From: Luke Kenneth Casson Leighton Date: Wed, 30 Sep 2020 17:15:15 +0000 (+0000) Subject: add full core ilang file X-Git-Tag: partial-core-ls180-gdsii~56 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=bee84b83b5962db5c12cf6434654783153b05024;p=soclayout.git add full core ilang file --- diff --git a/experiments9/non_generated/full_core_ls180.il b/experiments9/non_generated/full_core_ls180.il new file mode 100644 index 0000000..1ba1b0b --- /dev/null +++ b/experiments9/non_generated/full_core_ls180.il @@ -0,0 +1,392291 @@ +# Generated by Yosys 0.9+3578 (git sha1 c6ff947f, clang 9.0.1-12 -fPIC -Os) +autoidx 14178 +attribute \src "libresoc.v:5.1-330.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_ALU.dec.ALU_dec19" +attribute \generator "nMigen" +module \ALU_dec19 + attribute \src "libresoc.v:279.3-288.6" + wire width 3 $0\ALU_dec19_cr_in[2:0] + attribute \src "libresoc.v:289.3-298.6" + wire width 3 $0\ALU_dec19_cr_out[2:0] + attribute \src "libresoc.v:319.3-328.6" + wire width 2 $0\ALU_dec19_cry_in[1:0] + attribute \src "libresoc.v:219.3-228.6" + wire $0\ALU_dec19_cry_out[0:0] + attribute \src "libresoc.v:189.3-198.6" + wire width 12 $0\ALU_dec19_function_unit[11:0] + attribute \src "libresoc.v:259.3-268.6" + wire width 3 $0\ALU_dec19_in1_sel[2:0] + attribute \src "libresoc.v:269.3-278.6" + wire width 4 $0\ALU_dec19_in2_sel[3:0] + attribute \src "libresoc.v:249.3-258.6" + wire width 7 $0\ALU_dec19_internal_op[6:0] + attribute \src "libresoc.v:199.3-208.6" + wire $0\ALU_dec19_inv_a[0:0] + attribute \src "libresoc.v:209.3-218.6" + wire $0\ALU_dec19_inv_out[0:0] + attribute \src "libresoc.v:229.3-238.6" + wire $0\ALU_dec19_is_32b[0:0] + attribute \src "libresoc.v:299.3-308.6" + wire width 4 $0\ALU_dec19_ldst_len[3:0] + attribute \src "libresoc.v:309.3-318.6" + wire width 2 $0\ALU_dec19_rc_sel[1:0] + attribute \src "libresoc.v:239.3-248.6" + wire $0\ALU_dec19_sgn[0:0] + attribute \src "libresoc.v:6.7-6.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:279.3-288.6" + wire width 3 $1\ALU_dec19_cr_in[2:0] + attribute \src "libresoc.v:289.3-298.6" + wire width 3 $1\ALU_dec19_cr_out[2:0] + attribute \src "libresoc.v:319.3-328.6" + wire width 2 $1\ALU_dec19_cry_in[1:0] + attribute \src "libresoc.v:219.3-228.6" + wire $1\ALU_dec19_cry_out[0:0] + attribute \src "libresoc.v:189.3-198.6" + wire width 12 $1\ALU_dec19_function_unit[11:0] + attribute \src "libresoc.v:259.3-268.6" + wire width 3 $1\ALU_dec19_in1_sel[2:0] + attribute \src "libresoc.v:269.3-278.6" + wire width 4 $1\ALU_dec19_in2_sel[3:0] + attribute \src "libresoc.v:249.3-258.6" + wire width 7 $1\ALU_dec19_internal_op[6:0] + attribute \src "libresoc.v:199.3-208.6" + wire $1\ALU_dec19_inv_a[0:0] + attribute \src "libresoc.v:209.3-218.6" + wire $1\ALU_dec19_inv_out[0:0] + attribute \src "libresoc.v:229.3-238.6" + wire $1\ALU_dec19_is_32b[0:0] + attribute \src "libresoc.v:299.3-308.6" + wire width 4 $1\ALU_dec19_ldst_len[3:0] + attribute \src "libresoc.v:309.3-318.6" + wire width 2 $1\ALU_dec19_rc_sel[1:0] + attribute \src "libresoc.v:239.3-248.6" + wire $1\ALU_dec19_sgn[0:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \ALU_dec19_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 6 \ALU_dec19_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 9 \ALU_dec19_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 12 \ALU_dec19_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \ALU_dec19_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 3 \ALU_dec19_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 4 \ALU_dec19_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \ALU_dec19_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 10 \ALU_dec19_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 11 \ALU_dec19_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 13 \ALU_dec19_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 7 \ALU_dec19_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 8 \ALU_dec19_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 14 \ALU_dec19_sgn + attribute \src "libresoc.v:6.7-6.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 15 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 10 \opcode_switch + attribute \src "libresoc.v:189.3-198.6" + process $proc$libresoc.v:189$1 + assign { } { } + assign { } { } + assign $0\ALU_dec19_function_unit[11:0] $1\ALU_dec19_function_unit[11:0] + attribute \src "libresoc.v:190.5-190.29" + switch \initial + attribute \src "libresoc.v:190.9-190.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\ALU_dec19_function_unit[11:0] 12'000000000010 + case + assign $1\ALU_dec19_function_unit[11:0] 12'000000000000 + end + sync always + update \ALU_dec19_function_unit $0\ALU_dec19_function_unit[11:0] + end + attribute \src "libresoc.v:199.3-208.6" + process $proc$libresoc.v:199$2 + assign { } { } + assign { } { } + assign $0\ALU_dec19_inv_a[0:0] $1\ALU_dec19_inv_a[0:0] + attribute \src "libresoc.v:200.5-200.29" + switch \initial + attribute \src "libresoc.v:200.9-200.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\ALU_dec19_inv_a[0:0] 1'0 + case + assign $1\ALU_dec19_inv_a[0:0] 1'0 + end + sync always + update \ALU_dec19_inv_a $0\ALU_dec19_inv_a[0:0] + end + attribute \src "libresoc.v:209.3-218.6" + process $proc$libresoc.v:209$3 + assign { } { } + assign { } { } + assign $0\ALU_dec19_inv_out[0:0] $1\ALU_dec19_inv_out[0:0] + attribute \src "libresoc.v:210.5-210.29" + switch \initial + attribute \src "libresoc.v:210.9-210.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\ALU_dec19_inv_out[0:0] 1'0 + case + assign $1\ALU_dec19_inv_out[0:0] 1'0 + end + sync always + update \ALU_dec19_inv_out $0\ALU_dec19_inv_out[0:0] + end + attribute \src "libresoc.v:219.3-228.6" + process $proc$libresoc.v:219$4 + assign { } { } + assign { } { } + assign $0\ALU_dec19_cry_out[0:0] $1\ALU_dec19_cry_out[0:0] + attribute \src "libresoc.v:220.5-220.29" + switch \initial + attribute \src "libresoc.v:220.9-220.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\ALU_dec19_cry_out[0:0] 1'0 + case + assign $1\ALU_dec19_cry_out[0:0] 1'0 + end + sync always + update \ALU_dec19_cry_out $0\ALU_dec19_cry_out[0:0] + end + attribute \src "libresoc.v:229.3-238.6" + process $proc$libresoc.v:229$5 + assign { } { } + assign { } { } + assign $0\ALU_dec19_is_32b[0:0] $1\ALU_dec19_is_32b[0:0] + attribute \src "libresoc.v:230.5-230.29" + switch \initial + attribute \src "libresoc.v:230.9-230.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\ALU_dec19_is_32b[0:0] 1'0 + case + assign $1\ALU_dec19_is_32b[0:0] 1'0 + end + sync always + update \ALU_dec19_is_32b $0\ALU_dec19_is_32b[0:0] + end + attribute \src "libresoc.v:239.3-248.6" + process $proc$libresoc.v:239$6 + assign { } { } + assign { } { } + assign $0\ALU_dec19_sgn[0:0] $1\ALU_dec19_sgn[0:0] + attribute \src "libresoc.v:240.5-240.29" + switch \initial + attribute \src "libresoc.v:240.9-240.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\ALU_dec19_sgn[0:0] 1'0 + case + assign $1\ALU_dec19_sgn[0:0] 1'0 + end + sync always + update \ALU_dec19_sgn $0\ALU_dec19_sgn[0:0] + end + attribute \src "libresoc.v:249.3-258.6" + process $proc$libresoc.v:249$7 + assign { } { } + assign { } { } + assign $0\ALU_dec19_internal_op[6:0] $1\ALU_dec19_internal_op[6:0] + attribute \src "libresoc.v:250.5-250.29" + switch \initial + attribute \src "libresoc.v:250.9-250.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\ALU_dec19_internal_op[6:0] 7'0100100 + case + assign $1\ALU_dec19_internal_op[6:0] 7'0000000 + end + sync always + update \ALU_dec19_internal_op $0\ALU_dec19_internal_op[6:0] + end + attribute \src "libresoc.v:259.3-268.6" + process $proc$libresoc.v:259$8 + assign { } { } + assign { } { } + assign $0\ALU_dec19_in1_sel[2:0] $1\ALU_dec19_in1_sel[2:0] + attribute \src "libresoc.v:260.5-260.29" + switch \initial + attribute \src "libresoc.v:260.9-260.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\ALU_dec19_in1_sel[2:0] 3'000 + case + assign $1\ALU_dec19_in1_sel[2:0] 3'000 + end + sync always + update \ALU_dec19_in1_sel $0\ALU_dec19_in1_sel[2:0] + end + attribute \src "libresoc.v:269.3-278.6" + process $proc$libresoc.v:269$9 + assign { } { } + assign { } { } + assign $0\ALU_dec19_in2_sel[3:0] $1\ALU_dec19_in2_sel[3:0] + attribute \src "libresoc.v:270.5-270.29" + switch \initial + attribute \src "libresoc.v:270.9-270.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\ALU_dec19_in2_sel[3:0] 4'0000 + case + assign $1\ALU_dec19_in2_sel[3:0] 4'0000 + end + sync always + update \ALU_dec19_in2_sel $0\ALU_dec19_in2_sel[3:0] + end + attribute \src "libresoc.v:279.3-288.6" + process $proc$libresoc.v:279$10 + assign { } { } + assign { } { } + assign $0\ALU_dec19_cr_in[2:0] $1\ALU_dec19_cr_in[2:0] + attribute \src "libresoc.v:280.5-280.29" + switch \initial + attribute \src "libresoc.v:280.9-280.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\ALU_dec19_cr_in[2:0] 3'000 + case + assign $1\ALU_dec19_cr_in[2:0] 3'000 + end + sync always + update \ALU_dec19_cr_in $0\ALU_dec19_cr_in[2:0] + end + attribute \src "libresoc.v:289.3-298.6" + process $proc$libresoc.v:289$11 + assign { } { } + assign { } { } + assign $0\ALU_dec19_cr_out[2:0] $1\ALU_dec19_cr_out[2:0] + attribute \src "libresoc.v:290.5-290.29" + switch \initial + attribute \src "libresoc.v:290.9-290.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\ALU_dec19_cr_out[2:0] 3'000 + case + assign $1\ALU_dec19_cr_out[2:0] 3'000 + end + sync always + update \ALU_dec19_cr_out $0\ALU_dec19_cr_out[2:0] + end + attribute \src "libresoc.v:299.3-308.6" + process $proc$libresoc.v:299$12 + assign { } { } + assign { } { } + assign $0\ALU_dec19_ldst_len[3:0] $1\ALU_dec19_ldst_len[3:0] + attribute \src "libresoc.v:300.5-300.29" + switch \initial + attribute \src "libresoc.v:300.9-300.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\ALU_dec19_ldst_len[3:0] 4'0000 + case + assign $1\ALU_dec19_ldst_len[3:0] 4'0000 + end + sync always + update \ALU_dec19_ldst_len $0\ALU_dec19_ldst_len[3:0] + end + attribute \src "libresoc.v:309.3-318.6" + process $proc$libresoc.v:309$13 + assign { } { } + assign { } { } + assign $0\ALU_dec19_rc_sel[1:0] $1\ALU_dec19_rc_sel[1:0] + attribute \src "libresoc.v:310.5-310.29" + switch \initial + attribute \src "libresoc.v:310.9-310.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\ALU_dec19_rc_sel[1:0] 2'00 + case + assign $1\ALU_dec19_rc_sel[1:0] 2'00 + end + sync always + update \ALU_dec19_rc_sel $0\ALU_dec19_rc_sel[1:0] + end + attribute \src "libresoc.v:319.3-328.6" + process $proc$libresoc.v:319$14 + assign { } { } + assign { } { } + assign $0\ALU_dec19_cry_in[1:0] $1\ALU_dec19_cry_in[1:0] + attribute \src "libresoc.v:320.5-320.29" + switch \initial + attribute \src "libresoc.v:320.9-320.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\ALU_dec19_cry_in[1:0] 2'00 + case + assign $1\ALU_dec19_cry_in[1:0] 2'00 + end + sync always + update \ALU_dec19_cry_in $0\ALU_dec19_cry_in[1:0] + end + attribute \src "libresoc.v:6.7-6.20" + process $proc$libresoc.v:6$15 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + connect \opcode_switch \opcode_in [10:1] +end +attribute \src "libresoc.v:334.1-1750.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_ALU.dec.ALU_dec31" +attribute \generator "nMigen" +module \ALU_dec31 + attribute \src "libresoc.v:1457.3-1478.6" + wire width 3 $0\ALU_dec31_cr_in[2:0] + attribute \src "libresoc.v:1479.3-1500.6" + wire width 3 $0\ALU_dec31_cr_out[2:0] + attribute \src "libresoc.v:1545.3-1566.6" + wire width 2 $0\ALU_dec31_cry_in[1:0] + attribute \src "libresoc.v:1611.3-1632.6" + wire $0\ALU_dec31_cry_out[0:0] + attribute \src "libresoc.v:1677.3-1698.6" + wire width 12 $0\ALU_dec31_function_unit[11:0] + attribute \src "libresoc.v:1721.3-1742.6" + wire width 3 $0\ALU_dec31_in1_sel[2:0] + attribute \src "libresoc.v:1435.3-1456.6" + wire width 4 $0\ALU_dec31_in2_sel[3:0] + attribute \src "libresoc.v:1699.3-1720.6" + wire width 7 $0\ALU_dec31_internal_op[6:0] + attribute \src "libresoc.v:1567.3-1588.6" + wire $0\ALU_dec31_inv_a[0:0] + attribute \src "libresoc.v:1589.3-1610.6" + wire $0\ALU_dec31_inv_out[0:0] + attribute \src "libresoc.v:1633.3-1654.6" + wire $0\ALU_dec31_is_32b[0:0] + attribute \src "libresoc.v:1501.3-1522.6" + wire width 4 $0\ALU_dec31_ldst_len[3:0] + attribute \src "libresoc.v:1523.3-1544.6" + wire width 2 $0\ALU_dec31_rc_sel[1:0] + attribute \src "libresoc.v:1655.3-1676.6" + wire $0\ALU_dec31_sgn[0:0] + attribute \src "libresoc.v:335.7-335.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:1457.3-1478.6" + wire width 3 $1\ALU_dec31_cr_in[2:0] + attribute \src "libresoc.v:1479.3-1500.6" + wire width 3 $1\ALU_dec31_cr_out[2:0] + attribute \src "libresoc.v:1545.3-1566.6" + wire width 2 $1\ALU_dec31_cry_in[1:0] + attribute \src "libresoc.v:1611.3-1632.6" + wire $1\ALU_dec31_cry_out[0:0] + attribute \src "libresoc.v:1677.3-1698.6" + wire width 12 $1\ALU_dec31_function_unit[11:0] + attribute \src "libresoc.v:1721.3-1742.6" + wire width 3 $1\ALU_dec31_in1_sel[2:0] + attribute \src "libresoc.v:1435.3-1456.6" + wire width 4 $1\ALU_dec31_in2_sel[3:0] + attribute \src "libresoc.v:1699.3-1720.6" + wire width 7 $1\ALU_dec31_internal_op[6:0] + attribute \src "libresoc.v:1567.3-1588.6" + wire $1\ALU_dec31_inv_a[0:0] + attribute \src "libresoc.v:1589.3-1610.6" + wire $1\ALU_dec31_inv_out[0:0] + attribute \src "libresoc.v:1633.3-1654.6" + wire $1\ALU_dec31_is_32b[0:0] + attribute \src "libresoc.v:1501.3-1522.6" + wire width 4 $1\ALU_dec31_ldst_len[3:0] + attribute \src "libresoc.v:1523.3-1544.6" + wire width 2 $1\ALU_dec31_rc_sel[1:0] + attribute \src "libresoc.v:1655.3-1676.6" + wire $1\ALU_dec31_sgn[0:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \ALU_dec31_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 6 \ALU_dec31_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 9 \ALU_dec31_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 12 \ALU_dec31_cry_out + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \ALU_dec31_dec_sub0_opcode_in + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \ALU_dec31_dec_sub10_opcode_in + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \ALU_dec31_dec_sub22_opcode_in + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \ALU_dec31_dec_sub26_opcode_in + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \ALU_dec31_dec_sub8_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \ALU_dec31_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 3 \ALU_dec31_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 4 \ALU_dec31_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \ALU_dec31_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 10 \ALU_dec31_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 11 \ALU_dec31_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 13 \ALU_dec31_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 7 \ALU_dec31_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 8 \ALU_dec31_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 14 \ALU_dec31_sgn + attribute \src "libresoc.v:335.7-335.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:326" + wire width 5 \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 15 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 10 \opcode_switch + attribute \module_not_derived 1 + attribute \src "libresoc.v:1350.22-1366.4" + cell \ALU_dec31_dec_sub0 \ALU_dec31_dec_sub0 + connect \ALU_dec31_dec_sub0_cr_in \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cr_in + connect \ALU_dec31_dec_sub0_cr_out \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cr_out + connect \ALU_dec31_dec_sub0_cry_in \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cry_in + connect \ALU_dec31_dec_sub0_cry_out \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cry_out + connect \ALU_dec31_dec_sub0_function_unit \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_function_unit + connect \ALU_dec31_dec_sub0_in1_sel \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_in1_sel + connect \ALU_dec31_dec_sub0_in2_sel \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_in2_sel + connect \ALU_dec31_dec_sub0_internal_op \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_internal_op + connect \ALU_dec31_dec_sub0_inv_a \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_inv_a + connect \ALU_dec31_dec_sub0_inv_out \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_inv_out + connect \ALU_dec31_dec_sub0_is_32b \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_is_32b + connect \ALU_dec31_dec_sub0_ldst_len \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_ldst_len + connect \ALU_dec31_dec_sub0_rc_sel \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_rc_sel + connect \ALU_dec31_dec_sub0_sgn \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_sgn + connect \opcode_in \ALU_dec31_dec_sub0_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:1367.23-1383.4" + cell \ALU_dec31_dec_sub10 \ALU_dec31_dec_sub10 + connect \ALU_dec31_dec_sub10_cr_in \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cr_in + connect \ALU_dec31_dec_sub10_cr_out \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cr_out + connect \ALU_dec31_dec_sub10_cry_in \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cry_in + connect \ALU_dec31_dec_sub10_cry_out \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cry_out + connect \ALU_dec31_dec_sub10_function_unit \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_function_unit + connect \ALU_dec31_dec_sub10_in1_sel \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_in1_sel + connect \ALU_dec31_dec_sub10_in2_sel \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_in2_sel + connect \ALU_dec31_dec_sub10_internal_op \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_internal_op + connect \ALU_dec31_dec_sub10_inv_a \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_inv_a + connect \ALU_dec31_dec_sub10_inv_out \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_inv_out + connect \ALU_dec31_dec_sub10_is_32b \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_is_32b + connect \ALU_dec31_dec_sub10_ldst_len \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_ldst_len + connect \ALU_dec31_dec_sub10_rc_sel \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_rc_sel + connect \ALU_dec31_dec_sub10_sgn \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_sgn + connect \opcode_in \ALU_dec31_dec_sub10_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:1384.23-1400.4" + cell \ALU_dec31_dec_sub22 \ALU_dec31_dec_sub22 + connect \ALU_dec31_dec_sub22_cr_in \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_cr_in + connect \ALU_dec31_dec_sub22_cr_out \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_cr_out + connect \ALU_dec31_dec_sub22_cry_in \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_cry_in + connect \ALU_dec31_dec_sub22_cry_out \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_cry_out + connect \ALU_dec31_dec_sub22_function_unit \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_function_unit + connect \ALU_dec31_dec_sub22_in1_sel \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_in1_sel + connect \ALU_dec31_dec_sub22_in2_sel \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_in2_sel + connect \ALU_dec31_dec_sub22_internal_op \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_internal_op + connect \ALU_dec31_dec_sub22_inv_a \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_inv_a + connect \ALU_dec31_dec_sub22_inv_out \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_inv_out + connect \ALU_dec31_dec_sub22_is_32b \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_is_32b + connect \ALU_dec31_dec_sub22_ldst_len \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_ldst_len + connect \ALU_dec31_dec_sub22_rc_sel \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_rc_sel + connect \ALU_dec31_dec_sub22_sgn \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_sgn + connect \opcode_in \ALU_dec31_dec_sub22_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:1401.23-1417.4" + cell \ALU_dec31_dec_sub26 \ALU_dec31_dec_sub26 + connect \ALU_dec31_dec_sub26_cr_in \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_cr_in + connect \ALU_dec31_dec_sub26_cr_out \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_cr_out + connect \ALU_dec31_dec_sub26_cry_in \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_cry_in + connect \ALU_dec31_dec_sub26_cry_out \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_cry_out + connect \ALU_dec31_dec_sub26_function_unit \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_function_unit + connect \ALU_dec31_dec_sub26_in1_sel \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_in1_sel + connect \ALU_dec31_dec_sub26_in2_sel \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_in2_sel + connect \ALU_dec31_dec_sub26_internal_op \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_internal_op + connect \ALU_dec31_dec_sub26_inv_a \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_inv_a + connect \ALU_dec31_dec_sub26_inv_out \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_inv_out + connect \ALU_dec31_dec_sub26_is_32b \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_is_32b + connect \ALU_dec31_dec_sub26_ldst_len \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_ldst_len + connect \ALU_dec31_dec_sub26_rc_sel \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_rc_sel + connect \ALU_dec31_dec_sub26_sgn \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_sgn + connect \opcode_in \ALU_dec31_dec_sub26_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:1418.22-1434.4" + cell \ALU_dec31_dec_sub8 \ALU_dec31_dec_sub8 + connect \ALU_dec31_dec_sub8_cr_in \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cr_in + connect \ALU_dec31_dec_sub8_cr_out \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cr_out + connect \ALU_dec31_dec_sub8_cry_in \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cry_in + connect \ALU_dec31_dec_sub8_cry_out \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cry_out + connect \ALU_dec31_dec_sub8_function_unit \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_function_unit + connect \ALU_dec31_dec_sub8_in1_sel \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_in1_sel + connect \ALU_dec31_dec_sub8_in2_sel \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_in2_sel + connect \ALU_dec31_dec_sub8_internal_op \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_internal_op + connect \ALU_dec31_dec_sub8_inv_a \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_inv_a + connect \ALU_dec31_dec_sub8_inv_out \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_inv_out + connect \ALU_dec31_dec_sub8_is_32b \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_is_32b + connect \ALU_dec31_dec_sub8_ldst_len \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_ldst_len + connect \ALU_dec31_dec_sub8_rc_sel \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_rc_sel + connect \ALU_dec31_dec_sub8_sgn \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_sgn + connect \opcode_in \ALU_dec31_dec_sub8_opcode_in + end + attribute \src "libresoc.v:1435.3-1456.6" + process $proc$libresoc.v:1435$16 + assign { } { } + assign { } { } + assign $0\ALU_dec31_in2_sel[3:0] $1\ALU_dec31_in2_sel[3:0] + attribute \src "libresoc.v:1436.5-1436.29" + switch \initial + attribute \src "libresoc.v:1436.9-1436.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\ALU_dec31_in2_sel[3:0] \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_in2_sel[3:0] \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\ALU_dec31_in2_sel[3:0] \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_in2_sel[3:0] \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_in2_sel[3:0] \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_in2_sel + case + assign $1\ALU_dec31_in2_sel[3:0] 4'0000 + end + sync always + update \ALU_dec31_in2_sel $0\ALU_dec31_in2_sel[3:0] + end + attribute \src "libresoc.v:1457.3-1478.6" + process $proc$libresoc.v:1457$17 + assign { } { } + assign { } { } + assign $0\ALU_dec31_cr_in[2:0] $1\ALU_dec31_cr_in[2:0] + attribute \src "libresoc.v:1458.5-1458.29" + switch \initial + attribute \src "libresoc.v:1458.9-1458.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\ALU_dec31_cr_in[2:0] \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_cr_in[2:0] \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\ALU_dec31_cr_in[2:0] \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_cr_in[2:0] \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_cr_in[2:0] \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cr_in + case + assign $1\ALU_dec31_cr_in[2:0] 3'000 + end + sync always + update \ALU_dec31_cr_in $0\ALU_dec31_cr_in[2:0] + end + attribute \src "libresoc.v:1479.3-1500.6" + process $proc$libresoc.v:1479$18 + assign { } { } + assign { } { } + assign $0\ALU_dec31_cr_out[2:0] $1\ALU_dec31_cr_out[2:0] + attribute \src "libresoc.v:1480.5-1480.29" + switch \initial + attribute \src "libresoc.v:1480.9-1480.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\ALU_dec31_cr_out[2:0] \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_cr_out[2:0] \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\ALU_dec31_cr_out[2:0] \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_cr_out[2:0] \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_cr_out[2:0] \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cr_out + case + assign $1\ALU_dec31_cr_out[2:0] 3'000 + end + sync always + update \ALU_dec31_cr_out $0\ALU_dec31_cr_out[2:0] + end + attribute \src "libresoc.v:1501.3-1522.6" + process $proc$libresoc.v:1501$19 + assign { } { } + assign { } { } + assign $0\ALU_dec31_ldst_len[3:0] $1\ALU_dec31_ldst_len[3:0] + attribute \src "libresoc.v:1502.5-1502.29" + switch \initial + attribute \src "libresoc.v:1502.9-1502.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\ALU_dec31_ldst_len[3:0] \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_ldst_len[3:0] \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\ALU_dec31_ldst_len[3:0] \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_ldst_len[3:0] \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_ldst_len[3:0] \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_ldst_len + case + assign $1\ALU_dec31_ldst_len[3:0] 4'0000 + end + sync always + update \ALU_dec31_ldst_len $0\ALU_dec31_ldst_len[3:0] + end + attribute \src "libresoc.v:1523.3-1544.6" + process $proc$libresoc.v:1523$20 + assign { } { } + assign { } { } + assign $0\ALU_dec31_rc_sel[1:0] $1\ALU_dec31_rc_sel[1:0] + attribute \src "libresoc.v:1524.5-1524.29" + switch \initial + attribute \src "libresoc.v:1524.9-1524.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\ALU_dec31_rc_sel[1:0] \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_rc_sel[1:0] \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\ALU_dec31_rc_sel[1:0] \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_rc_sel[1:0] \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_rc_sel[1:0] \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_rc_sel + case + assign $1\ALU_dec31_rc_sel[1:0] 2'00 + end + sync always + update \ALU_dec31_rc_sel $0\ALU_dec31_rc_sel[1:0] + end + attribute \src "libresoc.v:1545.3-1566.6" + process $proc$libresoc.v:1545$21 + assign { } { } + assign { } { } + assign $0\ALU_dec31_cry_in[1:0] $1\ALU_dec31_cry_in[1:0] + attribute \src "libresoc.v:1546.5-1546.29" + switch \initial + attribute \src "libresoc.v:1546.9-1546.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\ALU_dec31_cry_in[1:0] \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_cry_in[1:0] \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\ALU_dec31_cry_in[1:0] \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_cry_in[1:0] \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_cry_in[1:0] \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cry_in + case + assign $1\ALU_dec31_cry_in[1:0] 2'00 + end + sync always + update \ALU_dec31_cry_in $0\ALU_dec31_cry_in[1:0] + end + attribute \src "libresoc.v:1567.3-1588.6" + process $proc$libresoc.v:1567$22 + assign { } { } + assign { } { } + assign $0\ALU_dec31_inv_a[0:0] $1\ALU_dec31_inv_a[0:0] + attribute \src "libresoc.v:1568.5-1568.29" + switch \initial + attribute \src "libresoc.v:1568.9-1568.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\ALU_dec31_inv_a[0:0] \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_inv_a[0:0] \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\ALU_dec31_inv_a[0:0] \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_inv_a[0:0] \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_inv_a[0:0] \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_inv_a + case + assign $1\ALU_dec31_inv_a[0:0] 1'0 + end + sync always + update \ALU_dec31_inv_a $0\ALU_dec31_inv_a[0:0] + end + attribute \src "libresoc.v:1589.3-1610.6" + process $proc$libresoc.v:1589$23 + assign { } { } + assign { } { } + assign $0\ALU_dec31_inv_out[0:0] $1\ALU_dec31_inv_out[0:0] + attribute \src "libresoc.v:1590.5-1590.29" + switch \initial + attribute \src "libresoc.v:1590.9-1590.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\ALU_dec31_inv_out[0:0] \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_inv_out[0:0] \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\ALU_dec31_inv_out[0:0] \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_inv_out[0:0] \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_inv_out[0:0] \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_inv_out + case + assign $1\ALU_dec31_inv_out[0:0] 1'0 + end + sync always + update \ALU_dec31_inv_out $0\ALU_dec31_inv_out[0:0] + end + attribute \src "libresoc.v:1611.3-1632.6" + process $proc$libresoc.v:1611$24 + assign { } { } + assign { } { } + assign $0\ALU_dec31_cry_out[0:0] $1\ALU_dec31_cry_out[0:0] + attribute \src "libresoc.v:1612.5-1612.29" + switch \initial + attribute \src "libresoc.v:1612.9-1612.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\ALU_dec31_cry_out[0:0] \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_cry_out[0:0] \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\ALU_dec31_cry_out[0:0] \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_cry_out[0:0] \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_cry_out[0:0] \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cry_out + case + assign $1\ALU_dec31_cry_out[0:0] 1'0 + end + sync always + update \ALU_dec31_cry_out $0\ALU_dec31_cry_out[0:0] + end + attribute \src "libresoc.v:1633.3-1654.6" + process $proc$libresoc.v:1633$25 + assign { } { } + assign { } { } + assign $0\ALU_dec31_is_32b[0:0] $1\ALU_dec31_is_32b[0:0] + attribute \src "libresoc.v:1634.5-1634.29" + switch \initial + attribute \src "libresoc.v:1634.9-1634.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\ALU_dec31_is_32b[0:0] \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_is_32b[0:0] \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\ALU_dec31_is_32b[0:0] \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_is_32b[0:0] \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_is_32b[0:0] \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_is_32b + case + assign $1\ALU_dec31_is_32b[0:0] 1'0 + end + sync always + update \ALU_dec31_is_32b $0\ALU_dec31_is_32b[0:0] + end + attribute \src "libresoc.v:1655.3-1676.6" + process $proc$libresoc.v:1655$26 + assign { } { } + assign { } { } + assign $0\ALU_dec31_sgn[0:0] $1\ALU_dec31_sgn[0:0] + attribute \src "libresoc.v:1656.5-1656.29" + switch \initial + attribute \src "libresoc.v:1656.9-1656.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\ALU_dec31_sgn[0:0] \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_sgn[0:0] \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\ALU_dec31_sgn[0:0] \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_sgn[0:0] \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_sgn[0:0] \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_sgn + case + assign $1\ALU_dec31_sgn[0:0] 1'0 + end + sync always + update \ALU_dec31_sgn $0\ALU_dec31_sgn[0:0] + end + attribute \src "libresoc.v:1677.3-1698.6" + process $proc$libresoc.v:1677$27 + assign { } { } + assign { } { } + assign $0\ALU_dec31_function_unit[11:0] $1\ALU_dec31_function_unit[11:0] + attribute \src "libresoc.v:1678.5-1678.29" + switch \initial + attribute \src "libresoc.v:1678.9-1678.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\ALU_dec31_function_unit[11:0] \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_function_unit[11:0] \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\ALU_dec31_function_unit[11:0] \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_function_unit[11:0] \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_function_unit[11:0] \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_function_unit + case + assign $1\ALU_dec31_function_unit[11:0] 12'000000000000 + end + sync always + update \ALU_dec31_function_unit $0\ALU_dec31_function_unit[11:0] + end + attribute \src "libresoc.v:1699.3-1720.6" + process $proc$libresoc.v:1699$28 + assign { } { } + assign { } { } + assign $0\ALU_dec31_internal_op[6:0] $1\ALU_dec31_internal_op[6:0] + attribute \src "libresoc.v:1700.5-1700.29" + switch \initial + attribute \src "libresoc.v:1700.9-1700.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\ALU_dec31_internal_op[6:0] \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_internal_op[6:0] \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\ALU_dec31_internal_op[6:0] \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_internal_op[6:0] \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_internal_op[6:0] \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_internal_op + case + assign $1\ALU_dec31_internal_op[6:0] 7'0000000 + end + sync always + update \ALU_dec31_internal_op $0\ALU_dec31_internal_op[6:0] + end + attribute \src "libresoc.v:1721.3-1742.6" + process $proc$libresoc.v:1721$29 + assign { } { } + assign { } { } + assign $0\ALU_dec31_in1_sel[2:0] $1\ALU_dec31_in1_sel[2:0] + attribute \src "libresoc.v:1722.5-1722.29" + switch \initial + attribute \src "libresoc.v:1722.9-1722.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\ALU_dec31_in1_sel[2:0] \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_in1_sel[2:0] \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\ALU_dec31_in1_sel[2:0] \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_in1_sel[2:0] \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_in1_sel[2:0] \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_in1_sel + case + assign $1\ALU_dec31_in1_sel[2:0] 3'000 + end + sync always + update \ALU_dec31_in1_sel $0\ALU_dec31_in1_sel[2:0] + end + attribute \src "libresoc.v:335.7-335.20" + process $proc$libresoc.v:335$30 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + connect \ALU_dec31_dec_sub8_opcode_in \opcode_in + connect \ALU_dec31_dec_sub22_opcode_in \opcode_in + connect \ALU_dec31_dec_sub26_opcode_in \opcode_in + connect \ALU_dec31_dec_sub0_opcode_in \opcode_in + connect \ALU_dec31_dec_sub10_opcode_in \opcode_in + connect \opc_in \opcode_switch [4:0] + connect \opcode_switch \opcode_in [10:1] +end +attribute \src "libresoc.v:1754.1-2163.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_ALU.dec.ALU_dec31.ALU_dec31_dec_sub0" +attribute \generator "nMigen" +module \ALU_dec31_dec_sub0 + attribute \src "libresoc.v:2082.3-2097.6" + wire width 3 $0\ALU_dec31_dec_sub0_cr_in[2:0] + attribute \src "libresoc.v:2098.3-2113.6" + wire width 3 $0\ALU_dec31_dec_sub0_cr_out[2:0] + attribute \src "libresoc.v:2146.3-2161.6" + wire width 2 $0\ALU_dec31_dec_sub0_cry_in[1:0] + attribute \src "libresoc.v:1986.3-2001.6" + wire $0\ALU_dec31_dec_sub0_cry_out[0:0] + attribute \src "libresoc.v:1938.3-1953.6" + wire width 12 $0\ALU_dec31_dec_sub0_function_unit[11:0] + attribute \src "libresoc.v:2050.3-2065.6" + wire width 3 $0\ALU_dec31_dec_sub0_in1_sel[2:0] + attribute \src "libresoc.v:2066.3-2081.6" + wire width 4 $0\ALU_dec31_dec_sub0_in2_sel[3:0] + attribute \src "libresoc.v:2034.3-2049.6" + wire width 7 $0\ALU_dec31_dec_sub0_internal_op[6:0] + attribute \src "libresoc.v:1954.3-1969.6" + wire $0\ALU_dec31_dec_sub0_inv_a[0:0] + attribute \src "libresoc.v:1970.3-1985.6" + wire $0\ALU_dec31_dec_sub0_inv_out[0:0] + attribute \src "libresoc.v:2002.3-2017.6" + wire $0\ALU_dec31_dec_sub0_is_32b[0:0] + attribute \src "libresoc.v:2114.3-2129.6" + wire width 4 $0\ALU_dec31_dec_sub0_ldst_len[3:0] + attribute \src "libresoc.v:2130.3-2145.6" + wire width 2 $0\ALU_dec31_dec_sub0_rc_sel[1:0] + attribute \src "libresoc.v:2018.3-2033.6" + wire $0\ALU_dec31_dec_sub0_sgn[0:0] + attribute \src "libresoc.v:1755.7-1755.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:2082.3-2097.6" + wire width 3 $1\ALU_dec31_dec_sub0_cr_in[2:0] + attribute \src "libresoc.v:2098.3-2113.6" + wire width 3 $1\ALU_dec31_dec_sub0_cr_out[2:0] + attribute \src "libresoc.v:2146.3-2161.6" + wire width 2 $1\ALU_dec31_dec_sub0_cry_in[1:0] + attribute \src "libresoc.v:1986.3-2001.6" + wire $1\ALU_dec31_dec_sub0_cry_out[0:0] + attribute \src "libresoc.v:1938.3-1953.6" + wire width 12 $1\ALU_dec31_dec_sub0_function_unit[11:0] + attribute \src "libresoc.v:2050.3-2065.6" + wire width 3 $1\ALU_dec31_dec_sub0_in1_sel[2:0] + attribute \src "libresoc.v:2066.3-2081.6" + wire width 4 $1\ALU_dec31_dec_sub0_in2_sel[3:0] + attribute \src "libresoc.v:2034.3-2049.6" + wire width 7 $1\ALU_dec31_dec_sub0_internal_op[6:0] + attribute \src "libresoc.v:1954.3-1969.6" + wire $1\ALU_dec31_dec_sub0_inv_a[0:0] + attribute \src "libresoc.v:1970.3-1985.6" + wire $1\ALU_dec31_dec_sub0_inv_out[0:0] + attribute \src "libresoc.v:2002.3-2017.6" + wire $1\ALU_dec31_dec_sub0_is_32b[0:0] + attribute \src "libresoc.v:2114.3-2129.6" + wire width 4 $1\ALU_dec31_dec_sub0_ldst_len[3:0] + attribute \src "libresoc.v:2130.3-2145.6" + wire width 2 $1\ALU_dec31_dec_sub0_rc_sel[1:0] + attribute \src "libresoc.v:2018.3-2033.6" + wire $1\ALU_dec31_dec_sub0_sgn[0:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \ALU_dec31_dec_sub0_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 6 \ALU_dec31_dec_sub0_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 9 \ALU_dec31_dec_sub0_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 12 \ALU_dec31_dec_sub0_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \ALU_dec31_dec_sub0_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 3 \ALU_dec31_dec_sub0_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 4 \ALU_dec31_dec_sub0_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \ALU_dec31_dec_sub0_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 10 \ALU_dec31_dec_sub0_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 11 \ALU_dec31_dec_sub0_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 13 \ALU_dec31_dec_sub0_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 7 \ALU_dec31_dec_sub0_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 8 \ALU_dec31_dec_sub0_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 14 \ALU_dec31_dec_sub0_sgn + attribute \src "libresoc.v:1755.7-1755.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 15 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 5 \opcode_switch + attribute \src "libresoc.v:1755.7-1755.20" + process $proc$libresoc.v:1755$45 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:1938.3-1953.6" + process $proc$libresoc.v:1938$31 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub0_function_unit[11:0] $1\ALU_dec31_dec_sub0_function_unit[11:0] + attribute \src "libresoc.v:1939.5-1939.29" + switch \initial + attribute \src "libresoc.v:1939.9-1939.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub0_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub0_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub0_function_unit[11:0] 12'000000000010 + case + assign $1\ALU_dec31_dec_sub0_function_unit[11:0] 12'000000000000 + end + sync always + update \ALU_dec31_dec_sub0_function_unit $0\ALU_dec31_dec_sub0_function_unit[11:0] + end + attribute \src "libresoc.v:1954.3-1969.6" + process $proc$libresoc.v:1954$32 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub0_inv_a[0:0] $1\ALU_dec31_dec_sub0_inv_a[0:0] + attribute \src "libresoc.v:1955.5-1955.29" + switch \initial + attribute \src "libresoc.v:1955.9-1955.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub0_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub0_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub0_inv_a[0:0] 1'1 + case + assign $1\ALU_dec31_dec_sub0_inv_a[0:0] 1'0 + end + sync always + update \ALU_dec31_dec_sub0_inv_a $0\ALU_dec31_dec_sub0_inv_a[0:0] + end + attribute \src "libresoc.v:1970.3-1985.6" + process $proc$libresoc.v:1970$33 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub0_inv_out[0:0] $1\ALU_dec31_dec_sub0_inv_out[0:0] + attribute \src "libresoc.v:1971.5-1971.29" + switch \initial + attribute \src "libresoc.v:1971.9-1971.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub0_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub0_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub0_inv_out[0:0] 1'0 + case + assign $1\ALU_dec31_dec_sub0_inv_out[0:0] 1'0 + end + sync always + update \ALU_dec31_dec_sub0_inv_out $0\ALU_dec31_dec_sub0_inv_out[0:0] + end + attribute \src "libresoc.v:1986.3-2001.6" + process $proc$libresoc.v:1986$34 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub0_cry_out[0:0] $1\ALU_dec31_dec_sub0_cry_out[0:0] + attribute \src "libresoc.v:1987.5-1987.29" + switch \initial + attribute \src "libresoc.v:1987.9-1987.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub0_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub0_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub0_cry_out[0:0] 1'0 + case + assign $1\ALU_dec31_dec_sub0_cry_out[0:0] 1'0 + end + sync always + update \ALU_dec31_dec_sub0_cry_out $0\ALU_dec31_dec_sub0_cry_out[0:0] + end + attribute \src "libresoc.v:2002.3-2017.6" + process $proc$libresoc.v:2002$35 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub0_is_32b[0:0] $1\ALU_dec31_dec_sub0_is_32b[0:0] + attribute \src "libresoc.v:2003.5-2003.29" + switch \initial + attribute \src "libresoc.v:2003.9-2003.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub0_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub0_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub0_is_32b[0:0] 1'0 + case + assign $1\ALU_dec31_dec_sub0_is_32b[0:0] 1'0 + end + sync always + update \ALU_dec31_dec_sub0_is_32b $0\ALU_dec31_dec_sub0_is_32b[0:0] + end + attribute \src "libresoc.v:2018.3-2033.6" + process $proc$libresoc.v:2018$36 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub0_sgn[0:0] $1\ALU_dec31_dec_sub0_sgn[0:0] + attribute \src "libresoc.v:2019.5-2019.29" + switch \initial + attribute \src "libresoc.v:2019.9-2019.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub0_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub0_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub0_sgn[0:0] 1'0 + case + assign $1\ALU_dec31_dec_sub0_sgn[0:0] 1'0 + end + sync always + update \ALU_dec31_dec_sub0_sgn $0\ALU_dec31_dec_sub0_sgn[0:0] + end + attribute \src "libresoc.v:2034.3-2049.6" + process $proc$libresoc.v:2034$37 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub0_internal_op[6:0] $1\ALU_dec31_dec_sub0_internal_op[6:0] + attribute \src "libresoc.v:2035.5-2035.29" + switch \initial + attribute \src "libresoc.v:2035.9-2035.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub0_internal_op[6:0] 7'0001010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub0_internal_op[6:0] 7'0001100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub0_internal_op[6:0] 7'0001010 + case + assign $1\ALU_dec31_dec_sub0_internal_op[6:0] 7'0000000 + end + sync always + update \ALU_dec31_dec_sub0_internal_op $0\ALU_dec31_dec_sub0_internal_op[6:0] + end + attribute \src "libresoc.v:2050.3-2065.6" + process $proc$libresoc.v:2050$38 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub0_in1_sel[2:0] $1\ALU_dec31_dec_sub0_in1_sel[2:0] + attribute \src "libresoc.v:2051.5-2051.29" + switch \initial + attribute \src "libresoc.v:2051.9-2051.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub0_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub0_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub0_in1_sel[2:0] 3'001 + case + assign $1\ALU_dec31_dec_sub0_in1_sel[2:0] 3'000 + end + sync always + update \ALU_dec31_dec_sub0_in1_sel $0\ALU_dec31_dec_sub0_in1_sel[2:0] + end + attribute \src "libresoc.v:2066.3-2081.6" + process $proc$libresoc.v:2066$39 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub0_in2_sel[3:0] $1\ALU_dec31_dec_sub0_in2_sel[3:0] + attribute \src "libresoc.v:2067.5-2067.29" + switch \initial + attribute \src "libresoc.v:2067.9-2067.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub0_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub0_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub0_in2_sel[3:0] 4'0001 + case + assign $1\ALU_dec31_dec_sub0_in2_sel[3:0] 4'0000 + end + sync always + update \ALU_dec31_dec_sub0_in2_sel $0\ALU_dec31_dec_sub0_in2_sel[3:0] + end + attribute \src "libresoc.v:2082.3-2097.6" + process $proc$libresoc.v:2082$40 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub0_cr_in[2:0] $1\ALU_dec31_dec_sub0_cr_in[2:0] + attribute \src "libresoc.v:2083.5-2083.29" + switch \initial + attribute \src "libresoc.v:2083.9-2083.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub0_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub0_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub0_cr_in[2:0] 3'000 + case + assign $1\ALU_dec31_dec_sub0_cr_in[2:0] 3'000 + end + sync always + update \ALU_dec31_dec_sub0_cr_in $0\ALU_dec31_dec_sub0_cr_in[2:0] + end + attribute \src "libresoc.v:2098.3-2113.6" + process $proc$libresoc.v:2098$41 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub0_cr_out[2:0] $1\ALU_dec31_dec_sub0_cr_out[2:0] + attribute \src "libresoc.v:2099.5-2099.29" + switch \initial + attribute \src "libresoc.v:2099.9-2099.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub0_cr_out[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub0_cr_out[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub0_cr_out[2:0] 3'010 + case + assign $1\ALU_dec31_dec_sub0_cr_out[2:0] 3'000 + end + sync always + update \ALU_dec31_dec_sub0_cr_out $0\ALU_dec31_dec_sub0_cr_out[2:0] + end + attribute \src "libresoc.v:2114.3-2129.6" + process $proc$libresoc.v:2114$42 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub0_ldst_len[3:0] $1\ALU_dec31_dec_sub0_ldst_len[3:0] + attribute \src "libresoc.v:2115.5-2115.29" + switch \initial + attribute \src "libresoc.v:2115.9-2115.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub0_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub0_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub0_ldst_len[3:0] 4'0000 + case + assign $1\ALU_dec31_dec_sub0_ldst_len[3:0] 4'0000 + end + sync always + update \ALU_dec31_dec_sub0_ldst_len $0\ALU_dec31_dec_sub0_ldst_len[3:0] + end + attribute \src "libresoc.v:2130.3-2145.6" + process $proc$libresoc.v:2130$43 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub0_rc_sel[1:0] $1\ALU_dec31_dec_sub0_rc_sel[1:0] + attribute \src "libresoc.v:2131.5-2131.29" + switch \initial + attribute \src "libresoc.v:2131.9-2131.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub0_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub0_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub0_rc_sel[1:0] 2'00 + case + assign $1\ALU_dec31_dec_sub0_rc_sel[1:0] 2'00 + end + sync always + update \ALU_dec31_dec_sub0_rc_sel $0\ALU_dec31_dec_sub0_rc_sel[1:0] + end + attribute \src "libresoc.v:2146.3-2161.6" + process $proc$libresoc.v:2146$44 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub0_cry_in[1:0] $1\ALU_dec31_dec_sub0_cry_in[1:0] + attribute \src "libresoc.v:2147.5-2147.29" + switch \initial + attribute \src "libresoc.v:2147.9-2147.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub0_cry_in[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub0_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub0_cry_in[1:0] 2'01 + case + assign $1\ALU_dec31_dec_sub0_cry_in[1:0] 2'00 + end + sync always + update \ALU_dec31_dec_sub0_cry_in $0\ALU_dec31_dec_sub0_cry_in[1:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:2167.1-2870.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_ALU.dec.ALU_dec31.ALU_dec31_dec_sub10" +attribute \generator "nMigen" +module \ALU_dec31_dec_sub10 + attribute \src "libresoc.v:2684.3-2720.6" + wire width 3 $0\ALU_dec31_dec_sub10_cr_in[2:0] + attribute \src "libresoc.v:2721.3-2757.6" + wire width 3 $0\ALU_dec31_dec_sub10_cr_out[2:0] + attribute \src "libresoc.v:2832.3-2868.6" + wire width 2 $0\ALU_dec31_dec_sub10_cry_in[1:0] + attribute \src "libresoc.v:2462.3-2498.6" + wire $0\ALU_dec31_dec_sub10_cry_out[0:0] + attribute \src "libresoc.v:2351.3-2387.6" + wire width 12 $0\ALU_dec31_dec_sub10_function_unit[11:0] + attribute \src "libresoc.v:2610.3-2646.6" + wire width 3 $0\ALU_dec31_dec_sub10_in1_sel[2:0] + attribute \src "libresoc.v:2647.3-2683.6" + wire width 4 $0\ALU_dec31_dec_sub10_in2_sel[3:0] + attribute \src "libresoc.v:2573.3-2609.6" + wire width 7 $0\ALU_dec31_dec_sub10_internal_op[6:0] + attribute \src "libresoc.v:2388.3-2424.6" + wire $0\ALU_dec31_dec_sub10_inv_a[0:0] + attribute \src "libresoc.v:2425.3-2461.6" + wire $0\ALU_dec31_dec_sub10_inv_out[0:0] + attribute \src "libresoc.v:2499.3-2535.6" + wire $0\ALU_dec31_dec_sub10_is_32b[0:0] + attribute \src "libresoc.v:2758.3-2794.6" + wire width 4 $0\ALU_dec31_dec_sub10_ldst_len[3:0] + attribute \src "libresoc.v:2795.3-2831.6" + wire width 2 $0\ALU_dec31_dec_sub10_rc_sel[1:0] + attribute \src "libresoc.v:2536.3-2572.6" + wire $0\ALU_dec31_dec_sub10_sgn[0:0] + attribute \src "libresoc.v:2168.7-2168.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:2684.3-2720.6" + wire width 3 $1\ALU_dec31_dec_sub10_cr_in[2:0] + attribute \src "libresoc.v:2721.3-2757.6" + wire width 3 $1\ALU_dec31_dec_sub10_cr_out[2:0] + attribute \src "libresoc.v:2832.3-2868.6" + wire width 2 $1\ALU_dec31_dec_sub10_cry_in[1:0] + attribute \src "libresoc.v:2462.3-2498.6" + wire $1\ALU_dec31_dec_sub10_cry_out[0:0] + attribute \src "libresoc.v:2351.3-2387.6" + wire width 12 $1\ALU_dec31_dec_sub10_function_unit[11:0] + attribute \src "libresoc.v:2610.3-2646.6" + wire width 3 $1\ALU_dec31_dec_sub10_in1_sel[2:0] + attribute \src "libresoc.v:2647.3-2683.6" + wire width 4 $1\ALU_dec31_dec_sub10_in2_sel[3:0] + attribute \src "libresoc.v:2573.3-2609.6" + wire width 7 $1\ALU_dec31_dec_sub10_internal_op[6:0] + attribute \src "libresoc.v:2388.3-2424.6" + wire $1\ALU_dec31_dec_sub10_inv_a[0:0] + attribute \src "libresoc.v:2425.3-2461.6" + wire $1\ALU_dec31_dec_sub10_inv_out[0:0] + attribute \src "libresoc.v:2499.3-2535.6" + wire $1\ALU_dec31_dec_sub10_is_32b[0:0] + attribute \src "libresoc.v:2758.3-2794.6" + wire width 4 $1\ALU_dec31_dec_sub10_ldst_len[3:0] + attribute \src "libresoc.v:2795.3-2831.6" + wire width 2 $1\ALU_dec31_dec_sub10_rc_sel[1:0] + attribute \src "libresoc.v:2536.3-2572.6" + wire $1\ALU_dec31_dec_sub10_sgn[0:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \ALU_dec31_dec_sub10_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 6 \ALU_dec31_dec_sub10_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 9 \ALU_dec31_dec_sub10_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 12 \ALU_dec31_dec_sub10_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \ALU_dec31_dec_sub10_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 3 \ALU_dec31_dec_sub10_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 4 \ALU_dec31_dec_sub10_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \ALU_dec31_dec_sub10_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 10 \ALU_dec31_dec_sub10_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 11 \ALU_dec31_dec_sub10_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 13 \ALU_dec31_dec_sub10_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 7 \ALU_dec31_dec_sub10_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 8 \ALU_dec31_dec_sub10_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 14 \ALU_dec31_dec_sub10_sgn + attribute \src "libresoc.v:2168.7-2168.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 15 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 5 \opcode_switch + attribute \src "libresoc.v:2168.7-2168.20" + process $proc$libresoc.v:2168$60 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:2351.3-2387.6" + process $proc$libresoc.v:2351$46 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub10_function_unit[11:0] $1\ALU_dec31_dec_sub10_function_unit[11:0] + attribute \src "libresoc.v:2352.5-2352.29" + switch \initial + attribute \src "libresoc.v:2352.9-2352.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_function_unit[11:0] 12'000000000010 + case + assign $1\ALU_dec31_dec_sub10_function_unit[11:0] 12'000000000000 + end + sync always + update \ALU_dec31_dec_sub10_function_unit $0\ALU_dec31_dec_sub10_function_unit[11:0] + end + attribute \src "libresoc.v:2388.3-2424.6" + process $proc$libresoc.v:2388$47 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub10_inv_a[0:0] $1\ALU_dec31_dec_sub10_inv_a[0:0] + attribute \src "libresoc.v:2389.5-2389.29" + switch \initial + attribute \src "libresoc.v:2389.9-2389.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_inv_a[0:0] 1'0 + case + assign $1\ALU_dec31_dec_sub10_inv_a[0:0] 1'0 + end + sync always + update \ALU_dec31_dec_sub10_inv_a $0\ALU_dec31_dec_sub10_inv_a[0:0] + end + attribute \src "libresoc.v:2425.3-2461.6" + process $proc$libresoc.v:2425$48 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub10_inv_out[0:0] $1\ALU_dec31_dec_sub10_inv_out[0:0] + attribute \src "libresoc.v:2426.5-2426.29" + switch \initial + attribute \src "libresoc.v:2426.9-2426.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_inv_out[0:0] 1'0 + case + assign $1\ALU_dec31_dec_sub10_inv_out[0:0] 1'0 + end + sync always + update \ALU_dec31_dec_sub10_inv_out $0\ALU_dec31_dec_sub10_inv_out[0:0] + end + attribute \src "libresoc.v:2462.3-2498.6" + process $proc$libresoc.v:2462$49 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub10_cry_out[0:0] $1\ALU_dec31_dec_sub10_cry_out[0:0] + attribute \src "libresoc.v:2463.5-2463.29" + switch \initial + attribute \src "libresoc.v:2463.9-2463.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cry_out[0:0] 1'1 + case + assign $1\ALU_dec31_dec_sub10_cry_out[0:0] 1'0 + end + sync always + update \ALU_dec31_dec_sub10_cry_out $0\ALU_dec31_dec_sub10_cry_out[0:0] + end + attribute \src "libresoc.v:2499.3-2535.6" + process $proc$libresoc.v:2499$50 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub10_is_32b[0:0] $1\ALU_dec31_dec_sub10_is_32b[0:0] + attribute \src "libresoc.v:2500.5-2500.29" + switch \initial + attribute \src "libresoc.v:2500.9-2500.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_is_32b[0:0] 1'0 + case + assign $1\ALU_dec31_dec_sub10_is_32b[0:0] 1'0 + end + sync always + update \ALU_dec31_dec_sub10_is_32b $0\ALU_dec31_dec_sub10_is_32b[0:0] + end + attribute \src "libresoc.v:2536.3-2572.6" + process $proc$libresoc.v:2536$51 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub10_sgn[0:0] $1\ALU_dec31_dec_sub10_sgn[0:0] + attribute \src "libresoc.v:2537.5-2537.29" + switch \initial + attribute \src "libresoc.v:2537.9-2537.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_sgn[0:0] 1'0 + case + assign $1\ALU_dec31_dec_sub10_sgn[0:0] 1'0 + end + sync always + update \ALU_dec31_dec_sub10_sgn $0\ALU_dec31_dec_sub10_sgn[0:0] + end + attribute \src "libresoc.v:2573.3-2609.6" + process $proc$libresoc.v:2573$52 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub10_internal_op[6:0] $1\ALU_dec31_dec_sub10_internal_op[6:0] + attribute \src "libresoc.v:2574.5-2574.29" + switch \initial + attribute \src "libresoc.v:2574.9-2574.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_internal_op[6:0] 7'0000010 + case + assign $1\ALU_dec31_dec_sub10_internal_op[6:0] 7'0000000 + end + sync always + update \ALU_dec31_dec_sub10_internal_op $0\ALU_dec31_dec_sub10_internal_op[6:0] + end + attribute \src "libresoc.v:2610.3-2646.6" + process $proc$libresoc.v:2610$53 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub10_in1_sel[2:0] $1\ALU_dec31_dec_sub10_in1_sel[2:0] + attribute \src "libresoc.v:2611.5-2611.29" + switch \initial + attribute \src "libresoc.v:2611.9-2611.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_in1_sel[2:0] 3'001 + case + assign $1\ALU_dec31_dec_sub10_in1_sel[2:0] 3'000 + end + sync always + update \ALU_dec31_dec_sub10_in1_sel $0\ALU_dec31_dec_sub10_in1_sel[2:0] + end + attribute \src "libresoc.v:2647.3-2683.6" + process $proc$libresoc.v:2647$54 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub10_in2_sel[3:0] $1\ALU_dec31_dec_sub10_in2_sel[3:0] + attribute \src "libresoc.v:2648.5-2648.29" + switch \initial + attribute \src "libresoc.v:2648.9-2648.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_in2_sel[3:0] 4'1001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_in2_sel[3:0] 4'1001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_in2_sel[3:0] 4'0000 + case + assign $1\ALU_dec31_dec_sub10_in2_sel[3:0] 4'0000 + end + sync always + update \ALU_dec31_dec_sub10_in2_sel $0\ALU_dec31_dec_sub10_in2_sel[3:0] + end + attribute \src "libresoc.v:2684.3-2720.6" + process $proc$libresoc.v:2684$55 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub10_cr_in[2:0] $1\ALU_dec31_dec_sub10_cr_in[2:0] + attribute \src "libresoc.v:2685.5-2685.29" + switch \initial + attribute \src "libresoc.v:2685.9-2685.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cr_in[2:0] 3'000 + case + assign $1\ALU_dec31_dec_sub10_cr_in[2:0] 3'000 + end + sync always + update \ALU_dec31_dec_sub10_cr_in $0\ALU_dec31_dec_sub10_cr_in[2:0] + end + attribute \src "libresoc.v:2721.3-2757.6" + process $proc$libresoc.v:2721$56 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub10_cr_out[2:0] $1\ALU_dec31_dec_sub10_cr_out[2:0] + attribute \src "libresoc.v:2722.5-2722.29" + switch \initial + attribute \src "libresoc.v:2722.9-2722.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cr_out[2:0] 3'001 + case + assign $1\ALU_dec31_dec_sub10_cr_out[2:0] 3'000 + end + sync always + update \ALU_dec31_dec_sub10_cr_out $0\ALU_dec31_dec_sub10_cr_out[2:0] + end + attribute \src "libresoc.v:2758.3-2794.6" + process $proc$libresoc.v:2758$57 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub10_ldst_len[3:0] $1\ALU_dec31_dec_sub10_ldst_len[3:0] + attribute \src "libresoc.v:2759.5-2759.29" + switch \initial + attribute \src "libresoc.v:2759.9-2759.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_ldst_len[3:0] 4'0000 + case + assign $1\ALU_dec31_dec_sub10_ldst_len[3:0] 4'0000 + end + sync always + update \ALU_dec31_dec_sub10_ldst_len $0\ALU_dec31_dec_sub10_ldst_len[3:0] + end + attribute \src "libresoc.v:2795.3-2831.6" + process $proc$libresoc.v:2795$58 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub10_rc_sel[1:0] $1\ALU_dec31_dec_sub10_rc_sel[1:0] + attribute \src "libresoc.v:2796.5-2796.29" + switch \initial + attribute \src "libresoc.v:2796.9-2796.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_rc_sel[1:0] 2'10 + case + assign $1\ALU_dec31_dec_sub10_rc_sel[1:0] 2'00 + end + sync always + update \ALU_dec31_dec_sub10_rc_sel $0\ALU_dec31_dec_sub10_rc_sel[1:0] + end + attribute \src "libresoc.v:2832.3-2868.6" + process $proc$libresoc.v:2832$59 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub10_cry_in[1:0] $1\ALU_dec31_dec_sub10_cry_in[1:0] + attribute \src "libresoc.v:2833.5-2833.29" + switch \initial + attribute \src "libresoc.v:2833.9-2833.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cry_in[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cry_in[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cry_in[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cry_in[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cry_in[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cry_in[1:0] 2'10 + case + assign $1\ALU_dec31_dec_sub10_cry_in[1:0] 2'00 + end + sync always + update \ALU_dec31_dec_sub10_cry_in $0\ALU_dec31_dec_sub10_cry_in[1:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:2874.1-3451.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_ALU.dec.ALU_dec31.ALU_dec31_dec_sub22" +attribute \generator "nMigen" +module \ALU_dec31_dec_sub22 + attribute \src "libresoc.v:3310.3-3337.6" + wire width 3 $0\ALU_dec31_dec_sub22_cr_in[2:0] + attribute \src "libresoc.v:3338.3-3365.6" + wire width 3 $0\ALU_dec31_dec_sub22_cr_out[2:0] + attribute \src "libresoc.v:3422.3-3449.6" + wire width 2 $0\ALU_dec31_dec_sub22_cry_in[1:0] + attribute \src "libresoc.v:3142.3-3169.6" + wire $0\ALU_dec31_dec_sub22_cry_out[0:0] + attribute \src "libresoc.v:3058.3-3085.6" + wire width 12 $0\ALU_dec31_dec_sub22_function_unit[11:0] + attribute \src "libresoc.v:3254.3-3281.6" + wire width 3 $0\ALU_dec31_dec_sub22_in1_sel[2:0] + attribute \src "libresoc.v:3282.3-3309.6" + wire width 4 $0\ALU_dec31_dec_sub22_in2_sel[3:0] + attribute \src "libresoc.v:3226.3-3253.6" + wire width 7 $0\ALU_dec31_dec_sub22_internal_op[6:0] + attribute \src "libresoc.v:3086.3-3113.6" + wire $0\ALU_dec31_dec_sub22_inv_a[0:0] + attribute \src "libresoc.v:3114.3-3141.6" + wire $0\ALU_dec31_dec_sub22_inv_out[0:0] + attribute \src "libresoc.v:3170.3-3197.6" + wire $0\ALU_dec31_dec_sub22_is_32b[0:0] + attribute \src "libresoc.v:3366.3-3393.6" + wire width 4 $0\ALU_dec31_dec_sub22_ldst_len[3:0] + attribute \src "libresoc.v:3394.3-3421.6" + wire width 2 $0\ALU_dec31_dec_sub22_rc_sel[1:0] + attribute \src "libresoc.v:3198.3-3225.6" + wire $0\ALU_dec31_dec_sub22_sgn[0:0] + attribute \src "libresoc.v:2875.7-2875.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:3310.3-3337.6" + wire width 3 $1\ALU_dec31_dec_sub22_cr_in[2:0] + attribute \src "libresoc.v:3338.3-3365.6" + wire width 3 $1\ALU_dec31_dec_sub22_cr_out[2:0] + attribute \src "libresoc.v:3422.3-3449.6" + wire width 2 $1\ALU_dec31_dec_sub22_cry_in[1:0] + attribute \src "libresoc.v:3142.3-3169.6" + wire $1\ALU_dec31_dec_sub22_cry_out[0:0] + attribute \src "libresoc.v:3058.3-3085.6" + wire width 12 $1\ALU_dec31_dec_sub22_function_unit[11:0] + attribute \src "libresoc.v:3254.3-3281.6" + wire width 3 $1\ALU_dec31_dec_sub22_in1_sel[2:0] + attribute \src "libresoc.v:3282.3-3309.6" + wire width 4 $1\ALU_dec31_dec_sub22_in2_sel[3:0] + attribute \src "libresoc.v:3226.3-3253.6" + wire width 7 $1\ALU_dec31_dec_sub22_internal_op[6:0] + attribute \src "libresoc.v:3086.3-3113.6" + wire $1\ALU_dec31_dec_sub22_inv_a[0:0] + attribute \src "libresoc.v:3114.3-3141.6" + wire $1\ALU_dec31_dec_sub22_inv_out[0:0] + attribute \src "libresoc.v:3170.3-3197.6" + wire $1\ALU_dec31_dec_sub22_is_32b[0:0] + attribute \src "libresoc.v:3366.3-3393.6" + wire width 4 $1\ALU_dec31_dec_sub22_ldst_len[3:0] + attribute \src "libresoc.v:3394.3-3421.6" + wire width 2 $1\ALU_dec31_dec_sub22_rc_sel[1:0] + attribute \src "libresoc.v:3198.3-3225.6" + wire $1\ALU_dec31_dec_sub22_sgn[0:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \ALU_dec31_dec_sub22_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 6 \ALU_dec31_dec_sub22_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 9 \ALU_dec31_dec_sub22_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 12 \ALU_dec31_dec_sub22_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \ALU_dec31_dec_sub22_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 3 \ALU_dec31_dec_sub22_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 4 \ALU_dec31_dec_sub22_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \ALU_dec31_dec_sub22_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 10 \ALU_dec31_dec_sub22_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 11 \ALU_dec31_dec_sub22_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 13 \ALU_dec31_dec_sub22_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 7 \ALU_dec31_dec_sub22_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 8 \ALU_dec31_dec_sub22_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 14 \ALU_dec31_dec_sub22_sgn + attribute \src "libresoc.v:2875.7-2875.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 15 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 5 \opcode_switch + attribute \src "libresoc.v:2875.7-2875.20" + process $proc$libresoc.v:2875$75 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:3058.3-3085.6" + process $proc$libresoc.v:3058$61 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub22_function_unit[11:0] $1\ALU_dec31_dec_sub22_function_unit[11:0] + attribute \src "libresoc.v:3059.5-3059.29" + switch \initial + attribute \src "libresoc.v:3059.9-3059.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub22_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub22_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub22_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_function_unit[11:0] 12'000000000010 + case + assign $1\ALU_dec31_dec_sub22_function_unit[11:0] 12'000000000000 + end + sync always + update \ALU_dec31_dec_sub22_function_unit $0\ALU_dec31_dec_sub22_function_unit[11:0] + end + attribute \src "libresoc.v:3086.3-3113.6" + process $proc$libresoc.v:3086$62 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub22_inv_a[0:0] $1\ALU_dec31_dec_sub22_inv_a[0:0] + attribute \src "libresoc.v:3087.5-3087.29" + switch \initial + attribute \src "libresoc.v:3087.9-3087.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_inv_a[0:0] 1'0 + case + assign $1\ALU_dec31_dec_sub22_inv_a[0:0] 1'0 + end + sync always + update \ALU_dec31_dec_sub22_inv_a $0\ALU_dec31_dec_sub22_inv_a[0:0] + end + attribute \src "libresoc.v:3114.3-3141.6" + process $proc$libresoc.v:3114$63 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub22_inv_out[0:0] $1\ALU_dec31_dec_sub22_inv_out[0:0] + attribute \src "libresoc.v:3115.5-3115.29" + switch \initial + attribute \src "libresoc.v:3115.9-3115.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_inv_out[0:0] 1'0 + case + assign $1\ALU_dec31_dec_sub22_inv_out[0:0] 1'0 + end + sync always + update \ALU_dec31_dec_sub22_inv_out $0\ALU_dec31_dec_sub22_inv_out[0:0] + end + attribute \src "libresoc.v:3142.3-3169.6" + process $proc$libresoc.v:3142$64 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub22_cry_out[0:0] $1\ALU_dec31_dec_sub22_cry_out[0:0] + attribute \src "libresoc.v:3143.5-3143.29" + switch \initial + attribute \src "libresoc.v:3143.9-3143.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cry_out[0:0] 1'0 + case + assign $1\ALU_dec31_dec_sub22_cry_out[0:0] 1'0 + end + sync always + update \ALU_dec31_dec_sub22_cry_out $0\ALU_dec31_dec_sub22_cry_out[0:0] + end + attribute \src "libresoc.v:3170.3-3197.6" + process $proc$libresoc.v:3170$65 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub22_is_32b[0:0] $1\ALU_dec31_dec_sub22_is_32b[0:0] + attribute \src "libresoc.v:3171.5-3171.29" + switch \initial + attribute \src "libresoc.v:3171.9-3171.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_is_32b[0:0] 1'0 + case + assign $1\ALU_dec31_dec_sub22_is_32b[0:0] 1'0 + end + sync always + update \ALU_dec31_dec_sub22_is_32b $0\ALU_dec31_dec_sub22_is_32b[0:0] + end + attribute \src "libresoc.v:3198.3-3225.6" + process $proc$libresoc.v:3198$66 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub22_sgn[0:0] $1\ALU_dec31_dec_sub22_sgn[0:0] + attribute \src "libresoc.v:3199.5-3199.29" + switch \initial + attribute \src "libresoc.v:3199.9-3199.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_sgn[0:0] 1'0 + case + assign $1\ALU_dec31_dec_sub22_sgn[0:0] 1'0 + end + sync always + update \ALU_dec31_dec_sub22_sgn $0\ALU_dec31_dec_sub22_sgn[0:0] + end + attribute \src "libresoc.v:3226.3-3253.6" + process $proc$libresoc.v:3226$67 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub22_internal_op[6:0] $1\ALU_dec31_dec_sub22_internal_op[6:0] + attribute \src "libresoc.v:3227.5-3227.29" + switch \initial + attribute \src "libresoc.v:3227.9-3227.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_internal_op[6:0] 7'0000001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub22_internal_op[6:0] 7'0000001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_internal_op[6:0] 7'0000001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub22_internal_op[6:0] 7'0000001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub22_internal_op[6:0] 7'0100001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_internal_op[6:0] 7'0000001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_internal_op[6:0] 7'0000001 + case + assign $1\ALU_dec31_dec_sub22_internal_op[6:0] 7'0000000 + end + sync always + update \ALU_dec31_dec_sub22_internal_op $0\ALU_dec31_dec_sub22_internal_op[6:0] + end + attribute \src "libresoc.v:3254.3-3281.6" + process $proc$libresoc.v:3254$68 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub22_in1_sel[2:0] $1\ALU_dec31_dec_sub22_in1_sel[2:0] + attribute \src "libresoc.v:3255.5-3255.29" + switch \initial + attribute \src "libresoc.v:3255.9-3255.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub22_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub22_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub22_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_in1_sel[2:0] 3'000 + case + assign $1\ALU_dec31_dec_sub22_in1_sel[2:0] 3'000 + end + sync always + update \ALU_dec31_dec_sub22_in1_sel $0\ALU_dec31_dec_sub22_in1_sel[2:0] + end + attribute \src "libresoc.v:3282.3-3309.6" + process $proc$libresoc.v:3282$69 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub22_in2_sel[3:0] $1\ALU_dec31_dec_sub22_in2_sel[3:0] + attribute \src "libresoc.v:3283.5-3283.29" + switch \initial + attribute \src "libresoc.v:3283.9-3283.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub22_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub22_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub22_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_in2_sel[3:0] 4'0000 + case + assign $1\ALU_dec31_dec_sub22_in2_sel[3:0] 4'0000 + end + sync always + update \ALU_dec31_dec_sub22_in2_sel $0\ALU_dec31_dec_sub22_in2_sel[3:0] + end + attribute \src "libresoc.v:3310.3-3337.6" + process $proc$libresoc.v:3310$70 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub22_cr_in[2:0] $1\ALU_dec31_dec_sub22_cr_in[2:0] + attribute \src "libresoc.v:3311.5-3311.29" + switch \initial + attribute \src "libresoc.v:3311.9-3311.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cr_in[2:0] 3'000 + case + assign $1\ALU_dec31_dec_sub22_cr_in[2:0] 3'000 + end + sync always + update \ALU_dec31_dec_sub22_cr_in $0\ALU_dec31_dec_sub22_cr_in[2:0] + end + attribute \src "libresoc.v:3338.3-3365.6" + process $proc$libresoc.v:3338$71 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub22_cr_out[2:0] $1\ALU_dec31_dec_sub22_cr_out[2:0] + attribute \src "libresoc.v:3339.5-3339.29" + switch \initial + attribute \src "libresoc.v:3339.9-3339.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cr_out[2:0] 3'000 + case + assign $1\ALU_dec31_dec_sub22_cr_out[2:0] 3'000 + end + sync always + update \ALU_dec31_dec_sub22_cr_out $0\ALU_dec31_dec_sub22_cr_out[2:0] + end + attribute \src "libresoc.v:3366.3-3393.6" + process $proc$libresoc.v:3366$72 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub22_ldst_len[3:0] $1\ALU_dec31_dec_sub22_ldst_len[3:0] + attribute \src "libresoc.v:3367.5-3367.29" + switch \initial + attribute \src "libresoc.v:3367.9-3367.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub22_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub22_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub22_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_ldst_len[3:0] 4'0000 + case + assign $1\ALU_dec31_dec_sub22_ldst_len[3:0] 4'0000 + end + sync always + update \ALU_dec31_dec_sub22_ldst_len $0\ALU_dec31_dec_sub22_ldst_len[3:0] + end + attribute \src "libresoc.v:3394.3-3421.6" + process $proc$libresoc.v:3394$73 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub22_rc_sel[1:0] $1\ALU_dec31_dec_sub22_rc_sel[1:0] + attribute \src "libresoc.v:3395.5-3395.29" + switch \initial + attribute \src "libresoc.v:3395.9-3395.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_rc_sel[1:0] 2'00 + case + assign $1\ALU_dec31_dec_sub22_rc_sel[1:0] 2'00 + end + sync always + update \ALU_dec31_dec_sub22_rc_sel $0\ALU_dec31_dec_sub22_rc_sel[1:0] + end + attribute \src "libresoc.v:3422.3-3449.6" + process $proc$libresoc.v:3422$74 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub22_cry_in[1:0] $1\ALU_dec31_dec_sub22_cry_in[1:0] + attribute \src "libresoc.v:3423.5-3423.29" + switch \initial + attribute \src "libresoc.v:3423.9-3423.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cry_in[1:0] 2'00 + case + assign $1\ALU_dec31_dec_sub22_cry_in[1:0] 2'00 + end + sync always + update \ALU_dec31_dec_sub22_cry_in $0\ALU_dec31_dec_sub22_cry_in[1:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:3455.1-3864.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_ALU.dec.ALU_dec31.ALU_dec31_dec_sub26" +attribute \generator "nMigen" +module \ALU_dec31_dec_sub26 + attribute \src "libresoc.v:3783.3-3798.6" + wire width 3 $0\ALU_dec31_dec_sub26_cr_in[2:0] + attribute \src "libresoc.v:3799.3-3814.6" + wire width 3 $0\ALU_dec31_dec_sub26_cr_out[2:0] + attribute \src "libresoc.v:3847.3-3862.6" + wire width 2 $0\ALU_dec31_dec_sub26_cry_in[1:0] + attribute \src "libresoc.v:3687.3-3702.6" + wire $0\ALU_dec31_dec_sub26_cry_out[0:0] + attribute \src "libresoc.v:3639.3-3654.6" + wire width 12 $0\ALU_dec31_dec_sub26_function_unit[11:0] + attribute \src "libresoc.v:3751.3-3766.6" + wire width 3 $0\ALU_dec31_dec_sub26_in1_sel[2:0] + attribute \src "libresoc.v:3767.3-3782.6" + wire width 4 $0\ALU_dec31_dec_sub26_in2_sel[3:0] + attribute \src "libresoc.v:3735.3-3750.6" + wire width 7 $0\ALU_dec31_dec_sub26_internal_op[6:0] + attribute \src "libresoc.v:3655.3-3670.6" + wire $0\ALU_dec31_dec_sub26_inv_a[0:0] + attribute \src "libresoc.v:3671.3-3686.6" + wire $0\ALU_dec31_dec_sub26_inv_out[0:0] + attribute \src "libresoc.v:3703.3-3718.6" + wire $0\ALU_dec31_dec_sub26_is_32b[0:0] + attribute \src "libresoc.v:3815.3-3830.6" + wire width 4 $0\ALU_dec31_dec_sub26_ldst_len[3:0] + attribute \src "libresoc.v:3831.3-3846.6" + wire width 2 $0\ALU_dec31_dec_sub26_rc_sel[1:0] + attribute \src "libresoc.v:3719.3-3734.6" + wire $0\ALU_dec31_dec_sub26_sgn[0:0] + attribute \src "libresoc.v:3456.7-3456.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:3783.3-3798.6" + wire width 3 $1\ALU_dec31_dec_sub26_cr_in[2:0] + attribute \src "libresoc.v:3799.3-3814.6" + wire width 3 $1\ALU_dec31_dec_sub26_cr_out[2:0] + attribute \src "libresoc.v:3847.3-3862.6" + wire width 2 $1\ALU_dec31_dec_sub26_cry_in[1:0] + attribute \src "libresoc.v:3687.3-3702.6" + wire $1\ALU_dec31_dec_sub26_cry_out[0:0] + attribute \src "libresoc.v:3639.3-3654.6" + wire width 12 $1\ALU_dec31_dec_sub26_function_unit[11:0] + attribute \src "libresoc.v:3751.3-3766.6" + wire width 3 $1\ALU_dec31_dec_sub26_in1_sel[2:0] + attribute \src "libresoc.v:3767.3-3782.6" + wire width 4 $1\ALU_dec31_dec_sub26_in2_sel[3:0] + attribute \src "libresoc.v:3735.3-3750.6" + wire width 7 $1\ALU_dec31_dec_sub26_internal_op[6:0] + attribute \src "libresoc.v:3655.3-3670.6" + wire $1\ALU_dec31_dec_sub26_inv_a[0:0] + attribute \src "libresoc.v:3671.3-3686.6" + wire $1\ALU_dec31_dec_sub26_inv_out[0:0] + attribute \src "libresoc.v:3703.3-3718.6" + wire $1\ALU_dec31_dec_sub26_is_32b[0:0] + attribute \src "libresoc.v:3815.3-3830.6" + wire width 4 $1\ALU_dec31_dec_sub26_ldst_len[3:0] + attribute \src "libresoc.v:3831.3-3846.6" + wire width 2 $1\ALU_dec31_dec_sub26_rc_sel[1:0] + attribute \src "libresoc.v:3719.3-3734.6" + wire $1\ALU_dec31_dec_sub26_sgn[0:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \ALU_dec31_dec_sub26_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 6 \ALU_dec31_dec_sub26_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 9 \ALU_dec31_dec_sub26_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 12 \ALU_dec31_dec_sub26_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \ALU_dec31_dec_sub26_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 3 \ALU_dec31_dec_sub26_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 4 \ALU_dec31_dec_sub26_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \ALU_dec31_dec_sub26_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 10 \ALU_dec31_dec_sub26_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 11 \ALU_dec31_dec_sub26_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 13 \ALU_dec31_dec_sub26_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 7 \ALU_dec31_dec_sub26_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 8 \ALU_dec31_dec_sub26_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 14 \ALU_dec31_dec_sub26_sgn + attribute \src "libresoc.v:3456.7-3456.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 15 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 5 \opcode_switch + attribute \src "libresoc.v:3456.7-3456.20" + process $proc$libresoc.v:3456$90 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:3639.3-3654.6" + process $proc$libresoc.v:3639$76 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub26_function_unit[11:0] $1\ALU_dec31_dec_sub26_function_unit[11:0] + attribute \src "libresoc.v:3640.5-3640.29" + switch \initial + attribute \src "libresoc.v:3640.9-3640.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\ALU_dec31_dec_sub26_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\ALU_dec31_dec_sub26_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub26_function_unit[11:0] 12'000000000010 + case + assign $1\ALU_dec31_dec_sub26_function_unit[11:0] 12'000000000000 + end + sync always + update \ALU_dec31_dec_sub26_function_unit $0\ALU_dec31_dec_sub26_function_unit[11:0] + end + attribute \src "libresoc.v:3655.3-3670.6" + process $proc$libresoc.v:3655$77 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub26_inv_a[0:0] $1\ALU_dec31_dec_sub26_inv_a[0:0] + attribute \src "libresoc.v:3656.5-3656.29" + switch \initial + attribute \src "libresoc.v:3656.9-3656.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\ALU_dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\ALU_dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub26_inv_a[0:0] 1'0 + case + assign $1\ALU_dec31_dec_sub26_inv_a[0:0] 1'0 + end + sync always + update \ALU_dec31_dec_sub26_inv_a $0\ALU_dec31_dec_sub26_inv_a[0:0] + end + attribute \src "libresoc.v:3671.3-3686.6" + process $proc$libresoc.v:3671$78 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub26_inv_out[0:0] $1\ALU_dec31_dec_sub26_inv_out[0:0] + attribute \src "libresoc.v:3672.5-3672.29" + switch \initial + attribute \src "libresoc.v:3672.9-3672.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\ALU_dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\ALU_dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub26_inv_out[0:0] 1'0 + case + assign $1\ALU_dec31_dec_sub26_inv_out[0:0] 1'0 + end + sync always + update \ALU_dec31_dec_sub26_inv_out $0\ALU_dec31_dec_sub26_inv_out[0:0] + end + attribute \src "libresoc.v:3687.3-3702.6" + process $proc$libresoc.v:3687$79 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub26_cry_out[0:0] $1\ALU_dec31_dec_sub26_cry_out[0:0] + attribute \src "libresoc.v:3688.5-3688.29" + switch \initial + attribute \src "libresoc.v:3688.9-3688.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\ALU_dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\ALU_dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub26_cry_out[0:0] 1'0 + case + assign $1\ALU_dec31_dec_sub26_cry_out[0:0] 1'0 + end + sync always + update \ALU_dec31_dec_sub26_cry_out $0\ALU_dec31_dec_sub26_cry_out[0:0] + end + attribute \src "libresoc.v:3703.3-3718.6" + process $proc$libresoc.v:3703$80 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub26_is_32b[0:0] $1\ALU_dec31_dec_sub26_is_32b[0:0] + attribute \src "libresoc.v:3704.5-3704.29" + switch \initial + attribute \src "libresoc.v:3704.9-3704.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\ALU_dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\ALU_dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub26_is_32b[0:0] 1'0 + case + assign $1\ALU_dec31_dec_sub26_is_32b[0:0] 1'0 + end + sync always + update \ALU_dec31_dec_sub26_is_32b $0\ALU_dec31_dec_sub26_is_32b[0:0] + end + attribute \src "libresoc.v:3719.3-3734.6" + process $proc$libresoc.v:3719$81 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub26_sgn[0:0] $1\ALU_dec31_dec_sub26_sgn[0:0] + attribute \src "libresoc.v:3720.5-3720.29" + switch \initial + attribute \src "libresoc.v:3720.9-3720.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\ALU_dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\ALU_dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub26_sgn[0:0] 1'0 + case + assign $1\ALU_dec31_dec_sub26_sgn[0:0] 1'0 + end + sync always + update \ALU_dec31_dec_sub26_sgn $0\ALU_dec31_dec_sub26_sgn[0:0] + end + attribute \src "libresoc.v:3735.3-3750.6" + process $proc$libresoc.v:3735$82 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub26_internal_op[6:0] $1\ALU_dec31_dec_sub26_internal_op[6:0] + attribute \src "libresoc.v:3736.5-3736.29" + switch \initial + attribute \src "libresoc.v:3736.9-3736.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\ALU_dec31_dec_sub26_internal_op[6:0] 7'0011111 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\ALU_dec31_dec_sub26_internal_op[6:0] 7'0011111 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub26_internal_op[6:0] 7'0011111 + case + assign $1\ALU_dec31_dec_sub26_internal_op[6:0] 7'0000000 + end + sync always + update \ALU_dec31_dec_sub26_internal_op $0\ALU_dec31_dec_sub26_internal_op[6:0] + end + attribute \src "libresoc.v:3751.3-3766.6" + process $proc$libresoc.v:3751$83 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub26_in1_sel[2:0] $1\ALU_dec31_dec_sub26_in1_sel[2:0] + attribute \src "libresoc.v:3752.5-3752.29" + switch \initial + attribute \src "libresoc.v:3752.9-3752.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\ALU_dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\ALU_dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub26_in1_sel[2:0] 3'100 + case + assign $1\ALU_dec31_dec_sub26_in1_sel[2:0] 3'000 + end + sync always + update \ALU_dec31_dec_sub26_in1_sel $0\ALU_dec31_dec_sub26_in1_sel[2:0] + end + attribute \src "libresoc.v:3767.3-3782.6" + process $proc$libresoc.v:3767$84 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub26_in2_sel[3:0] $1\ALU_dec31_dec_sub26_in2_sel[3:0] + attribute \src "libresoc.v:3768.5-3768.29" + switch \initial + attribute \src "libresoc.v:3768.9-3768.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\ALU_dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\ALU_dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub26_in2_sel[3:0] 4'0000 + case + assign $1\ALU_dec31_dec_sub26_in2_sel[3:0] 4'0000 + end + sync always + update \ALU_dec31_dec_sub26_in2_sel $0\ALU_dec31_dec_sub26_in2_sel[3:0] + end + attribute \src "libresoc.v:3783.3-3798.6" + process $proc$libresoc.v:3783$85 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub26_cr_in[2:0] $1\ALU_dec31_dec_sub26_cr_in[2:0] + attribute \src "libresoc.v:3784.5-3784.29" + switch \initial + attribute \src "libresoc.v:3784.9-3784.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\ALU_dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\ALU_dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub26_cr_in[2:0] 3'000 + case + assign $1\ALU_dec31_dec_sub26_cr_in[2:0] 3'000 + end + sync always + update \ALU_dec31_dec_sub26_cr_in $0\ALU_dec31_dec_sub26_cr_in[2:0] + end + attribute \src "libresoc.v:3799.3-3814.6" + process $proc$libresoc.v:3799$86 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub26_cr_out[2:0] $1\ALU_dec31_dec_sub26_cr_out[2:0] + attribute \src "libresoc.v:3800.5-3800.29" + switch \initial + attribute \src "libresoc.v:3800.9-3800.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\ALU_dec31_dec_sub26_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\ALU_dec31_dec_sub26_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub26_cr_out[2:0] 3'001 + case + assign $1\ALU_dec31_dec_sub26_cr_out[2:0] 3'000 + end + sync always + update \ALU_dec31_dec_sub26_cr_out $0\ALU_dec31_dec_sub26_cr_out[2:0] + end + attribute \src "libresoc.v:3815.3-3830.6" + process $proc$libresoc.v:3815$87 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub26_ldst_len[3:0] $1\ALU_dec31_dec_sub26_ldst_len[3:0] + attribute \src "libresoc.v:3816.5-3816.29" + switch \initial + attribute \src "libresoc.v:3816.9-3816.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\ALU_dec31_dec_sub26_ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\ALU_dec31_dec_sub26_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub26_ldst_len[3:0] 4'0100 + case + assign $1\ALU_dec31_dec_sub26_ldst_len[3:0] 4'0000 + end + sync always + update \ALU_dec31_dec_sub26_ldst_len $0\ALU_dec31_dec_sub26_ldst_len[3:0] + end + attribute \src "libresoc.v:3831.3-3846.6" + process $proc$libresoc.v:3831$88 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub26_rc_sel[1:0] $1\ALU_dec31_dec_sub26_rc_sel[1:0] + attribute \src "libresoc.v:3832.5-3832.29" + switch \initial + attribute \src "libresoc.v:3832.9-3832.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\ALU_dec31_dec_sub26_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\ALU_dec31_dec_sub26_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub26_rc_sel[1:0] 2'10 + case + assign $1\ALU_dec31_dec_sub26_rc_sel[1:0] 2'00 + end + sync always + update \ALU_dec31_dec_sub26_rc_sel $0\ALU_dec31_dec_sub26_rc_sel[1:0] + end + attribute \src "libresoc.v:3847.3-3862.6" + process $proc$libresoc.v:3847$89 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub26_cry_in[1:0] $1\ALU_dec31_dec_sub26_cry_in[1:0] + attribute \src "libresoc.v:3848.5-3848.29" + switch \initial + attribute \src "libresoc.v:3848.9-3848.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\ALU_dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\ALU_dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub26_cry_in[1:0] 2'00 + case + assign $1\ALU_dec31_dec_sub26_cry_in[1:0] 2'00 + end + sync always + update \ALU_dec31_dec_sub26_cry_in $0\ALU_dec31_dec_sub26_cry_in[1:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:3868.1-4655.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_ALU.dec.ALU_dec31.ALU_dec31_dec_sub8" +attribute \generator "nMigen" +module \ALU_dec31_dec_sub8 + attribute \src "libresoc.v:4439.3-4481.6" + wire width 3 $0\ALU_dec31_dec_sub8_cr_in[2:0] + attribute \src "libresoc.v:4482.3-4524.6" + wire width 3 $0\ALU_dec31_dec_sub8_cr_out[2:0] + attribute \src "libresoc.v:4611.3-4653.6" + wire width 2 $0\ALU_dec31_dec_sub8_cry_in[1:0] + attribute \src "libresoc.v:4181.3-4223.6" + wire $0\ALU_dec31_dec_sub8_cry_out[0:0] + attribute \src "libresoc.v:4052.3-4094.6" + wire width 12 $0\ALU_dec31_dec_sub8_function_unit[11:0] + attribute \src "libresoc.v:4353.3-4395.6" + wire width 3 $0\ALU_dec31_dec_sub8_in1_sel[2:0] + attribute \src "libresoc.v:4396.3-4438.6" + wire width 4 $0\ALU_dec31_dec_sub8_in2_sel[3:0] + attribute \src "libresoc.v:4310.3-4352.6" + wire width 7 $0\ALU_dec31_dec_sub8_internal_op[6:0] + attribute \src "libresoc.v:4095.3-4137.6" + wire $0\ALU_dec31_dec_sub8_inv_a[0:0] + attribute \src "libresoc.v:4138.3-4180.6" + wire $0\ALU_dec31_dec_sub8_inv_out[0:0] + attribute \src "libresoc.v:4224.3-4266.6" + wire $0\ALU_dec31_dec_sub8_is_32b[0:0] + attribute \src "libresoc.v:4525.3-4567.6" + wire width 4 $0\ALU_dec31_dec_sub8_ldst_len[3:0] + attribute \src "libresoc.v:4568.3-4610.6" + wire width 2 $0\ALU_dec31_dec_sub8_rc_sel[1:0] + attribute \src "libresoc.v:4267.3-4309.6" + wire $0\ALU_dec31_dec_sub8_sgn[0:0] + attribute \src "libresoc.v:3869.7-3869.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:4439.3-4481.6" + wire width 3 $1\ALU_dec31_dec_sub8_cr_in[2:0] + attribute \src "libresoc.v:4482.3-4524.6" + wire width 3 $1\ALU_dec31_dec_sub8_cr_out[2:0] + attribute \src "libresoc.v:4611.3-4653.6" + wire width 2 $1\ALU_dec31_dec_sub8_cry_in[1:0] + attribute \src "libresoc.v:4181.3-4223.6" + wire $1\ALU_dec31_dec_sub8_cry_out[0:0] + attribute \src "libresoc.v:4052.3-4094.6" + wire width 12 $1\ALU_dec31_dec_sub8_function_unit[11:0] + attribute \src "libresoc.v:4353.3-4395.6" + wire width 3 $1\ALU_dec31_dec_sub8_in1_sel[2:0] + attribute \src "libresoc.v:4396.3-4438.6" + wire width 4 $1\ALU_dec31_dec_sub8_in2_sel[3:0] + attribute \src "libresoc.v:4310.3-4352.6" + wire width 7 $1\ALU_dec31_dec_sub8_internal_op[6:0] + attribute \src "libresoc.v:4095.3-4137.6" + wire $1\ALU_dec31_dec_sub8_inv_a[0:0] + attribute \src "libresoc.v:4138.3-4180.6" + wire $1\ALU_dec31_dec_sub8_inv_out[0:0] + attribute \src "libresoc.v:4224.3-4266.6" + wire $1\ALU_dec31_dec_sub8_is_32b[0:0] + attribute \src "libresoc.v:4525.3-4567.6" + wire width 4 $1\ALU_dec31_dec_sub8_ldst_len[3:0] + attribute \src "libresoc.v:4568.3-4610.6" + wire width 2 $1\ALU_dec31_dec_sub8_rc_sel[1:0] + attribute \src "libresoc.v:4267.3-4309.6" + wire $1\ALU_dec31_dec_sub8_sgn[0:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \ALU_dec31_dec_sub8_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 6 \ALU_dec31_dec_sub8_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 9 \ALU_dec31_dec_sub8_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 12 \ALU_dec31_dec_sub8_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \ALU_dec31_dec_sub8_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 3 \ALU_dec31_dec_sub8_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 4 \ALU_dec31_dec_sub8_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \ALU_dec31_dec_sub8_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 10 \ALU_dec31_dec_sub8_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 11 \ALU_dec31_dec_sub8_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 13 \ALU_dec31_dec_sub8_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 7 \ALU_dec31_dec_sub8_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 8 \ALU_dec31_dec_sub8_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 14 \ALU_dec31_dec_sub8_sgn + attribute \src "libresoc.v:3869.7-3869.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 15 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 5 \opcode_switch + attribute \src "libresoc.v:3869.7-3869.20" + process $proc$libresoc.v:3869$105 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:4052.3-4094.6" + process $proc$libresoc.v:4052$91 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub8_function_unit[11:0] $1\ALU_dec31_dec_sub8_function_unit[11:0] + attribute \src "libresoc.v:4053.5-4053.29" + switch \initial + attribute \src "libresoc.v:4053.9-4053.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_function_unit[11:0] 12'000000000010 + case + assign $1\ALU_dec31_dec_sub8_function_unit[11:0] 12'000000000000 + end + sync always + update \ALU_dec31_dec_sub8_function_unit $0\ALU_dec31_dec_sub8_function_unit[11:0] + end + attribute \src "libresoc.v:4095.3-4137.6" + process $proc$libresoc.v:4095$92 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub8_inv_a[0:0] $1\ALU_dec31_dec_sub8_inv_a[0:0] + attribute \src "libresoc.v:4096.5-4096.29" + switch \initial + attribute \src "libresoc.v:4096.9-4096.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_inv_a[0:0] 1'1 + case + assign $1\ALU_dec31_dec_sub8_inv_a[0:0] 1'0 + end + sync always + update \ALU_dec31_dec_sub8_inv_a $0\ALU_dec31_dec_sub8_inv_a[0:0] + end + attribute \src "libresoc.v:4138.3-4180.6" + process $proc$libresoc.v:4138$93 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub8_inv_out[0:0] $1\ALU_dec31_dec_sub8_inv_out[0:0] + attribute \src "libresoc.v:4139.5-4139.29" + switch \initial + attribute \src "libresoc.v:4139.9-4139.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_inv_out[0:0] 1'0 + case + assign $1\ALU_dec31_dec_sub8_inv_out[0:0] 1'0 + end + sync always + update \ALU_dec31_dec_sub8_inv_out $0\ALU_dec31_dec_sub8_inv_out[0:0] + end + attribute \src "libresoc.v:4181.3-4223.6" + process $proc$libresoc.v:4181$94 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub8_cry_out[0:0] $1\ALU_dec31_dec_sub8_cry_out[0:0] + attribute \src "libresoc.v:4182.5-4182.29" + switch \initial + attribute \src "libresoc.v:4182.9-4182.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cry_out[0:0] 1'1 + case + assign $1\ALU_dec31_dec_sub8_cry_out[0:0] 1'0 + end + sync always + update \ALU_dec31_dec_sub8_cry_out $0\ALU_dec31_dec_sub8_cry_out[0:0] + end + attribute \src "libresoc.v:4224.3-4266.6" + process $proc$libresoc.v:4224$95 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub8_is_32b[0:0] $1\ALU_dec31_dec_sub8_is_32b[0:0] + attribute \src "libresoc.v:4225.5-4225.29" + switch \initial + attribute \src "libresoc.v:4225.9-4225.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_is_32b[0:0] 1'0 + case + assign $1\ALU_dec31_dec_sub8_is_32b[0:0] 1'0 + end + sync always + update \ALU_dec31_dec_sub8_is_32b $0\ALU_dec31_dec_sub8_is_32b[0:0] + end + attribute \src "libresoc.v:4267.3-4309.6" + process $proc$libresoc.v:4267$96 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub8_sgn[0:0] $1\ALU_dec31_dec_sub8_sgn[0:0] + attribute \src "libresoc.v:4268.5-4268.29" + switch \initial + attribute \src "libresoc.v:4268.9-4268.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_sgn[0:0] 1'0 + case + assign $1\ALU_dec31_dec_sub8_sgn[0:0] 1'0 + end + sync always + update \ALU_dec31_dec_sub8_sgn $0\ALU_dec31_dec_sub8_sgn[0:0] + end + attribute \src "libresoc.v:4310.3-4352.6" + process $proc$libresoc.v:4310$97 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub8_internal_op[6:0] $1\ALU_dec31_dec_sub8_internal_op[6:0] + attribute \src "libresoc.v:4311.5-4311.29" + switch \initial + attribute \src "libresoc.v:4311.9-4311.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_internal_op[6:0] 7'0000010 + case + assign $1\ALU_dec31_dec_sub8_internal_op[6:0] 7'0000000 + end + sync always + update \ALU_dec31_dec_sub8_internal_op $0\ALU_dec31_dec_sub8_internal_op[6:0] + end + attribute \src "libresoc.v:4353.3-4395.6" + process $proc$libresoc.v:4353$98 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub8_in1_sel[2:0] $1\ALU_dec31_dec_sub8_in1_sel[2:0] + attribute \src "libresoc.v:4354.5-4354.29" + switch \initial + attribute \src "libresoc.v:4354.9-4354.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_in1_sel[2:0] 3'001 + case + assign $1\ALU_dec31_dec_sub8_in1_sel[2:0] 3'000 + end + sync always + update \ALU_dec31_dec_sub8_in1_sel $0\ALU_dec31_dec_sub8_in1_sel[2:0] + end + attribute \src "libresoc.v:4396.3-4438.6" + process $proc$libresoc.v:4396$99 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub8_in2_sel[3:0] $1\ALU_dec31_dec_sub8_in2_sel[3:0] + attribute \src "libresoc.v:4397.5-4397.29" + switch \initial + attribute \src "libresoc.v:4397.9-4397.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_in2_sel[3:0] 4'1001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_in2_sel[3:0] 4'1001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_in2_sel[3:0] 4'0000 + case + assign $1\ALU_dec31_dec_sub8_in2_sel[3:0] 4'0000 + end + sync always + update \ALU_dec31_dec_sub8_in2_sel $0\ALU_dec31_dec_sub8_in2_sel[3:0] + end + attribute \src "libresoc.v:4439.3-4481.6" + process $proc$libresoc.v:4439$100 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub8_cr_in[2:0] $1\ALU_dec31_dec_sub8_cr_in[2:0] + attribute \src "libresoc.v:4440.5-4440.29" + switch \initial + attribute \src "libresoc.v:4440.9-4440.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cr_in[2:0] 3'000 + case + assign $1\ALU_dec31_dec_sub8_cr_in[2:0] 3'000 + end + sync always + update \ALU_dec31_dec_sub8_cr_in $0\ALU_dec31_dec_sub8_cr_in[2:0] + end + attribute \src "libresoc.v:4482.3-4524.6" + process $proc$libresoc.v:4482$101 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub8_cr_out[2:0] $1\ALU_dec31_dec_sub8_cr_out[2:0] + attribute \src "libresoc.v:4483.5-4483.29" + switch \initial + attribute \src "libresoc.v:4483.9-4483.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cr_out[2:0] 3'001 + case + assign $1\ALU_dec31_dec_sub8_cr_out[2:0] 3'000 + end + sync always + update \ALU_dec31_dec_sub8_cr_out $0\ALU_dec31_dec_sub8_cr_out[2:0] + end + attribute \src "libresoc.v:4525.3-4567.6" + process $proc$libresoc.v:4525$102 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub8_ldst_len[3:0] $1\ALU_dec31_dec_sub8_ldst_len[3:0] + attribute \src "libresoc.v:4526.5-4526.29" + switch \initial + attribute \src "libresoc.v:4526.9-4526.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_ldst_len[3:0] 4'0000 + case + assign $1\ALU_dec31_dec_sub8_ldst_len[3:0] 4'0000 + end + sync always + update \ALU_dec31_dec_sub8_ldst_len $0\ALU_dec31_dec_sub8_ldst_len[3:0] + end + attribute \src "libresoc.v:4568.3-4610.6" + process $proc$libresoc.v:4568$103 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub8_rc_sel[1:0] $1\ALU_dec31_dec_sub8_rc_sel[1:0] + attribute \src "libresoc.v:4569.5-4569.29" + switch \initial + attribute \src "libresoc.v:4569.9-4569.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_rc_sel[1:0] 2'10 + case + assign $1\ALU_dec31_dec_sub8_rc_sel[1:0] 2'00 + end + sync always + update \ALU_dec31_dec_sub8_rc_sel $0\ALU_dec31_dec_sub8_rc_sel[1:0] + end + attribute \src "libresoc.v:4611.3-4653.6" + process $proc$libresoc.v:4611$104 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub8_cry_in[1:0] $1\ALU_dec31_dec_sub8_cry_in[1:0] + attribute \src "libresoc.v:4612.5-4612.29" + switch \initial + attribute \src "libresoc.v:4612.9-4612.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cry_in[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cry_in[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cry_in[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cry_in[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cry_in[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cry_in[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cry_in[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cry_in[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cry_in[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cry_in[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cry_in[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cry_in[1:0] 2'10 + case + assign $1\ALU_dec31_dec_sub8_cry_in[1:0] 2'00 + end + sync always + update \ALU_dec31_dec_sub8_cry_in $0\ALU_dec31_dec_sub8_cry_in[1:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:4659.1-4938.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_BRANCH.dec.BRANCH_dec19" +attribute \generator "nMigen" +module \BRANCH_dec19 + attribute \src "libresoc.v:4857.3-4872.6" + wire width 3 $0\BRANCH_dec19_cr_in[2:0] + attribute \src "libresoc.v:4873.3-4888.6" + wire width 3 $0\BRANCH_dec19_cr_out[2:0] + attribute \src "libresoc.v:4809.3-4824.6" + wire width 12 $0\BRANCH_dec19_function_unit[11:0] + attribute \src "libresoc.v:4841.3-4856.6" + wire width 4 $0\BRANCH_dec19_in2_sel[3:0] + attribute \src "libresoc.v:4825.3-4840.6" + wire width 7 $0\BRANCH_dec19_internal_op[6:0] + attribute \src "libresoc.v:4905.3-4920.6" + wire $0\BRANCH_dec19_is_32b[0:0] + attribute \src "libresoc.v:4921.3-4936.6" + wire $0\BRANCH_dec19_lk[0:0] + attribute \src "libresoc.v:4889.3-4904.6" + wire width 2 $0\BRANCH_dec19_rc_sel[1:0] + attribute \src "libresoc.v:4660.7-4660.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:4857.3-4872.6" + wire width 3 $1\BRANCH_dec19_cr_in[2:0] + attribute \src "libresoc.v:4873.3-4888.6" + wire width 3 $1\BRANCH_dec19_cr_out[2:0] + attribute \src "libresoc.v:4809.3-4824.6" + wire width 12 $1\BRANCH_dec19_function_unit[11:0] + attribute \src "libresoc.v:4841.3-4856.6" + wire width 4 $1\BRANCH_dec19_in2_sel[3:0] + attribute \src "libresoc.v:4825.3-4840.6" + wire width 7 $1\BRANCH_dec19_internal_op[6:0] + attribute \src "libresoc.v:4905.3-4920.6" + wire $1\BRANCH_dec19_is_32b[0:0] + attribute \src "libresoc.v:4921.3-4936.6" + wire $1\BRANCH_dec19_lk[0:0] + attribute \src "libresoc.v:4889.3-4904.6" + wire width 2 $1\BRANCH_dec19_rc_sel[1:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 4 \BRANCH_dec19_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \BRANCH_dec19_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \BRANCH_dec19_function_unit + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 3 \BRANCH_dec19_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \BRANCH_dec19_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 7 \BRANCH_dec19_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 8 \BRANCH_dec19_lk + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 6 \BRANCH_dec19_rc_sel + attribute \src "libresoc.v:4660.7-4660.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 9 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 10 \opcode_switch + attribute \src "libresoc.v:4660.7-4660.20" + process $proc$libresoc.v:4660$114 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:4809.3-4824.6" + process $proc$libresoc.v:4809$106 + assign { } { } + assign { } { } + assign $0\BRANCH_dec19_function_unit[11:0] $1\BRANCH_dec19_function_unit[11:0] + attribute \src "libresoc.v:4810.5-4810.29" + switch \initial + attribute \src "libresoc.v:4810.9-4810.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\BRANCH_dec19_function_unit[11:0] 12'000000100000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\BRANCH_dec19_function_unit[11:0] 12'000000100000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\BRANCH_dec19_function_unit[11:0] 12'000000100000 + case + assign $1\BRANCH_dec19_function_unit[11:0] 12'000000000000 + end + sync always + update \BRANCH_dec19_function_unit $0\BRANCH_dec19_function_unit[11:0] + end + attribute \src "libresoc.v:4825.3-4840.6" + process $proc$libresoc.v:4825$107 + assign { } { } + assign { } { } + assign $0\BRANCH_dec19_internal_op[6:0] $1\BRANCH_dec19_internal_op[6:0] + attribute \src "libresoc.v:4826.5-4826.29" + switch \initial + attribute \src "libresoc.v:4826.9-4826.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\BRANCH_dec19_internal_op[6:0] 7'0001000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\BRANCH_dec19_internal_op[6:0] 7'0001000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\BRANCH_dec19_internal_op[6:0] 7'0001000 + case + assign $1\BRANCH_dec19_internal_op[6:0] 7'0000000 + end + sync always + update \BRANCH_dec19_internal_op $0\BRANCH_dec19_internal_op[6:0] + end + attribute \src "libresoc.v:4841.3-4856.6" + process $proc$libresoc.v:4841$108 + assign { } { } + assign { } { } + assign $0\BRANCH_dec19_in2_sel[3:0] $1\BRANCH_dec19_in2_sel[3:0] + attribute \src "libresoc.v:4842.5-4842.29" + switch \initial + attribute \src "libresoc.v:4842.9-4842.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\BRANCH_dec19_in2_sel[3:0] 4'1100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\BRANCH_dec19_in2_sel[3:0] 4'1100 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\BRANCH_dec19_in2_sel[3:0] 4'1100 + case + assign $1\BRANCH_dec19_in2_sel[3:0] 4'0000 + end + sync always + update \BRANCH_dec19_in2_sel $0\BRANCH_dec19_in2_sel[3:0] + end + attribute \src "libresoc.v:4857.3-4872.6" + process $proc$libresoc.v:4857$109 + assign { } { } + assign { } { } + assign $0\BRANCH_dec19_cr_in[2:0] $1\BRANCH_dec19_cr_in[2:0] + attribute \src "libresoc.v:4858.5-4858.29" + switch \initial + attribute \src "libresoc.v:4858.9-4858.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\BRANCH_dec19_cr_in[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\BRANCH_dec19_cr_in[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\BRANCH_dec19_cr_in[2:0] 3'010 + case + assign $1\BRANCH_dec19_cr_in[2:0] 3'000 + end + sync always + update \BRANCH_dec19_cr_in $0\BRANCH_dec19_cr_in[2:0] + end + attribute \src "libresoc.v:4873.3-4888.6" + process $proc$libresoc.v:4873$110 + assign { } { } + assign { } { } + assign $0\BRANCH_dec19_cr_out[2:0] $1\BRANCH_dec19_cr_out[2:0] + attribute \src "libresoc.v:4874.5-4874.29" + switch \initial + attribute \src "libresoc.v:4874.9-4874.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\BRANCH_dec19_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\BRANCH_dec19_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\BRANCH_dec19_cr_out[2:0] 3'000 + case + assign $1\BRANCH_dec19_cr_out[2:0] 3'000 + end + sync always + update \BRANCH_dec19_cr_out $0\BRANCH_dec19_cr_out[2:0] + end + attribute \src "libresoc.v:4889.3-4904.6" + process $proc$libresoc.v:4889$111 + assign { } { } + assign { } { } + assign $0\BRANCH_dec19_rc_sel[1:0] $1\BRANCH_dec19_rc_sel[1:0] + attribute \src "libresoc.v:4890.5-4890.29" + switch \initial + attribute \src "libresoc.v:4890.9-4890.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\BRANCH_dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\BRANCH_dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\BRANCH_dec19_rc_sel[1:0] 2'00 + case + assign $1\BRANCH_dec19_rc_sel[1:0] 2'00 + end + sync always + update \BRANCH_dec19_rc_sel $0\BRANCH_dec19_rc_sel[1:0] + end + attribute \src "libresoc.v:4905.3-4920.6" + process $proc$libresoc.v:4905$112 + assign { } { } + assign { } { } + assign $0\BRANCH_dec19_is_32b[0:0] $1\BRANCH_dec19_is_32b[0:0] + attribute \src "libresoc.v:4906.5-4906.29" + switch \initial + attribute \src "libresoc.v:4906.9-4906.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\BRANCH_dec19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\BRANCH_dec19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\BRANCH_dec19_is_32b[0:0] 1'0 + case + assign $1\BRANCH_dec19_is_32b[0:0] 1'0 + end + sync always + update \BRANCH_dec19_is_32b $0\BRANCH_dec19_is_32b[0:0] + end + attribute \src "libresoc.v:4921.3-4936.6" + process $proc$libresoc.v:4921$113 + assign { } { } + assign { } { } + assign $0\BRANCH_dec19_lk[0:0] $1\BRANCH_dec19_lk[0:0] + attribute \src "libresoc.v:4922.5-4922.29" + switch \initial + attribute \src "libresoc.v:4922.9-4922.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\BRANCH_dec19_lk[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\BRANCH_dec19_lk[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\BRANCH_dec19_lk[0:0] 1'1 + case + assign $1\BRANCH_dec19_lk[0:0] 1'0 + end + sync always + update \BRANCH_dec19_lk $0\BRANCH_dec19_lk[0:0] + end + connect \opcode_switch \opcode_in [10:1] +end +attribute \src "libresoc.v:4942.1-5239.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_CR.dec.CR_dec19" +attribute \generator "nMigen" +module \CR_dec19 + attribute \src "libresoc.v:5136.3-5169.6" + wire width 3 $0\CR_dec19_cr_in[2:0] + attribute \src "libresoc.v:5170.3-5203.6" + wire width 3 $0\CR_dec19_cr_out[2:0] + attribute \src "libresoc.v:5068.3-5101.6" + wire width 12 $0\CR_dec19_function_unit[11:0] + attribute \src "libresoc.v:5102.3-5135.6" + wire width 7 $0\CR_dec19_internal_op[6:0] + attribute \src "libresoc.v:5204.3-5237.6" + wire width 2 $0\CR_dec19_rc_sel[1:0] + attribute \src "libresoc.v:4943.7-4943.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:5136.3-5169.6" + wire width 3 $1\CR_dec19_cr_in[2:0] + attribute \src "libresoc.v:5170.3-5203.6" + wire width 3 $1\CR_dec19_cr_out[2:0] + attribute \src "libresoc.v:5068.3-5101.6" + wire width 12 $1\CR_dec19_function_unit[11:0] + attribute \src "libresoc.v:5102.3-5135.6" + wire width 7 $1\CR_dec19_internal_op[6:0] + attribute \src "libresoc.v:5204.3-5237.6" + wire width 2 $1\CR_dec19_rc_sel[1:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 3 \CR_dec19_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 4 \CR_dec19_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \CR_dec19_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \CR_dec19_internal_op + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 5 \CR_dec19_rc_sel + attribute \src "libresoc.v:4943.7-4943.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 6 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 10 \opcode_switch + attribute \src "libresoc.v:4943.7-4943.20" + process $proc$libresoc.v:4943$120 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:5068.3-5101.6" + process $proc$libresoc.v:5068$115 + assign { } { } + assign { } { } + assign $0\CR_dec19_function_unit[11:0] $1\CR_dec19_function_unit[11:0] + attribute \src "libresoc.v:5069.5-5069.29" + switch \initial + attribute \src "libresoc.v:5069.9-5069.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\CR_dec19_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\CR_dec19_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\CR_dec19_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\CR_dec19_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\CR_dec19_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\CR_dec19_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\CR_dec19_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\CR_dec19_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\CR_dec19_function_unit[11:0] 12'000001000000 + case + assign $1\CR_dec19_function_unit[11:0] 12'000000000000 + end + sync always + update \CR_dec19_function_unit $0\CR_dec19_function_unit[11:0] + end + attribute \src "libresoc.v:5102.3-5135.6" + process $proc$libresoc.v:5102$116 + assign { } { } + assign { } { } + assign $0\CR_dec19_internal_op[6:0] $1\CR_dec19_internal_op[6:0] + attribute \src "libresoc.v:5103.5-5103.29" + switch \initial + attribute \src "libresoc.v:5103.9-5103.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\CR_dec19_internal_op[6:0] 7'0101010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\CR_dec19_internal_op[6:0] 7'1000101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\CR_dec19_internal_op[6:0] 7'1000101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\CR_dec19_internal_op[6:0] 7'1000101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\CR_dec19_internal_op[6:0] 7'1000101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\CR_dec19_internal_op[6:0] 7'1000101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\CR_dec19_internal_op[6:0] 7'1000101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\CR_dec19_internal_op[6:0] 7'1000101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\CR_dec19_internal_op[6:0] 7'1000101 + case + assign $1\CR_dec19_internal_op[6:0] 7'0000000 + end + sync always + update \CR_dec19_internal_op $0\CR_dec19_internal_op[6:0] + end + attribute \src "libresoc.v:5136.3-5169.6" + process $proc$libresoc.v:5136$117 + assign { } { } + assign { } { } + assign $0\CR_dec19_cr_in[2:0] $1\CR_dec19_cr_in[2:0] + attribute \src "libresoc.v:5137.5-5137.29" + switch \initial + attribute \src "libresoc.v:5137.9-5137.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\CR_dec19_cr_in[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\CR_dec19_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\CR_dec19_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\CR_dec19_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\CR_dec19_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\CR_dec19_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\CR_dec19_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\CR_dec19_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\CR_dec19_cr_in[2:0] 3'100 + case + assign $1\CR_dec19_cr_in[2:0] 3'000 + end + sync always + update \CR_dec19_cr_in $0\CR_dec19_cr_in[2:0] + end + attribute \src "libresoc.v:5170.3-5203.6" + process $proc$libresoc.v:5170$118 + assign { } { } + assign { } { } + assign $0\CR_dec19_cr_out[2:0] $1\CR_dec19_cr_out[2:0] + attribute \src "libresoc.v:5171.5-5171.29" + switch \initial + attribute \src "libresoc.v:5171.9-5171.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\CR_dec19_cr_out[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\CR_dec19_cr_out[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\CR_dec19_cr_out[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\CR_dec19_cr_out[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\CR_dec19_cr_out[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\CR_dec19_cr_out[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\CR_dec19_cr_out[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\CR_dec19_cr_out[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\CR_dec19_cr_out[2:0] 3'011 + case + assign $1\CR_dec19_cr_out[2:0] 3'000 + end + sync always + update \CR_dec19_cr_out $0\CR_dec19_cr_out[2:0] + end + attribute \src "libresoc.v:5204.3-5237.6" + process $proc$libresoc.v:5204$119 + assign { } { } + assign { } { } + assign $0\CR_dec19_rc_sel[1:0] $1\CR_dec19_rc_sel[1:0] + attribute \src "libresoc.v:5205.5-5205.29" + switch \initial + attribute \src "libresoc.v:5205.9-5205.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\CR_dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\CR_dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\CR_dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\CR_dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\CR_dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\CR_dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\CR_dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\CR_dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\CR_dec19_rc_sel[1:0] 2'00 + case + assign $1\CR_dec19_rc_sel[1:0] 2'00 + end + sync always + update \CR_dec19_rc_sel $0\CR_dec19_rc_sel[1:0] + end + connect \opcode_switch \opcode_in [10:1] +end +attribute \src "libresoc.v:5243.1-5972.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_CR.dec.CR_dec31" +attribute \generator "nMigen" +module \CR_dec31 + attribute \src "libresoc.v:5928.3-5946.6" + wire width 3 $0\CR_dec31_cr_in[2:0] + attribute \src "libresoc.v:5947.3-5965.6" + wire width 3 $0\CR_dec31_cr_out[2:0] + attribute \src "libresoc.v:5890.3-5908.6" + wire width 12 $0\CR_dec31_function_unit[11:0] + attribute \src "libresoc.v:5909.3-5927.6" + wire width 7 $0\CR_dec31_internal_op[6:0] + attribute \src "libresoc.v:5871.3-5889.6" + wire width 2 $0\CR_dec31_rc_sel[1:0] + attribute \src "libresoc.v:5244.7-5244.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:5928.3-5946.6" + wire width 3 $1\CR_dec31_cr_in[2:0] + attribute \src "libresoc.v:5947.3-5965.6" + wire width 3 $1\CR_dec31_cr_out[2:0] + attribute \src "libresoc.v:5890.3-5908.6" + wire width 12 $1\CR_dec31_function_unit[11:0] + attribute \src "libresoc.v:5909.3-5927.6" + wire width 7 $1\CR_dec31_internal_op[6:0] + attribute \src "libresoc.v:5871.3-5889.6" + wire width 2 $1\CR_dec31_rc_sel[1:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 3 \CR_dec31_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 4 \CR_dec31_cr_out + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \CR_dec31_dec_sub0_CR_dec31_dec_sub0_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \CR_dec31_dec_sub0_CR_dec31_dec_sub0_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \CR_dec31_dec_sub0_CR_dec31_dec_sub0_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 \CR_dec31_dec_sub0_CR_dec31_dec_sub0_internal_op + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \CR_dec31_dec_sub0_CR_dec31_dec_sub0_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \CR_dec31_dec_sub0_opcode_in + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \CR_dec31_dec_sub15_CR_dec31_dec_sub15_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \CR_dec31_dec_sub15_CR_dec31_dec_sub15_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \CR_dec31_dec_sub15_CR_dec31_dec_sub15_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 \CR_dec31_dec_sub15_CR_dec31_dec_sub15_internal_op + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \CR_dec31_dec_sub15_CR_dec31_dec_sub15_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \CR_dec31_dec_sub15_opcode_in + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \CR_dec31_dec_sub16_CR_dec31_dec_sub16_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \CR_dec31_dec_sub16_CR_dec31_dec_sub16_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \CR_dec31_dec_sub16_CR_dec31_dec_sub16_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 \CR_dec31_dec_sub16_CR_dec31_dec_sub16_internal_op + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \CR_dec31_dec_sub16_CR_dec31_dec_sub16_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \CR_dec31_dec_sub16_opcode_in + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \CR_dec31_dec_sub19_CR_dec31_dec_sub19_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \CR_dec31_dec_sub19_CR_dec31_dec_sub19_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \CR_dec31_dec_sub19_CR_dec31_dec_sub19_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 \CR_dec31_dec_sub19_CR_dec31_dec_sub19_internal_op + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \CR_dec31_dec_sub19_CR_dec31_dec_sub19_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \CR_dec31_dec_sub19_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \CR_dec31_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \CR_dec31_internal_op + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 5 \CR_dec31_rc_sel + attribute \src "libresoc.v:5244.7-5244.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:326" + wire width 5 \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 6 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 10 \opcode_switch + attribute \module_not_derived 1 + attribute \src "libresoc.v:5839.21-5846.4" + cell \CR_dec31_dec_sub0 \CR_dec31_dec_sub0 + connect \CR_dec31_dec_sub0_cr_in \CR_dec31_dec_sub0_CR_dec31_dec_sub0_cr_in + connect \CR_dec31_dec_sub0_cr_out \CR_dec31_dec_sub0_CR_dec31_dec_sub0_cr_out + connect \CR_dec31_dec_sub0_function_unit \CR_dec31_dec_sub0_CR_dec31_dec_sub0_function_unit + connect \CR_dec31_dec_sub0_internal_op \CR_dec31_dec_sub0_CR_dec31_dec_sub0_internal_op + connect \CR_dec31_dec_sub0_rc_sel \CR_dec31_dec_sub0_CR_dec31_dec_sub0_rc_sel + connect \opcode_in \CR_dec31_dec_sub0_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:5847.22-5854.4" + cell \CR_dec31_dec_sub15 \CR_dec31_dec_sub15 + connect \CR_dec31_dec_sub15_cr_in \CR_dec31_dec_sub15_CR_dec31_dec_sub15_cr_in + connect \CR_dec31_dec_sub15_cr_out \CR_dec31_dec_sub15_CR_dec31_dec_sub15_cr_out + connect \CR_dec31_dec_sub15_function_unit \CR_dec31_dec_sub15_CR_dec31_dec_sub15_function_unit + connect \CR_dec31_dec_sub15_internal_op \CR_dec31_dec_sub15_CR_dec31_dec_sub15_internal_op + connect \CR_dec31_dec_sub15_rc_sel \CR_dec31_dec_sub15_CR_dec31_dec_sub15_rc_sel + connect \opcode_in \CR_dec31_dec_sub15_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:5855.22-5862.4" + cell \CR_dec31_dec_sub16 \CR_dec31_dec_sub16 + connect \CR_dec31_dec_sub16_cr_in \CR_dec31_dec_sub16_CR_dec31_dec_sub16_cr_in + connect \CR_dec31_dec_sub16_cr_out \CR_dec31_dec_sub16_CR_dec31_dec_sub16_cr_out + connect \CR_dec31_dec_sub16_function_unit \CR_dec31_dec_sub16_CR_dec31_dec_sub16_function_unit + connect \CR_dec31_dec_sub16_internal_op \CR_dec31_dec_sub16_CR_dec31_dec_sub16_internal_op + connect \CR_dec31_dec_sub16_rc_sel \CR_dec31_dec_sub16_CR_dec31_dec_sub16_rc_sel + connect \opcode_in \CR_dec31_dec_sub16_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:5863.22-5870.4" + cell \CR_dec31_dec_sub19 \CR_dec31_dec_sub19 + connect \CR_dec31_dec_sub19_cr_in \CR_dec31_dec_sub19_CR_dec31_dec_sub19_cr_in + connect \CR_dec31_dec_sub19_cr_out \CR_dec31_dec_sub19_CR_dec31_dec_sub19_cr_out + connect \CR_dec31_dec_sub19_function_unit \CR_dec31_dec_sub19_CR_dec31_dec_sub19_function_unit + connect \CR_dec31_dec_sub19_internal_op \CR_dec31_dec_sub19_CR_dec31_dec_sub19_internal_op + connect \CR_dec31_dec_sub19_rc_sel \CR_dec31_dec_sub19_CR_dec31_dec_sub19_rc_sel + connect \opcode_in \CR_dec31_dec_sub19_opcode_in + end + attribute \src "libresoc.v:5244.7-5244.20" + process $proc$libresoc.v:5244$126 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:5871.3-5889.6" + process $proc$libresoc.v:5871$121 + assign { } { } + assign { } { } + assign $0\CR_dec31_rc_sel[1:0] $1\CR_dec31_rc_sel[1:0] + attribute \src "libresoc.v:5872.5-5872.29" + switch \initial + attribute \src "libresoc.v:5872.9-5872.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\CR_dec31_rc_sel[1:0] \CR_dec31_dec_sub0_CR_dec31_dec_sub0_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\CR_dec31_rc_sel[1:0] \CR_dec31_dec_sub19_CR_dec31_dec_sub19_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\CR_dec31_rc_sel[1:0] \CR_dec31_dec_sub15_CR_dec31_dec_sub15_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\CR_dec31_rc_sel[1:0] \CR_dec31_dec_sub16_CR_dec31_dec_sub16_rc_sel + case + assign $1\CR_dec31_rc_sel[1:0] 2'00 + end + sync always + update \CR_dec31_rc_sel $0\CR_dec31_rc_sel[1:0] + end + attribute \src "libresoc.v:5890.3-5908.6" + process $proc$libresoc.v:5890$122 + assign { } { } + assign { } { } + assign $0\CR_dec31_function_unit[11:0] $1\CR_dec31_function_unit[11:0] + attribute \src "libresoc.v:5891.5-5891.29" + switch \initial + attribute \src "libresoc.v:5891.9-5891.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\CR_dec31_function_unit[11:0] \CR_dec31_dec_sub0_CR_dec31_dec_sub0_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\CR_dec31_function_unit[11:0] \CR_dec31_dec_sub19_CR_dec31_dec_sub19_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\CR_dec31_function_unit[11:0] \CR_dec31_dec_sub15_CR_dec31_dec_sub15_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\CR_dec31_function_unit[11:0] \CR_dec31_dec_sub16_CR_dec31_dec_sub16_function_unit + case + assign $1\CR_dec31_function_unit[11:0] 12'000000000000 + end + sync always + update \CR_dec31_function_unit $0\CR_dec31_function_unit[11:0] + end + attribute \src "libresoc.v:5909.3-5927.6" + process $proc$libresoc.v:5909$123 + assign { } { } + assign { } { } + assign $0\CR_dec31_internal_op[6:0] $1\CR_dec31_internal_op[6:0] + attribute \src "libresoc.v:5910.5-5910.29" + switch \initial + attribute \src "libresoc.v:5910.9-5910.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\CR_dec31_internal_op[6:0] \CR_dec31_dec_sub0_CR_dec31_dec_sub0_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\CR_dec31_internal_op[6:0] \CR_dec31_dec_sub19_CR_dec31_dec_sub19_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\CR_dec31_internal_op[6:0] \CR_dec31_dec_sub15_CR_dec31_dec_sub15_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\CR_dec31_internal_op[6:0] \CR_dec31_dec_sub16_CR_dec31_dec_sub16_internal_op + case + assign $1\CR_dec31_internal_op[6:0] 7'0000000 + end + sync always + update \CR_dec31_internal_op $0\CR_dec31_internal_op[6:0] + end + attribute \src "libresoc.v:5928.3-5946.6" + process $proc$libresoc.v:5928$124 + assign { } { } + assign { } { } + assign $0\CR_dec31_cr_in[2:0] $1\CR_dec31_cr_in[2:0] + attribute \src "libresoc.v:5929.5-5929.29" + switch \initial + attribute \src "libresoc.v:5929.9-5929.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\CR_dec31_cr_in[2:0] \CR_dec31_dec_sub0_CR_dec31_dec_sub0_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\CR_dec31_cr_in[2:0] \CR_dec31_dec_sub19_CR_dec31_dec_sub19_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\CR_dec31_cr_in[2:0] \CR_dec31_dec_sub15_CR_dec31_dec_sub15_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\CR_dec31_cr_in[2:0] \CR_dec31_dec_sub16_CR_dec31_dec_sub16_cr_in + case + assign $1\CR_dec31_cr_in[2:0] 3'000 + end + sync always + update \CR_dec31_cr_in $0\CR_dec31_cr_in[2:0] + end + attribute \src "libresoc.v:5947.3-5965.6" + process $proc$libresoc.v:5947$125 + assign { } { } + assign { } { } + assign $0\CR_dec31_cr_out[2:0] $1\CR_dec31_cr_out[2:0] + attribute \src "libresoc.v:5948.5-5948.29" + switch \initial + attribute \src "libresoc.v:5948.9-5948.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\CR_dec31_cr_out[2:0] \CR_dec31_dec_sub0_CR_dec31_dec_sub0_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\CR_dec31_cr_out[2:0] \CR_dec31_dec_sub19_CR_dec31_dec_sub19_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\CR_dec31_cr_out[2:0] \CR_dec31_dec_sub15_CR_dec31_dec_sub15_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\CR_dec31_cr_out[2:0] \CR_dec31_dec_sub16_CR_dec31_dec_sub16_cr_out + case + assign $1\CR_dec31_cr_out[2:0] 3'000 + end + sync always + update \CR_dec31_cr_out $0\CR_dec31_cr_out[2:0] + end + connect \CR_dec31_dec_sub16_opcode_in \opcode_in + connect \CR_dec31_dec_sub15_opcode_in \opcode_in + connect \CR_dec31_dec_sub19_opcode_in \opcode_in + connect \CR_dec31_dec_sub0_opcode_in \opcode_in + connect \opc_in \opcode_switch [4:0] + connect \opcode_switch \opcode_in [10:1] +end +attribute \src "libresoc.v:5976.1-6153.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_CR.dec.CR_dec31.CR_dec31_dec_sub0" +attribute \generator "nMigen" +module \CR_dec31_dec_sub0 + attribute \src "libresoc.v:6122.3-6131.6" + wire width 3 $0\CR_dec31_dec_sub0_cr_in[2:0] + attribute \src "libresoc.v:6132.3-6141.6" + wire width 3 $0\CR_dec31_dec_sub0_cr_out[2:0] + attribute \src "libresoc.v:6102.3-6111.6" + wire width 12 $0\CR_dec31_dec_sub0_function_unit[11:0] + attribute \src "libresoc.v:6112.3-6121.6" + wire width 7 $0\CR_dec31_dec_sub0_internal_op[6:0] + attribute \src "libresoc.v:6142.3-6151.6" + wire width 2 $0\CR_dec31_dec_sub0_rc_sel[1:0] + attribute \src "libresoc.v:5977.7-5977.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:6122.3-6131.6" + wire width 3 $1\CR_dec31_dec_sub0_cr_in[2:0] + attribute \src "libresoc.v:6132.3-6141.6" + wire width 3 $1\CR_dec31_dec_sub0_cr_out[2:0] + attribute \src "libresoc.v:6102.3-6111.6" + wire width 12 $1\CR_dec31_dec_sub0_function_unit[11:0] + attribute \src "libresoc.v:6112.3-6121.6" + wire width 7 $1\CR_dec31_dec_sub0_internal_op[6:0] + attribute \src "libresoc.v:6142.3-6151.6" + wire width 2 $1\CR_dec31_dec_sub0_rc_sel[1:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 3 \CR_dec31_dec_sub0_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 4 \CR_dec31_dec_sub0_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \CR_dec31_dec_sub0_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \CR_dec31_dec_sub0_internal_op + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 5 \CR_dec31_dec_sub0_rc_sel + attribute \src "libresoc.v:5977.7-5977.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 6 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 5 \opcode_switch + attribute \src "libresoc.v:5977.7-5977.20" + process $proc$libresoc.v:5977$132 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:6102.3-6111.6" + process $proc$libresoc.v:6102$127 + assign { } { } + assign { } { } + assign $0\CR_dec31_dec_sub0_function_unit[11:0] $1\CR_dec31_dec_sub0_function_unit[11:0] + attribute \src "libresoc.v:6103.5-6103.29" + switch \initial + attribute \src "libresoc.v:6103.9-6103.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\CR_dec31_dec_sub0_function_unit[11:0] 12'000001000000 + case + assign $1\CR_dec31_dec_sub0_function_unit[11:0] 12'000000000000 + end + sync always + update \CR_dec31_dec_sub0_function_unit $0\CR_dec31_dec_sub0_function_unit[11:0] + end + attribute \src "libresoc.v:6112.3-6121.6" + process $proc$libresoc.v:6112$128 + assign { } { } + assign { } { } + assign $0\CR_dec31_dec_sub0_internal_op[6:0] $1\CR_dec31_dec_sub0_internal_op[6:0] + attribute \src "libresoc.v:6113.5-6113.29" + switch \initial + attribute \src "libresoc.v:6113.9-6113.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\CR_dec31_dec_sub0_internal_op[6:0] 7'0111011 + case + assign $1\CR_dec31_dec_sub0_internal_op[6:0] 7'0000000 + end + sync always + update \CR_dec31_dec_sub0_internal_op $0\CR_dec31_dec_sub0_internal_op[6:0] + end + attribute \src "libresoc.v:6122.3-6131.6" + process $proc$libresoc.v:6122$129 + assign { } { } + assign { } { } + assign $0\CR_dec31_dec_sub0_cr_in[2:0] $1\CR_dec31_dec_sub0_cr_in[2:0] + attribute \src "libresoc.v:6123.5-6123.29" + switch \initial + attribute \src "libresoc.v:6123.9-6123.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\CR_dec31_dec_sub0_cr_in[2:0] 3'011 + case + assign $1\CR_dec31_dec_sub0_cr_in[2:0] 3'000 + end + sync always + update \CR_dec31_dec_sub0_cr_in $0\CR_dec31_dec_sub0_cr_in[2:0] + end + attribute \src "libresoc.v:6132.3-6141.6" + process $proc$libresoc.v:6132$130 + assign { } { } + assign { } { } + assign $0\CR_dec31_dec_sub0_cr_out[2:0] $1\CR_dec31_dec_sub0_cr_out[2:0] + attribute \src "libresoc.v:6133.5-6133.29" + switch \initial + attribute \src "libresoc.v:6133.9-6133.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\CR_dec31_dec_sub0_cr_out[2:0] 3'000 + case + assign $1\CR_dec31_dec_sub0_cr_out[2:0] 3'000 + end + sync always + update \CR_dec31_dec_sub0_cr_out $0\CR_dec31_dec_sub0_cr_out[2:0] + end + attribute \src "libresoc.v:6142.3-6151.6" + process $proc$libresoc.v:6142$131 + assign { } { } + assign { } { } + assign $0\CR_dec31_dec_sub0_rc_sel[1:0] $1\CR_dec31_dec_sub0_rc_sel[1:0] + attribute \src "libresoc.v:6143.5-6143.29" + switch \initial + attribute \src "libresoc.v:6143.9-6143.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\CR_dec31_dec_sub0_rc_sel[1:0] 2'00 + case + assign $1\CR_dec31_dec_sub0_rc_sel[1:0] 2'00 + end + sync always + update \CR_dec31_dec_sub0_rc_sel $0\CR_dec31_dec_sub0_rc_sel[1:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:6157.1-6799.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_CR.dec.CR_dec31.CR_dec31_dec_sub15" +attribute \generator "nMigen" +module \CR_dec31_dec_sub15 + attribute \src "libresoc.v:6489.3-6591.6" + wire width 3 $0\CR_dec31_dec_sub15_cr_in[2:0] + attribute \src "libresoc.v:6592.3-6694.6" + wire width 3 $0\CR_dec31_dec_sub15_cr_out[2:0] + attribute \src "libresoc.v:6283.3-6385.6" + wire width 12 $0\CR_dec31_dec_sub15_function_unit[11:0] + attribute \src "libresoc.v:6386.3-6488.6" + wire width 7 $0\CR_dec31_dec_sub15_internal_op[6:0] + attribute \src "libresoc.v:6695.3-6797.6" + wire width 2 $0\CR_dec31_dec_sub15_rc_sel[1:0] + attribute \src "libresoc.v:6158.7-6158.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:6489.3-6591.6" + wire width 3 $1\CR_dec31_dec_sub15_cr_in[2:0] + attribute \src "libresoc.v:6592.3-6694.6" + wire width 3 $1\CR_dec31_dec_sub15_cr_out[2:0] + attribute \src "libresoc.v:6283.3-6385.6" + wire width 12 $1\CR_dec31_dec_sub15_function_unit[11:0] + attribute \src "libresoc.v:6386.3-6488.6" + wire width 7 $1\CR_dec31_dec_sub15_internal_op[6:0] + attribute \src "libresoc.v:6695.3-6797.6" + wire width 2 $1\CR_dec31_dec_sub15_rc_sel[1:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 3 \CR_dec31_dec_sub15_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 4 \CR_dec31_dec_sub15_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \CR_dec31_dec_sub15_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \CR_dec31_dec_sub15_internal_op + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 5 \CR_dec31_dec_sub15_rc_sel + attribute \src "libresoc.v:6158.7-6158.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 6 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 5 \opcode_switch + attribute \src "libresoc.v:6158.7-6158.20" + process $proc$libresoc.v:6158$138 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:6283.3-6385.6" + process $proc$libresoc.v:6283$133 + assign { } { } + assign { } { } + assign $0\CR_dec31_dec_sub15_function_unit[11:0] $1\CR_dec31_dec_sub15_function_unit[11:0] + attribute \src "libresoc.v:6284.5-6284.29" + switch \initial + attribute \src "libresoc.v:6284.9-6284.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 + case + assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000000000000 + end + sync always + update \CR_dec31_dec_sub15_function_unit $0\CR_dec31_dec_sub15_function_unit[11:0] + end + attribute \src "libresoc.v:6386.3-6488.6" + process $proc$libresoc.v:6386$134 + assign { } { } + assign { } { } + assign $0\CR_dec31_dec_sub15_internal_op[6:0] $1\CR_dec31_dec_sub15_internal_op[6:0] + attribute \src "libresoc.v:6387.5-6387.29" + switch \initial + attribute \src "libresoc.v:6387.9-6387.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + case + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0000000 + end + sync always + update \CR_dec31_dec_sub15_internal_op $0\CR_dec31_dec_sub15_internal_op[6:0] + end + attribute \src "libresoc.v:6489.3-6591.6" + process $proc$libresoc.v:6489$135 + assign { } { } + assign { } { } + assign $0\CR_dec31_dec_sub15_cr_in[2:0] $1\CR_dec31_dec_sub15_cr_in[2:0] + attribute \src "libresoc.v:6490.5-6490.29" + switch \initial + attribute \src "libresoc.v:6490.9-6490.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + case + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'000 + end + sync always + update \CR_dec31_dec_sub15_cr_in $0\CR_dec31_dec_sub15_cr_in[2:0] + end + attribute \src "libresoc.v:6592.3-6694.6" + process $proc$libresoc.v:6592$136 + assign { } { } + assign { } { } + assign $0\CR_dec31_dec_sub15_cr_out[2:0] $1\CR_dec31_dec_sub15_cr_out[2:0] + attribute \src "libresoc.v:6593.5-6593.29" + switch \initial + attribute \src "libresoc.v:6593.9-6593.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + case + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + end + sync always + update \CR_dec31_dec_sub15_cr_out $0\CR_dec31_dec_sub15_cr_out[2:0] + end + attribute \src "libresoc.v:6695.3-6797.6" + process $proc$libresoc.v:6695$137 + assign { } { } + assign { } { } + assign $0\CR_dec31_dec_sub15_rc_sel[1:0] $1\CR_dec31_dec_sub15_rc_sel[1:0] + attribute \src "libresoc.v:6696.5-6696.29" + switch \initial + attribute \src "libresoc.v:6696.9-6696.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + case + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + end + sync always + update \CR_dec31_dec_sub15_rc_sel $0\CR_dec31_dec_sub15_rc_sel[1:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:6803.1-6980.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_CR.dec.CR_dec31.CR_dec31_dec_sub16" +attribute \generator "nMigen" +module \CR_dec31_dec_sub16 + attribute \src "libresoc.v:6949.3-6958.6" + wire width 3 $0\CR_dec31_dec_sub16_cr_in[2:0] + attribute \src "libresoc.v:6959.3-6968.6" + wire width 3 $0\CR_dec31_dec_sub16_cr_out[2:0] + attribute \src "libresoc.v:6929.3-6938.6" + wire width 12 $0\CR_dec31_dec_sub16_function_unit[11:0] + attribute \src "libresoc.v:6939.3-6948.6" + wire width 7 $0\CR_dec31_dec_sub16_internal_op[6:0] + attribute \src "libresoc.v:6969.3-6978.6" + wire width 2 $0\CR_dec31_dec_sub16_rc_sel[1:0] + attribute \src "libresoc.v:6804.7-6804.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:6949.3-6958.6" + wire width 3 $1\CR_dec31_dec_sub16_cr_in[2:0] + attribute \src "libresoc.v:6959.3-6968.6" + wire width 3 $1\CR_dec31_dec_sub16_cr_out[2:0] + attribute \src "libresoc.v:6929.3-6938.6" + wire width 12 $1\CR_dec31_dec_sub16_function_unit[11:0] + attribute \src "libresoc.v:6939.3-6948.6" + wire width 7 $1\CR_dec31_dec_sub16_internal_op[6:0] + attribute \src "libresoc.v:6969.3-6978.6" + wire width 2 $1\CR_dec31_dec_sub16_rc_sel[1:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 3 \CR_dec31_dec_sub16_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 4 \CR_dec31_dec_sub16_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \CR_dec31_dec_sub16_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \CR_dec31_dec_sub16_internal_op + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 5 \CR_dec31_dec_sub16_rc_sel + attribute \src "libresoc.v:6804.7-6804.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 6 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 5 \opcode_switch + attribute \src "libresoc.v:6804.7-6804.20" + process $proc$libresoc.v:6804$144 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:6929.3-6938.6" + process $proc$libresoc.v:6929$139 + assign { } { } + assign { } { } + assign $0\CR_dec31_dec_sub16_function_unit[11:0] $1\CR_dec31_dec_sub16_function_unit[11:0] + attribute \src "libresoc.v:6930.5-6930.29" + switch \initial + attribute \src "libresoc.v:6930.9-6930.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\CR_dec31_dec_sub16_function_unit[11:0] 12'000001000000 + case + assign $1\CR_dec31_dec_sub16_function_unit[11:0] 12'000000000000 + end + sync always + update \CR_dec31_dec_sub16_function_unit $0\CR_dec31_dec_sub16_function_unit[11:0] + end + attribute \src "libresoc.v:6939.3-6948.6" + process $proc$libresoc.v:6939$140 + assign { } { } + assign { } { } + assign $0\CR_dec31_dec_sub16_internal_op[6:0] $1\CR_dec31_dec_sub16_internal_op[6:0] + attribute \src "libresoc.v:6940.5-6940.29" + switch \initial + attribute \src "libresoc.v:6940.9-6940.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\CR_dec31_dec_sub16_internal_op[6:0] 7'0110000 + case + assign $1\CR_dec31_dec_sub16_internal_op[6:0] 7'0000000 + end + sync always + update \CR_dec31_dec_sub16_internal_op $0\CR_dec31_dec_sub16_internal_op[6:0] + end + attribute \src "libresoc.v:6949.3-6958.6" + process $proc$libresoc.v:6949$141 + assign { } { } + assign { } { } + assign $0\CR_dec31_dec_sub16_cr_in[2:0] $1\CR_dec31_dec_sub16_cr_in[2:0] + attribute \src "libresoc.v:6950.5-6950.29" + switch \initial + attribute \src "libresoc.v:6950.9-6950.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\CR_dec31_dec_sub16_cr_in[2:0] 3'110 + case + assign $1\CR_dec31_dec_sub16_cr_in[2:0] 3'000 + end + sync always + update \CR_dec31_dec_sub16_cr_in $0\CR_dec31_dec_sub16_cr_in[2:0] + end + attribute \src "libresoc.v:6959.3-6968.6" + process $proc$libresoc.v:6959$142 + assign { } { } + assign { } { } + assign $0\CR_dec31_dec_sub16_cr_out[2:0] $1\CR_dec31_dec_sub16_cr_out[2:0] + attribute \src "libresoc.v:6960.5-6960.29" + switch \initial + attribute \src "libresoc.v:6960.9-6960.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\CR_dec31_dec_sub16_cr_out[2:0] 3'100 + case + assign $1\CR_dec31_dec_sub16_cr_out[2:0] 3'000 + end + sync always + update \CR_dec31_dec_sub16_cr_out $0\CR_dec31_dec_sub16_cr_out[2:0] + end + attribute \src "libresoc.v:6969.3-6978.6" + process $proc$libresoc.v:6969$143 + assign { } { } + assign { } { } + assign $0\CR_dec31_dec_sub16_rc_sel[1:0] $1\CR_dec31_dec_sub16_rc_sel[1:0] + attribute \src "libresoc.v:6970.5-6970.29" + switch \initial + attribute \src "libresoc.v:6970.9-6970.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\CR_dec31_dec_sub16_rc_sel[1:0] 2'00 + case + assign $1\CR_dec31_dec_sub16_rc_sel[1:0] 2'00 + end + sync always + update \CR_dec31_dec_sub16_rc_sel $0\CR_dec31_dec_sub16_rc_sel[1:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:6984.1-7161.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_CR.dec.CR_dec31.CR_dec31_dec_sub19" +attribute \generator "nMigen" +module \CR_dec31_dec_sub19 + attribute \src "libresoc.v:7130.3-7139.6" + wire width 3 $0\CR_dec31_dec_sub19_cr_in[2:0] + attribute \src "libresoc.v:7140.3-7149.6" + wire width 3 $0\CR_dec31_dec_sub19_cr_out[2:0] + attribute \src "libresoc.v:7110.3-7119.6" + wire width 12 $0\CR_dec31_dec_sub19_function_unit[11:0] + attribute \src "libresoc.v:7120.3-7129.6" + wire width 7 $0\CR_dec31_dec_sub19_internal_op[6:0] + attribute \src "libresoc.v:7150.3-7159.6" + wire width 2 $0\CR_dec31_dec_sub19_rc_sel[1:0] + attribute \src "libresoc.v:6985.7-6985.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:7130.3-7139.6" + wire width 3 $1\CR_dec31_dec_sub19_cr_in[2:0] + attribute \src "libresoc.v:7140.3-7149.6" + wire width 3 $1\CR_dec31_dec_sub19_cr_out[2:0] + attribute \src "libresoc.v:7110.3-7119.6" + wire width 12 $1\CR_dec31_dec_sub19_function_unit[11:0] + attribute \src "libresoc.v:7120.3-7129.6" + wire width 7 $1\CR_dec31_dec_sub19_internal_op[6:0] + attribute \src "libresoc.v:7150.3-7159.6" + wire width 2 $1\CR_dec31_dec_sub19_rc_sel[1:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 3 \CR_dec31_dec_sub19_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 4 \CR_dec31_dec_sub19_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \CR_dec31_dec_sub19_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \CR_dec31_dec_sub19_internal_op + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 5 \CR_dec31_dec_sub19_rc_sel + attribute \src "libresoc.v:6985.7-6985.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 6 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 5 \opcode_switch + attribute \src "libresoc.v:6985.7-6985.20" + process $proc$libresoc.v:6985$150 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:7110.3-7119.6" + process $proc$libresoc.v:7110$145 + assign { } { } + assign { } { } + assign $0\CR_dec31_dec_sub19_function_unit[11:0] $1\CR_dec31_dec_sub19_function_unit[11:0] + attribute \src "libresoc.v:7111.5-7111.29" + switch \initial + attribute \src "libresoc.v:7111.9-7111.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\CR_dec31_dec_sub19_function_unit[11:0] 12'000001000000 + case + assign $1\CR_dec31_dec_sub19_function_unit[11:0] 12'000000000000 + end + sync always + update \CR_dec31_dec_sub19_function_unit $0\CR_dec31_dec_sub19_function_unit[11:0] + end + attribute \src "libresoc.v:7120.3-7129.6" + process $proc$libresoc.v:7120$146 + assign { } { } + assign { } { } + assign $0\CR_dec31_dec_sub19_internal_op[6:0] $1\CR_dec31_dec_sub19_internal_op[6:0] + attribute \src "libresoc.v:7121.5-7121.29" + switch \initial + attribute \src "libresoc.v:7121.9-7121.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\CR_dec31_dec_sub19_internal_op[6:0] 7'0101101 + case + assign $1\CR_dec31_dec_sub19_internal_op[6:0] 7'0000000 + end + sync always + update \CR_dec31_dec_sub19_internal_op $0\CR_dec31_dec_sub19_internal_op[6:0] + end + attribute \src "libresoc.v:7130.3-7139.6" + process $proc$libresoc.v:7130$147 + assign { } { } + assign { } { } + assign $0\CR_dec31_dec_sub19_cr_in[2:0] $1\CR_dec31_dec_sub19_cr_in[2:0] + attribute \src "libresoc.v:7131.5-7131.29" + switch \initial + attribute \src "libresoc.v:7131.9-7131.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\CR_dec31_dec_sub19_cr_in[2:0] 3'110 + case + assign $1\CR_dec31_dec_sub19_cr_in[2:0] 3'000 + end + sync always + update \CR_dec31_dec_sub19_cr_in $0\CR_dec31_dec_sub19_cr_in[2:0] + end + attribute \src "libresoc.v:7140.3-7149.6" + process $proc$libresoc.v:7140$148 + assign { } { } + assign { } { } + assign $0\CR_dec31_dec_sub19_cr_out[2:0] $1\CR_dec31_dec_sub19_cr_out[2:0] + attribute \src "libresoc.v:7141.5-7141.29" + switch \initial + attribute \src "libresoc.v:7141.9-7141.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\CR_dec31_dec_sub19_cr_out[2:0] 3'000 + case + assign $1\CR_dec31_dec_sub19_cr_out[2:0] 3'000 + end + sync always + update \CR_dec31_dec_sub19_cr_out $0\CR_dec31_dec_sub19_cr_out[2:0] + end + attribute \src "libresoc.v:7150.3-7159.6" + process $proc$libresoc.v:7150$149 + assign { } { } + assign { } { } + assign $0\CR_dec31_dec_sub19_rc_sel[1:0] $1\CR_dec31_dec_sub19_rc_sel[1:0] + attribute \src "libresoc.v:7151.5-7151.29" + switch \initial + attribute \src "libresoc.v:7151.9-7151.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\CR_dec31_dec_sub19_rc_sel[1:0] 2'00 + case + assign $1\CR_dec31_dec_sub19_rc_sel[1:0] 2'00 + end + sync always + update \CR_dec31_dec_sub19_rc_sel $0\CR_dec31_dec_sub19_rc_sel[1:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:7165.1-7903.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_DIV.dec.DIV_dec31" +attribute \generator "nMigen" +module \DIV_dec31 + attribute \src "libresoc.v:7873.3-7885.6" + wire width 3 $0\DIV_dec31_cr_in[2:0] + attribute \src "libresoc.v:7886.3-7898.6" + wire width 3 $0\DIV_dec31_cr_out[2:0] + attribute \src "libresoc.v:7743.3-7755.6" + wire width 2 $0\DIV_dec31_cry_in[1:0] + attribute \src "libresoc.v:7782.3-7794.6" + wire $0\DIV_dec31_cry_out[0:0] + attribute \src "libresoc.v:7821.3-7833.6" + wire width 12 $0\DIV_dec31_function_unit[11:0] + attribute \src "libresoc.v:7847.3-7859.6" + wire width 3 $0\DIV_dec31_in1_sel[2:0] + attribute \src "libresoc.v:7860.3-7872.6" + wire width 4 $0\DIV_dec31_in2_sel[3:0] + attribute \src "libresoc.v:7834.3-7846.6" + wire width 7 $0\DIV_dec31_internal_op[6:0] + attribute \src "libresoc.v:7756.3-7768.6" + wire $0\DIV_dec31_inv_a[0:0] + attribute \src "libresoc.v:7769.3-7781.6" + wire $0\DIV_dec31_inv_out[0:0] + attribute \src "libresoc.v:7795.3-7807.6" + wire $0\DIV_dec31_is_32b[0:0] + attribute \src "libresoc.v:7717.3-7729.6" + wire width 4 $0\DIV_dec31_ldst_len[3:0] + attribute \src "libresoc.v:7730.3-7742.6" + wire width 2 $0\DIV_dec31_rc_sel[1:0] + attribute \src "libresoc.v:7808.3-7820.6" + wire $0\DIV_dec31_sgn[0:0] + attribute \src "libresoc.v:7166.7-7166.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:7873.3-7885.6" + wire width 3 $1\DIV_dec31_cr_in[2:0] + attribute \src "libresoc.v:7886.3-7898.6" + wire width 3 $1\DIV_dec31_cr_out[2:0] + attribute \src "libresoc.v:7743.3-7755.6" + wire width 2 $1\DIV_dec31_cry_in[1:0] + attribute \src "libresoc.v:7782.3-7794.6" + wire $1\DIV_dec31_cry_out[0:0] + attribute \src "libresoc.v:7821.3-7833.6" + wire width 12 $1\DIV_dec31_function_unit[11:0] + attribute \src "libresoc.v:7847.3-7859.6" + wire width 3 $1\DIV_dec31_in1_sel[2:0] + attribute \src "libresoc.v:7860.3-7872.6" + wire width 4 $1\DIV_dec31_in2_sel[3:0] + attribute \src "libresoc.v:7834.3-7846.6" + wire width 7 $1\DIV_dec31_internal_op[6:0] + attribute \src "libresoc.v:7756.3-7768.6" + wire $1\DIV_dec31_inv_a[0:0] + attribute \src "libresoc.v:7769.3-7781.6" + wire $1\DIV_dec31_inv_out[0:0] + attribute \src "libresoc.v:7795.3-7807.6" + wire $1\DIV_dec31_is_32b[0:0] + attribute \src "libresoc.v:7717.3-7729.6" + wire width 4 $1\DIV_dec31_ldst_len[3:0] + attribute \src "libresoc.v:7730.3-7742.6" + wire width 2 $1\DIV_dec31_rc_sel[1:0] + attribute \src "libresoc.v:7808.3-7820.6" + wire $1\DIV_dec31_sgn[0:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \DIV_dec31_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 6 \DIV_dec31_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 9 \DIV_dec31_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 12 \DIV_dec31_cry_out + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \DIV_dec31_dec_sub11_opcode_in + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \DIV_dec31_dec_sub9_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \DIV_dec31_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 3 \DIV_dec31_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 4 \DIV_dec31_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \DIV_dec31_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 10 \DIV_dec31_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 11 \DIV_dec31_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 13 \DIV_dec31_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 7 \DIV_dec31_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 8 \DIV_dec31_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 14 \DIV_dec31_sgn + attribute \src "libresoc.v:7166.7-7166.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:326" + wire width 5 \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 15 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 10 \opcode_switch + attribute \module_not_derived 1 + attribute \src "libresoc.v:7683.23-7699.4" + cell \DIV_dec31_dec_sub11 \DIV_dec31_dec_sub11 + connect \DIV_dec31_dec_sub11_cr_in \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cr_in + connect \DIV_dec31_dec_sub11_cr_out \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cr_out + connect \DIV_dec31_dec_sub11_cry_in \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cry_in + connect \DIV_dec31_dec_sub11_cry_out \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cry_out + connect \DIV_dec31_dec_sub11_function_unit \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_function_unit + connect \DIV_dec31_dec_sub11_in1_sel \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_in1_sel + connect \DIV_dec31_dec_sub11_in2_sel \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_in2_sel + connect \DIV_dec31_dec_sub11_internal_op \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_internal_op + connect \DIV_dec31_dec_sub11_inv_a \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_inv_a + connect \DIV_dec31_dec_sub11_inv_out \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_inv_out + connect \DIV_dec31_dec_sub11_is_32b \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_is_32b + connect \DIV_dec31_dec_sub11_ldst_len \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_ldst_len + connect \DIV_dec31_dec_sub11_rc_sel \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_rc_sel + connect \DIV_dec31_dec_sub11_sgn \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_sgn + connect \opcode_in \DIV_dec31_dec_sub11_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:7700.22-7716.4" + cell \DIV_dec31_dec_sub9 \DIV_dec31_dec_sub9 + connect \DIV_dec31_dec_sub9_cr_in \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cr_in + connect \DIV_dec31_dec_sub9_cr_out \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cr_out + connect \DIV_dec31_dec_sub9_cry_in \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cry_in + connect \DIV_dec31_dec_sub9_cry_out \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cry_out + connect \DIV_dec31_dec_sub9_function_unit \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_function_unit + connect \DIV_dec31_dec_sub9_in1_sel \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_in1_sel + connect \DIV_dec31_dec_sub9_in2_sel \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_in2_sel + connect \DIV_dec31_dec_sub9_internal_op \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_internal_op + connect \DIV_dec31_dec_sub9_inv_a \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_inv_a + connect \DIV_dec31_dec_sub9_inv_out \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_inv_out + connect \DIV_dec31_dec_sub9_is_32b \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_is_32b + connect \DIV_dec31_dec_sub9_ldst_len \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_ldst_len + connect \DIV_dec31_dec_sub9_rc_sel \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_rc_sel + connect \DIV_dec31_dec_sub9_sgn \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_sgn + connect \opcode_in \DIV_dec31_dec_sub9_opcode_in + end + attribute \src "libresoc.v:7166.7-7166.20" + process $proc$libresoc.v:7166$165 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:7717.3-7729.6" + process $proc$libresoc.v:7717$151 + assign { } { } + assign { } { } + assign $0\DIV_dec31_ldst_len[3:0] $1\DIV_dec31_ldst_len[3:0] + attribute \src "libresoc.v:7718.5-7718.29" + switch \initial + attribute \src "libresoc.v:7718.9-7718.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\DIV_dec31_ldst_len[3:0] \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\DIV_dec31_ldst_len[3:0] \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_ldst_len + case + assign $1\DIV_dec31_ldst_len[3:0] 4'0000 + end + sync always + update \DIV_dec31_ldst_len $0\DIV_dec31_ldst_len[3:0] + end + attribute \src "libresoc.v:7730.3-7742.6" + process $proc$libresoc.v:7730$152 + assign { } { } + assign { } { } + assign $0\DIV_dec31_rc_sel[1:0] $1\DIV_dec31_rc_sel[1:0] + attribute \src "libresoc.v:7731.5-7731.29" + switch \initial + attribute \src "libresoc.v:7731.9-7731.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\DIV_dec31_rc_sel[1:0] \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\DIV_dec31_rc_sel[1:0] \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_rc_sel + case + assign $1\DIV_dec31_rc_sel[1:0] 2'00 + end + sync always + update \DIV_dec31_rc_sel $0\DIV_dec31_rc_sel[1:0] + end + attribute \src "libresoc.v:7743.3-7755.6" + process $proc$libresoc.v:7743$153 + assign { } { } + assign { } { } + assign $0\DIV_dec31_cry_in[1:0] $1\DIV_dec31_cry_in[1:0] + attribute \src "libresoc.v:7744.5-7744.29" + switch \initial + attribute \src "libresoc.v:7744.9-7744.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\DIV_dec31_cry_in[1:0] \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\DIV_dec31_cry_in[1:0] \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cry_in + case + assign $1\DIV_dec31_cry_in[1:0] 2'00 + end + sync always + update \DIV_dec31_cry_in $0\DIV_dec31_cry_in[1:0] + end + attribute \src "libresoc.v:7756.3-7768.6" + process $proc$libresoc.v:7756$154 + assign { } { } + assign { } { } + assign $0\DIV_dec31_inv_a[0:0] $1\DIV_dec31_inv_a[0:0] + attribute \src "libresoc.v:7757.5-7757.29" + switch \initial + attribute \src "libresoc.v:7757.9-7757.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\DIV_dec31_inv_a[0:0] \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\DIV_dec31_inv_a[0:0] \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_inv_a + case + assign $1\DIV_dec31_inv_a[0:0] 1'0 + end + sync always + update \DIV_dec31_inv_a $0\DIV_dec31_inv_a[0:0] + end + attribute \src "libresoc.v:7769.3-7781.6" + process $proc$libresoc.v:7769$155 + assign { } { } + assign { } { } + assign $0\DIV_dec31_inv_out[0:0] $1\DIV_dec31_inv_out[0:0] + attribute \src "libresoc.v:7770.5-7770.29" + switch \initial + attribute \src "libresoc.v:7770.9-7770.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\DIV_dec31_inv_out[0:0] \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\DIV_dec31_inv_out[0:0] \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_inv_out + case + assign $1\DIV_dec31_inv_out[0:0] 1'0 + end + sync always + update \DIV_dec31_inv_out $0\DIV_dec31_inv_out[0:0] + end + attribute \src "libresoc.v:7782.3-7794.6" + process $proc$libresoc.v:7782$156 + assign { } { } + assign { } { } + assign $0\DIV_dec31_cry_out[0:0] $1\DIV_dec31_cry_out[0:0] + attribute \src "libresoc.v:7783.5-7783.29" + switch \initial + attribute \src "libresoc.v:7783.9-7783.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\DIV_dec31_cry_out[0:0] \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\DIV_dec31_cry_out[0:0] \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cry_out + case + assign $1\DIV_dec31_cry_out[0:0] 1'0 + end + sync always + update \DIV_dec31_cry_out $0\DIV_dec31_cry_out[0:0] + end + attribute \src "libresoc.v:7795.3-7807.6" + process $proc$libresoc.v:7795$157 + assign { } { } + assign { } { } + assign $0\DIV_dec31_is_32b[0:0] $1\DIV_dec31_is_32b[0:0] + attribute \src "libresoc.v:7796.5-7796.29" + switch \initial + attribute \src "libresoc.v:7796.9-7796.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\DIV_dec31_is_32b[0:0] \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\DIV_dec31_is_32b[0:0] \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_is_32b + case + assign $1\DIV_dec31_is_32b[0:0] 1'0 + end + sync always + update \DIV_dec31_is_32b $0\DIV_dec31_is_32b[0:0] + end + attribute \src "libresoc.v:7808.3-7820.6" + process $proc$libresoc.v:7808$158 + assign { } { } + assign { } { } + assign $0\DIV_dec31_sgn[0:0] $1\DIV_dec31_sgn[0:0] + attribute \src "libresoc.v:7809.5-7809.29" + switch \initial + attribute \src "libresoc.v:7809.9-7809.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\DIV_dec31_sgn[0:0] \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\DIV_dec31_sgn[0:0] \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_sgn + case + assign $1\DIV_dec31_sgn[0:0] 1'0 + end + sync always + update \DIV_dec31_sgn $0\DIV_dec31_sgn[0:0] + end + attribute \src "libresoc.v:7821.3-7833.6" + process $proc$libresoc.v:7821$159 + assign { } { } + assign { } { } + assign $0\DIV_dec31_function_unit[11:0] $1\DIV_dec31_function_unit[11:0] + attribute \src "libresoc.v:7822.5-7822.29" + switch \initial + attribute \src "libresoc.v:7822.9-7822.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\DIV_dec31_function_unit[11:0] \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\DIV_dec31_function_unit[11:0] \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_function_unit + case + assign $1\DIV_dec31_function_unit[11:0] 12'000000000000 + end + sync always + update \DIV_dec31_function_unit $0\DIV_dec31_function_unit[11:0] + end + attribute \src "libresoc.v:7834.3-7846.6" + process $proc$libresoc.v:7834$160 + assign { } { } + assign { } { } + assign $0\DIV_dec31_internal_op[6:0] $1\DIV_dec31_internal_op[6:0] + attribute \src "libresoc.v:7835.5-7835.29" + switch \initial + attribute \src "libresoc.v:7835.9-7835.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\DIV_dec31_internal_op[6:0] \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\DIV_dec31_internal_op[6:0] \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_internal_op + case + assign $1\DIV_dec31_internal_op[6:0] 7'0000000 + end + sync always + update \DIV_dec31_internal_op $0\DIV_dec31_internal_op[6:0] + end + attribute \src "libresoc.v:7847.3-7859.6" + process $proc$libresoc.v:7847$161 + assign { } { } + assign { } { } + assign $0\DIV_dec31_in1_sel[2:0] $1\DIV_dec31_in1_sel[2:0] + attribute \src "libresoc.v:7848.5-7848.29" + switch \initial + attribute \src "libresoc.v:7848.9-7848.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\DIV_dec31_in1_sel[2:0] \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\DIV_dec31_in1_sel[2:0] \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_in1_sel + case + assign $1\DIV_dec31_in1_sel[2:0] 3'000 + end + sync always + update \DIV_dec31_in1_sel $0\DIV_dec31_in1_sel[2:0] + end + attribute \src "libresoc.v:7860.3-7872.6" + process $proc$libresoc.v:7860$162 + assign { } { } + assign { } { } + assign $0\DIV_dec31_in2_sel[3:0] $1\DIV_dec31_in2_sel[3:0] + attribute \src "libresoc.v:7861.5-7861.29" + switch \initial + attribute \src "libresoc.v:7861.9-7861.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\DIV_dec31_in2_sel[3:0] \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\DIV_dec31_in2_sel[3:0] \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_in2_sel + case + assign $1\DIV_dec31_in2_sel[3:0] 4'0000 + end + sync always + update \DIV_dec31_in2_sel $0\DIV_dec31_in2_sel[3:0] + end + attribute \src "libresoc.v:7873.3-7885.6" + process $proc$libresoc.v:7873$163 + assign { } { } + assign { } { } + assign $0\DIV_dec31_cr_in[2:0] $1\DIV_dec31_cr_in[2:0] + attribute \src "libresoc.v:7874.5-7874.29" + switch \initial + attribute \src "libresoc.v:7874.9-7874.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\DIV_dec31_cr_in[2:0] \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\DIV_dec31_cr_in[2:0] \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cr_in + case + assign $1\DIV_dec31_cr_in[2:0] 3'000 + end + sync always + update \DIV_dec31_cr_in $0\DIV_dec31_cr_in[2:0] + end + attribute \src "libresoc.v:7886.3-7898.6" + process $proc$libresoc.v:7886$164 + assign { } { } + assign { } { } + assign $0\DIV_dec31_cr_out[2:0] $1\DIV_dec31_cr_out[2:0] + attribute \src "libresoc.v:7887.5-7887.29" + switch \initial + attribute \src "libresoc.v:7887.9-7887.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\DIV_dec31_cr_out[2:0] \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\DIV_dec31_cr_out[2:0] \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cr_out + case + assign $1\DIV_dec31_cr_out[2:0] 3'000 + end + sync always + update \DIV_dec31_cr_out $0\DIV_dec31_cr_out[2:0] + end + connect \DIV_dec31_dec_sub11_opcode_in \opcode_in + connect \DIV_dec31_dec_sub9_opcode_in \opcode_in + connect \opc_in \opcode_switch [4:0] + connect \opcode_switch \opcode_in [10:1] +end +attribute \src "libresoc.v:7907.1-8610.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_DIV.dec.DIV_dec31.DIV_dec31_dec_sub11" +attribute \generator "nMigen" +module \DIV_dec31_dec_sub11 + attribute \src "libresoc.v:8424.3-8460.6" + wire width 3 $0\DIV_dec31_dec_sub11_cr_in[2:0] + attribute \src "libresoc.v:8461.3-8497.6" + wire width 3 $0\DIV_dec31_dec_sub11_cr_out[2:0] + attribute \src "libresoc.v:8572.3-8608.6" + wire width 2 $0\DIV_dec31_dec_sub11_cry_in[1:0] + attribute \src "libresoc.v:8202.3-8238.6" + wire $0\DIV_dec31_dec_sub11_cry_out[0:0] + attribute \src "libresoc.v:8091.3-8127.6" + wire width 12 $0\DIV_dec31_dec_sub11_function_unit[11:0] + attribute \src "libresoc.v:8350.3-8386.6" + wire width 3 $0\DIV_dec31_dec_sub11_in1_sel[2:0] + attribute \src "libresoc.v:8387.3-8423.6" + wire width 4 $0\DIV_dec31_dec_sub11_in2_sel[3:0] + attribute \src "libresoc.v:8313.3-8349.6" + wire width 7 $0\DIV_dec31_dec_sub11_internal_op[6:0] + attribute \src "libresoc.v:8128.3-8164.6" + wire $0\DIV_dec31_dec_sub11_inv_a[0:0] + attribute \src "libresoc.v:8165.3-8201.6" + wire $0\DIV_dec31_dec_sub11_inv_out[0:0] + attribute \src "libresoc.v:8239.3-8275.6" + wire $0\DIV_dec31_dec_sub11_is_32b[0:0] + attribute \src "libresoc.v:8498.3-8534.6" + wire width 4 $0\DIV_dec31_dec_sub11_ldst_len[3:0] + attribute \src "libresoc.v:8535.3-8571.6" + wire width 2 $0\DIV_dec31_dec_sub11_rc_sel[1:0] + attribute \src "libresoc.v:8276.3-8312.6" + wire $0\DIV_dec31_dec_sub11_sgn[0:0] + attribute \src "libresoc.v:7908.7-7908.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:8424.3-8460.6" + wire width 3 $1\DIV_dec31_dec_sub11_cr_in[2:0] + attribute \src "libresoc.v:8461.3-8497.6" + wire width 3 $1\DIV_dec31_dec_sub11_cr_out[2:0] + attribute \src "libresoc.v:8572.3-8608.6" + wire width 2 $1\DIV_dec31_dec_sub11_cry_in[1:0] + attribute \src "libresoc.v:8202.3-8238.6" + wire $1\DIV_dec31_dec_sub11_cry_out[0:0] + attribute \src "libresoc.v:8091.3-8127.6" + wire width 12 $1\DIV_dec31_dec_sub11_function_unit[11:0] + attribute \src "libresoc.v:8350.3-8386.6" + wire width 3 $1\DIV_dec31_dec_sub11_in1_sel[2:0] + attribute \src "libresoc.v:8387.3-8423.6" + wire width 4 $1\DIV_dec31_dec_sub11_in2_sel[3:0] + attribute \src "libresoc.v:8313.3-8349.6" + wire width 7 $1\DIV_dec31_dec_sub11_internal_op[6:0] + attribute \src "libresoc.v:8128.3-8164.6" + wire $1\DIV_dec31_dec_sub11_inv_a[0:0] + attribute \src "libresoc.v:8165.3-8201.6" + wire $1\DIV_dec31_dec_sub11_inv_out[0:0] + attribute \src "libresoc.v:8239.3-8275.6" + wire $1\DIV_dec31_dec_sub11_is_32b[0:0] + attribute \src "libresoc.v:8498.3-8534.6" + wire width 4 $1\DIV_dec31_dec_sub11_ldst_len[3:0] + attribute \src "libresoc.v:8535.3-8571.6" + wire width 2 $1\DIV_dec31_dec_sub11_rc_sel[1:0] + attribute \src "libresoc.v:8276.3-8312.6" + wire $1\DIV_dec31_dec_sub11_sgn[0:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \DIV_dec31_dec_sub11_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 6 \DIV_dec31_dec_sub11_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 9 \DIV_dec31_dec_sub11_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 12 \DIV_dec31_dec_sub11_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \DIV_dec31_dec_sub11_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 3 \DIV_dec31_dec_sub11_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 4 \DIV_dec31_dec_sub11_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \DIV_dec31_dec_sub11_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 10 \DIV_dec31_dec_sub11_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 11 \DIV_dec31_dec_sub11_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 13 \DIV_dec31_dec_sub11_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 7 \DIV_dec31_dec_sub11_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 8 \DIV_dec31_dec_sub11_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 14 \DIV_dec31_dec_sub11_sgn + attribute \src "libresoc.v:7908.7-7908.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 15 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 5 \opcode_switch + attribute \src "libresoc.v:7908.7-7908.20" + process $proc$libresoc.v:7908$180 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:8091.3-8127.6" + process $proc$libresoc.v:8091$166 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub11_function_unit[11:0] $1\DIV_dec31_dec_sub11_function_unit[11:0] + attribute \src "libresoc.v:8092.5-8092.29" + switch \initial + attribute \src "libresoc.v:8092.9-8092.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_function_unit[11:0] 12'001000000000 + case + assign $1\DIV_dec31_dec_sub11_function_unit[11:0] 12'000000000000 + end + sync always + update \DIV_dec31_dec_sub11_function_unit $0\DIV_dec31_dec_sub11_function_unit[11:0] + end + attribute \src "libresoc.v:8128.3-8164.6" + process $proc$libresoc.v:8128$167 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub11_inv_a[0:0] $1\DIV_dec31_dec_sub11_inv_a[0:0] + attribute \src "libresoc.v:8129.5-8129.29" + switch \initial + attribute \src "libresoc.v:8129.9-8129.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_inv_a[0:0] 1'0 + case + assign $1\DIV_dec31_dec_sub11_inv_a[0:0] 1'0 + end + sync always + update \DIV_dec31_dec_sub11_inv_a $0\DIV_dec31_dec_sub11_inv_a[0:0] + end + attribute \src "libresoc.v:8165.3-8201.6" + process $proc$libresoc.v:8165$168 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub11_inv_out[0:0] $1\DIV_dec31_dec_sub11_inv_out[0:0] + attribute \src "libresoc.v:8166.5-8166.29" + switch \initial + attribute \src "libresoc.v:8166.9-8166.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_inv_out[0:0] 1'0 + case + assign $1\DIV_dec31_dec_sub11_inv_out[0:0] 1'0 + end + sync always + update \DIV_dec31_dec_sub11_inv_out $0\DIV_dec31_dec_sub11_inv_out[0:0] + end + attribute \src "libresoc.v:8202.3-8238.6" + process $proc$libresoc.v:8202$169 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub11_cry_out[0:0] $1\DIV_dec31_dec_sub11_cry_out[0:0] + attribute \src "libresoc.v:8203.5-8203.29" + switch \initial + attribute \src "libresoc.v:8203.9-8203.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cry_out[0:0] 1'0 + case + assign $1\DIV_dec31_dec_sub11_cry_out[0:0] 1'0 + end + sync always + update \DIV_dec31_dec_sub11_cry_out $0\DIV_dec31_dec_sub11_cry_out[0:0] + end + attribute \src "libresoc.v:8239.3-8275.6" + process $proc$libresoc.v:8239$170 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub11_is_32b[0:0] $1\DIV_dec31_dec_sub11_is_32b[0:0] + attribute \src "libresoc.v:8240.5-8240.29" + switch \initial + attribute \src "libresoc.v:8240.9-8240.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_is_32b[0:0] 1'1 + case + assign $1\DIV_dec31_dec_sub11_is_32b[0:0] 1'0 + end + sync always + update \DIV_dec31_dec_sub11_is_32b $0\DIV_dec31_dec_sub11_is_32b[0:0] + end + attribute \src "libresoc.v:8276.3-8312.6" + process $proc$libresoc.v:8276$171 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub11_sgn[0:0] $1\DIV_dec31_dec_sub11_sgn[0:0] + attribute \src "libresoc.v:8277.5-8277.29" + switch \initial + attribute \src "libresoc.v:8277.9-8277.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_sgn[0:0] 1'1 + case + assign $1\DIV_dec31_dec_sub11_sgn[0:0] 1'0 + end + sync always + update \DIV_dec31_dec_sub11_sgn $0\DIV_dec31_dec_sub11_sgn[0:0] + end + attribute \src "libresoc.v:8313.3-8349.6" + process $proc$libresoc.v:8313$172 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub11_internal_op[6:0] $1\DIV_dec31_dec_sub11_internal_op[6:0] + attribute \src "libresoc.v:8314.5-8314.29" + switch \initial + attribute \src "libresoc.v:8314.9-8314.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_internal_op[6:0] 7'0011110 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_internal_op[6:0] 7'0011110 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_internal_op[6:0] 7'0011110 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_internal_op[6:0] 7'0011110 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_internal_op[6:0] 7'0011101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_internal_op[6:0] 7'0011101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_internal_op[6:0] 7'0011101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_internal_op[6:0] 7'0011101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_internal_op[6:0] 7'0101111 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_internal_op[6:0] 7'0101111 + case + assign $1\DIV_dec31_dec_sub11_internal_op[6:0] 7'0000000 + end + sync always + update \DIV_dec31_dec_sub11_internal_op $0\DIV_dec31_dec_sub11_internal_op[6:0] + end + attribute \src "libresoc.v:8350.3-8386.6" + process $proc$libresoc.v:8350$173 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub11_in1_sel[2:0] $1\DIV_dec31_dec_sub11_in1_sel[2:0] + attribute \src "libresoc.v:8351.5-8351.29" + switch \initial + attribute \src "libresoc.v:8351.9-8351.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_in1_sel[2:0] 3'001 + case + assign $1\DIV_dec31_dec_sub11_in1_sel[2:0] 3'000 + end + sync always + update \DIV_dec31_dec_sub11_in1_sel $0\DIV_dec31_dec_sub11_in1_sel[2:0] + end + attribute \src "libresoc.v:8387.3-8423.6" + process $proc$libresoc.v:8387$174 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub11_in2_sel[3:0] $1\DIV_dec31_dec_sub11_in2_sel[3:0] + attribute \src "libresoc.v:8388.5-8388.29" + switch \initial + attribute \src "libresoc.v:8388.9-8388.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_in2_sel[3:0] 4'0001 + case + assign $1\DIV_dec31_dec_sub11_in2_sel[3:0] 4'0000 + end + sync always + update \DIV_dec31_dec_sub11_in2_sel $0\DIV_dec31_dec_sub11_in2_sel[3:0] + end + attribute \src "libresoc.v:8424.3-8460.6" + process $proc$libresoc.v:8424$175 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub11_cr_in[2:0] $1\DIV_dec31_dec_sub11_cr_in[2:0] + attribute \src "libresoc.v:8425.5-8425.29" + switch \initial + attribute \src "libresoc.v:8425.9-8425.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cr_in[2:0] 3'000 + case + assign $1\DIV_dec31_dec_sub11_cr_in[2:0] 3'000 + end + sync always + update \DIV_dec31_dec_sub11_cr_in $0\DIV_dec31_dec_sub11_cr_in[2:0] + end + attribute \src "libresoc.v:8461.3-8497.6" + process $proc$libresoc.v:8461$176 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub11_cr_out[2:0] $1\DIV_dec31_dec_sub11_cr_out[2:0] + attribute \src "libresoc.v:8462.5-8462.29" + switch \initial + attribute \src "libresoc.v:8462.9-8462.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cr_out[2:0] 3'000 + case + assign $1\DIV_dec31_dec_sub11_cr_out[2:0] 3'000 + end + sync always + update \DIV_dec31_dec_sub11_cr_out $0\DIV_dec31_dec_sub11_cr_out[2:0] + end + attribute \src "libresoc.v:8498.3-8534.6" + process $proc$libresoc.v:8498$177 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub11_ldst_len[3:0] $1\DIV_dec31_dec_sub11_ldst_len[3:0] + attribute \src "libresoc.v:8499.5-8499.29" + switch \initial + attribute \src "libresoc.v:8499.9-8499.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_ldst_len[3:0] 4'0000 + case + assign $1\DIV_dec31_dec_sub11_ldst_len[3:0] 4'0000 + end + sync always + update \DIV_dec31_dec_sub11_ldst_len $0\DIV_dec31_dec_sub11_ldst_len[3:0] + end + attribute \src "libresoc.v:8535.3-8571.6" + process $proc$libresoc.v:8535$178 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub11_rc_sel[1:0] $1\DIV_dec31_dec_sub11_rc_sel[1:0] + attribute \src "libresoc.v:8536.5-8536.29" + switch \initial + attribute \src "libresoc.v:8536.9-8536.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_rc_sel[1:0] 2'00 + case + assign $1\DIV_dec31_dec_sub11_rc_sel[1:0] 2'00 + end + sync always + update \DIV_dec31_dec_sub11_rc_sel $0\DIV_dec31_dec_sub11_rc_sel[1:0] + end + attribute \src "libresoc.v:8572.3-8608.6" + process $proc$libresoc.v:8572$179 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub11_cry_in[1:0] $1\DIV_dec31_dec_sub11_cry_in[1:0] + attribute \src "libresoc.v:8573.5-8573.29" + switch \initial + attribute \src "libresoc.v:8573.9-8573.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cry_in[1:0] 2'00 + case + assign $1\DIV_dec31_dec_sub11_cry_in[1:0] 2'00 + end + sync always + update \DIV_dec31_dec_sub11_cry_in $0\DIV_dec31_dec_sub11_cry_in[1:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:8614.1-9317.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_DIV.dec.DIV_dec31.DIV_dec31_dec_sub9" +attribute \generator "nMigen" +module \DIV_dec31_dec_sub9 + attribute \src "libresoc.v:9131.3-9167.6" + wire width 3 $0\DIV_dec31_dec_sub9_cr_in[2:0] + attribute \src "libresoc.v:9168.3-9204.6" + wire width 3 $0\DIV_dec31_dec_sub9_cr_out[2:0] + attribute \src "libresoc.v:9279.3-9315.6" + wire width 2 $0\DIV_dec31_dec_sub9_cry_in[1:0] + attribute \src "libresoc.v:8909.3-8945.6" + wire $0\DIV_dec31_dec_sub9_cry_out[0:0] + attribute \src "libresoc.v:8798.3-8834.6" + wire width 12 $0\DIV_dec31_dec_sub9_function_unit[11:0] + attribute \src "libresoc.v:9057.3-9093.6" + wire width 3 $0\DIV_dec31_dec_sub9_in1_sel[2:0] + attribute \src "libresoc.v:9094.3-9130.6" + wire width 4 $0\DIV_dec31_dec_sub9_in2_sel[3:0] + attribute \src "libresoc.v:9020.3-9056.6" + wire width 7 $0\DIV_dec31_dec_sub9_internal_op[6:0] + attribute \src "libresoc.v:8835.3-8871.6" + wire $0\DIV_dec31_dec_sub9_inv_a[0:0] + attribute \src "libresoc.v:8872.3-8908.6" + wire $0\DIV_dec31_dec_sub9_inv_out[0:0] + attribute \src "libresoc.v:8946.3-8982.6" + wire $0\DIV_dec31_dec_sub9_is_32b[0:0] + attribute \src "libresoc.v:9205.3-9241.6" + wire width 4 $0\DIV_dec31_dec_sub9_ldst_len[3:0] + attribute \src "libresoc.v:9242.3-9278.6" + wire width 2 $0\DIV_dec31_dec_sub9_rc_sel[1:0] + attribute \src "libresoc.v:8983.3-9019.6" + wire $0\DIV_dec31_dec_sub9_sgn[0:0] + attribute \src "libresoc.v:8615.7-8615.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:9131.3-9167.6" + wire width 3 $1\DIV_dec31_dec_sub9_cr_in[2:0] + attribute \src "libresoc.v:9168.3-9204.6" + wire width 3 $1\DIV_dec31_dec_sub9_cr_out[2:0] + attribute \src "libresoc.v:9279.3-9315.6" + wire width 2 $1\DIV_dec31_dec_sub9_cry_in[1:0] + attribute \src "libresoc.v:8909.3-8945.6" + wire $1\DIV_dec31_dec_sub9_cry_out[0:0] + attribute \src "libresoc.v:8798.3-8834.6" + wire width 12 $1\DIV_dec31_dec_sub9_function_unit[11:0] + attribute \src "libresoc.v:9057.3-9093.6" + wire width 3 $1\DIV_dec31_dec_sub9_in1_sel[2:0] + attribute \src "libresoc.v:9094.3-9130.6" + wire width 4 $1\DIV_dec31_dec_sub9_in2_sel[3:0] + attribute \src "libresoc.v:9020.3-9056.6" + wire width 7 $1\DIV_dec31_dec_sub9_internal_op[6:0] + attribute \src "libresoc.v:8835.3-8871.6" + wire $1\DIV_dec31_dec_sub9_inv_a[0:0] + attribute \src "libresoc.v:8872.3-8908.6" + wire $1\DIV_dec31_dec_sub9_inv_out[0:0] + attribute \src "libresoc.v:8946.3-8982.6" + wire $1\DIV_dec31_dec_sub9_is_32b[0:0] + attribute \src "libresoc.v:9205.3-9241.6" + wire width 4 $1\DIV_dec31_dec_sub9_ldst_len[3:0] + attribute \src "libresoc.v:9242.3-9278.6" + wire width 2 $1\DIV_dec31_dec_sub9_rc_sel[1:0] + attribute \src "libresoc.v:8983.3-9019.6" + wire $1\DIV_dec31_dec_sub9_sgn[0:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \DIV_dec31_dec_sub9_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 6 \DIV_dec31_dec_sub9_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 9 \DIV_dec31_dec_sub9_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 12 \DIV_dec31_dec_sub9_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \DIV_dec31_dec_sub9_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 3 \DIV_dec31_dec_sub9_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 4 \DIV_dec31_dec_sub9_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \DIV_dec31_dec_sub9_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 10 \DIV_dec31_dec_sub9_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 11 \DIV_dec31_dec_sub9_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 13 \DIV_dec31_dec_sub9_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 7 \DIV_dec31_dec_sub9_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 8 \DIV_dec31_dec_sub9_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 14 \DIV_dec31_dec_sub9_sgn + attribute \src "libresoc.v:8615.7-8615.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 15 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 5 \opcode_switch + attribute \src "libresoc.v:8615.7-8615.20" + process $proc$libresoc.v:8615$195 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:8798.3-8834.6" + process $proc$libresoc.v:8798$181 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub9_function_unit[11:0] $1\DIV_dec31_dec_sub9_function_unit[11:0] + attribute \src "libresoc.v:8799.5-8799.29" + switch \initial + attribute \src "libresoc.v:8799.9-8799.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_function_unit[11:0] 12'001000000000 + case + assign $1\DIV_dec31_dec_sub9_function_unit[11:0] 12'000000000000 + end + sync always + update \DIV_dec31_dec_sub9_function_unit $0\DIV_dec31_dec_sub9_function_unit[11:0] + end + attribute \src "libresoc.v:8835.3-8871.6" + process $proc$libresoc.v:8835$182 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub9_inv_a[0:0] $1\DIV_dec31_dec_sub9_inv_a[0:0] + attribute \src "libresoc.v:8836.5-8836.29" + switch \initial + attribute \src "libresoc.v:8836.9-8836.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_inv_a[0:0] 1'0 + case + assign $1\DIV_dec31_dec_sub9_inv_a[0:0] 1'0 + end + sync always + update \DIV_dec31_dec_sub9_inv_a $0\DIV_dec31_dec_sub9_inv_a[0:0] + end + attribute \src "libresoc.v:8872.3-8908.6" + process $proc$libresoc.v:8872$183 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub9_inv_out[0:0] $1\DIV_dec31_dec_sub9_inv_out[0:0] + attribute \src "libresoc.v:8873.5-8873.29" + switch \initial + attribute \src "libresoc.v:8873.9-8873.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_inv_out[0:0] 1'0 + case + assign $1\DIV_dec31_dec_sub9_inv_out[0:0] 1'0 + end + sync always + update \DIV_dec31_dec_sub9_inv_out $0\DIV_dec31_dec_sub9_inv_out[0:0] + end + attribute \src "libresoc.v:8909.3-8945.6" + process $proc$libresoc.v:8909$184 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub9_cry_out[0:0] $1\DIV_dec31_dec_sub9_cry_out[0:0] + attribute \src "libresoc.v:8910.5-8910.29" + switch \initial + attribute \src "libresoc.v:8910.9-8910.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cry_out[0:0] 1'0 + case + assign $1\DIV_dec31_dec_sub9_cry_out[0:0] 1'0 + end + sync always + update \DIV_dec31_dec_sub9_cry_out $0\DIV_dec31_dec_sub9_cry_out[0:0] + end + attribute \src "libresoc.v:8946.3-8982.6" + process $proc$libresoc.v:8946$185 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub9_is_32b[0:0] $1\DIV_dec31_dec_sub9_is_32b[0:0] + attribute \src "libresoc.v:8947.5-8947.29" + switch \initial + attribute \src "libresoc.v:8947.9-8947.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_is_32b[0:0] 1'0 + case + assign $1\DIV_dec31_dec_sub9_is_32b[0:0] 1'0 + end + sync always + update \DIV_dec31_dec_sub9_is_32b $0\DIV_dec31_dec_sub9_is_32b[0:0] + end + attribute \src "libresoc.v:8983.3-9019.6" + process $proc$libresoc.v:8983$186 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub9_sgn[0:0] $1\DIV_dec31_dec_sub9_sgn[0:0] + attribute \src "libresoc.v:8984.5-8984.29" + switch \initial + attribute \src "libresoc.v:8984.9-8984.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_sgn[0:0] 1'1 + case + assign $1\DIV_dec31_dec_sub9_sgn[0:0] 1'0 + end + sync always + update \DIV_dec31_dec_sub9_sgn $0\DIV_dec31_dec_sub9_sgn[0:0] + end + attribute \src "libresoc.v:9020.3-9056.6" + process $proc$libresoc.v:9020$187 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub9_internal_op[6:0] $1\DIV_dec31_dec_sub9_internal_op[6:0] + attribute \src "libresoc.v:9021.5-9021.29" + switch \initial + attribute \src "libresoc.v:9021.9-9021.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_internal_op[6:0] 7'0011110 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_internal_op[6:0] 7'0011110 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_internal_op[6:0] 7'0011110 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_internal_op[6:0] 7'0011110 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_internal_op[6:0] 7'0011101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_internal_op[6:0] 7'0011101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_internal_op[6:0] 7'0011101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_internal_op[6:0] 7'0011101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_internal_op[6:0] 7'0101111 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_internal_op[6:0] 7'0101111 + case + assign $1\DIV_dec31_dec_sub9_internal_op[6:0] 7'0000000 + end + sync always + update \DIV_dec31_dec_sub9_internal_op $0\DIV_dec31_dec_sub9_internal_op[6:0] + end + attribute \src "libresoc.v:9057.3-9093.6" + process $proc$libresoc.v:9057$188 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub9_in1_sel[2:0] $1\DIV_dec31_dec_sub9_in1_sel[2:0] + attribute \src "libresoc.v:9058.5-9058.29" + switch \initial + attribute \src "libresoc.v:9058.9-9058.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_in1_sel[2:0] 3'001 + case + assign $1\DIV_dec31_dec_sub9_in1_sel[2:0] 3'000 + end + sync always + update \DIV_dec31_dec_sub9_in1_sel $0\DIV_dec31_dec_sub9_in1_sel[2:0] + end + attribute \src "libresoc.v:9094.3-9130.6" + process $proc$libresoc.v:9094$189 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub9_in2_sel[3:0] $1\DIV_dec31_dec_sub9_in2_sel[3:0] + attribute \src "libresoc.v:9095.5-9095.29" + switch \initial + attribute \src "libresoc.v:9095.9-9095.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_in2_sel[3:0] 4'0001 + case + assign $1\DIV_dec31_dec_sub9_in2_sel[3:0] 4'0000 + end + sync always + update \DIV_dec31_dec_sub9_in2_sel $0\DIV_dec31_dec_sub9_in2_sel[3:0] + end + attribute \src "libresoc.v:9131.3-9167.6" + process $proc$libresoc.v:9131$190 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub9_cr_in[2:0] $1\DIV_dec31_dec_sub9_cr_in[2:0] + attribute \src "libresoc.v:9132.5-9132.29" + switch \initial + attribute \src "libresoc.v:9132.9-9132.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cr_in[2:0] 3'000 + case + assign $1\DIV_dec31_dec_sub9_cr_in[2:0] 3'000 + end + sync always + update \DIV_dec31_dec_sub9_cr_in $0\DIV_dec31_dec_sub9_cr_in[2:0] + end + attribute \src "libresoc.v:9168.3-9204.6" + process $proc$libresoc.v:9168$191 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub9_cr_out[2:0] $1\DIV_dec31_dec_sub9_cr_out[2:0] + attribute \src "libresoc.v:9169.5-9169.29" + switch \initial + attribute \src "libresoc.v:9169.9-9169.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cr_out[2:0] 3'000 + case + assign $1\DIV_dec31_dec_sub9_cr_out[2:0] 3'000 + end + sync always + update \DIV_dec31_dec_sub9_cr_out $0\DIV_dec31_dec_sub9_cr_out[2:0] + end + attribute \src "libresoc.v:9205.3-9241.6" + process $proc$libresoc.v:9205$192 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub9_ldst_len[3:0] $1\DIV_dec31_dec_sub9_ldst_len[3:0] + attribute \src "libresoc.v:9206.5-9206.29" + switch \initial + attribute \src "libresoc.v:9206.9-9206.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_ldst_len[3:0] 4'0000 + case + assign $1\DIV_dec31_dec_sub9_ldst_len[3:0] 4'0000 + end + sync always + update \DIV_dec31_dec_sub9_ldst_len $0\DIV_dec31_dec_sub9_ldst_len[3:0] + end + attribute \src "libresoc.v:9242.3-9278.6" + process $proc$libresoc.v:9242$193 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub9_rc_sel[1:0] $1\DIV_dec31_dec_sub9_rc_sel[1:0] + attribute \src "libresoc.v:9243.5-9243.29" + switch \initial + attribute \src "libresoc.v:9243.9-9243.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_rc_sel[1:0] 2'00 + case + assign $1\DIV_dec31_dec_sub9_rc_sel[1:0] 2'00 + end + sync always + update \DIV_dec31_dec_sub9_rc_sel $0\DIV_dec31_dec_sub9_rc_sel[1:0] + end + attribute \src "libresoc.v:9279.3-9315.6" + process $proc$libresoc.v:9279$194 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub9_cry_in[1:0] $1\DIV_dec31_dec_sub9_cry_in[1:0] + attribute \src "libresoc.v:9280.5-9280.29" + switch \initial + attribute \src "libresoc.v:9280.9-9280.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cry_in[1:0] 2'00 + case + assign $1\DIV_dec31_dec_sub9_cry_in[1:0] 2'00 + end + sync always + update \DIV_dec31_dec_sub9_cry_in $0\DIV_dec31_dec_sub9_cry_in[1:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:9321.1-10482.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_LDST.dec.LDST_dec31" +attribute \generator "nMigen" +module \LDST_dec31 + attribute \src "libresoc.v:10324.3-10342.6" + wire $0\LDST_dec31_br[0:0] + attribute \src "libresoc.v:10229.3-10247.6" + wire width 3 $0\LDST_dec31_cr_in[2:0] + attribute \src "libresoc.v:10248.3-10266.6" + wire width 3 $0\LDST_dec31_cr_out[2:0] + attribute \src "libresoc.v:10400.3-10418.6" + wire width 12 $0\LDST_dec31_function_unit[11:0] + attribute \src "libresoc.v:10438.3-10456.6" + wire width 3 $0\LDST_dec31_in1_sel[2:0] + attribute \src "libresoc.v:10457.3-10475.6" + wire width 4 $0\LDST_dec31_in2_sel[3:0] + attribute \src "libresoc.v:10419.3-10437.6" + wire width 7 $0\LDST_dec31_internal_op[6:0] + attribute \src "libresoc.v:10362.3-10380.6" + wire $0\LDST_dec31_is_32b[0:0] + attribute \src "libresoc.v:10267.3-10285.6" + wire width 4 $0\LDST_dec31_ldst_len[3:0] + attribute \src "libresoc.v:10305.3-10323.6" + wire width 2 $0\LDST_dec31_rc_sel[1:0] + attribute \src "libresoc.v:10381.3-10399.6" + wire $0\LDST_dec31_sgn[0:0] + attribute \src "libresoc.v:10343.3-10361.6" + wire $0\LDST_dec31_sgn_ext[0:0] + attribute \src "libresoc.v:10286.3-10304.6" + wire width 2 $0\LDST_dec31_upd[1:0] + attribute \src "libresoc.v:9322.7-9322.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:10324.3-10342.6" + wire $1\LDST_dec31_br[0:0] + attribute \src "libresoc.v:10229.3-10247.6" + wire width 3 $1\LDST_dec31_cr_in[2:0] + attribute \src "libresoc.v:10248.3-10266.6" + wire width 3 $1\LDST_dec31_cr_out[2:0] + attribute \src "libresoc.v:10400.3-10418.6" + wire width 12 $1\LDST_dec31_function_unit[11:0] + attribute \src "libresoc.v:10438.3-10456.6" + wire width 3 $1\LDST_dec31_in1_sel[2:0] + attribute \src "libresoc.v:10457.3-10475.6" + wire width 4 $1\LDST_dec31_in2_sel[3:0] + attribute \src "libresoc.v:10419.3-10437.6" + wire width 7 $1\LDST_dec31_internal_op[6:0] + attribute \src "libresoc.v:10362.3-10380.6" + wire $1\LDST_dec31_is_32b[0:0] + attribute \src "libresoc.v:10267.3-10285.6" + wire width 4 $1\LDST_dec31_ldst_len[3:0] + attribute \src "libresoc.v:10305.3-10323.6" + wire width 2 $1\LDST_dec31_rc_sel[1:0] + attribute \src "libresoc.v:10381.3-10399.6" + wire $1\LDST_dec31_sgn[0:0] + attribute \src "libresoc.v:10343.3-10361.6" + wire $1\LDST_dec31_sgn_ext[0:0] + attribute \src "libresoc.v:10286.3-10304.6" + wire width 2 $1\LDST_dec31_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 10 \LDST_dec31_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \LDST_dec31_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 6 \LDST_dec31_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \LDST_dec31_dec_sub20_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \LDST_dec31_dec_sub21_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \LDST_dec31_dec_sub22_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \LDST_dec31_dec_sub23_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \LDST_dec31_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 3 \LDST_dec31_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 4 \LDST_dec31_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \LDST_dec31_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 12 \LDST_dec31_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 7 \LDST_dec31_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 9 \LDST_dec31_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 13 \LDST_dec31_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 11 \LDST_dec31_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 8 \LDST_dec31_upd + attribute \src "libresoc.v:9322.7-9322.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:326" + wire width 5 \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 14 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 10 \opcode_switch + attribute \module_not_derived 1 + attribute \src "libresoc.v:10165.24-10180.4" + cell \LDST_dec31_dec_sub20 \LDST_dec31_dec_sub20 + connect \LDST_dec31_dec_sub20_br \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_br + connect \LDST_dec31_dec_sub20_cr_in \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_cr_in + connect \LDST_dec31_dec_sub20_cr_out \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_cr_out + connect \LDST_dec31_dec_sub20_function_unit \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_function_unit + connect \LDST_dec31_dec_sub20_in1_sel \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_in1_sel + connect \LDST_dec31_dec_sub20_in2_sel \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_in2_sel + connect \LDST_dec31_dec_sub20_internal_op \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_internal_op + connect \LDST_dec31_dec_sub20_is_32b \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_is_32b + connect \LDST_dec31_dec_sub20_ldst_len \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_ldst_len + connect \LDST_dec31_dec_sub20_rc_sel \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_rc_sel + connect \LDST_dec31_dec_sub20_sgn \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_sgn + connect \LDST_dec31_dec_sub20_sgn_ext \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_sgn_ext + connect \LDST_dec31_dec_sub20_upd \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_upd + connect \opcode_in \LDST_dec31_dec_sub20_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:10181.24-10196.4" + cell \LDST_dec31_dec_sub21 \LDST_dec31_dec_sub21 + connect \LDST_dec31_dec_sub21_br \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_br + connect \LDST_dec31_dec_sub21_cr_in \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_cr_in + connect \LDST_dec31_dec_sub21_cr_out \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_cr_out + connect \LDST_dec31_dec_sub21_function_unit \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_function_unit + connect \LDST_dec31_dec_sub21_in1_sel \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_in1_sel + connect \LDST_dec31_dec_sub21_in2_sel \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_in2_sel + connect \LDST_dec31_dec_sub21_internal_op \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_internal_op + connect \LDST_dec31_dec_sub21_is_32b \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_is_32b + connect \LDST_dec31_dec_sub21_ldst_len \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_ldst_len + connect \LDST_dec31_dec_sub21_rc_sel \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_rc_sel + connect \LDST_dec31_dec_sub21_sgn \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_sgn + connect \LDST_dec31_dec_sub21_sgn_ext \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_sgn_ext + connect \LDST_dec31_dec_sub21_upd \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_upd + connect \opcode_in \LDST_dec31_dec_sub21_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:10197.24-10212.4" + cell \LDST_dec31_dec_sub22 \LDST_dec31_dec_sub22 + connect \LDST_dec31_dec_sub22_br \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_br + connect \LDST_dec31_dec_sub22_cr_in \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_cr_in + connect \LDST_dec31_dec_sub22_cr_out \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_cr_out + connect \LDST_dec31_dec_sub22_function_unit \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_function_unit + connect \LDST_dec31_dec_sub22_in1_sel \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_in1_sel + connect \LDST_dec31_dec_sub22_in2_sel \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_in2_sel + connect \LDST_dec31_dec_sub22_internal_op \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_internal_op + connect \LDST_dec31_dec_sub22_is_32b \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_is_32b + connect \LDST_dec31_dec_sub22_ldst_len \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_ldst_len + connect \LDST_dec31_dec_sub22_rc_sel \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_rc_sel + connect \LDST_dec31_dec_sub22_sgn \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_sgn + connect \LDST_dec31_dec_sub22_sgn_ext \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_sgn_ext + connect \LDST_dec31_dec_sub22_upd \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_upd + connect \opcode_in \LDST_dec31_dec_sub22_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:10213.24-10228.4" + cell \LDST_dec31_dec_sub23 \LDST_dec31_dec_sub23 + connect \LDST_dec31_dec_sub23_br \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_br + connect \LDST_dec31_dec_sub23_cr_in \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_cr_in + connect \LDST_dec31_dec_sub23_cr_out \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_cr_out + connect \LDST_dec31_dec_sub23_function_unit \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_function_unit + connect \LDST_dec31_dec_sub23_in1_sel \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_in1_sel + connect \LDST_dec31_dec_sub23_in2_sel \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_in2_sel + connect \LDST_dec31_dec_sub23_internal_op \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_internal_op + connect \LDST_dec31_dec_sub23_is_32b \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_is_32b + connect \LDST_dec31_dec_sub23_ldst_len \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_ldst_len + connect \LDST_dec31_dec_sub23_rc_sel \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_rc_sel + connect \LDST_dec31_dec_sub23_sgn \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_sgn + connect \LDST_dec31_dec_sub23_sgn_ext \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_sgn_ext + connect \LDST_dec31_dec_sub23_upd \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_upd + connect \opcode_in \LDST_dec31_dec_sub23_opcode_in + end + attribute \src "libresoc.v:10229.3-10247.6" + process $proc$libresoc.v:10229$196 + assign { } { } + assign { } { } + assign $0\LDST_dec31_cr_in[2:0] $1\LDST_dec31_cr_in[2:0] + attribute \src "libresoc.v:10230.5-10230.29" + switch \initial + attribute \src "libresoc.v:10230.9-10230.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\LDST_dec31_cr_in[2:0] \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_cr_in[2:0] \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\LDST_dec31_cr_in[2:0] \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\LDST_dec31_cr_in[2:0] \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_cr_in + case + assign $1\LDST_dec31_cr_in[2:0] 3'000 + end + sync always + update \LDST_dec31_cr_in $0\LDST_dec31_cr_in[2:0] + end + attribute \src "libresoc.v:10248.3-10266.6" + process $proc$libresoc.v:10248$197 + assign { } { } + assign { } { } + assign $0\LDST_dec31_cr_out[2:0] $1\LDST_dec31_cr_out[2:0] + attribute \src "libresoc.v:10249.5-10249.29" + switch \initial + attribute \src "libresoc.v:10249.9-10249.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\LDST_dec31_cr_out[2:0] \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_cr_out[2:0] \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\LDST_dec31_cr_out[2:0] \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\LDST_dec31_cr_out[2:0] \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_cr_out + case + assign $1\LDST_dec31_cr_out[2:0] 3'000 + end + sync always + update \LDST_dec31_cr_out $0\LDST_dec31_cr_out[2:0] + end + attribute \src "libresoc.v:10267.3-10285.6" + process $proc$libresoc.v:10267$198 + assign { } { } + assign { } { } + assign $0\LDST_dec31_ldst_len[3:0] $1\LDST_dec31_ldst_len[3:0] + attribute \src "libresoc.v:10268.5-10268.29" + switch \initial + attribute \src "libresoc.v:10268.9-10268.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\LDST_dec31_ldst_len[3:0] \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_ldst_len[3:0] \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\LDST_dec31_ldst_len[3:0] \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\LDST_dec31_ldst_len[3:0] \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_ldst_len + case + assign $1\LDST_dec31_ldst_len[3:0] 4'0000 + end + sync always + update \LDST_dec31_ldst_len $0\LDST_dec31_ldst_len[3:0] + end + attribute \src "libresoc.v:10286.3-10304.6" + process $proc$libresoc.v:10286$199 + assign { } { } + assign { } { } + assign $0\LDST_dec31_upd[1:0] $1\LDST_dec31_upd[1:0] + attribute \src "libresoc.v:10287.5-10287.29" + switch \initial + attribute \src "libresoc.v:10287.9-10287.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\LDST_dec31_upd[1:0] \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_upd[1:0] \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\LDST_dec31_upd[1:0] \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\LDST_dec31_upd[1:0] \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_upd + case + assign $1\LDST_dec31_upd[1:0] 2'00 + end + sync always + update \LDST_dec31_upd $0\LDST_dec31_upd[1:0] + end + attribute \src "libresoc.v:10305.3-10323.6" + process $proc$libresoc.v:10305$200 + assign { } { } + assign { } { } + assign $0\LDST_dec31_rc_sel[1:0] $1\LDST_dec31_rc_sel[1:0] + attribute \src "libresoc.v:10306.5-10306.29" + switch \initial + attribute \src "libresoc.v:10306.9-10306.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\LDST_dec31_rc_sel[1:0] \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_rc_sel[1:0] \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\LDST_dec31_rc_sel[1:0] \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\LDST_dec31_rc_sel[1:0] \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_rc_sel + case + assign $1\LDST_dec31_rc_sel[1:0] 2'00 + end + sync always + update \LDST_dec31_rc_sel $0\LDST_dec31_rc_sel[1:0] + end + attribute \src "libresoc.v:10324.3-10342.6" + process $proc$libresoc.v:10324$201 + assign { } { } + assign { } { } + assign $0\LDST_dec31_br[0:0] $1\LDST_dec31_br[0:0] + attribute \src "libresoc.v:10325.5-10325.29" + switch \initial + attribute \src "libresoc.v:10325.9-10325.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\LDST_dec31_br[0:0] \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_br + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_br[0:0] \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_br + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\LDST_dec31_br[0:0] \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_br + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\LDST_dec31_br[0:0] \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_br + case + assign $1\LDST_dec31_br[0:0] 1'0 + end + sync always + update \LDST_dec31_br $0\LDST_dec31_br[0:0] + end + attribute \src "libresoc.v:10343.3-10361.6" + process $proc$libresoc.v:10343$202 + assign { } { } + assign { } { } + assign $0\LDST_dec31_sgn_ext[0:0] $1\LDST_dec31_sgn_ext[0:0] + attribute \src "libresoc.v:10344.5-10344.29" + switch \initial + attribute \src "libresoc.v:10344.9-10344.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\LDST_dec31_sgn_ext[0:0] \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_sgn_ext[0:0] \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\LDST_dec31_sgn_ext[0:0] \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\LDST_dec31_sgn_ext[0:0] \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_sgn_ext + case + assign $1\LDST_dec31_sgn_ext[0:0] 1'0 + end + sync always + update \LDST_dec31_sgn_ext $0\LDST_dec31_sgn_ext[0:0] + end + attribute \src "libresoc.v:10362.3-10380.6" + process $proc$libresoc.v:10362$203 + assign { } { } + assign { } { } + assign $0\LDST_dec31_is_32b[0:0] $1\LDST_dec31_is_32b[0:0] + attribute \src "libresoc.v:10363.5-10363.29" + switch \initial + attribute \src "libresoc.v:10363.9-10363.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\LDST_dec31_is_32b[0:0] \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_is_32b[0:0] \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\LDST_dec31_is_32b[0:0] \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\LDST_dec31_is_32b[0:0] \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_is_32b + case + assign $1\LDST_dec31_is_32b[0:0] 1'0 + end + sync always + update \LDST_dec31_is_32b $0\LDST_dec31_is_32b[0:0] + end + attribute \src "libresoc.v:10381.3-10399.6" + process $proc$libresoc.v:10381$204 + assign { } { } + assign { } { } + assign $0\LDST_dec31_sgn[0:0] $1\LDST_dec31_sgn[0:0] + attribute \src "libresoc.v:10382.5-10382.29" + switch \initial + attribute \src "libresoc.v:10382.9-10382.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\LDST_dec31_sgn[0:0] \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_sgn[0:0] \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\LDST_dec31_sgn[0:0] \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\LDST_dec31_sgn[0:0] \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_sgn + case + assign $1\LDST_dec31_sgn[0:0] 1'0 + end + sync always + update \LDST_dec31_sgn $0\LDST_dec31_sgn[0:0] + end + attribute \src "libresoc.v:10400.3-10418.6" + process $proc$libresoc.v:10400$205 + assign { } { } + assign { } { } + assign $0\LDST_dec31_function_unit[11:0] $1\LDST_dec31_function_unit[11:0] + attribute \src "libresoc.v:10401.5-10401.29" + switch \initial + attribute \src "libresoc.v:10401.9-10401.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\LDST_dec31_function_unit[11:0] \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_function_unit[11:0] \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\LDST_dec31_function_unit[11:0] \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\LDST_dec31_function_unit[11:0] \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_function_unit + case + assign $1\LDST_dec31_function_unit[11:0] 12'000000000000 + end + sync always + update \LDST_dec31_function_unit $0\LDST_dec31_function_unit[11:0] + end + attribute \src "libresoc.v:10419.3-10437.6" + process $proc$libresoc.v:10419$206 + assign { } { } + assign { } { } + assign $0\LDST_dec31_internal_op[6:0] $1\LDST_dec31_internal_op[6:0] + attribute \src "libresoc.v:10420.5-10420.29" + switch \initial + attribute \src "libresoc.v:10420.9-10420.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\LDST_dec31_internal_op[6:0] \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_internal_op[6:0] \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\LDST_dec31_internal_op[6:0] \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\LDST_dec31_internal_op[6:0] \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_internal_op + case + assign $1\LDST_dec31_internal_op[6:0] 7'0000000 + end + sync always + update \LDST_dec31_internal_op $0\LDST_dec31_internal_op[6:0] + end + attribute \src "libresoc.v:10438.3-10456.6" + process $proc$libresoc.v:10438$207 + assign { } { } + assign { } { } + assign $0\LDST_dec31_in1_sel[2:0] $1\LDST_dec31_in1_sel[2:0] + attribute \src "libresoc.v:10439.5-10439.29" + switch \initial + attribute \src "libresoc.v:10439.9-10439.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\LDST_dec31_in1_sel[2:0] \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_in1_sel[2:0] \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\LDST_dec31_in1_sel[2:0] \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\LDST_dec31_in1_sel[2:0] \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_in1_sel + case + assign $1\LDST_dec31_in1_sel[2:0] 3'000 + end + sync always + update \LDST_dec31_in1_sel $0\LDST_dec31_in1_sel[2:0] + end + attribute \src "libresoc.v:10457.3-10475.6" + process $proc$libresoc.v:10457$208 + assign { } { } + assign { } { } + assign $0\LDST_dec31_in2_sel[3:0] $1\LDST_dec31_in2_sel[3:0] + attribute \src "libresoc.v:10458.5-10458.29" + switch \initial + attribute \src "libresoc.v:10458.9-10458.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\LDST_dec31_in2_sel[3:0] \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_in2_sel[3:0] \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\LDST_dec31_in2_sel[3:0] \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\LDST_dec31_in2_sel[3:0] \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_in2_sel + case + assign $1\LDST_dec31_in2_sel[3:0] 4'0000 + end + sync always + update \LDST_dec31_in2_sel $0\LDST_dec31_in2_sel[3:0] + end + attribute \src "libresoc.v:9322.7-9322.20" + process $proc$libresoc.v:9322$209 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + connect \LDST_dec31_dec_sub23_opcode_in \opcode_in + connect \LDST_dec31_dec_sub21_opcode_in \opcode_in + connect \LDST_dec31_dec_sub20_opcode_in \opcode_in + connect \LDST_dec31_dec_sub22_opcode_in \opcode_in + connect \opc_in \opcode_switch [4:0] + connect \opcode_switch \opcode_in [10:1] +end +attribute \src "libresoc.v:10486.1-10994.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_LDST.dec.LDST_dec31.LDST_dec31_dec_sub20" +attribute \generator "nMigen" +module \LDST_dec31_dec_sub20 + attribute \src "libresoc.v:10693.3-10717.6" + wire $0\LDST_dec31_dec_sub20_br[0:0] + attribute \src "libresoc.v:10868.3-10892.6" + wire width 3 $0\LDST_dec31_dec_sub20_cr_in[2:0] + attribute \src "libresoc.v:10893.3-10917.6" + wire width 3 $0\LDST_dec31_dec_sub20_cr_out[2:0] + attribute \src "libresoc.v:10668.3-10692.6" + wire width 12 $0\LDST_dec31_dec_sub20_function_unit[11:0] + attribute \src "libresoc.v:10818.3-10842.6" + wire width 3 $0\LDST_dec31_dec_sub20_in1_sel[2:0] + attribute \src "libresoc.v:10843.3-10867.6" + wire width 4 $0\LDST_dec31_dec_sub20_in2_sel[3:0] + attribute \src "libresoc.v:10793.3-10817.6" + wire width 7 $0\LDST_dec31_dec_sub20_internal_op[6:0] + attribute \src "libresoc.v:10743.3-10767.6" + wire $0\LDST_dec31_dec_sub20_is_32b[0:0] + attribute \src "libresoc.v:10918.3-10942.6" + wire width 4 $0\LDST_dec31_dec_sub20_ldst_len[3:0] + attribute \src "libresoc.v:10968.3-10992.6" + wire width 2 $0\LDST_dec31_dec_sub20_rc_sel[1:0] + attribute \src "libresoc.v:10768.3-10792.6" + wire $0\LDST_dec31_dec_sub20_sgn[0:0] + attribute \src "libresoc.v:10718.3-10742.6" + wire $0\LDST_dec31_dec_sub20_sgn_ext[0:0] + attribute \src "libresoc.v:10943.3-10967.6" + wire width 2 $0\LDST_dec31_dec_sub20_upd[1:0] + attribute \src "libresoc.v:10487.7-10487.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:10693.3-10717.6" + wire $1\LDST_dec31_dec_sub20_br[0:0] + attribute \src "libresoc.v:10868.3-10892.6" + wire width 3 $1\LDST_dec31_dec_sub20_cr_in[2:0] + attribute \src "libresoc.v:10893.3-10917.6" + wire width 3 $1\LDST_dec31_dec_sub20_cr_out[2:0] + attribute \src "libresoc.v:10668.3-10692.6" + wire width 12 $1\LDST_dec31_dec_sub20_function_unit[11:0] + attribute \src "libresoc.v:10818.3-10842.6" + wire width 3 $1\LDST_dec31_dec_sub20_in1_sel[2:0] + attribute \src "libresoc.v:10843.3-10867.6" + wire width 4 $1\LDST_dec31_dec_sub20_in2_sel[3:0] + attribute \src "libresoc.v:10793.3-10817.6" + wire width 7 $1\LDST_dec31_dec_sub20_internal_op[6:0] + attribute \src "libresoc.v:10743.3-10767.6" + wire $1\LDST_dec31_dec_sub20_is_32b[0:0] + attribute \src "libresoc.v:10918.3-10942.6" + wire width 4 $1\LDST_dec31_dec_sub20_ldst_len[3:0] + attribute \src "libresoc.v:10968.3-10992.6" + wire width 2 $1\LDST_dec31_dec_sub20_rc_sel[1:0] + attribute \src "libresoc.v:10768.3-10792.6" + wire $1\LDST_dec31_dec_sub20_sgn[0:0] + attribute \src "libresoc.v:10718.3-10742.6" + wire $1\LDST_dec31_dec_sub20_sgn_ext[0:0] + attribute \src "libresoc.v:10943.3-10967.6" + wire width 2 $1\LDST_dec31_dec_sub20_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 10 \LDST_dec31_dec_sub20_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \LDST_dec31_dec_sub20_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 6 \LDST_dec31_dec_sub20_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \LDST_dec31_dec_sub20_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 3 \LDST_dec31_dec_sub20_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 4 \LDST_dec31_dec_sub20_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \LDST_dec31_dec_sub20_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 12 \LDST_dec31_dec_sub20_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 7 \LDST_dec31_dec_sub20_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 9 \LDST_dec31_dec_sub20_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 13 \LDST_dec31_dec_sub20_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 11 \LDST_dec31_dec_sub20_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 8 \LDST_dec31_dec_sub20_upd + attribute \src "libresoc.v:10487.7-10487.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 14 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 5 \opcode_switch + attribute \src "libresoc.v:10487.7-10487.20" + process $proc$libresoc.v:10487$223 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:10668.3-10692.6" + process $proc$libresoc.v:10668$210 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub20_function_unit[11:0] $1\LDST_dec31_dec_sub20_function_unit[11:0] + attribute \src "libresoc.v:10669.5-10669.29" + switch \initial + attribute \src "libresoc.v:10669.9-10669.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub20_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\LDST_dec31_dec_sub20_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LDST_dec31_dec_sub20_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LDST_dec31_dec_sub20_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub20_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_dec_sub20_function_unit[11:0] 12'000000000100 + case + assign $1\LDST_dec31_dec_sub20_function_unit[11:0] 12'000000000000 + end + sync always + update \LDST_dec31_dec_sub20_function_unit $0\LDST_dec31_dec_sub20_function_unit[11:0] + end + attribute \src "libresoc.v:10693.3-10717.6" + process $proc$libresoc.v:10693$211 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub20_br[0:0] $1\LDST_dec31_dec_sub20_br[0:0] + attribute \src "libresoc.v:10694.5-10694.29" + switch \initial + attribute \src "libresoc.v:10694.9-10694.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub20_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\LDST_dec31_dec_sub20_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LDST_dec31_dec_sub20_br[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LDST_dec31_dec_sub20_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub20_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_dec_sub20_br[0:0] 1'1 + case + assign $1\LDST_dec31_dec_sub20_br[0:0] 1'0 + end + sync always + update \LDST_dec31_dec_sub20_br $0\LDST_dec31_dec_sub20_br[0:0] + end + attribute \src "libresoc.v:10718.3-10742.6" + process $proc$libresoc.v:10718$212 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub20_sgn_ext[0:0] $1\LDST_dec31_dec_sub20_sgn_ext[0:0] + attribute \src "libresoc.v:10719.5-10719.29" + switch \initial + attribute \src "libresoc.v:10719.9-10719.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub20_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\LDST_dec31_dec_sub20_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LDST_dec31_dec_sub20_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LDST_dec31_dec_sub20_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub20_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_dec_sub20_sgn_ext[0:0] 1'0 + case + assign $1\LDST_dec31_dec_sub20_sgn_ext[0:0] 1'0 + end + sync always + update \LDST_dec31_dec_sub20_sgn_ext $0\LDST_dec31_dec_sub20_sgn_ext[0:0] + end + attribute \src "libresoc.v:10743.3-10767.6" + process $proc$libresoc.v:10743$213 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub20_is_32b[0:0] $1\LDST_dec31_dec_sub20_is_32b[0:0] + attribute \src "libresoc.v:10744.5-10744.29" + switch \initial + attribute \src "libresoc.v:10744.9-10744.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub20_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\LDST_dec31_dec_sub20_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LDST_dec31_dec_sub20_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LDST_dec31_dec_sub20_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub20_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_dec_sub20_is_32b[0:0] 1'0 + case + assign $1\LDST_dec31_dec_sub20_is_32b[0:0] 1'0 + end + sync always + update \LDST_dec31_dec_sub20_is_32b $0\LDST_dec31_dec_sub20_is_32b[0:0] + end + attribute \src "libresoc.v:10768.3-10792.6" + process $proc$libresoc.v:10768$214 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub20_sgn[0:0] $1\LDST_dec31_dec_sub20_sgn[0:0] + attribute \src "libresoc.v:10769.5-10769.29" + switch \initial + attribute \src "libresoc.v:10769.9-10769.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub20_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\LDST_dec31_dec_sub20_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LDST_dec31_dec_sub20_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LDST_dec31_dec_sub20_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub20_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_dec_sub20_sgn[0:0] 1'0 + case + assign $1\LDST_dec31_dec_sub20_sgn[0:0] 1'0 + end + sync always + update \LDST_dec31_dec_sub20_sgn $0\LDST_dec31_dec_sub20_sgn[0:0] + end + attribute \src "libresoc.v:10793.3-10817.6" + process $proc$libresoc.v:10793$215 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub20_internal_op[6:0] $1\LDST_dec31_dec_sub20_internal_op[6:0] + attribute \src "libresoc.v:10794.5-10794.29" + switch \initial + attribute \src "libresoc.v:10794.9-10794.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub20_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\LDST_dec31_dec_sub20_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LDST_dec31_dec_sub20_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LDST_dec31_dec_sub20_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub20_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_dec_sub20_internal_op[6:0] 7'0100110 + case + assign $1\LDST_dec31_dec_sub20_internal_op[6:0] 7'0000000 + end + sync always + update \LDST_dec31_dec_sub20_internal_op $0\LDST_dec31_dec_sub20_internal_op[6:0] + end + attribute \src "libresoc.v:10818.3-10842.6" + process $proc$libresoc.v:10818$216 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub20_in1_sel[2:0] $1\LDST_dec31_dec_sub20_in1_sel[2:0] + attribute \src "libresoc.v:10819.5-10819.29" + switch \initial + attribute \src "libresoc.v:10819.9-10819.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub20_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\LDST_dec31_dec_sub20_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LDST_dec31_dec_sub20_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LDST_dec31_dec_sub20_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub20_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_dec_sub20_in1_sel[2:0] 3'010 + case + assign $1\LDST_dec31_dec_sub20_in1_sel[2:0] 3'000 + end + sync always + update \LDST_dec31_dec_sub20_in1_sel $0\LDST_dec31_dec_sub20_in1_sel[2:0] + end + attribute \src "libresoc.v:10843.3-10867.6" + process $proc$libresoc.v:10843$217 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub20_in2_sel[3:0] $1\LDST_dec31_dec_sub20_in2_sel[3:0] + attribute \src "libresoc.v:10844.5-10844.29" + switch \initial + attribute \src "libresoc.v:10844.9-10844.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub20_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\LDST_dec31_dec_sub20_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LDST_dec31_dec_sub20_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LDST_dec31_dec_sub20_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub20_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_dec_sub20_in2_sel[3:0] 4'0001 + case + assign $1\LDST_dec31_dec_sub20_in2_sel[3:0] 4'0000 + end + sync always + update \LDST_dec31_dec_sub20_in2_sel $0\LDST_dec31_dec_sub20_in2_sel[3:0] + end + attribute \src "libresoc.v:10868.3-10892.6" + process $proc$libresoc.v:10868$218 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub20_cr_in[2:0] $1\LDST_dec31_dec_sub20_cr_in[2:0] + attribute \src "libresoc.v:10869.5-10869.29" + switch \initial + attribute \src "libresoc.v:10869.9-10869.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub20_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\LDST_dec31_dec_sub20_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LDST_dec31_dec_sub20_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LDST_dec31_dec_sub20_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub20_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_dec_sub20_cr_in[2:0] 3'000 + case + assign $1\LDST_dec31_dec_sub20_cr_in[2:0] 3'000 + end + sync always + update \LDST_dec31_dec_sub20_cr_in $0\LDST_dec31_dec_sub20_cr_in[2:0] + end + attribute \src "libresoc.v:10893.3-10917.6" + process $proc$libresoc.v:10893$219 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub20_cr_out[2:0] $1\LDST_dec31_dec_sub20_cr_out[2:0] + attribute \src "libresoc.v:10894.5-10894.29" + switch \initial + attribute \src "libresoc.v:10894.9-10894.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub20_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\LDST_dec31_dec_sub20_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LDST_dec31_dec_sub20_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LDST_dec31_dec_sub20_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub20_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_dec_sub20_cr_out[2:0] 3'000 + case + assign $1\LDST_dec31_dec_sub20_cr_out[2:0] 3'000 + end + sync always + update \LDST_dec31_dec_sub20_cr_out $0\LDST_dec31_dec_sub20_cr_out[2:0] + end + attribute \src "libresoc.v:10918.3-10942.6" + process $proc$libresoc.v:10918$220 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub20_ldst_len[3:0] $1\LDST_dec31_dec_sub20_ldst_len[3:0] + attribute \src "libresoc.v:10919.5-10919.29" + switch \initial + attribute \src "libresoc.v:10919.9-10919.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub20_ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\LDST_dec31_dec_sub20_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LDST_dec31_dec_sub20_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LDST_dec31_dec_sub20_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub20_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_dec_sub20_ldst_len[3:0] 4'1000 + case + assign $1\LDST_dec31_dec_sub20_ldst_len[3:0] 4'0000 + end + sync always + update \LDST_dec31_dec_sub20_ldst_len $0\LDST_dec31_dec_sub20_ldst_len[3:0] + end + attribute \src "libresoc.v:10943.3-10967.6" + process $proc$libresoc.v:10943$221 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub20_upd[1:0] $1\LDST_dec31_dec_sub20_upd[1:0] + attribute \src "libresoc.v:10944.5-10944.29" + switch \initial + attribute \src "libresoc.v:10944.9-10944.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub20_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\LDST_dec31_dec_sub20_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LDST_dec31_dec_sub20_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LDST_dec31_dec_sub20_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub20_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_dec_sub20_upd[1:0] 2'00 + case + assign $1\LDST_dec31_dec_sub20_upd[1:0] 2'00 + end + sync always + update \LDST_dec31_dec_sub20_upd $0\LDST_dec31_dec_sub20_upd[1:0] + end + attribute \src "libresoc.v:10968.3-10992.6" + process $proc$libresoc.v:10968$222 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub20_rc_sel[1:0] $1\LDST_dec31_dec_sub20_rc_sel[1:0] + attribute \src "libresoc.v:10969.5-10969.29" + switch \initial + attribute \src "libresoc.v:10969.9-10969.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub20_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\LDST_dec31_dec_sub20_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LDST_dec31_dec_sub20_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LDST_dec31_dec_sub20_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub20_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_dec_sub20_rc_sel[1:0] 2'00 + case + assign $1\LDST_dec31_dec_sub20_rc_sel[1:0] 2'00 + end + sync always + update \LDST_dec31_dec_sub20_rc_sel $0\LDST_dec31_dec_sub20_rc_sel[1:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:10998.1-11818.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_LDST.dec.LDST_dec31.LDST_dec31_dec_sub21" +attribute \generator "nMigen" +module \LDST_dec31_dec_sub21 + attribute \src "libresoc.v:11229.3-11277.6" + wire $0\LDST_dec31_dec_sub21_br[0:0] + attribute \src "libresoc.v:11572.3-11620.6" + wire width 3 $0\LDST_dec31_dec_sub21_cr_in[2:0] + attribute \src "libresoc.v:11621.3-11669.6" + wire width 3 $0\LDST_dec31_dec_sub21_cr_out[2:0] + attribute \src "libresoc.v:11180.3-11228.6" + wire width 12 $0\LDST_dec31_dec_sub21_function_unit[11:0] + attribute \src "libresoc.v:11474.3-11522.6" + wire width 3 $0\LDST_dec31_dec_sub21_in1_sel[2:0] + attribute \src "libresoc.v:11523.3-11571.6" + wire width 4 $0\LDST_dec31_dec_sub21_in2_sel[3:0] + attribute \src "libresoc.v:11425.3-11473.6" + wire width 7 $0\LDST_dec31_dec_sub21_internal_op[6:0] + attribute \src "libresoc.v:11327.3-11375.6" + wire $0\LDST_dec31_dec_sub21_is_32b[0:0] + attribute \src "libresoc.v:11670.3-11718.6" + wire width 4 $0\LDST_dec31_dec_sub21_ldst_len[3:0] + attribute \src "libresoc.v:11768.3-11816.6" + wire width 2 $0\LDST_dec31_dec_sub21_rc_sel[1:0] + attribute \src "libresoc.v:11376.3-11424.6" + wire $0\LDST_dec31_dec_sub21_sgn[0:0] + attribute \src "libresoc.v:11278.3-11326.6" + wire $0\LDST_dec31_dec_sub21_sgn_ext[0:0] + attribute \src "libresoc.v:11719.3-11767.6" + wire width 2 $0\LDST_dec31_dec_sub21_upd[1:0] + attribute \src "libresoc.v:10999.7-10999.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:11229.3-11277.6" + wire $1\LDST_dec31_dec_sub21_br[0:0] + attribute \src "libresoc.v:11572.3-11620.6" + wire width 3 $1\LDST_dec31_dec_sub21_cr_in[2:0] + attribute \src "libresoc.v:11621.3-11669.6" + wire width 3 $1\LDST_dec31_dec_sub21_cr_out[2:0] + attribute \src "libresoc.v:11180.3-11228.6" + wire width 12 $1\LDST_dec31_dec_sub21_function_unit[11:0] + attribute \src "libresoc.v:11474.3-11522.6" + wire width 3 $1\LDST_dec31_dec_sub21_in1_sel[2:0] + attribute \src "libresoc.v:11523.3-11571.6" + wire width 4 $1\LDST_dec31_dec_sub21_in2_sel[3:0] + attribute \src "libresoc.v:11425.3-11473.6" + wire width 7 $1\LDST_dec31_dec_sub21_internal_op[6:0] + attribute \src "libresoc.v:11327.3-11375.6" + wire $1\LDST_dec31_dec_sub21_is_32b[0:0] + attribute \src "libresoc.v:11670.3-11718.6" + wire width 4 $1\LDST_dec31_dec_sub21_ldst_len[3:0] + attribute \src "libresoc.v:11768.3-11816.6" + wire width 2 $1\LDST_dec31_dec_sub21_rc_sel[1:0] + attribute \src "libresoc.v:11376.3-11424.6" + wire $1\LDST_dec31_dec_sub21_sgn[0:0] + attribute \src "libresoc.v:11278.3-11326.6" + wire $1\LDST_dec31_dec_sub21_sgn_ext[0:0] + attribute \src "libresoc.v:11719.3-11767.6" + wire width 2 $1\LDST_dec31_dec_sub21_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 10 \LDST_dec31_dec_sub21_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \LDST_dec31_dec_sub21_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 6 \LDST_dec31_dec_sub21_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \LDST_dec31_dec_sub21_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 3 \LDST_dec31_dec_sub21_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 4 \LDST_dec31_dec_sub21_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \LDST_dec31_dec_sub21_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 12 \LDST_dec31_dec_sub21_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 7 \LDST_dec31_dec_sub21_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 9 \LDST_dec31_dec_sub21_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 13 \LDST_dec31_dec_sub21_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 11 \LDST_dec31_dec_sub21_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 8 \LDST_dec31_dec_sub21_upd + attribute \src "libresoc.v:10999.7-10999.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 14 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 5 \opcode_switch + attribute \src "libresoc.v:10999.7-10999.20" + process $proc$libresoc.v:10999$237 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:11180.3-11228.6" + process $proc$libresoc.v:11180$224 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub21_function_unit[11:0] $1\LDST_dec31_dec_sub21_function_unit[11:0] + attribute \src "libresoc.v:11181.5-11181.29" + switch \initial + attribute \src "libresoc.v:11181.9-11181.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\LDST_dec31_dec_sub21_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\LDST_dec31_dec_sub21_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub21_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub21_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\LDST_dec31_dec_sub21_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LDST_dec31_dec_sub21_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\LDST_dec31_dec_sub21_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\LDST_dec31_dec_sub21_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\LDST_dec31_dec_sub21_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\LDST_dec31_dec_sub21_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LDST_dec31_dec_sub21_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub21_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\LDST_dec31_dec_sub21_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LDST_dec31_dec_sub21_function_unit[11:0] 12'000000000100 + case + assign $1\LDST_dec31_dec_sub21_function_unit[11:0] 12'000000000000 + end + sync always + update \LDST_dec31_dec_sub21_function_unit $0\LDST_dec31_dec_sub21_function_unit[11:0] + end + attribute \src "libresoc.v:11229.3-11277.6" + process $proc$libresoc.v:11229$225 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub21_br[0:0] $1\LDST_dec31_dec_sub21_br[0:0] + attribute \src "libresoc.v:11230.5-11230.29" + switch \initial + attribute \src "libresoc.v:11230.9-11230.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\LDST_dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\LDST_dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\LDST_dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LDST_dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\LDST_dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\LDST_dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\LDST_dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\LDST_dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LDST_dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\LDST_dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LDST_dec31_dec_sub21_br[0:0] 1'0 + case + assign $1\LDST_dec31_dec_sub21_br[0:0] 1'0 + end + sync always + update \LDST_dec31_dec_sub21_br $0\LDST_dec31_dec_sub21_br[0:0] + end + attribute \src "libresoc.v:11278.3-11326.6" + process $proc$libresoc.v:11278$226 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub21_sgn_ext[0:0] $1\LDST_dec31_dec_sub21_sgn_ext[0:0] + attribute \src "libresoc.v:11279.5-11279.29" + switch \initial + attribute \src "libresoc.v:11279.9-11279.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn_ext[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn_ext[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn_ext[0:0] 1'0 + case + assign $1\LDST_dec31_dec_sub21_sgn_ext[0:0] 1'0 + end + sync always + update \LDST_dec31_dec_sub21_sgn_ext $0\LDST_dec31_dec_sub21_sgn_ext[0:0] + end + attribute \src "libresoc.v:11327.3-11375.6" + process $proc$libresoc.v:11327$227 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub21_is_32b[0:0] $1\LDST_dec31_dec_sub21_is_32b[0:0] + attribute \src "libresoc.v:11328.5-11328.29" + switch \initial + attribute \src "libresoc.v:11328.9-11328.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\LDST_dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\LDST_dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\LDST_dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LDST_dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\LDST_dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\LDST_dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\LDST_dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\LDST_dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LDST_dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\LDST_dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LDST_dec31_dec_sub21_is_32b[0:0] 1'0 + case + assign $1\LDST_dec31_dec_sub21_is_32b[0:0] 1'0 + end + sync always + update \LDST_dec31_dec_sub21_is_32b $0\LDST_dec31_dec_sub21_is_32b[0:0] + end + attribute \src "libresoc.v:11376.3-11424.6" + process $proc$libresoc.v:11376$228 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub21_sgn[0:0] $1\LDST_dec31_dec_sub21_sgn[0:0] + attribute \src "libresoc.v:11377.5-11377.29" + switch \initial + attribute \src "libresoc.v:11377.9-11377.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn[0:0] 1'0 + case + assign $1\LDST_dec31_dec_sub21_sgn[0:0] 1'0 + end + sync always + update \LDST_dec31_dec_sub21_sgn $0\LDST_dec31_dec_sub21_sgn[0:0] + end + attribute \src "libresoc.v:11425.3-11473.6" + process $proc$libresoc.v:11425$229 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub21_internal_op[6:0] $1\LDST_dec31_dec_sub21_internal_op[6:0] + attribute \src "libresoc.v:11426.5-11426.29" + switch \initial + attribute \src "libresoc.v:11426.9-11426.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\LDST_dec31_dec_sub21_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\LDST_dec31_dec_sub21_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub21_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub21_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\LDST_dec31_dec_sub21_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LDST_dec31_dec_sub21_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\LDST_dec31_dec_sub21_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\LDST_dec31_dec_sub21_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\LDST_dec31_dec_sub21_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\LDST_dec31_dec_sub21_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LDST_dec31_dec_sub21_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub21_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\LDST_dec31_dec_sub21_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LDST_dec31_dec_sub21_internal_op[6:0] 7'0100110 + case + assign $1\LDST_dec31_dec_sub21_internal_op[6:0] 7'0000000 + end + sync always + update \LDST_dec31_dec_sub21_internal_op $0\LDST_dec31_dec_sub21_internal_op[6:0] + end + attribute \src "libresoc.v:11474.3-11522.6" + process $proc$libresoc.v:11474$230 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub21_in1_sel[2:0] $1\LDST_dec31_dec_sub21_in1_sel[2:0] + attribute \src "libresoc.v:11475.5-11475.29" + switch \initial + attribute \src "libresoc.v:11475.9-11475.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in1_sel[2:0] 3'010 + case + assign $1\LDST_dec31_dec_sub21_in1_sel[2:0] 3'000 + end + sync always + update \LDST_dec31_dec_sub21_in1_sel $0\LDST_dec31_dec_sub21_in1_sel[2:0] + end + attribute \src "libresoc.v:11523.3-11571.6" + process $proc$libresoc.v:11523$231 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub21_in2_sel[3:0] $1\LDST_dec31_dec_sub21_in2_sel[3:0] + attribute \src "libresoc.v:11524.5-11524.29" + switch \initial + attribute \src "libresoc.v:11524.9-11524.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in2_sel[3:0] 4'0001 + case + assign $1\LDST_dec31_dec_sub21_in2_sel[3:0] 4'0000 + end + sync always + update \LDST_dec31_dec_sub21_in2_sel $0\LDST_dec31_dec_sub21_in2_sel[3:0] + end + attribute \src "libresoc.v:11572.3-11620.6" + process $proc$libresoc.v:11572$232 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub21_cr_in[2:0] $1\LDST_dec31_dec_sub21_cr_in[2:0] + attribute \src "libresoc.v:11573.5-11573.29" + switch \initial + attribute \src "libresoc.v:11573.9-11573.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_in[2:0] 3'000 + case + assign $1\LDST_dec31_dec_sub21_cr_in[2:0] 3'000 + end + sync always + update \LDST_dec31_dec_sub21_cr_in $0\LDST_dec31_dec_sub21_cr_in[2:0] + end + attribute \src "libresoc.v:11621.3-11669.6" + process $proc$libresoc.v:11621$233 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub21_cr_out[2:0] $1\LDST_dec31_dec_sub21_cr_out[2:0] + attribute \src "libresoc.v:11622.5-11622.29" + switch \initial + attribute \src "libresoc.v:11622.9-11622.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_out[2:0] 3'000 + case + assign $1\LDST_dec31_dec_sub21_cr_out[2:0] 3'000 + end + sync always + update \LDST_dec31_dec_sub21_cr_out $0\LDST_dec31_dec_sub21_cr_out[2:0] + end + attribute \src "libresoc.v:11670.3-11718.6" + process $proc$libresoc.v:11670$234 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub21_ldst_len[3:0] $1\LDST_dec31_dec_sub21_ldst_len[3:0] + attribute \src "libresoc.v:11671.5-11671.29" + switch \initial + attribute \src "libresoc.v:11671.9-11671.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\LDST_dec31_dec_sub21_ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\LDST_dec31_dec_sub21_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub21_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub21_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\LDST_dec31_dec_sub21_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LDST_dec31_dec_sub21_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\LDST_dec31_dec_sub21_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\LDST_dec31_dec_sub21_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\LDST_dec31_dec_sub21_ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\LDST_dec31_dec_sub21_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LDST_dec31_dec_sub21_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub21_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\LDST_dec31_dec_sub21_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LDST_dec31_dec_sub21_ldst_len[3:0] 4'0100 + case + assign $1\LDST_dec31_dec_sub21_ldst_len[3:0] 4'0000 + end + sync always + update \LDST_dec31_dec_sub21_ldst_len $0\LDST_dec31_dec_sub21_ldst_len[3:0] + end + attribute \src "libresoc.v:11719.3-11767.6" + process $proc$libresoc.v:11719$235 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub21_upd[1:0] $1\LDST_dec31_dec_sub21_upd[1:0] + attribute \src "libresoc.v:11720.5-11720.29" + switch \initial + attribute \src "libresoc.v:11720.9-11720.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\LDST_dec31_dec_sub21_upd[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\LDST_dec31_dec_sub21_upd[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub21_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub21_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\LDST_dec31_dec_sub21_upd[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LDST_dec31_dec_sub21_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\LDST_dec31_dec_sub21_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\LDST_dec31_dec_sub21_upd[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\LDST_dec31_dec_sub21_upd[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\LDST_dec31_dec_sub21_upd[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LDST_dec31_dec_sub21_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub21_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\LDST_dec31_dec_sub21_upd[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LDST_dec31_dec_sub21_upd[1:0] 2'10 + case + assign $1\LDST_dec31_dec_sub21_upd[1:0] 2'00 + end + sync always + update \LDST_dec31_dec_sub21_upd $0\LDST_dec31_dec_sub21_upd[1:0] + end + attribute \src "libresoc.v:11768.3-11816.6" + process $proc$libresoc.v:11768$236 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub21_rc_sel[1:0] $1\LDST_dec31_dec_sub21_rc_sel[1:0] + attribute \src "libresoc.v:11769.5-11769.29" + switch \initial + attribute \src "libresoc.v:11769.9-11769.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\LDST_dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\LDST_dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\LDST_dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LDST_dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\LDST_dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\LDST_dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\LDST_dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\LDST_dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LDST_dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\LDST_dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LDST_dec31_dec_sub21_rc_sel[1:0] 2'00 + case + assign $1\LDST_dec31_dec_sub21_rc_sel[1:0] 2'00 + end + sync always + update \LDST_dec31_dec_sub21_rc_sel $0\LDST_dec31_dec_sub21_rc_sel[1:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:11822.1-12408.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_LDST.dec.LDST_dec31.LDST_dec31_dec_sub22" +attribute \generator "nMigen" +module \LDST_dec31_dec_sub22 + attribute \src "libresoc.v:12035.3-12065.6" + wire $0\LDST_dec31_dec_sub22_br[0:0] + attribute \src "libresoc.v:12252.3-12282.6" + wire width 3 $0\LDST_dec31_dec_sub22_cr_in[2:0] + attribute \src "libresoc.v:12283.3-12313.6" + wire width 3 $0\LDST_dec31_dec_sub22_cr_out[2:0] + attribute \src "libresoc.v:12004.3-12034.6" + wire width 12 $0\LDST_dec31_dec_sub22_function_unit[11:0] + attribute \src "libresoc.v:12190.3-12220.6" + wire width 3 $0\LDST_dec31_dec_sub22_in1_sel[2:0] + attribute \src "libresoc.v:12221.3-12251.6" + wire width 4 $0\LDST_dec31_dec_sub22_in2_sel[3:0] + attribute \src "libresoc.v:12159.3-12189.6" + wire width 7 $0\LDST_dec31_dec_sub22_internal_op[6:0] + attribute \src "libresoc.v:12097.3-12127.6" + wire $0\LDST_dec31_dec_sub22_is_32b[0:0] + attribute \src "libresoc.v:12314.3-12344.6" + wire width 4 $0\LDST_dec31_dec_sub22_ldst_len[3:0] + attribute \src "libresoc.v:12376.3-12406.6" + wire width 2 $0\LDST_dec31_dec_sub22_rc_sel[1:0] + attribute \src "libresoc.v:12128.3-12158.6" + wire $0\LDST_dec31_dec_sub22_sgn[0:0] + attribute \src "libresoc.v:12066.3-12096.6" + wire $0\LDST_dec31_dec_sub22_sgn_ext[0:0] + attribute \src "libresoc.v:12345.3-12375.6" + wire width 2 $0\LDST_dec31_dec_sub22_upd[1:0] + attribute \src "libresoc.v:11823.7-11823.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:12035.3-12065.6" + wire $1\LDST_dec31_dec_sub22_br[0:0] + attribute \src "libresoc.v:12252.3-12282.6" + wire width 3 $1\LDST_dec31_dec_sub22_cr_in[2:0] + attribute \src "libresoc.v:12283.3-12313.6" + wire width 3 $1\LDST_dec31_dec_sub22_cr_out[2:0] + attribute \src "libresoc.v:12004.3-12034.6" + wire width 12 $1\LDST_dec31_dec_sub22_function_unit[11:0] + attribute \src "libresoc.v:12190.3-12220.6" + wire width 3 $1\LDST_dec31_dec_sub22_in1_sel[2:0] + attribute \src "libresoc.v:12221.3-12251.6" + wire width 4 $1\LDST_dec31_dec_sub22_in2_sel[3:0] + attribute \src "libresoc.v:12159.3-12189.6" + wire width 7 $1\LDST_dec31_dec_sub22_internal_op[6:0] + attribute \src "libresoc.v:12097.3-12127.6" + wire $1\LDST_dec31_dec_sub22_is_32b[0:0] + attribute \src "libresoc.v:12314.3-12344.6" + wire width 4 $1\LDST_dec31_dec_sub22_ldst_len[3:0] + attribute \src "libresoc.v:12376.3-12406.6" + wire width 2 $1\LDST_dec31_dec_sub22_rc_sel[1:0] + attribute \src "libresoc.v:12128.3-12158.6" + wire $1\LDST_dec31_dec_sub22_sgn[0:0] + attribute \src "libresoc.v:12066.3-12096.6" + wire $1\LDST_dec31_dec_sub22_sgn_ext[0:0] + attribute \src "libresoc.v:12345.3-12375.6" + wire width 2 $1\LDST_dec31_dec_sub22_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 10 \LDST_dec31_dec_sub22_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \LDST_dec31_dec_sub22_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 6 \LDST_dec31_dec_sub22_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \LDST_dec31_dec_sub22_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 3 \LDST_dec31_dec_sub22_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 4 \LDST_dec31_dec_sub22_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \LDST_dec31_dec_sub22_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 12 \LDST_dec31_dec_sub22_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 7 \LDST_dec31_dec_sub22_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 9 \LDST_dec31_dec_sub22_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 13 \LDST_dec31_dec_sub22_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 11 \LDST_dec31_dec_sub22_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 8 \LDST_dec31_dec_sub22_upd + attribute \src "libresoc.v:11823.7-11823.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 14 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 5 \opcode_switch + attribute \src "libresoc.v:11823.7-11823.20" + process $proc$libresoc.v:11823$251 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:12004.3-12034.6" + process $proc$libresoc.v:12004$238 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub22_function_unit[11:0] $1\LDST_dec31_dec_sub22_function_unit[11:0] + attribute \src "libresoc.v:12005.5-12005.29" + switch \initial + attribute \src "libresoc.v:12005.9-12005.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\LDST_dec31_dec_sub22_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LDST_dec31_dec_sub22_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\LDST_dec31_dec_sub22_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\LDST_dec31_dec_sub22_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\LDST_dec31_dec_sub22_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_function_unit[11:0] 12'000000000100 + case + assign $1\LDST_dec31_dec_sub22_function_unit[11:0] 12'000000000000 + end + sync always + update \LDST_dec31_dec_sub22_function_unit $0\LDST_dec31_dec_sub22_function_unit[11:0] + end + attribute \src "libresoc.v:12035.3-12065.6" + process $proc$libresoc.v:12035$239 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub22_br[0:0] $1\LDST_dec31_dec_sub22_br[0:0] + attribute \src "libresoc.v:12036.5-12036.29" + switch \initial + attribute \src "libresoc.v:12036.9-12036.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\LDST_dec31_dec_sub22_br[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LDST_dec31_dec_sub22_br[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\LDST_dec31_dec_sub22_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\LDST_dec31_dec_sub22_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_br[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\LDST_dec31_dec_sub22_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_br[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_br[0:0] 1'0 + case + assign $1\LDST_dec31_dec_sub22_br[0:0] 1'0 + end + sync always + update \LDST_dec31_dec_sub22_br $0\LDST_dec31_dec_sub22_br[0:0] + end + attribute \src "libresoc.v:12066.3-12096.6" + process $proc$libresoc.v:12066$240 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub22_sgn_ext[0:0] $1\LDST_dec31_dec_sub22_sgn_ext[0:0] + attribute \src "libresoc.v:12067.5-12067.29" + switch \initial + attribute \src "libresoc.v:12067.9-12067.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\LDST_dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LDST_dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\LDST_dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\LDST_dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\LDST_dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_sgn_ext[0:0] 1'0 + case + assign $1\LDST_dec31_dec_sub22_sgn_ext[0:0] 1'0 + end + sync always + update \LDST_dec31_dec_sub22_sgn_ext $0\LDST_dec31_dec_sub22_sgn_ext[0:0] + end + attribute \src "libresoc.v:12097.3-12127.6" + process $proc$libresoc.v:12097$241 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub22_is_32b[0:0] $1\LDST_dec31_dec_sub22_is_32b[0:0] + attribute \src "libresoc.v:12098.5-12098.29" + switch \initial + attribute \src "libresoc.v:12098.9-12098.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\LDST_dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LDST_dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\LDST_dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\LDST_dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\LDST_dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_is_32b[0:0] 1'0 + case + assign $1\LDST_dec31_dec_sub22_is_32b[0:0] 1'0 + end + sync always + update \LDST_dec31_dec_sub22_is_32b $0\LDST_dec31_dec_sub22_is_32b[0:0] + end + attribute \src "libresoc.v:12128.3-12158.6" + process $proc$libresoc.v:12128$242 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub22_sgn[0:0] $1\LDST_dec31_dec_sub22_sgn[0:0] + attribute \src "libresoc.v:12129.5-12129.29" + switch \initial + attribute \src "libresoc.v:12129.9-12129.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\LDST_dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LDST_dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\LDST_dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\LDST_dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\LDST_dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_sgn[0:0] 1'0 + case + assign $1\LDST_dec31_dec_sub22_sgn[0:0] 1'0 + end + sync always + update \LDST_dec31_dec_sub22_sgn $0\LDST_dec31_dec_sub22_sgn[0:0] + end + attribute \src "libresoc.v:12159.3-12189.6" + process $proc$libresoc.v:12159$243 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub22_internal_op[6:0] $1\LDST_dec31_dec_sub22_internal_op[6:0] + attribute \src "libresoc.v:12160.5-12160.29" + switch \initial + attribute \src "libresoc.v:12160.9-12160.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\LDST_dec31_dec_sub22_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LDST_dec31_dec_sub22_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\LDST_dec31_dec_sub22_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\LDST_dec31_dec_sub22_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\LDST_dec31_dec_sub22_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_internal_op[6:0] 7'0100110 + case + assign $1\LDST_dec31_dec_sub22_internal_op[6:0] 7'0000000 + end + sync always + update \LDST_dec31_dec_sub22_internal_op $0\LDST_dec31_dec_sub22_internal_op[6:0] + end + attribute \src "libresoc.v:12190.3-12220.6" + process $proc$libresoc.v:12190$244 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub22_in1_sel[2:0] $1\LDST_dec31_dec_sub22_in1_sel[2:0] + attribute \src "libresoc.v:12191.5-12191.29" + switch \initial + attribute \src "libresoc.v:12191.9-12191.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\LDST_dec31_dec_sub22_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LDST_dec31_dec_sub22_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\LDST_dec31_dec_sub22_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\LDST_dec31_dec_sub22_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\LDST_dec31_dec_sub22_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_in1_sel[2:0] 3'010 + case + assign $1\LDST_dec31_dec_sub22_in1_sel[2:0] 3'000 + end + sync always + update \LDST_dec31_dec_sub22_in1_sel $0\LDST_dec31_dec_sub22_in1_sel[2:0] + end + attribute \src "libresoc.v:12221.3-12251.6" + process $proc$libresoc.v:12221$245 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub22_in2_sel[3:0] $1\LDST_dec31_dec_sub22_in2_sel[3:0] + attribute \src "libresoc.v:12222.5-12222.29" + switch \initial + attribute \src "libresoc.v:12222.9-12222.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\LDST_dec31_dec_sub22_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LDST_dec31_dec_sub22_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\LDST_dec31_dec_sub22_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\LDST_dec31_dec_sub22_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\LDST_dec31_dec_sub22_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_in2_sel[3:0] 4'0001 + case + assign $1\LDST_dec31_dec_sub22_in2_sel[3:0] 4'0000 + end + sync always + update \LDST_dec31_dec_sub22_in2_sel $0\LDST_dec31_dec_sub22_in2_sel[3:0] + end + attribute \src "libresoc.v:12252.3-12282.6" + process $proc$libresoc.v:12252$246 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub22_cr_in[2:0] $1\LDST_dec31_dec_sub22_cr_in[2:0] + attribute \src "libresoc.v:12253.5-12253.29" + switch \initial + attribute \src "libresoc.v:12253.9-12253.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\LDST_dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LDST_dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\LDST_dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\LDST_dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\LDST_dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_cr_in[2:0] 3'000 + case + assign $1\LDST_dec31_dec_sub22_cr_in[2:0] 3'000 + end + sync always + update \LDST_dec31_dec_sub22_cr_in $0\LDST_dec31_dec_sub22_cr_in[2:0] + end + attribute \src "libresoc.v:12283.3-12313.6" + process $proc$libresoc.v:12283$247 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub22_cr_out[2:0] $1\LDST_dec31_dec_sub22_cr_out[2:0] + attribute \src "libresoc.v:12284.5-12284.29" + switch \initial + attribute \src "libresoc.v:12284.9-12284.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\LDST_dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LDST_dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\LDST_dec31_dec_sub22_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\LDST_dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\LDST_dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_cr_out[2:0] 3'000 + case + assign $1\LDST_dec31_dec_sub22_cr_out[2:0] 3'000 + end + sync always + update \LDST_dec31_dec_sub22_cr_out $0\LDST_dec31_dec_sub22_cr_out[2:0] + end + attribute \src "libresoc.v:12314.3-12344.6" + process $proc$libresoc.v:12314$248 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub22_ldst_len[3:0] $1\LDST_dec31_dec_sub22_ldst_len[3:0] + attribute \src "libresoc.v:12315.5-12315.29" + switch \initial + attribute \src "libresoc.v:12315.9-12315.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\LDST_dec31_dec_sub22_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LDST_dec31_dec_sub22_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\LDST_dec31_dec_sub22_ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\LDST_dec31_dec_sub22_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\LDST_dec31_dec_sub22_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_ldst_len[3:0] 4'0100 + case + assign $1\LDST_dec31_dec_sub22_ldst_len[3:0] 4'0000 + end + sync always + update \LDST_dec31_dec_sub22_ldst_len $0\LDST_dec31_dec_sub22_ldst_len[3:0] + end + attribute \src "libresoc.v:12345.3-12375.6" + process $proc$libresoc.v:12345$249 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub22_upd[1:0] $1\LDST_dec31_dec_sub22_upd[1:0] + attribute \src "libresoc.v:12346.5-12346.29" + switch \initial + attribute \src "libresoc.v:12346.9-12346.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\LDST_dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LDST_dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\LDST_dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\LDST_dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\LDST_dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_upd[1:0] 2'00 + case + assign $1\LDST_dec31_dec_sub22_upd[1:0] 2'00 + end + sync always + update \LDST_dec31_dec_sub22_upd $0\LDST_dec31_dec_sub22_upd[1:0] + end + attribute \src "libresoc.v:12376.3-12406.6" + process $proc$libresoc.v:12376$250 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub22_rc_sel[1:0] $1\LDST_dec31_dec_sub22_rc_sel[1:0] + attribute \src "libresoc.v:12377.5-12377.29" + switch \initial + attribute \src "libresoc.v:12377.9-12377.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\LDST_dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LDST_dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\LDST_dec31_dec_sub22_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\LDST_dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\LDST_dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_rc_sel[1:0] 2'00 + case + assign $1\LDST_dec31_dec_sub22_rc_sel[1:0] 2'00 + end + sync always + update \LDST_dec31_dec_sub22_rc_sel $0\LDST_dec31_dec_sub22_rc_sel[1:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:12412.1-13232.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_LDST.dec.LDST_dec31.LDST_dec31_dec_sub23" +attribute \generator "nMigen" +module \LDST_dec31_dec_sub23 + attribute \src "libresoc.v:12643.3-12691.6" + wire $0\LDST_dec31_dec_sub23_br[0:0] + attribute \src "libresoc.v:12986.3-13034.6" + wire width 3 $0\LDST_dec31_dec_sub23_cr_in[2:0] + attribute \src "libresoc.v:13035.3-13083.6" + wire width 3 $0\LDST_dec31_dec_sub23_cr_out[2:0] + attribute \src "libresoc.v:12594.3-12642.6" + wire width 12 $0\LDST_dec31_dec_sub23_function_unit[11:0] + attribute \src "libresoc.v:12888.3-12936.6" + wire width 3 $0\LDST_dec31_dec_sub23_in1_sel[2:0] + attribute \src "libresoc.v:12937.3-12985.6" + wire width 4 $0\LDST_dec31_dec_sub23_in2_sel[3:0] + attribute \src "libresoc.v:12839.3-12887.6" + wire width 7 $0\LDST_dec31_dec_sub23_internal_op[6:0] + attribute \src "libresoc.v:12741.3-12789.6" + wire $0\LDST_dec31_dec_sub23_is_32b[0:0] + attribute \src "libresoc.v:13084.3-13132.6" + wire width 4 $0\LDST_dec31_dec_sub23_ldst_len[3:0] + attribute \src "libresoc.v:13182.3-13230.6" + wire width 2 $0\LDST_dec31_dec_sub23_rc_sel[1:0] + attribute \src "libresoc.v:12790.3-12838.6" + wire $0\LDST_dec31_dec_sub23_sgn[0:0] + attribute \src "libresoc.v:12692.3-12740.6" + wire $0\LDST_dec31_dec_sub23_sgn_ext[0:0] + attribute \src "libresoc.v:13133.3-13181.6" + wire width 2 $0\LDST_dec31_dec_sub23_upd[1:0] + attribute \src "libresoc.v:12413.7-12413.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:12643.3-12691.6" + wire $1\LDST_dec31_dec_sub23_br[0:0] + attribute \src "libresoc.v:12986.3-13034.6" + wire width 3 $1\LDST_dec31_dec_sub23_cr_in[2:0] + attribute \src "libresoc.v:13035.3-13083.6" + wire width 3 $1\LDST_dec31_dec_sub23_cr_out[2:0] + attribute \src "libresoc.v:12594.3-12642.6" + wire width 12 $1\LDST_dec31_dec_sub23_function_unit[11:0] + attribute \src "libresoc.v:12888.3-12936.6" + wire width 3 $1\LDST_dec31_dec_sub23_in1_sel[2:0] + attribute \src "libresoc.v:12937.3-12985.6" + wire width 4 $1\LDST_dec31_dec_sub23_in2_sel[3:0] + attribute \src "libresoc.v:12839.3-12887.6" + wire width 7 $1\LDST_dec31_dec_sub23_internal_op[6:0] + attribute \src "libresoc.v:12741.3-12789.6" + wire $1\LDST_dec31_dec_sub23_is_32b[0:0] + attribute \src "libresoc.v:13084.3-13132.6" + wire width 4 $1\LDST_dec31_dec_sub23_ldst_len[3:0] + attribute \src "libresoc.v:13182.3-13230.6" + wire width 2 $1\LDST_dec31_dec_sub23_rc_sel[1:0] + attribute \src "libresoc.v:12790.3-12838.6" + wire $1\LDST_dec31_dec_sub23_sgn[0:0] + attribute \src "libresoc.v:12692.3-12740.6" + wire $1\LDST_dec31_dec_sub23_sgn_ext[0:0] + attribute \src "libresoc.v:13133.3-13181.6" + wire width 2 $1\LDST_dec31_dec_sub23_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 10 \LDST_dec31_dec_sub23_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \LDST_dec31_dec_sub23_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 6 \LDST_dec31_dec_sub23_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \LDST_dec31_dec_sub23_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 3 \LDST_dec31_dec_sub23_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 4 \LDST_dec31_dec_sub23_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \LDST_dec31_dec_sub23_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 12 \LDST_dec31_dec_sub23_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 7 \LDST_dec31_dec_sub23_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 9 \LDST_dec31_dec_sub23_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 13 \LDST_dec31_dec_sub23_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 11 \LDST_dec31_dec_sub23_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 8 \LDST_dec31_dec_sub23_upd + attribute \src "libresoc.v:12413.7-12413.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 14 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 5 \opcode_switch + attribute \src "libresoc.v:12413.7-12413.20" + process $proc$libresoc.v:12413$265 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:12594.3-12642.6" + process $proc$libresoc.v:12594$252 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub23_function_unit[11:0] $1\LDST_dec31_dec_sub23_function_unit[11:0] + attribute \src "libresoc.v:12595.5-12595.29" + switch \initial + attribute \src "libresoc.v:12595.9-12595.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LDST_dec31_dec_sub23_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\LDST_dec31_dec_sub23_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LDST_dec31_dec_sub23_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\LDST_dec31_dec_sub23_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\LDST_dec31_dec_sub23_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\LDST_dec31_dec_sub23_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub23_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub23_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\LDST_dec31_dec_sub23_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\LDST_dec31_dec_sub23_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\LDST_dec31_dec_sub23_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\LDST_dec31_dec_sub23_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LDST_dec31_dec_sub23_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub23_function_unit[11:0] 12'000000000100 + case + assign $1\LDST_dec31_dec_sub23_function_unit[11:0] 12'000000000000 + end + sync always + update \LDST_dec31_dec_sub23_function_unit $0\LDST_dec31_dec_sub23_function_unit[11:0] + end + attribute \src "libresoc.v:12643.3-12691.6" + process $proc$libresoc.v:12643$253 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub23_br[0:0] $1\LDST_dec31_dec_sub23_br[0:0] + attribute \src "libresoc.v:12644.5-12644.29" + switch \initial + attribute \src "libresoc.v:12644.9-12644.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LDST_dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\LDST_dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LDST_dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\LDST_dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\LDST_dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\LDST_dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\LDST_dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\LDST_dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\LDST_dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\LDST_dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LDST_dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub23_br[0:0] 1'0 + case + assign $1\LDST_dec31_dec_sub23_br[0:0] 1'0 + end + sync always + update \LDST_dec31_dec_sub23_br $0\LDST_dec31_dec_sub23_br[0:0] + end + attribute \src "libresoc.v:12692.3-12740.6" + process $proc$libresoc.v:12692$254 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub23_sgn_ext[0:0] $1\LDST_dec31_dec_sub23_sgn_ext[0:0] + attribute \src "libresoc.v:12693.5-12693.29" + switch \initial + attribute \src "libresoc.v:12693.9-12693.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn_ext[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn_ext[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn_ext[0:0] 1'0 + case + assign $1\LDST_dec31_dec_sub23_sgn_ext[0:0] 1'0 + end + sync always + update \LDST_dec31_dec_sub23_sgn_ext $0\LDST_dec31_dec_sub23_sgn_ext[0:0] + end + attribute \src "libresoc.v:12741.3-12789.6" + process $proc$libresoc.v:12741$255 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub23_is_32b[0:0] $1\LDST_dec31_dec_sub23_is_32b[0:0] + attribute \src "libresoc.v:12742.5-12742.29" + switch \initial + attribute \src "libresoc.v:12742.9-12742.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LDST_dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\LDST_dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LDST_dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\LDST_dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\LDST_dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\LDST_dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\LDST_dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\LDST_dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\LDST_dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\LDST_dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LDST_dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub23_is_32b[0:0] 1'0 + case + assign $1\LDST_dec31_dec_sub23_is_32b[0:0] 1'0 + end + sync always + update \LDST_dec31_dec_sub23_is_32b $0\LDST_dec31_dec_sub23_is_32b[0:0] + end + attribute \src "libresoc.v:12790.3-12838.6" + process $proc$libresoc.v:12790$256 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub23_sgn[0:0] $1\LDST_dec31_dec_sub23_sgn[0:0] + attribute \src "libresoc.v:12791.5-12791.29" + switch \initial + attribute \src "libresoc.v:12791.9-12791.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn[0:0] 1'0 + case + assign $1\LDST_dec31_dec_sub23_sgn[0:0] 1'0 + end + sync always + update \LDST_dec31_dec_sub23_sgn $0\LDST_dec31_dec_sub23_sgn[0:0] + end + attribute \src "libresoc.v:12839.3-12887.6" + process $proc$libresoc.v:12839$257 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub23_internal_op[6:0] $1\LDST_dec31_dec_sub23_internal_op[6:0] + attribute \src "libresoc.v:12840.5-12840.29" + switch \initial + attribute \src "libresoc.v:12840.9-12840.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LDST_dec31_dec_sub23_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\LDST_dec31_dec_sub23_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LDST_dec31_dec_sub23_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\LDST_dec31_dec_sub23_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\LDST_dec31_dec_sub23_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\LDST_dec31_dec_sub23_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub23_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub23_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\LDST_dec31_dec_sub23_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\LDST_dec31_dec_sub23_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\LDST_dec31_dec_sub23_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\LDST_dec31_dec_sub23_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LDST_dec31_dec_sub23_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub23_internal_op[6:0] 7'0100110 + case + assign $1\LDST_dec31_dec_sub23_internal_op[6:0] 7'0000000 + end + sync always + update \LDST_dec31_dec_sub23_internal_op $0\LDST_dec31_dec_sub23_internal_op[6:0] + end + attribute \src "libresoc.v:12888.3-12936.6" + process $proc$libresoc.v:12888$258 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub23_in1_sel[2:0] $1\LDST_dec31_dec_sub23_in1_sel[2:0] + attribute \src "libresoc.v:12889.5-12889.29" + switch \initial + attribute \src "libresoc.v:12889.9-12889.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in1_sel[2:0] 3'010 + case + assign $1\LDST_dec31_dec_sub23_in1_sel[2:0] 3'000 + end + sync always + update \LDST_dec31_dec_sub23_in1_sel $0\LDST_dec31_dec_sub23_in1_sel[2:0] + end + attribute \src "libresoc.v:12937.3-12985.6" + process $proc$libresoc.v:12937$259 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub23_in2_sel[3:0] $1\LDST_dec31_dec_sub23_in2_sel[3:0] + attribute \src "libresoc.v:12938.5-12938.29" + switch \initial + attribute \src "libresoc.v:12938.9-12938.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in2_sel[3:0] 4'0001 + case + assign $1\LDST_dec31_dec_sub23_in2_sel[3:0] 4'0000 + end + sync always + update \LDST_dec31_dec_sub23_in2_sel $0\LDST_dec31_dec_sub23_in2_sel[3:0] + end + attribute \src "libresoc.v:12986.3-13034.6" + process $proc$libresoc.v:12986$260 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub23_cr_in[2:0] $1\LDST_dec31_dec_sub23_cr_in[2:0] + attribute \src "libresoc.v:12987.5-12987.29" + switch \initial + attribute \src "libresoc.v:12987.9-12987.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_in[2:0] 3'000 + case + assign $1\LDST_dec31_dec_sub23_cr_in[2:0] 3'000 + end + sync always + update \LDST_dec31_dec_sub23_cr_in $0\LDST_dec31_dec_sub23_cr_in[2:0] + end + attribute \src "libresoc.v:13035.3-13083.6" + process $proc$libresoc.v:13035$261 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub23_cr_out[2:0] $1\LDST_dec31_dec_sub23_cr_out[2:0] + attribute \src "libresoc.v:13036.5-13036.29" + switch \initial + attribute \src "libresoc.v:13036.9-13036.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_out[2:0] 3'000 + case + assign $1\LDST_dec31_dec_sub23_cr_out[2:0] 3'000 + end + sync always + update \LDST_dec31_dec_sub23_cr_out $0\LDST_dec31_dec_sub23_cr_out[2:0] + end + attribute \src "libresoc.v:13084.3-13132.6" + process $proc$libresoc.v:13084$262 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub23_ldst_len[3:0] $1\LDST_dec31_dec_sub23_ldst_len[3:0] + attribute \src "libresoc.v:13085.5-13085.29" + switch \initial + attribute \src "libresoc.v:13085.9-13085.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LDST_dec31_dec_sub23_ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\LDST_dec31_dec_sub23_ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LDST_dec31_dec_sub23_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\LDST_dec31_dec_sub23_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\LDST_dec31_dec_sub23_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\LDST_dec31_dec_sub23_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub23_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub23_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\LDST_dec31_dec_sub23_ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\LDST_dec31_dec_sub23_ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\LDST_dec31_dec_sub23_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\LDST_dec31_dec_sub23_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LDST_dec31_dec_sub23_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub23_ldst_len[3:0] 4'0100 + case + assign $1\LDST_dec31_dec_sub23_ldst_len[3:0] 4'0000 + end + sync always + update \LDST_dec31_dec_sub23_ldst_len $0\LDST_dec31_dec_sub23_ldst_len[3:0] + end + attribute \src "libresoc.v:13133.3-13181.6" + process $proc$libresoc.v:13133$263 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub23_upd[1:0] $1\LDST_dec31_dec_sub23_upd[1:0] + attribute \src "libresoc.v:13134.5-13134.29" + switch \initial + attribute \src "libresoc.v:13134.9-13134.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LDST_dec31_dec_sub23_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\LDST_dec31_dec_sub23_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LDST_dec31_dec_sub23_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\LDST_dec31_dec_sub23_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\LDST_dec31_dec_sub23_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\LDST_dec31_dec_sub23_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub23_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub23_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\LDST_dec31_dec_sub23_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\LDST_dec31_dec_sub23_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\LDST_dec31_dec_sub23_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\LDST_dec31_dec_sub23_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LDST_dec31_dec_sub23_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub23_upd[1:0] 2'00 + case + assign $1\LDST_dec31_dec_sub23_upd[1:0] 2'00 + end + sync always + update \LDST_dec31_dec_sub23_upd $0\LDST_dec31_dec_sub23_upd[1:0] + end + attribute \src "libresoc.v:13182.3-13230.6" + process $proc$libresoc.v:13182$264 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub23_rc_sel[1:0] $1\LDST_dec31_dec_sub23_rc_sel[1:0] + attribute \src "libresoc.v:13183.5-13183.29" + switch \initial + attribute \src "libresoc.v:13183.9-13183.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LDST_dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\LDST_dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LDST_dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\LDST_dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\LDST_dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\LDST_dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\LDST_dec31_dec_sub23_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\LDST_dec31_dec_sub23_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\LDST_dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\LDST_dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LDST_dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub23_rc_sel[1:0] 2'00 + case + assign $1\LDST_dec31_dec_sub23_rc_sel[1:0] 2'00 + end + sync always + update \LDST_dec31_dec_sub23_rc_sel $0\LDST_dec31_dec_sub23_rc_sel[1:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:13236.1-13627.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_LDST.dec.LDST_dec58" +attribute \generator "nMigen" +module \LDST_dec58 + attribute \src "libresoc.v:13434.3-13449.6" + wire $0\LDST_dec58_br[0:0] + attribute \src "libresoc.v:13546.3-13561.6" + wire width 3 $0\LDST_dec58_cr_in[2:0] + attribute \src "libresoc.v:13562.3-13577.6" + wire width 3 $0\LDST_dec58_cr_out[2:0] + attribute \src "libresoc.v:13418.3-13433.6" + wire width 12 $0\LDST_dec58_function_unit[11:0] + attribute \src "libresoc.v:13514.3-13529.6" + wire width 3 $0\LDST_dec58_in1_sel[2:0] + attribute \src "libresoc.v:13530.3-13545.6" + wire width 4 $0\LDST_dec58_in2_sel[3:0] + attribute \src "libresoc.v:13498.3-13513.6" + wire width 7 $0\LDST_dec58_internal_op[6:0] + attribute \src "libresoc.v:13466.3-13481.6" + wire $0\LDST_dec58_is_32b[0:0] + attribute \src "libresoc.v:13578.3-13593.6" + wire width 4 $0\LDST_dec58_ldst_len[3:0] + attribute \src "libresoc.v:13610.3-13625.6" + wire width 2 $0\LDST_dec58_rc_sel[1:0] + attribute \src "libresoc.v:13482.3-13497.6" + wire $0\LDST_dec58_sgn[0:0] + attribute \src "libresoc.v:13450.3-13465.6" + wire $0\LDST_dec58_sgn_ext[0:0] + attribute \src "libresoc.v:13594.3-13609.6" + wire width 2 $0\LDST_dec58_upd[1:0] + attribute \src "libresoc.v:13237.7-13237.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:13434.3-13449.6" + wire $1\LDST_dec58_br[0:0] + attribute \src "libresoc.v:13546.3-13561.6" + wire width 3 $1\LDST_dec58_cr_in[2:0] + attribute \src "libresoc.v:13562.3-13577.6" + wire width 3 $1\LDST_dec58_cr_out[2:0] + attribute \src "libresoc.v:13418.3-13433.6" + wire width 12 $1\LDST_dec58_function_unit[11:0] + attribute \src "libresoc.v:13514.3-13529.6" + wire width 3 $1\LDST_dec58_in1_sel[2:0] + attribute \src "libresoc.v:13530.3-13545.6" + wire width 4 $1\LDST_dec58_in2_sel[3:0] + attribute \src "libresoc.v:13498.3-13513.6" + wire width 7 $1\LDST_dec58_internal_op[6:0] + attribute \src "libresoc.v:13466.3-13481.6" + wire $1\LDST_dec58_is_32b[0:0] + attribute \src "libresoc.v:13578.3-13593.6" + wire width 4 $1\LDST_dec58_ldst_len[3:0] + attribute \src "libresoc.v:13610.3-13625.6" + wire width 2 $1\LDST_dec58_rc_sel[1:0] + attribute \src "libresoc.v:13482.3-13497.6" + wire $1\LDST_dec58_sgn[0:0] + attribute \src "libresoc.v:13450.3-13465.6" + wire $1\LDST_dec58_sgn_ext[0:0] + attribute \src "libresoc.v:13594.3-13609.6" + wire width 2 $1\LDST_dec58_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 10 \LDST_dec58_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \LDST_dec58_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 6 \LDST_dec58_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \LDST_dec58_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 3 \LDST_dec58_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 4 \LDST_dec58_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \LDST_dec58_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 12 \LDST_dec58_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 7 \LDST_dec58_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 9 \LDST_dec58_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 13 \LDST_dec58_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 11 \LDST_dec58_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 8 \LDST_dec58_upd + attribute \src "libresoc.v:13237.7-13237.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 14 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 2 \opcode_switch + attribute \src "libresoc.v:13237.7-13237.20" + process $proc$libresoc.v:13237$279 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:13418.3-13433.6" + process $proc$libresoc.v:13418$266 + assign { } { } + assign { } { } + assign $0\LDST_dec58_function_unit[11:0] $1\LDST_dec58_function_unit[11:0] + attribute \src "libresoc.v:13419.5-13419.29" + switch \initial + attribute \src "libresoc.v:13419.9-13419.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\LDST_dec58_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\LDST_dec58_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\LDST_dec58_function_unit[11:0] 12'000000000100 + case + assign $1\LDST_dec58_function_unit[11:0] 12'000000000000 + end + sync always + update \LDST_dec58_function_unit $0\LDST_dec58_function_unit[11:0] + end + attribute \src "libresoc.v:13434.3-13449.6" + process $proc$libresoc.v:13434$267 + assign { } { } + assign { } { } + assign $0\LDST_dec58_br[0:0] $1\LDST_dec58_br[0:0] + attribute \src "libresoc.v:13435.5-13435.29" + switch \initial + attribute \src "libresoc.v:13435.9-13435.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\LDST_dec58_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\LDST_dec58_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\LDST_dec58_br[0:0] 1'0 + case + assign $1\LDST_dec58_br[0:0] 1'0 + end + sync always + update \LDST_dec58_br $0\LDST_dec58_br[0:0] + end + attribute \src "libresoc.v:13450.3-13465.6" + process $proc$libresoc.v:13450$268 + assign { } { } + assign { } { } + assign $0\LDST_dec58_sgn_ext[0:0] $1\LDST_dec58_sgn_ext[0:0] + attribute \src "libresoc.v:13451.5-13451.29" + switch \initial + attribute \src "libresoc.v:13451.9-13451.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\LDST_dec58_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\LDST_dec58_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\LDST_dec58_sgn_ext[0:0] 1'1 + case + assign $1\LDST_dec58_sgn_ext[0:0] 1'0 + end + sync always + update \LDST_dec58_sgn_ext $0\LDST_dec58_sgn_ext[0:0] + end + attribute \src "libresoc.v:13466.3-13481.6" + process $proc$libresoc.v:13466$269 + assign { } { } + assign { } { } + assign $0\LDST_dec58_is_32b[0:0] $1\LDST_dec58_is_32b[0:0] + attribute \src "libresoc.v:13467.5-13467.29" + switch \initial + attribute \src "libresoc.v:13467.9-13467.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\LDST_dec58_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\LDST_dec58_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\LDST_dec58_is_32b[0:0] 1'0 + case + assign $1\LDST_dec58_is_32b[0:0] 1'0 + end + sync always + update \LDST_dec58_is_32b $0\LDST_dec58_is_32b[0:0] + end + attribute \src "libresoc.v:13482.3-13497.6" + process $proc$libresoc.v:13482$270 + assign { } { } + assign { } { } + assign $0\LDST_dec58_sgn[0:0] $1\LDST_dec58_sgn[0:0] + attribute \src "libresoc.v:13483.5-13483.29" + switch \initial + attribute \src "libresoc.v:13483.9-13483.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\LDST_dec58_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\LDST_dec58_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\LDST_dec58_sgn[0:0] 1'0 + case + assign $1\LDST_dec58_sgn[0:0] 1'0 + end + sync always + update \LDST_dec58_sgn $0\LDST_dec58_sgn[0:0] + end + attribute \src "libresoc.v:13498.3-13513.6" + process $proc$libresoc.v:13498$271 + assign { } { } + assign { } { } + assign $0\LDST_dec58_internal_op[6:0] $1\LDST_dec58_internal_op[6:0] + attribute \src "libresoc.v:13499.5-13499.29" + switch \initial + attribute \src "libresoc.v:13499.9-13499.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\LDST_dec58_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\LDST_dec58_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\LDST_dec58_internal_op[6:0] 7'0100101 + case + assign $1\LDST_dec58_internal_op[6:0] 7'0000000 + end + sync always + update \LDST_dec58_internal_op $0\LDST_dec58_internal_op[6:0] + end + attribute \src "libresoc.v:13514.3-13529.6" + process $proc$libresoc.v:13514$272 + assign { } { } + assign { } { } + assign $0\LDST_dec58_in1_sel[2:0] $1\LDST_dec58_in1_sel[2:0] + attribute \src "libresoc.v:13515.5-13515.29" + switch \initial + attribute \src "libresoc.v:13515.9-13515.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\LDST_dec58_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\LDST_dec58_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\LDST_dec58_in1_sel[2:0] 3'010 + case + assign $1\LDST_dec58_in1_sel[2:0] 3'000 + end + sync always + update \LDST_dec58_in1_sel $0\LDST_dec58_in1_sel[2:0] + end + attribute \src "libresoc.v:13530.3-13545.6" + process $proc$libresoc.v:13530$273 + assign { } { } + assign { } { } + assign $0\LDST_dec58_in2_sel[3:0] $1\LDST_dec58_in2_sel[3:0] + attribute \src "libresoc.v:13531.5-13531.29" + switch \initial + attribute \src "libresoc.v:13531.9-13531.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\LDST_dec58_in2_sel[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\LDST_dec58_in2_sel[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\LDST_dec58_in2_sel[3:0] 4'1000 + case + assign $1\LDST_dec58_in2_sel[3:0] 4'0000 + end + sync always + update \LDST_dec58_in2_sel $0\LDST_dec58_in2_sel[3:0] + end + attribute \src "libresoc.v:13546.3-13561.6" + process $proc$libresoc.v:13546$274 + assign { } { } + assign { } { } + assign $0\LDST_dec58_cr_in[2:0] $1\LDST_dec58_cr_in[2:0] + attribute \src "libresoc.v:13547.5-13547.29" + switch \initial + attribute \src "libresoc.v:13547.9-13547.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\LDST_dec58_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\LDST_dec58_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\LDST_dec58_cr_in[2:0] 3'000 + case + assign $1\LDST_dec58_cr_in[2:0] 3'000 + end + sync always + update \LDST_dec58_cr_in $0\LDST_dec58_cr_in[2:0] + end + attribute \src "libresoc.v:13562.3-13577.6" + process $proc$libresoc.v:13562$275 + assign { } { } + assign { } { } + assign $0\LDST_dec58_cr_out[2:0] $1\LDST_dec58_cr_out[2:0] + attribute \src "libresoc.v:13563.5-13563.29" + switch \initial + attribute \src "libresoc.v:13563.9-13563.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\LDST_dec58_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\LDST_dec58_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\LDST_dec58_cr_out[2:0] 3'000 + case + assign $1\LDST_dec58_cr_out[2:0] 3'000 + end + sync always + update \LDST_dec58_cr_out $0\LDST_dec58_cr_out[2:0] + end + attribute \src "libresoc.v:13578.3-13593.6" + process $proc$libresoc.v:13578$276 + assign { } { } + assign { } { } + assign $0\LDST_dec58_ldst_len[3:0] $1\LDST_dec58_ldst_len[3:0] + attribute \src "libresoc.v:13579.5-13579.29" + switch \initial + attribute \src "libresoc.v:13579.9-13579.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\LDST_dec58_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\LDST_dec58_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\LDST_dec58_ldst_len[3:0] 4'0100 + case + assign $1\LDST_dec58_ldst_len[3:0] 4'0000 + end + sync always + update \LDST_dec58_ldst_len $0\LDST_dec58_ldst_len[3:0] + end + attribute \src "libresoc.v:13594.3-13609.6" + process $proc$libresoc.v:13594$277 + assign { } { } + assign { } { } + assign $0\LDST_dec58_upd[1:0] $1\LDST_dec58_upd[1:0] + attribute \src "libresoc.v:13595.5-13595.29" + switch \initial + attribute \src "libresoc.v:13595.9-13595.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\LDST_dec58_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\LDST_dec58_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\LDST_dec58_upd[1:0] 2'00 + case + assign $1\LDST_dec58_upd[1:0] 2'00 + end + sync always + update \LDST_dec58_upd $0\LDST_dec58_upd[1:0] + end + attribute \src "libresoc.v:13610.3-13625.6" + process $proc$libresoc.v:13610$278 + assign { } { } + assign { } { } + assign $0\LDST_dec58_rc_sel[1:0] $1\LDST_dec58_rc_sel[1:0] + attribute \src "libresoc.v:13611.5-13611.29" + switch \initial + attribute \src "libresoc.v:13611.9-13611.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\LDST_dec58_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\LDST_dec58_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\LDST_dec58_rc_sel[1:0] 2'00 + case + assign $1\LDST_dec58_rc_sel[1:0] 2'00 + end + sync always + update \LDST_dec58_rc_sel $0\LDST_dec58_rc_sel[1:0] + end + connect \opcode_switch \opcode_in [1:0] +end +attribute \src "libresoc.v:13631.1-13983.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_LDST.dec.LDST_dec62" +attribute \generator "nMigen" +module \LDST_dec62 + attribute \src "libresoc.v:13826.3-13838.6" + wire $0\LDST_dec62_br[0:0] + attribute \src "libresoc.v:13917.3-13929.6" + wire width 3 $0\LDST_dec62_cr_in[2:0] + attribute \src "libresoc.v:13930.3-13942.6" + wire width 3 $0\LDST_dec62_cr_out[2:0] + attribute \src "libresoc.v:13813.3-13825.6" + wire width 12 $0\LDST_dec62_function_unit[11:0] + attribute \src "libresoc.v:13891.3-13903.6" + wire width 3 $0\LDST_dec62_in1_sel[2:0] + attribute \src "libresoc.v:13904.3-13916.6" + wire width 4 $0\LDST_dec62_in2_sel[3:0] + attribute \src "libresoc.v:13878.3-13890.6" + wire width 7 $0\LDST_dec62_internal_op[6:0] + attribute \src "libresoc.v:13852.3-13864.6" + wire $0\LDST_dec62_is_32b[0:0] + attribute \src "libresoc.v:13943.3-13955.6" + wire width 4 $0\LDST_dec62_ldst_len[3:0] + attribute \src "libresoc.v:13969.3-13981.6" + wire width 2 $0\LDST_dec62_rc_sel[1:0] + attribute \src "libresoc.v:13865.3-13877.6" + wire $0\LDST_dec62_sgn[0:0] + attribute \src "libresoc.v:13839.3-13851.6" + wire $0\LDST_dec62_sgn_ext[0:0] + attribute \src "libresoc.v:13956.3-13968.6" + wire width 2 $0\LDST_dec62_upd[1:0] + attribute \src "libresoc.v:13632.7-13632.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:13826.3-13838.6" + wire $1\LDST_dec62_br[0:0] + attribute \src "libresoc.v:13917.3-13929.6" + wire width 3 $1\LDST_dec62_cr_in[2:0] + attribute \src "libresoc.v:13930.3-13942.6" + wire width 3 $1\LDST_dec62_cr_out[2:0] + attribute \src "libresoc.v:13813.3-13825.6" + wire width 12 $1\LDST_dec62_function_unit[11:0] + attribute \src "libresoc.v:13891.3-13903.6" + wire width 3 $1\LDST_dec62_in1_sel[2:0] + attribute \src "libresoc.v:13904.3-13916.6" + wire width 4 $1\LDST_dec62_in2_sel[3:0] + attribute \src "libresoc.v:13878.3-13890.6" + wire width 7 $1\LDST_dec62_internal_op[6:0] + attribute \src "libresoc.v:13852.3-13864.6" + wire $1\LDST_dec62_is_32b[0:0] + attribute \src "libresoc.v:13943.3-13955.6" + wire width 4 $1\LDST_dec62_ldst_len[3:0] + attribute \src "libresoc.v:13969.3-13981.6" + wire width 2 $1\LDST_dec62_rc_sel[1:0] + attribute \src "libresoc.v:13865.3-13877.6" + wire $1\LDST_dec62_sgn[0:0] + attribute \src "libresoc.v:13839.3-13851.6" + wire $1\LDST_dec62_sgn_ext[0:0] + attribute \src "libresoc.v:13956.3-13968.6" + wire width 2 $1\LDST_dec62_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 10 \LDST_dec62_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \LDST_dec62_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 6 \LDST_dec62_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \LDST_dec62_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 3 \LDST_dec62_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 4 \LDST_dec62_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \LDST_dec62_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 12 \LDST_dec62_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 7 \LDST_dec62_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 9 \LDST_dec62_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 13 \LDST_dec62_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 11 \LDST_dec62_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 8 \LDST_dec62_upd + attribute \src "libresoc.v:13632.7-13632.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 14 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 2 \opcode_switch + attribute \src "libresoc.v:13632.7-13632.20" + process $proc$libresoc.v:13632$293 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:13813.3-13825.6" + process $proc$libresoc.v:13813$280 + assign { } { } + assign { } { } + assign $0\LDST_dec62_function_unit[11:0] $1\LDST_dec62_function_unit[11:0] + attribute \src "libresoc.v:13814.5-13814.29" + switch \initial + attribute \src "libresoc.v:13814.9-13814.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\LDST_dec62_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\LDST_dec62_function_unit[11:0] 12'000000000100 + case + assign $1\LDST_dec62_function_unit[11:0] 12'000000000000 + end + sync always + update \LDST_dec62_function_unit $0\LDST_dec62_function_unit[11:0] + end + attribute \src "libresoc.v:13826.3-13838.6" + process $proc$libresoc.v:13826$281 + assign { } { } + assign { } { } + assign $0\LDST_dec62_br[0:0] $1\LDST_dec62_br[0:0] + attribute \src "libresoc.v:13827.5-13827.29" + switch \initial + attribute \src "libresoc.v:13827.9-13827.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\LDST_dec62_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\LDST_dec62_br[0:0] 1'0 + case + assign $1\LDST_dec62_br[0:0] 1'0 + end + sync always + update \LDST_dec62_br $0\LDST_dec62_br[0:0] + end + attribute \src "libresoc.v:13839.3-13851.6" + process $proc$libresoc.v:13839$282 + assign { } { } + assign { } { } + assign $0\LDST_dec62_sgn_ext[0:0] $1\LDST_dec62_sgn_ext[0:0] + attribute \src "libresoc.v:13840.5-13840.29" + switch \initial + attribute \src "libresoc.v:13840.9-13840.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\LDST_dec62_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\LDST_dec62_sgn_ext[0:0] 1'0 + case + assign $1\LDST_dec62_sgn_ext[0:0] 1'0 + end + sync always + update \LDST_dec62_sgn_ext $0\LDST_dec62_sgn_ext[0:0] + end + attribute \src "libresoc.v:13852.3-13864.6" + process $proc$libresoc.v:13852$283 + assign { } { } + assign { } { } + assign $0\LDST_dec62_is_32b[0:0] $1\LDST_dec62_is_32b[0:0] + attribute \src "libresoc.v:13853.5-13853.29" + switch \initial + attribute \src "libresoc.v:13853.9-13853.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\LDST_dec62_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\LDST_dec62_is_32b[0:0] 1'0 + case + assign $1\LDST_dec62_is_32b[0:0] 1'0 + end + sync always + update \LDST_dec62_is_32b $0\LDST_dec62_is_32b[0:0] + end + attribute \src "libresoc.v:13865.3-13877.6" + process $proc$libresoc.v:13865$284 + assign { } { } + assign { } { } + assign $0\LDST_dec62_sgn[0:0] $1\LDST_dec62_sgn[0:0] + attribute \src "libresoc.v:13866.5-13866.29" + switch \initial + attribute \src "libresoc.v:13866.9-13866.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\LDST_dec62_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\LDST_dec62_sgn[0:0] 1'0 + case + assign $1\LDST_dec62_sgn[0:0] 1'0 + end + sync always + update \LDST_dec62_sgn $0\LDST_dec62_sgn[0:0] + end + attribute \src "libresoc.v:13878.3-13890.6" + process $proc$libresoc.v:13878$285 + assign { } { } + assign { } { } + assign $0\LDST_dec62_internal_op[6:0] $1\LDST_dec62_internal_op[6:0] + attribute \src "libresoc.v:13879.5-13879.29" + switch \initial + attribute \src "libresoc.v:13879.9-13879.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\LDST_dec62_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\LDST_dec62_internal_op[6:0] 7'0100110 + case + assign $1\LDST_dec62_internal_op[6:0] 7'0000000 + end + sync always + update \LDST_dec62_internal_op $0\LDST_dec62_internal_op[6:0] + end + attribute \src "libresoc.v:13891.3-13903.6" + process $proc$libresoc.v:13891$286 + assign { } { } + assign { } { } + assign $0\LDST_dec62_in1_sel[2:0] $1\LDST_dec62_in1_sel[2:0] + attribute \src "libresoc.v:13892.5-13892.29" + switch \initial + attribute \src "libresoc.v:13892.9-13892.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\LDST_dec62_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\LDST_dec62_in1_sel[2:0] 3'010 + case + assign $1\LDST_dec62_in1_sel[2:0] 3'000 + end + sync always + update \LDST_dec62_in1_sel $0\LDST_dec62_in1_sel[2:0] + end + attribute \src "libresoc.v:13904.3-13916.6" + process $proc$libresoc.v:13904$287 + assign { } { } + assign { } { } + assign $0\LDST_dec62_in2_sel[3:0] $1\LDST_dec62_in2_sel[3:0] + attribute \src "libresoc.v:13905.5-13905.29" + switch \initial + attribute \src "libresoc.v:13905.9-13905.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\LDST_dec62_in2_sel[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\LDST_dec62_in2_sel[3:0] 4'1000 + case + assign $1\LDST_dec62_in2_sel[3:0] 4'0000 + end + sync always + update \LDST_dec62_in2_sel $0\LDST_dec62_in2_sel[3:0] + end + attribute \src "libresoc.v:13917.3-13929.6" + process $proc$libresoc.v:13917$288 + assign { } { } + assign { } { } + assign $0\LDST_dec62_cr_in[2:0] $1\LDST_dec62_cr_in[2:0] + attribute \src "libresoc.v:13918.5-13918.29" + switch \initial + attribute \src "libresoc.v:13918.9-13918.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\LDST_dec62_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\LDST_dec62_cr_in[2:0] 3'000 + case + assign $1\LDST_dec62_cr_in[2:0] 3'000 + end + sync always + update \LDST_dec62_cr_in $0\LDST_dec62_cr_in[2:0] + end + attribute \src "libresoc.v:13930.3-13942.6" + process $proc$libresoc.v:13930$289 + assign { } { } + assign { } { } + assign $0\LDST_dec62_cr_out[2:0] $1\LDST_dec62_cr_out[2:0] + attribute \src "libresoc.v:13931.5-13931.29" + switch \initial + attribute \src "libresoc.v:13931.9-13931.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\LDST_dec62_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\LDST_dec62_cr_out[2:0] 3'000 + case + assign $1\LDST_dec62_cr_out[2:0] 3'000 + end + sync always + update \LDST_dec62_cr_out $0\LDST_dec62_cr_out[2:0] + end + attribute \src "libresoc.v:13943.3-13955.6" + process $proc$libresoc.v:13943$290 + assign { } { } + assign { } { } + assign $0\LDST_dec62_ldst_len[3:0] $1\LDST_dec62_ldst_len[3:0] + attribute \src "libresoc.v:13944.5-13944.29" + switch \initial + attribute \src "libresoc.v:13944.9-13944.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\LDST_dec62_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\LDST_dec62_ldst_len[3:0] 4'1000 + case + assign $1\LDST_dec62_ldst_len[3:0] 4'0000 + end + sync always + update \LDST_dec62_ldst_len $0\LDST_dec62_ldst_len[3:0] + end + attribute \src "libresoc.v:13956.3-13968.6" + process $proc$libresoc.v:13956$291 + assign { } { } + assign { } { } + assign $0\LDST_dec62_upd[1:0] $1\LDST_dec62_upd[1:0] + attribute \src "libresoc.v:13957.5-13957.29" + switch \initial + attribute \src "libresoc.v:13957.9-13957.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\LDST_dec62_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\LDST_dec62_upd[1:0] 2'01 + case + assign $1\LDST_dec62_upd[1:0] 2'00 + end + sync always + update \LDST_dec62_upd $0\LDST_dec62_upd[1:0] + end + attribute \src "libresoc.v:13969.3-13981.6" + process $proc$libresoc.v:13969$292 + assign { } { } + assign { } { } + assign $0\LDST_dec62_rc_sel[1:0] $1\LDST_dec62_rc_sel[1:0] + attribute \src "libresoc.v:13970.5-13970.29" + switch \initial + attribute \src "libresoc.v:13970.9-13970.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\LDST_dec62_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\LDST_dec62_rc_sel[1:0] 2'00 + case + assign $1\LDST_dec62_rc_sel[1:0] 2'00 + end + sync always + update \LDST_dec62_rc_sel $0\LDST_dec62_rc_sel[1:0] + end + connect \opcode_switch \opcode_in [1:0] +end +attribute \src "libresoc.v:13987.1-14725.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_LOGICAL.dec.LOGICAL_dec31" +attribute \generator "nMigen" +module \LOGICAL_dec31 + attribute \src "libresoc.v:14695.3-14707.6" + wire width 3 $0\LOGICAL_dec31_cr_in[2:0] + attribute \src "libresoc.v:14708.3-14720.6" + wire width 3 $0\LOGICAL_dec31_cr_out[2:0] + attribute \src "libresoc.v:14565.3-14577.6" + wire width 2 $0\LOGICAL_dec31_cry_in[1:0] + attribute \src "libresoc.v:14604.3-14616.6" + wire $0\LOGICAL_dec31_cry_out[0:0] + attribute \src "libresoc.v:14643.3-14655.6" + wire width 12 $0\LOGICAL_dec31_function_unit[11:0] + attribute \src "libresoc.v:14669.3-14681.6" + wire width 3 $0\LOGICAL_dec31_in1_sel[2:0] + attribute \src "libresoc.v:14682.3-14694.6" + wire width 4 $0\LOGICAL_dec31_in2_sel[3:0] + attribute \src "libresoc.v:14656.3-14668.6" + wire width 7 $0\LOGICAL_dec31_internal_op[6:0] + attribute \src "libresoc.v:14578.3-14590.6" + wire $0\LOGICAL_dec31_inv_a[0:0] + attribute \src "libresoc.v:14591.3-14603.6" + wire $0\LOGICAL_dec31_inv_out[0:0] + attribute \src "libresoc.v:14617.3-14629.6" + wire $0\LOGICAL_dec31_is_32b[0:0] + attribute \src "libresoc.v:14539.3-14551.6" + wire width 4 $0\LOGICAL_dec31_ldst_len[3:0] + attribute \src "libresoc.v:14552.3-14564.6" + wire width 2 $0\LOGICAL_dec31_rc_sel[1:0] + attribute \src "libresoc.v:14630.3-14642.6" + wire $0\LOGICAL_dec31_sgn[0:0] + attribute \src "libresoc.v:13988.7-13988.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:14695.3-14707.6" + wire width 3 $1\LOGICAL_dec31_cr_in[2:0] + attribute \src "libresoc.v:14708.3-14720.6" + wire width 3 $1\LOGICAL_dec31_cr_out[2:0] + attribute \src "libresoc.v:14565.3-14577.6" + wire width 2 $1\LOGICAL_dec31_cry_in[1:0] + attribute \src "libresoc.v:14604.3-14616.6" + wire $1\LOGICAL_dec31_cry_out[0:0] + attribute \src "libresoc.v:14643.3-14655.6" + wire width 12 $1\LOGICAL_dec31_function_unit[11:0] + attribute \src "libresoc.v:14669.3-14681.6" + wire width 3 $1\LOGICAL_dec31_in1_sel[2:0] + attribute \src "libresoc.v:14682.3-14694.6" + wire width 4 $1\LOGICAL_dec31_in2_sel[3:0] + attribute \src "libresoc.v:14656.3-14668.6" + wire width 7 $1\LOGICAL_dec31_internal_op[6:0] + attribute \src "libresoc.v:14578.3-14590.6" + wire $1\LOGICAL_dec31_inv_a[0:0] + attribute \src "libresoc.v:14591.3-14603.6" + wire $1\LOGICAL_dec31_inv_out[0:0] + attribute \src "libresoc.v:14617.3-14629.6" + wire $1\LOGICAL_dec31_is_32b[0:0] + attribute \src "libresoc.v:14539.3-14551.6" + wire width 4 $1\LOGICAL_dec31_ldst_len[3:0] + attribute \src "libresoc.v:14552.3-14564.6" + wire width 2 $1\LOGICAL_dec31_rc_sel[1:0] + attribute \src "libresoc.v:14630.3-14642.6" + wire $1\LOGICAL_dec31_sgn[0:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \LOGICAL_dec31_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 6 \LOGICAL_dec31_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 9 \LOGICAL_dec31_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 12 \LOGICAL_dec31_cry_out + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \LOGICAL_dec31_dec_sub26_opcode_in + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \LOGICAL_dec31_dec_sub28_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \LOGICAL_dec31_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 3 \LOGICAL_dec31_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 4 \LOGICAL_dec31_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \LOGICAL_dec31_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 10 \LOGICAL_dec31_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 11 \LOGICAL_dec31_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 13 \LOGICAL_dec31_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 7 \LOGICAL_dec31_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 8 \LOGICAL_dec31_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 14 \LOGICAL_dec31_sgn + attribute \src "libresoc.v:13988.7-13988.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:326" + wire width 5 \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 15 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 10 \opcode_switch + attribute \module_not_derived 1 + attribute \src "libresoc.v:14505.27-14521.4" + cell \LOGICAL_dec31_dec_sub26 \LOGICAL_dec31_dec_sub26 + connect \LOGICAL_dec31_dec_sub26_cr_in \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cr_in + connect \LOGICAL_dec31_dec_sub26_cr_out \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cr_out + connect \LOGICAL_dec31_dec_sub26_cry_in \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cry_in + connect \LOGICAL_dec31_dec_sub26_cry_out \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cry_out + connect \LOGICAL_dec31_dec_sub26_function_unit \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_function_unit + connect \LOGICAL_dec31_dec_sub26_in1_sel \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_in1_sel + connect \LOGICAL_dec31_dec_sub26_in2_sel \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_in2_sel + connect \LOGICAL_dec31_dec_sub26_internal_op \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_internal_op + connect \LOGICAL_dec31_dec_sub26_inv_a \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_inv_a + connect \LOGICAL_dec31_dec_sub26_inv_out \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_inv_out + connect \LOGICAL_dec31_dec_sub26_is_32b \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_is_32b + connect \LOGICAL_dec31_dec_sub26_ldst_len \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_ldst_len + connect \LOGICAL_dec31_dec_sub26_rc_sel \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_rc_sel + connect \LOGICAL_dec31_dec_sub26_sgn \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_sgn + connect \opcode_in \LOGICAL_dec31_dec_sub26_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:14522.27-14538.4" + cell \LOGICAL_dec31_dec_sub28 \LOGICAL_dec31_dec_sub28 + connect \LOGICAL_dec31_dec_sub28_cr_in \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cr_in + connect \LOGICAL_dec31_dec_sub28_cr_out \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cr_out + connect \LOGICAL_dec31_dec_sub28_cry_in \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cry_in + connect \LOGICAL_dec31_dec_sub28_cry_out \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cry_out + connect \LOGICAL_dec31_dec_sub28_function_unit \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_function_unit + connect \LOGICAL_dec31_dec_sub28_in1_sel \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_in1_sel + connect \LOGICAL_dec31_dec_sub28_in2_sel \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_in2_sel + connect \LOGICAL_dec31_dec_sub28_internal_op \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_internal_op + connect \LOGICAL_dec31_dec_sub28_inv_a \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_inv_a + connect \LOGICAL_dec31_dec_sub28_inv_out \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_inv_out + connect \LOGICAL_dec31_dec_sub28_is_32b \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_is_32b + connect \LOGICAL_dec31_dec_sub28_ldst_len \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_ldst_len + connect \LOGICAL_dec31_dec_sub28_rc_sel \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_rc_sel + connect \LOGICAL_dec31_dec_sub28_sgn \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_sgn + connect \opcode_in \LOGICAL_dec31_dec_sub28_opcode_in + end + attribute \src "libresoc.v:13988.7-13988.20" + process $proc$libresoc.v:13988$308 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:14539.3-14551.6" + process $proc$libresoc.v:14539$294 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_ldst_len[3:0] $1\LOGICAL_dec31_ldst_len[3:0] + attribute \src "libresoc.v:14540.5-14540.29" + switch \initial + attribute \src "libresoc.v:14540.9-14540.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LOGICAL_dec31_ldst_len[3:0] \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\LOGICAL_dec31_ldst_len[3:0] \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_ldst_len + case + assign $1\LOGICAL_dec31_ldst_len[3:0] 4'0000 + end + sync always + update \LOGICAL_dec31_ldst_len $0\LOGICAL_dec31_ldst_len[3:0] + end + attribute \src "libresoc.v:14552.3-14564.6" + process $proc$libresoc.v:14552$295 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_rc_sel[1:0] $1\LOGICAL_dec31_rc_sel[1:0] + attribute \src "libresoc.v:14553.5-14553.29" + switch \initial + attribute \src "libresoc.v:14553.9-14553.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LOGICAL_dec31_rc_sel[1:0] \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\LOGICAL_dec31_rc_sel[1:0] \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_rc_sel + case + assign $1\LOGICAL_dec31_rc_sel[1:0] 2'00 + end + sync always + update \LOGICAL_dec31_rc_sel $0\LOGICAL_dec31_rc_sel[1:0] + end + attribute \src "libresoc.v:14565.3-14577.6" + process $proc$libresoc.v:14565$296 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_cry_in[1:0] $1\LOGICAL_dec31_cry_in[1:0] + attribute \src "libresoc.v:14566.5-14566.29" + switch \initial + attribute \src "libresoc.v:14566.9-14566.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LOGICAL_dec31_cry_in[1:0] \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\LOGICAL_dec31_cry_in[1:0] \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cry_in + case + assign $1\LOGICAL_dec31_cry_in[1:0] 2'00 + end + sync always + update \LOGICAL_dec31_cry_in $0\LOGICAL_dec31_cry_in[1:0] + end + attribute \src "libresoc.v:14578.3-14590.6" + process $proc$libresoc.v:14578$297 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_inv_a[0:0] $1\LOGICAL_dec31_inv_a[0:0] + attribute \src "libresoc.v:14579.5-14579.29" + switch \initial + attribute \src "libresoc.v:14579.9-14579.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LOGICAL_dec31_inv_a[0:0] \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\LOGICAL_dec31_inv_a[0:0] \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_inv_a + case + assign $1\LOGICAL_dec31_inv_a[0:0] 1'0 + end + sync always + update \LOGICAL_dec31_inv_a $0\LOGICAL_dec31_inv_a[0:0] + end + attribute \src "libresoc.v:14591.3-14603.6" + process $proc$libresoc.v:14591$298 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_inv_out[0:0] $1\LOGICAL_dec31_inv_out[0:0] + attribute \src "libresoc.v:14592.5-14592.29" + switch \initial + attribute \src "libresoc.v:14592.9-14592.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LOGICAL_dec31_inv_out[0:0] \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\LOGICAL_dec31_inv_out[0:0] \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_inv_out + case + assign $1\LOGICAL_dec31_inv_out[0:0] 1'0 + end + sync always + update \LOGICAL_dec31_inv_out $0\LOGICAL_dec31_inv_out[0:0] + end + attribute \src "libresoc.v:14604.3-14616.6" + process $proc$libresoc.v:14604$299 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_cry_out[0:0] $1\LOGICAL_dec31_cry_out[0:0] + attribute \src "libresoc.v:14605.5-14605.29" + switch \initial + attribute \src "libresoc.v:14605.9-14605.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LOGICAL_dec31_cry_out[0:0] \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\LOGICAL_dec31_cry_out[0:0] \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cry_out + case + assign $1\LOGICAL_dec31_cry_out[0:0] 1'0 + end + sync always + update \LOGICAL_dec31_cry_out $0\LOGICAL_dec31_cry_out[0:0] + end + attribute \src "libresoc.v:14617.3-14629.6" + process $proc$libresoc.v:14617$300 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_is_32b[0:0] $1\LOGICAL_dec31_is_32b[0:0] + attribute \src "libresoc.v:14618.5-14618.29" + switch \initial + attribute \src "libresoc.v:14618.9-14618.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LOGICAL_dec31_is_32b[0:0] \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\LOGICAL_dec31_is_32b[0:0] \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_is_32b + case + assign $1\LOGICAL_dec31_is_32b[0:0] 1'0 + end + sync always + update \LOGICAL_dec31_is_32b $0\LOGICAL_dec31_is_32b[0:0] + end + attribute \src "libresoc.v:14630.3-14642.6" + process $proc$libresoc.v:14630$301 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_sgn[0:0] $1\LOGICAL_dec31_sgn[0:0] + attribute \src "libresoc.v:14631.5-14631.29" + switch \initial + attribute \src "libresoc.v:14631.9-14631.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LOGICAL_dec31_sgn[0:0] \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\LOGICAL_dec31_sgn[0:0] \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_sgn + case + assign $1\LOGICAL_dec31_sgn[0:0] 1'0 + end + sync always + update \LOGICAL_dec31_sgn $0\LOGICAL_dec31_sgn[0:0] + end + attribute \src "libresoc.v:14643.3-14655.6" + process $proc$libresoc.v:14643$302 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_function_unit[11:0] $1\LOGICAL_dec31_function_unit[11:0] + attribute \src "libresoc.v:14644.5-14644.29" + switch \initial + attribute \src "libresoc.v:14644.9-14644.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LOGICAL_dec31_function_unit[11:0] \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\LOGICAL_dec31_function_unit[11:0] \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_function_unit + case + assign $1\LOGICAL_dec31_function_unit[11:0] 12'000000000000 + end + sync always + update \LOGICAL_dec31_function_unit $0\LOGICAL_dec31_function_unit[11:0] + end + attribute \src "libresoc.v:14656.3-14668.6" + process $proc$libresoc.v:14656$303 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_internal_op[6:0] $1\LOGICAL_dec31_internal_op[6:0] + attribute \src "libresoc.v:14657.5-14657.29" + switch \initial + attribute \src "libresoc.v:14657.9-14657.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LOGICAL_dec31_internal_op[6:0] \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\LOGICAL_dec31_internal_op[6:0] \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_internal_op + case + assign $1\LOGICAL_dec31_internal_op[6:0] 7'0000000 + end + sync always + update \LOGICAL_dec31_internal_op $0\LOGICAL_dec31_internal_op[6:0] + end + attribute \src "libresoc.v:14669.3-14681.6" + process $proc$libresoc.v:14669$304 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_in1_sel[2:0] $1\LOGICAL_dec31_in1_sel[2:0] + attribute \src "libresoc.v:14670.5-14670.29" + switch \initial + attribute \src "libresoc.v:14670.9-14670.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LOGICAL_dec31_in1_sel[2:0] \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\LOGICAL_dec31_in1_sel[2:0] \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_in1_sel + case + assign $1\LOGICAL_dec31_in1_sel[2:0] 3'000 + end + sync always + update \LOGICAL_dec31_in1_sel $0\LOGICAL_dec31_in1_sel[2:0] + end + attribute \src "libresoc.v:14682.3-14694.6" + process $proc$libresoc.v:14682$305 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_in2_sel[3:0] $1\LOGICAL_dec31_in2_sel[3:0] + attribute \src "libresoc.v:14683.5-14683.29" + switch \initial + attribute \src "libresoc.v:14683.9-14683.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LOGICAL_dec31_in2_sel[3:0] \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\LOGICAL_dec31_in2_sel[3:0] \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_in2_sel + case + assign $1\LOGICAL_dec31_in2_sel[3:0] 4'0000 + end + sync always + update \LOGICAL_dec31_in2_sel $0\LOGICAL_dec31_in2_sel[3:0] + end + attribute \src "libresoc.v:14695.3-14707.6" + process $proc$libresoc.v:14695$306 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_cr_in[2:0] $1\LOGICAL_dec31_cr_in[2:0] + attribute \src "libresoc.v:14696.5-14696.29" + switch \initial + attribute \src "libresoc.v:14696.9-14696.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LOGICAL_dec31_cr_in[2:0] \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\LOGICAL_dec31_cr_in[2:0] \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cr_in + case + assign $1\LOGICAL_dec31_cr_in[2:0] 3'000 + end + sync always + update \LOGICAL_dec31_cr_in $0\LOGICAL_dec31_cr_in[2:0] + end + attribute \src "libresoc.v:14708.3-14720.6" + process $proc$libresoc.v:14708$307 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_cr_out[2:0] $1\LOGICAL_dec31_cr_out[2:0] + attribute \src "libresoc.v:14709.5-14709.29" + switch \initial + attribute \src "libresoc.v:14709.9-14709.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LOGICAL_dec31_cr_out[2:0] \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\LOGICAL_dec31_cr_out[2:0] \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cr_out + case + assign $1\LOGICAL_dec31_cr_out[2:0] 3'000 + end + sync always + update \LOGICAL_dec31_cr_out $0\LOGICAL_dec31_cr_out[2:0] + end + connect \LOGICAL_dec31_dec_sub26_opcode_in \opcode_in + connect \LOGICAL_dec31_dec_sub28_opcode_in \opcode_in + connect \opc_in \opcode_switch [4:0] + connect \opcode_switch \opcode_in [10:1] +end +attribute \src "libresoc.v:14729.1-15390.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_LOGICAL.dec.LOGICAL_dec31.LOGICAL_dec31_dec_sub26" +attribute \generator "nMigen" +module \LOGICAL_dec31_dec_sub26 + attribute \src "libresoc.v:15219.3-15252.6" + wire width 3 $0\LOGICAL_dec31_dec_sub26_cr_in[2:0] + attribute \src "libresoc.v:15253.3-15286.6" + wire width 3 $0\LOGICAL_dec31_dec_sub26_cr_out[2:0] + attribute \src "libresoc.v:15355.3-15388.6" + wire width 2 $0\LOGICAL_dec31_dec_sub26_cry_in[1:0] + attribute \src "libresoc.v:15015.3-15048.6" + wire $0\LOGICAL_dec31_dec_sub26_cry_out[0:0] + attribute \src "libresoc.v:14913.3-14946.6" + wire width 12 $0\LOGICAL_dec31_dec_sub26_function_unit[11:0] + attribute \src "libresoc.v:15151.3-15184.6" + wire width 3 $0\LOGICAL_dec31_dec_sub26_in1_sel[2:0] + attribute \src "libresoc.v:15185.3-15218.6" + wire width 4 $0\LOGICAL_dec31_dec_sub26_in2_sel[3:0] + attribute \src "libresoc.v:15117.3-15150.6" + wire width 7 $0\LOGICAL_dec31_dec_sub26_internal_op[6:0] + attribute \src "libresoc.v:14947.3-14980.6" + wire $0\LOGICAL_dec31_dec_sub26_inv_a[0:0] + attribute \src "libresoc.v:14981.3-15014.6" + wire $0\LOGICAL_dec31_dec_sub26_inv_out[0:0] + attribute \src "libresoc.v:15049.3-15082.6" + wire $0\LOGICAL_dec31_dec_sub26_is_32b[0:0] + attribute \src "libresoc.v:15287.3-15320.6" + wire width 4 $0\LOGICAL_dec31_dec_sub26_ldst_len[3:0] + attribute \src "libresoc.v:15321.3-15354.6" + wire width 2 $0\LOGICAL_dec31_dec_sub26_rc_sel[1:0] + attribute \src "libresoc.v:15083.3-15116.6" + wire $0\LOGICAL_dec31_dec_sub26_sgn[0:0] + attribute \src "libresoc.v:14730.7-14730.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:15219.3-15252.6" + wire width 3 $1\LOGICAL_dec31_dec_sub26_cr_in[2:0] + attribute \src "libresoc.v:15253.3-15286.6" + wire width 3 $1\LOGICAL_dec31_dec_sub26_cr_out[2:0] + attribute \src "libresoc.v:15355.3-15388.6" + wire width 2 $1\LOGICAL_dec31_dec_sub26_cry_in[1:0] + attribute \src "libresoc.v:15015.3-15048.6" + wire $1\LOGICAL_dec31_dec_sub26_cry_out[0:0] + attribute \src "libresoc.v:14913.3-14946.6" + wire width 12 $1\LOGICAL_dec31_dec_sub26_function_unit[11:0] + attribute \src "libresoc.v:15151.3-15184.6" + wire width 3 $1\LOGICAL_dec31_dec_sub26_in1_sel[2:0] + attribute \src "libresoc.v:15185.3-15218.6" + wire width 4 $1\LOGICAL_dec31_dec_sub26_in2_sel[3:0] + attribute \src "libresoc.v:15117.3-15150.6" + wire width 7 $1\LOGICAL_dec31_dec_sub26_internal_op[6:0] + attribute \src "libresoc.v:14947.3-14980.6" + wire $1\LOGICAL_dec31_dec_sub26_inv_a[0:0] + attribute \src "libresoc.v:14981.3-15014.6" + wire $1\LOGICAL_dec31_dec_sub26_inv_out[0:0] + attribute \src "libresoc.v:15049.3-15082.6" + wire $1\LOGICAL_dec31_dec_sub26_is_32b[0:0] + attribute \src "libresoc.v:15287.3-15320.6" + wire width 4 $1\LOGICAL_dec31_dec_sub26_ldst_len[3:0] + attribute \src "libresoc.v:15321.3-15354.6" + wire width 2 $1\LOGICAL_dec31_dec_sub26_rc_sel[1:0] + attribute \src "libresoc.v:15083.3-15116.6" + wire $1\LOGICAL_dec31_dec_sub26_sgn[0:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \LOGICAL_dec31_dec_sub26_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 6 \LOGICAL_dec31_dec_sub26_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 9 \LOGICAL_dec31_dec_sub26_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 12 \LOGICAL_dec31_dec_sub26_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \LOGICAL_dec31_dec_sub26_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 3 \LOGICAL_dec31_dec_sub26_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 4 \LOGICAL_dec31_dec_sub26_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \LOGICAL_dec31_dec_sub26_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 10 \LOGICAL_dec31_dec_sub26_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 11 \LOGICAL_dec31_dec_sub26_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 13 \LOGICAL_dec31_dec_sub26_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 7 \LOGICAL_dec31_dec_sub26_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 8 \LOGICAL_dec31_dec_sub26_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 14 \LOGICAL_dec31_dec_sub26_sgn + attribute \src "libresoc.v:14730.7-14730.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 15 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 5 \opcode_switch + attribute \src "libresoc.v:14730.7-14730.20" + process $proc$libresoc.v:14730$323 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:14913.3-14946.6" + process $proc$libresoc.v:14913$309 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub26_function_unit[11:0] $1\LOGICAL_dec31_dec_sub26_function_unit[11:0] + attribute \src "libresoc.v:14914.5-14914.29" + switch \initial + attribute \src "libresoc.v:14914.9-14914.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_function_unit[11:0] 12'000000010000 + case + assign $1\LOGICAL_dec31_dec_sub26_function_unit[11:0] 12'000000000000 + end + sync always + update \LOGICAL_dec31_dec_sub26_function_unit $0\LOGICAL_dec31_dec_sub26_function_unit[11:0] + end + attribute \src "libresoc.v:14947.3-14980.6" + process $proc$libresoc.v:14947$310 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub26_inv_a[0:0] $1\LOGICAL_dec31_dec_sub26_inv_a[0:0] + attribute \src "libresoc.v:14948.5-14948.29" + switch \initial + attribute \src "libresoc.v:14948.9-14948.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_inv_a[0:0] 1'0 + case + assign $1\LOGICAL_dec31_dec_sub26_inv_a[0:0] 1'0 + end + sync always + update \LOGICAL_dec31_dec_sub26_inv_a $0\LOGICAL_dec31_dec_sub26_inv_a[0:0] + end + attribute \src "libresoc.v:14981.3-15014.6" + process $proc$libresoc.v:14981$311 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub26_inv_out[0:0] $1\LOGICAL_dec31_dec_sub26_inv_out[0:0] + attribute \src "libresoc.v:14982.5-14982.29" + switch \initial + attribute \src "libresoc.v:14982.9-14982.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_inv_out[0:0] 1'0 + case + assign $1\LOGICAL_dec31_dec_sub26_inv_out[0:0] 1'0 + end + sync always + update \LOGICAL_dec31_dec_sub26_inv_out $0\LOGICAL_dec31_dec_sub26_inv_out[0:0] + end + attribute \src "libresoc.v:15015.3-15048.6" + process $proc$libresoc.v:15015$312 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub26_cry_out[0:0] $1\LOGICAL_dec31_dec_sub26_cry_out[0:0] + attribute \src "libresoc.v:15016.5-15016.29" + switch \initial + attribute \src "libresoc.v:15016.9-15016.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cry_out[0:0] 1'0 + case + assign $1\LOGICAL_dec31_dec_sub26_cry_out[0:0] 1'0 + end + sync always + update \LOGICAL_dec31_dec_sub26_cry_out $0\LOGICAL_dec31_dec_sub26_cry_out[0:0] + end + attribute \src "libresoc.v:15049.3-15082.6" + process $proc$libresoc.v:15049$313 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub26_is_32b[0:0] $1\LOGICAL_dec31_dec_sub26_is_32b[0:0] + attribute \src "libresoc.v:15050.5-15050.29" + switch \initial + attribute \src "libresoc.v:15050.9-15050.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_is_32b[0:0] 1'0 + case + assign $1\LOGICAL_dec31_dec_sub26_is_32b[0:0] 1'0 + end + sync always + update \LOGICAL_dec31_dec_sub26_is_32b $0\LOGICAL_dec31_dec_sub26_is_32b[0:0] + end + attribute \src "libresoc.v:15083.3-15116.6" + process $proc$libresoc.v:15083$314 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub26_sgn[0:0] $1\LOGICAL_dec31_dec_sub26_sgn[0:0] + attribute \src "libresoc.v:15084.5-15084.29" + switch \initial + attribute \src "libresoc.v:15084.9-15084.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_sgn[0:0] 1'0 + case + assign $1\LOGICAL_dec31_dec_sub26_sgn[0:0] 1'0 + end + sync always + update \LOGICAL_dec31_dec_sub26_sgn $0\LOGICAL_dec31_dec_sub26_sgn[0:0] + end + attribute \src "libresoc.v:15117.3-15150.6" + process $proc$libresoc.v:15117$315 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub26_internal_op[6:0] $1\LOGICAL_dec31_dec_sub26_internal_op[6:0] + attribute \src "libresoc.v:15118.5-15118.29" + switch \initial + attribute \src "libresoc.v:15118.9-15118.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_internal_op[6:0] 7'0001110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_internal_op[6:0] 7'0001110 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_internal_op[6:0] 7'0001110 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_internal_op[6:0] 7'0001110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_internal_op[6:0] 7'0110110 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_internal_op[6:0] 7'0110110 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_internal_op[6:0] 7'0110110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_internal_op[6:0] 7'0110111 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_internal_op[6:0] 7'0110111 + case + assign $1\LOGICAL_dec31_dec_sub26_internal_op[6:0] 7'0000000 + end + sync always + update \LOGICAL_dec31_dec_sub26_internal_op $0\LOGICAL_dec31_dec_sub26_internal_op[6:0] + end + attribute \src "libresoc.v:15151.3-15184.6" + process $proc$libresoc.v:15151$316 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub26_in1_sel[2:0] $1\LOGICAL_dec31_dec_sub26_in1_sel[2:0] + attribute \src "libresoc.v:15152.5-15152.29" + switch \initial + attribute \src "libresoc.v:15152.9-15152.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_in1_sel[2:0] 3'100 + case + assign $1\LOGICAL_dec31_dec_sub26_in1_sel[2:0] 3'000 + end + sync always + update \LOGICAL_dec31_dec_sub26_in1_sel $0\LOGICAL_dec31_dec_sub26_in1_sel[2:0] + end + attribute \src "libresoc.v:15185.3-15218.6" + process $proc$libresoc.v:15185$317 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub26_in2_sel[3:0] $1\LOGICAL_dec31_dec_sub26_in2_sel[3:0] + attribute \src "libresoc.v:15186.5-15186.29" + switch \initial + attribute \src "libresoc.v:15186.9-15186.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_in2_sel[3:0] 4'0000 + case + assign $1\LOGICAL_dec31_dec_sub26_in2_sel[3:0] 4'0000 + end + sync always + update \LOGICAL_dec31_dec_sub26_in2_sel $0\LOGICAL_dec31_dec_sub26_in2_sel[3:0] + end + attribute \src "libresoc.v:15219.3-15252.6" + process $proc$libresoc.v:15219$318 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub26_cr_in[2:0] $1\LOGICAL_dec31_dec_sub26_cr_in[2:0] + attribute \src "libresoc.v:15220.5-15220.29" + switch \initial + attribute \src "libresoc.v:15220.9-15220.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cr_in[2:0] 3'000 + case + assign $1\LOGICAL_dec31_dec_sub26_cr_in[2:0] 3'000 + end + sync always + update \LOGICAL_dec31_dec_sub26_cr_in $0\LOGICAL_dec31_dec_sub26_cr_in[2:0] + end + attribute \src "libresoc.v:15253.3-15286.6" + process $proc$libresoc.v:15253$319 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub26_cr_out[2:0] $1\LOGICAL_dec31_dec_sub26_cr_out[2:0] + attribute \src "libresoc.v:15254.5-15254.29" + switch \initial + attribute \src "libresoc.v:15254.9-15254.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cr_out[2:0] 3'000 + case + assign $1\LOGICAL_dec31_dec_sub26_cr_out[2:0] 3'000 + end + sync always + update \LOGICAL_dec31_dec_sub26_cr_out $0\LOGICAL_dec31_dec_sub26_cr_out[2:0] + end + attribute \src "libresoc.v:15287.3-15320.6" + process $proc$libresoc.v:15287$320 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub26_ldst_len[3:0] $1\LOGICAL_dec31_dec_sub26_ldst_len[3:0] + attribute \src "libresoc.v:15288.5-15288.29" + switch \initial + attribute \src "libresoc.v:15288.9-15288.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_ldst_len[3:0] 4'0100 + case + assign $1\LOGICAL_dec31_dec_sub26_ldst_len[3:0] 4'0000 + end + sync always + update \LOGICAL_dec31_dec_sub26_ldst_len $0\LOGICAL_dec31_dec_sub26_ldst_len[3:0] + end + attribute \src "libresoc.v:15321.3-15354.6" + process $proc$libresoc.v:15321$321 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub26_rc_sel[1:0] $1\LOGICAL_dec31_dec_sub26_rc_sel[1:0] + attribute \src "libresoc.v:15322.5-15322.29" + switch \initial + attribute \src "libresoc.v:15322.9-15322.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_rc_sel[1:0] 2'00 + case + assign $1\LOGICAL_dec31_dec_sub26_rc_sel[1:0] 2'00 + end + sync always + update \LOGICAL_dec31_dec_sub26_rc_sel $0\LOGICAL_dec31_dec_sub26_rc_sel[1:0] + end + attribute \src "libresoc.v:15355.3-15388.6" + process $proc$libresoc.v:15355$322 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub26_cry_in[1:0] $1\LOGICAL_dec31_dec_sub26_cry_in[1:0] + attribute \src "libresoc.v:15356.5-15356.29" + switch \initial + attribute \src "libresoc.v:15356.9-15356.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cry_in[1:0] 2'00 + case + assign $1\LOGICAL_dec31_dec_sub26_cry_in[1:0] 2'00 + end + sync always + update \LOGICAL_dec31_dec_sub26_cry_in $0\LOGICAL_dec31_dec_sub26_cry_in[1:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:15394.1-16097.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_LOGICAL.dec.LOGICAL_dec31.LOGICAL_dec31_dec_sub28" +attribute \generator "nMigen" +module \LOGICAL_dec31_dec_sub28 + attribute \src "libresoc.v:15911.3-15947.6" + wire width 3 $0\LOGICAL_dec31_dec_sub28_cr_in[2:0] + attribute \src "libresoc.v:15948.3-15984.6" + wire width 3 $0\LOGICAL_dec31_dec_sub28_cr_out[2:0] + attribute \src "libresoc.v:16059.3-16095.6" + wire width 2 $0\LOGICAL_dec31_dec_sub28_cry_in[1:0] + attribute \src "libresoc.v:15689.3-15725.6" + wire $0\LOGICAL_dec31_dec_sub28_cry_out[0:0] + attribute \src "libresoc.v:15578.3-15614.6" + wire width 12 $0\LOGICAL_dec31_dec_sub28_function_unit[11:0] + attribute \src "libresoc.v:15837.3-15873.6" + wire width 3 $0\LOGICAL_dec31_dec_sub28_in1_sel[2:0] + attribute \src "libresoc.v:15874.3-15910.6" + wire width 4 $0\LOGICAL_dec31_dec_sub28_in2_sel[3:0] + attribute \src "libresoc.v:15800.3-15836.6" + wire width 7 $0\LOGICAL_dec31_dec_sub28_internal_op[6:0] + attribute \src "libresoc.v:15615.3-15651.6" + wire $0\LOGICAL_dec31_dec_sub28_inv_a[0:0] + attribute \src "libresoc.v:15652.3-15688.6" + wire $0\LOGICAL_dec31_dec_sub28_inv_out[0:0] + attribute \src "libresoc.v:15726.3-15762.6" + wire $0\LOGICAL_dec31_dec_sub28_is_32b[0:0] + attribute \src "libresoc.v:15985.3-16021.6" + wire width 4 $0\LOGICAL_dec31_dec_sub28_ldst_len[3:0] + attribute \src "libresoc.v:16022.3-16058.6" + wire width 2 $0\LOGICAL_dec31_dec_sub28_rc_sel[1:0] + attribute \src "libresoc.v:15763.3-15799.6" + wire $0\LOGICAL_dec31_dec_sub28_sgn[0:0] + attribute \src "libresoc.v:15395.7-15395.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:15911.3-15947.6" + wire width 3 $1\LOGICAL_dec31_dec_sub28_cr_in[2:0] + attribute \src "libresoc.v:15948.3-15984.6" + wire width 3 $1\LOGICAL_dec31_dec_sub28_cr_out[2:0] + attribute \src "libresoc.v:16059.3-16095.6" + wire width 2 $1\LOGICAL_dec31_dec_sub28_cry_in[1:0] + attribute \src "libresoc.v:15689.3-15725.6" + wire $1\LOGICAL_dec31_dec_sub28_cry_out[0:0] + attribute \src "libresoc.v:15578.3-15614.6" + wire width 12 $1\LOGICAL_dec31_dec_sub28_function_unit[11:0] + attribute \src "libresoc.v:15837.3-15873.6" + wire width 3 $1\LOGICAL_dec31_dec_sub28_in1_sel[2:0] + attribute \src "libresoc.v:15874.3-15910.6" + wire width 4 $1\LOGICAL_dec31_dec_sub28_in2_sel[3:0] + attribute \src "libresoc.v:15800.3-15836.6" + wire width 7 $1\LOGICAL_dec31_dec_sub28_internal_op[6:0] + attribute \src "libresoc.v:15615.3-15651.6" + wire $1\LOGICAL_dec31_dec_sub28_inv_a[0:0] + attribute \src "libresoc.v:15652.3-15688.6" + wire $1\LOGICAL_dec31_dec_sub28_inv_out[0:0] + attribute \src "libresoc.v:15726.3-15762.6" + wire $1\LOGICAL_dec31_dec_sub28_is_32b[0:0] + attribute \src "libresoc.v:15985.3-16021.6" + wire width 4 $1\LOGICAL_dec31_dec_sub28_ldst_len[3:0] + attribute \src "libresoc.v:16022.3-16058.6" + wire width 2 $1\LOGICAL_dec31_dec_sub28_rc_sel[1:0] + attribute \src "libresoc.v:15763.3-15799.6" + wire $1\LOGICAL_dec31_dec_sub28_sgn[0:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \LOGICAL_dec31_dec_sub28_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 6 \LOGICAL_dec31_dec_sub28_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 9 \LOGICAL_dec31_dec_sub28_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 12 \LOGICAL_dec31_dec_sub28_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \LOGICAL_dec31_dec_sub28_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 3 \LOGICAL_dec31_dec_sub28_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 4 \LOGICAL_dec31_dec_sub28_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \LOGICAL_dec31_dec_sub28_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 10 \LOGICAL_dec31_dec_sub28_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 11 \LOGICAL_dec31_dec_sub28_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 13 \LOGICAL_dec31_dec_sub28_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 7 \LOGICAL_dec31_dec_sub28_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 8 \LOGICAL_dec31_dec_sub28_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 14 \LOGICAL_dec31_dec_sub28_sgn + attribute \src "libresoc.v:15395.7-15395.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 15 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 5 \opcode_switch + attribute \src "libresoc.v:15395.7-15395.20" + process $proc$libresoc.v:15395$338 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:15578.3-15614.6" + process $proc$libresoc.v:15578$324 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub28_function_unit[11:0] $1\LOGICAL_dec31_dec_sub28_function_unit[11:0] + attribute \src "libresoc.v:15579.5-15579.29" + switch \initial + attribute \src "libresoc.v:15579.9-15579.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_function_unit[11:0] 12'000000010000 + case + assign $1\LOGICAL_dec31_dec_sub28_function_unit[11:0] 12'000000000000 + end + sync always + update \LOGICAL_dec31_dec_sub28_function_unit $0\LOGICAL_dec31_dec_sub28_function_unit[11:0] + end + attribute \src "libresoc.v:15615.3-15651.6" + process $proc$libresoc.v:15615$325 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub28_inv_a[0:0] $1\LOGICAL_dec31_dec_sub28_inv_a[0:0] + attribute \src "libresoc.v:15616.5-15616.29" + switch \initial + attribute \src "libresoc.v:15616.9-15616.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_inv_a[0:0] 1'0 + case + assign $1\LOGICAL_dec31_dec_sub28_inv_a[0:0] 1'0 + end + sync always + update \LOGICAL_dec31_dec_sub28_inv_a $0\LOGICAL_dec31_dec_sub28_inv_a[0:0] + end + attribute \src "libresoc.v:15652.3-15688.6" + process $proc$libresoc.v:15652$326 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub28_inv_out[0:0] $1\LOGICAL_dec31_dec_sub28_inv_out[0:0] + attribute \src "libresoc.v:15653.5-15653.29" + switch \initial + attribute \src "libresoc.v:15653.9-15653.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_inv_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_inv_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_inv_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_inv_out[0:0] 1'0 + case + assign $1\LOGICAL_dec31_dec_sub28_inv_out[0:0] 1'0 + end + sync always + update \LOGICAL_dec31_dec_sub28_inv_out $0\LOGICAL_dec31_dec_sub28_inv_out[0:0] + end + attribute \src "libresoc.v:15689.3-15725.6" + process $proc$libresoc.v:15689$327 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub28_cry_out[0:0] $1\LOGICAL_dec31_dec_sub28_cry_out[0:0] + attribute \src "libresoc.v:15690.5-15690.29" + switch \initial + attribute \src "libresoc.v:15690.9-15690.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cry_out[0:0] 1'0 + case + assign $1\LOGICAL_dec31_dec_sub28_cry_out[0:0] 1'0 + end + sync always + update \LOGICAL_dec31_dec_sub28_cry_out $0\LOGICAL_dec31_dec_sub28_cry_out[0:0] + end + attribute \src "libresoc.v:15726.3-15762.6" + process $proc$libresoc.v:15726$328 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub28_is_32b[0:0] $1\LOGICAL_dec31_dec_sub28_is_32b[0:0] + attribute \src "libresoc.v:15727.5-15727.29" + switch \initial + attribute \src "libresoc.v:15727.9-15727.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_is_32b[0:0] 1'0 + case + assign $1\LOGICAL_dec31_dec_sub28_is_32b[0:0] 1'0 + end + sync always + update \LOGICAL_dec31_dec_sub28_is_32b $0\LOGICAL_dec31_dec_sub28_is_32b[0:0] + end + attribute \src "libresoc.v:15763.3-15799.6" + process $proc$libresoc.v:15763$329 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub28_sgn[0:0] $1\LOGICAL_dec31_dec_sub28_sgn[0:0] + attribute \src "libresoc.v:15764.5-15764.29" + switch \initial + attribute \src "libresoc.v:15764.9-15764.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_sgn[0:0] 1'0 + case + assign $1\LOGICAL_dec31_dec_sub28_sgn[0:0] 1'0 + end + sync always + update \LOGICAL_dec31_dec_sub28_sgn $0\LOGICAL_dec31_dec_sub28_sgn[0:0] + end + attribute \src "libresoc.v:15800.3-15836.6" + process $proc$libresoc.v:15800$330 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub28_internal_op[6:0] $1\LOGICAL_dec31_dec_sub28_internal_op[6:0] + attribute \src "libresoc.v:15801.5-15801.29" + switch \initial + attribute \src "libresoc.v:15801.9-15801.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_internal_op[6:0] 7'0000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_internal_op[6:0] 7'0000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_internal_op[6:0] 7'0001001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_internal_op[6:0] 7'0001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_internal_op[6:0] 7'1000011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_internal_op[6:0] 7'0000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_internal_op[6:0] 7'0110101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_internal_op[6:0] 7'0110101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_internal_op[6:0] 7'0110101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_internal_op[6:0] 7'1000011 + case + assign $1\LOGICAL_dec31_dec_sub28_internal_op[6:0] 7'0000000 + end + sync always + update \LOGICAL_dec31_dec_sub28_internal_op $0\LOGICAL_dec31_dec_sub28_internal_op[6:0] + end + attribute \src "libresoc.v:15837.3-15873.6" + process $proc$libresoc.v:15837$331 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub28_in1_sel[2:0] $1\LOGICAL_dec31_dec_sub28_in1_sel[2:0] + attribute \src "libresoc.v:15838.5-15838.29" + switch \initial + attribute \src "libresoc.v:15838.9-15838.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_in1_sel[2:0] 3'100 + case + assign $1\LOGICAL_dec31_dec_sub28_in1_sel[2:0] 3'000 + end + sync always + update \LOGICAL_dec31_dec_sub28_in1_sel $0\LOGICAL_dec31_dec_sub28_in1_sel[2:0] + end + attribute \src "libresoc.v:15874.3-15910.6" + process $proc$libresoc.v:15874$332 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub28_in2_sel[3:0] $1\LOGICAL_dec31_dec_sub28_in2_sel[3:0] + attribute \src "libresoc.v:15875.5-15875.29" + switch \initial + attribute \src "libresoc.v:15875.9-15875.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_in2_sel[3:0] 4'0001 + case + assign $1\LOGICAL_dec31_dec_sub28_in2_sel[3:0] 4'0000 + end + sync always + update \LOGICAL_dec31_dec_sub28_in2_sel $0\LOGICAL_dec31_dec_sub28_in2_sel[3:0] + end + attribute \src "libresoc.v:15911.3-15947.6" + process $proc$libresoc.v:15911$333 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub28_cr_in[2:0] $1\LOGICAL_dec31_dec_sub28_cr_in[2:0] + attribute \src "libresoc.v:15912.5-15912.29" + switch \initial + attribute \src "libresoc.v:15912.9-15912.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cr_in[2:0] 3'000 + case + assign $1\LOGICAL_dec31_dec_sub28_cr_in[2:0] 3'000 + end + sync always + update \LOGICAL_dec31_dec_sub28_cr_in $0\LOGICAL_dec31_dec_sub28_cr_in[2:0] + end + attribute \src "libresoc.v:15948.3-15984.6" + process $proc$libresoc.v:15948$334 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub28_cr_out[2:0] $1\LOGICAL_dec31_dec_sub28_cr_out[2:0] + attribute \src "libresoc.v:15949.5-15949.29" + switch \initial + attribute \src "libresoc.v:15949.9-15949.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cr_out[2:0] 3'001 + case + assign $1\LOGICAL_dec31_dec_sub28_cr_out[2:0] 3'000 + end + sync always + update \LOGICAL_dec31_dec_sub28_cr_out $0\LOGICAL_dec31_dec_sub28_cr_out[2:0] + end + attribute \src "libresoc.v:15985.3-16021.6" + process $proc$libresoc.v:15985$335 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub28_ldst_len[3:0] $1\LOGICAL_dec31_dec_sub28_ldst_len[3:0] + attribute \src "libresoc.v:15986.5-15986.29" + switch \initial + attribute \src "libresoc.v:15986.9-15986.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_ldst_len[3:0] 4'0000 + case + assign $1\LOGICAL_dec31_dec_sub28_ldst_len[3:0] 4'0000 + end + sync always + update \LOGICAL_dec31_dec_sub28_ldst_len $0\LOGICAL_dec31_dec_sub28_ldst_len[3:0] + end + attribute \src "libresoc.v:16022.3-16058.6" + process $proc$libresoc.v:16022$336 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub28_rc_sel[1:0] $1\LOGICAL_dec31_dec_sub28_rc_sel[1:0] + attribute \src "libresoc.v:16023.5-16023.29" + switch \initial + attribute \src "libresoc.v:16023.9-16023.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_rc_sel[1:0] 2'10 + case + assign $1\LOGICAL_dec31_dec_sub28_rc_sel[1:0] 2'00 + end + sync always + update \LOGICAL_dec31_dec_sub28_rc_sel $0\LOGICAL_dec31_dec_sub28_rc_sel[1:0] + end + attribute \src "libresoc.v:16059.3-16095.6" + process $proc$libresoc.v:16059$337 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub28_cry_in[1:0] $1\LOGICAL_dec31_dec_sub28_cry_in[1:0] + attribute \src "libresoc.v:16060.5-16060.29" + switch \initial + attribute \src "libresoc.v:16060.9-16060.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cry_in[1:0] 2'00 + case + assign $1\LOGICAL_dec31_dec_sub28_cry_in[1:0] 2'00 + end + sync always + update \LOGICAL_dec31_dec_sub28_cry_in $0\LOGICAL_dec31_dec_sub28_cry_in[1:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:16101.1-16659.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_MUL.dec.MUL_dec31" +attribute \generator "nMigen" +module \MUL_dec31 + attribute \src "libresoc.v:16616.3-16628.6" + wire width 3 $0\MUL_dec31_cr_in[2:0] + attribute \src "libresoc.v:16629.3-16641.6" + wire width 3 $0\MUL_dec31_cr_out[2:0] + attribute \src "libresoc.v:16577.3-16589.6" + wire width 12 $0\MUL_dec31_function_unit[11:0] + attribute \src "libresoc.v:16603.3-16615.6" + wire width 4 $0\MUL_dec31_in2_sel[3:0] + attribute \src "libresoc.v:16590.3-16602.6" + wire width 7 $0\MUL_dec31_internal_op[6:0] + attribute \src "libresoc.v:16551.3-16563.6" + wire $0\MUL_dec31_is_32b[0:0] + attribute \src "libresoc.v:16642.3-16654.6" + wire width 2 $0\MUL_dec31_rc_sel[1:0] + attribute \src "libresoc.v:16564.3-16576.6" + wire $0\MUL_dec31_sgn[0:0] + attribute \src "libresoc.v:16102.7-16102.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:16616.3-16628.6" + wire width 3 $1\MUL_dec31_cr_in[2:0] + attribute \src "libresoc.v:16629.3-16641.6" + wire width 3 $1\MUL_dec31_cr_out[2:0] + attribute \src "libresoc.v:16577.3-16589.6" + wire width 12 $1\MUL_dec31_function_unit[11:0] + attribute \src "libresoc.v:16603.3-16615.6" + wire width 4 $1\MUL_dec31_in2_sel[3:0] + attribute \src "libresoc.v:16590.3-16602.6" + wire width 7 $1\MUL_dec31_internal_op[6:0] + attribute \src "libresoc.v:16551.3-16563.6" + wire $1\MUL_dec31_is_32b[0:0] + attribute \src "libresoc.v:16642.3-16654.6" + wire width 2 $1\MUL_dec31_rc_sel[1:0] + attribute \src "libresoc.v:16564.3-16576.6" + wire $1\MUL_dec31_sgn[0:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 4 \MUL_dec31_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \MUL_dec31_cr_out + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_function_unit + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_is_32b + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \MUL_dec31_dec_sub11_opcode_in + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_function_unit + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_is_32b + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \MUL_dec31_dec_sub9_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \MUL_dec31_function_unit + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 3 \MUL_dec31_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \MUL_dec31_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 7 \MUL_dec31_is_32b + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 6 \MUL_dec31_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 8 \MUL_dec31_sgn + attribute \src "libresoc.v:16102.7-16102.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:326" + wire width 5 \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 9 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 10 \opcode_switch + attribute \module_not_derived 1 + attribute \src "libresoc.v:16529.23-16539.4" + cell \MUL_dec31_dec_sub11 \MUL_dec31_dec_sub11 + connect \MUL_dec31_dec_sub11_cr_in \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_cr_in + connect \MUL_dec31_dec_sub11_cr_out \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_cr_out + connect \MUL_dec31_dec_sub11_function_unit \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_function_unit + connect \MUL_dec31_dec_sub11_in2_sel \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_in2_sel + connect \MUL_dec31_dec_sub11_internal_op \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_internal_op + connect \MUL_dec31_dec_sub11_is_32b \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_is_32b + connect \MUL_dec31_dec_sub11_rc_sel \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_rc_sel + connect \MUL_dec31_dec_sub11_sgn \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_sgn + connect \opcode_in \MUL_dec31_dec_sub11_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:16540.22-16550.4" + cell \MUL_dec31_dec_sub9 \MUL_dec31_dec_sub9 + connect \MUL_dec31_dec_sub9_cr_in \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_cr_in + connect \MUL_dec31_dec_sub9_cr_out \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_cr_out + connect \MUL_dec31_dec_sub9_function_unit \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_function_unit + connect \MUL_dec31_dec_sub9_in2_sel \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_in2_sel + connect \MUL_dec31_dec_sub9_internal_op \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_internal_op + connect \MUL_dec31_dec_sub9_is_32b \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_is_32b + connect \MUL_dec31_dec_sub9_rc_sel \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_rc_sel + connect \MUL_dec31_dec_sub9_sgn \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_sgn + connect \opcode_in \MUL_dec31_dec_sub9_opcode_in + end + attribute \src "libresoc.v:16102.7-16102.20" + process $proc$libresoc.v:16102$347 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:16551.3-16563.6" + process $proc$libresoc.v:16551$339 + assign { } { } + assign { } { } + assign $0\MUL_dec31_is_32b[0:0] $1\MUL_dec31_is_32b[0:0] + attribute \src "libresoc.v:16552.5-16552.29" + switch \initial + attribute \src "libresoc.v:16552.9-16552.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\MUL_dec31_is_32b[0:0] \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\MUL_dec31_is_32b[0:0] \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_is_32b + case + assign $1\MUL_dec31_is_32b[0:0] 1'0 + end + sync always + update \MUL_dec31_is_32b $0\MUL_dec31_is_32b[0:0] + end + attribute \src "libresoc.v:16564.3-16576.6" + process $proc$libresoc.v:16564$340 + assign { } { } + assign { } { } + assign $0\MUL_dec31_sgn[0:0] $1\MUL_dec31_sgn[0:0] + attribute \src "libresoc.v:16565.5-16565.29" + switch \initial + attribute \src "libresoc.v:16565.9-16565.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\MUL_dec31_sgn[0:0] \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\MUL_dec31_sgn[0:0] \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_sgn + case + assign $1\MUL_dec31_sgn[0:0] 1'0 + end + sync always + update \MUL_dec31_sgn $0\MUL_dec31_sgn[0:0] + end + attribute \src "libresoc.v:16577.3-16589.6" + process $proc$libresoc.v:16577$341 + assign { } { } + assign { } { } + assign $0\MUL_dec31_function_unit[11:0] $1\MUL_dec31_function_unit[11:0] + attribute \src "libresoc.v:16578.5-16578.29" + switch \initial + attribute \src "libresoc.v:16578.9-16578.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\MUL_dec31_function_unit[11:0] \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\MUL_dec31_function_unit[11:0] \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_function_unit + case + assign $1\MUL_dec31_function_unit[11:0] 12'000000000000 + end + sync always + update \MUL_dec31_function_unit $0\MUL_dec31_function_unit[11:0] + end + attribute \src "libresoc.v:16590.3-16602.6" + process $proc$libresoc.v:16590$342 + assign { } { } + assign { } { } + assign $0\MUL_dec31_internal_op[6:0] $1\MUL_dec31_internal_op[6:0] + attribute \src "libresoc.v:16591.5-16591.29" + switch \initial + attribute \src "libresoc.v:16591.9-16591.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\MUL_dec31_internal_op[6:0] \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\MUL_dec31_internal_op[6:0] \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_internal_op + case + assign $1\MUL_dec31_internal_op[6:0] 7'0000000 + end + sync always + update \MUL_dec31_internal_op $0\MUL_dec31_internal_op[6:0] + end + attribute \src "libresoc.v:16603.3-16615.6" + process $proc$libresoc.v:16603$343 + assign { } { } + assign { } { } + assign $0\MUL_dec31_in2_sel[3:0] $1\MUL_dec31_in2_sel[3:0] + attribute \src "libresoc.v:16604.5-16604.29" + switch \initial + attribute \src "libresoc.v:16604.9-16604.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\MUL_dec31_in2_sel[3:0] \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\MUL_dec31_in2_sel[3:0] \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_in2_sel + case + assign $1\MUL_dec31_in2_sel[3:0] 4'0000 + end + sync always + update \MUL_dec31_in2_sel $0\MUL_dec31_in2_sel[3:0] + end + attribute \src "libresoc.v:16616.3-16628.6" + process $proc$libresoc.v:16616$344 + assign { } { } + assign { } { } + assign $0\MUL_dec31_cr_in[2:0] $1\MUL_dec31_cr_in[2:0] + attribute \src "libresoc.v:16617.5-16617.29" + switch \initial + attribute \src "libresoc.v:16617.9-16617.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\MUL_dec31_cr_in[2:0] \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\MUL_dec31_cr_in[2:0] \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_cr_in + case + assign $1\MUL_dec31_cr_in[2:0] 3'000 + end + sync always + update \MUL_dec31_cr_in $0\MUL_dec31_cr_in[2:0] + end + attribute \src "libresoc.v:16629.3-16641.6" + process $proc$libresoc.v:16629$345 + assign { } { } + assign { } { } + assign $0\MUL_dec31_cr_out[2:0] $1\MUL_dec31_cr_out[2:0] + attribute \src "libresoc.v:16630.5-16630.29" + switch \initial + attribute \src "libresoc.v:16630.9-16630.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\MUL_dec31_cr_out[2:0] \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\MUL_dec31_cr_out[2:0] \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_cr_out + case + assign $1\MUL_dec31_cr_out[2:0] 3'000 + end + sync always + update \MUL_dec31_cr_out $0\MUL_dec31_cr_out[2:0] + end + attribute \src "libresoc.v:16642.3-16654.6" + process $proc$libresoc.v:16642$346 + assign { } { } + assign { } { } + assign $0\MUL_dec31_rc_sel[1:0] $1\MUL_dec31_rc_sel[1:0] + attribute \src "libresoc.v:16643.5-16643.29" + switch \initial + attribute \src "libresoc.v:16643.9-16643.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\MUL_dec31_rc_sel[1:0] \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\MUL_dec31_rc_sel[1:0] \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_rc_sel + case + assign $1\MUL_dec31_rc_sel[1:0] 2'00 + end + sync always + update \MUL_dec31_rc_sel $0\MUL_dec31_rc_sel[1:0] + end + connect \MUL_dec31_dec_sub11_opcode_in \opcode_in + connect \MUL_dec31_dec_sub9_opcode_in \opcode_in + connect \opc_in \opcode_switch [4:0] + connect \opcode_switch \opcode_in [10:1] +end +attribute \src "libresoc.v:16663.1-17014.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_MUL.dec.MUL_dec31.MUL_dec31_dec_sub11" +attribute \generator "nMigen" +module \MUL_dec31_dec_sub11 + attribute \src "libresoc.v:16888.3-16912.6" + wire width 3 $0\MUL_dec31_dec_sub11_cr_in[2:0] + attribute \src "libresoc.v:16913.3-16937.6" + wire width 3 $0\MUL_dec31_dec_sub11_cr_out[2:0] + attribute \src "libresoc.v:16813.3-16837.6" + wire width 12 $0\MUL_dec31_dec_sub11_function_unit[11:0] + attribute \src "libresoc.v:16863.3-16887.6" + wire width 4 $0\MUL_dec31_dec_sub11_in2_sel[3:0] + attribute \src "libresoc.v:16838.3-16862.6" + wire width 7 $0\MUL_dec31_dec_sub11_internal_op[6:0] + attribute \src "libresoc.v:16963.3-16987.6" + wire $0\MUL_dec31_dec_sub11_is_32b[0:0] + attribute \src "libresoc.v:16938.3-16962.6" + wire width 2 $0\MUL_dec31_dec_sub11_rc_sel[1:0] + attribute \src "libresoc.v:16988.3-17012.6" + wire $0\MUL_dec31_dec_sub11_sgn[0:0] + attribute \src "libresoc.v:16664.7-16664.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:16888.3-16912.6" + wire width 3 $1\MUL_dec31_dec_sub11_cr_in[2:0] + attribute \src "libresoc.v:16913.3-16937.6" + wire width 3 $1\MUL_dec31_dec_sub11_cr_out[2:0] + attribute \src "libresoc.v:16813.3-16837.6" + wire width 12 $1\MUL_dec31_dec_sub11_function_unit[11:0] + attribute \src "libresoc.v:16863.3-16887.6" + wire width 4 $1\MUL_dec31_dec_sub11_in2_sel[3:0] + attribute \src "libresoc.v:16838.3-16862.6" + wire width 7 $1\MUL_dec31_dec_sub11_internal_op[6:0] + attribute \src "libresoc.v:16963.3-16987.6" + wire $1\MUL_dec31_dec_sub11_is_32b[0:0] + attribute \src "libresoc.v:16938.3-16962.6" + wire width 2 $1\MUL_dec31_dec_sub11_rc_sel[1:0] + attribute \src "libresoc.v:16988.3-17012.6" + wire $1\MUL_dec31_dec_sub11_sgn[0:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 4 \MUL_dec31_dec_sub11_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \MUL_dec31_dec_sub11_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \MUL_dec31_dec_sub11_function_unit + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 3 \MUL_dec31_dec_sub11_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \MUL_dec31_dec_sub11_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 7 \MUL_dec31_dec_sub11_is_32b + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 6 \MUL_dec31_dec_sub11_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 8 \MUL_dec31_dec_sub11_sgn + attribute \src "libresoc.v:16664.7-16664.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 9 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 5 \opcode_switch + attribute \src "libresoc.v:16664.7-16664.20" + process $proc$libresoc.v:16664$356 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:16813.3-16837.6" + process $proc$libresoc.v:16813$348 + assign { } { } + assign { } { } + assign $0\MUL_dec31_dec_sub11_function_unit[11:0] $1\MUL_dec31_dec_sub11_function_unit[11:0] + attribute \src "libresoc.v:16814.5-16814.29" + switch \initial + attribute \src "libresoc.v:16814.9-16814.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\MUL_dec31_dec_sub11_function_unit[11:0] 12'000100000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\MUL_dec31_dec_sub11_function_unit[11:0] 12'000100000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\MUL_dec31_dec_sub11_function_unit[11:0] 12'000100000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\MUL_dec31_dec_sub11_function_unit[11:0] 12'000100000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\MUL_dec31_dec_sub11_function_unit[11:0] 12'000100000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\MUL_dec31_dec_sub11_function_unit[11:0] 12'000100000000 + case + assign $1\MUL_dec31_dec_sub11_function_unit[11:0] 12'000000000000 + end + sync always + update \MUL_dec31_dec_sub11_function_unit $0\MUL_dec31_dec_sub11_function_unit[11:0] + end + attribute \src "libresoc.v:16838.3-16862.6" + process $proc$libresoc.v:16838$349 + assign { } { } + assign { } { } + assign $0\MUL_dec31_dec_sub11_internal_op[6:0] $1\MUL_dec31_dec_sub11_internal_op[6:0] + attribute \src "libresoc.v:16839.5-16839.29" + switch \initial + attribute \src "libresoc.v:16839.9-16839.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\MUL_dec31_dec_sub11_internal_op[6:0] 7'0110100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\MUL_dec31_dec_sub11_internal_op[6:0] 7'0110100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\MUL_dec31_dec_sub11_internal_op[6:0] 7'0110100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\MUL_dec31_dec_sub11_internal_op[6:0] 7'0110100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\MUL_dec31_dec_sub11_internal_op[6:0] 7'0110010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\MUL_dec31_dec_sub11_internal_op[6:0] 7'0110010 + case + assign $1\MUL_dec31_dec_sub11_internal_op[6:0] 7'0000000 + end + sync always + update \MUL_dec31_dec_sub11_internal_op $0\MUL_dec31_dec_sub11_internal_op[6:0] + end + attribute \src "libresoc.v:16863.3-16887.6" + process $proc$libresoc.v:16863$350 + assign { } { } + assign { } { } + assign $0\MUL_dec31_dec_sub11_in2_sel[3:0] $1\MUL_dec31_dec_sub11_in2_sel[3:0] + attribute \src "libresoc.v:16864.5-16864.29" + switch \initial + attribute \src "libresoc.v:16864.9-16864.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\MUL_dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\MUL_dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\MUL_dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\MUL_dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\MUL_dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\MUL_dec31_dec_sub11_in2_sel[3:0] 4'0001 + case + assign $1\MUL_dec31_dec_sub11_in2_sel[3:0] 4'0000 + end + sync always + update \MUL_dec31_dec_sub11_in2_sel $0\MUL_dec31_dec_sub11_in2_sel[3:0] + end + attribute \src "libresoc.v:16888.3-16912.6" + process $proc$libresoc.v:16888$351 + assign { } { } + assign { } { } + assign $0\MUL_dec31_dec_sub11_cr_in[2:0] $1\MUL_dec31_dec_sub11_cr_in[2:0] + attribute \src "libresoc.v:16889.5-16889.29" + switch \initial + attribute \src "libresoc.v:16889.9-16889.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\MUL_dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\MUL_dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\MUL_dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\MUL_dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\MUL_dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\MUL_dec31_dec_sub11_cr_in[2:0] 3'000 + case + assign $1\MUL_dec31_dec_sub11_cr_in[2:0] 3'000 + end + sync always + update \MUL_dec31_dec_sub11_cr_in $0\MUL_dec31_dec_sub11_cr_in[2:0] + end + attribute \src "libresoc.v:16913.3-16937.6" + process $proc$libresoc.v:16913$352 + assign { } { } + assign { } { } + assign $0\MUL_dec31_dec_sub11_cr_out[2:0] $1\MUL_dec31_dec_sub11_cr_out[2:0] + attribute \src "libresoc.v:16914.5-16914.29" + switch \initial + attribute \src "libresoc.v:16914.9-16914.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\MUL_dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\MUL_dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\MUL_dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\MUL_dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\MUL_dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\MUL_dec31_dec_sub11_cr_out[2:0] 3'001 + case + assign $1\MUL_dec31_dec_sub11_cr_out[2:0] 3'000 + end + sync always + update \MUL_dec31_dec_sub11_cr_out $0\MUL_dec31_dec_sub11_cr_out[2:0] + end + attribute \src "libresoc.v:16938.3-16962.6" + process $proc$libresoc.v:16938$353 + assign { } { } + assign { } { } + assign $0\MUL_dec31_dec_sub11_rc_sel[1:0] $1\MUL_dec31_dec_sub11_rc_sel[1:0] + attribute \src "libresoc.v:16939.5-16939.29" + switch \initial + attribute \src "libresoc.v:16939.9-16939.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\MUL_dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\MUL_dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\MUL_dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\MUL_dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\MUL_dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\MUL_dec31_dec_sub11_rc_sel[1:0] 2'10 + case + assign $1\MUL_dec31_dec_sub11_rc_sel[1:0] 2'00 + end + sync always + update \MUL_dec31_dec_sub11_rc_sel $0\MUL_dec31_dec_sub11_rc_sel[1:0] + end + attribute \src "libresoc.v:16963.3-16987.6" + process $proc$libresoc.v:16963$354 + assign { } { } + assign { } { } + assign $0\MUL_dec31_dec_sub11_is_32b[0:0] $1\MUL_dec31_dec_sub11_is_32b[0:0] + attribute \src "libresoc.v:16964.5-16964.29" + switch \initial + attribute \src "libresoc.v:16964.9-16964.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\MUL_dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\MUL_dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\MUL_dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\MUL_dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\MUL_dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\MUL_dec31_dec_sub11_is_32b[0:0] 1'1 + case + assign $1\MUL_dec31_dec_sub11_is_32b[0:0] 1'0 + end + sync always + update \MUL_dec31_dec_sub11_is_32b $0\MUL_dec31_dec_sub11_is_32b[0:0] + end + attribute \src "libresoc.v:16988.3-17012.6" + process $proc$libresoc.v:16988$355 + assign { } { } + assign { } { } + assign $0\MUL_dec31_dec_sub11_sgn[0:0] $1\MUL_dec31_dec_sub11_sgn[0:0] + attribute \src "libresoc.v:16989.5-16989.29" + switch \initial + attribute \src "libresoc.v:16989.9-16989.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\MUL_dec31_dec_sub11_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\MUL_dec31_dec_sub11_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\MUL_dec31_dec_sub11_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\MUL_dec31_dec_sub11_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\MUL_dec31_dec_sub11_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\MUL_dec31_dec_sub11_sgn[0:0] 1'1 + case + assign $1\MUL_dec31_dec_sub11_sgn[0:0] 1'0 + end + sync always + update \MUL_dec31_dec_sub11_sgn $0\MUL_dec31_dec_sub11_sgn[0:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:17018.1-17369.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_MUL.dec.MUL_dec31.MUL_dec31_dec_sub9" +attribute \generator "nMigen" +module \MUL_dec31_dec_sub9 + attribute \src "libresoc.v:17243.3-17267.6" + wire width 3 $0\MUL_dec31_dec_sub9_cr_in[2:0] + attribute \src "libresoc.v:17268.3-17292.6" + wire width 3 $0\MUL_dec31_dec_sub9_cr_out[2:0] + attribute \src "libresoc.v:17168.3-17192.6" + wire width 12 $0\MUL_dec31_dec_sub9_function_unit[11:0] + attribute \src "libresoc.v:17218.3-17242.6" + wire width 4 $0\MUL_dec31_dec_sub9_in2_sel[3:0] + attribute \src "libresoc.v:17193.3-17217.6" + wire width 7 $0\MUL_dec31_dec_sub9_internal_op[6:0] + attribute \src "libresoc.v:17318.3-17342.6" + wire $0\MUL_dec31_dec_sub9_is_32b[0:0] + attribute \src "libresoc.v:17293.3-17317.6" + wire width 2 $0\MUL_dec31_dec_sub9_rc_sel[1:0] + attribute \src "libresoc.v:17343.3-17367.6" + wire $0\MUL_dec31_dec_sub9_sgn[0:0] + attribute \src "libresoc.v:17019.7-17019.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:17243.3-17267.6" + wire width 3 $1\MUL_dec31_dec_sub9_cr_in[2:0] + attribute \src "libresoc.v:17268.3-17292.6" + wire width 3 $1\MUL_dec31_dec_sub9_cr_out[2:0] + attribute \src "libresoc.v:17168.3-17192.6" + wire width 12 $1\MUL_dec31_dec_sub9_function_unit[11:0] + attribute \src "libresoc.v:17218.3-17242.6" + wire width 4 $1\MUL_dec31_dec_sub9_in2_sel[3:0] + attribute \src "libresoc.v:17193.3-17217.6" + wire width 7 $1\MUL_dec31_dec_sub9_internal_op[6:0] + attribute \src "libresoc.v:17318.3-17342.6" + wire $1\MUL_dec31_dec_sub9_is_32b[0:0] + attribute \src "libresoc.v:17293.3-17317.6" + wire width 2 $1\MUL_dec31_dec_sub9_rc_sel[1:0] + attribute \src "libresoc.v:17343.3-17367.6" + wire $1\MUL_dec31_dec_sub9_sgn[0:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 4 \MUL_dec31_dec_sub9_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \MUL_dec31_dec_sub9_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \MUL_dec31_dec_sub9_function_unit + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 3 \MUL_dec31_dec_sub9_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \MUL_dec31_dec_sub9_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 7 \MUL_dec31_dec_sub9_is_32b + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 6 \MUL_dec31_dec_sub9_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 8 \MUL_dec31_dec_sub9_sgn + attribute \src "libresoc.v:17019.7-17019.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 9 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 5 \opcode_switch + attribute \src "libresoc.v:17019.7-17019.20" + process $proc$libresoc.v:17019$365 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:17168.3-17192.6" + process $proc$libresoc.v:17168$357 + assign { } { } + assign { } { } + assign $0\MUL_dec31_dec_sub9_function_unit[11:0] $1\MUL_dec31_dec_sub9_function_unit[11:0] + attribute \src "libresoc.v:17169.5-17169.29" + switch \initial + attribute \src "libresoc.v:17169.9-17169.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\MUL_dec31_dec_sub9_function_unit[11:0] 12'000100000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\MUL_dec31_dec_sub9_function_unit[11:0] 12'000100000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\MUL_dec31_dec_sub9_function_unit[11:0] 12'000100000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\MUL_dec31_dec_sub9_function_unit[11:0] 12'000100000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\MUL_dec31_dec_sub9_function_unit[11:0] 12'000100000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\MUL_dec31_dec_sub9_function_unit[11:0] 12'000100000000 + case + assign $1\MUL_dec31_dec_sub9_function_unit[11:0] 12'000000000000 + end + sync always + update \MUL_dec31_dec_sub9_function_unit $0\MUL_dec31_dec_sub9_function_unit[11:0] + end + attribute \src "libresoc.v:17193.3-17217.6" + process $proc$libresoc.v:17193$358 + assign { } { } + assign { } { } + assign $0\MUL_dec31_dec_sub9_internal_op[6:0] $1\MUL_dec31_dec_sub9_internal_op[6:0] + attribute \src "libresoc.v:17194.5-17194.29" + switch \initial + attribute \src "libresoc.v:17194.9-17194.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\MUL_dec31_dec_sub9_internal_op[6:0] 7'0110011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\MUL_dec31_dec_sub9_internal_op[6:0] 7'0110011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\MUL_dec31_dec_sub9_internal_op[6:0] 7'0110011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\MUL_dec31_dec_sub9_internal_op[6:0] 7'0110011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\MUL_dec31_dec_sub9_internal_op[6:0] 7'0110010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\MUL_dec31_dec_sub9_internal_op[6:0] 7'0110010 + case + assign $1\MUL_dec31_dec_sub9_internal_op[6:0] 7'0000000 + end + sync always + update \MUL_dec31_dec_sub9_internal_op $0\MUL_dec31_dec_sub9_internal_op[6:0] + end + attribute \src "libresoc.v:17218.3-17242.6" + process $proc$libresoc.v:17218$359 + assign { } { } + assign { } { } + assign $0\MUL_dec31_dec_sub9_in2_sel[3:0] $1\MUL_dec31_dec_sub9_in2_sel[3:0] + attribute \src "libresoc.v:17219.5-17219.29" + switch \initial + attribute \src "libresoc.v:17219.9-17219.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\MUL_dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\MUL_dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\MUL_dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\MUL_dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\MUL_dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\MUL_dec31_dec_sub9_in2_sel[3:0] 4'0001 + case + assign $1\MUL_dec31_dec_sub9_in2_sel[3:0] 4'0000 + end + sync always + update \MUL_dec31_dec_sub9_in2_sel $0\MUL_dec31_dec_sub9_in2_sel[3:0] + end + attribute \src "libresoc.v:17243.3-17267.6" + process $proc$libresoc.v:17243$360 + assign { } { } + assign { } { } + assign $0\MUL_dec31_dec_sub9_cr_in[2:0] $1\MUL_dec31_dec_sub9_cr_in[2:0] + attribute \src "libresoc.v:17244.5-17244.29" + switch \initial + attribute \src "libresoc.v:17244.9-17244.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\MUL_dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\MUL_dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\MUL_dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\MUL_dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\MUL_dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\MUL_dec31_dec_sub9_cr_in[2:0] 3'000 + case + assign $1\MUL_dec31_dec_sub9_cr_in[2:0] 3'000 + end + sync always + update \MUL_dec31_dec_sub9_cr_in $0\MUL_dec31_dec_sub9_cr_in[2:0] + end + attribute \src "libresoc.v:17268.3-17292.6" + process $proc$libresoc.v:17268$361 + assign { } { } + assign { } { } + assign $0\MUL_dec31_dec_sub9_cr_out[2:0] $1\MUL_dec31_dec_sub9_cr_out[2:0] + attribute \src "libresoc.v:17269.5-17269.29" + switch \initial + attribute \src "libresoc.v:17269.9-17269.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\MUL_dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\MUL_dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\MUL_dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\MUL_dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\MUL_dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\MUL_dec31_dec_sub9_cr_out[2:0] 3'001 + case + assign $1\MUL_dec31_dec_sub9_cr_out[2:0] 3'000 + end + sync always + update \MUL_dec31_dec_sub9_cr_out $0\MUL_dec31_dec_sub9_cr_out[2:0] + end + attribute \src "libresoc.v:17293.3-17317.6" + process $proc$libresoc.v:17293$362 + assign { } { } + assign { } { } + assign $0\MUL_dec31_dec_sub9_rc_sel[1:0] $1\MUL_dec31_dec_sub9_rc_sel[1:0] + attribute \src "libresoc.v:17294.5-17294.29" + switch \initial + attribute \src "libresoc.v:17294.9-17294.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\MUL_dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\MUL_dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\MUL_dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\MUL_dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\MUL_dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\MUL_dec31_dec_sub9_rc_sel[1:0] 2'10 + case + assign $1\MUL_dec31_dec_sub9_rc_sel[1:0] 2'00 + end + sync always + update \MUL_dec31_dec_sub9_rc_sel $0\MUL_dec31_dec_sub9_rc_sel[1:0] + end + attribute \src "libresoc.v:17318.3-17342.6" + process $proc$libresoc.v:17318$363 + assign { } { } + assign { } { } + assign $0\MUL_dec31_dec_sub9_is_32b[0:0] $1\MUL_dec31_dec_sub9_is_32b[0:0] + attribute \src "libresoc.v:17319.5-17319.29" + switch \initial + attribute \src "libresoc.v:17319.9-17319.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\MUL_dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\MUL_dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\MUL_dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\MUL_dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\MUL_dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\MUL_dec31_dec_sub9_is_32b[0:0] 1'0 + case + assign $1\MUL_dec31_dec_sub9_is_32b[0:0] 1'0 + end + sync always + update \MUL_dec31_dec_sub9_is_32b $0\MUL_dec31_dec_sub9_is_32b[0:0] + end + attribute \src "libresoc.v:17343.3-17367.6" + process $proc$libresoc.v:17343$364 + assign { } { } + assign { } { } + assign $0\MUL_dec31_dec_sub9_sgn[0:0] $1\MUL_dec31_dec_sub9_sgn[0:0] + attribute \src "libresoc.v:17344.5-17344.29" + switch \initial + attribute \src "libresoc.v:17344.9-17344.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\MUL_dec31_dec_sub9_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\MUL_dec31_dec_sub9_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\MUL_dec31_dec_sub9_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\MUL_dec31_dec_sub9_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\MUL_dec31_dec_sub9_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\MUL_dec31_dec_sub9_sgn[0:0] 1'1 + case + assign $1\MUL_dec31_dec_sub9_sgn[0:0] 1'0 + end + sync always + update \MUL_dec31_dec_sub9_sgn $0\MUL_dec31_dec_sub9_sgn[0:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:17373.1-17904.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_SHIFT_ROT.dec.SHIFT_ROT_dec30" +attribute \generator "nMigen" +module \SHIFT_ROT_dec30 + attribute \src "libresoc.v:17681.3-17717.6" + wire width 3 $0\SHIFT_ROT_dec30_cr_in[2:0] + attribute \src "libresoc.v:17718.3-17754.6" + wire width 3 $0\SHIFT_ROT_dec30_cr_out[2:0] + attribute \src "libresoc.v:17792.3-17828.6" + wire width 2 $0\SHIFT_ROT_dec30_cry_in[1:0] + attribute \src "libresoc.v:17829.3-17865.6" + wire $0\SHIFT_ROT_dec30_cry_out[0:0] + attribute \src "libresoc.v:17533.3-17569.6" + wire width 12 $0\SHIFT_ROT_dec30_function_unit[11:0] + attribute \src "libresoc.v:17644.3-17680.6" + wire width 4 $0\SHIFT_ROT_dec30_in2_sel[3:0] + attribute \src "libresoc.v:17607.3-17643.6" + wire width 7 $0\SHIFT_ROT_dec30_internal_op[6:0] + attribute \src "libresoc.v:17866.3-17902.6" + wire $0\SHIFT_ROT_dec30_is_32b[0:0] + attribute \src "libresoc.v:17755.3-17791.6" + wire width 2 $0\SHIFT_ROT_dec30_rc_sel[1:0] + attribute \src "libresoc.v:17570.3-17606.6" + wire $0\SHIFT_ROT_dec30_sgn[0:0] + attribute \src "libresoc.v:17374.7-17374.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:17681.3-17717.6" + wire width 3 $1\SHIFT_ROT_dec30_cr_in[2:0] + attribute \src "libresoc.v:17718.3-17754.6" + wire width 3 $1\SHIFT_ROT_dec30_cr_out[2:0] + attribute \src "libresoc.v:17792.3-17828.6" + wire width 2 $1\SHIFT_ROT_dec30_cry_in[1:0] + attribute \src "libresoc.v:17829.3-17865.6" + wire $1\SHIFT_ROT_dec30_cry_out[0:0] + attribute \src "libresoc.v:17533.3-17569.6" + wire width 12 $1\SHIFT_ROT_dec30_function_unit[11:0] + attribute \src "libresoc.v:17644.3-17680.6" + wire width 4 $1\SHIFT_ROT_dec30_in2_sel[3:0] + attribute \src "libresoc.v:17607.3-17643.6" + wire width 7 $1\SHIFT_ROT_dec30_internal_op[6:0] + attribute \src "libresoc.v:17866.3-17902.6" + wire $1\SHIFT_ROT_dec30_is_32b[0:0] + attribute \src "libresoc.v:17755.3-17791.6" + wire width 2 $1\SHIFT_ROT_dec30_rc_sel[1:0] + attribute \src "libresoc.v:17570.3-17606.6" + wire $1\SHIFT_ROT_dec30_sgn[0:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 4 \SHIFT_ROT_dec30_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \SHIFT_ROT_dec30_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 7 \SHIFT_ROT_dec30_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 8 \SHIFT_ROT_dec30_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \SHIFT_ROT_dec30_function_unit + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 3 \SHIFT_ROT_dec30_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \SHIFT_ROT_dec30_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 9 \SHIFT_ROT_dec30_is_32b + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 6 \SHIFT_ROT_dec30_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 10 \SHIFT_ROT_dec30_sgn + attribute \src "libresoc.v:17374.7-17374.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 11 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 4 \opcode_switch + attribute \src "libresoc.v:17374.7-17374.20" + process $proc$libresoc.v:17374$376 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:17533.3-17569.6" + process $proc$libresoc.v:17533$366 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec30_function_unit[11:0] $1\SHIFT_ROT_dec30_function_unit[11:0] + attribute \src "libresoc.v:17534.5-17534.29" + switch \initial + attribute \src "libresoc.v:17534.9-17534.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\SHIFT_ROT_dec30_function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\SHIFT_ROT_dec30_function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\SHIFT_ROT_dec30_function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\SHIFT_ROT_dec30_function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\SHIFT_ROT_dec30_function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\SHIFT_ROT_dec30_function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\SHIFT_ROT_dec30_function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\SHIFT_ROT_dec30_function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\SHIFT_ROT_dec30_function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\SHIFT_ROT_dec30_function_unit[11:0] 12'000000001000 + case + assign $1\SHIFT_ROT_dec30_function_unit[11:0] 12'000000000000 + end + sync always + update \SHIFT_ROT_dec30_function_unit $0\SHIFT_ROT_dec30_function_unit[11:0] + end + attribute \src "libresoc.v:17570.3-17606.6" + process $proc$libresoc.v:17570$367 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec30_sgn[0:0] $1\SHIFT_ROT_dec30_sgn[0:0] + attribute \src "libresoc.v:17571.5-17571.29" + switch \initial + attribute \src "libresoc.v:17571.9-17571.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\SHIFT_ROT_dec30_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\SHIFT_ROT_dec30_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\SHIFT_ROT_dec30_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\SHIFT_ROT_dec30_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\SHIFT_ROT_dec30_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\SHIFT_ROT_dec30_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\SHIFT_ROT_dec30_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\SHIFT_ROT_dec30_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\SHIFT_ROT_dec30_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\SHIFT_ROT_dec30_sgn[0:0] 1'0 + case + assign $1\SHIFT_ROT_dec30_sgn[0:0] 1'0 + end + sync always + update \SHIFT_ROT_dec30_sgn $0\SHIFT_ROT_dec30_sgn[0:0] + end + attribute \src "libresoc.v:17607.3-17643.6" + process $proc$libresoc.v:17607$368 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec30_internal_op[6:0] $1\SHIFT_ROT_dec30_internal_op[6:0] + attribute \src "libresoc.v:17608.5-17608.29" + switch \initial + attribute \src "libresoc.v:17608.9-17608.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\SHIFT_ROT_dec30_internal_op[6:0] 7'0111000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\SHIFT_ROT_dec30_internal_op[6:0] 7'0111000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\SHIFT_ROT_dec30_internal_op[6:0] 7'0111001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\SHIFT_ROT_dec30_internal_op[6:0] 7'0111001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\SHIFT_ROT_dec30_internal_op[6:0] 7'0111010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\SHIFT_ROT_dec30_internal_op[6:0] 7'0111010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\SHIFT_ROT_dec30_internal_op[6:0] 7'0111000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\SHIFT_ROT_dec30_internal_op[6:0] 7'0111000 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\SHIFT_ROT_dec30_internal_op[6:0] 7'0111001 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\SHIFT_ROT_dec30_internal_op[6:0] 7'0111010 + case + assign $1\SHIFT_ROT_dec30_internal_op[6:0] 7'0000000 + end + sync always + update \SHIFT_ROT_dec30_internal_op $0\SHIFT_ROT_dec30_internal_op[6:0] + end + attribute \src "libresoc.v:17644.3-17680.6" + process $proc$libresoc.v:17644$369 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec30_in2_sel[3:0] $1\SHIFT_ROT_dec30_in2_sel[3:0] + attribute \src "libresoc.v:17645.5-17645.29" + switch \initial + attribute \src "libresoc.v:17645.9-17645.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\SHIFT_ROT_dec30_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\SHIFT_ROT_dec30_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\SHIFT_ROT_dec30_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\SHIFT_ROT_dec30_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\SHIFT_ROT_dec30_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\SHIFT_ROT_dec30_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\SHIFT_ROT_dec30_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\SHIFT_ROT_dec30_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\SHIFT_ROT_dec30_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\SHIFT_ROT_dec30_in2_sel[3:0] 4'0001 + case + assign $1\SHIFT_ROT_dec30_in2_sel[3:0] 4'0000 + end + sync always + update \SHIFT_ROT_dec30_in2_sel $0\SHIFT_ROT_dec30_in2_sel[3:0] + end + attribute \src "libresoc.v:17681.3-17717.6" + process $proc$libresoc.v:17681$370 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec30_cr_in[2:0] $1\SHIFT_ROT_dec30_cr_in[2:0] + attribute \src "libresoc.v:17682.5-17682.29" + switch \initial + attribute \src "libresoc.v:17682.9-17682.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\SHIFT_ROT_dec30_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\SHIFT_ROT_dec30_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\SHIFT_ROT_dec30_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\SHIFT_ROT_dec30_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\SHIFT_ROT_dec30_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\SHIFT_ROT_dec30_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\SHIFT_ROT_dec30_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\SHIFT_ROT_dec30_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\SHIFT_ROT_dec30_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\SHIFT_ROT_dec30_cr_in[2:0] 3'000 + case + assign $1\SHIFT_ROT_dec30_cr_in[2:0] 3'000 + end + sync always + update \SHIFT_ROT_dec30_cr_in $0\SHIFT_ROT_dec30_cr_in[2:0] + end + attribute \src "libresoc.v:17718.3-17754.6" + process $proc$libresoc.v:17718$371 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec30_cr_out[2:0] $1\SHIFT_ROT_dec30_cr_out[2:0] + attribute \src "libresoc.v:17719.5-17719.29" + switch \initial + attribute \src "libresoc.v:17719.9-17719.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\SHIFT_ROT_dec30_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\SHIFT_ROT_dec30_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\SHIFT_ROT_dec30_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\SHIFT_ROT_dec30_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\SHIFT_ROT_dec30_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\SHIFT_ROT_dec30_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\SHIFT_ROT_dec30_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\SHIFT_ROT_dec30_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\SHIFT_ROT_dec30_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\SHIFT_ROT_dec30_cr_out[2:0] 3'001 + case + assign $1\SHIFT_ROT_dec30_cr_out[2:0] 3'000 + end + sync always + update \SHIFT_ROT_dec30_cr_out $0\SHIFT_ROT_dec30_cr_out[2:0] + end + attribute \src "libresoc.v:17755.3-17791.6" + process $proc$libresoc.v:17755$372 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec30_rc_sel[1:0] $1\SHIFT_ROT_dec30_rc_sel[1:0] + attribute \src "libresoc.v:17756.5-17756.29" + switch \initial + attribute \src "libresoc.v:17756.9-17756.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\SHIFT_ROT_dec30_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\SHIFT_ROT_dec30_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\SHIFT_ROT_dec30_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\SHIFT_ROT_dec30_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\SHIFT_ROT_dec30_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\SHIFT_ROT_dec30_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\SHIFT_ROT_dec30_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\SHIFT_ROT_dec30_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\SHIFT_ROT_dec30_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\SHIFT_ROT_dec30_rc_sel[1:0] 2'10 + case + assign $1\SHIFT_ROT_dec30_rc_sel[1:0] 2'00 + end + sync always + update \SHIFT_ROT_dec30_rc_sel $0\SHIFT_ROT_dec30_rc_sel[1:0] + end + attribute \src "libresoc.v:17792.3-17828.6" + process $proc$libresoc.v:17792$373 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec30_cry_in[1:0] $1\SHIFT_ROT_dec30_cry_in[1:0] + attribute \src "libresoc.v:17793.5-17793.29" + switch \initial + attribute \src "libresoc.v:17793.9-17793.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\SHIFT_ROT_dec30_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\SHIFT_ROT_dec30_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\SHIFT_ROT_dec30_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\SHIFT_ROT_dec30_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\SHIFT_ROT_dec30_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\SHIFT_ROT_dec30_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\SHIFT_ROT_dec30_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\SHIFT_ROT_dec30_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\SHIFT_ROT_dec30_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\SHIFT_ROT_dec30_cry_in[1:0] 2'00 + case + assign $1\SHIFT_ROT_dec30_cry_in[1:0] 2'00 + end + sync always + update \SHIFT_ROT_dec30_cry_in $0\SHIFT_ROT_dec30_cry_in[1:0] + end + attribute \src "libresoc.v:17829.3-17865.6" + process $proc$libresoc.v:17829$374 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec30_cry_out[0:0] $1\SHIFT_ROT_dec30_cry_out[0:0] + attribute \src "libresoc.v:17830.5-17830.29" + switch \initial + attribute \src "libresoc.v:17830.9-17830.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\SHIFT_ROT_dec30_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\SHIFT_ROT_dec30_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\SHIFT_ROT_dec30_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\SHIFT_ROT_dec30_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\SHIFT_ROT_dec30_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\SHIFT_ROT_dec30_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\SHIFT_ROT_dec30_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\SHIFT_ROT_dec30_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\SHIFT_ROT_dec30_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\SHIFT_ROT_dec30_cry_out[0:0] 1'0 + case + assign $1\SHIFT_ROT_dec30_cry_out[0:0] 1'0 + end + sync always + update \SHIFT_ROT_dec30_cry_out $0\SHIFT_ROT_dec30_cry_out[0:0] + end + attribute \src "libresoc.v:17866.3-17902.6" + process $proc$libresoc.v:17866$375 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec30_is_32b[0:0] $1\SHIFT_ROT_dec30_is_32b[0:0] + attribute \src "libresoc.v:17867.5-17867.29" + switch \initial + attribute \src "libresoc.v:17867.9-17867.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\SHIFT_ROT_dec30_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\SHIFT_ROT_dec30_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\SHIFT_ROT_dec30_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\SHIFT_ROT_dec30_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\SHIFT_ROT_dec30_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\SHIFT_ROT_dec30_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\SHIFT_ROT_dec30_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\SHIFT_ROT_dec30_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\SHIFT_ROT_dec30_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\SHIFT_ROT_dec30_is_32b[0:0] 1'0 + case + assign $1\SHIFT_ROT_dec30_is_32b[0:0] 1'0 + end + sync always + update \SHIFT_ROT_dec30_is_32b $0\SHIFT_ROT_dec30_is_32b[0:0] + end + connect \opcode_switch \opcode_in [4:1] +end +attribute \src "libresoc.v:17908.1-18712.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_SHIFT_ROT.dec.SHIFT_ROT_dec31" +attribute \generator "nMigen" +module \SHIFT_ROT_dec31 + attribute \src "libresoc.v:18675.3-18690.6" + wire width 3 $0\SHIFT_ROT_dec31_cr_in[2:0] + attribute \src "libresoc.v:18691.3-18706.6" + wire width 3 $0\SHIFT_ROT_dec31_cr_out[2:0] + attribute \src "libresoc.v:18563.3-18578.6" + wire width 2 $0\SHIFT_ROT_dec31_cry_in[1:0] + attribute \src "libresoc.v:18579.3-18594.6" + wire $0\SHIFT_ROT_dec31_cry_out[0:0] + attribute \src "libresoc.v:18627.3-18642.6" + wire width 12 $0\SHIFT_ROT_dec31_function_unit[11:0] + attribute \src "libresoc.v:18659.3-18674.6" + wire width 4 $0\SHIFT_ROT_dec31_in2_sel[3:0] + attribute \src "libresoc.v:18643.3-18658.6" + wire width 7 $0\SHIFT_ROT_dec31_internal_op[6:0] + attribute \src "libresoc.v:18595.3-18610.6" + wire $0\SHIFT_ROT_dec31_is_32b[0:0] + attribute \src "libresoc.v:18547.3-18562.6" + wire width 2 $0\SHIFT_ROT_dec31_rc_sel[1:0] + attribute \src "libresoc.v:18611.3-18626.6" + wire $0\SHIFT_ROT_dec31_sgn[0:0] + attribute \src "libresoc.v:17909.7-17909.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:18675.3-18690.6" + wire width 3 $1\SHIFT_ROT_dec31_cr_in[2:0] + attribute \src "libresoc.v:18691.3-18706.6" + wire width 3 $1\SHIFT_ROT_dec31_cr_out[2:0] + attribute \src "libresoc.v:18563.3-18578.6" + wire width 2 $1\SHIFT_ROT_dec31_cry_in[1:0] + attribute \src "libresoc.v:18579.3-18594.6" + wire $1\SHIFT_ROT_dec31_cry_out[0:0] + attribute \src "libresoc.v:18627.3-18642.6" + wire width 12 $1\SHIFT_ROT_dec31_function_unit[11:0] + attribute \src "libresoc.v:18659.3-18674.6" + wire width 4 $1\SHIFT_ROT_dec31_in2_sel[3:0] + attribute \src "libresoc.v:18643.3-18658.6" + wire width 7 $1\SHIFT_ROT_dec31_internal_op[6:0] + attribute \src "libresoc.v:18595.3-18610.6" + wire $1\SHIFT_ROT_dec31_is_32b[0:0] + attribute \src "libresoc.v:18547.3-18562.6" + wire width 2 $1\SHIFT_ROT_dec31_rc_sel[1:0] + attribute \src "libresoc.v:18611.3-18626.6" + wire $1\SHIFT_ROT_dec31_sgn[0:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 4 \SHIFT_ROT_dec31_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \SHIFT_ROT_dec31_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 7 \SHIFT_ROT_dec31_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 8 \SHIFT_ROT_dec31_cry_out + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_function_unit + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_is_32b + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \SHIFT_ROT_dec31_dec_sub24_opcode_in + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_function_unit + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_is_32b + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \SHIFT_ROT_dec31_dec_sub26_opcode_in + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_function_unit + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_is_32b + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \SHIFT_ROT_dec31_dec_sub27_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \SHIFT_ROT_dec31_function_unit + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 3 \SHIFT_ROT_dec31_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \SHIFT_ROT_dec31_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 9 \SHIFT_ROT_dec31_is_32b + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 6 \SHIFT_ROT_dec31_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 10 \SHIFT_ROT_dec31_sgn + attribute \src "libresoc.v:17909.7-17909.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:326" + wire width 5 \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 11 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 10 \opcode_switch + attribute \module_not_derived 1 + attribute \src "libresoc.v:18508.29-18520.4" + cell \SHIFT_ROT_dec31_dec_sub24 \SHIFT_ROT_dec31_dec_sub24 + connect \SHIFT_ROT_dec31_dec_sub24_cr_in \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cr_in + connect \SHIFT_ROT_dec31_dec_sub24_cr_out \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cr_out + connect \SHIFT_ROT_dec31_dec_sub24_cry_in \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cry_in + connect \SHIFT_ROT_dec31_dec_sub24_cry_out \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cry_out + connect \SHIFT_ROT_dec31_dec_sub24_function_unit \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_function_unit + connect \SHIFT_ROT_dec31_dec_sub24_in2_sel \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_in2_sel + connect \SHIFT_ROT_dec31_dec_sub24_internal_op \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_internal_op + connect \SHIFT_ROT_dec31_dec_sub24_is_32b \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_is_32b + connect \SHIFT_ROT_dec31_dec_sub24_rc_sel \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_rc_sel + connect \SHIFT_ROT_dec31_dec_sub24_sgn \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_sgn + connect \opcode_in \SHIFT_ROT_dec31_dec_sub24_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:18521.29-18533.4" + cell \SHIFT_ROT_dec31_dec_sub26 \SHIFT_ROT_dec31_dec_sub26 + connect \SHIFT_ROT_dec31_dec_sub26_cr_in \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cr_in + connect \SHIFT_ROT_dec31_dec_sub26_cr_out \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cr_out + connect \SHIFT_ROT_dec31_dec_sub26_cry_in \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cry_in + connect \SHIFT_ROT_dec31_dec_sub26_cry_out \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cry_out + connect \SHIFT_ROT_dec31_dec_sub26_function_unit \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_function_unit + connect \SHIFT_ROT_dec31_dec_sub26_in2_sel \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_in2_sel + connect \SHIFT_ROT_dec31_dec_sub26_internal_op \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_internal_op + connect \SHIFT_ROT_dec31_dec_sub26_is_32b \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_is_32b + connect \SHIFT_ROT_dec31_dec_sub26_rc_sel \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_rc_sel + connect \SHIFT_ROT_dec31_dec_sub26_sgn \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_sgn + connect \opcode_in \SHIFT_ROT_dec31_dec_sub26_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:18534.29-18546.4" + cell \SHIFT_ROT_dec31_dec_sub27 \SHIFT_ROT_dec31_dec_sub27 + connect \SHIFT_ROT_dec31_dec_sub27_cr_in \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cr_in + connect \SHIFT_ROT_dec31_dec_sub27_cr_out \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cr_out + connect \SHIFT_ROT_dec31_dec_sub27_cry_in \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cry_in + connect \SHIFT_ROT_dec31_dec_sub27_cry_out \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cry_out + connect \SHIFT_ROT_dec31_dec_sub27_function_unit \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_function_unit + connect \SHIFT_ROT_dec31_dec_sub27_in2_sel \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_in2_sel + connect \SHIFT_ROT_dec31_dec_sub27_internal_op \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_internal_op + connect \SHIFT_ROT_dec31_dec_sub27_is_32b \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_is_32b + connect \SHIFT_ROT_dec31_dec_sub27_rc_sel \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_rc_sel + connect \SHIFT_ROT_dec31_dec_sub27_sgn \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_sgn + connect \opcode_in \SHIFT_ROT_dec31_dec_sub27_opcode_in + end + attribute \src "libresoc.v:17909.7-17909.20" + process $proc$libresoc.v:17909$387 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:18547.3-18562.6" + process $proc$libresoc.v:18547$377 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_rc_sel[1:0] $1\SHIFT_ROT_dec31_rc_sel[1:0] + attribute \src "libresoc.v:18548.5-18548.29" + switch \initial + attribute \src "libresoc.v:18548.9-18548.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\SHIFT_ROT_dec31_rc_sel[1:0] \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_rc_sel[1:0] \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_rc_sel[1:0] \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_rc_sel + case + assign $1\SHIFT_ROT_dec31_rc_sel[1:0] 2'00 + end + sync always + update \SHIFT_ROT_dec31_rc_sel $0\SHIFT_ROT_dec31_rc_sel[1:0] + end + attribute \src "libresoc.v:18563.3-18578.6" + process $proc$libresoc.v:18563$378 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_cry_in[1:0] $1\SHIFT_ROT_dec31_cry_in[1:0] + attribute \src "libresoc.v:18564.5-18564.29" + switch \initial + attribute \src "libresoc.v:18564.9-18564.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\SHIFT_ROT_dec31_cry_in[1:0] \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_cry_in[1:0] \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_cry_in[1:0] \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cry_in + case + assign $1\SHIFT_ROT_dec31_cry_in[1:0] 2'00 + end + sync always + update \SHIFT_ROT_dec31_cry_in $0\SHIFT_ROT_dec31_cry_in[1:0] + end + attribute \src "libresoc.v:18579.3-18594.6" + process $proc$libresoc.v:18579$379 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_cry_out[0:0] $1\SHIFT_ROT_dec31_cry_out[0:0] + attribute \src "libresoc.v:18580.5-18580.29" + switch \initial + attribute \src "libresoc.v:18580.9-18580.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\SHIFT_ROT_dec31_cry_out[0:0] \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_cry_out[0:0] \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_cry_out[0:0] \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cry_out + case + assign $1\SHIFT_ROT_dec31_cry_out[0:0] 1'0 + end + sync always + update \SHIFT_ROT_dec31_cry_out $0\SHIFT_ROT_dec31_cry_out[0:0] + end + attribute \src "libresoc.v:18595.3-18610.6" + process $proc$libresoc.v:18595$380 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_is_32b[0:0] $1\SHIFT_ROT_dec31_is_32b[0:0] + attribute \src "libresoc.v:18596.5-18596.29" + switch \initial + attribute \src "libresoc.v:18596.9-18596.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\SHIFT_ROT_dec31_is_32b[0:0] \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_is_32b[0:0] \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_is_32b[0:0] \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_is_32b + case + assign $1\SHIFT_ROT_dec31_is_32b[0:0] 1'0 + end + sync always + update \SHIFT_ROT_dec31_is_32b $0\SHIFT_ROT_dec31_is_32b[0:0] + end + attribute \src "libresoc.v:18611.3-18626.6" + process $proc$libresoc.v:18611$381 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_sgn[0:0] $1\SHIFT_ROT_dec31_sgn[0:0] + attribute \src "libresoc.v:18612.5-18612.29" + switch \initial + attribute \src "libresoc.v:18612.9-18612.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\SHIFT_ROT_dec31_sgn[0:0] \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_sgn[0:0] \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_sgn[0:0] \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_sgn + case + assign $1\SHIFT_ROT_dec31_sgn[0:0] 1'0 + end + sync always + update \SHIFT_ROT_dec31_sgn $0\SHIFT_ROT_dec31_sgn[0:0] + end + attribute \src "libresoc.v:18627.3-18642.6" + process $proc$libresoc.v:18627$382 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_function_unit[11:0] $1\SHIFT_ROT_dec31_function_unit[11:0] + attribute \src "libresoc.v:18628.5-18628.29" + switch \initial + attribute \src "libresoc.v:18628.9-18628.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\SHIFT_ROT_dec31_function_unit[11:0] \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_function_unit[11:0] \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_function_unit[11:0] \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_function_unit + case + assign $1\SHIFT_ROT_dec31_function_unit[11:0] 12'000000000000 + end + sync always + update \SHIFT_ROT_dec31_function_unit $0\SHIFT_ROT_dec31_function_unit[11:0] + end + attribute \src "libresoc.v:18643.3-18658.6" + process $proc$libresoc.v:18643$383 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_internal_op[6:0] $1\SHIFT_ROT_dec31_internal_op[6:0] + attribute \src "libresoc.v:18644.5-18644.29" + switch \initial + attribute \src "libresoc.v:18644.9-18644.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\SHIFT_ROT_dec31_internal_op[6:0] \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_internal_op[6:0] \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_internal_op[6:0] \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_internal_op + case + assign $1\SHIFT_ROT_dec31_internal_op[6:0] 7'0000000 + end + sync always + update \SHIFT_ROT_dec31_internal_op $0\SHIFT_ROT_dec31_internal_op[6:0] + end + attribute \src "libresoc.v:18659.3-18674.6" + process $proc$libresoc.v:18659$384 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_in2_sel[3:0] $1\SHIFT_ROT_dec31_in2_sel[3:0] + attribute \src "libresoc.v:18660.5-18660.29" + switch \initial + attribute \src "libresoc.v:18660.9-18660.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\SHIFT_ROT_dec31_in2_sel[3:0] \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_in2_sel[3:0] \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_in2_sel[3:0] \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_in2_sel + case + assign $1\SHIFT_ROT_dec31_in2_sel[3:0] 4'0000 + end + sync always + update \SHIFT_ROT_dec31_in2_sel $0\SHIFT_ROT_dec31_in2_sel[3:0] + end + attribute \src "libresoc.v:18675.3-18690.6" + process $proc$libresoc.v:18675$385 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_cr_in[2:0] $1\SHIFT_ROT_dec31_cr_in[2:0] + attribute \src "libresoc.v:18676.5-18676.29" + switch \initial + attribute \src "libresoc.v:18676.9-18676.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\SHIFT_ROT_dec31_cr_in[2:0] \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_cr_in[2:0] \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_cr_in[2:0] \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cr_in + case + assign $1\SHIFT_ROT_dec31_cr_in[2:0] 3'000 + end + sync always + update \SHIFT_ROT_dec31_cr_in $0\SHIFT_ROT_dec31_cr_in[2:0] + end + attribute \src "libresoc.v:18691.3-18706.6" + process $proc$libresoc.v:18691$386 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_cr_out[2:0] $1\SHIFT_ROT_dec31_cr_out[2:0] + attribute \src "libresoc.v:18692.5-18692.29" + switch \initial + attribute \src "libresoc.v:18692.9-18692.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\SHIFT_ROT_dec31_cr_out[2:0] \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_cr_out[2:0] \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_cr_out[2:0] \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cr_out + case + assign $1\SHIFT_ROT_dec31_cr_out[2:0] 3'000 + end + sync always + update \SHIFT_ROT_dec31_cr_out $0\SHIFT_ROT_dec31_cr_out[2:0] + end + connect \SHIFT_ROT_dec31_dec_sub24_opcode_in \opcode_in + connect \SHIFT_ROT_dec31_dec_sub27_opcode_in \opcode_in + connect \SHIFT_ROT_dec31_dec_sub26_opcode_in \opcode_in + connect \opc_in \opcode_switch [4:0] + connect \opcode_switch \opcode_in [10:1] +end +attribute \src "libresoc.v:18716.1-19067.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_SHIFT_ROT.dec.SHIFT_ROT_dec31.SHIFT_ROT_dec31_dec_sub24" +attribute \generator "nMigen" +module \SHIFT_ROT_dec31_dec_sub24 + attribute \src "libresoc.v:18952.3-18970.6" + wire width 3 $0\SHIFT_ROT_dec31_dec_sub24_cr_in[2:0] + attribute \src "libresoc.v:18971.3-18989.6" + wire width 3 $0\SHIFT_ROT_dec31_dec_sub24_cr_out[2:0] + attribute \src "libresoc.v:19009.3-19027.6" + wire width 2 $0\SHIFT_ROT_dec31_dec_sub24_cry_in[1:0] + attribute \src "libresoc.v:19028.3-19046.6" + wire $0\SHIFT_ROT_dec31_dec_sub24_cry_out[0:0] + attribute \src "libresoc.v:18876.3-18894.6" + wire width 12 $0\SHIFT_ROT_dec31_dec_sub24_function_unit[11:0] + attribute \src "libresoc.v:18933.3-18951.6" + wire width 4 $0\SHIFT_ROT_dec31_dec_sub24_in2_sel[3:0] + attribute \src "libresoc.v:18914.3-18932.6" + wire width 7 $0\SHIFT_ROT_dec31_dec_sub24_internal_op[6:0] + attribute \src "libresoc.v:19047.3-19065.6" + wire $0\SHIFT_ROT_dec31_dec_sub24_is_32b[0:0] + attribute \src "libresoc.v:18990.3-19008.6" + wire width 2 $0\SHIFT_ROT_dec31_dec_sub24_rc_sel[1:0] + attribute \src "libresoc.v:18895.3-18913.6" + wire $0\SHIFT_ROT_dec31_dec_sub24_sgn[0:0] + attribute \src "libresoc.v:18717.7-18717.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:18952.3-18970.6" + wire width 3 $1\SHIFT_ROT_dec31_dec_sub24_cr_in[2:0] + attribute \src "libresoc.v:18971.3-18989.6" + wire width 3 $1\SHIFT_ROT_dec31_dec_sub24_cr_out[2:0] + attribute \src "libresoc.v:19009.3-19027.6" + wire width 2 $1\SHIFT_ROT_dec31_dec_sub24_cry_in[1:0] + attribute \src "libresoc.v:19028.3-19046.6" + wire $1\SHIFT_ROT_dec31_dec_sub24_cry_out[0:0] + attribute \src "libresoc.v:18876.3-18894.6" + wire width 12 $1\SHIFT_ROT_dec31_dec_sub24_function_unit[11:0] + attribute \src "libresoc.v:18933.3-18951.6" + wire width 4 $1\SHIFT_ROT_dec31_dec_sub24_in2_sel[3:0] + attribute \src "libresoc.v:18914.3-18932.6" + wire width 7 $1\SHIFT_ROT_dec31_dec_sub24_internal_op[6:0] + attribute \src "libresoc.v:19047.3-19065.6" + wire $1\SHIFT_ROT_dec31_dec_sub24_is_32b[0:0] + attribute \src "libresoc.v:18990.3-19008.6" + wire width 2 $1\SHIFT_ROT_dec31_dec_sub24_rc_sel[1:0] + attribute \src "libresoc.v:18895.3-18913.6" + wire $1\SHIFT_ROT_dec31_dec_sub24_sgn[0:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 4 \SHIFT_ROT_dec31_dec_sub24_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \SHIFT_ROT_dec31_dec_sub24_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 7 \SHIFT_ROT_dec31_dec_sub24_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 8 \SHIFT_ROT_dec31_dec_sub24_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \SHIFT_ROT_dec31_dec_sub24_function_unit + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 3 \SHIFT_ROT_dec31_dec_sub24_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \SHIFT_ROT_dec31_dec_sub24_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 9 \SHIFT_ROT_dec31_dec_sub24_is_32b + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 6 \SHIFT_ROT_dec31_dec_sub24_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 10 \SHIFT_ROT_dec31_dec_sub24_sgn + attribute \src "libresoc.v:18717.7-18717.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 11 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 5 \opcode_switch + attribute \src "libresoc.v:18717.7-18717.20" + process $proc$libresoc.v:18717$398 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:18876.3-18894.6" + process $proc$libresoc.v:18876$388 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub24_function_unit[11:0] $1\SHIFT_ROT_dec31_dec_sub24_function_unit[11:0] + attribute \src "libresoc.v:18877.5-18877.29" + switch \initial + attribute \src "libresoc.v:18877.9-18877.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_function_unit[11:0] 12'000000001000 + case + assign $1\SHIFT_ROT_dec31_dec_sub24_function_unit[11:0] 12'000000000000 + end + sync always + update \SHIFT_ROT_dec31_dec_sub24_function_unit $0\SHIFT_ROT_dec31_dec_sub24_function_unit[11:0] + end + attribute \src "libresoc.v:18895.3-18913.6" + process $proc$libresoc.v:18895$389 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub24_sgn[0:0] $1\SHIFT_ROT_dec31_dec_sub24_sgn[0:0] + attribute \src "libresoc.v:18896.5-18896.29" + switch \initial + attribute \src "libresoc.v:18896.9-18896.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_sgn[0:0] 1'0 + case + assign $1\SHIFT_ROT_dec31_dec_sub24_sgn[0:0] 1'0 + end + sync always + update \SHIFT_ROT_dec31_dec_sub24_sgn $0\SHIFT_ROT_dec31_dec_sub24_sgn[0:0] + end + attribute \src "libresoc.v:18914.3-18932.6" + process $proc$libresoc.v:18914$390 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub24_internal_op[6:0] $1\SHIFT_ROT_dec31_dec_sub24_internal_op[6:0] + attribute \src "libresoc.v:18915.5-18915.29" + switch \initial + attribute \src "libresoc.v:18915.9-18915.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_internal_op[6:0] 7'0111100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_internal_op[6:0] 7'0111101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_internal_op[6:0] 7'0111101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_internal_op[6:0] 7'0111101 + case + assign $1\SHIFT_ROT_dec31_dec_sub24_internal_op[6:0] 7'0000000 + end + sync always + update \SHIFT_ROT_dec31_dec_sub24_internal_op $0\SHIFT_ROT_dec31_dec_sub24_internal_op[6:0] + end + attribute \src "libresoc.v:18933.3-18951.6" + process $proc$libresoc.v:18933$391 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub24_in2_sel[3:0] $1\SHIFT_ROT_dec31_dec_sub24_in2_sel[3:0] + attribute \src "libresoc.v:18934.5-18934.29" + switch \initial + attribute \src "libresoc.v:18934.9-18934.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_in2_sel[3:0] 4'1011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_in2_sel[3:0] 4'0001 + case + assign $1\SHIFT_ROT_dec31_dec_sub24_in2_sel[3:0] 4'0000 + end + sync always + update \SHIFT_ROT_dec31_dec_sub24_in2_sel $0\SHIFT_ROT_dec31_dec_sub24_in2_sel[3:0] + end + attribute \src "libresoc.v:18952.3-18970.6" + process $proc$libresoc.v:18952$392 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub24_cr_in[2:0] $1\SHIFT_ROT_dec31_dec_sub24_cr_in[2:0] + attribute \src "libresoc.v:18953.5-18953.29" + switch \initial + attribute \src "libresoc.v:18953.9-18953.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_cr_in[2:0] 3'000 + case + assign $1\SHIFT_ROT_dec31_dec_sub24_cr_in[2:0] 3'000 + end + sync always + update \SHIFT_ROT_dec31_dec_sub24_cr_in $0\SHIFT_ROT_dec31_dec_sub24_cr_in[2:0] + end + attribute \src "libresoc.v:18971.3-18989.6" + process $proc$libresoc.v:18971$393 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub24_cr_out[2:0] $1\SHIFT_ROT_dec31_dec_sub24_cr_out[2:0] + attribute \src "libresoc.v:18972.5-18972.29" + switch \initial + attribute \src "libresoc.v:18972.9-18972.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_cr_out[2:0] 3'001 + case + assign $1\SHIFT_ROT_dec31_dec_sub24_cr_out[2:0] 3'000 + end + sync always + update \SHIFT_ROT_dec31_dec_sub24_cr_out $0\SHIFT_ROT_dec31_dec_sub24_cr_out[2:0] + end + attribute \src "libresoc.v:18990.3-19008.6" + process $proc$libresoc.v:18990$394 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub24_rc_sel[1:0] $1\SHIFT_ROT_dec31_dec_sub24_rc_sel[1:0] + attribute \src "libresoc.v:18991.5-18991.29" + switch \initial + attribute \src "libresoc.v:18991.9-18991.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_rc_sel[1:0] 2'10 + case + assign $1\SHIFT_ROT_dec31_dec_sub24_rc_sel[1:0] 2'00 + end + sync always + update \SHIFT_ROT_dec31_dec_sub24_rc_sel $0\SHIFT_ROT_dec31_dec_sub24_rc_sel[1:0] + end + attribute \src "libresoc.v:19009.3-19027.6" + process $proc$libresoc.v:19009$395 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub24_cry_in[1:0] $1\SHIFT_ROT_dec31_dec_sub24_cry_in[1:0] + attribute \src "libresoc.v:19010.5-19010.29" + switch \initial + attribute \src "libresoc.v:19010.9-19010.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_cry_in[1:0] 2'00 + case + assign $1\SHIFT_ROT_dec31_dec_sub24_cry_in[1:0] 2'00 + end + sync always + update \SHIFT_ROT_dec31_dec_sub24_cry_in $0\SHIFT_ROT_dec31_dec_sub24_cry_in[1:0] + end + attribute \src "libresoc.v:19028.3-19046.6" + process $proc$libresoc.v:19028$396 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub24_cry_out[0:0] $1\SHIFT_ROT_dec31_dec_sub24_cry_out[0:0] + attribute \src "libresoc.v:19029.5-19029.29" + switch \initial + attribute \src "libresoc.v:19029.9-19029.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_cry_out[0:0] 1'0 + case + assign $1\SHIFT_ROT_dec31_dec_sub24_cry_out[0:0] 1'0 + end + sync always + update \SHIFT_ROT_dec31_dec_sub24_cry_out $0\SHIFT_ROT_dec31_dec_sub24_cry_out[0:0] + end + attribute \src "libresoc.v:19047.3-19065.6" + process $proc$libresoc.v:19047$397 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub24_is_32b[0:0] $1\SHIFT_ROT_dec31_dec_sub24_is_32b[0:0] + attribute \src "libresoc.v:19048.5-19048.29" + switch \initial + attribute \src "libresoc.v:19048.9-19048.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_is_32b[0:0] 1'1 + case + assign $1\SHIFT_ROT_dec31_dec_sub24_is_32b[0:0] 1'0 + end + sync always + update \SHIFT_ROT_dec31_dec_sub24_is_32b $0\SHIFT_ROT_dec31_dec_sub24_is_32b[0:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:19071.1-19392.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_SHIFT_ROT.dec.SHIFT_ROT_dec31.SHIFT_ROT_dec31_dec_sub26" +attribute \generator "nMigen" +module \SHIFT_ROT_dec31_dec_sub26 + attribute \src "libresoc.v:19295.3-19310.6" + wire width 3 $0\SHIFT_ROT_dec31_dec_sub26_cr_in[2:0] + attribute \src "libresoc.v:19311.3-19326.6" + wire width 3 $0\SHIFT_ROT_dec31_dec_sub26_cr_out[2:0] + attribute \src "libresoc.v:19343.3-19358.6" + wire width 2 $0\SHIFT_ROT_dec31_dec_sub26_cry_in[1:0] + attribute \src "libresoc.v:19359.3-19374.6" + wire $0\SHIFT_ROT_dec31_dec_sub26_cry_out[0:0] + attribute \src "libresoc.v:19231.3-19246.6" + wire width 12 $0\SHIFT_ROT_dec31_dec_sub26_function_unit[11:0] + attribute \src "libresoc.v:19279.3-19294.6" + wire width 4 $0\SHIFT_ROT_dec31_dec_sub26_in2_sel[3:0] + attribute \src "libresoc.v:19263.3-19278.6" + wire width 7 $0\SHIFT_ROT_dec31_dec_sub26_internal_op[6:0] + attribute \src "libresoc.v:19375.3-19390.6" + wire $0\SHIFT_ROT_dec31_dec_sub26_is_32b[0:0] + attribute \src "libresoc.v:19327.3-19342.6" + wire width 2 $0\SHIFT_ROT_dec31_dec_sub26_rc_sel[1:0] + attribute \src "libresoc.v:19247.3-19262.6" + wire $0\SHIFT_ROT_dec31_dec_sub26_sgn[0:0] + attribute \src "libresoc.v:19072.7-19072.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:19295.3-19310.6" + wire width 3 $1\SHIFT_ROT_dec31_dec_sub26_cr_in[2:0] + attribute \src "libresoc.v:19311.3-19326.6" + wire width 3 $1\SHIFT_ROT_dec31_dec_sub26_cr_out[2:0] + attribute \src "libresoc.v:19343.3-19358.6" + wire width 2 $1\SHIFT_ROT_dec31_dec_sub26_cry_in[1:0] + attribute \src "libresoc.v:19359.3-19374.6" + wire $1\SHIFT_ROT_dec31_dec_sub26_cry_out[0:0] + attribute \src "libresoc.v:19231.3-19246.6" + wire width 12 $1\SHIFT_ROT_dec31_dec_sub26_function_unit[11:0] + attribute \src "libresoc.v:19279.3-19294.6" + wire width 4 $1\SHIFT_ROT_dec31_dec_sub26_in2_sel[3:0] + attribute \src "libresoc.v:19263.3-19278.6" + wire width 7 $1\SHIFT_ROT_dec31_dec_sub26_internal_op[6:0] + attribute \src "libresoc.v:19375.3-19390.6" + wire $1\SHIFT_ROT_dec31_dec_sub26_is_32b[0:0] + attribute \src "libresoc.v:19327.3-19342.6" + wire width 2 $1\SHIFT_ROT_dec31_dec_sub26_rc_sel[1:0] + attribute \src "libresoc.v:19247.3-19262.6" + wire $1\SHIFT_ROT_dec31_dec_sub26_sgn[0:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 4 \SHIFT_ROT_dec31_dec_sub26_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \SHIFT_ROT_dec31_dec_sub26_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 7 \SHIFT_ROT_dec31_dec_sub26_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 8 \SHIFT_ROT_dec31_dec_sub26_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \SHIFT_ROT_dec31_dec_sub26_function_unit + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 3 \SHIFT_ROT_dec31_dec_sub26_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \SHIFT_ROT_dec31_dec_sub26_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 9 \SHIFT_ROT_dec31_dec_sub26_is_32b + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 6 \SHIFT_ROT_dec31_dec_sub26_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 10 \SHIFT_ROT_dec31_dec_sub26_sgn + attribute \src "libresoc.v:19072.7-19072.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 11 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 5 \opcode_switch + attribute \src "libresoc.v:19072.7-19072.20" + process $proc$libresoc.v:19072$409 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:19231.3-19246.6" + process $proc$libresoc.v:19231$399 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub26_function_unit[11:0] $1\SHIFT_ROT_dec31_dec_sub26_function_unit[11:0] + attribute \src "libresoc.v:19232.5-19232.29" + switch \initial + attribute \src "libresoc.v:19232.9-19232.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_function_unit[11:0] 12'000000001000 + case + assign $1\SHIFT_ROT_dec31_dec_sub26_function_unit[11:0] 12'000000000000 + end + sync always + update \SHIFT_ROT_dec31_dec_sub26_function_unit $0\SHIFT_ROT_dec31_dec_sub26_function_unit[11:0] + end + attribute \src "libresoc.v:19247.3-19262.6" + process $proc$libresoc.v:19247$400 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub26_sgn[0:0] $1\SHIFT_ROT_dec31_dec_sub26_sgn[0:0] + attribute \src "libresoc.v:19248.5-19248.29" + switch \initial + attribute \src "libresoc.v:19248.9-19248.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_sgn[0:0] 1'1 + case + assign $1\SHIFT_ROT_dec31_dec_sub26_sgn[0:0] 1'0 + end + sync always + update \SHIFT_ROT_dec31_dec_sub26_sgn $0\SHIFT_ROT_dec31_dec_sub26_sgn[0:0] + end + attribute \src "libresoc.v:19263.3-19278.6" + process $proc$libresoc.v:19263$401 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub26_internal_op[6:0] $1\SHIFT_ROT_dec31_dec_sub26_internal_op[6:0] + attribute \src "libresoc.v:19264.5-19264.29" + switch \initial + attribute \src "libresoc.v:19264.9-19264.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_internal_op[6:0] 7'0100000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_internal_op[6:0] 7'0111101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_internal_op[6:0] 7'0111101 + case + assign $1\SHIFT_ROT_dec31_dec_sub26_internal_op[6:0] 7'0000000 + end + sync always + update \SHIFT_ROT_dec31_dec_sub26_internal_op $0\SHIFT_ROT_dec31_dec_sub26_internal_op[6:0] + end + attribute \src "libresoc.v:19279.3-19294.6" + process $proc$libresoc.v:19279$402 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub26_in2_sel[3:0] $1\SHIFT_ROT_dec31_dec_sub26_in2_sel[3:0] + attribute \src "libresoc.v:19280.5-19280.29" + switch \initial + attribute \src "libresoc.v:19280.9-19280.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_in2_sel[3:0] 4'1010 + case + assign $1\SHIFT_ROT_dec31_dec_sub26_in2_sel[3:0] 4'0000 + end + sync always + update \SHIFT_ROT_dec31_dec_sub26_in2_sel $0\SHIFT_ROT_dec31_dec_sub26_in2_sel[3:0] + end + attribute \src "libresoc.v:19295.3-19310.6" + process $proc$libresoc.v:19295$403 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub26_cr_in[2:0] $1\SHIFT_ROT_dec31_dec_sub26_cr_in[2:0] + attribute \src "libresoc.v:19296.5-19296.29" + switch \initial + attribute \src "libresoc.v:19296.9-19296.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_cr_in[2:0] 3'000 + case + assign $1\SHIFT_ROT_dec31_dec_sub26_cr_in[2:0] 3'000 + end + sync always + update \SHIFT_ROT_dec31_dec_sub26_cr_in $0\SHIFT_ROT_dec31_dec_sub26_cr_in[2:0] + end + attribute \src "libresoc.v:19311.3-19326.6" + process $proc$libresoc.v:19311$404 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub26_cr_out[2:0] $1\SHIFT_ROT_dec31_dec_sub26_cr_out[2:0] + attribute \src "libresoc.v:19312.5-19312.29" + switch \initial + attribute \src "libresoc.v:19312.9-19312.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_cr_out[2:0] 3'001 + case + assign $1\SHIFT_ROT_dec31_dec_sub26_cr_out[2:0] 3'000 + end + sync always + update \SHIFT_ROT_dec31_dec_sub26_cr_out $0\SHIFT_ROT_dec31_dec_sub26_cr_out[2:0] + end + attribute \src "libresoc.v:19327.3-19342.6" + process $proc$libresoc.v:19327$405 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub26_rc_sel[1:0] $1\SHIFT_ROT_dec31_dec_sub26_rc_sel[1:0] + attribute \src "libresoc.v:19328.5-19328.29" + switch \initial + attribute \src "libresoc.v:19328.9-19328.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_rc_sel[1:0] 2'10 + case + assign $1\SHIFT_ROT_dec31_dec_sub26_rc_sel[1:0] 2'00 + end + sync always + update \SHIFT_ROT_dec31_dec_sub26_rc_sel $0\SHIFT_ROT_dec31_dec_sub26_rc_sel[1:0] + end + attribute \src "libresoc.v:19343.3-19358.6" + process $proc$libresoc.v:19343$406 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub26_cry_in[1:0] $1\SHIFT_ROT_dec31_dec_sub26_cry_in[1:0] + attribute \src "libresoc.v:19344.5-19344.29" + switch \initial + attribute \src "libresoc.v:19344.9-19344.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_cry_in[1:0] 2'00 + case + assign $1\SHIFT_ROT_dec31_dec_sub26_cry_in[1:0] 2'00 + end + sync always + update \SHIFT_ROT_dec31_dec_sub26_cry_in $0\SHIFT_ROT_dec31_dec_sub26_cry_in[1:0] + end + attribute \src "libresoc.v:19359.3-19374.6" + process $proc$libresoc.v:19359$407 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub26_cry_out[0:0] $1\SHIFT_ROT_dec31_dec_sub26_cry_out[0:0] + attribute \src "libresoc.v:19360.5-19360.29" + switch \initial + attribute \src "libresoc.v:19360.9-19360.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_cry_out[0:0] 1'1 + case + assign $1\SHIFT_ROT_dec31_dec_sub26_cry_out[0:0] 1'0 + end + sync always + update \SHIFT_ROT_dec31_dec_sub26_cry_out $0\SHIFT_ROT_dec31_dec_sub26_cry_out[0:0] + end + attribute \src "libresoc.v:19375.3-19390.6" + process $proc$libresoc.v:19375$408 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub26_is_32b[0:0] $1\SHIFT_ROT_dec31_dec_sub26_is_32b[0:0] + attribute \src "libresoc.v:19376.5-19376.29" + switch \initial + attribute \src "libresoc.v:19376.9-19376.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_is_32b[0:0] 1'0 + case + assign $1\SHIFT_ROT_dec31_dec_sub26_is_32b[0:0] 1'0 + end + sync always + update \SHIFT_ROT_dec31_dec_sub26_is_32b $0\SHIFT_ROT_dec31_dec_sub26_is_32b[0:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:19396.1-19747.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_SHIFT_ROT.dec.SHIFT_ROT_dec31.SHIFT_ROT_dec31_dec_sub27" +attribute \generator "nMigen" +module \SHIFT_ROT_dec31_dec_sub27 + attribute \src "libresoc.v:19632.3-19650.6" + wire width 3 $0\SHIFT_ROT_dec31_dec_sub27_cr_in[2:0] + attribute \src "libresoc.v:19651.3-19669.6" + wire width 3 $0\SHIFT_ROT_dec31_dec_sub27_cr_out[2:0] + attribute \src "libresoc.v:19689.3-19707.6" + wire width 2 $0\SHIFT_ROT_dec31_dec_sub27_cry_in[1:0] + attribute \src "libresoc.v:19708.3-19726.6" + wire $0\SHIFT_ROT_dec31_dec_sub27_cry_out[0:0] + attribute \src "libresoc.v:19556.3-19574.6" + wire width 12 $0\SHIFT_ROT_dec31_dec_sub27_function_unit[11:0] + attribute \src "libresoc.v:19613.3-19631.6" + wire width 4 $0\SHIFT_ROT_dec31_dec_sub27_in2_sel[3:0] + attribute \src "libresoc.v:19594.3-19612.6" + wire width 7 $0\SHIFT_ROT_dec31_dec_sub27_internal_op[6:0] + attribute \src "libresoc.v:19727.3-19745.6" + wire $0\SHIFT_ROT_dec31_dec_sub27_is_32b[0:0] + attribute \src "libresoc.v:19670.3-19688.6" + wire width 2 $0\SHIFT_ROT_dec31_dec_sub27_rc_sel[1:0] + attribute \src "libresoc.v:19575.3-19593.6" + wire $0\SHIFT_ROT_dec31_dec_sub27_sgn[0:0] + attribute \src "libresoc.v:19397.7-19397.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:19632.3-19650.6" + wire width 3 $1\SHIFT_ROT_dec31_dec_sub27_cr_in[2:0] + attribute \src "libresoc.v:19651.3-19669.6" + wire width 3 $1\SHIFT_ROT_dec31_dec_sub27_cr_out[2:0] + attribute \src "libresoc.v:19689.3-19707.6" + wire width 2 $1\SHIFT_ROT_dec31_dec_sub27_cry_in[1:0] + attribute \src "libresoc.v:19708.3-19726.6" + wire $1\SHIFT_ROT_dec31_dec_sub27_cry_out[0:0] + attribute \src "libresoc.v:19556.3-19574.6" + wire width 12 $1\SHIFT_ROT_dec31_dec_sub27_function_unit[11:0] + attribute \src "libresoc.v:19613.3-19631.6" + wire width 4 $1\SHIFT_ROT_dec31_dec_sub27_in2_sel[3:0] + attribute \src "libresoc.v:19594.3-19612.6" + wire width 7 $1\SHIFT_ROT_dec31_dec_sub27_internal_op[6:0] + attribute \src "libresoc.v:19727.3-19745.6" + wire $1\SHIFT_ROT_dec31_dec_sub27_is_32b[0:0] + attribute \src "libresoc.v:19670.3-19688.6" + wire width 2 $1\SHIFT_ROT_dec31_dec_sub27_rc_sel[1:0] + attribute \src "libresoc.v:19575.3-19593.6" + wire $1\SHIFT_ROT_dec31_dec_sub27_sgn[0:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 4 \SHIFT_ROT_dec31_dec_sub27_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \SHIFT_ROT_dec31_dec_sub27_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 7 \SHIFT_ROT_dec31_dec_sub27_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 8 \SHIFT_ROT_dec31_dec_sub27_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \SHIFT_ROT_dec31_dec_sub27_function_unit + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 3 \SHIFT_ROT_dec31_dec_sub27_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \SHIFT_ROT_dec31_dec_sub27_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 9 \SHIFT_ROT_dec31_dec_sub27_is_32b + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 6 \SHIFT_ROT_dec31_dec_sub27_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 10 \SHIFT_ROT_dec31_dec_sub27_sgn + attribute \src "libresoc.v:19397.7-19397.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 11 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 5 \opcode_switch + attribute \src "libresoc.v:19397.7-19397.20" + process $proc$libresoc.v:19397$420 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:19556.3-19574.6" + process $proc$libresoc.v:19556$410 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub27_function_unit[11:0] $1\SHIFT_ROT_dec31_dec_sub27_function_unit[11:0] + attribute \src "libresoc.v:19557.5-19557.29" + switch \initial + attribute \src "libresoc.v:19557.9-19557.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_function_unit[11:0] 12'000000001000 + case + assign $1\SHIFT_ROT_dec31_dec_sub27_function_unit[11:0] 12'000000000000 + end + sync always + update \SHIFT_ROT_dec31_dec_sub27_function_unit $0\SHIFT_ROT_dec31_dec_sub27_function_unit[11:0] + end + attribute \src "libresoc.v:19575.3-19593.6" + process $proc$libresoc.v:19575$411 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub27_sgn[0:0] $1\SHIFT_ROT_dec31_dec_sub27_sgn[0:0] + attribute \src "libresoc.v:19576.5-19576.29" + switch \initial + attribute \src "libresoc.v:19576.9-19576.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_sgn[0:0] 1'0 + case + assign $1\SHIFT_ROT_dec31_dec_sub27_sgn[0:0] 1'0 + end + sync always + update \SHIFT_ROT_dec31_dec_sub27_sgn $0\SHIFT_ROT_dec31_dec_sub27_sgn[0:0] + end + attribute \src "libresoc.v:19594.3-19612.6" + process $proc$libresoc.v:19594$412 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub27_internal_op[6:0] $1\SHIFT_ROT_dec31_dec_sub27_internal_op[6:0] + attribute \src "libresoc.v:19595.5-19595.29" + switch \initial + attribute \src "libresoc.v:19595.9-19595.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_internal_op[6:0] 7'0100000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_internal_op[6:0] 7'0111100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_internal_op[6:0] 7'0111101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_internal_op[6:0] 7'0111101 + case + assign $1\SHIFT_ROT_dec31_dec_sub27_internal_op[6:0] 7'0000000 + end + sync always + update \SHIFT_ROT_dec31_dec_sub27_internal_op $0\SHIFT_ROT_dec31_dec_sub27_internal_op[6:0] + end + attribute \src "libresoc.v:19613.3-19631.6" + process $proc$libresoc.v:19613$413 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub27_in2_sel[3:0] $1\SHIFT_ROT_dec31_dec_sub27_in2_sel[3:0] + attribute \src "libresoc.v:19614.5-19614.29" + switch \initial + attribute \src "libresoc.v:19614.9-19614.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_in2_sel[3:0] 4'0001 + case + assign $1\SHIFT_ROT_dec31_dec_sub27_in2_sel[3:0] 4'0000 + end + sync always + update \SHIFT_ROT_dec31_dec_sub27_in2_sel $0\SHIFT_ROT_dec31_dec_sub27_in2_sel[3:0] + end + attribute \src "libresoc.v:19632.3-19650.6" + process $proc$libresoc.v:19632$414 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub27_cr_in[2:0] $1\SHIFT_ROT_dec31_dec_sub27_cr_in[2:0] + attribute \src "libresoc.v:19633.5-19633.29" + switch \initial + attribute \src "libresoc.v:19633.9-19633.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_cr_in[2:0] 3'000 + case + assign $1\SHIFT_ROT_dec31_dec_sub27_cr_in[2:0] 3'000 + end + sync always + update \SHIFT_ROT_dec31_dec_sub27_cr_in $0\SHIFT_ROT_dec31_dec_sub27_cr_in[2:0] + end + attribute \src "libresoc.v:19651.3-19669.6" + process $proc$libresoc.v:19651$415 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub27_cr_out[2:0] $1\SHIFT_ROT_dec31_dec_sub27_cr_out[2:0] + attribute \src "libresoc.v:19652.5-19652.29" + switch \initial + attribute \src "libresoc.v:19652.9-19652.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_cr_out[2:0] 3'001 + case + assign $1\SHIFT_ROT_dec31_dec_sub27_cr_out[2:0] 3'000 + end + sync always + update \SHIFT_ROT_dec31_dec_sub27_cr_out $0\SHIFT_ROT_dec31_dec_sub27_cr_out[2:0] + end + attribute \src "libresoc.v:19670.3-19688.6" + process $proc$libresoc.v:19670$416 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub27_rc_sel[1:0] $1\SHIFT_ROT_dec31_dec_sub27_rc_sel[1:0] + attribute \src "libresoc.v:19671.5-19671.29" + switch \initial + attribute \src "libresoc.v:19671.9-19671.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_rc_sel[1:0] 2'10 + case + assign $1\SHIFT_ROT_dec31_dec_sub27_rc_sel[1:0] 2'00 + end + sync always + update \SHIFT_ROT_dec31_dec_sub27_rc_sel $0\SHIFT_ROT_dec31_dec_sub27_rc_sel[1:0] + end + attribute \src "libresoc.v:19689.3-19707.6" + process $proc$libresoc.v:19689$417 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub27_cry_in[1:0] $1\SHIFT_ROT_dec31_dec_sub27_cry_in[1:0] + attribute \src "libresoc.v:19690.5-19690.29" + switch \initial + attribute \src "libresoc.v:19690.9-19690.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_cry_in[1:0] 2'00 + case + assign $1\SHIFT_ROT_dec31_dec_sub27_cry_in[1:0] 2'00 + end + sync always + update \SHIFT_ROT_dec31_dec_sub27_cry_in $0\SHIFT_ROT_dec31_dec_sub27_cry_in[1:0] + end + attribute \src "libresoc.v:19708.3-19726.6" + process $proc$libresoc.v:19708$418 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub27_cry_out[0:0] $1\SHIFT_ROT_dec31_dec_sub27_cry_out[0:0] + attribute \src "libresoc.v:19709.5-19709.29" + switch \initial + attribute \src "libresoc.v:19709.9-19709.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_cry_out[0:0] 1'0 + case + assign $1\SHIFT_ROT_dec31_dec_sub27_cry_out[0:0] 1'0 + end + sync always + update \SHIFT_ROT_dec31_dec_sub27_cry_out $0\SHIFT_ROT_dec31_dec_sub27_cry_out[0:0] + end + attribute \src "libresoc.v:19727.3-19745.6" + process $proc$libresoc.v:19727$419 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub27_is_32b[0:0] $1\SHIFT_ROT_dec31_dec_sub27_is_32b[0:0] + attribute \src "libresoc.v:19728.5-19728.29" + switch \initial + attribute \src "libresoc.v:19728.9-19728.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_is_32b[0:0] 1'0 + case + assign $1\SHIFT_ROT_dec31_dec_sub27_is_32b[0:0] 1'0 + end + sync always + update \SHIFT_ROT_dec31_dec_sub27_is_32b $0\SHIFT_ROT_dec31_dec_sub27_is_32b[0:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:19751.1-20073.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_SPR.dec.SPR_dec31" +attribute \generator "nMigen" +module \SPR_dec31 + attribute \src "libresoc.v:20030.3-20039.6" + wire width 3 $0\SPR_dec31_cr_in[2:0] + attribute \src "libresoc.v:20040.3-20049.6" + wire width 3 $0\SPR_dec31_cr_out[2:0] + attribute \src "libresoc.v:20010.3-20019.6" + wire width 12 $0\SPR_dec31_function_unit[11:0] + attribute \src "libresoc.v:20020.3-20029.6" + wire width 7 $0\SPR_dec31_internal_op[6:0] + attribute \src "libresoc.v:20060.3-20069.6" + wire $0\SPR_dec31_is_32b[0:0] + attribute \src "libresoc.v:20050.3-20059.6" + wire width 2 $0\SPR_dec31_rc_sel[1:0] + attribute \src "libresoc.v:19752.7-19752.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:20030.3-20039.6" + wire width 3 $1\SPR_dec31_cr_in[2:0] + attribute \src "libresoc.v:20040.3-20049.6" + wire width 3 $1\SPR_dec31_cr_out[2:0] + attribute \src "libresoc.v:20010.3-20019.6" + wire width 12 $1\SPR_dec31_function_unit[11:0] + attribute \src "libresoc.v:20020.3-20029.6" + wire width 7 $1\SPR_dec31_internal_op[6:0] + attribute \src "libresoc.v:20060.3-20069.6" + wire $1\SPR_dec31_is_32b[0:0] + attribute \src "libresoc.v:20050.3-20059.6" + wire width 2 $1\SPR_dec31_rc_sel[1:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 3 \SPR_dec31_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 4 \SPR_dec31_cr_out + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_is_32b + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \SPR_dec31_dec_sub19_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \SPR_dec31_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \SPR_dec31_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 6 \SPR_dec31_is_32b + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 5 \SPR_dec31_rc_sel + attribute \src "libresoc.v:19752.7-19752.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:326" + wire width 5 \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 7 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 10 \opcode_switch + attribute \module_not_derived 1 + attribute \src "libresoc.v:20001.23-20009.4" + cell \SPR_dec31_dec_sub19 \SPR_dec31_dec_sub19 + connect \SPR_dec31_dec_sub19_cr_in \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_cr_in + connect \SPR_dec31_dec_sub19_cr_out \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_cr_out + connect \SPR_dec31_dec_sub19_function_unit \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_function_unit + connect \SPR_dec31_dec_sub19_internal_op \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_internal_op + connect \SPR_dec31_dec_sub19_is_32b \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_is_32b + connect \SPR_dec31_dec_sub19_rc_sel \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_rc_sel + connect \opcode_in \SPR_dec31_dec_sub19_opcode_in + end + attribute \src "libresoc.v:19752.7-19752.20" + process $proc$libresoc.v:19752$427 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:20010.3-20019.6" + process $proc$libresoc.v:20010$421 + assign { } { } + assign { } { } + assign $0\SPR_dec31_function_unit[11:0] $1\SPR_dec31_function_unit[11:0] + attribute \src "libresoc.v:20011.5-20011.29" + switch \initial + attribute \src "libresoc.v:20011.9-20011.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\SPR_dec31_function_unit[11:0] \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_function_unit + case + assign $1\SPR_dec31_function_unit[11:0] 12'000000000000 + end + sync always + update \SPR_dec31_function_unit $0\SPR_dec31_function_unit[11:0] + end + attribute \src "libresoc.v:20020.3-20029.6" + process $proc$libresoc.v:20020$422 + assign { } { } + assign { } { } + assign $0\SPR_dec31_internal_op[6:0] $1\SPR_dec31_internal_op[6:0] + attribute \src "libresoc.v:20021.5-20021.29" + switch \initial + attribute \src "libresoc.v:20021.9-20021.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\SPR_dec31_internal_op[6:0] \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_internal_op + case + assign $1\SPR_dec31_internal_op[6:0] 7'0000000 + end + sync always + update \SPR_dec31_internal_op $0\SPR_dec31_internal_op[6:0] + end + attribute \src "libresoc.v:20030.3-20039.6" + process $proc$libresoc.v:20030$423 + assign { } { } + assign { } { } + assign $0\SPR_dec31_cr_in[2:0] $1\SPR_dec31_cr_in[2:0] + attribute \src "libresoc.v:20031.5-20031.29" + switch \initial + attribute \src "libresoc.v:20031.9-20031.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\SPR_dec31_cr_in[2:0] \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_cr_in + case + assign $1\SPR_dec31_cr_in[2:0] 3'000 + end + sync always + update \SPR_dec31_cr_in $0\SPR_dec31_cr_in[2:0] + end + attribute \src "libresoc.v:20040.3-20049.6" + process $proc$libresoc.v:20040$424 + assign { } { } + assign { } { } + assign $0\SPR_dec31_cr_out[2:0] $1\SPR_dec31_cr_out[2:0] + attribute \src "libresoc.v:20041.5-20041.29" + switch \initial + attribute \src "libresoc.v:20041.9-20041.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\SPR_dec31_cr_out[2:0] \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_cr_out + case + assign $1\SPR_dec31_cr_out[2:0] 3'000 + end + sync always + update \SPR_dec31_cr_out $0\SPR_dec31_cr_out[2:0] + end + attribute \src "libresoc.v:20050.3-20059.6" + process $proc$libresoc.v:20050$425 + assign { } { } + assign { } { } + assign $0\SPR_dec31_rc_sel[1:0] $1\SPR_dec31_rc_sel[1:0] + attribute \src "libresoc.v:20051.5-20051.29" + switch \initial + attribute \src "libresoc.v:20051.9-20051.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\SPR_dec31_rc_sel[1:0] \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_rc_sel + case + assign $1\SPR_dec31_rc_sel[1:0] 2'00 + end + sync always + update \SPR_dec31_rc_sel $0\SPR_dec31_rc_sel[1:0] + end + attribute \src "libresoc.v:20060.3-20069.6" + process $proc$libresoc.v:20060$426 + assign { } { } + assign { } { } + assign $0\SPR_dec31_is_32b[0:0] $1\SPR_dec31_is_32b[0:0] + attribute \src "libresoc.v:20061.5-20061.29" + switch \initial + attribute \src "libresoc.v:20061.9-20061.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\SPR_dec31_is_32b[0:0] \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_is_32b + case + assign $1\SPR_dec31_is_32b[0:0] 1'0 + end + sync always + update \SPR_dec31_is_32b $0\SPR_dec31_is_32b[0:0] + end + connect \SPR_dec31_dec_sub19_opcode_in \opcode_in + connect \opc_in \opcode_switch [4:0] + connect \opcode_switch \opcode_in [10:1] +end +attribute \src "libresoc.v:20077.1-20285.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_SPR.dec.SPR_dec31.SPR_dec31_dec_sub19" +attribute \generator "nMigen" +module \SPR_dec31_dec_sub19 + attribute \src "libresoc.v:20232.3-20244.6" + wire width 3 $0\SPR_dec31_dec_sub19_cr_in[2:0] + attribute \src "libresoc.v:20245.3-20257.6" + wire width 3 $0\SPR_dec31_dec_sub19_cr_out[2:0] + attribute \src "libresoc.v:20206.3-20218.6" + wire width 12 $0\SPR_dec31_dec_sub19_function_unit[11:0] + attribute \src "libresoc.v:20219.3-20231.6" + wire width 7 $0\SPR_dec31_dec_sub19_internal_op[6:0] + attribute \src "libresoc.v:20271.3-20283.6" + wire $0\SPR_dec31_dec_sub19_is_32b[0:0] + attribute \src "libresoc.v:20258.3-20270.6" + wire width 2 $0\SPR_dec31_dec_sub19_rc_sel[1:0] + attribute \src "libresoc.v:20078.7-20078.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:20232.3-20244.6" + wire width 3 $1\SPR_dec31_dec_sub19_cr_in[2:0] + attribute \src "libresoc.v:20245.3-20257.6" + wire width 3 $1\SPR_dec31_dec_sub19_cr_out[2:0] + attribute \src "libresoc.v:20206.3-20218.6" + wire width 12 $1\SPR_dec31_dec_sub19_function_unit[11:0] + attribute \src "libresoc.v:20219.3-20231.6" + wire width 7 $1\SPR_dec31_dec_sub19_internal_op[6:0] + attribute \src "libresoc.v:20271.3-20283.6" + wire $1\SPR_dec31_dec_sub19_is_32b[0:0] + attribute \src "libresoc.v:20258.3-20270.6" + wire width 2 $1\SPR_dec31_dec_sub19_rc_sel[1:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 3 \SPR_dec31_dec_sub19_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 4 \SPR_dec31_dec_sub19_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \SPR_dec31_dec_sub19_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \SPR_dec31_dec_sub19_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 6 \SPR_dec31_dec_sub19_is_32b + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 5 \SPR_dec31_dec_sub19_rc_sel + attribute \src "libresoc.v:20078.7-20078.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 7 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 5 \opcode_switch + attribute \src "libresoc.v:20078.7-20078.20" + process $proc$libresoc.v:20078$434 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:20206.3-20218.6" + process $proc$libresoc.v:20206$428 + assign { } { } + assign { } { } + assign $0\SPR_dec31_dec_sub19_function_unit[11:0] $1\SPR_dec31_dec_sub19_function_unit[11:0] + attribute \src "libresoc.v:20207.5-20207.29" + switch \initial + attribute \src "libresoc.v:20207.9-20207.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\SPR_dec31_dec_sub19_function_unit[11:0] 12'010000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\SPR_dec31_dec_sub19_function_unit[11:0] 12'010000000000 + case + assign $1\SPR_dec31_dec_sub19_function_unit[11:0] 12'000000000000 + end + sync always + update \SPR_dec31_dec_sub19_function_unit $0\SPR_dec31_dec_sub19_function_unit[11:0] + end + attribute \src "libresoc.v:20219.3-20231.6" + process $proc$libresoc.v:20219$429 + assign { } { } + assign { } { } + assign $0\SPR_dec31_dec_sub19_internal_op[6:0] $1\SPR_dec31_dec_sub19_internal_op[6:0] + attribute \src "libresoc.v:20220.5-20220.29" + switch \initial + attribute \src "libresoc.v:20220.9-20220.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\SPR_dec31_dec_sub19_internal_op[6:0] 7'0101110 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\SPR_dec31_dec_sub19_internal_op[6:0] 7'0110001 + case + assign $1\SPR_dec31_dec_sub19_internal_op[6:0] 7'0000000 + end + sync always + update \SPR_dec31_dec_sub19_internal_op $0\SPR_dec31_dec_sub19_internal_op[6:0] + end + attribute \src "libresoc.v:20232.3-20244.6" + process $proc$libresoc.v:20232$430 + assign { } { } + assign { } { } + assign $0\SPR_dec31_dec_sub19_cr_in[2:0] $1\SPR_dec31_dec_sub19_cr_in[2:0] + attribute \src "libresoc.v:20233.5-20233.29" + switch \initial + attribute \src "libresoc.v:20233.9-20233.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\SPR_dec31_dec_sub19_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\SPR_dec31_dec_sub19_cr_in[2:0] 3'000 + case + assign $1\SPR_dec31_dec_sub19_cr_in[2:0] 3'000 + end + sync always + update \SPR_dec31_dec_sub19_cr_in $0\SPR_dec31_dec_sub19_cr_in[2:0] + end + attribute \src "libresoc.v:20245.3-20257.6" + process $proc$libresoc.v:20245$431 + assign { } { } + assign { } { } + assign $0\SPR_dec31_dec_sub19_cr_out[2:0] $1\SPR_dec31_dec_sub19_cr_out[2:0] + attribute \src "libresoc.v:20246.5-20246.29" + switch \initial + attribute \src "libresoc.v:20246.9-20246.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\SPR_dec31_dec_sub19_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\SPR_dec31_dec_sub19_cr_out[2:0] 3'000 + case + assign $1\SPR_dec31_dec_sub19_cr_out[2:0] 3'000 + end + sync always + update \SPR_dec31_dec_sub19_cr_out $0\SPR_dec31_dec_sub19_cr_out[2:0] + end + attribute \src "libresoc.v:20258.3-20270.6" + process $proc$libresoc.v:20258$432 + assign { } { } + assign { } { } + assign $0\SPR_dec31_dec_sub19_rc_sel[1:0] $1\SPR_dec31_dec_sub19_rc_sel[1:0] + attribute \src "libresoc.v:20259.5-20259.29" + switch \initial + attribute \src "libresoc.v:20259.9-20259.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\SPR_dec31_dec_sub19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\SPR_dec31_dec_sub19_rc_sel[1:0] 2'00 + case + assign $1\SPR_dec31_dec_sub19_rc_sel[1:0] 2'00 + end + sync always + update \SPR_dec31_dec_sub19_rc_sel $0\SPR_dec31_dec_sub19_rc_sel[1:0] + end + attribute \src "libresoc.v:20271.3-20283.6" + process $proc$libresoc.v:20271$433 + assign { } { } + assign { } { } + assign $0\SPR_dec31_dec_sub19_is_32b[0:0] $1\SPR_dec31_dec_sub19_is_32b[0:0] + attribute \src "libresoc.v:20272.5-20272.29" + switch \initial + attribute \src "libresoc.v:20272.9-20272.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\SPR_dec31_dec_sub19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\SPR_dec31_dec_sub19_is_32b[0:0] 1'0 + case + assign $1\SPR_dec31_dec_sub19_is_32b[0:0] 1'0 + end + sync always + update \SPR_dec31_dec_sub19_is_32b $0\SPR_dec31_dec_sub19_is_32b[0:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:20289.1-20561.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.jtag._fsm" +attribute \generator "nMigen" +module \_fsm + attribute \src "libresoc.v:20409.3-20523.6" + wire width 4 $0\fsm_state$next[3:0]$459 + attribute \src "libresoc.v:20375.3-20376.35" + wire width 4 $0\fsm_state[3:0] + attribute \src "libresoc.v:20290.7-20290.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:20381.3-20408.6" + wire $0\isdr$next[0:0]$455 + attribute \src "libresoc.v:20377.3-20378.25" + wire $0\isdr[0:0] + attribute \src "libresoc.v:20524.3-20551.6" + wire $0\isir$next[0:0]$472 + attribute \src "libresoc.v:20379.3-20380.25" + wire $0\isir[0:0] + attribute \src "libresoc.v:20409.3-20523.6" + wire width 4 $10\fsm_state$next[3:0]$469 + attribute \src "libresoc.v:20409.3-20523.6" + wire width 4 $11\fsm_state$next[3:0]$470 + attribute \src "libresoc.v:20409.3-20523.6" + wire width 4 $1\fsm_state$next[3:0]$460 + attribute \src "libresoc.v:20330.13-20330.29" + wire width 4 $1\fsm_state[3:0] + attribute \src "libresoc.v:20381.3-20408.6" + wire $1\isdr$next[0:0]$456 + attribute \src "libresoc.v:20335.7-20335.18" + wire $1\isdr[0:0] + attribute \src "libresoc.v:20524.3-20551.6" + wire $1\isir$next[0:0]$473 + attribute \src "libresoc.v:20340.7-20340.18" + wire $1\isir[0:0] + attribute \src "libresoc.v:20409.3-20523.6" + wire width 4 $2\fsm_state$next[3:0]$461 + attribute \src "libresoc.v:20381.3-20408.6" + wire $2\isdr$next[0:0]$457 + attribute \src "libresoc.v:20524.3-20551.6" + wire $2\isir$next[0:0]$474 + attribute \src "libresoc.v:20409.3-20523.6" + wire width 4 $3\fsm_state$next[3:0]$462 + attribute \src "libresoc.v:20409.3-20523.6" + wire width 4 $4\fsm_state$next[3:0]$463 + attribute \src "libresoc.v:20409.3-20523.6" + wire width 4 $5\fsm_state$next[3:0]$464 + attribute \src "libresoc.v:20409.3-20523.6" + wire width 4 $6\fsm_state$next[3:0]$465 + attribute \src "libresoc.v:20409.3-20523.6" + wire width 4 $7\fsm_state$next[3:0]$466 + attribute \src "libresoc.v:20409.3-20523.6" + wire width 4 $8\fsm_state$next[3:0]$467 + attribute \src "libresoc.v:20409.3-20523.6" + wire width 4 $9\fsm_state$next[3:0]$468 + attribute \src "libresoc.v:20359.17-20359.110" + wire $eq$libresoc.v:20359$435_Y + attribute \src "libresoc.v:20360.18-20360.111" + wire $eq$libresoc.v:20360$436_Y + attribute \src "libresoc.v:20361.18-20361.111" + wire $eq$libresoc.v:20361$437_Y + attribute \src "libresoc.v:20362.18-20362.111" + wire $eq$libresoc.v:20362$438_Y + attribute \src "libresoc.v:20363.18-20363.111" + wire $eq$libresoc.v:20363$439_Y + attribute \src "libresoc.v:20364.17-20364.108" + wire $eq$libresoc.v:20364$440_Y + attribute \src "libresoc.v:20365.18-20365.111" + wire $eq$libresoc.v:20365$441_Y + attribute \src "libresoc.v:20366.18-20366.111" + wire $eq$libresoc.v:20366$442_Y + attribute \src "libresoc.v:20367.18-20367.111" + wire $eq$libresoc.v:20367$443_Y + attribute \src "libresoc.v:20368.18-20368.111" + wire $eq$libresoc.v:20368$444_Y + attribute \src "libresoc.v:20369.18-20369.111" + wire $eq$libresoc.v:20369$445_Y + attribute \src "libresoc.v:20370.18-20370.111" + wire $eq$libresoc.v:20370$446_Y + attribute \src "libresoc.v:20371.18-20371.112" + wire $eq$libresoc.v:20371$447_Y + attribute \src "libresoc.v:20372.17-20372.108" + wire $eq$libresoc.v:20372$448_Y + attribute \src "libresoc.v:20373.17-20373.108" + wire $eq$libresoc.v:20373$449_Y + attribute \src "libresoc.v:20374.17-20374.108" + wire $eq$libresoc.v:20374$450_Y + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:114" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:71" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:60" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:68" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:71" + wire \$17 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:77" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:83" + wire \$21 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:88" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:91" + wire \$25 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:96" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:99" + wire \$29 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:115" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:108" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:116" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:117" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:77" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:39" + wire input 9 \TAP_bus__tck + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:39" + wire input 10 \TAP_bus__tms + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:25" + wire output 11 \capture + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:53" + wire width 4 \fsm_state + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:53" + wire width 4 \fsm_state$next + attribute \src "libresoc.v:20290.7-20290.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:24" + wire output 1 \isdr + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:24" + wire \isdr$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:23" + wire output 4 \isir + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:23" + wire \isir$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:50" + wire \local_clk + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:30" + wire output 8 \negjtag_clk + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:30" + wire output 6 \negjtag_rst + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:29" + wire output 7 \posjtag_clk + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:29" + wire output 5 \posjtag_rst + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:37" + wire \rst + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:26" + wire output 2 \shift + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:27" + wire output 3 \update + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:77" + cell $eq $eq$libresoc.v:20359$435 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \TAP_bus__tms + connect \B 1'0 + connect \Y $eq$libresoc.v:20359$435_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:71" + cell $eq $eq$libresoc.v:20360$436 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \TAP_bus__tms + connect \B 1'0 + connect \Y $eq$libresoc.v:20360$436_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:60" + cell $eq $eq$libresoc.v:20361$437 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \TAP_bus__tms + connect \B 1'0 + connect \Y $eq$libresoc.v:20361$437_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:68" + cell $eq $eq$libresoc.v:20362$438 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \TAP_bus__tms + connect \B 1'1 + connect \Y $eq$libresoc.v:20362$438_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:71" + cell $eq $eq$libresoc.v:20363$439 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \TAP_bus__tms + connect \B 1'0 + connect \Y $eq$libresoc.v:20363$439_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:114" + cell $eq $eq$libresoc.v:20364$440 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fsm_state + connect \B 1'0 + connect \Y $eq$libresoc.v:20364$440_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:77" + cell $eq $eq$libresoc.v:20365$441 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \TAP_bus__tms + connect \B 1'0 + connect \Y $eq$libresoc.v:20365$441_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:83" + cell $eq $eq$libresoc.v:20366$442 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \TAP_bus__tms + connect \B 1'0 + connect \Y $eq$libresoc.v:20366$442_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:88" + cell $eq $eq$libresoc.v:20367$443 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \TAP_bus__tms + connect \B 1'1 + connect \Y $eq$libresoc.v:20367$443_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:91" + cell $eq $eq$libresoc.v:20368$444 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \TAP_bus__tms + connect \B 1'0 + connect \Y $eq$libresoc.v:20368$444_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:96" + cell $eq $eq$libresoc.v:20369$445 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \TAP_bus__tms + connect \B 1'1 + connect \Y $eq$libresoc.v:20369$445_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:99" + cell $eq $eq$libresoc.v:20370$446 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \TAP_bus__tms + connect \B 1'0 + connect \Y $eq$libresoc.v:20370$446_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:108" + cell $eq $eq$libresoc.v:20371$447 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \TAP_bus__tms + connect \B 1'0 + connect \Y $eq$libresoc.v:20371$447_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:115" + cell $eq $eq$libresoc.v:20372$448 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \fsm_state + connect \B 2'11 + connect \Y $eq$libresoc.v:20372$448_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:116" + cell $eq $eq$libresoc.v:20373$449 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \fsm_state + connect \B 3'101 + connect \Y $eq$libresoc.v:20373$449_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:117" + cell $eq $eq$libresoc.v:20374$450 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \fsm_state + connect \B 4'1000 + connect \Y $eq$libresoc.v:20374$450_Y + end + attribute \src "libresoc.v:20290.7-20290.20" + process $proc$libresoc.v:20290$475 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:20330.13-20330.29" + process $proc$libresoc.v:20330$476 + assign { } { } + assign $1\fsm_state[3:0] 4'0000 + sync always + sync init + update \fsm_state $1\fsm_state[3:0] + end + attribute \src "libresoc.v:20335.7-20335.18" + process $proc$libresoc.v:20335$477 + assign { } { } + assign $1\isdr[0:0] 1'0 + sync always + sync init + update \isdr $1\isdr[0:0] + end + attribute \src "libresoc.v:20340.7-20340.18" + process $proc$libresoc.v:20340$478 + assign { } { } + assign $1\isir[0:0] 1'0 + sync always + sync init + update \isir $1\isir[0:0] + end + attribute \src "libresoc.v:20375.3-20376.35" + process $proc$libresoc.v:20375$451 + assign { } { } + assign $0\fsm_state[3:0] \fsm_state$next + sync posedge \local_clk + update \fsm_state $0\fsm_state[3:0] + end + attribute \src "libresoc.v:20377.3-20378.25" + process $proc$libresoc.v:20377$452 + assign { } { } + assign $0\isdr[0:0] \isdr$next + sync posedge \local_clk + update \isdr $0\isdr[0:0] + end + attribute \src "libresoc.v:20379.3-20380.25" + process $proc$libresoc.v:20379$453 + assign { } { } + assign $0\isir[0:0] \isir$next + sync posedge \local_clk + update \isir $0\isir[0:0] + end + attribute \src "libresoc.v:20381.3-20408.6" + process $proc$libresoc.v:20381$454 + assign { } { } + assign { } { } + assign $0\isdr$next[0:0]$455 $1\isdr$next[0:0]$456 + attribute \src "libresoc.v:20382.5-20382.29" + switch \initial + attribute \src "libresoc.v:20382.9-20382.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:53" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\isdr$next[0:0]$456 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\isdr$next[0:0]$456 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\isdr$next[0:0]$456 $2\isdr$next[0:0]$457 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:71" + switch \$11 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\isdr$next[0:0]$457 1'1 + case + assign $2\isdr$next[0:0]$457 \isdr + end + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\isdr$next[0:0]$456 1'0 + case + assign $1\isdr$next[0:0]$456 \isdr + end + sync always + update \isdr$next $0\isdr$next[0:0]$455 + end + attribute \src "libresoc.v:20409.3-20523.6" + process $proc$libresoc.v:20409$458 + assign { } { } + assign { } { } + assign $0\fsm_state$next[3:0]$459 $1\fsm_state$next[3:0]$460 + attribute \src "libresoc.v:20410.5-20410.29" + switch \initial + attribute \src "libresoc.v:20410.9-20410.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:53" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\fsm_state$next[3:0]$460 $2\fsm_state$next[3:0]$461 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:60" + switch \$13 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\fsm_state$next[3:0]$461 4'0001 + case + assign $2\fsm_state$next[3:0]$461 \fsm_state + end + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\fsm_state$next[3:0]$460 $3\fsm_state$next[3:0]$462 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:68" + switch \$15 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fsm_state$next[3:0]$462 4'0010 + case + assign $3\fsm_state$next[3:0]$462 \fsm_state + end + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\fsm_state$next[3:0]$460 $4\fsm_state$next[3:0]$463 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:71" + switch \$17 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\fsm_state$next[3:0]$463 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $4\fsm_state$next[3:0]$463 4'0100 + end + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\fsm_state$next[3:0]$460 $5\fsm_state$next[3:0]$464 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:77" + switch \$19 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\fsm_state$next[3:0]$464 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $5\fsm_state$next[3:0]$464 4'0000 + end + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\fsm_state$next[3:0]$460 $6\fsm_state$next[3:0]$465 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:83" + switch \$21 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\fsm_state$next[3:0]$465 4'0101 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $6\fsm_state$next[3:0]$465 4'0110 + end + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\fsm_state$next[3:0]$460 $7\fsm_state$next[3:0]$466 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:88" + switch \$23 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\fsm_state$next[3:0]$466 4'0110 + case + assign $7\fsm_state$next[3:0]$466 \fsm_state + end + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\fsm_state$next[3:0]$460 $8\fsm_state$next[3:0]$467 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:91" + switch \$25 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $8\fsm_state$next[3:0]$467 4'0111 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $8\fsm_state$next[3:0]$467 4'1000 + end + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\fsm_state$next[3:0]$460 $9\fsm_state$next[3:0]$468 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:96" + switch \$27 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $9\fsm_state$next[3:0]$468 4'1001 + case + assign $9\fsm_state$next[3:0]$468 \fsm_state + end + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\fsm_state$next[3:0]$460 $10\fsm_state$next[3:0]$469 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:99" + switch \$29 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $10\fsm_state$next[3:0]$469 4'0101 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $10\fsm_state$next[3:0]$469 4'1000 + end + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\fsm_state$next[3:0]$460 $11\fsm_state$next[3:0]$470 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:108" + switch \$31 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $11\fsm_state$next[3:0]$470 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $11\fsm_state$next[3:0]$470 4'0010 + end + case + assign $1\fsm_state$next[3:0]$460 \fsm_state + end + sync always + update \fsm_state$next $0\fsm_state$next[3:0]$459 + end + attribute \src "libresoc.v:20524.3-20551.6" + process $proc$libresoc.v:20524$471 + assign { } { } + assign { } { } + assign $0\isir$next[0:0]$472 $1\isir$next[0:0]$473 + attribute \src "libresoc.v:20525.5-20525.29" + switch \initial + attribute \src "libresoc.v:20525.9-20525.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:53" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\isir$next[0:0]$473 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\isir$next[0:0]$473 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\isir$next[0:0]$473 $2\isir$next[0:0]$474 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:77" + switch \$9 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\isir$next[0:0]$474 1'1 + case + assign $2\isir$next[0:0]$474 \isir + end + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\isir$next[0:0]$473 1'0 + case + assign $1\isir$next[0:0]$473 \isir + end + sync always + update \isir$next $0\isir$next[0:0]$472 + end + connect \$9 $eq$libresoc.v:20359$435_Y + connect \$11 $eq$libresoc.v:20360$436_Y + connect \$13 $eq$libresoc.v:20361$437_Y + connect \$15 $eq$libresoc.v:20362$438_Y + connect \$17 $eq$libresoc.v:20363$439_Y + connect \$1 $eq$libresoc.v:20364$440_Y + connect \$19 $eq$libresoc.v:20365$441_Y + connect \$21 $eq$libresoc.v:20366$442_Y + connect \$23 $eq$libresoc.v:20367$443_Y + connect \$25 $eq$libresoc.v:20368$444_Y + connect \$27 $eq$libresoc.v:20369$445_Y + connect \$29 $eq$libresoc.v:20370$446_Y + connect \$31 $eq$libresoc.v:20371$447_Y + connect \$3 $eq$libresoc.v:20372$448_Y + connect \$5 $eq$libresoc.v:20373$449_Y + connect \$7 $eq$libresoc.v:20374$450_Y + connect \update \$7 + connect \shift \$5 + connect \capture \$3 + connect \rst \$1 + connect \local_clk \TAP_bus__tck + connect \negjtag_rst \rst + connect \negjtag_clk \TAP_bus__tck + connect \posjtag_rst \rst + connect \posjtag_clk \TAP_bus__tck +end +attribute \src "libresoc.v:20565.1-20676.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.jtag._idblock" +attribute \generator "nMigen" +module \_idblock + attribute \src "libresoc.v:20649.3-20669.6" + wire width 32 $0\TAP_id_sr$next[31:0]$497 + attribute \src "libresoc.v:20647.3-20648.35" + wire width 32 $0\TAP_id_sr[31:0] + attribute \src "libresoc.v:20566.7-20566.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:20649.3-20669.6" + wire width 32 $1\TAP_id_sr$next[31:0]$498 + attribute \src "libresoc.v:20602.14-20602.31" + wire width 32 $1\TAP_id_sr[31:0] + attribute \src "libresoc.v:20649.3-20669.6" + wire width 32 $2\TAP_id_sr$next[31:0]$499 + attribute \src "libresoc.v:20631.17-20631.105" + wire $and$libresoc.v:20631$479_Y + attribute \src "libresoc.v:20635.18-20635.103" + wire $and$libresoc.v:20635$483_Y + attribute \src "libresoc.v:20637.18-20637.105" + wire $and$libresoc.v:20637$485_Y + attribute \src "libresoc.v:20641.18-20641.103" + wire $and$libresoc.v:20641$489_Y + attribute \src "libresoc.v:20642.18-20642.106" + wire $and$libresoc.v:20642$490_Y + attribute \src "libresoc.v:20646.17-20646.101" + wire $and$libresoc.v:20646$494_Y + attribute \src "libresoc.v:20632.18-20632.102" + wire $eq$libresoc.v:20632$480_Y + attribute \src "libresoc.v:20633.18-20633.102" + wire $eq$libresoc.v:20633$481_Y + attribute \src "libresoc.v:20636.17-20636.101" + wire $eq$libresoc.v:20636$484_Y + attribute \src "libresoc.v:20638.18-20638.102" + wire $eq$libresoc.v:20638$486_Y + attribute \src "libresoc.v:20639.18-20639.102" + wire $eq$libresoc.v:20639$487_Y + attribute \src "libresoc.v:20643.18-20643.102" + wire $eq$libresoc.v:20643$491_Y + attribute \src "libresoc.v:20644.17-20644.101" + wire $eq$libresoc.v:20644$492_Y + attribute \src "libresoc.v:20634.18-20634.104" + wire $or$libresoc.v:20634$482_Y + attribute \src "libresoc.v:20640.18-20640.104" + wire $or$libresoc.v:20640$488_Y + attribute \src "libresoc.v:20645.17-20645.101" + wire $or$libresoc.v:20645$493_Y + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" + wire \$17 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:367" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" + wire \$21 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" + wire \$25 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:368" + wire \$29 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:369" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:366" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:39" + wire input 5 \TAP_bus__tdi + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:226" + wire width 32 \TAP_id_sr + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:226" + wire width 32 \TAP_id_sr$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:215" + wire output 6 \TAP_id_tdo + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:233" + wire \_bypass + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:230" + wire \_capture + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:231" + wire \_shift + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:229" + wire \_tdi + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:232" + wire \_update + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:25" + wire input 1 \capture + attribute \src "libresoc.v:20566.7-20566.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:128" + wire width 4 input 9 \ir + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:24" + wire input 2 \isdr + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:29" + wire input 8 \posjtag_clk + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:29" + wire input 7 \posjtag_rst + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:26" + wire input 3 \shift + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:27" + wire input 4 \update + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:366" + cell $and $and$libresoc.v:20631$479 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$7 + connect \B \capture + connect \Y $and$libresoc.v:20631$479_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" + cell $and $and$libresoc.v:20635$483 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \isdr + connect \B \$15 + connect \Y $and$libresoc.v:20635$483_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:367" + cell $and $and$libresoc.v:20637$485 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$17 + connect \B \shift + connect \Y $and$libresoc.v:20637$485_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" + cell $and $and$libresoc.v:20641$489 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \isdr + connect \B \$25 + connect \Y $and$libresoc.v:20641$489_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:368" + cell $and $and$libresoc.v:20642$490 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$27 + connect \B \update + connect \Y $and$libresoc.v:20642$490_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" + cell $and $and$libresoc.v:20646$494 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \isdr + connect \B \$5 + connect \Y $and$libresoc.v:20646$494_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" + cell $eq $eq$libresoc.v:20632$480 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ir + connect \B 1'1 + connect \Y $eq$libresoc.v:20632$480_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" + cell $eq $eq$libresoc.v:20633$481 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \ir + connect \B 4'1111 + connect \Y $eq$libresoc.v:20633$481_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" + cell $eq $eq$libresoc.v:20636$484 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ir + connect \B 1'1 + connect \Y $eq$libresoc.v:20636$484_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" + cell $eq $eq$libresoc.v:20638$486 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ir + connect \B 1'1 + connect \Y $eq$libresoc.v:20638$486_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" + cell $eq $eq$libresoc.v:20639$487 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \ir + connect \B 4'1111 + connect \Y $eq$libresoc.v:20639$487_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:369" + cell $eq $eq$libresoc.v:20643$491 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \ir + connect \B 4'1111 + connect \Y $eq$libresoc.v:20643$491_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" + cell $eq $eq$libresoc.v:20644$492 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \ir + connect \B 4'1111 + connect \Y $eq$libresoc.v:20644$492_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" + cell $or $or$libresoc.v:20634$482 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$11 + connect \B \$13 + connect \Y $or$libresoc.v:20634$482_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" + cell $or $or$libresoc.v:20640$488 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$21 + connect \B \$23 + connect \Y $or$libresoc.v:20640$488_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" + cell $or $or$libresoc.v:20645$493 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$1 + connect \B \$3 + connect \Y $or$libresoc.v:20645$493_Y + end + attribute \src "libresoc.v:20566.7-20566.20" + process $proc$libresoc.v:20566$500 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:20602.14-20602.31" + process $proc$libresoc.v:20602$501 + assign { } { } + assign $1\TAP_id_sr[31:0] 0 + sync always + sync init + update \TAP_id_sr $1\TAP_id_sr[31:0] + end + attribute \src "libresoc.v:20647.3-20648.35" + process $proc$libresoc.v:20647$495 + assign { } { } + assign $0\TAP_id_sr[31:0] \TAP_id_sr$next + sync posedge \posjtag_clk + update \TAP_id_sr $0\TAP_id_sr[31:0] + end + attribute \src "libresoc.v:20649.3-20669.6" + process $proc$libresoc.v:20649$496 + assign { } { } + assign { } { } + assign $0\TAP_id_sr$next[31:0]$497 $1\TAP_id_sr$next[31:0]$498 + attribute \src "libresoc.v:20650.5-20650.29" + switch \initial + attribute \src "libresoc.v:20650.9-20650.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:244" + switch { \_shift \_capture } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\TAP_id_sr$next[31:0]$498 6399 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\TAP_id_sr$next[31:0]$498 $2\TAP_id_sr$next[31:0]$499 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:247" + switch \_bypass + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $2\TAP_id_sr$next[31:0]$499 [31:1] \TAP_id_sr [31:1] + assign $2\TAP_id_sr$next[31:0]$499 [0] \_tdi + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\TAP_id_sr$next[31:0]$499 { \_tdi \TAP_id_sr [31:1] } + end + case + assign $1\TAP_id_sr$next[31:0]$498 \TAP_id_sr + end + sync always + update \TAP_id_sr$next $0\TAP_id_sr$next[31:0]$497 + end + connect \$9 $and$libresoc.v:20631$479_Y + connect \$11 $eq$libresoc.v:20632$480_Y + connect \$13 $eq$libresoc.v:20633$481_Y + connect \$15 $or$libresoc.v:20634$482_Y + connect \$17 $and$libresoc.v:20635$483_Y + connect \$1 $eq$libresoc.v:20636$484_Y + connect \$19 $and$libresoc.v:20637$485_Y + connect \$21 $eq$libresoc.v:20638$486_Y + connect \$23 $eq$libresoc.v:20639$487_Y + connect \$25 $or$libresoc.v:20640$488_Y + connect \$27 $and$libresoc.v:20641$489_Y + connect \$29 $and$libresoc.v:20642$490_Y + connect \$31 $eq$libresoc.v:20643$491_Y + connect \$3 $eq$libresoc.v:20644$492_Y + connect \$5 $or$libresoc.v:20645$493_Y + connect \$7 $and$libresoc.v:20646$494_Y + connect \TAP_id_tdo \TAP_id_sr [0] + connect \_bypass \$31 + connect \_update \$29 + connect \_shift \$19 + connect \_capture \$9 + connect \_tdi \TAP_bus__tdi +end +attribute \src "libresoc.v:20680.1-20764.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.jtag._irblock" +attribute \generator "nMigen" +module \_irblock + attribute \src "libresoc.v:20681.7-20681.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:20742.3-20762.6" + wire width 4 $0\ir$next[3:0]$514 + attribute \src "libresoc.v:20725.3-20726.21" + wire width 4 $0\ir[3:0] + attribute \src "libresoc.v:20729.3-20741.6" + wire width 4 $0\shift_ir$next[3:0]$511 + attribute \src "libresoc.v:20727.3-20728.33" + wire width 4 $0\shift_ir[3:0] + attribute \src "libresoc.v:20742.3-20762.6" + wire width 4 $1\ir$next[3:0]$515 + attribute \src "libresoc.v:20700.13-20700.22" + wire width 4 $1\ir[3:0] + attribute \src "libresoc.v:20729.3-20741.6" + wire width 4 $1\shift_ir$next[3:0]$512 + attribute \src "libresoc.v:20712.13-20712.28" + wire width 4 $1\shift_ir[3:0] + attribute \src "libresoc.v:20742.3-20762.6" + wire width 4 $2\ir$next[3:0]$516 + attribute \src "libresoc.v:20719.17-20719.103" + wire $and$libresoc.v:20719$502_Y + attribute \src "libresoc.v:20720.18-20720.105" + wire $and$libresoc.v:20720$503_Y + attribute \src "libresoc.v:20721.17-20721.105" + wire $and$libresoc.v:20721$504_Y + attribute \src "libresoc.v:20722.17-20722.103" + wire $and$libresoc.v:20722$505_Y + attribute \src "libresoc.v:20723.17-20723.104" + wire $and$libresoc.v:20723$506_Y + attribute \src "libresoc.v:20724.17-20724.105" + wire $and$libresoc.v:20724$507_Y + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:355" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:357" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:356" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:357" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:355" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:356" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:39" + wire input 4 \TAP_bus__tdi + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:25" + wire input 1 \capture + attribute \src "libresoc.v:20681.7-20681.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:128" + wire width 4 output 9 \ir + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:128" + wire width 4 \ir$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:23" + wire input 5 \isir + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:29" + wire input 8 \posjtag_clk + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:29" + wire input 7 \posjtag_rst + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:26" + wire input 2 \shift + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:139" + wire width 4 \shift_ir + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:139" + wire width 4 \shift_ir$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:129" + wire output 6 \tdo + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:27" + wire input 3 \update + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:356" + cell $and $and$libresoc.v:20719$502 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \isir + connect \B \shift + connect \Y $and$libresoc.v:20719$502_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:357" + cell $and $and$libresoc.v:20720$503 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \isir + connect \B \update + connect \Y $and$libresoc.v:20720$503_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:355" + cell $and $and$libresoc.v:20721$504 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \isir + connect \B \capture + connect \Y $and$libresoc.v:20721$504_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:356" + cell $and $and$libresoc.v:20722$505 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \isir + connect \B \shift + connect \Y $and$libresoc.v:20722$505_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:357" + cell $and $and$libresoc.v:20723$506 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \isir + connect \B \update + connect \Y $and$libresoc.v:20723$506_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:355" + cell $and $and$libresoc.v:20724$507 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \isir + connect \B \capture + connect \Y $and$libresoc.v:20724$507_Y + end + attribute \src "libresoc.v:20681.7-20681.20" + process $proc$libresoc.v:20681$517 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:20700.13-20700.22" + process $proc$libresoc.v:20700$518 + assign { } { } + assign $1\ir[3:0] 4'0001 + sync always + sync init + update \ir $1\ir[3:0] + end + attribute \src "libresoc.v:20712.13-20712.28" + process $proc$libresoc.v:20712$519 + assign { } { } + assign $1\shift_ir[3:0] 4'0000 + sync always + sync init + update \shift_ir $1\shift_ir[3:0] + end + attribute \src "libresoc.v:20725.3-20726.21" + process $proc$libresoc.v:20725$508 + assign { } { } + assign $0\ir[3:0] \ir$next + sync posedge \posjtag_clk + update \ir $0\ir[3:0] + end + attribute \src "libresoc.v:20727.3-20728.33" + process $proc$libresoc.v:20727$509 + assign { } { } + assign $0\shift_ir[3:0] \shift_ir$next + sync posedge \posjtag_clk + update \shift_ir $0\shift_ir[3:0] + end + attribute \src "libresoc.v:20729.3-20741.6" + process $proc$libresoc.v:20729$510 + assign { } { } + assign { } { } + assign $0\shift_ir$next[3:0]$511 $1\shift_ir$next[3:0]$512 + attribute \src "libresoc.v:20730.5-20730.29" + switch \initial + attribute \src "libresoc.v:20730.9-20730.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:142" + switch { \$5 \$3 \$1 } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign { } { } + assign $1\shift_ir$next[3:0]$512 \ir + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- + assign { } { } + assign $1\shift_ir$next[3:0]$512 { \TAP_bus__tdi \shift_ir [3:1] } + case + assign $1\shift_ir$next[3:0]$512 \shift_ir + end + sync always + update \shift_ir$next $0\shift_ir$next[3:0]$511 + end + attribute \src "libresoc.v:20742.3-20762.6" + process $proc$libresoc.v:20742$513 + assign { } { } + assign { } { } + assign { } { } + assign $0\ir$next[3:0]$514 $2\ir$next[3:0]$516 + attribute \src "libresoc.v:20743.5-20743.29" + switch \initial + attribute \src "libresoc.v:20743.9-20743.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:142" + switch { \$11 \$9 \$7 } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign $1\ir$next[3:0]$515 \ir + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- + assign $1\ir$next[3:0]$515 \ir + attribute \src "libresoc.v:0.0-0.0" + case 3'1-- + assign { } { } + assign $1\ir$next[3:0]$515 \shift_ir + case + assign $1\ir$next[3:0]$515 \ir + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \posjtag_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ir$next[3:0]$516 4'0001 + case + assign $2\ir$next[3:0]$516 $1\ir$next[3:0]$515 + end + sync always + update \ir$next $0\ir$next[3:0]$514 + end + connect \$9 $and$libresoc.v:20719$502_Y + connect \$11 $and$libresoc.v:20720$503_Y + connect \$1 $and$libresoc.v:20721$504_Y + connect \$3 $and$libresoc.v:20722$505_Y + connect \$5 $and$libresoc.v:20723$506_Y + connect \$7 $and$libresoc.v:20724$507_Y + connect \tdo \ir [0] +end +attribute \src "libresoc.v:20768.1-20826.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.adr_l" +attribute \generator "nMigen" +module \adr_l + attribute \src "libresoc.v:20769.7-20769.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:20814.3-20822.6" + wire $0\q_int$next[0:0]$530 + attribute \src "libresoc.v:20812.3-20813.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:20814.3-20822.6" + wire $1\q_int$next[0:0]$531 + attribute \src "libresoc.v:20793.7-20793.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:20804.17-20804.96" + wire $and$libresoc.v:20804$520_Y + attribute \src "libresoc.v:20809.17-20809.96" + wire $and$libresoc.v:20809$525_Y + attribute \src "libresoc.v:20806.18-20806.93" + wire $not$libresoc.v:20806$522_Y + attribute \src "libresoc.v:20808.17-20808.92" + wire $not$libresoc.v:20808$524_Y + attribute \src "libresoc.v:20811.17-20811.92" + wire $not$libresoc.v:20811$527_Y + attribute \src "libresoc.v:20805.18-20805.98" + wire $or$libresoc.v:20805$521_Y + attribute \src "libresoc.v:20807.18-20807.99" + wire $or$libresoc.v:20807$523_Y + attribute \src "libresoc.v:20810.17-20810.97" + wire $or$libresoc.v:20810$526_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 1 \coresync_rst + attribute \src "libresoc.v:20769.7-20769.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 4 \q_adr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_adr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_adr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_adr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 2 \s_adr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$libresoc.v:20804$520 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:20804$520_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:20809$525 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:20809$525_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:20806$522 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_adr + connect \Y $not$libresoc.v:20806$522_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:20808$524 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_adr + connect \Y $not$libresoc.v:20808$524_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:20811$527 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_adr + connect \Y $not$libresoc.v:20811$527_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:20805$521 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_adr + connect \Y $or$libresoc.v:20805$521_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:20807$523 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_adr + connect \B \q_int + connect \Y $or$libresoc.v:20807$523_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:20810$526 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_adr + connect \Y $or$libresoc.v:20810$526_Y + end + attribute \src "libresoc.v:20769.7-20769.20" + process $proc$libresoc.v:20769$532 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:20793.7-20793.19" + process $proc$libresoc.v:20793$533 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:20812.3-20813.27" + process $proc$libresoc.v:20812$528 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:20814.3-20822.6" + process $proc$libresoc.v:20814$529 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$530 $1\q_int$next[0:0]$531 + attribute \src "libresoc.v:20815.5-20815.29" + switch \initial + attribute \src "libresoc.v:20815.9-20815.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$531 1'0 + case + assign $1\q_int$next[0:0]$531 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$530 + end + connect \$9 $and$libresoc.v:20804$520_Y + connect \$11 $or$libresoc.v:20805$521_Y + connect \$13 $not$libresoc.v:20806$522_Y + connect \$15 $or$libresoc.v:20807$523_Y + connect \$1 $not$libresoc.v:20808$524_Y + connect \$3 $and$libresoc.v:20809$525_Y + connect \$5 $or$libresoc.v:20810$526_Y + connect \$7 $not$libresoc.v:20811$527_Y + connect \qlq_adr \$15 + connect \qn_adr \$13 + connect \q_adr \$11 +end +attribute \src "libresoc.v:20830.1-20888.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.l0.pimem.adrok_l" +attribute \generator "nMigen" +module \adrok_l + attribute \src "libresoc.v:20831.7-20831.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:20876.3-20884.6" + wire $0\q_int$next[0:0]$544 + attribute \src "libresoc.v:20874.3-20875.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:20876.3-20884.6" + wire $1\q_int$next[0:0]$545 + attribute \src "libresoc.v:20855.7-20855.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:20866.17-20866.96" + wire $and$libresoc.v:20866$534_Y + attribute \src "libresoc.v:20871.17-20871.96" + wire $and$libresoc.v:20871$539_Y + attribute \src "libresoc.v:20868.18-20868.100" + wire $not$libresoc.v:20868$536_Y + attribute \src "libresoc.v:20870.17-20870.99" + wire $not$libresoc.v:20870$538_Y + attribute \src "libresoc.v:20873.17-20873.99" + wire $not$libresoc.v:20873$541_Y + attribute \src "libresoc.v:20867.18-20867.105" + wire $or$libresoc.v:20867$535_Y + attribute \src "libresoc.v:20869.18-20869.106" + wire $or$libresoc.v:20869$537_Y + attribute \src "libresoc.v:20872.17-20872.104" + wire $or$libresoc.v:20872$540_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 6 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 1 \coresync_rst + attribute \src "libresoc.v:20831.7-20831.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 5 \q_addr_acked + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_addr_acked + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire output 4 \qn_addr_acked + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_addr_acked + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 2 \s_addr_acked + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$libresoc.v:20866$534 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:20866$534_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:20871$539 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:20871$539_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:20868$536 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_addr_acked + connect \Y $not$libresoc.v:20868$536_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:20870$538 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_addr_acked + connect \Y $not$libresoc.v:20870$538_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:20873$541 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_addr_acked + connect \Y $not$libresoc.v:20873$541_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:20867$535 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_addr_acked + connect \Y $or$libresoc.v:20867$535_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:20869$537 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_addr_acked + connect \B \q_int + connect \Y $or$libresoc.v:20869$537_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:20872$540 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_addr_acked + connect \Y $or$libresoc.v:20872$540_Y + end + attribute \src "libresoc.v:20831.7-20831.20" + process $proc$libresoc.v:20831$546 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:20855.7-20855.19" + process $proc$libresoc.v:20855$547 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:20874.3-20875.27" + process $proc$libresoc.v:20874$542 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:20876.3-20884.6" + process $proc$libresoc.v:20876$543 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$544 $1\q_int$next[0:0]$545 + attribute \src "libresoc.v:20877.5-20877.29" + switch \initial + attribute \src "libresoc.v:20877.9-20877.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$545 1'0 + case + assign $1\q_int$next[0:0]$545 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$544 + end + connect \$9 $and$libresoc.v:20866$534_Y + connect \$11 $or$libresoc.v:20867$535_Y + connect \$13 $not$libresoc.v:20868$536_Y + connect \$15 $or$libresoc.v:20869$537_Y + connect \$1 $not$libresoc.v:20870$538_Y + connect \$3 $and$libresoc.v:20871$539_Y + connect \$5 $or$libresoc.v:20872$540_Y + connect \$7 $not$libresoc.v:20873$541_Y + connect \qlq_addr_acked \$15 + connect \qn_addr_acked \$13 + connect \q_addr_acked \$11 +end +attribute \src "libresoc.v:20892.1-22217.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.alu0" +attribute \generator "nMigen" +module \alu0 + attribute \src "libresoc.v:21728.3-21729.25" + wire $0\all_rd_dly[0:0] + attribute \src "libresoc.v:21918.3-21956.6" + wire width 4 $0\alu_alu0_alu_op__data_len$next[3:0]$694 + attribute \src "libresoc.v:21700.3-21701.67" + wire width 4 $0\alu_alu0_alu_op__data_len[3:0] + attribute \src "libresoc.v:21918.3-21956.6" + wire width 12 $0\alu_alu0_alu_op__fn_unit$next[11:0]$695 + attribute \src "libresoc.v:21670.3-21671.65" + wire width 12 $0\alu_alu0_alu_op__fn_unit[11:0] + attribute \src "libresoc.v:21918.3-21956.6" + wire width 64 $0\alu_alu0_alu_op__imm_data__data$next[63:0]$696 + attribute \src "libresoc.v:21672.3-21673.79" + wire width 64 $0\alu_alu0_alu_op__imm_data__data[63:0] + attribute \src "libresoc.v:21918.3-21956.6" + wire $0\alu_alu0_alu_op__imm_data__ok$next[0:0]$697 + attribute \src "libresoc.v:21674.3-21675.75" + wire $0\alu_alu0_alu_op__imm_data__ok[0:0] + attribute \src "libresoc.v:21918.3-21956.6" + wire width 2 $0\alu_alu0_alu_op__input_carry$next[1:0]$698 + attribute \src "libresoc.v:21692.3-21693.73" + wire width 2 $0\alu_alu0_alu_op__input_carry[1:0] + attribute \src "libresoc.v:21918.3-21956.6" + wire width 32 $0\alu_alu0_alu_op__insn$next[31:0]$699 + attribute \src "libresoc.v:21702.3-21703.59" + wire width 32 $0\alu_alu0_alu_op__insn[31:0] + attribute \src "libresoc.v:21918.3-21956.6" + wire width 7 $0\alu_alu0_alu_op__insn_type$next[6:0]$700 + attribute \src "libresoc.v:21668.3-21669.69" + wire width 7 $0\alu_alu0_alu_op__insn_type[6:0] + attribute \src "libresoc.v:21918.3-21956.6" + wire $0\alu_alu0_alu_op__invert_in$next[0:0]$701 + attribute \src "libresoc.v:21684.3-21685.69" + wire $0\alu_alu0_alu_op__invert_in[0:0] + attribute \src "libresoc.v:21918.3-21956.6" + wire $0\alu_alu0_alu_op__invert_out$next[0:0]$702 + attribute \src "libresoc.v:21688.3-21689.71" + wire $0\alu_alu0_alu_op__invert_out[0:0] + attribute \src "libresoc.v:21918.3-21956.6" + wire $0\alu_alu0_alu_op__is_32bit$next[0:0]$703 + attribute \src "libresoc.v:21696.3-21697.67" + wire $0\alu_alu0_alu_op__is_32bit[0:0] + attribute \src "libresoc.v:21918.3-21956.6" + wire $0\alu_alu0_alu_op__is_signed$next[0:0]$704 + attribute \src "libresoc.v:21698.3-21699.69" + wire $0\alu_alu0_alu_op__is_signed[0:0] + attribute \src "libresoc.v:21918.3-21956.6" + wire $0\alu_alu0_alu_op__oe__oe$next[0:0]$705 + attribute \src "libresoc.v:21680.3-21681.63" + wire $0\alu_alu0_alu_op__oe__oe[0:0] + attribute \src "libresoc.v:21918.3-21956.6" + wire $0\alu_alu0_alu_op__oe__ok$next[0:0]$706 + attribute \src "libresoc.v:21682.3-21683.63" + wire $0\alu_alu0_alu_op__oe__ok[0:0] + attribute \src "libresoc.v:21918.3-21956.6" + wire $0\alu_alu0_alu_op__output_carry$next[0:0]$707 + attribute \src "libresoc.v:21694.3-21695.75" + wire $0\alu_alu0_alu_op__output_carry[0:0] + attribute \src "libresoc.v:21918.3-21956.6" + wire $0\alu_alu0_alu_op__rc__ok$next[0:0]$708 + attribute \src "libresoc.v:21678.3-21679.63" + wire $0\alu_alu0_alu_op__rc__ok[0:0] + attribute \src "libresoc.v:21918.3-21956.6" + wire $0\alu_alu0_alu_op__rc__rc$next[0:0]$709 + attribute \src "libresoc.v:21676.3-21677.63" + wire $0\alu_alu0_alu_op__rc__rc[0:0] + attribute \src "libresoc.v:21918.3-21956.6" + wire $0\alu_alu0_alu_op__write_cr0$next[0:0]$710 + attribute \src "libresoc.v:21690.3-21691.69" + wire $0\alu_alu0_alu_op__write_cr0[0:0] + attribute \src "libresoc.v:21918.3-21956.6" + wire $0\alu_alu0_alu_op__zero_a$next[0:0]$711 + attribute \src "libresoc.v:21686.3-21687.63" + wire $0\alu_alu0_alu_op__zero_a[0:0] + attribute \src "libresoc.v:21726.3-21727.40" + wire $0\alu_done_dly[0:0] + attribute \src "libresoc.v:22116.3-22124.6" + wire $0\alu_l_r_alu$next[0:0]$792 + attribute \src "libresoc.v:21636.3-21637.39" + wire $0\alu_l_r_alu[0:0] + attribute \src "libresoc.v:22107.3-22115.6" + wire $0\alui_l_r_alui$next[0:0]$789 + attribute \src "libresoc.v:21638.3-21639.43" + wire $0\alui_l_r_alui[0:0] + attribute \src "libresoc.v:21957.3-21978.6" + wire width 64 $0\data_r0__o$next[63:0]$737 + attribute \src "libresoc.v:21664.3-21665.37" + wire width 64 $0\data_r0__o[63:0] + attribute \src "libresoc.v:21957.3-21978.6" + wire $0\data_r0__o_ok$next[0:0]$738 + attribute \src "libresoc.v:21666.3-21667.43" + wire $0\data_r0__o_ok[0:0] + attribute \src "libresoc.v:21979.3-22000.6" + wire width 4 $0\data_r1__cr_a$next[3:0]$745 + attribute \src "libresoc.v:21660.3-21661.43" + wire width 4 $0\data_r1__cr_a[3:0] + attribute \src "libresoc.v:21979.3-22000.6" + wire $0\data_r1__cr_a_ok$next[0:0]$746 + attribute \src "libresoc.v:21662.3-21663.49" + wire $0\data_r1__cr_a_ok[0:0] + attribute \src "libresoc.v:22001.3-22022.6" + wire width 2 $0\data_r2__xer_ca$next[1:0]$753 + attribute \src "libresoc.v:21656.3-21657.47" + wire width 2 $0\data_r2__xer_ca[1:0] + attribute \src "libresoc.v:22001.3-22022.6" + wire $0\data_r2__xer_ca_ok$next[0:0]$754 + attribute \src "libresoc.v:21658.3-21659.53" + wire $0\data_r2__xer_ca_ok[0:0] + attribute \src "libresoc.v:22023.3-22044.6" + wire width 2 $0\data_r3__xer_ov$next[1:0]$761 + attribute \src "libresoc.v:21652.3-21653.47" + wire width 2 $0\data_r3__xer_ov[1:0] + attribute \src "libresoc.v:22023.3-22044.6" + wire $0\data_r3__xer_ov_ok$next[0:0]$762 + attribute \src "libresoc.v:21654.3-21655.53" + wire $0\data_r3__xer_ov_ok[0:0] + attribute \src "libresoc.v:22045.3-22066.6" + wire $0\data_r4__xer_so$next[0:0]$769 + attribute \src "libresoc.v:21648.3-21649.47" + wire $0\data_r4__xer_so[0:0] + attribute \src "libresoc.v:22045.3-22066.6" + wire $0\data_r4__xer_so_ok$next[0:0]$770 + attribute \src "libresoc.v:21650.3-21651.53" + wire $0\data_r4__xer_so_ok[0:0] + attribute \src "libresoc.v:22125.3-22134.6" + wire width 64 $0\dest1_o[63:0] + attribute \src "libresoc.v:22135.3-22144.6" + wire width 4 $0\dest2_o[3:0] + attribute \src "libresoc.v:22145.3-22154.6" + wire width 2 $0\dest3_o[1:0] + attribute \src "libresoc.v:22155.3-22164.6" + wire width 2 $0\dest4_o[1:0] + attribute \src "libresoc.v:22165.3-22174.6" + wire $0\dest5_o[0:0] + attribute \src "libresoc.v:20893.7-20893.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:21873.3-21881.6" + wire $0\opc_l_r_opc$next[0:0]$679 + attribute \src "libresoc.v:21712.3-21713.39" + wire $0\opc_l_r_opc[0:0] + attribute \src "libresoc.v:21864.3-21872.6" + wire $0\opc_l_s_opc$next[0:0]$676 + attribute \src "libresoc.v:21714.3-21715.39" + wire $0\opc_l_s_opc[0:0] + attribute \src "libresoc.v:22175.3-22183.6" + wire width 5 $0\prev_wr_go$next[4:0]$800 + attribute \src "libresoc.v:21724.3-21725.37" + wire width 5 $0\prev_wr_go[4:0] + attribute \src "libresoc.v:21818.3-21827.6" + wire $0\req_done[0:0] + attribute \src "libresoc.v:21909.3-21917.6" + wire width 5 $0\req_l_r_req$next[4:0]$691 + attribute \src "libresoc.v:21704.3-21705.39" + wire width 5 $0\req_l_r_req[4:0] + attribute \src "libresoc.v:21900.3-21908.6" + wire width 5 $0\req_l_s_req$next[4:0]$688 + attribute \src "libresoc.v:21706.3-21707.39" + wire width 5 $0\req_l_s_req[4:0] + attribute \src "libresoc.v:21837.3-21845.6" + wire $0\rok_l_r_rdok$next[0:0]$667 + attribute \src "libresoc.v:21720.3-21721.41" + wire $0\rok_l_r_rdok[0:0] + attribute \src "libresoc.v:21828.3-21836.6" + wire $0\rok_l_s_rdok$next[0:0]$664 + attribute \src "libresoc.v:21722.3-21723.41" + wire $0\rok_l_s_rdok[0:0] + attribute \src "libresoc.v:21855.3-21863.6" + wire $0\rst_l_r_rst$next[0:0]$673 + attribute \src "libresoc.v:21716.3-21717.39" + wire $0\rst_l_r_rst[0:0] + attribute \src "libresoc.v:21846.3-21854.6" + wire $0\rst_l_s_rst$next[0:0]$670 + attribute \src "libresoc.v:21718.3-21719.39" + wire $0\rst_l_s_rst[0:0] + attribute \src "libresoc.v:21891.3-21899.6" + wire width 4 $0\src_l_r_src$next[3:0]$685 + attribute \src "libresoc.v:21708.3-21709.39" + wire width 4 $0\src_l_r_src[3:0] + attribute \src "libresoc.v:21882.3-21890.6" + wire width 4 $0\src_l_s_src$next[3:0]$682 + attribute \src "libresoc.v:21710.3-21711.39" + wire width 4 $0\src_l_s_src[3:0] + attribute \src "libresoc.v:22067.3-22076.6" + wire width 64 $0\src_r0$next[63:0]$777 + attribute \src "libresoc.v:21646.3-21647.29" + wire width 64 $0\src_r0[63:0] + attribute \src "libresoc.v:22077.3-22086.6" + wire width 64 $0\src_r1$next[63:0]$780 + attribute \src "libresoc.v:21644.3-21645.29" + wire width 64 $0\src_r1[63:0] + attribute \src "libresoc.v:22087.3-22096.6" + wire $0\src_r2$next[0:0]$783 + attribute \src "libresoc.v:21642.3-21643.29" + wire $0\src_r2[0:0] + attribute \src "libresoc.v:22097.3-22106.6" + wire width 2 $0\src_r3$next[1:0]$786 + attribute \src "libresoc.v:21640.3-21641.29" + wire width 2 $0\src_r3[1:0] + attribute \src "libresoc.v:21031.7-21031.24" + wire $1\all_rd_dly[0:0] + attribute \src "libresoc.v:21918.3-21956.6" + wire width 4 $1\alu_alu0_alu_op__data_len$next[3:0]$712 + attribute \src "libresoc.v:21039.13-21039.45" + wire width 4 $1\alu_alu0_alu_op__data_len[3:0] + attribute \src "libresoc.v:21918.3-21956.6" + wire width 12 $1\alu_alu0_alu_op__fn_unit$next[11:0]$713 + attribute \src "libresoc.v:21056.14-21056.48" + wire width 12 $1\alu_alu0_alu_op__fn_unit[11:0] + attribute \src "libresoc.v:21918.3-21956.6" + wire width 64 $1\alu_alu0_alu_op__imm_data__data$next[63:0]$714 + attribute \src "libresoc.v:21060.14-21060.68" + wire width 64 $1\alu_alu0_alu_op__imm_data__data[63:0] + attribute \src "libresoc.v:21918.3-21956.6" + wire $1\alu_alu0_alu_op__imm_data__ok$next[0:0]$715 + attribute \src "libresoc.v:21064.7-21064.43" + wire $1\alu_alu0_alu_op__imm_data__ok[0:0] + attribute \src "libresoc.v:21918.3-21956.6" + wire width 2 $1\alu_alu0_alu_op__input_carry$next[1:0]$716 + attribute \src "libresoc.v:21072.13-21072.48" + wire width 2 $1\alu_alu0_alu_op__input_carry[1:0] + attribute \src "libresoc.v:21918.3-21956.6" + wire width 32 $1\alu_alu0_alu_op__insn$next[31:0]$717 + attribute \src "libresoc.v:21076.14-21076.43" + wire width 32 $1\alu_alu0_alu_op__insn[31:0] + attribute \src "libresoc.v:21918.3-21956.6" + wire width 7 $1\alu_alu0_alu_op__insn_type$next[6:0]$718 + attribute \src "libresoc.v:21154.13-21154.47" + wire width 7 $1\alu_alu0_alu_op__insn_type[6:0] + attribute \src "libresoc.v:21918.3-21956.6" + wire $1\alu_alu0_alu_op__invert_in$next[0:0]$719 + attribute \src "libresoc.v:21158.7-21158.40" + wire $1\alu_alu0_alu_op__invert_in[0:0] + attribute \src "libresoc.v:21918.3-21956.6" + wire $1\alu_alu0_alu_op__invert_out$next[0:0]$720 + attribute \src "libresoc.v:21162.7-21162.41" + wire $1\alu_alu0_alu_op__invert_out[0:0] + attribute \src "libresoc.v:21918.3-21956.6" + wire $1\alu_alu0_alu_op__is_32bit$next[0:0]$721 + attribute \src "libresoc.v:21166.7-21166.39" + wire $1\alu_alu0_alu_op__is_32bit[0:0] + attribute \src "libresoc.v:21918.3-21956.6" + wire $1\alu_alu0_alu_op__is_signed$next[0:0]$722 + attribute \src "libresoc.v:21170.7-21170.40" + wire $1\alu_alu0_alu_op__is_signed[0:0] + attribute \src "libresoc.v:21918.3-21956.6" + wire $1\alu_alu0_alu_op__oe__oe$next[0:0]$723 + attribute \src "libresoc.v:21174.7-21174.37" + wire $1\alu_alu0_alu_op__oe__oe[0:0] + attribute \src "libresoc.v:21918.3-21956.6" + wire $1\alu_alu0_alu_op__oe__ok$next[0:0]$724 + attribute \src "libresoc.v:21178.7-21178.37" + wire $1\alu_alu0_alu_op__oe__ok[0:0] + attribute \src "libresoc.v:21918.3-21956.6" + wire $1\alu_alu0_alu_op__output_carry$next[0:0]$725 + attribute \src "libresoc.v:21182.7-21182.43" + wire $1\alu_alu0_alu_op__output_carry[0:0] + attribute \src "libresoc.v:21918.3-21956.6" + wire $1\alu_alu0_alu_op__rc__ok$next[0:0]$726 + attribute \src "libresoc.v:21186.7-21186.37" + wire $1\alu_alu0_alu_op__rc__ok[0:0] + attribute \src "libresoc.v:21918.3-21956.6" + wire $1\alu_alu0_alu_op__rc__rc$next[0:0]$727 + attribute \src "libresoc.v:21190.7-21190.37" + wire $1\alu_alu0_alu_op__rc__rc[0:0] + attribute \src "libresoc.v:21918.3-21956.6" + wire $1\alu_alu0_alu_op__write_cr0$next[0:0]$728 + attribute \src "libresoc.v:21194.7-21194.40" + wire $1\alu_alu0_alu_op__write_cr0[0:0] + attribute \src "libresoc.v:21918.3-21956.6" + wire $1\alu_alu0_alu_op__zero_a$next[0:0]$729 + attribute \src "libresoc.v:21198.7-21198.37" + wire $1\alu_alu0_alu_op__zero_a[0:0] + attribute \src "libresoc.v:21230.7-21230.26" + wire $1\alu_done_dly[0:0] + attribute \src "libresoc.v:22116.3-22124.6" + wire $1\alu_l_r_alu$next[0:0]$793 + attribute \src "libresoc.v:21238.7-21238.25" + wire $1\alu_l_r_alu[0:0] + attribute \src "libresoc.v:22107.3-22115.6" + wire $1\alui_l_r_alui$next[0:0]$790 + attribute \src "libresoc.v:21250.7-21250.27" + wire $1\alui_l_r_alui[0:0] + attribute \src "libresoc.v:21957.3-21978.6" + wire width 64 $1\data_r0__o$next[63:0]$739 + attribute \src "libresoc.v:21284.14-21284.47" + wire width 64 $1\data_r0__o[63:0] + attribute \src "libresoc.v:21957.3-21978.6" + wire $1\data_r0__o_ok$next[0:0]$740 + attribute \src "libresoc.v:21288.7-21288.27" + wire $1\data_r0__o_ok[0:0] + attribute \src "libresoc.v:21979.3-22000.6" + wire width 4 $1\data_r1__cr_a$next[3:0]$747 + attribute \src "libresoc.v:21292.13-21292.33" + wire width 4 $1\data_r1__cr_a[3:0] + attribute \src "libresoc.v:21979.3-22000.6" + wire $1\data_r1__cr_a_ok$next[0:0]$748 + attribute \src "libresoc.v:21296.7-21296.30" + wire $1\data_r1__cr_a_ok[0:0] + attribute \src "libresoc.v:22001.3-22022.6" + wire width 2 $1\data_r2__xer_ca$next[1:0]$755 + attribute \src "libresoc.v:21300.13-21300.35" + wire width 2 $1\data_r2__xer_ca[1:0] + attribute \src "libresoc.v:22001.3-22022.6" + wire $1\data_r2__xer_ca_ok$next[0:0]$756 + attribute \src "libresoc.v:21304.7-21304.32" + wire $1\data_r2__xer_ca_ok[0:0] + attribute \src "libresoc.v:22023.3-22044.6" + wire width 2 $1\data_r3__xer_ov$next[1:0]$763 + attribute \src "libresoc.v:21308.13-21308.35" + wire width 2 $1\data_r3__xer_ov[1:0] + attribute \src "libresoc.v:22023.3-22044.6" + wire $1\data_r3__xer_ov_ok$next[0:0]$764 + attribute \src "libresoc.v:21312.7-21312.32" + wire $1\data_r3__xer_ov_ok[0:0] + attribute \src "libresoc.v:22045.3-22066.6" + wire $1\data_r4__xer_so$next[0:0]$771 + attribute \src "libresoc.v:21316.7-21316.29" + wire $1\data_r4__xer_so[0:0] + attribute \src "libresoc.v:22045.3-22066.6" + wire $1\data_r4__xer_so_ok$next[0:0]$772 + attribute \src "libresoc.v:21320.7-21320.32" + wire $1\data_r4__xer_so_ok[0:0] + attribute \src "libresoc.v:22125.3-22134.6" + wire width 64 $1\dest1_o[63:0] + attribute \src "libresoc.v:22135.3-22144.6" + wire width 4 $1\dest2_o[3:0] + attribute \src "libresoc.v:22145.3-22154.6" + wire width 2 $1\dest3_o[1:0] + attribute \src "libresoc.v:22155.3-22164.6" + wire width 2 $1\dest4_o[1:0] + attribute \src "libresoc.v:22165.3-22174.6" + wire $1\dest5_o[0:0] + attribute \src "libresoc.v:21873.3-21881.6" + wire $1\opc_l_r_opc$next[0:0]$680 + attribute \src "libresoc.v:21343.7-21343.25" + wire $1\opc_l_r_opc[0:0] + attribute \src "libresoc.v:21864.3-21872.6" + wire $1\opc_l_s_opc$next[0:0]$677 + attribute \src "libresoc.v:21347.7-21347.25" + wire $1\opc_l_s_opc[0:0] + attribute \src "libresoc.v:22175.3-22183.6" + wire width 5 $1\prev_wr_go$next[4:0]$801 + attribute \src "libresoc.v:21478.13-21478.31" + wire width 5 $1\prev_wr_go[4:0] + attribute \src "libresoc.v:21818.3-21827.6" + wire $1\req_done[0:0] + attribute \src "libresoc.v:21909.3-21917.6" + wire width 5 $1\req_l_r_req$next[4:0]$692 + attribute \src "libresoc.v:21486.13-21486.32" + wire width 5 $1\req_l_r_req[4:0] + attribute \src "libresoc.v:21900.3-21908.6" + wire width 5 $1\req_l_s_req$next[4:0]$689 + attribute \src "libresoc.v:21490.13-21490.32" + wire width 5 $1\req_l_s_req[4:0] + attribute \src "libresoc.v:21837.3-21845.6" + wire $1\rok_l_r_rdok$next[0:0]$668 + attribute \src "libresoc.v:21502.7-21502.26" + wire $1\rok_l_r_rdok[0:0] + attribute \src "libresoc.v:21828.3-21836.6" + wire $1\rok_l_s_rdok$next[0:0]$665 + attribute \src "libresoc.v:21506.7-21506.26" + wire $1\rok_l_s_rdok[0:0] + attribute \src "libresoc.v:21855.3-21863.6" + wire $1\rst_l_r_rst$next[0:0]$674 + attribute \src "libresoc.v:21510.7-21510.25" + wire $1\rst_l_r_rst[0:0] + attribute \src "libresoc.v:21846.3-21854.6" + wire $1\rst_l_s_rst$next[0:0]$671 + attribute \src "libresoc.v:21514.7-21514.25" + wire $1\rst_l_s_rst[0:0] + attribute \src "libresoc.v:21891.3-21899.6" + wire width 4 $1\src_l_r_src$next[3:0]$686 + attribute \src "libresoc.v:21530.13-21530.31" + wire width 4 $1\src_l_r_src[3:0] + attribute \src "libresoc.v:21882.3-21890.6" + wire width 4 $1\src_l_s_src$next[3:0]$683 + attribute \src "libresoc.v:21534.13-21534.31" + wire width 4 $1\src_l_s_src[3:0] + attribute \src "libresoc.v:22067.3-22076.6" + wire width 64 $1\src_r0$next[63:0]$778 + attribute \src "libresoc.v:21542.14-21542.43" + wire width 64 $1\src_r0[63:0] + attribute \src "libresoc.v:22077.3-22086.6" + wire width 64 $1\src_r1$next[63:0]$781 + attribute \src "libresoc.v:21546.14-21546.43" + wire width 64 $1\src_r1[63:0] + attribute \src "libresoc.v:22087.3-22096.6" + wire $1\src_r2$next[0:0]$784 + attribute \src "libresoc.v:21550.7-21550.20" + wire $1\src_r2[0:0] + attribute \src "libresoc.v:22097.3-22106.6" + wire width 2 $1\src_r3$next[1:0]$787 + attribute \src "libresoc.v:21554.13-21554.26" + wire width 2 $1\src_r3[1:0] + attribute \src "libresoc.v:21918.3-21956.6" + wire width 64 $2\alu_alu0_alu_op__imm_data__data$next[63:0]$730 + attribute \src "libresoc.v:21918.3-21956.6" + wire $2\alu_alu0_alu_op__imm_data__ok$next[0:0]$731 + attribute \src "libresoc.v:21918.3-21956.6" + wire $2\alu_alu0_alu_op__oe__oe$next[0:0]$732 + attribute \src "libresoc.v:21918.3-21956.6" + wire $2\alu_alu0_alu_op__oe__ok$next[0:0]$733 + attribute \src "libresoc.v:21918.3-21956.6" + wire $2\alu_alu0_alu_op__rc__ok$next[0:0]$734 + attribute \src "libresoc.v:21918.3-21956.6" + wire $2\alu_alu0_alu_op__rc__rc$next[0:0]$735 + attribute \src "libresoc.v:21957.3-21978.6" + wire width 64 $2\data_r0__o$next[63:0]$741 + attribute \src "libresoc.v:21957.3-21978.6" + wire $2\data_r0__o_ok$next[0:0]$742 + attribute \src "libresoc.v:21979.3-22000.6" + wire width 4 $2\data_r1__cr_a$next[3:0]$749 + attribute \src "libresoc.v:21979.3-22000.6" + wire $2\data_r1__cr_a_ok$next[0:0]$750 + attribute \src "libresoc.v:22001.3-22022.6" + wire width 2 $2\data_r2__xer_ca$next[1:0]$757 + attribute \src "libresoc.v:22001.3-22022.6" + wire $2\data_r2__xer_ca_ok$next[0:0]$758 + attribute \src "libresoc.v:22023.3-22044.6" + wire width 2 $2\data_r3__xer_ov$next[1:0]$765 + attribute \src "libresoc.v:22023.3-22044.6" + wire $2\data_r3__xer_ov_ok$next[0:0]$766 + attribute \src "libresoc.v:22045.3-22066.6" + wire $2\data_r4__xer_so$next[0:0]$773 + attribute \src "libresoc.v:22045.3-22066.6" + wire $2\data_r4__xer_so_ok$next[0:0]$774 + attribute \src "libresoc.v:21957.3-21978.6" + wire $3\data_r0__o_ok$next[0:0]$743 + attribute \src "libresoc.v:21979.3-22000.6" + wire $3\data_r1__cr_a_ok$next[0:0]$751 + attribute \src "libresoc.v:22001.3-22022.6" + wire $3\data_r2__xer_ca_ok$next[0:0]$759 + attribute \src "libresoc.v:22023.3-22044.6" + wire $3\data_r3__xer_ov_ok$next[0:0]$767 + attribute \src "libresoc.v:22045.3-22066.6" + wire $3\data_r4__xer_so_ok$next[0:0]$775 + attribute \src "libresoc.v:21570.18-21570.134" + wire $and$libresoc.v:21570$549_Y + attribute \src "libresoc.v:21571.19-21571.133" + wire $and$libresoc.v:21571$550_Y + attribute \src "libresoc.v:21572.19-21572.161" + wire width 4 $and$libresoc.v:21572$551_Y + attribute \src "libresoc.v:21575.19-21575.134" + wire width 4 $and$libresoc.v:21575$554_Y + attribute \src "libresoc.v:21577.19-21577.115" + wire width 4 $and$libresoc.v:21577$556_Y + attribute \src "libresoc.v:21578.19-21578.125" + wire $and$libresoc.v:21578$557_Y + attribute \src "libresoc.v:21579.19-21579.125" + wire $and$libresoc.v:21579$558_Y + attribute \src "libresoc.v:21580.18-21580.110" + wire $and$libresoc.v:21580$559_Y + attribute \src "libresoc.v:21581.19-21581.125" + wire $and$libresoc.v:21581$560_Y + attribute \src "libresoc.v:21582.19-21582.125" + wire $and$libresoc.v:21582$561_Y + attribute \src "libresoc.v:21583.19-21583.125" + wire $and$libresoc.v:21583$562_Y + attribute \src "libresoc.v:21584.19-21584.157" + wire width 5 $and$libresoc.v:21584$563_Y + attribute \src "libresoc.v:21585.19-21585.121" + wire width 5 $and$libresoc.v:21585$564_Y + attribute \src "libresoc.v:21586.19-21586.127" + wire $and$libresoc.v:21586$565_Y + attribute \src "libresoc.v:21587.19-21587.127" + wire $and$libresoc.v:21587$566_Y + attribute \src "libresoc.v:21588.19-21588.127" + wire $and$libresoc.v:21588$567_Y + attribute \src "libresoc.v:21589.19-21589.127" + wire $and$libresoc.v:21589$568_Y + attribute \src "libresoc.v:21590.19-21590.127" + wire $and$libresoc.v:21590$569_Y + attribute \src "libresoc.v:21592.18-21592.98" + wire $and$libresoc.v:21592$571_Y + attribute \src "libresoc.v:21594.18-21594.100" + wire $and$libresoc.v:21594$573_Y + attribute \src "libresoc.v:21595.18-21595.171" + wire width 5 $and$libresoc.v:21595$574_Y + attribute \src "libresoc.v:21597.18-21597.119" + wire width 5 $and$libresoc.v:21597$576_Y + attribute \src "libresoc.v:21600.18-21600.116" + wire $and$libresoc.v:21600$579_Y + attribute \src "libresoc.v:21604.17-21604.123" + wire $and$libresoc.v:21604$583_Y + attribute \src "libresoc.v:21606.18-21606.113" + wire $and$libresoc.v:21606$585_Y + attribute \src "libresoc.v:21607.18-21607.125" + wire width 5 $and$libresoc.v:21607$586_Y + attribute \src "libresoc.v:21609.18-21609.112" + wire $and$libresoc.v:21609$588_Y + attribute \src "libresoc.v:21611.18-21611.126" + wire $and$libresoc.v:21611$590_Y + attribute \src "libresoc.v:21612.18-21612.126" + wire $and$libresoc.v:21612$591_Y + attribute \src "libresoc.v:21613.18-21613.117" + wire $and$libresoc.v:21613$592_Y + attribute \src "libresoc.v:21618.18-21618.130" + wire $and$libresoc.v:21618$597_Y + attribute \src "libresoc.v:21619.18-21619.124" + wire width 5 $and$libresoc.v:21619$598_Y + attribute \src "libresoc.v:21622.18-21622.116" + wire $and$libresoc.v:21622$601_Y + attribute \src "libresoc.v:21623.18-21623.119" + wire $and$libresoc.v:21623$602_Y + attribute \src "libresoc.v:21624.18-21624.121" + wire $and$libresoc.v:21624$603_Y + attribute \src "libresoc.v:21625.18-21625.121" + wire $and$libresoc.v:21625$604_Y + attribute \src "libresoc.v:21626.18-21626.121" + wire $and$libresoc.v:21626$605_Y + attribute \src "libresoc.v:21608.18-21608.113" + wire $eq$libresoc.v:21608$587_Y + attribute \src "libresoc.v:21610.18-21610.119" + wire $eq$libresoc.v:21610$589_Y + attribute \src "libresoc.v:21573.19-21573.126" + wire $not$libresoc.v:21573$552_Y + attribute \src "libresoc.v:21574.19-21574.132" + wire $not$libresoc.v:21574$553_Y + attribute \src "libresoc.v:21576.19-21576.115" + wire width 4 $not$libresoc.v:21576$555_Y + attribute \src "libresoc.v:21591.18-21591.97" + wire $not$libresoc.v:21591$570_Y + attribute \src "libresoc.v:21593.18-21593.99" + wire $not$libresoc.v:21593$572_Y + attribute \src "libresoc.v:21596.18-21596.113" + wire width 5 $not$libresoc.v:21596$575_Y + attribute \src "libresoc.v:21599.18-21599.106" + wire $not$libresoc.v:21599$578_Y + attribute \src "libresoc.v:21605.18-21605.120" + wire $not$libresoc.v:21605$584_Y + attribute \src "libresoc.v:21620.17-21620.113" + wire width 4 $not$libresoc.v:21620$599_Y + attribute \src "libresoc.v:21603.18-21603.112" + wire $or$libresoc.v:21603$582_Y + attribute \src "libresoc.v:21614.18-21614.122" + wire $or$libresoc.v:21614$593_Y + attribute \src "libresoc.v:21615.18-21615.124" + wire $or$libresoc.v:21615$594_Y + attribute \src "libresoc.v:21616.18-21616.181" + wire width 5 $or$libresoc.v:21616$595_Y + attribute \src "libresoc.v:21617.18-21617.168" + wire width 4 $or$libresoc.v:21617$596_Y + attribute \src "libresoc.v:21621.18-21621.120" + wire width 5 $or$libresoc.v:21621$600_Y + attribute \src "libresoc.v:21630.17-21630.117" + wire width 4 $or$libresoc.v:21630$609_Y + attribute \src "libresoc.v:21569.17-21569.104" + wire $reduce_and$libresoc.v:21569$548_Y + attribute \src "libresoc.v:21598.18-21598.106" + wire $reduce_or$libresoc.v:21598$577_Y + attribute \src "libresoc.v:21601.18-21601.113" + wire $reduce_or$libresoc.v:21601$580_Y + attribute \src "libresoc.v:21602.18-21602.112" + wire $reduce_or$libresoc.v:21602$581_Y + attribute \src "libresoc.v:21627.18-21627.154" + wire $ternary$libresoc.v:21627$606_Y + attribute \src "libresoc.v:21628.18-21628.155" + wire width 64 $ternary$libresoc.v:21628$607_Y + attribute \src "libresoc.v:21629.18-21629.160" + wire $ternary$libresoc.v:21629$608_Y + attribute \src "libresoc.v:21631.18-21631.172" + wire width 64 $ternary$libresoc.v:21631$610_Y + attribute \src "libresoc.v:21632.18-21632.115" + wire width 64 $ternary$libresoc.v:21632$611_Y + attribute \src "libresoc.v:21633.18-21633.125" + wire width 64 $ternary$libresoc.v:21633$612_Y + attribute \src "libresoc.v:21634.18-21634.118" + wire $ternary$libresoc.v:21634$613_Y + attribute \src "libresoc.v:21635.18-21635.118" + wire width 2 $ternary$libresoc.v:21635$614_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" + wire \$101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + wire width 4 \$103 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" + wire \$105 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" + wire \$107 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + wire width 4 \$109 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + wire width 4 \$111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + wire width 4 \$113 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + wire \$115 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + wire \$117 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + wire \$119 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + wire \$121 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + wire \$123 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" + wire width 5 \$125 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" + wire width 5 \$127 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + wire \$129 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + wire \$131 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + wire \$133 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + wire \$135 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + wire \$137 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire \$17 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" + wire width 5 \$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + wire width 5 \$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + wire width 5 \$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + wire \$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + wire \$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + wire \$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + wire \$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + wire \$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + wire width 5 \$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + wire \$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + wire \$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + wire \$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + wire \$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + wire \$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + wire \$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" + wire \$57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" + wire \$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + wire width 4 \$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" + wire width 5 \$61 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" + wire width 4 \$63 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" + wire \$65 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" + wire width 5 \$67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" + wire width 5 \$69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + wire \$71 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + wire \$73 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + wire \$75 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + wire \$77 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + wire \$79 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + wire width 4 \$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" + wire \$81 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" + wire width 64 \$83 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" + wire \$86 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" + wire width 64 \$89 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 64 \$91 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 64 \$93 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire \$95 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 2 \$97 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" + wire \$99 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:187" + wire \all_rd + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire \all_rd_dly + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire \all_rd_dly$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:192" + wire \all_rd_pulse + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + wire \all_rd_rise + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \alu_alu0_alu_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \alu_alu0_alu_op__data_len$next + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \alu_alu0_alu_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \alu_alu0_alu_op__fn_unit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \alu_alu0_alu_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \alu_alu0_alu_op__imm_data__data$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_alu0_alu_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_alu0_alu_op__imm_data__ok$next + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \alu_alu0_alu_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \alu_alu0_alu_op__input_carry$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \alu_alu0_alu_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \alu_alu0_alu_op__insn$next + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \alu_alu0_alu_op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \alu_alu0_alu_op__insn_type$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_alu0_alu_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_alu0_alu_op__invert_in$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_alu0_alu_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_alu0_alu_op__invert_out$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_alu0_alu_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_alu0_alu_op__is_32bit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_alu0_alu_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_alu0_alu_op__is_signed$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_alu0_alu_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_alu0_alu_op__oe__oe$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_alu0_alu_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_alu0_alu_op__oe__ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_alu0_alu_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_alu0_alu_op__output_carry$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_alu0_alu_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_alu0_alu_op__rc__ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_alu0_alu_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_alu0_alu_op__rc__rc$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_alu0_alu_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_alu0_alu_op__write_cr0$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_alu0_alu_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_alu0_alu_op__zero_a$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \alu_alu0_cr_a + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire \alu_alu0_n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire \alu_alu0_n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \alu_alu0_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire \alu_alu0_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire \alu_alu0_p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \alu_alu0_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \alu_alu0_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \alu_alu0_xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 \alu_alu0_xer_ca$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \alu_alu0_xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \alu_alu0_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \alu_alu0_xer_so$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:196" + wire \alu_done + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire \alu_done_dly + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire \alu_done_dly$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + wire \alu_done_rise + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire \alu_l_q_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \alu_l_r_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \alu_l_r_alu$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \alu_l_s_alu + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:197" + wire \alu_pulse + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198" + wire width 5 \alu_pulsem + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire \alui_l_q_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \alui_l_r_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \alui_l_r_alui$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \alui_l_s_alui + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 41 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 40 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 32 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" + wire output 20 \cu_busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:108" + wire \cu_done_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:104" + wire \cu_go_die_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" + wire input 19 \cu_issue_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 4 input 23 \cu_rd__go_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 4 output 22 \cu_rd__rel_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" + wire width 4 input 21 \cu_rdmaskn_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:102" + wire \cu_shadown_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 5 input 30 \cu_wr__go_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 5 output 29 \cu_wr__rel_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:97" + wire width 5 \cu_wrmask_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 64 \data_r0__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 64 \data_r0__o$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r0__o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r0__o_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 4 \data_r1__cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 4 \data_r1__cr_a$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r1__cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r1__cr_a_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 2 \data_r2__xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 2 \data_r2__xer_ca$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r2__xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r2__xer_ca_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 2 \data_r3__xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 2 \data_r3__xer_ov$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r3__xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r3__xer_ov_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r4__xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r4__xer_so$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r4__xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r4__xer_so_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 31 \dest1_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 4 output 33 \dest2_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 2 output 35 \dest3_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 2 output 37 \dest4_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire output 39 \dest5_o + attribute \src "libresoc.v:20893.7-20893.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 28 \o_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire \opc_l_q_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \opc_l_r_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \opc_l_r_opc$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \opc_l_s_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \opc_l_s_opc$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 17 \oper_i_alu_alu0__data_len + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 2 \oper_i_alu_alu0__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 3 \oper_i_alu_alu0__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 4 \oper_i_alu_alu0__imm_data__ok + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 13 \oper_i_alu_alu0__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 18 \oper_i_alu_alu0__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \oper_i_alu_alu0__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \oper_i_alu_alu0__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 11 \oper_i_alu_alu0__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 15 \oper_i_alu_alu0__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 16 \oper_i_alu_alu0__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 7 \oper_i_alu_alu0__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \oper_i_alu_alu0__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \oper_i_alu_alu0__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 6 \oper_i_alu_alu0__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 5 \oper_i_alu_alu0__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \oper_i_alu_alu0__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \oper_i_alu_alu0__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" + wire width 5 \prev_wr_go + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" + wire width 5 \prev_wr_go$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212" + wire \req_done + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 5 \req_l_q_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 5 \req_l_r_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 5 \req_l_r_req$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 5 \req_l_s_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 5 \req_l_s_req$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226" + wire \reset + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:229" + wire width 4 \reset_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:228" + wire width 5 \reset_w + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire \rok_l_q_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \rok_l_r_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \rok_l_r_rdok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \rok_l_s_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \rok_l_s_rdok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \rst_l_r_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \rst_l_r_rst$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \rst_l_s_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \rst_l_s_rst$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227" + wire \rst_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 24 \src1_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 25 \src2_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire input 26 \src3_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 2 input 27 \src4_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 4 \src_l_q_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 4 \src_l_r_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 4 \src_l_r_src$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 4 \src_l_s_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 4 \src_l_s_src$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:166" + wire width 64 \src_or_imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:166" + wire width 64 \src_or_imm$88 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 64 \src_r0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 64 \src_r0$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 64 \src_r1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 64 \src_r1$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire \src_r2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire \src_r2$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 2 \src_r3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 2 \src_r3$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:167" + wire \src_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:167" + wire \src_sel$85 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" + wire \wr_any + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 34 \xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 36 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 38 \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" + cell $and $and$libresoc.v:21570$549 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_alu0_p_ready_o + connect \B \alui_l_q_alui + connect \Y $and$libresoc.v:21570$549_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" + cell $and $and$libresoc.v:21571$550 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_alu0_n_valid_o + connect \B \alu_l_q_alu + connect \Y $and$libresoc.v:21571$550_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + cell $and $and$libresoc.v:21572$551 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \src_l_q_src + connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } + connect \Y $and$libresoc.v:21572$551_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + cell $and $and$libresoc.v:21575$554 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \$103 + connect \B { 2'11 \$107 \$105 } + connect \Y $and$libresoc.v:21575$554_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + cell $and $and$libresoc.v:21577$556 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \$109 + connect \B \$111 + connect \Y $and$libresoc.v:21577$556_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + cell $and $and$libresoc.v:21578$557 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_busy_o + connect \B \cu_shadown_i + connect \Y $and$libresoc.v:21578$557_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + cell $and $and$libresoc.v:21579$558 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_busy_o + connect \B \cu_shadown_i + connect \Y $and$libresoc.v:21579$558_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $and $and$libresoc.v:21580$559 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \$5 + connect \Y $and$libresoc.v:21580$559_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + cell $and $and$libresoc.v:21581$560 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_busy_o + connect \B \cu_shadown_i + connect \Y $and$libresoc.v:21581$560_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + cell $and $and$libresoc.v:21582$561 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_busy_o + connect \B \cu_shadown_i + connect \Y $and$libresoc.v:21582$561_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + cell $and $and$libresoc.v:21583$562 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_busy_o + connect \B \cu_shadown_i + connect \Y $and$libresoc.v:21583$562_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" + cell $and $and$libresoc.v:21584$563 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \req_l_q_req + connect \B { \$115 \$117 \$119 \$121 \$123 } + connect \Y $and$libresoc.v:21584$563_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" + cell $and $and$libresoc.v:21585$564 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \$125 + connect \B \cu_wrmask_o + connect \Y $and$libresoc.v:21585$564_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + cell $and $and$libresoc.v:21586$565 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_wr__go_i [0] + connect \B \cu_busy_o + connect \Y $and$libresoc.v:21586$565_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + cell $and $and$libresoc.v:21587$566 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_wr__go_i [1] + connect \B \cu_busy_o + connect \Y $and$libresoc.v:21587$566_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + cell $and $and$libresoc.v:21588$567 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_wr__go_i [2] + connect \B \cu_busy_o + connect \Y $and$libresoc.v:21588$567_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + cell $and $and$libresoc.v:21589$568 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_wr__go_i [3] + connect \B \cu_busy_o + connect \Y $and$libresoc.v:21589$568_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + cell $and $and$libresoc.v:21590$569 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_wr__go_i [4] + connect \B \cu_busy_o + connect \Y $and$libresoc.v:21590$569_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $and$libresoc.v:21592$571 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \all_rd + connect \B \$13 + connect \Y $and$libresoc.v:21592$571_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $and$libresoc.v:21594$573 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_done + connect \B \$17 + connect \Y $and$libresoc.v:21594$573_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" + cell $and $and$libresoc.v:21595$574 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \cu_wr__go_i + connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } + connect \Y $and$libresoc.v:21595$574_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $and $and$libresoc.v:21597$576 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \cu_wr__rel_o + connect \B \$25 + connect \Y $and$libresoc.v:21597$576_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $and $and$libresoc.v:21600$579 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_busy_o + connect \B \$23 + connect \Y $and$libresoc.v:21600$579_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" + cell $and $and$libresoc.v:21604$583 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_busy_o + connect \B \rok_l_q_rdok + connect \Y $and$libresoc.v:21604$583_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + cell $and $and$libresoc.v:21606$585 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_any + connect \B \$39 + connect \Y $and$libresoc.v:21606$585_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + cell $and $and$libresoc.v:21607$586 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \req_l_q_req + connect \B \cu_wrmask_o + connect \Y $and$libresoc.v:21607$586_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + cell $and $and$libresoc.v:21609$588 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$41 + connect \B \$45 + connect \Y $and$libresoc.v:21609$588_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + cell $and $and$libresoc.v:21611$590 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$49 + connect \B \alu_alu0_n_ready_i + connect \Y $and$libresoc.v:21611$590_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + cell $and $and$libresoc.v:21612$591 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$51 + connect \B \alu_alu0_n_valid_o + connect \Y $and$libresoc.v:21612$591_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + cell $and $and$libresoc.v:21613$592 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$53 + connect \B \cu_busy_o + connect \Y $and$libresoc.v:21613$592_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" + cell $and $and$libresoc.v:21618$597 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_alu0_n_valid_o + connect \B \cu_busy_o + connect \Y $and$libresoc.v:21618$597_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" + cell $and $and$libresoc.v:21619$598 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \alu_pulsem + connect \B \cu_wrmask_o + connect \Y $and$libresoc.v:21619$598_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + cell $and $and$libresoc.v:21622$601 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \o_ok + connect \B \cu_busy_o + connect \Y $and$libresoc.v:21622$601_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + cell $and $and$libresoc.v:21623$602 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cr_a_ok + connect \B \cu_busy_o + connect \Y $and$libresoc.v:21623$602_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + cell $and $and$libresoc.v:21624$603 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \xer_ca_ok + connect \B \cu_busy_o + connect \Y $and$libresoc.v:21624$603_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + cell $and $and$libresoc.v:21625$604 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \xer_ov_ok + connect \B \cu_busy_o + connect \Y $and$libresoc.v:21625$604_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + cell $and $and$libresoc.v:21626$605 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \xer_so_ok + connect \B \cu_busy_o + connect \Y $and$libresoc.v:21626$605_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + cell $eq $eq$libresoc.v:21608$587 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$43 + connect \B 1'0 + connect \Y $eq$libresoc.v:21608$587_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + cell $eq $eq$libresoc.v:21610$589 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_wrmask_o + connect \B 1'0 + connect \Y $eq$libresoc.v:21610$589_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" + cell $not $not$libresoc.v:21573$552 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_alu0_alu_op__zero_a + connect \Y $not$libresoc.v:21573$552_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" + cell $not $not$libresoc.v:21574$553 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_alu0_alu_op__imm_data__ok + connect \Y $not$libresoc.v:21574$553_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + cell $not $not$libresoc.v:21576$555 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \cu_rdmaskn_i + connect \Y $not$libresoc.v:21576$555_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $not$libresoc.v:21591$570 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \all_rd_dly + connect \Y $not$libresoc.v:21591$570_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $not$libresoc.v:21593$572 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_done_dly + connect \Y $not$libresoc.v:21593$572_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $not $not$libresoc.v:21596$575 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \cu_wrmask_o + connect \Y $not$libresoc.v:21596$575_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $not $not$libresoc.v:21599$578 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$24 + connect \Y $not$libresoc.v:21599$578_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + cell $not $not$libresoc.v:21605$584 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_alu0_n_ready_i + connect \Y $not$libresoc.v:21605$584_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $not $not$libresoc.v:21620$599 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \cu_rd__rel_o + connect \Y $not$libresoc.v:21620$599_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $or $or$libresoc.v:21603$582 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$33 + connect \B \$35 + connect \Y $or$libresoc.v:21603$582_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" + cell $or $or$libresoc.v:21614$593 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \req_done + connect \B \cu_go_die_i + connect \Y $or$libresoc.v:21614$593_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" + cell $or $or$libresoc.v:21615$594 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_issue_i + connect \B \cu_go_die_i + connect \Y $or$libresoc.v:21615$594_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" + cell $or $or$libresoc.v:21616$595 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \cu_wr__go_i + connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } + connect \Y $or$libresoc.v:21616$595_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" + cell $or $or$libresoc.v:21617$596 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \cu_rd__go_i + connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } + connect \Y $or$libresoc.v:21617$596_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" + cell $or $or$libresoc.v:21621$600 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \reset_w + connect \B \prev_wr_go + connect \Y $or$libresoc.v:21621$600_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $or $or$libresoc.v:21630$609 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \$6 + connect \B \cu_rd__go_i + connect \Y $or$libresoc.v:21630$609_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $reduce_and $reduce_and$libresoc.v:21569$548 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $reduce_and$libresoc.v:21569$548_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $reduce_or $reduce_or$libresoc.v:21598$577 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \$27 + connect \Y $reduce_or$libresoc.v:21598$577_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $reduce_or $reduce_or$libresoc.v:21601$580 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \cu_wr__go_i + connect \Y $reduce_or$libresoc.v:21601$580_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $reduce_or $reduce_or$libresoc.v:21602$581 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \prev_wr_go + connect \Y $reduce_or$libresoc.v:21602$581_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" + cell $mux $ternary$libresoc.v:21627$606 + parameter \WIDTH 1 + connect \A \src_l_q_src [0] + connect \B \opc_l_q_opc + connect \S \alu_alu0_alu_op__zero_a + connect \Y $ternary$libresoc.v:21627$606_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" + cell $mux $ternary$libresoc.v:21628$607 + parameter \WIDTH 64 + connect \A \src1_i + connect \B 64'0000000000000000000000000000000000000000000000000000000000000000 + connect \S \alu_alu0_alu_op__zero_a + connect \Y $ternary$libresoc.v:21628$607_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" + cell $mux $ternary$libresoc.v:21629$608 + parameter \WIDTH 1 + connect \A \src_l_q_src [1] + connect \B \opc_l_q_opc + connect \S \alu_alu0_alu_op__imm_data__ok + connect \Y $ternary$libresoc.v:21629$608_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" + cell $mux $ternary$libresoc.v:21631$610 + parameter \WIDTH 64 + connect \A \src2_i + connect \B \alu_alu0_alu_op__imm_data__data + connect \S \alu_alu0_alu_op__imm_data__ok + connect \Y $ternary$libresoc.v:21631$610_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $ternary$libresoc.v:21632$611 + parameter \WIDTH 64 + connect \A \src_r0 + connect \B \src_or_imm + connect \S \src_sel + connect \Y $ternary$libresoc.v:21632$611_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $ternary$libresoc.v:21633$612 + parameter \WIDTH 64 + connect \A \src_r1 + connect \B \src_or_imm$88 + connect \S \src_sel$85 + connect \Y $ternary$libresoc.v:21633$612_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $ternary$libresoc.v:21634$613 + parameter \WIDTH 1 + connect \A \src_r2 + connect \B \src3_i + connect \S \src_l_q_src [2] + connect \Y $ternary$libresoc.v:21634$613_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $ternary$libresoc.v:21635$614 + parameter \WIDTH 2 + connect \A \src_r3 + connect \B \src4_i + connect \S \src_l_q_src [3] + connect \Y $ternary$libresoc.v:21635$614_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:21730.12-21769.4" + cell \alu_alu0 \alu_alu0 + connect \alu_op__data_len \alu_alu0_alu_op__data_len + connect \alu_op__fn_unit \alu_alu0_alu_op__fn_unit + connect \alu_op__imm_data__data \alu_alu0_alu_op__imm_data__data + connect \alu_op__imm_data__ok \alu_alu0_alu_op__imm_data__ok + connect \alu_op__input_carry \alu_alu0_alu_op__input_carry + connect \alu_op__insn \alu_alu0_alu_op__insn + connect \alu_op__insn_type \alu_alu0_alu_op__insn_type + connect \alu_op__invert_in \alu_alu0_alu_op__invert_in + connect \alu_op__invert_out \alu_alu0_alu_op__invert_out + connect \alu_op__is_32bit \alu_alu0_alu_op__is_32bit + connect \alu_op__is_signed \alu_alu0_alu_op__is_signed + connect \alu_op__oe__oe \alu_alu0_alu_op__oe__oe + connect \alu_op__oe__ok \alu_alu0_alu_op__oe__ok + connect \alu_op__output_carry \alu_alu0_alu_op__output_carry + connect \alu_op__rc__ok \alu_alu0_alu_op__rc__ok + connect \alu_op__rc__rc \alu_alu0_alu_op__rc__rc + connect \alu_op__write_cr0 \alu_alu0_alu_op__write_cr0 + connect \alu_op__zero_a \alu_alu0_alu_op__zero_a + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cr_a \alu_alu0_cr_a + connect \cr_a_ok \cr_a_ok + connect \n_ready_i \alu_alu0_n_ready_i + connect \n_valid_o \alu_alu0_n_valid_o + connect \o \alu_alu0_o + connect \o_ok \o_ok + connect \p_ready_o \alu_alu0_p_ready_o + connect \p_valid_i \alu_alu0_p_valid_i + connect \ra \alu_alu0_ra + connect \rb \alu_alu0_rb + connect \xer_ca \alu_alu0_xer_ca + connect \xer_ca$2 \alu_alu0_xer_ca$2 + connect \xer_ca_ok \xer_ca_ok + connect \xer_ov \alu_alu0_xer_ov + connect \xer_ov_ok \xer_ov_ok + connect \xer_so \alu_alu0_xer_so + connect \xer_so$1 \alu_alu0_xer_so$1 + connect \xer_so_ok \xer_so_ok + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:21770.9-21776.4" + cell \alu_l \alu_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_alu \alu_l_q_alu + connect \r_alu \alu_l_r_alu + connect \s_alu \alu_l_s_alu + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:21777.10-21783.4" + cell \alui_l \alui_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_alui \alui_l_q_alui + connect \r_alui \alui_l_r_alui + connect \s_alui \alui_l_s_alui + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:21784.9-21790.4" + cell \opc_l \opc_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_opc \opc_l_q_opc + connect \r_opc \opc_l_r_opc + connect \s_opc \opc_l_s_opc + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:21791.9-21797.4" + cell \req_l \req_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_req \req_l_q_req + connect \r_req \req_l_r_req + connect \s_req \req_l_s_req + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:21798.9-21804.4" + cell \rok_l \rok_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_rdok \rok_l_q_rdok + connect \r_rdok \rok_l_r_rdok + connect \s_rdok \rok_l_s_rdok + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:21805.9-21810.4" + cell \rst_l \rst_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \r_rst \rst_l_r_rst + connect \s_rst \rst_l_s_rst + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:21811.9-21817.4" + cell \src_l \src_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_src \src_l_q_src + connect \r_src \src_l_r_src + connect \s_src \src_l_s_src + end + attribute \src "libresoc.v:20893.7-20893.20" + process $proc$libresoc.v:20893$802 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:21031.7-21031.24" + process $proc$libresoc.v:21031$803 + assign { } { } + assign $1\all_rd_dly[0:0] 1'0 + sync always + sync init + update \all_rd_dly $1\all_rd_dly[0:0] + end + attribute \src "libresoc.v:21039.13-21039.45" + process $proc$libresoc.v:21039$804 + assign { } { } + assign $1\alu_alu0_alu_op__data_len[3:0] 4'0000 + sync always + sync init + update \alu_alu0_alu_op__data_len $1\alu_alu0_alu_op__data_len[3:0] + end + attribute \src "libresoc.v:21056.14-21056.48" + process $proc$libresoc.v:21056$805 + assign { } { } + assign $1\alu_alu0_alu_op__fn_unit[11:0] 12'000000000000 + sync always + sync init + update \alu_alu0_alu_op__fn_unit $1\alu_alu0_alu_op__fn_unit[11:0] + end + attribute \src "libresoc.v:21060.14-21060.68" + process $proc$libresoc.v:21060$806 + assign { } { } + assign $1\alu_alu0_alu_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \alu_alu0_alu_op__imm_data__data $1\alu_alu0_alu_op__imm_data__data[63:0] + end + attribute \src "libresoc.v:21064.7-21064.43" + process $proc$libresoc.v:21064$807 + assign { } { } + assign $1\alu_alu0_alu_op__imm_data__ok[0:0] 1'0 + sync always + sync init + update \alu_alu0_alu_op__imm_data__ok $1\alu_alu0_alu_op__imm_data__ok[0:0] + end + attribute \src "libresoc.v:21072.13-21072.48" + process $proc$libresoc.v:21072$808 + assign { } { } + assign $1\alu_alu0_alu_op__input_carry[1:0] 2'00 + sync always + sync init + update \alu_alu0_alu_op__input_carry $1\alu_alu0_alu_op__input_carry[1:0] + end + attribute \src "libresoc.v:21076.14-21076.43" + process $proc$libresoc.v:21076$809 + assign { } { } + assign $1\alu_alu0_alu_op__insn[31:0] 0 + sync always + sync init + update \alu_alu0_alu_op__insn $1\alu_alu0_alu_op__insn[31:0] + end + attribute \src "libresoc.v:21154.13-21154.47" + process $proc$libresoc.v:21154$810 + assign { } { } + assign $1\alu_alu0_alu_op__insn_type[6:0] 7'0000000 + sync always + sync init + update \alu_alu0_alu_op__insn_type $1\alu_alu0_alu_op__insn_type[6:0] + end + attribute \src "libresoc.v:21158.7-21158.40" + process $proc$libresoc.v:21158$811 + assign { } { } + assign $1\alu_alu0_alu_op__invert_in[0:0] 1'0 + sync always + sync init + update \alu_alu0_alu_op__invert_in $1\alu_alu0_alu_op__invert_in[0:0] + end + attribute \src "libresoc.v:21162.7-21162.41" + process $proc$libresoc.v:21162$812 + assign { } { } + assign $1\alu_alu0_alu_op__invert_out[0:0] 1'0 + sync always + sync init + update \alu_alu0_alu_op__invert_out $1\alu_alu0_alu_op__invert_out[0:0] + end + attribute \src "libresoc.v:21166.7-21166.39" + process $proc$libresoc.v:21166$813 + assign { } { } + assign $1\alu_alu0_alu_op__is_32bit[0:0] 1'0 + sync always + sync init + update \alu_alu0_alu_op__is_32bit $1\alu_alu0_alu_op__is_32bit[0:0] + end + attribute \src "libresoc.v:21170.7-21170.40" + process $proc$libresoc.v:21170$814 + assign { } { } + assign $1\alu_alu0_alu_op__is_signed[0:0] 1'0 + sync always + sync init + update \alu_alu0_alu_op__is_signed $1\alu_alu0_alu_op__is_signed[0:0] + end + attribute \src "libresoc.v:21174.7-21174.37" + process $proc$libresoc.v:21174$815 + assign { } { } + assign $1\alu_alu0_alu_op__oe__oe[0:0] 1'0 + sync always + sync init + update \alu_alu0_alu_op__oe__oe $1\alu_alu0_alu_op__oe__oe[0:0] + end + attribute \src "libresoc.v:21178.7-21178.37" + process $proc$libresoc.v:21178$816 + assign { } { } + assign $1\alu_alu0_alu_op__oe__ok[0:0] 1'0 + sync always + sync init + update \alu_alu0_alu_op__oe__ok $1\alu_alu0_alu_op__oe__ok[0:0] + end + attribute \src "libresoc.v:21182.7-21182.43" + process $proc$libresoc.v:21182$817 + assign { } { } + assign $1\alu_alu0_alu_op__output_carry[0:0] 1'0 + sync always + sync init + update \alu_alu0_alu_op__output_carry $1\alu_alu0_alu_op__output_carry[0:0] + end + attribute \src "libresoc.v:21186.7-21186.37" + process $proc$libresoc.v:21186$818 + assign { } { } + assign $1\alu_alu0_alu_op__rc__ok[0:0] 1'0 + sync always + sync init + update \alu_alu0_alu_op__rc__ok $1\alu_alu0_alu_op__rc__ok[0:0] + end + attribute \src "libresoc.v:21190.7-21190.37" + process $proc$libresoc.v:21190$819 + assign { } { } + assign $1\alu_alu0_alu_op__rc__rc[0:0] 1'0 + sync always + sync init + update \alu_alu0_alu_op__rc__rc $1\alu_alu0_alu_op__rc__rc[0:0] + end + attribute \src "libresoc.v:21194.7-21194.40" + process $proc$libresoc.v:21194$820 + assign { } { } + assign $1\alu_alu0_alu_op__write_cr0[0:0] 1'0 + sync always + sync init + update \alu_alu0_alu_op__write_cr0 $1\alu_alu0_alu_op__write_cr0[0:0] + end + attribute \src "libresoc.v:21198.7-21198.37" + process $proc$libresoc.v:21198$821 + assign { } { } + assign $1\alu_alu0_alu_op__zero_a[0:0] 1'0 + sync always + sync init + update \alu_alu0_alu_op__zero_a $1\alu_alu0_alu_op__zero_a[0:0] + end + attribute \src "libresoc.v:21230.7-21230.26" + process $proc$libresoc.v:21230$822 + assign { } { } + assign $1\alu_done_dly[0:0] 1'0 + sync always + sync init + update \alu_done_dly $1\alu_done_dly[0:0] + end + attribute \src "libresoc.v:21238.7-21238.25" + process $proc$libresoc.v:21238$823 + assign { } { } + assign $1\alu_l_r_alu[0:0] 1'1 + sync always + sync init + update \alu_l_r_alu $1\alu_l_r_alu[0:0] + end + attribute \src "libresoc.v:21250.7-21250.27" + process $proc$libresoc.v:21250$824 + assign { } { } + assign $1\alui_l_r_alui[0:0] 1'1 + sync always + sync init + update \alui_l_r_alui $1\alui_l_r_alui[0:0] + end + attribute \src "libresoc.v:21284.14-21284.47" + process $proc$libresoc.v:21284$825 + assign { } { } + assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \data_r0__o $1\data_r0__o[63:0] + end + attribute \src "libresoc.v:21288.7-21288.27" + process $proc$libresoc.v:21288$826 + assign { } { } + assign $1\data_r0__o_ok[0:0] 1'0 + sync always + sync init + update \data_r0__o_ok $1\data_r0__o_ok[0:0] + end + attribute \src "libresoc.v:21292.13-21292.33" + process $proc$libresoc.v:21292$827 + assign { } { } + assign $1\data_r1__cr_a[3:0] 4'0000 + sync always + sync init + update \data_r1__cr_a $1\data_r1__cr_a[3:0] + end + attribute \src "libresoc.v:21296.7-21296.30" + process $proc$libresoc.v:21296$828 + assign { } { } + assign $1\data_r1__cr_a_ok[0:0] 1'0 + sync always + sync init + update \data_r1__cr_a_ok $1\data_r1__cr_a_ok[0:0] + end + attribute \src "libresoc.v:21300.13-21300.35" + process $proc$libresoc.v:21300$829 + assign { } { } + assign $1\data_r2__xer_ca[1:0] 2'00 + sync always + sync init + update \data_r2__xer_ca $1\data_r2__xer_ca[1:0] + end + attribute \src "libresoc.v:21304.7-21304.32" + process $proc$libresoc.v:21304$830 + assign { } { } + assign $1\data_r2__xer_ca_ok[0:0] 1'0 + sync always + sync init + update \data_r2__xer_ca_ok $1\data_r2__xer_ca_ok[0:0] + end + attribute \src "libresoc.v:21308.13-21308.35" + process $proc$libresoc.v:21308$831 + assign { } { } + assign $1\data_r3__xer_ov[1:0] 2'00 + sync always + sync init + update \data_r3__xer_ov $1\data_r3__xer_ov[1:0] + end + attribute \src "libresoc.v:21312.7-21312.32" + process $proc$libresoc.v:21312$832 + assign { } { } + assign $1\data_r3__xer_ov_ok[0:0] 1'0 + sync always + sync init + update \data_r3__xer_ov_ok $1\data_r3__xer_ov_ok[0:0] + end + attribute \src "libresoc.v:21316.7-21316.29" + process $proc$libresoc.v:21316$833 + assign { } { } + assign $1\data_r4__xer_so[0:0] 1'0 + sync always + sync init + update \data_r4__xer_so $1\data_r4__xer_so[0:0] + end + attribute \src "libresoc.v:21320.7-21320.32" + process $proc$libresoc.v:21320$834 + assign { } { } + assign $1\data_r4__xer_so_ok[0:0] 1'0 + sync always + sync init + update \data_r4__xer_so_ok $1\data_r4__xer_so_ok[0:0] + end + attribute \src "libresoc.v:21343.7-21343.25" + process $proc$libresoc.v:21343$835 + assign { } { } + assign $1\opc_l_r_opc[0:0] 1'1 + sync always + sync init + update \opc_l_r_opc $1\opc_l_r_opc[0:0] + end + attribute \src "libresoc.v:21347.7-21347.25" + process $proc$libresoc.v:21347$836 + assign { } { } + assign $1\opc_l_s_opc[0:0] 1'0 + sync always + sync init + update \opc_l_s_opc $1\opc_l_s_opc[0:0] + end + attribute \src "libresoc.v:21478.13-21478.31" + process $proc$libresoc.v:21478$837 + assign { } { } + assign $1\prev_wr_go[4:0] 5'00000 + sync always + sync init + update \prev_wr_go $1\prev_wr_go[4:0] + end + attribute \src "libresoc.v:21486.13-21486.32" + process $proc$libresoc.v:21486$838 + assign { } { } + assign $1\req_l_r_req[4:0] 5'11111 + sync always + sync init + update \req_l_r_req $1\req_l_r_req[4:0] + end + attribute \src "libresoc.v:21490.13-21490.32" + process $proc$libresoc.v:21490$839 + assign { } { } + assign $1\req_l_s_req[4:0] 5'00000 + sync always + sync init + update \req_l_s_req $1\req_l_s_req[4:0] + end + attribute \src "libresoc.v:21502.7-21502.26" + process $proc$libresoc.v:21502$840 + assign { } { } + assign $1\rok_l_r_rdok[0:0] 1'1 + sync always + sync init + update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] + end + attribute \src "libresoc.v:21506.7-21506.26" + process $proc$libresoc.v:21506$841 + assign { } { } + assign $1\rok_l_s_rdok[0:0] 1'0 + sync always + sync init + update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] + end + attribute \src "libresoc.v:21510.7-21510.25" + process $proc$libresoc.v:21510$842 + assign { } { } + assign $1\rst_l_r_rst[0:0] 1'1 + sync always + sync init + update \rst_l_r_rst $1\rst_l_r_rst[0:0] + end + attribute \src "libresoc.v:21514.7-21514.25" + process $proc$libresoc.v:21514$843 + assign { } { } + assign $1\rst_l_s_rst[0:0] 1'0 + sync always + sync init + update \rst_l_s_rst $1\rst_l_s_rst[0:0] + end + attribute \src "libresoc.v:21530.13-21530.31" + process $proc$libresoc.v:21530$844 + assign { } { } + assign $1\src_l_r_src[3:0] 4'1111 + sync always + sync init + update \src_l_r_src $1\src_l_r_src[3:0] + end + attribute \src "libresoc.v:21534.13-21534.31" + process $proc$libresoc.v:21534$845 + assign { } { } + assign $1\src_l_s_src[3:0] 4'0000 + sync always + sync init + update \src_l_s_src $1\src_l_s_src[3:0] + end + attribute \src "libresoc.v:21542.14-21542.43" + process $proc$libresoc.v:21542$846 + assign { } { } + assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \src_r0 $1\src_r0[63:0] + end + attribute \src "libresoc.v:21546.14-21546.43" + process $proc$libresoc.v:21546$847 + assign { } { } + assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \src_r1 $1\src_r1[63:0] + end + attribute \src "libresoc.v:21550.7-21550.20" + process $proc$libresoc.v:21550$848 + assign { } { } + assign $1\src_r2[0:0] 1'0 + sync always + sync init + update \src_r2 $1\src_r2[0:0] + end + attribute \src "libresoc.v:21554.13-21554.26" + process $proc$libresoc.v:21554$849 + assign { } { } + assign $1\src_r3[1:0] 2'00 + sync always + sync init + update \src_r3 $1\src_r3[1:0] + end + attribute \src "libresoc.v:21636.3-21637.39" + process $proc$libresoc.v:21636$615 + assign { } { } + assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next + sync posedge \coresync_clk + update \alu_l_r_alu $0\alu_l_r_alu[0:0] + end + attribute \src "libresoc.v:21638.3-21639.43" + process $proc$libresoc.v:21638$616 + assign { } { } + assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next + sync posedge \coresync_clk + update \alui_l_r_alui $0\alui_l_r_alui[0:0] + end + attribute \src "libresoc.v:21640.3-21641.29" + process $proc$libresoc.v:21640$617 + assign { } { } + assign $0\src_r3[1:0] \src_r3$next + sync posedge \coresync_clk + update \src_r3 $0\src_r3[1:0] + end + attribute \src "libresoc.v:21642.3-21643.29" + process $proc$libresoc.v:21642$618 + assign { } { } + assign $0\src_r2[0:0] \src_r2$next + sync posedge \coresync_clk + update \src_r2 $0\src_r2[0:0] + end + attribute \src "libresoc.v:21644.3-21645.29" + process $proc$libresoc.v:21644$619 + assign { } { } + assign $0\src_r1[63:0] \src_r1$next + sync posedge \coresync_clk + update \src_r1 $0\src_r1[63:0] + end + attribute \src "libresoc.v:21646.3-21647.29" + process $proc$libresoc.v:21646$620 + assign { } { } + assign $0\src_r0[63:0] \src_r0$next + sync posedge \coresync_clk + update \src_r0 $0\src_r0[63:0] + end + attribute \src "libresoc.v:21648.3-21649.47" + process $proc$libresoc.v:21648$621 + assign { } { } + assign $0\data_r4__xer_so[0:0] \data_r4__xer_so$next + sync posedge \coresync_clk + update \data_r4__xer_so $0\data_r4__xer_so[0:0] + end + attribute \src "libresoc.v:21650.3-21651.53" + process $proc$libresoc.v:21650$622 + assign { } { } + assign $0\data_r4__xer_so_ok[0:0] \data_r4__xer_so_ok$next + sync posedge \coresync_clk + update \data_r4__xer_so_ok $0\data_r4__xer_so_ok[0:0] + end + attribute \src "libresoc.v:21652.3-21653.47" + process $proc$libresoc.v:21652$623 + assign { } { } + assign $0\data_r3__xer_ov[1:0] \data_r3__xer_ov$next + sync posedge \coresync_clk + update \data_r3__xer_ov $0\data_r3__xer_ov[1:0] + end + attribute \src "libresoc.v:21654.3-21655.53" + process $proc$libresoc.v:21654$624 + assign { } { } + assign $0\data_r3__xer_ov_ok[0:0] \data_r3__xer_ov_ok$next + sync posedge \coresync_clk + update \data_r3__xer_ov_ok $0\data_r3__xer_ov_ok[0:0] + end + attribute \src "libresoc.v:21656.3-21657.47" + process $proc$libresoc.v:21656$625 + assign { } { } + assign $0\data_r2__xer_ca[1:0] \data_r2__xer_ca$next + sync posedge \coresync_clk + update \data_r2__xer_ca $0\data_r2__xer_ca[1:0] + end + attribute \src "libresoc.v:21658.3-21659.53" + process $proc$libresoc.v:21658$626 + assign { } { } + assign $0\data_r2__xer_ca_ok[0:0] \data_r2__xer_ca_ok$next + sync posedge \coresync_clk + update \data_r2__xer_ca_ok $0\data_r2__xer_ca_ok[0:0] + end + attribute \src "libresoc.v:21660.3-21661.43" + process $proc$libresoc.v:21660$627 + assign { } { } + assign $0\data_r1__cr_a[3:0] \data_r1__cr_a$next + sync posedge \coresync_clk + update \data_r1__cr_a $0\data_r1__cr_a[3:0] + end + attribute \src "libresoc.v:21662.3-21663.49" + process $proc$libresoc.v:21662$628 + assign { } { } + assign $0\data_r1__cr_a_ok[0:0] \data_r1__cr_a_ok$next + sync posedge \coresync_clk + update \data_r1__cr_a_ok $0\data_r1__cr_a_ok[0:0] + end + attribute \src "libresoc.v:21664.3-21665.37" + process $proc$libresoc.v:21664$629 + assign { } { } + assign $0\data_r0__o[63:0] \data_r0__o$next + sync posedge \coresync_clk + update \data_r0__o $0\data_r0__o[63:0] + end + attribute \src "libresoc.v:21666.3-21667.43" + process $proc$libresoc.v:21666$630 + assign { } { } + assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next + sync posedge \coresync_clk + update \data_r0__o_ok $0\data_r0__o_ok[0:0] + end + attribute \src "libresoc.v:21668.3-21669.69" + process $proc$libresoc.v:21668$631 + assign { } { } + assign $0\alu_alu0_alu_op__insn_type[6:0] \alu_alu0_alu_op__insn_type$next + sync posedge \coresync_clk + update \alu_alu0_alu_op__insn_type $0\alu_alu0_alu_op__insn_type[6:0] + end + attribute \src "libresoc.v:21670.3-21671.65" + process $proc$libresoc.v:21670$632 + assign { } { } + assign $0\alu_alu0_alu_op__fn_unit[11:0] \alu_alu0_alu_op__fn_unit$next + sync posedge \coresync_clk + update \alu_alu0_alu_op__fn_unit $0\alu_alu0_alu_op__fn_unit[11:0] + end + attribute \src "libresoc.v:21672.3-21673.79" + process $proc$libresoc.v:21672$633 + assign { } { } + assign $0\alu_alu0_alu_op__imm_data__data[63:0] \alu_alu0_alu_op__imm_data__data$next + sync posedge \coresync_clk + update \alu_alu0_alu_op__imm_data__data $0\alu_alu0_alu_op__imm_data__data[63:0] + end + attribute \src "libresoc.v:21674.3-21675.75" + process $proc$libresoc.v:21674$634 + assign { } { } + assign $0\alu_alu0_alu_op__imm_data__ok[0:0] \alu_alu0_alu_op__imm_data__ok$next + sync posedge \coresync_clk + update \alu_alu0_alu_op__imm_data__ok $0\alu_alu0_alu_op__imm_data__ok[0:0] + end + attribute \src "libresoc.v:21676.3-21677.63" + process $proc$libresoc.v:21676$635 + assign { } { } + assign $0\alu_alu0_alu_op__rc__rc[0:0] \alu_alu0_alu_op__rc__rc$next + sync posedge \coresync_clk + update \alu_alu0_alu_op__rc__rc $0\alu_alu0_alu_op__rc__rc[0:0] + end + attribute \src "libresoc.v:21678.3-21679.63" + process $proc$libresoc.v:21678$636 + assign { } { } + assign $0\alu_alu0_alu_op__rc__ok[0:0] \alu_alu0_alu_op__rc__ok$next + sync posedge \coresync_clk + update \alu_alu0_alu_op__rc__ok $0\alu_alu0_alu_op__rc__ok[0:0] + end + attribute \src "libresoc.v:21680.3-21681.63" + process $proc$libresoc.v:21680$637 + assign { } { } + assign $0\alu_alu0_alu_op__oe__oe[0:0] \alu_alu0_alu_op__oe__oe$next + sync posedge \coresync_clk + update \alu_alu0_alu_op__oe__oe $0\alu_alu0_alu_op__oe__oe[0:0] + end + attribute \src "libresoc.v:21682.3-21683.63" + process $proc$libresoc.v:21682$638 + assign { } { } + assign $0\alu_alu0_alu_op__oe__ok[0:0] \alu_alu0_alu_op__oe__ok$next + sync posedge \coresync_clk + update \alu_alu0_alu_op__oe__ok $0\alu_alu0_alu_op__oe__ok[0:0] + end + attribute \src "libresoc.v:21684.3-21685.69" + process $proc$libresoc.v:21684$639 + assign { } { } + assign $0\alu_alu0_alu_op__invert_in[0:0] \alu_alu0_alu_op__invert_in$next + sync posedge \coresync_clk + update \alu_alu0_alu_op__invert_in $0\alu_alu0_alu_op__invert_in[0:0] + end + attribute \src "libresoc.v:21686.3-21687.63" + process $proc$libresoc.v:21686$640 + assign { } { } + assign $0\alu_alu0_alu_op__zero_a[0:0] \alu_alu0_alu_op__zero_a$next + sync posedge \coresync_clk + update \alu_alu0_alu_op__zero_a $0\alu_alu0_alu_op__zero_a[0:0] + end + attribute \src "libresoc.v:21688.3-21689.71" + process $proc$libresoc.v:21688$641 + assign { } { } + assign $0\alu_alu0_alu_op__invert_out[0:0] \alu_alu0_alu_op__invert_out$next + sync posedge \coresync_clk + update \alu_alu0_alu_op__invert_out $0\alu_alu0_alu_op__invert_out[0:0] + end + attribute \src "libresoc.v:21690.3-21691.69" + process $proc$libresoc.v:21690$642 + assign { } { } + assign $0\alu_alu0_alu_op__write_cr0[0:0] \alu_alu0_alu_op__write_cr0$next + sync posedge \coresync_clk + update \alu_alu0_alu_op__write_cr0 $0\alu_alu0_alu_op__write_cr0[0:0] + end + attribute \src "libresoc.v:21692.3-21693.73" + process $proc$libresoc.v:21692$643 + assign { } { } + assign $0\alu_alu0_alu_op__input_carry[1:0] \alu_alu0_alu_op__input_carry$next + sync posedge \coresync_clk + update \alu_alu0_alu_op__input_carry $0\alu_alu0_alu_op__input_carry[1:0] + end + attribute \src "libresoc.v:21694.3-21695.75" + process $proc$libresoc.v:21694$644 + assign { } { } + assign $0\alu_alu0_alu_op__output_carry[0:0] \alu_alu0_alu_op__output_carry$next + sync posedge \coresync_clk + update \alu_alu0_alu_op__output_carry $0\alu_alu0_alu_op__output_carry[0:0] + end + attribute \src "libresoc.v:21696.3-21697.67" + process $proc$libresoc.v:21696$645 + assign { } { } + assign $0\alu_alu0_alu_op__is_32bit[0:0] \alu_alu0_alu_op__is_32bit$next + sync posedge \coresync_clk + update \alu_alu0_alu_op__is_32bit $0\alu_alu0_alu_op__is_32bit[0:0] + end + attribute \src "libresoc.v:21698.3-21699.69" + process $proc$libresoc.v:21698$646 + assign { } { } + assign $0\alu_alu0_alu_op__is_signed[0:0] \alu_alu0_alu_op__is_signed$next + sync posedge \coresync_clk + update \alu_alu0_alu_op__is_signed $0\alu_alu0_alu_op__is_signed[0:0] + end + attribute \src "libresoc.v:21700.3-21701.67" + process $proc$libresoc.v:21700$647 + assign { } { } + assign $0\alu_alu0_alu_op__data_len[3:0] \alu_alu0_alu_op__data_len$next + sync posedge \coresync_clk + update \alu_alu0_alu_op__data_len $0\alu_alu0_alu_op__data_len[3:0] + end + attribute \src "libresoc.v:21702.3-21703.59" + process $proc$libresoc.v:21702$648 + assign { } { } + assign $0\alu_alu0_alu_op__insn[31:0] \alu_alu0_alu_op__insn$next + sync posedge \coresync_clk + update \alu_alu0_alu_op__insn $0\alu_alu0_alu_op__insn[31:0] + end + attribute \src "libresoc.v:21704.3-21705.39" + process $proc$libresoc.v:21704$649 + assign { } { } + assign $0\req_l_r_req[4:0] \req_l_r_req$next + sync posedge \coresync_clk + update \req_l_r_req $0\req_l_r_req[4:0] + end + attribute \src "libresoc.v:21706.3-21707.39" + process $proc$libresoc.v:21706$650 + assign { } { } + assign $0\req_l_s_req[4:0] \req_l_s_req$next + sync posedge \coresync_clk + update \req_l_s_req $0\req_l_s_req[4:0] + end + attribute \src "libresoc.v:21708.3-21709.39" + process $proc$libresoc.v:21708$651 + assign { } { } + assign $0\src_l_r_src[3:0] \src_l_r_src$next + sync posedge \coresync_clk + update \src_l_r_src $0\src_l_r_src[3:0] + end + attribute \src "libresoc.v:21710.3-21711.39" + process $proc$libresoc.v:21710$652 + assign { } { } + assign $0\src_l_s_src[3:0] \src_l_s_src$next + sync posedge \coresync_clk + update \src_l_s_src $0\src_l_s_src[3:0] + end + attribute \src "libresoc.v:21712.3-21713.39" + process $proc$libresoc.v:21712$653 + assign { } { } + assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next + sync posedge \coresync_clk + update \opc_l_r_opc $0\opc_l_r_opc[0:0] + end + attribute \src "libresoc.v:21714.3-21715.39" + process $proc$libresoc.v:21714$654 + assign { } { } + assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next + sync posedge \coresync_clk + update \opc_l_s_opc $0\opc_l_s_opc[0:0] + end + attribute \src "libresoc.v:21716.3-21717.39" + process $proc$libresoc.v:21716$655 + assign { } { } + assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next + sync posedge \coresync_clk + update \rst_l_r_rst $0\rst_l_r_rst[0:0] + end + attribute \src "libresoc.v:21718.3-21719.39" + process $proc$libresoc.v:21718$656 + assign { } { } + assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next + sync posedge \coresync_clk + update \rst_l_s_rst $0\rst_l_s_rst[0:0] + end + attribute \src "libresoc.v:21720.3-21721.41" + process $proc$libresoc.v:21720$657 + assign { } { } + assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next + sync posedge \coresync_clk + update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] + end + attribute \src "libresoc.v:21722.3-21723.41" + process $proc$libresoc.v:21722$658 + assign { } { } + assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next + sync posedge \coresync_clk + update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] + end + attribute \src "libresoc.v:21724.3-21725.37" + process $proc$libresoc.v:21724$659 + assign { } { } + assign $0\prev_wr_go[4:0] \prev_wr_go$next + sync posedge \coresync_clk + update \prev_wr_go $0\prev_wr_go[4:0] + end + attribute \src "libresoc.v:21726.3-21727.40" + process $proc$libresoc.v:21726$660 + assign { } { } + assign $0\alu_done_dly[0:0] \alu_alu0_n_valid_o + sync posedge \coresync_clk + update \alu_done_dly $0\alu_done_dly[0:0] + end + attribute \src "libresoc.v:21728.3-21729.25" + process $proc$libresoc.v:21728$661 + assign { } { } + assign $0\all_rd_dly[0:0] \$11 + sync posedge \coresync_clk + update \all_rd_dly $0\all_rd_dly[0:0] + end + attribute \src "libresoc.v:21818.3-21827.6" + process $proc$libresoc.v:21818$662 + assign { } { } + assign { } { } + assign $0\req_done[0:0] $1\req_done[0:0] + attribute \src "libresoc.v:21819.5-21819.29" + switch \initial + attribute \src "libresoc.v:21819.9-21819.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + switch \$55 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\req_done[0:0] 1'1 + case + assign $1\req_done[0:0] \$47 + end + sync always + update \req_done $0\req_done[0:0] + end + attribute \src "libresoc.v:21828.3-21836.6" + process $proc$libresoc.v:21828$663 + assign { } { } + assign { } { } + assign $0\rok_l_s_rdok$next[0:0]$664 $1\rok_l_s_rdok$next[0:0]$665 + attribute \src "libresoc.v:21829.5-21829.29" + switch \initial + attribute \src "libresoc.v:21829.9-21829.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rok_l_s_rdok$next[0:0]$665 1'0 + case + assign $1\rok_l_s_rdok$next[0:0]$665 \cu_issue_i + end + sync always + update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$664 + end + attribute \src "libresoc.v:21837.3-21845.6" + process $proc$libresoc.v:21837$666 + assign { } { } + assign { } { } + assign $0\rok_l_r_rdok$next[0:0]$667 $1\rok_l_r_rdok$next[0:0]$668 + attribute \src "libresoc.v:21838.5-21838.29" + switch \initial + attribute \src "libresoc.v:21838.9-21838.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rok_l_r_rdok$next[0:0]$668 1'1 + case + assign $1\rok_l_r_rdok$next[0:0]$668 \$65 + end + sync always + update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$667 + end + attribute \src "libresoc.v:21846.3-21854.6" + process $proc$libresoc.v:21846$669 + assign { } { } + assign { } { } + assign $0\rst_l_s_rst$next[0:0]$670 $1\rst_l_s_rst$next[0:0]$671 + attribute \src "libresoc.v:21847.5-21847.29" + switch \initial + attribute \src "libresoc.v:21847.9-21847.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rst_l_s_rst$next[0:0]$671 1'0 + case + assign $1\rst_l_s_rst$next[0:0]$671 \all_rd + end + sync always + update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$670 + end + attribute \src "libresoc.v:21855.3-21863.6" + process $proc$libresoc.v:21855$672 + assign { } { } + assign { } { } + assign $0\rst_l_r_rst$next[0:0]$673 $1\rst_l_r_rst$next[0:0]$674 + attribute \src "libresoc.v:21856.5-21856.29" + switch \initial + attribute \src "libresoc.v:21856.9-21856.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rst_l_r_rst$next[0:0]$674 1'1 + case + assign $1\rst_l_r_rst$next[0:0]$674 \rst_r + end + sync always + update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$673 + end + attribute \src "libresoc.v:21864.3-21872.6" + process $proc$libresoc.v:21864$675 + assign { } { } + assign { } { } + assign $0\opc_l_s_opc$next[0:0]$676 $1\opc_l_s_opc$next[0:0]$677 + attribute \src "libresoc.v:21865.5-21865.29" + switch \initial + attribute \src "libresoc.v:21865.9-21865.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\opc_l_s_opc$next[0:0]$677 1'0 + case + assign $1\opc_l_s_opc$next[0:0]$677 \cu_issue_i + end + sync always + update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$676 + end + attribute \src "libresoc.v:21873.3-21881.6" + process $proc$libresoc.v:21873$678 + assign { } { } + assign { } { } + assign $0\opc_l_r_opc$next[0:0]$679 $1\opc_l_r_opc$next[0:0]$680 + attribute \src "libresoc.v:21874.5-21874.29" + switch \initial + attribute \src "libresoc.v:21874.9-21874.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\opc_l_r_opc$next[0:0]$680 1'1 + case + assign $1\opc_l_r_opc$next[0:0]$680 \req_done + end + sync always + update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$679 + end + attribute \src "libresoc.v:21882.3-21890.6" + process $proc$libresoc.v:21882$681 + assign { } { } + assign { } { } + assign $0\src_l_s_src$next[3:0]$682 $1\src_l_s_src$next[3:0]$683 + attribute \src "libresoc.v:21883.5-21883.29" + switch \initial + attribute \src "libresoc.v:21883.9-21883.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_l_s_src$next[3:0]$683 4'0000 + case + assign $1\src_l_s_src$next[3:0]$683 { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i } + end + sync always + update \src_l_s_src$next $0\src_l_s_src$next[3:0]$682 + end + attribute \src "libresoc.v:21891.3-21899.6" + process $proc$libresoc.v:21891$684 + assign { } { } + assign { } { } + assign $0\src_l_r_src$next[3:0]$685 $1\src_l_r_src$next[3:0]$686 + attribute \src "libresoc.v:21892.5-21892.29" + switch \initial + attribute \src "libresoc.v:21892.9-21892.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_l_r_src$next[3:0]$686 4'1111 + case + assign $1\src_l_r_src$next[3:0]$686 \reset_r + end + sync always + update \src_l_r_src$next $0\src_l_r_src$next[3:0]$685 + end + attribute \src "libresoc.v:21900.3-21908.6" + process $proc$libresoc.v:21900$687 + assign { } { } + assign { } { } + assign $0\req_l_s_req$next[4:0]$688 $1\req_l_s_req$next[4:0]$689 + attribute \src "libresoc.v:21901.5-21901.29" + switch \initial + attribute \src "libresoc.v:21901.9-21901.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\req_l_s_req$next[4:0]$689 5'00000 + case + assign $1\req_l_s_req$next[4:0]$689 \$67 + end + sync always + update \req_l_s_req$next $0\req_l_s_req$next[4:0]$688 + end + attribute \src "libresoc.v:21909.3-21917.6" + process $proc$libresoc.v:21909$690 + assign { } { } + assign { } { } + assign $0\req_l_r_req$next[4:0]$691 $1\req_l_r_req$next[4:0]$692 + attribute \src "libresoc.v:21910.5-21910.29" + switch \initial + attribute \src "libresoc.v:21910.9-21910.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\req_l_r_req$next[4:0]$692 5'11111 + case + assign $1\req_l_r_req$next[4:0]$692 \$69 + end + sync always + update \req_l_r_req$next $0\req_l_r_req$next[4:0]$691 + end + attribute \src "libresoc.v:21918.3-21956.6" + process $proc$libresoc.v:21918$693 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\alu_alu0_alu_op__data_len$next[3:0]$694 $1\alu_alu0_alu_op__data_len$next[3:0]$712 + assign $0\alu_alu0_alu_op__fn_unit$next[11:0]$695 $1\alu_alu0_alu_op__fn_unit$next[11:0]$713 + assign { } { } + assign { } { } + assign $0\alu_alu0_alu_op__input_carry$next[1:0]$698 $1\alu_alu0_alu_op__input_carry$next[1:0]$716 + assign $0\alu_alu0_alu_op__insn$next[31:0]$699 $1\alu_alu0_alu_op__insn$next[31:0]$717 + assign $0\alu_alu0_alu_op__insn_type$next[6:0]$700 $1\alu_alu0_alu_op__insn_type$next[6:0]$718 + assign $0\alu_alu0_alu_op__invert_in$next[0:0]$701 $1\alu_alu0_alu_op__invert_in$next[0:0]$719 + assign $0\alu_alu0_alu_op__invert_out$next[0:0]$702 $1\alu_alu0_alu_op__invert_out$next[0:0]$720 + assign $0\alu_alu0_alu_op__is_32bit$next[0:0]$703 $1\alu_alu0_alu_op__is_32bit$next[0:0]$721 + assign $0\alu_alu0_alu_op__is_signed$next[0:0]$704 $1\alu_alu0_alu_op__is_signed$next[0:0]$722 + assign { } { } + assign { } { } + assign $0\alu_alu0_alu_op__output_carry$next[0:0]$707 $1\alu_alu0_alu_op__output_carry$next[0:0]$725 + assign { } { } + assign { } { } + assign $0\alu_alu0_alu_op__write_cr0$next[0:0]$710 $1\alu_alu0_alu_op__write_cr0$next[0:0]$728 + assign $0\alu_alu0_alu_op__zero_a$next[0:0]$711 $1\alu_alu0_alu_op__zero_a$next[0:0]$729 + assign $0\alu_alu0_alu_op__imm_data__data$next[63:0]$696 $2\alu_alu0_alu_op__imm_data__data$next[63:0]$730 + assign $0\alu_alu0_alu_op__imm_data__ok$next[0:0]$697 $2\alu_alu0_alu_op__imm_data__ok$next[0:0]$731 + assign $0\alu_alu0_alu_op__oe__oe$next[0:0]$705 $2\alu_alu0_alu_op__oe__oe$next[0:0]$732 + assign $0\alu_alu0_alu_op__oe__ok$next[0:0]$706 $2\alu_alu0_alu_op__oe__ok$next[0:0]$733 + assign $0\alu_alu0_alu_op__rc__ok$next[0:0]$708 $2\alu_alu0_alu_op__rc__ok$next[0:0]$734 + assign $0\alu_alu0_alu_op__rc__rc$next[0:0]$709 $2\alu_alu0_alu_op__rc__rc$next[0:0]$735 + attribute \src "libresoc.v:21919.5-21919.29" + switch \initial + attribute \src "libresoc.v:21919.9-21919.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\alu_alu0_alu_op__insn$next[31:0]$717 $1\alu_alu0_alu_op__data_len$next[3:0]$712 $1\alu_alu0_alu_op__is_signed$next[0:0]$722 $1\alu_alu0_alu_op__is_32bit$next[0:0]$721 $1\alu_alu0_alu_op__output_carry$next[0:0]$725 $1\alu_alu0_alu_op__input_carry$next[1:0]$716 $1\alu_alu0_alu_op__write_cr0$next[0:0]$728 $1\alu_alu0_alu_op__invert_out$next[0:0]$720 $1\alu_alu0_alu_op__zero_a$next[0:0]$729 $1\alu_alu0_alu_op__invert_in$next[0:0]$719 $1\alu_alu0_alu_op__oe__ok$next[0:0]$724 $1\alu_alu0_alu_op__oe__oe$next[0:0]$723 $1\alu_alu0_alu_op__rc__ok$next[0:0]$726 $1\alu_alu0_alu_op__rc__rc$next[0:0]$727 $1\alu_alu0_alu_op__imm_data__ok$next[0:0]$715 $1\alu_alu0_alu_op__imm_data__data$next[63:0]$714 $1\alu_alu0_alu_op__fn_unit$next[11:0]$713 $1\alu_alu0_alu_op__insn_type$next[6:0]$718 } { \oper_i_alu_alu0__insn \oper_i_alu_alu0__data_len \oper_i_alu_alu0__is_signed \oper_i_alu_alu0__is_32bit \oper_i_alu_alu0__output_carry \oper_i_alu_alu0__input_carry \oper_i_alu_alu0__write_cr0 \oper_i_alu_alu0__invert_out \oper_i_alu_alu0__zero_a \oper_i_alu_alu0__invert_in \oper_i_alu_alu0__oe__ok \oper_i_alu_alu0__oe__oe \oper_i_alu_alu0__rc__ok \oper_i_alu_alu0__rc__rc \oper_i_alu_alu0__imm_data__ok \oper_i_alu_alu0__imm_data__data \oper_i_alu_alu0__fn_unit \oper_i_alu_alu0__insn_type } + case + assign $1\alu_alu0_alu_op__data_len$next[3:0]$712 \alu_alu0_alu_op__data_len + assign $1\alu_alu0_alu_op__fn_unit$next[11:0]$713 \alu_alu0_alu_op__fn_unit + assign $1\alu_alu0_alu_op__imm_data__data$next[63:0]$714 \alu_alu0_alu_op__imm_data__data + assign $1\alu_alu0_alu_op__imm_data__ok$next[0:0]$715 \alu_alu0_alu_op__imm_data__ok + assign $1\alu_alu0_alu_op__input_carry$next[1:0]$716 \alu_alu0_alu_op__input_carry + assign $1\alu_alu0_alu_op__insn$next[31:0]$717 \alu_alu0_alu_op__insn + assign $1\alu_alu0_alu_op__insn_type$next[6:0]$718 \alu_alu0_alu_op__insn_type + assign $1\alu_alu0_alu_op__invert_in$next[0:0]$719 \alu_alu0_alu_op__invert_in + assign $1\alu_alu0_alu_op__invert_out$next[0:0]$720 \alu_alu0_alu_op__invert_out + assign $1\alu_alu0_alu_op__is_32bit$next[0:0]$721 \alu_alu0_alu_op__is_32bit + assign $1\alu_alu0_alu_op__is_signed$next[0:0]$722 \alu_alu0_alu_op__is_signed + assign $1\alu_alu0_alu_op__oe__oe$next[0:0]$723 \alu_alu0_alu_op__oe__oe + assign $1\alu_alu0_alu_op__oe__ok$next[0:0]$724 \alu_alu0_alu_op__oe__ok + assign $1\alu_alu0_alu_op__output_carry$next[0:0]$725 \alu_alu0_alu_op__output_carry + assign $1\alu_alu0_alu_op__rc__ok$next[0:0]$726 \alu_alu0_alu_op__rc__ok + assign $1\alu_alu0_alu_op__rc__rc$next[0:0]$727 \alu_alu0_alu_op__rc__rc + assign $1\alu_alu0_alu_op__write_cr0$next[0:0]$728 \alu_alu0_alu_op__write_cr0 + assign $1\alu_alu0_alu_op__zero_a$next[0:0]$729 \alu_alu0_alu_op__zero_a + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $2\alu_alu0_alu_op__imm_data__data$next[63:0]$730 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\alu_alu0_alu_op__imm_data__ok$next[0:0]$731 1'0 + assign $2\alu_alu0_alu_op__rc__rc$next[0:0]$735 1'0 + assign $2\alu_alu0_alu_op__rc__ok$next[0:0]$734 1'0 + assign $2\alu_alu0_alu_op__oe__oe$next[0:0]$732 1'0 + assign $2\alu_alu0_alu_op__oe__ok$next[0:0]$733 1'0 + case + assign $2\alu_alu0_alu_op__imm_data__data$next[63:0]$730 $1\alu_alu0_alu_op__imm_data__data$next[63:0]$714 + assign $2\alu_alu0_alu_op__imm_data__ok$next[0:0]$731 $1\alu_alu0_alu_op__imm_data__ok$next[0:0]$715 + assign $2\alu_alu0_alu_op__oe__oe$next[0:0]$732 $1\alu_alu0_alu_op__oe__oe$next[0:0]$723 + assign $2\alu_alu0_alu_op__oe__ok$next[0:0]$733 $1\alu_alu0_alu_op__oe__ok$next[0:0]$724 + assign $2\alu_alu0_alu_op__rc__ok$next[0:0]$734 $1\alu_alu0_alu_op__rc__ok$next[0:0]$726 + assign $2\alu_alu0_alu_op__rc__rc$next[0:0]$735 $1\alu_alu0_alu_op__rc__rc$next[0:0]$727 + end + sync always + update \alu_alu0_alu_op__data_len$next $0\alu_alu0_alu_op__data_len$next[3:0]$694 + update \alu_alu0_alu_op__fn_unit$next $0\alu_alu0_alu_op__fn_unit$next[11:0]$695 + update \alu_alu0_alu_op__imm_data__data$next $0\alu_alu0_alu_op__imm_data__data$next[63:0]$696 + update \alu_alu0_alu_op__imm_data__ok$next $0\alu_alu0_alu_op__imm_data__ok$next[0:0]$697 + update \alu_alu0_alu_op__input_carry$next $0\alu_alu0_alu_op__input_carry$next[1:0]$698 + update \alu_alu0_alu_op__insn$next $0\alu_alu0_alu_op__insn$next[31:0]$699 + update \alu_alu0_alu_op__insn_type$next $0\alu_alu0_alu_op__insn_type$next[6:0]$700 + update \alu_alu0_alu_op__invert_in$next $0\alu_alu0_alu_op__invert_in$next[0:0]$701 + update \alu_alu0_alu_op__invert_out$next $0\alu_alu0_alu_op__invert_out$next[0:0]$702 + update \alu_alu0_alu_op__is_32bit$next $0\alu_alu0_alu_op__is_32bit$next[0:0]$703 + update \alu_alu0_alu_op__is_signed$next $0\alu_alu0_alu_op__is_signed$next[0:0]$704 + update \alu_alu0_alu_op__oe__oe$next $0\alu_alu0_alu_op__oe__oe$next[0:0]$705 + update \alu_alu0_alu_op__oe__ok$next $0\alu_alu0_alu_op__oe__ok$next[0:0]$706 + update \alu_alu0_alu_op__output_carry$next $0\alu_alu0_alu_op__output_carry$next[0:0]$707 + update \alu_alu0_alu_op__rc__ok$next $0\alu_alu0_alu_op__rc__ok$next[0:0]$708 + update \alu_alu0_alu_op__rc__rc$next $0\alu_alu0_alu_op__rc__rc$next[0:0]$709 + update \alu_alu0_alu_op__write_cr0$next $0\alu_alu0_alu_op__write_cr0$next[0:0]$710 + update \alu_alu0_alu_op__zero_a$next $0\alu_alu0_alu_op__zero_a$next[0:0]$711 + end + attribute \src "libresoc.v:21957.3-21978.6" + process $proc$libresoc.v:21957$736 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r0__o$next[63:0]$737 $2\data_r0__o$next[63:0]$741 + assign { } { } + assign $0\data_r0__o_ok$next[0:0]$738 $3\data_r0__o_ok$next[0:0]$743 + attribute \src "libresoc.v:21958.5-21958.29" + switch \initial + attribute \src "libresoc.v:21958.9-21958.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r0__o_ok$next[0:0]$740 $1\data_r0__o$next[63:0]$739 } { \o_ok \alu_alu0_o } + case + assign $1\data_r0__o$next[63:0]$739 \data_r0__o + assign $1\data_r0__o_ok$next[0:0]$740 \data_r0__o_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r0__o_ok$next[0:0]$742 $2\data_r0__o$next[63:0]$741 } 65'00000000000000000000000000000000000000000000000000000000000000000 + case + assign $2\data_r0__o$next[63:0]$741 $1\data_r0__o$next[63:0]$739 + assign $2\data_r0__o_ok$next[0:0]$742 $1\data_r0__o_ok$next[0:0]$740 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r0__o_ok$next[0:0]$743 1'0 + case + assign $3\data_r0__o_ok$next[0:0]$743 $2\data_r0__o_ok$next[0:0]$742 + end + sync always + update \data_r0__o$next $0\data_r0__o$next[63:0]$737 + update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$738 + end + attribute \src "libresoc.v:21979.3-22000.6" + process $proc$libresoc.v:21979$744 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r1__cr_a$next[3:0]$745 $2\data_r1__cr_a$next[3:0]$749 + assign { } { } + assign $0\data_r1__cr_a_ok$next[0:0]$746 $3\data_r1__cr_a_ok$next[0:0]$751 + attribute \src "libresoc.v:21980.5-21980.29" + switch \initial + attribute \src "libresoc.v:21980.9-21980.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r1__cr_a_ok$next[0:0]$748 $1\data_r1__cr_a$next[3:0]$747 } { \cr_a_ok \alu_alu0_cr_a } + case + assign $1\data_r1__cr_a$next[3:0]$747 \data_r1__cr_a + assign $1\data_r1__cr_a_ok$next[0:0]$748 \data_r1__cr_a_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r1__cr_a_ok$next[0:0]$750 $2\data_r1__cr_a$next[3:0]$749 } 5'00000 + case + assign $2\data_r1__cr_a$next[3:0]$749 $1\data_r1__cr_a$next[3:0]$747 + assign $2\data_r1__cr_a_ok$next[0:0]$750 $1\data_r1__cr_a_ok$next[0:0]$748 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r1__cr_a_ok$next[0:0]$751 1'0 + case + assign $3\data_r1__cr_a_ok$next[0:0]$751 $2\data_r1__cr_a_ok$next[0:0]$750 + end + sync always + update \data_r1__cr_a$next $0\data_r1__cr_a$next[3:0]$745 + update \data_r1__cr_a_ok$next $0\data_r1__cr_a_ok$next[0:0]$746 + end + attribute \src "libresoc.v:22001.3-22022.6" + process $proc$libresoc.v:22001$752 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r2__xer_ca$next[1:0]$753 $2\data_r2__xer_ca$next[1:0]$757 + assign { } { } + assign $0\data_r2__xer_ca_ok$next[0:0]$754 $3\data_r2__xer_ca_ok$next[0:0]$759 + attribute \src "libresoc.v:22002.5-22002.29" + switch \initial + attribute \src "libresoc.v:22002.9-22002.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r2__xer_ca_ok$next[0:0]$756 $1\data_r2__xer_ca$next[1:0]$755 } { \xer_ca_ok \alu_alu0_xer_ca } + case + assign $1\data_r2__xer_ca$next[1:0]$755 \data_r2__xer_ca + assign $1\data_r2__xer_ca_ok$next[0:0]$756 \data_r2__xer_ca_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r2__xer_ca_ok$next[0:0]$758 $2\data_r2__xer_ca$next[1:0]$757 } 3'000 + case + assign $2\data_r2__xer_ca$next[1:0]$757 $1\data_r2__xer_ca$next[1:0]$755 + assign $2\data_r2__xer_ca_ok$next[0:0]$758 $1\data_r2__xer_ca_ok$next[0:0]$756 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r2__xer_ca_ok$next[0:0]$759 1'0 + case + assign $3\data_r2__xer_ca_ok$next[0:0]$759 $2\data_r2__xer_ca_ok$next[0:0]$758 + end + sync always + update \data_r2__xer_ca$next $0\data_r2__xer_ca$next[1:0]$753 + update \data_r2__xer_ca_ok$next $0\data_r2__xer_ca_ok$next[0:0]$754 + end + attribute \src "libresoc.v:22023.3-22044.6" + process $proc$libresoc.v:22023$760 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r3__xer_ov$next[1:0]$761 $2\data_r3__xer_ov$next[1:0]$765 + assign { } { } + assign $0\data_r3__xer_ov_ok$next[0:0]$762 $3\data_r3__xer_ov_ok$next[0:0]$767 + attribute \src "libresoc.v:22024.5-22024.29" + switch \initial + attribute \src "libresoc.v:22024.9-22024.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r3__xer_ov_ok$next[0:0]$764 $1\data_r3__xer_ov$next[1:0]$763 } { \xer_ov_ok \alu_alu0_xer_ov } + case + assign $1\data_r3__xer_ov$next[1:0]$763 \data_r3__xer_ov + assign $1\data_r3__xer_ov_ok$next[0:0]$764 \data_r3__xer_ov_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r3__xer_ov_ok$next[0:0]$766 $2\data_r3__xer_ov$next[1:0]$765 } 3'000 + case + assign $2\data_r3__xer_ov$next[1:0]$765 $1\data_r3__xer_ov$next[1:0]$763 + assign $2\data_r3__xer_ov_ok$next[0:0]$766 $1\data_r3__xer_ov_ok$next[0:0]$764 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r3__xer_ov_ok$next[0:0]$767 1'0 + case + assign $3\data_r3__xer_ov_ok$next[0:0]$767 $2\data_r3__xer_ov_ok$next[0:0]$766 + end + sync always + update \data_r3__xer_ov$next $0\data_r3__xer_ov$next[1:0]$761 + update \data_r3__xer_ov_ok$next $0\data_r3__xer_ov_ok$next[0:0]$762 + end + attribute \src "libresoc.v:22045.3-22066.6" + process $proc$libresoc.v:22045$768 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r4__xer_so$next[0:0]$769 $2\data_r4__xer_so$next[0:0]$773 + assign { } { } + assign $0\data_r4__xer_so_ok$next[0:0]$770 $3\data_r4__xer_so_ok$next[0:0]$775 + attribute \src "libresoc.v:22046.5-22046.29" + switch \initial + attribute \src "libresoc.v:22046.9-22046.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r4__xer_so_ok$next[0:0]$772 $1\data_r4__xer_so$next[0:0]$771 } { \xer_so_ok \alu_alu0_xer_so } + case + assign $1\data_r4__xer_so$next[0:0]$771 \data_r4__xer_so + assign $1\data_r4__xer_so_ok$next[0:0]$772 \data_r4__xer_so_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r4__xer_so_ok$next[0:0]$774 $2\data_r4__xer_so$next[0:0]$773 } 2'00 + case + assign $2\data_r4__xer_so$next[0:0]$773 $1\data_r4__xer_so$next[0:0]$771 + assign $2\data_r4__xer_so_ok$next[0:0]$774 $1\data_r4__xer_so_ok$next[0:0]$772 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r4__xer_so_ok$next[0:0]$775 1'0 + case + assign $3\data_r4__xer_so_ok$next[0:0]$775 $2\data_r4__xer_so_ok$next[0:0]$774 + end + sync always + update \data_r4__xer_so$next $0\data_r4__xer_so$next[0:0]$769 + update \data_r4__xer_so_ok$next $0\data_r4__xer_so_ok$next[0:0]$770 + end + attribute \src "libresoc.v:22067.3-22076.6" + process $proc$libresoc.v:22067$776 + assign { } { } + assign { } { } + assign $0\src_r0$next[63:0]$777 $1\src_r0$next[63:0]$778 + attribute \src "libresoc.v:22068.5-22068.29" + switch \initial + attribute \src "libresoc.v:22068.9-22068.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch \src_sel + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r0$next[63:0]$778 \src_or_imm + case + assign $1\src_r0$next[63:0]$778 \src_r0 + end + sync always + update \src_r0$next $0\src_r0$next[63:0]$777 + end + attribute \src "libresoc.v:22077.3-22086.6" + process $proc$libresoc.v:22077$779 + assign { } { } + assign { } { } + assign $0\src_r1$next[63:0]$780 $1\src_r1$next[63:0]$781 + attribute \src "libresoc.v:22078.5-22078.29" + switch \initial + attribute \src "libresoc.v:22078.9-22078.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch \src_sel$85 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r1$next[63:0]$781 \src_or_imm$88 + case + assign $1\src_r1$next[63:0]$781 \src_r1 + end + sync always + update \src_r1$next $0\src_r1$next[63:0]$780 + end + attribute \src "libresoc.v:22087.3-22096.6" + process $proc$libresoc.v:22087$782 + assign { } { } + assign { } { } + assign $0\src_r2$next[0:0]$783 $1\src_r2$next[0:0]$784 + attribute \src "libresoc.v:22088.5-22088.29" + switch \initial + attribute \src "libresoc.v:22088.9-22088.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch \src_l_q_src [2] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r2$next[0:0]$784 \src3_i + case + assign $1\src_r2$next[0:0]$784 \src_r2 + end + sync always + update \src_r2$next $0\src_r2$next[0:0]$783 + end + attribute \src "libresoc.v:22097.3-22106.6" + process $proc$libresoc.v:22097$785 + assign { } { } + assign { } { } + assign $0\src_r3$next[1:0]$786 $1\src_r3$next[1:0]$787 + attribute \src "libresoc.v:22098.5-22098.29" + switch \initial + attribute \src "libresoc.v:22098.9-22098.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch \src_l_q_src [3] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r3$next[1:0]$787 \src4_i + case + assign $1\src_r3$next[1:0]$787 \src_r3 + end + sync always + update \src_r3$next $0\src_r3$next[1:0]$786 + end + attribute \src "libresoc.v:22107.3-22115.6" + process $proc$libresoc.v:22107$788 + assign { } { } + assign { } { } + assign $0\alui_l_r_alui$next[0:0]$789 $1\alui_l_r_alui$next[0:0]$790 + attribute \src "libresoc.v:22108.5-22108.29" + switch \initial + attribute \src "libresoc.v:22108.9-22108.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\alui_l_r_alui$next[0:0]$790 1'1 + case + assign $1\alui_l_r_alui$next[0:0]$790 \$99 + end + sync always + update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$789 + end + attribute \src "libresoc.v:22116.3-22124.6" + process $proc$libresoc.v:22116$791 + assign { } { } + assign { } { } + assign $0\alu_l_r_alu$next[0:0]$792 $1\alu_l_r_alu$next[0:0]$793 + attribute \src "libresoc.v:22117.5-22117.29" + switch \initial + attribute \src "libresoc.v:22117.9-22117.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\alu_l_r_alu$next[0:0]$793 1'1 + case + assign $1\alu_l_r_alu$next[0:0]$793 \$101 + end + sync always + update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$792 + end + attribute \src "libresoc.v:22125.3-22134.6" + process $proc$libresoc.v:22125$794 + assign { } { } + assign { } { } + assign $0\dest1_o[63:0] $1\dest1_o[63:0] + attribute \src "libresoc.v:22126.5-22126.29" + switch \initial + attribute \src "libresoc.v:22126.9-22126.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$129 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest1_o[63:0] \data_r0__o + case + assign $1\dest1_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \dest1_o $0\dest1_o[63:0] + end + attribute \src "libresoc.v:22135.3-22144.6" + process $proc$libresoc.v:22135$795 + assign { } { } + assign { } { } + assign $0\dest2_o[3:0] $1\dest2_o[3:0] + attribute \src "libresoc.v:22136.5-22136.29" + switch \initial + attribute \src "libresoc.v:22136.9-22136.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$131 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest2_o[3:0] \data_r1__cr_a + case + assign $1\dest2_o[3:0] 4'0000 + end + sync always + update \dest2_o $0\dest2_o[3:0] + end + attribute \src "libresoc.v:22145.3-22154.6" + process $proc$libresoc.v:22145$796 + assign { } { } + assign { } { } + assign $0\dest3_o[1:0] $1\dest3_o[1:0] + attribute \src "libresoc.v:22146.5-22146.29" + switch \initial + attribute \src "libresoc.v:22146.9-22146.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$133 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest3_o[1:0] \data_r2__xer_ca + case + assign $1\dest3_o[1:0] 2'00 + end + sync always + update \dest3_o $0\dest3_o[1:0] + end + attribute \src "libresoc.v:22155.3-22164.6" + process $proc$libresoc.v:22155$797 + assign { } { } + assign { } { } + assign $0\dest4_o[1:0] $1\dest4_o[1:0] + attribute \src "libresoc.v:22156.5-22156.29" + switch \initial + attribute \src "libresoc.v:22156.9-22156.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$135 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest4_o[1:0] \data_r3__xer_ov + case + assign $1\dest4_o[1:0] 2'00 + end + sync always + update \dest4_o $0\dest4_o[1:0] + end + attribute \src "libresoc.v:22165.3-22174.6" + process $proc$libresoc.v:22165$798 + assign { } { } + assign { } { } + assign $0\dest5_o[0:0] $1\dest5_o[0:0] + attribute \src "libresoc.v:22166.5-22166.29" + switch \initial + attribute \src "libresoc.v:22166.9-22166.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$137 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest5_o[0:0] \data_r4__xer_so + case + assign $1\dest5_o[0:0] 1'0 + end + sync always + update \dest5_o $0\dest5_o[0:0] + end + attribute \src "libresoc.v:22175.3-22183.6" + process $proc$libresoc.v:22175$799 + assign { } { } + assign { } { } + assign $0\prev_wr_go$next[4:0]$800 $1\prev_wr_go$next[4:0]$801 + attribute \src "libresoc.v:22176.5-22176.29" + switch \initial + attribute \src "libresoc.v:22176.9-22176.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\prev_wr_go$next[4:0]$801 5'00000 + case + assign $1\prev_wr_go$next[4:0]$801 \$21 + end + sync always + update \prev_wr_go$next $0\prev_wr_go$next[4:0]$800 + end + connect \$5 $reduce_and$libresoc.v:21569$548_Y + connect \$99 $and$libresoc.v:21570$549_Y + connect \$101 $and$libresoc.v:21571$550_Y + connect \$103 $and$libresoc.v:21572$551_Y + connect \$105 $not$libresoc.v:21573$552_Y + connect \$107 $not$libresoc.v:21574$553_Y + connect \$109 $and$libresoc.v:21575$554_Y + connect \$111 $not$libresoc.v:21576$555_Y + connect \$113 $and$libresoc.v:21577$556_Y + connect \$115 $and$libresoc.v:21578$557_Y + connect \$117 $and$libresoc.v:21579$558_Y + connect \$11 $and$libresoc.v:21580$559_Y + connect \$119 $and$libresoc.v:21581$560_Y + connect \$121 $and$libresoc.v:21582$561_Y + connect \$123 $and$libresoc.v:21583$562_Y + connect \$125 $and$libresoc.v:21584$563_Y + connect \$127 $and$libresoc.v:21585$564_Y + connect \$129 $and$libresoc.v:21586$565_Y + connect \$131 $and$libresoc.v:21587$566_Y + connect \$133 $and$libresoc.v:21588$567_Y + connect \$135 $and$libresoc.v:21589$568_Y + connect \$137 $and$libresoc.v:21590$569_Y + connect \$13 $not$libresoc.v:21591$570_Y + connect \$15 $and$libresoc.v:21592$571_Y + connect \$17 $not$libresoc.v:21593$572_Y + connect \$19 $and$libresoc.v:21594$573_Y + connect \$21 $and$libresoc.v:21595$574_Y + connect \$25 $not$libresoc.v:21596$575_Y + connect \$27 $and$libresoc.v:21597$576_Y + connect \$24 $reduce_or$libresoc.v:21598$577_Y + connect \$23 $not$libresoc.v:21599$578_Y + connect \$31 $and$libresoc.v:21600$579_Y + connect \$33 $reduce_or$libresoc.v:21601$580_Y + connect \$35 $reduce_or$libresoc.v:21602$581_Y + connect \$37 $or$libresoc.v:21603$582_Y + connect \$3 $and$libresoc.v:21604$583_Y + connect \$39 $not$libresoc.v:21605$584_Y + connect \$41 $and$libresoc.v:21606$585_Y + connect \$43 $and$libresoc.v:21607$586_Y + connect \$45 $eq$libresoc.v:21608$587_Y + connect \$47 $and$libresoc.v:21609$588_Y + connect \$49 $eq$libresoc.v:21610$589_Y + connect \$51 $and$libresoc.v:21611$590_Y + connect \$53 $and$libresoc.v:21612$591_Y + connect \$55 $and$libresoc.v:21613$592_Y + connect \$57 $or$libresoc.v:21614$593_Y + connect \$59 $or$libresoc.v:21615$594_Y + connect \$61 $or$libresoc.v:21616$595_Y + connect \$63 $or$libresoc.v:21617$596_Y + connect \$65 $and$libresoc.v:21618$597_Y + connect \$67 $and$libresoc.v:21619$598_Y + connect \$6 $not$libresoc.v:21620$599_Y + connect \$69 $or$libresoc.v:21621$600_Y + connect \$71 $and$libresoc.v:21622$601_Y + connect \$73 $and$libresoc.v:21623$602_Y + connect \$75 $and$libresoc.v:21624$603_Y + connect \$77 $and$libresoc.v:21625$604_Y + connect \$79 $and$libresoc.v:21626$605_Y + connect \$81 $ternary$libresoc.v:21627$606_Y + connect \$83 $ternary$libresoc.v:21628$607_Y + connect \$86 $ternary$libresoc.v:21629$608_Y + connect \$8 $or$libresoc.v:21630$609_Y + connect \$89 $ternary$libresoc.v:21631$610_Y + connect \$91 $ternary$libresoc.v:21632$611_Y + connect \$93 $ternary$libresoc.v:21633$612_Y + connect \$95 $ternary$libresoc.v:21634$613_Y + connect \$97 $ternary$libresoc.v:21635$614_Y + connect \cu_go_die_i 1'0 + connect \cu_shadown_i 1'1 + connect \cu_wr__rel_o \$127 + connect \cu_rd__rel_o \$113 + connect \cu_busy_o \opc_l_q_opc + connect \alu_l_s_alu \all_rd_pulse + connect \alu_alu0_n_ready_i \alu_l_q_alu + connect \alui_l_s_alui \all_rd_pulse + connect \alu_alu0_p_valid_i \alui_l_q_alui + connect \alu_alu0_xer_ca$2 \$97 + connect \alu_alu0_xer_so$1 \$95 + connect \alu_alu0_rb \$93 + connect \alu_alu0_ra \$91 + connect \src_or_imm$88 \$89 + connect \src_sel$85 \$86 + connect \src_or_imm \$83 + connect \src_sel \$81 + connect \cu_wrmask_o { \$79 \$77 \$75 \$73 \$71 } + connect \reset_r \$63 + connect \reset_w \$61 + connect \rst_r \$59 + connect \reset \$57 + connect \wr_any \$37 + connect \cu_done_o \$31 + connect \alu_pulsem { \alu_pulse \alu_pulse \alu_pulse \alu_pulse \alu_pulse } + connect \alu_pulse \alu_done_rise + connect \alu_done_rise \$19 + connect \alu_done_dly$next \alu_done + connect \alu_done \alu_alu0_n_valid_o + connect \all_rd_pulse \all_rd_rise + connect \all_rd_rise \$15 + connect \all_rd_dly$next \all_rd + connect \all_rd \$11 +end +attribute \src "libresoc.v:22221.1-23281.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alu_alu0" +attribute \generator "nMigen" +module \alu_alu0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 25 \alu_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \alu_op__data_len$70 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 10 \alu_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \alu_op__fn_unit$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 11 \alu_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \alu_op__imm_data__data$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \alu_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__imm_data__ok$57 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 21 \alu_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \alu_op__input_carry$66 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 26 \alu_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \alu_op__insn$71 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 9 \alu_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \alu_op__insn_type$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 17 \alu_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__invert_in$62 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 19 \alu_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__invert_out$64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 23 \alu_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__is_32bit$68 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 24 \alu_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__is_signed$69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 15 \alu_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__oe__oe$60 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 16 \alu_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__oe__ok$61 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 22 \alu_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__output_carry$67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \alu_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__rc__ok$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \alu_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__rc__rc$58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 20 \alu_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__write_cr0$65 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 18 \alu_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__zero_a$63 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 38 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 6 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 output 28 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 2 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$53 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire input 8 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire output 7 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 27 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 1 \o_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire output 37 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire input 36 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \pipe1_alu_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \pipe1_alu_op__data_len$20 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \pipe1_alu_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \pipe1_alu_op__fn_unit$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe1_alu_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe1_alu_op__imm_data__data$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_alu_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_alu_op__imm_data__ok$7 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \pipe1_alu_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \pipe1_alu_op__input_carry$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe1_alu_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe1_alu_op__insn$21 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe1_alu_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe1_alu_op__insn_type$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_alu_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_alu_op__invert_in$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_alu_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_alu_op__invert_out$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_alu_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_alu_op__is_32bit$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_alu_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_alu_op__is_signed$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_alu_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_alu_op__oe__oe$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_alu_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_alu_op__oe__ok$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_alu_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_alu_op__output_carry$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_alu_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_alu_op__rc__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_alu_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_alu_op__rc__rc$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_alu_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_alu_op__write_cr0$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_alu_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_alu_op__zero_a$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \pipe1_cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \pipe1_cr_a_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \pipe1_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \pipe1_muxid$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire \pipe1_n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire \pipe1_n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \pipe1_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \pipe1_o_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire \pipe1_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire \pipe1_p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe1_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe1_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \pipe1_xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 \pipe1_xer_ca$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \pipe1_xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \pipe1_xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \pipe1_xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \pipe1_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \pipe1_xer_so$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \pipe1_xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \pipe2_alu_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \pipe2_alu_op__data_len$41 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \pipe2_alu_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \pipe2_alu_op__fn_unit$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe2_alu_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe2_alu_op__imm_data__data$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_alu_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_alu_op__imm_data__ok$28 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \pipe2_alu_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \pipe2_alu_op__input_carry$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe2_alu_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe2_alu_op__insn$42 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe2_alu_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe2_alu_op__insn_type$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_alu_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_alu_op__invert_in$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_alu_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_alu_op__invert_out$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_alu_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_alu_op__is_32bit$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_alu_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_alu_op__is_signed$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_alu_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_alu_op__oe__oe$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_alu_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_alu_op__oe__ok$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_alu_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_alu_op__output_carry$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_alu_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_alu_op__rc__ok$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_alu_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_alu_op__rc__rc$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_alu_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_alu_op__write_cr0$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_alu_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_alu_op__zero_a$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \pipe2_cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \pipe2_cr_a$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \pipe2_cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \pipe2_cr_a_ok$46 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \pipe2_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \pipe2_muxid$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire \pipe2_n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire \pipe2_n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \pipe2_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \pipe2_o$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \pipe2_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \pipe2_o_ok$44 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire \pipe2_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire \pipe2_p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \pipe2_xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \pipe2_xer_ca$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \pipe2_xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \pipe2_xer_ca_ok$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \pipe2_xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \pipe2_xer_ov$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \pipe2_xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \pipe2_xer_ov_ok$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \pipe2_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \pipe2_xer_so$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \pipe2_xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \pipe2_xer_so_ok$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 32 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 33 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 output 29 \xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 input 35 \xer_ca$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 3 \xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 output 30 \xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 4 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 31 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 34 \xer_so$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 5 \xer_so_ok + attribute \module_not_derived 1 + attribute \src "libresoc.v:23120.5-23123.4" + cell \n \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:23124.5-23127.4" + cell \p \p + connect \p_ready_o \p_ready_o + connect \p_valid_i \p_valid_i + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:23128.9-23187.4" + cell \pipe1 \pipe1 + connect \alu_op__data_len \pipe1_alu_op__data_len + connect \alu_op__data_len$18 \pipe1_alu_op__data_len$20 + connect \alu_op__fn_unit \pipe1_alu_op__fn_unit + connect \alu_op__fn_unit$3 \pipe1_alu_op__fn_unit$5 + connect \alu_op__imm_data__data \pipe1_alu_op__imm_data__data + connect \alu_op__imm_data__data$4 \pipe1_alu_op__imm_data__data$6 + connect \alu_op__imm_data__ok \pipe1_alu_op__imm_data__ok + connect \alu_op__imm_data__ok$5 \pipe1_alu_op__imm_data__ok$7 + connect \alu_op__input_carry \pipe1_alu_op__input_carry + connect \alu_op__input_carry$14 \pipe1_alu_op__input_carry$16 + connect \alu_op__insn \pipe1_alu_op__insn + connect \alu_op__insn$19 \pipe1_alu_op__insn$21 + connect \alu_op__insn_type \pipe1_alu_op__insn_type + connect \alu_op__insn_type$2 \pipe1_alu_op__insn_type$4 + connect \alu_op__invert_in \pipe1_alu_op__invert_in + connect \alu_op__invert_in$10 \pipe1_alu_op__invert_in$12 + connect \alu_op__invert_out \pipe1_alu_op__invert_out + connect \alu_op__invert_out$12 \pipe1_alu_op__invert_out$14 + connect \alu_op__is_32bit \pipe1_alu_op__is_32bit + connect \alu_op__is_32bit$16 \pipe1_alu_op__is_32bit$18 + connect \alu_op__is_signed \pipe1_alu_op__is_signed + connect \alu_op__is_signed$17 \pipe1_alu_op__is_signed$19 + connect \alu_op__oe__oe \pipe1_alu_op__oe__oe + connect \alu_op__oe__oe$8 \pipe1_alu_op__oe__oe$10 + connect \alu_op__oe__ok \pipe1_alu_op__oe__ok + connect \alu_op__oe__ok$9 \pipe1_alu_op__oe__ok$11 + connect \alu_op__output_carry \pipe1_alu_op__output_carry + connect \alu_op__output_carry$15 \pipe1_alu_op__output_carry$17 + connect \alu_op__rc__ok \pipe1_alu_op__rc__ok + connect \alu_op__rc__ok$7 \pipe1_alu_op__rc__ok$9 + connect \alu_op__rc__rc \pipe1_alu_op__rc__rc + connect \alu_op__rc__rc$6 \pipe1_alu_op__rc__rc$8 + connect \alu_op__write_cr0 \pipe1_alu_op__write_cr0 + connect \alu_op__write_cr0$13 \pipe1_alu_op__write_cr0$15 + connect \alu_op__zero_a \pipe1_alu_op__zero_a + connect \alu_op__zero_a$11 \pipe1_alu_op__zero_a$13 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cr_a \pipe1_cr_a + connect \cr_a_ok \pipe1_cr_a_ok + connect \muxid \pipe1_muxid + connect \muxid$1 \pipe1_muxid$3 + connect \n_ready_i \pipe1_n_ready_i + connect \n_valid_o \pipe1_n_valid_o + connect \o \pipe1_o + connect \o_ok \pipe1_o_ok + connect \p_ready_o \pipe1_p_ready_o + connect \p_valid_i \pipe1_p_valid_i + connect \ra \pipe1_ra + connect \rb \pipe1_rb + connect \xer_ca \pipe1_xer_ca + connect \xer_ca$21 \pipe1_xer_ca$23 + connect \xer_ca_ok \pipe1_xer_ca_ok + connect \xer_ov \pipe1_xer_ov + connect \xer_ov_ok \pipe1_xer_ov_ok + connect \xer_so \pipe1_xer_so + connect \xer_so$20 \pipe1_xer_so$22 + connect \xer_so_ok \pipe1_xer_so_ok + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:23188.9-23253.4" + cell \pipe2 \pipe2 + connect \alu_op__data_len \pipe2_alu_op__data_len + connect \alu_op__data_len$18 \pipe2_alu_op__data_len$41 + connect \alu_op__fn_unit \pipe2_alu_op__fn_unit + connect \alu_op__fn_unit$3 \pipe2_alu_op__fn_unit$26 + connect \alu_op__imm_data__data \pipe2_alu_op__imm_data__data + connect \alu_op__imm_data__data$4 \pipe2_alu_op__imm_data__data$27 + connect \alu_op__imm_data__ok \pipe2_alu_op__imm_data__ok + connect \alu_op__imm_data__ok$5 \pipe2_alu_op__imm_data__ok$28 + connect \alu_op__input_carry \pipe2_alu_op__input_carry + connect \alu_op__input_carry$14 \pipe2_alu_op__input_carry$37 + connect \alu_op__insn \pipe2_alu_op__insn + connect \alu_op__insn$19 \pipe2_alu_op__insn$42 + connect \alu_op__insn_type \pipe2_alu_op__insn_type + connect \alu_op__insn_type$2 \pipe2_alu_op__insn_type$25 + connect \alu_op__invert_in \pipe2_alu_op__invert_in + connect \alu_op__invert_in$10 \pipe2_alu_op__invert_in$33 + connect \alu_op__invert_out \pipe2_alu_op__invert_out + connect \alu_op__invert_out$12 \pipe2_alu_op__invert_out$35 + connect \alu_op__is_32bit \pipe2_alu_op__is_32bit + connect \alu_op__is_32bit$16 \pipe2_alu_op__is_32bit$39 + connect \alu_op__is_signed \pipe2_alu_op__is_signed + connect \alu_op__is_signed$17 \pipe2_alu_op__is_signed$40 + connect \alu_op__oe__oe \pipe2_alu_op__oe__oe + connect \alu_op__oe__oe$8 \pipe2_alu_op__oe__oe$31 + connect \alu_op__oe__ok \pipe2_alu_op__oe__ok + connect \alu_op__oe__ok$9 \pipe2_alu_op__oe__ok$32 + connect \alu_op__output_carry \pipe2_alu_op__output_carry + connect \alu_op__output_carry$15 \pipe2_alu_op__output_carry$38 + connect \alu_op__rc__ok \pipe2_alu_op__rc__ok + connect \alu_op__rc__ok$7 \pipe2_alu_op__rc__ok$30 + connect \alu_op__rc__rc \pipe2_alu_op__rc__rc + connect \alu_op__rc__rc$6 \pipe2_alu_op__rc__rc$29 + connect \alu_op__write_cr0 \pipe2_alu_op__write_cr0 + connect \alu_op__write_cr0$13 \pipe2_alu_op__write_cr0$36 + connect \alu_op__zero_a \pipe2_alu_op__zero_a + connect \alu_op__zero_a$11 \pipe2_alu_op__zero_a$34 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cr_a \pipe2_cr_a + connect \cr_a$22 \pipe2_cr_a$45 + connect \cr_a_ok \pipe2_cr_a_ok + connect \cr_a_ok$23 \pipe2_cr_a_ok$46 + connect \muxid \pipe2_muxid + connect \muxid$1 \pipe2_muxid$24 + connect \n_ready_i \pipe2_n_ready_i + connect \n_valid_o \pipe2_n_valid_o + connect \o \pipe2_o + connect \o$20 \pipe2_o$43 + connect \o_ok \pipe2_o_ok + connect \o_ok$21 \pipe2_o_ok$44 + connect \p_ready_o \pipe2_p_ready_o + connect \p_valid_i \pipe2_p_valid_i + connect \xer_ca \pipe2_xer_ca + connect \xer_ca$24 \pipe2_xer_ca$47 + connect \xer_ca_ok \pipe2_xer_ca_ok + connect \xer_ca_ok$25 \pipe2_xer_ca_ok$48 + connect \xer_ov \pipe2_xer_ov + connect \xer_ov$26 \pipe2_xer_ov$49 + connect \xer_ov_ok \pipe2_xer_ov_ok + connect \xer_ov_ok$27 \pipe2_xer_ov_ok$50 + connect \xer_so \pipe2_xer_so + connect \xer_so$28 \pipe2_xer_so$51 + connect \xer_so_ok \pipe2_xer_so_ok + connect \xer_so_ok$29 \pipe2_xer_so_ok$52 + end + connect \muxid 2'00 + connect { \xer_so_ok \xer_so } { \pipe2_xer_so_ok$52 \pipe2_xer_so$51 } + connect { \xer_ov_ok \xer_ov } { \pipe2_xer_ov_ok$50 \pipe2_xer_ov$49 } + connect { \xer_ca_ok \xer_ca } { \pipe2_xer_ca_ok$48 \pipe2_xer_ca$47 } + connect { \cr_a_ok \cr_a } { \pipe2_cr_a_ok$46 \pipe2_cr_a$45 } + connect { \o_ok \o } { \pipe2_o_ok$44 \pipe2_o$43 } + connect { \alu_op__insn$71 \alu_op__data_len$70 \alu_op__is_signed$69 \alu_op__is_32bit$68 \alu_op__output_carry$67 \alu_op__input_carry$66 \alu_op__write_cr0$65 \alu_op__invert_out$64 \alu_op__zero_a$63 \alu_op__invert_in$62 \alu_op__oe__ok$61 \alu_op__oe__oe$60 \alu_op__rc__ok$59 \alu_op__rc__rc$58 \alu_op__imm_data__ok$57 \alu_op__imm_data__data$56 \alu_op__fn_unit$55 \alu_op__insn_type$54 } { \pipe2_alu_op__insn$42 \pipe2_alu_op__data_len$41 \pipe2_alu_op__is_signed$40 \pipe2_alu_op__is_32bit$39 \pipe2_alu_op__output_carry$38 \pipe2_alu_op__input_carry$37 \pipe2_alu_op__write_cr0$36 \pipe2_alu_op__invert_out$35 \pipe2_alu_op__zero_a$34 \pipe2_alu_op__invert_in$33 \pipe2_alu_op__oe__ok$32 \pipe2_alu_op__oe__oe$31 \pipe2_alu_op__rc__ok$30 \pipe2_alu_op__rc__rc$29 \pipe2_alu_op__imm_data__ok$28 \pipe2_alu_op__imm_data__data$27 \pipe2_alu_op__fn_unit$26 \pipe2_alu_op__insn_type$25 } + connect \muxid$53 \pipe2_muxid$24 + connect \pipe2_n_ready_i \n_ready_i + connect \n_valid_o \pipe2_n_valid_o + connect \pipe1_xer_ca$23 \xer_ca$2 + connect \pipe1_xer_so$22 \xer_so$1 + connect \pipe1_rb \rb + connect \pipe1_ra \ra + connect { \pipe1_alu_op__insn$21 \pipe1_alu_op__data_len$20 \pipe1_alu_op__is_signed$19 \pipe1_alu_op__is_32bit$18 \pipe1_alu_op__output_carry$17 \pipe1_alu_op__input_carry$16 \pipe1_alu_op__write_cr0$15 \pipe1_alu_op__invert_out$14 \pipe1_alu_op__zero_a$13 \pipe1_alu_op__invert_in$12 \pipe1_alu_op__oe__ok$11 \pipe1_alu_op__oe__oe$10 \pipe1_alu_op__rc__ok$9 \pipe1_alu_op__rc__rc$8 \pipe1_alu_op__imm_data__ok$7 \pipe1_alu_op__imm_data__data$6 \pipe1_alu_op__fn_unit$5 \pipe1_alu_op__insn_type$4 } { \alu_op__insn \alu_op__data_len \alu_op__is_signed \alu_op__is_32bit \alu_op__output_carry \alu_op__input_carry \alu_op__write_cr0 \alu_op__invert_out \alu_op__zero_a \alu_op__invert_in \alu_op__oe__ok \alu_op__oe__oe \alu_op__rc__ok \alu_op__rc__rc \alu_op__imm_data__ok \alu_op__imm_data__data \alu_op__fn_unit \alu_op__insn_type } + connect \pipe1_muxid$3 2'00 + connect \p_ready_o \pipe1_p_ready_o + connect \pipe1_p_valid_i \p_valid_i + connect { \pipe2_xer_so_ok \pipe2_xer_so } { \pipe1_xer_so_ok \pipe1_xer_so } + connect { \pipe2_xer_ov_ok \pipe2_xer_ov } { \pipe1_xer_ov_ok \pipe1_xer_ov } + connect { \pipe2_xer_ca_ok \pipe2_xer_ca } { \pipe1_xer_ca_ok \pipe1_xer_ca } + connect { \pipe2_cr_a_ok \pipe2_cr_a } { \pipe1_cr_a_ok \pipe1_cr_a } + connect { \pipe2_o_ok \pipe2_o } { \pipe1_o_ok \pipe1_o } + connect { \pipe2_alu_op__insn \pipe2_alu_op__data_len \pipe2_alu_op__is_signed \pipe2_alu_op__is_32bit \pipe2_alu_op__output_carry \pipe2_alu_op__input_carry \pipe2_alu_op__write_cr0 \pipe2_alu_op__invert_out \pipe2_alu_op__zero_a \pipe2_alu_op__invert_in \pipe2_alu_op__oe__ok \pipe2_alu_op__oe__oe \pipe2_alu_op__rc__ok \pipe2_alu_op__rc__rc \pipe2_alu_op__imm_data__ok \pipe2_alu_op__imm_data__data \pipe2_alu_op__fn_unit \pipe2_alu_op__insn_type } { \pipe1_alu_op__insn \pipe1_alu_op__data_len \pipe1_alu_op__is_signed \pipe1_alu_op__is_32bit \pipe1_alu_op__output_carry \pipe1_alu_op__input_carry \pipe1_alu_op__write_cr0 \pipe1_alu_op__invert_out \pipe1_alu_op__zero_a \pipe1_alu_op__invert_in \pipe1_alu_op__oe__ok \pipe1_alu_op__oe__oe \pipe1_alu_op__rc__ok \pipe1_alu_op__rc__rc \pipe1_alu_op__imm_data__ok \pipe1_alu_op__imm_data__data \pipe1_alu_op__fn_unit \pipe1_alu_op__insn_type } + connect \pipe2_muxid \pipe1_muxid + connect \pipe1_n_ready_i \pipe2_p_ready_o + connect \pipe2_p_valid_i \pipe1_n_valid_o +end +attribute \src "libresoc.v:23285.1-23820.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.alu_branch0" +attribute \generator "nMigen" +module \alu_branch0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 7 \br_op__cia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \br_op__cia$15 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 9 \br_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \br_op__fn_unit$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 11 \br_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \br_op__imm_data__data$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \br_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \br_op__imm_data__ok$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 10 \br_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \br_op__insn$18 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 8 \br_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \br_op__insn_type$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \br_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \br_op__is_32bit$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \br_op__lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \br_op__lk$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 23 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 4 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 4 input 20 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 15 \fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 18 \fast1$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 1 \fast1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 16 \fast2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 19 \fast2$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 2 \fast2_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$14 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire input 6 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire output 5 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 17 \nia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 3 \nia_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire output 22 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire input 21 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe_br_op__cia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe_br_op__cia$4 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \pipe_br_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \pipe_br_op__fn_unit$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe_br_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe_br_op__imm_data__data$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_br_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_br_op__imm_data__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe_br_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe_br_op__insn$7 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe_br_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe_br_op__insn_type$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_br_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_br_op__is_32bit$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_br_op__lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_br_op__lk$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 4 \pipe_cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \pipe_fast1$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \pipe_fast1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_fast2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \pipe_fast2$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \pipe_fast2_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \pipe_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \pipe_muxid$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire \pipe_n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire \pipe_n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \pipe_nia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \pipe_nia_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire \pipe_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire \pipe_p_valid_i + attribute \module_not_derived 1 + attribute \src "libresoc.v:23762.10-23765.4" + cell \n$18 \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:23766.10-23769.4" + cell \p$17 \p + connect \p_ready_o \p_ready_o + connect \p_valid_i \p_valid_i + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:23770.13-23804.4" + cell \pipe$19 \pipe + connect \br_op__cia \pipe_br_op__cia + connect \br_op__cia$2 \pipe_br_op__cia$4 + connect \br_op__fn_unit \pipe_br_op__fn_unit + connect \br_op__fn_unit$4 \pipe_br_op__fn_unit$6 + connect \br_op__imm_data__data \pipe_br_op__imm_data__data + connect \br_op__imm_data__data$6 \pipe_br_op__imm_data__data$8 + connect \br_op__imm_data__ok \pipe_br_op__imm_data__ok + connect \br_op__imm_data__ok$7 \pipe_br_op__imm_data__ok$9 + connect \br_op__insn \pipe_br_op__insn + connect \br_op__insn$5 \pipe_br_op__insn$7 + connect \br_op__insn_type \pipe_br_op__insn_type + connect \br_op__insn_type$3 \pipe_br_op__insn_type$5 + connect \br_op__is_32bit \pipe_br_op__is_32bit + connect \br_op__is_32bit$9 \pipe_br_op__is_32bit$11 + connect \br_op__lk \pipe_br_op__lk + connect \br_op__lk$8 \pipe_br_op__lk$10 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cr_a \pipe_cr_a + connect \fast1 \pipe_fast1 + connect \fast1$10 \pipe_fast1$12 + connect \fast1_ok \pipe_fast1_ok + connect \fast2 \pipe_fast2 + connect \fast2$11 \pipe_fast2$13 + connect \fast2_ok \pipe_fast2_ok + connect \muxid \pipe_muxid + connect \muxid$1 \pipe_muxid$3 + connect \n_ready_i \pipe_n_ready_i + connect \n_valid_o \pipe_n_valid_o + connect \nia \pipe_nia + connect \nia_ok \pipe_nia_ok + connect \p_ready_o \pipe_p_ready_o + connect \p_valid_i \pipe_p_valid_i + end + connect \muxid 2'00 + connect { \nia_ok \nia } { \pipe_nia_ok \pipe_nia } + connect { \fast2_ok \fast2 } { \pipe_fast2_ok \pipe_fast2$13 } + connect { \fast1_ok \fast1 } { \pipe_fast1_ok \pipe_fast1$12 } + connect { \br_op__is_32bit$22 \br_op__lk$21 \br_op__imm_data__ok$20 \br_op__imm_data__data$19 \br_op__insn$18 \br_op__fn_unit$17 \br_op__insn_type$16 \br_op__cia$15 } { \pipe_br_op__is_32bit$11 \pipe_br_op__lk$10 \pipe_br_op__imm_data__ok$9 \pipe_br_op__imm_data__data$8 \pipe_br_op__insn$7 \pipe_br_op__fn_unit$6 \pipe_br_op__insn_type$5 \pipe_br_op__cia$4 } + connect \muxid$14 \pipe_muxid$3 + connect \pipe_n_ready_i \n_ready_i + connect \n_valid_o \pipe_n_valid_o + connect \pipe_cr_a \cr_a + connect \pipe_fast2 \fast2$2 + connect \pipe_fast1 \fast1$1 + connect { \pipe_br_op__is_32bit \pipe_br_op__lk \pipe_br_op__imm_data__ok \pipe_br_op__imm_data__data \pipe_br_op__insn \pipe_br_op__fn_unit \pipe_br_op__insn_type \pipe_br_op__cia } { \br_op__is_32bit \br_op__lk \br_op__imm_data__ok \br_op__imm_data__data \br_op__insn \br_op__fn_unit \br_op__insn_type \br_op__cia } + connect \pipe_muxid 2'00 + connect \p_ready_o \pipe_p_ready_o + connect \pipe_p_valid_i \p_valid_i +end +attribute \src "libresoc.v:23824.1-24327.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.alu_cr0" +attribute \generator "nMigen" +module \alu_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 21 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 4 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 output 12 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 4 input 16 \cr_a$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 3 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 4 input 17 \cr_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 4 input 18 \cr_c + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 8 \cr_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \cr_op__fn_unit$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 9 \cr_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \cr_op__insn$12 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 7 \cr_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \cr_op__insn_type$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 32 output 11 \full_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 32 input 15 \full_cr$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 2 \full_cr_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$9 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire input 6 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire output 5 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 10 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 1 \o_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire output 20 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire input 19 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 4 \pipe_cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \pipe_cr_a$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \pipe_cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 4 \pipe_cr_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 4 \pipe_cr_c + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \pipe_cr_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \pipe_cr_op__fn_unit$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe_cr_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe_cr_op__insn$6 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe_cr_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe_cr_op__insn_type$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 32 \pipe_full_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 32 \pipe_full_cr$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \pipe_full_cr_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \pipe_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \pipe_muxid$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire \pipe_n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire \pipe_n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \pipe_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \pipe_o_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire \pipe_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire \pipe_p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 13 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 14 \rb + attribute \module_not_derived 1 + attribute \src "libresoc.v:24273.9-24276.4" + cell \n$6 \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:24277.9-24280.4" + cell \p$5 \p + connect \p_ready_o \p_ready_o + connect \p_valid_i \p_valid_i + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:24281.8-24308.4" + cell \pipe \pipe + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cr_a \pipe_cr_a + connect \cr_a$6 \pipe_cr_a$8 + connect \cr_a_ok \pipe_cr_a_ok + connect \cr_b \pipe_cr_b + connect \cr_c \pipe_cr_c + connect \cr_op__fn_unit \pipe_cr_op__fn_unit + connect \cr_op__fn_unit$3 \pipe_cr_op__fn_unit$5 + connect \cr_op__insn \pipe_cr_op__insn + connect \cr_op__insn$4 \pipe_cr_op__insn$6 + connect \cr_op__insn_type \pipe_cr_op__insn_type + connect \cr_op__insn_type$2 \pipe_cr_op__insn_type$4 + connect \full_cr \pipe_full_cr + connect \full_cr$5 \pipe_full_cr$7 + connect \full_cr_ok \pipe_full_cr_ok + connect \muxid \pipe_muxid + connect \muxid$1 \pipe_muxid$3 + connect \n_ready_i \pipe_n_ready_i + connect \n_valid_o \pipe_n_valid_o + connect \o \pipe_o + connect \o_ok \pipe_o_ok + connect \p_ready_o \pipe_p_ready_o + connect \p_valid_i \pipe_p_valid_i + connect \ra \pipe_ra + connect \rb \pipe_rb + end + connect \muxid 2'00 + connect { \cr_a_ok \cr_a } { \pipe_cr_a_ok \pipe_cr_a$8 } + connect { \full_cr_ok \full_cr } { \pipe_full_cr_ok \pipe_full_cr$7 } + connect { \o_ok \o } { \pipe_o_ok \pipe_o } + connect { \cr_op__insn$12 \cr_op__fn_unit$11 \cr_op__insn_type$10 } { \pipe_cr_op__insn$6 \pipe_cr_op__fn_unit$5 \pipe_cr_op__insn_type$4 } + connect \muxid$9 \pipe_muxid$3 + connect \pipe_n_ready_i \n_ready_i + connect \n_valid_o \pipe_n_valid_o + connect \pipe_cr_c \cr_c + connect \pipe_cr_b \cr_b + connect \pipe_cr_a \cr_a$2 + connect \pipe_full_cr \full_cr$1 + connect \pipe_rb \rb + connect \pipe_ra \ra + connect { \pipe_cr_op__insn \pipe_cr_op__fn_unit \pipe_cr_op__insn_type } { \cr_op__insn \cr_op__fn_unit \cr_op__insn_type } + connect \pipe_muxid 2'00 + connect \p_ready_o \pipe_p_ready_o + connect \pipe_p_valid_i \p_valid_i +end +attribute \src "libresoc.v:24331.1-25772.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0" +attribute \generator "nMigen" +module \alu_div0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 35 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 5 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 output 27 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 2 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 24 \logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \logical_op__data_len$88 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 9 \logical_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \logical_op__fn_unit$73 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 10 \logical_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \logical_op__imm_data__data$74 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 11 \logical_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__imm_data__ok$75 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 18 \logical_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \logical_op__input_carry$82 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 25 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \logical_op__insn$89 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 8 \logical_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \logical_op__insn_type$72 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 16 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_in$80 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 19 \logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_out$83 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 22 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_32bit$86 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 23 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_signed$87 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__oe$78 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 15 \logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__ok$79 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 21 \logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__output_carry$85 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__ok$77 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__rc$76 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 20 \logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__write_cr0$84 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 17 \logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__zero_a$81 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$71 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire input 7 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire output 6 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 26 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 1 \o_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire output 34 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire input 33 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \pipe_end_cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \pipe_end_cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire \pipe_end_div_by_zero + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire \pipe_end_dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire \pipe_end_dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire \pipe_end_dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire \pipe_end_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \pipe_end_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \pipe_end_logical_op__data_len$68 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \pipe_end_logical_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \pipe_end_logical_op__fn_unit$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe_end_logical_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe_end_logical_op__imm_data__data$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_end_logical_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_end_logical_op__imm_data__ok$55 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \pipe_end_logical_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \pipe_end_logical_op__input_carry$62 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe_end_logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe_end_logical_op__insn$69 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe_end_logical_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe_end_logical_op__insn_type$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_end_logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_end_logical_op__invert_in$60 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_end_logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_end_logical_op__invert_out$63 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_end_logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_end_logical_op__is_32bit$66 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_end_logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_end_logical_op__is_signed$67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_end_logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_end_logical_op__oe__oe$58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_end_logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_end_logical_op__oe__ok$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_end_logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_end_logical_op__output_carry$65 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_end_logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_end_logical_op__rc__ok$57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_end_logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_end_logical_op__rc__rc$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_end_logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_end_logical_op__write_cr0$64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_end_logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_end_logical_op__zero_a$61 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \pipe_end_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \pipe_end_muxid$51 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire \pipe_end_n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire \pipe_end_n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \pipe_end_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \pipe_end_o_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire \pipe_end_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire \pipe_end_p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" + wire width 64 \pipe_end_quotient_root + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_end_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_end_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:41" + wire width 192 \pipe_end_remainder + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \pipe_end_xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \pipe_end_xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \pipe_end_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \pipe_end_xer_so$70 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \pipe_end_xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire \pipe_middle_0_div_by_zero + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire \pipe_middle_0_div_by_zero$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire \pipe_middle_0_dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire \pipe_middle_0_dive_abs_ov32$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire \pipe_middle_0_dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire \pipe_middle_0_dive_abs_ov64$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" + wire width 128 \pipe_middle_0_dividend + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire \pipe_middle_0_dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire \pipe_middle_0_dividend_neg$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire \pipe_middle_0_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire \pipe_middle_0_divisor_neg$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" + wire width 64 \pipe_middle_0_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \pipe_middle_0_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \pipe_middle_0_logical_op__data_len$41 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \pipe_middle_0_logical_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \pipe_middle_0_logical_op__fn_unit$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe_middle_0_logical_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe_middle_0_logical_op__imm_data__data$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_middle_0_logical_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_middle_0_logical_op__imm_data__ok$28 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \pipe_middle_0_logical_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \pipe_middle_0_logical_op__input_carry$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe_middle_0_logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe_middle_0_logical_op__insn$42 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe_middle_0_logical_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe_middle_0_logical_op__insn_type$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_middle_0_logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_middle_0_logical_op__invert_in$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_middle_0_logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_middle_0_logical_op__invert_out$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_middle_0_logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_middle_0_logical_op__is_32bit$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_middle_0_logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_middle_0_logical_op__is_signed$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_middle_0_logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_middle_0_logical_op__oe__oe$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_middle_0_logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_middle_0_logical_op__oe__ok$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_middle_0_logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_middle_0_logical_op__output_carry$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_middle_0_logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_middle_0_logical_op__rc__ok$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_middle_0_logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_middle_0_logical_op__rc__rc$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_middle_0_logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_middle_0_logical_op__write_cr0$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_middle_0_logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_middle_0_logical_op__zero_a$34 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \pipe_middle_0_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \pipe_middle_0_muxid$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire \pipe_middle_0_n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire \pipe_middle_0_n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" + wire width 2 \pipe_middle_0_operation + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire \pipe_middle_0_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire \pipe_middle_0_p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" + wire width 64 \pipe_middle_0_quotient_root + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_middle_0_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_middle_0_ra$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_middle_0_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_middle_0_rb$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:41" + wire width 192 \pipe_middle_0_remainder + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \pipe_middle_0_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \pipe_middle_0_xer_so$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire \pipe_start_div_by_zero + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire \pipe_start_dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire \pipe_start_dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" + wire width 128 \pipe_start_dividend + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire \pipe_start_dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire \pipe_start_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" + wire width 64 \pipe_start_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \pipe_start_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \pipe_start_logical_op__data_len$19 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \pipe_start_logical_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \pipe_start_logical_op__fn_unit$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe_start_logical_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe_start_logical_op__imm_data__data$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_start_logical_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_start_logical_op__imm_data__ok$6 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \pipe_start_logical_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \pipe_start_logical_op__input_carry$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe_start_logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe_start_logical_op__insn$20 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe_start_logical_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe_start_logical_op__insn_type$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_start_logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_start_logical_op__invert_in$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_start_logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_start_logical_op__invert_out$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_start_logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_start_logical_op__is_32bit$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_start_logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_start_logical_op__is_signed$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_start_logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_start_logical_op__oe__oe$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_start_logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_start_logical_op__oe__ok$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_start_logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_start_logical_op__output_carry$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_start_logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_start_logical_op__rc__ok$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_start_logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_start_logical_op__rc__rc$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_start_logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_start_logical_op__write_cr0$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_start_logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_start_logical_op__zero_a$12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \pipe_start_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \pipe_start_muxid$2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire \pipe_start_n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire \pipe_start_n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" + wire width 2 \pipe_start_operation + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire \pipe_start_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire \pipe_start_p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_start_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_start_ra$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_start_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_start_rb$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \pipe_start_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \pipe_start_xer_so$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 30 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 31 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 output 28 \xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 3 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 29 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 32 \xer_so$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 4 \xer_so_ok + attribute \module_not_derived 1 + attribute \src "libresoc.v:25528.10-25531.4" + cell \n$72 \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:25532.10-25535.4" + cell \p$71 \p + connect \p_ready_o \p_ready_o + connect \p_valid_i \p_valid_i + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:25536.12-25599.4" + cell \pipe_end \pipe_end + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cr_a \pipe_end_cr_a + connect \cr_a_ok \pipe_end_cr_a_ok + connect \div_by_zero \pipe_end_div_by_zero + connect \dive_abs_ov32 \pipe_end_dive_abs_ov32 + connect \dive_abs_ov64 \pipe_end_dive_abs_ov64 + connect \dividend_neg \pipe_end_dividend_neg + connect \divisor_neg \pipe_end_divisor_neg + connect \logical_op__data_len \pipe_end_logical_op__data_len + connect \logical_op__data_len$18 \pipe_end_logical_op__data_len$68 + connect \logical_op__fn_unit \pipe_end_logical_op__fn_unit + connect \logical_op__fn_unit$3 \pipe_end_logical_op__fn_unit$53 + connect \logical_op__imm_data__data \pipe_end_logical_op__imm_data__data + connect \logical_op__imm_data__data$4 \pipe_end_logical_op__imm_data__data$54 + connect \logical_op__imm_data__ok \pipe_end_logical_op__imm_data__ok + connect \logical_op__imm_data__ok$5 \pipe_end_logical_op__imm_data__ok$55 + connect \logical_op__input_carry \pipe_end_logical_op__input_carry + connect \logical_op__input_carry$12 \pipe_end_logical_op__input_carry$62 + connect \logical_op__insn \pipe_end_logical_op__insn + connect \logical_op__insn$19 \pipe_end_logical_op__insn$69 + connect \logical_op__insn_type \pipe_end_logical_op__insn_type + connect \logical_op__insn_type$2 \pipe_end_logical_op__insn_type$52 + connect \logical_op__invert_in \pipe_end_logical_op__invert_in + connect \logical_op__invert_in$10 \pipe_end_logical_op__invert_in$60 + connect \logical_op__invert_out \pipe_end_logical_op__invert_out + connect \logical_op__invert_out$13 \pipe_end_logical_op__invert_out$63 + connect \logical_op__is_32bit \pipe_end_logical_op__is_32bit + connect \logical_op__is_32bit$16 \pipe_end_logical_op__is_32bit$66 + connect \logical_op__is_signed \pipe_end_logical_op__is_signed + connect \logical_op__is_signed$17 \pipe_end_logical_op__is_signed$67 + connect \logical_op__oe__oe \pipe_end_logical_op__oe__oe + connect \logical_op__oe__oe$8 \pipe_end_logical_op__oe__oe$58 + connect \logical_op__oe__ok \pipe_end_logical_op__oe__ok + connect \logical_op__oe__ok$9 \pipe_end_logical_op__oe__ok$59 + connect \logical_op__output_carry \pipe_end_logical_op__output_carry + connect \logical_op__output_carry$15 \pipe_end_logical_op__output_carry$65 + connect \logical_op__rc__ok \pipe_end_logical_op__rc__ok + connect \logical_op__rc__ok$7 \pipe_end_logical_op__rc__ok$57 + connect \logical_op__rc__rc \pipe_end_logical_op__rc__rc + connect \logical_op__rc__rc$6 \pipe_end_logical_op__rc__rc$56 + connect \logical_op__write_cr0 \pipe_end_logical_op__write_cr0 + connect \logical_op__write_cr0$14 \pipe_end_logical_op__write_cr0$64 + connect \logical_op__zero_a \pipe_end_logical_op__zero_a + connect \logical_op__zero_a$11 \pipe_end_logical_op__zero_a$61 + connect \muxid \pipe_end_muxid + connect \muxid$1 \pipe_end_muxid$51 + connect \n_ready_i \pipe_end_n_ready_i + connect \n_valid_o \pipe_end_n_valid_o + connect \o \pipe_end_o + connect \o_ok \pipe_end_o_ok + connect \p_ready_o \pipe_end_p_ready_o + connect \p_valid_i \pipe_end_p_valid_i + connect \quotient_root \pipe_end_quotient_root + connect \ra \pipe_end_ra + connect \rb \pipe_end_rb + connect \remainder \pipe_end_remainder + connect \xer_ov \pipe_end_xer_ov + connect \xer_ov_ok \pipe_end_xer_ov_ok + connect \xer_so \pipe_end_xer_so + connect \xer_so$20 \pipe_end_xer_so$70 + connect \xer_so_ok \pipe_end_xer_so_ok + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:25600.17-25666.4" + cell \pipe_middle_0 \pipe_middle_0 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \div_by_zero \pipe_middle_0_div_by_zero + connect \div_by_zero$27 \pipe_middle_0_div_by_zero$50 + connect \dive_abs_ov32 \pipe_middle_0_dive_abs_ov32 + connect \dive_abs_ov32$25 \pipe_middle_0_dive_abs_ov32$48 + connect \dive_abs_ov64 \pipe_middle_0_dive_abs_ov64 + connect \dive_abs_ov64$26 \pipe_middle_0_dive_abs_ov64$49 + connect \dividend \pipe_middle_0_dividend + connect \dividend_neg \pipe_middle_0_dividend_neg + connect \dividend_neg$24 \pipe_middle_0_dividend_neg$47 + connect \divisor_neg \pipe_middle_0_divisor_neg + connect \divisor_neg$23 \pipe_middle_0_divisor_neg$46 + connect \divisor_radicand \pipe_middle_0_divisor_radicand + connect \logical_op__data_len \pipe_middle_0_logical_op__data_len + connect \logical_op__data_len$18 \pipe_middle_0_logical_op__data_len$41 + connect \logical_op__fn_unit \pipe_middle_0_logical_op__fn_unit + connect \logical_op__fn_unit$3 \pipe_middle_0_logical_op__fn_unit$26 + connect \logical_op__imm_data__data \pipe_middle_0_logical_op__imm_data__data + connect \logical_op__imm_data__data$4 \pipe_middle_0_logical_op__imm_data__data$27 + connect \logical_op__imm_data__ok \pipe_middle_0_logical_op__imm_data__ok + connect \logical_op__imm_data__ok$5 \pipe_middle_0_logical_op__imm_data__ok$28 + connect \logical_op__input_carry \pipe_middle_0_logical_op__input_carry + connect \logical_op__input_carry$12 \pipe_middle_0_logical_op__input_carry$35 + connect \logical_op__insn \pipe_middle_0_logical_op__insn + connect \logical_op__insn$19 \pipe_middle_0_logical_op__insn$42 + connect \logical_op__insn_type \pipe_middle_0_logical_op__insn_type + connect \logical_op__insn_type$2 \pipe_middle_0_logical_op__insn_type$25 + connect \logical_op__invert_in \pipe_middle_0_logical_op__invert_in + connect \logical_op__invert_in$10 \pipe_middle_0_logical_op__invert_in$33 + connect \logical_op__invert_out \pipe_middle_0_logical_op__invert_out + connect \logical_op__invert_out$13 \pipe_middle_0_logical_op__invert_out$36 + connect \logical_op__is_32bit \pipe_middle_0_logical_op__is_32bit + connect \logical_op__is_32bit$16 \pipe_middle_0_logical_op__is_32bit$39 + connect \logical_op__is_signed \pipe_middle_0_logical_op__is_signed + connect \logical_op__is_signed$17 \pipe_middle_0_logical_op__is_signed$40 + connect \logical_op__oe__oe \pipe_middle_0_logical_op__oe__oe + connect \logical_op__oe__oe$8 \pipe_middle_0_logical_op__oe__oe$31 + connect \logical_op__oe__ok \pipe_middle_0_logical_op__oe__ok + connect \logical_op__oe__ok$9 \pipe_middle_0_logical_op__oe__ok$32 + connect \logical_op__output_carry \pipe_middle_0_logical_op__output_carry + connect \logical_op__output_carry$15 \pipe_middle_0_logical_op__output_carry$38 + connect \logical_op__rc__ok \pipe_middle_0_logical_op__rc__ok + connect \logical_op__rc__ok$7 \pipe_middle_0_logical_op__rc__ok$30 + connect \logical_op__rc__rc \pipe_middle_0_logical_op__rc__rc + connect \logical_op__rc__rc$6 \pipe_middle_0_logical_op__rc__rc$29 + connect \logical_op__write_cr0 \pipe_middle_0_logical_op__write_cr0 + connect \logical_op__write_cr0$14 \pipe_middle_0_logical_op__write_cr0$37 + connect \logical_op__zero_a \pipe_middle_0_logical_op__zero_a + connect \logical_op__zero_a$11 \pipe_middle_0_logical_op__zero_a$34 + connect \muxid \pipe_middle_0_muxid + connect \muxid$1 \pipe_middle_0_muxid$24 + connect \n_ready_i \pipe_middle_0_n_ready_i + connect \n_valid_o \pipe_middle_0_n_valid_o + connect \operation \pipe_middle_0_operation + connect \p_ready_o \pipe_middle_0_p_ready_o + connect \p_valid_i \pipe_middle_0_p_valid_i + connect \quotient_root \pipe_middle_0_quotient_root + connect \ra \pipe_middle_0_ra + connect \ra$20 \pipe_middle_0_ra$43 + connect \rb \pipe_middle_0_rb + connect \rb$21 \pipe_middle_0_rb$44 + connect \remainder \pipe_middle_0_remainder + connect \xer_so \pipe_middle_0_xer_so + connect \xer_so$22 \pipe_middle_0_xer_so$45 + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:25667.14-25726.4" + cell \pipe_start \pipe_start + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \div_by_zero \pipe_start_div_by_zero + connect \dive_abs_ov32 \pipe_start_dive_abs_ov32 + connect \dive_abs_ov64 \pipe_start_dive_abs_ov64 + connect \dividend \pipe_start_dividend + connect \dividend_neg \pipe_start_dividend_neg + connect \divisor_neg \pipe_start_divisor_neg + connect \divisor_radicand \pipe_start_divisor_radicand + connect \logical_op__data_len \pipe_start_logical_op__data_len + connect \logical_op__data_len$18 \pipe_start_logical_op__data_len$19 + connect \logical_op__fn_unit \pipe_start_logical_op__fn_unit + connect \logical_op__fn_unit$3 \pipe_start_logical_op__fn_unit$4 + connect \logical_op__imm_data__data \pipe_start_logical_op__imm_data__data + connect \logical_op__imm_data__data$4 \pipe_start_logical_op__imm_data__data$5 + connect \logical_op__imm_data__ok \pipe_start_logical_op__imm_data__ok + connect \logical_op__imm_data__ok$5 \pipe_start_logical_op__imm_data__ok$6 + connect \logical_op__input_carry \pipe_start_logical_op__input_carry + connect \logical_op__input_carry$12 \pipe_start_logical_op__input_carry$13 + connect \logical_op__insn \pipe_start_logical_op__insn + connect \logical_op__insn$19 \pipe_start_logical_op__insn$20 + connect \logical_op__insn_type \pipe_start_logical_op__insn_type + connect \logical_op__insn_type$2 \pipe_start_logical_op__insn_type$3 + connect \logical_op__invert_in \pipe_start_logical_op__invert_in + connect \logical_op__invert_in$10 \pipe_start_logical_op__invert_in$11 + connect \logical_op__invert_out \pipe_start_logical_op__invert_out + connect \logical_op__invert_out$13 \pipe_start_logical_op__invert_out$14 + connect \logical_op__is_32bit \pipe_start_logical_op__is_32bit + connect \logical_op__is_32bit$16 \pipe_start_logical_op__is_32bit$17 + connect \logical_op__is_signed \pipe_start_logical_op__is_signed + connect \logical_op__is_signed$17 \pipe_start_logical_op__is_signed$18 + connect \logical_op__oe__oe \pipe_start_logical_op__oe__oe + connect \logical_op__oe__oe$8 \pipe_start_logical_op__oe__oe$9 + connect \logical_op__oe__ok \pipe_start_logical_op__oe__ok + connect \logical_op__oe__ok$9 \pipe_start_logical_op__oe__ok$10 + connect \logical_op__output_carry \pipe_start_logical_op__output_carry + connect \logical_op__output_carry$15 \pipe_start_logical_op__output_carry$16 + connect \logical_op__rc__ok \pipe_start_logical_op__rc__ok + connect \logical_op__rc__ok$7 \pipe_start_logical_op__rc__ok$8 + connect \logical_op__rc__rc \pipe_start_logical_op__rc__rc + connect \logical_op__rc__rc$6 \pipe_start_logical_op__rc__rc$7 + connect \logical_op__write_cr0 \pipe_start_logical_op__write_cr0 + connect \logical_op__write_cr0$14 \pipe_start_logical_op__write_cr0$15 + connect \logical_op__zero_a \pipe_start_logical_op__zero_a + connect \logical_op__zero_a$11 \pipe_start_logical_op__zero_a$12 + connect \muxid \pipe_start_muxid + connect \muxid$1 \pipe_start_muxid$2 + connect \n_ready_i \pipe_start_n_ready_i + connect \n_valid_o \pipe_start_n_valid_o + connect \operation \pipe_start_operation + connect \p_ready_o \pipe_start_p_ready_o + connect \p_valid_i \pipe_start_p_valid_i + connect \ra \pipe_start_ra + connect \ra$20 \pipe_start_ra$21 + connect \rb \pipe_start_rb + connect \rb$21 \pipe_start_rb$22 + connect \xer_so \pipe_start_xer_so + connect \xer_so$22 \pipe_start_xer_so$23 + end + connect \muxid 2'00 + connect { \xer_so_ok \xer_so } { \pipe_end_xer_so_ok \pipe_end_xer_so$70 } + connect { \xer_ov_ok \xer_ov } { \pipe_end_xer_ov_ok \pipe_end_xer_ov } + connect { \cr_a_ok \cr_a } { \pipe_end_cr_a_ok \pipe_end_cr_a } + connect { \o_ok \o } { \pipe_end_o_ok \pipe_end_o } + connect { \logical_op__insn$89 \logical_op__data_len$88 \logical_op__is_signed$87 \logical_op__is_32bit$86 \logical_op__output_carry$85 \logical_op__write_cr0$84 \logical_op__invert_out$83 \logical_op__input_carry$82 \logical_op__zero_a$81 \logical_op__invert_in$80 \logical_op__oe__ok$79 \logical_op__oe__oe$78 \logical_op__rc__ok$77 \logical_op__rc__rc$76 \logical_op__imm_data__ok$75 \logical_op__imm_data__data$74 \logical_op__fn_unit$73 \logical_op__insn_type$72 } { \pipe_end_logical_op__insn$69 \pipe_end_logical_op__data_len$68 \pipe_end_logical_op__is_signed$67 \pipe_end_logical_op__is_32bit$66 \pipe_end_logical_op__output_carry$65 \pipe_end_logical_op__write_cr0$64 \pipe_end_logical_op__invert_out$63 \pipe_end_logical_op__input_carry$62 \pipe_end_logical_op__zero_a$61 \pipe_end_logical_op__invert_in$60 \pipe_end_logical_op__oe__ok$59 \pipe_end_logical_op__oe__oe$58 \pipe_end_logical_op__rc__ok$57 \pipe_end_logical_op__rc__rc$56 \pipe_end_logical_op__imm_data__ok$55 \pipe_end_logical_op__imm_data__data$54 \pipe_end_logical_op__fn_unit$53 \pipe_end_logical_op__insn_type$52 } + connect \muxid$71 \pipe_end_muxid$51 + connect \pipe_end_n_ready_i \n_ready_i + connect \n_valid_o \pipe_end_n_valid_o + connect \pipe_start_xer_so$23 \xer_so$1 + connect \pipe_start_rb$22 \rb + connect \pipe_start_ra$21 \ra + connect { \pipe_start_logical_op__insn$20 \pipe_start_logical_op__data_len$19 \pipe_start_logical_op__is_signed$18 \pipe_start_logical_op__is_32bit$17 \pipe_start_logical_op__output_carry$16 \pipe_start_logical_op__write_cr0$15 \pipe_start_logical_op__invert_out$14 \pipe_start_logical_op__input_carry$13 \pipe_start_logical_op__zero_a$12 \pipe_start_logical_op__invert_in$11 \pipe_start_logical_op__oe__ok$10 \pipe_start_logical_op__oe__oe$9 \pipe_start_logical_op__rc__ok$8 \pipe_start_logical_op__rc__rc$7 \pipe_start_logical_op__imm_data__ok$6 \pipe_start_logical_op__imm_data__data$5 \pipe_start_logical_op__fn_unit$4 \pipe_start_logical_op__insn_type$3 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } + connect \pipe_start_muxid$2 2'00 + connect \p_ready_o \pipe_start_p_ready_o + connect \pipe_start_p_valid_i \p_valid_i + connect \pipe_end_remainder \pipe_middle_0_remainder + connect \pipe_end_quotient_root \pipe_middle_0_quotient_root + connect \pipe_end_div_by_zero \pipe_middle_0_div_by_zero$50 + connect \pipe_end_dive_abs_ov64 \pipe_middle_0_dive_abs_ov64$49 + connect \pipe_end_dive_abs_ov32 \pipe_middle_0_dive_abs_ov32$48 + connect \pipe_end_dividend_neg \pipe_middle_0_dividend_neg$47 + connect \pipe_end_divisor_neg \pipe_middle_0_divisor_neg$46 + connect \pipe_end_xer_so \pipe_middle_0_xer_so$45 + connect \pipe_end_rb \pipe_middle_0_rb$44 + connect \pipe_end_ra \pipe_middle_0_ra$43 + connect { \pipe_end_logical_op__insn \pipe_end_logical_op__data_len \pipe_end_logical_op__is_signed \pipe_end_logical_op__is_32bit \pipe_end_logical_op__output_carry \pipe_end_logical_op__write_cr0 \pipe_end_logical_op__invert_out \pipe_end_logical_op__input_carry \pipe_end_logical_op__zero_a \pipe_end_logical_op__invert_in \pipe_end_logical_op__oe__ok \pipe_end_logical_op__oe__oe \pipe_end_logical_op__rc__ok \pipe_end_logical_op__rc__rc \pipe_end_logical_op__imm_data__ok \pipe_end_logical_op__imm_data__data \pipe_end_logical_op__fn_unit \pipe_end_logical_op__insn_type } { \pipe_middle_0_logical_op__insn$42 \pipe_middle_0_logical_op__data_len$41 \pipe_middle_0_logical_op__is_signed$40 \pipe_middle_0_logical_op__is_32bit$39 \pipe_middle_0_logical_op__output_carry$38 \pipe_middle_0_logical_op__write_cr0$37 \pipe_middle_0_logical_op__invert_out$36 \pipe_middle_0_logical_op__input_carry$35 \pipe_middle_0_logical_op__zero_a$34 \pipe_middle_0_logical_op__invert_in$33 \pipe_middle_0_logical_op__oe__ok$32 \pipe_middle_0_logical_op__oe__oe$31 \pipe_middle_0_logical_op__rc__ok$30 \pipe_middle_0_logical_op__rc__rc$29 \pipe_middle_0_logical_op__imm_data__ok$28 \pipe_middle_0_logical_op__imm_data__data$27 \pipe_middle_0_logical_op__fn_unit$26 \pipe_middle_0_logical_op__insn_type$25 } + connect \pipe_end_muxid \pipe_middle_0_muxid$24 + connect \pipe_middle_0_n_ready_i \pipe_end_p_ready_o + connect \pipe_end_p_valid_i \pipe_middle_0_n_valid_o + connect \pipe_middle_0_operation \pipe_start_operation + connect \pipe_middle_0_divisor_radicand \pipe_start_divisor_radicand + connect \pipe_middle_0_dividend \pipe_start_dividend + connect \pipe_middle_0_div_by_zero \pipe_start_div_by_zero + connect \pipe_middle_0_dive_abs_ov64 \pipe_start_dive_abs_ov64 + connect \pipe_middle_0_dive_abs_ov32 \pipe_start_dive_abs_ov32 + connect \pipe_middle_0_dividend_neg \pipe_start_dividend_neg + connect \pipe_middle_0_divisor_neg \pipe_start_divisor_neg + connect \pipe_middle_0_xer_so \pipe_start_xer_so + connect \pipe_middle_0_rb \pipe_start_rb + connect \pipe_middle_0_ra \pipe_start_ra + connect { \pipe_middle_0_logical_op__insn \pipe_middle_0_logical_op__data_len \pipe_middle_0_logical_op__is_signed \pipe_middle_0_logical_op__is_32bit \pipe_middle_0_logical_op__output_carry \pipe_middle_0_logical_op__write_cr0 \pipe_middle_0_logical_op__invert_out \pipe_middle_0_logical_op__input_carry \pipe_middle_0_logical_op__zero_a \pipe_middle_0_logical_op__invert_in \pipe_middle_0_logical_op__oe__ok \pipe_middle_0_logical_op__oe__oe \pipe_middle_0_logical_op__rc__ok \pipe_middle_0_logical_op__rc__rc \pipe_middle_0_logical_op__imm_data__ok \pipe_middle_0_logical_op__imm_data__data \pipe_middle_0_logical_op__fn_unit \pipe_middle_0_logical_op__insn_type } { \pipe_start_logical_op__insn \pipe_start_logical_op__data_len \pipe_start_logical_op__is_signed \pipe_start_logical_op__is_32bit \pipe_start_logical_op__output_carry \pipe_start_logical_op__write_cr0 \pipe_start_logical_op__invert_out \pipe_start_logical_op__input_carry \pipe_start_logical_op__zero_a \pipe_start_logical_op__invert_in \pipe_start_logical_op__oe__ok \pipe_start_logical_op__oe__oe \pipe_start_logical_op__rc__ok \pipe_start_logical_op__rc__rc \pipe_start_logical_op__imm_data__ok \pipe_start_logical_op__imm_data__data \pipe_start_logical_op__fn_unit \pipe_start_logical_op__insn_type } + connect \pipe_middle_0_muxid \pipe_start_muxid + connect \pipe_start_n_ready_i \pipe_middle_0_p_ready_o + connect \pipe_middle_0_p_valid_i \pipe_start_n_valid_o +end +attribute \src "libresoc.v:25776.1-25834.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alu_l" +attribute \generator "nMigen" +module \alu_l + attribute \src "libresoc.v:25777.7-25777.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:25822.3-25830.6" + wire $0\q_int$next[0:0]$860 + attribute \src "libresoc.v:25820.3-25821.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:25822.3-25830.6" + wire $1\q_int$next[0:0]$861 + attribute \src "libresoc.v:25801.7-25801.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:25812.17-25812.96" + wire $and$libresoc.v:25812$850_Y + attribute \src "libresoc.v:25817.17-25817.96" + wire $and$libresoc.v:25817$855_Y + attribute \src "libresoc.v:25814.18-25814.93" + wire $not$libresoc.v:25814$852_Y + attribute \src "libresoc.v:25816.17-25816.92" + wire $not$libresoc.v:25816$854_Y + attribute \src "libresoc.v:25819.17-25819.92" + wire $not$libresoc.v:25819$857_Y + attribute \src "libresoc.v:25813.18-25813.98" + wire $or$libresoc.v:25813$851_Y + attribute \src "libresoc.v:25815.18-25815.99" + wire $or$libresoc.v:25815$853_Y + attribute \src "libresoc.v:25818.17-25818.97" + wire $or$libresoc.v:25818$856_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 1 \coresync_rst + attribute \src "libresoc.v:25777.7-25777.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 2 \q_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 4 \s_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$libresoc.v:25812$850 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:25812$850_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:25817$855 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:25817$855_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:25814$852 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alu + connect \Y $not$libresoc.v:25814$852_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:25816$854 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alu + connect \Y $not$libresoc.v:25816$854_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:25819$857 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alu + connect \Y $not$libresoc.v:25819$857_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:25813$851 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_alu + connect \Y $or$libresoc.v:25813$851_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:25815$853 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alu + connect \B \q_int + connect \Y $or$libresoc.v:25815$853_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:25818$856 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_alu + connect \Y $or$libresoc.v:25818$856_Y + end + attribute \src "libresoc.v:25777.7-25777.20" + process $proc$libresoc.v:25777$862 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:25801.7-25801.19" + process $proc$libresoc.v:25801$863 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:25820.3-25821.27" + process $proc$libresoc.v:25820$858 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:25822.3-25830.6" + process $proc$libresoc.v:25822$859 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$860 $1\q_int$next[0:0]$861 + attribute \src "libresoc.v:25823.5-25823.29" + switch \initial + attribute \src "libresoc.v:25823.9-25823.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$861 1'0 + case + assign $1\q_int$next[0:0]$861 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$860 + end + connect \$9 $and$libresoc.v:25812$850_Y + connect \$11 $or$libresoc.v:25813$851_Y + connect \$13 $not$libresoc.v:25814$852_Y + connect \$15 $or$libresoc.v:25815$853_Y + connect \$1 $not$libresoc.v:25816$854_Y + connect \$3 $and$libresoc.v:25817$855_Y + connect \$5 $or$libresoc.v:25818$856_Y + connect \$7 $not$libresoc.v:25819$857_Y + connect \qlq_alu \$15 + connect \qn_alu \$13 + connect \q_alu \$11 +end +attribute \src "libresoc.v:25838.1-25896.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_l" +attribute \generator "nMigen" +module \alu_l$104 + attribute \src "libresoc.v:25839.7-25839.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:25884.3-25892.6" + wire $0\q_int$next[0:0]$874 + attribute \src "libresoc.v:25882.3-25883.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:25884.3-25892.6" + wire $1\q_int$next[0:0]$875 + attribute \src "libresoc.v:25863.7-25863.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:25874.17-25874.96" + wire $and$libresoc.v:25874$864_Y + attribute \src "libresoc.v:25879.17-25879.96" + wire $and$libresoc.v:25879$869_Y + attribute \src "libresoc.v:25876.18-25876.93" + wire $not$libresoc.v:25876$866_Y + attribute \src "libresoc.v:25878.17-25878.92" + wire $not$libresoc.v:25878$868_Y + attribute \src "libresoc.v:25881.17-25881.92" + wire $not$libresoc.v:25881$871_Y + attribute \src "libresoc.v:25875.18-25875.98" + wire $or$libresoc.v:25875$865_Y + attribute \src "libresoc.v:25877.18-25877.99" + wire $or$libresoc.v:25877$867_Y + attribute \src "libresoc.v:25880.17-25880.97" + wire $or$libresoc.v:25880$870_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 1 \coresync_rst + attribute \src "libresoc.v:25839.7-25839.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 2 \q_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 4 \s_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$libresoc.v:25874$864 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:25874$864_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:25879$869 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:25879$869_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:25876$866 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alu + connect \Y $not$libresoc.v:25876$866_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:25878$868 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alu + connect \Y $not$libresoc.v:25878$868_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:25881$871 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alu + connect \Y $not$libresoc.v:25881$871_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:25875$865 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_alu + connect \Y $or$libresoc.v:25875$865_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:25877$867 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alu + connect \B \q_int + connect \Y $or$libresoc.v:25877$867_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:25880$870 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_alu + connect \Y $or$libresoc.v:25880$870_Y + end + attribute \src "libresoc.v:25839.7-25839.20" + process $proc$libresoc.v:25839$876 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:25863.7-25863.19" + process $proc$libresoc.v:25863$877 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:25882.3-25883.27" + process $proc$libresoc.v:25882$872 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:25884.3-25892.6" + process $proc$libresoc.v:25884$873 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$874 $1\q_int$next[0:0]$875 + attribute \src "libresoc.v:25885.5-25885.29" + switch \initial + attribute \src "libresoc.v:25885.9-25885.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$875 1'0 + case + assign $1\q_int$next[0:0]$875 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$874 + end + connect \$9 $and$libresoc.v:25874$864_Y + connect \$11 $or$libresoc.v:25875$865_Y + connect \$13 $not$libresoc.v:25876$866_Y + connect \$15 $or$libresoc.v:25877$867_Y + connect \$1 $not$libresoc.v:25878$868_Y + connect \$3 $and$libresoc.v:25879$869_Y + connect \$5 $or$libresoc.v:25880$870_Y + connect \$7 $not$libresoc.v:25881$871_Y + connect \qlq_alu \$15 + connect \qn_alu \$13 + connect \q_alu \$11 +end +attribute \src "libresoc.v:25900.1-25958.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_l" +attribute \generator "nMigen" +module \alu_l$122 + attribute \src "libresoc.v:25901.7-25901.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:25946.3-25954.6" + wire $0\q_int$next[0:0]$888 + attribute \src "libresoc.v:25944.3-25945.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:25946.3-25954.6" + wire $1\q_int$next[0:0]$889 + attribute \src "libresoc.v:25925.7-25925.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:25936.17-25936.96" + wire $and$libresoc.v:25936$878_Y + attribute \src "libresoc.v:25941.17-25941.96" + wire $and$libresoc.v:25941$883_Y + attribute \src "libresoc.v:25938.18-25938.93" + wire $not$libresoc.v:25938$880_Y + attribute \src "libresoc.v:25940.17-25940.92" + wire $not$libresoc.v:25940$882_Y + attribute \src "libresoc.v:25943.17-25943.92" + wire $not$libresoc.v:25943$885_Y + attribute \src "libresoc.v:25937.18-25937.98" + wire $or$libresoc.v:25937$879_Y + attribute \src "libresoc.v:25939.18-25939.99" + wire $or$libresoc.v:25939$881_Y + attribute \src "libresoc.v:25942.17-25942.97" + wire $or$libresoc.v:25942$884_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 1 \coresync_rst + attribute \src "libresoc.v:25901.7-25901.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 2 \q_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 4 \s_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$libresoc.v:25936$878 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:25936$878_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:25941$883 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:25941$883_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:25938$880 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alu + connect \Y $not$libresoc.v:25938$880_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:25940$882 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alu + connect \Y $not$libresoc.v:25940$882_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:25943$885 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alu + connect \Y $not$libresoc.v:25943$885_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:25937$879 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_alu + connect \Y $or$libresoc.v:25937$879_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:25939$881 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alu + connect \B \q_int + connect \Y $or$libresoc.v:25939$881_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:25942$884 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_alu + connect \Y $or$libresoc.v:25942$884_Y + end + attribute \src "libresoc.v:25901.7-25901.20" + process $proc$libresoc.v:25901$890 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:25925.7-25925.19" + process $proc$libresoc.v:25925$891 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:25944.3-25945.27" + process $proc$libresoc.v:25944$886 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:25946.3-25954.6" + process $proc$libresoc.v:25946$887 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$888 $1\q_int$next[0:0]$889 + attribute \src "libresoc.v:25947.5-25947.29" + switch \initial + attribute \src "libresoc.v:25947.9-25947.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$889 1'0 + case + assign $1\q_int$next[0:0]$889 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$888 + end + connect \$9 $and$libresoc.v:25936$878_Y + connect \$11 $or$libresoc.v:25937$879_Y + connect \$13 $not$libresoc.v:25938$880_Y + connect \$15 $or$libresoc.v:25939$881_Y + connect \$1 $not$libresoc.v:25940$882_Y + connect \$3 $and$libresoc.v:25941$883_Y + connect \$5 $or$libresoc.v:25942$884_Y + connect \$7 $not$libresoc.v:25943$885_Y + connect \qlq_alu \$15 + connect \qn_alu \$13 + connect \q_alu \$11 +end +attribute \src "libresoc.v:25962.1-26020.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.alu_l" +attribute \generator "nMigen" +module \alu_l$125 + attribute \src "libresoc.v:25963.7-25963.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:26008.3-26016.6" + wire $0\q_int$next[0:0]$902 + attribute \src "libresoc.v:26006.3-26007.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:26008.3-26016.6" + wire $1\q_int$next[0:0]$903 + attribute \src "libresoc.v:25987.7-25987.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:25998.17-25998.96" + wire $and$libresoc.v:25998$892_Y + attribute \src "libresoc.v:26003.17-26003.96" + wire $and$libresoc.v:26003$897_Y + attribute \src "libresoc.v:26000.18-26000.93" + wire $not$libresoc.v:26000$894_Y + attribute \src "libresoc.v:26002.17-26002.92" + wire $not$libresoc.v:26002$896_Y + attribute \src "libresoc.v:26005.17-26005.92" + wire $not$libresoc.v:26005$899_Y + attribute \src "libresoc.v:25999.18-25999.98" + wire $or$libresoc.v:25999$893_Y + attribute \src "libresoc.v:26001.18-26001.99" + wire $or$libresoc.v:26001$895_Y + attribute \src "libresoc.v:26004.17-26004.97" + wire $or$libresoc.v:26004$898_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 1 \coresync_rst + attribute \src "libresoc.v:25963.7-25963.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 4 \q_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 2 \s_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$libresoc.v:25998$892 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:25998$892_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:26003$897 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:26003$897_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:26000$894 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alu + connect \Y $not$libresoc.v:26000$894_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:26002$896 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alu + connect \Y $not$libresoc.v:26002$896_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:26005$899 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alu + connect \Y $not$libresoc.v:26005$899_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:25999$893 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_alu + connect \Y $or$libresoc.v:25999$893_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:26001$895 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alu + connect \B \q_int + connect \Y $or$libresoc.v:26001$895_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:26004$898 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_alu + connect \Y $or$libresoc.v:26004$898_Y + end + attribute \src "libresoc.v:25963.7-25963.20" + process $proc$libresoc.v:25963$904 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:25987.7-25987.19" + process $proc$libresoc.v:25987$905 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:26006.3-26007.27" + process $proc$libresoc.v:26006$900 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:26008.3-26016.6" + process $proc$libresoc.v:26008$901 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$902 $1\q_int$next[0:0]$903 + attribute \src "libresoc.v:26009.5-26009.29" + switch \initial + attribute \src "libresoc.v:26009.9-26009.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$903 1'0 + case + assign $1\q_int$next[0:0]$903 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$902 + end + connect \$9 $and$libresoc.v:25998$892_Y + connect \$11 $or$libresoc.v:25999$893_Y + connect \$13 $not$libresoc.v:26000$894_Y + connect \$15 $or$libresoc.v:26001$895_Y + connect \$1 $not$libresoc.v:26002$896_Y + connect \$3 $and$libresoc.v:26003$897_Y + connect \$5 $or$libresoc.v:26004$898_Y + connect \$7 $not$libresoc.v:26005$899_Y + connect \qlq_alu \$15 + connect \qn_alu \$13 + connect \q_alu \$11 +end +attribute \src "libresoc.v:26024.1-26082.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.alu_l" +attribute \generator "nMigen" +module \alu_l$16 + attribute \src "libresoc.v:26025.7-26025.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:26070.3-26078.6" + wire $0\q_int$next[0:0]$916 + attribute \src "libresoc.v:26068.3-26069.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:26070.3-26078.6" + wire $1\q_int$next[0:0]$917 + attribute \src "libresoc.v:26049.7-26049.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:26060.17-26060.96" + wire $and$libresoc.v:26060$906_Y + attribute \src "libresoc.v:26065.17-26065.96" + wire $and$libresoc.v:26065$911_Y + attribute \src "libresoc.v:26062.18-26062.93" + wire $not$libresoc.v:26062$908_Y + attribute \src "libresoc.v:26064.17-26064.92" + wire $not$libresoc.v:26064$910_Y + attribute \src "libresoc.v:26067.17-26067.92" + wire $not$libresoc.v:26067$913_Y + attribute \src "libresoc.v:26061.18-26061.98" + wire $or$libresoc.v:26061$907_Y + attribute \src "libresoc.v:26063.18-26063.99" + wire $or$libresoc.v:26063$909_Y + attribute \src "libresoc.v:26066.17-26066.97" + wire $or$libresoc.v:26066$912_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 1 \coresync_rst + attribute \src "libresoc.v:26025.7-26025.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 2 \q_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 4 \s_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$libresoc.v:26060$906 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:26060$906_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:26065$911 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:26065$911_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:26062$908 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alu + connect \Y $not$libresoc.v:26062$908_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:26064$910 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alu + connect \Y $not$libresoc.v:26064$910_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:26067$913 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alu + connect \Y $not$libresoc.v:26067$913_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:26061$907 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_alu + connect \Y $or$libresoc.v:26061$907_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:26063$909 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alu + connect \B \q_int + connect \Y $or$libresoc.v:26063$909_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:26066$912 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_alu + connect \Y $or$libresoc.v:26066$912_Y + end + attribute \src "libresoc.v:26025.7-26025.20" + process $proc$libresoc.v:26025$918 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:26049.7-26049.19" + process $proc$libresoc.v:26049$919 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:26068.3-26069.27" + process $proc$libresoc.v:26068$914 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:26070.3-26078.6" + process $proc$libresoc.v:26070$915 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$916 $1\q_int$next[0:0]$917 + attribute \src "libresoc.v:26071.5-26071.29" + switch \initial + attribute \src "libresoc.v:26071.9-26071.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$917 1'0 + case + assign $1\q_int$next[0:0]$917 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$916 + end + connect \$9 $and$libresoc.v:26060$906_Y + connect \$11 $or$libresoc.v:26061$907_Y + connect \$13 $not$libresoc.v:26062$908_Y + connect \$15 $or$libresoc.v:26063$909_Y + connect \$1 $not$libresoc.v:26064$910_Y + connect \$3 $and$libresoc.v:26065$911_Y + connect \$5 $or$libresoc.v:26066$912_Y + connect \$7 $not$libresoc.v:26067$913_Y + connect \qlq_alu \$15 + connect \qn_alu \$13 + connect \q_alu \$11 +end +attribute \src "libresoc.v:26086.1-26144.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.alu_l" +attribute \generator "nMigen" +module \alu_l$29 + attribute \src "libresoc.v:26087.7-26087.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:26132.3-26140.6" + wire $0\q_int$next[0:0]$930 + attribute \src "libresoc.v:26130.3-26131.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:26132.3-26140.6" + wire $1\q_int$next[0:0]$931 + attribute \src "libresoc.v:26111.7-26111.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:26122.17-26122.96" + wire $and$libresoc.v:26122$920_Y + attribute \src "libresoc.v:26127.17-26127.96" + wire $and$libresoc.v:26127$925_Y + attribute \src "libresoc.v:26124.18-26124.93" + wire $not$libresoc.v:26124$922_Y + attribute \src "libresoc.v:26126.17-26126.92" + wire $not$libresoc.v:26126$924_Y + attribute \src "libresoc.v:26129.17-26129.92" + wire $not$libresoc.v:26129$927_Y + attribute \src "libresoc.v:26123.18-26123.98" + wire $or$libresoc.v:26123$921_Y + attribute \src "libresoc.v:26125.18-26125.99" + wire $or$libresoc.v:26125$923_Y + attribute \src "libresoc.v:26128.17-26128.97" + wire $or$libresoc.v:26128$926_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 1 \coresync_rst + attribute \src "libresoc.v:26087.7-26087.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 2 \q_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 4 \s_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$libresoc.v:26122$920 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:26122$920_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:26127$925 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:26127$925_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:26124$922 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alu + connect \Y $not$libresoc.v:26124$922_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:26126$924 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alu + connect \Y $not$libresoc.v:26126$924_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:26129$927 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alu + connect \Y $not$libresoc.v:26129$927_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:26123$921 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_alu + connect \Y $or$libresoc.v:26123$921_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:26125$923 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alu + connect \B \q_int + connect \Y $or$libresoc.v:26125$923_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:26128$926 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_alu + connect \Y $or$libresoc.v:26128$926_Y + end + attribute \src "libresoc.v:26087.7-26087.20" + process $proc$libresoc.v:26087$932 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:26111.7-26111.19" + process $proc$libresoc.v:26111$933 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:26130.3-26131.27" + process $proc$libresoc.v:26130$928 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:26132.3-26140.6" + process $proc$libresoc.v:26132$929 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$930 $1\q_int$next[0:0]$931 + attribute \src "libresoc.v:26133.5-26133.29" + switch \initial + attribute \src "libresoc.v:26133.9-26133.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$931 1'0 + case + assign $1\q_int$next[0:0]$931 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$930 + end + connect \$9 $and$libresoc.v:26122$920_Y + connect \$11 $or$libresoc.v:26123$921_Y + connect \$13 $not$libresoc.v:26124$922_Y + connect \$15 $or$libresoc.v:26125$923_Y + connect \$1 $not$libresoc.v:26126$924_Y + connect \$3 $and$libresoc.v:26127$925_Y + connect \$5 $or$libresoc.v:26128$926_Y + connect \$7 $not$libresoc.v:26129$927_Y + connect \qlq_alu \$15 + connect \qn_alu \$13 + connect \q_alu \$11 +end +attribute \src "libresoc.v:26148.1-26206.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.alu_l" +attribute \generator "nMigen" +module \alu_l$42 + attribute \src "libresoc.v:26149.7-26149.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:26194.3-26202.6" + wire $0\q_int$next[0:0]$944 + attribute \src "libresoc.v:26192.3-26193.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:26194.3-26202.6" + wire $1\q_int$next[0:0]$945 + attribute \src "libresoc.v:26173.7-26173.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:26184.17-26184.96" + wire $and$libresoc.v:26184$934_Y + attribute \src "libresoc.v:26189.17-26189.96" + wire $and$libresoc.v:26189$939_Y + attribute \src "libresoc.v:26186.18-26186.93" + wire $not$libresoc.v:26186$936_Y + attribute \src "libresoc.v:26188.17-26188.92" + wire $not$libresoc.v:26188$938_Y + attribute \src "libresoc.v:26191.17-26191.92" + wire $not$libresoc.v:26191$941_Y + attribute \src "libresoc.v:26185.18-26185.98" + wire $or$libresoc.v:26185$935_Y + attribute \src "libresoc.v:26187.18-26187.99" + wire $or$libresoc.v:26187$937_Y + attribute \src "libresoc.v:26190.17-26190.97" + wire $or$libresoc.v:26190$940_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 1 \coresync_rst + attribute \src "libresoc.v:26149.7-26149.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 2 \q_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 4 \s_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$libresoc.v:26184$934 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:26184$934_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:26189$939 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:26189$939_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:26186$936 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alu + connect \Y $not$libresoc.v:26186$936_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:26188$938 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alu + connect \Y $not$libresoc.v:26188$938_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:26191$941 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alu + connect \Y $not$libresoc.v:26191$941_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:26185$935 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_alu + connect \Y $or$libresoc.v:26185$935_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:26187$937 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alu + connect \B \q_int + connect \Y $or$libresoc.v:26187$937_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:26190$940 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_alu + connect \Y $or$libresoc.v:26190$940_Y + end + attribute \src "libresoc.v:26149.7-26149.20" + process $proc$libresoc.v:26149$946 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:26173.7-26173.19" + process $proc$libresoc.v:26173$947 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:26192.3-26193.27" + process $proc$libresoc.v:26192$942 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:26194.3-26202.6" + process $proc$libresoc.v:26194$943 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$944 $1\q_int$next[0:0]$945 + attribute \src "libresoc.v:26195.5-26195.29" + switch \initial + attribute \src "libresoc.v:26195.9-26195.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$945 1'0 + case + assign $1\q_int$next[0:0]$945 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$944 + end + connect \$9 $and$libresoc.v:26184$934_Y + connect \$11 $or$libresoc.v:26185$935_Y + connect \$13 $not$libresoc.v:26186$936_Y + connect \$15 $or$libresoc.v:26187$937_Y + connect \$1 $not$libresoc.v:26188$938_Y + connect \$3 $and$libresoc.v:26189$939_Y + connect \$5 $or$libresoc.v:26190$940_Y + connect \$7 $not$libresoc.v:26191$941_Y + connect \qlq_alu \$15 + connect \qn_alu \$13 + connect \q_alu \$11 +end +attribute \src "libresoc.v:26210.1-26268.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_l" +attribute \generator "nMigen" +module \alu_l$58 + attribute \src "libresoc.v:26211.7-26211.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:26256.3-26264.6" + wire $0\q_int$next[0:0]$958 + attribute \src "libresoc.v:26254.3-26255.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:26256.3-26264.6" + wire $1\q_int$next[0:0]$959 + attribute \src "libresoc.v:26235.7-26235.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:26246.17-26246.96" + wire $and$libresoc.v:26246$948_Y + attribute \src "libresoc.v:26251.17-26251.96" + wire $and$libresoc.v:26251$953_Y + attribute \src "libresoc.v:26248.18-26248.93" + wire $not$libresoc.v:26248$950_Y + attribute \src "libresoc.v:26250.17-26250.92" + wire $not$libresoc.v:26250$952_Y + attribute \src "libresoc.v:26253.17-26253.92" + wire $not$libresoc.v:26253$955_Y + attribute \src "libresoc.v:26247.18-26247.98" + wire $or$libresoc.v:26247$949_Y + attribute \src "libresoc.v:26249.18-26249.99" + wire $or$libresoc.v:26249$951_Y + attribute \src "libresoc.v:26252.17-26252.97" + wire $or$libresoc.v:26252$954_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 1 \coresync_rst + attribute \src "libresoc.v:26211.7-26211.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 2 \q_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 4 \s_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$libresoc.v:26246$948 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:26246$948_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:26251$953 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:26251$953_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:26248$950 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alu + connect \Y $not$libresoc.v:26248$950_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:26250$952 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alu + connect \Y $not$libresoc.v:26250$952_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:26253$955 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alu + connect \Y $not$libresoc.v:26253$955_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:26247$949 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_alu + connect \Y $or$libresoc.v:26247$949_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:26249$951 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alu + connect \B \q_int + connect \Y $or$libresoc.v:26249$951_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:26252$954 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_alu + connect \Y $or$libresoc.v:26252$954_Y + end + attribute \src "libresoc.v:26211.7-26211.20" + process $proc$libresoc.v:26211$960 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:26235.7-26235.19" + process $proc$libresoc.v:26235$961 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:26254.3-26255.27" + process $proc$libresoc.v:26254$956 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:26256.3-26264.6" + process $proc$libresoc.v:26256$957 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$958 $1\q_int$next[0:0]$959 + attribute \src "libresoc.v:26257.5-26257.29" + switch \initial + attribute \src "libresoc.v:26257.9-26257.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$959 1'0 + case + assign $1\q_int$next[0:0]$959 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$958 + end + connect \$9 $and$libresoc.v:26246$948_Y + connect \$11 $or$libresoc.v:26247$949_Y + connect \$13 $not$libresoc.v:26248$950_Y + connect \$15 $or$libresoc.v:26249$951_Y + connect \$1 $not$libresoc.v:26250$952_Y + connect \$3 $and$libresoc.v:26251$953_Y + connect \$5 $or$libresoc.v:26252$954_Y + connect \$7 $not$libresoc.v:26253$955_Y + connect \qlq_alu \$15 + connect \qn_alu \$13 + connect \q_alu \$11 +end +attribute \src "libresoc.v:26272.1-26330.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.alu_l" +attribute \generator "nMigen" +module \alu_l$70 + attribute \src "libresoc.v:26273.7-26273.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:26318.3-26326.6" + wire $0\q_int$next[0:0]$972 + attribute \src "libresoc.v:26316.3-26317.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:26318.3-26326.6" + wire $1\q_int$next[0:0]$973 + attribute \src "libresoc.v:26297.7-26297.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:26308.17-26308.96" + wire $and$libresoc.v:26308$962_Y + attribute \src "libresoc.v:26313.17-26313.96" + wire $and$libresoc.v:26313$967_Y + attribute \src "libresoc.v:26310.18-26310.93" + wire $not$libresoc.v:26310$964_Y + attribute \src "libresoc.v:26312.17-26312.92" + wire $not$libresoc.v:26312$966_Y + attribute \src "libresoc.v:26315.17-26315.92" + wire $not$libresoc.v:26315$969_Y + attribute \src "libresoc.v:26309.18-26309.98" + wire $or$libresoc.v:26309$963_Y + attribute \src "libresoc.v:26311.18-26311.99" + wire $or$libresoc.v:26311$965_Y + attribute \src "libresoc.v:26314.17-26314.97" + wire $or$libresoc.v:26314$968_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 1 \coresync_rst + attribute \src "libresoc.v:26273.7-26273.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 2 \q_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 4 \s_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$libresoc.v:26308$962 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:26308$962_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:26313$967 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:26313$967_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:26310$964 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alu + connect \Y $not$libresoc.v:26310$964_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:26312$966 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alu + connect \Y $not$libresoc.v:26312$966_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:26315$969 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alu + connect \Y $not$libresoc.v:26315$969_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:26309$963 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_alu + connect \Y $or$libresoc.v:26309$963_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:26311$965 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alu + connect \B \q_int + connect \Y $or$libresoc.v:26311$965_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:26314$968 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_alu + connect \Y $or$libresoc.v:26314$968_Y + end + attribute \src "libresoc.v:26273.7-26273.20" + process $proc$libresoc.v:26273$974 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:26297.7-26297.19" + process $proc$libresoc.v:26297$975 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:26316.3-26317.27" + process $proc$libresoc.v:26316$970 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:26318.3-26326.6" + process $proc$libresoc.v:26318$971 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$972 $1\q_int$next[0:0]$973 + attribute \src "libresoc.v:26319.5-26319.29" + switch \initial + attribute \src "libresoc.v:26319.9-26319.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$973 1'0 + case + assign $1\q_int$next[0:0]$973 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$972 + end + connect \$9 $and$libresoc.v:26308$962_Y + connect \$11 $or$libresoc.v:26309$963_Y + connect \$13 $not$libresoc.v:26310$964_Y + connect \$15 $or$libresoc.v:26311$965_Y + connect \$1 $not$libresoc.v:26312$966_Y + connect \$3 $and$libresoc.v:26313$967_Y + connect \$5 $or$libresoc.v:26314$968_Y + connect \$7 $not$libresoc.v:26315$969_Y + connect \qlq_alu \$15 + connect \qn_alu \$13 + connect \q_alu \$11 +end +attribute \src "libresoc.v:26334.1-26392.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_l" +attribute \generator "nMigen" +module \alu_l$87 + attribute \src "libresoc.v:26335.7-26335.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:26380.3-26388.6" + wire $0\q_int$next[0:0]$986 + attribute \src "libresoc.v:26378.3-26379.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:26380.3-26388.6" + wire $1\q_int$next[0:0]$987 + attribute \src "libresoc.v:26359.7-26359.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:26370.17-26370.96" + wire $and$libresoc.v:26370$976_Y + attribute \src "libresoc.v:26375.17-26375.96" + wire $and$libresoc.v:26375$981_Y + attribute \src "libresoc.v:26372.18-26372.93" + wire $not$libresoc.v:26372$978_Y + attribute \src "libresoc.v:26374.17-26374.92" + wire $not$libresoc.v:26374$980_Y + attribute \src "libresoc.v:26377.17-26377.92" + wire $not$libresoc.v:26377$983_Y + attribute \src "libresoc.v:26371.18-26371.98" + wire $or$libresoc.v:26371$977_Y + attribute \src "libresoc.v:26373.18-26373.99" + wire $or$libresoc.v:26373$979_Y + attribute \src "libresoc.v:26376.17-26376.97" + wire $or$libresoc.v:26376$982_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 1 \coresync_rst + attribute \src "libresoc.v:26335.7-26335.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 2 \q_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 4 \s_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$libresoc.v:26370$976 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:26370$976_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:26375$981 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:26375$981_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:26372$978 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alu + connect \Y $not$libresoc.v:26372$978_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:26374$980 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alu + connect \Y $not$libresoc.v:26374$980_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:26377$983 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alu + connect \Y $not$libresoc.v:26377$983_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:26371$977 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_alu + connect \Y $or$libresoc.v:26371$977_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:26373$979 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alu + connect \B \q_int + connect \Y $or$libresoc.v:26373$979_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:26376$982 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_alu + connect \Y $or$libresoc.v:26376$982_Y + end + attribute \src "libresoc.v:26335.7-26335.20" + process $proc$libresoc.v:26335$988 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:26359.7-26359.19" + process $proc$libresoc.v:26359$989 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:26378.3-26379.27" + process $proc$libresoc.v:26378$984 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:26380.3-26388.6" + process $proc$libresoc.v:26380$985 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$986 $1\q_int$next[0:0]$987 + attribute \src "libresoc.v:26381.5-26381.29" + switch \initial + attribute \src "libresoc.v:26381.9-26381.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$987 1'0 + case + assign $1\q_int$next[0:0]$987 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$986 + end + connect \$9 $and$libresoc.v:26370$976_Y + connect \$11 $or$libresoc.v:26371$977_Y + connect \$13 $not$libresoc.v:26372$978_Y + connect \$15 $or$libresoc.v:26373$979_Y + connect \$1 $not$libresoc.v:26374$980_Y + connect \$3 $and$libresoc.v:26375$981_Y + connect \$5 $or$libresoc.v:26376$982_Y + connect \$7 $not$libresoc.v:26377$983_Y + connect \qlq_alu \$15 + connect \qn_alu \$13 + connect \q_alu \$11 +end +attribute \src "libresoc.v:26396.1-27391.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_logical0" +attribute \generator "nMigen" +module \alu_logical0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 31 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 3 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 output 25 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 2 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 22 \logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \logical_op__data_len$61 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 7 \logical_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \logical_op__fn_unit$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 8 \logical_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \logical_op__imm_data__data$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \logical_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__imm_data__ok$48 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 16 \logical_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \logical_op__input_carry$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 23 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \logical_op__insn$62 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 6 \logical_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \logical_op__insn_type$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_in$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 17 \logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_out$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 20 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_32bit$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 21 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_signed$60 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__oe$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__ok$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 19 \logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__output_carry$58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 11 \logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__ok$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__rc$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 18 \logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__write_cr0$57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 15 \logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__zero_a$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \logical_pipe1_cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \logical_pipe1_cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \logical_pipe1_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \logical_pipe1_logical_op__data_len$18 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \logical_pipe1_logical_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \logical_pipe1_logical_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \logical_pipe1_logical_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \logical_pipe1_logical_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe1_logical_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe1_logical_op__imm_data__ok$5 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \logical_pipe1_logical_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \logical_pipe1_logical_op__input_carry$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \logical_pipe1_logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \logical_pipe1_logical_op__insn$19 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \logical_pipe1_logical_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \logical_pipe1_logical_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe1_logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe1_logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe1_logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe1_logical_op__invert_out$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe1_logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe1_logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe1_logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe1_logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe1_logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe1_logical_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe1_logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe1_logical_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe1_logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe1_logical_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe1_logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe1_logical_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe1_logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe1_logical_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe1_logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe1_logical_op__write_cr0$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe1_logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe1_logical_op__zero_a$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \logical_pipe1_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \logical_pipe1_muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire \logical_pipe1_n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire \logical_pipe1_n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \logical_pipe1_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \logical_pipe1_o_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire \logical_pipe1_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire \logical_pipe1_p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \logical_pipe1_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \logical_pipe1_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \logical_pipe1_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \logical_pipe1_xer_so$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \logical_pipe1_xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \logical_pipe2_cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \logical_pipe2_cr_a$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \logical_pipe2_cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \logical_pipe2_cr_a_ok$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \logical_pipe2_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \logical_pipe2_logical_op__data_len$38 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \logical_pipe2_logical_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \logical_pipe2_logical_op__fn_unit$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \logical_pipe2_logical_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \logical_pipe2_logical_op__imm_data__data$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe2_logical_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe2_logical_op__imm_data__ok$25 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \logical_pipe2_logical_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \logical_pipe2_logical_op__input_carry$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \logical_pipe2_logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \logical_pipe2_logical_op__insn$39 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \logical_pipe2_logical_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \logical_pipe2_logical_op__insn_type$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe2_logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe2_logical_op__invert_in$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe2_logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe2_logical_op__invert_out$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe2_logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe2_logical_op__is_32bit$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe2_logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe2_logical_op__is_signed$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe2_logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe2_logical_op__oe__oe$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe2_logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe2_logical_op__oe__ok$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe2_logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe2_logical_op__output_carry$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe2_logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe2_logical_op__rc__ok$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe2_logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe2_logical_op__rc__rc$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe2_logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe2_logical_op__write_cr0$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe2_logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe2_logical_op__zero_a$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \logical_pipe2_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \logical_pipe2_muxid$21 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire \logical_pipe2_n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire \logical_pipe2_n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \logical_pipe2_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \logical_pipe2_o$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \logical_pipe2_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \logical_pipe2_o_ok$41 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire \logical_pipe2_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire \logical_pipe2_p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \logical_pipe2_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \logical_pipe2_xer_so_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$44 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire input 5 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire output 4 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 24 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 1 \o_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire output 30 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire input 29 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 26 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 27 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 28 \xer_so + attribute \module_not_derived 1 + attribute \src "libresoc.v:27251.17-27305.4" + cell \logical_pipe1 \logical_pipe1 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cr_a \logical_pipe1_cr_a + connect \cr_a_ok \logical_pipe1_cr_a_ok + connect \logical_op__data_len \logical_pipe1_logical_op__data_len + connect \logical_op__data_len$18 \logical_pipe1_logical_op__data_len$18 + connect \logical_op__fn_unit \logical_pipe1_logical_op__fn_unit + connect \logical_op__fn_unit$3 \logical_pipe1_logical_op__fn_unit$3 + connect \logical_op__imm_data__data \logical_pipe1_logical_op__imm_data__data + connect \logical_op__imm_data__data$4 \logical_pipe1_logical_op__imm_data__data$4 + connect \logical_op__imm_data__ok \logical_pipe1_logical_op__imm_data__ok + connect \logical_op__imm_data__ok$5 \logical_pipe1_logical_op__imm_data__ok$5 + connect \logical_op__input_carry \logical_pipe1_logical_op__input_carry + connect \logical_op__input_carry$12 \logical_pipe1_logical_op__input_carry$12 + connect \logical_op__insn \logical_pipe1_logical_op__insn + connect \logical_op__insn$19 \logical_pipe1_logical_op__insn$19 + connect \logical_op__insn_type \logical_pipe1_logical_op__insn_type + connect \logical_op__insn_type$2 \logical_pipe1_logical_op__insn_type$2 + connect \logical_op__invert_in \logical_pipe1_logical_op__invert_in + connect \logical_op__invert_in$10 \logical_pipe1_logical_op__invert_in$10 + connect \logical_op__invert_out \logical_pipe1_logical_op__invert_out + connect \logical_op__invert_out$13 \logical_pipe1_logical_op__invert_out$13 + connect \logical_op__is_32bit \logical_pipe1_logical_op__is_32bit + connect \logical_op__is_32bit$16 \logical_pipe1_logical_op__is_32bit$16 + connect \logical_op__is_signed \logical_pipe1_logical_op__is_signed + connect \logical_op__is_signed$17 \logical_pipe1_logical_op__is_signed$17 + connect \logical_op__oe__oe \logical_pipe1_logical_op__oe__oe + connect \logical_op__oe__oe$8 \logical_pipe1_logical_op__oe__oe$8 + connect \logical_op__oe__ok \logical_pipe1_logical_op__oe__ok + connect \logical_op__oe__ok$9 \logical_pipe1_logical_op__oe__ok$9 + connect \logical_op__output_carry \logical_pipe1_logical_op__output_carry + connect \logical_op__output_carry$15 \logical_pipe1_logical_op__output_carry$15 + connect \logical_op__rc__ok \logical_pipe1_logical_op__rc__ok + connect \logical_op__rc__ok$7 \logical_pipe1_logical_op__rc__ok$7 + connect \logical_op__rc__rc \logical_pipe1_logical_op__rc__rc + connect \logical_op__rc__rc$6 \logical_pipe1_logical_op__rc__rc$6 + connect \logical_op__write_cr0 \logical_pipe1_logical_op__write_cr0 + connect \logical_op__write_cr0$14 \logical_pipe1_logical_op__write_cr0$14 + connect \logical_op__zero_a \logical_pipe1_logical_op__zero_a + connect \logical_op__zero_a$11 \logical_pipe1_logical_op__zero_a$11 + connect \muxid \logical_pipe1_muxid + connect \muxid$1 \logical_pipe1_muxid$1 + connect \n_ready_i \logical_pipe1_n_ready_i + connect \n_valid_o \logical_pipe1_n_valid_o + connect \o \logical_pipe1_o + connect \o_ok \logical_pipe1_o_ok + connect \p_ready_o \logical_pipe1_p_ready_o + connect \p_valid_i \logical_pipe1_p_valid_i + connect \ra \logical_pipe1_ra + connect \rb \logical_pipe1_rb + connect \xer_so \logical_pipe1_xer_so + connect \xer_so$20 \logical_pipe1_xer_so$20 + connect \xer_so_ok \logical_pipe1_xer_so_ok + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:27306.17-27361.4" + cell \logical_pipe2 \logical_pipe2 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cr_a \logical_pipe2_cr_a + connect \cr_a$22 \logical_pipe2_cr_a$42 + connect \cr_a_ok \logical_pipe2_cr_a_ok + connect \cr_a_ok$23 \logical_pipe2_cr_a_ok$43 + connect \logical_op__data_len \logical_pipe2_logical_op__data_len + connect \logical_op__data_len$18 \logical_pipe2_logical_op__data_len$38 + connect \logical_op__fn_unit \logical_pipe2_logical_op__fn_unit + connect \logical_op__fn_unit$3 \logical_pipe2_logical_op__fn_unit$23 + connect \logical_op__imm_data__data \logical_pipe2_logical_op__imm_data__data + connect \logical_op__imm_data__data$4 \logical_pipe2_logical_op__imm_data__data$24 + connect \logical_op__imm_data__ok \logical_pipe2_logical_op__imm_data__ok + connect \logical_op__imm_data__ok$5 \logical_pipe2_logical_op__imm_data__ok$25 + connect \logical_op__input_carry \logical_pipe2_logical_op__input_carry + connect \logical_op__input_carry$12 \logical_pipe2_logical_op__input_carry$32 + connect \logical_op__insn \logical_pipe2_logical_op__insn + connect \logical_op__insn$19 \logical_pipe2_logical_op__insn$39 + connect \logical_op__insn_type \logical_pipe2_logical_op__insn_type + connect \logical_op__insn_type$2 \logical_pipe2_logical_op__insn_type$22 + connect \logical_op__invert_in \logical_pipe2_logical_op__invert_in + connect \logical_op__invert_in$10 \logical_pipe2_logical_op__invert_in$30 + connect \logical_op__invert_out \logical_pipe2_logical_op__invert_out + connect \logical_op__invert_out$13 \logical_pipe2_logical_op__invert_out$33 + connect \logical_op__is_32bit \logical_pipe2_logical_op__is_32bit + connect \logical_op__is_32bit$16 \logical_pipe2_logical_op__is_32bit$36 + connect \logical_op__is_signed \logical_pipe2_logical_op__is_signed + connect \logical_op__is_signed$17 \logical_pipe2_logical_op__is_signed$37 + connect \logical_op__oe__oe \logical_pipe2_logical_op__oe__oe + connect \logical_op__oe__oe$8 \logical_pipe2_logical_op__oe__oe$28 + connect \logical_op__oe__ok \logical_pipe2_logical_op__oe__ok + connect \logical_op__oe__ok$9 \logical_pipe2_logical_op__oe__ok$29 + connect \logical_op__output_carry \logical_pipe2_logical_op__output_carry + connect \logical_op__output_carry$15 \logical_pipe2_logical_op__output_carry$35 + connect \logical_op__rc__ok \logical_pipe2_logical_op__rc__ok + connect \logical_op__rc__ok$7 \logical_pipe2_logical_op__rc__ok$27 + connect \logical_op__rc__rc \logical_pipe2_logical_op__rc__rc + connect \logical_op__rc__rc$6 \logical_pipe2_logical_op__rc__rc$26 + connect \logical_op__write_cr0 \logical_pipe2_logical_op__write_cr0 + connect \logical_op__write_cr0$14 \logical_pipe2_logical_op__write_cr0$34 + connect \logical_op__zero_a \logical_pipe2_logical_op__zero_a + connect \logical_op__zero_a$11 \logical_pipe2_logical_op__zero_a$31 + connect \muxid \logical_pipe2_muxid + connect \muxid$1 \logical_pipe2_muxid$21 + connect \n_ready_i \logical_pipe2_n_ready_i + connect \n_valid_o \logical_pipe2_n_valid_o + connect \o \logical_pipe2_o + connect \o$20 \logical_pipe2_o$40 + connect \o_ok \logical_pipe2_o_ok + connect \o_ok$21 \logical_pipe2_o_ok$41 + connect \p_ready_o \logical_pipe2_p_ready_o + connect \p_valid_i \logical_pipe2_p_valid_i + connect \xer_so \logical_pipe2_xer_so + connect \xer_so_ok \logical_pipe2_xer_so_ok + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:27362.10-27365.4" + cell \n$44 \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:27366.10-27369.4" + cell \p$43 \p + connect \p_ready_o \p_ready_o + connect \p_valid_i \p_valid_i + end + connect \muxid 2'00 + connect { \cr_a_ok \cr_a } { \logical_pipe2_cr_a_ok$43 \logical_pipe2_cr_a$42 } + connect { \o_ok \o } { \logical_pipe2_o_ok$41 \logical_pipe2_o$40 } + connect { \logical_op__insn$62 \logical_op__data_len$61 \logical_op__is_signed$60 \logical_op__is_32bit$59 \logical_op__output_carry$58 \logical_op__write_cr0$57 \logical_op__invert_out$56 \logical_op__input_carry$55 \logical_op__zero_a$54 \logical_op__invert_in$53 \logical_op__oe__ok$52 \logical_op__oe__oe$51 \logical_op__rc__ok$50 \logical_op__rc__rc$49 \logical_op__imm_data__ok$48 \logical_op__imm_data__data$47 \logical_op__fn_unit$46 \logical_op__insn_type$45 } { \logical_pipe2_logical_op__insn$39 \logical_pipe2_logical_op__data_len$38 \logical_pipe2_logical_op__is_signed$37 \logical_pipe2_logical_op__is_32bit$36 \logical_pipe2_logical_op__output_carry$35 \logical_pipe2_logical_op__write_cr0$34 \logical_pipe2_logical_op__invert_out$33 \logical_pipe2_logical_op__input_carry$32 \logical_pipe2_logical_op__zero_a$31 \logical_pipe2_logical_op__invert_in$30 \logical_pipe2_logical_op__oe__ok$29 \logical_pipe2_logical_op__oe__oe$28 \logical_pipe2_logical_op__rc__ok$27 \logical_pipe2_logical_op__rc__rc$26 \logical_pipe2_logical_op__imm_data__ok$25 \logical_pipe2_logical_op__imm_data__data$24 \logical_pipe2_logical_op__fn_unit$23 \logical_pipe2_logical_op__insn_type$22 } + connect \muxid$44 \logical_pipe2_muxid$21 + connect \logical_pipe2_n_ready_i \n_ready_i + connect \n_valid_o \logical_pipe2_n_valid_o + connect \logical_pipe1_xer_so$20 \xer_so + connect \logical_pipe1_rb \rb + connect \logical_pipe1_ra \ra + connect { \logical_pipe1_logical_op__insn$19 \logical_pipe1_logical_op__data_len$18 \logical_pipe1_logical_op__is_signed$17 \logical_pipe1_logical_op__is_32bit$16 \logical_pipe1_logical_op__output_carry$15 \logical_pipe1_logical_op__write_cr0$14 \logical_pipe1_logical_op__invert_out$13 \logical_pipe1_logical_op__input_carry$12 \logical_pipe1_logical_op__zero_a$11 \logical_pipe1_logical_op__invert_in$10 \logical_pipe1_logical_op__oe__ok$9 \logical_pipe1_logical_op__oe__oe$8 \logical_pipe1_logical_op__rc__ok$7 \logical_pipe1_logical_op__rc__rc$6 \logical_pipe1_logical_op__imm_data__ok$5 \logical_pipe1_logical_op__imm_data__data$4 \logical_pipe1_logical_op__fn_unit$3 \logical_pipe1_logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } + connect \logical_pipe1_muxid$1 2'00 + connect \p_ready_o \logical_pipe1_p_ready_o + connect \logical_pipe1_p_valid_i \p_valid_i + connect { \logical_pipe2_xer_so_ok \logical_pipe2_xer_so } { \logical_pipe1_xer_so_ok \logical_pipe1_xer_so } + connect { \logical_pipe2_cr_a_ok \logical_pipe2_cr_a } { \logical_pipe1_cr_a_ok \logical_pipe1_cr_a } + connect { \logical_pipe2_o_ok \logical_pipe2_o } { \logical_pipe1_o_ok \logical_pipe1_o } + connect { \logical_pipe2_logical_op__insn \logical_pipe2_logical_op__data_len \logical_pipe2_logical_op__is_signed \logical_pipe2_logical_op__is_32bit \logical_pipe2_logical_op__output_carry \logical_pipe2_logical_op__write_cr0 \logical_pipe2_logical_op__invert_out \logical_pipe2_logical_op__input_carry \logical_pipe2_logical_op__zero_a \logical_pipe2_logical_op__invert_in \logical_pipe2_logical_op__oe__ok \logical_pipe2_logical_op__oe__oe \logical_pipe2_logical_op__rc__ok \logical_pipe2_logical_op__rc__rc \logical_pipe2_logical_op__imm_data__ok \logical_pipe2_logical_op__imm_data__data \logical_pipe2_logical_op__fn_unit \logical_pipe2_logical_op__insn_type } { \logical_pipe1_logical_op__insn \logical_pipe1_logical_op__data_len \logical_pipe1_logical_op__is_signed \logical_pipe1_logical_op__is_32bit \logical_pipe1_logical_op__output_carry \logical_pipe1_logical_op__write_cr0 \logical_pipe1_logical_op__invert_out \logical_pipe1_logical_op__input_carry \logical_pipe1_logical_op__zero_a \logical_pipe1_logical_op__invert_in \logical_pipe1_logical_op__oe__ok \logical_pipe1_logical_op__oe__oe \logical_pipe1_logical_op__rc__ok \logical_pipe1_logical_op__rc__rc \logical_pipe1_logical_op__imm_data__ok \logical_pipe1_logical_op__imm_data__data \logical_pipe1_logical_op__fn_unit \logical_pipe1_logical_op__insn_type } + connect \logical_pipe2_muxid \logical_pipe1_muxid + connect \logical_pipe1_n_ready_i \logical_pipe2_p_ready_o + connect \logical_pipe2_p_valid_i \logical_pipe1_n_valid_o +end +attribute \src "libresoc.v:27395.1-28588.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0" +attribute \generator "nMigen" +module \alu_mul0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 29 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 5 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 output 21 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 2 \cr_a_ok + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 9 \mul_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \mul_op__fn_unit$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 10 \mul_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \mul_op__imm_data__data$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 11 \mul_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__imm_data__ok$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 19 \mul_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \mul_op__insn$61 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 8 \mul_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \mul_op__insn_type$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 17 \mul_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__is_32bit$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 18 \mul_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__is_signed$60 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \mul_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__oe__oe$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 15 \mul_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__oe__ok$57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \mul_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__rc__ok$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \mul_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__rc__rc$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 16 \mul_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__write_cr0$58 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \mul_pipe1_mul_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \mul_pipe1_mul_op__fn_unit$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \mul_pipe1_mul_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \mul_pipe1_mul_op__imm_data__data$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe1_mul_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe1_mul_op__imm_data__ok$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \mul_pipe1_mul_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \mul_pipe1_mul_op__insn$14 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \mul_pipe1_mul_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \mul_pipe1_mul_op__insn_type$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe1_mul_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe1_mul_op__is_32bit$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe1_mul_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe1_mul_op__is_signed$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe1_mul_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe1_mul_op__oe__oe$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe1_mul_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe1_mul_op__oe__ok$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe1_mul_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe1_mul_op__rc__ok$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe1_mul_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe1_mul_op__rc__rc$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe1_mul_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe1_mul_op__write_cr0$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \mul_pipe1_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \mul_pipe1_muxid$2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire \mul_pipe1_n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire \mul_pipe1_n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" + wire \mul_pipe1_neg_res + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" + wire \mul_pipe1_neg_res32 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire \mul_pipe1_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire \mul_pipe1_p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \mul_pipe1_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \mul_pipe1_ra$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \mul_pipe1_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \mul_pipe1_rb$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \mul_pipe1_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \mul_pipe1_xer_so$17 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \mul_pipe2_mul_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \mul_pipe2_mul_op__fn_unit$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \mul_pipe2_mul_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \mul_pipe2_mul_op__imm_data__data$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe2_mul_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe2_mul_op__imm_data__ok$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \mul_pipe2_mul_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \mul_pipe2_mul_op__insn$30 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \mul_pipe2_mul_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \mul_pipe2_mul_op__insn_type$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe2_mul_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe2_mul_op__is_32bit$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe2_mul_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe2_mul_op__is_signed$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe2_mul_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe2_mul_op__oe__oe$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe2_mul_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe2_mul_op__oe__ok$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe2_mul_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe2_mul_op__rc__ok$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe2_mul_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe2_mul_op__rc__rc$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe2_mul_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe2_mul_op__write_cr0$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \mul_pipe2_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \mul_pipe2_muxid$18 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire \mul_pipe2_n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire \mul_pipe2_n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" + wire \mul_pipe2_neg_res + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" + wire \mul_pipe2_neg_res$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" + wire \mul_pipe2_neg_res32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" + wire \mul_pipe2_neg_res32$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 129 \mul_pipe2_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire \mul_pipe2_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire \mul_pipe2_p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \mul_pipe2_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \mul_pipe2_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \mul_pipe2_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \mul_pipe2_xer_so$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \mul_pipe3_cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \mul_pipe3_cr_a_ok + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \mul_pipe3_mul_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \mul_pipe3_mul_op__fn_unit$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \mul_pipe3_mul_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \mul_pipe3_mul_op__imm_data__data$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe3_mul_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe3_mul_op__imm_data__ok$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \mul_pipe3_mul_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \mul_pipe3_mul_op__insn$46 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \mul_pipe3_mul_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \mul_pipe3_mul_op__insn_type$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe3_mul_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe3_mul_op__is_32bit$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe3_mul_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe3_mul_op__is_signed$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe3_mul_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe3_mul_op__oe__oe$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe3_mul_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe3_mul_op__oe__ok$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe3_mul_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe3_mul_op__rc__ok$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe3_mul_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe3_mul_op__rc__rc$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe3_mul_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe3_mul_op__write_cr0$43 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \mul_pipe3_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \mul_pipe3_muxid$34 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire \mul_pipe3_n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire \mul_pipe3_n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" + wire \mul_pipe3_neg_res + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" + wire \mul_pipe3_neg_res32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 129 \mul_pipe3_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \mul_pipe3_o$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \mul_pipe3_o_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire \mul_pipe3_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire \mul_pipe3_p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \mul_pipe3_xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \mul_pipe3_xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \mul_pipe3_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \mul_pipe3_xer_so$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \mul_pipe3_xer_so_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$49 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire input 7 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire output 6 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 20 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 1 \o_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire output 28 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire input 27 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 24 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 25 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 output 22 \xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 3 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 23 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 26 \xer_so$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 4 \xer_so_ok + attribute \module_not_derived 1 + attribute \src "libresoc.v:28416.13-28457.4" + cell \mul_pipe1 \mul_pipe1 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \mul_op__fn_unit \mul_pipe1_mul_op__fn_unit + connect \mul_op__fn_unit$3 \mul_pipe1_mul_op__fn_unit$4 + connect \mul_op__imm_data__data \mul_pipe1_mul_op__imm_data__data + connect \mul_op__imm_data__data$4 \mul_pipe1_mul_op__imm_data__data$5 + connect \mul_op__imm_data__ok \mul_pipe1_mul_op__imm_data__ok + connect \mul_op__imm_data__ok$5 \mul_pipe1_mul_op__imm_data__ok$6 + connect \mul_op__insn \mul_pipe1_mul_op__insn + connect \mul_op__insn$13 \mul_pipe1_mul_op__insn$14 + connect \mul_op__insn_type \mul_pipe1_mul_op__insn_type + connect \mul_op__insn_type$2 \mul_pipe1_mul_op__insn_type$3 + connect \mul_op__is_32bit \mul_pipe1_mul_op__is_32bit + connect \mul_op__is_32bit$11 \mul_pipe1_mul_op__is_32bit$12 + connect \mul_op__is_signed \mul_pipe1_mul_op__is_signed + connect \mul_op__is_signed$12 \mul_pipe1_mul_op__is_signed$13 + connect \mul_op__oe__oe \mul_pipe1_mul_op__oe__oe + connect \mul_op__oe__oe$8 \mul_pipe1_mul_op__oe__oe$9 + connect \mul_op__oe__ok \mul_pipe1_mul_op__oe__ok + connect \mul_op__oe__ok$9 \mul_pipe1_mul_op__oe__ok$10 + connect \mul_op__rc__ok \mul_pipe1_mul_op__rc__ok + connect \mul_op__rc__ok$7 \mul_pipe1_mul_op__rc__ok$8 + connect \mul_op__rc__rc \mul_pipe1_mul_op__rc__rc + connect \mul_op__rc__rc$6 \mul_pipe1_mul_op__rc__rc$7 + connect \mul_op__write_cr0 \mul_pipe1_mul_op__write_cr0 + connect \mul_op__write_cr0$10 \mul_pipe1_mul_op__write_cr0$11 + connect \muxid \mul_pipe1_muxid + connect \muxid$1 \mul_pipe1_muxid$2 + connect \n_ready_i \mul_pipe1_n_ready_i + connect \n_valid_o \mul_pipe1_n_valid_o + connect \neg_res \mul_pipe1_neg_res + connect \neg_res32 \mul_pipe1_neg_res32 + connect \p_ready_o \mul_pipe1_p_ready_o + connect \p_valid_i \mul_pipe1_p_valid_i + connect \ra \mul_pipe1_ra + connect \ra$14 \mul_pipe1_ra$15 + connect \rb \mul_pipe1_rb + connect \rb$15 \mul_pipe1_rb$16 + connect \xer_so \mul_pipe1_xer_so + connect \xer_so$16 \mul_pipe1_xer_so$17 + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:28458.13-28500.4" + cell \mul_pipe2 \mul_pipe2 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \mul_op__fn_unit \mul_pipe2_mul_op__fn_unit + connect \mul_op__fn_unit$3 \mul_pipe2_mul_op__fn_unit$20 + connect \mul_op__imm_data__data \mul_pipe2_mul_op__imm_data__data + connect \mul_op__imm_data__data$4 \mul_pipe2_mul_op__imm_data__data$21 + connect \mul_op__imm_data__ok \mul_pipe2_mul_op__imm_data__ok + connect \mul_op__imm_data__ok$5 \mul_pipe2_mul_op__imm_data__ok$22 + connect \mul_op__insn \mul_pipe2_mul_op__insn + connect \mul_op__insn$13 \mul_pipe2_mul_op__insn$30 + connect \mul_op__insn_type \mul_pipe2_mul_op__insn_type + connect \mul_op__insn_type$2 \mul_pipe2_mul_op__insn_type$19 + connect \mul_op__is_32bit \mul_pipe2_mul_op__is_32bit + connect \mul_op__is_32bit$11 \mul_pipe2_mul_op__is_32bit$28 + connect \mul_op__is_signed \mul_pipe2_mul_op__is_signed + connect \mul_op__is_signed$12 \mul_pipe2_mul_op__is_signed$29 + connect \mul_op__oe__oe \mul_pipe2_mul_op__oe__oe + connect \mul_op__oe__oe$8 \mul_pipe2_mul_op__oe__oe$25 + connect \mul_op__oe__ok \mul_pipe2_mul_op__oe__ok + connect \mul_op__oe__ok$9 \mul_pipe2_mul_op__oe__ok$26 + connect \mul_op__rc__ok \mul_pipe2_mul_op__rc__ok + connect \mul_op__rc__ok$7 \mul_pipe2_mul_op__rc__ok$24 + connect \mul_op__rc__rc \mul_pipe2_mul_op__rc__rc + connect \mul_op__rc__rc$6 \mul_pipe2_mul_op__rc__rc$23 + connect \mul_op__write_cr0 \mul_pipe2_mul_op__write_cr0 + connect \mul_op__write_cr0$10 \mul_pipe2_mul_op__write_cr0$27 + connect \muxid \mul_pipe2_muxid + connect \muxid$1 \mul_pipe2_muxid$18 + connect \n_ready_i \mul_pipe2_n_ready_i + connect \n_valid_o \mul_pipe2_n_valid_o + connect \neg_res \mul_pipe2_neg_res + connect \neg_res$15 \mul_pipe2_neg_res$32 + connect \neg_res32 \mul_pipe2_neg_res32 + connect \neg_res32$16 \mul_pipe2_neg_res32$33 + connect \o \mul_pipe2_o + connect \p_ready_o \mul_pipe2_p_ready_o + connect \p_valid_i \mul_pipe2_p_valid_i + connect \ra \mul_pipe2_ra + connect \rb \mul_pipe2_rb + connect \xer_so \mul_pipe2_xer_so + connect \xer_so$14 \mul_pipe2_xer_so$31 + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:28501.13-28546.4" + cell \mul_pipe3 \mul_pipe3 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cr_a \mul_pipe3_cr_a + connect \cr_a_ok \mul_pipe3_cr_a_ok + connect \mul_op__fn_unit \mul_pipe3_mul_op__fn_unit + connect \mul_op__fn_unit$3 \mul_pipe3_mul_op__fn_unit$36 + connect \mul_op__imm_data__data \mul_pipe3_mul_op__imm_data__data + connect \mul_op__imm_data__data$4 \mul_pipe3_mul_op__imm_data__data$37 + connect \mul_op__imm_data__ok \mul_pipe3_mul_op__imm_data__ok + connect \mul_op__imm_data__ok$5 \mul_pipe3_mul_op__imm_data__ok$38 + connect \mul_op__insn \mul_pipe3_mul_op__insn + connect \mul_op__insn$13 \mul_pipe3_mul_op__insn$46 + connect \mul_op__insn_type \mul_pipe3_mul_op__insn_type + connect \mul_op__insn_type$2 \mul_pipe3_mul_op__insn_type$35 + connect \mul_op__is_32bit \mul_pipe3_mul_op__is_32bit + connect \mul_op__is_32bit$11 \mul_pipe3_mul_op__is_32bit$44 + connect \mul_op__is_signed \mul_pipe3_mul_op__is_signed + connect \mul_op__is_signed$12 \mul_pipe3_mul_op__is_signed$45 + connect \mul_op__oe__oe \mul_pipe3_mul_op__oe__oe + connect \mul_op__oe__oe$8 \mul_pipe3_mul_op__oe__oe$41 + connect \mul_op__oe__ok \mul_pipe3_mul_op__oe__ok + connect \mul_op__oe__ok$9 \mul_pipe3_mul_op__oe__ok$42 + connect \mul_op__rc__ok \mul_pipe3_mul_op__rc__ok + connect \mul_op__rc__ok$7 \mul_pipe3_mul_op__rc__ok$40 + connect \mul_op__rc__rc \mul_pipe3_mul_op__rc__rc + connect \mul_op__rc__rc$6 \mul_pipe3_mul_op__rc__rc$39 + connect \mul_op__write_cr0 \mul_pipe3_mul_op__write_cr0 + connect \mul_op__write_cr0$10 \mul_pipe3_mul_op__write_cr0$43 + connect \muxid \mul_pipe3_muxid + connect \muxid$1 \mul_pipe3_muxid$34 + connect \n_ready_i \mul_pipe3_n_ready_i + connect \n_valid_o \mul_pipe3_n_valid_o + connect \neg_res \mul_pipe3_neg_res + connect \neg_res32 \mul_pipe3_neg_res32 + connect \o \mul_pipe3_o + connect \o$14 \mul_pipe3_o$47 + connect \o_ok \mul_pipe3_o_ok + connect \p_ready_o \mul_pipe3_p_ready_o + connect \p_valid_i \mul_pipe3_p_valid_i + connect \xer_ov \mul_pipe3_xer_ov + connect \xer_ov_ok \mul_pipe3_xer_ov_ok + connect \xer_so \mul_pipe3_xer_so + connect \xer_so$15 \mul_pipe3_xer_so$48 + connect \xer_so_ok \mul_pipe3_xer_so_ok + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:28547.10-28550.4" + cell \n$89 \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:28551.10-28554.4" + cell \p$88 \p + connect \p_ready_o \p_ready_o + connect \p_valid_i \p_valid_i + end + connect \muxid 2'00 + connect { \xer_so_ok \xer_so } { \mul_pipe3_xer_so_ok \mul_pipe3_xer_so$48 } + connect { \xer_ov_ok \xer_ov } { \mul_pipe3_xer_ov_ok \mul_pipe3_xer_ov } + connect { \cr_a_ok \cr_a } { \mul_pipe3_cr_a_ok \mul_pipe3_cr_a } + connect { \o_ok \o } { \mul_pipe3_o_ok \mul_pipe3_o$47 } + connect { \mul_op__insn$61 \mul_op__is_signed$60 \mul_op__is_32bit$59 \mul_op__write_cr0$58 \mul_op__oe__ok$57 \mul_op__oe__oe$56 \mul_op__rc__ok$55 \mul_op__rc__rc$54 \mul_op__imm_data__ok$53 \mul_op__imm_data__data$52 \mul_op__fn_unit$51 \mul_op__insn_type$50 } { \mul_pipe3_mul_op__insn$46 \mul_pipe3_mul_op__is_signed$45 \mul_pipe3_mul_op__is_32bit$44 \mul_pipe3_mul_op__write_cr0$43 \mul_pipe3_mul_op__oe__ok$42 \mul_pipe3_mul_op__oe__oe$41 \mul_pipe3_mul_op__rc__ok$40 \mul_pipe3_mul_op__rc__rc$39 \mul_pipe3_mul_op__imm_data__ok$38 \mul_pipe3_mul_op__imm_data__data$37 \mul_pipe3_mul_op__fn_unit$36 \mul_pipe3_mul_op__insn_type$35 } + connect \muxid$49 \mul_pipe3_muxid$34 + connect \mul_pipe3_n_ready_i \n_ready_i + connect \n_valid_o \mul_pipe3_n_valid_o + connect \mul_pipe1_xer_so$17 \xer_so$1 + connect \mul_pipe1_rb$16 \rb + connect \mul_pipe1_ra$15 \ra + connect { \mul_pipe1_mul_op__insn$14 \mul_pipe1_mul_op__is_signed$13 \mul_pipe1_mul_op__is_32bit$12 \mul_pipe1_mul_op__write_cr0$11 \mul_pipe1_mul_op__oe__ok$10 \mul_pipe1_mul_op__oe__oe$9 \mul_pipe1_mul_op__rc__ok$8 \mul_pipe1_mul_op__rc__rc$7 \mul_pipe1_mul_op__imm_data__ok$6 \mul_pipe1_mul_op__imm_data__data$5 \mul_pipe1_mul_op__fn_unit$4 \mul_pipe1_mul_op__insn_type$3 } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__oe__ok \mul_op__oe__oe \mul_op__rc__ok \mul_op__rc__rc \mul_op__imm_data__ok \mul_op__imm_data__data \mul_op__fn_unit \mul_op__insn_type } + connect \mul_pipe1_muxid$2 2'00 + connect \p_ready_o \mul_pipe1_p_ready_o + connect \mul_pipe1_p_valid_i \p_valid_i + connect \mul_pipe3_neg_res32 \mul_pipe2_neg_res32$33 + connect \mul_pipe3_neg_res \mul_pipe2_neg_res$32 + connect \mul_pipe3_xer_so \mul_pipe2_xer_so$31 + connect \mul_pipe3_o \mul_pipe2_o + connect { \mul_pipe3_mul_op__insn \mul_pipe3_mul_op__is_signed \mul_pipe3_mul_op__is_32bit \mul_pipe3_mul_op__write_cr0 \mul_pipe3_mul_op__oe__ok \mul_pipe3_mul_op__oe__oe \mul_pipe3_mul_op__rc__ok \mul_pipe3_mul_op__rc__rc \mul_pipe3_mul_op__imm_data__ok \mul_pipe3_mul_op__imm_data__data \mul_pipe3_mul_op__fn_unit \mul_pipe3_mul_op__insn_type } { \mul_pipe2_mul_op__insn$30 \mul_pipe2_mul_op__is_signed$29 \mul_pipe2_mul_op__is_32bit$28 \mul_pipe2_mul_op__write_cr0$27 \mul_pipe2_mul_op__oe__ok$26 \mul_pipe2_mul_op__oe__oe$25 \mul_pipe2_mul_op__rc__ok$24 \mul_pipe2_mul_op__rc__rc$23 \mul_pipe2_mul_op__imm_data__ok$22 \mul_pipe2_mul_op__imm_data__data$21 \mul_pipe2_mul_op__fn_unit$20 \mul_pipe2_mul_op__insn_type$19 } + connect \mul_pipe3_muxid \mul_pipe2_muxid$18 + connect \mul_pipe2_n_ready_i \mul_pipe3_p_ready_o + connect \mul_pipe3_p_valid_i \mul_pipe2_n_valid_o + connect \mul_pipe2_neg_res32 \mul_pipe1_neg_res32 + connect \mul_pipe2_neg_res \mul_pipe1_neg_res + connect \mul_pipe2_xer_so \mul_pipe1_xer_so + connect \mul_pipe2_rb \mul_pipe1_rb + connect \mul_pipe2_ra \mul_pipe1_ra + connect { \mul_pipe2_mul_op__insn \mul_pipe2_mul_op__is_signed \mul_pipe2_mul_op__is_32bit \mul_pipe2_mul_op__write_cr0 \mul_pipe2_mul_op__oe__ok \mul_pipe2_mul_op__oe__oe \mul_pipe2_mul_op__rc__ok \mul_pipe2_mul_op__rc__rc \mul_pipe2_mul_op__imm_data__ok \mul_pipe2_mul_op__imm_data__data \mul_pipe2_mul_op__fn_unit \mul_pipe2_mul_op__insn_type } { \mul_pipe1_mul_op__insn \mul_pipe1_mul_op__is_signed \mul_pipe1_mul_op__is_32bit \mul_pipe1_mul_op__write_cr0 \mul_pipe1_mul_op__oe__ok \mul_pipe1_mul_op__oe__oe \mul_pipe1_mul_op__rc__ok \mul_pipe1_mul_op__rc__rc \mul_pipe1_mul_op__imm_data__ok \mul_pipe1_mul_op__imm_data__data \mul_pipe1_mul_op__fn_unit \mul_pipe1_mul_op__insn_type } + connect \mul_pipe2_muxid \mul_pipe1_muxid + connect \mul_pipe1_n_ready_i \mul_pipe2_p_ready_o + connect \mul_pipe2_p_valid_i \mul_pipe1_n_valid_o +end +attribute \src "libresoc.v:28592.1-29591.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0" +attribute \generator "nMigen" +module \alu_shift_rot0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 33 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 4 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 output 24 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 2 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$44 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire input 6 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire output 5 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 23 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 1 \o_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire output 32 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire input 31 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \pipe1_cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \pipe1_cr_a_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \pipe1_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \pipe1_muxid$2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire \pipe1_n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire \pipe1_n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \pipe1_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \pipe1_o_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire \pipe1_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire \pipe1_p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe1_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe1_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe1_rc + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \pipe1_sr_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \pipe1_sr_op__fn_unit$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe1_sr_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe1_sr_op__imm_data__data$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_sr_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_sr_op__imm_data__ok$6 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \pipe1_sr_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \pipe1_sr_op__input_carry$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_sr_op__input_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_sr_op__input_cr$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe1_sr_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe1_sr_op__insn$18 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe1_sr_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe1_sr_op__insn_type$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_sr_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_sr_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_sr_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_sr_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_sr_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_sr_op__oe__oe$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_sr_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_sr_op__oe__ok$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_sr_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_sr_op__output_carry$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_sr_op__output_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_sr_op__output_cr$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_sr_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_sr_op__rc__ok$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_sr_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_sr_op__rc__rc$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_sr_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_sr_op__write_cr0$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \pipe1_xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 \pipe1_xer_ca$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \pipe1_xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \pipe1_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \pipe1_xer_so$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \pipe1_xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \pipe2_cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \pipe2_cr_a$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \pipe2_cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \pipe2_cr_a_ok$41 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \pipe2_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \pipe2_muxid$21 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire \pipe2_n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire \pipe2_n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \pipe2_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \pipe2_o$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \pipe2_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \pipe2_o_ok$39 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire \pipe2_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire \pipe2_p_valid_i + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \pipe2_sr_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \pipe2_sr_op__fn_unit$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe2_sr_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe2_sr_op__imm_data__data$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_sr_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_sr_op__imm_data__ok$25 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \pipe2_sr_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \pipe2_sr_op__input_carry$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_sr_op__input_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_sr_op__input_cr$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe2_sr_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe2_sr_op__insn$37 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe2_sr_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe2_sr_op__insn_type$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_sr_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_sr_op__is_32bit$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_sr_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_sr_op__is_signed$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_sr_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_sr_op__oe__oe$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_sr_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_sr_op__oe__ok$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_sr_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_sr_op__output_carry$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_sr_op__output_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_sr_op__output_cr$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_sr_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_sr_op__rc__ok$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_sr_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_sr_op__rc__rc$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_sr_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_sr_op__write_cr0$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \pipe2_xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \pipe2_xer_ca$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \pipe2_xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \pipe2_xer_ca_ok$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \pipe2_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \pipe2_xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 26 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 27 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 28 \rc + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 8 \sr_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \sr_op__fn_unit$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 9 \sr_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \sr_op__imm_data__data$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \sr_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__imm_data__ok$48 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 16 \sr_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \sr_op__input_carry$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 18 \sr_op__input_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__input_cr$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 22 \sr_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \sr_op__insn$60 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 7 \sr_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \sr_op__insn_type$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 20 \sr_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__is_32bit$58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 21 \sr_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__is_signed$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \sr_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__oe__oe$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \sr_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__oe__ok$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 17 \sr_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__output_carry$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 19 \sr_op__output_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__output_cr$57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \sr_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__rc__ok$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 11 \sr_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__rc__rc$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 15 \sr_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__write_cr0$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 output 25 \xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 input 30 \xer_ca$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 3 \xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 29 \xer_so + attribute \module_not_derived 1 + attribute \src "libresoc.v:29447.11-29450.4" + cell \n$106 \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:29451.11-29454.4" + cell \p$105 \p + connect \p_ready_o \p_ready_o + connect \p_valid_i \p_valid_i + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:29455.15-29509.4" + cell \pipe1$107 \pipe1 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cr_a \pipe1_cr_a + connect \cr_a_ok \pipe1_cr_a_ok + connect \muxid \pipe1_muxid + connect \muxid$1 \pipe1_muxid$2 + connect \n_ready_i \pipe1_n_ready_i + connect \n_valid_o \pipe1_n_valid_o + connect \o \pipe1_o + connect \o_ok \pipe1_o_ok + connect \p_ready_o \pipe1_p_ready_o + connect \p_valid_i \pipe1_p_valid_i + connect \ra \pipe1_ra + connect \rb \pipe1_rb + connect \rc \pipe1_rc + connect \sr_op__fn_unit \pipe1_sr_op__fn_unit + connect \sr_op__fn_unit$3 \pipe1_sr_op__fn_unit$4 + connect \sr_op__imm_data__data \pipe1_sr_op__imm_data__data + connect \sr_op__imm_data__data$4 \pipe1_sr_op__imm_data__data$5 + connect \sr_op__imm_data__ok \pipe1_sr_op__imm_data__ok + connect \sr_op__imm_data__ok$5 \pipe1_sr_op__imm_data__ok$6 + connect \sr_op__input_carry \pipe1_sr_op__input_carry + connect \sr_op__input_carry$11 \pipe1_sr_op__input_carry$12 + connect \sr_op__input_cr \pipe1_sr_op__input_cr + connect \sr_op__input_cr$13 \pipe1_sr_op__input_cr$14 + connect \sr_op__insn \pipe1_sr_op__insn + connect \sr_op__insn$17 \pipe1_sr_op__insn$18 + connect \sr_op__insn_type \pipe1_sr_op__insn_type + connect \sr_op__insn_type$2 \pipe1_sr_op__insn_type$3 + connect \sr_op__is_32bit \pipe1_sr_op__is_32bit + connect \sr_op__is_32bit$15 \pipe1_sr_op__is_32bit$16 + connect \sr_op__is_signed \pipe1_sr_op__is_signed + connect \sr_op__is_signed$16 \pipe1_sr_op__is_signed$17 + connect \sr_op__oe__oe \pipe1_sr_op__oe__oe + connect \sr_op__oe__oe$8 \pipe1_sr_op__oe__oe$9 + connect \sr_op__oe__ok \pipe1_sr_op__oe__ok + connect \sr_op__oe__ok$9 \pipe1_sr_op__oe__ok$10 + connect \sr_op__output_carry \pipe1_sr_op__output_carry + connect \sr_op__output_carry$12 \pipe1_sr_op__output_carry$13 + connect \sr_op__output_cr \pipe1_sr_op__output_cr + connect \sr_op__output_cr$14 \pipe1_sr_op__output_cr$15 + connect \sr_op__rc__ok \pipe1_sr_op__rc__ok + connect \sr_op__rc__ok$7 \pipe1_sr_op__rc__ok$8 + connect \sr_op__rc__rc \pipe1_sr_op__rc__rc + connect \sr_op__rc__rc$6 \pipe1_sr_op__rc__rc$7 + connect \sr_op__write_cr0 \pipe1_sr_op__write_cr0 + connect \sr_op__write_cr0$10 \pipe1_sr_op__write_cr0$11 + connect \xer_ca \pipe1_xer_ca + connect \xer_ca$19 \pipe1_xer_ca$20 + connect \xer_ca_ok \pipe1_xer_ca_ok + connect \xer_so \pipe1_xer_so + connect \xer_so$18 \pipe1_xer_so$19 + connect \xer_so_ok \pipe1_xer_so_ok + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:29510.15-29565.4" + cell \pipe2$112 \pipe2 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cr_a \pipe2_cr_a + connect \cr_a$20 \pipe2_cr_a$40 + connect \cr_a_ok \pipe2_cr_a_ok + connect \cr_a_ok$21 \pipe2_cr_a_ok$41 + connect \muxid \pipe2_muxid + connect \muxid$1 \pipe2_muxid$21 + connect \n_ready_i \pipe2_n_ready_i + connect \n_valid_o \pipe2_n_valid_o + connect \o \pipe2_o + connect \o$18 \pipe2_o$38 + connect \o_ok \pipe2_o_ok + connect \o_ok$19 \pipe2_o_ok$39 + connect \p_ready_o \pipe2_p_ready_o + connect \p_valid_i \pipe2_p_valid_i + connect \sr_op__fn_unit \pipe2_sr_op__fn_unit + connect \sr_op__fn_unit$3 \pipe2_sr_op__fn_unit$23 + connect \sr_op__imm_data__data \pipe2_sr_op__imm_data__data + connect \sr_op__imm_data__data$4 \pipe2_sr_op__imm_data__data$24 + connect \sr_op__imm_data__ok \pipe2_sr_op__imm_data__ok + connect \sr_op__imm_data__ok$5 \pipe2_sr_op__imm_data__ok$25 + connect \sr_op__input_carry \pipe2_sr_op__input_carry + connect \sr_op__input_carry$11 \pipe2_sr_op__input_carry$31 + connect \sr_op__input_cr \pipe2_sr_op__input_cr + connect \sr_op__input_cr$13 \pipe2_sr_op__input_cr$33 + connect \sr_op__insn \pipe2_sr_op__insn + connect \sr_op__insn$17 \pipe2_sr_op__insn$37 + connect \sr_op__insn_type \pipe2_sr_op__insn_type + connect \sr_op__insn_type$2 \pipe2_sr_op__insn_type$22 + connect \sr_op__is_32bit \pipe2_sr_op__is_32bit + connect \sr_op__is_32bit$15 \pipe2_sr_op__is_32bit$35 + connect \sr_op__is_signed \pipe2_sr_op__is_signed + connect \sr_op__is_signed$16 \pipe2_sr_op__is_signed$36 + connect \sr_op__oe__oe \pipe2_sr_op__oe__oe + connect \sr_op__oe__oe$8 \pipe2_sr_op__oe__oe$28 + connect \sr_op__oe__ok \pipe2_sr_op__oe__ok + connect \sr_op__oe__ok$9 \pipe2_sr_op__oe__ok$29 + connect \sr_op__output_carry \pipe2_sr_op__output_carry + connect \sr_op__output_carry$12 \pipe2_sr_op__output_carry$32 + connect \sr_op__output_cr \pipe2_sr_op__output_cr + connect \sr_op__output_cr$14 \pipe2_sr_op__output_cr$34 + connect \sr_op__rc__ok \pipe2_sr_op__rc__ok + connect \sr_op__rc__ok$7 \pipe2_sr_op__rc__ok$27 + connect \sr_op__rc__rc \pipe2_sr_op__rc__rc + connect \sr_op__rc__rc$6 \pipe2_sr_op__rc__rc$26 + connect \sr_op__write_cr0 \pipe2_sr_op__write_cr0 + connect \sr_op__write_cr0$10 \pipe2_sr_op__write_cr0$30 + connect \xer_ca \pipe2_xer_ca + connect \xer_ca$22 \pipe2_xer_ca$42 + connect \xer_ca_ok \pipe2_xer_ca_ok + connect \xer_ca_ok$23 \pipe2_xer_ca_ok$43 + connect \xer_so \pipe2_xer_so + connect \xer_so_ok \pipe2_xer_so_ok + end + connect \muxid 2'00 + connect { \xer_ca_ok \xer_ca } { \pipe2_xer_ca_ok$43 \pipe2_xer_ca$42 } + connect { \cr_a_ok \cr_a } { \pipe2_cr_a_ok$41 \pipe2_cr_a$40 } + connect { \o_ok \o } { \pipe2_o_ok$39 \pipe2_o$38 } + connect { \sr_op__insn$60 \sr_op__is_signed$59 \sr_op__is_32bit$58 \sr_op__output_cr$57 \sr_op__input_cr$56 \sr_op__output_carry$55 \sr_op__input_carry$54 \sr_op__write_cr0$53 \sr_op__oe__ok$52 \sr_op__oe__oe$51 \sr_op__rc__ok$50 \sr_op__rc__rc$49 \sr_op__imm_data__ok$48 \sr_op__imm_data__data$47 \sr_op__fn_unit$46 \sr_op__insn_type$45 } { \pipe2_sr_op__insn$37 \pipe2_sr_op__is_signed$36 \pipe2_sr_op__is_32bit$35 \pipe2_sr_op__output_cr$34 \pipe2_sr_op__input_cr$33 \pipe2_sr_op__output_carry$32 \pipe2_sr_op__input_carry$31 \pipe2_sr_op__write_cr0$30 \pipe2_sr_op__oe__ok$29 \pipe2_sr_op__oe__oe$28 \pipe2_sr_op__rc__ok$27 \pipe2_sr_op__rc__rc$26 \pipe2_sr_op__imm_data__ok$25 \pipe2_sr_op__imm_data__data$24 \pipe2_sr_op__fn_unit$23 \pipe2_sr_op__insn_type$22 } + connect \muxid$44 \pipe2_muxid$21 + connect \pipe2_n_ready_i \n_ready_i + connect \n_valid_o \pipe2_n_valid_o + connect \pipe1_xer_ca$20 \xer_ca$1 + connect \pipe1_xer_so$19 \xer_so + connect \pipe1_rc \rc + connect \pipe1_rb \rb + connect \pipe1_ra \ra + connect { \pipe1_sr_op__insn$18 \pipe1_sr_op__is_signed$17 \pipe1_sr_op__is_32bit$16 \pipe1_sr_op__output_cr$15 \pipe1_sr_op__input_cr$14 \pipe1_sr_op__output_carry$13 \pipe1_sr_op__input_carry$12 \pipe1_sr_op__write_cr0$11 \pipe1_sr_op__oe__ok$10 \pipe1_sr_op__oe__oe$9 \pipe1_sr_op__rc__ok$8 \pipe1_sr_op__rc__rc$7 \pipe1_sr_op__imm_data__ok$6 \pipe1_sr_op__imm_data__data$5 \pipe1_sr_op__fn_unit$4 \pipe1_sr_op__insn_type$3 } { \sr_op__insn \sr_op__is_signed \sr_op__is_32bit \sr_op__output_cr \sr_op__input_cr \sr_op__output_carry \sr_op__input_carry \sr_op__write_cr0 \sr_op__oe__ok \sr_op__oe__oe \sr_op__rc__ok \sr_op__rc__rc \sr_op__imm_data__ok \sr_op__imm_data__data \sr_op__fn_unit \sr_op__insn_type } + connect \pipe1_muxid$2 2'00 + connect \p_ready_o \pipe1_p_ready_o + connect \pipe1_p_valid_i \p_valid_i + connect { \pipe2_xer_ca_ok \pipe2_xer_ca } { \pipe1_xer_ca_ok \pipe1_xer_ca } + connect { \pipe2_xer_so_ok \pipe2_xer_so } { \pipe1_xer_so_ok \pipe1_xer_so } + connect { \pipe2_cr_a_ok \pipe2_cr_a } { \pipe1_cr_a_ok \pipe1_cr_a } + connect { \pipe2_o_ok \pipe2_o } { \pipe1_o_ok \pipe1_o } + connect { \pipe2_sr_op__insn \pipe2_sr_op__is_signed \pipe2_sr_op__is_32bit \pipe2_sr_op__output_cr \pipe2_sr_op__input_cr \pipe2_sr_op__output_carry \pipe2_sr_op__input_carry \pipe2_sr_op__write_cr0 \pipe2_sr_op__oe__ok \pipe2_sr_op__oe__oe \pipe2_sr_op__rc__ok \pipe2_sr_op__rc__rc \pipe2_sr_op__imm_data__ok \pipe2_sr_op__imm_data__data \pipe2_sr_op__fn_unit \pipe2_sr_op__insn_type } { \pipe1_sr_op__insn \pipe1_sr_op__is_signed \pipe1_sr_op__is_32bit \pipe1_sr_op__output_cr \pipe1_sr_op__input_cr \pipe1_sr_op__output_carry \pipe1_sr_op__input_carry \pipe1_sr_op__write_cr0 \pipe1_sr_op__oe__ok \pipe1_sr_op__oe__oe \pipe1_sr_op__rc__ok \pipe1_sr_op__rc__rc \pipe1_sr_op__imm_data__ok \pipe1_sr_op__imm_data__data \pipe1_sr_op__fn_unit \pipe1_sr_op__insn_type } + connect \pipe2_muxid \pipe1_muxid + connect \pipe1_n_ready_i \pipe2_p_ready_o + connect \pipe2_p_valid_i \pipe1_n_valid_o +end +attribute \src "libresoc.v:29595.1-30141.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.alu_spr0" +attribute \generator "nMigen" +module \alu_spr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 28 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 7 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 16 \fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 22 \fast1$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 5 \fast1_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire input 9 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire output 8 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 14 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 1 \o_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire output 27 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire input 26 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \pipe_fast1$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \pipe_fast1_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \pipe_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \pipe_muxid$6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire \pipe_n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire \pipe_n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \pipe_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \pipe_o_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire \pipe_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire \pipe_p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_spr1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \pipe_spr1$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \pipe_spr1_ok + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \pipe_spr_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \pipe_spr_op__fn_unit$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe_spr_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe_spr_op__insn$9 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe_spr_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe_spr_op__insn_type$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_spr_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_spr_op__is_32bit$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 \pipe_xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \pipe_xer_ca$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \pipe_xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 \pipe_xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \pipe_xer_ov$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \pipe_xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \pipe_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \pipe_xer_so$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \pipe_xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 20 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 15 \spr1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 21 \spr1$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 6 \spr1_ok + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 11 \spr_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \spr_op__fn_unit$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 12 \spr_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \spr_op__insn$19 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 10 \spr_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \spr_op__insn_type$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \spr_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \spr_op__is_32bit$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 output 19 \xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 input 25 \xer_ca$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 2 \xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 output 18 \xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 input 24 \xer_ov$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 3 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 17 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 23 \xer_so$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 4 \xer_so_ok + attribute \module_not_derived 1 + attribute \src "libresoc.v:30076.10-30079.4" + cell \n$60 \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:30080.10-30083.4" + cell \p$59 \p + connect \p_ready_o \p_ready_o + connect \p_valid_i \p_valid_i + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:30084.13-30119.4" + cell \pipe$61 \pipe + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \fast1 \pipe_fast1 + connect \fast1$7 \pipe_fast1$12 + connect \fast1_ok \pipe_fast1_ok + connect \muxid \pipe_muxid + connect \muxid$1 \pipe_muxid$6 + connect \n_ready_i \pipe_n_ready_i + connect \n_valid_o \pipe_n_valid_o + connect \o \pipe_o + connect \o_ok \pipe_o_ok + connect \p_ready_o \pipe_p_ready_o + connect \p_valid_i \pipe_p_valid_i + connect \ra \pipe_ra + connect \spr1 \pipe_spr1 + connect \spr1$6 \pipe_spr1$11 + connect \spr1_ok \pipe_spr1_ok + connect \spr_op__fn_unit \pipe_spr_op__fn_unit + connect \spr_op__fn_unit$3 \pipe_spr_op__fn_unit$8 + connect \spr_op__insn \pipe_spr_op__insn + connect \spr_op__insn$4 \pipe_spr_op__insn$9 + connect \spr_op__insn_type \pipe_spr_op__insn_type + connect \spr_op__insn_type$2 \pipe_spr_op__insn_type$7 + connect \spr_op__is_32bit \pipe_spr_op__is_32bit + connect \spr_op__is_32bit$5 \pipe_spr_op__is_32bit$10 + connect \xer_ca \pipe_xer_ca + connect \xer_ca$10 \pipe_xer_ca$15 + connect \xer_ca_ok \pipe_xer_ca_ok + connect \xer_ov \pipe_xer_ov + connect \xer_ov$9 \pipe_xer_ov$14 + connect \xer_ov_ok \pipe_xer_ov_ok + connect \xer_so \pipe_xer_so + connect \xer_so$8 \pipe_xer_so$13 + connect \xer_so_ok \pipe_xer_so_ok + end + connect \muxid 2'00 + connect { \xer_ca_ok \xer_ca } { \pipe_xer_ca_ok \pipe_xer_ca$15 } + connect { \xer_ov_ok \xer_ov } { \pipe_xer_ov_ok \pipe_xer_ov$14 } + connect { \xer_so_ok \xer_so } { \pipe_xer_so_ok \pipe_xer_so$13 } + connect { \fast1_ok \fast1 } { \pipe_fast1_ok \pipe_fast1$12 } + connect { \spr1_ok \spr1 } { \pipe_spr1_ok \pipe_spr1$11 } + connect { \o_ok \o } { \pipe_o_ok \pipe_o } + connect { \spr_op__is_32bit$20 \spr_op__insn$19 \spr_op__fn_unit$18 \spr_op__insn_type$17 } { \pipe_spr_op__is_32bit$10 \pipe_spr_op__insn$9 \pipe_spr_op__fn_unit$8 \pipe_spr_op__insn_type$7 } + connect \muxid$16 \pipe_muxid$6 + connect \pipe_n_ready_i \n_ready_i + connect \n_valid_o \pipe_n_valid_o + connect \pipe_xer_ca \xer_ca$5 + connect \pipe_xer_ov \xer_ov$4 + connect \pipe_xer_so \xer_so$3 + connect \pipe_fast1 \fast1$2 + connect \pipe_spr1 \spr1$1 + connect \pipe_ra \ra + connect { \pipe_spr_op__is_32bit \pipe_spr_op__insn \pipe_spr_op__fn_unit \pipe_spr_op__insn_type } { \spr_op__is_32bit \spr_op__insn \spr_op__fn_unit \spr_op__insn_type } + connect \pipe_muxid 2'00 + connect \p_ready_o \pipe_p_ready_o + connect \pipe_p_valid_i \p_valid_i +end +attribute \src "libresoc.v:30145.1-30708.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.alu_trap0" +attribute \generator "nMigen" +module \alu_trap0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 28 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 6 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 18 \fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 24 \fast1$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 2 \fast1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 19 \fast2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 25 \fast2$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 3 \fast2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 21 \msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 5 \msr_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$14 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire input 8 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire output 7 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 20 \nia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 4 \nia_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 17 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 1 \o_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire output 27 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire input 26 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \pipe_fast1$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \pipe_fast1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_fast2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \pipe_fast2$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \pipe_fast2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \pipe_msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \pipe_msr_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \pipe_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \pipe_muxid$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire \pipe_n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire \pipe_n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \pipe_nia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \pipe_nia_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \pipe_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \pipe_o_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire \pipe_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire \pipe_p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe_trap_op__cia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe_trap_op__cia$8 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \pipe_trap_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \pipe_trap_op__fn_unit$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe_trap_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe_trap_op__insn$6 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe_trap_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe_trap_op__insn_type$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_trap_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_trap_op__is_32bit$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe_trap_op__msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe_trap_op__msr$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \pipe_trap_op__trapaddr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \pipe_trap_op__trapaddr$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe_trap_op__traptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe_trap_op__traptype$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 22 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 23 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 13 \trap_op__cia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \trap_op__cia$19 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 10 \trap_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \trap_op__fn_unit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 11 \trap_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \trap_op__insn$17 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 9 \trap_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \trap_op__insn_type$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \trap_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \trap_op__is_32bit$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 12 \trap_op__msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \trap_op__msr$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 input 16 \trap_op__trapaddr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \trap_op__trapaddr$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 15 \trap_op__traptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \trap_op__traptype$21 + attribute \module_not_derived 1 + attribute \src "libresoc.v:30642.10-30645.4" + cell \n$31 \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:30646.10-30649.4" + cell \p$30 \p + connect \p_ready_o \p_ready_o + connect \p_valid_i \p_valid_i + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:30650.13-30689.4" + cell \pipe$32 \pipe + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \fast1 \pipe_fast1 + connect \fast1$10 \pipe_fast1$12 + connect \fast1_ok \pipe_fast1_ok + connect \fast2 \pipe_fast2 + connect \fast2$11 \pipe_fast2$13 + connect \fast2_ok \pipe_fast2_ok + connect \msr \pipe_msr + connect \msr_ok \pipe_msr_ok + connect \muxid \pipe_muxid + connect \muxid$1 \pipe_muxid$3 + connect \n_ready_i \pipe_n_ready_i + connect \n_valid_o \pipe_n_valid_o + connect \nia \pipe_nia + connect \nia_ok \pipe_nia_ok + connect \o \pipe_o + connect \o_ok \pipe_o_ok + connect \p_ready_o \pipe_p_ready_o + connect \p_valid_i \pipe_p_valid_i + connect \ra \pipe_ra + connect \rb \pipe_rb + connect \trap_op__cia \pipe_trap_op__cia + connect \trap_op__cia$6 \pipe_trap_op__cia$8 + connect \trap_op__fn_unit \pipe_trap_op__fn_unit + connect \trap_op__fn_unit$3 \pipe_trap_op__fn_unit$5 + connect \trap_op__insn \pipe_trap_op__insn + connect \trap_op__insn$4 \pipe_trap_op__insn$6 + connect \trap_op__insn_type \pipe_trap_op__insn_type + connect \trap_op__insn_type$2 \pipe_trap_op__insn_type$4 + connect \trap_op__is_32bit \pipe_trap_op__is_32bit + connect \trap_op__is_32bit$7 \pipe_trap_op__is_32bit$9 + connect \trap_op__msr \pipe_trap_op__msr + connect \trap_op__msr$5 \pipe_trap_op__msr$7 + connect \trap_op__trapaddr \pipe_trap_op__trapaddr + connect \trap_op__trapaddr$9 \pipe_trap_op__trapaddr$11 + connect \trap_op__traptype \pipe_trap_op__traptype + connect \trap_op__traptype$8 \pipe_trap_op__traptype$10 + end + connect \muxid 2'00 + connect { \msr_ok \msr } { \pipe_msr_ok \pipe_msr } + connect { \nia_ok \nia } { \pipe_nia_ok \pipe_nia } + connect { \fast2_ok \fast2 } { \pipe_fast2_ok \pipe_fast2$13 } + connect { \fast1_ok \fast1 } { \pipe_fast1_ok \pipe_fast1$12 } + connect { \o_ok \o } { \pipe_o_ok \pipe_o } + connect { \trap_op__trapaddr$22 \trap_op__traptype$21 \trap_op__is_32bit$20 \trap_op__cia$19 \trap_op__msr$18 \trap_op__insn$17 \trap_op__fn_unit$16 \trap_op__insn_type$15 } { \pipe_trap_op__trapaddr$11 \pipe_trap_op__traptype$10 \pipe_trap_op__is_32bit$9 \pipe_trap_op__cia$8 \pipe_trap_op__msr$7 \pipe_trap_op__insn$6 \pipe_trap_op__fn_unit$5 \pipe_trap_op__insn_type$4 } + connect \muxid$14 \pipe_muxid$3 + connect \pipe_n_ready_i \n_ready_i + connect \n_valid_o \pipe_n_valid_o + connect \pipe_fast2 \fast2$2 + connect \pipe_fast1 \fast1$1 + connect \pipe_rb \rb + connect \pipe_ra \ra + connect { \pipe_trap_op__trapaddr \pipe_trap_op__traptype \pipe_trap_op__is_32bit \pipe_trap_op__cia \pipe_trap_op__msr \pipe_trap_op__insn \pipe_trap_op__fn_unit \pipe_trap_op__insn_type } { \trap_op__trapaddr \trap_op__traptype \trap_op__is_32bit \trap_op__cia \trap_op__msr \trap_op__insn \trap_op__fn_unit \trap_op__insn_type } + connect \pipe_muxid 2'00 + connect \p_ready_o \pipe_p_ready_o + connect \pipe_p_valid_i \p_valid_i +end +attribute \src "libresoc.v:30712.1-30770.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alui_l" +attribute \generator "nMigen" +module \alui_l + attribute \src "libresoc.v:30713.7-30713.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:30758.3-30766.6" + wire $0\q_int$next[0:0]$1000 + attribute \src "libresoc.v:30756.3-30757.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:30758.3-30766.6" + wire $1\q_int$next[0:0]$1001 + attribute \src "libresoc.v:30737.7-30737.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:30748.17-30748.96" + wire $and$libresoc.v:30748$990_Y + attribute \src "libresoc.v:30753.17-30753.96" + wire $and$libresoc.v:30753$995_Y + attribute \src "libresoc.v:30750.18-30750.94" + wire $not$libresoc.v:30750$992_Y + attribute \src "libresoc.v:30752.17-30752.93" + wire $not$libresoc.v:30752$994_Y + attribute \src "libresoc.v:30755.17-30755.93" + wire $not$libresoc.v:30755$997_Y + attribute \src "libresoc.v:30749.18-30749.99" + wire $or$libresoc.v:30749$991_Y + attribute \src "libresoc.v:30751.18-30751.100" + wire $or$libresoc.v:30751$993_Y + attribute \src "libresoc.v:30754.17-30754.98" + wire $or$libresoc.v:30754$996_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 1 \coresync_rst + attribute \src "libresoc.v:30713.7-30713.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 2 \q_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 4 \s_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$libresoc.v:30748$990 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:30748$990_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:30753$995 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:30753$995_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:30750$992 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alui + connect \Y $not$libresoc.v:30750$992_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:30752$994 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alui + connect \Y $not$libresoc.v:30752$994_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:30755$997 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alui + connect \Y $not$libresoc.v:30755$997_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:30749$991 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_alui + connect \Y $or$libresoc.v:30749$991_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:30751$993 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alui + connect \B \q_int + connect \Y $or$libresoc.v:30751$993_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:30754$996 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_alui + connect \Y $or$libresoc.v:30754$996_Y + end + attribute \src "libresoc.v:30713.7-30713.20" + process $proc$libresoc.v:30713$1002 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:30737.7-30737.19" + process $proc$libresoc.v:30737$1003 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:30756.3-30757.27" + process $proc$libresoc.v:30756$998 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:30758.3-30766.6" + process $proc$libresoc.v:30758$999 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$1000 $1\q_int$next[0:0]$1001 + attribute \src "libresoc.v:30759.5-30759.29" + switch \initial + attribute \src "libresoc.v:30759.9-30759.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$1001 1'0 + case + assign $1\q_int$next[0:0]$1001 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$1000 + end + connect \$9 $and$libresoc.v:30748$990_Y + connect \$11 $or$libresoc.v:30749$991_Y + connect \$13 $not$libresoc.v:30750$992_Y + connect \$15 $or$libresoc.v:30751$993_Y + connect \$1 $not$libresoc.v:30752$994_Y + connect \$3 $and$libresoc.v:30753$995_Y + connect \$5 $or$libresoc.v:30754$996_Y + connect \$7 $not$libresoc.v:30755$997_Y + connect \qlq_alui \$15 + connect \qn_alui \$13 + connect \q_alui \$11 +end +attribute \src "libresoc.v:30774.1-30832.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alui_l" +attribute \generator "nMigen" +module \alui_l$103 + attribute \src "libresoc.v:30775.7-30775.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:30820.3-30828.6" + wire $0\q_int$next[0:0]$1014 + attribute \src "libresoc.v:30818.3-30819.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:30820.3-30828.6" + wire $1\q_int$next[0:0]$1015 + attribute \src "libresoc.v:30799.7-30799.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:30810.17-30810.96" + wire $and$libresoc.v:30810$1004_Y + attribute \src "libresoc.v:30815.17-30815.96" + wire $and$libresoc.v:30815$1009_Y + attribute \src "libresoc.v:30812.18-30812.94" + wire $not$libresoc.v:30812$1006_Y + attribute \src "libresoc.v:30814.17-30814.93" + wire $not$libresoc.v:30814$1008_Y + attribute \src "libresoc.v:30817.17-30817.93" + wire $not$libresoc.v:30817$1011_Y + attribute \src "libresoc.v:30811.18-30811.99" + wire $or$libresoc.v:30811$1005_Y + attribute \src "libresoc.v:30813.18-30813.100" + wire $or$libresoc.v:30813$1007_Y + attribute \src "libresoc.v:30816.17-30816.98" + wire $or$libresoc.v:30816$1010_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 1 \coresync_rst + attribute \src "libresoc.v:30775.7-30775.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 2 \q_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 4 \s_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$libresoc.v:30810$1004 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:30810$1004_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:30815$1009 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:30815$1009_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:30812$1006 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alui + connect \Y $not$libresoc.v:30812$1006_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:30814$1008 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alui + connect \Y $not$libresoc.v:30814$1008_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:30817$1011 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alui + connect \Y $not$libresoc.v:30817$1011_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:30811$1005 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_alui + connect \Y $or$libresoc.v:30811$1005_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:30813$1007 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alui + connect \B \q_int + connect \Y $or$libresoc.v:30813$1007_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:30816$1010 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_alui + connect \Y $or$libresoc.v:30816$1010_Y + end + attribute \src "libresoc.v:30775.7-30775.20" + process $proc$libresoc.v:30775$1016 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:30799.7-30799.19" + process $proc$libresoc.v:30799$1017 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:30818.3-30819.27" + process $proc$libresoc.v:30818$1012 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:30820.3-30828.6" + process $proc$libresoc.v:30820$1013 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$1014 $1\q_int$next[0:0]$1015 + attribute \src "libresoc.v:30821.5-30821.29" + switch \initial + attribute \src "libresoc.v:30821.9-30821.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$1015 1'0 + case + assign $1\q_int$next[0:0]$1015 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$1014 + end + connect \$9 $and$libresoc.v:30810$1004_Y + connect \$11 $or$libresoc.v:30811$1005_Y + connect \$13 $not$libresoc.v:30812$1006_Y + connect \$15 $or$libresoc.v:30813$1007_Y + connect \$1 $not$libresoc.v:30814$1008_Y + connect \$3 $and$libresoc.v:30815$1009_Y + connect \$5 $or$libresoc.v:30816$1010_Y + connect \$7 $not$libresoc.v:30817$1011_Y + connect \qlq_alui \$15 + connect \qn_alui \$13 + connect \q_alui \$11 +end +attribute \src "libresoc.v:30836.1-30894.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alui_l" +attribute \generator "nMigen" +module \alui_l$121 + attribute \src "libresoc.v:30837.7-30837.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:30882.3-30890.6" + wire $0\q_int$next[0:0]$1028 + attribute \src "libresoc.v:30880.3-30881.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:30882.3-30890.6" + wire $1\q_int$next[0:0]$1029 + attribute \src "libresoc.v:30861.7-30861.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:30872.17-30872.96" + wire $and$libresoc.v:30872$1018_Y + attribute \src "libresoc.v:30877.17-30877.96" + wire $and$libresoc.v:30877$1023_Y + attribute \src "libresoc.v:30874.18-30874.94" + wire $not$libresoc.v:30874$1020_Y + attribute \src "libresoc.v:30876.17-30876.93" + wire $not$libresoc.v:30876$1022_Y + attribute \src "libresoc.v:30879.17-30879.93" + wire $not$libresoc.v:30879$1025_Y + attribute \src "libresoc.v:30873.18-30873.99" + wire $or$libresoc.v:30873$1019_Y + attribute \src "libresoc.v:30875.18-30875.100" + wire $or$libresoc.v:30875$1021_Y + attribute \src "libresoc.v:30878.17-30878.98" + wire $or$libresoc.v:30878$1024_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 1 \coresync_rst + attribute \src "libresoc.v:30837.7-30837.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 2 \q_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 4 \s_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$libresoc.v:30872$1018 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:30872$1018_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:30877$1023 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:30877$1023_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:30874$1020 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alui + connect \Y $not$libresoc.v:30874$1020_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:30876$1022 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alui + connect \Y $not$libresoc.v:30876$1022_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:30879$1025 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alui + connect \Y $not$libresoc.v:30879$1025_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:30873$1019 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_alui + connect \Y $or$libresoc.v:30873$1019_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:30875$1021 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alui + connect \B \q_int + connect \Y $or$libresoc.v:30875$1021_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:30878$1024 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_alui + connect \Y $or$libresoc.v:30878$1024_Y + end + attribute \src "libresoc.v:30837.7-30837.20" + process $proc$libresoc.v:30837$1030 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:30861.7-30861.19" + process $proc$libresoc.v:30861$1031 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:30880.3-30881.27" + process $proc$libresoc.v:30880$1026 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:30882.3-30890.6" + process $proc$libresoc.v:30882$1027 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$1028 $1\q_int$next[0:0]$1029 + attribute \src "libresoc.v:30883.5-30883.29" + switch \initial + attribute \src "libresoc.v:30883.9-30883.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$1029 1'0 + case + assign $1\q_int$next[0:0]$1029 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$1028 + end + connect \$9 $and$libresoc.v:30872$1018_Y + connect \$11 $or$libresoc.v:30873$1019_Y + connect \$13 $not$libresoc.v:30874$1020_Y + connect \$15 $or$libresoc.v:30875$1021_Y + connect \$1 $not$libresoc.v:30876$1022_Y + connect \$3 $and$libresoc.v:30877$1023_Y + connect \$5 $or$libresoc.v:30878$1024_Y + connect \$7 $not$libresoc.v:30879$1025_Y + connect \qlq_alui \$15 + connect \qn_alui \$13 + connect \q_alui \$11 +end +attribute \src "libresoc.v:30898.1-30956.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.alui_l" +attribute \generator "nMigen" +module \alui_l$15 + attribute \src "libresoc.v:30899.7-30899.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:30944.3-30952.6" + wire $0\q_int$next[0:0]$1042 + attribute \src "libresoc.v:30942.3-30943.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:30944.3-30952.6" + wire $1\q_int$next[0:0]$1043 + attribute \src "libresoc.v:30923.7-30923.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:30934.17-30934.96" + wire $and$libresoc.v:30934$1032_Y + attribute \src "libresoc.v:30939.17-30939.96" + wire $and$libresoc.v:30939$1037_Y + attribute \src "libresoc.v:30936.18-30936.94" + wire $not$libresoc.v:30936$1034_Y + attribute \src "libresoc.v:30938.17-30938.93" + wire $not$libresoc.v:30938$1036_Y + attribute \src "libresoc.v:30941.17-30941.93" + wire $not$libresoc.v:30941$1039_Y + attribute \src "libresoc.v:30935.18-30935.99" + wire $or$libresoc.v:30935$1033_Y + attribute \src "libresoc.v:30937.18-30937.100" + wire $or$libresoc.v:30937$1035_Y + attribute \src "libresoc.v:30940.17-30940.98" + wire $or$libresoc.v:30940$1038_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 1 \coresync_rst + attribute \src "libresoc.v:30899.7-30899.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 2 \q_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 4 \s_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$libresoc.v:30934$1032 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:30934$1032_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:30939$1037 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:30939$1037_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:30936$1034 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alui + connect \Y $not$libresoc.v:30936$1034_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:30938$1036 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alui + connect \Y $not$libresoc.v:30938$1036_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:30941$1039 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alui + connect \Y $not$libresoc.v:30941$1039_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:30935$1033 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_alui + connect \Y $or$libresoc.v:30935$1033_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:30937$1035 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alui + connect \B \q_int + connect \Y $or$libresoc.v:30937$1035_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:30940$1038 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_alui + connect \Y $or$libresoc.v:30940$1038_Y + end + attribute \src "libresoc.v:30899.7-30899.20" + process $proc$libresoc.v:30899$1044 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:30923.7-30923.19" + process $proc$libresoc.v:30923$1045 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:30942.3-30943.27" + process $proc$libresoc.v:30942$1040 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:30944.3-30952.6" + process $proc$libresoc.v:30944$1041 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$1042 $1\q_int$next[0:0]$1043 + attribute \src "libresoc.v:30945.5-30945.29" + switch \initial + attribute \src "libresoc.v:30945.9-30945.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$1043 1'0 + case + assign $1\q_int$next[0:0]$1043 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$1042 + end + connect \$9 $and$libresoc.v:30934$1032_Y + connect \$11 $or$libresoc.v:30935$1033_Y + connect \$13 $not$libresoc.v:30936$1034_Y + connect \$15 $or$libresoc.v:30937$1035_Y + connect \$1 $not$libresoc.v:30938$1036_Y + connect \$3 $and$libresoc.v:30939$1037_Y + connect \$5 $or$libresoc.v:30940$1038_Y + connect \$7 $not$libresoc.v:30941$1039_Y + connect \qlq_alui \$15 + connect \qn_alui \$13 + connect \q_alui \$11 +end +attribute \src "libresoc.v:30960.1-31018.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.alui_l" +attribute \generator "nMigen" +module \alui_l$28 + attribute \src "libresoc.v:30961.7-30961.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:31006.3-31014.6" + wire $0\q_int$next[0:0]$1056 + attribute \src "libresoc.v:31004.3-31005.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:31006.3-31014.6" + wire $1\q_int$next[0:0]$1057 + attribute \src "libresoc.v:30985.7-30985.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:30996.17-30996.96" + wire $and$libresoc.v:30996$1046_Y + attribute \src "libresoc.v:31001.17-31001.96" + wire $and$libresoc.v:31001$1051_Y + attribute \src "libresoc.v:30998.18-30998.94" + wire $not$libresoc.v:30998$1048_Y + attribute \src "libresoc.v:31000.17-31000.93" + wire $not$libresoc.v:31000$1050_Y + attribute \src "libresoc.v:31003.17-31003.93" + wire $not$libresoc.v:31003$1053_Y + attribute \src "libresoc.v:30997.18-30997.99" + wire $or$libresoc.v:30997$1047_Y + attribute \src "libresoc.v:30999.18-30999.100" + wire $or$libresoc.v:30999$1049_Y + attribute \src "libresoc.v:31002.17-31002.98" + wire $or$libresoc.v:31002$1052_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 1 \coresync_rst + attribute \src "libresoc.v:30961.7-30961.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 2 \q_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 4 \s_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$libresoc.v:30996$1046 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:30996$1046_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:31001$1051 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:31001$1051_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:30998$1048 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alui + connect \Y $not$libresoc.v:30998$1048_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:31000$1050 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alui + connect \Y $not$libresoc.v:31000$1050_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:31003$1053 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alui + connect \Y $not$libresoc.v:31003$1053_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:30997$1047 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_alui + connect \Y $or$libresoc.v:30997$1047_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:30999$1049 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alui + connect \B \q_int + connect \Y $or$libresoc.v:30999$1049_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:31002$1052 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_alui + connect \Y $or$libresoc.v:31002$1052_Y + end + attribute \src "libresoc.v:30961.7-30961.20" + process $proc$libresoc.v:30961$1058 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:30985.7-30985.19" + process $proc$libresoc.v:30985$1059 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:31004.3-31005.27" + process $proc$libresoc.v:31004$1054 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:31006.3-31014.6" + process $proc$libresoc.v:31006$1055 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$1056 $1\q_int$next[0:0]$1057 + attribute \src "libresoc.v:31007.5-31007.29" + switch \initial + attribute \src "libresoc.v:31007.9-31007.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$1057 1'0 + case + assign $1\q_int$next[0:0]$1057 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$1056 + end + connect \$9 $and$libresoc.v:30996$1046_Y + connect \$11 $or$libresoc.v:30997$1047_Y + connect \$13 $not$libresoc.v:30998$1048_Y + connect \$15 $or$libresoc.v:30999$1049_Y + connect \$1 $not$libresoc.v:31000$1050_Y + connect \$3 $and$libresoc.v:31001$1051_Y + connect \$5 $or$libresoc.v:31002$1052_Y + connect \$7 $not$libresoc.v:31003$1053_Y + connect \qlq_alui \$15 + connect \qn_alui \$13 + connect \q_alui \$11 +end +attribute \src "libresoc.v:31022.1-31080.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.alui_l" +attribute \generator "nMigen" +module \alui_l$41 + attribute \src "libresoc.v:31023.7-31023.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:31068.3-31076.6" + wire $0\q_int$next[0:0]$1070 + attribute \src "libresoc.v:31066.3-31067.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:31068.3-31076.6" + wire $1\q_int$next[0:0]$1071 + attribute \src "libresoc.v:31047.7-31047.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:31058.17-31058.96" + wire $and$libresoc.v:31058$1060_Y + attribute \src "libresoc.v:31063.17-31063.96" + wire $and$libresoc.v:31063$1065_Y + attribute \src "libresoc.v:31060.18-31060.94" + wire $not$libresoc.v:31060$1062_Y + attribute \src "libresoc.v:31062.17-31062.93" + wire $not$libresoc.v:31062$1064_Y + attribute \src "libresoc.v:31065.17-31065.93" + wire $not$libresoc.v:31065$1067_Y + attribute \src "libresoc.v:31059.18-31059.99" + wire $or$libresoc.v:31059$1061_Y + attribute \src "libresoc.v:31061.18-31061.100" + wire $or$libresoc.v:31061$1063_Y + attribute \src "libresoc.v:31064.17-31064.98" + wire $or$libresoc.v:31064$1066_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 1 \coresync_rst + attribute \src "libresoc.v:31023.7-31023.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 2 \q_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 4 \s_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$libresoc.v:31058$1060 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:31058$1060_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:31063$1065 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:31063$1065_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:31060$1062 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alui + connect \Y $not$libresoc.v:31060$1062_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:31062$1064 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alui + connect \Y $not$libresoc.v:31062$1064_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:31065$1067 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alui + connect \Y $not$libresoc.v:31065$1067_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:31059$1061 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_alui + connect \Y $or$libresoc.v:31059$1061_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:31061$1063 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alui + connect \B \q_int + connect \Y $or$libresoc.v:31061$1063_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:31064$1066 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_alui + connect \Y $or$libresoc.v:31064$1066_Y + end + attribute \src "libresoc.v:31023.7-31023.20" + process $proc$libresoc.v:31023$1072 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:31047.7-31047.19" + process $proc$libresoc.v:31047$1073 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:31066.3-31067.27" + process $proc$libresoc.v:31066$1068 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:31068.3-31076.6" + process $proc$libresoc.v:31068$1069 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$1070 $1\q_int$next[0:0]$1071 + attribute \src "libresoc.v:31069.5-31069.29" + switch \initial + attribute \src "libresoc.v:31069.9-31069.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$1071 1'0 + case + assign $1\q_int$next[0:0]$1071 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$1070 + end + connect \$9 $and$libresoc.v:31058$1060_Y + connect \$11 $or$libresoc.v:31059$1061_Y + connect \$13 $not$libresoc.v:31060$1062_Y + connect \$15 $or$libresoc.v:31061$1063_Y + connect \$1 $not$libresoc.v:31062$1064_Y + connect \$3 $and$libresoc.v:31063$1065_Y + connect \$5 $or$libresoc.v:31064$1066_Y + connect \$7 $not$libresoc.v:31065$1067_Y + connect \qlq_alui \$15 + connect \qn_alui \$13 + connect \q_alui \$11 +end +attribute \src "libresoc.v:31084.1-31142.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alui_l" +attribute \generator "nMigen" +module \alui_l$57 + attribute \src "libresoc.v:31085.7-31085.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:31130.3-31138.6" + wire $0\q_int$next[0:0]$1084 + attribute \src "libresoc.v:31128.3-31129.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:31130.3-31138.6" + wire $1\q_int$next[0:0]$1085 + attribute \src "libresoc.v:31109.7-31109.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:31120.17-31120.96" + wire $and$libresoc.v:31120$1074_Y + attribute \src "libresoc.v:31125.17-31125.96" + wire $and$libresoc.v:31125$1079_Y + attribute \src "libresoc.v:31122.18-31122.94" + wire $not$libresoc.v:31122$1076_Y + attribute \src "libresoc.v:31124.17-31124.93" + wire $not$libresoc.v:31124$1078_Y + attribute \src "libresoc.v:31127.17-31127.93" + wire $not$libresoc.v:31127$1081_Y + attribute \src "libresoc.v:31121.18-31121.99" + wire $or$libresoc.v:31121$1075_Y + attribute \src "libresoc.v:31123.18-31123.100" + wire $or$libresoc.v:31123$1077_Y + attribute \src "libresoc.v:31126.17-31126.98" + wire $or$libresoc.v:31126$1080_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 1 \coresync_rst + attribute \src "libresoc.v:31085.7-31085.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 2 \q_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 4 \s_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$libresoc.v:31120$1074 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:31120$1074_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:31125$1079 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:31125$1079_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:31122$1076 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alui + connect \Y $not$libresoc.v:31122$1076_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:31124$1078 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alui + connect \Y $not$libresoc.v:31124$1078_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:31127$1081 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alui + connect \Y $not$libresoc.v:31127$1081_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:31121$1075 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_alui + connect \Y $or$libresoc.v:31121$1075_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:31123$1077 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alui + connect \B \q_int + connect \Y $or$libresoc.v:31123$1077_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:31126$1080 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_alui + connect \Y $or$libresoc.v:31126$1080_Y + end + attribute \src "libresoc.v:31085.7-31085.20" + process $proc$libresoc.v:31085$1086 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:31109.7-31109.19" + process $proc$libresoc.v:31109$1087 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:31128.3-31129.27" + process $proc$libresoc.v:31128$1082 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:31130.3-31138.6" + process $proc$libresoc.v:31130$1083 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$1084 $1\q_int$next[0:0]$1085 + attribute \src "libresoc.v:31131.5-31131.29" + switch \initial + attribute \src "libresoc.v:31131.9-31131.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$1085 1'0 + case + assign $1\q_int$next[0:0]$1085 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$1084 + end + connect \$9 $and$libresoc.v:31120$1074_Y + connect \$11 $or$libresoc.v:31121$1075_Y + connect \$13 $not$libresoc.v:31122$1076_Y + connect \$15 $or$libresoc.v:31123$1077_Y + connect \$1 $not$libresoc.v:31124$1078_Y + connect \$3 $and$libresoc.v:31125$1079_Y + connect \$5 $or$libresoc.v:31126$1080_Y + connect \$7 $not$libresoc.v:31127$1081_Y + connect \qlq_alui \$15 + connect \qn_alui \$13 + connect \q_alui \$11 +end +attribute \src "libresoc.v:31146.1-31204.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.alui_l" +attribute \generator "nMigen" +module \alui_l$69 + attribute \src "libresoc.v:31147.7-31147.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:31192.3-31200.6" + wire $0\q_int$next[0:0]$1098 + attribute \src "libresoc.v:31190.3-31191.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:31192.3-31200.6" + wire $1\q_int$next[0:0]$1099 + attribute \src "libresoc.v:31171.7-31171.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:31182.17-31182.96" + wire $and$libresoc.v:31182$1088_Y + attribute \src "libresoc.v:31187.17-31187.96" + wire $and$libresoc.v:31187$1093_Y + attribute \src "libresoc.v:31184.18-31184.94" + wire $not$libresoc.v:31184$1090_Y + attribute \src "libresoc.v:31186.17-31186.93" + wire $not$libresoc.v:31186$1092_Y + attribute \src "libresoc.v:31189.17-31189.93" + wire $not$libresoc.v:31189$1095_Y + attribute \src "libresoc.v:31183.18-31183.99" + wire $or$libresoc.v:31183$1089_Y + attribute \src "libresoc.v:31185.18-31185.100" + wire $or$libresoc.v:31185$1091_Y + attribute \src "libresoc.v:31188.17-31188.98" + wire $or$libresoc.v:31188$1094_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 1 \coresync_rst + attribute \src "libresoc.v:31147.7-31147.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 2 \q_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 4 \s_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$libresoc.v:31182$1088 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:31182$1088_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:31187$1093 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:31187$1093_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:31184$1090 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alui + connect \Y $not$libresoc.v:31184$1090_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:31186$1092 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alui + connect \Y $not$libresoc.v:31186$1092_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:31189$1095 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alui + connect \Y $not$libresoc.v:31189$1095_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:31183$1089 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_alui + connect \Y $or$libresoc.v:31183$1089_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:31185$1091 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alui + connect \B \q_int + connect \Y $or$libresoc.v:31185$1091_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:31188$1094 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_alui + connect \Y $or$libresoc.v:31188$1094_Y + end + attribute \src "libresoc.v:31147.7-31147.20" + process $proc$libresoc.v:31147$1100 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:31171.7-31171.19" + process $proc$libresoc.v:31171$1101 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:31190.3-31191.27" + process $proc$libresoc.v:31190$1096 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:31192.3-31200.6" + process $proc$libresoc.v:31192$1097 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$1098 $1\q_int$next[0:0]$1099 + attribute \src "libresoc.v:31193.5-31193.29" + switch \initial + attribute \src "libresoc.v:31193.9-31193.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$1099 1'0 + case + assign $1\q_int$next[0:0]$1099 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$1098 + end + connect \$9 $and$libresoc.v:31182$1088_Y + connect \$11 $or$libresoc.v:31183$1089_Y + connect \$13 $not$libresoc.v:31184$1090_Y + connect \$15 $or$libresoc.v:31185$1091_Y + connect \$1 $not$libresoc.v:31186$1092_Y + connect \$3 $and$libresoc.v:31187$1093_Y + connect \$5 $or$libresoc.v:31188$1094_Y + connect \$7 $not$libresoc.v:31189$1095_Y + connect \qlq_alui \$15 + connect \qn_alui \$13 + connect \q_alui \$11 +end +attribute \src "libresoc.v:31208.1-31266.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alui_l" +attribute \generator "nMigen" +module \alui_l$86 + attribute \src "libresoc.v:31209.7-31209.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:31254.3-31262.6" + wire $0\q_int$next[0:0]$1112 + attribute \src "libresoc.v:31252.3-31253.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:31254.3-31262.6" + wire $1\q_int$next[0:0]$1113 + attribute \src "libresoc.v:31233.7-31233.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:31244.17-31244.96" + wire $and$libresoc.v:31244$1102_Y + attribute \src "libresoc.v:31249.17-31249.96" + wire $and$libresoc.v:31249$1107_Y + attribute \src "libresoc.v:31246.18-31246.94" + wire $not$libresoc.v:31246$1104_Y + attribute \src "libresoc.v:31248.17-31248.93" + wire $not$libresoc.v:31248$1106_Y + attribute \src "libresoc.v:31251.17-31251.93" + wire $not$libresoc.v:31251$1109_Y + attribute \src "libresoc.v:31245.18-31245.99" + wire $or$libresoc.v:31245$1103_Y + attribute \src "libresoc.v:31247.18-31247.100" + wire $or$libresoc.v:31247$1105_Y + attribute \src "libresoc.v:31250.17-31250.98" + wire $or$libresoc.v:31250$1108_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 1 \coresync_rst + attribute \src "libresoc.v:31209.7-31209.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 2 \q_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 4 \s_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$libresoc.v:31244$1102 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:31244$1102_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:31249$1107 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:31249$1107_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:31246$1104 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alui + connect \Y $not$libresoc.v:31246$1104_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:31248$1106 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alui + connect \Y $not$libresoc.v:31248$1106_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:31251$1109 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alui + connect \Y $not$libresoc.v:31251$1109_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:31245$1103 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_alui + connect \Y $or$libresoc.v:31245$1103_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:31247$1105 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alui + connect \B \q_int + connect \Y $or$libresoc.v:31247$1105_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:31250$1108 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_alui + connect \Y $or$libresoc.v:31250$1108_Y + end + attribute \src "libresoc.v:31209.7-31209.20" + process $proc$libresoc.v:31209$1114 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:31233.7-31233.19" + process $proc$libresoc.v:31233$1115 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:31252.3-31253.27" + process $proc$libresoc.v:31252$1110 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:31254.3-31262.6" + process $proc$libresoc.v:31254$1111 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$1112 $1\q_int$next[0:0]$1113 + attribute \src "libresoc.v:31255.5-31255.29" + switch \initial + attribute \src "libresoc.v:31255.9-31255.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$1113 1'0 + case + assign $1\q_int$next[0:0]$1113 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$1112 + end + connect \$9 $and$libresoc.v:31244$1102_Y + connect \$11 $or$libresoc.v:31245$1103_Y + connect \$13 $not$libresoc.v:31246$1104_Y + connect \$15 $or$libresoc.v:31247$1105_Y + connect \$1 $not$libresoc.v:31248$1106_Y + connect \$3 $and$libresoc.v:31249$1107_Y + connect \$5 $or$libresoc.v:31250$1108_Y + connect \$7 $not$libresoc.v:31251$1109_Y + connect \qlq_alui \$15 + connect \qn_alui \$13 + connect \q_alui \$11 +end +attribute \src "libresoc.v:31270.1-32614.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_logical0.logical_pipe1.main.bpermd" +attribute \generator "nMigen" +module \bpermd + attribute \src "libresoc.v:31271.7-31271.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:31448.3-32539.6" + wire width 64 $0\perm[63:0] + attribute \src "libresoc.v:31448.3-32539.6" + wire $10\perm[4:4] + attribute \src "libresoc.v:31448.3-32539.6" + wire $11\perm[5:5] + attribute \src "libresoc.v:31448.3-32539.6" + wire $12\perm[5:5] + attribute \src "libresoc.v:31448.3-32539.6" + wire $13\perm[6:6] + attribute \src "libresoc.v:31448.3-32539.6" + wire $14\perm[6:6] + attribute \src "libresoc.v:31448.3-32539.6" + wire $15\perm[7:7] + attribute \src "libresoc.v:31448.3-32539.6" + wire $16\perm[7:7] + attribute \src "libresoc.v:31448.3-32539.6" + wire $1\perm[0:0] + attribute \src "libresoc.v:31448.3-32539.6" + wire $2\perm[0:0] + attribute \src "libresoc.v:31448.3-32539.6" + wire $3\perm[1:1] + attribute \src "libresoc.v:31448.3-32539.6" + wire $4\perm[1:1] + attribute \src "libresoc.v:31448.3-32539.6" + wire $5\perm[2:2] + attribute \src "libresoc.v:31448.3-32539.6" + wire $6\perm[2:2] + attribute \src "libresoc.v:31448.3-32539.6" + wire $7\perm[3:3] + attribute \src "libresoc.v:31448.3-32539.6" + wire $8\perm[3:3] + attribute \src "libresoc.v:31448.3-32539.6" + wire $9\perm[4:4] + attribute \src "libresoc.v:31440.17-31440.104" + wire $lt$libresoc.v:31440$1116_Y + attribute \src "libresoc.v:31441.18-31441.105" + wire $lt$libresoc.v:31441$1117_Y + attribute \src "libresoc.v:31442.18-31442.105" + wire $lt$libresoc.v:31442$1118_Y + attribute \src "libresoc.v:31443.18-31443.105" + wire $lt$libresoc.v:31443$1119_Y + attribute \src "libresoc.v:31444.17-31444.104" + wire $lt$libresoc.v:31444$1120_Y + attribute \src "libresoc.v:31445.17-31445.104" + wire $lt$libresoc.v:31445$1121_Y + attribute \src "libresoc.v:31446.17-31446.104" + wire $lt$libresoc.v:31446$1122_Y + attribute \src "libresoc.v:31447.17-31447.104" + wire $lt$libresoc.v:31447$1123_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:67" + wire width 8 \idx_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:67" + wire width 8 \idx_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:67" + wire width 8 \idx_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:67" + wire width 8 \idx_3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:67" + wire width 8 \idx_4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:67" + wire width 8 \idx_5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:67" + wire width 8 \idx_6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:67" + wire width 8 \idx_7 + attribute \src "libresoc.v:31271.7-31271.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:60" + wire width 64 \perm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:55" + wire width 64 output 2 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:56" + wire width 64 input 1 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_60 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_61 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_62 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_63 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:54" + wire width 64 input 3 \rs + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" + cell $lt $lt$libresoc.v:31440$1116 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \idx_4 + connect \B 7'1000000 + connect \Y $lt$libresoc.v:31440$1116_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" + cell $lt $lt$libresoc.v:31441$1117 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \idx_5 + connect \B 7'1000000 + connect \Y $lt$libresoc.v:31441$1117_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" + cell $lt $lt$libresoc.v:31442$1118 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \idx_6 + connect \B 7'1000000 + connect \Y $lt$libresoc.v:31442$1118_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" + cell $lt $lt$libresoc.v:31443$1119 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \idx_7 + connect \B 7'1000000 + connect \Y $lt$libresoc.v:31443$1119_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" + cell $lt $lt$libresoc.v:31444$1120 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \idx_0 + connect \B 7'1000000 + connect \Y $lt$libresoc.v:31444$1120_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" + cell $lt $lt$libresoc.v:31445$1121 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \idx_1 + connect \B 7'1000000 + connect \Y $lt$libresoc.v:31445$1121_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" + cell $lt $lt$libresoc.v:31446$1122 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \idx_2 + connect \B 7'1000000 + connect \Y $lt$libresoc.v:31446$1122_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" + cell $lt $lt$libresoc.v:31447$1123 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \idx_3 + connect \B 7'1000000 + connect \Y $lt$libresoc.v:31447$1123_Y + end + attribute \src "libresoc.v:31271.7-31271.20" + process $proc$libresoc.v:31271$1125 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:31448.3-32539.6" + process $proc$libresoc.v:31448$1124 + assign { } { } + assign $0\perm[63:0] [63:8] 56'00000000000000000000000000000000000000000000000000000000 + assign $0\perm[63:0] [0] $1\perm[0:0] + assign $0\perm[63:0] [1] $3\perm[1:1] + assign $0\perm[63:0] [2] $5\perm[2:2] + assign $0\perm[63:0] [3] $7\perm[3:3] + assign $0\perm[63:0] [4] $9\perm[4:4] + assign $0\perm[63:0] [5] $11\perm[5:5] + assign $0\perm[63:0] [6] $13\perm[6:6] + assign $0\perm[63:0] [7] $15\perm[7:7] + attribute \src "libresoc.v:31449.5-31449.29" + switch \initial + attribute \src "libresoc.v:31449.9-31449.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\perm[0:0] $2\perm[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:70" + switch \idx_0 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000000 + assign { } { } + assign $2\perm[0:0] \rb64_0 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000001 + assign { } { } + assign $2\perm[0:0] \rb64_1 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000010 + assign { } { } + assign $2\perm[0:0] \rb64_2 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000011 + assign { } { } + assign $2\perm[0:0] \rb64_3 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000100 + assign { } { } + assign $2\perm[0:0] \rb64_4 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000101 + assign { } { } + assign $2\perm[0:0] \rb64_5 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000110 + assign { } { } + assign $2\perm[0:0] \rb64_6 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000111 + assign { } { } + assign $2\perm[0:0] \rb64_7 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001000 + assign { } { } + assign $2\perm[0:0] \rb64_8 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001001 + assign { } { } + assign $2\perm[0:0] \rb64_9 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001010 + assign { } { } + assign $2\perm[0:0] \rb64_10 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001011 + assign { } { } + assign $2\perm[0:0] \rb64_11 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001100 + assign { } { } + assign $2\perm[0:0] \rb64_12 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001101 + assign { } { } + assign $2\perm[0:0] \rb64_13 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001110 + assign { } { } + assign $2\perm[0:0] \rb64_14 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001111 + assign { } { } + assign $2\perm[0:0] \rb64_15 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010000 + assign { } { } + assign $2\perm[0:0] \rb64_16 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010001 + assign { } { } + assign $2\perm[0:0] \rb64_17 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010010 + assign { } { } + assign $2\perm[0:0] \rb64_18 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010011 + assign { } { } + assign $2\perm[0:0] \rb64_19 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010100 + assign { } { } + assign $2\perm[0:0] \rb64_20 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010101 + assign { } { } + assign $2\perm[0:0] \rb64_21 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010110 + assign { } { } + assign $2\perm[0:0] \rb64_22 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010111 + assign { } { } + assign $2\perm[0:0] \rb64_23 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011000 + assign { } { } + assign $2\perm[0:0] \rb64_24 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011001 + assign { } { } + assign $2\perm[0:0] \rb64_25 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011010 + assign { } { } + assign $2\perm[0:0] \rb64_26 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011011 + assign { } { } + assign $2\perm[0:0] \rb64_27 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011100 + assign { } { } + assign $2\perm[0:0] \rb64_28 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011101 + assign { } { } + assign $2\perm[0:0] \rb64_29 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011110 + assign { } { } + assign $2\perm[0:0] \rb64_30 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011111 + assign { } { } + assign $2\perm[0:0] \rb64_31 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100000 + assign { } { } + assign $2\perm[0:0] \rb64_32 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100001 + assign { } { } + assign $2\perm[0:0] \rb64_33 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100010 + assign { } { } + assign $2\perm[0:0] \rb64_34 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100011 + assign { } { } + assign $2\perm[0:0] \rb64_35 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100100 + assign { } { } + assign $2\perm[0:0] \rb64_36 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100101 + assign { } { } + assign $2\perm[0:0] \rb64_37 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100110 + assign { } { } + assign $2\perm[0:0] \rb64_38 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100111 + assign { } { } + assign $2\perm[0:0] \rb64_39 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101000 + assign { } { } + assign $2\perm[0:0] \rb64_40 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101001 + assign { } { } + assign $2\perm[0:0] \rb64_41 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101010 + assign { } { } + assign $2\perm[0:0] \rb64_42 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101011 + assign { } { } + assign $2\perm[0:0] \rb64_43 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101100 + assign { } { } + assign $2\perm[0:0] \rb64_44 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101101 + assign { } { } + assign $2\perm[0:0] \rb64_45 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101110 + assign { } { } + assign $2\perm[0:0] \rb64_46 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101111 + assign { } { } + assign $2\perm[0:0] \rb64_47 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110000 + assign { } { } + assign $2\perm[0:0] \rb64_48 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110001 + assign { } { } + assign $2\perm[0:0] \rb64_49 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110010 + assign { } { } + assign $2\perm[0:0] \rb64_50 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110011 + assign { } { } + assign $2\perm[0:0] \rb64_51 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110100 + assign { } { } + assign $2\perm[0:0] \rb64_52 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110101 + assign { } { } + assign $2\perm[0:0] \rb64_53 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110110 + assign { } { } + assign $2\perm[0:0] \rb64_54 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110111 + assign { } { } + assign $2\perm[0:0] \rb64_55 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111000 + assign { } { } + assign $2\perm[0:0] \rb64_56 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111001 + assign { } { } + assign $2\perm[0:0] \rb64_57 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111010 + assign { } { } + assign $2\perm[0:0] \rb64_58 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111011 + assign { } { } + assign $2\perm[0:0] \rb64_59 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111100 + assign { } { } + assign $2\perm[0:0] \rb64_60 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111101 + assign { } { } + assign $2\perm[0:0] \rb64_61 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111110 + assign { } { } + assign $2\perm[0:0] \rb64_62 + attribute \src "libresoc.v:0.0-0.0" + case 8'-------- + assign { } { } + assign $2\perm[0:0] \rb64_63 + case + assign $2\perm[0:0] 1'0 + end + case + assign $1\perm[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\perm[1:1] $4\perm[1:1] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:70" + switch \idx_1 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000000 + assign { } { } + assign $4\perm[1:1] \rb64_0 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000001 + assign { } { } + assign $4\perm[1:1] \rb64_1 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000010 + assign { } { } + assign $4\perm[1:1] \rb64_2 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000011 + assign { } { } + assign $4\perm[1:1] \rb64_3 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000100 + assign { } { } + assign $4\perm[1:1] \rb64_4 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000101 + assign { } { } + assign $4\perm[1:1] \rb64_5 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000110 + assign { } { } + assign $4\perm[1:1] \rb64_6 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000111 + assign { } { } + assign $4\perm[1:1] \rb64_7 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001000 + assign { } { } + assign $4\perm[1:1] \rb64_8 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001001 + assign { } { } + assign $4\perm[1:1] \rb64_9 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001010 + assign { } { } + assign $4\perm[1:1] \rb64_10 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001011 + assign { } { } + assign $4\perm[1:1] \rb64_11 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001100 + assign { } { } + assign $4\perm[1:1] \rb64_12 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001101 + assign { } { } + assign $4\perm[1:1] \rb64_13 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001110 + assign { } { } + assign $4\perm[1:1] \rb64_14 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001111 + assign { } { } + assign $4\perm[1:1] \rb64_15 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010000 + assign { } { } + assign $4\perm[1:1] \rb64_16 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010001 + assign { } { } + assign $4\perm[1:1] \rb64_17 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010010 + assign { } { } + assign $4\perm[1:1] \rb64_18 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010011 + assign { } { } + assign $4\perm[1:1] \rb64_19 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010100 + assign { } { } + assign $4\perm[1:1] \rb64_20 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010101 + assign { } { } + assign $4\perm[1:1] \rb64_21 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010110 + assign { } { } + assign $4\perm[1:1] \rb64_22 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010111 + assign { } { } + assign $4\perm[1:1] \rb64_23 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011000 + assign { } { } + assign $4\perm[1:1] \rb64_24 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011001 + assign { } { } + assign $4\perm[1:1] \rb64_25 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011010 + assign { } { } + assign $4\perm[1:1] \rb64_26 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011011 + assign { } { } + assign $4\perm[1:1] \rb64_27 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011100 + assign { } { } + assign $4\perm[1:1] \rb64_28 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011101 + assign { } { } + assign $4\perm[1:1] \rb64_29 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011110 + assign { } { } + assign $4\perm[1:1] \rb64_30 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011111 + assign { } { } + assign $4\perm[1:1] \rb64_31 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100000 + assign { } { } + assign $4\perm[1:1] \rb64_32 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100001 + assign { } { } + assign $4\perm[1:1] \rb64_33 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100010 + assign { } { } + assign $4\perm[1:1] \rb64_34 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100011 + assign { } { } + assign $4\perm[1:1] \rb64_35 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100100 + assign { } { } + assign $4\perm[1:1] \rb64_36 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100101 + assign { } { } + assign $4\perm[1:1] \rb64_37 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100110 + assign { } { } + assign $4\perm[1:1] \rb64_38 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100111 + assign { } { } + assign $4\perm[1:1] \rb64_39 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101000 + assign { } { } + assign $4\perm[1:1] \rb64_40 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101001 + assign { } { } + assign $4\perm[1:1] \rb64_41 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101010 + assign { } { } + assign $4\perm[1:1] \rb64_42 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101011 + assign { } { } + assign $4\perm[1:1] \rb64_43 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101100 + assign { } { } + assign $4\perm[1:1] \rb64_44 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101101 + assign { } { } + assign $4\perm[1:1] \rb64_45 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101110 + assign { } { } + assign $4\perm[1:1] \rb64_46 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101111 + assign { } { } + assign $4\perm[1:1] \rb64_47 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110000 + assign { } { } + assign $4\perm[1:1] \rb64_48 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110001 + assign { } { } + assign $4\perm[1:1] \rb64_49 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110010 + assign { } { } + assign $4\perm[1:1] \rb64_50 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110011 + assign { } { } + assign $4\perm[1:1] \rb64_51 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110100 + assign { } { } + assign $4\perm[1:1] \rb64_52 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110101 + assign { } { } + assign $4\perm[1:1] \rb64_53 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110110 + assign { } { } + assign $4\perm[1:1] \rb64_54 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110111 + assign { } { } + assign $4\perm[1:1] \rb64_55 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111000 + assign { } { } + assign $4\perm[1:1] \rb64_56 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111001 + assign { } { } + assign $4\perm[1:1] \rb64_57 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111010 + assign { } { } + assign $4\perm[1:1] \rb64_58 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111011 + assign { } { } + assign $4\perm[1:1] \rb64_59 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111100 + assign { } { } + assign $4\perm[1:1] \rb64_60 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111101 + assign { } { } + assign $4\perm[1:1] \rb64_61 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111110 + assign { } { } + assign $4\perm[1:1] \rb64_62 + attribute \src "libresoc.v:0.0-0.0" + case 8'-------- + assign { } { } + assign $4\perm[1:1] \rb64_63 + case + assign $4\perm[1:1] 1'0 + end + case + assign $3\perm[1:1] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" + switch \$5 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\perm[2:2] $6\perm[2:2] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:70" + switch \idx_2 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000000 + assign { } { } + assign $6\perm[2:2] \rb64_0 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000001 + assign { } { } + assign $6\perm[2:2] \rb64_1 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000010 + assign { } { } + assign $6\perm[2:2] \rb64_2 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000011 + assign { } { } + assign $6\perm[2:2] \rb64_3 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000100 + assign { } { } + assign $6\perm[2:2] \rb64_4 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000101 + assign { } { } + assign $6\perm[2:2] \rb64_5 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000110 + assign { } { } + assign $6\perm[2:2] \rb64_6 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000111 + assign { } { } + assign $6\perm[2:2] \rb64_7 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001000 + assign { } { } + assign $6\perm[2:2] \rb64_8 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001001 + assign { } { } + assign $6\perm[2:2] \rb64_9 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001010 + assign { } { } + assign $6\perm[2:2] \rb64_10 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001011 + assign { } { } + assign $6\perm[2:2] \rb64_11 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001100 + assign { } { } + assign $6\perm[2:2] \rb64_12 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001101 + assign { } { } + assign $6\perm[2:2] \rb64_13 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001110 + assign { } { } + assign $6\perm[2:2] \rb64_14 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001111 + assign { } { } + assign $6\perm[2:2] \rb64_15 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010000 + assign { } { } + assign $6\perm[2:2] \rb64_16 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010001 + assign { } { } + assign $6\perm[2:2] \rb64_17 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010010 + assign { } { } + assign $6\perm[2:2] \rb64_18 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010011 + assign { } { } + assign $6\perm[2:2] \rb64_19 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010100 + assign { } { } + assign $6\perm[2:2] \rb64_20 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010101 + assign { } { } + assign $6\perm[2:2] \rb64_21 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010110 + assign { } { } + assign $6\perm[2:2] \rb64_22 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010111 + assign { } { } + assign $6\perm[2:2] \rb64_23 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011000 + assign { } { } + assign $6\perm[2:2] \rb64_24 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011001 + assign { } { } + assign $6\perm[2:2] \rb64_25 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011010 + assign { } { } + assign $6\perm[2:2] \rb64_26 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011011 + assign { } { } + assign $6\perm[2:2] \rb64_27 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011100 + assign { } { } + assign $6\perm[2:2] \rb64_28 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011101 + assign { } { } + assign $6\perm[2:2] \rb64_29 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011110 + assign { } { } + assign $6\perm[2:2] \rb64_30 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011111 + assign { } { } + assign $6\perm[2:2] \rb64_31 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100000 + assign { } { } + assign $6\perm[2:2] \rb64_32 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100001 + assign { } { } + assign $6\perm[2:2] \rb64_33 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100010 + assign { } { } + assign $6\perm[2:2] \rb64_34 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100011 + assign { } { } + assign $6\perm[2:2] \rb64_35 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100100 + assign { } { } + assign $6\perm[2:2] \rb64_36 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100101 + assign { } { } + assign $6\perm[2:2] \rb64_37 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100110 + assign { } { } + assign $6\perm[2:2] \rb64_38 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100111 + assign { } { } + assign $6\perm[2:2] \rb64_39 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101000 + assign { } { } + assign $6\perm[2:2] \rb64_40 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101001 + assign { } { } + assign $6\perm[2:2] \rb64_41 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101010 + assign { } { } + assign $6\perm[2:2] \rb64_42 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101011 + assign { } { } + assign $6\perm[2:2] \rb64_43 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101100 + assign { } { } + assign $6\perm[2:2] \rb64_44 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101101 + assign { } { } + assign $6\perm[2:2] \rb64_45 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101110 + assign { } { } + assign $6\perm[2:2] \rb64_46 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101111 + assign { } { } + assign $6\perm[2:2] \rb64_47 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110000 + assign { } { } + assign $6\perm[2:2] \rb64_48 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110001 + assign { } { } + assign $6\perm[2:2] \rb64_49 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110010 + assign { } { } + assign $6\perm[2:2] \rb64_50 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110011 + assign { } { } + assign $6\perm[2:2] \rb64_51 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110100 + assign { } { } + assign $6\perm[2:2] \rb64_52 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110101 + assign { } { } + assign $6\perm[2:2] \rb64_53 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110110 + assign { } { } + assign $6\perm[2:2] \rb64_54 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110111 + assign { } { } + assign $6\perm[2:2] \rb64_55 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111000 + assign { } { } + assign $6\perm[2:2] \rb64_56 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111001 + assign { } { } + assign $6\perm[2:2] \rb64_57 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111010 + assign { } { } + assign $6\perm[2:2] \rb64_58 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111011 + assign { } { } + assign $6\perm[2:2] \rb64_59 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111100 + assign { } { } + assign $6\perm[2:2] \rb64_60 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111101 + assign { } { } + assign $6\perm[2:2] \rb64_61 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111110 + assign { } { } + assign $6\perm[2:2] \rb64_62 + attribute \src "libresoc.v:0.0-0.0" + case 8'-------- + assign { } { } + assign $6\perm[2:2] \rb64_63 + case + assign $6\perm[2:2] 1'0 + end + case + assign $5\perm[2:2] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" + switch \$7 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\perm[3:3] $8\perm[3:3] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:70" + switch \idx_3 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000000 + assign { } { } + assign $8\perm[3:3] \rb64_0 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000001 + assign { } { } + assign $8\perm[3:3] \rb64_1 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000010 + assign { } { } + assign $8\perm[3:3] \rb64_2 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000011 + assign { } { } + assign $8\perm[3:3] \rb64_3 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000100 + assign { } { } + assign $8\perm[3:3] \rb64_4 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000101 + assign { } { } + assign $8\perm[3:3] \rb64_5 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000110 + assign { } { } + assign $8\perm[3:3] \rb64_6 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000111 + assign { } { } + assign $8\perm[3:3] \rb64_7 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001000 + assign { } { } + assign $8\perm[3:3] \rb64_8 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001001 + assign { } { } + assign $8\perm[3:3] \rb64_9 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001010 + assign { } { } + assign $8\perm[3:3] \rb64_10 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001011 + assign { } { } + assign $8\perm[3:3] \rb64_11 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001100 + assign { } { } + assign $8\perm[3:3] \rb64_12 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001101 + assign { } { } + assign $8\perm[3:3] \rb64_13 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001110 + assign { } { } + assign $8\perm[3:3] \rb64_14 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001111 + assign { } { } + assign $8\perm[3:3] \rb64_15 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010000 + assign { } { } + assign $8\perm[3:3] \rb64_16 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010001 + assign { } { } + assign $8\perm[3:3] \rb64_17 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010010 + assign { } { } + assign $8\perm[3:3] \rb64_18 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010011 + assign { } { } + assign $8\perm[3:3] \rb64_19 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010100 + assign { } { } + assign $8\perm[3:3] \rb64_20 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010101 + assign { } { } + assign $8\perm[3:3] \rb64_21 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010110 + assign { } { } + assign $8\perm[3:3] \rb64_22 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010111 + assign { } { } + assign $8\perm[3:3] \rb64_23 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011000 + assign { } { } + assign $8\perm[3:3] \rb64_24 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011001 + assign { } { } + assign $8\perm[3:3] \rb64_25 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011010 + assign { } { } + assign $8\perm[3:3] \rb64_26 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011011 + assign { } { } + assign $8\perm[3:3] \rb64_27 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011100 + assign { } { } + assign $8\perm[3:3] \rb64_28 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011101 + assign { } { } + assign $8\perm[3:3] \rb64_29 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011110 + assign { } { } + assign $8\perm[3:3] \rb64_30 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011111 + assign { } { } + assign $8\perm[3:3] \rb64_31 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100000 + assign { } { } + assign $8\perm[3:3] \rb64_32 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100001 + assign { } { } + assign $8\perm[3:3] \rb64_33 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100010 + assign { } { } + assign $8\perm[3:3] \rb64_34 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100011 + assign { } { } + assign $8\perm[3:3] \rb64_35 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100100 + assign { } { } + assign $8\perm[3:3] \rb64_36 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100101 + assign { } { } + assign $8\perm[3:3] \rb64_37 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100110 + assign { } { } + assign $8\perm[3:3] \rb64_38 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100111 + assign { } { } + assign $8\perm[3:3] \rb64_39 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101000 + assign { } { } + assign $8\perm[3:3] \rb64_40 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101001 + assign { } { } + assign $8\perm[3:3] \rb64_41 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101010 + assign { } { } + assign $8\perm[3:3] \rb64_42 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101011 + assign { } { } + assign $8\perm[3:3] \rb64_43 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101100 + assign { } { } + assign $8\perm[3:3] \rb64_44 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101101 + assign { } { } + assign $8\perm[3:3] \rb64_45 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101110 + assign { } { } + assign $8\perm[3:3] \rb64_46 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101111 + assign { } { } + assign $8\perm[3:3] \rb64_47 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110000 + assign { } { } + assign $8\perm[3:3] \rb64_48 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110001 + assign { } { } + assign $8\perm[3:3] \rb64_49 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110010 + assign { } { } + assign $8\perm[3:3] \rb64_50 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110011 + assign { } { } + assign $8\perm[3:3] \rb64_51 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110100 + assign { } { } + assign $8\perm[3:3] \rb64_52 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110101 + assign { } { } + assign $8\perm[3:3] \rb64_53 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110110 + assign { } { } + assign $8\perm[3:3] \rb64_54 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110111 + assign { } { } + assign $8\perm[3:3] \rb64_55 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111000 + assign { } { } + assign $8\perm[3:3] \rb64_56 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111001 + assign { } { } + assign $8\perm[3:3] \rb64_57 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111010 + assign { } { } + assign $8\perm[3:3] \rb64_58 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111011 + assign { } { } + assign $8\perm[3:3] \rb64_59 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111100 + assign { } { } + assign $8\perm[3:3] \rb64_60 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111101 + assign { } { } + assign $8\perm[3:3] \rb64_61 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111110 + assign { } { } + assign $8\perm[3:3] \rb64_62 + attribute \src "libresoc.v:0.0-0.0" + case 8'-------- + assign { } { } + assign $8\perm[3:3] \rb64_63 + case + assign $8\perm[3:3] 1'0 + end + case + assign $7\perm[3:3] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" + switch \$9 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $9\perm[4:4] $10\perm[4:4] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:70" + switch \idx_4 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000000 + assign { } { } + assign $10\perm[4:4] \rb64_0 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000001 + assign { } { } + assign $10\perm[4:4] \rb64_1 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000010 + assign { } { } + assign $10\perm[4:4] \rb64_2 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000011 + assign { } { } + assign $10\perm[4:4] \rb64_3 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000100 + assign { } { } + assign $10\perm[4:4] \rb64_4 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000101 + assign { } { } + assign $10\perm[4:4] \rb64_5 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000110 + assign { } { } + assign $10\perm[4:4] \rb64_6 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000111 + assign { } { } + assign $10\perm[4:4] \rb64_7 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001000 + assign { } { } + assign $10\perm[4:4] \rb64_8 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001001 + assign { } { } + assign $10\perm[4:4] \rb64_9 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001010 + assign { } { } + assign $10\perm[4:4] \rb64_10 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001011 + assign { } { } + assign $10\perm[4:4] \rb64_11 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001100 + assign { } { } + assign $10\perm[4:4] \rb64_12 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001101 + assign { } { } + assign $10\perm[4:4] \rb64_13 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001110 + assign { } { } + assign $10\perm[4:4] \rb64_14 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001111 + assign { } { } + assign $10\perm[4:4] \rb64_15 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010000 + assign { } { } + assign $10\perm[4:4] \rb64_16 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010001 + assign { } { } + assign $10\perm[4:4] \rb64_17 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010010 + assign { } { } + assign $10\perm[4:4] \rb64_18 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010011 + assign { } { } + assign $10\perm[4:4] \rb64_19 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010100 + assign { } { } + assign $10\perm[4:4] \rb64_20 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010101 + assign { } { } + assign $10\perm[4:4] \rb64_21 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010110 + assign { } { } + assign $10\perm[4:4] \rb64_22 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010111 + assign { } { } + assign $10\perm[4:4] \rb64_23 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011000 + assign { } { } + assign $10\perm[4:4] \rb64_24 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011001 + assign { } { } + assign $10\perm[4:4] \rb64_25 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011010 + assign { } { } + assign $10\perm[4:4] \rb64_26 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011011 + assign { } { } + assign $10\perm[4:4] \rb64_27 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011100 + assign { } { } + assign $10\perm[4:4] \rb64_28 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011101 + assign { } { } + assign $10\perm[4:4] \rb64_29 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011110 + assign { } { } + assign $10\perm[4:4] \rb64_30 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011111 + assign { } { } + assign $10\perm[4:4] \rb64_31 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100000 + assign { } { } + assign $10\perm[4:4] \rb64_32 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100001 + assign { } { } + assign $10\perm[4:4] \rb64_33 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100010 + assign { } { } + assign $10\perm[4:4] \rb64_34 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100011 + assign { } { } + assign $10\perm[4:4] \rb64_35 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100100 + assign { } { } + assign $10\perm[4:4] \rb64_36 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100101 + assign { } { } + assign $10\perm[4:4] \rb64_37 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100110 + assign { } { } + assign $10\perm[4:4] \rb64_38 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100111 + assign { } { } + assign $10\perm[4:4] \rb64_39 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101000 + assign { } { } + assign $10\perm[4:4] \rb64_40 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101001 + assign { } { } + assign $10\perm[4:4] \rb64_41 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101010 + assign { } { } + assign $10\perm[4:4] \rb64_42 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101011 + assign { } { } + assign $10\perm[4:4] \rb64_43 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101100 + assign { } { } + assign $10\perm[4:4] \rb64_44 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101101 + assign { } { } + assign $10\perm[4:4] \rb64_45 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101110 + assign { } { } + assign $10\perm[4:4] \rb64_46 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101111 + assign { } { } + assign $10\perm[4:4] \rb64_47 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110000 + assign { } { } + assign $10\perm[4:4] \rb64_48 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110001 + assign { } { } + assign $10\perm[4:4] \rb64_49 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110010 + assign { } { } + assign $10\perm[4:4] \rb64_50 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110011 + assign { } { } + assign $10\perm[4:4] \rb64_51 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110100 + assign { } { } + assign $10\perm[4:4] \rb64_52 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110101 + assign { } { } + assign $10\perm[4:4] \rb64_53 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110110 + assign { } { } + assign $10\perm[4:4] \rb64_54 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110111 + assign { } { } + assign $10\perm[4:4] \rb64_55 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111000 + assign { } { } + assign $10\perm[4:4] \rb64_56 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111001 + assign { } { } + assign $10\perm[4:4] \rb64_57 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111010 + assign { } { } + assign $10\perm[4:4] \rb64_58 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111011 + assign { } { } + assign $10\perm[4:4] \rb64_59 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111100 + assign { } { } + assign $10\perm[4:4] \rb64_60 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111101 + assign { } { } + assign $10\perm[4:4] \rb64_61 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111110 + assign { } { } + assign $10\perm[4:4] \rb64_62 + attribute \src "libresoc.v:0.0-0.0" + case 8'-------- + assign { } { } + assign $10\perm[4:4] \rb64_63 + case + assign $10\perm[4:4] 1'0 + end + case + assign $9\perm[4:4] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" + switch \$11 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $11\perm[5:5] $12\perm[5:5] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:70" + switch \idx_5 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000000 + assign { } { } + assign $12\perm[5:5] \rb64_0 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000001 + assign { } { } + assign $12\perm[5:5] \rb64_1 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000010 + assign { } { } + assign $12\perm[5:5] \rb64_2 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000011 + assign { } { } + assign $12\perm[5:5] \rb64_3 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000100 + assign { } { } + assign $12\perm[5:5] \rb64_4 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000101 + assign { } { } + assign $12\perm[5:5] \rb64_5 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000110 + assign { } { } + assign $12\perm[5:5] \rb64_6 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000111 + assign { } { } + assign $12\perm[5:5] \rb64_7 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001000 + assign { } { } + assign $12\perm[5:5] \rb64_8 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001001 + assign { } { } + assign $12\perm[5:5] \rb64_9 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001010 + assign { } { } + assign $12\perm[5:5] \rb64_10 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001011 + assign { } { } + assign $12\perm[5:5] \rb64_11 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001100 + assign { } { } + assign $12\perm[5:5] \rb64_12 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001101 + assign { } { } + assign $12\perm[5:5] \rb64_13 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001110 + assign { } { } + assign $12\perm[5:5] \rb64_14 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001111 + assign { } { } + assign $12\perm[5:5] \rb64_15 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010000 + assign { } { } + assign $12\perm[5:5] \rb64_16 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010001 + assign { } { } + assign $12\perm[5:5] \rb64_17 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010010 + assign { } { } + assign $12\perm[5:5] \rb64_18 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010011 + assign { } { } + assign $12\perm[5:5] \rb64_19 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010100 + assign { } { } + assign $12\perm[5:5] \rb64_20 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010101 + assign { } { } + assign $12\perm[5:5] \rb64_21 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010110 + assign { } { } + assign $12\perm[5:5] \rb64_22 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010111 + assign { } { } + assign $12\perm[5:5] \rb64_23 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011000 + assign { } { } + assign $12\perm[5:5] \rb64_24 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011001 + assign { } { } + assign $12\perm[5:5] \rb64_25 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011010 + assign { } { } + assign $12\perm[5:5] \rb64_26 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011011 + assign { } { } + assign $12\perm[5:5] \rb64_27 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011100 + assign { } { } + assign $12\perm[5:5] \rb64_28 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011101 + assign { } { } + assign $12\perm[5:5] \rb64_29 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011110 + assign { } { } + assign $12\perm[5:5] \rb64_30 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011111 + assign { } { } + assign $12\perm[5:5] \rb64_31 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100000 + assign { } { } + assign $12\perm[5:5] \rb64_32 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100001 + assign { } { } + assign $12\perm[5:5] \rb64_33 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100010 + assign { } { } + assign $12\perm[5:5] \rb64_34 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100011 + assign { } { } + assign $12\perm[5:5] \rb64_35 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100100 + assign { } { } + assign $12\perm[5:5] \rb64_36 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100101 + assign { } { } + assign $12\perm[5:5] \rb64_37 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100110 + assign { } { } + assign $12\perm[5:5] \rb64_38 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100111 + assign { } { } + assign $12\perm[5:5] \rb64_39 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101000 + assign { } { } + assign $12\perm[5:5] \rb64_40 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101001 + assign { } { } + assign $12\perm[5:5] \rb64_41 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101010 + assign { } { } + assign $12\perm[5:5] \rb64_42 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101011 + assign { } { } + assign $12\perm[5:5] \rb64_43 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101100 + assign { } { } + assign $12\perm[5:5] \rb64_44 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101101 + assign { } { } + assign $12\perm[5:5] \rb64_45 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101110 + assign { } { } + assign $12\perm[5:5] \rb64_46 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101111 + assign { } { } + assign $12\perm[5:5] \rb64_47 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110000 + assign { } { } + assign $12\perm[5:5] \rb64_48 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110001 + assign { } { } + assign $12\perm[5:5] \rb64_49 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110010 + assign { } { } + assign $12\perm[5:5] \rb64_50 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110011 + assign { } { } + assign $12\perm[5:5] \rb64_51 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110100 + assign { } { } + assign $12\perm[5:5] \rb64_52 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110101 + assign { } { } + assign $12\perm[5:5] \rb64_53 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110110 + assign { } { } + assign $12\perm[5:5] \rb64_54 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110111 + assign { } { } + assign $12\perm[5:5] \rb64_55 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111000 + assign { } { } + assign $12\perm[5:5] \rb64_56 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111001 + assign { } { } + assign $12\perm[5:5] \rb64_57 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111010 + assign { } { } + assign $12\perm[5:5] \rb64_58 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111011 + assign { } { } + assign $12\perm[5:5] \rb64_59 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111100 + assign { } { } + assign $12\perm[5:5] \rb64_60 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111101 + assign { } { } + assign $12\perm[5:5] \rb64_61 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111110 + assign { } { } + assign $12\perm[5:5] \rb64_62 + attribute \src "libresoc.v:0.0-0.0" + case 8'-------- + assign { } { } + assign $12\perm[5:5] \rb64_63 + case + assign $12\perm[5:5] 1'0 + end + case + assign $11\perm[5:5] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" + switch \$13 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $13\perm[6:6] $14\perm[6:6] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:70" + switch \idx_6 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000000 + assign { } { } + assign $14\perm[6:6] \rb64_0 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000001 + assign { } { } + assign $14\perm[6:6] \rb64_1 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000010 + assign { } { } + assign $14\perm[6:6] \rb64_2 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000011 + assign { } { } + assign $14\perm[6:6] \rb64_3 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000100 + assign { } { } + assign $14\perm[6:6] \rb64_4 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000101 + assign { } { } + assign $14\perm[6:6] \rb64_5 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000110 + assign { } { } + assign $14\perm[6:6] \rb64_6 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000111 + assign { } { } + assign $14\perm[6:6] \rb64_7 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001000 + assign { } { } + assign $14\perm[6:6] \rb64_8 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001001 + assign { } { } + assign $14\perm[6:6] \rb64_9 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001010 + assign { } { } + assign $14\perm[6:6] \rb64_10 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001011 + assign { } { } + assign $14\perm[6:6] \rb64_11 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001100 + assign { } { } + assign $14\perm[6:6] \rb64_12 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001101 + assign { } { } + assign $14\perm[6:6] \rb64_13 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001110 + assign { } { } + assign $14\perm[6:6] \rb64_14 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001111 + assign { } { } + assign $14\perm[6:6] \rb64_15 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010000 + assign { } { } + assign $14\perm[6:6] \rb64_16 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010001 + assign { } { } + assign $14\perm[6:6] \rb64_17 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010010 + assign { } { } + assign $14\perm[6:6] \rb64_18 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010011 + assign { } { } + assign $14\perm[6:6] \rb64_19 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010100 + assign { } { } + assign $14\perm[6:6] \rb64_20 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010101 + assign { } { } + assign $14\perm[6:6] \rb64_21 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010110 + assign { } { } + assign $14\perm[6:6] \rb64_22 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010111 + assign { } { } + assign $14\perm[6:6] \rb64_23 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011000 + assign { } { } + assign $14\perm[6:6] \rb64_24 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011001 + assign { } { } + assign $14\perm[6:6] \rb64_25 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011010 + assign { } { } + assign $14\perm[6:6] \rb64_26 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011011 + assign { } { } + assign $14\perm[6:6] \rb64_27 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011100 + assign { } { } + assign $14\perm[6:6] \rb64_28 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011101 + assign { } { } + assign $14\perm[6:6] \rb64_29 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011110 + assign { } { } + assign $14\perm[6:6] \rb64_30 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011111 + assign { } { } + assign $14\perm[6:6] \rb64_31 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100000 + assign { } { } + assign $14\perm[6:6] \rb64_32 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100001 + assign { } { } + assign $14\perm[6:6] \rb64_33 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100010 + assign { } { } + assign $14\perm[6:6] \rb64_34 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100011 + assign { } { } + assign $14\perm[6:6] \rb64_35 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100100 + assign { } { } + assign $14\perm[6:6] \rb64_36 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100101 + assign { } { } + assign $14\perm[6:6] \rb64_37 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100110 + assign { } { } + assign $14\perm[6:6] \rb64_38 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100111 + assign { } { } + assign $14\perm[6:6] \rb64_39 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101000 + assign { } { } + assign $14\perm[6:6] \rb64_40 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101001 + assign { } { } + assign $14\perm[6:6] \rb64_41 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101010 + assign { } { } + assign $14\perm[6:6] \rb64_42 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101011 + assign { } { } + assign $14\perm[6:6] \rb64_43 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101100 + assign { } { } + assign $14\perm[6:6] \rb64_44 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101101 + assign { } { } + assign $14\perm[6:6] \rb64_45 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101110 + assign { } { } + assign $14\perm[6:6] \rb64_46 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101111 + assign { } { } + assign $14\perm[6:6] \rb64_47 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110000 + assign { } { } + assign $14\perm[6:6] \rb64_48 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110001 + assign { } { } + assign $14\perm[6:6] \rb64_49 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110010 + assign { } { } + assign $14\perm[6:6] \rb64_50 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110011 + assign { } { } + assign $14\perm[6:6] \rb64_51 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110100 + assign { } { } + assign $14\perm[6:6] \rb64_52 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110101 + assign { } { } + assign $14\perm[6:6] \rb64_53 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110110 + assign { } { } + assign $14\perm[6:6] \rb64_54 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110111 + assign { } { } + assign $14\perm[6:6] \rb64_55 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111000 + assign { } { } + assign $14\perm[6:6] \rb64_56 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111001 + assign { } { } + assign $14\perm[6:6] \rb64_57 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111010 + assign { } { } + assign $14\perm[6:6] \rb64_58 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111011 + assign { } { } + assign $14\perm[6:6] \rb64_59 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111100 + assign { } { } + assign $14\perm[6:6] \rb64_60 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111101 + assign { } { } + assign $14\perm[6:6] \rb64_61 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111110 + assign { } { } + assign $14\perm[6:6] \rb64_62 + attribute \src "libresoc.v:0.0-0.0" + case 8'-------- + assign { } { } + assign $14\perm[6:6] \rb64_63 + case + assign $14\perm[6:6] 1'0 + end + case + assign $13\perm[6:6] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" + switch \$15 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $15\perm[7:7] $16\perm[7:7] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:70" + switch \idx_7 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000000 + assign { } { } + assign $16\perm[7:7] \rb64_0 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000001 + assign { } { } + assign $16\perm[7:7] \rb64_1 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000010 + assign { } { } + assign $16\perm[7:7] \rb64_2 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000011 + assign { } { } + assign $16\perm[7:7] \rb64_3 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000100 + assign { } { } + assign $16\perm[7:7] \rb64_4 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000101 + assign { } { } + assign $16\perm[7:7] \rb64_5 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000110 + assign { } { } + assign $16\perm[7:7] \rb64_6 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000111 + assign { } { } + assign $16\perm[7:7] \rb64_7 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001000 + assign { } { } + assign $16\perm[7:7] \rb64_8 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001001 + assign { } { } + assign $16\perm[7:7] \rb64_9 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001010 + assign { } { } + assign $16\perm[7:7] \rb64_10 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001011 + assign { } { } + assign $16\perm[7:7] \rb64_11 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001100 + assign { } { } + assign $16\perm[7:7] \rb64_12 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001101 + assign { } { } + assign $16\perm[7:7] \rb64_13 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001110 + assign { } { } + assign $16\perm[7:7] \rb64_14 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001111 + assign { } { } + assign $16\perm[7:7] \rb64_15 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010000 + assign { } { } + assign $16\perm[7:7] \rb64_16 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010001 + assign { } { } + assign $16\perm[7:7] \rb64_17 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010010 + assign { } { } + assign $16\perm[7:7] \rb64_18 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010011 + assign { } { } + assign $16\perm[7:7] \rb64_19 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010100 + assign { } { } + assign $16\perm[7:7] \rb64_20 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010101 + assign { } { } + assign $16\perm[7:7] \rb64_21 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010110 + assign { } { } + assign $16\perm[7:7] \rb64_22 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010111 + assign { } { } + assign $16\perm[7:7] \rb64_23 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011000 + assign { } { } + assign $16\perm[7:7] \rb64_24 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011001 + assign { } { } + assign $16\perm[7:7] \rb64_25 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011010 + assign { } { } + assign $16\perm[7:7] \rb64_26 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011011 + assign { } { } + assign $16\perm[7:7] \rb64_27 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011100 + assign { } { } + assign $16\perm[7:7] \rb64_28 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011101 + assign { } { } + assign $16\perm[7:7] \rb64_29 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011110 + assign { } { } + assign $16\perm[7:7] \rb64_30 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011111 + assign { } { } + assign $16\perm[7:7] \rb64_31 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100000 + assign { } { } + assign $16\perm[7:7] \rb64_32 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100001 + assign { } { } + assign $16\perm[7:7] \rb64_33 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100010 + assign { } { } + assign $16\perm[7:7] \rb64_34 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100011 + assign { } { } + assign $16\perm[7:7] \rb64_35 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100100 + assign { } { } + assign $16\perm[7:7] \rb64_36 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100101 + assign { } { } + assign $16\perm[7:7] \rb64_37 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100110 + assign { } { } + assign $16\perm[7:7] \rb64_38 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100111 + assign { } { } + assign $16\perm[7:7] \rb64_39 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101000 + assign { } { } + assign $16\perm[7:7] \rb64_40 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101001 + assign { } { } + assign $16\perm[7:7] \rb64_41 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101010 + assign { } { } + assign $16\perm[7:7] \rb64_42 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101011 + assign { } { } + assign $16\perm[7:7] \rb64_43 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101100 + assign { } { } + assign $16\perm[7:7] \rb64_44 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101101 + assign { } { } + assign $16\perm[7:7] \rb64_45 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101110 + assign { } { } + assign $16\perm[7:7] \rb64_46 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101111 + assign { } { } + assign $16\perm[7:7] \rb64_47 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110000 + assign { } { } + assign $16\perm[7:7] \rb64_48 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110001 + assign { } { } + assign $16\perm[7:7] \rb64_49 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110010 + assign { } { } + assign $16\perm[7:7] \rb64_50 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110011 + assign { } { } + assign $16\perm[7:7] \rb64_51 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110100 + assign { } { } + assign $16\perm[7:7] \rb64_52 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110101 + assign { } { } + assign $16\perm[7:7] \rb64_53 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110110 + assign { } { } + assign $16\perm[7:7] \rb64_54 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110111 + assign { } { } + assign $16\perm[7:7] \rb64_55 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111000 + assign { } { } + assign $16\perm[7:7] \rb64_56 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111001 + assign { } { } + assign $16\perm[7:7] \rb64_57 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111010 + assign { } { } + assign $16\perm[7:7] \rb64_58 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111011 + assign { } { } + assign $16\perm[7:7] \rb64_59 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111100 + assign { } { } + assign $16\perm[7:7] \rb64_60 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111101 + assign { } { } + assign $16\perm[7:7] \rb64_61 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111110 + assign { } { } + assign $16\perm[7:7] \rb64_62 + attribute \src "libresoc.v:0.0-0.0" + case 8'-------- + assign { } { } + assign $16\perm[7:7] \rb64_63 + case + assign $16\perm[7:7] 1'0 + end + case + assign $15\perm[7:7] 1'0 + end + sync always + update \perm $0\perm[63:0] + end + connect \$9 $lt$libresoc.v:31440$1116_Y + connect \$11 $lt$libresoc.v:31441$1117_Y + connect \$13 $lt$libresoc.v:31442$1118_Y + connect \$15 $lt$libresoc.v:31443$1119_Y + connect \$1 $lt$libresoc.v:31444$1120_Y + connect \$3 $lt$libresoc.v:31445$1121_Y + connect \$5 $lt$libresoc.v:31446$1122_Y + connect \$7 $lt$libresoc.v:31447$1123_Y + connect \ra [7:0] \perm [7:0] + connect \ra [63:8] 56'00000000000000000000000000000000000000000000000000000000 + connect \idx_7 \rs [63:56] + connect \idx_6 \rs [55:48] + connect \idx_5 \rs [47:40] + connect \idx_4 \rs [39:32] + connect \idx_3 \rs [31:24] + connect \idx_2 \rs [23:16] + connect \idx_1 \rs [15:8] + connect \idx_0 \rs [7:0] + connect \rb64_63 \rb [0] + connect \rb64_62 \rb [1] + connect \rb64_61 \rb [2] + connect \rb64_60 \rb [3] + connect \rb64_59 \rb [4] + connect \rb64_58 \rb [5] + connect \rb64_57 \rb [6] + connect \rb64_56 \rb [7] + connect \rb64_55 \rb [8] + connect \rb64_54 \rb [9] + connect \rb64_53 \rb [10] + connect \rb64_52 \rb [11] + connect \rb64_51 \rb [12] + connect \rb64_50 \rb [13] + connect \rb64_49 \rb [14] + connect \rb64_48 \rb [15] + connect \rb64_47 \rb [16] + connect \rb64_46 \rb [17] + connect \rb64_45 \rb [18] + connect \rb64_44 \rb [19] + connect \rb64_43 \rb [20] + connect \rb64_42 \rb [21] + connect \rb64_41 \rb [22] + connect \rb64_40 \rb [23] + connect \rb64_39 \rb [24] + connect \rb64_38 \rb [25] + connect \rb64_37 \rb [26] + connect \rb64_36 \rb [27] + connect \rb64_35 \rb [28] + connect \rb64_34 \rb [29] + connect \rb64_33 \rb [30] + connect \rb64_32 \rb [31] + connect \rb64_31 \rb [32] + connect \rb64_30 \rb [33] + connect \rb64_29 \rb [34] + connect \rb64_28 \rb [35] + connect \rb64_27 \rb [36] + connect \rb64_26 \rb [37] + connect \rb64_25 \rb [38] + connect \rb64_24 \rb [39] + connect \rb64_23 \rb [40] + connect \rb64_22 \rb [41] + connect \rb64_21 \rb [42] + connect \rb64_20 \rb [43] + connect \rb64_19 \rb [44] + connect \rb64_18 \rb [45] + connect \rb64_17 \rb [46] + connect \rb64_16 \rb [47] + connect \rb64_15 \rb [48] + connect \rb64_14 \rb [49] + connect \rb64_13 \rb [50] + connect \rb64_12 \rb [51] + connect \rb64_11 \rb [52] + connect \rb64_10 \rb [53] + connect \rb64_9 \rb [54] + connect \rb64_8 \rb [55] + connect \rb64_7 \rb [56] + connect \rb64_6 \rb [57] + connect \rb64_5 \rb [58] + connect \rb64_4 \rb [59] + connect \rb64_3 \rb [60] + connect \rb64_2 \rb [61] + connect \rb64_1 \rb [62] + connect \rb64_0 \rb [63] +end +attribute \src "libresoc.v:32618.1-33667.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.branch0" +attribute \generator "nMigen" +module \branch0 + attribute \src "libresoc.v:33234.3-33235.25" + wire $0\all_rd_dly[0:0] + attribute \src "libresoc.v:33459.3-33483.6" + wire width 64 $0\alu_branch0_br_op__cia$next[63:0]$1247 + attribute \src "libresoc.v:33258.3-33259.61" + wire width 64 $0\alu_branch0_br_op__cia[63:0] + attribute \src "libresoc.v:33459.3-33483.6" + wire width 12 $0\alu_branch0_br_op__fn_unit$next[11:0]$1248 + attribute \src "libresoc.v:33262.3-33263.69" + wire width 12 $0\alu_branch0_br_op__fn_unit[11:0] + attribute \src "libresoc.v:33459.3-33483.6" + wire width 64 $0\alu_branch0_br_op__imm_data__data$next[63:0]$1249 + attribute \src "libresoc.v:33266.3-33267.83" + wire width 64 $0\alu_branch0_br_op__imm_data__data[63:0] + attribute \src "libresoc.v:33459.3-33483.6" + wire $0\alu_branch0_br_op__imm_data__ok$next[0:0]$1250 + attribute \src "libresoc.v:33268.3-33269.79" + wire $0\alu_branch0_br_op__imm_data__ok[0:0] + attribute \src "libresoc.v:33459.3-33483.6" + wire width 32 $0\alu_branch0_br_op__insn$next[31:0]$1251 + attribute \src "libresoc.v:33264.3-33265.63" + wire width 32 $0\alu_branch0_br_op__insn[31:0] + attribute \src "libresoc.v:33459.3-33483.6" + wire width 7 $0\alu_branch0_br_op__insn_type$next[6:0]$1252 + attribute \src "libresoc.v:33260.3-33261.73" + wire width 7 $0\alu_branch0_br_op__insn_type[6:0] + attribute \src "libresoc.v:33459.3-33483.6" + wire $0\alu_branch0_br_op__is_32bit$next[0:0]$1253 + attribute \src "libresoc.v:33272.3-33273.71" + wire $0\alu_branch0_br_op__is_32bit[0:0] + attribute \src "libresoc.v:33459.3-33483.6" + wire $0\alu_branch0_br_op__lk$next[0:0]$1254 + attribute \src "libresoc.v:33270.3-33271.59" + wire $0\alu_branch0_br_op__lk[0:0] + attribute \src "libresoc.v:33232.3-33233.43" + wire $0\alu_done_dly[0:0] + attribute \src "libresoc.v:33589.3-33597.6" + wire $0\alu_l_r_alu$next[0:0]$1302 + attribute \src "libresoc.v:33236.3-33237.39" + wire $0\alu_l_r_alu[0:0] + attribute \src "libresoc.v:33580.3-33588.6" + wire $0\alui_l_r_alui$next[0:0]$1299 + attribute \src "libresoc.v:33238.3-33239.43" + wire $0\alui_l_r_alui[0:0] + attribute \src "libresoc.v:33484.3-33505.6" + wire width 64 $0\data_r0__fast1$next[63:0]$1266 + attribute \src "libresoc.v:33254.3-33255.45" + wire width 64 $0\data_r0__fast1[63:0] + attribute \src "libresoc.v:33484.3-33505.6" + wire $0\data_r0__fast1_ok$next[0:0]$1267 + attribute \src "libresoc.v:33256.3-33257.51" + wire $0\data_r0__fast1_ok[0:0] + attribute \src "libresoc.v:33506.3-33527.6" + wire width 64 $0\data_r1__fast2$next[63:0]$1274 + attribute \src "libresoc.v:33250.3-33251.45" + wire width 64 $0\data_r1__fast2[63:0] + attribute \src "libresoc.v:33506.3-33527.6" + wire $0\data_r1__fast2_ok$next[0:0]$1275 + attribute \src "libresoc.v:33252.3-33253.51" + wire $0\data_r1__fast2_ok[0:0] + attribute \src "libresoc.v:33528.3-33549.6" + wire width 64 $0\data_r2__nia$next[63:0]$1282 + attribute \src "libresoc.v:33246.3-33247.41" + wire width 64 $0\data_r2__nia[63:0] + attribute \src "libresoc.v:33528.3-33549.6" + wire $0\data_r2__nia_ok$next[0:0]$1283 + attribute \src "libresoc.v:33248.3-33249.47" + wire $0\data_r2__nia_ok[0:0] + attribute \src "libresoc.v:33598.3-33607.6" + wire width 64 $0\dest1_o[63:0] + attribute \src "libresoc.v:33608.3-33617.6" + wire width 64 $0\dest2_o[63:0] + attribute \src "libresoc.v:33618.3-33627.6" + wire width 64 $0\dest3_o[63:0] + attribute \src "libresoc.v:32619.7-32619.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:33414.3-33422.6" + wire $0\opc_l_r_opc$next[0:0]$1232 + attribute \src "libresoc.v:33282.3-33283.39" + wire $0\opc_l_r_opc[0:0] + attribute \src "libresoc.v:33405.3-33413.6" + wire $0\opc_l_s_opc$next[0:0]$1229 + attribute \src "libresoc.v:33284.3-33285.39" + wire $0\opc_l_s_opc[0:0] + attribute \src "libresoc.v:33628.3-33636.6" + wire width 3 $0\prev_wr_go$next[2:0]$1308 + attribute \src "libresoc.v:33230.3-33231.37" + wire width 3 $0\prev_wr_go[2:0] + attribute \src "libresoc.v:33359.3-33368.6" + wire $0\req_done[0:0] + attribute \src "libresoc.v:33450.3-33458.6" + wire width 3 $0\req_l_r_req$next[2:0]$1244 + attribute \src "libresoc.v:33274.3-33275.39" + wire width 3 $0\req_l_r_req[2:0] + attribute \src "libresoc.v:33441.3-33449.6" + wire width 3 $0\req_l_s_req$next[2:0]$1241 + attribute \src "libresoc.v:33276.3-33277.39" + wire width 3 $0\req_l_s_req[2:0] + attribute \src "libresoc.v:33378.3-33386.6" + wire $0\rok_l_r_rdok$next[0:0]$1220 + attribute \src "libresoc.v:33226.3-33227.41" + wire $0\rok_l_r_rdok[0:0] + attribute \src "libresoc.v:33369.3-33377.6" + wire $0\rok_l_s_rdok$next[0:0]$1217 + attribute \src "libresoc.v:33228.3-33229.41" + wire $0\rok_l_s_rdok[0:0] + attribute \src "libresoc.v:33396.3-33404.6" + wire $0\rst_l_r_rst$next[0:0]$1226 + attribute \src "libresoc.v:33222.3-33223.39" + wire $0\rst_l_r_rst[0:0] + attribute \src "libresoc.v:33387.3-33395.6" + wire $0\rst_l_s_rst$next[0:0]$1223 + attribute \src "libresoc.v:33224.3-33225.39" + wire $0\rst_l_s_rst[0:0] + attribute \src "libresoc.v:33432.3-33440.6" + wire width 3 $0\src_l_r_src$next[2:0]$1238 + attribute \src "libresoc.v:33278.3-33279.39" + wire width 3 $0\src_l_r_src[2:0] + attribute \src "libresoc.v:33423.3-33431.6" + wire width 3 $0\src_l_s_src$next[2:0]$1235 + attribute \src "libresoc.v:33280.3-33281.39" + wire width 3 $0\src_l_s_src[2:0] + attribute \src "libresoc.v:33550.3-33559.6" + wire width 64 $0\src_r0$next[63:0]$1290 + attribute \src "libresoc.v:33244.3-33245.29" + wire width 64 $0\src_r0[63:0] + attribute \src "libresoc.v:33560.3-33569.6" + wire width 64 $0\src_r1$next[63:0]$1293 + attribute \src "libresoc.v:33242.3-33243.29" + wire width 64 $0\src_r1[63:0] + attribute \src "libresoc.v:33570.3-33579.6" + wire width 4 $0\src_r2$next[3:0]$1296 + attribute \src "libresoc.v:33240.3-33241.29" + wire width 4 $0\src_r2[3:0] + attribute \src "libresoc.v:32737.7-32737.24" + wire $1\all_rd_dly[0:0] + attribute \src "libresoc.v:33459.3-33483.6" + wire width 64 $1\alu_branch0_br_op__cia$next[63:0]$1255 + attribute \src "libresoc.v:32745.14-32745.59" + wire width 64 $1\alu_branch0_br_op__cia[63:0] + attribute \src "libresoc.v:33459.3-33483.6" + wire width 12 $1\alu_branch0_br_op__fn_unit$next[11:0]$1256 + attribute \src "libresoc.v:32762.14-32762.50" + wire width 12 $1\alu_branch0_br_op__fn_unit[11:0] + attribute \src "libresoc.v:33459.3-33483.6" + wire width 64 $1\alu_branch0_br_op__imm_data__data$next[63:0]$1257 + attribute \src "libresoc.v:32766.14-32766.70" + wire width 64 $1\alu_branch0_br_op__imm_data__data[63:0] + attribute \src "libresoc.v:33459.3-33483.6" + wire $1\alu_branch0_br_op__imm_data__ok$next[0:0]$1258 + attribute \src "libresoc.v:32770.7-32770.45" + wire $1\alu_branch0_br_op__imm_data__ok[0:0] + attribute \src "libresoc.v:33459.3-33483.6" + wire width 32 $1\alu_branch0_br_op__insn$next[31:0]$1259 + attribute \src "libresoc.v:32774.14-32774.45" + wire width 32 $1\alu_branch0_br_op__insn[31:0] + attribute \src "libresoc.v:33459.3-33483.6" + wire width 7 $1\alu_branch0_br_op__insn_type$next[6:0]$1260 + attribute \src "libresoc.v:32852.13-32852.49" + wire width 7 $1\alu_branch0_br_op__insn_type[6:0] + attribute \src "libresoc.v:33459.3-33483.6" + wire $1\alu_branch0_br_op__is_32bit$next[0:0]$1261 + attribute \src "libresoc.v:32856.7-32856.41" + wire $1\alu_branch0_br_op__is_32bit[0:0] + attribute \src "libresoc.v:33459.3-33483.6" + wire $1\alu_branch0_br_op__lk$next[0:0]$1262 + attribute \src "libresoc.v:32860.7-32860.35" + wire $1\alu_branch0_br_op__lk[0:0] + attribute \src "libresoc.v:32886.7-32886.26" + wire $1\alu_done_dly[0:0] + attribute \src "libresoc.v:33589.3-33597.6" + wire $1\alu_l_r_alu$next[0:0]$1303 + attribute \src "libresoc.v:32894.7-32894.25" + wire $1\alu_l_r_alu[0:0] + attribute \src "libresoc.v:33580.3-33588.6" + wire $1\alui_l_r_alui$next[0:0]$1300 + attribute \src "libresoc.v:32906.7-32906.27" + wire $1\alui_l_r_alui[0:0] + attribute \src "libresoc.v:33484.3-33505.6" + wire width 64 $1\data_r0__fast1$next[63:0]$1268 + attribute \src "libresoc.v:32938.14-32938.51" + wire width 64 $1\data_r0__fast1[63:0] + attribute \src "libresoc.v:33484.3-33505.6" + wire $1\data_r0__fast1_ok$next[0:0]$1269 + attribute \src "libresoc.v:32942.7-32942.31" + wire $1\data_r0__fast1_ok[0:0] + attribute \src "libresoc.v:33506.3-33527.6" + wire width 64 $1\data_r1__fast2$next[63:0]$1276 + attribute \src "libresoc.v:32946.14-32946.51" + wire width 64 $1\data_r1__fast2[63:0] + attribute \src "libresoc.v:33506.3-33527.6" + wire $1\data_r1__fast2_ok$next[0:0]$1277 + attribute \src "libresoc.v:32950.7-32950.31" + wire $1\data_r1__fast2_ok[0:0] + attribute \src "libresoc.v:33528.3-33549.6" + wire width 64 $1\data_r2__nia$next[63:0]$1284 + attribute \src "libresoc.v:32954.14-32954.49" + wire width 64 $1\data_r2__nia[63:0] + attribute \src "libresoc.v:33528.3-33549.6" + wire $1\data_r2__nia_ok$next[0:0]$1285 + attribute \src "libresoc.v:32958.7-32958.29" + wire $1\data_r2__nia_ok[0:0] + attribute \src "libresoc.v:33598.3-33607.6" + wire width 64 $1\dest1_o[63:0] + attribute \src "libresoc.v:33608.3-33617.6" + wire width 64 $1\dest2_o[63:0] + attribute \src "libresoc.v:33618.3-33627.6" + wire width 64 $1\dest3_o[63:0] + attribute \src "libresoc.v:33414.3-33422.6" + wire $1\opc_l_r_opc$next[0:0]$1233 + attribute \src "libresoc.v:32979.7-32979.25" + wire $1\opc_l_r_opc[0:0] + attribute \src "libresoc.v:33405.3-33413.6" + wire $1\opc_l_s_opc$next[0:0]$1230 + attribute \src "libresoc.v:32983.7-32983.25" + wire $1\opc_l_s_opc[0:0] + attribute \src "libresoc.v:33628.3-33636.6" + wire width 3 $1\prev_wr_go$next[2:0]$1309 + attribute \src "libresoc.v:33090.13-33090.30" + wire width 3 $1\prev_wr_go[2:0] + attribute \src "libresoc.v:33359.3-33368.6" + wire $1\req_done[0:0] + attribute \src "libresoc.v:33450.3-33458.6" + wire width 3 $1\req_l_r_req$next[2:0]$1245 + attribute \src "libresoc.v:33098.13-33098.31" + wire width 3 $1\req_l_r_req[2:0] + attribute \src "libresoc.v:33441.3-33449.6" + wire width 3 $1\req_l_s_req$next[2:0]$1242 + attribute \src "libresoc.v:33102.13-33102.31" + wire width 3 $1\req_l_s_req[2:0] + attribute \src "libresoc.v:33378.3-33386.6" + wire $1\rok_l_r_rdok$next[0:0]$1221 + attribute \src "libresoc.v:33114.7-33114.26" + wire $1\rok_l_r_rdok[0:0] + attribute \src "libresoc.v:33369.3-33377.6" + wire $1\rok_l_s_rdok$next[0:0]$1218 + attribute \src "libresoc.v:33118.7-33118.26" + wire $1\rok_l_s_rdok[0:0] + attribute \src "libresoc.v:33396.3-33404.6" + wire $1\rst_l_r_rst$next[0:0]$1227 + attribute \src "libresoc.v:33122.7-33122.25" + wire $1\rst_l_r_rst[0:0] + attribute \src "libresoc.v:33387.3-33395.6" + wire $1\rst_l_s_rst$next[0:0]$1224 + attribute \src "libresoc.v:33126.7-33126.25" + wire $1\rst_l_s_rst[0:0] + attribute \src "libresoc.v:33432.3-33440.6" + wire width 3 $1\src_l_r_src$next[2:0]$1239 + attribute \src "libresoc.v:33140.13-33140.31" + wire width 3 $1\src_l_r_src[2:0] + attribute \src "libresoc.v:33423.3-33431.6" + wire width 3 $1\src_l_s_src$next[2:0]$1236 + attribute \src "libresoc.v:33144.13-33144.31" + wire width 3 $1\src_l_s_src[2:0] + attribute \src "libresoc.v:33550.3-33559.6" + wire width 64 $1\src_r0$next[63:0]$1291 + attribute \src "libresoc.v:33150.14-33150.43" + wire width 64 $1\src_r0[63:0] + attribute \src "libresoc.v:33560.3-33569.6" + wire width 64 $1\src_r1$next[63:0]$1294 + attribute \src "libresoc.v:33154.14-33154.43" + wire width 64 $1\src_r1[63:0] + attribute \src "libresoc.v:33570.3-33579.6" + wire width 4 $1\src_r2$next[3:0]$1297 + attribute \src "libresoc.v:33158.13-33158.26" + wire width 4 $1\src_r2[3:0] + attribute \src "libresoc.v:33459.3-33483.6" + wire width 64 $2\alu_branch0_br_op__imm_data__data$next[63:0]$1263 + attribute \src "libresoc.v:33459.3-33483.6" + wire $2\alu_branch0_br_op__imm_data__ok$next[0:0]$1264 + attribute \src "libresoc.v:33484.3-33505.6" + wire width 64 $2\data_r0__fast1$next[63:0]$1270 + attribute \src "libresoc.v:33484.3-33505.6" + wire $2\data_r0__fast1_ok$next[0:0]$1271 + attribute \src "libresoc.v:33506.3-33527.6" + wire width 64 $2\data_r1__fast2$next[63:0]$1278 + attribute \src "libresoc.v:33506.3-33527.6" + wire $2\data_r1__fast2_ok$next[0:0]$1279 + attribute \src "libresoc.v:33528.3-33549.6" + wire width 64 $2\data_r2__nia$next[63:0]$1286 + attribute \src "libresoc.v:33528.3-33549.6" + wire $2\data_r2__nia_ok$next[0:0]$1287 + attribute \src "libresoc.v:33484.3-33505.6" + wire $3\data_r0__fast1_ok$next[0:0]$1272 + attribute \src "libresoc.v:33506.3-33527.6" + wire $3\data_r1__fast2_ok$next[0:0]$1280 + attribute \src "libresoc.v:33528.3-33549.6" + wire $3\data_r2__nia_ok$next[0:0]$1288 + attribute \src "libresoc.v:33166.18-33166.112" + wire width 3 $and$libresoc.v:33166$1127_Y + attribute \src "libresoc.v:33167.19-33167.125" + wire $and$libresoc.v:33167$1128_Y + attribute \src "libresoc.v:33168.19-33168.125" + wire $and$libresoc.v:33168$1129_Y + attribute \src "libresoc.v:33169.19-33169.125" + wire $and$libresoc.v:33169$1130_Y + attribute \src "libresoc.v:33170.19-33170.141" + wire width 3 $and$libresoc.v:33170$1131_Y + attribute \src "libresoc.v:33171.19-33171.121" + wire width 3 $and$libresoc.v:33171$1132_Y + attribute \src "libresoc.v:33172.19-33172.127" + wire $and$libresoc.v:33172$1133_Y + attribute \src "libresoc.v:33173.19-33173.127" + wire $and$libresoc.v:33173$1134_Y + attribute \src "libresoc.v:33174.19-33174.127" + wire $and$libresoc.v:33174$1135_Y + attribute \src "libresoc.v:33175.18-33175.110" + wire $and$libresoc.v:33175$1136_Y + attribute \src "libresoc.v:33177.18-33177.98" + wire $and$libresoc.v:33177$1138_Y + attribute \src "libresoc.v:33179.18-33179.100" + wire $and$libresoc.v:33179$1140_Y + attribute \src "libresoc.v:33180.18-33180.149" + wire width 3 $and$libresoc.v:33180$1141_Y + attribute \src "libresoc.v:33182.18-33182.119" + wire width 3 $and$libresoc.v:33182$1143_Y + attribute \src "libresoc.v:33185.18-33185.116" + wire $and$libresoc.v:33185$1146_Y + attribute \src "libresoc.v:33189.17-33189.123" + wire $and$libresoc.v:33189$1150_Y + attribute \src "libresoc.v:33191.18-33191.113" + wire $and$libresoc.v:33191$1152_Y + attribute \src "libresoc.v:33192.18-33192.125" + wire width 3 $and$libresoc.v:33192$1153_Y + attribute \src "libresoc.v:33194.18-33194.112" + wire $and$libresoc.v:33194$1155_Y + attribute \src "libresoc.v:33196.18-33196.129" + wire $and$libresoc.v:33196$1157_Y + attribute \src "libresoc.v:33197.18-33197.129" + wire $and$libresoc.v:33197$1158_Y + attribute \src "libresoc.v:33198.18-33198.117" + wire $and$libresoc.v:33198$1159_Y + attribute \src "libresoc.v:33203.18-33203.133" + wire $and$libresoc.v:33203$1164_Y + attribute \src "libresoc.v:33204.18-33204.124" + wire width 3 $and$libresoc.v:33204$1165_Y + attribute \src "libresoc.v:33207.18-33207.120" + wire $and$libresoc.v:33207$1168_Y + attribute \src "libresoc.v:33208.18-33208.120" + wire $and$libresoc.v:33208$1169_Y + attribute \src "libresoc.v:33209.18-33209.118" + wire $and$libresoc.v:33209$1170_Y + attribute \src "libresoc.v:33215.18-33215.137" + wire $and$libresoc.v:33215$1176_Y + attribute \src "libresoc.v:33217.18-33217.135" + wire $and$libresoc.v:33217$1178_Y + attribute \src "libresoc.v:33218.18-33218.149" + wire width 3 $and$libresoc.v:33218$1179_Y + attribute \src "libresoc.v:33220.18-33220.129" + wire width 3 $and$libresoc.v:33220$1181_Y + attribute \src "libresoc.v:33193.18-33193.113" + wire $eq$libresoc.v:33193$1154_Y + attribute \src "libresoc.v:33195.18-33195.119" + wire $eq$libresoc.v:33195$1156_Y + attribute \src "libresoc.v:33176.18-33176.97" + wire $not$libresoc.v:33176$1137_Y + attribute \src "libresoc.v:33178.18-33178.99" + wire $not$libresoc.v:33178$1139_Y + attribute \src "libresoc.v:33181.18-33181.113" + wire width 3 $not$libresoc.v:33181$1142_Y + attribute \src "libresoc.v:33184.18-33184.106" + wire $not$libresoc.v:33184$1145_Y + attribute \src "libresoc.v:33190.18-33190.123" + wire $not$libresoc.v:33190$1151_Y + attribute \src "libresoc.v:33205.17-33205.113" + wire width 3 $not$libresoc.v:33205$1166_Y + attribute \src "libresoc.v:33219.18-33219.133" + wire $not$libresoc.v:33219$1180_Y + attribute \src "libresoc.v:33221.18-33221.114" + wire width 3 $not$libresoc.v:33221$1182_Y + attribute \src "libresoc.v:33188.18-33188.112" + wire $or$libresoc.v:33188$1149_Y + attribute \src "libresoc.v:33199.18-33199.122" + wire $or$libresoc.v:33199$1160_Y + attribute \src "libresoc.v:33200.18-33200.124" + wire $or$libresoc.v:33200$1161_Y + attribute \src "libresoc.v:33201.18-33201.155" + wire width 3 $or$libresoc.v:33201$1162_Y + attribute \src "libresoc.v:33202.18-33202.155" + wire width 3 $or$libresoc.v:33202$1163_Y + attribute \src "libresoc.v:33206.18-33206.120" + wire width 3 $or$libresoc.v:33206$1167_Y + attribute \src "libresoc.v:33216.17-33216.117" + wire width 3 $or$libresoc.v:33216$1177_Y + attribute \src "libresoc.v:33165.17-33165.104" + wire $reduce_and$libresoc.v:33165$1126_Y + attribute \src "libresoc.v:33183.18-33183.106" + wire $reduce_or$libresoc.v:33183$1144_Y + attribute \src "libresoc.v:33186.18-33186.113" + wire $reduce_or$libresoc.v:33186$1147_Y + attribute \src "libresoc.v:33187.18-33187.112" + wire $reduce_or$libresoc.v:33187$1148_Y + attribute \src "libresoc.v:33210.18-33210.162" + wire $ternary$libresoc.v:33210$1171_Y + attribute \src "libresoc.v:33211.18-33211.176" + wire width 64 $ternary$libresoc.v:33211$1172_Y + attribute \src "libresoc.v:33212.18-33212.118" + wire width 64 $ternary$libresoc.v:33212$1173_Y + attribute \src "libresoc.v:33213.18-33213.115" + wire width 64 $ternary$libresoc.v:33213$1174_Y + attribute \src "libresoc.v:33214.18-33214.118" + wire width 4 $ternary$libresoc.v:33214$1175_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + wire \$101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + wire \$103 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + wire \$105 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" + wire width 3 \$107 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" + wire width 3 \$109 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + wire \$111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + wire \$113 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + wire \$115 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire \$17 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" + wire width 3 \$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + wire width 3 \$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + wire width 3 \$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + wire \$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + wire \$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + wire \$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + wire \$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + wire \$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + wire width 3 \$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + wire \$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + wire \$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + wire \$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + wire \$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + wire \$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + wire \$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" + wire \$57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" + wire \$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + wire width 3 \$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" + wire width 3 \$61 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" + wire width 3 \$63 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" + wire \$65 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" + wire width 3 \$67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" + wire width 3 \$69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + wire \$71 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + wire \$73 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + wire \$75 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" + wire \$77 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" + wire width 64 \$79 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + wire width 3 \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 64 \$81 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 64 \$83 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 4 \$85 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" + wire \$87 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" + wire \$89 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + wire width 3 \$91 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" + wire \$93 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + wire width 3 \$95 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + wire width 3 \$97 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + wire width 3 \$99 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:187" + wire \all_rd + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire \all_rd_dly + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire \all_rd_dly$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:192" + wire \all_rd_pulse + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + wire \all_rd_rise + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \alu_branch0_br_op__cia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \alu_branch0_br_op__cia$next + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \alu_branch0_br_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \alu_branch0_br_op__fn_unit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \alu_branch0_br_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \alu_branch0_br_op__imm_data__data$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_branch0_br_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_branch0_br_op__imm_data__ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \alu_branch0_br_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \alu_branch0_br_op__insn$next + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \alu_branch0_br_op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \alu_branch0_br_op__insn_type$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_branch0_br_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_branch0_br_op__is_32bit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_branch0_br_op__lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_branch0_br_op__lk$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 4 \alu_branch0_cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \alu_branch0_fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \alu_branch0_fast1$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \alu_branch0_fast2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \alu_branch0_fast2$2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire \alu_branch0_n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire \alu_branch0_n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \alu_branch0_nia + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire \alu_branch0_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire \alu_branch0_p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:196" + wire \alu_done + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire \alu_done_dly + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire \alu_done_dly$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + wire \alu_done_rise + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire \alu_l_q_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \alu_l_r_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \alu_l_r_alu$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \alu_l_s_alu + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:197" + wire \alu_pulse + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198" + wire width 3 \alu_pulsem + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire \alui_l_q_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \alui_l_r_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \alui_l_r_alui$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \alui_l_s_alui + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 26 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 25 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" + wire output 10 \cu_busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:108" + wire \cu_done_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:104" + wire \cu_go_die_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" + wire input 9 \cu_issue_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 input 13 \cu_rd__go_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 output 12 \cu_rd__rel_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" + wire width 3 input 11 \cu_rdmaskn_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:102" + wire \cu_shadown_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 input 19 \cu_wr__go_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 output 18 \cu_wr__rel_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:97" + wire width 3 \cu_wrmask_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 64 \data_r0__fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 64 \data_r0__fast1$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r0__fast1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r0__fast1_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 64 \data_r1__fast2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 64 \data_r1__fast2$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r1__fast2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r1__fast2_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 64 \data_r2__nia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 64 \data_r2__nia$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r2__nia_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r2__nia_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 21 \dest1_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 22 \dest2_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 24 \dest3_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 17 \fast1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 20 \fast2_ok + attribute \src "libresoc.v:32619.7-32619.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 23 \nia_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire \opc_l_q_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \opc_l_r_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \opc_l_r_opc$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \opc_l_s_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \opc_l_s_opc$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 1 \oper_i_alu_branch0__cia + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 3 \oper_i_alu_branch0__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 5 \oper_i_alu_branch0__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 6 \oper_i_alu_branch0__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 4 \oper_i_alu_branch0__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 2 \oper_i_alu_branch0__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \oper_i_alu_branch0__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 7 \oper_i_alu_branch0__lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" + wire width 3 \prev_wr_go + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" + wire width 3 \prev_wr_go$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212" + wire \req_done + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 3 \req_l_q_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 3 \req_l_r_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 3 \req_l_r_req$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 3 \req_l_s_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 3 \req_l_s_req$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226" + wire \reset + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:229" + wire width 3 \reset_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:228" + wire width 3 \reset_w + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire \rok_l_q_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \rok_l_r_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \rok_l_r_rdok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \rok_l_s_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \rok_l_s_rdok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \rst_l_r_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \rst_l_r_rst$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \rst_l_s_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \rst_l_s_rst$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227" + wire \rst_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 15 \src1_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 16 \src2_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 4 input 14 \src3_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 3 \src_l_q_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 3 \src_l_r_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 3 \src_l_r_src$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 3 \src_l_s_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 3 \src_l_s_src$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:166" + wire width 64 \src_or_imm + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 64 \src_r0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 64 \src_r0$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 64 \src_r1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 64 \src_r1$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 4 \src_r2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 4 \src_r2$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:167" + wire \src_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" + wire \wr_any + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + cell $and $and$libresoc.v:33166$1127 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \$95 + connect \B \$97 + connect \Y $and$libresoc.v:33166$1127_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + cell $and $and$libresoc.v:33167$1128 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_busy_o + connect \B \cu_shadown_i + connect \Y $and$libresoc.v:33167$1128_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + cell $and $and$libresoc.v:33168$1129 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_busy_o + connect \B \cu_shadown_i + connect \Y $and$libresoc.v:33168$1129_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + cell $and $and$libresoc.v:33169$1130 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_busy_o + connect \B \cu_shadown_i + connect \Y $and$libresoc.v:33169$1130_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" + cell $and $and$libresoc.v:33170$1131 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \req_l_q_req + connect \B { \$101 \$103 \$105 } + connect \Y $and$libresoc.v:33170$1131_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" + cell $and $and$libresoc.v:33171$1132 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \$107 + connect \B \cu_wrmask_o + connect \Y $and$libresoc.v:33171$1132_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + cell $and $and$libresoc.v:33172$1133 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_wr__go_i [0] + connect \B \cu_busy_o + connect \Y $and$libresoc.v:33172$1133_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + cell $and $and$libresoc.v:33173$1134 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_wr__go_i [1] + connect \B \cu_busy_o + connect \Y $and$libresoc.v:33173$1134_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + cell $and $and$libresoc.v:33174$1135 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_wr__go_i [2] + connect \B \cu_busy_o + connect \Y $and$libresoc.v:33174$1135_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $and $and$libresoc.v:33175$1136 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \$5 + connect \Y $and$libresoc.v:33175$1136_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $and$libresoc.v:33177$1138 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \all_rd + connect \B \$13 + connect \Y $and$libresoc.v:33177$1138_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $and$libresoc.v:33179$1140 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_done + connect \B \$17 + connect \Y $and$libresoc.v:33179$1140_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" + cell $and $and$libresoc.v:33180$1141 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \cu_wr__go_i + connect \B { \cu_busy_o \cu_busy_o \cu_busy_o } + connect \Y $and$libresoc.v:33180$1141_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $and $and$libresoc.v:33182$1143 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \cu_wr__rel_o + connect \B \$25 + connect \Y $and$libresoc.v:33182$1143_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $and $and$libresoc.v:33185$1146 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_busy_o + connect \B \$23 + connect \Y $and$libresoc.v:33185$1146_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" + cell $and $and$libresoc.v:33189$1150 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_busy_o + connect \B \rok_l_q_rdok + connect \Y $and$libresoc.v:33189$1150_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + cell $and $and$libresoc.v:33191$1152 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_any + connect \B \$39 + connect \Y $and$libresoc.v:33191$1152_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + cell $and $and$libresoc.v:33192$1153 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \req_l_q_req + connect \B \cu_wrmask_o + connect \Y $and$libresoc.v:33192$1153_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + cell $and $and$libresoc.v:33194$1155 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$41 + connect \B \$45 + connect \Y $and$libresoc.v:33194$1155_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + cell $and $and$libresoc.v:33196$1157 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$49 + connect \B \alu_branch0_n_ready_i + connect \Y $and$libresoc.v:33196$1157_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + cell $and $and$libresoc.v:33197$1158 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$51 + connect \B \alu_branch0_n_valid_o + connect \Y $and$libresoc.v:33197$1158_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + cell $and $and$libresoc.v:33198$1159 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$53 + connect \B \cu_busy_o + connect \Y $and$libresoc.v:33198$1159_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" + cell $and $and$libresoc.v:33203$1164 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_branch0_n_valid_o + connect \B \cu_busy_o + connect \Y $and$libresoc.v:33203$1164_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" + cell $and $and$libresoc.v:33204$1165 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \alu_pulsem + connect \B \cu_wrmask_o + connect \Y $and$libresoc.v:33204$1165_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + cell $and $and$libresoc.v:33207$1168 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fast1_ok + connect \B \cu_busy_o + connect \Y $and$libresoc.v:33207$1168_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + cell $and $and$libresoc.v:33208$1169 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fast2_ok + connect \B \cu_busy_o + connect \Y $and$libresoc.v:33208$1169_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + cell $and $and$libresoc.v:33209$1170 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \nia_ok + connect \B \cu_busy_o + connect \Y $and$libresoc.v:33209$1170_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" + cell $and $and$libresoc.v:33215$1176 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_branch0_p_ready_o + connect \B \alui_l_q_alui + connect \Y $and$libresoc.v:33215$1176_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" + cell $and $and$libresoc.v:33217$1178 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_branch0_n_valid_o + connect \B \alu_l_q_alu + connect \Y $and$libresoc.v:33217$1178_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + cell $and $and$libresoc.v:33218$1179 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \src_l_q_src + connect \B { \cu_busy_o \cu_busy_o \cu_busy_o } + connect \Y $and$libresoc.v:33218$1179_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + cell $and $and$libresoc.v:33220$1181 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \$91 + connect \B { 1'1 \$93 1'1 } + connect \Y $and$libresoc.v:33220$1181_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + cell $eq $eq$libresoc.v:33193$1154 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$43 + connect \B 1'0 + connect \Y $eq$libresoc.v:33193$1154_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + cell $eq $eq$libresoc.v:33195$1156 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_wrmask_o + connect \B 1'0 + connect \Y $eq$libresoc.v:33195$1156_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $not$libresoc.v:33176$1137 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \all_rd_dly + connect \Y $not$libresoc.v:33176$1137_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $not$libresoc.v:33178$1139 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_done_dly + connect \Y $not$libresoc.v:33178$1139_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $not $not$libresoc.v:33181$1142 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \cu_wrmask_o + connect \Y $not$libresoc.v:33181$1142_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $not $not$libresoc.v:33184$1145 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$24 + connect \Y $not$libresoc.v:33184$1145_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + cell $not $not$libresoc.v:33190$1151 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_branch0_n_ready_i + connect \Y $not$libresoc.v:33190$1151_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $not $not$libresoc.v:33205$1166 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \cu_rd__rel_o + connect \Y $not$libresoc.v:33205$1166_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" + cell $not $not$libresoc.v:33219$1180 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_branch0_br_op__imm_data__ok + connect \Y $not$libresoc.v:33219$1180_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + cell $not $not$libresoc.v:33221$1182 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \cu_rdmaskn_i + connect \Y $not$libresoc.v:33221$1182_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $or $or$libresoc.v:33188$1149 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$33 + connect \B \$35 + connect \Y $or$libresoc.v:33188$1149_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" + cell $or $or$libresoc.v:33199$1160 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \req_done + connect \B \cu_go_die_i + connect \Y $or$libresoc.v:33199$1160_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" + cell $or $or$libresoc.v:33200$1161 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_issue_i + connect \B \cu_go_die_i + connect \Y $or$libresoc.v:33200$1161_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" + cell $or $or$libresoc.v:33201$1162 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \cu_wr__go_i + connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } + connect \Y $or$libresoc.v:33201$1162_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" + cell $or $or$libresoc.v:33202$1163 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \cu_rd__go_i + connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } + connect \Y $or$libresoc.v:33202$1163_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" + cell $or $or$libresoc.v:33206$1167 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \reset_w + connect \B \prev_wr_go + connect \Y $or$libresoc.v:33206$1167_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $or $or$libresoc.v:33216$1177 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \$6 + connect \B \cu_rd__go_i + connect \Y $or$libresoc.v:33216$1177_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $reduce_and $reduce_and$libresoc.v:33165$1126 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $reduce_and$libresoc.v:33165$1126_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $reduce_or $reduce_or$libresoc.v:33183$1144 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \$27 + connect \Y $reduce_or$libresoc.v:33183$1144_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $reduce_or $reduce_or$libresoc.v:33186$1147 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \cu_wr__go_i + connect \Y $reduce_or$libresoc.v:33186$1147_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $reduce_or $reduce_or$libresoc.v:33187$1148 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \prev_wr_go + connect \Y $reduce_or$libresoc.v:33187$1148_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" + cell $mux $ternary$libresoc.v:33210$1171 + parameter \WIDTH 1 + connect \A \src_l_q_src [1] + connect \B \opc_l_q_opc + connect \S \alu_branch0_br_op__imm_data__ok + connect \Y $ternary$libresoc.v:33210$1171_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" + cell $mux $ternary$libresoc.v:33211$1172 + parameter \WIDTH 64 + connect \A \src2_i + connect \B \alu_branch0_br_op__imm_data__data + connect \S \alu_branch0_br_op__imm_data__ok + connect \Y $ternary$libresoc.v:33211$1172_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $ternary$libresoc.v:33212$1173 + parameter \WIDTH 64 + connect \A \src_r0 + connect \B \src1_i + connect \S \src_l_q_src [0] + connect \Y $ternary$libresoc.v:33212$1173_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $ternary$libresoc.v:33213$1174 + parameter \WIDTH 64 + connect \A \src_r1 + connect \B \src_or_imm + connect \S \src_sel + connect \Y $ternary$libresoc.v:33213$1174_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $ternary$libresoc.v:33214$1175 + parameter \WIDTH 4 + connect \A \src_r2 + connect \B \src3_i + connect \S \src_l_q_src [2] + connect \Y $ternary$libresoc.v:33214$1175_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:33286.15-33310.4" + cell \alu_branch0 \alu_branch0 + connect \br_op__cia \alu_branch0_br_op__cia + connect \br_op__fn_unit \alu_branch0_br_op__fn_unit + connect \br_op__imm_data__data \alu_branch0_br_op__imm_data__data + connect \br_op__imm_data__ok \alu_branch0_br_op__imm_data__ok + connect \br_op__insn \alu_branch0_br_op__insn + connect \br_op__insn_type \alu_branch0_br_op__insn_type + connect \br_op__is_32bit \alu_branch0_br_op__is_32bit + connect \br_op__lk \alu_branch0_br_op__lk + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cr_a \alu_branch0_cr_a + connect \fast1 \alu_branch0_fast1 + connect \fast1$1 \alu_branch0_fast1$1 + connect \fast1_ok \fast1_ok + connect \fast2 \alu_branch0_fast2 + connect \fast2$2 \alu_branch0_fast2$2 + connect \fast2_ok \fast2_ok + connect \n_ready_i \alu_branch0_n_ready_i + connect \n_valid_o \alu_branch0_n_valid_o + connect \nia \alu_branch0_nia + connect \nia_ok \nia_ok + connect \p_ready_o \alu_branch0_p_ready_o + connect \p_valid_i \alu_branch0_p_valid_i + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:33311.14-33317.4" + cell \alu_l$29 \alu_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_alu \alu_l_q_alu + connect \r_alu \alu_l_r_alu + connect \s_alu \alu_l_s_alu + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:33318.15-33324.4" + cell \alui_l$28 \alui_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_alui \alui_l_q_alui + connect \r_alui \alui_l_r_alui + connect \s_alui \alui_l_s_alui + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:33325.14-33331.4" + cell \opc_l$24 \opc_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_opc \opc_l_q_opc + connect \r_opc \opc_l_r_opc + connect \s_opc \opc_l_s_opc + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:33332.14-33338.4" + cell \req_l$25 \req_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_req \req_l_q_req + connect \r_req \req_l_r_req + connect \s_req \req_l_s_req + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:33339.14-33345.4" + cell \rok_l$27 \rok_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_rdok \rok_l_q_rdok + connect \r_rdok \rok_l_r_rdok + connect \s_rdok \rok_l_s_rdok + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:33346.14-33351.4" + cell \rst_l$26 \rst_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \r_rst \rst_l_r_rst + connect \s_rst \rst_l_s_rst + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:33352.14-33358.4" + cell \src_l$23 \src_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_src \src_l_q_src + connect \r_src \src_l_r_src + connect \s_src \src_l_s_src + end + attribute \src "libresoc.v:32619.7-32619.20" + process $proc$libresoc.v:32619$1310 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:32737.7-32737.24" + process $proc$libresoc.v:32737$1311 + assign { } { } + assign $1\all_rd_dly[0:0] 1'0 + sync always + sync init + update \all_rd_dly $1\all_rd_dly[0:0] + end + attribute \src "libresoc.v:32745.14-32745.59" + process $proc$libresoc.v:32745$1312 + assign { } { } + assign $1\alu_branch0_br_op__cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \alu_branch0_br_op__cia $1\alu_branch0_br_op__cia[63:0] + end + attribute \src "libresoc.v:32762.14-32762.50" + process $proc$libresoc.v:32762$1313 + assign { } { } + assign $1\alu_branch0_br_op__fn_unit[11:0] 12'000000000000 + sync always + sync init + update \alu_branch0_br_op__fn_unit $1\alu_branch0_br_op__fn_unit[11:0] + end + attribute \src "libresoc.v:32766.14-32766.70" + process $proc$libresoc.v:32766$1314 + assign { } { } + assign $1\alu_branch0_br_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \alu_branch0_br_op__imm_data__data $1\alu_branch0_br_op__imm_data__data[63:0] + end + attribute \src "libresoc.v:32770.7-32770.45" + process $proc$libresoc.v:32770$1315 + assign { } { } + assign $1\alu_branch0_br_op__imm_data__ok[0:0] 1'0 + sync always + sync init + update \alu_branch0_br_op__imm_data__ok $1\alu_branch0_br_op__imm_data__ok[0:0] + end + attribute \src "libresoc.v:32774.14-32774.45" + process $proc$libresoc.v:32774$1316 + assign { } { } + assign $1\alu_branch0_br_op__insn[31:0] 0 + sync always + sync init + update \alu_branch0_br_op__insn $1\alu_branch0_br_op__insn[31:0] + end + attribute \src "libresoc.v:32852.13-32852.49" + process $proc$libresoc.v:32852$1317 + assign { } { } + assign $1\alu_branch0_br_op__insn_type[6:0] 7'0000000 + sync always + sync init + update \alu_branch0_br_op__insn_type $1\alu_branch0_br_op__insn_type[6:0] + end + attribute \src "libresoc.v:32856.7-32856.41" + process $proc$libresoc.v:32856$1318 + assign { } { } + assign $1\alu_branch0_br_op__is_32bit[0:0] 1'0 + sync always + sync init + update \alu_branch0_br_op__is_32bit $1\alu_branch0_br_op__is_32bit[0:0] + end + attribute \src "libresoc.v:32860.7-32860.35" + process $proc$libresoc.v:32860$1319 + assign { } { } + assign $1\alu_branch0_br_op__lk[0:0] 1'0 + sync always + sync init + update \alu_branch0_br_op__lk $1\alu_branch0_br_op__lk[0:0] + end + attribute \src "libresoc.v:32886.7-32886.26" + process $proc$libresoc.v:32886$1320 + assign { } { } + assign $1\alu_done_dly[0:0] 1'0 + sync always + sync init + update \alu_done_dly $1\alu_done_dly[0:0] + end + attribute \src "libresoc.v:32894.7-32894.25" + process $proc$libresoc.v:32894$1321 + assign { } { } + assign $1\alu_l_r_alu[0:0] 1'1 + sync always + sync init + update \alu_l_r_alu $1\alu_l_r_alu[0:0] + end + attribute \src "libresoc.v:32906.7-32906.27" + process $proc$libresoc.v:32906$1322 + assign { } { } + assign $1\alui_l_r_alui[0:0] 1'1 + sync always + sync init + update \alui_l_r_alui $1\alui_l_r_alui[0:0] + end + attribute \src "libresoc.v:32938.14-32938.51" + process $proc$libresoc.v:32938$1323 + assign { } { } + assign $1\data_r0__fast1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \data_r0__fast1 $1\data_r0__fast1[63:0] + end + attribute \src "libresoc.v:32942.7-32942.31" + process $proc$libresoc.v:32942$1324 + assign { } { } + assign $1\data_r0__fast1_ok[0:0] 1'0 + sync always + sync init + update \data_r0__fast1_ok $1\data_r0__fast1_ok[0:0] + end + attribute \src "libresoc.v:32946.14-32946.51" + process $proc$libresoc.v:32946$1325 + assign { } { } + assign $1\data_r1__fast2[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \data_r1__fast2 $1\data_r1__fast2[63:0] + end + attribute \src "libresoc.v:32950.7-32950.31" + process $proc$libresoc.v:32950$1326 + assign { } { } + assign $1\data_r1__fast2_ok[0:0] 1'0 + sync always + sync init + update \data_r1__fast2_ok $1\data_r1__fast2_ok[0:0] + end + attribute \src "libresoc.v:32954.14-32954.49" + process $proc$libresoc.v:32954$1327 + assign { } { } + assign $1\data_r2__nia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \data_r2__nia $1\data_r2__nia[63:0] + end + attribute \src "libresoc.v:32958.7-32958.29" + process $proc$libresoc.v:32958$1328 + assign { } { } + assign $1\data_r2__nia_ok[0:0] 1'0 + sync always + sync init + update \data_r2__nia_ok $1\data_r2__nia_ok[0:0] + end + attribute \src "libresoc.v:32979.7-32979.25" + process $proc$libresoc.v:32979$1329 + assign { } { } + assign $1\opc_l_r_opc[0:0] 1'1 + sync always + sync init + update \opc_l_r_opc $1\opc_l_r_opc[0:0] + end + attribute \src "libresoc.v:32983.7-32983.25" + process $proc$libresoc.v:32983$1330 + assign { } { } + assign $1\opc_l_s_opc[0:0] 1'0 + sync always + sync init + update \opc_l_s_opc $1\opc_l_s_opc[0:0] + end + attribute \src "libresoc.v:33090.13-33090.30" + process $proc$libresoc.v:33090$1331 + assign { } { } + assign $1\prev_wr_go[2:0] 3'000 + sync always + sync init + update \prev_wr_go $1\prev_wr_go[2:0] + end + attribute \src "libresoc.v:33098.13-33098.31" + process $proc$libresoc.v:33098$1332 + assign { } { } + assign $1\req_l_r_req[2:0] 3'111 + sync always + sync init + update \req_l_r_req $1\req_l_r_req[2:0] + end + attribute \src "libresoc.v:33102.13-33102.31" + process $proc$libresoc.v:33102$1333 + assign { } { } + assign $1\req_l_s_req[2:0] 3'000 + sync always + sync init + update \req_l_s_req $1\req_l_s_req[2:0] + end + attribute \src "libresoc.v:33114.7-33114.26" + process $proc$libresoc.v:33114$1334 + assign { } { } + assign $1\rok_l_r_rdok[0:0] 1'1 + sync always + sync init + update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] + end + attribute \src "libresoc.v:33118.7-33118.26" + process $proc$libresoc.v:33118$1335 + assign { } { } + assign $1\rok_l_s_rdok[0:0] 1'0 + sync always + sync init + update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] + end + attribute \src "libresoc.v:33122.7-33122.25" + process $proc$libresoc.v:33122$1336 + assign { } { } + assign $1\rst_l_r_rst[0:0] 1'1 + sync always + sync init + update \rst_l_r_rst $1\rst_l_r_rst[0:0] + end + attribute \src "libresoc.v:33126.7-33126.25" + process $proc$libresoc.v:33126$1337 + assign { } { } + assign $1\rst_l_s_rst[0:0] 1'0 + sync always + sync init + update \rst_l_s_rst $1\rst_l_s_rst[0:0] + end + attribute \src "libresoc.v:33140.13-33140.31" + process $proc$libresoc.v:33140$1338 + assign { } { } + assign $1\src_l_r_src[2:0] 3'111 + sync always + sync init + update \src_l_r_src $1\src_l_r_src[2:0] + end + attribute \src "libresoc.v:33144.13-33144.31" + process $proc$libresoc.v:33144$1339 + assign { } { } + assign $1\src_l_s_src[2:0] 3'000 + sync always + sync init + update \src_l_s_src $1\src_l_s_src[2:0] + end + attribute \src "libresoc.v:33150.14-33150.43" + process $proc$libresoc.v:33150$1340 + assign { } { } + assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \src_r0 $1\src_r0[63:0] + end + attribute \src "libresoc.v:33154.14-33154.43" + process $proc$libresoc.v:33154$1341 + assign { } { } + assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \src_r1 $1\src_r1[63:0] + end + attribute \src "libresoc.v:33158.13-33158.26" + process $proc$libresoc.v:33158$1342 + assign { } { } + assign $1\src_r2[3:0] 4'0000 + sync always + sync init + update \src_r2 $1\src_r2[3:0] + end + attribute \src "libresoc.v:33222.3-33223.39" + process $proc$libresoc.v:33222$1183 + assign { } { } + assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next + sync posedge \coresync_clk + update \rst_l_r_rst $0\rst_l_r_rst[0:0] + end + attribute \src "libresoc.v:33224.3-33225.39" + process $proc$libresoc.v:33224$1184 + assign { } { } + assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next + sync posedge \coresync_clk + update \rst_l_s_rst $0\rst_l_s_rst[0:0] + end + attribute \src "libresoc.v:33226.3-33227.41" + process $proc$libresoc.v:33226$1185 + assign { } { } + assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next + sync posedge \coresync_clk + update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] + end + attribute \src "libresoc.v:33228.3-33229.41" + process $proc$libresoc.v:33228$1186 + assign { } { } + assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next + sync posedge \coresync_clk + update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] + end + attribute \src "libresoc.v:33230.3-33231.37" + process $proc$libresoc.v:33230$1187 + assign { } { } + assign $0\prev_wr_go[2:0] \prev_wr_go$next + sync posedge \coresync_clk + update \prev_wr_go $0\prev_wr_go[2:0] + end + attribute \src "libresoc.v:33232.3-33233.43" + process $proc$libresoc.v:33232$1188 + assign { } { } + assign $0\alu_done_dly[0:0] \alu_branch0_n_valid_o + sync posedge \coresync_clk + update \alu_done_dly $0\alu_done_dly[0:0] + end + attribute \src "libresoc.v:33234.3-33235.25" + process $proc$libresoc.v:33234$1189 + assign { } { } + assign $0\all_rd_dly[0:0] \$11 + sync posedge \coresync_clk + update \all_rd_dly $0\all_rd_dly[0:0] + end + attribute \src "libresoc.v:33236.3-33237.39" + process $proc$libresoc.v:33236$1190 + assign { } { } + assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next + sync posedge \coresync_clk + update \alu_l_r_alu $0\alu_l_r_alu[0:0] + end + attribute \src "libresoc.v:33238.3-33239.43" + process $proc$libresoc.v:33238$1191 + assign { } { } + assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next + sync posedge \coresync_clk + update \alui_l_r_alui $0\alui_l_r_alui[0:0] + end + attribute \src "libresoc.v:33240.3-33241.29" + process $proc$libresoc.v:33240$1192 + assign { } { } + assign $0\src_r2[3:0] \src_r2$next + sync posedge \coresync_clk + update \src_r2 $0\src_r2[3:0] + end + attribute \src "libresoc.v:33242.3-33243.29" + process $proc$libresoc.v:33242$1193 + assign { } { } + assign $0\src_r1[63:0] \src_r1$next + sync posedge \coresync_clk + update \src_r1 $0\src_r1[63:0] + end + attribute \src "libresoc.v:33244.3-33245.29" + process $proc$libresoc.v:33244$1194 + assign { } { } + assign $0\src_r0[63:0] \src_r0$next + sync posedge \coresync_clk + update \src_r0 $0\src_r0[63:0] + end + attribute \src "libresoc.v:33246.3-33247.41" + process $proc$libresoc.v:33246$1195 + assign { } { } + assign $0\data_r2__nia[63:0] \data_r2__nia$next + sync posedge \coresync_clk + update \data_r2__nia $0\data_r2__nia[63:0] + end + attribute \src "libresoc.v:33248.3-33249.47" + process $proc$libresoc.v:33248$1196 + assign { } { } + assign $0\data_r2__nia_ok[0:0] \data_r2__nia_ok$next + sync posedge \coresync_clk + update \data_r2__nia_ok $0\data_r2__nia_ok[0:0] + end + attribute \src "libresoc.v:33250.3-33251.45" + process $proc$libresoc.v:33250$1197 + assign { } { } + assign $0\data_r1__fast2[63:0] \data_r1__fast2$next + sync posedge \coresync_clk + update \data_r1__fast2 $0\data_r1__fast2[63:0] + end + attribute \src "libresoc.v:33252.3-33253.51" + process $proc$libresoc.v:33252$1198 + assign { } { } + assign $0\data_r1__fast2_ok[0:0] \data_r1__fast2_ok$next + sync posedge \coresync_clk + update \data_r1__fast2_ok $0\data_r1__fast2_ok[0:0] + end + attribute \src "libresoc.v:33254.3-33255.45" + process $proc$libresoc.v:33254$1199 + assign { } { } + assign $0\data_r0__fast1[63:0] \data_r0__fast1$next + sync posedge \coresync_clk + update \data_r0__fast1 $0\data_r0__fast1[63:0] + end + attribute \src "libresoc.v:33256.3-33257.51" + process $proc$libresoc.v:33256$1200 + assign { } { } + assign $0\data_r0__fast1_ok[0:0] \data_r0__fast1_ok$next + sync posedge \coresync_clk + update \data_r0__fast1_ok $0\data_r0__fast1_ok[0:0] + end + attribute \src "libresoc.v:33258.3-33259.61" + process $proc$libresoc.v:33258$1201 + assign { } { } + assign $0\alu_branch0_br_op__cia[63:0] \alu_branch0_br_op__cia$next + sync posedge \coresync_clk + update \alu_branch0_br_op__cia $0\alu_branch0_br_op__cia[63:0] + end + attribute \src "libresoc.v:33260.3-33261.73" + process $proc$libresoc.v:33260$1202 + assign { } { } + assign $0\alu_branch0_br_op__insn_type[6:0] \alu_branch0_br_op__insn_type$next + sync posedge \coresync_clk + update \alu_branch0_br_op__insn_type $0\alu_branch0_br_op__insn_type[6:0] + end + attribute \src "libresoc.v:33262.3-33263.69" + process $proc$libresoc.v:33262$1203 + assign { } { } + assign $0\alu_branch0_br_op__fn_unit[11:0] \alu_branch0_br_op__fn_unit$next + sync posedge \coresync_clk + update \alu_branch0_br_op__fn_unit $0\alu_branch0_br_op__fn_unit[11:0] + end + attribute \src "libresoc.v:33264.3-33265.63" + process $proc$libresoc.v:33264$1204 + assign { } { } + assign $0\alu_branch0_br_op__insn[31:0] \alu_branch0_br_op__insn$next + sync posedge \coresync_clk + update \alu_branch0_br_op__insn $0\alu_branch0_br_op__insn[31:0] + end + attribute \src "libresoc.v:33266.3-33267.83" + process $proc$libresoc.v:33266$1205 + assign { } { } + assign $0\alu_branch0_br_op__imm_data__data[63:0] \alu_branch0_br_op__imm_data__data$next + sync posedge \coresync_clk + update \alu_branch0_br_op__imm_data__data $0\alu_branch0_br_op__imm_data__data[63:0] + end + attribute \src "libresoc.v:33268.3-33269.79" + process $proc$libresoc.v:33268$1206 + assign { } { } + assign $0\alu_branch0_br_op__imm_data__ok[0:0] \alu_branch0_br_op__imm_data__ok$next + sync posedge \coresync_clk + update \alu_branch0_br_op__imm_data__ok $0\alu_branch0_br_op__imm_data__ok[0:0] + end + attribute \src "libresoc.v:33270.3-33271.59" + process $proc$libresoc.v:33270$1207 + assign { } { } + assign $0\alu_branch0_br_op__lk[0:0] \alu_branch0_br_op__lk$next + sync posedge \coresync_clk + update \alu_branch0_br_op__lk $0\alu_branch0_br_op__lk[0:0] + end + attribute \src "libresoc.v:33272.3-33273.71" + process $proc$libresoc.v:33272$1208 + assign { } { } + assign $0\alu_branch0_br_op__is_32bit[0:0] \alu_branch0_br_op__is_32bit$next + sync posedge \coresync_clk + update \alu_branch0_br_op__is_32bit $0\alu_branch0_br_op__is_32bit[0:0] + end + attribute \src "libresoc.v:33274.3-33275.39" + process $proc$libresoc.v:33274$1209 + assign { } { } + assign $0\req_l_r_req[2:0] \req_l_r_req$next + sync posedge \coresync_clk + update \req_l_r_req $0\req_l_r_req[2:0] + end + attribute \src "libresoc.v:33276.3-33277.39" + process $proc$libresoc.v:33276$1210 + assign { } { } + assign $0\req_l_s_req[2:0] \req_l_s_req$next + sync posedge \coresync_clk + update \req_l_s_req $0\req_l_s_req[2:0] + end + attribute \src "libresoc.v:33278.3-33279.39" + process $proc$libresoc.v:33278$1211 + assign { } { } + assign $0\src_l_r_src[2:0] \src_l_r_src$next + sync posedge \coresync_clk + update \src_l_r_src $0\src_l_r_src[2:0] + end + attribute \src "libresoc.v:33280.3-33281.39" + process $proc$libresoc.v:33280$1212 + assign { } { } + assign $0\src_l_s_src[2:0] \src_l_s_src$next + sync posedge \coresync_clk + update \src_l_s_src $0\src_l_s_src[2:0] + end + attribute \src "libresoc.v:33282.3-33283.39" + process $proc$libresoc.v:33282$1213 + assign { } { } + assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next + sync posedge \coresync_clk + update \opc_l_r_opc $0\opc_l_r_opc[0:0] + end + attribute \src "libresoc.v:33284.3-33285.39" + process $proc$libresoc.v:33284$1214 + assign { } { } + assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next + sync posedge \coresync_clk + update \opc_l_s_opc $0\opc_l_s_opc[0:0] + end + attribute \src "libresoc.v:33359.3-33368.6" + process $proc$libresoc.v:33359$1215 + assign { } { } + assign { } { } + assign $0\req_done[0:0] $1\req_done[0:0] + attribute \src "libresoc.v:33360.5-33360.29" + switch \initial + attribute \src "libresoc.v:33360.9-33360.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + switch \$55 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\req_done[0:0] 1'1 + case + assign $1\req_done[0:0] \$47 + end + sync always + update \req_done $0\req_done[0:0] + end + attribute \src "libresoc.v:33369.3-33377.6" + process $proc$libresoc.v:33369$1216 + assign { } { } + assign { } { } + assign $0\rok_l_s_rdok$next[0:0]$1217 $1\rok_l_s_rdok$next[0:0]$1218 + attribute \src "libresoc.v:33370.5-33370.29" + switch \initial + attribute \src "libresoc.v:33370.9-33370.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rok_l_s_rdok$next[0:0]$1218 1'0 + case + assign $1\rok_l_s_rdok$next[0:0]$1218 \cu_issue_i + end + sync always + update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$1217 + end + attribute \src "libresoc.v:33378.3-33386.6" + process $proc$libresoc.v:33378$1219 + assign { } { } + assign { } { } + assign $0\rok_l_r_rdok$next[0:0]$1220 $1\rok_l_r_rdok$next[0:0]$1221 + attribute \src "libresoc.v:33379.5-33379.29" + switch \initial + attribute \src "libresoc.v:33379.9-33379.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rok_l_r_rdok$next[0:0]$1221 1'1 + case + assign $1\rok_l_r_rdok$next[0:0]$1221 \$65 + end + sync always + update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$1220 + end + attribute \src "libresoc.v:33387.3-33395.6" + process $proc$libresoc.v:33387$1222 + assign { } { } + assign { } { } + assign $0\rst_l_s_rst$next[0:0]$1223 $1\rst_l_s_rst$next[0:0]$1224 + attribute \src "libresoc.v:33388.5-33388.29" + switch \initial + attribute \src "libresoc.v:33388.9-33388.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rst_l_s_rst$next[0:0]$1224 1'0 + case + assign $1\rst_l_s_rst$next[0:0]$1224 \all_rd + end + sync always + update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$1223 + end + attribute \src "libresoc.v:33396.3-33404.6" + process $proc$libresoc.v:33396$1225 + assign { } { } + assign { } { } + assign $0\rst_l_r_rst$next[0:0]$1226 $1\rst_l_r_rst$next[0:0]$1227 + attribute \src "libresoc.v:33397.5-33397.29" + switch \initial + attribute \src "libresoc.v:33397.9-33397.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rst_l_r_rst$next[0:0]$1227 1'1 + case + assign $1\rst_l_r_rst$next[0:0]$1227 \rst_r + end + sync always + update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$1226 + end + attribute \src "libresoc.v:33405.3-33413.6" + process $proc$libresoc.v:33405$1228 + assign { } { } + assign { } { } + assign $0\opc_l_s_opc$next[0:0]$1229 $1\opc_l_s_opc$next[0:0]$1230 + attribute \src "libresoc.v:33406.5-33406.29" + switch \initial + attribute \src "libresoc.v:33406.9-33406.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\opc_l_s_opc$next[0:0]$1230 1'0 + case + assign $1\opc_l_s_opc$next[0:0]$1230 \cu_issue_i + end + sync always + update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$1229 + end + attribute \src "libresoc.v:33414.3-33422.6" + process $proc$libresoc.v:33414$1231 + assign { } { } + assign { } { } + assign $0\opc_l_r_opc$next[0:0]$1232 $1\opc_l_r_opc$next[0:0]$1233 + attribute \src "libresoc.v:33415.5-33415.29" + switch \initial + attribute \src "libresoc.v:33415.9-33415.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\opc_l_r_opc$next[0:0]$1233 1'1 + case + assign $1\opc_l_r_opc$next[0:0]$1233 \req_done + end + sync always + update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$1232 + end + attribute \src "libresoc.v:33423.3-33431.6" + process $proc$libresoc.v:33423$1234 + assign { } { } + assign { } { } + assign $0\src_l_s_src$next[2:0]$1235 $1\src_l_s_src$next[2:0]$1236 + attribute \src "libresoc.v:33424.5-33424.29" + switch \initial + attribute \src "libresoc.v:33424.9-33424.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_l_s_src$next[2:0]$1236 3'000 + case + assign $1\src_l_s_src$next[2:0]$1236 { \cu_issue_i \cu_issue_i \cu_issue_i } + end + sync always + update \src_l_s_src$next $0\src_l_s_src$next[2:0]$1235 + end + attribute \src "libresoc.v:33432.3-33440.6" + process $proc$libresoc.v:33432$1237 + assign { } { } + assign { } { } + assign $0\src_l_r_src$next[2:0]$1238 $1\src_l_r_src$next[2:0]$1239 + attribute \src "libresoc.v:33433.5-33433.29" + switch \initial + attribute \src "libresoc.v:33433.9-33433.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_l_r_src$next[2:0]$1239 3'111 + case + assign $1\src_l_r_src$next[2:0]$1239 \reset_r + end + sync always + update \src_l_r_src$next $0\src_l_r_src$next[2:0]$1238 + end + attribute \src "libresoc.v:33441.3-33449.6" + process $proc$libresoc.v:33441$1240 + assign { } { } + assign { } { } + assign $0\req_l_s_req$next[2:0]$1241 $1\req_l_s_req$next[2:0]$1242 + attribute \src "libresoc.v:33442.5-33442.29" + switch \initial + attribute \src "libresoc.v:33442.9-33442.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\req_l_s_req$next[2:0]$1242 3'000 + case + assign $1\req_l_s_req$next[2:0]$1242 \$67 + end + sync always + update \req_l_s_req$next $0\req_l_s_req$next[2:0]$1241 + end + attribute \src "libresoc.v:33450.3-33458.6" + process $proc$libresoc.v:33450$1243 + assign { } { } + assign { } { } + assign $0\req_l_r_req$next[2:0]$1244 $1\req_l_r_req$next[2:0]$1245 + attribute \src "libresoc.v:33451.5-33451.29" + switch \initial + attribute \src "libresoc.v:33451.9-33451.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\req_l_r_req$next[2:0]$1245 3'111 + case + assign $1\req_l_r_req$next[2:0]$1245 \$69 + end + sync always + update \req_l_r_req$next $0\req_l_r_req$next[2:0]$1244 + end + attribute \src "libresoc.v:33459.3-33483.6" + process $proc$libresoc.v:33459$1246 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\alu_branch0_br_op__cia$next[63:0]$1247 $1\alu_branch0_br_op__cia$next[63:0]$1255 + assign $0\alu_branch0_br_op__fn_unit$next[11:0]$1248 $1\alu_branch0_br_op__fn_unit$next[11:0]$1256 + assign { } { } + assign { } { } + assign $0\alu_branch0_br_op__insn$next[31:0]$1251 $1\alu_branch0_br_op__insn$next[31:0]$1259 + assign $0\alu_branch0_br_op__insn_type$next[6:0]$1252 $1\alu_branch0_br_op__insn_type$next[6:0]$1260 + assign $0\alu_branch0_br_op__is_32bit$next[0:0]$1253 $1\alu_branch0_br_op__is_32bit$next[0:0]$1261 + assign $0\alu_branch0_br_op__lk$next[0:0]$1254 $1\alu_branch0_br_op__lk$next[0:0]$1262 + assign $0\alu_branch0_br_op__imm_data__data$next[63:0]$1249 $2\alu_branch0_br_op__imm_data__data$next[63:0]$1263 + assign $0\alu_branch0_br_op__imm_data__ok$next[0:0]$1250 $2\alu_branch0_br_op__imm_data__ok$next[0:0]$1264 + attribute \src "libresoc.v:33460.5-33460.29" + switch \initial + attribute \src "libresoc.v:33460.9-33460.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\alu_branch0_br_op__is_32bit$next[0:0]$1261 $1\alu_branch0_br_op__lk$next[0:0]$1262 $1\alu_branch0_br_op__imm_data__ok$next[0:0]$1258 $1\alu_branch0_br_op__imm_data__data$next[63:0]$1257 $1\alu_branch0_br_op__insn$next[31:0]$1259 $1\alu_branch0_br_op__fn_unit$next[11:0]$1256 $1\alu_branch0_br_op__insn_type$next[6:0]$1260 $1\alu_branch0_br_op__cia$next[63:0]$1255 } { \oper_i_alu_branch0__is_32bit \oper_i_alu_branch0__lk \oper_i_alu_branch0__imm_data__ok \oper_i_alu_branch0__imm_data__data \oper_i_alu_branch0__insn \oper_i_alu_branch0__fn_unit \oper_i_alu_branch0__insn_type \oper_i_alu_branch0__cia } + case + assign $1\alu_branch0_br_op__cia$next[63:0]$1255 \alu_branch0_br_op__cia + assign $1\alu_branch0_br_op__fn_unit$next[11:0]$1256 \alu_branch0_br_op__fn_unit + assign $1\alu_branch0_br_op__imm_data__data$next[63:0]$1257 \alu_branch0_br_op__imm_data__data + assign $1\alu_branch0_br_op__imm_data__ok$next[0:0]$1258 \alu_branch0_br_op__imm_data__ok + assign $1\alu_branch0_br_op__insn$next[31:0]$1259 \alu_branch0_br_op__insn + assign $1\alu_branch0_br_op__insn_type$next[6:0]$1260 \alu_branch0_br_op__insn_type + assign $1\alu_branch0_br_op__is_32bit$next[0:0]$1261 \alu_branch0_br_op__is_32bit + assign $1\alu_branch0_br_op__lk$next[0:0]$1262 \alu_branch0_br_op__lk + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $2\alu_branch0_br_op__imm_data__data$next[63:0]$1263 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\alu_branch0_br_op__imm_data__ok$next[0:0]$1264 1'0 + case + assign $2\alu_branch0_br_op__imm_data__data$next[63:0]$1263 $1\alu_branch0_br_op__imm_data__data$next[63:0]$1257 + assign $2\alu_branch0_br_op__imm_data__ok$next[0:0]$1264 $1\alu_branch0_br_op__imm_data__ok$next[0:0]$1258 + end + sync always + update \alu_branch0_br_op__cia$next $0\alu_branch0_br_op__cia$next[63:0]$1247 + update \alu_branch0_br_op__fn_unit$next $0\alu_branch0_br_op__fn_unit$next[11:0]$1248 + update \alu_branch0_br_op__imm_data__data$next $0\alu_branch0_br_op__imm_data__data$next[63:0]$1249 + update \alu_branch0_br_op__imm_data__ok$next $0\alu_branch0_br_op__imm_data__ok$next[0:0]$1250 + update \alu_branch0_br_op__insn$next $0\alu_branch0_br_op__insn$next[31:0]$1251 + update \alu_branch0_br_op__insn_type$next $0\alu_branch0_br_op__insn_type$next[6:0]$1252 + update \alu_branch0_br_op__is_32bit$next $0\alu_branch0_br_op__is_32bit$next[0:0]$1253 + update \alu_branch0_br_op__lk$next $0\alu_branch0_br_op__lk$next[0:0]$1254 + end + attribute \src "libresoc.v:33484.3-33505.6" + process $proc$libresoc.v:33484$1265 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r0__fast1$next[63:0]$1266 $2\data_r0__fast1$next[63:0]$1270 + assign { } { } + assign $0\data_r0__fast1_ok$next[0:0]$1267 $3\data_r0__fast1_ok$next[0:0]$1272 + attribute \src "libresoc.v:33485.5-33485.29" + switch \initial + attribute \src "libresoc.v:33485.9-33485.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r0__fast1_ok$next[0:0]$1269 $1\data_r0__fast1$next[63:0]$1268 } { \fast1_ok \alu_branch0_fast1 } + case + assign $1\data_r0__fast1$next[63:0]$1268 \data_r0__fast1 + assign $1\data_r0__fast1_ok$next[0:0]$1269 \data_r0__fast1_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r0__fast1_ok$next[0:0]$1271 $2\data_r0__fast1$next[63:0]$1270 } 65'00000000000000000000000000000000000000000000000000000000000000000 + case + assign $2\data_r0__fast1$next[63:0]$1270 $1\data_r0__fast1$next[63:0]$1268 + assign $2\data_r0__fast1_ok$next[0:0]$1271 $1\data_r0__fast1_ok$next[0:0]$1269 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r0__fast1_ok$next[0:0]$1272 1'0 + case + assign $3\data_r0__fast1_ok$next[0:0]$1272 $2\data_r0__fast1_ok$next[0:0]$1271 + end + sync always + update \data_r0__fast1$next $0\data_r0__fast1$next[63:0]$1266 + update \data_r0__fast1_ok$next $0\data_r0__fast1_ok$next[0:0]$1267 + end + attribute \src "libresoc.v:33506.3-33527.6" + process $proc$libresoc.v:33506$1273 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r1__fast2$next[63:0]$1274 $2\data_r1__fast2$next[63:0]$1278 + assign { } { } + assign $0\data_r1__fast2_ok$next[0:0]$1275 $3\data_r1__fast2_ok$next[0:0]$1280 + attribute \src "libresoc.v:33507.5-33507.29" + switch \initial + attribute \src "libresoc.v:33507.9-33507.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r1__fast2_ok$next[0:0]$1277 $1\data_r1__fast2$next[63:0]$1276 } { \fast2_ok \alu_branch0_fast2 } + case + assign $1\data_r1__fast2$next[63:0]$1276 \data_r1__fast2 + assign $1\data_r1__fast2_ok$next[0:0]$1277 \data_r1__fast2_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r1__fast2_ok$next[0:0]$1279 $2\data_r1__fast2$next[63:0]$1278 } 65'00000000000000000000000000000000000000000000000000000000000000000 + case + assign $2\data_r1__fast2$next[63:0]$1278 $1\data_r1__fast2$next[63:0]$1276 + assign $2\data_r1__fast2_ok$next[0:0]$1279 $1\data_r1__fast2_ok$next[0:0]$1277 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r1__fast2_ok$next[0:0]$1280 1'0 + case + assign $3\data_r1__fast2_ok$next[0:0]$1280 $2\data_r1__fast2_ok$next[0:0]$1279 + end + sync always + update \data_r1__fast2$next $0\data_r1__fast2$next[63:0]$1274 + update \data_r1__fast2_ok$next $0\data_r1__fast2_ok$next[0:0]$1275 + end + attribute \src "libresoc.v:33528.3-33549.6" + process $proc$libresoc.v:33528$1281 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r2__nia$next[63:0]$1282 $2\data_r2__nia$next[63:0]$1286 + assign { } { } + assign $0\data_r2__nia_ok$next[0:0]$1283 $3\data_r2__nia_ok$next[0:0]$1288 + attribute \src "libresoc.v:33529.5-33529.29" + switch \initial + attribute \src "libresoc.v:33529.9-33529.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r2__nia_ok$next[0:0]$1285 $1\data_r2__nia$next[63:0]$1284 } { \nia_ok \alu_branch0_nia } + case + assign $1\data_r2__nia$next[63:0]$1284 \data_r2__nia + assign $1\data_r2__nia_ok$next[0:0]$1285 \data_r2__nia_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r2__nia_ok$next[0:0]$1287 $2\data_r2__nia$next[63:0]$1286 } 65'00000000000000000000000000000000000000000000000000000000000000000 + case + assign $2\data_r2__nia$next[63:0]$1286 $1\data_r2__nia$next[63:0]$1284 + assign $2\data_r2__nia_ok$next[0:0]$1287 $1\data_r2__nia_ok$next[0:0]$1285 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r2__nia_ok$next[0:0]$1288 1'0 + case + assign $3\data_r2__nia_ok$next[0:0]$1288 $2\data_r2__nia_ok$next[0:0]$1287 + end + sync always + update \data_r2__nia$next $0\data_r2__nia$next[63:0]$1282 + update \data_r2__nia_ok$next $0\data_r2__nia_ok$next[0:0]$1283 + end + attribute \src "libresoc.v:33550.3-33559.6" + process $proc$libresoc.v:33550$1289 + assign { } { } + assign { } { } + assign $0\src_r0$next[63:0]$1290 $1\src_r0$next[63:0]$1291 + attribute \src "libresoc.v:33551.5-33551.29" + switch \initial + attribute \src "libresoc.v:33551.9-33551.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch \src_l_q_src [0] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r0$next[63:0]$1291 \src1_i + case + assign $1\src_r0$next[63:0]$1291 \src_r0 + end + sync always + update \src_r0$next $0\src_r0$next[63:0]$1290 + end + attribute \src "libresoc.v:33560.3-33569.6" + process $proc$libresoc.v:33560$1292 + assign { } { } + assign { } { } + assign $0\src_r1$next[63:0]$1293 $1\src_r1$next[63:0]$1294 + attribute \src "libresoc.v:33561.5-33561.29" + switch \initial + attribute \src "libresoc.v:33561.9-33561.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch \src_sel + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r1$next[63:0]$1294 \src_or_imm + case + assign $1\src_r1$next[63:0]$1294 \src_r1 + end + sync always + update \src_r1$next $0\src_r1$next[63:0]$1293 + end + attribute \src "libresoc.v:33570.3-33579.6" + process $proc$libresoc.v:33570$1295 + assign { } { } + assign { } { } + assign $0\src_r2$next[3:0]$1296 $1\src_r2$next[3:0]$1297 + attribute \src "libresoc.v:33571.5-33571.29" + switch \initial + attribute \src "libresoc.v:33571.9-33571.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch \src_l_q_src [2] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r2$next[3:0]$1297 \src3_i + case + assign $1\src_r2$next[3:0]$1297 \src_r2 + end + sync always + update \src_r2$next $0\src_r2$next[3:0]$1296 + end + attribute \src "libresoc.v:33580.3-33588.6" + process $proc$libresoc.v:33580$1298 + assign { } { } + assign { } { } + assign $0\alui_l_r_alui$next[0:0]$1299 $1\alui_l_r_alui$next[0:0]$1300 + attribute \src "libresoc.v:33581.5-33581.29" + switch \initial + attribute \src "libresoc.v:33581.9-33581.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\alui_l_r_alui$next[0:0]$1300 1'1 + case + assign $1\alui_l_r_alui$next[0:0]$1300 \$87 + end + sync always + update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$1299 + end + attribute \src "libresoc.v:33589.3-33597.6" + process $proc$libresoc.v:33589$1301 + assign { } { } + assign { } { } + assign $0\alu_l_r_alu$next[0:0]$1302 $1\alu_l_r_alu$next[0:0]$1303 + attribute \src "libresoc.v:33590.5-33590.29" + switch \initial + attribute \src "libresoc.v:33590.9-33590.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\alu_l_r_alu$next[0:0]$1303 1'1 + case + assign $1\alu_l_r_alu$next[0:0]$1303 \$89 + end + sync always + update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$1302 + end + attribute \src "libresoc.v:33598.3-33607.6" + process $proc$libresoc.v:33598$1304 + assign { } { } + assign { } { } + assign $0\dest1_o[63:0] $1\dest1_o[63:0] + attribute \src "libresoc.v:33599.5-33599.29" + switch \initial + attribute \src "libresoc.v:33599.9-33599.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$111 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest1_o[63:0] \data_r0__fast1 + case + assign $1\dest1_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \dest1_o $0\dest1_o[63:0] + end + attribute \src "libresoc.v:33608.3-33617.6" + process $proc$libresoc.v:33608$1305 + assign { } { } + assign { } { } + assign $0\dest2_o[63:0] $1\dest2_o[63:0] + attribute \src "libresoc.v:33609.5-33609.29" + switch \initial + attribute \src "libresoc.v:33609.9-33609.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$113 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest2_o[63:0] \data_r1__fast2 + case + assign $1\dest2_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \dest2_o $0\dest2_o[63:0] + end + attribute \src "libresoc.v:33618.3-33627.6" + process $proc$libresoc.v:33618$1306 + assign { } { } + assign { } { } + assign $0\dest3_o[63:0] $1\dest3_o[63:0] + attribute \src "libresoc.v:33619.5-33619.29" + switch \initial + attribute \src "libresoc.v:33619.9-33619.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$115 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest3_o[63:0] \data_r2__nia + case + assign $1\dest3_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \dest3_o $0\dest3_o[63:0] + end + attribute \src "libresoc.v:33628.3-33636.6" + process $proc$libresoc.v:33628$1307 + assign { } { } + assign { } { } + assign $0\prev_wr_go$next[2:0]$1308 $1\prev_wr_go$next[2:0]$1309 + attribute \src "libresoc.v:33629.5-33629.29" + switch \initial + attribute \src "libresoc.v:33629.9-33629.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\prev_wr_go$next[2:0]$1309 3'000 + case + assign $1\prev_wr_go$next[2:0]$1309 \$21 + end + sync always + update \prev_wr_go$next $0\prev_wr_go$next[2:0]$1308 + end + connect \$5 $reduce_and$libresoc.v:33165$1126_Y + connect \$99 $and$libresoc.v:33166$1127_Y + connect \$101 $and$libresoc.v:33167$1128_Y + connect \$103 $and$libresoc.v:33168$1129_Y + connect \$105 $and$libresoc.v:33169$1130_Y + connect \$107 $and$libresoc.v:33170$1131_Y + connect \$109 $and$libresoc.v:33171$1132_Y + connect \$111 $and$libresoc.v:33172$1133_Y + connect \$113 $and$libresoc.v:33173$1134_Y + connect \$115 $and$libresoc.v:33174$1135_Y + connect \$11 $and$libresoc.v:33175$1136_Y + connect \$13 $not$libresoc.v:33176$1137_Y + connect \$15 $and$libresoc.v:33177$1138_Y + connect \$17 $not$libresoc.v:33178$1139_Y + connect \$19 $and$libresoc.v:33179$1140_Y + connect \$21 $and$libresoc.v:33180$1141_Y + connect \$25 $not$libresoc.v:33181$1142_Y + connect \$27 $and$libresoc.v:33182$1143_Y + connect \$24 $reduce_or$libresoc.v:33183$1144_Y + connect \$23 $not$libresoc.v:33184$1145_Y + connect \$31 $and$libresoc.v:33185$1146_Y + connect \$33 $reduce_or$libresoc.v:33186$1147_Y + connect \$35 $reduce_or$libresoc.v:33187$1148_Y + connect \$37 $or$libresoc.v:33188$1149_Y + connect \$3 $and$libresoc.v:33189$1150_Y + connect \$39 $not$libresoc.v:33190$1151_Y + connect \$41 $and$libresoc.v:33191$1152_Y + connect \$43 $and$libresoc.v:33192$1153_Y + connect \$45 $eq$libresoc.v:33193$1154_Y + connect \$47 $and$libresoc.v:33194$1155_Y + connect \$49 $eq$libresoc.v:33195$1156_Y + connect \$51 $and$libresoc.v:33196$1157_Y + connect \$53 $and$libresoc.v:33197$1158_Y + connect \$55 $and$libresoc.v:33198$1159_Y + connect \$57 $or$libresoc.v:33199$1160_Y + connect \$59 $or$libresoc.v:33200$1161_Y + connect \$61 $or$libresoc.v:33201$1162_Y + connect \$63 $or$libresoc.v:33202$1163_Y + connect \$65 $and$libresoc.v:33203$1164_Y + connect \$67 $and$libresoc.v:33204$1165_Y + connect \$6 $not$libresoc.v:33205$1166_Y + connect \$69 $or$libresoc.v:33206$1167_Y + connect \$71 $and$libresoc.v:33207$1168_Y + connect \$73 $and$libresoc.v:33208$1169_Y + connect \$75 $and$libresoc.v:33209$1170_Y + connect \$77 $ternary$libresoc.v:33210$1171_Y + connect \$79 $ternary$libresoc.v:33211$1172_Y + connect \$81 $ternary$libresoc.v:33212$1173_Y + connect \$83 $ternary$libresoc.v:33213$1174_Y + connect \$85 $ternary$libresoc.v:33214$1175_Y + connect \$87 $and$libresoc.v:33215$1176_Y + connect \$8 $or$libresoc.v:33216$1177_Y + connect \$89 $and$libresoc.v:33217$1178_Y + connect \$91 $and$libresoc.v:33218$1179_Y + connect \$93 $not$libresoc.v:33219$1180_Y + connect \$95 $and$libresoc.v:33220$1181_Y + connect \$97 $not$libresoc.v:33221$1182_Y + connect \cu_go_die_i 1'0 + connect \cu_shadown_i 1'1 + connect \cu_wr__rel_o \$109 + connect \cu_rd__rel_o \$99 + connect \cu_busy_o \opc_l_q_opc + connect \alu_l_s_alu \all_rd_pulse + connect \alu_branch0_n_ready_i \alu_l_q_alu + connect \alui_l_s_alui \all_rd_pulse + connect \alu_branch0_p_valid_i \alui_l_q_alui + connect \alu_branch0_cr_a \$85 + connect \alu_branch0_fast2$2 \$83 + connect \alu_branch0_fast1$1 \$81 + connect \src_or_imm \$79 + connect \src_sel \$77 + connect \cu_wrmask_o { \$75 \$73 \$71 } + connect \reset_r \$63 + connect \reset_w \$61 + connect \rst_r \$59 + connect \reset \$57 + connect \wr_any \$37 + connect \cu_done_o \$31 + connect \alu_pulsem { \alu_pulse \alu_pulse \alu_pulse } + connect \alu_pulse \alu_done_rise + connect \alu_done_rise \$19 + connect \alu_done_dly$next \alu_done + connect \alu_done \alu_branch0_n_valid_o + connect \all_rd_pulse \all_rd_rise + connect \all_rd_rise \$15 + connect \all_rd_dly$next \all_rd + connect \all_rd \$11 +end +attribute \src "libresoc.v:33671.1-33729.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.l0.pimem.busy_l" +attribute \generator "nMigen" +module \busy_l + attribute \src "libresoc.v:33672.7-33672.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:33717.3-33725.6" + wire $0\q_int$next[0:0]$1353 + attribute \src "libresoc.v:33715.3-33716.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:33717.3-33725.6" + wire $1\q_int$next[0:0]$1354 + attribute \src "libresoc.v:33696.7-33696.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:33707.17-33707.96" + wire $and$libresoc.v:33707$1343_Y + attribute \src "libresoc.v:33712.17-33712.96" + wire $and$libresoc.v:33712$1348_Y + attribute \src "libresoc.v:33709.18-33709.94" + wire $not$libresoc.v:33709$1345_Y + attribute \src "libresoc.v:33711.17-33711.93" + wire $not$libresoc.v:33711$1347_Y + attribute \src "libresoc.v:33714.17-33714.93" + wire $not$libresoc.v:33714$1350_Y + attribute \src "libresoc.v:33708.18-33708.99" + wire $or$libresoc.v:33708$1344_Y + attribute \src "libresoc.v:33710.18-33710.100" + wire $or$libresoc.v:33710$1346_Y + attribute \src "libresoc.v:33713.17-33713.98" + wire $or$libresoc.v:33713$1349_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 1 \coresync_rst + attribute \src "libresoc.v:33672.7-33672.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 4 \q_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 2 \s_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$libresoc.v:33707$1343 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:33707$1343_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:33712$1348 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:33712$1348_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:33709$1345 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_busy + connect \Y $not$libresoc.v:33709$1345_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:33711$1347 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_busy + connect \Y $not$libresoc.v:33711$1347_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:33714$1350 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_busy + connect \Y $not$libresoc.v:33714$1350_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:33708$1344 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_busy + connect \Y $or$libresoc.v:33708$1344_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:33710$1346 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_busy + connect \B \q_int + connect \Y $or$libresoc.v:33710$1346_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:33713$1349 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_busy + connect \Y $or$libresoc.v:33713$1349_Y + end + attribute \src "libresoc.v:33672.7-33672.20" + process $proc$libresoc.v:33672$1355 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:33696.7-33696.19" + process $proc$libresoc.v:33696$1356 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:33715.3-33716.27" + process $proc$libresoc.v:33715$1351 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:33717.3-33725.6" + process $proc$libresoc.v:33717$1352 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$1353 $1\q_int$next[0:0]$1354 + attribute \src "libresoc.v:33718.5-33718.29" + switch \initial + attribute \src "libresoc.v:33718.9-33718.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$1354 1'0 + case + assign $1\q_int$next[0:0]$1354 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$1353 + end + connect \$9 $and$libresoc.v:33707$1343_Y + connect \$11 $or$libresoc.v:33708$1344_Y + connect \$13 $not$libresoc.v:33709$1345_Y + connect \$15 $or$libresoc.v:33710$1346_Y + connect \$1 $not$libresoc.v:33711$1347_Y + connect \$3 $and$libresoc.v:33712$1348_Y + connect \$5 $or$libresoc.v:33713$1349_Y + connect \$7 $not$libresoc.v:33714$1350_Y + connect \qlq_busy \$15 + connect \qn_busy \$13 + connect \q_busy \$11 +end +attribute \src "libresoc.v:33733.1-35341.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_logical0.logical_pipe1.main.clz" +attribute \generator "nMigen" +module \clz + attribute \src "libresoc.v:34208.3-34222.6" + wire width 2 $0\cnt_1_0[1:0] + attribute \src "libresoc.v:34298.3-34312.6" + wire width 2 $0\cnt_1_10[1:0] + attribute \src "libresoc.v:34313.3-34327.6" + wire width 2 $0\cnt_1_11[1:0] + attribute \src "libresoc.v:34328.3-34342.6" + wire width 2 $0\cnt_1_12[1:0] + attribute \src "libresoc.v:34343.3-34357.6" + wire width 2 $0\cnt_1_13[1:0] + attribute \src "libresoc.v:34358.3-34372.6" + wire width 2 $0\cnt_1_14[1:0] + attribute \src "libresoc.v:34388.3-34402.6" + wire width 2 $0\cnt_1_15[1:0] + attribute \src "libresoc.v:34403.3-34417.6" + wire width 2 $0\cnt_1_16[1:0] + attribute \src "libresoc.v:34418.3-34432.6" + wire width 2 $0\cnt_1_17[1:0] + attribute \src "libresoc.v:34433.3-34447.6" + wire width 2 $0\cnt_1_18[1:0] + attribute \src "libresoc.v:34448.3-34462.6" + wire width 2 $0\cnt_1_19[1:0] + attribute \src "libresoc.v:34373.3-34387.6" + wire width 2 $0\cnt_1_1[1:0] + attribute \src "libresoc.v:34463.3-34477.6" + wire width 2 $0\cnt_1_20[1:0] + attribute \src "libresoc.v:34478.3-34492.6" + wire width 2 $0\cnt_1_21[1:0] + attribute \src "libresoc.v:34493.3-34507.6" + wire width 2 $0\cnt_1_22[1:0] + attribute \src "libresoc.v:34508.3-34522.6" + wire width 2 $0\cnt_1_23[1:0] + attribute \src "libresoc.v:34523.3-34537.6" + wire width 2 $0\cnt_1_24[1:0] + attribute \src "libresoc.v:34553.3-34567.6" + wire width 2 $0\cnt_1_25[1:0] + attribute \src "libresoc.v:34568.3-34582.6" + wire width 2 $0\cnt_1_26[1:0] + attribute \src "libresoc.v:34583.3-34597.6" + wire width 2 $0\cnt_1_27[1:0] + attribute \src "libresoc.v:34598.3-34612.6" + wire width 2 $0\cnt_1_28[1:0] + attribute \src "libresoc.v:34613.3-34627.6" + wire width 2 $0\cnt_1_29[1:0] + attribute \src "libresoc.v:34538.3-34552.6" + wire width 2 $0\cnt_1_2[1:0] + attribute \src "libresoc.v:34628.3-34642.6" + wire width 2 $0\cnt_1_30[1:0] + attribute \src "libresoc.v:34643.3-34657.6" + wire width 2 $0\cnt_1_31[1:0] + attribute \src "libresoc.v:34778.3-34792.6" + wire width 2 $0\cnt_1_3[1:0] + attribute \src "libresoc.v:35193.3-35207.6" + wire width 2 $0\cnt_1_4[1:0] + attribute \src "libresoc.v:34223.3-34237.6" + wire width 2 $0\cnt_1_5[1:0] + attribute \src "libresoc.v:34238.3-34252.6" + wire width 2 $0\cnt_1_6[1:0] + attribute \src "libresoc.v:34253.3-34267.6" + wire width 2 $0\cnt_1_7[1:0] + attribute \src "libresoc.v:34268.3-34282.6" + wire width 2 $0\cnt_1_8[1:0] + attribute \src "libresoc.v:34283.3-34297.6" + wire width 2 $0\cnt_1_9[1:0] + attribute \src "libresoc.v:34658.3-34677.6" + wire width 3 $0\cnt_2_0[2:0] + attribute \src "libresoc.v:34758.3-34777.6" + wire width 3 $0\cnt_2_10[2:0] + attribute \src "libresoc.v:34793.3-34812.6" + wire width 3 $0\cnt_2_12[2:0] + attribute \src "libresoc.v:34813.3-34832.6" + wire width 3 $0\cnt_2_14[2:0] + attribute \src "libresoc.v:34833.3-34852.6" + wire width 3 $0\cnt_2_16[2:0] + attribute \src "libresoc.v:34853.3-34872.6" + wire width 3 $0\cnt_2_18[2:0] + attribute \src "libresoc.v:34873.3-34892.6" + wire width 3 $0\cnt_2_20[2:0] + attribute \src "libresoc.v:34893.3-34912.6" + wire width 3 $0\cnt_2_22[2:0] + attribute \src "libresoc.v:34913.3-34932.6" + wire width 3 $0\cnt_2_24[2:0] + attribute \src "libresoc.v:34933.3-34952.6" + wire width 3 $0\cnt_2_26[2:0] + attribute \src "libresoc.v:34953.3-34972.6" + wire width 3 $0\cnt_2_28[2:0] + attribute \src "libresoc.v:34678.3-34697.6" + wire width 3 $0\cnt_2_2[2:0] + attribute \src "libresoc.v:34973.3-34992.6" + wire width 3 $0\cnt_2_30[2:0] + attribute \src "libresoc.v:34698.3-34717.6" + wire width 3 $0\cnt_2_4[2:0] + attribute \src "libresoc.v:34718.3-34737.6" + wire width 3 $0\cnt_2_6[2:0] + attribute \src "libresoc.v:34738.3-34757.6" + wire width 3 $0\cnt_2_8[2:0] + attribute \src "libresoc.v:34993.3-35012.6" + wire width 4 $0\cnt_3_0[3:0] + attribute \src "libresoc.v:35093.3-35112.6" + wire width 4 $0\cnt_3_10[3:0] + attribute \src "libresoc.v:35113.3-35132.6" + wire width 4 $0\cnt_3_12[3:0] + attribute \src "libresoc.v:35133.3-35152.6" + wire width 4 $0\cnt_3_14[3:0] + attribute \src "libresoc.v:35013.3-35032.6" + wire width 4 $0\cnt_3_2[3:0] + attribute \src "libresoc.v:35033.3-35052.6" + wire width 4 $0\cnt_3_4[3:0] + attribute \src "libresoc.v:35053.3-35072.6" + wire width 4 $0\cnt_3_6[3:0] + attribute \src "libresoc.v:35073.3-35092.6" + wire width 4 $0\cnt_3_8[3:0] + attribute \src "libresoc.v:35153.3-35172.6" + wire width 5 $0\cnt_4_0[4:0] + attribute \src "libresoc.v:35173.3-35192.6" + wire width 5 $0\cnt_4_2[4:0] + attribute \src "libresoc.v:35208.3-35227.6" + wire width 5 $0\cnt_4_4[4:0] + attribute \src "libresoc.v:35228.3-35247.6" + wire width 5 $0\cnt_4_6[4:0] + attribute \src "libresoc.v:35248.3-35267.6" + wire width 6 $0\cnt_5_0[5:0] + attribute \src "libresoc.v:35268.3-35287.6" + wire width 6 $0\cnt_5_2[5:0] + attribute \src "libresoc.v:35288.3-35307.6" + wire width 7 $0\cnt_6_0[6:0] + attribute \src "libresoc.v:33734.7-33734.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:34208.3-34222.6" + wire width 2 $1\cnt_1_0[1:0] + attribute \src "libresoc.v:34298.3-34312.6" + wire width 2 $1\cnt_1_10[1:0] + attribute \src "libresoc.v:34313.3-34327.6" + wire width 2 $1\cnt_1_11[1:0] + attribute \src "libresoc.v:34328.3-34342.6" + wire width 2 $1\cnt_1_12[1:0] + attribute \src "libresoc.v:34343.3-34357.6" + wire width 2 $1\cnt_1_13[1:0] + attribute \src "libresoc.v:34358.3-34372.6" + wire width 2 $1\cnt_1_14[1:0] + attribute \src "libresoc.v:34388.3-34402.6" + wire width 2 $1\cnt_1_15[1:0] + attribute \src "libresoc.v:34403.3-34417.6" + wire width 2 $1\cnt_1_16[1:0] + attribute \src "libresoc.v:34418.3-34432.6" + wire width 2 $1\cnt_1_17[1:0] + attribute \src "libresoc.v:34433.3-34447.6" + wire width 2 $1\cnt_1_18[1:0] + attribute \src "libresoc.v:34448.3-34462.6" + wire width 2 $1\cnt_1_19[1:0] + attribute \src "libresoc.v:34373.3-34387.6" + wire width 2 $1\cnt_1_1[1:0] + attribute \src "libresoc.v:34463.3-34477.6" + wire width 2 $1\cnt_1_20[1:0] + attribute \src "libresoc.v:34478.3-34492.6" + wire width 2 $1\cnt_1_21[1:0] + attribute \src "libresoc.v:34493.3-34507.6" + wire width 2 $1\cnt_1_22[1:0] + attribute \src "libresoc.v:34508.3-34522.6" + wire width 2 $1\cnt_1_23[1:0] + attribute \src "libresoc.v:34523.3-34537.6" + wire width 2 $1\cnt_1_24[1:0] + attribute \src "libresoc.v:34553.3-34567.6" + wire width 2 $1\cnt_1_25[1:0] + attribute \src "libresoc.v:34568.3-34582.6" + wire width 2 $1\cnt_1_26[1:0] + attribute \src "libresoc.v:34583.3-34597.6" + wire width 2 $1\cnt_1_27[1:0] + attribute \src "libresoc.v:34598.3-34612.6" + wire width 2 $1\cnt_1_28[1:0] + attribute \src "libresoc.v:34613.3-34627.6" + wire width 2 $1\cnt_1_29[1:0] + attribute \src "libresoc.v:34538.3-34552.6" + wire width 2 $1\cnt_1_2[1:0] + attribute \src "libresoc.v:34628.3-34642.6" + wire width 2 $1\cnt_1_30[1:0] + attribute \src "libresoc.v:34643.3-34657.6" + wire width 2 $1\cnt_1_31[1:0] + attribute \src "libresoc.v:34778.3-34792.6" + wire width 2 $1\cnt_1_3[1:0] + attribute \src "libresoc.v:35193.3-35207.6" + wire width 2 $1\cnt_1_4[1:0] + attribute \src "libresoc.v:34223.3-34237.6" + wire width 2 $1\cnt_1_5[1:0] + attribute \src "libresoc.v:34238.3-34252.6" + wire width 2 $1\cnt_1_6[1:0] + attribute \src "libresoc.v:34253.3-34267.6" + wire width 2 $1\cnt_1_7[1:0] + attribute \src "libresoc.v:34268.3-34282.6" + wire width 2 $1\cnt_1_8[1:0] + attribute \src "libresoc.v:34283.3-34297.6" + wire width 2 $1\cnt_1_9[1:0] + attribute \src "libresoc.v:34658.3-34677.6" + wire width 3 $1\cnt_2_0[2:0] + attribute \src "libresoc.v:34758.3-34777.6" + wire width 3 $1\cnt_2_10[2:0] + attribute \src "libresoc.v:34793.3-34812.6" + wire width 3 $1\cnt_2_12[2:0] + attribute \src "libresoc.v:34813.3-34832.6" + wire width 3 $1\cnt_2_14[2:0] + attribute \src "libresoc.v:34833.3-34852.6" + wire width 3 $1\cnt_2_16[2:0] + attribute \src "libresoc.v:34853.3-34872.6" + wire width 3 $1\cnt_2_18[2:0] + attribute \src "libresoc.v:34873.3-34892.6" + wire width 3 $1\cnt_2_20[2:0] + attribute \src "libresoc.v:34893.3-34912.6" + wire width 3 $1\cnt_2_22[2:0] + attribute \src "libresoc.v:34913.3-34932.6" + wire width 3 $1\cnt_2_24[2:0] + attribute \src "libresoc.v:34933.3-34952.6" + wire width 3 $1\cnt_2_26[2:0] + attribute \src "libresoc.v:34953.3-34972.6" + wire width 3 $1\cnt_2_28[2:0] + attribute \src "libresoc.v:34678.3-34697.6" + wire width 3 $1\cnt_2_2[2:0] + attribute \src "libresoc.v:34973.3-34992.6" + wire width 3 $1\cnt_2_30[2:0] + attribute \src "libresoc.v:34698.3-34717.6" + wire width 3 $1\cnt_2_4[2:0] + attribute \src "libresoc.v:34718.3-34737.6" + wire width 3 $1\cnt_2_6[2:0] + attribute \src "libresoc.v:34738.3-34757.6" + wire width 3 $1\cnt_2_8[2:0] + attribute \src "libresoc.v:34993.3-35012.6" + wire width 4 $1\cnt_3_0[3:0] + attribute \src "libresoc.v:35093.3-35112.6" + wire width 4 $1\cnt_3_10[3:0] + attribute \src "libresoc.v:35113.3-35132.6" + wire width 4 $1\cnt_3_12[3:0] + attribute \src "libresoc.v:35133.3-35152.6" + wire width 4 $1\cnt_3_14[3:0] + attribute \src "libresoc.v:35013.3-35032.6" + wire width 4 $1\cnt_3_2[3:0] + attribute \src "libresoc.v:35033.3-35052.6" + wire width 4 $1\cnt_3_4[3:0] + attribute \src "libresoc.v:35053.3-35072.6" + wire width 4 $1\cnt_3_6[3:0] + attribute \src "libresoc.v:35073.3-35092.6" + wire width 4 $1\cnt_3_8[3:0] + attribute \src "libresoc.v:35153.3-35172.6" + wire width 5 $1\cnt_4_0[4:0] + attribute \src "libresoc.v:35173.3-35192.6" + wire width 5 $1\cnt_4_2[4:0] + attribute \src "libresoc.v:35208.3-35227.6" + wire width 5 $1\cnt_4_4[4:0] + attribute \src "libresoc.v:35228.3-35247.6" + wire width 5 $1\cnt_4_6[4:0] + attribute \src "libresoc.v:35248.3-35267.6" + wire width 6 $1\cnt_5_0[5:0] + attribute \src "libresoc.v:35268.3-35287.6" + wire width 6 $1\cnt_5_2[5:0] + attribute \src "libresoc.v:35288.3-35307.6" + wire width 7 $1\cnt_6_0[6:0] + attribute \src "libresoc.v:34658.3-34677.6" + wire width 3 $2\cnt_2_0[2:0] + attribute \src "libresoc.v:34758.3-34777.6" + wire width 3 $2\cnt_2_10[2:0] + attribute \src "libresoc.v:34793.3-34812.6" + wire width 3 $2\cnt_2_12[2:0] + attribute \src "libresoc.v:34813.3-34832.6" + wire width 3 $2\cnt_2_14[2:0] + attribute \src "libresoc.v:34833.3-34852.6" + wire width 3 $2\cnt_2_16[2:0] + attribute \src "libresoc.v:34853.3-34872.6" + wire width 3 $2\cnt_2_18[2:0] + attribute \src "libresoc.v:34873.3-34892.6" + wire width 3 $2\cnt_2_20[2:0] + attribute \src "libresoc.v:34893.3-34912.6" + wire width 3 $2\cnt_2_22[2:0] + attribute \src "libresoc.v:34913.3-34932.6" + wire width 3 $2\cnt_2_24[2:0] + attribute \src "libresoc.v:34933.3-34952.6" + wire width 3 $2\cnt_2_26[2:0] + attribute \src "libresoc.v:34953.3-34972.6" + wire width 3 $2\cnt_2_28[2:0] + attribute \src "libresoc.v:34678.3-34697.6" + wire width 3 $2\cnt_2_2[2:0] + attribute \src "libresoc.v:34973.3-34992.6" + wire width 3 $2\cnt_2_30[2:0] + attribute \src "libresoc.v:34698.3-34717.6" + wire width 3 $2\cnt_2_4[2:0] + attribute \src "libresoc.v:34718.3-34737.6" + wire width 3 $2\cnt_2_6[2:0] + attribute \src "libresoc.v:34738.3-34757.6" + wire width 3 $2\cnt_2_8[2:0] + attribute \src "libresoc.v:34993.3-35012.6" + wire width 4 $2\cnt_3_0[3:0] + attribute \src "libresoc.v:35093.3-35112.6" + wire width 4 $2\cnt_3_10[3:0] + attribute \src "libresoc.v:35113.3-35132.6" + wire width 4 $2\cnt_3_12[3:0] + attribute \src "libresoc.v:35133.3-35152.6" + wire width 4 $2\cnt_3_14[3:0] + attribute \src "libresoc.v:35013.3-35032.6" + wire width 4 $2\cnt_3_2[3:0] + attribute \src "libresoc.v:35033.3-35052.6" + wire width 4 $2\cnt_3_4[3:0] + attribute \src "libresoc.v:35053.3-35072.6" + wire width 4 $2\cnt_3_6[3:0] + attribute \src "libresoc.v:35073.3-35092.6" + wire width 4 $2\cnt_3_8[3:0] + attribute \src "libresoc.v:35153.3-35172.6" + wire width 5 $2\cnt_4_0[4:0] + attribute \src "libresoc.v:35173.3-35192.6" + wire width 5 $2\cnt_4_2[4:0] + attribute \src "libresoc.v:35208.3-35227.6" + wire width 5 $2\cnt_4_4[4:0] + attribute \src "libresoc.v:35228.3-35247.6" + wire width 5 $2\cnt_4_6[4:0] + attribute \src "libresoc.v:35248.3-35267.6" + wire width 6 $2\cnt_5_0[5:0] + attribute \src "libresoc.v:35268.3-35287.6" + wire width 6 $2\cnt_5_2[5:0] + attribute \src "libresoc.v:35288.3-35307.6" + wire width 7 $2\cnt_6_0[6:0] + attribute \src "libresoc.v:34115.17-34115.101" + wire $eq$libresoc.v:34115$1357_Y + attribute \src "libresoc.v:34116.18-34116.102" + wire $eq$libresoc.v:34116$1358_Y + attribute \src "libresoc.v:34118.19-34118.103" + wire $eq$libresoc.v:34118$1360_Y + attribute \src "libresoc.v:34119.19-34119.103" + wire $eq$libresoc.v:34119$1361_Y + attribute \src "libresoc.v:34121.19-34121.104" + wire $eq$libresoc.v:34121$1363_Y + attribute \src "libresoc.v:34122.19-34122.103" + wire $eq$libresoc.v:34122$1364_Y + attribute \src "libresoc.v:34124.19-34124.104" + wire $eq$libresoc.v:34124$1366_Y + attribute \src "libresoc.v:34125.19-34125.104" + wire $eq$libresoc.v:34125$1367_Y + attribute \src "libresoc.v:34128.19-34128.104" + wire $eq$libresoc.v:34128$1370_Y + attribute \src "libresoc.v:34129.19-34129.104" + wire $eq$libresoc.v:34129$1371_Y + attribute \src "libresoc.v:34131.19-34131.104" + wire $eq$libresoc.v:34131$1373_Y + attribute \src "libresoc.v:34132.19-34132.104" + wire $eq$libresoc.v:34132$1374_Y + attribute \src "libresoc.v:34134.19-34134.104" + wire $eq$libresoc.v:34134$1376_Y + attribute \src "libresoc.v:34135.19-34135.104" + wire $eq$libresoc.v:34135$1377_Y + attribute \src "libresoc.v:34137.18-34137.102" + wire $eq$libresoc.v:34137$1379_Y + attribute \src "libresoc.v:34138.19-34138.104" + wire $eq$libresoc.v:34138$1380_Y + attribute \src "libresoc.v:34139.19-34139.104" + wire $eq$libresoc.v:34139$1381_Y + attribute \src "libresoc.v:34141.19-34141.103" + wire $eq$libresoc.v:34141$1383_Y + attribute \src "libresoc.v:34142.19-34142.103" + wire $eq$libresoc.v:34142$1384_Y + attribute \src "libresoc.v:34144.19-34144.103" + wire $eq$libresoc.v:34144$1386_Y + attribute \src "libresoc.v:34145.19-34145.103" + wire $eq$libresoc.v:34145$1387_Y + attribute \src "libresoc.v:34147.19-34147.104" + wire $eq$libresoc.v:34147$1389_Y + attribute \src "libresoc.v:34148.18-34148.102" + wire $eq$libresoc.v:34148$1390_Y + attribute \src "libresoc.v:34149.19-34149.103" + wire $eq$libresoc.v:34149$1391_Y + attribute \src "libresoc.v:34151.19-34151.104" + wire $eq$libresoc.v:34151$1393_Y + attribute \src "libresoc.v:34152.19-34152.104" + wire $eq$libresoc.v:34152$1394_Y + attribute \src "libresoc.v:34154.19-34154.103" + wire $eq$libresoc.v:34154$1396_Y + attribute \src "libresoc.v:34155.19-34155.103" + wire $eq$libresoc.v:34155$1397_Y + attribute \src "libresoc.v:34157.19-34157.103" + wire $eq$libresoc.v:34157$1399_Y + attribute \src "libresoc.v:34158.19-34158.103" + wire $eq$libresoc.v:34158$1400_Y + attribute \src "libresoc.v:34161.19-34161.103" + wire $eq$libresoc.v:34161$1403_Y + attribute \src "libresoc.v:34162.19-34162.103" + wire $eq$libresoc.v:34162$1404_Y + attribute \src "libresoc.v:34164.17-34164.101" + wire $eq$libresoc.v:34164$1406_Y + attribute \src "libresoc.v:34165.18-34165.102" + wire $eq$libresoc.v:34165$1407_Y + attribute \src "libresoc.v:34166.18-34166.102" + wire $eq$libresoc.v:34166$1408_Y + attribute \src "libresoc.v:34168.18-34168.102" + wire $eq$libresoc.v:34168$1410_Y + attribute \src "libresoc.v:34169.18-34169.102" + wire $eq$libresoc.v:34169$1411_Y + attribute \src "libresoc.v:34171.18-34171.103" + wire $eq$libresoc.v:34171$1413_Y + attribute \src "libresoc.v:34172.18-34172.103" + wire $eq$libresoc.v:34172$1414_Y + attribute \src "libresoc.v:34174.18-34174.103" + wire $eq$libresoc.v:34174$1416_Y + attribute \src "libresoc.v:34175.17-34175.101" + wire $eq$libresoc.v:34175$1417_Y + attribute \src "libresoc.v:34176.18-34176.103" + wire $eq$libresoc.v:34176$1418_Y + attribute \src "libresoc.v:34178.18-34178.103" + wire $eq$libresoc.v:34178$1420_Y + attribute \src "libresoc.v:34179.18-34179.103" + wire $eq$libresoc.v:34179$1421_Y + attribute \src "libresoc.v:34181.18-34181.103" + wire $eq$libresoc.v:34181$1423_Y + attribute \src "libresoc.v:34182.18-34182.103" + wire $eq$libresoc.v:34182$1424_Y + attribute \src "libresoc.v:34184.18-34184.103" + wire $eq$libresoc.v:34184$1426_Y + attribute \src "libresoc.v:34185.18-34185.103" + wire $eq$libresoc.v:34185$1427_Y + attribute \src "libresoc.v:34188.18-34188.103" + wire $eq$libresoc.v:34188$1430_Y + attribute \src "libresoc.v:34189.18-34189.103" + wire $eq$libresoc.v:34189$1431_Y + attribute \src "libresoc.v:34191.18-34191.103" + wire $eq$libresoc.v:34191$1433_Y + attribute \src "libresoc.v:34192.18-34192.103" + wire $eq$libresoc.v:34192$1434_Y + attribute \src "libresoc.v:34194.18-34194.103" + wire $eq$libresoc.v:34194$1436_Y + attribute \src "libresoc.v:34195.18-34195.103" + wire $eq$libresoc.v:34195$1437_Y + attribute \src "libresoc.v:34197.17-34197.101" + wire $eq$libresoc.v:34197$1439_Y + attribute \src "libresoc.v:34198.18-34198.103" + wire $eq$libresoc.v:34198$1440_Y + attribute \src "libresoc.v:34199.18-34199.103" + wire $eq$libresoc.v:34199$1441_Y + attribute \src "libresoc.v:34201.18-34201.103" + wire $eq$libresoc.v:34201$1443_Y + attribute \src "libresoc.v:34202.18-34202.103" + wire $eq$libresoc.v:34202$1444_Y + attribute \src "libresoc.v:34204.18-34204.103" + wire $eq$libresoc.v:34204$1446_Y + attribute \src "libresoc.v:34205.18-34205.103" + wire $eq$libresoc.v:34205$1447_Y + attribute \src "libresoc.v:34207.18-34207.102" + wire $eq$libresoc.v:34207$1449_Y + attribute \src "libresoc.v:34117.19-34117.109" + wire width 4 $pos$libresoc.v:34117$1359_Y + attribute \src "libresoc.v:34120.19-34120.109" + wire width 4 $pos$libresoc.v:34120$1362_Y + attribute \src "libresoc.v:34123.19-34123.109" + wire width 4 $pos$libresoc.v:34123$1365_Y + attribute \src "libresoc.v:34126.18-34126.106" + wire width 3 $pos$libresoc.v:34126$1368_Y + attribute \src "libresoc.v:34127.19-34127.110" + wire width 4 $pos$libresoc.v:34127$1369_Y + attribute \src "libresoc.v:34130.19-34130.110" + wire width 4 $pos$libresoc.v:34130$1372_Y + attribute \src "libresoc.v:34133.19-34133.110" + wire width 4 $pos$libresoc.v:34133$1375_Y + attribute \src "libresoc.v:34136.19-34136.110" + wire width 4 $pos$libresoc.v:34136$1378_Y + attribute \src "libresoc.v:34140.19-34140.110" + wire width 4 $pos$libresoc.v:34140$1382_Y + attribute \src "libresoc.v:34143.19-34143.109" + wire width 5 $pos$libresoc.v:34143$1385_Y + attribute \src "libresoc.v:34146.19-34146.109" + wire width 5 $pos$libresoc.v:34146$1388_Y + attribute \src "libresoc.v:34150.19-34150.109" + wire width 5 $pos$libresoc.v:34150$1392_Y + attribute \src "libresoc.v:34153.19-34153.110" + wire width 5 $pos$libresoc.v:34153$1395_Y + attribute \src "libresoc.v:34156.19-34156.109" + wire width 6 $pos$libresoc.v:34156$1398_Y + attribute \src "libresoc.v:34159.18-34159.106" + wire width 3 $pos$libresoc.v:34159$1401_Y + attribute \src "libresoc.v:34160.19-34160.109" + wire width 6 $pos$libresoc.v:34160$1402_Y + attribute \src "libresoc.v:34163.19-34163.109" + wire width 7 $pos$libresoc.v:34163$1405_Y + attribute \src "libresoc.v:34167.18-34167.106" + wire width 3 $pos$libresoc.v:34167$1409_Y + attribute \src "libresoc.v:34170.18-34170.106" + wire width 3 $pos$libresoc.v:34170$1412_Y + attribute \src "libresoc.v:34173.18-34173.107" + wire width 3 $pos$libresoc.v:34173$1415_Y + attribute \src "libresoc.v:34177.18-34177.107" + wire width 3 $pos$libresoc.v:34177$1419_Y + attribute \src "libresoc.v:34180.18-34180.107" + wire width 3 $pos$libresoc.v:34180$1422_Y + attribute \src "libresoc.v:34183.18-34183.107" + wire width 3 $pos$libresoc.v:34183$1425_Y + attribute \src "libresoc.v:34186.17-34186.105" + wire width 3 $pos$libresoc.v:34186$1428_Y + attribute \src "libresoc.v:34187.18-34187.107" + wire width 3 $pos$libresoc.v:34187$1429_Y + attribute \src "libresoc.v:34190.18-34190.107" + wire width 3 $pos$libresoc.v:34190$1432_Y + attribute \src "libresoc.v:34193.18-34193.107" + wire width 3 $pos$libresoc.v:34193$1435_Y + attribute \src "libresoc.v:34196.18-34196.107" + wire width 3 $pos$libresoc.v:34196$1438_Y + attribute \src "libresoc.v:34200.18-34200.107" + wire width 3 $pos$libresoc.v:34200$1442_Y + attribute \src "libresoc.v:34203.18-34203.107" + wire width 3 $pos$libresoc.v:34203$1445_Y + attribute \src "libresoc.v:34206.18-34206.107" + wire width 3 $pos$libresoc.v:34206$1448_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + wire width 4 \$101 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + wire \$103 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + wire \$105 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + wire width 4 \$107 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + wire \$109 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + wire width 3 \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + wire \$111 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + wire width 4 \$113 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + wire \$115 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + wire \$117 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + wire width 4 \$119 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + wire \$121 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + wire \$123 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + wire width 4 \$125 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + wire \$127 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + wire \$129 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + wire width 4 \$131 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + wire \$133 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + wire \$135 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + wire width 4 \$137 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + wire \$139 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + wire \$141 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + wire width 4 \$143 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + wire \$145 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + wire \$147 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + wire width 5 \$149 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + wire \$151 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + wire \$153 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + wire width 5 \$155 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + wire \$157 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + wire \$159 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + wire width 5 \$161 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + wire \$163 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + wire \$165 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + wire width 5 \$167 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + wire \$169 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + wire width 3 \$17 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + wire \$171 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + wire width 6 \$173 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + wire \$175 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + wire \$177 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + wire width 6 \$179 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + wire \$181 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + wire \$183 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + wire width 7 \$185 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + wire \$21 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + wire width 3 \$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + wire \$25 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + wire width 3 \$29 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + wire \$33 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + wire width 3 \$35 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + wire \$37 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + wire \$39 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + wire width 3 \$41 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + wire \$43 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + wire \$45 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + wire width 3 \$47 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + wire \$49 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + wire width 3 \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + wire \$51 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + wire width 3 \$53 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + wire \$55 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + wire \$57 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + wire width 3 \$59 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + wire \$61 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + wire \$63 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + wire width 3 \$65 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + wire \$67 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + wire \$69 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + wire width 3 \$71 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + wire \$73 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + wire \$75 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + wire width 3 \$77 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + wire \$79 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + wire \$81 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + wire width 3 \$83 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + wire \$85 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + wire \$87 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + wire width 3 \$89 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + wire \$91 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + wire \$93 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + wire width 3 \$95 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + wire \$97 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + wire \$99 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + wire width 2 \cnt_1_0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + wire width 2 \cnt_1_1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + wire width 2 \cnt_1_10 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + wire width 2 \cnt_1_11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + wire width 2 \cnt_1_12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + wire width 2 \cnt_1_13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + wire width 2 \cnt_1_14 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + wire width 2 \cnt_1_15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + wire width 2 \cnt_1_16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + wire width 2 \cnt_1_17 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + wire width 2 \cnt_1_18 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + wire width 2 \cnt_1_19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + wire width 2 \cnt_1_2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + wire width 2 \cnt_1_20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + wire width 2 \cnt_1_21 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + wire width 2 \cnt_1_22 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + wire width 2 \cnt_1_23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + wire width 2 \cnt_1_24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + wire width 2 \cnt_1_25 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + wire width 2 \cnt_1_26 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + wire width 2 \cnt_1_27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + wire width 2 \cnt_1_28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + wire width 2 \cnt_1_29 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + wire width 2 \cnt_1_3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + wire width 2 \cnt_1_30 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + wire width 2 \cnt_1_31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + wire width 2 \cnt_1_4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + wire width 2 \cnt_1_5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + wire width 2 \cnt_1_6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + wire width 2 \cnt_1_7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + wire width 2 \cnt_1_8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + wire width 2 \cnt_1_9 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + wire width 3 \cnt_2_0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + wire width 3 \cnt_2_10 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + wire width 3 \cnt_2_12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + wire width 3 \cnt_2_14 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + wire width 3 \cnt_2_16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + wire width 3 \cnt_2_18 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + wire width 3 \cnt_2_2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + wire width 3 \cnt_2_20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + wire width 3 \cnt_2_22 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + wire width 3 \cnt_2_24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + wire width 3 \cnt_2_26 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + wire width 3 \cnt_2_28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + wire width 3 \cnt_2_30 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + wire width 3 \cnt_2_4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + wire width 3 \cnt_2_6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + wire width 3 \cnt_2_8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + wire width 4 \cnt_3_0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + wire width 4 \cnt_3_10 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + wire width 4 \cnt_3_12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + wire width 4 \cnt_3_14 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + wire width 4 \cnt_3_2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + wire width 4 \cnt_3_4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + wire width 4 \cnt_3_6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + wire width 4 \cnt_3_8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + wire width 5 \cnt_4_0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + wire width 5 \cnt_4_2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + wire width 5 \cnt_4_4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + wire width 5 \cnt_4_6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + wire width 6 \cnt_5_0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + wire width 6 \cnt_5_2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + wire width 7 \cnt_6_0 + attribute \src "libresoc.v:33734.7-33734.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:13" + wire width 7 output 1 \lz + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + wire width 2 \pair0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + wire width 2 \pair10 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + wire width 2 \pair12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + wire width 2 \pair14 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + wire width 2 \pair16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + wire width 2 \pair18 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + wire width 2 \pair2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + wire width 2 \pair20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + wire width 2 \pair22 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + wire width 2 \pair24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + wire width 2 \pair26 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + wire width 2 \pair28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + wire width 2 \pair30 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + wire width 2 \pair32 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + wire width 2 \pair34 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + wire width 2 \pair36 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + wire width 2 \pair38 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + wire width 2 \pair4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + wire width 2 \pair40 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + wire width 2 \pair42 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + wire width 2 \pair44 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + wire width 2 \pair46 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + wire width 2 \pair48 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + wire width 2 \pair50 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + wire width 2 \pair52 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + wire width 2 \pair54 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + wire width 2 \pair56 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + wire width 2 \pair58 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + wire width 2 \pair6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + wire width 2 \pair60 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + wire width 2 \pair62 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + wire width 2 \pair8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:11" + wire width 64 input 2 \sig_in + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + cell $eq $eq$libresoc.v:34115$1357 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_2 [1] + connect \B 1'1 + connect \Y $eq$libresoc.v:34115$1357_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + cell $eq $eq$libresoc.v:34116$1358 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_2_0 [2] + connect \B 1'1 + connect \Y $eq$libresoc.v:34116$1358_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + cell $eq $eq$libresoc.v:34118$1360 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_2_6 [2] + connect \B 1'1 + connect \Y $eq$libresoc.v:34118$1360_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + cell $eq $eq$libresoc.v:34119$1361 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_2_4 [2] + connect \B 1'1 + connect \Y $eq$libresoc.v:34119$1361_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + cell $eq $eq$libresoc.v:34121$1363 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_2_10 [2] + connect \B 1'1 + connect \Y $eq$libresoc.v:34121$1363_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + cell $eq $eq$libresoc.v:34122$1364 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_2_8 [2] + connect \B 1'1 + connect \Y $eq$libresoc.v:34122$1364_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + cell $eq $eq$libresoc.v:34124$1366 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_2_14 [2] + connect \B 1'1 + connect \Y $eq$libresoc.v:34124$1366_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + cell $eq $eq$libresoc.v:34125$1367 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_2_12 [2] + connect \B 1'1 + connect \Y $eq$libresoc.v:34125$1367_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + cell $eq $eq$libresoc.v:34128$1370 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_2_18 [2] + connect \B 1'1 + connect \Y $eq$libresoc.v:34128$1370_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + cell $eq $eq$libresoc.v:34129$1371 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_2_16 [2] + connect \B 1'1 + connect \Y $eq$libresoc.v:34129$1371_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + cell $eq $eq$libresoc.v:34131$1373 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_2_22 [2] + connect \B 1'1 + connect \Y $eq$libresoc.v:34131$1373_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + cell $eq $eq$libresoc.v:34132$1374 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_2_20 [2] + connect \B 1'1 + connect \Y $eq$libresoc.v:34132$1374_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + cell $eq $eq$libresoc.v:34134$1376 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_2_26 [2] + connect \B 1'1 + connect \Y $eq$libresoc.v:34134$1376_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + cell $eq $eq$libresoc.v:34135$1377 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_2_24 [2] + connect \B 1'1 + connect \Y $eq$libresoc.v:34135$1377_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + cell $eq $eq$libresoc.v:34137$1379 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_5 [1] + connect \B 1'1 + connect \Y $eq$libresoc.v:34137$1379_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + cell $eq $eq$libresoc.v:34138$1380 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_2_30 [2] + connect \B 1'1 + connect \Y $eq$libresoc.v:34138$1380_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + cell $eq $eq$libresoc.v:34139$1381 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_2_28 [2] + connect \B 1'1 + connect \Y $eq$libresoc.v:34139$1381_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + cell $eq $eq$libresoc.v:34141$1383 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_3_2 [3] + connect \B 1'1 + connect \Y $eq$libresoc.v:34141$1383_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + cell $eq $eq$libresoc.v:34142$1384 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_3_0 [3] + connect \B 1'1 + connect \Y $eq$libresoc.v:34142$1384_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + cell $eq $eq$libresoc.v:34144$1386 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_3_6 [3] + connect \B 1'1 + connect \Y $eq$libresoc.v:34144$1386_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + cell $eq $eq$libresoc.v:34145$1387 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_3_4 [3] + connect \B 1'1 + connect \Y $eq$libresoc.v:34145$1387_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + cell $eq $eq$libresoc.v:34147$1389 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_3_10 [3] + connect \B 1'1 + connect \Y $eq$libresoc.v:34147$1389_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + cell $eq $eq$libresoc.v:34148$1390 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_4 [1] + connect \B 1'1 + connect \Y $eq$libresoc.v:34148$1390_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + cell $eq $eq$libresoc.v:34149$1391 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_3_8 [3] + connect \B 1'1 + connect \Y $eq$libresoc.v:34149$1391_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + cell $eq $eq$libresoc.v:34151$1393 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_3_14 [3] + connect \B 1'1 + connect \Y $eq$libresoc.v:34151$1393_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + cell $eq $eq$libresoc.v:34152$1394 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_3_12 [3] + connect \B 1'1 + connect \Y $eq$libresoc.v:34152$1394_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + cell $eq $eq$libresoc.v:34154$1396 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_4_2 [4] + connect \B 1'1 + connect \Y $eq$libresoc.v:34154$1396_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + cell $eq $eq$libresoc.v:34155$1397 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_4_0 [4] + connect \B 1'1 + connect \Y $eq$libresoc.v:34155$1397_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + cell $eq $eq$libresoc.v:34157$1399 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_4_6 [4] + connect \B 1'1 + connect \Y $eq$libresoc.v:34157$1399_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + cell $eq $eq$libresoc.v:34158$1400 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_4_4 [4] + connect \B 1'1 + connect \Y $eq$libresoc.v:34158$1400_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + cell $eq $eq$libresoc.v:34161$1403 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_5_2 [5] + connect \B 1'1 + connect \Y $eq$libresoc.v:34161$1403_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + cell $eq $eq$libresoc.v:34162$1404 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_5_0 [5] + connect \B 1'1 + connect \Y $eq$libresoc.v:34162$1404_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + cell $eq $eq$libresoc.v:34164$1406 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_1 [1] + connect \B 1'1 + connect \Y $eq$libresoc.v:34164$1406_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + cell $eq $eq$libresoc.v:34165$1407 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_7 [1] + connect \B 1'1 + connect \Y $eq$libresoc.v:34165$1407_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + cell $eq $eq$libresoc.v:34166$1408 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_6 [1] + connect \B 1'1 + connect \Y $eq$libresoc.v:34166$1408_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + cell $eq $eq$libresoc.v:34168$1410 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_9 [1] + connect \B 1'1 + connect \Y $eq$libresoc.v:34168$1410_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + cell $eq $eq$libresoc.v:34169$1411 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_8 [1] + connect \B 1'1 + connect \Y $eq$libresoc.v:34169$1411_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + cell $eq $eq$libresoc.v:34171$1413 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_11 [1] + connect \B 1'1 + connect \Y $eq$libresoc.v:34171$1413_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + cell $eq $eq$libresoc.v:34172$1414 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_10 [1] + connect \B 1'1 + connect \Y $eq$libresoc.v:34172$1414_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + cell $eq $eq$libresoc.v:34174$1416 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_13 [1] + connect \B 1'1 + connect \Y $eq$libresoc.v:34174$1416_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + cell $eq $eq$libresoc.v:34175$1417 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_0 [1] + connect \B 1'1 + connect \Y $eq$libresoc.v:34175$1417_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + cell $eq $eq$libresoc.v:34176$1418 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_12 [1] + connect \B 1'1 + connect \Y $eq$libresoc.v:34176$1418_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + cell $eq $eq$libresoc.v:34178$1420 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_15 [1] + connect \B 1'1 + connect \Y $eq$libresoc.v:34178$1420_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + cell $eq $eq$libresoc.v:34179$1421 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_14 [1] + connect \B 1'1 + connect \Y $eq$libresoc.v:34179$1421_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + cell $eq $eq$libresoc.v:34181$1423 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_17 [1] + connect \B 1'1 + connect \Y $eq$libresoc.v:34181$1423_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + cell $eq $eq$libresoc.v:34182$1424 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_16 [1] + connect \B 1'1 + connect \Y $eq$libresoc.v:34182$1424_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + cell $eq $eq$libresoc.v:34184$1426 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_19 [1] + connect \B 1'1 + connect \Y $eq$libresoc.v:34184$1426_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + cell $eq $eq$libresoc.v:34185$1427 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_18 [1] + connect \B 1'1 + connect \Y $eq$libresoc.v:34185$1427_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + cell $eq $eq$libresoc.v:34188$1430 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_21 [1] + connect \B 1'1 + connect \Y $eq$libresoc.v:34188$1430_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + cell $eq $eq$libresoc.v:34189$1431 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_20 [1] + connect \B 1'1 + connect \Y $eq$libresoc.v:34189$1431_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + cell $eq $eq$libresoc.v:34191$1433 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_23 [1] + connect \B 1'1 + connect \Y $eq$libresoc.v:34191$1433_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + cell $eq $eq$libresoc.v:34192$1434 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_22 [1] + connect \B 1'1 + connect \Y $eq$libresoc.v:34192$1434_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + cell $eq $eq$libresoc.v:34194$1436 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_25 [1] + connect \B 1'1 + connect \Y $eq$libresoc.v:34194$1436_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + cell $eq $eq$libresoc.v:34195$1437 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_24 [1] + connect \B 1'1 + connect \Y $eq$libresoc.v:34195$1437_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + cell $eq $eq$libresoc.v:34197$1439 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_3 [1] + connect \B 1'1 + connect \Y $eq$libresoc.v:34197$1439_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + cell $eq $eq$libresoc.v:34198$1440 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_27 [1] + connect \B 1'1 + connect \Y $eq$libresoc.v:34198$1440_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + cell $eq $eq$libresoc.v:34199$1441 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_26 [1] + connect \B 1'1 + connect \Y $eq$libresoc.v:34199$1441_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + cell $eq $eq$libresoc.v:34201$1443 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_29 [1] + connect \B 1'1 + connect \Y $eq$libresoc.v:34201$1443_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + cell $eq $eq$libresoc.v:34202$1444 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_28 [1] + connect \B 1'1 + connect \Y $eq$libresoc.v:34202$1444_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + cell $eq $eq$libresoc.v:34204$1446 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_31 [1] + connect \B 1'1 + connect \Y $eq$libresoc.v:34204$1446_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + cell $eq $eq$libresoc.v:34205$1447 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_30 [1] + connect \B 1'1 + connect \Y $eq$libresoc.v:34205$1447_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + cell $eq $eq$libresoc.v:34207$1449 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_2_2 [2] + connect \B 1'1 + connect \Y $eq$libresoc.v:34207$1449_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + cell $pos $pos$libresoc.v:34117$1359 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A { 2'01 \cnt_2_0 [1:0] } + connect \Y $pos$libresoc.v:34117$1359_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + cell $pos $pos$libresoc.v:34120$1362 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A { 2'01 \cnt_2_4 [1:0] } + connect \Y $pos$libresoc.v:34120$1362_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + cell $pos $pos$libresoc.v:34123$1365 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A { 2'01 \cnt_2_8 [1:0] } + connect \Y $pos$libresoc.v:34123$1365_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + cell $pos $pos$libresoc.v:34126$1368 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'01 \cnt_1_2 [0] } + connect \Y $pos$libresoc.v:34126$1368_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + cell $pos $pos$libresoc.v:34127$1369 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A { 2'01 \cnt_2_12 [1:0] } + connect \Y $pos$libresoc.v:34127$1369_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + cell $pos $pos$libresoc.v:34130$1372 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A { 2'01 \cnt_2_16 [1:0] } + connect \Y $pos$libresoc.v:34130$1372_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + cell $pos $pos$libresoc.v:34133$1375 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A { 2'01 \cnt_2_20 [1:0] } + connect \Y $pos$libresoc.v:34133$1375_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + cell $pos $pos$libresoc.v:34136$1378 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A { 2'01 \cnt_2_24 [1:0] } + connect \Y $pos$libresoc.v:34136$1378_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + cell $pos $pos$libresoc.v:34140$1382 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A { 2'01 \cnt_2_28 [1:0] } + connect \Y $pos$libresoc.v:34140$1382_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + cell $pos $pos$libresoc.v:34143$1385 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A { 2'01 \cnt_3_0 [2:0] } + connect \Y $pos$libresoc.v:34143$1385_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + cell $pos $pos$libresoc.v:34146$1388 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A { 2'01 \cnt_3_4 [2:0] } + connect \Y $pos$libresoc.v:34146$1388_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + cell $pos $pos$libresoc.v:34150$1392 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A { 2'01 \cnt_3_8 [2:0] } + connect \Y $pos$libresoc.v:34150$1392_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + cell $pos $pos$libresoc.v:34153$1395 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A { 2'01 \cnt_3_12 [2:0] } + connect \Y $pos$libresoc.v:34153$1395_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + cell $pos $pos$libresoc.v:34156$1398 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A { 2'01 \cnt_4_0 [3:0] } + connect \Y $pos$libresoc.v:34156$1398_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + cell $pos $pos$libresoc.v:34159$1401 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'01 \cnt_1_4 [0] } + connect \Y $pos$libresoc.v:34159$1401_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + cell $pos $pos$libresoc.v:34160$1402 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A { 2'01 \cnt_4_4 [3:0] } + connect \Y $pos$libresoc.v:34160$1402_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + cell $pos $pos$libresoc.v:34163$1405 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 7 + connect \A { 2'01 \cnt_5_0 [4:0] } + connect \Y $pos$libresoc.v:34163$1405_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + cell $pos $pos$libresoc.v:34167$1409 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'01 \cnt_1_6 [0] } + connect \Y $pos$libresoc.v:34167$1409_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + cell $pos $pos$libresoc.v:34170$1412 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'01 \cnt_1_8 [0] } + connect \Y $pos$libresoc.v:34170$1412_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + cell $pos $pos$libresoc.v:34173$1415 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'01 \cnt_1_10 [0] } + connect \Y $pos$libresoc.v:34173$1415_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + cell $pos $pos$libresoc.v:34177$1419 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'01 \cnt_1_12 [0] } + connect \Y $pos$libresoc.v:34177$1419_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + cell $pos $pos$libresoc.v:34180$1422 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'01 \cnt_1_14 [0] } + connect \Y $pos$libresoc.v:34180$1422_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + cell $pos $pos$libresoc.v:34183$1425 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'01 \cnt_1_16 [0] } + connect \Y $pos$libresoc.v:34183$1425_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + cell $pos $pos$libresoc.v:34186$1428 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'01 \cnt_1_0 [0] } + connect \Y $pos$libresoc.v:34186$1428_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + cell $pos $pos$libresoc.v:34187$1429 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'01 \cnt_1_18 [0] } + connect \Y $pos$libresoc.v:34187$1429_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + cell $pos $pos$libresoc.v:34190$1432 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'01 \cnt_1_20 [0] } + connect \Y $pos$libresoc.v:34190$1432_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + cell $pos $pos$libresoc.v:34193$1435 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'01 \cnt_1_22 [0] } + connect \Y $pos$libresoc.v:34193$1435_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + cell $pos $pos$libresoc.v:34196$1438 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'01 \cnt_1_24 [0] } + connect \Y $pos$libresoc.v:34196$1438_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + cell $pos $pos$libresoc.v:34200$1442 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'01 \cnt_1_26 [0] } + connect \Y $pos$libresoc.v:34200$1442_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + cell $pos $pos$libresoc.v:34203$1445 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'01 \cnt_1_28 [0] } + connect \Y $pos$libresoc.v:34203$1445_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + cell $pos $pos$libresoc.v:34206$1448 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'01 \cnt_1_30 [0] } + connect \Y $pos$libresoc.v:34206$1448_Y + end + attribute \src "libresoc.v:33734.7-33734.20" + process $proc$libresoc.v:33734$1513 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:34208.3-34222.6" + process $proc$libresoc.v:34208$1450 + assign { } { } + assign $0\cnt_1_0[1:0] $1\cnt_1_0[1:0] + attribute \src "libresoc.v:34209.5-34209.29" + switch \initial + attribute \src "libresoc.v:34209.9-34209.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + switch \pair0 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_0[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_0[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_0[1:0] 2'00 + end + sync always + update \cnt_1_0 $0\cnt_1_0[1:0] + end + attribute \src "libresoc.v:34223.3-34237.6" + process $proc$libresoc.v:34223$1451 + assign { } { } + assign $0\cnt_1_5[1:0] $1\cnt_1_5[1:0] + attribute \src "libresoc.v:34224.5-34224.29" + switch \initial + attribute \src "libresoc.v:34224.9-34224.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + switch \pair10 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_5[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_5[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_5[1:0] 2'00 + end + sync always + update \cnt_1_5 $0\cnt_1_5[1:0] + end + attribute \src "libresoc.v:34238.3-34252.6" + process $proc$libresoc.v:34238$1452 + assign { } { } + assign $0\cnt_1_6[1:0] $1\cnt_1_6[1:0] + attribute \src "libresoc.v:34239.5-34239.29" + switch \initial + attribute \src "libresoc.v:34239.9-34239.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + switch \pair12 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_6[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_6[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_6[1:0] 2'00 + end + sync always + update \cnt_1_6 $0\cnt_1_6[1:0] + end + attribute \src "libresoc.v:34253.3-34267.6" + process $proc$libresoc.v:34253$1453 + assign { } { } + assign $0\cnt_1_7[1:0] $1\cnt_1_7[1:0] + attribute \src "libresoc.v:34254.5-34254.29" + switch \initial + attribute \src "libresoc.v:34254.9-34254.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + switch \pair14 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_7[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_7[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_7[1:0] 2'00 + end + sync always + update \cnt_1_7 $0\cnt_1_7[1:0] + end + attribute \src "libresoc.v:34268.3-34282.6" + process $proc$libresoc.v:34268$1454 + assign { } { } + assign $0\cnt_1_8[1:0] $1\cnt_1_8[1:0] + attribute \src "libresoc.v:34269.5-34269.29" + switch \initial + attribute \src "libresoc.v:34269.9-34269.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + switch \pair16 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_8[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_8[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_8[1:0] 2'00 + end + sync always + update \cnt_1_8 $0\cnt_1_8[1:0] + end + attribute \src "libresoc.v:34283.3-34297.6" + process $proc$libresoc.v:34283$1455 + assign { } { } + assign $0\cnt_1_9[1:0] $1\cnt_1_9[1:0] + attribute \src "libresoc.v:34284.5-34284.29" + switch \initial + attribute \src "libresoc.v:34284.9-34284.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + switch \pair18 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_9[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_9[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_9[1:0] 2'00 + end + sync always + update \cnt_1_9 $0\cnt_1_9[1:0] + end + attribute \src "libresoc.v:34298.3-34312.6" + process $proc$libresoc.v:34298$1456 + assign { } { } + assign $0\cnt_1_10[1:0] $1\cnt_1_10[1:0] + attribute \src "libresoc.v:34299.5-34299.29" + switch \initial + attribute \src "libresoc.v:34299.9-34299.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + switch \pair20 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_10[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_10[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_10[1:0] 2'00 + end + sync always + update \cnt_1_10 $0\cnt_1_10[1:0] + end + attribute \src "libresoc.v:34313.3-34327.6" + process $proc$libresoc.v:34313$1457 + assign { } { } + assign $0\cnt_1_11[1:0] $1\cnt_1_11[1:0] + attribute \src "libresoc.v:34314.5-34314.29" + switch \initial + attribute \src "libresoc.v:34314.9-34314.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + switch \pair22 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_11[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_11[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_11[1:0] 2'00 + end + sync always + update \cnt_1_11 $0\cnt_1_11[1:0] + end + attribute \src "libresoc.v:34328.3-34342.6" + process $proc$libresoc.v:34328$1458 + assign { } { } + assign $0\cnt_1_12[1:0] $1\cnt_1_12[1:0] + attribute \src "libresoc.v:34329.5-34329.29" + switch \initial + attribute \src "libresoc.v:34329.9-34329.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + switch \pair24 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_12[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_12[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_12[1:0] 2'00 + end + sync always + update \cnt_1_12 $0\cnt_1_12[1:0] + end + attribute \src "libresoc.v:34343.3-34357.6" + process $proc$libresoc.v:34343$1459 + assign { } { } + assign $0\cnt_1_13[1:0] $1\cnt_1_13[1:0] + attribute \src "libresoc.v:34344.5-34344.29" + switch \initial + attribute \src "libresoc.v:34344.9-34344.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + switch \pair26 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_13[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_13[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_13[1:0] 2'00 + end + sync always + update \cnt_1_13 $0\cnt_1_13[1:0] + end + attribute \src "libresoc.v:34358.3-34372.6" + process $proc$libresoc.v:34358$1460 + assign { } { } + assign $0\cnt_1_14[1:0] $1\cnt_1_14[1:0] + attribute \src "libresoc.v:34359.5-34359.29" + switch \initial + attribute \src "libresoc.v:34359.9-34359.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + switch \pair28 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_14[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_14[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_14[1:0] 2'00 + end + sync always + update \cnt_1_14 $0\cnt_1_14[1:0] + end + attribute \src "libresoc.v:34373.3-34387.6" + process $proc$libresoc.v:34373$1461 + assign { } { } + assign $0\cnt_1_1[1:0] $1\cnt_1_1[1:0] + attribute \src "libresoc.v:34374.5-34374.29" + switch \initial + attribute \src "libresoc.v:34374.9-34374.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + switch \pair2 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_1[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_1[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_1[1:0] 2'00 + end + sync always + update \cnt_1_1 $0\cnt_1_1[1:0] + end + attribute \src "libresoc.v:34388.3-34402.6" + process $proc$libresoc.v:34388$1462 + assign { } { } + assign $0\cnt_1_15[1:0] $1\cnt_1_15[1:0] + attribute \src "libresoc.v:34389.5-34389.29" + switch \initial + attribute \src "libresoc.v:34389.9-34389.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + switch \pair30 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_15[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_15[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_15[1:0] 2'00 + end + sync always + update \cnt_1_15 $0\cnt_1_15[1:0] + end + attribute \src "libresoc.v:34403.3-34417.6" + process $proc$libresoc.v:34403$1463 + assign { } { } + assign $0\cnt_1_16[1:0] $1\cnt_1_16[1:0] + attribute \src "libresoc.v:34404.5-34404.29" + switch \initial + attribute \src "libresoc.v:34404.9-34404.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + switch \pair32 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_16[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_16[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_16[1:0] 2'00 + end + sync always + update \cnt_1_16 $0\cnt_1_16[1:0] + end + attribute \src "libresoc.v:34418.3-34432.6" + process $proc$libresoc.v:34418$1464 + assign { } { } + assign $0\cnt_1_17[1:0] $1\cnt_1_17[1:0] + attribute \src "libresoc.v:34419.5-34419.29" + switch \initial + attribute \src "libresoc.v:34419.9-34419.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + switch \pair34 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_17[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_17[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_17[1:0] 2'00 + end + sync always + update \cnt_1_17 $0\cnt_1_17[1:0] + end + attribute \src "libresoc.v:34433.3-34447.6" + process $proc$libresoc.v:34433$1465 + assign { } { } + assign $0\cnt_1_18[1:0] $1\cnt_1_18[1:0] + attribute \src "libresoc.v:34434.5-34434.29" + switch \initial + attribute \src "libresoc.v:34434.9-34434.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + switch \pair36 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_18[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_18[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_18[1:0] 2'00 + end + sync always + update \cnt_1_18 $0\cnt_1_18[1:0] + end + attribute \src "libresoc.v:34448.3-34462.6" + process $proc$libresoc.v:34448$1466 + assign { } { } + assign $0\cnt_1_19[1:0] $1\cnt_1_19[1:0] + attribute \src "libresoc.v:34449.5-34449.29" + switch \initial + attribute \src "libresoc.v:34449.9-34449.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + switch \pair38 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_19[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_19[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_19[1:0] 2'00 + end + sync always + update \cnt_1_19 $0\cnt_1_19[1:0] + end + attribute \src "libresoc.v:34463.3-34477.6" + process $proc$libresoc.v:34463$1467 + assign { } { } + assign $0\cnt_1_20[1:0] $1\cnt_1_20[1:0] + attribute \src "libresoc.v:34464.5-34464.29" + switch \initial + attribute \src "libresoc.v:34464.9-34464.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + switch \pair40 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_20[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_20[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_20[1:0] 2'00 + end + sync always + update \cnt_1_20 $0\cnt_1_20[1:0] + end + attribute \src "libresoc.v:34478.3-34492.6" + process $proc$libresoc.v:34478$1468 + assign { } { } + assign $0\cnt_1_21[1:0] $1\cnt_1_21[1:0] + attribute \src "libresoc.v:34479.5-34479.29" + switch \initial + attribute \src "libresoc.v:34479.9-34479.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + switch \pair42 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_21[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_21[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_21[1:0] 2'00 + end + sync always + update \cnt_1_21 $0\cnt_1_21[1:0] + end + attribute \src "libresoc.v:34493.3-34507.6" + process $proc$libresoc.v:34493$1469 + assign { } { } + assign $0\cnt_1_22[1:0] $1\cnt_1_22[1:0] + attribute \src "libresoc.v:34494.5-34494.29" + switch \initial + attribute \src "libresoc.v:34494.9-34494.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + switch \pair44 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_22[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_22[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_22[1:0] 2'00 + end + sync always + update \cnt_1_22 $0\cnt_1_22[1:0] + end + attribute \src "libresoc.v:34508.3-34522.6" + process $proc$libresoc.v:34508$1470 + assign { } { } + assign $0\cnt_1_23[1:0] $1\cnt_1_23[1:0] + attribute \src "libresoc.v:34509.5-34509.29" + switch \initial + attribute \src "libresoc.v:34509.9-34509.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + switch \pair46 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_23[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_23[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_23[1:0] 2'00 + end + sync always + update \cnt_1_23 $0\cnt_1_23[1:0] + end + attribute \src "libresoc.v:34523.3-34537.6" + process $proc$libresoc.v:34523$1471 + assign { } { } + assign $0\cnt_1_24[1:0] $1\cnt_1_24[1:0] + attribute \src "libresoc.v:34524.5-34524.29" + switch \initial + attribute \src "libresoc.v:34524.9-34524.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + switch \pair48 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_24[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_24[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_24[1:0] 2'00 + end + sync always + update \cnt_1_24 $0\cnt_1_24[1:0] + end + attribute \src "libresoc.v:34538.3-34552.6" + process $proc$libresoc.v:34538$1472 + assign { } { } + assign $0\cnt_1_2[1:0] $1\cnt_1_2[1:0] + attribute \src "libresoc.v:34539.5-34539.29" + switch \initial + attribute \src "libresoc.v:34539.9-34539.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + switch \pair4 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_2[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_2[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_2[1:0] 2'00 + end + sync always + update \cnt_1_2 $0\cnt_1_2[1:0] + end + attribute \src "libresoc.v:34553.3-34567.6" + process $proc$libresoc.v:34553$1473 + assign { } { } + assign $0\cnt_1_25[1:0] $1\cnt_1_25[1:0] + attribute \src "libresoc.v:34554.5-34554.29" + switch \initial + attribute \src "libresoc.v:34554.9-34554.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + switch \pair50 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_25[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_25[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_25[1:0] 2'00 + end + sync always + update \cnt_1_25 $0\cnt_1_25[1:0] + end + attribute \src "libresoc.v:34568.3-34582.6" + process $proc$libresoc.v:34568$1474 + assign { } { } + assign $0\cnt_1_26[1:0] $1\cnt_1_26[1:0] + attribute \src "libresoc.v:34569.5-34569.29" + switch \initial + attribute \src "libresoc.v:34569.9-34569.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + switch \pair52 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_26[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_26[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_26[1:0] 2'00 + end + sync always + update \cnt_1_26 $0\cnt_1_26[1:0] + end + attribute \src "libresoc.v:34583.3-34597.6" + process $proc$libresoc.v:34583$1475 + assign { } { } + assign $0\cnt_1_27[1:0] $1\cnt_1_27[1:0] + attribute \src "libresoc.v:34584.5-34584.29" + switch \initial + attribute \src "libresoc.v:34584.9-34584.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + switch \pair54 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_27[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_27[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_27[1:0] 2'00 + end + sync always + update \cnt_1_27 $0\cnt_1_27[1:0] + end + attribute \src "libresoc.v:34598.3-34612.6" + process $proc$libresoc.v:34598$1476 + assign { } { } + assign $0\cnt_1_28[1:0] $1\cnt_1_28[1:0] + attribute \src "libresoc.v:34599.5-34599.29" + switch \initial + attribute \src "libresoc.v:34599.9-34599.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + switch \pair56 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_28[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_28[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_28[1:0] 2'00 + end + sync always + update \cnt_1_28 $0\cnt_1_28[1:0] + end + attribute \src "libresoc.v:34613.3-34627.6" + process $proc$libresoc.v:34613$1477 + assign { } { } + assign $0\cnt_1_29[1:0] $1\cnt_1_29[1:0] + attribute \src "libresoc.v:34614.5-34614.29" + switch \initial + attribute \src "libresoc.v:34614.9-34614.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + switch \pair58 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_29[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_29[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_29[1:0] 2'00 + end + sync always + update \cnt_1_29 $0\cnt_1_29[1:0] + end + attribute \src "libresoc.v:34628.3-34642.6" + process $proc$libresoc.v:34628$1478 + assign { } { } + assign $0\cnt_1_30[1:0] $1\cnt_1_30[1:0] + attribute \src "libresoc.v:34629.5-34629.29" + switch \initial + attribute \src "libresoc.v:34629.9-34629.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + switch \pair60 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_30[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_30[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_30[1:0] 2'00 + end + sync always + update \cnt_1_30 $0\cnt_1_30[1:0] + end + attribute \src "libresoc.v:34643.3-34657.6" + process $proc$libresoc.v:34643$1479 + assign { } { } + assign $0\cnt_1_31[1:0] $1\cnt_1_31[1:0] + attribute \src "libresoc.v:34644.5-34644.29" + switch \initial + attribute \src "libresoc.v:34644.9-34644.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + switch \pair62 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_31[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_31[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_31[1:0] 2'00 + end + sync always + update \cnt_1_31 $0\cnt_1_31[1:0] + end + attribute \src "libresoc.v:34658.3-34677.6" + process $proc$libresoc.v:34658$1480 + assign { } { } + assign $0\cnt_2_0[2:0] $1\cnt_2_0[2:0] + attribute \src "libresoc.v:34659.5-34659.29" + switch \initial + attribute \src "libresoc.v:34659.9-34659.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_2_0[2:0] $2\cnt_2_0[2:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_2_0[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_2_0[2:0] \$5 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_2_0[2:0] { 1'0 \cnt_1_1 } + end + sync always + update \cnt_2_0 $0\cnt_2_0[2:0] + end + attribute \src "libresoc.v:34678.3-34697.6" + process $proc$libresoc.v:34678$1481 + assign { } { } + assign $0\cnt_2_2[2:0] $1\cnt_2_2[2:0] + attribute \src "libresoc.v:34679.5-34679.29" + switch \initial + attribute \src "libresoc.v:34679.9-34679.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + switch \$7 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_2_2[2:0] $2\cnt_2_2[2:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + switch \$9 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_2_2[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_2_2[2:0] \$11 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_2_2[2:0] { 1'0 \cnt_1_3 } + end + sync always + update \cnt_2_2 $0\cnt_2_2[2:0] + end + attribute \src "libresoc.v:34698.3-34717.6" + process $proc$libresoc.v:34698$1482 + assign { } { } + assign $0\cnt_2_4[2:0] $1\cnt_2_4[2:0] + attribute \src "libresoc.v:34699.5-34699.29" + switch \initial + attribute \src "libresoc.v:34699.9-34699.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + switch \$13 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_2_4[2:0] $2\cnt_2_4[2:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + switch \$15 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_2_4[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_2_4[2:0] \$17 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_2_4[2:0] { 1'0 \cnt_1_5 } + end + sync always + update \cnt_2_4 $0\cnt_2_4[2:0] + end + attribute \src "libresoc.v:34718.3-34737.6" + process $proc$libresoc.v:34718$1483 + assign { } { } + assign $0\cnt_2_6[2:0] $1\cnt_2_6[2:0] + attribute \src "libresoc.v:34719.5-34719.29" + switch \initial + attribute \src "libresoc.v:34719.9-34719.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + switch \$19 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_2_6[2:0] $2\cnt_2_6[2:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + switch \$21 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_2_6[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_2_6[2:0] \$23 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_2_6[2:0] { 1'0 \cnt_1_7 } + end + sync always + update \cnt_2_6 $0\cnt_2_6[2:0] + end + attribute \src "libresoc.v:34738.3-34757.6" + process $proc$libresoc.v:34738$1484 + assign { } { } + assign $0\cnt_2_8[2:0] $1\cnt_2_8[2:0] + attribute \src "libresoc.v:34739.5-34739.29" + switch \initial + attribute \src "libresoc.v:34739.9-34739.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + switch \$25 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_2_8[2:0] $2\cnt_2_8[2:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + switch \$27 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_2_8[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_2_8[2:0] \$29 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_2_8[2:0] { 1'0 \cnt_1_9 } + end + sync always + update \cnt_2_8 $0\cnt_2_8[2:0] + end + attribute \src "libresoc.v:34758.3-34777.6" + process $proc$libresoc.v:34758$1485 + assign { } { } + assign $0\cnt_2_10[2:0] $1\cnt_2_10[2:0] + attribute \src "libresoc.v:34759.5-34759.29" + switch \initial + attribute \src "libresoc.v:34759.9-34759.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + switch \$31 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_2_10[2:0] $2\cnt_2_10[2:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + switch \$33 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_2_10[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_2_10[2:0] \$35 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_2_10[2:0] { 1'0 \cnt_1_11 } + end + sync always + update \cnt_2_10 $0\cnt_2_10[2:0] + end + attribute \src "libresoc.v:34778.3-34792.6" + process $proc$libresoc.v:34778$1486 + assign { } { } + assign $0\cnt_1_3[1:0] $1\cnt_1_3[1:0] + attribute \src "libresoc.v:34779.5-34779.29" + switch \initial + attribute \src "libresoc.v:34779.9-34779.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + switch \pair6 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_3[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_3[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_3[1:0] 2'00 + end + sync always + update \cnt_1_3 $0\cnt_1_3[1:0] + end + attribute \src "libresoc.v:34793.3-34812.6" + process $proc$libresoc.v:34793$1487 + assign { } { } + assign $0\cnt_2_12[2:0] $1\cnt_2_12[2:0] + attribute \src "libresoc.v:34794.5-34794.29" + switch \initial + attribute \src "libresoc.v:34794.9-34794.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + switch \$37 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_2_12[2:0] $2\cnt_2_12[2:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + switch \$39 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_2_12[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_2_12[2:0] \$41 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_2_12[2:0] { 1'0 \cnt_1_13 } + end + sync always + update \cnt_2_12 $0\cnt_2_12[2:0] + end + attribute \src "libresoc.v:34813.3-34832.6" + process $proc$libresoc.v:34813$1488 + assign { } { } + assign $0\cnt_2_14[2:0] $1\cnt_2_14[2:0] + attribute \src "libresoc.v:34814.5-34814.29" + switch \initial + attribute \src "libresoc.v:34814.9-34814.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + switch \$43 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_2_14[2:0] $2\cnt_2_14[2:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + switch \$45 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_2_14[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_2_14[2:0] \$47 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_2_14[2:0] { 1'0 \cnt_1_15 } + end + sync always + update \cnt_2_14 $0\cnt_2_14[2:0] + end + attribute \src "libresoc.v:34833.3-34852.6" + process $proc$libresoc.v:34833$1489 + assign { } { } + assign $0\cnt_2_16[2:0] $1\cnt_2_16[2:0] + attribute \src "libresoc.v:34834.5-34834.29" + switch \initial + attribute \src "libresoc.v:34834.9-34834.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + switch \$49 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_2_16[2:0] $2\cnt_2_16[2:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + switch \$51 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_2_16[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_2_16[2:0] \$53 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_2_16[2:0] { 1'0 \cnt_1_17 } + end + sync always + update \cnt_2_16 $0\cnt_2_16[2:0] + end + attribute \src "libresoc.v:34853.3-34872.6" + process $proc$libresoc.v:34853$1490 + assign { } { } + assign $0\cnt_2_18[2:0] $1\cnt_2_18[2:0] + attribute \src "libresoc.v:34854.5-34854.29" + switch \initial + attribute \src "libresoc.v:34854.9-34854.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + switch \$55 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_2_18[2:0] $2\cnt_2_18[2:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + switch \$57 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_2_18[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_2_18[2:0] \$59 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_2_18[2:0] { 1'0 \cnt_1_19 } + end + sync always + update \cnt_2_18 $0\cnt_2_18[2:0] + end + attribute \src "libresoc.v:34873.3-34892.6" + process $proc$libresoc.v:34873$1491 + assign { } { } + assign $0\cnt_2_20[2:0] $1\cnt_2_20[2:0] + attribute \src "libresoc.v:34874.5-34874.29" + switch \initial + attribute \src "libresoc.v:34874.9-34874.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + switch \$61 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_2_20[2:0] $2\cnt_2_20[2:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + switch \$63 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_2_20[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_2_20[2:0] \$65 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_2_20[2:0] { 1'0 \cnt_1_21 } + end + sync always + update \cnt_2_20 $0\cnt_2_20[2:0] + end + attribute \src "libresoc.v:34893.3-34912.6" + process $proc$libresoc.v:34893$1492 + assign { } { } + assign $0\cnt_2_22[2:0] $1\cnt_2_22[2:0] + attribute \src "libresoc.v:34894.5-34894.29" + switch \initial + attribute \src "libresoc.v:34894.9-34894.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + switch \$67 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_2_22[2:0] $2\cnt_2_22[2:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + switch \$69 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_2_22[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_2_22[2:0] \$71 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_2_22[2:0] { 1'0 \cnt_1_23 } + end + sync always + update \cnt_2_22 $0\cnt_2_22[2:0] + end + attribute \src "libresoc.v:34913.3-34932.6" + process $proc$libresoc.v:34913$1493 + assign { } { } + assign $0\cnt_2_24[2:0] $1\cnt_2_24[2:0] + attribute \src "libresoc.v:34914.5-34914.29" + switch \initial + attribute \src "libresoc.v:34914.9-34914.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + switch \$73 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_2_24[2:0] $2\cnt_2_24[2:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + switch \$75 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_2_24[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_2_24[2:0] \$77 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_2_24[2:0] { 1'0 \cnt_1_25 } + end + sync always + update \cnt_2_24 $0\cnt_2_24[2:0] + end + attribute \src "libresoc.v:34933.3-34952.6" + process $proc$libresoc.v:34933$1494 + assign { } { } + assign $0\cnt_2_26[2:0] $1\cnt_2_26[2:0] + attribute \src "libresoc.v:34934.5-34934.29" + switch \initial + attribute \src "libresoc.v:34934.9-34934.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + switch \$79 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_2_26[2:0] $2\cnt_2_26[2:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + switch \$81 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_2_26[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_2_26[2:0] \$83 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_2_26[2:0] { 1'0 \cnt_1_27 } + end + sync always + update \cnt_2_26 $0\cnt_2_26[2:0] + end + attribute \src "libresoc.v:34953.3-34972.6" + process $proc$libresoc.v:34953$1495 + assign { } { } + assign $0\cnt_2_28[2:0] $1\cnt_2_28[2:0] + attribute \src "libresoc.v:34954.5-34954.29" + switch \initial + attribute \src "libresoc.v:34954.9-34954.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + switch \$85 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_2_28[2:0] $2\cnt_2_28[2:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + switch \$87 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_2_28[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_2_28[2:0] \$89 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_2_28[2:0] { 1'0 \cnt_1_29 } + end + sync always + update \cnt_2_28 $0\cnt_2_28[2:0] + end + attribute \src "libresoc.v:34973.3-34992.6" + process $proc$libresoc.v:34973$1496 + assign { } { } + assign $0\cnt_2_30[2:0] $1\cnt_2_30[2:0] + attribute \src "libresoc.v:34974.5-34974.29" + switch \initial + attribute \src "libresoc.v:34974.9-34974.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + switch \$91 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_2_30[2:0] $2\cnt_2_30[2:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + switch \$93 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_2_30[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_2_30[2:0] \$95 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_2_30[2:0] { 1'0 \cnt_1_31 } + end + sync always + update \cnt_2_30 $0\cnt_2_30[2:0] + end + attribute \src "libresoc.v:34993.3-35012.6" + process $proc$libresoc.v:34993$1497 + assign { } { } + assign $0\cnt_3_0[3:0] $1\cnt_3_0[3:0] + attribute \src "libresoc.v:34994.5-34994.29" + switch \initial + attribute \src "libresoc.v:34994.9-34994.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + switch \$97 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_3_0[3:0] $2\cnt_3_0[3:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + switch \$99 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_3_0[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_3_0[3:0] \$101 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_3_0[3:0] { 1'0 \cnt_2_2 } + end + sync always + update \cnt_3_0 $0\cnt_3_0[3:0] + end + attribute \src "libresoc.v:35013.3-35032.6" + process $proc$libresoc.v:35013$1498 + assign { } { } + assign $0\cnt_3_2[3:0] $1\cnt_3_2[3:0] + attribute \src "libresoc.v:35014.5-35014.29" + switch \initial + attribute \src "libresoc.v:35014.9-35014.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + switch \$103 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_3_2[3:0] $2\cnt_3_2[3:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + switch \$105 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_3_2[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_3_2[3:0] \$107 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_3_2[3:0] { 1'0 \cnt_2_6 } + end + sync always + update \cnt_3_2 $0\cnt_3_2[3:0] + end + attribute \src "libresoc.v:35033.3-35052.6" + process $proc$libresoc.v:35033$1499 + assign { } { } + assign $0\cnt_3_4[3:0] $1\cnt_3_4[3:0] + attribute \src "libresoc.v:35034.5-35034.29" + switch \initial + attribute \src "libresoc.v:35034.9-35034.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + switch \$109 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_3_4[3:0] $2\cnt_3_4[3:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + switch \$111 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_3_4[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_3_4[3:0] \$113 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_3_4[3:0] { 1'0 \cnt_2_10 } + end + sync always + update \cnt_3_4 $0\cnt_3_4[3:0] + end + attribute \src "libresoc.v:35053.3-35072.6" + process $proc$libresoc.v:35053$1500 + assign { } { } + assign $0\cnt_3_6[3:0] $1\cnt_3_6[3:0] + attribute \src "libresoc.v:35054.5-35054.29" + switch \initial + attribute \src "libresoc.v:35054.9-35054.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + switch \$115 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_3_6[3:0] $2\cnt_3_6[3:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + switch \$117 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_3_6[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_3_6[3:0] \$119 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_3_6[3:0] { 1'0 \cnt_2_14 } + end + sync always + update \cnt_3_6 $0\cnt_3_6[3:0] + end + attribute \src "libresoc.v:35073.3-35092.6" + process $proc$libresoc.v:35073$1501 + assign { } { } + assign $0\cnt_3_8[3:0] $1\cnt_3_8[3:0] + attribute \src "libresoc.v:35074.5-35074.29" + switch \initial + attribute \src "libresoc.v:35074.9-35074.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + switch \$121 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_3_8[3:0] $2\cnt_3_8[3:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + switch \$123 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_3_8[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_3_8[3:0] \$125 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_3_8[3:0] { 1'0 \cnt_2_18 } + end + sync always + update \cnt_3_8 $0\cnt_3_8[3:0] + end + attribute \src "libresoc.v:35093.3-35112.6" + process $proc$libresoc.v:35093$1502 + assign { } { } + assign $0\cnt_3_10[3:0] $1\cnt_3_10[3:0] + attribute \src "libresoc.v:35094.5-35094.29" + switch \initial + attribute \src "libresoc.v:35094.9-35094.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + switch \$127 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_3_10[3:0] $2\cnt_3_10[3:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + switch \$129 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_3_10[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_3_10[3:0] \$131 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_3_10[3:0] { 1'0 \cnt_2_22 } + end + sync always + update \cnt_3_10 $0\cnt_3_10[3:0] + end + attribute \src "libresoc.v:35113.3-35132.6" + process $proc$libresoc.v:35113$1503 + assign { } { } + assign $0\cnt_3_12[3:0] $1\cnt_3_12[3:0] + attribute \src "libresoc.v:35114.5-35114.29" + switch \initial + attribute \src "libresoc.v:35114.9-35114.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + switch \$133 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_3_12[3:0] $2\cnt_3_12[3:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + switch \$135 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_3_12[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_3_12[3:0] \$137 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_3_12[3:0] { 1'0 \cnt_2_26 } + end + sync always + update \cnt_3_12 $0\cnt_3_12[3:0] + end + attribute \src "libresoc.v:35133.3-35152.6" + process $proc$libresoc.v:35133$1504 + assign { } { } + assign $0\cnt_3_14[3:0] $1\cnt_3_14[3:0] + attribute \src "libresoc.v:35134.5-35134.29" + switch \initial + attribute \src "libresoc.v:35134.9-35134.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + switch \$139 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_3_14[3:0] $2\cnt_3_14[3:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + switch \$141 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_3_14[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_3_14[3:0] \$143 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_3_14[3:0] { 1'0 \cnt_2_30 } + end + sync always + update \cnt_3_14 $0\cnt_3_14[3:0] + end + attribute \src "libresoc.v:35153.3-35172.6" + process $proc$libresoc.v:35153$1505 + assign { } { } + assign $0\cnt_4_0[4:0] $1\cnt_4_0[4:0] + attribute \src "libresoc.v:35154.5-35154.29" + switch \initial + attribute \src "libresoc.v:35154.9-35154.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + switch \$145 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_4_0[4:0] $2\cnt_4_0[4:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + switch \$147 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_4_0[4:0] 5'10000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_4_0[4:0] \$149 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_4_0[4:0] { 1'0 \cnt_3_2 } + end + sync always + update \cnt_4_0 $0\cnt_4_0[4:0] + end + attribute \src "libresoc.v:35173.3-35192.6" + process $proc$libresoc.v:35173$1506 + assign { } { } + assign $0\cnt_4_2[4:0] $1\cnt_4_2[4:0] + attribute \src "libresoc.v:35174.5-35174.29" + switch \initial + attribute \src "libresoc.v:35174.9-35174.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + switch \$151 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_4_2[4:0] $2\cnt_4_2[4:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + switch \$153 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_4_2[4:0] 5'10000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_4_2[4:0] \$155 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_4_2[4:0] { 1'0 \cnt_3_6 } + end + sync always + update \cnt_4_2 $0\cnt_4_2[4:0] + end + attribute \src "libresoc.v:35193.3-35207.6" + process $proc$libresoc.v:35193$1507 + assign { } { } + assign $0\cnt_1_4[1:0] $1\cnt_1_4[1:0] + attribute \src "libresoc.v:35194.5-35194.29" + switch \initial + attribute \src "libresoc.v:35194.9-35194.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + switch \pair8 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_4[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_4[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_4[1:0] 2'00 + end + sync always + update \cnt_1_4 $0\cnt_1_4[1:0] + end + attribute \src "libresoc.v:35208.3-35227.6" + process $proc$libresoc.v:35208$1508 + assign { } { } + assign $0\cnt_4_4[4:0] $1\cnt_4_4[4:0] + attribute \src "libresoc.v:35209.5-35209.29" + switch \initial + attribute \src "libresoc.v:35209.9-35209.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + switch \$157 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_4_4[4:0] $2\cnt_4_4[4:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + switch \$159 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_4_4[4:0] 5'10000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_4_4[4:0] \$161 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_4_4[4:0] { 1'0 \cnt_3_10 } + end + sync always + update \cnt_4_4 $0\cnt_4_4[4:0] + end + attribute \src "libresoc.v:35228.3-35247.6" + process $proc$libresoc.v:35228$1509 + assign { } { } + assign $0\cnt_4_6[4:0] $1\cnt_4_6[4:0] + attribute \src "libresoc.v:35229.5-35229.29" + switch \initial + attribute \src "libresoc.v:35229.9-35229.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + switch \$163 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_4_6[4:0] $2\cnt_4_6[4:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + switch \$165 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_4_6[4:0] 5'10000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_4_6[4:0] \$167 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_4_6[4:0] { 1'0 \cnt_3_14 } + end + sync always + update \cnt_4_6 $0\cnt_4_6[4:0] + end + attribute \src "libresoc.v:35248.3-35267.6" + process $proc$libresoc.v:35248$1510 + assign { } { } + assign $0\cnt_5_0[5:0] $1\cnt_5_0[5:0] + attribute \src "libresoc.v:35249.5-35249.29" + switch \initial + attribute \src "libresoc.v:35249.9-35249.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + switch \$169 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_5_0[5:0] $2\cnt_5_0[5:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + switch \$171 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_5_0[5:0] 6'100000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_5_0[5:0] \$173 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_5_0[5:0] { 1'0 \cnt_4_2 } + end + sync always + update \cnt_5_0 $0\cnt_5_0[5:0] + end + attribute \src "libresoc.v:35268.3-35287.6" + process $proc$libresoc.v:35268$1511 + assign { } { } + assign $0\cnt_5_2[5:0] $1\cnt_5_2[5:0] + attribute \src "libresoc.v:35269.5-35269.29" + switch \initial + attribute \src "libresoc.v:35269.9-35269.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + switch \$175 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_5_2[5:0] $2\cnt_5_2[5:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + switch \$177 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_5_2[5:0] 6'100000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_5_2[5:0] \$179 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_5_2[5:0] { 1'0 \cnt_4_6 } + end + sync always + update \cnt_5_2 $0\cnt_5_2[5:0] + end + attribute \src "libresoc.v:35288.3-35307.6" + process $proc$libresoc.v:35288$1512 + assign { } { } + assign $0\cnt_6_0[6:0] $1\cnt_6_0[6:0] + attribute \src "libresoc.v:35289.5-35289.29" + switch \initial + attribute \src "libresoc.v:35289.9-35289.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + switch \$181 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_6_0[6:0] $2\cnt_6_0[6:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + switch \$183 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_6_0[6:0] 7'1000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_6_0[6:0] \$185 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_6_0[6:0] { 1'0 \cnt_5_2 } + end + sync always + update \cnt_6_0 $0\cnt_6_0[6:0] + end + connect \$9 $eq$libresoc.v:34115$1357_Y + connect \$99 $eq$libresoc.v:34116$1358_Y + connect \$101 $pos$libresoc.v:34117$1359_Y + connect \$103 $eq$libresoc.v:34118$1360_Y + connect \$105 $eq$libresoc.v:34119$1361_Y + connect \$107 $pos$libresoc.v:34120$1362_Y + connect \$109 $eq$libresoc.v:34121$1363_Y + connect \$111 $eq$libresoc.v:34122$1364_Y + connect \$113 $pos$libresoc.v:34123$1365_Y + connect \$115 $eq$libresoc.v:34124$1366_Y + connect \$117 $eq$libresoc.v:34125$1367_Y + connect \$11 $pos$libresoc.v:34126$1368_Y + connect \$119 $pos$libresoc.v:34127$1369_Y + connect \$121 $eq$libresoc.v:34128$1370_Y + connect \$123 $eq$libresoc.v:34129$1371_Y + connect \$125 $pos$libresoc.v:34130$1372_Y + connect \$127 $eq$libresoc.v:34131$1373_Y + connect \$129 $eq$libresoc.v:34132$1374_Y + connect \$131 $pos$libresoc.v:34133$1375_Y + connect \$133 $eq$libresoc.v:34134$1376_Y + connect \$135 $eq$libresoc.v:34135$1377_Y + connect \$137 $pos$libresoc.v:34136$1378_Y + connect \$13 $eq$libresoc.v:34137$1379_Y + connect \$139 $eq$libresoc.v:34138$1380_Y + connect \$141 $eq$libresoc.v:34139$1381_Y + connect \$143 $pos$libresoc.v:34140$1382_Y + connect \$145 $eq$libresoc.v:34141$1383_Y + connect \$147 $eq$libresoc.v:34142$1384_Y + connect \$149 $pos$libresoc.v:34143$1385_Y + connect \$151 $eq$libresoc.v:34144$1386_Y + connect \$153 $eq$libresoc.v:34145$1387_Y + connect \$155 $pos$libresoc.v:34146$1388_Y + connect \$157 $eq$libresoc.v:34147$1389_Y + connect \$15 $eq$libresoc.v:34148$1390_Y + connect \$159 $eq$libresoc.v:34149$1391_Y + connect \$161 $pos$libresoc.v:34150$1392_Y + connect \$163 $eq$libresoc.v:34151$1393_Y + connect \$165 $eq$libresoc.v:34152$1394_Y + connect \$167 $pos$libresoc.v:34153$1395_Y + connect \$169 $eq$libresoc.v:34154$1396_Y + connect \$171 $eq$libresoc.v:34155$1397_Y + connect \$173 $pos$libresoc.v:34156$1398_Y + connect \$175 $eq$libresoc.v:34157$1399_Y + connect \$177 $eq$libresoc.v:34158$1400_Y + connect \$17 $pos$libresoc.v:34159$1401_Y + connect \$179 $pos$libresoc.v:34160$1402_Y + connect \$181 $eq$libresoc.v:34161$1403_Y + connect \$183 $eq$libresoc.v:34162$1404_Y + connect \$185 $pos$libresoc.v:34163$1405_Y + connect \$1 $eq$libresoc.v:34164$1406_Y + connect \$19 $eq$libresoc.v:34165$1407_Y + connect \$21 $eq$libresoc.v:34166$1408_Y + connect \$23 $pos$libresoc.v:34167$1409_Y + connect \$25 $eq$libresoc.v:34168$1410_Y + connect \$27 $eq$libresoc.v:34169$1411_Y + connect \$29 $pos$libresoc.v:34170$1412_Y + connect \$31 $eq$libresoc.v:34171$1413_Y + connect \$33 $eq$libresoc.v:34172$1414_Y + connect \$35 $pos$libresoc.v:34173$1415_Y + connect \$37 $eq$libresoc.v:34174$1416_Y + connect \$3 $eq$libresoc.v:34175$1417_Y + connect \$39 $eq$libresoc.v:34176$1418_Y + connect \$41 $pos$libresoc.v:34177$1419_Y + connect \$43 $eq$libresoc.v:34178$1420_Y + connect \$45 $eq$libresoc.v:34179$1421_Y + connect \$47 $pos$libresoc.v:34180$1422_Y + connect \$49 $eq$libresoc.v:34181$1423_Y + connect \$51 $eq$libresoc.v:34182$1424_Y + connect \$53 $pos$libresoc.v:34183$1425_Y + connect \$55 $eq$libresoc.v:34184$1426_Y + connect \$57 $eq$libresoc.v:34185$1427_Y + connect \$5 $pos$libresoc.v:34186$1428_Y + connect \$59 $pos$libresoc.v:34187$1429_Y + connect \$61 $eq$libresoc.v:34188$1430_Y + connect \$63 $eq$libresoc.v:34189$1431_Y + connect \$65 $pos$libresoc.v:34190$1432_Y + connect \$67 $eq$libresoc.v:34191$1433_Y + connect \$69 $eq$libresoc.v:34192$1434_Y + connect \$71 $pos$libresoc.v:34193$1435_Y + connect \$73 $eq$libresoc.v:34194$1436_Y + connect \$75 $eq$libresoc.v:34195$1437_Y + connect \$77 $pos$libresoc.v:34196$1438_Y + connect \$7 $eq$libresoc.v:34197$1439_Y + connect \$79 $eq$libresoc.v:34198$1440_Y + connect \$81 $eq$libresoc.v:34199$1441_Y + connect \$83 $pos$libresoc.v:34200$1442_Y + connect \$85 $eq$libresoc.v:34201$1443_Y + connect \$87 $eq$libresoc.v:34202$1444_Y + connect \$89 $pos$libresoc.v:34203$1445_Y + connect \$91 $eq$libresoc.v:34204$1446_Y + connect \$93 $eq$libresoc.v:34205$1447_Y + connect \$95 $pos$libresoc.v:34206$1448_Y + connect \$97 $eq$libresoc.v:34207$1449_Y + connect \lz \cnt_6_0 + connect \pair62 \sig_in [63:62] + connect \pair60 \sig_in [61:60] + connect \pair58 \sig_in [59:58] + connect \pair56 \sig_in [57:56] + connect \pair54 \sig_in [55:54] + connect \pair52 \sig_in [53:52] + connect \pair50 \sig_in [51:50] + connect \pair48 \sig_in [49:48] + connect \pair46 \sig_in [47:46] + connect \pair44 \sig_in [45:44] + connect \pair42 \sig_in [43:42] + connect \pair40 \sig_in [41:40] + connect \pair38 \sig_in [39:38] + connect \pair36 \sig_in [37:36] + connect \pair34 \sig_in [35:34] + connect \pair32 \sig_in [33:32] + connect \pair30 \sig_in [31:30] + connect \pair28 \sig_in [29:28] + connect \pair26 \sig_in [27:26] + connect \pair24 \sig_in [25:24] + connect \pair22 \sig_in [23:22] + connect \pair20 \sig_in [21:20] + connect \pair18 \sig_in [19:18] + connect \pair16 \sig_in [17:16] + connect \pair14 \sig_in [15:14] + connect \pair12 \sig_in [13:12] + connect \pair10 \sig_in [11:10] + connect \pair8 \sig_in [9:8] + connect \pair6 \sig_in [7:6] + connect \pair4 \sig_in [5:4] + connect \pair2 \sig_in [3:2] + connect \pair0 \sig_in [1:0] +end +attribute \src "libresoc.v:35345.1-48039.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core" +attribute \generator "nMigen" +module \core + attribute \src "libresoc.v:45017.3-45037.6" + wire $0\core_terminate_o$next[0:0]$2597 + attribute \src "libresoc.v:41976.3-41977.49" + wire $0\core_terminate_o[0:0] + attribute \src "libresoc.v:44888.3-44978.6" + wire $0\corebusy_o[0:0] + attribute \src "libresoc.v:44833.3-44859.6" + wire width 2 $0\counter$next[1:0]$2571 + attribute \src "libresoc.v:41978.3-41979.31" + wire width 2 $0\counter[1:0] + attribute \src "libresoc.v:45318.3-45326.6" + wire $0\dp_CR_cr_a_branch0_1$next[0:0]$2653 + attribute \src "libresoc.v:41912.3-41913.57" + wire $0\dp_CR_cr_a_branch0_1[0:0] + attribute \src "libresoc.v:45299.3-45307.6" + wire $0\dp_CR_cr_a_cr0_0$next[0:0]$2647 + attribute \src "libresoc.v:41914.3-41915.49" + wire $0\dp_CR_cr_a_cr0_0[0:0] + attribute \src "libresoc.v:45337.3-45345.6" + wire $0\dp_CR_cr_b_cr0_0$next[0:0]$2659 + attribute \src "libresoc.v:41910.3-41911.49" + wire $0\dp_CR_cr_b_cr0_0[0:0] + attribute \src "libresoc.v:45386.3-45394.6" + wire $0\dp_CR_cr_c_cr0_0$next[0:0]$2666 + attribute \src "libresoc.v:41908.3-41909.49" + wire $0\dp_CR_cr_c_cr0_0[0:0] + attribute \src "libresoc.v:45250.3-45258.6" + wire $0\dp_CR_full_cr_cr0_0$next[0:0]$2640 + attribute \src "libresoc.v:41916.3-41917.55" + wire $0\dp_CR_full_cr_cr0_0[0:0] + attribute \src "libresoc.v:45405.3-45413.6" + wire $0\dp_FAST_fast1_branch0_0$next[0:0]$2672 + attribute \src "libresoc.v:41906.3-41907.63" + wire $0\dp_FAST_fast1_branch0_0[0:0] + attribute \src "libresoc.v:45472.3-45480.6" + wire $0\dp_FAST_fast1_spr0_2$next[0:0]$2685 + attribute \src "libresoc.v:41902.3-41903.57" + wire $0\dp_FAST_fast1_spr0_2[0:0] + attribute \src "libresoc.v:45424.3-45432.6" + wire $0\dp_FAST_fast1_trap0_1$next[0:0]$2678 + attribute \src "libresoc.v:41904.3-41905.59" + wire $0\dp_FAST_fast1_trap0_1[0:0] + attribute \src "libresoc.v:45491.3-45499.6" + wire $0\dp_FAST_fast2_branch0_0$next[0:0]$2691 + attribute \src "libresoc.v:41900.3-41901.63" + wire $0\dp_FAST_fast2_branch0_0[0:0] + attribute \src "libresoc.v:45539.3-45547.6" + wire $0\dp_FAST_fast2_trap0_1$next[0:0]$2698 + attribute \src "libresoc.v:41898.3-41899.59" + wire $0\dp_FAST_fast2_trap0_1[0:0] + attribute \src "libresoc.v:44472.3-44480.6" + wire $0\dp_INT_ra_alu0_0$next[0:0]$2463 + attribute \src "libresoc.v:41974.3-41975.49" + wire $0\dp_INT_ra_alu0_0[0:0] + attribute \src "libresoc.v:44491.3-44499.6" + wire $0\dp_INT_ra_cr0_1$next[0:0]$2467 + attribute \src "libresoc.v:41972.3-41973.47" + wire $0\dp_INT_ra_cr0_1[0:0] + attribute \src "libresoc.v:44567.3-44575.6" + wire $0\dp_INT_ra_div0_5$next[0:0]$2491 + attribute \src "libresoc.v:41964.3-41965.49" + wire $0\dp_INT_ra_div0_5[0:0] + attribute \src "libresoc.v:44624.3-44632.6" + wire $0\dp_INT_ra_ldst0_8$next[0:0]$2509 + attribute \src "libresoc.v:41958.3-41959.51" + wire $0\dp_INT_ra_ldst0_8[0:0] + attribute \src "libresoc.v:44529.3-44537.6" + wire $0\dp_INT_ra_logical0_3$next[0:0]$2479 + attribute \src "libresoc.v:41968.3-41969.57" + wire $0\dp_INT_ra_logical0_3[0:0] + attribute \src "libresoc.v:44586.3-44594.6" + wire $0\dp_INT_ra_mul0_6$next[0:0]$2497 + attribute \src "libresoc.v:41962.3-41963.49" + wire $0\dp_INT_ra_mul0_6[0:0] + attribute \src "libresoc.v:44605.3-44613.6" + wire $0\dp_INT_ra_shiftrot0_7$next[0:0]$2503 + attribute \src "libresoc.v:41960.3-41961.59" + wire $0\dp_INT_ra_shiftrot0_7[0:0] + attribute \src "libresoc.v:44548.3-44556.6" + wire $0\dp_INT_ra_spr0_4$next[0:0]$2485 + attribute \src "libresoc.v:41966.3-41967.49" + wire $0\dp_INT_ra_spr0_4[0:0] + attribute \src "libresoc.v:44510.3-44518.6" + wire $0\dp_INT_ra_trap0_2$next[0:0]$2473 + attribute \src "libresoc.v:41970.3-41971.51" + wire $0\dp_INT_ra_trap0_2[0:0] + attribute \src "libresoc.v:44643.3-44651.6" + wire $0\dp_INT_rb_alu0_0$next[0:0]$2515 + attribute \src "libresoc.v:41956.3-41957.49" + wire $0\dp_INT_rb_alu0_0[0:0] + attribute \src "libresoc.v:44662.3-44670.6" + wire $0\dp_INT_rb_cr0_1$next[0:0]$2519 + attribute \src "libresoc.v:41954.3-41955.47" + wire $0\dp_INT_rb_cr0_1[0:0] + attribute \src "libresoc.v:44719.3-44727.6" + wire $0\dp_INT_rb_div0_4$next[0:0]$2537 + attribute \src "libresoc.v:41948.3-41949.49" + wire $0\dp_INT_rb_div0_4[0:0] + attribute \src "libresoc.v:44776.3-44784.6" + wire $0\dp_INT_rb_ldst0_7$next[0:0]$2555 + attribute \src "libresoc.v:41942.3-41943.51" + wire $0\dp_INT_rb_ldst0_7[0:0] + attribute \src "libresoc.v:44700.3-44708.6" + wire $0\dp_INT_rb_logical0_3$next[0:0]$2531 + attribute \src "libresoc.v:41950.3-41951.57" + wire $0\dp_INT_rb_logical0_3[0:0] + attribute \src "libresoc.v:44738.3-44746.6" + wire $0\dp_INT_rb_mul0_5$next[0:0]$2543 + attribute \src "libresoc.v:41946.3-41947.49" + wire $0\dp_INT_rb_mul0_5[0:0] + attribute \src "libresoc.v:44757.3-44765.6" + wire $0\dp_INT_rb_shiftrot0_6$next[0:0]$2549 + attribute \src "libresoc.v:41944.3-41945.59" + wire $0\dp_INT_rb_shiftrot0_6[0:0] + attribute \src "libresoc.v:44681.3-44689.6" + wire $0\dp_INT_rb_trap0_2$next[0:0]$2525 + attribute \src "libresoc.v:41952.3-41953.51" + wire $0\dp_INT_rb_trap0_2[0:0] + attribute \src "libresoc.v:44814.3-44822.6" + wire $0\dp_INT_rc_ldst0_1$next[0:0]$2565 + attribute \src "libresoc.v:41938.3-41939.51" + wire $0\dp_INT_rc_ldst0_1[0:0] + attribute \src "libresoc.v:44795.3-44803.6" + wire $0\dp_INT_rc_shiftrot0_0$next[0:0]$2561 + attribute \src "libresoc.v:41940.3-41941.59" + wire $0\dp_INT_rc_shiftrot0_0[0:0] + attribute \src "libresoc.v:45587.3-45595.6" + wire $0\dp_SPR_spr1_spr0_0$next[0:0]$2705 + attribute \src "libresoc.v:41896.3-41897.53" + wire $0\dp_SPR_spr1_spr0_0[0:0] + attribute \src "libresoc.v:45115.3-45123.6" + wire $0\dp_XER_xer_ca_alu0_0$next[0:0]$2618 + attribute \src "libresoc.v:41924.3-41925.57" + wire $0\dp_XER_xer_ca_alu0_0[0:0] + attribute \src "libresoc.v:45182.3-45190.6" + wire $0\dp_XER_xer_ca_shiftrot0_2$next[0:0]$2629 + attribute \src "libresoc.v:41920.3-41921.67" + wire $0\dp_XER_xer_ca_shiftrot0_2[0:0] + attribute \src "libresoc.v:45163.3-45171.6" + wire $0\dp_XER_xer_ca_spr0_1$next[0:0]$2625 + attribute \src "libresoc.v:41922.3-41923.57" + wire $0\dp_XER_xer_ca_spr0_1[0:0] + attribute \src "libresoc.v:45231.3-45239.6" + wire $0\dp_XER_xer_ov_spr0_0$next[0:0]$2634 + attribute \src "libresoc.v:41918.3-41919.57" + wire $0\dp_XER_xer_ov_spr0_0[0:0] + attribute \src "libresoc.v:44860.3-44868.6" + wire $0\dp_XER_xer_so_alu0_0$next[0:0]$2577 + attribute \src "libresoc.v:41936.3-41937.57" + wire $0\dp_XER_xer_so_alu0_0[0:0] + attribute \src "libresoc.v:45008.3-45016.6" + wire $0\dp_XER_xer_so_div0_3$next[0:0]$2594 + attribute \src "libresoc.v:41930.3-41931.57" + wire $0\dp_XER_xer_so_div0_3[0:0] + attribute \src "libresoc.v:44879.3-44887.6" + wire $0\dp_XER_xer_so_logical0_1$next[0:0]$2583 + attribute \src "libresoc.v:41934.3-41935.65" + wire $0\dp_XER_xer_so_logical0_1[0:0] + attribute \src "libresoc.v:45048.3-45056.6" + wire $0\dp_XER_xer_so_mul0_4$next[0:0]$2605 + attribute \src "libresoc.v:41928.3-41929.57" + wire $0\dp_XER_xer_so_mul0_4[0:0] + attribute \src "libresoc.v:45067.3-45075.6" + wire $0\dp_XER_xer_so_shiftrot0_5$next[0:0]$2611 + attribute \src "libresoc.v:41926.3-41927.67" + wire $0\dp_XER_xer_so_shiftrot0_5[0:0] + attribute \src "libresoc.v:44989.3-44997.6" + wire $0\dp_XER_xer_so_spr0_2$next[0:0]$2590 + attribute \src "libresoc.v:41932.3-41933.57" + wire $0\dp_XER_xer_so_spr0_2[0:0] + attribute \src "libresoc.v:46839.3-46867.6" + wire $0\fus_cu_issue_i$10[0:0]$2869 + attribute \src "libresoc.v:47335.3-47363.6" + wire $0\fus_cu_issue_i$13[0:0]$2894 + attribute \src "libresoc.v:42720.3-42748.6" + wire $0\fus_cu_issue_i$16[0:0]$2363 + attribute \src "libresoc.v:43216.3-43244.6" + wire $0\fus_cu_issue_i$19[0:0]$2388 + attribute \src "libresoc.v:43538.3-43566.6" + wire $0\fus_cu_issue_i$22[0:0]$2407 + attribute \src "libresoc.v:43976.3-44004.6" + wire $0\fus_cu_issue_i$25[0:0]$2430 + attribute \src "libresoc.v:44414.3-44442.6" + wire $0\fus_cu_issue_i$28[0:0]$2453 + attribute \src "libresoc.v:46107.3-46135.6" + wire $0\fus_cu_issue_i$4[0:0]$2774 + attribute \src "libresoc.v:46504.3-46532.6" + wire $0\fus_cu_issue_i$7[0:0]$2836 + attribute \src "libresoc.v:45899.3-45927.6" + wire $0\fus_cu_issue_i[0:0] + attribute \src "libresoc.v:46868.3-46896.6" + wire width 4 $0\fus_cu_rdmaskn_i$12[3:0]$2874 + attribute \src "libresoc.v:47364.3-47392.6" + wire width 3 $0\fus_cu_rdmaskn_i$15[2:0]$2899 + attribute \src "libresoc.v:42749.3-42777.6" + wire width 6 $0\fus_cu_rdmaskn_i$18[5:0]$2368 + attribute \src "libresoc.v:43245.3-43273.6" + wire width 3 $0\fus_cu_rdmaskn_i$21[2:0]$2393 + attribute \src "libresoc.v:43567.3-43595.6" + wire width 3 $0\fus_cu_rdmaskn_i$24[2:0]$2412 + attribute \src "libresoc.v:44005.3-44033.6" + wire width 5 $0\fus_cu_rdmaskn_i$27[4:0]$2435 + attribute \src "libresoc.v:44443.3-44471.6" + wire width 3 $0\fus_cu_rdmaskn_i$30[2:0]$2458 + attribute \src "libresoc.v:46154.3-46182.6" + wire width 6 $0\fus_cu_rdmaskn_i$6[5:0]$2785 + attribute \src "libresoc.v:46542.3-46570.6" + wire width 3 $0\fus_cu_rdmaskn_i$9[2:0]$2844 + attribute \src "libresoc.v:45937.3-45965.6" + wire width 4 $0\fus_cu_rdmaskn_i[3:0] + attribute \src "libresoc.v:45814.3-45842.6" + wire width 4 $0\fus_oper_i_alu_alu0__data_len[3:0] + attribute \src "libresoc.v:45134.3-45162.6" + wire width 12 $0\fus_oper_i_alu_alu0__fn_unit[11:0] + attribute \src "libresoc.v:45201.3-45230.6" + wire width 64 $0\fus_oper_i_alu_alu0__imm_data__data[63:0] + attribute \src "libresoc.v:45201.3-45230.6" + wire $0\fus_oper_i_alu_alu0__imm_data__ok[0:0] + attribute \src "libresoc.v:45653.3-45681.6" + wire width 2 $0\fus_oper_i_alu_alu0__input_carry[1:0] + attribute \src "libresoc.v:45861.3-45889.6" + wire width 32 $0\fus_oper_i_alu_alu0__insn[31:0] + attribute \src "libresoc.v:45076.3-45104.6" + wire width 7 $0\fus_oper_i_alu_alu0__insn_type[6:0] + attribute \src "libresoc.v:45443.3-45471.6" + wire $0\fus_oper_i_alu_alu0__invert_in[0:0] + attribute \src "libresoc.v:45558.3-45586.6" + wire $0\fus_oper_i_alu_alu0__invert_out[0:0] + attribute \src "libresoc.v:45738.3-45766.6" + wire $0\fus_oper_i_alu_alu0__is_32bit[0:0] + attribute \src "libresoc.v:45776.3-45804.6" + wire $0\fus_oper_i_alu_alu0__is_signed[0:0] + attribute \src "libresoc.v:45356.3-45385.6" + wire $0\fus_oper_i_alu_alu0__oe__oe[0:0] + attribute \src "libresoc.v:45356.3-45385.6" + wire $0\fus_oper_i_alu_alu0__oe__ok[0:0] + attribute \src "libresoc.v:45691.3-45719.6" + wire $0\fus_oper_i_alu_alu0__output_carry[0:0] + attribute \src "libresoc.v:45269.3-45298.6" + wire $0\fus_oper_i_alu_alu0__rc__ok[0:0] + attribute \src "libresoc.v:45269.3-45298.6" + wire $0\fus_oper_i_alu_alu0__rc__rc[0:0] + attribute \src "libresoc.v:45606.3-45634.6" + wire $0\fus_oper_i_alu_alu0__write_cr0[0:0] + attribute \src "libresoc.v:45500.3-45528.6" + wire $0\fus_oper_i_alu_alu0__zero_a[0:0] + attribute \src "libresoc.v:46192.3-46220.6" + wire width 64 $0\fus_oper_i_alu_branch0__cia[63:0] + attribute \src "libresoc.v:46277.3-46305.6" + wire width 12 $0\fus_oper_i_alu_branch0__fn_unit[11:0] + attribute \src "libresoc.v:46362.3-46391.6" + wire width 64 $0\fus_oper_i_alu_branch0__imm_data__data[63:0] + attribute \src "libresoc.v:46362.3-46391.6" + wire $0\fus_oper_i_alu_branch0__imm_data__ok[0:0] + attribute \src "libresoc.v:46315.3-46343.6" + wire width 32 $0\fus_oper_i_alu_branch0__insn[31:0] + attribute \src "libresoc.v:46239.3-46267.6" + wire width 7 $0\fus_oper_i_alu_branch0__insn_type[6:0] + attribute \src "libresoc.v:46457.3-46485.6" + wire $0\fus_oper_i_alu_branch0__is_32bit[0:0] + attribute \src "libresoc.v:46419.3-46447.6" + wire $0\fus_oper_i_alu_branch0__lk[0:0] + attribute \src "libresoc.v:46022.3-46050.6" + wire width 12 $0\fus_oper_i_alu_cr0__fn_unit[11:0] + attribute \src "libresoc.v:46069.3-46097.6" + wire width 32 $0\fus_oper_i_alu_cr0__insn[31:0] + attribute \src "libresoc.v:45984.3-46012.6" + wire width 7 $0\fus_oper_i_alu_cr0__insn_type[6:0] + attribute \src "libresoc.v:43158.3-43186.6" + wire width 4 $0\fus_oper_i_alu_div0__data_len[3:0] + attribute \src "libresoc.v:42807.3-42835.6" + wire width 12 $0\fus_oper_i_alu_div0__fn_unit[11:0] + attribute \src "libresoc.v:42836.3-42865.6" + wire width 64 $0\fus_oper_i_alu_div0__imm_data__data[63:0] + attribute \src "libresoc.v:42836.3-42865.6" + wire $0\fus_oper_i_alu_div0__imm_data__ok[0:0] + attribute \src "libresoc.v:42984.3-43012.6" + wire width 2 $0\fus_oper_i_alu_div0__input_carry[1:0] + attribute \src "libresoc.v:43187.3-43215.6" + wire width 32 $0\fus_oper_i_alu_div0__insn[31:0] + attribute \src "libresoc.v:42778.3-42806.6" + wire width 7 $0\fus_oper_i_alu_div0__insn_type[6:0] + attribute \src "libresoc.v:42926.3-42954.6" + wire $0\fus_oper_i_alu_div0__invert_in[0:0] + attribute \src "libresoc.v:43013.3-43041.6" + wire $0\fus_oper_i_alu_div0__invert_out[0:0] + attribute \src "libresoc.v:43100.3-43128.6" + wire $0\fus_oper_i_alu_div0__is_32bit[0:0] + attribute \src "libresoc.v:43129.3-43157.6" + wire $0\fus_oper_i_alu_div0__is_signed[0:0] + attribute \src "libresoc.v:42896.3-42925.6" + wire $0\fus_oper_i_alu_div0__oe__oe[0:0] + attribute \src "libresoc.v:42896.3-42925.6" + wire $0\fus_oper_i_alu_div0__oe__ok[0:0] + attribute \src "libresoc.v:43071.3-43099.6" + wire $0\fus_oper_i_alu_div0__output_carry[0:0] + attribute \src "libresoc.v:42866.3-42895.6" + wire $0\fus_oper_i_alu_div0__rc__ok[0:0] + attribute \src "libresoc.v:42866.3-42895.6" + wire $0\fus_oper_i_alu_div0__rc__rc[0:0] + attribute \src "libresoc.v:43042.3-43070.6" + wire $0\fus_oper_i_alu_div0__write_cr0[0:0] + attribute \src "libresoc.v:42955.3-42983.6" + wire $0\fus_oper_i_alu_div0__zero_a[0:0] + attribute \src "libresoc.v:47277.3-47305.6" + wire width 4 $0\fus_oper_i_alu_logical0__data_len[3:0] + attribute \src "libresoc.v:46926.3-46954.6" + wire width 12 $0\fus_oper_i_alu_logical0__fn_unit[11:0] + attribute \src "libresoc.v:46955.3-46984.6" + wire width 64 $0\fus_oper_i_alu_logical0__imm_data__data[63:0] + attribute \src "libresoc.v:46955.3-46984.6" + wire $0\fus_oper_i_alu_logical0__imm_data__ok[0:0] + attribute \src "libresoc.v:47103.3-47131.6" + wire width 2 $0\fus_oper_i_alu_logical0__input_carry[1:0] + attribute \src "libresoc.v:47306.3-47334.6" + wire width 32 $0\fus_oper_i_alu_logical0__insn[31:0] + attribute \src "libresoc.v:46897.3-46925.6" + wire width 7 $0\fus_oper_i_alu_logical0__insn_type[6:0] + attribute \src "libresoc.v:47045.3-47073.6" + wire $0\fus_oper_i_alu_logical0__invert_in[0:0] + attribute \src "libresoc.v:47132.3-47160.6" + wire $0\fus_oper_i_alu_logical0__invert_out[0:0] + attribute \src "libresoc.v:47219.3-47247.6" + wire $0\fus_oper_i_alu_logical0__is_32bit[0:0] + attribute \src "libresoc.v:47248.3-47276.6" + wire $0\fus_oper_i_alu_logical0__is_signed[0:0] + attribute \src "libresoc.v:47015.3-47044.6" + wire $0\fus_oper_i_alu_logical0__oe__oe[0:0] + attribute \src "libresoc.v:47015.3-47044.6" + wire $0\fus_oper_i_alu_logical0__oe__ok[0:0] + attribute \src "libresoc.v:47190.3-47218.6" + wire $0\fus_oper_i_alu_logical0__output_carry[0:0] + attribute \src "libresoc.v:46985.3-47014.6" + wire $0\fus_oper_i_alu_logical0__rc__ok[0:0] + attribute \src "libresoc.v:46985.3-47014.6" + wire $0\fus_oper_i_alu_logical0__rc__rc[0:0] + attribute \src "libresoc.v:47161.3-47189.6" + wire $0\fus_oper_i_alu_logical0__write_cr0[0:0] + attribute \src "libresoc.v:47074.3-47102.6" + wire $0\fus_oper_i_alu_logical0__zero_a[0:0] + attribute \src "libresoc.v:43303.3-43331.6" + wire width 12 $0\fus_oper_i_alu_mul0__fn_unit[11:0] + attribute \src "libresoc.v:43332.3-43361.6" + wire width 64 $0\fus_oper_i_alu_mul0__imm_data__data[63:0] + attribute \src "libresoc.v:43332.3-43361.6" + wire $0\fus_oper_i_alu_mul0__imm_data__ok[0:0] + attribute \src "libresoc.v:43509.3-43537.6" + wire width 32 $0\fus_oper_i_alu_mul0__insn[31:0] + attribute \src "libresoc.v:43274.3-43302.6" + wire width 7 $0\fus_oper_i_alu_mul0__insn_type[6:0] + attribute \src "libresoc.v:43451.3-43479.6" + wire $0\fus_oper_i_alu_mul0__is_32bit[0:0] + attribute \src "libresoc.v:43480.3-43508.6" + wire $0\fus_oper_i_alu_mul0__is_signed[0:0] + attribute \src "libresoc.v:43392.3-43421.6" + wire $0\fus_oper_i_alu_mul0__oe__oe[0:0] + attribute \src "libresoc.v:43392.3-43421.6" + wire $0\fus_oper_i_alu_mul0__oe__ok[0:0] + attribute \src "libresoc.v:43362.3-43391.6" + wire $0\fus_oper_i_alu_mul0__rc__ok[0:0] + attribute \src "libresoc.v:43362.3-43391.6" + wire $0\fus_oper_i_alu_mul0__rc__rc[0:0] + attribute \src "libresoc.v:43422.3-43450.6" + wire $0\fus_oper_i_alu_mul0__write_cr0[0:0] + attribute \src "libresoc.v:43625.3-43653.6" + wire width 12 $0\fus_oper_i_alu_shift_rot0__fn_unit[11:0] + attribute \src "libresoc.v:43654.3-43683.6" + wire width 64 $0\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] + attribute \src "libresoc.v:43654.3-43683.6" + wire $0\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] + attribute \src "libresoc.v:43773.3-43801.6" + wire width 2 $0\fus_oper_i_alu_shift_rot0__input_carry[1:0] + attribute \src "libresoc.v:43831.3-43859.6" + wire $0\fus_oper_i_alu_shift_rot0__input_cr[0:0] + attribute \src "libresoc.v:43947.3-43975.6" + wire width 32 $0\fus_oper_i_alu_shift_rot0__insn[31:0] + attribute \src "libresoc.v:43596.3-43624.6" + wire width 7 $0\fus_oper_i_alu_shift_rot0__insn_type[6:0] + attribute \src "libresoc.v:43889.3-43917.6" + wire $0\fus_oper_i_alu_shift_rot0__is_32bit[0:0] + attribute \src "libresoc.v:43918.3-43946.6" + wire $0\fus_oper_i_alu_shift_rot0__is_signed[0:0] + attribute \src "libresoc.v:43714.3-43743.6" + wire $0\fus_oper_i_alu_shift_rot0__oe__oe[0:0] + attribute \src "libresoc.v:43714.3-43743.6" + wire $0\fus_oper_i_alu_shift_rot0__oe__ok[0:0] + attribute \src "libresoc.v:43802.3-43830.6" + wire $0\fus_oper_i_alu_shift_rot0__output_carry[0:0] + attribute \src "libresoc.v:43860.3-43888.6" + wire $0\fus_oper_i_alu_shift_rot0__output_cr[0:0] + attribute \src "libresoc.v:43684.3-43713.6" + wire $0\fus_oper_i_alu_shift_rot0__rc__ok[0:0] + attribute \src "libresoc.v:43684.3-43713.6" + wire $0\fus_oper_i_alu_shift_rot0__rc__rc[0:0] + attribute \src "libresoc.v:43744.3-43772.6" + wire $0\fus_oper_i_alu_shift_rot0__write_cr0[0:0] + attribute \src "libresoc.v:47422.3-47450.6" + wire width 12 $0\fus_oper_i_alu_spr0__fn_unit[11:0] + attribute \src "libresoc.v:47451.3-47479.6" + wire width 32 $0\fus_oper_i_alu_spr0__insn[31:0] + attribute \src "libresoc.v:47393.3-47421.6" + wire width 7 $0\fus_oper_i_alu_spr0__insn_type[6:0] + attribute \src "libresoc.v:42691.3-42719.6" + wire $0\fus_oper_i_alu_spr0__is_32bit[0:0] + attribute \src "libresoc.v:46723.3-46751.6" + wire width 64 $0\fus_oper_i_alu_trap0__cia[63:0] + attribute \src "libresoc.v:46627.3-46655.6" + wire width 12 $0\fus_oper_i_alu_trap0__fn_unit[11:0] + attribute \src "libresoc.v:46665.3-46693.6" + wire width 32 $0\fus_oper_i_alu_trap0__insn[31:0] + attribute \src "libresoc.v:46589.3-46617.6" + wire width 7 $0\fus_oper_i_alu_trap0__insn_type[6:0] + attribute \src "libresoc.v:46752.3-46780.6" + wire $0\fus_oper_i_alu_trap0__is_32bit[0:0] + attribute \src "libresoc.v:46694.3-46722.6" + wire width 64 $0\fus_oper_i_alu_trap0__msr[63:0] + attribute \src "libresoc.v:46810.3-46838.6" + wire width 13 $0\fus_oper_i_alu_trap0__trapaddr[12:0] + attribute \src "libresoc.v:46781.3-46809.6" + wire width 7 $0\fus_oper_i_alu_trap0__traptype[6:0] + attribute \src "libresoc.v:44298.3-44326.6" + wire $0\fus_oper_i_ldst_ldst0__byte_reverse[0:0] + attribute \src "libresoc.v:44269.3-44297.6" + wire width 4 $0\fus_oper_i_ldst_ldst0__data_len[3:0] + attribute \src "libresoc.v:44063.3-44091.6" + wire width 12 $0\fus_oper_i_ldst_ldst0__fn_unit[11:0] + attribute \src "libresoc.v:44092.3-44121.6" + wire width 64 $0\fus_oper_i_ldst_ldst0__imm_data__data[63:0] + attribute \src "libresoc.v:44092.3-44121.6" + wire $0\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] + attribute \src "libresoc.v:44385.3-44413.6" + wire width 32 $0\fus_oper_i_ldst_ldst0__insn[31:0] + attribute \src "libresoc.v:44034.3-44062.6" + wire width 7 $0\fus_oper_i_ldst_ldst0__insn_type[6:0] + attribute \src "libresoc.v:44211.3-44239.6" + wire $0\fus_oper_i_ldst_ldst0__is_32bit[0:0] + attribute \src "libresoc.v:44240.3-44268.6" + wire $0\fus_oper_i_ldst_ldst0__is_signed[0:0] + attribute \src "libresoc.v:44356.3-44384.6" + wire width 2 $0\fus_oper_i_ldst_ldst0__ldst_mode[1:0] + attribute \src "libresoc.v:44181.3-44210.6" + wire $0\fus_oper_i_ldst_ldst0__oe__oe[0:0] + attribute \src "libresoc.v:44181.3-44210.6" + wire $0\fus_oper_i_ldst_ldst0__oe__ok[0:0] + attribute \src "libresoc.v:44151.3-44180.6" + wire $0\fus_oper_i_ldst_ldst0__rc__ok[0:0] + attribute \src "libresoc.v:44151.3-44180.6" + wire $0\fus_oper_i_ldst_ldst0__rc__rc[0:0] + attribute \src "libresoc.v:44327.3-44355.6" + wire $0\fus_oper_i_ldst_ldst0__sign_extend[0:0] + attribute \src "libresoc.v:44122.3-44150.6" + wire $0\fus_oper_i_ldst_ldst0__zero_a[0:0] + attribute \src "libresoc.v:44500.3-44509.6" + wire width 64 $0\fus_src1_i$33[63:0]$2470 + attribute \src "libresoc.v:44519.3-44528.6" + wire width 64 $0\fus_src1_i$36[63:0]$2476 + attribute \src "libresoc.v:44538.3-44547.6" + wire width 64 $0\fus_src1_i$39[63:0]$2482 + attribute \src "libresoc.v:44557.3-44566.6" + wire width 64 $0\fus_src1_i$42[63:0]$2488 + attribute \src "libresoc.v:44576.3-44585.6" + wire width 64 $0\fus_src1_i$45[63:0]$2494 + attribute \src "libresoc.v:44595.3-44604.6" + wire width 64 $0\fus_src1_i$48[63:0]$2500 + attribute \src "libresoc.v:44614.3-44623.6" + wire width 64 $0\fus_src1_i$51[63:0]$2506 + attribute \src "libresoc.v:44633.3-44642.6" + wire width 64 $0\fus_src1_i$54[63:0]$2512 + attribute \src "libresoc.v:45414.3-45423.6" + wire width 64 $0\fus_src1_i$77[63:0]$2675 + attribute \src "libresoc.v:44481.3-44490.6" + wire width 64 $0\fus_src1_i[63:0] + attribute \src "libresoc.v:44671.3-44680.6" + wire width 64 $0\fus_src2_i$55[63:0]$2522 + attribute \src "libresoc.v:44690.3-44699.6" + wire width 64 $0\fus_src2_i$56[63:0]$2528 + attribute \src "libresoc.v:44709.3-44718.6" + wire width 64 $0\fus_src2_i$57[63:0]$2534 + attribute \src "libresoc.v:44728.3-44737.6" + wire width 64 $0\fus_src2_i$58[63:0]$2540 + attribute \src "libresoc.v:44747.3-44756.6" + wire width 64 $0\fus_src2_i$59[63:0]$2546 + attribute \src "libresoc.v:44766.3-44775.6" + wire width 64 $0\fus_src2_i$60[63:0]$2552 + attribute \src "libresoc.v:44785.3-44794.6" + wire width 64 $0\fus_src2_i$61[63:0]$2558 + attribute \src "libresoc.v:45529.3-45538.6" + wire width 64 $0\fus_src2_i$80[63:0]$2695 + attribute \src "libresoc.v:45596.3-45605.6" + wire width 64 $0\fus_src2_i$82[63:0]$2708 + attribute \src "libresoc.v:44652.3-44661.6" + wire width 64 $0\fus_src2_i[63:0] + attribute \src "libresoc.v:44823.3-44832.6" + wire width 64 $0\fus_src3_i$62[63:0]$2568 + attribute \src "libresoc.v:44869.3-44878.6" + wire $0\fus_src3_i$63[0:0]$2580 + attribute \src "libresoc.v:44979.3-44988.6" + wire $0\fus_src3_i$64[0:0]$2587 + attribute \src "libresoc.v:45038.3-45047.6" + wire $0\fus_src3_i$65[0:0]$2602 + attribute \src "libresoc.v:45057.3-45066.6" + wire $0\fus_src3_i$66[0:0]$2608 + attribute \src "libresoc.v:45259.3-45268.6" + wire width 32 $0\fus_src3_i$70[31:0]$2643 + attribute \src "libresoc.v:45327.3-45336.6" + wire width 4 $0\fus_src3_i$74[3:0]$2656 + attribute \src "libresoc.v:45433.3-45442.6" + wire width 64 $0\fus_src3_i$78[63:0]$2681 + attribute \src "libresoc.v:45481.3-45490.6" + wire width 64 $0\fus_src3_i$79[63:0]$2688 + attribute \src "libresoc.v:44804.3-44813.6" + wire width 64 $0\fus_src3_i[63:0] + attribute \src "libresoc.v:45105.3-45114.6" + wire $0\fus_src4_i$67[0:0]$2615 + attribute \src "libresoc.v:45124.3-45133.6" + wire width 2 $0\fus_src4_i$68[1:0]$2621 + attribute \src "libresoc.v:45308.3-45317.6" + wire width 4 $0\fus_src4_i$71[3:0]$2650 + attribute \src "libresoc.v:45548.3-45557.6" + wire width 64 $0\fus_src4_i$81[63:0]$2701 + attribute \src "libresoc.v:44998.3-45007.6" + wire $0\fus_src4_i[0:0] + attribute \src "libresoc.v:45240.3-45249.6" + wire width 2 $0\fus_src5_i$69[1:0]$2637 + attribute \src "libresoc.v:45346.3-45355.6" + wire width 4 $0\fus_src5_i$75[3:0]$2662 + attribute \src "libresoc.v:45191.3-45200.6" + wire width 2 $0\fus_src5_i[1:0] + attribute \src "libresoc.v:45395.3-45404.6" + wire width 4 $0\fus_src6_i$76[3:0]$2669 + attribute \src "libresoc.v:45172.3-45181.6" + wire width 2 $0\fus_src6_i[1:0] + attribute \src "libresoc.v:35346.7-35346.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:45720.3-45728.6" + wire $0\wr_pick_dly$1007$next[0:0]$2723 + attribute \src "libresoc.v:41888.3-41889.51" + wire $0\wr_pick_dly$1007[0:0]$2313 + attribute \src "libresoc.v:40720.7-40720.32" + wire $0\wr_pick_dly$1007[0:0]$2951 + attribute \src "libresoc.v:45729.3-45737.6" + wire $0\wr_pick_dly$1025$next[0:0]$2726 + attribute \src "libresoc.v:41886.3-41887.51" + wire $0\wr_pick_dly$1025[0:0]$2311 + attribute \src "libresoc.v:40724.7-40724.32" + wire $0\wr_pick_dly$1025[0:0]$2953 + attribute \src "libresoc.v:45767.3-45775.6" + wire $0\wr_pick_dly$1047$next[0:0]$2730 + attribute \src "libresoc.v:41884.3-41885.51" + wire $0\wr_pick_dly$1047[0:0]$2309 + attribute \src "libresoc.v:40728.7-40728.32" + wire $0\wr_pick_dly$1047[0:0]$2955 + attribute \src "libresoc.v:45805.3-45813.6" + wire $0\wr_pick_dly$1067$next[0:0]$2734 + attribute \src "libresoc.v:41882.3-41883.51" + wire $0\wr_pick_dly$1067[0:0]$2307 + attribute \src "libresoc.v:40732.7-40732.32" + wire $0\wr_pick_dly$1067[0:0]$2957 + attribute \src "libresoc.v:45843.3-45851.6" + wire $0\wr_pick_dly$1087$next[0:0]$2738 + attribute \src "libresoc.v:41880.3-41881.51" + wire $0\wr_pick_dly$1087[0:0]$2305 + attribute \src "libresoc.v:40736.7-40736.32" + wire $0\wr_pick_dly$1087[0:0]$2959 + attribute \src "libresoc.v:45852.3-45860.6" + wire $0\wr_pick_dly$1106$next[0:0]$2741 + attribute \src "libresoc.v:41878.3-41879.51" + wire $0\wr_pick_dly$1106[0:0]$2303 + attribute \src "libresoc.v:40740.7-40740.32" + wire $0\wr_pick_dly$1106[0:0]$2961 + attribute \src "libresoc.v:45890.3-45898.6" + wire $0\wr_pick_dly$1124$next[0:0]$2745 + attribute \src "libresoc.v:41876.3-41877.51" + wire $0\wr_pick_dly$1124[0:0]$2301 + attribute \src "libresoc.v:40744.7-40744.32" + wire $0\wr_pick_dly$1124[0:0]$2963 + attribute \src "libresoc.v:45928.3-45936.6" + wire $0\wr_pick_dly$1197$next[0:0]$2749 + attribute \src "libresoc.v:41874.3-41875.51" + wire $0\wr_pick_dly$1197[0:0]$2299 + attribute \src "libresoc.v:40748.7-40748.32" + wire $0\wr_pick_dly$1197[0:0]$2965 + attribute \src "libresoc.v:45966.3-45974.6" + wire $0\wr_pick_dly$1225$next[0:0]$2753 + attribute \src "libresoc.v:41872.3-41873.51" + wire $0\wr_pick_dly$1225[0:0]$2297 + attribute \src "libresoc.v:40752.7-40752.32" + wire $0\wr_pick_dly$1225[0:0]$2967 + attribute \src "libresoc.v:45975.3-45983.6" + wire $0\wr_pick_dly$1245$next[0:0]$2756 + attribute \src "libresoc.v:41870.3-41871.51" + wire $0\wr_pick_dly$1245[0:0]$2295 + attribute \src "libresoc.v:40756.7-40756.32" + wire $0\wr_pick_dly$1245[0:0]$2969 + attribute \src "libresoc.v:46013.3-46021.6" + wire $0\wr_pick_dly$1265$next[0:0]$2760 + attribute \src "libresoc.v:41868.3-41869.51" + wire $0\wr_pick_dly$1265[0:0]$2293 + attribute \src "libresoc.v:40760.7-40760.32" + wire $0\wr_pick_dly$1265[0:0]$2971 + attribute \src "libresoc.v:46051.3-46059.6" + wire $0\wr_pick_dly$1285$next[0:0]$2764 + attribute \src "libresoc.v:41866.3-41867.51" + wire $0\wr_pick_dly$1285[0:0]$2291 + attribute \src "libresoc.v:40764.7-40764.32" + wire $0\wr_pick_dly$1285[0:0]$2973 + attribute \src "libresoc.v:46060.3-46068.6" + wire $0\wr_pick_dly$1305$next[0:0]$2767 + attribute \src "libresoc.v:41864.3-41865.51" + wire $0\wr_pick_dly$1305[0:0]$2289 + attribute \src "libresoc.v:40768.7-40768.32" + wire $0\wr_pick_dly$1305[0:0]$2975 + attribute \src "libresoc.v:46098.3-46106.6" + wire $0\wr_pick_dly$1325$next[0:0]$2771 + attribute \src "libresoc.v:41862.3-41863.51" + wire $0\wr_pick_dly$1325[0:0]$2287 + attribute \src "libresoc.v:40772.7-40772.32" + wire $0\wr_pick_dly$1325[0:0]$2977 + attribute \src "libresoc.v:46136.3-46144.6" + wire $0\wr_pick_dly$1372$next[0:0]$2779 + attribute \src "libresoc.v:41860.3-41861.51" + wire $0\wr_pick_dly$1372[0:0]$2285 + attribute \src "libresoc.v:40776.7-40776.32" + wire $0\wr_pick_dly$1372[0:0]$2979 + attribute \src "libresoc.v:46145.3-46153.6" + wire $0\wr_pick_dly$1388$next[0:0]$2782 + attribute \src "libresoc.v:41858.3-41859.51" + wire $0\wr_pick_dly$1388[0:0]$2283 + attribute \src "libresoc.v:40780.7-40780.32" + wire $0\wr_pick_dly$1388[0:0]$2981 + attribute \src "libresoc.v:46183.3-46191.6" + wire $0\wr_pick_dly$1404$next[0:0]$2790 + attribute \src "libresoc.v:41856.3-41857.51" + wire $0\wr_pick_dly$1404[0:0]$2281 + attribute \src "libresoc.v:40784.7-40784.32" + wire $0\wr_pick_dly$1404[0:0]$2983 + attribute \src "libresoc.v:46221.3-46229.6" + wire $0\wr_pick_dly$1438$next[0:0]$2794 + attribute \src "libresoc.v:41854.3-41855.51" + wire $0\wr_pick_dly$1438[0:0]$2279 + attribute \src "libresoc.v:40788.7-40788.32" + wire $0\wr_pick_dly$1438[0:0]$2985 + attribute \src "libresoc.v:46230.3-46238.6" + wire $0\wr_pick_dly$1454$next[0:0]$2797 + attribute \src "libresoc.v:41852.3-41853.51" + wire $0\wr_pick_dly$1454[0:0]$2277 + attribute \src "libresoc.v:40792.7-40792.32" + wire $0\wr_pick_dly$1454[0:0]$2987 + attribute \src "libresoc.v:46268.3-46276.6" + wire $0\wr_pick_dly$1470$next[0:0]$2801 + attribute \src "libresoc.v:41850.3-41851.51" + wire $0\wr_pick_dly$1470[0:0]$2275 + attribute \src "libresoc.v:40796.7-40796.32" + wire $0\wr_pick_dly$1470[0:0]$2989 + attribute \src "libresoc.v:46306.3-46314.6" + wire $0\wr_pick_dly$1486$next[0:0]$2805 + attribute \src "libresoc.v:41848.3-41849.51" + wire $0\wr_pick_dly$1486[0:0]$2273 + attribute \src "libresoc.v:40800.7-40800.32" + wire $0\wr_pick_dly$1486[0:0]$2991 + attribute \src "libresoc.v:46344.3-46352.6" + wire $0\wr_pick_dly$1522$next[0:0]$2809 + attribute \src "libresoc.v:41846.3-41847.51" + wire $0\wr_pick_dly$1522[0:0]$2271 + attribute \src "libresoc.v:40804.7-40804.32" + wire $0\wr_pick_dly$1522[0:0]$2993 + attribute \src "libresoc.v:46353.3-46361.6" + wire $0\wr_pick_dly$1538$next[0:0]$2812 + attribute \src "libresoc.v:41844.3-41845.51" + wire $0\wr_pick_dly$1538[0:0]$2269 + attribute \src "libresoc.v:40808.7-40808.32" + wire $0\wr_pick_dly$1538[0:0]$2995 + attribute \src "libresoc.v:46392.3-46400.6" + wire $0\wr_pick_dly$1554$next[0:0]$2816 + attribute \src "libresoc.v:41842.3-41843.51" + wire $0\wr_pick_dly$1554[0:0]$2267 + attribute \src "libresoc.v:40812.7-40812.32" + wire $0\wr_pick_dly$1554[0:0]$2997 + attribute \src "libresoc.v:46401.3-46409.6" + wire $0\wr_pick_dly$1570$next[0:0]$2819 + attribute \src "libresoc.v:41840.3-41841.51" + wire $0\wr_pick_dly$1570[0:0]$2265 + attribute \src "libresoc.v:40816.7-40816.32" + wire $0\wr_pick_dly$1570[0:0]$2999 + attribute \src "libresoc.v:46410.3-46418.6" + wire $0\wr_pick_dly$1612$next[0:0]$2822 + attribute \src "libresoc.v:41838.3-41839.51" + wire $0\wr_pick_dly$1612[0:0]$2263 + attribute \src "libresoc.v:40820.7-40820.32" + wire $0\wr_pick_dly$1612[0:0]$3001 + attribute \src "libresoc.v:46448.3-46456.6" + wire $0\wr_pick_dly$1631$next[0:0]$2826 + attribute \src "libresoc.v:41836.3-41837.51" + wire $0\wr_pick_dly$1631[0:0]$2261 + attribute \src "libresoc.v:40824.7-40824.32" + wire $0\wr_pick_dly$1631[0:0]$3003 + attribute \src "libresoc.v:46486.3-46494.6" + wire $0\wr_pick_dly$1647$next[0:0]$2830 + attribute \src "libresoc.v:41834.3-41835.51" + wire $0\wr_pick_dly$1647[0:0]$2259 + attribute \src "libresoc.v:40828.7-40828.32" + wire $0\wr_pick_dly$1647[0:0]$3005 + attribute \src "libresoc.v:46495.3-46503.6" + wire $0\wr_pick_dly$1663$next[0:0]$2833 + attribute \src "libresoc.v:41832.3-41833.51" + wire $0\wr_pick_dly$1663[0:0]$2257 + attribute \src "libresoc.v:40832.7-40832.32" + wire $0\wr_pick_dly$1663[0:0]$3007 + attribute \src "libresoc.v:46533.3-46541.6" + wire $0\wr_pick_dly$1679$next[0:0]$2841 + attribute \src "libresoc.v:41830.3-41831.51" + wire $0\wr_pick_dly$1679[0:0]$2255 + attribute \src "libresoc.v:40836.7-40836.32" + wire $0\wr_pick_dly$1679[0:0]$3009 + attribute \src "libresoc.v:46571.3-46579.6" + wire $0\wr_pick_dly$1723$next[0:0]$2849 + attribute \src "libresoc.v:41828.3-41829.51" + wire $0\wr_pick_dly$1723[0:0]$2253 + attribute \src "libresoc.v:40840.7-40840.32" + wire $0\wr_pick_dly$1723[0:0]$3011 + attribute \src "libresoc.v:46580.3-46588.6" + wire $0\wr_pick_dly$1739$next[0:0]$2852 + attribute \src "libresoc.v:41826.3-41827.51" + wire $0\wr_pick_dly$1739[0:0]$2251 + attribute \src "libresoc.v:40844.7-40844.32" + wire $0\wr_pick_dly$1739[0:0]$3013 + attribute \src "libresoc.v:46618.3-46626.6" + wire $0\wr_pick_dly$1763$next[0:0]$2856 + attribute \src "libresoc.v:41824.3-41825.51" + wire $0\wr_pick_dly$1763[0:0]$2249 + attribute \src "libresoc.v:40848.7-40848.32" + wire $0\wr_pick_dly$1763[0:0]$3015 + attribute \src "libresoc.v:46656.3-46664.6" + wire $0\wr_pick_dly$1783$next[0:0]$2860 + attribute \src "libresoc.v:41822.3-41823.51" + wire $0\wr_pick_dly$1783[0:0]$2247 + attribute \src "libresoc.v:40852.7-40852.32" + wire $0\wr_pick_dly$1783[0:0]$3017 + attribute \src "libresoc.v:45644.3-45652.6" + wire $0\wr_pick_dly$967$next[0:0]$2715 + attribute \src "libresoc.v:41892.3-41893.49" + wire $0\wr_pick_dly$967[0:0]$2317 + attribute \src "libresoc.v:40856.7-40856.31" + wire $0\wr_pick_dly$967[0:0]$3019 + attribute \src "libresoc.v:45682.3-45690.6" + wire $0\wr_pick_dly$986$next[0:0]$2719 + attribute \src "libresoc.v:41890.3-41891.49" + wire $0\wr_pick_dly$986[0:0]$2315 + attribute \src "libresoc.v:40860.7-40860.31" + wire $0\wr_pick_dly$986[0:0]$3021 + attribute \src "libresoc.v:45635.3-45643.6" + wire $0\wr_pick_dly$next[0:0]$2712 + attribute \src "libresoc.v:41894.3-41895.39" + wire $0\wr_pick_dly[0:0] + attribute \src "libresoc.v:44888.3-44978.6" + wire $10\corebusy_o[0:0] + attribute \src "libresoc.v:44888.3-44978.6" + wire $11\corebusy_o[0:0] + attribute \src "libresoc.v:44888.3-44978.6" + wire $12\corebusy_o[0:0] + attribute \src "libresoc.v:44888.3-44978.6" + wire $13\corebusy_o[0:0] + attribute \src "libresoc.v:45017.3-45037.6" + wire $1\core_terminate_o$next[0:0]$2598 + attribute \src "libresoc.v:37364.7-37364.30" + wire $1\core_terminate_o[0:0] + attribute \src "libresoc.v:44888.3-44978.6" + wire $1\corebusy_o[0:0] + attribute \src "libresoc.v:44833.3-44859.6" + wire width 2 $1\counter$next[1:0]$2572 + attribute \src "libresoc.v:37377.13-37377.27" + wire width 2 $1\counter[1:0] + attribute \src "libresoc.v:45318.3-45326.6" + wire $1\dp_CR_cr_a_branch0_1$next[0:0]$2654 + attribute \src "libresoc.v:38505.7-38505.34" + wire $1\dp_CR_cr_a_branch0_1[0:0] + attribute \src "libresoc.v:45299.3-45307.6" + wire $1\dp_CR_cr_a_cr0_0$next[0:0]$2648 + attribute \src "libresoc.v:38509.7-38509.30" + wire $1\dp_CR_cr_a_cr0_0[0:0] + attribute \src "libresoc.v:45337.3-45345.6" + wire $1\dp_CR_cr_b_cr0_0$next[0:0]$2660 + attribute \src "libresoc.v:38513.7-38513.30" + wire $1\dp_CR_cr_b_cr0_0[0:0] + attribute \src "libresoc.v:45386.3-45394.6" + wire $1\dp_CR_cr_c_cr0_0$next[0:0]$2667 + attribute \src "libresoc.v:38517.7-38517.30" + wire $1\dp_CR_cr_c_cr0_0[0:0] + attribute \src "libresoc.v:45250.3-45258.6" + wire $1\dp_CR_full_cr_cr0_0$next[0:0]$2641 + attribute \src "libresoc.v:38521.7-38521.33" + wire $1\dp_CR_full_cr_cr0_0[0:0] + attribute \src "libresoc.v:45405.3-45413.6" + wire $1\dp_FAST_fast1_branch0_0$next[0:0]$2673 + attribute \src "libresoc.v:38525.7-38525.37" + wire $1\dp_FAST_fast1_branch0_0[0:0] + attribute \src "libresoc.v:45472.3-45480.6" + wire $1\dp_FAST_fast1_spr0_2$next[0:0]$2686 + attribute \src "libresoc.v:38529.7-38529.34" + wire $1\dp_FAST_fast1_spr0_2[0:0] + attribute \src "libresoc.v:45424.3-45432.6" + wire $1\dp_FAST_fast1_trap0_1$next[0:0]$2679 + attribute \src "libresoc.v:38533.7-38533.35" + wire $1\dp_FAST_fast1_trap0_1[0:0] + attribute \src "libresoc.v:45491.3-45499.6" + wire $1\dp_FAST_fast2_branch0_0$next[0:0]$2692 + attribute \src "libresoc.v:38537.7-38537.37" + wire $1\dp_FAST_fast2_branch0_0[0:0] + attribute \src "libresoc.v:45539.3-45547.6" + wire $1\dp_FAST_fast2_trap0_1$next[0:0]$2699 + attribute \src "libresoc.v:38541.7-38541.35" + wire $1\dp_FAST_fast2_trap0_1[0:0] + attribute \src "libresoc.v:44472.3-44480.6" + wire $1\dp_INT_ra_alu0_0$next[0:0]$2464 + attribute \src "libresoc.v:38545.7-38545.30" + wire $1\dp_INT_ra_alu0_0[0:0] + attribute \src "libresoc.v:44491.3-44499.6" + wire $1\dp_INT_ra_cr0_1$next[0:0]$2468 + attribute \src "libresoc.v:38549.7-38549.29" + wire $1\dp_INT_ra_cr0_1[0:0] + attribute \src "libresoc.v:44567.3-44575.6" + wire $1\dp_INT_ra_div0_5$next[0:0]$2492 + attribute \src "libresoc.v:38553.7-38553.30" + wire $1\dp_INT_ra_div0_5[0:0] + attribute \src "libresoc.v:44624.3-44632.6" + wire $1\dp_INT_ra_ldst0_8$next[0:0]$2510 + attribute \src "libresoc.v:38557.7-38557.31" + wire $1\dp_INT_ra_ldst0_8[0:0] + attribute \src "libresoc.v:44529.3-44537.6" + wire $1\dp_INT_ra_logical0_3$next[0:0]$2480 + attribute \src "libresoc.v:38561.7-38561.34" + wire $1\dp_INT_ra_logical0_3[0:0] + attribute \src "libresoc.v:44586.3-44594.6" + wire $1\dp_INT_ra_mul0_6$next[0:0]$2498 + attribute \src "libresoc.v:38565.7-38565.30" + wire $1\dp_INT_ra_mul0_6[0:0] + attribute \src "libresoc.v:44605.3-44613.6" + wire $1\dp_INT_ra_shiftrot0_7$next[0:0]$2504 + attribute \src "libresoc.v:38569.7-38569.35" + wire $1\dp_INT_ra_shiftrot0_7[0:0] + attribute \src "libresoc.v:44548.3-44556.6" + wire $1\dp_INT_ra_spr0_4$next[0:0]$2486 + attribute \src "libresoc.v:38573.7-38573.30" + wire $1\dp_INT_ra_spr0_4[0:0] + attribute \src "libresoc.v:44510.3-44518.6" + wire $1\dp_INT_ra_trap0_2$next[0:0]$2474 + attribute \src "libresoc.v:38577.7-38577.31" + wire $1\dp_INT_ra_trap0_2[0:0] + attribute \src "libresoc.v:44643.3-44651.6" + wire $1\dp_INT_rb_alu0_0$next[0:0]$2516 + attribute \src "libresoc.v:38581.7-38581.30" + wire $1\dp_INT_rb_alu0_0[0:0] + attribute \src "libresoc.v:44662.3-44670.6" + wire $1\dp_INT_rb_cr0_1$next[0:0]$2520 + attribute \src "libresoc.v:38585.7-38585.29" + wire $1\dp_INT_rb_cr0_1[0:0] + attribute \src "libresoc.v:44719.3-44727.6" + wire $1\dp_INT_rb_div0_4$next[0:0]$2538 + attribute \src "libresoc.v:38589.7-38589.30" + wire $1\dp_INT_rb_div0_4[0:0] + attribute \src "libresoc.v:44776.3-44784.6" + wire $1\dp_INT_rb_ldst0_7$next[0:0]$2556 + attribute \src "libresoc.v:38593.7-38593.31" + wire $1\dp_INT_rb_ldst0_7[0:0] + attribute \src "libresoc.v:44700.3-44708.6" + wire $1\dp_INT_rb_logical0_3$next[0:0]$2532 + attribute \src "libresoc.v:38597.7-38597.34" + wire $1\dp_INT_rb_logical0_3[0:0] + attribute \src "libresoc.v:44738.3-44746.6" + wire $1\dp_INT_rb_mul0_5$next[0:0]$2544 + attribute \src "libresoc.v:38601.7-38601.30" + wire $1\dp_INT_rb_mul0_5[0:0] + attribute \src "libresoc.v:44757.3-44765.6" + wire $1\dp_INT_rb_shiftrot0_6$next[0:0]$2550 + attribute \src "libresoc.v:38605.7-38605.35" + wire $1\dp_INT_rb_shiftrot0_6[0:0] + attribute \src "libresoc.v:44681.3-44689.6" + wire $1\dp_INT_rb_trap0_2$next[0:0]$2526 + attribute \src "libresoc.v:38609.7-38609.31" + wire $1\dp_INT_rb_trap0_2[0:0] + attribute \src "libresoc.v:44814.3-44822.6" + wire $1\dp_INT_rc_ldst0_1$next[0:0]$2566 + attribute \src "libresoc.v:38613.7-38613.31" + wire $1\dp_INT_rc_ldst0_1[0:0] + attribute \src "libresoc.v:44795.3-44803.6" + wire $1\dp_INT_rc_shiftrot0_0$next[0:0]$2562 + attribute \src "libresoc.v:38617.7-38617.35" + wire $1\dp_INT_rc_shiftrot0_0[0:0] + attribute \src "libresoc.v:45587.3-45595.6" + wire $1\dp_SPR_spr1_spr0_0$next[0:0]$2706 + attribute \src "libresoc.v:38621.7-38621.32" + wire $1\dp_SPR_spr1_spr0_0[0:0] + attribute \src "libresoc.v:45115.3-45123.6" + wire $1\dp_XER_xer_ca_alu0_0$next[0:0]$2619 + attribute \src "libresoc.v:38625.7-38625.34" + wire $1\dp_XER_xer_ca_alu0_0[0:0] + attribute \src "libresoc.v:45182.3-45190.6" + wire $1\dp_XER_xer_ca_shiftrot0_2$next[0:0]$2630 + attribute \src "libresoc.v:38629.7-38629.39" + wire $1\dp_XER_xer_ca_shiftrot0_2[0:0] + attribute \src "libresoc.v:45163.3-45171.6" + wire $1\dp_XER_xer_ca_spr0_1$next[0:0]$2626 + attribute \src "libresoc.v:38633.7-38633.34" + wire $1\dp_XER_xer_ca_spr0_1[0:0] + attribute \src "libresoc.v:45231.3-45239.6" + wire $1\dp_XER_xer_ov_spr0_0$next[0:0]$2635 + attribute \src "libresoc.v:38637.7-38637.34" + wire $1\dp_XER_xer_ov_spr0_0[0:0] + attribute \src "libresoc.v:44860.3-44868.6" + wire $1\dp_XER_xer_so_alu0_0$next[0:0]$2578 + attribute \src "libresoc.v:38641.7-38641.34" + wire $1\dp_XER_xer_so_alu0_0[0:0] + attribute \src "libresoc.v:45008.3-45016.6" + wire $1\dp_XER_xer_so_div0_3$next[0:0]$2595 + attribute \src "libresoc.v:38645.7-38645.34" + wire $1\dp_XER_xer_so_div0_3[0:0] + attribute \src "libresoc.v:44879.3-44887.6" + wire $1\dp_XER_xer_so_logical0_1$next[0:0]$2584 + attribute \src "libresoc.v:38649.7-38649.38" + wire $1\dp_XER_xer_so_logical0_1[0:0] + attribute \src "libresoc.v:45048.3-45056.6" + wire $1\dp_XER_xer_so_mul0_4$next[0:0]$2606 + attribute \src "libresoc.v:38653.7-38653.34" + wire $1\dp_XER_xer_so_mul0_4[0:0] + attribute \src "libresoc.v:45067.3-45075.6" + wire $1\dp_XER_xer_so_shiftrot0_5$next[0:0]$2612 + attribute \src "libresoc.v:38657.7-38657.39" + wire $1\dp_XER_xer_so_shiftrot0_5[0:0] + attribute \src "libresoc.v:44989.3-44997.6" + wire $1\dp_XER_xer_so_spr0_2$next[0:0]$2591 + attribute \src "libresoc.v:38661.7-38661.34" + wire $1\dp_XER_xer_so_spr0_2[0:0] + attribute \src "libresoc.v:46839.3-46867.6" + wire $1\fus_cu_issue_i$10[0:0]$2870 + attribute \src "libresoc.v:47335.3-47363.6" + wire $1\fus_cu_issue_i$13[0:0]$2895 + attribute \src "libresoc.v:42720.3-42748.6" + wire $1\fus_cu_issue_i$16[0:0]$2364 + attribute \src "libresoc.v:43216.3-43244.6" + wire $1\fus_cu_issue_i$19[0:0]$2389 + attribute \src "libresoc.v:43538.3-43566.6" + wire $1\fus_cu_issue_i$22[0:0]$2408 + attribute \src "libresoc.v:43976.3-44004.6" + wire $1\fus_cu_issue_i$25[0:0]$2431 + attribute \src "libresoc.v:44414.3-44442.6" + wire $1\fus_cu_issue_i$28[0:0]$2454 + attribute \src "libresoc.v:46107.3-46135.6" + wire $1\fus_cu_issue_i$4[0:0]$2775 + attribute \src "libresoc.v:46504.3-46532.6" + wire $1\fus_cu_issue_i$7[0:0]$2837 + attribute \src "libresoc.v:45899.3-45927.6" + wire $1\fus_cu_issue_i[0:0] + attribute \src "libresoc.v:46868.3-46896.6" + wire width 4 $1\fus_cu_rdmaskn_i$12[3:0]$2875 + attribute \src "libresoc.v:47364.3-47392.6" + wire width 3 $1\fus_cu_rdmaskn_i$15[2:0]$2900 + attribute \src "libresoc.v:42749.3-42777.6" + wire width 6 $1\fus_cu_rdmaskn_i$18[5:0]$2369 + attribute \src "libresoc.v:43245.3-43273.6" + wire width 3 $1\fus_cu_rdmaskn_i$21[2:0]$2394 + attribute \src "libresoc.v:43567.3-43595.6" + wire width 3 $1\fus_cu_rdmaskn_i$24[2:0]$2413 + attribute \src "libresoc.v:44005.3-44033.6" + wire width 5 $1\fus_cu_rdmaskn_i$27[4:0]$2436 + attribute \src "libresoc.v:44443.3-44471.6" + wire width 3 $1\fus_cu_rdmaskn_i$30[2:0]$2459 + attribute \src "libresoc.v:46154.3-46182.6" + wire width 6 $1\fus_cu_rdmaskn_i$6[5:0]$2786 + attribute \src "libresoc.v:46542.3-46570.6" + wire width 3 $1\fus_cu_rdmaskn_i$9[2:0]$2845 + attribute \src "libresoc.v:45937.3-45965.6" + wire width 4 $1\fus_cu_rdmaskn_i[3:0] + attribute \src "libresoc.v:45814.3-45842.6" + wire width 4 $1\fus_oper_i_alu_alu0__data_len[3:0] + attribute \src "libresoc.v:45134.3-45162.6" + wire width 12 $1\fus_oper_i_alu_alu0__fn_unit[11:0] + attribute \src "libresoc.v:45201.3-45230.6" + wire width 64 $1\fus_oper_i_alu_alu0__imm_data__data[63:0] + attribute \src "libresoc.v:45201.3-45230.6" + wire $1\fus_oper_i_alu_alu0__imm_data__ok[0:0] + attribute \src "libresoc.v:45653.3-45681.6" + wire width 2 $1\fus_oper_i_alu_alu0__input_carry[1:0] + attribute \src "libresoc.v:45861.3-45889.6" + wire width 32 $1\fus_oper_i_alu_alu0__insn[31:0] + attribute \src "libresoc.v:45076.3-45104.6" + wire width 7 $1\fus_oper_i_alu_alu0__insn_type[6:0] + attribute \src "libresoc.v:45443.3-45471.6" + wire $1\fus_oper_i_alu_alu0__invert_in[0:0] + attribute \src "libresoc.v:45558.3-45586.6" + wire $1\fus_oper_i_alu_alu0__invert_out[0:0] + attribute \src "libresoc.v:45738.3-45766.6" + wire $1\fus_oper_i_alu_alu0__is_32bit[0:0] + attribute \src "libresoc.v:45776.3-45804.6" + wire $1\fus_oper_i_alu_alu0__is_signed[0:0] + attribute \src "libresoc.v:45356.3-45385.6" + wire $1\fus_oper_i_alu_alu0__oe__oe[0:0] + attribute \src "libresoc.v:45356.3-45385.6" + wire $1\fus_oper_i_alu_alu0__oe__ok[0:0] + attribute \src "libresoc.v:45691.3-45719.6" + wire $1\fus_oper_i_alu_alu0__output_carry[0:0] + attribute \src "libresoc.v:45269.3-45298.6" + wire $1\fus_oper_i_alu_alu0__rc__ok[0:0] + attribute \src "libresoc.v:45269.3-45298.6" + wire $1\fus_oper_i_alu_alu0__rc__rc[0:0] + attribute \src "libresoc.v:45606.3-45634.6" + wire $1\fus_oper_i_alu_alu0__write_cr0[0:0] + attribute \src "libresoc.v:45500.3-45528.6" + wire $1\fus_oper_i_alu_alu0__zero_a[0:0] + attribute \src "libresoc.v:46192.3-46220.6" + wire width 64 $1\fus_oper_i_alu_branch0__cia[63:0] + attribute \src "libresoc.v:46277.3-46305.6" + wire width 12 $1\fus_oper_i_alu_branch0__fn_unit[11:0] + attribute \src "libresoc.v:46362.3-46391.6" + wire width 64 $1\fus_oper_i_alu_branch0__imm_data__data[63:0] + attribute \src "libresoc.v:46362.3-46391.6" + wire $1\fus_oper_i_alu_branch0__imm_data__ok[0:0] + attribute \src "libresoc.v:46315.3-46343.6" + wire width 32 $1\fus_oper_i_alu_branch0__insn[31:0] + attribute \src "libresoc.v:46239.3-46267.6" + wire width 7 $1\fus_oper_i_alu_branch0__insn_type[6:0] + attribute \src "libresoc.v:46457.3-46485.6" + wire $1\fus_oper_i_alu_branch0__is_32bit[0:0] + attribute \src "libresoc.v:46419.3-46447.6" + wire $1\fus_oper_i_alu_branch0__lk[0:0] + attribute \src "libresoc.v:46022.3-46050.6" + wire width 12 $1\fus_oper_i_alu_cr0__fn_unit[11:0] + attribute \src "libresoc.v:46069.3-46097.6" + wire width 32 $1\fus_oper_i_alu_cr0__insn[31:0] + attribute \src "libresoc.v:45984.3-46012.6" + wire width 7 $1\fus_oper_i_alu_cr0__insn_type[6:0] + attribute \src "libresoc.v:43158.3-43186.6" + wire width 4 $1\fus_oper_i_alu_div0__data_len[3:0] + attribute \src "libresoc.v:42807.3-42835.6" + wire width 12 $1\fus_oper_i_alu_div0__fn_unit[11:0] + attribute \src "libresoc.v:42836.3-42865.6" + wire width 64 $1\fus_oper_i_alu_div0__imm_data__data[63:0] + attribute \src "libresoc.v:42836.3-42865.6" + wire $1\fus_oper_i_alu_div0__imm_data__ok[0:0] + attribute \src "libresoc.v:42984.3-43012.6" + wire width 2 $1\fus_oper_i_alu_div0__input_carry[1:0] + attribute \src "libresoc.v:43187.3-43215.6" + wire width 32 $1\fus_oper_i_alu_div0__insn[31:0] + attribute \src "libresoc.v:42778.3-42806.6" + wire width 7 $1\fus_oper_i_alu_div0__insn_type[6:0] + attribute \src "libresoc.v:42926.3-42954.6" + wire $1\fus_oper_i_alu_div0__invert_in[0:0] + attribute \src "libresoc.v:43013.3-43041.6" + wire $1\fus_oper_i_alu_div0__invert_out[0:0] + attribute \src "libresoc.v:43100.3-43128.6" + wire $1\fus_oper_i_alu_div0__is_32bit[0:0] + attribute \src "libresoc.v:43129.3-43157.6" + wire $1\fus_oper_i_alu_div0__is_signed[0:0] + attribute \src "libresoc.v:42896.3-42925.6" + wire $1\fus_oper_i_alu_div0__oe__oe[0:0] + attribute \src "libresoc.v:42896.3-42925.6" + wire $1\fus_oper_i_alu_div0__oe__ok[0:0] + attribute \src "libresoc.v:43071.3-43099.6" + wire $1\fus_oper_i_alu_div0__output_carry[0:0] + attribute \src "libresoc.v:42866.3-42895.6" + wire $1\fus_oper_i_alu_div0__rc__ok[0:0] + attribute \src "libresoc.v:42866.3-42895.6" + wire $1\fus_oper_i_alu_div0__rc__rc[0:0] + attribute \src "libresoc.v:43042.3-43070.6" + wire $1\fus_oper_i_alu_div0__write_cr0[0:0] + attribute \src "libresoc.v:42955.3-42983.6" + wire $1\fus_oper_i_alu_div0__zero_a[0:0] + attribute \src "libresoc.v:47277.3-47305.6" + wire width 4 $1\fus_oper_i_alu_logical0__data_len[3:0] + attribute \src "libresoc.v:46926.3-46954.6" + wire width 12 $1\fus_oper_i_alu_logical0__fn_unit[11:0] + attribute \src "libresoc.v:46955.3-46984.6" + wire width 64 $1\fus_oper_i_alu_logical0__imm_data__data[63:0] + attribute \src "libresoc.v:46955.3-46984.6" + wire $1\fus_oper_i_alu_logical0__imm_data__ok[0:0] + attribute \src "libresoc.v:47103.3-47131.6" + wire width 2 $1\fus_oper_i_alu_logical0__input_carry[1:0] + attribute \src "libresoc.v:47306.3-47334.6" + wire width 32 $1\fus_oper_i_alu_logical0__insn[31:0] + attribute \src "libresoc.v:46897.3-46925.6" + wire width 7 $1\fus_oper_i_alu_logical0__insn_type[6:0] + attribute \src "libresoc.v:47045.3-47073.6" + wire $1\fus_oper_i_alu_logical0__invert_in[0:0] + attribute \src "libresoc.v:47132.3-47160.6" + wire $1\fus_oper_i_alu_logical0__invert_out[0:0] + attribute \src "libresoc.v:47219.3-47247.6" + wire $1\fus_oper_i_alu_logical0__is_32bit[0:0] + attribute \src "libresoc.v:47248.3-47276.6" + wire $1\fus_oper_i_alu_logical0__is_signed[0:0] + attribute \src "libresoc.v:47015.3-47044.6" + wire $1\fus_oper_i_alu_logical0__oe__oe[0:0] + attribute \src "libresoc.v:47015.3-47044.6" + wire $1\fus_oper_i_alu_logical0__oe__ok[0:0] + attribute \src "libresoc.v:47190.3-47218.6" + wire $1\fus_oper_i_alu_logical0__output_carry[0:0] + attribute \src "libresoc.v:46985.3-47014.6" + wire $1\fus_oper_i_alu_logical0__rc__ok[0:0] + attribute \src "libresoc.v:46985.3-47014.6" + wire $1\fus_oper_i_alu_logical0__rc__rc[0:0] + attribute \src "libresoc.v:47161.3-47189.6" + wire $1\fus_oper_i_alu_logical0__write_cr0[0:0] + attribute \src "libresoc.v:47074.3-47102.6" + wire $1\fus_oper_i_alu_logical0__zero_a[0:0] + attribute \src "libresoc.v:43303.3-43331.6" + wire width 12 $1\fus_oper_i_alu_mul0__fn_unit[11:0] + attribute \src "libresoc.v:43332.3-43361.6" + wire width 64 $1\fus_oper_i_alu_mul0__imm_data__data[63:0] + attribute \src "libresoc.v:43332.3-43361.6" + wire $1\fus_oper_i_alu_mul0__imm_data__ok[0:0] + attribute \src "libresoc.v:43509.3-43537.6" + wire width 32 $1\fus_oper_i_alu_mul0__insn[31:0] + attribute \src "libresoc.v:43274.3-43302.6" + wire width 7 $1\fus_oper_i_alu_mul0__insn_type[6:0] + attribute \src "libresoc.v:43451.3-43479.6" + wire $1\fus_oper_i_alu_mul0__is_32bit[0:0] + attribute \src "libresoc.v:43480.3-43508.6" + wire $1\fus_oper_i_alu_mul0__is_signed[0:0] + attribute \src "libresoc.v:43392.3-43421.6" + wire $1\fus_oper_i_alu_mul0__oe__oe[0:0] + attribute \src "libresoc.v:43392.3-43421.6" + wire $1\fus_oper_i_alu_mul0__oe__ok[0:0] + attribute \src "libresoc.v:43362.3-43391.6" + wire $1\fus_oper_i_alu_mul0__rc__ok[0:0] + attribute \src "libresoc.v:43362.3-43391.6" + wire $1\fus_oper_i_alu_mul0__rc__rc[0:0] + attribute \src "libresoc.v:43422.3-43450.6" + wire $1\fus_oper_i_alu_mul0__write_cr0[0:0] + attribute \src "libresoc.v:43625.3-43653.6" + wire width 12 $1\fus_oper_i_alu_shift_rot0__fn_unit[11:0] + attribute \src "libresoc.v:43654.3-43683.6" + wire width 64 $1\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] + attribute \src "libresoc.v:43654.3-43683.6" + wire $1\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] + attribute \src "libresoc.v:43773.3-43801.6" + wire width 2 $1\fus_oper_i_alu_shift_rot0__input_carry[1:0] + attribute \src "libresoc.v:43831.3-43859.6" + wire $1\fus_oper_i_alu_shift_rot0__input_cr[0:0] + attribute \src "libresoc.v:43947.3-43975.6" + wire width 32 $1\fus_oper_i_alu_shift_rot0__insn[31:0] + attribute \src "libresoc.v:43596.3-43624.6" + wire width 7 $1\fus_oper_i_alu_shift_rot0__insn_type[6:0] + attribute \src "libresoc.v:43889.3-43917.6" + wire $1\fus_oper_i_alu_shift_rot0__is_32bit[0:0] + attribute \src "libresoc.v:43918.3-43946.6" + wire $1\fus_oper_i_alu_shift_rot0__is_signed[0:0] + attribute \src "libresoc.v:43714.3-43743.6" + wire $1\fus_oper_i_alu_shift_rot0__oe__oe[0:0] + attribute \src "libresoc.v:43714.3-43743.6" + wire $1\fus_oper_i_alu_shift_rot0__oe__ok[0:0] + attribute \src "libresoc.v:43802.3-43830.6" + wire $1\fus_oper_i_alu_shift_rot0__output_carry[0:0] + attribute \src "libresoc.v:43860.3-43888.6" + wire $1\fus_oper_i_alu_shift_rot0__output_cr[0:0] + attribute \src "libresoc.v:43684.3-43713.6" + wire $1\fus_oper_i_alu_shift_rot0__rc__ok[0:0] + attribute \src "libresoc.v:43684.3-43713.6" + wire $1\fus_oper_i_alu_shift_rot0__rc__rc[0:0] + attribute \src "libresoc.v:43744.3-43772.6" + wire $1\fus_oper_i_alu_shift_rot0__write_cr0[0:0] + attribute \src "libresoc.v:47422.3-47450.6" + wire width 12 $1\fus_oper_i_alu_spr0__fn_unit[11:0] + attribute \src "libresoc.v:47451.3-47479.6" + wire width 32 $1\fus_oper_i_alu_spr0__insn[31:0] + attribute \src "libresoc.v:47393.3-47421.6" + wire width 7 $1\fus_oper_i_alu_spr0__insn_type[6:0] + attribute \src "libresoc.v:42691.3-42719.6" + wire $1\fus_oper_i_alu_spr0__is_32bit[0:0] + attribute \src "libresoc.v:46723.3-46751.6" + wire width 64 $1\fus_oper_i_alu_trap0__cia[63:0] + attribute \src "libresoc.v:46627.3-46655.6" + wire width 12 $1\fus_oper_i_alu_trap0__fn_unit[11:0] + attribute \src "libresoc.v:46665.3-46693.6" + wire width 32 $1\fus_oper_i_alu_trap0__insn[31:0] + attribute \src "libresoc.v:46589.3-46617.6" + wire width 7 $1\fus_oper_i_alu_trap0__insn_type[6:0] + attribute \src "libresoc.v:46752.3-46780.6" + wire $1\fus_oper_i_alu_trap0__is_32bit[0:0] + attribute \src "libresoc.v:46694.3-46722.6" + wire width 64 $1\fus_oper_i_alu_trap0__msr[63:0] + attribute \src "libresoc.v:46810.3-46838.6" + wire width 13 $1\fus_oper_i_alu_trap0__trapaddr[12:0] + attribute \src "libresoc.v:46781.3-46809.6" + wire width 7 $1\fus_oper_i_alu_trap0__traptype[6:0] + attribute \src "libresoc.v:44298.3-44326.6" + wire $1\fus_oper_i_ldst_ldst0__byte_reverse[0:0] + attribute \src "libresoc.v:44269.3-44297.6" + wire width 4 $1\fus_oper_i_ldst_ldst0__data_len[3:0] + attribute \src "libresoc.v:44063.3-44091.6" + wire width 12 $1\fus_oper_i_ldst_ldst0__fn_unit[11:0] + attribute \src "libresoc.v:44092.3-44121.6" + wire width 64 $1\fus_oper_i_ldst_ldst0__imm_data__data[63:0] + attribute \src "libresoc.v:44092.3-44121.6" + wire $1\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] + attribute \src "libresoc.v:44385.3-44413.6" + wire width 32 $1\fus_oper_i_ldst_ldst0__insn[31:0] + attribute \src "libresoc.v:44034.3-44062.6" + wire width 7 $1\fus_oper_i_ldst_ldst0__insn_type[6:0] + attribute \src "libresoc.v:44211.3-44239.6" + wire $1\fus_oper_i_ldst_ldst0__is_32bit[0:0] + attribute \src "libresoc.v:44240.3-44268.6" + wire $1\fus_oper_i_ldst_ldst0__is_signed[0:0] + attribute \src "libresoc.v:44356.3-44384.6" + wire width 2 $1\fus_oper_i_ldst_ldst0__ldst_mode[1:0] + attribute \src "libresoc.v:44181.3-44210.6" + wire $1\fus_oper_i_ldst_ldst0__oe__oe[0:0] + attribute \src "libresoc.v:44181.3-44210.6" + wire $1\fus_oper_i_ldst_ldst0__oe__ok[0:0] + attribute \src "libresoc.v:44151.3-44180.6" + wire $1\fus_oper_i_ldst_ldst0__rc__ok[0:0] + attribute \src "libresoc.v:44151.3-44180.6" + wire $1\fus_oper_i_ldst_ldst0__rc__rc[0:0] + attribute \src "libresoc.v:44327.3-44355.6" + wire $1\fus_oper_i_ldst_ldst0__sign_extend[0:0] + attribute \src "libresoc.v:44122.3-44150.6" + wire $1\fus_oper_i_ldst_ldst0__zero_a[0:0] + attribute \src "libresoc.v:44500.3-44509.6" + wire width 64 $1\fus_src1_i$33[63:0]$2471 + attribute \src "libresoc.v:44519.3-44528.6" + wire width 64 $1\fus_src1_i$36[63:0]$2477 + attribute \src "libresoc.v:44538.3-44547.6" + wire width 64 $1\fus_src1_i$39[63:0]$2483 + attribute \src "libresoc.v:44557.3-44566.6" + wire width 64 $1\fus_src1_i$42[63:0]$2489 + attribute \src "libresoc.v:44576.3-44585.6" + wire width 64 $1\fus_src1_i$45[63:0]$2495 + attribute \src "libresoc.v:44595.3-44604.6" + wire width 64 $1\fus_src1_i$48[63:0]$2501 + attribute \src "libresoc.v:44614.3-44623.6" + wire width 64 $1\fus_src1_i$51[63:0]$2507 + attribute \src "libresoc.v:44633.3-44642.6" + wire width 64 $1\fus_src1_i$54[63:0]$2513 + attribute \src "libresoc.v:45414.3-45423.6" + wire width 64 $1\fus_src1_i$77[63:0]$2676 + attribute \src "libresoc.v:44481.3-44490.6" + wire width 64 $1\fus_src1_i[63:0] + attribute \src "libresoc.v:44671.3-44680.6" + wire width 64 $1\fus_src2_i$55[63:0]$2523 + attribute \src "libresoc.v:44690.3-44699.6" + wire width 64 $1\fus_src2_i$56[63:0]$2529 + attribute \src "libresoc.v:44709.3-44718.6" + wire width 64 $1\fus_src2_i$57[63:0]$2535 + attribute \src "libresoc.v:44728.3-44737.6" + wire width 64 $1\fus_src2_i$58[63:0]$2541 + attribute \src "libresoc.v:44747.3-44756.6" + wire width 64 $1\fus_src2_i$59[63:0]$2547 + attribute \src "libresoc.v:44766.3-44775.6" + wire width 64 $1\fus_src2_i$60[63:0]$2553 + attribute \src "libresoc.v:44785.3-44794.6" + wire width 64 $1\fus_src2_i$61[63:0]$2559 + attribute \src "libresoc.v:45529.3-45538.6" + wire width 64 $1\fus_src2_i$80[63:0]$2696 + attribute \src "libresoc.v:45596.3-45605.6" + wire width 64 $1\fus_src2_i$82[63:0]$2709 + attribute \src "libresoc.v:44652.3-44661.6" + wire width 64 $1\fus_src2_i[63:0] + attribute \src "libresoc.v:44823.3-44832.6" + wire width 64 $1\fus_src3_i$62[63:0]$2569 + attribute \src "libresoc.v:44869.3-44878.6" + wire $1\fus_src3_i$63[0:0]$2581 + attribute \src "libresoc.v:44979.3-44988.6" + wire $1\fus_src3_i$64[0:0]$2588 + attribute \src "libresoc.v:45038.3-45047.6" + wire $1\fus_src3_i$65[0:0]$2603 + attribute \src "libresoc.v:45057.3-45066.6" + wire $1\fus_src3_i$66[0:0]$2609 + attribute \src "libresoc.v:45259.3-45268.6" + wire width 32 $1\fus_src3_i$70[31:0]$2644 + attribute \src "libresoc.v:45327.3-45336.6" + wire width 4 $1\fus_src3_i$74[3:0]$2657 + attribute \src "libresoc.v:45433.3-45442.6" + wire width 64 $1\fus_src3_i$78[63:0]$2682 + attribute \src "libresoc.v:45481.3-45490.6" + wire width 64 $1\fus_src3_i$79[63:0]$2689 + attribute \src "libresoc.v:44804.3-44813.6" + wire width 64 $1\fus_src3_i[63:0] + attribute \src "libresoc.v:45105.3-45114.6" + wire $1\fus_src4_i$67[0:0]$2616 + attribute \src "libresoc.v:45124.3-45133.6" + wire width 2 $1\fus_src4_i$68[1:0]$2622 + attribute \src "libresoc.v:45308.3-45317.6" + wire width 4 $1\fus_src4_i$71[3:0]$2651 + attribute \src "libresoc.v:45548.3-45557.6" + wire width 64 $1\fus_src4_i$81[63:0]$2702 + attribute \src "libresoc.v:44998.3-45007.6" + wire $1\fus_src4_i[0:0] + attribute \src "libresoc.v:45240.3-45249.6" + wire width 2 $1\fus_src5_i$69[1:0]$2638 + attribute \src "libresoc.v:45346.3-45355.6" + wire width 4 $1\fus_src5_i$75[3:0]$2663 + attribute \src "libresoc.v:45191.3-45200.6" + wire width 2 $1\fus_src5_i[1:0] + attribute \src "libresoc.v:45395.3-45404.6" + wire width 4 $1\fus_src6_i$76[3:0]$2670 + attribute \src "libresoc.v:45172.3-45181.6" + wire width 2 $1\fus_src6_i[1:0] + attribute \src "libresoc.v:45720.3-45728.6" + wire $1\wr_pick_dly$1007$next[0:0]$2724 + attribute \src "libresoc.v:45729.3-45737.6" + wire $1\wr_pick_dly$1025$next[0:0]$2727 + attribute \src "libresoc.v:45767.3-45775.6" + wire $1\wr_pick_dly$1047$next[0:0]$2731 + attribute \src "libresoc.v:45805.3-45813.6" + wire $1\wr_pick_dly$1067$next[0:0]$2735 + attribute \src "libresoc.v:45843.3-45851.6" + wire $1\wr_pick_dly$1087$next[0:0]$2739 + attribute \src "libresoc.v:45852.3-45860.6" + wire $1\wr_pick_dly$1106$next[0:0]$2742 + attribute \src "libresoc.v:45890.3-45898.6" + wire $1\wr_pick_dly$1124$next[0:0]$2746 + attribute \src "libresoc.v:45928.3-45936.6" + wire $1\wr_pick_dly$1197$next[0:0]$2750 + attribute \src "libresoc.v:45966.3-45974.6" + wire $1\wr_pick_dly$1225$next[0:0]$2754 + attribute \src "libresoc.v:45975.3-45983.6" + wire $1\wr_pick_dly$1245$next[0:0]$2757 + attribute \src "libresoc.v:46013.3-46021.6" + wire $1\wr_pick_dly$1265$next[0:0]$2761 + attribute \src "libresoc.v:46051.3-46059.6" + wire $1\wr_pick_dly$1285$next[0:0]$2765 + attribute \src "libresoc.v:46060.3-46068.6" + wire $1\wr_pick_dly$1305$next[0:0]$2768 + attribute \src "libresoc.v:46098.3-46106.6" + wire $1\wr_pick_dly$1325$next[0:0]$2772 + attribute \src "libresoc.v:46136.3-46144.6" + wire $1\wr_pick_dly$1372$next[0:0]$2780 + attribute \src "libresoc.v:46145.3-46153.6" + wire $1\wr_pick_dly$1388$next[0:0]$2783 + attribute \src "libresoc.v:46183.3-46191.6" + wire $1\wr_pick_dly$1404$next[0:0]$2791 + attribute \src "libresoc.v:46221.3-46229.6" + wire $1\wr_pick_dly$1438$next[0:0]$2795 + attribute \src "libresoc.v:46230.3-46238.6" + wire $1\wr_pick_dly$1454$next[0:0]$2798 + attribute \src "libresoc.v:46268.3-46276.6" + wire $1\wr_pick_dly$1470$next[0:0]$2802 + attribute \src "libresoc.v:46306.3-46314.6" + wire $1\wr_pick_dly$1486$next[0:0]$2806 + attribute \src "libresoc.v:46344.3-46352.6" + wire $1\wr_pick_dly$1522$next[0:0]$2810 + attribute \src "libresoc.v:46353.3-46361.6" + wire $1\wr_pick_dly$1538$next[0:0]$2813 + attribute \src "libresoc.v:46392.3-46400.6" + wire $1\wr_pick_dly$1554$next[0:0]$2817 + attribute \src "libresoc.v:46401.3-46409.6" + wire $1\wr_pick_dly$1570$next[0:0]$2820 + attribute \src "libresoc.v:46410.3-46418.6" + wire $1\wr_pick_dly$1612$next[0:0]$2823 + attribute \src "libresoc.v:46448.3-46456.6" + wire $1\wr_pick_dly$1631$next[0:0]$2827 + attribute \src "libresoc.v:46486.3-46494.6" + wire $1\wr_pick_dly$1647$next[0:0]$2831 + attribute \src "libresoc.v:46495.3-46503.6" + wire $1\wr_pick_dly$1663$next[0:0]$2834 + attribute \src "libresoc.v:46533.3-46541.6" + wire $1\wr_pick_dly$1679$next[0:0]$2842 + attribute \src "libresoc.v:46571.3-46579.6" + wire $1\wr_pick_dly$1723$next[0:0]$2850 + attribute \src "libresoc.v:46580.3-46588.6" + wire $1\wr_pick_dly$1739$next[0:0]$2853 + attribute \src "libresoc.v:46618.3-46626.6" + wire $1\wr_pick_dly$1763$next[0:0]$2857 + attribute \src "libresoc.v:46656.3-46664.6" + wire $1\wr_pick_dly$1783$next[0:0]$2861 + attribute \src "libresoc.v:45644.3-45652.6" + wire $1\wr_pick_dly$967$next[0:0]$2716 + attribute \src "libresoc.v:45682.3-45690.6" + wire $1\wr_pick_dly$986$next[0:0]$2720 + attribute \src "libresoc.v:45635.3-45643.6" + wire $1\wr_pick_dly$next[0:0]$2713 + attribute \src "libresoc.v:40718.7-40718.25" + wire $1\wr_pick_dly[0:0] + attribute \src "libresoc.v:45017.3-45037.6" + wire $2\core_terminate_o$next[0:0]$2599 + attribute \src "libresoc.v:44888.3-44978.6" + wire $2\corebusy_o[0:0] + attribute \src "libresoc.v:44833.3-44859.6" + wire width 2 $2\counter$next[1:0]$2573 + attribute \src "libresoc.v:46839.3-46867.6" + wire $2\fus_cu_issue_i$10[0:0]$2871 + attribute \src "libresoc.v:47335.3-47363.6" + wire $2\fus_cu_issue_i$13[0:0]$2896 + attribute \src "libresoc.v:42720.3-42748.6" + wire $2\fus_cu_issue_i$16[0:0]$2365 + attribute \src "libresoc.v:43216.3-43244.6" + wire $2\fus_cu_issue_i$19[0:0]$2390 + attribute \src "libresoc.v:43538.3-43566.6" + wire $2\fus_cu_issue_i$22[0:0]$2409 + attribute \src "libresoc.v:43976.3-44004.6" + wire $2\fus_cu_issue_i$25[0:0]$2432 + attribute \src "libresoc.v:44414.3-44442.6" + wire $2\fus_cu_issue_i$28[0:0]$2455 + attribute \src "libresoc.v:46107.3-46135.6" + wire $2\fus_cu_issue_i$4[0:0]$2776 + attribute \src "libresoc.v:46504.3-46532.6" + wire $2\fus_cu_issue_i$7[0:0]$2838 + attribute \src "libresoc.v:45899.3-45927.6" + wire $2\fus_cu_issue_i[0:0] + attribute \src "libresoc.v:46868.3-46896.6" + wire width 4 $2\fus_cu_rdmaskn_i$12[3:0]$2876 + attribute \src "libresoc.v:47364.3-47392.6" + wire width 3 $2\fus_cu_rdmaskn_i$15[2:0]$2901 + attribute \src "libresoc.v:42749.3-42777.6" + wire width 6 $2\fus_cu_rdmaskn_i$18[5:0]$2370 + attribute \src "libresoc.v:43245.3-43273.6" + wire width 3 $2\fus_cu_rdmaskn_i$21[2:0]$2395 + attribute \src "libresoc.v:43567.3-43595.6" + wire width 3 $2\fus_cu_rdmaskn_i$24[2:0]$2414 + attribute \src "libresoc.v:44005.3-44033.6" + wire width 5 $2\fus_cu_rdmaskn_i$27[4:0]$2437 + attribute \src "libresoc.v:44443.3-44471.6" + wire width 3 $2\fus_cu_rdmaskn_i$30[2:0]$2460 + attribute \src "libresoc.v:46154.3-46182.6" + wire width 6 $2\fus_cu_rdmaskn_i$6[5:0]$2787 + attribute \src "libresoc.v:46542.3-46570.6" + wire width 3 $2\fus_cu_rdmaskn_i$9[2:0]$2846 + attribute \src "libresoc.v:45937.3-45965.6" + wire width 4 $2\fus_cu_rdmaskn_i[3:0] + attribute \src "libresoc.v:45814.3-45842.6" + wire width 4 $2\fus_oper_i_alu_alu0__data_len[3:0] + attribute \src "libresoc.v:45134.3-45162.6" + wire width 12 $2\fus_oper_i_alu_alu0__fn_unit[11:0] + attribute \src "libresoc.v:45201.3-45230.6" + wire width 64 $2\fus_oper_i_alu_alu0__imm_data__data[63:0] + attribute \src "libresoc.v:45201.3-45230.6" + wire $2\fus_oper_i_alu_alu0__imm_data__ok[0:0] + attribute \src "libresoc.v:45653.3-45681.6" + wire width 2 $2\fus_oper_i_alu_alu0__input_carry[1:0] + attribute \src "libresoc.v:45861.3-45889.6" + wire width 32 $2\fus_oper_i_alu_alu0__insn[31:0] + attribute \src "libresoc.v:45076.3-45104.6" + wire width 7 $2\fus_oper_i_alu_alu0__insn_type[6:0] + attribute \src "libresoc.v:45443.3-45471.6" + wire $2\fus_oper_i_alu_alu0__invert_in[0:0] + attribute \src "libresoc.v:45558.3-45586.6" + wire $2\fus_oper_i_alu_alu0__invert_out[0:0] + attribute \src "libresoc.v:45738.3-45766.6" + wire $2\fus_oper_i_alu_alu0__is_32bit[0:0] + attribute \src "libresoc.v:45776.3-45804.6" + wire $2\fus_oper_i_alu_alu0__is_signed[0:0] + attribute \src "libresoc.v:45356.3-45385.6" + wire $2\fus_oper_i_alu_alu0__oe__oe[0:0] + attribute \src "libresoc.v:45356.3-45385.6" + wire $2\fus_oper_i_alu_alu0__oe__ok[0:0] + attribute \src "libresoc.v:45691.3-45719.6" + wire $2\fus_oper_i_alu_alu0__output_carry[0:0] + attribute \src "libresoc.v:45269.3-45298.6" + wire $2\fus_oper_i_alu_alu0__rc__ok[0:0] + attribute \src "libresoc.v:45269.3-45298.6" + wire $2\fus_oper_i_alu_alu0__rc__rc[0:0] + attribute \src "libresoc.v:45606.3-45634.6" + wire $2\fus_oper_i_alu_alu0__write_cr0[0:0] + attribute \src "libresoc.v:45500.3-45528.6" + wire $2\fus_oper_i_alu_alu0__zero_a[0:0] + attribute \src "libresoc.v:46192.3-46220.6" + wire width 64 $2\fus_oper_i_alu_branch0__cia[63:0] + attribute \src "libresoc.v:46277.3-46305.6" + wire width 12 $2\fus_oper_i_alu_branch0__fn_unit[11:0] + attribute \src "libresoc.v:46362.3-46391.6" + wire width 64 $2\fus_oper_i_alu_branch0__imm_data__data[63:0] + attribute \src "libresoc.v:46362.3-46391.6" + wire $2\fus_oper_i_alu_branch0__imm_data__ok[0:0] + attribute \src "libresoc.v:46315.3-46343.6" + wire width 32 $2\fus_oper_i_alu_branch0__insn[31:0] + attribute \src "libresoc.v:46239.3-46267.6" + wire width 7 $2\fus_oper_i_alu_branch0__insn_type[6:0] + attribute \src "libresoc.v:46457.3-46485.6" + wire $2\fus_oper_i_alu_branch0__is_32bit[0:0] + attribute \src "libresoc.v:46419.3-46447.6" + wire $2\fus_oper_i_alu_branch0__lk[0:0] + attribute \src "libresoc.v:46022.3-46050.6" + wire width 12 $2\fus_oper_i_alu_cr0__fn_unit[11:0] + attribute \src "libresoc.v:46069.3-46097.6" + wire width 32 $2\fus_oper_i_alu_cr0__insn[31:0] + attribute \src "libresoc.v:45984.3-46012.6" + wire width 7 $2\fus_oper_i_alu_cr0__insn_type[6:0] + attribute \src "libresoc.v:43158.3-43186.6" + wire width 4 $2\fus_oper_i_alu_div0__data_len[3:0] + attribute \src "libresoc.v:42807.3-42835.6" + wire width 12 $2\fus_oper_i_alu_div0__fn_unit[11:0] + attribute \src "libresoc.v:42836.3-42865.6" + wire width 64 $2\fus_oper_i_alu_div0__imm_data__data[63:0] + attribute \src "libresoc.v:42836.3-42865.6" + wire $2\fus_oper_i_alu_div0__imm_data__ok[0:0] + attribute \src "libresoc.v:42984.3-43012.6" + wire width 2 $2\fus_oper_i_alu_div0__input_carry[1:0] + attribute \src "libresoc.v:43187.3-43215.6" + wire width 32 $2\fus_oper_i_alu_div0__insn[31:0] + attribute \src "libresoc.v:42778.3-42806.6" + wire width 7 $2\fus_oper_i_alu_div0__insn_type[6:0] + attribute \src "libresoc.v:42926.3-42954.6" + wire $2\fus_oper_i_alu_div0__invert_in[0:0] + attribute \src "libresoc.v:43013.3-43041.6" + wire $2\fus_oper_i_alu_div0__invert_out[0:0] + attribute \src "libresoc.v:43100.3-43128.6" + wire $2\fus_oper_i_alu_div0__is_32bit[0:0] + attribute \src "libresoc.v:43129.3-43157.6" + wire $2\fus_oper_i_alu_div0__is_signed[0:0] + attribute \src "libresoc.v:42896.3-42925.6" + wire $2\fus_oper_i_alu_div0__oe__oe[0:0] + attribute \src "libresoc.v:42896.3-42925.6" + wire $2\fus_oper_i_alu_div0__oe__ok[0:0] + attribute \src "libresoc.v:43071.3-43099.6" + wire $2\fus_oper_i_alu_div0__output_carry[0:0] + attribute \src "libresoc.v:42866.3-42895.6" + wire $2\fus_oper_i_alu_div0__rc__ok[0:0] + attribute \src "libresoc.v:42866.3-42895.6" + wire $2\fus_oper_i_alu_div0__rc__rc[0:0] + attribute \src "libresoc.v:43042.3-43070.6" + wire $2\fus_oper_i_alu_div0__write_cr0[0:0] + attribute \src "libresoc.v:42955.3-42983.6" + wire $2\fus_oper_i_alu_div0__zero_a[0:0] + attribute \src "libresoc.v:47277.3-47305.6" + wire width 4 $2\fus_oper_i_alu_logical0__data_len[3:0] + attribute \src "libresoc.v:46926.3-46954.6" + wire width 12 $2\fus_oper_i_alu_logical0__fn_unit[11:0] + attribute \src "libresoc.v:46955.3-46984.6" + wire width 64 $2\fus_oper_i_alu_logical0__imm_data__data[63:0] + attribute \src "libresoc.v:46955.3-46984.6" + wire $2\fus_oper_i_alu_logical0__imm_data__ok[0:0] + attribute \src "libresoc.v:47103.3-47131.6" + wire width 2 $2\fus_oper_i_alu_logical0__input_carry[1:0] + attribute \src "libresoc.v:47306.3-47334.6" + wire width 32 $2\fus_oper_i_alu_logical0__insn[31:0] + attribute \src "libresoc.v:46897.3-46925.6" + wire width 7 $2\fus_oper_i_alu_logical0__insn_type[6:0] + attribute \src "libresoc.v:47045.3-47073.6" + wire $2\fus_oper_i_alu_logical0__invert_in[0:0] + attribute \src "libresoc.v:47132.3-47160.6" + wire $2\fus_oper_i_alu_logical0__invert_out[0:0] + attribute \src "libresoc.v:47219.3-47247.6" + wire $2\fus_oper_i_alu_logical0__is_32bit[0:0] + attribute \src "libresoc.v:47248.3-47276.6" + wire $2\fus_oper_i_alu_logical0__is_signed[0:0] + attribute \src "libresoc.v:47015.3-47044.6" + wire $2\fus_oper_i_alu_logical0__oe__oe[0:0] + attribute \src "libresoc.v:47015.3-47044.6" + wire $2\fus_oper_i_alu_logical0__oe__ok[0:0] + attribute \src "libresoc.v:47190.3-47218.6" + wire $2\fus_oper_i_alu_logical0__output_carry[0:0] + attribute \src "libresoc.v:46985.3-47014.6" + wire $2\fus_oper_i_alu_logical0__rc__ok[0:0] + attribute \src "libresoc.v:46985.3-47014.6" + wire $2\fus_oper_i_alu_logical0__rc__rc[0:0] + attribute \src "libresoc.v:47161.3-47189.6" + wire $2\fus_oper_i_alu_logical0__write_cr0[0:0] + attribute \src "libresoc.v:47074.3-47102.6" + wire $2\fus_oper_i_alu_logical0__zero_a[0:0] + attribute \src "libresoc.v:43303.3-43331.6" + wire width 12 $2\fus_oper_i_alu_mul0__fn_unit[11:0] + attribute \src "libresoc.v:43332.3-43361.6" + wire width 64 $2\fus_oper_i_alu_mul0__imm_data__data[63:0] + attribute \src "libresoc.v:43332.3-43361.6" + wire $2\fus_oper_i_alu_mul0__imm_data__ok[0:0] + attribute \src "libresoc.v:43509.3-43537.6" + wire width 32 $2\fus_oper_i_alu_mul0__insn[31:0] + attribute \src "libresoc.v:43274.3-43302.6" + wire width 7 $2\fus_oper_i_alu_mul0__insn_type[6:0] + attribute \src "libresoc.v:43451.3-43479.6" + wire $2\fus_oper_i_alu_mul0__is_32bit[0:0] + attribute \src "libresoc.v:43480.3-43508.6" + wire $2\fus_oper_i_alu_mul0__is_signed[0:0] + attribute \src "libresoc.v:43392.3-43421.6" + wire $2\fus_oper_i_alu_mul0__oe__oe[0:0] + attribute \src "libresoc.v:43392.3-43421.6" + wire $2\fus_oper_i_alu_mul0__oe__ok[0:0] + attribute \src "libresoc.v:43362.3-43391.6" + wire $2\fus_oper_i_alu_mul0__rc__ok[0:0] + attribute \src "libresoc.v:43362.3-43391.6" + wire $2\fus_oper_i_alu_mul0__rc__rc[0:0] + attribute \src "libresoc.v:43422.3-43450.6" + wire $2\fus_oper_i_alu_mul0__write_cr0[0:0] + attribute \src "libresoc.v:43625.3-43653.6" + wire width 12 $2\fus_oper_i_alu_shift_rot0__fn_unit[11:0] + attribute \src "libresoc.v:43654.3-43683.6" + wire width 64 $2\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] + attribute \src "libresoc.v:43654.3-43683.6" + wire $2\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] + attribute \src "libresoc.v:43773.3-43801.6" + wire width 2 $2\fus_oper_i_alu_shift_rot0__input_carry[1:0] + attribute \src "libresoc.v:43831.3-43859.6" + wire $2\fus_oper_i_alu_shift_rot0__input_cr[0:0] + attribute \src "libresoc.v:43947.3-43975.6" + wire width 32 $2\fus_oper_i_alu_shift_rot0__insn[31:0] + attribute \src "libresoc.v:43596.3-43624.6" + wire width 7 $2\fus_oper_i_alu_shift_rot0__insn_type[6:0] + attribute \src "libresoc.v:43889.3-43917.6" + wire $2\fus_oper_i_alu_shift_rot0__is_32bit[0:0] + attribute \src "libresoc.v:43918.3-43946.6" + wire $2\fus_oper_i_alu_shift_rot0__is_signed[0:0] + attribute \src "libresoc.v:43714.3-43743.6" + wire $2\fus_oper_i_alu_shift_rot0__oe__oe[0:0] + attribute \src "libresoc.v:43714.3-43743.6" + wire $2\fus_oper_i_alu_shift_rot0__oe__ok[0:0] + attribute \src "libresoc.v:43802.3-43830.6" + wire $2\fus_oper_i_alu_shift_rot0__output_carry[0:0] + attribute \src "libresoc.v:43860.3-43888.6" + wire $2\fus_oper_i_alu_shift_rot0__output_cr[0:0] + attribute \src "libresoc.v:43684.3-43713.6" + wire $2\fus_oper_i_alu_shift_rot0__rc__ok[0:0] + attribute \src "libresoc.v:43684.3-43713.6" + wire $2\fus_oper_i_alu_shift_rot0__rc__rc[0:0] + attribute \src "libresoc.v:43744.3-43772.6" + wire $2\fus_oper_i_alu_shift_rot0__write_cr0[0:0] + attribute \src "libresoc.v:47422.3-47450.6" + wire width 12 $2\fus_oper_i_alu_spr0__fn_unit[11:0] + attribute \src "libresoc.v:47451.3-47479.6" + wire width 32 $2\fus_oper_i_alu_spr0__insn[31:0] + attribute \src "libresoc.v:47393.3-47421.6" + wire width 7 $2\fus_oper_i_alu_spr0__insn_type[6:0] + attribute \src "libresoc.v:42691.3-42719.6" + wire $2\fus_oper_i_alu_spr0__is_32bit[0:0] + attribute \src "libresoc.v:46723.3-46751.6" + wire width 64 $2\fus_oper_i_alu_trap0__cia[63:0] + attribute \src "libresoc.v:46627.3-46655.6" + wire width 12 $2\fus_oper_i_alu_trap0__fn_unit[11:0] + attribute \src "libresoc.v:46665.3-46693.6" + wire width 32 $2\fus_oper_i_alu_trap0__insn[31:0] + attribute \src "libresoc.v:46589.3-46617.6" + wire width 7 $2\fus_oper_i_alu_trap0__insn_type[6:0] + attribute \src "libresoc.v:46752.3-46780.6" + wire $2\fus_oper_i_alu_trap0__is_32bit[0:0] + attribute \src "libresoc.v:46694.3-46722.6" + wire width 64 $2\fus_oper_i_alu_trap0__msr[63:0] + attribute \src "libresoc.v:46810.3-46838.6" + wire width 13 $2\fus_oper_i_alu_trap0__trapaddr[12:0] + attribute \src "libresoc.v:46781.3-46809.6" + wire width 7 $2\fus_oper_i_alu_trap0__traptype[6:0] + attribute \src "libresoc.v:44298.3-44326.6" + wire $2\fus_oper_i_ldst_ldst0__byte_reverse[0:0] + attribute \src "libresoc.v:44269.3-44297.6" + wire width 4 $2\fus_oper_i_ldst_ldst0__data_len[3:0] + attribute \src "libresoc.v:44063.3-44091.6" + wire width 12 $2\fus_oper_i_ldst_ldst0__fn_unit[11:0] + attribute \src "libresoc.v:44092.3-44121.6" + wire width 64 $2\fus_oper_i_ldst_ldst0__imm_data__data[63:0] + attribute \src "libresoc.v:44092.3-44121.6" + wire $2\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] + attribute \src "libresoc.v:44385.3-44413.6" + wire width 32 $2\fus_oper_i_ldst_ldst0__insn[31:0] + attribute \src "libresoc.v:44034.3-44062.6" + wire width 7 $2\fus_oper_i_ldst_ldst0__insn_type[6:0] + attribute \src "libresoc.v:44211.3-44239.6" + wire $2\fus_oper_i_ldst_ldst0__is_32bit[0:0] + attribute \src "libresoc.v:44240.3-44268.6" + wire $2\fus_oper_i_ldst_ldst0__is_signed[0:0] + attribute \src "libresoc.v:44356.3-44384.6" + wire width 2 $2\fus_oper_i_ldst_ldst0__ldst_mode[1:0] + attribute \src "libresoc.v:44181.3-44210.6" + wire $2\fus_oper_i_ldst_ldst0__oe__oe[0:0] + attribute \src "libresoc.v:44181.3-44210.6" + wire $2\fus_oper_i_ldst_ldst0__oe__ok[0:0] + attribute \src "libresoc.v:44151.3-44180.6" + wire $2\fus_oper_i_ldst_ldst0__rc__ok[0:0] + attribute \src "libresoc.v:44151.3-44180.6" + wire $2\fus_oper_i_ldst_ldst0__rc__rc[0:0] + attribute \src "libresoc.v:44327.3-44355.6" + wire $2\fus_oper_i_ldst_ldst0__sign_extend[0:0] + attribute \src "libresoc.v:44122.3-44150.6" + wire $2\fus_oper_i_ldst_ldst0__zero_a[0:0] + attribute \src "libresoc.v:45017.3-45037.6" + wire $3\core_terminate_o$next[0:0]$2600 + attribute \src "libresoc.v:44888.3-44978.6" + wire $3\corebusy_o[0:0] + attribute \src "libresoc.v:44833.3-44859.6" + wire width 2 $3\counter$next[1:0]$2574 + attribute \src "libresoc.v:46839.3-46867.6" + wire $3\fus_cu_issue_i$10[0:0]$2872 + attribute \src "libresoc.v:47335.3-47363.6" + wire $3\fus_cu_issue_i$13[0:0]$2897 + attribute \src "libresoc.v:42720.3-42748.6" + wire $3\fus_cu_issue_i$16[0:0]$2366 + attribute \src "libresoc.v:43216.3-43244.6" + wire $3\fus_cu_issue_i$19[0:0]$2391 + attribute \src "libresoc.v:43538.3-43566.6" + wire $3\fus_cu_issue_i$22[0:0]$2410 + attribute \src "libresoc.v:43976.3-44004.6" + wire $3\fus_cu_issue_i$25[0:0]$2433 + attribute \src "libresoc.v:44414.3-44442.6" + wire $3\fus_cu_issue_i$28[0:0]$2456 + attribute \src "libresoc.v:46107.3-46135.6" + wire $3\fus_cu_issue_i$4[0:0]$2777 + attribute \src "libresoc.v:46504.3-46532.6" + wire $3\fus_cu_issue_i$7[0:0]$2839 + attribute \src "libresoc.v:45899.3-45927.6" + wire $3\fus_cu_issue_i[0:0] + attribute \src "libresoc.v:46868.3-46896.6" + wire width 4 $3\fus_cu_rdmaskn_i$12[3:0]$2877 + attribute \src "libresoc.v:47364.3-47392.6" + wire width 3 $3\fus_cu_rdmaskn_i$15[2:0]$2902 + attribute \src "libresoc.v:42749.3-42777.6" + wire width 6 $3\fus_cu_rdmaskn_i$18[5:0]$2371 + attribute \src "libresoc.v:43245.3-43273.6" + wire width 3 $3\fus_cu_rdmaskn_i$21[2:0]$2396 + attribute \src "libresoc.v:43567.3-43595.6" + wire width 3 $3\fus_cu_rdmaskn_i$24[2:0]$2415 + attribute \src "libresoc.v:44005.3-44033.6" + wire width 5 $3\fus_cu_rdmaskn_i$27[4:0]$2438 + attribute \src "libresoc.v:44443.3-44471.6" + wire width 3 $3\fus_cu_rdmaskn_i$30[2:0]$2461 + attribute \src "libresoc.v:46154.3-46182.6" + wire width 6 $3\fus_cu_rdmaskn_i$6[5:0]$2788 + attribute \src "libresoc.v:46542.3-46570.6" + wire width 3 $3\fus_cu_rdmaskn_i$9[2:0]$2847 + attribute \src "libresoc.v:45937.3-45965.6" + wire width 4 $3\fus_cu_rdmaskn_i[3:0] + attribute \src "libresoc.v:45814.3-45842.6" + wire width 4 $3\fus_oper_i_alu_alu0__data_len[3:0] + attribute \src "libresoc.v:45134.3-45162.6" + wire width 12 $3\fus_oper_i_alu_alu0__fn_unit[11:0] + attribute \src "libresoc.v:45201.3-45230.6" + wire width 64 $3\fus_oper_i_alu_alu0__imm_data__data[63:0] + attribute \src "libresoc.v:45201.3-45230.6" + wire $3\fus_oper_i_alu_alu0__imm_data__ok[0:0] + attribute \src "libresoc.v:45653.3-45681.6" + wire width 2 $3\fus_oper_i_alu_alu0__input_carry[1:0] + attribute \src "libresoc.v:45861.3-45889.6" + wire width 32 $3\fus_oper_i_alu_alu0__insn[31:0] + attribute \src "libresoc.v:45076.3-45104.6" + wire width 7 $3\fus_oper_i_alu_alu0__insn_type[6:0] + attribute \src "libresoc.v:45443.3-45471.6" + wire $3\fus_oper_i_alu_alu0__invert_in[0:0] + attribute \src "libresoc.v:45558.3-45586.6" + wire $3\fus_oper_i_alu_alu0__invert_out[0:0] + attribute \src "libresoc.v:45738.3-45766.6" + wire $3\fus_oper_i_alu_alu0__is_32bit[0:0] + attribute \src "libresoc.v:45776.3-45804.6" + wire $3\fus_oper_i_alu_alu0__is_signed[0:0] + attribute \src "libresoc.v:45356.3-45385.6" + wire $3\fus_oper_i_alu_alu0__oe__oe[0:0] + attribute \src "libresoc.v:45356.3-45385.6" + wire $3\fus_oper_i_alu_alu0__oe__ok[0:0] + attribute \src "libresoc.v:45691.3-45719.6" + wire $3\fus_oper_i_alu_alu0__output_carry[0:0] + attribute \src "libresoc.v:45269.3-45298.6" + wire $3\fus_oper_i_alu_alu0__rc__ok[0:0] + attribute \src "libresoc.v:45269.3-45298.6" + wire $3\fus_oper_i_alu_alu0__rc__rc[0:0] + attribute \src "libresoc.v:45606.3-45634.6" + wire $3\fus_oper_i_alu_alu0__write_cr0[0:0] + attribute \src "libresoc.v:45500.3-45528.6" + wire $3\fus_oper_i_alu_alu0__zero_a[0:0] + attribute \src "libresoc.v:46192.3-46220.6" + wire width 64 $3\fus_oper_i_alu_branch0__cia[63:0] + attribute \src "libresoc.v:46277.3-46305.6" + wire width 12 $3\fus_oper_i_alu_branch0__fn_unit[11:0] + attribute \src "libresoc.v:46362.3-46391.6" + wire width 64 $3\fus_oper_i_alu_branch0__imm_data__data[63:0] + attribute \src "libresoc.v:46362.3-46391.6" + wire $3\fus_oper_i_alu_branch0__imm_data__ok[0:0] + attribute \src "libresoc.v:46315.3-46343.6" + wire width 32 $3\fus_oper_i_alu_branch0__insn[31:0] + attribute \src "libresoc.v:46239.3-46267.6" + wire width 7 $3\fus_oper_i_alu_branch0__insn_type[6:0] + attribute \src "libresoc.v:46457.3-46485.6" + wire $3\fus_oper_i_alu_branch0__is_32bit[0:0] + attribute \src "libresoc.v:46419.3-46447.6" + wire $3\fus_oper_i_alu_branch0__lk[0:0] + attribute \src "libresoc.v:46022.3-46050.6" + wire width 12 $3\fus_oper_i_alu_cr0__fn_unit[11:0] + attribute \src "libresoc.v:46069.3-46097.6" + wire width 32 $3\fus_oper_i_alu_cr0__insn[31:0] + attribute \src "libresoc.v:45984.3-46012.6" + wire width 7 $3\fus_oper_i_alu_cr0__insn_type[6:0] + attribute \src "libresoc.v:43158.3-43186.6" + wire width 4 $3\fus_oper_i_alu_div0__data_len[3:0] + attribute \src "libresoc.v:42807.3-42835.6" + wire width 12 $3\fus_oper_i_alu_div0__fn_unit[11:0] + attribute \src "libresoc.v:42836.3-42865.6" + wire width 64 $3\fus_oper_i_alu_div0__imm_data__data[63:0] + attribute \src "libresoc.v:42836.3-42865.6" + wire $3\fus_oper_i_alu_div0__imm_data__ok[0:0] + attribute \src "libresoc.v:42984.3-43012.6" + wire width 2 $3\fus_oper_i_alu_div0__input_carry[1:0] + attribute \src "libresoc.v:43187.3-43215.6" + wire width 32 $3\fus_oper_i_alu_div0__insn[31:0] + attribute \src "libresoc.v:42778.3-42806.6" + wire width 7 $3\fus_oper_i_alu_div0__insn_type[6:0] + attribute \src "libresoc.v:42926.3-42954.6" + wire $3\fus_oper_i_alu_div0__invert_in[0:0] + attribute \src "libresoc.v:43013.3-43041.6" + wire $3\fus_oper_i_alu_div0__invert_out[0:0] + attribute \src "libresoc.v:43100.3-43128.6" + wire $3\fus_oper_i_alu_div0__is_32bit[0:0] + attribute \src "libresoc.v:43129.3-43157.6" + wire $3\fus_oper_i_alu_div0__is_signed[0:0] + attribute \src "libresoc.v:42896.3-42925.6" + wire $3\fus_oper_i_alu_div0__oe__oe[0:0] + attribute \src "libresoc.v:42896.3-42925.6" + wire $3\fus_oper_i_alu_div0__oe__ok[0:0] + attribute \src "libresoc.v:43071.3-43099.6" + wire $3\fus_oper_i_alu_div0__output_carry[0:0] + attribute \src "libresoc.v:42866.3-42895.6" + wire $3\fus_oper_i_alu_div0__rc__ok[0:0] + attribute \src "libresoc.v:42866.3-42895.6" + wire $3\fus_oper_i_alu_div0__rc__rc[0:0] + attribute \src "libresoc.v:43042.3-43070.6" + wire $3\fus_oper_i_alu_div0__write_cr0[0:0] + attribute \src "libresoc.v:42955.3-42983.6" + wire $3\fus_oper_i_alu_div0__zero_a[0:0] + attribute \src "libresoc.v:47277.3-47305.6" + wire width 4 $3\fus_oper_i_alu_logical0__data_len[3:0] + attribute \src "libresoc.v:46926.3-46954.6" + wire width 12 $3\fus_oper_i_alu_logical0__fn_unit[11:0] + attribute \src "libresoc.v:46955.3-46984.6" + wire width 64 $3\fus_oper_i_alu_logical0__imm_data__data[63:0] + attribute \src "libresoc.v:46955.3-46984.6" + wire $3\fus_oper_i_alu_logical0__imm_data__ok[0:0] + attribute \src "libresoc.v:47103.3-47131.6" + wire width 2 $3\fus_oper_i_alu_logical0__input_carry[1:0] + attribute \src "libresoc.v:47306.3-47334.6" + wire width 32 $3\fus_oper_i_alu_logical0__insn[31:0] + attribute \src "libresoc.v:46897.3-46925.6" + wire width 7 $3\fus_oper_i_alu_logical0__insn_type[6:0] + attribute \src "libresoc.v:47045.3-47073.6" + wire $3\fus_oper_i_alu_logical0__invert_in[0:0] + attribute \src "libresoc.v:47132.3-47160.6" + wire $3\fus_oper_i_alu_logical0__invert_out[0:0] + attribute \src "libresoc.v:47219.3-47247.6" + wire $3\fus_oper_i_alu_logical0__is_32bit[0:0] + attribute \src "libresoc.v:47248.3-47276.6" + wire $3\fus_oper_i_alu_logical0__is_signed[0:0] + attribute \src "libresoc.v:47015.3-47044.6" + wire $3\fus_oper_i_alu_logical0__oe__oe[0:0] + attribute \src "libresoc.v:47015.3-47044.6" + wire $3\fus_oper_i_alu_logical0__oe__ok[0:0] + attribute \src "libresoc.v:47190.3-47218.6" + wire $3\fus_oper_i_alu_logical0__output_carry[0:0] + attribute \src "libresoc.v:46985.3-47014.6" + wire $3\fus_oper_i_alu_logical0__rc__ok[0:0] + attribute \src "libresoc.v:46985.3-47014.6" + wire $3\fus_oper_i_alu_logical0__rc__rc[0:0] + attribute \src "libresoc.v:47161.3-47189.6" + wire $3\fus_oper_i_alu_logical0__write_cr0[0:0] + attribute \src "libresoc.v:47074.3-47102.6" + wire $3\fus_oper_i_alu_logical0__zero_a[0:0] + attribute \src "libresoc.v:43303.3-43331.6" + wire width 12 $3\fus_oper_i_alu_mul0__fn_unit[11:0] + attribute \src "libresoc.v:43332.3-43361.6" + wire width 64 $3\fus_oper_i_alu_mul0__imm_data__data[63:0] + attribute \src "libresoc.v:43332.3-43361.6" + wire $3\fus_oper_i_alu_mul0__imm_data__ok[0:0] + attribute \src "libresoc.v:43509.3-43537.6" + wire width 32 $3\fus_oper_i_alu_mul0__insn[31:0] + attribute \src "libresoc.v:43274.3-43302.6" + wire width 7 $3\fus_oper_i_alu_mul0__insn_type[6:0] + attribute \src "libresoc.v:43451.3-43479.6" + wire $3\fus_oper_i_alu_mul0__is_32bit[0:0] + attribute \src "libresoc.v:43480.3-43508.6" + wire $3\fus_oper_i_alu_mul0__is_signed[0:0] + attribute \src "libresoc.v:43392.3-43421.6" + wire $3\fus_oper_i_alu_mul0__oe__oe[0:0] + attribute \src "libresoc.v:43392.3-43421.6" + wire $3\fus_oper_i_alu_mul0__oe__ok[0:0] + attribute \src "libresoc.v:43362.3-43391.6" + wire $3\fus_oper_i_alu_mul0__rc__ok[0:0] + attribute \src "libresoc.v:43362.3-43391.6" + wire $3\fus_oper_i_alu_mul0__rc__rc[0:0] + attribute \src "libresoc.v:43422.3-43450.6" + wire $3\fus_oper_i_alu_mul0__write_cr0[0:0] + attribute \src "libresoc.v:43625.3-43653.6" + wire width 12 $3\fus_oper_i_alu_shift_rot0__fn_unit[11:0] + attribute \src "libresoc.v:43654.3-43683.6" + wire width 64 $3\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] + attribute \src "libresoc.v:43654.3-43683.6" + wire $3\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] + attribute \src "libresoc.v:43773.3-43801.6" + wire width 2 $3\fus_oper_i_alu_shift_rot0__input_carry[1:0] + attribute \src "libresoc.v:43831.3-43859.6" + wire $3\fus_oper_i_alu_shift_rot0__input_cr[0:0] + attribute \src "libresoc.v:43947.3-43975.6" + wire width 32 $3\fus_oper_i_alu_shift_rot0__insn[31:0] + attribute \src "libresoc.v:43596.3-43624.6" + wire width 7 $3\fus_oper_i_alu_shift_rot0__insn_type[6:0] + attribute \src "libresoc.v:43889.3-43917.6" + wire $3\fus_oper_i_alu_shift_rot0__is_32bit[0:0] + attribute \src "libresoc.v:43918.3-43946.6" + wire $3\fus_oper_i_alu_shift_rot0__is_signed[0:0] + attribute \src "libresoc.v:43714.3-43743.6" + wire $3\fus_oper_i_alu_shift_rot0__oe__oe[0:0] + attribute \src "libresoc.v:43714.3-43743.6" + wire $3\fus_oper_i_alu_shift_rot0__oe__ok[0:0] + attribute \src "libresoc.v:43802.3-43830.6" + wire $3\fus_oper_i_alu_shift_rot0__output_carry[0:0] + attribute \src "libresoc.v:43860.3-43888.6" + wire $3\fus_oper_i_alu_shift_rot0__output_cr[0:0] + attribute \src "libresoc.v:43684.3-43713.6" + wire $3\fus_oper_i_alu_shift_rot0__rc__ok[0:0] + attribute \src "libresoc.v:43684.3-43713.6" + wire $3\fus_oper_i_alu_shift_rot0__rc__rc[0:0] + attribute \src "libresoc.v:43744.3-43772.6" + wire $3\fus_oper_i_alu_shift_rot0__write_cr0[0:0] + attribute \src "libresoc.v:47422.3-47450.6" + wire width 12 $3\fus_oper_i_alu_spr0__fn_unit[11:0] + attribute \src "libresoc.v:47451.3-47479.6" + wire width 32 $3\fus_oper_i_alu_spr0__insn[31:0] + attribute \src "libresoc.v:47393.3-47421.6" + wire width 7 $3\fus_oper_i_alu_spr0__insn_type[6:0] + attribute \src "libresoc.v:42691.3-42719.6" + wire $3\fus_oper_i_alu_spr0__is_32bit[0:0] + attribute \src "libresoc.v:46723.3-46751.6" + wire width 64 $3\fus_oper_i_alu_trap0__cia[63:0] + attribute \src "libresoc.v:46627.3-46655.6" + wire width 12 $3\fus_oper_i_alu_trap0__fn_unit[11:0] + attribute \src "libresoc.v:46665.3-46693.6" + wire width 32 $3\fus_oper_i_alu_trap0__insn[31:0] + attribute \src "libresoc.v:46589.3-46617.6" + wire width 7 $3\fus_oper_i_alu_trap0__insn_type[6:0] + attribute \src "libresoc.v:46752.3-46780.6" + wire $3\fus_oper_i_alu_trap0__is_32bit[0:0] + attribute \src "libresoc.v:46694.3-46722.6" + wire width 64 $3\fus_oper_i_alu_trap0__msr[63:0] + attribute \src "libresoc.v:46810.3-46838.6" + wire width 13 $3\fus_oper_i_alu_trap0__trapaddr[12:0] + attribute \src "libresoc.v:46781.3-46809.6" + wire width 7 $3\fus_oper_i_alu_trap0__traptype[6:0] + attribute \src "libresoc.v:44298.3-44326.6" + wire $3\fus_oper_i_ldst_ldst0__byte_reverse[0:0] + attribute \src "libresoc.v:44269.3-44297.6" + wire width 4 $3\fus_oper_i_ldst_ldst0__data_len[3:0] + attribute \src "libresoc.v:44063.3-44091.6" + wire width 12 $3\fus_oper_i_ldst_ldst0__fn_unit[11:0] + attribute \src "libresoc.v:44092.3-44121.6" + wire width 64 $3\fus_oper_i_ldst_ldst0__imm_data__data[63:0] + attribute \src "libresoc.v:44092.3-44121.6" + wire $3\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] + attribute \src "libresoc.v:44385.3-44413.6" + wire width 32 $3\fus_oper_i_ldst_ldst0__insn[31:0] + attribute \src "libresoc.v:44034.3-44062.6" + wire width 7 $3\fus_oper_i_ldst_ldst0__insn_type[6:0] + attribute \src "libresoc.v:44211.3-44239.6" + wire $3\fus_oper_i_ldst_ldst0__is_32bit[0:0] + attribute \src "libresoc.v:44240.3-44268.6" + wire $3\fus_oper_i_ldst_ldst0__is_signed[0:0] + attribute \src "libresoc.v:44356.3-44384.6" + wire width 2 $3\fus_oper_i_ldst_ldst0__ldst_mode[1:0] + attribute \src "libresoc.v:44181.3-44210.6" + wire $3\fus_oper_i_ldst_ldst0__oe__oe[0:0] + attribute \src "libresoc.v:44181.3-44210.6" + wire $3\fus_oper_i_ldst_ldst0__oe__ok[0:0] + attribute \src "libresoc.v:44151.3-44180.6" + wire $3\fus_oper_i_ldst_ldst0__rc__ok[0:0] + attribute \src "libresoc.v:44151.3-44180.6" + wire $3\fus_oper_i_ldst_ldst0__rc__rc[0:0] + attribute \src "libresoc.v:44327.3-44355.6" + wire $3\fus_oper_i_ldst_ldst0__sign_extend[0:0] + attribute \src "libresoc.v:44122.3-44150.6" + wire $3\fus_oper_i_ldst_ldst0__zero_a[0:0] + attribute \src "libresoc.v:44888.3-44978.6" + wire $4\corebusy_o[0:0] + attribute \src "libresoc.v:44833.3-44859.6" + wire width 2 $4\counter$next[1:0]$2575 + attribute \src "libresoc.v:44888.3-44978.6" + wire $5\corebusy_o[0:0] + attribute \src "libresoc.v:44888.3-44978.6" + wire $6\corebusy_o[0:0] + attribute \src "libresoc.v:44888.3-44978.6" + wire $7\corebusy_o[0:0] + attribute \src "libresoc.v:44888.3-44978.6" + wire $8\corebusy_o[0:0] + attribute \src "libresoc.v:44888.3-44978.6" + wire $9\corebusy_o[0:0] + attribute \src "libresoc.v:41098.20-41098.122" + wire $and$libresoc.v:41098$1515_Y + attribute \src "libresoc.v:41099.20-41099.126" + wire $and$libresoc.v:41099$1516_Y + attribute \src "libresoc.v:41101.20-41101.110" + wire $and$libresoc.v:41101$1518_Y + attribute \src "libresoc.v:41102.20-41102.123" + wire $and$libresoc.v:41102$1519_Y + attribute \src "libresoc.v:41104.20-41104.122" + wire $and$libresoc.v:41104$1521_Y + attribute \src "libresoc.v:41105.20-41105.126" + wire $and$libresoc.v:41105$1522_Y + attribute \src "libresoc.v:41107.20-41107.110" + wire $and$libresoc.v:41107$1524_Y + attribute \src "libresoc.v:41108.20-41108.123" + wire $and$libresoc.v:41108$1525_Y + attribute \src "libresoc.v:41110.20-41110.122" + wire $and$libresoc.v:41110$1527_Y + attribute \src "libresoc.v:41111.20-41111.126" + wire $and$libresoc.v:41111$1528_Y + attribute \src "libresoc.v:41113.20-41113.110" + wire $and$libresoc.v:41113$1530_Y + attribute \src "libresoc.v:41114.20-41114.123" + wire $and$libresoc.v:41114$1531_Y + attribute \src "libresoc.v:41116.20-41116.122" + wire $and$libresoc.v:41116$1533_Y + attribute \src "libresoc.v:41117.20-41117.126" + wire $and$libresoc.v:41117$1534_Y + attribute \src "libresoc.v:41119.20-41119.110" + wire $and$libresoc.v:41119$1536_Y + attribute \src "libresoc.v:41120.20-41120.123" + wire $and$libresoc.v:41120$1537_Y + attribute \src "libresoc.v:41122.20-41122.123" + wire $and$libresoc.v:41122$1539_Y + attribute \src "libresoc.v:41123.20-41123.126" + wire $and$libresoc.v:41123$1540_Y + attribute \src "libresoc.v:41125.20-41125.110" + wire $and$libresoc.v:41125$1542_Y + attribute \src "libresoc.v:41126.20-41126.123" + wire $and$libresoc.v:41126$1543_Y + attribute \src "libresoc.v:41128.20-41128.113" + wire $and$libresoc.v:41128$1545_Y + attribute \src "libresoc.v:41129.20-41129.126" + wire $and$libresoc.v:41129$1546_Y + attribute \src "libresoc.v:41131.20-41131.110" + wire $and$libresoc.v:41131$1548_Y + attribute \src "libresoc.v:41132.20-41132.123" + wire $and$libresoc.v:41132$1549_Y + attribute \src "libresoc.v:41134.20-41134.114" + wire $and$libresoc.v:41134$1551_Y + attribute \src "libresoc.v:41135.20-41135.126" + wire $and$libresoc.v:41135$1552_Y + attribute \src "libresoc.v:41137.20-41137.110" + wire $and$libresoc.v:41137$1554_Y + attribute \src "libresoc.v:41138.20-41138.123" + wire $and$libresoc.v:41138$1555_Y + attribute \src "libresoc.v:41167.20-41167.122" + wire $and$libresoc.v:41167$1584_Y + attribute \src "libresoc.v:41168.20-41168.128" + wire $and$libresoc.v:41168$1585_Y + attribute \src "libresoc.v:41169.20-41169.133" + wire $and$libresoc.v:41169$1586_Y + attribute \src "libresoc.v:41171.20-41171.110" + wire $and$libresoc.v:41171$1588_Y + attribute \src "libresoc.v:41172.20-41172.128" + wire $and$libresoc.v:41172$1589_Y + attribute \src "libresoc.v:41174.20-41174.116" + wire $and$libresoc.v:41174$1591_Y + attribute \src "libresoc.v:41175.20-41175.123" + wire $and$libresoc.v:41175$1592_Y + attribute \src "libresoc.v:41176.20-41176.128" + wire $and$libresoc.v:41176$1593_Y + attribute \src "libresoc.v:41177.20-41177.128" + wire $and$libresoc.v:41177$1594_Y + attribute \src "libresoc.v:41178.20-41178.128" + wire $and$libresoc.v:41178$1595_Y + attribute \src "libresoc.v:41179.20-41179.128" + wire $and$libresoc.v:41179$1596_Y + attribute \src "libresoc.v:41180.20-41180.129" + wire $and$libresoc.v:41180$1597_Y + attribute \src "libresoc.v:41181.20-41181.130" + wire $and$libresoc.v:41181$1598_Y + attribute \src "libresoc.v:41183.20-41183.110" + wire $and$libresoc.v:41183$1600_Y + attribute \src "libresoc.v:41184.20-41184.125" + wire $and$libresoc.v:41184$1601_Y + attribute \src "libresoc.v:41188.20-41188.125" + wire $and$libresoc.v:41188$1605_Y + attribute \src "libresoc.v:41189.20-41189.130" + wire $and$libresoc.v:41189$1606_Y + attribute \src "libresoc.v:41191.20-41191.110" + wire $and$libresoc.v:41191$1608_Y + attribute \src "libresoc.v:41192.20-41192.125" + wire $and$libresoc.v:41192$1609_Y + attribute \src "libresoc.v:41196.20-41196.126" + wire $and$libresoc.v:41196$1613_Y + attribute \src "libresoc.v:41197.20-41197.130" + wire $and$libresoc.v:41197$1614_Y + attribute \src "libresoc.v:41199.20-41199.110" + wire $and$libresoc.v:41199$1616_Y + attribute \src "libresoc.v:41200.20-41200.125" + wire $and$libresoc.v:41200$1617_Y + attribute \src "libresoc.v:41204.20-41204.126" + wire $and$libresoc.v:41204$1621_Y + attribute \src "libresoc.v:41205.20-41205.130" + wire $and$libresoc.v:41205$1622_Y + attribute \src "libresoc.v:41207.20-41207.110" + wire $and$libresoc.v:41207$1624_Y + attribute \src "libresoc.v:41208.20-41208.125" + wire $and$libresoc.v:41208$1625_Y + attribute \src "libresoc.v:41212.20-41212.126" + wire $and$libresoc.v:41212$1629_Y + attribute \src "libresoc.v:41213.20-41213.130" + wire $and$libresoc.v:41213$1630_Y + attribute \src "libresoc.v:41215.20-41215.110" + wire $and$libresoc.v:41215$1632_Y + attribute \src "libresoc.v:41216.20-41216.125" + wire $and$libresoc.v:41216$1633_Y + attribute \src "libresoc.v:41220.20-41220.126" + wire $and$libresoc.v:41220$1637_Y + attribute \src "libresoc.v:41221.20-41221.130" + wire $and$libresoc.v:41221$1638_Y + attribute \src "libresoc.v:41223.20-41223.110" + wire $and$libresoc.v:41223$1640_Y + attribute \src "libresoc.v:41224.20-41224.125" + wire $and$libresoc.v:41224$1641_Y + attribute \src "libresoc.v:41238.20-41238.118" + wire $and$libresoc.v:41238$1655_Y + attribute \src "libresoc.v:41239.20-41239.123" + wire $and$libresoc.v:41239$1656_Y + attribute \src "libresoc.v:41240.20-41240.128" + wire $and$libresoc.v:41240$1657_Y + attribute \src "libresoc.v:41241.20-41241.129" + wire $and$libresoc.v:41241$1658_Y + attribute \src "libresoc.v:41242.20-41242.136" + wire $and$libresoc.v:41242$1659_Y + attribute \src "libresoc.v:41244.20-41244.110" + wire $and$libresoc.v:41244$1661_Y + attribute \src "libresoc.v:41245.20-41245.128" + wire $and$libresoc.v:41245$1662_Y + attribute \src "libresoc.v:41247.20-41247.128" + wire $and$libresoc.v:41247$1664_Y + attribute \src "libresoc.v:41248.20-41248.136" + wire $and$libresoc.v:41248$1665_Y + attribute \src "libresoc.v:41250.20-41250.110" + wire $and$libresoc.v:41250$1667_Y + attribute \src "libresoc.v:41251.20-41251.128" + wire $and$libresoc.v:41251$1668_Y + attribute \src "libresoc.v:41253.20-41253.128" + wire $and$libresoc.v:41253$1670_Y + attribute \src "libresoc.v:41254.20-41254.136" + wire $and$libresoc.v:41254$1671_Y + attribute \src "libresoc.v:41256.20-41256.110" + wire $and$libresoc.v:41256$1673_Y + attribute \src "libresoc.v:41257.20-41257.128" + wire $and$libresoc.v:41257$1674_Y + attribute \src "libresoc.v:41264.20-41264.118" + wire $and$libresoc.v:41264$1682_Y + attribute \src "libresoc.v:41265.20-41265.123" + wire $and$libresoc.v:41265$1683_Y + attribute \src "libresoc.v:41266.20-41266.128" + wire $and$libresoc.v:41266$1684_Y + attribute \src "libresoc.v:41267.20-41267.128" + wire $and$libresoc.v:41267$1685_Y + attribute \src "libresoc.v:41268.20-41268.128" + wire $and$libresoc.v:41268$1686_Y + attribute \src "libresoc.v:41269.20-41269.136" + wire $and$libresoc.v:41269$1687_Y + attribute \src "libresoc.v:41271.20-41271.110" + wire $and$libresoc.v:41271$1689_Y + attribute \src "libresoc.v:41272.20-41272.128" + wire $and$libresoc.v:41272$1690_Y + attribute \src "libresoc.v:41274.20-41274.128" + wire $and$libresoc.v:41274$1692_Y + attribute \src "libresoc.v:41275.20-41275.136" + wire $and$libresoc.v:41275$1693_Y + attribute \src "libresoc.v:41277.20-41277.110" + wire $and$libresoc.v:41277$1695_Y + attribute \src "libresoc.v:41278.20-41278.128" + wire $and$libresoc.v:41278$1696_Y + attribute \src "libresoc.v:41280.20-41280.128" + wire $and$libresoc.v:41280$1698_Y + attribute \src "libresoc.v:41281.20-41281.136" + wire $and$libresoc.v:41281$1699_Y + attribute \src "libresoc.v:41283.20-41283.110" + wire $and$libresoc.v:41283$1701_Y + attribute \src "libresoc.v:41284.20-41284.128" + wire $and$libresoc.v:41284$1702_Y + attribute \src "libresoc.v:41286.20-41286.128" + wire $and$libresoc.v:41286$1704_Y + attribute \src "libresoc.v:41287.20-41287.136" + wire $and$libresoc.v:41287$1705_Y + attribute \src "libresoc.v:41289.20-41289.110" + wire $and$libresoc.v:41289$1707_Y + attribute \src "libresoc.v:41290.20-41290.128" + wire $and$libresoc.v:41290$1708_Y + attribute \src "libresoc.v:41298.20-41298.118" + wire $and$libresoc.v:41298$1716_Y + attribute \src "libresoc.v:41299.20-41299.123" + wire $and$libresoc.v:41299$1717_Y + attribute \src "libresoc.v:41300.20-41300.128" + wire $and$libresoc.v:41300$1718_Y + attribute \src "libresoc.v:41301.20-41301.128" + wire $and$libresoc.v:41301$1719_Y + attribute \src "libresoc.v:41302.20-41302.128" + wire $and$libresoc.v:41302$1720_Y + attribute \src "libresoc.v:41303.20-41303.136" + wire $and$libresoc.v:41303$1721_Y + attribute \src "libresoc.v:41305.20-41305.110" + wire $and$libresoc.v:41305$1723_Y + attribute \src "libresoc.v:41306.20-41306.128" + wire $and$libresoc.v:41306$1724_Y + attribute \src "libresoc.v:41308.20-41308.128" + wire $and$libresoc.v:41308$1726_Y + attribute \src "libresoc.v:41309.20-41309.136" + wire $and$libresoc.v:41309$1727_Y + attribute \src "libresoc.v:41311.20-41311.110" + wire $and$libresoc.v:41311$1729_Y + attribute \src "libresoc.v:41312.20-41312.128" + wire $and$libresoc.v:41312$1730_Y + attribute \src "libresoc.v:41314.20-41314.128" + wire $and$libresoc.v:41314$1732_Y + attribute \src "libresoc.v:41315.20-41315.136" + wire $and$libresoc.v:41315$1733_Y + attribute \src "libresoc.v:41317.20-41317.110" + wire $and$libresoc.v:41317$1735_Y + attribute \src "libresoc.v:41318.20-41318.128" + wire $and$libresoc.v:41318$1736_Y + attribute \src "libresoc.v:41320.20-41320.128" + wire $and$libresoc.v:41320$1738_Y + attribute \src "libresoc.v:41321.20-41321.136" + wire $and$libresoc.v:41321$1739_Y + attribute \src "libresoc.v:41323.20-41323.110" + wire $and$libresoc.v:41323$1741_Y + attribute \src "libresoc.v:41324.20-41324.128" + wire $and$libresoc.v:41324$1742_Y + attribute \src "libresoc.v:41334.20-41334.120" + wire $and$libresoc.v:41334$1754_Y + attribute \src "libresoc.v:41335.20-41335.129" + wire $and$libresoc.v:41335$1755_Y + attribute \src "libresoc.v:41336.20-41336.128" + wire $and$libresoc.v:41336$1756_Y + attribute \src "libresoc.v:41337.20-41337.128" + wire $and$libresoc.v:41337$1757_Y + attribute \src "libresoc.v:41338.20-41338.129" + wire $and$libresoc.v:41338$1758_Y + attribute \src "libresoc.v:41339.20-41339.128" + wire $and$libresoc.v:41339$1759_Y + attribute \src "libresoc.v:41340.20-41340.136" + wire $and$libresoc.v:41340$1760_Y + attribute \src "libresoc.v:41342.20-41342.110" + wire $and$libresoc.v:41342$1762_Y + attribute \src "libresoc.v:41343.19-41343.112" + wire width 12 $and$libresoc.v:41343$1763_Y + attribute \src "libresoc.v:41344.20-41344.128" + wire $and$libresoc.v:41344$1764_Y + attribute \src "libresoc.v:41346.20-41346.127" + wire $and$libresoc.v:41346$1766_Y + attribute \src "libresoc.v:41348.20-41348.136" + wire $and$libresoc.v:41348$1768_Y + attribute \src "libresoc.v:41350.20-41350.110" + wire $and$libresoc.v:41350$1770_Y + attribute \src "libresoc.v:41351.20-41351.128" + wire $and$libresoc.v:41351$1771_Y + attribute \src "libresoc.v:41353.20-41353.127" + wire $and$libresoc.v:41353$1773_Y + attribute \src "libresoc.v:41354.20-41354.136" + wire $and$libresoc.v:41354$1774_Y + attribute \src "libresoc.v:41356.20-41356.110" + wire $and$libresoc.v:41356$1776_Y + attribute \src "libresoc.v:41357.20-41357.128" + wire $and$libresoc.v:41357$1777_Y + attribute \src "libresoc.v:41359.20-41359.120" + wire $and$libresoc.v:41359$1779_Y + attribute \src "libresoc.v:41360.19-41360.113" + wire width 12 $and$libresoc.v:41360$1780_Y + attribute \src "libresoc.v:41361.20-41361.136" + wire $and$libresoc.v:41361$1781_Y + attribute \src "libresoc.v:41363.20-41363.110" + wire $and$libresoc.v:41363$1783_Y + attribute \src "libresoc.v:41365.20-41365.128" + wire $and$libresoc.v:41365$1785_Y + attribute \src "libresoc.v:41367.20-41367.127" + wire $and$libresoc.v:41367$1787_Y + attribute \src "libresoc.v:41368.20-41368.136" + wire $and$libresoc.v:41368$1788_Y + attribute \src "libresoc.v:41370.20-41370.110" + wire $and$libresoc.v:41370$1790_Y + attribute \src "libresoc.v:41371.20-41371.128" + wire $and$libresoc.v:41371$1791_Y + attribute \src "libresoc.v:41378.19-41378.113" + wire width 12 $and$libresoc.v:41378$1798_Y + attribute \src "libresoc.v:41387.20-41387.118" + wire $and$libresoc.v:41387$1807_Y + attribute \src "libresoc.v:41388.20-41388.129" + wire $and$libresoc.v:41388$1808_Y + attribute \src "libresoc.v:41389.20-41389.128" + wire $and$libresoc.v:41389$1809_Y + attribute \src "libresoc.v:41390.20-41390.134" + wire $and$libresoc.v:41390$1810_Y + attribute \src "libresoc.v:41392.20-41392.110" + wire $and$libresoc.v:41392$1812_Y + attribute \src "libresoc.v:41393.20-41393.127" + wire $and$libresoc.v:41393$1813_Y + attribute \src "libresoc.v:41395.20-41395.125" + wire $and$libresoc.v:41395$1815_Y + attribute \src "libresoc.v:41396.20-41396.134" + wire $and$libresoc.v:41396$1816_Y + attribute \src "libresoc.v:41397.19-41397.113" + wire width 12 $and$libresoc.v:41397$1817_Y + attribute \src "libresoc.v:41399.20-41399.110" + wire $and$libresoc.v:41399$1819_Y + attribute \src "libresoc.v:41400.20-41400.127" + wire $and$libresoc.v:41400$1820_Y + attribute \src "libresoc.v:41406.20-41406.119" + wire $and$libresoc.v:41406$1827_Y + attribute \src "libresoc.v:41407.20-41407.128" + wire $and$libresoc.v:41407$1828_Y + attribute \src "libresoc.v:41408.20-41408.131" + wire $and$libresoc.v:41408$1829_Y + attribute \src "libresoc.v:41410.20-41410.110" + wire $and$libresoc.v:41410$1831_Y + attribute \src "libresoc.v:41411.20-41411.127" + wire $and$libresoc.v:41411$1832_Y + attribute \src "libresoc.v:41414.20-41414.120" + wire $and$libresoc.v:41414$1836_Y + attribute \src "libresoc.v:41415.20-41415.128" + wire $and$libresoc.v:41415$1837_Y + attribute \src "libresoc.v:41416.19-41416.113" + wire width 12 $and$libresoc.v:41416$1838_Y + attribute \src "libresoc.v:41417.20-41417.129" + wire $and$libresoc.v:41417$1839_Y + attribute \src "libresoc.v:41419.20-41419.110" + wire $and$libresoc.v:41419$1841_Y + attribute \src "libresoc.v:41421.20-41421.126" + wire $and$libresoc.v:41421$1843_Y + attribute \src "libresoc.v:41423.19-41423.115" + wire width 12 $and$libresoc.v:41423$1845_Y + attribute \src "libresoc.v:41425.19-41425.115" + wire width 12 $and$libresoc.v:41425$1847_Y + attribute \src "libresoc.v:41427.19-41427.114" + wire width 12 $and$libresoc.v:41427$1849_Y + attribute \src "libresoc.v:41429.19-41429.112" + wire width 12 $and$libresoc.v:41429$1851_Y + attribute \src "libresoc.v:41431.19-41431.112" + wire width 12 $and$libresoc.v:41431$1853_Y + attribute \src "libresoc.v:41436.19-41436.131" + wire $and$libresoc.v:41436$1858_Y + attribute \src "libresoc.v:41437.19-41437.119" + wire width 3 $and$libresoc.v:41437$1859_Y + attribute \src "libresoc.v:41440.19-41440.131" + wire $and$libresoc.v:41440$1862_Y + attribute \src "libresoc.v:41443.19-41443.119" + wire width 3 $and$libresoc.v:41443$1865_Y + attribute \src "libresoc.v:41450.19-41450.131" + wire $and$libresoc.v:41450$1872_Y + attribute \src "libresoc.v:41451.19-41451.119" + wire width 3 $and$libresoc.v:41451$1873_Y + attribute \src "libresoc.v:41454.19-41454.131" + wire $and$libresoc.v:41454$1876_Y + attribute \src "libresoc.v:41457.19-41457.131" + wire $and$libresoc.v:41457$1879_Y + attribute \src "libresoc.v:41458.19-41458.119" + wire width 3 $and$libresoc.v:41458$1880_Y + attribute \src "libresoc.v:41461.19-41461.131" + wire $and$libresoc.v:41461$1883_Y + attribute \src "libresoc.v:41463.19-41463.131" + wire $and$libresoc.v:41463$1885_Y + attribute \src "libresoc.v:41464.19-41464.119" + wire width 3 $and$libresoc.v:41464$1886_Y + attribute \src "libresoc.v:41468.19-41468.119" + wire width 3 $and$libresoc.v:41468$1890_Y + attribute \src "libresoc.v:41472.19-41472.131" + wire $and$libresoc.v:41472$1894_Y + attribute \src "libresoc.v:41473.19-41473.119" + wire width 3 $and$libresoc.v:41473$1895_Y + attribute \src "libresoc.v:41476.19-41476.131" + wire $and$libresoc.v:41476$1898_Y + attribute \src "libresoc.v:41479.19-41479.131" + wire $and$libresoc.v:41479$1901_Y + attribute \src "libresoc.v:41480.19-41480.119" + wire width 3 $and$libresoc.v:41480$1902_Y + attribute \src "libresoc.v:41483.19-41483.131" + wire $and$libresoc.v:41483$1905_Y + attribute \src "libresoc.v:41486.19-41486.131" + wire $and$libresoc.v:41486$1908_Y + attribute \src "libresoc.v:41487.19-41487.119" + wire width 3 $and$libresoc.v:41487$1909_Y + attribute \src "libresoc.v:41490.19-41490.131" + wire $and$libresoc.v:41490$1912_Y + attribute \src "libresoc.v:41493.19-41493.119" + wire width 3 $and$libresoc.v:41493$1915_Y + attribute \src "libresoc.v:41498.19-41498.122" + wire $and$libresoc.v:41498$1920_Y + attribute \src "libresoc.v:41499.19-41499.112" + wire $and$libresoc.v:41499$1921_Y + attribute \src "libresoc.v:41501.19-41501.102" + wire $and$libresoc.v:41501$1923_Y + attribute \src "libresoc.v:41502.19-41502.127" + wire $and$libresoc.v:41502$1924_Y + attribute \src "libresoc.v:41504.19-41504.127" + wire $and$libresoc.v:41504$1926_Y + attribute \src "libresoc.v:41505.19-41505.112" + wire $and$libresoc.v:41505$1927_Y + attribute \src "libresoc.v:41507.19-41507.102" + wire $and$libresoc.v:41507$1929_Y + attribute \src "libresoc.v:41508.19-41508.127" + wire $and$libresoc.v:41508$1930_Y + attribute \src "libresoc.v:41510.19-41510.127" + wire $and$libresoc.v:41510$1932_Y + attribute \src "libresoc.v:41511.19-41511.112" + wire $and$libresoc.v:41511$1933_Y + attribute \src "libresoc.v:41513.19-41513.102" + wire $and$libresoc.v:41513$1935_Y + attribute \src "libresoc.v:41514.19-41514.127" + wire $and$libresoc.v:41514$1936_Y + attribute \src "libresoc.v:41516.19-41516.127" + wire $and$libresoc.v:41516$1938_Y + attribute \src "libresoc.v:41517.19-41517.112" + wire $and$libresoc.v:41517$1939_Y + attribute \src "libresoc.v:41519.19-41519.102" + wire $and$libresoc.v:41519$1941_Y + attribute \src "libresoc.v:41520.19-41520.127" + wire $and$libresoc.v:41520$1942_Y + attribute \src "libresoc.v:41522.19-41522.127" + wire $and$libresoc.v:41522$1944_Y + attribute \src "libresoc.v:41523.19-41523.112" + wire $and$libresoc.v:41523$1945_Y + attribute \src "libresoc.v:41525.19-41525.102" + wire $and$libresoc.v:41525$1947_Y + attribute \src "libresoc.v:41526.19-41526.127" + wire $and$libresoc.v:41526$1948_Y + attribute \src "libresoc.v:41528.19-41528.127" + wire $and$libresoc.v:41528$1950_Y + attribute \src "libresoc.v:41529.19-41529.112" + wire $and$libresoc.v:41529$1951_Y + attribute \src "libresoc.v:41531.19-41531.102" + wire $and$libresoc.v:41531$1953_Y + attribute \src "libresoc.v:41532.19-41532.127" + wire $and$libresoc.v:41532$1954_Y + attribute \src "libresoc.v:41534.19-41534.127" + wire $and$libresoc.v:41534$1956_Y + attribute \src "libresoc.v:41535.19-41535.112" + wire $and$libresoc.v:41535$1957_Y + attribute \src "libresoc.v:41537.19-41537.102" + wire $and$libresoc.v:41537$1959_Y + attribute \src "libresoc.v:41538.19-41538.127" + wire $and$libresoc.v:41538$1960_Y + attribute \src "libresoc.v:41540.19-41540.127" + wire $and$libresoc.v:41540$1962_Y + attribute \src "libresoc.v:41541.19-41541.112" + wire $and$libresoc.v:41541$1963_Y + attribute \src "libresoc.v:41543.19-41543.102" + wire $and$libresoc.v:41543$1965_Y + attribute \src "libresoc.v:41544.19-41544.127" + wire $and$libresoc.v:41544$1966_Y + attribute \src "libresoc.v:41546.19-41546.127" + wire $and$libresoc.v:41546$1968_Y + attribute \src "libresoc.v:41547.19-41547.112" + wire $and$libresoc.v:41547$1969_Y + attribute \src "libresoc.v:41549.19-41549.102" + wire $and$libresoc.v:41549$1971_Y + attribute \src "libresoc.v:41550.19-41550.127" + wire $and$libresoc.v:41550$1972_Y + attribute \src "libresoc.v:41561.19-41561.122" + wire $and$libresoc.v:41561$1983_Y + attribute \src "libresoc.v:41562.19-41562.112" + wire $and$libresoc.v:41562$1984_Y + attribute \src "libresoc.v:41564.19-41564.102" + wire $and$libresoc.v:41564$1986_Y + attribute \src "libresoc.v:41565.19-41565.127" + wire $and$libresoc.v:41565$1987_Y + attribute \src "libresoc.v:41567.19-41567.127" + wire $and$libresoc.v:41567$1989_Y + attribute \src "libresoc.v:41568.19-41568.112" + wire $and$libresoc.v:41568$1990_Y + attribute \src "libresoc.v:41570.19-41570.102" + wire $and$libresoc.v:41570$1992_Y + attribute \src "libresoc.v:41571.19-41571.127" + wire $and$libresoc.v:41571$1993_Y + attribute \src "libresoc.v:41573.19-41573.127" + wire $and$libresoc.v:41573$1995_Y + attribute \src "libresoc.v:41574.19-41574.112" + wire $and$libresoc.v:41574$1996_Y + attribute \src "libresoc.v:41576.19-41576.102" + wire $and$libresoc.v:41576$1998_Y + attribute \src "libresoc.v:41577.19-41577.127" + wire $and$libresoc.v:41577$1999_Y + attribute \src "libresoc.v:41579.19-41579.127" + wire $and$libresoc.v:41579$2001_Y + attribute \src "libresoc.v:41580.19-41580.112" + wire $and$libresoc.v:41580$2002_Y + attribute \src "libresoc.v:41582.19-41582.102" + wire $and$libresoc.v:41582$2004_Y + attribute \src "libresoc.v:41583.19-41583.127" + wire $and$libresoc.v:41583$2005_Y + attribute \src "libresoc.v:41585.19-41585.127" + wire $and$libresoc.v:41585$2007_Y + attribute \src "libresoc.v:41586.19-41586.112" + wire $and$libresoc.v:41586$2008_Y + attribute \src "libresoc.v:41588.19-41588.102" + wire $and$libresoc.v:41588$2010_Y + attribute \src "libresoc.v:41589.19-41589.127" + wire $and$libresoc.v:41589$2011_Y + attribute \src "libresoc.v:41591.19-41591.127" + wire $and$libresoc.v:41591$2013_Y + attribute \src "libresoc.v:41592.19-41592.112" + wire $and$libresoc.v:41592$2014_Y + attribute \src "libresoc.v:41594.19-41594.102" + wire $and$libresoc.v:41594$2016_Y + attribute \src "libresoc.v:41595.19-41595.127" + wire $and$libresoc.v:41595$2017_Y + attribute \src "libresoc.v:41597.19-41597.127" + wire $and$libresoc.v:41597$2019_Y + attribute \src "libresoc.v:41598.19-41598.112" + wire $and$libresoc.v:41598$2020_Y + attribute \src "libresoc.v:41600.19-41600.102" + wire $and$libresoc.v:41600$2022_Y + attribute \src "libresoc.v:41601.19-41601.127" + wire $and$libresoc.v:41601$2023_Y + attribute \src "libresoc.v:41603.19-41603.127" + wire $and$libresoc.v:41603$2025_Y + attribute \src "libresoc.v:41604.19-41604.112" + wire $and$libresoc.v:41604$2026_Y + attribute \src "libresoc.v:41606.19-41606.102" + wire $and$libresoc.v:41606$2028_Y + attribute \src "libresoc.v:41607.19-41607.127" + wire $and$libresoc.v:41607$2029_Y + attribute \src "libresoc.v:41617.19-41617.127" + wire $and$libresoc.v:41617$2039_Y + attribute \src "libresoc.v:41618.19-41618.112" + wire $and$libresoc.v:41618$2040_Y + attribute \src "libresoc.v:41620.19-41620.102" + wire $and$libresoc.v:41620$2042_Y + attribute \src "libresoc.v:41621.19-41621.127" + wire $and$libresoc.v:41621$2043_Y + attribute \src "libresoc.v:41623.19-41623.127" + wire $and$libresoc.v:41623$2045_Y + attribute \src "libresoc.v:41624.19-41624.112" + wire $and$libresoc.v:41624$2046_Y + attribute \src "libresoc.v:41626.19-41626.102" + wire $and$libresoc.v:41626$2048_Y + attribute \src "libresoc.v:41627.19-41627.127" + wire $and$libresoc.v:41627$2049_Y + attribute \src "libresoc.v:41631.19-41631.131" + wire $and$libresoc.v:41631$2053_Y + attribute \src "libresoc.v:41632.19-41632.119" + wire width 3 $and$libresoc.v:41632$2054_Y + attribute \src "libresoc.v:41635.19-41635.131" + wire $and$libresoc.v:41635$2057_Y + attribute \src "libresoc.v:41637.19-41637.122" + wire $and$libresoc.v:41637$2059_Y + attribute \src "libresoc.v:41638.19-41638.116" + wire $and$libresoc.v:41638$2060_Y + attribute \src "libresoc.v:41640.19-41640.102" + wire $and$libresoc.v:41640$2062_Y + attribute \src "libresoc.v:41641.19-41641.135" + wire $and$libresoc.v:41641$2063_Y + attribute \src "libresoc.v:41643.19-41643.127" + wire $and$libresoc.v:41643$2065_Y + attribute \src "libresoc.v:41644.19-41644.116" + wire $and$libresoc.v:41644$2066_Y + attribute \src "libresoc.v:41646.19-41646.102" + wire $and$libresoc.v:41646$2068_Y + attribute \src "libresoc.v:41647.19-41647.135" + wire $and$libresoc.v:41647$2069_Y + attribute \src "libresoc.v:41649.19-41649.127" + wire $and$libresoc.v:41649$2071_Y + attribute \src "libresoc.v:41650.19-41650.116" + wire $and$libresoc.v:41650$2072_Y + attribute \src "libresoc.v:41652.19-41652.102" + wire $and$libresoc.v:41652$2074_Y + attribute \src "libresoc.v:41653.19-41653.135" + wire $and$libresoc.v:41653$2075_Y + attribute \src "libresoc.v:41655.19-41655.127" + wire $and$libresoc.v:41655$2077_Y + attribute \src "libresoc.v:41656.19-41656.116" + wire $and$libresoc.v:41656$2078_Y + attribute \src "libresoc.v:41658.19-41658.102" + wire $and$libresoc.v:41658$2080_Y + attribute \src "libresoc.v:41659.19-41659.135" + wire $and$libresoc.v:41659$2081_Y + attribute \src "libresoc.v:41661.19-41661.127" + wire $and$libresoc.v:41661$2083_Y + attribute \src "libresoc.v:41662.19-41662.116" + wire $and$libresoc.v:41662$2084_Y + attribute \src "libresoc.v:41664.19-41664.102" + wire $and$libresoc.v:41664$2086_Y + attribute \src "libresoc.v:41665.19-41665.135" + wire $and$libresoc.v:41665$2087_Y + attribute \src "libresoc.v:41667.19-41667.127" + wire $and$libresoc.v:41667$2089_Y + attribute \src "libresoc.v:41668.19-41668.116" + wire $and$libresoc.v:41668$2090_Y + attribute \src "libresoc.v:41670.19-41670.102" + wire $and$libresoc.v:41670$2092_Y + attribute \src "libresoc.v:41671.19-41671.135" + wire $and$libresoc.v:41671$2093_Y + attribute \src "libresoc.v:41680.19-41680.119" + wire width 3 $and$libresoc.v:41680$2103_Y + attribute \src "libresoc.v:41683.19-41683.122" + wire $and$libresoc.v:41683$2106_Y + attribute \src "libresoc.v:41684.19-41684.116" + wire $and$libresoc.v:41684$2107_Y + attribute \src "libresoc.v:41686.19-41686.102" + wire $and$libresoc.v:41686$2109_Y + attribute \src "libresoc.v:41687.19-41687.135" + wire $and$libresoc.v:41687$2110_Y + attribute \src "libresoc.v:41689.19-41689.127" + wire $and$libresoc.v:41689$2112_Y + attribute \src "libresoc.v:41690.19-41690.116" + wire $and$libresoc.v:41690$2113_Y + attribute \src "libresoc.v:41692.19-41692.102" + wire $and$libresoc.v:41692$2115_Y + attribute \src "libresoc.v:41693.19-41693.135" + wire $and$libresoc.v:41693$2116_Y + attribute \src "libresoc.v:41695.19-41695.127" + wire $and$libresoc.v:41695$2118_Y + attribute \src "libresoc.v:41696.19-41696.116" + wire $and$libresoc.v:41696$2119_Y + attribute \src "libresoc.v:41698.19-41698.102" + wire $and$libresoc.v:41698$2121_Y + attribute \src "libresoc.v:41699.19-41699.135" + wire $and$libresoc.v:41699$2122_Y + attribute \src "libresoc.v:41704.19-41704.131" + wire $and$libresoc.v:41704$2128_Y + attribute \src "libresoc.v:41705.19-41705.119" + wire width 3 $and$libresoc.v:41705$2129_Y + attribute \src "libresoc.v:41708.19-41708.127" + wire $and$libresoc.v:41708$2132_Y + attribute \src "libresoc.v:41709.19-41709.116" + wire $and$libresoc.v:41709$2133_Y + attribute \src "libresoc.v:41711.19-41711.102" + wire $and$libresoc.v:41711$2135_Y + attribute \src "libresoc.v:41712.19-41712.132" + wire $and$libresoc.v:41712$2136_Y + attribute \src "libresoc.v:41714.19-41714.127" + wire $and$libresoc.v:41714$2138_Y + attribute \src "libresoc.v:41715.19-41715.116" + wire $and$libresoc.v:41715$2139_Y + attribute \src "libresoc.v:41717.19-41717.102" + wire $and$libresoc.v:41717$2141_Y + attribute \src "libresoc.v:41718.19-41718.132" + wire $and$libresoc.v:41718$2142_Y + attribute \src "libresoc.v:41720.19-41720.127" + wire $and$libresoc.v:41720$2144_Y + attribute \src "libresoc.v:41721.19-41721.113" + wire $and$libresoc.v:41721$2145_Y + attribute \src "libresoc.v:41723.19-41723.102" + wire $and$libresoc.v:41723$2147_Y + attribute \src "libresoc.v:41724.19-41724.129" + wire $and$libresoc.v:41724$2148_Y + attribute \src "libresoc.v:41728.19-41728.127" + wire $and$libresoc.v:41728$2152_Y + attribute \src "libresoc.v:41729.19-41729.113" + wire $and$libresoc.v:41729$2153_Y + attribute \src "libresoc.v:41731.19-41731.102" + wire $and$libresoc.v:41731$2155_Y + attribute \src "libresoc.v:41732.19-41732.129" + wire $and$libresoc.v:41732$2156_Y + attribute \src "libresoc.v:41737.19-41737.127" + wire $and$libresoc.v:41737$2161_Y + attribute \src "libresoc.v:41738.19-41738.113" + wire $and$libresoc.v:41738$2162_Y + attribute \src "libresoc.v:41740.19-41740.102" + wire $and$libresoc.v:41740$2164_Y + attribute \src "libresoc.v:41741.19-41741.126" + wire $and$libresoc.v:41741$2165_Y + attribute \src "libresoc.v:41745.19-41745.127" + wire $and$libresoc.v:41745$2169_Y + attribute \src "libresoc.v:41746.19-41746.113" + wire $and$libresoc.v:41746$2170_Y + attribute \src "libresoc.v:41748.19-41748.102" + wire $and$libresoc.v:41748$2172_Y + attribute \src "libresoc.v:41749.19-41749.126" + wire $and$libresoc.v:41749$2173_Y + attribute \src "libresoc.v:41753.19-41753.127" + wire $and$libresoc.v:41753$2177_Y + attribute \src "libresoc.v:41754.19-41754.116" + wire $and$libresoc.v:41754$2178_Y + attribute \src "libresoc.v:41756.19-41756.102" + wire $and$libresoc.v:41756$2180_Y + attribute \src "libresoc.v:41757.19-41757.135" + wire $and$libresoc.v:41757$2181_Y + attribute \src "libresoc.v:41759.19-41759.127" + wire $and$libresoc.v:41759$2183_Y + attribute \src "libresoc.v:41760.19-41760.116" + wire $and$libresoc.v:41760$2184_Y + attribute \src "libresoc.v:41762.19-41762.102" + wire $and$libresoc.v:41762$2186_Y + attribute \src "libresoc.v:41763.19-41763.135" + wire $and$libresoc.v:41763$2187_Y + attribute \src "libresoc.v:41765.19-41765.127" + wire $and$libresoc.v:41765$2189_Y + attribute \src "libresoc.v:41766.19-41766.116" + wire $and$libresoc.v:41766$2190_Y + attribute \src "libresoc.v:41768.19-41768.102" + wire $and$libresoc.v:41768$2192_Y + attribute \src "libresoc.v:41769.19-41769.135" + wire $and$libresoc.v:41769$2193_Y + attribute \src "libresoc.v:41774.19-41774.127" + wire $and$libresoc.v:41774$2198_Y + attribute \src "libresoc.v:41775.19-41775.116" + wire $and$libresoc.v:41775$2199_Y + attribute \src "libresoc.v:41777.19-41777.102" + wire $and$libresoc.v:41777$2201_Y + attribute \src "libresoc.v:41778.19-41778.135" + wire $and$libresoc.v:41778$2202_Y + attribute \src "libresoc.v:41780.19-41780.127" + wire $and$libresoc.v:41780$2204_Y + attribute \src "libresoc.v:41781.19-41781.116" + wire $and$libresoc.v:41781$2205_Y + attribute \src "libresoc.v:41783.19-41783.102" + wire $and$libresoc.v:41783$2207_Y + attribute \src "libresoc.v:41784.19-41784.135" + wire $and$libresoc.v:41784$2208_Y + attribute \src "libresoc.v:41788.19-41788.127" + wire $and$libresoc.v:41788$2212_Y + attribute \src "libresoc.v:41789.19-41789.114" + wire $and$libresoc.v:41789$2213_Y + attribute \src "libresoc.v:41791.19-41791.102" + wire $and$libresoc.v:41791$2215_Y + attribute \src "libresoc.v:41792.19-41792.128" + wire $and$libresoc.v:41792$2216_Y + attribute \src "libresoc.v:41795.19-41795.112" + wire $and$libresoc.v:41795$2219_Y + attribute \src "libresoc.v:41796.19-41796.122" + wire $and$libresoc.v:41796$2220_Y + attribute \src "libresoc.v:41797.19-41797.127" + wire $and$libresoc.v:41797$2221_Y + attribute \src "libresoc.v:41798.19-41798.127" + wire $and$libresoc.v:41798$2222_Y + attribute \src "libresoc.v:41799.19-41799.127" + wire $and$libresoc.v:41799$2223_Y + attribute \src "libresoc.v:41800.19-41800.127" + wire $and$libresoc.v:41800$2224_Y + attribute \src "libresoc.v:41801.19-41801.127" + wire $and$libresoc.v:41801$2225_Y + attribute \src "libresoc.v:41802.19-41802.127" + wire $and$libresoc.v:41802$2226_Y + attribute \src "libresoc.v:41803.19-41803.128" + wire $and$libresoc.v:41803$2227_Y + attribute \src "libresoc.v:41804.19-41804.128" + wire $and$libresoc.v:41804$2228_Y + attribute \src "libresoc.v:41805.19-41805.128" + wire $and$libresoc.v:41805$2229_Y + attribute \src "libresoc.v:41806.19-41806.125" + wire $and$libresoc.v:41806$2230_Y + attribute \src "libresoc.v:41808.19-41808.101" + wire $and$libresoc.v:41808$2232_Y + attribute \src "libresoc.v:41809.19-41809.115" + wire $and$libresoc.v:41809$2233_Y + attribute \src "libresoc.v:41811.19-41811.120" + wire $and$libresoc.v:41811$2235_Y + attribute \src "libresoc.v:41812.19-41812.125" + wire $and$libresoc.v:41812$2236_Y + attribute \src "libresoc.v:41814.19-41814.107" + wire $and$libresoc.v:41814$2238_Y + attribute \src "libresoc.v:41815.19-41815.121" + wire $and$libresoc.v:41815$2239_Y + attribute \src "libresoc.v:41817.19-41817.121" + wire $and$libresoc.v:41817$2241_Y + attribute \src "libresoc.v:41818.19-41818.125" + wire $and$libresoc.v:41818$2242_Y + attribute \src "libresoc.v:41820.19-41820.107" + wire $and$libresoc.v:41820$2244_Y + attribute \src "libresoc.v:41821.19-41821.121" + wire $and$libresoc.v:41821$2245_Y + attribute \src "libresoc.v:41438.19-41438.115" + wire $eq$libresoc.v:41438$1860_Y + attribute \src "libresoc.v:41442.19-41442.130" + wire $eq$libresoc.v:41442$1864_Y + attribute \src "libresoc.v:41444.19-41444.115" + wire $eq$libresoc.v:41444$1866_Y + attribute \src "libresoc.v:41452.19-41452.115" + wire $eq$libresoc.v:41452$1874_Y + attribute \src "libresoc.v:41459.19-41459.115" + wire $eq$libresoc.v:41459$1881_Y + attribute \src "libresoc.v:41465.19-41465.115" + wire $eq$libresoc.v:41465$1887_Y + attribute \src "libresoc.v:41467.19-41467.130" + wire $eq$libresoc.v:41467$1889_Y + attribute \src "libresoc.v:41469.19-41469.115" + wire $eq$libresoc.v:41469$1891_Y + attribute \src "libresoc.v:41474.19-41474.115" + wire $eq$libresoc.v:41474$1896_Y + attribute \src "libresoc.v:41481.19-41481.115" + wire $eq$libresoc.v:41481$1903_Y + attribute \src "libresoc.v:41488.19-41488.115" + wire $eq$libresoc.v:41488$1910_Y + attribute \src "libresoc.v:41492.19-41492.130" + wire $eq$libresoc.v:41492$1914_Y + attribute \src "libresoc.v:41494.19-41494.115" + wire $eq$libresoc.v:41494$1916_Y + attribute \src "libresoc.v:41633.19-41633.115" + wire $eq$libresoc.v:41633$2055_Y + attribute \src "libresoc.v:41679.19-41679.130" + wire $eq$libresoc.v:41679$2102_Y + attribute \src "libresoc.v:41681.19-41681.115" + wire $eq$libresoc.v:41681$2104_Y + attribute \src "libresoc.v:41706.19-41706.115" + wire $eq$libresoc.v:41706$2130_Y + attribute \src "libresoc.v:41263.20-41263.95" + wire width 3 $extend$libresoc.v:41263$1680_Y + attribute \src "libresoc.v:41329.20-41329.95" + wire width 2 $extend$libresoc.v:41329$1747_Y + attribute \src "libresoc.v:41333.20-41333.95" + wire width 3 $extend$libresoc.v:41333$1752_Y + attribute \src "libresoc.v:41405.20-41405.95" + wire width 4 $extend$libresoc.v:41405$1825_Y + attribute \src "libresoc.v:41413.20-41413.104" + wire width 4 $extend$libresoc.v:41413$1834_Y + attribute \src "libresoc.v:41678.19-41678.93" + wire width 3 $extend$libresoc.v:41678$2100_Y + attribute \src "libresoc.v:41703.19-41703.93" + wire width 3 $extend$libresoc.v:41703$2126_Y + attribute \src "libresoc.v:41433.19-41433.103" + wire $ne$libresoc.v:41433$1855_Y + attribute \src "libresoc.v:41435.19-41435.103" + wire $ne$libresoc.v:41435$1857_Y + attribute \src "libresoc.v:41100.20-41100.106" + wire $not$libresoc.v:41100$1517_Y + attribute \src "libresoc.v:41106.20-41106.106" + wire $not$libresoc.v:41106$1523_Y + attribute \src "libresoc.v:41112.20-41112.106" + wire $not$libresoc.v:41112$1529_Y + attribute \src "libresoc.v:41118.20-41118.106" + wire $not$libresoc.v:41118$1535_Y + attribute \src "libresoc.v:41124.20-41124.106" + wire $not$libresoc.v:41124$1541_Y + attribute \src "libresoc.v:41130.20-41130.106" + wire $not$libresoc.v:41130$1547_Y + attribute \src "libresoc.v:41136.20-41136.106" + wire $not$libresoc.v:41136$1553_Y + attribute \src "libresoc.v:41170.20-41170.106" + wire $not$libresoc.v:41170$1587_Y + attribute \src "libresoc.v:41182.20-41182.106" + wire $not$libresoc.v:41182$1599_Y + attribute \src "libresoc.v:41190.20-41190.106" + wire $not$libresoc.v:41190$1607_Y + attribute \src "libresoc.v:41198.20-41198.106" + wire $not$libresoc.v:41198$1615_Y + attribute \src "libresoc.v:41206.20-41206.106" + wire $not$libresoc.v:41206$1623_Y + attribute \src "libresoc.v:41214.20-41214.106" + wire $not$libresoc.v:41214$1631_Y + attribute \src "libresoc.v:41222.20-41222.106" + wire $not$libresoc.v:41222$1639_Y + attribute \src "libresoc.v:41243.20-41243.106" + wire $not$libresoc.v:41243$1660_Y + attribute \src "libresoc.v:41249.20-41249.106" + wire $not$libresoc.v:41249$1666_Y + attribute \src "libresoc.v:41255.20-41255.106" + wire $not$libresoc.v:41255$1672_Y + attribute \src "libresoc.v:41270.20-41270.106" + wire $not$libresoc.v:41270$1688_Y + attribute \src "libresoc.v:41276.20-41276.106" + wire $not$libresoc.v:41276$1694_Y + attribute \src "libresoc.v:41282.20-41282.106" + wire $not$libresoc.v:41282$1700_Y + attribute \src "libresoc.v:41288.20-41288.106" + wire $not$libresoc.v:41288$1706_Y + attribute \src "libresoc.v:41304.20-41304.106" + wire $not$libresoc.v:41304$1722_Y + attribute \src "libresoc.v:41310.20-41310.106" + wire $not$libresoc.v:41310$1728_Y + attribute \src "libresoc.v:41316.20-41316.106" + wire $not$libresoc.v:41316$1734_Y + attribute \src "libresoc.v:41322.20-41322.106" + wire $not$libresoc.v:41322$1740_Y + attribute \src "libresoc.v:41341.20-41341.106" + wire $not$libresoc.v:41341$1761_Y + attribute \src "libresoc.v:41349.20-41349.106" + wire $not$libresoc.v:41349$1769_Y + attribute \src "libresoc.v:41355.20-41355.106" + wire $not$libresoc.v:41355$1775_Y + attribute \src "libresoc.v:41362.20-41362.106" + wire $not$libresoc.v:41362$1782_Y + attribute \src "libresoc.v:41369.20-41369.106" + wire $not$libresoc.v:41369$1789_Y + attribute \src "libresoc.v:41391.20-41391.106" + wire $not$libresoc.v:41391$1811_Y + attribute \src "libresoc.v:41398.20-41398.106" + wire $not$libresoc.v:41398$1818_Y + attribute \src "libresoc.v:41409.20-41409.106" + wire $not$libresoc.v:41409$1830_Y + attribute \src "libresoc.v:41418.20-41418.106" + wire $not$libresoc.v:41418$1840_Y + attribute \src "libresoc.v:41446.19-41446.136" + wire width 4 $not$libresoc.v:41446$1868_Y + attribute \src "libresoc.v:41447.19-41447.192" + wire width 6 $not$libresoc.v:41447$1869_Y + attribute \src "libresoc.v:41448.19-41448.138" + wire width 3 $not$libresoc.v:41448$1870_Y + attribute \src "libresoc.v:41449.19-41449.150" + wire width 4 $not$libresoc.v:41449$1871_Y + attribute \src "libresoc.v:41456.19-41456.128" + wire width 3 $not$libresoc.v:41456$1878_Y + attribute \src "libresoc.v:41471.19-41471.159" + wire width 6 $not$libresoc.v:41471$1893_Y + attribute \src "libresoc.v:41478.19-41478.128" + wire width 3 $not$libresoc.v:41478$1900_Y + attribute \src "libresoc.v:41485.19-41485.128" + wire width 3 $not$libresoc.v:41485$1907_Y + attribute \src "libresoc.v:41496.19-41496.150" + wire width 5 $not$libresoc.v:41496$1918_Y + attribute \src "libresoc.v:41497.19-41497.134" + wire width 3 $not$libresoc.v:41497$1919_Y + attribute \src "libresoc.v:41500.19-41500.106" + wire $not$libresoc.v:41500$1922_Y + attribute \src "libresoc.v:41506.19-41506.105" + wire $not$libresoc.v:41506$1928_Y + attribute \src "libresoc.v:41512.19-41512.107" + wire $not$libresoc.v:41512$1934_Y + attribute \src "libresoc.v:41518.19-41518.110" + wire $not$libresoc.v:41518$1940_Y + attribute \src "libresoc.v:41524.19-41524.106" + wire $not$libresoc.v:41524$1946_Y + attribute \src "libresoc.v:41530.19-41530.106" + wire $not$libresoc.v:41530$1952_Y + attribute \src "libresoc.v:41536.19-41536.106" + wire $not$libresoc.v:41536$1958_Y + attribute \src "libresoc.v:41542.19-41542.111" + wire $not$libresoc.v:41542$1964_Y + attribute \src "libresoc.v:41548.19-41548.107" + wire $not$libresoc.v:41548$1970_Y + attribute \src "libresoc.v:41563.19-41563.106" + wire $not$libresoc.v:41563$1985_Y + attribute \src "libresoc.v:41569.19-41569.105" + wire $not$libresoc.v:41569$1991_Y + attribute \src "libresoc.v:41575.19-41575.107" + wire $not$libresoc.v:41575$1997_Y + attribute \src "libresoc.v:41581.19-41581.110" + wire $not$libresoc.v:41581$2003_Y + attribute \src "libresoc.v:41587.19-41587.106" + wire $not$libresoc.v:41587$2009_Y + attribute \src "libresoc.v:41593.19-41593.106" + wire $not$libresoc.v:41593$2015_Y + attribute \src "libresoc.v:41599.19-41599.111" + wire $not$libresoc.v:41599$2021_Y + attribute \src "libresoc.v:41605.19-41605.107" + wire $not$libresoc.v:41605$2027_Y + attribute \src "libresoc.v:41619.19-41619.111" + wire $not$libresoc.v:41619$2041_Y + attribute \src "libresoc.v:41625.19-41625.107" + wire $not$libresoc.v:41625$2047_Y + attribute \src "libresoc.v:41639.19-41639.110" + wire $not$libresoc.v:41639$2061_Y + attribute \src "libresoc.v:41645.19-41645.114" + wire $not$libresoc.v:41645$2067_Y + attribute \src "libresoc.v:41651.19-41651.110" + wire $not$libresoc.v:41651$2073_Y + attribute \src "libresoc.v:41657.19-41657.110" + wire $not$libresoc.v:41657$2079_Y + attribute \src "libresoc.v:41663.19-41663.110" + wire $not$libresoc.v:41663$2085_Y + attribute \src "libresoc.v:41669.19-41669.115" + wire $not$libresoc.v:41669$2091_Y + attribute \src "libresoc.v:41685.19-41685.110" + wire $not$libresoc.v:41685$2108_Y + attribute \src "libresoc.v:41691.19-41691.110" + wire $not$libresoc.v:41691$2114_Y + attribute \src "libresoc.v:41697.19-41697.115" + wire $not$libresoc.v:41697$2120_Y + attribute \src "libresoc.v:41710.19-41710.110" + wire $not$libresoc.v:41710$2134_Y + attribute \src "libresoc.v:41716.19-41716.109" + wire $not$libresoc.v:41716$2140_Y + attribute \src "libresoc.v:41722.19-41722.106" + wire $not$libresoc.v:41722$2146_Y + attribute \src "libresoc.v:41730.19-41730.110" + wire $not$libresoc.v:41730$2154_Y + attribute \src "libresoc.v:41739.19-41739.106" + wire $not$libresoc.v:41739$2163_Y + attribute \src "libresoc.v:41747.19-41747.106" + wire $not$libresoc.v:41747$2171_Y + attribute \src "libresoc.v:41755.19-41755.113" + wire $not$libresoc.v:41755$2179_Y + attribute \src "libresoc.v:41761.19-41761.111" + wire $not$libresoc.v:41761$2185_Y + attribute \src "libresoc.v:41767.19-41767.110" + wire $not$libresoc.v:41767$2191_Y + attribute \src "libresoc.v:41776.19-41776.113" + wire $not$libresoc.v:41776$2200_Y + attribute \src "libresoc.v:41782.19-41782.111" + wire $not$libresoc.v:41782$2206_Y + attribute \src "libresoc.v:41790.19-41790.108" + wire $not$libresoc.v:41790$2214_Y + attribute \src "libresoc.v:41807.19-41807.99" + wire $not$libresoc.v:41807$2231_Y + attribute \src "libresoc.v:41813.19-41813.104" + wire $not$libresoc.v:41813$2237_Y + attribute \src "libresoc.v:41819.19-41819.104" + wire $not$libresoc.v:41819$2243_Y + attribute \src "libresoc.v:41140.20-41140.117" + wire width 64 $or$libresoc.v:41140$1557_Y + attribute \src "libresoc.v:41141.20-41141.123" + wire width 64 $or$libresoc.v:41141$1558_Y + attribute \src "libresoc.v:41142.20-41142.113" + wire width 64 $or$libresoc.v:41142$1559_Y + attribute \src "libresoc.v:41143.20-41143.103" + wire width 64 $or$libresoc.v:41143$1560_Y + attribute \src "libresoc.v:41144.20-41144.123" + wire width 64 $or$libresoc.v:41144$1561_Y + attribute \src "libresoc.v:41145.20-41145.122" + wire width 65 $or$libresoc.v:41145$1562_Y + attribute \src "libresoc.v:41146.20-41146.113" + wire width 65 $or$libresoc.v:41146$1563_Y + attribute \src "libresoc.v:41147.20-41147.103" + wire width 65 $or$libresoc.v:41147$1564_Y + attribute \src "libresoc.v:41148.20-41148.103" + wire width 65 $or$libresoc.v:41148$1565_Y + attribute \src "libresoc.v:41149.20-41149.109" + wire width 5 $or$libresoc.v:41149$1566_Y + attribute \src "libresoc.v:41150.20-41150.117" + wire width 5 $or$libresoc.v:41150$1567_Y + attribute \src "libresoc.v:41151.20-41151.109" + wire width 5 $or$libresoc.v:41151$1568_Y + attribute \src "libresoc.v:41152.20-41152.103" + wire width 5 $or$libresoc.v:41152$1569_Y + attribute \src "libresoc.v:41153.20-41153.117" + wire width 5 $or$libresoc.v:41153$1570_Y + attribute \src "libresoc.v:41154.20-41154.117" + wire width 5 $or$libresoc.v:41154$1571_Y + attribute \src "libresoc.v:41155.20-41155.110" + wire width 5 $or$libresoc.v:41155$1572_Y + attribute \src "libresoc.v:41156.20-41156.103" + wire width 5 $or$libresoc.v:41156$1573_Y + attribute \src "libresoc.v:41157.20-41157.103" + wire width 5 $or$libresoc.v:41157$1574_Y + attribute \src "libresoc.v:41158.20-41158.99" + wire $or$libresoc.v:41158$1575_Y + attribute \src "libresoc.v:41159.20-41159.107" + wire $or$libresoc.v:41159$1576_Y + attribute \src "libresoc.v:41160.20-41160.104" + wire $or$libresoc.v:41160$1577_Y + attribute \src "libresoc.v:41161.20-41161.103" + wire $or$libresoc.v:41161$1578_Y + attribute \src "libresoc.v:41162.20-41162.107" + wire $or$libresoc.v:41162$1579_Y + attribute \src "libresoc.v:41163.20-41163.107" + wire $or$libresoc.v:41163$1580_Y + attribute \src "libresoc.v:41164.20-41164.105" + wire $or$libresoc.v:41164$1581_Y + attribute \src "libresoc.v:41165.20-41165.103" + wire $or$libresoc.v:41165$1582_Y + attribute \src "libresoc.v:41166.20-41166.103" + wire $or$libresoc.v:41166$1583_Y + attribute \src "libresoc.v:41228.20-41228.117" + wire width 4 $or$libresoc.v:41228$1645_Y + attribute \src "libresoc.v:41229.20-41229.113" + wire width 4 $or$libresoc.v:41229$1646_Y + attribute \src "libresoc.v:41230.20-41230.123" + wire width 4 $or$libresoc.v:41230$1647_Y + attribute \src "libresoc.v:41231.20-41231.113" + wire width 4 $or$libresoc.v:41231$1648_Y + attribute \src "libresoc.v:41232.20-41232.103" + wire width 4 $or$libresoc.v:41232$1649_Y + attribute \src "libresoc.v:41233.20-41233.117" + wire width 16 $or$libresoc.v:41233$1650_Y + attribute \src "libresoc.v:41234.20-41234.110" + wire width 16 $or$libresoc.v:41234$1651_Y + attribute \src "libresoc.v:41235.20-41235.117" + wire width 16 $or$libresoc.v:41235$1652_Y + attribute \src "libresoc.v:41236.20-41236.110" + wire width 16 $or$libresoc.v:41236$1653_Y + attribute \src "libresoc.v:41237.20-41237.103" + wire width 16 $or$libresoc.v:41237$1654_Y + attribute \src "libresoc.v:41259.20-41259.117" + wire width 2 $or$libresoc.v:41259$1676_Y + attribute \src "libresoc.v:41260.20-41260.113" + wire width 2 $or$libresoc.v:41260$1677_Y + attribute \src "libresoc.v:41261.20-41261.117" + wire width 2 $or$libresoc.v:41261$1678_Y + attribute \src "libresoc.v:41262.20-41262.110" + wire width 2 $or$libresoc.v:41262$1679_Y + attribute \src "libresoc.v:41292.20-41292.112" + wire width 2 $or$libresoc.v:41292$1710_Y + attribute \src "libresoc.v:41293.20-41293.123" + wire width 2 $or$libresoc.v:41293$1711_Y + attribute \src "libresoc.v:41294.20-41294.103" + wire width 2 $or$libresoc.v:41294$1712_Y + attribute \src "libresoc.v:41295.20-41295.117" + wire width 3 $or$libresoc.v:41295$1713_Y + attribute \src "libresoc.v:41296.20-41296.117" + wire width 3 $or$libresoc.v:41296$1714_Y + attribute \src "libresoc.v:41297.20-41297.103" + wire width 3 $or$libresoc.v:41297$1715_Y + attribute \src "libresoc.v:41326.20-41326.123" + wire $or$libresoc.v:41326$1744_Y + attribute \src "libresoc.v:41327.20-41327.123" + wire $or$libresoc.v:41327$1745_Y + attribute \src "libresoc.v:41328.20-41328.103" + wire $or$libresoc.v:41328$1746_Y + attribute \src "libresoc.v:41330.20-41330.117" + wire $or$libresoc.v:41330$1749_Y + attribute \src "libresoc.v:41331.20-41331.117" + wire $or$libresoc.v:41331$1750_Y + attribute \src "libresoc.v:41332.20-41332.103" + wire $or$libresoc.v:41332$1751_Y + attribute \src "libresoc.v:41373.20-41373.123" + wire width 64 $or$libresoc.v:41373$1793_Y + attribute \src "libresoc.v:41374.20-41374.123" + wire width 64 $or$libresoc.v:41374$1794_Y + attribute \src "libresoc.v:41375.20-41375.113" + wire width 64 $or$libresoc.v:41375$1795_Y + attribute \src "libresoc.v:41376.20-41376.103" + wire width 64 $or$libresoc.v:41376$1796_Y + attribute \src "libresoc.v:41377.20-41377.117" + wire width 3 $or$libresoc.v:41377$1797_Y + attribute \src "libresoc.v:41379.20-41379.117" + wire width 3 $or$libresoc.v:41379$1799_Y + attribute \src "libresoc.v:41380.20-41380.110" + wire width 3 $or$libresoc.v:41380$1800_Y + attribute \src "libresoc.v:41381.20-41381.103" + wire width 3 $or$libresoc.v:41381$1801_Y + attribute \src "libresoc.v:41382.20-41382.107" + wire $or$libresoc.v:41382$1802_Y + attribute \src "libresoc.v:41383.20-41383.107" + wire $or$libresoc.v:41383$1803_Y + attribute \src "libresoc.v:41385.20-41385.105" + wire $or$libresoc.v:41385$1805_Y + attribute \src "libresoc.v:41386.20-41386.103" + wire $or$libresoc.v:41386$1806_Y + attribute \src "libresoc.v:41403.20-41403.123" + wire width 64 $or$libresoc.v:41403$1823_Y + attribute \src "libresoc.v:41404.20-41404.117" + wire $or$libresoc.v:41404$1824_Y + attribute \src "libresoc.v:41439.19-41439.115" + wire $or$libresoc.v:41439$1861_Y + attribute \src "libresoc.v:41441.19-41441.115" + wire $or$libresoc.v:41441$1863_Y + attribute \src "libresoc.v:41445.19-41445.115" + wire $or$libresoc.v:41445$1867_Y + attribute \src "libresoc.v:41453.19-41453.115" + wire $or$libresoc.v:41453$1875_Y + attribute \src "libresoc.v:41455.19-41455.115" + wire $or$libresoc.v:41455$1877_Y + attribute \src "libresoc.v:41460.19-41460.115" + wire $or$libresoc.v:41460$1882_Y + attribute \src "libresoc.v:41462.19-41462.115" + wire $or$libresoc.v:41462$1884_Y + attribute \src "libresoc.v:41466.19-41466.115" + wire $or$libresoc.v:41466$1888_Y + attribute \src "libresoc.v:41470.19-41470.115" + wire $or$libresoc.v:41470$1892_Y + attribute \src "libresoc.v:41475.19-41475.115" + wire $or$libresoc.v:41475$1897_Y + attribute \src "libresoc.v:41477.19-41477.115" + wire $or$libresoc.v:41477$1899_Y + attribute \src "libresoc.v:41482.19-41482.115" + wire $or$libresoc.v:41482$1904_Y + attribute \src "libresoc.v:41484.19-41484.115" + wire $or$libresoc.v:41484$1906_Y + attribute \src "libresoc.v:41489.19-41489.115" + wire $or$libresoc.v:41489$1911_Y + attribute \src "libresoc.v:41491.19-41491.115" + wire $or$libresoc.v:41491$1913_Y + attribute \src "libresoc.v:41495.19-41495.115" + wire $or$libresoc.v:41495$1917_Y + attribute \src "libresoc.v:41552.19-41552.130" + wire width 5 $or$libresoc.v:41552$1974_Y + attribute \src "libresoc.v:41553.19-41553.136" + wire width 5 $or$libresoc.v:41553$1975_Y + attribute \src "libresoc.v:41554.19-41554.100" + wire width 5 $or$libresoc.v:41554$1976_Y + attribute \src "libresoc.v:41555.19-41555.131" + wire width 5 $or$libresoc.v:41555$1977_Y + attribute \src "libresoc.v:41556.19-41556.137" + wire width 5 $or$libresoc.v:41556$1978_Y + attribute \src "libresoc.v:41557.19-41557.115" + wire width 5 $or$libresoc.v:41557$1979_Y + attribute \src "libresoc.v:41558.19-41558.100" + wire width 5 $or$libresoc.v:41558$1980_Y + attribute \src "libresoc.v:41559.19-41559.100" + wire width 5 $or$libresoc.v:41559$1981_Y + attribute \src "libresoc.v:41609.19-41609.130" + wire width 5 $or$libresoc.v:41609$2031_Y + attribute \src "libresoc.v:41610.19-41610.136" + wire width 5 $or$libresoc.v:41610$2032_Y + attribute \src "libresoc.v:41611.19-41611.100" + wire width 5 $or$libresoc.v:41611$2033_Y + attribute \src "libresoc.v:41612.19-41612.131" + wire width 5 $or$libresoc.v:41612$2034_Y + attribute \src "libresoc.v:41613.19-41613.137" + wire width 5 $or$libresoc.v:41613$2035_Y + attribute \src "libresoc.v:41614.19-41614.100" + wire width 5 $or$libresoc.v:41614$2036_Y + attribute \src "libresoc.v:41615.19-41615.100" + wire width 5 $or$libresoc.v:41615$2037_Y + attribute \src "libresoc.v:41629.19-41629.137" + wire width 5 $or$libresoc.v:41629$2051_Y + attribute \src "libresoc.v:41634.19-41634.115" + wire $or$libresoc.v:41634$2056_Y + attribute \src "libresoc.v:41636.19-41636.115" + wire $or$libresoc.v:41636$2058_Y + attribute \src "libresoc.v:41673.19-41673.143" + wire $or$libresoc.v:41673$2095_Y + attribute \src "libresoc.v:41674.19-41674.119" + wire $or$libresoc.v:41674$2096_Y + attribute \src "libresoc.v:41675.19-41675.144" + wire $or$libresoc.v:41675$2097_Y + attribute \src "libresoc.v:41676.19-41676.119" + wire $or$libresoc.v:41676$2098_Y + attribute \src "libresoc.v:41677.19-41677.100" + wire $or$libresoc.v:41677$2099_Y + attribute \src "libresoc.v:41682.19-41682.115" + wire $or$libresoc.v:41682$2105_Y + attribute \src "libresoc.v:41701.19-41701.144" + wire width 2 $or$libresoc.v:41701$2124_Y + attribute \src "libresoc.v:41702.19-41702.119" + wire width 2 $or$libresoc.v:41702$2125_Y + attribute \src "libresoc.v:41707.19-41707.115" + wire $or$libresoc.v:41707$2131_Y + attribute \src "libresoc.v:41736.19-41736.135" + wire width 16 $or$libresoc.v:41736$2160_Y + attribute \src "libresoc.v:41771.19-41771.140" + wire width 3 $or$libresoc.v:41771$2195_Y + attribute \src "libresoc.v:41772.19-41772.122" + wire width 3 $or$libresoc.v:41772$2196_Y + attribute \src "libresoc.v:41786.19-41786.143" + wire width 3 $or$libresoc.v:41786$2210_Y + attribute \src "libresoc.v:41263.20-41263.95" + wire width 3 $pos$libresoc.v:41263$1681_Y + attribute \src "libresoc.v:41329.20-41329.95" + wire width 2 $pos$libresoc.v:41329$1748_Y + attribute \src "libresoc.v:41333.20-41333.95" + wire width 3 $pos$libresoc.v:41333$1753_Y + attribute \src "libresoc.v:41405.20-41405.95" + wire width 4 $pos$libresoc.v:41405$1826_Y + attribute \src "libresoc.v:41413.20-41413.104" + wire width 4 $pos$libresoc.v:41413$1835_Y + attribute \src "libresoc.v:41678.19-41678.93" + wire width 3 $pos$libresoc.v:41678$2101_Y + attribute \src "libresoc.v:41703.19-41703.93" + wire width 3 $pos$libresoc.v:41703$2127_Y + attribute \src "libresoc.v:41347.19-41347.95" + wire $reduce_or$libresoc.v:41347$1767_Y + attribute \src "libresoc.v:41364.19-41364.95" + wire $reduce_or$libresoc.v:41364$1784_Y + attribute \src "libresoc.v:41384.19-41384.95" + wire $reduce_or$libresoc.v:41384$1804_Y + attribute \src "libresoc.v:41402.19-41402.95" + wire $reduce_or$libresoc.v:41402$1822_Y + attribute \src "libresoc.v:41420.19-41420.95" + wire $reduce_or$libresoc.v:41420$1842_Y + attribute \src "libresoc.v:41424.19-41424.95" + wire $reduce_or$libresoc.v:41424$1846_Y + attribute \src "libresoc.v:41426.19-41426.95" + wire $reduce_or$libresoc.v:41426$1848_Y + attribute \src "libresoc.v:41428.19-41428.95" + wire $reduce_or$libresoc.v:41428$1850_Y + attribute \src "libresoc.v:41430.19-41430.95" + wire $reduce_or$libresoc.v:41430$1852_Y + attribute \src "libresoc.v:41432.19-41432.95" + wire $reduce_or$libresoc.v:41432$1854_Y + attribute \src "libresoc.v:41560.19-41560.264" + wire $reduce_or$libresoc.v:41560$1982_Y + attribute \src "libresoc.v:41616.19-41616.246" + wire $reduce_or$libresoc.v:41616$2038_Y + attribute \src "libresoc.v:41630.19-41630.134" + wire $reduce_or$libresoc.v:41630$2052_Y + attribute \src "libresoc.v:41773.19-41773.162" + wire $reduce_or$libresoc.v:41773$2197_Y + attribute \src "libresoc.v:41787.19-41787.140" + wire $reduce_or$libresoc.v:41787$2211_Y + attribute \src "libresoc.v:41794.19-41794.108" + wire $reduce_or$libresoc.v:41794$2218_Y + attribute \src "libresoc.v:41186.20-41186.118" + wire width 16 $sshl$libresoc.v:41186$1603_Y + attribute \src "libresoc.v:41194.20-41194.118" + wire width 16 $sshl$libresoc.v:41194$1611_Y + attribute \src "libresoc.v:41202.20-41202.118" + wire width 16 $sshl$libresoc.v:41202$1619_Y + attribute \src "libresoc.v:41210.20-41210.118" + wire width 16 $sshl$libresoc.v:41210$1627_Y + attribute \src "libresoc.v:41218.20-41218.118" + wire width 16 $sshl$libresoc.v:41218$1635_Y + attribute \src "libresoc.v:41226.20-41226.118" + wire width 16 $sshl$libresoc.v:41226$1643_Y + attribute \src "libresoc.v:41726.19-41726.115" + wire width 16 $sshl$libresoc.v:41726$2150_Y + attribute \src "libresoc.v:41734.19-41734.115" + wire width 16 $sshl$libresoc.v:41734$2158_Y + attribute \src "libresoc.v:41743.19-41743.115" + wire width 16 $sshl$libresoc.v:41743$2167_Y + attribute \src "libresoc.v:41751.19-41751.115" + wire width 16 $sshl$libresoc.v:41751$2175_Y + attribute \src "libresoc.v:41185.20-41185.121" + wire width 4 $sub$libresoc.v:41185$1602_Y + attribute \src "libresoc.v:41193.20-41193.121" + wire width 4 $sub$libresoc.v:41193$1610_Y + attribute \src "libresoc.v:41201.20-41201.121" + wire width 4 $sub$libresoc.v:41201$1618_Y + attribute \src "libresoc.v:41209.20-41209.121" + wire width 4 $sub$libresoc.v:41209$1626_Y + attribute \src "libresoc.v:41217.20-41217.121" + wire width 4 $sub$libresoc.v:41217$1634_Y + attribute \src "libresoc.v:41225.20-41225.121" + wire width 4 $sub$libresoc.v:41225$1642_Y + attribute \src "libresoc.v:41434.19-41434.102" + wire width 3 $sub$libresoc.v:41434$1856_Y + attribute \src "libresoc.v:41725.19-41725.119" + wire width 4 $sub$libresoc.v:41725$2149_Y + attribute \src "libresoc.v:41733.19-41733.119" + wire width 4 $sub$libresoc.v:41733$2157_Y + attribute \src "libresoc.v:41742.19-41742.119" + wire width 4 $sub$libresoc.v:41742$2166_Y + attribute \src "libresoc.v:41750.19-41750.122" + wire width 4 $sub$libresoc.v:41750$2174_Y + attribute \src "libresoc.v:41097.20-41097.117" + wire width 5 $ternary$libresoc.v:41097$1514_Y + attribute \src "libresoc.v:41103.20-41103.118" + wire width 5 $ternary$libresoc.v:41103$1520_Y + attribute \src "libresoc.v:41109.20-41109.118" + wire width 5 $ternary$libresoc.v:41109$1526_Y + attribute \src "libresoc.v:41115.20-41115.118" + wire width 5 $ternary$libresoc.v:41115$1532_Y + attribute \src "libresoc.v:41121.20-41121.118" + wire width 5 $ternary$libresoc.v:41121$1538_Y + attribute \src "libresoc.v:41127.20-41127.118" + wire width 5 $ternary$libresoc.v:41127$1544_Y + attribute \src "libresoc.v:41133.20-41133.118" + wire width 5 $ternary$libresoc.v:41133$1550_Y + attribute \src "libresoc.v:41139.20-41139.116" + wire width 5 $ternary$libresoc.v:41139$1556_Y + attribute \src "libresoc.v:41173.20-41173.124" + wire width 8 $ternary$libresoc.v:41173$1590_Y + attribute \src "libresoc.v:41187.20-41187.119" + wire width 16 $ternary$libresoc.v:41187$1604_Y + attribute \src "libresoc.v:41195.20-41195.119" + wire width 16 $ternary$libresoc.v:41195$1612_Y + attribute \src "libresoc.v:41203.20-41203.119" + wire width 16 $ternary$libresoc.v:41203$1620_Y + attribute \src "libresoc.v:41211.20-41211.119" + wire width 16 $ternary$libresoc.v:41211$1628_Y + attribute \src "libresoc.v:41219.20-41219.119" + wire width 16 $ternary$libresoc.v:41219$1636_Y + attribute \src "libresoc.v:41227.20-41227.119" + wire width 16 $ternary$libresoc.v:41227$1644_Y + attribute \src "libresoc.v:41246.20-41246.112" + wire width 2 $ternary$libresoc.v:41246$1663_Y + attribute \src "libresoc.v:41252.20-41252.112" + wire width 2 $ternary$libresoc.v:41252$1669_Y + attribute \src "libresoc.v:41258.20-41258.112" + wire width 2 $ternary$libresoc.v:41258$1675_Y + attribute \src "libresoc.v:41273.20-41273.112" + wire width 3 $ternary$libresoc.v:41273$1691_Y + attribute \src "libresoc.v:41279.20-41279.112" + wire width 3 $ternary$libresoc.v:41279$1697_Y + attribute \src "libresoc.v:41285.20-41285.112" + wire width 3 $ternary$libresoc.v:41285$1703_Y + attribute \src "libresoc.v:41291.20-41291.112" + wire width 3 $ternary$libresoc.v:41291$1709_Y + attribute \src "libresoc.v:41307.20-41307.112" + wire $ternary$libresoc.v:41307$1725_Y + attribute \src "libresoc.v:41313.20-41313.112" + wire $ternary$libresoc.v:41313$1731_Y + attribute \src "libresoc.v:41319.20-41319.112" + wire $ternary$libresoc.v:41319$1737_Y + attribute \src "libresoc.v:41325.20-41325.112" + wire $ternary$libresoc.v:41325$1743_Y + attribute \src "libresoc.v:41345.20-41345.119" + wire width 3 $ternary$libresoc.v:41345$1765_Y + attribute \src "libresoc.v:41352.20-41352.119" + wire width 3 $ternary$libresoc.v:41352$1772_Y + attribute \src "libresoc.v:41358.20-41358.119" + wire width 3 $ternary$libresoc.v:41358$1778_Y + attribute \src "libresoc.v:41366.20-41366.119" + wire width 3 $ternary$libresoc.v:41366$1786_Y + attribute \src "libresoc.v:41372.20-41372.119" + wire width 3 $ternary$libresoc.v:41372$1792_Y + attribute \src "libresoc.v:41394.20-41394.112" + wire $ternary$libresoc.v:41394$1814_Y + attribute \src "libresoc.v:41401.20-41401.112" + wire $ternary$libresoc.v:41401$1821_Y + attribute \src "libresoc.v:41412.20-41412.112" + wire width 2 $ternary$libresoc.v:41412$1833_Y + attribute \src "libresoc.v:41422.20-41422.120" + wire width 10 $ternary$libresoc.v:41422$1844_Y + attribute \src "libresoc.v:41503.19-41503.124" + wire width 5 $ternary$libresoc.v:41503$1925_Y + attribute \src "libresoc.v:41509.19-41509.123" + wire width 5 $ternary$libresoc.v:41509$1931_Y + attribute \src "libresoc.v:41515.19-41515.125" + wire width 5 $ternary$libresoc.v:41515$1937_Y + attribute \src "libresoc.v:41521.19-41521.128" + wire width 5 $ternary$libresoc.v:41521$1943_Y + attribute \src "libresoc.v:41527.19-41527.124" + wire width 5 $ternary$libresoc.v:41527$1949_Y + attribute \src "libresoc.v:41533.19-41533.124" + wire width 5 $ternary$libresoc.v:41533$1955_Y + attribute \src "libresoc.v:41539.19-41539.124" + wire width 5 $ternary$libresoc.v:41539$1961_Y + attribute \src "libresoc.v:41545.19-41545.129" + wire width 5 $ternary$libresoc.v:41545$1967_Y + attribute \src "libresoc.v:41551.19-41551.125" + wire width 5 $ternary$libresoc.v:41551$1973_Y + attribute \src "libresoc.v:41566.19-41566.124" + wire width 5 $ternary$libresoc.v:41566$1988_Y + attribute \src "libresoc.v:41572.19-41572.123" + wire width 5 $ternary$libresoc.v:41572$1994_Y + attribute \src "libresoc.v:41578.19-41578.125" + wire width 5 $ternary$libresoc.v:41578$2000_Y + attribute \src "libresoc.v:41584.19-41584.128" + wire width 5 $ternary$libresoc.v:41584$2006_Y + attribute \src "libresoc.v:41590.19-41590.124" + wire width 5 $ternary$libresoc.v:41590$2012_Y + attribute \src "libresoc.v:41596.19-41596.124" + wire width 5 $ternary$libresoc.v:41596$2018_Y + attribute \src "libresoc.v:41602.19-41602.129" + wire width 5 $ternary$libresoc.v:41602$2024_Y + attribute \src "libresoc.v:41608.19-41608.125" + wire width 5 $ternary$libresoc.v:41608$2030_Y + attribute \src "libresoc.v:41622.19-41622.129" + wire width 5 $ternary$libresoc.v:41622$2044_Y + attribute \src "libresoc.v:41628.19-41628.125" + wire width 5 $ternary$libresoc.v:41628$2050_Y + attribute \src "libresoc.v:41642.19-41642.122" + wire $ternary$libresoc.v:41642$2064_Y + attribute \src "libresoc.v:41648.19-41648.126" + wire $ternary$libresoc.v:41648$2070_Y + attribute \src "libresoc.v:41654.19-41654.122" + wire $ternary$libresoc.v:41654$2076_Y + attribute \src "libresoc.v:41660.19-41660.122" + wire $ternary$libresoc.v:41660$2082_Y + attribute \src "libresoc.v:41666.19-41666.122" + wire $ternary$libresoc.v:41666$2088_Y + attribute \src "libresoc.v:41672.19-41672.127" + wire $ternary$libresoc.v:41672$2094_Y + attribute \src "libresoc.v:41688.19-41688.122" + wire width 2 $ternary$libresoc.v:41688$2111_Y + attribute \src "libresoc.v:41694.19-41694.122" + wire width 2 $ternary$libresoc.v:41694$2117_Y + attribute \src "libresoc.v:41700.19-41700.127" + wire width 2 $ternary$libresoc.v:41700$2123_Y + attribute \src "libresoc.v:41713.19-41713.122" + wire width 3 $ternary$libresoc.v:41713$2137_Y + attribute \src "libresoc.v:41719.19-41719.133" + wire width 8 $ternary$libresoc.v:41719$2143_Y + attribute \src "libresoc.v:41727.19-41727.124" + wire width 16 $ternary$libresoc.v:41727$2151_Y + attribute \src "libresoc.v:41735.19-41735.128" + wire width 16 $ternary$libresoc.v:41735$2159_Y + attribute \src "libresoc.v:41744.19-41744.124" + wire width 16 $ternary$libresoc.v:41744$2168_Y + attribute \src "libresoc.v:41752.19-41752.124" + wire width 16 $ternary$libresoc.v:41752$2176_Y + attribute \src "libresoc.v:41758.19-41758.131" + wire width 3 $ternary$libresoc.v:41758$2182_Y + attribute \src "libresoc.v:41764.19-41764.129" + wire width 3 $ternary$libresoc.v:41764$2188_Y + attribute \src "libresoc.v:41770.19-41770.128" + wire width 3 $ternary$libresoc.v:41770$2194_Y + attribute \src "libresoc.v:41779.19-41779.131" + wire width 3 $ternary$libresoc.v:41779$2203_Y + attribute \src "libresoc.v:41785.19-41785.129" + wire width 3 $ternary$libresoc.v:41785$2209_Y + attribute \src "libresoc.v:41793.19-41793.128" + wire width 10 $ternary$libresoc.v:41793$2217_Y + attribute \src "libresoc.v:41810.19-41810.110" + wire width 5 $ternary$libresoc.v:41810$2234_Y + attribute \src "libresoc.v:41816.19-41816.116" + wire width 5 $ternary$libresoc.v:41816$2240_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" + wire width 5 \$1000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:400" + wire \$1002 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + wire \$1005 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire \$1009 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire \$1011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" + wire \$1015 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" + wire width 5 \$1018 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:400" + wire \$1020 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + wire \$1023 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire \$1027 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire \$1029 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" + wire \$1037 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" + wire width 5 \$1040 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:400" + wire \$1042 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + wire \$1045 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire \$1049 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire \$1051 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" + wire \$1057 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" + wire width 5 \$1060 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:400" + wire \$1062 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + wire \$1065 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire \$1069 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire \$1071 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" + wire \$1077 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" + wire width 5 \$1080 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:400" + wire \$1082 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + wire \$1085 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire \$1089 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire \$1091 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" + wire \$1096 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" + wire width 5 \$1099 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:400" + wire \$1101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + wire \$1104 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire \$1108 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire \$1110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" + wire \$1114 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" + wire width 5 \$1117 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:400" + wire \$1119 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + wire \$1122 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire \$1125 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire \$1127 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" + wire \$1130 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" + wire width 5 \$1133 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 65 \$1135 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 64 \$1136 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 64 \$1138 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 64 \$1140 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 64 \$1142 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 64 \$1144 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 65 \$1146 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 65 \$1148 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 65 \$1150 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 65 \$1152 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 5 \$1154 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 5 \$1156 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 5 \$1158 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 5 \$1160 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 5 \$1162 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 5 \$1164 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 5 \$1166 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 5 \$1168 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 5 \$1170 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire \$1172 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire \$1174 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire \$1176 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire \$1178 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire \$1180 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire \$1182 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire \$1184 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire \$1186 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire \$1188 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:400" + wire \$1190 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" + wire \$1192 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + wire \$1195 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire \$1198 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire \$1200 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" + wire \$1203 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" + wire width 8 \$1206 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:400" + wire \$1208 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" + wire \$1210 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" + wire \$1212 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" + wire \$1214 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" + wire \$1216 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" + wire \$1218 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" + wire \$1220 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + wire \$1223 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire \$1226 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire \$1228 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" + wire \$1231 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" + wire width 4 \$1234 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" + wire width 16 \$1236 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" + wire width 16 \$1238 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:400" + wire \$1240 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + wire \$1243 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire \$1246 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire \$1248 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" + wire \$1251 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" + wire width 4 \$1254 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" + wire width 16 \$1256 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" + wire width 16 \$1258 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:400" + wire \$1260 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + wire \$1263 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire \$1266 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire \$1268 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" + wire \$1271 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" + wire width 4 \$1274 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" + wire width 16 \$1276 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" + wire width 16 \$1278 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:400" + wire \$1280 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + wire \$1283 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire \$1286 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire \$1288 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" + wire \$1291 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" + wire width 4 \$1294 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" + wire width 16 \$1296 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" + wire width 16 \$1298 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:400" + wire \$1300 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + wire \$1303 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire \$1306 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire \$1308 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" + wire \$1311 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" + wire width 4 \$1314 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" + wire width 16 \$1316 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" + wire width 16 \$1318 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:400" + wire \$1320 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + wire \$1323 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire \$1326 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire \$1328 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" + wire \$1331 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" + wire width 4 \$1334 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" + wire width 16 \$1336 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" + wire width 16 \$1338 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 4 \$1340 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 4 \$1342 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 4 \$1344 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 4 \$1346 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 4 \$1348 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 16 \$1350 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 16 \$1351 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 16 \$1353 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 16 \$1355 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 16 \$1357 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 16 \$1359 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:400" + wire \$1361 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" + wire \$1363 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" + wire \$1365 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" + wire \$1367 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + wire \$1370 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire \$1373 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire \$1375 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" + wire \$1378 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" + wire width 2 \$1381 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:400" + wire \$1383 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + wire \$1386 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire \$1389 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire \$1391 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" + wire \$1394 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" + wire width 2 \$1397 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:400" + wire \$1399 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + wire \$1402 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire \$1405 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire \$1407 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" + wire \$1410 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" + wire width 2 \$1413 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 2 \$1415 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 2 \$1417 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 3 \$1419 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 2 \$1420 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 2 \$1422 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:400" + wire \$1425 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" + wire \$1427 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" + wire \$1429 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" + wire \$1431 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" + wire \$1433 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + wire \$1436 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire \$1439 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire \$1441 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" + wire \$1444 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" + wire width 3 \$1447 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:400" + wire \$1449 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + wire \$1452 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire \$1455 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire \$1457 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" + wire \$1460 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" + wire width 3 \$1463 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:400" + wire \$1465 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + wire \$1468 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire \$1471 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire \$1473 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" + wire \$1476 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" + wire width 3 \$1479 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:400" + wire \$1481 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + wire \$1484 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire \$1487 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire \$1489 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" + wire \$1492 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" + wire width 3 \$1495 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 2 \$1497 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 2 \$1499 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 2 \$1501 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 3 \$1503 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 3 \$1505 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 3 \$1507 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:400" + wire \$1509 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" + wire \$1511 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" + wire \$1513 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" + wire \$1515 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" + wire \$1517 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + wire \$1520 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire \$1523 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire \$1525 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" + wire \$1528 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" + wire \$1531 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:400" + wire \$1533 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + wire \$1536 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire \$1539 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire \$1541 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" + wire \$1544 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" + wire \$1547 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:400" + wire \$1549 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + wire \$1552 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire \$1555 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire \$1557 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" + wire \$1560 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" + wire \$1563 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:400" + wire \$1565 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + wire \$1568 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire \$1571 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire \$1573 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" + wire \$1576 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" + wire \$1579 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 2 \$1581 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire \$1582 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire \$1584 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire \$1586 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 3 \$1589 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire \$1590 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire \$1592 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire \$1594 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:400" + wire \$1597 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" + wire \$1599 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + wire \$160 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" + wire \$1601 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" + wire \$1603 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" + wire \$1605 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" + wire \$1607 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + wire width 12 \$161 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + wire \$1610 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire \$1614 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire \$1616 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" + wire \$1621 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" + wire width 3 \$1624 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:400" + wire \$1626 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + wire \$1629 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire \$1632 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire \$1634 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" + wire \$1637 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + wire \$164 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" + wire width 3 \$1640 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:400" + wire \$1642 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + wire \$1645 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire \$1648 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + wire width 12 \$165 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire \$1650 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" + wire \$1653 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" + wire width 3 \$1656 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:400" + wire \$1658 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + wire \$1661 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire \$1664 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire \$1666 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" + wire \$1669 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" + wire width 3 \$1672 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:400" + wire \$1674 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + wire \$1677 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + wire \$168 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire \$1680 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire \$1682 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" + wire \$1685 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" + wire width 3 \$1688 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + wire width 12 \$169 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 64 \$1690 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 64 \$1692 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 64 \$1694 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 64 \$1696 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 3 \$1698 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 3 \$1700 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 3 \$1702 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 3 \$1704 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire \$1706 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire \$1708 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire \$1710 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire \$1712 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:400" + wire \$1714 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" + wire \$1716 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" + wire \$1718 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + wire \$172 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + wire \$1721 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire \$1724 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire \$1726 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" + wire \$1729 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + wire width 12 \$173 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" + wire \$1732 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:400" + wire \$1734 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + wire \$1737 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire \$1740 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire \$1742 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" + wire \$1745 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" + wire \$1748 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 64 \$1750 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 4 \$1752 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire \$1753 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:400" + wire \$1756 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" + wire \$1758 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + wire \$176 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + wire \$1761 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire \$1764 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire \$1766 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" + wire \$1769 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + wire width 12 \$177 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" + wire width 2 \$1772 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + wire width 4 \$1774 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:400" + wire \$1776 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" + wire \$1778 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + wire \$1781 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire \$1784 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire \$1786 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" + wire \$1789 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" + wire width 10 \$1792 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + wire \$180 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + wire width 12 \$181 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + wire \$184 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + wire width 12 \$185 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + wire \$188 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + wire width 12 \$189 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + wire \$192 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + wire width 12 \$193 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + wire \$196 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + wire width 12 \$197 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:186" + wire \$200 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + wire width 3 \$202 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + wire width 3 \$203 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:186" + wire \$205 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:217" + wire width 4 \$207 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" + wire \$208 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" + wire width 3 \$210 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" + wire \$212 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" + wire \$214 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" + wire \$216 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" + wire \$218 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:86" + wire \$220 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" + wire width 3 \$222 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" + wire \$224 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" + wire \$226 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:217" + wire width 6 \$229 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:217" + wire width 3 \$231 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:217" + wire width 4 \$233 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:217" + wire width 3 \$235 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" + wire \$236 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" + wire width 3 \$238 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" + wire \$240 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" + wire \$242 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" + wire \$244 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" + wire \$246 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:217" + wire width 6 \$249 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" + wire \$250 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" + wire width 3 \$252 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" + wire \$254 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" + wire \$256 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" + wire \$258 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" + wire \$260 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83" + wire \$262 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" + wire width 3 \$264 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" + wire \$266 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" + wire \$268 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:86" + wire \$270 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" + wire width 3 \$272 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" + wire \$274 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" + wire \$276 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:217" + wire width 3 \$279 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" + wire \$280 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" + wire width 3 \$282 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" + wire \$284 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" + wire \$286 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" + wire \$288 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" + wire \$290 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:217" + wire width 3 \$293 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" + wire \$294 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" + wire width 3 \$296 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" + wire \$298 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" + wire \$300 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" + wire \$302 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" + wire \$304 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:217" + wire width 5 \$307 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" + wire \$308 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" + wire width 3 \$310 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" + wire \$312 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" + wire \$314 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" + wire \$316 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" + wire \$318 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:86" + wire \$320 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" + wire width 3 \$322 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" + wire \$324 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" + wire \$326 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:217" + wire width 3 \$329 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \$331 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \$333 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + wire \$335 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + wire \$337 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + wire \$339 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + wire width 5 \$341 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \$343 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \$345 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + wire \$347 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + wire \$349 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + wire \$351 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + wire width 5 \$353 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \$355 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \$357 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + wire \$359 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + wire \$361 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + wire \$363 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + wire width 5 \$365 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \$367 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \$369 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + wire \$371 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + wire \$373 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + wire \$375 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + wire width 5 \$377 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \$379 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \$381 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + wire \$383 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + wire \$385 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + wire \$387 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + wire width 5 \$389 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \$391 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \$393 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + wire \$395 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + wire \$397 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + wire \$399 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + wire width 5 \$401 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \$403 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \$405 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + wire \$407 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + wire \$409 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + wire \$411 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + wire width 5 \$413 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \$415 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \$417 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + wire \$419 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + wire \$421 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + wire \$423 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + wire width 5 \$425 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \$427 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \$429 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + wire \$431 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + wire \$433 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + wire \$435 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + wire width 5 \$437 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 5 \$439 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 5 \$441 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 5 \$443 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 5 \$445 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 5 \$447 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 5 \$449 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 5 \$451 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 5 \$453 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:313" + wire \$455 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \$457 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \$459 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + wire \$461 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + wire \$463 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + wire \$465 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + wire width 5 \$467 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \$469 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \$471 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + wire \$473 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + wire \$475 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + wire \$477 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + wire width 5 \$479 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \$481 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \$483 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + wire \$485 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + wire \$487 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + wire \$489 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + wire width 5 \$491 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \$493 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \$495 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + wire \$497 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + wire \$499 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + wire \$501 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + wire width 5 \$503 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \$505 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \$507 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + wire \$509 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + wire \$511 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + wire \$513 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + wire width 5 \$515 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \$517 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \$519 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + wire \$521 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + wire \$523 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + wire \$525 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + wire width 5 \$527 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \$529 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \$531 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + wire \$533 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + wire \$535 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + wire \$537 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + wire width 5 \$539 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \$541 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \$543 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + wire \$545 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + wire \$547 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + wire \$549 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + wire width 5 \$551 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 5 \$553 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 5 \$555 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 5 \$557 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 5 \$559 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 5 \$561 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 5 \$563 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 5 \$565 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:313" + wire \$567 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \$569 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \$571 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + wire \$573 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + wire \$575 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + wire \$577 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + wire width 5 \$579 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \$581 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \$583 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + wire \$585 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + wire \$587 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + wire \$589 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + wire width 5 \$591 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 5 \$593 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:313" + wire \$595 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" + wire \$597 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" + wire width 3 \$599 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" + wire \$601 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" + wire \$603 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" + wire \$605 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" + wire \$607 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \$609 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \$611 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + wire \$613 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + wire \$615 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + wire \$617 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + wire \$619 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \$621 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \$623 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + wire \$625 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + wire \$627 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + wire \$629 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + wire \$631 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \$633 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \$635 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + wire \$637 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + wire \$639 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + wire \$641 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + wire \$643 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \$645 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \$647 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + wire \$649 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + wire \$651 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + wire \$653 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + wire \$655 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \$657 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \$659 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + wire \$661 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + wire \$663 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + wire \$665 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + wire \$667 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \$669 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \$671 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + wire \$673 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + wire \$675 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + wire \$677 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + wire \$679 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 3 \$681 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire \$682 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire \$684 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire \$686 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire \$688 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire \$690 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:86" + wire \$693 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" + wire width 3 \$695 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" + wire \$697 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" + wire \$699 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \$701 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \$703 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + wire \$705 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + wire \$707 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + wire \$709 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + wire width 2 \$711 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \$713 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \$715 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + wire \$717 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + wire \$719 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + wire \$721 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + wire width 2 \$723 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \$725 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \$727 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + wire \$729 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + wire \$731 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + wire \$733 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + wire width 2 \$735 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 3 \$737 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 2 \$738 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 2 \$740 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83" + wire \$743 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" + wire width 3 \$745 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" + wire \$747 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" + wire \$749 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \$751 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \$753 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + wire \$755 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + wire \$757 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + wire \$759 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + wire width 3 \$761 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \$763 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \$765 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + wire \$767 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + wire \$769 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + wire \$771 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + wire width 8 \$773 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \$775 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \$777 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + wire \$779 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + wire \$781 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + wire \$783 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:64" + wire width 4 \$785 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:64" + wire width 16 \$787 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + wire width 16 \$789 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \$791 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \$793 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + wire \$795 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + wire \$797 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + wire \$799 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:64" + wire width 4 \$801 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:64" + wire width 16 \$803 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + wire width 16 \$805 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 16 \$807 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 16 \$808 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \$810 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \$812 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + wire \$814 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + wire \$816 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + wire \$818 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:66" + wire width 4 \$820 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:66" + wire width 16 \$822 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + wire width 16 \$824 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \$826 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \$828 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + wire \$830 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + wire \$832 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + wire \$834 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:68" + wire width 4 \$836 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:68" + wire width 16 \$838 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + wire width 16 \$840 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \$842 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \$844 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + wire \$846 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + wire \$848 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + wire \$850 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + wire width 3 \$852 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \$854 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \$856 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + wire \$858 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + wire \$860 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + wire \$862 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + wire width 3 \$864 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \$866 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \$868 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + wire \$870 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + wire \$872 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + wire \$874 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + wire width 3 \$876 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 3 \$878 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 3 \$880 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:313" + wire \$882 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \$884 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \$886 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + wire \$888 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + wire \$890 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + wire \$892 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + wire width 3 \$894 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \$896 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \$898 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + wire \$900 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + wire \$902 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + wire \$904 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + wire width 3 \$906 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 3 \$908 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:313" + wire \$910 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \$912 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \$914 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + wire \$916 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + wire \$918 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + wire \$920 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + wire width 10 \$922 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:313" + wire \$924 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:400" + wire \$926 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" + wire \$928 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" + wire \$930 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" + wire \$932 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" + wire \$934 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" + wire \$936 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" + wire \$938 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" + wire \$940 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" + wire \$942 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" + wire \$944 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" + wire \$946 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + wire \$948 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire \$950 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire \$952 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" + wire \$958 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" + wire width 5 \$960 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:400" + wire \$962 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + wire \$965 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire \$969 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire \$971 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" + wire \$976 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" + wire width 5 \$979 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:400" + wire \$981 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + wire \$984 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire \$988 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire \$990 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" + wire \$997 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + wire width 5 \addr_en + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + wire width 5 \addr_en$1017 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + wire width 5 \addr_en$1039 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + wire width 5 \addr_en$1059 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + wire width 5 \addr_en$1079 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + wire width 5 \addr_en$1098 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + wire width 5 \addr_en$1116 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + wire width 5 \addr_en$1132 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + wire width 8 \addr_en$1205 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + wire width 16 \addr_en$1233 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + wire width 16 \addr_en$1253 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + wire width 16 \addr_en$1273 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + wire width 16 \addr_en$1293 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + wire width 16 \addr_en$1313 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + wire width 16 \addr_en$1333 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + wire width 2 \addr_en$1380 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + wire width 2 \addr_en$1396 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + wire width 2 \addr_en$1412 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + wire width 3 \addr_en$1446 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + wire width 3 \addr_en$1462 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + wire width 3 \addr_en$1478 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + wire width 3 \addr_en$1494 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + wire \addr_en$1530 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + wire \addr_en$1546 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + wire \addr_en$1562 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + wire \addr_en$1578 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + wire width 3 \addr_en$1623 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + wire width 3 \addr_en$1639 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + wire width 3 \addr_en$1655 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + wire width 3 \addr_en$1671 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + wire width 3 \addr_en$1687 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + wire \addr_en$1731 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + wire \addr_en$1747 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + wire width 2 \addr_en$1771 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + wire width 10 \addr_en$1791 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + wire width 5 \addr_en$978 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + wire width 5 \addr_en$999 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + wire width 16 \addr_en_CR_cr_a_branch0_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + wire width 16 \addr_en_CR_cr_a_cr0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + wire width 16 \addr_en_CR_cr_b_cr0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + wire width 16 \addr_en_CR_cr_c_cr0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + wire width 8 \addr_en_CR_full_cr_cr0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + wire width 3 \addr_en_FAST_fast1_branch0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + wire width 3 \addr_en_FAST_fast1_spr0_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + wire width 3 \addr_en_FAST_fast1_trap0_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + wire width 3 \addr_en_FAST_fast2_branch0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + wire width 3 \addr_en_FAST_fast2_trap0_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + wire width 5 \addr_en_INT_ra_alu0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + wire width 5 \addr_en_INT_ra_cr0_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + wire width 5 \addr_en_INT_ra_div0_5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + wire width 5 \addr_en_INT_ra_ldst0_8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + wire width 5 \addr_en_INT_ra_logical0_3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + wire width 5 \addr_en_INT_ra_mul0_6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + wire width 5 \addr_en_INT_ra_shiftrot0_7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + wire width 5 \addr_en_INT_ra_spr0_4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + wire width 5 \addr_en_INT_ra_trap0_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + wire width 5 \addr_en_INT_rb_alu0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + wire width 5 \addr_en_INT_rb_cr0_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + wire width 5 \addr_en_INT_rb_div0_4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + wire width 5 \addr_en_INT_rb_ldst0_7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + wire width 5 \addr_en_INT_rb_logical0_3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + wire width 5 \addr_en_INT_rb_mul0_5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + wire width 5 \addr_en_INT_rb_shiftrot0_6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + wire width 5 \addr_en_INT_rb_trap0_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + wire width 5 \addr_en_INT_rc_ldst0_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + wire width 5 \addr_en_INT_rc_shiftrot0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + wire width 10 \addr_en_SPR_spr1_spr0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + wire width 2 \addr_en_XER_xer_ca_alu0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + wire width 2 \addr_en_XER_xer_ca_shiftrot0_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + wire width 2 \addr_en_XER_xer_ca_spr0_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + wire width 3 \addr_en_XER_xer_ov_spr0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + wire \addr_en_XER_xer_so_alu0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + wire \addr_en_XER_xer_so_div0_3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + wire \addr_en_XER_xer_so_logical0_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + wire \addr_en_XER_xer_so_mul0_4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + wire \addr_en_XER_xer_so_shiftrot0_5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + wire \addr_en_XER_xer_so_spr0_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:94" + wire input 55 \bigendian_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 output 8 \cia__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 input 7 \cia__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:42" + wire width 64 input 39 \core_core_cia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 8 input 50 \core_core_cr_rd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire input 51 \core_core_cr_rd_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 8 input 52 \core_core_cr_wr + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47" + wire width 12 input 42 \core_core_fn_unit + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:51" + wire width 2 input 47 \core_core_input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:45" + wire width 32 input 40 \core_core_insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:46" + wire width 7 input 41 \core_core_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:56" + wire input 53 \core_core_is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:41" + wire width 64 input 38 \core_core_msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire input 45 \core_core_oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire input 46 \core_core_oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire input 43 \core_core_rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire input 44 \core_core_rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53" + wire width 13 input 49 \core_core_trapaddr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:52" + wire width 7 input 48 \core_core_traptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 input 31 \core_cr_in1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire input 32 \core_cr_in1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 input 33 \core_cr_in2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 input 35 \core_cr_in2$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire input 34 \core_cr_in2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire input 36 \core_cr_in2_ok$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 input 37 \core_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 input 14 \core_ea + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 input 25 \core_fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire input 26 \core_fast1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 input 27 \core_fast2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire input 28 \core_fast2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 input 29 \core_fasto1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 input 30 \core_fasto2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:8" + wire width 64 input 57 \core_pc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 input 15 \core_reg1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire input 16 \core_reg1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 input 17 \core_reg2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire input 18 \core_reg2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 input 19 \core_reg3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire input 20 \core_reg3_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 input 13 \core_rego + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:103" + wire input 1 \core_reset_i + attribute \enum_base_type "SPR" + attribute \enum_value_0000000001 "XER" + attribute \enum_value_0000000011 "DSCR" + attribute \enum_value_0000001000 "LR" + attribute \enum_value_0000001001 "CTR" + attribute \enum_value_0000001101 "AMR" + attribute \enum_value_0000010001 "DSCR_priv" + attribute \enum_value_0000010010 "DSISR" + attribute \enum_value_0000010011 "DAR" + attribute \enum_value_0000010110 "DEC" + attribute \enum_value_0000011010 "SRR0" + attribute \enum_value_0000011011 "SRR1" + attribute \enum_value_0000011100 "CFAR" + attribute \enum_value_0000011101 "AMR_priv" + attribute \enum_value_0000110000 "PIDR" + attribute \enum_value_0000111101 "IAMR" + attribute \enum_value_0010000000 "TFHAR" + attribute \enum_value_0010000001 "TFIAR" + attribute \enum_value_0010000010 "TEXASR" + attribute \enum_value_0010000011 "TEXASRU" + attribute \enum_value_0010001000 "CTRL" + attribute \enum_value_0010010000 "TIDR" + attribute \enum_value_0010011000 "CTRL_priv" + attribute \enum_value_0010011001 "FSCR" + attribute \enum_value_0010011101 "UAMOR" + attribute \enum_value_0010011110 "GSR" + attribute \enum_value_0010011111 "PSPB" + attribute \enum_value_0010110000 "DPDES" + attribute \enum_value_0010110100 "DAWR0" + attribute \enum_value_0010111010 "RPR" + attribute \enum_value_0010111011 "CIABR" + attribute \enum_value_0010111100 "DAWRX0" + attribute \enum_value_0010111110 "HFSCR" + attribute \enum_value_0100000000 "VRSAVE" + attribute \enum_value_0100000011 "SPRG3" + attribute \enum_value_0100001100 "TB" + attribute \enum_value_0100001101 "TBU" + attribute \enum_value_0100010000 "SPRG0_priv" + attribute \enum_value_0100010001 "SPRG1_priv" + attribute \enum_value_0100010010 "SPRG2_priv" + attribute \enum_value_0100010011 "SPRG3_priv" + attribute \enum_value_0100011011 "CIR" + attribute \enum_value_0100011100 "TBL" + attribute \enum_value_0100011101 "TBU_hypv" + attribute \enum_value_0100011110 "TBU40" + attribute \enum_value_0100011111 "PVR" + attribute \enum_value_0100110000 "HSPRG0" + attribute \enum_value_0100110001 "HSPRG1" + attribute \enum_value_0100110010 "HDSISR" + attribute \enum_value_0100110011 "HDAR" + attribute \enum_value_0100110100 "SPURR" + attribute \enum_value_0100110101 "PURR" + attribute \enum_value_0100110110 "HDEC" + attribute \enum_value_0100111001 "HRMOR" + attribute \enum_value_0100111010 "HSRR0" + attribute \enum_value_0100111011 "HSRR1" + attribute \enum_value_0100111110 "LPCR" + attribute \enum_value_0100111111 "LPIDR" + attribute \enum_value_0101010000 "HMER" + attribute \enum_value_0101010001 "HMEER" + attribute \enum_value_0101010010 "PCR" + attribute \enum_value_0101010011 "HEIR" + attribute \enum_value_0101011101 "AMOR" + attribute \enum_value_0110111110 "TIR" + attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1100000000 "SIER" + attribute \enum_value_1100000001 "MMCR2" + attribute \enum_value_1100000010 "MMCRA" + attribute \enum_value_1100000011 "PMC1" + attribute \enum_value_1100000100 "PMC2" + attribute \enum_value_1100000101 "PMC3" + attribute \enum_value_1100000110 "PMC4" + attribute \enum_value_1100000111 "PMC5" + attribute \enum_value_1100001000 "PMC6" + attribute \enum_value_1100001011 "MMCR0" + attribute \enum_value_1100001100 "SIAR" + attribute \enum_value_1100001101 "SDAR" + attribute \enum_value_1100001110 "MMCR1" + attribute \enum_value_1100010000 "SIER_priv" + attribute \enum_value_1100010001 "MMCR2_priv" + attribute \enum_value_1100010010 "MMCRA_priv" + attribute \enum_value_1100010011 "PMC1_priv" + attribute \enum_value_1100010100 "PMC2_priv" + attribute \enum_value_1100010101 "PMC3_priv" + attribute \enum_value_1100010110 "PMC4_priv" + attribute \enum_value_1100010111 "PMC5_priv" + attribute \enum_value_1100011000 "PMC6_priv" + attribute \enum_value_1100011011 "MMCR0_priv" + attribute \enum_value_1100011100 "SIAR_priv" + attribute \enum_value_1100011101 "SDAR_priv" + attribute \enum_value_1100011110 "MMCR1_priv" + attribute \enum_value_1100100000 "BESCRS" + attribute \enum_value_1100100001 "BESCRSU" + attribute \enum_value_1100100010 "BESCRR" + attribute \enum_value_1100100011 "BESCRRU" + attribute \enum_value_1100100100 "EBBHR" + attribute \enum_value_1100100101 "EBBRR" + attribute \enum_value_1100100110 "BESCR" + attribute \enum_value_1100101000 "reserved808" + attribute \enum_value_1100101001 "reserved809" + attribute \enum_value_1100101010 "reserved810" + attribute \enum_value_1100101011 "reserved811" + attribute \enum_value_1100101111 "TAR" + attribute \enum_value_1100110000 "ASDR" + attribute \enum_value_1100110111 "PSSCR" + attribute \enum_value_1101010000 "IC" + attribute \enum_value_1101010001 "VTB" + attribute \enum_value_1101010111 "PSSCR_hypv" + attribute \enum_value_1110000000 "PPR" + attribute \enum_value_1110000010 "PPR32" + attribute \enum_value_1111111111 "PIR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 10 input 22 \core_spr1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire input 23 \core_spr1_ok + attribute \enum_base_type "SPR" + attribute \enum_value_0000000001 "XER" + attribute \enum_value_0000000011 "DSCR" + attribute \enum_value_0000001000 "LR" + attribute \enum_value_0000001001 "CTR" + attribute \enum_value_0000001101 "AMR" + attribute \enum_value_0000010001 "DSCR_priv" + attribute \enum_value_0000010010 "DSISR" + attribute \enum_value_0000010011 "DAR" + attribute \enum_value_0000010110 "DEC" + attribute \enum_value_0000011010 "SRR0" + attribute \enum_value_0000011011 "SRR1" + attribute \enum_value_0000011100 "CFAR" + attribute \enum_value_0000011101 "AMR_priv" + attribute \enum_value_0000110000 "PIDR" + attribute \enum_value_0000111101 "IAMR" + attribute \enum_value_0010000000 "TFHAR" + attribute \enum_value_0010000001 "TFIAR" + attribute \enum_value_0010000010 "TEXASR" + attribute \enum_value_0010000011 "TEXASRU" + attribute \enum_value_0010001000 "CTRL" + attribute \enum_value_0010010000 "TIDR" + attribute \enum_value_0010011000 "CTRL_priv" + attribute \enum_value_0010011001 "FSCR" + attribute \enum_value_0010011101 "UAMOR" + attribute \enum_value_0010011110 "GSR" + attribute \enum_value_0010011111 "PSPB" + attribute \enum_value_0010110000 "DPDES" + attribute \enum_value_0010110100 "DAWR0" + attribute \enum_value_0010111010 "RPR" + attribute \enum_value_0010111011 "CIABR" + attribute \enum_value_0010111100 "DAWRX0" + attribute \enum_value_0010111110 "HFSCR" + attribute \enum_value_0100000000 "VRSAVE" + attribute \enum_value_0100000011 "SPRG3" + attribute \enum_value_0100001100 "TB" + attribute \enum_value_0100001101 "TBU" + attribute \enum_value_0100010000 "SPRG0_priv" + attribute \enum_value_0100010001 "SPRG1_priv" + attribute \enum_value_0100010010 "SPRG2_priv" + attribute \enum_value_0100010011 "SPRG3_priv" + attribute \enum_value_0100011011 "CIR" + attribute \enum_value_0100011100 "TBL" + attribute \enum_value_0100011101 "TBU_hypv" + attribute \enum_value_0100011110 "TBU40" + attribute \enum_value_0100011111 "PVR" + attribute \enum_value_0100110000 "HSPRG0" + attribute \enum_value_0100110001 "HSPRG1" + attribute \enum_value_0100110010 "HDSISR" + attribute \enum_value_0100110011 "HDAR" + attribute \enum_value_0100110100 "SPURR" + attribute \enum_value_0100110101 "PURR" + attribute \enum_value_0100110110 "HDEC" + attribute \enum_value_0100111001 "HRMOR" + attribute \enum_value_0100111010 "HSRR0" + attribute \enum_value_0100111011 "HSRR1" + attribute \enum_value_0100111110 "LPCR" + attribute \enum_value_0100111111 "LPIDR" + attribute \enum_value_0101010000 "HMER" + attribute \enum_value_0101010001 "HMEER" + attribute \enum_value_0101010010 "PCR" + attribute \enum_value_0101010011 "HEIR" + attribute \enum_value_0101011101 "AMOR" + attribute \enum_value_0110111110 "TIR" + attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1100000000 "SIER" + attribute \enum_value_1100000001 "MMCR2" + attribute \enum_value_1100000010 "MMCRA" + attribute \enum_value_1100000011 "PMC1" + attribute \enum_value_1100000100 "PMC2" + attribute \enum_value_1100000101 "PMC3" + attribute \enum_value_1100000110 "PMC4" + attribute \enum_value_1100000111 "PMC5" + attribute \enum_value_1100001000 "PMC6" + attribute \enum_value_1100001011 "MMCR0" + attribute \enum_value_1100001100 "SIAR" + attribute \enum_value_1100001101 "SDAR" + attribute \enum_value_1100001110 "MMCR1" + attribute \enum_value_1100010000 "SIER_priv" + attribute \enum_value_1100010001 "MMCR2_priv" + attribute \enum_value_1100010010 "MMCRA_priv" + attribute \enum_value_1100010011 "PMC1_priv" + attribute \enum_value_1100010100 "PMC2_priv" + attribute \enum_value_1100010101 "PMC3_priv" + attribute \enum_value_1100010110 "PMC4_priv" + attribute \enum_value_1100010111 "PMC5_priv" + attribute \enum_value_1100011000 "PMC6_priv" + attribute \enum_value_1100011011 "MMCR0_priv" + attribute \enum_value_1100011100 "SIAR_priv" + attribute \enum_value_1100011101 "SDAR_priv" + attribute \enum_value_1100011110 "MMCR1_priv" + attribute \enum_value_1100100000 "BESCRS" + attribute \enum_value_1100100001 "BESCRSU" + attribute \enum_value_1100100010 "BESCRR" + attribute \enum_value_1100100011 "BESCRRU" + attribute \enum_value_1100100100 "EBBHR" + attribute \enum_value_1100100101 "EBBRR" + attribute \enum_value_1100100110 "BESCR" + attribute \enum_value_1100101000 "reserved808" + attribute \enum_value_1100101001 "reserved809" + attribute \enum_value_1100101010 "reserved810" + attribute \enum_value_1100101011 "reserved811" + attribute \enum_value_1100101111 "TAR" + attribute \enum_value_1100110000 "ASDR" + attribute \enum_value_1100110111 "PSSCR" + attribute \enum_value_1101010000 "IC" + attribute \enum_value_1101010001 "VTB" + attribute \enum_value_1101010111 "PSSCR_hypv" + attribute \enum_value_1110000000 "PPR" + attribute \enum_value_1110000010 "PPR32" + attribute \enum_value_1111111111 "PIR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 10 input 21 \core_spro + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:104" + wire output 12 \core_terminate_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:104" + wire \core_terminate_o$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:102" + wire width 3 input 24 \core_xer_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:99" + wire output 2 \corebusy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 83 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:185" + wire width 2 \counter + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:185" + wire width 2 \counter$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \cr_data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 32 \cr_full_rd__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 8 \cr_full_rd__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 32 \cr_full_wr__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 8 \cr_full_wr__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \cr_src1__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 8 \cr_src1__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \cr_src2__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 8 \cr_src2__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \cr_src3__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 8 \cr_src3__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 8 \cr_wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire input 4 \cu_ad__go_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire output 5 \cu_ad__rel_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire input 6 \cu_st__go_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire output 3 \cu_st__rel_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 input 10 \data_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire input 75 \dbus__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 45 output 80 \dbus__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire output 74 \dbus__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 64 input 79 \dbus__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 64 output 82 \dbus__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire input 76 \dbus__err + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 8 output 78 \dbus__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire output 77 \dbus__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire output 81 \dbus__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \dec_ALU_ALU_ALU__data_len + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \dec_ALU_ALU_ALU__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \dec_ALU_ALU_ALU__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_ALU_ALU_ALU__imm_data__ok + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \dec_ALU_ALU_ALU__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \dec_ALU_ALU_ALU__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \dec_ALU_ALU_ALU__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_ALU_ALU_ALU__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_ALU_ALU_ALU__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_ALU_ALU_ALU__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_ALU_ALU_ALU__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_ALU_ALU_ALU__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_ALU_ALU_ALU__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_ALU_ALU_ALU__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_ALU_ALU_ALU__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_ALU_ALU_ALU__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_ALU_ALU_ALU__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_ALU_ALU_ALU__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + wire \dec_ALU_bigendian + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:442" + wire width 32 \dec_ALU_raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \dec_BRANCH_BRANCH_BRANCH__cia + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \dec_BRANCH_BRANCH_BRANCH__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \dec_BRANCH_BRANCH_BRANCH__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_BRANCH_BRANCH_BRANCH__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \dec_BRANCH_BRANCH_BRANCH__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \dec_BRANCH_BRANCH_BRANCH__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_BRANCH_BRANCH_BRANCH__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_BRANCH_BRANCH_BRANCH__lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + wire \dec_BRANCH_bigendian + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:442" + wire width 32 \dec_BRANCH_raw_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \dec_CR_CR_CR__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \dec_CR_CR_CR__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \dec_CR_CR_CR__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + wire \dec_CR_bigendian + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:442" + wire width 32 \dec_CR_raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \dec_DIV_DIV_DIV__data_len + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \dec_DIV_DIV_DIV__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \dec_DIV_DIV_DIV__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_DIV_DIV_DIV__imm_data__ok + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \dec_DIV_DIV_DIV__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \dec_DIV_DIV_DIV__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \dec_DIV_DIV_DIV__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_DIV_DIV_DIV__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_DIV_DIV_DIV__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_DIV_DIV_DIV__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_DIV_DIV_DIV__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_DIV_DIV_DIV__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_DIV_DIV_DIV__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_DIV_DIV_DIV__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_DIV_DIV_DIV__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_DIV_DIV_DIV__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_DIV_DIV_DIV__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_DIV_DIV_DIV__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + wire \dec_DIV_bigendian + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:442" + wire width 32 \dec_DIV_raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_LDST_LDST_LDST__byte_reverse + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \dec_LDST_LDST_LDST__data_len + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \dec_LDST_LDST_LDST__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \dec_LDST_LDST_LDST__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_LDST_LDST_LDST__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \dec_LDST_LDST_LDST__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \dec_LDST_LDST_LDST__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_LDST_LDST_LDST__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_LDST_LDST_LDST__is_signed + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \dec_LDST_LDST_LDST__ldst_mode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_LDST_LDST_LDST__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_LDST_LDST_LDST__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_LDST_LDST_LDST__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_LDST_LDST_LDST__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_LDST_LDST_LDST__sign_extend + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_LDST_LDST_LDST__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + wire \dec_LDST_bigendian + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:442" + wire width 32 \dec_LDST_raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \dec_LOGICAL_LOGICAL_LOGICAL__data_len + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \dec_LOGICAL_LOGICAL_LOGICAL__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \dec_LOGICAL_LOGICAL_LOGICAL__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_LOGICAL_LOGICAL_LOGICAL__imm_data__ok + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \dec_LOGICAL_LOGICAL_LOGICAL__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \dec_LOGICAL_LOGICAL_LOGICAL__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \dec_LOGICAL_LOGICAL_LOGICAL__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_LOGICAL_LOGICAL_LOGICAL__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_LOGICAL_LOGICAL_LOGICAL__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_LOGICAL_LOGICAL_LOGICAL__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_LOGICAL_LOGICAL_LOGICAL__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_LOGICAL_LOGICAL_LOGICAL__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_LOGICAL_LOGICAL_LOGICAL__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_LOGICAL_LOGICAL_LOGICAL__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_LOGICAL_LOGICAL_LOGICAL__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_LOGICAL_LOGICAL_LOGICAL__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_LOGICAL_LOGICAL_LOGICAL__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_LOGICAL_LOGICAL_LOGICAL__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + wire \dec_LOGICAL_bigendian + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:442" + wire width 32 \dec_LOGICAL_raw_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \dec_MUL_MUL_MUL__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \dec_MUL_MUL_MUL__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_MUL_MUL_MUL__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \dec_MUL_MUL_MUL__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \dec_MUL_MUL_MUL__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_MUL_MUL_MUL__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_MUL_MUL_MUL__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_MUL_MUL_MUL__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_MUL_MUL_MUL__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_MUL_MUL_MUL__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_MUL_MUL_MUL__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_MUL_MUL_MUL__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + wire \dec_MUL_bigendian + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:442" + wire width 32 \dec_MUL_raw_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__imm_data__ok + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__input_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__output_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + wire \dec_SHIFT_ROT_bigendian + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:442" + wire width 32 \dec_SHIFT_ROT_raw_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \dec_SPR_SPR_SPR__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \dec_SPR_SPR_SPR__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \dec_SPR_SPR_SPR__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_SPR_SPR_SPR__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + wire \dec_SPR_bigendian + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:442" + wire width 32 \dec_SPR_raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 5 input 61 \dmi__addr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 output 63 \dmi__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 62 \dmi__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + wire \dp_CR_cr_a_branch0_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + wire \dp_CR_cr_a_branch0_1$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + wire \dp_CR_cr_a_cr0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + wire \dp_CR_cr_a_cr0_0$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + wire \dp_CR_cr_b_cr0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + wire \dp_CR_cr_b_cr0_0$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + wire \dp_CR_cr_c_cr0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + wire \dp_CR_cr_c_cr0_0$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + wire \dp_CR_full_cr_cr0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + wire \dp_CR_full_cr_cr0_0$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + wire \dp_FAST_fast1_branch0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + wire \dp_FAST_fast1_branch0_0$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + wire \dp_FAST_fast1_spr0_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + wire \dp_FAST_fast1_spr0_2$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + wire \dp_FAST_fast1_trap0_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + wire \dp_FAST_fast1_trap0_1$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + wire \dp_FAST_fast2_branch0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + wire \dp_FAST_fast2_branch0_0$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + wire \dp_FAST_fast2_trap0_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + wire \dp_FAST_fast2_trap0_1$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + wire \dp_INT_ra_alu0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + wire \dp_INT_ra_alu0_0$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + wire \dp_INT_ra_cr0_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + wire \dp_INT_ra_cr0_1$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + wire \dp_INT_ra_div0_5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + wire \dp_INT_ra_div0_5$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + wire \dp_INT_ra_ldst0_8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + wire \dp_INT_ra_ldst0_8$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + wire \dp_INT_ra_logical0_3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + wire \dp_INT_ra_logical0_3$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + wire \dp_INT_ra_mul0_6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + wire \dp_INT_ra_mul0_6$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + wire \dp_INT_ra_shiftrot0_7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + wire \dp_INT_ra_shiftrot0_7$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + wire \dp_INT_ra_spr0_4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + wire \dp_INT_ra_spr0_4$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + wire \dp_INT_ra_trap0_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + wire \dp_INT_ra_trap0_2$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + wire \dp_INT_rb_alu0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + wire \dp_INT_rb_alu0_0$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + wire \dp_INT_rb_cr0_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + wire \dp_INT_rb_cr0_1$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + wire \dp_INT_rb_div0_4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + wire \dp_INT_rb_div0_4$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + wire \dp_INT_rb_ldst0_7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + wire \dp_INT_rb_ldst0_7$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + wire \dp_INT_rb_logical0_3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + wire \dp_INT_rb_logical0_3$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + wire \dp_INT_rb_mul0_5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + wire \dp_INT_rb_mul0_5$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + wire \dp_INT_rb_shiftrot0_6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + wire \dp_INT_rb_shiftrot0_6$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + wire \dp_INT_rb_trap0_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + wire \dp_INT_rb_trap0_2$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + wire \dp_INT_rc_ldst0_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + wire \dp_INT_rc_ldst0_1$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + wire \dp_INT_rc_shiftrot0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + wire \dp_INT_rc_shiftrot0_0$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + wire \dp_SPR_spr1_spr0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + wire \dp_SPR_spr1_spr0_0$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + wire \dp_XER_xer_ca_alu0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + wire \dp_XER_xer_ca_alu0_0$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + wire \dp_XER_xer_ca_shiftrot0_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + wire \dp_XER_xer_ca_shiftrot0_2$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + wire \dp_XER_xer_ca_spr0_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + wire \dp_XER_xer_ca_spr0_1$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + wire \dp_XER_xer_ov_spr0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + wire \dp_XER_xer_ov_spr0_0$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + wire \dp_XER_xer_so_alu0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + wire \dp_XER_xer_so_alu0_0$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + wire \dp_XER_xer_so_div0_3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + wire \dp_XER_xer_so_div0_3$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + wire \dp_XER_xer_so_logical0_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + wire \dp_XER_xer_so_logical0_1$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + wire \dp_XER_xer_so_mul0_4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + wire \dp_XER_xer_so_mul0_4$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + wire \dp_XER_xer_so_shiftrot0_5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + wire \dp_XER_xer_so_shiftrot0_5$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + wire \dp_XER_xer_so_spr0_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + wire \dp_XER_xer_so_spr0_2$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \ea_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:180" + wire \en_alu0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:180" + wire \en_branch0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:180" + wire \en_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:180" + wire \en_div0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:180" + wire \en_ldst0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:180" + wire \en_logical0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:180" + wire \en_mul0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:180" + wire \en_shiftrot0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:180" + wire \en_spr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:180" + wire \en_trap0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 3 \fast_dest1__addr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \fast_dest1__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \fast_dest1__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 3 \fast_src1__addr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \fast_src1__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \fast_src1__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 3 \fast_src2__addr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \fast_src2__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \fast_src2__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:170" + wire width 10 \fu_enable + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 32 output 65 \full_rd2__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 8 input 64 \full_rd2__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 6 output 67 \full_rd__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 3 input 66 \full_rd__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \fus_cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \fus_cr_a_ok$113 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \fus_cr_a_ok$114 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \fus_cr_a_ok$115 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \fus_cr_a_ok$116 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \fus_cr_a_ok$117 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" + wire \fus_cu_busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" + wire \fus_cu_busy_o$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" + wire \fus_cu_busy_o$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" + wire \fus_cu_busy_o$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" + wire \fus_cu_busy_o$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" + wire \fus_cu_busy_o$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" + wire \fus_cu_busy_o$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" + wire \fus_cu_busy_o$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" + wire \fus_cu_busy_o$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" + wire \fus_cu_busy_o$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" + wire \fus_cu_issue_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" + wire \fus_cu_issue_i$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" + wire \fus_cu_issue_i$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" + wire \fus_cu_issue_i$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" + wire \fus_cu_issue_i$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" + wire \fus_cu_issue_i$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" + wire \fus_cu_issue_i$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" + wire \fus_cu_issue_i$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" + wire \fus_cu_issue_i$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" + wire \fus_cu_issue_i$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 4 \fus_cu_rd__go_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 6 \fus_cu_rd__go_i$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 4 \fus_cu_rd__go_i$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 \fus_cu_rd__go_i$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 6 \fus_cu_rd__go_i$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 \fus_cu_rd__go_i$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 \fus_cu_rd__go_i$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 5 \fus_cu_rd__go_i$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 \fus_cu_rd__go_i$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 \fus_cu_rd__go_i$73 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 4 \fus_cu_rd__rel_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 6 \fus_cu_rd__rel_o$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 4 \fus_cu_rd__rel_o$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 \fus_cu_rd__rel_o$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 6 \fus_cu_rd__rel_o$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 \fus_cu_rd__rel_o$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 \fus_cu_rd__rel_o$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 5 \fus_cu_rd__rel_o$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 \fus_cu_rd__rel_o$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 \fus_cu_rd__rel_o$72 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" + wire width 4 \fus_cu_rdmaskn_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" + wire width 4 \fus_cu_rdmaskn_i$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" + wire width 3 \fus_cu_rdmaskn_i$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" + wire width 6 \fus_cu_rdmaskn_i$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" + wire width 3 \fus_cu_rdmaskn_i$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" + wire width 3 \fus_cu_rdmaskn_i$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" + wire width 5 \fus_cu_rdmaskn_i$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" + wire width 3 \fus_cu_rdmaskn_i$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" + wire width 6 \fus_cu_rdmaskn_i$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" + wire width 3 \fus_cu_rdmaskn_i$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 5 \fus_cu_wr__go_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 4 \fus_cu_wr__go_i$100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 \fus_cu_wr__go_i$103 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 2 \fus_cu_wr__go_i$105 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 \fus_cu_wr__go_i$140 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 \fus_cu_wr__go_i$85 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 5 \fus_cu_wr__go_i$88 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 2 \fus_cu_wr__go_i$91 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 6 \fus_cu_wr__go_i$94 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 4 \fus_cu_wr__go_i$97 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 5 \fus_cu_wr__rel_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 \fus_cu_wr__rel_o$102 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 2 \fus_cu_wr__rel_o$104 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 \fus_cu_wr__rel_o$139 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 \fus_cu_wr__rel_o$84 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 5 \fus_cu_wr__rel_o$87 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 2 \fus_cu_wr__rel_o$90 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 6 \fus_cu_wr__rel_o$93 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 4 \fus_cu_wr__rel_o$96 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 4 \fus_cu_wr__rel_o$99 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 \fus_dest1_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 \fus_dest1_o$106 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 \fus_dest1_o$107 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 \fus_dest1_o$108 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 \fus_dest1_o$109 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 \fus_dest1_o$110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 \fus_dest1_o$111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 \fus_dest1_o$112 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 \fus_dest1_o$144 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 32 \fus_dest2_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 4 \fus_dest2_o$118 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 4 \fus_dest2_o$119 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 4 \fus_dest2_o$120 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 4 \fus_dest2_o$121 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 4 \fus_dest2_o$122 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 \fus_dest2_o$145 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 \fus_dest2_o$147 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 \fus_dest2_o$153 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 4 \fus_dest3_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 2 \fus_dest3_o$125 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 2 \fus_dest3_o$126 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 2 \fus_dest3_o$130 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 2 \fus_dest3_o$131 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 \fus_dest3_o$146 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 \fus_dest3_o$148 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 \fus_dest3_o$150 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 2 \fus_dest4_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire \fus_dest4_o$136 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire \fus_dest4_o$137 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire \fus_dest4_o$138 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 \fus_dest4_o$151 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 2 \fus_dest5_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire \fus_dest5_o$135 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 \fus_dest5_o$152 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 2 \fus_dest6_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \fus_ea + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \fus_fast1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \fus_fast1_ok$141 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \fus_fast1_ok$142 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \fus_fast2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \fus_fast2_ok$143 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \fus_full_cr_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:110" + wire \fus_ldst_port0_addr_exc_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 96 \fus_ldst_port0_addr_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \fus_ldst_port0_addr_i_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:109" + wire \fus_ldst_port0_addr_ok_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:105" + wire \fus_ldst_port0_busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102" + wire width 4 \fus_ldst_port0_data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:98" + wire \fus_ldst_port0_is_ld_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" + wire \fus_ldst_port0_is_st_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \fus_ldst_port0_ld_data_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \fus_ldst_port0_ld_data_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \fus_ldst_port0_st_data_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \fus_ldst_port0_st_data_i_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \fus_msr_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \fus_nia_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \fus_nia_ok$149 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \fus_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \fus_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \fus_o_ok$101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \fus_o_ok$83 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \fus_o_ok$86 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \fus_o_ok$89 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \fus_o_ok$92 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \fus_o_ok$95 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \fus_o_ok$98 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \fus_oper_i_alu_alu0__data_len + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \fus_oper_i_alu_alu0__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \fus_oper_i_alu_alu0__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_alu0__imm_data__ok + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \fus_oper_i_alu_alu0__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \fus_oper_i_alu_alu0__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \fus_oper_i_alu_alu0__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_alu0__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_alu0__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_alu0__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_alu0__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_alu0__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_alu0__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_alu0__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_alu0__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_alu0__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_alu0__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_alu0__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \fus_oper_i_alu_branch0__cia + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \fus_oper_i_alu_branch0__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \fus_oper_i_alu_branch0__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_branch0__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \fus_oper_i_alu_branch0__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \fus_oper_i_alu_branch0__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_branch0__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_branch0__lk + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \fus_oper_i_alu_cr0__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \fus_oper_i_alu_cr0__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \fus_oper_i_alu_cr0__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \fus_oper_i_alu_div0__data_len + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \fus_oper_i_alu_div0__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \fus_oper_i_alu_div0__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_div0__imm_data__ok + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \fus_oper_i_alu_div0__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \fus_oper_i_alu_div0__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \fus_oper_i_alu_div0__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_div0__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_div0__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_div0__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_div0__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_div0__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_div0__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_div0__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_div0__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_div0__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_div0__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_div0__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \fus_oper_i_alu_logical0__data_len + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \fus_oper_i_alu_logical0__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \fus_oper_i_alu_logical0__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_logical0__imm_data__ok + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \fus_oper_i_alu_logical0__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \fus_oper_i_alu_logical0__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \fus_oper_i_alu_logical0__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_logical0__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_logical0__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_logical0__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_logical0__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_logical0__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_logical0__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_logical0__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_logical0__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_logical0__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_logical0__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_logical0__zero_a + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \fus_oper_i_alu_mul0__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \fus_oper_i_alu_mul0__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_mul0__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \fus_oper_i_alu_mul0__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \fus_oper_i_alu_mul0__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_mul0__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_mul0__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_mul0__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_mul0__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_mul0__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_mul0__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_mul0__write_cr0 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \fus_oper_i_alu_shift_rot0__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \fus_oper_i_alu_shift_rot0__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_shift_rot0__imm_data__ok + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \fus_oper_i_alu_shift_rot0__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_shift_rot0__input_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \fus_oper_i_alu_shift_rot0__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \fus_oper_i_alu_shift_rot0__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_shift_rot0__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_shift_rot0__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_shift_rot0__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_shift_rot0__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_shift_rot0__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_shift_rot0__output_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_shift_rot0__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_shift_rot0__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_shift_rot0__write_cr0 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \fus_oper_i_alu_spr0__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \fus_oper_i_alu_spr0__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \fus_oper_i_alu_spr0__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_spr0__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \fus_oper_i_alu_trap0__cia + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \fus_oper_i_alu_trap0__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \fus_oper_i_alu_trap0__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \fus_oper_i_alu_trap0__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_trap0__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \fus_oper_i_alu_trap0__msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \fus_oper_i_alu_trap0__trapaddr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \fus_oper_i_alu_trap0__traptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_ldst_ldst0__byte_reverse + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \fus_oper_i_ldst_ldst0__data_len + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \fus_oper_i_ldst_ldst0__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \fus_oper_i_ldst_ldst0__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_ldst_ldst0__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \fus_oper_i_ldst_ldst0__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \fus_oper_i_ldst_ldst0__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_ldst_ldst0__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_ldst_ldst0__is_signed + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \fus_oper_i_ldst_ldst0__ldst_mode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_ldst_ldst0__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_ldst_ldst0__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_ldst_ldst0__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_ldst_ldst0__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_ldst_ldst0__sign_extend + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_ldst_ldst0__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \fus_spr1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 \fus_src1_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 \fus_src1_i$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 \fus_src1_i$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 \fus_src1_i$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 \fus_src1_i$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 \fus_src1_i$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 \fus_src1_i$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 \fus_src1_i$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 \fus_src1_i$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 \fus_src1_i$77 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 \fus_src2_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 \fus_src2_i$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 \fus_src2_i$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 \fus_src2_i$57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 \fus_src2_i$58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 \fus_src2_i$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 \fus_src2_i$60 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 \fus_src2_i$61 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 \fus_src2_i$80 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 \fus_src2_i$82 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 \fus_src3_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 \fus_src3_i$62 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire \fus_src3_i$63 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire \fus_src3_i$64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire \fus_src3_i$65 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire \fus_src3_i$66 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 32 \fus_src3_i$70 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 4 \fus_src3_i$74 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 \fus_src3_i$78 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 \fus_src3_i$79 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire \fus_src4_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire \fus_src4_i$67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 2 \fus_src4_i$68 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 4 \fus_src4_i$71 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 \fus_src4_i$81 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 2 \fus_src5_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 2 \fus_src5_i$69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 4 \fus_src5_i$75 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 2 \fus_src6_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 4 \fus_src6_i$76 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \fus_xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \fus_xer_ca_ok$123 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \fus_xer_ca_ok$124 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \fus_xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \fus_xer_ov_ok$127 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \fus_xer_ov_ok$128 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \fus_xer_ov_ok$129 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \fus_xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \fus_xer_so_ok$132 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \fus_xer_so_ok$133 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \fus_xer_so_ok$134 + attribute \src "libresoc.v:35346.7-35346.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 5 \int_dest1__addr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \int_dest1__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \int_dest1__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 5 \int_src1__addr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \int_src1__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \int_src1__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 5 \int_src2__addr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \int_src2__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \int_src2__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 5 \int_src3__addr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \int_src3__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \int_src3__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 3 input 68 \issue__addr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 3 input 71 \issue__addr$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 input 73 \issue__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 output 70 \issue__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 69 \issue__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 72 \issue__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:98" + wire input 59 \issue_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:97" + wire input 58 \ivalid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 output 56 \msr__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 input 11 \msr__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + wire \pick_CR_cr_a_branch0_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + wire \pick_CR_cr_a_cr0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + wire \pick_CR_cr_b_cr0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + wire \pick_CR_cr_c_cr0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + wire \pick_CR_full_cr_cr0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + wire \pick_FAST_fast1_branch0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + wire \pick_FAST_fast1_spr0_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + wire \pick_FAST_fast1_trap0_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + wire \pick_FAST_fast2_branch0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + wire \pick_FAST_fast2_trap0_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + wire \pick_INT_ra_alu0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + wire \pick_INT_ra_cr0_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + wire \pick_INT_ra_div0_5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + wire \pick_INT_ra_ldst0_8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + wire \pick_INT_ra_logical0_3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + wire \pick_INT_ra_mul0_6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + wire \pick_INT_ra_shiftrot0_7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + wire \pick_INT_ra_spr0_4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + wire \pick_INT_ra_trap0_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + wire \pick_INT_rb_alu0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + wire \pick_INT_rb_cr0_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + wire \pick_INT_rb_div0_4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + wire \pick_INT_rb_ldst0_7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + wire \pick_INT_rb_logical0_3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + wire \pick_INT_rb_mul0_5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + wire \pick_INT_rb_shiftrot0_6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + wire \pick_INT_rb_trap0_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + wire \pick_INT_rc_ldst0_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + wire \pick_INT_rc_shiftrot0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + wire \pick_SPR_spr1_spr0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + wire \pick_XER_xer_ca_alu0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + wire \pick_XER_xer_ca_shiftrot0_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + wire \pick_XER_xer_ca_spr0_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + wire \pick_XER_xer_ov_spr0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + wire \pick_XER_xer_so_alu0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + wire \pick_XER_xer_so_div0_3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + wire \pick_XER_xer_so_logical0_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + wire \pick_XER_xer_so_mul0_4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + wire \pick_XER_xer_so_shiftrot0_5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + wire \pick_XER_xer_so_spr0_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:93" + wire width 32 input 54 \raw_insn_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + wire \rdflag_CR_cr_a_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + wire \rdflag_CR_cr_b_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + wire \rdflag_CR_cr_c_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + wire \rdflag_CR_full_cr_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + wire \rdflag_FAST_fast1_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + wire \rdflag_FAST_fast2_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + wire \rdflag_INT_ra_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + wire \rdflag_INT_rb_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + wire \rdflag_INT_rc_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + wire \rdflag_SPR_spr1_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + wire \rdflag_XER_xer_ca_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + wire \rdflag_XER_xer_ov_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + wire \rdflag_XER_xer_so_0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire \rdpick_CR_cr_a_en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 2 \rdpick_CR_cr_a_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 2 \rdpick_CR_cr_a_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire \rdpick_CR_cr_b_en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire \rdpick_CR_cr_b_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire \rdpick_CR_cr_b_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire \rdpick_CR_cr_c_en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire \rdpick_CR_cr_c_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire \rdpick_CR_cr_c_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire \rdpick_CR_full_cr_en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire \rdpick_CR_full_cr_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire \rdpick_CR_full_cr_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire \rdpick_FAST_fast1_en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 3 \rdpick_FAST_fast1_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 3 \rdpick_FAST_fast1_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire \rdpick_FAST_fast2_en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 2 \rdpick_FAST_fast2_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 2 \rdpick_FAST_fast2_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire \rdpick_INT_ra_en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 9 \rdpick_INT_ra_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 9 \rdpick_INT_ra_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire \rdpick_INT_rb_en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 \rdpick_INT_rb_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 \rdpick_INT_rb_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire \rdpick_INT_rc_en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 2 \rdpick_INT_rc_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 2 \rdpick_INT_rc_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire \rdpick_SPR_spr1_en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire \rdpick_SPR_spr1_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire \rdpick_SPR_spr1_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire \rdpick_XER_xer_ca_en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 3 \rdpick_XER_xer_ca_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 3 \rdpick_XER_xer_ca_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire \rdpick_XER_xer_ov_en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire \rdpick_XER_xer_ov_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire \rdpick_XER_xer_ov_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire \rdpick_XER_xer_so_en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 6 \rdpick_XER_xer_so_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 6 \rdpick_XER_xer_so_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:274" + wire \rp_CR_cr_a_branch0_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:274" + wire \rp_CR_cr_a_cr0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:274" + wire \rp_CR_cr_b_cr0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:274" + wire \rp_CR_cr_c_cr0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:274" + wire \rp_CR_full_cr_cr0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:274" + wire \rp_FAST_fast1_branch0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:274" + wire \rp_FAST_fast1_spr0_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:274" + wire \rp_FAST_fast1_trap0_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:274" + wire \rp_FAST_fast2_branch0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:274" + wire \rp_FAST_fast2_trap0_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:274" + wire \rp_INT_ra_alu0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:274" + wire \rp_INT_ra_cr0_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:274" + wire \rp_INT_ra_div0_5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:274" + wire \rp_INT_ra_ldst0_8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:274" + wire \rp_INT_ra_logical0_3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:274" + wire \rp_INT_ra_mul0_6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:274" + wire \rp_INT_ra_shiftrot0_7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:274" + wire \rp_INT_ra_spr0_4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:274" + wire \rp_INT_ra_trap0_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:274" + wire \rp_INT_rb_alu0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:274" + wire \rp_INT_rb_cr0_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:274" + wire \rp_INT_rb_div0_4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:274" + wire \rp_INT_rb_ldst0_7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:274" + wire \rp_INT_rb_logical0_3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:274" + wire \rp_INT_rb_mul0_5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:274" + wire \rp_INT_rb_shiftrot0_6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:274" + wire \rp_INT_rb_trap0_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:274" + wire \rp_INT_rc_ldst0_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:274" + wire \rp_INT_rc_shiftrot0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:274" + wire \rp_SPR_spr1_spr0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:274" + wire \rp_XER_xer_ca_alu0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:274" + wire \rp_XER_xer_ca_shiftrot0_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:274" + wire \rp_XER_xer_ca_spr0_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:274" + wire \rp_XER_xer_ov_spr0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:274" + wire \rp_XER_xer_so_alu0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:274" + wire \rp_XER_xer_so_div0_3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:274" + wire \rp_XER_xer_so_logical0_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:274" + wire \rp_XER_xer_so_mul0_4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:274" + wire \rp_XER_xer_so_shiftrot0_5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:274" + wire \rp_XER_xer_so_spr0_2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 7 \spr_spr1__addr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 7 \spr_spr1__addr$159 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \spr_spr1__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \spr_spr1__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \spr_spr1__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \spr_spr1__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \state_data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \state_data_i$158 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 60 \state_nia_wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \state_wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 input 9 \wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" + wire \wp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" + wire \wp$1014 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" + wire \wp$1036 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" + wire \wp$1056 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" + wire \wp$1076 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" + wire \wp$1095 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" + wire \wp$1113 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" + wire \wp$1129 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" + wire \wp$1202 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" + wire \wp$1230 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" + wire \wp$1250 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" + wire \wp$1270 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" + wire \wp$1290 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" + wire \wp$1310 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" + wire \wp$1330 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" + wire \wp$1377 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" + wire \wp$1393 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" + wire \wp$1409 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" + wire \wp$1443 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" + wire \wp$1459 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" + wire \wp$1475 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" + wire \wp$1491 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" + wire \wp$1527 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" + wire \wp$1543 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" + wire \wp$1559 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" + wire \wp$1575 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" + wire \wp$1620 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" + wire \wp$1636 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" + wire \wp$1652 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" + wire \wp$1668 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" + wire \wp$1684 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" + wire \wp$1728 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" + wire \wp$1744 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" + wire \wp$1768 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" + wire \wp$1788 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" + wire \wp$975 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" + wire \wp$996 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + wire \wr_pick + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + wire \wr_pick$1004 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + wire \wr_pick$1022 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + wire \wr_pick$1044 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + wire \wr_pick$1064 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + wire \wr_pick$1084 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + wire \wr_pick$1103 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + wire \wr_pick$1121 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + wire \wr_pick$1194 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + wire \wr_pick$1222 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + wire \wr_pick$1242 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + wire \wr_pick$1262 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + wire \wr_pick$1282 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + wire \wr_pick$1302 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + wire \wr_pick$1322 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + wire \wr_pick$1369 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + wire \wr_pick$1385 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + wire \wr_pick$1401 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + wire \wr_pick$1435 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + wire \wr_pick$1451 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + wire \wr_pick$1467 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + wire \wr_pick$1483 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + wire \wr_pick$1519 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + wire \wr_pick$1535 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + wire \wr_pick$1551 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + wire \wr_pick$1567 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + wire \wr_pick$1609 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + wire \wr_pick$1628 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + wire \wr_pick$1644 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + wire \wr_pick$1660 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + wire \wr_pick$1676 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + wire \wr_pick$1720 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + wire \wr_pick$1736 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + wire \wr_pick$1760 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + wire \wr_pick$1780 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + wire \wr_pick$964 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + wire \wr_pick$983 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire \wr_pick_dly + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire \wr_pick_dly$1007 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire \wr_pick_dly$1007$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire \wr_pick_dly$1025 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire \wr_pick_dly$1025$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire \wr_pick_dly$1047 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire \wr_pick_dly$1047$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire \wr_pick_dly$1067 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire \wr_pick_dly$1067$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire \wr_pick_dly$1087 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire \wr_pick_dly$1087$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire \wr_pick_dly$1106 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire \wr_pick_dly$1106$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire \wr_pick_dly$1124 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire \wr_pick_dly$1124$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire \wr_pick_dly$1197 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire \wr_pick_dly$1197$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire \wr_pick_dly$1225 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire \wr_pick_dly$1225$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire \wr_pick_dly$1245 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire \wr_pick_dly$1245$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire \wr_pick_dly$1265 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire \wr_pick_dly$1265$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire \wr_pick_dly$1285 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire \wr_pick_dly$1285$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire \wr_pick_dly$1305 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire \wr_pick_dly$1305$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire \wr_pick_dly$1325 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire \wr_pick_dly$1325$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire \wr_pick_dly$1372 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire \wr_pick_dly$1372$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire \wr_pick_dly$1388 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire \wr_pick_dly$1388$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire \wr_pick_dly$1404 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire \wr_pick_dly$1404$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire \wr_pick_dly$1438 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire \wr_pick_dly$1438$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire \wr_pick_dly$1454 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire \wr_pick_dly$1454$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire \wr_pick_dly$1470 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire \wr_pick_dly$1470$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire \wr_pick_dly$1486 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire \wr_pick_dly$1486$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire \wr_pick_dly$1522 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire \wr_pick_dly$1522$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire \wr_pick_dly$1538 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire \wr_pick_dly$1538$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire \wr_pick_dly$1554 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire \wr_pick_dly$1554$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire \wr_pick_dly$1570 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire \wr_pick_dly$1570$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire \wr_pick_dly$1612 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire \wr_pick_dly$1612$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire \wr_pick_dly$1631 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire \wr_pick_dly$1631$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire \wr_pick_dly$1647 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire \wr_pick_dly$1647$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire \wr_pick_dly$1663 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire \wr_pick_dly$1663$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire \wr_pick_dly$1679 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire \wr_pick_dly$1679$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire \wr_pick_dly$1723 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire \wr_pick_dly$1723$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire \wr_pick_dly$1739 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire \wr_pick_dly$1739$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire \wr_pick_dly$1763 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire \wr_pick_dly$1763$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire \wr_pick_dly$1783 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire \wr_pick_dly$1783$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire \wr_pick_dly$967 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire \wr_pick_dly$967$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire \wr_pick_dly$986 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire \wr_pick_dly$986$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire \wr_pick_dly$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + wire \wr_pick_rise + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + wire \wr_pick_rise$1008 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + wire \wr_pick_rise$1013 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + wire \wr_pick_rise$1026 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + wire \wr_pick_rise$1031 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + wire \wr_pick_rise$1032 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + wire \wr_pick_rise$1033 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + wire \wr_pick_rise$1034 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + wire \wr_pick_rise$1035 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + wire \wr_pick_rise$1048 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + wire \wr_pick_rise$1053 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + wire \wr_pick_rise$1054 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + wire \wr_pick_rise$1055 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + wire \wr_pick_rise$1068 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + wire \wr_pick_rise$1073 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + wire \wr_pick_rise$1074 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + wire \wr_pick_rise$1075 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + wire \wr_pick_rise$1088 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + wire \wr_pick_rise$1093 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + wire \wr_pick_rise$1094 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + wire \wr_pick_rise$1107 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + wire \wr_pick_rise$1112 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + wire \wr_pick_rise$1613 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + wire \wr_pick_rise$1618 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + wire \wr_pick_rise$1619 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + wire \wr_pick_rise$954 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + wire \wr_pick_rise$955 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + wire \wr_pick_rise$956 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + wire \wr_pick_rise$957 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + wire \wr_pick_rise$968 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + wire \wr_pick_rise$973 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + wire \wr_pick_rise$974 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + wire \wr_pick_rise$987 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + wire \wr_pick_rise$992 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + wire \wr_pick_rise$993 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + wire \wr_pick_rise$994 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + wire \wr_pick_rise$995 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + wire \wrflag_alu0_cr_a_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + wire \wrflag_alu0_o_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + wire \wrflag_alu0_xer_ca_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + wire \wrflag_alu0_xer_ov_3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + wire \wrflag_alu0_xer_so_4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + wire \wrflag_branch0_fast1_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + wire \wrflag_branch0_fast1_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + wire \wrflag_branch0_nia_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + wire \wrflag_cr0_cr_a_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + wire \wrflag_cr0_full_cr_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + wire \wrflag_cr0_o_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + wire \wrflag_div0_cr_a_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + wire \wrflag_div0_o_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + wire \wrflag_div0_xer_ov_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + wire \wrflag_div0_xer_so_3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + wire \wrflag_ldst0_o_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + wire \wrflag_ldst0_o_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + wire \wrflag_logical0_cr_a_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + wire \wrflag_logical0_o_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + wire \wrflag_mul0_cr_a_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + wire \wrflag_mul0_o_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + wire \wrflag_mul0_xer_ov_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + wire \wrflag_mul0_xer_so_3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + wire \wrflag_shiftrot0_cr_a_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + wire \wrflag_shiftrot0_o_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + wire \wrflag_shiftrot0_xer_ca_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + wire \wrflag_spr0_fast1_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + wire \wrflag_spr0_o_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + wire \wrflag_spr0_spr1_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + wire \wrflag_spr0_xer_ca_5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + wire \wrflag_spr0_xer_ov_4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + wire \wrflag_spr0_xer_so_3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + wire \wrflag_trap0_fast1_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + wire \wrflag_trap0_fast1_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + wire \wrflag_trap0_msr_4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + wire \wrflag_trap0_nia_3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + wire \wrflag_trap0_o_0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire \wrpick_CR_cr_a_en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 6 \wrpick_CR_cr_a_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 6 \wrpick_CR_cr_a_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire \wrpick_CR_full_cr_en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire \wrpick_CR_full_cr_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire \wrpick_CR_full_cr_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire \wrpick_FAST_fast1_en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 5 \wrpick_FAST_fast1_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 5 \wrpick_FAST_fast1_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire \wrpick_INT_o_en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 10 \wrpick_INT_o_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 10 \wrpick_INT_o_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire \wrpick_SPR_spr1_en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire \wrpick_SPR_spr1_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire \wrpick_SPR_spr1_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire \wrpick_STATE_msr_en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire \wrpick_STATE_msr_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire \wrpick_STATE_msr_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire \wrpick_STATE_nia_en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 2 \wrpick_STATE_nia_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 2 \wrpick_STATE_nia_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire \wrpick_XER_xer_ca_en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 3 \wrpick_XER_xer_ca_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 3 \wrpick_XER_xer_ca_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire \wrpick_XER_xer_ov_en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 4 \wrpick_XER_xer_ov_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 4 \wrpick_XER_xer_ov_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire \wrpick_XER_xer_so_en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 4 \wrpick_XER_xer_so_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 4 \wrpick_XER_xer_so_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 \xer_data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 \xer_data_i$154 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 \xer_data_i$156 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 \xer_src1__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 3 \xer_src1__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 \xer_src2__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 3 \xer_src2__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 \xer_src3__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 3 \xer_src3__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 3 \xer_wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 3 \xer_wen$155 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 3 \xer_wen$157 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:400" + cell $and $and$libresoc.v:41098$1515 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_o_ok$89 + connect \B \fus_cu_busy_o$14 + connect \Y $and$libresoc.v:41098$1515_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + cell $and $and$libresoc.v:41099$1516 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wrpick_INT_o_o [3] + connect \B \wrpick_INT_o_en_o + connect \Y $and$libresoc.v:41099$1516_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $and$libresoc.v:41101$1518 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1004 + connect \B \$1009 + connect \Y $and$libresoc.v:41101$1518_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" + cell $and $and$libresoc.v:41102$1519 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1004 + connect \B \wrpick_INT_o_en_o + connect \Y $and$libresoc.v:41102$1519_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:400" + cell $and $and$libresoc.v:41104$1521 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_o_ok$92 + connect \B \fus_cu_busy_o$17 + connect \Y $and$libresoc.v:41104$1521_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + cell $and $and$libresoc.v:41105$1522 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wrpick_INT_o_o [4] + connect \B \wrpick_INT_o_en_o + connect \Y $and$libresoc.v:41105$1522_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $and$libresoc.v:41107$1524 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1022 + connect \B \$1027 + connect \Y $and$libresoc.v:41107$1524_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" + cell $and $and$libresoc.v:41108$1525 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1022 + connect \B \wrpick_INT_o_en_o + connect \Y $and$libresoc.v:41108$1525_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:400" + cell $and $and$libresoc.v:41110$1527 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_o_ok$95 + connect \B \fus_cu_busy_o$20 + connect \Y $and$libresoc.v:41110$1527_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + cell $and $and$libresoc.v:41111$1528 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wrpick_INT_o_o [5] + connect \B \wrpick_INT_o_en_o + connect \Y $and$libresoc.v:41111$1528_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $and$libresoc.v:41113$1530 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1044 + connect \B \$1049 + connect \Y $and$libresoc.v:41113$1530_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" + cell $and $and$libresoc.v:41114$1531 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1044 + connect \B \wrpick_INT_o_en_o + connect \Y $and$libresoc.v:41114$1531_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:400" + cell $and $and$libresoc.v:41116$1533 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_o_ok$98 + connect \B \fus_cu_busy_o$23 + connect \Y $and$libresoc.v:41116$1533_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + cell $and $and$libresoc.v:41117$1534 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wrpick_INT_o_o [6] + connect \B \wrpick_INT_o_en_o + connect \Y $and$libresoc.v:41117$1534_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $and$libresoc.v:41119$1536 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1064 + connect \B \$1069 + connect \Y $and$libresoc.v:41119$1536_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" + cell $and $and$libresoc.v:41120$1537 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1064 + connect \B \wrpick_INT_o_en_o + connect \Y $and$libresoc.v:41120$1537_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:400" + cell $and $and$libresoc.v:41122$1539 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_o_ok$101 + connect \B \fus_cu_busy_o$26 + connect \Y $and$libresoc.v:41122$1539_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + cell $and $and$libresoc.v:41123$1540 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wrpick_INT_o_o [7] + connect \B \wrpick_INT_o_en_o + connect \Y $and$libresoc.v:41123$1540_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $and$libresoc.v:41125$1542 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1084 + connect \B \$1089 + connect \Y $and$libresoc.v:41125$1542_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" + cell $and $and$libresoc.v:41126$1543 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1084 + connect \B \wrpick_INT_o_en_o + connect \Y $and$libresoc.v:41126$1543_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:400" + cell $and $and$libresoc.v:41128$1545 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \o_ok + connect \B \fus_cu_busy_o$29 + connect \Y $and$libresoc.v:41128$1545_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + cell $and $and$libresoc.v:41129$1546 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wrpick_INT_o_o [8] + connect \B \wrpick_INT_o_en_o + connect \Y $and$libresoc.v:41129$1546_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $and$libresoc.v:41131$1548 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1103 + connect \B \$1108 + connect \Y $and$libresoc.v:41131$1548_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" + cell $and $and$libresoc.v:41132$1549 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1103 + connect \B \wrpick_INT_o_en_o + connect \Y $and$libresoc.v:41132$1549_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:400" + cell $and $and$libresoc.v:41134$1551 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ea_ok + connect \B \fus_cu_busy_o$29 + connect \Y $and$libresoc.v:41134$1551_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + cell $and $and$libresoc.v:41135$1552 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wrpick_INT_o_o [9] + connect \B \wrpick_INT_o_en_o + connect \Y $and$libresoc.v:41135$1552_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $and$libresoc.v:41137$1554 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1121 + connect \B \$1125 + connect \Y $and$libresoc.v:41137$1554_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" + cell $and $and$libresoc.v:41138$1555 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1121 + connect \B \wrpick_INT_o_en_o + connect \Y $and$libresoc.v:41138$1555_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:400" + cell $and $and$libresoc.v:41167$1584 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_full_cr_ok + connect \B \fus_cu_busy_o$5 + connect \Y $and$libresoc.v:41167$1584_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" + cell $and $and$libresoc.v:41168$1585 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_wr__rel_o$84 [1] + connect \B \fu_enable [1] + connect \Y $and$libresoc.v:41168$1585_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + cell $and $and$libresoc.v:41169$1586 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wrpick_CR_full_cr_o + connect \B \wrpick_CR_full_cr_en_o + connect \Y $and$libresoc.v:41169$1586_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $and$libresoc.v:41171$1588 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1194 + connect \B \$1198 + connect \Y $and$libresoc.v:41171$1588_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" + cell $and $and$libresoc.v:41172$1589 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1194 + connect \B \wrpick_CR_full_cr_en_o + connect \Y $and$libresoc.v:41172$1589_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:400" + cell $and $and$libresoc.v:41174$1591 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cr_a_ok + connect \B \fus_cu_busy_o + connect \Y $and$libresoc.v:41174$1591_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" + cell $and $and$libresoc.v:41175$1592 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_wr__rel_o [1] + connect \B \fu_enable [0] + connect \Y $and$libresoc.v:41175$1592_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" + cell $and $and$libresoc.v:41176$1593 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_wr__rel_o$84 [2] + connect \B \fu_enable [1] + connect \Y $and$libresoc.v:41176$1593_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" + cell $and $and$libresoc.v:41177$1594 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_wr__rel_o$90 [1] + connect \B \fu_enable [4] + connect \Y $and$libresoc.v:41177$1594_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" + cell $and $and$libresoc.v:41178$1595 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_wr__rel_o$96 [1] + connect \B \fu_enable [6] + connect \Y $and$libresoc.v:41178$1595_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" + cell $and $and$libresoc.v:41179$1596 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_wr__rel_o$99 [1] + connect \B \fu_enable [7] + connect \Y $and$libresoc.v:41179$1596_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" + cell $and $and$libresoc.v:41180$1597 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_wr__rel_o$102 [1] + connect \B \fu_enable [8] + connect \Y $and$libresoc.v:41180$1597_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + cell $and $and$libresoc.v:41181$1598 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wrpick_CR_cr_a_o [0] + connect \B \wrpick_CR_cr_a_en_o + connect \Y $and$libresoc.v:41181$1598_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $and$libresoc.v:41183$1600 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1222 + connect \B \$1226 + connect \Y $and$libresoc.v:41183$1600_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" + cell $and $and$libresoc.v:41184$1601 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1222 + connect \B \wrpick_CR_cr_a_en_o + connect \Y $and$libresoc.v:41184$1601_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:400" + cell $and $and$libresoc.v:41188$1605 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cr_a_ok$113 + connect \B \fus_cu_busy_o$5 + connect \Y $and$libresoc.v:41188$1605_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + cell $and $and$libresoc.v:41189$1606 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wrpick_CR_cr_a_o [1] + connect \B \wrpick_CR_cr_a_en_o + connect \Y $and$libresoc.v:41189$1606_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $and$libresoc.v:41191$1608 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1242 + connect \B \$1246 + connect \Y $and$libresoc.v:41191$1608_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" + cell $and $and$libresoc.v:41192$1609 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1242 + connect \B \wrpick_CR_cr_a_en_o + connect \Y $and$libresoc.v:41192$1609_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:400" + cell $and $and$libresoc.v:41196$1613 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cr_a_ok$114 + connect \B \fus_cu_busy_o$14 + connect \Y $and$libresoc.v:41196$1613_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + cell $and $and$libresoc.v:41197$1614 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wrpick_CR_cr_a_o [2] + connect \B \wrpick_CR_cr_a_en_o + connect \Y $and$libresoc.v:41197$1614_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $and$libresoc.v:41199$1616 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1262 + connect \B \$1266 + connect \Y $and$libresoc.v:41199$1616_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" + cell $and $and$libresoc.v:41200$1617 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1262 + connect \B \wrpick_CR_cr_a_en_o + connect \Y $and$libresoc.v:41200$1617_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:400" + cell $and $and$libresoc.v:41204$1621 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cr_a_ok$115 + connect \B \fus_cu_busy_o$20 + connect \Y $and$libresoc.v:41204$1621_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + cell $and $and$libresoc.v:41205$1622 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wrpick_CR_cr_a_o [3] + connect \B \wrpick_CR_cr_a_en_o + connect \Y $and$libresoc.v:41205$1622_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $and$libresoc.v:41207$1624 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1282 + connect \B \$1286 + connect \Y $and$libresoc.v:41207$1624_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" + cell $and $and$libresoc.v:41208$1625 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1282 + connect \B \wrpick_CR_cr_a_en_o + connect \Y $and$libresoc.v:41208$1625_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:400" + cell $and $and$libresoc.v:41212$1629 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cr_a_ok$116 + connect \B \fus_cu_busy_o$23 + connect \Y $and$libresoc.v:41212$1629_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + cell $and $and$libresoc.v:41213$1630 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wrpick_CR_cr_a_o [4] + connect \B \wrpick_CR_cr_a_en_o + connect \Y $and$libresoc.v:41213$1630_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $and$libresoc.v:41215$1632 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1302 + connect \B \$1306 + connect \Y $and$libresoc.v:41215$1632_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" + cell $and $and$libresoc.v:41216$1633 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1302 + connect \B \wrpick_CR_cr_a_en_o + connect \Y $and$libresoc.v:41216$1633_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:400" + cell $and $and$libresoc.v:41220$1637 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cr_a_ok$117 + connect \B \fus_cu_busy_o$26 + connect \Y $and$libresoc.v:41220$1637_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + cell $and $and$libresoc.v:41221$1638 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wrpick_CR_cr_a_o [5] + connect \B \wrpick_CR_cr_a_en_o + connect \Y $and$libresoc.v:41221$1638_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $and$libresoc.v:41223$1640 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1322 + connect \B \$1326 + connect \Y $and$libresoc.v:41223$1640_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" + cell $and $and$libresoc.v:41224$1641 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1322 + connect \B \wrpick_CR_cr_a_en_o + connect \Y $and$libresoc.v:41224$1641_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:400" + cell $and $and$libresoc.v:41238$1655 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_xer_ca_ok + connect \B \fus_cu_busy_o + connect \Y $and$libresoc.v:41238$1655_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" + cell $and $and$libresoc.v:41239$1656 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_wr__rel_o [2] + connect \B \fu_enable [0] + connect \Y $and$libresoc.v:41239$1656_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" + cell $and $and$libresoc.v:41240$1657 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_wr__rel_o$93 [5] + connect \B \fu_enable [5] + connect \Y $and$libresoc.v:41240$1657_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" + cell $and $and$libresoc.v:41241$1658 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_wr__rel_o$102 [2] + connect \B \fu_enable [8] + connect \Y $and$libresoc.v:41241$1658_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + cell $and $and$libresoc.v:41242$1659 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wrpick_XER_xer_ca_o [0] + connect \B \wrpick_XER_xer_ca_en_o + connect \Y $and$libresoc.v:41242$1659_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $and$libresoc.v:41244$1661 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1369 + connect \B \$1373 + connect \Y $and$libresoc.v:41244$1661_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" + cell $and $and$libresoc.v:41245$1662 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1369 + connect \B \wrpick_XER_xer_ca_en_o + connect \Y $and$libresoc.v:41245$1662_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:400" + cell $and $and$libresoc.v:41247$1664 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_xer_ca_ok$123 + connect \B \fus_cu_busy_o$17 + connect \Y $and$libresoc.v:41247$1664_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + cell $and $and$libresoc.v:41248$1665 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wrpick_XER_xer_ca_o [1] + connect \B \wrpick_XER_xer_ca_en_o + connect \Y $and$libresoc.v:41248$1665_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $and$libresoc.v:41250$1667 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1385 + connect \B \$1389 + connect \Y $and$libresoc.v:41250$1667_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" + cell $and $and$libresoc.v:41251$1668 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1385 + connect \B \wrpick_XER_xer_ca_en_o + connect \Y $and$libresoc.v:41251$1668_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:400" + cell $and $and$libresoc.v:41253$1670 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_xer_ca_ok$124 + connect \B \fus_cu_busy_o$26 + connect \Y $and$libresoc.v:41253$1670_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + cell $and $and$libresoc.v:41254$1671 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wrpick_XER_xer_ca_o [2] + connect \B \wrpick_XER_xer_ca_en_o + connect \Y $and$libresoc.v:41254$1671_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $and$libresoc.v:41256$1673 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1401 + connect \B \$1405 + connect \Y $and$libresoc.v:41256$1673_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" + cell $and $and$libresoc.v:41257$1674 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1401 + connect \B \wrpick_XER_xer_ca_en_o + connect \Y $and$libresoc.v:41257$1674_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:400" + cell $and $and$libresoc.v:41264$1682 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_xer_ov_ok + connect \B \fus_cu_busy_o + connect \Y $and$libresoc.v:41264$1682_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" + cell $and $and$libresoc.v:41265$1683 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_wr__rel_o [3] + connect \B \fu_enable [0] + connect \Y $and$libresoc.v:41265$1683_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" + cell $and $and$libresoc.v:41266$1684 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_wr__rel_o$93 [4] + connect \B \fu_enable [5] + connect \Y $and$libresoc.v:41266$1684_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" + cell $and $and$libresoc.v:41267$1685 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_wr__rel_o$96 [2] + connect \B \fu_enable [6] + connect \Y $and$libresoc.v:41267$1685_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" + cell $and $and$libresoc.v:41268$1686 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_wr__rel_o$99 [2] + connect \B \fu_enable [7] + connect \Y $and$libresoc.v:41268$1686_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + cell $and $and$libresoc.v:41269$1687 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wrpick_XER_xer_ov_o [0] + connect \B \wrpick_XER_xer_ov_en_o + connect \Y $and$libresoc.v:41269$1687_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $and$libresoc.v:41271$1689 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1435 + connect \B \$1439 + connect \Y $and$libresoc.v:41271$1689_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" + cell $and $and$libresoc.v:41272$1690 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1435 + connect \B \wrpick_XER_xer_ov_en_o + connect \Y $and$libresoc.v:41272$1690_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:400" + cell $and $and$libresoc.v:41274$1692 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_xer_ov_ok$127 + connect \B \fus_cu_busy_o$17 + connect \Y $and$libresoc.v:41274$1692_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + cell $and $and$libresoc.v:41275$1693 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wrpick_XER_xer_ov_o [1] + connect \B \wrpick_XER_xer_ov_en_o + connect \Y $and$libresoc.v:41275$1693_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $and$libresoc.v:41277$1695 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1451 + connect \B \$1455 + connect \Y $and$libresoc.v:41277$1695_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" + cell $and $and$libresoc.v:41278$1696 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1451 + connect \B \wrpick_XER_xer_ov_en_o + connect \Y $and$libresoc.v:41278$1696_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:400" + cell $and $and$libresoc.v:41280$1698 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_xer_ov_ok$128 + connect \B \fus_cu_busy_o$20 + connect \Y $and$libresoc.v:41280$1698_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + cell $and $and$libresoc.v:41281$1699 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wrpick_XER_xer_ov_o [2] + connect \B \wrpick_XER_xer_ov_en_o + connect \Y $and$libresoc.v:41281$1699_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $and$libresoc.v:41283$1701 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1467 + connect \B \$1471 + connect \Y $and$libresoc.v:41283$1701_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" + cell $and $and$libresoc.v:41284$1702 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1467 + connect \B \wrpick_XER_xer_ov_en_o + connect \Y $and$libresoc.v:41284$1702_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:400" + cell $and $and$libresoc.v:41286$1704 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_xer_ov_ok$129 + connect \B \fus_cu_busy_o$23 + connect \Y $and$libresoc.v:41286$1704_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + cell $and $and$libresoc.v:41287$1705 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wrpick_XER_xer_ov_o [3] + connect \B \wrpick_XER_xer_ov_en_o + connect \Y $and$libresoc.v:41287$1705_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $and$libresoc.v:41289$1707 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1483 + connect \B \$1487 + connect \Y $and$libresoc.v:41289$1707_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" + cell $and $and$libresoc.v:41290$1708 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1483 + connect \B \wrpick_XER_xer_ov_en_o + connect \Y $and$libresoc.v:41290$1708_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:400" + cell $and $and$libresoc.v:41298$1716 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_xer_so_ok + connect \B \fus_cu_busy_o + connect \Y $and$libresoc.v:41298$1716_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" + cell $and $and$libresoc.v:41299$1717 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_wr__rel_o [4] + connect \B \fu_enable [0] + connect \Y $and$libresoc.v:41299$1717_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" + cell $and $and$libresoc.v:41300$1718 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_wr__rel_o$93 [3] + connect \B \fu_enable [5] + connect \Y $and$libresoc.v:41300$1718_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" + cell $and $and$libresoc.v:41301$1719 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_wr__rel_o$96 [3] + connect \B \fu_enable [6] + connect \Y $and$libresoc.v:41301$1719_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" + cell $and $and$libresoc.v:41302$1720 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_wr__rel_o$99 [3] + connect \B \fu_enable [7] + connect \Y $and$libresoc.v:41302$1720_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + cell $and $and$libresoc.v:41303$1721 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wrpick_XER_xer_so_o [0] + connect \B \wrpick_XER_xer_so_en_o + connect \Y $and$libresoc.v:41303$1721_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $and$libresoc.v:41305$1723 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1519 + connect \B \$1523 + connect \Y $and$libresoc.v:41305$1723_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" + cell $and $and$libresoc.v:41306$1724 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1519 + connect \B \wrpick_XER_xer_so_en_o + connect \Y $and$libresoc.v:41306$1724_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:400" + cell $and $and$libresoc.v:41308$1726 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_xer_so_ok$132 + connect \B \fus_cu_busy_o$17 + connect \Y $and$libresoc.v:41308$1726_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + cell $and $and$libresoc.v:41309$1727 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wrpick_XER_xer_so_o [1] + connect \B \wrpick_XER_xer_so_en_o + connect \Y $and$libresoc.v:41309$1727_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $and$libresoc.v:41311$1729 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1535 + connect \B \$1539 + connect \Y $and$libresoc.v:41311$1729_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" + cell $and $and$libresoc.v:41312$1730 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1535 + connect \B \wrpick_XER_xer_so_en_o + connect \Y $and$libresoc.v:41312$1730_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:400" + cell $and $and$libresoc.v:41314$1732 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_xer_so_ok$133 + connect \B \fus_cu_busy_o$20 + connect \Y $and$libresoc.v:41314$1732_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + cell $and $and$libresoc.v:41315$1733 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wrpick_XER_xer_so_o [2] + connect \B \wrpick_XER_xer_so_en_o + connect \Y $and$libresoc.v:41315$1733_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $and$libresoc.v:41317$1735 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1551 + connect \B \$1555 + connect \Y $and$libresoc.v:41317$1735_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" + cell $and $and$libresoc.v:41318$1736 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1551 + connect \B \wrpick_XER_xer_so_en_o + connect \Y $and$libresoc.v:41318$1736_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:400" + cell $and $and$libresoc.v:41320$1738 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_xer_so_ok$134 + connect \B \fus_cu_busy_o$23 + connect \Y $and$libresoc.v:41320$1738_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + cell $and $and$libresoc.v:41321$1739 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wrpick_XER_xer_so_o [3] + connect \B \wrpick_XER_xer_so_en_o + connect \Y $and$libresoc.v:41321$1739_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $and$libresoc.v:41323$1741 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1567 + connect \B \$1571 + connect \Y $and$libresoc.v:41323$1741_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" + cell $and $and$libresoc.v:41324$1742 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1567 + connect \B \wrpick_XER_xer_so_en_o + connect \Y $and$libresoc.v:41324$1742_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:400" + cell $and $and$libresoc.v:41334$1754 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_fast1_ok + connect \B \fus_cu_busy_o$8 + connect \Y $and$libresoc.v:41334$1754_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" + cell $and $and$libresoc.v:41335$1755 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_wr__rel_o$139 [0] + connect \B \fu_enable [2] + connect \Y $and$libresoc.v:41335$1755_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" + cell $and $and$libresoc.v:41336$1756 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_wr__rel_o$87 [1] + connect \B \fu_enable [3] + connect \Y $and$libresoc.v:41336$1756_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" + cell $and $and$libresoc.v:41337$1757 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_wr__rel_o$93 [2] + connect \B \fu_enable [5] + connect \Y $and$libresoc.v:41337$1757_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" + cell $and $and$libresoc.v:41338$1758 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_wr__rel_o$139 [1] + connect \B \fu_enable [2] + connect \Y $and$libresoc.v:41338$1758_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" + cell $and $and$libresoc.v:41339$1759 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_wr__rel_o$87 [2] + connect \B \fu_enable [3] + connect \Y $and$libresoc.v:41339$1759_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + cell $and $and$libresoc.v:41340$1760 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wrpick_FAST_fast1_o [0] + connect \B \wrpick_FAST_fast1_en_o + connect \Y $and$libresoc.v:41340$1760_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $and$libresoc.v:41342$1762 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1609 + connect \B \$1614 + connect \Y $and$libresoc.v:41342$1762_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + cell $and $and$libresoc.v:41343$1763 + parameter \A_SIGNED 0 + parameter \A_WIDTH 12 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 12 + connect \A \core_core_fn_unit + connect \B 2'10 + connect \Y $and$libresoc.v:41343$1763_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" + cell $and $and$libresoc.v:41344$1764 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1609 + connect \B \wrpick_FAST_fast1_en_o + connect \Y $and$libresoc.v:41344$1764_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:400" + cell $and $and$libresoc.v:41346$1766 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_fast1_ok$141 + connect \B \fus_cu_busy_o$11 + connect \Y $and$libresoc.v:41346$1766_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + cell $and $and$libresoc.v:41348$1768 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wrpick_FAST_fast1_o [1] + connect \B \wrpick_FAST_fast1_en_o + connect \Y $and$libresoc.v:41348$1768_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $and$libresoc.v:41350$1770 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1628 + connect \B \$1632 + connect \Y $and$libresoc.v:41350$1770_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" + cell $and $and$libresoc.v:41351$1771 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1628 + connect \B \wrpick_FAST_fast1_en_o + connect \Y $and$libresoc.v:41351$1771_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:400" + cell $and $and$libresoc.v:41353$1773 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_fast1_ok$142 + connect \B \fus_cu_busy_o$17 + connect \Y $and$libresoc.v:41353$1773_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + cell $and $and$libresoc.v:41354$1774 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wrpick_FAST_fast1_o [2] + connect \B \wrpick_FAST_fast1_en_o + connect \Y $and$libresoc.v:41354$1774_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $and$libresoc.v:41356$1776 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1644 + connect \B \$1648 + connect \Y $and$libresoc.v:41356$1776_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" + cell $and $and$libresoc.v:41357$1777 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1644 + connect \B \wrpick_FAST_fast1_en_o + connect \Y $and$libresoc.v:41357$1777_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:400" + cell $and $and$libresoc.v:41359$1779 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_fast2_ok + connect \B \fus_cu_busy_o$8 + connect \Y $and$libresoc.v:41359$1779_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + cell $and $and$libresoc.v:41360$1780 + parameter \A_SIGNED 0 + parameter \A_WIDTH 12 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 12 + connect \A \core_core_fn_unit + connect \B 7'1000000 + connect \Y $and$libresoc.v:41360$1780_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + cell $and $and$libresoc.v:41361$1781 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wrpick_FAST_fast1_o [3] + connect \B \wrpick_FAST_fast1_en_o + connect \Y $and$libresoc.v:41361$1781_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $and$libresoc.v:41363$1783 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1660 + connect \B \$1664 + connect \Y $and$libresoc.v:41363$1783_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" + cell $and $and$libresoc.v:41365$1785 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1660 + connect \B \wrpick_FAST_fast1_en_o + connect \Y $and$libresoc.v:41365$1785_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:400" + cell $and $and$libresoc.v:41367$1787 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_fast2_ok$143 + connect \B \fus_cu_busy_o$11 + connect \Y $and$libresoc.v:41367$1787_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + cell $and $and$libresoc.v:41368$1788 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wrpick_FAST_fast1_o [4] + connect \B \wrpick_FAST_fast1_en_o + connect \Y $and$libresoc.v:41368$1788_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $and$libresoc.v:41370$1790 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1676 + connect \B \$1680 + connect \Y $and$libresoc.v:41370$1790_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" + cell $and $and$libresoc.v:41371$1791 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1676 + connect \B \wrpick_FAST_fast1_en_o + connect \Y $and$libresoc.v:41371$1791_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + cell $and $and$libresoc.v:41378$1798 + parameter \A_SIGNED 0 + parameter \A_WIDTH 12 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 12 + connect \A \core_core_fn_unit + connect \B 6'100000 + connect \Y $and$libresoc.v:41378$1798_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:400" + cell $and $and$libresoc.v:41387$1807 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_nia_ok + connect \B \fus_cu_busy_o$8 + connect \Y $and$libresoc.v:41387$1807_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" + cell $and $and$libresoc.v:41388$1808 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_wr__rel_o$139 [2] + connect \B \fu_enable [2] + connect \Y $and$libresoc.v:41388$1808_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" + cell $and $and$libresoc.v:41389$1809 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_wr__rel_o$87 [3] + connect \B \fu_enable [3] + connect \Y $and$libresoc.v:41389$1809_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + cell $and $and$libresoc.v:41390$1810 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wrpick_STATE_nia_o [0] + connect \B \wrpick_STATE_nia_en_o + connect \Y $and$libresoc.v:41390$1810_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $and$libresoc.v:41392$1812 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1720 + connect \B \$1724 + connect \Y $and$libresoc.v:41392$1812_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" + cell $and $and$libresoc.v:41393$1813 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1720 + connect \B \wrpick_STATE_nia_en_o + connect \Y $and$libresoc.v:41393$1813_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:400" + cell $and $and$libresoc.v:41395$1815 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_nia_ok$149 + connect \B \fus_cu_busy_o$11 + connect \Y $and$libresoc.v:41395$1815_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + cell $and $and$libresoc.v:41396$1816 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wrpick_STATE_nia_o [1] + connect \B \wrpick_STATE_nia_en_o + connect \Y $and$libresoc.v:41396$1816_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + cell $and $and$libresoc.v:41397$1817 + parameter \A_SIGNED 0 + parameter \A_WIDTH 12 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 12 + connect \A \core_core_fn_unit + connect \B 8'10000000 + connect \Y $and$libresoc.v:41397$1817_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $and$libresoc.v:41399$1819 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1736 + connect \B \$1740 + connect \Y $and$libresoc.v:41399$1819_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" + cell $and $and$libresoc.v:41400$1820 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1736 + connect \B \wrpick_STATE_nia_en_o + connect \Y $and$libresoc.v:41400$1820_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:400" + cell $and $and$libresoc.v:41406$1827 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_msr_ok + connect \B \fus_cu_busy_o$11 + connect \Y $and$libresoc.v:41406$1827_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" + cell $and $and$libresoc.v:41407$1828 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_wr__rel_o$87 [4] + connect \B \fu_enable [3] + connect \Y $and$libresoc.v:41407$1828_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + cell $and $and$libresoc.v:41408$1829 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wrpick_STATE_msr_o + connect \B \wrpick_STATE_msr_en_o + connect \Y $and$libresoc.v:41408$1829_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $and$libresoc.v:41410$1831 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1760 + connect \B \$1764 + connect \Y $and$libresoc.v:41410$1831_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" + cell $and $and$libresoc.v:41411$1832 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1760 + connect \B \wrpick_STATE_msr_en_o + connect \Y $and$libresoc.v:41411$1832_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:400" + cell $and $and$libresoc.v:41414$1836 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_spr1_ok + connect \B \fus_cu_busy_o$17 + connect \Y $and$libresoc.v:41414$1836_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" + cell $and $and$libresoc.v:41415$1837 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_wr__rel_o$93 [1] + connect \B \fu_enable [5] + connect \Y $and$libresoc.v:41415$1837_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + cell $and $and$libresoc.v:41416$1838 + parameter \A_SIGNED 0 + parameter \A_WIDTH 12 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 12 + connect \A \core_core_fn_unit + connect \B 5'10000 + connect \Y $and$libresoc.v:41416$1838_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + cell $and $and$libresoc.v:41417$1839 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wrpick_SPR_spr1_o + connect \B \wrpick_SPR_spr1_en_o + connect \Y $and$libresoc.v:41417$1839_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $and$libresoc.v:41419$1841 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1780 + connect \B \$1784 + connect \Y $and$libresoc.v:41419$1841_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" + cell $and $and$libresoc.v:41421$1843 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1780 + connect \B \wrpick_SPR_spr1_en_o + connect \Y $and$libresoc.v:41421$1843_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + cell $and $and$libresoc.v:41423$1845 + parameter \A_SIGNED 0 + parameter \A_WIDTH 12 + parameter \B_SIGNED 0 + parameter \B_WIDTH 11 + parameter \Y_WIDTH 12 + connect \A \core_core_fn_unit + connect \B 11'10000000000 + connect \Y $and$libresoc.v:41423$1845_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + cell $and $and$libresoc.v:41425$1847 + parameter \A_SIGNED 0 + parameter \A_WIDTH 12 + parameter \B_SIGNED 0 + parameter \B_WIDTH 10 + parameter \Y_WIDTH 12 + connect \A \core_core_fn_unit + connect \B 10'1000000000 + connect \Y $and$libresoc.v:41425$1847_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + cell $and $and$libresoc.v:41427$1849 + parameter \A_SIGNED 0 + parameter \A_WIDTH 12 + parameter \B_SIGNED 0 + parameter \B_WIDTH 9 + parameter \Y_WIDTH 12 + connect \A \core_core_fn_unit + connect \B 9'100000000 + connect \Y $and$libresoc.v:41427$1849_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + cell $and $and$libresoc.v:41429$1851 + parameter \A_SIGNED 0 + parameter \A_WIDTH 12 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 12 + connect \A \core_core_fn_unit + connect \B 4'1000 + connect \Y $and$libresoc.v:41429$1851_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + cell $and $and$libresoc.v:41431$1853 + parameter \A_SIGNED 0 + parameter \A_WIDTH 12 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 12 + connect \A \core_core_fn_unit + connect \B 3'100 + connect \Y $and$libresoc.v:41431$1853_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" + cell $and $and$libresoc.v:41436$1858 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \core_core_oe + connect \B \core_core_oe_ok + connect \Y $and$libresoc.v:41436$1858_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" + cell $and $and$libresoc.v:41437$1859 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \core_xer_in + connect \B 1'1 + connect \Y $and$libresoc.v:41437$1859_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" + cell $and $and$libresoc.v:41440$1862 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \core_core_rc + connect \B \core_core_rc_ok + connect \Y $and$libresoc.v:41440$1862_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" + cell $and $and$libresoc.v:41443$1865 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \core_xer_in + connect \B 3'100 + connect \Y $and$libresoc.v:41443$1865_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" + cell $and $and$libresoc.v:41450$1872 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \core_core_oe + connect \B \core_core_oe_ok + connect \Y $and$libresoc.v:41450$1872_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" + cell $and $and$libresoc.v:41451$1873 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \core_xer_in + connect \B 1'1 + connect \Y $and$libresoc.v:41451$1873_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" + cell $and $and$libresoc.v:41454$1876 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \core_core_rc + connect \B \core_core_rc_ok + connect \Y $and$libresoc.v:41454$1876_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" + cell $and $and$libresoc.v:41457$1879 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \core_core_oe + connect \B \core_core_oe_ok + connect \Y $and$libresoc.v:41457$1879_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" + cell $and $and$libresoc.v:41458$1880 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \core_xer_in + connect \B 1'1 + connect \Y $and$libresoc.v:41458$1880_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" + cell $and $and$libresoc.v:41461$1883 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \core_core_rc + connect \B \core_core_rc_ok + connect \Y $and$libresoc.v:41461$1883_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83" + cell $and $and$libresoc.v:41463$1885 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \core_core_oe + connect \B \core_core_oe_ok + connect \Y $and$libresoc.v:41463$1885_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" + cell $and $and$libresoc.v:41464$1886 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 3 + connect \A \core_xer_in + connect \B 2'10 + connect \Y $and$libresoc.v:41464$1886_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" + cell $and $and$libresoc.v:41468$1890 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \core_xer_in + connect \B 3'100 + connect \Y $and$libresoc.v:41468$1890_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" + cell $and $and$libresoc.v:41472$1894 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \core_core_oe + connect \B \core_core_oe_ok + connect \Y $and$libresoc.v:41472$1894_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" + cell $and $and$libresoc.v:41473$1895 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \core_xer_in + connect \B 1'1 + connect \Y $and$libresoc.v:41473$1895_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" + cell $and $and$libresoc.v:41476$1898 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \core_core_rc + connect \B \core_core_rc_ok + connect \Y $and$libresoc.v:41476$1898_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" + cell $and $and$libresoc.v:41479$1901 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \core_core_oe + connect \B \core_core_oe_ok + connect \Y $and$libresoc.v:41479$1901_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" + cell $and $and$libresoc.v:41480$1902 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \core_xer_in + connect \B 1'1 + connect \Y $and$libresoc.v:41480$1902_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" + cell $and $and$libresoc.v:41483$1905 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \core_core_rc + connect \B \core_core_rc_ok + connect \Y $and$libresoc.v:41483$1905_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" + cell $and $and$libresoc.v:41486$1908 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \core_core_oe + connect \B \core_core_oe_ok + connect \Y $and$libresoc.v:41486$1908_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" + cell $and $and$libresoc.v:41487$1909 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \core_xer_in + connect \B 1'1 + connect \Y $and$libresoc.v:41487$1909_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" + cell $and $and$libresoc.v:41490$1912 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \core_core_rc + connect \B \core_core_rc_ok + connect \Y $and$libresoc.v:41490$1912_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" + cell $and $and$libresoc.v:41493$1915 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \core_xer_in + connect \B 3'100 + connect \Y $and$libresoc.v:41493$1915_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + cell $and $and$libresoc.v:41498$1920 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_rd__rel_o [0] + connect \B \fu_enable [0] + connect \Y $and$libresoc.v:41498$1920_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + cell $and $and$libresoc.v:41499$1921 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$331 + connect \B \rdflag_INT_ra_0 + connect \Y $and$libresoc.v:41499$1921_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + cell $and $and$libresoc.v:41501$1923 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$333 + connect \B \$335 + connect \Y $and$libresoc.v:41501$1923_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + cell $and $and$libresoc.v:41502$1924 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \rdpick_INT_ra_o [0] + connect \B \rdpick_INT_ra_en_o + connect \Y $and$libresoc.v:41502$1924_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + cell $and $and$libresoc.v:41504$1926 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_rd__rel_o$31 [0] + connect \B \fu_enable [1] + connect \Y $and$libresoc.v:41504$1926_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + cell $and $and$libresoc.v:41505$1927 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$343 + connect \B \rdflag_INT_ra_0 + connect \Y $and$libresoc.v:41505$1927_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + cell $and $and$libresoc.v:41507$1929 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$345 + connect \B \$347 + connect \Y $and$libresoc.v:41507$1929_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + cell $and $and$libresoc.v:41508$1930 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \rdpick_INT_ra_o [1] + connect \B \rdpick_INT_ra_en_o + connect \Y $and$libresoc.v:41508$1930_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + cell $and $and$libresoc.v:41510$1932 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_rd__rel_o$34 [0] + connect \B \fu_enable [3] + connect \Y $and$libresoc.v:41510$1932_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + cell $and $and$libresoc.v:41511$1933 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$355 + connect \B \rdflag_INT_ra_0 + connect \Y $and$libresoc.v:41511$1933_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + cell $and $and$libresoc.v:41513$1935 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$357 + connect \B \$359 + connect \Y $and$libresoc.v:41513$1935_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + cell $and $and$libresoc.v:41514$1936 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \rdpick_INT_ra_o [2] + connect \B \rdpick_INT_ra_en_o + connect \Y $and$libresoc.v:41514$1936_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + cell $and $and$libresoc.v:41516$1938 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_rd__rel_o$37 [0] + connect \B \fu_enable [4] + connect \Y $and$libresoc.v:41516$1938_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + cell $and $and$libresoc.v:41517$1939 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$367 + connect \B \rdflag_INT_ra_0 + connect \Y $and$libresoc.v:41517$1939_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + cell $and $and$libresoc.v:41519$1941 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$369 + connect \B \$371 + connect \Y $and$libresoc.v:41519$1941_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + cell $and $and$libresoc.v:41520$1942 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \rdpick_INT_ra_o [3] + connect \B \rdpick_INT_ra_en_o + connect \Y $and$libresoc.v:41520$1942_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + cell $and $and$libresoc.v:41522$1944 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_rd__rel_o$40 [0] + connect \B \fu_enable [5] + connect \Y $and$libresoc.v:41522$1944_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + cell $and $and$libresoc.v:41523$1945 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$379 + connect \B \rdflag_INT_ra_0 + connect \Y $and$libresoc.v:41523$1945_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + cell $and $and$libresoc.v:41525$1947 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$381 + connect \B \$383 + connect \Y $and$libresoc.v:41525$1947_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + cell $and $and$libresoc.v:41526$1948 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \rdpick_INT_ra_o [4] + connect \B \rdpick_INT_ra_en_o + connect \Y $and$libresoc.v:41526$1948_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + cell $and $and$libresoc.v:41528$1950 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_rd__rel_o$43 [0] + connect \B \fu_enable [6] + connect \Y $and$libresoc.v:41528$1950_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + cell $and $and$libresoc.v:41529$1951 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$391 + connect \B \rdflag_INT_ra_0 + connect \Y $and$libresoc.v:41529$1951_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + cell $and $and$libresoc.v:41531$1953 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$393 + connect \B \$395 + connect \Y $and$libresoc.v:41531$1953_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + cell $and $and$libresoc.v:41532$1954 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \rdpick_INT_ra_o [5] + connect \B \rdpick_INT_ra_en_o + connect \Y $and$libresoc.v:41532$1954_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + cell $and $and$libresoc.v:41534$1956 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_rd__rel_o$46 [0] + connect \B \fu_enable [7] + connect \Y $and$libresoc.v:41534$1956_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + cell $and $and$libresoc.v:41535$1957 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$403 + connect \B \rdflag_INT_ra_0 + connect \Y $and$libresoc.v:41535$1957_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + cell $and $and$libresoc.v:41537$1959 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$405 + connect \B \$407 + connect \Y $and$libresoc.v:41537$1959_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + cell $and $and$libresoc.v:41538$1960 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \rdpick_INT_ra_o [6] + connect \B \rdpick_INT_ra_en_o + connect \Y $and$libresoc.v:41538$1960_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + cell $and $and$libresoc.v:41540$1962 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_rd__rel_o$49 [0] + connect \B \fu_enable [8] + connect \Y $and$libresoc.v:41540$1962_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + cell $and $and$libresoc.v:41541$1963 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$415 + connect \B \rdflag_INT_ra_0 + connect \Y $and$libresoc.v:41541$1963_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + cell $and $and$libresoc.v:41543$1965 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$417 + connect \B \$419 + connect \Y $and$libresoc.v:41543$1965_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + cell $and $and$libresoc.v:41544$1966 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \rdpick_INT_ra_o [7] + connect \B \rdpick_INT_ra_en_o + connect \Y $and$libresoc.v:41544$1966_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + cell $and $and$libresoc.v:41546$1968 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_rd__rel_o$52 [0] + connect \B \fu_enable [9] + connect \Y $and$libresoc.v:41546$1968_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + cell $and $and$libresoc.v:41547$1969 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$427 + connect \B \rdflag_INT_ra_0 + connect \Y $and$libresoc.v:41547$1969_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + cell $and $and$libresoc.v:41549$1971 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$429 + connect \B \$431 + connect \Y $and$libresoc.v:41549$1971_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + cell $and $and$libresoc.v:41550$1972 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \rdpick_INT_ra_o [8] + connect \B \rdpick_INT_ra_en_o + connect \Y $and$libresoc.v:41550$1972_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + cell $and $and$libresoc.v:41561$1983 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_rd__rel_o [1] + connect \B \fu_enable [0] + connect \Y $and$libresoc.v:41561$1983_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + cell $and $and$libresoc.v:41562$1984 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$457 + connect \B \rdflag_INT_rb_0 + connect \Y $and$libresoc.v:41562$1984_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + cell $and $and$libresoc.v:41564$1986 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$459 + connect \B \$461 + connect \Y $and$libresoc.v:41564$1986_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + cell $and $and$libresoc.v:41565$1987 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \rdpick_INT_rb_o [0] + connect \B \rdpick_INT_rb_en_o + connect \Y $and$libresoc.v:41565$1987_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + cell $and $and$libresoc.v:41567$1989 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_rd__rel_o$31 [1] + connect \B \fu_enable [1] + connect \Y $and$libresoc.v:41567$1989_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + cell $and $and$libresoc.v:41568$1990 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$469 + connect \B \rdflag_INT_rb_0 + connect \Y $and$libresoc.v:41568$1990_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + cell $and $and$libresoc.v:41570$1992 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$471 + connect \B \$473 + connect \Y $and$libresoc.v:41570$1992_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + cell $and $and$libresoc.v:41571$1993 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \rdpick_INT_rb_o [1] + connect \B \rdpick_INT_rb_en_o + connect \Y $and$libresoc.v:41571$1993_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + cell $and $and$libresoc.v:41573$1995 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_rd__rel_o$34 [1] + connect \B \fu_enable [3] + connect \Y $and$libresoc.v:41573$1995_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + cell $and $and$libresoc.v:41574$1996 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$481 + connect \B \rdflag_INT_rb_0 + connect \Y $and$libresoc.v:41574$1996_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + cell $and $and$libresoc.v:41576$1998 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$483 + connect \B \$485 + connect \Y $and$libresoc.v:41576$1998_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + cell $and $and$libresoc.v:41577$1999 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \rdpick_INT_rb_o [2] + connect \B \rdpick_INT_rb_en_o + connect \Y $and$libresoc.v:41577$1999_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + cell $and $and$libresoc.v:41579$2001 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_rd__rel_o$37 [1] + connect \B \fu_enable [4] + connect \Y $and$libresoc.v:41579$2001_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + cell $and $and$libresoc.v:41580$2002 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$493 + connect \B \rdflag_INT_rb_0 + connect \Y $and$libresoc.v:41580$2002_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + cell $and $and$libresoc.v:41582$2004 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$495 + connect \B \$497 + connect \Y $and$libresoc.v:41582$2004_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + cell $and $and$libresoc.v:41583$2005 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \rdpick_INT_rb_o [3] + connect \B \rdpick_INT_rb_en_o + connect \Y $and$libresoc.v:41583$2005_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + cell $and $and$libresoc.v:41585$2007 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_rd__rel_o$43 [1] + connect \B \fu_enable [6] + connect \Y $and$libresoc.v:41585$2007_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + cell $and $and$libresoc.v:41586$2008 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$505 + connect \B \rdflag_INT_rb_0 + connect \Y $and$libresoc.v:41586$2008_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + cell $and $and$libresoc.v:41588$2010 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$507 + connect \B \$509 + connect \Y $and$libresoc.v:41588$2010_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + cell $and $and$libresoc.v:41589$2011 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \rdpick_INT_rb_o [4] + connect \B \rdpick_INT_rb_en_o + connect \Y $and$libresoc.v:41589$2011_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + cell $and $and$libresoc.v:41591$2013 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_rd__rel_o$46 [1] + connect \B \fu_enable [7] + connect \Y $and$libresoc.v:41591$2013_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + cell $and $and$libresoc.v:41592$2014 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$517 + connect \B \rdflag_INT_rb_0 + connect \Y $and$libresoc.v:41592$2014_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + cell $and $and$libresoc.v:41594$2016 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$519 + connect \B \$521 + connect \Y $and$libresoc.v:41594$2016_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + cell $and $and$libresoc.v:41595$2017 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \rdpick_INT_rb_o [5] + connect \B \rdpick_INT_rb_en_o + connect \Y $and$libresoc.v:41595$2017_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + cell $and $and$libresoc.v:41597$2019 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_rd__rel_o$49 [1] + connect \B \fu_enable [8] + connect \Y $and$libresoc.v:41597$2019_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + cell $and $and$libresoc.v:41598$2020 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$529 + connect \B \rdflag_INT_rb_0 + connect \Y $and$libresoc.v:41598$2020_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + cell $and $and$libresoc.v:41600$2022 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$531 + connect \B \$533 + connect \Y $and$libresoc.v:41600$2022_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + cell $and $and$libresoc.v:41601$2023 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \rdpick_INT_rb_o [6] + connect \B \rdpick_INT_rb_en_o + connect \Y $and$libresoc.v:41601$2023_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + cell $and $and$libresoc.v:41603$2025 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_rd__rel_o$52 [1] + connect \B \fu_enable [9] + connect \Y $and$libresoc.v:41603$2025_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + cell $and $and$libresoc.v:41604$2026 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$541 + connect \B \rdflag_INT_rb_0 + connect \Y $and$libresoc.v:41604$2026_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + cell $and $and$libresoc.v:41606$2028 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$543 + connect \B \$545 + connect \Y $and$libresoc.v:41606$2028_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + cell $and $and$libresoc.v:41607$2029 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \rdpick_INT_rb_o [7] + connect \B \rdpick_INT_rb_en_o + connect \Y $and$libresoc.v:41607$2029_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + cell $and $and$libresoc.v:41617$2039 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_rd__rel_o$49 [2] + connect \B \fu_enable [8] + connect \Y $and$libresoc.v:41617$2039_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + cell $and $and$libresoc.v:41618$2040 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$569 + connect \B \rdflag_INT_rc_0 + connect \Y $and$libresoc.v:41618$2040_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + cell $and $and$libresoc.v:41620$2042 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$571 + connect \B \$573 + connect \Y $and$libresoc.v:41620$2042_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + cell $and $and$libresoc.v:41621$2043 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \rdpick_INT_rc_o [0] + connect \B \rdpick_INT_rc_en_o + connect \Y $and$libresoc.v:41621$2043_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + cell $and $and$libresoc.v:41623$2045 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_rd__rel_o$52 [2] + connect \B \fu_enable [9] + connect \Y $and$libresoc.v:41623$2045_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + cell $and $and$libresoc.v:41624$2046 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$581 + connect \B \rdflag_INT_rc_0 + connect \Y $and$libresoc.v:41624$2046_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + cell $and $and$libresoc.v:41626$2048 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$583 + connect \B \$585 + connect \Y $and$libresoc.v:41626$2048_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + cell $and $and$libresoc.v:41627$2049 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \rdpick_INT_rc_o [1] + connect \B \rdpick_INT_rc_en_o + connect \Y $and$libresoc.v:41627$2049_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" + cell $and $and$libresoc.v:41631$2053 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \core_core_oe + connect \B \core_core_oe_ok + connect \Y $and$libresoc.v:41631$2053_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" + cell $and $and$libresoc.v:41632$2054 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \core_xer_in + connect \B 1'1 + connect \Y $and$libresoc.v:41632$2054_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" + cell $and $and$libresoc.v:41635$2057 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \core_core_rc + connect \B \core_core_rc_ok + connect \Y $and$libresoc.v:41635$2057_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + cell $and $and$libresoc.v:41637$2059 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_rd__rel_o [2] + connect \B \fu_enable [0] + connect \Y $and$libresoc.v:41637$2059_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + cell $and $and$libresoc.v:41638$2060 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$609 + connect \B \rdflag_XER_xer_so_0 + connect \Y $and$libresoc.v:41638$2060_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + cell $and $and$libresoc.v:41640$2062 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$611 + connect \B \$613 + connect \Y $and$libresoc.v:41640$2062_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + cell $and $and$libresoc.v:41641$2063 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \rdpick_XER_xer_so_o [0] + connect \B \rdpick_XER_xer_so_en_o + connect \Y $and$libresoc.v:41641$2063_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + cell $and $and$libresoc.v:41643$2065 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_rd__rel_o$37 [2] + connect \B \fu_enable [4] + connect \Y $and$libresoc.v:41643$2065_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + cell $and $and$libresoc.v:41644$2066 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$621 + connect \B \rdflag_XER_xer_so_0 + connect \Y $and$libresoc.v:41644$2066_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + cell $and $and$libresoc.v:41646$2068 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$623 + connect \B \$625 + connect \Y $and$libresoc.v:41646$2068_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + cell $and $and$libresoc.v:41647$2069 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \rdpick_XER_xer_so_o [1] + connect \B \rdpick_XER_xer_so_en_o + connect \Y $and$libresoc.v:41647$2069_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + cell $and $and$libresoc.v:41649$2071 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_rd__rel_o$40 [3] + connect \B \fu_enable [5] + connect \Y $and$libresoc.v:41649$2071_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + cell $and $and$libresoc.v:41650$2072 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$633 + connect \B \rdflag_XER_xer_so_0 + connect \Y $and$libresoc.v:41650$2072_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + cell $and $and$libresoc.v:41652$2074 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$635 + connect \B \$637 + connect \Y $and$libresoc.v:41652$2074_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + cell $and $and$libresoc.v:41653$2075 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \rdpick_XER_xer_so_o [2] + connect \B \rdpick_XER_xer_so_en_o + connect \Y $and$libresoc.v:41653$2075_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + cell $and $and$libresoc.v:41655$2077 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_rd__rel_o$43 [2] + connect \B \fu_enable [6] + connect \Y $and$libresoc.v:41655$2077_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + cell $and $and$libresoc.v:41656$2078 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$645 + connect \B \rdflag_XER_xer_so_0 + connect \Y $and$libresoc.v:41656$2078_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + cell $and $and$libresoc.v:41658$2080 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$647 + connect \B \$649 + connect \Y $and$libresoc.v:41658$2080_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + cell $and $and$libresoc.v:41659$2081 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \rdpick_XER_xer_so_o [3] + connect \B \rdpick_XER_xer_so_en_o + connect \Y $and$libresoc.v:41659$2081_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + cell $and $and$libresoc.v:41661$2083 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_rd__rel_o$46 [2] + connect \B \fu_enable [7] + connect \Y $and$libresoc.v:41661$2083_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + cell $and $and$libresoc.v:41662$2084 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$657 + connect \B \rdflag_XER_xer_so_0 + connect \Y $and$libresoc.v:41662$2084_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + cell $and $and$libresoc.v:41664$2086 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$659 + connect \B \$661 + connect \Y $and$libresoc.v:41664$2086_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + cell $and $and$libresoc.v:41665$2087 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \rdpick_XER_xer_so_o [4] + connect \B \rdpick_XER_xer_so_en_o + connect \Y $and$libresoc.v:41665$2087_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + cell $and $and$libresoc.v:41667$2089 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_rd__rel_o$49 [3] + connect \B \fu_enable [8] + connect \Y $and$libresoc.v:41667$2089_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + cell $and $and$libresoc.v:41668$2090 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$669 + connect \B \rdflag_XER_xer_so_0 + connect \Y $and$libresoc.v:41668$2090_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + cell $and $and$libresoc.v:41670$2092 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$671 + connect \B \$673 + connect \Y $and$libresoc.v:41670$2092_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + cell $and $and$libresoc.v:41671$2093 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \rdpick_XER_xer_so_o [5] + connect \B \rdpick_XER_xer_so_en_o + connect \Y $and$libresoc.v:41671$2093_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" + cell $and $and$libresoc.v:41680$2103 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \core_xer_in + connect \B 3'100 + connect \Y $and$libresoc.v:41680$2103_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + cell $and $and$libresoc.v:41683$2106 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_rd__rel_o [3] + connect \B \fu_enable [0] + connect \Y $and$libresoc.v:41683$2106_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + cell $and $and$libresoc.v:41684$2107 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$701 + connect \B \rdflag_XER_xer_ca_0 + connect \Y $and$libresoc.v:41684$2107_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + cell $and $and$libresoc.v:41686$2109 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$703 + connect \B \$705 + connect \Y $and$libresoc.v:41686$2109_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + cell $and $and$libresoc.v:41687$2110 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \rdpick_XER_xer_ca_o [0] + connect \B \rdpick_XER_xer_ca_en_o + connect \Y $and$libresoc.v:41687$2110_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + cell $and $and$libresoc.v:41689$2112 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_rd__rel_o$40 [5] + connect \B \fu_enable [5] + connect \Y $and$libresoc.v:41689$2112_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + cell $and $and$libresoc.v:41690$2113 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$713 + connect \B \rdflag_XER_xer_ca_0 + connect \Y $and$libresoc.v:41690$2113_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + cell $and $and$libresoc.v:41692$2115 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$715 + connect \B \$717 + connect \Y $and$libresoc.v:41692$2115_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + cell $and $and$libresoc.v:41693$2116 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \rdpick_XER_xer_ca_o [1] + connect \B \rdpick_XER_xer_ca_en_o + connect \Y $and$libresoc.v:41693$2116_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + cell $and $and$libresoc.v:41695$2118 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_rd__rel_o$49 [4] + connect \B \fu_enable [8] + connect \Y $and$libresoc.v:41695$2118_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + cell $and $and$libresoc.v:41696$2119 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$725 + connect \B \rdflag_XER_xer_ca_0 + connect \Y $and$libresoc.v:41696$2119_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + cell $and $and$libresoc.v:41698$2121 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$727 + connect \B \$729 + connect \Y $and$libresoc.v:41698$2121_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + cell $and $and$libresoc.v:41699$2122 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \rdpick_XER_xer_ca_o [2] + connect \B \rdpick_XER_xer_ca_en_o + connect \Y $and$libresoc.v:41699$2122_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83" + cell $and $and$libresoc.v:41704$2128 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \core_core_oe + connect \B \core_core_oe_ok + connect \Y $and$libresoc.v:41704$2128_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" + cell $and $and$libresoc.v:41705$2129 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 3 + connect \A \core_xer_in + connect \B 2'10 + connect \Y $and$libresoc.v:41705$2129_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + cell $and $and$libresoc.v:41708$2132 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_rd__rel_o$40 [4] + connect \B \fu_enable [5] + connect \Y $and$libresoc.v:41708$2132_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + cell $and $and$libresoc.v:41709$2133 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$751 + connect \B \rdflag_XER_xer_ov_0 + connect \Y $and$libresoc.v:41709$2133_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + cell $and $and$libresoc.v:41711$2135 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$753 + connect \B \$755 + connect \Y $and$libresoc.v:41711$2135_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + cell $and $and$libresoc.v:41712$2136 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \rdpick_XER_xer_ov_o + connect \B \rdpick_XER_xer_ov_en_o + connect \Y $and$libresoc.v:41712$2136_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + cell $and $and$libresoc.v:41714$2138 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_rd__rel_o$31 [2] + connect \B \fu_enable [1] + connect \Y $and$libresoc.v:41714$2138_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + cell $and $and$libresoc.v:41715$2139 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$763 + connect \B \rdflag_CR_full_cr_0 + connect \Y $and$libresoc.v:41715$2139_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + cell $and $and$libresoc.v:41717$2141 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$765 + connect \B \$767 + connect \Y $and$libresoc.v:41717$2141_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + cell $and $and$libresoc.v:41718$2142 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \rdpick_CR_full_cr_o + connect \B \rdpick_CR_full_cr_en_o + connect \Y $and$libresoc.v:41718$2142_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + cell $and $and$libresoc.v:41720$2144 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_rd__rel_o$31 [3] + connect \B \fu_enable [1] + connect \Y $and$libresoc.v:41720$2144_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + cell $and $and$libresoc.v:41721$2145 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$775 + connect \B \rdflag_CR_cr_a_0 + connect \Y $and$libresoc.v:41721$2145_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + cell $and $and$libresoc.v:41723$2147 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$777 + connect \B \$779 + connect \Y $and$libresoc.v:41723$2147_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + cell $and $and$libresoc.v:41724$2148 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \rdpick_CR_cr_a_o [0] + connect \B \rdpick_CR_cr_a_en_o + connect \Y $and$libresoc.v:41724$2148_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + cell $and $and$libresoc.v:41728$2152 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_rd__rel_o$72 [2] + connect \B \fu_enable [2] + connect \Y $and$libresoc.v:41728$2152_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + cell $and $and$libresoc.v:41729$2153 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$791 + connect \B \rdflag_CR_cr_a_0 + connect \Y $and$libresoc.v:41729$2153_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + cell $and $and$libresoc.v:41731$2155 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$793 + connect \B \$795 + connect \Y $and$libresoc.v:41731$2155_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + cell $and $and$libresoc.v:41732$2156 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \rdpick_CR_cr_a_o [1] + connect \B \rdpick_CR_cr_a_en_o + connect \Y $and$libresoc.v:41732$2156_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + cell $and $and$libresoc.v:41737$2161 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_rd__rel_o$31 [4] + connect \B \fu_enable [1] + connect \Y $and$libresoc.v:41737$2161_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + cell $and $and$libresoc.v:41738$2162 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$810 + connect \B \rdflag_CR_cr_b_0 + connect \Y $and$libresoc.v:41738$2162_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + cell $and $and$libresoc.v:41740$2164 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$812 + connect \B \$814 + connect \Y $and$libresoc.v:41740$2164_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + cell $and $and$libresoc.v:41741$2165 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \rdpick_CR_cr_b_o + connect \B \rdpick_CR_cr_b_en_o + connect \Y $and$libresoc.v:41741$2165_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + cell $and $and$libresoc.v:41745$2169 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_rd__rel_o$31 [5] + connect \B \fu_enable [1] + connect \Y $and$libresoc.v:41745$2169_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + cell $and $and$libresoc.v:41746$2170 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$826 + connect \B \rdflag_CR_cr_c_0 + connect \Y $and$libresoc.v:41746$2170_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + cell $and $and$libresoc.v:41748$2172 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$828 + connect \B \$830 + connect \Y $and$libresoc.v:41748$2172_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + cell $and $and$libresoc.v:41749$2173 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \rdpick_CR_cr_c_o + connect \B \rdpick_CR_cr_c_en_o + connect \Y $and$libresoc.v:41749$2173_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + cell $and $and$libresoc.v:41753$2177 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_rd__rel_o$72 [0] + connect \B \fu_enable [2] + connect \Y $and$libresoc.v:41753$2177_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + cell $and $and$libresoc.v:41754$2178 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$842 + connect \B \rdflag_FAST_fast1_0 + connect \Y $and$libresoc.v:41754$2178_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + cell $and $and$libresoc.v:41756$2180 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$844 + connect \B \$846 + connect \Y $and$libresoc.v:41756$2180_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + cell $and $and$libresoc.v:41757$2181 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \rdpick_FAST_fast1_o [0] + connect \B \rdpick_FAST_fast1_en_o + connect \Y $and$libresoc.v:41757$2181_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + cell $and $and$libresoc.v:41759$2183 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_rd__rel_o$34 [2] + connect \B \fu_enable [3] + connect \Y $and$libresoc.v:41759$2183_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + cell $and $and$libresoc.v:41760$2184 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$854 + connect \B \rdflag_FAST_fast1_0 + connect \Y $and$libresoc.v:41760$2184_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + cell $and $and$libresoc.v:41762$2186 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$856 + connect \B \$858 + connect \Y $and$libresoc.v:41762$2186_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + cell $and $and$libresoc.v:41763$2187 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \rdpick_FAST_fast1_o [1] + connect \B \rdpick_FAST_fast1_en_o + connect \Y $and$libresoc.v:41763$2187_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + cell $and $and$libresoc.v:41765$2189 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_rd__rel_o$40 [2] + connect \B \fu_enable [5] + connect \Y $and$libresoc.v:41765$2189_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + cell $and $and$libresoc.v:41766$2190 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$866 + connect \B \rdflag_FAST_fast1_0 + connect \Y $and$libresoc.v:41766$2190_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + cell $and $and$libresoc.v:41768$2192 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$868 + connect \B \$870 + connect \Y $and$libresoc.v:41768$2192_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + cell $and $and$libresoc.v:41769$2193 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \rdpick_FAST_fast1_o [2] + connect \B \rdpick_FAST_fast1_en_o + connect \Y $and$libresoc.v:41769$2193_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + cell $and $and$libresoc.v:41774$2198 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_rd__rel_o$72 [1] + connect \B \fu_enable [2] + connect \Y $and$libresoc.v:41774$2198_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + cell $and $and$libresoc.v:41775$2199 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$884 + connect \B \rdflag_FAST_fast2_0 + connect \Y $and$libresoc.v:41775$2199_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + cell $and $and$libresoc.v:41777$2201 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$886 + connect \B \$888 + connect \Y $and$libresoc.v:41777$2201_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + cell $and $and$libresoc.v:41778$2202 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \rdpick_FAST_fast2_o [0] + connect \B \rdpick_FAST_fast2_en_o + connect \Y $and$libresoc.v:41778$2202_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + cell $and $and$libresoc.v:41780$2204 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_rd__rel_o$34 [3] + connect \B \fu_enable [3] + connect \Y $and$libresoc.v:41780$2204_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + cell $and $and$libresoc.v:41781$2205 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$896 + connect \B \rdflag_FAST_fast2_0 + connect \Y $and$libresoc.v:41781$2205_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + cell $and $and$libresoc.v:41783$2207 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$898 + connect \B \$900 + connect \Y $and$libresoc.v:41783$2207_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + cell $and $and$libresoc.v:41784$2208 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \rdpick_FAST_fast2_o [1] + connect \B \rdpick_FAST_fast2_en_o + connect \Y $and$libresoc.v:41784$2208_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + cell $and $and$libresoc.v:41788$2212 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_rd__rel_o$40 [1] + connect \B \fu_enable [5] + connect \Y $and$libresoc.v:41788$2212_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + cell $and $and$libresoc.v:41789$2213 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$912 + connect \B \rdflag_SPR_spr1_0 + connect \Y $and$libresoc.v:41789$2213_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + cell $and $and$libresoc.v:41791$2215 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$914 + connect \B \$916 + connect \Y $and$libresoc.v:41791$2215_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + cell $and $and$libresoc.v:41792$2216 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \rdpick_SPR_spr1_o + connect \B \rdpick_SPR_spr1_en_o + connect \Y $and$libresoc.v:41792$2216_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:400" + cell $and $and$libresoc.v:41795$2219 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_o_ok + connect \B \fus_cu_busy_o + connect \Y $and$libresoc.v:41795$2219_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" + cell $and $and$libresoc.v:41796$2220 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_wr__rel_o [0] + connect \B \fu_enable [0] + connect \Y $and$libresoc.v:41796$2220_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" + cell $and $and$libresoc.v:41797$2221 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_wr__rel_o$84 [0] + connect \B \fu_enable [1] + connect \Y $and$libresoc.v:41797$2221_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" + cell $and $and$libresoc.v:41798$2222 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_wr__rel_o$87 [0] + connect \B \fu_enable [3] + connect \Y $and$libresoc.v:41798$2222_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" + cell $and $and$libresoc.v:41799$2223 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_wr__rel_o$90 [0] + connect \B \fu_enable [4] + connect \Y $and$libresoc.v:41799$2223_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" + cell $and $and$libresoc.v:41800$2224 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_wr__rel_o$93 [0] + connect \B \fu_enable [5] + connect \Y $and$libresoc.v:41800$2224_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" + cell $and $and$libresoc.v:41801$2225 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_wr__rel_o$96 [0] + connect \B \fu_enable [6] + connect \Y $and$libresoc.v:41801$2225_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" + cell $and $and$libresoc.v:41802$2226 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_wr__rel_o$99 [0] + connect \B \fu_enable [7] + connect \Y $and$libresoc.v:41802$2226_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" + cell $and $and$libresoc.v:41803$2227 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_wr__rel_o$102 [0] + connect \B \fu_enable [8] + connect \Y $and$libresoc.v:41803$2227_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" + cell $and $and$libresoc.v:41804$2228 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_wr__rel_o$104 [0] + connect \B \fu_enable [9] + connect \Y $and$libresoc.v:41804$2228_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" + cell $and $and$libresoc.v:41805$2229 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_wr__rel_o$104 [1] + connect \B \fu_enable [9] + connect \Y $and$libresoc.v:41805$2229_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + cell $and $and$libresoc.v:41806$2230 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wrpick_INT_o_o [0] + connect \B \wrpick_INT_o_en_o + connect \Y $and$libresoc.v:41806$2230_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $and$libresoc.v:41808$2232 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick + connect \B \$950 + connect \Y $and$libresoc.v:41808$2232_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" + cell $and $and$libresoc.v:41809$2233 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick + connect \B \wrpick_INT_o_en_o + connect \Y $and$libresoc.v:41809$2233_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:400" + cell $and $and$libresoc.v:41811$2235 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_o_ok$83 + connect \B \fus_cu_busy_o$5 + connect \Y $and$libresoc.v:41811$2235_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + cell $and $and$libresoc.v:41812$2236 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wrpick_INT_o_o [1] + connect \B \wrpick_INT_o_en_o + connect \Y $and$libresoc.v:41812$2236_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $and$libresoc.v:41814$2238 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$964 + connect \B \$969 + connect \Y $and$libresoc.v:41814$2238_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" + cell $and $and$libresoc.v:41815$2239 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$964 + connect \B \wrpick_INT_o_en_o + connect \Y $and$libresoc.v:41815$2239_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:400" + cell $and $and$libresoc.v:41817$2241 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_o_ok$86 + connect \B \fus_cu_busy_o$11 + connect \Y $and$libresoc.v:41817$2241_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + cell $and $and$libresoc.v:41818$2242 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wrpick_INT_o_o [2] + connect \B \wrpick_INT_o_en_o + connect \Y $and$libresoc.v:41818$2242_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $and$libresoc.v:41820$2244 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$983 + connect \B \$988 + connect \Y $and$libresoc.v:41820$2244_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" + cell $and $and$libresoc.v:41821$2245 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$983 + connect \B \wrpick_INT_o_en_o + connect \Y $and$libresoc.v:41821$2245_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" + cell $eq $eq$libresoc.v:41438$1860 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$210 + connect \B 1'1 + connect \Y $eq$libresoc.v:41438$1860_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:86" + cell $eq $eq$libresoc.v:41442$1864 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \core_core_input_carry + connect \B 2'10 + connect \Y $eq$libresoc.v:41442$1864_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" + cell $eq $eq$libresoc.v:41444$1866 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \$222 + connect \B 3'100 + connect \Y $eq$libresoc.v:41444$1866_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" + cell $eq $eq$libresoc.v:41452$1874 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$238 + connect \B 1'1 + connect \Y $eq$libresoc.v:41452$1874_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" + cell $eq $eq$libresoc.v:41459$1881 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$252 + connect \B 1'1 + connect \Y $eq$libresoc.v:41459$1881_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" + cell $eq $eq$libresoc.v:41465$1887 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \$264 + connect \B 2'10 + connect \Y $eq$libresoc.v:41465$1887_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:86" + cell $eq $eq$libresoc.v:41467$1889 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \core_core_input_carry + connect \B 2'10 + connect \Y $eq$libresoc.v:41467$1889_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" + cell $eq $eq$libresoc.v:41469$1891 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \$272 + connect \B 3'100 + connect \Y $eq$libresoc.v:41469$1891_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" + cell $eq $eq$libresoc.v:41474$1896 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$282 + connect \B 1'1 + connect \Y $eq$libresoc.v:41474$1896_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" + cell $eq $eq$libresoc.v:41481$1903 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$296 + connect \B 1'1 + connect \Y $eq$libresoc.v:41481$1903_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" + cell $eq $eq$libresoc.v:41488$1910 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$310 + connect \B 1'1 + connect \Y $eq$libresoc.v:41488$1910_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:86" + cell $eq $eq$libresoc.v:41492$1914 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \core_core_input_carry + connect \B 2'10 + connect \Y $eq$libresoc.v:41492$1914_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" + cell $eq $eq$libresoc.v:41494$1916 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \$322 + connect \B 3'100 + connect \Y $eq$libresoc.v:41494$1916_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" + cell $eq $eq$libresoc.v:41633$2055 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$599 + connect \B 1'1 + connect \Y $eq$libresoc.v:41633$2055_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:86" + cell $eq $eq$libresoc.v:41679$2102 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \core_core_input_carry + connect \B 2'10 + connect \Y $eq$libresoc.v:41679$2102_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" + cell $eq $eq$libresoc.v:41681$2104 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \$695 + connect \B 3'100 + connect \Y $eq$libresoc.v:41681$2104_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" + cell $eq $eq$libresoc.v:41706$2130 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \$745 + connect \B 2'10 + connect \Y $eq$libresoc.v:41706$2130_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $pos $extend$libresoc.v:41263$1680 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 3 + connect \A \$1422 + connect \Y $extend$libresoc.v:41263$1680_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $pos $extend$libresoc.v:41329$1747 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 2 + connect \A \$1586 + connect \Y $extend$libresoc.v:41329$1747_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $pos $extend$libresoc.v:41333$1752 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \$1594 + connect \Y $extend$libresoc.v:41333$1752_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $pos $extend$libresoc.v:41405$1825 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \$1753 + connect \Y $extend$libresoc.v:41405$1825_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + cell $pos $extend$libresoc.v:41413$1834 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 4 + connect \A \addr_en$1771 + connect \Y $extend$libresoc.v:41413$1834_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $pos $extend$libresoc.v:41678$2100 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \$690 + connect \Y $extend$libresoc.v:41678$2100_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $pos $extend$libresoc.v:41703$2126 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 3 + connect \A \$740 + connect \Y $extend$libresoc.v:41703$2126_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:186" + cell $ne $ne$libresoc.v:41433$1855 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \counter + connect \B 1'0 + connect \Y $ne$libresoc.v:41433$1855_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:186" + cell $ne $ne$libresoc.v:41435$1857 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \counter + connect \B 1'0 + connect \Y $ne$libresoc.v:41435$1857_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $not$libresoc.v:41100$1517 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick_dly$1007 + connect \Y $not$libresoc.v:41100$1517_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $not$libresoc.v:41106$1523 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick_dly$1025 + connect \Y $not$libresoc.v:41106$1523_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $not$libresoc.v:41112$1529 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick_dly$1047 + connect \Y $not$libresoc.v:41112$1529_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $not$libresoc.v:41118$1535 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick_dly$1067 + connect \Y $not$libresoc.v:41118$1535_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $not$libresoc.v:41124$1541 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick_dly$1087 + connect \Y $not$libresoc.v:41124$1541_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $not$libresoc.v:41130$1547 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick_dly$1106 + connect \Y $not$libresoc.v:41130$1547_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $not$libresoc.v:41136$1553 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick_dly$1124 + connect \Y $not$libresoc.v:41136$1553_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $not$libresoc.v:41170$1587 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick_dly$1197 + connect \Y $not$libresoc.v:41170$1587_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $not$libresoc.v:41182$1599 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick_dly$1225 + connect \Y $not$libresoc.v:41182$1599_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $not$libresoc.v:41190$1607 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick_dly$1245 + connect \Y $not$libresoc.v:41190$1607_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $not$libresoc.v:41198$1615 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick_dly$1265 + connect \Y $not$libresoc.v:41198$1615_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $not$libresoc.v:41206$1623 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick_dly$1285 + connect \Y $not$libresoc.v:41206$1623_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $not$libresoc.v:41214$1631 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick_dly$1305 + connect \Y $not$libresoc.v:41214$1631_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $not$libresoc.v:41222$1639 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick_dly$1325 + connect \Y $not$libresoc.v:41222$1639_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $not$libresoc.v:41243$1660 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick_dly$1372 + connect \Y $not$libresoc.v:41243$1660_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $not$libresoc.v:41249$1666 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick_dly$1388 + connect \Y $not$libresoc.v:41249$1666_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $not$libresoc.v:41255$1672 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick_dly$1404 + connect \Y $not$libresoc.v:41255$1672_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $not$libresoc.v:41270$1688 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick_dly$1438 + connect \Y $not$libresoc.v:41270$1688_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $not$libresoc.v:41276$1694 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick_dly$1454 + connect \Y $not$libresoc.v:41276$1694_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $not$libresoc.v:41282$1700 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick_dly$1470 + connect \Y $not$libresoc.v:41282$1700_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $not$libresoc.v:41288$1706 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick_dly$1486 + connect \Y $not$libresoc.v:41288$1706_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $not$libresoc.v:41304$1722 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick_dly$1522 + connect \Y $not$libresoc.v:41304$1722_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $not$libresoc.v:41310$1728 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick_dly$1538 + connect \Y $not$libresoc.v:41310$1728_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $not$libresoc.v:41316$1734 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick_dly$1554 + connect \Y $not$libresoc.v:41316$1734_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $not$libresoc.v:41322$1740 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick_dly$1570 + connect \Y $not$libresoc.v:41322$1740_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $not$libresoc.v:41341$1761 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick_dly$1612 + connect \Y $not$libresoc.v:41341$1761_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $not$libresoc.v:41349$1769 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick_dly$1631 + connect \Y $not$libresoc.v:41349$1769_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $not$libresoc.v:41355$1775 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick_dly$1647 + connect \Y $not$libresoc.v:41355$1775_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $not$libresoc.v:41362$1782 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick_dly$1663 + connect \Y $not$libresoc.v:41362$1782_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $not$libresoc.v:41369$1789 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick_dly$1679 + connect \Y $not$libresoc.v:41369$1789_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $not$libresoc.v:41391$1811 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick_dly$1723 + connect \Y $not$libresoc.v:41391$1811_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $not$libresoc.v:41398$1818 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick_dly$1739 + connect \Y $not$libresoc.v:41398$1818_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $not$libresoc.v:41409$1830 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick_dly$1763 + connect \Y $not$libresoc.v:41409$1830_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $not$libresoc.v:41418$1840 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick_dly$1783 + connect \Y $not$libresoc.v:41418$1840_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:217" + cell $not $not$libresoc.v:41446$1868 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A { \$226 \$218 \core_reg2_ok \core_reg1_ok } + connect \Y $not$libresoc.v:41446$1868_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:217" + cell $not $not$libresoc.v:41447$1869 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A { \core_cr_in2_ok$2 \core_cr_in2_ok \core_cr_in1_ok \core_core_cr_rd_ok \core_reg2_ok \core_reg1_ok } + connect \Y $not$libresoc.v:41447$1869_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:217" + cell $not $not$libresoc.v:41448$1870 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { \core_cr_in1_ok \core_fast2_ok \core_fast1_ok } + connect \Y $not$libresoc.v:41448$1870_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:217" + cell $not $not$libresoc.v:41449$1871 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A { \core_fast2_ok \core_fast1_ok \core_reg2_ok \core_reg1_ok } + connect \Y $not$libresoc.v:41449$1871_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:217" + cell $not $not$libresoc.v:41456$1878 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { \$246 \core_reg2_ok \core_reg1_ok } + connect \Y $not$libresoc.v:41456$1878_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:217" + cell $not $not$libresoc.v:41471$1893 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A { \$276 \$268 \$260 \core_fast1_ok \core_spr1_ok \core_reg1_ok } + connect \Y $not$libresoc.v:41471$1893_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:217" + cell $not $not$libresoc.v:41478$1900 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { \$290 \core_reg2_ok \core_reg1_ok } + connect \Y $not$libresoc.v:41478$1900_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:217" + cell $not $not$libresoc.v:41485$1907 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { \$304 \core_reg2_ok \core_reg1_ok } + connect \Y $not$libresoc.v:41485$1907_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:217" + cell $not $not$libresoc.v:41496$1918 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A { \$326 \$318 \core_reg3_ok \core_reg2_ok \core_reg1_ok } + connect \Y $not$libresoc.v:41496$1918_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:217" + cell $not $not$libresoc.v:41497$1919 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { \core_reg3_ok \core_reg2_ok \core_reg1_ok } + connect \Y $not$libresoc.v:41497$1919_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + cell $not $not$libresoc.v:41500$1922 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dp_INT_ra_alu0_0 + connect \Y $not$libresoc.v:41500$1922_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + cell $not $not$libresoc.v:41506$1928 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dp_INT_ra_cr0_1 + connect \Y $not$libresoc.v:41506$1928_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + cell $not $not$libresoc.v:41512$1934 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dp_INT_ra_trap0_2 + connect \Y $not$libresoc.v:41512$1934_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + cell $not $not$libresoc.v:41518$1940 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dp_INT_ra_logical0_3 + connect \Y $not$libresoc.v:41518$1940_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + cell $not $not$libresoc.v:41524$1946 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dp_INT_ra_spr0_4 + connect \Y $not$libresoc.v:41524$1946_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + cell $not $not$libresoc.v:41530$1952 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dp_INT_ra_div0_5 + connect \Y $not$libresoc.v:41530$1952_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + cell $not $not$libresoc.v:41536$1958 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dp_INT_ra_mul0_6 + connect \Y $not$libresoc.v:41536$1958_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + cell $not $not$libresoc.v:41542$1964 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dp_INT_ra_shiftrot0_7 + connect \Y $not$libresoc.v:41542$1964_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + cell $not $not$libresoc.v:41548$1970 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dp_INT_ra_ldst0_8 + connect \Y $not$libresoc.v:41548$1970_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + cell $not $not$libresoc.v:41563$1985 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dp_INT_rb_alu0_0 + connect \Y $not$libresoc.v:41563$1985_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + cell $not $not$libresoc.v:41569$1991 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dp_INT_rb_cr0_1 + connect \Y $not$libresoc.v:41569$1991_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + cell $not $not$libresoc.v:41575$1997 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dp_INT_rb_trap0_2 + connect \Y $not$libresoc.v:41575$1997_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + cell $not $not$libresoc.v:41581$2003 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dp_INT_rb_logical0_3 + connect \Y $not$libresoc.v:41581$2003_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + cell $not $not$libresoc.v:41587$2009 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dp_INT_rb_div0_4 + connect \Y $not$libresoc.v:41587$2009_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + cell $not $not$libresoc.v:41593$2015 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dp_INT_rb_mul0_5 + connect \Y $not$libresoc.v:41593$2015_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + cell $not $not$libresoc.v:41599$2021 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dp_INT_rb_shiftrot0_6 + connect \Y $not$libresoc.v:41599$2021_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + cell $not $not$libresoc.v:41605$2027 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dp_INT_rb_ldst0_7 + connect \Y $not$libresoc.v:41605$2027_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + cell $not $not$libresoc.v:41619$2041 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dp_INT_rc_shiftrot0_0 + connect \Y $not$libresoc.v:41619$2041_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + cell $not $not$libresoc.v:41625$2047 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dp_INT_rc_ldst0_1 + connect \Y $not$libresoc.v:41625$2047_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + cell $not $not$libresoc.v:41639$2061 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dp_XER_xer_so_alu0_0 + connect \Y $not$libresoc.v:41639$2061_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + cell $not $not$libresoc.v:41645$2067 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dp_XER_xer_so_logical0_1 + connect \Y $not$libresoc.v:41645$2067_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + cell $not $not$libresoc.v:41651$2073 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dp_XER_xer_so_spr0_2 + connect \Y $not$libresoc.v:41651$2073_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + cell $not $not$libresoc.v:41657$2079 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dp_XER_xer_so_div0_3 + connect \Y $not$libresoc.v:41657$2079_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + cell $not $not$libresoc.v:41663$2085 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dp_XER_xer_so_mul0_4 + connect \Y $not$libresoc.v:41663$2085_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + cell $not $not$libresoc.v:41669$2091 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dp_XER_xer_so_shiftrot0_5 + connect \Y $not$libresoc.v:41669$2091_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + cell $not $not$libresoc.v:41685$2108 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dp_XER_xer_ca_alu0_0 + connect \Y $not$libresoc.v:41685$2108_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + cell $not $not$libresoc.v:41691$2114 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dp_XER_xer_ca_spr0_1 + connect \Y $not$libresoc.v:41691$2114_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + cell $not $not$libresoc.v:41697$2120 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dp_XER_xer_ca_shiftrot0_2 + connect \Y $not$libresoc.v:41697$2120_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + cell $not $not$libresoc.v:41710$2134 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dp_XER_xer_ov_spr0_0 + connect \Y $not$libresoc.v:41710$2134_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + cell $not $not$libresoc.v:41716$2140 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dp_CR_full_cr_cr0_0 + connect \Y $not$libresoc.v:41716$2140_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + cell $not $not$libresoc.v:41722$2146 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dp_CR_cr_a_cr0_0 + connect \Y $not$libresoc.v:41722$2146_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + cell $not $not$libresoc.v:41730$2154 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dp_CR_cr_a_branch0_1 + connect \Y $not$libresoc.v:41730$2154_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + cell $not $not$libresoc.v:41739$2163 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dp_CR_cr_b_cr0_0 + connect \Y $not$libresoc.v:41739$2163_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + cell $not $not$libresoc.v:41747$2171 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dp_CR_cr_c_cr0_0 + connect \Y $not$libresoc.v:41747$2171_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + cell $not $not$libresoc.v:41755$2179 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dp_FAST_fast1_branch0_0 + connect \Y $not$libresoc.v:41755$2179_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + cell $not $not$libresoc.v:41761$2185 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dp_FAST_fast1_trap0_1 + connect \Y $not$libresoc.v:41761$2185_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + cell $not $not$libresoc.v:41767$2191 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dp_FAST_fast1_spr0_2 + connect \Y $not$libresoc.v:41767$2191_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + cell $not $not$libresoc.v:41776$2200 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dp_FAST_fast2_branch0_0 + connect \Y $not$libresoc.v:41776$2200_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + cell $not $not$libresoc.v:41782$2206 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dp_FAST_fast2_trap0_1 + connect \Y $not$libresoc.v:41782$2206_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + cell $not $not$libresoc.v:41790$2214 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dp_SPR_spr1_spr0_0 + connect \Y $not$libresoc.v:41790$2214_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $not$libresoc.v:41807$2231 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick_dly + connect \Y $not$libresoc.v:41807$2231_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $not$libresoc.v:41813$2237 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick_dly$967 + connect \Y $not$libresoc.v:41813$2237_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $not$libresoc.v:41819$2243 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick_dly$986 + connect \Y $not$libresoc.v:41819$2243_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $or$libresoc.v:41140$1557 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \fus_dest1_o + connect \B \fus_dest1_o$106 + connect \Y $or$libresoc.v:41140$1557_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $or$libresoc.v:41141$1558 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \fus_dest1_o$108 + connect \B \fus_dest1_o$109 + connect \Y $or$libresoc.v:41141$1558_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $or$libresoc.v:41142$1559 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \fus_dest1_o$107 + connect \B \$1138 + connect \Y $or$libresoc.v:41142$1559_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $or$libresoc.v:41143$1560 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \$1136 + connect \B \$1140 + connect \Y $or$libresoc.v:41143$1560_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $or$libresoc.v:41144$1561 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \fus_dest1_o$110 + connect \B \fus_dest1_o$111 + connect \Y $or$libresoc.v:41144$1561_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $or$libresoc.v:41145$1562 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \B_SIGNED 0 + parameter \B_WIDTH 65 + parameter \Y_WIDTH 65 + connect \A { \o_ok \fus_o } + connect \B { \ea_ok \fus_ea } + connect \Y $or$libresoc.v:41145$1562_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $or$libresoc.v:41146$1563 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 65 + parameter \Y_WIDTH 65 + connect \A \fus_dest1_o$112 + connect \B \$1146 + connect \Y $or$libresoc.v:41146$1563_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $or$libresoc.v:41147$1564 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 65 + parameter \Y_WIDTH 65 + connect \A \$1144 + connect \B \$1148 + connect \Y $or$libresoc.v:41147$1564_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $or$libresoc.v:41148$1565 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 65 + parameter \Y_WIDTH 65 + connect \A \$1142 + connect \B \$1150 + connect \Y $or$libresoc.v:41148$1565_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $or$libresoc.v:41149$1566 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \addr_en + connect \B \addr_en$978 + connect \Y $or$libresoc.v:41149$1566_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $or$libresoc.v:41150$1567 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \addr_en$1017 + connect \B \addr_en$1039 + connect \Y $or$libresoc.v:41150$1567_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $or$libresoc.v:41151$1568 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \addr_en$999 + connect \B \$1156 + connect \Y $or$libresoc.v:41151$1568_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $or$libresoc.v:41152$1569 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \$1154 + connect \B \$1158 + connect \Y $or$libresoc.v:41152$1569_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $or$libresoc.v:41153$1570 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \addr_en$1059 + connect \B \addr_en$1079 + connect \Y $or$libresoc.v:41153$1570_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $or$libresoc.v:41154$1571 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \addr_en$1116 + connect \B \addr_en$1132 + connect \Y $or$libresoc.v:41154$1571_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $or$libresoc.v:41155$1572 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \addr_en$1098 + connect \B \$1164 + connect \Y $or$libresoc.v:41155$1572_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $or$libresoc.v:41156$1573 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \$1162 + connect \B \$1166 + connect \Y $or$libresoc.v:41156$1573_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $or$libresoc.v:41157$1574 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \$1160 + connect \B \$1168 + connect \Y $or$libresoc.v:41157$1574_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $or$libresoc.v:41158$1575 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wp + connect \B \wp$975 + connect \Y $or$libresoc.v:41158$1575_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $or$libresoc.v:41159$1576 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wp$1014 + connect \B \wp$1036 + connect \Y $or$libresoc.v:41159$1576_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $or$libresoc.v:41160$1577 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wp$996 + connect \B \$1174 + connect \Y $or$libresoc.v:41160$1577_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $or$libresoc.v:41161$1578 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$1172 + connect \B \$1176 + connect \Y $or$libresoc.v:41161$1578_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $or$libresoc.v:41162$1579 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wp$1056 + connect \B \wp$1076 + connect \Y $or$libresoc.v:41162$1579_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $or$libresoc.v:41163$1580 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wp$1113 + connect \B \wp$1129 + connect \Y $or$libresoc.v:41163$1580_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $or$libresoc.v:41164$1581 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wp$1095 + connect \B \$1182 + connect \Y $or$libresoc.v:41164$1581_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $or$libresoc.v:41165$1582 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$1180 + connect \B \$1184 + connect \Y $or$libresoc.v:41165$1582_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $or$libresoc.v:41166$1583 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$1178 + connect \B \$1186 + connect \Y $or$libresoc.v:41166$1583_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $or$libresoc.v:41228$1645 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \fus_dest3_o + connect \B \fus_dest2_o$119 + connect \Y $or$libresoc.v:41228$1645_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $or$libresoc.v:41229$1646 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \fus_dest2_o$118 + connect \B \$1340 + connect \Y $or$libresoc.v:41229$1646_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $or$libresoc.v:41230$1647 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \fus_dest2_o$121 + connect \B \fus_dest2_o$122 + connect \Y $or$libresoc.v:41230$1647_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $or$libresoc.v:41231$1648 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \fus_dest2_o$120 + connect \B \$1344 + connect \Y $or$libresoc.v:41231$1648_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $or$libresoc.v:41232$1649 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \$1342 + connect \B \$1346 + connect \Y $or$libresoc.v:41232$1649_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $or$libresoc.v:41233$1650 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 16 + parameter \Y_WIDTH 16 + connect \A \addr_en$1253 + connect \B \addr_en$1273 + connect \Y $or$libresoc.v:41233$1650_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $or$libresoc.v:41234$1651 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 16 + parameter \Y_WIDTH 16 + connect \A \addr_en$1233 + connect \B \$1351 + connect \Y $or$libresoc.v:41234$1651_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $or$libresoc.v:41235$1652 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 16 + parameter \Y_WIDTH 16 + connect \A \addr_en$1313 + connect \B \addr_en$1333 + connect \Y $or$libresoc.v:41235$1652_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $or$libresoc.v:41236$1653 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 16 + parameter \Y_WIDTH 16 + connect \A \addr_en$1293 + connect \B \$1355 + connect \Y $or$libresoc.v:41236$1653_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $or$libresoc.v:41237$1654 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 16 + parameter \Y_WIDTH 16 + connect \A \$1353 + connect \B \$1357 + connect \Y $or$libresoc.v:41237$1654_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $or$libresoc.v:41259$1676 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \fus_dest6_o + connect \B \fus_dest3_o$126 + connect \Y $or$libresoc.v:41259$1676_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $or$libresoc.v:41260$1677 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \fus_dest3_o$125 + connect \B \$1415 + connect \Y $or$libresoc.v:41260$1677_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $or$libresoc.v:41261$1678 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \addr_en$1396 + connect \B \addr_en$1412 + connect \Y $or$libresoc.v:41261$1678_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $or$libresoc.v:41262$1679 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \addr_en$1380 + connect \B \$1420 + connect \Y $or$libresoc.v:41262$1679_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $or$libresoc.v:41292$1710 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \fus_dest4_o + connect \B \fus_dest5_o + connect \Y $or$libresoc.v:41292$1710_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $or$libresoc.v:41293$1711 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \fus_dest3_o$130 + connect \B \fus_dest3_o$131 + connect \Y $or$libresoc.v:41293$1711_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $or$libresoc.v:41294$1712 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \$1497 + connect \B \$1499 + connect \Y $or$libresoc.v:41294$1712_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $or$libresoc.v:41295$1713 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \addr_en$1446 + connect \B \addr_en$1462 + connect \Y $or$libresoc.v:41295$1713_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $or$libresoc.v:41296$1714 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \addr_en$1478 + connect \B \addr_en$1494 + connect \Y $or$libresoc.v:41296$1714_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $or$libresoc.v:41297$1715 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \$1503 + connect \B \$1505 + connect \Y $or$libresoc.v:41297$1715_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $or$libresoc.v:41326$1744 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_dest5_o$135 + connect \B \fus_dest4_o$136 + connect \Y $or$libresoc.v:41326$1744_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $or$libresoc.v:41327$1745 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_dest4_o$137 + connect \B \fus_dest4_o$138 + connect \Y $or$libresoc.v:41327$1745_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $or$libresoc.v:41328$1746 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$1582 + connect \B \$1584 + connect \Y $or$libresoc.v:41328$1746_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $or$libresoc.v:41330$1749 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \addr_en$1530 + connect \B \addr_en$1546 + connect \Y $or$libresoc.v:41330$1749_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $or$libresoc.v:41331$1750 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \addr_en$1562 + connect \B \addr_en$1578 + connect \Y $or$libresoc.v:41331$1750_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $or$libresoc.v:41332$1751 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$1590 + connect \B \$1592 + connect \Y $or$libresoc.v:41332$1751_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $or$libresoc.v:41373$1793 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \fus_dest1_o$144 + connect \B \fus_dest2_o$145 + connect \Y $or$libresoc.v:41373$1793_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $or$libresoc.v:41374$1794 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \fus_dest2_o$147 + connect \B \fus_dest3_o$148 + connect \Y $or$libresoc.v:41374$1794_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $or$libresoc.v:41375$1795 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \fus_dest3_o$146 + connect \B \$1692 + connect \Y $or$libresoc.v:41375$1795_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $or$libresoc.v:41376$1796 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \$1690 + connect \B \$1694 + connect \Y $or$libresoc.v:41376$1796_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $or$libresoc.v:41377$1797 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \addr_en$1623 + connect \B \addr_en$1639 + connect \Y $or$libresoc.v:41377$1797_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $or$libresoc.v:41379$1799 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \addr_en$1671 + connect \B \addr_en$1687 + connect \Y $or$libresoc.v:41379$1799_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $or$libresoc.v:41380$1800 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \addr_en$1655 + connect \B \$1700 + connect \Y $or$libresoc.v:41380$1800_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $or$libresoc.v:41381$1801 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \$1698 + connect \B \$1702 + connect \Y $or$libresoc.v:41381$1801_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $or$libresoc.v:41382$1802 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wp$1620 + connect \B \wp$1636 + connect \Y $or$libresoc.v:41382$1802_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $or$libresoc.v:41383$1803 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wp$1668 + connect \B \wp$1684 + connect \Y $or$libresoc.v:41383$1803_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $or$libresoc.v:41385$1805 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wp$1652 + connect \B \$1708 + connect \Y $or$libresoc.v:41385$1805_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $or$libresoc.v:41386$1806 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$1706 + connect \B \$1710 + connect \Y $or$libresoc.v:41386$1806_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $or$libresoc.v:41403$1823 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \fus_dest3_o$150 + connect \B \fus_dest4_o$151 + connect \Y $or$libresoc.v:41403$1823_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $or$libresoc.v:41404$1824 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \addr_en$1731 + connect \B \addr_en$1747 + connect \Y $or$libresoc.v:41404$1824_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" + cell $or $or$libresoc.v:41439$1861 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$208 + connect \B \$212 + connect \Y $or$libresoc.v:41439$1861_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" + cell $or $or$libresoc.v:41441$1863 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$214 + connect \B \$216 + connect \Y $or$libresoc.v:41441$1863_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" + cell $or $or$libresoc.v:41445$1867 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$220 + connect \B \$224 + connect \Y $or$libresoc.v:41445$1867_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" + cell $or $or$libresoc.v:41453$1875 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$236 + connect \B \$240 + connect \Y $or$libresoc.v:41453$1875_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" + cell $or $or$libresoc.v:41455$1877 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$242 + connect \B \$244 + connect \Y $or$libresoc.v:41455$1877_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" + cell $or $or$libresoc.v:41460$1882 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$250 + connect \B \$254 + connect \Y $or$libresoc.v:41460$1882_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" + cell $or $or$libresoc.v:41462$1884 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$256 + connect \B \$258 + connect \Y $or$libresoc.v:41462$1884_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" + cell $or $or$libresoc.v:41466$1888 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$262 + connect \B \$266 + connect \Y $or$libresoc.v:41466$1888_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" + cell $or $or$libresoc.v:41470$1892 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$270 + connect \B \$274 + connect \Y $or$libresoc.v:41470$1892_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" + cell $or $or$libresoc.v:41475$1897 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$280 + connect \B \$284 + connect \Y $or$libresoc.v:41475$1897_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" + cell $or $or$libresoc.v:41477$1899 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$286 + connect \B \$288 + connect \Y $or$libresoc.v:41477$1899_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" + cell $or $or$libresoc.v:41482$1904 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$294 + connect \B \$298 + connect \Y $or$libresoc.v:41482$1904_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" + cell $or $or$libresoc.v:41484$1906 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$300 + connect \B \$302 + connect \Y $or$libresoc.v:41484$1906_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" + cell $or $or$libresoc.v:41489$1911 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$308 + connect \B \$312 + connect \Y $or$libresoc.v:41489$1911_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" + cell $or $or$libresoc.v:41491$1913 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$314 + connect \B \$316 + connect \Y $or$libresoc.v:41491$1913_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" + cell $or $or$libresoc.v:41495$1917 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$320 + connect \B \$324 + connect \Y $or$libresoc.v:41495$1917_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $or$libresoc.v:41552$1974 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \addr_en_INT_ra_alu0_0 + connect \B \addr_en_INT_ra_cr0_1 + connect \Y $or$libresoc.v:41552$1974_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $or$libresoc.v:41553$1975 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \addr_en_INT_ra_trap0_2 + connect \B \addr_en_INT_ra_logical0_3 + connect \Y $or$libresoc.v:41553$1975_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $or$libresoc.v:41554$1976 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \$439 + connect \B \$441 + connect \Y $or$libresoc.v:41554$1976_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $or$libresoc.v:41555$1977 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \addr_en_INT_ra_spr0_4 + connect \B \addr_en_INT_ra_div0_5 + connect \Y $or$libresoc.v:41555$1977_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $or$libresoc.v:41556$1978 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \addr_en_INT_ra_shiftrot0_7 + connect \B \addr_en_INT_ra_ldst0_8 + connect \Y $or$libresoc.v:41556$1978_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $or$libresoc.v:41557$1979 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \addr_en_INT_ra_mul0_6 + connect \B \$447 + connect \Y $or$libresoc.v:41557$1979_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $or$libresoc.v:41558$1980 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \$445 + connect \B \$449 + connect \Y $or$libresoc.v:41558$1980_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $or$libresoc.v:41559$1981 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \$443 + connect \B \$451 + connect \Y $or$libresoc.v:41559$1981_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $or$libresoc.v:41609$2031 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \addr_en_INT_rb_alu0_0 + connect \B \addr_en_INT_rb_cr0_1 + connect \Y $or$libresoc.v:41609$2031_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $or$libresoc.v:41610$2032 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \addr_en_INT_rb_trap0_2 + connect \B \addr_en_INT_rb_logical0_3 + connect \Y $or$libresoc.v:41610$2032_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $or$libresoc.v:41611$2033 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \$553 + connect \B \$555 + connect \Y $or$libresoc.v:41611$2033_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $or$libresoc.v:41612$2034 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \addr_en_INT_rb_div0_4 + connect \B \addr_en_INT_rb_mul0_5 + connect \Y $or$libresoc.v:41612$2034_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $or$libresoc.v:41613$2035 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \addr_en_INT_rb_shiftrot0_6 + connect \B \addr_en_INT_rb_ldst0_7 + connect \Y $or$libresoc.v:41613$2035_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $or$libresoc.v:41614$2036 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \$559 + connect \B \$561 + connect \Y $or$libresoc.v:41614$2036_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $or$libresoc.v:41615$2037 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \$557 + connect \B \$563 + connect \Y $or$libresoc.v:41615$2037_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $or$libresoc.v:41629$2051 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \addr_en_INT_rc_shiftrot0_0 + connect \B \addr_en_INT_rc_ldst0_1 + connect \Y $or$libresoc.v:41629$2051_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" + cell $or $or$libresoc.v:41634$2056 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$597 + connect \B \$601 + connect \Y $or$libresoc.v:41634$2056_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" + cell $or $or$libresoc.v:41636$2058 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$603 + connect \B \$605 + connect \Y $or$libresoc.v:41636$2058_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $or$libresoc.v:41673$2095 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \addr_en_XER_xer_so_logical0_1 + connect \B \addr_en_XER_xer_so_spr0_2 + connect \Y $or$libresoc.v:41673$2095_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $or$libresoc.v:41674$2096 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \addr_en_XER_xer_so_alu0_0 + connect \B \$682 + connect \Y $or$libresoc.v:41674$2096_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $or$libresoc.v:41675$2097 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \addr_en_XER_xer_so_mul0_4 + connect \B \addr_en_XER_xer_so_shiftrot0_5 + connect \Y $or$libresoc.v:41675$2097_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $or$libresoc.v:41676$2098 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \addr_en_XER_xer_so_div0_3 + connect \B \$686 + connect \Y $or$libresoc.v:41676$2098_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $or$libresoc.v:41677$2099 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$684 + connect \B \$688 + connect \Y $or$libresoc.v:41677$2099_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" + cell $or $or$libresoc.v:41682$2105 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$693 + connect \B \$697 + connect \Y $or$libresoc.v:41682$2105_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $or$libresoc.v:41701$2124 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \addr_en_XER_xer_ca_spr0_1 + connect \B \addr_en_XER_xer_ca_shiftrot0_2 + connect \Y $or$libresoc.v:41701$2124_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $or$libresoc.v:41702$2125 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \addr_en_XER_xer_ca_alu0_0 + connect \B \$738 + connect \Y $or$libresoc.v:41702$2125_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" + cell $or $or$libresoc.v:41707$2131 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$743 + connect \B \$747 + connect \Y $or$libresoc.v:41707$2131_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $or$libresoc.v:41736$2160 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 16 + parameter \Y_WIDTH 16 + connect \A \addr_en_CR_cr_a_cr0_0 + connect \B \addr_en_CR_cr_a_branch0_1 + connect \Y $or$libresoc.v:41736$2160_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $or$libresoc.v:41771$2195 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \addr_en_FAST_fast1_trap0_1 + connect \B \addr_en_FAST_fast1_spr0_2 + connect \Y $or$libresoc.v:41771$2195_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $or$libresoc.v:41772$2196 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \addr_en_FAST_fast1_branch0_0 + connect \B \$878 + connect \Y $or$libresoc.v:41772$2196_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $or$libresoc.v:41786$2210 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \addr_en_FAST_fast2_branch0_0 + connect \B \addr_en_FAST_fast2_trap0_1 + connect \Y $or$libresoc.v:41786$2210_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $pos $pos$libresoc.v:41263$1681 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A $extend$libresoc.v:41263$1680_Y + connect \Y $pos$libresoc.v:41263$1681_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $pos $pos$libresoc.v:41329$1748 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A $extend$libresoc.v:41329$1747_Y + connect \Y $pos$libresoc.v:41329$1748_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $pos $pos$libresoc.v:41333$1753 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A $extend$libresoc.v:41333$1752_Y + connect \Y $pos$libresoc.v:41333$1753_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $pos $pos$libresoc.v:41405$1826 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A $extend$libresoc.v:41405$1825_Y + connect \Y $pos$libresoc.v:41405$1826_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + cell $pos $pos$libresoc.v:41413$1835 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A $extend$libresoc.v:41413$1834_Y + connect \Y $pos$libresoc.v:41413$1835_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $pos $pos$libresoc.v:41678$2101 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A $extend$libresoc.v:41678$2100_Y + connect \Y $pos$libresoc.v:41678$2101_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $pos $pos$libresoc.v:41703$2127 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A $extend$libresoc.v:41703$2126_Y + connect \Y $pos$libresoc.v:41703$2127_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + cell $reduce_or $reduce_or$libresoc.v:41347$1767 + parameter \A_SIGNED 0 + parameter \A_WIDTH 12 + parameter \Y_WIDTH 1 + connect \A \$161 + connect \Y $reduce_or$libresoc.v:41347$1767_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + cell $reduce_or $reduce_or$libresoc.v:41364$1784 + parameter \A_SIGNED 0 + parameter \A_WIDTH 12 + parameter \Y_WIDTH 1 + connect \A \$165 + connect \Y $reduce_or$libresoc.v:41364$1784_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + cell $reduce_or $reduce_or$libresoc.v:41384$1804 + parameter \A_SIGNED 0 + parameter \A_WIDTH 12 + parameter \Y_WIDTH 1 + connect \A \$169 + connect \Y $reduce_or$libresoc.v:41384$1804_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + cell $reduce_or $reduce_or$libresoc.v:41402$1822 + parameter \A_SIGNED 0 + parameter \A_WIDTH 12 + parameter \Y_WIDTH 1 + connect \A \$173 + connect \Y $reduce_or$libresoc.v:41402$1822_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + cell $reduce_or $reduce_or$libresoc.v:41420$1842 + parameter \A_SIGNED 0 + parameter \A_WIDTH 12 + parameter \Y_WIDTH 1 + connect \A \$177 + connect \Y $reduce_or$libresoc.v:41420$1842_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + cell $reduce_or $reduce_or$libresoc.v:41424$1846 + parameter \A_SIGNED 0 + parameter \A_WIDTH 12 + parameter \Y_WIDTH 1 + connect \A \$181 + connect \Y $reduce_or$libresoc.v:41424$1846_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + cell $reduce_or $reduce_or$libresoc.v:41426$1848 + parameter \A_SIGNED 0 + parameter \A_WIDTH 12 + parameter \Y_WIDTH 1 + connect \A \$185 + connect \Y $reduce_or$libresoc.v:41426$1848_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + cell $reduce_or $reduce_or$libresoc.v:41428$1850 + parameter \A_SIGNED 0 + parameter \A_WIDTH 12 + parameter \Y_WIDTH 1 + connect \A \$189 + connect \Y $reduce_or$libresoc.v:41428$1850_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + cell $reduce_or $reduce_or$libresoc.v:41430$1852 + parameter \A_SIGNED 0 + parameter \A_WIDTH 12 + parameter \Y_WIDTH 1 + connect \A \$193 + connect \Y $reduce_or$libresoc.v:41430$1852_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + cell $reduce_or $reduce_or$libresoc.v:41432$1854 + parameter \A_SIGNED 0 + parameter \A_WIDTH 12 + parameter \Y_WIDTH 1 + connect \A \$197 + connect \Y $reduce_or$libresoc.v:41432$1854_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:313" + cell $reduce_or $reduce_or$libresoc.v:41560$1982 + parameter \A_SIGNED 0 + parameter \A_WIDTH 9 + parameter \Y_WIDTH 1 + connect \A { \rp_INT_ra_ldst0_8 \rp_INT_ra_shiftrot0_7 \rp_INT_ra_mul0_6 \rp_INT_ra_div0_5 \rp_INT_ra_spr0_4 \rp_INT_ra_logical0_3 \rp_INT_ra_trap0_2 \rp_INT_ra_cr0_1 \rp_INT_ra_alu0_0 } + connect \Y $reduce_or$libresoc.v:41560$1982_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:313" + cell $reduce_or $reduce_or$libresoc.v:41616$2038 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A { \rp_INT_rb_ldst0_7 \rp_INT_rb_shiftrot0_6 \rp_INT_rb_mul0_5 \rp_INT_rb_div0_4 \rp_INT_rb_logical0_3 \rp_INT_rb_trap0_2 \rp_INT_rb_cr0_1 \rp_INT_rb_alu0_0 } + connect \Y $reduce_or$libresoc.v:41616$2038_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:313" + cell $reduce_or $reduce_or$libresoc.v:41630$2052 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \rp_INT_rc_ldst0_1 \rp_INT_rc_shiftrot0_0 } + connect \Y $reduce_or$libresoc.v:41630$2052_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:313" + cell $reduce_or $reduce_or$libresoc.v:41773$2197 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \rp_FAST_fast1_spr0_2 \rp_FAST_fast1_trap0_1 \rp_FAST_fast1_branch0_0 } + connect \Y $reduce_or$libresoc.v:41773$2197_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:313" + cell $reduce_or $reduce_or$libresoc.v:41787$2211 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \rp_FAST_fast2_trap0_1 \rp_FAST_fast2_branch0_0 } + connect \Y $reduce_or$libresoc.v:41787$2211_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:313" + cell $reduce_or $reduce_or$libresoc.v:41794$2218 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \rp_SPR_spr1_spr0_0 + connect \Y $reduce_or$libresoc.v:41794$2218_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" + cell $sshl $sshl$libresoc.v:41186$1603 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 16 + connect \A 1'1 + connect \B \$1234 + connect \Y $sshl$libresoc.v:41186$1603_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" + cell $sshl $sshl$libresoc.v:41194$1611 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 16 + connect \A 1'1 + connect \B \$1254 + connect \Y $sshl$libresoc.v:41194$1611_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" + cell $sshl $sshl$libresoc.v:41202$1619 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 16 + connect \A 1'1 + connect \B \$1274 + connect \Y $sshl$libresoc.v:41202$1619_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" + cell $sshl $sshl$libresoc.v:41210$1627 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 16 + connect \A 1'1 + connect \B \$1294 + connect \Y $sshl$libresoc.v:41210$1627_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" + cell $sshl $sshl$libresoc.v:41218$1635 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 16 + connect \A 1'1 + connect \B \$1314 + connect \Y $sshl$libresoc.v:41218$1635_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" + cell $sshl $sshl$libresoc.v:41226$1643 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 16 + connect \A 1'1 + connect \B \$1334 + connect \Y $sshl$libresoc.v:41226$1643_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:64" + cell $sshl $sshl$libresoc.v:41726$2150 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 16 + connect \A 1'1 + connect \B \$785 + connect \Y $sshl$libresoc.v:41726$2150_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:64" + cell $sshl $sshl$libresoc.v:41734$2158 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 16 + connect \A 1'1 + connect \B \$801 + connect \Y $sshl$libresoc.v:41734$2158_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:66" + cell $sshl $sshl$libresoc.v:41743$2167 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 16 + connect \A 1'1 + connect \B \$820 + connect \Y $sshl$libresoc.v:41743$2167_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:68" + cell $sshl $sshl$libresoc.v:41751$2175 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 16 + connect \A 1'1 + connect \B \$836 + connect \Y $sshl$libresoc.v:41751$2175_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" + cell $sub $sub$libresoc.v:41185$1602 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 4 + connect \A 3'111 + connect \B \core_cr_out + connect \Y $sub$libresoc.v:41185$1602_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" + cell $sub $sub$libresoc.v:41193$1610 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 4 + connect \A 3'111 + connect \B \core_cr_out + connect \Y $sub$libresoc.v:41193$1610_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" + cell $sub $sub$libresoc.v:41201$1618 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 4 + connect \A 3'111 + connect \B \core_cr_out + connect \Y $sub$libresoc.v:41201$1618_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" + cell $sub $sub$libresoc.v:41209$1626 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 4 + connect \A 3'111 + connect \B \core_cr_out + connect \Y $sub$libresoc.v:41209$1626_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" + cell $sub $sub$libresoc.v:41217$1634 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 4 + connect \A 3'111 + connect \B \core_cr_out + connect \Y $sub$libresoc.v:41217$1634_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" + cell $sub $sub$libresoc.v:41225$1642 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 4 + connect \A 3'111 + connect \B \core_cr_out + connect \Y $sub$libresoc.v:41225$1642_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + cell $sub $sub$libresoc.v:41434$1856 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \counter + connect \B 1'1 + connect \Y $sub$libresoc.v:41434$1856_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:64" + cell $sub $sub$libresoc.v:41725$2149 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 4 + connect \A 3'111 + connect \B \core_cr_in1 + connect \Y $sub$libresoc.v:41725$2149_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:64" + cell $sub $sub$libresoc.v:41733$2157 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 4 + connect \A 3'111 + connect \B \core_cr_in1 + connect \Y $sub$libresoc.v:41733$2157_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:66" + cell $sub $sub$libresoc.v:41742$2166 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 4 + connect \A 3'111 + connect \B \core_cr_in2 + connect \Y $sub$libresoc.v:41742$2166_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:68" + cell $sub $sub$libresoc.v:41750$2174 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 4 + connect \A 3'111 + connect \B \core_cr_in2$1 + connect \Y $sub$libresoc.v:41750$2174_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" + cell $mux $ternary$libresoc.v:41097$1514 + parameter \WIDTH 5 + connect \A 5'00000 + connect \B \core_rego + connect \S \wp$996 + connect \Y $ternary$libresoc.v:41097$1514_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" + cell $mux $ternary$libresoc.v:41103$1520 + parameter \WIDTH 5 + connect \A 5'00000 + connect \B \core_rego + connect \S \wp$1014 + connect \Y $ternary$libresoc.v:41103$1520_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" + cell $mux $ternary$libresoc.v:41109$1526 + parameter \WIDTH 5 + connect \A 5'00000 + connect \B \core_rego + connect \S \wp$1036 + connect \Y $ternary$libresoc.v:41109$1526_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" + cell $mux $ternary$libresoc.v:41115$1532 + parameter \WIDTH 5 + connect \A 5'00000 + connect \B \core_rego + connect \S \wp$1056 + connect \Y $ternary$libresoc.v:41115$1532_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" + cell $mux $ternary$libresoc.v:41121$1538 + parameter \WIDTH 5 + connect \A 5'00000 + connect \B \core_rego + connect \S \wp$1076 + connect \Y $ternary$libresoc.v:41121$1538_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" + cell $mux $ternary$libresoc.v:41127$1544 + parameter \WIDTH 5 + connect \A 5'00000 + connect \B \core_rego + connect \S \wp$1095 + connect \Y $ternary$libresoc.v:41127$1544_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" + cell $mux $ternary$libresoc.v:41133$1550 + parameter \WIDTH 5 + connect \A 5'00000 + connect \B \core_rego + connect \S \wp$1113 + connect \Y $ternary$libresoc.v:41133$1550_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" + cell $mux $ternary$libresoc.v:41139$1556 + parameter \WIDTH 5 + connect \A 5'00000 + connect \B \core_ea + connect \S \wp$1129 + connect \Y $ternary$libresoc.v:41139$1556_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" + cell $mux $ternary$libresoc.v:41173$1590 + parameter \WIDTH 8 + connect \A 8'00000000 + connect \B \core_core_cr_wr + connect \S \wp$1202 + connect \Y $ternary$libresoc.v:41173$1590_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" + cell $mux $ternary$libresoc.v:41187$1604 + parameter \WIDTH 16 + connect \A 16'0000000000000000 + connect \B \$1236 + connect \S \wp$1230 + connect \Y $ternary$libresoc.v:41187$1604_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" + cell $mux $ternary$libresoc.v:41195$1612 + parameter \WIDTH 16 + connect \A 16'0000000000000000 + connect \B \$1256 + connect \S \wp$1250 + connect \Y $ternary$libresoc.v:41195$1612_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" + cell $mux $ternary$libresoc.v:41203$1620 + parameter \WIDTH 16 + connect \A 16'0000000000000000 + connect \B \$1276 + connect \S \wp$1270 + connect \Y $ternary$libresoc.v:41203$1620_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" + cell $mux $ternary$libresoc.v:41211$1628 + parameter \WIDTH 16 + connect \A 16'0000000000000000 + connect \B \$1296 + connect \S \wp$1290 + connect \Y $ternary$libresoc.v:41211$1628_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" + cell $mux $ternary$libresoc.v:41219$1636 + parameter \WIDTH 16 + connect \A 16'0000000000000000 + connect \B \$1316 + connect \S \wp$1310 + connect \Y $ternary$libresoc.v:41219$1636_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" + cell $mux $ternary$libresoc.v:41227$1644 + parameter \WIDTH 16 + connect \A 16'0000000000000000 + connect \B \$1336 + connect \S \wp$1330 + connect \Y $ternary$libresoc.v:41227$1644_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" + cell $mux $ternary$libresoc.v:41246$1663 + parameter \WIDTH 2 + connect \A 2'00 + connect \B 2'10 + connect \S \wp$1377 + connect \Y $ternary$libresoc.v:41246$1663_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" + cell $mux $ternary$libresoc.v:41252$1669 + parameter \WIDTH 2 + connect \A 2'00 + connect \B 2'10 + connect \S \wp$1393 + connect \Y $ternary$libresoc.v:41252$1669_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" + cell $mux $ternary$libresoc.v:41258$1675 + parameter \WIDTH 2 + connect \A 2'00 + connect \B 2'10 + connect \S \wp$1409 + connect \Y $ternary$libresoc.v:41258$1675_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" + cell $mux $ternary$libresoc.v:41273$1691 + parameter \WIDTH 3 + connect \A 3'000 + connect \B 3'100 + connect \S \wp$1443 + connect \Y $ternary$libresoc.v:41273$1691_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" + cell $mux $ternary$libresoc.v:41279$1697 + parameter \WIDTH 3 + connect \A 3'000 + connect \B 3'100 + connect \S \wp$1459 + connect \Y $ternary$libresoc.v:41279$1697_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" + cell $mux $ternary$libresoc.v:41285$1703 + parameter \WIDTH 3 + connect \A 3'000 + connect \B 3'100 + connect \S \wp$1475 + connect \Y $ternary$libresoc.v:41285$1703_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" + cell $mux $ternary$libresoc.v:41291$1709 + parameter \WIDTH 3 + connect \A 3'000 + connect \B 3'100 + connect \S \wp$1491 + connect \Y $ternary$libresoc.v:41291$1709_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" + cell $mux $ternary$libresoc.v:41307$1725 + parameter \WIDTH 1 + connect \A 1'0 + connect \B 1'1 + connect \S \wp$1527 + connect \Y $ternary$libresoc.v:41307$1725_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" + cell $mux $ternary$libresoc.v:41313$1731 + parameter \WIDTH 1 + connect \A 1'0 + connect \B 1'1 + connect \S \wp$1543 + connect \Y $ternary$libresoc.v:41313$1731_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" + cell $mux $ternary$libresoc.v:41319$1737 + parameter \WIDTH 1 + connect \A 1'0 + connect \B 1'1 + connect \S \wp$1559 + connect \Y $ternary$libresoc.v:41319$1737_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" + cell $mux $ternary$libresoc.v:41325$1743 + parameter \WIDTH 1 + connect \A 1'0 + connect \B 1'1 + connect \S \wp$1575 + connect \Y $ternary$libresoc.v:41325$1743_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" + cell $mux $ternary$libresoc.v:41345$1765 + parameter \WIDTH 3 + connect \A 3'000 + connect \B \core_fasto1 + connect \S \wp$1620 + connect \Y $ternary$libresoc.v:41345$1765_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" + cell $mux $ternary$libresoc.v:41352$1772 + parameter \WIDTH 3 + connect \A 3'000 + connect \B \core_fasto1 + connect \S \wp$1636 + connect \Y $ternary$libresoc.v:41352$1772_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" + cell $mux $ternary$libresoc.v:41358$1778 + parameter \WIDTH 3 + connect \A 3'000 + connect \B \core_fasto1 + connect \S \wp$1652 + connect \Y $ternary$libresoc.v:41358$1778_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" + cell $mux $ternary$libresoc.v:41366$1786 + parameter \WIDTH 3 + connect \A 3'000 + connect \B \core_fasto2 + connect \S \wp$1668 + connect \Y $ternary$libresoc.v:41366$1786_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" + cell $mux $ternary$libresoc.v:41372$1792 + parameter \WIDTH 3 + connect \A 3'000 + connect \B \core_fasto2 + connect \S \wp$1684 + connect \Y $ternary$libresoc.v:41372$1792_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" + cell $mux $ternary$libresoc.v:41394$1814 + parameter \WIDTH 1 + connect \A 1'0 + connect \B 1'1 + connect \S \wp$1728 + connect \Y $ternary$libresoc.v:41394$1814_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" + cell $mux $ternary$libresoc.v:41401$1821 + parameter \WIDTH 1 + connect \A 1'0 + connect \B 1'1 + connect \S \wp$1744 + connect \Y $ternary$libresoc.v:41401$1821_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" + cell $mux $ternary$libresoc.v:41412$1833 + parameter \WIDTH 2 + connect \A 2'00 + connect \B 2'10 + connect \S \wp$1768 + connect \Y $ternary$libresoc.v:41412$1833_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" + cell $mux $ternary$libresoc.v:41422$1844 + parameter \WIDTH 10 + connect \A 10'0000000000 + connect \B \core_spro + connect \S \wp$1788 + connect \Y $ternary$libresoc.v:41422$1844_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + cell $mux $ternary$libresoc.v:41503$1925 + parameter \WIDTH 5 + connect \A 5'00000 + connect \B \core_reg1 + connect \S \rp_INT_ra_alu0_0 + connect \Y $ternary$libresoc.v:41503$1925_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + cell $mux $ternary$libresoc.v:41509$1931 + parameter \WIDTH 5 + connect \A 5'00000 + connect \B \core_reg1 + connect \S \rp_INT_ra_cr0_1 + connect \Y $ternary$libresoc.v:41509$1931_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + cell $mux $ternary$libresoc.v:41515$1937 + parameter \WIDTH 5 + connect \A 5'00000 + connect \B \core_reg1 + connect \S \rp_INT_ra_trap0_2 + connect \Y $ternary$libresoc.v:41515$1937_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + cell $mux $ternary$libresoc.v:41521$1943 + parameter \WIDTH 5 + connect \A 5'00000 + connect \B \core_reg1 + connect \S \rp_INT_ra_logical0_3 + connect \Y $ternary$libresoc.v:41521$1943_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + cell $mux $ternary$libresoc.v:41527$1949 + parameter \WIDTH 5 + connect \A 5'00000 + connect \B \core_reg1 + connect \S \rp_INT_ra_spr0_4 + connect \Y $ternary$libresoc.v:41527$1949_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + cell $mux $ternary$libresoc.v:41533$1955 + parameter \WIDTH 5 + connect \A 5'00000 + connect \B \core_reg1 + connect \S \rp_INT_ra_div0_5 + connect \Y $ternary$libresoc.v:41533$1955_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + cell $mux $ternary$libresoc.v:41539$1961 + parameter \WIDTH 5 + connect \A 5'00000 + connect \B \core_reg1 + connect \S \rp_INT_ra_mul0_6 + connect \Y $ternary$libresoc.v:41539$1961_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + cell $mux $ternary$libresoc.v:41545$1967 + parameter \WIDTH 5 + connect \A 5'00000 + connect \B \core_reg1 + connect \S \rp_INT_ra_shiftrot0_7 + connect \Y $ternary$libresoc.v:41545$1967_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + cell $mux $ternary$libresoc.v:41551$1973 + parameter \WIDTH 5 + connect \A 5'00000 + connect \B \core_reg1 + connect \S \rp_INT_ra_ldst0_8 + connect \Y $ternary$libresoc.v:41551$1973_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + cell $mux $ternary$libresoc.v:41566$1988 + parameter \WIDTH 5 + connect \A 5'00000 + connect \B \core_reg2 + connect \S \rp_INT_rb_alu0_0 + connect \Y $ternary$libresoc.v:41566$1988_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + cell $mux $ternary$libresoc.v:41572$1994 + parameter \WIDTH 5 + connect \A 5'00000 + connect \B \core_reg2 + connect \S \rp_INT_rb_cr0_1 + connect \Y $ternary$libresoc.v:41572$1994_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + cell $mux $ternary$libresoc.v:41578$2000 + parameter \WIDTH 5 + connect \A 5'00000 + connect \B \core_reg2 + connect \S \rp_INT_rb_trap0_2 + connect \Y $ternary$libresoc.v:41578$2000_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + cell $mux $ternary$libresoc.v:41584$2006 + parameter \WIDTH 5 + connect \A 5'00000 + connect \B \core_reg2 + connect \S \rp_INT_rb_logical0_3 + connect \Y $ternary$libresoc.v:41584$2006_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + cell $mux $ternary$libresoc.v:41590$2012 + parameter \WIDTH 5 + connect \A 5'00000 + connect \B \core_reg2 + connect \S \rp_INT_rb_div0_4 + connect \Y $ternary$libresoc.v:41590$2012_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + cell $mux $ternary$libresoc.v:41596$2018 + parameter \WIDTH 5 + connect \A 5'00000 + connect \B \core_reg2 + connect \S \rp_INT_rb_mul0_5 + connect \Y $ternary$libresoc.v:41596$2018_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + cell $mux $ternary$libresoc.v:41602$2024 + parameter \WIDTH 5 + connect \A 5'00000 + connect \B \core_reg2 + connect \S \rp_INT_rb_shiftrot0_6 + connect \Y $ternary$libresoc.v:41602$2024_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + cell $mux $ternary$libresoc.v:41608$2030 + parameter \WIDTH 5 + connect \A 5'00000 + connect \B \core_reg2 + connect \S \rp_INT_rb_ldst0_7 + connect \Y $ternary$libresoc.v:41608$2030_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + cell $mux $ternary$libresoc.v:41622$2044 + parameter \WIDTH 5 + connect \A 5'00000 + connect \B \core_reg3 + connect \S \rp_INT_rc_shiftrot0_0 + connect \Y $ternary$libresoc.v:41622$2044_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + cell $mux $ternary$libresoc.v:41628$2050 + parameter \WIDTH 5 + connect \A 5'00000 + connect \B \core_reg3 + connect \S \rp_INT_rc_ldst0_1 + connect \Y $ternary$libresoc.v:41628$2050_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + cell $mux $ternary$libresoc.v:41642$2064 + parameter \WIDTH 1 + connect \A 1'0 + connect \B 1'1 + connect \S \rp_XER_xer_so_alu0_0 + connect \Y $ternary$libresoc.v:41642$2064_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + cell $mux $ternary$libresoc.v:41648$2070 + parameter \WIDTH 1 + connect \A 1'0 + connect \B 1'1 + connect \S \rp_XER_xer_so_logical0_1 + connect \Y $ternary$libresoc.v:41648$2070_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + cell $mux $ternary$libresoc.v:41654$2076 + parameter \WIDTH 1 + connect \A 1'0 + connect \B 1'1 + connect \S \rp_XER_xer_so_spr0_2 + connect \Y $ternary$libresoc.v:41654$2076_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + cell $mux $ternary$libresoc.v:41660$2082 + parameter \WIDTH 1 + connect \A 1'0 + connect \B 1'1 + connect \S \rp_XER_xer_so_div0_3 + connect \Y $ternary$libresoc.v:41660$2082_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + cell $mux $ternary$libresoc.v:41666$2088 + parameter \WIDTH 1 + connect \A 1'0 + connect \B 1'1 + connect \S \rp_XER_xer_so_mul0_4 + connect \Y $ternary$libresoc.v:41666$2088_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + cell $mux $ternary$libresoc.v:41672$2094 + parameter \WIDTH 1 + connect \A 1'0 + connect \B 1'1 + connect \S \rp_XER_xer_so_shiftrot0_5 + connect \Y $ternary$libresoc.v:41672$2094_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + cell $mux $ternary$libresoc.v:41688$2111 + parameter \WIDTH 2 + connect \A 2'00 + connect \B 2'10 + connect \S \rp_XER_xer_ca_alu0_0 + connect \Y $ternary$libresoc.v:41688$2111_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + cell $mux $ternary$libresoc.v:41694$2117 + parameter \WIDTH 2 + connect \A 2'00 + connect \B 2'10 + connect \S \rp_XER_xer_ca_spr0_1 + connect \Y $ternary$libresoc.v:41694$2117_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + cell $mux $ternary$libresoc.v:41700$2123 + parameter \WIDTH 2 + connect \A 2'00 + connect \B 2'10 + connect \S \rp_XER_xer_ca_shiftrot0_2 + connect \Y $ternary$libresoc.v:41700$2123_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + cell $mux $ternary$libresoc.v:41713$2137 + parameter \WIDTH 3 + connect \A 3'000 + connect \B 3'100 + connect \S \rp_XER_xer_ov_spr0_0 + connect \Y $ternary$libresoc.v:41713$2137_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + cell $mux $ternary$libresoc.v:41719$2143 + parameter \WIDTH 8 + connect \A 8'00000000 + connect \B \core_core_cr_rd + connect \S \rp_CR_full_cr_cr0_0 + connect \Y $ternary$libresoc.v:41719$2143_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + cell $mux $ternary$libresoc.v:41727$2151 + parameter \WIDTH 16 + connect \A 16'0000000000000000 + connect \B \$787 + connect \S \rp_CR_cr_a_cr0_0 + connect \Y $ternary$libresoc.v:41727$2151_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + cell $mux $ternary$libresoc.v:41735$2159 + parameter \WIDTH 16 + connect \A 16'0000000000000000 + connect \B \$803 + connect \S \rp_CR_cr_a_branch0_1 + connect \Y $ternary$libresoc.v:41735$2159_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + cell $mux $ternary$libresoc.v:41744$2168 + parameter \WIDTH 16 + connect \A 16'0000000000000000 + connect \B \$822 + connect \S \rp_CR_cr_b_cr0_0 + connect \Y $ternary$libresoc.v:41744$2168_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + cell $mux $ternary$libresoc.v:41752$2176 + parameter \WIDTH 16 + connect \A 16'0000000000000000 + connect \B \$838 + connect \S \rp_CR_cr_c_cr0_0 + connect \Y $ternary$libresoc.v:41752$2176_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + cell $mux $ternary$libresoc.v:41758$2182 + parameter \WIDTH 3 + connect \A 3'000 + connect \B \core_fast1 + connect \S \rp_FAST_fast1_branch0_0 + connect \Y $ternary$libresoc.v:41758$2182_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + cell $mux $ternary$libresoc.v:41764$2188 + parameter \WIDTH 3 + connect \A 3'000 + connect \B \core_fast1 + connect \S \rp_FAST_fast1_trap0_1 + connect \Y $ternary$libresoc.v:41764$2188_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + cell $mux $ternary$libresoc.v:41770$2194 + parameter \WIDTH 3 + connect \A 3'000 + connect \B \core_fast1 + connect \S \rp_FAST_fast1_spr0_2 + connect \Y $ternary$libresoc.v:41770$2194_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + cell $mux $ternary$libresoc.v:41779$2203 + parameter \WIDTH 3 + connect \A 3'000 + connect \B \core_fast2 + connect \S \rp_FAST_fast2_branch0_0 + connect \Y $ternary$libresoc.v:41779$2203_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + cell $mux $ternary$libresoc.v:41785$2209 + parameter \WIDTH 3 + connect \A 3'000 + connect \B \core_fast2 + connect \S \rp_FAST_fast2_trap0_1 + connect \Y $ternary$libresoc.v:41785$2209_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" + cell $mux $ternary$libresoc.v:41793$2217 + parameter \WIDTH 10 + connect \A 10'0000000000 + connect \B \core_spr1 + connect \S \rp_SPR_spr1_spr0_0 + connect \Y $ternary$libresoc.v:41793$2217_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" + cell $mux $ternary$libresoc.v:41810$2234 + parameter \WIDTH 5 + connect \A 5'00000 + connect \B \core_rego + connect \S \wp + connect \Y $ternary$libresoc.v:41810$2234_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" + cell $mux $ternary$libresoc.v:41816$2240 + parameter \WIDTH 5 + connect \A 5'00000 + connect \B \core_rego + connect \S \wp$975 + connect \Y $ternary$libresoc.v:41816$2240_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:41980.6-41997.4" + cell \cr \cr + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \data_i \cr_data_i + connect \full_rd2__data_o \full_rd2__data_o + connect \full_rd2__ren \full_rd2__ren + connect \full_rd__data_o \cr_full_rd__data_o + connect \full_rd__ren \cr_full_rd__ren + connect \full_wr__data_i \cr_full_wr__data_i + connect \full_wr__wen \cr_full_wr__wen + connect \src1__data_o \cr_src1__data_o + connect \src1__ren \cr_src1__ren + connect \src2__data_o \cr_src2__data_o + connect \src2__ren \cr_src2__ren + connect \src3__data_o \cr_src3__data_o + connect \src3__ren \cr_src3__ren + connect \wen \cr_wen + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:41998.11-42019.4" + cell \dec_ALU \dec_ALU + connect \ALU_ALU__data_len \dec_ALU_ALU_ALU__data_len + connect \ALU_ALU__fn_unit \dec_ALU_ALU_ALU__fn_unit + connect \ALU_ALU__imm_data__data \dec_ALU_ALU_ALU__imm_data__data + connect \ALU_ALU__imm_data__ok \dec_ALU_ALU_ALU__imm_data__ok + connect \ALU_ALU__input_carry \dec_ALU_ALU_ALU__input_carry + connect \ALU_ALU__insn \dec_ALU_ALU_ALU__insn + connect \ALU_ALU__insn_type \dec_ALU_ALU_ALU__insn_type + connect \ALU_ALU__invert_in \dec_ALU_ALU_ALU__invert_in + connect \ALU_ALU__invert_out \dec_ALU_ALU_ALU__invert_out + connect \ALU_ALU__is_32bit \dec_ALU_ALU_ALU__is_32bit + connect \ALU_ALU__is_signed \dec_ALU_ALU_ALU__is_signed + connect \ALU_ALU__oe__oe \dec_ALU_ALU_ALU__oe__oe + connect \ALU_ALU__oe__ok \dec_ALU_ALU_ALU__oe__ok + connect \ALU_ALU__output_carry \dec_ALU_ALU_ALU__output_carry + connect \ALU_ALU__rc__ok \dec_ALU_ALU_ALU__rc__ok + connect \ALU_ALU__rc__rc \dec_ALU_ALU_ALU__rc__rc + connect \ALU_ALU__write_cr0 \dec_ALU_ALU_ALU__write_cr0 + connect \ALU_ALU__zero_a \dec_ALU_ALU_ALU__zero_a + connect \bigendian \dec_ALU_bigendian + connect \raw_opcode_in \dec_ALU_raw_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:42020.14-42032.4" + cell \dec_BRANCH \dec_BRANCH + connect \BRANCH_BRANCH__cia \dec_BRANCH_BRANCH_BRANCH__cia + connect \BRANCH_BRANCH__fn_unit \dec_BRANCH_BRANCH_BRANCH__fn_unit + connect \BRANCH_BRANCH__imm_data__data \dec_BRANCH_BRANCH_BRANCH__imm_data__data + connect \BRANCH_BRANCH__imm_data__ok \dec_BRANCH_BRANCH_BRANCH__imm_data__ok + connect \BRANCH_BRANCH__insn \dec_BRANCH_BRANCH_BRANCH__insn + connect \BRANCH_BRANCH__insn_type \dec_BRANCH_BRANCH_BRANCH__insn_type + connect \BRANCH_BRANCH__is_32bit \dec_BRANCH_BRANCH_BRANCH__is_32bit + connect \BRANCH_BRANCH__lk \dec_BRANCH_BRANCH_BRANCH__lk + connect \bigendian \dec_BRANCH_bigendian + connect \core_pc \core_pc + connect \raw_opcode_in \dec_BRANCH_raw_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:42033.10-42039.4" + cell \dec_CR \dec_CR + connect \CR_CR__fn_unit \dec_CR_CR_CR__fn_unit + connect \CR_CR__insn \dec_CR_CR_CR__insn + connect \CR_CR__insn_type \dec_CR_CR_CR__insn_type + connect \bigendian \dec_CR_bigendian + connect \raw_opcode_in \dec_CR_raw_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:42040.11-42061.4" + cell \dec_DIV \dec_DIV + connect \DIV_DIV__data_len \dec_DIV_DIV_DIV__data_len + connect \DIV_DIV__fn_unit \dec_DIV_DIV_DIV__fn_unit + connect \DIV_DIV__imm_data__data \dec_DIV_DIV_DIV__imm_data__data + connect \DIV_DIV__imm_data__ok \dec_DIV_DIV_DIV__imm_data__ok + connect \DIV_DIV__input_carry \dec_DIV_DIV_DIV__input_carry + connect \DIV_DIV__insn \dec_DIV_DIV_DIV__insn + connect \DIV_DIV__insn_type \dec_DIV_DIV_DIV__insn_type + connect \DIV_DIV__invert_in \dec_DIV_DIV_DIV__invert_in + connect \DIV_DIV__invert_out \dec_DIV_DIV_DIV__invert_out + connect \DIV_DIV__is_32bit \dec_DIV_DIV_DIV__is_32bit + connect \DIV_DIV__is_signed \dec_DIV_DIV_DIV__is_signed + connect \DIV_DIV__oe__oe \dec_DIV_DIV_DIV__oe__oe + connect \DIV_DIV__oe__ok \dec_DIV_DIV_DIV__oe__ok + connect \DIV_DIV__output_carry \dec_DIV_DIV_DIV__output_carry + connect \DIV_DIV__rc__ok \dec_DIV_DIV_DIV__rc__ok + connect \DIV_DIV__rc__rc \dec_DIV_DIV_DIV__rc__rc + connect \DIV_DIV__write_cr0 \dec_DIV_DIV_DIV__write_cr0 + connect \DIV_DIV__zero_a \dec_DIV_DIV_DIV__zero_a + connect \bigendian \dec_DIV_bigendian + connect \raw_opcode_in \dec_DIV_raw_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:42062.12-42081.4" + cell \dec_LDST \dec_LDST + connect \LDST_LDST__byte_reverse \dec_LDST_LDST_LDST__byte_reverse + connect \LDST_LDST__data_len \dec_LDST_LDST_LDST__data_len + connect \LDST_LDST__fn_unit \dec_LDST_LDST_LDST__fn_unit + connect \LDST_LDST__imm_data__data \dec_LDST_LDST_LDST__imm_data__data + connect \LDST_LDST__imm_data__ok \dec_LDST_LDST_LDST__imm_data__ok + connect \LDST_LDST__insn \dec_LDST_LDST_LDST__insn + connect \LDST_LDST__insn_type \dec_LDST_LDST_LDST__insn_type + connect \LDST_LDST__is_32bit \dec_LDST_LDST_LDST__is_32bit + connect \LDST_LDST__is_signed \dec_LDST_LDST_LDST__is_signed + connect \LDST_LDST__ldst_mode \dec_LDST_LDST_LDST__ldst_mode + connect \LDST_LDST__oe__oe \dec_LDST_LDST_LDST__oe__oe + connect \LDST_LDST__oe__ok \dec_LDST_LDST_LDST__oe__ok + connect \LDST_LDST__rc__ok \dec_LDST_LDST_LDST__rc__ok + connect \LDST_LDST__rc__rc \dec_LDST_LDST_LDST__rc__rc + connect \LDST_LDST__sign_extend \dec_LDST_LDST_LDST__sign_extend + connect \LDST_LDST__zero_a \dec_LDST_LDST_LDST__zero_a + connect \bigendian \dec_LDST_bigendian + connect \raw_opcode_in \dec_LDST_raw_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:42082.15-42103.4" + cell \dec_LOGICAL \dec_LOGICAL + connect \LOGICAL_LOGICAL__data_len \dec_LOGICAL_LOGICAL_LOGICAL__data_len + connect \LOGICAL_LOGICAL__fn_unit \dec_LOGICAL_LOGICAL_LOGICAL__fn_unit + connect \LOGICAL_LOGICAL__imm_data__data \dec_LOGICAL_LOGICAL_LOGICAL__imm_data__data + connect \LOGICAL_LOGICAL__imm_data__ok \dec_LOGICAL_LOGICAL_LOGICAL__imm_data__ok + connect \LOGICAL_LOGICAL__input_carry \dec_LOGICAL_LOGICAL_LOGICAL__input_carry + connect \LOGICAL_LOGICAL__insn \dec_LOGICAL_LOGICAL_LOGICAL__insn + connect \LOGICAL_LOGICAL__insn_type \dec_LOGICAL_LOGICAL_LOGICAL__insn_type + connect \LOGICAL_LOGICAL__invert_in \dec_LOGICAL_LOGICAL_LOGICAL__invert_in + connect \LOGICAL_LOGICAL__invert_out \dec_LOGICAL_LOGICAL_LOGICAL__invert_out + connect \LOGICAL_LOGICAL__is_32bit \dec_LOGICAL_LOGICAL_LOGICAL__is_32bit + connect \LOGICAL_LOGICAL__is_signed \dec_LOGICAL_LOGICAL_LOGICAL__is_signed + connect \LOGICAL_LOGICAL__oe__oe \dec_LOGICAL_LOGICAL_LOGICAL__oe__oe + connect \LOGICAL_LOGICAL__oe__ok \dec_LOGICAL_LOGICAL_LOGICAL__oe__ok + connect \LOGICAL_LOGICAL__output_carry \dec_LOGICAL_LOGICAL_LOGICAL__output_carry + connect \LOGICAL_LOGICAL__rc__ok \dec_LOGICAL_LOGICAL_LOGICAL__rc__ok + connect \LOGICAL_LOGICAL__rc__rc \dec_LOGICAL_LOGICAL_LOGICAL__rc__rc + connect \LOGICAL_LOGICAL__write_cr0 \dec_LOGICAL_LOGICAL_LOGICAL__write_cr0 + connect \LOGICAL_LOGICAL__zero_a \dec_LOGICAL_LOGICAL_LOGICAL__zero_a + connect \bigendian \dec_LOGICAL_bigendian + connect \raw_opcode_in \dec_LOGICAL_raw_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:42104.11-42119.4" + cell \dec_MUL \dec_MUL + connect \MUL_MUL__fn_unit \dec_MUL_MUL_MUL__fn_unit + connect \MUL_MUL__imm_data__data \dec_MUL_MUL_MUL__imm_data__data + connect \MUL_MUL__imm_data__ok \dec_MUL_MUL_MUL__imm_data__ok + connect \MUL_MUL__insn \dec_MUL_MUL_MUL__insn + connect \MUL_MUL__insn_type \dec_MUL_MUL_MUL__insn_type + connect \MUL_MUL__is_32bit \dec_MUL_MUL_MUL__is_32bit + connect \MUL_MUL__is_signed \dec_MUL_MUL_MUL__is_signed + connect \MUL_MUL__oe__oe \dec_MUL_MUL_MUL__oe__oe + connect \MUL_MUL__oe__ok \dec_MUL_MUL_MUL__oe__ok + connect \MUL_MUL__rc__ok \dec_MUL_MUL_MUL__rc__ok + connect \MUL_MUL__rc__rc \dec_MUL_MUL_MUL__rc__rc + connect \MUL_MUL__write_cr0 \dec_MUL_MUL_MUL__write_cr0 + connect \bigendian \dec_MUL_bigendian + connect \raw_opcode_in \dec_MUL_raw_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:42120.17-42139.4" + cell \dec_SHIFT_ROT \dec_SHIFT_ROT + connect \SHIFT_ROT_SHIFT_ROT__fn_unit \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__fn_unit + connect \SHIFT_ROT_SHIFT_ROT__imm_data__data \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__imm_data__data + connect \SHIFT_ROT_SHIFT_ROT__imm_data__ok \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__imm_data__ok + connect \SHIFT_ROT_SHIFT_ROT__input_carry \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__input_carry + connect \SHIFT_ROT_SHIFT_ROT__input_cr \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__input_cr + connect \SHIFT_ROT_SHIFT_ROT__insn \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__insn + connect \SHIFT_ROT_SHIFT_ROT__insn_type \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__insn_type + connect \SHIFT_ROT_SHIFT_ROT__is_32bit \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__is_32bit + connect \SHIFT_ROT_SHIFT_ROT__is_signed \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__is_signed + connect \SHIFT_ROT_SHIFT_ROT__oe__oe \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__oe__oe + connect \SHIFT_ROT_SHIFT_ROT__oe__ok \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__oe__ok + connect \SHIFT_ROT_SHIFT_ROT__output_carry \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__output_carry + connect \SHIFT_ROT_SHIFT_ROT__output_cr \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__output_cr + connect \SHIFT_ROT_SHIFT_ROT__rc__ok \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__rc__ok + connect \SHIFT_ROT_SHIFT_ROT__rc__rc \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__rc__rc + connect \SHIFT_ROT_SHIFT_ROT__write_cr0 \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__write_cr0 + connect \bigendian \dec_SHIFT_ROT_bigendian + connect \raw_opcode_in \dec_SHIFT_ROT_raw_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:42140.11-42147.4" + cell \dec_SPR \dec_SPR + connect \SPR_SPR__fn_unit \dec_SPR_SPR_SPR__fn_unit + connect \SPR_SPR__insn \dec_SPR_SPR_SPR__insn + connect \SPR_SPR__insn_type \dec_SPR_SPR_SPR__insn_type + connect \SPR_SPR__is_32bit \dec_SPR_SPR_SPR__is_32bit + connect \bigendian \dec_SPR_bigendian + connect \raw_opcode_in \dec_SPR_raw_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:42148.8-42166.4" + cell \fast \fast + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \dest1__addr \fast_dest1__addr + connect \dest1__data_i \fast_dest1__data_i + connect \dest1__wen \fast_dest1__wen + connect \issue__addr \issue__addr + connect \issue__addr$1 \issue__addr$3 + connect \issue__data_i \issue__data_i + connect \issue__data_o \issue__data_o + connect \issue__ren \issue__ren + connect \issue__wen \issue__wen + connect \src1__addr \fast_src1__addr + connect \src1__data_o \fast_src1__data_o + connect \src1__ren \fast_src1__ren + connect \src2__addr \fast_src2__addr + connect \src2__data_o \fast_src2__data_o + connect \src2__ren \fast_src2__ren + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:42167.7-42489.4" + cell \fus \fus + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cr_a_ok \fus_cr_a_ok + connect \cr_a_ok$110 \fus_cr_a_ok$113 + connect \cr_a_ok$111 \fus_cr_a_ok$114 + connect \cr_a_ok$112 \fus_cr_a_ok$115 + connect \cr_a_ok$113 \fus_cr_a_ok$116 + connect \cr_a_ok$114 \fus_cr_a_ok$117 + connect \cu_ad__go_i \cu_ad__go_i + connect \cu_ad__rel_o \cu_ad__rel_o + connect \cu_busy_o \fus_cu_busy_o + connect \cu_busy_o$11 \fus_cu_busy_o$14 + connect \cu_busy_o$14 \fus_cu_busy_o$17 + connect \cu_busy_o$17 \fus_cu_busy_o$20 + connect \cu_busy_o$2 \fus_cu_busy_o$5 + connect \cu_busy_o$20 \fus_cu_busy_o$23 + connect \cu_busy_o$23 \fus_cu_busy_o$26 + connect \cu_busy_o$26 \fus_cu_busy_o$29 + connect \cu_busy_o$5 \fus_cu_busy_o$8 + connect \cu_busy_o$8 \fus_cu_busy_o$11 + connect \cu_issue_i \fus_cu_issue_i + connect \cu_issue_i$1 \fus_cu_issue_i$4 + connect \cu_issue_i$10 \fus_cu_issue_i$13 + connect \cu_issue_i$13 \fus_cu_issue_i$16 + connect \cu_issue_i$16 \fus_cu_issue_i$19 + connect \cu_issue_i$19 \fus_cu_issue_i$22 + connect \cu_issue_i$22 \fus_cu_issue_i$25 + connect \cu_issue_i$25 \fus_cu_issue_i$28 + connect \cu_issue_i$4 \fus_cu_issue_i$7 + connect \cu_issue_i$7 \fus_cu_issue_i$10 + connect \cu_rd__go_i \fus_cu_rd__go_i + connect \cu_rd__go_i$29 \fus_cu_rd__go_i$32 + connect \cu_rd__go_i$32 \fus_cu_rd__go_i$35 + connect \cu_rd__go_i$35 \fus_cu_rd__go_i$38 + connect \cu_rd__go_i$38 \fus_cu_rd__go_i$41 + connect \cu_rd__go_i$41 \fus_cu_rd__go_i$44 + connect \cu_rd__go_i$44 \fus_cu_rd__go_i$47 + connect \cu_rd__go_i$47 \fus_cu_rd__go_i$50 + connect \cu_rd__go_i$50 \fus_cu_rd__go_i$53 + connect \cu_rd__go_i$70 \fus_cu_rd__go_i$73 + connect \cu_rd__rel_o \fus_cu_rd__rel_o + connect \cu_rd__rel_o$28 \fus_cu_rd__rel_o$31 + connect \cu_rd__rel_o$31 \fus_cu_rd__rel_o$34 + connect \cu_rd__rel_o$34 \fus_cu_rd__rel_o$37 + connect \cu_rd__rel_o$37 \fus_cu_rd__rel_o$40 + connect \cu_rd__rel_o$40 \fus_cu_rd__rel_o$43 + connect \cu_rd__rel_o$43 \fus_cu_rd__rel_o$46 + connect \cu_rd__rel_o$46 \fus_cu_rd__rel_o$49 + connect \cu_rd__rel_o$49 \fus_cu_rd__rel_o$52 + connect \cu_rd__rel_o$69 \fus_cu_rd__rel_o$72 + connect \cu_rdmaskn_i \fus_cu_rdmaskn_i + connect \cu_rdmaskn_i$12 \fus_cu_rdmaskn_i$15 + connect \cu_rdmaskn_i$15 \fus_cu_rdmaskn_i$18 + connect \cu_rdmaskn_i$18 \fus_cu_rdmaskn_i$21 + connect \cu_rdmaskn_i$21 \fus_cu_rdmaskn_i$24 + connect \cu_rdmaskn_i$24 \fus_cu_rdmaskn_i$27 + connect \cu_rdmaskn_i$27 \fus_cu_rdmaskn_i$30 + connect \cu_rdmaskn_i$3 \fus_cu_rdmaskn_i$6 + connect \cu_rdmaskn_i$6 \fus_cu_rdmaskn_i$9 + connect \cu_rdmaskn_i$9 \fus_cu_rdmaskn_i$12 + connect \cu_st__go_i \cu_st__go_i + connect \cu_st__rel_o \cu_st__rel_o + connect \cu_wr__go_i \fus_cu_wr__go_i + connect \cu_wr__go_i$100 \fus_cu_wr__go_i$103 + connect \cu_wr__go_i$102 \fus_cu_wr__go_i$105 + connect \cu_wr__go_i$137 \fus_cu_wr__go_i$140 + connect \cu_wr__go_i$82 \fus_cu_wr__go_i$85 + connect \cu_wr__go_i$85 \fus_cu_wr__go_i$88 + connect \cu_wr__go_i$88 \fus_cu_wr__go_i$91 + connect \cu_wr__go_i$91 \fus_cu_wr__go_i$94 + connect \cu_wr__go_i$94 \fus_cu_wr__go_i$97 + connect \cu_wr__go_i$97 \fus_cu_wr__go_i$100 + connect \cu_wr__rel_o \fus_cu_wr__rel_o + connect \cu_wr__rel_o$101 \fus_cu_wr__rel_o$104 + connect \cu_wr__rel_o$136 \fus_cu_wr__rel_o$139 + connect \cu_wr__rel_o$81 \fus_cu_wr__rel_o$84 + connect \cu_wr__rel_o$84 \fus_cu_wr__rel_o$87 + connect \cu_wr__rel_o$87 \fus_cu_wr__rel_o$90 + connect \cu_wr__rel_o$90 \fus_cu_wr__rel_o$93 + connect \cu_wr__rel_o$93 \fus_cu_wr__rel_o$96 + connect \cu_wr__rel_o$96 \fus_cu_wr__rel_o$99 + connect \cu_wr__rel_o$99 \fus_cu_wr__rel_o$102 + connect \dest1_o \fus_dest1_o + connect \dest1_o$103 \fus_dest1_o$106 + connect \dest1_o$104 \fus_dest1_o$107 + connect \dest1_o$105 \fus_dest1_o$108 + connect \dest1_o$106 \fus_dest1_o$109 + connect \dest1_o$107 \fus_dest1_o$110 + connect \dest1_o$108 \fus_dest1_o$111 + connect \dest1_o$109 \fus_dest1_o$112 + connect \dest1_o$141 \fus_dest1_o$144 + connect \dest2_o \fus_dest2_o + connect \dest2_o$115 \fus_dest2_o$118 + connect \dest2_o$116 \fus_dest2_o$119 + connect \dest2_o$117 \fus_dest2_o$120 + connect \dest2_o$118 \fus_dest2_o$121 + connect \dest2_o$119 \fus_dest2_o$122 + connect \dest2_o$142 \fus_dest2_o$145 + connect \dest2_o$144 \fus_dest2_o$147 + connect \dest2_o$150 \fus_dest2_o$153 + connect \dest3_o \fus_dest3_o + connect \dest3_o$122 \fus_dest3_o$125 + connect \dest3_o$123 \fus_dest3_o$126 + connect \dest3_o$127 \fus_dest3_o$130 + connect \dest3_o$128 \fus_dest3_o$131 + connect \dest3_o$143 \fus_dest3_o$146 + connect \dest3_o$145 \fus_dest3_o$148 + connect \dest3_o$147 \fus_dest3_o$150 + connect \dest4_o \fus_dest4_o + connect \dest4_o$133 \fus_dest4_o$136 + connect \dest4_o$134 \fus_dest4_o$137 + connect \dest4_o$135 \fus_dest4_o$138 + connect \dest4_o$148 \fus_dest4_o$151 + connect \dest5_o \fus_dest5_o + connect \dest5_o$132 \fus_dest5_o$135 + connect \dest5_o$149 \fus_dest5_o$152 + connect \dest6_o \fus_dest6_o + connect \ea \fus_ea + connect \fast1_ok \fus_fast1_ok + connect \fast1_ok$138 \fus_fast1_ok$141 + connect \fast1_ok$139 \fus_fast1_ok$142 + connect \fast2_ok \fus_fast2_ok + connect \fast2_ok$140 \fus_fast2_ok$143 + connect \full_cr_ok \fus_full_cr_ok + connect \ldst_port0_addr_exc_o \fus_ldst_port0_addr_exc_o + connect \ldst_port0_addr_i \fus_ldst_port0_addr_i + connect \ldst_port0_addr_i_ok \fus_ldst_port0_addr_i_ok + connect \ldst_port0_addr_ok_o \fus_ldst_port0_addr_ok_o + connect \ldst_port0_busy_o \fus_ldst_port0_busy_o + connect \ldst_port0_data_len \fus_ldst_port0_data_len + connect \ldst_port0_is_ld_i \fus_ldst_port0_is_ld_i + connect \ldst_port0_is_st_i \fus_ldst_port0_is_st_i + connect \ldst_port0_ld_data_o \fus_ldst_port0_ld_data_o + connect \ldst_port0_ld_data_o_ok \fus_ldst_port0_ld_data_o_ok + connect \ldst_port0_st_data_i \fus_ldst_port0_st_data_i + connect \ldst_port0_st_data_i_ok \fus_ldst_port0_st_data_i_ok + connect \msr_ok \fus_msr_ok + connect \nia_ok \fus_nia_ok + connect \nia_ok$146 \fus_nia_ok$149 + connect \o \fus_o + connect \o_ok \fus_o_ok + connect \o_ok$80 \fus_o_ok$83 + connect \o_ok$83 \fus_o_ok$86 + connect \o_ok$86 \fus_o_ok$89 + connect \o_ok$89 \fus_o_ok$92 + connect \o_ok$92 \fus_o_ok$95 + connect \o_ok$95 \fus_o_ok$98 + connect \o_ok$98 \fus_o_ok$101 + connect \oper_i_alu_alu0__data_len \fus_oper_i_alu_alu0__data_len + connect \oper_i_alu_alu0__fn_unit \fus_oper_i_alu_alu0__fn_unit + connect \oper_i_alu_alu0__imm_data__data \fus_oper_i_alu_alu0__imm_data__data + connect \oper_i_alu_alu0__imm_data__ok \fus_oper_i_alu_alu0__imm_data__ok + connect \oper_i_alu_alu0__input_carry \fus_oper_i_alu_alu0__input_carry + connect \oper_i_alu_alu0__insn \fus_oper_i_alu_alu0__insn + connect \oper_i_alu_alu0__insn_type \fus_oper_i_alu_alu0__insn_type + connect \oper_i_alu_alu0__invert_in \fus_oper_i_alu_alu0__invert_in + connect \oper_i_alu_alu0__invert_out \fus_oper_i_alu_alu0__invert_out + connect \oper_i_alu_alu0__is_32bit \fus_oper_i_alu_alu0__is_32bit + connect \oper_i_alu_alu0__is_signed \fus_oper_i_alu_alu0__is_signed + connect \oper_i_alu_alu0__oe__oe \fus_oper_i_alu_alu0__oe__oe + connect \oper_i_alu_alu0__oe__ok \fus_oper_i_alu_alu0__oe__ok + connect \oper_i_alu_alu0__output_carry \fus_oper_i_alu_alu0__output_carry + connect \oper_i_alu_alu0__rc__ok \fus_oper_i_alu_alu0__rc__ok + connect \oper_i_alu_alu0__rc__rc \fus_oper_i_alu_alu0__rc__rc + connect \oper_i_alu_alu0__write_cr0 \fus_oper_i_alu_alu0__write_cr0 + connect \oper_i_alu_alu0__zero_a \fus_oper_i_alu_alu0__zero_a + connect \oper_i_alu_branch0__cia \fus_oper_i_alu_branch0__cia + connect \oper_i_alu_branch0__fn_unit \fus_oper_i_alu_branch0__fn_unit + connect \oper_i_alu_branch0__imm_data__data \fus_oper_i_alu_branch0__imm_data__data + connect \oper_i_alu_branch0__imm_data__ok \fus_oper_i_alu_branch0__imm_data__ok + connect \oper_i_alu_branch0__insn \fus_oper_i_alu_branch0__insn + connect \oper_i_alu_branch0__insn_type \fus_oper_i_alu_branch0__insn_type + connect \oper_i_alu_branch0__is_32bit \fus_oper_i_alu_branch0__is_32bit + connect \oper_i_alu_branch0__lk \fus_oper_i_alu_branch0__lk + connect \oper_i_alu_cr0__fn_unit \fus_oper_i_alu_cr0__fn_unit + connect \oper_i_alu_cr0__insn \fus_oper_i_alu_cr0__insn + connect \oper_i_alu_cr0__insn_type \fus_oper_i_alu_cr0__insn_type + connect \oper_i_alu_div0__data_len \fus_oper_i_alu_div0__data_len + connect \oper_i_alu_div0__fn_unit \fus_oper_i_alu_div0__fn_unit + connect \oper_i_alu_div0__imm_data__data \fus_oper_i_alu_div0__imm_data__data + connect \oper_i_alu_div0__imm_data__ok \fus_oper_i_alu_div0__imm_data__ok + connect \oper_i_alu_div0__input_carry \fus_oper_i_alu_div0__input_carry + connect \oper_i_alu_div0__insn \fus_oper_i_alu_div0__insn + connect \oper_i_alu_div0__insn_type \fus_oper_i_alu_div0__insn_type + connect \oper_i_alu_div0__invert_in \fus_oper_i_alu_div0__invert_in + connect \oper_i_alu_div0__invert_out \fus_oper_i_alu_div0__invert_out + connect \oper_i_alu_div0__is_32bit \fus_oper_i_alu_div0__is_32bit + connect \oper_i_alu_div0__is_signed \fus_oper_i_alu_div0__is_signed + connect \oper_i_alu_div0__oe__oe \fus_oper_i_alu_div0__oe__oe + connect \oper_i_alu_div0__oe__ok \fus_oper_i_alu_div0__oe__ok + connect \oper_i_alu_div0__output_carry \fus_oper_i_alu_div0__output_carry + connect \oper_i_alu_div0__rc__ok \fus_oper_i_alu_div0__rc__ok + connect \oper_i_alu_div0__rc__rc \fus_oper_i_alu_div0__rc__rc + connect \oper_i_alu_div0__write_cr0 \fus_oper_i_alu_div0__write_cr0 + connect \oper_i_alu_div0__zero_a \fus_oper_i_alu_div0__zero_a + connect \oper_i_alu_logical0__data_len \fus_oper_i_alu_logical0__data_len + connect \oper_i_alu_logical0__fn_unit \fus_oper_i_alu_logical0__fn_unit + connect \oper_i_alu_logical0__imm_data__data \fus_oper_i_alu_logical0__imm_data__data + connect \oper_i_alu_logical0__imm_data__ok \fus_oper_i_alu_logical0__imm_data__ok + connect \oper_i_alu_logical0__input_carry \fus_oper_i_alu_logical0__input_carry + connect \oper_i_alu_logical0__insn \fus_oper_i_alu_logical0__insn + connect \oper_i_alu_logical0__insn_type \fus_oper_i_alu_logical0__insn_type + connect \oper_i_alu_logical0__invert_in \fus_oper_i_alu_logical0__invert_in + connect \oper_i_alu_logical0__invert_out \fus_oper_i_alu_logical0__invert_out + connect \oper_i_alu_logical0__is_32bit \fus_oper_i_alu_logical0__is_32bit + connect \oper_i_alu_logical0__is_signed \fus_oper_i_alu_logical0__is_signed + connect \oper_i_alu_logical0__oe__oe \fus_oper_i_alu_logical0__oe__oe + connect \oper_i_alu_logical0__oe__ok \fus_oper_i_alu_logical0__oe__ok + connect \oper_i_alu_logical0__output_carry \fus_oper_i_alu_logical0__output_carry + connect \oper_i_alu_logical0__rc__ok \fus_oper_i_alu_logical0__rc__ok + connect \oper_i_alu_logical0__rc__rc \fus_oper_i_alu_logical0__rc__rc + connect \oper_i_alu_logical0__write_cr0 \fus_oper_i_alu_logical0__write_cr0 + connect \oper_i_alu_logical0__zero_a \fus_oper_i_alu_logical0__zero_a + connect \oper_i_alu_mul0__fn_unit \fus_oper_i_alu_mul0__fn_unit + connect \oper_i_alu_mul0__imm_data__data \fus_oper_i_alu_mul0__imm_data__data + connect \oper_i_alu_mul0__imm_data__ok \fus_oper_i_alu_mul0__imm_data__ok + connect \oper_i_alu_mul0__insn \fus_oper_i_alu_mul0__insn + connect \oper_i_alu_mul0__insn_type \fus_oper_i_alu_mul0__insn_type + connect \oper_i_alu_mul0__is_32bit \fus_oper_i_alu_mul0__is_32bit + connect \oper_i_alu_mul0__is_signed \fus_oper_i_alu_mul0__is_signed + connect \oper_i_alu_mul0__oe__oe \fus_oper_i_alu_mul0__oe__oe + connect \oper_i_alu_mul0__oe__ok \fus_oper_i_alu_mul0__oe__ok + connect \oper_i_alu_mul0__rc__ok \fus_oper_i_alu_mul0__rc__ok + connect \oper_i_alu_mul0__rc__rc \fus_oper_i_alu_mul0__rc__rc + connect \oper_i_alu_mul0__write_cr0 \fus_oper_i_alu_mul0__write_cr0 + connect \oper_i_alu_shift_rot0__fn_unit \fus_oper_i_alu_shift_rot0__fn_unit + connect \oper_i_alu_shift_rot0__imm_data__data \fus_oper_i_alu_shift_rot0__imm_data__data + connect \oper_i_alu_shift_rot0__imm_data__ok \fus_oper_i_alu_shift_rot0__imm_data__ok + connect \oper_i_alu_shift_rot0__input_carry \fus_oper_i_alu_shift_rot0__input_carry + connect \oper_i_alu_shift_rot0__input_cr \fus_oper_i_alu_shift_rot0__input_cr + connect \oper_i_alu_shift_rot0__insn \fus_oper_i_alu_shift_rot0__insn + connect \oper_i_alu_shift_rot0__insn_type \fus_oper_i_alu_shift_rot0__insn_type + connect \oper_i_alu_shift_rot0__is_32bit \fus_oper_i_alu_shift_rot0__is_32bit + connect \oper_i_alu_shift_rot0__is_signed \fus_oper_i_alu_shift_rot0__is_signed + connect \oper_i_alu_shift_rot0__oe__oe \fus_oper_i_alu_shift_rot0__oe__oe + connect \oper_i_alu_shift_rot0__oe__ok \fus_oper_i_alu_shift_rot0__oe__ok + connect \oper_i_alu_shift_rot0__output_carry \fus_oper_i_alu_shift_rot0__output_carry + connect \oper_i_alu_shift_rot0__output_cr \fus_oper_i_alu_shift_rot0__output_cr + connect \oper_i_alu_shift_rot0__rc__ok \fus_oper_i_alu_shift_rot0__rc__ok + connect \oper_i_alu_shift_rot0__rc__rc \fus_oper_i_alu_shift_rot0__rc__rc + connect \oper_i_alu_shift_rot0__write_cr0 \fus_oper_i_alu_shift_rot0__write_cr0 + connect \oper_i_alu_spr0__fn_unit \fus_oper_i_alu_spr0__fn_unit + connect \oper_i_alu_spr0__insn \fus_oper_i_alu_spr0__insn + connect \oper_i_alu_spr0__insn_type \fus_oper_i_alu_spr0__insn_type + connect \oper_i_alu_spr0__is_32bit \fus_oper_i_alu_spr0__is_32bit + connect \oper_i_alu_trap0__cia \fus_oper_i_alu_trap0__cia + connect \oper_i_alu_trap0__fn_unit \fus_oper_i_alu_trap0__fn_unit + connect \oper_i_alu_trap0__insn \fus_oper_i_alu_trap0__insn + connect \oper_i_alu_trap0__insn_type \fus_oper_i_alu_trap0__insn_type + connect \oper_i_alu_trap0__is_32bit \fus_oper_i_alu_trap0__is_32bit + connect \oper_i_alu_trap0__msr \fus_oper_i_alu_trap0__msr + connect \oper_i_alu_trap0__trapaddr \fus_oper_i_alu_trap0__trapaddr + connect \oper_i_alu_trap0__traptype \fus_oper_i_alu_trap0__traptype + connect \oper_i_ldst_ldst0__byte_reverse \fus_oper_i_ldst_ldst0__byte_reverse + connect \oper_i_ldst_ldst0__data_len \fus_oper_i_ldst_ldst0__data_len + connect \oper_i_ldst_ldst0__fn_unit \fus_oper_i_ldst_ldst0__fn_unit + connect \oper_i_ldst_ldst0__imm_data__data \fus_oper_i_ldst_ldst0__imm_data__data + connect \oper_i_ldst_ldst0__imm_data__ok \fus_oper_i_ldst_ldst0__imm_data__ok + connect \oper_i_ldst_ldst0__insn \fus_oper_i_ldst_ldst0__insn + connect \oper_i_ldst_ldst0__insn_type \fus_oper_i_ldst_ldst0__insn_type + connect \oper_i_ldst_ldst0__is_32bit \fus_oper_i_ldst_ldst0__is_32bit + connect \oper_i_ldst_ldst0__is_signed \fus_oper_i_ldst_ldst0__is_signed + connect \oper_i_ldst_ldst0__ldst_mode \fus_oper_i_ldst_ldst0__ldst_mode + connect \oper_i_ldst_ldst0__oe__oe \fus_oper_i_ldst_ldst0__oe__oe + connect \oper_i_ldst_ldst0__oe__ok \fus_oper_i_ldst_ldst0__oe__ok + connect \oper_i_ldst_ldst0__rc__ok \fus_oper_i_ldst_ldst0__rc__ok + connect \oper_i_ldst_ldst0__rc__rc \fus_oper_i_ldst_ldst0__rc__rc + connect \oper_i_ldst_ldst0__sign_extend \fus_oper_i_ldst_ldst0__sign_extend + connect \oper_i_ldst_ldst0__zero_a \fus_oper_i_ldst_ldst0__zero_a + connect \spr1_ok \fus_spr1_ok + connect \src1_i \fus_src1_i + connect \src1_i$30 \fus_src1_i$33 + connect \src1_i$33 \fus_src1_i$36 + connect \src1_i$36 \fus_src1_i$39 + connect \src1_i$39 \fus_src1_i$42 + connect \src1_i$42 \fus_src1_i$45 + connect \src1_i$45 \fus_src1_i$48 + connect \src1_i$48 \fus_src1_i$51 + connect \src1_i$51 \fus_src1_i$54 + connect \src1_i$74 \fus_src1_i$77 + connect \src2_i \fus_src2_i + connect \src2_i$52 \fus_src2_i$55 + connect \src2_i$53 \fus_src2_i$56 + connect \src2_i$54 \fus_src2_i$57 + connect \src2_i$55 \fus_src2_i$58 + connect \src2_i$56 \fus_src2_i$59 + connect \src2_i$57 \fus_src2_i$60 + connect \src2_i$58 \fus_src2_i$61 + connect \src2_i$77 \fus_src2_i$80 + connect \src2_i$79 \fus_src2_i$82 + connect \src3_i \fus_src3_i + connect \src3_i$59 \fus_src3_i$62 + connect \src3_i$60 \fus_src3_i$63 + connect \src3_i$61 \fus_src3_i$64 + connect \src3_i$62 \fus_src3_i$65 + connect \src3_i$63 \fus_src3_i$66 + connect \src3_i$67 \fus_src3_i$70 + connect \src3_i$71 \fus_src3_i$74 + connect \src3_i$75 \fus_src3_i$78 + connect \src3_i$76 \fus_src3_i$79 + connect \src4_i \fus_src4_i + connect \src4_i$64 \fus_src4_i$67 + connect \src4_i$65 \fus_src4_i$68 + connect \src4_i$68 \fus_src4_i$71 + connect \src4_i$78 \fus_src4_i$81 + connect \src5_i \fus_src5_i + connect \src5_i$66 \fus_src5_i$69 + connect \src5_i$72 \fus_src5_i$75 + connect \src6_i \fus_src6_i + connect \src6_i$73 \fus_src6_i$76 + connect \xer_ca_ok \fus_xer_ca_ok + connect \xer_ca_ok$120 \fus_xer_ca_ok$123 + connect \xer_ca_ok$121 \fus_xer_ca_ok$124 + connect \xer_ov_ok \fus_xer_ov_ok + connect \xer_ov_ok$124 \fus_xer_ov_ok$127 + connect \xer_ov_ok$125 \fus_xer_ov_ok$128 + connect \xer_ov_ok$126 \fus_xer_ov_ok$129 + connect \xer_so_ok \fus_xer_so_ok + connect \xer_so_ok$129 \fus_xer_so_ok$132 + connect \xer_so_ok$130 \fus_xer_so_ok$133 + connect \xer_so_ok$131 \fus_xer_so_ok$134 + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:42490.9-42508.4" + cell \int \int + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \dest1__addr \int_dest1__addr + connect \dest1__data_i \int_dest1__data_i + connect \dest1__wen \int_dest1__wen + connect \dmi__addr \dmi__addr + connect \dmi__data_o \dmi__data_o + connect \dmi__ren \dmi__ren + connect \src1__addr \int_src1__addr + connect \src1__data_o \int_src1__data_o + connect \src1__ren \int_src1__ren + connect \src2__addr \int_src2__addr + connect \src2__data_o \int_src2__data_o + connect \src2__ren \int_src2__ren + connect \src3__addr \int_src3__addr + connect \src3__data_o \int_src3__data_o + connect \src3__ren \int_src3__ren + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:42509.6-42533.4" + cell \l0 \l0 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \dbus__ack \dbus__ack + connect \dbus__adr \dbus__adr + connect \dbus__cyc \dbus__cyc + connect \dbus__dat_r \dbus__dat_r + connect \dbus__dat_w \dbus__dat_w + connect \dbus__err \dbus__err + connect \dbus__sel \dbus__sel + connect \dbus__stb \dbus__stb + connect \dbus__we \dbus__we + connect \ldst_port0_addr_exc_o \fus_ldst_port0_addr_exc_o + connect \ldst_port0_addr_i \fus_ldst_port0_addr_i + connect \ldst_port0_addr_i_ok \fus_ldst_port0_addr_i_ok + connect \ldst_port0_addr_ok_o \fus_ldst_port0_addr_ok_o + connect \ldst_port0_busy_o \fus_ldst_port0_busy_o + connect \ldst_port0_data_len \fus_ldst_port0_data_len + connect \ldst_port0_is_ld_i \fus_ldst_port0_is_ld_i + connect \ldst_port0_is_st_i \fus_ldst_port0_is_st_i + connect \ldst_port0_ld_data_o \fus_ldst_port0_ld_data_o + connect \ldst_port0_ld_data_o_ok \fus_ldst_port0_ld_data_o_ok + connect \ldst_port0_st_data_i \fus_ldst_port0_st_data_i + connect \ldst_port0_st_data_i_ok \fus_ldst_port0_st_data_i_ok + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:42534.18-42538.4" + cell \rdpick_CR_cr_a \rdpick_CR_cr_a + connect \en_o \rdpick_CR_cr_a_en_o + connect \i \rdpick_CR_cr_a_i + connect \o \rdpick_CR_cr_a_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:42539.18-42543.4" + cell \rdpick_CR_cr_b \rdpick_CR_cr_b + connect \en_o \rdpick_CR_cr_b_en_o + connect \i \rdpick_CR_cr_b_i + connect \o \rdpick_CR_cr_b_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:42544.18-42548.4" + cell \rdpick_CR_cr_c \rdpick_CR_cr_c + connect \en_o \rdpick_CR_cr_c_en_o + connect \i \rdpick_CR_cr_c_i + connect \o \rdpick_CR_cr_c_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:42549.21-42553.4" + cell \rdpick_CR_full_cr \rdpick_CR_full_cr + connect \en_o \rdpick_CR_full_cr_en_o + connect \i \rdpick_CR_full_cr_i + connect \o \rdpick_CR_full_cr_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:42554.21-42558.4" + cell \rdpick_FAST_fast1 \rdpick_FAST_fast1 + connect \en_o \rdpick_FAST_fast1_en_o + connect \i \rdpick_FAST_fast1_i + connect \o \rdpick_FAST_fast1_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:42559.21-42563.4" + cell \rdpick_FAST_fast2 \rdpick_FAST_fast2 + connect \en_o \rdpick_FAST_fast2_en_o + connect \i \rdpick_FAST_fast2_i + connect \o \rdpick_FAST_fast2_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:42564.17-42568.4" + cell \rdpick_INT_ra \rdpick_INT_ra + connect \en_o \rdpick_INT_ra_en_o + connect \i \rdpick_INT_ra_i + connect \o \rdpick_INT_ra_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:42569.17-42573.4" + cell \rdpick_INT_rb \rdpick_INT_rb + connect \en_o \rdpick_INT_rb_en_o + connect \i \rdpick_INT_rb_i + connect \o \rdpick_INT_rb_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:42574.17-42578.4" + cell \rdpick_INT_rc \rdpick_INT_rc + connect \en_o \rdpick_INT_rc_en_o + connect \i \rdpick_INT_rc_i + connect \o \rdpick_INT_rc_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:42579.19-42583.4" + cell \rdpick_SPR_spr1 \rdpick_SPR_spr1 + connect \en_o \rdpick_SPR_spr1_en_o + connect \i \rdpick_SPR_spr1_i + connect \o \rdpick_SPR_spr1_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:42584.21-42588.4" + cell \rdpick_XER_xer_ca \rdpick_XER_xer_ca + connect \en_o \rdpick_XER_xer_ca_en_o + connect \i \rdpick_XER_xer_ca_i + connect \o \rdpick_XER_xer_ca_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:42589.21-42593.4" + cell \rdpick_XER_xer_ov \rdpick_XER_xer_ov + connect \en_o \rdpick_XER_xer_ov_en_o + connect \i \rdpick_XER_xer_ov_i + connect \o \rdpick_XER_xer_ov_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:42594.21-42598.4" + cell \rdpick_XER_xer_so \rdpick_XER_xer_so + connect \en_o \rdpick_XER_xer_so_en_o + connect \i \rdpick_XER_xer_so_i + connect \o \rdpick_XER_xer_so_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:42599.7-42608.4" + cell \spr \spr + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \spr1__addr \spr_spr1__addr + connect \spr1__addr$1 \spr_spr1__addr$159 + connect \spr1__data_i \spr_spr1__data_i + connect \spr1__data_o \spr_spr1__data_o + connect \spr1__ren \spr_spr1__ren + connect \spr1__wen \spr_spr1__wen + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:42609.9-42622.4" + cell \state \state + connect \cia__data_o \cia__data_o + connect \cia__ren \cia__ren + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \data_i \data_i + connect \data_i$1 \state_data_i + connect \data_i$2 \state_data_i$158 + connect \msr__data_o \msr__data_o + connect \msr__ren \msr__ren + connect \state_nia_wen \state_nia_wen + connect \wen \wen + connect \wen$3 \state_wen + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:42623.18-42627.4" + cell \wrpick_CR_cr_a \wrpick_CR_cr_a + connect \en_o \wrpick_CR_cr_a_en_o + connect \i \wrpick_CR_cr_a_i + connect \o \wrpick_CR_cr_a_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:42628.21-42632.4" + cell \wrpick_CR_full_cr \wrpick_CR_full_cr + connect \en_o \wrpick_CR_full_cr_en_o + connect \i \wrpick_CR_full_cr_i + connect \o \wrpick_CR_full_cr_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:42633.21-42637.4" + cell \wrpick_FAST_fast1 \wrpick_FAST_fast1 + connect \en_o \wrpick_FAST_fast1_en_o + connect \i \wrpick_FAST_fast1_i + connect \o \wrpick_FAST_fast1_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:42638.16-42642.4" + cell \wrpick_INT_o \wrpick_INT_o + connect \en_o \wrpick_INT_o_en_o + connect \i \wrpick_INT_o_i + connect \o \wrpick_INT_o_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:42643.19-42647.4" + cell \wrpick_SPR_spr1 \wrpick_SPR_spr1 + connect \en_o \wrpick_SPR_spr1_en_o + connect \i \wrpick_SPR_spr1_i + connect \o \wrpick_SPR_spr1_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:42648.20-42652.4" + cell \wrpick_STATE_msr \wrpick_STATE_msr + connect \en_o \wrpick_STATE_msr_en_o + connect \i \wrpick_STATE_msr_i + connect \o \wrpick_STATE_msr_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:42653.20-42657.4" + cell \wrpick_STATE_nia \wrpick_STATE_nia + connect \en_o \wrpick_STATE_nia_en_o + connect \i \wrpick_STATE_nia_i + connect \o \wrpick_STATE_nia_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:42658.21-42662.4" + cell \wrpick_XER_xer_ca \wrpick_XER_xer_ca + connect \en_o \wrpick_XER_xer_ca_en_o + connect \i \wrpick_XER_xer_ca_i + connect \o \wrpick_XER_xer_ca_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:42663.21-42667.4" + cell \wrpick_XER_xer_ov \wrpick_XER_xer_ov + connect \en_o \wrpick_XER_xer_ov_en_o + connect \i \wrpick_XER_xer_ov_i + connect \o \wrpick_XER_xer_ov_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:42668.21-42672.4" + cell \wrpick_XER_xer_so \wrpick_XER_xer_so + connect \en_o \wrpick_XER_xer_so_en_o + connect \i \wrpick_XER_xer_so_i + connect \o \wrpick_XER_xer_so_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:42673.7-42690.4" + cell \xer \xer + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \data_i \xer_data_i + connect \data_i$1 \xer_data_i$154 + connect \data_i$3 \xer_data_i$156 + connect \full_rd__data_o \full_rd__data_o + connect \full_rd__ren \full_rd__ren + connect \src1__data_o \xer_src1__data_o + connect \src1__ren \xer_src1__ren + connect \src2__data_o \xer_src2__data_o + connect \src2__ren \xer_src2__ren + connect \src3__data_o \xer_src3__data_o + connect \src3__ren \xer_src3__ren + connect \wen \xer_wen + connect \wen$2 \xer_wen$155 + connect \wen$4 \xer_wen$157 + end + attribute \src "libresoc.v:35346.7-35346.20" + process $proc$libresoc.v:35346$2906 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:37364.7-37364.30" + process $proc$libresoc.v:37364$2907 + assign { } { } + assign $1\core_terminate_o[0:0] 1'0 + sync always + sync init + update \core_terminate_o $1\core_terminate_o[0:0] + end + attribute \src "libresoc.v:37377.13-37377.27" + process $proc$libresoc.v:37377$2908 + assign { } { } + assign $1\counter[1:0] 2'00 + sync always + sync init + update \counter $1\counter[1:0] + end + attribute \src "libresoc.v:38505.7-38505.34" + process $proc$libresoc.v:38505$2909 + assign { } { } + assign $1\dp_CR_cr_a_branch0_1[0:0] 1'0 + sync always + sync init + update \dp_CR_cr_a_branch0_1 $1\dp_CR_cr_a_branch0_1[0:0] + end + attribute \src "libresoc.v:38509.7-38509.30" + process $proc$libresoc.v:38509$2910 + assign { } { } + assign $1\dp_CR_cr_a_cr0_0[0:0] 1'0 + sync always + sync init + update \dp_CR_cr_a_cr0_0 $1\dp_CR_cr_a_cr0_0[0:0] + end + attribute \src "libresoc.v:38513.7-38513.30" + process $proc$libresoc.v:38513$2911 + assign { } { } + assign $1\dp_CR_cr_b_cr0_0[0:0] 1'0 + sync always + sync init + update \dp_CR_cr_b_cr0_0 $1\dp_CR_cr_b_cr0_0[0:0] + end + attribute \src "libresoc.v:38517.7-38517.30" + process $proc$libresoc.v:38517$2912 + assign { } { } + assign $1\dp_CR_cr_c_cr0_0[0:0] 1'0 + sync always + sync init + update \dp_CR_cr_c_cr0_0 $1\dp_CR_cr_c_cr0_0[0:0] + end + attribute \src "libresoc.v:38521.7-38521.33" + process $proc$libresoc.v:38521$2913 + assign { } { } + assign $1\dp_CR_full_cr_cr0_0[0:0] 1'0 + sync always + sync init + update \dp_CR_full_cr_cr0_0 $1\dp_CR_full_cr_cr0_0[0:0] + end + attribute \src "libresoc.v:38525.7-38525.37" + process $proc$libresoc.v:38525$2914 + assign { } { } + assign $1\dp_FAST_fast1_branch0_0[0:0] 1'0 + sync always + sync init + update \dp_FAST_fast1_branch0_0 $1\dp_FAST_fast1_branch0_0[0:0] + end + attribute \src "libresoc.v:38529.7-38529.34" + process $proc$libresoc.v:38529$2915 + assign { } { } + assign $1\dp_FAST_fast1_spr0_2[0:0] 1'0 + sync always + sync init + update \dp_FAST_fast1_spr0_2 $1\dp_FAST_fast1_spr0_2[0:0] + end + attribute \src "libresoc.v:38533.7-38533.35" + process $proc$libresoc.v:38533$2916 + assign { } { } + assign $1\dp_FAST_fast1_trap0_1[0:0] 1'0 + sync always + sync init + update \dp_FAST_fast1_trap0_1 $1\dp_FAST_fast1_trap0_1[0:0] + end + attribute \src "libresoc.v:38537.7-38537.37" + process $proc$libresoc.v:38537$2917 + assign { } { } + assign $1\dp_FAST_fast2_branch0_0[0:0] 1'0 + sync always + sync init + update \dp_FAST_fast2_branch0_0 $1\dp_FAST_fast2_branch0_0[0:0] + end + attribute \src "libresoc.v:38541.7-38541.35" + process $proc$libresoc.v:38541$2918 + assign { } { } + assign $1\dp_FAST_fast2_trap0_1[0:0] 1'0 + sync always + sync init + update \dp_FAST_fast2_trap0_1 $1\dp_FAST_fast2_trap0_1[0:0] + end + attribute \src "libresoc.v:38545.7-38545.30" + process $proc$libresoc.v:38545$2919 + assign { } { } + assign $1\dp_INT_ra_alu0_0[0:0] 1'0 + sync always + sync init + update \dp_INT_ra_alu0_0 $1\dp_INT_ra_alu0_0[0:0] + end + attribute \src "libresoc.v:38549.7-38549.29" + process $proc$libresoc.v:38549$2920 + assign { } { } + assign $1\dp_INT_ra_cr0_1[0:0] 1'0 + sync always + sync init + update \dp_INT_ra_cr0_1 $1\dp_INT_ra_cr0_1[0:0] + end + attribute \src "libresoc.v:38553.7-38553.30" + process $proc$libresoc.v:38553$2921 + assign { } { } + assign $1\dp_INT_ra_div0_5[0:0] 1'0 + sync always + sync init + update \dp_INT_ra_div0_5 $1\dp_INT_ra_div0_5[0:0] + end + attribute \src "libresoc.v:38557.7-38557.31" + process $proc$libresoc.v:38557$2922 + assign { } { } + assign $1\dp_INT_ra_ldst0_8[0:0] 1'0 + sync always + sync init + update \dp_INT_ra_ldst0_8 $1\dp_INT_ra_ldst0_8[0:0] + end + attribute \src "libresoc.v:38561.7-38561.34" + process $proc$libresoc.v:38561$2923 + assign { } { } + assign $1\dp_INT_ra_logical0_3[0:0] 1'0 + sync always + sync init + update \dp_INT_ra_logical0_3 $1\dp_INT_ra_logical0_3[0:0] + end + attribute \src "libresoc.v:38565.7-38565.30" + process $proc$libresoc.v:38565$2924 + assign { } { } + assign $1\dp_INT_ra_mul0_6[0:0] 1'0 + sync always + sync init + update \dp_INT_ra_mul0_6 $1\dp_INT_ra_mul0_6[0:0] + end + attribute \src "libresoc.v:38569.7-38569.35" + process $proc$libresoc.v:38569$2925 + assign { } { } + assign $1\dp_INT_ra_shiftrot0_7[0:0] 1'0 + sync always + sync init + update \dp_INT_ra_shiftrot0_7 $1\dp_INT_ra_shiftrot0_7[0:0] + end + attribute \src "libresoc.v:38573.7-38573.30" + process $proc$libresoc.v:38573$2926 + assign { } { } + assign $1\dp_INT_ra_spr0_4[0:0] 1'0 + sync always + sync init + update \dp_INT_ra_spr0_4 $1\dp_INT_ra_spr0_4[0:0] + end + attribute \src "libresoc.v:38577.7-38577.31" + process $proc$libresoc.v:38577$2927 + assign { } { } + assign $1\dp_INT_ra_trap0_2[0:0] 1'0 + sync always + sync init + update \dp_INT_ra_trap0_2 $1\dp_INT_ra_trap0_2[0:0] + end + attribute \src "libresoc.v:38581.7-38581.30" + process $proc$libresoc.v:38581$2928 + assign { } { } + assign $1\dp_INT_rb_alu0_0[0:0] 1'0 + sync always + sync init + update \dp_INT_rb_alu0_0 $1\dp_INT_rb_alu0_0[0:0] + end + attribute \src "libresoc.v:38585.7-38585.29" + process $proc$libresoc.v:38585$2929 + assign { } { } + assign $1\dp_INT_rb_cr0_1[0:0] 1'0 + sync always + sync init + update \dp_INT_rb_cr0_1 $1\dp_INT_rb_cr0_1[0:0] + end + attribute \src "libresoc.v:38589.7-38589.30" + process $proc$libresoc.v:38589$2930 + assign { } { } + assign $1\dp_INT_rb_div0_4[0:0] 1'0 + sync always + sync init + update \dp_INT_rb_div0_4 $1\dp_INT_rb_div0_4[0:0] + end + attribute \src "libresoc.v:38593.7-38593.31" + process $proc$libresoc.v:38593$2931 + assign { } { } + assign $1\dp_INT_rb_ldst0_7[0:0] 1'0 + sync always + sync init + update \dp_INT_rb_ldst0_7 $1\dp_INT_rb_ldst0_7[0:0] + end + attribute \src "libresoc.v:38597.7-38597.34" + process $proc$libresoc.v:38597$2932 + assign { } { } + assign $1\dp_INT_rb_logical0_3[0:0] 1'0 + sync always + sync init + update \dp_INT_rb_logical0_3 $1\dp_INT_rb_logical0_3[0:0] + end + attribute \src "libresoc.v:38601.7-38601.30" + process $proc$libresoc.v:38601$2933 + assign { } { } + assign $1\dp_INT_rb_mul0_5[0:0] 1'0 + sync always + sync init + update \dp_INT_rb_mul0_5 $1\dp_INT_rb_mul0_5[0:0] + end + attribute \src "libresoc.v:38605.7-38605.35" + process $proc$libresoc.v:38605$2934 + assign { } { } + assign $1\dp_INT_rb_shiftrot0_6[0:0] 1'0 + sync always + sync init + update \dp_INT_rb_shiftrot0_6 $1\dp_INT_rb_shiftrot0_6[0:0] + end + attribute \src "libresoc.v:38609.7-38609.31" + process $proc$libresoc.v:38609$2935 + assign { } { } + assign $1\dp_INT_rb_trap0_2[0:0] 1'0 + sync always + sync init + update \dp_INT_rb_trap0_2 $1\dp_INT_rb_trap0_2[0:0] + end + attribute \src "libresoc.v:38613.7-38613.31" + process $proc$libresoc.v:38613$2936 + assign { } { } + assign $1\dp_INT_rc_ldst0_1[0:0] 1'0 + sync always + sync init + update \dp_INT_rc_ldst0_1 $1\dp_INT_rc_ldst0_1[0:0] + end + attribute \src "libresoc.v:38617.7-38617.35" + process $proc$libresoc.v:38617$2937 + assign { } { } + assign $1\dp_INT_rc_shiftrot0_0[0:0] 1'0 + sync always + sync init + update \dp_INT_rc_shiftrot0_0 $1\dp_INT_rc_shiftrot0_0[0:0] + end + attribute \src "libresoc.v:38621.7-38621.32" + process $proc$libresoc.v:38621$2938 + assign { } { } + assign $1\dp_SPR_spr1_spr0_0[0:0] 1'0 + sync always + sync init + update \dp_SPR_spr1_spr0_0 $1\dp_SPR_spr1_spr0_0[0:0] + end + attribute \src "libresoc.v:38625.7-38625.34" + process $proc$libresoc.v:38625$2939 + assign { } { } + assign $1\dp_XER_xer_ca_alu0_0[0:0] 1'0 + sync always + sync init + update \dp_XER_xer_ca_alu0_0 $1\dp_XER_xer_ca_alu0_0[0:0] + end + attribute \src "libresoc.v:38629.7-38629.39" + process $proc$libresoc.v:38629$2940 + assign { } { } + assign $1\dp_XER_xer_ca_shiftrot0_2[0:0] 1'0 + sync always + sync init + update \dp_XER_xer_ca_shiftrot0_2 $1\dp_XER_xer_ca_shiftrot0_2[0:0] + end + attribute \src "libresoc.v:38633.7-38633.34" + process $proc$libresoc.v:38633$2941 + assign { } { } + assign $1\dp_XER_xer_ca_spr0_1[0:0] 1'0 + sync always + sync init + update \dp_XER_xer_ca_spr0_1 $1\dp_XER_xer_ca_spr0_1[0:0] + end + attribute \src "libresoc.v:38637.7-38637.34" + process $proc$libresoc.v:38637$2942 + assign { } { } + assign $1\dp_XER_xer_ov_spr0_0[0:0] 1'0 + sync always + sync init + update \dp_XER_xer_ov_spr0_0 $1\dp_XER_xer_ov_spr0_0[0:0] + end + attribute \src "libresoc.v:38641.7-38641.34" + process $proc$libresoc.v:38641$2943 + assign { } { } + assign $1\dp_XER_xer_so_alu0_0[0:0] 1'0 + sync always + sync init + update \dp_XER_xer_so_alu0_0 $1\dp_XER_xer_so_alu0_0[0:0] + end + attribute \src "libresoc.v:38645.7-38645.34" + process $proc$libresoc.v:38645$2944 + assign { } { } + assign $1\dp_XER_xer_so_div0_3[0:0] 1'0 + sync always + sync init + update \dp_XER_xer_so_div0_3 $1\dp_XER_xer_so_div0_3[0:0] + end + attribute \src "libresoc.v:38649.7-38649.38" + process $proc$libresoc.v:38649$2945 + assign { } { } + assign $1\dp_XER_xer_so_logical0_1[0:0] 1'0 + sync always + sync init + update \dp_XER_xer_so_logical0_1 $1\dp_XER_xer_so_logical0_1[0:0] + end + attribute \src "libresoc.v:38653.7-38653.34" + process $proc$libresoc.v:38653$2946 + assign { } { } + assign $1\dp_XER_xer_so_mul0_4[0:0] 1'0 + sync always + sync init + update \dp_XER_xer_so_mul0_4 $1\dp_XER_xer_so_mul0_4[0:0] + end + attribute \src "libresoc.v:38657.7-38657.39" + process $proc$libresoc.v:38657$2947 + assign { } { } + assign $1\dp_XER_xer_so_shiftrot0_5[0:0] 1'0 + sync always + sync init + update \dp_XER_xer_so_shiftrot0_5 $1\dp_XER_xer_so_shiftrot0_5[0:0] + end + attribute \src "libresoc.v:38661.7-38661.34" + process $proc$libresoc.v:38661$2948 + assign { } { } + assign $1\dp_XER_xer_so_spr0_2[0:0] 1'0 + sync always + sync init + update \dp_XER_xer_so_spr0_2 $1\dp_XER_xer_so_spr0_2[0:0] + end + attribute \src "libresoc.v:40718.7-40718.25" + process $proc$libresoc.v:40718$2949 + assign { } { } + assign $1\wr_pick_dly[0:0] 1'0 + sync always + sync init + update \wr_pick_dly $1\wr_pick_dly[0:0] + end + attribute \src "libresoc.v:40720.7-40720.32" + process $proc$libresoc.v:40720$2950 + assign { } { } + assign $0\wr_pick_dly$1007[0:0]$2951 1'0 + sync always + sync init + update \wr_pick_dly$1007 $0\wr_pick_dly$1007[0:0]$2951 + end + attribute \src "libresoc.v:40724.7-40724.32" + process $proc$libresoc.v:40724$2952 + assign { } { } + assign $0\wr_pick_dly$1025[0:0]$2953 1'0 + sync always + sync init + update \wr_pick_dly$1025 $0\wr_pick_dly$1025[0:0]$2953 + end + attribute \src "libresoc.v:40728.7-40728.32" + process $proc$libresoc.v:40728$2954 + assign { } { } + assign $0\wr_pick_dly$1047[0:0]$2955 1'0 + sync always + sync init + update \wr_pick_dly$1047 $0\wr_pick_dly$1047[0:0]$2955 + end + attribute \src "libresoc.v:40732.7-40732.32" + process $proc$libresoc.v:40732$2956 + assign { } { } + assign $0\wr_pick_dly$1067[0:0]$2957 1'0 + sync always + sync init + update \wr_pick_dly$1067 $0\wr_pick_dly$1067[0:0]$2957 + end + attribute \src "libresoc.v:40736.7-40736.32" + process $proc$libresoc.v:40736$2958 + assign { } { } + assign $0\wr_pick_dly$1087[0:0]$2959 1'0 + sync always + sync init + update \wr_pick_dly$1087 $0\wr_pick_dly$1087[0:0]$2959 + end + attribute \src "libresoc.v:40740.7-40740.32" + process $proc$libresoc.v:40740$2960 + assign { } { } + assign $0\wr_pick_dly$1106[0:0]$2961 1'0 + sync always + sync init + update \wr_pick_dly$1106 $0\wr_pick_dly$1106[0:0]$2961 + end + attribute \src "libresoc.v:40744.7-40744.32" + process $proc$libresoc.v:40744$2962 + assign { } { } + assign $0\wr_pick_dly$1124[0:0]$2963 1'0 + sync always + sync init + update \wr_pick_dly$1124 $0\wr_pick_dly$1124[0:0]$2963 + end + attribute \src "libresoc.v:40748.7-40748.32" + process $proc$libresoc.v:40748$2964 + assign { } { } + assign $0\wr_pick_dly$1197[0:0]$2965 1'0 + sync always + sync init + update \wr_pick_dly$1197 $0\wr_pick_dly$1197[0:0]$2965 + end + attribute \src "libresoc.v:40752.7-40752.32" + process $proc$libresoc.v:40752$2966 + assign { } { } + assign $0\wr_pick_dly$1225[0:0]$2967 1'0 + sync always + sync init + update \wr_pick_dly$1225 $0\wr_pick_dly$1225[0:0]$2967 + end + attribute \src "libresoc.v:40756.7-40756.32" + process $proc$libresoc.v:40756$2968 + assign { } { } + assign $0\wr_pick_dly$1245[0:0]$2969 1'0 + sync always + sync init + update \wr_pick_dly$1245 $0\wr_pick_dly$1245[0:0]$2969 + end + attribute \src "libresoc.v:40760.7-40760.32" + process $proc$libresoc.v:40760$2970 + assign { } { } + assign $0\wr_pick_dly$1265[0:0]$2971 1'0 + sync always + sync init + update \wr_pick_dly$1265 $0\wr_pick_dly$1265[0:0]$2971 + end + attribute \src "libresoc.v:40764.7-40764.32" + process $proc$libresoc.v:40764$2972 + assign { } { } + assign $0\wr_pick_dly$1285[0:0]$2973 1'0 + sync always + sync init + update \wr_pick_dly$1285 $0\wr_pick_dly$1285[0:0]$2973 + end + attribute \src "libresoc.v:40768.7-40768.32" + process $proc$libresoc.v:40768$2974 + assign { } { } + assign $0\wr_pick_dly$1305[0:0]$2975 1'0 + sync always + sync init + update \wr_pick_dly$1305 $0\wr_pick_dly$1305[0:0]$2975 + end + attribute \src "libresoc.v:40772.7-40772.32" + process $proc$libresoc.v:40772$2976 + assign { } { } + assign $0\wr_pick_dly$1325[0:0]$2977 1'0 + sync always + sync init + update \wr_pick_dly$1325 $0\wr_pick_dly$1325[0:0]$2977 + end + attribute \src "libresoc.v:40776.7-40776.32" + process $proc$libresoc.v:40776$2978 + assign { } { } + assign $0\wr_pick_dly$1372[0:0]$2979 1'0 + sync always + sync init + update \wr_pick_dly$1372 $0\wr_pick_dly$1372[0:0]$2979 + end + attribute \src "libresoc.v:40780.7-40780.32" + process $proc$libresoc.v:40780$2980 + assign { } { } + assign $0\wr_pick_dly$1388[0:0]$2981 1'0 + sync always + sync init + update \wr_pick_dly$1388 $0\wr_pick_dly$1388[0:0]$2981 + end + attribute \src "libresoc.v:40784.7-40784.32" + process $proc$libresoc.v:40784$2982 + assign { } { } + assign $0\wr_pick_dly$1404[0:0]$2983 1'0 + sync always + sync init + update \wr_pick_dly$1404 $0\wr_pick_dly$1404[0:0]$2983 + end + attribute \src "libresoc.v:40788.7-40788.32" + process $proc$libresoc.v:40788$2984 + assign { } { } + assign $0\wr_pick_dly$1438[0:0]$2985 1'0 + sync always + sync init + update \wr_pick_dly$1438 $0\wr_pick_dly$1438[0:0]$2985 + end + attribute \src "libresoc.v:40792.7-40792.32" + process $proc$libresoc.v:40792$2986 + assign { } { } + assign $0\wr_pick_dly$1454[0:0]$2987 1'0 + sync always + sync init + update \wr_pick_dly$1454 $0\wr_pick_dly$1454[0:0]$2987 + end + attribute \src "libresoc.v:40796.7-40796.32" + process $proc$libresoc.v:40796$2988 + assign { } { } + assign $0\wr_pick_dly$1470[0:0]$2989 1'0 + sync always + sync init + update \wr_pick_dly$1470 $0\wr_pick_dly$1470[0:0]$2989 + end + attribute \src "libresoc.v:40800.7-40800.32" + process $proc$libresoc.v:40800$2990 + assign { } { } + assign $0\wr_pick_dly$1486[0:0]$2991 1'0 + sync always + sync init + update \wr_pick_dly$1486 $0\wr_pick_dly$1486[0:0]$2991 + end + attribute \src "libresoc.v:40804.7-40804.32" + process $proc$libresoc.v:40804$2992 + assign { } { } + assign $0\wr_pick_dly$1522[0:0]$2993 1'0 + sync always + sync init + update \wr_pick_dly$1522 $0\wr_pick_dly$1522[0:0]$2993 + end + attribute \src "libresoc.v:40808.7-40808.32" + process $proc$libresoc.v:40808$2994 + assign { } { } + assign $0\wr_pick_dly$1538[0:0]$2995 1'0 + sync always + sync init + update \wr_pick_dly$1538 $0\wr_pick_dly$1538[0:0]$2995 + end + attribute \src "libresoc.v:40812.7-40812.32" + process $proc$libresoc.v:40812$2996 + assign { } { } + assign $0\wr_pick_dly$1554[0:0]$2997 1'0 + sync always + sync init + update \wr_pick_dly$1554 $0\wr_pick_dly$1554[0:0]$2997 + end + attribute \src "libresoc.v:40816.7-40816.32" + process $proc$libresoc.v:40816$2998 + assign { } { } + assign $0\wr_pick_dly$1570[0:0]$2999 1'0 + sync always + sync init + update \wr_pick_dly$1570 $0\wr_pick_dly$1570[0:0]$2999 + end + attribute \src "libresoc.v:40820.7-40820.32" + process $proc$libresoc.v:40820$3000 + assign { } { } + assign $0\wr_pick_dly$1612[0:0]$3001 1'0 + sync always + sync init + update \wr_pick_dly$1612 $0\wr_pick_dly$1612[0:0]$3001 + end + attribute \src "libresoc.v:40824.7-40824.32" + process $proc$libresoc.v:40824$3002 + assign { } { } + assign $0\wr_pick_dly$1631[0:0]$3003 1'0 + sync always + sync init + update \wr_pick_dly$1631 $0\wr_pick_dly$1631[0:0]$3003 + end + attribute \src "libresoc.v:40828.7-40828.32" + process $proc$libresoc.v:40828$3004 + assign { } { } + assign $0\wr_pick_dly$1647[0:0]$3005 1'0 + sync always + sync init + update \wr_pick_dly$1647 $0\wr_pick_dly$1647[0:0]$3005 + end + attribute \src "libresoc.v:40832.7-40832.32" + process $proc$libresoc.v:40832$3006 + assign { } { } + assign $0\wr_pick_dly$1663[0:0]$3007 1'0 + sync always + sync init + update \wr_pick_dly$1663 $0\wr_pick_dly$1663[0:0]$3007 + end + attribute \src "libresoc.v:40836.7-40836.32" + process $proc$libresoc.v:40836$3008 + assign { } { } + assign $0\wr_pick_dly$1679[0:0]$3009 1'0 + sync always + sync init + update \wr_pick_dly$1679 $0\wr_pick_dly$1679[0:0]$3009 + end + attribute \src "libresoc.v:40840.7-40840.32" + process $proc$libresoc.v:40840$3010 + assign { } { } + assign $0\wr_pick_dly$1723[0:0]$3011 1'0 + sync always + sync init + update \wr_pick_dly$1723 $0\wr_pick_dly$1723[0:0]$3011 + end + attribute \src "libresoc.v:40844.7-40844.32" + process $proc$libresoc.v:40844$3012 + assign { } { } + assign $0\wr_pick_dly$1739[0:0]$3013 1'0 + sync always + sync init + update \wr_pick_dly$1739 $0\wr_pick_dly$1739[0:0]$3013 + end + attribute \src "libresoc.v:40848.7-40848.32" + process $proc$libresoc.v:40848$3014 + assign { } { } + assign $0\wr_pick_dly$1763[0:0]$3015 1'0 + sync always + sync init + update \wr_pick_dly$1763 $0\wr_pick_dly$1763[0:0]$3015 + end + attribute \src "libresoc.v:40852.7-40852.32" + process $proc$libresoc.v:40852$3016 + assign { } { } + assign $0\wr_pick_dly$1783[0:0]$3017 1'0 + sync always + sync init + update \wr_pick_dly$1783 $0\wr_pick_dly$1783[0:0]$3017 + end + attribute \src "libresoc.v:40856.7-40856.31" + process $proc$libresoc.v:40856$3018 + assign { } { } + assign $0\wr_pick_dly$967[0:0]$3019 1'0 + sync always + sync init + update \wr_pick_dly$967 $0\wr_pick_dly$967[0:0]$3019 + end + attribute \src "libresoc.v:40860.7-40860.31" + process $proc$libresoc.v:40860$3020 + assign { } { } + assign $0\wr_pick_dly$986[0:0]$3021 1'0 + sync always + sync init + update \wr_pick_dly$986 $0\wr_pick_dly$986[0:0]$3021 + end + attribute \src "libresoc.v:41822.3-41823.51" + process $proc$libresoc.v:41822$2246 + assign { } { } + assign $0\wr_pick_dly$1783[0:0]$2247 \wr_pick_dly$1783$next + sync posedge \coresync_clk + update \wr_pick_dly$1783 $0\wr_pick_dly$1783[0:0]$2247 + end + attribute \src "libresoc.v:41824.3-41825.51" + process $proc$libresoc.v:41824$2248 + assign { } { } + assign $0\wr_pick_dly$1763[0:0]$2249 \wr_pick_dly$1763$next + sync posedge \coresync_clk + update \wr_pick_dly$1763 $0\wr_pick_dly$1763[0:0]$2249 + end + attribute \src "libresoc.v:41826.3-41827.51" + process $proc$libresoc.v:41826$2250 + assign { } { } + assign $0\wr_pick_dly$1739[0:0]$2251 \wr_pick_dly$1739$next + sync posedge \coresync_clk + update \wr_pick_dly$1739 $0\wr_pick_dly$1739[0:0]$2251 + end + attribute \src "libresoc.v:41828.3-41829.51" + process $proc$libresoc.v:41828$2252 + assign { } { } + assign $0\wr_pick_dly$1723[0:0]$2253 \wr_pick_dly$1723$next + sync posedge \coresync_clk + update \wr_pick_dly$1723 $0\wr_pick_dly$1723[0:0]$2253 + end + attribute \src "libresoc.v:41830.3-41831.51" + process $proc$libresoc.v:41830$2254 + assign { } { } + assign $0\wr_pick_dly$1679[0:0]$2255 \wr_pick_dly$1679$next + sync posedge \coresync_clk + update \wr_pick_dly$1679 $0\wr_pick_dly$1679[0:0]$2255 + end + attribute \src "libresoc.v:41832.3-41833.51" + process $proc$libresoc.v:41832$2256 + assign { } { } + assign $0\wr_pick_dly$1663[0:0]$2257 \wr_pick_dly$1663$next + sync posedge \coresync_clk + update \wr_pick_dly$1663 $0\wr_pick_dly$1663[0:0]$2257 + end + attribute \src "libresoc.v:41834.3-41835.51" + process $proc$libresoc.v:41834$2258 + assign { } { } + assign $0\wr_pick_dly$1647[0:0]$2259 \wr_pick_dly$1647$next + sync posedge \coresync_clk + update \wr_pick_dly$1647 $0\wr_pick_dly$1647[0:0]$2259 + end + attribute \src "libresoc.v:41836.3-41837.51" + process $proc$libresoc.v:41836$2260 + assign { } { } + assign $0\wr_pick_dly$1631[0:0]$2261 \wr_pick_dly$1631$next + sync posedge \coresync_clk + update \wr_pick_dly$1631 $0\wr_pick_dly$1631[0:0]$2261 + end + attribute \src "libresoc.v:41838.3-41839.51" + process $proc$libresoc.v:41838$2262 + assign { } { } + assign $0\wr_pick_dly$1612[0:0]$2263 \wr_pick_dly$1612$next + sync posedge \coresync_clk + update \wr_pick_dly$1612 $0\wr_pick_dly$1612[0:0]$2263 + end + attribute \src "libresoc.v:41840.3-41841.51" + process $proc$libresoc.v:41840$2264 + assign { } { } + assign $0\wr_pick_dly$1570[0:0]$2265 \wr_pick_dly$1570$next + sync posedge \coresync_clk + update \wr_pick_dly$1570 $0\wr_pick_dly$1570[0:0]$2265 + end + attribute \src "libresoc.v:41842.3-41843.51" + process $proc$libresoc.v:41842$2266 + assign { } { } + assign $0\wr_pick_dly$1554[0:0]$2267 \wr_pick_dly$1554$next + sync posedge \coresync_clk + update \wr_pick_dly$1554 $0\wr_pick_dly$1554[0:0]$2267 + end + attribute \src "libresoc.v:41844.3-41845.51" + process $proc$libresoc.v:41844$2268 + assign { } { } + assign $0\wr_pick_dly$1538[0:0]$2269 \wr_pick_dly$1538$next + sync posedge \coresync_clk + update \wr_pick_dly$1538 $0\wr_pick_dly$1538[0:0]$2269 + end + attribute \src "libresoc.v:41846.3-41847.51" + process $proc$libresoc.v:41846$2270 + assign { } { } + assign $0\wr_pick_dly$1522[0:0]$2271 \wr_pick_dly$1522$next + sync posedge \coresync_clk + update \wr_pick_dly$1522 $0\wr_pick_dly$1522[0:0]$2271 + end + attribute \src "libresoc.v:41848.3-41849.51" + process $proc$libresoc.v:41848$2272 + assign { } { } + assign $0\wr_pick_dly$1486[0:0]$2273 \wr_pick_dly$1486$next + sync posedge \coresync_clk + update \wr_pick_dly$1486 $0\wr_pick_dly$1486[0:0]$2273 + end + attribute \src "libresoc.v:41850.3-41851.51" + process $proc$libresoc.v:41850$2274 + assign { } { } + assign $0\wr_pick_dly$1470[0:0]$2275 \wr_pick_dly$1470$next + sync posedge \coresync_clk + update \wr_pick_dly$1470 $0\wr_pick_dly$1470[0:0]$2275 + end + attribute \src "libresoc.v:41852.3-41853.51" + process $proc$libresoc.v:41852$2276 + assign { } { } + assign $0\wr_pick_dly$1454[0:0]$2277 \wr_pick_dly$1454$next + sync posedge \coresync_clk + update \wr_pick_dly$1454 $0\wr_pick_dly$1454[0:0]$2277 + end + attribute \src "libresoc.v:41854.3-41855.51" + process $proc$libresoc.v:41854$2278 + assign { } { } + assign $0\wr_pick_dly$1438[0:0]$2279 \wr_pick_dly$1438$next + sync posedge \coresync_clk + update \wr_pick_dly$1438 $0\wr_pick_dly$1438[0:0]$2279 + end + attribute \src "libresoc.v:41856.3-41857.51" + process $proc$libresoc.v:41856$2280 + assign { } { } + assign $0\wr_pick_dly$1404[0:0]$2281 \wr_pick_dly$1404$next + sync posedge \coresync_clk + update \wr_pick_dly$1404 $0\wr_pick_dly$1404[0:0]$2281 + end + attribute \src "libresoc.v:41858.3-41859.51" + process $proc$libresoc.v:41858$2282 + assign { } { } + assign $0\wr_pick_dly$1388[0:0]$2283 \wr_pick_dly$1388$next + sync posedge \coresync_clk + update \wr_pick_dly$1388 $0\wr_pick_dly$1388[0:0]$2283 + end + attribute \src "libresoc.v:41860.3-41861.51" + process $proc$libresoc.v:41860$2284 + assign { } { } + assign $0\wr_pick_dly$1372[0:0]$2285 \wr_pick_dly$1372$next + sync posedge \coresync_clk + update \wr_pick_dly$1372 $0\wr_pick_dly$1372[0:0]$2285 + end + attribute \src "libresoc.v:41862.3-41863.51" + process $proc$libresoc.v:41862$2286 + assign { } { } + assign $0\wr_pick_dly$1325[0:0]$2287 \wr_pick_dly$1325$next + sync posedge \coresync_clk + update \wr_pick_dly$1325 $0\wr_pick_dly$1325[0:0]$2287 + end + attribute \src "libresoc.v:41864.3-41865.51" + process $proc$libresoc.v:41864$2288 + assign { } { } + assign $0\wr_pick_dly$1305[0:0]$2289 \wr_pick_dly$1305$next + sync posedge \coresync_clk + update \wr_pick_dly$1305 $0\wr_pick_dly$1305[0:0]$2289 + end + attribute \src "libresoc.v:41866.3-41867.51" + process $proc$libresoc.v:41866$2290 + assign { } { } + assign $0\wr_pick_dly$1285[0:0]$2291 \wr_pick_dly$1285$next + sync posedge \coresync_clk + update \wr_pick_dly$1285 $0\wr_pick_dly$1285[0:0]$2291 + end + attribute \src "libresoc.v:41868.3-41869.51" + process $proc$libresoc.v:41868$2292 + assign { } { } + assign $0\wr_pick_dly$1265[0:0]$2293 \wr_pick_dly$1265$next + sync posedge \coresync_clk + update \wr_pick_dly$1265 $0\wr_pick_dly$1265[0:0]$2293 + end + attribute \src "libresoc.v:41870.3-41871.51" + process $proc$libresoc.v:41870$2294 + assign { } { } + assign $0\wr_pick_dly$1245[0:0]$2295 \wr_pick_dly$1245$next + sync posedge \coresync_clk + update \wr_pick_dly$1245 $0\wr_pick_dly$1245[0:0]$2295 + end + attribute \src "libresoc.v:41872.3-41873.51" + process $proc$libresoc.v:41872$2296 + assign { } { } + assign $0\wr_pick_dly$1225[0:0]$2297 \wr_pick_dly$1225$next + sync posedge \coresync_clk + update \wr_pick_dly$1225 $0\wr_pick_dly$1225[0:0]$2297 + end + attribute \src "libresoc.v:41874.3-41875.51" + process $proc$libresoc.v:41874$2298 + assign { } { } + assign $0\wr_pick_dly$1197[0:0]$2299 \wr_pick_dly$1197$next + sync posedge \coresync_clk + update \wr_pick_dly$1197 $0\wr_pick_dly$1197[0:0]$2299 + end + attribute \src "libresoc.v:41876.3-41877.51" + process $proc$libresoc.v:41876$2300 + assign { } { } + assign $0\wr_pick_dly$1124[0:0]$2301 \wr_pick_dly$1124$next + sync posedge \coresync_clk + update \wr_pick_dly$1124 $0\wr_pick_dly$1124[0:0]$2301 + end + attribute \src "libresoc.v:41878.3-41879.51" + process $proc$libresoc.v:41878$2302 + assign { } { } + assign $0\wr_pick_dly$1106[0:0]$2303 \wr_pick_dly$1106$next + sync posedge \coresync_clk + update \wr_pick_dly$1106 $0\wr_pick_dly$1106[0:0]$2303 + end + attribute \src "libresoc.v:41880.3-41881.51" + process $proc$libresoc.v:41880$2304 + assign { } { } + assign $0\wr_pick_dly$1087[0:0]$2305 \wr_pick_dly$1087$next + sync posedge \coresync_clk + update \wr_pick_dly$1087 $0\wr_pick_dly$1087[0:0]$2305 + end + attribute \src "libresoc.v:41882.3-41883.51" + process $proc$libresoc.v:41882$2306 + assign { } { } + assign $0\wr_pick_dly$1067[0:0]$2307 \wr_pick_dly$1067$next + sync posedge \coresync_clk + update \wr_pick_dly$1067 $0\wr_pick_dly$1067[0:0]$2307 + end + attribute \src "libresoc.v:41884.3-41885.51" + process $proc$libresoc.v:41884$2308 + assign { } { } + assign $0\wr_pick_dly$1047[0:0]$2309 \wr_pick_dly$1047$next + sync posedge \coresync_clk + update \wr_pick_dly$1047 $0\wr_pick_dly$1047[0:0]$2309 + end + attribute \src "libresoc.v:41886.3-41887.51" + process $proc$libresoc.v:41886$2310 + assign { } { } + assign $0\wr_pick_dly$1025[0:0]$2311 \wr_pick_dly$1025$next + sync posedge \coresync_clk + update \wr_pick_dly$1025 $0\wr_pick_dly$1025[0:0]$2311 + end + attribute \src "libresoc.v:41888.3-41889.51" + process $proc$libresoc.v:41888$2312 + assign { } { } + assign $0\wr_pick_dly$1007[0:0]$2313 \wr_pick_dly$1007$next + sync posedge \coresync_clk + update \wr_pick_dly$1007 $0\wr_pick_dly$1007[0:0]$2313 + end + attribute \src "libresoc.v:41890.3-41891.49" + process $proc$libresoc.v:41890$2314 + assign { } { } + assign $0\wr_pick_dly$986[0:0]$2315 \wr_pick_dly$986$next + sync posedge \coresync_clk + update \wr_pick_dly$986 $0\wr_pick_dly$986[0:0]$2315 + end + attribute \src "libresoc.v:41892.3-41893.49" + process $proc$libresoc.v:41892$2316 + assign { } { } + assign $0\wr_pick_dly$967[0:0]$2317 \wr_pick_dly$967$next + sync posedge \coresync_clk + update \wr_pick_dly$967 $0\wr_pick_dly$967[0:0]$2317 + end + attribute \src "libresoc.v:41894.3-41895.39" + process $proc$libresoc.v:41894$2318 + assign { } { } + assign $0\wr_pick_dly[0:0] \wr_pick_dly$next + sync posedge \coresync_clk + update \wr_pick_dly $0\wr_pick_dly[0:0] + end + attribute \src "libresoc.v:41896.3-41897.53" + process $proc$libresoc.v:41896$2319 + assign { } { } + assign $0\dp_SPR_spr1_spr0_0[0:0] \dp_SPR_spr1_spr0_0$next + sync posedge \coresync_clk + update \dp_SPR_spr1_spr0_0 $0\dp_SPR_spr1_spr0_0[0:0] + end + attribute \src "libresoc.v:41898.3-41899.59" + process $proc$libresoc.v:41898$2320 + assign { } { } + assign $0\dp_FAST_fast2_trap0_1[0:0] \dp_FAST_fast2_trap0_1$next + sync posedge \coresync_clk + update \dp_FAST_fast2_trap0_1 $0\dp_FAST_fast2_trap0_1[0:0] + end + attribute \src "libresoc.v:41900.3-41901.63" + process $proc$libresoc.v:41900$2321 + assign { } { } + assign $0\dp_FAST_fast2_branch0_0[0:0] \dp_FAST_fast2_branch0_0$next + sync posedge \coresync_clk + update \dp_FAST_fast2_branch0_0 $0\dp_FAST_fast2_branch0_0[0:0] + end + attribute \src "libresoc.v:41902.3-41903.57" + process $proc$libresoc.v:41902$2322 + assign { } { } + assign $0\dp_FAST_fast1_spr0_2[0:0] \dp_FAST_fast1_spr0_2$next + sync posedge \coresync_clk + update \dp_FAST_fast1_spr0_2 $0\dp_FAST_fast1_spr0_2[0:0] + end + attribute \src "libresoc.v:41904.3-41905.59" + process $proc$libresoc.v:41904$2323 + assign { } { } + assign $0\dp_FAST_fast1_trap0_1[0:0] \dp_FAST_fast1_trap0_1$next + sync posedge \coresync_clk + update \dp_FAST_fast1_trap0_1 $0\dp_FAST_fast1_trap0_1[0:0] + end + attribute \src "libresoc.v:41906.3-41907.63" + process $proc$libresoc.v:41906$2324 + assign { } { } + assign $0\dp_FAST_fast1_branch0_0[0:0] \dp_FAST_fast1_branch0_0$next + sync posedge \coresync_clk + update \dp_FAST_fast1_branch0_0 $0\dp_FAST_fast1_branch0_0[0:0] + end + attribute \src "libresoc.v:41908.3-41909.49" + process $proc$libresoc.v:41908$2325 + assign { } { } + assign $0\dp_CR_cr_c_cr0_0[0:0] \dp_CR_cr_c_cr0_0$next + sync posedge \coresync_clk + update \dp_CR_cr_c_cr0_0 $0\dp_CR_cr_c_cr0_0[0:0] + end + attribute \src "libresoc.v:41910.3-41911.49" + process $proc$libresoc.v:41910$2326 + assign { } { } + assign $0\dp_CR_cr_b_cr0_0[0:0] \dp_CR_cr_b_cr0_0$next + sync posedge \coresync_clk + update \dp_CR_cr_b_cr0_0 $0\dp_CR_cr_b_cr0_0[0:0] + end + attribute \src "libresoc.v:41912.3-41913.57" + process $proc$libresoc.v:41912$2327 + assign { } { } + assign $0\dp_CR_cr_a_branch0_1[0:0] \dp_CR_cr_a_branch0_1$next + sync posedge \coresync_clk + update \dp_CR_cr_a_branch0_1 $0\dp_CR_cr_a_branch0_1[0:0] + end + attribute \src "libresoc.v:41914.3-41915.49" + process $proc$libresoc.v:41914$2328 + assign { } { } + assign $0\dp_CR_cr_a_cr0_0[0:0] \dp_CR_cr_a_cr0_0$next + sync posedge \coresync_clk + update \dp_CR_cr_a_cr0_0 $0\dp_CR_cr_a_cr0_0[0:0] + end + attribute \src "libresoc.v:41916.3-41917.55" + process $proc$libresoc.v:41916$2329 + assign { } { } + assign $0\dp_CR_full_cr_cr0_0[0:0] \dp_CR_full_cr_cr0_0$next + sync posedge \coresync_clk + update \dp_CR_full_cr_cr0_0 $0\dp_CR_full_cr_cr0_0[0:0] + end + attribute \src "libresoc.v:41918.3-41919.57" + process $proc$libresoc.v:41918$2330 + assign { } { } + assign $0\dp_XER_xer_ov_spr0_0[0:0] \dp_XER_xer_ov_spr0_0$next + sync posedge \coresync_clk + update \dp_XER_xer_ov_spr0_0 $0\dp_XER_xer_ov_spr0_0[0:0] + end + attribute \src "libresoc.v:41920.3-41921.67" + process $proc$libresoc.v:41920$2331 + assign { } { } + assign $0\dp_XER_xer_ca_shiftrot0_2[0:0] \dp_XER_xer_ca_shiftrot0_2$next + sync posedge \coresync_clk + update \dp_XER_xer_ca_shiftrot0_2 $0\dp_XER_xer_ca_shiftrot0_2[0:0] + end + attribute \src "libresoc.v:41922.3-41923.57" + process $proc$libresoc.v:41922$2332 + assign { } { } + assign $0\dp_XER_xer_ca_spr0_1[0:0] \dp_XER_xer_ca_spr0_1$next + sync posedge \coresync_clk + update \dp_XER_xer_ca_spr0_1 $0\dp_XER_xer_ca_spr0_1[0:0] + end + attribute \src "libresoc.v:41924.3-41925.57" + process $proc$libresoc.v:41924$2333 + assign { } { } + assign $0\dp_XER_xer_ca_alu0_0[0:0] \dp_XER_xer_ca_alu0_0$next + sync posedge \coresync_clk + update \dp_XER_xer_ca_alu0_0 $0\dp_XER_xer_ca_alu0_0[0:0] + end + attribute \src "libresoc.v:41926.3-41927.67" + process $proc$libresoc.v:41926$2334 + assign { } { } + assign $0\dp_XER_xer_so_shiftrot0_5[0:0] \dp_XER_xer_so_shiftrot0_5$next + sync posedge \coresync_clk + update \dp_XER_xer_so_shiftrot0_5 $0\dp_XER_xer_so_shiftrot0_5[0:0] + end + attribute \src "libresoc.v:41928.3-41929.57" + process $proc$libresoc.v:41928$2335 + assign { } { } + assign $0\dp_XER_xer_so_mul0_4[0:0] \dp_XER_xer_so_mul0_4$next + sync posedge \coresync_clk + update \dp_XER_xer_so_mul0_4 $0\dp_XER_xer_so_mul0_4[0:0] + end + attribute \src "libresoc.v:41930.3-41931.57" + process $proc$libresoc.v:41930$2336 + assign { } { } + assign $0\dp_XER_xer_so_div0_3[0:0] \dp_XER_xer_so_div0_3$next + sync posedge \coresync_clk + update \dp_XER_xer_so_div0_3 $0\dp_XER_xer_so_div0_3[0:0] + end + attribute \src "libresoc.v:41932.3-41933.57" + process $proc$libresoc.v:41932$2337 + assign { } { } + assign $0\dp_XER_xer_so_spr0_2[0:0] \dp_XER_xer_so_spr0_2$next + sync posedge \coresync_clk + update \dp_XER_xer_so_spr0_2 $0\dp_XER_xer_so_spr0_2[0:0] + end + attribute \src "libresoc.v:41934.3-41935.65" + process $proc$libresoc.v:41934$2338 + assign { } { } + assign $0\dp_XER_xer_so_logical0_1[0:0] \dp_XER_xer_so_logical0_1$next + sync posedge \coresync_clk + update \dp_XER_xer_so_logical0_1 $0\dp_XER_xer_so_logical0_1[0:0] + end + attribute \src "libresoc.v:41936.3-41937.57" + process $proc$libresoc.v:41936$2339 + assign { } { } + assign $0\dp_XER_xer_so_alu0_0[0:0] \dp_XER_xer_so_alu0_0$next + sync posedge \coresync_clk + update \dp_XER_xer_so_alu0_0 $0\dp_XER_xer_so_alu0_0[0:0] + end + attribute \src "libresoc.v:41938.3-41939.51" + process $proc$libresoc.v:41938$2340 + assign { } { } + assign $0\dp_INT_rc_ldst0_1[0:0] \dp_INT_rc_ldst0_1$next + sync posedge \coresync_clk + update \dp_INT_rc_ldst0_1 $0\dp_INT_rc_ldst0_1[0:0] + end + attribute \src "libresoc.v:41940.3-41941.59" + process $proc$libresoc.v:41940$2341 + assign { } { } + assign $0\dp_INT_rc_shiftrot0_0[0:0] \dp_INT_rc_shiftrot0_0$next + sync posedge \coresync_clk + update \dp_INT_rc_shiftrot0_0 $0\dp_INT_rc_shiftrot0_0[0:0] + end + attribute \src "libresoc.v:41942.3-41943.51" + process $proc$libresoc.v:41942$2342 + assign { } { } + assign $0\dp_INT_rb_ldst0_7[0:0] \dp_INT_rb_ldst0_7$next + sync posedge \coresync_clk + update \dp_INT_rb_ldst0_7 $0\dp_INT_rb_ldst0_7[0:0] + end + attribute \src "libresoc.v:41944.3-41945.59" + process $proc$libresoc.v:41944$2343 + assign { } { } + assign $0\dp_INT_rb_shiftrot0_6[0:0] \dp_INT_rb_shiftrot0_6$next + sync posedge \coresync_clk + update \dp_INT_rb_shiftrot0_6 $0\dp_INT_rb_shiftrot0_6[0:0] + end + attribute \src "libresoc.v:41946.3-41947.49" + process $proc$libresoc.v:41946$2344 + assign { } { } + assign $0\dp_INT_rb_mul0_5[0:0] \dp_INT_rb_mul0_5$next + sync posedge \coresync_clk + update \dp_INT_rb_mul0_5 $0\dp_INT_rb_mul0_5[0:0] + end + attribute \src "libresoc.v:41948.3-41949.49" + process $proc$libresoc.v:41948$2345 + assign { } { } + assign $0\dp_INT_rb_div0_4[0:0] \dp_INT_rb_div0_4$next + sync posedge \coresync_clk + update \dp_INT_rb_div0_4 $0\dp_INT_rb_div0_4[0:0] + end + attribute \src "libresoc.v:41950.3-41951.57" + process $proc$libresoc.v:41950$2346 + assign { } { } + assign $0\dp_INT_rb_logical0_3[0:0] \dp_INT_rb_logical0_3$next + sync posedge \coresync_clk + update \dp_INT_rb_logical0_3 $0\dp_INT_rb_logical0_3[0:0] + end + attribute \src "libresoc.v:41952.3-41953.51" + process $proc$libresoc.v:41952$2347 + assign { } { } + assign $0\dp_INT_rb_trap0_2[0:0] \dp_INT_rb_trap0_2$next + sync posedge \coresync_clk + update \dp_INT_rb_trap0_2 $0\dp_INT_rb_trap0_2[0:0] + end + attribute \src "libresoc.v:41954.3-41955.47" + process $proc$libresoc.v:41954$2348 + assign { } { } + assign $0\dp_INT_rb_cr0_1[0:0] \dp_INT_rb_cr0_1$next + sync posedge \coresync_clk + update \dp_INT_rb_cr0_1 $0\dp_INT_rb_cr0_1[0:0] + end + attribute \src "libresoc.v:41956.3-41957.49" + process $proc$libresoc.v:41956$2349 + assign { } { } + assign $0\dp_INT_rb_alu0_0[0:0] \dp_INT_rb_alu0_0$next + sync posedge \coresync_clk + update \dp_INT_rb_alu0_0 $0\dp_INT_rb_alu0_0[0:0] + end + attribute \src "libresoc.v:41958.3-41959.51" + process $proc$libresoc.v:41958$2350 + assign { } { } + assign $0\dp_INT_ra_ldst0_8[0:0] \dp_INT_ra_ldst0_8$next + sync posedge \coresync_clk + update \dp_INT_ra_ldst0_8 $0\dp_INT_ra_ldst0_8[0:0] + end + attribute \src "libresoc.v:41960.3-41961.59" + process $proc$libresoc.v:41960$2351 + assign { } { } + assign $0\dp_INT_ra_shiftrot0_7[0:0] \dp_INT_ra_shiftrot0_7$next + sync posedge \coresync_clk + update \dp_INT_ra_shiftrot0_7 $0\dp_INT_ra_shiftrot0_7[0:0] + end + attribute \src "libresoc.v:41962.3-41963.49" + process $proc$libresoc.v:41962$2352 + assign { } { } + assign $0\dp_INT_ra_mul0_6[0:0] \dp_INT_ra_mul0_6$next + sync posedge \coresync_clk + update \dp_INT_ra_mul0_6 $0\dp_INT_ra_mul0_6[0:0] + end + attribute \src "libresoc.v:41964.3-41965.49" + process $proc$libresoc.v:41964$2353 + assign { } { } + assign $0\dp_INT_ra_div0_5[0:0] \dp_INT_ra_div0_5$next + sync posedge \coresync_clk + update \dp_INT_ra_div0_5 $0\dp_INT_ra_div0_5[0:0] + end + attribute \src "libresoc.v:41966.3-41967.49" + process $proc$libresoc.v:41966$2354 + assign { } { } + assign $0\dp_INT_ra_spr0_4[0:0] \dp_INT_ra_spr0_4$next + sync posedge \coresync_clk + update \dp_INT_ra_spr0_4 $0\dp_INT_ra_spr0_4[0:0] + end + attribute \src "libresoc.v:41968.3-41969.57" + process $proc$libresoc.v:41968$2355 + assign { } { } + assign $0\dp_INT_ra_logical0_3[0:0] \dp_INT_ra_logical0_3$next + sync posedge \coresync_clk + update \dp_INT_ra_logical0_3 $0\dp_INT_ra_logical0_3[0:0] + end + attribute \src "libresoc.v:41970.3-41971.51" + process $proc$libresoc.v:41970$2356 + assign { } { } + assign $0\dp_INT_ra_trap0_2[0:0] \dp_INT_ra_trap0_2$next + sync posedge \coresync_clk + update \dp_INT_ra_trap0_2 $0\dp_INT_ra_trap0_2[0:0] + end + attribute \src "libresoc.v:41972.3-41973.47" + process $proc$libresoc.v:41972$2357 + assign { } { } + assign $0\dp_INT_ra_cr0_1[0:0] \dp_INT_ra_cr0_1$next + sync posedge \coresync_clk + update \dp_INT_ra_cr0_1 $0\dp_INT_ra_cr0_1[0:0] + end + attribute \src "libresoc.v:41974.3-41975.49" + process $proc$libresoc.v:41974$2358 + assign { } { } + assign $0\dp_INT_ra_alu0_0[0:0] \dp_INT_ra_alu0_0$next + sync posedge \coresync_clk + update \dp_INT_ra_alu0_0 $0\dp_INT_ra_alu0_0[0:0] + end + attribute \src "libresoc.v:41976.3-41977.49" + process $proc$libresoc.v:41976$2359 + assign { } { } + assign $0\core_terminate_o[0:0] \core_terminate_o$next + sync posedge \coresync_clk + update \core_terminate_o $0\core_terminate_o[0:0] + end + attribute \src "libresoc.v:41978.3-41979.31" + process $proc$libresoc.v:41978$2360 + assign { } { } + assign $0\counter[1:0] \counter$next + sync posedge \coresync_clk + update \counter $0\counter[1:0] + end + attribute \src "libresoc.v:42691.3-42719.6" + process $proc$libresoc.v:42691$2361 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_spr0__is_32bit[0:0] $1\fus_oper_i_alu_spr0__is_32bit[0:0] + attribute \src "libresoc.v:42692.5-42692.29" + switch \initial + attribute \src "libresoc.v:42692.9-42692.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_spr0__is_32bit[0:0] $2\fus_oper_i_alu_spr0__is_32bit[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_spr0__is_32bit[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_spr0__is_32bit[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_spr0__is_32bit[0:0] $3\fus_oper_i_alu_spr0__is_32bit[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + switch \fu_enable [5] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_spr0__is_32bit[0:0] \dec_SPR_SPR_SPR__is_32bit + case + assign $3\fus_oper_i_alu_spr0__is_32bit[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_spr0__is_32bit[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_spr0__is_32bit $0\fus_oper_i_alu_spr0__is_32bit[0:0] + end + attribute \src "libresoc.v:42720.3-42748.6" + process $proc$libresoc.v:42720$2362 + assign { } { } + assign { } { } + assign $0\fus_cu_issue_i$16[0:0]$2363 $1\fus_cu_issue_i$16[0:0]$2364 + attribute \src "libresoc.v:42721.5-42721.29" + switch \initial + attribute \src "libresoc.v:42721.9-42721.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_cu_issue_i$16[0:0]$2364 $2\fus_cu_issue_i$16[0:0]$2365 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_cu_issue_i$16[0:0]$2365 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_cu_issue_i$16[0:0]$2365 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_cu_issue_i$16[0:0]$2365 $3\fus_cu_issue_i$16[0:0]$2366 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + switch \fu_enable [5] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_cu_issue_i$16[0:0]$2366 \issue_i + case + assign $3\fus_cu_issue_i$16[0:0]$2366 1'0 + end + end + case + assign $1\fus_cu_issue_i$16[0:0]$2364 1'0 + end + sync always + update \fus_cu_issue_i$16 $0\fus_cu_issue_i$16[0:0]$2363 + end + attribute \src "libresoc.v:42749.3-42777.6" + process $proc$libresoc.v:42749$2367 + assign { } { } + assign { } { } + assign $0\fus_cu_rdmaskn_i$18[5:0]$2368 $1\fus_cu_rdmaskn_i$18[5:0]$2369 + attribute \src "libresoc.v:42750.5-42750.29" + switch \initial + attribute \src "libresoc.v:42750.9-42750.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_cu_rdmaskn_i$18[5:0]$2369 $2\fus_cu_rdmaskn_i$18[5:0]$2370 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_cu_rdmaskn_i$18[5:0]$2370 6'000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_cu_rdmaskn_i$18[5:0]$2370 6'000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_cu_rdmaskn_i$18[5:0]$2370 $3\fus_cu_rdmaskn_i$18[5:0]$2371 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + switch \fu_enable [5] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_cu_rdmaskn_i$18[5:0]$2371 \$249 + case + assign $3\fus_cu_rdmaskn_i$18[5:0]$2371 6'000000 + end + end + case + assign $1\fus_cu_rdmaskn_i$18[5:0]$2369 6'000000 + end + sync always + update \fus_cu_rdmaskn_i$18 $0\fus_cu_rdmaskn_i$18[5:0]$2368 + end + attribute \src "libresoc.v:42778.3-42806.6" + process $proc$libresoc.v:42778$2372 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_div0__insn_type[6:0] $1\fus_oper_i_alu_div0__insn_type[6:0] + attribute \src "libresoc.v:42779.5-42779.29" + switch \initial + attribute \src "libresoc.v:42779.9-42779.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_div0__insn_type[6:0] $2\fus_oper_i_alu_div0__insn_type[6:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_div0__insn_type[6:0] 7'0000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_div0__insn_type[6:0] 7'0000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_div0__insn_type[6:0] $3\fus_oper_i_alu_div0__insn_type[6:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + switch \fu_enable [6] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_div0__insn_type[6:0] \dec_DIV_DIV_DIV__insn_type + case + assign $3\fus_oper_i_alu_div0__insn_type[6:0] 7'0000000 + end + end + case + assign $1\fus_oper_i_alu_div0__insn_type[6:0] 7'0000000 + end + sync always + update \fus_oper_i_alu_div0__insn_type $0\fus_oper_i_alu_div0__insn_type[6:0] + end + attribute \src "libresoc.v:42807.3-42835.6" + process $proc$libresoc.v:42807$2373 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_div0__fn_unit[11:0] $1\fus_oper_i_alu_div0__fn_unit[11:0] + attribute \src "libresoc.v:42808.5-42808.29" + switch \initial + attribute \src "libresoc.v:42808.9-42808.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_div0__fn_unit[11:0] $2\fus_oper_i_alu_div0__fn_unit[11:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_div0__fn_unit[11:0] 12'000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_div0__fn_unit[11:0] 12'000000000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_div0__fn_unit[11:0] $3\fus_oper_i_alu_div0__fn_unit[11:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + switch \fu_enable [6] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_div0__fn_unit[11:0] \dec_DIV_DIV_DIV__fn_unit + case + assign $3\fus_oper_i_alu_div0__fn_unit[11:0] 12'000000000000 + end + end + case + assign $1\fus_oper_i_alu_div0__fn_unit[11:0] 12'000000000000 + end + sync always + update \fus_oper_i_alu_div0__fn_unit $0\fus_oper_i_alu_div0__fn_unit[11:0] + end + attribute \src "libresoc.v:42836.3-42865.6" + process $proc$libresoc.v:42836$2374 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_div0__imm_data__data[63:0] $1\fus_oper_i_alu_div0__imm_data__data[63:0] + assign $0\fus_oper_i_alu_div0__imm_data__ok[0:0] $1\fus_oper_i_alu_div0__imm_data__ok[0:0] + attribute \src "libresoc.v:42837.5-42837.29" + switch \initial + attribute \src "libresoc.v:42837.9-42837.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $1\fus_oper_i_alu_div0__imm_data__data[63:0] $2\fus_oper_i_alu_div0__imm_data__data[63:0] + assign $1\fus_oper_i_alu_div0__imm_data__ok[0:0] $2\fus_oper_i_alu_div0__imm_data__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_div0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\fus_oper_i_alu_div0__imm_data__ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_div0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\fus_oper_i_alu_div0__imm_data__ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign $2\fus_oper_i_alu_div0__imm_data__data[63:0] $3\fus_oper_i_alu_div0__imm_data__data[63:0] + assign $2\fus_oper_i_alu_div0__imm_data__ok[0:0] $3\fus_oper_i_alu_div0__imm_data__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + switch \fu_enable [6] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $3\fus_oper_i_alu_div0__imm_data__ok[0:0] $3\fus_oper_i_alu_div0__imm_data__data[63:0] } { \dec_DIV_DIV_DIV__imm_data__ok \dec_DIV_DIV_DIV__imm_data__data } + case + assign $3\fus_oper_i_alu_div0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\fus_oper_i_alu_div0__imm_data__ok[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_div0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fus_oper_i_alu_div0__imm_data__ok[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_div0__imm_data__data $0\fus_oper_i_alu_div0__imm_data__data[63:0] + update \fus_oper_i_alu_div0__imm_data__ok $0\fus_oper_i_alu_div0__imm_data__ok[0:0] + end + attribute \src "libresoc.v:42866.3-42895.6" + process $proc$libresoc.v:42866$2375 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_div0__rc__ok[0:0] $1\fus_oper_i_alu_div0__rc__ok[0:0] + assign $0\fus_oper_i_alu_div0__rc__rc[0:0] $1\fus_oper_i_alu_div0__rc__rc[0:0] + attribute \src "libresoc.v:42867.5-42867.29" + switch \initial + attribute \src "libresoc.v:42867.9-42867.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $1\fus_oper_i_alu_div0__rc__ok[0:0] $2\fus_oper_i_alu_div0__rc__ok[0:0] + assign $1\fus_oper_i_alu_div0__rc__rc[0:0] $2\fus_oper_i_alu_div0__rc__rc[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_div0__rc__ok[0:0] 1'0 + assign $2\fus_oper_i_alu_div0__rc__rc[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_div0__rc__ok[0:0] 1'0 + assign $2\fus_oper_i_alu_div0__rc__rc[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign $2\fus_oper_i_alu_div0__rc__ok[0:0] $3\fus_oper_i_alu_div0__rc__ok[0:0] + assign $2\fus_oper_i_alu_div0__rc__rc[0:0] $3\fus_oper_i_alu_div0__rc__rc[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + switch \fu_enable [6] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $3\fus_oper_i_alu_div0__rc__ok[0:0] $3\fus_oper_i_alu_div0__rc__rc[0:0] } { \dec_DIV_DIV_DIV__rc__ok \dec_DIV_DIV_DIV__rc__rc } + case + assign $3\fus_oper_i_alu_div0__rc__ok[0:0] 1'0 + assign $3\fus_oper_i_alu_div0__rc__rc[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_div0__rc__ok[0:0] 1'0 + assign $1\fus_oper_i_alu_div0__rc__rc[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_div0__rc__ok $0\fus_oper_i_alu_div0__rc__ok[0:0] + update \fus_oper_i_alu_div0__rc__rc $0\fus_oper_i_alu_div0__rc__rc[0:0] + end + attribute \src "libresoc.v:42896.3-42925.6" + process $proc$libresoc.v:42896$2376 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_div0__oe__oe[0:0] $1\fus_oper_i_alu_div0__oe__oe[0:0] + assign $0\fus_oper_i_alu_div0__oe__ok[0:0] $1\fus_oper_i_alu_div0__oe__ok[0:0] + attribute \src "libresoc.v:42897.5-42897.29" + switch \initial + attribute \src "libresoc.v:42897.9-42897.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $1\fus_oper_i_alu_div0__oe__oe[0:0] $2\fus_oper_i_alu_div0__oe__oe[0:0] + assign $1\fus_oper_i_alu_div0__oe__ok[0:0] $2\fus_oper_i_alu_div0__oe__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_div0__oe__oe[0:0] 1'0 + assign $2\fus_oper_i_alu_div0__oe__ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_div0__oe__oe[0:0] 1'0 + assign $2\fus_oper_i_alu_div0__oe__ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign $2\fus_oper_i_alu_div0__oe__oe[0:0] $3\fus_oper_i_alu_div0__oe__oe[0:0] + assign $2\fus_oper_i_alu_div0__oe__ok[0:0] $3\fus_oper_i_alu_div0__oe__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + switch \fu_enable [6] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $3\fus_oper_i_alu_div0__oe__ok[0:0] $3\fus_oper_i_alu_div0__oe__oe[0:0] } { \dec_DIV_DIV_DIV__oe__ok \dec_DIV_DIV_DIV__oe__oe } + case + assign $3\fus_oper_i_alu_div0__oe__oe[0:0] 1'0 + assign $3\fus_oper_i_alu_div0__oe__ok[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_div0__oe__oe[0:0] 1'0 + assign $1\fus_oper_i_alu_div0__oe__ok[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_div0__oe__oe $0\fus_oper_i_alu_div0__oe__oe[0:0] + update \fus_oper_i_alu_div0__oe__ok $0\fus_oper_i_alu_div0__oe__ok[0:0] + end + attribute \src "libresoc.v:42926.3-42954.6" + process $proc$libresoc.v:42926$2377 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_div0__invert_in[0:0] $1\fus_oper_i_alu_div0__invert_in[0:0] + attribute \src "libresoc.v:42927.5-42927.29" + switch \initial + attribute \src "libresoc.v:42927.9-42927.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_div0__invert_in[0:0] $2\fus_oper_i_alu_div0__invert_in[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_div0__invert_in[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_div0__invert_in[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_div0__invert_in[0:0] $3\fus_oper_i_alu_div0__invert_in[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + switch \fu_enable [6] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_div0__invert_in[0:0] \dec_DIV_DIV_DIV__invert_in + case + assign $3\fus_oper_i_alu_div0__invert_in[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_div0__invert_in[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_div0__invert_in $0\fus_oper_i_alu_div0__invert_in[0:0] + end + attribute \src "libresoc.v:42955.3-42983.6" + process $proc$libresoc.v:42955$2378 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_div0__zero_a[0:0] $1\fus_oper_i_alu_div0__zero_a[0:0] + attribute \src "libresoc.v:42956.5-42956.29" + switch \initial + attribute \src "libresoc.v:42956.9-42956.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_div0__zero_a[0:0] $2\fus_oper_i_alu_div0__zero_a[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_div0__zero_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_div0__zero_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_div0__zero_a[0:0] $3\fus_oper_i_alu_div0__zero_a[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + switch \fu_enable [6] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_div0__zero_a[0:0] \dec_DIV_DIV_DIV__zero_a + case + assign $3\fus_oper_i_alu_div0__zero_a[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_div0__zero_a[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_div0__zero_a $0\fus_oper_i_alu_div0__zero_a[0:0] + end + attribute \src "libresoc.v:42984.3-43012.6" + process $proc$libresoc.v:42984$2379 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_div0__input_carry[1:0] $1\fus_oper_i_alu_div0__input_carry[1:0] + attribute \src "libresoc.v:42985.5-42985.29" + switch \initial + attribute \src "libresoc.v:42985.9-42985.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_div0__input_carry[1:0] $2\fus_oper_i_alu_div0__input_carry[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_div0__input_carry[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_div0__input_carry[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_div0__input_carry[1:0] $3\fus_oper_i_alu_div0__input_carry[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + switch \fu_enable [6] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_div0__input_carry[1:0] \dec_DIV_DIV_DIV__input_carry + case + assign $3\fus_oper_i_alu_div0__input_carry[1:0] 2'00 + end + end + case + assign $1\fus_oper_i_alu_div0__input_carry[1:0] 2'00 + end + sync always + update \fus_oper_i_alu_div0__input_carry $0\fus_oper_i_alu_div0__input_carry[1:0] + end + attribute \src "libresoc.v:43013.3-43041.6" + process $proc$libresoc.v:43013$2380 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_div0__invert_out[0:0] $1\fus_oper_i_alu_div0__invert_out[0:0] + attribute \src "libresoc.v:43014.5-43014.29" + switch \initial + attribute \src "libresoc.v:43014.9-43014.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_div0__invert_out[0:0] $2\fus_oper_i_alu_div0__invert_out[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_div0__invert_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_div0__invert_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_div0__invert_out[0:0] $3\fus_oper_i_alu_div0__invert_out[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + switch \fu_enable [6] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_div0__invert_out[0:0] \dec_DIV_DIV_DIV__invert_out + case + assign $3\fus_oper_i_alu_div0__invert_out[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_div0__invert_out[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_div0__invert_out $0\fus_oper_i_alu_div0__invert_out[0:0] + end + attribute \src "libresoc.v:43042.3-43070.6" + process $proc$libresoc.v:43042$2381 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_div0__write_cr0[0:0] $1\fus_oper_i_alu_div0__write_cr0[0:0] + attribute \src "libresoc.v:43043.5-43043.29" + switch \initial + attribute \src "libresoc.v:43043.9-43043.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_div0__write_cr0[0:0] $2\fus_oper_i_alu_div0__write_cr0[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_div0__write_cr0[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_div0__write_cr0[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_div0__write_cr0[0:0] $3\fus_oper_i_alu_div0__write_cr0[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + switch \fu_enable [6] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_div0__write_cr0[0:0] \dec_DIV_DIV_DIV__write_cr0 + case + assign $3\fus_oper_i_alu_div0__write_cr0[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_div0__write_cr0[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_div0__write_cr0 $0\fus_oper_i_alu_div0__write_cr0[0:0] + end + attribute \src "libresoc.v:43071.3-43099.6" + process $proc$libresoc.v:43071$2382 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_div0__output_carry[0:0] $1\fus_oper_i_alu_div0__output_carry[0:0] + attribute \src "libresoc.v:43072.5-43072.29" + switch \initial + attribute \src "libresoc.v:43072.9-43072.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_div0__output_carry[0:0] $2\fus_oper_i_alu_div0__output_carry[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_div0__output_carry[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_div0__output_carry[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_div0__output_carry[0:0] $3\fus_oper_i_alu_div0__output_carry[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + switch \fu_enable [6] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_div0__output_carry[0:0] \dec_DIV_DIV_DIV__output_carry + case + assign $3\fus_oper_i_alu_div0__output_carry[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_div0__output_carry[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_div0__output_carry $0\fus_oper_i_alu_div0__output_carry[0:0] + end + attribute \src "libresoc.v:43100.3-43128.6" + process $proc$libresoc.v:43100$2383 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_div0__is_32bit[0:0] $1\fus_oper_i_alu_div0__is_32bit[0:0] + attribute \src "libresoc.v:43101.5-43101.29" + switch \initial + attribute \src "libresoc.v:43101.9-43101.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_div0__is_32bit[0:0] $2\fus_oper_i_alu_div0__is_32bit[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_div0__is_32bit[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_div0__is_32bit[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_div0__is_32bit[0:0] $3\fus_oper_i_alu_div0__is_32bit[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + switch \fu_enable [6] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_div0__is_32bit[0:0] \dec_DIV_DIV_DIV__is_32bit + case + assign $3\fus_oper_i_alu_div0__is_32bit[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_div0__is_32bit[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_div0__is_32bit $0\fus_oper_i_alu_div0__is_32bit[0:0] + end + attribute \src "libresoc.v:43129.3-43157.6" + process $proc$libresoc.v:43129$2384 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_div0__is_signed[0:0] $1\fus_oper_i_alu_div0__is_signed[0:0] + attribute \src "libresoc.v:43130.5-43130.29" + switch \initial + attribute \src "libresoc.v:43130.9-43130.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_div0__is_signed[0:0] $2\fus_oper_i_alu_div0__is_signed[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_div0__is_signed[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_div0__is_signed[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_div0__is_signed[0:0] $3\fus_oper_i_alu_div0__is_signed[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + switch \fu_enable [6] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_div0__is_signed[0:0] \dec_DIV_DIV_DIV__is_signed + case + assign $3\fus_oper_i_alu_div0__is_signed[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_div0__is_signed[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_div0__is_signed $0\fus_oper_i_alu_div0__is_signed[0:0] + end + attribute \src "libresoc.v:43158.3-43186.6" + process $proc$libresoc.v:43158$2385 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_div0__data_len[3:0] $1\fus_oper_i_alu_div0__data_len[3:0] + attribute \src "libresoc.v:43159.5-43159.29" + switch \initial + attribute \src "libresoc.v:43159.9-43159.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_div0__data_len[3:0] $2\fus_oper_i_alu_div0__data_len[3:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_div0__data_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_div0__data_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_div0__data_len[3:0] $3\fus_oper_i_alu_div0__data_len[3:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + switch \fu_enable [6] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_div0__data_len[3:0] \dec_DIV_DIV_DIV__data_len + case + assign $3\fus_oper_i_alu_div0__data_len[3:0] 4'0000 + end + end + case + assign $1\fus_oper_i_alu_div0__data_len[3:0] 4'0000 + end + sync always + update \fus_oper_i_alu_div0__data_len $0\fus_oper_i_alu_div0__data_len[3:0] + end + attribute \src "libresoc.v:43187.3-43215.6" + process $proc$libresoc.v:43187$2386 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_div0__insn[31:0] $1\fus_oper_i_alu_div0__insn[31:0] + attribute \src "libresoc.v:43188.5-43188.29" + switch \initial + attribute \src "libresoc.v:43188.9-43188.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_div0__insn[31:0] $2\fus_oper_i_alu_div0__insn[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_div0__insn[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_div0__insn[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_div0__insn[31:0] $3\fus_oper_i_alu_div0__insn[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + switch \fu_enable [6] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_div0__insn[31:0] \dec_DIV_DIV_DIV__insn + case + assign $3\fus_oper_i_alu_div0__insn[31:0] 0 + end + end + case + assign $1\fus_oper_i_alu_div0__insn[31:0] 0 + end + sync always + update \fus_oper_i_alu_div0__insn $0\fus_oper_i_alu_div0__insn[31:0] + end + attribute \src "libresoc.v:43216.3-43244.6" + process $proc$libresoc.v:43216$2387 + assign { } { } + assign { } { } + assign $0\fus_cu_issue_i$19[0:0]$2388 $1\fus_cu_issue_i$19[0:0]$2389 + attribute \src "libresoc.v:43217.5-43217.29" + switch \initial + attribute \src "libresoc.v:43217.9-43217.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_cu_issue_i$19[0:0]$2389 $2\fus_cu_issue_i$19[0:0]$2390 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_cu_issue_i$19[0:0]$2390 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_cu_issue_i$19[0:0]$2390 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_cu_issue_i$19[0:0]$2390 $3\fus_cu_issue_i$19[0:0]$2391 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + switch \fu_enable [6] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_cu_issue_i$19[0:0]$2391 \issue_i + case + assign $3\fus_cu_issue_i$19[0:0]$2391 1'0 + end + end + case + assign $1\fus_cu_issue_i$19[0:0]$2389 1'0 + end + sync always + update \fus_cu_issue_i$19 $0\fus_cu_issue_i$19[0:0]$2388 + end + attribute \src "libresoc.v:43245.3-43273.6" + process $proc$libresoc.v:43245$2392 + assign { } { } + assign { } { } + assign $0\fus_cu_rdmaskn_i$21[2:0]$2393 $1\fus_cu_rdmaskn_i$21[2:0]$2394 + attribute \src "libresoc.v:43246.5-43246.29" + switch \initial + attribute \src "libresoc.v:43246.9-43246.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_cu_rdmaskn_i$21[2:0]$2394 $2\fus_cu_rdmaskn_i$21[2:0]$2395 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_cu_rdmaskn_i$21[2:0]$2395 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_cu_rdmaskn_i$21[2:0]$2395 3'000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_cu_rdmaskn_i$21[2:0]$2395 $3\fus_cu_rdmaskn_i$21[2:0]$2396 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + switch \fu_enable [6] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_cu_rdmaskn_i$21[2:0]$2396 \$279 + case + assign $3\fus_cu_rdmaskn_i$21[2:0]$2396 3'000 + end + end + case + assign $1\fus_cu_rdmaskn_i$21[2:0]$2394 3'000 + end + sync always + update \fus_cu_rdmaskn_i$21 $0\fus_cu_rdmaskn_i$21[2:0]$2393 + end + attribute \src "libresoc.v:43274.3-43302.6" + process $proc$libresoc.v:43274$2397 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_mul0__insn_type[6:0] $1\fus_oper_i_alu_mul0__insn_type[6:0] + attribute \src "libresoc.v:43275.5-43275.29" + switch \initial + attribute \src "libresoc.v:43275.9-43275.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_mul0__insn_type[6:0] $2\fus_oper_i_alu_mul0__insn_type[6:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_mul0__insn_type[6:0] 7'0000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_mul0__insn_type[6:0] 7'0000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_mul0__insn_type[6:0] $3\fus_oper_i_alu_mul0__insn_type[6:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + switch \fu_enable [7] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_mul0__insn_type[6:0] \dec_MUL_MUL_MUL__insn_type + case + assign $3\fus_oper_i_alu_mul0__insn_type[6:0] 7'0000000 + end + end + case + assign $1\fus_oper_i_alu_mul0__insn_type[6:0] 7'0000000 + end + sync always + update \fus_oper_i_alu_mul0__insn_type $0\fus_oper_i_alu_mul0__insn_type[6:0] + end + attribute \src "libresoc.v:43303.3-43331.6" + process $proc$libresoc.v:43303$2398 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_mul0__fn_unit[11:0] $1\fus_oper_i_alu_mul0__fn_unit[11:0] + attribute \src "libresoc.v:43304.5-43304.29" + switch \initial + attribute \src "libresoc.v:43304.9-43304.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_mul0__fn_unit[11:0] $2\fus_oper_i_alu_mul0__fn_unit[11:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_mul0__fn_unit[11:0] 12'000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_mul0__fn_unit[11:0] 12'000000000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_mul0__fn_unit[11:0] $3\fus_oper_i_alu_mul0__fn_unit[11:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + switch \fu_enable [7] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_mul0__fn_unit[11:0] \dec_MUL_MUL_MUL__fn_unit + case + assign $3\fus_oper_i_alu_mul0__fn_unit[11:0] 12'000000000000 + end + end + case + assign $1\fus_oper_i_alu_mul0__fn_unit[11:0] 12'000000000000 + end + sync always + update \fus_oper_i_alu_mul0__fn_unit $0\fus_oper_i_alu_mul0__fn_unit[11:0] + end + attribute \src "libresoc.v:43332.3-43361.6" + process $proc$libresoc.v:43332$2399 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_mul0__imm_data__data[63:0] $1\fus_oper_i_alu_mul0__imm_data__data[63:0] + assign $0\fus_oper_i_alu_mul0__imm_data__ok[0:0] $1\fus_oper_i_alu_mul0__imm_data__ok[0:0] + attribute \src "libresoc.v:43333.5-43333.29" + switch \initial + attribute \src "libresoc.v:43333.9-43333.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $1\fus_oper_i_alu_mul0__imm_data__data[63:0] $2\fus_oper_i_alu_mul0__imm_data__data[63:0] + assign $1\fus_oper_i_alu_mul0__imm_data__ok[0:0] $2\fus_oper_i_alu_mul0__imm_data__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_mul0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\fus_oper_i_alu_mul0__imm_data__ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_mul0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\fus_oper_i_alu_mul0__imm_data__ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign $2\fus_oper_i_alu_mul0__imm_data__data[63:0] $3\fus_oper_i_alu_mul0__imm_data__data[63:0] + assign $2\fus_oper_i_alu_mul0__imm_data__ok[0:0] $3\fus_oper_i_alu_mul0__imm_data__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + switch \fu_enable [7] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $3\fus_oper_i_alu_mul0__imm_data__ok[0:0] $3\fus_oper_i_alu_mul0__imm_data__data[63:0] } { \dec_MUL_MUL_MUL__imm_data__ok \dec_MUL_MUL_MUL__imm_data__data } + case + assign $3\fus_oper_i_alu_mul0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\fus_oper_i_alu_mul0__imm_data__ok[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_mul0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fus_oper_i_alu_mul0__imm_data__ok[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_mul0__imm_data__data $0\fus_oper_i_alu_mul0__imm_data__data[63:0] + update \fus_oper_i_alu_mul0__imm_data__ok $0\fus_oper_i_alu_mul0__imm_data__ok[0:0] + end + attribute \src "libresoc.v:43362.3-43391.6" + process $proc$libresoc.v:43362$2400 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_mul0__rc__ok[0:0] $1\fus_oper_i_alu_mul0__rc__ok[0:0] + assign $0\fus_oper_i_alu_mul0__rc__rc[0:0] $1\fus_oper_i_alu_mul0__rc__rc[0:0] + attribute \src "libresoc.v:43363.5-43363.29" + switch \initial + attribute \src "libresoc.v:43363.9-43363.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $1\fus_oper_i_alu_mul0__rc__ok[0:0] $2\fus_oper_i_alu_mul0__rc__ok[0:0] + assign $1\fus_oper_i_alu_mul0__rc__rc[0:0] $2\fus_oper_i_alu_mul0__rc__rc[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_mul0__rc__ok[0:0] 1'0 + assign $2\fus_oper_i_alu_mul0__rc__rc[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_mul0__rc__ok[0:0] 1'0 + assign $2\fus_oper_i_alu_mul0__rc__rc[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign $2\fus_oper_i_alu_mul0__rc__ok[0:0] $3\fus_oper_i_alu_mul0__rc__ok[0:0] + assign $2\fus_oper_i_alu_mul0__rc__rc[0:0] $3\fus_oper_i_alu_mul0__rc__rc[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + switch \fu_enable [7] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $3\fus_oper_i_alu_mul0__rc__ok[0:0] $3\fus_oper_i_alu_mul0__rc__rc[0:0] } { \dec_MUL_MUL_MUL__rc__ok \dec_MUL_MUL_MUL__rc__rc } + case + assign $3\fus_oper_i_alu_mul0__rc__ok[0:0] 1'0 + assign $3\fus_oper_i_alu_mul0__rc__rc[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_mul0__rc__ok[0:0] 1'0 + assign $1\fus_oper_i_alu_mul0__rc__rc[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_mul0__rc__ok $0\fus_oper_i_alu_mul0__rc__ok[0:0] + update \fus_oper_i_alu_mul0__rc__rc $0\fus_oper_i_alu_mul0__rc__rc[0:0] + end + attribute \src "libresoc.v:43392.3-43421.6" + process $proc$libresoc.v:43392$2401 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_mul0__oe__oe[0:0] $1\fus_oper_i_alu_mul0__oe__oe[0:0] + assign $0\fus_oper_i_alu_mul0__oe__ok[0:0] $1\fus_oper_i_alu_mul0__oe__ok[0:0] + attribute \src "libresoc.v:43393.5-43393.29" + switch \initial + attribute \src "libresoc.v:43393.9-43393.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $1\fus_oper_i_alu_mul0__oe__oe[0:0] $2\fus_oper_i_alu_mul0__oe__oe[0:0] + assign $1\fus_oper_i_alu_mul0__oe__ok[0:0] $2\fus_oper_i_alu_mul0__oe__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_mul0__oe__oe[0:0] 1'0 + assign $2\fus_oper_i_alu_mul0__oe__ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_mul0__oe__oe[0:0] 1'0 + assign $2\fus_oper_i_alu_mul0__oe__ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign $2\fus_oper_i_alu_mul0__oe__oe[0:0] $3\fus_oper_i_alu_mul0__oe__oe[0:0] + assign $2\fus_oper_i_alu_mul0__oe__ok[0:0] $3\fus_oper_i_alu_mul0__oe__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + switch \fu_enable [7] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $3\fus_oper_i_alu_mul0__oe__ok[0:0] $3\fus_oper_i_alu_mul0__oe__oe[0:0] } { \dec_MUL_MUL_MUL__oe__ok \dec_MUL_MUL_MUL__oe__oe } + case + assign $3\fus_oper_i_alu_mul0__oe__oe[0:0] 1'0 + assign $3\fus_oper_i_alu_mul0__oe__ok[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_mul0__oe__oe[0:0] 1'0 + assign $1\fus_oper_i_alu_mul0__oe__ok[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_mul0__oe__oe $0\fus_oper_i_alu_mul0__oe__oe[0:0] + update \fus_oper_i_alu_mul0__oe__ok $0\fus_oper_i_alu_mul0__oe__ok[0:0] + end + attribute \src "libresoc.v:43422.3-43450.6" + process $proc$libresoc.v:43422$2402 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_mul0__write_cr0[0:0] $1\fus_oper_i_alu_mul0__write_cr0[0:0] + attribute \src "libresoc.v:43423.5-43423.29" + switch \initial + attribute \src "libresoc.v:43423.9-43423.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_mul0__write_cr0[0:0] $2\fus_oper_i_alu_mul0__write_cr0[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_mul0__write_cr0[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_mul0__write_cr0[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_mul0__write_cr0[0:0] $3\fus_oper_i_alu_mul0__write_cr0[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + switch \fu_enable [7] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_mul0__write_cr0[0:0] \dec_MUL_MUL_MUL__write_cr0 + case + assign $3\fus_oper_i_alu_mul0__write_cr0[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_mul0__write_cr0[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_mul0__write_cr0 $0\fus_oper_i_alu_mul0__write_cr0[0:0] + end + attribute \src "libresoc.v:43451.3-43479.6" + process $proc$libresoc.v:43451$2403 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_mul0__is_32bit[0:0] $1\fus_oper_i_alu_mul0__is_32bit[0:0] + attribute \src "libresoc.v:43452.5-43452.29" + switch \initial + attribute \src "libresoc.v:43452.9-43452.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_mul0__is_32bit[0:0] $2\fus_oper_i_alu_mul0__is_32bit[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_mul0__is_32bit[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_mul0__is_32bit[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_mul0__is_32bit[0:0] $3\fus_oper_i_alu_mul0__is_32bit[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + switch \fu_enable [7] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_mul0__is_32bit[0:0] \dec_MUL_MUL_MUL__is_32bit + case + assign $3\fus_oper_i_alu_mul0__is_32bit[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_mul0__is_32bit[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_mul0__is_32bit $0\fus_oper_i_alu_mul0__is_32bit[0:0] + end + attribute \src "libresoc.v:43480.3-43508.6" + process $proc$libresoc.v:43480$2404 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_mul0__is_signed[0:0] $1\fus_oper_i_alu_mul0__is_signed[0:0] + attribute \src "libresoc.v:43481.5-43481.29" + switch \initial + attribute \src "libresoc.v:43481.9-43481.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_mul0__is_signed[0:0] $2\fus_oper_i_alu_mul0__is_signed[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_mul0__is_signed[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_mul0__is_signed[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_mul0__is_signed[0:0] $3\fus_oper_i_alu_mul0__is_signed[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + switch \fu_enable [7] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_mul0__is_signed[0:0] \dec_MUL_MUL_MUL__is_signed + case + assign $3\fus_oper_i_alu_mul0__is_signed[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_mul0__is_signed[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_mul0__is_signed $0\fus_oper_i_alu_mul0__is_signed[0:0] + end + attribute \src "libresoc.v:43509.3-43537.6" + process $proc$libresoc.v:43509$2405 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_mul0__insn[31:0] $1\fus_oper_i_alu_mul0__insn[31:0] + attribute \src "libresoc.v:43510.5-43510.29" + switch \initial + attribute \src "libresoc.v:43510.9-43510.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_mul0__insn[31:0] $2\fus_oper_i_alu_mul0__insn[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_mul0__insn[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_mul0__insn[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_mul0__insn[31:0] $3\fus_oper_i_alu_mul0__insn[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + switch \fu_enable [7] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_mul0__insn[31:0] \dec_MUL_MUL_MUL__insn + case + assign $3\fus_oper_i_alu_mul0__insn[31:0] 0 + end + end + case + assign $1\fus_oper_i_alu_mul0__insn[31:0] 0 + end + sync always + update \fus_oper_i_alu_mul0__insn $0\fus_oper_i_alu_mul0__insn[31:0] + end + attribute \src "libresoc.v:43538.3-43566.6" + process $proc$libresoc.v:43538$2406 + assign { } { } + assign { } { } + assign $0\fus_cu_issue_i$22[0:0]$2407 $1\fus_cu_issue_i$22[0:0]$2408 + attribute \src "libresoc.v:43539.5-43539.29" + switch \initial + attribute \src "libresoc.v:43539.9-43539.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_cu_issue_i$22[0:0]$2408 $2\fus_cu_issue_i$22[0:0]$2409 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_cu_issue_i$22[0:0]$2409 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_cu_issue_i$22[0:0]$2409 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_cu_issue_i$22[0:0]$2409 $3\fus_cu_issue_i$22[0:0]$2410 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + switch \fu_enable [7] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_cu_issue_i$22[0:0]$2410 \issue_i + case + assign $3\fus_cu_issue_i$22[0:0]$2410 1'0 + end + end + case + assign $1\fus_cu_issue_i$22[0:0]$2408 1'0 + end + sync always + update \fus_cu_issue_i$22 $0\fus_cu_issue_i$22[0:0]$2407 + end + attribute \src "libresoc.v:43567.3-43595.6" + process $proc$libresoc.v:43567$2411 + assign { } { } + assign { } { } + assign $0\fus_cu_rdmaskn_i$24[2:0]$2412 $1\fus_cu_rdmaskn_i$24[2:0]$2413 + attribute \src "libresoc.v:43568.5-43568.29" + switch \initial + attribute \src "libresoc.v:43568.9-43568.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_cu_rdmaskn_i$24[2:0]$2413 $2\fus_cu_rdmaskn_i$24[2:0]$2414 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_cu_rdmaskn_i$24[2:0]$2414 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_cu_rdmaskn_i$24[2:0]$2414 3'000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_cu_rdmaskn_i$24[2:0]$2414 $3\fus_cu_rdmaskn_i$24[2:0]$2415 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + switch \fu_enable [7] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_cu_rdmaskn_i$24[2:0]$2415 \$293 + case + assign $3\fus_cu_rdmaskn_i$24[2:0]$2415 3'000 + end + end + case + assign $1\fus_cu_rdmaskn_i$24[2:0]$2413 3'000 + end + sync always + update \fus_cu_rdmaskn_i$24 $0\fus_cu_rdmaskn_i$24[2:0]$2412 + end + attribute \src "libresoc.v:43596.3-43624.6" + process $proc$libresoc.v:43596$2416 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_shift_rot0__insn_type[6:0] $1\fus_oper_i_alu_shift_rot0__insn_type[6:0] + attribute \src "libresoc.v:43597.5-43597.29" + switch \initial + attribute \src "libresoc.v:43597.9-43597.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_shift_rot0__insn_type[6:0] $2\fus_oper_i_alu_shift_rot0__insn_type[6:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_shift_rot0__insn_type[6:0] 7'0000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_shift_rot0__insn_type[6:0] 7'0000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_shift_rot0__insn_type[6:0] $3\fus_oper_i_alu_shift_rot0__insn_type[6:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + switch \fu_enable [8] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_shift_rot0__insn_type[6:0] \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__insn_type + case + assign $3\fus_oper_i_alu_shift_rot0__insn_type[6:0] 7'0000000 + end + end + case + assign $1\fus_oper_i_alu_shift_rot0__insn_type[6:0] 7'0000000 + end + sync always + update \fus_oper_i_alu_shift_rot0__insn_type $0\fus_oper_i_alu_shift_rot0__insn_type[6:0] + end + attribute \src "libresoc.v:43625.3-43653.6" + process $proc$libresoc.v:43625$2417 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_shift_rot0__fn_unit[11:0] $1\fus_oper_i_alu_shift_rot0__fn_unit[11:0] + attribute \src "libresoc.v:43626.5-43626.29" + switch \initial + attribute \src "libresoc.v:43626.9-43626.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_shift_rot0__fn_unit[11:0] $2\fus_oper_i_alu_shift_rot0__fn_unit[11:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_shift_rot0__fn_unit[11:0] 12'000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_shift_rot0__fn_unit[11:0] 12'000000000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_shift_rot0__fn_unit[11:0] $3\fus_oper_i_alu_shift_rot0__fn_unit[11:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + switch \fu_enable [8] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_shift_rot0__fn_unit[11:0] \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__fn_unit + case + assign $3\fus_oper_i_alu_shift_rot0__fn_unit[11:0] 12'000000000000 + end + end + case + assign $1\fus_oper_i_alu_shift_rot0__fn_unit[11:0] 12'000000000000 + end + sync always + update \fus_oper_i_alu_shift_rot0__fn_unit $0\fus_oper_i_alu_shift_rot0__fn_unit[11:0] + end + attribute \src "libresoc.v:43654.3-43683.6" + process $proc$libresoc.v:43654$2418 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] $1\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] + assign $0\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] $1\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] + attribute \src "libresoc.v:43655.5-43655.29" + switch \initial + attribute \src "libresoc.v:43655.9-43655.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $1\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] $2\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] + assign $1\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] $2\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign $2\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] $3\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] + assign $2\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] $3\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + switch \fu_enable [8] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $3\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] $3\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] } { \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__imm_data__ok \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__imm_data__data } + case + assign $3\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_shift_rot0__imm_data__data $0\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] + update \fus_oper_i_alu_shift_rot0__imm_data__ok $0\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] + end + attribute \src "libresoc.v:43684.3-43713.6" + process $proc$libresoc.v:43684$2419 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_shift_rot0__rc__ok[0:0] $1\fus_oper_i_alu_shift_rot0__rc__ok[0:0] + assign $0\fus_oper_i_alu_shift_rot0__rc__rc[0:0] $1\fus_oper_i_alu_shift_rot0__rc__rc[0:0] + attribute \src "libresoc.v:43685.5-43685.29" + switch \initial + attribute \src "libresoc.v:43685.9-43685.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $1\fus_oper_i_alu_shift_rot0__rc__ok[0:0] $2\fus_oper_i_alu_shift_rot0__rc__ok[0:0] + assign $1\fus_oper_i_alu_shift_rot0__rc__rc[0:0] $2\fus_oper_i_alu_shift_rot0__rc__rc[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_shift_rot0__rc__ok[0:0] 1'0 + assign $2\fus_oper_i_alu_shift_rot0__rc__rc[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_shift_rot0__rc__ok[0:0] 1'0 + assign $2\fus_oper_i_alu_shift_rot0__rc__rc[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign $2\fus_oper_i_alu_shift_rot0__rc__ok[0:0] $3\fus_oper_i_alu_shift_rot0__rc__ok[0:0] + assign $2\fus_oper_i_alu_shift_rot0__rc__rc[0:0] $3\fus_oper_i_alu_shift_rot0__rc__rc[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + switch \fu_enable [8] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $3\fus_oper_i_alu_shift_rot0__rc__ok[0:0] $3\fus_oper_i_alu_shift_rot0__rc__rc[0:0] } { \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__rc__ok \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__rc__rc } + case + assign $3\fus_oper_i_alu_shift_rot0__rc__ok[0:0] 1'0 + assign $3\fus_oper_i_alu_shift_rot0__rc__rc[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_shift_rot0__rc__ok[0:0] 1'0 + assign $1\fus_oper_i_alu_shift_rot0__rc__rc[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_shift_rot0__rc__ok $0\fus_oper_i_alu_shift_rot0__rc__ok[0:0] + update \fus_oper_i_alu_shift_rot0__rc__rc $0\fus_oper_i_alu_shift_rot0__rc__rc[0:0] + end + attribute \src "libresoc.v:43714.3-43743.6" + process $proc$libresoc.v:43714$2420 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_shift_rot0__oe__oe[0:0] $1\fus_oper_i_alu_shift_rot0__oe__oe[0:0] + assign $0\fus_oper_i_alu_shift_rot0__oe__ok[0:0] $1\fus_oper_i_alu_shift_rot0__oe__ok[0:0] + attribute \src "libresoc.v:43715.5-43715.29" + switch \initial + attribute \src "libresoc.v:43715.9-43715.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $1\fus_oper_i_alu_shift_rot0__oe__oe[0:0] $2\fus_oper_i_alu_shift_rot0__oe__oe[0:0] + assign $1\fus_oper_i_alu_shift_rot0__oe__ok[0:0] $2\fus_oper_i_alu_shift_rot0__oe__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_shift_rot0__oe__oe[0:0] 1'0 + assign $2\fus_oper_i_alu_shift_rot0__oe__ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_shift_rot0__oe__oe[0:0] 1'0 + assign $2\fus_oper_i_alu_shift_rot0__oe__ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign $2\fus_oper_i_alu_shift_rot0__oe__oe[0:0] $3\fus_oper_i_alu_shift_rot0__oe__oe[0:0] + assign $2\fus_oper_i_alu_shift_rot0__oe__ok[0:0] $3\fus_oper_i_alu_shift_rot0__oe__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + switch \fu_enable [8] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $3\fus_oper_i_alu_shift_rot0__oe__ok[0:0] $3\fus_oper_i_alu_shift_rot0__oe__oe[0:0] } { \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__oe__ok \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__oe__oe } + case + assign $3\fus_oper_i_alu_shift_rot0__oe__oe[0:0] 1'0 + assign $3\fus_oper_i_alu_shift_rot0__oe__ok[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_shift_rot0__oe__oe[0:0] 1'0 + assign $1\fus_oper_i_alu_shift_rot0__oe__ok[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_shift_rot0__oe__oe $0\fus_oper_i_alu_shift_rot0__oe__oe[0:0] + update \fus_oper_i_alu_shift_rot0__oe__ok $0\fus_oper_i_alu_shift_rot0__oe__ok[0:0] + end + attribute \src "libresoc.v:43744.3-43772.6" + process $proc$libresoc.v:43744$2421 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_shift_rot0__write_cr0[0:0] $1\fus_oper_i_alu_shift_rot0__write_cr0[0:0] + attribute \src "libresoc.v:43745.5-43745.29" + switch \initial + attribute \src "libresoc.v:43745.9-43745.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_shift_rot0__write_cr0[0:0] $2\fus_oper_i_alu_shift_rot0__write_cr0[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_shift_rot0__write_cr0[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_shift_rot0__write_cr0[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_shift_rot0__write_cr0[0:0] $3\fus_oper_i_alu_shift_rot0__write_cr0[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + switch \fu_enable [8] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_shift_rot0__write_cr0[0:0] \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__write_cr0 + case + assign $3\fus_oper_i_alu_shift_rot0__write_cr0[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_shift_rot0__write_cr0[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_shift_rot0__write_cr0 $0\fus_oper_i_alu_shift_rot0__write_cr0[0:0] + end + attribute \src "libresoc.v:43773.3-43801.6" + process $proc$libresoc.v:43773$2422 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_shift_rot0__input_carry[1:0] $1\fus_oper_i_alu_shift_rot0__input_carry[1:0] + attribute \src "libresoc.v:43774.5-43774.29" + switch \initial + attribute \src "libresoc.v:43774.9-43774.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_shift_rot0__input_carry[1:0] $2\fus_oper_i_alu_shift_rot0__input_carry[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_shift_rot0__input_carry[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_shift_rot0__input_carry[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_shift_rot0__input_carry[1:0] $3\fus_oper_i_alu_shift_rot0__input_carry[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + switch \fu_enable [8] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_shift_rot0__input_carry[1:0] \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__input_carry + case + assign $3\fus_oper_i_alu_shift_rot0__input_carry[1:0] 2'00 + end + end + case + assign $1\fus_oper_i_alu_shift_rot0__input_carry[1:0] 2'00 + end + sync always + update \fus_oper_i_alu_shift_rot0__input_carry $0\fus_oper_i_alu_shift_rot0__input_carry[1:0] + end + attribute \src "libresoc.v:43802.3-43830.6" + process $proc$libresoc.v:43802$2423 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_shift_rot0__output_carry[0:0] $1\fus_oper_i_alu_shift_rot0__output_carry[0:0] + attribute \src "libresoc.v:43803.5-43803.29" + switch \initial + attribute \src "libresoc.v:43803.9-43803.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_shift_rot0__output_carry[0:0] $2\fus_oper_i_alu_shift_rot0__output_carry[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_shift_rot0__output_carry[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_shift_rot0__output_carry[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_shift_rot0__output_carry[0:0] $3\fus_oper_i_alu_shift_rot0__output_carry[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + switch \fu_enable [8] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_shift_rot0__output_carry[0:0] \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__output_carry + case + assign $3\fus_oper_i_alu_shift_rot0__output_carry[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_shift_rot0__output_carry[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_shift_rot0__output_carry $0\fus_oper_i_alu_shift_rot0__output_carry[0:0] + end + attribute \src "libresoc.v:43831.3-43859.6" + process $proc$libresoc.v:43831$2424 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_shift_rot0__input_cr[0:0] $1\fus_oper_i_alu_shift_rot0__input_cr[0:0] + attribute \src "libresoc.v:43832.5-43832.29" + switch \initial + attribute \src "libresoc.v:43832.9-43832.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_shift_rot0__input_cr[0:0] $2\fus_oper_i_alu_shift_rot0__input_cr[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_shift_rot0__input_cr[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_shift_rot0__input_cr[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_shift_rot0__input_cr[0:0] $3\fus_oper_i_alu_shift_rot0__input_cr[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + switch \fu_enable [8] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_shift_rot0__input_cr[0:0] \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__input_cr + case + assign $3\fus_oper_i_alu_shift_rot0__input_cr[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_shift_rot0__input_cr[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_shift_rot0__input_cr $0\fus_oper_i_alu_shift_rot0__input_cr[0:0] + end + attribute \src "libresoc.v:43860.3-43888.6" + process $proc$libresoc.v:43860$2425 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_shift_rot0__output_cr[0:0] $1\fus_oper_i_alu_shift_rot0__output_cr[0:0] + attribute \src "libresoc.v:43861.5-43861.29" + switch \initial + attribute \src "libresoc.v:43861.9-43861.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_shift_rot0__output_cr[0:0] $2\fus_oper_i_alu_shift_rot0__output_cr[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_shift_rot0__output_cr[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_shift_rot0__output_cr[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_shift_rot0__output_cr[0:0] $3\fus_oper_i_alu_shift_rot0__output_cr[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + switch \fu_enable [8] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_shift_rot0__output_cr[0:0] \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__output_cr + case + assign $3\fus_oper_i_alu_shift_rot0__output_cr[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_shift_rot0__output_cr[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_shift_rot0__output_cr $0\fus_oper_i_alu_shift_rot0__output_cr[0:0] + end + attribute \src "libresoc.v:43889.3-43917.6" + process $proc$libresoc.v:43889$2426 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_shift_rot0__is_32bit[0:0] $1\fus_oper_i_alu_shift_rot0__is_32bit[0:0] + attribute \src "libresoc.v:43890.5-43890.29" + switch \initial + attribute \src "libresoc.v:43890.9-43890.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_shift_rot0__is_32bit[0:0] $2\fus_oper_i_alu_shift_rot0__is_32bit[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_shift_rot0__is_32bit[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_shift_rot0__is_32bit[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_shift_rot0__is_32bit[0:0] $3\fus_oper_i_alu_shift_rot0__is_32bit[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + switch \fu_enable [8] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_shift_rot0__is_32bit[0:0] \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__is_32bit + case + assign $3\fus_oper_i_alu_shift_rot0__is_32bit[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_shift_rot0__is_32bit[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_shift_rot0__is_32bit $0\fus_oper_i_alu_shift_rot0__is_32bit[0:0] + end + attribute \src "libresoc.v:43918.3-43946.6" + process $proc$libresoc.v:43918$2427 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_shift_rot0__is_signed[0:0] $1\fus_oper_i_alu_shift_rot0__is_signed[0:0] + attribute \src "libresoc.v:43919.5-43919.29" + switch \initial + attribute \src "libresoc.v:43919.9-43919.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_shift_rot0__is_signed[0:0] $2\fus_oper_i_alu_shift_rot0__is_signed[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_shift_rot0__is_signed[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_shift_rot0__is_signed[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_shift_rot0__is_signed[0:0] $3\fus_oper_i_alu_shift_rot0__is_signed[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + switch \fu_enable [8] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_shift_rot0__is_signed[0:0] \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__is_signed + case + assign $3\fus_oper_i_alu_shift_rot0__is_signed[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_shift_rot0__is_signed[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_shift_rot0__is_signed $0\fus_oper_i_alu_shift_rot0__is_signed[0:0] + end + attribute \src "libresoc.v:43947.3-43975.6" + process $proc$libresoc.v:43947$2428 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_shift_rot0__insn[31:0] $1\fus_oper_i_alu_shift_rot0__insn[31:0] + attribute \src "libresoc.v:43948.5-43948.29" + switch \initial + attribute \src "libresoc.v:43948.9-43948.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_shift_rot0__insn[31:0] $2\fus_oper_i_alu_shift_rot0__insn[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_shift_rot0__insn[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_shift_rot0__insn[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_shift_rot0__insn[31:0] $3\fus_oper_i_alu_shift_rot0__insn[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + switch \fu_enable [8] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_shift_rot0__insn[31:0] \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__insn + case + assign $3\fus_oper_i_alu_shift_rot0__insn[31:0] 0 + end + end + case + assign $1\fus_oper_i_alu_shift_rot0__insn[31:0] 0 + end + sync always + update \fus_oper_i_alu_shift_rot0__insn $0\fus_oper_i_alu_shift_rot0__insn[31:0] + end + attribute \src "libresoc.v:43976.3-44004.6" + process $proc$libresoc.v:43976$2429 + assign { } { } + assign { } { } + assign $0\fus_cu_issue_i$25[0:0]$2430 $1\fus_cu_issue_i$25[0:0]$2431 + attribute \src "libresoc.v:43977.5-43977.29" + switch \initial + attribute \src "libresoc.v:43977.9-43977.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_cu_issue_i$25[0:0]$2431 $2\fus_cu_issue_i$25[0:0]$2432 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_cu_issue_i$25[0:0]$2432 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_cu_issue_i$25[0:0]$2432 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_cu_issue_i$25[0:0]$2432 $3\fus_cu_issue_i$25[0:0]$2433 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + switch \fu_enable [8] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_cu_issue_i$25[0:0]$2433 \issue_i + case + assign $3\fus_cu_issue_i$25[0:0]$2433 1'0 + end + end + case + assign $1\fus_cu_issue_i$25[0:0]$2431 1'0 + end + sync always + update \fus_cu_issue_i$25 $0\fus_cu_issue_i$25[0:0]$2430 + end + attribute \src "libresoc.v:44005.3-44033.6" + process $proc$libresoc.v:44005$2434 + assign { } { } + assign { } { } + assign $0\fus_cu_rdmaskn_i$27[4:0]$2435 $1\fus_cu_rdmaskn_i$27[4:0]$2436 + attribute \src "libresoc.v:44006.5-44006.29" + switch \initial + attribute \src "libresoc.v:44006.9-44006.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_cu_rdmaskn_i$27[4:0]$2436 $2\fus_cu_rdmaskn_i$27[4:0]$2437 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_cu_rdmaskn_i$27[4:0]$2437 5'00000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_cu_rdmaskn_i$27[4:0]$2437 5'00000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_cu_rdmaskn_i$27[4:0]$2437 $3\fus_cu_rdmaskn_i$27[4:0]$2438 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + switch \fu_enable [8] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_cu_rdmaskn_i$27[4:0]$2438 \$307 + case + assign $3\fus_cu_rdmaskn_i$27[4:0]$2438 5'00000 + end + end + case + assign $1\fus_cu_rdmaskn_i$27[4:0]$2436 5'00000 + end + sync always + update \fus_cu_rdmaskn_i$27 $0\fus_cu_rdmaskn_i$27[4:0]$2435 + end + attribute \src "libresoc.v:44034.3-44062.6" + process $proc$libresoc.v:44034$2439 + assign { } { } + assign { } { } + assign $0\fus_oper_i_ldst_ldst0__insn_type[6:0] $1\fus_oper_i_ldst_ldst0__insn_type[6:0] + attribute \src "libresoc.v:44035.5-44035.29" + switch \initial + attribute \src "libresoc.v:44035.9-44035.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_ldst_ldst0__insn_type[6:0] $2\fus_oper_i_ldst_ldst0__insn_type[6:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_ldst_ldst0__insn_type[6:0] 7'0000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_ldst_ldst0__insn_type[6:0] 7'0000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_ldst_ldst0__insn_type[6:0] $3\fus_oper_i_ldst_ldst0__insn_type[6:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + switch \fu_enable [9] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_ldst_ldst0__insn_type[6:0] \dec_LDST_LDST_LDST__insn_type + case + assign $3\fus_oper_i_ldst_ldst0__insn_type[6:0] 7'0000000 + end + end + case + assign $1\fus_oper_i_ldst_ldst0__insn_type[6:0] 7'0000000 + end + sync always + update \fus_oper_i_ldst_ldst0__insn_type $0\fus_oper_i_ldst_ldst0__insn_type[6:0] + end + attribute \src "libresoc.v:44063.3-44091.6" + process $proc$libresoc.v:44063$2440 + assign { } { } + assign { } { } + assign $0\fus_oper_i_ldst_ldst0__fn_unit[11:0] $1\fus_oper_i_ldst_ldst0__fn_unit[11:0] + attribute \src "libresoc.v:44064.5-44064.29" + switch \initial + attribute \src "libresoc.v:44064.9-44064.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_ldst_ldst0__fn_unit[11:0] $2\fus_oper_i_ldst_ldst0__fn_unit[11:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_ldst_ldst0__fn_unit[11:0] 12'000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_ldst_ldst0__fn_unit[11:0] 12'000000000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_ldst_ldst0__fn_unit[11:0] $3\fus_oper_i_ldst_ldst0__fn_unit[11:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + switch \fu_enable [9] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_ldst_ldst0__fn_unit[11:0] \dec_LDST_LDST_LDST__fn_unit + case + assign $3\fus_oper_i_ldst_ldst0__fn_unit[11:0] 12'000000000000 + end + end + case + assign $1\fus_oper_i_ldst_ldst0__fn_unit[11:0] 12'000000000000 + end + sync always + update \fus_oper_i_ldst_ldst0__fn_unit $0\fus_oper_i_ldst_ldst0__fn_unit[11:0] + end + attribute \src "libresoc.v:44092.3-44121.6" + process $proc$libresoc.v:44092$2441 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fus_oper_i_ldst_ldst0__imm_data__data[63:0] $1\fus_oper_i_ldst_ldst0__imm_data__data[63:0] + assign $0\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] $1\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] + attribute \src "libresoc.v:44093.5-44093.29" + switch \initial + attribute \src "libresoc.v:44093.9-44093.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $1\fus_oper_i_ldst_ldst0__imm_data__data[63:0] $2\fus_oper_i_ldst_ldst0__imm_data__data[63:0] + assign $1\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] $2\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_ldst_ldst0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_ldst_ldst0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign $2\fus_oper_i_ldst_ldst0__imm_data__data[63:0] $3\fus_oper_i_ldst_ldst0__imm_data__data[63:0] + assign $2\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] $3\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + switch \fu_enable [9] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $3\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] $3\fus_oper_i_ldst_ldst0__imm_data__data[63:0] } { \dec_LDST_LDST_LDST__imm_data__ok \dec_LDST_LDST_LDST__imm_data__data } + case + assign $3\fus_oper_i_ldst_ldst0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_ldst_ldst0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] 1'0 + end + sync always + update \fus_oper_i_ldst_ldst0__imm_data__data $0\fus_oper_i_ldst_ldst0__imm_data__data[63:0] + update \fus_oper_i_ldst_ldst0__imm_data__ok $0\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] + end + attribute \src "libresoc.v:44122.3-44150.6" + process $proc$libresoc.v:44122$2442 + assign { } { } + assign { } { } + assign $0\fus_oper_i_ldst_ldst0__zero_a[0:0] $1\fus_oper_i_ldst_ldst0__zero_a[0:0] + attribute \src "libresoc.v:44123.5-44123.29" + switch \initial + attribute \src "libresoc.v:44123.9-44123.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_ldst_ldst0__zero_a[0:0] $2\fus_oper_i_ldst_ldst0__zero_a[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_ldst_ldst0__zero_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_ldst_ldst0__zero_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_ldst_ldst0__zero_a[0:0] $3\fus_oper_i_ldst_ldst0__zero_a[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + switch \fu_enable [9] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_ldst_ldst0__zero_a[0:0] \dec_LDST_LDST_LDST__zero_a + case + assign $3\fus_oper_i_ldst_ldst0__zero_a[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_ldst_ldst0__zero_a[0:0] 1'0 + end + sync always + update \fus_oper_i_ldst_ldst0__zero_a $0\fus_oper_i_ldst_ldst0__zero_a[0:0] + end + attribute \src "libresoc.v:44151.3-44180.6" + process $proc$libresoc.v:44151$2443 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fus_oper_i_ldst_ldst0__rc__ok[0:0] $1\fus_oper_i_ldst_ldst0__rc__ok[0:0] + assign $0\fus_oper_i_ldst_ldst0__rc__rc[0:0] $1\fus_oper_i_ldst_ldst0__rc__rc[0:0] + attribute \src "libresoc.v:44152.5-44152.29" + switch \initial + attribute \src "libresoc.v:44152.9-44152.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $1\fus_oper_i_ldst_ldst0__rc__ok[0:0] $2\fus_oper_i_ldst_ldst0__rc__ok[0:0] + assign $1\fus_oper_i_ldst_ldst0__rc__rc[0:0] $2\fus_oper_i_ldst_ldst0__rc__rc[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_ldst_ldst0__rc__ok[0:0] 1'0 + assign $2\fus_oper_i_ldst_ldst0__rc__rc[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_ldst_ldst0__rc__ok[0:0] 1'0 + assign $2\fus_oper_i_ldst_ldst0__rc__rc[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign $2\fus_oper_i_ldst_ldst0__rc__ok[0:0] $3\fus_oper_i_ldst_ldst0__rc__ok[0:0] + assign $2\fus_oper_i_ldst_ldst0__rc__rc[0:0] $3\fus_oper_i_ldst_ldst0__rc__rc[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + switch \fu_enable [9] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $3\fus_oper_i_ldst_ldst0__rc__ok[0:0] $3\fus_oper_i_ldst_ldst0__rc__rc[0:0] } { \dec_LDST_LDST_LDST__rc__ok \dec_LDST_LDST_LDST__rc__rc } + case + assign $3\fus_oper_i_ldst_ldst0__rc__ok[0:0] 1'0 + assign $3\fus_oper_i_ldst_ldst0__rc__rc[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_ldst_ldst0__rc__ok[0:0] 1'0 + assign $1\fus_oper_i_ldst_ldst0__rc__rc[0:0] 1'0 + end + sync always + update \fus_oper_i_ldst_ldst0__rc__ok $0\fus_oper_i_ldst_ldst0__rc__ok[0:0] + update \fus_oper_i_ldst_ldst0__rc__rc $0\fus_oper_i_ldst_ldst0__rc__rc[0:0] + end + attribute \src "libresoc.v:44181.3-44210.6" + process $proc$libresoc.v:44181$2444 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fus_oper_i_ldst_ldst0__oe__oe[0:0] $1\fus_oper_i_ldst_ldst0__oe__oe[0:0] + assign $0\fus_oper_i_ldst_ldst0__oe__ok[0:0] $1\fus_oper_i_ldst_ldst0__oe__ok[0:0] + attribute \src "libresoc.v:44182.5-44182.29" + switch \initial + attribute \src "libresoc.v:44182.9-44182.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $1\fus_oper_i_ldst_ldst0__oe__oe[0:0] $2\fus_oper_i_ldst_ldst0__oe__oe[0:0] + assign $1\fus_oper_i_ldst_ldst0__oe__ok[0:0] $2\fus_oper_i_ldst_ldst0__oe__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_ldst_ldst0__oe__oe[0:0] 1'0 + assign $2\fus_oper_i_ldst_ldst0__oe__ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_ldst_ldst0__oe__oe[0:0] 1'0 + assign $2\fus_oper_i_ldst_ldst0__oe__ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign $2\fus_oper_i_ldst_ldst0__oe__oe[0:0] $3\fus_oper_i_ldst_ldst0__oe__oe[0:0] + assign $2\fus_oper_i_ldst_ldst0__oe__ok[0:0] $3\fus_oper_i_ldst_ldst0__oe__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + switch \fu_enable [9] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $3\fus_oper_i_ldst_ldst0__oe__ok[0:0] $3\fus_oper_i_ldst_ldst0__oe__oe[0:0] } { \dec_LDST_LDST_LDST__oe__ok \dec_LDST_LDST_LDST__oe__oe } + case + assign $3\fus_oper_i_ldst_ldst0__oe__oe[0:0] 1'0 + assign $3\fus_oper_i_ldst_ldst0__oe__ok[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_ldst_ldst0__oe__oe[0:0] 1'0 + assign $1\fus_oper_i_ldst_ldst0__oe__ok[0:0] 1'0 + end + sync always + update \fus_oper_i_ldst_ldst0__oe__oe $0\fus_oper_i_ldst_ldst0__oe__oe[0:0] + update \fus_oper_i_ldst_ldst0__oe__ok $0\fus_oper_i_ldst_ldst0__oe__ok[0:0] + end + attribute \src "libresoc.v:44211.3-44239.6" + process $proc$libresoc.v:44211$2445 + assign { } { } + assign { } { } + assign $0\fus_oper_i_ldst_ldst0__is_32bit[0:0] $1\fus_oper_i_ldst_ldst0__is_32bit[0:0] + attribute \src "libresoc.v:44212.5-44212.29" + switch \initial + attribute \src "libresoc.v:44212.9-44212.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_ldst_ldst0__is_32bit[0:0] $2\fus_oper_i_ldst_ldst0__is_32bit[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_ldst_ldst0__is_32bit[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_ldst_ldst0__is_32bit[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_ldst_ldst0__is_32bit[0:0] $3\fus_oper_i_ldst_ldst0__is_32bit[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + switch \fu_enable [9] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_ldst_ldst0__is_32bit[0:0] \dec_LDST_LDST_LDST__is_32bit + case + assign $3\fus_oper_i_ldst_ldst0__is_32bit[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_ldst_ldst0__is_32bit[0:0] 1'0 + end + sync always + update \fus_oper_i_ldst_ldst0__is_32bit $0\fus_oper_i_ldst_ldst0__is_32bit[0:0] + end + attribute \src "libresoc.v:44240.3-44268.6" + process $proc$libresoc.v:44240$2446 + assign { } { } + assign { } { } + assign $0\fus_oper_i_ldst_ldst0__is_signed[0:0] $1\fus_oper_i_ldst_ldst0__is_signed[0:0] + attribute \src "libresoc.v:44241.5-44241.29" + switch \initial + attribute \src "libresoc.v:44241.9-44241.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_ldst_ldst0__is_signed[0:0] $2\fus_oper_i_ldst_ldst0__is_signed[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_ldst_ldst0__is_signed[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_ldst_ldst0__is_signed[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_ldst_ldst0__is_signed[0:0] $3\fus_oper_i_ldst_ldst0__is_signed[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + switch \fu_enable [9] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_ldst_ldst0__is_signed[0:0] \dec_LDST_LDST_LDST__is_signed + case + assign $3\fus_oper_i_ldst_ldst0__is_signed[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_ldst_ldst0__is_signed[0:0] 1'0 + end + sync always + update \fus_oper_i_ldst_ldst0__is_signed $0\fus_oper_i_ldst_ldst0__is_signed[0:0] + end + attribute \src "libresoc.v:44269.3-44297.6" + process $proc$libresoc.v:44269$2447 + assign { } { } + assign { } { } + assign $0\fus_oper_i_ldst_ldst0__data_len[3:0] $1\fus_oper_i_ldst_ldst0__data_len[3:0] + attribute \src "libresoc.v:44270.5-44270.29" + switch \initial + attribute \src "libresoc.v:44270.9-44270.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_ldst_ldst0__data_len[3:0] $2\fus_oper_i_ldst_ldst0__data_len[3:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_ldst_ldst0__data_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_ldst_ldst0__data_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_ldst_ldst0__data_len[3:0] $3\fus_oper_i_ldst_ldst0__data_len[3:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + switch \fu_enable [9] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_ldst_ldst0__data_len[3:0] \dec_LDST_LDST_LDST__data_len + case + assign $3\fus_oper_i_ldst_ldst0__data_len[3:0] 4'0000 + end + end + case + assign $1\fus_oper_i_ldst_ldst0__data_len[3:0] 4'0000 + end + sync always + update \fus_oper_i_ldst_ldst0__data_len $0\fus_oper_i_ldst_ldst0__data_len[3:0] + end + attribute \src "libresoc.v:44298.3-44326.6" + process $proc$libresoc.v:44298$2448 + assign { } { } + assign { } { } + assign $0\fus_oper_i_ldst_ldst0__byte_reverse[0:0] $1\fus_oper_i_ldst_ldst0__byte_reverse[0:0] + attribute \src "libresoc.v:44299.5-44299.29" + switch \initial + attribute \src "libresoc.v:44299.9-44299.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_ldst_ldst0__byte_reverse[0:0] $2\fus_oper_i_ldst_ldst0__byte_reverse[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_ldst_ldst0__byte_reverse[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_ldst_ldst0__byte_reverse[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_ldst_ldst0__byte_reverse[0:0] $3\fus_oper_i_ldst_ldst0__byte_reverse[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + switch \fu_enable [9] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_ldst_ldst0__byte_reverse[0:0] \dec_LDST_LDST_LDST__byte_reverse + case + assign $3\fus_oper_i_ldst_ldst0__byte_reverse[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_ldst_ldst0__byte_reverse[0:0] 1'0 + end + sync always + update \fus_oper_i_ldst_ldst0__byte_reverse $0\fus_oper_i_ldst_ldst0__byte_reverse[0:0] + end + attribute \src "libresoc.v:44327.3-44355.6" + process $proc$libresoc.v:44327$2449 + assign { } { } + assign { } { } + assign $0\fus_oper_i_ldst_ldst0__sign_extend[0:0] $1\fus_oper_i_ldst_ldst0__sign_extend[0:0] + attribute \src "libresoc.v:44328.5-44328.29" + switch \initial + attribute \src "libresoc.v:44328.9-44328.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_ldst_ldst0__sign_extend[0:0] $2\fus_oper_i_ldst_ldst0__sign_extend[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_ldst_ldst0__sign_extend[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_ldst_ldst0__sign_extend[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_ldst_ldst0__sign_extend[0:0] $3\fus_oper_i_ldst_ldst0__sign_extend[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + switch \fu_enable [9] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_ldst_ldst0__sign_extend[0:0] \dec_LDST_LDST_LDST__sign_extend + case + assign $3\fus_oper_i_ldst_ldst0__sign_extend[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_ldst_ldst0__sign_extend[0:0] 1'0 + end + sync always + update \fus_oper_i_ldst_ldst0__sign_extend $0\fus_oper_i_ldst_ldst0__sign_extend[0:0] + end + attribute \src "libresoc.v:44356.3-44384.6" + process $proc$libresoc.v:44356$2450 + assign { } { } + assign { } { } + assign $0\fus_oper_i_ldst_ldst0__ldst_mode[1:0] $1\fus_oper_i_ldst_ldst0__ldst_mode[1:0] + attribute \src "libresoc.v:44357.5-44357.29" + switch \initial + attribute \src "libresoc.v:44357.9-44357.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_ldst_ldst0__ldst_mode[1:0] $2\fus_oper_i_ldst_ldst0__ldst_mode[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_ldst_ldst0__ldst_mode[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_ldst_ldst0__ldst_mode[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_ldst_ldst0__ldst_mode[1:0] $3\fus_oper_i_ldst_ldst0__ldst_mode[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + switch \fu_enable [9] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_ldst_ldst0__ldst_mode[1:0] \dec_LDST_LDST_LDST__ldst_mode + case + assign $3\fus_oper_i_ldst_ldst0__ldst_mode[1:0] 2'00 + end + end + case + assign $1\fus_oper_i_ldst_ldst0__ldst_mode[1:0] 2'00 + end + sync always + update \fus_oper_i_ldst_ldst0__ldst_mode $0\fus_oper_i_ldst_ldst0__ldst_mode[1:0] + end + attribute \src "libresoc.v:44385.3-44413.6" + process $proc$libresoc.v:44385$2451 + assign { } { } + assign { } { } + assign $0\fus_oper_i_ldst_ldst0__insn[31:0] $1\fus_oper_i_ldst_ldst0__insn[31:0] + attribute \src "libresoc.v:44386.5-44386.29" + switch \initial + attribute \src "libresoc.v:44386.9-44386.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_ldst_ldst0__insn[31:0] $2\fus_oper_i_ldst_ldst0__insn[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_ldst_ldst0__insn[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_ldst_ldst0__insn[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_ldst_ldst0__insn[31:0] $3\fus_oper_i_ldst_ldst0__insn[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + switch \fu_enable [9] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_ldst_ldst0__insn[31:0] \dec_LDST_LDST_LDST__insn + case + assign $3\fus_oper_i_ldst_ldst0__insn[31:0] 0 + end + end + case + assign $1\fus_oper_i_ldst_ldst0__insn[31:0] 0 + end + sync always + update \fus_oper_i_ldst_ldst0__insn $0\fus_oper_i_ldst_ldst0__insn[31:0] + end + attribute \src "libresoc.v:44414.3-44442.6" + process $proc$libresoc.v:44414$2452 + assign { } { } + assign { } { } + assign $0\fus_cu_issue_i$28[0:0]$2453 $1\fus_cu_issue_i$28[0:0]$2454 + attribute \src "libresoc.v:44415.5-44415.29" + switch \initial + attribute \src "libresoc.v:44415.9-44415.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_cu_issue_i$28[0:0]$2454 $2\fus_cu_issue_i$28[0:0]$2455 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_cu_issue_i$28[0:0]$2455 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_cu_issue_i$28[0:0]$2455 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_cu_issue_i$28[0:0]$2455 $3\fus_cu_issue_i$28[0:0]$2456 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + switch \fu_enable [9] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_cu_issue_i$28[0:0]$2456 \issue_i + case + assign $3\fus_cu_issue_i$28[0:0]$2456 1'0 + end + end + case + assign $1\fus_cu_issue_i$28[0:0]$2454 1'0 + end + sync always + update \fus_cu_issue_i$28 $0\fus_cu_issue_i$28[0:0]$2453 + end + attribute \src "libresoc.v:44443.3-44471.6" + process $proc$libresoc.v:44443$2457 + assign { } { } + assign { } { } + assign $0\fus_cu_rdmaskn_i$30[2:0]$2458 $1\fus_cu_rdmaskn_i$30[2:0]$2459 + attribute \src "libresoc.v:44444.5-44444.29" + switch \initial + attribute \src "libresoc.v:44444.9-44444.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_cu_rdmaskn_i$30[2:0]$2459 $2\fus_cu_rdmaskn_i$30[2:0]$2460 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_cu_rdmaskn_i$30[2:0]$2460 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_cu_rdmaskn_i$30[2:0]$2460 3'000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_cu_rdmaskn_i$30[2:0]$2460 $3\fus_cu_rdmaskn_i$30[2:0]$2461 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + switch \fu_enable [9] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_cu_rdmaskn_i$30[2:0]$2461 \$329 + case + assign $3\fus_cu_rdmaskn_i$30[2:0]$2461 3'000 + end + end + case + assign $1\fus_cu_rdmaskn_i$30[2:0]$2459 3'000 + end + sync always + update \fus_cu_rdmaskn_i$30 $0\fus_cu_rdmaskn_i$30[2:0]$2458 + end + attribute \src "libresoc.v:44472.3-44480.6" + process $proc$libresoc.v:44472$2462 + assign { } { } + assign { } { } + assign $0\dp_INT_ra_alu0_0$next[0:0]$2463 $1\dp_INT_ra_alu0_0$next[0:0]$2464 + attribute \src "libresoc.v:44473.5-44473.29" + switch \initial + attribute \src "libresoc.v:44473.9-44473.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_INT_ra_alu0_0$next[0:0]$2464 1'0 + case + assign $1\dp_INT_ra_alu0_0$next[0:0]$2464 \rp_INT_ra_alu0_0 + end + sync always + update \dp_INT_ra_alu0_0$next $0\dp_INT_ra_alu0_0$next[0:0]$2463 + end + attribute \src "libresoc.v:44481.3-44490.6" + process $proc$libresoc.v:44481$2465 + assign { } { } + assign { } { } + assign $0\fus_src1_i[63:0] $1\fus_src1_i[63:0] + attribute \src "libresoc.v:44482.5-44482.29" + switch \initial + attribute \src "libresoc.v:44482.9-44482.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + switch \dp_INT_ra_alu0_0 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src1_i[63:0] \int_src1__data_o + case + assign $1\fus_src1_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_src1_i $0\fus_src1_i[63:0] + end + attribute \src "libresoc.v:44491.3-44499.6" + process $proc$libresoc.v:44491$2466 + assign { } { } + assign { } { } + assign $0\dp_INT_ra_cr0_1$next[0:0]$2467 $1\dp_INT_ra_cr0_1$next[0:0]$2468 + attribute \src "libresoc.v:44492.5-44492.29" + switch \initial + attribute \src "libresoc.v:44492.9-44492.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_INT_ra_cr0_1$next[0:0]$2468 1'0 + case + assign $1\dp_INT_ra_cr0_1$next[0:0]$2468 \rp_INT_ra_cr0_1 + end + sync always + update \dp_INT_ra_cr0_1$next $0\dp_INT_ra_cr0_1$next[0:0]$2467 + end + attribute \src "libresoc.v:44500.3-44509.6" + process $proc$libresoc.v:44500$2469 + assign { } { } + assign { } { } + assign $0\fus_src1_i$33[63:0]$2470 $1\fus_src1_i$33[63:0]$2471 + attribute \src "libresoc.v:44501.5-44501.29" + switch \initial + attribute \src "libresoc.v:44501.9-44501.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + switch \dp_INT_ra_cr0_1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src1_i$33[63:0]$2471 \int_src1__data_o + case + assign $1\fus_src1_i$33[63:0]$2471 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_src1_i$33 $0\fus_src1_i$33[63:0]$2470 + end + attribute \src "libresoc.v:44510.3-44518.6" + process $proc$libresoc.v:44510$2472 + assign { } { } + assign { } { } + assign $0\dp_INT_ra_trap0_2$next[0:0]$2473 $1\dp_INT_ra_trap0_2$next[0:0]$2474 + attribute \src "libresoc.v:44511.5-44511.29" + switch \initial + attribute \src "libresoc.v:44511.9-44511.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_INT_ra_trap0_2$next[0:0]$2474 1'0 + case + assign $1\dp_INT_ra_trap0_2$next[0:0]$2474 \rp_INT_ra_trap0_2 + end + sync always + update \dp_INT_ra_trap0_2$next $0\dp_INT_ra_trap0_2$next[0:0]$2473 + end + attribute \src "libresoc.v:44519.3-44528.6" + process $proc$libresoc.v:44519$2475 + assign { } { } + assign { } { } + assign $0\fus_src1_i$36[63:0]$2476 $1\fus_src1_i$36[63:0]$2477 + attribute \src "libresoc.v:44520.5-44520.29" + switch \initial + attribute \src "libresoc.v:44520.9-44520.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + switch \dp_INT_ra_trap0_2 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src1_i$36[63:0]$2477 \int_src1__data_o + case + assign $1\fus_src1_i$36[63:0]$2477 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_src1_i$36 $0\fus_src1_i$36[63:0]$2476 + end + attribute \src "libresoc.v:44529.3-44537.6" + process $proc$libresoc.v:44529$2478 + assign { } { } + assign { } { } + assign $0\dp_INT_ra_logical0_3$next[0:0]$2479 $1\dp_INT_ra_logical0_3$next[0:0]$2480 + attribute \src "libresoc.v:44530.5-44530.29" + switch \initial + attribute \src "libresoc.v:44530.9-44530.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_INT_ra_logical0_3$next[0:0]$2480 1'0 + case + assign $1\dp_INT_ra_logical0_3$next[0:0]$2480 \rp_INT_ra_logical0_3 + end + sync always + update \dp_INT_ra_logical0_3$next $0\dp_INT_ra_logical0_3$next[0:0]$2479 + end + attribute \src "libresoc.v:44538.3-44547.6" + process $proc$libresoc.v:44538$2481 + assign { } { } + assign { } { } + assign $0\fus_src1_i$39[63:0]$2482 $1\fus_src1_i$39[63:0]$2483 + attribute \src "libresoc.v:44539.5-44539.29" + switch \initial + attribute \src "libresoc.v:44539.9-44539.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + switch \dp_INT_ra_logical0_3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src1_i$39[63:0]$2483 \int_src1__data_o + case + assign $1\fus_src1_i$39[63:0]$2483 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_src1_i$39 $0\fus_src1_i$39[63:0]$2482 + end + attribute \src "libresoc.v:44548.3-44556.6" + process $proc$libresoc.v:44548$2484 + assign { } { } + assign { } { } + assign $0\dp_INT_ra_spr0_4$next[0:0]$2485 $1\dp_INT_ra_spr0_4$next[0:0]$2486 + attribute \src "libresoc.v:44549.5-44549.29" + switch \initial + attribute \src "libresoc.v:44549.9-44549.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_INT_ra_spr0_4$next[0:0]$2486 1'0 + case + assign $1\dp_INT_ra_spr0_4$next[0:0]$2486 \rp_INT_ra_spr0_4 + end + sync always + update \dp_INT_ra_spr0_4$next $0\dp_INT_ra_spr0_4$next[0:0]$2485 + end + attribute \src "libresoc.v:44557.3-44566.6" + process $proc$libresoc.v:44557$2487 + assign { } { } + assign { } { } + assign $0\fus_src1_i$42[63:0]$2488 $1\fus_src1_i$42[63:0]$2489 + attribute \src "libresoc.v:44558.5-44558.29" + switch \initial + attribute \src "libresoc.v:44558.9-44558.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + switch \dp_INT_ra_spr0_4 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src1_i$42[63:0]$2489 \int_src1__data_o + case + assign $1\fus_src1_i$42[63:0]$2489 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_src1_i$42 $0\fus_src1_i$42[63:0]$2488 + end + attribute \src "libresoc.v:44567.3-44575.6" + process $proc$libresoc.v:44567$2490 + assign { } { } + assign { } { } + assign $0\dp_INT_ra_div0_5$next[0:0]$2491 $1\dp_INT_ra_div0_5$next[0:0]$2492 + attribute \src "libresoc.v:44568.5-44568.29" + switch \initial + attribute \src "libresoc.v:44568.9-44568.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_INT_ra_div0_5$next[0:0]$2492 1'0 + case + assign $1\dp_INT_ra_div0_5$next[0:0]$2492 \rp_INT_ra_div0_5 + end + sync always + update \dp_INT_ra_div0_5$next $0\dp_INT_ra_div0_5$next[0:0]$2491 + end + attribute \src "libresoc.v:44576.3-44585.6" + process $proc$libresoc.v:44576$2493 + assign { } { } + assign { } { } + assign $0\fus_src1_i$45[63:0]$2494 $1\fus_src1_i$45[63:0]$2495 + attribute \src "libresoc.v:44577.5-44577.29" + switch \initial + attribute \src "libresoc.v:44577.9-44577.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + switch \dp_INT_ra_div0_5 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src1_i$45[63:0]$2495 \int_src1__data_o + case + assign $1\fus_src1_i$45[63:0]$2495 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_src1_i$45 $0\fus_src1_i$45[63:0]$2494 + end + attribute \src "libresoc.v:44586.3-44594.6" + process $proc$libresoc.v:44586$2496 + assign { } { } + assign { } { } + assign $0\dp_INT_ra_mul0_6$next[0:0]$2497 $1\dp_INT_ra_mul0_6$next[0:0]$2498 + attribute \src "libresoc.v:44587.5-44587.29" + switch \initial + attribute \src "libresoc.v:44587.9-44587.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_INT_ra_mul0_6$next[0:0]$2498 1'0 + case + assign $1\dp_INT_ra_mul0_6$next[0:0]$2498 \rp_INT_ra_mul0_6 + end + sync always + update \dp_INT_ra_mul0_6$next $0\dp_INT_ra_mul0_6$next[0:0]$2497 + end + attribute \src "libresoc.v:44595.3-44604.6" + process $proc$libresoc.v:44595$2499 + assign { } { } + assign { } { } + assign $0\fus_src1_i$48[63:0]$2500 $1\fus_src1_i$48[63:0]$2501 + attribute \src "libresoc.v:44596.5-44596.29" + switch \initial + attribute \src "libresoc.v:44596.9-44596.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + switch \dp_INT_ra_mul0_6 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src1_i$48[63:0]$2501 \int_src1__data_o + case + assign $1\fus_src1_i$48[63:0]$2501 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_src1_i$48 $0\fus_src1_i$48[63:0]$2500 + end + attribute \src "libresoc.v:44605.3-44613.6" + process $proc$libresoc.v:44605$2502 + assign { } { } + assign { } { } + assign $0\dp_INT_ra_shiftrot0_7$next[0:0]$2503 $1\dp_INT_ra_shiftrot0_7$next[0:0]$2504 + attribute \src "libresoc.v:44606.5-44606.29" + switch \initial + attribute \src "libresoc.v:44606.9-44606.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_INT_ra_shiftrot0_7$next[0:0]$2504 1'0 + case + assign $1\dp_INT_ra_shiftrot0_7$next[0:0]$2504 \rp_INT_ra_shiftrot0_7 + end + sync always + update \dp_INT_ra_shiftrot0_7$next $0\dp_INT_ra_shiftrot0_7$next[0:0]$2503 + end + attribute \src "libresoc.v:44614.3-44623.6" + process $proc$libresoc.v:44614$2505 + assign { } { } + assign { } { } + assign $0\fus_src1_i$51[63:0]$2506 $1\fus_src1_i$51[63:0]$2507 + attribute \src "libresoc.v:44615.5-44615.29" + switch \initial + attribute \src "libresoc.v:44615.9-44615.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + switch \dp_INT_ra_shiftrot0_7 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src1_i$51[63:0]$2507 \int_src1__data_o + case + assign $1\fus_src1_i$51[63:0]$2507 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_src1_i$51 $0\fus_src1_i$51[63:0]$2506 + end + attribute \src "libresoc.v:44624.3-44632.6" + process $proc$libresoc.v:44624$2508 + assign { } { } + assign { } { } + assign $0\dp_INT_ra_ldst0_8$next[0:0]$2509 $1\dp_INT_ra_ldst0_8$next[0:0]$2510 + attribute \src "libresoc.v:44625.5-44625.29" + switch \initial + attribute \src "libresoc.v:44625.9-44625.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_INT_ra_ldst0_8$next[0:0]$2510 1'0 + case + assign $1\dp_INT_ra_ldst0_8$next[0:0]$2510 \rp_INT_ra_ldst0_8 + end + sync always + update \dp_INT_ra_ldst0_8$next $0\dp_INT_ra_ldst0_8$next[0:0]$2509 + end + attribute \src "libresoc.v:44633.3-44642.6" + process $proc$libresoc.v:44633$2511 + assign { } { } + assign { } { } + assign $0\fus_src1_i$54[63:0]$2512 $1\fus_src1_i$54[63:0]$2513 + attribute \src "libresoc.v:44634.5-44634.29" + switch \initial + attribute \src "libresoc.v:44634.9-44634.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + switch \dp_INT_ra_ldst0_8 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src1_i$54[63:0]$2513 \int_src1__data_o + case + assign $1\fus_src1_i$54[63:0]$2513 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_src1_i$54 $0\fus_src1_i$54[63:0]$2512 + end + attribute \src "libresoc.v:44643.3-44651.6" + process $proc$libresoc.v:44643$2514 + assign { } { } + assign { } { } + assign $0\dp_INT_rb_alu0_0$next[0:0]$2515 $1\dp_INT_rb_alu0_0$next[0:0]$2516 + attribute \src "libresoc.v:44644.5-44644.29" + switch \initial + attribute \src "libresoc.v:44644.9-44644.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_INT_rb_alu0_0$next[0:0]$2516 1'0 + case + assign $1\dp_INT_rb_alu0_0$next[0:0]$2516 \rp_INT_rb_alu0_0 + end + sync always + update \dp_INT_rb_alu0_0$next $0\dp_INT_rb_alu0_0$next[0:0]$2515 + end + attribute \src "libresoc.v:44652.3-44661.6" + process $proc$libresoc.v:44652$2517 + assign { } { } + assign { } { } + assign $0\fus_src2_i[63:0] $1\fus_src2_i[63:0] + attribute \src "libresoc.v:44653.5-44653.29" + switch \initial + attribute \src "libresoc.v:44653.9-44653.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + switch \dp_INT_rb_alu0_0 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src2_i[63:0] \int_src2__data_o + case + assign $1\fus_src2_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_src2_i $0\fus_src2_i[63:0] + end + attribute \src "libresoc.v:44662.3-44670.6" + process $proc$libresoc.v:44662$2518 + assign { } { } + assign { } { } + assign $0\dp_INT_rb_cr0_1$next[0:0]$2519 $1\dp_INT_rb_cr0_1$next[0:0]$2520 + attribute \src "libresoc.v:44663.5-44663.29" + switch \initial + attribute \src "libresoc.v:44663.9-44663.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_INT_rb_cr0_1$next[0:0]$2520 1'0 + case + assign $1\dp_INT_rb_cr0_1$next[0:0]$2520 \rp_INT_rb_cr0_1 + end + sync always + update \dp_INT_rb_cr0_1$next $0\dp_INT_rb_cr0_1$next[0:0]$2519 + end + attribute \src "libresoc.v:44671.3-44680.6" + process $proc$libresoc.v:44671$2521 + assign { } { } + assign { } { } + assign $0\fus_src2_i$55[63:0]$2522 $1\fus_src2_i$55[63:0]$2523 + attribute \src "libresoc.v:44672.5-44672.29" + switch \initial + attribute \src "libresoc.v:44672.9-44672.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + switch \dp_INT_rb_cr0_1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src2_i$55[63:0]$2523 \int_src2__data_o + case + assign $1\fus_src2_i$55[63:0]$2523 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_src2_i$55 $0\fus_src2_i$55[63:0]$2522 + end + attribute \src "libresoc.v:44681.3-44689.6" + process $proc$libresoc.v:44681$2524 + assign { } { } + assign { } { } + assign $0\dp_INT_rb_trap0_2$next[0:0]$2525 $1\dp_INT_rb_trap0_2$next[0:0]$2526 + attribute \src "libresoc.v:44682.5-44682.29" + switch \initial + attribute \src "libresoc.v:44682.9-44682.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_INT_rb_trap0_2$next[0:0]$2526 1'0 + case + assign $1\dp_INT_rb_trap0_2$next[0:0]$2526 \rp_INT_rb_trap0_2 + end + sync always + update \dp_INT_rb_trap0_2$next $0\dp_INT_rb_trap0_2$next[0:0]$2525 + end + attribute \src "libresoc.v:44690.3-44699.6" + process $proc$libresoc.v:44690$2527 + assign { } { } + assign { } { } + assign $0\fus_src2_i$56[63:0]$2528 $1\fus_src2_i$56[63:0]$2529 + attribute \src "libresoc.v:44691.5-44691.29" + switch \initial + attribute \src "libresoc.v:44691.9-44691.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + switch \dp_INT_rb_trap0_2 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src2_i$56[63:0]$2529 \int_src2__data_o + case + assign $1\fus_src2_i$56[63:0]$2529 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_src2_i$56 $0\fus_src2_i$56[63:0]$2528 + end + attribute \src "libresoc.v:44700.3-44708.6" + process $proc$libresoc.v:44700$2530 + assign { } { } + assign { } { } + assign $0\dp_INT_rb_logical0_3$next[0:0]$2531 $1\dp_INT_rb_logical0_3$next[0:0]$2532 + attribute \src "libresoc.v:44701.5-44701.29" + switch \initial + attribute \src "libresoc.v:44701.9-44701.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_INT_rb_logical0_3$next[0:0]$2532 1'0 + case + assign $1\dp_INT_rb_logical0_3$next[0:0]$2532 \rp_INT_rb_logical0_3 + end + sync always + update \dp_INT_rb_logical0_3$next $0\dp_INT_rb_logical0_3$next[0:0]$2531 + end + attribute \src "libresoc.v:44709.3-44718.6" + process $proc$libresoc.v:44709$2533 + assign { } { } + assign { } { } + assign $0\fus_src2_i$57[63:0]$2534 $1\fus_src2_i$57[63:0]$2535 + attribute \src "libresoc.v:44710.5-44710.29" + switch \initial + attribute \src "libresoc.v:44710.9-44710.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + switch \dp_INT_rb_logical0_3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src2_i$57[63:0]$2535 \int_src2__data_o + case + assign $1\fus_src2_i$57[63:0]$2535 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_src2_i$57 $0\fus_src2_i$57[63:0]$2534 + end + attribute \src "libresoc.v:44719.3-44727.6" + process $proc$libresoc.v:44719$2536 + assign { } { } + assign { } { } + assign $0\dp_INT_rb_div0_4$next[0:0]$2537 $1\dp_INT_rb_div0_4$next[0:0]$2538 + attribute \src "libresoc.v:44720.5-44720.29" + switch \initial + attribute \src "libresoc.v:44720.9-44720.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_INT_rb_div0_4$next[0:0]$2538 1'0 + case + assign $1\dp_INT_rb_div0_4$next[0:0]$2538 \rp_INT_rb_div0_4 + end + sync always + update \dp_INT_rb_div0_4$next $0\dp_INT_rb_div0_4$next[0:0]$2537 + end + attribute \src "libresoc.v:44728.3-44737.6" + process $proc$libresoc.v:44728$2539 + assign { } { } + assign { } { } + assign $0\fus_src2_i$58[63:0]$2540 $1\fus_src2_i$58[63:0]$2541 + attribute \src "libresoc.v:44729.5-44729.29" + switch \initial + attribute \src "libresoc.v:44729.9-44729.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + switch \dp_INT_rb_div0_4 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src2_i$58[63:0]$2541 \int_src2__data_o + case + assign $1\fus_src2_i$58[63:0]$2541 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_src2_i$58 $0\fus_src2_i$58[63:0]$2540 + end + attribute \src "libresoc.v:44738.3-44746.6" + process $proc$libresoc.v:44738$2542 + assign { } { } + assign { } { } + assign $0\dp_INT_rb_mul0_5$next[0:0]$2543 $1\dp_INT_rb_mul0_5$next[0:0]$2544 + attribute \src "libresoc.v:44739.5-44739.29" + switch \initial + attribute \src "libresoc.v:44739.9-44739.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_INT_rb_mul0_5$next[0:0]$2544 1'0 + case + assign $1\dp_INT_rb_mul0_5$next[0:0]$2544 \rp_INT_rb_mul0_5 + end + sync always + update \dp_INT_rb_mul0_5$next $0\dp_INT_rb_mul0_5$next[0:0]$2543 + end + attribute \src "libresoc.v:44747.3-44756.6" + process $proc$libresoc.v:44747$2545 + assign { } { } + assign { } { } + assign $0\fus_src2_i$59[63:0]$2546 $1\fus_src2_i$59[63:0]$2547 + attribute \src "libresoc.v:44748.5-44748.29" + switch \initial + attribute \src "libresoc.v:44748.9-44748.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + switch \dp_INT_rb_mul0_5 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src2_i$59[63:0]$2547 \int_src2__data_o + case + assign $1\fus_src2_i$59[63:0]$2547 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_src2_i$59 $0\fus_src2_i$59[63:0]$2546 + end + attribute \src "libresoc.v:44757.3-44765.6" + process $proc$libresoc.v:44757$2548 + assign { } { } + assign { } { } + assign $0\dp_INT_rb_shiftrot0_6$next[0:0]$2549 $1\dp_INT_rb_shiftrot0_6$next[0:0]$2550 + attribute \src "libresoc.v:44758.5-44758.29" + switch \initial + attribute \src "libresoc.v:44758.9-44758.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_INT_rb_shiftrot0_6$next[0:0]$2550 1'0 + case + assign $1\dp_INT_rb_shiftrot0_6$next[0:0]$2550 \rp_INT_rb_shiftrot0_6 + end + sync always + update \dp_INT_rb_shiftrot0_6$next $0\dp_INT_rb_shiftrot0_6$next[0:0]$2549 + end + attribute \src "libresoc.v:44766.3-44775.6" + process $proc$libresoc.v:44766$2551 + assign { } { } + assign { } { } + assign $0\fus_src2_i$60[63:0]$2552 $1\fus_src2_i$60[63:0]$2553 + attribute \src "libresoc.v:44767.5-44767.29" + switch \initial + attribute \src "libresoc.v:44767.9-44767.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + switch \dp_INT_rb_shiftrot0_6 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src2_i$60[63:0]$2553 \int_src2__data_o + case + assign $1\fus_src2_i$60[63:0]$2553 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_src2_i$60 $0\fus_src2_i$60[63:0]$2552 + end + attribute \src "libresoc.v:44776.3-44784.6" + process $proc$libresoc.v:44776$2554 + assign { } { } + assign { } { } + assign $0\dp_INT_rb_ldst0_7$next[0:0]$2555 $1\dp_INT_rb_ldst0_7$next[0:0]$2556 + attribute \src "libresoc.v:44777.5-44777.29" + switch \initial + attribute \src "libresoc.v:44777.9-44777.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_INT_rb_ldst0_7$next[0:0]$2556 1'0 + case + assign $1\dp_INT_rb_ldst0_7$next[0:0]$2556 \rp_INT_rb_ldst0_7 + end + sync always + update \dp_INT_rb_ldst0_7$next $0\dp_INT_rb_ldst0_7$next[0:0]$2555 + end + attribute \src "libresoc.v:44785.3-44794.6" + process $proc$libresoc.v:44785$2557 + assign { } { } + assign { } { } + assign $0\fus_src2_i$61[63:0]$2558 $1\fus_src2_i$61[63:0]$2559 + attribute \src "libresoc.v:44786.5-44786.29" + switch \initial + attribute \src "libresoc.v:44786.9-44786.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + switch \dp_INT_rb_ldst0_7 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src2_i$61[63:0]$2559 \int_src2__data_o + case + assign $1\fus_src2_i$61[63:0]$2559 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_src2_i$61 $0\fus_src2_i$61[63:0]$2558 + end + attribute \src "libresoc.v:44795.3-44803.6" + process $proc$libresoc.v:44795$2560 + assign { } { } + assign { } { } + assign $0\dp_INT_rc_shiftrot0_0$next[0:0]$2561 $1\dp_INT_rc_shiftrot0_0$next[0:0]$2562 + attribute \src "libresoc.v:44796.5-44796.29" + switch \initial + attribute \src "libresoc.v:44796.9-44796.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_INT_rc_shiftrot0_0$next[0:0]$2562 1'0 + case + assign $1\dp_INT_rc_shiftrot0_0$next[0:0]$2562 \rp_INT_rc_shiftrot0_0 + end + sync always + update \dp_INT_rc_shiftrot0_0$next $0\dp_INT_rc_shiftrot0_0$next[0:0]$2561 + end + attribute \src "libresoc.v:44804.3-44813.6" + process $proc$libresoc.v:44804$2563 + assign { } { } + assign { } { } + assign $0\fus_src3_i[63:0] $1\fus_src3_i[63:0] + attribute \src "libresoc.v:44805.5-44805.29" + switch \initial + attribute \src "libresoc.v:44805.9-44805.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + switch \dp_INT_rc_shiftrot0_0 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src3_i[63:0] \int_src3__data_o + case + assign $1\fus_src3_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_src3_i $0\fus_src3_i[63:0] + end + attribute \src "libresoc.v:44814.3-44822.6" + process $proc$libresoc.v:44814$2564 + assign { } { } + assign { } { } + assign $0\dp_INT_rc_ldst0_1$next[0:0]$2565 $1\dp_INT_rc_ldst0_1$next[0:0]$2566 + attribute \src "libresoc.v:44815.5-44815.29" + switch \initial + attribute \src "libresoc.v:44815.9-44815.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_INT_rc_ldst0_1$next[0:0]$2566 1'0 + case + assign $1\dp_INT_rc_ldst0_1$next[0:0]$2566 \rp_INT_rc_ldst0_1 + end + sync always + update \dp_INT_rc_ldst0_1$next $0\dp_INT_rc_ldst0_1$next[0:0]$2565 + end + attribute \src "libresoc.v:44823.3-44832.6" + process $proc$libresoc.v:44823$2567 + assign { } { } + assign { } { } + assign $0\fus_src3_i$62[63:0]$2568 $1\fus_src3_i$62[63:0]$2569 + attribute \src "libresoc.v:44824.5-44824.29" + switch \initial + attribute \src "libresoc.v:44824.9-44824.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + switch \dp_INT_rc_ldst0_1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src3_i$62[63:0]$2569 \int_src3__data_o + case + assign $1\fus_src3_i$62[63:0]$2569 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_src3_i$62 $0\fus_src3_i$62[63:0]$2568 + end + attribute \src "libresoc.v:44833.3-44859.6" + process $proc$libresoc.v:44833$2570 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\counter$next[1:0]$2571 $4\counter$next[1:0]$2575 + attribute \src "libresoc.v:44834.5-44834.29" + switch \initial + attribute \src "libresoc.v:44834.9-44834.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:186" + switch \$200 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\counter$next[1:0]$2572 \$202 [1:0] + case + assign $1\counter$next[1:0]$2572 \counter + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\counter$next[1:0]$2573 $3\counter$next[1:0]$2574 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign { } { } + assign $3\counter$next[1:0]$2574 2'10 + case + assign $3\counter$next[1:0]$2574 $1\counter$next[1:0]$2572 + end + case + assign $2\counter$next[1:0]$2573 $1\counter$next[1:0]$2572 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\counter$next[1:0]$2575 2'00 + case + assign $4\counter$next[1:0]$2575 $2\counter$next[1:0]$2573 + end + sync always + update \counter$next $0\counter$next[1:0]$2571 + end + attribute \src "libresoc.v:44860.3-44868.6" + process $proc$libresoc.v:44860$2576 + assign { } { } + assign { } { } + assign $0\dp_XER_xer_so_alu0_0$next[0:0]$2577 $1\dp_XER_xer_so_alu0_0$next[0:0]$2578 + attribute \src "libresoc.v:44861.5-44861.29" + switch \initial + attribute \src "libresoc.v:44861.9-44861.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_XER_xer_so_alu0_0$next[0:0]$2578 1'0 + case + assign $1\dp_XER_xer_so_alu0_0$next[0:0]$2578 \rp_XER_xer_so_alu0_0 + end + sync always + update \dp_XER_xer_so_alu0_0$next $0\dp_XER_xer_so_alu0_0$next[0:0]$2577 + end + attribute \src "libresoc.v:44869.3-44878.6" + process $proc$libresoc.v:44869$2579 + assign { } { } + assign { } { } + assign $0\fus_src3_i$63[0:0]$2580 $1\fus_src3_i$63[0:0]$2581 + attribute \src "libresoc.v:44870.5-44870.29" + switch \initial + attribute \src "libresoc.v:44870.9-44870.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + switch \dp_XER_xer_so_alu0_0 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src3_i$63[0:0]$2581 \xer_src1__data_o [0] + case + assign $1\fus_src3_i$63[0:0]$2581 1'0 + end + sync always + update \fus_src3_i$63 $0\fus_src3_i$63[0:0]$2580 + end + attribute \src "libresoc.v:44879.3-44887.6" + process $proc$libresoc.v:44879$2582 + assign { } { } + assign { } { } + assign $0\dp_XER_xer_so_logical0_1$next[0:0]$2583 $1\dp_XER_xer_so_logical0_1$next[0:0]$2584 + attribute \src "libresoc.v:44880.5-44880.29" + switch \initial + attribute \src "libresoc.v:44880.9-44880.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_XER_xer_so_logical0_1$next[0:0]$2584 1'0 + case + assign $1\dp_XER_xer_so_logical0_1$next[0:0]$2584 \rp_XER_xer_so_logical0_1 + end + sync always + update \dp_XER_xer_so_logical0_1$next $0\dp_XER_xer_so_logical0_1$next[0:0]$2583 + end + attribute \src "libresoc.v:44888.3-44978.6" + process $proc$libresoc.v:44888$2585 + assign { } { } + assign { } { } + assign { } { } + assign $0\corebusy_o[0:0] $2\corebusy_o[0:0] + attribute \src "libresoc.v:44889.5-44889.29" + switch \initial + attribute \src "libresoc.v:44889.9-44889.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:186" + switch \$205 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\corebusy_o[0:0] 1'1 + case + assign $1\corebusy_o[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\corebusy_o[0:0] $3\corebusy_o[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $3\corebusy_o[0:0] $1\corebusy_o[0:0] + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign { } { } + assign $3\corebusy_o[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $3\corebusy_o[0:0] $13\corebusy_o[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + switch \fu_enable [0] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\corebusy_o[0:0] \fus_cu_busy_o + case + assign $4\corebusy_o[0:0] $1\corebusy_o[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + switch \fu_enable [1] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\corebusy_o[0:0] \fus_cu_busy_o$5 + case + assign $5\corebusy_o[0:0] $4\corebusy_o[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + switch \fu_enable [2] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\corebusy_o[0:0] \fus_cu_busy_o$8 + case + assign $6\corebusy_o[0:0] $5\corebusy_o[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + switch \fu_enable [3] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\corebusy_o[0:0] \fus_cu_busy_o$11 + case + assign $7\corebusy_o[0:0] $6\corebusy_o[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + switch \fu_enable [4] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $8\corebusy_o[0:0] \fus_cu_busy_o$14 + case + assign $8\corebusy_o[0:0] $7\corebusy_o[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + switch \fu_enable [5] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $9\corebusy_o[0:0] \fus_cu_busy_o$17 + case + assign $9\corebusy_o[0:0] $8\corebusy_o[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + switch \fu_enable [6] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $10\corebusy_o[0:0] \fus_cu_busy_o$20 + case + assign $10\corebusy_o[0:0] $9\corebusy_o[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + switch \fu_enable [7] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $11\corebusy_o[0:0] \fus_cu_busy_o$23 + case + assign $11\corebusy_o[0:0] $10\corebusy_o[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + switch \fu_enable [8] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $12\corebusy_o[0:0] \fus_cu_busy_o$26 + case + assign $12\corebusy_o[0:0] $11\corebusy_o[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + switch \fu_enable [9] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $13\corebusy_o[0:0] \fus_cu_busy_o$29 + case + assign $13\corebusy_o[0:0] $12\corebusy_o[0:0] + end + end + case + assign $2\corebusy_o[0:0] $1\corebusy_o[0:0] + end + sync always + update \corebusy_o $0\corebusy_o[0:0] + end + attribute \src "libresoc.v:44979.3-44988.6" + process $proc$libresoc.v:44979$2586 + assign { } { } + assign { } { } + assign $0\fus_src3_i$64[0:0]$2587 $1\fus_src3_i$64[0:0]$2588 + attribute \src "libresoc.v:44980.5-44980.29" + switch \initial + attribute \src "libresoc.v:44980.9-44980.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + switch \dp_XER_xer_so_logical0_1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src3_i$64[0:0]$2588 \xer_src1__data_o [0] + case + assign $1\fus_src3_i$64[0:0]$2588 1'0 + end + sync always + update \fus_src3_i$64 $0\fus_src3_i$64[0:0]$2587 + end + attribute \src "libresoc.v:44989.3-44997.6" + process $proc$libresoc.v:44989$2589 + assign { } { } + assign { } { } + assign $0\dp_XER_xer_so_spr0_2$next[0:0]$2590 $1\dp_XER_xer_so_spr0_2$next[0:0]$2591 + attribute \src "libresoc.v:44990.5-44990.29" + switch \initial + attribute \src "libresoc.v:44990.9-44990.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_XER_xer_so_spr0_2$next[0:0]$2591 1'0 + case + assign $1\dp_XER_xer_so_spr0_2$next[0:0]$2591 \rp_XER_xer_so_spr0_2 + end + sync always + update \dp_XER_xer_so_spr0_2$next $0\dp_XER_xer_so_spr0_2$next[0:0]$2590 + end + attribute \src "libresoc.v:44998.3-45007.6" + process $proc$libresoc.v:44998$2592 + assign { } { } + assign { } { } + assign $0\fus_src4_i[0:0] $1\fus_src4_i[0:0] + attribute \src "libresoc.v:44999.5-44999.29" + switch \initial + attribute \src "libresoc.v:44999.9-44999.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + switch \dp_XER_xer_so_spr0_2 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src4_i[0:0] \xer_src1__data_o [0] + case + assign $1\fus_src4_i[0:0] 1'0 + end + sync always + update \fus_src4_i $0\fus_src4_i[0:0] + end + attribute \src "libresoc.v:45008.3-45016.6" + process $proc$libresoc.v:45008$2593 + assign { } { } + assign { } { } + assign $0\dp_XER_xer_so_div0_3$next[0:0]$2594 $1\dp_XER_xer_so_div0_3$next[0:0]$2595 + attribute \src "libresoc.v:45009.5-45009.29" + switch \initial + attribute \src "libresoc.v:45009.9-45009.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_XER_xer_so_div0_3$next[0:0]$2595 1'0 + case + assign $1\dp_XER_xer_so_div0_3$next[0:0]$2595 \rp_XER_xer_so_div0_3 + end + sync always + update \dp_XER_xer_so_div0_3$next $0\dp_XER_xer_so_div0_3$next[0:0]$2594 + end + attribute \src "libresoc.v:45017.3-45037.6" + process $proc$libresoc.v:45017$2596 + assign { } { } + assign { } { } + assign { } { } + assign $0\core_terminate_o$next[0:0]$2597 $3\core_terminate_o$next[0:0]$2600 + attribute \src "libresoc.v:45018.5-45018.29" + switch \initial + attribute \src "libresoc.v:45018.9-45018.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\core_terminate_o$next[0:0]$2598 $2\core_terminate_o$next[0:0]$2599 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign { } { } + assign $2\core_terminate_o$next[0:0]$2599 1'1 + case + assign $2\core_terminate_o$next[0:0]$2599 \core_terminate_o + end + case + assign $1\core_terminate_o$next[0:0]$2598 \core_terminate_o + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\core_terminate_o$next[0:0]$2600 1'0 + case + assign $3\core_terminate_o$next[0:0]$2600 $1\core_terminate_o$next[0:0]$2598 + end + sync always + update \core_terminate_o$next $0\core_terminate_o$next[0:0]$2597 + end + attribute \src "libresoc.v:45038.3-45047.6" + process $proc$libresoc.v:45038$2601 + assign { } { } + assign { } { } + assign $0\fus_src3_i$65[0:0]$2602 $1\fus_src3_i$65[0:0]$2603 + attribute \src "libresoc.v:45039.5-45039.29" + switch \initial + attribute \src "libresoc.v:45039.9-45039.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + switch \dp_XER_xer_so_div0_3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src3_i$65[0:0]$2603 \xer_src1__data_o [0] + case + assign $1\fus_src3_i$65[0:0]$2603 1'0 + end + sync always + update \fus_src3_i$65 $0\fus_src3_i$65[0:0]$2602 + end + attribute \src "libresoc.v:45048.3-45056.6" + process $proc$libresoc.v:45048$2604 + assign { } { } + assign { } { } + assign $0\dp_XER_xer_so_mul0_4$next[0:0]$2605 $1\dp_XER_xer_so_mul0_4$next[0:0]$2606 + attribute \src "libresoc.v:45049.5-45049.29" + switch \initial + attribute \src "libresoc.v:45049.9-45049.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_XER_xer_so_mul0_4$next[0:0]$2606 1'0 + case + assign $1\dp_XER_xer_so_mul0_4$next[0:0]$2606 \rp_XER_xer_so_mul0_4 + end + sync always + update \dp_XER_xer_so_mul0_4$next $0\dp_XER_xer_so_mul0_4$next[0:0]$2605 + end + attribute \src "libresoc.v:45057.3-45066.6" + process $proc$libresoc.v:45057$2607 + assign { } { } + assign { } { } + assign $0\fus_src3_i$66[0:0]$2608 $1\fus_src3_i$66[0:0]$2609 + attribute \src "libresoc.v:45058.5-45058.29" + switch \initial + attribute \src "libresoc.v:45058.9-45058.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + switch \dp_XER_xer_so_mul0_4 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src3_i$66[0:0]$2609 \xer_src1__data_o [0] + case + assign $1\fus_src3_i$66[0:0]$2609 1'0 + end + sync always + update \fus_src3_i$66 $0\fus_src3_i$66[0:0]$2608 + end + attribute \src "libresoc.v:45067.3-45075.6" + process $proc$libresoc.v:45067$2610 + assign { } { } + assign { } { } + assign $0\dp_XER_xer_so_shiftrot0_5$next[0:0]$2611 $1\dp_XER_xer_so_shiftrot0_5$next[0:0]$2612 + attribute \src "libresoc.v:45068.5-45068.29" + switch \initial + attribute \src "libresoc.v:45068.9-45068.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_XER_xer_so_shiftrot0_5$next[0:0]$2612 1'0 + case + assign $1\dp_XER_xer_so_shiftrot0_5$next[0:0]$2612 \rp_XER_xer_so_shiftrot0_5 + end + sync always + update \dp_XER_xer_so_shiftrot0_5$next $0\dp_XER_xer_so_shiftrot0_5$next[0:0]$2611 + end + attribute \src "libresoc.v:45076.3-45104.6" + process $proc$libresoc.v:45076$2613 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_alu0__insn_type[6:0] $1\fus_oper_i_alu_alu0__insn_type[6:0] + attribute \src "libresoc.v:45077.5-45077.29" + switch \initial + attribute \src "libresoc.v:45077.9-45077.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_alu0__insn_type[6:0] $2\fus_oper_i_alu_alu0__insn_type[6:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_alu0__insn_type[6:0] 7'0000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_alu0__insn_type[6:0] 7'0000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_alu0__insn_type[6:0] $3\fus_oper_i_alu_alu0__insn_type[6:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + switch \fu_enable [0] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_alu0__insn_type[6:0] \dec_ALU_ALU_ALU__insn_type + case + assign $3\fus_oper_i_alu_alu0__insn_type[6:0] 7'0000000 + end + end + case + assign $1\fus_oper_i_alu_alu0__insn_type[6:0] 7'0000000 + end + sync always + update \fus_oper_i_alu_alu0__insn_type $0\fus_oper_i_alu_alu0__insn_type[6:0] + end + attribute \src "libresoc.v:45105.3-45114.6" + process $proc$libresoc.v:45105$2614 + assign { } { } + assign { } { } + assign $0\fus_src4_i$67[0:0]$2615 $1\fus_src4_i$67[0:0]$2616 + attribute \src "libresoc.v:45106.5-45106.29" + switch \initial + attribute \src "libresoc.v:45106.9-45106.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + switch \dp_XER_xer_so_shiftrot0_5 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src4_i$67[0:0]$2616 \xer_src1__data_o [0] + case + assign $1\fus_src4_i$67[0:0]$2616 1'0 + end + sync always + update \fus_src4_i$67 $0\fus_src4_i$67[0:0]$2615 + end + attribute \src "libresoc.v:45115.3-45123.6" + process $proc$libresoc.v:45115$2617 + assign { } { } + assign { } { } + assign $0\dp_XER_xer_ca_alu0_0$next[0:0]$2618 $1\dp_XER_xer_ca_alu0_0$next[0:0]$2619 + attribute \src "libresoc.v:45116.5-45116.29" + switch \initial + attribute \src "libresoc.v:45116.9-45116.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_XER_xer_ca_alu0_0$next[0:0]$2619 1'0 + case + assign $1\dp_XER_xer_ca_alu0_0$next[0:0]$2619 \rp_XER_xer_ca_alu0_0 + end + sync always + update \dp_XER_xer_ca_alu0_0$next $0\dp_XER_xer_ca_alu0_0$next[0:0]$2618 + end + attribute \src "libresoc.v:45124.3-45133.6" + process $proc$libresoc.v:45124$2620 + assign { } { } + assign { } { } + assign $0\fus_src4_i$68[1:0]$2621 $1\fus_src4_i$68[1:0]$2622 + attribute \src "libresoc.v:45125.5-45125.29" + switch \initial + attribute \src "libresoc.v:45125.9-45125.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + switch \dp_XER_xer_ca_alu0_0 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src4_i$68[1:0]$2622 \xer_src2__data_o + case + assign $1\fus_src4_i$68[1:0]$2622 2'00 + end + sync always + update \fus_src4_i$68 $0\fus_src4_i$68[1:0]$2621 + end + attribute \src "libresoc.v:45134.3-45162.6" + process $proc$libresoc.v:45134$2623 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_alu0__fn_unit[11:0] $1\fus_oper_i_alu_alu0__fn_unit[11:0] + attribute \src "libresoc.v:45135.5-45135.29" + switch \initial + attribute \src "libresoc.v:45135.9-45135.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_alu0__fn_unit[11:0] $2\fus_oper_i_alu_alu0__fn_unit[11:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_alu0__fn_unit[11:0] 12'000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_alu0__fn_unit[11:0] 12'000000000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_alu0__fn_unit[11:0] $3\fus_oper_i_alu_alu0__fn_unit[11:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + switch \fu_enable [0] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_alu0__fn_unit[11:0] \dec_ALU_ALU_ALU__fn_unit + case + assign $3\fus_oper_i_alu_alu0__fn_unit[11:0] 12'000000000000 + end + end + case + assign $1\fus_oper_i_alu_alu0__fn_unit[11:0] 12'000000000000 + end + sync always + update \fus_oper_i_alu_alu0__fn_unit $0\fus_oper_i_alu_alu0__fn_unit[11:0] + end + attribute \src "libresoc.v:45163.3-45171.6" + process $proc$libresoc.v:45163$2624 + assign { } { } + assign { } { } + assign $0\dp_XER_xer_ca_spr0_1$next[0:0]$2625 $1\dp_XER_xer_ca_spr0_1$next[0:0]$2626 + attribute \src "libresoc.v:45164.5-45164.29" + switch \initial + attribute \src "libresoc.v:45164.9-45164.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_XER_xer_ca_spr0_1$next[0:0]$2626 1'0 + case + assign $1\dp_XER_xer_ca_spr0_1$next[0:0]$2626 \rp_XER_xer_ca_spr0_1 + end + sync always + update \dp_XER_xer_ca_spr0_1$next $0\dp_XER_xer_ca_spr0_1$next[0:0]$2625 + end + attribute \src "libresoc.v:45172.3-45181.6" + process $proc$libresoc.v:45172$2627 + assign { } { } + assign { } { } + assign $0\fus_src6_i[1:0] $1\fus_src6_i[1:0] + attribute \src "libresoc.v:45173.5-45173.29" + switch \initial + attribute \src "libresoc.v:45173.9-45173.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + switch \dp_XER_xer_ca_spr0_1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src6_i[1:0] \xer_src2__data_o + case + assign $1\fus_src6_i[1:0] 2'00 + end + sync always + update \fus_src6_i $0\fus_src6_i[1:0] + end + attribute \src "libresoc.v:45182.3-45190.6" + process $proc$libresoc.v:45182$2628 + assign { } { } + assign { } { } + assign $0\dp_XER_xer_ca_shiftrot0_2$next[0:0]$2629 $1\dp_XER_xer_ca_shiftrot0_2$next[0:0]$2630 + attribute \src "libresoc.v:45183.5-45183.29" + switch \initial + attribute \src "libresoc.v:45183.9-45183.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_XER_xer_ca_shiftrot0_2$next[0:0]$2630 1'0 + case + assign $1\dp_XER_xer_ca_shiftrot0_2$next[0:0]$2630 \rp_XER_xer_ca_shiftrot0_2 + end + sync always + update \dp_XER_xer_ca_shiftrot0_2$next $0\dp_XER_xer_ca_shiftrot0_2$next[0:0]$2629 + end + attribute \src "libresoc.v:45191.3-45200.6" + process $proc$libresoc.v:45191$2631 + assign { } { } + assign { } { } + assign $0\fus_src5_i[1:0] $1\fus_src5_i[1:0] + attribute \src "libresoc.v:45192.5-45192.29" + switch \initial + attribute \src "libresoc.v:45192.9-45192.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + switch \dp_XER_xer_ca_shiftrot0_2 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src5_i[1:0] \xer_src2__data_o + case + assign $1\fus_src5_i[1:0] 2'00 + end + sync always + update \fus_src5_i $0\fus_src5_i[1:0] + end + attribute \src "libresoc.v:45201.3-45230.6" + process $proc$libresoc.v:45201$2632 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_alu0__imm_data__data[63:0] $1\fus_oper_i_alu_alu0__imm_data__data[63:0] + assign $0\fus_oper_i_alu_alu0__imm_data__ok[0:0] $1\fus_oper_i_alu_alu0__imm_data__ok[0:0] + attribute \src "libresoc.v:45202.5-45202.29" + switch \initial + attribute \src "libresoc.v:45202.9-45202.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $1\fus_oper_i_alu_alu0__imm_data__data[63:0] $2\fus_oper_i_alu_alu0__imm_data__data[63:0] + assign $1\fus_oper_i_alu_alu0__imm_data__ok[0:0] $2\fus_oper_i_alu_alu0__imm_data__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_alu0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\fus_oper_i_alu_alu0__imm_data__ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_alu0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\fus_oper_i_alu_alu0__imm_data__ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign $2\fus_oper_i_alu_alu0__imm_data__data[63:0] $3\fus_oper_i_alu_alu0__imm_data__data[63:0] + assign $2\fus_oper_i_alu_alu0__imm_data__ok[0:0] $3\fus_oper_i_alu_alu0__imm_data__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + switch \fu_enable [0] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $3\fus_oper_i_alu_alu0__imm_data__ok[0:0] $3\fus_oper_i_alu_alu0__imm_data__data[63:0] } { \dec_ALU_ALU_ALU__imm_data__ok \dec_ALU_ALU_ALU__imm_data__data } + case + assign $3\fus_oper_i_alu_alu0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\fus_oper_i_alu_alu0__imm_data__ok[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_alu0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fus_oper_i_alu_alu0__imm_data__ok[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_alu0__imm_data__data $0\fus_oper_i_alu_alu0__imm_data__data[63:0] + update \fus_oper_i_alu_alu0__imm_data__ok $0\fus_oper_i_alu_alu0__imm_data__ok[0:0] + end + attribute \src "libresoc.v:45231.3-45239.6" + process $proc$libresoc.v:45231$2633 + assign { } { } + assign { } { } + assign $0\dp_XER_xer_ov_spr0_0$next[0:0]$2634 $1\dp_XER_xer_ov_spr0_0$next[0:0]$2635 + attribute \src "libresoc.v:45232.5-45232.29" + switch \initial + attribute \src "libresoc.v:45232.9-45232.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_XER_xer_ov_spr0_0$next[0:0]$2635 1'0 + case + assign $1\dp_XER_xer_ov_spr0_0$next[0:0]$2635 \rp_XER_xer_ov_spr0_0 + end + sync always + update \dp_XER_xer_ov_spr0_0$next $0\dp_XER_xer_ov_spr0_0$next[0:0]$2634 + end + attribute \src "libresoc.v:45240.3-45249.6" + process $proc$libresoc.v:45240$2636 + assign { } { } + assign { } { } + assign $0\fus_src5_i$69[1:0]$2637 $1\fus_src5_i$69[1:0]$2638 + attribute \src "libresoc.v:45241.5-45241.29" + switch \initial + attribute \src "libresoc.v:45241.9-45241.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + switch \dp_XER_xer_ov_spr0_0 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src5_i$69[1:0]$2638 \xer_src3__data_o + case + assign $1\fus_src5_i$69[1:0]$2638 2'00 + end + sync always + update \fus_src5_i$69 $0\fus_src5_i$69[1:0]$2637 + end + attribute \src "libresoc.v:45250.3-45258.6" + process $proc$libresoc.v:45250$2639 + assign { } { } + assign { } { } + assign $0\dp_CR_full_cr_cr0_0$next[0:0]$2640 $1\dp_CR_full_cr_cr0_0$next[0:0]$2641 + attribute \src "libresoc.v:45251.5-45251.29" + switch \initial + attribute \src "libresoc.v:45251.9-45251.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_CR_full_cr_cr0_0$next[0:0]$2641 1'0 + case + assign $1\dp_CR_full_cr_cr0_0$next[0:0]$2641 \rp_CR_full_cr_cr0_0 + end + sync always + update \dp_CR_full_cr_cr0_0$next $0\dp_CR_full_cr_cr0_0$next[0:0]$2640 + end + attribute \src "libresoc.v:45259.3-45268.6" + process $proc$libresoc.v:45259$2642 + assign { } { } + assign { } { } + assign $0\fus_src3_i$70[31:0]$2643 $1\fus_src3_i$70[31:0]$2644 + attribute \src "libresoc.v:45260.5-45260.29" + switch \initial + attribute \src "libresoc.v:45260.9-45260.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + switch \dp_CR_full_cr_cr0_0 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src3_i$70[31:0]$2644 \cr_full_rd__data_o + case + assign $1\fus_src3_i$70[31:0]$2644 0 + end + sync always + update \fus_src3_i$70 $0\fus_src3_i$70[31:0]$2643 + end + attribute \src "libresoc.v:45269.3-45298.6" + process $proc$libresoc.v:45269$2645 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_alu0__rc__ok[0:0] $1\fus_oper_i_alu_alu0__rc__ok[0:0] + assign $0\fus_oper_i_alu_alu0__rc__rc[0:0] $1\fus_oper_i_alu_alu0__rc__rc[0:0] + attribute \src "libresoc.v:45270.5-45270.29" + switch \initial + attribute \src "libresoc.v:45270.9-45270.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $1\fus_oper_i_alu_alu0__rc__ok[0:0] $2\fus_oper_i_alu_alu0__rc__ok[0:0] + assign $1\fus_oper_i_alu_alu0__rc__rc[0:0] $2\fus_oper_i_alu_alu0__rc__rc[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_alu0__rc__ok[0:0] 1'0 + assign $2\fus_oper_i_alu_alu0__rc__rc[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_alu0__rc__ok[0:0] 1'0 + assign $2\fus_oper_i_alu_alu0__rc__rc[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign $2\fus_oper_i_alu_alu0__rc__ok[0:0] $3\fus_oper_i_alu_alu0__rc__ok[0:0] + assign $2\fus_oper_i_alu_alu0__rc__rc[0:0] $3\fus_oper_i_alu_alu0__rc__rc[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + switch \fu_enable [0] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $3\fus_oper_i_alu_alu0__rc__ok[0:0] $3\fus_oper_i_alu_alu0__rc__rc[0:0] } { \dec_ALU_ALU_ALU__rc__ok \dec_ALU_ALU_ALU__rc__rc } + case + assign $3\fus_oper_i_alu_alu0__rc__ok[0:0] 1'0 + assign $3\fus_oper_i_alu_alu0__rc__rc[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_alu0__rc__ok[0:0] 1'0 + assign $1\fus_oper_i_alu_alu0__rc__rc[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_alu0__rc__ok $0\fus_oper_i_alu_alu0__rc__ok[0:0] + update \fus_oper_i_alu_alu0__rc__rc $0\fus_oper_i_alu_alu0__rc__rc[0:0] + end + attribute \src "libresoc.v:45299.3-45307.6" + process $proc$libresoc.v:45299$2646 + assign { } { } + assign { } { } + assign $0\dp_CR_cr_a_cr0_0$next[0:0]$2647 $1\dp_CR_cr_a_cr0_0$next[0:0]$2648 + attribute \src "libresoc.v:45300.5-45300.29" + switch \initial + attribute \src "libresoc.v:45300.9-45300.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_CR_cr_a_cr0_0$next[0:0]$2648 1'0 + case + assign $1\dp_CR_cr_a_cr0_0$next[0:0]$2648 \rp_CR_cr_a_cr0_0 + end + sync always + update \dp_CR_cr_a_cr0_0$next $0\dp_CR_cr_a_cr0_0$next[0:0]$2647 + end + attribute \src "libresoc.v:45308.3-45317.6" + process $proc$libresoc.v:45308$2649 + assign { } { } + assign { } { } + assign $0\fus_src4_i$71[3:0]$2650 $1\fus_src4_i$71[3:0]$2651 + attribute \src "libresoc.v:45309.5-45309.29" + switch \initial + attribute \src "libresoc.v:45309.9-45309.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + switch \dp_CR_cr_a_cr0_0 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src4_i$71[3:0]$2651 \cr_src1__data_o + case + assign $1\fus_src4_i$71[3:0]$2651 4'0000 + end + sync always + update \fus_src4_i$71 $0\fus_src4_i$71[3:0]$2650 + end + attribute \src "libresoc.v:45318.3-45326.6" + process $proc$libresoc.v:45318$2652 + assign { } { } + assign { } { } + assign $0\dp_CR_cr_a_branch0_1$next[0:0]$2653 $1\dp_CR_cr_a_branch0_1$next[0:0]$2654 + attribute \src "libresoc.v:45319.5-45319.29" + switch \initial + attribute \src "libresoc.v:45319.9-45319.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_CR_cr_a_branch0_1$next[0:0]$2654 1'0 + case + assign $1\dp_CR_cr_a_branch0_1$next[0:0]$2654 \rp_CR_cr_a_branch0_1 + end + sync always + update \dp_CR_cr_a_branch0_1$next $0\dp_CR_cr_a_branch0_1$next[0:0]$2653 + end + attribute \src "libresoc.v:45327.3-45336.6" + process $proc$libresoc.v:45327$2655 + assign { } { } + assign { } { } + assign $0\fus_src3_i$74[3:0]$2656 $1\fus_src3_i$74[3:0]$2657 + attribute \src "libresoc.v:45328.5-45328.29" + switch \initial + attribute \src "libresoc.v:45328.9-45328.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + switch \dp_CR_cr_a_branch0_1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src3_i$74[3:0]$2657 \cr_src1__data_o + case + assign $1\fus_src3_i$74[3:0]$2657 4'0000 + end + sync always + update \fus_src3_i$74 $0\fus_src3_i$74[3:0]$2656 + end + attribute \src "libresoc.v:45337.3-45345.6" + process $proc$libresoc.v:45337$2658 + assign { } { } + assign { } { } + assign $0\dp_CR_cr_b_cr0_0$next[0:0]$2659 $1\dp_CR_cr_b_cr0_0$next[0:0]$2660 + attribute \src "libresoc.v:45338.5-45338.29" + switch \initial + attribute \src "libresoc.v:45338.9-45338.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_CR_cr_b_cr0_0$next[0:0]$2660 1'0 + case + assign $1\dp_CR_cr_b_cr0_0$next[0:0]$2660 \rp_CR_cr_b_cr0_0 + end + sync always + update \dp_CR_cr_b_cr0_0$next $0\dp_CR_cr_b_cr0_0$next[0:0]$2659 + end + attribute \src "libresoc.v:45346.3-45355.6" + process $proc$libresoc.v:45346$2661 + assign { } { } + assign { } { } + assign $0\fus_src5_i$75[3:0]$2662 $1\fus_src5_i$75[3:0]$2663 + attribute \src "libresoc.v:45347.5-45347.29" + switch \initial + attribute \src "libresoc.v:45347.9-45347.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + switch \dp_CR_cr_b_cr0_0 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src5_i$75[3:0]$2663 \cr_src2__data_o + case + assign $1\fus_src5_i$75[3:0]$2663 4'0000 + end + sync always + update \fus_src5_i$75 $0\fus_src5_i$75[3:0]$2662 + end + attribute \src "libresoc.v:45356.3-45385.6" + process $proc$libresoc.v:45356$2664 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_alu0__oe__oe[0:0] $1\fus_oper_i_alu_alu0__oe__oe[0:0] + assign $0\fus_oper_i_alu_alu0__oe__ok[0:0] $1\fus_oper_i_alu_alu0__oe__ok[0:0] + attribute \src "libresoc.v:45357.5-45357.29" + switch \initial + attribute \src "libresoc.v:45357.9-45357.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $1\fus_oper_i_alu_alu0__oe__oe[0:0] $2\fus_oper_i_alu_alu0__oe__oe[0:0] + assign $1\fus_oper_i_alu_alu0__oe__ok[0:0] $2\fus_oper_i_alu_alu0__oe__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_alu0__oe__oe[0:0] 1'0 + assign $2\fus_oper_i_alu_alu0__oe__ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_alu0__oe__oe[0:0] 1'0 + assign $2\fus_oper_i_alu_alu0__oe__ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign $2\fus_oper_i_alu_alu0__oe__oe[0:0] $3\fus_oper_i_alu_alu0__oe__oe[0:0] + assign $2\fus_oper_i_alu_alu0__oe__ok[0:0] $3\fus_oper_i_alu_alu0__oe__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + switch \fu_enable [0] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $3\fus_oper_i_alu_alu0__oe__ok[0:0] $3\fus_oper_i_alu_alu0__oe__oe[0:0] } { \dec_ALU_ALU_ALU__oe__ok \dec_ALU_ALU_ALU__oe__oe } + case + assign $3\fus_oper_i_alu_alu0__oe__oe[0:0] 1'0 + assign $3\fus_oper_i_alu_alu0__oe__ok[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_alu0__oe__oe[0:0] 1'0 + assign $1\fus_oper_i_alu_alu0__oe__ok[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_alu0__oe__oe $0\fus_oper_i_alu_alu0__oe__oe[0:0] + update \fus_oper_i_alu_alu0__oe__ok $0\fus_oper_i_alu_alu0__oe__ok[0:0] + end + attribute \src "libresoc.v:45386.3-45394.6" + process $proc$libresoc.v:45386$2665 + assign { } { } + assign { } { } + assign $0\dp_CR_cr_c_cr0_0$next[0:0]$2666 $1\dp_CR_cr_c_cr0_0$next[0:0]$2667 + attribute \src "libresoc.v:45387.5-45387.29" + switch \initial + attribute \src "libresoc.v:45387.9-45387.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_CR_cr_c_cr0_0$next[0:0]$2667 1'0 + case + assign $1\dp_CR_cr_c_cr0_0$next[0:0]$2667 \rp_CR_cr_c_cr0_0 + end + sync always + update \dp_CR_cr_c_cr0_0$next $0\dp_CR_cr_c_cr0_0$next[0:0]$2666 + end + attribute \src "libresoc.v:45395.3-45404.6" + process $proc$libresoc.v:45395$2668 + assign { } { } + assign { } { } + assign $0\fus_src6_i$76[3:0]$2669 $1\fus_src6_i$76[3:0]$2670 + attribute \src "libresoc.v:45396.5-45396.29" + switch \initial + attribute \src "libresoc.v:45396.9-45396.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + switch \dp_CR_cr_c_cr0_0 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src6_i$76[3:0]$2670 \cr_src3__data_o + case + assign $1\fus_src6_i$76[3:0]$2670 4'0000 + end + sync always + update \fus_src6_i$76 $0\fus_src6_i$76[3:0]$2669 + end + attribute \src "libresoc.v:45405.3-45413.6" + process $proc$libresoc.v:45405$2671 + assign { } { } + assign { } { } + assign $0\dp_FAST_fast1_branch0_0$next[0:0]$2672 $1\dp_FAST_fast1_branch0_0$next[0:0]$2673 + attribute \src "libresoc.v:45406.5-45406.29" + switch \initial + attribute \src "libresoc.v:45406.9-45406.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_FAST_fast1_branch0_0$next[0:0]$2673 1'0 + case + assign $1\dp_FAST_fast1_branch0_0$next[0:0]$2673 \rp_FAST_fast1_branch0_0 + end + sync always + update \dp_FAST_fast1_branch0_0$next $0\dp_FAST_fast1_branch0_0$next[0:0]$2672 + end + attribute \src "libresoc.v:45414.3-45423.6" + process $proc$libresoc.v:45414$2674 + assign { } { } + assign { } { } + assign $0\fus_src1_i$77[63:0]$2675 $1\fus_src1_i$77[63:0]$2676 + attribute \src "libresoc.v:45415.5-45415.29" + switch \initial + attribute \src "libresoc.v:45415.9-45415.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + switch \dp_FAST_fast1_branch0_0 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src1_i$77[63:0]$2676 \fast_src1__data_o + case + assign $1\fus_src1_i$77[63:0]$2676 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_src1_i$77 $0\fus_src1_i$77[63:0]$2675 + end + attribute \src "libresoc.v:45424.3-45432.6" + process $proc$libresoc.v:45424$2677 + assign { } { } + assign { } { } + assign $0\dp_FAST_fast1_trap0_1$next[0:0]$2678 $1\dp_FAST_fast1_trap0_1$next[0:0]$2679 + attribute \src "libresoc.v:45425.5-45425.29" + switch \initial + attribute \src "libresoc.v:45425.9-45425.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_FAST_fast1_trap0_1$next[0:0]$2679 1'0 + case + assign $1\dp_FAST_fast1_trap0_1$next[0:0]$2679 \rp_FAST_fast1_trap0_1 + end + sync always + update \dp_FAST_fast1_trap0_1$next $0\dp_FAST_fast1_trap0_1$next[0:0]$2678 + end + attribute \src "libresoc.v:45433.3-45442.6" + process $proc$libresoc.v:45433$2680 + assign { } { } + assign { } { } + assign $0\fus_src3_i$78[63:0]$2681 $1\fus_src3_i$78[63:0]$2682 + attribute \src "libresoc.v:45434.5-45434.29" + switch \initial + attribute \src "libresoc.v:45434.9-45434.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + switch \dp_FAST_fast1_trap0_1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src3_i$78[63:0]$2682 \fast_src1__data_o + case + assign $1\fus_src3_i$78[63:0]$2682 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_src3_i$78 $0\fus_src3_i$78[63:0]$2681 + end + attribute \src "libresoc.v:45443.3-45471.6" + process $proc$libresoc.v:45443$2683 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_alu0__invert_in[0:0] $1\fus_oper_i_alu_alu0__invert_in[0:0] + attribute \src "libresoc.v:45444.5-45444.29" + switch \initial + attribute \src "libresoc.v:45444.9-45444.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_alu0__invert_in[0:0] $2\fus_oper_i_alu_alu0__invert_in[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_alu0__invert_in[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_alu0__invert_in[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_alu0__invert_in[0:0] $3\fus_oper_i_alu_alu0__invert_in[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + switch \fu_enable [0] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_alu0__invert_in[0:0] \dec_ALU_ALU_ALU__invert_in + case + assign $3\fus_oper_i_alu_alu0__invert_in[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_alu0__invert_in[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_alu0__invert_in $0\fus_oper_i_alu_alu0__invert_in[0:0] + end + attribute \src "libresoc.v:45472.3-45480.6" + process $proc$libresoc.v:45472$2684 + assign { } { } + assign { } { } + assign $0\dp_FAST_fast1_spr0_2$next[0:0]$2685 $1\dp_FAST_fast1_spr0_2$next[0:0]$2686 + attribute \src "libresoc.v:45473.5-45473.29" + switch \initial + attribute \src "libresoc.v:45473.9-45473.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_FAST_fast1_spr0_2$next[0:0]$2686 1'0 + case + assign $1\dp_FAST_fast1_spr0_2$next[0:0]$2686 \rp_FAST_fast1_spr0_2 + end + sync always + update \dp_FAST_fast1_spr0_2$next $0\dp_FAST_fast1_spr0_2$next[0:0]$2685 + end + attribute \src "libresoc.v:45481.3-45490.6" + process $proc$libresoc.v:45481$2687 + assign { } { } + assign { } { } + assign $0\fus_src3_i$79[63:0]$2688 $1\fus_src3_i$79[63:0]$2689 + attribute \src "libresoc.v:45482.5-45482.29" + switch \initial + attribute \src "libresoc.v:45482.9-45482.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + switch \dp_FAST_fast1_spr0_2 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src3_i$79[63:0]$2689 \fast_src1__data_o + case + assign $1\fus_src3_i$79[63:0]$2689 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_src3_i$79 $0\fus_src3_i$79[63:0]$2688 + end + attribute \src "libresoc.v:45491.3-45499.6" + process $proc$libresoc.v:45491$2690 + assign { } { } + assign { } { } + assign $0\dp_FAST_fast2_branch0_0$next[0:0]$2691 $1\dp_FAST_fast2_branch0_0$next[0:0]$2692 + attribute \src "libresoc.v:45492.5-45492.29" + switch \initial + attribute \src "libresoc.v:45492.9-45492.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_FAST_fast2_branch0_0$next[0:0]$2692 1'0 + case + assign $1\dp_FAST_fast2_branch0_0$next[0:0]$2692 \rp_FAST_fast2_branch0_0 + end + sync always + update \dp_FAST_fast2_branch0_0$next $0\dp_FAST_fast2_branch0_0$next[0:0]$2691 + end + attribute \src "libresoc.v:45500.3-45528.6" + process $proc$libresoc.v:45500$2693 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_alu0__zero_a[0:0] $1\fus_oper_i_alu_alu0__zero_a[0:0] + attribute \src "libresoc.v:45501.5-45501.29" + switch \initial + attribute \src "libresoc.v:45501.9-45501.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_alu0__zero_a[0:0] $2\fus_oper_i_alu_alu0__zero_a[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_alu0__zero_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_alu0__zero_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_alu0__zero_a[0:0] $3\fus_oper_i_alu_alu0__zero_a[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + switch \fu_enable [0] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_alu0__zero_a[0:0] \dec_ALU_ALU_ALU__zero_a + case + assign $3\fus_oper_i_alu_alu0__zero_a[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_alu0__zero_a[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_alu0__zero_a $0\fus_oper_i_alu_alu0__zero_a[0:0] + end + attribute \src "libresoc.v:45529.3-45538.6" + process $proc$libresoc.v:45529$2694 + assign { } { } + assign { } { } + assign $0\fus_src2_i$80[63:0]$2695 $1\fus_src2_i$80[63:0]$2696 + attribute \src "libresoc.v:45530.5-45530.29" + switch \initial + attribute \src "libresoc.v:45530.9-45530.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + switch \dp_FAST_fast2_branch0_0 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src2_i$80[63:0]$2696 \fast_src2__data_o + case + assign $1\fus_src2_i$80[63:0]$2696 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_src2_i$80 $0\fus_src2_i$80[63:0]$2695 + end + attribute \src "libresoc.v:45539.3-45547.6" + process $proc$libresoc.v:45539$2697 + assign { } { } + assign { } { } + assign $0\dp_FAST_fast2_trap0_1$next[0:0]$2698 $1\dp_FAST_fast2_trap0_1$next[0:0]$2699 + attribute \src "libresoc.v:45540.5-45540.29" + switch \initial + attribute \src "libresoc.v:45540.9-45540.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_FAST_fast2_trap0_1$next[0:0]$2699 1'0 + case + assign $1\dp_FAST_fast2_trap0_1$next[0:0]$2699 \rp_FAST_fast2_trap0_1 + end + sync always + update \dp_FAST_fast2_trap0_1$next $0\dp_FAST_fast2_trap0_1$next[0:0]$2698 + end + attribute \src "libresoc.v:45548.3-45557.6" + process $proc$libresoc.v:45548$2700 + assign { } { } + assign { } { } + assign $0\fus_src4_i$81[63:0]$2701 $1\fus_src4_i$81[63:0]$2702 + attribute \src "libresoc.v:45549.5-45549.29" + switch \initial + attribute \src "libresoc.v:45549.9-45549.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + switch \dp_FAST_fast2_trap0_1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src4_i$81[63:0]$2702 \fast_src2__data_o + case + assign $1\fus_src4_i$81[63:0]$2702 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_src4_i$81 $0\fus_src4_i$81[63:0]$2701 + end + attribute \src "libresoc.v:45558.3-45586.6" + process $proc$libresoc.v:45558$2703 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_alu0__invert_out[0:0] $1\fus_oper_i_alu_alu0__invert_out[0:0] + attribute \src "libresoc.v:45559.5-45559.29" + switch \initial + attribute \src "libresoc.v:45559.9-45559.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_alu0__invert_out[0:0] $2\fus_oper_i_alu_alu0__invert_out[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_alu0__invert_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_alu0__invert_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_alu0__invert_out[0:0] $3\fus_oper_i_alu_alu0__invert_out[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + switch \fu_enable [0] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_alu0__invert_out[0:0] \dec_ALU_ALU_ALU__invert_out + case + assign $3\fus_oper_i_alu_alu0__invert_out[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_alu0__invert_out[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_alu0__invert_out $0\fus_oper_i_alu_alu0__invert_out[0:0] + end + attribute \src "libresoc.v:45587.3-45595.6" + process $proc$libresoc.v:45587$2704 + assign { } { } + assign { } { } + assign $0\dp_SPR_spr1_spr0_0$next[0:0]$2705 $1\dp_SPR_spr1_spr0_0$next[0:0]$2706 + attribute \src "libresoc.v:45588.5-45588.29" + switch \initial + attribute \src "libresoc.v:45588.9-45588.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_SPR_spr1_spr0_0$next[0:0]$2706 1'0 + case + assign $1\dp_SPR_spr1_spr0_0$next[0:0]$2706 \rp_SPR_spr1_spr0_0 + end + sync always + update \dp_SPR_spr1_spr0_0$next $0\dp_SPR_spr1_spr0_0$next[0:0]$2705 + end + attribute \src "libresoc.v:45596.3-45605.6" + process $proc$libresoc.v:45596$2707 + assign { } { } + assign { } { } + assign $0\fus_src2_i$82[63:0]$2708 $1\fus_src2_i$82[63:0]$2709 + attribute \src "libresoc.v:45597.5-45597.29" + switch \initial + attribute \src "libresoc.v:45597.9-45597.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + switch \dp_SPR_spr1_spr0_0 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src2_i$82[63:0]$2709 \spr_spr1__data_o + case + assign $1\fus_src2_i$82[63:0]$2709 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_src2_i$82 $0\fus_src2_i$82[63:0]$2708 + end + attribute \src "libresoc.v:45606.3-45634.6" + process $proc$libresoc.v:45606$2710 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_alu0__write_cr0[0:0] $1\fus_oper_i_alu_alu0__write_cr0[0:0] + attribute \src "libresoc.v:45607.5-45607.29" + switch \initial + attribute \src "libresoc.v:45607.9-45607.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_alu0__write_cr0[0:0] $2\fus_oper_i_alu_alu0__write_cr0[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_alu0__write_cr0[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_alu0__write_cr0[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_alu0__write_cr0[0:0] $3\fus_oper_i_alu_alu0__write_cr0[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + switch \fu_enable [0] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_alu0__write_cr0[0:0] \dec_ALU_ALU_ALU__write_cr0 + case + assign $3\fus_oper_i_alu_alu0__write_cr0[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_alu0__write_cr0[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_alu0__write_cr0 $0\fus_oper_i_alu_alu0__write_cr0[0:0] + end + attribute \src "libresoc.v:45635.3-45643.6" + process $proc$libresoc.v:45635$2711 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$next[0:0]$2712 $1\wr_pick_dly$next[0:0]$2713 + attribute \src "libresoc.v:45636.5-45636.29" + switch \initial + attribute \src "libresoc.v:45636.9-45636.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$next[0:0]$2713 1'0 + case + assign $1\wr_pick_dly$next[0:0]$2713 \wr_pick + end + sync always + update \wr_pick_dly$next $0\wr_pick_dly$next[0:0]$2712 + end + attribute \src "libresoc.v:45644.3-45652.6" + process $proc$libresoc.v:45644$2714 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$967$next[0:0]$2715 $1\wr_pick_dly$967$next[0:0]$2716 + attribute \src "libresoc.v:45645.5-45645.29" + switch \initial + attribute \src "libresoc.v:45645.9-45645.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$967$next[0:0]$2716 1'0 + case + assign $1\wr_pick_dly$967$next[0:0]$2716 \wr_pick$964 + end + sync always + update \wr_pick_dly$967$next $0\wr_pick_dly$967$next[0:0]$2715 + end + attribute \src "libresoc.v:45653.3-45681.6" + process $proc$libresoc.v:45653$2717 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_alu0__input_carry[1:0] $1\fus_oper_i_alu_alu0__input_carry[1:0] + attribute \src "libresoc.v:45654.5-45654.29" + switch \initial + attribute \src "libresoc.v:45654.9-45654.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_alu0__input_carry[1:0] $2\fus_oper_i_alu_alu0__input_carry[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_alu0__input_carry[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_alu0__input_carry[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_alu0__input_carry[1:0] $3\fus_oper_i_alu_alu0__input_carry[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + switch \fu_enable [0] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_alu0__input_carry[1:0] \dec_ALU_ALU_ALU__input_carry + case + assign $3\fus_oper_i_alu_alu0__input_carry[1:0] 2'00 + end + end + case + assign $1\fus_oper_i_alu_alu0__input_carry[1:0] 2'00 + end + sync always + update \fus_oper_i_alu_alu0__input_carry $0\fus_oper_i_alu_alu0__input_carry[1:0] + end + attribute \src "libresoc.v:45682.3-45690.6" + process $proc$libresoc.v:45682$2718 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$986$next[0:0]$2719 $1\wr_pick_dly$986$next[0:0]$2720 + attribute \src "libresoc.v:45683.5-45683.29" + switch \initial + attribute \src "libresoc.v:45683.9-45683.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$986$next[0:0]$2720 1'0 + case + assign $1\wr_pick_dly$986$next[0:0]$2720 \wr_pick$983 + end + sync always + update \wr_pick_dly$986$next $0\wr_pick_dly$986$next[0:0]$2719 + end + attribute \src "libresoc.v:45691.3-45719.6" + process $proc$libresoc.v:45691$2721 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_alu0__output_carry[0:0] $1\fus_oper_i_alu_alu0__output_carry[0:0] + attribute \src "libresoc.v:45692.5-45692.29" + switch \initial + attribute \src "libresoc.v:45692.9-45692.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_alu0__output_carry[0:0] $2\fus_oper_i_alu_alu0__output_carry[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_alu0__output_carry[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_alu0__output_carry[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_alu0__output_carry[0:0] $3\fus_oper_i_alu_alu0__output_carry[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + switch \fu_enable [0] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_alu0__output_carry[0:0] \dec_ALU_ALU_ALU__output_carry + case + assign $3\fus_oper_i_alu_alu0__output_carry[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_alu0__output_carry[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_alu0__output_carry $0\fus_oper_i_alu_alu0__output_carry[0:0] + end + attribute \src "libresoc.v:45720.3-45728.6" + process $proc$libresoc.v:45720$2722 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1007$next[0:0]$2723 $1\wr_pick_dly$1007$next[0:0]$2724 + attribute \src "libresoc.v:45721.5-45721.29" + switch \initial + attribute \src "libresoc.v:45721.9-45721.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1007$next[0:0]$2724 1'0 + case + assign $1\wr_pick_dly$1007$next[0:0]$2724 \wr_pick$1004 + end + sync always + update \wr_pick_dly$1007$next $0\wr_pick_dly$1007$next[0:0]$2723 + end + attribute \src "libresoc.v:45729.3-45737.6" + process $proc$libresoc.v:45729$2725 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1025$next[0:0]$2726 $1\wr_pick_dly$1025$next[0:0]$2727 + attribute \src "libresoc.v:45730.5-45730.29" + switch \initial + attribute \src "libresoc.v:45730.9-45730.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1025$next[0:0]$2727 1'0 + case + assign $1\wr_pick_dly$1025$next[0:0]$2727 \wr_pick$1022 + end + sync always + update \wr_pick_dly$1025$next $0\wr_pick_dly$1025$next[0:0]$2726 + end + attribute \src "libresoc.v:45738.3-45766.6" + process $proc$libresoc.v:45738$2728 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_alu0__is_32bit[0:0] $1\fus_oper_i_alu_alu0__is_32bit[0:0] + attribute \src "libresoc.v:45739.5-45739.29" + switch \initial + attribute \src "libresoc.v:45739.9-45739.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_alu0__is_32bit[0:0] $2\fus_oper_i_alu_alu0__is_32bit[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_alu0__is_32bit[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_alu0__is_32bit[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_alu0__is_32bit[0:0] $3\fus_oper_i_alu_alu0__is_32bit[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + switch \fu_enable [0] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_alu0__is_32bit[0:0] \dec_ALU_ALU_ALU__is_32bit + case + assign $3\fus_oper_i_alu_alu0__is_32bit[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_alu0__is_32bit[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_alu0__is_32bit $0\fus_oper_i_alu_alu0__is_32bit[0:0] + end + attribute \src "libresoc.v:45767.3-45775.6" + process $proc$libresoc.v:45767$2729 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1047$next[0:0]$2730 $1\wr_pick_dly$1047$next[0:0]$2731 + attribute \src "libresoc.v:45768.5-45768.29" + switch \initial + attribute \src "libresoc.v:45768.9-45768.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1047$next[0:0]$2731 1'0 + case + assign $1\wr_pick_dly$1047$next[0:0]$2731 \wr_pick$1044 + end + sync always + update \wr_pick_dly$1047$next $0\wr_pick_dly$1047$next[0:0]$2730 + end + attribute \src "libresoc.v:45776.3-45804.6" + process $proc$libresoc.v:45776$2732 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_alu0__is_signed[0:0] $1\fus_oper_i_alu_alu0__is_signed[0:0] + attribute \src "libresoc.v:45777.5-45777.29" + switch \initial + attribute \src "libresoc.v:45777.9-45777.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_alu0__is_signed[0:0] $2\fus_oper_i_alu_alu0__is_signed[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_alu0__is_signed[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_alu0__is_signed[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_alu0__is_signed[0:0] $3\fus_oper_i_alu_alu0__is_signed[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + switch \fu_enable [0] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_alu0__is_signed[0:0] \dec_ALU_ALU_ALU__is_signed + case + assign $3\fus_oper_i_alu_alu0__is_signed[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_alu0__is_signed[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_alu0__is_signed $0\fus_oper_i_alu_alu0__is_signed[0:0] + end + attribute \src "libresoc.v:45805.3-45813.6" + process $proc$libresoc.v:45805$2733 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1067$next[0:0]$2734 $1\wr_pick_dly$1067$next[0:0]$2735 + attribute \src "libresoc.v:45806.5-45806.29" + switch \initial + attribute \src "libresoc.v:45806.9-45806.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1067$next[0:0]$2735 1'0 + case + assign $1\wr_pick_dly$1067$next[0:0]$2735 \wr_pick$1064 + end + sync always + update \wr_pick_dly$1067$next $0\wr_pick_dly$1067$next[0:0]$2734 + end + attribute \src "libresoc.v:45814.3-45842.6" + process $proc$libresoc.v:45814$2736 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_alu0__data_len[3:0] $1\fus_oper_i_alu_alu0__data_len[3:0] + attribute \src "libresoc.v:45815.5-45815.29" + switch \initial + attribute \src "libresoc.v:45815.9-45815.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_alu0__data_len[3:0] $2\fus_oper_i_alu_alu0__data_len[3:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_alu0__data_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_alu0__data_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_alu0__data_len[3:0] $3\fus_oper_i_alu_alu0__data_len[3:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + switch \fu_enable [0] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_alu0__data_len[3:0] \dec_ALU_ALU_ALU__data_len + case + assign $3\fus_oper_i_alu_alu0__data_len[3:0] 4'0000 + end + end + case + assign $1\fus_oper_i_alu_alu0__data_len[3:0] 4'0000 + end + sync always + update \fus_oper_i_alu_alu0__data_len $0\fus_oper_i_alu_alu0__data_len[3:0] + end + attribute \src "libresoc.v:45843.3-45851.6" + process $proc$libresoc.v:45843$2737 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1087$next[0:0]$2738 $1\wr_pick_dly$1087$next[0:0]$2739 + attribute \src "libresoc.v:45844.5-45844.29" + switch \initial + attribute \src "libresoc.v:45844.9-45844.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1087$next[0:0]$2739 1'0 + case + assign $1\wr_pick_dly$1087$next[0:0]$2739 \wr_pick$1084 + end + sync always + update \wr_pick_dly$1087$next $0\wr_pick_dly$1087$next[0:0]$2738 + end + attribute \src "libresoc.v:45852.3-45860.6" + process $proc$libresoc.v:45852$2740 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1106$next[0:0]$2741 $1\wr_pick_dly$1106$next[0:0]$2742 + attribute \src "libresoc.v:45853.5-45853.29" + switch \initial + attribute \src "libresoc.v:45853.9-45853.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1106$next[0:0]$2742 1'0 + case + assign $1\wr_pick_dly$1106$next[0:0]$2742 \wr_pick$1103 + end + sync always + update \wr_pick_dly$1106$next $0\wr_pick_dly$1106$next[0:0]$2741 + end + attribute \src "libresoc.v:45861.3-45889.6" + process $proc$libresoc.v:45861$2743 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_alu0__insn[31:0] $1\fus_oper_i_alu_alu0__insn[31:0] + attribute \src "libresoc.v:45862.5-45862.29" + switch \initial + attribute \src "libresoc.v:45862.9-45862.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_alu0__insn[31:0] $2\fus_oper_i_alu_alu0__insn[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_alu0__insn[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_alu0__insn[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_alu0__insn[31:0] $3\fus_oper_i_alu_alu0__insn[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + switch \fu_enable [0] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_alu0__insn[31:0] \dec_ALU_ALU_ALU__insn + case + assign $3\fus_oper_i_alu_alu0__insn[31:0] 0 + end + end + case + assign $1\fus_oper_i_alu_alu0__insn[31:0] 0 + end + sync always + update \fus_oper_i_alu_alu0__insn $0\fus_oper_i_alu_alu0__insn[31:0] + end + attribute \src "libresoc.v:45890.3-45898.6" + process $proc$libresoc.v:45890$2744 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1124$next[0:0]$2745 $1\wr_pick_dly$1124$next[0:0]$2746 + attribute \src "libresoc.v:45891.5-45891.29" + switch \initial + attribute \src "libresoc.v:45891.9-45891.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1124$next[0:0]$2746 1'0 + case + assign $1\wr_pick_dly$1124$next[0:0]$2746 \wr_pick$1121 + end + sync always + update \wr_pick_dly$1124$next $0\wr_pick_dly$1124$next[0:0]$2745 + end + attribute \src "libresoc.v:45899.3-45927.6" + process $proc$libresoc.v:45899$2747 + assign { } { } + assign { } { } + assign $0\fus_cu_issue_i[0:0] $1\fus_cu_issue_i[0:0] + attribute \src "libresoc.v:45900.5-45900.29" + switch \initial + attribute \src "libresoc.v:45900.9-45900.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_cu_issue_i[0:0] $2\fus_cu_issue_i[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_cu_issue_i[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_cu_issue_i[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_cu_issue_i[0:0] $3\fus_cu_issue_i[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + switch \fu_enable [0] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_cu_issue_i[0:0] \issue_i + case + assign $3\fus_cu_issue_i[0:0] 1'0 + end + end + case + assign $1\fus_cu_issue_i[0:0] 1'0 + end + sync always + update \fus_cu_issue_i $0\fus_cu_issue_i[0:0] + end + attribute \src "libresoc.v:45928.3-45936.6" + process $proc$libresoc.v:45928$2748 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1197$next[0:0]$2749 $1\wr_pick_dly$1197$next[0:0]$2750 + attribute \src "libresoc.v:45929.5-45929.29" + switch \initial + attribute \src "libresoc.v:45929.9-45929.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1197$next[0:0]$2750 1'0 + case + assign $1\wr_pick_dly$1197$next[0:0]$2750 \wr_pick$1194 + end + sync always + update \wr_pick_dly$1197$next $0\wr_pick_dly$1197$next[0:0]$2749 + end + attribute \src "libresoc.v:45937.3-45965.6" + process $proc$libresoc.v:45937$2751 + assign { } { } + assign { } { } + assign $0\fus_cu_rdmaskn_i[3:0] $1\fus_cu_rdmaskn_i[3:0] + attribute \src "libresoc.v:45938.5-45938.29" + switch \initial + attribute \src "libresoc.v:45938.9-45938.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_cu_rdmaskn_i[3:0] $2\fus_cu_rdmaskn_i[3:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_cu_rdmaskn_i[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_cu_rdmaskn_i[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_cu_rdmaskn_i[3:0] $3\fus_cu_rdmaskn_i[3:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + switch \fu_enable [0] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_cu_rdmaskn_i[3:0] \$207 + case + assign $3\fus_cu_rdmaskn_i[3:0] 4'0000 + end + end + case + assign $1\fus_cu_rdmaskn_i[3:0] 4'0000 + end + sync always + update \fus_cu_rdmaskn_i $0\fus_cu_rdmaskn_i[3:0] + end + attribute \src "libresoc.v:45966.3-45974.6" + process $proc$libresoc.v:45966$2752 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1225$next[0:0]$2753 $1\wr_pick_dly$1225$next[0:0]$2754 + attribute \src "libresoc.v:45967.5-45967.29" + switch \initial + attribute \src "libresoc.v:45967.9-45967.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1225$next[0:0]$2754 1'0 + case + assign $1\wr_pick_dly$1225$next[0:0]$2754 \wr_pick$1222 + end + sync always + update \wr_pick_dly$1225$next $0\wr_pick_dly$1225$next[0:0]$2753 + end + attribute \src "libresoc.v:45975.3-45983.6" + process $proc$libresoc.v:45975$2755 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1245$next[0:0]$2756 $1\wr_pick_dly$1245$next[0:0]$2757 + attribute \src "libresoc.v:45976.5-45976.29" + switch \initial + attribute \src "libresoc.v:45976.9-45976.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1245$next[0:0]$2757 1'0 + case + assign $1\wr_pick_dly$1245$next[0:0]$2757 \wr_pick$1242 + end + sync always + update \wr_pick_dly$1245$next $0\wr_pick_dly$1245$next[0:0]$2756 + end + attribute \src "libresoc.v:45984.3-46012.6" + process $proc$libresoc.v:45984$2758 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_cr0__insn_type[6:0] $1\fus_oper_i_alu_cr0__insn_type[6:0] + attribute \src "libresoc.v:45985.5-45985.29" + switch \initial + attribute \src "libresoc.v:45985.9-45985.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_cr0__insn_type[6:0] $2\fus_oper_i_alu_cr0__insn_type[6:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_cr0__insn_type[6:0] 7'0000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_cr0__insn_type[6:0] 7'0000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_cr0__insn_type[6:0] $3\fus_oper_i_alu_cr0__insn_type[6:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + switch \fu_enable [1] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_cr0__insn_type[6:0] \dec_CR_CR_CR__insn_type + case + assign $3\fus_oper_i_alu_cr0__insn_type[6:0] 7'0000000 + end + end + case + assign $1\fus_oper_i_alu_cr0__insn_type[6:0] 7'0000000 + end + sync always + update \fus_oper_i_alu_cr0__insn_type $0\fus_oper_i_alu_cr0__insn_type[6:0] + end + attribute \src "libresoc.v:46013.3-46021.6" + process $proc$libresoc.v:46013$2759 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1265$next[0:0]$2760 $1\wr_pick_dly$1265$next[0:0]$2761 + attribute \src "libresoc.v:46014.5-46014.29" + switch \initial + attribute \src "libresoc.v:46014.9-46014.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1265$next[0:0]$2761 1'0 + case + assign $1\wr_pick_dly$1265$next[0:0]$2761 \wr_pick$1262 + end + sync always + update \wr_pick_dly$1265$next $0\wr_pick_dly$1265$next[0:0]$2760 + end + attribute \src "libresoc.v:46022.3-46050.6" + process $proc$libresoc.v:46022$2762 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_cr0__fn_unit[11:0] $1\fus_oper_i_alu_cr0__fn_unit[11:0] + attribute \src "libresoc.v:46023.5-46023.29" + switch \initial + attribute \src "libresoc.v:46023.9-46023.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_cr0__fn_unit[11:0] $2\fus_oper_i_alu_cr0__fn_unit[11:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_cr0__fn_unit[11:0] 12'000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_cr0__fn_unit[11:0] 12'000000000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_cr0__fn_unit[11:0] $3\fus_oper_i_alu_cr0__fn_unit[11:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + switch \fu_enable [1] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_cr0__fn_unit[11:0] \dec_CR_CR_CR__fn_unit + case + assign $3\fus_oper_i_alu_cr0__fn_unit[11:0] 12'000000000000 + end + end + case + assign $1\fus_oper_i_alu_cr0__fn_unit[11:0] 12'000000000000 + end + sync always + update \fus_oper_i_alu_cr0__fn_unit $0\fus_oper_i_alu_cr0__fn_unit[11:0] + end + attribute \src "libresoc.v:46051.3-46059.6" + process $proc$libresoc.v:46051$2763 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1285$next[0:0]$2764 $1\wr_pick_dly$1285$next[0:0]$2765 + attribute \src "libresoc.v:46052.5-46052.29" + switch \initial + attribute \src "libresoc.v:46052.9-46052.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1285$next[0:0]$2765 1'0 + case + assign $1\wr_pick_dly$1285$next[0:0]$2765 \wr_pick$1282 + end + sync always + update \wr_pick_dly$1285$next $0\wr_pick_dly$1285$next[0:0]$2764 + end + attribute \src "libresoc.v:46060.3-46068.6" + process $proc$libresoc.v:46060$2766 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1305$next[0:0]$2767 $1\wr_pick_dly$1305$next[0:0]$2768 + attribute \src "libresoc.v:46061.5-46061.29" + switch \initial + attribute \src "libresoc.v:46061.9-46061.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1305$next[0:0]$2768 1'0 + case + assign $1\wr_pick_dly$1305$next[0:0]$2768 \wr_pick$1302 + end + sync always + update \wr_pick_dly$1305$next $0\wr_pick_dly$1305$next[0:0]$2767 + end + attribute \src "libresoc.v:46069.3-46097.6" + process $proc$libresoc.v:46069$2769 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_cr0__insn[31:0] $1\fus_oper_i_alu_cr0__insn[31:0] + attribute \src "libresoc.v:46070.5-46070.29" + switch \initial + attribute \src "libresoc.v:46070.9-46070.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_cr0__insn[31:0] $2\fus_oper_i_alu_cr0__insn[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_cr0__insn[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_cr0__insn[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_cr0__insn[31:0] $3\fus_oper_i_alu_cr0__insn[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + switch \fu_enable [1] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_cr0__insn[31:0] \dec_CR_CR_CR__insn + case + assign $3\fus_oper_i_alu_cr0__insn[31:0] 0 + end + end + case + assign $1\fus_oper_i_alu_cr0__insn[31:0] 0 + end + sync always + update \fus_oper_i_alu_cr0__insn $0\fus_oper_i_alu_cr0__insn[31:0] + end + attribute \src "libresoc.v:46098.3-46106.6" + process $proc$libresoc.v:46098$2770 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1325$next[0:0]$2771 $1\wr_pick_dly$1325$next[0:0]$2772 + attribute \src "libresoc.v:46099.5-46099.29" + switch \initial + attribute \src "libresoc.v:46099.9-46099.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1325$next[0:0]$2772 1'0 + case + assign $1\wr_pick_dly$1325$next[0:0]$2772 \wr_pick$1322 + end + sync always + update \wr_pick_dly$1325$next $0\wr_pick_dly$1325$next[0:0]$2771 + end + attribute \src "libresoc.v:46107.3-46135.6" + process $proc$libresoc.v:46107$2773 + assign { } { } + assign { } { } + assign $0\fus_cu_issue_i$4[0:0]$2774 $1\fus_cu_issue_i$4[0:0]$2775 + attribute \src "libresoc.v:46108.5-46108.29" + switch \initial + attribute \src "libresoc.v:46108.9-46108.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_cu_issue_i$4[0:0]$2775 $2\fus_cu_issue_i$4[0:0]$2776 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_cu_issue_i$4[0:0]$2776 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_cu_issue_i$4[0:0]$2776 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_cu_issue_i$4[0:0]$2776 $3\fus_cu_issue_i$4[0:0]$2777 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + switch \fu_enable [1] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_cu_issue_i$4[0:0]$2777 \issue_i + case + assign $3\fus_cu_issue_i$4[0:0]$2777 1'0 + end + end + case + assign $1\fus_cu_issue_i$4[0:0]$2775 1'0 + end + sync always + update \fus_cu_issue_i$4 $0\fus_cu_issue_i$4[0:0]$2774 + end + attribute \src "libresoc.v:46136.3-46144.6" + process $proc$libresoc.v:46136$2778 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1372$next[0:0]$2779 $1\wr_pick_dly$1372$next[0:0]$2780 + attribute \src "libresoc.v:46137.5-46137.29" + switch \initial + attribute \src "libresoc.v:46137.9-46137.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1372$next[0:0]$2780 1'0 + case + assign $1\wr_pick_dly$1372$next[0:0]$2780 \wr_pick$1369 + end + sync always + update \wr_pick_dly$1372$next $0\wr_pick_dly$1372$next[0:0]$2779 + end + attribute \src "libresoc.v:46145.3-46153.6" + process $proc$libresoc.v:46145$2781 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1388$next[0:0]$2782 $1\wr_pick_dly$1388$next[0:0]$2783 + attribute \src "libresoc.v:46146.5-46146.29" + switch \initial + attribute \src "libresoc.v:46146.9-46146.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1388$next[0:0]$2783 1'0 + case + assign $1\wr_pick_dly$1388$next[0:0]$2783 \wr_pick$1385 + end + sync always + update \wr_pick_dly$1388$next $0\wr_pick_dly$1388$next[0:0]$2782 + end + attribute \src "libresoc.v:46154.3-46182.6" + process $proc$libresoc.v:46154$2784 + assign { } { } + assign { } { } + assign $0\fus_cu_rdmaskn_i$6[5:0]$2785 $1\fus_cu_rdmaskn_i$6[5:0]$2786 + attribute \src "libresoc.v:46155.5-46155.29" + switch \initial + attribute \src "libresoc.v:46155.9-46155.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_cu_rdmaskn_i$6[5:0]$2786 $2\fus_cu_rdmaskn_i$6[5:0]$2787 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_cu_rdmaskn_i$6[5:0]$2787 6'000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_cu_rdmaskn_i$6[5:0]$2787 6'000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_cu_rdmaskn_i$6[5:0]$2787 $3\fus_cu_rdmaskn_i$6[5:0]$2788 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + switch \fu_enable [1] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_cu_rdmaskn_i$6[5:0]$2788 \$229 + case + assign $3\fus_cu_rdmaskn_i$6[5:0]$2788 6'000000 + end + end + case + assign $1\fus_cu_rdmaskn_i$6[5:0]$2786 6'000000 + end + sync always + update \fus_cu_rdmaskn_i$6 $0\fus_cu_rdmaskn_i$6[5:0]$2785 + end + attribute \src "libresoc.v:46183.3-46191.6" + process $proc$libresoc.v:46183$2789 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1404$next[0:0]$2790 $1\wr_pick_dly$1404$next[0:0]$2791 + attribute \src "libresoc.v:46184.5-46184.29" + switch \initial + attribute \src "libresoc.v:46184.9-46184.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1404$next[0:0]$2791 1'0 + case + assign $1\wr_pick_dly$1404$next[0:0]$2791 \wr_pick$1401 + end + sync always + update \wr_pick_dly$1404$next $0\wr_pick_dly$1404$next[0:0]$2790 + end + attribute \src "libresoc.v:46192.3-46220.6" + process $proc$libresoc.v:46192$2792 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_branch0__cia[63:0] $1\fus_oper_i_alu_branch0__cia[63:0] + attribute \src "libresoc.v:46193.5-46193.29" + switch \initial + attribute \src "libresoc.v:46193.9-46193.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_branch0__cia[63:0] $2\fus_oper_i_alu_branch0__cia[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_branch0__cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_branch0__cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_branch0__cia[63:0] $3\fus_oper_i_alu_branch0__cia[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + switch \fu_enable [2] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_branch0__cia[63:0] \dec_BRANCH_BRANCH_BRANCH__cia + case + assign $3\fus_oper_i_alu_branch0__cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + end + case + assign $1\fus_oper_i_alu_branch0__cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_oper_i_alu_branch0__cia $0\fus_oper_i_alu_branch0__cia[63:0] + end + attribute \src "libresoc.v:46221.3-46229.6" + process $proc$libresoc.v:46221$2793 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1438$next[0:0]$2794 $1\wr_pick_dly$1438$next[0:0]$2795 + attribute \src "libresoc.v:46222.5-46222.29" + switch \initial + attribute \src "libresoc.v:46222.9-46222.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1438$next[0:0]$2795 1'0 + case + assign $1\wr_pick_dly$1438$next[0:0]$2795 \wr_pick$1435 + end + sync always + update \wr_pick_dly$1438$next $0\wr_pick_dly$1438$next[0:0]$2794 + end + attribute \src "libresoc.v:46230.3-46238.6" + process $proc$libresoc.v:46230$2796 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1454$next[0:0]$2797 $1\wr_pick_dly$1454$next[0:0]$2798 + attribute \src "libresoc.v:46231.5-46231.29" + switch \initial + attribute \src "libresoc.v:46231.9-46231.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1454$next[0:0]$2798 1'0 + case + assign $1\wr_pick_dly$1454$next[0:0]$2798 \wr_pick$1451 + end + sync always + update \wr_pick_dly$1454$next $0\wr_pick_dly$1454$next[0:0]$2797 + end + attribute \src "libresoc.v:46239.3-46267.6" + process $proc$libresoc.v:46239$2799 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_branch0__insn_type[6:0] $1\fus_oper_i_alu_branch0__insn_type[6:0] + attribute \src "libresoc.v:46240.5-46240.29" + switch \initial + attribute \src "libresoc.v:46240.9-46240.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_branch0__insn_type[6:0] $2\fus_oper_i_alu_branch0__insn_type[6:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_branch0__insn_type[6:0] 7'0000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_branch0__insn_type[6:0] 7'0000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_branch0__insn_type[6:0] $3\fus_oper_i_alu_branch0__insn_type[6:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + switch \fu_enable [2] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_branch0__insn_type[6:0] \dec_BRANCH_BRANCH_BRANCH__insn_type + case + assign $3\fus_oper_i_alu_branch0__insn_type[6:0] 7'0000000 + end + end + case + assign $1\fus_oper_i_alu_branch0__insn_type[6:0] 7'0000000 + end + sync always + update \fus_oper_i_alu_branch0__insn_type $0\fus_oper_i_alu_branch0__insn_type[6:0] + end + attribute \src "libresoc.v:46268.3-46276.6" + process $proc$libresoc.v:46268$2800 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1470$next[0:0]$2801 $1\wr_pick_dly$1470$next[0:0]$2802 + attribute \src "libresoc.v:46269.5-46269.29" + switch \initial + attribute \src "libresoc.v:46269.9-46269.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1470$next[0:0]$2802 1'0 + case + assign $1\wr_pick_dly$1470$next[0:0]$2802 \wr_pick$1467 + end + sync always + update \wr_pick_dly$1470$next $0\wr_pick_dly$1470$next[0:0]$2801 + end + attribute \src "libresoc.v:46277.3-46305.6" + process $proc$libresoc.v:46277$2803 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_branch0__fn_unit[11:0] $1\fus_oper_i_alu_branch0__fn_unit[11:0] + attribute \src "libresoc.v:46278.5-46278.29" + switch \initial + attribute \src "libresoc.v:46278.9-46278.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_branch0__fn_unit[11:0] $2\fus_oper_i_alu_branch0__fn_unit[11:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_branch0__fn_unit[11:0] 12'000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_branch0__fn_unit[11:0] 12'000000000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_branch0__fn_unit[11:0] $3\fus_oper_i_alu_branch0__fn_unit[11:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + switch \fu_enable [2] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_branch0__fn_unit[11:0] \dec_BRANCH_BRANCH_BRANCH__fn_unit + case + assign $3\fus_oper_i_alu_branch0__fn_unit[11:0] 12'000000000000 + end + end + case + assign $1\fus_oper_i_alu_branch0__fn_unit[11:0] 12'000000000000 + end + sync always + update \fus_oper_i_alu_branch0__fn_unit $0\fus_oper_i_alu_branch0__fn_unit[11:0] + end + attribute \src "libresoc.v:46306.3-46314.6" + process $proc$libresoc.v:46306$2804 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1486$next[0:0]$2805 $1\wr_pick_dly$1486$next[0:0]$2806 + attribute \src "libresoc.v:46307.5-46307.29" + switch \initial + attribute \src "libresoc.v:46307.9-46307.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1486$next[0:0]$2806 1'0 + case + assign $1\wr_pick_dly$1486$next[0:0]$2806 \wr_pick$1483 + end + sync always + update \wr_pick_dly$1486$next $0\wr_pick_dly$1486$next[0:0]$2805 + end + attribute \src "libresoc.v:46315.3-46343.6" + process $proc$libresoc.v:46315$2807 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_branch0__insn[31:0] $1\fus_oper_i_alu_branch0__insn[31:0] + attribute \src "libresoc.v:46316.5-46316.29" + switch \initial + attribute \src "libresoc.v:46316.9-46316.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_branch0__insn[31:0] $2\fus_oper_i_alu_branch0__insn[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_branch0__insn[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_branch0__insn[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_branch0__insn[31:0] $3\fus_oper_i_alu_branch0__insn[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + switch \fu_enable [2] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_branch0__insn[31:0] \dec_BRANCH_BRANCH_BRANCH__insn + case + assign $3\fus_oper_i_alu_branch0__insn[31:0] 0 + end + end + case + assign $1\fus_oper_i_alu_branch0__insn[31:0] 0 + end + sync always + update \fus_oper_i_alu_branch0__insn $0\fus_oper_i_alu_branch0__insn[31:0] + end + attribute \src "libresoc.v:46344.3-46352.6" + process $proc$libresoc.v:46344$2808 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1522$next[0:0]$2809 $1\wr_pick_dly$1522$next[0:0]$2810 + attribute \src "libresoc.v:46345.5-46345.29" + switch \initial + attribute \src "libresoc.v:46345.9-46345.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1522$next[0:0]$2810 1'0 + case + assign $1\wr_pick_dly$1522$next[0:0]$2810 \wr_pick$1519 + end + sync always + update \wr_pick_dly$1522$next $0\wr_pick_dly$1522$next[0:0]$2809 + end + attribute \src "libresoc.v:46353.3-46361.6" + process $proc$libresoc.v:46353$2811 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1538$next[0:0]$2812 $1\wr_pick_dly$1538$next[0:0]$2813 + attribute \src "libresoc.v:46354.5-46354.29" + switch \initial + attribute \src "libresoc.v:46354.9-46354.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1538$next[0:0]$2813 1'0 + case + assign $1\wr_pick_dly$1538$next[0:0]$2813 \wr_pick$1535 + end + sync always + update \wr_pick_dly$1538$next $0\wr_pick_dly$1538$next[0:0]$2812 + end + attribute \src "libresoc.v:46362.3-46391.6" + process $proc$libresoc.v:46362$2814 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_branch0__imm_data__data[63:0] $1\fus_oper_i_alu_branch0__imm_data__data[63:0] + assign $0\fus_oper_i_alu_branch0__imm_data__ok[0:0] $1\fus_oper_i_alu_branch0__imm_data__ok[0:0] + attribute \src "libresoc.v:46363.5-46363.29" + switch \initial + attribute \src "libresoc.v:46363.9-46363.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $1\fus_oper_i_alu_branch0__imm_data__data[63:0] $2\fus_oper_i_alu_branch0__imm_data__data[63:0] + assign $1\fus_oper_i_alu_branch0__imm_data__ok[0:0] $2\fus_oper_i_alu_branch0__imm_data__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_branch0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\fus_oper_i_alu_branch0__imm_data__ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_branch0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\fus_oper_i_alu_branch0__imm_data__ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign $2\fus_oper_i_alu_branch0__imm_data__data[63:0] $3\fus_oper_i_alu_branch0__imm_data__data[63:0] + assign $2\fus_oper_i_alu_branch0__imm_data__ok[0:0] $3\fus_oper_i_alu_branch0__imm_data__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + switch \fu_enable [2] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $3\fus_oper_i_alu_branch0__imm_data__ok[0:0] $3\fus_oper_i_alu_branch0__imm_data__data[63:0] } { \dec_BRANCH_BRANCH_BRANCH__imm_data__ok \dec_BRANCH_BRANCH_BRANCH__imm_data__data } + case + assign $3\fus_oper_i_alu_branch0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\fus_oper_i_alu_branch0__imm_data__ok[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_branch0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fus_oper_i_alu_branch0__imm_data__ok[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_branch0__imm_data__data $0\fus_oper_i_alu_branch0__imm_data__data[63:0] + update \fus_oper_i_alu_branch0__imm_data__ok $0\fus_oper_i_alu_branch0__imm_data__ok[0:0] + end + attribute \src "libresoc.v:46392.3-46400.6" + process $proc$libresoc.v:46392$2815 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1554$next[0:0]$2816 $1\wr_pick_dly$1554$next[0:0]$2817 + attribute \src "libresoc.v:46393.5-46393.29" + switch \initial + attribute \src "libresoc.v:46393.9-46393.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1554$next[0:0]$2817 1'0 + case + assign $1\wr_pick_dly$1554$next[0:0]$2817 \wr_pick$1551 + end + sync always + update \wr_pick_dly$1554$next $0\wr_pick_dly$1554$next[0:0]$2816 + end + attribute \src "libresoc.v:46401.3-46409.6" + process $proc$libresoc.v:46401$2818 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1570$next[0:0]$2819 $1\wr_pick_dly$1570$next[0:0]$2820 + attribute \src "libresoc.v:46402.5-46402.29" + switch \initial + attribute \src "libresoc.v:46402.9-46402.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1570$next[0:0]$2820 1'0 + case + assign $1\wr_pick_dly$1570$next[0:0]$2820 \wr_pick$1567 + end + sync always + update \wr_pick_dly$1570$next $0\wr_pick_dly$1570$next[0:0]$2819 + end + attribute \src "libresoc.v:46410.3-46418.6" + process $proc$libresoc.v:46410$2821 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1612$next[0:0]$2822 $1\wr_pick_dly$1612$next[0:0]$2823 + attribute \src "libresoc.v:46411.5-46411.29" + switch \initial + attribute \src "libresoc.v:46411.9-46411.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1612$next[0:0]$2823 1'0 + case + assign $1\wr_pick_dly$1612$next[0:0]$2823 \wr_pick$1609 + end + sync always + update \wr_pick_dly$1612$next $0\wr_pick_dly$1612$next[0:0]$2822 + end + attribute \src "libresoc.v:46419.3-46447.6" + process $proc$libresoc.v:46419$2824 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_branch0__lk[0:0] $1\fus_oper_i_alu_branch0__lk[0:0] + attribute \src "libresoc.v:46420.5-46420.29" + switch \initial + attribute \src "libresoc.v:46420.9-46420.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_branch0__lk[0:0] $2\fus_oper_i_alu_branch0__lk[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_branch0__lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_branch0__lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_branch0__lk[0:0] $3\fus_oper_i_alu_branch0__lk[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + switch \fu_enable [2] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_branch0__lk[0:0] \dec_BRANCH_BRANCH_BRANCH__lk + case + assign $3\fus_oper_i_alu_branch0__lk[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_branch0__lk[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_branch0__lk $0\fus_oper_i_alu_branch0__lk[0:0] + end + attribute \src "libresoc.v:46448.3-46456.6" + process $proc$libresoc.v:46448$2825 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1631$next[0:0]$2826 $1\wr_pick_dly$1631$next[0:0]$2827 + attribute \src "libresoc.v:46449.5-46449.29" + switch \initial + attribute \src "libresoc.v:46449.9-46449.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1631$next[0:0]$2827 1'0 + case + assign $1\wr_pick_dly$1631$next[0:0]$2827 \wr_pick$1628 + end + sync always + update \wr_pick_dly$1631$next $0\wr_pick_dly$1631$next[0:0]$2826 + end + attribute \src "libresoc.v:46457.3-46485.6" + process $proc$libresoc.v:46457$2828 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_branch0__is_32bit[0:0] $1\fus_oper_i_alu_branch0__is_32bit[0:0] + attribute \src "libresoc.v:46458.5-46458.29" + switch \initial + attribute \src "libresoc.v:46458.9-46458.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_branch0__is_32bit[0:0] $2\fus_oper_i_alu_branch0__is_32bit[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_branch0__is_32bit[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_branch0__is_32bit[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_branch0__is_32bit[0:0] $3\fus_oper_i_alu_branch0__is_32bit[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + switch \fu_enable [2] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_branch0__is_32bit[0:0] \dec_BRANCH_BRANCH_BRANCH__is_32bit + case + assign $3\fus_oper_i_alu_branch0__is_32bit[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_branch0__is_32bit[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_branch0__is_32bit $0\fus_oper_i_alu_branch0__is_32bit[0:0] + end + attribute \src "libresoc.v:46486.3-46494.6" + process $proc$libresoc.v:46486$2829 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1647$next[0:0]$2830 $1\wr_pick_dly$1647$next[0:0]$2831 + attribute \src "libresoc.v:46487.5-46487.29" + switch \initial + attribute \src "libresoc.v:46487.9-46487.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1647$next[0:0]$2831 1'0 + case + assign $1\wr_pick_dly$1647$next[0:0]$2831 \wr_pick$1644 + end + sync always + update \wr_pick_dly$1647$next $0\wr_pick_dly$1647$next[0:0]$2830 + end + attribute \src "libresoc.v:46495.3-46503.6" + process $proc$libresoc.v:46495$2832 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1663$next[0:0]$2833 $1\wr_pick_dly$1663$next[0:0]$2834 + attribute \src "libresoc.v:46496.5-46496.29" + switch \initial + attribute \src "libresoc.v:46496.9-46496.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1663$next[0:0]$2834 1'0 + case + assign $1\wr_pick_dly$1663$next[0:0]$2834 \wr_pick$1660 + end + sync always + update \wr_pick_dly$1663$next $0\wr_pick_dly$1663$next[0:0]$2833 + end + attribute \src "libresoc.v:46504.3-46532.6" + process $proc$libresoc.v:46504$2835 + assign { } { } + assign { } { } + assign $0\fus_cu_issue_i$7[0:0]$2836 $1\fus_cu_issue_i$7[0:0]$2837 + attribute \src "libresoc.v:46505.5-46505.29" + switch \initial + attribute \src "libresoc.v:46505.9-46505.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_cu_issue_i$7[0:0]$2837 $2\fus_cu_issue_i$7[0:0]$2838 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_cu_issue_i$7[0:0]$2838 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_cu_issue_i$7[0:0]$2838 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_cu_issue_i$7[0:0]$2838 $3\fus_cu_issue_i$7[0:0]$2839 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + switch \fu_enable [2] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_cu_issue_i$7[0:0]$2839 \issue_i + case + assign $3\fus_cu_issue_i$7[0:0]$2839 1'0 + end + end + case + assign $1\fus_cu_issue_i$7[0:0]$2837 1'0 + end + sync always + update \fus_cu_issue_i$7 $0\fus_cu_issue_i$7[0:0]$2836 + end + attribute \src "libresoc.v:46533.3-46541.6" + process $proc$libresoc.v:46533$2840 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1679$next[0:0]$2841 $1\wr_pick_dly$1679$next[0:0]$2842 + attribute \src "libresoc.v:46534.5-46534.29" + switch \initial + attribute \src "libresoc.v:46534.9-46534.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1679$next[0:0]$2842 1'0 + case + assign $1\wr_pick_dly$1679$next[0:0]$2842 \wr_pick$1676 + end + sync always + update \wr_pick_dly$1679$next $0\wr_pick_dly$1679$next[0:0]$2841 + end + attribute \src "libresoc.v:46542.3-46570.6" + process $proc$libresoc.v:46542$2843 + assign { } { } + assign { } { } + assign $0\fus_cu_rdmaskn_i$9[2:0]$2844 $1\fus_cu_rdmaskn_i$9[2:0]$2845 + attribute \src "libresoc.v:46543.5-46543.29" + switch \initial + attribute \src "libresoc.v:46543.9-46543.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_cu_rdmaskn_i$9[2:0]$2845 $2\fus_cu_rdmaskn_i$9[2:0]$2846 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_cu_rdmaskn_i$9[2:0]$2846 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_cu_rdmaskn_i$9[2:0]$2846 3'000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_cu_rdmaskn_i$9[2:0]$2846 $3\fus_cu_rdmaskn_i$9[2:0]$2847 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + switch \fu_enable [2] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_cu_rdmaskn_i$9[2:0]$2847 \$231 + case + assign $3\fus_cu_rdmaskn_i$9[2:0]$2847 3'000 + end + end + case + assign $1\fus_cu_rdmaskn_i$9[2:0]$2845 3'000 + end + sync always + update \fus_cu_rdmaskn_i$9 $0\fus_cu_rdmaskn_i$9[2:0]$2844 + end + attribute \src "libresoc.v:46571.3-46579.6" + process $proc$libresoc.v:46571$2848 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1723$next[0:0]$2849 $1\wr_pick_dly$1723$next[0:0]$2850 + attribute \src "libresoc.v:46572.5-46572.29" + switch \initial + attribute \src "libresoc.v:46572.9-46572.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1723$next[0:0]$2850 1'0 + case + assign $1\wr_pick_dly$1723$next[0:0]$2850 \wr_pick$1720 + end + sync always + update \wr_pick_dly$1723$next $0\wr_pick_dly$1723$next[0:0]$2849 + end + attribute \src "libresoc.v:46580.3-46588.6" + process $proc$libresoc.v:46580$2851 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1739$next[0:0]$2852 $1\wr_pick_dly$1739$next[0:0]$2853 + attribute \src "libresoc.v:46581.5-46581.29" + switch \initial + attribute \src "libresoc.v:46581.9-46581.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1739$next[0:0]$2853 1'0 + case + assign $1\wr_pick_dly$1739$next[0:0]$2853 \wr_pick$1736 + end + sync always + update \wr_pick_dly$1739$next $0\wr_pick_dly$1739$next[0:0]$2852 + end + attribute \src "libresoc.v:46589.3-46617.6" + process $proc$libresoc.v:46589$2854 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_trap0__insn_type[6:0] $1\fus_oper_i_alu_trap0__insn_type[6:0] + attribute \src "libresoc.v:46590.5-46590.29" + switch \initial + attribute \src "libresoc.v:46590.9-46590.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_trap0__insn_type[6:0] $2\fus_oper_i_alu_trap0__insn_type[6:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_trap0__insn_type[6:0] 7'0000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_trap0__insn_type[6:0] 7'0000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_trap0__insn_type[6:0] $3\fus_oper_i_alu_trap0__insn_type[6:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + switch \fu_enable [3] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_trap0__insn_type[6:0] \core_core_insn_type + case + assign $3\fus_oper_i_alu_trap0__insn_type[6:0] 7'0000000 + end + end + case + assign $1\fus_oper_i_alu_trap0__insn_type[6:0] 7'0000000 + end + sync always + update \fus_oper_i_alu_trap0__insn_type $0\fus_oper_i_alu_trap0__insn_type[6:0] + end + attribute \src "libresoc.v:46618.3-46626.6" + process $proc$libresoc.v:46618$2855 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1763$next[0:0]$2856 $1\wr_pick_dly$1763$next[0:0]$2857 + attribute \src "libresoc.v:46619.5-46619.29" + switch \initial + attribute \src "libresoc.v:46619.9-46619.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1763$next[0:0]$2857 1'0 + case + assign $1\wr_pick_dly$1763$next[0:0]$2857 \wr_pick$1760 + end + sync always + update \wr_pick_dly$1763$next $0\wr_pick_dly$1763$next[0:0]$2856 + end + attribute \src "libresoc.v:46627.3-46655.6" + process $proc$libresoc.v:46627$2858 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_trap0__fn_unit[11:0] $1\fus_oper_i_alu_trap0__fn_unit[11:0] + attribute \src "libresoc.v:46628.5-46628.29" + switch \initial + attribute \src "libresoc.v:46628.9-46628.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_trap0__fn_unit[11:0] $2\fus_oper_i_alu_trap0__fn_unit[11:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_trap0__fn_unit[11:0] 12'000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_trap0__fn_unit[11:0] 12'000000000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_trap0__fn_unit[11:0] $3\fus_oper_i_alu_trap0__fn_unit[11:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + switch \fu_enable [3] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_trap0__fn_unit[11:0] \core_core_fn_unit + case + assign $3\fus_oper_i_alu_trap0__fn_unit[11:0] 12'000000000000 + end + end + case + assign $1\fus_oper_i_alu_trap0__fn_unit[11:0] 12'000000000000 + end + sync always + update \fus_oper_i_alu_trap0__fn_unit $0\fus_oper_i_alu_trap0__fn_unit[11:0] + end + attribute \src "libresoc.v:46656.3-46664.6" + process $proc$libresoc.v:46656$2859 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1783$next[0:0]$2860 $1\wr_pick_dly$1783$next[0:0]$2861 + attribute \src "libresoc.v:46657.5-46657.29" + switch \initial + attribute \src "libresoc.v:46657.9-46657.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1783$next[0:0]$2861 1'0 + case + assign $1\wr_pick_dly$1783$next[0:0]$2861 \wr_pick$1780 + end + sync always + update \wr_pick_dly$1783$next $0\wr_pick_dly$1783$next[0:0]$2860 + end + attribute \src "libresoc.v:46665.3-46693.6" + process $proc$libresoc.v:46665$2862 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_trap0__insn[31:0] $1\fus_oper_i_alu_trap0__insn[31:0] + attribute \src "libresoc.v:46666.5-46666.29" + switch \initial + attribute \src "libresoc.v:46666.9-46666.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_trap0__insn[31:0] $2\fus_oper_i_alu_trap0__insn[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_trap0__insn[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_trap0__insn[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_trap0__insn[31:0] $3\fus_oper_i_alu_trap0__insn[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + switch \fu_enable [3] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_trap0__insn[31:0] \core_core_insn + case + assign $3\fus_oper_i_alu_trap0__insn[31:0] 0 + end + end + case + assign $1\fus_oper_i_alu_trap0__insn[31:0] 0 + end + sync always + update \fus_oper_i_alu_trap0__insn $0\fus_oper_i_alu_trap0__insn[31:0] + end + attribute \src "libresoc.v:46694.3-46722.6" + process $proc$libresoc.v:46694$2863 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_trap0__msr[63:0] $1\fus_oper_i_alu_trap0__msr[63:0] + attribute \src "libresoc.v:46695.5-46695.29" + switch \initial + attribute \src "libresoc.v:46695.9-46695.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_trap0__msr[63:0] $2\fus_oper_i_alu_trap0__msr[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_trap0__msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_trap0__msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_trap0__msr[63:0] $3\fus_oper_i_alu_trap0__msr[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + switch \fu_enable [3] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_trap0__msr[63:0] \core_core_msr + case + assign $3\fus_oper_i_alu_trap0__msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + end + case + assign $1\fus_oper_i_alu_trap0__msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_oper_i_alu_trap0__msr $0\fus_oper_i_alu_trap0__msr[63:0] + end + attribute \src "libresoc.v:46723.3-46751.6" + process $proc$libresoc.v:46723$2864 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_trap0__cia[63:0] $1\fus_oper_i_alu_trap0__cia[63:0] + attribute \src "libresoc.v:46724.5-46724.29" + switch \initial + attribute \src "libresoc.v:46724.9-46724.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_trap0__cia[63:0] $2\fus_oper_i_alu_trap0__cia[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_trap0__cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_trap0__cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_trap0__cia[63:0] $3\fus_oper_i_alu_trap0__cia[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + switch \fu_enable [3] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_trap0__cia[63:0] \core_core_cia + case + assign $3\fus_oper_i_alu_trap0__cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + end + case + assign $1\fus_oper_i_alu_trap0__cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_oper_i_alu_trap0__cia $0\fus_oper_i_alu_trap0__cia[63:0] + end + attribute \src "libresoc.v:46752.3-46780.6" + process $proc$libresoc.v:46752$2865 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_trap0__is_32bit[0:0] $1\fus_oper_i_alu_trap0__is_32bit[0:0] + attribute \src "libresoc.v:46753.5-46753.29" + switch \initial + attribute \src "libresoc.v:46753.9-46753.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_trap0__is_32bit[0:0] $2\fus_oper_i_alu_trap0__is_32bit[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_trap0__is_32bit[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_trap0__is_32bit[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_trap0__is_32bit[0:0] $3\fus_oper_i_alu_trap0__is_32bit[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + switch \fu_enable [3] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_trap0__is_32bit[0:0] \core_core_is_32bit + case + assign $3\fus_oper_i_alu_trap0__is_32bit[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_trap0__is_32bit[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_trap0__is_32bit $0\fus_oper_i_alu_trap0__is_32bit[0:0] + end + attribute \src "libresoc.v:46781.3-46809.6" + process $proc$libresoc.v:46781$2866 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_trap0__traptype[6:0] $1\fus_oper_i_alu_trap0__traptype[6:0] + attribute \src "libresoc.v:46782.5-46782.29" + switch \initial + attribute \src "libresoc.v:46782.9-46782.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_trap0__traptype[6:0] $2\fus_oper_i_alu_trap0__traptype[6:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_trap0__traptype[6:0] 7'0000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_trap0__traptype[6:0] 7'0000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_trap0__traptype[6:0] $3\fus_oper_i_alu_trap0__traptype[6:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + switch \fu_enable [3] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_trap0__traptype[6:0] \core_core_traptype + case + assign $3\fus_oper_i_alu_trap0__traptype[6:0] 7'0000000 + end + end + case + assign $1\fus_oper_i_alu_trap0__traptype[6:0] 7'0000000 + end + sync always + update \fus_oper_i_alu_trap0__traptype $0\fus_oper_i_alu_trap0__traptype[6:0] + end + attribute \src "libresoc.v:46810.3-46838.6" + process $proc$libresoc.v:46810$2867 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_trap0__trapaddr[12:0] $1\fus_oper_i_alu_trap0__trapaddr[12:0] + attribute \src "libresoc.v:46811.5-46811.29" + switch \initial + attribute \src "libresoc.v:46811.9-46811.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_trap0__trapaddr[12:0] $2\fus_oper_i_alu_trap0__trapaddr[12:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_trap0__trapaddr[12:0] 13'0000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_trap0__trapaddr[12:0] 13'0000000000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_trap0__trapaddr[12:0] $3\fus_oper_i_alu_trap0__trapaddr[12:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + switch \fu_enable [3] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_trap0__trapaddr[12:0] \core_core_trapaddr + case + assign $3\fus_oper_i_alu_trap0__trapaddr[12:0] 13'0000000000000 + end + end + case + assign $1\fus_oper_i_alu_trap0__trapaddr[12:0] 13'0000000000000 + end + sync always + update \fus_oper_i_alu_trap0__trapaddr $0\fus_oper_i_alu_trap0__trapaddr[12:0] + end + attribute \src "libresoc.v:46839.3-46867.6" + process $proc$libresoc.v:46839$2868 + assign { } { } + assign { } { } + assign $0\fus_cu_issue_i$10[0:0]$2869 $1\fus_cu_issue_i$10[0:0]$2870 + attribute \src "libresoc.v:46840.5-46840.29" + switch \initial + attribute \src "libresoc.v:46840.9-46840.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_cu_issue_i$10[0:0]$2870 $2\fus_cu_issue_i$10[0:0]$2871 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_cu_issue_i$10[0:0]$2871 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_cu_issue_i$10[0:0]$2871 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_cu_issue_i$10[0:0]$2871 $3\fus_cu_issue_i$10[0:0]$2872 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + switch \fu_enable [3] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_cu_issue_i$10[0:0]$2872 \issue_i + case + assign $3\fus_cu_issue_i$10[0:0]$2872 1'0 + end + end + case + assign $1\fus_cu_issue_i$10[0:0]$2870 1'0 + end + sync always + update \fus_cu_issue_i$10 $0\fus_cu_issue_i$10[0:0]$2869 + end + attribute \src "libresoc.v:46868.3-46896.6" + process $proc$libresoc.v:46868$2873 + assign { } { } + assign { } { } + assign $0\fus_cu_rdmaskn_i$12[3:0]$2874 $1\fus_cu_rdmaskn_i$12[3:0]$2875 + attribute \src "libresoc.v:46869.5-46869.29" + switch \initial + attribute \src "libresoc.v:46869.9-46869.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_cu_rdmaskn_i$12[3:0]$2875 $2\fus_cu_rdmaskn_i$12[3:0]$2876 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_cu_rdmaskn_i$12[3:0]$2876 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_cu_rdmaskn_i$12[3:0]$2876 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_cu_rdmaskn_i$12[3:0]$2876 $3\fus_cu_rdmaskn_i$12[3:0]$2877 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + switch \fu_enable [3] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_cu_rdmaskn_i$12[3:0]$2877 \$233 + case + assign $3\fus_cu_rdmaskn_i$12[3:0]$2877 4'0000 + end + end + case + assign $1\fus_cu_rdmaskn_i$12[3:0]$2875 4'0000 + end + sync always + update \fus_cu_rdmaskn_i$12 $0\fus_cu_rdmaskn_i$12[3:0]$2874 + end + attribute \src "libresoc.v:46897.3-46925.6" + process $proc$libresoc.v:46897$2878 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_logical0__insn_type[6:0] $1\fus_oper_i_alu_logical0__insn_type[6:0] + attribute \src "libresoc.v:46898.5-46898.29" + switch \initial + attribute \src "libresoc.v:46898.9-46898.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_logical0__insn_type[6:0] $2\fus_oper_i_alu_logical0__insn_type[6:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_logical0__insn_type[6:0] 7'0000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_logical0__insn_type[6:0] 7'0000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_logical0__insn_type[6:0] $3\fus_oper_i_alu_logical0__insn_type[6:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + switch \fu_enable [4] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_logical0__insn_type[6:0] \dec_LOGICAL_LOGICAL_LOGICAL__insn_type + case + assign $3\fus_oper_i_alu_logical0__insn_type[6:0] 7'0000000 + end + end + case + assign $1\fus_oper_i_alu_logical0__insn_type[6:0] 7'0000000 + end + sync always + update \fus_oper_i_alu_logical0__insn_type $0\fus_oper_i_alu_logical0__insn_type[6:0] + end + attribute \src "libresoc.v:46926.3-46954.6" + process $proc$libresoc.v:46926$2879 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_logical0__fn_unit[11:0] $1\fus_oper_i_alu_logical0__fn_unit[11:0] + attribute \src "libresoc.v:46927.5-46927.29" + switch \initial + attribute \src "libresoc.v:46927.9-46927.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_logical0__fn_unit[11:0] $2\fus_oper_i_alu_logical0__fn_unit[11:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_logical0__fn_unit[11:0] 12'000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_logical0__fn_unit[11:0] 12'000000000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_logical0__fn_unit[11:0] $3\fus_oper_i_alu_logical0__fn_unit[11:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + switch \fu_enable [4] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_logical0__fn_unit[11:0] \dec_LOGICAL_LOGICAL_LOGICAL__fn_unit + case + assign $3\fus_oper_i_alu_logical0__fn_unit[11:0] 12'000000000000 + end + end + case + assign $1\fus_oper_i_alu_logical0__fn_unit[11:0] 12'000000000000 + end + sync always + update \fus_oper_i_alu_logical0__fn_unit $0\fus_oper_i_alu_logical0__fn_unit[11:0] + end + attribute \src "libresoc.v:46955.3-46984.6" + process $proc$libresoc.v:46955$2880 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_logical0__imm_data__data[63:0] $1\fus_oper_i_alu_logical0__imm_data__data[63:0] + assign $0\fus_oper_i_alu_logical0__imm_data__ok[0:0] $1\fus_oper_i_alu_logical0__imm_data__ok[0:0] + attribute \src "libresoc.v:46956.5-46956.29" + switch \initial + attribute \src "libresoc.v:46956.9-46956.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $1\fus_oper_i_alu_logical0__imm_data__data[63:0] $2\fus_oper_i_alu_logical0__imm_data__data[63:0] + assign $1\fus_oper_i_alu_logical0__imm_data__ok[0:0] $2\fus_oper_i_alu_logical0__imm_data__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_logical0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\fus_oper_i_alu_logical0__imm_data__ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_logical0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\fus_oper_i_alu_logical0__imm_data__ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign $2\fus_oper_i_alu_logical0__imm_data__data[63:0] $3\fus_oper_i_alu_logical0__imm_data__data[63:0] + assign $2\fus_oper_i_alu_logical0__imm_data__ok[0:0] $3\fus_oper_i_alu_logical0__imm_data__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + switch \fu_enable [4] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $3\fus_oper_i_alu_logical0__imm_data__ok[0:0] $3\fus_oper_i_alu_logical0__imm_data__data[63:0] } { \dec_LOGICAL_LOGICAL_LOGICAL__imm_data__ok \dec_LOGICAL_LOGICAL_LOGICAL__imm_data__data } + case + assign $3\fus_oper_i_alu_logical0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\fus_oper_i_alu_logical0__imm_data__ok[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_logical0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fus_oper_i_alu_logical0__imm_data__ok[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_logical0__imm_data__data $0\fus_oper_i_alu_logical0__imm_data__data[63:0] + update \fus_oper_i_alu_logical0__imm_data__ok $0\fus_oper_i_alu_logical0__imm_data__ok[0:0] + end + attribute \src "libresoc.v:46985.3-47014.6" + process $proc$libresoc.v:46985$2881 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_logical0__rc__ok[0:0] $1\fus_oper_i_alu_logical0__rc__ok[0:0] + assign $0\fus_oper_i_alu_logical0__rc__rc[0:0] $1\fus_oper_i_alu_logical0__rc__rc[0:0] + attribute \src "libresoc.v:46986.5-46986.29" + switch \initial + attribute \src "libresoc.v:46986.9-46986.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $1\fus_oper_i_alu_logical0__rc__ok[0:0] $2\fus_oper_i_alu_logical0__rc__ok[0:0] + assign $1\fus_oper_i_alu_logical0__rc__rc[0:0] $2\fus_oper_i_alu_logical0__rc__rc[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_logical0__rc__ok[0:0] 1'0 + assign $2\fus_oper_i_alu_logical0__rc__rc[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_logical0__rc__ok[0:0] 1'0 + assign $2\fus_oper_i_alu_logical0__rc__rc[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign $2\fus_oper_i_alu_logical0__rc__ok[0:0] $3\fus_oper_i_alu_logical0__rc__ok[0:0] + assign $2\fus_oper_i_alu_logical0__rc__rc[0:0] $3\fus_oper_i_alu_logical0__rc__rc[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + switch \fu_enable [4] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $3\fus_oper_i_alu_logical0__rc__ok[0:0] $3\fus_oper_i_alu_logical0__rc__rc[0:0] } { \dec_LOGICAL_LOGICAL_LOGICAL__rc__ok \dec_LOGICAL_LOGICAL_LOGICAL__rc__rc } + case + assign $3\fus_oper_i_alu_logical0__rc__ok[0:0] 1'0 + assign $3\fus_oper_i_alu_logical0__rc__rc[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_logical0__rc__ok[0:0] 1'0 + assign $1\fus_oper_i_alu_logical0__rc__rc[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_logical0__rc__ok $0\fus_oper_i_alu_logical0__rc__ok[0:0] + update \fus_oper_i_alu_logical0__rc__rc $0\fus_oper_i_alu_logical0__rc__rc[0:0] + end + attribute \src "libresoc.v:47015.3-47044.6" + process $proc$libresoc.v:47015$2882 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_logical0__oe__oe[0:0] $1\fus_oper_i_alu_logical0__oe__oe[0:0] + assign $0\fus_oper_i_alu_logical0__oe__ok[0:0] $1\fus_oper_i_alu_logical0__oe__ok[0:0] + attribute \src "libresoc.v:47016.5-47016.29" + switch \initial + attribute \src "libresoc.v:47016.9-47016.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $1\fus_oper_i_alu_logical0__oe__oe[0:0] $2\fus_oper_i_alu_logical0__oe__oe[0:0] + assign $1\fus_oper_i_alu_logical0__oe__ok[0:0] $2\fus_oper_i_alu_logical0__oe__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_logical0__oe__oe[0:0] 1'0 + assign $2\fus_oper_i_alu_logical0__oe__ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_logical0__oe__oe[0:0] 1'0 + assign $2\fus_oper_i_alu_logical0__oe__ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign $2\fus_oper_i_alu_logical0__oe__oe[0:0] $3\fus_oper_i_alu_logical0__oe__oe[0:0] + assign $2\fus_oper_i_alu_logical0__oe__ok[0:0] $3\fus_oper_i_alu_logical0__oe__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + switch \fu_enable [4] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $3\fus_oper_i_alu_logical0__oe__ok[0:0] $3\fus_oper_i_alu_logical0__oe__oe[0:0] } { \dec_LOGICAL_LOGICAL_LOGICAL__oe__ok \dec_LOGICAL_LOGICAL_LOGICAL__oe__oe } + case + assign $3\fus_oper_i_alu_logical0__oe__oe[0:0] 1'0 + assign $3\fus_oper_i_alu_logical0__oe__ok[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_logical0__oe__oe[0:0] 1'0 + assign $1\fus_oper_i_alu_logical0__oe__ok[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_logical0__oe__oe $0\fus_oper_i_alu_logical0__oe__oe[0:0] + update \fus_oper_i_alu_logical0__oe__ok $0\fus_oper_i_alu_logical0__oe__ok[0:0] + end + attribute \src "libresoc.v:47045.3-47073.6" + process $proc$libresoc.v:47045$2883 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_logical0__invert_in[0:0] $1\fus_oper_i_alu_logical0__invert_in[0:0] + attribute \src "libresoc.v:47046.5-47046.29" + switch \initial + attribute \src "libresoc.v:47046.9-47046.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_logical0__invert_in[0:0] $2\fus_oper_i_alu_logical0__invert_in[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_logical0__invert_in[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_logical0__invert_in[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_logical0__invert_in[0:0] $3\fus_oper_i_alu_logical0__invert_in[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + switch \fu_enable [4] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_logical0__invert_in[0:0] \dec_LOGICAL_LOGICAL_LOGICAL__invert_in + case + assign $3\fus_oper_i_alu_logical0__invert_in[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_logical0__invert_in[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_logical0__invert_in $0\fus_oper_i_alu_logical0__invert_in[0:0] + end + attribute \src "libresoc.v:47074.3-47102.6" + process $proc$libresoc.v:47074$2884 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_logical0__zero_a[0:0] $1\fus_oper_i_alu_logical0__zero_a[0:0] + attribute \src "libresoc.v:47075.5-47075.29" + switch \initial + attribute \src "libresoc.v:47075.9-47075.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_logical0__zero_a[0:0] $2\fus_oper_i_alu_logical0__zero_a[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_logical0__zero_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_logical0__zero_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_logical0__zero_a[0:0] $3\fus_oper_i_alu_logical0__zero_a[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + switch \fu_enable [4] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_logical0__zero_a[0:0] \dec_LOGICAL_LOGICAL_LOGICAL__zero_a + case + assign $3\fus_oper_i_alu_logical0__zero_a[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_logical0__zero_a[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_logical0__zero_a $0\fus_oper_i_alu_logical0__zero_a[0:0] + end + attribute \src "libresoc.v:47103.3-47131.6" + process $proc$libresoc.v:47103$2885 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_logical0__input_carry[1:0] $1\fus_oper_i_alu_logical0__input_carry[1:0] + attribute \src "libresoc.v:47104.5-47104.29" + switch \initial + attribute \src "libresoc.v:47104.9-47104.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_logical0__input_carry[1:0] $2\fus_oper_i_alu_logical0__input_carry[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_logical0__input_carry[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_logical0__input_carry[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_logical0__input_carry[1:0] $3\fus_oper_i_alu_logical0__input_carry[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + switch \fu_enable [4] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_logical0__input_carry[1:0] \dec_LOGICAL_LOGICAL_LOGICAL__input_carry + case + assign $3\fus_oper_i_alu_logical0__input_carry[1:0] 2'00 + end + end + case + assign $1\fus_oper_i_alu_logical0__input_carry[1:0] 2'00 + end + sync always + update \fus_oper_i_alu_logical0__input_carry $0\fus_oper_i_alu_logical0__input_carry[1:0] + end + attribute \src "libresoc.v:47132.3-47160.6" + process $proc$libresoc.v:47132$2886 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_logical0__invert_out[0:0] $1\fus_oper_i_alu_logical0__invert_out[0:0] + attribute \src "libresoc.v:47133.5-47133.29" + switch \initial + attribute \src "libresoc.v:47133.9-47133.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_logical0__invert_out[0:0] $2\fus_oper_i_alu_logical0__invert_out[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_logical0__invert_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_logical0__invert_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_logical0__invert_out[0:0] $3\fus_oper_i_alu_logical0__invert_out[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + switch \fu_enable [4] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_logical0__invert_out[0:0] \dec_LOGICAL_LOGICAL_LOGICAL__invert_out + case + assign $3\fus_oper_i_alu_logical0__invert_out[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_logical0__invert_out[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_logical0__invert_out $0\fus_oper_i_alu_logical0__invert_out[0:0] + end + attribute \src "libresoc.v:47161.3-47189.6" + process $proc$libresoc.v:47161$2887 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_logical0__write_cr0[0:0] $1\fus_oper_i_alu_logical0__write_cr0[0:0] + attribute \src "libresoc.v:47162.5-47162.29" + switch \initial + attribute \src "libresoc.v:47162.9-47162.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_logical0__write_cr0[0:0] $2\fus_oper_i_alu_logical0__write_cr0[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_logical0__write_cr0[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_logical0__write_cr0[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_logical0__write_cr0[0:0] $3\fus_oper_i_alu_logical0__write_cr0[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + switch \fu_enable [4] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_logical0__write_cr0[0:0] \dec_LOGICAL_LOGICAL_LOGICAL__write_cr0 + case + assign $3\fus_oper_i_alu_logical0__write_cr0[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_logical0__write_cr0[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_logical0__write_cr0 $0\fus_oper_i_alu_logical0__write_cr0[0:0] + end + attribute \src "libresoc.v:47190.3-47218.6" + process $proc$libresoc.v:47190$2888 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_logical0__output_carry[0:0] $1\fus_oper_i_alu_logical0__output_carry[0:0] + attribute \src "libresoc.v:47191.5-47191.29" + switch \initial + attribute \src "libresoc.v:47191.9-47191.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_logical0__output_carry[0:0] $2\fus_oper_i_alu_logical0__output_carry[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_logical0__output_carry[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_logical0__output_carry[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_logical0__output_carry[0:0] $3\fus_oper_i_alu_logical0__output_carry[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + switch \fu_enable [4] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_logical0__output_carry[0:0] \dec_LOGICAL_LOGICAL_LOGICAL__output_carry + case + assign $3\fus_oper_i_alu_logical0__output_carry[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_logical0__output_carry[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_logical0__output_carry $0\fus_oper_i_alu_logical0__output_carry[0:0] + end + attribute \src "libresoc.v:47219.3-47247.6" + process $proc$libresoc.v:47219$2889 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_logical0__is_32bit[0:0] $1\fus_oper_i_alu_logical0__is_32bit[0:0] + attribute \src "libresoc.v:47220.5-47220.29" + switch \initial + attribute \src "libresoc.v:47220.9-47220.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_logical0__is_32bit[0:0] $2\fus_oper_i_alu_logical0__is_32bit[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_logical0__is_32bit[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_logical0__is_32bit[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_logical0__is_32bit[0:0] $3\fus_oper_i_alu_logical0__is_32bit[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + switch \fu_enable [4] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_logical0__is_32bit[0:0] \dec_LOGICAL_LOGICAL_LOGICAL__is_32bit + case + assign $3\fus_oper_i_alu_logical0__is_32bit[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_logical0__is_32bit[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_logical0__is_32bit $0\fus_oper_i_alu_logical0__is_32bit[0:0] + end + attribute \src "libresoc.v:47248.3-47276.6" + process $proc$libresoc.v:47248$2890 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_logical0__is_signed[0:0] $1\fus_oper_i_alu_logical0__is_signed[0:0] + attribute \src "libresoc.v:47249.5-47249.29" + switch \initial + attribute \src "libresoc.v:47249.9-47249.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_logical0__is_signed[0:0] $2\fus_oper_i_alu_logical0__is_signed[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_logical0__is_signed[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_logical0__is_signed[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_logical0__is_signed[0:0] $3\fus_oper_i_alu_logical0__is_signed[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + switch \fu_enable [4] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_logical0__is_signed[0:0] \dec_LOGICAL_LOGICAL_LOGICAL__is_signed + case + assign $3\fus_oper_i_alu_logical0__is_signed[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_logical0__is_signed[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_logical0__is_signed $0\fus_oper_i_alu_logical0__is_signed[0:0] + end + attribute \src "libresoc.v:47277.3-47305.6" + process $proc$libresoc.v:47277$2891 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_logical0__data_len[3:0] $1\fus_oper_i_alu_logical0__data_len[3:0] + attribute \src "libresoc.v:47278.5-47278.29" + switch \initial + attribute \src "libresoc.v:47278.9-47278.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_logical0__data_len[3:0] $2\fus_oper_i_alu_logical0__data_len[3:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_logical0__data_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_logical0__data_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_logical0__data_len[3:0] $3\fus_oper_i_alu_logical0__data_len[3:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + switch \fu_enable [4] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_logical0__data_len[3:0] \dec_LOGICAL_LOGICAL_LOGICAL__data_len + case + assign $3\fus_oper_i_alu_logical0__data_len[3:0] 4'0000 + end + end + case + assign $1\fus_oper_i_alu_logical0__data_len[3:0] 4'0000 + end + sync always + update \fus_oper_i_alu_logical0__data_len $0\fus_oper_i_alu_logical0__data_len[3:0] + end + attribute \src "libresoc.v:47306.3-47334.6" + process $proc$libresoc.v:47306$2892 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_logical0__insn[31:0] $1\fus_oper_i_alu_logical0__insn[31:0] + attribute \src "libresoc.v:47307.5-47307.29" + switch \initial + attribute \src "libresoc.v:47307.9-47307.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_logical0__insn[31:0] $2\fus_oper_i_alu_logical0__insn[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_logical0__insn[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_logical0__insn[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_logical0__insn[31:0] $3\fus_oper_i_alu_logical0__insn[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + switch \fu_enable [4] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_logical0__insn[31:0] \dec_LOGICAL_LOGICAL_LOGICAL__insn + case + assign $3\fus_oper_i_alu_logical0__insn[31:0] 0 + end + end + case + assign $1\fus_oper_i_alu_logical0__insn[31:0] 0 + end + sync always + update \fus_oper_i_alu_logical0__insn $0\fus_oper_i_alu_logical0__insn[31:0] + end + attribute \src "libresoc.v:47335.3-47363.6" + process $proc$libresoc.v:47335$2893 + assign { } { } + assign { } { } + assign $0\fus_cu_issue_i$13[0:0]$2894 $1\fus_cu_issue_i$13[0:0]$2895 + attribute \src "libresoc.v:47336.5-47336.29" + switch \initial + attribute \src "libresoc.v:47336.9-47336.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_cu_issue_i$13[0:0]$2895 $2\fus_cu_issue_i$13[0:0]$2896 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_cu_issue_i$13[0:0]$2896 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_cu_issue_i$13[0:0]$2896 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_cu_issue_i$13[0:0]$2896 $3\fus_cu_issue_i$13[0:0]$2897 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + switch \fu_enable [4] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_cu_issue_i$13[0:0]$2897 \issue_i + case + assign $3\fus_cu_issue_i$13[0:0]$2897 1'0 + end + end + case + assign $1\fus_cu_issue_i$13[0:0]$2895 1'0 + end + sync always + update \fus_cu_issue_i$13 $0\fus_cu_issue_i$13[0:0]$2894 + end + attribute \src "libresoc.v:47364.3-47392.6" + process $proc$libresoc.v:47364$2898 + assign { } { } + assign { } { } + assign $0\fus_cu_rdmaskn_i$15[2:0]$2899 $1\fus_cu_rdmaskn_i$15[2:0]$2900 + attribute \src "libresoc.v:47365.5-47365.29" + switch \initial + attribute \src "libresoc.v:47365.9-47365.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_cu_rdmaskn_i$15[2:0]$2900 $2\fus_cu_rdmaskn_i$15[2:0]$2901 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_cu_rdmaskn_i$15[2:0]$2901 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_cu_rdmaskn_i$15[2:0]$2901 3'000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_cu_rdmaskn_i$15[2:0]$2901 $3\fus_cu_rdmaskn_i$15[2:0]$2902 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + switch \fu_enable [4] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_cu_rdmaskn_i$15[2:0]$2902 \$235 + case + assign $3\fus_cu_rdmaskn_i$15[2:0]$2902 3'000 + end + end + case + assign $1\fus_cu_rdmaskn_i$15[2:0]$2900 3'000 + end + sync always + update \fus_cu_rdmaskn_i$15 $0\fus_cu_rdmaskn_i$15[2:0]$2899 + end + attribute \src "libresoc.v:47393.3-47421.6" + process $proc$libresoc.v:47393$2903 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_spr0__insn_type[6:0] $1\fus_oper_i_alu_spr0__insn_type[6:0] + attribute \src "libresoc.v:47394.5-47394.29" + switch \initial + attribute \src "libresoc.v:47394.9-47394.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_spr0__insn_type[6:0] $2\fus_oper_i_alu_spr0__insn_type[6:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_spr0__insn_type[6:0] 7'0000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_spr0__insn_type[6:0] 7'0000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_spr0__insn_type[6:0] $3\fus_oper_i_alu_spr0__insn_type[6:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + switch \fu_enable [5] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_spr0__insn_type[6:0] \dec_SPR_SPR_SPR__insn_type + case + assign $3\fus_oper_i_alu_spr0__insn_type[6:0] 7'0000000 + end + end + case + assign $1\fus_oper_i_alu_spr0__insn_type[6:0] 7'0000000 + end + sync always + update \fus_oper_i_alu_spr0__insn_type $0\fus_oper_i_alu_spr0__insn_type[6:0] + end + attribute \src "libresoc.v:47422.3-47450.6" + process $proc$libresoc.v:47422$2904 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_spr0__fn_unit[11:0] $1\fus_oper_i_alu_spr0__fn_unit[11:0] + attribute \src "libresoc.v:47423.5-47423.29" + switch \initial + attribute \src "libresoc.v:47423.9-47423.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_spr0__fn_unit[11:0] $2\fus_oper_i_alu_spr0__fn_unit[11:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_spr0__fn_unit[11:0] 12'000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_spr0__fn_unit[11:0] 12'000000000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_spr0__fn_unit[11:0] $3\fus_oper_i_alu_spr0__fn_unit[11:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + switch \fu_enable [5] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_spr0__fn_unit[11:0] \dec_SPR_SPR_SPR__fn_unit + case + assign $3\fus_oper_i_alu_spr0__fn_unit[11:0] 12'000000000000 + end + end + case + assign $1\fus_oper_i_alu_spr0__fn_unit[11:0] 12'000000000000 + end + sync always + update \fus_oper_i_alu_spr0__fn_unit $0\fus_oper_i_alu_spr0__fn_unit[11:0] + end + attribute \src "libresoc.v:47451.3-47479.6" + process $proc$libresoc.v:47451$2905 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_spr0__insn[31:0] $1\fus_oper_i_alu_spr0__insn[31:0] + attribute \src "libresoc.v:47452.5-47452.29" + switch \initial + attribute \src "libresoc.v:47452.9-47452.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_spr0__insn[31:0] $2\fus_oper_i_alu_spr0__insn[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_spr0__insn[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_spr0__insn[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_spr0__insn[31:0] $3\fus_oper_i_alu_spr0__insn[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + switch \fu_enable [5] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_spr0__insn[31:0] \dec_SPR_SPR_SPR__insn + case + assign $3\fus_oper_i_alu_spr0__insn[31:0] 0 + end + end + case + assign $1\fus_oper_i_alu_spr0__insn[31:0] 0 + end + sync always + update \fus_oper_i_alu_spr0__insn $0\fus_oper_i_alu_spr0__insn[31:0] + end + connect \$1000 $ternary$libresoc.v:41097$1514_Y + connect \$1002 $and$libresoc.v:41098$1515_Y + connect \$1005 $and$libresoc.v:41099$1516_Y + connect \$1009 $not$libresoc.v:41100$1517_Y + connect \$1011 $and$libresoc.v:41101$1518_Y + connect \$1015 $and$libresoc.v:41102$1519_Y + connect \$1018 $ternary$libresoc.v:41103$1520_Y + connect \$1020 $and$libresoc.v:41104$1521_Y + connect \$1023 $and$libresoc.v:41105$1522_Y + connect \$1027 $not$libresoc.v:41106$1523_Y + connect \$1029 $and$libresoc.v:41107$1524_Y + connect \$1037 $and$libresoc.v:41108$1525_Y + connect \$1040 $ternary$libresoc.v:41109$1526_Y + connect \$1042 $and$libresoc.v:41110$1527_Y + connect \$1045 $and$libresoc.v:41111$1528_Y + connect \$1049 $not$libresoc.v:41112$1529_Y + connect \$1051 $and$libresoc.v:41113$1530_Y + connect \$1057 $and$libresoc.v:41114$1531_Y + connect \$1060 $ternary$libresoc.v:41115$1532_Y + connect \$1062 $and$libresoc.v:41116$1533_Y + connect \$1065 $and$libresoc.v:41117$1534_Y + connect \$1069 $not$libresoc.v:41118$1535_Y + connect \$1071 $and$libresoc.v:41119$1536_Y + connect \$1077 $and$libresoc.v:41120$1537_Y + connect \$1080 $ternary$libresoc.v:41121$1538_Y + connect \$1082 $and$libresoc.v:41122$1539_Y + connect \$1085 $and$libresoc.v:41123$1540_Y + connect \$1089 $not$libresoc.v:41124$1541_Y + connect \$1091 $and$libresoc.v:41125$1542_Y + connect \$1096 $and$libresoc.v:41126$1543_Y + connect \$1099 $ternary$libresoc.v:41127$1544_Y + connect \$1101 $and$libresoc.v:41128$1545_Y + connect \$1104 $and$libresoc.v:41129$1546_Y + connect \$1108 $not$libresoc.v:41130$1547_Y + connect \$1110 $and$libresoc.v:41131$1548_Y + connect \$1114 $and$libresoc.v:41132$1549_Y + connect \$1117 $ternary$libresoc.v:41133$1550_Y + connect \$1119 $and$libresoc.v:41134$1551_Y + connect \$1122 $and$libresoc.v:41135$1552_Y + connect \$1125 $not$libresoc.v:41136$1553_Y + connect \$1127 $and$libresoc.v:41137$1554_Y + connect \$1130 $and$libresoc.v:41138$1555_Y + connect \$1133 $ternary$libresoc.v:41139$1556_Y + connect \$1136 $or$libresoc.v:41140$1557_Y + connect \$1138 $or$libresoc.v:41141$1558_Y + connect \$1140 $or$libresoc.v:41142$1559_Y + connect \$1142 $or$libresoc.v:41143$1560_Y + connect \$1144 $or$libresoc.v:41144$1561_Y + connect \$1146 $or$libresoc.v:41145$1562_Y + connect \$1148 $or$libresoc.v:41146$1563_Y + connect \$1150 $or$libresoc.v:41147$1564_Y + connect \$1152 $or$libresoc.v:41148$1565_Y + connect \$1154 $or$libresoc.v:41149$1566_Y + connect \$1156 $or$libresoc.v:41150$1567_Y + connect \$1158 $or$libresoc.v:41151$1568_Y + connect \$1160 $or$libresoc.v:41152$1569_Y + connect \$1162 $or$libresoc.v:41153$1570_Y + connect \$1164 $or$libresoc.v:41154$1571_Y + connect \$1166 $or$libresoc.v:41155$1572_Y + connect \$1168 $or$libresoc.v:41156$1573_Y + connect \$1170 $or$libresoc.v:41157$1574_Y + connect \$1172 $or$libresoc.v:41158$1575_Y + connect \$1174 $or$libresoc.v:41159$1576_Y + connect \$1176 $or$libresoc.v:41160$1577_Y + connect \$1178 $or$libresoc.v:41161$1578_Y + connect \$1180 $or$libresoc.v:41162$1579_Y + connect \$1182 $or$libresoc.v:41163$1580_Y + connect \$1184 $or$libresoc.v:41164$1581_Y + connect \$1186 $or$libresoc.v:41165$1582_Y + connect \$1188 $or$libresoc.v:41166$1583_Y + connect \$1190 $and$libresoc.v:41167$1584_Y + connect \$1192 $and$libresoc.v:41168$1585_Y + connect \$1195 $and$libresoc.v:41169$1586_Y + connect \$1198 $not$libresoc.v:41170$1587_Y + connect \$1200 $and$libresoc.v:41171$1588_Y + connect \$1203 $and$libresoc.v:41172$1589_Y + connect \$1206 $ternary$libresoc.v:41173$1590_Y + connect \$1208 $and$libresoc.v:41174$1591_Y + connect \$1210 $and$libresoc.v:41175$1592_Y + connect \$1212 $and$libresoc.v:41176$1593_Y + connect \$1214 $and$libresoc.v:41177$1594_Y + connect \$1216 $and$libresoc.v:41178$1595_Y + connect \$1218 $and$libresoc.v:41179$1596_Y + connect \$1220 $and$libresoc.v:41180$1597_Y + connect \$1223 $and$libresoc.v:41181$1598_Y + connect \$1226 $not$libresoc.v:41182$1599_Y + connect \$1228 $and$libresoc.v:41183$1600_Y + connect \$1231 $and$libresoc.v:41184$1601_Y + connect \$1234 $sub$libresoc.v:41185$1602_Y + connect \$1236 $sshl$libresoc.v:41186$1603_Y + connect \$1238 $ternary$libresoc.v:41187$1604_Y + connect \$1240 $and$libresoc.v:41188$1605_Y + connect \$1243 $and$libresoc.v:41189$1606_Y + connect \$1246 $not$libresoc.v:41190$1607_Y + connect \$1248 $and$libresoc.v:41191$1608_Y + connect \$1251 $and$libresoc.v:41192$1609_Y + connect \$1254 $sub$libresoc.v:41193$1610_Y + connect \$1256 $sshl$libresoc.v:41194$1611_Y + connect \$1258 $ternary$libresoc.v:41195$1612_Y + connect \$1260 $and$libresoc.v:41196$1613_Y + connect \$1263 $and$libresoc.v:41197$1614_Y + connect \$1266 $not$libresoc.v:41198$1615_Y + connect \$1268 $and$libresoc.v:41199$1616_Y + connect \$1271 $and$libresoc.v:41200$1617_Y + connect \$1274 $sub$libresoc.v:41201$1618_Y + connect \$1276 $sshl$libresoc.v:41202$1619_Y + connect \$1278 $ternary$libresoc.v:41203$1620_Y + connect \$1280 $and$libresoc.v:41204$1621_Y + connect \$1283 $and$libresoc.v:41205$1622_Y + connect \$1286 $not$libresoc.v:41206$1623_Y + connect \$1288 $and$libresoc.v:41207$1624_Y + connect \$1291 $and$libresoc.v:41208$1625_Y + connect \$1294 $sub$libresoc.v:41209$1626_Y + connect \$1296 $sshl$libresoc.v:41210$1627_Y + connect \$1298 $ternary$libresoc.v:41211$1628_Y + connect \$1300 $and$libresoc.v:41212$1629_Y + connect \$1303 $and$libresoc.v:41213$1630_Y + connect \$1306 $not$libresoc.v:41214$1631_Y + connect \$1308 $and$libresoc.v:41215$1632_Y + connect \$1311 $and$libresoc.v:41216$1633_Y + connect \$1314 $sub$libresoc.v:41217$1634_Y + connect \$1316 $sshl$libresoc.v:41218$1635_Y + connect \$1318 $ternary$libresoc.v:41219$1636_Y + connect \$1320 $and$libresoc.v:41220$1637_Y + connect \$1323 $and$libresoc.v:41221$1638_Y + connect \$1326 $not$libresoc.v:41222$1639_Y + connect \$1328 $and$libresoc.v:41223$1640_Y + connect \$1331 $and$libresoc.v:41224$1641_Y + connect \$1334 $sub$libresoc.v:41225$1642_Y + connect \$1336 $sshl$libresoc.v:41226$1643_Y + connect \$1338 $ternary$libresoc.v:41227$1644_Y + connect \$1340 $or$libresoc.v:41228$1645_Y + connect \$1342 $or$libresoc.v:41229$1646_Y + connect \$1344 $or$libresoc.v:41230$1647_Y + connect \$1346 $or$libresoc.v:41231$1648_Y + connect \$1348 $or$libresoc.v:41232$1649_Y + connect \$1351 $or$libresoc.v:41233$1650_Y + connect \$1353 $or$libresoc.v:41234$1651_Y + connect \$1355 $or$libresoc.v:41235$1652_Y + connect \$1357 $or$libresoc.v:41236$1653_Y + connect \$1359 $or$libresoc.v:41237$1654_Y + connect \$1361 $and$libresoc.v:41238$1655_Y + connect \$1363 $and$libresoc.v:41239$1656_Y + connect \$1365 $and$libresoc.v:41240$1657_Y + connect \$1367 $and$libresoc.v:41241$1658_Y + connect \$1370 $and$libresoc.v:41242$1659_Y + connect \$1373 $not$libresoc.v:41243$1660_Y + connect \$1375 $and$libresoc.v:41244$1661_Y + connect \$1378 $and$libresoc.v:41245$1662_Y + connect \$1381 $ternary$libresoc.v:41246$1663_Y + connect \$1383 $and$libresoc.v:41247$1664_Y + connect \$1386 $and$libresoc.v:41248$1665_Y + connect \$1389 $not$libresoc.v:41249$1666_Y + connect \$1391 $and$libresoc.v:41250$1667_Y + connect \$1394 $and$libresoc.v:41251$1668_Y + connect \$1397 $ternary$libresoc.v:41252$1669_Y + connect \$1399 $and$libresoc.v:41253$1670_Y + connect \$1402 $and$libresoc.v:41254$1671_Y + connect \$1405 $not$libresoc.v:41255$1672_Y + connect \$1407 $and$libresoc.v:41256$1673_Y + connect \$1410 $and$libresoc.v:41257$1674_Y + connect \$1413 $ternary$libresoc.v:41258$1675_Y + connect \$1415 $or$libresoc.v:41259$1676_Y + connect \$1417 $or$libresoc.v:41260$1677_Y + connect \$1420 $or$libresoc.v:41261$1678_Y + connect \$1422 $or$libresoc.v:41262$1679_Y + connect \$1419 $pos$libresoc.v:41263$1681_Y + connect \$1425 $and$libresoc.v:41264$1682_Y + connect \$1427 $and$libresoc.v:41265$1683_Y + connect \$1429 $and$libresoc.v:41266$1684_Y + connect \$1431 $and$libresoc.v:41267$1685_Y + connect \$1433 $and$libresoc.v:41268$1686_Y + connect \$1436 $and$libresoc.v:41269$1687_Y + connect \$1439 $not$libresoc.v:41270$1688_Y + connect \$1441 $and$libresoc.v:41271$1689_Y + connect \$1444 $and$libresoc.v:41272$1690_Y + connect \$1447 $ternary$libresoc.v:41273$1691_Y + connect \$1449 $and$libresoc.v:41274$1692_Y + connect \$1452 $and$libresoc.v:41275$1693_Y + connect \$1455 $not$libresoc.v:41276$1694_Y + connect \$1457 $and$libresoc.v:41277$1695_Y + connect \$1460 $and$libresoc.v:41278$1696_Y + connect \$1463 $ternary$libresoc.v:41279$1697_Y + connect \$1465 $and$libresoc.v:41280$1698_Y + connect \$1468 $and$libresoc.v:41281$1699_Y + connect \$1471 $not$libresoc.v:41282$1700_Y + connect \$1473 $and$libresoc.v:41283$1701_Y + connect \$1476 $and$libresoc.v:41284$1702_Y + connect \$1479 $ternary$libresoc.v:41285$1703_Y + connect \$1481 $and$libresoc.v:41286$1704_Y + connect \$1484 $and$libresoc.v:41287$1705_Y + connect \$1487 $not$libresoc.v:41288$1706_Y + connect \$1489 $and$libresoc.v:41289$1707_Y + connect \$1492 $and$libresoc.v:41290$1708_Y + connect \$1495 $ternary$libresoc.v:41291$1709_Y + connect \$1497 $or$libresoc.v:41292$1710_Y + connect \$1499 $or$libresoc.v:41293$1711_Y + connect \$1501 $or$libresoc.v:41294$1712_Y + connect \$1503 $or$libresoc.v:41295$1713_Y + connect \$1505 $or$libresoc.v:41296$1714_Y + connect \$1507 $or$libresoc.v:41297$1715_Y + connect \$1509 $and$libresoc.v:41298$1716_Y + connect \$1511 $and$libresoc.v:41299$1717_Y + connect \$1513 $and$libresoc.v:41300$1718_Y + connect \$1515 $and$libresoc.v:41301$1719_Y + connect \$1517 $and$libresoc.v:41302$1720_Y + connect \$1520 $and$libresoc.v:41303$1721_Y + connect \$1523 $not$libresoc.v:41304$1722_Y + connect \$1525 $and$libresoc.v:41305$1723_Y + connect \$1528 $and$libresoc.v:41306$1724_Y + connect \$1531 $ternary$libresoc.v:41307$1725_Y + connect \$1533 $and$libresoc.v:41308$1726_Y + connect \$1536 $and$libresoc.v:41309$1727_Y + connect \$1539 $not$libresoc.v:41310$1728_Y + connect \$1541 $and$libresoc.v:41311$1729_Y + connect \$1544 $and$libresoc.v:41312$1730_Y + connect \$1547 $ternary$libresoc.v:41313$1731_Y + connect \$1549 $and$libresoc.v:41314$1732_Y + connect \$1552 $and$libresoc.v:41315$1733_Y + connect \$1555 $not$libresoc.v:41316$1734_Y + connect \$1557 $and$libresoc.v:41317$1735_Y + connect \$1560 $and$libresoc.v:41318$1736_Y + connect \$1563 $ternary$libresoc.v:41319$1737_Y + connect \$1565 $and$libresoc.v:41320$1738_Y + connect \$1568 $and$libresoc.v:41321$1739_Y + connect \$1571 $not$libresoc.v:41322$1740_Y + connect \$1573 $and$libresoc.v:41323$1741_Y + connect \$1576 $and$libresoc.v:41324$1742_Y + connect \$1579 $ternary$libresoc.v:41325$1743_Y + connect \$1582 $or$libresoc.v:41326$1744_Y + connect \$1584 $or$libresoc.v:41327$1745_Y + connect \$1586 $or$libresoc.v:41328$1746_Y + connect \$1581 $pos$libresoc.v:41329$1748_Y + connect \$1590 $or$libresoc.v:41330$1749_Y + connect \$1592 $or$libresoc.v:41331$1750_Y + connect \$1594 $or$libresoc.v:41332$1751_Y + connect \$1589 $pos$libresoc.v:41333$1753_Y + connect \$1597 $and$libresoc.v:41334$1754_Y + connect \$1599 $and$libresoc.v:41335$1755_Y + connect \$1601 $and$libresoc.v:41336$1756_Y + connect \$1603 $and$libresoc.v:41337$1757_Y + connect \$1605 $and$libresoc.v:41338$1758_Y + connect \$1607 $and$libresoc.v:41339$1759_Y + connect \$1610 $and$libresoc.v:41340$1760_Y + connect \$1614 $not$libresoc.v:41341$1761_Y + connect \$1616 $and$libresoc.v:41342$1762_Y + connect \$161 $and$libresoc.v:41343$1763_Y + connect \$1621 $and$libresoc.v:41344$1764_Y + connect \$1624 $ternary$libresoc.v:41345$1765_Y + connect \$1626 $and$libresoc.v:41346$1766_Y + connect \$160 $reduce_or$libresoc.v:41347$1767_Y + connect \$1629 $and$libresoc.v:41348$1768_Y + connect \$1632 $not$libresoc.v:41349$1769_Y + connect \$1634 $and$libresoc.v:41350$1770_Y + connect \$1637 $and$libresoc.v:41351$1771_Y + connect \$1640 $ternary$libresoc.v:41352$1772_Y + connect \$1642 $and$libresoc.v:41353$1773_Y + connect \$1645 $and$libresoc.v:41354$1774_Y + connect \$1648 $not$libresoc.v:41355$1775_Y + connect \$1650 $and$libresoc.v:41356$1776_Y + connect \$1653 $and$libresoc.v:41357$1777_Y + connect \$1656 $ternary$libresoc.v:41358$1778_Y + connect \$1658 $and$libresoc.v:41359$1779_Y + connect \$165 $and$libresoc.v:41360$1780_Y + connect \$1661 $and$libresoc.v:41361$1781_Y + connect \$1664 $not$libresoc.v:41362$1782_Y + connect \$1666 $and$libresoc.v:41363$1783_Y + connect \$164 $reduce_or$libresoc.v:41364$1784_Y + connect \$1669 $and$libresoc.v:41365$1785_Y + connect \$1672 $ternary$libresoc.v:41366$1786_Y + connect \$1674 $and$libresoc.v:41367$1787_Y + connect \$1677 $and$libresoc.v:41368$1788_Y + connect \$1680 $not$libresoc.v:41369$1789_Y + connect \$1682 $and$libresoc.v:41370$1790_Y + connect \$1685 $and$libresoc.v:41371$1791_Y + connect \$1688 $ternary$libresoc.v:41372$1792_Y + connect \$1690 $or$libresoc.v:41373$1793_Y + connect \$1692 $or$libresoc.v:41374$1794_Y + connect \$1694 $or$libresoc.v:41375$1795_Y + connect \$1696 $or$libresoc.v:41376$1796_Y + connect \$1698 $or$libresoc.v:41377$1797_Y + connect \$169 $and$libresoc.v:41378$1798_Y + connect \$1700 $or$libresoc.v:41379$1799_Y + connect \$1702 $or$libresoc.v:41380$1800_Y + connect \$1704 $or$libresoc.v:41381$1801_Y + connect \$1706 $or$libresoc.v:41382$1802_Y + connect \$1708 $or$libresoc.v:41383$1803_Y + connect \$168 $reduce_or$libresoc.v:41384$1804_Y + connect \$1710 $or$libresoc.v:41385$1805_Y + connect \$1712 $or$libresoc.v:41386$1806_Y + connect \$1714 $and$libresoc.v:41387$1807_Y + connect \$1716 $and$libresoc.v:41388$1808_Y + connect \$1718 $and$libresoc.v:41389$1809_Y + connect \$1721 $and$libresoc.v:41390$1810_Y + connect \$1724 $not$libresoc.v:41391$1811_Y + connect \$1726 $and$libresoc.v:41392$1812_Y + connect \$1729 $and$libresoc.v:41393$1813_Y + connect \$1732 $ternary$libresoc.v:41394$1814_Y + connect \$1734 $and$libresoc.v:41395$1815_Y + connect \$1737 $and$libresoc.v:41396$1816_Y + connect \$173 $and$libresoc.v:41397$1817_Y + connect \$1740 $not$libresoc.v:41398$1818_Y + connect \$1742 $and$libresoc.v:41399$1819_Y + connect \$1745 $and$libresoc.v:41400$1820_Y + connect \$1748 $ternary$libresoc.v:41401$1821_Y + connect \$172 $reduce_or$libresoc.v:41402$1822_Y + connect \$1750 $or$libresoc.v:41403$1823_Y + connect \$1753 $or$libresoc.v:41404$1824_Y + connect \$1752 $pos$libresoc.v:41405$1826_Y + connect \$1756 $and$libresoc.v:41406$1827_Y + connect \$1758 $and$libresoc.v:41407$1828_Y + connect \$1761 $and$libresoc.v:41408$1829_Y + connect \$1764 $not$libresoc.v:41409$1830_Y + connect \$1766 $and$libresoc.v:41410$1831_Y + connect \$1769 $and$libresoc.v:41411$1832_Y + connect \$1772 $ternary$libresoc.v:41412$1833_Y + connect \$1774 $pos$libresoc.v:41413$1835_Y + connect \$1776 $and$libresoc.v:41414$1836_Y + connect \$1778 $and$libresoc.v:41415$1837_Y + connect \$177 $and$libresoc.v:41416$1838_Y + connect \$1781 $and$libresoc.v:41417$1839_Y + connect \$1784 $not$libresoc.v:41418$1840_Y + connect \$1786 $and$libresoc.v:41419$1841_Y + connect \$176 $reduce_or$libresoc.v:41420$1842_Y + connect \$1789 $and$libresoc.v:41421$1843_Y + connect \$1792 $ternary$libresoc.v:41422$1844_Y + connect \$181 $and$libresoc.v:41423$1845_Y + connect \$180 $reduce_or$libresoc.v:41424$1846_Y + connect \$185 $and$libresoc.v:41425$1847_Y + connect \$184 $reduce_or$libresoc.v:41426$1848_Y + connect \$189 $and$libresoc.v:41427$1849_Y + connect \$188 $reduce_or$libresoc.v:41428$1850_Y + connect \$193 $and$libresoc.v:41429$1851_Y + connect \$192 $reduce_or$libresoc.v:41430$1852_Y + connect \$197 $and$libresoc.v:41431$1853_Y + connect \$196 $reduce_or$libresoc.v:41432$1854_Y + connect \$200 $ne$libresoc.v:41433$1855_Y + connect \$203 $sub$libresoc.v:41434$1856_Y + connect \$205 $ne$libresoc.v:41435$1857_Y + connect \$208 $and$libresoc.v:41436$1858_Y + connect \$210 $and$libresoc.v:41437$1859_Y + connect \$212 $eq$libresoc.v:41438$1860_Y + connect \$214 $or$libresoc.v:41439$1861_Y + connect \$216 $and$libresoc.v:41440$1862_Y + connect \$218 $or$libresoc.v:41441$1863_Y + connect \$220 $eq$libresoc.v:41442$1864_Y + connect \$222 $and$libresoc.v:41443$1865_Y + connect \$224 $eq$libresoc.v:41444$1866_Y + connect \$226 $or$libresoc.v:41445$1867_Y + connect \$207 $not$libresoc.v:41446$1868_Y + connect \$229 $not$libresoc.v:41447$1869_Y + connect \$231 $not$libresoc.v:41448$1870_Y + connect \$233 $not$libresoc.v:41449$1871_Y + connect \$236 $and$libresoc.v:41450$1872_Y + connect \$238 $and$libresoc.v:41451$1873_Y + connect \$240 $eq$libresoc.v:41452$1874_Y + connect \$242 $or$libresoc.v:41453$1875_Y + connect \$244 $and$libresoc.v:41454$1876_Y + connect \$246 $or$libresoc.v:41455$1877_Y + connect \$235 $not$libresoc.v:41456$1878_Y + connect \$250 $and$libresoc.v:41457$1879_Y + connect \$252 $and$libresoc.v:41458$1880_Y + connect \$254 $eq$libresoc.v:41459$1881_Y + connect \$256 $or$libresoc.v:41460$1882_Y + connect \$258 $and$libresoc.v:41461$1883_Y + connect \$260 $or$libresoc.v:41462$1884_Y + connect \$262 $and$libresoc.v:41463$1885_Y + connect \$264 $and$libresoc.v:41464$1886_Y + connect \$266 $eq$libresoc.v:41465$1887_Y + connect \$268 $or$libresoc.v:41466$1888_Y + connect \$270 $eq$libresoc.v:41467$1889_Y + connect \$272 $and$libresoc.v:41468$1890_Y + connect \$274 $eq$libresoc.v:41469$1891_Y + connect \$276 $or$libresoc.v:41470$1892_Y + connect \$249 $not$libresoc.v:41471$1893_Y + connect \$280 $and$libresoc.v:41472$1894_Y + connect \$282 $and$libresoc.v:41473$1895_Y + connect \$284 $eq$libresoc.v:41474$1896_Y + connect \$286 $or$libresoc.v:41475$1897_Y + connect \$288 $and$libresoc.v:41476$1898_Y + connect \$290 $or$libresoc.v:41477$1899_Y + connect \$279 $not$libresoc.v:41478$1900_Y + connect \$294 $and$libresoc.v:41479$1901_Y + connect \$296 $and$libresoc.v:41480$1902_Y + connect \$298 $eq$libresoc.v:41481$1903_Y + connect \$300 $or$libresoc.v:41482$1904_Y + connect \$302 $and$libresoc.v:41483$1905_Y + connect \$304 $or$libresoc.v:41484$1906_Y + connect \$293 $not$libresoc.v:41485$1907_Y + connect \$308 $and$libresoc.v:41486$1908_Y + connect \$310 $and$libresoc.v:41487$1909_Y + connect \$312 $eq$libresoc.v:41488$1910_Y + connect \$314 $or$libresoc.v:41489$1911_Y + connect \$316 $and$libresoc.v:41490$1912_Y + connect \$318 $or$libresoc.v:41491$1913_Y + connect \$320 $eq$libresoc.v:41492$1914_Y + connect \$322 $and$libresoc.v:41493$1915_Y + connect \$324 $eq$libresoc.v:41494$1916_Y + connect \$326 $or$libresoc.v:41495$1917_Y + connect \$307 $not$libresoc.v:41496$1918_Y + connect \$329 $not$libresoc.v:41497$1919_Y + connect \$331 $and$libresoc.v:41498$1920_Y + connect \$333 $and$libresoc.v:41499$1921_Y + connect \$335 $not$libresoc.v:41500$1922_Y + connect \$337 $and$libresoc.v:41501$1923_Y + connect \$339 $and$libresoc.v:41502$1924_Y + connect \$341 $ternary$libresoc.v:41503$1925_Y + connect \$343 $and$libresoc.v:41504$1926_Y + connect \$345 $and$libresoc.v:41505$1927_Y + connect \$347 $not$libresoc.v:41506$1928_Y + connect \$349 $and$libresoc.v:41507$1929_Y + connect \$351 $and$libresoc.v:41508$1930_Y + connect \$353 $ternary$libresoc.v:41509$1931_Y + connect \$355 $and$libresoc.v:41510$1932_Y + connect \$357 $and$libresoc.v:41511$1933_Y + connect \$359 $not$libresoc.v:41512$1934_Y + connect \$361 $and$libresoc.v:41513$1935_Y + connect \$363 $and$libresoc.v:41514$1936_Y + connect \$365 $ternary$libresoc.v:41515$1937_Y + connect \$367 $and$libresoc.v:41516$1938_Y + connect \$369 $and$libresoc.v:41517$1939_Y + connect \$371 $not$libresoc.v:41518$1940_Y + connect \$373 $and$libresoc.v:41519$1941_Y + connect \$375 $and$libresoc.v:41520$1942_Y + connect \$377 $ternary$libresoc.v:41521$1943_Y + connect \$379 $and$libresoc.v:41522$1944_Y + connect \$381 $and$libresoc.v:41523$1945_Y + connect \$383 $not$libresoc.v:41524$1946_Y + connect \$385 $and$libresoc.v:41525$1947_Y + connect \$387 $and$libresoc.v:41526$1948_Y + connect \$389 $ternary$libresoc.v:41527$1949_Y + connect \$391 $and$libresoc.v:41528$1950_Y + connect \$393 $and$libresoc.v:41529$1951_Y + connect \$395 $not$libresoc.v:41530$1952_Y + connect \$397 $and$libresoc.v:41531$1953_Y + connect \$399 $and$libresoc.v:41532$1954_Y + connect \$401 $ternary$libresoc.v:41533$1955_Y + connect \$403 $and$libresoc.v:41534$1956_Y + connect \$405 $and$libresoc.v:41535$1957_Y + connect \$407 $not$libresoc.v:41536$1958_Y + connect \$409 $and$libresoc.v:41537$1959_Y + connect \$411 $and$libresoc.v:41538$1960_Y + connect \$413 $ternary$libresoc.v:41539$1961_Y + connect \$415 $and$libresoc.v:41540$1962_Y + connect \$417 $and$libresoc.v:41541$1963_Y + connect \$419 $not$libresoc.v:41542$1964_Y + connect \$421 $and$libresoc.v:41543$1965_Y + connect \$423 $and$libresoc.v:41544$1966_Y + connect \$425 $ternary$libresoc.v:41545$1967_Y + connect \$427 $and$libresoc.v:41546$1968_Y + connect \$429 $and$libresoc.v:41547$1969_Y + connect \$431 $not$libresoc.v:41548$1970_Y + connect \$433 $and$libresoc.v:41549$1971_Y + connect \$435 $and$libresoc.v:41550$1972_Y + connect \$437 $ternary$libresoc.v:41551$1973_Y + connect \$439 $or$libresoc.v:41552$1974_Y + connect \$441 $or$libresoc.v:41553$1975_Y + connect \$443 $or$libresoc.v:41554$1976_Y + connect \$445 $or$libresoc.v:41555$1977_Y + connect \$447 $or$libresoc.v:41556$1978_Y + connect \$449 $or$libresoc.v:41557$1979_Y + connect \$451 $or$libresoc.v:41558$1980_Y + connect \$453 $or$libresoc.v:41559$1981_Y + connect \$455 $reduce_or$libresoc.v:41560$1982_Y + connect \$457 $and$libresoc.v:41561$1983_Y + connect \$459 $and$libresoc.v:41562$1984_Y + connect \$461 $not$libresoc.v:41563$1985_Y + connect \$463 $and$libresoc.v:41564$1986_Y + connect \$465 $and$libresoc.v:41565$1987_Y + connect \$467 $ternary$libresoc.v:41566$1988_Y + connect \$469 $and$libresoc.v:41567$1989_Y + connect \$471 $and$libresoc.v:41568$1990_Y + connect \$473 $not$libresoc.v:41569$1991_Y + connect \$475 $and$libresoc.v:41570$1992_Y + connect \$477 $and$libresoc.v:41571$1993_Y + connect \$479 $ternary$libresoc.v:41572$1994_Y + connect \$481 $and$libresoc.v:41573$1995_Y + connect \$483 $and$libresoc.v:41574$1996_Y + connect \$485 $not$libresoc.v:41575$1997_Y + connect \$487 $and$libresoc.v:41576$1998_Y + connect \$489 $and$libresoc.v:41577$1999_Y + connect \$491 $ternary$libresoc.v:41578$2000_Y + connect \$493 $and$libresoc.v:41579$2001_Y + connect \$495 $and$libresoc.v:41580$2002_Y + connect \$497 $not$libresoc.v:41581$2003_Y + connect \$499 $and$libresoc.v:41582$2004_Y + connect \$501 $and$libresoc.v:41583$2005_Y + connect \$503 $ternary$libresoc.v:41584$2006_Y + connect \$505 $and$libresoc.v:41585$2007_Y + connect \$507 $and$libresoc.v:41586$2008_Y + connect \$509 $not$libresoc.v:41587$2009_Y + connect \$511 $and$libresoc.v:41588$2010_Y + connect \$513 $and$libresoc.v:41589$2011_Y + connect \$515 $ternary$libresoc.v:41590$2012_Y + connect \$517 $and$libresoc.v:41591$2013_Y + connect \$519 $and$libresoc.v:41592$2014_Y + connect \$521 $not$libresoc.v:41593$2015_Y + connect \$523 $and$libresoc.v:41594$2016_Y + connect \$525 $and$libresoc.v:41595$2017_Y + connect \$527 $ternary$libresoc.v:41596$2018_Y + connect \$529 $and$libresoc.v:41597$2019_Y + connect \$531 $and$libresoc.v:41598$2020_Y + connect \$533 $not$libresoc.v:41599$2021_Y + connect \$535 $and$libresoc.v:41600$2022_Y + connect \$537 $and$libresoc.v:41601$2023_Y + connect \$539 $ternary$libresoc.v:41602$2024_Y + connect \$541 $and$libresoc.v:41603$2025_Y + connect \$543 $and$libresoc.v:41604$2026_Y + connect \$545 $not$libresoc.v:41605$2027_Y + connect \$547 $and$libresoc.v:41606$2028_Y + connect \$549 $and$libresoc.v:41607$2029_Y + connect \$551 $ternary$libresoc.v:41608$2030_Y + connect \$553 $or$libresoc.v:41609$2031_Y + connect \$555 $or$libresoc.v:41610$2032_Y + connect \$557 $or$libresoc.v:41611$2033_Y + connect \$559 $or$libresoc.v:41612$2034_Y + connect \$561 $or$libresoc.v:41613$2035_Y + connect \$563 $or$libresoc.v:41614$2036_Y + connect \$565 $or$libresoc.v:41615$2037_Y + connect \$567 $reduce_or$libresoc.v:41616$2038_Y + connect \$569 $and$libresoc.v:41617$2039_Y + connect \$571 $and$libresoc.v:41618$2040_Y + connect \$573 $not$libresoc.v:41619$2041_Y + connect \$575 $and$libresoc.v:41620$2042_Y + connect \$577 $and$libresoc.v:41621$2043_Y + connect \$579 $ternary$libresoc.v:41622$2044_Y + connect \$581 $and$libresoc.v:41623$2045_Y + connect \$583 $and$libresoc.v:41624$2046_Y + connect \$585 $not$libresoc.v:41625$2047_Y + connect \$587 $and$libresoc.v:41626$2048_Y + connect \$589 $and$libresoc.v:41627$2049_Y + connect \$591 $ternary$libresoc.v:41628$2050_Y + connect \$593 $or$libresoc.v:41629$2051_Y + connect \$595 $reduce_or$libresoc.v:41630$2052_Y + connect \$597 $and$libresoc.v:41631$2053_Y + connect \$599 $and$libresoc.v:41632$2054_Y + connect \$601 $eq$libresoc.v:41633$2055_Y + connect \$603 $or$libresoc.v:41634$2056_Y + connect \$605 $and$libresoc.v:41635$2057_Y + connect \$607 $or$libresoc.v:41636$2058_Y + connect \$609 $and$libresoc.v:41637$2059_Y + connect \$611 $and$libresoc.v:41638$2060_Y + connect \$613 $not$libresoc.v:41639$2061_Y + connect \$615 $and$libresoc.v:41640$2062_Y + connect \$617 $and$libresoc.v:41641$2063_Y + connect \$619 $ternary$libresoc.v:41642$2064_Y + connect \$621 $and$libresoc.v:41643$2065_Y + connect \$623 $and$libresoc.v:41644$2066_Y + connect \$625 $not$libresoc.v:41645$2067_Y + connect \$627 $and$libresoc.v:41646$2068_Y + connect \$629 $and$libresoc.v:41647$2069_Y + connect \$631 $ternary$libresoc.v:41648$2070_Y + connect \$633 $and$libresoc.v:41649$2071_Y + connect \$635 $and$libresoc.v:41650$2072_Y + connect \$637 $not$libresoc.v:41651$2073_Y + connect \$639 $and$libresoc.v:41652$2074_Y + connect \$641 $and$libresoc.v:41653$2075_Y + connect \$643 $ternary$libresoc.v:41654$2076_Y + connect \$645 $and$libresoc.v:41655$2077_Y + connect \$647 $and$libresoc.v:41656$2078_Y + connect \$649 $not$libresoc.v:41657$2079_Y + connect \$651 $and$libresoc.v:41658$2080_Y + connect \$653 $and$libresoc.v:41659$2081_Y + connect \$655 $ternary$libresoc.v:41660$2082_Y + connect \$657 $and$libresoc.v:41661$2083_Y + connect \$659 $and$libresoc.v:41662$2084_Y + connect \$661 $not$libresoc.v:41663$2085_Y + connect \$663 $and$libresoc.v:41664$2086_Y + connect \$665 $and$libresoc.v:41665$2087_Y + connect \$667 $ternary$libresoc.v:41666$2088_Y + connect \$669 $and$libresoc.v:41667$2089_Y + connect \$671 $and$libresoc.v:41668$2090_Y + connect \$673 $not$libresoc.v:41669$2091_Y + connect \$675 $and$libresoc.v:41670$2092_Y + connect \$677 $and$libresoc.v:41671$2093_Y + connect \$679 $ternary$libresoc.v:41672$2094_Y + connect \$682 $or$libresoc.v:41673$2095_Y + connect \$684 $or$libresoc.v:41674$2096_Y + connect \$686 $or$libresoc.v:41675$2097_Y + connect \$688 $or$libresoc.v:41676$2098_Y + connect \$690 $or$libresoc.v:41677$2099_Y + connect \$681 $pos$libresoc.v:41678$2101_Y + connect \$693 $eq$libresoc.v:41679$2102_Y + connect \$695 $and$libresoc.v:41680$2103_Y + connect \$697 $eq$libresoc.v:41681$2104_Y + connect \$699 $or$libresoc.v:41682$2105_Y + connect \$701 $and$libresoc.v:41683$2106_Y + connect \$703 $and$libresoc.v:41684$2107_Y + connect \$705 $not$libresoc.v:41685$2108_Y + connect \$707 $and$libresoc.v:41686$2109_Y + connect \$709 $and$libresoc.v:41687$2110_Y + connect \$711 $ternary$libresoc.v:41688$2111_Y + connect \$713 $and$libresoc.v:41689$2112_Y + connect \$715 $and$libresoc.v:41690$2113_Y + connect \$717 $not$libresoc.v:41691$2114_Y + connect \$719 $and$libresoc.v:41692$2115_Y + connect \$721 $and$libresoc.v:41693$2116_Y + connect \$723 $ternary$libresoc.v:41694$2117_Y + connect \$725 $and$libresoc.v:41695$2118_Y + connect \$727 $and$libresoc.v:41696$2119_Y + connect \$729 $not$libresoc.v:41697$2120_Y + connect \$731 $and$libresoc.v:41698$2121_Y + connect \$733 $and$libresoc.v:41699$2122_Y + connect \$735 $ternary$libresoc.v:41700$2123_Y + connect \$738 $or$libresoc.v:41701$2124_Y + connect \$740 $or$libresoc.v:41702$2125_Y + connect \$737 $pos$libresoc.v:41703$2127_Y + connect \$743 $and$libresoc.v:41704$2128_Y + connect \$745 $and$libresoc.v:41705$2129_Y + connect \$747 $eq$libresoc.v:41706$2130_Y + connect \$749 $or$libresoc.v:41707$2131_Y + connect \$751 $and$libresoc.v:41708$2132_Y + connect \$753 $and$libresoc.v:41709$2133_Y + connect \$755 $not$libresoc.v:41710$2134_Y + connect \$757 $and$libresoc.v:41711$2135_Y + connect \$759 $and$libresoc.v:41712$2136_Y + connect \$761 $ternary$libresoc.v:41713$2137_Y + connect \$763 $and$libresoc.v:41714$2138_Y + connect \$765 $and$libresoc.v:41715$2139_Y + connect \$767 $not$libresoc.v:41716$2140_Y + connect \$769 $and$libresoc.v:41717$2141_Y + connect \$771 $and$libresoc.v:41718$2142_Y + connect \$773 $ternary$libresoc.v:41719$2143_Y + connect \$775 $and$libresoc.v:41720$2144_Y + connect \$777 $and$libresoc.v:41721$2145_Y + connect \$779 $not$libresoc.v:41722$2146_Y + connect \$781 $and$libresoc.v:41723$2147_Y + connect \$783 $and$libresoc.v:41724$2148_Y + connect \$785 $sub$libresoc.v:41725$2149_Y + connect \$787 $sshl$libresoc.v:41726$2150_Y + connect \$789 $ternary$libresoc.v:41727$2151_Y + connect \$791 $and$libresoc.v:41728$2152_Y + connect \$793 $and$libresoc.v:41729$2153_Y + connect \$795 $not$libresoc.v:41730$2154_Y + connect \$797 $and$libresoc.v:41731$2155_Y + connect \$799 $and$libresoc.v:41732$2156_Y + connect \$801 $sub$libresoc.v:41733$2157_Y + connect \$803 $sshl$libresoc.v:41734$2158_Y + connect \$805 $ternary$libresoc.v:41735$2159_Y + connect \$808 $or$libresoc.v:41736$2160_Y + connect \$810 $and$libresoc.v:41737$2161_Y + connect \$812 $and$libresoc.v:41738$2162_Y + connect \$814 $not$libresoc.v:41739$2163_Y + connect \$816 $and$libresoc.v:41740$2164_Y + connect \$818 $and$libresoc.v:41741$2165_Y + connect \$820 $sub$libresoc.v:41742$2166_Y + connect \$822 $sshl$libresoc.v:41743$2167_Y + connect \$824 $ternary$libresoc.v:41744$2168_Y + connect \$826 $and$libresoc.v:41745$2169_Y + connect \$828 $and$libresoc.v:41746$2170_Y + connect \$830 $not$libresoc.v:41747$2171_Y + connect \$832 $and$libresoc.v:41748$2172_Y + connect \$834 $and$libresoc.v:41749$2173_Y + connect \$836 $sub$libresoc.v:41750$2174_Y + connect \$838 $sshl$libresoc.v:41751$2175_Y + connect \$840 $ternary$libresoc.v:41752$2176_Y + connect \$842 $and$libresoc.v:41753$2177_Y + connect \$844 $and$libresoc.v:41754$2178_Y + connect \$846 $not$libresoc.v:41755$2179_Y + connect \$848 $and$libresoc.v:41756$2180_Y + connect \$850 $and$libresoc.v:41757$2181_Y + connect \$852 $ternary$libresoc.v:41758$2182_Y + connect \$854 $and$libresoc.v:41759$2183_Y + connect \$856 $and$libresoc.v:41760$2184_Y + connect \$858 $not$libresoc.v:41761$2185_Y + connect \$860 $and$libresoc.v:41762$2186_Y + connect \$862 $and$libresoc.v:41763$2187_Y + connect \$864 $ternary$libresoc.v:41764$2188_Y + connect \$866 $and$libresoc.v:41765$2189_Y + connect \$868 $and$libresoc.v:41766$2190_Y + connect \$870 $not$libresoc.v:41767$2191_Y + connect \$872 $and$libresoc.v:41768$2192_Y + connect \$874 $and$libresoc.v:41769$2193_Y + connect \$876 $ternary$libresoc.v:41770$2194_Y + connect \$878 $or$libresoc.v:41771$2195_Y + connect \$880 $or$libresoc.v:41772$2196_Y + connect \$882 $reduce_or$libresoc.v:41773$2197_Y + connect \$884 $and$libresoc.v:41774$2198_Y + connect \$886 $and$libresoc.v:41775$2199_Y + connect \$888 $not$libresoc.v:41776$2200_Y + connect \$890 $and$libresoc.v:41777$2201_Y + connect \$892 $and$libresoc.v:41778$2202_Y + connect \$894 $ternary$libresoc.v:41779$2203_Y + connect \$896 $and$libresoc.v:41780$2204_Y + connect \$898 $and$libresoc.v:41781$2205_Y + connect \$900 $not$libresoc.v:41782$2206_Y + connect \$902 $and$libresoc.v:41783$2207_Y + connect \$904 $and$libresoc.v:41784$2208_Y + connect \$906 $ternary$libresoc.v:41785$2209_Y + connect \$908 $or$libresoc.v:41786$2210_Y + connect \$910 $reduce_or$libresoc.v:41787$2211_Y + connect \$912 $and$libresoc.v:41788$2212_Y + connect \$914 $and$libresoc.v:41789$2213_Y + connect \$916 $not$libresoc.v:41790$2214_Y + connect \$918 $and$libresoc.v:41791$2215_Y + connect \$920 $and$libresoc.v:41792$2216_Y + connect \$922 $ternary$libresoc.v:41793$2217_Y + connect \$924 $reduce_or$libresoc.v:41794$2218_Y + connect \$926 $and$libresoc.v:41795$2219_Y + connect \$928 $and$libresoc.v:41796$2220_Y + connect \$930 $and$libresoc.v:41797$2221_Y + connect \$932 $and$libresoc.v:41798$2222_Y + connect \$934 $and$libresoc.v:41799$2223_Y + connect \$936 $and$libresoc.v:41800$2224_Y + connect \$938 $and$libresoc.v:41801$2225_Y + connect \$940 $and$libresoc.v:41802$2226_Y + connect \$942 $and$libresoc.v:41803$2227_Y + connect \$944 $and$libresoc.v:41804$2228_Y + connect \$946 $and$libresoc.v:41805$2229_Y + connect \$948 $and$libresoc.v:41806$2230_Y + connect \$950 $not$libresoc.v:41807$2231_Y + connect \$952 $and$libresoc.v:41808$2232_Y + connect \$958 $and$libresoc.v:41809$2233_Y + connect \$960 $ternary$libresoc.v:41810$2234_Y + connect \$962 $and$libresoc.v:41811$2235_Y + connect \$965 $and$libresoc.v:41812$2236_Y + connect \$969 $not$libresoc.v:41813$2237_Y + connect \$971 $and$libresoc.v:41814$2238_Y + connect \$976 $and$libresoc.v:41815$2239_Y + connect \$979 $ternary$libresoc.v:41816$2240_Y + connect \$981 $and$libresoc.v:41817$2241_Y + connect \$984 $and$libresoc.v:41818$2242_Y + connect \$988 $not$libresoc.v:41819$2243_Y + connect \$990 $and$libresoc.v:41820$2244_Y + connect \$997 $and$libresoc.v:41821$2245_Y + connect \$202 \$203 + connect \$807 \$808 + connect \$1135 \$1152 + connect \$1350 \$1359 + connect \o_ok 1'0 + connect \ea_ok 1'0 + connect \coresync_rst \core_reset_i + connect \spr_spr1__wen \wp$1788 + connect \spr_spr1__addr$159 \addr_en$1791 [6:0] + connect \spr_spr1__data_i \fus_dest2_o$153 + connect \addr_en$1791 \$1792 + connect \wp$1788 \$1789 + connect \wr_pick_rise$1035 \$1786 + connect \wr_pick$1780 \$1781 + connect \wrpick_SPR_spr1_i \$1778 + connect \wrflag_spr0_spr1_1 \$1776 + connect \state_wen \$1774 + connect \state_data_i$158 \fus_dest5_o$152 + connect \addr_en$1771 \$1772 + connect \wp$1768 \$1769 + connect \wr_pick_rise$995 \$1766 + connect \wr_pick$1760 \$1761 + connect \wrpick_STATE_msr_i \$1758 + connect \wrflag_trap0_msr_4 \$1756 + connect \state_nia_wen \$1752 + connect \state_data_i \$1750 + connect \addr_en$1747 \$1748 + connect \wp$1744 \$1745 + connect \wr_pick_rise$994 \$1742 + connect \wr_pick$1736 \$1737 + connect \wrflag_trap0_nia_3 \$1734 + connect \addr_en$1731 \$1732 + connect \wp$1728 \$1729 + connect \wr_pick_rise$1619 \$1726 + connect \wr_pick$1720 \$1721 + connect \wrpick_STATE_nia_i [1] \$1718 + connect \wrpick_STATE_nia_i [0] \$1716 + connect \wrflag_branch0_nia_2 \$1714 + connect \fast_dest1__wen \$1712 + connect \fast_dest1__addr \$1704 + connect \fast_dest1__data_i \$1696 + connect \addr_en$1687 \$1688 + connect \wp$1684 \$1685 + connect \wr_pick_rise$993 \$1682 + connect \wr_pick$1676 \$1677 + connect \wrflag_trap0_fast1_2 \$1674 + connect \addr_en$1671 \$1672 + connect \wp$1668 \$1669 + connect \wr_pick_rise$1618 \$1666 + connect \wr_pick$1660 \$1661 + connect \wrflag_branch0_fast1_1 \$1658 + connect \addr_en$1655 \$1656 + connect \wp$1652 \$1653 + connect \wr_pick_rise$1034 \$1650 + connect \wr_pick$1644 \$1645 + connect \wrflag_spr0_fast1_2 \$1642 + connect \addr_en$1639 \$1640 + connect \wp$1636 \$1637 + connect \wr_pick_rise$992 \$1634 + connect \wr_pick$1628 \$1629 + connect \wrflag_trap0_fast1_1 \$1626 + connect \addr_en$1623 \$1624 + connect \wp$1620 \$1621 + connect \fus_cu_wr__go_i$140 [2] \wr_pick_rise$1619 + connect \fus_cu_wr__go_i$140 [1] \wr_pick_rise$1618 + connect \fus_cu_wr__go_i$140 [0] \wr_pick_rise$1613 + connect \wr_pick_rise$1613 \$1616 + connect \wr_pick$1609 \$1610 + connect \wrpick_FAST_fast1_i [4] \$1607 + connect \wrpick_FAST_fast1_i [3] \$1605 + connect \wrpick_FAST_fast1_i [2] \$1603 + connect \wrpick_FAST_fast1_i [1] \$1601 + connect \wrpick_FAST_fast1_i [0] \$1599 + connect \wrflag_branch0_fast1_0 \$1597 + connect \xer_wen$157 \$1589 + connect \xer_data_i$156 \$1581 + connect \addr_en$1578 \$1579 + connect \wp$1575 \$1576 + connect \wr_pick_rise$1075 \$1573 + connect \wr_pick$1567 \$1568 + connect \wrflag_mul0_xer_so_3 \$1565 + connect \addr_en$1562 \$1563 + connect \wp$1559 \$1560 + connect \wr_pick_rise$1055 \$1557 + connect \wr_pick$1551 \$1552 + connect \wrflag_div0_xer_so_3 \$1549 + connect \addr_en$1546 \$1547 + connect \wp$1543 \$1544 + connect \wr_pick_rise$1033 \$1541 + connect \wr_pick$1535 \$1536 + connect \wrflag_spr0_xer_so_3 \$1533 + connect \addr_en$1530 \$1531 + connect \wp$1527 \$1528 + connect \wr_pick_rise$957 \$1525 + connect \wr_pick$1519 \$1520 + connect \wrpick_XER_xer_so_i [3] \$1517 + connect \wrpick_XER_xer_so_i [2] \$1515 + connect \wrpick_XER_xer_so_i [1] \$1513 + connect \wrpick_XER_xer_so_i [0] \$1511 + connect \wrflag_alu0_xer_so_4 \$1509 + connect \xer_wen$155 \$1507 + connect \xer_data_i$154 \$1501 + connect \addr_en$1494 \$1495 + connect \wp$1491 \$1492 + connect \wr_pick_rise$1074 \$1489 + connect \wr_pick$1483 \$1484 + connect \wrflag_mul0_xer_ov_2 \$1481 + connect \addr_en$1478 \$1479 + connect \wp$1475 \$1476 + connect \wr_pick_rise$1054 \$1473 + connect \wr_pick$1467 \$1468 + connect \wrflag_div0_xer_ov_2 \$1465 + connect \addr_en$1462 \$1463 + connect \wp$1459 \$1460 + connect \wr_pick_rise$1032 \$1457 + connect \wr_pick$1451 \$1452 + connect \wrflag_spr0_xer_ov_4 \$1449 + connect \addr_en$1446 \$1447 + connect \wp$1443 \$1444 + connect \wr_pick_rise$956 \$1441 + connect \wr_pick$1435 \$1436 + connect \wrpick_XER_xer_ov_i [3] \$1433 + connect \wrpick_XER_xer_ov_i [2] \$1431 + connect \wrpick_XER_xer_ov_i [1] \$1429 + connect \wrpick_XER_xer_ov_i [0] \$1427 + connect \wrflag_alu0_xer_ov_3 \$1425 + connect \xer_wen \$1419 + connect \xer_data_i \$1417 + connect \addr_en$1412 \$1413 + connect \wp$1409 \$1410 + connect \wr_pick_rise$1094 \$1407 + connect \wr_pick$1401 \$1402 + connect \wrflag_shiftrot0_xer_ca_2 \$1399 + connect \addr_en$1396 \$1397 + connect \wp$1393 \$1394 + connect \wr_pick_rise$1031 \$1391 + connect \wr_pick$1385 \$1386 + connect \wrflag_spr0_xer_ca_5 \$1383 + connect \addr_en$1380 \$1381 + connect \wp$1377 \$1378 + connect \wr_pick_rise$955 \$1375 + connect \wr_pick$1369 \$1370 + connect \wrpick_XER_xer_ca_i [2] \$1367 + connect \wrpick_XER_xer_ca_i [1] \$1365 + connect \wrpick_XER_xer_ca_i [0] \$1363 + connect \wrflag_alu0_xer_ca_2 \$1361 + connect \cr_wen \$1359 [7:0] + connect \cr_data_i \$1348 + connect \addr_en$1333 \$1338 + connect \wp$1330 \$1331 + connect \wr_pick_rise$1093 \$1328 + connect \wr_pick$1322 \$1323 + connect \wrflag_shiftrot0_cr_a_1 \$1320 + connect \addr_en$1313 \$1318 + connect \wp$1310 \$1311 + connect \wr_pick_rise$1073 \$1308 + connect \wr_pick$1302 \$1303 + connect \wrflag_mul0_cr_a_1 \$1300 + connect \addr_en$1293 \$1298 + connect \wp$1290 \$1291 + connect \wr_pick_rise$1053 \$1288 + connect \wr_pick$1282 \$1283 + connect \wrflag_div0_cr_a_1 \$1280 + connect \addr_en$1273 \$1278 + connect \wp$1270 \$1271 + connect \wr_pick_rise$1013 \$1268 + connect \wr_pick$1262 \$1263 + connect \wrflag_logical0_cr_a_1 \$1260 + connect \addr_en$1253 \$1258 + connect \wp$1250 \$1251 + connect \wr_pick_rise$974 \$1248 + connect \wr_pick$1242 \$1243 + connect \wrflag_cr0_cr_a_2 \$1240 + connect \addr_en$1233 \$1238 + connect \wp$1230 \$1231 + connect \wr_pick_rise$954 \$1228 + connect \wr_pick$1222 \$1223 + connect \wrpick_CR_cr_a_i [5] \$1220 + connect \wrpick_CR_cr_a_i [4] \$1218 + connect \wrpick_CR_cr_a_i [3] \$1216 + connect \wrpick_CR_cr_a_i [2] \$1214 + connect \wrpick_CR_cr_a_i [1] \$1212 + connect \wrpick_CR_cr_a_i [0] \$1210 + connect \wrflag_alu0_cr_a_1 \$1208 + connect \cr_full_wr__wen \addr_en$1205 + connect \cr_full_wr__data_i \fus_dest2_o + connect \addr_en$1205 \$1206 + connect \wp$1202 \$1203 + connect \wr_pick_rise$973 \$1200 + connect \wr_pick$1194 \$1195 + connect \wrpick_CR_full_cr_i \$1192 + connect \wrflag_cr0_full_cr_1 \$1190 + connect \int_dest1__wen \$1188 + connect \int_dest1__addr \$1170 + connect \int_dest1__data_i \$1152 [63:0] + connect \addr_en$1132 \$1133 + connect \wp$1129 \$1130 + connect \wr_pick_rise$1112 \$1127 + connect \wr_pick$1121 \$1122 + connect \wrflag_ldst0_o_1 \$1119 + connect \addr_en$1116 \$1117 + connect \wp$1113 \$1114 + connect \fus_cu_wr__go_i$105 [1] \wr_pick_rise$1112 + connect \fus_cu_wr__go_i$105 [0] \wr_pick_rise$1107 + connect \wr_pick_rise$1107 \$1110 + connect \wr_pick$1103 \$1104 + connect \wrflag_ldst0_o_0 \$1101 + connect \addr_en$1098 \$1099 + connect \wp$1095 \$1096 + connect \fus_cu_wr__go_i$103 [2] \wr_pick_rise$1094 + connect \fus_cu_wr__go_i$103 [1] \wr_pick_rise$1093 + connect \fus_cu_wr__go_i$103 [0] \wr_pick_rise$1088 + connect \wr_pick_rise$1088 \$1091 + connect \wr_pick$1084 \$1085 + connect \wrflag_shiftrot0_o_0 \$1082 + connect \addr_en$1079 \$1080 + connect \wp$1076 \$1077 + connect \fus_cu_wr__go_i$100 [3] \wr_pick_rise$1075 + connect \fus_cu_wr__go_i$100 [2] \wr_pick_rise$1074 + connect \fus_cu_wr__go_i$100 [1] \wr_pick_rise$1073 + connect \fus_cu_wr__go_i$100 [0] \wr_pick_rise$1068 + connect \wr_pick_rise$1068 \$1071 + connect \wr_pick$1064 \$1065 + connect \wrflag_mul0_o_0 \$1062 + connect \addr_en$1059 \$1060 + connect \wp$1056 \$1057 + connect \fus_cu_wr__go_i$97 [3] \wr_pick_rise$1055 + connect \fus_cu_wr__go_i$97 [2] \wr_pick_rise$1054 + connect \fus_cu_wr__go_i$97 [1] \wr_pick_rise$1053 + connect \fus_cu_wr__go_i$97 [0] \wr_pick_rise$1048 + connect \wr_pick_rise$1048 \$1051 + connect \wr_pick$1044 \$1045 + connect \wrflag_div0_o_0 \$1042 + connect \addr_en$1039 \$1040 + connect \wp$1036 \$1037 + connect \fus_cu_wr__go_i$94 [1] \wr_pick_rise$1035 + connect \fus_cu_wr__go_i$94 [2] \wr_pick_rise$1034 + connect \fus_cu_wr__go_i$94 [3] \wr_pick_rise$1033 + connect \fus_cu_wr__go_i$94 [4] \wr_pick_rise$1032 + connect \fus_cu_wr__go_i$94 [5] \wr_pick_rise$1031 + connect \fus_cu_wr__go_i$94 [0] \wr_pick_rise$1026 + connect \wr_pick_rise$1026 \$1029 + connect \wr_pick$1022 \$1023 + connect \wrflag_spr0_o_0 \$1020 + connect \addr_en$1017 \$1018 + connect \wp$1014 \$1015 + connect \fus_cu_wr__go_i$91 [1] \wr_pick_rise$1013 + connect \fus_cu_wr__go_i$91 [0] \wr_pick_rise$1008 + connect \wr_pick_rise$1008 \$1011 + connect \wr_pick$1004 \$1005 + connect \wrflag_logical0_o_0 \$1002 + connect \addr_en$999 \$1000 + connect \wp$996 \$997 + connect \fus_cu_wr__go_i$88 [4] \wr_pick_rise$995 + connect \fus_cu_wr__go_i$88 [3] \wr_pick_rise$994 + connect \fus_cu_wr__go_i$88 [2] \wr_pick_rise$993 + connect \fus_cu_wr__go_i$88 [1] \wr_pick_rise$992 + connect \fus_cu_wr__go_i$88 [0] \wr_pick_rise$987 + connect \wr_pick_rise$987 \$990 + connect \wr_pick$983 \$984 + connect \wrflag_trap0_o_0 \$981 + connect \addr_en$978 \$979 + connect \wp$975 \$976 + connect \fus_cu_wr__go_i$85 [2] \wr_pick_rise$974 + connect \fus_cu_wr__go_i$85 [1] \wr_pick_rise$973 + connect \fus_cu_wr__go_i$85 [0] \wr_pick_rise$968 + connect \wr_pick_rise$968 \$971 + connect \wr_pick$964 \$965 + connect \wrflag_cr0_o_0 \$962 + connect \addr_en \$960 + connect \wp \$958 + connect \fus_cu_wr__go_i [4] \wr_pick_rise$957 + connect \fus_cu_wr__go_i [3] \wr_pick_rise$956 + connect \fus_cu_wr__go_i [2] \wr_pick_rise$955 + connect \fus_cu_wr__go_i [1] \wr_pick_rise$954 + connect \fus_cu_wr__go_i [0] \wr_pick_rise + connect \wr_pick_rise \$952 + connect \wr_pick \$948 + connect \wrpick_INT_o_i [9] \$946 + connect \wrpick_INT_o_i [8] \$944 + connect \wrpick_INT_o_i [7] \$942 + connect \wrpick_INT_o_i [6] \$940 + connect \wrpick_INT_o_i [5] \$938 + connect \wrpick_INT_o_i [4] \$936 + connect \wrpick_INT_o_i [3] \$934 + connect \wrpick_INT_o_i [2] \$932 + connect \wrpick_INT_o_i [1] \$930 + connect \wrpick_INT_o_i [0] \$928 + connect \wrflag_alu0_o_0 \$926 + connect \spr_spr1__ren \$924 + connect \spr_spr1__addr \addr_en_SPR_spr1_spr0_0 [6:0] + connect \addr_en_SPR_spr1_spr0_0 \$922 + connect \rp_SPR_spr1_spr0_0 \$920 + connect \rdpick_SPR_spr1_i \pick_SPR_spr1_spr0_0 + connect \pick_SPR_spr1_spr0_0 \$918 + connect \rdflag_SPR_spr1_0 \core_spr1_ok + connect \fast_src2__ren \$910 + connect \fast_src2__addr \$908 + connect \addr_en_FAST_fast2_trap0_1 \$906 + connect \rp_FAST_fast2_trap0_1 \$904 + connect \pick_FAST_fast2_trap0_1 \$902 + connect \addr_en_FAST_fast2_branch0_0 \$894 + connect \rp_FAST_fast2_branch0_0 \$892 + connect \rdpick_FAST_fast2_i [1] \pick_FAST_fast2_trap0_1 + connect \rdpick_FAST_fast2_i [0] \pick_FAST_fast2_branch0_0 + connect \pick_FAST_fast2_branch0_0 \$890 + connect \rdflag_FAST_fast2_0 \core_fast2_ok + connect \fast_src1__ren \$882 + connect \fast_src1__addr \$880 + connect \addr_en_FAST_fast1_spr0_2 \$876 + connect \rp_FAST_fast1_spr0_2 \$874 + connect \pick_FAST_fast1_spr0_2 \$872 + connect \addr_en_FAST_fast1_trap0_1 \$864 + connect \rp_FAST_fast1_trap0_1 \$862 + connect \pick_FAST_fast1_trap0_1 \$860 + connect \addr_en_FAST_fast1_branch0_0 \$852 + connect \rp_FAST_fast1_branch0_0 \$850 + connect \rdpick_FAST_fast1_i [2] \pick_FAST_fast1_spr0_2 + connect \rdpick_FAST_fast1_i [1] \pick_FAST_fast1_trap0_1 + connect \rdpick_FAST_fast1_i [0] \pick_FAST_fast1_branch0_0 + connect \pick_FAST_fast1_branch0_0 \$848 + connect \rdflag_FAST_fast1_0 \core_fast1_ok + connect \cr_src3__ren \addr_en_CR_cr_c_cr0_0 [7:0] + connect \addr_en_CR_cr_c_cr0_0 \$840 + connect \rp_CR_cr_c_cr0_0 \$834 + connect \rdpick_CR_cr_c_i \pick_CR_cr_c_cr0_0 + connect \pick_CR_cr_c_cr0_0 \$832 + connect \rdflag_CR_cr_c_0 \core_cr_in2_ok$2 + connect \cr_src2__ren \addr_en_CR_cr_b_cr0_0 [7:0] + connect \addr_en_CR_cr_b_cr0_0 \$824 + connect \rp_CR_cr_b_cr0_0 \$818 + connect \rdpick_CR_cr_b_i \pick_CR_cr_b_cr0_0 + connect \pick_CR_cr_b_cr0_0 \$816 + connect \rdflag_CR_cr_b_0 \core_cr_in2_ok + connect \cr_src1__ren \$808 [7:0] + connect \addr_en_CR_cr_a_branch0_1 \$805 + connect \rp_CR_cr_a_branch0_1 \$799 + connect \fus_cu_rd__go_i$73 [1] \dp_FAST_fast2_branch0_0 + connect \fus_cu_rd__go_i$73 [0] \dp_FAST_fast1_branch0_0 + connect \fus_cu_rd__go_i$73 [2] \dp_CR_cr_a_branch0_1 + connect \pick_CR_cr_a_branch0_1 \$797 + connect \addr_en_CR_cr_a_cr0_0 \$789 + connect \rp_CR_cr_a_cr0_0 \$783 + connect \rdpick_CR_cr_a_i [1] \pick_CR_cr_a_branch0_1 + connect \rdpick_CR_cr_a_i [0] \pick_CR_cr_a_cr0_0 + connect \pick_CR_cr_a_cr0_0 \$781 + connect \rdflag_CR_cr_a_0 \core_cr_in1_ok + connect \cr_full_rd__ren \addr_en_CR_full_cr_cr0_0 + connect \addr_en_CR_full_cr_cr0_0 \$773 + connect \rp_CR_full_cr_cr0_0 \$771 + connect \rdpick_CR_full_cr_i \pick_CR_full_cr_cr0_0 + connect \pick_CR_full_cr_cr0_0 \$769 + connect \rdflag_CR_full_cr_0 \core_core_cr_rd_ok + connect \xer_src3__ren \addr_en_XER_xer_ov_spr0_0 + connect \addr_en_XER_xer_ov_spr0_0 \$761 + connect \rp_XER_xer_ov_spr0_0 \$759 + connect \rdpick_XER_xer_ov_i \pick_XER_xer_ov_spr0_0 + connect \pick_XER_xer_ov_spr0_0 \$757 + connect \rdflag_XER_xer_ov_0 \$749 + connect \xer_src2__ren \$737 + connect \addr_en_XER_xer_ca_shiftrot0_2 \$735 + connect \rp_XER_xer_ca_shiftrot0_2 \$733 + connect \pick_XER_xer_ca_shiftrot0_2 \$731 + connect \addr_en_XER_xer_ca_spr0_1 \$723 + connect \rp_XER_xer_ca_spr0_1 \$721 + connect \pick_XER_xer_ca_spr0_1 \$719 + connect \addr_en_XER_xer_ca_alu0_0 \$711 + connect \rp_XER_xer_ca_alu0_0 \$709 + connect \rdpick_XER_xer_ca_i [2] \pick_XER_xer_ca_shiftrot0_2 + connect \rdpick_XER_xer_ca_i [1] \pick_XER_xer_ca_spr0_1 + connect \rdpick_XER_xer_ca_i [0] \pick_XER_xer_ca_alu0_0 + connect \pick_XER_xer_ca_alu0_0 \$707 + connect \rdflag_XER_xer_ca_0 \$699 + connect \xer_src1__ren \$681 + connect \addr_en_XER_xer_so_shiftrot0_5 \$679 + connect \rp_XER_xer_so_shiftrot0_5 \$677 + connect \pick_XER_xer_so_shiftrot0_5 \$675 + connect \addr_en_XER_xer_so_mul0_4 \$667 + connect \rp_XER_xer_so_mul0_4 \$665 + connect \pick_XER_xer_so_mul0_4 \$663 + connect \addr_en_XER_xer_so_div0_3 \$655 + connect \rp_XER_xer_so_div0_3 \$653 + connect \pick_XER_xer_so_div0_3 \$651 + connect \addr_en_XER_xer_so_spr0_2 \$643 + connect \rp_XER_xer_so_spr0_2 \$641 + connect \pick_XER_xer_so_spr0_2 \$639 + connect \addr_en_XER_xer_so_logical0_1 \$631 + connect \rp_XER_xer_so_logical0_1 \$629 + connect \pick_XER_xer_so_logical0_1 \$627 + connect \addr_en_XER_xer_so_alu0_0 \$619 + connect \rp_XER_xer_so_alu0_0 \$617 + connect \rdpick_XER_xer_so_i [5] \pick_XER_xer_so_shiftrot0_5 + connect \rdpick_XER_xer_so_i [4] \pick_XER_xer_so_mul0_4 + connect \rdpick_XER_xer_so_i [3] \pick_XER_xer_so_div0_3 + connect \rdpick_XER_xer_so_i [2] \pick_XER_xer_so_spr0_2 + connect \rdpick_XER_xer_so_i [1] \pick_XER_xer_so_logical0_1 + connect \rdpick_XER_xer_so_i [0] \pick_XER_xer_so_alu0_0 + connect \pick_XER_xer_so_alu0_0 \$615 + connect \rdflag_XER_xer_so_0 \$607 + connect \int_src3__ren \$595 + connect \int_src3__addr \$593 + connect \addr_en_INT_rc_ldst0_1 \$591 + connect \rp_INT_rc_ldst0_1 \$589 + connect \pick_INT_rc_ldst0_1 \$587 + connect \addr_en_INT_rc_shiftrot0_0 \$579 + connect \rp_INT_rc_shiftrot0_0 \$577 + connect \rdpick_INT_rc_i [1] \pick_INT_rc_ldst0_1 + connect \rdpick_INT_rc_i [0] \pick_INT_rc_shiftrot0_0 + connect \pick_INT_rc_shiftrot0_0 \$575 + connect \rdflag_INT_rc_0 \core_reg3_ok + connect \int_src2__ren \$567 + connect \int_src2__addr \$565 + connect \addr_en_INT_rb_ldst0_7 \$551 + connect \rp_INT_rb_ldst0_7 \$549 + connect \pick_INT_rb_ldst0_7 \$547 + connect \addr_en_INT_rb_shiftrot0_6 \$539 + connect \rp_INT_rb_shiftrot0_6 \$537 + connect \pick_INT_rb_shiftrot0_6 \$535 + connect \addr_en_INT_rb_mul0_5 \$527 + connect \rp_INT_rb_mul0_5 \$525 + connect \pick_INT_rb_mul0_5 \$523 + connect \addr_en_INT_rb_div0_4 \$515 + connect \rp_INT_rb_div0_4 \$513 + connect \pick_INT_rb_div0_4 \$511 + connect \addr_en_INT_rb_logical0_3 \$503 + connect \rp_INT_rb_logical0_3 \$501 + connect \pick_INT_rb_logical0_3 \$499 + connect \addr_en_INT_rb_trap0_2 \$491 + connect \rp_INT_rb_trap0_2 \$489 + connect \pick_INT_rb_trap0_2 \$487 + connect \addr_en_INT_rb_cr0_1 \$479 + connect \rp_INT_rb_cr0_1 \$477 + connect \pick_INT_rb_cr0_1 \$475 + connect \addr_en_INT_rb_alu0_0 \$467 + connect \rp_INT_rb_alu0_0 \$465 + connect \rdpick_INT_rb_i [7] \pick_INT_rb_ldst0_7 + connect \rdpick_INT_rb_i [6] \pick_INT_rb_shiftrot0_6 + connect \rdpick_INT_rb_i [5] \pick_INT_rb_mul0_5 + connect \rdpick_INT_rb_i [4] \pick_INT_rb_div0_4 + connect \rdpick_INT_rb_i [3] \pick_INT_rb_logical0_3 + connect \rdpick_INT_rb_i [2] \pick_INT_rb_trap0_2 + connect \rdpick_INT_rb_i [1] \pick_INT_rb_cr0_1 + connect \rdpick_INT_rb_i [0] \pick_INT_rb_alu0_0 + connect \pick_INT_rb_alu0_0 \$463 + connect \rdflag_INT_rb_0 \core_reg2_ok + connect \int_src1__ren \$455 + connect \int_src1__addr \$453 + connect \addr_en_INT_ra_ldst0_8 \$437 + connect \rp_INT_ra_ldst0_8 \$435 + connect \fus_cu_rd__go_i$53 [2] \dp_INT_rc_ldst0_1 + connect \fus_cu_rd__go_i$53 [1] \dp_INT_rb_ldst0_7 + connect \fus_cu_rd__go_i$53 [0] \dp_INT_ra_ldst0_8 + connect \pick_INT_ra_ldst0_8 \$433 + connect \addr_en_INT_ra_shiftrot0_7 \$425 + connect \rp_INT_ra_shiftrot0_7 \$423 + connect \fus_cu_rd__go_i$50 [4] \dp_XER_xer_ca_shiftrot0_2 + connect \fus_cu_rd__go_i$50 [3] \dp_XER_xer_so_shiftrot0_5 + connect \fus_cu_rd__go_i$50 [2] \dp_INT_rc_shiftrot0_0 + connect \fus_cu_rd__go_i$50 [1] \dp_INT_rb_shiftrot0_6 + connect \fus_cu_rd__go_i$50 [0] \dp_INT_ra_shiftrot0_7 + connect \pick_INT_ra_shiftrot0_7 \$421 + connect \addr_en_INT_ra_mul0_6 \$413 + connect \rp_INT_ra_mul0_6 \$411 + connect \fus_cu_rd__go_i$47 [2] \dp_XER_xer_so_mul0_4 + connect \fus_cu_rd__go_i$47 [1] \dp_INT_rb_mul0_5 + connect \fus_cu_rd__go_i$47 [0] \dp_INT_ra_mul0_6 + connect \pick_INT_ra_mul0_6 \$409 + connect \addr_en_INT_ra_div0_5 \$401 + connect \rp_INT_ra_div0_5 \$399 + connect \fus_cu_rd__go_i$44 [2] \dp_XER_xer_so_div0_3 + connect \fus_cu_rd__go_i$44 [1] \dp_INT_rb_div0_4 + connect \fus_cu_rd__go_i$44 [0] \dp_INT_ra_div0_5 + connect \pick_INT_ra_div0_5 \$397 + connect \addr_en_INT_ra_spr0_4 \$389 + connect \rp_INT_ra_spr0_4 \$387 + connect \fus_cu_rd__go_i$41 [1] \dp_SPR_spr1_spr0_0 + connect \fus_cu_rd__go_i$41 [2] \dp_FAST_fast1_spr0_2 + connect \fus_cu_rd__go_i$41 [4] \dp_XER_xer_ov_spr0_0 + connect \fus_cu_rd__go_i$41 [5] \dp_XER_xer_ca_spr0_1 + connect \fus_cu_rd__go_i$41 [3] \dp_XER_xer_so_spr0_2 + connect \fus_cu_rd__go_i$41 [0] \dp_INT_ra_spr0_4 + connect \pick_INT_ra_spr0_4 \$385 + connect \addr_en_INT_ra_logical0_3 \$377 + connect \rp_INT_ra_logical0_3 \$375 + connect \fus_cu_rd__go_i$38 [2] \dp_XER_xer_so_logical0_1 + connect \fus_cu_rd__go_i$38 [1] \dp_INT_rb_logical0_3 + connect \fus_cu_rd__go_i$38 [0] \dp_INT_ra_logical0_3 + connect \pick_INT_ra_logical0_3 \$373 + connect \addr_en_INT_ra_trap0_2 \$365 + connect \rp_INT_ra_trap0_2 \$363 + connect \fus_cu_rd__go_i$35 [3] \dp_FAST_fast2_trap0_1 + connect \fus_cu_rd__go_i$35 [2] \dp_FAST_fast1_trap0_1 + connect \fus_cu_rd__go_i$35 [1] \dp_INT_rb_trap0_2 + connect \fus_cu_rd__go_i$35 [0] \dp_INT_ra_trap0_2 + connect \pick_INT_ra_trap0_2 \$361 + connect \addr_en_INT_ra_cr0_1 \$353 + connect \rp_INT_ra_cr0_1 \$351 + connect \fus_cu_rd__go_i$32 [5] \dp_CR_cr_c_cr0_0 + connect \fus_cu_rd__go_i$32 [4] \dp_CR_cr_b_cr0_0 + connect \fus_cu_rd__go_i$32 [3] \dp_CR_cr_a_cr0_0 + connect \fus_cu_rd__go_i$32 [2] \dp_CR_full_cr_cr0_0 + connect \fus_cu_rd__go_i$32 [1] \dp_INT_rb_cr0_1 + connect \fus_cu_rd__go_i$32 [0] \dp_INT_ra_cr0_1 + connect \pick_INT_ra_cr0_1 \$349 + connect \addr_en_INT_ra_alu0_0 \$341 + connect \rp_INT_ra_alu0_0 \$339 + connect \fus_cu_rd__go_i [3] \dp_XER_xer_ca_alu0_0 + connect \fus_cu_rd__go_i [2] \dp_XER_xer_so_alu0_0 + connect \fus_cu_rd__go_i [1] \dp_INT_rb_alu0_0 + connect \fus_cu_rd__go_i [0] \dp_INT_ra_alu0_0 + connect \rdpick_INT_ra_i [8] \pick_INT_ra_ldst0_8 + connect \rdpick_INT_ra_i [7] \pick_INT_ra_shiftrot0_7 + connect \rdpick_INT_ra_i [6] \pick_INT_ra_mul0_6 + connect \rdpick_INT_ra_i [5] \pick_INT_ra_div0_5 + connect \rdpick_INT_ra_i [4] \pick_INT_ra_spr0_4 + connect \rdpick_INT_ra_i [3] \pick_INT_ra_logical0_3 + connect \rdpick_INT_ra_i [2] \pick_INT_ra_trap0_2 + connect \rdpick_INT_ra_i [1] \pick_INT_ra_cr0_1 + connect \rdpick_INT_ra_i [0] \pick_INT_ra_alu0_0 + connect \pick_INT_ra_alu0_0 \$337 + connect \rdflag_INT_ra_0 \core_reg1_ok + connect \en_ldst0 \$196 + connect \en_shiftrot0 \$192 + connect \en_mul0 \$188 + connect \en_div0 \$184 + connect \en_spr0 \$180 + connect \en_logical0 \$176 + connect \en_trap0 \$172 + connect \en_branch0 \$168 + connect \en_cr0 \$164 + connect \fu_enable [9] \en_ldst0 + connect \fu_enable [8] \en_shiftrot0 + connect \fu_enable [7] \en_mul0 + connect \fu_enable [6] \en_div0 + connect \fu_enable [5] \en_spr0 + connect \fu_enable [4] \en_logical0 + connect \fu_enable [3] \en_trap0 + connect \fu_enable [2] \en_branch0 + connect \fu_enable [1] \en_cr0 + connect \fu_enable [0] \en_alu0 + connect \en_alu0 \$160 + connect \dec_LDST_bigendian \bigendian_i + connect \dec_LDST_raw_opcode_in \raw_insn_i + connect \dec_SHIFT_ROT_bigendian \bigendian_i + connect \dec_SHIFT_ROT_raw_opcode_in \raw_insn_i + connect \dec_MUL_bigendian \bigendian_i + connect \dec_MUL_raw_opcode_in \raw_insn_i + connect \dec_DIV_bigendian \bigendian_i + connect \dec_DIV_raw_opcode_in \raw_insn_i + connect \dec_SPR_bigendian \bigendian_i + connect \dec_SPR_raw_opcode_in \raw_insn_i + connect \dec_LOGICAL_bigendian \bigendian_i + connect \dec_LOGICAL_raw_opcode_in \raw_insn_i + connect \dec_BRANCH_bigendian \bigendian_i + connect \dec_BRANCH_raw_opcode_in \raw_insn_i + connect \dec_CR_bigendian \bigendian_i + connect \dec_CR_raw_opcode_in \raw_insn_i + connect \dec_ALU_bigendian \bigendian_i + connect \dec_ALU_raw_opcode_in \raw_insn_i +end +attribute \src "libresoc.v:48043.1-48676.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.cr" +attribute \generator "nMigen" +module \cr + attribute \src "libresoc.v:48044.7-48044.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:48590.3-48598.6" + wire width 8 $0\ren_delay$17$next[7:0]$3052 + attribute \src "libresoc.v:48426.3-48427.43" + wire width 8 $0\ren_delay$17[7:0]$3049 + attribute \src "libresoc.v:48372.13-48372.35" + wire width 8 $0\ren_delay$17[7:0]$3066 + attribute \src "libresoc.v:48609.3-48617.6" + wire width 8 $0\ren_delay$34$next[7:0]$3056 + attribute \src "libresoc.v:48424.3-48425.43" + wire width 8 $0\ren_delay$34[7:0]$3047 + attribute \src "libresoc.v:48376.13-48376.35" + wire width 8 $0\ren_delay$34[7:0]$3068 + attribute \src "libresoc.v:48628.3-48636.6" + wire width 8 $0\ren_delay$next[7:0]$3060 + attribute \src "libresoc.v:48428.3-48429.35" + wire width 8 $0\ren_delay[7:0] + attribute \src "libresoc.v:48637.3-48646.6" + wire width 4 $0\src1__data_o[3:0] + attribute \src "libresoc.v:48599.3-48608.6" + wire width 4 $0\src2__data_o[3:0] + attribute \src "libresoc.v:48618.3-48627.6" + wire width 4 $0\src3__data_o[3:0] + attribute \src "libresoc.v:48590.3-48598.6" + wire width 8 $1\ren_delay$17$next[7:0]$3053 + attribute \src "libresoc.v:48609.3-48617.6" + wire width 8 $1\ren_delay$34$next[7:0]$3057 + attribute \src "libresoc.v:48628.3-48636.6" + wire width 8 $1\ren_delay$next[7:0]$3061 + attribute \src "libresoc.v:48370.13-48370.30" + wire width 8 $1\ren_delay[7:0] + attribute \src "libresoc.v:48637.3-48646.6" + wire width 4 $1\src1__data_o[3:0] + attribute \src "libresoc.v:48599.3-48608.6" + wire width 4 $1\src2__data_o[3:0] + attribute \src "libresoc.v:48618.3-48627.6" + wire width 4 $1\src3__data_o[3:0] + attribute \src "libresoc.v:48400.17-48400.125" + wire width 4 $or$libresoc.v:48400$3022_Y + attribute \src "libresoc.v:48401.18-48401.126" + wire width 4 $or$libresoc.v:48401$3023_Y + attribute \src "libresoc.v:48402.18-48402.96" + wire width 4 $or$libresoc.v:48402$3024_Y + attribute \src "libresoc.v:48403.18-48403.96" + wire width 4 $or$libresoc.v:48403$3025_Y + attribute \src "libresoc.v:48406.18-48406.126" + wire width 4 $or$libresoc.v:48406$3028_Y + attribute \src "libresoc.v:48407.18-48407.126" + wire width 4 $or$libresoc.v:48407$3029_Y + attribute \src "libresoc.v:48408.18-48408.97" + wire width 4 $or$libresoc.v:48408$3030_Y + attribute \src "libresoc.v:48409.18-48409.126" + wire width 4 $or$libresoc.v:48409$3031_Y + attribute \src "libresoc.v:48410.18-48410.126" + wire width 4 $or$libresoc.v:48410$3032_Y + attribute \src "libresoc.v:48411.18-48411.97" + wire width 4 $or$libresoc.v:48411$3033_Y + attribute \src "libresoc.v:48412.18-48412.97" + wire width 4 $or$libresoc.v:48412$3034_Y + attribute \src "libresoc.v:48414.18-48414.126" + wire width 4 $or$libresoc.v:48414$3036_Y + attribute \src "libresoc.v:48415.17-48415.125" + wire width 4 $or$libresoc.v:48415$3037_Y + attribute \src "libresoc.v:48416.18-48416.126" + wire width 4 $or$libresoc.v:48416$3038_Y + attribute \src "libresoc.v:48417.18-48417.97" + wire width 4 $or$libresoc.v:48417$3039_Y + attribute \src "libresoc.v:48418.18-48418.126" + wire width 4 $or$libresoc.v:48418$3040_Y + attribute \src "libresoc.v:48419.18-48419.126" + wire width 4 $or$libresoc.v:48419$3041_Y + attribute \src "libresoc.v:48420.18-48420.97" + wire width 4 $or$libresoc.v:48420$3042_Y + attribute \src "libresoc.v:48421.18-48421.97" + wire width 4 $or$libresoc.v:48421$3043_Y + attribute \src "libresoc.v:48422.17-48422.125" + wire width 4 $or$libresoc.v:48422$3044_Y + attribute \src "libresoc.v:48423.17-48423.94" + wire width 4 $or$libresoc.v:48423$3045_Y + attribute \src "libresoc.v:48404.18-48404.100" + wire $reduce_or$libresoc.v:48404$3026_Y + attribute \src "libresoc.v:48405.17-48405.95" + wire $reduce_or$libresoc.v:48405$3027_Y + attribute \src "libresoc.v:48413.18-48413.100" + wire $reduce_or$libresoc.v:48413$3035_Y + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 4 \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 4 \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 4 \$15 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + wire \$18 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 4 \$20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 4 \$22 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 4 \$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 4 \$26 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 4 \$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 4 \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 4 \$30 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 4 \$32 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + wire \$35 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 4 \$37 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 4 \$39 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 4 \$41 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 4 \$43 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 4 \$45 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 4 \$47 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 4 \$49 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 4 \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 4 \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 4 \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 16 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 15 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 input 13 \data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \data_i$52 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 32 output 2 \full_rd2__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 8 input 1 \full_rd2__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 32 output 3 \full_rd__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 8 input 4 \full_rd__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 32 input 11 \full_wr__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 8 input 12 \full_wr__wen + attribute \src "libresoc.v:48044.7-48044.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_0_dest10__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_0_dest10__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_0_dest20__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_0_dest20__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_0_r0__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_0_r0__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_0_r20__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_0_r20__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_0_src10__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_0_src10__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_0_src20__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_0_src20__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_0_src30__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_0_src30__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_0_w0__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_0_w0__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_1_dest11__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_1_dest11__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_1_dest21__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_1_dest21__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_1_r1__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_1_r1__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_1_r21__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_1_r21__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_1_src11__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_1_src11__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_1_src21__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_1_src21__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_1_src31__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_1_src31__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_1_w1__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_1_w1__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_2_dest12__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_2_dest12__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_2_dest22__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_2_dest22__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_2_r22__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_2_r22__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_2_r2__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_2_r2__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_2_src12__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_2_src12__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_2_src22__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_2_src22__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_2_src32__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_2_src32__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_2_w2__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_2_w2__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_3_dest13__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_3_dest13__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_3_dest23__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_3_dest23__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_3_r23__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_3_r23__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_3_r3__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_3_r3__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_3_src13__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_3_src13__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_3_src23__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_3_src23__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_3_src33__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_3_src33__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_3_w3__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_3_w3__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_4_dest14__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_4_dest14__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_4_dest24__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_4_dest24__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_4_r24__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_4_r24__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_4_r4__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_4_r4__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_4_src14__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_4_src14__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_4_src24__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_4_src24__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_4_src34__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_4_src34__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_4_w4__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_4_w4__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_5_dest15__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_5_dest15__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_5_dest25__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_5_dest25__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_5_r25__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_5_r25__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_5_r5__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_5_r5__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_5_src15__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_5_src15__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_5_src25__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_5_src25__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_5_src35__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_5_src35__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_5_w5__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_5_w5__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_6_dest16__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_6_dest16__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_6_dest26__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_6_dest26__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_6_r26__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_6_r26__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_6_r6__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_6_r6__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_6_src16__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_6_src16__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_6_src26__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_6_src26__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_6_src36__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_6_src36__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_6_w6__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_6_w6__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_7_dest17__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_7_dest17__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_7_dest27__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_7_dest27__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_7_r27__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_7_r27__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_7_r7__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_7_r7__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_7_src17__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_7_src17__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_7_src27__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_7_src27__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_7_src37__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_7_src37__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_7_w7__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_7_w7__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" + wire width 8 \ren_delay + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" + wire width 8 \ren_delay$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" + wire width 8 \ren_delay$17$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" + wire width 8 \ren_delay$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" + wire width 8 \ren_delay$34$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" + wire width 8 \ren_delay$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 5 \src1__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 8 input 6 \src1__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 7 \src2__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 8 input 8 \src2__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 9 \src3__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 8 input 10 \src3__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 8 input 14 \wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 8 \wen$51 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $or$libresoc.v:48400$3022 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \reg_4_src14__data_o + connect \B \reg_5_src15__data_o + connect \Y $or$libresoc.v:48400$3022_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $or$libresoc.v:48401$3023 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \reg_6_src16__data_o + connect \B \reg_7_src17__data_o + connect \Y $or$libresoc.v:48401$3023_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $or$libresoc.v:48402$3024 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \$9 + connect \B \$11 + connect \Y $or$libresoc.v:48402$3024_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $or$libresoc.v:48403$3025 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \$7 + connect \B \$13 + connect \Y $or$libresoc.v:48403$3025_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $or$libresoc.v:48406$3028 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \reg_0_src20__data_o + connect \B \reg_1_src21__data_o + connect \Y $or$libresoc.v:48406$3028_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $or$libresoc.v:48407$3029 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \reg_2_src22__data_o + connect \B \reg_3_src23__data_o + connect \Y $or$libresoc.v:48407$3029_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $or$libresoc.v:48408$3030 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \$20 + connect \B \$22 + connect \Y $or$libresoc.v:48408$3030_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $or$libresoc.v:48409$3031 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \reg_4_src24__data_o + connect \B \reg_5_src25__data_o + connect \Y $or$libresoc.v:48409$3031_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $or$libresoc.v:48410$3032 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \reg_6_src26__data_o + connect \B \reg_7_src27__data_o + connect \Y $or$libresoc.v:48410$3032_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $or$libresoc.v:48411$3033 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \$26 + connect \B \$28 + connect \Y $or$libresoc.v:48411$3033_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $or$libresoc.v:48412$3034 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \$24 + connect \B \$30 + connect \Y $or$libresoc.v:48412$3034_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $or$libresoc.v:48414$3036 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \reg_0_src30__data_o + connect \B \reg_1_src31__data_o + connect \Y $or$libresoc.v:48414$3036_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $or$libresoc.v:48415$3037 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \reg_0_src10__data_o + connect \B \reg_1_src11__data_o + connect \Y $or$libresoc.v:48415$3037_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $or$libresoc.v:48416$3038 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \reg_2_src32__data_o + connect \B \reg_3_src33__data_o + connect \Y $or$libresoc.v:48416$3038_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $or$libresoc.v:48417$3039 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \$37 + connect \B \$39 + connect \Y $or$libresoc.v:48417$3039_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $or$libresoc.v:48418$3040 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \reg_4_src34__data_o + connect \B \reg_5_src35__data_o + connect \Y $or$libresoc.v:48418$3040_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $or$libresoc.v:48419$3041 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \reg_6_src36__data_o + connect \B \reg_7_src37__data_o + connect \Y $or$libresoc.v:48419$3041_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $or$libresoc.v:48420$3042 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \$43 + connect \B \$45 + connect \Y $or$libresoc.v:48420$3042_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $or$libresoc.v:48421$3043 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \$41 + connect \B \$47 + connect \Y $or$libresoc.v:48421$3043_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $or$libresoc.v:48422$3044 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \reg_2_src12__data_o + connect \B \reg_3_src13__data_o + connect \Y $or$libresoc.v:48422$3044_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $or$libresoc.v:48423$3045 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \$3 + connect \B \$5 + connect \Y $or$libresoc.v:48423$3045_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + cell $reduce_or $reduce_or$libresoc.v:48404$3026 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ren_delay$17 + connect \Y $reduce_or$libresoc.v:48404$3026_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + cell $reduce_or $reduce_or$libresoc.v:48405$3027 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ren_delay + connect \Y $reduce_or$libresoc.v:48405$3027_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + cell $reduce_or $reduce_or$libresoc.v:48413$3035 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ren_delay$34 + connect \Y $reduce_or$libresoc.v:48413$3035_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:48430.9-48449.4" + cell \reg_0 \reg_0 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \dest10__data_i \reg_0_dest10__data_i + connect \dest10__wen \reg_0_dest10__wen + connect \dest20__data_i \reg_0_dest20__data_i + connect \dest20__wen \reg_0_dest20__wen + connect \r0__data_o \reg_0_r0__data_o + connect \r0__ren \reg_0_r0__ren + connect \r20__data_o \reg_0_r20__data_o + connect \r20__ren \reg_0_r20__ren + connect \src10__data_o \reg_0_src10__data_o + connect \src10__ren \reg_0_src10__ren + connect \src20__data_o \reg_0_src20__data_o + connect \src20__ren \reg_0_src20__ren + connect \src30__data_o \reg_0_src30__data_o + connect \src30__ren \reg_0_src30__ren + connect \w0__data_i \reg_0_w0__data_i + connect \w0__wen \reg_0_w0__wen + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:48450.9-48469.4" + cell \reg_1 \reg_1 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \dest11__data_i \reg_1_dest11__data_i + connect \dest11__wen \reg_1_dest11__wen + connect \dest21__data_i \reg_1_dest21__data_i + connect \dest21__wen \reg_1_dest21__wen + connect \r1__data_o \reg_1_r1__data_o + connect \r1__ren \reg_1_r1__ren + connect \r21__data_o \reg_1_r21__data_o + connect \r21__ren \reg_1_r21__ren + connect \src11__data_o \reg_1_src11__data_o + connect \src11__ren \reg_1_src11__ren + connect \src21__data_o \reg_1_src21__data_o + connect \src21__ren \reg_1_src21__ren + connect \src31__data_o \reg_1_src31__data_o + connect \src31__ren \reg_1_src31__ren + connect \w1__data_i \reg_1_w1__data_i + connect \w1__wen \reg_1_w1__wen + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:48470.9-48489.4" + cell \reg_2 \reg_2 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \dest12__data_i \reg_2_dest12__data_i + connect \dest12__wen \reg_2_dest12__wen + connect \dest22__data_i \reg_2_dest22__data_i + connect \dest22__wen \reg_2_dest22__wen + connect \r22__data_o \reg_2_r22__data_o + connect \r22__ren \reg_2_r22__ren + connect \r2__data_o \reg_2_r2__data_o + connect \r2__ren \reg_2_r2__ren + connect \src12__data_o \reg_2_src12__data_o + connect \src12__ren \reg_2_src12__ren + connect \src22__data_o \reg_2_src22__data_o + connect \src22__ren \reg_2_src22__ren + connect \src32__data_o \reg_2_src32__data_o + connect \src32__ren \reg_2_src32__ren + connect \w2__data_i \reg_2_w2__data_i + connect \w2__wen \reg_2_w2__wen + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:48490.9-48509.4" + cell \reg_3 \reg_3 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \dest13__data_i \reg_3_dest13__data_i + connect \dest13__wen \reg_3_dest13__wen + connect \dest23__data_i \reg_3_dest23__data_i + connect \dest23__wen \reg_3_dest23__wen + connect \r23__data_o \reg_3_r23__data_o + connect \r23__ren \reg_3_r23__ren + connect \r3__data_o \reg_3_r3__data_o + connect \r3__ren \reg_3_r3__ren + connect \src13__data_o \reg_3_src13__data_o + connect \src13__ren \reg_3_src13__ren + connect \src23__data_o \reg_3_src23__data_o + connect \src23__ren \reg_3_src23__ren + connect \src33__data_o \reg_3_src33__data_o + connect \src33__ren \reg_3_src33__ren + connect \w3__data_i \reg_3_w3__data_i + connect \w3__wen \reg_3_w3__wen + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:48510.9-48529.4" + cell \reg_4 \reg_4 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \dest14__data_i \reg_4_dest14__data_i + connect \dest14__wen \reg_4_dest14__wen + connect \dest24__data_i \reg_4_dest24__data_i + connect \dest24__wen \reg_4_dest24__wen + connect \r24__data_o \reg_4_r24__data_o + connect \r24__ren \reg_4_r24__ren + connect \r4__data_o \reg_4_r4__data_o + connect \r4__ren \reg_4_r4__ren + connect \src14__data_o \reg_4_src14__data_o + connect \src14__ren \reg_4_src14__ren + connect \src24__data_o \reg_4_src24__data_o + connect \src24__ren \reg_4_src24__ren + connect \src34__data_o \reg_4_src34__data_o + connect \src34__ren \reg_4_src34__ren + connect \w4__data_i \reg_4_w4__data_i + connect \w4__wen \reg_4_w4__wen + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:48530.9-48549.4" + cell \reg_5 \reg_5 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \dest15__data_i \reg_5_dest15__data_i + connect \dest15__wen \reg_5_dest15__wen + connect \dest25__data_i \reg_5_dest25__data_i + connect \dest25__wen \reg_5_dest25__wen + connect \r25__data_o \reg_5_r25__data_o + connect \r25__ren \reg_5_r25__ren + connect \r5__data_o \reg_5_r5__data_o + connect \r5__ren \reg_5_r5__ren + connect \src15__data_o \reg_5_src15__data_o + connect \src15__ren \reg_5_src15__ren + connect \src25__data_o \reg_5_src25__data_o + connect \src25__ren \reg_5_src25__ren + connect \src35__data_o \reg_5_src35__data_o + connect \src35__ren \reg_5_src35__ren + connect \w5__data_i \reg_5_w5__data_i + connect \w5__wen \reg_5_w5__wen + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:48550.9-48569.4" + cell \reg_6 \reg_6 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \dest16__data_i \reg_6_dest16__data_i + connect \dest16__wen \reg_6_dest16__wen + connect \dest26__data_i \reg_6_dest26__data_i + connect \dest26__wen \reg_6_dest26__wen + connect \r26__data_o \reg_6_r26__data_o + connect \r26__ren \reg_6_r26__ren + connect \r6__data_o \reg_6_r6__data_o + connect \r6__ren \reg_6_r6__ren + connect \src16__data_o \reg_6_src16__data_o + connect \src16__ren \reg_6_src16__ren + connect \src26__data_o \reg_6_src26__data_o + connect \src26__ren \reg_6_src26__ren + connect \src36__data_o \reg_6_src36__data_o + connect \src36__ren \reg_6_src36__ren + connect \w6__data_i \reg_6_w6__data_i + connect \w6__wen \reg_6_w6__wen + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:48570.9-48589.4" + cell \reg_7 \reg_7 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \dest17__data_i \reg_7_dest17__data_i + connect \dest17__wen \reg_7_dest17__wen + connect \dest27__data_i \reg_7_dest27__data_i + connect \dest27__wen \reg_7_dest27__wen + connect \r27__data_o \reg_7_r27__data_o + connect \r27__ren \reg_7_r27__ren + connect \r7__data_o \reg_7_r7__data_o + connect \r7__ren \reg_7_r7__ren + connect \src17__data_o \reg_7_src17__data_o + connect \src17__ren \reg_7_src17__ren + connect \src27__data_o \reg_7_src27__data_o + connect \src27__ren \reg_7_src27__ren + connect \src37__data_o \reg_7_src37__data_o + connect \src37__ren \reg_7_src37__ren + connect \w7__data_i \reg_7_w7__data_i + connect \w7__wen \reg_7_w7__wen + end + attribute \src "libresoc.v:48044.7-48044.20" + process $proc$libresoc.v:48044$3063 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:48370.13-48370.30" + process $proc$libresoc.v:48370$3064 + assign { } { } + assign $1\ren_delay[7:0] 8'00000000 + sync always + sync init + update \ren_delay $1\ren_delay[7:0] + end + attribute \src "libresoc.v:48372.13-48372.35" + process $proc$libresoc.v:48372$3065 + assign { } { } + assign $0\ren_delay$17[7:0]$3066 8'00000000 + sync always + sync init + update \ren_delay$17 $0\ren_delay$17[7:0]$3066 + end + attribute \src "libresoc.v:48376.13-48376.35" + process $proc$libresoc.v:48376$3067 + assign { } { } + assign $0\ren_delay$34[7:0]$3068 8'00000000 + sync always + sync init + update \ren_delay$34 $0\ren_delay$34[7:0]$3068 + end + attribute \src "libresoc.v:48424.3-48425.43" + process $proc$libresoc.v:48424$3046 + assign { } { } + assign $0\ren_delay$34[7:0]$3047 \ren_delay$34$next + sync posedge \coresync_clk + update \ren_delay$34 $0\ren_delay$34[7:0]$3047 + end + attribute \src "libresoc.v:48426.3-48427.43" + process $proc$libresoc.v:48426$3048 + assign { } { } + assign $0\ren_delay$17[7:0]$3049 \ren_delay$17$next + sync posedge \coresync_clk + update \ren_delay$17 $0\ren_delay$17[7:0]$3049 + end + attribute \src "libresoc.v:48428.3-48429.35" + process $proc$libresoc.v:48428$3050 + assign { } { } + assign $0\ren_delay[7:0] \ren_delay$next + sync posedge \coresync_clk + update \ren_delay $0\ren_delay[7:0] + end + attribute \src "libresoc.v:48590.3-48598.6" + process $proc$libresoc.v:48590$3051 + assign { } { } + assign { } { } + assign $0\ren_delay$17$next[7:0]$3052 $1\ren_delay$17$next[7:0]$3053 + attribute \src "libresoc.v:48591.5-48591.29" + switch \initial + attribute \src "libresoc.v:48591.9-48591.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ren_delay$17$next[7:0]$3053 8'00000000 + case + assign $1\ren_delay$17$next[7:0]$3053 \src2__ren + end + sync always + update \ren_delay$17$next $0\ren_delay$17$next[7:0]$3052 + end + attribute \src "libresoc.v:48599.3-48608.6" + process $proc$libresoc.v:48599$3054 + assign { } { } + assign { } { } + assign $0\src2__data_o[3:0] $1\src2__data_o[3:0] + attribute \src "libresoc.v:48600.5-48600.29" + switch \initial + attribute \src "libresoc.v:48600.9-48600.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" + switch \$18 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src2__data_o[3:0] \$32 + case + assign $1\src2__data_o[3:0] 4'0000 + end + sync always + update \src2__data_o $0\src2__data_o[3:0] + end + attribute \src "libresoc.v:48609.3-48617.6" + process $proc$libresoc.v:48609$3055 + assign { } { } + assign { } { } + assign $0\ren_delay$34$next[7:0]$3056 $1\ren_delay$34$next[7:0]$3057 + attribute \src "libresoc.v:48610.5-48610.29" + switch \initial + attribute \src "libresoc.v:48610.9-48610.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ren_delay$34$next[7:0]$3057 8'00000000 + case + assign $1\ren_delay$34$next[7:0]$3057 \src3__ren + end + sync always + update \ren_delay$34$next $0\ren_delay$34$next[7:0]$3056 + end + attribute \src "libresoc.v:48618.3-48627.6" + process $proc$libresoc.v:48618$3058 + assign { } { } + assign { } { } + assign $0\src3__data_o[3:0] $1\src3__data_o[3:0] + attribute \src "libresoc.v:48619.5-48619.29" + switch \initial + attribute \src "libresoc.v:48619.9-48619.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" + switch \$35 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src3__data_o[3:0] \$49 + case + assign $1\src3__data_o[3:0] 4'0000 + end + sync always + update \src3__data_o $0\src3__data_o[3:0] + end + attribute \src "libresoc.v:48628.3-48636.6" + process $proc$libresoc.v:48628$3059 + assign { } { } + assign { } { } + assign $0\ren_delay$next[7:0]$3060 $1\ren_delay$next[7:0]$3061 + attribute \src "libresoc.v:48629.5-48629.29" + switch \initial + attribute \src "libresoc.v:48629.9-48629.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ren_delay$next[7:0]$3061 8'00000000 + case + assign $1\ren_delay$next[7:0]$3061 \src1__ren + end + sync always + update \ren_delay$next $0\ren_delay$next[7:0]$3060 + end + attribute \src "libresoc.v:48637.3-48646.6" + process $proc$libresoc.v:48637$3062 + assign { } { } + assign { } { } + assign $0\src1__data_o[3:0] $1\src1__data_o[3:0] + attribute \src "libresoc.v:48638.5-48638.29" + switch \initial + attribute \src "libresoc.v:48638.9-48638.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src1__data_o[3:0] \$15 + case + assign $1\src1__data_o[3:0] 4'0000 + end + sync always + update \src1__data_o $0\src1__data_o[3:0] + end + connect \$9 $or$libresoc.v:48400$3022_Y + connect \$11 $or$libresoc.v:48401$3023_Y + connect \$13 $or$libresoc.v:48402$3024_Y + connect \$15 $or$libresoc.v:48403$3025_Y + connect \$18 $reduce_or$libresoc.v:48404$3026_Y + connect \$1 $reduce_or$libresoc.v:48405$3027_Y + connect \$20 $or$libresoc.v:48406$3028_Y + connect \$22 $or$libresoc.v:48407$3029_Y + connect \$24 $or$libresoc.v:48408$3030_Y + connect \$26 $or$libresoc.v:48409$3031_Y + connect \$28 $or$libresoc.v:48410$3032_Y + connect \$30 $or$libresoc.v:48411$3033_Y + connect \$32 $or$libresoc.v:48412$3034_Y + connect \$35 $reduce_or$libresoc.v:48413$3035_Y + connect \$37 $or$libresoc.v:48414$3036_Y + connect \$3 $or$libresoc.v:48415$3037_Y + connect \$39 $or$libresoc.v:48416$3038_Y + connect \$41 $or$libresoc.v:48417$3039_Y + connect \$43 $or$libresoc.v:48418$3040_Y + connect \$45 $or$libresoc.v:48419$3041_Y + connect \$47 $or$libresoc.v:48420$3042_Y + connect \$49 $or$libresoc.v:48421$3043_Y + connect \$5 $or$libresoc.v:48422$3044_Y + connect \$7 $or$libresoc.v:48423$3045_Y + connect \wen$51 8'00000000 + connect \data_i$52 4'0000 + connect { \reg_7_w7__wen \reg_6_w6__wen \reg_5_w5__wen \reg_4_w4__wen \reg_3_w3__wen \reg_2_w2__wen \reg_1_w1__wen \reg_0_w0__wen } \full_wr__wen + connect { \reg_7_w7__data_i \reg_6_w6__data_i \reg_5_w5__data_i \reg_4_w4__data_i \reg_3_w3__data_i \reg_2_w2__data_i \reg_1_w1__data_i \reg_0_w0__data_i } \full_wr__data_i + connect { \reg_7_r27__ren \reg_6_r26__ren \reg_5_r25__ren \reg_4_r24__ren \reg_3_r23__ren \reg_2_r22__ren \reg_1_r21__ren \reg_0_r20__ren } \full_rd2__ren + connect \full_rd2__data_o { \reg_7_r27__data_o \reg_6_r26__data_o \reg_5_r25__data_o \reg_4_r24__data_o \reg_3_r23__data_o \reg_2_r22__data_o \reg_1_r21__data_o \reg_0_r20__data_o } + connect { \reg_7_r7__ren \reg_6_r6__ren \reg_5_r5__ren \reg_4_r4__ren \reg_3_r3__ren \reg_2_r2__ren \reg_1_r1__ren \reg_0_r0__ren } \full_rd__ren + connect \full_rd__data_o { \reg_7_r7__data_o \reg_6_r6__data_o \reg_5_r5__data_o \reg_4_r4__data_o \reg_3_r3__data_o \reg_2_r2__data_o \reg_1_r1__data_o \reg_0_r0__data_o } + connect \reg_7_dest27__data_i 4'0000 + connect \reg_6_dest26__data_i 4'0000 + connect \reg_5_dest25__data_i 4'0000 + connect \reg_4_dest24__data_i 4'0000 + connect \reg_3_dest23__data_i 4'0000 + connect \reg_2_dest22__data_i 4'0000 + connect \reg_1_dest21__data_i 4'0000 + connect \reg_0_dest20__data_i 4'0000 + connect { \reg_7_dest27__wen \reg_6_dest26__wen \reg_5_dest25__wen \reg_4_dest24__wen \reg_3_dest23__wen \reg_2_dest22__wen \reg_1_dest21__wen \reg_0_dest20__wen } 8'00000000 + connect \reg_7_dest17__data_i \data_i + connect \reg_6_dest16__data_i \data_i + connect \reg_5_dest15__data_i \data_i + connect \reg_4_dest14__data_i \data_i + connect \reg_3_dest13__data_i \data_i + connect \reg_2_dest12__data_i \data_i + connect \reg_1_dest11__data_i \data_i + connect \reg_0_dest10__data_i \data_i + connect { \reg_7_dest17__wen \reg_6_dest16__wen \reg_5_dest15__wen \reg_4_dest14__wen \reg_3_dest13__wen \reg_2_dest12__wen \reg_1_dest11__wen \reg_0_dest10__wen } \wen + connect { \reg_7_src37__ren \reg_6_src36__ren \reg_5_src35__ren \reg_4_src34__ren \reg_3_src33__ren \reg_2_src32__ren \reg_1_src31__ren \reg_0_src30__ren } \src3__ren + connect { \reg_7_src27__ren \reg_6_src26__ren \reg_5_src25__ren \reg_4_src24__ren \reg_3_src23__ren \reg_2_src22__ren \reg_1_src21__ren \reg_0_src20__ren } \src2__ren + connect { \reg_7_src17__ren \reg_6_src16__ren \reg_5_src15__ren \reg_4_src14__ren \reg_3_src13__ren \reg_2_src12__ren \reg_1_src11__ren \reg_0_src10__ren } \src1__ren +end +attribute \src "libresoc.v:48680.1-49731.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.cr0" +attribute \generator "nMigen" +module \cr0 + attribute \src "libresoc.v:49332.3-49333.25" + wire $0\all_rd_dly[0:0] + attribute \src "libresoc.v:49505.3-49516.6" + wire width 12 $0\alu_cr0_cr_op__fn_unit$next[11:0]$3188 + attribute \src "libresoc.v:49304.3-49305.61" + wire width 12 $0\alu_cr0_cr_op__fn_unit[11:0] + attribute \src "libresoc.v:49505.3-49516.6" + wire width 32 $0\alu_cr0_cr_op__insn$next[31:0]$3189 + attribute \src "libresoc.v:49306.3-49307.55" + wire width 32 $0\alu_cr0_cr_op__insn[31:0] + attribute \src "libresoc.v:49505.3-49516.6" + wire width 7 $0\alu_cr0_cr_op__insn_type$next[6:0]$3190 + attribute \src "libresoc.v:49302.3-49303.65" + wire width 7 $0\alu_cr0_cr_op__insn_type[6:0] + attribute \src "libresoc.v:49330.3-49331.39" + wire $0\alu_done_dly[0:0] + attribute \src "libresoc.v:49652.3-49660.6" + wire $0\alu_l_r_alu$next[0:0]$3240 + attribute \src "libresoc.v:49274.3-49275.39" + wire $0\alu_l_r_alu[0:0] + attribute \src "libresoc.v:49643.3-49651.6" + wire $0\alui_l_r_alui$next[0:0]$3237 + attribute \src "libresoc.v:49276.3-49277.43" + wire $0\alui_l_r_alui[0:0] + attribute \src "libresoc.v:49517.3-49538.6" + wire width 64 $0\data_r0__o$next[63:0]$3195 + attribute \src "libresoc.v:49298.3-49299.37" + wire width 64 $0\data_r0__o[63:0] + attribute \src "libresoc.v:49517.3-49538.6" + wire $0\data_r0__o_ok$next[0:0]$3196 + attribute \src "libresoc.v:49300.3-49301.43" + wire $0\data_r0__o_ok[0:0] + attribute \src "libresoc.v:49539.3-49560.6" + wire width 32 $0\data_r1__full_cr$next[31:0]$3203 + attribute \src "libresoc.v:49294.3-49295.49" + wire width 32 $0\data_r1__full_cr[31:0] + attribute \src "libresoc.v:49539.3-49560.6" + wire $0\data_r1__full_cr_ok$next[0:0]$3204 + attribute \src "libresoc.v:49296.3-49297.55" + wire $0\data_r1__full_cr_ok[0:0] + attribute \src "libresoc.v:49561.3-49582.6" + wire width 4 $0\data_r2__cr_a$next[3:0]$3211 + attribute \src "libresoc.v:49290.3-49291.43" + wire width 4 $0\data_r2__cr_a[3:0] + attribute \src "libresoc.v:49561.3-49582.6" + wire $0\data_r2__cr_a_ok$next[0:0]$3212 + attribute \src "libresoc.v:49292.3-49293.49" + wire $0\data_r2__cr_a_ok[0:0] + attribute \src "libresoc.v:49661.3-49670.6" + wire width 64 $0\dest1_o[63:0] + attribute \src "libresoc.v:49671.3-49680.6" + wire width 32 $0\dest2_o[31:0] + attribute \src "libresoc.v:49681.3-49690.6" + wire width 4 $0\dest3_o[3:0] + attribute \src "libresoc.v:48681.7-48681.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:49460.3-49468.6" + wire $0\opc_l_r_opc$next[0:0]$3173 + attribute \src "libresoc.v:49316.3-49317.39" + wire $0\opc_l_r_opc[0:0] + attribute \src "libresoc.v:49451.3-49459.6" + wire $0\opc_l_s_opc$next[0:0]$3170 + attribute \src "libresoc.v:49318.3-49319.39" + wire $0\opc_l_s_opc[0:0] + attribute \src "libresoc.v:49691.3-49699.6" + wire width 3 $0\prev_wr_go$next[2:0]$3246 + attribute \src "libresoc.v:49328.3-49329.37" + wire width 3 $0\prev_wr_go[2:0] + attribute \src "libresoc.v:49405.3-49414.6" + wire $0\req_done[0:0] + attribute \src "libresoc.v:49496.3-49504.6" + wire width 3 $0\req_l_r_req$next[2:0]$3185 + attribute \src "libresoc.v:49308.3-49309.39" + wire width 3 $0\req_l_r_req[2:0] + attribute \src "libresoc.v:49487.3-49495.6" + wire width 3 $0\req_l_s_req$next[2:0]$3182 + attribute \src "libresoc.v:49310.3-49311.39" + wire width 3 $0\req_l_s_req[2:0] + attribute \src "libresoc.v:49424.3-49432.6" + wire $0\rok_l_r_rdok$next[0:0]$3161 + attribute \src "libresoc.v:49324.3-49325.41" + wire $0\rok_l_r_rdok[0:0] + attribute \src "libresoc.v:49415.3-49423.6" + wire $0\rok_l_s_rdok$next[0:0]$3158 + attribute \src "libresoc.v:49326.3-49327.41" + wire $0\rok_l_s_rdok[0:0] + attribute \src "libresoc.v:49442.3-49450.6" + wire $0\rst_l_r_rst$next[0:0]$3167 + attribute \src "libresoc.v:49320.3-49321.39" + wire $0\rst_l_r_rst[0:0] + attribute \src "libresoc.v:49433.3-49441.6" + wire $0\rst_l_s_rst$next[0:0]$3164 + attribute \src "libresoc.v:49322.3-49323.39" + wire $0\rst_l_s_rst[0:0] + attribute \src "libresoc.v:49478.3-49486.6" + wire width 6 $0\src_l_r_src$next[5:0]$3179 + attribute \src "libresoc.v:49312.3-49313.39" + wire width 6 $0\src_l_r_src[5:0] + attribute \src "libresoc.v:49469.3-49477.6" + wire width 6 $0\src_l_s_src$next[5:0]$3176 + attribute \src "libresoc.v:49314.3-49315.39" + wire width 6 $0\src_l_s_src[5:0] + attribute \src "libresoc.v:49583.3-49592.6" + wire width 64 $0\src_r0$next[63:0]$3219 + attribute \src "libresoc.v:49288.3-49289.29" + wire width 64 $0\src_r0[63:0] + attribute \src "libresoc.v:49593.3-49602.6" + wire width 64 $0\src_r1$next[63:0]$3222 + attribute \src "libresoc.v:49286.3-49287.29" + wire width 64 $0\src_r1[63:0] + attribute \src "libresoc.v:49603.3-49612.6" + wire width 32 $0\src_r2$next[31:0]$3225 + attribute \src "libresoc.v:49284.3-49285.29" + wire width 32 $0\src_r2[31:0] + attribute \src "libresoc.v:49613.3-49622.6" + wire width 4 $0\src_r3$next[3:0]$3228 + attribute \src "libresoc.v:49282.3-49283.29" + wire width 4 $0\src_r3[3:0] + attribute \src "libresoc.v:49623.3-49632.6" + wire width 4 $0\src_r4$next[3:0]$3231 + attribute \src "libresoc.v:49280.3-49281.29" + wire width 4 $0\src_r4[3:0] + attribute \src "libresoc.v:49633.3-49642.6" + wire width 4 $0\src_r5$next[3:0]$3234 + attribute \src "libresoc.v:49278.3-49279.29" + wire width 4 $0\src_r5[3:0] + attribute \src "libresoc.v:48799.7-48799.24" + wire $1\all_rd_dly[0:0] + attribute \src "libresoc.v:49505.3-49516.6" + wire width 12 $1\alu_cr0_cr_op__fn_unit$next[11:0]$3191 + attribute \src "libresoc.v:48828.14-48828.46" + wire width 12 $1\alu_cr0_cr_op__fn_unit[11:0] + attribute \src "libresoc.v:49505.3-49516.6" + wire width 32 $1\alu_cr0_cr_op__insn$next[31:0]$3192 + attribute \src "libresoc.v:48832.14-48832.41" + wire width 32 $1\alu_cr0_cr_op__insn[31:0] + attribute \src "libresoc.v:49505.3-49516.6" + wire width 7 $1\alu_cr0_cr_op__insn_type$next[6:0]$3193 + attribute \src "libresoc.v:48910.13-48910.45" + wire width 7 $1\alu_cr0_cr_op__insn_type[6:0] + attribute \src "libresoc.v:48934.7-48934.26" + wire $1\alu_done_dly[0:0] + attribute \src "libresoc.v:49652.3-49660.6" + wire $1\alu_l_r_alu$next[0:0]$3241 + attribute \src "libresoc.v:48942.7-48942.25" + wire $1\alu_l_r_alu[0:0] + attribute \src "libresoc.v:49643.3-49651.6" + wire $1\alui_l_r_alui$next[0:0]$3238 + attribute \src "libresoc.v:48954.7-48954.27" + wire $1\alui_l_r_alui[0:0] + attribute \src "libresoc.v:49517.3-49538.6" + wire width 64 $1\data_r0__o$next[63:0]$3197 + attribute \src "libresoc.v:48988.14-48988.47" + wire width 64 $1\data_r0__o[63:0] + attribute \src "libresoc.v:49517.3-49538.6" + wire $1\data_r0__o_ok$next[0:0]$3198 + attribute \src "libresoc.v:48992.7-48992.27" + wire $1\data_r0__o_ok[0:0] + attribute \src "libresoc.v:49539.3-49560.6" + wire width 32 $1\data_r1__full_cr$next[31:0]$3205 + attribute \src "libresoc.v:48996.14-48996.38" + wire width 32 $1\data_r1__full_cr[31:0] + attribute \src "libresoc.v:49539.3-49560.6" + wire $1\data_r1__full_cr_ok$next[0:0]$3206 + attribute \src "libresoc.v:49000.7-49000.33" + wire $1\data_r1__full_cr_ok[0:0] + attribute \src "libresoc.v:49561.3-49582.6" + wire width 4 $1\data_r2__cr_a$next[3:0]$3213 + attribute \src "libresoc.v:49004.13-49004.33" + wire width 4 $1\data_r2__cr_a[3:0] + attribute \src "libresoc.v:49561.3-49582.6" + wire $1\data_r2__cr_a_ok$next[0:0]$3214 + attribute \src "libresoc.v:49008.7-49008.30" + wire $1\data_r2__cr_a_ok[0:0] + attribute \src "libresoc.v:49661.3-49670.6" + wire width 64 $1\dest1_o[63:0] + attribute \src "libresoc.v:49671.3-49680.6" + wire width 32 $1\dest2_o[31:0] + attribute \src "libresoc.v:49681.3-49690.6" + wire width 4 $1\dest3_o[3:0] + attribute \src "libresoc.v:49460.3-49468.6" + wire $1\opc_l_r_opc$next[0:0]$3174 + attribute \src "libresoc.v:49027.7-49027.25" + wire $1\opc_l_r_opc[0:0] + attribute \src "libresoc.v:49451.3-49459.6" + wire $1\opc_l_s_opc$next[0:0]$3171 + attribute \src "libresoc.v:49031.7-49031.25" + wire $1\opc_l_s_opc[0:0] + attribute \src "libresoc.v:49691.3-49699.6" + wire width 3 $1\prev_wr_go$next[2:0]$3247 + attribute \src "libresoc.v:49128.13-49128.30" + wire width 3 $1\prev_wr_go[2:0] + attribute \src "libresoc.v:49405.3-49414.6" + wire $1\req_done[0:0] + attribute \src "libresoc.v:49496.3-49504.6" + wire width 3 $1\req_l_r_req$next[2:0]$3186 + attribute \src "libresoc.v:49136.13-49136.31" + wire width 3 $1\req_l_r_req[2:0] + attribute \src "libresoc.v:49487.3-49495.6" + wire width 3 $1\req_l_s_req$next[2:0]$3183 + attribute \src "libresoc.v:49140.13-49140.31" + wire width 3 $1\req_l_s_req[2:0] + attribute \src "libresoc.v:49424.3-49432.6" + wire $1\rok_l_r_rdok$next[0:0]$3162 + attribute \src "libresoc.v:49152.7-49152.26" + wire $1\rok_l_r_rdok[0:0] + attribute \src "libresoc.v:49415.3-49423.6" + wire $1\rok_l_s_rdok$next[0:0]$3159 + attribute \src "libresoc.v:49156.7-49156.26" + wire $1\rok_l_s_rdok[0:0] + attribute \src "libresoc.v:49442.3-49450.6" + wire $1\rst_l_r_rst$next[0:0]$3168 + attribute \src "libresoc.v:49160.7-49160.25" + wire $1\rst_l_r_rst[0:0] + attribute \src "libresoc.v:49433.3-49441.6" + wire $1\rst_l_s_rst$next[0:0]$3165 + attribute \src "libresoc.v:49164.7-49164.25" + wire $1\rst_l_s_rst[0:0] + attribute \src "libresoc.v:49478.3-49486.6" + wire width 6 $1\src_l_r_src$next[5:0]$3180 + attribute \src "libresoc.v:49184.13-49184.32" + wire width 6 $1\src_l_r_src[5:0] + attribute \src "libresoc.v:49469.3-49477.6" + wire width 6 $1\src_l_s_src$next[5:0]$3177 + attribute \src "libresoc.v:49188.13-49188.32" + wire width 6 $1\src_l_s_src[5:0] + attribute \src "libresoc.v:49583.3-49592.6" + wire width 64 $1\src_r0$next[63:0]$3220 + attribute \src "libresoc.v:49192.14-49192.43" + wire width 64 $1\src_r0[63:0] + attribute \src "libresoc.v:49593.3-49602.6" + wire width 64 $1\src_r1$next[63:0]$3223 + attribute \src "libresoc.v:49196.14-49196.43" + wire width 64 $1\src_r1[63:0] + attribute \src "libresoc.v:49603.3-49612.6" + wire width 32 $1\src_r2$next[31:0]$3226 + attribute \src "libresoc.v:49200.14-49200.28" + wire width 32 $1\src_r2[31:0] + attribute \src "libresoc.v:49613.3-49622.6" + wire width 4 $1\src_r3$next[3:0]$3229 + attribute \src "libresoc.v:49204.13-49204.26" + wire width 4 $1\src_r3[3:0] + attribute \src "libresoc.v:49623.3-49632.6" + wire width 4 $1\src_r4$next[3:0]$3232 + attribute \src "libresoc.v:49208.13-49208.26" + wire width 4 $1\src_r4[3:0] + attribute \src "libresoc.v:49633.3-49642.6" + wire width 4 $1\src_r5$next[3:0]$3235 + attribute \src "libresoc.v:49212.13-49212.26" + wire width 4 $1\src_r5[3:0] + attribute \src "libresoc.v:49517.3-49538.6" + wire width 64 $2\data_r0__o$next[63:0]$3199 + attribute \src "libresoc.v:49517.3-49538.6" + wire $2\data_r0__o_ok$next[0:0]$3200 + attribute \src "libresoc.v:49539.3-49560.6" + wire width 32 $2\data_r1__full_cr$next[31:0]$3207 + attribute \src "libresoc.v:49539.3-49560.6" + wire $2\data_r1__full_cr_ok$next[0:0]$3208 + attribute \src "libresoc.v:49561.3-49582.6" + wire width 4 $2\data_r2__cr_a$next[3:0]$3215 + attribute \src "libresoc.v:49561.3-49582.6" + wire $2\data_r2__cr_a_ok$next[0:0]$3216 + attribute \src "libresoc.v:49517.3-49538.6" + wire $3\data_r0__o_ok$next[0:0]$3201 + attribute \src "libresoc.v:49539.3-49560.6" + wire $3\data_r1__full_cr_ok$next[0:0]$3209 + attribute \src "libresoc.v:49561.3-49582.6" + wire $3\data_r2__cr_a_ok$next[0:0]$3217 + attribute \src "libresoc.v:49218.18-49218.112" + wire width 6 $and$libresoc.v:49218$3070_Y + attribute \src "libresoc.v:49219.19-49219.125" + wire $and$libresoc.v:49219$3071_Y + attribute \src "libresoc.v:49220.19-49220.125" + wire $and$libresoc.v:49220$3072_Y + attribute \src "libresoc.v:49221.19-49221.125" + wire $and$libresoc.v:49221$3073_Y + attribute \src "libresoc.v:49222.19-49222.141" + wire width 3 $and$libresoc.v:49222$3074_Y + attribute \src "libresoc.v:49223.19-49223.121" + wire width 3 $and$libresoc.v:49223$3075_Y + attribute \src "libresoc.v:49224.19-49224.127" + wire $and$libresoc.v:49224$3076_Y + attribute \src "libresoc.v:49225.19-49225.127" + wire $and$libresoc.v:49225$3077_Y + attribute \src "libresoc.v:49226.19-49226.127" + wire $and$libresoc.v:49226$3078_Y + attribute \src "libresoc.v:49227.18-49227.110" + wire $and$libresoc.v:49227$3079_Y + attribute \src "libresoc.v:49229.18-49229.98" + wire $and$libresoc.v:49229$3081_Y + attribute \src "libresoc.v:49231.18-49231.100" + wire $and$libresoc.v:49231$3083_Y + attribute \src "libresoc.v:49232.18-49232.149" + wire width 3 $and$libresoc.v:49232$3084_Y + attribute \src "libresoc.v:49234.18-49234.119" + wire width 3 $and$libresoc.v:49234$3086_Y + attribute \src "libresoc.v:49237.18-49237.116" + wire $and$libresoc.v:49237$3089_Y + attribute \src "libresoc.v:49241.17-49241.123" + wire $and$libresoc.v:49241$3093_Y + attribute \src "libresoc.v:49243.18-49243.113" + wire $and$libresoc.v:49243$3095_Y + attribute \src "libresoc.v:49244.18-49244.125" + wire width 3 $and$libresoc.v:49244$3096_Y + attribute \src "libresoc.v:49246.18-49246.112" + wire $and$libresoc.v:49246$3098_Y + attribute \src "libresoc.v:49248.18-49248.125" + wire $and$libresoc.v:49248$3100_Y + attribute \src "libresoc.v:49249.18-49249.125" + wire $and$libresoc.v:49249$3101_Y + attribute \src "libresoc.v:49250.18-49250.117" + wire $and$libresoc.v:49250$3102_Y + attribute \src "libresoc.v:49255.18-49255.129" + wire $and$libresoc.v:49255$3107_Y + attribute \src "libresoc.v:49256.18-49256.124" + wire width 3 $and$libresoc.v:49256$3108_Y + attribute \src "libresoc.v:49259.18-49259.116" + wire $and$libresoc.v:49259$3111_Y + attribute \src "libresoc.v:49260.18-49260.122" + wire $and$libresoc.v:49260$3112_Y + attribute \src "libresoc.v:49261.18-49261.119" + wire $and$libresoc.v:49261$3113_Y + attribute \src "libresoc.v:49269.18-49269.133" + wire $and$libresoc.v:49269$3121_Y + attribute \src "libresoc.v:49270.18-49270.131" + wire $and$libresoc.v:49270$3122_Y + attribute \src "libresoc.v:49271.18-49271.182" + wire width 6 $and$libresoc.v:49271$3123_Y + attribute \src "libresoc.v:49272.18-49272.113" + wire width 6 $and$libresoc.v:49272$3124_Y + attribute \src "libresoc.v:49245.18-49245.113" + wire $eq$libresoc.v:49245$3097_Y + attribute \src "libresoc.v:49247.18-49247.119" + wire $eq$libresoc.v:49247$3099_Y + attribute \src "libresoc.v:49228.18-49228.97" + wire $not$libresoc.v:49228$3080_Y + attribute \src "libresoc.v:49230.18-49230.99" + wire $not$libresoc.v:49230$3082_Y + attribute \src "libresoc.v:49233.18-49233.113" + wire width 3 $not$libresoc.v:49233$3085_Y + attribute \src "libresoc.v:49236.18-49236.106" + wire $not$libresoc.v:49236$3088_Y + attribute \src "libresoc.v:49242.18-49242.119" + wire $not$libresoc.v:49242$3094_Y + attribute \src "libresoc.v:49257.17-49257.113" + wire width 6 $not$libresoc.v:49257$3109_Y + attribute \src "libresoc.v:49273.18-49273.114" + wire width 6 $not$libresoc.v:49273$3125_Y + attribute \src "libresoc.v:49240.18-49240.112" + wire $or$libresoc.v:49240$3092_Y + attribute \src "libresoc.v:49251.18-49251.122" + wire $or$libresoc.v:49251$3103_Y + attribute \src "libresoc.v:49252.18-49252.124" + wire $or$libresoc.v:49252$3104_Y + attribute \src "libresoc.v:49253.18-49253.155" + wire width 3 $or$libresoc.v:49253$3105_Y + attribute \src "libresoc.v:49254.18-49254.194" + wire width 6 $or$libresoc.v:49254$3106_Y + attribute \src "libresoc.v:49258.18-49258.120" + wire width 3 $or$libresoc.v:49258$3110_Y + attribute \src "libresoc.v:49268.17-49268.117" + wire width 6 $or$libresoc.v:49268$3120_Y + attribute \src "libresoc.v:49217.17-49217.104" + wire $reduce_and$libresoc.v:49217$3069_Y + attribute \src "libresoc.v:49235.18-49235.106" + wire $reduce_or$libresoc.v:49235$3087_Y + attribute \src "libresoc.v:49238.18-49238.113" + wire $reduce_or$libresoc.v:49238$3090_Y + attribute \src "libresoc.v:49239.18-49239.112" + wire $reduce_or$libresoc.v:49239$3091_Y + attribute \src "libresoc.v:49262.18-49262.118" + wire width 64 $ternary$libresoc.v:49262$3114_Y + attribute \src "libresoc.v:49263.18-49263.118" + wire width 64 $ternary$libresoc.v:49263$3115_Y + attribute \src "libresoc.v:49264.18-49264.118" + wire width 32 $ternary$libresoc.v:49264$3116_Y + attribute \src "libresoc.v:49265.18-49265.118" + wire width 4 $ternary$libresoc.v:49265$3117_Y + attribute \src "libresoc.v:49266.18-49266.118" + wire width 4 $ternary$libresoc.v:49266$3118_Y + attribute \src "libresoc.v:49267.18-49267.118" + wire width 4 $ternary$libresoc.v:49267$3119_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + wire \$101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + wire \$103 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + wire \$105 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" + wire width 3 \$107 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" + wire width 3 \$109 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + wire \$111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + wire \$113 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + wire \$115 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire \$17 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" + wire width 3 \$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + wire width 3 \$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + wire width 3 \$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + wire \$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + wire \$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + wire \$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + wire \$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + wire \$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + wire width 3 \$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + wire \$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + wire \$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + wire \$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + wire \$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + wire \$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + wire \$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" + wire \$57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" + wire \$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + wire width 6 \$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" + wire width 3 \$61 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" + wire width 6 \$63 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" + wire \$65 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" + wire width 3 \$67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" + wire width 3 \$69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + wire \$71 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + wire \$73 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + wire \$75 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 64 \$77 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 64 \$79 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + wire width 6 \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 32 \$81 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 4 \$83 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 4 \$85 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 4 \$87 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" + wire \$89 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" + wire \$91 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + wire width 6 \$93 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + wire width 6 \$95 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + wire width 6 \$97 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + wire width 6 \$99 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:187" + wire \all_rd + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire \all_rd_dly + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire \all_rd_dly$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:192" + wire \all_rd_pulse + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + wire \all_rd_rise + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \alu_cr0_cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 4 \alu_cr0_cr_a$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 4 \alu_cr0_cr_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 4 \alu_cr0_cr_c + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \alu_cr0_cr_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \alu_cr0_cr_op__fn_unit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \alu_cr0_cr_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \alu_cr0_cr_op__insn$next + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \alu_cr0_cr_op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \alu_cr0_cr_op__insn_type$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 32 \alu_cr0_full_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 32 \alu_cr0_full_cr$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire \alu_cr0_n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire \alu_cr0_n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \alu_cr0_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire \alu_cr0_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire \alu_cr0_p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \alu_cr0_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \alu_cr0_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:196" + wire \alu_done + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire \alu_done_dly + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire \alu_done_dly$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + wire \alu_done_rise + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire \alu_l_q_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \alu_l_r_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \alu_l_r_alu$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \alu_l_s_alu + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:197" + wire \alu_pulse + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198" + wire width 3 \alu_pulsem + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire \alui_l_q_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \alui_l_r_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \alui_l_r_alui$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \alui_l_s_alui + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 24 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 23 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 21 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" + wire output 5 \cu_busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:108" + wire \cu_done_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:104" + wire \cu_go_die_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" + wire input 4 \cu_issue_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 6 input 8 \cu_rd__go_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 6 output 7 \cu_rd__rel_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" + wire width 6 input 6 \cu_rdmaskn_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:102" + wire \cu_shadown_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 input 17 \cu_wr__go_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 output 16 \cu_wr__rel_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:97" + wire width 3 \cu_wrmask_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 64 \data_r0__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 64 \data_r0__o$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r0__o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r0__o_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 32 \data_r1__full_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 32 \data_r1__full_cr$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r1__full_cr_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r1__full_cr_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 4 \data_r2__cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 4 \data_r2__cr_a$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r2__cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r2__cr_a_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 18 \dest1_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 32 output 20 \dest2_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 4 output 22 \dest3_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 19 \full_cr_ok + attribute \src "libresoc.v:48681.7-48681.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 15 \o_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire \opc_l_q_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \opc_l_r_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \opc_l_r_opc$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \opc_l_s_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \opc_l_s_opc$next + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 2 \oper_i_alu_cr0__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 3 \oper_i_alu_cr0__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \oper_i_alu_cr0__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" + wire width 3 \prev_wr_go + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" + wire width 3 \prev_wr_go$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212" + wire \req_done + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 3 \req_l_q_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 3 \req_l_r_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 3 \req_l_r_req$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 3 \req_l_s_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 3 \req_l_s_req$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226" + wire \reset + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:229" + wire width 6 \reset_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:228" + wire width 3 \reset_w + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire \rok_l_q_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \rok_l_r_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \rok_l_r_rdok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \rok_l_s_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \rok_l_s_rdok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \rst_l_r_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \rst_l_r_rst$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \rst_l_s_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \rst_l_s_rst$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227" + wire \rst_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 9 \src1_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 10 \src2_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 32 input 11 \src3_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 4 input 12 \src4_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 4 input 13 \src5_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 4 input 14 \src6_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 6 \src_l_q_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 6 \src_l_r_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 6 \src_l_r_src$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 6 \src_l_s_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 6 \src_l_s_src$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 64 \src_r0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 64 \src_r0$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 64 \src_r1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 64 \src_r1$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 32 \src_r2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 32 \src_r2$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 4 \src_r3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 4 \src_r3$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 4 \src_r4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 4 \src_r4$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 4 \src_r5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 4 \src_r5$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" + wire \wr_any + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + cell $and $and$libresoc.v:49218$3070 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \$95 + connect \B \$97 + connect \Y $and$libresoc.v:49218$3070_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + cell $and $and$libresoc.v:49219$3071 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_busy_o + connect \B \cu_shadown_i + connect \Y $and$libresoc.v:49219$3071_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + cell $and $and$libresoc.v:49220$3072 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_busy_o + connect \B \cu_shadown_i + connect \Y $and$libresoc.v:49220$3072_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + cell $and $and$libresoc.v:49221$3073 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_busy_o + connect \B \cu_shadown_i + connect \Y $and$libresoc.v:49221$3073_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" + cell $and $and$libresoc.v:49222$3074 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \req_l_q_req + connect \B { \$101 \$103 \$105 } + connect \Y $and$libresoc.v:49222$3074_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" + cell $and $and$libresoc.v:49223$3075 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \$107 + connect \B \cu_wrmask_o + connect \Y $and$libresoc.v:49223$3075_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + cell $and $and$libresoc.v:49224$3076 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_wr__go_i [0] + connect \B \cu_busy_o + connect \Y $and$libresoc.v:49224$3076_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + cell $and $and$libresoc.v:49225$3077 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_wr__go_i [1] + connect \B \cu_busy_o + connect \Y $and$libresoc.v:49225$3077_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + cell $and $and$libresoc.v:49226$3078 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_wr__go_i [2] + connect \B \cu_busy_o + connect \Y $and$libresoc.v:49226$3078_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $and $and$libresoc.v:49227$3079 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \$5 + connect \Y $and$libresoc.v:49227$3079_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $and$libresoc.v:49229$3081 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \all_rd + connect \B \$13 + connect \Y $and$libresoc.v:49229$3081_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $and$libresoc.v:49231$3083 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_done + connect \B \$17 + connect \Y $and$libresoc.v:49231$3083_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" + cell $and $and$libresoc.v:49232$3084 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \cu_wr__go_i + connect \B { \cu_busy_o \cu_busy_o \cu_busy_o } + connect \Y $and$libresoc.v:49232$3084_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $and $and$libresoc.v:49234$3086 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \cu_wr__rel_o + connect \B \$25 + connect \Y $and$libresoc.v:49234$3086_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $and $and$libresoc.v:49237$3089 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_busy_o + connect \B \$23 + connect \Y $and$libresoc.v:49237$3089_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" + cell $and $and$libresoc.v:49241$3093 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_busy_o + connect \B \rok_l_q_rdok + connect \Y $and$libresoc.v:49241$3093_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + cell $and $and$libresoc.v:49243$3095 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_any + connect \B \$39 + connect \Y $and$libresoc.v:49243$3095_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + cell $and $and$libresoc.v:49244$3096 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \req_l_q_req + connect \B \cu_wrmask_o + connect \Y $and$libresoc.v:49244$3096_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + cell $and $and$libresoc.v:49246$3098 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$41 + connect \B \$45 + connect \Y $and$libresoc.v:49246$3098_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + cell $and $and$libresoc.v:49248$3100 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$49 + connect \B \alu_cr0_n_ready_i + connect \Y $and$libresoc.v:49248$3100_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + cell $and $and$libresoc.v:49249$3101 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$51 + connect \B \alu_cr0_n_valid_o + connect \Y $and$libresoc.v:49249$3101_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + cell $and $and$libresoc.v:49250$3102 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$53 + connect \B \cu_busy_o + connect \Y $and$libresoc.v:49250$3102_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" + cell $and $and$libresoc.v:49255$3107 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_cr0_n_valid_o + connect \B \cu_busy_o + connect \Y $and$libresoc.v:49255$3107_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" + cell $and $and$libresoc.v:49256$3108 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \alu_pulsem + connect \B \cu_wrmask_o + connect \Y $and$libresoc.v:49256$3108_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + cell $and $and$libresoc.v:49259$3111 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \o_ok + connect \B \cu_busy_o + connect \Y $and$libresoc.v:49259$3111_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + cell $and $and$libresoc.v:49260$3112 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \full_cr_ok + connect \B \cu_busy_o + connect \Y $and$libresoc.v:49260$3112_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + cell $and $and$libresoc.v:49261$3113 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cr_a_ok + connect \B \cu_busy_o + connect \Y $and$libresoc.v:49261$3113_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" + cell $and $and$libresoc.v:49269$3121 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_cr0_p_ready_o + connect \B \alui_l_q_alui + connect \Y $and$libresoc.v:49269$3121_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" + cell $and $and$libresoc.v:49270$3122 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_cr0_n_valid_o + connect \B \alu_l_q_alu + connect \Y $and$libresoc.v:49270$3122_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + cell $and $and$libresoc.v:49271$3123 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \src_l_q_src + connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } + connect \Y $and$libresoc.v:49271$3123_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + cell $and $and$libresoc.v:49272$3124 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \$93 + connect \B 6'111111 + connect \Y $and$libresoc.v:49272$3124_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + cell $eq $eq$libresoc.v:49245$3097 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$43 + connect \B 1'0 + connect \Y $eq$libresoc.v:49245$3097_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + cell $eq $eq$libresoc.v:49247$3099 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_wrmask_o + connect \B 1'0 + connect \Y $eq$libresoc.v:49247$3099_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $not$libresoc.v:49228$3080 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \all_rd_dly + connect \Y $not$libresoc.v:49228$3080_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $not$libresoc.v:49230$3082 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_done_dly + connect \Y $not$libresoc.v:49230$3082_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $not $not$libresoc.v:49233$3085 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \cu_wrmask_o + connect \Y $not$libresoc.v:49233$3085_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $not $not$libresoc.v:49236$3088 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$24 + connect \Y $not$libresoc.v:49236$3088_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + cell $not $not$libresoc.v:49242$3094 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_cr0_n_ready_i + connect \Y $not$libresoc.v:49242$3094_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $not $not$libresoc.v:49257$3109 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \cu_rd__rel_o + connect \Y $not$libresoc.v:49257$3109_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + cell $not $not$libresoc.v:49273$3125 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \cu_rdmaskn_i + connect \Y $not$libresoc.v:49273$3125_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $or $or$libresoc.v:49240$3092 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$33 + connect \B \$35 + connect \Y $or$libresoc.v:49240$3092_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" + cell $or $or$libresoc.v:49251$3103 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \req_done + connect \B \cu_go_die_i + connect \Y $or$libresoc.v:49251$3103_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" + cell $or $or$libresoc.v:49252$3104 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_issue_i + connect \B \cu_go_die_i + connect \Y $or$libresoc.v:49252$3104_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" + cell $or $or$libresoc.v:49253$3105 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \cu_wr__go_i + connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } + connect \Y $or$libresoc.v:49253$3105_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" + cell $or $or$libresoc.v:49254$3106 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \cu_rd__go_i + connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } + connect \Y $or$libresoc.v:49254$3106_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" + cell $or $or$libresoc.v:49258$3110 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \reset_w + connect \B \prev_wr_go + connect \Y $or$libresoc.v:49258$3110_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $or $or$libresoc.v:49268$3120 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \$6 + connect \B \cu_rd__go_i + connect \Y $or$libresoc.v:49268$3120_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $reduce_and $reduce_and$libresoc.v:49217$3069 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $reduce_and$libresoc.v:49217$3069_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $reduce_or $reduce_or$libresoc.v:49235$3087 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \$27 + connect \Y $reduce_or$libresoc.v:49235$3087_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $reduce_or $reduce_or$libresoc.v:49238$3090 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \cu_wr__go_i + connect \Y $reduce_or$libresoc.v:49238$3090_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $reduce_or $reduce_or$libresoc.v:49239$3091 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \prev_wr_go + connect \Y $reduce_or$libresoc.v:49239$3091_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $ternary$libresoc.v:49262$3114 + parameter \WIDTH 64 + connect \A \src_r0 + connect \B \src1_i + connect \S \src_l_q_src [0] + connect \Y $ternary$libresoc.v:49262$3114_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $ternary$libresoc.v:49263$3115 + parameter \WIDTH 64 + connect \A \src_r1 + connect \B \src2_i + connect \S \src_l_q_src [1] + connect \Y $ternary$libresoc.v:49263$3115_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $ternary$libresoc.v:49264$3116 + parameter \WIDTH 32 + connect \A \src_r2 + connect \B \src3_i + connect \S \src_l_q_src [2] + connect \Y $ternary$libresoc.v:49264$3116_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $ternary$libresoc.v:49265$3117 + parameter \WIDTH 4 + connect \A \src_r3 + connect \B \src4_i + connect \S \src_l_q_src [3] + connect \Y $ternary$libresoc.v:49265$3117_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $ternary$libresoc.v:49266$3118 + parameter \WIDTH 4 + connect \A \src_r4 + connect \B \src5_i + connect \S \src_l_q_src [4] + connect \Y $ternary$libresoc.v:49266$3118_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $ternary$libresoc.v:49267$3119 + parameter \WIDTH 4 + connect \A \src_r5 + connect \B \src6_i + connect \S \src_l_q_src [5] + connect \Y $ternary$libresoc.v:49267$3119_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:49334.11-49356.4" + cell \alu_cr0 \alu_cr0 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cr_a \alu_cr0_cr_a + connect \cr_a$2 \alu_cr0_cr_a$2 + connect \cr_a_ok \cr_a_ok + connect \cr_b \alu_cr0_cr_b + connect \cr_c \alu_cr0_cr_c + connect \cr_op__fn_unit \alu_cr0_cr_op__fn_unit + connect \cr_op__insn \alu_cr0_cr_op__insn + connect \cr_op__insn_type \alu_cr0_cr_op__insn_type + connect \full_cr \alu_cr0_full_cr + connect \full_cr$1 \alu_cr0_full_cr$1 + connect \full_cr_ok \full_cr_ok + connect \n_ready_i \alu_cr0_n_ready_i + connect \n_valid_o \alu_cr0_n_valid_o + connect \o \alu_cr0_o + connect \o_ok \o_ok + connect \p_ready_o \alu_cr0_p_ready_o + connect \p_valid_i \alu_cr0_p_valid_i + connect \ra \alu_cr0_ra + connect \rb \alu_cr0_rb + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:49357.14-49363.4" + cell \alu_l$16 \alu_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_alu \alu_l_q_alu + connect \r_alu \alu_l_r_alu + connect \s_alu \alu_l_s_alu + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:49364.15-49370.4" + cell \alui_l$15 \alui_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_alui \alui_l_q_alui + connect \r_alui \alui_l_r_alui + connect \s_alui \alui_l_s_alui + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:49371.14-49377.4" + cell \opc_l$11 \opc_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_opc \opc_l_q_opc + connect \r_opc \opc_l_r_opc + connect \s_opc \opc_l_s_opc + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:49378.14-49384.4" + cell \req_l$12 \req_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_req \req_l_q_req + connect \r_req \req_l_r_req + connect \s_req \req_l_s_req + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:49385.14-49391.4" + cell \rok_l$14 \rok_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_rdok \rok_l_q_rdok + connect \r_rdok \rok_l_r_rdok + connect \s_rdok \rok_l_s_rdok + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:49392.14-49397.4" + cell \rst_l$13 \rst_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \r_rst \rst_l_r_rst + connect \s_rst \rst_l_s_rst + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:49398.14-49404.4" + cell \src_l$10 \src_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_src \src_l_q_src + connect \r_src \src_l_r_src + connect \s_src \src_l_s_src + end + attribute \src "libresoc.v:48681.7-48681.20" + process $proc$libresoc.v:48681$3248 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:48799.7-48799.24" + process $proc$libresoc.v:48799$3249 + assign { } { } + assign $1\all_rd_dly[0:0] 1'0 + sync always + sync init + update \all_rd_dly $1\all_rd_dly[0:0] + end + attribute \src "libresoc.v:48828.14-48828.46" + process $proc$libresoc.v:48828$3250 + assign { } { } + assign $1\alu_cr0_cr_op__fn_unit[11:0] 12'000000000000 + sync always + sync init + update \alu_cr0_cr_op__fn_unit $1\alu_cr0_cr_op__fn_unit[11:0] + end + attribute \src "libresoc.v:48832.14-48832.41" + process $proc$libresoc.v:48832$3251 + assign { } { } + assign $1\alu_cr0_cr_op__insn[31:0] 0 + sync always + sync init + update \alu_cr0_cr_op__insn $1\alu_cr0_cr_op__insn[31:0] + end + attribute \src "libresoc.v:48910.13-48910.45" + process $proc$libresoc.v:48910$3252 + assign { } { } + assign $1\alu_cr0_cr_op__insn_type[6:0] 7'0000000 + sync always + sync init + update \alu_cr0_cr_op__insn_type $1\alu_cr0_cr_op__insn_type[6:0] + end + attribute \src "libresoc.v:48934.7-48934.26" + process $proc$libresoc.v:48934$3253 + assign { } { } + assign $1\alu_done_dly[0:0] 1'0 + sync always + sync init + update \alu_done_dly $1\alu_done_dly[0:0] + end + attribute \src "libresoc.v:48942.7-48942.25" + process $proc$libresoc.v:48942$3254 + assign { } { } + assign $1\alu_l_r_alu[0:0] 1'1 + sync always + sync init + update \alu_l_r_alu $1\alu_l_r_alu[0:0] + end + attribute \src "libresoc.v:48954.7-48954.27" + process $proc$libresoc.v:48954$3255 + assign { } { } + assign $1\alui_l_r_alui[0:0] 1'1 + sync always + sync init + update \alui_l_r_alui $1\alui_l_r_alui[0:0] + end + attribute \src "libresoc.v:48988.14-48988.47" + process $proc$libresoc.v:48988$3256 + assign { } { } + assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \data_r0__o $1\data_r0__o[63:0] + end + attribute \src "libresoc.v:48992.7-48992.27" + process $proc$libresoc.v:48992$3257 + assign { } { } + assign $1\data_r0__o_ok[0:0] 1'0 + sync always + sync init + update \data_r0__o_ok $1\data_r0__o_ok[0:0] + end + attribute \src "libresoc.v:48996.14-48996.38" + process $proc$libresoc.v:48996$3258 + assign { } { } + assign $1\data_r1__full_cr[31:0] 0 + sync always + sync init + update \data_r1__full_cr $1\data_r1__full_cr[31:0] + end + attribute \src "libresoc.v:49000.7-49000.33" + process $proc$libresoc.v:49000$3259 + assign { } { } + assign $1\data_r1__full_cr_ok[0:0] 1'0 + sync always + sync init + update \data_r1__full_cr_ok $1\data_r1__full_cr_ok[0:0] + end + attribute \src "libresoc.v:49004.13-49004.33" + process $proc$libresoc.v:49004$3260 + assign { } { } + assign $1\data_r2__cr_a[3:0] 4'0000 + sync always + sync init + update \data_r2__cr_a $1\data_r2__cr_a[3:0] + end + attribute \src "libresoc.v:49008.7-49008.30" + process $proc$libresoc.v:49008$3261 + assign { } { } + assign $1\data_r2__cr_a_ok[0:0] 1'0 + sync always + sync init + update \data_r2__cr_a_ok $1\data_r2__cr_a_ok[0:0] + end + attribute \src "libresoc.v:49027.7-49027.25" + process $proc$libresoc.v:49027$3262 + assign { } { } + assign $1\opc_l_r_opc[0:0] 1'1 + sync always + sync init + update \opc_l_r_opc $1\opc_l_r_opc[0:0] + end + attribute \src "libresoc.v:49031.7-49031.25" + process $proc$libresoc.v:49031$3263 + assign { } { } + assign $1\opc_l_s_opc[0:0] 1'0 + sync always + sync init + update \opc_l_s_opc $1\opc_l_s_opc[0:0] + end + attribute \src "libresoc.v:49128.13-49128.30" + process $proc$libresoc.v:49128$3264 + assign { } { } + assign $1\prev_wr_go[2:0] 3'000 + sync always + sync init + update \prev_wr_go $1\prev_wr_go[2:0] + end + attribute \src "libresoc.v:49136.13-49136.31" + process $proc$libresoc.v:49136$3265 + assign { } { } + assign $1\req_l_r_req[2:0] 3'111 + sync always + sync init + update \req_l_r_req $1\req_l_r_req[2:0] + end + attribute \src "libresoc.v:49140.13-49140.31" + process $proc$libresoc.v:49140$3266 + assign { } { } + assign $1\req_l_s_req[2:0] 3'000 + sync always + sync init + update \req_l_s_req $1\req_l_s_req[2:0] + end + attribute \src "libresoc.v:49152.7-49152.26" + process $proc$libresoc.v:49152$3267 + assign { } { } + assign $1\rok_l_r_rdok[0:0] 1'1 + sync always + sync init + update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] + end + attribute \src "libresoc.v:49156.7-49156.26" + process $proc$libresoc.v:49156$3268 + assign { } { } + assign $1\rok_l_s_rdok[0:0] 1'0 + sync always + sync init + update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] + end + attribute \src "libresoc.v:49160.7-49160.25" + process $proc$libresoc.v:49160$3269 + assign { } { } + assign $1\rst_l_r_rst[0:0] 1'1 + sync always + sync init + update \rst_l_r_rst $1\rst_l_r_rst[0:0] + end + attribute \src "libresoc.v:49164.7-49164.25" + process $proc$libresoc.v:49164$3270 + assign { } { } + assign $1\rst_l_s_rst[0:0] 1'0 + sync always + sync init + update \rst_l_s_rst $1\rst_l_s_rst[0:0] + end + attribute \src "libresoc.v:49184.13-49184.32" + process $proc$libresoc.v:49184$3271 + assign { } { } + assign $1\src_l_r_src[5:0] 6'111111 + sync always + sync init + update \src_l_r_src $1\src_l_r_src[5:0] + end + attribute \src "libresoc.v:49188.13-49188.32" + process $proc$libresoc.v:49188$3272 + assign { } { } + assign $1\src_l_s_src[5:0] 6'000000 + sync always + sync init + update \src_l_s_src $1\src_l_s_src[5:0] + end + attribute \src "libresoc.v:49192.14-49192.43" + process $proc$libresoc.v:49192$3273 + assign { } { } + assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \src_r0 $1\src_r0[63:0] + end + attribute \src "libresoc.v:49196.14-49196.43" + process $proc$libresoc.v:49196$3274 + assign { } { } + assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \src_r1 $1\src_r1[63:0] + end + attribute \src "libresoc.v:49200.14-49200.28" + process $proc$libresoc.v:49200$3275 + assign { } { } + assign $1\src_r2[31:0] 0 + sync always + sync init + update \src_r2 $1\src_r2[31:0] + end + attribute \src "libresoc.v:49204.13-49204.26" + process $proc$libresoc.v:49204$3276 + assign { } { } + assign $1\src_r3[3:0] 4'0000 + sync always + sync init + update \src_r3 $1\src_r3[3:0] + end + attribute \src "libresoc.v:49208.13-49208.26" + process $proc$libresoc.v:49208$3277 + assign { } { } + assign $1\src_r4[3:0] 4'0000 + sync always + sync init + update \src_r4 $1\src_r4[3:0] + end + attribute \src "libresoc.v:49212.13-49212.26" + process $proc$libresoc.v:49212$3278 + assign { } { } + assign $1\src_r5[3:0] 4'0000 + sync always + sync init + update \src_r5 $1\src_r5[3:0] + end + attribute \src "libresoc.v:49274.3-49275.39" + process $proc$libresoc.v:49274$3126 + assign { } { } + assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next + sync posedge \coresync_clk + update \alu_l_r_alu $0\alu_l_r_alu[0:0] + end + attribute \src "libresoc.v:49276.3-49277.43" + process $proc$libresoc.v:49276$3127 + assign { } { } + assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next + sync posedge \coresync_clk + update \alui_l_r_alui $0\alui_l_r_alui[0:0] + end + attribute \src "libresoc.v:49278.3-49279.29" + process $proc$libresoc.v:49278$3128 + assign { } { } + assign $0\src_r5[3:0] \src_r5$next + sync posedge \coresync_clk + update \src_r5 $0\src_r5[3:0] + end + attribute \src "libresoc.v:49280.3-49281.29" + process $proc$libresoc.v:49280$3129 + assign { } { } + assign $0\src_r4[3:0] \src_r4$next + sync posedge \coresync_clk + update \src_r4 $0\src_r4[3:0] + end + attribute \src "libresoc.v:49282.3-49283.29" + process $proc$libresoc.v:49282$3130 + assign { } { } + assign $0\src_r3[3:0] \src_r3$next + sync posedge \coresync_clk + update \src_r3 $0\src_r3[3:0] + end + attribute \src "libresoc.v:49284.3-49285.29" + process $proc$libresoc.v:49284$3131 + assign { } { } + assign $0\src_r2[31:0] \src_r2$next + sync posedge \coresync_clk + update \src_r2 $0\src_r2[31:0] + end + attribute \src "libresoc.v:49286.3-49287.29" + process $proc$libresoc.v:49286$3132 + assign { } { } + assign $0\src_r1[63:0] \src_r1$next + sync posedge \coresync_clk + update \src_r1 $0\src_r1[63:0] + end + attribute \src "libresoc.v:49288.3-49289.29" + process $proc$libresoc.v:49288$3133 + assign { } { } + assign $0\src_r0[63:0] \src_r0$next + sync posedge \coresync_clk + update \src_r0 $0\src_r0[63:0] + end + attribute \src "libresoc.v:49290.3-49291.43" + process $proc$libresoc.v:49290$3134 + assign { } { } + assign $0\data_r2__cr_a[3:0] \data_r2__cr_a$next + sync posedge \coresync_clk + update \data_r2__cr_a $0\data_r2__cr_a[3:0] + end + attribute \src "libresoc.v:49292.3-49293.49" + process $proc$libresoc.v:49292$3135 + assign { } { } + assign $0\data_r2__cr_a_ok[0:0] \data_r2__cr_a_ok$next + sync posedge \coresync_clk + update \data_r2__cr_a_ok $0\data_r2__cr_a_ok[0:0] + end + attribute \src "libresoc.v:49294.3-49295.49" + process $proc$libresoc.v:49294$3136 + assign { } { } + assign $0\data_r1__full_cr[31:0] \data_r1__full_cr$next + sync posedge \coresync_clk + update \data_r1__full_cr $0\data_r1__full_cr[31:0] + end + attribute \src "libresoc.v:49296.3-49297.55" + process $proc$libresoc.v:49296$3137 + assign { } { } + assign $0\data_r1__full_cr_ok[0:0] \data_r1__full_cr_ok$next + sync posedge \coresync_clk + update \data_r1__full_cr_ok $0\data_r1__full_cr_ok[0:0] + end + attribute \src "libresoc.v:49298.3-49299.37" + process $proc$libresoc.v:49298$3138 + assign { } { } + assign $0\data_r0__o[63:0] \data_r0__o$next + sync posedge \coresync_clk + update \data_r0__o $0\data_r0__o[63:0] + end + attribute \src "libresoc.v:49300.3-49301.43" + process $proc$libresoc.v:49300$3139 + assign { } { } + assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next + sync posedge \coresync_clk + update \data_r0__o_ok $0\data_r0__o_ok[0:0] + end + attribute \src "libresoc.v:49302.3-49303.65" + process $proc$libresoc.v:49302$3140 + assign { } { } + assign $0\alu_cr0_cr_op__insn_type[6:0] \alu_cr0_cr_op__insn_type$next + sync posedge \coresync_clk + update \alu_cr0_cr_op__insn_type $0\alu_cr0_cr_op__insn_type[6:0] + end + attribute \src "libresoc.v:49304.3-49305.61" + process $proc$libresoc.v:49304$3141 + assign { } { } + assign $0\alu_cr0_cr_op__fn_unit[11:0] \alu_cr0_cr_op__fn_unit$next + sync posedge \coresync_clk + update \alu_cr0_cr_op__fn_unit $0\alu_cr0_cr_op__fn_unit[11:0] + end + attribute \src "libresoc.v:49306.3-49307.55" + process $proc$libresoc.v:49306$3142 + assign { } { } + assign $0\alu_cr0_cr_op__insn[31:0] \alu_cr0_cr_op__insn$next + sync posedge \coresync_clk + update \alu_cr0_cr_op__insn $0\alu_cr0_cr_op__insn[31:0] + end + attribute \src "libresoc.v:49308.3-49309.39" + process $proc$libresoc.v:49308$3143 + assign { } { } + assign $0\req_l_r_req[2:0] \req_l_r_req$next + sync posedge \coresync_clk + update \req_l_r_req $0\req_l_r_req[2:0] + end + attribute \src "libresoc.v:49310.3-49311.39" + process $proc$libresoc.v:49310$3144 + assign { } { } + assign $0\req_l_s_req[2:0] \req_l_s_req$next + sync posedge \coresync_clk + update \req_l_s_req $0\req_l_s_req[2:0] + end + attribute \src "libresoc.v:49312.3-49313.39" + process $proc$libresoc.v:49312$3145 + assign { } { } + assign $0\src_l_r_src[5:0] \src_l_r_src$next + sync posedge \coresync_clk + update \src_l_r_src $0\src_l_r_src[5:0] + end + attribute \src "libresoc.v:49314.3-49315.39" + process $proc$libresoc.v:49314$3146 + assign { } { } + assign $0\src_l_s_src[5:0] \src_l_s_src$next + sync posedge \coresync_clk + update \src_l_s_src $0\src_l_s_src[5:0] + end + attribute \src "libresoc.v:49316.3-49317.39" + process $proc$libresoc.v:49316$3147 + assign { } { } + assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next + sync posedge \coresync_clk + update \opc_l_r_opc $0\opc_l_r_opc[0:0] + end + attribute \src "libresoc.v:49318.3-49319.39" + process $proc$libresoc.v:49318$3148 + assign { } { } + assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next + sync posedge \coresync_clk + update \opc_l_s_opc $0\opc_l_s_opc[0:0] + end + attribute \src "libresoc.v:49320.3-49321.39" + process $proc$libresoc.v:49320$3149 + assign { } { } + assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next + sync posedge \coresync_clk + update \rst_l_r_rst $0\rst_l_r_rst[0:0] + end + attribute \src "libresoc.v:49322.3-49323.39" + process $proc$libresoc.v:49322$3150 + assign { } { } + assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next + sync posedge \coresync_clk + update \rst_l_s_rst $0\rst_l_s_rst[0:0] + end + attribute \src "libresoc.v:49324.3-49325.41" + process $proc$libresoc.v:49324$3151 + assign { } { } + assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next + sync posedge \coresync_clk + update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] + end + attribute \src "libresoc.v:49326.3-49327.41" + process $proc$libresoc.v:49326$3152 + assign { } { } + assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next + sync posedge \coresync_clk + update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] + end + attribute \src "libresoc.v:49328.3-49329.37" + process $proc$libresoc.v:49328$3153 + assign { } { } + assign $0\prev_wr_go[2:0] \prev_wr_go$next + sync posedge \coresync_clk + update \prev_wr_go $0\prev_wr_go[2:0] + end + attribute \src "libresoc.v:49330.3-49331.39" + process $proc$libresoc.v:49330$3154 + assign { } { } + assign $0\alu_done_dly[0:0] \alu_cr0_n_valid_o + sync posedge \coresync_clk + update \alu_done_dly $0\alu_done_dly[0:0] + end + attribute \src "libresoc.v:49332.3-49333.25" + process $proc$libresoc.v:49332$3155 + assign { } { } + assign $0\all_rd_dly[0:0] \$11 + sync posedge \coresync_clk + update \all_rd_dly $0\all_rd_dly[0:0] + end + attribute \src "libresoc.v:49405.3-49414.6" + process $proc$libresoc.v:49405$3156 + assign { } { } + assign { } { } + assign $0\req_done[0:0] $1\req_done[0:0] + attribute \src "libresoc.v:49406.5-49406.29" + switch \initial + attribute \src "libresoc.v:49406.9-49406.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + switch \$55 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\req_done[0:0] 1'1 + case + assign $1\req_done[0:0] \$47 + end + sync always + update \req_done $0\req_done[0:0] + end + attribute \src "libresoc.v:49415.3-49423.6" + process $proc$libresoc.v:49415$3157 + assign { } { } + assign { } { } + assign $0\rok_l_s_rdok$next[0:0]$3158 $1\rok_l_s_rdok$next[0:0]$3159 + attribute \src "libresoc.v:49416.5-49416.29" + switch \initial + attribute \src "libresoc.v:49416.9-49416.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rok_l_s_rdok$next[0:0]$3159 1'0 + case + assign $1\rok_l_s_rdok$next[0:0]$3159 \cu_issue_i + end + sync always + update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$3158 + end + attribute \src "libresoc.v:49424.3-49432.6" + process $proc$libresoc.v:49424$3160 + assign { } { } + assign { } { } + assign $0\rok_l_r_rdok$next[0:0]$3161 $1\rok_l_r_rdok$next[0:0]$3162 + attribute \src "libresoc.v:49425.5-49425.29" + switch \initial + attribute \src "libresoc.v:49425.9-49425.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rok_l_r_rdok$next[0:0]$3162 1'1 + case + assign $1\rok_l_r_rdok$next[0:0]$3162 \$65 + end + sync always + update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$3161 + end + attribute \src "libresoc.v:49433.3-49441.6" + process $proc$libresoc.v:49433$3163 + assign { } { } + assign { } { } + assign $0\rst_l_s_rst$next[0:0]$3164 $1\rst_l_s_rst$next[0:0]$3165 + attribute \src "libresoc.v:49434.5-49434.29" + switch \initial + attribute \src "libresoc.v:49434.9-49434.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rst_l_s_rst$next[0:0]$3165 1'0 + case + assign $1\rst_l_s_rst$next[0:0]$3165 \all_rd + end + sync always + update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$3164 + end + attribute \src "libresoc.v:49442.3-49450.6" + process $proc$libresoc.v:49442$3166 + assign { } { } + assign { } { } + assign $0\rst_l_r_rst$next[0:0]$3167 $1\rst_l_r_rst$next[0:0]$3168 + attribute \src "libresoc.v:49443.5-49443.29" + switch \initial + attribute \src "libresoc.v:49443.9-49443.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rst_l_r_rst$next[0:0]$3168 1'1 + case + assign $1\rst_l_r_rst$next[0:0]$3168 \rst_r + end + sync always + update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$3167 + end + attribute \src "libresoc.v:49451.3-49459.6" + process $proc$libresoc.v:49451$3169 + assign { } { } + assign { } { } + assign $0\opc_l_s_opc$next[0:0]$3170 $1\opc_l_s_opc$next[0:0]$3171 + attribute \src "libresoc.v:49452.5-49452.29" + switch \initial + attribute \src "libresoc.v:49452.9-49452.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\opc_l_s_opc$next[0:0]$3171 1'0 + case + assign $1\opc_l_s_opc$next[0:0]$3171 \cu_issue_i + end + sync always + update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$3170 + end + attribute \src "libresoc.v:49460.3-49468.6" + process $proc$libresoc.v:49460$3172 + assign { } { } + assign { } { } + assign $0\opc_l_r_opc$next[0:0]$3173 $1\opc_l_r_opc$next[0:0]$3174 + attribute \src "libresoc.v:49461.5-49461.29" + switch \initial + attribute \src "libresoc.v:49461.9-49461.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\opc_l_r_opc$next[0:0]$3174 1'1 + case + assign $1\opc_l_r_opc$next[0:0]$3174 \req_done + end + sync always + update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$3173 + end + attribute \src "libresoc.v:49469.3-49477.6" + process $proc$libresoc.v:49469$3175 + assign { } { } + assign { } { } + assign $0\src_l_s_src$next[5:0]$3176 $1\src_l_s_src$next[5:0]$3177 + attribute \src "libresoc.v:49470.5-49470.29" + switch \initial + attribute \src "libresoc.v:49470.9-49470.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_l_s_src$next[5:0]$3177 6'000000 + case + assign $1\src_l_s_src$next[5:0]$3177 { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i } + end + sync always + update \src_l_s_src$next $0\src_l_s_src$next[5:0]$3176 + end + attribute \src "libresoc.v:49478.3-49486.6" + process $proc$libresoc.v:49478$3178 + assign { } { } + assign { } { } + assign $0\src_l_r_src$next[5:0]$3179 $1\src_l_r_src$next[5:0]$3180 + attribute \src "libresoc.v:49479.5-49479.29" + switch \initial + attribute \src "libresoc.v:49479.9-49479.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_l_r_src$next[5:0]$3180 6'111111 + case + assign $1\src_l_r_src$next[5:0]$3180 \reset_r + end + sync always + update \src_l_r_src$next $0\src_l_r_src$next[5:0]$3179 + end + attribute \src "libresoc.v:49487.3-49495.6" + process $proc$libresoc.v:49487$3181 + assign { } { } + assign { } { } + assign $0\req_l_s_req$next[2:0]$3182 $1\req_l_s_req$next[2:0]$3183 + attribute \src "libresoc.v:49488.5-49488.29" + switch \initial + attribute \src "libresoc.v:49488.9-49488.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\req_l_s_req$next[2:0]$3183 3'000 + case + assign $1\req_l_s_req$next[2:0]$3183 \$67 + end + sync always + update \req_l_s_req$next $0\req_l_s_req$next[2:0]$3182 + end + attribute \src "libresoc.v:49496.3-49504.6" + process $proc$libresoc.v:49496$3184 + assign { } { } + assign { } { } + assign $0\req_l_r_req$next[2:0]$3185 $1\req_l_r_req$next[2:0]$3186 + attribute \src "libresoc.v:49497.5-49497.29" + switch \initial + attribute \src "libresoc.v:49497.9-49497.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\req_l_r_req$next[2:0]$3186 3'111 + case + assign $1\req_l_r_req$next[2:0]$3186 \$69 + end + sync always + update \req_l_r_req$next $0\req_l_r_req$next[2:0]$3185 + end + attribute \src "libresoc.v:49505.3-49516.6" + process $proc$libresoc.v:49505$3187 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\alu_cr0_cr_op__fn_unit$next[11:0]$3188 $1\alu_cr0_cr_op__fn_unit$next[11:0]$3191 + assign $0\alu_cr0_cr_op__insn$next[31:0]$3189 $1\alu_cr0_cr_op__insn$next[31:0]$3192 + assign $0\alu_cr0_cr_op__insn_type$next[6:0]$3190 $1\alu_cr0_cr_op__insn_type$next[6:0]$3193 + attribute \src "libresoc.v:49506.5-49506.29" + switch \initial + attribute \src "libresoc.v:49506.9-49506.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { $1\alu_cr0_cr_op__insn$next[31:0]$3192 $1\alu_cr0_cr_op__fn_unit$next[11:0]$3191 $1\alu_cr0_cr_op__insn_type$next[6:0]$3193 } { \oper_i_alu_cr0__insn \oper_i_alu_cr0__fn_unit \oper_i_alu_cr0__insn_type } + case + assign $1\alu_cr0_cr_op__fn_unit$next[11:0]$3191 \alu_cr0_cr_op__fn_unit + assign $1\alu_cr0_cr_op__insn$next[31:0]$3192 \alu_cr0_cr_op__insn + assign $1\alu_cr0_cr_op__insn_type$next[6:0]$3193 \alu_cr0_cr_op__insn_type + end + sync always + update \alu_cr0_cr_op__fn_unit$next $0\alu_cr0_cr_op__fn_unit$next[11:0]$3188 + update \alu_cr0_cr_op__insn$next $0\alu_cr0_cr_op__insn$next[31:0]$3189 + update \alu_cr0_cr_op__insn_type$next $0\alu_cr0_cr_op__insn_type$next[6:0]$3190 + end + attribute \src "libresoc.v:49517.3-49538.6" + process $proc$libresoc.v:49517$3194 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r0__o$next[63:0]$3195 $2\data_r0__o$next[63:0]$3199 + assign { } { } + assign $0\data_r0__o_ok$next[0:0]$3196 $3\data_r0__o_ok$next[0:0]$3201 + attribute \src "libresoc.v:49518.5-49518.29" + switch \initial + attribute \src "libresoc.v:49518.9-49518.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r0__o_ok$next[0:0]$3198 $1\data_r0__o$next[63:0]$3197 } { \o_ok \alu_cr0_o } + case + assign $1\data_r0__o$next[63:0]$3197 \data_r0__o + assign $1\data_r0__o_ok$next[0:0]$3198 \data_r0__o_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r0__o_ok$next[0:0]$3200 $2\data_r0__o$next[63:0]$3199 } 65'00000000000000000000000000000000000000000000000000000000000000000 + case + assign $2\data_r0__o$next[63:0]$3199 $1\data_r0__o$next[63:0]$3197 + assign $2\data_r0__o_ok$next[0:0]$3200 $1\data_r0__o_ok$next[0:0]$3198 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r0__o_ok$next[0:0]$3201 1'0 + case + assign $3\data_r0__o_ok$next[0:0]$3201 $2\data_r0__o_ok$next[0:0]$3200 + end + sync always + update \data_r0__o$next $0\data_r0__o$next[63:0]$3195 + update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$3196 + end + attribute \src "libresoc.v:49539.3-49560.6" + process $proc$libresoc.v:49539$3202 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r1__full_cr$next[31:0]$3203 $2\data_r1__full_cr$next[31:0]$3207 + assign { } { } + assign $0\data_r1__full_cr_ok$next[0:0]$3204 $3\data_r1__full_cr_ok$next[0:0]$3209 + attribute \src "libresoc.v:49540.5-49540.29" + switch \initial + attribute \src "libresoc.v:49540.9-49540.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r1__full_cr_ok$next[0:0]$3206 $1\data_r1__full_cr$next[31:0]$3205 } { \full_cr_ok \alu_cr0_full_cr } + case + assign $1\data_r1__full_cr$next[31:0]$3205 \data_r1__full_cr + assign $1\data_r1__full_cr_ok$next[0:0]$3206 \data_r1__full_cr_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r1__full_cr_ok$next[0:0]$3208 $2\data_r1__full_cr$next[31:0]$3207 } 33'000000000000000000000000000000000 + case + assign $2\data_r1__full_cr$next[31:0]$3207 $1\data_r1__full_cr$next[31:0]$3205 + assign $2\data_r1__full_cr_ok$next[0:0]$3208 $1\data_r1__full_cr_ok$next[0:0]$3206 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r1__full_cr_ok$next[0:0]$3209 1'0 + case + assign $3\data_r1__full_cr_ok$next[0:0]$3209 $2\data_r1__full_cr_ok$next[0:0]$3208 + end + sync always + update \data_r1__full_cr$next $0\data_r1__full_cr$next[31:0]$3203 + update \data_r1__full_cr_ok$next $0\data_r1__full_cr_ok$next[0:0]$3204 + end + attribute \src "libresoc.v:49561.3-49582.6" + process $proc$libresoc.v:49561$3210 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r2__cr_a$next[3:0]$3211 $2\data_r2__cr_a$next[3:0]$3215 + assign { } { } + assign $0\data_r2__cr_a_ok$next[0:0]$3212 $3\data_r2__cr_a_ok$next[0:0]$3217 + attribute \src "libresoc.v:49562.5-49562.29" + switch \initial + attribute \src "libresoc.v:49562.9-49562.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r2__cr_a_ok$next[0:0]$3214 $1\data_r2__cr_a$next[3:0]$3213 } { \cr_a_ok \alu_cr0_cr_a } + case + assign $1\data_r2__cr_a$next[3:0]$3213 \data_r2__cr_a + assign $1\data_r2__cr_a_ok$next[0:0]$3214 \data_r2__cr_a_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r2__cr_a_ok$next[0:0]$3216 $2\data_r2__cr_a$next[3:0]$3215 } 5'00000 + case + assign $2\data_r2__cr_a$next[3:0]$3215 $1\data_r2__cr_a$next[3:0]$3213 + assign $2\data_r2__cr_a_ok$next[0:0]$3216 $1\data_r2__cr_a_ok$next[0:0]$3214 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r2__cr_a_ok$next[0:0]$3217 1'0 + case + assign $3\data_r2__cr_a_ok$next[0:0]$3217 $2\data_r2__cr_a_ok$next[0:0]$3216 + end + sync always + update \data_r2__cr_a$next $0\data_r2__cr_a$next[3:0]$3211 + update \data_r2__cr_a_ok$next $0\data_r2__cr_a_ok$next[0:0]$3212 + end + attribute \src "libresoc.v:49583.3-49592.6" + process $proc$libresoc.v:49583$3218 + assign { } { } + assign { } { } + assign $0\src_r0$next[63:0]$3219 $1\src_r0$next[63:0]$3220 + attribute \src "libresoc.v:49584.5-49584.29" + switch \initial + attribute \src "libresoc.v:49584.9-49584.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch \src_l_q_src [0] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r0$next[63:0]$3220 \src1_i + case + assign $1\src_r0$next[63:0]$3220 \src_r0 + end + sync always + update \src_r0$next $0\src_r0$next[63:0]$3219 + end + attribute \src "libresoc.v:49593.3-49602.6" + process $proc$libresoc.v:49593$3221 + assign { } { } + assign { } { } + assign $0\src_r1$next[63:0]$3222 $1\src_r1$next[63:0]$3223 + attribute \src "libresoc.v:49594.5-49594.29" + switch \initial + attribute \src "libresoc.v:49594.9-49594.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch \src_l_q_src [1] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r1$next[63:0]$3223 \src2_i + case + assign $1\src_r1$next[63:0]$3223 \src_r1 + end + sync always + update \src_r1$next $0\src_r1$next[63:0]$3222 + end + attribute \src "libresoc.v:49603.3-49612.6" + process $proc$libresoc.v:49603$3224 + assign { } { } + assign { } { } + assign $0\src_r2$next[31:0]$3225 $1\src_r2$next[31:0]$3226 + attribute \src "libresoc.v:49604.5-49604.29" + switch \initial + attribute \src "libresoc.v:49604.9-49604.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch \src_l_q_src [2] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r2$next[31:0]$3226 \src3_i + case + assign $1\src_r2$next[31:0]$3226 \src_r2 + end + sync always + update \src_r2$next $0\src_r2$next[31:0]$3225 + end + attribute \src "libresoc.v:49613.3-49622.6" + process $proc$libresoc.v:49613$3227 + assign { } { } + assign { } { } + assign $0\src_r3$next[3:0]$3228 $1\src_r3$next[3:0]$3229 + attribute \src "libresoc.v:49614.5-49614.29" + switch \initial + attribute \src "libresoc.v:49614.9-49614.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch \src_l_q_src [3] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r3$next[3:0]$3229 \src4_i + case + assign $1\src_r3$next[3:0]$3229 \src_r3 + end + sync always + update \src_r3$next $0\src_r3$next[3:0]$3228 + end + attribute \src "libresoc.v:49623.3-49632.6" + process $proc$libresoc.v:49623$3230 + assign { } { } + assign { } { } + assign $0\src_r4$next[3:0]$3231 $1\src_r4$next[3:0]$3232 + attribute \src "libresoc.v:49624.5-49624.29" + switch \initial + attribute \src "libresoc.v:49624.9-49624.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch \src_l_q_src [4] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r4$next[3:0]$3232 \src5_i + case + assign $1\src_r4$next[3:0]$3232 \src_r4 + end + sync always + update \src_r4$next $0\src_r4$next[3:0]$3231 + end + attribute \src "libresoc.v:49633.3-49642.6" + process $proc$libresoc.v:49633$3233 + assign { } { } + assign { } { } + assign $0\src_r5$next[3:0]$3234 $1\src_r5$next[3:0]$3235 + attribute \src "libresoc.v:49634.5-49634.29" + switch \initial + attribute \src "libresoc.v:49634.9-49634.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch \src_l_q_src [5] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r5$next[3:0]$3235 \src6_i + case + assign $1\src_r5$next[3:0]$3235 \src_r5 + end + sync always + update \src_r5$next $0\src_r5$next[3:0]$3234 + end + attribute \src "libresoc.v:49643.3-49651.6" + process $proc$libresoc.v:49643$3236 + assign { } { } + assign { } { } + assign $0\alui_l_r_alui$next[0:0]$3237 $1\alui_l_r_alui$next[0:0]$3238 + attribute \src "libresoc.v:49644.5-49644.29" + switch \initial + attribute \src "libresoc.v:49644.9-49644.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\alui_l_r_alui$next[0:0]$3238 1'1 + case + assign $1\alui_l_r_alui$next[0:0]$3238 \$89 + end + sync always + update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$3237 + end + attribute \src "libresoc.v:49652.3-49660.6" + process $proc$libresoc.v:49652$3239 + assign { } { } + assign { } { } + assign $0\alu_l_r_alu$next[0:0]$3240 $1\alu_l_r_alu$next[0:0]$3241 + attribute \src "libresoc.v:49653.5-49653.29" + switch \initial + attribute \src "libresoc.v:49653.9-49653.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\alu_l_r_alu$next[0:0]$3241 1'1 + case + assign $1\alu_l_r_alu$next[0:0]$3241 \$91 + end + sync always + update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$3240 + end + attribute \src "libresoc.v:49661.3-49670.6" + process $proc$libresoc.v:49661$3242 + assign { } { } + assign { } { } + assign $0\dest1_o[63:0] $1\dest1_o[63:0] + attribute \src "libresoc.v:49662.5-49662.29" + switch \initial + attribute \src "libresoc.v:49662.9-49662.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$111 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest1_o[63:0] \data_r0__o + case + assign $1\dest1_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \dest1_o $0\dest1_o[63:0] + end + attribute \src "libresoc.v:49671.3-49680.6" + process $proc$libresoc.v:49671$3243 + assign { } { } + assign { } { } + assign $0\dest2_o[31:0] $1\dest2_o[31:0] + attribute \src "libresoc.v:49672.5-49672.29" + switch \initial + attribute \src "libresoc.v:49672.9-49672.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$113 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest2_o[31:0] \data_r1__full_cr + case + assign $1\dest2_o[31:0] 0 + end + sync always + update \dest2_o $0\dest2_o[31:0] + end + attribute \src "libresoc.v:49681.3-49690.6" + process $proc$libresoc.v:49681$3244 + assign { } { } + assign { } { } + assign $0\dest3_o[3:0] $1\dest3_o[3:0] + attribute \src "libresoc.v:49682.5-49682.29" + switch \initial + attribute \src "libresoc.v:49682.9-49682.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$115 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest3_o[3:0] \data_r2__cr_a + case + assign $1\dest3_o[3:0] 4'0000 + end + sync always + update \dest3_o $0\dest3_o[3:0] + end + attribute \src "libresoc.v:49691.3-49699.6" + process $proc$libresoc.v:49691$3245 + assign { } { } + assign { } { } + assign $0\prev_wr_go$next[2:0]$3246 $1\prev_wr_go$next[2:0]$3247 + attribute \src "libresoc.v:49692.5-49692.29" + switch \initial + attribute \src "libresoc.v:49692.9-49692.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\prev_wr_go$next[2:0]$3247 3'000 + case + assign $1\prev_wr_go$next[2:0]$3247 \$21 + end + sync always + update \prev_wr_go$next $0\prev_wr_go$next[2:0]$3246 + end + connect \$5 $reduce_and$libresoc.v:49217$3069_Y + connect \$99 $and$libresoc.v:49218$3070_Y + connect \$101 $and$libresoc.v:49219$3071_Y + connect \$103 $and$libresoc.v:49220$3072_Y + connect \$105 $and$libresoc.v:49221$3073_Y + connect \$107 $and$libresoc.v:49222$3074_Y + connect \$109 $and$libresoc.v:49223$3075_Y + connect \$111 $and$libresoc.v:49224$3076_Y + connect \$113 $and$libresoc.v:49225$3077_Y + connect \$115 $and$libresoc.v:49226$3078_Y + connect \$11 $and$libresoc.v:49227$3079_Y + connect \$13 $not$libresoc.v:49228$3080_Y + connect \$15 $and$libresoc.v:49229$3081_Y + connect \$17 $not$libresoc.v:49230$3082_Y + connect \$19 $and$libresoc.v:49231$3083_Y + connect \$21 $and$libresoc.v:49232$3084_Y + connect \$25 $not$libresoc.v:49233$3085_Y + connect \$27 $and$libresoc.v:49234$3086_Y + connect \$24 $reduce_or$libresoc.v:49235$3087_Y + connect \$23 $not$libresoc.v:49236$3088_Y + connect \$31 $and$libresoc.v:49237$3089_Y + connect \$33 $reduce_or$libresoc.v:49238$3090_Y + connect \$35 $reduce_or$libresoc.v:49239$3091_Y + connect \$37 $or$libresoc.v:49240$3092_Y + connect \$3 $and$libresoc.v:49241$3093_Y + connect \$39 $not$libresoc.v:49242$3094_Y + connect \$41 $and$libresoc.v:49243$3095_Y + connect \$43 $and$libresoc.v:49244$3096_Y + connect \$45 $eq$libresoc.v:49245$3097_Y + connect \$47 $and$libresoc.v:49246$3098_Y + connect \$49 $eq$libresoc.v:49247$3099_Y + connect \$51 $and$libresoc.v:49248$3100_Y + connect \$53 $and$libresoc.v:49249$3101_Y + connect \$55 $and$libresoc.v:49250$3102_Y + connect \$57 $or$libresoc.v:49251$3103_Y + connect \$59 $or$libresoc.v:49252$3104_Y + connect \$61 $or$libresoc.v:49253$3105_Y + connect \$63 $or$libresoc.v:49254$3106_Y + connect \$65 $and$libresoc.v:49255$3107_Y + connect \$67 $and$libresoc.v:49256$3108_Y + connect \$6 $not$libresoc.v:49257$3109_Y + connect \$69 $or$libresoc.v:49258$3110_Y + connect \$71 $and$libresoc.v:49259$3111_Y + connect \$73 $and$libresoc.v:49260$3112_Y + connect \$75 $and$libresoc.v:49261$3113_Y + connect \$77 $ternary$libresoc.v:49262$3114_Y + connect \$79 $ternary$libresoc.v:49263$3115_Y + connect \$81 $ternary$libresoc.v:49264$3116_Y + connect \$83 $ternary$libresoc.v:49265$3117_Y + connect \$85 $ternary$libresoc.v:49266$3118_Y + connect \$87 $ternary$libresoc.v:49267$3119_Y + connect \$8 $or$libresoc.v:49268$3120_Y + connect \$89 $and$libresoc.v:49269$3121_Y + connect \$91 $and$libresoc.v:49270$3122_Y + connect \$93 $and$libresoc.v:49271$3123_Y + connect \$95 $and$libresoc.v:49272$3124_Y + connect \$97 $not$libresoc.v:49273$3125_Y + connect \cu_go_die_i 1'0 + connect \cu_shadown_i 1'1 + connect \cu_wr__rel_o \$109 + connect \cu_rd__rel_o \$99 + connect \cu_busy_o \opc_l_q_opc + connect \alu_l_s_alu \all_rd_pulse + connect \alu_cr0_n_ready_i \alu_l_q_alu + connect \alui_l_s_alui \all_rd_pulse + connect \alu_cr0_p_valid_i \alui_l_q_alui + connect \alu_cr0_cr_c \$87 + connect \alu_cr0_cr_b \$85 + connect \alu_cr0_cr_a$2 \$83 + connect \alu_cr0_full_cr$1 \$81 + connect \alu_cr0_rb \$79 + connect \alu_cr0_ra \$77 + connect \cu_wrmask_o { \$75 \$73 \$71 } + connect \reset_r \$63 + connect \reset_w \$61 + connect \rst_r \$59 + connect \reset \$57 + connect \wr_any \$37 + connect \cu_done_o \$31 + connect \alu_pulsem { \alu_pulse \alu_pulse \alu_pulse } + connect \alu_pulse \alu_done_rise + connect \alu_done_rise \$19 + connect \alu_done_dly$next \alu_done + connect \alu_done \alu_cr0_n_valid_o + connect \all_rd_pulse \all_rd_rise + connect \all_rd_rise \$15 + connect \all_rd_dly$next \all_rd + connect \all_rd \$11 +end +attribute \src "libresoc.v:49735.1-49784.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.l0.pimem.cyc_l" +attribute \generator "nMigen" +module \cyc_l + attribute \src "libresoc.v:49736.7-49736.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:49772.3-49780.6" + wire $0\q_int$next[0:0]$3286 + attribute \src "libresoc.v:49770.3-49771.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:49772.3-49780.6" + wire $1\q_int$next[0:0]$3287 + attribute \src "libresoc.v:49754.7-49754.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:49767.17-49767.96" + wire $and$libresoc.v:49767$3281_Y + attribute \src "libresoc.v:49766.17-49766.92" + wire $not$libresoc.v:49766$3280_Y + attribute \src "libresoc.v:49769.17-49769.92" + wire $not$libresoc.v:49769$3283_Y + attribute \src "libresoc.v:49765.17-49765.98" + wire $or$libresoc.v:49765$3279_Y + attribute \src "libresoc.v:49768.17-49768.97" + wire $or$libresoc.v:49768$3282_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 1 \coresync_rst + attribute \src "libresoc.v:49736.7-49736.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 4 \q_cyc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_cyc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_cyc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_cyc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 2 \s_cyc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:49767$3281 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:49767$3281_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:49766$3280 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_cyc + connect \Y $not$libresoc.v:49766$3280_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:49769$3283 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_cyc + connect \Y $not$libresoc.v:49769$3283_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:49765$3279 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_cyc + connect \B \q_int + connect \Y $or$libresoc.v:49765$3279_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:49768$3282 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_cyc + connect \Y $or$libresoc.v:49768$3282_Y + end + attribute \src "libresoc.v:49736.7-49736.20" + process $proc$libresoc.v:49736$3288 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:49754.7-49754.19" + process $proc$libresoc.v:49754$3289 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:49770.3-49771.27" + process $proc$libresoc.v:49770$3284 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:49772.3-49780.6" + process $proc$libresoc.v:49772$3285 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$3286 $1\q_int$next[0:0]$3287 + attribute \src "libresoc.v:49773.5-49773.29" + switch \initial + attribute \src "libresoc.v:49773.9-49773.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$3287 1'0 + case + assign $1\q_int$next[0:0]$3287 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$3286 + end + connect \$9 $or$libresoc.v:49765$3279_Y + connect \$1 $not$libresoc.v:49766$3280_Y + connect \$3 $and$libresoc.v:49767$3281_Y + connect \$5 $or$libresoc.v:49768$3282_Y + connect \$7 $not$libresoc.v:49769$3283_Y + connect \qlq_cyc \$9 + connect \qn_cyc \$7 + connect \q_cyc \q_int +end +attribute \src "libresoc.v:49788.1-50502.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.dbg" +attribute \generator "nMigen" +module \dbg + attribute \src "libresoc.v:50318.3-50327.6" + wire $0\d_cr_req[0:0] + attribute \src "libresoc.v:50125.3-50134.6" + wire $0\d_gpr_req[0:0] + attribute \src "libresoc.v:50328.3-50337.6" + wire $0\d_xer_req[0:0] + attribute \src "libresoc.v:50107.3-50124.6" + wire $0\dmi_ack_o[0:0] + attribute \src "libresoc.v:50338.3-50368.6" + wire width 64 $0\dmi_dout[63:0] + attribute \src "libresoc.v:50309.3-50317.6" + wire $0\dmi_read_log_data$next[0:0]$3403 + attribute \src "libresoc.v:50085.3-50086.51" + wire $0\dmi_read_log_data[0:0] + attribute \src "libresoc.v:50300.3-50308.6" + wire $0\dmi_read_log_data_1$next[0:0]$3400 + attribute \src "libresoc.v:50087.3-50088.55" + wire $0\dmi_read_log_data_1[0:0] + attribute \src "libresoc.v:50135.3-50143.6" + wire $0\dmi_req_i_1$next[0:0]$3366 + attribute \src "libresoc.v:50097.3-50098.39" + wire $0\dmi_req_i_1[0:0] + attribute \src "libresoc.v:50459.3-50492.6" + wire $0\do_dmi_log_rd$next[0:0]$3430 + attribute \src "libresoc.v:50099.3-50100.43" + wire $0\do_dmi_log_rd[0:0] + attribute \src "libresoc.v:50429.3-50458.6" + wire $0\do_icreset$next[0:0]$3423 + attribute \src "libresoc.v:50101.3-50102.37" + wire $0\do_icreset[0:0] + attribute \src "libresoc.v:50399.3-50428.6" + wire $0\do_reset$next[0:0]$3416 + attribute \src "libresoc.v:50103.3-50104.33" + wire $0\do_reset[0:0] + attribute \src "libresoc.v:50369.3-50398.6" + wire $0\do_step$next[0:0]$3409 + attribute \src "libresoc.v:50105.3-50106.31" + wire $0\do_step[0:0] + attribute \src "libresoc.v:50238.3-50265.6" + wire width 7 $0\gspr_index$next[6:0]$3388 + attribute \src "libresoc.v:50091.3-50092.37" + wire width 7 $0\gspr_index[6:0] + attribute \src "libresoc.v:49789.7-49789.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:50266.3-50299.6" + wire width 32 $0\log_dmi_addr$next[31:0]$3394 + attribute \src "libresoc.v:50089.3-50090.41" + wire width 32 $0\log_dmi_addr[31:0] + attribute \src "libresoc.v:50194.3-50237.6" + wire $0\stopping$next[0:0]$3379 + attribute \src "libresoc.v:50093.3-50094.33" + wire $0\stopping[0:0] + attribute \src "libresoc.v:50144.3-50193.6" + wire $0\terminated$next[0:0]$3369 + attribute \src "libresoc.v:50095.3-50096.37" + wire $0\terminated[0:0] + attribute \src "libresoc.v:50318.3-50327.6" + wire $1\d_cr_req[0:0] + attribute \src "libresoc.v:50125.3-50134.6" + wire $1\d_gpr_req[0:0] + attribute \src "libresoc.v:50328.3-50337.6" + wire $1\d_xer_req[0:0] + attribute \src "libresoc.v:50107.3-50124.6" + wire $1\dmi_ack_o[0:0] + attribute \src "libresoc.v:50338.3-50368.6" + wire width 64 $1\dmi_dout[63:0] + attribute \src "libresoc.v:50309.3-50317.6" + wire $1\dmi_read_log_data$next[0:0]$3404 + attribute \src "libresoc.v:49962.7-49962.31" + wire $1\dmi_read_log_data[0:0] + attribute \src "libresoc.v:50300.3-50308.6" + wire $1\dmi_read_log_data_1$next[0:0]$3401 + attribute \src "libresoc.v:49966.7-49966.33" + wire $1\dmi_read_log_data_1[0:0] + attribute \src "libresoc.v:50135.3-50143.6" + wire $1\dmi_req_i_1$next[0:0]$3367 + attribute \src "libresoc.v:49972.7-49972.25" + wire $1\dmi_req_i_1[0:0] + attribute \src "libresoc.v:50459.3-50492.6" + wire $1\do_dmi_log_rd$next[0:0]$3431 + attribute \src "libresoc.v:49978.7-49978.27" + wire $1\do_dmi_log_rd[0:0] + attribute \src "libresoc.v:50429.3-50458.6" + wire $1\do_icreset$next[0:0]$3424 + attribute \src "libresoc.v:49982.7-49982.24" + wire $1\do_icreset[0:0] + attribute \src "libresoc.v:50399.3-50428.6" + wire $1\do_reset$next[0:0]$3417 + attribute \src "libresoc.v:49986.7-49986.22" + wire $1\do_reset[0:0] + attribute \src "libresoc.v:50369.3-50398.6" + wire $1\do_step$next[0:0]$3410 + attribute \src "libresoc.v:49990.7-49990.21" + wire $1\do_step[0:0] + attribute \src "libresoc.v:50238.3-50265.6" + wire width 7 $1\gspr_index$next[6:0]$3389 + attribute \src "libresoc.v:49994.13-49994.31" + wire width 7 $1\gspr_index[6:0] + attribute \src "libresoc.v:50266.3-50299.6" + wire width 32 $1\log_dmi_addr$next[31:0]$3395 + attribute \src "libresoc.v:50000.14-50000.34" + wire width 32 $1\log_dmi_addr[31:0] + attribute \src "libresoc.v:50194.3-50237.6" + wire $1\stopping$next[0:0]$3380 + attribute \src "libresoc.v:50012.7-50012.22" + wire $1\stopping[0:0] + attribute \src "libresoc.v:50144.3-50193.6" + wire $1\terminated$next[0:0]$3370 + attribute \src "libresoc.v:50018.7-50018.24" + wire $1\terminated[0:0] + attribute \src "libresoc.v:50459.3-50492.6" + wire $2\do_dmi_log_rd$next[0:0]$3432 + attribute \src "libresoc.v:50429.3-50458.6" + wire $2\do_icreset$next[0:0]$3425 + attribute \src "libresoc.v:50399.3-50428.6" + wire $2\do_reset$next[0:0]$3418 + attribute \src "libresoc.v:50369.3-50398.6" + wire $2\do_step$next[0:0]$3411 + attribute \src "libresoc.v:50238.3-50265.6" + wire width 7 $2\gspr_index$next[6:0]$3390 + attribute \src "libresoc.v:50266.3-50299.6" + wire width 32 $2\log_dmi_addr$next[31:0]$3396 + attribute \src "libresoc.v:50194.3-50237.6" + wire $2\stopping$next[0:0]$3381 + attribute \src "libresoc.v:50144.3-50193.6" + wire $2\terminated$next[0:0]$3371 + attribute \src "libresoc.v:50459.3-50492.6" + wire $3\do_dmi_log_rd$next[0:0]$3433 + attribute \src "libresoc.v:50429.3-50458.6" + wire $3\do_icreset$next[0:0]$3426 + attribute \src "libresoc.v:50399.3-50428.6" + wire $3\do_reset$next[0:0]$3419 + attribute \src "libresoc.v:50369.3-50398.6" + wire $3\do_step$next[0:0]$3412 + attribute \src "libresoc.v:50238.3-50265.6" + wire width 7 $3\gspr_index$next[6:0]$3391 + attribute \src "libresoc.v:50266.3-50299.6" + wire width 32 $3\log_dmi_addr$next[31:0]$3397 + attribute \src "libresoc.v:50194.3-50237.6" + wire $3\stopping$next[0:0]$3382 + attribute \src "libresoc.v:50144.3-50193.6" + wire $3\terminated$next[0:0]$3372 + attribute \src "libresoc.v:50459.3-50492.6" + wire $4\do_dmi_log_rd$next[0:0]$3434 + attribute \src "libresoc.v:50429.3-50458.6" + wire $4\do_icreset$next[0:0]$3427 + attribute \src "libresoc.v:50399.3-50428.6" + wire $4\do_reset$next[0:0]$3420 + attribute \src "libresoc.v:50369.3-50398.6" + wire $4\do_step$next[0:0]$3413 + attribute \src "libresoc.v:50238.3-50265.6" + wire width 7 $4\gspr_index$next[6:0]$3392 + attribute \src "libresoc.v:50266.3-50299.6" + wire width 32 $4\log_dmi_addr$next[31:0]$3398 + attribute \src "libresoc.v:50194.3-50237.6" + wire $4\stopping$next[0:0]$3383 + attribute \src "libresoc.v:50144.3-50193.6" + wire $4\terminated$next[0:0]$3373 + attribute \src "libresoc.v:50429.3-50458.6" + wire $5\do_icreset$next[0:0]$3428 + attribute \src "libresoc.v:50399.3-50428.6" + wire $5\do_reset$next[0:0]$3421 + attribute \src "libresoc.v:50369.3-50398.6" + wire $5\do_step$next[0:0]$3414 + attribute \src "libresoc.v:50194.3-50237.6" + wire $5\stopping$next[0:0]$3384 + attribute \src "libresoc.v:50144.3-50193.6" + wire $5\terminated$next[0:0]$3374 + attribute \src "libresoc.v:50194.3-50237.6" + wire $6\stopping$next[0:0]$3385 + attribute \src "libresoc.v:50144.3-50193.6" + wire $6\terminated$next[0:0]$3375 + attribute \src "libresoc.v:50194.3-50237.6" + wire $7\stopping$next[0:0]$3386 + attribute \src "libresoc.v:50144.3-50193.6" + wire $7\terminated$next[0:0]$3376 + attribute \src "libresoc.v:50144.3-50193.6" + wire $8\terminated$next[0:0]$3377 + attribute \src "libresoc.v:50032.19-50032.110" + wire width 3 $add$libresoc.v:50032$3299_Y + attribute \src "libresoc.v:50023.17-50023.109" + wire $and$libresoc.v:50023$3290_Y + attribute \src "libresoc.v:50026.19-50026.103" + wire $and$libresoc.v:50026$3293_Y + attribute \src "libresoc.v:50028.19-50028.113" + wire $and$libresoc.v:50028$3295_Y + attribute \src "libresoc.v:50035.19-50035.103" + wire $and$libresoc.v:50035$3302_Y + attribute \src "libresoc.v:50037.19-50037.102" + wire $and$libresoc.v:50037$3304_Y + attribute \src "libresoc.v:50042.18-50042.101" + wire $and$libresoc.v:50042$3309_Y + attribute \src "libresoc.v:50044.18-50044.111" + wire $and$libresoc.v:50044$3311_Y + attribute \src "libresoc.v:50049.18-50049.101" + wire $and$libresoc.v:50049$3316_Y + attribute \src "libresoc.v:50051.18-50051.111" + wire $and$libresoc.v:50051$3318_Y + attribute \src "libresoc.v:50057.18-50057.101" + wire $and$libresoc.v:50057$3324_Y + attribute \src "libresoc.v:50059.18-50059.111" + wire $and$libresoc.v:50059$3326_Y + attribute \src "libresoc.v:50063.17-50063.99" + wire $and$libresoc.v:50063$3330_Y + attribute \src "libresoc.v:50065.18-50065.101" + wire $and$libresoc.v:50065$3332_Y + attribute \src "libresoc.v:50067.18-50067.111" + wire $and$libresoc.v:50067$3334_Y + attribute \src "libresoc.v:50072.18-50072.101" + wire $and$libresoc.v:50072$3339_Y + attribute \src "libresoc.v:50075.18-50075.111" + wire $and$libresoc.v:50075$3342_Y + attribute \src "libresoc.v:50080.18-50080.101" + wire $and$libresoc.v:50080$3347_Y + attribute \src "libresoc.v:50082.18-50082.111" + wire $and$libresoc.v:50082$3349_Y + attribute \src "libresoc.v:50024.18-50024.103" + wire $eq$libresoc.v:50024$3291_Y + attribute \src "libresoc.v:50029.19-50029.104" + wire $eq$libresoc.v:50029$3296_Y + attribute \src "libresoc.v:50030.19-50030.104" + wire $eq$libresoc.v:50030$3297_Y + attribute \src "libresoc.v:50031.19-50031.104" + wire $eq$libresoc.v:50031$3298_Y + attribute \src "libresoc.v:50033.19-50033.104" + wire $eq$libresoc.v:50033$3300_Y + attribute \src "libresoc.v:50034.18-50034.103" + wire $eq$libresoc.v:50034$3301_Y + attribute \src "libresoc.v:50038.18-50038.103" + wire $eq$libresoc.v:50038$3305_Y + attribute \src "libresoc.v:50039.18-50039.103" + wire $eq$libresoc.v:50039$3306_Y + attribute \src "libresoc.v:50045.18-50045.103" + wire $eq$libresoc.v:50045$3312_Y + attribute \src "libresoc.v:50046.18-50046.103" + wire $eq$libresoc.v:50046$3313_Y + attribute \src "libresoc.v:50047.18-50047.103" + wire $eq$libresoc.v:50047$3314_Y + attribute \src "libresoc.v:50053.18-50053.103" + wire $eq$libresoc.v:50053$3320_Y + attribute \src "libresoc.v:50054.18-50054.103" + wire $eq$libresoc.v:50054$3321_Y + attribute \src "libresoc.v:50055.18-50055.103" + wire $eq$libresoc.v:50055$3322_Y + attribute \src "libresoc.v:50060.18-50060.103" + wire $eq$libresoc.v:50060$3327_Y + attribute \src "libresoc.v:50061.18-50061.103" + wire $eq$libresoc.v:50061$3328_Y + attribute \src "libresoc.v:50062.18-50062.103" + wire $eq$libresoc.v:50062$3329_Y + attribute \src "libresoc.v:50068.18-50068.103" + wire $eq$libresoc.v:50068$3335_Y + attribute \src "libresoc.v:50069.18-50069.103" + wire $eq$libresoc.v:50069$3336_Y + attribute \src "libresoc.v:50070.18-50070.103" + wire $eq$libresoc.v:50070$3337_Y + attribute \src "libresoc.v:50076.18-50076.103" + wire $eq$libresoc.v:50076$3343_Y + attribute \src "libresoc.v:50077.18-50077.103" + wire $eq$libresoc.v:50077$3344_Y + attribute \src "libresoc.v:50078.18-50078.103" + wire $eq$libresoc.v:50078$3345_Y + attribute \src "libresoc.v:50083.18-50083.103" + wire $eq$libresoc.v:50083$3350_Y + attribute \src "libresoc.v:50084.18-50084.103" + wire $eq$libresoc.v:50084$3351_Y + attribute \src "libresoc.v:50025.19-50025.99" + wire $not$libresoc.v:50025$3292_Y + attribute \src "libresoc.v:50027.19-50027.105" + wire $not$libresoc.v:50027$3294_Y + attribute \src "libresoc.v:50036.19-50036.95" + wire $not$libresoc.v:50036$3303_Y + attribute \src "libresoc.v:50040.18-50040.98" + wire $not$libresoc.v:50040$3307_Y + attribute \src "libresoc.v:50043.18-50043.104" + wire $not$libresoc.v:50043$3310_Y + attribute \src "libresoc.v:50048.18-50048.98" + wire $not$libresoc.v:50048$3315_Y + attribute \src "libresoc.v:50050.18-50050.104" + wire $not$libresoc.v:50050$3317_Y + attribute \src "libresoc.v:50052.17-50052.97" + wire $not$libresoc.v:50052$3319_Y + attribute \src "libresoc.v:50056.18-50056.98" + wire $not$libresoc.v:50056$3323_Y + attribute \src "libresoc.v:50058.18-50058.104" + wire $not$libresoc.v:50058$3325_Y + attribute \src "libresoc.v:50064.18-50064.98" + wire $not$libresoc.v:50064$3331_Y + attribute \src "libresoc.v:50066.18-50066.104" + wire $not$libresoc.v:50066$3333_Y + attribute \src "libresoc.v:50071.18-50071.98" + wire $not$libresoc.v:50071$3338_Y + attribute \src "libresoc.v:50073.18-50073.104" + wire $not$libresoc.v:50073$3340_Y + attribute \src "libresoc.v:50074.17-50074.103" + wire $not$libresoc.v:50074$3341_Y + attribute \src "libresoc.v:50079.18-50079.98" + wire $not$libresoc.v:50079$3346_Y + attribute \src "libresoc.v:50081.18-50081.104" + wire $not$libresoc.v:50081$3348_Y + attribute \src "libresoc.v:50041.17-50041.126" + wire width 64 $pos$libresoc.v:50041$3308_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:170" + wire width 64 \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + wire \$101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + wire \$103 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + wire \$105 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + wire \$107 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" + wire \$109 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223" + wire \$111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227" + wire \$113 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" + wire width 3 \$115 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" + wire width 3 \$116 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:242" + wire \$118 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:242" + wire \$120 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:254" + wire \$122 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:254" + wire \$124 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + wire \$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + wire \$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" + wire \$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227" + wire \$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + wire \$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + wire \$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + wire \$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" + wire \$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223" + wire \$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227" + wire \$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + wire \$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + wire \$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + wire \$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + wire \$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" + wire \$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223" + wire \$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227" + wire \$57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + wire \$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + wire \$61 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + wire \$63 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + wire \$65 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" + wire \$67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223" + wire \$69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227" + wire \$71 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + wire \$73 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + wire \$75 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + wire \$77 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + wire \$79 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" + wire \$81 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223" + wire \$83 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227" + wire \$85 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + wire \$87 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + wire \$89 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + wire \$91 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + wire \$93 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" + wire \$95 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223" + wire \$97 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227" + wire \$99 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:151" + wire input 6 \clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:9" + wire width 64 input 10 \core_dbg_msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:8" + wire width 64 input 9 \core_dbg_pc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:98" + wire output 7 \core_rst_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:97" + wire output 11 \core_stop_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:103" + wire input 12 \core_stopped_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:77" + wire input 19 \d_cr_ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:79" + wire width 64 input 18 \d_cr_data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:76" + wire output 17 \d_cr_req + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:77" + wire input 16 \d_gpr_ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:78" + wire width 7 output 14 \d_gpr_addr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:79" + wire width 64 input 15 \d_gpr_data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:76" + wire output 13 \d_gpr_req + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:77" + wire input 22 \d_xer_ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:79" + wire width 64 input 21 \d_xer_data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:76" + wire output 20 \d_xer_req + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:62" + wire output 4 \dmi_ack_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:57" + wire width 4 input 24 \dmi_addr_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:58" + wire width 64 input 3 \dmi_din + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:59" + wire width 64 output 5 \dmi_dout + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:148" + wire \dmi_read_log_data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:148" + wire \dmi_read_log_data$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:149" + wire \dmi_read_log_data_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:149" + wire \dmi_read_log_data_1$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:60" + wire input 1 \dmi_req_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:131" + wire \dmi_req_i_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:131" + wire \dmi_req_i_1$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:61" + wire input 2 \dmi_we_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:147" + wire \do_dmi_log_rd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:147" + wire \do_dmi_log_rd$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:140" + wire \do_icreset + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:140" + wire \do_icreset$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:139" + wire \do_reset + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:139" + wire \do_reset$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:138" + wire \do_step + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:138" + wire \do_step$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:143" + wire width 7 \gspr_index + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:143" + wire width 7 \gspr_index$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:99" + wire \icache_rst_o + attribute \src "libresoc.v:49789.7-49789.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:145" + wire width 32 \log_dmi_addr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:145" + wire width 32 \log_dmi_addr$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:146" + wire width 64 \log_dmi_data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:119" + wire width 32 \log_write_addr_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:151" + wire input 23 \rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:134" + wire width 64 \stat_reg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:137" + wire \stopping + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:137" + wire \stopping$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:102" + wire input 8 \terminate_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:141" + wire \terminated + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:141" + wire \terminated$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:122" + wire \terminated_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" + cell $add $add$libresoc.v:50032$3299 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \log_dmi_addr [1:0] + connect \B 1'1 + connect \Y $add$libresoc.v:50032$3299_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + cell $and $and$libresoc.v:50023$3290 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_read_log_data_1 + connect \B \$7 + connect \Y $and$libresoc.v:50023$3290_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + cell $and $and$libresoc.v:50026$3293 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_req_i + connect \B \$101 + connect \Y $and$libresoc.v:50026$3293_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + cell $and $and$libresoc.v:50028$3295 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_read_log_data_1 + connect \B \$105 + connect \Y $and$libresoc.v:50028$3295_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:242" + cell $and $and$libresoc.v:50035$3302 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_req_i + connect \B \$118 + connect \Y $and$libresoc.v:50035$3302_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:254" + cell $and $and$libresoc.v:50037$3304 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \stopping + connect \B \$122 + connect \Y $and$libresoc.v:50037$3304_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + cell $and $and$libresoc.v:50042$3309 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_req_i + connect \B \$17 + connect \Y $and$libresoc.v:50042$3309_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + cell $and $and$libresoc.v:50044$3311 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_read_log_data_1 + connect \B \$21 + connect \Y $and$libresoc.v:50044$3311_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + cell $and $and$libresoc.v:50049$3316 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_req_i + connect \B \$31 + connect \Y $and$libresoc.v:50049$3316_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + cell $and $and$libresoc.v:50051$3318 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_read_log_data_1 + connect \B \$35 + connect \Y $and$libresoc.v:50051$3318_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + cell $and $and$libresoc.v:50057$3324 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_req_i + connect \B \$45 + connect \Y $and$libresoc.v:50057$3324_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + cell $and $and$libresoc.v:50059$3326 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_read_log_data_1 + connect \B \$49 + connect \Y $and$libresoc.v:50059$3326_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + cell $and $and$libresoc.v:50063$3330 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_req_i + connect \B \$3 + connect \Y $and$libresoc.v:50063$3330_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + cell $and $and$libresoc.v:50065$3332 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_req_i + connect \B \$59 + connect \Y $and$libresoc.v:50065$3332_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + cell $and $and$libresoc.v:50067$3334 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_read_log_data_1 + connect \B \$63 + connect \Y $and$libresoc.v:50067$3334_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + cell $and $and$libresoc.v:50072$3339 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_req_i + connect \B \$73 + connect \Y $and$libresoc.v:50072$3339_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + cell $and $and$libresoc.v:50075$3342 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_read_log_data_1 + connect \B \$77 + connect \Y $and$libresoc.v:50075$3342_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + cell $and $and$libresoc.v:50080$3347 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_req_i + connect \B \$87 + connect \Y $and$libresoc.v:50080$3347_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + cell $and $and$libresoc.v:50082$3349 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_read_log_data_1 + connect \B \$91 + connect \Y $and$libresoc.v:50082$3349_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227" + cell $eq $eq$libresoc.v:50024$3291 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 3'110 + connect \Y $eq$libresoc.v:50024$3291_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" + cell $eq $eq$libresoc.v:50029$3296 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 1'0 + connect \Y $eq$libresoc.v:50029$3296_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223" + cell $eq $eq$libresoc.v:50030$3297 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 3'100 + connect \Y $eq$libresoc.v:50030$3297_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227" + cell $eq $eq$libresoc.v:50031$3298 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 3'110 + connect \Y $eq$libresoc.v:50031$3298_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:242" + cell $eq $eq$libresoc.v:50033$3300 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 3'111 + connect \Y $eq$libresoc.v:50033$3300_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" + cell $eq $eq$libresoc.v:50034$3301 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 1'0 + connect \Y $eq$libresoc.v:50034$3301_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223" + cell $eq $eq$libresoc.v:50038$3305 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 3'100 + connect \Y $eq$libresoc.v:50038$3305_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227" + cell $eq $eq$libresoc.v:50039$3306 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 3'110 + connect \Y $eq$libresoc.v:50039$3306_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" + cell $eq $eq$libresoc.v:50045$3312 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 1'0 + connect \Y $eq$libresoc.v:50045$3312_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223" + cell $eq $eq$libresoc.v:50046$3313 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 3'100 + connect \Y $eq$libresoc.v:50046$3313_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227" + cell $eq $eq$libresoc.v:50047$3314 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 3'110 + connect \Y $eq$libresoc.v:50047$3314_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" + cell $eq $eq$libresoc.v:50053$3320 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 1'0 + connect \Y $eq$libresoc.v:50053$3320_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223" + cell $eq $eq$libresoc.v:50054$3321 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 3'100 + connect \Y $eq$libresoc.v:50054$3321_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227" + cell $eq $eq$libresoc.v:50055$3322 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 3'110 + connect \Y $eq$libresoc.v:50055$3322_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" + cell $eq $eq$libresoc.v:50060$3327 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 1'0 + connect \Y $eq$libresoc.v:50060$3327_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223" + cell $eq $eq$libresoc.v:50061$3328 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 3'100 + connect \Y $eq$libresoc.v:50061$3328_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227" + cell $eq $eq$libresoc.v:50062$3329 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 3'110 + connect \Y $eq$libresoc.v:50062$3329_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" + cell $eq $eq$libresoc.v:50068$3335 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 1'0 + connect \Y $eq$libresoc.v:50068$3335_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223" + cell $eq $eq$libresoc.v:50069$3336 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 3'100 + connect \Y $eq$libresoc.v:50069$3336_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227" + cell $eq $eq$libresoc.v:50070$3337 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 3'110 + connect \Y $eq$libresoc.v:50070$3337_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" + cell $eq $eq$libresoc.v:50076$3343 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 1'0 + connect \Y $eq$libresoc.v:50076$3343_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223" + cell $eq $eq$libresoc.v:50077$3344 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 3'100 + connect \Y $eq$libresoc.v:50077$3344_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227" + cell $eq $eq$libresoc.v:50078$3345 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 3'110 + connect \Y $eq$libresoc.v:50078$3345_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" + cell $eq $eq$libresoc.v:50083$3350 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 1'0 + connect \Y $eq$libresoc.v:50083$3350_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223" + cell $eq $eq$libresoc.v:50084$3351 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 3'100 + connect \Y $eq$libresoc.v:50084$3351_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + cell $not $not$libresoc.v:50025$3292 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_req_i_1 + connect \Y $not$libresoc.v:50025$3292_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + cell $not $not$libresoc.v:50027$3294 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_read_log_data + connect \Y $not$libresoc.v:50027$3294_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:254" + cell $not $not$libresoc.v:50036$3303 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \do_step + connect \Y $not$libresoc.v:50036$3303_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + cell $not $not$libresoc.v:50040$3307 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_req_i_1 + connect \Y $not$libresoc.v:50040$3307_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + cell $not $not$libresoc.v:50043$3310 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_read_log_data + connect \Y $not$libresoc.v:50043$3310_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + cell $not $not$libresoc.v:50048$3315 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_req_i_1 + connect \Y $not$libresoc.v:50048$3315_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + cell $not $not$libresoc.v:50050$3317 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_read_log_data + connect \Y $not$libresoc.v:50050$3317_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + cell $not $not$libresoc.v:50052$3319 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_req_i_1 + connect \Y $not$libresoc.v:50052$3319_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + cell $not $not$libresoc.v:50056$3323 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_req_i_1 + connect \Y $not$libresoc.v:50056$3323_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + cell $not $not$libresoc.v:50058$3325 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_read_log_data + connect \Y $not$libresoc.v:50058$3325_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + cell $not $not$libresoc.v:50064$3331 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_req_i_1 + connect \Y $not$libresoc.v:50064$3331_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + cell $not $not$libresoc.v:50066$3333 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_read_log_data + connect \Y $not$libresoc.v:50066$3333_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + cell $not $not$libresoc.v:50071$3338 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_req_i_1 + connect \Y $not$libresoc.v:50071$3338_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + cell $not $not$libresoc.v:50073$3340 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_read_log_data + connect \Y $not$libresoc.v:50073$3340_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + cell $not $not$libresoc.v:50074$3341 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_read_log_data + connect \Y $not$libresoc.v:50074$3341_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + cell $not $not$libresoc.v:50079$3346 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_req_i_1 + connect \Y $not$libresoc.v:50079$3346_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + cell $not $not$libresoc.v:50081$3348 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_read_log_data + connect \Y $not$libresoc.v:50081$3348_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:170" + cell $pos $pos$libresoc.v:50041$3308 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A { 61'0000000000000000000000000000000000000000000000000000000000000 \terminated \core_stopped_i \stopping } + connect \Y $pos$libresoc.v:50041$3308_Y + end + attribute \src "libresoc.v:49789.7-49789.20" + process $proc$libresoc.v:49789$3435 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:49962.7-49962.31" + process $proc$libresoc.v:49962$3436 + assign { } { } + assign $1\dmi_read_log_data[0:0] 1'0 + sync always + sync init + update \dmi_read_log_data $1\dmi_read_log_data[0:0] + end + attribute \src "libresoc.v:49966.7-49966.33" + process $proc$libresoc.v:49966$3437 + assign { } { } + assign $1\dmi_read_log_data_1[0:0] 1'0 + sync always + sync init + update \dmi_read_log_data_1 $1\dmi_read_log_data_1[0:0] + end + attribute \src "libresoc.v:49972.7-49972.25" + process $proc$libresoc.v:49972$3438 + assign { } { } + assign $1\dmi_req_i_1[0:0] 1'0 + sync always + sync init + update \dmi_req_i_1 $1\dmi_req_i_1[0:0] + end + attribute \src "libresoc.v:49978.7-49978.27" + process $proc$libresoc.v:49978$3439 + assign { } { } + assign $1\do_dmi_log_rd[0:0] 1'0 + sync always + sync init + update \do_dmi_log_rd $1\do_dmi_log_rd[0:0] + end + attribute \src "libresoc.v:49982.7-49982.24" + process $proc$libresoc.v:49982$3440 + assign { } { } + assign $1\do_icreset[0:0] 1'0 + sync always + sync init + update \do_icreset $1\do_icreset[0:0] + end + attribute \src "libresoc.v:49986.7-49986.22" + process $proc$libresoc.v:49986$3441 + assign { } { } + assign $1\do_reset[0:0] 1'0 + sync always + sync init + update \do_reset $1\do_reset[0:0] + end + attribute \src "libresoc.v:49990.7-49990.21" + process $proc$libresoc.v:49990$3442 + assign { } { } + assign $1\do_step[0:0] 1'0 + sync always + sync init + update \do_step $1\do_step[0:0] + end + attribute \src "libresoc.v:49994.13-49994.31" + process $proc$libresoc.v:49994$3443 + assign { } { } + assign $1\gspr_index[6:0] 7'0000000 + sync always + sync init + update \gspr_index $1\gspr_index[6:0] + end + attribute \src "libresoc.v:50000.14-50000.34" + process $proc$libresoc.v:50000$3444 + assign { } { } + assign $1\log_dmi_addr[31:0] 0 + sync always + sync init + update \log_dmi_addr $1\log_dmi_addr[31:0] + end + attribute \src "libresoc.v:50012.7-50012.22" + process $proc$libresoc.v:50012$3445 + assign { } { } + assign $1\stopping[0:0] 1'0 + sync always + sync init + update \stopping $1\stopping[0:0] + end + attribute \src "libresoc.v:50018.7-50018.24" + process $proc$libresoc.v:50018$3446 + assign { } { } + assign $1\terminated[0:0] 1'0 + sync always + sync init + update \terminated $1\terminated[0:0] + end + attribute \src "libresoc.v:50085.3-50086.51" + process $proc$libresoc.v:50085$3352 + assign { } { } + assign $0\dmi_read_log_data[0:0] \dmi_read_log_data$next + sync posedge \clk + update \dmi_read_log_data $0\dmi_read_log_data[0:0] + end + attribute \src "libresoc.v:50087.3-50088.55" + process $proc$libresoc.v:50087$3353 + assign { } { } + assign $0\dmi_read_log_data_1[0:0] \dmi_read_log_data_1$next + sync posedge \clk + update \dmi_read_log_data_1 $0\dmi_read_log_data_1[0:0] + end + attribute \src "libresoc.v:50089.3-50090.41" + process $proc$libresoc.v:50089$3354 + assign { } { } + assign $0\log_dmi_addr[31:0] \log_dmi_addr$next + sync posedge \clk + update \log_dmi_addr $0\log_dmi_addr[31:0] + end + attribute \src "libresoc.v:50091.3-50092.37" + process $proc$libresoc.v:50091$3355 + assign { } { } + assign $0\gspr_index[6:0] \gspr_index$next + sync posedge \clk + update \gspr_index $0\gspr_index[6:0] + end + attribute \src "libresoc.v:50093.3-50094.33" + process $proc$libresoc.v:50093$3356 + assign { } { } + assign $0\stopping[0:0] \stopping$next + sync posedge \clk + update \stopping $0\stopping[0:0] + end + attribute \src "libresoc.v:50095.3-50096.37" + process $proc$libresoc.v:50095$3357 + assign { } { } + assign $0\terminated[0:0] \terminated$next + sync posedge \clk + update \terminated $0\terminated[0:0] + end + attribute \src "libresoc.v:50097.3-50098.39" + process $proc$libresoc.v:50097$3358 + assign { } { } + assign $0\dmi_req_i_1[0:0] \dmi_req_i_1$next + sync posedge \clk + update \dmi_req_i_1 $0\dmi_req_i_1[0:0] + end + attribute \src "libresoc.v:50099.3-50100.43" + process $proc$libresoc.v:50099$3359 + assign { } { } + assign $0\do_dmi_log_rd[0:0] \do_dmi_log_rd$next + sync posedge \clk + update \do_dmi_log_rd $0\do_dmi_log_rd[0:0] + end + attribute \src "libresoc.v:50101.3-50102.37" + process $proc$libresoc.v:50101$3360 + assign { } { } + assign $0\do_icreset[0:0] \do_icreset$next + sync posedge \clk + update \do_icreset $0\do_icreset[0:0] + end + attribute \src "libresoc.v:50103.3-50104.33" + process $proc$libresoc.v:50103$3361 + assign { } { } + assign $0\do_reset[0:0] \do_reset$next + sync posedge \clk + update \do_reset $0\do_reset[0:0] + end + attribute \src "libresoc.v:50105.3-50106.31" + process $proc$libresoc.v:50105$3362 + assign { } { } + assign $0\do_step[0:0] \do_step$next + sync posedge \clk + update \do_step $0\do_step[0:0] + end + attribute \src "libresoc.v:50107.3-50124.6" + process $proc$libresoc.v:50107$3363 + assign { } { } + assign $0\dmi_ack_o[0:0] $1\dmi_ack_o[0:0] + attribute \src "libresoc.v:50108.5-50108.29" + switch \initial + attribute \src "libresoc.v:50108.9-50108.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:154" + switch \dmi_addr_i + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dmi_ack_o[0:0] \d_gpr_ack + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dmi_ack_o[0:0] \d_cr_ack + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dmi_ack_o[0:0] \d_xer_ack + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\dmi_ack_o[0:0] \dmi_req_i + end + sync always + update \dmi_ack_o $0\dmi_ack_o[0:0] + end + attribute \src "libresoc.v:50125.3-50134.6" + process $proc$libresoc.v:50125$3364 + assign { } { } + assign { } { } + assign $0\d_gpr_req[0:0] $1\d_gpr_req[0:0] + attribute \src "libresoc.v:50126.5-50126.29" + switch \initial + attribute \src "libresoc.v:50126.9-50126.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:154" + switch \dmi_addr_i + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\d_gpr_req[0:0] \dmi_req_i + case + assign $1\d_gpr_req[0:0] 1'0 + end + sync always + update \d_gpr_req $0\d_gpr_req[0:0] + end + attribute \src "libresoc.v:50135.3-50143.6" + process $proc$libresoc.v:50135$3365 + assign { } { } + assign { } { } + assign $0\dmi_req_i_1$next[0:0]$3366 $1\dmi_req_i_1$next[0:0]$3367 + attribute \src "libresoc.v:50136.5-50136.29" + switch \initial + attribute \src "libresoc.v:50136.9-50136.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dmi_req_i_1$next[0:0]$3367 1'0 + case + assign $1\dmi_req_i_1$next[0:0]$3367 \dmi_req_i + end + sync always + update \dmi_req_i_1$next $0\dmi_req_i_1$next[0:0]$3366 + end + attribute \src "libresoc.v:50144.3-50193.6" + process $proc$libresoc.v:50144$3368 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\terminated$next[0:0]$3369 $8\terminated$next[0:0]$3377 + attribute \src "libresoc.v:50145.5-50145.29" + switch \initial + attribute \src "libresoc.v:50145.9-50145.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + switch { \$65 \$61 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\terminated$next[0:0]$3370 $2\terminated$next[0:0]$3371 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201" + switch \dmi_we_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\terminated$next[0:0]$3371 $3\terminated$next[0:0]$3372 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" + switch { \$71 \$69 \$67 } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign { } { } + assign { } { } + assign { } { } + assign $3\terminated$next[0:0]$3372 $6\terminated$next[0:0]$3375 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:208" + switch \dmi_din [1] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\terminated$next[0:0]$3373 1'0 + case + assign $4\terminated$next[0:0]$3373 \terminated + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:213" + switch \dmi_din [3] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\terminated$next[0:0]$3374 1'0 + case + assign $5\terminated$next[0:0]$3374 $4\terminated$next[0:0]$3373 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:218" + switch \dmi_din [4] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\terminated$next[0:0]$3375 1'0 + case + assign $6\terminated$next[0:0]$3375 $5\terminated$next[0:0]$3374 + end + case + assign $3\terminated$next[0:0]$3372 \terminated + end + case + assign $2\terminated$next[0:0]$3371 \terminated + end + case + assign $1\terminated$next[0:0]$3370 \terminated + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:247" + switch \terminate_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\terminated$next[0:0]$3376 1'1 + case + assign $7\terminated$next[0:0]$3376 $1\terminated$next[0:0]$3370 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $8\terminated$next[0:0]$3377 1'0 + case + assign $8\terminated$next[0:0]$3377 $7\terminated$next[0:0]$3376 + end + sync always + update \terminated$next $0\terminated$next[0:0]$3369 + end + attribute \src "libresoc.v:50194.3-50237.6" + process $proc$libresoc.v:50194$3378 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\stopping$next[0:0]$3379 $7\stopping$next[0:0]$3386 + attribute \src "libresoc.v:50195.5-50195.29" + switch \initial + attribute \src "libresoc.v:50195.9-50195.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + switch { \$79 \$75 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\stopping$next[0:0]$3380 $2\stopping$next[0:0]$3381 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201" + switch \dmi_we_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\stopping$next[0:0]$3381 $3\stopping$next[0:0]$3382 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" + switch { \$85 \$83 \$81 } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign { } { } + assign { } { } + assign $3\stopping$next[0:0]$3382 $5\stopping$next[0:0]$3384 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:211" + switch \dmi_din [0] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\stopping$next[0:0]$3383 1'1 + case + assign $4\stopping$next[0:0]$3383 \stopping + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:218" + switch \dmi_din [4] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\stopping$next[0:0]$3384 1'0 + case + assign $5\stopping$next[0:0]$3384 $4\stopping$next[0:0]$3383 + end + case + assign $3\stopping$next[0:0]$3382 \stopping + end + case + assign $2\stopping$next[0:0]$3381 \stopping + end + case + assign $1\stopping$next[0:0]$3380 \stopping + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:247" + switch \terminate_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\stopping$next[0:0]$3385 1'1 + case + assign $6\stopping$next[0:0]$3385 $1\stopping$next[0:0]$3380 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\stopping$next[0:0]$3386 1'0 + case + assign $7\stopping$next[0:0]$3386 $6\stopping$next[0:0]$3385 + end + sync always + update \stopping$next $0\stopping$next[0:0]$3379 + end + attribute \src "libresoc.v:50238.3-50265.6" + process $proc$libresoc.v:50238$3387 + assign { } { } + assign { } { } + assign { } { } + assign $0\gspr_index$next[6:0]$3388 $4\gspr_index$next[6:0]$3392 + attribute \src "libresoc.v:50239.5-50239.29" + switch \initial + attribute \src "libresoc.v:50239.9-50239.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + switch { \$93 \$89 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\gspr_index$next[6:0]$3389 $2\gspr_index$next[6:0]$3390 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201" + switch \dmi_we_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\gspr_index$next[6:0]$3390 $3\gspr_index$next[6:0]$3391 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" + switch { \$99 \$97 \$95 } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign $3\gspr_index$next[6:0]$3391 \gspr_index + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- + assign { } { } + assign $3\gspr_index$next[6:0]$3391 \dmi_din [6:0] + case + assign $3\gspr_index$next[6:0]$3391 \gspr_index + end + case + assign $2\gspr_index$next[6:0]$3390 \gspr_index + end + case + assign $1\gspr_index$next[6:0]$3389 \gspr_index + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\gspr_index$next[6:0]$3392 7'0000000 + case + assign $4\gspr_index$next[6:0]$3392 $1\gspr_index$next[6:0]$3389 + end + sync always + update \gspr_index$next $0\gspr_index$next[6:0]$3388 + end + attribute \src "libresoc.v:50266.3-50299.6" + process $proc$libresoc.v:50266$3393 + assign { } { } + assign { } { } + assign { } { } + assign $0\log_dmi_addr$next[31:0]$3394 $4\log_dmi_addr$next[31:0]$3398 + attribute \src "libresoc.v:50267.5-50267.29" + switch \initial + attribute \src "libresoc.v:50267.9-50267.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + switch { \$107 \$103 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\log_dmi_addr$next[31:0]$3395 $2\log_dmi_addr$next[31:0]$3396 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201" + switch \dmi_we_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\log_dmi_addr$next[31:0]$3396 $3\log_dmi_addr$next[31:0]$3397 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" + switch { \$113 \$111 \$109 } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign $3\log_dmi_addr$next[31:0]$3397 \log_dmi_addr + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- + assign $3\log_dmi_addr$next[31:0]$3397 \log_dmi_addr + attribute \src "libresoc.v:0.0-0.0" + case 3'1-- + assign { } { } + assign $3\log_dmi_addr$next[31:0]$3397 \dmi_din [31:0] + case + assign $3\log_dmi_addr$next[31:0]$3397 \log_dmi_addr + end + case + assign $2\log_dmi_addr$next[31:0]$3396 \log_dmi_addr + end + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign $1\log_dmi_addr$next[31:0]$3395 [31:2] \log_dmi_addr [31:2] + assign $1\log_dmi_addr$next[31:0]$3395 [1:0] \$115 [1:0] + case + assign $1\log_dmi_addr$next[31:0]$3395 \log_dmi_addr + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\log_dmi_addr$next[31:0]$3398 0 + case + assign $4\log_dmi_addr$next[31:0]$3398 $1\log_dmi_addr$next[31:0]$3395 + end + sync always + update \log_dmi_addr$next $0\log_dmi_addr$next[31:0]$3394 + end + attribute \src "libresoc.v:50300.3-50308.6" + process $proc$libresoc.v:50300$3399 + assign { } { } + assign { } { } + assign $0\dmi_read_log_data_1$next[0:0]$3400 $1\dmi_read_log_data_1$next[0:0]$3401 + attribute \src "libresoc.v:50301.5-50301.29" + switch \initial + attribute \src "libresoc.v:50301.9-50301.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dmi_read_log_data_1$next[0:0]$3401 1'0 + case + assign $1\dmi_read_log_data_1$next[0:0]$3401 \dmi_read_log_data + end + sync always + update \dmi_read_log_data_1$next $0\dmi_read_log_data_1$next[0:0]$3400 + end + attribute \src "libresoc.v:50309.3-50317.6" + process $proc$libresoc.v:50309$3402 + assign { } { } + assign { } { } + assign $0\dmi_read_log_data$next[0:0]$3403 $1\dmi_read_log_data$next[0:0]$3404 + attribute \src "libresoc.v:50310.5-50310.29" + switch \initial + attribute \src "libresoc.v:50310.9-50310.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dmi_read_log_data$next[0:0]$3404 1'0 + case + assign $1\dmi_read_log_data$next[0:0]$3404 \$120 + end + sync always + update \dmi_read_log_data$next $0\dmi_read_log_data$next[0:0]$3403 + end + attribute \src "libresoc.v:50318.3-50327.6" + process $proc$libresoc.v:50318$3405 + assign { } { } + assign { } { } + assign $0\d_cr_req[0:0] $1\d_cr_req[0:0] + attribute \src "libresoc.v:50319.5-50319.29" + switch \initial + attribute \src "libresoc.v:50319.9-50319.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:154" + switch \dmi_addr_i + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\d_cr_req[0:0] \dmi_req_i + case + assign $1\d_cr_req[0:0] 1'0 + end + sync always + update \d_cr_req $0\d_cr_req[0:0] + end + attribute \src "libresoc.v:50328.3-50337.6" + process $proc$libresoc.v:50328$3406 + assign { } { } + assign { } { } + assign $0\d_xer_req[0:0] $1\d_xer_req[0:0] + attribute \src "libresoc.v:50329.5-50329.29" + switch \initial + attribute \src "libresoc.v:50329.9-50329.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:154" + switch \dmi_addr_i + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\d_xer_req[0:0] \dmi_req_i + case + assign $1\d_xer_req[0:0] 1'0 + end + sync always + update \d_xer_req $0\d_xer_req[0:0] + end + attribute \src "libresoc.v:50338.3-50368.6" + process $proc$libresoc.v:50338$3407 + assign { } { } + assign { } { } + assign $0\dmi_dout[63:0] $1\dmi_dout[63:0] + attribute \src "libresoc.v:50339.5-50339.29" + switch \initial + attribute \src "libresoc.v:50339.9-50339.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:173" + switch \dmi_addr_i + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dmi_dout[63:0] \stat_reg + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dmi_dout[63:0] \core_dbg_pc + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dmi_dout[63:0] \core_dbg_msr + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dmi_dout[63:0] \d_gpr_data + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dmi_dout[63:0] { \log_write_addr_o \log_dmi_addr } + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dmi_dout[63:0] \log_dmi_data + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dmi_dout[63:0] \d_cr_data + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dmi_dout[63:0] \d_xer_data + case + assign $1\dmi_dout[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \dmi_dout $0\dmi_dout[63:0] + end + attribute \src "libresoc.v:50369.3-50398.6" + process $proc$libresoc.v:50369$3408 + assign { } { } + assign { } { } + assign { } { } + assign $0\do_step$next[0:0]$3409 $5\do_step$next[0:0]$3414 + attribute \src "libresoc.v:50370.5-50370.29" + switch \initial + attribute \src "libresoc.v:50370.9-50370.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + switch { \$9 \$5 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\do_step$next[0:0]$3410 $2\do_step$next[0:0]$3411 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201" + switch \dmi_we_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\do_step$next[0:0]$3411 $3\do_step$next[0:0]$3412 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" + switch { \$15 \$13 \$11 } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign { } { } + assign $3\do_step$next[0:0]$3412 $4\do_step$next[0:0]$3413 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:213" + switch \dmi_din [3] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\do_step$next[0:0]$3413 1'1 + case + assign $4\do_step$next[0:0]$3413 1'0 + end + case + assign $3\do_step$next[0:0]$3412 1'0 + end + case + assign $2\do_step$next[0:0]$3411 1'0 + end + case + assign $1\do_step$next[0:0]$3410 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\do_step$next[0:0]$3414 1'0 + case + assign $5\do_step$next[0:0]$3414 $1\do_step$next[0:0]$3410 + end + sync always + update \do_step$next $0\do_step$next[0:0]$3409 + end + attribute \src "libresoc.v:50399.3-50428.6" + process $proc$libresoc.v:50399$3415 + assign { } { } + assign { } { } + assign { } { } + assign $0\do_reset$next[0:0]$3416 $5\do_reset$next[0:0]$3421 + attribute \src "libresoc.v:50400.5-50400.29" + switch \initial + attribute \src "libresoc.v:50400.9-50400.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + switch { \$23 \$19 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\do_reset$next[0:0]$3417 $2\do_reset$next[0:0]$3418 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201" + switch \dmi_we_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\do_reset$next[0:0]$3418 $3\do_reset$next[0:0]$3419 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" + switch { \$29 \$27 \$25 } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign { } { } + assign $3\do_reset$next[0:0]$3419 $4\do_reset$next[0:0]$3420 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:208" + switch \dmi_din [1] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\do_reset$next[0:0]$3420 1'1 + case + assign $4\do_reset$next[0:0]$3420 1'0 + end + case + assign $3\do_reset$next[0:0]$3419 1'0 + end + case + assign $2\do_reset$next[0:0]$3418 1'0 + end + case + assign $1\do_reset$next[0:0]$3417 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\do_reset$next[0:0]$3421 1'0 + case + assign $5\do_reset$next[0:0]$3421 $1\do_reset$next[0:0]$3417 + end + sync always + update \do_reset$next $0\do_reset$next[0:0]$3416 + end + attribute \src "libresoc.v:50429.3-50458.6" + process $proc$libresoc.v:50429$3422 + assign { } { } + assign { } { } + assign { } { } + assign $0\do_icreset$next[0:0]$3423 $5\do_icreset$next[0:0]$3428 + attribute \src "libresoc.v:50430.5-50430.29" + switch \initial + attribute \src "libresoc.v:50430.9-50430.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + switch { \$37 \$33 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\do_icreset$next[0:0]$3424 $2\do_icreset$next[0:0]$3425 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201" + switch \dmi_we_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\do_icreset$next[0:0]$3425 $3\do_icreset$next[0:0]$3426 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" + switch { \$43 \$41 \$39 } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign { } { } + assign $3\do_icreset$next[0:0]$3426 $4\do_icreset$next[0:0]$3427 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:216" + switch \dmi_din [2] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\do_icreset$next[0:0]$3427 1'1 + case + assign $4\do_icreset$next[0:0]$3427 1'0 + end + case + assign $3\do_icreset$next[0:0]$3426 1'0 + end + case + assign $2\do_icreset$next[0:0]$3425 1'0 + end + case + assign $1\do_icreset$next[0:0]$3424 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\do_icreset$next[0:0]$3428 1'0 + case + assign $5\do_icreset$next[0:0]$3428 $1\do_icreset$next[0:0]$3424 + end + sync always + update \do_icreset$next $0\do_icreset$next[0:0]$3423 + end + attribute \src "libresoc.v:50459.3-50492.6" + process $proc$libresoc.v:50459$3429 + assign { } { } + assign { } { } + assign { } { } + assign $0\do_dmi_log_rd$next[0:0]$3430 $4\do_dmi_log_rd$next[0:0]$3434 + attribute \src "libresoc.v:50460.5-50460.29" + switch \initial + attribute \src "libresoc.v:50460.9-50460.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + switch { \$51 \$47 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\do_dmi_log_rd$next[0:0]$3431 $2\do_dmi_log_rd$next[0:0]$3432 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201" + switch \dmi_we_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\do_dmi_log_rd$next[0:0]$3432 $3\do_dmi_log_rd$next[0:0]$3433 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" + switch { \$57 \$55 \$53 } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign $3\do_dmi_log_rd$next[0:0]$3433 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- + assign $3\do_dmi_log_rd$next[0:0]$3433 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 3'1-- + assign { } { } + assign $3\do_dmi_log_rd$next[0:0]$3433 1'1 + case + assign $3\do_dmi_log_rd$next[0:0]$3433 1'0 + end + case + assign $2\do_dmi_log_rd$next[0:0]$3432 1'0 + end + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\do_dmi_log_rd$next[0:0]$3431 1'1 + case + assign $1\do_dmi_log_rd$next[0:0]$3431 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\do_dmi_log_rd$next[0:0]$3434 1'0 + case + assign $4\do_dmi_log_rd$next[0:0]$3434 $1\do_dmi_log_rd$next[0:0]$3431 + end + sync always + update \do_dmi_log_rd$next $0\do_dmi_log_rd$next[0:0]$3430 + end + connect \$9 $and$libresoc.v:50023$3290_Y + connect \$99 $eq$libresoc.v:50024$3291_Y + connect \$101 $not$libresoc.v:50025$3292_Y + connect \$103 $and$libresoc.v:50026$3293_Y + connect \$105 $not$libresoc.v:50027$3294_Y + connect \$107 $and$libresoc.v:50028$3295_Y + connect \$109 $eq$libresoc.v:50029$3296_Y + connect \$111 $eq$libresoc.v:50030$3297_Y + connect \$113 $eq$libresoc.v:50031$3298_Y + connect \$116 $add$libresoc.v:50032$3299_Y + connect \$118 $eq$libresoc.v:50033$3300_Y + connect \$11 $eq$libresoc.v:50034$3301_Y + connect \$120 $and$libresoc.v:50035$3302_Y + connect \$122 $not$libresoc.v:50036$3303_Y + connect \$124 $and$libresoc.v:50037$3304_Y + connect \$13 $eq$libresoc.v:50038$3305_Y + connect \$15 $eq$libresoc.v:50039$3306_Y + connect \$17 $not$libresoc.v:50040$3307_Y + connect \$1 $pos$libresoc.v:50041$3308_Y + connect \$19 $and$libresoc.v:50042$3309_Y + connect \$21 $not$libresoc.v:50043$3310_Y + connect \$23 $and$libresoc.v:50044$3311_Y + connect \$25 $eq$libresoc.v:50045$3312_Y + connect \$27 $eq$libresoc.v:50046$3313_Y + connect \$29 $eq$libresoc.v:50047$3314_Y + connect \$31 $not$libresoc.v:50048$3315_Y + connect \$33 $and$libresoc.v:50049$3316_Y + connect \$35 $not$libresoc.v:50050$3317_Y + connect \$37 $and$libresoc.v:50051$3318_Y + connect \$3 $not$libresoc.v:50052$3319_Y + connect \$39 $eq$libresoc.v:50053$3320_Y + connect \$41 $eq$libresoc.v:50054$3321_Y + connect \$43 $eq$libresoc.v:50055$3322_Y + connect \$45 $not$libresoc.v:50056$3323_Y + connect \$47 $and$libresoc.v:50057$3324_Y + connect \$49 $not$libresoc.v:50058$3325_Y + connect \$51 $and$libresoc.v:50059$3326_Y + connect \$53 $eq$libresoc.v:50060$3327_Y + connect \$55 $eq$libresoc.v:50061$3328_Y + connect \$57 $eq$libresoc.v:50062$3329_Y + connect \$5 $and$libresoc.v:50063$3330_Y + connect \$59 $not$libresoc.v:50064$3331_Y + connect \$61 $and$libresoc.v:50065$3332_Y + connect \$63 $not$libresoc.v:50066$3333_Y + connect \$65 $and$libresoc.v:50067$3334_Y + connect \$67 $eq$libresoc.v:50068$3335_Y + connect \$69 $eq$libresoc.v:50069$3336_Y + connect \$71 $eq$libresoc.v:50070$3337_Y + connect \$73 $not$libresoc.v:50071$3338_Y + connect \$75 $and$libresoc.v:50072$3339_Y + connect \$77 $not$libresoc.v:50073$3340_Y + connect \$7 $not$libresoc.v:50074$3341_Y + connect \$79 $and$libresoc.v:50075$3342_Y + connect \$81 $eq$libresoc.v:50076$3343_Y + connect \$83 $eq$libresoc.v:50077$3344_Y + connect \$85 $eq$libresoc.v:50078$3345_Y + connect \$87 $not$libresoc.v:50079$3346_Y + connect \$89 $and$libresoc.v:50080$3347_Y + connect \$91 $not$libresoc.v:50081$3348_Y + connect \$93 $and$libresoc.v:50082$3349_Y + connect \$95 $eq$libresoc.v:50083$3350_Y + connect \$97 $eq$libresoc.v:50084$3351_Y + connect \$115 \$116 + connect \log_write_addr_o 0 + connect \log_dmi_data 64'0000000000000000000000000000000000000000000000000000000000000000 + connect \terminated_o \terminated + connect \icache_rst_o \do_icreset + connect \core_rst_o \do_reset + connect \core_stop_o \$124 + connect \d_gpr_addr \gspr_index + connect \stat_reg \$1 +end +attribute \src "libresoc.v:50506.1-52521.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_ALU.dec" +attribute \generator "nMigen" +module \dec + attribute \src "libresoc.v:52089.3-52122.6" + wire width 3 $0\ALU_cr_in[2:0] + attribute \src "libresoc.v:52123.3-52156.6" + wire width 3 $0\ALU_cr_out[2:0] + attribute \src "libresoc.v:51749.3-51782.6" + wire width 2 $0\ALU_cry_in[1:0] + attribute \src "libresoc.v:51851.3-51884.6" + wire $0\ALU_cry_out[0:0] + attribute \src "libresoc.v:51953.3-51986.6" + wire width 12 $0\ALU_function_unit[11:0] + attribute \src "libresoc.v:52021.3-52054.6" + wire width 3 $0\ALU_in1_sel[2:0] + attribute \src "libresoc.v:52055.3-52088.6" + wire width 4 $0\ALU_in2_sel[3:0] + attribute \src "libresoc.v:51987.3-52020.6" + wire width 7 $0\ALU_internal_op[6:0] + attribute \src "libresoc.v:51783.3-51816.6" + wire $0\ALU_inv_a[0:0] + attribute \src "libresoc.v:51817.3-51850.6" + wire $0\ALU_inv_out[0:0] + attribute \src "libresoc.v:51885.3-51918.6" + wire $0\ALU_is_32b[0:0] + attribute \src "libresoc.v:52157.3-52190.6" + wire width 4 $0\ALU_ldst_len[3:0] + attribute \src "libresoc.v:51715.3-51748.6" + wire width 2 $0\ALU_rc_sel[1:0] + attribute \src "libresoc.v:51919.3-51952.6" + wire $0\ALU_sgn[0:0] + attribute \src "libresoc.v:50507.7-50507.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:52089.3-52122.6" + wire width 3 $1\ALU_cr_in[2:0] + attribute \src "libresoc.v:52123.3-52156.6" + wire width 3 $1\ALU_cr_out[2:0] + attribute \src "libresoc.v:51749.3-51782.6" + wire width 2 $1\ALU_cry_in[1:0] + attribute \src "libresoc.v:51851.3-51884.6" + wire $1\ALU_cry_out[0:0] + attribute \src "libresoc.v:51953.3-51986.6" + wire width 12 $1\ALU_function_unit[11:0] + attribute \src "libresoc.v:52021.3-52054.6" + wire width 3 $1\ALU_in1_sel[2:0] + attribute \src "libresoc.v:52055.3-52088.6" + wire width 4 $1\ALU_in2_sel[3:0] + attribute \src "libresoc.v:51987.3-52020.6" + wire width 7 $1\ALU_internal_op[6:0] + attribute \src "libresoc.v:51783.3-51816.6" + wire $1\ALU_inv_a[0:0] + attribute \src "libresoc.v:51817.3-51850.6" + wire $1\ALU_inv_out[0:0] + attribute \src "libresoc.v:51885.3-51918.6" + wire $1\ALU_is_32b[0:0] + attribute \src "libresoc.v:52157.3-52190.6" + wire width 4 $1\ALU_ldst_len[3:0] + attribute \src "libresoc.v:51715.3-51748.6" + wire width 2 $1\ALU_rc_sel[1:0] + attribute \src "libresoc.v:51919.3-51952.6" + wire $1\ALU_sgn[0:0] + attribute \src "libresoc.v:51680.17-51680.211" + wire width 32 $ternary$libresoc.v:51680$3447_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:478" + wire width 32 \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire \ALU_AA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 output 27 \ALU_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 output 26 \ALU_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 output 32 \ALU_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 14 output 25 \ALU_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 3 \ALU_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 2 \ALU_BH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 output 30 \ALU_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \ALU_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 output 28 \ALU_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 10 \ALU_CR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 16 \ALU_D + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 14 output 31 \ALU_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 8 output 29 \ALU_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire \ALU_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 24 output 22 \ALU_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire \ALU_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \ALU_MB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \ALU_MB32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \ALU_ME + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \ALU_ME32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire output 24 \ALU_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 output 17 \ALU_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \ALU_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \ALU_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \ALU_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire output 23 \ALU_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \ALU_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 output 20 \ALU_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 16 output 18 \ALU_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 10 \ALU_SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \ALU_TO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 16 output 19 \ALU_UI + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 4 \ALU_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \ALU_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 13 \ALU_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 14 \ALU_cry_out + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \ALU_dec19_ALU_dec19_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \ALU_dec19_ALU_dec19_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \ALU_dec19_ALU_dec19_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \ALU_dec19_ALU_dec19_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \ALU_dec19_ALU_dec19_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \ALU_dec19_ALU_dec19_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \ALU_dec19_ALU_dec19_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 \ALU_dec19_ALU_dec19_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \ALU_dec19_ALU_dec19_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \ALU_dec19_ALU_dec19_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \ALU_dec19_ALU_dec19_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \ALU_dec19_ALU_dec19_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \ALU_dec19_ALU_dec19_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \ALU_dec19_ALU_dec19_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \ALU_dec19_opcode_in + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \ALU_dec31_ALU_dec31_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \ALU_dec31_ALU_dec31_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \ALU_dec31_ALU_dec31_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \ALU_dec31_ALU_dec31_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \ALU_dec31_ALU_dec31_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \ALU_dec31_ALU_dec31_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \ALU_dec31_ALU_dec31_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 \ALU_dec31_ALU_dec31_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \ALU_dec31_ALU_dec31_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \ALU_dec31_ALU_dec31_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \ALU_dec31_ALU_dec31_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \ALU_dec31_ALU_dec31_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \ALU_dec31_ALU_dec31_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \ALU_dec31_ALU_dec31_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \ALU_dec31_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 7 \ALU_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 8 \ALU_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 9 \ALU_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 6 \ALU_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 11 \ALU_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 12 \ALU_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 15 \ALU_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 10 \ALU_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 3 \ALU_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 16 \ALU_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 6 output 21 \ALU_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_FRC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \A_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \B_AA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 14 \B_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \B_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \B_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \B_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DQE_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DQE_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \DQE_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 12 \DQ_DQ + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \DQ_PT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DQ_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DQ_RTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DQ_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \DQ_SX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \DQ_SX_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DQ_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \DQ_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \DQ_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \DQ_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 14 \DS_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_FRSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_RSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_VRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \DS_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DX_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \DX_d0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 16 \DX_d0_d1_d2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DX_d1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \DX_d2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \D_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 16 \D_D + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \D_FRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \D_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \D_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \D_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \D_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \D_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 16 \D_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \D_TO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 16 \D_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \EVS_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \I_AA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 24 \I_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \I_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MDS_IB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MDS_IS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MDS_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MDS_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MDS_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \MDS_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \MDS_XBI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \MDS_XBI_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \MDS_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \MDS_mb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \MDS_me + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MD_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MD_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \MD_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \MD_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \MD_mb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \MD_me + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \MD_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \M_MB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \M_ME + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \M_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \M_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \M_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \M_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \M_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 7 \SC_LEV + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \SC_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \SC_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \TX_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \TX_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \TX_XBI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \TX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_RC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \VA_SHB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_VRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_VRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_VRC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \VA_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \VC_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VC_VRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VC_VRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VC_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \VC_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_EO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \VX_PS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_SIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_UIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \VX_UIM_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \VX_UIM_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \VX_UIM_3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_VRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_VRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \VX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 11 \VX_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 8 \XFL_FLM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XFL_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XFL_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XFL_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XFL_W + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \XFL_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \XFX_BHRBE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XFX_DUI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \XFX_DUIS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 8 \XFX_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XFX_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XFX_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \XFX_SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \XFX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XL_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XL_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \XL_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \XL_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \XL_BH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XL_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XL_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XL_BO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 output 35 \XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XL_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 15 \XL_OC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XL_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \XL_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XO_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XO_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XO_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XO_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XO_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 9 \XO_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XS_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XS_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XS_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 9 \XS_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XS_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX2_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \XX2_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX2_BX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX2_BX_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 7 \XX2_DCMX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX2_EO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX2_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX2_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX2_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX2_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \XX2_UIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \XX2_UIM_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 7 \XX2_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 9 \XX2_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX2_dc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 7 \XX2_dc_dm_dx + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX2_dm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX2_dx + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX3_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX3_AX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX3_AX_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX3_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \XX3_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX3_BX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX3_BX_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \XX3_DM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX3_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \XX3_SHW + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX3_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX3_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX3_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \XX3_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 8 \XX3_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 9 \XX3_XO_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX4_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX4_AX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX4_AX_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX4_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX4_BX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX4_BX_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX4_C + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX4_CX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX4_CX_C + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX4_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX4_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX4_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \XX4_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 output 33 \X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 output 34 \X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \X_CT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 7 \X_DCMX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \X_DRM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_E + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \X_EO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_EO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_EX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \X_E_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRAp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRBp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \X_IH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 8 \X_IMM8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_L1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \X_L2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \X_L3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_MO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_NB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_PRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_R + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \X_RIC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \X_RM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_RO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_RSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_RTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_R_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \X_SP + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \X_SR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_SX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \X_SX_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \X_TBR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_TH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_TO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \X_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \X_U + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_UIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_VRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_W + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \X_WC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \X_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 8 \X_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \Z22_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \Z22_DCM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \Z22_DGM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z22_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z22_FRAp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z22_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z22_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \Z22_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \Z22_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 9 \Z22_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_FRAp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_FRBp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \Z23_R + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \Z23_RMC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \Z23_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_TE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 8 \Z23_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \all_OPCD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \all_PO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + wire input 1 \bigendian + attribute \src "libresoc.v:50507.7-50507.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 output 2 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 6 \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:442" + wire width 32 input 36 \raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:478" + cell $mux $ternary$libresoc.v:51680$3447 + parameter \WIDTH 32 + connect \A \raw_opcode_in + connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } + connect \S \bigendian + connect \Y $ternary$libresoc.v:51680$3447_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:51681.13-51697.4" + cell \ALU_dec19 \ALU_dec19 + connect \ALU_dec19_cr_in \ALU_dec19_ALU_dec19_cr_in + connect \ALU_dec19_cr_out \ALU_dec19_ALU_dec19_cr_out + connect \ALU_dec19_cry_in \ALU_dec19_ALU_dec19_cry_in + connect \ALU_dec19_cry_out \ALU_dec19_ALU_dec19_cry_out + connect \ALU_dec19_function_unit \ALU_dec19_ALU_dec19_function_unit + connect \ALU_dec19_in1_sel \ALU_dec19_ALU_dec19_in1_sel + connect \ALU_dec19_in2_sel \ALU_dec19_ALU_dec19_in2_sel + connect \ALU_dec19_internal_op \ALU_dec19_ALU_dec19_internal_op + connect \ALU_dec19_inv_a \ALU_dec19_ALU_dec19_inv_a + connect \ALU_dec19_inv_out \ALU_dec19_ALU_dec19_inv_out + connect \ALU_dec19_is_32b \ALU_dec19_ALU_dec19_is_32b + connect \ALU_dec19_ldst_len \ALU_dec19_ALU_dec19_ldst_len + connect \ALU_dec19_rc_sel \ALU_dec19_ALU_dec19_rc_sel + connect \ALU_dec19_sgn \ALU_dec19_ALU_dec19_sgn + connect \opcode_in \ALU_dec19_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:51698.13-51714.4" + cell \ALU_dec31 \ALU_dec31 + connect \ALU_dec31_cr_in \ALU_dec31_ALU_dec31_cr_in + connect \ALU_dec31_cr_out \ALU_dec31_ALU_dec31_cr_out + connect \ALU_dec31_cry_in \ALU_dec31_ALU_dec31_cry_in + connect \ALU_dec31_cry_out \ALU_dec31_ALU_dec31_cry_out + connect \ALU_dec31_function_unit \ALU_dec31_ALU_dec31_function_unit + connect \ALU_dec31_in1_sel \ALU_dec31_ALU_dec31_in1_sel + connect \ALU_dec31_in2_sel \ALU_dec31_ALU_dec31_in2_sel + connect \ALU_dec31_internal_op \ALU_dec31_ALU_dec31_internal_op + connect \ALU_dec31_inv_a \ALU_dec31_ALU_dec31_inv_a + connect \ALU_dec31_inv_out \ALU_dec31_ALU_dec31_inv_out + connect \ALU_dec31_is_32b \ALU_dec31_ALU_dec31_is_32b + connect \ALU_dec31_ldst_len \ALU_dec31_ALU_dec31_ldst_len + connect \ALU_dec31_rc_sel \ALU_dec31_ALU_dec31_rc_sel + connect \ALU_dec31_sgn \ALU_dec31_ALU_dec31_sgn + connect \opcode_in \ALU_dec31_opcode_in + end + attribute \src "libresoc.v:50507.7-50507.20" + process $proc$libresoc.v:50507$3462 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:51715.3-51748.6" + process $proc$libresoc.v:51715$3448 + assign { } { } + assign { } { } + assign $0\ALU_rc_sel[1:0] $1\ALU_rc_sel[1:0] + attribute \src "libresoc.v:51716.5-51716.29" + switch \initial + attribute \src "libresoc.v:51716.9-51716.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\ALU_rc_sel[1:0] \ALU_dec19_ALU_dec19_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\ALU_rc_sel[1:0] \ALU_dec31_ALU_dec31_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\ALU_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\ALU_rc_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\ALU_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\ALU_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\ALU_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\ALU_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\ALU_rc_sel[1:0] 2'00 + case + assign $1\ALU_rc_sel[1:0] 2'00 + end + sync always + update \ALU_rc_sel $0\ALU_rc_sel[1:0] + end + attribute \src "libresoc.v:51749.3-51782.6" + process $proc$libresoc.v:51749$3449 + assign { } { } + assign { } { } + assign $0\ALU_cry_in[1:0] $1\ALU_cry_in[1:0] + attribute \src "libresoc.v:51750.5-51750.29" + switch \initial + attribute \src "libresoc.v:51750.9-51750.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\ALU_cry_in[1:0] \ALU_dec19_ALU_dec19_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\ALU_cry_in[1:0] \ALU_dec31_ALU_dec31_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\ALU_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\ALU_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\ALU_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\ALU_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\ALU_cry_in[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\ALU_cry_in[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\ALU_cry_in[1:0] 2'01 + case + assign $1\ALU_cry_in[1:0] 2'00 + end + sync always + update \ALU_cry_in $0\ALU_cry_in[1:0] + end + attribute \src "libresoc.v:51783.3-51816.6" + process $proc$libresoc.v:51783$3450 + assign { } { } + assign { } { } + assign $0\ALU_inv_a[0:0] $1\ALU_inv_a[0:0] + attribute \src "libresoc.v:51784.5-51784.29" + switch \initial + attribute \src "libresoc.v:51784.9-51784.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\ALU_inv_a[0:0] \ALU_dec19_ALU_dec19_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\ALU_inv_a[0:0] \ALU_dec31_ALU_dec31_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\ALU_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\ALU_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\ALU_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\ALU_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\ALU_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\ALU_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\ALU_inv_a[0:0] 1'1 + case + assign $1\ALU_inv_a[0:0] 1'0 + end + sync always + update \ALU_inv_a $0\ALU_inv_a[0:0] + end + attribute \src "libresoc.v:51817.3-51850.6" + process $proc$libresoc.v:51817$3451 + assign { } { } + assign { } { } + assign $0\ALU_inv_out[0:0] $1\ALU_inv_out[0:0] + attribute \src "libresoc.v:51818.5-51818.29" + switch \initial + attribute \src "libresoc.v:51818.9-51818.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\ALU_inv_out[0:0] \ALU_dec19_ALU_dec19_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\ALU_inv_out[0:0] \ALU_dec31_ALU_dec31_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\ALU_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\ALU_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\ALU_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\ALU_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\ALU_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\ALU_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\ALU_inv_out[0:0] 1'0 + case + assign $1\ALU_inv_out[0:0] 1'0 + end + sync always + update \ALU_inv_out $0\ALU_inv_out[0:0] + end + attribute \src "libresoc.v:51851.3-51884.6" + process $proc$libresoc.v:51851$3452 + assign { } { } + assign { } { } + assign $0\ALU_cry_out[0:0] $1\ALU_cry_out[0:0] + attribute \src "libresoc.v:51852.5-51852.29" + switch \initial + attribute \src "libresoc.v:51852.9-51852.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\ALU_cry_out[0:0] \ALU_dec19_ALU_dec19_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\ALU_cry_out[0:0] \ALU_dec31_ALU_dec31_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\ALU_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\ALU_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\ALU_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\ALU_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\ALU_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\ALU_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\ALU_cry_out[0:0] 1'1 + case + assign $1\ALU_cry_out[0:0] 1'0 + end + sync always + update \ALU_cry_out $0\ALU_cry_out[0:0] + end + attribute \src "libresoc.v:51885.3-51918.6" + process $proc$libresoc.v:51885$3453 + assign { } { } + assign { } { } + assign $0\ALU_is_32b[0:0] $1\ALU_is_32b[0:0] + attribute \src "libresoc.v:51886.5-51886.29" + switch \initial + attribute \src "libresoc.v:51886.9-51886.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\ALU_is_32b[0:0] \ALU_dec19_ALU_dec19_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\ALU_is_32b[0:0] \ALU_dec31_ALU_dec31_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\ALU_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\ALU_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\ALU_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\ALU_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\ALU_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\ALU_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\ALU_is_32b[0:0] 1'0 + case + assign $1\ALU_is_32b[0:0] 1'0 + end + sync always + update \ALU_is_32b $0\ALU_is_32b[0:0] + end + attribute \src "libresoc.v:51919.3-51952.6" + process $proc$libresoc.v:51919$3454 + assign { } { } + assign { } { } + assign $0\ALU_sgn[0:0] $1\ALU_sgn[0:0] + attribute \src "libresoc.v:51920.5-51920.29" + switch \initial + attribute \src "libresoc.v:51920.9-51920.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\ALU_sgn[0:0] \ALU_dec19_ALU_dec19_sgn + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\ALU_sgn[0:0] \ALU_dec31_ALU_dec31_sgn + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\ALU_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\ALU_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\ALU_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\ALU_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\ALU_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\ALU_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\ALU_sgn[0:0] 1'0 + case + assign $1\ALU_sgn[0:0] 1'0 + end + sync always + update \ALU_sgn $0\ALU_sgn[0:0] + end + attribute \src "libresoc.v:51953.3-51986.6" + process $proc$libresoc.v:51953$3455 + assign { } { } + assign { } { } + assign $0\ALU_function_unit[11:0] $1\ALU_function_unit[11:0] + attribute \src "libresoc.v:51954.5-51954.29" + switch \initial + attribute \src "libresoc.v:51954.9-51954.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\ALU_function_unit[11:0] \ALU_dec19_ALU_dec19_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\ALU_function_unit[11:0] \ALU_dec31_ALU_dec31_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\ALU_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\ALU_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\ALU_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\ALU_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\ALU_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\ALU_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\ALU_function_unit[11:0] 12'000000000010 + case + assign $1\ALU_function_unit[11:0] 12'000000000000 + end + sync always + update \ALU_function_unit $0\ALU_function_unit[11:0] + end + attribute \src "libresoc.v:51987.3-52020.6" + process $proc$libresoc.v:51987$3456 + assign { } { } + assign { } { } + assign $0\ALU_internal_op[6:0] $1\ALU_internal_op[6:0] + attribute \src "libresoc.v:51988.5-51988.29" + switch \initial + attribute \src "libresoc.v:51988.9-51988.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\ALU_internal_op[6:0] \ALU_dec19_ALU_dec19_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\ALU_internal_op[6:0] \ALU_dec31_ALU_dec31_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\ALU_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\ALU_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\ALU_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\ALU_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\ALU_internal_op[6:0] 7'0001010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\ALU_internal_op[6:0] 7'0001010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\ALU_internal_op[6:0] 7'0000010 + case + assign $1\ALU_internal_op[6:0] 7'0000000 + end + sync always + update \ALU_internal_op $0\ALU_internal_op[6:0] + end + attribute \src "libresoc.v:52021.3-52054.6" + process $proc$libresoc.v:52021$3457 + assign { } { } + assign { } { } + assign $0\ALU_in1_sel[2:0] $1\ALU_in1_sel[2:0] + attribute \src "libresoc.v:52022.5-52022.29" + switch \initial + attribute \src "libresoc.v:52022.9-52022.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\ALU_in1_sel[2:0] \ALU_dec19_ALU_dec19_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\ALU_in1_sel[2:0] \ALU_dec31_ALU_dec31_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\ALU_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\ALU_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\ALU_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\ALU_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\ALU_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\ALU_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\ALU_in1_sel[2:0] 3'001 + case + assign $1\ALU_in1_sel[2:0] 3'000 + end + sync always + update \ALU_in1_sel $0\ALU_in1_sel[2:0] + end + attribute \src "libresoc.v:52055.3-52088.6" + process $proc$libresoc.v:52055$3458 + assign { } { } + assign { } { } + assign $0\ALU_in2_sel[3:0] $1\ALU_in2_sel[3:0] + attribute \src "libresoc.v:52056.5-52056.29" + switch \initial + attribute \src "libresoc.v:52056.9-52056.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\ALU_in2_sel[3:0] \ALU_dec19_ALU_dec19_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\ALU_in2_sel[3:0] \ALU_dec31_ALU_dec31_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\ALU_in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\ALU_in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\ALU_in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\ALU_in2_sel[3:0] 4'0101 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\ALU_in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\ALU_in2_sel[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\ALU_in2_sel[3:0] 4'0011 + case + assign $1\ALU_in2_sel[3:0] 4'0000 + end + sync always + update \ALU_in2_sel $0\ALU_in2_sel[3:0] + end + attribute \src "libresoc.v:52089.3-52122.6" + process $proc$libresoc.v:52089$3459 + assign { } { } + assign { } { } + assign $0\ALU_cr_in[2:0] $1\ALU_cr_in[2:0] + attribute \src "libresoc.v:52090.5-52090.29" + switch \initial + attribute \src "libresoc.v:52090.9-52090.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\ALU_cr_in[2:0] \ALU_dec19_ALU_dec19_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\ALU_cr_in[2:0] \ALU_dec31_ALU_dec31_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\ALU_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\ALU_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\ALU_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\ALU_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\ALU_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\ALU_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\ALU_cr_in[2:0] 3'000 + case + assign $1\ALU_cr_in[2:0] 3'000 + end + sync always + update \ALU_cr_in $0\ALU_cr_in[2:0] + end + attribute \src "libresoc.v:52123.3-52156.6" + process $proc$libresoc.v:52123$3460 + assign { } { } + assign { } { } + assign $0\ALU_cr_out[2:0] $1\ALU_cr_out[2:0] + attribute \src "libresoc.v:52124.5-52124.29" + switch \initial + attribute \src "libresoc.v:52124.9-52124.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\ALU_cr_out[2:0] \ALU_dec19_ALU_dec19_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\ALU_cr_out[2:0] \ALU_dec31_ALU_dec31_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\ALU_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\ALU_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\ALU_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\ALU_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\ALU_cr_out[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\ALU_cr_out[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\ALU_cr_out[2:0] 3'000 + case + assign $1\ALU_cr_out[2:0] 3'000 + end + sync always + update \ALU_cr_out $0\ALU_cr_out[2:0] + end + attribute \src "libresoc.v:52157.3-52190.6" + process $proc$libresoc.v:52157$3461 + assign { } { } + assign { } { } + assign $0\ALU_ldst_len[3:0] $1\ALU_ldst_len[3:0] + attribute \src "libresoc.v:52158.5-52158.29" + switch \initial + attribute \src "libresoc.v:52158.9-52158.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\ALU_ldst_len[3:0] \ALU_dec19_ALU_dec19_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\ALU_ldst_len[3:0] \ALU_dec31_ALU_dec31_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\ALU_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\ALU_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\ALU_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\ALU_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\ALU_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\ALU_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\ALU_ldst_len[3:0] 4'0000 + case + assign $1\ALU_ldst_len[3:0] 4'0000 + end + sync always + update \ALU_ldst_len $0\ALU_ldst_len[3:0] + end + connect \$1 $ternary$libresoc.v:51680$3447_Y + connect \VC_XO \opcode_in [9:0] + connect \VC_VRT \opcode_in [25:21] + connect \VC_VRB \opcode_in [15:11] + connect \VC_VRA \opcode_in [20:16] + connect \VC_Rc \opcode_in [10] + connect \XS_XO \opcode_in [10:2] + connect \XS_sh { \opcode_in [1] \opcode_in [15:11] } + connect \XS_RS \opcode_in [25:21] + connect \XS_Rc \opcode_in [0] + connect \XS_RA \opcode_in [20:16] + connect \VA_XO \opcode_in [5:0] + connect \VA_VRT \opcode_in [25:21] + connect \VA_VRC \opcode_in [10:6] + connect \VA_VRB \opcode_in [15:11] + connect \VA_VRA \opcode_in [20:16] + connect \VA_SHB \opcode_in [9:6] + connect \VA_RT \opcode_in [25:21] + connect \VA_RC \opcode_in [10:6] + connect \VA_RB \opcode_in [15:11] + connect \VA_RA \opcode_in [20:16] + connect \TX_XO \opcode_in [6:1] + connect \TX_XBI \opcode_in [10:7] + connect \TX_UI \opcode_in [15:11] + connect \TX_RA \opcode_in [20:16] + connect \DQE_XO \opcode_in [1:0] + connect \DQE_RT \opcode_in [25:21] + connect \DQE_RA \opcode_in [20:16] + connect \XO_XO \opcode_in [9:1] + connect \XO_RT \opcode_in [25:21] + connect \XO_Rc \opcode_in [0] + connect \XO_RB \opcode_in [15:11] + connect \XO_RA \opcode_in [20:16] + connect \XO_OE \opcode_in [10] + connect \all_PO \opcode_in [31:26] + connect \all_OPCD \opcode_in [31:26] + connect \MD_XO \opcode_in [4:2] + connect \MD_sh { \opcode_in [1] \opcode_in [15:11] } + connect \MD_RS \opcode_in [25:21] + connect \MD_Rc \opcode_in [0] + connect \MD_RA \opcode_in [20:16] + connect \MD_me \opcode_in [10:5] + connect \MD_mb \opcode_in [10:5] + connect \M_SH \opcode_in [15:11] + connect \M_RS \opcode_in [25:21] + connect \M_Rc \opcode_in [0] + connect \M_RB \opcode_in [15:11] + connect \M_RA \opcode_in [20:16] + connect \M_ME \opcode_in [5:1] + connect \M_MB \opcode_in [10:6] + connect \SC_XO_1 \opcode_in [1:0] + connect \SC_XO \opcode_in [1] + connect \SC_LEV \opcode_in [11:5] + connect \MDS_XO \opcode_in [4:1] + connect \MDS_XBI_1 \opcode_in [10:7] + connect \MDS_XBI \opcode_in [10:7] + connect \MDS_RS \opcode_in [25:21] + connect \MDS_Rc \opcode_in [0] + connect \MDS_RB \opcode_in [15:11] + connect \MDS_RA \opcode_in [20:16] + connect \MDS_me \opcode_in [10:5] + connect \MDS_mb \opcode_in [10:5] + connect \MDS_IS \opcode_in [25:21] + connect \MDS_IB \opcode_in [15:11] + connect \Z23_XO \opcode_in [8:1] + connect \Z23_TE \opcode_in [20:16] + connect \Z23_RMC \opcode_in [10:9] + connect \Z23_Rc \opcode_in [0] + connect \Z23_R \opcode_in [16] + connect \Z23_FRTp \opcode_in [25:21] + connect \Z23_FRT \opcode_in [25:21] + connect \Z23_FRBp \opcode_in [15:11] + connect \Z23_FRB \opcode_in [15:11] + connect \Z23_FRAp \opcode_in [20:16] + connect \Z23_FRA \opcode_in [20:16] + connect \XFL_XO \opcode_in [10:1] + connect \XFL_W \opcode_in [16] + connect \XFL_Rc \opcode_in [0] + connect \XFL_L \opcode_in [25] + connect \XFL_FRB \opcode_in [15:11] + connect \XFL_FLM \opcode_in [24:17] + connect \VX_XO_1 \opcode_in [10:0] + connect \VX_XO { \opcode_in [10] \opcode_in [8:0] } + connect \VX_VRT \opcode_in [25:21] + connect \VX_VRB \opcode_in [15:11] + connect \VX_VRA \opcode_in [20:16] + connect \VX_UIM_3 \opcode_in [17:16] + connect \VX_UIM_2 \opcode_in [18:16] + connect \VX_UIM_1 \opcode_in [19:16] + connect \VX_UIM \opcode_in [20:16] + connect \VX_SIM \opcode_in [20:16] + connect \VX_RT \opcode_in [25:21] + connect \VX_RA \opcode_in [20:16] + connect \VX_PS \opcode_in [9] + connect \VX_EO \opcode_in [20:16] + connect \DS_XO \opcode_in [1:0] + connect \DS_VRT \opcode_in [25:21] + connect \DS_VRS \opcode_in [25:21] + connect \DS_RT \opcode_in [25:21] + connect \DS_RSp \opcode_in [25:21] + connect \DS_RS \opcode_in [25:21] + connect \DS_RA \opcode_in [20:16] + connect \DS_FRTp \opcode_in [25:21] + connect \DS_FRSp \opcode_in [25:21] + connect \DS_DS \opcode_in [15:2] + connect \DQ_XO \opcode_in [2:0] + connect \DQ_TX_T { \opcode_in [3] \opcode_in [25:21] } + connect \DQ_T \opcode_in [25:21] + connect \DQ_TX \opcode_in [3] + connect \DQ_SX_S { \opcode_in [3] \opcode_in [25:21] } + connect \DQ_S \opcode_in [25:21] + connect \DQ_SX \opcode_in [3] + connect \DQ_RTp \opcode_in [25:21] + connect \DQ_RA \opcode_in [20:16] + connect \DQ_PT \opcode_in [3:0] + connect \DQ_DQ \opcode_in [15:4] + connect \DX_XO \opcode_in [5:1] + connect \DX_RT \opcode_in [25:21] + connect \DX_d0_d1_d2 { \opcode_in [15:6] \opcode_in [20:16] \opcode_in [0] } + connect \DX_d2 \opcode_in [0] + connect \DX_d1 \opcode_in [20:16] + connect \DX_d0 \opcode_in [15:6] + connect \XFX_XO \opcode_in [10:1] + connect \XFX_SPR \opcode_in [20:11] + connect \XFX_RT \opcode_in [25:21] + connect \XFX_RS \opcode_in [25:21] + connect \XFX_FXM \opcode_in [19:12] + connect \XFX_DUIS \opcode_in [20:11] + connect \XFX_DUI \opcode_in [25:21] + connect \XFX_BHRBE \opcode_in [20:11] + connect \EVS_BFA \opcode_in [2:0] + connect \Z22_XO \opcode_in [9:1] + connect \Z22_SH \opcode_in [15:10] + connect \Z22_Rc \opcode_in [0] + connect \Z22_FRTp \opcode_in [25:21] + connect \Z22_FRT \opcode_in [25:21] + connect \Z22_FRAp \opcode_in [20:16] + connect \Z22_FRA \opcode_in [20:16] + connect \Z22_DGM \opcode_in [15:10] + connect \Z22_DCM \opcode_in [15:10] + connect \Z22_BF \opcode_in [25:23] + connect \XX2_XO_1 \opcode_in [10:2] + connect \XX2_XO { \opcode_in [10:7] \opcode_in [5:3] } + connect \XX2_UIM_1 \opcode_in [17:16] + connect \XX2_UIM \opcode_in [19:16] + connect \XX2_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX2_T \opcode_in [25:21] + connect \XX2_TX \opcode_in [0] + connect \XX2_RT \opcode_in [25:21] + connect \XX2_EO \opcode_in [20:16] + connect \XX2_DCMX \opcode_in [22:16] + connect \XX2_dc_dm_dx { \opcode_in [6] \opcode_in [2] \opcode_in [20:16] } + connect \XX2_dx \opcode_in [20:16] + connect \XX2_dm \opcode_in [2] + connect \XX2_dc \opcode_in [6] + connect \XX2_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX2_B \opcode_in [15:11] + connect \XX2_BX \opcode_in [1] + connect \XX2_BF \opcode_in [25:23] + connect \D_UI \opcode_in [15:0] + connect \D_TO \opcode_in [25:21] + connect \D_SI \opcode_in [15:0] + connect \D_RT \opcode_in [25:21] + connect \D_RS \opcode_in [25:21] + connect \D_RA \opcode_in [20:16] + connect \D_L \opcode_in [21] + connect \D_FRT \opcode_in [25:21] + connect \D_FRS \opcode_in [25:21] + connect \D_D \opcode_in [15:0] + connect \D_BF \opcode_in [25:23] + connect \A_XO \opcode_in [5:1] + connect \A_RT \opcode_in [25:21] + connect \A_Rc \opcode_in [0] + connect \A_RB \opcode_in [15:11] + connect \A_RA \opcode_in [20:16] + connect \A_FRT \opcode_in [25:21] + connect \A_FRC \opcode_in [10:6] + connect \A_FRB \opcode_in [15:11] + connect \A_FRA \opcode_in [20:16] + connect \A_BC \opcode_in [10:6] + connect \XL_XO \opcode_in [10:1] + connect \XL_S \opcode_in [11] + connect \XL_OC \opcode_in [25:11] + connect \XL_LK \opcode_in [0] + connect \XL_BT \opcode_in [25:21] + connect \XL_BO_1 \opcode_in [25:21] + connect \XL_BO \opcode_in [25:21] + connect \XL_BI \opcode_in [20:16] + connect \XL_BH \opcode_in [12:11] + connect \XL_BFA \opcode_in [20:18] + connect \XL_BF \opcode_in [25:23] + connect \XL_BB \opcode_in [15:11] + connect \XL_BA \opcode_in [20:16] + connect \XX4_XO \opcode_in [5:4] + connect \XX4_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX4_T \opcode_in [25:21] + connect \XX4_TX \opcode_in [0] + connect \XX4_CX_C { \opcode_in [3] \opcode_in [10:6] } + connect \XX4_C \opcode_in [10:6] + connect \XX4_CX \opcode_in [3] + connect \XX4_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX4_B \opcode_in [15:11] + connect \XX4_BX \opcode_in [1] + connect \XX4_AX_A { \opcode_in [2] \opcode_in [20:16] } + connect \XX4_A \opcode_in [20:16] + connect \XX4_AX \opcode_in [2] + connect \XX3_XO_2 \opcode_in [9:1] + connect \XX3_XO_1 \opcode_in [10:3] + connect \XX3_XO \opcode_in [10:7] + connect \XX3_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX3_T \opcode_in [25:21] + connect \XX3_TX \opcode_in [0] + connect \XX3_SHW \opcode_in [9:8] + connect \XX3_Rc \opcode_in [10] + connect \XX3_DM \opcode_in [9:8] + connect \XX3_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX3_B \opcode_in [15:11] + connect \XX3_BX \opcode_in [1] + connect \XX3_BF \opcode_in [25:23] + connect \XX3_AX_A { \opcode_in [2] \opcode_in [20:16] } + connect \XX3_A \opcode_in [20:16] + connect \XX3_AX \opcode_in [2] + connect \I_LK \opcode_in [0] + connect \I_LI \opcode_in [25:2] + connect \I_AA \opcode_in [1] + connect \B_LK \opcode_in [0] + connect \B_BO \opcode_in [25:21] + connect \B_BI \opcode_in [20:16] + connect \B_BD \opcode_in [15:2] + connect \B_AA \opcode_in [1] + connect \X_XO_1 \opcode_in [8:1] + connect \X_XO \opcode_in [10:1] + connect \X_WC \opcode_in [22:21] + connect \X_W \opcode_in [16] + connect \X_VRT \opcode_in [25:21] + connect \X_VRS \opcode_in [25:21] + connect \X_UIM \opcode_in [20:16] + connect \X_U \opcode_in [15:12] + connect \X_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \X_TX \opcode_in [0] + connect \X_TO \opcode_in [25:21] + connect \X_TH \opcode_in [25:21] + connect \X_TBR \opcode_in [20:11] + connect \X_T \opcode_in [25:21] + connect \X_SX_S { \opcode_in [0] \opcode_in [25:21] } + connect \X_SX \opcode_in [0] + connect \X_SR \opcode_in [19:16] + connect \X_SP \opcode_in [20:19] + connect \X_SI \opcode_in [15:11] + connect \X_SH \opcode_in [15:11] + connect \X_S \opcode_in [25:21] + connect \X_RTp \opcode_in [25:21] + connect \X_RT \opcode_in [25:21] + connect \X_RSp \opcode_in [25:21] + connect \X_RS \opcode_in [25:21] + connect \X_RO \opcode_in [0] + connect \X_RM \opcode_in [12:11] + connect \X_RIC \opcode_in [19:18] + connect \X_Rc \opcode_in [0] + connect \X_RB \opcode_in [15:11] + connect \X_RA \opcode_in [20:16] + connect \X_R_1 \opcode_in [16] + connect \X_R \opcode_in [21] + connect \X_PRS \opcode_in [17] + connect \X_NB \opcode_in [15:11] + connect \X_MO \opcode_in [25:21] + connect \X_L3 \opcode_in [17:16] + connect \X_L1 \opcode_in [16] + connect \X_L \opcode_in [21] + connect \X_L2 \opcode_in [22:21] + connect \X_IMM8 \opcode_in [18:11] + connect \X_IH \opcode_in [23:21] + connect \X_FRTp \opcode_in [25:21] + connect \X_FRT \opcode_in [25:21] + connect \X_FRSp \opcode_in [25:21] + connect \X_FRS \opcode_in [25:21] + connect \X_FRBp \opcode_in [15:11] + connect \X_FRB \opcode_in [15:11] + connect \X_FRAp \opcode_in [20:16] + connect \X_FRA \opcode_in [20:16] + connect \X_FC \opcode_in [15:11] + connect \X_EX \opcode_in [0] + connect \X_EO_1 \opcode_in [20:16] + connect \X_EO \opcode_in [20:19] + connect \X_E_1 \opcode_in [19:16] + connect \X_E \opcode_in [15] + connect \X_DRM \opcode_in [13:11] + connect \X_DCMX \opcode_in [22:16] + connect \X_CT \opcode_in [24:21] + connect \X_BO \opcode_in [25:21] + connect \X_BFA \opcode_in [20:18] + connect \X_BF \opcode_in [25:23] + connect \X_A \opcode_in [25] + connect \ALU_SPR \opcode_in [20:11] + connect \ALU_MB \opcode_in [10:6] + connect \ALU_ME \opcode_in [5:1] + connect \ALU_SH \opcode_in [15:11] + connect \ALU_BC \opcode_in [10:6] + connect \ALU_TO \opcode_in [25:21] + connect \ALU_DS \opcode_in [15:2] + connect \ALU_D \opcode_in [15:0] + connect \ALU_BH \opcode_in [12:11] + connect \ALU_BI \opcode_in [20:16] + connect \ALU_BO \opcode_in [25:21] + connect \ALU_FXM \opcode_in [19:12] + connect \ALU_BT \opcode_in [25:21] + connect \ALU_BA \opcode_in [20:16] + connect \ALU_BB \opcode_in [15:11] + connect \ALU_CR \opcode_in [10:1] + connect \ALU_BF \opcode_in [25:23] + connect \ALU_BD \opcode_in [15:2] + connect \ALU_OE \opcode_in [10] + connect \ALU_Rc \opcode_in [0] + connect \ALU_AA \opcode_in [1] + connect \ALU_LK \opcode_in [0] + connect \ALU_LI \opcode_in [25:2] + connect \ALU_ME32 \opcode_in [5:1] + connect \ALU_MB32 \opcode_in [10:6] + connect \ALU_sh { \opcode_in [1] \opcode_in [15:11] } + connect \ALU_SH32 \opcode_in [15:11] + connect \ALU_L \opcode_in [21] + connect \ALU_UI \opcode_in [15:0] + connect \ALU_SI \opcode_in [15:0] + connect \ALU_RB \opcode_in [15:11] + connect \ALU_RA \opcode_in [20:16] + connect \ALU_RT \opcode_in [25:21] + connect \ALU_RS \opcode_in [25:21] + connect \opcode_in \$1 + connect \ALU_dec31_opcode_in \opcode_in + connect \ALU_dec19_opcode_in \opcode_in + connect \opcode_switch \opcode_in [31:26] +end +attribute \src "libresoc.v:52525.1-53955.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_CR.dec" +attribute \generator "nMigen" +module \dec$137 + attribute \src "libresoc.v:53586.3-53598.6" + wire width 3 $0\CR_cr_in[2:0] + attribute \src "libresoc.v:53599.3-53611.6" + wire width 3 $0\CR_cr_out[2:0] + attribute \src "libresoc.v:53560.3-53572.6" + wire width 12 $0\CR_function_unit[11:0] + attribute \src "libresoc.v:53573.3-53585.6" + wire width 7 $0\CR_internal_op[6:0] + attribute \src "libresoc.v:53612.3-53624.6" + wire width 2 $0\CR_rc_sel[1:0] + attribute \src "libresoc.v:52526.7-52526.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:53586.3-53598.6" + wire width 3 $1\CR_cr_in[2:0] + attribute \src "libresoc.v:53599.3-53611.6" + wire width 3 $1\CR_cr_out[2:0] + attribute \src "libresoc.v:53560.3-53572.6" + wire width 12 $1\CR_function_unit[11:0] + attribute \src "libresoc.v:53573.3-53585.6" + wire width 7 $1\CR_internal_op[6:0] + attribute \src "libresoc.v:53612.3-53624.6" + wire width 2 $1\CR_rc_sel[1:0] + attribute \src "libresoc.v:53543.17-53543.211" + wire width 32 $ternary$libresoc.v:53543$3463_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:478" + wire width 32 \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_FRC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \A_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \B_AA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 14 \B_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \B_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \B_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \B_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire \CR_AA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 output 11 \CR_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 output 10 \CR_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 output 15 \CR_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 14 \CR_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 3 \CR_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 2 \CR_BH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 output 14 \CR_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \CR_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 output 12 \CR_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 10 \CR_CR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 16 \CR_D + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 14 \CR_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 8 output 13 \CR_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire \CR_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 24 \CR_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire \CR_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \CR_MB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \CR_MB32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \CR_ME + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \CR_ME32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire output 9 \CR_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \CR_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \CR_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \CR_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \CR_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire output 8 \CR_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \CR_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \CR_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 16 \CR_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 10 \CR_SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \CR_TO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 16 \CR_UI + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 4 \CR_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \CR_cr_out + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \CR_dec19_CR_dec19_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \CR_dec19_CR_dec19_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \CR_dec19_CR_dec19_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 \CR_dec19_CR_dec19_internal_op + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \CR_dec19_CR_dec19_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \CR_dec19_opcode_in + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \CR_dec31_CR_dec31_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \CR_dec31_CR_dec31_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \CR_dec31_CR_dec31_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 \CR_dec31_CR_dec31_internal_op + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \CR_dec31_CR_dec31_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \CR_dec31_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 7 \CR_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 6 \CR_internal_op + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 3 \CR_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 6 \CR_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DQE_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DQE_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \DQE_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 12 \DQ_DQ + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \DQ_PT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DQ_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DQ_RTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DQ_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \DQ_SX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \DQ_SX_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DQ_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \DQ_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \DQ_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \DQ_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 14 \DS_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_FRSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_RSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_VRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \DS_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DX_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \DX_d0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 16 \DX_d0_d1_d2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DX_d1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \DX_d2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \D_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 16 \D_D + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \D_FRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \D_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \D_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \D_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \D_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \D_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 16 \D_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \D_TO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 16 \D_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \EVS_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \I_AA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 24 \I_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \I_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MDS_IB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MDS_IS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MDS_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MDS_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MDS_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \MDS_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \MDS_XBI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \MDS_XBI_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \MDS_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \MDS_mb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \MDS_me + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MD_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MD_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \MD_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \MD_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \MD_mb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \MD_me + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \MD_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \M_MB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \M_ME + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \M_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \M_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \M_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \M_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \M_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 7 \SC_LEV + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \SC_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \SC_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \TX_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \TX_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \TX_XBI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \TX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_RC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \VA_SHB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_VRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_VRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_VRC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \VA_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \VC_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VC_VRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VC_VRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VC_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \VC_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_EO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \VX_PS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_SIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_UIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \VX_UIM_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \VX_UIM_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \VX_UIM_3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_VRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_VRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \VX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 11 \VX_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 8 \XFL_FLM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XFL_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XFL_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XFL_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XFL_W + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \XFL_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \XFX_BHRBE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XFX_DUI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \XFX_DUIS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 8 \XFX_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XFX_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XFX_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \XFX_SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \XFX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XL_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XL_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \XL_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \XL_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \XL_BH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XL_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XL_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XL_BO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 output 18 \XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XL_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 15 \XL_OC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XL_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \XL_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XO_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XO_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XO_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XO_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XO_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 9 \XO_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XS_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XS_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XS_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 9 \XS_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XS_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX2_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \XX2_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX2_BX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX2_BX_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 7 \XX2_DCMX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX2_EO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX2_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX2_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX2_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX2_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \XX2_UIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \XX2_UIM_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 7 \XX2_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 9 \XX2_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX2_dc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 7 \XX2_dc_dm_dx + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX2_dm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX2_dx + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX3_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX3_AX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX3_AX_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX3_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \XX3_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX3_BX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX3_BX_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \XX3_DM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX3_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \XX3_SHW + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX3_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX3_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX3_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \XX3_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 8 \XX3_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 9 \XX3_XO_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX4_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX4_AX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX4_AX_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX4_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX4_BX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX4_BX_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX4_C + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX4_CX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX4_CX_C + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX4_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX4_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX4_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \XX4_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 output 16 \X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 output 17 \X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \X_CT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 7 \X_DCMX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \X_DRM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_E + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \X_EO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_EO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_EX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \X_E_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRAp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRBp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \X_IH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 8 \X_IMM8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_L1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \X_L2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \X_L3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_MO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_NB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_PRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_R + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \X_RIC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \X_RM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_RO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_RSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_RTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_R_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \X_SP + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \X_SR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_SX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \X_SX_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \X_TBR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_TH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_TO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \X_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \X_U + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_UIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_VRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_W + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \X_WC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \X_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 8 \X_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \Z22_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \Z22_DCM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \Z22_DGM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z22_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z22_FRAp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z22_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z22_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \Z22_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \Z22_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 9 \Z22_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_FRAp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_FRBp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \Z23_R + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \Z23_RMC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \Z23_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_TE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 8 \Z23_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \all_OPCD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \all_PO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + wire input 1 \bigendian + attribute \src "libresoc.v:52526.7-52526.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 output 2 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 6 \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:442" + wire width 32 input 19 \raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:478" + cell $mux $ternary$libresoc.v:53543$3463 + parameter \WIDTH 32 + connect \A \raw_opcode_in + connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } + connect \S \bigendian + connect \Y $ternary$libresoc.v:53543$3463_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:53544.12-53551.4" + cell \CR_dec19 \CR_dec19 + connect \CR_dec19_cr_in \CR_dec19_CR_dec19_cr_in + connect \CR_dec19_cr_out \CR_dec19_CR_dec19_cr_out + connect \CR_dec19_function_unit \CR_dec19_CR_dec19_function_unit + connect \CR_dec19_internal_op \CR_dec19_CR_dec19_internal_op + connect \CR_dec19_rc_sel \CR_dec19_CR_dec19_rc_sel + connect \opcode_in \CR_dec19_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:53552.12-53559.4" + cell \CR_dec31 \CR_dec31 + connect \CR_dec31_cr_in \CR_dec31_CR_dec31_cr_in + connect \CR_dec31_cr_out \CR_dec31_CR_dec31_cr_out + connect \CR_dec31_function_unit \CR_dec31_CR_dec31_function_unit + connect \CR_dec31_internal_op \CR_dec31_CR_dec31_internal_op + connect \CR_dec31_rc_sel \CR_dec31_CR_dec31_rc_sel + connect \opcode_in \CR_dec31_opcode_in + end + attribute \src "libresoc.v:52526.7-52526.20" + process $proc$libresoc.v:52526$3469 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:53560.3-53572.6" + process $proc$libresoc.v:53560$3464 + assign { } { } + assign { } { } + assign $0\CR_function_unit[11:0] $1\CR_function_unit[11:0] + attribute \src "libresoc.v:53561.5-53561.29" + switch \initial + attribute \src "libresoc.v:53561.9-53561.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\CR_function_unit[11:0] \CR_dec19_CR_dec19_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\CR_function_unit[11:0] \CR_dec31_CR_dec31_function_unit + case + assign $1\CR_function_unit[11:0] 12'000000000000 + end + sync always + update \CR_function_unit $0\CR_function_unit[11:0] + end + attribute \src "libresoc.v:53573.3-53585.6" + process $proc$libresoc.v:53573$3465 + assign { } { } + assign { } { } + assign $0\CR_internal_op[6:0] $1\CR_internal_op[6:0] + attribute \src "libresoc.v:53574.5-53574.29" + switch \initial + attribute \src "libresoc.v:53574.9-53574.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\CR_internal_op[6:0] \CR_dec19_CR_dec19_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\CR_internal_op[6:0] \CR_dec31_CR_dec31_internal_op + case + assign $1\CR_internal_op[6:0] 7'0000000 + end + sync always + update \CR_internal_op $0\CR_internal_op[6:0] + end + attribute \src "libresoc.v:53586.3-53598.6" + process $proc$libresoc.v:53586$3466 + assign { } { } + assign { } { } + assign $0\CR_cr_in[2:0] $1\CR_cr_in[2:0] + attribute \src "libresoc.v:53587.5-53587.29" + switch \initial + attribute \src "libresoc.v:53587.9-53587.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\CR_cr_in[2:0] \CR_dec19_CR_dec19_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\CR_cr_in[2:0] \CR_dec31_CR_dec31_cr_in + case + assign $1\CR_cr_in[2:0] 3'000 + end + sync always + update \CR_cr_in $0\CR_cr_in[2:0] + end + attribute \src "libresoc.v:53599.3-53611.6" + process $proc$libresoc.v:53599$3467 + assign { } { } + assign { } { } + assign $0\CR_cr_out[2:0] $1\CR_cr_out[2:0] + attribute \src "libresoc.v:53600.5-53600.29" + switch \initial + attribute \src "libresoc.v:53600.9-53600.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\CR_cr_out[2:0] \CR_dec19_CR_dec19_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\CR_cr_out[2:0] \CR_dec31_CR_dec31_cr_out + case + assign $1\CR_cr_out[2:0] 3'000 + end + sync always + update \CR_cr_out $0\CR_cr_out[2:0] + end + attribute \src "libresoc.v:53612.3-53624.6" + process $proc$libresoc.v:53612$3468 + assign { } { } + assign { } { } + assign $0\CR_rc_sel[1:0] $1\CR_rc_sel[1:0] + attribute \src "libresoc.v:53613.5-53613.29" + switch \initial + attribute \src "libresoc.v:53613.9-53613.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\CR_rc_sel[1:0] \CR_dec19_CR_dec19_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\CR_rc_sel[1:0] \CR_dec31_CR_dec31_rc_sel + case + assign $1\CR_rc_sel[1:0] 2'00 + end + sync always + update \CR_rc_sel $0\CR_rc_sel[1:0] + end + connect \$1 $ternary$libresoc.v:53543$3463_Y + connect \VC_XO \opcode_in [9:0] + connect \VC_VRT \opcode_in [25:21] + connect \VC_VRB \opcode_in [15:11] + connect \VC_VRA \opcode_in [20:16] + connect \VC_Rc \opcode_in [10] + connect \XS_XO \opcode_in [10:2] + connect \XS_sh { \opcode_in [1] \opcode_in [15:11] } + connect \XS_RS \opcode_in [25:21] + connect \XS_Rc \opcode_in [0] + connect \XS_RA \opcode_in [20:16] + connect \VA_XO \opcode_in [5:0] + connect \VA_VRT \opcode_in [25:21] + connect \VA_VRC \opcode_in [10:6] + connect \VA_VRB \opcode_in [15:11] + connect \VA_VRA \opcode_in [20:16] + connect \VA_SHB \opcode_in [9:6] + connect \VA_RT \opcode_in [25:21] + connect \VA_RC \opcode_in [10:6] + connect \VA_RB \opcode_in [15:11] + connect \VA_RA \opcode_in [20:16] + connect \TX_XO \opcode_in [6:1] + connect \TX_XBI \opcode_in [10:7] + connect \TX_UI \opcode_in [15:11] + connect \TX_RA \opcode_in [20:16] + connect \DQE_XO \opcode_in [1:0] + connect \DQE_RT \opcode_in [25:21] + connect \DQE_RA \opcode_in [20:16] + connect \XO_XO \opcode_in [9:1] + connect \XO_RT \opcode_in [25:21] + connect \XO_Rc \opcode_in [0] + connect \XO_RB \opcode_in [15:11] + connect \XO_RA \opcode_in [20:16] + connect \XO_OE \opcode_in [10] + connect \all_PO \opcode_in [31:26] + connect \all_OPCD \opcode_in [31:26] + connect \MD_XO \opcode_in [4:2] + connect \MD_sh { \opcode_in [1] \opcode_in [15:11] } + connect \MD_RS \opcode_in [25:21] + connect \MD_Rc \opcode_in [0] + connect \MD_RA \opcode_in [20:16] + connect \MD_me \opcode_in [10:5] + connect \MD_mb \opcode_in [10:5] + connect \M_SH \opcode_in [15:11] + connect \M_RS \opcode_in [25:21] + connect \M_Rc \opcode_in [0] + connect \M_RB \opcode_in [15:11] + connect \M_RA \opcode_in [20:16] + connect \M_ME \opcode_in [5:1] + connect \M_MB \opcode_in [10:6] + connect \SC_XO_1 \opcode_in [1:0] + connect \SC_XO \opcode_in [1] + connect \SC_LEV \opcode_in [11:5] + connect \MDS_XO \opcode_in [4:1] + connect \MDS_XBI_1 \opcode_in [10:7] + connect \MDS_XBI \opcode_in [10:7] + connect \MDS_RS \opcode_in [25:21] + connect \MDS_Rc \opcode_in [0] + connect \MDS_RB \opcode_in [15:11] + connect \MDS_RA \opcode_in [20:16] + connect \MDS_me \opcode_in [10:5] + connect \MDS_mb \opcode_in [10:5] + connect \MDS_IS \opcode_in [25:21] + connect \MDS_IB \opcode_in [15:11] + connect \Z23_XO \opcode_in [8:1] + connect \Z23_TE \opcode_in [20:16] + connect \Z23_RMC \opcode_in [10:9] + connect \Z23_Rc \opcode_in [0] + connect \Z23_R \opcode_in [16] + connect \Z23_FRTp \opcode_in [25:21] + connect \Z23_FRT \opcode_in [25:21] + connect \Z23_FRBp \opcode_in [15:11] + connect \Z23_FRB \opcode_in [15:11] + connect \Z23_FRAp \opcode_in [20:16] + connect \Z23_FRA \opcode_in [20:16] + connect \XFL_XO \opcode_in [10:1] + connect \XFL_W \opcode_in [16] + connect \XFL_Rc \opcode_in [0] + connect \XFL_L \opcode_in [25] + connect \XFL_FRB \opcode_in [15:11] + connect \XFL_FLM \opcode_in [24:17] + connect \VX_XO_1 \opcode_in [10:0] + connect \VX_XO { \opcode_in [10] \opcode_in [8:0] } + connect \VX_VRT \opcode_in [25:21] + connect \VX_VRB \opcode_in [15:11] + connect \VX_VRA \opcode_in [20:16] + connect \VX_UIM_3 \opcode_in [17:16] + connect \VX_UIM_2 \opcode_in [18:16] + connect \VX_UIM_1 \opcode_in [19:16] + connect \VX_UIM \opcode_in [20:16] + connect \VX_SIM \opcode_in [20:16] + connect \VX_RT \opcode_in [25:21] + connect \VX_RA \opcode_in [20:16] + connect \VX_PS \opcode_in [9] + connect \VX_EO \opcode_in [20:16] + connect \DS_XO \opcode_in [1:0] + connect \DS_VRT \opcode_in [25:21] + connect \DS_VRS \opcode_in [25:21] + connect \DS_RT \opcode_in [25:21] + connect \DS_RSp \opcode_in [25:21] + connect \DS_RS \opcode_in [25:21] + connect \DS_RA \opcode_in [20:16] + connect \DS_FRTp \opcode_in [25:21] + connect \DS_FRSp \opcode_in [25:21] + connect \DS_DS \opcode_in [15:2] + connect \DQ_XO \opcode_in [2:0] + connect \DQ_TX_T { \opcode_in [3] \opcode_in [25:21] } + connect \DQ_T \opcode_in [25:21] + connect \DQ_TX \opcode_in [3] + connect \DQ_SX_S { \opcode_in [3] \opcode_in [25:21] } + connect \DQ_S \opcode_in [25:21] + connect \DQ_SX \opcode_in [3] + connect \DQ_RTp \opcode_in [25:21] + connect \DQ_RA \opcode_in [20:16] + connect \DQ_PT \opcode_in [3:0] + connect \DQ_DQ \opcode_in [15:4] + connect \DX_XO \opcode_in [5:1] + connect \DX_RT \opcode_in [25:21] + connect \DX_d0_d1_d2 { \opcode_in [15:6] \opcode_in [20:16] \opcode_in [0] } + connect \DX_d2 \opcode_in [0] + connect \DX_d1 \opcode_in [20:16] + connect \DX_d0 \opcode_in [15:6] + connect \XFX_XO \opcode_in [10:1] + connect \XFX_SPR \opcode_in [20:11] + connect \XFX_RT \opcode_in [25:21] + connect \XFX_RS \opcode_in [25:21] + connect \XFX_FXM \opcode_in [19:12] + connect \XFX_DUIS \opcode_in [20:11] + connect \XFX_DUI \opcode_in [25:21] + connect \XFX_BHRBE \opcode_in [20:11] + connect \EVS_BFA \opcode_in [2:0] + connect \Z22_XO \opcode_in [9:1] + connect \Z22_SH \opcode_in [15:10] + connect \Z22_Rc \opcode_in [0] + connect \Z22_FRTp \opcode_in [25:21] + connect \Z22_FRT \opcode_in [25:21] + connect \Z22_FRAp \opcode_in [20:16] + connect \Z22_FRA \opcode_in [20:16] + connect \Z22_DGM \opcode_in [15:10] + connect \Z22_DCM \opcode_in [15:10] + connect \Z22_BF \opcode_in [25:23] + connect \XX2_XO_1 \opcode_in [10:2] + connect \XX2_XO { \opcode_in [10:7] \opcode_in [5:3] } + connect \XX2_UIM_1 \opcode_in [17:16] + connect \XX2_UIM \opcode_in [19:16] + connect \XX2_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX2_T \opcode_in [25:21] + connect \XX2_TX \opcode_in [0] + connect \XX2_RT \opcode_in [25:21] + connect \XX2_EO \opcode_in [20:16] + connect \XX2_DCMX \opcode_in [22:16] + connect \XX2_dc_dm_dx { \opcode_in [6] \opcode_in [2] \opcode_in [20:16] } + connect \XX2_dx \opcode_in [20:16] + connect \XX2_dm \opcode_in [2] + connect \XX2_dc \opcode_in [6] + connect \XX2_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX2_B \opcode_in [15:11] + connect \XX2_BX \opcode_in [1] + connect \XX2_BF \opcode_in [25:23] + connect \D_UI \opcode_in [15:0] + connect \D_TO \opcode_in [25:21] + connect \D_SI \opcode_in [15:0] + connect \D_RT \opcode_in [25:21] + connect \D_RS \opcode_in [25:21] + connect \D_RA \opcode_in [20:16] + connect \D_L \opcode_in [21] + connect \D_FRT \opcode_in [25:21] + connect \D_FRS \opcode_in [25:21] + connect \D_D \opcode_in [15:0] + connect \D_BF \opcode_in [25:23] + connect \A_XO \opcode_in [5:1] + connect \A_RT \opcode_in [25:21] + connect \A_Rc \opcode_in [0] + connect \A_RB \opcode_in [15:11] + connect \A_RA \opcode_in [20:16] + connect \A_FRT \opcode_in [25:21] + connect \A_FRC \opcode_in [10:6] + connect \A_FRB \opcode_in [15:11] + connect \A_FRA \opcode_in [20:16] + connect \A_BC \opcode_in [10:6] + connect \XL_XO \opcode_in [10:1] + connect \XL_S \opcode_in [11] + connect \XL_OC \opcode_in [25:11] + connect \XL_LK \opcode_in [0] + connect \XL_BT \opcode_in [25:21] + connect \XL_BO_1 \opcode_in [25:21] + connect \XL_BO \opcode_in [25:21] + connect \XL_BI \opcode_in [20:16] + connect \XL_BH \opcode_in [12:11] + connect \XL_BFA \opcode_in [20:18] + connect \XL_BF \opcode_in [25:23] + connect \XL_BB \opcode_in [15:11] + connect \XL_BA \opcode_in [20:16] + connect \XX4_XO \opcode_in [5:4] + connect \XX4_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX4_T \opcode_in [25:21] + connect \XX4_TX \opcode_in [0] + connect \XX4_CX_C { \opcode_in [3] \opcode_in [10:6] } + connect \XX4_C \opcode_in [10:6] + connect \XX4_CX \opcode_in [3] + connect \XX4_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX4_B \opcode_in [15:11] + connect \XX4_BX \opcode_in [1] + connect \XX4_AX_A { \opcode_in [2] \opcode_in [20:16] } + connect \XX4_A \opcode_in [20:16] + connect \XX4_AX \opcode_in [2] + connect \XX3_XO_2 \opcode_in [9:1] + connect \XX3_XO_1 \opcode_in [10:3] + connect \XX3_XO \opcode_in [10:7] + connect \XX3_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX3_T \opcode_in [25:21] + connect \XX3_TX \opcode_in [0] + connect \XX3_SHW \opcode_in [9:8] + connect \XX3_Rc \opcode_in [10] + connect \XX3_DM \opcode_in [9:8] + connect \XX3_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX3_B \opcode_in [15:11] + connect \XX3_BX \opcode_in [1] + connect \XX3_BF \opcode_in [25:23] + connect \XX3_AX_A { \opcode_in [2] \opcode_in [20:16] } + connect \XX3_A \opcode_in [20:16] + connect \XX3_AX \opcode_in [2] + connect \I_LK \opcode_in [0] + connect \I_LI \opcode_in [25:2] + connect \I_AA \opcode_in [1] + connect \B_LK \opcode_in [0] + connect \B_BO \opcode_in [25:21] + connect \B_BI \opcode_in [20:16] + connect \B_BD \opcode_in [15:2] + connect \B_AA \opcode_in [1] + connect \X_XO_1 \opcode_in [8:1] + connect \X_XO \opcode_in [10:1] + connect \X_WC \opcode_in [22:21] + connect \X_W \opcode_in [16] + connect \X_VRT \opcode_in [25:21] + connect \X_VRS \opcode_in [25:21] + connect \X_UIM \opcode_in [20:16] + connect \X_U \opcode_in [15:12] + connect \X_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \X_TX \opcode_in [0] + connect \X_TO \opcode_in [25:21] + connect \X_TH \opcode_in [25:21] + connect \X_TBR \opcode_in [20:11] + connect \X_T \opcode_in [25:21] + connect \X_SX_S { \opcode_in [0] \opcode_in [25:21] } + connect \X_SX \opcode_in [0] + connect \X_SR \opcode_in [19:16] + connect \X_SP \opcode_in [20:19] + connect \X_SI \opcode_in [15:11] + connect \X_SH \opcode_in [15:11] + connect \X_S \opcode_in [25:21] + connect \X_RTp \opcode_in [25:21] + connect \X_RT \opcode_in [25:21] + connect \X_RSp \opcode_in [25:21] + connect \X_RS \opcode_in [25:21] + connect \X_RO \opcode_in [0] + connect \X_RM \opcode_in [12:11] + connect \X_RIC \opcode_in [19:18] + connect \X_Rc \opcode_in [0] + connect \X_RB \opcode_in [15:11] + connect \X_RA \opcode_in [20:16] + connect \X_R_1 \opcode_in [16] + connect \X_R \opcode_in [21] + connect \X_PRS \opcode_in [17] + connect \X_NB \opcode_in [15:11] + connect \X_MO \opcode_in [25:21] + connect \X_L3 \opcode_in [17:16] + connect \X_L1 \opcode_in [16] + connect \X_L \opcode_in [21] + connect \X_L2 \opcode_in [22:21] + connect \X_IMM8 \opcode_in [18:11] + connect \X_IH \opcode_in [23:21] + connect \X_FRTp \opcode_in [25:21] + connect \X_FRT \opcode_in [25:21] + connect \X_FRSp \opcode_in [25:21] + connect \X_FRS \opcode_in [25:21] + connect \X_FRBp \opcode_in [15:11] + connect \X_FRB \opcode_in [15:11] + connect \X_FRAp \opcode_in [20:16] + connect \X_FRA \opcode_in [20:16] + connect \X_FC \opcode_in [15:11] + connect \X_EX \opcode_in [0] + connect \X_EO_1 \opcode_in [20:16] + connect \X_EO \opcode_in [20:19] + connect \X_E_1 \opcode_in [19:16] + connect \X_E \opcode_in [15] + connect \X_DRM \opcode_in [13:11] + connect \X_DCMX \opcode_in [22:16] + connect \X_CT \opcode_in [24:21] + connect \X_BO \opcode_in [25:21] + connect \X_BFA \opcode_in [20:18] + connect \X_BF \opcode_in [25:23] + connect \X_A \opcode_in [25] + connect \CR_SPR \opcode_in [20:11] + connect \CR_MB \opcode_in [10:6] + connect \CR_ME \opcode_in [5:1] + connect \CR_SH \opcode_in [15:11] + connect \CR_BC \opcode_in [10:6] + connect \CR_TO \opcode_in [25:21] + connect \CR_DS \opcode_in [15:2] + connect \CR_D \opcode_in [15:0] + connect \CR_BH \opcode_in [12:11] + connect \CR_BI \opcode_in [20:16] + connect \CR_BO \opcode_in [25:21] + connect \CR_FXM \opcode_in [19:12] + connect \CR_BT \opcode_in [25:21] + connect \CR_BA \opcode_in [20:16] + connect \CR_BB \opcode_in [15:11] + connect \CR_CR \opcode_in [10:1] + connect \CR_BF \opcode_in [25:23] + connect \CR_BD \opcode_in [15:2] + connect \CR_OE \opcode_in [10] + connect \CR_Rc \opcode_in [0] + connect \CR_AA \opcode_in [1] + connect \CR_LK \opcode_in [0] + connect \CR_LI \opcode_in [25:2] + connect \CR_ME32 \opcode_in [5:1] + connect \CR_MB32 \opcode_in [10:6] + connect \CR_sh { \opcode_in [1] \opcode_in [15:11] } + connect \CR_SH32 \opcode_in [15:11] + connect \CR_L \opcode_in [21] + connect \CR_UI \opcode_in [15:0] + connect \CR_SI \opcode_in [15:0] + connect \CR_RB \opcode_in [15:11] + connect \CR_RA \opcode_in [20:16] + connect \CR_RT \opcode_in [25:21] + connect \CR_RS \opcode_in [25:21] + connect \opcode_in \$1 + connect \CR_dec31_opcode_in \opcode_in + connect \CR_dec19_opcode_in \opcode_in + connect \opcode_switch \opcode_in [31:26] +end +attribute \src "libresoc.v:53959.1-55374.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_BRANCH.dec" +attribute \generator "nMigen" +module \dec$144 + attribute \src "libresoc.v:54965.3-54980.6" + wire width 3 $0\BRANCH_cr_in[2:0] + attribute \src "libresoc.v:54981.3-54996.6" + wire width 3 $0\BRANCH_cr_out[2:0] + attribute \src "libresoc.v:54917.3-54932.6" + wire width 12 $0\BRANCH_function_unit[11:0] + attribute \src "libresoc.v:54949.3-54964.6" + wire width 4 $0\BRANCH_in2_sel[3:0] + attribute \src "libresoc.v:54933.3-54948.6" + wire width 7 $0\BRANCH_internal_op[6:0] + attribute \src "libresoc.v:55013.3-55028.6" + wire $0\BRANCH_is_32b[0:0] + attribute \src "libresoc.v:55029.3-55044.6" + wire $0\BRANCH_lk[0:0] + attribute \src "libresoc.v:54997.3-55012.6" + wire width 2 $0\BRANCH_rc_sel[1:0] + attribute \src "libresoc.v:53960.7-53960.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:54965.3-54980.6" + wire width 3 $1\BRANCH_cr_in[2:0] + attribute \src "libresoc.v:54981.3-54996.6" + wire width 3 $1\BRANCH_cr_out[2:0] + attribute \src "libresoc.v:54917.3-54932.6" + wire width 12 $1\BRANCH_function_unit[11:0] + attribute \src "libresoc.v:54949.3-54964.6" + wire width 4 $1\BRANCH_in2_sel[3:0] + attribute \src "libresoc.v:54933.3-54948.6" + wire width 7 $1\BRANCH_internal_op[6:0] + attribute \src "libresoc.v:55013.3-55028.6" + wire $1\BRANCH_is_32b[0:0] + attribute \src "libresoc.v:55029.3-55044.6" + wire $1\BRANCH_lk[0:0] + attribute \src "libresoc.v:54997.3-55012.6" + wire width 2 $1\BRANCH_rc_sel[1:0] + attribute \src "libresoc.v:54905.17-54905.211" + wire width 32 $ternary$libresoc.v:54905$3470_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:478" + wire width 32 \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_FRC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \A_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire \BRANCH_AA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 output 21 \BRANCH_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 output 20 \BRANCH_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 output 26 \BRANCH_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 14 output 19 \BRANCH_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 3 \BRANCH_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 2 \BRANCH_BH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 output 24 \BRANCH_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \BRANCH_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 output 22 \BRANCH_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 10 \BRANCH_CR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 16 \BRANCH_D + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 14 output 25 \BRANCH_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 8 output 23 \BRANCH_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire \BRANCH_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 24 output 16 \BRANCH_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire output 11 \BRANCH_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \BRANCH_MB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \BRANCH_MB32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \BRANCH_ME + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \BRANCH_ME32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire output 18 \BRANCH_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \BRANCH_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \BRANCH_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \BRANCH_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \BRANCH_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire output 17 \BRANCH_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \BRANCH_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 output 14 \BRANCH_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 16 output 12 \BRANCH_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 10 \BRANCH_SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \BRANCH_TO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 16 output 13 \BRANCH_UI + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 4 \BRANCH_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \BRANCH_cr_out + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \BRANCH_dec19_BRANCH_dec19_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \BRANCH_dec19_BRANCH_dec19_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \BRANCH_dec19_BRANCH_dec19_function_unit + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \BRANCH_dec19_BRANCH_dec19_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 \BRANCH_dec19_BRANCH_dec19_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \BRANCH_dec19_BRANCH_dec19_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \BRANCH_dec19_BRANCH_dec19_lk + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \BRANCH_dec19_BRANCH_dec19_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \BRANCH_dec19_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 7 \BRANCH_function_unit + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 8 \BRANCH_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 6 \BRANCH_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 9 \BRANCH_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 10 \BRANCH_lk + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 3 \BRANCH_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 6 output 15 \BRANCH_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \B_AA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 14 \B_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \B_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \B_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \B_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DQE_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DQE_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \DQE_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 12 \DQ_DQ + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \DQ_PT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DQ_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DQ_RTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DQ_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \DQ_SX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \DQ_SX_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DQ_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \DQ_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \DQ_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \DQ_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 14 \DS_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_FRSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_RSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_VRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \DS_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DX_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \DX_d0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 16 \DX_d0_d1_d2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DX_d1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \DX_d2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \D_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 16 \D_D + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \D_FRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \D_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \D_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \D_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \D_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \D_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 16 \D_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \D_TO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 16 \D_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \EVS_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \I_AA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 24 \I_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \I_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MDS_IB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MDS_IS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MDS_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MDS_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MDS_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \MDS_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \MDS_XBI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \MDS_XBI_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \MDS_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \MDS_mb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \MDS_me + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MD_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MD_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \MD_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \MD_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \MD_mb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \MD_me + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \MD_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \M_MB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \M_ME + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \M_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \M_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \M_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \M_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \M_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 7 \SC_LEV + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \SC_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \SC_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \TX_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \TX_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \TX_XBI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \TX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_RC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \VA_SHB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_VRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_VRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_VRC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \VA_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \VC_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VC_VRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VC_VRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VC_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \VC_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_EO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \VX_PS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_SIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_UIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \VX_UIM_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \VX_UIM_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \VX_UIM_3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_VRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_VRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \VX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 11 \VX_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 8 \XFL_FLM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XFL_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XFL_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XFL_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XFL_W + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \XFL_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \XFX_BHRBE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XFX_DUI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \XFX_DUIS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 8 \XFX_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XFX_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XFX_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \XFX_SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \XFX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XL_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XL_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \XL_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \XL_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \XL_BH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XL_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XL_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XL_BO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 output 29 \XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XL_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 15 \XL_OC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XL_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \XL_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XO_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XO_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XO_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XO_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XO_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 9 \XO_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XS_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XS_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XS_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 9 \XS_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XS_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX2_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \XX2_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX2_BX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX2_BX_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 7 \XX2_DCMX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX2_EO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX2_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX2_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX2_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX2_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \XX2_UIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \XX2_UIM_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 7 \XX2_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 9 \XX2_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX2_dc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 7 \XX2_dc_dm_dx + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX2_dm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX2_dx + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX3_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX3_AX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX3_AX_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX3_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \XX3_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX3_BX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX3_BX_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \XX3_DM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX3_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \XX3_SHW + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX3_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX3_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX3_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \XX3_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 8 \XX3_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 9 \XX3_XO_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX4_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX4_AX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX4_AX_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX4_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX4_BX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX4_BX_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX4_C + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX4_CX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX4_CX_C + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX4_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX4_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX4_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \XX4_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 output 27 \X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 output 28 \X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \X_CT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 7 \X_DCMX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \X_DRM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_E + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \X_EO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_EO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_EX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \X_E_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRAp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRBp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \X_IH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 8 \X_IMM8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_L1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \X_L2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \X_L3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_MO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_NB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_PRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_R + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \X_RIC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \X_RM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_RO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_RSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_RTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_R_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \X_SP + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \X_SR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_SX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \X_SX_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \X_TBR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_TH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_TO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \X_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \X_U + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_UIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_VRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_W + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \X_WC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \X_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 8 \X_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \Z22_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \Z22_DCM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \Z22_DGM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z22_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z22_FRAp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z22_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z22_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \Z22_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \Z22_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 9 \Z22_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_FRAp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_FRBp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \Z23_R + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \Z23_RMC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \Z23_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_TE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 8 \Z23_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \all_OPCD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \all_PO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + wire input 1 \bigendian + attribute \src "libresoc.v:53960.7-53960.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 output 2 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 6 \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:442" + wire width 32 input 30 \raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:478" + cell $mux $ternary$libresoc.v:54905$3470 + parameter \WIDTH 32 + connect \A \raw_opcode_in + connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } + connect \S \bigendian + connect \Y $ternary$libresoc.v:54905$3470_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:54906.16-54916.4" + cell \BRANCH_dec19 \BRANCH_dec19 + connect \BRANCH_dec19_cr_in \BRANCH_dec19_BRANCH_dec19_cr_in + connect \BRANCH_dec19_cr_out \BRANCH_dec19_BRANCH_dec19_cr_out + connect \BRANCH_dec19_function_unit \BRANCH_dec19_BRANCH_dec19_function_unit + connect \BRANCH_dec19_in2_sel \BRANCH_dec19_BRANCH_dec19_in2_sel + connect \BRANCH_dec19_internal_op \BRANCH_dec19_BRANCH_dec19_internal_op + connect \BRANCH_dec19_is_32b \BRANCH_dec19_BRANCH_dec19_is_32b + connect \BRANCH_dec19_lk \BRANCH_dec19_BRANCH_dec19_lk + connect \BRANCH_dec19_rc_sel \BRANCH_dec19_BRANCH_dec19_rc_sel + connect \opcode_in \BRANCH_dec19_opcode_in + end + attribute \src "libresoc.v:53960.7-53960.20" + process $proc$libresoc.v:53960$3479 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:54917.3-54932.6" + process $proc$libresoc.v:54917$3471 + assign { } { } + assign { } { } + assign $0\BRANCH_function_unit[11:0] $1\BRANCH_function_unit[11:0] + attribute \src "libresoc.v:54918.5-54918.29" + switch \initial + attribute \src "libresoc.v:54918.9-54918.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\BRANCH_function_unit[11:0] \BRANCH_dec19_BRANCH_dec19_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\BRANCH_function_unit[11:0] 12'000000100000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\BRANCH_function_unit[11:0] 12'000000100000 + case + assign $1\BRANCH_function_unit[11:0] 12'000000000000 + end + sync always + update \BRANCH_function_unit $0\BRANCH_function_unit[11:0] + end + attribute \src "libresoc.v:54933.3-54948.6" + process $proc$libresoc.v:54933$3472 + assign { } { } + assign { } { } + assign $0\BRANCH_internal_op[6:0] $1\BRANCH_internal_op[6:0] + attribute \src "libresoc.v:54934.5-54934.29" + switch \initial + attribute \src "libresoc.v:54934.9-54934.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\BRANCH_internal_op[6:0] \BRANCH_dec19_BRANCH_dec19_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\BRANCH_internal_op[6:0] 7'0000110 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\BRANCH_internal_op[6:0] 7'0000111 + case + assign $1\BRANCH_internal_op[6:0] 7'0000000 + end + sync always + update \BRANCH_internal_op $0\BRANCH_internal_op[6:0] + end + attribute \src "libresoc.v:54949.3-54964.6" + process $proc$libresoc.v:54949$3473 + assign { } { } + assign { } { } + assign $0\BRANCH_in2_sel[3:0] $1\BRANCH_in2_sel[3:0] + attribute \src "libresoc.v:54950.5-54950.29" + switch \initial + attribute \src "libresoc.v:54950.9-54950.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\BRANCH_in2_sel[3:0] \BRANCH_dec19_BRANCH_dec19_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\BRANCH_in2_sel[3:0] 4'0110 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\BRANCH_in2_sel[3:0] 4'0111 + case + assign $1\BRANCH_in2_sel[3:0] 4'0000 + end + sync always + update \BRANCH_in2_sel $0\BRANCH_in2_sel[3:0] + end + attribute \src "libresoc.v:54965.3-54980.6" + process $proc$libresoc.v:54965$3474 + assign { } { } + assign { } { } + assign $0\BRANCH_cr_in[2:0] $1\BRANCH_cr_in[2:0] + attribute \src "libresoc.v:54966.5-54966.29" + switch \initial + attribute \src "libresoc.v:54966.9-54966.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\BRANCH_cr_in[2:0] \BRANCH_dec19_BRANCH_dec19_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\BRANCH_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\BRANCH_cr_in[2:0] 3'010 + case + assign $1\BRANCH_cr_in[2:0] 3'000 + end + sync always + update \BRANCH_cr_in $0\BRANCH_cr_in[2:0] + end + attribute \src "libresoc.v:54981.3-54996.6" + process $proc$libresoc.v:54981$3475 + assign { } { } + assign { } { } + assign $0\BRANCH_cr_out[2:0] $1\BRANCH_cr_out[2:0] + attribute \src "libresoc.v:54982.5-54982.29" + switch \initial + attribute \src "libresoc.v:54982.9-54982.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\BRANCH_cr_out[2:0] \BRANCH_dec19_BRANCH_dec19_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\BRANCH_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\BRANCH_cr_out[2:0] 3'000 + case + assign $1\BRANCH_cr_out[2:0] 3'000 + end + sync always + update \BRANCH_cr_out $0\BRANCH_cr_out[2:0] + end + attribute \src "libresoc.v:54997.3-55012.6" + process $proc$libresoc.v:54997$3476 + assign { } { } + assign { } { } + assign $0\BRANCH_rc_sel[1:0] $1\BRANCH_rc_sel[1:0] + attribute \src "libresoc.v:54998.5-54998.29" + switch \initial + attribute \src "libresoc.v:54998.9-54998.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\BRANCH_rc_sel[1:0] \BRANCH_dec19_BRANCH_dec19_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\BRANCH_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\BRANCH_rc_sel[1:0] 2'00 + case + assign $1\BRANCH_rc_sel[1:0] 2'00 + end + sync always + update \BRANCH_rc_sel $0\BRANCH_rc_sel[1:0] + end + attribute \src "libresoc.v:55013.3-55028.6" + process $proc$libresoc.v:55013$3477 + assign { } { } + assign { } { } + assign $0\BRANCH_is_32b[0:0] $1\BRANCH_is_32b[0:0] + attribute \src "libresoc.v:55014.5-55014.29" + switch \initial + attribute \src "libresoc.v:55014.9-55014.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\BRANCH_is_32b[0:0] \BRANCH_dec19_BRANCH_dec19_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\BRANCH_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\BRANCH_is_32b[0:0] 1'0 + case + assign $1\BRANCH_is_32b[0:0] 1'0 + end + sync always + update \BRANCH_is_32b $0\BRANCH_is_32b[0:0] + end + attribute \src "libresoc.v:55029.3-55044.6" + process $proc$libresoc.v:55029$3478 + assign { } { } + assign { } { } + assign $0\BRANCH_lk[0:0] $1\BRANCH_lk[0:0] + attribute \src "libresoc.v:55030.5-55030.29" + switch \initial + attribute \src "libresoc.v:55030.9-55030.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\BRANCH_lk[0:0] \BRANCH_dec19_BRANCH_dec19_lk + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\BRANCH_lk[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\BRANCH_lk[0:0] 1'1 + case + assign $1\BRANCH_lk[0:0] 1'0 + end + sync always + update \BRANCH_lk $0\BRANCH_lk[0:0] + end + connect \$1 $ternary$libresoc.v:54905$3470_Y + connect \VC_XO \opcode_in [9:0] + connect \VC_VRT \opcode_in [25:21] + connect \VC_VRB \opcode_in [15:11] + connect \VC_VRA \opcode_in [20:16] + connect \VC_Rc \opcode_in [10] + connect \XS_XO \opcode_in [10:2] + connect \XS_sh { \opcode_in [1] \opcode_in [15:11] } + connect \XS_RS \opcode_in [25:21] + connect \XS_Rc \opcode_in [0] + connect \XS_RA \opcode_in [20:16] + connect \VA_XO \opcode_in [5:0] + connect \VA_VRT \opcode_in [25:21] + connect \VA_VRC \opcode_in [10:6] + connect \VA_VRB \opcode_in [15:11] + connect \VA_VRA \opcode_in [20:16] + connect \VA_SHB \opcode_in [9:6] + connect \VA_RT \opcode_in [25:21] + connect \VA_RC \opcode_in [10:6] + connect \VA_RB \opcode_in [15:11] + connect \VA_RA \opcode_in [20:16] + connect \TX_XO \opcode_in [6:1] + connect \TX_XBI \opcode_in [10:7] + connect \TX_UI \opcode_in [15:11] + connect \TX_RA \opcode_in [20:16] + connect \DQE_XO \opcode_in [1:0] + connect \DQE_RT \opcode_in [25:21] + connect \DQE_RA \opcode_in [20:16] + connect \XO_XO \opcode_in [9:1] + connect \XO_RT \opcode_in [25:21] + connect \XO_Rc \opcode_in [0] + connect \XO_RB \opcode_in [15:11] + connect \XO_RA \opcode_in [20:16] + connect \XO_OE \opcode_in [10] + connect \all_PO \opcode_in [31:26] + connect \all_OPCD \opcode_in [31:26] + connect \MD_XO \opcode_in [4:2] + connect \MD_sh { \opcode_in [1] \opcode_in [15:11] } + connect \MD_RS \opcode_in [25:21] + connect \MD_Rc \opcode_in [0] + connect \MD_RA \opcode_in [20:16] + connect \MD_me \opcode_in [10:5] + connect \MD_mb \opcode_in [10:5] + connect \M_SH \opcode_in [15:11] + connect \M_RS \opcode_in [25:21] + connect \M_Rc \opcode_in [0] + connect \M_RB \opcode_in [15:11] + connect \M_RA \opcode_in [20:16] + connect \M_ME \opcode_in [5:1] + connect \M_MB \opcode_in [10:6] + connect \SC_XO_1 \opcode_in [1:0] + connect \SC_XO \opcode_in [1] + connect \SC_LEV \opcode_in [11:5] + connect \MDS_XO \opcode_in [4:1] + connect \MDS_XBI_1 \opcode_in [10:7] + connect \MDS_XBI \opcode_in [10:7] + connect \MDS_RS \opcode_in [25:21] + connect \MDS_Rc \opcode_in [0] + connect \MDS_RB \opcode_in [15:11] + connect \MDS_RA \opcode_in [20:16] + connect \MDS_me \opcode_in [10:5] + connect \MDS_mb \opcode_in [10:5] + connect \MDS_IS \opcode_in [25:21] + connect \MDS_IB \opcode_in [15:11] + connect \Z23_XO \opcode_in [8:1] + connect \Z23_TE \opcode_in [20:16] + connect \Z23_RMC \opcode_in [10:9] + connect \Z23_Rc \opcode_in [0] + connect \Z23_R \opcode_in [16] + connect \Z23_FRTp \opcode_in [25:21] + connect \Z23_FRT \opcode_in [25:21] + connect \Z23_FRBp \opcode_in [15:11] + connect \Z23_FRB \opcode_in [15:11] + connect \Z23_FRAp \opcode_in [20:16] + connect \Z23_FRA \opcode_in [20:16] + connect \XFL_XO \opcode_in [10:1] + connect \XFL_W \opcode_in [16] + connect \XFL_Rc \opcode_in [0] + connect \XFL_L \opcode_in [25] + connect \XFL_FRB \opcode_in [15:11] + connect \XFL_FLM \opcode_in [24:17] + connect \VX_XO_1 \opcode_in [10:0] + connect \VX_XO { \opcode_in [10] \opcode_in [8:0] } + connect \VX_VRT \opcode_in [25:21] + connect \VX_VRB \opcode_in [15:11] + connect \VX_VRA \opcode_in [20:16] + connect \VX_UIM_3 \opcode_in [17:16] + connect \VX_UIM_2 \opcode_in [18:16] + connect \VX_UIM_1 \opcode_in [19:16] + connect \VX_UIM \opcode_in [20:16] + connect \VX_SIM \opcode_in [20:16] + connect \VX_RT \opcode_in [25:21] + connect \VX_RA \opcode_in [20:16] + connect \VX_PS \opcode_in [9] + connect \VX_EO \opcode_in [20:16] + connect \DS_XO \opcode_in [1:0] + connect \DS_VRT \opcode_in [25:21] + connect \DS_VRS \opcode_in [25:21] + connect \DS_RT \opcode_in [25:21] + connect \DS_RSp \opcode_in [25:21] + connect \DS_RS \opcode_in [25:21] + connect \DS_RA \opcode_in [20:16] + connect \DS_FRTp \opcode_in [25:21] + connect \DS_FRSp \opcode_in [25:21] + connect \DS_DS \opcode_in [15:2] + connect \DQ_XO \opcode_in [2:0] + connect \DQ_TX_T { \opcode_in [3] \opcode_in [25:21] } + connect \DQ_T \opcode_in [25:21] + connect \DQ_TX \opcode_in [3] + connect \DQ_SX_S { \opcode_in [3] \opcode_in [25:21] } + connect \DQ_S \opcode_in [25:21] + connect \DQ_SX \opcode_in [3] + connect \DQ_RTp \opcode_in [25:21] + connect \DQ_RA \opcode_in [20:16] + connect \DQ_PT \opcode_in [3:0] + connect \DQ_DQ \opcode_in [15:4] + connect \DX_XO \opcode_in [5:1] + connect \DX_RT \opcode_in [25:21] + connect \DX_d0_d1_d2 { \opcode_in [15:6] \opcode_in [20:16] \opcode_in [0] } + connect \DX_d2 \opcode_in [0] + connect \DX_d1 \opcode_in [20:16] + connect \DX_d0 \opcode_in [15:6] + connect \XFX_XO \opcode_in [10:1] + connect \XFX_SPR \opcode_in [20:11] + connect \XFX_RT \opcode_in [25:21] + connect \XFX_RS \opcode_in [25:21] + connect \XFX_FXM \opcode_in [19:12] + connect \XFX_DUIS \opcode_in [20:11] + connect \XFX_DUI \opcode_in [25:21] + connect \XFX_BHRBE \opcode_in [20:11] + connect \EVS_BFA \opcode_in [2:0] + connect \Z22_XO \opcode_in [9:1] + connect \Z22_SH \opcode_in [15:10] + connect \Z22_Rc \opcode_in [0] + connect \Z22_FRTp \opcode_in [25:21] + connect \Z22_FRT \opcode_in [25:21] + connect \Z22_FRAp \opcode_in [20:16] + connect \Z22_FRA \opcode_in [20:16] + connect \Z22_DGM \opcode_in [15:10] + connect \Z22_DCM \opcode_in [15:10] + connect \Z22_BF \opcode_in [25:23] + connect \XX2_XO_1 \opcode_in [10:2] + connect \XX2_XO { \opcode_in [10:7] \opcode_in [5:3] } + connect \XX2_UIM_1 \opcode_in [17:16] + connect \XX2_UIM \opcode_in [19:16] + connect \XX2_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX2_T \opcode_in [25:21] + connect \XX2_TX \opcode_in [0] + connect \XX2_RT \opcode_in [25:21] + connect \XX2_EO \opcode_in [20:16] + connect \XX2_DCMX \opcode_in [22:16] + connect \XX2_dc_dm_dx { \opcode_in [6] \opcode_in [2] \opcode_in [20:16] } + connect \XX2_dx \opcode_in [20:16] + connect \XX2_dm \opcode_in [2] + connect \XX2_dc \opcode_in [6] + connect \XX2_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX2_B \opcode_in [15:11] + connect \XX2_BX \opcode_in [1] + connect \XX2_BF \opcode_in [25:23] + connect \D_UI \opcode_in [15:0] + connect \D_TO \opcode_in [25:21] + connect \D_SI \opcode_in [15:0] + connect \D_RT \opcode_in [25:21] + connect \D_RS \opcode_in [25:21] + connect \D_RA \opcode_in [20:16] + connect \D_L \opcode_in [21] + connect \D_FRT \opcode_in [25:21] + connect \D_FRS \opcode_in [25:21] + connect \D_D \opcode_in [15:0] + connect \D_BF \opcode_in [25:23] + connect \A_XO \opcode_in [5:1] + connect \A_RT \opcode_in [25:21] + connect \A_Rc \opcode_in [0] + connect \A_RB \opcode_in [15:11] + connect \A_RA \opcode_in [20:16] + connect \A_FRT \opcode_in [25:21] + connect \A_FRC \opcode_in [10:6] + connect \A_FRB \opcode_in [15:11] + connect \A_FRA \opcode_in [20:16] + connect \A_BC \opcode_in [10:6] + connect \XL_XO \opcode_in [10:1] + connect \XL_S \opcode_in [11] + connect \XL_OC \opcode_in [25:11] + connect \XL_LK \opcode_in [0] + connect \XL_BT \opcode_in [25:21] + connect \XL_BO_1 \opcode_in [25:21] + connect \XL_BO \opcode_in [25:21] + connect \XL_BI \opcode_in [20:16] + connect \XL_BH \opcode_in [12:11] + connect \XL_BFA \opcode_in [20:18] + connect \XL_BF \opcode_in [25:23] + connect \XL_BB \opcode_in [15:11] + connect \XL_BA \opcode_in [20:16] + connect \XX4_XO \opcode_in [5:4] + connect \XX4_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX4_T \opcode_in [25:21] + connect \XX4_TX \opcode_in [0] + connect \XX4_CX_C { \opcode_in [3] \opcode_in [10:6] } + connect \XX4_C \opcode_in [10:6] + connect \XX4_CX \opcode_in [3] + connect \XX4_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX4_B \opcode_in [15:11] + connect \XX4_BX \opcode_in [1] + connect \XX4_AX_A { \opcode_in [2] \opcode_in [20:16] } + connect \XX4_A \opcode_in [20:16] + connect \XX4_AX \opcode_in [2] + connect \XX3_XO_2 \opcode_in [9:1] + connect \XX3_XO_1 \opcode_in [10:3] + connect \XX3_XO \opcode_in [10:7] + connect \XX3_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX3_T \opcode_in [25:21] + connect \XX3_TX \opcode_in [0] + connect \XX3_SHW \opcode_in [9:8] + connect \XX3_Rc \opcode_in [10] + connect \XX3_DM \opcode_in [9:8] + connect \XX3_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX3_B \opcode_in [15:11] + connect \XX3_BX \opcode_in [1] + connect \XX3_BF \opcode_in [25:23] + connect \XX3_AX_A { \opcode_in [2] \opcode_in [20:16] } + connect \XX3_A \opcode_in [20:16] + connect \XX3_AX \opcode_in [2] + connect \I_LK \opcode_in [0] + connect \I_LI \opcode_in [25:2] + connect \I_AA \opcode_in [1] + connect \B_LK \opcode_in [0] + connect \B_BO \opcode_in [25:21] + connect \B_BI \opcode_in [20:16] + connect \B_BD \opcode_in [15:2] + connect \B_AA \opcode_in [1] + connect \X_XO_1 \opcode_in [8:1] + connect \X_XO \opcode_in [10:1] + connect \X_WC \opcode_in [22:21] + connect \X_W \opcode_in [16] + connect \X_VRT \opcode_in [25:21] + connect \X_VRS \opcode_in [25:21] + connect \X_UIM \opcode_in [20:16] + connect \X_U \opcode_in [15:12] + connect \X_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \X_TX \opcode_in [0] + connect \X_TO \opcode_in [25:21] + connect \X_TH \opcode_in [25:21] + connect \X_TBR \opcode_in [20:11] + connect \X_T \opcode_in [25:21] + connect \X_SX_S { \opcode_in [0] \opcode_in [25:21] } + connect \X_SX \opcode_in [0] + connect \X_SR \opcode_in [19:16] + connect \X_SP \opcode_in [20:19] + connect \X_SI \opcode_in [15:11] + connect \X_SH \opcode_in [15:11] + connect \X_S \opcode_in [25:21] + connect \X_RTp \opcode_in [25:21] + connect \X_RT \opcode_in [25:21] + connect \X_RSp \opcode_in [25:21] + connect \X_RS \opcode_in [25:21] + connect \X_RO \opcode_in [0] + connect \X_RM \opcode_in [12:11] + connect \X_RIC \opcode_in [19:18] + connect \X_Rc \opcode_in [0] + connect \X_RB \opcode_in [15:11] + connect \X_RA \opcode_in [20:16] + connect \X_R_1 \opcode_in [16] + connect \X_R \opcode_in [21] + connect \X_PRS \opcode_in [17] + connect \X_NB \opcode_in [15:11] + connect \X_MO \opcode_in [25:21] + connect \X_L3 \opcode_in [17:16] + connect \X_L1 \opcode_in [16] + connect \X_L \opcode_in [21] + connect \X_L2 \opcode_in [22:21] + connect \X_IMM8 \opcode_in [18:11] + connect \X_IH \opcode_in [23:21] + connect \X_FRTp \opcode_in [25:21] + connect \X_FRT \opcode_in [25:21] + connect \X_FRSp \opcode_in [25:21] + connect \X_FRS \opcode_in [25:21] + connect \X_FRBp \opcode_in [15:11] + connect \X_FRB \opcode_in [15:11] + connect \X_FRAp \opcode_in [20:16] + connect \X_FRA \opcode_in [20:16] + connect \X_FC \opcode_in [15:11] + connect \X_EX \opcode_in [0] + connect \X_EO_1 \opcode_in [20:16] + connect \X_EO \opcode_in [20:19] + connect \X_E_1 \opcode_in [19:16] + connect \X_E \opcode_in [15] + connect \X_DRM \opcode_in [13:11] + connect \X_DCMX \opcode_in [22:16] + connect \X_CT \opcode_in [24:21] + connect \X_BO \opcode_in [25:21] + connect \X_BFA \opcode_in [20:18] + connect \X_BF \opcode_in [25:23] + connect \X_A \opcode_in [25] + connect \BRANCH_SPR \opcode_in [20:11] + connect \BRANCH_MB \opcode_in [10:6] + connect \BRANCH_ME \opcode_in [5:1] + connect \BRANCH_SH \opcode_in [15:11] + connect \BRANCH_BC \opcode_in [10:6] + connect \BRANCH_TO \opcode_in [25:21] + connect \BRANCH_DS \opcode_in [15:2] + connect \BRANCH_D \opcode_in [15:0] + connect \BRANCH_BH \opcode_in [12:11] + connect \BRANCH_BI \opcode_in [20:16] + connect \BRANCH_BO \opcode_in [25:21] + connect \BRANCH_FXM \opcode_in [19:12] + connect \BRANCH_BT \opcode_in [25:21] + connect \BRANCH_BA \opcode_in [20:16] + connect \BRANCH_BB \opcode_in [15:11] + connect \BRANCH_CR \opcode_in [10:1] + connect \BRANCH_BF \opcode_in [25:23] + connect \BRANCH_BD \opcode_in [15:2] + connect \BRANCH_OE \opcode_in [10] + connect \BRANCH_Rc \opcode_in [0] + connect \BRANCH_AA \opcode_in [1] + connect \BRANCH_LK \opcode_in [0] + connect \BRANCH_LI \opcode_in [25:2] + connect \BRANCH_ME32 \opcode_in [5:1] + connect \BRANCH_MB32 \opcode_in [10:6] + connect \BRANCH_sh { \opcode_in [1] \opcode_in [15:11] } + connect \BRANCH_SH32 \opcode_in [15:11] + connect \BRANCH_L \opcode_in [21] + connect \BRANCH_UI \opcode_in [15:0] + connect \BRANCH_SI \opcode_in [15:0] + connect \BRANCH_RB \opcode_in [15:11] + connect \BRANCH_RA \opcode_in [20:16] + connect \BRANCH_RT \opcode_in [25:21] + connect \BRANCH_RS \opcode_in [25:21] + connect \opcode_in \$1 + connect \BRANCH_dec19_opcode_in \opcode_in + connect \opcode_switch \opcode_in [31:26] +end +attribute \src "libresoc.v:55378.1-57125.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_LOGICAL.dec" +attribute \generator "nMigen" +module \dec$152 + attribute \src "libresoc.v:56684.3-56711.6" + wire width 3 $0\LOGICAL_cr_in[2:0] + attribute \src "libresoc.v:56712.3-56739.6" + wire width 3 $0\LOGICAL_cr_out[2:0] + attribute \src "libresoc.v:56404.3-56431.6" + wire width 2 $0\LOGICAL_cry_in[1:0] + attribute \src "libresoc.v:56488.3-56515.6" + wire $0\LOGICAL_cry_out[0:0] + attribute \src "libresoc.v:56572.3-56599.6" + wire width 12 $0\LOGICAL_function_unit[11:0] + attribute \src "libresoc.v:56628.3-56655.6" + wire width 3 $0\LOGICAL_in1_sel[2:0] + attribute \src "libresoc.v:56656.3-56683.6" + wire width 4 $0\LOGICAL_in2_sel[3:0] + attribute \src "libresoc.v:56600.3-56627.6" + wire width 7 $0\LOGICAL_internal_op[6:0] + attribute \src "libresoc.v:56432.3-56459.6" + wire $0\LOGICAL_inv_a[0:0] + attribute \src "libresoc.v:56460.3-56487.6" + wire $0\LOGICAL_inv_out[0:0] + attribute \src "libresoc.v:56516.3-56543.6" + wire $0\LOGICAL_is_32b[0:0] + attribute \src "libresoc.v:56740.3-56767.6" + wire width 4 $0\LOGICAL_ldst_len[3:0] + attribute \src "libresoc.v:56768.3-56795.6" + wire width 2 $0\LOGICAL_rc_sel[1:0] + attribute \src "libresoc.v:56544.3-56571.6" + wire $0\LOGICAL_sgn[0:0] + attribute \src "libresoc.v:55379.7-55379.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:56684.3-56711.6" + wire width 3 $1\LOGICAL_cr_in[2:0] + attribute \src "libresoc.v:56712.3-56739.6" + wire width 3 $1\LOGICAL_cr_out[2:0] + attribute \src "libresoc.v:56404.3-56431.6" + wire width 2 $1\LOGICAL_cry_in[1:0] + attribute \src "libresoc.v:56488.3-56515.6" + wire $1\LOGICAL_cry_out[0:0] + attribute \src "libresoc.v:56572.3-56599.6" + wire width 12 $1\LOGICAL_function_unit[11:0] + attribute \src "libresoc.v:56628.3-56655.6" + wire width 3 $1\LOGICAL_in1_sel[2:0] + attribute \src "libresoc.v:56656.3-56683.6" + wire width 4 $1\LOGICAL_in2_sel[3:0] + attribute \src "libresoc.v:56600.3-56627.6" + wire width 7 $1\LOGICAL_internal_op[6:0] + attribute \src "libresoc.v:56432.3-56459.6" + wire $1\LOGICAL_inv_a[0:0] + attribute \src "libresoc.v:56460.3-56487.6" + wire $1\LOGICAL_inv_out[0:0] + attribute \src "libresoc.v:56516.3-56543.6" + wire $1\LOGICAL_is_32b[0:0] + attribute \src "libresoc.v:56740.3-56767.6" + wire width 4 $1\LOGICAL_ldst_len[3:0] + attribute \src "libresoc.v:56768.3-56795.6" + wire width 2 $1\LOGICAL_rc_sel[1:0] + attribute \src "libresoc.v:56544.3-56571.6" + wire $1\LOGICAL_sgn[0:0] + attribute \src "libresoc.v:56386.17-56386.211" + wire width 32 $ternary$libresoc.v:56386$3480_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:478" + wire width 32 \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_FRC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \A_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \B_AA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 14 \B_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \B_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \B_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \B_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DQE_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DQE_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \DQE_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 12 \DQ_DQ + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \DQ_PT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DQ_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DQ_RTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DQ_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \DQ_SX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \DQ_SX_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DQ_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \DQ_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \DQ_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \DQ_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 14 \DS_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_FRSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_RSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_VRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \DS_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DX_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \DX_d0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 16 \DX_d0_d1_d2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DX_d1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \DX_d2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \D_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 16 \D_D + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \D_FRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \D_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \D_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \D_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \D_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \D_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 16 \D_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \D_TO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 16 \D_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \EVS_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \I_AA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 24 \I_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \I_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire \LOGICAL_AA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 output 27 \LOGICAL_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 output 26 \LOGICAL_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 output 32 \LOGICAL_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 14 output 25 \LOGICAL_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 3 \LOGICAL_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 2 \LOGICAL_BH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 output 30 \LOGICAL_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \LOGICAL_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 output 28 \LOGICAL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 10 \LOGICAL_CR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 16 \LOGICAL_D + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 14 output 31 \LOGICAL_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 8 output 29 \LOGICAL_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire \LOGICAL_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 24 output 22 \LOGICAL_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire \LOGICAL_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \LOGICAL_MB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \LOGICAL_MB32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \LOGICAL_ME + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \LOGICAL_ME32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire output 24 \LOGICAL_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 output 17 \LOGICAL_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \LOGICAL_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \LOGICAL_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \LOGICAL_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire output 23 \LOGICAL_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \LOGICAL_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 output 20 \LOGICAL_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 16 output 18 \LOGICAL_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 10 \LOGICAL_SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \LOGICAL_TO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 16 output 19 \LOGICAL_UI + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 4 \LOGICAL_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \LOGICAL_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 13 \LOGICAL_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 14 \LOGICAL_cry_out + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \LOGICAL_dec31_LOGICAL_dec31_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \LOGICAL_dec31_LOGICAL_dec31_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \LOGICAL_dec31_LOGICAL_dec31_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \LOGICAL_dec31_LOGICAL_dec31_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \LOGICAL_dec31_LOGICAL_dec31_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \LOGICAL_dec31_LOGICAL_dec31_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \LOGICAL_dec31_LOGICAL_dec31_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 \LOGICAL_dec31_LOGICAL_dec31_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \LOGICAL_dec31_LOGICAL_dec31_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \LOGICAL_dec31_LOGICAL_dec31_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \LOGICAL_dec31_LOGICAL_dec31_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \LOGICAL_dec31_LOGICAL_dec31_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \LOGICAL_dec31_LOGICAL_dec31_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \LOGICAL_dec31_LOGICAL_dec31_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \LOGICAL_dec31_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 7 \LOGICAL_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 8 \LOGICAL_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 9 \LOGICAL_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 6 \LOGICAL_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 11 \LOGICAL_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 12 \LOGICAL_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 15 \LOGICAL_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 10 \LOGICAL_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 3 \LOGICAL_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 16 \LOGICAL_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 6 output 21 \LOGICAL_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MDS_IB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MDS_IS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MDS_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MDS_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MDS_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \MDS_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \MDS_XBI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \MDS_XBI_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \MDS_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \MDS_mb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \MDS_me + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MD_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MD_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \MD_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \MD_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \MD_mb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \MD_me + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \MD_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \M_MB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \M_ME + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \M_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \M_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \M_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \M_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \M_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 7 \SC_LEV + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \SC_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \SC_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \TX_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \TX_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \TX_XBI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \TX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_RC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \VA_SHB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_VRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_VRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_VRC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \VA_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \VC_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VC_VRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VC_VRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VC_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \VC_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_EO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \VX_PS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_SIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_UIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \VX_UIM_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \VX_UIM_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \VX_UIM_3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_VRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_VRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \VX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 11 \VX_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 8 \XFL_FLM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XFL_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XFL_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XFL_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XFL_W + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \XFL_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \XFX_BHRBE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XFX_DUI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \XFX_DUIS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 8 \XFX_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XFX_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XFX_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \XFX_SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \XFX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XL_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XL_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \XL_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \XL_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \XL_BH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XL_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XL_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XL_BO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 output 35 \XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XL_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 15 \XL_OC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XL_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \XL_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XO_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XO_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XO_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XO_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XO_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 9 \XO_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XS_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XS_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XS_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 9 \XS_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XS_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX2_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \XX2_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX2_BX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX2_BX_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 7 \XX2_DCMX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX2_EO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX2_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX2_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX2_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX2_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \XX2_UIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \XX2_UIM_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 7 \XX2_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 9 \XX2_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX2_dc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 7 \XX2_dc_dm_dx + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX2_dm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX2_dx + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX3_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX3_AX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX3_AX_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX3_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \XX3_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX3_BX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX3_BX_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \XX3_DM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX3_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \XX3_SHW + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX3_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX3_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX3_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \XX3_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 8 \XX3_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 9 \XX3_XO_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX4_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX4_AX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX4_AX_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX4_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX4_BX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX4_BX_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX4_C + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX4_CX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX4_CX_C + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX4_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX4_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX4_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \XX4_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 output 33 \X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 output 34 \X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \X_CT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 7 \X_DCMX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \X_DRM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_E + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \X_EO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_EO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_EX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \X_E_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRAp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRBp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \X_IH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 8 \X_IMM8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_L1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \X_L2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \X_L3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_MO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_NB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_PRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_R + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \X_RIC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \X_RM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_RO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_RSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_RTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_R_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \X_SP + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \X_SR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_SX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \X_SX_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \X_TBR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_TH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_TO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \X_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \X_U + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_UIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_VRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_W + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \X_WC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \X_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 8 \X_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \Z22_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \Z22_DCM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \Z22_DGM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z22_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z22_FRAp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z22_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z22_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \Z22_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \Z22_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 9 \Z22_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_FRAp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_FRBp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \Z23_R + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \Z23_RMC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \Z23_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_TE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 8 \Z23_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \all_OPCD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \all_PO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + wire input 1 \bigendian + attribute \src "libresoc.v:55379.7-55379.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 output 2 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 6 \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:442" + wire width 32 input 36 \raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:478" + cell $mux $ternary$libresoc.v:56386$3480 + parameter \WIDTH 32 + connect \A \raw_opcode_in + connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } + connect \S \bigendian + connect \Y $ternary$libresoc.v:56386$3480_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:56387.17-56403.4" + cell \LOGICAL_dec31 \LOGICAL_dec31 + connect \LOGICAL_dec31_cr_in \LOGICAL_dec31_LOGICAL_dec31_cr_in + connect \LOGICAL_dec31_cr_out \LOGICAL_dec31_LOGICAL_dec31_cr_out + connect \LOGICAL_dec31_cry_in \LOGICAL_dec31_LOGICAL_dec31_cry_in + connect \LOGICAL_dec31_cry_out \LOGICAL_dec31_LOGICAL_dec31_cry_out + connect \LOGICAL_dec31_function_unit \LOGICAL_dec31_LOGICAL_dec31_function_unit + connect \LOGICAL_dec31_in1_sel \LOGICAL_dec31_LOGICAL_dec31_in1_sel + connect \LOGICAL_dec31_in2_sel \LOGICAL_dec31_LOGICAL_dec31_in2_sel + connect \LOGICAL_dec31_internal_op \LOGICAL_dec31_LOGICAL_dec31_internal_op + connect \LOGICAL_dec31_inv_a \LOGICAL_dec31_LOGICAL_dec31_inv_a + connect \LOGICAL_dec31_inv_out \LOGICAL_dec31_LOGICAL_dec31_inv_out + connect \LOGICAL_dec31_is_32b \LOGICAL_dec31_LOGICAL_dec31_is_32b + connect \LOGICAL_dec31_ldst_len \LOGICAL_dec31_LOGICAL_dec31_ldst_len + connect \LOGICAL_dec31_rc_sel \LOGICAL_dec31_LOGICAL_dec31_rc_sel + connect \LOGICAL_dec31_sgn \LOGICAL_dec31_LOGICAL_dec31_sgn + connect \opcode_in \LOGICAL_dec31_opcode_in + end + attribute \src "libresoc.v:55379.7-55379.20" + process $proc$libresoc.v:55379$3495 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:56404.3-56431.6" + process $proc$libresoc.v:56404$3481 + assign { } { } + assign { } { } + assign $0\LOGICAL_cry_in[1:0] $1\LOGICAL_cry_in[1:0] + attribute \src "libresoc.v:56405.5-56405.29" + switch \initial + attribute \src "libresoc.v:56405.9-56405.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\LOGICAL_cry_in[1:0] \LOGICAL_dec31_LOGICAL_dec31_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\LOGICAL_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\LOGICAL_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\LOGICAL_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\LOGICAL_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\LOGICAL_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\LOGICAL_cry_in[1:0] 2'00 + case + assign $1\LOGICAL_cry_in[1:0] 2'00 + end + sync always + update \LOGICAL_cry_in $0\LOGICAL_cry_in[1:0] + end + attribute \src "libresoc.v:56432.3-56459.6" + process $proc$libresoc.v:56432$3482 + assign { } { } + assign { } { } + assign $0\LOGICAL_inv_a[0:0] $1\LOGICAL_inv_a[0:0] + attribute \src "libresoc.v:56433.5-56433.29" + switch \initial + attribute \src "libresoc.v:56433.9-56433.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\LOGICAL_inv_a[0:0] \LOGICAL_dec31_LOGICAL_dec31_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\LOGICAL_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\LOGICAL_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\LOGICAL_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\LOGICAL_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\LOGICAL_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\LOGICAL_inv_a[0:0] 1'0 + case + assign $1\LOGICAL_inv_a[0:0] 1'0 + end + sync always + update \LOGICAL_inv_a $0\LOGICAL_inv_a[0:0] + end + attribute \src "libresoc.v:56460.3-56487.6" + process $proc$libresoc.v:56460$3483 + assign { } { } + assign { } { } + assign $0\LOGICAL_inv_out[0:0] $1\LOGICAL_inv_out[0:0] + attribute \src "libresoc.v:56461.5-56461.29" + switch \initial + attribute \src "libresoc.v:56461.9-56461.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\LOGICAL_inv_out[0:0] \LOGICAL_dec31_LOGICAL_dec31_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\LOGICAL_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\LOGICAL_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\LOGICAL_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\LOGICAL_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\LOGICAL_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\LOGICAL_inv_out[0:0] 1'0 + case + assign $1\LOGICAL_inv_out[0:0] 1'0 + end + sync always + update \LOGICAL_inv_out $0\LOGICAL_inv_out[0:0] + end + attribute \src "libresoc.v:56488.3-56515.6" + process $proc$libresoc.v:56488$3484 + assign { } { } + assign { } { } + assign $0\LOGICAL_cry_out[0:0] $1\LOGICAL_cry_out[0:0] + attribute \src "libresoc.v:56489.5-56489.29" + switch \initial + attribute \src "libresoc.v:56489.9-56489.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\LOGICAL_cry_out[0:0] \LOGICAL_dec31_LOGICAL_dec31_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\LOGICAL_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\LOGICAL_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\LOGICAL_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\LOGICAL_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\LOGICAL_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\LOGICAL_cry_out[0:0] 1'0 + case + assign $1\LOGICAL_cry_out[0:0] 1'0 + end + sync always + update \LOGICAL_cry_out $0\LOGICAL_cry_out[0:0] + end + attribute \src "libresoc.v:56516.3-56543.6" + process $proc$libresoc.v:56516$3485 + assign { } { } + assign { } { } + assign $0\LOGICAL_is_32b[0:0] $1\LOGICAL_is_32b[0:0] + attribute \src "libresoc.v:56517.5-56517.29" + switch \initial + attribute \src "libresoc.v:56517.9-56517.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\LOGICAL_is_32b[0:0] \LOGICAL_dec31_LOGICAL_dec31_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\LOGICAL_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\LOGICAL_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\LOGICAL_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\LOGICAL_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\LOGICAL_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\LOGICAL_is_32b[0:0] 1'0 + case + assign $1\LOGICAL_is_32b[0:0] 1'0 + end + sync always + update \LOGICAL_is_32b $0\LOGICAL_is_32b[0:0] + end + attribute \src "libresoc.v:56544.3-56571.6" + process $proc$libresoc.v:56544$3486 + assign { } { } + assign { } { } + assign $0\LOGICAL_sgn[0:0] $1\LOGICAL_sgn[0:0] + attribute \src "libresoc.v:56545.5-56545.29" + switch \initial + attribute \src "libresoc.v:56545.9-56545.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\LOGICAL_sgn[0:0] \LOGICAL_dec31_LOGICAL_dec31_sgn + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\LOGICAL_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\LOGICAL_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\LOGICAL_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\LOGICAL_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\LOGICAL_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\LOGICAL_sgn[0:0] 1'0 + case + assign $1\LOGICAL_sgn[0:0] 1'0 + end + sync always + update \LOGICAL_sgn $0\LOGICAL_sgn[0:0] + end + attribute \src "libresoc.v:56572.3-56599.6" + process $proc$libresoc.v:56572$3487 + assign { } { } + assign { } { } + assign $0\LOGICAL_function_unit[11:0] $1\LOGICAL_function_unit[11:0] + attribute \src "libresoc.v:56573.5-56573.29" + switch \initial + attribute \src "libresoc.v:56573.9-56573.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\LOGICAL_function_unit[11:0] \LOGICAL_dec31_LOGICAL_dec31_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\LOGICAL_function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\LOGICAL_function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\LOGICAL_function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\LOGICAL_function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\LOGICAL_function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\LOGICAL_function_unit[11:0] 12'000000010000 + case + assign $1\LOGICAL_function_unit[11:0] 12'000000000000 + end + sync always + update \LOGICAL_function_unit $0\LOGICAL_function_unit[11:0] + end + attribute \src "libresoc.v:56600.3-56627.6" + process $proc$libresoc.v:56600$3488 + assign { } { } + assign { } { } + assign $0\LOGICAL_internal_op[6:0] $1\LOGICAL_internal_op[6:0] + attribute \src "libresoc.v:56601.5-56601.29" + switch \initial + attribute \src "libresoc.v:56601.9-56601.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\LOGICAL_internal_op[6:0] \LOGICAL_dec31_LOGICAL_dec31_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\LOGICAL_internal_op[6:0] 7'0000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\LOGICAL_internal_op[6:0] 7'0000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\LOGICAL_internal_op[6:0] 7'0110101 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\LOGICAL_internal_op[6:0] 7'0110101 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\LOGICAL_internal_op[6:0] 7'1000011 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\LOGICAL_internal_op[6:0] 7'1000011 + case + assign $1\LOGICAL_internal_op[6:0] 7'0000000 + end + sync always + update \LOGICAL_internal_op $0\LOGICAL_internal_op[6:0] + end + attribute \src "libresoc.v:56628.3-56655.6" + process $proc$libresoc.v:56628$3489 + assign { } { } + assign { } { } + assign $0\LOGICAL_in1_sel[2:0] $1\LOGICAL_in1_sel[2:0] + attribute \src "libresoc.v:56629.5-56629.29" + switch \initial + attribute \src "libresoc.v:56629.9-56629.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\LOGICAL_in1_sel[2:0] \LOGICAL_dec31_LOGICAL_dec31_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\LOGICAL_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\LOGICAL_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\LOGICAL_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\LOGICAL_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\LOGICAL_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\LOGICAL_in1_sel[2:0] 3'100 + case + assign $1\LOGICAL_in1_sel[2:0] 3'000 + end + sync always + update \LOGICAL_in1_sel $0\LOGICAL_in1_sel[2:0] + end + attribute \src "libresoc.v:56656.3-56683.6" + process $proc$libresoc.v:56656$3490 + assign { } { } + assign { } { } + assign $0\LOGICAL_in2_sel[3:0] $1\LOGICAL_in2_sel[3:0] + attribute \src "libresoc.v:56657.5-56657.29" + switch \initial + attribute \src "libresoc.v:56657.9-56657.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\LOGICAL_in2_sel[3:0] \LOGICAL_dec31_LOGICAL_dec31_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\LOGICAL_in2_sel[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\LOGICAL_in2_sel[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\LOGICAL_in2_sel[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\LOGICAL_in2_sel[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\LOGICAL_in2_sel[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\LOGICAL_in2_sel[3:0] 4'0100 + case + assign $1\LOGICAL_in2_sel[3:0] 4'0000 + end + sync always + update \LOGICAL_in2_sel $0\LOGICAL_in2_sel[3:0] + end + attribute \src "libresoc.v:56684.3-56711.6" + process $proc$libresoc.v:56684$3491 + assign { } { } + assign { } { } + assign $0\LOGICAL_cr_in[2:0] $1\LOGICAL_cr_in[2:0] + attribute \src "libresoc.v:56685.5-56685.29" + switch \initial + attribute \src "libresoc.v:56685.9-56685.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\LOGICAL_cr_in[2:0] \LOGICAL_dec31_LOGICAL_dec31_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\LOGICAL_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\LOGICAL_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\LOGICAL_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\LOGICAL_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\LOGICAL_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\LOGICAL_cr_in[2:0] 3'000 + case + assign $1\LOGICAL_cr_in[2:0] 3'000 + end + sync always + update \LOGICAL_cr_in $0\LOGICAL_cr_in[2:0] + end + attribute \src "libresoc.v:56712.3-56739.6" + process $proc$libresoc.v:56712$3492 + assign { } { } + assign { } { } + assign $0\LOGICAL_cr_out[2:0] $1\LOGICAL_cr_out[2:0] + attribute \src "libresoc.v:56713.5-56713.29" + switch \initial + attribute \src "libresoc.v:56713.9-56713.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\LOGICAL_cr_out[2:0] \LOGICAL_dec31_LOGICAL_dec31_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\LOGICAL_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\LOGICAL_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\LOGICAL_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\LOGICAL_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\LOGICAL_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\LOGICAL_cr_out[2:0] 3'000 + case + assign $1\LOGICAL_cr_out[2:0] 3'000 + end + sync always + update \LOGICAL_cr_out $0\LOGICAL_cr_out[2:0] + end + attribute \src "libresoc.v:56740.3-56767.6" + process $proc$libresoc.v:56740$3493 + assign { } { } + assign { } { } + assign $0\LOGICAL_ldst_len[3:0] $1\LOGICAL_ldst_len[3:0] + attribute \src "libresoc.v:56741.5-56741.29" + switch \initial + attribute \src "libresoc.v:56741.9-56741.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\LOGICAL_ldst_len[3:0] \LOGICAL_dec31_LOGICAL_dec31_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\LOGICAL_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\LOGICAL_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\LOGICAL_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\LOGICAL_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\LOGICAL_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\LOGICAL_ldst_len[3:0] 4'0000 + case + assign $1\LOGICAL_ldst_len[3:0] 4'0000 + end + sync always + update \LOGICAL_ldst_len $0\LOGICAL_ldst_len[3:0] + end + attribute \src "libresoc.v:56768.3-56795.6" + process $proc$libresoc.v:56768$3494 + assign { } { } + assign { } { } + assign $0\LOGICAL_rc_sel[1:0] $1\LOGICAL_rc_sel[1:0] + attribute \src "libresoc.v:56769.5-56769.29" + switch \initial + attribute \src "libresoc.v:56769.9-56769.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\LOGICAL_rc_sel[1:0] \LOGICAL_dec31_LOGICAL_dec31_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\LOGICAL_rc_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\LOGICAL_rc_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\LOGICAL_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\LOGICAL_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\LOGICAL_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\LOGICAL_rc_sel[1:0] 2'00 + case + assign $1\LOGICAL_rc_sel[1:0] 2'00 + end + sync always + update \LOGICAL_rc_sel $0\LOGICAL_rc_sel[1:0] + end + connect \$1 $ternary$libresoc.v:56386$3480_Y + connect \VC_XO \opcode_in [9:0] + connect \VC_VRT \opcode_in [25:21] + connect \VC_VRB \opcode_in [15:11] + connect \VC_VRA \opcode_in [20:16] + connect \VC_Rc \opcode_in [10] + connect \XS_XO \opcode_in [10:2] + connect \XS_sh { \opcode_in [1] \opcode_in [15:11] } + connect \XS_RS \opcode_in [25:21] + connect \XS_Rc \opcode_in [0] + connect \XS_RA \opcode_in [20:16] + connect \VA_XO \opcode_in [5:0] + connect \VA_VRT \opcode_in [25:21] + connect \VA_VRC \opcode_in [10:6] + connect \VA_VRB \opcode_in [15:11] + connect \VA_VRA \opcode_in [20:16] + connect \VA_SHB \opcode_in [9:6] + connect \VA_RT \opcode_in [25:21] + connect \VA_RC \opcode_in [10:6] + connect \VA_RB \opcode_in [15:11] + connect \VA_RA \opcode_in [20:16] + connect \TX_XO \opcode_in [6:1] + connect \TX_XBI \opcode_in [10:7] + connect \TX_UI \opcode_in [15:11] + connect \TX_RA \opcode_in [20:16] + connect \DQE_XO \opcode_in [1:0] + connect \DQE_RT \opcode_in [25:21] + connect \DQE_RA \opcode_in [20:16] + connect \XO_XO \opcode_in [9:1] + connect \XO_RT \opcode_in [25:21] + connect \XO_Rc \opcode_in [0] + connect \XO_RB \opcode_in [15:11] + connect \XO_RA \opcode_in [20:16] + connect \XO_OE \opcode_in [10] + connect \all_PO \opcode_in [31:26] + connect \all_OPCD \opcode_in [31:26] + connect \MD_XO \opcode_in [4:2] + connect \MD_sh { \opcode_in [1] \opcode_in [15:11] } + connect \MD_RS \opcode_in [25:21] + connect \MD_Rc \opcode_in [0] + connect \MD_RA \opcode_in [20:16] + connect \MD_me \opcode_in [10:5] + connect \MD_mb \opcode_in [10:5] + connect \M_SH \opcode_in [15:11] + connect \M_RS \opcode_in [25:21] + connect \M_Rc \opcode_in [0] + connect \M_RB \opcode_in [15:11] + connect \M_RA \opcode_in [20:16] + connect \M_ME \opcode_in [5:1] + connect \M_MB \opcode_in [10:6] + connect \SC_XO_1 \opcode_in [1:0] + connect \SC_XO \opcode_in [1] + connect \SC_LEV \opcode_in [11:5] + connect \MDS_XO \opcode_in [4:1] + connect \MDS_XBI_1 \opcode_in [10:7] + connect \MDS_XBI \opcode_in [10:7] + connect \MDS_RS \opcode_in [25:21] + connect \MDS_Rc \opcode_in [0] + connect \MDS_RB \opcode_in [15:11] + connect \MDS_RA \opcode_in [20:16] + connect \MDS_me \opcode_in [10:5] + connect \MDS_mb \opcode_in [10:5] + connect \MDS_IS \opcode_in [25:21] + connect \MDS_IB \opcode_in [15:11] + connect \Z23_XO \opcode_in [8:1] + connect \Z23_TE \opcode_in [20:16] + connect \Z23_RMC \opcode_in [10:9] + connect \Z23_Rc \opcode_in [0] + connect \Z23_R \opcode_in [16] + connect \Z23_FRTp \opcode_in [25:21] + connect \Z23_FRT \opcode_in [25:21] + connect \Z23_FRBp \opcode_in [15:11] + connect \Z23_FRB \opcode_in [15:11] + connect \Z23_FRAp \opcode_in [20:16] + connect \Z23_FRA \opcode_in [20:16] + connect \XFL_XO \opcode_in [10:1] + connect \XFL_W \opcode_in [16] + connect \XFL_Rc \opcode_in [0] + connect \XFL_L \opcode_in [25] + connect \XFL_FRB \opcode_in [15:11] + connect \XFL_FLM \opcode_in [24:17] + connect \VX_XO_1 \opcode_in [10:0] + connect \VX_XO { \opcode_in [10] \opcode_in [8:0] } + connect \VX_VRT \opcode_in [25:21] + connect \VX_VRB \opcode_in [15:11] + connect \VX_VRA \opcode_in [20:16] + connect \VX_UIM_3 \opcode_in [17:16] + connect \VX_UIM_2 \opcode_in [18:16] + connect \VX_UIM_1 \opcode_in [19:16] + connect \VX_UIM \opcode_in [20:16] + connect \VX_SIM \opcode_in [20:16] + connect \VX_RT \opcode_in [25:21] + connect \VX_RA \opcode_in [20:16] + connect \VX_PS \opcode_in [9] + connect \VX_EO \opcode_in [20:16] + connect \DS_XO \opcode_in [1:0] + connect \DS_VRT \opcode_in [25:21] + connect \DS_VRS \opcode_in [25:21] + connect \DS_RT \opcode_in [25:21] + connect \DS_RSp \opcode_in [25:21] + connect \DS_RS \opcode_in [25:21] + connect \DS_RA \opcode_in [20:16] + connect \DS_FRTp \opcode_in [25:21] + connect \DS_FRSp \opcode_in [25:21] + connect \DS_DS \opcode_in [15:2] + connect \DQ_XO \opcode_in [2:0] + connect \DQ_TX_T { \opcode_in [3] \opcode_in [25:21] } + connect \DQ_T \opcode_in [25:21] + connect \DQ_TX \opcode_in [3] + connect \DQ_SX_S { \opcode_in [3] \opcode_in [25:21] } + connect \DQ_S \opcode_in [25:21] + connect \DQ_SX \opcode_in [3] + connect \DQ_RTp \opcode_in [25:21] + connect \DQ_RA \opcode_in [20:16] + connect \DQ_PT \opcode_in [3:0] + connect \DQ_DQ \opcode_in [15:4] + connect \DX_XO \opcode_in [5:1] + connect \DX_RT \opcode_in [25:21] + connect \DX_d0_d1_d2 { \opcode_in [15:6] \opcode_in [20:16] \opcode_in [0] } + connect \DX_d2 \opcode_in [0] + connect \DX_d1 \opcode_in [20:16] + connect \DX_d0 \opcode_in [15:6] + connect \XFX_XO \opcode_in [10:1] + connect \XFX_SPR \opcode_in [20:11] + connect \XFX_RT \opcode_in [25:21] + connect \XFX_RS \opcode_in [25:21] + connect \XFX_FXM \opcode_in [19:12] + connect \XFX_DUIS \opcode_in [20:11] + connect \XFX_DUI \opcode_in [25:21] + connect \XFX_BHRBE \opcode_in [20:11] + connect \EVS_BFA \opcode_in [2:0] + connect \Z22_XO \opcode_in [9:1] + connect \Z22_SH \opcode_in [15:10] + connect \Z22_Rc \opcode_in [0] + connect \Z22_FRTp \opcode_in [25:21] + connect \Z22_FRT \opcode_in [25:21] + connect \Z22_FRAp \opcode_in [20:16] + connect \Z22_FRA \opcode_in [20:16] + connect \Z22_DGM \opcode_in [15:10] + connect \Z22_DCM \opcode_in [15:10] + connect \Z22_BF \opcode_in [25:23] + connect \XX2_XO_1 \opcode_in [10:2] + connect \XX2_XO { \opcode_in [10:7] \opcode_in [5:3] } + connect \XX2_UIM_1 \opcode_in [17:16] + connect \XX2_UIM \opcode_in [19:16] + connect \XX2_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX2_T \opcode_in [25:21] + connect \XX2_TX \opcode_in [0] + connect \XX2_RT \opcode_in [25:21] + connect \XX2_EO \opcode_in [20:16] + connect \XX2_DCMX \opcode_in [22:16] + connect \XX2_dc_dm_dx { \opcode_in [6] \opcode_in [2] \opcode_in [20:16] } + connect \XX2_dx \opcode_in [20:16] + connect \XX2_dm \opcode_in [2] + connect \XX2_dc \opcode_in [6] + connect \XX2_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX2_B \opcode_in [15:11] + connect \XX2_BX \opcode_in [1] + connect \XX2_BF \opcode_in [25:23] + connect \D_UI \opcode_in [15:0] + connect \D_TO \opcode_in [25:21] + connect \D_SI \opcode_in [15:0] + connect \D_RT \opcode_in [25:21] + connect \D_RS \opcode_in [25:21] + connect \D_RA \opcode_in [20:16] + connect \D_L \opcode_in [21] + connect \D_FRT \opcode_in [25:21] + connect \D_FRS \opcode_in [25:21] + connect \D_D \opcode_in [15:0] + connect \D_BF \opcode_in [25:23] + connect \A_XO \opcode_in [5:1] + connect \A_RT \opcode_in [25:21] + connect \A_Rc \opcode_in [0] + connect \A_RB \opcode_in [15:11] + connect \A_RA \opcode_in [20:16] + connect \A_FRT \opcode_in [25:21] + connect \A_FRC \opcode_in [10:6] + connect \A_FRB \opcode_in [15:11] + connect \A_FRA \opcode_in [20:16] + connect \A_BC \opcode_in [10:6] + connect \XL_XO \opcode_in [10:1] + connect \XL_S \opcode_in [11] + connect \XL_OC \opcode_in [25:11] + connect \XL_LK \opcode_in [0] + connect \XL_BT \opcode_in [25:21] + connect \XL_BO_1 \opcode_in [25:21] + connect \XL_BO \opcode_in [25:21] + connect \XL_BI \opcode_in [20:16] + connect \XL_BH \opcode_in [12:11] + connect \XL_BFA \opcode_in [20:18] + connect \XL_BF \opcode_in [25:23] + connect \XL_BB \opcode_in [15:11] + connect \XL_BA \opcode_in [20:16] + connect \XX4_XO \opcode_in [5:4] + connect \XX4_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX4_T \opcode_in [25:21] + connect \XX4_TX \opcode_in [0] + connect \XX4_CX_C { \opcode_in [3] \opcode_in [10:6] } + connect \XX4_C \opcode_in [10:6] + connect \XX4_CX \opcode_in [3] + connect \XX4_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX4_B \opcode_in [15:11] + connect \XX4_BX \opcode_in [1] + connect \XX4_AX_A { \opcode_in [2] \opcode_in [20:16] } + connect \XX4_A \opcode_in [20:16] + connect \XX4_AX \opcode_in [2] + connect \XX3_XO_2 \opcode_in [9:1] + connect \XX3_XO_1 \opcode_in [10:3] + connect \XX3_XO \opcode_in [10:7] + connect \XX3_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX3_T \opcode_in [25:21] + connect \XX3_TX \opcode_in [0] + connect \XX3_SHW \opcode_in [9:8] + connect \XX3_Rc \opcode_in [10] + connect \XX3_DM \opcode_in [9:8] + connect \XX3_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX3_B \opcode_in [15:11] + connect \XX3_BX \opcode_in [1] + connect \XX3_BF \opcode_in [25:23] + connect \XX3_AX_A { \opcode_in [2] \opcode_in [20:16] } + connect \XX3_A \opcode_in [20:16] + connect \XX3_AX \opcode_in [2] + connect \I_LK \opcode_in [0] + connect \I_LI \opcode_in [25:2] + connect \I_AA \opcode_in [1] + connect \B_LK \opcode_in [0] + connect \B_BO \opcode_in [25:21] + connect \B_BI \opcode_in [20:16] + connect \B_BD \opcode_in [15:2] + connect \B_AA \opcode_in [1] + connect \X_XO_1 \opcode_in [8:1] + connect \X_XO \opcode_in [10:1] + connect \X_WC \opcode_in [22:21] + connect \X_W \opcode_in [16] + connect \X_VRT \opcode_in [25:21] + connect \X_VRS \opcode_in [25:21] + connect \X_UIM \opcode_in [20:16] + connect \X_U \opcode_in [15:12] + connect \X_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \X_TX \opcode_in [0] + connect \X_TO \opcode_in [25:21] + connect \X_TH \opcode_in [25:21] + connect \X_TBR \opcode_in [20:11] + connect \X_T \opcode_in [25:21] + connect \X_SX_S { \opcode_in [0] \opcode_in [25:21] } + connect \X_SX \opcode_in [0] + connect \X_SR \opcode_in [19:16] + connect \X_SP \opcode_in [20:19] + connect \X_SI \opcode_in [15:11] + connect \X_SH \opcode_in [15:11] + connect \X_S \opcode_in [25:21] + connect \X_RTp \opcode_in [25:21] + connect \X_RT \opcode_in [25:21] + connect \X_RSp \opcode_in [25:21] + connect \X_RS \opcode_in [25:21] + connect \X_RO \opcode_in [0] + connect \X_RM \opcode_in [12:11] + connect \X_RIC \opcode_in [19:18] + connect \X_Rc \opcode_in [0] + connect \X_RB \opcode_in [15:11] + connect \X_RA \opcode_in [20:16] + connect \X_R_1 \opcode_in [16] + connect \X_R \opcode_in [21] + connect \X_PRS \opcode_in [17] + connect \X_NB \opcode_in [15:11] + connect \X_MO \opcode_in [25:21] + connect \X_L3 \opcode_in [17:16] + connect \X_L1 \opcode_in [16] + connect \X_L \opcode_in [21] + connect \X_L2 \opcode_in [22:21] + connect \X_IMM8 \opcode_in [18:11] + connect \X_IH \opcode_in [23:21] + connect \X_FRTp \opcode_in [25:21] + connect \X_FRT \opcode_in [25:21] + connect \X_FRSp \opcode_in [25:21] + connect \X_FRS \opcode_in [25:21] + connect \X_FRBp \opcode_in [15:11] + connect \X_FRB \opcode_in [15:11] + connect \X_FRAp \opcode_in [20:16] + connect \X_FRA \opcode_in [20:16] + connect \X_FC \opcode_in [15:11] + connect \X_EX \opcode_in [0] + connect \X_EO_1 \opcode_in [20:16] + connect \X_EO \opcode_in [20:19] + connect \X_E_1 \opcode_in [19:16] + connect \X_E \opcode_in [15] + connect \X_DRM \opcode_in [13:11] + connect \X_DCMX \opcode_in [22:16] + connect \X_CT \opcode_in [24:21] + connect \X_BO \opcode_in [25:21] + connect \X_BFA \opcode_in [20:18] + connect \X_BF \opcode_in [25:23] + connect \X_A \opcode_in [25] + connect \LOGICAL_SPR \opcode_in [20:11] + connect \LOGICAL_MB \opcode_in [10:6] + connect \LOGICAL_ME \opcode_in [5:1] + connect \LOGICAL_SH \opcode_in [15:11] + connect \LOGICAL_BC \opcode_in [10:6] + connect \LOGICAL_TO \opcode_in [25:21] + connect \LOGICAL_DS \opcode_in [15:2] + connect \LOGICAL_D \opcode_in [15:0] + connect \LOGICAL_BH \opcode_in [12:11] + connect \LOGICAL_BI \opcode_in [20:16] + connect \LOGICAL_BO \opcode_in [25:21] + connect \LOGICAL_FXM \opcode_in [19:12] + connect \LOGICAL_BT \opcode_in [25:21] + connect \LOGICAL_BA \opcode_in [20:16] + connect \LOGICAL_BB \opcode_in [15:11] + connect \LOGICAL_CR \opcode_in [10:1] + connect \LOGICAL_BF \opcode_in [25:23] + connect \LOGICAL_BD \opcode_in [15:2] + connect \LOGICAL_OE \opcode_in [10] + connect \LOGICAL_Rc \opcode_in [0] + connect \LOGICAL_AA \opcode_in [1] + connect \LOGICAL_LK \opcode_in [0] + connect \LOGICAL_LI \opcode_in [25:2] + connect \LOGICAL_ME32 \opcode_in [5:1] + connect \LOGICAL_MB32 \opcode_in [10:6] + connect \LOGICAL_sh { \opcode_in [1] \opcode_in [15:11] } + connect \LOGICAL_SH32 \opcode_in [15:11] + connect \LOGICAL_L \opcode_in [21] + connect \LOGICAL_UI \opcode_in [15:0] + connect \LOGICAL_SI \opcode_in [15:0] + connect \LOGICAL_RB \opcode_in [15:11] + connect \LOGICAL_RA \opcode_in [20:16] + connect \LOGICAL_RT \opcode_in [25:21] + connect \LOGICAL_RS \opcode_in [25:21] + connect \opcode_in \$1 + connect \LOGICAL_dec31_opcode_in \opcode_in + connect \opcode_switch \opcode_in [31:26] +end +attribute \src "libresoc.v:57129.1-58434.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_SPR.dec" +attribute \generator "nMigen" +module \dec$161 + attribute \src "libresoc.v:58065.3-58074.6" + wire width 3 $0\SPR_cr_in[2:0] + attribute \src "libresoc.v:58075.3-58084.6" + wire width 3 $0\SPR_cr_out[2:0] + attribute \src "libresoc.v:58045.3-58054.6" + wire width 12 $0\SPR_function_unit[11:0] + attribute \src "libresoc.v:58055.3-58064.6" + wire width 7 $0\SPR_internal_op[6:0] + attribute \src "libresoc.v:58095.3-58104.6" + wire $0\SPR_is_32b[0:0] + attribute \src "libresoc.v:58085.3-58094.6" + wire width 2 $0\SPR_rc_sel[1:0] + attribute \src "libresoc.v:57130.7-57130.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:58065.3-58074.6" + wire width 3 $1\SPR_cr_in[2:0] + attribute \src "libresoc.v:58075.3-58084.6" + wire width 3 $1\SPR_cr_out[2:0] + attribute \src "libresoc.v:58045.3-58054.6" + wire width 12 $1\SPR_function_unit[11:0] + attribute \src "libresoc.v:58055.3-58064.6" + wire width 7 $1\SPR_internal_op[6:0] + attribute \src "libresoc.v:58095.3-58104.6" + wire $1\SPR_is_32b[0:0] + attribute \src "libresoc.v:58085.3-58094.6" + wire width 2 $1\SPR_rc_sel[1:0] + attribute \src "libresoc.v:58035.17-58035.211" + wire width 32 $ternary$libresoc.v:58035$3496_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:478" + wire width 32 \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_FRC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \A_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \B_AA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 14 \B_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \B_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \B_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \B_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DQE_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DQE_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \DQE_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 12 \DQ_DQ + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \DQ_PT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DQ_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DQ_RTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DQ_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \DQ_SX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \DQ_SX_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DQ_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \DQ_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \DQ_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \DQ_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 14 \DS_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_FRSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_RSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_VRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \DS_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DX_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \DX_d0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 16 \DX_d0_d1_d2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DX_d1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \DX_d2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \D_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 16 \D_D + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \D_FRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \D_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \D_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \D_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \D_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \D_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 16 \D_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \D_TO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 16 \D_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \EVS_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \I_AA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 24 \I_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \I_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MDS_IB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MDS_IS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MDS_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MDS_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MDS_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \MDS_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \MDS_XBI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \MDS_XBI_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \MDS_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \MDS_mb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \MDS_me + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MD_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MD_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \MD_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \MD_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \MD_mb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \MD_me + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \MD_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \M_MB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \M_ME + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \M_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \M_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \M_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \M_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \M_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 7 \SC_LEV + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \SC_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \SC_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire \SPR_AA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 output 12 \SPR_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 output 11 \SPR_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 output 16 \SPR_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 14 \SPR_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 3 \SPR_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 2 \SPR_BH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 output 15 \SPR_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \SPR_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 output 13 \SPR_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 10 \SPR_CR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 16 \SPR_D + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 14 \SPR_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 8 output 14 \SPR_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire \SPR_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 24 \SPR_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire \SPR_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \SPR_MB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \SPR_MB32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \SPR_ME + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \SPR_ME32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire output 10 \SPR_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \SPR_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \SPR_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \SPR_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \SPR_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire output 9 \SPR_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \SPR_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \SPR_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 16 \SPR_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 10 \SPR_SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \SPR_TO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 16 \SPR_UI + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 4 \SPR_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \SPR_cr_out + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \SPR_dec31_SPR_dec31_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \SPR_dec31_SPR_dec31_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \SPR_dec31_SPR_dec31_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 \SPR_dec31_SPR_dec31_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \SPR_dec31_SPR_dec31_is_32b + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \SPR_dec31_SPR_dec31_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \SPR_dec31_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 7 \SPR_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 6 \SPR_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 8 \SPR_is_32b + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 3 \SPR_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 6 \SPR_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \TX_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \TX_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \TX_XBI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \TX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_RC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \VA_SHB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_VRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_VRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_VRC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \VA_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \VC_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VC_VRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VC_VRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VC_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \VC_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_EO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \VX_PS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_SIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_UIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \VX_UIM_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \VX_UIM_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \VX_UIM_3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_VRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_VRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \VX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 11 \VX_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 8 \XFL_FLM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XFL_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XFL_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XFL_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XFL_W + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \XFL_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \XFX_BHRBE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XFX_DUI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \XFX_DUIS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 8 \XFX_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XFX_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XFX_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \XFX_SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \XFX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XL_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XL_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \XL_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \XL_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \XL_BH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XL_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XL_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XL_BO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 output 19 \XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XL_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 15 \XL_OC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XL_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \XL_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XO_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XO_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XO_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XO_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XO_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 9 \XO_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XS_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XS_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XS_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 9 \XS_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XS_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX2_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \XX2_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX2_BX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX2_BX_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 7 \XX2_DCMX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX2_EO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX2_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX2_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX2_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX2_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \XX2_UIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \XX2_UIM_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 7 \XX2_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 9 \XX2_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX2_dc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 7 \XX2_dc_dm_dx + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX2_dm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX2_dx + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX3_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX3_AX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX3_AX_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX3_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \XX3_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX3_BX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX3_BX_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \XX3_DM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX3_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \XX3_SHW + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX3_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX3_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX3_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \XX3_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 8 \XX3_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 9 \XX3_XO_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX4_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX4_AX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX4_AX_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX4_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX4_BX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX4_BX_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX4_C + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX4_CX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX4_CX_C + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX4_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX4_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX4_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \XX4_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 output 17 \X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 output 18 \X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \X_CT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 7 \X_DCMX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \X_DRM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_E + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \X_EO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_EO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_EX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \X_E_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRAp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRBp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \X_IH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 8 \X_IMM8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_L1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \X_L2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \X_L3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_MO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_NB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_PRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_R + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \X_RIC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \X_RM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_RO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_RSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_RTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_R_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \X_SP + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \X_SR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_SX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \X_SX_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \X_TBR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_TH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_TO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \X_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \X_U + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_UIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_VRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_W + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \X_WC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \X_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 8 \X_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \Z22_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \Z22_DCM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \Z22_DGM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z22_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z22_FRAp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z22_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z22_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \Z22_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \Z22_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 9 \Z22_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_FRAp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_FRBp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \Z23_R + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \Z23_RMC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \Z23_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_TE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 8 \Z23_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \all_OPCD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \all_PO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + wire input 1 \bigendian + attribute \src "libresoc.v:57130.7-57130.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 output 2 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 6 \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:442" + wire width 32 input 20 \raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:478" + cell $mux $ternary$libresoc.v:58035$3496 + parameter \WIDTH 32 + connect \A \raw_opcode_in + connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } + connect \S \bigendian + connect \Y $ternary$libresoc.v:58035$3496_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:58036.13-58044.4" + cell \SPR_dec31 \SPR_dec31 + connect \SPR_dec31_cr_in \SPR_dec31_SPR_dec31_cr_in + connect \SPR_dec31_cr_out \SPR_dec31_SPR_dec31_cr_out + connect \SPR_dec31_function_unit \SPR_dec31_SPR_dec31_function_unit + connect \SPR_dec31_internal_op \SPR_dec31_SPR_dec31_internal_op + connect \SPR_dec31_is_32b \SPR_dec31_SPR_dec31_is_32b + connect \SPR_dec31_rc_sel \SPR_dec31_SPR_dec31_rc_sel + connect \opcode_in \SPR_dec31_opcode_in + end + attribute \src "libresoc.v:57130.7-57130.20" + process $proc$libresoc.v:57130$3503 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:58045.3-58054.6" + process $proc$libresoc.v:58045$3497 + assign { } { } + assign { } { } + assign $0\SPR_function_unit[11:0] $1\SPR_function_unit[11:0] + attribute \src "libresoc.v:58046.5-58046.29" + switch \initial + attribute \src "libresoc.v:58046.9-58046.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\SPR_function_unit[11:0] \SPR_dec31_SPR_dec31_function_unit + case + assign $1\SPR_function_unit[11:0] 12'000000000000 + end + sync always + update \SPR_function_unit $0\SPR_function_unit[11:0] + end + attribute \src "libresoc.v:58055.3-58064.6" + process $proc$libresoc.v:58055$3498 + assign { } { } + assign { } { } + assign $0\SPR_internal_op[6:0] $1\SPR_internal_op[6:0] + attribute \src "libresoc.v:58056.5-58056.29" + switch \initial + attribute \src "libresoc.v:58056.9-58056.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\SPR_internal_op[6:0] \SPR_dec31_SPR_dec31_internal_op + case + assign $1\SPR_internal_op[6:0] 7'0000000 + end + sync always + update \SPR_internal_op $0\SPR_internal_op[6:0] + end + attribute \src "libresoc.v:58065.3-58074.6" + process $proc$libresoc.v:58065$3499 + assign { } { } + assign { } { } + assign $0\SPR_cr_in[2:0] $1\SPR_cr_in[2:0] + attribute \src "libresoc.v:58066.5-58066.29" + switch \initial + attribute \src "libresoc.v:58066.9-58066.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\SPR_cr_in[2:0] \SPR_dec31_SPR_dec31_cr_in + case + assign $1\SPR_cr_in[2:0] 3'000 + end + sync always + update \SPR_cr_in $0\SPR_cr_in[2:0] + end + attribute \src "libresoc.v:58075.3-58084.6" + process $proc$libresoc.v:58075$3500 + assign { } { } + assign { } { } + assign $0\SPR_cr_out[2:0] $1\SPR_cr_out[2:0] + attribute \src "libresoc.v:58076.5-58076.29" + switch \initial + attribute \src "libresoc.v:58076.9-58076.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\SPR_cr_out[2:0] \SPR_dec31_SPR_dec31_cr_out + case + assign $1\SPR_cr_out[2:0] 3'000 + end + sync always + update \SPR_cr_out $0\SPR_cr_out[2:0] + end + attribute \src "libresoc.v:58085.3-58094.6" + process $proc$libresoc.v:58085$3501 + assign { } { } + assign { } { } + assign $0\SPR_rc_sel[1:0] $1\SPR_rc_sel[1:0] + attribute \src "libresoc.v:58086.5-58086.29" + switch \initial + attribute \src "libresoc.v:58086.9-58086.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\SPR_rc_sel[1:0] \SPR_dec31_SPR_dec31_rc_sel + case + assign $1\SPR_rc_sel[1:0] 2'00 + end + sync always + update \SPR_rc_sel $0\SPR_rc_sel[1:0] + end + attribute \src "libresoc.v:58095.3-58104.6" + process $proc$libresoc.v:58095$3502 + assign { } { } + assign { } { } + assign $0\SPR_is_32b[0:0] $1\SPR_is_32b[0:0] + attribute \src "libresoc.v:58096.5-58096.29" + switch \initial + attribute \src "libresoc.v:58096.9-58096.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\SPR_is_32b[0:0] \SPR_dec31_SPR_dec31_is_32b + case + assign $1\SPR_is_32b[0:0] 1'0 + end + sync always + update \SPR_is_32b $0\SPR_is_32b[0:0] + end + connect \$1 $ternary$libresoc.v:58035$3496_Y + connect \VC_XO \opcode_in [9:0] + connect \VC_VRT \opcode_in [25:21] + connect \VC_VRB \opcode_in [15:11] + connect \VC_VRA \opcode_in [20:16] + connect \VC_Rc \opcode_in [10] + connect \XS_XO \opcode_in [10:2] + connect \XS_sh { \opcode_in [1] \opcode_in [15:11] } + connect \XS_RS \opcode_in [25:21] + connect \XS_Rc \opcode_in [0] + connect \XS_RA \opcode_in [20:16] + connect \VA_XO \opcode_in [5:0] + connect \VA_VRT \opcode_in [25:21] + connect \VA_VRC \opcode_in [10:6] + connect \VA_VRB \opcode_in [15:11] + connect \VA_VRA \opcode_in [20:16] + connect \VA_SHB \opcode_in [9:6] + connect \VA_RT \opcode_in [25:21] + connect \VA_RC \opcode_in [10:6] + connect \VA_RB \opcode_in [15:11] + connect \VA_RA \opcode_in [20:16] + connect \TX_XO \opcode_in [6:1] + connect \TX_XBI \opcode_in [10:7] + connect \TX_UI \opcode_in [15:11] + connect \TX_RA \opcode_in [20:16] + connect \DQE_XO \opcode_in [1:0] + connect \DQE_RT \opcode_in [25:21] + connect \DQE_RA \opcode_in [20:16] + connect \XO_XO \opcode_in [9:1] + connect \XO_RT \opcode_in [25:21] + connect \XO_Rc \opcode_in [0] + connect \XO_RB \opcode_in [15:11] + connect \XO_RA \opcode_in [20:16] + connect \XO_OE \opcode_in [10] + connect \all_PO \opcode_in [31:26] + connect \all_OPCD \opcode_in [31:26] + connect \MD_XO \opcode_in [4:2] + connect \MD_sh { \opcode_in [1] \opcode_in [15:11] } + connect \MD_RS \opcode_in [25:21] + connect \MD_Rc \opcode_in [0] + connect \MD_RA \opcode_in [20:16] + connect \MD_me \opcode_in [10:5] + connect \MD_mb \opcode_in [10:5] + connect \M_SH \opcode_in [15:11] + connect \M_RS \opcode_in [25:21] + connect \M_Rc \opcode_in [0] + connect \M_RB \opcode_in [15:11] + connect \M_RA \opcode_in [20:16] + connect \M_ME \opcode_in [5:1] + connect \M_MB \opcode_in [10:6] + connect \SC_XO_1 \opcode_in [1:0] + connect \SC_XO \opcode_in [1] + connect \SC_LEV \opcode_in [11:5] + connect \MDS_XO \opcode_in [4:1] + connect \MDS_XBI_1 \opcode_in [10:7] + connect \MDS_XBI \opcode_in [10:7] + connect \MDS_RS \opcode_in [25:21] + connect \MDS_Rc \opcode_in [0] + connect \MDS_RB \opcode_in [15:11] + connect \MDS_RA \opcode_in [20:16] + connect \MDS_me \opcode_in [10:5] + connect \MDS_mb \opcode_in [10:5] + connect \MDS_IS \opcode_in [25:21] + connect \MDS_IB \opcode_in [15:11] + connect \Z23_XO \opcode_in [8:1] + connect \Z23_TE \opcode_in [20:16] + connect \Z23_RMC \opcode_in [10:9] + connect \Z23_Rc \opcode_in [0] + connect \Z23_R \opcode_in [16] + connect \Z23_FRTp \opcode_in [25:21] + connect \Z23_FRT \opcode_in [25:21] + connect \Z23_FRBp \opcode_in [15:11] + connect \Z23_FRB \opcode_in [15:11] + connect \Z23_FRAp \opcode_in [20:16] + connect \Z23_FRA \opcode_in [20:16] + connect \XFL_XO \opcode_in [10:1] + connect \XFL_W \opcode_in [16] + connect \XFL_Rc \opcode_in [0] + connect \XFL_L \opcode_in [25] + connect \XFL_FRB \opcode_in [15:11] + connect \XFL_FLM \opcode_in [24:17] + connect \VX_XO_1 \opcode_in [10:0] + connect \VX_XO { \opcode_in [10] \opcode_in [8:0] } + connect \VX_VRT \opcode_in [25:21] + connect \VX_VRB \opcode_in [15:11] + connect \VX_VRA \opcode_in [20:16] + connect \VX_UIM_3 \opcode_in [17:16] + connect \VX_UIM_2 \opcode_in [18:16] + connect \VX_UIM_1 \opcode_in [19:16] + connect \VX_UIM \opcode_in [20:16] + connect \VX_SIM \opcode_in [20:16] + connect \VX_RT \opcode_in [25:21] + connect \VX_RA \opcode_in [20:16] + connect \VX_PS \opcode_in [9] + connect \VX_EO \opcode_in [20:16] + connect \DS_XO \opcode_in [1:0] + connect \DS_VRT \opcode_in [25:21] + connect \DS_VRS \opcode_in [25:21] + connect \DS_RT \opcode_in [25:21] + connect \DS_RSp \opcode_in [25:21] + connect \DS_RS \opcode_in [25:21] + connect \DS_RA \opcode_in [20:16] + connect \DS_FRTp \opcode_in [25:21] + connect \DS_FRSp \opcode_in [25:21] + connect \DS_DS \opcode_in [15:2] + connect \DQ_XO \opcode_in [2:0] + connect \DQ_TX_T { \opcode_in [3] \opcode_in [25:21] } + connect \DQ_T \opcode_in [25:21] + connect \DQ_TX \opcode_in [3] + connect \DQ_SX_S { \opcode_in [3] \opcode_in [25:21] } + connect \DQ_S \opcode_in [25:21] + connect \DQ_SX \opcode_in [3] + connect \DQ_RTp \opcode_in [25:21] + connect \DQ_RA \opcode_in [20:16] + connect \DQ_PT \opcode_in [3:0] + connect \DQ_DQ \opcode_in [15:4] + connect \DX_XO \opcode_in [5:1] + connect \DX_RT \opcode_in [25:21] + connect \DX_d0_d1_d2 { \opcode_in [15:6] \opcode_in [20:16] \opcode_in [0] } + connect \DX_d2 \opcode_in [0] + connect \DX_d1 \opcode_in [20:16] + connect \DX_d0 \opcode_in [15:6] + connect \XFX_XO \opcode_in [10:1] + connect \XFX_SPR \opcode_in [20:11] + connect \XFX_RT \opcode_in [25:21] + connect \XFX_RS \opcode_in [25:21] + connect \XFX_FXM \opcode_in [19:12] + connect \XFX_DUIS \opcode_in [20:11] + connect \XFX_DUI \opcode_in [25:21] + connect \XFX_BHRBE \opcode_in [20:11] + connect \EVS_BFA \opcode_in [2:0] + connect \Z22_XO \opcode_in [9:1] + connect \Z22_SH \opcode_in [15:10] + connect \Z22_Rc \opcode_in [0] + connect \Z22_FRTp \opcode_in [25:21] + connect \Z22_FRT \opcode_in [25:21] + connect \Z22_FRAp \opcode_in [20:16] + connect \Z22_FRA \opcode_in [20:16] + connect \Z22_DGM \opcode_in [15:10] + connect \Z22_DCM \opcode_in [15:10] + connect \Z22_BF \opcode_in [25:23] + connect \XX2_XO_1 \opcode_in [10:2] + connect \XX2_XO { \opcode_in [10:7] \opcode_in [5:3] } + connect \XX2_UIM_1 \opcode_in [17:16] + connect \XX2_UIM \opcode_in [19:16] + connect \XX2_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX2_T \opcode_in [25:21] + connect \XX2_TX \opcode_in [0] + connect \XX2_RT \opcode_in [25:21] + connect \XX2_EO \opcode_in [20:16] + connect \XX2_DCMX \opcode_in [22:16] + connect \XX2_dc_dm_dx { \opcode_in [6] \opcode_in [2] \opcode_in [20:16] } + connect \XX2_dx \opcode_in [20:16] + connect \XX2_dm \opcode_in [2] + connect \XX2_dc \opcode_in [6] + connect \XX2_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX2_B \opcode_in [15:11] + connect \XX2_BX \opcode_in [1] + connect \XX2_BF \opcode_in [25:23] + connect \D_UI \opcode_in [15:0] + connect \D_TO \opcode_in [25:21] + connect \D_SI \opcode_in [15:0] + connect \D_RT \opcode_in [25:21] + connect \D_RS \opcode_in [25:21] + connect \D_RA \opcode_in [20:16] + connect \D_L \opcode_in [21] + connect \D_FRT \opcode_in [25:21] + connect \D_FRS \opcode_in [25:21] + connect \D_D \opcode_in [15:0] + connect \D_BF \opcode_in [25:23] + connect \A_XO \opcode_in [5:1] + connect \A_RT \opcode_in [25:21] + connect \A_Rc \opcode_in [0] + connect \A_RB \opcode_in [15:11] + connect \A_RA \opcode_in [20:16] + connect \A_FRT \opcode_in [25:21] + connect \A_FRC \opcode_in [10:6] + connect \A_FRB \opcode_in [15:11] + connect \A_FRA \opcode_in [20:16] + connect \A_BC \opcode_in [10:6] + connect \XL_XO \opcode_in [10:1] + connect \XL_S \opcode_in [11] + connect \XL_OC \opcode_in [25:11] + connect \XL_LK \opcode_in [0] + connect \XL_BT \opcode_in [25:21] + connect \XL_BO_1 \opcode_in [25:21] + connect \XL_BO \opcode_in [25:21] + connect \XL_BI \opcode_in [20:16] + connect \XL_BH \opcode_in [12:11] + connect \XL_BFA \opcode_in [20:18] + connect \XL_BF \opcode_in [25:23] + connect \XL_BB \opcode_in [15:11] + connect \XL_BA \opcode_in [20:16] + connect \XX4_XO \opcode_in [5:4] + connect \XX4_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX4_T \opcode_in [25:21] + connect \XX4_TX \opcode_in [0] + connect \XX4_CX_C { \opcode_in [3] \opcode_in [10:6] } + connect \XX4_C \opcode_in [10:6] + connect \XX4_CX \opcode_in [3] + connect \XX4_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX4_B \opcode_in [15:11] + connect \XX4_BX \opcode_in [1] + connect \XX4_AX_A { \opcode_in [2] \opcode_in [20:16] } + connect \XX4_A \opcode_in [20:16] + connect \XX4_AX \opcode_in [2] + connect \XX3_XO_2 \opcode_in [9:1] + connect \XX3_XO_1 \opcode_in [10:3] + connect \XX3_XO \opcode_in [10:7] + connect \XX3_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX3_T \opcode_in [25:21] + connect \XX3_TX \opcode_in [0] + connect \XX3_SHW \opcode_in [9:8] + connect \XX3_Rc \opcode_in [10] + connect \XX3_DM \opcode_in [9:8] + connect \XX3_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX3_B \opcode_in [15:11] + connect \XX3_BX \opcode_in [1] + connect \XX3_BF \opcode_in [25:23] + connect \XX3_AX_A { \opcode_in [2] \opcode_in [20:16] } + connect \XX3_A \opcode_in [20:16] + connect \XX3_AX \opcode_in [2] + connect \I_LK \opcode_in [0] + connect \I_LI \opcode_in [25:2] + connect \I_AA \opcode_in [1] + connect \B_LK \opcode_in [0] + connect \B_BO \opcode_in [25:21] + connect \B_BI \opcode_in [20:16] + connect \B_BD \opcode_in [15:2] + connect \B_AA \opcode_in [1] + connect \X_XO_1 \opcode_in [8:1] + connect \X_XO \opcode_in [10:1] + connect \X_WC \opcode_in [22:21] + connect \X_W \opcode_in [16] + connect \X_VRT \opcode_in [25:21] + connect \X_VRS \opcode_in [25:21] + connect \X_UIM \opcode_in [20:16] + connect \X_U \opcode_in [15:12] + connect \X_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \X_TX \opcode_in [0] + connect \X_TO \opcode_in [25:21] + connect \X_TH \opcode_in [25:21] + connect \X_TBR \opcode_in [20:11] + connect \X_T \opcode_in [25:21] + connect \X_SX_S { \opcode_in [0] \opcode_in [25:21] } + connect \X_SX \opcode_in [0] + connect \X_SR \opcode_in [19:16] + connect \X_SP \opcode_in [20:19] + connect \X_SI \opcode_in [15:11] + connect \X_SH \opcode_in [15:11] + connect \X_S \opcode_in [25:21] + connect \X_RTp \opcode_in [25:21] + connect \X_RT \opcode_in [25:21] + connect \X_RSp \opcode_in [25:21] + connect \X_RS \opcode_in [25:21] + connect \X_RO \opcode_in [0] + connect \X_RM \opcode_in [12:11] + connect \X_RIC \opcode_in [19:18] + connect \X_Rc \opcode_in [0] + connect \X_RB \opcode_in [15:11] + connect \X_RA \opcode_in [20:16] + connect \X_R_1 \opcode_in [16] + connect \X_R \opcode_in [21] + connect \X_PRS \opcode_in [17] + connect \X_NB \opcode_in [15:11] + connect \X_MO \opcode_in [25:21] + connect \X_L3 \opcode_in [17:16] + connect \X_L1 \opcode_in [16] + connect \X_L \opcode_in [21] + connect \X_L2 \opcode_in [22:21] + connect \X_IMM8 \opcode_in [18:11] + connect \X_IH \opcode_in [23:21] + connect \X_FRTp \opcode_in [25:21] + connect \X_FRT \opcode_in [25:21] + connect \X_FRSp \opcode_in [25:21] + connect \X_FRS \opcode_in [25:21] + connect \X_FRBp \opcode_in [15:11] + connect \X_FRB \opcode_in [15:11] + connect \X_FRAp \opcode_in [20:16] + connect \X_FRA \opcode_in [20:16] + connect \X_FC \opcode_in [15:11] + connect \X_EX \opcode_in [0] + connect \X_EO_1 \opcode_in [20:16] + connect \X_EO \opcode_in [20:19] + connect \X_E_1 \opcode_in [19:16] + connect \X_E \opcode_in [15] + connect \X_DRM \opcode_in [13:11] + connect \X_DCMX \opcode_in [22:16] + connect \X_CT \opcode_in [24:21] + connect \X_BO \opcode_in [25:21] + connect \X_BFA \opcode_in [20:18] + connect \X_BF \opcode_in [25:23] + connect \X_A \opcode_in [25] + connect \SPR_SPR \opcode_in [20:11] + connect \SPR_MB \opcode_in [10:6] + connect \SPR_ME \opcode_in [5:1] + connect \SPR_SH \opcode_in [15:11] + connect \SPR_BC \opcode_in [10:6] + connect \SPR_TO \opcode_in [25:21] + connect \SPR_DS \opcode_in [15:2] + connect \SPR_D \opcode_in [15:0] + connect \SPR_BH \opcode_in [12:11] + connect \SPR_BI \opcode_in [20:16] + connect \SPR_BO \opcode_in [25:21] + connect \SPR_FXM \opcode_in [19:12] + connect \SPR_BT \opcode_in [25:21] + connect \SPR_BA \opcode_in [20:16] + connect \SPR_BB \opcode_in [15:11] + connect \SPR_CR \opcode_in [10:1] + connect \SPR_BF \opcode_in [25:23] + connect \SPR_BD \opcode_in [15:2] + connect \SPR_OE \opcode_in [10] + connect \SPR_Rc \opcode_in [0] + connect \SPR_AA \opcode_in [1] + connect \SPR_LK \opcode_in [0] + connect \SPR_LI \opcode_in [25:2] + connect \SPR_ME32 \opcode_in [5:1] + connect \SPR_MB32 \opcode_in [10:6] + connect \SPR_sh { \opcode_in [1] \opcode_in [15:11] } + connect \SPR_SH32 \opcode_in [15:11] + connect \SPR_L \opcode_in [21] + connect \SPR_UI \opcode_in [15:0] + connect \SPR_SI \opcode_in [15:0] + connect \SPR_RB \opcode_in [15:11] + connect \SPR_RA \opcode_in [20:16] + connect \SPR_RT \opcode_in [25:21] + connect \SPR_RS \opcode_in [25:21] + connect \opcode_in \$1 + connect \SPR_dec31_opcode_in \opcode_in + connect \opcode_switch \opcode_in [31:26] +end +attribute \src "libresoc.v:58438.1-59933.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_DIV.dec" +attribute \generator "nMigen" +module \dec$168 + attribute \src "libresoc.v:59564.3-59573.6" + wire width 3 $0\DIV_cr_in[2:0] + attribute \src "libresoc.v:59574.3-59583.6" + wire width 3 $0\DIV_cr_out[2:0] + attribute \src "libresoc.v:59464.3-59473.6" + wire width 2 $0\DIV_cry_in[1:0] + attribute \src "libresoc.v:59494.3-59503.6" + wire $0\DIV_cry_out[0:0] + attribute \src "libresoc.v:59524.3-59533.6" + wire width 12 $0\DIV_function_unit[11:0] + attribute \src "libresoc.v:59544.3-59553.6" + wire width 3 $0\DIV_in1_sel[2:0] + attribute \src "libresoc.v:59554.3-59563.6" + wire width 4 $0\DIV_in2_sel[3:0] + attribute \src "libresoc.v:59534.3-59543.6" + wire width 7 $0\DIV_internal_op[6:0] + attribute \src "libresoc.v:59474.3-59483.6" + wire $0\DIV_inv_a[0:0] + attribute \src "libresoc.v:59484.3-59493.6" + wire $0\DIV_inv_out[0:0] + attribute \src "libresoc.v:59504.3-59513.6" + wire $0\DIV_is_32b[0:0] + attribute \src "libresoc.v:59584.3-59593.6" + wire width 4 $0\DIV_ldst_len[3:0] + attribute \src "libresoc.v:59594.3-59603.6" + wire width 2 $0\DIV_rc_sel[1:0] + attribute \src "libresoc.v:59514.3-59523.6" + wire $0\DIV_sgn[0:0] + attribute \src "libresoc.v:58439.7-58439.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:59564.3-59573.6" + wire width 3 $1\DIV_cr_in[2:0] + attribute \src "libresoc.v:59574.3-59583.6" + wire width 3 $1\DIV_cr_out[2:0] + attribute \src "libresoc.v:59464.3-59473.6" + wire width 2 $1\DIV_cry_in[1:0] + attribute \src "libresoc.v:59494.3-59503.6" + wire $1\DIV_cry_out[0:0] + attribute \src "libresoc.v:59524.3-59533.6" + wire width 12 $1\DIV_function_unit[11:0] + attribute \src "libresoc.v:59544.3-59553.6" + wire width 3 $1\DIV_in1_sel[2:0] + attribute \src "libresoc.v:59554.3-59563.6" + wire width 4 $1\DIV_in2_sel[3:0] + attribute \src "libresoc.v:59534.3-59543.6" + wire width 7 $1\DIV_internal_op[6:0] + attribute \src "libresoc.v:59474.3-59483.6" + wire $1\DIV_inv_a[0:0] + attribute \src "libresoc.v:59484.3-59493.6" + wire $1\DIV_inv_out[0:0] + attribute \src "libresoc.v:59504.3-59513.6" + wire $1\DIV_is_32b[0:0] + attribute \src "libresoc.v:59584.3-59593.6" + wire width 4 $1\DIV_ldst_len[3:0] + attribute \src "libresoc.v:59594.3-59603.6" + wire width 2 $1\DIV_rc_sel[1:0] + attribute \src "libresoc.v:59514.3-59523.6" + wire $1\DIV_sgn[0:0] + attribute \src "libresoc.v:59446.17-59446.211" + wire width 32 $ternary$libresoc.v:59446$3504_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:478" + wire width 32 \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_FRC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \A_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \B_AA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 14 \B_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \B_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \B_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \B_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire \DIV_AA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 output 27 \DIV_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 output 26 \DIV_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 output 32 \DIV_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 14 output 25 \DIV_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 3 \DIV_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 2 \DIV_BH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 output 30 \DIV_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \DIV_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 output 28 \DIV_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 10 \DIV_CR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 16 \DIV_D + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 14 output 31 \DIV_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 8 output 29 \DIV_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire \DIV_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 24 output 22 \DIV_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire \DIV_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \DIV_MB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \DIV_MB32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \DIV_ME + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \DIV_ME32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire output 24 \DIV_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 output 17 \DIV_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \DIV_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \DIV_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \DIV_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire output 23 \DIV_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \DIV_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 output 20 \DIV_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 16 output 18 \DIV_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 10 \DIV_SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \DIV_TO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 16 output 19 \DIV_UI + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 4 \DIV_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \DIV_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 13 \DIV_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 14 \DIV_cry_out + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \DIV_dec31_DIV_dec31_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \DIV_dec31_DIV_dec31_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \DIV_dec31_DIV_dec31_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \DIV_dec31_DIV_dec31_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \DIV_dec31_DIV_dec31_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \DIV_dec31_DIV_dec31_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \DIV_dec31_DIV_dec31_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 \DIV_dec31_DIV_dec31_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \DIV_dec31_DIV_dec31_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \DIV_dec31_DIV_dec31_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \DIV_dec31_DIV_dec31_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \DIV_dec31_DIV_dec31_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \DIV_dec31_DIV_dec31_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \DIV_dec31_DIV_dec31_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \DIV_dec31_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 7 \DIV_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 8 \DIV_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 9 \DIV_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 6 \DIV_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 11 \DIV_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 12 \DIV_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 15 \DIV_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 10 \DIV_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 3 \DIV_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 16 \DIV_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 6 output 21 \DIV_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DQE_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DQE_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \DQE_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 12 \DQ_DQ + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \DQ_PT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DQ_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DQ_RTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DQ_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \DQ_SX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \DQ_SX_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DQ_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \DQ_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \DQ_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \DQ_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 14 \DS_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_FRSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_RSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_VRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \DS_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DX_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \DX_d0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 16 \DX_d0_d1_d2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DX_d1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \DX_d2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \D_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 16 \D_D + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \D_FRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \D_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \D_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \D_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \D_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \D_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 16 \D_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \D_TO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 16 \D_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \EVS_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \I_AA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 24 \I_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \I_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MDS_IB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MDS_IS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MDS_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MDS_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MDS_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \MDS_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \MDS_XBI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \MDS_XBI_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \MDS_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \MDS_mb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \MDS_me + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MD_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MD_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \MD_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \MD_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \MD_mb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \MD_me + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \MD_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \M_MB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \M_ME + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \M_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \M_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \M_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \M_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \M_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 7 \SC_LEV + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \SC_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \SC_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \TX_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \TX_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \TX_XBI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \TX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_RC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \VA_SHB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_VRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_VRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_VRC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \VA_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \VC_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VC_VRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VC_VRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VC_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \VC_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_EO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \VX_PS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_SIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_UIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \VX_UIM_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \VX_UIM_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \VX_UIM_3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_VRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_VRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \VX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 11 \VX_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 8 \XFL_FLM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XFL_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XFL_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XFL_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XFL_W + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \XFL_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \XFX_BHRBE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XFX_DUI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \XFX_DUIS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 8 \XFX_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XFX_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XFX_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \XFX_SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \XFX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XL_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XL_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \XL_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \XL_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \XL_BH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XL_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XL_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XL_BO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 output 35 \XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XL_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 15 \XL_OC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XL_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \XL_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XO_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XO_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XO_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XO_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XO_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 9 \XO_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XS_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XS_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XS_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 9 \XS_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XS_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX2_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \XX2_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX2_BX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX2_BX_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 7 \XX2_DCMX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX2_EO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX2_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX2_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX2_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX2_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \XX2_UIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \XX2_UIM_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 7 \XX2_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 9 \XX2_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX2_dc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 7 \XX2_dc_dm_dx + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX2_dm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX2_dx + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX3_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX3_AX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX3_AX_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX3_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \XX3_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX3_BX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX3_BX_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \XX3_DM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX3_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \XX3_SHW + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX3_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX3_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX3_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \XX3_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 8 \XX3_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 9 \XX3_XO_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX4_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX4_AX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX4_AX_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX4_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX4_BX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX4_BX_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX4_C + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX4_CX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX4_CX_C + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX4_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX4_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX4_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \XX4_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 output 33 \X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 output 34 \X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \X_CT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 7 \X_DCMX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \X_DRM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_E + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \X_EO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_EO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_EX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \X_E_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRAp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRBp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \X_IH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 8 \X_IMM8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_L1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \X_L2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \X_L3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_MO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_NB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_PRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_R + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \X_RIC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \X_RM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_RO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_RSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_RTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_R_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \X_SP + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \X_SR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_SX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \X_SX_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \X_TBR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_TH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_TO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \X_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \X_U + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_UIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_VRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_W + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \X_WC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \X_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 8 \X_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \Z22_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \Z22_DCM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \Z22_DGM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z22_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z22_FRAp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z22_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z22_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \Z22_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \Z22_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 9 \Z22_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_FRAp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_FRBp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \Z23_R + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \Z23_RMC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \Z23_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_TE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 8 \Z23_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \all_OPCD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \all_PO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + wire input 1 \bigendian + attribute \src "libresoc.v:58439.7-58439.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 output 2 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 6 \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:442" + wire width 32 input 36 \raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:478" + cell $mux $ternary$libresoc.v:59446$3504 + parameter \WIDTH 32 + connect \A \raw_opcode_in + connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } + connect \S \bigendian + connect \Y $ternary$libresoc.v:59446$3504_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:59447.13-59463.4" + cell \DIV_dec31 \DIV_dec31 + connect \DIV_dec31_cr_in \DIV_dec31_DIV_dec31_cr_in + connect \DIV_dec31_cr_out \DIV_dec31_DIV_dec31_cr_out + connect \DIV_dec31_cry_in \DIV_dec31_DIV_dec31_cry_in + connect \DIV_dec31_cry_out \DIV_dec31_DIV_dec31_cry_out + connect \DIV_dec31_function_unit \DIV_dec31_DIV_dec31_function_unit + connect \DIV_dec31_in1_sel \DIV_dec31_DIV_dec31_in1_sel + connect \DIV_dec31_in2_sel \DIV_dec31_DIV_dec31_in2_sel + connect \DIV_dec31_internal_op \DIV_dec31_DIV_dec31_internal_op + connect \DIV_dec31_inv_a \DIV_dec31_DIV_dec31_inv_a + connect \DIV_dec31_inv_out \DIV_dec31_DIV_dec31_inv_out + connect \DIV_dec31_is_32b \DIV_dec31_DIV_dec31_is_32b + connect \DIV_dec31_ldst_len \DIV_dec31_DIV_dec31_ldst_len + connect \DIV_dec31_rc_sel \DIV_dec31_DIV_dec31_rc_sel + connect \DIV_dec31_sgn \DIV_dec31_DIV_dec31_sgn + connect \opcode_in \DIV_dec31_opcode_in + end + attribute \src "libresoc.v:58439.7-58439.20" + process $proc$libresoc.v:58439$3519 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:59464.3-59473.6" + process $proc$libresoc.v:59464$3505 + assign { } { } + assign { } { } + assign $0\DIV_cry_in[1:0] $1\DIV_cry_in[1:0] + attribute \src "libresoc.v:59465.5-59465.29" + switch \initial + attribute \src "libresoc.v:59465.9-59465.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\DIV_cry_in[1:0] \DIV_dec31_DIV_dec31_cry_in + case + assign $1\DIV_cry_in[1:0] 2'00 + end + sync always + update \DIV_cry_in $0\DIV_cry_in[1:0] + end + attribute \src "libresoc.v:59474.3-59483.6" + process $proc$libresoc.v:59474$3506 + assign { } { } + assign { } { } + assign $0\DIV_inv_a[0:0] $1\DIV_inv_a[0:0] + attribute \src "libresoc.v:59475.5-59475.29" + switch \initial + attribute \src "libresoc.v:59475.9-59475.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\DIV_inv_a[0:0] \DIV_dec31_DIV_dec31_inv_a + case + assign $1\DIV_inv_a[0:0] 1'0 + end + sync always + update \DIV_inv_a $0\DIV_inv_a[0:0] + end + attribute \src "libresoc.v:59484.3-59493.6" + process $proc$libresoc.v:59484$3507 + assign { } { } + assign { } { } + assign $0\DIV_inv_out[0:0] $1\DIV_inv_out[0:0] + attribute \src "libresoc.v:59485.5-59485.29" + switch \initial + attribute \src "libresoc.v:59485.9-59485.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\DIV_inv_out[0:0] \DIV_dec31_DIV_dec31_inv_out + case + assign $1\DIV_inv_out[0:0] 1'0 + end + sync always + update \DIV_inv_out $0\DIV_inv_out[0:0] + end + attribute \src "libresoc.v:59494.3-59503.6" + process $proc$libresoc.v:59494$3508 + assign { } { } + assign { } { } + assign $0\DIV_cry_out[0:0] $1\DIV_cry_out[0:0] + attribute \src "libresoc.v:59495.5-59495.29" + switch \initial + attribute \src "libresoc.v:59495.9-59495.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\DIV_cry_out[0:0] \DIV_dec31_DIV_dec31_cry_out + case + assign $1\DIV_cry_out[0:0] 1'0 + end + sync always + update \DIV_cry_out $0\DIV_cry_out[0:0] + end + attribute \src "libresoc.v:59504.3-59513.6" + process $proc$libresoc.v:59504$3509 + assign { } { } + assign { } { } + assign $0\DIV_is_32b[0:0] $1\DIV_is_32b[0:0] + attribute \src "libresoc.v:59505.5-59505.29" + switch \initial + attribute \src "libresoc.v:59505.9-59505.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\DIV_is_32b[0:0] \DIV_dec31_DIV_dec31_is_32b + case + assign $1\DIV_is_32b[0:0] 1'0 + end + sync always + update \DIV_is_32b $0\DIV_is_32b[0:0] + end + attribute \src "libresoc.v:59514.3-59523.6" + process $proc$libresoc.v:59514$3510 + assign { } { } + assign { } { } + assign $0\DIV_sgn[0:0] $1\DIV_sgn[0:0] + attribute \src "libresoc.v:59515.5-59515.29" + switch \initial + attribute \src "libresoc.v:59515.9-59515.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\DIV_sgn[0:0] \DIV_dec31_DIV_dec31_sgn + case + assign $1\DIV_sgn[0:0] 1'0 + end + sync always + update \DIV_sgn $0\DIV_sgn[0:0] + end + attribute \src "libresoc.v:59524.3-59533.6" + process $proc$libresoc.v:59524$3511 + assign { } { } + assign { } { } + assign $0\DIV_function_unit[11:0] $1\DIV_function_unit[11:0] + attribute \src "libresoc.v:59525.5-59525.29" + switch \initial + attribute \src "libresoc.v:59525.9-59525.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\DIV_function_unit[11:0] \DIV_dec31_DIV_dec31_function_unit + case + assign $1\DIV_function_unit[11:0] 12'000000000000 + end + sync always + update \DIV_function_unit $0\DIV_function_unit[11:0] + end + attribute \src "libresoc.v:59534.3-59543.6" + process $proc$libresoc.v:59534$3512 + assign { } { } + assign { } { } + assign $0\DIV_internal_op[6:0] $1\DIV_internal_op[6:0] + attribute \src "libresoc.v:59535.5-59535.29" + switch \initial + attribute \src "libresoc.v:59535.9-59535.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\DIV_internal_op[6:0] \DIV_dec31_DIV_dec31_internal_op + case + assign $1\DIV_internal_op[6:0] 7'0000000 + end + sync always + update \DIV_internal_op $0\DIV_internal_op[6:0] + end + attribute \src "libresoc.v:59544.3-59553.6" + process $proc$libresoc.v:59544$3513 + assign { } { } + assign { } { } + assign $0\DIV_in1_sel[2:0] $1\DIV_in1_sel[2:0] + attribute \src "libresoc.v:59545.5-59545.29" + switch \initial + attribute \src "libresoc.v:59545.9-59545.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\DIV_in1_sel[2:0] \DIV_dec31_DIV_dec31_in1_sel + case + assign $1\DIV_in1_sel[2:0] 3'000 + end + sync always + update \DIV_in1_sel $0\DIV_in1_sel[2:0] + end + attribute \src "libresoc.v:59554.3-59563.6" + process $proc$libresoc.v:59554$3514 + assign { } { } + assign { } { } + assign $0\DIV_in2_sel[3:0] $1\DIV_in2_sel[3:0] + attribute \src "libresoc.v:59555.5-59555.29" + switch \initial + attribute \src "libresoc.v:59555.9-59555.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\DIV_in2_sel[3:0] \DIV_dec31_DIV_dec31_in2_sel + case + assign $1\DIV_in2_sel[3:0] 4'0000 + end + sync always + update \DIV_in2_sel $0\DIV_in2_sel[3:0] + end + attribute \src "libresoc.v:59564.3-59573.6" + process $proc$libresoc.v:59564$3515 + assign { } { } + assign { } { } + assign $0\DIV_cr_in[2:0] $1\DIV_cr_in[2:0] + attribute \src "libresoc.v:59565.5-59565.29" + switch \initial + attribute \src "libresoc.v:59565.9-59565.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\DIV_cr_in[2:0] \DIV_dec31_DIV_dec31_cr_in + case + assign $1\DIV_cr_in[2:0] 3'000 + end + sync always + update \DIV_cr_in $0\DIV_cr_in[2:0] + end + attribute \src "libresoc.v:59574.3-59583.6" + process $proc$libresoc.v:59574$3516 + assign { } { } + assign { } { } + assign $0\DIV_cr_out[2:0] $1\DIV_cr_out[2:0] + attribute \src "libresoc.v:59575.5-59575.29" + switch \initial + attribute \src "libresoc.v:59575.9-59575.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\DIV_cr_out[2:0] \DIV_dec31_DIV_dec31_cr_out + case + assign $1\DIV_cr_out[2:0] 3'000 + end + sync always + update \DIV_cr_out $0\DIV_cr_out[2:0] + end + attribute \src "libresoc.v:59584.3-59593.6" + process $proc$libresoc.v:59584$3517 + assign { } { } + assign { } { } + assign $0\DIV_ldst_len[3:0] $1\DIV_ldst_len[3:0] + attribute \src "libresoc.v:59585.5-59585.29" + switch \initial + attribute \src "libresoc.v:59585.9-59585.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\DIV_ldst_len[3:0] \DIV_dec31_DIV_dec31_ldst_len + case + assign $1\DIV_ldst_len[3:0] 4'0000 + end + sync always + update \DIV_ldst_len $0\DIV_ldst_len[3:0] + end + attribute \src "libresoc.v:59594.3-59603.6" + process $proc$libresoc.v:59594$3518 + assign { } { } + assign { } { } + assign $0\DIV_rc_sel[1:0] $1\DIV_rc_sel[1:0] + attribute \src "libresoc.v:59595.5-59595.29" + switch \initial + attribute \src "libresoc.v:59595.9-59595.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\DIV_rc_sel[1:0] \DIV_dec31_DIV_dec31_rc_sel + case + assign $1\DIV_rc_sel[1:0] 2'00 + end + sync always + update \DIV_rc_sel $0\DIV_rc_sel[1:0] + end + connect \$1 $ternary$libresoc.v:59446$3504_Y + connect \VC_XO \opcode_in [9:0] + connect \VC_VRT \opcode_in [25:21] + connect \VC_VRB \opcode_in [15:11] + connect \VC_VRA \opcode_in [20:16] + connect \VC_Rc \opcode_in [10] + connect \XS_XO \opcode_in [10:2] + connect \XS_sh { \opcode_in [1] \opcode_in [15:11] } + connect \XS_RS \opcode_in [25:21] + connect \XS_Rc \opcode_in [0] + connect \XS_RA \opcode_in [20:16] + connect \VA_XO \opcode_in [5:0] + connect \VA_VRT \opcode_in [25:21] + connect \VA_VRC \opcode_in [10:6] + connect \VA_VRB \opcode_in [15:11] + connect \VA_VRA \opcode_in [20:16] + connect \VA_SHB \opcode_in [9:6] + connect \VA_RT \opcode_in [25:21] + connect \VA_RC \opcode_in [10:6] + connect \VA_RB \opcode_in [15:11] + connect \VA_RA \opcode_in [20:16] + connect \TX_XO \opcode_in [6:1] + connect \TX_XBI \opcode_in [10:7] + connect \TX_UI \opcode_in [15:11] + connect \TX_RA \opcode_in [20:16] + connect \DQE_XO \opcode_in [1:0] + connect \DQE_RT \opcode_in [25:21] + connect \DQE_RA \opcode_in [20:16] + connect \XO_XO \opcode_in [9:1] + connect \XO_RT \opcode_in [25:21] + connect \XO_Rc \opcode_in [0] + connect \XO_RB \opcode_in [15:11] + connect \XO_RA \opcode_in [20:16] + connect \XO_OE \opcode_in [10] + connect \all_PO \opcode_in [31:26] + connect \all_OPCD \opcode_in [31:26] + connect \MD_XO \opcode_in [4:2] + connect \MD_sh { \opcode_in [1] \opcode_in [15:11] } + connect \MD_RS \opcode_in [25:21] + connect \MD_Rc \opcode_in [0] + connect \MD_RA \opcode_in [20:16] + connect \MD_me \opcode_in [10:5] + connect \MD_mb \opcode_in [10:5] + connect \M_SH \opcode_in [15:11] + connect \M_RS \opcode_in [25:21] + connect \M_Rc \opcode_in [0] + connect \M_RB \opcode_in [15:11] + connect \M_RA \opcode_in [20:16] + connect \M_ME \opcode_in [5:1] + connect \M_MB \opcode_in [10:6] + connect \SC_XO_1 \opcode_in [1:0] + connect \SC_XO \opcode_in [1] + connect \SC_LEV \opcode_in [11:5] + connect \MDS_XO \opcode_in [4:1] + connect \MDS_XBI_1 \opcode_in [10:7] + connect \MDS_XBI \opcode_in [10:7] + connect \MDS_RS \opcode_in [25:21] + connect \MDS_Rc \opcode_in [0] + connect \MDS_RB \opcode_in [15:11] + connect \MDS_RA \opcode_in [20:16] + connect \MDS_me \opcode_in [10:5] + connect \MDS_mb \opcode_in [10:5] + connect \MDS_IS \opcode_in [25:21] + connect \MDS_IB \opcode_in [15:11] + connect \Z23_XO \opcode_in [8:1] + connect \Z23_TE \opcode_in [20:16] + connect \Z23_RMC \opcode_in [10:9] + connect \Z23_Rc \opcode_in [0] + connect \Z23_R \opcode_in [16] + connect \Z23_FRTp \opcode_in [25:21] + connect \Z23_FRT \opcode_in [25:21] + connect \Z23_FRBp \opcode_in [15:11] + connect \Z23_FRB \opcode_in [15:11] + connect \Z23_FRAp \opcode_in [20:16] + connect \Z23_FRA \opcode_in [20:16] + connect \XFL_XO \opcode_in [10:1] + connect \XFL_W \opcode_in [16] + connect \XFL_Rc \opcode_in [0] + connect \XFL_L \opcode_in [25] + connect \XFL_FRB \opcode_in [15:11] + connect \XFL_FLM \opcode_in [24:17] + connect \VX_XO_1 \opcode_in [10:0] + connect \VX_XO { \opcode_in [10] \opcode_in [8:0] } + connect \VX_VRT \opcode_in [25:21] + connect \VX_VRB \opcode_in [15:11] + connect \VX_VRA \opcode_in [20:16] + connect \VX_UIM_3 \opcode_in [17:16] + connect \VX_UIM_2 \opcode_in [18:16] + connect \VX_UIM_1 \opcode_in [19:16] + connect \VX_UIM \opcode_in [20:16] + connect \VX_SIM \opcode_in [20:16] + connect \VX_RT \opcode_in [25:21] + connect \VX_RA \opcode_in [20:16] + connect \VX_PS \opcode_in [9] + connect \VX_EO \opcode_in [20:16] + connect \DS_XO \opcode_in [1:0] + connect \DS_VRT \opcode_in [25:21] + connect \DS_VRS \opcode_in [25:21] + connect \DS_RT \opcode_in [25:21] + connect \DS_RSp \opcode_in [25:21] + connect \DS_RS \opcode_in [25:21] + connect \DS_RA \opcode_in [20:16] + connect \DS_FRTp \opcode_in [25:21] + connect \DS_FRSp \opcode_in [25:21] + connect \DS_DS \opcode_in [15:2] + connect \DQ_XO \opcode_in [2:0] + connect \DQ_TX_T { \opcode_in [3] \opcode_in [25:21] } + connect \DQ_T \opcode_in [25:21] + connect \DQ_TX \opcode_in [3] + connect \DQ_SX_S { \opcode_in [3] \opcode_in [25:21] } + connect \DQ_S \opcode_in [25:21] + connect \DQ_SX \opcode_in [3] + connect \DQ_RTp \opcode_in [25:21] + connect \DQ_RA \opcode_in [20:16] + connect \DQ_PT \opcode_in [3:0] + connect \DQ_DQ \opcode_in [15:4] + connect \DX_XO \opcode_in [5:1] + connect \DX_RT \opcode_in [25:21] + connect \DX_d0_d1_d2 { \opcode_in [15:6] \opcode_in [20:16] \opcode_in [0] } + connect \DX_d2 \opcode_in [0] + connect \DX_d1 \opcode_in [20:16] + connect \DX_d0 \opcode_in [15:6] + connect \XFX_XO \opcode_in [10:1] + connect \XFX_SPR \opcode_in [20:11] + connect \XFX_RT \opcode_in [25:21] + connect \XFX_RS \opcode_in [25:21] + connect \XFX_FXM \opcode_in [19:12] + connect \XFX_DUIS \opcode_in [20:11] + connect \XFX_DUI \opcode_in [25:21] + connect \XFX_BHRBE \opcode_in [20:11] + connect \EVS_BFA \opcode_in [2:0] + connect \Z22_XO \opcode_in [9:1] + connect \Z22_SH \opcode_in [15:10] + connect \Z22_Rc \opcode_in [0] + connect \Z22_FRTp \opcode_in [25:21] + connect \Z22_FRT \opcode_in [25:21] + connect \Z22_FRAp \opcode_in [20:16] + connect \Z22_FRA \opcode_in [20:16] + connect \Z22_DGM \opcode_in [15:10] + connect \Z22_DCM \opcode_in [15:10] + connect \Z22_BF \opcode_in [25:23] + connect \XX2_XO_1 \opcode_in [10:2] + connect \XX2_XO { \opcode_in [10:7] \opcode_in [5:3] } + connect \XX2_UIM_1 \opcode_in [17:16] + connect \XX2_UIM \opcode_in [19:16] + connect \XX2_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX2_T \opcode_in [25:21] + connect \XX2_TX \opcode_in [0] + connect \XX2_RT \opcode_in [25:21] + connect \XX2_EO \opcode_in [20:16] + connect \XX2_DCMX \opcode_in [22:16] + connect \XX2_dc_dm_dx { \opcode_in [6] \opcode_in [2] \opcode_in [20:16] } + connect \XX2_dx \opcode_in [20:16] + connect \XX2_dm \opcode_in [2] + connect \XX2_dc \opcode_in [6] + connect \XX2_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX2_B \opcode_in [15:11] + connect \XX2_BX \opcode_in [1] + connect \XX2_BF \opcode_in [25:23] + connect \D_UI \opcode_in [15:0] + connect \D_TO \opcode_in [25:21] + connect \D_SI \opcode_in [15:0] + connect \D_RT \opcode_in [25:21] + connect \D_RS \opcode_in [25:21] + connect \D_RA \opcode_in [20:16] + connect \D_L \opcode_in [21] + connect \D_FRT \opcode_in [25:21] + connect \D_FRS \opcode_in [25:21] + connect \D_D \opcode_in [15:0] + connect \D_BF \opcode_in [25:23] + connect \A_XO \opcode_in [5:1] + connect \A_RT \opcode_in [25:21] + connect \A_Rc \opcode_in [0] + connect \A_RB \opcode_in [15:11] + connect \A_RA \opcode_in [20:16] + connect \A_FRT \opcode_in [25:21] + connect \A_FRC \opcode_in [10:6] + connect \A_FRB \opcode_in [15:11] + connect \A_FRA \opcode_in [20:16] + connect \A_BC \opcode_in [10:6] + connect \XL_XO \opcode_in [10:1] + connect \XL_S \opcode_in [11] + connect \XL_OC \opcode_in [25:11] + connect \XL_LK \opcode_in [0] + connect \XL_BT \opcode_in [25:21] + connect \XL_BO_1 \opcode_in [25:21] + connect \XL_BO \opcode_in [25:21] + connect \XL_BI \opcode_in [20:16] + connect \XL_BH \opcode_in [12:11] + connect \XL_BFA \opcode_in [20:18] + connect \XL_BF \opcode_in [25:23] + connect \XL_BB \opcode_in [15:11] + connect \XL_BA \opcode_in [20:16] + connect \XX4_XO \opcode_in [5:4] + connect \XX4_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX4_T \opcode_in [25:21] + connect \XX4_TX \opcode_in [0] + connect \XX4_CX_C { \opcode_in [3] \opcode_in [10:6] } + connect \XX4_C \opcode_in [10:6] + connect \XX4_CX \opcode_in [3] + connect \XX4_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX4_B \opcode_in [15:11] + connect \XX4_BX \opcode_in [1] + connect \XX4_AX_A { \opcode_in [2] \opcode_in [20:16] } + connect \XX4_A \opcode_in [20:16] + connect \XX4_AX \opcode_in [2] + connect \XX3_XO_2 \opcode_in [9:1] + connect \XX3_XO_1 \opcode_in [10:3] + connect \XX3_XO \opcode_in [10:7] + connect \XX3_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX3_T \opcode_in [25:21] + connect \XX3_TX \opcode_in [0] + connect \XX3_SHW \opcode_in [9:8] + connect \XX3_Rc \opcode_in [10] + connect \XX3_DM \opcode_in [9:8] + connect \XX3_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX3_B \opcode_in [15:11] + connect \XX3_BX \opcode_in [1] + connect \XX3_BF \opcode_in [25:23] + connect \XX3_AX_A { \opcode_in [2] \opcode_in [20:16] } + connect \XX3_A \opcode_in [20:16] + connect \XX3_AX \opcode_in [2] + connect \I_LK \opcode_in [0] + connect \I_LI \opcode_in [25:2] + connect \I_AA \opcode_in [1] + connect \B_LK \opcode_in [0] + connect \B_BO \opcode_in [25:21] + connect \B_BI \opcode_in [20:16] + connect \B_BD \opcode_in [15:2] + connect \B_AA \opcode_in [1] + connect \X_XO_1 \opcode_in [8:1] + connect \X_XO \opcode_in [10:1] + connect \X_WC \opcode_in [22:21] + connect \X_W \opcode_in [16] + connect \X_VRT \opcode_in [25:21] + connect \X_VRS \opcode_in [25:21] + connect \X_UIM \opcode_in [20:16] + connect \X_U \opcode_in [15:12] + connect \X_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \X_TX \opcode_in [0] + connect \X_TO \opcode_in [25:21] + connect \X_TH \opcode_in [25:21] + connect \X_TBR \opcode_in [20:11] + connect \X_T \opcode_in [25:21] + connect \X_SX_S { \opcode_in [0] \opcode_in [25:21] } + connect \X_SX \opcode_in [0] + connect \X_SR \opcode_in [19:16] + connect \X_SP \opcode_in [20:19] + connect \X_SI \opcode_in [15:11] + connect \X_SH \opcode_in [15:11] + connect \X_S \opcode_in [25:21] + connect \X_RTp \opcode_in [25:21] + connect \X_RT \opcode_in [25:21] + connect \X_RSp \opcode_in [25:21] + connect \X_RS \opcode_in [25:21] + connect \X_RO \opcode_in [0] + connect \X_RM \opcode_in [12:11] + connect \X_RIC \opcode_in [19:18] + connect \X_Rc \opcode_in [0] + connect \X_RB \opcode_in [15:11] + connect \X_RA \opcode_in [20:16] + connect \X_R_1 \opcode_in [16] + connect \X_R \opcode_in [21] + connect \X_PRS \opcode_in [17] + connect \X_NB \opcode_in [15:11] + connect \X_MO \opcode_in [25:21] + connect \X_L3 \opcode_in [17:16] + connect \X_L1 \opcode_in [16] + connect \X_L \opcode_in [21] + connect \X_L2 \opcode_in [22:21] + connect \X_IMM8 \opcode_in [18:11] + connect \X_IH \opcode_in [23:21] + connect \X_FRTp \opcode_in [25:21] + connect \X_FRT \opcode_in [25:21] + connect \X_FRSp \opcode_in [25:21] + connect \X_FRS \opcode_in [25:21] + connect \X_FRBp \opcode_in [15:11] + connect \X_FRB \opcode_in [15:11] + connect \X_FRAp \opcode_in [20:16] + connect \X_FRA \opcode_in [20:16] + connect \X_FC \opcode_in [15:11] + connect \X_EX \opcode_in [0] + connect \X_EO_1 \opcode_in [20:16] + connect \X_EO \opcode_in [20:19] + connect \X_E_1 \opcode_in [19:16] + connect \X_E \opcode_in [15] + connect \X_DRM \opcode_in [13:11] + connect \X_DCMX \opcode_in [22:16] + connect \X_CT \opcode_in [24:21] + connect \X_BO \opcode_in [25:21] + connect \X_BFA \opcode_in [20:18] + connect \X_BF \opcode_in [25:23] + connect \X_A \opcode_in [25] + connect \DIV_SPR \opcode_in [20:11] + connect \DIV_MB \opcode_in [10:6] + connect \DIV_ME \opcode_in [5:1] + connect \DIV_SH \opcode_in [15:11] + connect \DIV_BC \opcode_in [10:6] + connect \DIV_TO \opcode_in [25:21] + connect \DIV_DS \opcode_in [15:2] + connect \DIV_D \opcode_in [15:0] + connect \DIV_BH \opcode_in [12:11] + connect \DIV_BI \opcode_in [20:16] + connect \DIV_BO \opcode_in [25:21] + connect \DIV_FXM \opcode_in [19:12] + connect \DIV_BT \opcode_in [25:21] + connect \DIV_BA \opcode_in [20:16] + connect \DIV_BB \opcode_in [15:11] + connect \DIV_CR \opcode_in [10:1] + connect \DIV_BF \opcode_in [25:23] + connect \DIV_BD \opcode_in [15:2] + connect \DIV_OE \opcode_in [10] + connect \DIV_Rc \opcode_in [0] + connect \DIV_AA \opcode_in [1] + connect \DIV_LK \opcode_in [0] + connect \DIV_LI \opcode_in [25:2] + connect \DIV_ME32 \opcode_in [5:1] + connect \DIV_MB32 \opcode_in [10:6] + connect \DIV_sh { \opcode_in [1] \opcode_in [15:11] } + connect \DIV_SH32 \opcode_in [15:11] + connect \DIV_L \opcode_in [21] + connect \DIV_UI \opcode_in [15:0] + connect \DIV_SI \opcode_in [15:0] + connect \DIV_RB \opcode_in [15:11] + connect \DIV_RA \opcode_in [20:16] + connect \DIV_RT \opcode_in [25:21] + connect \DIV_RS \opcode_in [25:21] + connect \opcode_in \$1 + connect \DIV_dec31_opcode_in \opcode_in + connect \opcode_switch \opcode_in [31:26] +end +attribute \src "libresoc.v:59937.1-61328.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_MUL.dec" +attribute \generator "nMigen" +module \dec$177 + attribute \src "libresoc.v:60934.3-60946.6" + wire width 3 $0\MUL_cr_in[2:0] + attribute \src "libresoc.v:60947.3-60959.6" + wire width 3 $0\MUL_cr_out[2:0] + attribute \src "libresoc.v:60895.3-60907.6" + wire width 12 $0\MUL_function_unit[11:0] + attribute \src "libresoc.v:60921.3-60933.6" + wire width 4 $0\MUL_in2_sel[3:0] + attribute \src "libresoc.v:60908.3-60920.6" + wire width 7 $0\MUL_internal_op[6:0] + attribute \src "libresoc.v:60973.3-60985.6" + wire $0\MUL_is_32b[0:0] + attribute \src "libresoc.v:60960.3-60972.6" + wire width 2 $0\MUL_rc_sel[1:0] + attribute \src "libresoc.v:60986.3-60998.6" + wire $0\MUL_sgn[0:0] + attribute \src "libresoc.v:59938.7-59938.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:60934.3-60946.6" + wire width 3 $1\MUL_cr_in[2:0] + attribute \src "libresoc.v:60947.3-60959.6" + wire width 3 $1\MUL_cr_out[2:0] + attribute \src "libresoc.v:60895.3-60907.6" + wire width 12 $1\MUL_function_unit[11:0] + attribute \src "libresoc.v:60921.3-60933.6" + wire width 4 $1\MUL_in2_sel[3:0] + attribute \src "libresoc.v:60908.3-60920.6" + wire width 7 $1\MUL_internal_op[6:0] + attribute \src "libresoc.v:60973.3-60985.6" + wire $1\MUL_is_32b[0:0] + attribute \src "libresoc.v:60960.3-60972.6" + wire width 2 $1\MUL_rc_sel[1:0] + attribute \src "libresoc.v:60986.3-60998.6" + wire $1\MUL_sgn[0:0] + attribute \src "libresoc.v:60883.17-60883.211" + wire width 32 $ternary$libresoc.v:60883$3520_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:478" + wire width 32 \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_FRC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \A_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \B_AA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 14 \B_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \B_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \B_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \B_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DQE_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DQE_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \DQE_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 12 \DQ_DQ + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \DQ_PT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DQ_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DQ_RTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DQ_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \DQ_SX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \DQ_SX_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DQ_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \DQ_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \DQ_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \DQ_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 14 \DS_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_FRSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_RSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_VRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \DS_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DX_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \DX_d0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 16 \DX_d0_d1_d2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DX_d1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \DX_d2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \D_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 16 \D_D + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \D_FRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \D_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \D_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \D_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \D_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \D_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 16 \D_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \D_TO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 16 \D_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \EVS_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \I_AA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 24 \I_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \I_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MDS_IB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MDS_IS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MDS_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MDS_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MDS_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \MDS_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \MDS_XBI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \MDS_XBI_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \MDS_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \MDS_mb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \MDS_me + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MD_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MD_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \MD_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \MD_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \MD_mb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \MD_me + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \MD_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire \MUL_AA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 output 20 \MUL_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 output 19 \MUL_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 output 25 \MUL_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 14 output 18 \MUL_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 3 \MUL_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 2 \MUL_BH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 output 23 \MUL_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \MUL_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 output 21 \MUL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 10 \MUL_CR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 16 \MUL_D + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 14 output 24 \MUL_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 8 output 22 \MUL_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire \MUL_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 24 output 15 \MUL_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire \MUL_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \MUL_MB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \MUL_MB32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \MUL_ME + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \MUL_ME32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire output 17 \MUL_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \MUL_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \MUL_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \MUL_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \MUL_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire output 16 \MUL_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \MUL_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 output 13 \MUL_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 16 output 11 \MUL_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 10 \MUL_SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \MUL_TO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 16 output 12 \MUL_UI + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 4 \MUL_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \MUL_cr_out + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \MUL_dec31_MUL_dec31_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \MUL_dec31_MUL_dec31_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \MUL_dec31_MUL_dec31_function_unit + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \MUL_dec31_MUL_dec31_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 \MUL_dec31_MUL_dec31_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \MUL_dec31_MUL_dec31_is_32b + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \MUL_dec31_MUL_dec31_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \MUL_dec31_MUL_dec31_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \MUL_dec31_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 7 \MUL_function_unit + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 8 \MUL_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 6 \MUL_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 9 \MUL_is_32b + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 3 \MUL_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 10 \MUL_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 6 output 14 \MUL_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \M_MB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \M_ME + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \M_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \M_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \M_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \M_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \M_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 7 \SC_LEV + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \SC_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \SC_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \TX_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \TX_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \TX_XBI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \TX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_RC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \VA_SHB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_VRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_VRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_VRC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \VA_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \VC_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VC_VRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VC_VRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VC_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \VC_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_EO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \VX_PS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_SIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_UIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \VX_UIM_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \VX_UIM_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \VX_UIM_3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_VRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_VRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \VX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 11 \VX_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 8 \XFL_FLM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XFL_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XFL_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XFL_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XFL_W + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \XFL_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \XFX_BHRBE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XFX_DUI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \XFX_DUIS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 8 \XFX_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XFX_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XFX_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \XFX_SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \XFX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XL_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XL_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \XL_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \XL_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \XL_BH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XL_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XL_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XL_BO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 output 28 \XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XL_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 15 \XL_OC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XL_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \XL_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XO_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XO_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XO_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XO_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XO_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 9 \XO_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XS_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XS_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XS_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 9 \XS_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XS_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX2_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \XX2_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX2_BX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX2_BX_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 7 \XX2_DCMX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX2_EO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX2_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX2_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX2_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX2_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \XX2_UIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \XX2_UIM_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 7 \XX2_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 9 \XX2_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX2_dc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 7 \XX2_dc_dm_dx + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX2_dm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX2_dx + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX3_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX3_AX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX3_AX_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX3_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \XX3_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX3_BX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX3_BX_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \XX3_DM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX3_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \XX3_SHW + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX3_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX3_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX3_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \XX3_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 8 \XX3_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 9 \XX3_XO_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX4_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX4_AX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX4_AX_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX4_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX4_BX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX4_BX_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX4_C + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX4_CX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX4_CX_C + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX4_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX4_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX4_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \XX4_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 output 26 \X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 output 27 \X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \X_CT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 7 \X_DCMX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \X_DRM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_E + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \X_EO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_EO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_EX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \X_E_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRAp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRBp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \X_IH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 8 \X_IMM8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_L1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \X_L2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \X_L3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_MO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_NB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_PRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_R + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \X_RIC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \X_RM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_RO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_RSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_RTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_R_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \X_SP + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \X_SR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_SX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \X_SX_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \X_TBR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_TH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_TO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \X_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \X_U + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_UIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_VRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_W + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \X_WC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \X_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 8 \X_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \Z22_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \Z22_DCM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \Z22_DGM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z22_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z22_FRAp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z22_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z22_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \Z22_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \Z22_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 9 \Z22_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_FRAp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_FRBp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \Z23_R + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \Z23_RMC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \Z23_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_TE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 8 \Z23_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \all_OPCD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \all_PO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + wire input 1 \bigendian + attribute \src "libresoc.v:59938.7-59938.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 output 2 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 6 \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:442" + wire width 32 input 29 \raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:478" + cell $mux $ternary$libresoc.v:60883$3520 + parameter \WIDTH 32 + connect \A \raw_opcode_in + connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } + connect \S \bigendian + connect \Y $ternary$libresoc.v:60883$3520_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:60884.13-60894.4" + cell \MUL_dec31 \MUL_dec31 + connect \MUL_dec31_cr_in \MUL_dec31_MUL_dec31_cr_in + connect \MUL_dec31_cr_out \MUL_dec31_MUL_dec31_cr_out + connect \MUL_dec31_function_unit \MUL_dec31_MUL_dec31_function_unit + connect \MUL_dec31_in2_sel \MUL_dec31_MUL_dec31_in2_sel + connect \MUL_dec31_internal_op \MUL_dec31_MUL_dec31_internal_op + connect \MUL_dec31_is_32b \MUL_dec31_MUL_dec31_is_32b + connect \MUL_dec31_rc_sel \MUL_dec31_MUL_dec31_rc_sel + connect \MUL_dec31_sgn \MUL_dec31_MUL_dec31_sgn + connect \opcode_in \MUL_dec31_opcode_in + end + attribute \src "libresoc.v:59938.7-59938.20" + process $proc$libresoc.v:59938$3529 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:60895.3-60907.6" + process $proc$libresoc.v:60895$3521 + assign { } { } + assign { } { } + assign $0\MUL_function_unit[11:0] $1\MUL_function_unit[11:0] + attribute \src "libresoc.v:60896.5-60896.29" + switch \initial + attribute \src "libresoc.v:60896.9-60896.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\MUL_function_unit[11:0] \MUL_dec31_MUL_dec31_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\MUL_function_unit[11:0] 12'000100000000 + case + assign $1\MUL_function_unit[11:0] 12'000000000000 + end + sync always + update \MUL_function_unit $0\MUL_function_unit[11:0] + end + attribute \src "libresoc.v:60908.3-60920.6" + process $proc$libresoc.v:60908$3522 + assign { } { } + assign { } { } + assign $0\MUL_internal_op[6:0] $1\MUL_internal_op[6:0] + attribute \src "libresoc.v:60909.5-60909.29" + switch \initial + attribute \src "libresoc.v:60909.9-60909.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\MUL_internal_op[6:0] \MUL_dec31_MUL_dec31_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\MUL_internal_op[6:0] 7'0110010 + case + assign $1\MUL_internal_op[6:0] 7'0000000 + end + sync always + update \MUL_internal_op $0\MUL_internal_op[6:0] + end + attribute \src "libresoc.v:60921.3-60933.6" + process $proc$libresoc.v:60921$3523 + assign { } { } + assign { } { } + assign $0\MUL_in2_sel[3:0] $1\MUL_in2_sel[3:0] + attribute \src "libresoc.v:60922.5-60922.29" + switch \initial + attribute \src "libresoc.v:60922.9-60922.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\MUL_in2_sel[3:0] \MUL_dec31_MUL_dec31_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\MUL_in2_sel[3:0] 4'0011 + case + assign $1\MUL_in2_sel[3:0] 4'0000 + end + sync always + update \MUL_in2_sel $0\MUL_in2_sel[3:0] + end + attribute \src "libresoc.v:60934.3-60946.6" + process $proc$libresoc.v:60934$3524 + assign { } { } + assign { } { } + assign $0\MUL_cr_in[2:0] $1\MUL_cr_in[2:0] + attribute \src "libresoc.v:60935.5-60935.29" + switch \initial + attribute \src "libresoc.v:60935.9-60935.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\MUL_cr_in[2:0] \MUL_dec31_MUL_dec31_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\MUL_cr_in[2:0] 3'000 + case + assign $1\MUL_cr_in[2:0] 3'000 + end + sync always + update \MUL_cr_in $0\MUL_cr_in[2:0] + end + attribute \src "libresoc.v:60947.3-60959.6" + process $proc$libresoc.v:60947$3525 + assign { } { } + assign { } { } + assign $0\MUL_cr_out[2:0] $1\MUL_cr_out[2:0] + attribute \src "libresoc.v:60948.5-60948.29" + switch \initial + attribute \src "libresoc.v:60948.9-60948.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\MUL_cr_out[2:0] \MUL_dec31_MUL_dec31_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\MUL_cr_out[2:0] 3'001 + case + assign $1\MUL_cr_out[2:0] 3'000 + end + sync always + update \MUL_cr_out $0\MUL_cr_out[2:0] + end + attribute \src "libresoc.v:60960.3-60972.6" + process $proc$libresoc.v:60960$3526 + assign { } { } + assign { } { } + assign $0\MUL_rc_sel[1:0] $1\MUL_rc_sel[1:0] + attribute \src "libresoc.v:60961.5-60961.29" + switch \initial + attribute \src "libresoc.v:60961.9-60961.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\MUL_rc_sel[1:0] \MUL_dec31_MUL_dec31_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\MUL_rc_sel[1:0] 2'00 + case + assign $1\MUL_rc_sel[1:0] 2'00 + end + sync always + update \MUL_rc_sel $0\MUL_rc_sel[1:0] + end + attribute \src "libresoc.v:60973.3-60985.6" + process $proc$libresoc.v:60973$3527 + assign { } { } + assign { } { } + assign $0\MUL_is_32b[0:0] $1\MUL_is_32b[0:0] + attribute \src "libresoc.v:60974.5-60974.29" + switch \initial + attribute \src "libresoc.v:60974.9-60974.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\MUL_is_32b[0:0] \MUL_dec31_MUL_dec31_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\MUL_is_32b[0:0] 1'0 + case + assign $1\MUL_is_32b[0:0] 1'0 + end + sync always + update \MUL_is_32b $0\MUL_is_32b[0:0] + end + attribute \src "libresoc.v:60986.3-60998.6" + process $proc$libresoc.v:60986$3528 + assign { } { } + assign { } { } + assign $0\MUL_sgn[0:0] $1\MUL_sgn[0:0] + attribute \src "libresoc.v:60987.5-60987.29" + switch \initial + attribute \src "libresoc.v:60987.9-60987.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\MUL_sgn[0:0] \MUL_dec31_MUL_dec31_sgn + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\MUL_sgn[0:0] 1'1 + case + assign $1\MUL_sgn[0:0] 1'0 + end + sync always + update \MUL_sgn $0\MUL_sgn[0:0] + end + connect \$1 $ternary$libresoc.v:60883$3520_Y + connect \VC_XO \opcode_in [9:0] + connect \VC_VRT \opcode_in [25:21] + connect \VC_VRB \opcode_in [15:11] + connect \VC_VRA \opcode_in [20:16] + connect \VC_Rc \opcode_in [10] + connect \XS_XO \opcode_in [10:2] + connect \XS_sh { \opcode_in [1] \opcode_in [15:11] } + connect \XS_RS \opcode_in [25:21] + connect \XS_Rc \opcode_in [0] + connect \XS_RA \opcode_in [20:16] + connect \VA_XO \opcode_in [5:0] + connect \VA_VRT \opcode_in [25:21] + connect \VA_VRC \opcode_in [10:6] + connect \VA_VRB \opcode_in [15:11] + connect \VA_VRA \opcode_in [20:16] + connect \VA_SHB \opcode_in [9:6] + connect \VA_RT \opcode_in [25:21] + connect \VA_RC \opcode_in [10:6] + connect \VA_RB \opcode_in [15:11] + connect \VA_RA \opcode_in [20:16] + connect \TX_XO \opcode_in [6:1] + connect \TX_XBI \opcode_in [10:7] + connect \TX_UI \opcode_in [15:11] + connect \TX_RA \opcode_in [20:16] + connect \DQE_XO \opcode_in [1:0] + connect \DQE_RT \opcode_in [25:21] + connect \DQE_RA \opcode_in [20:16] + connect \XO_XO \opcode_in [9:1] + connect \XO_RT \opcode_in [25:21] + connect \XO_Rc \opcode_in [0] + connect \XO_RB \opcode_in [15:11] + connect \XO_RA \opcode_in [20:16] + connect \XO_OE \opcode_in [10] + connect \all_PO \opcode_in [31:26] + connect \all_OPCD \opcode_in [31:26] + connect \MD_XO \opcode_in [4:2] + connect \MD_sh { \opcode_in [1] \opcode_in [15:11] } + connect \MD_RS \opcode_in [25:21] + connect \MD_Rc \opcode_in [0] + connect \MD_RA \opcode_in [20:16] + connect \MD_me \opcode_in [10:5] + connect \MD_mb \opcode_in [10:5] + connect \M_SH \opcode_in [15:11] + connect \M_RS \opcode_in [25:21] + connect \M_Rc \opcode_in [0] + connect \M_RB \opcode_in [15:11] + connect \M_RA \opcode_in [20:16] + connect \M_ME \opcode_in [5:1] + connect \M_MB \opcode_in [10:6] + connect \SC_XO_1 \opcode_in [1:0] + connect \SC_XO \opcode_in [1] + connect \SC_LEV \opcode_in [11:5] + connect \MDS_XO \opcode_in [4:1] + connect \MDS_XBI_1 \opcode_in [10:7] + connect \MDS_XBI \opcode_in [10:7] + connect \MDS_RS \opcode_in [25:21] + connect \MDS_Rc \opcode_in [0] + connect \MDS_RB \opcode_in [15:11] + connect \MDS_RA \opcode_in [20:16] + connect \MDS_me \opcode_in [10:5] + connect \MDS_mb \opcode_in [10:5] + connect \MDS_IS \opcode_in [25:21] + connect \MDS_IB \opcode_in [15:11] + connect \Z23_XO \opcode_in [8:1] + connect \Z23_TE \opcode_in [20:16] + connect \Z23_RMC \opcode_in [10:9] + connect \Z23_Rc \opcode_in [0] + connect \Z23_R \opcode_in [16] + connect \Z23_FRTp \opcode_in [25:21] + connect \Z23_FRT \opcode_in [25:21] + connect \Z23_FRBp \opcode_in [15:11] + connect \Z23_FRB \opcode_in [15:11] + connect \Z23_FRAp \opcode_in [20:16] + connect \Z23_FRA \opcode_in [20:16] + connect \XFL_XO \opcode_in [10:1] + connect \XFL_W \opcode_in [16] + connect \XFL_Rc \opcode_in [0] + connect \XFL_L \opcode_in [25] + connect \XFL_FRB \opcode_in [15:11] + connect \XFL_FLM \opcode_in [24:17] + connect \VX_XO_1 \opcode_in [10:0] + connect \VX_XO { \opcode_in [10] \opcode_in [8:0] } + connect \VX_VRT \opcode_in [25:21] + connect \VX_VRB \opcode_in [15:11] + connect \VX_VRA \opcode_in [20:16] + connect \VX_UIM_3 \opcode_in [17:16] + connect \VX_UIM_2 \opcode_in [18:16] + connect \VX_UIM_1 \opcode_in [19:16] + connect \VX_UIM \opcode_in [20:16] + connect \VX_SIM \opcode_in [20:16] + connect \VX_RT \opcode_in [25:21] + connect \VX_RA \opcode_in [20:16] + connect \VX_PS \opcode_in [9] + connect \VX_EO \opcode_in [20:16] + connect \DS_XO \opcode_in [1:0] + connect \DS_VRT \opcode_in [25:21] + connect \DS_VRS \opcode_in [25:21] + connect \DS_RT \opcode_in [25:21] + connect \DS_RSp \opcode_in [25:21] + connect \DS_RS \opcode_in [25:21] + connect \DS_RA \opcode_in [20:16] + connect \DS_FRTp \opcode_in [25:21] + connect \DS_FRSp \opcode_in [25:21] + connect \DS_DS \opcode_in [15:2] + connect \DQ_XO \opcode_in [2:0] + connect \DQ_TX_T { \opcode_in [3] \opcode_in [25:21] } + connect \DQ_T \opcode_in [25:21] + connect \DQ_TX \opcode_in [3] + connect \DQ_SX_S { \opcode_in [3] \opcode_in [25:21] } + connect \DQ_S \opcode_in [25:21] + connect \DQ_SX \opcode_in [3] + connect \DQ_RTp \opcode_in [25:21] + connect \DQ_RA \opcode_in [20:16] + connect \DQ_PT \opcode_in [3:0] + connect \DQ_DQ \opcode_in [15:4] + connect \DX_XO \opcode_in [5:1] + connect \DX_RT \opcode_in [25:21] + connect \DX_d0_d1_d2 { \opcode_in [15:6] \opcode_in [20:16] \opcode_in [0] } + connect \DX_d2 \opcode_in [0] + connect \DX_d1 \opcode_in [20:16] + connect \DX_d0 \opcode_in [15:6] + connect \XFX_XO \opcode_in [10:1] + connect \XFX_SPR \opcode_in [20:11] + connect \XFX_RT \opcode_in [25:21] + connect \XFX_RS \opcode_in [25:21] + connect \XFX_FXM \opcode_in [19:12] + connect \XFX_DUIS \opcode_in [20:11] + connect \XFX_DUI \opcode_in [25:21] + connect \XFX_BHRBE \opcode_in [20:11] + connect \EVS_BFA \opcode_in [2:0] + connect \Z22_XO \opcode_in [9:1] + connect \Z22_SH \opcode_in [15:10] + connect \Z22_Rc \opcode_in [0] + connect \Z22_FRTp \opcode_in [25:21] + connect \Z22_FRT \opcode_in [25:21] + connect \Z22_FRAp \opcode_in [20:16] + connect \Z22_FRA \opcode_in [20:16] + connect \Z22_DGM \opcode_in [15:10] + connect \Z22_DCM \opcode_in [15:10] + connect \Z22_BF \opcode_in [25:23] + connect \XX2_XO_1 \opcode_in [10:2] + connect \XX2_XO { \opcode_in [10:7] \opcode_in [5:3] } + connect \XX2_UIM_1 \opcode_in [17:16] + connect \XX2_UIM \opcode_in [19:16] + connect \XX2_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX2_T \opcode_in [25:21] + connect \XX2_TX \opcode_in [0] + connect \XX2_RT \opcode_in [25:21] + connect \XX2_EO \opcode_in [20:16] + connect \XX2_DCMX \opcode_in [22:16] + connect \XX2_dc_dm_dx { \opcode_in [6] \opcode_in [2] \opcode_in [20:16] } + connect \XX2_dx \opcode_in [20:16] + connect \XX2_dm \opcode_in [2] + connect \XX2_dc \opcode_in [6] + connect \XX2_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX2_B \opcode_in [15:11] + connect \XX2_BX \opcode_in [1] + connect \XX2_BF \opcode_in [25:23] + connect \D_UI \opcode_in [15:0] + connect \D_TO \opcode_in [25:21] + connect \D_SI \opcode_in [15:0] + connect \D_RT \opcode_in [25:21] + connect \D_RS \opcode_in [25:21] + connect \D_RA \opcode_in [20:16] + connect \D_L \opcode_in [21] + connect \D_FRT \opcode_in [25:21] + connect \D_FRS \opcode_in [25:21] + connect \D_D \opcode_in [15:0] + connect \D_BF \opcode_in [25:23] + connect \A_XO \opcode_in [5:1] + connect \A_RT \opcode_in [25:21] + connect \A_Rc \opcode_in [0] + connect \A_RB \opcode_in [15:11] + connect \A_RA \opcode_in [20:16] + connect \A_FRT \opcode_in [25:21] + connect \A_FRC \opcode_in [10:6] + connect \A_FRB \opcode_in [15:11] + connect \A_FRA \opcode_in [20:16] + connect \A_BC \opcode_in [10:6] + connect \XL_XO \opcode_in [10:1] + connect \XL_S \opcode_in [11] + connect \XL_OC \opcode_in [25:11] + connect \XL_LK \opcode_in [0] + connect \XL_BT \opcode_in [25:21] + connect \XL_BO_1 \opcode_in [25:21] + connect \XL_BO \opcode_in [25:21] + connect \XL_BI \opcode_in [20:16] + connect \XL_BH \opcode_in [12:11] + connect \XL_BFA \opcode_in [20:18] + connect \XL_BF \opcode_in [25:23] + connect \XL_BB \opcode_in [15:11] + connect \XL_BA \opcode_in [20:16] + connect \XX4_XO \opcode_in [5:4] + connect \XX4_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX4_T \opcode_in [25:21] + connect \XX4_TX \opcode_in [0] + connect \XX4_CX_C { \opcode_in [3] \opcode_in [10:6] } + connect \XX4_C \opcode_in [10:6] + connect \XX4_CX \opcode_in [3] + connect \XX4_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX4_B \opcode_in [15:11] + connect \XX4_BX \opcode_in [1] + connect \XX4_AX_A { \opcode_in [2] \opcode_in [20:16] } + connect \XX4_A \opcode_in [20:16] + connect \XX4_AX \opcode_in [2] + connect \XX3_XO_2 \opcode_in [9:1] + connect \XX3_XO_1 \opcode_in [10:3] + connect \XX3_XO \opcode_in [10:7] + connect \XX3_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX3_T \opcode_in [25:21] + connect \XX3_TX \opcode_in [0] + connect \XX3_SHW \opcode_in [9:8] + connect \XX3_Rc \opcode_in [10] + connect \XX3_DM \opcode_in [9:8] + connect \XX3_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX3_B \opcode_in [15:11] + connect \XX3_BX \opcode_in [1] + connect \XX3_BF \opcode_in [25:23] + connect \XX3_AX_A { \opcode_in [2] \opcode_in [20:16] } + connect \XX3_A \opcode_in [20:16] + connect \XX3_AX \opcode_in [2] + connect \I_LK \opcode_in [0] + connect \I_LI \opcode_in [25:2] + connect \I_AA \opcode_in [1] + connect \B_LK \opcode_in [0] + connect \B_BO \opcode_in [25:21] + connect \B_BI \opcode_in [20:16] + connect \B_BD \opcode_in [15:2] + connect \B_AA \opcode_in [1] + connect \X_XO_1 \opcode_in [8:1] + connect \X_XO \opcode_in [10:1] + connect \X_WC \opcode_in [22:21] + connect \X_W \opcode_in [16] + connect \X_VRT \opcode_in [25:21] + connect \X_VRS \opcode_in [25:21] + connect \X_UIM \opcode_in [20:16] + connect \X_U \opcode_in [15:12] + connect \X_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \X_TX \opcode_in [0] + connect \X_TO \opcode_in [25:21] + connect \X_TH \opcode_in [25:21] + connect \X_TBR \opcode_in [20:11] + connect \X_T \opcode_in [25:21] + connect \X_SX_S { \opcode_in [0] \opcode_in [25:21] } + connect \X_SX \opcode_in [0] + connect \X_SR \opcode_in [19:16] + connect \X_SP \opcode_in [20:19] + connect \X_SI \opcode_in [15:11] + connect \X_SH \opcode_in [15:11] + connect \X_S \opcode_in [25:21] + connect \X_RTp \opcode_in [25:21] + connect \X_RT \opcode_in [25:21] + connect \X_RSp \opcode_in [25:21] + connect \X_RS \opcode_in [25:21] + connect \X_RO \opcode_in [0] + connect \X_RM \opcode_in [12:11] + connect \X_RIC \opcode_in [19:18] + connect \X_Rc \opcode_in [0] + connect \X_RB \opcode_in [15:11] + connect \X_RA \opcode_in [20:16] + connect \X_R_1 \opcode_in [16] + connect \X_R \opcode_in [21] + connect \X_PRS \opcode_in [17] + connect \X_NB \opcode_in [15:11] + connect \X_MO \opcode_in [25:21] + connect \X_L3 \opcode_in [17:16] + connect \X_L1 \opcode_in [16] + connect \X_L \opcode_in [21] + connect \X_L2 \opcode_in [22:21] + connect \X_IMM8 \opcode_in [18:11] + connect \X_IH \opcode_in [23:21] + connect \X_FRTp \opcode_in [25:21] + connect \X_FRT \opcode_in [25:21] + connect \X_FRSp \opcode_in [25:21] + connect \X_FRS \opcode_in [25:21] + connect \X_FRBp \opcode_in [15:11] + connect \X_FRB \opcode_in [15:11] + connect \X_FRAp \opcode_in [20:16] + connect \X_FRA \opcode_in [20:16] + connect \X_FC \opcode_in [15:11] + connect \X_EX \opcode_in [0] + connect \X_EO_1 \opcode_in [20:16] + connect \X_EO \opcode_in [20:19] + connect \X_E_1 \opcode_in [19:16] + connect \X_E \opcode_in [15] + connect \X_DRM \opcode_in [13:11] + connect \X_DCMX \opcode_in [22:16] + connect \X_CT \opcode_in [24:21] + connect \X_BO \opcode_in [25:21] + connect \X_BFA \opcode_in [20:18] + connect \X_BF \opcode_in [25:23] + connect \X_A \opcode_in [25] + connect \MUL_SPR \opcode_in [20:11] + connect \MUL_MB \opcode_in [10:6] + connect \MUL_ME \opcode_in [5:1] + connect \MUL_SH \opcode_in [15:11] + connect \MUL_BC \opcode_in [10:6] + connect \MUL_TO \opcode_in [25:21] + connect \MUL_DS \opcode_in [15:2] + connect \MUL_D \opcode_in [15:0] + connect \MUL_BH \opcode_in [12:11] + connect \MUL_BI \opcode_in [20:16] + connect \MUL_BO \opcode_in [25:21] + connect \MUL_FXM \opcode_in [19:12] + connect \MUL_BT \opcode_in [25:21] + connect \MUL_BA \opcode_in [20:16] + connect \MUL_BB \opcode_in [15:11] + connect \MUL_CR \opcode_in [10:1] + connect \MUL_BF \opcode_in [25:23] + connect \MUL_BD \opcode_in [15:2] + connect \MUL_OE \opcode_in [10] + connect \MUL_Rc \opcode_in [0] + connect \MUL_AA \opcode_in [1] + connect \MUL_LK \opcode_in [0] + connect \MUL_LI \opcode_in [25:2] + connect \MUL_ME32 \opcode_in [5:1] + connect \MUL_MB32 \opcode_in [10:6] + connect \MUL_sh { \opcode_in [1] \opcode_in [15:11] } + connect \MUL_SH32 \opcode_in [15:11] + connect \MUL_L \opcode_in [21] + connect \MUL_UI \opcode_in [15:0] + connect \MUL_SI \opcode_in [15:0] + connect \MUL_RB \opcode_in [15:11] + connect \MUL_RA \opcode_in [20:16] + connect \MUL_RT \opcode_in [25:21] + connect \MUL_RS \opcode_in [25:21] + connect \opcode_in \$1 + connect \MUL_dec31_opcode_in \opcode_in + connect \opcode_switch \opcode_in [31:26] +end +attribute \src "libresoc.v:61332.1-63019.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_SHIFT_ROT.dec" +attribute \generator "nMigen" +module \dec$185 + attribute \src "libresoc.v:62601.3-62622.6" + wire width 3 $0\SHIFT_ROT_cr_in[2:0] + attribute \src "libresoc.v:62623.3-62644.6" + wire width 3 $0\SHIFT_ROT_cr_out[2:0] + attribute \src "libresoc.v:62667.3-62688.6" + wire width 2 $0\SHIFT_ROT_cry_in[1:0] + attribute \src "libresoc.v:62469.3-62490.6" + wire $0\SHIFT_ROT_cry_out[0:0] + attribute \src "libresoc.v:62535.3-62556.6" + wire width 12 $0\SHIFT_ROT_function_unit[11:0] + attribute \src "libresoc.v:62579.3-62600.6" + wire width 4 $0\SHIFT_ROT_in2_sel[3:0] + attribute \src "libresoc.v:62557.3-62578.6" + wire width 7 $0\SHIFT_ROT_internal_op[6:0] + attribute \src "libresoc.v:62491.3-62512.6" + wire $0\SHIFT_ROT_is_32b[0:0] + attribute \src "libresoc.v:62645.3-62666.6" + wire width 2 $0\SHIFT_ROT_rc_sel[1:0] + attribute \src "libresoc.v:62513.3-62534.6" + wire $0\SHIFT_ROT_sgn[0:0] + attribute \src "libresoc.v:61333.7-61333.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:62601.3-62622.6" + wire width 3 $1\SHIFT_ROT_cr_in[2:0] + attribute \src "libresoc.v:62623.3-62644.6" + wire width 3 $1\SHIFT_ROT_cr_out[2:0] + attribute \src "libresoc.v:62667.3-62688.6" + wire width 2 $1\SHIFT_ROT_cry_in[1:0] + attribute \src "libresoc.v:62469.3-62490.6" + wire $1\SHIFT_ROT_cry_out[0:0] + attribute \src "libresoc.v:62535.3-62556.6" + wire width 12 $1\SHIFT_ROT_function_unit[11:0] + attribute \src "libresoc.v:62579.3-62600.6" + wire width 4 $1\SHIFT_ROT_in2_sel[3:0] + attribute \src "libresoc.v:62557.3-62578.6" + wire width 7 $1\SHIFT_ROT_internal_op[6:0] + attribute \src "libresoc.v:62491.3-62512.6" + wire $1\SHIFT_ROT_is_32b[0:0] + attribute \src "libresoc.v:62645.3-62666.6" + wire width 2 $1\SHIFT_ROT_rc_sel[1:0] + attribute \src "libresoc.v:62513.3-62534.6" + wire $1\SHIFT_ROT_sgn[0:0] + attribute \src "libresoc.v:62442.17-62442.211" + wire width 32 $ternary$libresoc.v:62442$3530_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:478" + wire width 32 \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_FRC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \A_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \B_AA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 14 \B_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \B_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \B_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \B_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DQE_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DQE_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \DQE_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 12 \DQ_DQ + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \DQ_PT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DQ_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DQ_RTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DQ_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \DQ_SX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \DQ_SX_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DQ_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \DQ_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \DQ_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \DQ_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 14 \DS_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_FRSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_RSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_VRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \DS_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DX_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \DX_d0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 16 \DX_d0_d1_d2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DX_d1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \DX_d2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \D_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 16 \D_D + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \D_FRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \D_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \D_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \D_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \D_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \D_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 16 \D_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \D_TO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 16 \D_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \EVS_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \I_AA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 24 \I_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \I_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MDS_IB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MDS_IS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MDS_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MDS_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MDS_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \MDS_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \MDS_XBI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \MDS_XBI_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \MDS_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \MDS_mb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \MDS_me + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MD_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MD_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \MD_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \MD_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \MD_mb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \MD_me + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \MD_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \M_MB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \M_ME + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \M_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \M_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \M_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \M_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \M_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 7 \SC_LEV + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \SC_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \SC_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire \SHIFT_ROT_AA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 output 22 \SHIFT_ROT_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 output 21 \SHIFT_ROT_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 output 27 \SHIFT_ROT_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 14 output 20 \SHIFT_ROT_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 3 \SHIFT_ROT_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 2 \SHIFT_ROT_BH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 output 25 \SHIFT_ROT_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \SHIFT_ROT_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 output 23 \SHIFT_ROT_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 10 \SHIFT_ROT_CR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 16 \SHIFT_ROT_D + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 14 output 26 \SHIFT_ROT_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 8 output 24 \SHIFT_ROT_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire \SHIFT_ROT_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 24 output 17 \SHIFT_ROT_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire \SHIFT_ROT_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \SHIFT_ROT_MB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \SHIFT_ROT_MB32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \SHIFT_ROT_ME + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \SHIFT_ROT_ME32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire output 19 \SHIFT_ROT_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \SHIFT_ROT_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \SHIFT_ROT_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \SHIFT_ROT_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \SHIFT_ROT_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire output 18 \SHIFT_ROT_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \SHIFT_ROT_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 output 15 \SHIFT_ROT_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 16 output 13 \SHIFT_ROT_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 10 \SHIFT_ROT_SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \SHIFT_ROT_TO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 16 output 14 \SHIFT_ROT_UI + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 4 \SHIFT_ROT_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \SHIFT_ROT_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 9 \SHIFT_ROT_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 10 \SHIFT_ROT_cry_out + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \SHIFT_ROT_dec30_SHIFT_ROT_dec30_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \SHIFT_ROT_dec30_SHIFT_ROT_dec30_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \SHIFT_ROT_dec30_SHIFT_ROT_dec30_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \SHIFT_ROT_dec30_SHIFT_ROT_dec30_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \SHIFT_ROT_dec30_SHIFT_ROT_dec30_function_unit + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \SHIFT_ROT_dec30_SHIFT_ROT_dec30_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 \SHIFT_ROT_dec30_SHIFT_ROT_dec30_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \SHIFT_ROT_dec30_SHIFT_ROT_dec30_is_32b + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \SHIFT_ROT_dec30_SHIFT_ROT_dec30_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \SHIFT_ROT_dec30_SHIFT_ROT_dec30_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \SHIFT_ROT_dec30_opcode_in + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \SHIFT_ROT_dec31_SHIFT_ROT_dec31_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \SHIFT_ROT_dec31_SHIFT_ROT_dec31_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \SHIFT_ROT_dec31_SHIFT_ROT_dec31_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \SHIFT_ROT_dec31_SHIFT_ROT_dec31_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \SHIFT_ROT_dec31_SHIFT_ROT_dec31_function_unit + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \SHIFT_ROT_dec31_SHIFT_ROT_dec31_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 \SHIFT_ROT_dec31_SHIFT_ROT_dec31_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \SHIFT_ROT_dec31_SHIFT_ROT_dec31_is_32b + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \SHIFT_ROT_dec31_SHIFT_ROT_dec31_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \SHIFT_ROT_dec31_SHIFT_ROT_dec31_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \SHIFT_ROT_dec31_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 7 \SHIFT_ROT_function_unit + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 8 \SHIFT_ROT_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 6 \SHIFT_ROT_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 11 \SHIFT_ROT_is_32b + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 3 \SHIFT_ROT_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 12 \SHIFT_ROT_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 6 output 16 \SHIFT_ROT_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \TX_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \TX_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \TX_XBI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \TX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_RC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \VA_SHB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_VRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_VRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_VRC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \VA_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \VC_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VC_VRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VC_VRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VC_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \VC_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_EO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \VX_PS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_SIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_UIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \VX_UIM_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \VX_UIM_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \VX_UIM_3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_VRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_VRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \VX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 11 \VX_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 8 \XFL_FLM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XFL_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XFL_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XFL_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XFL_W + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \XFL_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \XFX_BHRBE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XFX_DUI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \XFX_DUIS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 8 \XFX_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XFX_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XFX_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \XFX_SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \XFX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XL_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XL_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \XL_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \XL_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \XL_BH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XL_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XL_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XL_BO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 output 30 \XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XL_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 15 \XL_OC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XL_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \XL_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XO_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XO_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XO_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XO_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XO_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 9 \XO_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XS_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XS_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XS_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 9 \XS_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XS_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX2_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \XX2_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX2_BX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX2_BX_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 7 \XX2_DCMX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX2_EO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX2_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX2_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX2_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX2_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \XX2_UIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \XX2_UIM_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 7 \XX2_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 9 \XX2_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX2_dc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 7 \XX2_dc_dm_dx + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX2_dm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX2_dx + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX3_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX3_AX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX3_AX_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX3_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \XX3_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX3_BX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX3_BX_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \XX3_DM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX3_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \XX3_SHW + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX3_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX3_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX3_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \XX3_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 8 \XX3_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 9 \XX3_XO_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX4_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX4_AX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX4_AX_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX4_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX4_BX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX4_BX_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX4_C + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX4_CX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX4_CX_C + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX4_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX4_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX4_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \XX4_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 output 28 \X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 output 29 \X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \X_CT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 7 \X_DCMX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \X_DRM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_E + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \X_EO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_EO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_EX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \X_E_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRAp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRBp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \X_IH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 8 \X_IMM8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_L1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \X_L2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \X_L3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_MO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_NB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_PRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_R + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \X_RIC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \X_RM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_RO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_RSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_RTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_R_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \X_SP + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \X_SR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_SX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \X_SX_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \X_TBR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_TH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_TO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \X_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \X_U + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_UIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_VRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_W + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \X_WC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \X_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 8 \X_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \Z22_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \Z22_DCM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \Z22_DGM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z22_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z22_FRAp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z22_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z22_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \Z22_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \Z22_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 9 \Z22_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_FRAp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_FRBp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \Z23_R + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \Z23_RMC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \Z23_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_TE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 8 \Z23_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \all_OPCD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \all_PO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + wire input 1 \bigendian + attribute \src "libresoc.v:61333.7-61333.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 output 2 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 6 \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:442" + wire width 32 input 31 \raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:478" + cell $mux $ternary$libresoc.v:62442$3530 + parameter \WIDTH 32 + connect \A \raw_opcode_in + connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } + connect \S \bigendian + connect \Y $ternary$libresoc.v:62442$3530_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:62443.19-62455.4" + cell \SHIFT_ROT_dec30 \SHIFT_ROT_dec30 + connect \SHIFT_ROT_dec30_cr_in \SHIFT_ROT_dec30_SHIFT_ROT_dec30_cr_in + connect \SHIFT_ROT_dec30_cr_out \SHIFT_ROT_dec30_SHIFT_ROT_dec30_cr_out + connect \SHIFT_ROT_dec30_cry_in \SHIFT_ROT_dec30_SHIFT_ROT_dec30_cry_in + connect \SHIFT_ROT_dec30_cry_out \SHIFT_ROT_dec30_SHIFT_ROT_dec30_cry_out + connect \SHIFT_ROT_dec30_function_unit \SHIFT_ROT_dec30_SHIFT_ROT_dec30_function_unit + connect \SHIFT_ROT_dec30_in2_sel \SHIFT_ROT_dec30_SHIFT_ROT_dec30_in2_sel + connect \SHIFT_ROT_dec30_internal_op \SHIFT_ROT_dec30_SHIFT_ROT_dec30_internal_op + connect \SHIFT_ROT_dec30_is_32b \SHIFT_ROT_dec30_SHIFT_ROT_dec30_is_32b + connect \SHIFT_ROT_dec30_rc_sel \SHIFT_ROT_dec30_SHIFT_ROT_dec30_rc_sel + connect \SHIFT_ROT_dec30_sgn \SHIFT_ROT_dec30_SHIFT_ROT_dec30_sgn + connect \opcode_in \SHIFT_ROT_dec30_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:62456.19-62468.4" + cell \SHIFT_ROT_dec31 \SHIFT_ROT_dec31 + connect \SHIFT_ROT_dec31_cr_in \SHIFT_ROT_dec31_SHIFT_ROT_dec31_cr_in + connect \SHIFT_ROT_dec31_cr_out \SHIFT_ROT_dec31_SHIFT_ROT_dec31_cr_out + connect \SHIFT_ROT_dec31_cry_in \SHIFT_ROT_dec31_SHIFT_ROT_dec31_cry_in + connect \SHIFT_ROT_dec31_cry_out \SHIFT_ROT_dec31_SHIFT_ROT_dec31_cry_out + connect \SHIFT_ROT_dec31_function_unit \SHIFT_ROT_dec31_SHIFT_ROT_dec31_function_unit + connect \SHIFT_ROT_dec31_in2_sel \SHIFT_ROT_dec31_SHIFT_ROT_dec31_in2_sel + connect \SHIFT_ROT_dec31_internal_op \SHIFT_ROT_dec31_SHIFT_ROT_dec31_internal_op + connect \SHIFT_ROT_dec31_is_32b \SHIFT_ROT_dec31_SHIFT_ROT_dec31_is_32b + connect \SHIFT_ROT_dec31_rc_sel \SHIFT_ROT_dec31_SHIFT_ROT_dec31_rc_sel + connect \SHIFT_ROT_dec31_sgn \SHIFT_ROT_dec31_SHIFT_ROT_dec31_sgn + connect \opcode_in \SHIFT_ROT_dec31_opcode_in + end + attribute \src "libresoc.v:61333.7-61333.20" + process $proc$libresoc.v:61333$3541 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:62469.3-62490.6" + process $proc$libresoc.v:62469$3531 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_cry_out[0:0] $1\SHIFT_ROT_cry_out[0:0] + attribute \src "libresoc.v:62470.5-62470.29" + switch \initial + attribute \src "libresoc.v:62470.9-62470.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\SHIFT_ROT_cry_out[0:0] \SHIFT_ROT_dec30_SHIFT_ROT_dec30_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\SHIFT_ROT_cry_out[0:0] \SHIFT_ROT_dec31_SHIFT_ROT_dec31_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\SHIFT_ROT_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\SHIFT_ROT_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\SHIFT_ROT_cry_out[0:0] 1'0 + case + assign $1\SHIFT_ROT_cry_out[0:0] 1'0 + end + sync always + update \SHIFT_ROT_cry_out $0\SHIFT_ROT_cry_out[0:0] + end + attribute \src "libresoc.v:62491.3-62512.6" + process $proc$libresoc.v:62491$3532 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_is_32b[0:0] $1\SHIFT_ROT_is_32b[0:0] + attribute \src "libresoc.v:62492.5-62492.29" + switch \initial + attribute \src "libresoc.v:62492.9-62492.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\SHIFT_ROT_is_32b[0:0] \SHIFT_ROT_dec30_SHIFT_ROT_dec30_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\SHIFT_ROT_is_32b[0:0] \SHIFT_ROT_dec31_SHIFT_ROT_dec31_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\SHIFT_ROT_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\SHIFT_ROT_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\SHIFT_ROT_is_32b[0:0] 1'1 + case + assign $1\SHIFT_ROT_is_32b[0:0] 1'0 + end + sync always + update \SHIFT_ROT_is_32b $0\SHIFT_ROT_is_32b[0:0] + end + attribute \src "libresoc.v:62513.3-62534.6" + process $proc$libresoc.v:62513$3533 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_sgn[0:0] $1\SHIFT_ROT_sgn[0:0] + attribute \src "libresoc.v:62514.5-62514.29" + switch \initial + attribute \src "libresoc.v:62514.9-62514.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\SHIFT_ROT_sgn[0:0] \SHIFT_ROT_dec30_SHIFT_ROT_dec30_sgn + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\SHIFT_ROT_sgn[0:0] \SHIFT_ROT_dec31_SHIFT_ROT_dec31_sgn + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\SHIFT_ROT_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\SHIFT_ROT_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\SHIFT_ROT_sgn[0:0] 1'0 + case + assign $1\SHIFT_ROT_sgn[0:0] 1'0 + end + sync always + update \SHIFT_ROT_sgn $0\SHIFT_ROT_sgn[0:0] + end + attribute \src "libresoc.v:62535.3-62556.6" + process $proc$libresoc.v:62535$3534 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_function_unit[11:0] $1\SHIFT_ROT_function_unit[11:0] + attribute \src "libresoc.v:62536.5-62536.29" + switch \initial + attribute \src "libresoc.v:62536.9-62536.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\SHIFT_ROT_function_unit[11:0] \SHIFT_ROT_dec30_SHIFT_ROT_dec30_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\SHIFT_ROT_function_unit[11:0] \SHIFT_ROT_dec31_SHIFT_ROT_dec31_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\SHIFT_ROT_function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\SHIFT_ROT_function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\SHIFT_ROT_function_unit[11:0] 12'000000001000 + case + assign $1\SHIFT_ROT_function_unit[11:0] 12'000000000000 + end + sync always + update \SHIFT_ROT_function_unit $0\SHIFT_ROT_function_unit[11:0] + end + attribute \src "libresoc.v:62557.3-62578.6" + process $proc$libresoc.v:62557$3535 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_internal_op[6:0] $1\SHIFT_ROT_internal_op[6:0] + attribute \src "libresoc.v:62558.5-62558.29" + switch \initial + attribute \src "libresoc.v:62558.9-62558.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\SHIFT_ROT_internal_op[6:0] \SHIFT_ROT_dec30_SHIFT_ROT_dec30_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\SHIFT_ROT_internal_op[6:0] \SHIFT_ROT_dec31_SHIFT_ROT_dec31_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\SHIFT_ROT_internal_op[6:0] 7'0111000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\SHIFT_ROT_internal_op[6:0] 7'0111000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\SHIFT_ROT_internal_op[6:0] 7'0111000 + case + assign $1\SHIFT_ROT_internal_op[6:0] 7'0000000 + end + sync always + update \SHIFT_ROT_internal_op $0\SHIFT_ROT_internal_op[6:0] + end + attribute \src "libresoc.v:62579.3-62600.6" + process $proc$libresoc.v:62579$3536 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_in2_sel[3:0] $1\SHIFT_ROT_in2_sel[3:0] + attribute \src "libresoc.v:62580.5-62580.29" + switch \initial + attribute \src "libresoc.v:62580.9-62580.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\SHIFT_ROT_in2_sel[3:0] \SHIFT_ROT_dec30_SHIFT_ROT_dec30_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\SHIFT_ROT_in2_sel[3:0] \SHIFT_ROT_dec31_SHIFT_ROT_dec31_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\SHIFT_ROT_in2_sel[3:0] 4'1011 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\SHIFT_ROT_in2_sel[3:0] 4'1011 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\SHIFT_ROT_in2_sel[3:0] 4'0001 + case + assign $1\SHIFT_ROT_in2_sel[3:0] 4'0000 + end + sync always + update \SHIFT_ROT_in2_sel $0\SHIFT_ROT_in2_sel[3:0] + end + attribute \src "libresoc.v:62601.3-62622.6" + process $proc$libresoc.v:62601$3537 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_cr_in[2:0] $1\SHIFT_ROT_cr_in[2:0] + attribute \src "libresoc.v:62602.5-62602.29" + switch \initial + attribute \src "libresoc.v:62602.9-62602.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\SHIFT_ROT_cr_in[2:0] \SHIFT_ROT_dec30_SHIFT_ROT_dec30_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\SHIFT_ROT_cr_in[2:0] \SHIFT_ROT_dec31_SHIFT_ROT_dec31_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\SHIFT_ROT_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\SHIFT_ROT_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\SHIFT_ROT_cr_in[2:0] 3'000 + case + assign $1\SHIFT_ROT_cr_in[2:0] 3'000 + end + sync always + update \SHIFT_ROT_cr_in $0\SHIFT_ROT_cr_in[2:0] + end + attribute \src "libresoc.v:62623.3-62644.6" + process $proc$libresoc.v:62623$3538 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_cr_out[2:0] $1\SHIFT_ROT_cr_out[2:0] + attribute \src "libresoc.v:62624.5-62624.29" + switch \initial + attribute \src "libresoc.v:62624.9-62624.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\SHIFT_ROT_cr_out[2:0] \SHIFT_ROT_dec30_SHIFT_ROT_dec30_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\SHIFT_ROT_cr_out[2:0] \SHIFT_ROT_dec31_SHIFT_ROT_dec31_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\SHIFT_ROT_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\SHIFT_ROT_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\SHIFT_ROT_cr_out[2:0] 3'000 + case + assign $1\SHIFT_ROT_cr_out[2:0] 3'000 + end + sync always + update \SHIFT_ROT_cr_out $0\SHIFT_ROT_cr_out[2:0] + end + attribute \src "libresoc.v:62645.3-62666.6" + process $proc$libresoc.v:62645$3539 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_rc_sel[1:0] $1\SHIFT_ROT_rc_sel[1:0] + attribute \src "libresoc.v:62646.5-62646.29" + switch \initial + attribute \src "libresoc.v:62646.9-62646.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\SHIFT_ROT_rc_sel[1:0] \SHIFT_ROT_dec30_SHIFT_ROT_dec30_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\SHIFT_ROT_rc_sel[1:0] \SHIFT_ROT_dec31_SHIFT_ROT_dec31_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\SHIFT_ROT_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\SHIFT_ROT_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\SHIFT_ROT_rc_sel[1:0] 2'10 + case + assign $1\SHIFT_ROT_rc_sel[1:0] 2'00 + end + sync always + update \SHIFT_ROT_rc_sel $0\SHIFT_ROT_rc_sel[1:0] + end + attribute \src "libresoc.v:62667.3-62688.6" + process $proc$libresoc.v:62667$3540 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_cry_in[1:0] $1\SHIFT_ROT_cry_in[1:0] + attribute \src "libresoc.v:62668.5-62668.29" + switch \initial + attribute \src "libresoc.v:62668.9-62668.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\SHIFT_ROT_cry_in[1:0] \SHIFT_ROT_dec30_SHIFT_ROT_dec30_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\SHIFT_ROT_cry_in[1:0] \SHIFT_ROT_dec31_SHIFT_ROT_dec31_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\SHIFT_ROT_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\SHIFT_ROT_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\SHIFT_ROT_cry_in[1:0] 2'00 + case + assign $1\SHIFT_ROT_cry_in[1:0] 2'00 + end + sync always + update \SHIFT_ROT_cry_in $0\SHIFT_ROT_cry_in[1:0] + end + connect \$1 $ternary$libresoc.v:62442$3530_Y + connect \VC_XO \opcode_in [9:0] + connect \VC_VRT \opcode_in [25:21] + connect \VC_VRB \opcode_in [15:11] + connect \VC_VRA \opcode_in [20:16] + connect \VC_Rc \opcode_in [10] + connect \XS_XO \opcode_in [10:2] + connect \XS_sh { \opcode_in [1] \opcode_in [15:11] } + connect \XS_RS \opcode_in [25:21] + connect \XS_Rc \opcode_in [0] + connect \XS_RA \opcode_in [20:16] + connect \VA_XO \opcode_in [5:0] + connect \VA_VRT \opcode_in [25:21] + connect \VA_VRC \opcode_in [10:6] + connect \VA_VRB \opcode_in [15:11] + connect \VA_VRA \opcode_in [20:16] + connect \VA_SHB \opcode_in [9:6] + connect \VA_RT \opcode_in [25:21] + connect \VA_RC \opcode_in [10:6] + connect \VA_RB \opcode_in [15:11] + connect \VA_RA \opcode_in [20:16] + connect \TX_XO \opcode_in [6:1] + connect \TX_XBI \opcode_in [10:7] + connect \TX_UI \opcode_in [15:11] + connect \TX_RA \opcode_in [20:16] + connect \DQE_XO \opcode_in [1:0] + connect \DQE_RT \opcode_in [25:21] + connect \DQE_RA \opcode_in [20:16] + connect \XO_XO \opcode_in [9:1] + connect \XO_RT \opcode_in [25:21] + connect \XO_Rc \opcode_in [0] + connect \XO_RB \opcode_in [15:11] + connect \XO_RA \opcode_in [20:16] + connect \XO_OE \opcode_in [10] + connect \all_PO \opcode_in [31:26] + connect \all_OPCD \opcode_in [31:26] + connect \MD_XO \opcode_in [4:2] + connect \MD_sh { \opcode_in [1] \opcode_in [15:11] } + connect \MD_RS \opcode_in [25:21] + connect \MD_Rc \opcode_in [0] + connect \MD_RA \opcode_in [20:16] + connect \MD_me \opcode_in [10:5] + connect \MD_mb \opcode_in [10:5] + connect \M_SH \opcode_in [15:11] + connect \M_RS \opcode_in [25:21] + connect \M_Rc \opcode_in [0] + connect \M_RB \opcode_in [15:11] + connect \M_RA \opcode_in [20:16] + connect \M_ME \opcode_in [5:1] + connect \M_MB \opcode_in [10:6] + connect \SC_XO_1 \opcode_in [1:0] + connect \SC_XO \opcode_in [1] + connect \SC_LEV \opcode_in [11:5] + connect \MDS_XO \opcode_in [4:1] + connect \MDS_XBI_1 \opcode_in [10:7] + connect \MDS_XBI \opcode_in [10:7] + connect \MDS_RS \opcode_in [25:21] + connect \MDS_Rc \opcode_in [0] + connect \MDS_RB \opcode_in [15:11] + connect \MDS_RA \opcode_in [20:16] + connect \MDS_me \opcode_in [10:5] + connect \MDS_mb \opcode_in [10:5] + connect \MDS_IS \opcode_in [25:21] + connect \MDS_IB \opcode_in [15:11] + connect \Z23_XO \opcode_in [8:1] + connect \Z23_TE \opcode_in [20:16] + connect \Z23_RMC \opcode_in [10:9] + connect \Z23_Rc \opcode_in [0] + connect \Z23_R \opcode_in [16] + connect \Z23_FRTp \opcode_in [25:21] + connect \Z23_FRT \opcode_in [25:21] + connect \Z23_FRBp \opcode_in [15:11] + connect \Z23_FRB \opcode_in [15:11] + connect \Z23_FRAp \opcode_in [20:16] + connect \Z23_FRA \opcode_in [20:16] + connect \XFL_XO \opcode_in [10:1] + connect \XFL_W \opcode_in [16] + connect \XFL_Rc \opcode_in [0] + connect \XFL_L \opcode_in [25] + connect \XFL_FRB \opcode_in [15:11] + connect \XFL_FLM \opcode_in [24:17] + connect \VX_XO_1 \opcode_in [10:0] + connect \VX_XO { \opcode_in [10] \opcode_in [8:0] } + connect \VX_VRT \opcode_in [25:21] + connect \VX_VRB \opcode_in [15:11] + connect \VX_VRA \opcode_in [20:16] + connect \VX_UIM_3 \opcode_in [17:16] + connect \VX_UIM_2 \opcode_in [18:16] + connect \VX_UIM_1 \opcode_in [19:16] + connect \VX_UIM \opcode_in [20:16] + connect \VX_SIM \opcode_in [20:16] + connect \VX_RT \opcode_in [25:21] + connect \VX_RA \opcode_in [20:16] + connect \VX_PS \opcode_in [9] + connect \VX_EO \opcode_in [20:16] + connect \DS_XO \opcode_in [1:0] + connect \DS_VRT \opcode_in [25:21] + connect \DS_VRS \opcode_in [25:21] + connect \DS_RT \opcode_in [25:21] + connect \DS_RSp \opcode_in [25:21] + connect \DS_RS \opcode_in [25:21] + connect \DS_RA \opcode_in [20:16] + connect \DS_FRTp \opcode_in [25:21] + connect \DS_FRSp \opcode_in [25:21] + connect \DS_DS \opcode_in [15:2] + connect \DQ_XO \opcode_in [2:0] + connect \DQ_TX_T { \opcode_in [3] \opcode_in [25:21] } + connect \DQ_T \opcode_in [25:21] + connect \DQ_TX \opcode_in [3] + connect \DQ_SX_S { \opcode_in [3] \opcode_in [25:21] } + connect \DQ_S \opcode_in [25:21] + connect \DQ_SX \opcode_in [3] + connect \DQ_RTp \opcode_in [25:21] + connect \DQ_RA \opcode_in [20:16] + connect \DQ_PT \opcode_in [3:0] + connect \DQ_DQ \opcode_in [15:4] + connect \DX_XO \opcode_in [5:1] + connect \DX_RT \opcode_in [25:21] + connect \DX_d0_d1_d2 { \opcode_in [15:6] \opcode_in [20:16] \opcode_in [0] } + connect \DX_d2 \opcode_in [0] + connect \DX_d1 \opcode_in [20:16] + connect \DX_d0 \opcode_in [15:6] + connect \XFX_XO \opcode_in [10:1] + connect \XFX_SPR \opcode_in [20:11] + connect \XFX_RT \opcode_in [25:21] + connect \XFX_RS \opcode_in [25:21] + connect \XFX_FXM \opcode_in [19:12] + connect \XFX_DUIS \opcode_in [20:11] + connect \XFX_DUI \opcode_in [25:21] + connect \XFX_BHRBE \opcode_in [20:11] + connect \EVS_BFA \opcode_in [2:0] + connect \Z22_XO \opcode_in [9:1] + connect \Z22_SH \opcode_in [15:10] + connect \Z22_Rc \opcode_in [0] + connect \Z22_FRTp \opcode_in [25:21] + connect \Z22_FRT \opcode_in [25:21] + connect \Z22_FRAp \opcode_in [20:16] + connect \Z22_FRA \opcode_in [20:16] + connect \Z22_DGM \opcode_in [15:10] + connect \Z22_DCM \opcode_in [15:10] + connect \Z22_BF \opcode_in [25:23] + connect \XX2_XO_1 \opcode_in [10:2] + connect \XX2_XO { \opcode_in [10:7] \opcode_in [5:3] } + connect \XX2_UIM_1 \opcode_in [17:16] + connect \XX2_UIM \opcode_in [19:16] + connect \XX2_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX2_T \opcode_in [25:21] + connect \XX2_TX \opcode_in [0] + connect \XX2_RT \opcode_in [25:21] + connect \XX2_EO \opcode_in [20:16] + connect \XX2_DCMX \opcode_in [22:16] + connect \XX2_dc_dm_dx { \opcode_in [6] \opcode_in [2] \opcode_in [20:16] } + connect \XX2_dx \opcode_in [20:16] + connect \XX2_dm \opcode_in [2] + connect \XX2_dc \opcode_in [6] + connect \XX2_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX2_B \opcode_in [15:11] + connect \XX2_BX \opcode_in [1] + connect \XX2_BF \opcode_in [25:23] + connect \D_UI \opcode_in [15:0] + connect \D_TO \opcode_in [25:21] + connect \D_SI \opcode_in [15:0] + connect \D_RT \opcode_in [25:21] + connect \D_RS \opcode_in [25:21] + connect \D_RA \opcode_in [20:16] + connect \D_L \opcode_in [21] + connect \D_FRT \opcode_in [25:21] + connect \D_FRS \opcode_in [25:21] + connect \D_D \opcode_in [15:0] + connect \D_BF \opcode_in [25:23] + connect \A_XO \opcode_in [5:1] + connect \A_RT \opcode_in [25:21] + connect \A_Rc \opcode_in [0] + connect \A_RB \opcode_in [15:11] + connect \A_RA \opcode_in [20:16] + connect \A_FRT \opcode_in [25:21] + connect \A_FRC \opcode_in [10:6] + connect \A_FRB \opcode_in [15:11] + connect \A_FRA \opcode_in [20:16] + connect \A_BC \opcode_in [10:6] + connect \XL_XO \opcode_in [10:1] + connect \XL_S \opcode_in [11] + connect \XL_OC \opcode_in [25:11] + connect \XL_LK \opcode_in [0] + connect \XL_BT \opcode_in [25:21] + connect \XL_BO_1 \opcode_in [25:21] + connect \XL_BO \opcode_in [25:21] + connect \XL_BI \opcode_in [20:16] + connect \XL_BH \opcode_in [12:11] + connect \XL_BFA \opcode_in [20:18] + connect \XL_BF \opcode_in [25:23] + connect \XL_BB \opcode_in [15:11] + connect \XL_BA \opcode_in [20:16] + connect \XX4_XO \opcode_in [5:4] + connect \XX4_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX4_T \opcode_in [25:21] + connect \XX4_TX \opcode_in [0] + connect \XX4_CX_C { \opcode_in [3] \opcode_in [10:6] } + connect \XX4_C \opcode_in [10:6] + connect \XX4_CX \opcode_in [3] + connect \XX4_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX4_B \opcode_in [15:11] + connect \XX4_BX \opcode_in [1] + connect \XX4_AX_A { \opcode_in [2] \opcode_in [20:16] } + connect \XX4_A \opcode_in [20:16] + connect \XX4_AX \opcode_in [2] + connect \XX3_XO_2 \opcode_in [9:1] + connect \XX3_XO_1 \opcode_in [10:3] + connect \XX3_XO \opcode_in [10:7] + connect \XX3_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX3_T \opcode_in [25:21] + connect \XX3_TX \opcode_in [0] + connect \XX3_SHW \opcode_in [9:8] + connect \XX3_Rc \opcode_in [10] + connect \XX3_DM \opcode_in [9:8] + connect \XX3_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX3_B \opcode_in [15:11] + connect \XX3_BX \opcode_in [1] + connect \XX3_BF \opcode_in [25:23] + connect \XX3_AX_A { \opcode_in [2] \opcode_in [20:16] } + connect \XX3_A \opcode_in [20:16] + connect \XX3_AX \opcode_in [2] + connect \I_LK \opcode_in [0] + connect \I_LI \opcode_in [25:2] + connect \I_AA \opcode_in [1] + connect \B_LK \opcode_in [0] + connect \B_BO \opcode_in [25:21] + connect \B_BI \opcode_in [20:16] + connect \B_BD \opcode_in [15:2] + connect \B_AA \opcode_in [1] + connect \X_XO_1 \opcode_in [8:1] + connect \X_XO \opcode_in [10:1] + connect \X_WC \opcode_in [22:21] + connect \X_W \opcode_in [16] + connect \X_VRT \opcode_in [25:21] + connect \X_VRS \opcode_in [25:21] + connect \X_UIM \opcode_in [20:16] + connect \X_U \opcode_in [15:12] + connect \X_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \X_TX \opcode_in [0] + connect \X_TO \opcode_in [25:21] + connect \X_TH \opcode_in [25:21] + connect \X_TBR \opcode_in [20:11] + connect \X_T \opcode_in [25:21] + connect \X_SX_S { \opcode_in [0] \opcode_in [25:21] } + connect \X_SX \opcode_in [0] + connect \X_SR \opcode_in [19:16] + connect \X_SP \opcode_in [20:19] + connect \X_SI \opcode_in [15:11] + connect \X_SH \opcode_in [15:11] + connect \X_S \opcode_in [25:21] + connect \X_RTp \opcode_in [25:21] + connect \X_RT \opcode_in [25:21] + connect \X_RSp \opcode_in [25:21] + connect \X_RS \opcode_in [25:21] + connect \X_RO \opcode_in [0] + connect \X_RM \opcode_in [12:11] + connect \X_RIC \opcode_in [19:18] + connect \X_Rc \opcode_in [0] + connect \X_RB \opcode_in [15:11] + connect \X_RA \opcode_in [20:16] + connect \X_R_1 \opcode_in [16] + connect \X_R \opcode_in [21] + connect \X_PRS \opcode_in [17] + connect \X_NB \opcode_in [15:11] + connect \X_MO \opcode_in [25:21] + connect \X_L3 \opcode_in [17:16] + connect \X_L1 \opcode_in [16] + connect \X_L \opcode_in [21] + connect \X_L2 \opcode_in [22:21] + connect \X_IMM8 \opcode_in [18:11] + connect \X_IH \opcode_in [23:21] + connect \X_FRTp \opcode_in [25:21] + connect \X_FRT \opcode_in [25:21] + connect \X_FRSp \opcode_in [25:21] + connect \X_FRS \opcode_in [25:21] + connect \X_FRBp \opcode_in [15:11] + connect \X_FRB \opcode_in [15:11] + connect \X_FRAp \opcode_in [20:16] + connect \X_FRA \opcode_in [20:16] + connect \X_FC \opcode_in [15:11] + connect \X_EX \opcode_in [0] + connect \X_EO_1 \opcode_in [20:16] + connect \X_EO \opcode_in [20:19] + connect \X_E_1 \opcode_in [19:16] + connect \X_E \opcode_in [15] + connect \X_DRM \opcode_in [13:11] + connect \X_DCMX \opcode_in [22:16] + connect \X_CT \opcode_in [24:21] + connect \X_BO \opcode_in [25:21] + connect \X_BFA \opcode_in [20:18] + connect \X_BF \opcode_in [25:23] + connect \X_A \opcode_in [25] + connect \SHIFT_ROT_SPR \opcode_in [20:11] + connect \SHIFT_ROT_MB \opcode_in [10:6] + connect \SHIFT_ROT_ME \opcode_in [5:1] + connect \SHIFT_ROT_SH \opcode_in [15:11] + connect \SHIFT_ROT_BC \opcode_in [10:6] + connect \SHIFT_ROT_TO \opcode_in [25:21] + connect \SHIFT_ROT_DS \opcode_in [15:2] + connect \SHIFT_ROT_D \opcode_in [15:0] + connect \SHIFT_ROT_BH \opcode_in [12:11] + connect \SHIFT_ROT_BI \opcode_in [20:16] + connect \SHIFT_ROT_BO \opcode_in [25:21] + connect \SHIFT_ROT_FXM \opcode_in [19:12] + connect \SHIFT_ROT_BT \opcode_in [25:21] + connect \SHIFT_ROT_BA \opcode_in [20:16] + connect \SHIFT_ROT_BB \opcode_in [15:11] + connect \SHIFT_ROT_CR \opcode_in [10:1] + connect \SHIFT_ROT_BF \opcode_in [25:23] + connect \SHIFT_ROT_BD \opcode_in [15:2] + connect \SHIFT_ROT_OE \opcode_in [10] + connect \SHIFT_ROT_Rc \opcode_in [0] + connect \SHIFT_ROT_AA \opcode_in [1] + connect \SHIFT_ROT_LK \opcode_in [0] + connect \SHIFT_ROT_LI \opcode_in [25:2] + connect \SHIFT_ROT_ME32 \opcode_in [5:1] + connect \SHIFT_ROT_MB32 \opcode_in [10:6] + connect \SHIFT_ROT_sh { \opcode_in [1] \opcode_in [15:11] } + connect \SHIFT_ROT_SH32 \opcode_in [15:11] + connect \SHIFT_ROT_L \opcode_in [21] + connect \SHIFT_ROT_UI \opcode_in [15:0] + connect \SHIFT_ROT_SI \opcode_in [15:0] + connect \SHIFT_ROT_RB \opcode_in [15:11] + connect \SHIFT_ROT_RA \opcode_in [20:16] + connect \SHIFT_ROT_RT \opcode_in [25:21] + connect \SHIFT_ROT_RS \opcode_in [25:21] + connect \opcode_in \$1 + connect \SHIFT_ROT_dec31_opcode_in \opcode_in + connect \SHIFT_ROT_dec30_opcode_in \opcode_in + connect \opcode_switch \opcode_in [31:26] +end +attribute \src "libresoc.v:63023.1-65492.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_LDST.dec" +attribute \generator "nMigen" +module \dec$193 + attribute \src "libresoc.v:64581.3-64638.6" + wire $0\LDST_br[0:0] + attribute \src "libresoc.v:65045.3-65102.6" + wire width 3 $0\LDST_cr_in[2:0] + attribute \src "libresoc.v:65103.3-65160.6" + wire width 3 $0\LDST_cr_out[2:0] + attribute \src "libresoc.v:64813.3-64870.6" + wire width 12 $0\LDST_function_unit[11:0] + attribute \src "libresoc.v:64929.3-64986.6" + wire width 3 $0\LDST_in1_sel[2:0] + attribute \src "libresoc.v:64987.3-65044.6" + wire width 4 $0\LDST_in2_sel[3:0] + attribute \src "libresoc.v:64871.3-64928.6" + wire width 7 $0\LDST_internal_op[6:0] + attribute \src "libresoc.v:64697.3-64754.6" + wire $0\LDST_is_32b[0:0] + attribute \src "libresoc.v:64407.3-64464.6" + wire width 4 $0\LDST_ldst_len[3:0] + attribute \src "libresoc.v:64523.3-64580.6" + wire width 2 $0\LDST_rc_sel[1:0] + attribute \src "libresoc.v:64755.3-64812.6" + wire $0\LDST_sgn[0:0] + attribute \src "libresoc.v:64639.3-64696.6" + wire $0\LDST_sgn_ext[0:0] + attribute \src "libresoc.v:64465.3-64522.6" + wire width 2 $0\LDST_upd[1:0] + attribute \src "libresoc.v:63024.7-63024.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:64581.3-64638.6" + wire $1\LDST_br[0:0] + attribute \src "libresoc.v:65045.3-65102.6" + wire width 3 $1\LDST_cr_in[2:0] + attribute \src "libresoc.v:65103.3-65160.6" + wire width 3 $1\LDST_cr_out[2:0] + attribute \src "libresoc.v:64813.3-64870.6" + wire width 12 $1\LDST_function_unit[11:0] + attribute \src "libresoc.v:64929.3-64986.6" + wire width 3 $1\LDST_in1_sel[2:0] + attribute \src "libresoc.v:64987.3-65044.6" + wire width 4 $1\LDST_in2_sel[3:0] + attribute \src "libresoc.v:64871.3-64928.6" + wire width 7 $1\LDST_internal_op[6:0] + attribute \src "libresoc.v:64697.3-64754.6" + wire $1\LDST_is_32b[0:0] + attribute \src "libresoc.v:64407.3-64464.6" + wire width 4 $1\LDST_ldst_len[3:0] + attribute \src "libresoc.v:64523.3-64580.6" + wire width 2 $1\LDST_rc_sel[1:0] + attribute \src "libresoc.v:64755.3-64812.6" + wire $1\LDST_sgn[0:0] + attribute \src "libresoc.v:64639.3-64696.6" + wire $1\LDST_sgn_ext[0:0] + attribute \src "libresoc.v:64465.3-64522.6" + wire width 2 $1\LDST_upd[1:0] + attribute \src "libresoc.v:64358.17-64358.211" + wire width 32 $ternary$libresoc.v:64358$3542_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:478" + wire width 32 \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_FRC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \A_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \B_AA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 14 \B_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \B_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \B_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \B_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DQE_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DQE_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \DQE_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 12 \DQ_DQ + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \DQ_PT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DQ_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DQ_RTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DQ_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \DQ_SX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \DQ_SX_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DQ_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \DQ_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \DQ_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \DQ_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 14 \DS_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_FRSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_RSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_VRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \DS_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DX_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \DX_d0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 16 \DX_d0_d1_d2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DX_d1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \DX_d2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \D_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 16 \D_D + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \D_FRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \D_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \D_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \D_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \D_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \D_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 16 \D_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \D_TO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 16 \D_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \EVS_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \I_AA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 24 \I_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \I_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire \LDST_AA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 output 26 \LDST_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 output 25 \LDST_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 output 31 \LDST_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 14 output 24 \LDST_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 3 \LDST_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 2 \LDST_BH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 output 29 \LDST_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \LDST_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 output 27 \LDST_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 10 \LDST_CR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 16 \LDST_D + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 14 output 30 \LDST_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 8 output 28 \LDST_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire \LDST_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 24 output 21 \LDST_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire \LDST_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \LDST_MB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \LDST_MB32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \LDST_ME + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \LDST_ME32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire output 23 \LDST_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 output 16 \LDST_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \LDST_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \LDST_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \LDST_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire output 22 \LDST_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \LDST_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 output 19 \LDST_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 16 output 17 \LDST_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 10 \LDST_SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \LDST_TO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 16 output 18 \LDST_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 13 \LDST_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 4 \LDST_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \LDST_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \LDST_dec31_LDST_dec31_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \LDST_dec31_LDST_dec31_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \LDST_dec31_LDST_dec31_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \LDST_dec31_LDST_dec31_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \LDST_dec31_LDST_dec31_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \LDST_dec31_LDST_dec31_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 \LDST_dec31_LDST_dec31_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \LDST_dec31_LDST_dec31_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \LDST_dec31_LDST_dec31_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \LDST_dec31_LDST_dec31_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \LDST_dec31_LDST_dec31_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \LDST_dec31_LDST_dec31_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \LDST_dec31_LDST_dec31_upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \LDST_dec31_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \LDST_dec58_LDST_dec58_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \LDST_dec58_LDST_dec58_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \LDST_dec58_LDST_dec58_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \LDST_dec58_LDST_dec58_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \LDST_dec58_LDST_dec58_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \LDST_dec58_LDST_dec58_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 \LDST_dec58_LDST_dec58_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \LDST_dec58_LDST_dec58_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \LDST_dec58_LDST_dec58_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \LDST_dec58_LDST_dec58_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \LDST_dec58_LDST_dec58_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \LDST_dec58_LDST_dec58_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \LDST_dec58_LDST_dec58_upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \LDST_dec58_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \LDST_dec62_LDST_dec62_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \LDST_dec62_LDST_dec62_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \LDST_dec62_LDST_dec62_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \LDST_dec62_LDST_dec62_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \LDST_dec62_LDST_dec62_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \LDST_dec62_LDST_dec62_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 \LDST_dec62_LDST_dec62_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \LDST_dec62_LDST_dec62_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \LDST_dec62_LDST_dec62_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \LDST_dec62_LDST_dec62_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \LDST_dec62_LDST_dec62_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \LDST_dec62_LDST_dec62_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \LDST_dec62_LDST_dec62_upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \LDST_dec62_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 7 \LDST_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 8 \LDST_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 9 \LDST_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 6 \LDST_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 11 \LDST_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 10 \LDST_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 3 \LDST_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 12 \LDST_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 14 \LDST_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 6 output 20 \LDST_sh + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 15 \LDST_upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MDS_IB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MDS_IS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MDS_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MDS_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MDS_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \MDS_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \MDS_XBI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \MDS_XBI_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \MDS_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \MDS_mb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \MDS_me + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MD_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MD_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \MD_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \MD_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \MD_mb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \MD_me + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \MD_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \M_MB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \M_ME + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \M_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \M_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \M_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \M_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \M_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 7 \SC_LEV + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \SC_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \SC_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \TX_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \TX_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \TX_XBI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \TX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_RC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \VA_SHB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_VRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_VRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_VRC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \VA_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \VC_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VC_VRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VC_VRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VC_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \VC_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_EO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \VX_PS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_SIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_UIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \VX_UIM_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \VX_UIM_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \VX_UIM_3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_VRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_VRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \VX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 11 \VX_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 8 \XFL_FLM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XFL_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XFL_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XFL_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XFL_W + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \XFL_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \XFX_BHRBE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XFX_DUI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \XFX_DUIS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 8 \XFX_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XFX_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XFX_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \XFX_SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \XFX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XL_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XL_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \XL_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \XL_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \XL_BH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XL_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XL_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XL_BO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 output 34 \XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XL_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 15 \XL_OC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XL_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \XL_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XO_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XO_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XO_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XO_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XO_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 9 \XO_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XS_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XS_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XS_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 9 \XS_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XS_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX2_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \XX2_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX2_BX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX2_BX_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 7 \XX2_DCMX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX2_EO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX2_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX2_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX2_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX2_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \XX2_UIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \XX2_UIM_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 7 \XX2_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 9 \XX2_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX2_dc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 7 \XX2_dc_dm_dx + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX2_dm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX2_dx + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX3_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX3_AX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX3_AX_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX3_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \XX3_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX3_BX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX3_BX_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \XX3_DM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX3_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \XX3_SHW + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX3_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX3_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX3_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \XX3_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 8 \XX3_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 9 \XX3_XO_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX4_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX4_AX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX4_AX_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX4_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX4_BX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX4_BX_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX4_C + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX4_CX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX4_CX_C + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX4_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX4_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX4_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \XX4_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 output 32 \X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 output 33 \X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \X_CT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 7 \X_DCMX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \X_DRM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_E + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \X_EO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_EO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_EX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \X_E_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRAp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRBp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \X_IH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 8 \X_IMM8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_L1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \X_L2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \X_L3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_MO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_NB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_PRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_R + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \X_RIC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \X_RM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_RO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_RSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_RTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_R_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \X_SP + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \X_SR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_SX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \X_SX_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \X_TBR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_TH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_TO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \X_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \X_U + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_UIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_VRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_W + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \X_WC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \X_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 8 \X_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \Z22_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \Z22_DCM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \Z22_DGM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z22_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z22_FRAp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z22_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z22_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \Z22_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \Z22_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 9 \Z22_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_FRAp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_FRBp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \Z23_R + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \Z23_RMC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \Z23_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_TE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 8 \Z23_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \all_OPCD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \all_PO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + wire input 1 \bigendian + attribute \src "libresoc.v:63024.7-63024.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 output 2 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 6 \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:442" + wire width 32 input 35 \raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:478" + cell $mux $ternary$libresoc.v:64358$3542 + parameter \WIDTH 32 + connect \A \raw_opcode_in + connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } + connect \S \bigendian + connect \Y $ternary$libresoc.v:64358$3542_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:64359.14-64374.4" + cell \LDST_dec31 \LDST_dec31 + connect \LDST_dec31_br \LDST_dec31_LDST_dec31_br + connect \LDST_dec31_cr_in \LDST_dec31_LDST_dec31_cr_in + connect \LDST_dec31_cr_out \LDST_dec31_LDST_dec31_cr_out + connect \LDST_dec31_function_unit \LDST_dec31_LDST_dec31_function_unit + connect \LDST_dec31_in1_sel \LDST_dec31_LDST_dec31_in1_sel + connect \LDST_dec31_in2_sel \LDST_dec31_LDST_dec31_in2_sel + connect \LDST_dec31_internal_op \LDST_dec31_LDST_dec31_internal_op + connect \LDST_dec31_is_32b \LDST_dec31_LDST_dec31_is_32b + connect \LDST_dec31_ldst_len \LDST_dec31_LDST_dec31_ldst_len + connect \LDST_dec31_rc_sel \LDST_dec31_LDST_dec31_rc_sel + connect \LDST_dec31_sgn \LDST_dec31_LDST_dec31_sgn + connect \LDST_dec31_sgn_ext \LDST_dec31_LDST_dec31_sgn_ext + connect \LDST_dec31_upd \LDST_dec31_LDST_dec31_upd + connect \opcode_in \LDST_dec31_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:64375.14-64390.4" + cell \LDST_dec58 \LDST_dec58 + connect \LDST_dec58_br \LDST_dec58_LDST_dec58_br + connect \LDST_dec58_cr_in \LDST_dec58_LDST_dec58_cr_in + connect \LDST_dec58_cr_out \LDST_dec58_LDST_dec58_cr_out + connect \LDST_dec58_function_unit \LDST_dec58_LDST_dec58_function_unit + connect \LDST_dec58_in1_sel \LDST_dec58_LDST_dec58_in1_sel + connect \LDST_dec58_in2_sel \LDST_dec58_LDST_dec58_in2_sel + connect \LDST_dec58_internal_op \LDST_dec58_LDST_dec58_internal_op + connect \LDST_dec58_is_32b \LDST_dec58_LDST_dec58_is_32b + connect \LDST_dec58_ldst_len \LDST_dec58_LDST_dec58_ldst_len + connect \LDST_dec58_rc_sel \LDST_dec58_LDST_dec58_rc_sel + connect \LDST_dec58_sgn \LDST_dec58_LDST_dec58_sgn + connect \LDST_dec58_sgn_ext \LDST_dec58_LDST_dec58_sgn_ext + connect \LDST_dec58_upd \LDST_dec58_LDST_dec58_upd + connect \opcode_in \LDST_dec58_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:64391.14-64406.4" + cell \LDST_dec62 \LDST_dec62 + connect \LDST_dec62_br \LDST_dec62_LDST_dec62_br + connect \LDST_dec62_cr_in \LDST_dec62_LDST_dec62_cr_in + connect \LDST_dec62_cr_out \LDST_dec62_LDST_dec62_cr_out + connect \LDST_dec62_function_unit \LDST_dec62_LDST_dec62_function_unit + connect \LDST_dec62_in1_sel \LDST_dec62_LDST_dec62_in1_sel + connect \LDST_dec62_in2_sel \LDST_dec62_LDST_dec62_in2_sel + connect \LDST_dec62_internal_op \LDST_dec62_LDST_dec62_internal_op + connect \LDST_dec62_is_32b \LDST_dec62_LDST_dec62_is_32b + connect \LDST_dec62_ldst_len \LDST_dec62_LDST_dec62_ldst_len + connect \LDST_dec62_rc_sel \LDST_dec62_LDST_dec62_rc_sel + connect \LDST_dec62_sgn \LDST_dec62_LDST_dec62_sgn + connect \LDST_dec62_sgn_ext \LDST_dec62_LDST_dec62_sgn_ext + connect \LDST_dec62_upd \LDST_dec62_LDST_dec62_upd + connect \opcode_in \LDST_dec62_opcode_in + end + attribute \src "libresoc.v:63024.7-63024.20" + process $proc$libresoc.v:63024$3556 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:64407.3-64464.6" + process $proc$libresoc.v:64407$3543 + assign { } { } + assign { } { } + assign $0\LDST_ldst_len[3:0] $1\LDST_ldst_len[3:0] + attribute \src "libresoc.v:64408.5-64408.29" + switch \initial + attribute \src "libresoc.v:64408.9-64408.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\LDST_ldst_len[3:0] \LDST_dec31_LDST_dec31_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\LDST_ldst_len[3:0] \LDST_dec58_LDST_dec58_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\LDST_ldst_len[3:0] \LDST_dec62_LDST_dec62_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\LDST_ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\LDST_ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\LDST_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\LDST_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\LDST_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\LDST_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\LDST_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\LDST_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\LDST_ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\LDST_ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\LDST_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\LDST_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\LDST_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\LDST_ldst_len[3:0] 4'0100 + case + assign $1\LDST_ldst_len[3:0] 4'0000 + end + sync always + update \LDST_ldst_len $0\LDST_ldst_len[3:0] + end + attribute \src "libresoc.v:64465.3-64522.6" + process $proc$libresoc.v:64465$3544 + assign { } { } + assign { } { } + assign $0\LDST_upd[1:0] $1\LDST_upd[1:0] + attribute \src "libresoc.v:64466.5-64466.29" + switch \initial + attribute \src "libresoc.v:64466.9-64466.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\LDST_upd[1:0] \LDST_dec31_LDST_dec31_upd + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\LDST_upd[1:0] \LDST_dec58_LDST_dec58_upd + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\LDST_upd[1:0] \LDST_dec62_LDST_dec62_upd + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\LDST_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\LDST_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\LDST_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\LDST_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\LDST_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\LDST_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\LDST_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\LDST_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\LDST_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\LDST_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\LDST_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\LDST_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\LDST_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\LDST_upd[1:0] 2'01 + case + assign $1\LDST_upd[1:0] 2'00 + end + sync always + update \LDST_upd $0\LDST_upd[1:0] + end + attribute \src "libresoc.v:64523.3-64580.6" + process $proc$libresoc.v:64523$3545 + assign { } { } + assign { } { } + assign $0\LDST_rc_sel[1:0] $1\LDST_rc_sel[1:0] + attribute \src "libresoc.v:64524.5-64524.29" + switch \initial + attribute \src "libresoc.v:64524.9-64524.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\LDST_rc_sel[1:0] \LDST_dec31_LDST_dec31_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\LDST_rc_sel[1:0] \LDST_dec58_LDST_dec58_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\LDST_rc_sel[1:0] \LDST_dec62_LDST_dec62_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\LDST_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\LDST_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\LDST_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\LDST_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\LDST_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\LDST_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\LDST_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\LDST_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\LDST_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\LDST_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\LDST_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\LDST_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\LDST_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\LDST_rc_sel[1:0] 2'00 + case + assign $1\LDST_rc_sel[1:0] 2'00 + end + sync always + update \LDST_rc_sel $0\LDST_rc_sel[1:0] + end + attribute \src "libresoc.v:64581.3-64638.6" + process $proc$libresoc.v:64581$3546 + assign { } { } + assign { } { } + assign $0\LDST_br[0:0] $1\LDST_br[0:0] + attribute \src "libresoc.v:64582.5-64582.29" + switch \initial + attribute \src "libresoc.v:64582.9-64582.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\LDST_br[0:0] \LDST_dec31_LDST_dec31_br + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\LDST_br[0:0] \LDST_dec58_LDST_dec58_br + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\LDST_br[0:0] \LDST_dec62_LDST_dec62_br + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\LDST_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\LDST_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\LDST_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\LDST_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\LDST_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\LDST_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\LDST_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\LDST_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\LDST_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\LDST_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\LDST_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\LDST_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\LDST_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\LDST_br[0:0] 1'0 + case + assign $1\LDST_br[0:0] 1'0 + end + sync always + update \LDST_br $0\LDST_br[0:0] + end + attribute \src "libresoc.v:64639.3-64696.6" + process $proc$libresoc.v:64639$3547 + assign { } { } + assign { } { } + assign $0\LDST_sgn_ext[0:0] $1\LDST_sgn_ext[0:0] + attribute \src "libresoc.v:64640.5-64640.29" + switch \initial + attribute \src "libresoc.v:64640.9-64640.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\LDST_sgn_ext[0:0] \LDST_dec31_LDST_dec31_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\LDST_sgn_ext[0:0] \LDST_dec58_LDST_dec58_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\LDST_sgn_ext[0:0] \LDST_dec62_LDST_dec62_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\LDST_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\LDST_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\LDST_sgn_ext[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\LDST_sgn_ext[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\LDST_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\LDST_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\LDST_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\LDST_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\LDST_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\LDST_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\LDST_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\LDST_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\LDST_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\LDST_sgn_ext[0:0] 1'0 + case + assign $1\LDST_sgn_ext[0:0] 1'0 + end + sync always + update \LDST_sgn_ext $0\LDST_sgn_ext[0:0] + end + attribute \src "libresoc.v:64697.3-64754.6" + process $proc$libresoc.v:64697$3548 + assign { } { } + assign { } { } + assign $0\LDST_is_32b[0:0] $1\LDST_is_32b[0:0] + attribute \src "libresoc.v:64698.5-64698.29" + switch \initial + attribute \src "libresoc.v:64698.9-64698.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\LDST_is_32b[0:0] \LDST_dec31_LDST_dec31_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\LDST_is_32b[0:0] \LDST_dec58_LDST_dec58_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\LDST_is_32b[0:0] \LDST_dec62_LDST_dec62_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\LDST_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\LDST_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\LDST_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\LDST_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\LDST_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\LDST_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\LDST_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\LDST_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\LDST_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\LDST_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\LDST_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\LDST_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\LDST_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\LDST_is_32b[0:0] 1'0 + case + assign $1\LDST_is_32b[0:0] 1'0 + end + sync always + update \LDST_is_32b $0\LDST_is_32b[0:0] + end + attribute \src "libresoc.v:64755.3-64812.6" + process $proc$libresoc.v:64755$3549 + assign { } { } + assign { } { } + assign $0\LDST_sgn[0:0] $1\LDST_sgn[0:0] + attribute \src "libresoc.v:64756.5-64756.29" + switch \initial + attribute \src "libresoc.v:64756.9-64756.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\LDST_sgn[0:0] \LDST_dec31_LDST_dec31_sgn + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\LDST_sgn[0:0] \LDST_dec58_LDST_dec58_sgn + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\LDST_sgn[0:0] \LDST_dec62_LDST_dec62_sgn + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\LDST_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\LDST_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\LDST_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\LDST_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\LDST_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\LDST_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\LDST_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\LDST_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\LDST_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\LDST_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\LDST_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\LDST_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\LDST_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\LDST_sgn[0:0] 1'0 + case + assign $1\LDST_sgn[0:0] 1'0 + end + sync always + update \LDST_sgn $0\LDST_sgn[0:0] + end + attribute \src "libresoc.v:64813.3-64870.6" + process $proc$libresoc.v:64813$3550 + assign { } { } + assign { } { } + assign $0\LDST_function_unit[11:0] $1\LDST_function_unit[11:0] + attribute \src "libresoc.v:64814.5-64814.29" + switch \initial + attribute \src "libresoc.v:64814.9-64814.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\LDST_function_unit[11:0] \LDST_dec31_LDST_dec31_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\LDST_function_unit[11:0] \LDST_dec58_LDST_dec58_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\LDST_function_unit[11:0] \LDST_dec62_LDST_dec62_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\LDST_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\LDST_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\LDST_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\LDST_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\LDST_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\LDST_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\LDST_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\LDST_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\LDST_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\LDST_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\LDST_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\LDST_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\LDST_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\LDST_function_unit[11:0] 12'000000000100 + case + assign $1\LDST_function_unit[11:0] 12'000000000000 + end + sync always + update \LDST_function_unit $0\LDST_function_unit[11:0] + end + attribute \src "libresoc.v:64871.3-64928.6" + process $proc$libresoc.v:64871$3551 + assign { } { } + assign { } { } + assign $0\LDST_internal_op[6:0] $1\LDST_internal_op[6:0] + attribute \src "libresoc.v:64872.5-64872.29" + switch \initial + attribute \src "libresoc.v:64872.9-64872.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\LDST_internal_op[6:0] \LDST_dec31_LDST_dec31_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\LDST_internal_op[6:0] \LDST_dec58_LDST_dec58_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\LDST_internal_op[6:0] \LDST_dec62_LDST_dec62_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\LDST_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\LDST_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\LDST_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\LDST_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\LDST_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\LDST_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\LDST_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\LDST_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\LDST_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\LDST_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\LDST_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\LDST_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\LDST_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\LDST_internal_op[6:0] 7'0100110 + case + assign $1\LDST_internal_op[6:0] 7'0000000 + end + sync always + update \LDST_internal_op $0\LDST_internal_op[6:0] + end + attribute \src "libresoc.v:64929.3-64986.6" + process $proc$libresoc.v:64929$3552 + assign { } { } + assign { } { } + assign $0\LDST_in1_sel[2:0] $1\LDST_in1_sel[2:0] + attribute \src "libresoc.v:64930.5-64930.29" + switch \initial + attribute \src "libresoc.v:64930.9-64930.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\LDST_in1_sel[2:0] \LDST_dec31_LDST_dec31_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\LDST_in1_sel[2:0] \LDST_dec58_LDST_dec58_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\LDST_in1_sel[2:0] \LDST_dec62_LDST_dec62_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\LDST_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\LDST_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\LDST_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\LDST_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\LDST_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\LDST_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\LDST_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\LDST_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\LDST_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\LDST_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\LDST_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\LDST_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\LDST_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\LDST_in1_sel[2:0] 3'010 + case + assign $1\LDST_in1_sel[2:0] 3'000 + end + sync always + update \LDST_in1_sel $0\LDST_in1_sel[2:0] + end + attribute \src "libresoc.v:64987.3-65044.6" + process $proc$libresoc.v:64987$3553 + assign { } { } + assign { } { } + assign $0\LDST_in2_sel[3:0] $1\LDST_in2_sel[3:0] + attribute \src "libresoc.v:64988.5-64988.29" + switch \initial + attribute \src "libresoc.v:64988.9-64988.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\LDST_in2_sel[3:0] \LDST_dec31_LDST_dec31_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\LDST_in2_sel[3:0] \LDST_dec58_LDST_dec58_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\LDST_in2_sel[3:0] \LDST_dec62_LDST_dec62_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\LDST_in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\LDST_in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\LDST_in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\LDST_in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\LDST_in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\LDST_in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\LDST_in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\LDST_in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\LDST_in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\LDST_in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\LDST_in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\LDST_in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\LDST_in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\LDST_in2_sel[3:0] 4'0011 + case + assign $1\LDST_in2_sel[3:0] 4'0000 + end + sync always + update \LDST_in2_sel $0\LDST_in2_sel[3:0] + end + attribute \src "libresoc.v:65045.3-65102.6" + process $proc$libresoc.v:65045$3554 + assign { } { } + assign { } { } + assign $0\LDST_cr_in[2:0] $1\LDST_cr_in[2:0] + attribute \src "libresoc.v:65046.5-65046.29" + switch \initial + attribute \src "libresoc.v:65046.9-65046.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\LDST_cr_in[2:0] \LDST_dec31_LDST_dec31_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\LDST_cr_in[2:0] \LDST_dec58_LDST_dec58_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\LDST_cr_in[2:0] \LDST_dec62_LDST_dec62_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\LDST_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\LDST_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\LDST_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\LDST_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\LDST_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\LDST_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\LDST_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\LDST_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\LDST_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\LDST_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\LDST_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\LDST_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\LDST_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\LDST_cr_in[2:0] 3'000 + case + assign $1\LDST_cr_in[2:0] 3'000 + end + sync always + update \LDST_cr_in $0\LDST_cr_in[2:0] + end + attribute \src "libresoc.v:65103.3-65160.6" + process $proc$libresoc.v:65103$3555 + assign { } { } + assign { } { } + assign $0\LDST_cr_out[2:0] $1\LDST_cr_out[2:0] + attribute \src "libresoc.v:65104.5-65104.29" + switch \initial + attribute \src "libresoc.v:65104.9-65104.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\LDST_cr_out[2:0] \LDST_dec31_LDST_dec31_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\LDST_cr_out[2:0] \LDST_dec58_LDST_dec58_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\LDST_cr_out[2:0] \LDST_dec62_LDST_dec62_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\LDST_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\LDST_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\LDST_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\LDST_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\LDST_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\LDST_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\LDST_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\LDST_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\LDST_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\LDST_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\LDST_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\LDST_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\LDST_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\LDST_cr_out[2:0] 3'000 + case + assign $1\LDST_cr_out[2:0] 3'000 + end + sync always + update \LDST_cr_out $0\LDST_cr_out[2:0] + end + connect \$1 $ternary$libresoc.v:64358$3542_Y + connect \VC_XO \opcode_in [9:0] + connect \VC_VRT \opcode_in [25:21] + connect \VC_VRB \opcode_in [15:11] + connect \VC_VRA \opcode_in [20:16] + connect \VC_Rc \opcode_in [10] + connect \XS_XO \opcode_in [10:2] + connect \XS_sh { \opcode_in [1] \opcode_in [15:11] } + connect \XS_RS \opcode_in [25:21] + connect \XS_Rc \opcode_in [0] + connect \XS_RA \opcode_in [20:16] + connect \VA_XO \opcode_in [5:0] + connect \VA_VRT \opcode_in [25:21] + connect \VA_VRC \opcode_in [10:6] + connect \VA_VRB \opcode_in [15:11] + connect \VA_VRA \opcode_in [20:16] + connect \VA_SHB \opcode_in [9:6] + connect \VA_RT \opcode_in [25:21] + connect \VA_RC \opcode_in [10:6] + connect \VA_RB \opcode_in [15:11] + connect \VA_RA \opcode_in [20:16] + connect \TX_XO \opcode_in [6:1] + connect \TX_XBI \opcode_in [10:7] + connect \TX_UI \opcode_in [15:11] + connect \TX_RA \opcode_in [20:16] + connect \DQE_XO \opcode_in [1:0] + connect \DQE_RT \opcode_in [25:21] + connect \DQE_RA \opcode_in [20:16] + connect \XO_XO \opcode_in [9:1] + connect \XO_RT \opcode_in [25:21] + connect \XO_Rc \opcode_in [0] + connect \XO_RB \opcode_in [15:11] + connect \XO_RA \opcode_in [20:16] + connect \XO_OE \opcode_in [10] + connect \all_PO \opcode_in [31:26] + connect \all_OPCD \opcode_in [31:26] + connect \MD_XO \opcode_in [4:2] + connect \MD_sh { \opcode_in [1] \opcode_in [15:11] } + connect \MD_RS \opcode_in [25:21] + connect \MD_Rc \opcode_in [0] + connect \MD_RA \opcode_in [20:16] + connect \MD_me \opcode_in [10:5] + connect \MD_mb \opcode_in [10:5] + connect \M_SH \opcode_in [15:11] + connect \M_RS \opcode_in [25:21] + connect \M_Rc \opcode_in [0] + connect \M_RB \opcode_in [15:11] + connect \M_RA \opcode_in [20:16] + connect \M_ME \opcode_in [5:1] + connect \M_MB \opcode_in [10:6] + connect \SC_XO_1 \opcode_in [1:0] + connect \SC_XO \opcode_in [1] + connect \SC_LEV \opcode_in [11:5] + connect \MDS_XO \opcode_in [4:1] + connect \MDS_XBI_1 \opcode_in [10:7] + connect \MDS_XBI \opcode_in [10:7] + connect \MDS_RS \opcode_in [25:21] + connect \MDS_Rc \opcode_in [0] + connect \MDS_RB \opcode_in [15:11] + connect \MDS_RA \opcode_in [20:16] + connect \MDS_me \opcode_in [10:5] + connect \MDS_mb \opcode_in [10:5] + connect \MDS_IS \opcode_in [25:21] + connect \MDS_IB \opcode_in [15:11] + connect \Z23_XO \opcode_in [8:1] + connect \Z23_TE \opcode_in [20:16] + connect \Z23_RMC \opcode_in [10:9] + connect \Z23_Rc \opcode_in [0] + connect \Z23_R \opcode_in [16] + connect \Z23_FRTp \opcode_in [25:21] + connect \Z23_FRT \opcode_in [25:21] + connect \Z23_FRBp \opcode_in [15:11] + connect \Z23_FRB \opcode_in [15:11] + connect \Z23_FRAp \opcode_in [20:16] + connect \Z23_FRA \opcode_in [20:16] + connect \XFL_XO \opcode_in [10:1] + connect \XFL_W \opcode_in [16] + connect \XFL_Rc \opcode_in [0] + connect \XFL_L \opcode_in [25] + connect \XFL_FRB \opcode_in [15:11] + connect \XFL_FLM \opcode_in [24:17] + connect \VX_XO_1 \opcode_in [10:0] + connect \VX_XO { \opcode_in [10] \opcode_in [8:0] } + connect \VX_VRT \opcode_in [25:21] + connect \VX_VRB \opcode_in [15:11] + connect \VX_VRA \opcode_in [20:16] + connect \VX_UIM_3 \opcode_in [17:16] + connect \VX_UIM_2 \opcode_in [18:16] + connect \VX_UIM_1 \opcode_in [19:16] + connect \VX_UIM \opcode_in [20:16] + connect \VX_SIM \opcode_in [20:16] + connect \VX_RT \opcode_in [25:21] + connect \VX_RA \opcode_in [20:16] + connect \VX_PS \opcode_in [9] + connect \VX_EO \opcode_in [20:16] + connect \DS_XO \opcode_in [1:0] + connect \DS_VRT \opcode_in [25:21] + connect \DS_VRS \opcode_in [25:21] + connect \DS_RT \opcode_in [25:21] + connect \DS_RSp \opcode_in [25:21] + connect \DS_RS \opcode_in [25:21] + connect \DS_RA \opcode_in [20:16] + connect \DS_FRTp \opcode_in [25:21] + connect \DS_FRSp \opcode_in [25:21] + connect \DS_DS \opcode_in [15:2] + connect \DQ_XO \opcode_in [2:0] + connect \DQ_TX_T { \opcode_in [3] \opcode_in [25:21] } + connect \DQ_T \opcode_in [25:21] + connect \DQ_TX \opcode_in [3] + connect \DQ_SX_S { \opcode_in [3] \opcode_in [25:21] } + connect \DQ_S \opcode_in [25:21] + connect \DQ_SX \opcode_in [3] + connect \DQ_RTp \opcode_in [25:21] + connect \DQ_RA \opcode_in [20:16] + connect \DQ_PT \opcode_in [3:0] + connect \DQ_DQ \opcode_in [15:4] + connect \DX_XO \opcode_in [5:1] + connect \DX_RT \opcode_in [25:21] + connect \DX_d0_d1_d2 { \opcode_in [15:6] \opcode_in [20:16] \opcode_in [0] } + connect \DX_d2 \opcode_in [0] + connect \DX_d1 \opcode_in [20:16] + connect \DX_d0 \opcode_in [15:6] + connect \XFX_XO \opcode_in [10:1] + connect \XFX_SPR \opcode_in [20:11] + connect \XFX_RT \opcode_in [25:21] + connect \XFX_RS \opcode_in [25:21] + connect \XFX_FXM \opcode_in [19:12] + connect \XFX_DUIS \opcode_in [20:11] + connect \XFX_DUI \opcode_in [25:21] + connect \XFX_BHRBE \opcode_in [20:11] + connect \EVS_BFA \opcode_in [2:0] + connect \Z22_XO \opcode_in [9:1] + connect \Z22_SH \opcode_in [15:10] + connect \Z22_Rc \opcode_in [0] + connect \Z22_FRTp \opcode_in [25:21] + connect \Z22_FRT \opcode_in [25:21] + connect \Z22_FRAp \opcode_in [20:16] + connect \Z22_FRA \opcode_in [20:16] + connect \Z22_DGM \opcode_in [15:10] + connect \Z22_DCM \opcode_in [15:10] + connect \Z22_BF \opcode_in [25:23] + connect \XX2_XO_1 \opcode_in [10:2] + connect \XX2_XO { \opcode_in [10:7] \opcode_in [5:3] } + connect \XX2_UIM_1 \opcode_in [17:16] + connect \XX2_UIM \opcode_in [19:16] + connect \XX2_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX2_T \opcode_in [25:21] + connect \XX2_TX \opcode_in [0] + connect \XX2_RT \opcode_in [25:21] + connect \XX2_EO \opcode_in [20:16] + connect \XX2_DCMX \opcode_in [22:16] + connect \XX2_dc_dm_dx { \opcode_in [6] \opcode_in [2] \opcode_in [20:16] } + connect \XX2_dx \opcode_in [20:16] + connect \XX2_dm \opcode_in [2] + connect \XX2_dc \opcode_in [6] + connect \XX2_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX2_B \opcode_in [15:11] + connect \XX2_BX \opcode_in [1] + connect \XX2_BF \opcode_in [25:23] + connect \D_UI \opcode_in [15:0] + connect \D_TO \opcode_in [25:21] + connect \D_SI \opcode_in [15:0] + connect \D_RT \opcode_in [25:21] + connect \D_RS \opcode_in [25:21] + connect \D_RA \opcode_in [20:16] + connect \D_L \opcode_in [21] + connect \D_FRT \opcode_in [25:21] + connect \D_FRS \opcode_in [25:21] + connect \D_D \opcode_in [15:0] + connect \D_BF \opcode_in [25:23] + connect \A_XO \opcode_in [5:1] + connect \A_RT \opcode_in [25:21] + connect \A_Rc \opcode_in [0] + connect \A_RB \opcode_in [15:11] + connect \A_RA \opcode_in [20:16] + connect \A_FRT \opcode_in [25:21] + connect \A_FRC \opcode_in [10:6] + connect \A_FRB \opcode_in [15:11] + connect \A_FRA \opcode_in [20:16] + connect \A_BC \opcode_in [10:6] + connect \XL_XO \opcode_in [10:1] + connect \XL_S \opcode_in [11] + connect \XL_OC \opcode_in [25:11] + connect \XL_LK \opcode_in [0] + connect \XL_BT \opcode_in [25:21] + connect \XL_BO_1 \opcode_in [25:21] + connect \XL_BO \opcode_in [25:21] + connect \XL_BI \opcode_in [20:16] + connect \XL_BH \opcode_in [12:11] + connect \XL_BFA \opcode_in [20:18] + connect \XL_BF \opcode_in [25:23] + connect \XL_BB \opcode_in [15:11] + connect \XL_BA \opcode_in [20:16] + connect \XX4_XO \opcode_in [5:4] + connect \XX4_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX4_T \opcode_in [25:21] + connect \XX4_TX \opcode_in [0] + connect \XX4_CX_C { \opcode_in [3] \opcode_in [10:6] } + connect \XX4_C \opcode_in [10:6] + connect \XX4_CX \opcode_in [3] + connect \XX4_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX4_B \opcode_in [15:11] + connect \XX4_BX \opcode_in [1] + connect \XX4_AX_A { \opcode_in [2] \opcode_in [20:16] } + connect \XX4_A \opcode_in [20:16] + connect \XX4_AX \opcode_in [2] + connect \XX3_XO_2 \opcode_in [9:1] + connect \XX3_XO_1 \opcode_in [10:3] + connect \XX3_XO \opcode_in [10:7] + connect \XX3_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX3_T \opcode_in [25:21] + connect \XX3_TX \opcode_in [0] + connect \XX3_SHW \opcode_in [9:8] + connect \XX3_Rc \opcode_in [10] + connect \XX3_DM \opcode_in [9:8] + connect \XX3_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX3_B \opcode_in [15:11] + connect \XX3_BX \opcode_in [1] + connect \XX3_BF \opcode_in [25:23] + connect \XX3_AX_A { \opcode_in [2] \opcode_in [20:16] } + connect \XX3_A \opcode_in [20:16] + connect \XX3_AX \opcode_in [2] + connect \I_LK \opcode_in [0] + connect \I_LI \opcode_in [25:2] + connect \I_AA \opcode_in [1] + connect \B_LK \opcode_in [0] + connect \B_BO \opcode_in [25:21] + connect \B_BI \opcode_in [20:16] + connect \B_BD \opcode_in [15:2] + connect \B_AA \opcode_in [1] + connect \X_XO_1 \opcode_in [8:1] + connect \X_XO \opcode_in [10:1] + connect \X_WC \opcode_in [22:21] + connect \X_W \opcode_in [16] + connect \X_VRT \opcode_in [25:21] + connect \X_VRS \opcode_in [25:21] + connect \X_UIM \opcode_in [20:16] + connect \X_U \opcode_in [15:12] + connect \X_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \X_TX \opcode_in [0] + connect \X_TO \opcode_in [25:21] + connect \X_TH \opcode_in [25:21] + connect \X_TBR \opcode_in [20:11] + connect \X_T \opcode_in [25:21] + connect \X_SX_S { \opcode_in [0] \opcode_in [25:21] } + connect \X_SX \opcode_in [0] + connect \X_SR \opcode_in [19:16] + connect \X_SP \opcode_in [20:19] + connect \X_SI \opcode_in [15:11] + connect \X_SH \opcode_in [15:11] + connect \X_S \opcode_in [25:21] + connect \X_RTp \opcode_in [25:21] + connect \X_RT \opcode_in [25:21] + connect \X_RSp \opcode_in [25:21] + connect \X_RS \opcode_in [25:21] + connect \X_RO \opcode_in [0] + connect \X_RM \opcode_in [12:11] + connect \X_RIC \opcode_in [19:18] + connect \X_Rc \opcode_in [0] + connect \X_RB \opcode_in [15:11] + connect \X_RA \opcode_in [20:16] + connect \X_R_1 \opcode_in [16] + connect \X_R \opcode_in [21] + connect \X_PRS \opcode_in [17] + connect \X_NB \opcode_in [15:11] + connect \X_MO \opcode_in [25:21] + connect \X_L3 \opcode_in [17:16] + connect \X_L1 \opcode_in [16] + connect \X_L \opcode_in [21] + connect \X_L2 \opcode_in [22:21] + connect \X_IMM8 \opcode_in [18:11] + connect \X_IH \opcode_in [23:21] + connect \X_FRTp \opcode_in [25:21] + connect \X_FRT \opcode_in [25:21] + connect \X_FRSp \opcode_in [25:21] + connect \X_FRS \opcode_in [25:21] + connect \X_FRBp \opcode_in [15:11] + connect \X_FRB \opcode_in [15:11] + connect \X_FRAp \opcode_in [20:16] + connect \X_FRA \opcode_in [20:16] + connect \X_FC \opcode_in [15:11] + connect \X_EX \opcode_in [0] + connect \X_EO_1 \opcode_in [20:16] + connect \X_EO \opcode_in [20:19] + connect \X_E_1 \opcode_in [19:16] + connect \X_E \opcode_in [15] + connect \X_DRM \opcode_in [13:11] + connect \X_DCMX \opcode_in [22:16] + connect \X_CT \opcode_in [24:21] + connect \X_BO \opcode_in [25:21] + connect \X_BFA \opcode_in [20:18] + connect \X_BF \opcode_in [25:23] + connect \X_A \opcode_in [25] + connect \LDST_SPR \opcode_in [20:11] + connect \LDST_MB \opcode_in [10:6] + connect \LDST_ME \opcode_in [5:1] + connect \LDST_SH \opcode_in [15:11] + connect \LDST_BC \opcode_in [10:6] + connect \LDST_TO \opcode_in [25:21] + connect \LDST_DS \opcode_in [15:2] + connect \LDST_D \opcode_in [15:0] + connect \LDST_BH \opcode_in [12:11] + connect \LDST_BI \opcode_in [20:16] + connect \LDST_BO \opcode_in [25:21] + connect \LDST_FXM \opcode_in [19:12] + connect \LDST_BT \opcode_in [25:21] + connect \LDST_BA \opcode_in [20:16] + connect \LDST_BB \opcode_in [15:11] + connect \LDST_CR \opcode_in [10:1] + connect \LDST_BF \opcode_in [25:23] + connect \LDST_BD \opcode_in [15:2] + connect \LDST_OE \opcode_in [10] + connect \LDST_Rc \opcode_in [0] + connect \LDST_AA \opcode_in [1] + connect \LDST_LK \opcode_in [0] + connect \LDST_LI \opcode_in [25:2] + connect \LDST_ME32 \opcode_in [5:1] + connect \LDST_MB32 \opcode_in [10:6] + connect \LDST_sh { \opcode_in [1] \opcode_in [15:11] } + connect \LDST_SH32 \opcode_in [15:11] + connect \LDST_L \opcode_in [21] + connect \LDST_UI \opcode_in [15:0] + connect \LDST_SI \opcode_in [15:0] + connect \LDST_RB \opcode_in [15:11] + connect \LDST_RA \opcode_in [20:16] + connect \LDST_RT \opcode_in [25:21] + connect \LDST_RS \opcode_in [25:21] + connect \opcode_in \$1 + connect \LDST_dec62_opcode_in \opcode_in + connect \LDST_dec58_opcode_in \opcode_in + connect \LDST_dec31_opcode_in \opcode_in + connect \opcode_switch \opcode_in [31:26] +end +attribute \src "libresoc.v:65496.1-71429.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.dec2.dec" +attribute \generator "nMigen" +module \dec$202 + attribute \src "libresoc.v:67690.3-67828.6" + wire width 8 $0\asmcode[7:0] + attribute \src "libresoc.v:69675.3-69816.6" + wire $0\br[0:0] + attribute \src "libresoc.v:68397.3-68538.6" + wire width 3 $0\cr_in[2:0] + attribute \src "libresoc.v:68539.3-68680.6" + wire width 3 $0\cr_out[2:0] + attribute \src "libresoc.v:69107.3-69248.6" + wire width 2 $0\cry_in[1:0] + attribute \src "libresoc.v:69533.3-69674.6" + wire $0\cry_out[0:0] + attribute \src "libresoc.v:70953.3-71094.6" + wire width 5 $0\form[4:0] + attribute \src "libresoc.v:70669.3-70810.6" + wire width 12 $0\function_unit[11:0] + attribute \src "libresoc.v:67829.3-67970.6" + wire width 3 $0\in1_sel[2:0] + attribute \src "libresoc.v:67971.3-68112.6" + wire width 4 $0\in2_sel[3:0] + attribute \src "libresoc.v:68113.3-68254.6" + wire width 2 $0\in3_sel[1:0] + attribute \src "libresoc.v:65497.7-65497.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:70811.3-70952.6" + wire width 7 $0\internal_op[6:0] + attribute \src "libresoc.v:69249.3-69390.6" + wire $0\inv_a[0:0] + attribute \src "libresoc.v:69391.3-69532.6" + wire $0\inv_out[0:0] + attribute \src "libresoc.v:70101.3-70242.6" + wire $0\is_32b[0:0] + attribute \src "libresoc.v:68681.3-68822.6" + wire width 4 $0\ldst_len[3:0] + attribute \src "libresoc.v:70385.3-70526.6" + wire $0\lk[0:0] + attribute \src "libresoc.v:68255.3-68396.6" + wire width 2 $0\out_sel[1:0] + attribute \src "libresoc.v:68965.3-69106.6" + wire width 2 $0\rc_sel[1:0] + attribute \src "libresoc.v:69959.3-70100.6" + wire $0\rsrv[0:0] + attribute \src "libresoc.v:70527.3-70668.6" + wire $0\sgl_pipe[0:0] + attribute \src "libresoc.v:70243.3-70384.6" + wire $0\sgn[0:0] + attribute \src "libresoc.v:69817.3-69958.6" + wire $0\sgn_ext[0:0] + attribute \src "libresoc.v:68823.3-68964.6" + wire width 2 $0\upd[1:0] + attribute \src "libresoc.v:67690.3-67828.6" + wire width 8 $1\asmcode[7:0] + attribute \src "libresoc.v:69675.3-69816.6" + wire $1\br[0:0] + attribute \src "libresoc.v:68397.3-68538.6" + wire width 3 $1\cr_in[2:0] + attribute \src "libresoc.v:68539.3-68680.6" + wire width 3 $1\cr_out[2:0] + attribute \src "libresoc.v:69107.3-69248.6" + wire width 2 $1\cry_in[1:0] + attribute \src "libresoc.v:69533.3-69674.6" + wire $1\cry_out[0:0] + attribute \src "libresoc.v:70953.3-71094.6" + wire width 5 $1\form[4:0] + attribute \src "libresoc.v:70669.3-70810.6" + wire width 12 $1\function_unit[11:0] + attribute \src "libresoc.v:67829.3-67970.6" + wire width 3 $1\in1_sel[2:0] + attribute \src "libresoc.v:67971.3-68112.6" + wire width 4 $1\in2_sel[3:0] + attribute \src "libresoc.v:68113.3-68254.6" + wire width 2 $1\in3_sel[1:0] + attribute \src "libresoc.v:70811.3-70952.6" + wire width 7 $1\internal_op[6:0] + attribute \src "libresoc.v:69249.3-69390.6" + wire $1\inv_a[0:0] + attribute \src "libresoc.v:69391.3-69532.6" + wire $1\inv_out[0:0] + attribute \src "libresoc.v:70101.3-70242.6" + wire $1\is_32b[0:0] + attribute \src "libresoc.v:68681.3-68822.6" + wire width 4 $1\ldst_len[3:0] + attribute \src "libresoc.v:70385.3-70526.6" + wire $1\lk[0:0] + attribute \src "libresoc.v:68255.3-68396.6" + wire width 2 $1\out_sel[1:0] + attribute \src "libresoc.v:68965.3-69106.6" + wire width 2 $1\rc_sel[1:0] + attribute \src "libresoc.v:69959.3-70100.6" + wire $1\rsrv[0:0] + attribute \src "libresoc.v:70527.3-70668.6" + wire $1\sgl_pipe[0:0] + attribute \src "libresoc.v:70243.3-70384.6" + wire $1\sgn[0:0] + attribute \src "libresoc.v:69817.3-69958.6" + wire $1\sgn_ext[0:0] + attribute \src "libresoc.v:68823.3-68964.6" + wire width 2 $1\upd[1:0] + attribute \src "libresoc.v:67690.3-67828.6" + wire width 8 $2\asmcode[7:0] + attribute \src "libresoc.v:69675.3-69816.6" + wire $2\br[0:0] + attribute \src "libresoc.v:68397.3-68538.6" + wire width 3 $2\cr_in[2:0] + attribute \src "libresoc.v:68539.3-68680.6" + wire width 3 $2\cr_out[2:0] + attribute \src "libresoc.v:69107.3-69248.6" + wire width 2 $2\cry_in[1:0] + attribute \src "libresoc.v:69533.3-69674.6" + wire $2\cry_out[0:0] + attribute \src "libresoc.v:70953.3-71094.6" + wire width 5 $2\form[4:0] + attribute \src "libresoc.v:70669.3-70810.6" + wire width 12 $2\function_unit[11:0] + attribute \src "libresoc.v:67829.3-67970.6" + wire width 3 $2\in1_sel[2:0] + attribute \src "libresoc.v:67971.3-68112.6" + wire width 4 $2\in2_sel[3:0] + attribute \src "libresoc.v:68113.3-68254.6" + wire width 2 $2\in3_sel[1:0] + attribute \src "libresoc.v:70811.3-70952.6" + wire width 7 $2\internal_op[6:0] + attribute \src "libresoc.v:69249.3-69390.6" + wire $2\inv_a[0:0] + attribute \src "libresoc.v:69391.3-69532.6" + wire $2\inv_out[0:0] + attribute \src "libresoc.v:70101.3-70242.6" + wire $2\is_32b[0:0] + attribute \src "libresoc.v:68681.3-68822.6" + wire width 4 $2\ldst_len[3:0] + attribute \src "libresoc.v:70385.3-70526.6" + wire $2\lk[0:0] + attribute \src "libresoc.v:68255.3-68396.6" + wire width 2 $2\out_sel[1:0] + attribute \src "libresoc.v:68965.3-69106.6" + wire width 2 $2\rc_sel[1:0] + attribute \src "libresoc.v:69959.3-70100.6" + wire $2\rsrv[0:0] + attribute \src "libresoc.v:70527.3-70668.6" + wire $2\sgl_pipe[0:0] + attribute \src "libresoc.v:70243.3-70384.6" + wire $2\sgn[0:0] + attribute \src "libresoc.v:69817.3-69958.6" + wire $2\sgn_ext[0:0] + attribute \src "libresoc.v:68823.3-68964.6" + wire width 2 $2\upd[1:0] + attribute \src "libresoc.v:67554.17-67554.211" + wire width 32 $ternary$libresoc.v:67554$3557_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:478" + wire width 32 \$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire \AA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_FRC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \A_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 output 25 \BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 output 24 \BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 output 30 \BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 14 \BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 3 \BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 2 \BH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 output 29 \BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 output 28 \BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 output 26 \BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \B_AA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 14 \B_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \B_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \B_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \B_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 10 \CR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 16 \D + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DQE_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DQE_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \DQE_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 12 \DQ_DQ + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \DQ_PT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DQ_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DQ_RTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DQ_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \DQ_SX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \DQ_SX_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DQ_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \DQ_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \DQ_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \DQ_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 14 \DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 14 \DS_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_FRSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_RSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_VRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \DS_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DX_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \DX_d0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 16 \DX_d0_d1_d2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DX_d1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \DX_d2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \D_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 16 \D_D + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \D_FRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \D_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \D_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \D_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \D_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \D_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 16 \D_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \D_TO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 16 \D_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \EVS_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 8 output 27 \FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \I_AA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 24 \I_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \I_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire \L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 24 \LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire output 11 \LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \MB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \MB32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MDS_IB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MDS_IS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MDS_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MDS_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MDS_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \MDS_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \MDS_XBI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \MDS_XBI_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \MDS_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \MDS_mb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \MDS_me + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MD_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MD_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \MD_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \MD_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \MD_mb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \MD_me + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \MD_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \ME + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \ME32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \M_MB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \M_ME + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \M_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \M_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \M_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \M_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \M_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire output 23 \OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 output 20 \RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 output 21 \RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 output 18 \RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 output 19 \RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire output 22 \Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 7 \SC_LEV + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \SC_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \SC_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 16 \SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 10 output 31 \SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \TO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \TX_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \TX_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \TX_XBI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \TX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 16 \UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_RC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \VA_SHB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_VRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_VRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_VRC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \VA_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \VC_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VC_VRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VC_VRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VC_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \VC_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_EO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \VX_PS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_SIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_UIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \VX_UIM_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \VX_UIM_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \VX_UIM_3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_VRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_VRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \VX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 11 \VX_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 8 \XFL_FLM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XFL_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XFL_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XFL_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XFL_W + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \XFL_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \XFX_BHRBE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XFX_DUI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \XFX_DUIS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 8 \XFX_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XFX_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XFX_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \XFX_SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \XFX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XL_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XL_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \XL_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \XL_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \XL_BH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XL_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XL_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XL_BO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 output 34 \XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XL_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 15 \XL_OC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XL_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 output 35 \XL_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XO_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XO_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XO_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XO_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XO_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 9 \XO_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XS_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XS_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XS_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 9 \XS_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XS_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX2_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \XX2_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX2_BX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX2_BX_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 7 \XX2_DCMX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX2_EO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX2_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX2_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX2_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX2_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \XX2_UIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \XX2_UIM_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 7 \XX2_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 9 \XX2_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX2_dc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 7 \XX2_dc_dm_dx + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX2_dm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX2_dx + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX3_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX3_AX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX3_AX_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX3_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \XX3_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX3_BX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX3_BX_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \XX3_DM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX3_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \XX3_SHW + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX3_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX3_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX3_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \XX3_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 8 \XX3_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 9 \XX3_XO_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX4_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX4_AX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX4_AX_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX4_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX4_BX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX4_BX_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX4_C + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX4_CX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX4_CX_C + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX4_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX4_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX4_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \XX4_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 output 32 \X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 output 33 \X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \X_CT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 7 \X_DCMX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \X_DRM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_E + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \X_EO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_EO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_EX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \X_E_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRAp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRBp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \X_IH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 8 \X_IMM8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_L1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \X_L2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \X_L3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_MO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_NB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_PRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_R + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \X_RIC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \X_RM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_RO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_RSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_RTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_R_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \X_SP + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \X_SR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_SX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \X_SX_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \X_TBR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_TH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_TO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \X_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \X_U + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_UIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_VRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_W + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \X_WC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \X_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 8 \X_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \Z22_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \Z22_DCM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \Z22_DGM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z22_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z22_FRAp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z22_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z22_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \Z22_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \Z22_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 9 \Z22_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_FRAp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_FRBp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \Z23_R + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \Z23_RMC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \Z23_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_TE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 8 \Z23_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \all_OPCD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \all_PO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 output 16 \asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + wire input 36 \bigendian + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 4 \cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 8 \cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 \dec19_dec19_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec19_dec19_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec19_dec19_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec19_dec19_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec19_dec19_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec19_dec19_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 \dec19_dec19_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \dec19_dec19_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec19_dec19_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec19_dec19_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec19_dec19_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 \dec19_dec19_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec19_dec19_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec19_dec19_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec19_dec19_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec19_dec19_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec19_dec19_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec19_dec19_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec19_dec19_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec19_dec19_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec19_dec19_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec19_dec19_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec19_dec19_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec19_dec19_upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \dec19_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 \dec30_dec30_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec30_dec30_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec30_dec30_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec30_dec30_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec30_dec30_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec30_dec30_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 \dec30_dec30_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \dec30_dec30_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec30_dec30_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec30_dec30_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec30_dec30_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 \dec30_dec30_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec30_dec30_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec30_dec30_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec30_dec30_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec30_dec30_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec30_dec30_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec30_dec30_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec30_dec30_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec30_dec30_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec30_dec30_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec30_dec30_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec30_dec30_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec30_dec30_upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \dec30_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 \dec31_dec31_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec31_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec31_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec31_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec31_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec31_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 \dec31_dec31_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \dec31_dec31_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec31_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec31_dec31_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec31_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 \dec31_dec31_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec31_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec31_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec31_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec31_dec31_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec31_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec31_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec31_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec31_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec31_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec31_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec31_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec31_upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \dec31_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 \dec58_dec58_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec58_dec58_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec58_dec58_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec58_dec58_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec58_dec58_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec58_dec58_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 \dec58_dec58_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \dec58_dec58_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec58_dec58_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec58_dec58_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec58_dec58_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 \dec58_dec58_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec58_dec58_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec58_dec58_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec58_dec58_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec58_dec58_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec58_dec58_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec58_dec58_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec58_dec58_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec58_dec58_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec58_dec58_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec58_dec58_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec58_dec58_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec58_dec58_upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \dec58_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 \dec62_dec62_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec62_dec62_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec62_dec62_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec62_dec62_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec62_dec62_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec62_dec62_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 \dec62_dec62_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \dec62_dec62_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec62_dec62_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec62_dec62_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec62_dec62_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 \dec62_dec62_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec62_dec62_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec62_dec62_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec62_dec62_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec62_dec62_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec62_dec62_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec62_dec62_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec62_dec62_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec62_dec62_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec62_dec62_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec62_dec62_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec62_dec62_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec62_dec62_upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \dec62_opcode_in + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 \form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 7 \function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 12 \in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 13 \in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 14 \in3_sel + attribute \src "libresoc.v:65497.7-65497.15" + wire \initial + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 6 \internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 9 \is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 10 \lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 output 2 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 6 \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 32 \opcode_switch$1 + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 15 \out_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:442" + wire width 32 input 1 \raw_opcode_in + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 3 \rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 6 \sh + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 17 \upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:478" + cell $mux $ternary$libresoc.v:67554$3557 + parameter \WIDTH 32 + connect \A \raw_opcode_in + connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } + connect \S \bigendian + connect \Y $ternary$libresoc.v:67554$3557_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:67555.9-67581.4" + cell \dec19 \dec19 + connect \dec19_asmcode \dec19_dec19_asmcode + connect \dec19_br \dec19_dec19_br + connect \dec19_cr_in \dec19_dec19_cr_in + connect \dec19_cr_out \dec19_dec19_cr_out + connect \dec19_cry_in \dec19_dec19_cry_in + connect \dec19_cry_out \dec19_dec19_cry_out + connect \dec19_form \dec19_dec19_form + connect \dec19_function_unit \dec19_dec19_function_unit + connect \dec19_in1_sel \dec19_dec19_in1_sel + connect \dec19_in2_sel \dec19_dec19_in2_sel + connect \dec19_in3_sel \dec19_dec19_in3_sel + connect \dec19_internal_op \dec19_dec19_internal_op + connect \dec19_inv_a \dec19_dec19_inv_a + connect \dec19_inv_out \dec19_dec19_inv_out + connect \dec19_is_32b \dec19_dec19_is_32b + connect \dec19_ldst_len \dec19_dec19_ldst_len + connect \dec19_lk \dec19_dec19_lk + connect \dec19_out_sel \dec19_dec19_out_sel + connect \dec19_rc_sel \dec19_dec19_rc_sel + connect \dec19_rsrv \dec19_dec19_rsrv + connect \dec19_sgl_pipe \dec19_dec19_sgl_pipe + connect \dec19_sgn \dec19_dec19_sgn + connect \dec19_sgn_ext \dec19_dec19_sgn_ext + connect \dec19_upd \dec19_dec19_upd + connect \opcode_in \dec19_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:67582.9-67608.4" + cell \dec30 \dec30 + connect \dec30_asmcode \dec30_dec30_asmcode + connect \dec30_br \dec30_dec30_br + connect \dec30_cr_in \dec30_dec30_cr_in + connect \dec30_cr_out \dec30_dec30_cr_out + connect \dec30_cry_in \dec30_dec30_cry_in + connect \dec30_cry_out \dec30_dec30_cry_out + connect \dec30_form \dec30_dec30_form + connect \dec30_function_unit \dec30_dec30_function_unit + connect \dec30_in1_sel \dec30_dec30_in1_sel + connect \dec30_in2_sel \dec30_dec30_in2_sel + connect \dec30_in3_sel \dec30_dec30_in3_sel + connect \dec30_internal_op \dec30_dec30_internal_op + connect \dec30_inv_a \dec30_dec30_inv_a + connect \dec30_inv_out \dec30_dec30_inv_out + connect \dec30_is_32b \dec30_dec30_is_32b + connect \dec30_ldst_len \dec30_dec30_ldst_len + connect \dec30_lk \dec30_dec30_lk + connect \dec30_out_sel \dec30_dec30_out_sel + connect \dec30_rc_sel \dec30_dec30_rc_sel + connect \dec30_rsrv \dec30_dec30_rsrv + connect \dec30_sgl_pipe \dec30_dec30_sgl_pipe + connect \dec30_sgn \dec30_dec30_sgn + connect \dec30_sgn_ext \dec30_dec30_sgn_ext + connect \dec30_upd \dec30_dec30_upd + connect \opcode_in \dec30_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:67609.9-67635.4" + cell \dec31 \dec31 + connect \dec31_asmcode \dec31_dec31_asmcode + connect \dec31_br \dec31_dec31_br + connect \dec31_cr_in \dec31_dec31_cr_in + connect \dec31_cr_out \dec31_dec31_cr_out + connect \dec31_cry_in \dec31_dec31_cry_in + connect \dec31_cry_out \dec31_dec31_cry_out + connect \dec31_form \dec31_dec31_form + connect \dec31_function_unit \dec31_dec31_function_unit + connect \dec31_in1_sel \dec31_dec31_in1_sel + connect \dec31_in2_sel \dec31_dec31_in2_sel + connect \dec31_in3_sel \dec31_dec31_in3_sel + connect \dec31_internal_op \dec31_dec31_internal_op + connect \dec31_inv_a \dec31_dec31_inv_a + connect \dec31_inv_out \dec31_dec31_inv_out + connect \dec31_is_32b \dec31_dec31_is_32b + connect \dec31_ldst_len \dec31_dec31_ldst_len + connect \dec31_lk \dec31_dec31_lk + connect \dec31_out_sel \dec31_dec31_out_sel + connect \dec31_rc_sel \dec31_dec31_rc_sel + connect \dec31_rsrv \dec31_dec31_rsrv + connect \dec31_sgl_pipe \dec31_dec31_sgl_pipe + connect \dec31_sgn \dec31_dec31_sgn + connect \dec31_sgn_ext \dec31_dec31_sgn_ext + connect \dec31_upd \dec31_dec31_upd + connect \opcode_in \dec31_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:67636.9-67662.4" + cell \dec58 \dec58 + connect \dec58_asmcode \dec58_dec58_asmcode + connect \dec58_br \dec58_dec58_br + connect \dec58_cr_in \dec58_dec58_cr_in + connect \dec58_cr_out \dec58_dec58_cr_out + connect \dec58_cry_in \dec58_dec58_cry_in + connect \dec58_cry_out \dec58_dec58_cry_out + connect \dec58_form \dec58_dec58_form + connect \dec58_function_unit \dec58_dec58_function_unit + connect \dec58_in1_sel \dec58_dec58_in1_sel + connect \dec58_in2_sel \dec58_dec58_in2_sel + connect \dec58_in3_sel \dec58_dec58_in3_sel + connect \dec58_internal_op \dec58_dec58_internal_op + connect \dec58_inv_a \dec58_dec58_inv_a + connect \dec58_inv_out \dec58_dec58_inv_out + connect \dec58_is_32b \dec58_dec58_is_32b + connect \dec58_ldst_len \dec58_dec58_ldst_len + connect \dec58_lk \dec58_dec58_lk + connect \dec58_out_sel \dec58_dec58_out_sel + connect \dec58_rc_sel \dec58_dec58_rc_sel + connect \dec58_rsrv \dec58_dec58_rsrv + connect \dec58_sgl_pipe \dec58_dec58_sgl_pipe + connect \dec58_sgn \dec58_dec58_sgn + connect \dec58_sgn_ext \dec58_dec58_sgn_ext + connect \dec58_upd \dec58_dec58_upd + connect \opcode_in \dec58_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:67663.9-67689.4" + cell \dec62 \dec62 + connect \dec62_asmcode \dec62_dec62_asmcode + connect \dec62_br \dec62_dec62_br + connect \dec62_cr_in \dec62_dec62_cr_in + connect \dec62_cr_out \dec62_dec62_cr_out + connect \dec62_cry_in \dec62_dec62_cry_in + connect \dec62_cry_out \dec62_dec62_cry_out + connect \dec62_form \dec62_dec62_form + connect \dec62_function_unit \dec62_dec62_function_unit + connect \dec62_in1_sel \dec62_dec62_in1_sel + connect \dec62_in2_sel \dec62_dec62_in2_sel + connect \dec62_in3_sel \dec62_dec62_in3_sel + connect \dec62_internal_op \dec62_dec62_internal_op + connect \dec62_inv_a \dec62_dec62_inv_a + connect \dec62_inv_out \dec62_dec62_inv_out + connect \dec62_is_32b \dec62_dec62_is_32b + connect \dec62_ldst_len \dec62_dec62_ldst_len + connect \dec62_lk \dec62_dec62_lk + connect \dec62_out_sel \dec62_dec62_out_sel + connect \dec62_rc_sel \dec62_dec62_rc_sel + connect \dec62_rsrv \dec62_dec62_rsrv + connect \dec62_sgl_pipe \dec62_dec62_sgl_pipe + connect \dec62_sgn \dec62_dec62_sgn + connect \dec62_sgn_ext \dec62_dec62_sgn_ext + connect \dec62_upd \dec62_dec62_upd + connect \opcode_in \dec62_opcode_in + end + attribute \src "libresoc.v:65497.7-65497.20" + process $proc$libresoc.v:65497$3582 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:67690.3-67828.6" + process $proc$libresoc.v:67690$3558 + assign { } { } + assign { } { } + assign { } { } + assign $0\asmcode[7:0] $2\asmcode[7:0] + attribute \src "libresoc.v:67691.5-67691.29" + switch \initial + attribute \src "libresoc.v:67691.9-67691.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\asmcode[7:0] \dec19_dec19_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\asmcode[7:0] \dec30_dec30_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\asmcode[7:0] \dec31_dec31_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\asmcode[7:0] \dec58_dec58_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\asmcode[7:0] \dec62_dec62_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\asmcode[7:0] 8'00000111 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\asmcode[7:0] 8'00001000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\asmcode[7:0] 8'00000110 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\asmcode[7:0] 8'00001001 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\asmcode[7:0] 8'00010001 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\asmcode[7:0] 8'00010010 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\asmcode[7:0] 8'00010100 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\asmcode[7:0] 8'00010101 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\asmcode[7:0] 8'00011101 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\asmcode[7:0] 8'00011111 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\asmcode[7:0] 8'01001110 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\asmcode[7:0] 8'01001111 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\asmcode[7:0] 8'01011000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\asmcode[7:0] 8'01011010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\asmcode[7:0] 8'01011110 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\asmcode[7:0] 8'01011111 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\asmcode[7:0] 8'01100111 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\asmcode[7:0] 8'01101001 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\asmcode[7:0] 8'10000000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\asmcode[7:0] 8'10001010 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\asmcode[7:0] 8'10001011 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\asmcode[7:0] 8'10011000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\asmcode[7:0] 8'10011001 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\asmcode[7:0] 8'10011010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\asmcode[7:0] 8'10100110 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\asmcode[7:0] 8'10101001 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\asmcode[7:0] 8'10110010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\asmcode[7:0] 8'10110101 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\asmcode[7:0] 8'10111000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\asmcode[7:0] 8'10111011 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\asmcode[7:0] 8'11000011 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\asmcode[7:0] 8'11001011 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\asmcode[7:0] 8'11001111 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\asmcode[7:0] 8'11010001 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\asmcode[7:0] 8'11010010 + case + assign $1\asmcode[7:0] 8'00000000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\asmcode[7:0] 8'00010011 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\asmcode[7:0] 8'10000110 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\asmcode[7:0] 8'10011100 + case + assign $2\asmcode[7:0] $1\asmcode[7:0] + end + sync always + update \asmcode $0\asmcode[7:0] + end + attribute \src "libresoc.v:67829.3-67970.6" + process $proc$libresoc.v:67829$3559 + assign { } { } + assign { } { } + assign { } { } + assign $0\in1_sel[2:0] $2\in1_sel[2:0] + attribute \src "libresoc.v:67830.5-67830.29" + switch \initial + attribute \src "libresoc.v:67830.9-67830.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\in1_sel[2:0] \dec19_dec19_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\in1_sel[2:0] \dec30_dec30_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\in1_sel[2:0] \dec31_dec31_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\in1_sel[2:0] \dec58_dec58_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\in1_sel[2:0] \dec62_dec62_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\in1_sel[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\in1_sel[2:0] 3'100 + case + assign $1\in1_sel[2:0] 3'000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\in1_sel[2:0] 3'000 + case + assign $2\in1_sel[2:0] $1\in1_sel[2:0] + end + sync always + update \in1_sel $0\in1_sel[2:0] + end + attribute \src "libresoc.v:67971.3-68112.6" + process $proc$libresoc.v:67971$3560 + assign { } { } + assign { } { } + assign { } { } + assign $0\in2_sel[3:0] $2\in2_sel[3:0] + attribute \src "libresoc.v:67972.5-67972.29" + switch \initial + attribute \src "libresoc.v:67972.9-67972.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\in2_sel[3:0] \dec19_dec19_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\in2_sel[3:0] \dec30_dec30_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\in2_sel[3:0] \dec31_dec31_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\in2_sel[3:0] \dec58_dec58_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\in2_sel[3:0] \dec62_dec62_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\in2_sel[3:0] 4'0101 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\in2_sel[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\in2_sel[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\in2_sel[3:0] 4'0110 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\in2_sel[3:0] 4'0111 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\in2_sel[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\in2_sel[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\in2_sel[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\in2_sel[3:0] 4'1011 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\in2_sel[3:0] 4'1011 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\in2_sel[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\in2_sel[3:0] 4'0100 + case + assign $1\in2_sel[3:0] 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\in2_sel[3:0] 4'0000 + case + assign $2\in2_sel[3:0] $1\in2_sel[3:0] + end + sync always + update \in2_sel $0\in2_sel[3:0] + end + attribute \src "libresoc.v:68113.3-68254.6" + process $proc$libresoc.v:68113$3561 + assign { } { } + assign { } { } + assign { } { } + assign $0\in3_sel[1:0] $2\in3_sel[1:0] + attribute \src "libresoc.v:68114.5-68114.29" + switch \initial + attribute \src "libresoc.v:68114.9-68114.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\in3_sel[1:0] \dec19_dec19_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\in3_sel[1:0] \dec30_dec30_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\in3_sel[1:0] \dec31_dec31_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\in3_sel[1:0] \dec58_dec58_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\in3_sel[1:0] \dec62_dec62_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + case + assign $1\in3_sel[1:0] 2'00 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\in3_sel[1:0] 2'00 + case + assign $2\in3_sel[1:0] $1\in3_sel[1:0] + end + sync always + update \in3_sel $0\in3_sel[1:0] + end + attribute \src "libresoc.v:68255.3-68396.6" + process $proc$libresoc.v:68255$3562 + assign { } { } + assign { } { } + assign { } { } + assign $0\out_sel[1:0] $2\out_sel[1:0] + attribute \src "libresoc.v:68256.5-68256.29" + switch \initial + attribute \src "libresoc.v:68256.9-68256.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\out_sel[1:0] \dec19_dec19_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\out_sel[1:0] \dec30_dec30_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\out_sel[1:0] \dec31_dec31_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\out_sel[1:0] \dec58_dec58_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\out_sel[1:0] \dec62_dec62_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\out_sel[1:0] 2'11 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\out_sel[1:0] 2'10 + case + assign $1\out_sel[1:0] 2'00 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\out_sel[1:0] 2'01 + case + assign $2\out_sel[1:0] $1\out_sel[1:0] + end + sync always + update \out_sel $0\out_sel[1:0] + end + attribute \src "libresoc.v:68397.3-68538.6" + process $proc$libresoc.v:68397$3563 + assign { } { } + assign { } { } + assign { } { } + assign $0\cr_in[2:0] $2\cr_in[2:0] + attribute \src "libresoc.v:68398.5-68398.29" + switch \initial + attribute \src "libresoc.v:68398.9-68398.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\cr_in[2:0] \dec19_dec19_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\cr_in[2:0] \dec30_dec30_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\cr_in[2:0] \dec31_dec31_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\cr_in[2:0] \dec58_dec58_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\cr_in[2:0] \dec62_dec62_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\cr_in[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\cr_in[2:0] 3'000 + case + assign $1\cr_in[2:0] 3'000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\cr_in[2:0] 3'000 + case + assign $2\cr_in[2:0] $1\cr_in[2:0] + end + sync always + update \cr_in $0\cr_in[2:0] + end + attribute \src "libresoc.v:68539.3-68680.6" + process $proc$libresoc.v:68539$3564 + assign { } { } + assign { } { } + assign { } { } + assign $0\cr_out[2:0] $2\cr_out[2:0] + attribute \src "libresoc.v:68540.5-68540.29" + switch \initial + attribute \src "libresoc.v:68540.9-68540.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\cr_out[2:0] \dec19_dec19_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\cr_out[2:0] \dec30_dec30_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\cr_out[2:0] \dec31_dec31_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\cr_out[2:0] \dec58_dec58_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\cr_out[2:0] \dec62_dec62_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\cr_out[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\cr_out[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\cr_out[2:0] 3'000 + case + assign $1\cr_out[2:0] 3'000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\cr_out[2:0] 3'000 + case + assign $2\cr_out[2:0] $1\cr_out[2:0] + end + sync always + update \cr_out $0\cr_out[2:0] + end + attribute \src "libresoc.v:68681.3-68822.6" + process $proc$libresoc.v:68681$3565 + assign { } { } + assign { } { } + assign { } { } + assign $0\ldst_len[3:0] $2\ldst_len[3:0] + attribute \src "libresoc.v:68682.5-68682.29" + switch \initial + attribute \src "libresoc.v:68682.9-68682.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\ldst_len[3:0] \dec19_dec19_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\ldst_len[3:0] \dec30_dec30_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\ldst_len[3:0] \dec31_dec31_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\ldst_len[3:0] \dec58_dec58_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\ldst_len[3:0] \dec62_dec62_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + case + assign $1\ldst_len[3:0] 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\ldst_len[3:0] 4'0000 + case + assign $2\ldst_len[3:0] $1\ldst_len[3:0] + end + sync always + update \ldst_len $0\ldst_len[3:0] + end + attribute \src "libresoc.v:68823.3-68964.6" + process $proc$libresoc.v:68823$3566 + assign { } { } + assign { } { } + assign { } { } + assign $0\upd[1:0] $2\upd[1:0] + attribute \src "libresoc.v:68824.5-68824.29" + switch \initial + attribute \src "libresoc.v:68824.9-68824.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\upd[1:0] \dec19_dec19_upd + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\upd[1:0] \dec30_dec30_upd + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\upd[1:0] \dec31_dec31_upd + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\upd[1:0] \dec58_dec58_upd + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\upd[1:0] \dec62_dec62_upd + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\upd[1:0] 2'00 + case + assign $1\upd[1:0] 2'00 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\upd[1:0] 2'00 + case + assign $2\upd[1:0] $1\upd[1:0] + end + sync always + update \upd $0\upd[1:0] + end + attribute \src "libresoc.v:68965.3-69106.6" + process $proc$libresoc.v:68965$3567 + assign { } { } + assign { } { } + assign { } { } + assign $0\rc_sel[1:0] $2\rc_sel[1:0] + attribute \src "libresoc.v:68966.5-68966.29" + switch \initial + attribute \src "libresoc.v:68966.9-68966.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\rc_sel[1:0] \dec19_dec19_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\rc_sel[1:0] \dec30_dec30_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\rc_sel[1:0] \dec31_dec31_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\rc_sel[1:0] \dec58_dec58_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\rc_sel[1:0] \dec62_dec62_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\rc_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\rc_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\rc_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + case + assign $1\rc_sel[1:0] 2'00 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\rc_sel[1:0] 2'00 + case + assign $2\rc_sel[1:0] $1\rc_sel[1:0] + end + sync always + update \rc_sel $0\rc_sel[1:0] + end + attribute \src "libresoc.v:69107.3-69248.6" + process $proc$libresoc.v:69107$3568 + assign { } { } + assign { } { } + assign { } { } + assign $0\cry_in[1:0] $2\cry_in[1:0] + attribute \src "libresoc.v:69108.5-69108.29" + switch \initial + attribute \src "libresoc.v:69108.9-69108.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\cry_in[1:0] \dec19_dec19_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\cry_in[1:0] \dec30_dec30_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\cry_in[1:0] \dec31_dec31_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\cry_in[1:0] \dec58_dec58_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\cry_in[1:0] \dec62_dec62_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\cry_in[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\cry_in[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\cry_in[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\cry_in[1:0] 2'00 + case + assign $1\cry_in[1:0] 2'00 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\cry_in[1:0] 2'00 + case + assign $2\cry_in[1:0] $1\cry_in[1:0] + end + sync always + update \cry_in $0\cry_in[1:0] + end + attribute \src "libresoc.v:69249.3-69390.6" + process $proc$libresoc.v:69249$3569 + assign { } { } + assign { } { } + assign { } { } + assign $0\inv_a[0:0] $2\inv_a[0:0] + attribute \src "libresoc.v:69250.5-69250.29" + switch \initial + attribute \src "libresoc.v:69250.9-69250.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\inv_a[0:0] \dec19_dec19_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\inv_a[0:0] \dec30_dec30_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\inv_a[0:0] \dec31_dec31_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\inv_a[0:0] \dec58_dec58_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\inv_a[0:0] \dec62_dec62_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\inv_a[0:0] 1'0 + case + assign $1\inv_a[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\inv_a[0:0] 1'0 + case + assign $2\inv_a[0:0] $1\inv_a[0:0] + end + sync always + update \inv_a $0\inv_a[0:0] + end + attribute \src "libresoc.v:69391.3-69532.6" + process $proc$libresoc.v:69391$3570 + assign { } { } + assign { } { } + assign { } { } + assign $0\inv_out[0:0] $2\inv_out[0:0] + attribute \src "libresoc.v:69392.5-69392.29" + switch \initial + attribute \src "libresoc.v:69392.9-69392.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\inv_out[0:0] \dec19_dec19_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\inv_out[0:0] \dec30_dec30_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\inv_out[0:0] \dec31_dec31_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\inv_out[0:0] \dec58_dec58_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\inv_out[0:0] \dec62_dec62_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\inv_out[0:0] 1'0 + case + assign $1\inv_out[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\inv_out[0:0] 1'0 + case + assign $2\inv_out[0:0] $1\inv_out[0:0] + end + sync always + update \inv_out $0\inv_out[0:0] + end + attribute \src "libresoc.v:69533.3-69674.6" + process $proc$libresoc.v:69533$3571 + assign { } { } + assign { } { } + assign { } { } + assign $0\cry_out[0:0] $2\cry_out[0:0] + attribute \src "libresoc.v:69534.5-69534.29" + switch \initial + attribute \src "libresoc.v:69534.9-69534.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\cry_out[0:0] \dec19_dec19_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\cry_out[0:0] \dec30_dec30_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\cry_out[0:0] \dec31_dec31_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\cry_out[0:0] \dec58_dec58_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\cry_out[0:0] \dec62_dec62_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\cry_out[0:0] 1'0 + case + assign $1\cry_out[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\cry_out[0:0] 1'0 + case + assign $2\cry_out[0:0] $1\cry_out[0:0] + end + sync always + update \cry_out $0\cry_out[0:0] + end + attribute \src "libresoc.v:69675.3-69816.6" + process $proc$libresoc.v:69675$3572 + assign { } { } + assign { } { } + assign { } { } + assign $0\br[0:0] $2\br[0:0] + attribute \src "libresoc.v:69676.5-69676.29" + switch \initial + attribute \src "libresoc.v:69676.9-69676.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\br[0:0] \dec19_dec19_br + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\br[0:0] \dec30_dec30_br + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\br[0:0] \dec31_dec31_br + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\br[0:0] \dec58_dec58_br + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\br[0:0] \dec62_dec62_br + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\br[0:0] 1'0 + case + assign $1\br[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\br[0:0] 1'0 + case + assign $2\br[0:0] $1\br[0:0] + end + sync always + update \br $0\br[0:0] + end + attribute \src "libresoc.v:69817.3-69958.6" + process $proc$libresoc.v:69817$3573 + assign { } { } + assign { } { } + assign { } { } + assign $0\sgn_ext[0:0] $2\sgn_ext[0:0] + attribute \src "libresoc.v:69818.5-69818.29" + switch \initial + attribute \src "libresoc.v:69818.9-69818.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\sgn_ext[0:0] \dec19_dec19_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\sgn_ext[0:0] \dec30_dec30_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\sgn_ext[0:0] \dec31_dec31_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\sgn_ext[0:0] \dec58_dec58_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\sgn_ext[0:0] \dec62_dec62_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\sgn_ext[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\sgn_ext[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + case + assign $1\sgn_ext[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\sgn_ext[0:0] 1'0 + case + assign $2\sgn_ext[0:0] $1\sgn_ext[0:0] + end + sync always + update \sgn_ext $0\sgn_ext[0:0] + end + attribute \src "libresoc.v:69959.3-70100.6" + process $proc$libresoc.v:69959$3574 + assign { } { } + assign { } { } + assign { } { } + assign $0\rsrv[0:0] $2\rsrv[0:0] + attribute \src "libresoc.v:69960.5-69960.29" + switch \initial + attribute \src "libresoc.v:69960.9-69960.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\rsrv[0:0] \dec19_dec19_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\rsrv[0:0] \dec30_dec30_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\rsrv[0:0] \dec31_dec31_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\rsrv[0:0] \dec58_dec58_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\rsrv[0:0] \dec62_dec62_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\rsrv[0:0] 1'0 + case + assign $1\rsrv[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\rsrv[0:0] 1'0 + case + assign $2\rsrv[0:0] $1\rsrv[0:0] + end + sync always + update \rsrv $0\rsrv[0:0] + end + attribute \src "libresoc.v:70101.3-70242.6" + process $proc$libresoc.v:70101$3575 + assign { } { } + assign { } { } + assign { } { } + assign $0\is_32b[0:0] $2\is_32b[0:0] + attribute \src "libresoc.v:70102.5-70102.29" + switch \initial + attribute \src "libresoc.v:70102.9-70102.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\is_32b[0:0] \dec19_dec19_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\is_32b[0:0] \dec30_dec30_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\is_32b[0:0] \dec31_dec31_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\is_32b[0:0] \dec58_dec58_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\is_32b[0:0] \dec62_dec62_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\is_32b[0:0] 1'0 + case + assign $1\is_32b[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\is_32b[0:0] 1'0 + case + assign $2\is_32b[0:0] $1\is_32b[0:0] + end + sync always + update \is_32b $0\is_32b[0:0] + end + attribute \src "libresoc.v:70243.3-70384.6" + process $proc$libresoc.v:70243$3576 + assign { } { } + assign { } { } + assign { } { } + assign $0\sgn[0:0] $2\sgn[0:0] + attribute \src "libresoc.v:70244.5-70244.29" + switch \initial + attribute \src "libresoc.v:70244.9-70244.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\sgn[0:0] \dec19_dec19_sgn + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\sgn[0:0] \dec30_dec30_sgn + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\sgn[0:0] \dec31_dec31_sgn + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\sgn[0:0] \dec58_dec58_sgn + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\sgn[0:0] \dec62_dec62_sgn + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\sgn[0:0] 1'0 + case + assign $1\sgn[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\sgn[0:0] 1'0 + case + assign $2\sgn[0:0] $1\sgn[0:0] + end + sync always + update \sgn $0\sgn[0:0] + end + attribute \src "libresoc.v:70385.3-70526.6" + process $proc$libresoc.v:70385$3577 + assign { } { } + assign { } { } + assign { } { } + assign $0\lk[0:0] $2\lk[0:0] + attribute \src "libresoc.v:70386.5-70386.29" + switch \initial + attribute \src "libresoc.v:70386.9-70386.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\lk[0:0] \dec19_dec19_lk + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\lk[0:0] \dec30_dec30_lk + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\lk[0:0] \dec31_dec31_lk + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\lk[0:0] \dec58_dec58_lk + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\lk[0:0] \dec62_dec62_lk + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\lk[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\lk[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\lk[0:0] 1'0 + case + assign $1\lk[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\lk[0:0] 1'0 + case + assign $2\lk[0:0] $1\lk[0:0] + end + sync always + update \lk $0\lk[0:0] + end + attribute \src "libresoc.v:70527.3-70668.6" + process $proc$libresoc.v:70527$3578 + assign { } { } + assign { } { } + assign { } { } + assign $0\sgl_pipe[0:0] $2\sgl_pipe[0:0] + attribute \src "libresoc.v:70528.5-70528.29" + switch \initial + attribute \src "libresoc.v:70528.9-70528.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\sgl_pipe[0:0] \dec19_dec19_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\sgl_pipe[0:0] \dec30_dec30_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\sgl_pipe[0:0] \dec31_dec31_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\sgl_pipe[0:0] \dec58_dec58_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\sgl_pipe[0:0] \dec62_dec62_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + case + assign $1\sgl_pipe[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\sgl_pipe[0:0] 1'1 + case + assign $2\sgl_pipe[0:0] $1\sgl_pipe[0:0] + end + sync always + update \sgl_pipe $0\sgl_pipe[0:0] + end + attribute \src "libresoc.v:70669.3-70810.6" + process $proc$libresoc.v:70669$3579 + assign { } { } + assign { } { } + assign { } { } + assign $0\function_unit[11:0] $2\function_unit[11:0] + attribute \src "libresoc.v:70670.5-70670.29" + switch \initial + attribute \src "libresoc.v:70670.9-70670.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\function_unit[11:0] \dec19_dec19_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\function_unit[11:0] \dec30_dec30_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\function_unit[11:0] \dec31_dec31_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\function_unit[11:0] \dec58_dec58_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\function_unit[11:0] \dec62_dec62_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\function_unit[11:0] 12'000010000000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\function_unit[11:0] 12'000000100000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\function_unit[11:0] 12'000000100000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\function_unit[11:0] 12'000100000000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\function_unit[11:0] 12'000010000000 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\function_unit[11:0] 12'000010000000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\function_unit[11:0] 12'000000010000 + case + assign $1\function_unit[11:0] 12'000000000000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\function_unit[11:0] 12'000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\function_unit[11:0] 12'000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\function_unit[11:0] 12'000000000000 + case + assign $2\function_unit[11:0] $1\function_unit[11:0] + end + sync always + update \function_unit $0\function_unit[11:0] + end + attribute \src "libresoc.v:70811.3-70952.6" + process $proc$libresoc.v:70811$3580 + assign { } { } + assign { } { } + assign { } { } + assign $0\internal_op[6:0] $2\internal_op[6:0] + attribute \src "libresoc.v:70812.5-70812.29" + switch \initial + attribute \src "libresoc.v:70812.9-70812.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\internal_op[6:0] \dec19_dec19_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\internal_op[6:0] \dec30_dec30_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\internal_op[6:0] \dec31_dec31_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\internal_op[6:0] \dec58_dec58_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\internal_op[6:0] \dec62_dec62_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\internal_op[6:0] 7'1001001 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\internal_op[6:0] 7'0000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\internal_op[6:0] 7'0000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\internal_op[6:0] 7'0000110 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\internal_op[6:0] 7'0000111 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\internal_op[6:0] 7'0001010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\internal_op[6:0] 7'0001010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\internal_op[6:0] 7'0110010 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\internal_op[6:0] 7'0110101 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\internal_op[6:0] 7'0110101 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\internal_op[6:0] 7'0111000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\internal_op[6:0] 7'0111000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\internal_op[6:0] 7'0111000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\internal_op[6:0] 7'0111111 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\internal_op[6:0] 7'0111111 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\internal_op[6:0] 7'1000011 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\internal_op[6:0] 7'1000011 + case + assign $1\internal_op[6:0] 7'0000000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\internal_op[6:0] 7'0000101 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\internal_op[6:0] 7'0000001 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\internal_op[6:0] 7'1000100 + case + assign $2\internal_op[6:0] $1\internal_op[6:0] + end + sync always + update \internal_op $0\internal_op[6:0] + end + attribute \src "libresoc.v:70953.3-71094.6" + process $proc$libresoc.v:70953$3581 + assign { } { } + assign { } { } + assign { } { } + assign $0\form[4:0] $2\form[4:0] + attribute \src "libresoc.v:70954.5-70954.29" + switch \initial + attribute \src "libresoc.v:70954.9-70954.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\form[4:0] \dec19_dec19_form + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\form[4:0] \dec30_dec30_form + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\form[4:0] \dec31_dec31_form + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\form[4:0] \dec58_dec58_form + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\form[4:0] \dec62_dec62_form + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\form[4:0] 5'00011 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\form[4:0] 5'00010 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\form[4:0] 5'00010 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\form[4:0] 5'00001 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\form[4:0] 5'00010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\form[4:0] 5'10011 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\form[4:0] 5'10011 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\form[4:0] 5'10011 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\form[4:0] 5'00100 + case + assign $1\form[4:0] 5'00000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\form[4:0] 5'00000 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\form[4:0] 5'00000 + case + assign $2\form[4:0] $1\form[4:0] + end + sync always + update \form $0\form[4:0] + end + connect \$2 $ternary$libresoc.v:67554$3557_Y + connect \VC_XO \opcode_in [9:0] + connect \VC_VRT \opcode_in [25:21] + connect \VC_VRB \opcode_in [15:11] + connect \VC_VRA \opcode_in [20:16] + connect \VC_Rc \opcode_in [10] + connect \XS_XO \opcode_in [10:2] + connect \XS_sh { \opcode_in [1] \opcode_in [15:11] } + connect \XS_RS \opcode_in [25:21] + connect \XS_Rc \opcode_in [0] + connect \XS_RA \opcode_in [20:16] + connect \VA_XO \opcode_in [5:0] + connect \VA_VRT \opcode_in [25:21] + connect \VA_VRC \opcode_in [10:6] + connect \VA_VRB \opcode_in [15:11] + connect \VA_VRA \opcode_in [20:16] + connect \VA_SHB \opcode_in [9:6] + connect \VA_RT \opcode_in [25:21] + connect \VA_RC \opcode_in [10:6] + connect \VA_RB \opcode_in [15:11] + connect \VA_RA \opcode_in [20:16] + connect \TX_XO \opcode_in [6:1] + connect \TX_XBI \opcode_in [10:7] + connect \TX_UI \opcode_in [15:11] + connect \TX_RA \opcode_in [20:16] + connect \DQE_XO \opcode_in [1:0] + connect \DQE_RT \opcode_in [25:21] + connect \DQE_RA \opcode_in [20:16] + connect \XO_XO \opcode_in [9:1] + connect \XO_RT \opcode_in [25:21] + connect \XO_Rc \opcode_in [0] + connect \XO_RB \opcode_in [15:11] + connect \XO_RA \opcode_in [20:16] + connect \XO_OE \opcode_in [10] + connect \all_PO \opcode_in [31:26] + connect \all_OPCD \opcode_in [31:26] + connect \MD_XO \opcode_in [4:2] + connect \MD_sh { \opcode_in [1] \opcode_in [15:11] } + connect \MD_RS \opcode_in [25:21] + connect \MD_Rc \opcode_in [0] + connect \MD_RA \opcode_in [20:16] + connect \MD_me \opcode_in [10:5] + connect \MD_mb \opcode_in [10:5] + connect \M_SH \opcode_in [15:11] + connect \M_RS \opcode_in [25:21] + connect \M_Rc \opcode_in [0] + connect \M_RB \opcode_in [15:11] + connect \M_RA \opcode_in [20:16] + connect \M_ME \opcode_in [5:1] + connect \M_MB \opcode_in [10:6] + connect \SC_XO_1 \opcode_in [1:0] + connect \SC_XO \opcode_in [1] + connect \SC_LEV \opcode_in [11:5] + connect \MDS_XO \opcode_in [4:1] + connect \MDS_XBI_1 \opcode_in [10:7] + connect \MDS_XBI \opcode_in [10:7] + connect \MDS_RS \opcode_in [25:21] + connect \MDS_Rc \opcode_in [0] + connect \MDS_RB \opcode_in [15:11] + connect \MDS_RA \opcode_in [20:16] + connect \MDS_me \opcode_in [10:5] + connect \MDS_mb \opcode_in [10:5] + connect \MDS_IS \opcode_in [25:21] + connect \MDS_IB \opcode_in [15:11] + connect \Z23_XO \opcode_in [8:1] + connect \Z23_TE \opcode_in [20:16] + connect \Z23_RMC \opcode_in [10:9] + connect \Z23_Rc \opcode_in [0] + connect \Z23_R \opcode_in [16] + connect \Z23_FRTp \opcode_in [25:21] + connect \Z23_FRT \opcode_in [25:21] + connect \Z23_FRBp \opcode_in [15:11] + connect \Z23_FRB \opcode_in [15:11] + connect \Z23_FRAp \opcode_in [20:16] + connect \Z23_FRA \opcode_in [20:16] + connect \XFL_XO \opcode_in [10:1] + connect \XFL_W \opcode_in [16] + connect \XFL_Rc \opcode_in [0] + connect \XFL_L \opcode_in [25] + connect \XFL_FRB \opcode_in [15:11] + connect \XFL_FLM \opcode_in [24:17] + connect \VX_XO_1 \opcode_in [10:0] + connect \VX_XO { \opcode_in [10] \opcode_in [8:0] } + connect \VX_VRT \opcode_in [25:21] + connect \VX_VRB \opcode_in [15:11] + connect \VX_VRA \opcode_in [20:16] + connect \VX_UIM_3 \opcode_in [17:16] + connect \VX_UIM_2 \opcode_in [18:16] + connect \VX_UIM_1 \opcode_in [19:16] + connect \VX_UIM \opcode_in [20:16] + connect \VX_SIM \opcode_in [20:16] + connect \VX_RT \opcode_in [25:21] + connect \VX_RA \opcode_in [20:16] + connect \VX_PS \opcode_in [9] + connect \VX_EO \opcode_in [20:16] + connect \DS_XO \opcode_in [1:0] + connect \DS_VRT \opcode_in [25:21] + connect \DS_VRS \opcode_in [25:21] + connect \DS_RT \opcode_in [25:21] + connect \DS_RSp \opcode_in [25:21] + connect \DS_RS \opcode_in [25:21] + connect \DS_RA \opcode_in [20:16] + connect \DS_FRTp \opcode_in [25:21] + connect \DS_FRSp \opcode_in [25:21] + connect \DS_DS \opcode_in [15:2] + connect \DQ_XO \opcode_in [2:0] + connect \DQ_TX_T { \opcode_in [3] \opcode_in [25:21] } + connect \DQ_T \opcode_in [25:21] + connect \DQ_TX \opcode_in [3] + connect \DQ_SX_S { \opcode_in [3] \opcode_in [25:21] } + connect \DQ_S \opcode_in [25:21] + connect \DQ_SX \opcode_in [3] + connect \DQ_RTp \opcode_in [25:21] + connect \DQ_RA \opcode_in [20:16] + connect \DQ_PT \opcode_in [3:0] + connect \DQ_DQ \opcode_in [15:4] + connect \DX_XO \opcode_in [5:1] + connect \DX_RT \opcode_in [25:21] + connect \DX_d0_d1_d2 { \opcode_in [15:6] \opcode_in [20:16] \opcode_in [0] } + connect \DX_d2 \opcode_in [0] + connect \DX_d1 \opcode_in [20:16] + connect \DX_d0 \opcode_in [15:6] + connect \XFX_XO \opcode_in [10:1] + connect \XFX_SPR \opcode_in [20:11] + connect \XFX_RT \opcode_in [25:21] + connect \XFX_RS \opcode_in [25:21] + connect \XFX_FXM \opcode_in [19:12] + connect \XFX_DUIS \opcode_in [20:11] + connect \XFX_DUI \opcode_in [25:21] + connect \XFX_BHRBE \opcode_in [20:11] + connect \EVS_BFA \opcode_in [2:0] + connect \Z22_XO \opcode_in [9:1] + connect \Z22_SH \opcode_in [15:10] + connect \Z22_Rc \opcode_in [0] + connect \Z22_FRTp \opcode_in [25:21] + connect \Z22_FRT \opcode_in [25:21] + connect \Z22_FRAp \opcode_in [20:16] + connect \Z22_FRA \opcode_in [20:16] + connect \Z22_DGM \opcode_in [15:10] + connect \Z22_DCM \opcode_in [15:10] + connect \Z22_BF \opcode_in [25:23] + connect \XX2_XO_1 \opcode_in [10:2] + connect \XX2_XO { \opcode_in [10:7] \opcode_in [5:3] } + connect \XX2_UIM_1 \opcode_in [17:16] + connect \XX2_UIM \opcode_in [19:16] + connect \XX2_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX2_T \opcode_in [25:21] + connect \XX2_TX \opcode_in [0] + connect \XX2_RT \opcode_in [25:21] + connect \XX2_EO \opcode_in [20:16] + connect \XX2_DCMX \opcode_in [22:16] + connect \XX2_dc_dm_dx { \opcode_in [6] \opcode_in [2] \opcode_in [20:16] } + connect \XX2_dx \opcode_in [20:16] + connect \XX2_dm \opcode_in [2] + connect \XX2_dc \opcode_in [6] + connect \XX2_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX2_B \opcode_in [15:11] + connect \XX2_BX \opcode_in [1] + connect \XX2_BF \opcode_in [25:23] + connect \D_UI \opcode_in [15:0] + connect \D_TO \opcode_in [25:21] + connect \D_SI \opcode_in [15:0] + connect \D_RT \opcode_in [25:21] + connect \D_RS \opcode_in [25:21] + connect \D_RA \opcode_in [20:16] + connect \D_L \opcode_in [21] + connect \D_FRT \opcode_in [25:21] + connect \D_FRS \opcode_in [25:21] + connect \D_D \opcode_in [15:0] + connect \D_BF \opcode_in [25:23] + connect \A_XO \opcode_in [5:1] + connect \A_RT \opcode_in [25:21] + connect \A_Rc \opcode_in [0] + connect \A_RB \opcode_in [15:11] + connect \A_RA \opcode_in [20:16] + connect \A_FRT \opcode_in [25:21] + connect \A_FRC \opcode_in [10:6] + connect \A_FRB \opcode_in [15:11] + connect \A_FRA \opcode_in [20:16] + connect \A_BC \opcode_in [10:6] + connect \XL_XO \opcode_in [10:1] + connect \XL_S \opcode_in [11] + connect \XL_OC \opcode_in [25:11] + connect \XL_LK \opcode_in [0] + connect \XL_BT \opcode_in [25:21] + connect \XL_BO_1 \opcode_in [25:21] + connect \XL_BO \opcode_in [25:21] + connect \XL_BI \opcode_in [20:16] + connect \XL_BH \opcode_in [12:11] + connect \XL_BFA \opcode_in [20:18] + connect \XL_BF \opcode_in [25:23] + connect \XL_BB \opcode_in [15:11] + connect \XL_BA \opcode_in [20:16] + connect \XX4_XO \opcode_in [5:4] + connect \XX4_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX4_T \opcode_in [25:21] + connect \XX4_TX \opcode_in [0] + connect \XX4_CX_C { \opcode_in [3] \opcode_in [10:6] } + connect \XX4_C \opcode_in [10:6] + connect \XX4_CX \opcode_in [3] + connect \XX4_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX4_B \opcode_in [15:11] + connect \XX4_BX \opcode_in [1] + connect \XX4_AX_A { \opcode_in [2] \opcode_in [20:16] } + connect \XX4_A \opcode_in [20:16] + connect \XX4_AX \opcode_in [2] + connect \XX3_XO_2 \opcode_in [9:1] + connect \XX3_XO_1 \opcode_in [10:3] + connect \XX3_XO \opcode_in [10:7] + connect \XX3_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX3_T \opcode_in [25:21] + connect \XX3_TX \opcode_in [0] + connect \XX3_SHW \opcode_in [9:8] + connect \XX3_Rc \opcode_in [10] + connect \XX3_DM \opcode_in [9:8] + connect \XX3_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX3_B \opcode_in [15:11] + connect \XX3_BX \opcode_in [1] + connect \XX3_BF \opcode_in [25:23] + connect \XX3_AX_A { \opcode_in [2] \opcode_in [20:16] } + connect \XX3_A \opcode_in [20:16] + connect \XX3_AX \opcode_in [2] + connect \I_LK \opcode_in [0] + connect \I_LI \opcode_in [25:2] + connect \I_AA \opcode_in [1] + connect \B_LK \opcode_in [0] + connect \B_BO \opcode_in [25:21] + connect \B_BI \opcode_in [20:16] + connect \B_BD \opcode_in [15:2] + connect \B_AA \opcode_in [1] + connect \X_XO_1 \opcode_in [8:1] + connect \X_XO \opcode_in [10:1] + connect \X_WC \opcode_in [22:21] + connect \X_W \opcode_in [16] + connect \X_VRT \opcode_in [25:21] + connect \X_VRS \opcode_in [25:21] + connect \X_UIM \opcode_in [20:16] + connect \X_U \opcode_in [15:12] + connect \X_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \X_TX \opcode_in [0] + connect \X_TO \opcode_in [25:21] + connect \X_TH \opcode_in [25:21] + connect \X_TBR \opcode_in [20:11] + connect \X_T \opcode_in [25:21] + connect \X_SX_S { \opcode_in [0] \opcode_in [25:21] } + connect \X_SX \opcode_in [0] + connect \X_SR \opcode_in [19:16] + connect \X_SP \opcode_in [20:19] + connect \X_SI \opcode_in [15:11] + connect \X_SH \opcode_in [15:11] + connect \X_S \opcode_in [25:21] + connect \X_RTp \opcode_in [25:21] + connect \X_RT \opcode_in [25:21] + connect \X_RSp \opcode_in [25:21] + connect \X_RS \opcode_in [25:21] + connect \X_RO \opcode_in [0] + connect \X_RM \opcode_in [12:11] + connect \X_RIC \opcode_in [19:18] + connect \X_Rc \opcode_in [0] + connect \X_RB \opcode_in [15:11] + connect \X_RA \opcode_in [20:16] + connect \X_R_1 \opcode_in [16] + connect \X_R \opcode_in [21] + connect \X_PRS \opcode_in [17] + connect \X_NB \opcode_in [15:11] + connect \X_MO \opcode_in [25:21] + connect \X_L3 \opcode_in [17:16] + connect \X_L1 \opcode_in [16] + connect \X_L \opcode_in [21] + connect \X_L2 \opcode_in [22:21] + connect \X_IMM8 \opcode_in [18:11] + connect \X_IH \opcode_in [23:21] + connect \X_FRTp \opcode_in [25:21] + connect \X_FRT \opcode_in [25:21] + connect \X_FRSp \opcode_in [25:21] + connect \X_FRS \opcode_in [25:21] + connect \X_FRBp \opcode_in [15:11] + connect \X_FRB \opcode_in [15:11] + connect \X_FRAp \opcode_in [20:16] + connect \X_FRA \opcode_in [20:16] + connect \X_FC \opcode_in [15:11] + connect \X_EX \opcode_in [0] + connect \X_EO_1 \opcode_in [20:16] + connect \X_EO \opcode_in [20:19] + connect \X_E_1 \opcode_in [19:16] + connect \X_E \opcode_in [15] + connect \X_DRM \opcode_in [13:11] + connect \X_DCMX \opcode_in [22:16] + connect \X_CT \opcode_in [24:21] + connect \X_BO \opcode_in [25:21] + connect \X_BFA \opcode_in [20:18] + connect \X_BF \opcode_in [25:23] + connect \X_A \opcode_in [25] + connect \SPR \opcode_in [20:11] + connect \MB \opcode_in [10:6] + connect \ME \opcode_in [5:1] + connect \SH \opcode_in [15:11] + connect \BC \opcode_in [10:6] + connect \TO \opcode_in [25:21] + connect \DS \opcode_in [15:2] + connect \D \opcode_in [15:0] + connect \BH \opcode_in [12:11] + connect \BI \opcode_in [20:16] + connect \BO \opcode_in [25:21] + connect \FXM \opcode_in [19:12] + connect \BT \opcode_in [25:21] + connect \BA \opcode_in [20:16] + connect \BB \opcode_in [15:11] + connect \CR \opcode_in [10:1] + connect \BF \opcode_in [25:23] + connect \BD \opcode_in [15:2] + connect \OE \opcode_in [10] + connect \Rc \opcode_in [0] + connect \AA \opcode_in [1] + connect \LK \opcode_in [0] + connect \LI \opcode_in [25:2] + connect \ME32 \opcode_in [5:1] + connect \MB32 \opcode_in [10:6] + connect \sh { \opcode_in [1] \opcode_in [15:11] } + connect \SH32 \opcode_in [15:11] + connect \L \opcode_in [21] + connect \UI \opcode_in [15:0] + connect \SI \opcode_in [15:0] + connect \RB \opcode_in [15:11] + connect \RA \opcode_in [20:16] + connect \RT \opcode_in [25:21] + connect \RS \opcode_in [25:21] + connect \opcode_in \$2 + connect \opcode_switch$1 \opcode_in + connect \dec62_opcode_in \opcode_in + connect \dec58_opcode_in \opcode_in + connect \dec31_opcode_in \opcode_in + connect \dec30_opcode_in \opcode_in + connect \dec19_opcode_in \opcode_in + connect \opcode_switch \opcode_in [31:26] +end +attribute \src "libresoc.v:71433.1-72940.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec19" +attribute \generator "nMigen" +module \dec19 + attribute \src "libresoc.v:71951.3-72002.6" + wire width 8 $0\dec19_asmcode[7:0] + attribute \src "libresoc.v:72159.3-72210.6" + wire $0\dec19_br[0:0] + attribute \src "libresoc.v:72835.3-72886.6" + wire width 3 $0\dec19_cr_in[2:0] + attribute \src "libresoc.v:72887.3-72938.6" + wire width 3 $0\dec19_cr_out[2:0] + attribute \src "libresoc.v:71899.3-71950.6" + wire width 2 $0\dec19_cry_in[1:0] + attribute \src "libresoc.v:72107.3-72158.6" + wire $0\dec19_cry_out[0:0] + attribute \src "libresoc.v:72575.3-72626.6" + wire width 5 $0\dec19_form[4:0] + attribute \src "libresoc.v:71691.3-71742.6" + wire width 12 $0\dec19_function_unit[11:0] + attribute \src "libresoc.v:72627.3-72678.6" + wire width 3 $0\dec19_in1_sel[2:0] + attribute \src "libresoc.v:72679.3-72730.6" + wire width 4 $0\dec19_in2_sel[3:0] + attribute \src "libresoc.v:72731.3-72782.6" + wire width 2 $0\dec19_in3_sel[1:0] + attribute \src "libresoc.v:72263.3-72314.6" + wire width 7 $0\dec19_internal_op[6:0] + attribute \src "libresoc.v:72003.3-72054.6" + wire $0\dec19_inv_a[0:0] + attribute \src "libresoc.v:72055.3-72106.6" + wire $0\dec19_inv_out[0:0] + attribute \src "libresoc.v:72367.3-72418.6" + wire $0\dec19_is_32b[0:0] + attribute \src "libresoc.v:71743.3-71794.6" + wire width 4 $0\dec19_ldst_len[3:0] + attribute \src "libresoc.v:72471.3-72522.6" + wire $0\dec19_lk[0:0] + attribute \src "libresoc.v:72783.3-72834.6" + wire width 2 $0\dec19_out_sel[1:0] + attribute \src "libresoc.v:71847.3-71898.6" + wire width 2 $0\dec19_rc_sel[1:0] + attribute \src "libresoc.v:72315.3-72366.6" + wire $0\dec19_rsrv[0:0] + attribute \src "libresoc.v:72523.3-72574.6" + wire $0\dec19_sgl_pipe[0:0] + attribute \src "libresoc.v:72419.3-72470.6" + wire $0\dec19_sgn[0:0] + attribute \src "libresoc.v:72211.3-72262.6" + wire $0\dec19_sgn_ext[0:0] + attribute \src "libresoc.v:71795.3-71846.6" + wire width 2 $0\dec19_upd[1:0] + attribute \src "libresoc.v:71434.7-71434.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:71951.3-72002.6" + wire width 8 $1\dec19_asmcode[7:0] + attribute \src "libresoc.v:72159.3-72210.6" + wire $1\dec19_br[0:0] + attribute \src "libresoc.v:72835.3-72886.6" + wire width 3 $1\dec19_cr_in[2:0] + attribute \src "libresoc.v:72887.3-72938.6" + wire width 3 $1\dec19_cr_out[2:0] + attribute \src "libresoc.v:71899.3-71950.6" + wire width 2 $1\dec19_cry_in[1:0] + attribute \src "libresoc.v:72107.3-72158.6" + wire $1\dec19_cry_out[0:0] + attribute \src "libresoc.v:72575.3-72626.6" + wire width 5 $1\dec19_form[4:0] + attribute \src "libresoc.v:71691.3-71742.6" + wire width 12 $1\dec19_function_unit[11:0] + attribute \src "libresoc.v:72627.3-72678.6" + wire width 3 $1\dec19_in1_sel[2:0] + attribute \src "libresoc.v:72679.3-72730.6" + wire width 4 $1\dec19_in2_sel[3:0] + attribute \src "libresoc.v:72731.3-72782.6" + wire width 2 $1\dec19_in3_sel[1:0] + attribute \src "libresoc.v:72263.3-72314.6" + wire width 7 $1\dec19_internal_op[6:0] + attribute \src "libresoc.v:72003.3-72054.6" + wire $1\dec19_inv_a[0:0] + attribute \src "libresoc.v:72055.3-72106.6" + wire $1\dec19_inv_out[0:0] + attribute \src "libresoc.v:72367.3-72418.6" + wire $1\dec19_is_32b[0:0] + attribute \src "libresoc.v:71743.3-71794.6" + wire width 4 $1\dec19_ldst_len[3:0] + attribute \src "libresoc.v:72471.3-72522.6" + wire $1\dec19_lk[0:0] + attribute \src "libresoc.v:72783.3-72834.6" + wire width 2 $1\dec19_out_sel[1:0] + attribute \src "libresoc.v:71847.3-71898.6" + wire width 2 $1\dec19_rc_sel[1:0] + attribute \src "libresoc.v:72315.3-72366.6" + wire $1\dec19_rsrv[0:0] + attribute \src "libresoc.v:72523.3-72574.6" + wire $1\dec19_sgl_pipe[0:0] + attribute \src "libresoc.v:72419.3-72470.6" + wire $1\dec19_sgn[0:0] + attribute \src "libresoc.v:72211.3-72262.6" + wire $1\dec19_sgn_ext[0:0] + attribute \src "libresoc.v:71795.3-71846.6" + wire width 2 $1\dec19_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 output 4 \dec19_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 18 \dec19_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 9 \dec19_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 10 \dec19_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 14 \dec19_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 17 \dec19_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 output 3 \dec19_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \dec19_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \dec19_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 6 \dec19_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 7 \dec19_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \dec19_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 15 \dec19_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 16 \dec19_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 21 \dec19_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 11 \dec19_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 23 \dec19_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 8 \dec19_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 13 \dec19_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 20 \dec19_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 24 \dec19_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 22 \dec19_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 19 \dec19_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 12 \dec19_upd + attribute \src "libresoc.v:71434.7-71434.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 10 \opcode_switch + attribute \src "libresoc.v:71434.7-71434.20" + process $proc$libresoc.v:71434$3607 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:71691.3-71742.6" + process $proc$libresoc.v:71691$3583 + assign { } { } + assign { } { } + assign $0\dec19_function_unit[11:0] $1\dec19_function_unit[11:0] + attribute \src "libresoc.v:71692.5-71692.29" + switch \initial + attribute \src "libresoc.v:71692.9-71692.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_function_unit[11:0] 12'000000100000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_function_unit[11:0] 12'000000100000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_function_unit[11:0] 12'000000100000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_function_unit[11:0] 12'000010000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_function_unit[11:0] 12'000010000000 + case + assign $1\dec19_function_unit[11:0] 12'000000000000 + end + sync always + update \dec19_function_unit $0\dec19_function_unit[11:0] + end + attribute \src "libresoc.v:71743.3-71794.6" + process $proc$libresoc.v:71743$3584 + assign { } { } + assign { } { } + assign $0\dec19_ldst_len[3:0] $1\dec19_ldst_len[3:0] + attribute \src "libresoc.v:71744.5-71744.29" + switch \initial + attribute \src "libresoc.v:71744.9-71744.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_ldst_len[3:0] 4'0000 + case + assign $1\dec19_ldst_len[3:0] 4'0000 + end + sync always + update \dec19_ldst_len $0\dec19_ldst_len[3:0] + end + attribute \src "libresoc.v:71795.3-71846.6" + process $proc$libresoc.v:71795$3585 + assign { } { } + assign { } { } + assign $0\dec19_upd[1:0] $1\dec19_upd[1:0] + attribute \src "libresoc.v:71796.5-71796.29" + switch \initial + attribute \src "libresoc.v:71796.9-71796.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_upd[1:0] 2'00 + case + assign $1\dec19_upd[1:0] 2'00 + end + sync always + update \dec19_upd $0\dec19_upd[1:0] + end + attribute \src "libresoc.v:71847.3-71898.6" + process $proc$libresoc.v:71847$3586 + assign { } { } + assign { } { } + assign $0\dec19_rc_sel[1:0] $1\dec19_rc_sel[1:0] + attribute \src "libresoc.v:71848.5-71848.29" + switch \initial + attribute \src "libresoc.v:71848.9-71848.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_rc_sel[1:0] 2'00 + case + assign $1\dec19_rc_sel[1:0] 2'00 + end + sync always + update \dec19_rc_sel $0\dec19_rc_sel[1:0] + end + attribute \src "libresoc.v:71899.3-71950.6" + process $proc$libresoc.v:71899$3587 + assign { } { } + assign { } { } + assign $0\dec19_cry_in[1:0] $1\dec19_cry_in[1:0] + attribute \src "libresoc.v:71900.5-71900.29" + switch \initial + attribute \src "libresoc.v:71900.9-71900.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_cry_in[1:0] 2'00 + case + assign $1\dec19_cry_in[1:0] 2'00 + end + sync always + update \dec19_cry_in $0\dec19_cry_in[1:0] + end + attribute \src "libresoc.v:71951.3-72002.6" + process $proc$libresoc.v:71951$3588 + assign { } { } + assign { } { } + assign $0\dec19_asmcode[7:0] $1\dec19_asmcode[7:0] + attribute \src "libresoc.v:71952.5-71952.29" + switch \initial + attribute \src "libresoc.v:71952.9-71952.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_asmcode[7:0] 8'01101100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_asmcode[7:0] 8'00100101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_asmcode[7:0] 8'00100110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_asmcode[7:0] 8'00100111 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_asmcode[7:0] 8'00101000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_asmcode[7:0] 8'00101001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_asmcode[7:0] 8'00101010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_asmcode[7:0] 8'00101011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_asmcode[7:0] 8'00101100 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_asmcode[7:0] 8'00010110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_asmcode[7:0] 8'00010111 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_asmcode[7:0] 8'00011000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_asmcode[7:0] 8'01001100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_asmcode[7:0] 8'10010001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_asmcode[7:0] 8'01001000 + case + assign $1\dec19_asmcode[7:0] 8'00000000 + end + sync always + update \dec19_asmcode $0\dec19_asmcode[7:0] + end + attribute \src "libresoc.v:72003.3-72054.6" + process $proc$libresoc.v:72003$3589 + assign { } { } + assign { } { } + assign $0\dec19_inv_a[0:0] $1\dec19_inv_a[0:0] + attribute \src "libresoc.v:72004.5-72004.29" + switch \initial + attribute \src "libresoc.v:72004.9-72004.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_inv_a[0:0] 1'0 + case + assign $1\dec19_inv_a[0:0] 1'0 + end + sync always + update \dec19_inv_a $0\dec19_inv_a[0:0] + end + attribute \src "libresoc.v:72055.3-72106.6" + process $proc$libresoc.v:72055$3590 + assign { } { } + assign { } { } + assign $0\dec19_inv_out[0:0] $1\dec19_inv_out[0:0] + attribute \src "libresoc.v:72056.5-72056.29" + switch \initial + attribute \src "libresoc.v:72056.9-72056.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + case + assign $1\dec19_inv_out[0:0] 1'0 + end + sync always + update \dec19_inv_out $0\dec19_inv_out[0:0] + end + attribute \src "libresoc.v:72107.3-72158.6" + process $proc$libresoc.v:72107$3591 + assign { } { } + assign { } { } + assign $0\dec19_cry_out[0:0] $1\dec19_cry_out[0:0] + attribute \src "libresoc.v:72108.5-72108.29" + switch \initial + attribute \src "libresoc.v:72108.9-72108.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + case + assign $1\dec19_cry_out[0:0] 1'0 + end + sync always + update \dec19_cry_out $0\dec19_cry_out[0:0] + end + attribute \src "libresoc.v:72159.3-72210.6" + process $proc$libresoc.v:72159$3592 + assign { } { } + assign { } { } + assign $0\dec19_br[0:0] $1\dec19_br[0:0] + attribute \src "libresoc.v:72160.5-72160.29" + switch \initial + attribute \src "libresoc.v:72160.9-72160.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + case + assign $1\dec19_br[0:0] 1'0 + end + sync always + update \dec19_br $0\dec19_br[0:0] + end + attribute \src "libresoc.v:72211.3-72262.6" + process $proc$libresoc.v:72211$3593 + assign { } { } + assign { } { } + assign $0\dec19_sgn_ext[0:0] $1\dec19_sgn_ext[0:0] + attribute \src "libresoc.v:72212.5-72212.29" + switch \initial + attribute \src "libresoc.v:72212.9-72212.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + case + assign $1\dec19_sgn_ext[0:0] 1'0 + end + sync always + update \dec19_sgn_ext $0\dec19_sgn_ext[0:0] + end + attribute \src "libresoc.v:72263.3-72314.6" + process $proc$libresoc.v:72263$3594 + assign { } { } + assign { } { } + assign $0\dec19_internal_op[6:0] $1\dec19_internal_op[6:0] + attribute \src "libresoc.v:72264.5-72264.29" + switch \initial + attribute \src "libresoc.v:72264.9-72264.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_internal_op[6:0] 7'0101010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_internal_op[6:0] 7'1000101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_internal_op[6:0] 7'1000101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_internal_op[6:0] 7'1000101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_internal_op[6:0] 7'1000101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_internal_op[6:0] 7'1000101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_internal_op[6:0] 7'1000101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_internal_op[6:0] 7'1000101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_internal_op[6:0] 7'1000101 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_internal_op[6:0] 7'0001000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_internal_op[6:0] 7'0001000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_internal_op[6:0] 7'0001000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_internal_op[6:0] 7'0100100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_internal_op[6:0] 7'1000110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_internal_op[6:0] 7'1000110 + case + assign $1\dec19_internal_op[6:0] 7'0000000 + end + sync always + update \dec19_internal_op $0\dec19_internal_op[6:0] + end + attribute \src "libresoc.v:72315.3-72366.6" + process $proc$libresoc.v:72315$3595 + assign { } { } + assign { } { } + assign $0\dec19_rsrv[0:0] $1\dec19_rsrv[0:0] + attribute \src "libresoc.v:72316.5-72316.29" + switch \initial + attribute \src "libresoc.v:72316.9-72316.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_rsrv[0:0] 1'0 + case + assign $1\dec19_rsrv[0:0] 1'0 + end + sync always + update \dec19_rsrv $0\dec19_rsrv[0:0] + end + attribute \src "libresoc.v:72367.3-72418.6" + process $proc$libresoc.v:72367$3596 + assign { } { } + assign { } { } + assign $0\dec19_is_32b[0:0] $1\dec19_is_32b[0:0] + attribute \src "libresoc.v:72368.5-72368.29" + switch \initial + attribute \src "libresoc.v:72368.9-72368.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_is_32b[0:0] 1'0 + case + assign $1\dec19_is_32b[0:0] 1'0 + end + sync always + update \dec19_is_32b $0\dec19_is_32b[0:0] + end + attribute \src "libresoc.v:72419.3-72470.6" + process $proc$libresoc.v:72419$3597 + assign { } { } + assign { } { } + assign $0\dec19_sgn[0:0] $1\dec19_sgn[0:0] + attribute \src "libresoc.v:72420.5-72420.29" + switch \initial + attribute \src "libresoc.v:72420.9-72420.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_sgn[0:0] 1'0 + case + assign $1\dec19_sgn[0:0] 1'0 + end + sync always + update \dec19_sgn $0\dec19_sgn[0:0] + end + attribute \src "libresoc.v:72471.3-72522.6" + process $proc$libresoc.v:72471$3598 + assign { } { } + assign { } { } + assign $0\dec19_lk[0:0] $1\dec19_lk[0:0] + attribute \src "libresoc.v:72472.5-72472.29" + switch \initial + attribute \src "libresoc.v:72472.9-72472.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_lk[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_lk[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_lk[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_lk[0:0] 1'0 + case + assign $1\dec19_lk[0:0] 1'0 + end + sync always + update \dec19_lk $0\dec19_lk[0:0] + end + attribute \src "libresoc.v:72523.3-72574.6" + process $proc$libresoc.v:72523$3599 + assign { } { } + assign { } { } + assign $0\dec19_sgl_pipe[0:0] $1\dec19_sgl_pipe[0:0] + attribute \src "libresoc.v:72524.5-72524.29" + switch \initial + attribute \src "libresoc.v:72524.9-72524.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_sgl_pipe[0:0] 1'0 + case + assign $1\dec19_sgl_pipe[0:0] 1'0 + end + sync always + update \dec19_sgl_pipe $0\dec19_sgl_pipe[0:0] + end + attribute \src "libresoc.v:72575.3-72626.6" + process $proc$libresoc.v:72575$3600 + assign { } { } + assign { } { } + assign $0\dec19_form[4:0] $1\dec19_form[4:0] + attribute \src "libresoc.v:72576.5-72576.29" + switch \initial + attribute \src "libresoc.v:72576.9-72576.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_form[4:0] 5'01001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_form[4:0] 5'01001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_form[4:0] 5'01001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_form[4:0] 5'01001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_form[4:0] 5'01001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_form[4:0] 5'01001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_form[4:0] 5'01001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_form[4:0] 5'01001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_form[4:0] 5'01001 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_form[4:0] 5'01001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_form[4:0] 5'01001 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_form[4:0] 5'01001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_form[4:0] 5'01001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_form[4:0] 5'01001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_form[4:0] 5'01001 + case + assign $1\dec19_form[4:0] 5'00000 + end + sync always + update \dec19_form $0\dec19_form[4:0] + end + attribute \src "libresoc.v:72627.3-72678.6" + process $proc$libresoc.v:72627$3601 + assign { } { } + assign { } { } + assign $0\dec19_in1_sel[2:0] $1\dec19_in1_sel[2:0] + attribute \src "libresoc.v:72628.5-72628.29" + switch \initial + attribute \src "libresoc.v:72628.9-72628.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_in1_sel[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_in1_sel[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_in1_sel[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_in1_sel[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_in1_sel[2:0] 3'011 + case + assign $1\dec19_in1_sel[2:0] 3'000 + end + sync always + update \dec19_in1_sel $0\dec19_in1_sel[2:0] + end + attribute \src "libresoc.v:72679.3-72730.6" + process $proc$libresoc.v:72679$3602 + assign { } { } + assign { } { } + assign $0\dec19_in2_sel[3:0] $1\dec19_in2_sel[3:0] + attribute \src "libresoc.v:72680.5-72680.29" + switch \initial + attribute \src "libresoc.v:72680.9-72680.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_in2_sel[3:0] 4'1100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_in2_sel[3:0] 4'1100 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_in2_sel[3:0] 4'1100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_in2_sel[3:0] 4'1100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_in2_sel[3:0] 4'1100 + case + assign $1\dec19_in2_sel[3:0] 4'0000 + end + sync always + update \dec19_in2_sel $0\dec19_in2_sel[3:0] + end + attribute \src "libresoc.v:72731.3-72782.6" + process $proc$libresoc.v:72731$3603 + assign { } { } + assign { } { } + assign $0\dec19_in3_sel[1:0] $1\dec19_in3_sel[1:0] + attribute \src "libresoc.v:72732.5-72732.29" + switch \initial + attribute \src "libresoc.v:72732.9-72732.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_in3_sel[1:0] 2'00 + case + assign $1\dec19_in3_sel[1:0] 2'00 + end + sync always + update \dec19_in3_sel $0\dec19_in3_sel[1:0] + end + attribute \src "libresoc.v:72783.3-72834.6" + process $proc$libresoc.v:72783$3604 + assign { } { } + assign { } { } + assign $0\dec19_out_sel[1:0] $1\dec19_out_sel[1:0] + attribute \src "libresoc.v:72784.5-72784.29" + switch \initial + attribute \src "libresoc.v:72784.9-72784.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_out_sel[1:0] 2'11 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_out_sel[1:0] 2'11 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_out_sel[1:0] 2'11 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_out_sel[1:0] 2'00 + case + assign $1\dec19_out_sel[1:0] 2'00 + end + sync always + update \dec19_out_sel $0\dec19_out_sel[1:0] + end + attribute \src "libresoc.v:72835.3-72886.6" + process $proc$libresoc.v:72835$3605 + assign { } { } + assign { } { } + assign $0\dec19_cr_in[2:0] $1\dec19_cr_in[2:0] + attribute \src "libresoc.v:72836.5-72836.29" + switch \initial + attribute \src "libresoc.v:72836.9-72836.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_cr_in[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_cr_in[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_cr_in[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_cr_in[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_cr_in[2:0] 3'000 + case + assign $1\dec19_cr_in[2:0] 3'000 + end + sync always + update \dec19_cr_in $0\dec19_cr_in[2:0] + end + attribute \src "libresoc.v:72887.3-72938.6" + process $proc$libresoc.v:72887$3606 + assign { } { } + assign { } { } + assign $0\dec19_cr_out[2:0] $1\dec19_cr_out[2:0] + attribute \src "libresoc.v:72888.5-72888.29" + switch \initial + attribute \src "libresoc.v:72888.9-72888.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_cr_out[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_cr_out[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_cr_out[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_cr_out[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_cr_out[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_cr_out[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_cr_out[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_cr_out[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_cr_out[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_cr_out[2:0] 3'000 + case + assign $1\dec19_cr_out[2:0] 3'000 + end + sync always + update \dec19_cr_out $0\dec19_cr_out[2:0] + end + connect \opcode_switch \opcode_in [10:1] +end +attribute \src "libresoc.v:72944.1-74833.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.dec2" +attribute \generator "nMigen" +module \dec2 + attribute \src "libresoc.v:74699.3-74780.6" + wire width 8 $0\asmcode[7:0] + attribute \src "libresoc.v:74699.3-74780.6" + wire width 64 $0\cia[63:0] + attribute \src "libresoc.v:74699.3-74780.6" + wire width 3 $0\cr_in1[2:0] + attribute \src "libresoc.v:74699.3-74780.6" + wire $0\cr_in1_ok[0:0] + attribute \src "libresoc.v:74699.3-74780.6" + wire width 3 $0\cr_in2$1[2:0]$3626 + attribute \src "libresoc.v:74699.3-74780.6" + wire width 3 $0\cr_in2[2:0] + attribute \src "libresoc.v:74699.3-74780.6" + wire $0\cr_in2_ok$2[0:0]$3627 + attribute \src "libresoc.v:74699.3-74780.6" + wire $0\cr_in2_ok[0:0] + attribute \src "libresoc.v:74699.3-74780.6" + wire width 3 $0\cr_out[2:0] + attribute \src "libresoc.v:74699.3-74780.6" + wire $0\cr_out_ok[0:0] + attribute \src "libresoc.v:74699.3-74780.6" + wire width 8 $0\cr_rd[7:0] + attribute \src "libresoc.v:74699.3-74780.6" + wire $0\cr_rd_ok[0:0] + attribute \src "libresoc.v:74699.3-74780.6" + wire width 8 $0\cr_wr[7:0] + attribute \src "libresoc.v:74699.3-74780.6" + wire $0\cr_wr_ok[0:0] + attribute \src "libresoc.v:74699.3-74780.6" + wire width 5 $0\ea[4:0] + attribute \src "libresoc.v:74699.3-74780.6" + wire $0\ea_ok[0:0] + attribute \src "libresoc.v:74699.3-74780.6" + wire width 3 $0\fast1[2:0] + attribute \src "libresoc.v:74699.3-74780.6" + wire $0\fast1_ok[0:0] + attribute \src "libresoc.v:74699.3-74780.6" + wire width 3 $0\fast2[2:0] + attribute \src "libresoc.v:74699.3-74780.6" + wire $0\fast2_ok[0:0] + attribute \src "libresoc.v:74699.3-74780.6" + wire width 3 $0\fasto1[2:0] + attribute \src "libresoc.v:74699.3-74780.6" + wire $0\fasto1_ok[0:0] + attribute \src "libresoc.v:74699.3-74780.6" + wire width 3 $0\fasto2[2:0] + attribute \src "libresoc.v:74699.3-74780.6" + wire $0\fasto2_ok[0:0] + attribute \src "libresoc.v:74699.3-74780.6" + wire width 12 $0\fn_unit[11:0] + attribute \src "libresoc.v:72945.7-72945.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:74699.3-74780.6" + wire width 2 $0\input_carry[1:0] + attribute \src "libresoc.v:74699.3-74780.6" + wire width 32 $0\insn[31:0] + attribute \src "libresoc.v:74699.3-74780.6" + wire width 7 $0\insn_type[6:0] + attribute \src "libresoc.v:74699.3-74780.6" + wire $0\is_32bit[0:0] + attribute \src "libresoc.v:74679.3-74698.6" + wire $0\is_priv_insn[0:0] + attribute \src "libresoc.v:74699.3-74780.6" + wire $0\lk[0:0] + attribute \src "libresoc.v:74699.3-74780.6" + wire width 64 $0\msr[63:0] + attribute \src "libresoc.v:74699.3-74780.6" + wire $0\oe[0:0] + attribute \src "libresoc.v:74699.3-74780.6" + wire $0\oe_ok[0:0] + attribute \src "libresoc.v:74699.3-74780.6" + wire $0\rc[0:0] + attribute \src "libresoc.v:74699.3-74780.6" + wire $0\rc_ok[0:0] + attribute \src "libresoc.v:74699.3-74780.6" + wire width 5 $0\reg1[4:0] + attribute \src "libresoc.v:74699.3-74780.6" + wire $0\reg1_ok[0:0] + attribute \src "libresoc.v:74699.3-74780.6" + wire width 5 $0\reg2[4:0] + attribute \src "libresoc.v:74699.3-74780.6" + wire $0\reg2_ok[0:0] + attribute \src "libresoc.v:74699.3-74780.6" + wire width 5 $0\reg3[4:0] + attribute \src "libresoc.v:74699.3-74780.6" + wire $0\reg3_ok[0:0] + attribute \src "libresoc.v:74699.3-74780.6" + wire width 5 $0\rego[4:0] + attribute \src "libresoc.v:74699.3-74780.6" + wire $0\rego_ok[0:0] + attribute \src "libresoc.v:74699.3-74780.6" + wire width 10 $0\spr1[9:0] + attribute \src "libresoc.v:74699.3-74780.6" + wire $0\spr1_ok[0:0] + attribute \src "libresoc.v:74699.3-74780.6" + wire width 10 $0\spro[9:0] + attribute \src "libresoc.v:74699.3-74780.6" + wire $0\spro_ok[0:0] + attribute \src "libresoc.v:74633.3-74642.6" + wire $0\tmp_tmp_lk[0:0] + attribute \src "libresoc.v:74669.3-74678.6" + wire width 13 $0\tmp_tmp_trapaddr[12:0] + attribute \src "libresoc.v:74643.3-74658.6" + wire width 3 $0\tmp_xer_in[2:0] + attribute \src "libresoc.v:74659.3-74668.6" + wire $0\tmp_xer_out[0:0] + attribute \src "libresoc.v:74699.3-74780.6" + wire width 13 $0\trapaddr[12:0] + attribute \src "libresoc.v:74699.3-74780.6" + wire width 7 $0\traptype[6:0] + attribute \src "libresoc.v:74699.3-74780.6" + wire width 3 $0\xer_in[2:0] + attribute \src "libresoc.v:74699.3-74780.6" + wire $0\xer_out[0:0] + attribute \src "libresoc.v:74699.3-74780.6" + wire width 8 $1\asmcode[7:0] + attribute \src "libresoc.v:74699.3-74780.6" + wire width 64 $1\cia[63:0] + attribute \src "libresoc.v:74699.3-74780.6" + wire width 3 $1\cr_in1[2:0] + attribute \src "libresoc.v:74699.3-74780.6" + wire $1\cr_in1_ok[0:0] + attribute \src "libresoc.v:74699.3-74780.6" + wire width 3 $1\cr_in2$1[2:0]$3628 + attribute \src "libresoc.v:74699.3-74780.6" + wire width 3 $1\cr_in2[2:0] + attribute \src "libresoc.v:74699.3-74780.6" + wire $1\cr_in2_ok$2[0:0]$3629 + attribute \src "libresoc.v:74699.3-74780.6" + wire $1\cr_in2_ok[0:0] + attribute \src "libresoc.v:74699.3-74780.6" + wire width 3 $1\cr_out[2:0] + attribute \src "libresoc.v:74699.3-74780.6" + wire $1\cr_out_ok[0:0] + attribute \src "libresoc.v:74699.3-74780.6" + wire width 8 $1\cr_rd[7:0] + attribute \src "libresoc.v:74699.3-74780.6" + wire $1\cr_rd_ok[0:0] + attribute \src "libresoc.v:74699.3-74780.6" + wire width 8 $1\cr_wr[7:0] + attribute \src "libresoc.v:74699.3-74780.6" + wire $1\cr_wr_ok[0:0] + attribute \src "libresoc.v:74699.3-74780.6" + wire width 5 $1\ea[4:0] + attribute \src "libresoc.v:74699.3-74780.6" + wire $1\ea_ok[0:0] + attribute \src "libresoc.v:74699.3-74780.6" + wire width 3 $1\fast1[2:0] + attribute \src "libresoc.v:74699.3-74780.6" + wire $1\fast1_ok[0:0] + attribute \src "libresoc.v:74699.3-74780.6" + wire width 3 $1\fast2[2:0] + attribute \src "libresoc.v:74699.3-74780.6" + wire $1\fast2_ok[0:0] + attribute \src "libresoc.v:74699.3-74780.6" + wire width 3 $1\fasto1[2:0] + attribute \src "libresoc.v:74699.3-74780.6" + wire $1\fasto1_ok[0:0] + attribute \src "libresoc.v:74699.3-74780.6" + wire width 3 $1\fasto2[2:0] + attribute \src "libresoc.v:74699.3-74780.6" + wire $1\fasto2_ok[0:0] + attribute \src "libresoc.v:74699.3-74780.6" + wire width 12 $1\fn_unit[11:0] + attribute \src "libresoc.v:74699.3-74780.6" + wire width 2 $1\input_carry[1:0] + attribute \src "libresoc.v:74699.3-74780.6" + wire width 32 $1\insn[31:0] + attribute \src "libresoc.v:74699.3-74780.6" + wire width 7 $1\insn_type[6:0] + attribute \src "libresoc.v:74699.3-74780.6" + wire $1\is_32bit[0:0] + attribute \src "libresoc.v:74679.3-74698.6" + wire $1\is_priv_insn[0:0] + attribute \src "libresoc.v:74699.3-74780.6" + wire $1\lk[0:0] + attribute \src "libresoc.v:74699.3-74780.6" + wire width 64 $1\msr[63:0] + attribute \src "libresoc.v:74699.3-74780.6" + wire $1\oe[0:0] + attribute \src "libresoc.v:74699.3-74780.6" + wire $1\oe_ok[0:0] + attribute \src "libresoc.v:74699.3-74780.6" + wire $1\rc[0:0] + attribute \src "libresoc.v:74699.3-74780.6" + wire $1\rc_ok[0:0] + attribute \src "libresoc.v:74699.3-74780.6" + wire width 5 $1\reg1[4:0] + attribute \src "libresoc.v:74699.3-74780.6" + wire $1\reg1_ok[0:0] + attribute \src "libresoc.v:74699.3-74780.6" + wire width 5 $1\reg2[4:0] + attribute \src "libresoc.v:74699.3-74780.6" + wire $1\reg2_ok[0:0] + attribute \src "libresoc.v:74699.3-74780.6" + wire width 5 $1\reg3[4:0] + attribute \src "libresoc.v:74699.3-74780.6" + wire $1\reg3_ok[0:0] + attribute \src "libresoc.v:74699.3-74780.6" + wire width 5 $1\rego[4:0] + attribute \src "libresoc.v:74699.3-74780.6" + wire $1\rego_ok[0:0] + attribute \src "libresoc.v:74699.3-74780.6" + wire width 10 $1\spr1[9:0] + attribute \src "libresoc.v:74699.3-74780.6" + wire $1\spr1_ok[0:0] + attribute \src "libresoc.v:74699.3-74780.6" + wire width 10 $1\spro[9:0] + attribute \src "libresoc.v:74699.3-74780.6" + wire $1\spro_ok[0:0] + attribute \src "libresoc.v:74633.3-74642.6" + wire $1\tmp_tmp_lk[0:0] + attribute \src "libresoc.v:74669.3-74678.6" + wire width 13 $1\tmp_tmp_trapaddr[12:0] + attribute \src "libresoc.v:74643.3-74658.6" + wire width 3 $1\tmp_xer_in[2:0] + attribute \src "libresoc.v:74659.3-74668.6" + wire $1\tmp_xer_out[0:0] + attribute \src "libresoc.v:74699.3-74780.6" + wire width 13 $1\trapaddr[12:0] + attribute \src "libresoc.v:74699.3-74780.6" + wire width 7 $1\traptype[6:0] + attribute \src "libresoc.v:74699.3-74780.6" + wire width 3 $1\xer_in[2:0] + attribute \src "libresoc.v:74699.3-74780.6" + wire $1\xer_out[0:0] + attribute \src "libresoc.v:74699.3-74780.6" + wire width 3 $2\fast1[2:0] + attribute \src "libresoc.v:74699.3-74780.6" + wire $2\fast1_ok[0:0] + attribute \src "libresoc.v:74699.3-74780.6" + wire width 3 $2\fast2[2:0] + attribute \src "libresoc.v:74699.3-74780.6" + wire $2\fast2_ok[0:0] + attribute \src "libresoc.v:74699.3-74780.6" + wire width 3 $2\fasto1[2:0] + attribute \src "libresoc.v:74699.3-74780.6" + wire $2\fasto1_ok[0:0] + attribute \src "libresoc.v:74699.3-74780.6" + wire width 3 $2\fasto2[2:0] + attribute \src "libresoc.v:74699.3-74780.6" + wire $2\fasto2_ok[0:0] + attribute \src "libresoc.v:74679.3-74698.6" + wire $2\is_priv_insn[0:0] + attribute \src "libresoc.v:74643.3-74658.6" + wire width 3 $2\tmp_xer_in[2:0] + attribute \src "libresoc.v:74484.18-74484.120" + wire $and$libresoc.v:74484$3612_Y + attribute \src "libresoc.v:74485.18-74485.123" + wire $and$libresoc.v:74485$3613_Y + attribute \src "libresoc.v:74486.18-74486.124" + wire $and$libresoc.v:74486$3614_Y + attribute \src "libresoc.v:74480.18-74480.122" + wire $eq$libresoc.v:74480$3608_Y + attribute \src "libresoc.v:74481.18-74481.122" + wire $eq$libresoc.v:74481$3609_Y + attribute \src "libresoc.v:74482.18-74482.122" + wire $eq$libresoc.v:74482$3610_Y + attribute \src "libresoc.v:74483.18-74483.122" + wire $eq$libresoc.v:74483$3611_Y + attribute \src "libresoc.v:74487.18-74487.122" + wire $eq$libresoc.v:74487$3615_Y + attribute \src "libresoc.v:74488.18-74488.116" + wire $eq$libresoc.v:74488$3616_Y + attribute \src "libresoc.v:74489.18-74489.116" + wire $eq$libresoc.v:74489$3617_Y + attribute \src "libresoc.v:74491.18-74491.116" + wire $eq$libresoc.v:74491$3619_Y + attribute \src "libresoc.v:74490.18-74490.110" + wire $or$libresoc.v:74490$3618_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:859" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:861" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:863" + wire \$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:867" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:889" + wire \$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:890" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:891" + wire \$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:892" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:923" + wire \$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:924" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:924" + wire \$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:933" + wire \$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:92" + wire width 8 output 5 \asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + wire input 1 \bigendian + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:42" + wire width 64 output 39 \cia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 output 30 \cr_in1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 31 \cr_in1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 output 32 \cr_in2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 output 34 \cr_in2$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 33 \cr_in2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 35 \cr_in2_ok$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 output 36 \cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 37 \cr_out_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 8 output 51 \cr_rd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 52 \cr_rd_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 8 output 53 \cr_wr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 54 \cr_wr_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:11" + wire width 64 input 56 \cur_dec + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:10" + wire input 57 \cur_eint + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:9" + wire width 64 input 3 \cur_msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:8" + wire width 64 input 2 \cur_pc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 8 \dec_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire \dec_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire \dec_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire \dec_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 10 \dec_SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \dec_XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \dec_XL_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \dec_X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \dec_X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \dec_a_fast_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_a_fast_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 \dec_a_reg_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_a_reg_a_ok + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:85" + wire width 3 \dec_a_sel_in + attribute \enum_base_type "SPR" + attribute \enum_value_0000000001 "XER" + attribute \enum_value_0000000011 "DSCR" + attribute \enum_value_0000001000 "LR" + attribute \enum_value_0000001001 "CTR" + attribute \enum_value_0000001101 "AMR" + attribute \enum_value_0000010001 "DSCR_priv" + attribute \enum_value_0000010010 "DSISR" + attribute \enum_value_0000010011 "DAR" + attribute \enum_value_0000010110 "DEC" + attribute \enum_value_0000011010 "SRR0" + attribute \enum_value_0000011011 "SRR1" + attribute \enum_value_0000011100 "CFAR" + attribute \enum_value_0000011101 "AMR_priv" + attribute \enum_value_0000110000 "PIDR" + attribute \enum_value_0000111101 "IAMR" + attribute \enum_value_0010000000 "TFHAR" + attribute \enum_value_0010000001 "TFIAR" + attribute \enum_value_0010000010 "TEXASR" + attribute \enum_value_0010000011 "TEXASRU" + attribute \enum_value_0010001000 "CTRL" + attribute \enum_value_0010010000 "TIDR" + attribute \enum_value_0010011000 "CTRL_priv" + attribute \enum_value_0010011001 "FSCR" + attribute \enum_value_0010011101 "UAMOR" + attribute \enum_value_0010011110 "GSR" + attribute \enum_value_0010011111 "PSPB" + attribute \enum_value_0010110000 "DPDES" + attribute \enum_value_0010110100 "DAWR0" + attribute \enum_value_0010111010 "RPR" + attribute \enum_value_0010111011 "CIABR" + attribute \enum_value_0010111100 "DAWRX0" + attribute \enum_value_0010111110 "HFSCR" + attribute \enum_value_0100000000 "VRSAVE" + attribute \enum_value_0100000011 "SPRG3" + attribute \enum_value_0100001100 "TB" + attribute \enum_value_0100001101 "TBU" + attribute \enum_value_0100010000 "SPRG0_priv" + attribute \enum_value_0100010001 "SPRG1_priv" + attribute \enum_value_0100010010 "SPRG2_priv" + attribute \enum_value_0100010011 "SPRG3_priv" + attribute \enum_value_0100011011 "CIR" + attribute \enum_value_0100011100 "TBL" + attribute \enum_value_0100011101 "TBU_hypv" + attribute \enum_value_0100011110 "TBU40" + attribute \enum_value_0100011111 "PVR" + attribute \enum_value_0100110000 "HSPRG0" + attribute \enum_value_0100110001 "HSPRG1" + attribute \enum_value_0100110010 "HDSISR" + attribute \enum_value_0100110011 "HDAR" + attribute \enum_value_0100110100 "SPURR" + attribute \enum_value_0100110101 "PURR" + attribute \enum_value_0100110110 "HDEC" + attribute \enum_value_0100111001 "HRMOR" + attribute \enum_value_0100111010 "HSRR0" + attribute \enum_value_0100111011 "HSRR1" + attribute \enum_value_0100111110 "LPCR" + attribute \enum_value_0100111111 "LPIDR" + attribute \enum_value_0101010000 "HMER" + attribute \enum_value_0101010001 "HMEER" + attribute \enum_value_0101010010 "PCR" + attribute \enum_value_0101010011 "HEIR" + attribute \enum_value_0101011101 "AMOR" + attribute \enum_value_0110111110 "TIR" + attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1100000000 "SIER" + attribute \enum_value_1100000001 "MMCR2" + attribute \enum_value_1100000010 "MMCRA" + attribute \enum_value_1100000011 "PMC1" + attribute \enum_value_1100000100 "PMC2" + attribute \enum_value_1100000101 "PMC3" + attribute \enum_value_1100000110 "PMC4" + attribute \enum_value_1100000111 "PMC5" + attribute \enum_value_1100001000 "PMC6" + attribute \enum_value_1100001011 "MMCR0" + attribute \enum_value_1100001100 "SIAR" + attribute \enum_value_1100001101 "SDAR" + attribute \enum_value_1100001110 "MMCR1" + attribute \enum_value_1100010000 "SIER_priv" + attribute \enum_value_1100010001 "MMCR2_priv" + attribute \enum_value_1100010010 "MMCRA_priv" + attribute \enum_value_1100010011 "PMC1_priv" + attribute \enum_value_1100010100 "PMC2_priv" + attribute \enum_value_1100010101 "PMC3_priv" + attribute \enum_value_1100010110 "PMC4_priv" + attribute \enum_value_1100010111 "PMC5_priv" + attribute \enum_value_1100011000 "PMC6_priv" + attribute \enum_value_1100011011 "MMCR0_priv" + attribute \enum_value_1100011100 "SIAR_priv" + attribute \enum_value_1100011101 "SDAR_priv" + attribute \enum_value_1100011110 "MMCR1_priv" + attribute \enum_value_1100100000 "BESCRS" + attribute \enum_value_1100100001 "BESCRSU" + attribute \enum_value_1100100010 "BESCRR" + attribute \enum_value_1100100011 "BESCRRU" + attribute \enum_value_1100100100 "EBBHR" + attribute \enum_value_1100100101 "EBBRR" + attribute \enum_value_1100100110 "BESCR" + attribute \enum_value_1100101000 "reserved808" + attribute \enum_value_1100101001 "reserved809" + attribute \enum_value_1100101010 "reserved810" + attribute \enum_value_1100101011 "reserved811" + attribute \enum_value_1100101111 "TAR" + attribute \enum_value_1100110000 "ASDR" + attribute \enum_value_1100110111 "PSSCR" + attribute \enum_value_1101010000 "IC" + attribute \enum_value_1101010001 "VTB" + attribute \enum_value_1101010111 "PSSCR_hypv" + attribute \enum_value_1110000000 "PPR" + attribute \enum_value_1110000010 "PPR32" + attribute \enum_value_1111111111 "PIR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 10 \dec_a_spr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_a_spr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 \dec_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \dec_b_fast_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_b_fast_b_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 \dec_b_reg_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_b_reg_b_ok + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" + wire width 4 \dec_b_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 \dec_c_reg_c + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_c_reg_c_ok + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" + wire width 2 \dec_c_sel_in + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec_cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \dec_cr_in_cr_bitfield + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \dec_cr_in_cr_bitfield_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_cr_in_cr_bitfield_b_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \dec_cr_in_cr_bitfield_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_cr_in_cr_bitfield_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_cr_in_cr_bitfield_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 8 \dec_cr_in_cr_fxm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_cr_in_cr_fxm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486" + wire width 32 \dec_cr_in_insn_in + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:485" + wire width 3 \dec_cr_in_sel_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \dec_cr_out_cr_bitfield + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_cr_out_cr_bitfield_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 8 \dec_cr_out_cr_fxm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_cr_out_cr_fxm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:551" + wire width 32 \dec_cr_out_insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:549" + wire \dec_cr_out_rc_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:550" + wire width 3 \dec_cr_out_sel_in + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec_cry_in + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \dec_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 \dec_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:885" + wire \dec_irq_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \dec_o2_fast_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_o2_fast_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:363" + wire \dec_o2_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 \dec_o2_reg_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_o2_reg_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \dec_o_fast_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_o_fast_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 \dec_o_reg_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_o_reg_o_ok + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:308" + wire width 2 \dec_o_sel_in + attribute \enum_base_type "SPR" + attribute \enum_value_0000000001 "XER" + attribute \enum_value_0000000011 "DSCR" + attribute \enum_value_0000001000 "LR" + attribute \enum_value_0000001001 "CTR" + attribute \enum_value_0000001101 "AMR" + attribute \enum_value_0000010001 "DSCR_priv" + attribute \enum_value_0000010010 "DSISR" + attribute \enum_value_0000010011 "DAR" + attribute \enum_value_0000010110 "DEC" + attribute \enum_value_0000011010 "SRR0" + attribute \enum_value_0000011011 "SRR1" + attribute \enum_value_0000011100 "CFAR" + attribute \enum_value_0000011101 "AMR_priv" + attribute \enum_value_0000110000 "PIDR" + attribute \enum_value_0000111101 "IAMR" + attribute \enum_value_0010000000 "TFHAR" + attribute \enum_value_0010000001 "TFIAR" + attribute \enum_value_0010000010 "TEXASR" + attribute \enum_value_0010000011 "TEXASRU" + attribute \enum_value_0010001000 "CTRL" + attribute \enum_value_0010010000 "TIDR" + attribute \enum_value_0010011000 "CTRL_priv" + attribute \enum_value_0010011001 "FSCR" + attribute \enum_value_0010011101 "UAMOR" + attribute \enum_value_0010011110 "GSR" + attribute \enum_value_0010011111 "PSPB" + attribute \enum_value_0010110000 "DPDES" + attribute \enum_value_0010110100 "DAWR0" + attribute \enum_value_0010111010 "RPR" + attribute \enum_value_0010111011 "CIABR" + attribute \enum_value_0010111100 "DAWRX0" + attribute \enum_value_0010111110 "HFSCR" + attribute \enum_value_0100000000 "VRSAVE" + attribute \enum_value_0100000011 "SPRG3" + attribute \enum_value_0100001100 "TB" + attribute \enum_value_0100001101 "TBU" + attribute \enum_value_0100010000 "SPRG0_priv" + attribute \enum_value_0100010001 "SPRG1_priv" + attribute \enum_value_0100010010 "SPRG2_priv" + attribute \enum_value_0100010011 "SPRG3_priv" + attribute \enum_value_0100011011 "CIR" + attribute \enum_value_0100011100 "TBL" + attribute \enum_value_0100011101 "TBU_hypv" + attribute \enum_value_0100011110 "TBU40" + attribute \enum_value_0100011111 "PVR" + attribute \enum_value_0100110000 "HSPRG0" + attribute \enum_value_0100110001 "HSPRG1" + attribute \enum_value_0100110010 "HDSISR" + attribute \enum_value_0100110011 "HDAR" + attribute \enum_value_0100110100 "SPURR" + attribute \enum_value_0100110101 "PURR" + attribute \enum_value_0100110110 "HDEC" + attribute \enum_value_0100111001 "HRMOR" + attribute \enum_value_0100111010 "HSRR0" + attribute \enum_value_0100111011 "HSRR1" + attribute \enum_value_0100111110 "LPCR" + attribute \enum_value_0100111111 "LPIDR" + attribute \enum_value_0101010000 "HMER" + attribute \enum_value_0101010001 "HMEER" + attribute \enum_value_0101010010 "PCR" + attribute \enum_value_0101010011 "HEIR" + attribute \enum_value_0101011101 "AMOR" + attribute \enum_value_0110111110 "TIR" + attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1100000000 "SIER" + attribute \enum_value_1100000001 "MMCR2" + attribute \enum_value_1100000010 "MMCRA" + attribute \enum_value_1100000011 "PMC1" + attribute \enum_value_1100000100 "PMC2" + attribute \enum_value_1100000101 "PMC3" + attribute \enum_value_1100000110 "PMC4" + attribute \enum_value_1100000111 "PMC5" + attribute \enum_value_1100001000 "PMC6" + attribute \enum_value_1100001011 "MMCR0" + attribute \enum_value_1100001100 "SIAR" + attribute \enum_value_1100001101 "SDAR" + attribute \enum_value_1100001110 "MMCR1" + attribute \enum_value_1100010000 "SIER_priv" + attribute \enum_value_1100010001 "MMCR2_priv" + attribute \enum_value_1100010010 "MMCRA_priv" + attribute \enum_value_1100010011 "PMC1_priv" + attribute \enum_value_1100010100 "PMC2_priv" + attribute \enum_value_1100010101 "PMC3_priv" + attribute \enum_value_1100010110 "PMC4_priv" + attribute \enum_value_1100010111 "PMC5_priv" + attribute \enum_value_1100011000 "PMC6_priv" + attribute \enum_value_1100011011 "MMCR0_priv" + attribute \enum_value_1100011100 "SIAR_priv" + attribute \enum_value_1100011101 "SDAR_priv" + attribute \enum_value_1100011110 "MMCR1_priv" + attribute \enum_value_1100100000 "BESCRS" + attribute \enum_value_1100100001 "BESCRSU" + attribute \enum_value_1100100010 "BESCRR" + attribute \enum_value_1100100011 "BESCRRU" + attribute \enum_value_1100100100 "EBBHR" + attribute \enum_value_1100100101 "EBBRR" + attribute \enum_value_1100100110 "BESCR" + attribute \enum_value_1100101000 "reserved808" + attribute \enum_value_1100101001 "reserved809" + attribute \enum_value_1100101010 "reserved810" + attribute \enum_value_1100101011 "reserved811" + attribute \enum_value_1100101111 "TAR" + attribute \enum_value_1100110000 "ASDR" + attribute \enum_value_1100110111 "PSSCR" + attribute \enum_value_1101010000 "IC" + attribute \enum_value_1101010001 "VTB" + attribute \enum_value_1101010111 "PSSCR_hypv" + attribute \enum_value_1110000000 "PPR" + attribute \enum_value_1110000010 "PPR32" + attribute \enum_value_1111111111 "PIR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 10 \dec_o_spr_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_o_spr_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_oe_oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_oe_oe_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" + wire width 2 \dec_oe_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \dec_opcode_in + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec_out_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_rc_rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_rc_rc_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec_rc_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:405" + wire width 2 \dec_rc_sel_in + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec_upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 output 8 \ea + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 9 \ea_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:884" + wire \ext_irq_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 output 22 \fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 23 \fast1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 output 24 \fast2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 25 \fast2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 output 26 \fasto1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 27 \fasto1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 output 28 \fasto2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 29 \fasto2_ok + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47" + wire width 12 output 42 \fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:887" + wire \illeg_ok + attribute \src "libresoc.v:72945.7-72945.15" + wire \initial + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:51" + wire width 2 output 48 \input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:45" + wire width 32 output 40 \insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:406" + wire width 32 \insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:364" + wire width 32 \insn_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:443" + wire width 32 \insn_in$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:86" + wire width 32 \insn_in$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:176" + wire width 32 \insn_in$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:280" + wire width 32 \insn_in$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:309" + wire width 32 \insn_in$9 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:46" + wire width 7 output 41 \insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:56" + wire output 55 \is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:41" + wire \is_priv_insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48" + wire output 43 \lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:41" + wire width 64 output 38 \msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 46 \oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 47 \oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:886" + wire \priv_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:442" + wire width 32 input 4 \raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 44 \rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 45 \rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 output 10 \reg1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 11 \reg1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 output 12 \reg2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 13 \reg2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 output 14 \reg3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 15 \reg3_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 output 6 \rego + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 7 \rego_ok + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:362" + wire width 2 \sel_in + attribute \enum_base_type "SPR" + attribute \enum_value_0000000001 "XER" + attribute \enum_value_0000000011 "DSCR" + attribute \enum_value_0000001000 "LR" + attribute \enum_value_0000001001 "CTR" + attribute \enum_value_0000001101 "AMR" + attribute \enum_value_0000010001 "DSCR_priv" + attribute \enum_value_0000010010 "DSISR" + attribute \enum_value_0000010011 "DAR" + attribute \enum_value_0000010110 "DEC" + attribute \enum_value_0000011010 "SRR0" + attribute \enum_value_0000011011 "SRR1" + attribute \enum_value_0000011100 "CFAR" + attribute \enum_value_0000011101 "AMR_priv" + attribute \enum_value_0000110000 "PIDR" + attribute \enum_value_0000111101 "IAMR" + attribute \enum_value_0010000000 "TFHAR" + attribute \enum_value_0010000001 "TFIAR" + attribute \enum_value_0010000010 "TEXASR" + attribute \enum_value_0010000011 "TEXASRU" + attribute \enum_value_0010001000 "CTRL" + attribute \enum_value_0010010000 "TIDR" + attribute \enum_value_0010011000 "CTRL_priv" + attribute \enum_value_0010011001 "FSCR" + attribute \enum_value_0010011101 "UAMOR" + attribute \enum_value_0010011110 "GSR" + attribute \enum_value_0010011111 "PSPB" + attribute \enum_value_0010110000 "DPDES" + attribute \enum_value_0010110100 "DAWR0" + attribute \enum_value_0010111010 "RPR" + attribute \enum_value_0010111011 "CIABR" + attribute \enum_value_0010111100 "DAWRX0" + attribute \enum_value_0010111110 "HFSCR" + attribute \enum_value_0100000000 "VRSAVE" + attribute \enum_value_0100000011 "SPRG3" + attribute \enum_value_0100001100 "TB" + attribute \enum_value_0100001101 "TBU" + attribute \enum_value_0100010000 "SPRG0_priv" + attribute \enum_value_0100010001 "SPRG1_priv" + attribute \enum_value_0100010010 "SPRG2_priv" + attribute \enum_value_0100010011 "SPRG3_priv" + attribute \enum_value_0100011011 "CIR" + attribute \enum_value_0100011100 "TBL" + attribute \enum_value_0100011101 "TBU_hypv" + attribute \enum_value_0100011110 "TBU40" + attribute \enum_value_0100011111 "PVR" + attribute \enum_value_0100110000 "HSPRG0" + attribute \enum_value_0100110001 "HSPRG1" + attribute \enum_value_0100110010 "HDSISR" + attribute \enum_value_0100110011 "HDAR" + attribute \enum_value_0100110100 "SPURR" + attribute \enum_value_0100110101 "PURR" + attribute \enum_value_0100110110 "HDEC" + attribute \enum_value_0100111001 "HRMOR" + attribute \enum_value_0100111010 "HSRR0" + attribute \enum_value_0100111011 "HSRR1" + attribute \enum_value_0100111110 "LPCR" + attribute \enum_value_0100111111 "LPIDR" + attribute \enum_value_0101010000 "HMER" + attribute \enum_value_0101010001 "HMEER" + attribute \enum_value_0101010010 "PCR" + attribute \enum_value_0101010011 "HEIR" + attribute \enum_value_0101011101 "AMOR" + attribute \enum_value_0110111110 "TIR" + attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1100000000 "SIER" + attribute \enum_value_1100000001 "MMCR2" + attribute \enum_value_1100000010 "MMCRA" + attribute \enum_value_1100000011 "PMC1" + attribute \enum_value_1100000100 "PMC2" + attribute \enum_value_1100000101 "PMC3" + attribute \enum_value_1100000110 "PMC4" + attribute \enum_value_1100000111 "PMC5" + attribute \enum_value_1100001000 "PMC6" + attribute \enum_value_1100001011 "MMCR0" + attribute \enum_value_1100001100 "SIAR" + attribute \enum_value_1100001101 "SDAR" + attribute \enum_value_1100001110 "MMCR1" + attribute \enum_value_1100010000 "SIER_priv" + attribute \enum_value_1100010001 "MMCR2_priv" + attribute \enum_value_1100010010 "MMCRA_priv" + attribute \enum_value_1100010011 "PMC1_priv" + attribute \enum_value_1100010100 "PMC2_priv" + attribute \enum_value_1100010101 "PMC3_priv" + attribute \enum_value_1100010110 "PMC4_priv" + attribute \enum_value_1100010111 "PMC5_priv" + attribute \enum_value_1100011000 "PMC6_priv" + attribute \enum_value_1100011011 "MMCR0_priv" + attribute \enum_value_1100011100 "SIAR_priv" + attribute \enum_value_1100011101 "SDAR_priv" + attribute \enum_value_1100011110 "MMCR1_priv" + attribute \enum_value_1100100000 "BESCRS" + attribute \enum_value_1100100001 "BESCRSU" + attribute \enum_value_1100100010 "BESCRR" + attribute \enum_value_1100100011 "BESCRRU" + attribute \enum_value_1100100100 "EBBHR" + attribute \enum_value_1100100101 "EBBRR" + attribute \enum_value_1100100110 "BESCR" + attribute \enum_value_1100101000 "reserved808" + attribute \enum_value_1100101001 "reserved809" + attribute \enum_value_1100101010 "reserved810" + attribute \enum_value_1100101011 "reserved811" + attribute \enum_value_1100101111 "TAR" + attribute \enum_value_1100110000 "ASDR" + attribute \enum_value_1100110111 "PSSCR" + attribute \enum_value_1101010000 "IC" + attribute \enum_value_1101010001 "VTB" + attribute \enum_value_1101010111 "PSSCR_hypv" + attribute \enum_value_1110000000 "PPR" + attribute \enum_value_1110000010 "PPR32" + attribute \enum_value_1111111111 "PIR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 10 output 18 \spr1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 19 \spr1_ok + attribute \enum_base_type "SPR" + attribute \enum_value_0000000001 "XER" + attribute \enum_value_0000000011 "DSCR" + attribute \enum_value_0000001000 "LR" + attribute \enum_value_0000001001 "CTR" + attribute \enum_value_0000001101 "AMR" + attribute \enum_value_0000010001 "DSCR_priv" + attribute \enum_value_0000010010 "DSISR" + attribute \enum_value_0000010011 "DAR" + attribute \enum_value_0000010110 "DEC" + attribute \enum_value_0000011010 "SRR0" + attribute \enum_value_0000011011 "SRR1" + attribute \enum_value_0000011100 "CFAR" + attribute \enum_value_0000011101 "AMR_priv" + attribute \enum_value_0000110000 "PIDR" + attribute \enum_value_0000111101 "IAMR" + attribute \enum_value_0010000000 "TFHAR" + attribute \enum_value_0010000001 "TFIAR" + attribute \enum_value_0010000010 "TEXASR" + attribute \enum_value_0010000011 "TEXASRU" + attribute \enum_value_0010001000 "CTRL" + attribute \enum_value_0010010000 "TIDR" + attribute \enum_value_0010011000 "CTRL_priv" + attribute \enum_value_0010011001 "FSCR" + attribute \enum_value_0010011101 "UAMOR" + attribute \enum_value_0010011110 "GSR" + attribute \enum_value_0010011111 "PSPB" + attribute \enum_value_0010110000 "DPDES" + attribute \enum_value_0010110100 "DAWR0" + attribute \enum_value_0010111010 "RPR" + attribute \enum_value_0010111011 "CIABR" + attribute \enum_value_0010111100 "DAWRX0" + attribute \enum_value_0010111110 "HFSCR" + attribute \enum_value_0100000000 "VRSAVE" + attribute \enum_value_0100000011 "SPRG3" + attribute \enum_value_0100001100 "TB" + attribute \enum_value_0100001101 "TBU" + attribute \enum_value_0100010000 "SPRG0_priv" + attribute \enum_value_0100010001 "SPRG1_priv" + attribute \enum_value_0100010010 "SPRG2_priv" + attribute \enum_value_0100010011 "SPRG3_priv" + attribute \enum_value_0100011011 "CIR" + attribute \enum_value_0100011100 "TBL" + attribute \enum_value_0100011101 "TBU_hypv" + attribute \enum_value_0100011110 "TBU40" + attribute \enum_value_0100011111 "PVR" + attribute \enum_value_0100110000 "HSPRG0" + attribute \enum_value_0100110001 "HSPRG1" + attribute \enum_value_0100110010 "HDSISR" + attribute \enum_value_0100110011 "HDAR" + attribute \enum_value_0100110100 "SPURR" + attribute \enum_value_0100110101 "PURR" + attribute \enum_value_0100110110 "HDEC" + attribute \enum_value_0100111001 "HRMOR" + attribute \enum_value_0100111010 "HSRR0" + attribute \enum_value_0100111011 "HSRR1" + attribute \enum_value_0100111110 "LPCR" + attribute \enum_value_0100111111 "LPIDR" + attribute \enum_value_0101010000 "HMER" + attribute \enum_value_0101010001 "HMEER" + attribute \enum_value_0101010010 "PCR" + attribute \enum_value_0101010011 "HEIR" + attribute \enum_value_0101011101 "AMOR" + attribute \enum_value_0110111110 "TIR" + attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1100000000 "SIER" + attribute \enum_value_1100000001 "MMCR2" + attribute \enum_value_1100000010 "MMCRA" + attribute \enum_value_1100000011 "PMC1" + attribute \enum_value_1100000100 "PMC2" + attribute \enum_value_1100000101 "PMC3" + attribute \enum_value_1100000110 "PMC4" + attribute \enum_value_1100000111 "PMC5" + attribute \enum_value_1100001000 "PMC6" + attribute \enum_value_1100001011 "MMCR0" + attribute \enum_value_1100001100 "SIAR" + attribute \enum_value_1100001101 "SDAR" + attribute \enum_value_1100001110 "MMCR1" + attribute \enum_value_1100010000 "SIER_priv" + attribute \enum_value_1100010001 "MMCR2_priv" + attribute \enum_value_1100010010 "MMCRA_priv" + attribute \enum_value_1100010011 "PMC1_priv" + attribute \enum_value_1100010100 "PMC2_priv" + attribute \enum_value_1100010101 "PMC3_priv" + attribute \enum_value_1100010110 "PMC4_priv" + attribute \enum_value_1100010111 "PMC5_priv" + attribute \enum_value_1100011000 "PMC6_priv" + attribute \enum_value_1100011011 "MMCR0_priv" + attribute \enum_value_1100011100 "SIAR_priv" + attribute \enum_value_1100011101 "SDAR_priv" + attribute \enum_value_1100011110 "MMCR1_priv" + attribute \enum_value_1100100000 "BESCRS" + attribute \enum_value_1100100001 "BESCRSU" + attribute \enum_value_1100100010 "BESCRR" + attribute \enum_value_1100100011 "BESCRRU" + attribute \enum_value_1100100100 "EBBHR" + attribute \enum_value_1100100101 "EBBRR" + attribute \enum_value_1100100110 "BESCR" + attribute \enum_value_1100101000 "reserved808" + attribute \enum_value_1100101001 "reserved809" + attribute \enum_value_1100101010 "reserved810" + attribute \enum_value_1100101011 "reserved811" + attribute \enum_value_1100101111 "TAR" + attribute \enum_value_1100110000 "ASDR" + attribute \enum_value_1100110111 "PSSCR" + attribute \enum_value_1101010000 "IC" + attribute \enum_value_1101010001 "VTB" + attribute \enum_value_1101010111 "PSSCR_hypv" + attribute \enum_value_1110000000 "PPR" + attribute \enum_value_1110000010 "PPR32" + attribute \enum_value_1111111111 "PIR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 10 output 16 \spro + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 17 \spro_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:92" + wire width 8 \tmp_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \tmp_cr_in1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \tmp_cr_in1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \tmp_cr_in2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \tmp_cr_in2$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \tmp_cr_in2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \tmp_cr_in2_ok$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \tmp_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \tmp_cr_out_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 \tmp_ea + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \tmp_ea_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \tmp_fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \tmp_fast1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \tmp_fast2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \tmp_fast2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \tmp_fasto1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \tmp_fasto1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \tmp_fasto2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \tmp_fasto2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 \tmp_reg1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \tmp_reg1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 \tmp_reg2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \tmp_reg2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 \tmp_reg3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \tmp_reg3_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 \tmp_rego + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \tmp_rego_ok + attribute \enum_base_type "SPR" + attribute \enum_value_0000000001 "XER" + attribute \enum_value_0000000011 "DSCR" + attribute \enum_value_0000001000 "LR" + attribute \enum_value_0000001001 "CTR" + attribute \enum_value_0000001101 "AMR" + attribute \enum_value_0000010001 "DSCR_priv" + attribute \enum_value_0000010010 "DSISR" + attribute \enum_value_0000010011 "DAR" + attribute \enum_value_0000010110 "DEC" + attribute \enum_value_0000011010 "SRR0" + attribute \enum_value_0000011011 "SRR1" + attribute \enum_value_0000011100 "CFAR" + attribute \enum_value_0000011101 "AMR_priv" + attribute \enum_value_0000110000 "PIDR" + attribute \enum_value_0000111101 "IAMR" + attribute \enum_value_0010000000 "TFHAR" + attribute \enum_value_0010000001 "TFIAR" + attribute \enum_value_0010000010 "TEXASR" + attribute \enum_value_0010000011 "TEXASRU" + attribute \enum_value_0010001000 "CTRL" + attribute \enum_value_0010010000 "TIDR" + attribute \enum_value_0010011000 "CTRL_priv" + attribute \enum_value_0010011001 "FSCR" + attribute \enum_value_0010011101 "UAMOR" + attribute \enum_value_0010011110 "GSR" + attribute \enum_value_0010011111 "PSPB" + attribute \enum_value_0010110000 "DPDES" + attribute \enum_value_0010110100 "DAWR0" + attribute \enum_value_0010111010 "RPR" + attribute \enum_value_0010111011 "CIABR" + attribute \enum_value_0010111100 "DAWRX0" + attribute \enum_value_0010111110 "HFSCR" + attribute \enum_value_0100000000 "VRSAVE" + attribute \enum_value_0100000011 "SPRG3" + attribute \enum_value_0100001100 "TB" + attribute \enum_value_0100001101 "TBU" + attribute \enum_value_0100010000 "SPRG0_priv" + attribute \enum_value_0100010001 "SPRG1_priv" + attribute \enum_value_0100010010 "SPRG2_priv" + attribute \enum_value_0100010011 "SPRG3_priv" + attribute \enum_value_0100011011 "CIR" + attribute \enum_value_0100011100 "TBL" + attribute \enum_value_0100011101 "TBU_hypv" + attribute \enum_value_0100011110 "TBU40" + attribute \enum_value_0100011111 "PVR" + attribute \enum_value_0100110000 "HSPRG0" + attribute \enum_value_0100110001 "HSPRG1" + attribute \enum_value_0100110010 "HDSISR" + attribute \enum_value_0100110011 "HDAR" + attribute \enum_value_0100110100 "SPURR" + attribute \enum_value_0100110101 "PURR" + attribute \enum_value_0100110110 "HDEC" + attribute \enum_value_0100111001 "HRMOR" + attribute \enum_value_0100111010 "HSRR0" + attribute \enum_value_0100111011 "HSRR1" + attribute \enum_value_0100111110 "LPCR" + attribute \enum_value_0100111111 "LPIDR" + attribute \enum_value_0101010000 "HMER" + attribute \enum_value_0101010001 "HMEER" + attribute \enum_value_0101010010 "PCR" + attribute \enum_value_0101010011 "HEIR" + attribute \enum_value_0101011101 "AMOR" + attribute \enum_value_0110111110 "TIR" + attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1100000000 "SIER" + attribute \enum_value_1100000001 "MMCR2" + attribute \enum_value_1100000010 "MMCRA" + attribute \enum_value_1100000011 "PMC1" + attribute \enum_value_1100000100 "PMC2" + attribute \enum_value_1100000101 "PMC3" + attribute \enum_value_1100000110 "PMC4" + attribute \enum_value_1100000111 "PMC5" + attribute \enum_value_1100001000 "PMC6" + attribute \enum_value_1100001011 "MMCR0" + attribute \enum_value_1100001100 "SIAR" + attribute \enum_value_1100001101 "SDAR" + attribute \enum_value_1100001110 "MMCR1" + attribute \enum_value_1100010000 "SIER_priv" + attribute \enum_value_1100010001 "MMCR2_priv" + attribute \enum_value_1100010010 "MMCRA_priv" + attribute \enum_value_1100010011 "PMC1_priv" + attribute \enum_value_1100010100 "PMC2_priv" + attribute \enum_value_1100010101 "PMC3_priv" + attribute \enum_value_1100010110 "PMC4_priv" + attribute \enum_value_1100010111 "PMC5_priv" + attribute \enum_value_1100011000 "PMC6_priv" + attribute \enum_value_1100011011 "MMCR0_priv" + attribute \enum_value_1100011100 "SIAR_priv" + attribute \enum_value_1100011101 "SDAR_priv" + attribute \enum_value_1100011110 "MMCR1_priv" + attribute \enum_value_1100100000 "BESCRS" + attribute \enum_value_1100100001 "BESCRSU" + attribute \enum_value_1100100010 "BESCRR" + attribute \enum_value_1100100011 "BESCRRU" + attribute \enum_value_1100100100 "EBBHR" + attribute \enum_value_1100100101 "EBBRR" + attribute \enum_value_1100100110 "BESCR" + attribute \enum_value_1100101000 "reserved808" + attribute \enum_value_1100101001 "reserved809" + attribute \enum_value_1100101010 "reserved810" + attribute \enum_value_1100101011 "reserved811" + attribute \enum_value_1100101111 "TAR" + attribute \enum_value_1100110000 "ASDR" + attribute \enum_value_1100110111 "PSSCR" + attribute \enum_value_1101010000 "IC" + attribute \enum_value_1101010001 "VTB" + attribute \enum_value_1101010111 "PSSCR_hypv" + attribute \enum_value_1110000000 "PPR" + attribute \enum_value_1110000010 "PPR32" + attribute \enum_value_1111111111 "PIR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 10 \tmp_spr1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \tmp_spr1_ok + attribute \enum_base_type "SPR" + attribute \enum_value_0000000001 "XER" + attribute \enum_value_0000000011 "DSCR" + attribute \enum_value_0000001000 "LR" + attribute \enum_value_0000001001 "CTR" + attribute \enum_value_0000001101 "AMR" + attribute \enum_value_0000010001 "DSCR_priv" + attribute \enum_value_0000010010 "DSISR" + attribute \enum_value_0000010011 "DAR" + attribute \enum_value_0000010110 "DEC" + attribute \enum_value_0000011010 "SRR0" + attribute \enum_value_0000011011 "SRR1" + attribute \enum_value_0000011100 "CFAR" + attribute \enum_value_0000011101 "AMR_priv" + attribute \enum_value_0000110000 "PIDR" + attribute \enum_value_0000111101 "IAMR" + attribute \enum_value_0010000000 "TFHAR" + attribute \enum_value_0010000001 "TFIAR" + attribute \enum_value_0010000010 "TEXASR" + attribute \enum_value_0010000011 "TEXASRU" + attribute \enum_value_0010001000 "CTRL" + attribute \enum_value_0010010000 "TIDR" + attribute \enum_value_0010011000 "CTRL_priv" + attribute \enum_value_0010011001 "FSCR" + attribute \enum_value_0010011101 "UAMOR" + attribute \enum_value_0010011110 "GSR" + attribute \enum_value_0010011111 "PSPB" + attribute \enum_value_0010110000 "DPDES" + attribute \enum_value_0010110100 "DAWR0" + attribute \enum_value_0010111010 "RPR" + attribute \enum_value_0010111011 "CIABR" + attribute \enum_value_0010111100 "DAWRX0" + attribute \enum_value_0010111110 "HFSCR" + attribute \enum_value_0100000000 "VRSAVE" + attribute \enum_value_0100000011 "SPRG3" + attribute \enum_value_0100001100 "TB" + attribute \enum_value_0100001101 "TBU" + attribute \enum_value_0100010000 "SPRG0_priv" + attribute \enum_value_0100010001 "SPRG1_priv" + attribute \enum_value_0100010010 "SPRG2_priv" + attribute \enum_value_0100010011 "SPRG3_priv" + attribute \enum_value_0100011011 "CIR" + attribute \enum_value_0100011100 "TBL" + attribute \enum_value_0100011101 "TBU_hypv" + attribute \enum_value_0100011110 "TBU40" + attribute \enum_value_0100011111 "PVR" + attribute \enum_value_0100110000 "HSPRG0" + attribute \enum_value_0100110001 "HSPRG1" + attribute \enum_value_0100110010 "HDSISR" + attribute \enum_value_0100110011 "HDAR" + attribute \enum_value_0100110100 "SPURR" + attribute \enum_value_0100110101 "PURR" + attribute \enum_value_0100110110 "HDEC" + attribute \enum_value_0100111001 "HRMOR" + attribute \enum_value_0100111010 "HSRR0" + attribute \enum_value_0100111011 "HSRR1" + attribute \enum_value_0100111110 "LPCR" + attribute \enum_value_0100111111 "LPIDR" + attribute \enum_value_0101010000 "HMER" + attribute \enum_value_0101010001 "HMEER" + attribute \enum_value_0101010010 "PCR" + attribute \enum_value_0101010011 "HEIR" + attribute \enum_value_0101011101 "AMOR" + attribute \enum_value_0110111110 "TIR" + attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1100000000 "SIER" + attribute \enum_value_1100000001 "MMCR2" + attribute \enum_value_1100000010 "MMCRA" + attribute \enum_value_1100000011 "PMC1" + attribute \enum_value_1100000100 "PMC2" + attribute \enum_value_1100000101 "PMC3" + attribute \enum_value_1100000110 "PMC4" + attribute \enum_value_1100000111 "PMC5" + attribute \enum_value_1100001000 "PMC6" + attribute \enum_value_1100001011 "MMCR0" + attribute \enum_value_1100001100 "SIAR" + attribute \enum_value_1100001101 "SDAR" + attribute \enum_value_1100001110 "MMCR1" + attribute \enum_value_1100010000 "SIER_priv" + attribute \enum_value_1100010001 "MMCR2_priv" + attribute \enum_value_1100010010 "MMCRA_priv" + attribute \enum_value_1100010011 "PMC1_priv" + attribute \enum_value_1100010100 "PMC2_priv" + attribute \enum_value_1100010101 "PMC3_priv" + attribute \enum_value_1100010110 "PMC4_priv" + attribute \enum_value_1100010111 "PMC5_priv" + attribute \enum_value_1100011000 "PMC6_priv" + attribute \enum_value_1100011011 "MMCR0_priv" + attribute \enum_value_1100011100 "SIAR_priv" + attribute \enum_value_1100011101 "SDAR_priv" + attribute \enum_value_1100011110 "MMCR1_priv" + attribute \enum_value_1100100000 "BESCRS" + attribute \enum_value_1100100001 "BESCRSU" + attribute \enum_value_1100100010 "BESCRR" + attribute \enum_value_1100100011 "BESCRRU" + attribute \enum_value_1100100100 "EBBHR" + attribute \enum_value_1100100101 "EBBRR" + attribute \enum_value_1100100110 "BESCR" + attribute \enum_value_1100101000 "reserved808" + attribute \enum_value_1100101001 "reserved809" + attribute \enum_value_1100101010 "reserved810" + attribute \enum_value_1100101011 "reserved811" + attribute \enum_value_1100101111 "TAR" + attribute \enum_value_1100110000 "ASDR" + attribute \enum_value_1100110111 "PSSCR" + attribute \enum_value_1101010000 "IC" + attribute \enum_value_1101010001 "VTB" + attribute \enum_value_1101010111 "PSSCR_hypv" + attribute \enum_value_1110000000 "PPR" + attribute \enum_value_1110000010 "PPR32" + attribute \enum_value_1111111111 "PIR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 10 \tmp_spro + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \tmp_spro_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:42" + wire width 64 \tmp_tmp_cia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 8 \tmp_tmp_cr_rd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \tmp_tmp_cr_rd_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 8 \tmp_tmp_cr_wr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \tmp_tmp_cr_wr_ok + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47" + wire width 12 \tmp_tmp_fn_unit + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:51" + wire width 2 \tmp_tmp_input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:45" + wire width 32 \tmp_tmp_insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:46" + wire width 7 \tmp_tmp_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:56" + wire \tmp_tmp_is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48" + wire \tmp_tmp_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:41" + wire width 64 \tmp_tmp_msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \tmp_tmp_oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \tmp_tmp_oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \tmp_tmp_rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \tmp_tmp_rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53" + wire width 13 \tmp_tmp_trapaddr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:52" + wire width 7 \tmp_tmp_traptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:102" + wire width 3 \tmp_xer_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:103" + wire \tmp_xer_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53" + wire width 13 output 50 \trapaddr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:52" + wire width 7 output 49 \traptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:102" + wire width 3 output 20 \xer_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:103" + wire output 21 \xer_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:889" + cell $and $and$libresoc.v:74484$3612 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cur_eint + connect \B \cur_msr [15] + connect \Y $and$libresoc.v:74484$3612_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:890" + cell $and $and$libresoc.v:74485$3613 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cur_dec [63] + connect \B \cur_msr [15] + connect \Y $and$libresoc.v:74485$3613_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:891" + cell $and $and$libresoc.v:74486$3614 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_priv_insn + connect \B \cur_msr [14] + connect \Y $and$libresoc.v:74486$3614_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:859" + cell $eq $eq$libresoc.v:74480$3608 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \dec_internal_op + connect \B 7'0101110 + connect \Y $eq$libresoc.v:74480$3608_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:861" + cell $eq $eq$libresoc.v:74481$3609 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \dec_internal_op + connect \B 7'0001010 + connect \Y $eq$libresoc.v:74481$3609_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:863" + cell $eq $eq$libresoc.v:74482$3610 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \dec_internal_op + connect \B 7'0110001 + connect \Y $eq$libresoc.v:74482$3610_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:867" + cell $eq $eq$libresoc.v:74483$3611 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \dec_internal_op + connect \B 7'0111111 + connect \Y $eq$libresoc.v:74483$3611_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:892" + cell $eq $eq$libresoc.v:74487$3615 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \dec_internal_op + connect \B 7'0000000 + connect \Y $eq$libresoc.v:74487$3615_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:923" + cell $eq $eq$libresoc.v:74488$3616 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \insn_type + connect \B 7'0111111 + connect \Y $eq$libresoc.v:74488$3616_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:924" + cell $eq $eq$libresoc.v:74489$3617 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \insn_type + connect \B 7'1001001 + connect \Y $eq$libresoc.v:74489$3617_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:933" + cell $eq $eq$libresoc.v:74491$3619 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \insn_type + connect \B 7'1000110 + connect \Y $eq$libresoc.v:74491$3619_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:924" + cell $or $or$libresoc.v:74490$3618 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$29 + connect \B \$31 + connect \Y $or$libresoc.v:74490$3618_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:74492.13-74529.4" + cell \dec$202 \dec + connect \BA \dec_BA + connect \BB \dec_BB + connect \BC \dec_BC + connect \BI \dec_BI + connect \BO \dec_BO + connect \BT \dec_BT + connect \FXM \dec_FXM + connect \LK \dec_LK + connect \OE \dec_OE + connect \RA \dec_RA + connect \RB \dec_RB + connect \RS \dec_RS + connect \RT \dec_RT + connect \Rc \dec_Rc + connect \SPR \dec_SPR + connect \XL_BT \dec_XL_BT + connect \XL_XO \dec_XL_XO + connect \X_BF \dec_X_BF + connect \X_BFA \dec_X_BFA + connect \asmcode \dec_asmcode + connect \bigendian \bigendian + connect \cr_in \dec_cr_in + connect \cr_out \dec_cr_out + connect \cry_in \dec_cry_in + connect \function_unit \dec_function_unit + connect \in1_sel \dec_in1_sel + connect \in2_sel \dec_in2_sel + connect \in3_sel \dec_in3_sel + connect \internal_op \dec_internal_op + connect \is_32b \dec_is_32b + connect \lk \dec_lk + connect \opcode_in \dec_opcode_in + connect \out_sel \dec_out_sel + connect \raw_opcode_in \raw_opcode_in + connect \rc_sel \dec_rc_sel + connect \upd \dec_upd + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:74530.9-74544.4" + cell \dec_a \dec_a + connect \BO \dec_BO + connect \RA \dec_RA + connect \RS \dec_RS + connect \SPR \dec_SPR + connect \XL_XO \dec_XL_XO + connect \fast_a \dec_a_fast_a + connect \fast_a_ok \dec_a_fast_a_ok + connect \internal_op \dec_internal_op + connect \reg_a \dec_a_reg_a + connect \reg_a_ok \dec_a_reg_a_ok + connect \sel_in \dec_a_sel_in + connect \spr_a \dec_a_spr_a + connect \spr_a_ok \dec_a_spr_a_ok + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:74545.9-74555.4" + cell \dec_b \dec_b + connect \RB \dec_RB + connect \RS \dec_RS + connect \XL_XO \dec_XL_XO + connect \fast_b \dec_b_fast_b + connect \fast_b_ok \dec_b_fast_b_ok + connect \internal_op \dec_internal_op + connect \reg_b \dec_b_reg_b + connect \reg_b_ok \dec_b_reg_b_ok + connect \sel_in \dec_b_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:74556.9-74562.4" + cell \dec_c \dec_c + connect \RB \dec_RB + connect \RS \dec_RS + connect \reg_c \dec_c_reg_c + connect \reg_c_ok \dec_c_reg_c_ok + connect \sel_in \dec_c_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:74563.19-74582.4" + cell \dec_cr_in$205 \dec_cr_in$3 + connect \BA \dec_BA + connect \BB \dec_BB + connect \BC \dec_BC + connect \BI \dec_BI + connect \BT \dec_BT + connect \FXM \dec_FXM + connect \X_BFA \dec_X_BFA + connect \cr_bitfield \dec_cr_in_cr_bitfield + connect \cr_bitfield_b \dec_cr_in_cr_bitfield_b + connect \cr_bitfield_b_ok \dec_cr_in_cr_bitfield_b_ok + connect \cr_bitfield_o \dec_cr_in_cr_bitfield_o + connect \cr_bitfield_o_ok \dec_cr_in_cr_bitfield_o_ok + connect \cr_bitfield_ok \dec_cr_in_cr_bitfield_ok + connect \cr_fxm \dec_cr_in_cr_fxm + connect \cr_fxm_ok \dec_cr_in_cr_fxm_ok + connect \insn_in \dec_cr_in_insn_in + connect \internal_op \dec_internal_op + connect \sel_in \dec_cr_in_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:74583.20-74595.4" + cell \dec_cr_out$207 \dec_cr_out$4 + connect \FXM \dec_FXM + connect \XL_BT \dec_XL_BT + connect \X_BF \dec_X_BF + connect \cr_bitfield \dec_cr_out_cr_bitfield + connect \cr_bitfield_ok \dec_cr_out_cr_bitfield_ok + connect \cr_fxm \dec_cr_out_cr_fxm + connect \cr_fxm_ok \dec_cr_out_cr_fxm_ok + connect \insn_in \dec_cr_out_insn_in + connect \internal_op \dec_internal_op + connect \rc_in \dec_cr_out_rc_in + connect \sel_in \dec_cr_out_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:74596.9-74609.4" + cell \dec_o \dec_o + connect \BO \dec_BO + connect \RA \dec_RA + connect \RT \dec_RT + connect \SPR \dec_SPR + connect \fast_o \dec_o_fast_o + connect \fast_o_ok \dec_o_fast_o_ok + connect \internal_op \dec_internal_op + connect \reg_o \dec_o_reg_o + connect \reg_o_ok \dec_o_reg_o_ok + connect \sel_in \dec_o_sel_in + connect \spr_o \dec_o_spr_o + connect \spr_o_ok \dec_o_spr_o_ok + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:74610.10-74619.4" + cell \dec_o2 \dec_o2 + connect \RA \dec_RA + connect \fast_o \dec_o2_fast_o + connect \fast_o_ok \dec_o2_fast_o_ok + connect \internal_op \dec_internal_op + connect \lk \dec_o2_lk + connect \reg_o \dec_o2_reg_o + connect \reg_o_ok \dec_o2_reg_o_ok + connect \upd \dec_upd + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:74620.16-74626.4" + cell \dec_oe$204 \dec_oe + connect \OE \dec_OE + connect \internal_op \dec_internal_op + connect \oe \dec_oe_oe + connect \oe_ok \dec_oe_oe_ok + connect \sel_in \dec_oe_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:74627.16-74632.4" + cell \dec_rc$203 \dec_rc + connect \Rc \dec_Rc + connect \rc \dec_rc_rc + connect \rc_ok \dec_rc_rc_ok + connect \sel_in \dec_rc_sel_in + end + attribute \src "libresoc.v:72945.7-72945.20" + process $proc$libresoc.v:72945$3630 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:74633.3-74642.6" + process $proc$libresoc.v:74633$3620 + assign { } { } + assign { } { } + assign $0\tmp_tmp_lk[0:0] $1\tmp_tmp_lk[0:0] + attribute \src "libresoc.v:74634.5-74634.29" + switch \initial + attribute \src "libresoc.v:74634.9-74634.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:758" + switch \dec_lk + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\tmp_tmp_lk[0:0] \dec_LK + case + assign $1\tmp_tmp_lk[0:0] 1'0 + end + sync always + update \tmp_tmp_lk $0\tmp_tmp_lk[0:0] + end + attribute \src "libresoc.v:74643.3-74658.6" + process $proc$libresoc.v:74643$3621 + assign { } { } + assign { } { } + assign { } { } + assign $0\tmp_xer_in[2:0] $2\tmp_xer_in[2:0] + attribute \src "libresoc.v:74644.5-74644.29" + switch \initial + attribute \src "libresoc.v:74644.9-74644.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:859" + switch \$13 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\tmp_xer_in[2:0] 3'111 + case + assign $1\tmp_xer_in[2:0] 3'000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:861" + switch \$15 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\tmp_xer_in[2:0] 3'001 + case + assign $2\tmp_xer_in[2:0] $1\tmp_xer_in[2:0] + end + sync always + update \tmp_xer_in $0\tmp_xer_in[2:0] + end + attribute \src "libresoc.v:74659.3-74668.6" + process $proc$libresoc.v:74659$3622 + assign { } { } + assign { } { } + assign $0\tmp_xer_out[0:0] $1\tmp_xer_out[0:0] + attribute \src "libresoc.v:74660.5-74660.29" + switch \initial + attribute \src "libresoc.v:74660.9-74660.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:863" + switch \$17 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\tmp_xer_out[0:0] 1'1 + case + assign $1\tmp_xer_out[0:0] 1'0 + end + sync always + update \tmp_xer_out $0\tmp_xer_out[0:0] + end + attribute \src "libresoc.v:74669.3-74678.6" + process $proc$libresoc.v:74669$3623 + assign { } { } + assign { } { } + assign $0\tmp_tmp_trapaddr[12:0] $1\tmp_tmp_trapaddr[12:0] + attribute \src "libresoc.v:74670.5-74670.29" + switch \initial + attribute \src "libresoc.v:74670.9-74670.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:867" + switch \$19 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\tmp_tmp_trapaddr[12:0] 13'0000001110000 + case + assign $1\tmp_tmp_trapaddr[12:0] 13'0000000000000 + end + sync always + update \tmp_tmp_trapaddr $0\tmp_tmp_trapaddr[12:0] + end + attribute \src "libresoc.v:74679.3-74698.6" + process $proc$libresoc.v:74679$3624 + assign { } { } + assign { } { } + assign $0\is_priv_insn[0:0] $1\is_priv_insn[0:0] + attribute \src "libresoc.v:74680.5-74680.29" + switch \initial + attribute \src "libresoc.v:74680.9-74680.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:42" + switch \dec_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 , 7'1000111 , 7'1001000 , 7'1001010 , 7'1000110 + assign { } { } + assign $1\is_priv_insn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 7'0101110 , 7'0110001 + assign { } { } + assign $1\is_priv_insn[0:0] $2\is_priv_insn[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:49" + switch \tmp_tmp_insn [20] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\is_priv_insn[0:0] 1'1 + case + assign $2\is_priv_insn[0:0] 1'0 + end + case + assign $1\is_priv_insn[0:0] 1'0 + end + sync always + update \is_priv_insn $0\is_priv_insn[0:0] + end + attribute \src "libresoc.v:74699.3-74780.6" + process $proc$libresoc.v:74699$3625 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\rc[0:0] $1\rc[0:0] + assign $0\spr1[9:0] $1\spr1[9:0] + assign $0\spr1_ok[0:0] $1\spr1_ok[0:0] + assign $0\msr[63:0] $1\msr[63:0] + assign $0\ea_ok[0:0] $1\ea_ok[0:0] + assign $0\ea[4:0] $1\ea[4:0] + assign { } { } + assign $0\cr_out[2:0] $1\cr_out[2:0] + assign $0\lk[0:0] $1\lk[0:0] + assign $0\cia[63:0] $1\cia[63:0] + assign $0\cr_in1[2:0] $1\cr_in1[2:0] + assign $0\cr_in1_ok[0:0] $1\cr_in1_ok[0:0] + assign $0\cr_in2[2:0] $1\cr_in2[2:0] + assign $0\cr_in2$1[2:0]$3626 $1\cr_in2$1[2:0]$3628 + assign $0\cr_in2_ok[0:0] $1\cr_in2_ok[0:0] + assign $0\cr_in2_ok$2[0:0]$3627 $1\cr_in2_ok$2[0:0]$3629 + assign $0\cr_out_ok[0:0] $1\cr_out_ok[0:0] + assign $0\cr_rd[7:0] $1\cr_rd[7:0] + assign $0\cr_rd_ok[0:0] $1\cr_rd_ok[0:0] + assign $0\cr_wr[7:0] $1\cr_wr[7:0] + assign $0\cr_wr_ok[0:0] $1\cr_wr_ok[0:0] + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fn_unit[11:0] $1\fn_unit[11:0] + assign $0\input_carry[1:0] $1\input_carry[1:0] + assign $0\insn[31:0] $1\insn[31:0] + assign $0\insn_type[6:0] $1\insn_type[6:0] + assign $0\is_32bit[0:0] $1\is_32bit[0:0] + assign $0\oe[0:0] $1\oe[0:0] + assign $0\oe_ok[0:0] $1\oe_ok[0:0] + assign $0\rc_ok[0:0] $1\rc_ok[0:0] + assign $0\reg1[4:0] $1\reg1[4:0] + assign $0\reg1_ok[0:0] $1\reg1_ok[0:0] + assign $0\reg2[4:0] $1\reg2[4:0] + assign $0\reg2_ok[0:0] $1\reg2_ok[0:0] + assign $0\reg3[4:0] $1\reg3[4:0] + assign $0\reg3_ok[0:0] $1\reg3_ok[0:0] + assign $0\rego[4:0] $1\rego[4:0] + assign $0\rego_ok[0:0] $1\rego_ok[0:0] + assign $0\spro[9:0] $1\spro[9:0] + assign $0\spro_ok[0:0] $1\spro_ok[0:0] + assign $0\trapaddr[12:0] $1\trapaddr[12:0] + assign $0\traptype[6:0] $1\traptype[6:0] + assign $0\xer_in[2:0] $1\xer_in[2:0] + assign $0\xer_out[0:0] $1\xer_out[0:0] + assign $0\fasto1[2:0] $2\fasto1[2:0] + assign $0\fasto1_ok[0:0] $2\fasto1_ok[0:0] + assign $0\fasto2[2:0] $2\fasto2[2:0] + assign $0\fasto2_ok[0:0] $2\fasto2_ok[0:0] + assign $0\fast1[2:0] $2\fast1[2:0] + assign $0\fast1_ok[0:0] $2\fast1_ok[0:0] + assign $0\fast2[2:0] $2\fast2[2:0] + assign $0\fast2_ok[0:0] $2\fast2_ok[0:0] + assign $0\asmcode[7:0] \dec_asmcode + attribute \src "libresoc.v:74700.5-74700.29" + switch \initial + attribute \src "libresoc.v:74700.9-74700.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:895" + switch { \illeg_ok \priv_ok \ext_irq_ok \dec_irq_ok } + attribute \src "libresoc.v:0.0-0.0" + case 4'---1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\cr_out_ok[0:0] $1\cr_out[2:0] $1\cr_in2_ok$2[0:0]$3629 $1\cr_in2$1[2:0]$3628 $1\cr_in2_ok[0:0] $1\cr_in2[2:0] $1\cr_in1_ok[0:0] $1\cr_in1[2:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[4:0] $1\reg2_ok[0:0] $1\reg2[4:0] $1\reg1_ok[0:0] $1\reg1[4:0] $1\ea_ok[0:0] $1\ea[4:0] $1\rego_ok[0:0] $1\rego[4:0] $1\asmcode[7:0] } 122'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign $1\insn[31:0] \dec_opcode_in + assign $1\insn_type[6:0] 7'0111111 + assign $1\fn_unit[11:0] 12'000010000000 + assign $1\trapaddr[12:0] 13'0000010010000 + assign $1\traptype[6:0] 7'0100000 + assign $1\msr[63:0] \cur_msr + assign $1\cia[63:0] \cur_pc + attribute \src "libresoc.v:0.0-0.0" + case 4'--1- + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\cr_out_ok[0:0] $1\cr_out[2:0] $1\cr_in2_ok$2[0:0]$3629 $1\cr_in2$1[2:0]$3628 $1\cr_in2_ok[0:0] $1\cr_in2[2:0] $1\cr_in1_ok[0:0] $1\cr_in1[2:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[4:0] $1\reg2_ok[0:0] $1\reg2[4:0] $1\reg1_ok[0:0] $1\reg1[4:0] $1\ea_ok[0:0] $1\ea[4:0] $1\rego_ok[0:0] $1\rego[4:0] $1\asmcode[7:0] } 122'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign $1\insn[31:0] \dec_opcode_in + assign $1\insn_type[6:0] 7'0111111 + assign $1\fn_unit[11:0] 12'000010000000 + assign $1\trapaddr[12:0] 13'0000001010000 + assign $1\traptype[6:0] 7'0010000 + assign $1\msr[63:0] \cur_msr + assign $1\cia[63:0] \cur_pc + attribute \src "libresoc.v:0.0-0.0" + case 4'-1-- + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\cr_out_ok[0:0] $1\cr_out[2:0] $1\cr_in2_ok$2[0:0]$3629 $1\cr_in2$1[2:0]$3628 $1\cr_in2_ok[0:0] $1\cr_in2[2:0] $1\cr_in1_ok[0:0] $1\cr_in1[2:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[4:0] $1\reg2_ok[0:0] $1\reg2[4:0] $1\reg1_ok[0:0] $1\reg1[4:0] $1\ea_ok[0:0] $1\ea[4:0] $1\rego_ok[0:0] $1\rego[4:0] $1\asmcode[7:0] } 122'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign $1\insn[31:0] \dec_opcode_in + assign $1\insn_type[6:0] 7'0111111 + assign $1\fn_unit[11:0] 12'000010000000 + assign $1\trapaddr[12:0] 13'0000001110000 + assign $1\traptype[6:0] 7'0000010 + assign $1\msr[63:0] \cur_msr + assign $1\cia[63:0] \cur_pc + attribute \src "libresoc.v:0.0-0.0" + case 4'1--- + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\cr_out_ok[0:0] $1\cr_out[2:0] $1\cr_in2_ok$2[0:0]$3629 $1\cr_in2$1[2:0]$3628 $1\cr_in2_ok[0:0] $1\cr_in2[2:0] $1\cr_in1_ok[0:0] $1\cr_in1[2:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[4:0] $1\reg2_ok[0:0] $1\reg2[4:0] $1\reg1_ok[0:0] $1\reg1[4:0] $1\ea_ok[0:0] $1\ea[4:0] $1\rego_ok[0:0] $1\rego[4:0] $1\asmcode[7:0] } 122'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign $1\insn[31:0] \dec_opcode_in + assign $1\insn_type[6:0] 7'0111111 + assign $1\fn_unit[11:0] 12'000010000000 + assign $1\trapaddr[12:0] 13'0000001110000 + assign $1\traptype[6:0] 7'1000000 + assign $1\msr[63:0] \cur_msr + assign $1\cia[63:0] \cur_pc + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\trapaddr[12:0] $1\traptype[6:0] $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\fn_unit[11:0] $1\insn_type[6:0] $1\insn[31:0] $1\cia[63:0] $1\msr[63:0] $1\cr_out_ok[0:0] $1\cr_out[2:0] $1\cr_in2_ok$2[0:0]$3629 $1\cr_in2$1[2:0]$3628 $1\cr_in2_ok[0:0] $1\cr_in2[2:0] $1\cr_in1_ok[0:0] $1\cr_in1[2:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[4:0] $1\reg2_ok[0:0] $1\reg2[4:0] $1\reg1_ok[0:0] $1\reg1[4:0] $1\ea_ok[0:0] $1\ea[4:0] $1\rego_ok[0:0] $1\rego[4:0] $1\asmcode[7:0] } { \tmp_tmp_is_32bit \tmp_tmp_cr_wr_ok \tmp_tmp_cr_wr \tmp_tmp_cr_rd_ok \tmp_tmp_cr_rd \tmp_tmp_trapaddr \tmp_tmp_traptype \tmp_tmp_input_carry \tmp_tmp_oe_ok \tmp_tmp_oe \tmp_tmp_rc_ok \tmp_tmp_rc \tmp_tmp_lk \tmp_tmp_fn_unit \tmp_tmp_insn_type \tmp_tmp_insn \tmp_tmp_cia \tmp_tmp_msr \tmp_cr_out_ok \tmp_cr_out \tmp_cr_in2_ok$12 \tmp_cr_in2$11 \tmp_cr_in2_ok \tmp_cr_in2 \tmp_cr_in1_ok \tmp_cr_in1 \tmp_fasto2_ok \tmp_fasto2 \tmp_fasto1_ok \tmp_fasto1 \tmp_fast2_ok \tmp_fast2 \tmp_fast1_ok \tmp_fast1 \tmp_xer_out \tmp_xer_in \tmp_spr1_ok \tmp_spr1 \tmp_spro_ok \tmp_spro \tmp_reg3_ok \tmp_reg3 \tmp_reg2_ok \tmp_reg2 \tmp_reg1_ok \tmp_reg1 \tmp_ea_ok \tmp_ea \tmp_rego_ok \tmp_rego \tmp_asmcode } + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:924" + switch \$33 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $2\fasto1[2:0] 3'011 + assign $2\fasto1_ok[0:0] 1'1 + assign $2\fasto2[2:0] 3'100 + assign $2\fasto2_ok[0:0] 1'1 + case + assign $2\fasto1[2:0] $1\fasto1[2:0] + assign $2\fasto1_ok[0:0] $1\fasto1_ok[0:0] + assign $2\fasto2[2:0] $1\fasto2[2:0] + assign $2\fasto2_ok[0:0] $1\fasto2_ok[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:933" + switch \$35 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $2\fast1[2:0] 3'011 + assign $2\fast1_ok[0:0] 1'1 + assign $2\fast2[2:0] 3'100 + assign $2\fast2_ok[0:0] 1'1 + case + assign $2\fast1[2:0] $1\fast1[2:0] + assign $2\fast1_ok[0:0] $1\fast1_ok[0:0] + assign $2\fast2[2:0] $1\fast2[2:0] + assign $2\fast2_ok[0:0] $1\fast2_ok[0:0] + end + sync always + update \fast1 $0\fast1[2:0] + update \fast1_ok $0\fast1_ok[0:0] + update \fast2 $0\fast2[2:0] + update \fast2_ok $0\fast2_ok[0:0] + update \rc $0\rc[0:0] + update \spr1 $0\spr1[9:0] + update \spr1_ok $0\spr1_ok[0:0] + update \msr $0\msr[63:0] + update \ea_ok $0\ea_ok[0:0] + update \ea $0\ea[4:0] + update \asmcode $0\asmcode[7:0] + update \cr_out $0\cr_out[2:0] + update \lk $0\lk[0:0] + update \cia $0\cia[63:0] + update \cr_in1 $0\cr_in1[2:0] + update \cr_in1_ok $0\cr_in1_ok[0:0] + update \cr_in2 $0\cr_in2[2:0] + update \cr_in2$1 $0\cr_in2$1[2:0]$3626 + update \cr_in2_ok $0\cr_in2_ok[0:0] + update \cr_in2_ok$2 $0\cr_in2_ok$2[0:0]$3627 + update \cr_out_ok $0\cr_out_ok[0:0] + update \cr_rd $0\cr_rd[7:0] + update \cr_rd_ok $0\cr_rd_ok[0:0] + update \cr_wr $0\cr_wr[7:0] + update \cr_wr_ok $0\cr_wr_ok[0:0] + update \fasto1 $0\fasto1[2:0] + update \fasto1_ok $0\fasto1_ok[0:0] + update \fasto2 $0\fasto2[2:0] + update \fasto2_ok $0\fasto2_ok[0:0] + update \fn_unit $0\fn_unit[11:0] + update \input_carry $0\input_carry[1:0] + update \insn $0\insn[31:0] + update \insn_type $0\insn_type[6:0] + update \is_32bit $0\is_32bit[0:0] + update \oe $0\oe[0:0] + update \oe_ok $0\oe_ok[0:0] + update \rc_ok $0\rc_ok[0:0] + update \reg1 $0\reg1[4:0] + update \reg1_ok $0\reg1_ok[0:0] + update \reg2 $0\reg2[4:0] + update \reg2_ok $0\reg2_ok[0:0] + update \reg3 $0\reg3[4:0] + update \reg3_ok $0\reg3_ok[0:0] + update \rego $0\rego[4:0] + update \rego_ok $0\rego_ok[0:0] + update \spro $0\spro[9:0] + update \spro_ok $0\spro_ok[0:0] + update \trapaddr $0\trapaddr[12:0] + update \traptype $0\traptype[6:0] + update \xer_in $0\xer_in[2:0] + update \xer_out $0\xer_out[0:0] + end + connect \$13 $eq$libresoc.v:74480$3608_Y + connect \$15 $eq$libresoc.v:74481$3609_Y + connect \$17 $eq$libresoc.v:74482$3610_Y + connect \$19 $eq$libresoc.v:74483$3611_Y + connect \$21 $and$libresoc.v:74484$3612_Y + connect \$23 $and$libresoc.v:74485$3613_Y + connect \$25 $and$libresoc.v:74486$3614_Y + connect \$27 $eq$libresoc.v:74487$3615_Y + connect \$29 $eq$libresoc.v:74488$3616_Y + connect \$31 $eq$libresoc.v:74489$3617_Y + connect \$33 $or$libresoc.v:74490$3618_Y + connect \$35 $eq$libresoc.v:74491$3619_Y + connect \tmp_asmcode 8'00000000 + connect \tmp_tmp_traptype 7'0000000 + connect \illeg_ok \$27 + connect \priv_ok \$25 + connect \dec_irq_ok \$23 + connect \ext_irq_ok \$21 + connect { \tmp_cr_out_ok \tmp_cr_out } { \dec_cr_out_cr_bitfield_ok \dec_cr_out_cr_bitfield } + connect { \tmp_cr_in2_ok$12 \tmp_cr_in2$11 } { \dec_cr_in_cr_bitfield_o_ok \dec_cr_in_cr_bitfield_o } + connect { \tmp_cr_in2_ok \tmp_cr_in2 } { \dec_cr_in_cr_bitfield_b_ok \dec_cr_in_cr_bitfield_b } + connect { \tmp_cr_in1_ok \tmp_cr_in1 } { \dec_cr_in_cr_bitfield_ok \dec_cr_in_cr_bitfield } + connect { \tmp_fasto2_ok \tmp_fasto2 } { \dec_o2_fast_o_ok \dec_o2_fast_o } + connect { \tmp_fasto1_ok \tmp_fasto1 } { \dec_o_fast_o_ok \dec_o_fast_o } + connect { \tmp_fast2_ok \tmp_fast2 } { \dec_b_fast_b_ok \dec_b_fast_b } + connect { \tmp_fast1_ok \tmp_fast1 } { \dec_a_fast_a_ok \dec_a_fast_a } + connect { \tmp_spro_ok \tmp_spro } { \dec_o_spr_o_ok \dec_o_spr_o } + connect { \tmp_spr1_ok \tmp_spr1 } { \dec_a_spr_a_ok \dec_a_spr_a } + connect { \tmp_ea_ok \tmp_ea } { \dec_o2_reg_o_ok \dec_o2_reg_o } + connect { \tmp_rego_ok \tmp_rego } { \dec_o_reg_o_ok \dec_o_reg_o } + connect { \tmp_reg3_ok \tmp_reg3 } { \dec_c_reg_c_ok \dec_c_reg_c } + connect { \tmp_reg2_ok \tmp_reg2 } { \dec_b_reg_b_ok \dec_b_reg_b } + connect { \tmp_reg1_ok \tmp_reg1 } { \dec_a_reg_a_ok \dec_a_reg_a } + connect \dec_o2_lk \tmp_tmp_lk + connect \sel_in \dec_out_sel + connect \dec_o_sel_in \dec_out_sel + connect \dec_c_sel_in \dec_in3_sel + connect \dec_b_sel_in \dec_in2_sel + connect \dec_a_sel_in \dec_in1_sel + connect \insn_in$10 \dec_opcode_in + connect \insn_in$9 \dec_opcode_in + connect \insn_in$8 \dec_opcode_in + connect \insn_in$7 \dec_opcode_in + connect \insn_in$6 \dec_opcode_in + connect \tmp_tmp_is_32bit \dec_is_32b + connect \tmp_tmp_input_carry \dec_cry_in + connect { \tmp_tmp_cr_wr_ok \tmp_tmp_cr_wr } { \dec_cr_out_cr_fxm_ok \dec_cr_out_cr_fxm } + connect { \tmp_tmp_cr_rd_ok \tmp_tmp_cr_rd } { \dec_cr_in_cr_fxm_ok \dec_cr_in_cr_fxm } + connect { \tmp_tmp_oe_ok \tmp_tmp_oe } { \dec_oe_oe_ok \dec_oe_oe } + connect { \tmp_tmp_rc_ok \tmp_tmp_rc } { \dec_rc_rc_ok \dec_rc_rc } + connect \tmp_tmp_fn_unit \dec_function_unit + connect \tmp_tmp_insn_type \dec_internal_op + connect \tmp_tmp_cia \cur_pc + connect \tmp_tmp_msr \cur_msr + connect \dec_cr_out_rc_in \dec_rc_rc + connect \dec_cr_out_sel_in \dec_cr_out + connect \dec_cr_in_sel_in \dec_cr_in + connect \dec_oe_sel_in \dec_rc_sel + connect \dec_rc_sel_in \dec_rc_sel + connect \dec_cr_out_insn_in \dec_opcode_in + connect \dec_cr_in_insn_in \dec_opcode_in + connect \insn_in$5 \dec_opcode_in + connect \insn_in \dec_opcode_in + connect \tmp_tmp_insn \dec_opcode_in +end +attribute \src "libresoc.v:74837.1-75984.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec30" +attribute \generator "nMigen" +module \dec30 + attribute \src "libresoc.v:75280.3-75316.6" + wire width 8 $0\dec30_asmcode[7:0] + attribute \src "libresoc.v:75428.3-75464.6" + wire $0\dec30_br[0:0] + attribute \src "libresoc.v:75909.3-75945.6" + wire width 3 $0\dec30_cr_in[2:0] + attribute \src "libresoc.v:75946.3-75982.6" + wire width 3 $0\dec30_cr_out[2:0] + attribute \src "libresoc.v:75243.3-75279.6" + wire width 2 $0\dec30_cry_in[1:0] + attribute \src "libresoc.v:75391.3-75427.6" + wire $0\dec30_cry_out[0:0] + attribute \src "libresoc.v:75724.3-75760.6" + wire width 5 $0\dec30_form[4:0] + attribute \src "libresoc.v:75095.3-75131.6" + wire width 12 $0\dec30_function_unit[11:0] + attribute \src "libresoc.v:75761.3-75797.6" + wire width 3 $0\dec30_in1_sel[2:0] + attribute \src "libresoc.v:75798.3-75834.6" + wire width 4 $0\dec30_in2_sel[3:0] + attribute \src "libresoc.v:75835.3-75871.6" + wire width 2 $0\dec30_in3_sel[1:0] + attribute \src "libresoc.v:75502.3-75538.6" + wire width 7 $0\dec30_internal_op[6:0] + attribute \src "libresoc.v:75317.3-75353.6" + wire $0\dec30_inv_a[0:0] + attribute \src "libresoc.v:75354.3-75390.6" + wire $0\dec30_inv_out[0:0] + attribute \src "libresoc.v:75576.3-75612.6" + wire $0\dec30_is_32b[0:0] + attribute \src "libresoc.v:75132.3-75168.6" + wire width 4 $0\dec30_ldst_len[3:0] + attribute \src "libresoc.v:75650.3-75686.6" + wire $0\dec30_lk[0:0] + attribute \src "libresoc.v:75872.3-75908.6" + wire width 2 $0\dec30_out_sel[1:0] + attribute \src "libresoc.v:75206.3-75242.6" + wire width 2 $0\dec30_rc_sel[1:0] + attribute \src "libresoc.v:75539.3-75575.6" + wire $0\dec30_rsrv[0:0] + attribute \src "libresoc.v:75687.3-75723.6" + wire $0\dec30_sgl_pipe[0:0] + attribute \src "libresoc.v:75613.3-75649.6" + wire $0\dec30_sgn[0:0] + attribute \src "libresoc.v:75465.3-75501.6" + wire $0\dec30_sgn_ext[0:0] + attribute \src "libresoc.v:75169.3-75205.6" + wire width 2 $0\dec30_upd[1:0] + attribute \src "libresoc.v:74838.7-74838.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:75280.3-75316.6" + wire width 8 $1\dec30_asmcode[7:0] + attribute \src "libresoc.v:75428.3-75464.6" + wire $1\dec30_br[0:0] + attribute \src "libresoc.v:75909.3-75945.6" + wire width 3 $1\dec30_cr_in[2:0] + attribute \src "libresoc.v:75946.3-75982.6" + wire width 3 $1\dec30_cr_out[2:0] + attribute \src "libresoc.v:75243.3-75279.6" + wire width 2 $1\dec30_cry_in[1:0] + attribute \src "libresoc.v:75391.3-75427.6" + wire $1\dec30_cry_out[0:0] + attribute \src "libresoc.v:75724.3-75760.6" + wire width 5 $1\dec30_form[4:0] + attribute \src "libresoc.v:75095.3-75131.6" + wire width 12 $1\dec30_function_unit[11:0] + attribute \src "libresoc.v:75761.3-75797.6" + wire width 3 $1\dec30_in1_sel[2:0] + attribute \src "libresoc.v:75798.3-75834.6" + wire width 4 $1\dec30_in2_sel[3:0] + attribute \src "libresoc.v:75835.3-75871.6" + wire width 2 $1\dec30_in3_sel[1:0] + attribute \src "libresoc.v:75502.3-75538.6" + wire width 7 $1\dec30_internal_op[6:0] + attribute \src "libresoc.v:75317.3-75353.6" + wire $1\dec30_inv_a[0:0] + attribute \src "libresoc.v:75354.3-75390.6" + wire $1\dec30_inv_out[0:0] + attribute \src "libresoc.v:75576.3-75612.6" + wire $1\dec30_is_32b[0:0] + attribute \src "libresoc.v:75132.3-75168.6" + wire width 4 $1\dec30_ldst_len[3:0] + attribute \src "libresoc.v:75650.3-75686.6" + wire $1\dec30_lk[0:0] + attribute \src "libresoc.v:75872.3-75908.6" + wire width 2 $1\dec30_out_sel[1:0] + attribute \src "libresoc.v:75206.3-75242.6" + wire width 2 $1\dec30_rc_sel[1:0] + attribute \src "libresoc.v:75539.3-75575.6" + wire $1\dec30_rsrv[0:0] + attribute \src "libresoc.v:75687.3-75723.6" + wire $1\dec30_sgl_pipe[0:0] + attribute \src "libresoc.v:75613.3-75649.6" + wire $1\dec30_sgn[0:0] + attribute \src "libresoc.v:75465.3-75501.6" + wire $1\dec30_sgn_ext[0:0] + attribute \src "libresoc.v:75169.3-75205.6" + wire width 2 $1\dec30_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 output 4 \dec30_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 18 \dec30_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 9 \dec30_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 10 \dec30_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 14 \dec30_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 17 \dec30_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 output 3 \dec30_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \dec30_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \dec30_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 6 \dec30_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 7 \dec30_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \dec30_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 15 \dec30_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 16 \dec30_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 21 \dec30_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 11 \dec30_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 23 \dec30_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 8 \dec30_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 13 \dec30_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 20 \dec30_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 24 \dec30_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 22 \dec30_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 19 \dec30_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 12 \dec30_upd + attribute \src "libresoc.v:74838.7-74838.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 4 \opcode_switch + attribute \src "libresoc.v:74838.7-74838.20" + process $proc$libresoc.v:74838$3655 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:75095.3-75131.6" + process $proc$libresoc.v:75095$3631 + assign { } { } + assign { } { } + assign $0\dec30_function_unit[11:0] $1\dec30_function_unit[11:0] + attribute \src "libresoc.v:75096.5-75096.29" + switch \initial + attribute \src "libresoc.v:75096.9-75096.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_function_unit[11:0] 12'000000001000 + case + assign $1\dec30_function_unit[11:0] 12'000000000000 + end + sync always + update \dec30_function_unit $0\dec30_function_unit[11:0] + end + attribute \src "libresoc.v:75132.3-75168.6" + process $proc$libresoc.v:75132$3632 + assign { } { } + assign { } { } + assign $0\dec30_ldst_len[3:0] $1\dec30_ldst_len[3:0] + attribute \src "libresoc.v:75133.5-75133.29" + switch \initial + attribute \src "libresoc.v:75133.9-75133.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_ldst_len[3:0] 4'0000 + case + assign $1\dec30_ldst_len[3:0] 4'0000 + end + sync always + update \dec30_ldst_len $0\dec30_ldst_len[3:0] + end + attribute \src "libresoc.v:75169.3-75205.6" + process $proc$libresoc.v:75169$3633 + assign { } { } + assign { } { } + assign $0\dec30_upd[1:0] $1\dec30_upd[1:0] + attribute \src "libresoc.v:75170.5-75170.29" + switch \initial + attribute \src "libresoc.v:75170.9-75170.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_upd[1:0] 2'00 + case + assign $1\dec30_upd[1:0] 2'00 + end + sync always + update \dec30_upd $0\dec30_upd[1:0] + end + attribute \src "libresoc.v:75206.3-75242.6" + process $proc$libresoc.v:75206$3634 + assign { } { } + assign { } { } + assign $0\dec30_rc_sel[1:0] $1\dec30_rc_sel[1:0] + attribute \src "libresoc.v:75207.5-75207.29" + switch \initial + attribute \src "libresoc.v:75207.9-75207.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_rc_sel[1:0] 2'10 + case + assign $1\dec30_rc_sel[1:0] 2'00 + end + sync always + update \dec30_rc_sel $0\dec30_rc_sel[1:0] + end + attribute \src "libresoc.v:75243.3-75279.6" + process $proc$libresoc.v:75243$3635 + assign { } { } + assign { } { } + assign $0\dec30_cry_in[1:0] $1\dec30_cry_in[1:0] + attribute \src "libresoc.v:75244.5-75244.29" + switch \initial + attribute \src "libresoc.v:75244.9-75244.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_cry_in[1:0] 2'00 + case + assign $1\dec30_cry_in[1:0] 2'00 + end + sync always + update \dec30_cry_in $0\dec30_cry_in[1:0] + end + attribute \src "libresoc.v:75280.3-75316.6" + process $proc$libresoc.v:75280$3636 + assign { } { } + assign { } { } + assign $0\dec30_asmcode[7:0] $1\dec30_asmcode[7:0] + attribute \src "libresoc.v:75281.5-75281.29" + switch \initial + attribute \src "libresoc.v:75281.9-75281.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_asmcode[7:0] 8'10010100 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_asmcode[7:0] 8'10010100 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_asmcode[7:0] 8'10010101 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_asmcode[7:0] 8'10010101 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_asmcode[7:0] 8'10010110 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_asmcode[7:0] 8'10010110 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_asmcode[7:0] 8'10010111 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_asmcode[7:0] 8'10010111 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_asmcode[7:0] 8'10010010 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_asmcode[7:0] 8'10010011 + case + assign $1\dec30_asmcode[7:0] 8'00000000 + end + sync always + update \dec30_asmcode $0\dec30_asmcode[7:0] + end + attribute \src "libresoc.v:75317.3-75353.6" + process $proc$libresoc.v:75317$3637 + assign { } { } + assign { } { } + assign $0\dec30_inv_a[0:0] $1\dec30_inv_a[0:0] + attribute \src "libresoc.v:75318.5-75318.29" + switch \initial + attribute \src "libresoc.v:75318.9-75318.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_inv_a[0:0] 1'0 + case + assign $1\dec30_inv_a[0:0] 1'0 + end + sync always + update \dec30_inv_a $0\dec30_inv_a[0:0] + end + attribute \src "libresoc.v:75354.3-75390.6" + process $proc$libresoc.v:75354$3638 + assign { } { } + assign { } { } + assign $0\dec30_inv_out[0:0] $1\dec30_inv_out[0:0] + attribute \src "libresoc.v:75355.5-75355.29" + switch \initial + attribute \src "libresoc.v:75355.9-75355.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_inv_out[0:0] 1'0 + case + assign $1\dec30_inv_out[0:0] 1'0 + end + sync always + update \dec30_inv_out $0\dec30_inv_out[0:0] + end + attribute \src "libresoc.v:75391.3-75427.6" + process $proc$libresoc.v:75391$3639 + assign { } { } + assign { } { } + assign $0\dec30_cry_out[0:0] $1\dec30_cry_out[0:0] + attribute \src "libresoc.v:75392.5-75392.29" + switch \initial + attribute \src "libresoc.v:75392.9-75392.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_cry_out[0:0] 1'0 + case + assign $1\dec30_cry_out[0:0] 1'0 + end + sync always + update \dec30_cry_out $0\dec30_cry_out[0:0] + end + attribute \src "libresoc.v:75428.3-75464.6" + process $proc$libresoc.v:75428$3640 + assign { } { } + assign { } { } + assign $0\dec30_br[0:0] $1\dec30_br[0:0] + attribute \src "libresoc.v:75429.5-75429.29" + switch \initial + attribute \src "libresoc.v:75429.9-75429.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_br[0:0] 1'0 + case + assign $1\dec30_br[0:0] 1'0 + end + sync always + update \dec30_br $0\dec30_br[0:0] + end + attribute \src "libresoc.v:75465.3-75501.6" + process $proc$libresoc.v:75465$3641 + assign { } { } + assign { } { } + assign $0\dec30_sgn_ext[0:0] $1\dec30_sgn_ext[0:0] + attribute \src "libresoc.v:75466.5-75466.29" + switch \initial + attribute \src "libresoc.v:75466.9-75466.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_sgn_ext[0:0] 1'0 + case + assign $1\dec30_sgn_ext[0:0] 1'0 + end + sync always + update \dec30_sgn_ext $0\dec30_sgn_ext[0:0] + end + attribute \src "libresoc.v:75502.3-75538.6" + process $proc$libresoc.v:75502$3642 + assign { } { } + assign { } { } + assign $0\dec30_internal_op[6:0] $1\dec30_internal_op[6:0] + attribute \src "libresoc.v:75503.5-75503.29" + switch \initial + attribute \src "libresoc.v:75503.9-75503.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_internal_op[6:0] 7'0111000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_internal_op[6:0] 7'0111000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_internal_op[6:0] 7'0111001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_internal_op[6:0] 7'0111001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_internal_op[6:0] 7'0111010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_internal_op[6:0] 7'0111010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_internal_op[6:0] 7'0111000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_internal_op[6:0] 7'0111000 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_internal_op[6:0] 7'0111001 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_internal_op[6:0] 7'0111010 + case + assign $1\dec30_internal_op[6:0] 7'0000000 + end + sync always + update \dec30_internal_op $0\dec30_internal_op[6:0] + end + attribute \src "libresoc.v:75539.3-75575.6" + process $proc$libresoc.v:75539$3643 + assign { } { } + assign { } { } + assign $0\dec30_rsrv[0:0] $1\dec30_rsrv[0:0] + attribute \src "libresoc.v:75540.5-75540.29" + switch \initial + attribute \src "libresoc.v:75540.9-75540.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_rsrv[0:0] 1'0 + case + assign $1\dec30_rsrv[0:0] 1'0 + end + sync always + update \dec30_rsrv $0\dec30_rsrv[0:0] + end + attribute \src "libresoc.v:75576.3-75612.6" + process $proc$libresoc.v:75576$3644 + assign { } { } + assign { } { } + assign $0\dec30_is_32b[0:0] $1\dec30_is_32b[0:0] + attribute \src "libresoc.v:75577.5-75577.29" + switch \initial + attribute \src "libresoc.v:75577.9-75577.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_is_32b[0:0] 1'0 + case + assign $1\dec30_is_32b[0:0] 1'0 + end + sync always + update \dec30_is_32b $0\dec30_is_32b[0:0] + end + attribute \src "libresoc.v:75613.3-75649.6" + process $proc$libresoc.v:75613$3645 + assign { } { } + assign { } { } + assign $0\dec30_sgn[0:0] $1\dec30_sgn[0:0] + attribute \src "libresoc.v:75614.5-75614.29" + switch \initial + attribute \src "libresoc.v:75614.9-75614.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_sgn[0:0] 1'0 + case + assign $1\dec30_sgn[0:0] 1'0 + end + sync always + update \dec30_sgn $0\dec30_sgn[0:0] + end + attribute \src "libresoc.v:75650.3-75686.6" + process $proc$libresoc.v:75650$3646 + assign { } { } + assign { } { } + assign $0\dec30_lk[0:0] $1\dec30_lk[0:0] + attribute \src "libresoc.v:75651.5-75651.29" + switch \initial + attribute \src "libresoc.v:75651.9-75651.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_lk[0:0] 1'0 + case + assign $1\dec30_lk[0:0] 1'0 + end + sync always + update \dec30_lk $0\dec30_lk[0:0] + end + attribute \src "libresoc.v:75687.3-75723.6" + process $proc$libresoc.v:75687$3647 + assign { } { } + assign { } { } + assign $0\dec30_sgl_pipe[0:0] $1\dec30_sgl_pipe[0:0] + attribute \src "libresoc.v:75688.5-75688.29" + switch \initial + attribute \src "libresoc.v:75688.9-75688.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_sgl_pipe[0:0] 1'0 + case + assign $1\dec30_sgl_pipe[0:0] 1'0 + end + sync always + update \dec30_sgl_pipe $0\dec30_sgl_pipe[0:0] + end + attribute \src "libresoc.v:75724.3-75760.6" + process $proc$libresoc.v:75724$3648 + assign { } { } + assign { } { } + assign $0\dec30_form[4:0] $1\dec30_form[4:0] + attribute \src "libresoc.v:75725.5-75725.29" + switch \initial + attribute \src "libresoc.v:75725.9-75725.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_form[4:0] 5'10100 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_form[4:0] 5'10100 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_form[4:0] 5'10101 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_form[4:0] 5'10101 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_form[4:0] 5'10100 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_form[4:0] 5'10100 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_form[4:0] 5'10100 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_form[4:0] 5'10100 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_form[4:0] 5'10100 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_form[4:0] 5'10100 + case + assign $1\dec30_form[4:0] 5'00000 + end + sync always + update \dec30_form $0\dec30_form[4:0] + end + attribute \src "libresoc.v:75761.3-75797.6" + process $proc$libresoc.v:75761$3649 + assign { } { } + assign { } { } + assign $0\dec30_in1_sel[2:0] $1\dec30_in1_sel[2:0] + attribute \src "libresoc.v:75762.5-75762.29" + switch \initial + attribute \src "libresoc.v:75762.9-75762.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_in1_sel[2:0] 3'000 + case + assign $1\dec30_in1_sel[2:0] 3'000 + end + sync always + update \dec30_in1_sel $0\dec30_in1_sel[2:0] + end + attribute \src "libresoc.v:75798.3-75834.6" + process $proc$libresoc.v:75798$3650 + assign { } { } + assign { } { } + assign $0\dec30_in2_sel[3:0] $1\dec30_in2_sel[3:0] + attribute \src "libresoc.v:75799.5-75799.29" + switch \initial + attribute \src "libresoc.v:75799.9-75799.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_in2_sel[3:0] 4'0001 + case + assign $1\dec30_in2_sel[3:0] 4'0000 + end + sync always + update \dec30_in2_sel $0\dec30_in2_sel[3:0] + end + attribute \src "libresoc.v:75835.3-75871.6" + process $proc$libresoc.v:75835$3651 + assign { } { } + assign { } { } + assign $0\dec30_in3_sel[1:0] $1\dec30_in3_sel[1:0] + attribute \src "libresoc.v:75836.5-75836.29" + switch \initial + attribute \src "libresoc.v:75836.9-75836.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_in3_sel[1:0] 2'01 + case + assign $1\dec30_in3_sel[1:0] 2'00 + end + sync always + update \dec30_in3_sel $0\dec30_in3_sel[1:0] + end + attribute \src "libresoc.v:75872.3-75908.6" + process $proc$libresoc.v:75872$3652 + assign { } { } + assign { } { } + assign $0\dec30_out_sel[1:0] $1\dec30_out_sel[1:0] + attribute \src "libresoc.v:75873.5-75873.29" + switch \initial + attribute \src "libresoc.v:75873.9-75873.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_out_sel[1:0] 2'10 + case + assign $1\dec30_out_sel[1:0] 2'00 + end + sync always + update \dec30_out_sel $0\dec30_out_sel[1:0] + end + attribute \src "libresoc.v:75909.3-75945.6" + process $proc$libresoc.v:75909$3653 + assign { } { } + assign { } { } + assign $0\dec30_cr_in[2:0] $1\dec30_cr_in[2:0] + attribute \src "libresoc.v:75910.5-75910.29" + switch \initial + attribute \src "libresoc.v:75910.9-75910.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_cr_in[2:0] 3'000 + case + assign $1\dec30_cr_in[2:0] 3'000 + end + sync always + update \dec30_cr_in $0\dec30_cr_in[2:0] + end + attribute \src "libresoc.v:75946.3-75982.6" + process $proc$libresoc.v:75946$3654 + assign { } { } + assign { } { } + assign $0\dec30_cr_out[2:0] $1\dec30_cr_out[2:0] + attribute \src "libresoc.v:75947.5-75947.29" + switch \initial + attribute \src "libresoc.v:75947.9-75947.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_cr_out[2:0] 3'001 + case + assign $1\dec30_cr_out[2:0] 3'000 + end + sync always + update \dec30_cr_out $0\dec30_cr_out[2:0] + end + connect \opcode_switch \opcode_in [4:1] +end +attribute \src "libresoc.v:75988.1-82358.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31" +attribute \generator "nMigen" +module \dec31 + attribute \src "libresoc.v:81057.3-81117.6" + wire width 8 $0\dec31_asmcode[7:0] + attribute \src "libresoc.v:81911.3-81971.6" + wire $0\dec31_br[0:0] + attribute \src "libresoc.v:81362.3-81422.6" + wire width 3 $0\dec31_cr_in[2:0] + attribute \src "libresoc.v:81423.3-81483.6" + wire width 3 $0\dec31_cr_out[2:0] + attribute \src "libresoc.v:81667.3-81727.6" + wire width 2 $0\dec31_cry_in[1:0] + attribute \src "libresoc.v:81850.3-81910.6" + wire $0\dec31_cry_out[0:0] + attribute \src "libresoc.v:80996.3-81056.6" + wire width 5 $0\dec31_form[4:0] + attribute \src "libresoc.v:80874.3-80934.6" + wire width 12 $0\dec31_function_unit[11:0] + attribute \src "libresoc.v:81118.3-81178.6" + wire width 3 $0\dec31_in1_sel[2:0] + attribute \src "libresoc.v:81179.3-81239.6" + wire width 4 $0\dec31_in2_sel[3:0] + attribute \src "libresoc.v:81240.3-81300.6" + wire width 2 $0\dec31_in3_sel[1:0] + attribute \src "libresoc.v:80935.3-80995.6" + wire width 7 $0\dec31_internal_op[6:0] + attribute \src "libresoc.v:81728.3-81788.6" + wire $0\dec31_inv_a[0:0] + attribute \src "libresoc.v:81789.3-81849.6" + wire $0\dec31_inv_out[0:0] + attribute \src "libresoc.v:82094.3-82154.6" + wire $0\dec31_is_32b[0:0] + attribute \src "libresoc.v:81484.3-81544.6" + wire width 4 $0\dec31_ldst_len[3:0] + attribute \src "libresoc.v:82216.3-82276.6" + wire $0\dec31_lk[0:0] + attribute \src "libresoc.v:81301.3-81361.6" + wire width 2 $0\dec31_out_sel[1:0] + attribute \src "libresoc.v:81606.3-81666.6" + wire width 2 $0\dec31_rc_sel[1:0] + attribute \src "libresoc.v:82033.3-82093.6" + wire $0\dec31_rsrv[0:0] + attribute \src "libresoc.v:82277.3-82337.6" + wire $0\dec31_sgl_pipe[0:0] + attribute \src "libresoc.v:82155.3-82215.6" + wire $0\dec31_sgn[0:0] + attribute \src "libresoc.v:81972.3-82032.6" + wire $0\dec31_sgn_ext[0:0] + attribute \src "libresoc.v:81545.3-81605.6" + wire width 2 $0\dec31_upd[1:0] + attribute \src "libresoc.v:75989.7-75989.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:81057.3-81117.6" + wire width 8 $1\dec31_asmcode[7:0] + attribute \src "libresoc.v:81911.3-81971.6" + wire $1\dec31_br[0:0] + attribute \src "libresoc.v:81362.3-81422.6" + wire width 3 $1\dec31_cr_in[2:0] + attribute \src "libresoc.v:81423.3-81483.6" + wire width 3 $1\dec31_cr_out[2:0] + attribute \src "libresoc.v:81667.3-81727.6" + wire width 2 $1\dec31_cry_in[1:0] + attribute \src "libresoc.v:81850.3-81910.6" + wire $1\dec31_cry_out[0:0] + attribute \src "libresoc.v:80996.3-81056.6" + wire width 5 $1\dec31_form[4:0] + attribute \src "libresoc.v:80874.3-80934.6" + wire width 12 $1\dec31_function_unit[11:0] + attribute \src "libresoc.v:81118.3-81178.6" + wire width 3 $1\dec31_in1_sel[2:0] + attribute \src "libresoc.v:81179.3-81239.6" + wire width 4 $1\dec31_in2_sel[3:0] + attribute \src "libresoc.v:81240.3-81300.6" + wire width 2 $1\dec31_in3_sel[1:0] + attribute \src "libresoc.v:80935.3-80995.6" + wire width 7 $1\dec31_internal_op[6:0] + attribute \src "libresoc.v:81728.3-81788.6" + wire $1\dec31_inv_a[0:0] + attribute \src "libresoc.v:81789.3-81849.6" + wire $1\dec31_inv_out[0:0] + attribute \src "libresoc.v:82094.3-82154.6" + wire $1\dec31_is_32b[0:0] + attribute \src "libresoc.v:81484.3-81544.6" + wire width 4 $1\dec31_ldst_len[3:0] + attribute \src "libresoc.v:82216.3-82276.6" + wire $1\dec31_lk[0:0] + attribute \src "libresoc.v:81301.3-81361.6" + wire width 2 $1\dec31_out_sel[1:0] + attribute \src "libresoc.v:81606.3-81666.6" + wire width 2 $1\dec31_rc_sel[1:0] + attribute \src "libresoc.v:82033.3-82093.6" + wire $1\dec31_rsrv[0:0] + attribute \src "libresoc.v:82277.3-82337.6" + wire $1\dec31_sgl_pipe[0:0] + attribute \src "libresoc.v:82155.3-82215.6" + wire $1\dec31_sgn[0:0] + attribute \src "libresoc.v:81972.3-82032.6" + wire $1\dec31_sgn_ext[0:0] + attribute \src "libresoc.v:81545.3-81605.6" + wire width 2 $1\dec31_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 output 4 \dec31_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 18 \dec31_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 9 \dec31_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 10 \dec31_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 14 \dec31_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 17 \dec31_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 \dec31_dec_sub0_dec31_dec_sub0_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub0_dec31_dec_sub0_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec_sub0_dec31_dec_sub0_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec_sub0_dec31_dec_sub0_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub0_dec31_dec_sub0_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub0_dec31_dec_sub0_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 \dec31_dec_sub0_dec31_dec_sub0_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \dec31_dec_sub0_dec31_dec_sub0_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec_sub0_dec31_dec_sub0_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec31_dec_sub0_dec31_dec_sub0_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub0_dec31_dec_sub0_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 \dec31_dec_sub0_dec31_dec_sub0_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub0_dec31_dec_sub0_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub0_dec31_dec_sub0_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub0_dec31_dec_sub0_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec31_dec_sub0_dec31_dec_sub0_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub0_dec31_dec_sub0_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub0_dec31_dec_sub0_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub0_dec31_dec_sub0_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub0_dec31_dec_sub0_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub0_dec31_dec_sub0_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub0_dec31_dec_sub0_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub0_dec31_dec_sub0_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub0_dec31_dec_sub0_upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \dec31_dec_sub0_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 \dec31_dec_sub10_dec31_dec_sub10_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub10_dec31_dec_sub10_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec_sub10_dec31_dec_sub10_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec_sub10_dec31_dec_sub10_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub10_dec31_dec_sub10_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub10_dec31_dec_sub10_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 \dec31_dec_sub10_dec31_dec_sub10_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \dec31_dec_sub10_dec31_dec_sub10_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec_sub10_dec31_dec_sub10_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec31_dec_sub10_dec31_dec_sub10_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub10_dec31_dec_sub10_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 \dec31_dec_sub10_dec31_dec_sub10_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub10_dec31_dec_sub10_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub10_dec31_dec_sub10_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub10_dec31_dec_sub10_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec31_dec_sub10_dec31_dec_sub10_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub10_dec31_dec_sub10_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub10_dec31_dec_sub10_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub10_dec31_dec_sub10_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub10_dec31_dec_sub10_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub10_dec31_dec_sub10_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub10_dec31_dec_sub10_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub10_dec31_dec_sub10_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub10_dec31_dec_sub10_upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \dec31_dec_sub10_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 \dec31_dec_sub11_dec31_dec_sub11_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub11_dec31_dec_sub11_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec_sub11_dec31_dec_sub11_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec_sub11_dec31_dec_sub11_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub11_dec31_dec_sub11_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub11_dec31_dec_sub11_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 \dec31_dec_sub11_dec31_dec_sub11_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \dec31_dec_sub11_dec31_dec_sub11_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec_sub11_dec31_dec_sub11_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec31_dec_sub11_dec31_dec_sub11_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub11_dec31_dec_sub11_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 \dec31_dec_sub11_dec31_dec_sub11_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub11_dec31_dec_sub11_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub11_dec31_dec_sub11_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub11_dec31_dec_sub11_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec31_dec_sub11_dec31_dec_sub11_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub11_dec31_dec_sub11_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub11_dec31_dec_sub11_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub11_dec31_dec_sub11_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub11_dec31_dec_sub11_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub11_dec31_dec_sub11_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub11_dec31_dec_sub11_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub11_dec31_dec_sub11_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub11_dec31_dec_sub11_upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \dec31_dec_sub11_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 \dec31_dec_sub15_dec31_dec_sub15_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub15_dec31_dec_sub15_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec_sub15_dec31_dec_sub15_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec_sub15_dec31_dec_sub15_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub15_dec31_dec_sub15_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub15_dec31_dec_sub15_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 \dec31_dec_sub15_dec31_dec_sub15_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \dec31_dec_sub15_dec31_dec_sub15_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec_sub15_dec31_dec_sub15_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec31_dec_sub15_dec31_dec_sub15_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub15_dec31_dec_sub15_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 \dec31_dec_sub15_dec31_dec_sub15_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub15_dec31_dec_sub15_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub15_dec31_dec_sub15_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub15_dec31_dec_sub15_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec31_dec_sub15_dec31_dec_sub15_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub15_dec31_dec_sub15_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub15_dec31_dec_sub15_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub15_dec31_dec_sub15_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub15_dec31_dec_sub15_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub15_dec31_dec_sub15_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub15_dec31_dec_sub15_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub15_dec31_dec_sub15_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub15_dec31_dec_sub15_upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \dec31_dec_sub15_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 \dec31_dec_sub16_dec31_dec_sub16_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub16_dec31_dec_sub16_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec_sub16_dec31_dec_sub16_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec_sub16_dec31_dec_sub16_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub16_dec31_dec_sub16_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub16_dec31_dec_sub16_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 \dec31_dec_sub16_dec31_dec_sub16_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \dec31_dec_sub16_dec31_dec_sub16_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec_sub16_dec31_dec_sub16_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec31_dec_sub16_dec31_dec_sub16_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub16_dec31_dec_sub16_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 \dec31_dec_sub16_dec31_dec_sub16_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub16_dec31_dec_sub16_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub16_dec31_dec_sub16_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub16_dec31_dec_sub16_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec31_dec_sub16_dec31_dec_sub16_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub16_dec31_dec_sub16_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub16_dec31_dec_sub16_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub16_dec31_dec_sub16_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub16_dec31_dec_sub16_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub16_dec31_dec_sub16_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub16_dec31_dec_sub16_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub16_dec31_dec_sub16_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub16_dec31_dec_sub16_upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \dec31_dec_sub16_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 \dec31_dec_sub18_dec31_dec_sub18_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub18_dec31_dec_sub18_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec_sub18_dec31_dec_sub18_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec_sub18_dec31_dec_sub18_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub18_dec31_dec_sub18_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub18_dec31_dec_sub18_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 \dec31_dec_sub18_dec31_dec_sub18_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \dec31_dec_sub18_dec31_dec_sub18_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec_sub18_dec31_dec_sub18_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec31_dec_sub18_dec31_dec_sub18_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub18_dec31_dec_sub18_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 \dec31_dec_sub18_dec31_dec_sub18_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub18_dec31_dec_sub18_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub18_dec31_dec_sub18_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub18_dec31_dec_sub18_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec31_dec_sub18_dec31_dec_sub18_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub18_dec31_dec_sub18_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub18_dec31_dec_sub18_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub18_dec31_dec_sub18_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub18_dec31_dec_sub18_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub18_dec31_dec_sub18_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub18_dec31_dec_sub18_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub18_dec31_dec_sub18_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub18_dec31_dec_sub18_upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \dec31_dec_sub18_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 \dec31_dec_sub19_dec31_dec_sub19_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub19_dec31_dec_sub19_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec_sub19_dec31_dec_sub19_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec_sub19_dec31_dec_sub19_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub19_dec31_dec_sub19_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub19_dec31_dec_sub19_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 \dec31_dec_sub19_dec31_dec_sub19_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \dec31_dec_sub19_dec31_dec_sub19_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec_sub19_dec31_dec_sub19_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec31_dec_sub19_dec31_dec_sub19_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub19_dec31_dec_sub19_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 \dec31_dec_sub19_dec31_dec_sub19_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub19_dec31_dec_sub19_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub19_dec31_dec_sub19_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub19_dec31_dec_sub19_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec31_dec_sub19_dec31_dec_sub19_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub19_dec31_dec_sub19_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub19_dec31_dec_sub19_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub19_dec31_dec_sub19_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub19_dec31_dec_sub19_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub19_dec31_dec_sub19_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub19_dec31_dec_sub19_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub19_dec31_dec_sub19_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub19_dec31_dec_sub19_upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \dec31_dec_sub19_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 \dec31_dec_sub20_dec31_dec_sub20_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub20_dec31_dec_sub20_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec_sub20_dec31_dec_sub20_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec_sub20_dec31_dec_sub20_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub20_dec31_dec_sub20_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub20_dec31_dec_sub20_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 \dec31_dec_sub20_dec31_dec_sub20_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \dec31_dec_sub20_dec31_dec_sub20_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec_sub20_dec31_dec_sub20_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec31_dec_sub20_dec31_dec_sub20_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub20_dec31_dec_sub20_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 \dec31_dec_sub20_dec31_dec_sub20_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub20_dec31_dec_sub20_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub20_dec31_dec_sub20_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub20_dec31_dec_sub20_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec31_dec_sub20_dec31_dec_sub20_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub20_dec31_dec_sub20_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub20_dec31_dec_sub20_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub20_dec31_dec_sub20_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub20_dec31_dec_sub20_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub20_dec31_dec_sub20_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub20_dec31_dec_sub20_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub20_dec31_dec_sub20_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub20_dec31_dec_sub20_upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \dec31_dec_sub20_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 \dec31_dec_sub21_dec31_dec_sub21_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub21_dec31_dec_sub21_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec_sub21_dec31_dec_sub21_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec_sub21_dec31_dec_sub21_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub21_dec31_dec_sub21_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub21_dec31_dec_sub21_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 \dec31_dec_sub21_dec31_dec_sub21_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \dec31_dec_sub21_dec31_dec_sub21_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec_sub21_dec31_dec_sub21_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec31_dec_sub21_dec31_dec_sub21_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub21_dec31_dec_sub21_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 \dec31_dec_sub21_dec31_dec_sub21_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub21_dec31_dec_sub21_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub21_dec31_dec_sub21_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub21_dec31_dec_sub21_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec31_dec_sub21_dec31_dec_sub21_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub21_dec31_dec_sub21_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub21_dec31_dec_sub21_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub21_dec31_dec_sub21_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub21_dec31_dec_sub21_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub21_dec31_dec_sub21_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub21_dec31_dec_sub21_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub21_dec31_dec_sub21_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub21_dec31_dec_sub21_upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \dec31_dec_sub21_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 \dec31_dec_sub22_dec31_dec_sub22_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub22_dec31_dec_sub22_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec_sub22_dec31_dec_sub22_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec_sub22_dec31_dec_sub22_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub22_dec31_dec_sub22_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub22_dec31_dec_sub22_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 \dec31_dec_sub22_dec31_dec_sub22_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \dec31_dec_sub22_dec31_dec_sub22_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec_sub22_dec31_dec_sub22_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec31_dec_sub22_dec31_dec_sub22_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub22_dec31_dec_sub22_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 \dec31_dec_sub22_dec31_dec_sub22_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub22_dec31_dec_sub22_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub22_dec31_dec_sub22_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub22_dec31_dec_sub22_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec31_dec_sub22_dec31_dec_sub22_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub22_dec31_dec_sub22_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub22_dec31_dec_sub22_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub22_dec31_dec_sub22_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub22_dec31_dec_sub22_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub22_dec31_dec_sub22_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub22_dec31_dec_sub22_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub22_dec31_dec_sub22_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub22_dec31_dec_sub22_upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \dec31_dec_sub22_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 \dec31_dec_sub23_dec31_dec_sub23_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub23_dec31_dec_sub23_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec_sub23_dec31_dec_sub23_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec_sub23_dec31_dec_sub23_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub23_dec31_dec_sub23_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub23_dec31_dec_sub23_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 \dec31_dec_sub23_dec31_dec_sub23_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \dec31_dec_sub23_dec31_dec_sub23_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec_sub23_dec31_dec_sub23_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec31_dec_sub23_dec31_dec_sub23_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub23_dec31_dec_sub23_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 \dec31_dec_sub23_dec31_dec_sub23_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub23_dec31_dec_sub23_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub23_dec31_dec_sub23_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub23_dec31_dec_sub23_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec31_dec_sub23_dec31_dec_sub23_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub23_dec31_dec_sub23_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub23_dec31_dec_sub23_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub23_dec31_dec_sub23_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub23_dec31_dec_sub23_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub23_dec31_dec_sub23_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub23_dec31_dec_sub23_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub23_dec31_dec_sub23_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub23_dec31_dec_sub23_upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \dec31_dec_sub23_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 \dec31_dec_sub24_dec31_dec_sub24_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub24_dec31_dec_sub24_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec_sub24_dec31_dec_sub24_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec_sub24_dec31_dec_sub24_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub24_dec31_dec_sub24_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub24_dec31_dec_sub24_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 \dec31_dec_sub24_dec31_dec_sub24_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \dec31_dec_sub24_dec31_dec_sub24_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec_sub24_dec31_dec_sub24_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec31_dec_sub24_dec31_dec_sub24_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub24_dec31_dec_sub24_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 \dec31_dec_sub24_dec31_dec_sub24_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub24_dec31_dec_sub24_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub24_dec31_dec_sub24_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub24_dec31_dec_sub24_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec31_dec_sub24_dec31_dec_sub24_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub24_dec31_dec_sub24_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub24_dec31_dec_sub24_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub24_dec31_dec_sub24_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub24_dec31_dec_sub24_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub24_dec31_dec_sub24_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub24_dec31_dec_sub24_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub24_dec31_dec_sub24_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub24_dec31_dec_sub24_upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \dec31_dec_sub24_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 \dec31_dec_sub26_dec31_dec_sub26_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub26_dec31_dec_sub26_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec_sub26_dec31_dec_sub26_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec_sub26_dec31_dec_sub26_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub26_dec31_dec_sub26_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub26_dec31_dec_sub26_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 \dec31_dec_sub26_dec31_dec_sub26_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \dec31_dec_sub26_dec31_dec_sub26_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec_sub26_dec31_dec_sub26_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec31_dec_sub26_dec31_dec_sub26_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub26_dec31_dec_sub26_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 \dec31_dec_sub26_dec31_dec_sub26_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub26_dec31_dec_sub26_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub26_dec31_dec_sub26_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub26_dec31_dec_sub26_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec31_dec_sub26_dec31_dec_sub26_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub26_dec31_dec_sub26_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub26_dec31_dec_sub26_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub26_dec31_dec_sub26_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub26_dec31_dec_sub26_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub26_dec31_dec_sub26_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub26_dec31_dec_sub26_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub26_dec31_dec_sub26_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub26_dec31_dec_sub26_upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \dec31_dec_sub26_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 \dec31_dec_sub27_dec31_dec_sub27_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub27_dec31_dec_sub27_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec_sub27_dec31_dec_sub27_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec_sub27_dec31_dec_sub27_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub27_dec31_dec_sub27_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub27_dec31_dec_sub27_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 \dec31_dec_sub27_dec31_dec_sub27_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \dec31_dec_sub27_dec31_dec_sub27_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec_sub27_dec31_dec_sub27_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec31_dec_sub27_dec31_dec_sub27_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub27_dec31_dec_sub27_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 \dec31_dec_sub27_dec31_dec_sub27_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub27_dec31_dec_sub27_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub27_dec31_dec_sub27_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub27_dec31_dec_sub27_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec31_dec_sub27_dec31_dec_sub27_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub27_dec31_dec_sub27_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub27_dec31_dec_sub27_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub27_dec31_dec_sub27_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub27_dec31_dec_sub27_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub27_dec31_dec_sub27_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub27_dec31_dec_sub27_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub27_dec31_dec_sub27_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub27_dec31_dec_sub27_upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \dec31_dec_sub27_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 \dec31_dec_sub28_dec31_dec_sub28_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub28_dec31_dec_sub28_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec_sub28_dec31_dec_sub28_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec_sub28_dec31_dec_sub28_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub28_dec31_dec_sub28_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub28_dec31_dec_sub28_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 \dec31_dec_sub28_dec31_dec_sub28_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \dec31_dec_sub28_dec31_dec_sub28_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec_sub28_dec31_dec_sub28_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec31_dec_sub28_dec31_dec_sub28_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub28_dec31_dec_sub28_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 \dec31_dec_sub28_dec31_dec_sub28_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub28_dec31_dec_sub28_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub28_dec31_dec_sub28_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub28_dec31_dec_sub28_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec31_dec_sub28_dec31_dec_sub28_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub28_dec31_dec_sub28_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub28_dec31_dec_sub28_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub28_dec31_dec_sub28_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub28_dec31_dec_sub28_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub28_dec31_dec_sub28_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub28_dec31_dec_sub28_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub28_dec31_dec_sub28_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub28_dec31_dec_sub28_upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \dec31_dec_sub28_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 \dec31_dec_sub4_dec31_dec_sub4_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub4_dec31_dec_sub4_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec_sub4_dec31_dec_sub4_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec_sub4_dec31_dec_sub4_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub4_dec31_dec_sub4_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub4_dec31_dec_sub4_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 \dec31_dec_sub4_dec31_dec_sub4_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \dec31_dec_sub4_dec31_dec_sub4_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec_sub4_dec31_dec_sub4_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec31_dec_sub4_dec31_dec_sub4_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub4_dec31_dec_sub4_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 \dec31_dec_sub4_dec31_dec_sub4_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub4_dec31_dec_sub4_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub4_dec31_dec_sub4_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub4_dec31_dec_sub4_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec31_dec_sub4_dec31_dec_sub4_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub4_dec31_dec_sub4_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub4_dec31_dec_sub4_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub4_dec31_dec_sub4_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub4_dec31_dec_sub4_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub4_dec31_dec_sub4_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub4_dec31_dec_sub4_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub4_dec31_dec_sub4_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub4_dec31_dec_sub4_upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \dec31_dec_sub4_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 \dec31_dec_sub8_dec31_dec_sub8_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub8_dec31_dec_sub8_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec_sub8_dec31_dec_sub8_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec_sub8_dec31_dec_sub8_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub8_dec31_dec_sub8_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub8_dec31_dec_sub8_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 \dec31_dec_sub8_dec31_dec_sub8_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \dec31_dec_sub8_dec31_dec_sub8_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec_sub8_dec31_dec_sub8_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec31_dec_sub8_dec31_dec_sub8_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub8_dec31_dec_sub8_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 \dec31_dec_sub8_dec31_dec_sub8_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub8_dec31_dec_sub8_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub8_dec31_dec_sub8_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub8_dec31_dec_sub8_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec31_dec_sub8_dec31_dec_sub8_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub8_dec31_dec_sub8_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub8_dec31_dec_sub8_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub8_dec31_dec_sub8_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub8_dec31_dec_sub8_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub8_dec31_dec_sub8_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub8_dec31_dec_sub8_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub8_dec31_dec_sub8_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub8_dec31_dec_sub8_upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \dec31_dec_sub8_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 \dec31_dec_sub9_dec31_dec_sub9_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub9_dec31_dec_sub9_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec_sub9_dec31_dec_sub9_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec_sub9_dec31_dec_sub9_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub9_dec31_dec_sub9_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub9_dec31_dec_sub9_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 \dec31_dec_sub9_dec31_dec_sub9_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \dec31_dec_sub9_dec31_dec_sub9_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec_sub9_dec31_dec_sub9_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec31_dec_sub9_dec31_dec_sub9_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub9_dec31_dec_sub9_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 \dec31_dec_sub9_dec31_dec_sub9_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub9_dec31_dec_sub9_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub9_dec31_dec_sub9_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub9_dec31_dec_sub9_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec31_dec_sub9_dec31_dec_sub9_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub9_dec31_dec_sub9_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub9_dec31_dec_sub9_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub9_dec31_dec_sub9_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub9_dec31_dec_sub9_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub9_dec31_dec_sub9_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub9_dec31_dec_sub9_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub9_dec31_dec_sub9_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub9_dec31_dec_sub9_upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \dec31_dec_sub9_opcode_in + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 output 3 \dec31_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \dec31_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \dec31_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 6 \dec31_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 7 \dec31_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \dec31_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 15 \dec31_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 16 \dec31_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 21 \dec31_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 11 \dec31_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 23 \dec31_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 8 \dec31_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 13 \dec31_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 20 \dec31_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 24 \dec31_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 22 \dec31_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 19 \dec31_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 12 \dec31_upd + attribute \src "libresoc.v:75989.7-75989.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:326" + wire width 5 \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 10 \opcode_switch + attribute \module_not_derived 1 + attribute \src "libresoc.v:80388.18-80414.4" + cell \dec31_dec_sub0 \dec31_dec_sub0 + connect \dec31_dec_sub0_asmcode \dec31_dec_sub0_dec31_dec_sub0_asmcode + connect \dec31_dec_sub0_br \dec31_dec_sub0_dec31_dec_sub0_br + connect \dec31_dec_sub0_cr_in \dec31_dec_sub0_dec31_dec_sub0_cr_in + connect \dec31_dec_sub0_cr_out \dec31_dec_sub0_dec31_dec_sub0_cr_out + connect \dec31_dec_sub0_cry_in \dec31_dec_sub0_dec31_dec_sub0_cry_in + connect \dec31_dec_sub0_cry_out \dec31_dec_sub0_dec31_dec_sub0_cry_out + connect \dec31_dec_sub0_form \dec31_dec_sub0_dec31_dec_sub0_form + connect \dec31_dec_sub0_function_unit \dec31_dec_sub0_dec31_dec_sub0_function_unit + connect \dec31_dec_sub0_in1_sel \dec31_dec_sub0_dec31_dec_sub0_in1_sel + connect \dec31_dec_sub0_in2_sel \dec31_dec_sub0_dec31_dec_sub0_in2_sel + connect \dec31_dec_sub0_in3_sel \dec31_dec_sub0_dec31_dec_sub0_in3_sel + connect \dec31_dec_sub0_internal_op \dec31_dec_sub0_dec31_dec_sub0_internal_op + connect \dec31_dec_sub0_inv_a \dec31_dec_sub0_dec31_dec_sub0_inv_a + connect \dec31_dec_sub0_inv_out \dec31_dec_sub0_dec31_dec_sub0_inv_out + connect \dec31_dec_sub0_is_32b \dec31_dec_sub0_dec31_dec_sub0_is_32b + connect \dec31_dec_sub0_ldst_len \dec31_dec_sub0_dec31_dec_sub0_ldst_len + connect \dec31_dec_sub0_lk \dec31_dec_sub0_dec31_dec_sub0_lk + connect \dec31_dec_sub0_out_sel \dec31_dec_sub0_dec31_dec_sub0_out_sel + connect \dec31_dec_sub0_rc_sel \dec31_dec_sub0_dec31_dec_sub0_rc_sel + connect \dec31_dec_sub0_rsrv \dec31_dec_sub0_dec31_dec_sub0_rsrv + connect \dec31_dec_sub0_sgl_pipe \dec31_dec_sub0_dec31_dec_sub0_sgl_pipe + connect \dec31_dec_sub0_sgn \dec31_dec_sub0_dec31_dec_sub0_sgn + connect \dec31_dec_sub0_sgn_ext \dec31_dec_sub0_dec31_dec_sub0_sgn_ext + connect \dec31_dec_sub0_upd \dec31_dec_sub0_dec31_dec_sub0_upd + connect \opcode_in \dec31_dec_sub0_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:80415.19-80441.4" + cell \dec31_dec_sub10 \dec31_dec_sub10 + connect \dec31_dec_sub10_asmcode \dec31_dec_sub10_dec31_dec_sub10_asmcode + connect \dec31_dec_sub10_br \dec31_dec_sub10_dec31_dec_sub10_br + connect \dec31_dec_sub10_cr_in \dec31_dec_sub10_dec31_dec_sub10_cr_in + connect \dec31_dec_sub10_cr_out \dec31_dec_sub10_dec31_dec_sub10_cr_out + connect \dec31_dec_sub10_cry_in \dec31_dec_sub10_dec31_dec_sub10_cry_in + connect \dec31_dec_sub10_cry_out \dec31_dec_sub10_dec31_dec_sub10_cry_out + connect \dec31_dec_sub10_form \dec31_dec_sub10_dec31_dec_sub10_form + connect \dec31_dec_sub10_function_unit \dec31_dec_sub10_dec31_dec_sub10_function_unit + connect \dec31_dec_sub10_in1_sel \dec31_dec_sub10_dec31_dec_sub10_in1_sel + connect \dec31_dec_sub10_in2_sel \dec31_dec_sub10_dec31_dec_sub10_in2_sel + connect \dec31_dec_sub10_in3_sel \dec31_dec_sub10_dec31_dec_sub10_in3_sel + connect \dec31_dec_sub10_internal_op \dec31_dec_sub10_dec31_dec_sub10_internal_op + connect \dec31_dec_sub10_inv_a \dec31_dec_sub10_dec31_dec_sub10_inv_a + connect \dec31_dec_sub10_inv_out \dec31_dec_sub10_dec31_dec_sub10_inv_out + connect \dec31_dec_sub10_is_32b \dec31_dec_sub10_dec31_dec_sub10_is_32b + connect \dec31_dec_sub10_ldst_len \dec31_dec_sub10_dec31_dec_sub10_ldst_len + connect \dec31_dec_sub10_lk \dec31_dec_sub10_dec31_dec_sub10_lk + connect \dec31_dec_sub10_out_sel \dec31_dec_sub10_dec31_dec_sub10_out_sel + connect \dec31_dec_sub10_rc_sel \dec31_dec_sub10_dec31_dec_sub10_rc_sel + connect \dec31_dec_sub10_rsrv \dec31_dec_sub10_dec31_dec_sub10_rsrv + connect \dec31_dec_sub10_sgl_pipe \dec31_dec_sub10_dec31_dec_sub10_sgl_pipe + connect \dec31_dec_sub10_sgn \dec31_dec_sub10_dec31_dec_sub10_sgn + connect \dec31_dec_sub10_sgn_ext \dec31_dec_sub10_dec31_dec_sub10_sgn_ext + connect \dec31_dec_sub10_upd \dec31_dec_sub10_dec31_dec_sub10_upd + connect \opcode_in \dec31_dec_sub10_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:80442.19-80468.4" + cell \dec31_dec_sub11 \dec31_dec_sub11 + connect \dec31_dec_sub11_asmcode \dec31_dec_sub11_dec31_dec_sub11_asmcode + connect \dec31_dec_sub11_br \dec31_dec_sub11_dec31_dec_sub11_br + connect \dec31_dec_sub11_cr_in \dec31_dec_sub11_dec31_dec_sub11_cr_in + connect \dec31_dec_sub11_cr_out \dec31_dec_sub11_dec31_dec_sub11_cr_out + connect \dec31_dec_sub11_cry_in \dec31_dec_sub11_dec31_dec_sub11_cry_in + connect \dec31_dec_sub11_cry_out \dec31_dec_sub11_dec31_dec_sub11_cry_out + connect \dec31_dec_sub11_form \dec31_dec_sub11_dec31_dec_sub11_form + connect \dec31_dec_sub11_function_unit \dec31_dec_sub11_dec31_dec_sub11_function_unit + connect \dec31_dec_sub11_in1_sel \dec31_dec_sub11_dec31_dec_sub11_in1_sel + connect \dec31_dec_sub11_in2_sel \dec31_dec_sub11_dec31_dec_sub11_in2_sel + connect \dec31_dec_sub11_in3_sel \dec31_dec_sub11_dec31_dec_sub11_in3_sel + connect \dec31_dec_sub11_internal_op \dec31_dec_sub11_dec31_dec_sub11_internal_op + connect \dec31_dec_sub11_inv_a \dec31_dec_sub11_dec31_dec_sub11_inv_a + connect \dec31_dec_sub11_inv_out \dec31_dec_sub11_dec31_dec_sub11_inv_out + connect \dec31_dec_sub11_is_32b \dec31_dec_sub11_dec31_dec_sub11_is_32b + connect \dec31_dec_sub11_ldst_len \dec31_dec_sub11_dec31_dec_sub11_ldst_len + connect \dec31_dec_sub11_lk \dec31_dec_sub11_dec31_dec_sub11_lk + connect \dec31_dec_sub11_out_sel \dec31_dec_sub11_dec31_dec_sub11_out_sel + connect \dec31_dec_sub11_rc_sel \dec31_dec_sub11_dec31_dec_sub11_rc_sel + connect \dec31_dec_sub11_rsrv \dec31_dec_sub11_dec31_dec_sub11_rsrv + connect \dec31_dec_sub11_sgl_pipe \dec31_dec_sub11_dec31_dec_sub11_sgl_pipe + connect \dec31_dec_sub11_sgn \dec31_dec_sub11_dec31_dec_sub11_sgn + connect \dec31_dec_sub11_sgn_ext \dec31_dec_sub11_dec31_dec_sub11_sgn_ext + connect \dec31_dec_sub11_upd \dec31_dec_sub11_dec31_dec_sub11_upd + connect \opcode_in \dec31_dec_sub11_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:80469.19-80495.4" + cell \dec31_dec_sub15 \dec31_dec_sub15 + connect \dec31_dec_sub15_asmcode \dec31_dec_sub15_dec31_dec_sub15_asmcode + connect \dec31_dec_sub15_br \dec31_dec_sub15_dec31_dec_sub15_br + connect \dec31_dec_sub15_cr_in \dec31_dec_sub15_dec31_dec_sub15_cr_in + connect \dec31_dec_sub15_cr_out \dec31_dec_sub15_dec31_dec_sub15_cr_out + connect \dec31_dec_sub15_cry_in \dec31_dec_sub15_dec31_dec_sub15_cry_in + connect \dec31_dec_sub15_cry_out \dec31_dec_sub15_dec31_dec_sub15_cry_out + connect \dec31_dec_sub15_form \dec31_dec_sub15_dec31_dec_sub15_form + connect \dec31_dec_sub15_function_unit \dec31_dec_sub15_dec31_dec_sub15_function_unit + connect \dec31_dec_sub15_in1_sel \dec31_dec_sub15_dec31_dec_sub15_in1_sel + connect \dec31_dec_sub15_in2_sel \dec31_dec_sub15_dec31_dec_sub15_in2_sel + connect \dec31_dec_sub15_in3_sel \dec31_dec_sub15_dec31_dec_sub15_in3_sel + connect \dec31_dec_sub15_internal_op \dec31_dec_sub15_dec31_dec_sub15_internal_op + connect \dec31_dec_sub15_inv_a \dec31_dec_sub15_dec31_dec_sub15_inv_a + connect \dec31_dec_sub15_inv_out \dec31_dec_sub15_dec31_dec_sub15_inv_out + connect \dec31_dec_sub15_is_32b \dec31_dec_sub15_dec31_dec_sub15_is_32b + connect \dec31_dec_sub15_ldst_len \dec31_dec_sub15_dec31_dec_sub15_ldst_len + connect \dec31_dec_sub15_lk \dec31_dec_sub15_dec31_dec_sub15_lk + connect \dec31_dec_sub15_out_sel \dec31_dec_sub15_dec31_dec_sub15_out_sel + connect \dec31_dec_sub15_rc_sel \dec31_dec_sub15_dec31_dec_sub15_rc_sel + connect \dec31_dec_sub15_rsrv \dec31_dec_sub15_dec31_dec_sub15_rsrv + connect \dec31_dec_sub15_sgl_pipe \dec31_dec_sub15_dec31_dec_sub15_sgl_pipe + connect \dec31_dec_sub15_sgn \dec31_dec_sub15_dec31_dec_sub15_sgn + connect \dec31_dec_sub15_sgn_ext \dec31_dec_sub15_dec31_dec_sub15_sgn_ext + connect \dec31_dec_sub15_upd \dec31_dec_sub15_dec31_dec_sub15_upd + connect \opcode_in \dec31_dec_sub15_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:80496.19-80522.4" + cell \dec31_dec_sub16 \dec31_dec_sub16 + connect \dec31_dec_sub16_asmcode \dec31_dec_sub16_dec31_dec_sub16_asmcode + connect \dec31_dec_sub16_br \dec31_dec_sub16_dec31_dec_sub16_br + connect \dec31_dec_sub16_cr_in \dec31_dec_sub16_dec31_dec_sub16_cr_in + connect \dec31_dec_sub16_cr_out \dec31_dec_sub16_dec31_dec_sub16_cr_out + connect \dec31_dec_sub16_cry_in \dec31_dec_sub16_dec31_dec_sub16_cry_in + connect \dec31_dec_sub16_cry_out \dec31_dec_sub16_dec31_dec_sub16_cry_out + connect \dec31_dec_sub16_form \dec31_dec_sub16_dec31_dec_sub16_form + connect \dec31_dec_sub16_function_unit \dec31_dec_sub16_dec31_dec_sub16_function_unit + connect \dec31_dec_sub16_in1_sel \dec31_dec_sub16_dec31_dec_sub16_in1_sel + connect \dec31_dec_sub16_in2_sel \dec31_dec_sub16_dec31_dec_sub16_in2_sel + connect \dec31_dec_sub16_in3_sel \dec31_dec_sub16_dec31_dec_sub16_in3_sel + connect \dec31_dec_sub16_internal_op \dec31_dec_sub16_dec31_dec_sub16_internal_op + connect \dec31_dec_sub16_inv_a \dec31_dec_sub16_dec31_dec_sub16_inv_a + connect \dec31_dec_sub16_inv_out \dec31_dec_sub16_dec31_dec_sub16_inv_out + connect \dec31_dec_sub16_is_32b \dec31_dec_sub16_dec31_dec_sub16_is_32b + connect \dec31_dec_sub16_ldst_len \dec31_dec_sub16_dec31_dec_sub16_ldst_len + connect \dec31_dec_sub16_lk \dec31_dec_sub16_dec31_dec_sub16_lk + connect \dec31_dec_sub16_out_sel \dec31_dec_sub16_dec31_dec_sub16_out_sel + connect \dec31_dec_sub16_rc_sel \dec31_dec_sub16_dec31_dec_sub16_rc_sel + connect \dec31_dec_sub16_rsrv \dec31_dec_sub16_dec31_dec_sub16_rsrv + connect \dec31_dec_sub16_sgl_pipe \dec31_dec_sub16_dec31_dec_sub16_sgl_pipe + connect \dec31_dec_sub16_sgn \dec31_dec_sub16_dec31_dec_sub16_sgn + connect \dec31_dec_sub16_sgn_ext \dec31_dec_sub16_dec31_dec_sub16_sgn_ext + connect \dec31_dec_sub16_upd \dec31_dec_sub16_dec31_dec_sub16_upd + connect \opcode_in \dec31_dec_sub16_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:80523.19-80549.4" + cell \dec31_dec_sub18 \dec31_dec_sub18 + connect \dec31_dec_sub18_asmcode \dec31_dec_sub18_dec31_dec_sub18_asmcode + connect \dec31_dec_sub18_br \dec31_dec_sub18_dec31_dec_sub18_br + connect \dec31_dec_sub18_cr_in \dec31_dec_sub18_dec31_dec_sub18_cr_in + connect \dec31_dec_sub18_cr_out \dec31_dec_sub18_dec31_dec_sub18_cr_out + connect \dec31_dec_sub18_cry_in \dec31_dec_sub18_dec31_dec_sub18_cry_in + connect \dec31_dec_sub18_cry_out \dec31_dec_sub18_dec31_dec_sub18_cry_out + connect \dec31_dec_sub18_form \dec31_dec_sub18_dec31_dec_sub18_form + connect \dec31_dec_sub18_function_unit \dec31_dec_sub18_dec31_dec_sub18_function_unit + connect \dec31_dec_sub18_in1_sel \dec31_dec_sub18_dec31_dec_sub18_in1_sel + connect \dec31_dec_sub18_in2_sel \dec31_dec_sub18_dec31_dec_sub18_in2_sel + connect \dec31_dec_sub18_in3_sel \dec31_dec_sub18_dec31_dec_sub18_in3_sel + connect \dec31_dec_sub18_internal_op \dec31_dec_sub18_dec31_dec_sub18_internal_op + connect \dec31_dec_sub18_inv_a \dec31_dec_sub18_dec31_dec_sub18_inv_a + connect \dec31_dec_sub18_inv_out \dec31_dec_sub18_dec31_dec_sub18_inv_out + connect \dec31_dec_sub18_is_32b \dec31_dec_sub18_dec31_dec_sub18_is_32b + connect \dec31_dec_sub18_ldst_len \dec31_dec_sub18_dec31_dec_sub18_ldst_len + connect \dec31_dec_sub18_lk \dec31_dec_sub18_dec31_dec_sub18_lk + connect \dec31_dec_sub18_out_sel \dec31_dec_sub18_dec31_dec_sub18_out_sel + connect \dec31_dec_sub18_rc_sel \dec31_dec_sub18_dec31_dec_sub18_rc_sel + connect \dec31_dec_sub18_rsrv \dec31_dec_sub18_dec31_dec_sub18_rsrv + connect \dec31_dec_sub18_sgl_pipe \dec31_dec_sub18_dec31_dec_sub18_sgl_pipe + connect \dec31_dec_sub18_sgn \dec31_dec_sub18_dec31_dec_sub18_sgn + connect \dec31_dec_sub18_sgn_ext \dec31_dec_sub18_dec31_dec_sub18_sgn_ext + connect \dec31_dec_sub18_upd \dec31_dec_sub18_dec31_dec_sub18_upd + connect \opcode_in \dec31_dec_sub18_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:80550.19-80576.4" + cell \dec31_dec_sub19 \dec31_dec_sub19 + connect \dec31_dec_sub19_asmcode \dec31_dec_sub19_dec31_dec_sub19_asmcode + connect \dec31_dec_sub19_br \dec31_dec_sub19_dec31_dec_sub19_br + connect \dec31_dec_sub19_cr_in \dec31_dec_sub19_dec31_dec_sub19_cr_in + connect \dec31_dec_sub19_cr_out \dec31_dec_sub19_dec31_dec_sub19_cr_out + connect \dec31_dec_sub19_cry_in \dec31_dec_sub19_dec31_dec_sub19_cry_in + connect \dec31_dec_sub19_cry_out \dec31_dec_sub19_dec31_dec_sub19_cry_out + connect \dec31_dec_sub19_form \dec31_dec_sub19_dec31_dec_sub19_form + connect \dec31_dec_sub19_function_unit \dec31_dec_sub19_dec31_dec_sub19_function_unit + connect \dec31_dec_sub19_in1_sel \dec31_dec_sub19_dec31_dec_sub19_in1_sel + connect \dec31_dec_sub19_in2_sel \dec31_dec_sub19_dec31_dec_sub19_in2_sel + connect \dec31_dec_sub19_in3_sel \dec31_dec_sub19_dec31_dec_sub19_in3_sel + connect \dec31_dec_sub19_internal_op \dec31_dec_sub19_dec31_dec_sub19_internal_op + connect \dec31_dec_sub19_inv_a \dec31_dec_sub19_dec31_dec_sub19_inv_a + connect \dec31_dec_sub19_inv_out \dec31_dec_sub19_dec31_dec_sub19_inv_out + connect \dec31_dec_sub19_is_32b \dec31_dec_sub19_dec31_dec_sub19_is_32b + connect \dec31_dec_sub19_ldst_len \dec31_dec_sub19_dec31_dec_sub19_ldst_len + connect \dec31_dec_sub19_lk \dec31_dec_sub19_dec31_dec_sub19_lk + connect \dec31_dec_sub19_out_sel \dec31_dec_sub19_dec31_dec_sub19_out_sel + connect \dec31_dec_sub19_rc_sel \dec31_dec_sub19_dec31_dec_sub19_rc_sel + connect \dec31_dec_sub19_rsrv \dec31_dec_sub19_dec31_dec_sub19_rsrv + connect \dec31_dec_sub19_sgl_pipe \dec31_dec_sub19_dec31_dec_sub19_sgl_pipe + connect \dec31_dec_sub19_sgn \dec31_dec_sub19_dec31_dec_sub19_sgn + connect \dec31_dec_sub19_sgn_ext \dec31_dec_sub19_dec31_dec_sub19_sgn_ext + connect \dec31_dec_sub19_upd \dec31_dec_sub19_dec31_dec_sub19_upd + connect \opcode_in \dec31_dec_sub19_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:80577.19-80603.4" + cell \dec31_dec_sub20 \dec31_dec_sub20 + connect \dec31_dec_sub20_asmcode \dec31_dec_sub20_dec31_dec_sub20_asmcode + connect \dec31_dec_sub20_br \dec31_dec_sub20_dec31_dec_sub20_br + connect \dec31_dec_sub20_cr_in \dec31_dec_sub20_dec31_dec_sub20_cr_in + connect \dec31_dec_sub20_cr_out \dec31_dec_sub20_dec31_dec_sub20_cr_out + connect \dec31_dec_sub20_cry_in \dec31_dec_sub20_dec31_dec_sub20_cry_in + connect \dec31_dec_sub20_cry_out \dec31_dec_sub20_dec31_dec_sub20_cry_out + connect \dec31_dec_sub20_form \dec31_dec_sub20_dec31_dec_sub20_form + connect \dec31_dec_sub20_function_unit \dec31_dec_sub20_dec31_dec_sub20_function_unit + connect \dec31_dec_sub20_in1_sel \dec31_dec_sub20_dec31_dec_sub20_in1_sel + connect \dec31_dec_sub20_in2_sel \dec31_dec_sub20_dec31_dec_sub20_in2_sel + connect \dec31_dec_sub20_in3_sel \dec31_dec_sub20_dec31_dec_sub20_in3_sel + connect \dec31_dec_sub20_internal_op \dec31_dec_sub20_dec31_dec_sub20_internal_op + connect \dec31_dec_sub20_inv_a \dec31_dec_sub20_dec31_dec_sub20_inv_a + connect \dec31_dec_sub20_inv_out \dec31_dec_sub20_dec31_dec_sub20_inv_out + connect \dec31_dec_sub20_is_32b \dec31_dec_sub20_dec31_dec_sub20_is_32b + connect \dec31_dec_sub20_ldst_len \dec31_dec_sub20_dec31_dec_sub20_ldst_len + connect \dec31_dec_sub20_lk \dec31_dec_sub20_dec31_dec_sub20_lk + connect \dec31_dec_sub20_out_sel \dec31_dec_sub20_dec31_dec_sub20_out_sel + connect \dec31_dec_sub20_rc_sel \dec31_dec_sub20_dec31_dec_sub20_rc_sel + connect \dec31_dec_sub20_rsrv \dec31_dec_sub20_dec31_dec_sub20_rsrv + connect \dec31_dec_sub20_sgl_pipe \dec31_dec_sub20_dec31_dec_sub20_sgl_pipe + connect \dec31_dec_sub20_sgn \dec31_dec_sub20_dec31_dec_sub20_sgn + connect \dec31_dec_sub20_sgn_ext \dec31_dec_sub20_dec31_dec_sub20_sgn_ext + connect \dec31_dec_sub20_upd \dec31_dec_sub20_dec31_dec_sub20_upd + connect \opcode_in \dec31_dec_sub20_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:80604.19-80630.4" + cell \dec31_dec_sub21 \dec31_dec_sub21 + connect \dec31_dec_sub21_asmcode \dec31_dec_sub21_dec31_dec_sub21_asmcode + connect \dec31_dec_sub21_br \dec31_dec_sub21_dec31_dec_sub21_br + connect \dec31_dec_sub21_cr_in \dec31_dec_sub21_dec31_dec_sub21_cr_in + connect \dec31_dec_sub21_cr_out \dec31_dec_sub21_dec31_dec_sub21_cr_out + connect \dec31_dec_sub21_cry_in \dec31_dec_sub21_dec31_dec_sub21_cry_in + connect \dec31_dec_sub21_cry_out \dec31_dec_sub21_dec31_dec_sub21_cry_out + connect \dec31_dec_sub21_form \dec31_dec_sub21_dec31_dec_sub21_form + connect \dec31_dec_sub21_function_unit \dec31_dec_sub21_dec31_dec_sub21_function_unit + connect \dec31_dec_sub21_in1_sel \dec31_dec_sub21_dec31_dec_sub21_in1_sel + connect \dec31_dec_sub21_in2_sel \dec31_dec_sub21_dec31_dec_sub21_in2_sel + connect \dec31_dec_sub21_in3_sel \dec31_dec_sub21_dec31_dec_sub21_in3_sel + connect \dec31_dec_sub21_internal_op \dec31_dec_sub21_dec31_dec_sub21_internal_op + connect \dec31_dec_sub21_inv_a \dec31_dec_sub21_dec31_dec_sub21_inv_a + connect \dec31_dec_sub21_inv_out \dec31_dec_sub21_dec31_dec_sub21_inv_out + connect \dec31_dec_sub21_is_32b \dec31_dec_sub21_dec31_dec_sub21_is_32b + connect \dec31_dec_sub21_ldst_len \dec31_dec_sub21_dec31_dec_sub21_ldst_len + connect \dec31_dec_sub21_lk \dec31_dec_sub21_dec31_dec_sub21_lk + connect \dec31_dec_sub21_out_sel \dec31_dec_sub21_dec31_dec_sub21_out_sel + connect \dec31_dec_sub21_rc_sel \dec31_dec_sub21_dec31_dec_sub21_rc_sel + connect \dec31_dec_sub21_rsrv \dec31_dec_sub21_dec31_dec_sub21_rsrv + connect \dec31_dec_sub21_sgl_pipe \dec31_dec_sub21_dec31_dec_sub21_sgl_pipe + connect \dec31_dec_sub21_sgn \dec31_dec_sub21_dec31_dec_sub21_sgn + connect \dec31_dec_sub21_sgn_ext \dec31_dec_sub21_dec31_dec_sub21_sgn_ext + connect \dec31_dec_sub21_upd \dec31_dec_sub21_dec31_dec_sub21_upd + connect \opcode_in \dec31_dec_sub21_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:80631.19-80657.4" + cell \dec31_dec_sub22 \dec31_dec_sub22 + connect \dec31_dec_sub22_asmcode \dec31_dec_sub22_dec31_dec_sub22_asmcode + connect \dec31_dec_sub22_br \dec31_dec_sub22_dec31_dec_sub22_br + connect \dec31_dec_sub22_cr_in \dec31_dec_sub22_dec31_dec_sub22_cr_in + connect \dec31_dec_sub22_cr_out \dec31_dec_sub22_dec31_dec_sub22_cr_out + connect \dec31_dec_sub22_cry_in \dec31_dec_sub22_dec31_dec_sub22_cry_in + connect \dec31_dec_sub22_cry_out \dec31_dec_sub22_dec31_dec_sub22_cry_out + connect \dec31_dec_sub22_form \dec31_dec_sub22_dec31_dec_sub22_form + connect \dec31_dec_sub22_function_unit \dec31_dec_sub22_dec31_dec_sub22_function_unit + connect \dec31_dec_sub22_in1_sel \dec31_dec_sub22_dec31_dec_sub22_in1_sel + connect \dec31_dec_sub22_in2_sel \dec31_dec_sub22_dec31_dec_sub22_in2_sel + connect \dec31_dec_sub22_in3_sel \dec31_dec_sub22_dec31_dec_sub22_in3_sel + connect \dec31_dec_sub22_internal_op \dec31_dec_sub22_dec31_dec_sub22_internal_op + connect \dec31_dec_sub22_inv_a \dec31_dec_sub22_dec31_dec_sub22_inv_a + connect \dec31_dec_sub22_inv_out \dec31_dec_sub22_dec31_dec_sub22_inv_out + connect \dec31_dec_sub22_is_32b \dec31_dec_sub22_dec31_dec_sub22_is_32b + connect \dec31_dec_sub22_ldst_len \dec31_dec_sub22_dec31_dec_sub22_ldst_len + connect \dec31_dec_sub22_lk \dec31_dec_sub22_dec31_dec_sub22_lk + connect \dec31_dec_sub22_out_sel \dec31_dec_sub22_dec31_dec_sub22_out_sel + connect \dec31_dec_sub22_rc_sel \dec31_dec_sub22_dec31_dec_sub22_rc_sel + connect \dec31_dec_sub22_rsrv \dec31_dec_sub22_dec31_dec_sub22_rsrv + connect \dec31_dec_sub22_sgl_pipe \dec31_dec_sub22_dec31_dec_sub22_sgl_pipe + connect \dec31_dec_sub22_sgn \dec31_dec_sub22_dec31_dec_sub22_sgn + connect \dec31_dec_sub22_sgn_ext \dec31_dec_sub22_dec31_dec_sub22_sgn_ext + connect \dec31_dec_sub22_upd \dec31_dec_sub22_dec31_dec_sub22_upd + connect \opcode_in \dec31_dec_sub22_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:80658.19-80684.4" + cell \dec31_dec_sub23 \dec31_dec_sub23 + connect \dec31_dec_sub23_asmcode \dec31_dec_sub23_dec31_dec_sub23_asmcode + connect \dec31_dec_sub23_br \dec31_dec_sub23_dec31_dec_sub23_br + connect \dec31_dec_sub23_cr_in \dec31_dec_sub23_dec31_dec_sub23_cr_in + connect \dec31_dec_sub23_cr_out \dec31_dec_sub23_dec31_dec_sub23_cr_out + connect \dec31_dec_sub23_cry_in \dec31_dec_sub23_dec31_dec_sub23_cry_in + connect \dec31_dec_sub23_cry_out \dec31_dec_sub23_dec31_dec_sub23_cry_out + connect \dec31_dec_sub23_form \dec31_dec_sub23_dec31_dec_sub23_form + connect \dec31_dec_sub23_function_unit \dec31_dec_sub23_dec31_dec_sub23_function_unit + connect \dec31_dec_sub23_in1_sel \dec31_dec_sub23_dec31_dec_sub23_in1_sel + connect \dec31_dec_sub23_in2_sel \dec31_dec_sub23_dec31_dec_sub23_in2_sel + connect \dec31_dec_sub23_in3_sel \dec31_dec_sub23_dec31_dec_sub23_in3_sel + connect \dec31_dec_sub23_internal_op \dec31_dec_sub23_dec31_dec_sub23_internal_op + connect \dec31_dec_sub23_inv_a \dec31_dec_sub23_dec31_dec_sub23_inv_a + connect \dec31_dec_sub23_inv_out \dec31_dec_sub23_dec31_dec_sub23_inv_out + connect \dec31_dec_sub23_is_32b \dec31_dec_sub23_dec31_dec_sub23_is_32b + connect \dec31_dec_sub23_ldst_len \dec31_dec_sub23_dec31_dec_sub23_ldst_len + connect \dec31_dec_sub23_lk \dec31_dec_sub23_dec31_dec_sub23_lk + connect \dec31_dec_sub23_out_sel \dec31_dec_sub23_dec31_dec_sub23_out_sel + connect \dec31_dec_sub23_rc_sel \dec31_dec_sub23_dec31_dec_sub23_rc_sel + connect \dec31_dec_sub23_rsrv \dec31_dec_sub23_dec31_dec_sub23_rsrv + connect \dec31_dec_sub23_sgl_pipe \dec31_dec_sub23_dec31_dec_sub23_sgl_pipe + connect \dec31_dec_sub23_sgn \dec31_dec_sub23_dec31_dec_sub23_sgn + connect \dec31_dec_sub23_sgn_ext \dec31_dec_sub23_dec31_dec_sub23_sgn_ext + connect \dec31_dec_sub23_upd \dec31_dec_sub23_dec31_dec_sub23_upd + connect \opcode_in \dec31_dec_sub23_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:80685.19-80711.4" + cell \dec31_dec_sub24 \dec31_dec_sub24 + connect \dec31_dec_sub24_asmcode \dec31_dec_sub24_dec31_dec_sub24_asmcode + connect \dec31_dec_sub24_br \dec31_dec_sub24_dec31_dec_sub24_br + connect \dec31_dec_sub24_cr_in \dec31_dec_sub24_dec31_dec_sub24_cr_in + connect \dec31_dec_sub24_cr_out \dec31_dec_sub24_dec31_dec_sub24_cr_out + connect \dec31_dec_sub24_cry_in \dec31_dec_sub24_dec31_dec_sub24_cry_in + connect \dec31_dec_sub24_cry_out \dec31_dec_sub24_dec31_dec_sub24_cry_out + connect \dec31_dec_sub24_form \dec31_dec_sub24_dec31_dec_sub24_form + connect \dec31_dec_sub24_function_unit \dec31_dec_sub24_dec31_dec_sub24_function_unit + connect \dec31_dec_sub24_in1_sel \dec31_dec_sub24_dec31_dec_sub24_in1_sel + connect \dec31_dec_sub24_in2_sel \dec31_dec_sub24_dec31_dec_sub24_in2_sel + connect \dec31_dec_sub24_in3_sel \dec31_dec_sub24_dec31_dec_sub24_in3_sel + connect \dec31_dec_sub24_internal_op \dec31_dec_sub24_dec31_dec_sub24_internal_op + connect \dec31_dec_sub24_inv_a \dec31_dec_sub24_dec31_dec_sub24_inv_a + connect \dec31_dec_sub24_inv_out \dec31_dec_sub24_dec31_dec_sub24_inv_out + connect \dec31_dec_sub24_is_32b \dec31_dec_sub24_dec31_dec_sub24_is_32b + connect \dec31_dec_sub24_ldst_len \dec31_dec_sub24_dec31_dec_sub24_ldst_len + connect \dec31_dec_sub24_lk \dec31_dec_sub24_dec31_dec_sub24_lk + connect \dec31_dec_sub24_out_sel \dec31_dec_sub24_dec31_dec_sub24_out_sel + connect \dec31_dec_sub24_rc_sel \dec31_dec_sub24_dec31_dec_sub24_rc_sel + connect \dec31_dec_sub24_rsrv \dec31_dec_sub24_dec31_dec_sub24_rsrv + connect \dec31_dec_sub24_sgl_pipe \dec31_dec_sub24_dec31_dec_sub24_sgl_pipe + connect \dec31_dec_sub24_sgn \dec31_dec_sub24_dec31_dec_sub24_sgn + connect \dec31_dec_sub24_sgn_ext \dec31_dec_sub24_dec31_dec_sub24_sgn_ext + connect \dec31_dec_sub24_upd \dec31_dec_sub24_dec31_dec_sub24_upd + connect \opcode_in \dec31_dec_sub24_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:80712.19-80738.4" + cell \dec31_dec_sub26 \dec31_dec_sub26 + connect \dec31_dec_sub26_asmcode \dec31_dec_sub26_dec31_dec_sub26_asmcode + connect \dec31_dec_sub26_br \dec31_dec_sub26_dec31_dec_sub26_br + connect \dec31_dec_sub26_cr_in \dec31_dec_sub26_dec31_dec_sub26_cr_in + connect \dec31_dec_sub26_cr_out \dec31_dec_sub26_dec31_dec_sub26_cr_out + connect \dec31_dec_sub26_cry_in \dec31_dec_sub26_dec31_dec_sub26_cry_in + connect \dec31_dec_sub26_cry_out \dec31_dec_sub26_dec31_dec_sub26_cry_out + connect \dec31_dec_sub26_form \dec31_dec_sub26_dec31_dec_sub26_form + connect \dec31_dec_sub26_function_unit \dec31_dec_sub26_dec31_dec_sub26_function_unit + connect \dec31_dec_sub26_in1_sel \dec31_dec_sub26_dec31_dec_sub26_in1_sel + connect \dec31_dec_sub26_in2_sel \dec31_dec_sub26_dec31_dec_sub26_in2_sel + connect \dec31_dec_sub26_in3_sel \dec31_dec_sub26_dec31_dec_sub26_in3_sel + connect \dec31_dec_sub26_internal_op \dec31_dec_sub26_dec31_dec_sub26_internal_op + connect \dec31_dec_sub26_inv_a \dec31_dec_sub26_dec31_dec_sub26_inv_a + connect \dec31_dec_sub26_inv_out \dec31_dec_sub26_dec31_dec_sub26_inv_out + connect \dec31_dec_sub26_is_32b \dec31_dec_sub26_dec31_dec_sub26_is_32b + connect \dec31_dec_sub26_ldst_len \dec31_dec_sub26_dec31_dec_sub26_ldst_len + connect \dec31_dec_sub26_lk \dec31_dec_sub26_dec31_dec_sub26_lk + connect \dec31_dec_sub26_out_sel \dec31_dec_sub26_dec31_dec_sub26_out_sel + connect \dec31_dec_sub26_rc_sel \dec31_dec_sub26_dec31_dec_sub26_rc_sel + connect \dec31_dec_sub26_rsrv \dec31_dec_sub26_dec31_dec_sub26_rsrv + connect \dec31_dec_sub26_sgl_pipe \dec31_dec_sub26_dec31_dec_sub26_sgl_pipe + connect \dec31_dec_sub26_sgn \dec31_dec_sub26_dec31_dec_sub26_sgn + connect \dec31_dec_sub26_sgn_ext \dec31_dec_sub26_dec31_dec_sub26_sgn_ext + connect \dec31_dec_sub26_upd \dec31_dec_sub26_dec31_dec_sub26_upd + connect \opcode_in \dec31_dec_sub26_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:80739.19-80765.4" + cell \dec31_dec_sub27 \dec31_dec_sub27 + connect \dec31_dec_sub27_asmcode \dec31_dec_sub27_dec31_dec_sub27_asmcode + connect \dec31_dec_sub27_br \dec31_dec_sub27_dec31_dec_sub27_br + connect \dec31_dec_sub27_cr_in \dec31_dec_sub27_dec31_dec_sub27_cr_in + connect \dec31_dec_sub27_cr_out \dec31_dec_sub27_dec31_dec_sub27_cr_out + connect \dec31_dec_sub27_cry_in \dec31_dec_sub27_dec31_dec_sub27_cry_in + connect \dec31_dec_sub27_cry_out \dec31_dec_sub27_dec31_dec_sub27_cry_out + connect \dec31_dec_sub27_form \dec31_dec_sub27_dec31_dec_sub27_form + connect \dec31_dec_sub27_function_unit \dec31_dec_sub27_dec31_dec_sub27_function_unit + connect \dec31_dec_sub27_in1_sel \dec31_dec_sub27_dec31_dec_sub27_in1_sel + connect \dec31_dec_sub27_in2_sel \dec31_dec_sub27_dec31_dec_sub27_in2_sel + connect \dec31_dec_sub27_in3_sel \dec31_dec_sub27_dec31_dec_sub27_in3_sel + connect \dec31_dec_sub27_internal_op \dec31_dec_sub27_dec31_dec_sub27_internal_op + connect \dec31_dec_sub27_inv_a \dec31_dec_sub27_dec31_dec_sub27_inv_a + connect \dec31_dec_sub27_inv_out \dec31_dec_sub27_dec31_dec_sub27_inv_out + connect \dec31_dec_sub27_is_32b \dec31_dec_sub27_dec31_dec_sub27_is_32b + connect \dec31_dec_sub27_ldst_len \dec31_dec_sub27_dec31_dec_sub27_ldst_len + connect \dec31_dec_sub27_lk \dec31_dec_sub27_dec31_dec_sub27_lk + connect \dec31_dec_sub27_out_sel \dec31_dec_sub27_dec31_dec_sub27_out_sel + connect \dec31_dec_sub27_rc_sel \dec31_dec_sub27_dec31_dec_sub27_rc_sel + connect \dec31_dec_sub27_rsrv \dec31_dec_sub27_dec31_dec_sub27_rsrv + connect \dec31_dec_sub27_sgl_pipe \dec31_dec_sub27_dec31_dec_sub27_sgl_pipe + connect \dec31_dec_sub27_sgn \dec31_dec_sub27_dec31_dec_sub27_sgn + connect \dec31_dec_sub27_sgn_ext \dec31_dec_sub27_dec31_dec_sub27_sgn_ext + connect \dec31_dec_sub27_upd \dec31_dec_sub27_dec31_dec_sub27_upd + connect \opcode_in \dec31_dec_sub27_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:80766.19-80792.4" + cell \dec31_dec_sub28 \dec31_dec_sub28 + connect \dec31_dec_sub28_asmcode \dec31_dec_sub28_dec31_dec_sub28_asmcode + connect \dec31_dec_sub28_br \dec31_dec_sub28_dec31_dec_sub28_br + connect \dec31_dec_sub28_cr_in \dec31_dec_sub28_dec31_dec_sub28_cr_in + connect \dec31_dec_sub28_cr_out \dec31_dec_sub28_dec31_dec_sub28_cr_out + connect \dec31_dec_sub28_cry_in \dec31_dec_sub28_dec31_dec_sub28_cry_in + connect \dec31_dec_sub28_cry_out \dec31_dec_sub28_dec31_dec_sub28_cry_out + connect \dec31_dec_sub28_form \dec31_dec_sub28_dec31_dec_sub28_form + connect \dec31_dec_sub28_function_unit \dec31_dec_sub28_dec31_dec_sub28_function_unit + connect \dec31_dec_sub28_in1_sel \dec31_dec_sub28_dec31_dec_sub28_in1_sel + connect \dec31_dec_sub28_in2_sel \dec31_dec_sub28_dec31_dec_sub28_in2_sel + connect \dec31_dec_sub28_in3_sel \dec31_dec_sub28_dec31_dec_sub28_in3_sel + connect \dec31_dec_sub28_internal_op \dec31_dec_sub28_dec31_dec_sub28_internal_op + connect \dec31_dec_sub28_inv_a \dec31_dec_sub28_dec31_dec_sub28_inv_a + connect \dec31_dec_sub28_inv_out \dec31_dec_sub28_dec31_dec_sub28_inv_out + connect \dec31_dec_sub28_is_32b \dec31_dec_sub28_dec31_dec_sub28_is_32b + connect \dec31_dec_sub28_ldst_len \dec31_dec_sub28_dec31_dec_sub28_ldst_len + connect \dec31_dec_sub28_lk \dec31_dec_sub28_dec31_dec_sub28_lk + connect \dec31_dec_sub28_out_sel \dec31_dec_sub28_dec31_dec_sub28_out_sel + connect \dec31_dec_sub28_rc_sel \dec31_dec_sub28_dec31_dec_sub28_rc_sel + connect \dec31_dec_sub28_rsrv \dec31_dec_sub28_dec31_dec_sub28_rsrv + connect \dec31_dec_sub28_sgl_pipe \dec31_dec_sub28_dec31_dec_sub28_sgl_pipe + connect \dec31_dec_sub28_sgn \dec31_dec_sub28_dec31_dec_sub28_sgn + connect \dec31_dec_sub28_sgn_ext \dec31_dec_sub28_dec31_dec_sub28_sgn_ext + connect \dec31_dec_sub28_upd \dec31_dec_sub28_dec31_dec_sub28_upd + connect \opcode_in \dec31_dec_sub28_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:80793.18-80819.4" + cell \dec31_dec_sub4 \dec31_dec_sub4 + connect \dec31_dec_sub4_asmcode \dec31_dec_sub4_dec31_dec_sub4_asmcode + connect \dec31_dec_sub4_br \dec31_dec_sub4_dec31_dec_sub4_br + connect \dec31_dec_sub4_cr_in \dec31_dec_sub4_dec31_dec_sub4_cr_in + connect \dec31_dec_sub4_cr_out \dec31_dec_sub4_dec31_dec_sub4_cr_out + connect \dec31_dec_sub4_cry_in \dec31_dec_sub4_dec31_dec_sub4_cry_in + connect \dec31_dec_sub4_cry_out \dec31_dec_sub4_dec31_dec_sub4_cry_out + connect \dec31_dec_sub4_form \dec31_dec_sub4_dec31_dec_sub4_form + connect \dec31_dec_sub4_function_unit \dec31_dec_sub4_dec31_dec_sub4_function_unit + connect \dec31_dec_sub4_in1_sel \dec31_dec_sub4_dec31_dec_sub4_in1_sel + connect \dec31_dec_sub4_in2_sel \dec31_dec_sub4_dec31_dec_sub4_in2_sel + connect \dec31_dec_sub4_in3_sel \dec31_dec_sub4_dec31_dec_sub4_in3_sel + connect \dec31_dec_sub4_internal_op \dec31_dec_sub4_dec31_dec_sub4_internal_op + connect \dec31_dec_sub4_inv_a \dec31_dec_sub4_dec31_dec_sub4_inv_a + connect \dec31_dec_sub4_inv_out \dec31_dec_sub4_dec31_dec_sub4_inv_out + connect \dec31_dec_sub4_is_32b \dec31_dec_sub4_dec31_dec_sub4_is_32b + connect \dec31_dec_sub4_ldst_len \dec31_dec_sub4_dec31_dec_sub4_ldst_len + connect \dec31_dec_sub4_lk \dec31_dec_sub4_dec31_dec_sub4_lk + connect \dec31_dec_sub4_out_sel \dec31_dec_sub4_dec31_dec_sub4_out_sel + connect \dec31_dec_sub4_rc_sel \dec31_dec_sub4_dec31_dec_sub4_rc_sel + connect \dec31_dec_sub4_rsrv \dec31_dec_sub4_dec31_dec_sub4_rsrv + connect \dec31_dec_sub4_sgl_pipe \dec31_dec_sub4_dec31_dec_sub4_sgl_pipe + connect \dec31_dec_sub4_sgn \dec31_dec_sub4_dec31_dec_sub4_sgn + connect \dec31_dec_sub4_sgn_ext \dec31_dec_sub4_dec31_dec_sub4_sgn_ext + connect \dec31_dec_sub4_upd \dec31_dec_sub4_dec31_dec_sub4_upd + connect \opcode_in \dec31_dec_sub4_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:80820.18-80846.4" + cell \dec31_dec_sub8 \dec31_dec_sub8 + connect \dec31_dec_sub8_asmcode \dec31_dec_sub8_dec31_dec_sub8_asmcode + connect \dec31_dec_sub8_br \dec31_dec_sub8_dec31_dec_sub8_br + connect \dec31_dec_sub8_cr_in \dec31_dec_sub8_dec31_dec_sub8_cr_in + connect \dec31_dec_sub8_cr_out \dec31_dec_sub8_dec31_dec_sub8_cr_out + connect \dec31_dec_sub8_cry_in \dec31_dec_sub8_dec31_dec_sub8_cry_in + connect \dec31_dec_sub8_cry_out \dec31_dec_sub8_dec31_dec_sub8_cry_out + connect \dec31_dec_sub8_form \dec31_dec_sub8_dec31_dec_sub8_form + connect \dec31_dec_sub8_function_unit \dec31_dec_sub8_dec31_dec_sub8_function_unit + connect \dec31_dec_sub8_in1_sel \dec31_dec_sub8_dec31_dec_sub8_in1_sel + connect \dec31_dec_sub8_in2_sel \dec31_dec_sub8_dec31_dec_sub8_in2_sel + connect \dec31_dec_sub8_in3_sel \dec31_dec_sub8_dec31_dec_sub8_in3_sel + connect \dec31_dec_sub8_internal_op \dec31_dec_sub8_dec31_dec_sub8_internal_op + connect \dec31_dec_sub8_inv_a \dec31_dec_sub8_dec31_dec_sub8_inv_a + connect \dec31_dec_sub8_inv_out \dec31_dec_sub8_dec31_dec_sub8_inv_out + connect \dec31_dec_sub8_is_32b \dec31_dec_sub8_dec31_dec_sub8_is_32b + connect \dec31_dec_sub8_ldst_len \dec31_dec_sub8_dec31_dec_sub8_ldst_len + connect \dec31_dec_sub8_lk \dec31_dec_sub8_dec31_dec_sub8_lk + connect \dec31_dec_sub8_out_sel \dec31_dec_sub8_dec31_dec_sub8_out_sel + connect \dec31_dec_sub8_rc_sel \dec31_dec_sub8_dec31_dec_sub8_rc_sel + connect \dec31_dec_sub8_rsrv \dec31_dec_sub8_dec31_dec_sub8_rsrv + connect \dec31_dec_sub8_sgl_pipe \dec31_dec_sub8_dec31_dec_sub8_sgl_pipe + connect \dec31_dec_sub8_sgn \dec31_dec_sub8_dec31_dec_sub8_sgn + connect \dec31_dec_sub8_sgn_ext \dec31_dec_sub8_dec31_dec_sub8_sgn_ext + connect \dec31_dec_sub8_upd \dec31_dec_sub8_dec31_dec_sub8_upd + connect \opcode_in \dec31_dec_sub8_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:80847.18-80873.4" + cell \dec31_dec_sub9 \dec31_dec_sub9 + connect \dec31_dec_sub9_asmcode \dec31_dec_sub9_dec31_dec_sub9_asmcode + connect \dec31_dec_sub9_br \dec31_dec_sub9_dec31_dec_sub9_br + connect \dec31_dec_sub9_cr_in \dec31_dec_sub9_dec31_dec_sub9_cr_in + connect \dec31_dec_sub9_cr_out \dec31_dec_sub9_dec31_dec_sub9_cr_out + connect \dec31_dec_sub9_cry_in \dec31_dec_sub9_dec31_dec_sub9_cry_in + connect \dec31_dec_sub9_cry_out \dec31_dec_sub9_dec31_dec_sub9_cry_out + connect \dec31_dec_sub9_form \dec31_dec_sub9_dec31_dec_sub9_form + connect \dec31_dec_sub9_function_unit \dec31_dec_sub9_dec31_dec_sub9_function_unit + connect \dec31_dec_sub9_in1_sel \dec31_dec_sub9_dec31_dec_sub9_in1_sel + connect \dec31_dec_sub9_in2_sel \dec31_dec_sub9_dec31_dec_sub9_in2_sel + connect \dec31_dec_sub9_in3_sel \dec31_dec_sub9_dec31_dec_sub9_in3_sel + connect \dec31_dec_sub9_internal_op \dec31_dec_sub9_dec31_dec_sub9_internal_op + connect \dec31_dec_sub9_inv_a \dec31_dec_sub9_dec31_dec_sub9_inv_a + connect \dec31_dec_sub9_inv_out \dec31_dec_sub9_dec31_dec_sub9_inv_out + connect \dec31_dec_sub9_is_32b \dec31_dec_sub9_dec31_dec_sub9_is_32b + connect \dec31_dec_sub9_ldst_len \dec31_dec_sub9_dec31_dec_sub9_ldst_len + connect \dec31_dec_sub9_lk \dec31_dec_sub9_dec31_dec_sub9_lk + connect \dec31_dec_sub9_out_sel \dec31_dec_sub9_dec31_dec_sub9_out_sel + connect \dec31_dec_sub9_rc_sel \dec31_dec_sub9_dec31_dec_sub9_rc_sel + connect \dec31_dec_sub9_rsrv \dec31_dec_sub9_dec31_dec_sub9_rsrv + connect \dec31_dec_sub9_sgl_pipe \dec31_dec_sub9_dec31_dec_sub9_sgl_pipe + connect \dec31_dec_sub9_sgn \dec31_dec_sub9_dec31_dec_sub9_sgn + connect \dec31_dec_sub9_sgn_ext \dec31_dec_sub9_dec31_dec_sub9_sgn_ext + connect \dec31_dec_sub9_upd \dec31_dec_sub9_dec31_dec_sub9_upd + connect \opcode_in \dec31_dec_sub9_opcode_in + end + attribute \src "libresoc.v:75989.7-75989.20" + process $proc$libresoc.v:75989$3680 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:80874.3-80934.6" + process $proc$libresoc.v:80874$3656 + assign { } { } + assign { } { } + assign $0\dec31_function_unit[11:0] $1\dec31_function_unit[11:0] + attribute \src "libresoc.v:80875.5-80875.29" + switch \initial + attribute \src "libresoc.v:80875.9-80875.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_function_unit[11:0] \dec31_dec_sub10_dec31_dec_sub10_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_function_unit[11:0] \dec31_dec_sub28_dec31_dec_sub28_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_function_unit[11:0] \dec31_dec_sub0_dec31_dec_sub0_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_function_unit[11:0] \dec31_dec_sub26_dec31_dec_sub26_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_function_unit[11:0] \dec31_dec_sub19_dec31_dec_sub19_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_function_unit[11:0] \dec31_dec_sub22_dec31_dec_sub22_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_function_unit[11:0] \dec31_dec_sub9_dec31_dec_sub9_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_function_unit[11:0] \dec31_dec_sub11_dec31_dec_sub11_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_function_unit[11:0] \dec31_dec_sub27_dec31_dec_sub27_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_function_unit[11:0] \dec31_dec_sub15_dec31_dec_sub15_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_function_unit[11:0] \dec31_dec_sub20_dec31_dec_sub20_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_function_unit[11:0] \dec31_dec_sub21_dec31_dec_sub21_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_function_unit[11:0] \dec31_dec_sub23_dec31_dec_sub23_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_function_unit[11:0] \dec31_dec_sub16_dec31_dec_sub16_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_function_unit[11:0] \dec31_dec_sub18_dec31_dec_sub18_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_function_unit[11:0] \dec31_dec_sub8_dec31_dec_sub8_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_function_unit[11:0] \dec31_dec_sub24_dec31_dec_sub24_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_function_unit[11:0] \dec31_dec_sub4_dec31_dec_sub4_function_unit + case + assign $1\dec31_function_unit[11:0] 12'000000000000 + end + sync always + update \dec31_function_unit $0\dec31_function_unit[11:0] + end + attribute \src "libresoc.v:80935.3-80995.6" + process $proc$libresoc.v:80935$3657 + assign { } { } + assign { } { } + assign $0\dec31_internal_op[6:0] $1\dec31_internal_op[6:0] + attribute \src "libresoc.v:80936.5-80936.29" + switch \initial + attribute \src "libresoc.v:80936.9-80936.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub10_dec31_dec_sub10_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub28_dec31_dec_sub28_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub0_dec31_dec_sub0_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub26_dec31_dec_sub26_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub19_dec31_dec_sub19_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub22_dec31_dec_sub22_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub9_dec31_dec_sub9_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub11_dec31_dec_sub11_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub27_dec31_dec_sub27_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub15_dec31_dec_sub15_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub20_dec31_dec_sub20_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub21_dec31_dec_sub21_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub23_dec31_dec_sub23_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub16_dec31_dec_sub16_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub18_dec31_dec_sub18_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub8_dec31_dec_sub8_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub24_dec31_dec_sub24_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub4_dec31_dec_sub4_internal_op + case + assign $1\dec31_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_internal_op $0\dec31_internal_op[6:0] + end + attribute \src "libresoc.v:80996.3-81056.6" + process $proc$libresoc.v:80996$3658 + assign { } { } + assign { } { } + assign $0\dec31_form[4:0] $1\dec31_form[4:0] + attribute \src "libresoc.v:80997.5-80997.29" + switch \initial + attribute \src "libresoc.v:80997.9-80997.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub10_dec31_dec_sub10_form + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub28_dec31_dec_sub28_form + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub0_dec31_dec_sub0_form + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub26_dec31_dec_sub26_form + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub19_dec31_dec_sub19_form + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub22_dec31_dec_sub22_form + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub9_dec31_dec_sub9_form + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub11_dec31_dec_sub11_form + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub27_dec31_dec_sub27_form + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub15_dec31_dec_sub15_form + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub20_dec31_dec_sub20_form + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub21_dec31_dec_sub21_form + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub23_dec31_dec_sub23_form + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub16_dec31_dec_sub16_form + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub18_dec31_dec_sub18_form + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub8_dec31_dec_sub8_form + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub24_dec31_dec_sub24_form + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub4_dec31_dec_sub4_form + case + assign $1\dec31_form[4:0] 5'00000 + end + sync always + update \dec31_form $0\dec31_form[4:0] + end + attribute \src "libresoc.v:81057.3-81117.6" + process $proc$libresoc.v:81057$3659 + assign { } { } + assign { } { } + assign $0\dec31_asmcode[7:0] $1\dec31_asmcode[7:0] + attribute \src "libresoc.v:81058.5-81058.29" + switch \initial + attribute \src "libresoc.v:81058.9-81058.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub10_dec31_dec_sub10_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub28_dec31_dec_sub28_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub0_dec31_dec_sub0_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub26_dec31_dec_sub26_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub19_dec31_dec_sub19_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub22_dec31_dec_sub22_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub9_dec31_dec_sub9_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub11_dec31_dec_sub11_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub27_dec31_dec_sub27_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub15_dec31_dec_sub15_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub20_dec31_dec_sub20_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub21_dec31_dec_sub21_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub23_dec31_dec_sub23_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub16_dec31_dec_sub16_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub18_dec31_dec_sub18_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub8_dec31_dec_sub8_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub24_dec31_dec_sub24_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub4_dec31_dec_sub4_asmcode + case + assign $1\dec31_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_asmcode $0\dec31_asmcode[7:0] + end + attribute \src "libresoc.v:81118.3-81178.6" + process $proc$libresoc.v:81118$3660 + assign { } { } + assign { } { } + assign $0\dec31_in1_sel[2:0] $1\dec31_in1_sel[2:0] + attribute \src "libresoc.v:81119.5-81119.29" + switch \initial + attribute \src "libresoc.v:81119.9-81119.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub10_dec31_dec_sub10_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub28_dec31_dec_sub28_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub0_dec31_dec_sub0_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub26_dec31_dec_sub26_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub19_dec31_dec_sub19_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub22_dec31_dec_sub22_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub9_dec31_dec_sub9_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub11_dec31_dec_sub11_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub27_dec31_dec_sub27_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub15_dec31_dec_sub15_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub20_dec31_dec_sub20_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub21_dec31_dec_sub21_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub23_dec31_dec_sub23_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub16_dec31_dec_sub16_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub18_dec31_dec_sub18_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub8_dec31_dec_sub8_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub24_dec31_dec_sub24_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub4_dec31_dec_sub4_in1_sel + case + assign $1\dec31_in1_sel[2:0] 3'000 + end + sync always + update \dec31_in1_sel $0\dec31_in1_sel[2:0] + end + attribute \src "libresoc.v:81179.3-81239.6" + process $proc$libresoc.v:81179$3661 + assign { } { } + assign { } { } + assign $0\dec31_in2_sel[3:0] $1\dec31_in2_sel[3:0] + attribute \src "libresoc.v:81180.5-81180.29" + switch \initial + attribute \src "libresoc.v:81180.9-81180.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub10_dec31_dec_sub10_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub28_dec31_dec_sub28_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub0_dec31_dec_sub0_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub26_dec31_dec_sub26_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub19_dec31_dec_sub19_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub22_dec31_dec_sub22_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub9_dec31_dec_sub9_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub11_dec31_dec_sub11_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub27_dec31_dec_sub27_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub15_dec31_dec_sub15_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub20_dec31_dec_sub20_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub21_dec31_dec_sub21_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub23_dec31_dec_sub23_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub16_dec31_dec_sub16_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub18_dec31_dec_sub18_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub8_dec31_dec_sub8_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub24_dec31_dec_sub24_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub4_dec31_dec_sub4_in2_sel + case + assign $1\dec31_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_in2_sel $0\dec31_in2_sel[3:0] + end + attribute \src "libresoc.v:81240.3-81300.6" + process $proc$libresoc.v:81240$3662 + assign { } { } + assign { } { } + assign $0\dec31_in3_sel[1:0] $1\dec31_in3_sel[1:0] + attribute \src "libresoc.v:81241.5-81241.29" + switch \initial + attribute \src "libresoc.v:81241.9-81241.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub10_dec31_dec_sub10_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub28_dec31_dec_sub28_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub0_dec31_dec_sub0_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub26_dec31_dec_sub26_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub19_dec31_dec_sub19_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub22_dec31_dec_sub22_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub9_dec31_dec_sub9_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub11_dec31_dec_sub11_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub27_dec31_dec_sub27_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub15_dec31_dec_sub15_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub20_dec31_dec_sub20_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub21_dec31_dec_sub21_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub23_dec31_dec_sub23_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub16_dec31_dec_sub16_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub18_dec31_dec_sub18_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub8_dec31_dec_sub8_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub24_dec31_dec_sub24_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub4_dec31_dec_sub4_in3_sel + case + assign $1\dec31_in3_sel[1:0] 2'00 + end + sync always + update \dec31_in3_sel $0\dec31_in3_sel[1:0] + end + attribute \src "libresoc.v:81301.3-81361.6" + process $proc$libresoc.v:81301$3663 + assign { } { } + assign { } { } + assign $0\dec31_out_sel[1:0] $1\dec31_out_sel[1:0] + attribute \src "libresoc.v:81302.5-81302.29" + switch \initial + attribute \src "libresoc.v:81302.9-81302.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub10_dec31_dec_sub10_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub28_dec31_dec_sub28_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub0_dec31_dec_sub0_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub26_dec31_dec_sub26_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub19_dec31_dec_sub19_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub22_dec31_dec_sub22_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub9_dec31_dec_sub9_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub11_dec31_dec_sub11_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub27_dec31_dec_sub27_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub15_dec31_dec_sub15_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub20_dec31_dec_sub20_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub21_dec31_dec_sub21_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub23_dec31_dec_sub23_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub16_dec31_dec_sub16_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub18_dec31_dec_sub18_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub8_dec31_dec_sub8_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub24_dec31_dec_sub24_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub4_dec31_dec_sub4_out_sel + case + assign $1\dec31_out_sel[1:0] 2'00 + end + sync always + update \dec31_out_sel $0\dec31_out_sel[1:0] + end + attribute \src "libresoc.v:81362.3-81422.6" + process $proc$libresoc.v:81362$3664 + assign { } { } + assign { } { } + assign $0\dec31_cr_in[2:0] $1\dec31_cr_in[2:0] + attribute \src "libresoc.v:81363.5-81363.29" + switch \initial + attribute \src "libresoc.v:81363.9-81363.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub10_dec31_dec_sub10_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub28_dec31_dec_sub28_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub0_dec31_dec_sub0_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub26_dec31_dec_sub26_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub19_dec31_dec_sub19_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub22_dec31_dec_sub22_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub9_dec31_dec_sub9_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub11_dec31_dec_sub11_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub27_dec31_dec_sub27_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub15_dec31_dec_sub15_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub20_dec31_dec_sub20_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub21_dec31_dec_sub21_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub23_dec31_dec_sub23_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub16_dec31_dec_sub16_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub18_dec31_dec_sub18_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub8_dec31_dec_sub8_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub24_dec31_dec_sub24_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub4_dec31_dec_sub4_cr_in + case + assign $1\dec31_cr_in[2:0] 3'000 + end + sync always + update \dec31_cr_in $0\dec31_cr_in[2:0] + end + attribute \src "libresoc.v:81423.3-81483.6" + process $proc$libresoc.v:81423$3665 + assign { } { } + assign { } { } + assign $0\dec31_cr_out[2:0] $1\dec31_cr_out[2:0] + attribute \src "libresoc.v:81424.5-81424.29" + switch \initial + attribute \src "libresoc.v:81424.9-81424.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub10_dec31_dec_sub10_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub28_dec31_dec_sub28_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub0_dec31_dec_sub0_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub26_dec31_dec_sub26_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub19_dec31_dec_sub19_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub22_dec31_dec_sub22_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub9_dec31_dec_sub9_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub11_dec31_dec_sub11_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub27_dec31_dec_sub27_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub15_dec31_dec_sub15_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub20_dec31_dec_sub20_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub21_dec31_dec_sub21_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub23_dec31_dec_sub23_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub16_dec31_dec_sub16_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub18_dec31_dec_sub18_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub8_dec31_dec_sub8_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub24_dec31_dec_sub24_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub4_dec31_dec_sub4_cr_out + case + assign $1\dec31_cr_out[2:0] 3'000 + end + sync always + update \dec31_cr_out $0\dec31_cr_out[2:0] + end + attribute \src "libresoc.v:81484.3-81544.6" + process $proc$libresoc.v:81484$3666 + assign { } { } + assign { } { } + assign $0\dec31_ldst_len[3:0] $1\dec31_ldst_len[3:0] + attribute \src "libresoc.v:81485.5-81485.29" + switch \initial + attribute \src "libresoc.v:81485.9-81485.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub10_dec31_dec_sub10_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub28_dec31_dec_sub28_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub0_dec31_dec_sub0_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub26_dec31_dec_sub26_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub19_dec31_dec_sub19_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub22_dec31_dec_sub22_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub9_dec31_dec_sub9_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub11_dec31_dec_sub11_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub27_dec31_dec_sub27_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub15_dec31_dec_sub15_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub20_dec31_dec_sub20_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub21_dec31_dec_sub21_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub23_dec31_dec_sub23_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub16_dec31_dec_sub16_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub18_dec31_dec_sub18_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub8_dec31_dec_sub8_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub24_dec31_dec_sub24_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub4_dec31_dec_sub4_ldst_len + case + assign $1\dec31_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_ldst_len $0\dec31_ldst_len[3:0] + end + attribute \src "libresoc.v:81545.3-81605.6" + process $proc$libresoc.v:81545$3667 + assign { } { } + assign { } { } + assign $0\dec31_upd[1:0] $1\dec31_upd[1:0] + attribute \src "libresoc.v:81546.5-81546.29" + switch \initial + attribute \src "libresoc.v:81546.9-81546.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub10_dec31_dec_sub10_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub28_dec31_dec_sub28_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub0_dec31_dec_sub0_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub26_dec31_dec_sub26_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub19_dec31_dec_sub19_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub22_dec31_dec_sub22_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub9_dec31_dec_sub9_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub11_dec31_dec_sub11_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub27_dec31_dec_sub27_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub15_dec31_dec_sub15_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub20_dec31_dec_sub20_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub21_dec31_dec_sub21_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub23_dec31_dec_sub23_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub16_dec31_dec_sub16_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub18_dec31_dec_sub18_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub8_dec31_dec_sub8_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub24_dec31_dec_sub24_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub4_dec31_dec_sub4_upd + case + assign $1\dec31_upd[1:0] 2'00 + end + sync always + update \dec31_upd $0\dec31_upd[1:0] + end + attribute \src "libresoc.v:81606.3-81666.6" + process $proc$libresoc.v:81606$3668 + assign { } { } + assign { } { } + assign $0\dec31_rc_sel[1:0] $1\dec31_rc_sel[1:0] + attribute \src "libresoc.v:81607.5-81607.29" + switch \initial + attribute \src "libresoc.v:81607.9-81607.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub10_dec31_dec_sub10_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub28_dec31_dec_sub28_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub0_dec31_dec_sub0_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub26_dec31_dec_sub26_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub19_dec31_dec_sub19_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub22_dec31_dec_sub22_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub9_dec31_dec_sub9_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub11_dec31_dec_sub11_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub27_dec31_dec_sub27_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub15_dec31_dec_sub15_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub20_dec31_dec_sub20_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub21_dec31_dec_sub21_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub23_dec31_dec_sub23_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub16_dec31_dec_sub16_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub18_dec31_dec_sub18_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub8_dec31_dec_sub8_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub24_dec31_dec_sub24_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub4_dec31_dec_sub4_rc_sel + case + assign $1\dec31_rc_sel[1:0] 2'00 + end + sync always + update \dec31_rc_sel $0\dec31_rc_sel[1:0] + end + attribute \src "libresoc.v:81667.3-81727.6" + process $proc$libresoc.v:81667$3669 + assign { } { } + assign { } { } + assign $0\dec31_cry_in[1:0] $1\dec31_cry_in[1:0] + attribute \src "libresoc.v:81668.5-81668.29" + switch \initial + attribute \src "libresoc.v:81668.9-81668.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub10_dec31_dec_sub10_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub28_dec31_dec_sub28_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub0_dec31_dec_sub0_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub26_dec31_dec_sub26_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub19_dec31_dec_sub19_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub22_dec31_dec_sub22_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub9_dec31_dec_sub9_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub11_dec31_dec_sub11_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub27_dec31_dec_sub27_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub15_dec31_dec_sub15_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub20_dec31_dec_sub20_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub21_dec31_dec_sub21_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub23_dec31_dec_sub23_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub16_dec31_dec_sub16_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub18_dec31_dec_sub18_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub8_dec31_dec_sub8_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub24_dec31_dec_sub24_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub4_dec31_dec_sub4_cry_in + case + assign $1\dec31_cry_in[1:0] 2'00 + end + sync always + update \dec31_cry_in $0\dec31_cry_in[1:0] + end + attribute \src "libresoc.v:81728.3-81788.6" + process $proc$libresoc.v:81728$3670 + assign { } { } + assign { } { } + assign $0\dec31_inv_a[0:0] $1\dec31_inv_a[0:0] + attribute \src "libresoc.v:81729.5-81729.29" + switch \initial + attribute \src "libresoc.v:81729.9-81729.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub10_dec31_dec_sub10_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub28_dec31_dec_sub28_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub0_dec31_dec_sub0_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub26_dec31_dec_sub26_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub19_dec31_dec_sub19_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub22_dec31_dec_sub22_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub9_dec31_dec_sub9_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub11_dec31_dec_sub11_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub27_dec31_dec_sub27_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub15_dec31_dec_sub15_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub20_dec31_dec_sub20_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub21_dec31_dec_sub21_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub23_dec31_dec_sub23_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub16_dec31_dec_sub16_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub18_dec31_dec_sub18_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub8_dec31_dec_sub8_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub24_dec31_dec_sub24_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub4_dec31_dec_sub4_inv_a + case + assign $1\dec31_inv_a[0:0] 1'0 + end + sync always + update \dec31_inv_a $0\dec31_inv_a[0:0] + end + attribute \src "libresoc.v:81789.3-81849.6" + process $proc$libresoc.v:81789$3671 + assign { } { } + assign { } { } + assign $0\dec31_inv_out[0:0] $1\dec31_inv_out[0:0] + attribute \src "libresoc.v:81790.5-81790.29" + switch \initial + attribute \src "libresoc.v:81790.9-81790.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub10_dec31_dec_sub10_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub28_dec31_dec_sub28_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub0_dec31_dec_sub0_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub26_dec31_dec_sub26_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub19_dec31_dec_sub19_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub22_dec31_dec_sub22_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub9_dec31_dec_sub9_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub11_dec31_dec_sub11_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub27_dec31_dec_sub27_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub15_dec31_dec_sub15_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub20_dec31_dec_sub20_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub21_dec31_dec_sub21_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub23_dec31_dec_sub23_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub16_dec31_dec_sub16_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub18_dec31_dec_sub18_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub8_dec31_dec_sub8_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub24_dec31_dec_sub24_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub4_dec31_dec_sub4_inv_out + case + assign $1\dec31_inv_out[0:0] 1'0 + end + sync always + update \dec31_inv_out $0\dec31_inv_out[0:0] + end + attribute \src "libresoc.v:81850.3-81910.6" + process $proc$libresoc.v:81850$3672 + assign { } { } + assign { } { } + assign $0\dec31_cry_out[0:0] $1\dec31_cry_out[0:0] + attribute \src "libresoc.v:81851.5-81851.29" + switch \initial + attribute \src "libresoc.v:81851.9-81851.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub10_dec31_dec_sub10_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub28_dec31_dec_sub28_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub0_dec31_dec_sub0_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub26_dec31_dec_sub26_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub19_dec31_dec_sub19_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub22_dec31_dec_sub22_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub9_dec31_dec_sub9_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub11_dec31_dec_sub11_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub27_dec31_dec_sub27_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub15_dec31_dec_sub15_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub20_dec31_dec_sub20_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub21_dec31_dec_sub21_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub23_dec31_dec_sub23_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub16_dec31_dec_sub16_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub18_dec31_dec_sub18_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub8_dec31_dec_sub8_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub24_dec31_dec_sub24_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub4_dec31_dec_sub4_cry_out + case + assign $1\dec31_cry_out[0:0] 1'0 + end + sync always + update \dec31_cry_out $0\dec31_cry_out[0:0] + end + attribute \src "libresoc.v:81911.3-81971.6" + process $proc$libresoc.v:81911$3673 + assign { } { } + assign { } { } + assign $0\dec31_br[0:0] $1\dec31_br[0:0] + attribute \src "libresoc.v:81912.5-81912.29" + switch \initial + attribute \src "libresoc.v:81912.9-81912.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub10_dec31_dec_sub10_br + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub28_dec31_dec_sub28_br + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub0_dec31_dec_sub0_br + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub26_dec31_dec_sub26_br + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub19_dec31_dec_sub19_br + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub22_dec31_dec_sub22_br + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub9_dec31_dec_sub9_br + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub11_dec31_dec_sub11_br + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub27_dec31_dec_sub27_br + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub15_dec31_dec_sub15_br + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub20_dec31_dec_sub20_br + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub21_dec31_dec_sub21_br + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub23_dec31_dec_sub23_br + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub16_dec31_dec_sub16_br + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub18_dec31_dec_sub18_br + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub8_dec31_dec_sub8_br + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub24_dec31_dec_sub24_br + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub4_dec31_dec_sub4_br + case + assign $1\dec31_br[0:0] 1'0 + end + sync always + update \dec31_br $0\dec31_br[0:0] + end + attribute \src "libresoc.v:81972.3-82032.6" + process $proc$libresoc.v:81972$3674 + assign { } { } + assign { } { } + assign $0\dec31_sgn_ext[0:0] $1\dec31_sgn_ext[0:0] + attribute \src "libresoc.v:81973.5-81973.29" + switch \initial + attribute \src "libresoc.v:81973.9-81973.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub10_dec31_dec_sub10_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub28_dec31_dec_sub28_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub0_dec31_dec_sub0_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub26_dec31_dec_sub26_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub19_dec31_dec_sub19_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub22_dec31_dec_sub22_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub9_dec31_dec_sub9_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub11_dec31_dec_sub11_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub27_dec31_dec_sub27_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub15_dec31_dec_sub15_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub20_dec31_dec_sub20_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub21_dec31_dec_sub21_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub23_dec31_dec_sub23_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub16_dec31_dec_sub16_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub18_dec31_dec_sub18_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub8_dec31_dec_sub8_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub24_dec31_dec_sub24_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub4_dec31_dec_sub4_sgn_ext + case + assign $1\dec31_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_sgn_ext $0\dec31_sgn_ext[0:0] + end + attribute \src "libresoc.v:82033.3-82093.6" + process $proc$libresoc.v:82033$3675 + assign { } { } + assign { } { } + assign $0\dec31_rsrv[0:0] $1\dec31_rsrv[0:0] + attribute \src "libresoc.v:82034.5-82034.29" + switch \initial + attribute \src "libresoc.v:82034.9-82034.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub10_dec31_dec_sub10_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub28_dec31_dec_sub28_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub0_dec31_dec_sub0_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub26_dec31_dec_sub26_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub19_dec31_dec_sub19_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub22_dec31_dec_sub22_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub9_dec31_dec_sub9_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub11_dec31_dec_sub11_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub27_dec31_dec_sub27_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub15_dec31_dec_sub15_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub20_dec31_dec_sub20_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub21_dec31_dec_sub21_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub23_dec31_dec_sub23_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub16_dec31_dec_sub16_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub18_dec31_dec_sub18_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub8_dec31_dec_sub8_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub24_dec31_dec_sub24_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub4_dec31_dec_sub4_rsrv + case + assign $1\dec31_rsrv[0:0] 1'0 + end + sync always + update \dec31_rsrv $0\dec31_rsrv[0:0] + end + attribute \src "libresoc.v:82094.3-82154.6" + process $proc$libresoc.v:82094$3676 + assign { } { } + assign { } { } + assign $0\dec31_is_32b[0:0] $1\dec31_is_32b[0:0] + attribute \src "libresoc.v:82095.5-82095.29" + switch \initial + attribute \src "libresoc.v:82095.9-82095.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub10_dec31_dec_sub10_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub28_dec31_dec_sub28_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub0_dec31_dec_sub0_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub26_dec31_dec_sub26_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub19_dec31_dec_sub19_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub22_dec31_dec_sub22_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub9_dec31_dec_sub9_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub11_dec31_dec_sub11_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub27_dec31_dec_sub27_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub15_dec31_dec_sub15_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub20_dec31_dec_sub20_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub21_dec31_dec_sub21_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub23_dec31_dec_sub23_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub16_dec31_dec_sub16_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub18_dec31_dec_sub18_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub8_dec31_dec_sub8_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub24_dec31_dec_sub24_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub4_dec31_dec_sub4_is_32b + case + assign $1\dec31_is_32b[0:0] 1'0 + end + sync always + update \dec31_is_32b $0\dec31_is_32b[0:0] + end + attribute \src "libresoc.v:82155.3-82215.6" + process $proc$libresoc.v:82155$3677 + assign { } { } + assign { } { } + assign $0\dec31_sgn[0:0] $1\dec31_sgn[0:0] + attribute \src "libresoc.v:82156.5-82156.29" + switch \initial + attribute \src "libresoc.v:82156.9-82156.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub10_dec31_dec_sub10_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub28_dec31_dec_sub28_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub0_dec31_dec_sub0_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub26_dec31_dec_sub26_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub19_dec31_dec_sub19_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub22_dec31_dec_sub22_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub9_dec31_dec_sub9_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub11_dec31_dec_sub11_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub27_dec31_dec_sub27_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub15_dec31_dec_sub15_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub20_dec31_dec_sub20_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub21_dec31_dec_sub21_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub23_dec31_dec_sub23_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub16_dec31_dec_sub16_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub18_dec31_dec_sub18_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub8_dec31_dec_sub8_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub24_dec31_dec_sub24_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub4_dec31_dec_sub4_sgn + case + assign $1\dec31_sgn[0:0] 1'0 + end + sync always + update \dec31_sgn $0\dec31_sgn[0:0] + end + attribute \src "libresoc.v:82216.3-82276.6" + process $proc$libresoc.v:82216$3678 + assign { } { } + assign { } { } + assign $0\dec31_lk[0:0] $1\dec31_lk[0:0] + attribute \src "libresoc.v:82217.5-82217.29" + switch \initial + attribute \src "libresoc.v:82217.9-82217.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub10_dec31_dec_sub10_lk + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub28_dec31_dec_sub28_lk + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub0_dec31_dec_sub0_lk + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub26_dec31_dec_sub26_lk + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub19_dec31_dec_sub19_lk + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub22_dec31_dec_sub22_lk + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub9_dec31_dec_sub9_lk + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub11_dec31_dec_sub11_lk + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub27_dec31_dec_sub27_lk + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub15_dec31_dec_sub15_lk + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub20_dec31_dec_sub20_lk + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub21_dec31_dec_sub21_lk + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub23_dec31_dec_sub23_lk + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub16_dec31_dec_sub16_lk + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub18_dec31_dec_sub18_lk + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub8_dec31_dec_sub8_lk + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub24_dec31_dec_sub24_lk + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub4_dec31_dec_sub4_lk + case + assign $1\dec31_lk[0:0] 1'0 + end + sync always + update \dec31_lk $0\dec31_lk[0:0] + end + attribute \src "libresoc.v:82277.3-82337.6" + process $proc$libresoc.v:82277$3679 + assign { } { } + assign { } { } + assign $0\dec31_sgl_pipe[0:0] $1\dec31_sgl_pipe[0:0] + attribute \src "libresoc.v:82278.5-82278.29" + switch \initial + attribute \src "libresoc.v:82278.9-82278.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub10_dec31_dec_sub10_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub28_dec31_dec_sub28_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub0_dec31_dec_sub0_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub26_dec31_dec_sub26_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub19_dec31_dec_sub19_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub22_dec31_dec_sub22_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub9_dec31_dec_sub9_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub11_dec31_dec_sub11_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub27_dec31_dec_sub27_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub15_dec31_dec_sub15_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub20_dec31_dec_sub20_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub21_dec31_dec_sub21_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub23_dec31_dec_sub23_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub16_dec31_dec_sub16_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub18_dec31_dec_sub18_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub8_dec31_dec_sub8_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub24_dec31_dec_sub24_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub4_dec31_dec_sub4_sgl_pipe + case + assign $1\dec31_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_sgl_pipe $0\dec31_sgl_pipe[0:0] + end + connect \dec31_dec_sub4_opcode_in \opcode_in + connect \dec31_dec_sub24_opcode_in \opcode_in + connect \dec31_dec_sub8_opcode_in \opcode_in + connect \dec31_dec_sub18_opcode_in \opcode_in + connect \dec31_dec_sub16_opcode_in \opcode_in + connect \dec31_dec_sub23_opcode_in \opcode_in + connect \dec31_dec_sub21_opcode_in \opcode_in + connect \dec31_dec_sub20_opcode_in \opcode_in + connect \dec31_dec_sub15_opcode_in \opcode_in + connect \dec31_dec_sub27_opcode_in \opcode_in + connect \dec31_dec_sub11_opcode_in \opcode_in + connect \dec31_dec_sub9_opcode_in \opcode_in + connect \dec31_dec_sub22_opcode_in \opcode_in + connect \dec31_dec_sub19_opcode_in \opcode_in + connect \dec31_dec_sub26_opcode_in \opcode_in + connect \dec31_dec_sub0_opcode_in \opcode_in + connect \dec31_dec_sub28_opcode_in \opcode_in + connect \dec31_dec_sub10_opcode_in \opcode_in + connect \opc_in \opcode_switch [4:0] + connect \opcode_switch \opcode_in [10:1] +end +attribute \src "libresoc.v:82362.1-83077.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec31_dec_sub0" +attribute \generator "nMigen" +module \dec31_dec_sub0 + attribute \src "libresoc.v:82715.3-82733.6" + wire width 8 $0\dec31_dec_sub0_asmcode[7:0] + attribute \src "libresoc.v:82791.3-82809.6" + wire $0\dec31_dec_sub0_br[0:0] + attribute \src "libresoc.v:83038.3-83056.6" + wire width 3 $0\dec31_dec_sub0_cr_in[2:0] + attribute \src "libresoc.v:83057.3-83075.6" + wire width 3 $0\dec31_dec_sub0_cr_out[2:0] + attribute \src "libresoc.v:82696.3-82714.6" + wire width 2 $0\dec31_dec_sub0_cry_in[1:0] + attribute \src "libresoc.v:82772.3-82790.6" + wire $0\dec31_dec_sub0_cry_out[0:0] + attribute \src "libresoc.v:82943.3-82961.6" + wire width 5 $0\dec31_dec_sub0_form[4:0] + attribute \src "libresoc.v:82620.3-82638.6" + wire width 12 $0\dec31_dec_sub0_function_unit[11:0] + attribute \src "libresoc.v:82962.3-82980.6" + wire width 3 $0\dec31_dec_sub0_in1_sel[2:0] + attribute \src "libresoc.v:82981.3-82999.6" + wire width 4 $0\dec31_dec_sub0_in2_sel[3:0] + attribute \src "libresoc.v:83000.3-83018.6" + wire width 2 $0\dec31_dec_sub0_in3_sel[1:0] + attribute \src "libresoc.v:82829.3-82847.6" + wire width 7 $0\dec31_dec_sub0_internal_op[6:0] + attribute \src "libresoc.v:82734.3-82752.6" + wire $0\dec31_dec_sub0_inv_a[0:0] + attribute \src "libresoc.v:82753.3-82771.6" + wire $0\dec31_dec_sub0_inv_out[0:0] + attribute \src "libresoc.v:82867.3-82885.6" + wire $0\dec31_dec_sub0_is_32b[0:0] + attribute \src "libresoc.v:82639.3-82657.6" + wire width 4 $0\dec31_dec_sub0_ldst_len[3:0] + attribute \src "libresoc.v:82905.3-82923.6" + wire $0\dec31_dec_sub0_lk[0:0] + attribute \src "libresoc.v:83019.3-83037.6" + wire width 2 $0\dec31_dec_sub0_out_sel[1:0] + attribute \src "libresoc.v:82677.3-82695.6" + wire width 2 $0\dec31_dec_sub0_rc_sel[1:0] + attribute \src "libresoc.v:82848.3-82866.6" + wire $0\dec31_dec_sub0_rsrv[0:0] + attribute \src "libresoc.v:82924.3-82942.6" + wire $0\dec31_dec_sub0_sgl_pipe[0:0] + attribute \src "libresoc.v:82886.3-82904.6" + wire $0\dec31_dec_sub0_sgn[0:0] + attribute \src "libresoc.v:82810.3-82828.6" + wire $0\dec31_dec_sub0_sgn_ext[0:0] + attribute \src "libresoc.v:82658.3-82676.6" + wire width 2 $0\dec31_dec_sub0_upd[1:0] + attribute \src "libresoc.v:82363.7-82363.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:82715.3-82733.6" + wire width 8 $1\dec31_dec_sub0_asmcode[7:0] + attribute \src "libresoc.v:82791.3-82809.6" + wire $1\dec31_dec_sub0_br[0:0] + attribute \src "libresoc.v:83038.3-83056.6" + wire width 3 $1\dec31_dec_sub0_cr_in[2:0] + attribute \src "libresoc.v:83057.3-83075.6" + wire width 3 $1\dec31_dec_sub0_cr_out[2:0] + attribute \src "libresoc.v:82696.3-82714.6" + wire width 2 $1\dec31_dec_sub0_cry_in[1:0] + attribute \src "libresoc.v:82772.3-82790.6" + wire $1\dec31_dec_sub0_cry_out[0:0] + attribute \src "libresoc.v:82943.3-82961.6" + wire width 5 $1\dec31_dec_sub0_form[4:0] + attribute \src "libresoc.v:82620.3-82638.6" + wire width 12 $1\dec31_dec_sub0_function_unit[11:0] + attribute \src "libresoc.v:82962.3-82980.6" + wire width 3 $1\dec31_dec_sub0_in1_sel[2:0] + attribute \src "libresoc.v:82981.3-82999.6" + wire width 4 $1\dec31_dec_sub0_in2_sel[3:0] + attribute \src "libresoc.v:83000.3-83018.6" + wire width 2 $1\dec31_dec_sub0_in3_sel[1:0] + attribute \src "libresoc.v:82829.3-82847.6" + wire width 7 $1\dec31_dec_sub0_internal_op[6:0] + attribute \src "libresoc.v:82734.3-82752.6" + wire $1\dec31_dec_sub0_inv_a[0:0] + attribute \src "libresoc.v:82753.3-82771.6" + wire $1\dec31_dec_sub0_inv_out[0:0] + attribute \src "libresoc.v:82867.3-82885.6" + wire $1\dec31_dec_sub0_is_32b[0:0] + attribute \src "libresoc.v:82639.3-82657.6" + wire width 4 $1\dec31_dec_sub0_ldst_len[3:0] + attribute \src "libresoc.v:82905.3-82923.6" + wire $1\dec31_dec_sub0_lk[0:0] + attribute \src "libresoc.v:83019.3-83037.6" + wire width 2 $1\dec31_dec_sub0_out_sel[1:0] + attribute \src "libresoc.v:82677.3-82695.6" + wire width 2 $1\dec31_dec_sub0_rc_sel[1:0] + attribute \src "libresoc.v:82848.3-82866.6" + wire $1\dec31_dec_sub0_rsrv[0:0] + attribute \src "libresoc.v:82924.3-82942.6" + wire $1\dec31_dec_sub0_sgl_pipe[0:0] + attribute \src "libresoc.v:82886.3-82904.6" + wire $1\dec31_dec_sub0_sgn[0:0] + attribute \src "libresoc.v:82810.3-82828.6" + wire $1\dec31_dec_sub0_sgn_ext[0:0] + attribute \src "libresoc.v:82658.3-82676.6" + wire width 2 $1\dec31_dec_sub0_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 output 4 \dec31_dec_sub0_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 18 \dec31_dec_sub0_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 9 \dec31_dec_sub0_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 10 \dec31_dec_sub0_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 14 \dec31_dec_sub0_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 17 \dec31_dec_sub0_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 output 3 \dec31_dec_sub0_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \dec31_dec_sub0_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \dec31_dec_sub0_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 6 \dec31_dec_sub0_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 7 \dec31_dec_sub0_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \dec31_dec_sub0_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 15 \dec31_dec_sub0_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 16 \dec31_dec_sub0_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 21 \dec31_dec_sub0_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 11 \dec31_dec_sub0_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 23 \dec31_dec_sub0_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 8 \dec31_dec_sub0_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 13 \dec31_dec_sub0_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 20 \dec31_dec_sub0_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 24 \dec31_dec_sub0_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 22 \dec31_dec_sub0_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 19 \dec31_dec_sub0_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 12 \dec31_dec_sub0_upd + attribute \src "libresoc.v:82363.7-82363.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 5 \opcode_switch + attribute \src "libresoc.v:82363.7-82363.20" + process $proc$libresoc.v:82363$3705 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:82620.3-82638.6" + process $proc$libresoc.v:82620$3681 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_function_unit[11:0] $1\dec31_dec_sub0_function_unit[11:0] + attribute \src "libresoc.v:82621.5-82621.29" + switch \initial + attribute \src "libresoc.v:82621.9-82621.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_function_unit[11:0] 12'000001000000 + case + assign $1\dec31_dec_sub0_function_unit[11:0] 12'000000000000 + end + sync always + update \dec31_dec_sub0_function_unit $0\dec31_dec_sub0_function_unit[11:0] + end + attribute \src "libresoc.v:82639.3-82657.6" + process $proc$libresoc.v:82639$3682 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_ldst_len[3:0] $1\dec31_dec_sub0_ldst_len[3:0] + attribute \src "libresoc.v:82640.5-82640.29" + switch \initial + attribute \src "libresoc.v:82640.9-82640.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_ldst_len[3:0] 4'0000 + case + assign $1\dec31_dec_sub0_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub0_ldst_len $0\dec31_dec_sub0_ldst_len[3:0] + end + attribute \src "libresoc.v:82658.3-82676.6" + process $proc$libresoc.v:82658$3683 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_upd[1:0] $1\dec31_dec_sub0_upd[1:0] + attribute \src "libresoc.v:82659.5-82659.29" + switch \initial + attribute \src "libresoc.v:82659.9-82659.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub0_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub0_upd $0\dec31_dec_sub0_upd[1:0] + end + attribute \src "libresoc.v:82677.3-82695.6" + process $proc$libresoc.v:82677$3684 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_rc_sel[1:0] $1\dec31_dec_sub0_rc_sel[1:0] + attribute \src "libresoc.v:82678.5-82678.29" + switch \initial + attribute \src "libresoc.v:82678.9-82678.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_rc_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub0_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub0_rc_sel $0\dec31_dec_sub0_rc_sel[1:0] + end + attribute \src "libresoc.v:82696.3-82714.6" + process $proc$libresoc.v:82696$3685 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_cry_in[1:0] $1\dec31_dec_sub0_cry_in[1:0] + attribute \src "libresoc.v:82697.5-82697.29" + switch \initial + attribute \src "libresoc.v:82697.9-82697.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_cry_in[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_cry_in[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_cry_in[1:0] 2'00 + case + assign $1\dec31_dec_sub0_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub0_cry_in $0\dec31_dec_sub0_cry_in[1:0] + end + attribute \src "libresoc.v:82715.3-82733.6" + process $proc$libresoc.v:82715$3686 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_asmcode[7:0] $1\dec31_dec_sub0_asmcode[7:0] + attribute \src "libresoc.v:82716.5-82716.29" + switch \initial + attribute \src "libresoc.v:82716.9-82716.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_asmcode[7:0] 8'00011010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_asmcode[7:0] 8'00011100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_asmcode[7:0] 8'00011110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_asmcode[7:0] 8'10011011 + case + assign $1\dec31_dec_sub0_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub0_asmcode $0\dec31_dec_sub0_asmcode[7:0] + end + attribute \src "libresoc.v:82734.3-82752.6" + process $proc$libresoc.v:82734$3687 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_inv_a[0:0] $1\dec31_dec_sub0_inv_a[0:0] + attribute \src "libresoc.v:82735.5-82735.29" + switch \initial + attribute \src "libresoc.v:82735.9-82735.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub0_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub0_inv_a $0\dec31_dec_sub0_inv_a[0:0] + end + attribute \src "libresoc.v:82753.3-82771.6" + process $proc$libresoc.v:82753$3688 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_inv_out[0:0] $1\dec31_dec_sub0_inv_out[0:0] + attribute \src "libresoc.v:82754.5-82754.29" + switch \initial + attribute \src "libresoc.v:82754.9-82754.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub0_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub0_inv_out $0\dec31_dec_sub0_inv_out[0:0] + end + attribute \src "libresoc.v:82772.3-82790.6" + process $proc$libresoc.v:82772$3689 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_cry_out[0:0] $1\dec31_dec_sub0_cry_out[0:0] + attribute \src "libresoc.v:82773.5-82773.29" + switch \initial + attribute \src "libresoc.v:82773.9-82773.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_cry_out[0:0] 1'0 + case + assign $1\dec31_dec_sub0_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub0_cry_out $0\dec31_dec_sub0_cry_out[0:0] + end + attribute \src "libresoc.v:82791.3-82809.6" + process $proc$libresoc.v:82791$3690 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_br[0:0] $1\dec31_dec_sub0_br[0:0] + attribute \src "libresoc.v:82792.5-82792.29" + switch \initial + attribute \src "libresoc.v:82792.9-82792.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_br[0:0] 1'0 + case + assign $1\dec31_dec_sub0_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub0_br $0\dec31_dec_sub0_br[0:0] + end + attribute \src "libresoc.v:82810.3-82828.6" + process $proc$libresoc.v:82810$3691 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_sgn_ext[0:0] $1\dec31_dec_sub0_sgn_ext[0:0] + attribute \src "libresoc.v:82811.5-82811.29" + switch \initial + attribute \src "libresoc.v:82811.9-82811.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub0_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub0_sgn_ext $0\dec31_dec_sub0_sgn_ext[0:0] + end + attribute \src "libresoc.v:82829.3-82847.6" + process $proc$libresoc.v:82829$3692 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_internal_op[6:0] $1\dec31_dec_sub0_internal_op[6:0] + attribute \src "libresoc.v:82830.5-82830.29" + switch \initial + attribute \src "libresoc.v:82830.9-82830.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_internal_op[6:0] 7'0001010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_internal_op[6:0] 7'0001100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_internal_op[6:0] 7'0001010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_internal_op[6:0] 7'0111011 + case + assign $1\dec31_dec_sub0_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub0_internal_op $0\dec31_dec_sub0_internal_op[6:0] + end + attribute \src "libresoc.v:82848.3-82866.6" + process $proc$libresoc.v:82848$3693 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_rsrv[0:0] $1\dec31_dec_sub0_rsrv[0:0] + attribute \src "libresoc.v:82849.5-82849.29" + switch \initial + attribute \src "libresoc.v:82849.9-82849.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub0_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub0_rsrv $0\dec31_dec_sub0_rsrv[0:0] + end + attribute \src "libresoc.v:82867.3-82885.6" + process $proc$libresoc.v:82867$3694 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_is_32b[0:0] $1\dec31_dec_sub0_is_32b[0:0] + attribute \src "libresoc.v:82868.5-82868.29" + switch \initial + attribute \src "libresoc.v:82868.9-82868.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_is_32b[0:0] 1'0 + case + assign $1\dec31_dec_sub0_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub0_is_32b $0\dec31_dec_sub0_is_32b[0:0] + end + attribute \src "libresoc.v:82886.3-82904.6" + process $proc$libresoc.v:82886$3695 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_sgn[0:0] $1\dec31_dec_sub0_sgn[0:0] + attribute \src "libresoc.v:82887.5-82887.29" + switch \initial + attribute \src "libresoc.v:82887.9-82887.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_sgn[0:0] 1'0 + case + assign $1\dec31_dec_sub0_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub0_sgn $0\dec31_dec_sub0_sgn[0:0] + end + attribute \src "libresoc.v:82905.3-82923.6" + process $proc$libresoc.v:82905$3696 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_lk[0:0] $1\dec31_dec_sub0_lk[0:0] + attribute \src "libresoc.v:82906.5-82906.29" + switch \initial + attribute \src "libresoc.v:82906.9-82906.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub0_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub0_lk $0\dec31_dec_sub0_lk[0:0] + end + attribute \src "libresoc.v:82924.3-82942.6" + process $proc$libresoc.v:82924$3697 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_sgl_pipe[0:0] $1\dec31_dec_sub0_sgl_pipe[0:0] + attribute \src "libresoc.v:82925.5-82925.29" + switch \initial + attribute \src "libresoc.v:82925.9-82925.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_sgl_pipe[0:0] 1'0 + case + assign $1\dec31_dec_sub0_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub0_sgl_pipe $0\dec31_dec_sub0_sgl_pipe[0:0] + end + attribute \src "libresoc.v:82943.3-82961.6" + process $proc$libresoc.v:82943$3698 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_form[4:0] $1\dec31_dec_sub0_form[4:0] + attribute \src "libresoc.v:82944.5-82944.29" + switch \initial + attribute \src "libresoc.v:82944.9-82944.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_form[4:0] 5'11000 + case + assign $1\dec31_dec_sub0_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub0_form $0\dec31_dec_sub0_form[4:0] + end + attribute \src "libresoc.v:82962.3-82980.6" + process $proc$libresoc.v:82962$3699 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_in1_sel[2:0] $1\dec31_dec_sub0_in1_sel[2:0] + attribute \src "libresoc.v:82963.5-82963.29" + switch \initial + attribute \src "libresoc.v:82963.9-82963.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_in1_sel[2:0] 3'000 + case + assign $1\dec31_dec_sub0_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub0_in1_sel $0\dec31_dec_sub0_in1_sel[2:0] + end + attribute \src "libresoc.v:82981.3-82999.6" + process $proc$libresoc.v:82981$3700 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_in2_sel[3:0] $1\dec31_dec_sub0_in2_sel[3:0] + attribute \src "libresoc.v:82982.5-82982.29" + switch \initial + attribute \src "libresoc.v:82982.9-82982.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_in2_sel[3:0] 4'0000 + case + assign $1\dec31_dec_sub0_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub0_in2_sel $0\dec31_dec_sub0_in2_sel[3:0] + end + attribute \src "libresoc.v:83000.3-83018.6" + process $proc$libresoc.v:83000$3701 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_in3_sel[1:0] $1\dec31_dec_sub0_in3_sel[1:0] + attribute \src "libresoc.v:83001.5-83001.29" + switch \initial + attribute \src "libresoc.v:83001.9-83001.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_in3_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub0_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub0_in3_sel $0\dec31_dec_sub0_in3_sel[1:0] + end + attribute \src "libresoc.v:83019.3-83037.6" + process $proc$libresoc.v:83019$3702 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_out_sel[1:0] $1\dec31_dec_sub0_out_sel[1:0] + attribute \src "libresoc.v:83020.5-83020.29" + switch \initial + attribute \src "libresoc.v:83020.9-83020.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_out_sel[1:0] 2'01 + case + assign $1\dec31_dec_sub0_out_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub0_out_sel $0\dec31_dec_sub0_out_sel[1:0] + end + attribute \src "libresoc.v:83038.3-83056.6" + process $proc$libresoc.v:83038$3703 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_cr_in[2:0] $1\dec31_dec_sub0_cr_in[2:0] + attribute \src "libresoc.v:83039.5-83039.29" + switch \initial + attribute \src "libresoc.v:83039.9-83039.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_cr_in[2:0] 3'011 + case + assign $1\dec31_dec_sub0_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub0_cr_in $0\dec31_dec_sub0_cr_in[2:0] + end + attribute \src "libresoc.v:83057.3-83075.6" + process $proc$libresoc.v:83057$3704 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_cr_out[2:0] $1\dec31_dec_sub0_cr_out[2:0] + attribute \src "libresoc.v:83058.5-83058.29" + switch \initial + attribute \src "libresoc.v:83058.9-83058.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_cr_out[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_cr_out[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_cr_out[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_cr_out[2:0] 3'000 + case + assign $1\dec31_dec_sub0_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub0_cr_out $0\dec31_dec_sub0_cr_out[2:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:83081.1-84228.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec31_dec_sub10" +attribute \generator "nMigen" +module \dec31_dec_sub10 + attribute \src "libresoc.v:83524.3-83560.6" + wire width 8 $0\dec31_dec_sub10_asmcode[7:0] + attribute \src "libresoc.v:83672.3-83708.6" + wire $0\dec31_dec_sub10_br[0:0] + attribute \src "libresoc.v:84153.3-84189.6" + wire width 3 $0\dec31_dec_sub10_cr_in[2:0] + attribute \src "libresoc.v:84190.3-84226.6" + wire width 3 $0\dec31_dec_sub10_cr_out[2:0] + attribute \src "libresoc.v:83487.3-83523.6" + wire width 2 $0\dec31_dec_sub10_cry_in[1:0] + attribute \src "libresoc.v:83635.3-83671.6" + wire $0\dec31_dec_sub10_cry_out[0:0] + attribute \src "libresoc.v:83968.3-84004.6" + wire width 5 $0\dec31_dec_sub10_form[4:0] + attribute \src "libresoc.v:83339.3-83375.6" + wire width 12 $0\dec31_dec_sub10_function_unit[11:0] + attribute \src "libresoc.v:84005.3-84041.6" + wire width 3 $0\dec31_dec_sub10_in1_sel[2:0] + attribute \src "libresoc.v:84042.3-84078.6" + wire width 4 $0\dec31_dec_sub10_in2_sel[3:0] + attribute \src "libresoc.v:84079.3-84115.6" + wire width 2 $0\dec31_dec_sub10_in3_sel[1:0] + attribute \src "libresoc.v:83746.3-83782.6" + wire width 7 $0\dec31_dec_sub10_internal_op[6:0] + attribute \src "libresoc.v:83561.3-83597.6" + wire $0\dec31_dec_sub10_inv_a[0:0] + attribute \src "libresoc.v:83598.3-83634.6" + wire $0\dec31_dec_sub10_inv_out[0:0] + attribute \src "libresoc.v:83820.3-83856.6" + wire $0\dec31_dec_sub10_is_32b[0:0] + attribute \src "libresoc.v:83376.3-83412.6" + wire width 4 $0\dec31_dec_sub10_ldst_len[3:0] + attribute \src "libresoc.v:83894.3-83930.6" + wire $0\dec31_dec_sub10_lk[0:0] + attribute \src "libresoc.v:84116.3-84152.6" + wire width 2 $0\dec31_dec_sub10_out_sel[1:0] + attribute \src "libresoc.v:83450.3-83486.6" + wire width 2 $0\dec31_dec_sub10_rc_sel[1:0] + attribute \src "libresoc.v:83783.3-83819.6" + wire $0\dec31_dec_sub10_rsrv[0:0] + attribute \src "libresoc.v:83931.3-83967.6" + wire $0\dec31_dec_sub10_sgl_pipe[0:0] + attribute \src "libresoc.v:83857.3-83893.6" + wire $0\dec31_dec_sub10_sgn[0:0] + attribute \src "libresoc.v:83709.3-83745.6" + wire $0\dec31_dec_sub10_sgn_ext[0:0] + attribute \src "libresoc.v:83413.3-83449.6" + wire width 2 $0\dec31_dec_sub10_upd[1:0] + attribute \src "libresoc.v:83082.7-83082.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:83524.3-83560.6" + wire width 8 $1\dec31_dec_sub10_asmcode[7:0] + attribute \src "libresoc.v:83672.3-83708.6" + wire $1\dec31_dec_sub10_br[0:0] + attribute \src "libresoc.v:84153.3-84189.6" + wire width 3 $1\dec31_dec_sub10_cr_in[2:0] + attribute \src "libresoc.v:84190.3-84226.6" + wire width 3 $1\dec31_dec_sub10_cr_out[2:0] + attribute \src "libresoc.v:83487.3-83523.6" + wire width 2 $1\dec31_dec_sub10_cry_in[1:0] + attribute \src "libresoc.v:83635.3-83671.6" + wire $1\dec31_dec_sub10_cry_out[0:0] + attribute \src "libresoc.v:83968.3-84004.6" + wire width 5 $1\dec31_dec_sub10_form[4:0] + attribute \src "libresoc.v:83339.3-83375.6" + wire width 12 $1\dec31_dec_sub10_function_unit[11:0] + attribute \src "libresoc.v:84005.3-84041.6" + wire width 3 $1\dec31_dec_sub10_in1_sel[2:0] + attribute \src "libresoc.v:84042.3-84078.6" + wire width 4 $1\dec31_dec_sub10_in2_sel[3:0] + attribute \src "libresoc.v:84079.3-84115.6" + wire width 2 $1\dec31_dec_sub10_in3_sel[1:0] + attribute \src "libresoc.v:83746.3-83782.6" + wire width 7 $1\dec31_dec_sub10_internal_op[6:0] + attribute \src "libresoc.v:83561.3-83597.6" + wire $1\dec31_dec_sub10_inv_a[0:0] + attribute \src "libresoc.v:83598.3-83634.6" + wire $1\dec31_dec_sub10_inv_out[0:0] + attribute \src "libresoc.v:83820.3-83856.6" + wire $1\dec31_dec_sub10_is_32b[0:0] + attribute \src "libresoc.v:83376.3-83412.6" + wire width 4 $1\dec31_dec_sub10_ldst_len[3:0] + attribute \src "libresoc.v:83894.3-83930.6" + wire $1\dec31_dec_sub10_lk[0:0] + attribute \src "libresoc.v:84116.3-84152.6" + wire width 2 $1\dec31_dec_sub10_out_sel[1:0] + attribute \src "libresoc.v:83450.3-83486.6" + wire width 2 $1\dec31_dec_sub10_rc_sel[1:0] + attribute \src "libresoc.v:83783.3-83819.6" + wire $1\dec31_dec_sub10_rsrv[0:0] + attribute \src "libresoc.v:83931.3-83967.6" + wire $1\dec31_dec_sub10_sgl_pipe[0:0] + attribute \src "libresoc.v:83857.3-83893.6" + wire $1\dec31_dec_sub10_sgn[0:0] + attribute \src "libresoc.v:83709.3-83745.6" + wire $1\dec31_dec_sub10_sgn_ext[0:0] + attribute \src "libresoc.v:83413.3-83449.6" + wire width 2 $1\dec31_dec_sub10_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 output 4 \dec31_dec_sub10_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 18 \dec31_dec_sub10_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 9 \dec31_dec_sub10_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 10 \dec31_dec_sub10_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 14 \dec31_dec_sub10_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 17 \dec31_dec_sub10_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 output 3 \dec31_dec_sub10_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \dec31_dec_sub10_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \dec31_dec_sub10_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 6 \dec31_dec_sub10_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 7 \dec31_dec_sub10_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \dec31_dec_sub10_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 15 \dec31_dec_sub10_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 16 \dec31_dec_sub10_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 21 \dec31_dec_sub10_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 11 \dec31_dec_sub10_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 23 \dec31_dec_sub10_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 8 \dec31_dec_sub10_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 13 \dec31_dec_sub10_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 20 \dec31_dec_sub10_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 24 \dec31_dec_sub10_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 22 \dec31_dec_sub10_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 19 \dec31_dec_sub10_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 12 \dec31_dec_sub10_upd + attribute \src "libresoc.v:83082.7-83082.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 5 \opcode_switch + attribute \src "libresoc.v:83082.7-83082.20" + process $proc$libresoc.v:83082$3730 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:83339.3-83375.6" + process $proc$libresoc.v:83339$3706 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_function_unit[11:0] $1\dec31_dec_sub10_function_unit[11:0] + attribute \src "libresoc.v:83340.5-83340.29" + switch \initial + attribute \src "libresoc.v:83340.9-83340.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000010 + case + assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000000 + end + sync always + update \dec31_dec_sub10_function_unit $0\dec31_dec_sub10_function_unit[11:0] + end + attribute \src "libresoc.v:83376.3-83412.6" + process $proc$libresoc.v:83376$3707 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_ldst_len[3:0] $1\dec31_dec_sub10_ldst_len[3:0] + attribute \src "libresoc.v:83377.5-83377.29" + switch \initial + attribute \src "libresoc.v:83377.9-83377.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 + case + assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub10_ldst_len $0\dec31_dec_sub10_ldst_len[3:0] + end + attribute \src "libresoc.v:83413.3-83449.6" + process $proc$libresoc.v:83413$3708 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_upd[1:0] $1\dec31_dec_sub10_upd[1:0] + attribute \src "libresoc.v:83414.5-83414.29" + switch \initial + attribute \src "libresoc.v:83414.9-83414.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub10_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub10_upd $0\dec31_dec_sub10_upd[1:0] + end + attribute \src "libresoc.v:83450.3-83486.6" + process $proc$libresoc.v:83450$3709 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_rc_sel[1:0] $1\dec31_dec_sub10_rc_sel[1:0] + attribute \src "libresoc.v:83451.5-83451.29" + switch \initial + attribute \src "libresoc.v:83451.9-83451.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 + case + assign $1\dec31_dec_sub10_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub10_rc_sel $0\dec31_dec_sub10_rc_sel[1:0] + end + attribute \src "libresoc.v:83487.3-83523.6" + process $proc$libresoc.v:83487$3710 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_cry_in[1:0] $1\dec31_dec_sub10_cry_in[1:0] + attribute \src "libresoc.v:83488.5-83488.29" + switch \initial + attribute \src "libresoc.v:83488.9-83488.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_cry_in[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_cry_in[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_cry_in[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_cry_in[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_cry_in[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_cry_in[1:0] 2'10 + case + assign $1\dec31_dec_sub10_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub10_cry_in $0\dec31_dec_sub10_cry_in[1:0] + end + attribute \src "libresoc.v:83524.3-83560.6" + process $proc$libresoc.v:83524$3711 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_asmcode[7:0] $1\dec31_dec_sub10_asmcode[7:0] + attribute \src "libresoc.v:83525.5-83525.29" + switch \initial + attribute \src "libresoc.v:83525.9-83525.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_asmcode[7:0] 8'00000001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_asmcode[7:0] 8'00001100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_asmcode[7:0] 8'00000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_asmcode[7:0] 8'00000011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_asmcode[7:0] 8'00000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_asmcode[7:0] 8'00000101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_asmcode[7:0] 8'00001010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_asmcode[7:0] 8'00001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_asmcode[7:0] 8'00001101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_asmcode[7:0] 8'00001110 + case + assign $1\dec31_dec_sub10_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub10_asmcode $0\dec31_dec_sub10_asmcode[7:0] + end + attribute \src "libresoc.v:83561.3-83597.6" + process $proc$libresoc.v:83561$3712 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_inv_a[0:0] $1\dec31_dec_sub10_inv_a[0:0] + attribute \src "libresoc.v:83562.5-83562.29" + switch \initial + attribute \src "libresoc.v:83562.9-83562.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub10_inv_a $0\dec31_dec_sub10_inv_a[0:0] + end + attribute \src "libresoc.v:83598.3-83634.6" + process $proc$libresoc.v:83598$3713 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_inv_out[0:0] $1\dec31_dec_sub10_inv_out[0:0] + attribute \src "libresoc.v:83599.5-83599.29" + switch \initial + attribute \src "libresoc.v:83599.9-83599.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub10_inv_out $0\dec31_dec_sub10_inv_out[0:0] + end + attribute \src "libresoc.v:83635.3-83671.6" + process $proc$libresoc.v:83635$3714 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_cry_out[0:0] $1\dec31_dec_sub10_cry_out[0:0] + attribute \src "libresoc.v:83636.5-83636.29" + switch \initial + attribute \src "libresoc.v:83636.9-83636.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_cry_out[0:0] 1'1 + case + assign $1\dec31_dec_sub10_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub10_cry_out $0\dec31_dec_sub10_cry_out[0:0] + end + attribute \src "libresoc.v:83672.3-83708.6" + process $proc$libresoc.v:83672$3715 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_br[0:0] $1\dec31_dec_sub10_br[0:0] + attribute \src "libresoc.v:83673.5-83673.29" + switch \initial + attribute \src "libresoc.v:83673.9-83673.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_br[0:0] 1'0 + case + assign $1\dec31_dec_sub10_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub10_br $0\dec31_dec_sub10_br[0:0] + end + attribute \src "libresoc.v:83709.3-83745.6" + process $proc$libresoc.v:83709$3716 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_sgn_ext[0:0] $1\dec31_dec_sub10_sgn_ext[0:0] + attribute \src "libresoc.v:83710.5-83710.29" + switch \initial + attribute \src "libresoc.v:83710.9-83710.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub10_sgn_ext $0\dec31_dec_sub10_sgn_ext[0:0] + end + attribute \src "libresoc.v:83746.3-83782.6" + process $proc$libresoc.v:83746$3717 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_internal_op[6:0] $1\dec31_dec_sub10_internal_op[6:0] + attribute \src "libresoc.v:83747.5-83747.29" + switch \initial + attribute \src "libresoc.v:83747.9-83747.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 + case + assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub10_internal_op $0\dec31_dec_sub10_internal_op[6:0] + end + attribute \src "libresoc.v:83783.3-83819.6" + process $proc$libresoc.v:83783$3718 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_rsrv[0:0] $1\dec31_dec_sub10_rsrv[0:0] + attribute \src "libresoc.v:83784.5-83784.29" + switch \initial + attribute \src "libresoc.v:83784.9-83784.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub10_rsrv $0\dec31_dec_sub10_rsrv[0:0] + end + attribute \src "libresoc.v:83820.3-83856.6" + process $proc$libresoc.v:83820$3719 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_is_32b[0:0] $1\dec31_dec_sub10_is_32b[0:0] + attribute \src "libresoc.v:83821.5-83821.29" + switch \initial + attribute \src "libresoc.v:83821.9-83821.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 + case + assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub10_is_32b $0\dec31_dec_sub10_is_32b[0:0] + end + attribute \src "libresoc.v:83857.3-83893.6" + process $proc$libresoc.v:83857$3720 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_sgn[0:0] $1\dec31_dec_sub10_sgn[0:0] + attribute \src "libresoc.v:83858.5-83858.29" + switch \initial + attribute \src "libresoc.v:83858.9-83858.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_sgn[0:0] 1'0 + case + assign $1\dec31_dec_sub10_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub10_sgn $0\dec31_dec_sub10_sgn[0:0] + end + attribute \src "libresoc.v:83894.3-83930.6" + process $proc$libresoc.v:83894$3721 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_lk[0:0] $1\dec31_dec_sub10_lk[0:0] + attribute \src "libresoc.v:83895.5-83895.29" + switch \initial + attribute \src "libresoc.v:83895.9-83895.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub10_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub10_lk $0\dec31_dec_sub10_lk[0:0] + end + attribute \src "libresoc.v:83931.3-83967.6" + process $proc$libresoc.v:83931$3722 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_sgl_pipe[0:0] $1\dec31_dec_sub10_sgl_pipe[0:0] + attribute \src "libresoc.v:83932.5-83932.29" + switch \initial + attribute \src "libresoc.v:83932.9-83932.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 + case + assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub10_sgl_pipe $0\dec31_dec_sub10_sgl_pipe[0:0] + end + attribute \src "libresoc.v:83968.3-84004.6" + process $proc$libresoc.v:83968$3723 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_form[4:0] $1\dec31_dec_sub10_form[4:0] + attribute \src "libresoc.v:83969.5-83969.29" + switch \initial + attribute \src "libresoc.v:83969.9-83969.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_form[4:0] 5'10001 + case + assign $1\dec31_dec_sub10_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub10_form $0\dec31_dec_sub10_form[4:0] + end + attribute \src "libresoc.v:84005.3-84041.6" + process $proc$libresoc.v:84005$3724 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_in1_sel[2:0] $1\dec31_dec_sub10_in1_sel[2:0] + attribute \src "libresoc.v:84006.5-84006.29" + switch \initial + attribute \src "libresoc.v:84006.9-84006.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 + case + assign $1\dec31_dec_sub10_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub10_in1_sel $0\dec31_dec_sub10_in1_sel[2:0] + end + attribute \src "libresoc.v:84042.3-84078.6" + process $proc$libresoc.v:84042$3725 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_in2_sel[3:0] $1\dec31_dec_sub10_in2_sel[3:0] + attribute \src "libresoc.v:84043.5-84043.29" + switch \initial + attribute \src "libresoc.v:84043.9-84043.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_in2_sel[3:0] 4'1001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_in2_sel[3:0] 4'1001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0000 + case + assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub10_in2_sel $0\dec31_dec_sub10_in2_sel[3:0] + end + attribute \src "libresoc.v:84079.3-84115.6" + process $proc$libresoc.v:84079$3726 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_in3_sel[1:0] $1\dec31_dec_sub10_in3_sel[1:0] + attribute \src "libresoc.v:84080.5-84080.29" + switch \initial + attribute \src "libresoc.v:84080.9-84080.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub10_in3_sel $0\dec31_dec_sub10_in3_sel[1:0] + end + attribute \src "libresoc.v:84116.3-84152.6" + process $proc$libresoc.v:84116$3727 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_out_sel[1:0] $1\dec31_dec_sub10_out_sel[1:0] + attribute \src "libresoc.v:84117.5-84117.29" + switch \initial + attribute \src "libresoc.v:84117.9-84117.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 + case + assign $1\dec31_dec_sub10_out_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub10_out_sel $0\dec31_dec_sub10_out_sel[1:0] + end + attribute \src "libresoc.v:84153.3-84189.6" + process $proc$libresoc.v:84153$3728 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_cr_in[2:0] $1\dec31_dec_sub10_cr_in[2:0] + attribute \src "libresoc.v:84154.5-84154.29" + switch \initial + attribute \src "libresoc.v:84154.9-84154.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub10_cr_in $0\dec31_dec_sub10_cr_in[2:0] + end + attribute \src "libresoc.v:84190.3-84226.6" + process $proc$libresoc.v:84190$3729 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_cr_out[2:0] $1\dec31_dec_sub10_cr_out[2:0] + attribute \src "libresoc.v:84191.5-84191.29" + switch \initial + attribute \src "libresoc.v:84191.9-84191.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 + case + assign $1\dec31_dec_sub10_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub10_cr_out $0\dec31_dec_sub10_cr_out[2:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:84232.1-85811.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec31_dec_sub11" +attribute \generator "nMigen" +module \dec31_dec_sub11 + attribute \src "libresoc.v:84765.3-84819.6" + wire width 8 $0\dec31_dec_sub11_asmcode[7:0] + attribute \src "libresoc.v:84985.3-85039.6" + wire $0\dec31_dec_sub11_br[0:0] + attribute \src "libresoc.v:85700.3-85754.6" + wire width 3 $0\dec31_dec_sub11_cr_in[2:0] + attribute \src "libresoc.v:85755.3-85809.6" + wire width 3 $0\dec31_dec_sub11_cr_out[2:0] + attribute \src "libresoc.v:84710.3-84764.6" + wire width 2 $0\dec31_dec_sub11_cry_in[1:0] + attribute \src "libresoc.v:84930.3-84984.6" + wire $0\dec31_dec_sub11_cry_out[0:0] + attribute \src "libresoc.v:85425.3-85479.6" + wire width 5 $0\dec31_dec_sub11_form[4:0] + attribute \src "libresoc.v:84490.3-84544.6" + wire width 12 $0\dec31_dec_sub11_function_unit[11:0] + attribute \src "libresoc.v:85480.3-85534.6" + wire width 3 $0\dec31_dec_sub11_in1_sel[2:0] + attribute \src "libresoc.v:85535.3-85589.6" + wire width 4 $0\dec31_dec_sub11_in2_sel[3:0] + attribute \src "libresoc.v:85590.3-85644.6" + wire width 2 $0\dec31_dec_sub11_in3_sel[1:0] + attribute \src "libresoc.v:85095.3-85149.6" + wire width 7 $0\dec31_dec_sub11_internal_op[6:0] + attribute \src "libresoc.v:84820.3-84874.6" + wire $0\dec31_dec_sub11_inv_a[0:0] + attribute \src "libresoc.v:84875.3-84929.6" + wire $0\dec31_dec_sub11_inv_out[0:0] + attribute \src "libresoc.v:85205.3-85259.6" + wire $0\dec31_dec_sub11_is_32b[0:0] + attribute \src "libresoc.v:84545.3-84599.6" + wire width 4 $0\dec31_dec_sub11_ldst_len[3:0] + attribute \src "libresoc.v:85315.3-85369.6" + wire $0\dec31_dec_sub11_lk[0:0] + attribute \src "libresoc.v:85645.3-85699.6" + wire width 2 $0\dec31_dec_sub11_out_sel[1:0] + attribute \src "libresoc.v:84655.3-84709.6" + wire width 2 $0\dec31_dec_sub11_rc_sel[1:0] + attribute \src "libresoc.v:85150.3-85204.6" + wire $0\dec31_dec_sub11_rsrv[0:0] + attribute \src "libresoc.v:85370.3-85424.6" + wire $0\dec31_dec_sub11_sgl_pipe[0:0] + attribute \src "libresoc.v:85260.3-85314.6" + wire $0\dec31_dec_sub11_sgn[0:0] + attribute \src "libresoc.v:85040.3-85094.6" + wire $0\dec31_dec_sub11_sgn_ext[0:0] + attribute \src "libresoc.v:84600.3-84654.6" + wire width 2 $0\dec31_dec_sub11_upd[1:0] + attribute \src "libresoc.v:84233.7-84233.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:84765.3-84819.6" + wire width 8 $1\dec31_dec_sub11_asmcode[7:0] + attribute \src "libresoc.v:84985.3-85039.6" + wire $1\dec31_dec_sub11_br[0:0] + attribute \src "libresoc.v:85700.3-85754.6" + wire width 3 $1\dec31_dec_sub11_cr_in[2:0] + attribute \src "libresoc.v:85755.3-85809.6" + wire width 3 $1\dec31_dec_sub11_cr_out[2:0] + attribute \src "libresoc.v:84710.3-84764.6" + wire width 2 $1\dec31_dec_sub11_cry_in[1:0] + attribute \src "libresoc.v:84930.3-84984.6" + wire $1\dec31_dec_sub11_cry_out[0:0] + attribute \src "libresoc.v:85425.3-85479.6" + wire width 5 $1\dec31_dec_sub11_form[4:0] + attribute \src "libresoc.v:84490.3-84544.6" + wire width 12 $1\dec31_dec_sub11_function_unit[11:0] + attribute \src "libresoc.v:85480.3-85534.6" + wire width 3 $1\dec31_dec_sub11_in1_sel[2:0] + attribute \src "libresoc.v:85535.3-85589.6" + wire width 4 $1\dec31_dec_sub11_in2_sel[3:0] + attribute \src "libresoc.v:85590.3-85644.6" + wire width 2 $1\dec31_dec_sub11_in3_sel[1:0] + attribute \src "libresoc.v:85095.3-85149.6" + wire width 7 $1\dec31_dec_sub11_internal_op[6:0] + attribute \src "libresoc.v:84820.3-84874.6" + wire $1\dec31_dec_sub11_inv_a[0:0] + attribute \src "libresoc.v:84875.3-84929.6" + wire $1\dec31_dec_sub11_inv_out[0:0] + attribute \src "libresoc.v:85205.3-85259.6" + wire $1\dec31_dec_sub11_is_32b[0:0] + attribute \src "libresoc.v:84545.3-84599.6" + wire width 4 $1\dec31_dec_sub11_ldst_len[3:0] + attribute \src "libresoc.v:85315.3-85369.6" + wire $1\dec31_dec_sub11_lk[0:0] + attribute \src "libresoc.v:85645.3-85699.6" + wire width 2 $1\dec31_dec_sub11_out_sel[1:0] + attribute \src "libresoc.v:84655.3-84709.6" + wire width 2 $1\dec31_dec_sub11_rc_sel[1:0] + attribute \src "libresoc.v:85150.3-85204.6" + wire $1\dec31_dec_sub11_rsrv[0:0] + attribute \src "libresoc.v:85370.3-85424.6" + wire $1\dec31_dec_sub11_sgl_pipe[0:0] + attribute \src "libresoc.v:85260.3-85314.6" + wire $1\dec31_dec_sub11_sgn[0:0] + attribute \src "libresoc.v:85040.3-85094.6" + wire $1\dec31_dec_sub11_sgn_ext[0:0] + attribute \src "libresoc.v:84600.3-84654.6" + wire width 2 $1\dec31_dec_sub11_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 output 4 \dec31_dec_sub11_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 18 \dec31_dec_sub11_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 9 \dec31_dec_sub11_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 10 \dec31_dec_sub11_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 14 \dec31_dec_sub11_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 17 \dec31_dec_sub11_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 output 3 \dec31_dec_sub11_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \dec31_dec_sub11_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \dec31_dec_sub11_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 6 \dec31_dec_sub11_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 7 \dec31_dec_sub11_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \dec31_dec_sub11_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 15 \dec31_dec_sub11_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 16 \dec31_dec_sub11_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 21 \dec31_dec_sub11_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 11 \dec31_dec_sub11_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 23 \dec31_dec_sub11_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 8 \dec31_dec_sub11_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 13 \dec31_dec_sub11_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 20 \dec31_dec_sub11_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 24 \dec31_dec_sub11_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 22 \dec31_dec_sub11_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 19 \dec31_dec_sub11_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 12 \dec31_dec_sub11_upd + attribute \src "libresoc.v:84233.7-84233.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 5 \opcode_switch + attribute \src "libresoc.v:84233.7-84233.20" + process $proc$libresoc.v:84233$3755 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:84490.3-84544.6" + process $proc$libresoc.v:84490$3731 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_function_unit[11:0] $1\dec31_dec_sub11_function_unit[11:0] + attribute \src "libresoc.v:84491.5-84491.29" + switch \initial + attribute \src "libresoc.v:84491.9-84491.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[11:0] 12'000100000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[11:0] 12'000100000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[11:0] 12'000100000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[11:0] 12'000100000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[11:0] 12'000100000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[11:0] 12'000100000000 + case + assign $1\dec31_dec_sub11_function_unit[11:0] 12'000000000000 + end + sync always + update \dec31_dec_sub11_function_unit $0\dec31_dec_sub11_function_unit[11:0] + end + attribute \src "libresoc.v:84545.3-84599.6" + process $proc$libresoc.v:84545$3732 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_ldst_len[3:0] $1\dec31_dec_sub11_ldst_len[3:0] + attribute \src "libresoc.v:84546.5-84546.29" + switch \initial + attribute \src "libresoc.v:84546.9-84546.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + case + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub11_ldst_len $0\dec31_dec_sub11_ldst_len[3:0] + end + attribute \src "libresoc.v:84600.3-84654.6" + process $proc$libresoc.v:84600$3733 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_upd[1:0] $1\dec31_dec_sub11_upd[1:0] + attribute \src "libresoc.v:84601.5-84601.29" + switch \initial + attribute \src "libresoc.v:84601.9-84601.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub11_upd $0\dec31_dec_sub11_upd[1:0] + end + attribute \src "libresoc.v:84655.3-84709.6" + process $proc$libresoc.v:84655$3734 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_rc_sel[1:0] $1\dec31_dec_sub11_rc_sel[1:0] + attribute \src "libresoc.v:84656.5-84656.29" + switch \initial + attribute \src "libresoc.v:84656.9-84656.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + case + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub11_rc_sel $0\dec31_dec_sub11_rc_sel[1:0] + end + attribute \src "libresoc.v:84710.3-84764.6" + process $proc$libresoc.v:84710$3735 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_cry_in[1:0] $1\dec31_dec_sub11_cry_in[1:0] + attribute \src "libresoc.v:84711.5-84711.29" + switch \initial + attribute \src "libresoc.v:84711.9-84711.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + case + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub11_cry_in $0\dec31_dec_sub11_cry_in[1:0] + end + attribute \src "libresoc.v:84765.3-84819.6" + process $proc$libresoc.v:84765$3736 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_asmcode[7:0] $1\dec31_dec_sub11_asmcode[7:0] + attribute \src "libresoc.v:84766.5-84766.29" + switch \initial + attribute \src "libresoc.v:84766.9-84766.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'00111110 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'00111111 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'00111100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'00111101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'01000001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'01000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'00111011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'01000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'01110101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'01110011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'01111100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'01111101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'01111100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'01111101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'10000001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'10000010 + case + assign $1\dec31_dec_sub11_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub11_asmcode $0\dec31_dec_sub11_asmcode[7:0] + end + attribute \src "libresoc.v:84820.3-84874.6" + process $proc$libresoc.v:84820$3737 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_inv_a[0:0] $1\dec31_dec_sub11_inv_a[0:0] + attribute \src "libresoc.v:84821.5-84821.29" + switch \initial + attribute \src "libresoc.v:84821.9-84821.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub11_inv_a $0\dec31_dec_sub11_inv_a[0:0] + end + attribute \src "libresoc.v:84875.3-84929.6" + process $proc$libresoc.v:84875$3738 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_inv_out[0:0] $1\dec31_dec_sub11_inv_out[0:0] + attribute \src "libresoc.v:84876.5-84876.29" + switch \initial + attribute \src "libresoc.v:84876.9-84876.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub11_inv_out $0\dec31_dec_sub11_inv_out[0:0] + end + attribute \src "libresoc.v:84930.3-84984.6" + process $proc$libresoc.v:84930$3739 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_cry_out[0:0] $1\dec31_dec_sub11_cry_out[0:0] + attribute \src "libresoc.v:84931.5-84931.29" + switch \initial + attribute \src "libresoc.v:84931.9-84931.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + case + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub11_cry_out $0\dec31_dec_sub11_cry_out[0:0] + end + attribute \src "libresoc.v:84985.3-85039.6" + process $proc$libresoc.v:84985$3740 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_br[0:0] $1\dec31_dec_sub11_br[0:0] + attribute \src "libresoc.v:84986.5-84986.29" + switch \initial + attribute \src "libresoc.v:84986.9-84986.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + case + assign $1\dec31_dec_sub11_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub11_br $0\dec31_dec_sub11_br[0:0] + end + attribute \src "libresoc.v:85040.3-85094.6" + process $proc$libresoc.v:85040$3741 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_sgn_ext[0:0] $1\dec31_dec_sub11_sgn_ext[0:0] + attribute \src "libresoc.v:85041.5-85041.29" + switch \initial + attribute \src "libresoc.v:85041.9-85041.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub11_sgn_ext $0\dec31_dec_sub11_sgn_ext[0:0] + end + attribute \src "libresoc.v:85095.3-85149.6" + process $proc$libresoc.v:85095$3742 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_internal_op[6:0] $1\dec31_dec_sub11_internal_op[6:0] + attribute \src "libresoc.v:85096.5-85096.29" + switch \initial + attribute \src "libresoc.v:85096.9-85096.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011110 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011110 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011110 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011110 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0101111 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0101111 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0110100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0110100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0110100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0110100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0110010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0110010 + case + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub11_internal_op $0\dec31_dec_sub11_internal_op[6:0] + end + attribute \src "libresoc.v:85150.3-85204.6" + process $proc$libresoc.v:85150$3743 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_rsrv[0:0] $1\dec31_dec_sub11_rsrv[0:0] + attribute \src "libresoc.v:85151.5-85151.29" + switch \initial + attribute \src "libresoc.v:85151.9-85151.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub11_rsrv $0\dec31_dec_sub11_rsrv[0:0] + end + attribute \src "libresoc.v:85205.3-85259.6" + process $proc$libresoc.v:85205$3744 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_is_32b[0:0] $1\dec31_dec_sub11_is_32b[0:0] + attribute \src "libresoc.v:85206.5-85206.29" + switch \initial + attribute \src "libresoc.v:85206.9-85206.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + case + assign $1\dec31_dec_sub11_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub11_is_32b $0\dec31_dec_sub11_is_32b[0:0] + end + attribute \src "libresoc.v:85260.3-85314.6" + process $proc$libresoc.v:85260$3745 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_sgn[0:0] $1\dec31_dec_sub11_sgn[0:0] + attribute \src "libresoc.v:85261.5-85261.29" + switch \initial + attribute \src "libresoc.v:85261.9-85261.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'1 + case + assign $1\dec31_dec_sub11_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub11_sgn $0\dec31_dec_sub11_sgn[0:0] + end + attribute \src "libresoc.v:85315.3-85369.6" + process $proc$libresoc.v:85315$3746 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_lk[0:0] $1\dec31_dec_sub11_lk[0:0] + attribute \src "libresoc.v:85316.5-85316.29" + switch \initial + attribute \src "libresoc.v:85316.9-85316.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub11_lk $0\dec31_dec_sub11_lk[0:0] + end + attribute \src "libresoc.v:85370.3-85424.6" + process $proc$libresoc.v:85370$3747 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_sgl_pipe[0:0] $1\dec31_dec_sub11_sgl_pipe[0:0] + attribute \src "libresoc.v:85371.5-85371.29" + switch \initial + attribute \src "libresoc.v:85371.9-85371.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + case + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub11_sgl_pipe $0\dec31_dec_sub11_sgl_pipe[0:0] + end + attribute \src "libresoc.v:85425.3-85479.6" + process $proc$libresoc.v:85425$3748 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_form[4:0] $1\dec31_dec_sub11_form[4:0] + attribute \src "libresoc.v:85426.5-85426.29" + switch \initial + attribute \src "libresoc.v:85426.9-85426.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'10001 + case + assign $1\dec31_dec_sub11_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub11_form $0\dec31_dec_sub11_form[4:0] + end + attribute \src "libresoc.v:85480.3-85534.6" + process $proc$libresoc.v:85480$3749 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_in1_sel[2:0] $1\dec31_dec_sub11_in1_sel[2:0] + attribute \src "libresoc.v:85481.5-85481.29" + switch \initial + attribute \src "libresoc.v:85481.9-85481.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + case + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub11_in1_sel $0\dec31_dec_sub11_in1_sel[2:0] + end + attribute \src "libresoc.v:85535.3-85589.6" + process $proc$libresoc.v:85535$3750 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_in2_sel[3:0] $1\dec31_dec_sub11_in2_sel[3:0] + attribute \src "libresoc.v:85536.5-85536.29" + switch \initial + attribute \src "libresoc.v:85536.9-85536.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + case + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub11_in2_sel $0\dec31_dec_sub11_in2_sel[3:0] + end + attribute \src "libresoc.v:85590.3-85644.6" + process $proc$libresoc.v:85590$3751 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_in3_sel[1:0] $1\dec31_dec_sub11_in3_sel[1:0] + attribute \src "libresoc.v:85591.5-85591.29" + switch \initial + attribute \src "libresoc.v:85591.9-85591.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub11_in3_sel $0\dec31_dec_sub11_in3_sel[1:0] + end + attribute \src "libresoc.v:85645.3-85699.6" + process $proc$libresoc.v:85645$3752 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_out_sel[1:0] $1\dec31_dec_sub11_out_sel[1:0] + attribute \src "libresoc.v:85646.5-85646.29" + switch \initial + attribute \src "libresoc.v:85646.9-85646.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + case + assign $1\dec31_dec_sub11_out_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub11_out_sel $0\dec31_dec_sub11_out_sel[1:0] + end + attribute \src "libresoc.v:85700.3-85754.6" + process $proc$libresoc.v:85700$3753 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_cr_in[2:0] $1\dec31_dec_sub11_cr_in[2:0] + attribute \src "libresoc.v:85701.5-85701.29" + switch \initial + attribute \src "libresoc.v:85701.9-85701.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub11_cr_in $0\dec31_dec_sub11_cr_in[2:0] + end + attribute \src "libresoc.v:85755.3-85809.6" + process $proc$libresoc.v:85755$3754 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_cr_out[2:0] $1\dec31_dec_sub11_cr_out[2:0] + attribute \src "libresoc.v:85756.5-85756.29" + switch \initial + attribute \src "libresoc.v:85756.9-85756.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + case + assign $1\dec31_dec_sub11_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub11_cr_out $0\dec31_dec_sub11_cr_out[2:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:85815.1-88546.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec31_dec_sub15" +attribute \generator "nMigen" +module \dec31_dec_sub15 + attribute \src "libresoc.v:86588.3-86690.6" + wire width 8 $0\dec31_dec_sub15_asmcode[7:0] + attribute \src "libresoc.v:87000.3-87102.6" + wire $0\dec31_dec_sub15_br[0:0] + attribute \src "libresoc.v:88339.3-88441.6" + wire width 3 $0\dec31_dec_sub15_cr_in[2:0] + attribute \src "libresoc.v:88442.3-88544.6" + wire width 3 $0\dec31_dec_sub15_cr_out[2:0] + attribute \src "libresoc.v:86485.3-86587.6" + wire width 2 $0\dec31_dec_sub15_cry_in[1:0] + attribute \src "libresoc.v:86897.3-86999.6" + wire $0\dec31_dec_sub15_cry_out[0:0] + attribute \src "libresoc.v:87824.3-87926.6" + wire width 5 $0\dec31_dec_sub15_form[4:0] + attribute \src "libresoc.v:86073.3-86175.6" + wire width 12 $0\dec31_dec_sub15_function_unit[11:0] + attribute \src "libresoc.v:87927.3-88029.6" + wire width 3 $0\dec31_dec_sub15_in1_sel[2:0] + attribute \src "libresoc.v:88030.3-88132.6" + wire width 4 $0\dec31_dec_sub15_in2_sel[3:0] + attribute \src "libresoc.v:88133.3-88235.6" + wire width 2 $0\dec31_dec_sub15_in3_sel[1:0] + attribute \src "libresoc.v:87206.3-87308.6" + wire width 7 $0\dec31_dec_sub15_internal_op[6:0] + attribute \src "libresoc.v:86691.3-86793.6" + wire $0\dec31_dec_sub15_inv_a[0:0] + attribute \src "libresoc.v:86794.3-86896.6" + wire $0\dec31_dec_sub15_inv_out[0:0] + attribute \src "libresoc.v:87412.3-87514.6" + wire $0\dec31_dec_sub15_is_32b[0:0] + attribute \src "libresoc.v:86176.3-86278.6" + wire width 4 $0\dec31_dec_sub15_ldst_len[3:0] + attribute \src "libresoc.v:87618.3-87720.6" + wire $0\dec31_dec_sub15_lk[0:0] + attribute \src "libresoc.v:88236.3-88338.6" + wire width 2 $0\dec31_dec_sub15_out_sel[1:0] + attribute \src "libresoc.v:86382.3-86484.6" + wire width 2 $0\dec31_dec_sub15_rc_sel[1:0] + attribute \src "libresoc.v:87309.3-87411.6" + wire $0\dec31_dec_sub15_rsrv[0:0] + attribute \src "libresoc.v:87721.3-87823.6" + wire $0\dec31_dec_sub15_sgl_pipe[0:0] + attribute \src "libresoc.v:87515.3-87617.6" + wire $0\dec31_dec_sub15_sgn[0:0] + attribute \src "libresoc.v:87103.3-87205.6" + wire $0\dec31_dec_sub15_sgn_ext[0:0] + attribute \src "libresoc.v:86279.3-86381.6" + wire width 2 $0\dec31_dec_sub15_upd[1:0] + attribute \src "libresoc.v:85816.7-85816.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:86588.3-86690.6" + wire width 8 $1\dec31_dec_sub15_asmcode[7:0] + attribute \src "libresoc.v:87000.3-87102.6" + wire $1\dec31_dec_sub15_br[0:0] + attribute \src "libresoc.v:88339.3-88441.6" + wire width 3 $1\dec31_dec_sub15_cr_in[2:0] + attribute \src "libresoc.v:88442.3-88544.6" + wire width 3 $1\dec31_dec_sub15_cr_out[2:0] + attribute \src "libresoc.v:86485.3-86587.6" + wire width 2 $1\dec31_dec_sub15_cry_in[1:0] + attribute \src "libresoc.v:86897.3-86999.6" + wire $1\dec31_dec_sub15_cry_out[0:0] + attribute \src "libresoc.v:87824.3-87926.6" + wire width 5 $1\dec31_dec_sub15_form[4:0] + attribute \src "libresoc.v:86073.3-86175.6" + wire width 12 $1\dec31_dec_sub15_function_unit[11:0] + attribute \src "libresoc.v:87927.3-88029.6" + wire width 3 $1\dec31_dec_sub15_in1_sel[2:0] + attribute \src "libresoc.v:88030.3-88132.6" + wire width 4 $1\dec31_dec_sub15_in2_sel[3:0] + attribute \src "libresoc.v:88133.3-88235.6" + wire width 2 $1\dec31_dec_sub15_in3_sel[1:0] + attribute \src "libresoc.v:87206.3-87308.6" + wire width 7 $1\dec31_dec_sub15_internal_op[6:0] + attribute \src "libresoc.v:86691.3-86793.6" + wire $1\dec31_dec_sub15_inv_a[0:0] + attribute \src "libresoc.v:86794.3-86896.6" + wire $1\dec31_dec_sub15_inv_out[0:0] + attribute \src "libresoc.v:87412.3-87514.6" + wire $1\dec31_dec_sub15_is_32b[0:0] + attribute \src "libresoc.v:86176.3-86278.6" + wire width 4 $1\dec31_dec_sub15_ldst_len[3:0] + attribute \src "libresoc.v:87618.3-87720.6" + wire $1\dec31_dec_sub15_lk[0:0] + attribute \src "libresoc.v:88236.3-88338.6" + wire width 2 $1\dec31_dec_sub15_out_sel[1:0] + attribute \src "libresoc.v:86382.3-86484.6" + wire width 2 $1\dec31_dec_sub15_rc_sel[1:0] + attribute \src "libresoc.v:87309.3-87411.6" + wire $1\dec31_dec_sub15_rsrv[0:0] + attribute \src "libresoc.v:87721.3-87823.6" + wire $1\dec31_dec_sub15_sgl_pipe[0:0] + attribute \src "libresoc.v:87515.3-87617.6" + wire $1\dec31_dec_sub15_sgn[0:0] + attribute \src "libresoc.v:87103.3-87205.6" + wire $1\dec31_dec_sub15_sgn_ext[0:0] + attribute \src "libresoc.v:86279.3-86381.6" + wire width 2 $1\dec31_dec_sub15_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 output 4 \dec31_dec_sub15_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 18 \dec31_dec_sub15_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 9 \dec31_dec_sub15_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 10 \dec31_dec_sub15_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 14 \dec31_dec_sub15_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 17 \dec31_dec_sub15_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 output 3 \dec31_dec_sub15_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \dec31_dec_sub15_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \dec31_dec_sub15_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 6 \dec31_dec_sub15_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 7 \dec31_dec_sub15_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \dec31_dec_sub15_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 15 \dec31_dec_sub15_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 16 \dec31_dec_sub15_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 21 \dec31_dec_sub15_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 11 \dec31_dec_sub15_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 23 \dec31_dec_sub15_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 8 \dec31_dec_sub15_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 13 \dec31_dec_sub15_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 20 \dec31_dec_sub15_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 24 \dec31_dec_sub15_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 22 \dec31_dec_sub15_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 19 \dec31_dec_sub15_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 12 \dec31_dec_sub15_upd + attribute \src "libresoc.v:85816.7-85816.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 5 \opcode_switch + attribute \src "libresoc.v:85816.7-85816.20" + process $proc$libresoc.v:85816$3780 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:86073.3-86175.6" + process $proc$libresoc.v:86073$3756 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_function_unit[11:0] $1\dec31_dec_sub15_function_unit[11:0] + attribute \src "libresoc.v:86074.5-86074.29" + switch \initial + attribute \src "libresoc.v:86074.9-86074.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + case + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000000000000 + end + sync always + update \dec31_dec_sub15_function_unit $0\dec31_dec_sub15_function_unit[11:0] + end + attribute \src "libresoc.v:86176.3-86278.6" + process $proc$libresoc.v:86176$3757 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_ldst_len[3:0] $1\dec31_dec_sub15_ldst_len[3:0] + attribute \src "libresoc.v:86177.5-86177.29" + switch \initial + attribute \src "libresoc.v:86177.9-86177.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + case + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub15_ldst_len $0\dec31_dec_sub15_ldst_len[3:0] + end + attribute \src "libresoc.v:86279.3-86381.6" + process $proc$libresoc.v:86279$3758 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_upd[1:0] $1\dec31_dec_sub15_upd[1:0] + attribute \src "libresoc.v:86280.5-86280.29" + switch \initial + attribute \src "libresoc.v:86280.9-86280.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub15_upd $0\dec31_dec_sub15_upd[1:0] + end + attribute \src "libresoc.v:86382.3-86484.6" + process $proc$libresoc.v:86382$3759 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_rc_sel[1:0] $1\dec31_dec_sub15_rc_sel[1:0] + attribute \src "libresoc.v:86383.5-86383.29" + switch \initial + attribute \src "libresoc.v:86383.9-86383.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub15_rc_sel $0\dec31_dec_sub15_rc_sel[1:0] + end + attribute \src "libresoc.v:86485.3-86587.6" + process $proc$libresoc.v:86485$3760 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_cry_in[1:0] $1\dec31_dec_sub15_cry_in[1:0] + attribute \src "libresoc.v:86486.5-86486.29" + switch \initial + attribute \src "libresoc.v:86486.9-86486.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + case + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub15_cry_in $0\dec31_dec_sub15_cry_in[1:0] + end + attribute \src "libresoc.v:86588.3-86690.6" + process $proc$libresoc.v:86588$3761 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_asmcode[7:0] $1\dec31_dec_sub15_asmcode[7:0] + attribute \src "libresoc.v:86589.5-86589.29" + switch \initial + attribute \src "libresoc.v:86589.9-86589.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + case + assign $1\dec31_dec_sub15_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub15_asmcode $0\dec31_dec_sub15_asmcode[7:0] + end + attribute \src "libresoc.v:86691.3-86793.6" + process $proc$libresoc.v:86691$3762 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_inv_a[0:0] $1\dec31_dec_sub15_inv_a[0:0] + attribute \src "libresoc.v:86692.5-86692.29" + switch \initial + attribute \src "libresoc.v:86692.9-86692.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub15_inv_a $0\dec31_dec_sub15_inv_a[0:0] + end + attribute \src "libresoc.v:86794.3-86896.6" + process $proc$libresoc.v:86794$3763 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_inv_out[0:0] $1\dec31_dec_sub15_inv_out[0:0] + attribute \src "libresoc.v:86795.5-86795.29" + switch \initial + attribute \src "libresoc.v:86795.9-86795.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub15_inv_out $0\dec31_dec_sub15_inv_out[0:0] + end + attribute \src "libresoc.v:86897.3-86999.6" + process $proc$libresoc.v:86897$3764 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_cry_out[0:0] $1\dec31_dec_sub15_cry_out[0:0] + attribute \src "libresoc.v:86898.5-86898.29" + switch \initial + attribute \src "libresoc.v:86898.9-86898.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + case + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub15_cry_out $0\dec31_dec_sub15_cry_out[0:0] + end + attribute \src "libresoc.v:87000.3-87102.6" + process $proc$libresoc.v:87000$3765 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_br[0:0] $1\dec31_dec_sub15_br[0:0] + attribute \src "libresoc.v:87001.5-87001.29" + switch \initial + attribute \src "libresoc.v:87001.9-87001.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + case + assign $1\dec31_dec_sub15_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub15_br $0\dec31_dec_sub15_br[0:0] + end + attribute \src "libresoc.v:87103.3-87205.6" + process $proc$libresoc.v:87103$3766 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_sgn_ext[0:0] $1\dec31_dec_sub15_sgn_ext[0:0] + attribute \src "libresoc.v:87104.5-87104.29" + switch \initial + attribute \src "libresoc.v:87104.9-87104.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub15_sgn_ext $0\dec31_dec_sub15_sgn_ext[0:0] + end + attribute \src "libresoc.v:87206.3-87308.6" + process $proc$libresoc.v:87206$3767 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_internal_op[6:0] $1\dec31_dec_sub15_internal_op[6:0] + attribute \src "libresoc.v:87207.5-87207.29" + switch \initial + attribute \src "libresoc.v:87207.9-87207.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + case + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub15_internal_op $0\dec31_dec_sub15_internal_op[6:0] + end + attribute \src "libresoc.v:87309.3-87411.6" + process $proc$libresoc.v:87309$3768 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_rsrv[0:0] $1\dec31_dec_sub15_rsrv[0:0] + attribute \src "libresoc.v:87310.5-87310.29" + switch \initial + attribute \src "libresoc.v:87310.9-87310.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub15_rsrv $0\dec31_dec_sub15_rsrv[0:0] + end + attribute \src "libresoc.v:87412.3-87514.6" + process $proc$libresoc.v:87412$3769 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_is_32b[0:0] $1\dec31_dec_sub15_is_32b[0:0] + attribute \src "libresoc.v:87413.5-87413.29" + switch \initial + attribute \src "libresoc.v:87413.9-87413.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + case + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub15_is_32b $0\dec31_dec_sub15_is_32b[0:0] + end + attribute \src "libresoc.v:87515.3-87617.6" + process $proc$libresoc.v:87515$3770 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_sgn[0:0] $1\dec31_dec_sub15_sgn[0:0] + attribute \src "libresoc.v:87516.5-87516.29" + switch \initial + attribute \src "libresoc.v:87516.9-87516.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + case + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub15_sgn $0\dec31_dec_sub15_sgn[0:0] + end + attribute \src "libresoc.v:87618.3-87720.6" + process $proc$libresoc.v:87618$3771 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_lk[0:0] $1\dec31_dec_sub15_lk[0:0] + attribute \src "libresoc.v:87619.5-87619.29" + switch \initial + attribute \src "libresoc.v:87619.9-87619.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub15_lk $0\dec31_dec_sub15_lk[0:0] + end + attribute \src "libresoc.v:87721.3-87823.6" + process $proc$libresoc.v:87721$3772 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_sgl_pipe[0:0] $1\dec31_dec_sub15_sgl_pipe[0:0] + attribute \src "libresoc.v:87722.5-87722.29" + switch \initial + attribute \src "libresoc.v:87722.9-87722.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + case + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub15_sgl_pipe $0\dec31_dec_sub15_sgl_pipe[0:0] + end + attribute \src "libresoc.v:87824.3-87926.6" + process $proc$libresoc.v:87824$3773 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_form[4:0] $1\dec31_dec_sub15_form[4:0] + attribute \src "libresoc.v:87825.5-87825.29" + switch \initial + attribute \src "libresoc.v:87825.9-87825.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + case + assign $1\dec31_dec_sub15_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub15_form $0\dec31_dec_sub15_form[4:0] + end + attribute \src "libresoc.v:87927.3-88029.6" + process $proc$libresoc.v:87927$3774 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_in1_sel[2:0] $1\dec31_dec_sub15_in1_sel[2:0] + attribute \src "libresoc.v:87928.5-87928.29" + switch \initial + attribute \src "libresoc.v:87928.9-87928.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + case + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub15_in1_sel $0\dec31_dec_sub15_in1_sel[2:0] + end + attribute \src "libresoc.v:88030.3-88132.6" + process $proc$libresoc.v:88030$3775 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_in2_sel[3:0] $1\dec31_dec_sub15_in2_sel[3:0] + attribute \src "libresoc.v:88031.5-88031.29" + switch \initial + attribute \src "libresoc.v:88031.9-88031.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + case + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub15_in2_sel $0\dec31_dec_sub15_in2_sel[3:0] + end + attribute \src "libresoc.v:88133.3-88235.6" + process $proc$libresoc.v:88133$3776 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_in3_sel[1:0] $1\dec31_dec_sub15_in3_sel[1:0] + attribute \src "libresoc.v:88134.5-88134.29" + switch \initial + attribute \src "libresoc.v:88134.9-88134.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub15_in3_sel $0\dec31_dec_sub15_in3_sel[1:0] + end + attribute \src "libresoc.v:88236.3-88338.6" + process $proc$libresoc.v:88236$3777 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_out_sel[1:0] $1\dec31_dec_sub15_out_sel[1:0] + attribute \src "libresoc.v:88237.5-88237.29" + switch \initial + attribute \src "libresoc.v:88237.9-88237.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + case + assign $1\dec31_dec_sub15_out_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub15_out_sel $0\dec31_dec_sub15_out_sel[1:0] + end + attribute \src "libresoc.v:88339.3-88441.6" + process $proc$libresoc.v:88339$3778 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_cr_in[2:0] $1\dec31_dec_sub15_cr_in[2:0] + attribute \src "libresoc.v:88340.5-88340.29" + switch \initial + attribute \src "libresoc.v:88340.9-88340.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + case + assign $1\dec31_dec_sub15_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub15_cr_in $0\dec31_dec_sub15_cr_in[2:0] + end + attribute \src "libresoc.v:88442.3-88544.6" + process $proc$libresoc.v:88442$3779 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_cr_out[2:0] $1\dec31_dec_sub15_cr_out[2:0] + attribute \src "libresoc.v:88443.5-88443.29" + switch \initial + attribute \src "libresoc.v:88443.9-88443.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + case + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub15_cr_out $0\dec31_dec_sub15_cr_out[2:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:88550.1-89049.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec31_dec_sub16" +attribute \generator "nMigen" +module \dec31_dec_sub16 + attribute \src "libresoc.v:88858.3-88867.6" + wire width 8 $0\dec31_dec_sub16_asmcode[7:0] + attribute \src "libresoc.v:88898.3-88907.6" + wire $0\dec31_dec_sub16_br[0:0] + attribute \src "libresoc.v:89028.3-89037.6" + wire width 3 $0\dec31_dec_sub16_cr_in[2:0] + attribute \src "libresoc.v:89038.3-89047.6" + wire width 3 $0\dec31_dec_sub16_cr_out[2:0] + attribute \src "libresoc.v:88848.3-88857.6" + wire width 2 $0\dec31_dec_sub16_cry_in[1:0] + attribute \src "libresoc.v:88888.3-88897.6" + wire $0\dec31_dec_sub16_cry_out[0:0] + attribute \src "libresoc.v:88978.3-88987.6" + wire width 5 $0\dec31_dec_sub16_form[4:0] + attribute \src "libresoc.v:88808.3-88817.6" + wire width 12 $0\dec31_dec_sub16_function_unit[11:0] + attribute \src "libresoc.v:88988.3-88997.6" + wire width 3 $0\dec31_dec_sub16_in1_sel[2:0] + attribute \src "libresoc.v:88998.3-89007.6" + wire width 4 $0\dec31_dec_sub16_in2_sel[3:0] + attribute \src "libresoc.v:89008.3-89017.6" + wire width 2 $0\dec31_dec_sub16_in3_sel[1:0] + attribute \src "libresoc.v:88918.3-88927.6" + wire width 7 $0\dec31_dec_sub16_internal_op[6:0] + attribute \src "libresoc.v:88868.3-88877.6" + wire $0\dec31_dec_sub16_inv_a[0:0] + attribute \src "libresoc.v:88878.3-88887.6" + wire $0\dec31_dec_sub16_inv_out[0:0] + attribute \src "libresoc.v:88938.3-88947.6" + wire $0\dec31_dec_sub16_is_32b[0:0] + attribute \src "libresoc.v:88818.3-88827.6" + wire width 4 $0\dec31_dec_sub16_ldst_len[3:0] + attribute \src "libresoc.v:88958.3-88967.6" + wire $0\dec31_dec_sub16_lk[0:0] + attribute \src "libresoc.v:89018.3-89027.6" + wire width 2 $0\dec31_dec_sub16_out_sel[1:0] + attribute \src "libresoc.v:88838.3-88847.6" + wire width 2 $0\dec31_dec_sub16_rc_sel[1:0] + attribute \src "libresoc.v:88928.3-88937.6" + wire $0\dec31_dec_sub16_rsrv[0:0] + attribute \src "libresoc.v:88968.3-88977.6" + wire $0\dec31_dec_sub16_sgl_pipe[0:0] + attribute \src "libresoc.v:88948.3-88957.6" + wire $0\dec31_dec_sub16_sgn[0:0] + attribute \src "libresoc.v:88908.3-88917.6" + wire $0\dec31_dec_sub16_sgn_ext[0:0] + attribute \src "libresoc.v:88828.3-88837.6" + wire width 2 $0\dec31_dec_sub16_upd[1:0] + attribute \src "libresoc.v:88551.7-88551.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:88858.3-88867.6" + wire width 8 $1\dec31_dec_sub16_asmcode[7:0] + attribute \src "libresoc.v:88898.3-88907.6" + wire $1\dec31_dec_sub16_br[0:0] + attribute \src "libresoc.v:89028.3-89037.6" + wire width 3 $1\dec31_dec_sub16_cr_in[2:0] + attribute \src "libresoc.v:89038.3-89047.6" + wire width 3 $1\dec31_dec_sub16_cr_out[2:0] + attribute \src "libresoc.v:88848.3-88857.6" + wire width 2 $1\dec31_dec_sub16_cry_in[1:0] + attribute \src "libresoc.v:88888.3-88897.6" + wire $1\dec31_dec_sub16_cry_out[0:0] + attribute \src "libresoc.v:88978.3-88987.6" + wire width 5 $1\dec31_dec_sub16_form[4:0] + attribute \src "libresoc.v:88808.3-88817.6" + wire width 12 $1\dec31_dec_sub16_function_unit[11:0] + attribute \src "libresoc.v:88988.3-88997.6" + wire width 3 $1\dec31_dec_sub16_in1_sel[2:0] + attribute \src "libresoc.v:88998.3-89007.6" + wire width 4 $1\dec31_dec_sub16_in2_sel[3:0] + attribute \src "libresoc.v:89008.3-89017.6" + wire width 2 $1\dec31_dec_sub16_in3_sel[1:0] + attribute \src "libresoc.v:88918.3-88927.6" + wire width 7 $1\dec31_dec_sub16_internal_op[6:0] + attribute \src "libresoc.v:88868.3-88877.6" + wire $1\dec31_dec_sub16_inv_a[0:0] + attribute \src "libresoc.v:88878.3-88887.6" + wire $1\dec31_dec_sub16_inv_out[0:0] + attribute \src "libresoc.v:88938.3-88947.6" + wire $1\dec31_dec_sub16_is_32b[0:0] + attribute \src "libresoc.v:88818.3-88827.6" + wire width 4 $1\dec31_dec_sub16_ldst_len[3:0] + attribute \src "libresoc.v:88958.3-88967.6" + wire $1\dec31_dec_sub16_lk[0:0] + attribute \src "libresoc.v:89018.3-89027.6" + wire width 2 $1\dec31_dec_sub16_out_sel[1:0] + attribute \src "libresoc.v:88838.3-88847.6" + wire width 2 $1\dec31_dec_sub16_rc_sel[1:0] + attribute \src "libresoc.v:88928.3-88937.6" + wire $1\dec31_dec_sub16_rsrv[0:0] + attribute \src "libresoc.v:88968.3-88977.6" + wire $1\dec31_dec_sub16_sgl_pipe[0:0] + attribute \src "libresoc.v:88948.3-88957.6" + wire $1\dec31_dec_sub16_sgn[0:0] + attribute \src "libresoc.v:88908.3-88917.6" + wire $1\dec31_dec_sub16_sgn_ext[0:0] + attribute \src "libresoc.v:88828.3-88837.6" + wire width 2 $1\dec31_dec_sub16_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 output 4 \dec31_dec_sub16_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 18 \dec31_dec_sub16_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 9 \dec31_dec_sub16_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 10 \dec31_dec_sub16_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 14 \dec31_dec_sub16_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 17 \dec31_dec_sub16_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 output 3 \dec31_dec_sub16_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \dec31_dec_sub16_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \dec31_dec_sub16_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 6 \dec31_dec_sub16_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 7 \dec31_dec_sub16_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \dec31_dec_sub16_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 15 \dec31_dec_sub16_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 16 \dec31_dec_sub16_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 21 \dec31_dec_sub16_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 11 \dec31_dec_sub16_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 23 \dec31_dec_sub16_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 8 \dec31_dec_sub16_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 13 \dec31_dec_sub16_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 20 \dec31_dec_sub16_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 24 \dec31_dec_sub16_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 22 \dec31_dec_sub16_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 19 \dec31_dec_sub16_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 12 \dec31_dec_sub16_upd + attribute \src "libresoc.v:88551.7-88551.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 5 \opcode_switch + attribute \src "libresoc.v:88551.7-88551.20" + process $proc$libresoc.v:88551$3805 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:88808.3-88817.6" + process $proc$libresoc.v:88808$3781 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_function_unit[11:0] $1\dec31_dec_sub16_function_unit[11:0] + attribute \src "libresoc.v:88809.5-88809.29" + switch \initial + attribute \src "libresoc.v:88809.9-88809.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_function_unit[11:0] 12'000001000000 + case + assign $1\dec31_dec_sub16_function_unit[11:0] 12'000000000000 + end + sync always + update \dec31_dec_sub16_function_unit $0\dec31_dec_sub16_function_unit[11:0] + end + attribute \src "libresoc.v:88818.3-88827.6" + process $proc$libresoc.v:88818$3782 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_ldst_len[3:0] $1\dec31_dec_sub16_ldst_len[3:0] + attribute \src "libresoc.v:88819.5-88819.29" + switch \initial + attribute \src "libresoc.v:88819.9-88819.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_ldst_len[3:0] 4'0000 + case + assign $1\dec31_dec_sub16_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub16_ldst_len $0\dec31_dec_sub16_ldst_len[3:0] + end + attribute \src "libresoc.v:88828.3-88837.6" + process $proc$libresoc.v:88828$3783 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_upd[1:0] $1\dec31_dec_sub16_upd[1:0] + attribute \src "libresoc.v:88829.5-88829.29" + switch \initial + attribute \src "libresoc.v:88829.9-88829.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub16_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub16_upd $0\dec31_dec_sub16_upd[1:0] + end + attribute \src "libresoc.v:88838.3-88847.6" + process $proc$libresoc.v:88838$3784 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_rc_sel[1:0] $1\dec31_dec_sub16_rc_sel[1:0] + attribute \src "libresoc.v:88839.5-88839.29" + switch \initial + attribute \src "libresoc.v:88839.9-88839.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_rc_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub16_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub16_rc_sel $0\dec31_dec_sub16_rc_sel[1:0] + end + attribute \src "libresoc.v:88848.3-88857.6" + process $proc$libresoc.v:88848$3785 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_cry_in[1:0] $1\dec31_dec_sub16_cry_in[1:0] + attribute \src "libresoc.v:88849.5-88849.29" + switch \initial + attribute \src "libresoc.v:88849.9-88849.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_cry_in[1:0] 2'00 + case + assign $1\dec31_dec_sub16_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub16_cry_in $0\dec31_dec_sub16_cry_in[1:0] + end + attribute \src "libresoc.v:88858.3-88867.6" + process $proc$libresoc.v:88858$3786 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_asmcode[7:0] $1\dec31_dec_sub16_asmcode[7:0] + attribute \src "libresoc.v:88859.5-88859.29" + switch \initial + attribute \src "libresoc.v:88859.9-88859.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_asmcode[7:0] 8'01110110 + case + assign $1\dec31_dec_sub16_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub16_asmcode $0\dec31_dec_sub16_asmcode[7:0] + end + attribute \src "libresoc.v:88868.3-88877.6" + process $proc$libresoc.v:88868$3787 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_inv_a[0:0] $1\dec31_dec_sub16_inv_a[0:0] + attribute \src "libresoc.v:88869.5-88869.29" + switch \initial + attribute \src "libresoc.v:88869.9-88869.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub16_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub16_inv_a $0\dec31_dec_sub16_inv_a[0:0] + end + attribute \src "libresoc.v:88878.3-88887.6" + process $proc$libresoc.v:88878$3788 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_inv_out[0:0] $1\dec31_dec_sub16_inv_out[0:0] + attribute \src "libresoc.v:88879.5-88879.29" + switch \initial + attribute \src "libresoc.v:88879.9-88879.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub16_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub16_inv_out $0\dec31_dec_sub16_inv_out[0:0] + end + attribute \src "libresoc.v:88888.3-88897.6" + process $proc$libresoc.v:88888$3789 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_cry_out[0:0] $1\dec31_dec_sub16_cry_out[0:0] + attribute \src "libresoc.v:88889.5-88889.29" + switch \initial + attribute \src "libresoc.v:88889.9-88889.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_cry_out[0:0] 1'0 + case + assign $1\dec31_dec_sub16_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub16_cry_out $0\dec31_dec_sub16_cry_out[0:0] + end + attribute \src "libresoc.v:88898.3-88907.6" + process $proc$libresoc.v:88898$3790 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_br[0:0] $1\dec31_dec_sub16_br[0:0] + attribute \src "libresoc.v:88899.5-88899.29" + switch \initial + attribute \src "libresoc.v:88899.9-88899.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_br[0:0] 1'0 + case + assign $1\dec31_dec_sub16_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub16_br $0\dec31_dec_sub16_br[0:0] + end + attribute \src "libresoc.v:88908.3-88917.6" + process $proc$libresoc.v:88908$3791 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_sgn_ext[0:0] $1\dec31_dec_sub16_sgn_ext[0:0] + attribute \src "libresoc.v:88909.5-88909.29" + switch \initial + attribute \src "libresoc.v:88909.9-88909.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub16_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub16_sgn_ext $0\dec31_dec_sub16_sgn_ext[0:0] + end + attribute \src "libresoc.v:88918.3-88927.6" + process $proc$libresoc.v:88918$3792 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_internal_op[6:0] $1\dec31_dec_sub16_internal_op[6:0] + attribute \src "libresoc.v:88919.5-88919.29" + switch \initial + attribute \src "libresoc.v:88919.9-88919.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_internal_op[6:0] 7'0110000 + case + assign $1\dec31_dec_sub16_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub16_internal_op $0\dec31_dec_sub16_internal_op[6:0] + end + attribute \src "libresoc.v:88928.3-88937.6" + process $proc$libresoc.v:88928$3793 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_rsrv[0:0] $1\dec31_dec_sub16_rsrv[0:0] + attribute \src "libresoc.v:88929.5-88929.29" + switch \initial + attribute \src "libresoc.v:88929.9-88929.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub16_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub16_rsrv $0\dec31_dec_sub16_rsrv[0:0] + end + attribute \src "libresoc.v:88938.3-88947.6" + process $proc$libresoc.v:88938$3794 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_is_32b[0:0] $1\dec31_dec_sub16_is_32b[0:0] + attribute \src "libresoc.v:88939.5-88939.29" + switch \initial + attribute \src "libresoc.v:88939.9-88939.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_is_32b[0:0] 1'0 + case + assign $1\dec31_dec_sub16_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub16_is_32b $0\dec31_dec_sub16_is_32b[0:0] + end + attribute \src "libresoc.v:88948.3-88957.6" + process $proc$libresoc.v:88948$3795 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_sgn[0:0] $1\dec31_dec_sub16_sgn[0:0] + attribute \src "libresoc.v:88949.5-88949.29" + switch \initial + attribute \src "libresoc.v:88949.9-88949.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_sgn[0:0] 1'0 + case + assign $1\dec31_dec_sub16_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub16_sgn $0\dec31_dec_sub16_sgn[0:0] + end + attribute \src "libresoc.v:88958.3-88967.6" + process $proc$libresoc.v:88958$3796 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_lk[0:0] $1\dec31_dec_sub16_lk[0:0] + attribute \src "libresoc.v:88959.5-88959.29" + switch \initial + attribute \src "libresoc.v:88959.9-88959.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub16_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub16_lk $0\dec31_dec_sub16_lk[0:0] + end + attribute \src "libresoc.v:88968.3-88977.6" + process $proc$libresoc.v:88968$3797 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_sgl_pipe[0:0] $1\dec31_dec_sub16_sgl_pipe[0:0] + attribute \src "libresoc.v:88969.5-88969.29" + switch \initial + attribute \src "libresoc.v:88969.9-88969.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_sgl_pipe[0:0] 1'0 + case + assign $1\dec31_dec_sub16_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub16_sgl_pipe $0\dec31_dec_sub16_sgl_pipe[0:0] + end + attribute \src "libresoc.v:88978.3-88987.6" + process $proc$libresoc.v:88978$3798 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_form[4:0] $1\dec31_dec_sub16_form[4:0] + attribute \src "libresoc.v:88979.5-88979.29" + switch \initial + attribute \src "libresoc.v:88979.9-88979.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_form[4:0] 5'01010 + case + assign $1\dec31_dec_sub16_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub16_form $0\dec31_dec_sub16_form[4:0] + end + attribute \src "libresoc.v:88988.3-88997.6" + process $proc$libresoc.v:88988$3799 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_in1_sel[2:0] $1\dec31_dec_sub16_in1_sel[2:0] + attribute \src "libresoc.v:88989.5-88989.29" + switch \initial + attribute \src "libresoc.v:88989.9-88989.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_in1_sel[2:0] 3'100 + case + assign $1\dec31_dec_sub16_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub16_in1_sel $0\dec31_dec_sub16_in1_sel[2:0] + end + attribute \src "libresoc.v:88998.3-89007.6" + process $proc$libresoc.v:88998$3800 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_in2_sel[3:0] $1\dec31_dec_sub16_in2_sel[3:0] + attribute \src "libresoc.v:88999.5-88999.29" + switch \initial + attribute \src "libresoc.v:88999.9-88999.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_in2_sel[3:0] 4'0000 + case + assign $1\dec31_dec_sub16_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub16_in2_sel $0\dec31_dec_sub16_in2_sel[3:0] + end + attribute \src "libresoc.v:89008.3-89017.6" + process $proc$libresoc.v:89008$3801 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_in3_sel[1:0] $1\dec31_dec_sub16_in3_sel[1:0] + attribute \src "libresoc.v:89009.5-89009.29" + switch \initial + attribute \src "libresoc.v:89009.9-89009.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_in3_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub16_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub16_in3_sel $0\dec31_dec_sub16_in3_sel[1:0] + end + attribute \src "libresoc.v:89018.3-89027.6" + process $proc$libresoc.v:89018$3802 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_out_sel[1:0] $1\dec31_dec_sub16_out_sel[1:0] + attribute \src "libresoc.v:89019.5-89019.29" + switch \initial + attribute \src "libresoc.v:89019.9-89019.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_out_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub16_out_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub16_out_sel $0\dec31_dec_sub16_out_sel[1:0] + end + attribute \src "libresoc.v:89028.3-89037.6" + process $proc$libresoc.v:89028$3803 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_cr_in[2:0] $1\dec31_dec_sub16_cr_in[2:0] + attribute \src "libresoc.v:89029.5-89029.29" + switch \initial + attribute \src "libresoc.v:89029.9-89029.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_cr_in[2:0] 3'110 + case + assign $1\dec31_dec_sub16_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub16_cr_in $0\dec31_dec_sub16_cr_in[2:0] + end + attribute \src "libresoc.v:89038.3-89047.6" + process $proc$libresoc.v:89038$3804 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_cr_out[2:0] $1\dec31_dec_sub16_cr_out[2:0] + attribute \src "libresoc.v:89039.5-89039.29" + switch \initial + attribute \src "libresoc.v:89039.9-89039.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_cr_out[2:0] 3'100 + case + assign $1\dec31_dec_sub16_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub16_cr_out $0\dec31_dec_sub16_cr_out[2:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:89053.1-89840.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec31_dec_sub18" +attribute \generator "nMigen" +module \dec31_dec_sub18 + attribute \src "libresoc.v:89421.3-89442.6" + wire width 8 $0\dec31_dec_sub18_asmcode[7:0] + attribute \src "libresoc.v:89509.3-89530.6" + wire $0\dec31_dec_sub18_br[0:0] + attribute \src "libresoc.v:89795.3-89816.6" + wire width 3 $0\dec31_dec_sub18_cr_in[2:0] + attribute \src "libresoc.v:89817.3-89838.6" + wire width 3 $0\dec31_dec_sub18_cr_out[2:0] + attribute \src "libresoc.v:89399.3-89420.6" + wire width 2 $0\dec31_dec_sub18_cry_in[1:0] + attribute \src "libresoc.v:89487.3-89508.6" + wire $0\dec31_dec_sub18_cry_out[0:0] + attribute \src "libresoc.v:89685.3-89706.6" + wire width 5 $0\dec31_dec_sub18_form[4:0] + attribute \src "libresoc.v:89311.3-89332.6" + wire width 12 $0\dec31_dec_sub18_function_unit[11:0] + attribute \src "libresoc.v:89707.3-89728.6" + wire width 3 $0\dec31_dec_sub18_in1_sel[2:0] + attribute \src "libresoc.v:89729.3-89750.6" + wire width 4 $0\dec31_dec_sub18_in2_sel[3:0] + attribute \src "libresoc.v:89751.3-89772.6" + wire width 2 $0\dec31_dec_sub18_in3_sel[1:0] + attribute \src "libresoc.v:89553.3-89574.6" + wire width 7 $0\dec31_dec_sub18_internal_op[6:0] + attribute \src "libresoc.v:89443.3-89464.6" + wire $0\dec31_dec_sub18_inv_a[0:0] + attribute \src "libresoc.v:89465.3-89486.6" + wire $0\dec31_dec_sub18_inv_out[0:0] + attribute \src "libresoc.v:89597.3-89618.6" + wire $0\dec31_dec_sub18_is_32b[0:0] + attribute \src "libresoc.v:89333.3-89354.6" + wire width 4 $0\dec31_dec_sub18_ldst_len[3:0] + attribute \src "libresoc.v:89641.3-89662.6" + wire $0\dec31_dec_sub18_lk[0:0] + attribute \src "libresoc.v:89773.3-89794.6" + wire width 2 $0\dec31_dec_sub18_out_sel[1:0] + attribute \src "libresoc.v:89377.3-89398.6" + wire width 2 $0\dec31_dec_sub18_rc_sel[1:0] + attribute \src "libresoc.v:89575.3-89596.6" + wire $0\dec31_dec_sub18_rsrv[0:0] + attribute \src "libresoc.v:89663.3-89684.6" + wire $0\dec31_dec_sub18_sgl_pipe[0:0] + attribute \src "libresoc.v:89619.3-89640.6" + wire $0\dec31_dec_sub18_sgn[0:0] + attribute \src "libresoc.v:89531.3-89552.6" + wire $0\dec31_dec_sub18_sgn_ext[0:0] + attribute \src "libresoc.v:89355.3-89376.6" + wire width 2 $0\dec31_dec_sub18_upd[1:0] + attribute \src "libresoc.v:89054.7-89054.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:89421.3-89442.6" + wire width 8 $1\dec31_dec_sub18_asmcode[7:0] + attribute \src "libresoc.v:89509.3-89530.6" + wire $1\dec31_dec_sub18_br[0:0] + attribute \src "libresoc.v:89795.3-89816.6" + wire width 3 $1\dec31_dec_sub18_cr_in[2:0] + attribute \src "libresoc.v:89817.3-89838.6" + wire width 3 $1\dec31_dec_sub18_cr_out[2:0] + attribute \src "libresoc.v:89399.3-89420.6" + wire width 2 $1\dec31_dec_sub18_cry_in[1:0] + attribute \src "libresoc.v:89487.3-89508.6" + wire $1\dec31_dec_sub18_cry_out[0:0] + attribute \src "libresoc.v:89685.3-89706.6" + wire width 5 $1\dec31_dec_sub18_form[4:0] + attribute \src "libresoc.v:89311.3-89332.6" + wire width 12 $1\dec31_dec_sub18_function_unit[11:0] + attribute \src "libresoc.v:89707.3-89728.6" + wire width 3 $1\dec31_dec_sub18_in1_sel[2:0] + attribute \src "libresoc.v:89729.3-89750.6" + wire width 4 $1\dec31_dec_sub18_in2_sel[3:0] + attribute \src "libresoc.v:89751.3-89772.6" + wire width 2 $1\dec31_dec_sub18_in3_sel[1:0] + attribute \src "libresoc.v:89553.3-89574.6" + wire width 7 $1\dec31_dec_sub18_internal_op[6:0] + attribute \src "libresoc.v:89443.3-89464.6" + wire $1\dec31_dec_sub18_inv_a[0:0] + attribute \src "libresoc.v:89465.3-89486.6" + wire $1\dec31_dec_sub18_inv_out[0:0] + attribute \src "libresoc.v:89597.3-89618.6" + wire $1\dec31_dec_sub18_is_32b[0:0] + attribute \src "libresoc.v:89333.3-89354.6" + wire width 4 $1\dec31_dec_sub18_ldst_len[3:0] + attribute \src "libresoc.v:89641.3-89662.6" + wire $1\dec31_dec_sub18_lk[0:0] + attribute \src "libresoc.v:89773.3-89794.6" + wire width 2 $1\dec31_dec_sub18_out_sel[1:0] + attribute \src "libresoc.v:89377.3-89398.6" + wire width 2 $1\dec31_dec_sub18_rc_sel[1:0] + attribute \src "libresoc.v:89575.3-89596.6" + wire $1\dec31_dec_sub18_rsrv[0:0] + attribute \src "libresoc.v:89663.3-89684.6" + wire $1\dec31_dec_sub18_sgl_pipe[0:0] + attribute \src "libresoc.v:89619.3-89640.6" + wire $1\dec31_dec_sub18_sgn[0:0] + attribute \src "libresoc.v:89531.3-89552.6" + wire $1\dec31_dec_sub18_sgn_ext[0:0] + attribute \src "libresoc.v:89355.3-89376.6" + wire width 2 $1\dec31_dec_sub18_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 output 4 \dec31_dec_sub18_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 18 \dec31_dec_sub18_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 9 \dec31_dec_sub18_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 10 \dec31_dec_sub18_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 14 \dec31_dec_sub18_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 17 \dec31_dec_sub18_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 output 3 \dec31_dec_sub18_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \dec31_dec_sub18_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \dec31_dec_sub18_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 6 \dec31_dec_sub18_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 7 \dec31_dec_sub18_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \dec31_dec_sub18_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 15 \dec31_dec_sub18_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 16 \dec31_dec_sub18_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 21 \dec31_dec_sub18_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 11 \dec31_dec_sub18_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 23 \dec31_dec_sub18_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 8 \dec31_dec_sub18_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 13 \dec31_dec_sub18_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 20 \dec31_dec_sub18_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 24 \dec31_dec_sub18_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 22 \dec31_dec_sub18_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 19 \dec31_dec_sub18_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 12 \dec31_dec_sub18_upd + attribute \src "libresoc.v:89054.7-89054.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 5 \opcode_switch + attribute \src "libresoc.v:89054.7-89054.20" + process $proc$libresoc.v:89054$3830 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:89311.3-89332.6" + process $proc$libresoc.v:89311$3806 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_function_unit[11:0] $1\dec31_dec_sub18_function_unit[11:0] + attribute \src "libresoc.v:89312.5-89312.29" + switch \initial + attribute \src "libresoc.v:89312.9-89312.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_function_unit[11:0] 12'000010000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_function_unit[11:0] 12'000010000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_function_unit[11:0] 12'100000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_function_unit[11:0] 12'100000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_function_unit[11:0] 12'100000000000 + case + assign $1\dec31_dec_sub18_function_unit[11:0] 12'000000000000 + end + sync always + update \dec31_dec_sub18_function_unit $0\dec31_dec_sub18_function_unit[11:0] + end + attribute \src "libresoc.v:89333.3-89354.6" + process $proc$libresoc.v:89333$3807 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_ldst_len[3:0] $1\dec31_dec_sub18_ldst_len[3:0] + attribute \src "libresoc.v:89334.5-89334.29" + switch \initial + attribute \src "libresoc.v:89334.9-89334.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_ldst_len[3:0] 4'0000 + case + assign $1\dec31_dec_sub18_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub18_ldst_len $0\dec31_dec_sub18_ldst_len[3:0] + end + attribute \src "libresoc.v:89355.3-89376.6" + process $proc$libresoc.v:89355$3808 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_upd[1:0] $1\dec31_dec_sub18_upd[1:0] + attribute \src "libresoc.v:89356.5-89356.29" + switch \initial + attribute \src "libresoc.v:89356.9-89356.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub18_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub18_upd $0\dec31_dec_sub18_upd[1:0] + end + attribute \src "libresoc.v:89377.3-89398.6" + process $proc$libresoc.v:89377$3809 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_rc_sel[1:0] $1\dec31_dec_sub18_rc_sel[1:0] + attribute \src "libresoc.v:89378.5-89378.29" + switch \initial + attribute \src "libresoc.v:89378.9-89378.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_rc_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub18_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub18_rc_sel $0\dec31_dec_sub18_rc_sel[1:0] + end + attribute \src "libresoc.v:89399.3-89420.6" + process $proc$libresoc.v:89399$3810 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_cry_in[1:0] $1\dec31_dec_sub18_cry_in[1:0] + attribute \src "libresoc.v:89400.5-89400.29" + switch \initial + attribute \src "libresoc.v:89400.9-89400.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_cry_in[1:0] 2'00 + case + assign $1\dec31_dec_sub18_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub18_cry_in $0\dec31_dec_sub18_cry_in[1:0] + end + attribute \src "libresoc.v:89421.3-89442.6" + process $proc$libresoc.v:89421$3811 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_asmcode[7:0] $1\dec31_dec_sub18_asmcode[7:0] + attribute \src "libresoc.v:89422.5-89422.29" + switch \initial + attribute \src "libresoc.v:89422.9-89422.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_asmcode[7:0] 8'01111000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_asmcode[7:0] 8'01110111 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_asmcode[7:0] 8'10011101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_asmcode[7:0] 8'11001100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_asmcode[7:0] 8'11001101 + case + assign $1\dec31_dec_sub18_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub18_asmcode $0\dec31_dec_sub18_asmcode[7:0] + end + attribute \src "libresoc.v:89443.3-89464.6" + process $proc$libresoc.v:89443$3812 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_inv_a[0:0] $1\dec31_dec_sub18_inv_a[0:0] + attribute \src "libresoc.v:89444.5-89444.29" + switch \initial + attribute \src "libresoc.v:89444.9-89444.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub18_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub18_inv_a $0\dec31_dec_sub18_inv_a[0:0] + end + attribute \src "libresoc.v:89465.3-89486.6" + process $proc$libresoc.v:89465$3813 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_inv_out[0:0] $1\dec31_dec_sub18_inv_out[0:0] + attribute \src "libresoc.v:89466.5-89466.29" + switch \initial + attribute \src "libresoc.v:89466.9-89466.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub18_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub18_inv_out $0\dec31_dec_sub18_inv_out[0:0] + end + attribute \src "libresoc.v:89487.3-89508.6" + process $proc$libresoc.v:89487$3814 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_cry_out[0:0] $1\dec31_dec_sub18_cry_out[0:0] + attribute \src "libresoc.v:89488.5-89488.29" + switch \initial + attribute \src "libresoc.v:89488.9-89488.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_cry_out[0:0] 1'0 + case + assign $1\dec31_dec_sub18_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub18_cry_out $0\dec31_dec_sub18_cry_out[0:0] + end + attribute \src "libresoc.v:89509.3-89530.6" + process $proc$libresoc.v:89509$3815 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_br[0:0] $1\dec31_dec_sub18_br[0:0] + attribute \src "libresoc.v:89510.5-89510.29" + switch \initial + attribute \src "libresoc.v:89510.9-89510.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_br[0:0] 1'0 + case + assign $1\dec31_dec_sub18_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub18_br $0\dec31_dec_sub18_br[0:0] + end + attribute \src "libresoc.v:89531.3-89552.6" + process $proc$libresoc.v:89531$3816 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_sgn_ext[0:0] $1\dec31_dec_sub18_sgn_ext[0:0] + attribute \src "libresoc.v:89532.5-89532.29" + switch \initial + attribute \src "libresoc.v:89532.9-89532.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub18_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub18_sgn_ext $0\dec31_dec_sub18_sgn_ext[0:0] + end + attribute \src "libresoc.v:89553.3-89574.6" + process $proc$libresoc.v:89553$3817 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_internal_op[6:0] $1\dec31_dec_sub18_internal_op[6:0] + attribute \src "libresoc.v:89554.5-89554.29" + switch \initial + attribute \src "libresoc.v:89554.9-89554.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_internal_op[6:0] 7'1001000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_internal_op[6:0] 7'1001010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_internal_op[6:0] 7'1001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_internal_op[6:0] 7'1001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_internal_op[6:0] 7'1001011 + case + assign $1\dec31_dec_sub18_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub18_internal_op $0\dec31_dec_sub18_internal_op[6:0] + end + attribute \src "libresoc.v:89575.3-89596.6" + process $proc$libresoc.v:89575$3818 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_rsrv[0:0] $1\dec31_dec_sub18_rsrv[0:0] + attribute \src "libresoc.v:89576.5-89576.29" + switch \initial + attribute \src "libresoc.v:89576.9-89576.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub18_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub18_rsrv $0\dec31_dec_sub18_rsrv[0:0] + end + attribute \src "libresoc.v:89597.3-89618.6" + process $proc$libresoc.v:89597$3819 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_is_32b[0:0] $1\dec31_dec_sub18_is_32b[0:0] + attribute \src "libresoc.v:89598.5-89598.29" + switch \initial + attribute \src "libresoc.v:89598.9-89598.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_is_32b[0:0] 1'0 + case + assign $1\dec31_dec_sub18_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub18_is_32b $0\dec31_dec_sub18_is_32b[0:0] + end + attribute \src "libresoc.v:89619.3-89640.6" + process $proc$libresoc.v:89619$3820 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_sgn[0:0] $1\dec31_dec_sub18_sgn[0:0] + attribute \src "libresoc.v:89620.5-89620.29" + switch \initial + attribute \src "libresoc.v:89620.9-89620.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_sgn[0:0] 1'0 + case + assign $1\dec31_dec_sub18_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub18_sgn $0\dec31_dec_sub18_sgn[0:0] + end + attribute \src "libresoc.v:89641.3-89662.6" + process $proc$libresoc.v:89641$3821 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_lk[0:0] $1\dec31_dec_sub18_lk[0:0] + attribute \src "libresoc.v:89642.5-89642.29" + switch \initial + attribute \src "libresoc.v:89642.9-89642.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub18_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub18_lk $0\dec31_dec_sub18_lk[0:0] + end + attribute \src "libresoc.v:89663.3-89684.6" + process $proc$libresoc.v:89663$3822 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_sgl_pipe[0:0] $1\dec31_dec_sub18_sgl_pipe[0:0] + attribute \src "libresoc.v:89664.5-89664.29" + switch \initial + attribute \src "libresoc.v:89664.9-89664.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_sgl_pipe[0:0] 1'0 + case + assign $1\dec31_dec_sub18_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub18_sgl_pipe $0\dec31_dec_sub18_sgl_pipe[0:0] + end + attribute \src "libresoc.v:89685.3-89706.6" + process $proc$libresoc.v:89685$3823 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_form[4:0] $1\dec31_dec_sub18_form[4:0] + attribute \src "libresoc.v:89686.5-89686.29" + switch \initial + attribute \src "libresoc.v:89686.9-89686.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_form[4:0] 5'01000 + case + assign $1\dec31_dec_sub18_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub18_form $0\dec31_dec_sub18_form[4:0] + end + attribute \src "libresoc.v:89707.3-89728.6" + process $proc$libresoc.v:89707$3824 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_in1_sel[2:0] $1\dec31_dec_sub18_in1_sel[2:0] + attribute \src "libresoc.v:89708.5-89708.29" + switch \initial + attribute \src "libresoc.v:89708.9-89708.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_in1_sel[2:0] 3'000 + case + assign $1\dec31_dec_sub18_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub18_in1_sel $0\dec31_dec_sub18_in1_sel[2:0] + end + attribute \src "libresoc.v:89729.3-89750.6" + process $proc$libresoc.v:89729$3825 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_in2_sel[3:0] $1\dec31_dec_sub18_in2_sel[3:0] + attribute \src "libresoc.v:89730.5-89730.29" + switch \initial + attribute \src "libresoc.v:89730.9-89730.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_in2_sel[3:0] 4'0001 + case + assign $1\dec31_dec_sub18_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub18_in2_sel $0\dec31_dec_sub18_in2_sel[3:0] + end + attribute \src "libresoc.v:89751.3-89772.6" + process $proc$libresoc.v:89751$3826 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_in3_sel[1:0] $1\dec31_dec_sub18_in3_sel[1:0] + attribute \src "libresoc.v:89752.5-89752.29" + switch \initial + attribute \src "libresoc.v:89752.9-89752.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_in3_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub18_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub18_in3_sel $0\dec31_dec_sub18_in3_sel[1:0] + end + attribute \src "libresoc.v:89773.3-89794.6" + process $proc$libresoc.v:89773$3827 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_out_sel[1:0] $1\dec31_dec_sub18_out_sel[1:0] + attribute \src "libresoc.v:89774.5-89774.29" + switch \initial + attribute \src "libresoc.v:89774.9-89774.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_out_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub18_out_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub18_out_sel $0\dec31_dec_sub18_out_sel[1:0] + end + attribute \src "libresoc.v:89795.3-89816.6" + process $proc$libresoc.v:89795$3828 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_cr_in[2:0] $1\dec31_dec_sub18_cr_in[2:0] + attribute \src "libresoc.v:89796.5-89796.29" + switch \initial + attribute \src "libresoc.v:89796.9-89796.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub18_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub18_cr_in $0\dec31_dec_sub18_cr_in[2:0] + end + attribute \src "libresoc.v:89817.3-89838.6" + process $proc$libresoc.v:89817$3829 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_cr_out[2:0] $1\dec31_dec_sub18_cr_out[2:0] + attribute \src "libresoc.v:89818.5-89818.29" + switch \initial + attribute \src "libresoc.v:89818.9-89818.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_cr_out[2:0] 3'000 + case + assign $1\dec31_dec_sub18_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub18_cr_out $0\dec31_dec_sub18_cr_out[2:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:89844.1-90559.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec31_dec_sub19" +attribute \generator "nMigen" +module \dec31_dec_sub19 + attribute \src "libresoc.v:90197.3-90215.6" + wire width 8 $0\dec31_dec_sub19_asmcode[7:0] + attribute \src "libresoc.v:90273.3-90291.6" + wire $0\dec31_dec_sub19_br[0:0] + attribute \src "libresoc.v:90520.3-90538.6" + wire width 3 $0\dec31_dec_sub19_cr_in[2:0] + attribute \src "libresoc.v:90539.3-90557.6" + wire width 3 $0\dec31_dec_sub19_cr_out[2:0] + attribute \src "libresoc.v:90178.3-90196.6" + wire width 2 $0\dec31_dec_sub19_cry_in[1:0] + attribute \src "libresoc.v:90254.3-90272.6" + wire $0\dec31_dec_sub19_cry_out[0:0] + attribute \src "libresoc.v:90425.3-90443.6" + wire width 5 $0\dec31_dec_sub19_form[4:0] + attribute \src "libresoc.v:90102.3-90120.6" + wire width 12 $0\dec31_dec_sub19_function_unit[11:0] + attribute \src "libresoc.v:90444.3-90462.6" + wire width 3 $0\dec31_dec_sub19_in1_sel[2:0] + attribute \src "libresoc.v:90463.3-90481.6" + wire width 4 $0\dec31_dec_sub19_in2_sel[3:0] + attribute \src "libresoc.v:90482.3-90500.6" + wire width 2 $0\dec31_dec_sub19_in3_sel[1:0] + attribute \src "libresoc.v:90311.3-90329.6" + wire width 7 $0\dec31_dec_sub19_internal_op[6:0] + attribute \src "libresoc.v:90216.3-90234.6" + wire $0\dec31_dec_sub19_inv_a[0:0] + attribute \src "libresoc.v:90235.3-90253.6" + wire $0\dec31_dec_sub19_inv_out[0:0] + attribute \src "libresoc.v:90349.3-90367.6" + wire $0\dec31_dec_sub19_is_32b[0:0] + attribute \src "libresoc.v:90121.3-90139.6" + wire width 4 $0\dec31_dec_sub19_ldst_len[3:0] + attribute \src "libresoc.v:90387.3-90405.6" + wire $0\dec31_dec_sub19_lk[0:0] + attribute \src "libresoc.v:90501.3-90519.6" + wire width 2 $0\dec31_dec_sub19_out_sel[1:0] + attribute \src "libresoc.v:90159.3-90177.6" + wire width 2 $0\dec31_dec_sub19_rc_sel[1:0] + attribute \src "libresoc.v:90330.3-90348.6" + wire $0\dec31_dec_sub19_rsrv[0:0] + attribute \src "libresoc.v:90406.3-90424.6" + wire $0\dec31_dec_sub19_sgl_pipe[0:0] + attribute \src "libresoc.v:90368.3-90386.6" + wire $0\dec31_dec_sub19_sgn[0:0] + attribute \src "libresoc.v:90292.3-90310.6" + wire $0\dec31_dec_sub19_sgn_ext[0:0] + attribute \src "libresoc.v:90140.3-90158.6" + wire width 2 $0\dec31_dec_sub19_upd[1:0] + attribute \src "libresoc.v:89845.7-89845.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:90197.3-90215.6" + wire width 8 $1\dec31_dec_sub19_asmcode[7:0] + attribute \src "libresoc.v:90273.3-90291.6" + wire $1\dec31_dec_sub19_br[0:0] + attribute \src "libresoc.v:90520.3-90538.6" + wire width 3 $1\dec31_dec_sub19_cr_in[2:0] + attribute \src "libresoc.v:90539.3-90557.6" + wire width 3 $1\dec31_dec_sub19_cr_out[2:0] + attribute \src "libresoc.v:90178.3-90196.6" + wire width 2 $1\dec31_dec_sub19_cry_in[1:0] + attribute \src "libresoc.v:90254.3-90272.6" + wire $1\dec31_dec_sub19_cry_out[0:0] + attribute \src "libresoc.v:90425.3-90443.6" + wire width 5 $1\dec31_dec_sub19_form[4:0] + attribute \src "libresoc.v:90102.3-90120.6" + wire width 12 $1\dec31_dec_sub19_function_unit[11:0] + attribute \src "libresoc.v:90444.3-90462.6" + wire width 3 $1\dec31_dec_sub19_in1_sel[2:0] + attribute \src "libresoc.v:90463.3-90481.6" + wire width 4 $1\dec31_dec_sub19_in2_sel[3:0] + attribute \src "libresoc.v:90482.3-90500.6" + wire width 2 $1\dec31_dec_sub19_in3_sel[1:0] + attribute \src "libresoc.v:90311.3-90329.6" + wire width 7 $1\dec31_dec_sub19_internal_op[6:0] + attribute \src "libresoc.v:90216.3-90234.6" + wire $1\dec31_dec_sub19_inv_a[0:0] + attribute \src "libresoc.v:90235.3-90253.6" + wire $1\dec31_dec_sub19_inv_out[0:0] + attribute \src "libresoc.v:90349.3-90367.6" + wire $1\dec31_dec_sub19_is_32b[0:0] + attribute \src "libresoc.v:90121.3-90139.6" + wire width 4 $1\dec31_dec_sub19_ldst_len[3:0] + attribute \src "libresoc.v:90387.3-90405.6" + wire $1\dec31_dec_sub19_lk[0:0] + attribute \src "libresoc.v:90501.3-90519.6" + wire width 2 $1\dec31_dec_sub19_out_sel[1:0] + attribute \src "libresoc.v:90159.3-90177.6" + wire width 2 $1\dec31_dec_sub19_rc_sel[1:0] + attribute \src "libresoc.v:90330.3-90348.6" + wire $1\dec31_dec_sub19_rsrv[0:0] + attribute \src "libresoc.v:90406.3-90424.6" + wire $1\dec31_dec_sub19_sgl_pipe[0:0] + attribute \src "libresoc.v:90368.3-90386.6" + wire $1\dec31_dec_sub19_sgn[0:0] + attribute \src "libresoc.v:90292.3-90310.6" + wire $1\dec31_dec_sub19_sgn_ext[0:0] + attribute \src "libresoc.v:90140.3-90158.6" + wire width 2 $1\dec31_dec_sub19_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 output 4 \dec31_dec_sub19_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 18 \dec31_dec_sub19_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 9 \dec31_dec_sub19_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 10 \dec31_dec_sub19_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 14 \dec31_dec_sub19_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 17 \dec31_dec_sub19_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 output 3 \dec31_dec_sub19_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \dec31_dec_sub19_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \dec31_dec_sub19_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 6 \dec31_dec_sub19_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 7 \dec31_dec_sub19_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \dec31_dec_sub19_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 15 \dec31_dec_sub19_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 16 \dec31_dec_sub19_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 21 \dec31_dec_sub19_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 11 \dec31_dec_sub19_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 23 \dec31_dec_sub19_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 8 \dec31_dec_sub19_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 13 \dec31_dec_sub19_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 20 \dec31_dec_sub19_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 24 \dec31_dec_sub19_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 22 \dec31_dec_sub19_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 19 \dec31_dec_sub19_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 12 \dec31_dec_sub19_upd + attribute \src "libresoc.v:89845.7-89845.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 5 \opcode_switch + attribute \src "libresoc.v:89845.7-89845.20" + process $proc$libresoc.v:89845$3855 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:90102.3-90120.6" + process $proc$libresoc.v:90102$3831 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_function_unit[11:0] $1\dec31_dec_sub19_function_unit[11:0] + attribute \src "libresoc.v:90103.5-90103.29" + switch \initial + attribute \src "libresoc.v:90103.9-90103.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_function_unit[11:0] 12'000010000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_function_unit[11:0] 12'010000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_function_unit[11:0] 12'010000000000 + case + assign $1\dec31_dec_sub19_function_unit[11:0] 12'000000000000 + end + sync always + update \dec31_dec_sub19_function_unit $0\dec31_dec_sub19_function_unit[11:0] + end + attribute \src "libresoc.v:90121.3-90139.6" + process $proc$libresoc.v:90121$3832 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_ldst_len[3:0] $1\dec31_dec_sub19_ldst_len[3:0] + attribute \src "libresoc.v:90122.5-90122.29" + switch \initial + attribute \src "libresoc.v:90122.9-90122.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_ldst_len[3:0] 4'0000 + case + assign $1\dec31_dec_sub19_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub19_ldst_len $0\dec31_dec_sub19_ldst_len[3:0] + end + attribute \src "libresoc.v:90140.3-90158.6" + process $proc$libresoc.v:90140$3833 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_upd[1:0] $1\dec31_dec_sub19_upd[1:0] + attribute \src "libresoc.v:90141.5-90141.29" + switch \initial + attribute \src "libresoc.v:90141.9-90141.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub19_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub19_upd $0\dec31_dec_sub19_upd[1:0] + end + attribute \src "libresoc.v:90159.3-90177.6" + process $proc$libresoc.v:90159$3834 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_rc_sel[1:0] $1\dec31_dec_sub19_rc_sel[1:0] + attribute \src "libresoc.v:90160.5-90160.29" + switch \initial + attribute \src "libresoc.v:90160.9-90160.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_rc_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub19_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub19_rc_sel $0\dec31_dec_sub19_rc_sel[1:0] + end + attribute \src "libresoc.v:90178.3-90196.6" + process $proc$libresoc.v:90178$3835 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_cry_in[1:0] $1\dec31_dec_sub19_cry_in[1:0] + attribute \src "libresoc.v:90179.5-90179.29" + switch \initial + attribute \src "libresoc.v:90179.9-90179.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_cry_in[1:0] 2'00 + case + assign $1\dec31_dec_sub19_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub19_cry_in $0\dec31_dec_sub19_cry_in[1:0] + end + attribute \src "libresoc.v:90197.3-90215.6" + process $proc$libresoc.v:90197$3836 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_asmcode[7:0] $1\dec31_dec_sub19_asmcode[7:0] + attribute \src "libresoc.v:90198.5-90198.29" + switch \initial + attribute \src "libresoc.v:90198.9-90198.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_asmcode[7:0] 8'01101111 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_asmcode[7:0] 8'01110000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_asmcode[7:0] 8'01110001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_asmcode[7:0] 8'01111001 + case + assign $1\dec31_dec_sub19_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub19_asmcode $0\dec31_dec_sub19_asmcode[7:0] + end + attribute \src "libresoc.v:90216.3-90234.6" + process $proc$libresoc.v:90216$3837 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_inv_a[0:0] $1\dec31_dec_sub19_inv_a[0:0] + attribute \src "libresoc.v:90217.5-90217.29" + switch \initial + attribute \src "libresoc.v:90217.9-90217.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub19_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub19_inv_a $0\dec31_dec_sub19_inv_a[0:0] + end + attribute \src "libresoc.v:90235.3-90253.6" + process $proc$libresoc.v:90235$3838 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_inv_out[0:0] $1\dec31_dec_sub19_inv_out[0:0] + attribute \src "libresoc.v:90236.5-90236.29" + switch \initial + attribute \src "libresoc.v:90236.9-90236.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub19_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub19_inv_out $0\dec31_dec_sub19_inv_out[0:0] + end + attribute \src "libresoc.v:90254.3-90272.6" + process $proc$libresoc.v:90254$3839 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_cry_out[0:0] $1\dec31_dec_sub19_cry_out[0:0] + attribute \src "libresoc.v:90255.5-90255.29" + switch \initial + attribute \src "libresoc.v:90255.9-90255.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_cry_out[0:0] 1'0 + case + assign $1\dec31_dec_sub19_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub19_cry_out $0\dec31_dec_sub19_cry_out[0:0] + end + attribute \src "libresoc.v:90273.3-90291.6" + process $proc$libresoc.v:90273$3840 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_br[0:0] $1\dec31_dec_sub19_br[0:0] + attribute \src "libresoc.v:90274.5-90274.29" + switch \initial + attribute \src "libresoc.v:90274.9-90274.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_br[0:0] 1'0 + case + assign $1\dec31_dec_sub19_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub19_br $0\dec31_dec_sub19_br[0:0] + end + attribute \src "libresoc.v:90292.3-90310.6" + process $proc$libresoc.v:90292$3841 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_sgn_ext[0:0] $1\dec31_dec_sub19_sgn_ext[0:0] + attribute \src "libresoc.v:90293.5-90293.29" + switch \initial + attribute \src "libresoc.v:90293.9-90293.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub19_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub19_sgn_ext $0\dec31_dec_sub19_sgn_ext[0:0] + end + attribute \src "libresoc.v:90311.3-90329.6" + process $proc$libresoc.v:90311$3842 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_internal_op[6:0] $1\dec31_dec_sub19_internal_op[6:0] + attribute \src "libresoc.v:90312.5-90312.29" + switch \initial + attribute \src "libresoc.v:90312.9-90312.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_internal_op[6:0] 7'0101101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_internal_op[6:0] 7'1000111 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_internal_op[6:0] 7'0101110 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_internal_op[6:0] 7'0110001 + case + assign $1\dec31_dec_sub19_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub19_internal_op $0\dec31_dec_sub19_internal_op[6:0] + end + attribute \src "libresoc.v:90330.3-90348.6" + process $proc$libresoc.v:90330$3843 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_rsrv[0:0] $1\dec31_dec_sub19_rsrv[0:0] + attribute \src "libresoc.v:90331.5-90331.29" + switch \initial + attribute \src "libresoc.v:90331.9-90331.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub19_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub19_rsrv $0\dec31_dec_sub19_rsrv[0:0] + end + attribute \src "libresoc.v:90349.3-90367.6" + process $proc$libresoc.v:90349$3844 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_is_32b[0:0] $1\dec31_dec_sub19_is_32b[0:0] + attribute \src "libresoc.v:90350.5-90350.29" + switch \initial + attribute \src "libresoc.v:90350.9-90350.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_is_32b[0:0] 1'0 + case + assign $1\dec31_dec_sub19_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub19_is_32b $0\dec31_dec_sub19_is_32b[0:0] + end + attribute \src "libresoc.v:90368.3-90386.6" + process $proc$libresoc.v:90368$3845 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_sgn[0:0] $1\dec31_dec_sub19_sgn[0:0] + attribute \src "libresoc.v:90369.5-90369.29" + switch \initial + attribute \src "libresoc.v:90369.9-90369.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_sgn[0:0] 1'0 + case + assign $1\dec31_dec_sub19_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub19_sgn $0\dec31_dec_sub19_sgn[0:0] + end + attribute \src "libresoc.v:90387.3-90405.6" + process $proc$libresoc.v:90387$3846 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_lk[0:0] $1\dec31_dec_sub19_lk[0:0] + attribute \src "libresoc.v:90388.5-90388.29" + switch \initial + attribute \src "libresoc.v:90388.9-90388.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub19_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub19_lk $0\dec31_dec_sub19_lk[0:0] + end + attribute \src "libresoc.v:90406.3-90424.6" + process $proc$libresoc.v:90406$3847 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_sgl_pipe[0:0] $1\dec31_dec_sub19_sgl_pipe[0:0] + attribute \src "libresoc.v:90407.5-90407.29" + switch \initial + attribute \src "libresoc.v:90407.9-90407.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_sgl_pipe[0:0] 1'0 + case + assign $1\dec31_dec_sub19_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub19_sgl_pipe $0\dec31_dec_sub19_sgl_pipe[0:0] + end + attribute \src "libresoc.v:90425.3-90443.6" + process $proc$libresoc.v:90425$3848 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_form[4:0] $1\dec31_dec_sub19_form[4:0] + attribute \src "libresoc.v:90426.5-90426.29" + switch \initial + attribute \src "libresoc.v:90426.9-90426.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_form[4:0] 5'01010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_form[4:0] 5'01010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_form[4:0] 5'01010 + case + assign $1\dec31_dec_sub19_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub19_form $0\dec31_dec_sub19_form[4:0] + end + attribute \src "libresoc.v:90444.3-90462.6" + process $proc$libresoc.v:90444$3849 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_in1_sel[2:0] $1\dec31_dec_sub19_in1_sel[2:0] + attribute \src "libresoc.v:90445.5-90445.29" + switch \initial + attribute \src "libresoc.v:90445.9-90445.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_in1_sel[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_in1_sel[2:0] 3'100 + case + assign $1\dec31_dec_sub19_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub19_in1_sel $0\dec31_dec_sub19_in1_sel[2:0] + end + attribute \src "libresoc.v:90463.3-90481.6" + process $proc$libresoc.v:90463$3850 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_in2_sel[3:0] $1\dec31_dec_sub19_in2_sel[3:0] + attribute \src "libresoc.v:90464.5-90464.29" + switch \initial + attribute \src "libresoc.v:90464.9-90464.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_in2_sel[3:0] 4'0000 + case + assign $1\dec31_dec_sub19_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub19_in2_sel $0\dec31_dec_sub19_in2_sel[3:0] + end + attribute \src "libresoc.v:90482.3-90500.6" + process $proc$libresoc.v:90482$3851 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_in3_sel[1:0] $1\dec31_dec_sub19_in3_sel[1:0] + attribute \src "libresoc.v:90483.5-90483.29" + switch \initial + attribute \src "libresoc.v:90483.9-90483.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_in3_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub19_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub19_in3_sel $0\dec31_dec_sub19_in3_sel[1:0] + end + attribute \src "libresoc.v:90501.3-90519.6" + process $proc$libresoc.v:90501$3852 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_out_sel[1:0] $1\dec31_dec_sub19_out_sel[1:0] + attribute \src "libresoc.v:90502.5-90502.29" + switch \initial + attribute \src "libresoc.v:90502.9-90502.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_out_sel[1:0] 2'11 + case + assign $1\dec31_dec_sub19_out_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub19_out_sel $0\dec31_dec_sub19_out_sel[1:0] + end + attribute \src "libresoc.v:90520.3-90538.6" + process $proc$libresoc.v:90520$3853 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_cr_in[2:0] $1\dec31_dec_sub19_cr_in[2:0] + attribute \src "libresoc.v:90521.5-90521.29" + switch \initial + attribute \src "libresoc.v:90521.9-90521.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_cr_in[2:0] 3'110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub19_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub19_cr_in $0\dec31_dec_sub19_cr_in[2:0] + end + attribute \src "libresoc.v:90539.3-90557.6" + process $proc$libresoc.v:90539$3854 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_cr_out[2:0] $1\dec31_dec_sub19_cr_out[2:0] + attribute \src "libresoc.v:90540.5-90540.29" + switch \initial + attribute \src "libresoc.v:90540.9-90540.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_cr_out[2:0] 3'000 + case + assign $1\dec31_dec_sub19_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub19_cr_out $0\dec31_dec_sub19_cr_out[2:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:90563.1-91422.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec31_dec_sub20" +attribute \generator "nMigen" +module \dec31_dec_sub20 + attribute \src "libresoc.v:90946.3-90970.6" + wire width 8 $0\dec31_dec_sub20_asmcode[7:0] + attribute \src "libresoc.v:91046.3-91070.6" + wire $0\dec31_dec_sub20_br[0:0] + attribute \src "libresoc.v:91371.3-91395.6" + wire width 3 $0\dec31_dec_sub20_cr_in[2:0] + attribute \src "libresoc.v:91396.3-91420.6" + wire width 3 $0\dec31_dec_sub20_cr_out[2:0] + attribute \src "libresoc.v:90921.3-90945.6" + wire width 2 $0\dec31_dec_sub20_cry_in[1:0] + attribute \src "libresoc.v:91021.3-91045.6" + wire $0\dec31_dec_sub20_cry_out[0:0] + attribute \src "libresoc.v:91246.3-91270.6" + wire width 5 $0\dec31_dec_sub20_form[4:0] + attribute \src "libresoc.v:90821.3-90845.6" + wire width 12 $0\dec31_dec_sub20_function_unit[11:0] + attribute \src "libresoc.v:91271.3-91295.6" + wire width 3 $0\dec31_dec_sub20_in1_sel[2:0] + attribute \src "libresoc.v:91296.3-91320.6" + wire width 4 $0\dec31_dec_sub20_in2_sel[3:0] + attribute \src "libresoc.v:91321.3-91345.6" + wire width 2 $0\dec31_dec_sub20_in3_sel[1:0] + attribute \src "libresoc.v:91096.3-91120.6" + wire width 7 $0\dec31_dec_sub20_internal_op[6:0] + attribute \src "libresoc.v:90971.3-90995.6" + wire $0\dec31_dec_sub20_inv_a[0:0] + attribute \src "libresoc.v:90996.3-91020.6" + wire $0\dec31_dec_sub20_inv_out[0:0] + attribute \src "libresoc.v:91146.3-91170.6" + wire $0\dec31_dec_sub20_is_32b[0:0] + attribute \src "libresoc.v:90846.3-90870.6" + wire width 4 $0\dec31_dec_sub20_ldst_len[3:0] + attribute \src "libresoc.v:91196.3-91220.6" + wire $0\dec31_dec_sub20_lk[0:0] + attribute \src "libresoc.v:91346.3-91370.6" + wire width 2 $0\dec31_dec_sub20_out_sel[1:0] + attribute \src "libresoc.v:90896.3-90920.6" + wire width 2 $0\dec31_dec_sub20_rc_sel[1:0] + attribute \src "libresoc.v:91121.3-91145.6" + wire $0\dec31_dec_sub20_rsrv[0:0] + attribute \src "libresoc.v:91221.3-91245.6" + wire $0\dec31_dec_sub20_sgl_pipe[0:0] + attribute \src "libresoc.v:91171.3-91195.6" + wire $0\dec31_dec_sub20_sgn[0:0] + attribute \src "libresoc.v:91071.3-91095.6" + wire $0\dec31_dec_sub20_sgn_ext[0:0] + attribute \src "libresoc.v:90871.3-90895.6" + wire width 2 $0\dec31_dec_sub20_upd[1:0] + attribute \src "libresoc.v:90564.7-90564.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:90946.3-90970.6" + wire width 8 $1\dec31_dec_sub20_asmcode[7:0] + attribute \src "libresoc.v:91046.3-91070.6" + wire $1\dec31_dec_sub20_br[0:0] + attribute \src "libresoc.v:91371.3-91395.6" + wire width 3 $1\dec31_dec_sub20_cr_in[2:0] + attribute \src "libresoc.v:91396.3-91420.6" + wire width 3 $1\dec31_dec_sub20_cr_out[2:0] + attribute \src "libresoc.v:90921.3-90945.6" + wire width 2 $1\dec31_dec_sub20_cry_in[1:0] + attribute \src "libresoc.v:91021.3-91045.6" + wire $1\dec31_dec_sub20_cry_out[0:0] + attribute \src "libresoc.v:91246.3-91270.6" + wire width 5 $1\dec31_dec_sub20_form[4:0] + attribute \src "libresoc.v:90821.3-90845.6" + wire width 12 $1\dec31_dec_sub20_function_unit[11:0] + attribute \src "libresoc.v:91271.3-91295.6" + wire width 3 $1\dec31_dec_sub20_in1_sel[2:0] + attribute \src "libresoc.v:91296.3-91320.6" + wire width 4 $1\dec31_dec_sub20_in2_sel[3:0] + attribute \src "libresoc.v:91321.3-91345.6" + wire width 2 $1\dec31_dec_sub20_in3_sel[1:0] + attribute \src "libresoc.v:91096.3-91120.6" + wire width 7 $1\dec31_dec_sub20_internal_op[6:0] + attribute \src "libresoc.v:90971.3-90995.6" + wire $1\dec31_dec_sub20_inv_a[0:0] + attribute \src "libresoc.v:90996.3-91020.6" + wire $1\dec31_dec_sub20_inv_out[0:0] + attribute \src "libresoc.v:91146.3-91170.6" + wire $1\dec31_dec_sub20_is_32b[0:0] + attribute \src "libresoc.v:90846.3-90870.6" + wire width 4 $1\dec31_dec_sub20_ldst_len[3:0] + attribute \src "libresoc.v:91196.3-91220.6" + wire $1\dec31_dec_sub20_lk[0:0] + attribute \src "libresoc.v:91346.3-91370.6" + wire width 2 $1\dec31_dec_sub20_out_sel[1:0] + attribute \src "libresoc.v:90896.3-90920.6" + wire width 2 $1\dec31_dec_sub20_rc_sel[1:0] + attribute \src "libresoc.v:91121.3-91145.6" + wire $1\dec31_dec_sub20_rsrv[0:0] + attribute \src "libresoc.v:91221.3-91245.6" + wire $1\dec31_dec_sub20_sgl_pipe[0:0] + attribute \src "libresoc.v:91171.3-91195.6" + wire $1\dec31_dec_sub20_sgn[0:0] + attribute \src "libresoc.v:91071.3-91095.6" + wire $1\dec31_dec_sub20_sgn_ext[0:0] + attribute \src "libresoc.v:90871.3-90895.6" + wire width 2 $1\dec31_dec_sub20_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 output 4 \dec31_dec_sub20_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 18 \dec31_dec_sub20_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 9 \dec31_dec_sub20_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 10 \dec31_dec_sub20_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 14 \dec31_dec_sub20_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 17 \dec31_dec_sub20_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 output 3 \dec31_dec_sub20_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \dec31_dec_sub20_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \dec31_dec_sub20_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 6 \dec31_dec_sub20_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 7 \dec31_dec_sub20_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \dec31_dec_sub20_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 15 \dec31_dec_sub20_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 16 \dec31_dec_sub20_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 21 \dec31_dec_sub20_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 11 \dec31_dec_sub20_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 23 \dec31_dec_sub20_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 8 \dec31_dec_sub20_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 13 \dec31_dec_sub20_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 20 \dec31_dec_sub20_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 24 \dec31_dec_sub20_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 22 \dec31_dec_sub20_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 19 \dec31_dec_sub20_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 12 \dec31_dec_sub20_upd + attribute \src "libresoc.v:90564.7-90564.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 5 \opcode_switch + attribute \src "libresoc.v:90564.7-90564.20" + process $proc$libresoc.v:90564$3880 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:90821.3-90845.6" + process $proc$libresoc.v:90821$3856 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_function_unit[11:0] $1\dec31_dec_sub20_function_unit[11:0] + attribute \src "libresoc.v:90822.5-90822.29" + switch \initial + attribute \src "libresoc.v:90822.9-90822.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_function_unit[11:0] 12'000000000100 + case + assign $1\dec31_dec_sub20_function_unit[11:0] 12'000000000000 + end + sync always + update \dec31_dec_sub20_function_unit $0\dec31_dec_sub20_function_unit[11:0] + end + attribute \src "libresoc.v:90846.3-90870.6" + process $proc$libresoc.v:90846$3857 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_ldst_len[3:0] $1\dec31_dec_sub20_ldst_len[3:0] + attribute \src "libresoc.v:90847.5-90847.29" + switch \initial + attribute \src "libresoc.v:90847.9-90847.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_ldst_len[3:0] 4'1000 + case + assign $1\dec31_dec_sub20_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub20_ldst_len $0\dec31_dec_sub20_ldst_len[3:0] + end + attribute \src "libresoc.v:90871.3-90895.6" + process $proc$libresoc.v:90871$3858 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_upd[1:0] $1\dec31_dec_sub20_upd[1:0] + attribute \src "libresoc.v:90872.5-90872.29" + switch \initial + attribute \src "libresoc.v:90872.9-90872.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub20_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub20_upd $0\dec31_dec_sub20_upd[1:0] + end + attribute \src "libresoc.v:90896.3-90920.6" + process $proc$libresoc.v:90896$3859 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_rc_sel[1:0] $1\dec31_dec_sub20_rc_sel[1:0] + attribute \src "libresoc.v:90897.5-90897.29" + switch \initial + attribute \src "libresoc.v:90897.9-90897.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_rc_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub20_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub20_rc_sel $0\dec31_dec_sub20_rc_sel[1:0] + end + attribute \src "libresoc.v:90921.3-90945.6" + process $proc$libresoc.v:90921$3860 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_cry_in[1:0] $1\dec31_dec_sub20_cry_in[1:0] + attribute \src "libresoc.v:90922.5-90922.29" + switch \initial + attribute \src "libresoc.v:90922.9-90922.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_cry_in[1:0] 2'00 + case + assign $1\dec31_dec_sub20_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub20_cry_in $0\dec31_dec_sub20_cry_in[1:0] + end + attribute \src "libresoc.v:90946.3-90970.6" + process $proc$libresoc.v:90946$3861 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_asmcode[7:0] $1\dec31_dec_sub20_asmcode[7:0] + attribute \src "libresoc.v:90947.5-90947.29" + switch \initial + attribute \src "libresoc.v:90947.9-90947.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_asmcode[7:0] 8'01001101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_asmcode[7:0] 8'01010011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_asmcode[7:0] 8'01010100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_asmcode[7:0] 8'01011001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_asmcode[7:0] 8'01100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_asmcode[7:0] 8'10101101 + case + assign $1\dec31_dec_sub20_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub20_asmcode $0\dec31_dec_sub20_asmcode[7:0] + end + attribute \src "libresoc.v:90971.3-90995.6" + process $proc$libresoc.v:90971$3862 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_inv_a[0:0] $1\dec31_dec_sub20_inv_a[0:0] + attribute \src "libresoc.v:90972.5-90972.29" + switch \initial + attribute \src "libresoc.v:90972.9-90972.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub20_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub20_inv_a $0\dec31_dec_sub20_inv_a[0:0] + end + attribute \src "libresoc.v:90996.3-91020.6" + process $proc$libresoc.v:90996$3863 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_inv_out[0:0] $1\dec31_dec_sub20_inv_out[0:0] + attribute \src "libresoc.v:90997.5-90997.29" + switch \initial + attribute \src "libresoc.v:90997.9-90997.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub20_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub20_inv_out $0\dec31_dec_sub20_inv_out[0:0] + end + attribute \src "libresoc.v:91021.3-91045.6" + process $proc$libresoc.v:91021$3864 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_cry_out[0:0] $1\dec31_dec_sub20_cry_out[0:0] + attribute \src "libresoc.v:91022.5-91022.29" + switch \initial + attribute \src "libresoc.v:91022.9-91022.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_cry_out[0:0] 1'0 + case + assign $1\dec31_dec_sub20_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub20_cry_out $0\dec31_dec_sub20_cry_out[0:0] + end + attribute \src "libresoc.v:91046.3-91070.6" + process $proc$libresoc.v:91046$3865 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_br[0:0] $1\dec31_dec_sub20_br[0:0] + attribute \src "libresoc.v:91047.5-91047.29" + switch \initial + attribute \src "libresoc.v:91047.9-91047.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_br[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_br[0:0] 1'1 + case + assign $1\dec31_dec_sub20_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub20_br $0\dec31_dec_sub20_br[0:0] + end + attribute \src "libresoc.v:91071.3-91095.6" + process $proc$libresoc.v:91071$3866 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_sgn_ext[0:0] $1\dec31_dec_sub20_sgn_ext[0:0] + attribute \src "libresoc.v:91072.5-91072.29" + switch \initial + attribute \src "libresoc.v:91072.9-91072.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub20_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub20_sgn_ext $0\dec31_dec_sub20_sgn_ext[0:0] + end + attribute \src "libresoc.v:91096.3-91120.6" + process $proc$libresoc.v:91096$3867 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_internal_op[6:0] $1\dec31_dec_sub20_internal_op[6:0] + attribute \src "libresoc.v:91097.5-91097.29" + switch \initial + attribute \src "libresoc.v:91097.9-91097.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_internal_op[6:0] 7'0100110 + case + assign $1\dec31_dec_sub20_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub20_internal_op $0\dec31_dec_sub20_internal_op[6:0] + end + attribute \src "libresoc.v:91121.3-91145.6" + process $proc$libresoc.v:91121$3868 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_rsrv[0:0] $1\dec31_dec_sub20_rsrv[0:0] + attribute \src "libresoc.v:91122.5-91122.29" + switch \initial + attribute \src "libresoc.v:91122.9-91122.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_rsrv[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_rsrv[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_rsrv[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_rsrv[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub20_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub20_rsrv $0\dec31_dec_sub20_rsrv[0:0] + end + attribute \src "libresoc.v:91146.3-91170.6" + process $proc$libresoc.v:91146$3869 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_is_32b[0:0] $1\dec31_dec_sub20_is_32b[0:0] + attribute \src "libresoc.v:91147.5-91147.29" + switch \initial + attribute \src "libresoc.v:91147.9-91147.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 + case + assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub20_is_32b $0\dec31_dec_sub20_is_32b[0:0] + end + attribute \src "libresoc.v:91171.3-91195.6" + process $proc$libresoc.v:91171$3870 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_sgn[0:0] $1\dec31_dec_sub20_sgn[0:0] + attribute \src "libresoc.v:91172.5-91172.29" + switch \initial + attribute \src "libresoc.v:91172.9-91172.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_sgn[0:0] 1'0 + case + assign $1\dec31_dec_sub20_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub20_sgn $0\dec31_dec_sub20_sgn[0:0] + end + attribute \src "libresoc.v:91196.3-91220.6" + process $proc$libresoc.v:91196$3871 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_lk[0:0] $1\dec31_dec_sub20_lk[0:0] + attribute \src "libresoc.v:91197.5-91197.29" + switch \initial + attribute \src "libresoc.v:91197.9-91197.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub20_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub20_lk $0\dec31_dec_sub20_lk[0:0] + end + attribute \src "libresoc.v:91221.3-91245.6" + process $proc$libresoc.v:91221$3872 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_sgl_pipe[0:0] $1\dec31_dec_sub20_sgl_pipe[0:0] + attribute \src "libresoc.v:91222.5-91222.29" + switch \initial + attribute \src "libresoc.v:91222.9-91222.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'1 + case + assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub20_sgl_pipe $0\dec31_dec_sub20_sgl_pipe[0:0] + end + attribute \src "libresoc.v:91246.3-91270.6" + process $proc$libresoc.v:91246$3873 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_form[4:0] $1\dec31_dec_sub20_form[4:0] + attribute \src "libresoc.v:91247.5-91247.29" + switch \initial + attribute \src "libresoc.v:91247.9-91247.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_form[4:0] 5'01000 + case + assign $1\dec31_dec_sub20_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub20_form $0\dec31_dec_sub20_form[4:0] + end + attribute \src "libresoc.v:91271.3-91295.6" + process $proc$libresoc.v:91271$3874 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_in1_sel[2:0] $1\dec31_dec_sub20_in1_sel[2:0] + attribute \src "libresoc.v:91272.5-91272.29" + switch \initial + attribute \src "libresoc.v:91272.9-91272.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_in1_sel[2:0] 3'010 + case + assign $1\dec31_dec_sub20_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub20_in1_sel $0\dec31_dec_sub20_in1_sel[2:0] + end + attribute \src "libresoc.v:91296.3-91320.6" + process $proc$libresoc.v:91296$3875 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_in2_sel[3:0] $1\dec31_dec_sub20_in2_sel[3:0] + attribute \src "libresoc.v:91297.5-91297.29" + switch \initial + attribute \src "libresoc.v:91297.9-91297.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0001 + case + assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub20_in2_sel $0\dec31_dec_sub20_in2_sel[3:0] + end + attribute \src "libresoc.v:91321.3-91345.6" + process $proc$libresoc.v:91321$3876 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_in3_sel[1:0] $1\dec31_dec_sub20_in3_sel[1:0] + attribute \src "libresoc.v:91322.5-91322.29" + switch \initial + attribute \src "libresoc.v:91322.9-91322.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_in3_sel[1:0] 2'01 + case + assign $1\dec31_dec_sub20_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub20_in3_sel $0\dec31_dec_sub20_in3_sel[1:0] + end + attribute \src "libresoc.v:91346.3-91370.6" + process $proc$libresoc.v:91346$3877 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_out_sel[1:0] $1\dec31_dec_sub20_out_sel[1:0] + attribute \src "libresoc.v:91347.5-91347.29" + switch \initial + attribute \src "libresoc.v:91347.9-91347.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_out_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub20_out_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub20_out_sel $0\dec31_dec_sub20_out_sel[1:0] + end + attribute \src "libresoc.v:91371.3-91395.6" + process $proc$libresoc.v:91371$3878 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_cr_in[2:0] $1\dec31_dec_sub20_cr_in[2:0] + attribute \src "libresoc.v:91372.5-91372.29" + switch \initial + attribute \src "libresoc.v:91372.9-91372.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub20_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub20_cr_in $0\dec31_dec_sub20_cr_in[2:0] + end + attribute \src "libresoc.v:91396.3-91420.6" + process $proc$libresoc.v:91396$3879 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_cr_out[2:0] $1\dec31_dec_sub20_cr_out[2:0] + attribute \src "libresoc.v:91397.5-91397.29" + switch \initial + attribute \src "libresoc.v:91397.9-91397.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_cr_out[2:0] 3'000 + case + assign $1\dec31_dec_sub20_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub20_cr_out $0\dec31_dec_sub20_cr_out[2:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:91426.1-92843.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec31_dec_sub21" +attribute \generator "nMigen" +module \dec31_dec_sub21 + attribute \src "libresoc.v:92468.3-92498.6" + wire width 8 $0\dec31_dec_sub21_asmcode[7:0] + attribute \src "libresoc.v:92076.3-92124.6" + wire $0\dec31_dec_sub21_br[0:0] + attribute \src "libresoc.v:92744.3-92792.6" + wire width 3 $0\dec31_dec_sub21_cr_in[2:0] + attribute \src "libresoc.v:92793.3-92841.6" + wire width 3 $0\dec31_dec_sub21_cr_out[2:0] + attribute \src "libresoc.v:91880.3-91928.6" + wire width 2 $0\dec31_dec_sub21_cry_in[1:0] + attribute \src "libresoc.v:92027.3-92075.6" + wire $0\dec31_dec_sub21_cry_out[0:0] + attribute \src "libresoc.v:92499.3-92547.6" + wire width 5 $0\dec31_dec_sub21_form[4:0] + attribute \src "libresoc.v:91684.3-91732.6" + wire width 12 $0\dec31_dec_sub21_function_unit[11:0] + attribute \src "libresoc.v:92548.3-92596.6" + wire width 3 $0\dec31_dec_sub21_in1_sel[2:0] + attribute \src "libresoc.v:92597.3-92645.6" + wire width 4 $0\dec31_dec_sub21_in2_sel[3:0] + attribute \src "libresoc.v:92646.3-92694.6" + wire width 2 $0\dec31_dec_sub21_in3_sel[1:0] + attribute \src "libresoc.v:92223.3-92271.6" + wire width 7 $0\dec31_dec_sub21_internal_op[6:0] + attribute \src "libresoc.v:91929.3-91977.6" + wire $0\dec31_dec_sub21_inv_a[0:0] + attribute \src "libresoc.v:91978.3-92026.6" + wire $0\dec31_dec_sub21_inv_out[0:0] + attribute \src "libresoc.v:92272.3-92320.6" + wire $0\dec31_dec_sub21_is_32b[0:0] + attribute \src "libresoc.v:91733.3-91781.6" + wire width 4 $0\dec31_dec_sub21_ldst_len[3:0] + attribute \src "libresoc.v:92370.3-92418.6" + wire $0\dec31_dec_sub21_lk[0:0] + attribute \src "libresoc.v:92695.3-92743.6" + wire width 2 $0\dec31_dec_sub21_out_sel[1:0] + attribute \src "libresoc.v:91831.3-91879.6" + wire width 2 $0\dec31_dec_sub21_rc_sel[1:0] + attribute \src "libresoc.v:92174.3-92222.6" + wire $0\dec31_dec_sub21_rsrv[0:0] + attribute \src "libresoc.v:92419.3-92467.6" + wire $0\dec31_dec_sub21_sgl_pipe[0:0] + attribute \src "libresoc.v:92321.3-92369.6" + wire $0\dec31_dec_sub21_sgn[0:0] + attribute \src "libresoc.v:92125.3-92173.6" + wire $0\dec31_dec_sub21_sgn_ext[0:0] + attribute \src "libresoc.v:91782.3-91830.6" + wire width 2 $0\dec31_dec_sub21_upd[1:0] + attribute \src "libresoc.v:91427.7-91427.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:92468.3-92498.6" + wire width 8 $1\dec31_dec_sub21_asmcode[7:0] + attribute \src "libresoc.v:92076.3-92124.6" + wire $1\dec31_dec_sub21_br[0:0] + attribute \src "libresoc.v:92744.3-92792.6" + wire width 3 $1\dec31_dec_sub21_cr_in[2:0] + attribute \src "libresoc.v:92793.3-92841.6" + wire width 3 $1\dec31_dec_sub21_cr_out[2:0] + attribute \src "libresoc.v:91880.3-91928.6" + wire width 2 $1\dec31_dec_sub21_cry_in[1:0] + attribute \src "libresoc.v:92027.3-92075.6" + wire $1\dec31_dec_sub21_cry_out[0:0] + attribute \src "libresoc.v:92499.3-92547.6" + wire width 5 $1\dec31_dec_sub21_form[4:0] + attribute \src "libresoc.v:91684.3-91732.6" + wire width 12 $1\dec31_dec_sub21_function_unit[11:0] + attribute \src "libresoc.v:92548.3-92596.6" + wire width 3 $1\dec31_dec_sub21_in1_sel[2:0] + attribute \src "libresoc.v:92597.3-92645.6" + wire width 4 $1\dec31_dec_sub21_in2_sel[3:0] + attribute \src "libresoc.v:92646.3-92694.6" + wire width 2 $1\dec31_dec_sub21_in3_sel[1:0] + attribute \src "libresoc.v:92223.3-92271.6" + wire width 7 $1\dec31_dec_sub21_internal_op[6:0] + attribute \src "libresoc.v:91929.3-91977.6" + wire $1\dec31_dec_sub21_inv_a[0:0] + attribute \src "libresoc.v:91978.3-92026.6" + wire $1\dec31_dec_sub21_inv_out[0:0] + attribute \src "libresoc.v:92272.3-92320.6" + wire $1\dec31_dec_sub21_is_32b[0:0] + attribute \src "libresoc.v:91733.3-91781.6" + wire width 4 $1\dec31_dec_sub21_ldst_len[3:0] + attribute \src "libresoc.v:92370.3-92418.6" + wire $1\dec31_dec_sub21_lk[0:0] + attribute \src "libresoc.v:92695.3-92743.6" + wire width 2 $1\dec31_dec_sub21_out_sel[1:0] + attribute \src "libresoc.v:91831.3-91879.6" + wire width 2 $1\dec31_dec_sub21_rc_sel[1:0] + attribute \src "libresoc.v:92174.3-92222.6" + wire $1\dec31_dec_sub21_rsrv[0:0] + attribute \src "libresoc.v:92419.3-92467.6" + wire $1\dec31_dec_sub21_sgl_pipe[0:0] + attribute \src "libresoc.v:92321.3-92369.6" + wire $1\dec31_dec_sub21_sgn[0:0] + attribute \src "libresoc.v:92125.3-92173.6" + wire $1\dec31_dec_sub21_sgn_ext[0:0] + attribute \src "libresoc.v:91782.3-91830.6" + wire width 2 $1\dec31_dec_sub21_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 output 4 \dec31_dec_sub21_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 18 \dec31_dec_sub21_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 9 \dec31_dec_sub21_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 10 \dec31_dec_sub21_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 14 \dec31_dec_sub21_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 17 \dec31_dec_sub21_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 output 3 \dec31_dec_sub21_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \dec31_dec_sub21_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \dec31_dec_sub21_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 6 \dec31_dec_sub21_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 7 \dec31_dec_sub21_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \dec31_dec_sub21_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 15 \dec31_dec_sub21_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 16 \dec31_dec_sub21_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 21 \dec31_dec_sub21_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 11 \dec31_dec_sub21_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 23 \dec31_dec_sub21_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 8 \dec31_dec_sub21_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 13 \dec31_dec_sub21_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 20 \dec31_dec_sub21_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 24 \dec31_dec_sub21_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 22 \dec31_dec_sub21_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 19 \dec31_dec_sub21_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 12 \dec31_dec_sub21_upd + attribute \src "libresoc.v:91427.7-91427.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 5 \opcode_switch + attribute \src "libresoc.v:91427.7-91427.20" + process $proc$libresoc.v:91427$3905 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:91684.3-91732.6" + process $proc$libresoc.v:91684$3881 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_function_unit[11:0] $1\dec31_dec_sub21_function_unit[11:0] + attribute \src "libresoc.v:91685.5-91685.29" + switch \initial + attribute \src "libresoc.v:91685.9-91685.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 + case + assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000000 + end + sync always + update \dec31_dec_sub21_function_unit $0\dec31_dec_sub21_function_unit[11:0] + end + attribute \src "libresoc.v:91733.3-91781.6" + process $proc$libresoc.v:91733$3882 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_ldst_len[3:0] $1\dec31_dec_sub21_ldst_len[3:0] + attribute \src "libresoc.v:91734.5-91734.29" + switch \initial + attribute \src "libresoc.v:91734.9-91734.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0100 + case + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub21_ldst_len $0\dec31_dec_sub21_ldst_len[3:0] + end + attribute \src "libresoc.v:91782.3-91830.6" + process $proc$libresoc.v:91782$3883 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_upd[1:0] $1\dec31_dec_sub21_upd[1:0] + attribute \src "libresoc.v:91783.5-91783.29" + switch \initial + attribute \src "libresoc.v:91783.9-91783.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_upd[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_upd[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_upd[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_upd[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_upd[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_upd[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_upd[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_upd[1:0] 2'10 + case + assign $1\dec31_dec_sub21_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub21_upd $0\dec31_dec_sub21_upd[1:0] + end + attribute \src "libresoc.v:91831.3-91879.6" + process $proc$libresoc.v:91831$3884 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_rc_sel[1:0] $1\dec31_dec_sub21_rc_sel[1:0] + attribute \src "libresoc.v:91832.5-91832.29" + switch \initial + attribute \src "libresoc.v:91832.9-91832.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub21_rc_sel $0\dec31_dec_sub21_rc_sel[1:0] + end + attribute \src "libresoc.v:91880.3-91928.6" + process $proc$libresoc.v:91880$3885 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_cry_in[1:0] $1\dec31_dec_sub21_cry_in[1:0] + attribute \src "libresoc.v:91881.5-91881.29" + switch \initial + attribute \src "libresoc.v:91881.9-91881.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + case + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub21_cry_in $0\dec31_dec_sub21_cry_in[1:0] + end + attribute \src "libresoc.v:91929.3-91977.6" + process $proc$libresoc.v:91929$3886 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_inv_a[0:0] $1\dec31_dec_sub21_inv_a[0:0] + attribute \src "libresoc.v:91930.5-91930.29" + switch \initial + attribute \src "libresoc.v:91930.9-91930.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub21_inv_a $0\dec31_dec_sub21_inv_a[0:0] + end + attribute \src "libresoc.v:91978.3-92026.6" + process $proc$libresoc.v:91978$3887 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_inv_out[0:0] $1\dec31_dec_sub21_inv_out[0:0] + attribute \src "libresoc.v:91979.5-91979.29" + switch \initial + attribute \src "libresoc.v:91979.9-91979.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub21_inv_out $0\dec31_dec_sub21_inv_out[0:0] + end + attribute \src "libresoc.v:92027.3-92075.6" + process $proc$libresoc.v:92027$3888 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_cry_out[0:0] $1\dec31_dec_sub21_cry_out[0:0] + attribute \src "libresoc.v:92028.5-92028.29" + switch \initial + attribute \src "libresoc.v:92028.9-92028.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + case + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub21_cry_out $0\dec31_dec_sub21_cry_out[0:0] + end + attribute \src "libresoc.v:92076.3-92124.6" + process $proc$libresoc.v:92076$3889 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_br[0:0] $1\dec31_dec_sub21_br[0:0] + attribute \src "libresoc.v:92077.5-92077.29" + switch \initial + attribute \src "libresoc.v:92077.9-92077.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_br[0:0] 1'0 + case + assign $1\dec31_dec_sub21_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub21_br $0\dec31_dec_sub21_br[0:0] + end + attribute \src "libresoc.v:92125.3-92173.6" + process $proc$libresoc.v:92125$3890 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_sgn_ext[0:0] $1\dec31_dec_sub21_sgn_ext[0:0] + attribute \src "libresoc.v:92126.5-92126.29" + switch \initial + attribute \src "libresoc.v:92126.9-92126.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub21_sgn_ext $0\dec31_dec_sub21_sgn_ext[0:0] + end + attribute \src "libresoc.v:92174.3-92222.6" + process $proc$libresoc.v:92174$3891 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_rsrv[0:0] $1\dec31_dec_sub21_rsrv[0:0] + attribute \src "libresoc.v:92175.5-92175.29" + switch \initial + attribute \src "libresoc.v:92175.9-92175.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub21_rsrv $0\dec31_dec_sub21_rsrv[0:0] + end + attribute \src "libresoc.v:92223.3-92271.6" + process $proc$libresoc.v:92223$3892 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_internal_op[6:0] $1\dec31_dec_sub21_internal_op[6:0] + attribute \src "libresoc.v:92224.5-92224.29" + switch \initial + attribute \src "libresoc.v:92224.9-92224.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100110 + case + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub21_internal_op $0\dec31_dec_sub21_internal_op[6:0] + end + attribute \src "libresoc.v:92272.3-92320.6" + process $proc$libresoc.v:92272$3893 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_is_32b[0:0] $1\dec31_dec_sub21_is_32b[0:0] + attribute \src "libresoc.v:92273.5-92273.29" + switch \initial + attribute \src "libresoc.v:92273.9-92273.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + case + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub21_is_32b $0\dec31_dec_sub21_is_32b[0:0] + end + attribute \src "libresoc.v:92321.3-92369.6" + process $proc$libresoc.v:92321$3894 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_sgn[0:0] $1\dec31_dec_sub21_sgn[0:0] + attribute \src "libresoc.v:92322.5-92322.29" + switch \initial + attribute \src "libresoc.v:92322.9-92322.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + case + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub21_sgn $0\dec31_dec_sub21_sgn[0:0] + end + attribute \src "libresoc.v:92370.3-92418.6" + process $proc$libresoc.v:92370$3895 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_lk[0:0] $1\dec31_dec_sub21_lk[0:0] + attribute \src "libresoc.v:92371.5-92371.29" + switch \initial + attribute \src "libresoc.v:92371.9-92371.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub21_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub21_lk $0\dec31_dec_sub21_lk[0:0] + end + attribute \src "libresoc.v:92419.3-92467.6" + process $proc$libresoc.v:92419$3896 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_sgl_pipe[0:0] $1\dec31_dec_sub21_sgl_pipe[0:0] + attribute \src "libresoc.v:92420.5-92420.29" + switch \initial + attribute \src "libresoc.v:92420.9-92420.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 + case + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub21_sgl_pipe $0\dec31_dec_sub21_sgl_pipe[0:0] + end + attribute \src "libresoc.v:92468.3-92498.6" + process $proc$libresoc.v:92468$3897 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_asmcode[7:0] $1\dec31_dec_sub21_asmcode[7:0] + attribute \src "libresoc.v:92469.5-92469.29" + switch \initial + attribute \src "libresoc.v:92469.9-92469.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_asmcode[7:0] 8'01010110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_asmcode[7:0] 8'01010111 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_asmcode[7:0] 8'01100100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_asmcode[7:0] 8'01100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_asmcode[7:0] 8'01101000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_asmcode[7:0] 8'10100111 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_asmcode[7:0] 8'10110000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_asmcode[7:0] 8'10110001 + case + assign $1\dec31_dec_sub21_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub21_asmcode $0\dec31_dec_sub21_asmcode[7:0] + end + attribute \src "libresoc.v:92499.3-92547.6" + process $proc$libresoc.v:92499$3898 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_form[4:0] $1\dec31_dec_sub21_form[4:0] + attribute \src "libresoc.v:92500.5-92500.29" + switch \initial + attribute \src "libresoc.v:92500.9-92500.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_form[4:0] 5'01000 + case + assign $1\dec31_dec_sub21_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub21_form $0\dec31_dec_sub21_form[4:0] + end + attribute \src "libresoc.v:92548.3-92596.6" + process $proc$libresoc.v:92548$3899 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_in1_sel[2:0] $1\dec31_dec_sub21_in1_sel[2:0] + attribute \src "libresoc.v:92549.5-92549.29" + switch \initial + attribute \src "libresoc.v:92549.9-92549.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + case + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub21_in1_sel $0\dec31_dec_sub21_in1_sel[2:0] + end + attribute \src "libresoc.v:92597.3-92645.6" + process $proc$libresoc.v:92597$3900 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_in2_sel[3:0] $1\dec31_dec_sub21_in2_sel[3:0] + attribute \src "libresoc.v:92598.5-92598.29" + switch \initial + attribute \src "libresoc.v:92598.9-92598.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + case + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub21_in2_sel $0\dec31_dec_sub21_in2_sel[3:0] + end + attribute \src "libresoc.v:92646.3-92694.6" + process $proc$libresoc.v:92646$3901 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_in3_sel[1:0] $1\dec31_dec_sub21_in3_sel[1:0] + attribute \src "libresoc.v:92647.5-92647.29" + switch \initial + attribute \src "libresoc.v:92647.9-92647.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'01 + case + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub21_in3_sel $0\dec31_dec_sub21_in3_sel[1:0] + end + attribute \src "libresoc.v:92695.3-92743.6" + process $proc$libresoc.v:92695$3902 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_out_sel[1:0] $1\dec31_dec_sub21_out_sel[1:0] + attribute \src "libresoc.v:92696.5-92696.29" + switch \initial + attribute \src "libresoc.v:92696.9-92696.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_out_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub21_out_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub21_out_sel $0\dec31_dec_sub21_out_sel[1:0] + end + attribute \src "libresoc.v:92744.3-92792.6" + process $proc$libresoc.v:92744$3903 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_cr_in[2:0] $1\dec31_dec_sub21_cr_in[2:0] + attribute \src "libresoc.v:92745.5-92745.29" + switch \initial + attribute \src "libresoc.v:92745.9-92745.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub21_cr_in $0\dec31_dec_sub21_cr_in[2:0] + end + attribute \src "libresoc.v:92793.3-92841.6" + process $proc$libresoc.v:92793$3904 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_cr_out[2:0] $1\dec31_dec_sub21_cr_out[2:0] + attribute \src "libresoc.v:92794.5-92794.29" + switch \initial + attribute \src "libresoc.v:92794.9-92794.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + case + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub21_cr_out $0\dec31_dec_sub21_cr_out[2:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:92847.1-94426.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec31_dec_sub22" +attribute \generator "nMigen" +module \dec31_dec_sub22 + attribute \src "libresoc.v:93380.3-93434.6" + wire width 8 $0\dec31_dec_sub22_asmcode[7:0] + attribute \src "libresoc.v:93600.3-93654.6" + wire $0\dec31_dec_sub22_br[0:0] + attribute \src "libresoc.v:94315.3-94369.6" + wire width 3 $0\dec31_dec_sub22_cr_in[2:0] + attribute \src "libresoc.v:94370.3-94424.6" + wire width 3 $0\dec31_dec_sub22_cr_out[2:0] + attribute \src "libresoc.v:93325.3-93379.6" + wire width 2 $0\dec31_dec_sub22_cry_in[1:0] + attribute \src "libresoc.v:93545.3-93599.6" + wire $0\dec31_dec_sub22_cry_out[0:0] + attribute \src "libresoc.v:94040.3-94094.6" + wire width 5 $0\dec31_dec_sub22_form[4:0] + attribute \src "libresoc.v:93105.3-93159.6" + wire width 12 $0\dec31_dec_sub22_function_unit[11:0] + attribute \src "libresoc.v:94095.3-94149.6" + wire width 3 $0\dec31_dec_sub22_in1_sel[2:0] + attribute \src "libresoc.v:94150.3-94204.6" + wire width 4 $0\dec31_dec_sub22_in2_sel[3:0] + attribute \src "libresoc.v:94205.3-94259.6" + wire width 2 $0\dec31_dec_sub22_in3_sel[1:0] + attribute \src "libresoc.v:93710.3-93764.6" + wire width 7 $0\dec31_dec_sub22_internal_op[6:0] + attribute \src "libresoc.v:93435.3-93489.6" + wire $0\dec31_dec_sub22_inv_a[0:0] + attribute \src "libresoc.v:93490.3-93544.6" + wire $0\dec31_dec_sub22_inv_out[0:0] + attribute \src "libresoc.v:93820.3-93874.6" + wire $0\dec31_dec_sub22_is_32b[0:0] + attribute \src "libresoc.v:93160.3-93214.6" + wire width 4 $0\dec31_dec_sub22_ldst_len[3:0] + attribute \src "libresoc.v:93930.3-93984.6" + wire $0\dec31_dec_sub22_lk[0:0] + attribute \src "libresoc.v:94260.3-94314.6" + wire width 2 $0\dec31_dec_sub22_out_sel[1:0] + attribute \src "libresoc.v:93270.3-93324.6" + wire width 2 $0\dec31_dec_sub22_rc_sel[1:0] + attribute \src "libresoc.v:93765.3-93819.6" + wire $0\dec31_dec_sub22_rsrv[0:0] + attribute \src "libresoc.v:93985.3-94039.6" + wire $0\dec31_dec_sub22_sgl_pipe[0:0] + attribute \src "libresoc.v:93875.3-93929.6" + wire $0\dec31_dec_sub22_sgn[0:0] + attribute \src "libresoc.v:93655.3-93709.6" + wire $0\dec31_dec_sub22_sgn_ext[0:0] + attribute \src "libresoc.v:93215.3-93269.6" + wire width 2 $0\dec31_dec_sub22_upd[1:0] + attribute \src "libresoc.v:92848.7-92848.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:93380.3-93434.6" + wire width 8 $1\dec31_dec_sub22_asmcode[7:0] + attribute \src "libresoc.v:93600.3-93654.6" + wire $1\dec31_dec_sub22_br[0:0] + attribute \src "libresoc.v:94315.3-94369.6" + wire width 3 $1\dec31_dec_sub22_cr_in[2:0] + attribute \src "libresoc.v:94370.3-94424.6" + wire width 3 $1\dec31_dec_sub22_cr_out[2:0] + attribute \src "libresoc.v:93325.3-93379.6" + wire width 2 $1\dec31_dec_sub22_cry_in[1:0] + attribute \src "libresoc.v:93545.3-93599.6" + wire $1\dec31_dec_sub22_cry_out[0:0] + attribute \src "libresoc.v:94040.3-94094.6" + wire width 5 $1\dec31_dec_sub22_form[4:0] + attribute \src "libresoc.v:93105.3-93159.6" + wire width 12 $1\dec31_dec_sub22_function_unit[11:0] + attribute \src "libresoc.v:94095.3-94149.6" + wire width 3 $1\dec31_dec_sub22_in1_sel[2:0] + attribute \src "libresoc.v:94150.3-94204.6" + wire width 4 $1\dec31_dec_sub22_in2_sel[3:0] + attribute \src "libresoc.v:94205.3-94259.6" + wire width 2 $1\dec31_dec_sub22_in3_sel[1:0] + attribute \src "libresoc.v:93710.3-93764.6" + wire width 7 $1\dec31_dec_sub22_internal_op[6:0] + attribute \src "libresoc.v:93435.3-93489.6" + wire $1\dec31_dec_sub22_inv_a[0:0] + attribute \src "libresoc.v:93490.3-93544.6" + wire $1\dec31_dec_sub22_inv_out[0:0] + attribute \src "libresoc.v:93820.3-93874.6" + wire $1\dec31_dec_sub22_is_32b[0:0] + attribute \src "libresoc.v:93160.3-93214.6" + wire width 4 $1\dec31_dec_sub22_ldst_len[3:0] + attribute \src "libresoc.v:93930.3-93984.6" + wire $1\dec31_dec_sub22_lk[0:0] + attribute \src "libresoc.v:94260.3-94314.6" + wire width 2 $1\dec31_dec_sub22_out_sel[1:0] + attribute \src "libresoc.v:93270.3-93324.6" + wire width 2 $1\dec31_dec_sub22_rc_sel[1:0] + attribute \src "libresoc.v:93765.3-93819.6" + wire $1\dec31_dec_sub22_rsrv[0:0] + attribute \src "libresoc.v:93985.3-94039.6" + wire $1\dec31_dec_sub22_sgl_pipe[0:0] + attribute \src "libresoc.v:93875.3-93929.6" + wire $1\dec31_dec_sub22_sgn[0:0] + attribute \src "libresoc.v:93655.3-93709.6" + wire $1\dec31_dec_sub22_sgn_ext[0:0] + attribute \src "libresoc.v:93215.3-93269.6" + wire width 2 $1\dec31_dec_sub22_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 output 4 \dec31_dec_sub22_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 18 \dec31_dec_sub22_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 9 \dec31_dec_sub22_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 10 \dec31_dec_sub22_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 14 \dec31_dec_sub22_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 17 \dec31_dec_sub22_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 output 3 \dec31_dec_sub22_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \dec31_dec_sub22_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \dec31_dec_sub22_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 6 \dec31_dec_sub22_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 7 \dec31_dec_sub22_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \dec31_dec_sub22_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 15 \dec31_dec_sub22_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 16 \dec31_dec_sub22_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 21 \dec31_dec_sub22_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 11 \dec31_dec_sub22_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 23 \dec31_dec_sub22_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 8 \dec31_dec_sub22_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 13 \dec31_dec_sub22_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 20 \dec31_dec_sub22_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 24 \dec31_dec_sub22_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 22 \dec31_dec_sub22_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 19 \dec31_dec_sub22_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 12 \dec31_dec_sub22_upd + attribute \src "libresoc.v:92848.7-92848.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 5 \opcode_switch + attribute \src "libresoc.v:92848.7-92848.20" + process $proc$libresoc.v:92848$3930 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:93105.3-93159.6" + process $proc$libresoc.v:93105$3906 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_function_unit[11:0] $1\dec31_dec_sub22_function_unit[11:0] + attribute \src "libresoc.v:93106.5-93106.29" + switch \initial + attribute \src "libresoc.v:93106.9-93106.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[11:0] 12'100000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000010 + case + assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000000 + end + sync always + update \dec31_dec_sub22_function_unit $0\dec31_dec_sub22_function_unit[11:0] + end + attribute \src "libresoc.v:93160.3-93214.6" + process $proc$libresoc.v:93160$3907 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_ldst_len[3:0] $1\dec31_dec_sub22_ldst_len[3:0] + attribute \src "libresoc.v:93161.5-93161.29" + switch \initial + attribute \src "libresoc.v:93161.9-93161.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 + case + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub22_ldst_len $0\dec31_dec_sub22_ldst_len[3:0] + end + attribute \src "libresoc.v:93215.3-93269.6" + process $proc$libresoc.v:93215$3908 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_upd[1:0] $1\dec31_dec_sub22_upd[1:0] + attribute \src "libresoc.v:93216.5-93216.29" + switch \initial + attribute \src "libresoc.v:93216.9-93216.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub22_upd $0\dec31_dec_sub22_upd[1:0] + end + attribute \src "libresoc.v:93270.3-93324.6" + process $proc$libresoc.v:93270$3909 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_rc_sel[1:0] $1\dec31_dec_sub22_rc_sel[1:0] + attribute \src "libresoc.v:93271.5-93271.29" + switch \initial + attribute \src "libresoc.v:93271.9-93271.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub22_rc_sel $0\dec31_dec_sub22_rc_sel[1:0] + end + attribute \src "libresoc.v:93325.3-93379.6" + process $proc$libresoc.v:93325$3910 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_cry_in[1:0] $1\dec31_dec_sub22_cry_in[1:0] + attribute \src "libresoc.v:93326.5-93326.29" + switch \initial + attribute \src "libresoc.v:93326.9-93326.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + case + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub22_cry_in $0\dec31_dec_sub22_cry_in[1:0] + end + attribute \src "libresoc.v:93380.3-93434.6" + process $proc$libresoc.v:93380$3911 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_asmcode[7:0] $1\dec31_dec_sub22_asmcode[7:0] + attribute \src "libresoc.v:93381.5-93381.29" + switch \initial + attribute \src "libresoc.v:93381.9-93381.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'00101110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'00101111 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'00110000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'00110001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'00110010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'01001001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'01001010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'01011101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'01100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'10101000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'10101110 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'10110011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'10110100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'10111001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'10111010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'11001001 + case + assign $1\dec31_dec_sub22_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub22_asmcode $0\dec31_dec_sub22_asmcode[7:0] + end + attribute \src "libresoc.v:93435.3-93489.6" + process $proc$libresoc.v:93435$3912 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_inv_a[0:0] $1\dec31_dec_sub22_inv_a[0:0] + attribute \src "libresoc.v:93436.5-93436.29" + switch \initial + attribute \src "libresoc.v:93436.9-93436.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub22_inv_a $0\dec31_dec_sub22_inv_a[0:0] + end + attribute \src "libresoc.v:93490.3-93544.6" + process $proc$libresoc.v:93490$3913 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_inv_out[0:0] $1\dec31_dec_sub22_inv_out[0:0] + attribute \src "libresoc.v:93491.5-93491.29" + switch \initial + attribute \src "libresoc.v:93491.9-93491.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub22_inv_out $0\dec31_dec_sub22_inv_out[0:0] + end + attribute \src "libresoc.v:93545.3-93599.6" + process $proc$libresoc.v:93545$3914 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_cry_out[0:0] $1\dec31_dec_sub22_cry_out[0:0] + attribute \src "libresoc.v:93546.5-93546.29" + switch \initial + attribute \src "libresoc.v:93546.9-93546.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + case + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub22_cry_out $0\dec31_dec_sub22_cry_out[0:0] + end + attribute \src "libresoc.v:93600.3-93654.6" + process $proc$libresoc.v:93600$3915 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_br[0:0] $1\dec31_dec_sub22_br[0:0] + attribute \src "libresoc.v:93601.5-93601.29" + switch \initial + attribute \src "libresoc.v:93601.9-93601.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'0 + case + assign $1\dec31_dec_sub22_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub22_br $0\dec31_dec_sub22_br[0:0] + end + attribute \src "libresoc.v:93655.3-93709.6" + process $proc$libresoc.v:93655$3916 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_sgn_ext[0:0] $1\dec31_dec_sub22_sgn_ext[0:0] + attribute \src "libresoc.v:93656.5-93656.29" + switch \initial + attribute \src "libresoc.v:93656.9-93656.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub22_sgn_ext $0\dec31_dec_sub22_sgn_ext[0:0] + end + attribute \src "libresoc.v:93710.3-93764.6" + process $proc$libresoc.v:93710$3917 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_internal_op[6:0] $1\dec31_dec_sub22_internal_op[6:0] + attribute \src "libresoc.v:93711.5-93711.29" + switch \initial + attribute \src "libresoc.v:93711.9-93711.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0011100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000001 + case + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub22_internal_op $0\dec31_dec_sub22_internal_op[6:0] + end + attribute \src "libresoc.v:93765.3-93819.6" + process $proc$libresoc.v:93765$3918 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_rsrv[0:0] $1\dec31_dec_sub22_rsrv[0:0] + attribute \src "libresoc.v:93766.5-93766.29" + switch \initial + attribute \src "libresoc.v:93766.9-93766.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_rsrv[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_rsrv[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_rsrv[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_rsrv[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub22_rsrv $0\dec31_dec_sub22_rsrv[0:0] + end + attribute \src "libresoc.v:93820.3-93874.6" + process $proc$libresoc.v:93820$3919 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_is_32b[0:0] $1\dec31_dec_sub22_is_32b[0:0] + attribute \src "libresoc.v:93821.5-93821.29" + switch \initial + attribute \src "libresoc.v:93821.9-93821.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + case + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub22_is_32b $0\dec31_dec_sub22_is_32b[0:0] + end + attribute \src "libresoc.v:93875.3-93929.6" + process $proc$libresoc.v:93875$3920 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_sgn[0:0] $1\dec31_dec_sub22_sgn[0:0] + attribute \src "libresoc.v:93876.5-93876.29" + switch \initial + attribute \src "libresoc.v:93876.9-93876.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + case + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub22_sgn $0\dec31_dec_sub22_sgn[0:0] + end + attribute \src "libresoc.v:93930.3-93984.6" + process $proc$libresoc.v:93930$3921 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_lk[0:0] $1\dec31_dec_sub22_lk[0:0] + attribute \src "libresoc.v:93931.5-93931.29" + switch \initial + attribute \src "libresoc.v:93931.9-93931.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub22_lk $0\dec31_dec_sub22_lk[0:0] + end + attribute \src "libresoc.v:93985.3-94039.6" + process $proc$libresoc.v:93985$3922 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_sgl_pipe[0:0] $1\dec31_dec_sub22_sgl_pipe[0:0] + attribute \src "libresoc.v:93986.5-93986.29" + switch \initial + attribute \src "libresoc.v:93986.9-93986.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 + case + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub22_sgl_pipe $0\dec31_dec_sub22_sgl_pipe[0:0] + end + attribute \src "libresoc.v:94040.3-94094.6" + process $proc$libresoc.v:94040$3923 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_form[4:0] $1\dec31_dec_sub22_form[4:0] + attribute \src "libresoc.v:94041.5-94041.29" + switch \initial + attribute \src "libresoc.v:94041.9-94041.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_form[4:0] 5'01000 + case + assign $1\dec31_dec_sub22_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub22_form $0\dec31_dec_sub22_form[4:0] + end + attribute \src "libresoc.v:94095.3-94149.6" + process $proc$libresoc.v:94095$3924 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_in1_sel[2:0] $1\dec31_dec_sub22_in1_sel[2:0] + attribute \src "libresoc.v:94096.5-94096.29" + switch \initial + attribute \src "libresoc.v:94096.9-94096.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'000 + case + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub22_in1_sel $0\dec31_dec_sub22_in1_sel[2:0] + end + attribute \src "libresoc.v:94150.3-94204.6" + process $proc$libresoc.v:94150$3925 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_in2_sel[3:0] $1\dec31_dec_sub22_in2_sel[3:0] + attribute \src "libresoc.v:94151.5-94151.29" + switch \initial + attribute \src "libresoc.v:94151.9-94151.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0000 + case + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub22_in2_sel $0\dec31_dec_sub22_in2_sel[3:0] + end + attribute \src "libresoc.v:94205.3-94259.6" + process $proc$libresoc.v:94205$3926 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_in3_sel[1:0] $1\dec31_dec_sub22_in3_sel[1:0] + attribute \src "libresoc.v:94206.5-94206.29" + switch \initial + attribute \src "libresoc.v:94206.9-94206.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub22_in3_sel $0\dec31_dec_sub22_in3_sel[1:0] + end + attribute \src "libresoc.v:94260.3-94314.6" + process $proc$libresoc.v:94260$3927 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_out_sel[1:0] $1\dec31_dec_sub22_out_sel[1:0] + attribute \src "libresoc.v:94261.5-94261.29" + switch \initial + attribute \src "libresoc.v:94261.9-94261.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub22_out_sel $0\dec31_dec_sub22_out_sel[1:0] + end + attribute \src "libresoc.v:94315.3-94369.6" + process $proc$libresoc.v:94315$3928 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_cr_in[2:0] $1\dec31_dec_sub22_cr_in[2:0] + attribute \src "libresoc.v:94316.5-94316.29" + switch \initial + attribute \src "libresoc.v:94316.9-94316.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub22_cr_in $0\dec31_dec_sub22_cr_in[2:0] + end + attribute \src "libresoc.v:94370.3-94424.6" + process $proc$libresoc.v:94370$3929 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_cr_out[2:0] $1\dec31_dec_sub22_cr_out[2:0] + attribute \src "libresoc.v:94371.5-94371.29" + switch \initial + attribute \src "libresoc.v:94371.9-94371.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 + case + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub22_cr_out $0\dec31_dec_sub22_cr_out[2:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:94430.1-95865.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec31_dec_sub23" +attribute \generator "nMigen" +module \dec31_dec_sub23 + attribute \src "libresoc.v:94933.3-94981.6" + wire width 8 $0\dec31_dec_sub23_asmcode[7:0] + attribute \src "libresoc.v:95129.3-95177.6" + wire $0\dec31_dec_sub23_br[0:0] + attribute \src "libresoc.v:95766.3-95814.6" + wire width 3 $0\dec31_dec_sub23_cr_in[2:0] + attribute \src "libresoc.v:95815.3-95863.6" + wire width 3 $0\dec31_dec_sub23_cr_out[2:0] + attribute \src "libresoc.v:94884.3-94932.6" + wire width 2 $0\dec31_dec_sub23_cry_in[1:0] + attribute \src "libresoc.v:95080.3-95128.6" + wire $0\dec31_dec_sub23_cry_out[0:0] + attribute \src "libresoc.v:95521.3-95569.6" + wire width 5 $0\dec31_dec_sub23_form[4:0] + attribute \src "libresoc.v:94688.3-94736.6" + wire width 12 $0\dec31_dec_sub23_function_unit[11:0] + attribute \src "libresoc.v:95570.3-95618.6" + wire width 3 $0\dec31_dec_sub23_in1_sel[2:0] + attribute \src "libresoc.v:95619.3-95667.6" + wire width 4 $0\dec31_dec_sub23_in2_sel[3:0] + attribute \src "libresoc.v:95668.3-95716.6" + wire width 2 $0\dec31_dec_sub23_in3_sel[1:0] + attribute \src "libresoc.v:95227.3-95275.6" + wire width 7 $0\dec31_dec_sub23_internal_op[6:0] + attribute \src "libresoc.v:94982.3-95030.6" + wire $0\dec31_dec_sub23_inv_a[0:0] + attribute \src "libresoc.v:95031.3-95079.6" + wire $0\dec31_dec_sub23_inv_out[0:0] + attribute \src "libresoc.v:95325.3-95373.6" + wire $0\dec31_dec_sub23_is_32b[0:0] + attribute \src "libresoc.v:94737.3-94785.6" + wire width 4 $0\dec31_dec_sub23_ldst_len[3:0] + attribute \src "libresoc.v:95423.3-95471.6" + wire $0\dec31_dec_sub23_lk[0:0] + attribute \src "libresoc.v:95717.3-95765.6" + wire width 2 $0\dec31_dec_sub23_out_sel[1:0] + attribute \src "libresoc.v:94835.3-94883.6" + wire width 2 $0\dec31_dec_sub23_rc_sel[1:0] + attribute \src "libresoc.v:95276.3-95324.6" + wire $0\dec31_dec_sub23_rsrv[0:0] + attribute \src "libresoc.v:95472.3-95520.6" + wire $0\dec31_dec_sub23_sgl_pipe[0:0] + attribute \src "libresoc.v:95374.3-95422.6" + wire $0\dec31_dec_sub23_sgn[0:0] + attribute \src "libresoc.v:95178.3-95226.6" + wire $0\dec31_dec_sub23_sgn_ext[0:0] + attribute \src "libresoc.v:94786.3-94834.6" + wire width 2 $0\dec31_dec_sub23_upd[1:0] + attribute \src "libresoc.v:94431.7-94431.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:94933.3-94981.6" + wire width 8 $1\dec31_dec_sub23_asmcode[7:0] + attribute \src "libresoc.v:95129.3-95177.6" + wire $1\dec31_dec_sub23_br[0:0] + attribute \src "libresoc.v:95766.3-95814.6" + wire width 3 $1\dec31_dec_sub23_cr_in[2:0] + attribute \src "libresoc.v:95815.3-95863.6" + wire width 3 $1\dec31_dec_sub23_cr_out[2:0] + attribute \src "libresoc.v:94884.3-94932.6" + wire width 2 $1\dec31_dec_sub23_cry_in[1:0] + attribute \src "libresoc.v:95080.3-95128.6" + wire $1\dec31_dec_sub23_cry_out[0:0] + attribute \src "libresoc.v:95521.3-95569.6" + wire width 5 $1\dec31_dec_sub23_form[4:0] + attribute \src "libresoc.v:94688.3-94736.6" + wire width 12 $1\dec31_dec_sub23_function_unit[11:0] + attribute \src "libresoc.v:95570.3-95618.6" + wire width 3 $1\dec31_dec_sub23_in1_sel[2:0] + attribute \src "libresoc.v:95619.3-95667.6" + wire width 4 $1\dec31_dec_sub23_in2_sel[3:0] + attribute \src "libresoc.v:95668.3-95716.6" + wire width 2 $1\dec31_dec_sub23_in3_sel[1:0] + attribute \src "libresoc.v:95227.3-95275.6" + wire width 7 $1\dec31_dec_sub23_internal_op[6:0] + attribute \src "libresoc.v:94982.3-95030.6" + wire $1\dec31_dec_sub23_inv_a[0:0] + attribute \src "libresoc.v:95031.3-95079.6" + wire $1\dec31_dec_sub23_inv_out[0:0] + attribute \src "libresoc.v:95325.3-95373.6" + wire $1\dec31_dec_sub23_is_32b[0:0] + attribute \src "libresoc.v:94737.3-94785.6" + wire width 4 $1\dec31_dec_sub23_ldst_len[3:0] + attribute \src "libresoc.v:95423.3-95471.6" + wire $1\dec31_dec_sub23_lk[0:0] + attribute \src "libresoc.v:95717.3-95765.6" + wire width 2 $1\dec31_dec_sub23_out_sel[1:0] + attribute \src "libresoc.v:94835.3-94883.6" + wire width 2 $1\dec31_dec_sub23_rc_sel[1:0] + attribute \src "libresoc.v:95276.3-95324.6" + wire $1\dec31_dec_sub23_rsrv[0:0] + attribute \src "libresoc.v:95472.3-95520.6" + wire $1\dec31_dec_sub23_sgl_pipe[0:0] + attribute \src "libresoc.v:95374.3-95422.6" + wire $1\dec31_dec_sub23_sgn[0:0] + attribute \src "libresoc.v:95178.3-95226.6" + wire $1\dec31_dec_sub23_sgn_ext[0:0] + attribute \src "libresoc.v:94786.3-94834.6" + wire width 2 $1\dec31_dec_sub23_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 output 4 \dec31_dec_sub23_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 18 \dec31_dec_sub23_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 9 \dec31_dec_sub23_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 10 \dec31_dec_sub23_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 14 \dec31_dec_sub23_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 17 \dec31_dec_sub23_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 output 3 \dec31_dec_sub23_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \dec31_dec_sub23_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \dec31_dec_sub23_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 6 \dec31_dec_sub23_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 7 \dec31_dec_sub23_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \dec31_dec_sub23_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 15 \dec31_dec_sub23_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 16 \dec31_dec_sub23_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 21 \dec31_dec_sub23_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 11 \dec31_dec_sub23_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 23 \dec31_dec_sub23_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 8 \dec31_dec_sub23_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 13 \dec31_dec_sub23_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 20 \dec31_dec_sub23_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 24 \dec31_dec_sub23_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 22 \dec31_dec_sub23_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 19 \dec31_dec_sub23_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 12 \dec31_dec_sub23_upd + attribute \src "libresoc.v:94431.7-94431.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 5 \opcode_switch + attribute \src "libresoc.v:94431.7-94431.20" + process $proc$libresoc.v:94431$3955 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:94688.3-94736.6" + process $proc$libresoc.v:94688$3931 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_function_unit[11:0] $1\dec31_dec_sub23_function_unit[11:0] + attribute \src "libresoc.v:94689.5-94689.29" + switch \initial + attribute \src "libresoc.v:94689.9-94689.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 + case + assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000000 + end + sync always + update \dec31_dec_sub23_function_unit $0\dec31_dec_sub23_function_unit[11:0] + end + attribute \src "libresoc.v:94737.3-94785.6" + process $proc$libresoc.v:94737$3932 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_ldst_len[3:0] $1\dec31_dec_sub23_ldst_len[3:0] + attribute \src "libresoc.v:94738.5-94738.29" + switch \initial + attribute \src "libresoc.v:94738.9-94738.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0100 + case + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub23_ldst_len $0\dec31_dec_sub23_ldst_len[3:0] + end + attribute \src "libresoc.v:94786.3-94834.6" + process $proc$libresoc.v:94786$3933 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_upd[1:0] $1\dec31_dec_sub23_upd[1:0] + attribute \src "libresoc.v:94787.5-94787.29" + switch \initial + attribute \src "libresoc.v:94787.9-94787.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub23_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub23_upd $0\dec31_dec_sub23_upd[1:0] + end + attribute \src "libresoc.v:94835.3-94883.6" + process $proc$libresoc.v:94835$3934 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_rc_sel[1:0] $1\dec31_dec_sub23_rc_sel[1:0] + attribute \src "libresoc.v:94836.5-94836.29" + switch \initial + attribute \src "libresoc.v:94836.9-94836.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub23_rc_sel $0\dec31_dec_sub23_rc_sel[1:0] + end + attribute \src "libresoc.v:94884.3-94932.6" + process $proc$libresoc.v:94884$3935 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_cry_in[1:0] $1\dec31_dec_sub23_cry_in[1:0] + attribute \src "libresoc.v:94885.5-94885.29" + switch \initial + attribute \src "libresoc.v:94885.9-94885.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 + case + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub23_cry_in $0\dec31_dec_sub23_cry_in[1:0] + end + attribute \src "libresoc.v:94933.3-94981.6" + process $proc$libresoc.v:94933$3936 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_asmcode[7:0] $1\dec31_dec_sub23_asmcode[7:0] + attribute \src "libresoc.v:94934.5-94934.29" + switch \initial + attribute \src "libresoc.v:94934.9-94934.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_asmcode[7:0] 8'01010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_asmcode[7:0] 8'01010001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_asmcode[7:0] 8'01011011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_asmcode[7:0] 8'01011100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_asmcode[7:0] 8'01100000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_asmcode[7:0] 8'01100001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_asmcode[7:0] 8'01101010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_asmcode[7:0] 8'01101011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_asmcode[7:0] 8'10101010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_asmcode[7:0] 8'10101011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_asmcode[7:0] 8'10110110 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_asmcode[7:0] 8'10110111 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_asmcode[7:0] 8'10111100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_asmcode[7:0] 8'10111101 + case + assign $1\dec31_dec_sub23_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub23_asmcode $0\dec31_dec_sub23_asmcode[7:0] + end + attribute \src "libresoc.v:94982.3-95030.6" + process $proc$libresoc.v:94982$3937 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_inv_a[0:0] $1\dec31_dec_sub23_inv_a[0:0] + attribute \src "libresoc.v:94983.5-94983.29" + switch \initial + attribute \src "libresoc.v:94983.9-94983.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub23_inv_a $0\dec31_dec_sub23_inv_a[0:0] + end + attribute \src "libresoc.v:95031.3-95079.6" + process $proc$libresoc.v:95031$3938 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_inv_out[0:0] $1\dec31_dec_sub23_inv_out[0:0] + attribute \src "libresoc.v:95032.5-95032.29" + switch \initial + attribute \src "libresoc.v:95032.9-95032.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub23_inv_out $0\dec31_dec_sub23_inv_out[0:0] + end + attribute \src "libresoc.v:95080.3-95128.6" + process $proc$libresoc.v:95080$3939 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_cry_out[0:0] $1\dec31_dec_sub23_cry_out[0:0] + attribute \src "libresoc.v:95081.5-95081.29" + switch \initial + attribute \src "libresoc.v:95081.9-95081.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 + case + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub23_cry_out $0\dec31_dec_sub23_cry_out[0:0] + end + attribute \src "libresoc.v:95129.3-95177.6" + process $proc$libresoc.v:95129$3940 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_br[0:0] $1\dec31_dec_sub23_br[0:0] + attribute \src "libresoc.v:95130.5-95130.29" + switch \initial + attribute \src "libresoc.v:95130.9-95130.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_br[0:0] 1'0 + case + assign $1\dec31_dec_sub23_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub23_br $0\dec31_dec_sub23_br[0:0] + end + attribute \src "libresoc.v:95178.3-95226.6" + process $proc$libresoc.v:95178$3941 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_sgn_ext[0:0] $1\dec31_dec_sub23_sgn_ext[0:0] + attribute \src "libresoc.v:95179.5-95179.29" + switch \initial + attribute \src "libresoc.v:95179.9-95179.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub23_sgn_ext $0\dec31_dec_sub23_sgn_ext[0:0] + end + attribute \src "libresoc.v:95227.3-95275.6" + process $proc$libresoc.v:95227$3942 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_internal_op[6:0] $1\dec31_dec_sub23_internal_op[6:0] + attribute \src "libresoc.v:95228.5-95228.29" + switch \initial + attribute \src "libresoc.v:95228.9-95228.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100110 + case + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub23_internal_op $0\dec31_dec_sub23_internal_op[6:0] + end + attribute \src "libresoc.v:95276.3-95324.6" + process $proc$libresoc.v:95276$3943 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_rsrv[0:0] $1\dec31_dec_sub23_rsrv[0:0] + attribute \src "libresoc.v:95277.5-95277.29" + switch \initial + attribute \src "libresoc.v:95277.9-95277.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub23_rsrv $0\dec31_dec_sub23_rsrv[0:0] + end + attribute \src "libresoc.v:95325.3-95373.6" + process $proc$libresoc.v:95325$3944 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_is_32b[0:0] $1\dec31_dec_sub23_is_32b[0:0] + attribute \src "libresoc.v:95326.5-95326.29" + switch \initial + attribute \src "libresoc.v:95326.9-95326.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + case + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub23_is_32b $0\dec31_dec_sub23_is_32b[0:0] + end + attribute \src "libresoc.v:95374.3-95422.6" + process $proc$libresoc.v:95374$3945 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_sgn[0:0] $1\dec31_dec_sub23_sgn[0:0] + attribute \src "libresoc.v:95375.5-95375.29" + switch \initial + attribute \src "libresoc.v:95375.9-95375.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + case + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub23_sgn $0\dec31_dec_sub23_sgn[0:0] + end + attribute \src "libresoc.v:95423.3-95471.6" + process $proc$libresoc.v:95423$3946 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_lk[0:0] $1\dec31_dec_sub23_lk[0:0] + attribute \src "libresoc.v:95424.5-95424.29" + switch \initial + attribute \src "libresoc.v:95424.9-95424.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub23_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub23_lk $0\dec31_dec_sub23_lk[0:0] + end + attribute \src "libresoc.v:95472.3-95520.6" + process $proc$libresoc.v:95472$3947 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_sgl_pipe[0:0] $1\dec31_dec_sub23_sgl_pipe[0:0] + attribute \src "libresoc.v:95473.5-95473.29" + switch \initial + attribute \src "libresoc.v:95473.9-95473.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 + case + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub23_sgl_pipe $0\dec31_dec_sub23_sgl_pipe[0:0] + end + attribute \src "libresoc.v:95521.3-95569.6" + process $proc$libresoc.v:95521$3948 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_form[4:0] $1\dec31_dec_sub23_form[4:0] + attribute \src "libresoc.v:95522.5-95522.29" + switch \initial + attribute \src "libresoc.v:95522.9-95522.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_form[4:0] 5'01000 + case + assign $1\dec31_dec_sub23_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub23_form $0\dec31_dec_sub23_form[4:0] + end + attribute \src "libresoc.v:95570.3-95618.6" + process $proc$libresoc.v:95570$3949 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_in1_sel[2:0] $1\dec31_dec_sub23_in1_sel[2:0] + attribute \src "libresoc.v:95571.5-95571.29" + switch \initial + attribute \src "libresoc.v:95571.9-95571.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 + case + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub23_in1_sel $0\dec31_dec_sub23_in1_sel[2:0] + end + attribute \src "libresoc.v:95619.3-95667.6" + process $proc$libresoc.v:95619$3950 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_in2_sel[3:0] $1\dec31_dec_sub23_in2_sel[3:0] + attribute \src "libresoc.v:95620.5-95620.29" + switch \initial + attribute \src "libresoc.v:95620.9-95620.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 + case + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub23_in2_sel $0\dec31_dec_sub23_in2_sel[3:0] + end + attribute \src "libresoc.v:95668.3-95716.6" + process $proc$libresoc.v:95668$3951 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_in3_sel[1:0] $1\dec31_dec_sub23_in3_sel[1:0] + attribute \src "libresoc.v:95669.5-95669.29" + switch \initial + attribute \src "libresoc.v:95669.9-95669.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'01 + case + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub23_in3_sel $0\dec31_dec_sub23_in3_sel[1:0] + end + attribute \src "libresoc.v:95717.3-95765.6" + process $proc$libresoc.v:95717$3952 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_out_sel[1:0] $1\dec31_dec_sub23_out_sel[1:0] + attribute \src "libresoc.v:95718.5-95718.29" + switch \initial + attribute \src "libresoc.v:95718.9-95718.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_out_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub23_out_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub23_out_sel $0\dec31_dec_sub23_out_sel[1:0] + end + attribute \src "libresoc.v:95766.3-95814.6" + process $proc$libresoc.v:95766$3953 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_cr_in[2:0] $1\dec31_dec_sub23_cr_in[2:0] + attribute \src "libresoc.v:95767.5-95767.29" + switch \initial + attribute \src "libresoc.v:95767.9-95767.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub23_cr_in $0\dec31_dec_sub23_cr_in[2:0] + end + attribute \src "libresoc.v:95815.3-95863.6" + process $proc$libresoc.v:95815$3954 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_cr_out[2:0] $1\dec31_dec_sub23_cr_out[2:0] + attribute \src "libresoc.v:95816.5-95816.29" + switch \initial + attribute \src "libresoc.v:95816.9-95816.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 + case + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub23_cr_out $0\dec31_dec_sub23_cr_out[2:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:95869.1-96584.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec31_dec_sub24" +attribute \generator "nMigen" +module \dec31_dec_sub24 + attribute \src "libresoc.v:96222.3-96240.6" + wire width 8 $0\dec31_dec_sub24_asmcode[7:0] + attribute \src "libresoc.v:96298.3-96316.6" + wire $0\dec31_dec_sub24_br[0:0] + attribute \src "libresoc.v:96545.3-96563.6" + wire width 3 $0\dec31_dec_sub24_cr_in[2:0] + attribute \src "libresoc.v:96564.3-96582.6" + wire width 3 $0\dec31_dec_sub24_cr_out[2:0] + attribute \src "libresoc.v:96203.3-96221.6" + wire width 2 $0\dec31_dec_sub24_cry_in[1:0] + attribute \src "libresoc.v:96279.3-96297.6" + wire $0\dec31_dec_sub24_cry_out[0:0] + attribute \src "libresoc.v:96450.3-96468.6" + wire width 5 $0\dec31_dec_sub24_form[4:0] + attribute \src "libresoc.v:96127.3-96145.6" + wire width 12 $0\dec31_dec_sub24_function_unit[11:0] + attribute \src "libresoc.v:96469.3-96487.6" + wire width 3 $0\dec31_dec_sub24_in1_sel[2:0] + attribute \src "libresoc.v:96488.3-96506.6" + wire width 4 $0\dec31_dec_sub24_in2_sel[3:0] + attribute \src "libresoc.v:96507.3-96525.6" + wire width 2 $0\dec31_dec_sub24_in3_sel[1:0] + attribute \src "libresoc.v:96336.3-96354.6" + wire width 7 $0\dec31_dec_sub24_internal_op[6:0] + attribute \src "libresoc.v:96241.3-96259.6" + wire $0\dec31_dec_sub24_inv_a[0:0] + attribute \src "libresoc.v:96260.3-96278.6" + wire $0\dec31_dec_sub24_inv_out[0:0] + attribute \src "libresoc.v:96374.3-96392.6" + wire $0\dec31_dec_sub24_is_32b[0:0] + attribute \src "libresoc.v:96146.3-96164.6" + wire width 4 $0\dec31_dec_sub24_ldst_len[3:0] + attribute \src "libresoc.v:96412.3-96430.6" + wire $0\dec31_dec_sub24_lk[0:0] + attribute \src "libresoc.v:96526.3-96544.6" + wire width 2 $0\dec31_dec_sub24_out_sel[1:0] + attribute \src "libresoc.v:96184.3-96202.6" + wire width 2 $0\dec31_dec_sub24_rc_sel[1:0] + attribute \src "libresoc.v:96355.3-96373.6" + wire $0\dec31_dec_sub24_rsrv[0:0] + attribute \src "libresoc.v:96431.3-96449.6" + wire $0\dec31_dec_sub24_sgl_pipe[0:0] + attribute \src "libresoc.v:96393.3-96411.6" + wire $0\dec31_dec_sub24_sgn[0:0] + attribute \src "libresoc.v:96317.3-96335.6" + wire $0\dec31_dec_sub24_sgn_ext[0:0] + attribute \src "libresoc.v:96165.3-96183.6" + wire width 2 $0\dec31_dec_sub24_upd[1:0] + attribute \src "libresoc.v:95870.7-95870.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:96222.3-96240.6" + wire width 8 $1\dec31_dec_sub24_asmcode[7:0] + attribute \src "libresoc.v:96298.3-96316.6" + wire $1\dec31_dec_sub24_br[0:0] + attribute \src "libresoc.v:96545.3-96563.6" + wire width 3 $1\dec31_dec_sub24_cr_in[2:0] + attribute \src "libresoc.v:96564.3-96582.6" + wire width 3 $1\dec31_dec_sub24_cr_out[2:0] + attribute \src "libresoc.v:96203.3-96221.6" + wire width 2 $1\dec31_dec_sub24_cry_in[1:0] + attribute \src "libresoc.v:96279.3-96297.6" + wire $1\dec31_dec_sub24_cry_out[0:0] + attribute \src "libresoc.v:96450.3-96468.6" + wire width 5 $1\dec31_dec_sub24_form[4:0] + attribute \src "libresoc.v:96127.3-96145.6" + wire width 12 $1\dec31_dec_sub24_function_unit[11:0] + attribute \src "libresoc.v:96469.3-96487.6" + wire width 3 $1\dec31_dec_sub24_in1_sel[2:0] + attribute \src "libresoc.v:96488.3-96506.6" + wire width 4 $1\dec31_dec_sub24_in2_sel[3:0] + attribute \src "libresoc.v:96507.3-96525.6" + wire width 2 $1\dec31_dec_sub24_in3_sel[1:0] + attribute \src "libresoc.v:96336.3-96354.6" + wire width 7 $1\dec31_dec_sub24_internal_op[6:0] + attribute \src "libresoc.v:96241.3-96259.6" + wire $1\dec31_dec_sub24_inv_a[0:0] + attribute \src "libresoc.v:96260.3-96278.6" + wire $1\dec31_dec_sub24_inv_out[0:0] + attribute \src "libresoc.v:96374.3-96392.6" + wire $1\dec31_dec_sub24_is_32b[0:0] + attribute \src "libresoc.v:96146.3-96164.6" + wire width 4 $1\dec31_dec_sub24_ldst_len[3:0] + attribute \src "libresoc.v:96412.3-96430.6" + wire $1\dec31_dec_sub24_lk[0:0] + attribute \src "libresoc.v:96526.3-96544.6" + wire width 2 $1\dec31_dec_sub24_out_sel[1:0] + attribute \src "libresoc.v:96184.3-96202.6" + wire width 2 $1\dec31_dec_sub24_rc_sel[1:0] + attribute \src "libresoc.v:96355.3-96373.6" + wire $1\dec31_dec_sub24_rsrv[0:0] + attribute \src "libresoc.v:96431.3-96449.6" + wire $1\dec31_dec_sub24_sgl_pipe[0:0] + attribute \src "libresoc.v:96393.3-96411.6" + wire $1\dec31_dec_sub24_sgn[0:0] + attribute \src "libresoc.v:96317.3-96335.6" + wire $1\dec31_dec_sub24_sgn_ext[0:0] + attribute \src "libresoc.v:96165.3-96183.6" + wire width 2 $1\dec31_dec_sub24_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 output 4 \dec31_dec_sub24_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 18 \dec31_dec_sub24_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 9 \dec31_dec_sub24_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 10 \dec31_dec_sub24_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 14 \dec31_dec_sub24_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 17 \dec31_dec_sub24_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 output 3 \dec31_dec_sub24_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \dec31_dec_sub24_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \dec31_dec_sub24_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 6 \dec31_dec_sub24_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 7 \dec31_dec_sub24_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \dec31_dec_sub24_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 15 \dec31_dec_sub24_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 16 \dec31_dec_sub24_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 21 \dec31_dec_sub24_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 11 \dec31_dec_sub24_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 23 \dec31_dec_sub24_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 8 \dec31_dec_sub24_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 13 \dec31_dec_sub24_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 20 \dec31_dec_sub24_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 24 \dec31_dec_sub24_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 22 \dec31_dec_sub24_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 19 \dec31_dec_sub24_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 12 \dec31_dec_sub24_upd + attribute \src "libresoc.v:95870.7-95870.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 5 \opcode_switch + attribute \src "libresoc.v:95870.7-95870.20" + process $proc$libresoc.v:95870$3980 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:96127.3-96145.6" + process $proc$libresoc.v:96127$3956 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_function_unit[11:0] $1\dec31_dec_sub24_function_unit[11:0] + attribute \src "libresoc.v:96128.5-96128.29" + switch \initial + attribute \src "libresoc.v:96128.9-96128.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_function_unit[11:0] 12'000000001000 + case + assign $1\dec31_dec_sub24_function_unit[11:0] 12'000000000000 + end + sync always + update \dec31_dec_sub24_function_unit $0\dec31_dec_sub24_function_unit[11:0] + end + attribute \src "libresoc.v:96146.3-96164.6" + process $proc$libresoc.v:96146$3957 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_ldst_len[3:0] $1\dec31_dec_sub24_ldst_len[3:0] + attribute \src "libresoc.v:96147.5-96147.29" + switch \initial + attribute \src "libresoc.v:96147.9-96147.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_ldst_len[3:0] 4'0000 + case + assign $1\dec31_dec_sub24_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub24_ldst_len $0\dec31_dec_sub24_ldst_len[3:0] + end + attribute \src "libresoc.v:96165.3-96183.6" + process $proc$libresoc.v:96165$3958 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_upd[1:0] $1\dec31_dec_sub24_upd[1:0] + attribute \src "libresoc.v:96166.5-96166.29" + switch \initial + attribute \src "libresoc.v:96166.9-96166.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub24_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub24_upd $0\dec31_dec_sub24_upd[1:0] + end + attribute \src "libresoc.v:96184.3-96202.6" + process $proc$libresoc.v:96184$3959 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_rc_sel[1:0] $1\dec31_dec_sub24_rc_sel[1:0] + attribute \src "libresoc.v:96185.5-96185.29" + switch \initial + attribute \src "libresoc.v:96185.9-96185.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_rc_sel[1:0] 2'10 + case + assign $1\dec31_dec_sub24_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub24_rc_sel $0\dec31_dec_sub24_rc_sel[1:0] + end + attribute \src "libresoc.v:96203.3-96221.6" + process $proc$libresoc.v:96203$3960 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_cry_in[1:0] $1\dec31_dec_sub24_cry_in[1:0] + attribute \src "libresoc.v:96204.5-96204.29" + switch \initial + attribute \src "libresoc.v:96204.9-96204.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_cry_in[1:0] 2'00 + case + assign $1\dec31_dec_sub24_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub24_cry_in $0\dec31_dec_sub24_cry_in[1:0] + end + attribute \src "libresoc.v:96222.3-96240.6" + process $proc$libresoc.v:96222$3961 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_asmcode[7:0] $1\dec31_dec_sub24_asmcode[7:0] + attribute \src "libresoc.v:96223.5-96223.29" + switch \initial + attribute \src "libresoc.v:96223.9-96223.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_asmcode[7:0] 8'10011111 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_asmcode[7:0] 8'10100010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_asmcode[7:0] 8'10100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_asmcode[7:0] 8'10100101 + case + assign $1\dec31_dec_sub24_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub24_asmcode $0\dec31_dec_sub24_asmcode[7:0] + end + attribute \src "libresoc.v:96241.3-96259.6" + process $proc$libresoc.v:96241$3962 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_inv_a[0:0] $1\dec31_dec_sub24_inv_a[0:0] + attribute \src "libresoc.v:96242.5-96242.29" + switch \initial + attribute \src "libresoc.v:96242.9-96242.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub24_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub24_inv_a $0\dec31_dec_sub24_inv_a[0:0] + end + attribute \src "libresoc.v:96260.3-96278.6" + process $proc$libresoc.v:96260$3963 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_inv_out[0:0] $1\dec31_dec_sub24_inv_out[0:0] + attribute \src "libresoc.v:96261.5-96261.29" + switch \initial + attribute \src "libresoc.v:96261.9-96261.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub24_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub24_inv_out $0\dec31_dec_sub24_inv_out[0:0] + end + attribute \src "libresoc.v:96279.3-96297.6" + process $proc$libresoc.v:96279$3964 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_cry_out[0:0] $1\dec31_dec_sub24_cry_out[0:0] + attribute \src "libresoc.v:96280.5-96280.29" + switch \initial + attribute \src "libresoc.v:96280.9-96280.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_cry_out[0:0] 1'0 + case + assign $1\dec31_dec_sub24_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub24_cry_out $0\dec31_dec_sub24_cry_out[0:0] + end + attribute \src "libresoc.v:96298.3-96316.6" + process $proc$libresoc.v:96298$3965 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_br[0:0] $1\dec31_dec_sub24_br[0:0] + attribute \src "libresoc.v:96299.5-96299.29" + switch \initial + attribute \src "libresoc.v:96299.9-96299.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_br[0:0] 1'0 + case + assign $1\dec31_dec_sub24_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub24_br $0\dec31_dec_sub24_br[0:0] + end + attribute \src "libresoc.v:96317.3-96335.6" + process $proc$libresoc.v:96317$3966 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_sgn_ext[0:0] $1\dec31_dec_sub24_sgn_ext[0:0] + attribute \src "libresoc.v:96318.5-96318.29" + switch \initial + attribute \src "libresoc.v:96318.9-96318.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub24_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub24_sgn_ext $0\dec31_dec_sub24_sgn_ext[0:0] + end + attribute \src "libresoc.v:96336.3-96354.6" + process $proc$libresoc.v:96336$3967 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_internal_op[6:0] $1\dec31_dec_sub24_internal_op[6:0] + attribute \src "libresoc.v:96337.5-96337.29" + switch \initial + attribute \src "libresoc.v:96337.9-96337.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_internal_op[6:0] 7'0111100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_internal_op[6:0] 7'0111101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_internal_op[6:0] 7'0111101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_internal_op[6:0] 7'0111101 + case + assign $1\dec31_dec_sub24_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub24_internal_op $0\dec31_dec_sub24_internal_op[6:0] + end + attribute \src "libresoc.v:96355.3-96373.6" + process $proc$libresoc.v:96355$3968 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_rsrv[0:0] $1\dec31_dec_sub24_rsrv[0:0] + attribute \src "libresoc.v:96356.5-96356.29" + switch \initial + attribute \src "libresoc.v:96356.9-96356.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub24_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub24_rsrv $0\dec31_dec_sub24_rsrv[0:0] + end + attribute \src "libresoc.v:96374.3-96392.6" + process $proc$libresoc.v:96374$3969 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_is_32b[0:0] $1\dec31_dec_sub24_is_32b[0:0] + attribute \src "libresoc.v:96375.5-96375.29" + switch \initial + attribute \src "libresoc.v:96375.9-96375.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_is_32b[0:0] 1'1 + case + assign $1\dec31_dec_sub24_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub24_is_32b $0\dec31_dec_sub24_is_32b[0:0] + end + attribute \src "libresoc.v:96393.3-96411.6" + process $proc$libresoc.v:96393$3970 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_sgn[0:0] $1\dec31_dec_sub24_sgn[0:0] + attribute \src "libresoc.v:96394.5-96394.29" + switch \initial + attribute \src "libresoc.v:96394.9-96394.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_sgn[0:0] 1'0 + case + assign $1\dec31_dec_sub24_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub24_sgn $0\dec31_dec_sub24_sgn[0:0] + end + attribute \src "libresoc.v:96412.3-96430.6" + process $proc$libresoc.v:96412$3971 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_lk[0:0] $1\dec31_dec_sub24_lk[0:0] + attribute \src "libresoc.v:96413.5-96413.29" + switch \initial + attribute \src "libresoc.v:96413.9-96413.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub24_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub24_lk $0\dec31_dec_sub24_lk[0:0] + end + attribute \src "libresoc.v:96431.3-96449.6" + process $proc$libresoc.v:96431$3972 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_sgl_pipe[0:0] $1\dec31_dec_sub24_sgl_pipe[0:0] + attribute \src "libresoc.v:96432.5-96432.29" + switch \initial + attribute \src "libresoc.v:96432.9-96432.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_sgl_pipe[0:0] 1'0 + case + assign $1\dec31_dec_sub24_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub24_sgl_pipe $0\dec31_dec_sub24_sgl_pipe[0:0] + end + attribute \src "libresoc.v:96450.3-96468.6" + process $proc$libresoc.v:96450$3973 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_form[4:0] $1\dec31_dec_sub24_form[4:0] + attribute \src "libresoc.v:96451.5-96451.29" + switch \initial + attribute \src "libresoc.v:96451.9-96451.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_form[4:0] 5'01000 + case + assign $1\dec31_dec_sub24_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub24_form $0\dec31_dec_sub24_form[4:0] + end + attribute \src "libresoc.v:96469.3-96487.6" + process $proc$libresoc.v:96469$3974 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_in1_sel[2:0] $1\dec31_dec_sub24_in1_sel[2:0] + attribute \src "libresoc.v:96470.5-96470.29" + switch \initial + attribute \src "libresoc.v:96470.9-96470.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_in1_sel[2:0] 3'000 + case + assign $1\dec31_dec_sub24_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub24_in1_sel $0\dec31_dec_sub24_in1_sel[2:0] + end + attribute \src "libresoc.v:96488.3-96506.6" + process $proc$libresoc.v:96488$3975 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_in2_sel[3:0] $1\dec31_dec_sub24_in2_sel[3:0] + attribute \src "libresoc.v:96489.5-96489.29" + switch \initial + attribute \src "libresoc.v:96489.9-96489.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_in2_sel[3:0] 4'1011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_in2_sel[3:0] 4'0001 + case + assign $1\dec31_dec_sub24_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub24_in2_sel $0\dec31_dec_sub24_in2_sel[3:0] + end + attribute \src "libresoc.v:96507.3-96525.6" + process $proc$libresoc.v:96507$3976 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_in3_sel[1:0] $1\dec31_dec_sub24_in3_sel[1:0] + attribute \src "libresoc.v:96508.5-96508.29" + switch \initial + attribute \src "libresoc.v:96508.9-96508.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_in3_sel[1:0] 2'01 + case + assign $1\dec31_dec_sub24_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub24_in3_sel $0\dec31_dec_sub24_in3_sel[1:0] + end + attribute \src "libresoc.v:96526.3-96544.6" + process $proc$libresoc.v:96526$3977 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_out_sel[1:0] $1\dec31_dec_sub24_out_sel[1:0] + attribute \src "libresoc.v:96527.5-96527.29" + switch \initial + attribute \src "libresoc.v:96527.9-96527.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_out_sel[1:0] 2'10 + case + assign $1\dec31_dec_sub24_out_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub24_out_sel $0\dec31_dec_sub24_out_sel[1:0] + end + attribute \src "libresoc.v:96545.3-96563.6" + process $proc$libresoc.v:96545$3978 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_cr_in[2:0] $1\dec31_dec_sub24_cr_in[2:0] + attribute \src "libresoc.v:96546.5-96546.29" + switch \initial + attribute \src "libresoc.v:96546.9-96546.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub24_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub24_cr_in $0\dec31_dec_sub24_cr_in[2:0] + end + attribute \src "libresoc.v:96564.3-96582.6" + process $proc$libresoc.v:96564$3979 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_cr_out[2:0] $1\dec31_dec_sub24_cr_out[2:0] + attribute \src "libresoc.v:96565.5-96565.29" + switch \initial + attribute \src "libresoc.v:96565.9-96565.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_cr_out[2:0] 3'001 + case + assign $1\dec31_dec_sub24_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub24_cr_out $0\dec31_dec_sub24_cr_out[2:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:96588.1-98095.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec31_dec_sub26" +attribute \generator "nMigen" +module \dec31_dec_sub26 + attribute \src "libresoc.v:97106.3-97157.6" + wire width 8 $0\dec31_dec_sub26_asmcode[7:0] + attribute \src "libresoc.v:97314.3-97365.6" + wire $0\dec31_dec_sub26_br[0:0] + attribute \src "libresoc.v:97990.3-98041.6" + wire width 3 $0\dec31_dec_sub26_cr_in[2:0] + attribute \src "libresoc.v:98042.3-98093.6" + wire width 3 $0\dec31_dec_sub26_cr_out[2:0] + attribute \src "libresoc.v:97054.3-97105.6" + wire width 2 $0\dec31_dec_sub26_cry_in[1:0] + attribute \src "libresoc.v:97262.3-97313.6" + wire $0\dec31_dec_sub26_cry_out[0:0] + attribute \src "libresoc.v:97730.3-97781.6" + wire width 5 $0\dec31_dec_sub26_form[4:0] + attribute \src "libresoc.v:96846.3-96897.6" + wire width 12 $0\dec31_dec_sub26_function_unit[11:0] + attribute \src "libresoc.v:97782.3-97833.6" + wire width 3 $0\dec31_dec_sub26_in1_sel[2:0] + attribute \src "libresoc.v:97834.3-97885.6" + wire width 4 $0\dec31_dec_sub26_in2_sel[3:0] + attribute \src "libresoc.v:97886.3-97937.6" + wire width 2 $0\dec31_dec_sub26_in3_sel[1:0] + attribute \src "libresoc.v:97418.3-97469.6" + wire width 7 $0\dec31_dec_sub26_internal_op[6:0] + attribute \src "libresoc.v:97158.3-97209.6" + wire $0\dec31_dec_sub26_inv_a[0:0] + attribute \src "libresoc.v:97210.3-97261.6" + wire $0\dec31_dec_sub26_inv_out[0:0] + attribute \src "libresoc.v:97522.3-97573.6" + wire $0\dec31_dec_sub26_is_32b[0:0] + attribute \src "libresoc.v:96898.3-96949.6" + wire width 4 $0\dec31_dec_sub26_ldst_len[3:0] + attribute \src "libresoc.v:97626.3-97677.6" + wire $0\dec31_dec_sub26_lk[0:0] + attribute \src "libresoc.v:97938.3-97989.6" + wire width 2 $0\dec31_dec_sub26_out_sel[1:0] + attribute \src "libresoc.v:97002.3-97053.6" + wire width 2 $0\dec31_dec_sub26_rc_sel[1:0] + attribute \src "libresoc.v:97470.3-97521.6" + wire $0\dec31_dec_sub26_rsrv[0:0] + attribute \src "libresoc.v:97678.3-97729.6" + wire $0\dec31_dec_sub26_sgl_pipe[0:0] + attribute \src "libresoc.v:97574.3-97625.6" + wire $0\dec31_dec_sub26_sgn[0:0] + attribute \src "libresoc.v:97366.3-97417.6" + wire $0\dec31_dec_sub26_sgn_ext[0:0] + attribute \src "libresoc.v:96950.3-97001.6" + wire width 2 $0\dec31_dec_sub26_upd[1:0] + attribute \src "libresoc.v:96589.7-96589.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:97106.3-97157.6" + wire width 8 $1\dec31_dec_sub26_asmcode[7:0] + attribute \src "libresoc.v:97314.3-97365.6" + wire $1\dec31_dec_sub26_br[0:0] + attribute \src "libresoc.v:97990.3-98041.6" + wire width 3 $1\dec31_dec_sub26_cr_in[2:0] + attribute \src "libresoc.v:98042.3-98093.6" + wire width 3 $1\dec31_dec_sub26_cr_out[2:0] + attribute \src "libresoc.v:97054.3-97105.6" + wire width 2 $1\dec31_dec_sub26_cry_in[1:0] + attribute \src "libresoc.v:97262.3-97313.6" + wire $1\dec31_dec_sub26_cry_out[0:0] + attribute \src "libresoc.v:97730.3-97781.6" + wire width 5 $1\dec31_dec_sub26_form[4:0] + attribute \src "libresoc.v:96846.3-96897.6" + wire width 12 $1\dec31_dec_sub26_function_unit[11:0] + attribute \src "libresoc.v:97782.3-97833.6" + wire width 3 $1\dec31_dec_sub26_in1_sel[2:0] + attribute \src "libresoc.v:97834.3-97885.6" + wire width 4 $1\dec31_dec_sub26_in2_sel[3:0] + attribute \src "libresoc.v:97886.3-97937.6" + wire width 2 $1\dec31_dec_sub26_in3_sel[1:0] + attribute \src "libresoc.v:97418.3-97469.6" + wire width 7 $1\dec31_dec_sub26_internal_op[6:0] + attribute \src "libresoc.v:97158.3-97209.6" + wire $1\dec31_dec_sub26_inv_a[0:0] + attribute \src "libresoc.v:97210.3-97261.6" + wire $1\dec31_dec_sub26_inv_out[0:0] + attribute \src "libresoc.v:97522.3-97573.6" + wire $1\dec31_dec_sub26_is_32b[0:0] + attribute \src "libresoc.v:96898.3-96949.6" + wire width 4 $1\dec31_dec_sub26_ldst_len[3:0] + attribute \src "libresoc.v:97626.3-97677.6" + wire $1\dec31_dec_sub26_lk[0:0] + attribute \src "libresoc.v:97938.3-97989.6" + wire width 2 $1\dec31_dec_sub26_out_sel[1:0] + attribute \src "libresoc.v:97002.3-97053.6" + wire width 2 $1\dec31_dec_sub26_rc_sel[1:0] + attribute \src "libresoc.v:97470.3-97521.6" + wire $1\dec31_dec_sub26_rsrv[0:0] + attribute \src "libresoc.v:97678.3-97729.6" + wire $1\dec31_dec_sub26_sgl_pipe[0:0] + attribute \src "libresoc.v:97574.3-97625.6" + wire $1\dec31_dec_sub26_sgn[0:0] + attribute \src "libresoc.v:97366.3-97417.6" + wire $1\dec31_dec_sub26_sgn_ext[0:0] + attribute \src "libresoc.v:96950.3-97001.6" + wire width 2 $1\dec31_dec_sub26_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 output 4 \dec31_dec_sub26_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 18 \dec31_dec_sub26_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 9 \dec31_dec_sub26_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 10 \dec31_dec_sub26_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 14 \dec31_dec_sub26_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 17 \dec31_dec_sub26_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 output 3 \dec31_dec_sub26_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \dec31_dec_sub26_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \dec31_dec_sub26_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 6 \dec31_dec_sub26_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 7 \dec31_dec_sub26_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \dec31_dec_sub26_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 15 \dec31_dec_sub26_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 16 \dec31_dec_sub26_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 21 \dec31_dec_sub26_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 11 \dec31_dec_sub26_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 23 \dec31_dec_sub26_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 8 \dec31_dec_sub26_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 13 \dec31_dec_sub26_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 20 \dec31_dec_sub26_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 24 \dec31_dec_sub26_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 22 \dec31_dec_sub26_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 19 \dec31_dec_sub26_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 12 \dec31_dec_sub26_upd + attribute \src "libresoc.v:96589.7-96589.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 5 \opcode_switch + attribute \src "libresoc.v:96589.7-96589.20" + process $proc$libresoc.v:96589$4005 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:96846.3-96897.6" + process $proc$libresoc.v:96846$3981 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_function_unit[11:0] $1\dec31_dec_sub26_function_unit[11:0] + attribute \src "libresoc.v:96847.5-96847.29" + switch \initial + attribute \src "libresoc.v:96847.9-96847.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000001000 + case + assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000000000 + end + sync always + update \dec31_dec_sub26_function_unit $0\dec31_dec_sub26_function_unit[11:0] + end + attribute \src "libresoc.v:96898.3-96949.6" + process $proc$libresoc.v:96898$3982 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_ldst_len[3:0] $1\dec31_dec_sub26_ldst_len[3:0] + attribute \src "libresoc.v:96899.5-96899.29" + switch \initial + attribute \src "libresoc.v:96899.9-96899.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0000 + case + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub26_ldst_len $0\dec31_dec_sub26_ldst_len[3:0] + end + attribute \src "libresoc.v:96950.3-97001.6" + process $proc$libresoc.v:96950$3983 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_upd[1:0] $1\dec31_dec_sub26_upd[1:0] + attribute \src "libresoc.v:96951.5-96951.29" + switch \initial + attribute \src "libresoc.v:96951.9-96951.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub26_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub26_upd $0\dec31_dec_sub26_upd[1:0] + end + attribute \src "libresoc.v:97002.3-97053.6" + process $proc$libresoc.v:97002$3984 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_rc_sel[1:0] $1\dec31_dec_sub26_rc_sel[1:0] + attribute \src "libresoc.v:97003.5-97003.29" + switch \initial + attribute \src "libresoc.v:97003.9-97003.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 + case + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub26_rc_sel $0\dec31_dec_sub26_rc_sel[1:0] + end + attribute \src "libresoc.v:97054.3-97105.6" + process $proc$libresoc.v:97054$3985 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_cry_in[1:0] $1\dec31_dec_sub26_cry_in[1:0] + attribute \src "libresoc.v:97055.5-97055.29" + switch \initial + attribute \src "libresoc.v:97055.9-97055.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + case + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub26_cry_in $0\dec31_dec_sub26_cry_in[1:0] + end + attribute \src "libresoc.v:97106.3-97157.6" + process $proc$libresoc.v:97106$3986 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_asmcode[7:0] $1\dec31_dec_sub26_asmcode[7:0] + attribute \src "libresoc.v:97107.5-97107.29" + switch \initial + attribute \src "libresoc.v:97107.9-97107.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_asmcode[7:0] 8'00100001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_asmcode[7:0] 8'00100010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_asmcode[7:0] 8'00100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_asmcode[7:0] 8'00100100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_asmcode[7:0] 8'01000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_asmcode[7:0] 8'01000101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_asmcode[7:0] 8'01000110 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_asmcode[7:0] 8'01000111 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_asmcode[7:0] 8'10001100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_asmcode[7:0] 8'10001101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_asmcode[7:0] 8'10001110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_asmcode[7:0] 8'10001111 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_asmcode[7:0] 8'10010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_asmcode[7:0] 8'10100000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_asmcode[7:0] 8'10100001 + case + assign $1\dec31_dec_sub26_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub26_asmcode $0\dec31_dec_sub26_asmcode[7:0] + end + attribute \src "libresoc.v:97158.3-97209.6" + process $proc$libresoc.v:97158$3987 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_inv_a[0:0] $1\dec31_dec_sub26_inv_a[0:0] + attribute \src "libresoc.v:97159.5-97159.29" + switch \initial + attribute \src "libresoc.v:97159.9-97159.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub26_inv_a $0\dec31_dec_sub26_inv_a[0:0] + end + attribute \src "libresoc.v:97210.3-97261.6" + process $proc$libresoc.v:97210$3988 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_inv_out[0:0] $1\dec31_dec_sub26_inv_out[0:0] + attribute \src "libresoc.v:97211.5-97211.29" + switch \initial + attribute \src "libresoc.v:97211.9-97211.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub26_inv_out $0\dec31_dec_sub26_inv_out[0:0] + end + attribute \src "libresoc.v:97262.3-97313.6" + process $proc$libresoc.v:97262$3989 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_cry_out[0:0] $1\dec31_dec_sub26_cry_out[0:0] + attribute \src "libresoc.v:97263.5-97263.29" + switch \initial + attribute \src "libresoc.v:97263.9-97263.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_cry_out[0:0] 1'1 + case + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub26_cry_out $0\dec31_dec_sub26_cry_out[0:0] + end + attribute \src "libresoc.v:97314.3-97365.6" + process $proc$libresoc.v:97314$3990 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_br[0:0] $1\dec31_dec_sub26_br[0:0] + attribute \src "libresoc.v:97315.5-97315.29" + switch \initial + attribute \src "libresoc.v:97315.9-97315.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_br[0:0] 1'0 + case + assign $1\dec31_dec_sub26_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub26_br $0\dec31_dec_sub26_br[0:0] + end + attribute \src "libresoc.v:97366.3-97417.6" + process $proc$libresoc.v:97366$3991 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_sgn_ext[0:0] $1\dec31_dec_sub26_sgn_ext[0:0] + attribute \src "libresoc.v:97367.5-97367.29" + switch \initial + attribute \src "libresoc.v:97367.9-97367.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub26_sgn_ext $0\dec31_dec_sub26_sgn_ext[0:0] + end + attribute \src "libresoc.v:97418.3-97469.6" + process $proc$libresoc.v:97418$3992 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_internal_op[6:0] $1\dec31_dec_sub26_internal_op[6:0] + attribute \src "libresoc.v:97419.5-97419.29" + switch \initial + attribute \src "libresoc.v:97419.9-97419.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0001110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0001110 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0001110 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0001110 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0011111 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0011111 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0011111 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0100000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0110110 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0110110 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0110110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0110111 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0110111 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0111101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0111101 + case + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub26_internal_op $0\dec31_dec_sub26_internal_op[6:0] + end + attribute \src "libresoc.v:97470.3-97521.6" + process $proc$libresoc.v:97470$3993 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_rsrv[0:0] $1\dec31_dec_sub26_rsrv[0:0] + attribute \src "libresoc.v:97471.5-97471.29" + switch \initial + attribute \src "libresoc.v:97471.9-97471.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub26_rsrv $0\dec31_dec_sub26_rsrv[0:0] + end + attribute \src "libresoc.v:97522.3-97573.6" + process $proc$libresoc.v:97522$3994 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_is_32b[0:0] $1\dec31_dec_sub26_is_32b[0:0] + attribute \src "libresoc.v:97523.5-97523.29" + switch \initial + attribute \src "libresoc.v:97523.9-97523.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + case + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub26_is_32b $0\dec31_dec_sub26_is_32b[0:0] + end + attribute \src "libresoc.v:97574.3-97625.6" + process $proc$libresoc.v:97574$3995 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_sgn[0:0] $1\dec31_dec_sub26_sgn[0:0] + attribute \src "libresoc.v:97575.5-97575.29" + switch \initial + attribute \src "libresoc.v:97575.9-97575.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_sgn[0:0] 1'1 + case + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub26_sgn $0\dec31_dec_sub26_sgn[0:0] + end + attribute \src "libresoc.v:97626.3-97677.6" + process $proc$libresoc.v:97626$3996 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_lk[0:0] $1\dec31_dec_sub26_lk[0:0] + attribute \src "libresoc.v:97627.5-97627.29" + switch \initial + attribute \src "libresoc.v:97627.9-97627.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub26_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub26_lk $0\dec31_dec_sub26_lk[0:0] + end + attribute \src "libresoc.v:97678.3-97729.6" + process $proc$libresoc.v:97678$3997 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_sgl_pipe[0:0] $1\dec31_dec_sub26_sgl_pipe[0:0] + attribute \src "libresoc.v:97679.5-97679.29" + switch \initial + attribute \src "libresoc.v:97679.9-97679.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + case + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub26_sgl_pipe $0\dec31_dec_sub26_sgl_pipe[0:0] + end + attribute \src "libresoc.v:97730.3-97781.6" + process $proc$libresoc.v:97730$3998 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_form[4:0] $1\dec31_dec_sub26_form[4:0] + attribute \src "libresoc.v:97731.5-97731.29" + switch \initial + attribute \src "libresoc.v:97731.9-97731.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_form[4:0] 5'10000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_form[4:0] 5'10000 + case + assign $1\dec31_dec_sub26_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub26_form $0\dec31_dec_sub26_form[4:0] + end + attribute \src "libresoc.v:97782.3-97833.6" + process $proc$libresoc.v:97782$3999 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_in1_sel[2:0] $1\dec31_dec_sub26_in1_sel[2:0] + attribute \src "libresoc.v:97783.5-97783.29" + switch \initial + attribute \src "libresoc.v:97783.9-97783.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'000 + case + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub26_in1_sel $0\dec31_dec_sub26_in1_sel[2:0] + end + attribute \src "libresoc.v:97834.3-97885.6" + process $proc$libresoc.v:97834$4000 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_in2_sel[3:0] $1\dec31_dec_sub26_in2_sel[3:0] + attribute \src "libresoc.v:97835.5-97835.29" + switch \initial + attribute \src "libresoc.v:97835.9-97835.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'1010 + case + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub26_in2_sel $0\dec31_dec_sub26_in2_sel[3:0] + end + attribute \src "libresoc.v:97886.3-97937.6" + process $proc$libresoc.v:97886$4001 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_in3_sel[1:0] $1\dec31_dec_sub26_in3_sel[1:0] + attribute \src "libresoc.v:97887.5-97887.29" + switch \initial + attribute \src "libresoc.v:97887.9-97887.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'01 + case + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub26_in3_sel $0\dec31_dec_sub26_in3_sel[1:0] + end + attribute \src "libresoc.v:97938.3-97989.6" + process $proc$libresoc.v:97938$4002 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_out_sel[1:0] $1\dec31_dec_sub26_out_sel[1:0] + attribute \src "libresoc.v:97939.5-97939.29" + switch \initial + attribute \src "libresoc.v:97939.9-97939.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 + case + assign $1\dec31_dec_sub26_out_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub26_out_sel $0\dec31_dec_sub26_out_sel[1:0] + end + attribute \src "libresoc.v:97990.3-98041.6" + process $proc$libresoc.v:97990$4003 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_cr_in[2:0] $1\dec31_dec_sub26_cr_in[2:0] + attribute \src "libresoc.v:97991.5-97991.29" + switch \initial + attribute \src "libresoc.v:97991.9-97991.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub26_cr_in $0\dec31_dec_sub26_cr_in[2:0] + end + attribute \src "libresoc.v:98042.3-98093.6" + process $proc$libresoc.v:98042$4004 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_cr_out[2:0] $1\dec31_dec_sub26_cr_out[2:0] + attribute \src "libresoc.v:98043.5-98043.29" + switch \initial + attribute \src "libresoc.v:98043.9-98043.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 + case + assign $1\dec31_dec_sub26_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub26_cr_out $0\dec31_dec_sub26_cr_out[2:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:98099.1-98814.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec31_dec_sub27" +attribute \generator "nMigen" +module \dec31_dec_sub27 + attribute \src "libresoc.v:98452.3-98470.6" + wire width 8 $0\dec31_dec_sub27_asmcode[7:0] + attribute \src "libresoc.v:98528.3-98546.6" + wire $0\dec31_dec_sub27_br[0:0] + attribute \src "libresoc.v:98775.3-98793.6" + wire width 3 $0\dec31_dec_sub27_cr_in[2:0] + attribute \src "libresoc.v:98794.3-98812.6" + wire width 3 $0\dec31_dec_sub27_cr_out[2:0] + attribute \src "libresoc.v:98433.3-98451.6" + wire width 2 $0\dec31_dec_sub27_cry_in[1:0] + attribute \src "libresoc.v:98509.3-98527.6" + wire $0\dec31_dec_sub27_cry_out[0:0] + attribute \src "libresoc.v:98680.3-98698.6" + wire width 5 $0\dec31_dec_sub27_form[4:0] + attribute \src "libresoc.v:98357.3-98375.6" + wire width 12 $0\dec31_dec_sub27_function_unit[11:0] + attribute \src "libresoc.v:98699.3-98717.6" + wire width 3 $0\dec31_dec_sub27_in1_sel[2:0] + attribute \src "libresoc.v:98718.3-98736.6" + wire width 4 $0\dec31_dec_sub27_in2_sel[3:0] + attribute \src "libresoc.v:98737.3-98755.6" + wire width 2 $0\dec31_dec_sub27_in3_sel[1:0] + attribute \src "libresoc.v:98566.3-98584.6" + wire width 7 $0\dec31_dec_sub27_internal_op[6:0] + attribute \src "libresoc.v:98471.3-98489.6" + wire $0\dec31_dec_sub27_inv_a[0:0] + attribute \src "libresoc.v:98490.3-98508.6" + wire $0\dec31_dec_sub27_inv_out[0:0] + attribute \src "libresoc.v:98604.3-98622.6" + wire $0\dec31_dec_sub27_is_32b[0:0] + attribute \src "libresoc.v:98376.3-98394.6" + wire width 4 $0\dec31_dec_sub27_ldst_len[3:0] + attribute \src "libresoc.v:98642.3-98660.6" + wire $0\dec31_dec_sub27_lk[0:0] + attribute \src "libresoc.v:98756.3-98774.6" + wire width 2 $0\dec31_dec_sub27_out_sel[1:0] + attribute \src "libresoc.v:98414.3-98432.6" + wire width 2 $0\dec31_dec_sub27_rc_sel[1:0] + attribute \src "libresoc.v:98585.3-98603.6" + wire $0\dec31_dec_sub27_rsrv[0:0] + attribute \src "libresoc.v:98661.3-98679.6" + wire $0\dec31_dec_sub27_sgl_pipe[0:0] + attribute \src "libresoc.v:98623.3-98641.6" + wire $0\dec31_dec_sub27_sgn[0:0] + attribute \src "libresoc.v:98547.3-98565.6" + wire $0\dec31_dec_sub27_sgn_ext[0:0] + attribute \src "libresoc.v:98395.3-98413.6" + wire width 2 $0\dec31_dec_sub27_upd[1:0] + attribute \src "libresoc.v:98100.7-98100.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:98452.3-98470.6" + wire width 8 $1\dec31_dec_sub27_asmcode[7:0] + attribute \src "libresoc.v:98528.3-98546.6" + wire $1\dec31_dec_sub27_br[0:0] + attribute \src "libresoc.v:98775.3-98793.6" + wire width 3 $1\dec31_dec_sub27_cr_in[2:0] + attribute \src "libresoc.v:98794.3-98812.6" + wire width 3 $1\dec31_dec_sub27_cr_out[2:0] + attribute \src "libresoc.v:98433.3-98451.6" + wire width 2 $1\dec31_dec_sub27_cry_in[1:0] + attribute \src "libresoc.v:98509.3-98527.6" + wire $1\dec31_dec_sub27_cry_out[0:0] + attribute \src "libresoc.v:98680.3-98698.6" + wire width 5 $1\dec31_dec_sub27_form[4:0] + attribute \src "libresoc.v:98357.3-98375.6" + wire width 12 $1\dec31_dec_sub27_function_unit[11:0] + attribute \src "libresoc.v:98699.3-98717.6" + wire width 3 $1\dec31_dec_sub27_in1_sel[2:0] + attribute \src "libresoc.v:98718.3-98736.6" + wire width 4 $1\dec31_dec_sub27_in2_sel[3:0] + attribute \src "libresoc.v:98737.3-98755.6" + wire width 2 $1\dec31_dec_sub27_in3_sel[1:0] + attribute \src "libresoc.v:98566.3-98584.6" + wire width 7 $1\dec31_dec_sub27_internal_op[6:0] + attribute \src "libresoc.v:98471.3-98489.6" + wire $1\dec31_dec_sub27_inv_a[0:0] + attribute \src "libresoc.v:98490.3-98508.6" + wire $1\dec31_dec_sub27_inv_out[0:0] + attribute \src "libresoc.v:98604.3-98622.6" + wire $1\dec31_dec_sub27_is_32b[0:0] + attribute \src "libresoc.v:98376.3-98394.6" + wire width 4 $1\dec31_dec_sub27_ldst_len[3:0] + attribute \src "libresoc.v:98642.3-98660.6" + wire $1\dec31_dec_sub27_lk[0:0] + attribute \src "libresoc.v:98756.3-98774.6" + wire width 2 $1\dec31_dec_sub27_out_sel[1:0] + attribute \src "libresoc.v:98414.3-98432.6" + wire width 2 $1\dec31_dec_sub27_rc_sel[1:0] + attribute \src "libresoc.v:98585.3-98603.6" + wire $1\dec31_dec_sub27_rsrv[0:0] + attribute \src "libresoc.v:98661.3-98679.6" + wire $1\dec31_dec_sub27_sgl_pipe[0:0] + attribute \src "libresoc.v:98623.3-98641.6" + wire $1\dec31_dec_sub27_sgn[0:0] + attribute \src "libresoc.v:98547.3-98565.6" + wire $1\dec31_dec_sub27_sgn_ext[0:0] + attribute \src "libresoc.v:98395.3-98413.6" + wire width 2 $1\dec31_dec_sub27_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 output 4 \dec31_dec_sub27_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 18 \dec31_dec_sub27_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 9 \dec31_dec_sub27_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 10 \dec31_dec_sub27_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 14 \dec31_dec_sub27_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 17 \dec31_dec_sub27_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 output 3 \dec31_dec_sub27_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \dec31_dec_sub27_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \dec31_dec_sub27_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 6 \dec31_dec_sub27_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 7 \dec31_dec_sub27_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \dec31_dec_sub27_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 15 \dec31_dec_sub27_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 16 \dec31_dec_sub27_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 21 \dec31_dec_sub27_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 11 \dec31_dec_sub27_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 23 \dec31_dec_sub27_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 8 \dec31_dec_sub27_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 13 \dec31_dec_sub27_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 20 \dec31_dec_sub27_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 24 \dec31_dec_sub27_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 22 \dec31_dec_sub27_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 19 \dec31_dec_sub27_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 12 \dec31_dec_sub27_upd + attribute \src "libresoc.v:98100.7-98100.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 5 \opcode_switch + attribute \src "libresoc.v:98100.7-98100.20" + process $proc$libresoc.v:98100$4030 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:98357.3-98375.6" + process $proc$libresoc.v:98357$4006 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_function_unit[11:0] $1\dec31_dec_sub27_function_unit[11:0] + attribute \src "libresoc.v:98358.5-98358.29" + switch \initial + attribute \src "libresoc.v:98358.9-98358.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_function_unit[11:0] 12'000000001000 + case + assign $1\dec31_dec_sub27_function_unit[11:0] 12'000000000000 + end + sync always + update \dec31_dec_sub27_function_unit $0\dec31_dec_sub27_function_unit[11:0] + end + attribute \src "libresoc.v:98376.3-98394.6" + process $proc$libresoc.v:98376$4007 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_ldst_len[3:0] $1\dec31_dec_sub27_ldst_len[3:0] + attribute \src "libresoc.v:98377.5-98377.29" + switch \initial + attribute \src "libresoc.v:98377.9-98377.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_ldst_len[3:0] 4'0000 + case + assign $1\dec31_dec_sub27_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub27_ldst_len $0\dec31_dec_sub27_ldst_len[3:0] + end + attribute \src "libresoc.v:98395.3-98413.6" + process $proc$libresoc.v:98395$4008 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_upd[1:0] $1\dec31_dec_sub27_upd[1:0] + attribute \src "libresoc.v:98396.5-98396.29" + switch \initial + attribute \src "libresoc.v:98396.9-98396.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub27_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub27_upd $0\dec31_dec_sub27_upd[1:0] + end + attribute \src "libresoc.v:98414.3-98432.6" + process $proc$libresoc.v:98414$4009 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_rc_sel[1:0] $1\dec31_dec_sub27_rc_sel[1:0] + attribute \src "libresoc.v:98415.5-98415.29" + switch \initial + attribute \src "libresoc.v:98415.9-98415.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_rc_sel[1:0] 2'10 + case + assign $1\dec31_dec_sub27_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub27_rc_sel $0\dec31_dec_sub27_rc_sel[1:0] + end + attribute \src "libresoc.v:98433.3-98451.6" + process $proc$libresoc.v:98433$4010 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_cry_in[1:0] $1\dec31_dec_sub27_cry_in[1:0] + attribute \src "libresoc.v:98434.5-98434.29" + switch \initial + attribute \src "libresoc.v:98434.9-98434.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_cry_in[1:0] 2'00 + case + assign $1\dec31_dec_sub27_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub27_cry_in $0\dec31_dec_sub27_cry_in[1:0] + end + attribute \src "libresoc.v:98452.3-98470.6" + process $proc$libresoc.v:98452$4011 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_asmcode[7:0] $1\dec31_dec_sub27_asmcode[7:0] + attribute \src "libresoc.v:98453.5-98453.29" + switch \initial + attribute \src "libresoc.v:98453.9-98453.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_asmcode[7:0] 8'01000111 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_asmcode[7:0] 8'10011110 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_asmcode[7:0] 8'10100001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_asmcode[7:0] 8'10100100 + case + assign $1\dec31_dec_sub27_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub27_asmcode $0\dec31_dec_sub27_asmcode[7:0] + end + attribute \src "libresoc.v:98471.3-98489.6" + process $proc$libresoc.v:98471$4012 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_inv_a[0:0] $1\dec31_dec_sub27_inv_a[0:0] + attribute \src "libresoc.v:98472.5-98472.29" + switch \initial + attribute \src "libresoc.v:98472.9-98472.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub27_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub27_inv_a $0\dec31_dec_sub27_inv_a[0:0] + end + attribute \src "libresoc.v:98490.3-98508.6" + process $proc$libresoc.v:98490$4013 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_inv_out[0:0] $1\dec31_dec_sub27_inv_out[0:0] + attribute \src "libresoc.v:98491.5-98491.29" + switch \initial + attribute \src "libresoc.v:98491.9-98491.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub27_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub27_inv_out $0\dec31_dec_sub27_inv_out[0:0] + end + attribute \src "libresoc.v:98509.3-98527.6" + process $proc$libresoc.v:98509$4014 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_cry_out[0:0] $1\dec31_dec_sub27_cry_out[0:0] + attribute \src "libresoc.v:98510.5-98510.29" + switch \initial + attribute \src "libresoc.v:98510.9-98510.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_cry_out[0:0] 1'0 + case + assign $1\dec31_dec_sub27_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub27_cry_out $0\dec31_dec_sub27_cry_out[0:0] + end + attribute \src "libresoc.v:98528.3-98546.6" + process $proc$libresoc.v:98528$4015 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_br[0:0] $1\dec31_dec_sub27_br[0:0] + attribute \src "libresoc.v:98529.5-98529.29" + switch \initial + attribute \src "libresoc.v:98529.9-98529.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_br[0:0] 1'0 + case + assign $1\dec31_dec_sub27_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub27_br $0\dec31_dec_sub27_br[0:0] + end + attribute \src "libresoc.v:98547.3-98565.6" + process $proc$libresoc.v:98547$4016 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_sgn_ext[0:0] $1\dec31_dec_sub27_sgn_ext[0:0] + attribute \src "libresoc.v:98548.5-98548.29" + switch \initial + attribute \src "libresoc.v:98548.9-98548.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub27_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub27_sgn_ext $0\dec31_dec_sub27_sgn_ext[0:0] + end + attribute \src "libresoc.v:98566.3-98584.6" + process $proc$libresoc.v:98566$4017 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_internal_op[6:0] $1\dec31_dec_sub27_internal_op[6:0] + attribute \src "libresoc.v:98567.5-98567.29" + switch \initial + attribute \src "libresoc.v:98567.9-98567.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_internal_op[6:0] 7'0100000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_internal_op[6:0] 7'0111100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_internal_op[6:0] 7'0111101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_internal_op[6:0] 7'0111101 + case + assign $1\dec31_dec_sub27_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub27_internal_op $0\dec31_dec_sub27_internal_op[6:0] + end + attribute \src "libresoc.v:98585.3-98603.6" + process $proc$libresoc.v:98585$4018 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_rsrv[0:0] $1\dec31_dec_sub27_rsrv[0:0] + attribute \src "libresoc.v:98586.5-98586.29" + switch \initial + attribute \src "libresoc.v:98586.9-98586.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub27_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub27_rsrv $0\dec31_dec_sub27_rsrv[0:0] + end + attribute \src "libresoc.v:98604.3-98622.6" + process $proc$libresoc.v:98604$4019 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_is_32b[0:0] $1\dec31_dec_sub27_is_32b[0:0] + attribute \src "libresoc.v:98605.5-98605.29" + switch \initial + attribute \src "libresoc.v:98605.9-98605.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_is_32b[0:0] 1'0 + case + assign $1\dec31_dec_sub27_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub27_is_32b $0\dec31_dec_sub27_is_32b[0:0] + end + attribute \src "libresoc.v:98623.3-98641.6" + process $proc$libresoc.v:98623$4020 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_sgn[0:0] $1\dec31_dec_sub27_sgn[0:0] + attribute \src "libresoc.v:98624.5-98624.29" + switch \initial + attribute \src "libresoc.v:98624.9-98624.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_sgn[0:0] 1'0 + case + assign $1\dec31_dec_sub27_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub27_sgn $0\dec31_dec_sub27_sgn[0:0] + end + attribute \src "libresoc.v:98642.3-98660.6" + process $proc$libresoc.v:98642$4021 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_lk[0:0] $1\dec31_dec_sub27_lk[0:0] + attribute \src "libresoc.v:98643.5-98643.29" + switch \initial + attribute \src "libresoc.v:98643.9-98643.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub27_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub27_lk $0\dec31_dec_sub27_lk[0:0] + end + attribute \src "libresoc.v:98661.3-98679.6" + process $proc$libresoc.v:98661$4022 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_sgl_pipe[0:0] $1\dec31_dec_sub27_sgl_pipe[0:0] + attribute \src "libresoc.v:98662.5-98662.29" + switch \initial + attribute \src "libresoc.v:98662.9-98662.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_sgl_pipe[0:0] 1'0 + case + assign $1\dec31_dec_sub27_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub27_sgl_pipe $0\dec31_dec_sub27_sgl_pipe[0:0] + end + attribute \src "libresoc.v:98680.3-98698.6" + process $proc$libresoc.v:98680$4023 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_form[4:0] $1\dec31_dec_sub27_form[4:0] + attribute \src "libresoc.v:98681.5-98681.29" + switch \initial + attribute \src "libresoc.v:98681.9-98681.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_form[4:0] 5'10000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_form[4:0] 5'10000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_form[4:0] 5'01000 + case + assign $1\dec31_dec_sub27_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub27_form $0\dec31_dec_sub27_form[4:0] + end + attribute \src "libresoc.v:98699.3-98717.6" + process $proc$libresoc.v:98699$4024 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_in1_sel[2:0] $1\dec31_dec_sub27_in1_sel[2:0] + attribute \src "libresoc.v:98700.5-98700.29" + switch \initial + attribute \src "libresoc.v:98700.9-98700.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_in1_sel[2:0] 3'000 + case + assign $1\dec31_dec_sub27_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub27_in1_sel $0\dec31_dec_sub27_in1_sel[2:0] + end + attribute \src "libresoc.v:98718.3-98736.6" + process $proc$libresoc.v:98718$4025 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_in2_sel[3:0] $1\dec31_dec_sub27_in2_sel[3:0] + attribute \src "libresoc.v:98719.5-98719.29" + switch \initial + attribute \src "libresoc.v:98719.9-98719.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_in2_sel[3:0] 4'0001 + case + assign $1\dec31_dec_sub27_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub27_in2_sel $0\dec31_dec_sub27_in2_sel[3:0] + end + attribute \src "libresoc.v:98737.3-98755.6" + process $proc$libresoc.v:98737$4026 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_in3_sel[1:0] $1\dec31_dec_sub27_in3_sel[1:0] + attribute \src "libresoc.v:98738.5-98738.29" + switch \initial + attribute \src "libresoc.v:98738.9-98738.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_in3_sel[1:0] 2'01 + case + assign $1\dec31_dec_sub27_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub27_in3_sel $0\dec31_dec_sub27_in3_sel[1:0] + end + attribute \src "libresoc.v:98756.3-98774.6" + process $proc$libresoc.v:98756$4027 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_out_sel[1:0] $1\dec31_dec_sub27_out_sel[1:0] + attribute \src "libresoc.v:98757.5-98757.29" + switch \initial + attribute \src "libresoc.v:98757.9-98757.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_out_sel[1:0] 2'10 + case + assign $1\dec31_dec_sub27_out_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub27_out_sel $0\dec31_dec_sub27_out_sel[1:0] + end + attribute \src "libresoc.v:98775.3-98793.6" + process $proc$libresoc.v:98775$4028 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_cr_in[2:0] $1\dec31_dec_sub27_cr_in[2:0] + attribute \src "libresoc.v:98776.5-98776.29" + switch \initial + attribute \src "libresoc.v:98776.9-98776.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub27_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub27_cr_in $0\dec31_dec_sub27_cr_in[2:0] + end + attribute \src "libresoc.v:98794.3-98812.6" + process $proc$libresoc.v:98794$4029 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_cr_out[2:0] $1\dec31_dec_sub27_cr_out[2:0] + attribute \src "libresoc.v:98795.5-98795.29" + switch \initial + attribute \src "libresoc.v:98795.9-98795.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_cr_out[2:0] 3'001 + case + assign $1\dec31_dec_sub27_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub27_cr_out $0\dec31_dec_sub27_cr_out[2:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:98818.1-99965.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec31_dec_sub28" +attribute \generator "nMigen" +module \dec31_dec_sub28 + attribute \src "libresoc.v:99261.3-99297.6" + wire width 8 $0\dec31_dec_sub28_asmcode[7:0] + attribute \src "libresoc.v:99409.3-99445.6" + wire $0\dec31_dec_sub28_br[0:0] + attribute \src "libresoc.v:99890.3-99926.6" + wire width 3 $0\dec31_dec_sub28_cr_in[2:0] + attribute \src "libresoc.v:99927.3-99963.6" + wire width 3 $0\dec31_dec_sub28_cr_out[2:0] + attribute \src "libresoc.v:99224.3-99260.6" + wire width 2 $0\dec31_dec_sub28_cry_in[1:0] + attribute \src "libresoc.v:99372.3-99408.6" + wire $0\dec31_dec_sub28_cry_out[0:0] + attribute \src "libresoc.v:99705.3-99741.6" + wire width 5 $0\dec31_dec_sub28_form[4:0] + attribute \src "libresoc.v:99076.3-99112.6" + wire width 12 $0\dec31_dec_sub28_function_unit[11:0] + attribute \src "libresoc.v:99742.3-99778.6" + wire width 3 $0\dec31_dec_sub28_in1_sel[2:0] + attribute \src "libresoc.v:99779.3-99815.6" + wire width 4 $0\dec31_dec_sub28_in2_sel[3:0] + attribute \src "libresoc.v:99816.3-99852.6" + wire width 2 $0\dec31_dec_sub28_in3_sel[1:0] + attribute \src "libresoc.v:99483.3-99519.6" + wire width 7 $0\dec31_dec_sub28_internal_op[6:0] + attribute \src "libresoc.v:99298.3-99334.6" + wire $0\dec31_dec_sub28_inv_a[0:0] + attribute \src "libresoc.v:99335.3-99371.6" + wire $0\dec31_dec_sub28_inv_out[0:0] + attribute \src "libresoc.v:99557.3-99593.6" + wire $0\dec31_dec_sub28_is_32b[0:0] + attribute \src "libresoc.v:99113.3-99149.6" + wire width 4 $0\dec31_dec_sub28_ldst_len[3:0] + attribute \src "libresoc.v:99631.3-99667.6" + wire $0\dec31_dec_sub28_lk[0:0] + attribute \src "libresoc.v:99853.3-99889.6" + wire width 2 $0\dec31_dec_sub28_out_sel[1:0] + attribute \src "libresoc.v:99187.3-99223.6" + wire width 2 $0\dec31_dec_sub28_rc_sel[1:0] + attribute \src "libresoc.v:99520.3-99556.6" + wire $0\dec31_dec_sub28_rsrv[0:0] + attribute \src "libresoc.v:99668.3-99704.6" + wire $0\dec31_dec_sub28_sgl_pipe[0:0] + attribute \src "libresoc.v:99594.3-99630.6" + wire $0\dec31_dec_sub28_sgn[0:0] + attribute \src "libresoc.v:99446.3-99482.6" + wire $0\dec31_dec_sub28_sgn_ext[0:0] + attribute \src "libresoc.v:99150.3-99186.6" + wire width 2 $0\dec31_dec_sub28_upd[1:0] + attribute \src "libresoc.v:98819.7-98819.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:99261.3-99297.6" + wire width 8 $1\dec31_dec_sub28_asmcode[7:0] + attribute \src "libresoc.v:99409.3-99445.6" + wire $1\dec31_dec_sub28_br[0:0] + attribute \src "libresoc.v:99890.3-99926.6" + wire width 3 $1\dec31_dec_sub28_cr_in[2:0] + attribute \src "libresoc.v:99927.3-99963.6" + wire width 3 $1\dec31_dec_sub28_cr_out[2:0] + attribute \src "libresoc.v:99224.3-99260.6" + wire width 2 $1\dec31_dec_sub28_cry_in[1:0] + attribute \src "libresoc.v:99372.3-99408.6" + wire $1\dec31_dec_sub28_cry_out[0:0] + attribute \src "libresoc.v:99705.3-99741.6" + wire width 5 $1\dec31_dec_sub28_form[4:0] + attribute \src "libresoc.v:99076.3-99112.6" + wire width 12 $1\dec31_dec_sub28_function_unit[11:0] + attribute \src "libresoc.v:99742.3-99778.6" + wire width 3 $1\dec31_dec_sub28_in1_sel[2:0] + attribute \src "libresoc.v:99779.3-99815.6" + wire width 4 $1\dec31_dec_sub28_in2_sel[3:0] + attribute \src "libresoc.v:99816.3-99852.6" + wire width 2 $1\dec31_dec_sub28_in3_sel[1:0] + attribute \src "libresoc.v:99483.3-99519.6" + wire width 7 $1\dec31_dec_sub28_internal_op[6:0] + attribute \src "libresoc.v:99298.3-99334.6" + wire $1\dec31_dec_sub28_inv_a[0:0] + attribute \src "libresoc.v:99335.3-99371.6" + wire $1\dec31_dec_sub28_inv_out[0:0] + attribute \src "libresoc.v:99557.3-99593.6" + wire $1\dec31_dec_sub28_is_32b[0:0] + attribute \src "libresoc.v:99113.3-99149.6" + wire width 4 $1\dec31_dec_sub28_ldst_len[3:0] + attribute \src "libresoc.v:99631.3-99667.6" + wire $1\dec31_dec_sub28_lk[0:0] + attribute \src "libresoc.v:99853.3-99889.6" + wire width 2 $1\dec31_dec_sub28_out_sel[1:0] + attribute \src "libresoc.v:99187.3-99223.6" + wire width 2 $1\dec31_dec_sub28_rc_sel[1:0] + attribute \src "libresoc.v:99520.3-99556.6" + wire $1\dec31_dec_sub28_rsrv[0:0] + attribute \src "libresoc.v:99668.3-99704.6" + wire $1\dec31_dec_sub28_sgl_pipe[0:0] + attribute \src "libresoc.v:99594.3-99630.6" + wire $1\dec31_dec_sub28_sgn[0:0] + attribute \src "libresoc.v:99446.3-99482.6" + wire $1\dec31_dec_sub28_sgn_ext[0:0] + attribute \src "libresoc.v:99150.3-99186.6" + wire width 2 $1\dec31_dec_sub28_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 output 4 \dec31_dec_sub28_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 18 \dec31_dec_sub28_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 9 \dec31_dec_sub28_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 10 \dec31_dec_sub28_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 14 \dec31_dec_sub28_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 17 \dec31_dec_sub28_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 output 3 \dec31_dec_sub28_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \dec31_dec_sub28_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \dec31_dec_sub28_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 6 \dec31_dec_sub28_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 7 \dec31_dec_sub28_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \dec31_dec_sub28_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 15 \dec31_dec_sub28_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 16 \dec31_dec_sub28_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 21 \dec31_dec_sub28_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 11 \dec31_dec_sub28_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 23 \dec31_dec_sub28_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 8 \dec31_dec_sub28_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 13 \dec31_dec_sub28_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 20 \dec31_dec_sub28_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 24 \dec31_dec_sub28_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 22 \dec31_dec_sub28_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 19 \dec31_dec_sub28_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 12 \dec31_dec_sub28_upd + attribute \src "libresoc.v:98819.7-98819.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 5 \opcode_switch + attribute \src "libresoc.v:98819.7-98819.20" + process $proc$libresoc.v:98819$4055 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:99076.3-99112.6" + process $proc$libresoc.v:99076$4031 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_function_unit[11:0] $1\dec31_dec_sub28_function_unit[11:0] + attribute \src "libresoc.v:99077.5-99077.29" + switch \initial + attribute \src "libresoc.v:99077.9-99077.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 + case + assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000000000 + end + sync always + update \dec31_dec_sub28_function_unit $0\dec31_dec_sub28_function_unit[11:0] + end + attribute \src "libresoc.v:99113.3-99149.6" + process $proc$libresoc.v:99113$4032 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_ldst_len[3:0] $1\dec31_dec_sub28_ldst_len[3:0] + attribute \src "libresoc.v:99114.5-99114.29" + switch \initial + attribute \src "libresoc.v:99114.9-99114.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 + case + assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub28_ldst_len $0\dec31_dec_sub28_ldst_len[3:0] + end + attribute \src "libresoc.v:99150.3-99186.6" + process $proc$libresoc.v:99150$4033 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_upd[1:0] $1\dec31_dec_sub28_upd[1:0] + attribute \src "libresoc.v:99151.5-99151.29" + switch \initial + attribute \src "libresoc.v:99151.9-99151.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub28_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub28_upd $0\dec31_dec_sub28_upd[1:0] + end + attribute \src "libresoc.v:99187.3-99223.6" + process $proc$libresoc.v:99187$4034 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_rc_sel[1:0] $1\dec31_dec_sub28_rc_sel[1:0] + attribute \src "libresoc.v:99188.5-99188.29" + switch \initial + attribute \src "libresoc.v:99188.9-99188.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_rc_sel[1:0] 2'10 + case + assign $1\dec31_dec_sub28_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub28_rc_sel $0\dec31_dec_sub28_rc_sel[1:0] + end + attribute \src "libresoc.v:99224.3-99260.6" + process $proc$libresoc.v:99224$4035 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_cry_in[1:0] $1\dec31_dec_sub28_cry_in[1:0] + attribute \src "libresoc.v:99225.5-99225.29" + switch \initial + attribute \src "libresoc.v:99225.9-99225.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 + case + assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub28_cry_in $0\dec31_dec_sub28_cry_in[1:0] + end + attribute \src "libresoc.v:99261.3-99297.6" + process $proc$libresoc.v:99261$4036 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_asmcode[7:0] $1\dec31_dec_sub28_asmcode[7:0] + attribute \src "libresoc.v:99262.5-99262.29" + switch \initial + attribute \src "libresoc.v:99262.9-99262.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_asmcode[7:0] 8'00001111 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_asmcode[7:0] 8'00010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_asmcode[7:0] 8'00011001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_asmcode[7:0] 8'00011011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_asmcode[7:0] 8'01000011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_asmcode[7:0] 8'10000011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_asmcode[7:0] 8'10000111 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_asmcode[7:0] 8'10001000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_asmcode[7:0] 8'10001001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_asmcode[7:0] 8'11010000 + case + assign $1\dec31_dec_sub28_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub28_asmcode $0\dec31_dec_sub28_asmcode[7:0] + end + attribute \src "libresoc.v:99298.3-99334.6" + process $proc$libresoc.v:99298$4037 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_inv_a[0:0] $1\dec31_dec_sub28_inv_a[0:0] + attribute \src "libresoc.v:99299.5-99299.29" + switch \initial + attribute \src "libresoc.v:99299.9-99299.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub28_inv_a $0\dec31_dec_sub28_inv_a[0:0] + end + attribute \src "libresoc.v:99335.3-99371.6" + process $proc$libresoc.v:99335$4038 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_inv_out[0:0] $1\dec31_dec_sub28_inv_out[0:0] + attribute \src "libresoc.v:99336.5-99336.29" + switch \initial + attribute \src "libresoc.v:99336.9-99336.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_inv_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_inv_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_inv_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub28_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub28_inv_out $0\dec31_dec_sub28_inv_out[0:0] + end + attribute \src "libresoc.v:99372.3-99408.6" + process $proc$libresoc.v:99372$4039 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_cry_out[0:0] $1\dec31_dec_sub28_cry_out[0:0] + attribute \src "libresoc.v:99373.5-99373.29" + switch \initial + attribute \src "libresoc.v:99373.9-99373.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 + case + assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub28_cry_out $0\dec31_dec_sub28_cry_out[0:0] + end + attribute \src "libresoc.v:99409.3-99445.6" + process $proc$libresoc.v:99409$4040 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_br[0:0] $1\dec31_dec_sub28_br[0:0] + attribute \src "libresoc.v:99410.5-99410.29" + switch \initial + attribute \src "libresoc.v:99410.9-99410.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_br[0:0] 1'0 + case + assign $1\dec31_dec_sub28_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub28_br $0\dec31_dec_sub28_br[0:0] + end + attribute \src "libresoc.v:99446.3-99482.6" + process $proc$libresoc.v:99446$4041 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_sgn_ext[0:0] $1\dec31_dec_sub28_sgn_ext[0:0] + attribute \src "libresoc.v:99447.5-99447.29" + switch \initial + attribute \src "libresoc.v:99447.9-99447.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub28_sgn_ext $0\dec31_dec_sub28_sgn_ext[0:0] + end + attribute \src "libresoc.v:99483.3-99519.6" + process $proc$libresoc.v:99483$4042 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_internal_op[6:0] $1\dec31_dec_sub28_internal_op[6:0] + attribute \src "libresoc.v:99484.5-99484.29" + switch \initial + attribute \src "libresoc.v:99484.9-99484.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_internal_op[6:0] 7'0000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_internal_op[6:0] 7'0000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_internal_op[6:0] 7'0001001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_internal_op[6:0] 7'0001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_internal_op[6:0] 7'1000011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_internal_op[6:0] 7'0000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_internal_op[6:0] 7'0110101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_internal_op[6:0] 7'0110101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_internal_op[6:0] 7'0110101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_internal_op[6:0] 7'1000011 + case + assign $1\dec31_dec_sub28_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub28_internal_op $0\dec31_dec_sub28_internal_op[6:0] + end + attribute \src "libresoc.v:99520.3-99556.6" + process $proc$libresoc.v:99520$4043 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_rsrv[0:0] $1\dec31_dec_sub28_rsrv[0:0] + attribute \src "libresoc.v:99521.5-99521.29" + switch \initial + attribute \src "libresoc.v:99521.9-99521.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub28_rsrv $0\dec31_dec_sub28_rsrv[0:0] + end + attribute \src "libresoc.v:99557.3-99593.6" + process $proc$libresoc.v:99557$4044 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_is_32b[0:0] $1\dec31_dec_sub28_is_32b[0:0] + attribute \src "libresoc.v:99558.5-99558.29" + switch \initial + attribute \src "libresoc.v:99558.9-99558.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 + case + assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub28_is_32b $0\dec31_dec_sub28_is_32b[0:0] + end + attribute \src "libresoc.v:99594.3-99630.6" + process $proc$libresoc.v:99594$4045 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_sgn[0:0] $1\dec31_dec_sub28_sgn[0:0] + attribute \src "libresoc.v:99595.5-99595.29" + switch \initial + attribute \src "libresoc.v:99595.9-99595.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_sgn[0:0] 1'0 + case + assign $1\dec31_dec_sub28_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub28_sgn $0\dec31_dec_sub28_sgn[0:0] + end + attribute \src "libresoc.v:99631.3-99667.6" + process $proc$libresoc.v:99631$4046 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_lk[0:0] $1\dec31_dec_sub28_lk[0:0] + attribute \src "libresoc.v:99632.5-99632.29" + switch \initial + attribute \src "libresoc.v:99632.9-99632.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub28_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub28_lk $0\dec31_dec_sub28_lk[0:0] + end + attribute \src "libresoc.v:99668.3-99704.6" + process $proc$libresoc.v:99668$4047 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_sgl_pipe[0:0] $1\dec31_dec_sub28_sgl_pipe[0:0] + attribute \src "libresoc.v:99669.5-99669.29" + switch \initial + attribute \src "libresoc.v:99669.9-99669.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 + case + assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub28_sgl_pipe $0\dec31_dec_sub28_sgl_pipe[0:0] + end + attribute \src "libresoc.v:99705.3-99741.6" + process $proc$libresoc.v:99705$4048 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_form[4:0] $1\dec31_dec_sub28_form[4:0] + attribute \src "libresoc.v:99706.5-99706.29" + switch \initial + attribute \src "libresoc.v:99706.9-99706.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_form[4:0] 5'01000 + case + assign $1\dec31_dec_sub28_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub28_form $0\dec31_dec_sub28_form[4:0] + end + attribute \src "libresoc.v:99742.3-99778.6" + process $proc$libresoc.v:99742$4049 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_in1_sel[2:0] $1\dec31_dec_sub28_in1_sel[2:0] + attribute \src "libresoc.v:99743.5-99743.29" + switch \initial + attribute \src "libresoc.v:99743.9-99743.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 + case + assign $1\dec31_dec_sub28_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub28_in1_sel $0\dec31_dec_sub28_in1_sel[2:0] + end + attribute \src "libresoc.v:99779.3-99815.6" + process $proc$libresoc.v:99779$4050 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_in2_sel[3:0] $1\dec31_dec_sub28_in2_sel[3:0] + attribute \src "libresoc.v:99780.5-99780.29" + switch \initial + attribute \src "libresoc.v:99780.9-99780.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 + case + assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub28_in2_sel $0\dec31_dec_sub28_in2_sel[3:0] + end + attribute \src "libresoc.v:99816.3-99852.6" + process $proc$libresoc.v:99816$4051 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_in3_sel[1:0] $1\dec31_dec_sub28_in3_sel[1:0] + attribute \src "libresoc.v:99817.5-99817.29" + switch \initial + attribute \src "libresoc.v:99817.9-99817.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub28_in3_sel $0\dec31_dec_sub28_in3_sel[1:0] + end + attribute \src "libresoc.v:99853.3-99889.6" + process $proc$libresoc.v:99853$4052 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_out_sel[1:0] $1\dec31_dec_sub28_out_sel[1:0] + attribute \src "libresoc.v:99854.5-99854.29" + switch \initial + attribute \src "libresoc.v:99854.9-99854.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 + case + assign $1\dec31_dec_sub28_out_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub28_out_sel $0\dec31_dec_sub28_out_sel[1:0] + end + attribute \src "libresoc.v:99890.3-99926.6" + process $proc$libresoc.v:99890$4053 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_cr_in[2:0] $1\dec31_dec_sub28_cr_in[2:0] + attribute \src "libresoc.v:99891.5-99891.29" + switch \initial + attribute \src "libresoc.v:99891.9-99891.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub28_cr_in $0\dec31_dec_sub28_cr_in[2:0] + end + attribute \src "libresoc.v:99927.3-99963.6" + process $proc$libresoc.v:99927$4054 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_cr_out[2:0] $1\dec31_dec_sub28_cr_out[2:0] + attribute \src "libresoc.v:99928.5-99928.29" + switch \initial + attribute \src "libresoc.v:99928.9-99928.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_cr_out[2:0] 3'001 + case + assign $1\dec31_dec_sub28_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub28_cr_out $0\dec31_dec_sub28_cr_out[2:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:99969.1-100540.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec31_dec_sub4" +attribute \generator "nMigen" +module \dec31_dec_sub4 + attribute \src "libresoc.v:100292.3-100304.6" + wire width 8 $0\dec31_dec_sub4_asmcode[7:0] + attribute \src "libresoc.v:100344.3-100356.6" + wire $0\dec31_dec_sub4_br[0:0] + attribute \src "libresoc.v:100513.3-100525.6" + wire width 3 $0\dec31_dec_sub4_cr_in[2:0] + attribute \src "libresoc.v:100526.3-100538.6" + wire width 3 $0\dec31_dec_sub4_cr_out[2:0] + attribute \src "libresoc.v:100279.3-100291.6" + wire width 2 $0\dec31_dec_sub4_cry_in[1:0] + attribute \src "libresoc.v:100331.3-100343.6" + wire $0\dec31_dec_sub4_cry_out[0:0] + attribute \src "libresoc.v:100448.3-100460.6" + wire width 5 $0\dec31_dec_sub4_form[4:0] + attribute \src "libresoc.v:100227.3-100239.6" + wire width 12 $0\dec31_dec_sub4_function_unit[11:0] + attribute \src "libresoc.v:100461.3-100473.6" + wire width 3 $0\dec31_dec_sub4_in1_sel[2:0] + attribute \src "libresoc.v:100474.3-100486.6" + wire width 4 $0\dec31_dec_sub4_in2_sel[3:0] + attribute \src "libresoc.v:100487.3-100499.6" + wire width 2 $0\dec31_dec_sub4_in3_sel[1:0] + attribute \src "libresoc.v:100370.3-100382.6" + wire width 7 $0\dec31_dec_sub4_internal_op[6:0] + attribute \src "libresoc.v:100305.3-100317.6" + wire $0\dec31_dec_sub4_inv_a[0:0] + attribute \src "libresoc.v:100318.3-100330.6" + wire $0\dec31_dec_sub4_inv_out[0:0] + attribute \src "libresoc.v:100396.3-100408.6" + wire $0\dec31_dec_sub4_is_32b[0:0] + attribute \src "libresoc.v:100240.3-100252.6" + wire width 4 $0\dec31_dec_sub4_ldst_len[3:0] + attribute \src "libresoc.v:100422.3-100434.6" + wire $0\dec31_dec_sub4_lk[0:0] + attribute \src "libresoc.v:100500.3-100512.6" + wire width 2 $0\dec31_dec_sub4_out_sel[1:0] + attribute \src "libresoc.v:100266.3-100278.6" + wire width 2 $0\dec31_dec_sub4_rc_sel[1:0] + attribute \src "libresoc.v:100383.3-100395.6" + wire $0\dec31_dec_sub4_rsrv[0:0] + attribute \src "libresoc.v:100435.3-100447.6" + wire $0\dec31_dec_sub4_sgl_pipe[0:0] + attribute \src "libresoc.v:100409.3-100421.6" + wire $0\dec31_dec_sub4_sgn[0:0] + attribute \src "libresoc.v:100357.3-100369.6" + wire $0\dec31_dec_sub4_sgn_ext[0:0] + attribute \src "libresoc.v:100253.3-100265.6" + wire width 2 $0\dec31_dec_sub4_upd[1:0] + attribute \src "libresoc.v:99970.7-99970.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:100292.3-100304.6" + wire width 8 $1\dec31_dec_sub4_asmcode[7:0] + attribute \src "libresoc.v:100344.3-100356.6" + wire $1\dec31_dec_sub4_br[0:0] + attribute \src "libresoc.v:100513.3-100525.6" + wire width 3 $1\dec31_dec_sub4_cr_in[2:0] + attribute \src "libresoc.v:100526.3-100538.6" + wire width 3 $1\dec31_dec_sub4_cr_out[2:0] + attribute \src "libresoc.v:100279.3-100291.6" + wire width 2 $1\dec31_dec_sub4_cry_in[1:0] + attribute \src "libresoc.v:100331.3-100343.6" + wire $1\dec31_dec_sub4_cry_out[0:0] + attribute \src "libresoc.v:100448.3-100460.6" + wire width 5 $1\dec31_dec_sub4_form[4:0] + attribute \src "libresoc.v:100227.3-100239.6" + wire width 12 $1\dec31_dec_sub4_function_unit[11:0] + attribute \src "libresoc.v:100461.3-100473.6" + wire width 3 $1\dec31_dec_sub4_in1_sel[2:0] + attribute \src "libresoc.v:100474.3-100486.6" + wire width 4 $1\dec31_dec_sub4_in2_sel[3:0] + attribute \src "libresoc.v:100487.3-100499.6" + wire width 2 $1\dec31_dec_sub4_in3_sel[1:0] + attribute \src "libresoc.v:100370.3-100382.6" + wire width 7 $1\dec31_dec_sub4_internal_op[6:0] + attribute \src "libresoc.v:100305.3-100317.6" + wire $1\dec31_dec_sub4_inv_a[0:0] + attribute \src "libresoc.v:100318.3-100330.6" + wire $1\dec31_dec_sub4_inv_out[0:0] + attribute \src "libresoc.v:100396.3-100408.6" + wire $1\dec31_dec_sub4_is_32b[0:0] + attribute \src "libresoc.v:100240.3-100252.6" + wire width 4 $1\dec31_dec_sub4_ldst_len[3:0] + attribute \src "libresoc.v:100422.3-100434.6" + wire $1\dec31_dec_sub4_lk[0:0] + attribute \src "libresoc.v:100500.3-100512.6" + wire width 2 $1\dec31_dec_sub4_out_sel[1:0] + attribute \src "libresoc.v:100266.3-100278.6" + wire width 2 $1\dec31_dec_sub4_rc_sel[1:0] + attribute \src "libresoc.v:100383.3-100395.6" + wire $1\dec31_dec_sub4_rsrv[0:0] + attribute \src "libresoc.v:100435.3-100447.6" + wire $1\dec31_dec_sub4_sgl_pipe[0:0] + attribute \src "libresoc.v:100409.3-100421.6" + wire $1\dec31_dec_sub4_sgn[0:0] + attribute \src "libresoc.v:100357.3-100369.6" + wire $1\dec31_dec_sub4_sgn_ext[0:0] + attribute \src "libresoc.v:100253.3-100265.6" + wire width 2 $1\dec31_dec_sub4_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 output 4 \dec31_dec_sub4_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 18 \dec31_dec_sub4_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 9 \dec31_dec_sub4_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 10 \dec31_dec_sub4_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 14 \dec31_dec_sub4_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 17 \dec31_dec_sub4_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 output 3 \dec31_dec_sub4_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \dec31_dec_sub4_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \dec31_dec_sub4_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 6 \dec31_dec_sub4_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 7 \dec31_dec_sub4_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \dec31_dec_sub4_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 15 \dec31_dec_sub4_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 16 \dec31_dec_sub4_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 21 \dec31_dec_sub4_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 11 \dec31_dec_sub4_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 23 \dec31_dec_sub4_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 8 \dec31_dec_sub4_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 13 \dec31_dec_sub4_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 20 \dec31_dec_sub4_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 24 \dec31_dec_sub4_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 22 \dec31_dec_sub4_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 19 \dec31_dec_sub4_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 12 \dec31_dec_sub4_upd + attribute \src "libresoc.v:99970.7-99970.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 5 \opcode_switch + attribute \src "libresoc.v:100227.3-100239.6" + process $proc$libresoc.v:100227$4056 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_function_unit[11:0] $1\dec31_dec_sub4_function_unit[11:0] + attribute \src "libresoc.v:100228.5-100228.29" + switch \initial + attribute \src "libresoc.v:100228.9-100228.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_function_unit[11:0] 12'000010000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_function_unit[11:0] 12'000010000000 + case + assign $1\dec31_dec_sub4_function_unit[11:0] 12'000000000000 + end + sync always + update \dec31_dec_sub4_function_unit $0\dec31_dec_sub4_function_unit[11:0] + end + attribute \src "libresoc.v:100240.3-100252.6" + process $proc$libresoc.v:100240$4057 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_ldst_len[3:0] $1\dec31_dec_sub4_ldst_len[3:0] + attribute \src "libresoc.v:100241.5-100241.29" + switch \initial + attribute \src "libresoc.v:100241.9-100241.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_ldst_len[3:0] 4'0000 + case + assign $1\dec31_dec_sub4_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub4_ldst_len $0\dec31_dec_sub4_ldst_len[3:0] + end + attribute \src "libresoc.v:100253.3-100265.6" + process $proc$libresoc.v:100253$4058 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_upd[1:0] $1\dec31_dec_sub4_upd[1:0] + attribute \src "libresoc.v:100254.5-100254.29" + switch \initial + attribute \src "libresoc.v:100254.9-100254.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub4_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub4_upd $0\dec31_dec_sub4_upd[1:0] + end + attribute \src "libresoc.v:100266.3-100278.6" + process $proc$libresoc.v:100266$4059 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_rc_sel[1:0] $1\dec31_dec_sub4_rc_sel[1:0] + attribute \src "libresoc.v:100267.5-100267.29" + switch \initial + attribute \src "libresoc.v:100267.9-100267.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_rc_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub4_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub4_rc_sel $0\dec31_dec_sub4_rc_sel[1:0] + end + attribute \src "libresoc.v:100279.3-100291.6" + process $proc$libresoc.v:100279$4060 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_cry_in[1:0] $1\dec31_dec_sub4_cry_in[1:0] + attribute \src "libresoc.v:100280.5-100280.29" + switch \initial + attribute \src "libresoc.v:100280.9-100280.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_cry_in[1:0] 2'00 + case + assign $1\dec31_dec_sub4_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub4_cry_in $0\dec31_dec_sub4_cry_in[1:0] + end + attribute \src "libresoc.v:100292.3-100304.6" + process $proc$libresoc.v:100292$4061 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_asmcode[7:0] $1\dec31_dec_sub4_asmcode[7:0] + attribute \src "libresoc.v:100293.5-100293.29" + switch \initial + attribute \src "libresoc.v:100293.9-100293.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_asmcode[7:0] 8'11001010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_asmcode[7:0] 8'11001110 + case + assign $1\dec31_dec_sub4_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub4_asmcode $0\dec31_dec_sub4_asmcode[7:0] + end + attribute \src "libresoc.v:100305.3-100317.6" + process $proc$libresoc.v:100305$4062 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_inv_a[0:0] $1\dec31_dec_sub4_inv_a[0:0] + attribute \src "libresoc.v:100306.5-100306.29" + switch \initial + attribute \src "libresoc.v:100306.9-100306.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub4_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub4_inv_a $0\dec31_dec_sub4_inv_a[0:0] + end + attribute \src "libresoc.v:100318.3-100330.6" + process $proc$libresoc.v:100318$4063 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_inv_out[0:0] $1\dec31_dec_sub4_inv_out[0:0] + attribute \src "libresoc.v:100319.5-100319.29" + switch \initial + attribute \src "libresoc.v:100319.9-100319.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub4_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub4_inv_out $0\dec31_dec_sub4_inv_out[0:0] + end + attribute \src "libresoc.v:100331.3-100343.6" + process $proc$libresoc.v:100331$4064 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_cry_out[0:0] $1\dec31_dec_sub4_cry_out[0:0] + attribute \src "libresoc.v:100332.5-100332.29" + switch \initial + attribute \src "libresoc.v:100332.9-100332.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_cry_out[0:0] 1'0 + case + assign $1\dec31_dec_sub4_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub4_cry_out $0\dec31_dec_sub4_cry_out[0:0] + end + attribute \src "libresoc.v:100344.3-100356.6" + process $proc$libresoc.v:100344$4065 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_br[0:0] $1\dec31_dec_sub4_br[0:0] + attribute \src "libresoc.v:100345.5-100345.29" + switch \initial + attribute \src "libresoc.v:100345.9-100345.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_br[0:0] 1'0 + case + assign $1\dec31_dec_sub4_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub4_br $0\dec31_dec_sub4_br[0:0] + end + attribute \src "libresoc.v:100357.3-100369.6" + process $proc$libresoc.v:100357$4066 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_sgn_ext[0:0] $1\dec31_dec_sub4_sgn_ext[0:0] + attribute \src "libresoc.v:100358.5-100358.29" + switch \initial + attribute \src "libresoc.v:100358.9-100358.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub4_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub4_sgn_ext $0\dec31_dec_sub4_sgn_ext[0:0] + end + attribute \src "libresoc.v:100370.3-100382.6" + process $proc$libresoc.v:100370$4067 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_internal_op[6:0] $1\dec31_dec_sub4_internal_op[6:0] + attribute \src "libresoc.v:100371.5-100371.29" + switch \initial + attribute \src "libresoc.v:100371.9-100371.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_internal_op[6:0] 7'0111111 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_internal_op[6:0] 7'0111111 + case + assign $1\dec31_dec_sub4_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub4_internal_op $0\dec31_dec_sub4_internal_op[6:0] + end + attribute \src "libresoc.v:100383.3-100395.6" + process $proc$libresoc.v:100383$4068 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_rsrv[0:0] $1\dec31_dec_sub4_rsrv[0:0] + attribute \src "libresoc.v:100384.5-100384.29" + switch \initial + attribute \src "libresoc.v:100384.9-100384.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub4_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub4_rsrv $0\dec31_dec_sub4_rsrv[0:0] + end + attribute \src "libresoc.v:100396.3-100408.6" + process $proc$libresoc.v:100396$4069 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_is_32b[0:0] $1\dec31_dec_sub4_is_32b[0:0] + attribute \src "libresoc.v:100397.5-100397.29" + switch \initial + attribute \src "libresoc.v:100397.9-100397.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_is_32b[0:0] 1'1 + case + assign $1\dec31_dec_sub4_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub4_is_32b $0\dec31_dec_sub4_is_32b[0:0] + end + attribute \src "libresoc.v:100409.3-100421.6" + process $proc$libresoc.v:100409$4070 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_sgn[0:0] $1\dec31_dec_sub4_sgn[0:0] + attribute \src "libresoc.v:100410.5-100410.29" + switch \initial + attribute \src "libresoc.v:100410.9-100410.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_sgn[0:0] 1'0 + case + assign $1\dec31_dec_sub4_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub4_sgn $0\dec31_dec_sub4_sgn[0:0] + end + attribute \src "libresoc.v:100422.3-100434.6" + process $proc$libresoc.v:100422$4071 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_lk[0:0] $1\dec31_dec_sub4_lk[0:0] + attribute \src "libresoc.v:100423.5-100423.29" + switch \initial + attribute \src "libresoc.v:100423.9-100423.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub4_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub4_lk $0\dec31_dec_sub4_lk[0:0] + end + attribute \src "libresoc.v:100435.3-100447.6" + process $proc$libresoc.v:100435$4072 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_sgl_pipe[0:0] $1\dec31_dec_sub4_sgl_pipe[0:0] + attribute \src "libresoc.v:100436.5-100436.29" + switch \initial + attribute \src "libresoc.v:100436.9-100436.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_sgl_pipe[0:0] 1'1 + case + assign $1\dec31_dec_sub4_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub4_sgl_pipe $0\dec31_dec_sub4_sgl_pipe[0:0] + end + attribute \src "libresoc.v:100448.3-100460.6" + process $proc$libresoc.v:100448$4073 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_form[4:0] $1\dec31_dec_sub4_form[4:0] + attribute \src "libresoc.v:100449.5-100449.29" + switch \initial + attribute \src "libresoc.v:100449.9-100449.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_form[4:0] 5'01000 + case + assign $1\dec31_dec_sub4_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub4_form $0\dec31_dec_sub4_form[4:0] + end + attribute \src "libresoc.v:100461.3-100473.6" + process $proc$libresoc.v:100461$4074 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_in1_sel[2:0] $1\dec31_dec_sub4_in1_sel[2:0] + attribute \src "libresoc.v:100462.5-100462.29" + switch \initial + attribute \src "libresoc.v:100462.9-100462.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_in1_sel[2:0] 3'001 + case + assign $1\dec31_dec_sub4_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub4_in1_sel $0\dec31_dec_sub4_in1_sel[2:0] + end + attribute \src "libresoc.v:100474.3-100486.6" + process $proc$libresoc.v:100474$4075 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_in2_sel[3:0] $1\dec31_dec_sub4_in2_sel[3:0] + attribute \src "libresoc.v:100475.5-100475.29" + switch \initial + attribute \src "libresoc.v:100475.9-100475.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_in2_sel[3:0] 4'0001 + case + assign $1\dec31_dec_sub4_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub4_in2_sel $0\dec31_dec_sub4_in2_sel[3:0] + end + attribute \src "libresoc.v:100487.3-100499.6" + process $proc$libresoc.v:100487$4076 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_in3_sel[1:0] $1\dec31_dec_sub4_in3_sel[1:0] + attribute \src "libresoc.v:100488.5-100488.29" + switch \initial + attribute \src "libresoc.v:100488.9-100488.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_in3_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub4_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub4_in3_sel $0\dec31_dec_sub4_in3_sel[1:0] + end + attribute \src "libresoc.v:100500.3-100512.6" + process $proc$libresoc.v:100500$4077 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_out_sel[1:0] $1\dec31_dec_sub4_out_sel[1:0] + attribute \src "libresoc.v:100501.5-100501.29" + switch \initial + attribute \src "libresoc.v:100501.9-100501.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_out_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub4_out_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub4_out_sel $0\dec31_dec_sub4_out_sel[1:0] + end + attribute \src "libresoc.v:100513.3-100525.6" + process $proc$libresoc.v:100513$4078 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_cr_in[2:0] $1\dec31_dec_sub4_cr_in[2:0] + attribute \src "libresoc.v:100514.5-100514.29" + switch \initial + attribute \src "libresoc.v:100514.9-100514.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub4_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub4_cr_in $0\dec31_dec_sub4_cr_in[2:0] + end + attribute \src "libresoc.v:100526.3-100538.6" + process $proc$libresoc.v:100526$4079 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_cr_out[2:0] $1\dec31_dec_sub4_cr_out[2:0] + attribute \src "libresoc.v:100527.5-100527.29" + switch \initial + attribute \src "libresoc.v:100527.9-100527.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_cr_out[2:0] 3'000 + case + assign $1\dec31_dec_sub4_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub4_cr_out $0\dec31_dec_sub4_cr_out[2:0] + end + attribute \src "libresoc.v:99970.7-99970.20" + process $proc$libresoc.v:99970$4080 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:100544.1-101835.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec31_dec_sub8" +attribute \generator "nMigen" +module \dec31_dec_sub8 + attribute \src "libresoc.v:101017.3-101059.6" + wire width 8 $0\dec31_dec_sub8_asmcode[7:0] + attribute \src "libresoc.v:101189.3-101231.6" + wire $0\dec31_dec_sub8_br[0:0] + attribute \src "libresoc.v:101748.3-101790.6" + wire width 3 $0\dec31_dec_sub8_cr_in[2:0] + attribute \src "libresoc.v:101791.3-101833.6" + wire width 3 $0\dec31_dec_sub8_cr_out[2:0] + attribute \src "libresoc.v:100974.3-101016.6" + wire width 2 $0\dec31_dec_sub8_cry_in[1:0] + attribute \src "libresoc.v:101146.3-101188.6" + wire $0\dec31_dec_sub8_cry_out[0:0] + attribute \src "libresoc.v:101533.3-101575.6" + wire width 5 $0\dec31_dec_sub8_form[4:0] + attribute \src "libresoc.v:100802.3-100844.6" + wire width 12 $0\dec31_dec_sub8_function_unit[11:0] + attribute \src "libresoc.v:101576.3-101618.6" + wire width 3 $0\dec31_dec_sub8_in1_sel[2:0] + attribute \src "libresoc.v:101619.3-101661.6" + wire width 4 $0\dec31_dec_sub8_in2_sel[3:0] + attribute \src "libresoc.v:101662.3-101704.6" + wire width 2 $0\dec31_dec_sub8_in3_sel[1:0] + attribute \src "libresoc.v:101275.3-101317.6" + wire width 7 $0\dec31_dec_sub8_internal_op[6:0] + attribute \src "libresoc.v:101060.3-101102.6" + wire $0\dec31_dec_sub8_inv_a[0:0] + attribute \src "libresoc.v:101103.3-101145.6" + wire $0\dec31_dec_sub8_inv_out[0:0] + attribute \src "libresoc.v:101361.3-101403.6" + wire $0\dec31_dec_sub8_is_32b[0:0] + attribute \src "libresoc.v:100845.3-100887.6" + wire width 4 $0\dec31_dec_sub8_ldst_len[3:0] + attribute \src "libresoc.v:101447.3-101489.6" + wire $0\dec31_dec_sub8_lk[0:0] + attribute \src "libresoc.v:101705.3-101747.6" + wire width 2 $0\dec31_dec_sub8_out_sel[1:0] + attribute \src "libresoc.v:100931.3-100973.6" + wire width 2 $0\dec31_dec_sub8_rc_sel[1:0] + attribute \src "libresoc.v:101318.3-101360.6" + wire $0\dec31_dec_sub8_rsrv[0:0] + attribute \src "libresoc.v:101490.3-101532.6" + wire $0\dec31_dec_sub8_sgl_pipe[0:0] + attribute \src "libresoc.v:101404.3-101446.6" + wire $0\dec31_dec_sub8_sgn[0:0] + attribute \src "libresoc.v:101232.3-101274.6" + wire $0\dec31_dec_sub8_sgn_ext[0:0] + attribute \src "libresoc.v:100888.3-100930.6" + wire width 2 $0\dec31_dec_sub8_upd[1:0] + attribute \src "libresoc.v:100545.7-100545.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:101017.3-101059.6" + wire width 8 $1\dec31_dec_sub8_asmcode[7:0] + attribute \src "libresoc.v:101189.3-101231.6" + wire $1\dec31_dec_sub8_br[0:0] + attribute \src "libresoc.v:101748.3-101790.6" + wire width 3 $1\dec31_dec_sub8_cr_in[2:0] + attribute \src "libresoc.v:101791.3-101833.6" + wire width 3 $1\dec31_dec_sub8_cr_out[2:0] + attribute \src "libresoc.v:100974.3-101016.6" + wire width 2 $1\dec31_dec_sub8_cry_in[1:0] + attribute \src "libresoc.v:101146.3-101188.6" + wire $1\dec31_dec_sub8_cry_out[0:0] + attribute \src "libresoc.v:101533.3-101575.6" + wire width 5 $1\dec31_dec_sub8_form[4:0] + attribute \src "libresoc.v:100802.3-100844.6" + wire width 12 $1\dec31_dec_sub8_function_unit[11:0] + attribute \src "libresoc.v:101576.3-101618.6" + wire width 3 $1\dec31_dec_sub8_in1_sel[2:0] + attribute \src "libresoc.v:101619.3-101661.6" + wire width 4 $1\dec31_dec_sub8_in2_sel[3:0] + attribute \src "libresoc.v:101662.3-101704.6" + wire width 2 $1\dec31_dec_sub8_in3_sel[1:0] + attribute \src "libresoc.v:101275.3-101317.6" + wire width 7 $1\dec31_dec_sub8_internal_op[6:0] + attribute \src "libresoc.v:101060.3-101102.6" + wire $1\dec31_dec_sub8_inv_a[0:0] + attribute \src "libresoc.v:101103.3-101145.6" + wire $1\dec31_dec_sub8_inv_out[0:0] + attribute \src "libresoc.v:101361.3-101403.6" + wire $1\dec31_dec_sub8_is_32b[0:0] + attribute \src "libresoc.v:100845.3-100887.6" + wire width 4 $1\dec31_dec_sub8_ldst_len[3:0] + attribute \src "libresoc.v:101447.3-101489.6" + wire $1\dec31_dec_sub8_lk[0:0] + attribute \src "libresoc.v:101705.3-101747.6" + wire width 2 $1\dec31_dec_sub8_out_sel[1:0] + attribute \src "libresoc.v:100931.3-100973.6" + wire width 2 $1\dec31_dec_sub8_rc_sel[1:0] + attribute \src "libresoc.v:101318.3-101360.6" + wire $1\dec31_dec_sub8_rsrv[0:0] + attribute \src "libresoc.v:101490.3-101532.6" + wire $1\dec31_dec_sub8_sgl_pipe[0:0] + attribute \src "libresoc.v:101404.3-101446.6" + wire $1\dec31_dec_sub8_sgn[0:0] + attribute \src "libresoc.v:101232.3-101274.6" + wire $1\dec31_dec_sub8_sgn_ext[0:0] + attribute \src "libresoc.v:100888.3-100930.6" + wire width 2 $1\dec31_dec_sub8_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 output 4 \dec31_dec_sub8_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 18 \dec31_dec_sub8_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 9 \dec31_dec_sub8_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 10 \dec31_dec_sub8_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 14 \dec31_dec_sub8_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 17 \dec31_dec_sub8_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 output 3 \dec31_dec_sub8_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \dec31_dec_sub8_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \dec31_dec_sub8_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 6 \dec31_dec_sub8_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 7 \dec31_dec_sub8_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \dec31_dec_sub8_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 15 \dec31_dec_sub8_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 16 \dec31_dec_sub8_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 21 \dec31_dec_sub8_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 11 \dec31_dec_sub8_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 23 \dec31_dec_sub8_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 8 \dec31_dec_sub8_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 13 \dec31_dec_sub8_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 20 \dec31_dec_sub8_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 24 \dec31_dec_sub8_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 22 \dec31_dec_sub8_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 19 \dec31_dec_sub8_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 12 \dec31_dec_sub8_upd + attribute \src "libresoc.v:100545.7-100545.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 5 \opcode_switch + attribute \src "libresoc.v:100545.7-100545.20" + process $proc$libresoc.v:100545$4105 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:100802.3-100844.6" + process $proc$libresoc.v:100802$4081 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_function_unit[11:0] $1\dec31_dec_sub8_function_unit[11:0] + attribute \src "libresoc.v:100803.5-100803.29" + switch \initial + attribute \src "libresoc.v:100803.9-100803.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 + case + assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000000 + end + sync always + update \dec31_dec_sub8_function_unit $0\dec31_dec_sub8_function_unit[11:0] + end + attribute \src "libresoc.v:100845.3-100887.6" + process $proc$libresoc.v:100845$4082 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_ldst_len[3:0] $1\dec31_dec_sub8_ldst_len[3:0] + attribute \src "libresoc.v:100846.5-100846.29" + switch \initial + attribute \src "libresoc.v:100846.9-100846.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 + case + assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub8_ldst_len $0\dec31_dec_sub8_ldst_len[3:0] + end + attribute \src "libresoc.v:100888.3-100930.6" + process $proc$libresoc.v:100888$4083 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_upd[1:0] $1\dec31_dec_sub8_upd[1:0] + attribute \src "libresoc.v:100889.5-100889.29" + switch \initial + attribute \src "libresoc.v:100889.9-100889.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub8_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub8_upd $0\dec31_dec_sub8_upd[1:0] + end + attribute \src "libresoc.v:100931.3-100973.6" + process $proc$libresoc.v:100931$4084 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_rc_sel[1:0] $1\dec31_dec_sub8_rc_sel[1:0] + attribute \src "libresoc.v:100932.5-100932.29" + switch \initial + attribute \src "libresoc.v:100932.9-100932.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 + case + assign $1\dec31_dec_sub8_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub8_rc_sel $0\dec31_dec_sub8_rc_sel[1:0] + end + attribute \src "libresoc.v:100974.3-101016.6" + process $proc$libresoc.v:100974$4085 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_cry_in[1:0] $1\dec31_dec_sub8_cry_in[1:0] + attribute \src "libresoc.v:100975.5-100975.29" + switch \initial + attribute \src "libresoc.v:100975.9-100975.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_cry_in[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_cry_in[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_cry_in[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_cry_in[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_cry_in[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_cry_in[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_cry_in[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_cry_in[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_cry_in[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_cry_in[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_cry_in[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_cry_in[1:0] 2'10 + case + assign $1\dec31_dec_sub8_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub8_cry_in $0\dec31_dec_sub8_cry_in[1:0] + end + attribute \src "libresoc.v:101017.3-101059.6" + process $proc$libresoc.v:101017$4086 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_asmcode[7:0] $1\dec31_dec_sub8_asmcode[7:0] + attribute \src "libresoc.v:101018.5-101018.29" + switch \initial + attribute \src "libresoc.v:101018.9-101018.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_asmcode[7:0] 8'10000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_asmcode[7:0] 8'10000101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_asmcode[7:0] 8'10111110 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_asmcode[7:0] 8'11000110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_asmcode[7:0] 8'10111111 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_asmcode[7:0] 8'11000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_asmcode[7:0] 8'11000001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_asmcode[7:0] 8'11000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_asmcode[7:0] 8'11000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_asmcode[7:0] 8'11000101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_asmcode[7:0] 8'11000111 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_asmcode[7:0] 8'11001000 + case + assign $1\dec31_dec_sub8_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub8_asmcode $0\dec31_dec_sub8_asmcode[7:0] + end + attribute \src "libresoc.v:101060.3-101102.6" + process $proc$libresoc.v:101060$4087 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_inv_a[0:0] $1\dec31_dec_sub8_inv_a[0:0] + attribute \src "libresoc.v:101061.5-101061.29" + switch \initial + attribute \src "libresoc.v:101061.9-101061.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 + case + assign $1\dec31_dec_sub8_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub8_inv_a $0\dec31_dec_sub8_inv_a[0:0] + end + attribute \src "libresoc.v:101103.3-101145.6" + process $proc$libresoc.v:101103$4088 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_inv_out[0:0] $1\dec31_dec_sub8_inv_out[0:0] + attribute \src "libresoc.v:101104.5-101104.29" + switch \initial + attribute \src "libresoc.v:101104.9-101104.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub8_inv_out $0\dec31_dec_sub8_inv_out[0:0] + end + attribute \src "libresoc.v:101146.3-101188.6" + process $proc$libresoc.v:101146$4089 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_cry_out[0:0] $1\dec31_dec_sub8_cry_out[0:0] + attribute \src "libresoc.v:101147.5-101147.29" + switch \initial + attribute \src "libresoc.v:101147.9-101147.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_cry_out[0:0] 1'1 + case + assign $1\dec31_dec_sub8_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub8_cry_out $0\dec31_dec_sub8_cry_out[0:0] + end + attribute \src "libresoc.v:101189.3-101231.6" + process $proc$libresoc.v:101189$4090 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_br[0:0] $1\dec31_dec_sub8_br[0:0] + attribute \src "libresoc.v:101190.5-101190.29" + switch \initial + attribute \src "libresoc.v:101190.9-101190.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_br[0:0] 1'0 + case + assign $1\dec31_dec_sub8_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub8_br $0\dec31_dec_sub8_br[0:0] + end + attribute \src "libresoc.v:101232.3-101274.6" + process $proc$libresoc.v:101232$4091 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_sgn_ext[0:0] $1\dec31_dec_sub8_sgn_ext[0:0] + attribute \src "libresoc.v:101233.5-101233.29" + switch \initial + attribute \src "libresoc.v:101233.9-101233.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub8_sgn_ext $0\dec31_dec_sub8_sgn_ext[0:0] + end + attribute \src "libresoc.v:101275.3-101317.6" + process $proc$libresoc.v:101275$4092 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_internal_op[6:0] $1\dec31_dec_sub8_internal_op[6:0] + attribute \src "libresoc.v:101276.5-101276.29" + switch \initial + attribute \src "libresoc.v:101276.9-101276.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + case + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub8_internal_op $0\dec31_dec_sub8_internal_op[6:0] + end + attribute \src "libresoc.v:101318.3-101360.6" + process $proc$libresoc.v:101318$4093 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_rsrv[0:0] $1\dec31_dec_sub8_rsrv[0:0] + attribute \src "libresoc.v:101319.5-101319.29" + switch \initial + attribute \src "libresoc.v:101319.9-101319.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub8_rsrv $0\dec31_dec_sub8_rsrv[0:0] + end + attribute \src "libresoc.v:101361.3-101403.6" + process $proc$libresoc.v:101361$4094 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_is_32b[0:0] $1\dec31_dec_sub8_is_32b[0:0] + attribute \src "libresoc.v:101362.5-101362.29" + switch \initial + attribute \src "libresoc.v:101362.9-101362.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + case + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub8_is_32b $0\dec31_dec_sub8_is_32b[0:0] + end + attribute \src "libresoc.v:101404.3-101446.6" + process $proc$libresoc.v:101404$4095 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_sgn[0:0] $1\dec31_dec_sub8_sgn[0:0] + attribute \src "libresoc.v:101405.5-101405.29" + switch \initial + attribute \src "libresoc.v:101405.9-101405.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_sgn[0:0] 1'0 + case + assign $1\dec31_dec_sub8_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub8_sgn $0\dec31_dec_sub8_sgn[0:0] + end + attribute \src "libresoc.v:101447.3-101489.6" + process $proc$libresoc.v:101447$4096 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_lk[0:0] $1\dec31_dec_sub8_lk[0:0] + attribute \src "libresoc.v:101448.5-101448.29" + switch \initial + attribute \src "libresoc.v:101448.9-101448.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub8_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub8_lk $0\dec31_dec_sub8_lk[0:0] + end + attribute \src "libresoc.v:101490.3-101532.6" + process $proc$libresoc.v:101490$4097 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_sgl_pipe[0:0] $1\dec31_dec_sub8_sgl_pipe[0:0] + attribute \src "libresoc.v:101491.5-101491.29" + switch \initial + attribute \src "libresoc.v:101491.9-101491.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 + case + assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub8_sgl_pipe $0\dec31_dec_sub8_sgl_pipe[0:0] + end + attribute \src "libresoc.v:101533.3-101575.6" + process $proc$libresoc.v:101533$4098 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_form[4:0] $1\dec31_dec_sub8_form[4:0] + attribute \src "libresoc.v:101534.5-101534.29" + switch \initial + attribute \src "libresoc.v:101534.9-101534.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_form[4:0] 5'10001 + case + assign $1\dec31_dec_sub8_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub8_form $0\dec31_dec_sub8_form[4:0] + end + attribute \src "libresoc.v:101576.3-101618.6" + process $proc$libresoc.v:101576$4099 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_in1_sel[2:0] $1\dec31_dec_sub8_in1_sel[2:0] + attribute \src "libresoc.v:101577.5-101577.29" + switch \initial + attribute \src "libresoc.v:101577.9-101577.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 + case + assign $1\dec31_dec_sub8_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub8_in1_sel $0\dec31_dec_sub8_in1_sel[2:0] + end + attribute \src "libresoc.v:101619.3-101661.6" + process $proc$libresoc.v:101619$4100 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_in2_sel[3:0] $1\dec31_dec_sub8_in2_sel[3:0] + attribute \src "libresoc.v:101620.5-101620.29" + switch \initial + attribute \src "libresoc.v:101620.9-101620.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_in2_sel[3:0] 4'1001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_in2_sel[3:0] 4'1001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0000 + case + assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub8_in2_sel $0\dec31_dec_sub8_in2_sel[3:0] + end + attribute \src "libresoc.v:101662.3-101704.6" + process $proc$libresoc.v:101662$4101 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_in3_sel[1:0] $1\dec31_dec_sub8_in3_sel[1:0] + attribute \src "libresoc.v:101663.5-101663.29" + switch \initial + attribute \src "libresoc.v:101663.9-101663.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub8_in3_sel $0\dec31_dec_sub8_in3_sel[1:0] + end + attribute \src "libresoc.v:101705.3-101747.6" + process $proc$libresoc.v:101705$4102 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_out_sel[1:0] $1\dec31_dec_sub8_out_sel[1:0] + attribute \src "libresoc.v:101706.5-101706.29" + switch \initial + attribute \src "libresoc.v:101706.9-101706.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 + case + assign $1\dec31_dec_sub8_out_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub8_out_sel $0\dec31_dec_sub8_out_sel[1:0] + end + attribute \src "libresoc.v:101748.3-101790.6" + process $proc$libresoc.v:101748$4103 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_cr_in[2:0] $1\dec31_dec_sub8_cr_in[2:0] + attribute \src "libresoc.v:101749.5-101749.29" + switch \initial + attribute \src "libresoc.v:101749.9-101749.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub8_cr_in $0\dec31_dec_sub8_cr_in[2:0] + end + attribute \src "libresoc.v:101791.3-101833.6" + process $proc$libresoc.v:101791$4104 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_cr_out[2:0] $1\dec31_dec_sub8_cr_out[2:0] + attribute \src "libresoc.v:101792.5-101792.29" + switch \initial + attribute \src "libresoc.v:101792.9-101792.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 + case + assign $1\dec31_dec_sub8_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub8_cr_out $0\dec31_dec_sub8_cr_out[2:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:101839.1-103418.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec31_dec_sub9" +attribute \generator "nMigen" +module \dec31_dec_sub9 + attribute \src "libresoc.v:102372.3-102426.6" + wire width 8 $0\dec31_dec_sub9_asmcode[7:0] + attribute \src "libresoc.v:102592.3-102646.6" + wire $0\dec31_dec_sub9_br[0:0] + attribute \src "libresoc.v:103307.3-103361.6" + wire width 3 $0\dec31_dec_sub9_cr_in[2:0] + attribute \src "libresoc.v:103362.3-103416.6" + wire width 3 $0\dec31_dec_sub9_cr_out[2:0] + attribute \src "libresoc.v:102317.3-102371.6" + wire width 2 $0\dec31_dec_sub9_cry_in[1:0] + attribute \src "libresoc.v:102537.3-102591.6" + wire $0\dec31_dec_sub9_cry_out[0:0] + attribute \src "libresoc.v:103032.3-103086.6" + wire width 5 $0\dec31_dec_sub9_form[4:0] + attribute \src "libresoc.v:102097.3-102151.6" + wire width 12 $0\dec31_dec_sub9_function_unit[11:0] + attribute \src "libresoc.v:103087.3-103141.6" + wire width 3 $0\dec31_dec_sub9_in1_sel[2:0] + attribute \src "libresoc.v:103142.3-103196.6" + wire width 4 $0\dec31_dec_sub9_in2_sel[3:0] + attribute \src "libresoc.v:103197.3-103251.6" + wire width 2 $0\dec31_dec_sub9_in3_sel[1:0] + attribute \src "libresoc.v:102702.3-102756.6" + wire width 7 $0\dec31_dec_sub9_internal_op[6:0] + attribute \src "libresoc.v:102427.3-102481.6" + wire $0\dec31_dec_sub9_inv_a[0:0] + attribute \src "libresoc.v:102482.3-102536.6" + wire $0\dec31_dec_sub9_inv_out[0:0] + attribute \src "libresoc.v:102812.3-102866.6" + wire $0\dec31_dec_sub9_is_32b[0:0] + attribute \src "libresoc.v:102152.3-102206.6" + wire width 4 $0\dec31_dec_sub9_ldst_len[3:0] + attribute \src "libresoc.v:102922.3-102976.6" + wire $0\dec31_dec_sub9_lk[0:0] + attribute \src "libresoc.v:103252.3-103306.6" + wire width 2 $0\dec31_dec_sub9_out_sel[1:0] + attribute \src "libresoc.v:102262.3-102316.6" + wire width 2 $0\dec31_dec_sub9_rc_sel[1:0] + attribute \src "libresoc.v:102757.3-102811.6" + wire $0\dec31_dec_sub9_rsrv[0:0] + attribute \src "libresoc.v:102977.3-103031.6" + wire $0\dec31_dec_sub9_sgl_pipe[0:0] + attribute \src "libresoc.v:102867.3-102921.6" + wire $0\dec31_dec_sub9_sgn[0:0] + attribute \src "libresoc.v:102647.3-102701.6" + wire $0\dec31_dec_sub9_sgn_ext[0:0] + attribute \src "libresoc.v:102207.3-102261.6" + wire width 2 $0\dec31_dec_sub9_upd[1:0] + attribute \src "libresoc.v:101840.7-101840.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:102372.3-102426.6" + wire width 8 $1\dec31_dec_sub9_asmcode[7:0] + attribute \src "libresoc.v:102592.3-102646.6" + wire $1\dec31_dec_sub9_br[0:0] + attribute \src "libresoc.v:103307.3-103361.6" + wire width 3 $1\dec31_dec_sub9_cr_in[2:0] + attribute \src "libresoc.v:103362.3-103416.6" + wire width 3 $1\dec31_dec_sub9_cr_out[2:0] + attribute \src "libresoc.v:102317.3-102371.6" + wire width 2 $1\dec31_dec_sub9_cry_in[1:0] + attribute \src "libresoc.v:102537.3-102591.6" + wire $1\dec31_dec_sub9_cry_out[0:0] + attribute \src "libresoc.v:103032.3-103086.6" + wire width 5 $1\dec31_dec_sub9_form[4:0] + attribute \src "libresoc.v:102097.3-102151.6" + wire width 12 $1\dec31_dec_sub9_function_unit[11:0] + attribute \src "libresoc.v:103087.3-103141.6" + wire width 3 $1\dec31_dec_sub9_in1_sel[2:0] + attribute \src "libresoc.v:103142.3-103196.6" + wire width 4 $1\dec31_dec_sub9_in2_sel[3:0] + attribute \src "libresoc.v:103197.3-103251.6" + wire width 2 $1\dec31_dec_sub9_in3_sel[1:0] + attribute \src "libresoc.v:102702.3-102756.6" + wire width 7 $1\dec31_dec_sub9_internal_op[6:0] + attribute \src "libresoc.v:102427.3-102481.6" + wire $1\dec31_dec_sub9_inv_a[0:0] + attribute \src "libresoc.v:102482.3-102536.6" + wire $1\dec31_dec_sub9_inv_out[0:0] + attribute \src "libresoc.v:102812.3-102866.6" + wire $1\dec31_dec_sub9_is_32b[0:0] + attribute \src "libresoc.v:102152.3-102206.6" + wire width 4 $1\dec31_dec_sub9_ldst_len[3:0] + attribute \src "libresoc.v:102922.3-102976.6" + wire $1\dec31_dec_sub9_lk[0:0] + attribute \src "libresoc.v:103252.3-103306.6" + wire width 2 $1\dec31_dec_sub9_out_sel[1:0] + attribute \src "libresoc.v:102262.3-102316.6" + wire width 2 $1\dec31_dec_sub9_rc_sel[1:0] + attribute \src "libresoc.v:102757.3-102811.6" + wire $1\dec31_dec_sub9_rsrv[0:0] + attribute \src "libresoc.v:102977.3-103031.6" + wire $1\dec31_dec_sub9_sgl_pipe[0:0] + attribute \src "libresoc.v:102867.3-102921.6" + wire $1\dec31_dec_sub9_sgn[0:0] + attribute \src "libresoc.v:102647.3-102701.6" + wire $1\dec31_dec_sub9_sgn_ext[0:0] + attribute \src "libresoc.v:102207.3-102261.6" + wire width 2 $1\dec31_dec_sub9_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 output 4 \dec31_dec_sub9_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 18 \dec31_dec_sub9_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 9 \dec31_dec_sub9_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 10 \dec31_dec_sub9_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 14 \dec31_dec_sub9_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 17 \dec31_dec_sub9_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 output 3 \dec31_dec_sub9_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \dec31_dec_sub9_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \dec31_dec_sub9_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 6 \dec31_dec_sub9_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 7 \dec31_dec_sub9_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \dec31_dec_sub9_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 15 \dec31_dec_sub9_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 16 \dec31_dec_sub9_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 21 \dec31_dec_sub9_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 11 \dec31_dec_sub9_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 23 \dec31_dec_sub9_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 8 \dec31_dec_sub9_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 13 \dec31_dec_sub9_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 20 \dec31_dec_sub9_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 24 \dec31_dec_sub9_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 22 \dec31_dec_sub9_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 19 \dec31_dec_sub9_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 12 \dec31_dec_sub9_upd + attribute \src "libresoc.v:101840.7-101840.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 5 \opcode_switch + attribute \src "libresoc.v:101840.7-101840.20" + process $proc$libresoc.v:101840$4130 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:102097.3-102151.6" + process $proc$libresoc.v:102097$4106 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_function_unit[11:0] $1\dec31_dec_sub9_function_unit[11:0] + attribute \src "libresoc.v:102098.5-102098.29" + switch \initial + attribute \src "libresoc.v:102098.9-102098.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_function_unit[11:0] 12'000100000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_function_unit[11:0] 12'000100000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_function_unit[11:0] 12'000100000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_function_unit[11:0] 12'000100000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_function_unit[11:0] 12'000100000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_function_unit[11:0] 12'000100000000 + case + assign $1\dec31_dec_sub9_function_unit[11:0] 12'000000000000 + end + sync always + update \dec31_dec_sub9_function_unit $0\dec31_dec_sub9_function_unit[11:0] + end + attribute \src "libresoc.v:102152.3-102206.6" + process $proc$libresoc.v:102152$4107 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_ldst_len[3:0] $1\dec31_dec_sub9_ldst_len[3:0] + attribute \src "libresoc.v:102153.5-102153.29" + switch \initial + attribute \src "libresoc.v:102153.9-102153.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + case + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub9_ldst_len $0\dec31_dec_sub9_ldst_len[3:0] + end + attribute \src "libresoc.v:102207.3-102261.6" + process $proc$libresoc.v:102207$4108 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_upd[1:0] $1\dec31_dec_sub9_upd[1:0] + attribute \src "libresoc.v:102208.5-102208.29" + switch \initial + attribute \src "libresoc.v:102208.9-102208.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub9_upd $0\dec31_dec_sub9_upd[1:0] + end + attribute \src "libresoc.v:102262.3-102316.6" + process $proc$libresoc.v:102262$4109 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_rc_sel[1:0] $1\dec31_dec_sub9_rc_sel[1:0] + attribute \src "libresoc.v:102263.5-102263.29" + switch \initial + attribute \src "libresoc.v:102263.9-102263.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + case + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub9_rc_sel $0\dec31_dec_sub9_rc_sel[1:0] + end + attribute \src "libresoc.v:102317.3-102371.6" + process $proc$libresoc.v:102317$4110 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_cry_in[1:0] $1\dec31_dec_sub9_cry_in[1:0] + attribute \src "libresoc.v:102318.5-102318.29" + switch \initial + attribute \src "libresoc.v:102318.9-102318.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + case + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub9_cry_in $0\dec31_dec_sub9_cry_in[1:0] + end + attribute \src "libresoc.v:102372.3-102426.6" + process $proc$libresoc.v:102372$4111 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_asmcode[7:0] $1\dec31_dec_sub9_asmcode[7:0] + attribute \src "libresoc.v:102373.5-102373.29" + switch \initial + attribute \src "libresoc.v:102373.9-102373.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_asmcode[7:0] 8'00110110 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_asmcode[7:0] 8'00110111 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_asmcode[7:0] 8'00110100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_asmcode[7:0] 8'00110101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_asmcode[7:0] 8'00111001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_asmcode[7:0] 8'00111010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_asmcode[7:0] 8'00110011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_asmcode[7:0] 8'00111000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_asmcode[7:0] 8'01110100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_asmcode[7:0] 8'01110010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_asmcode[7:0] 8'01111010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_asmcode[7:0] 8'01111011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_asmcode[7:0] 8'01111010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_asmcode[7:0] 8'01111011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_asmcode[7:0] 8'01111110 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_asmcode[7:0] 8'01111111 + case + assign $1\dec31_dec_sub9_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub9_asmcode $0\dec31_dec_sub9_asmcode[7:0] + end + attribute \src "libresoc.v:102427.3-102481.6" + process $proc$libresoc.v:102427$4112 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_inv_a[0:0] $1\dec31_dec_sub9_inv_a[0:0] + attribute \src "libresoc.v:102428.5-102428.29" + switch \initial + attribute \src "libresoc.v:102428.9-102428.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub9_inv_a $0\dec31_dec_sub9_inv_a[0:0] + end + attribute \src "libresoc.v:102482.3-102536.6" + process $proc$libresoc.v:102482$4113 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_inv_out[0:0] $1\dec31_dec_sub9_inv_out[0:0] + attribute \src "libresoc.v:102483.5-102483.29" + switch \initial + attribute \src "libresoc.v:102483.9-102483.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub9_inv_out $0\dec31_dec_sub9_inv_out[0:0] + end + attribute \src "libresoc.v:102537.3-102591.6" + process $proc$libresoc.v:102537$4114 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_cry_out[0:0] $1\dec31_dec_sub9_cry_out[0:0] + attribute \src "libresoc.v:102538.5-102538.29" + switch \initial + attribute \src "libresoc.v:102538.9-102538.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + case + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub9_cry_out $0\dec31_dec_sub9_cry_out[0:0] + end + attribute \src "libresoc.v:102592.3-102646.6" + process $proc$libresoc.v:102592$4115 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_br[0:0] $1\dec31_dec_sub9_br[0:0] + attribute \src "libresoc.v:102593.5-102593.29" + switch \initial + attribute \src "libresoc.v:102593.9-102593.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + case + assign $1\dec31_dec_sub9_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub9_br $0\dec31_dec_sub9_br[0:0] + end + attribute \src "libresoc.v:102647.3-102701.6" + process $proc$libresoc.v:102647$4116 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_sgn_ext[0:0] $1\dec31_dec_sub9_sgn_ext[0:0] + attribute \src "libresoc.v:102648.5-102648.29" + switch \initial + attribute \src "libresoc.v:102648.9-102648.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub9_sgn_ext $0\dec31_dec_sub9_sgn_ext[0:0] + end + attribute \src "libresoc.v:102702.3-102756.6" + process $proc$libresoc.v:102702$4117 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_internal_op[6:0] $1\dec31_dec_sub9_internal_op[6:0] + attribute \src "libresoc.v:102703.5-102703.29" + switch \initial + attribute \src "libresoc.v:102703.9-102703.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011110 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011110 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011110 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011110 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0101111 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0101111 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0110011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0110011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0110011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0110011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0110010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0110010 + case + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub9_internal_op $0\dec31_dec_sub9_internal_op[6:0] + end + attribute \src "libresoc.v:102757.3-102811.6" + process $proc$libresoc.v:102757$4118 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_rsrv[0:0] $1\dec31_dec_sub9_rsrv[0:0] + attribute \src "libresoc.v:102758.5-102758.29" + switch \initial + attribute \src "libresoc.v:102758.9-102758.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub9_rsrv $0\dec31_dec_sub9_rsrv[0:0] + end + attribute \src "libresoc.v:102812.3-102866.6" + process $proc$libresoc.v:102812$4119 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_is_32b[0:0] $1\dec31_dec_sub9_is_32b[0:0] + attribute \src "libresoc.v:102813.5-102813.29" + switch \initial + attribute \src "libresoc.v:102813.9-102813.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + case + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub9_is_32b $0\dec31_dec_sub9_is_32b[0:0] + end + attribute \src "libresoc.v:102867.3-102921.6" + process $proc$libresoc.v:102867$4120 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_sgn[0:0] $1\dec31_dec_sub9_sgn[0:0] + attribute \src "libresoc.v:102868.5-102868.29" + switch \initial + attribute \src "libresoc.v:102868.9-102868.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'1 + case + assign $1\dec31_dec_sub9_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub9_sgn $0\dec31_dec_sub9_sgn[0:0] + end + attribute \src "libresoc.v:102922.3-102976.6" + process $proc$libresoc.v:102922$4121 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_lk[0:0] $1\dec31_dec_sub9_lk[0:0] + attribute \src "libresoc.v:102923.5-102923.29" + switch \initial + attribute \src "libresoc.v:102923.9-102923.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub9_lk $0\dec31_dec_sub9_lk[0:0] + end + attribute \src "libresoc.v:102977.3-103031.6" + process $proc$libresoc.v:102977$4122 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_sgl_pipe[0:0] $1\dec31_dec_sub9_sgl_pipe[0:0] + attribute \src "libresoc.v:102978.5-102978.29" + switch \initial + attribute \src "libresoc.v:102978.9-102978.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + case + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub9_sgl_pipe $0\dec31_dec_sub9_sgl_pipe[0:0] + end + attribute \src "libresoc.v:103032.3-103086.6" + process $proc$libresoc.v:103032$4123 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_form[4:0] $1\dec31_dec_sub9_form[4:0] + attribute \src "libresoc.v:103033.5-103033.29" + switch \initial + attribute \src "libresoc.v:103033.9-103033.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'10001 + case + assign $1\dec31_dec_sub9_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub9_form $0\dec31_dec_sub9_form[4:0] + end + attribute \src "libresoc.v:103087.3-103141.6" + process $proc$libresoc.v:103087$4124 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_in1_sel[2:0] $1\dec31_dec_sub9_in1_sel[2:0] + attribute \src "libresoc.v:103088.5-103088.29" + switch \initial + attribute \src "libresoc.v:103088.9-103088.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + case + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub9_in1_sel $0\dec31_dec_sub9_in1_sel[2:0] + end + attribute \src "libresoc.v:103142.3-103196.6" + process $proc$libresoc.v:103142$4125 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_in2_sel[3:0] $1\dec31_dec_sub9_in2_sel[3:0] + attribute \src "libresoc.v:103143.5-103143.29" + switch \initial + attribute \src "libresoc.v:103143.9-103143.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + case + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub9_in2_sel $0\dec31_dec_sub9_in2_sel[3:0] + end + attribute \src "libresoc.v:103197.3-103251.6" + process $proc$libresoc.v:103197$4126 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_in3_sel[1:0] $1\dec31_dec_sub9_in3_sel[1:0] + attribute \src "libresoc.v:103198.5-103198.29" + switch \initial + attribute \src "libresoc.v:103198.9-103198.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub9_in3_sel $0\dec31_dec_sub9_in3_sel[1:0] + end + attribute \src "libresoc.v:103252.3-103306.6" + process $proc$libresoc.v:103252$4127 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_out_sel[1:0] $1\dec31_dec_sub9_out_sel[1:0] + attribute \src "libresoc.v:103253.5-103253.29" + switch \initial + attribute \src "libresoc.v:103253.9-103253.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 + case + assign $1\dec31_dec_sub9_out_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub9_out_sel $0\dec31_dec_sub9_out_sel[1:0] + end + attribute \src "libresoc.v:103307.3-103361.6" + process $proc$libresoc.v:103307$4128 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_cr_in[2:0] $1\dec31_dec_sub9_cr_in[2:0] + attribute \src "libresoc.v:103308.5-103308.29" + switch \initial + attribute \src "libresoc.v:103308.9-103308.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub9_cr_in $0\dec31_dec_sub9_cr_in[2:0] + end + attribute \src "libresoc.v:103362.3-103416.6" + process $proc$libresoc.v:103362$4129 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_cr_out[2:0] $1\dec31_dec_sub9_cr_out[2:0] + attribute \src "libresoc.v:103363.5-103363.29" + switch \initial + attribute \src "libresoc.v:103363.9-103363.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 + case + assign $1\dec31_dec_sub9_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub9_cr_out $0\dec31_dec_sub9_cr_out[2:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:103422.1-104065.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec58" +attribute \generator "nMigen" +module \dec58 + attribute \src "libresoc.v:103760.3-103775.6" + wire width 8 $0\dec58_asmcode[7:0] + attribute \src "libresoc.v:103824.3-103839.6" + wire $0\dec58_br[0:0] + attribute \src "libresoc.v:104032.3-104047.6" + wire width 3 $0\dec58_cr_in[2:0] + attribute \src "libresoc.v:104048.3-104063.6" + wire width 3 $0\dec58_cr_out[2:0] + attribute \src "libresoc.v:103744.3-103759.6" + wire width 2 $0\dec58_cry_in[1:0] + attribute \src "libresoc.v:103808.3-103823.6" + wire $0\dec58_cry_out[0:0] + attribute \src "libresoc.v:103952.3-103967.6" + wire width 5 $0\dec58_form[4:0] + attribute \src "libresoc.v:103680.3-103695.6" + wire width 12 $0\dec58_function_unit[11:0] + attribute \src "libresoc.v:103968.3-103983.6" + wire width 3 $0\dec58_in1_sel[2:0] + attribute \src "libresoc.v:103984.3-103999.6" + wire width 4 $0\dec58_in2_sel[3:0] + attribute \src "libresoc.v:104000.3-104015.6" + wire width 2 $0\dec58_in3_sel[1:0] + attribute \src "libresoc.v:103856.3-103871.6" + wire width 7 $0\dec58_internal_op[6:0] + attribute \src "libresoc.v:103776.3-103791.6" + wire $0\dec58_inv_a[0:0] + attribute \src "libresoc.v:103792.3-103807.6" + wire $0\dec58_inv_out[0:0] + attribute \src "libresoc.v:103888.3-103903.6" + wire $0\dec58_is_32b[0:0] + attribute \src "libresoc.v:103696.3-103711.6" + wire width 4 $0\dec58_ldst_len[3:0] + attribute \src "libresoc.v:103920.3-103935.6" + wire $0\dec58_lk[0:0] + attribute \src "libresoc.v:104016.3-104031.6" + wire width 2 $0\dec58_out_sel[1:0] + attribute \src "libresoc.v:103728.3-103743.6" + wire width 2 $0\dec58_rc_sel[1:0] + attribute \src "libresoc.v:103872.3-103887.6" + wire $0\dec58_rsrv[0:0] + attribute \src "libresoc.v:103936.3-103951.6" + wire $0\dec58_sgl_pipe[0:0] + attribute \src "libresoc.v:103904.3-103919.6" + wire $0\dec58_sgn[0:0] + attribute \src "libresoc.v:103840.3-103855.6" + wire $0\dec58_sgn_ext[0:0] + attribute \src "libresoc.v:103712.3-103727.6" + wire width 2 $0\dec58_upd[1:0] + attribute \src "libresoc.v:103423.7-103423.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:103760.3-103775.6" + wire width 8 $1\dec58_asmcode[7:0] + attribute \src "libresoc.v:103824.3-103839.6" + wire $1\dec58_br[0:0] + attribute \src "libresoc.v:104032.3-104047.6" + wire width 3 $1\dec58_cr_in[2:0] + attribute \src "libresoc.v:104048.3-104063.6" + wire width 3 $1\dec58_cr_out[2:0] + attribute \src "libresoc.v:103744.3-103759.6" + wire width 2 $1\dec58_cry_in[1:0] + attribute \src "libresoc.v:103808.3-103823.6" + wire $1\dec58_cry_out[0:0] + attribute \src "libresoc.v:103952.3-103967.6" + wire width 5 $1\dec58_form[4:0] + attribute \src "libresoc.v:103680.3-103695.6" + wire width 12 $1\dec58_function_unit[11:0] + attribute \src "libresoc.v:103968.3-103983.6" + wire width 3 $1\dec58_in1_sel[2:0] + attribute \src "libresoc.v:103984.3-103999.6" + wire width 4 $1\dec58_in2_sel[3:0] + attribute \src "libresoc.v:104000.3-104015.6" + wire width 2 $1\dec58_in3_sel[1:0] + attribute \src "libresoc.v:103856.3-103871.6" + wire width 7 $1\dec58_internal_op[6:0] + attribute \src "libresoc.v:103776.3-103791.6" + wire $1\dec58_inv_a[0:0] + attribute \src "libresoc.v:103792.3-103807.6" + wire $1\dec58_inv_out[0:0] + attribute \src "libresoc.v:103888.3-103903.6" + wire $1\dec58_is_32b[0:0] + attribute \src "libresoc.v:103696.3-103711.6" + wire width 4 $1\dec58_ldst_len[3:0] + attribute \src "libresoc.v:103920.3-103935.6" + wire $1\dec58_lk[0:0] + attribute \src "libresoc.v:104016.3-104031.6" + wire width 2 $1\dec58_out_sel[1:0] + attribute \src "libresoc.v:103728.3-103743.6" + wire width 2 $1\dec58_rc_sel[1:0] + attribute \src "libresoc.v:103872.3-103887.6" + wire $1\dec58_rsrv[0:0] + attribute \src "libresoc.v:103936.3-103951.6" + wire $1\dec58_sgl_pipe[0:0] + attribute \src "libresoc.v:103904.3-103919.6" + wire $1\dec58_sgn[0:0] + attribute \src "libresoc.v:103840.3-103855.6" + wire $1\dec58_sgn_ext[0:0] + attribute \src "libresoc.v:103712.3-103727.6" + wire width 2 $1\dec58_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 output 4 \dec58_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 18 \dec58_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 9 \dec58_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 10 \dec58_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 14 \dec58_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 17 \dec58_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 output 3 \dec58_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \dec58_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \dec58_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 6 \dec58_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 7 \dec58_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \dec58_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 15 \dec58_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 16 \dec58_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 21 \dec58_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 11 \dec58_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 23 \dec58_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 8 \dec58_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 13 \dec58_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 20 \dec58_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 24 \dec58_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 22 \dec58_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 19 \dec58_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 12 \dec58_upd + attribute \src "libresoc.v:103423.7-103423.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 2 \opcode_switch + attribute \src "libresoc.v:103423.7-103423.20" + process $proc$libresoc.v:103423$4155 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:103680.3-103695.6" + process $proc$libresoc.v:103680$4131 + assign { } { } + assign { } { } + assign $0\dec58_function_unit[11:0] $1\dec58_function_unit[11:0] + attribute \src "libresoc.v:103681.5-103681.29" + switch \initial + attribute \src "libresoc.v:103681.9-103681.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_function_unit[11:0] 12'000000000100 + case + assign $1\dec58_function_unit[11:0] 12'000000000000 + end + sync always + update \dec58_function_unit $0\dec58_function_unit[11:0] + end + attribute \src "libresoc.v:103696.3-103711.6" + process $proc$libresoc.v:103696$4132 + assign { } { } + assign { } { } + assign $0\dec58_ldst_len[3:0] $1\dec58_ldst_len[3:0] + attribute \src "libresoc.v:103697.5-103697.29" + switch \initial + attribute \src "libresoc.v:103697.9-103697.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_ldst_len[3:0] 4'0100 + case + assign $1\dec58_ldst_len[3:0] 4'0000 + end + sync always + update \dec58_ldst_len $0\dec58_ldst_len[3:0] + end + attribute \src "libresoc.v:103712.3-103727.6" + process $proc$libresoc.v:103712$4133 + assign { } { } + assign { } { } + assign $0\dec58_upd[1:0] $1\dec58_upd[1:0] + attribute \src "libresoc.v:103713.5-103713.29" + switch \initial + attribute \src "libresoc.v:103713.9-103713.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_upd[1:0] 2'00 + case + assign $1\dec58_upd[1:0] 2'00 + end + sync always + update \dec58_upd $0\dec58_upd[1:0] + end + attribute \src "libresoc.v:103728.3-103743.6" + process $proc$libresoc.v:103728$4134 + assign { } { } + assign { } { } + assign $0\dec58_rc_sel[1:0] $1\dec58_rc_sel[1:0] + attribute \src "libresoc.v:103729.5-103729.29" + switch \initial + attribute \src "libresoc.v:103729.9-103729.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_rc_sel[1:0] 2'00 + case + assign $1\dec58_rc_sel[1:0] 2'00 + end + sync always + update \dec58_rc_sel $0\dec58_rc_sel[1:0] + end + attribute \src "libresoc.v:103744.3-103759.6" + process $proc$libresoc.v:103744$4135 + assign { } { } + assign { } { } + assign $0\dec58_cry_in[1:0] $1\dec58_cry_in[1:0] + attribute \src "libresoc.v:103745.5-103745.29" + switch \initial + attribute \src "libresoc.v:103745.9-103745.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_cry_in[1:0] 2'00 + case + assign $1\dec58_cry_in[1:0] 2'00 + end + sync always + update \dec58_cry_in $0\dec58_cry_in[1:0] + end + attribute \src "libresoc.v:103760.3-103775.6" + process $proc$libresoc.v:103760$4136 + assign { } { } + assign { } { } + assign $0\dec58_asmcode[7:0] $1\dec58_asmcode[7:0] + attribute \src "libresoc.v:103761.5-103761.29" + switch \initial + attribute \src "libresoc.v:103761.9-103761.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_asmcode[7:0] 8'01010010 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_asmcode[7:0] 8'01010101 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_asmcode[7:0] 8'01100010 + case + assign $1\dec58_asmcode[7:0] 8'00000000 + end + sync always + update \dec58_asmcode $0\dec58_asmcode[7:0] + end + attribute \src "libresoc.v:103776.3-103791.6" + process $proc$libresoc.v:103776$4137 + assign { } { } + assign { } { } + assign $0\dec58_inv_a[0:0] $1\dec58_inv_a[0:0] + attribute \src "libresoc.v:103777.5-103777.29" + switch \initial + attribute \src "libresoc.v:103777.9-103777.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_inv_a[0:0] 1'0 + case + assign $1\dec58_inv_a[0:0] 1'0 + end + sync always + update \dec58_inv_a $0\dec58_inv_a[0:0] + end + attribute \src "libresoc.v:103792.3-103807.6" + process $proc$libresoc.v:103792$4138 + assign { } { } + assign { } { } + assign $0\dec58_inv_out[0:0] $1\dec58_inv_out[0:0] + attribute \src "libresoc.v:103793.5-103793.29" + switch \initial + attribute \src "libresoc.v:103793.9-103793.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_inv_out[0:0] 1'0 + case + assign $1\dec58_inv_out[0:0] 1'0 + end + sync always + update \dec58_inv_out $0\dec58_inv_out[0:0] + end + attribute \src "libresoc.v:103808.3-103823.6" + process $proc$libresoc.v:103808$4139 + assign { } { } + assign { } { } + assign $0\dec58_cry_out[0:0] $1\dec58_cry_out[0:0] + attribute \src "libresoc.v:103809.5-103809.29" + switch \initial + attribute \src "libresoc.v:103809.9-103809.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_cry_out[0:0] 1'0 + case + assign $1\dec58_cry_out[0:0] 1'0 + end + sync always + update \dec58_cry_out $0\dec58_cry_out[0:0] + end + attribute \src "libresoc.v:103824.3-103839.6" + process $proc$libresoc.v:103824$4140 + assign { } { } + assign { } { } + assign $0\dec58_br[0:0] $1\dec58_br[0:0] + attribute \src "libresoc.v:103825.5-103825.29" + switch \initial + attribute \src "libresoc.v:103825.9-103825.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_br[0:0] 1'0 + case + assign $1\dec58_br[0:0] 1'0 + end + sync always + update \dec58_br $0\dec58_br[0:0] + end + attribute \src "libresoc.v:103840.3-103855.6" + process $proc$libresoc.v:103840$4141 + assign { } { } + assign { } { } + assign $0\dec58_sgn_ext[0:0] $1\dec58_sgn_ext[0:0] + attribute \src "libresoc.v:103841.5-103841.29" + switch \initial + attribute \src "libresoc.v:103841.9-103841.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_sgn_ext[0:0] 1'1 + case + assign $1\dec58_sgn_ext[0:0] 1'0 + end + sync always + update \dec58_sgn_ext $0\dec58_sgn_ext[0:0] + end + attribute \src "libresoc.v:103856.3-103871.6" + process $proc$libresoc.v:103856$4142 + assign { } { } + assign { } { } + assign $0\dec58_internal_op[6:0] $1\dec58_internal_op[6:0] + attribute \src "libresoc.v:103857.5-103857.29" + switch \initial + attribute \src "libresoc.v:103857.9-103857.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_internal_op[6:0] 7'0100101 + case + assign $1\dec58_internal_op[6:0] 7'0000000 + end + sync always + update \dec58_internal_op $0\dec58_internal_op[6:0] + end + attribute \src "libresoc.v:103872.3-103887.6" + process $proc$libresoc.v:103872$4143 + assign { } { } + assign { } { } + assign $0\dec58_rsrv[0:0] $1\dec58_rsrv[0:0] + attribute \src "libresoc.v:103873.5-103873.29" + switch \initial + attribute \src "libresoc.v:103873.9-103873.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_rsrv[0:0] 1'0 + case + assign $1\dec58_rsrv[0:0] 1'0 + end + sync always + update \dec58_rsrv $0\dec58_rsrv[0:0] + end + attribute \src "libresoc.v:103888.3-103903.6" + process $proc$libresoc.v:103888$4144 + assign { } { } + assign { } { } + assign $0\dec58_is_32b[0:0] $1\dec58_is_32b[0:0] + attribute \src "libresoc.v:103889.5-103889.29" + switch \initial + attribute \src "libresoc.v:103889.9-103889.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_is_32b[0:0] 1'0 + case + assign $1\dec58_is_32b[0:0] 1'0 + end + sync always + update \dec58_is_32b $0\dec58_is_32b[0:0] + end + attribute \src "libresoc.v:103904.3-103919.6" + process $proc$libresoc.v:103904$4145 + assign { } { } + assign { } { } + assign $0\dec58_sgn[0:0] $1\dec58_sgn[0:0] + attribute \src "libresoc.v:103905.5-103905.29" + switch \initial + attribute \src "libresoc.v:103905.9-103905.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_sgn[0:0] 1'0 + case + assign $1\dec58_sgn[0:0] 1'0 + end + sync always + update \dec58_sgn $0\dec58_sgn[0:0] + end + attribute \src "libresoc.v:103920.3-103935.6" + process $proc$libresoc.v:103920$4146 + assign { } { } + assign { } { } + assign $0\dec58_lk[0:0] $1\dec58_lk[0:0] + attribute \src "libresoc.v:103921.5-103921.29" + switch \initial + attribute \src "libresoc.v:103921.9-103921.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_lk[0:0] 1'0 + case + assign $1\dec58_lk[0:0] 1'0 + end + sync always + update \dec58_lk $0\dec58_lk[0:0] + end + attribute \src "libresoc.v:103936.3-103951.6" + process $proc$libresoc.v:103936$4147 + assign { } { } + assign { } { } + assign $0\dec58_sgl_pipe[0:0] $1\dec58_sgl_pipe[0:0] + attribute \src "libresoc.v:103937.5-103937.29" + switch \initial + attribute \src "libresoc.v:103937.9-103937.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_sgl_pipe[0:0] 1'1 + case + assign $1\dec58_sgl_pipe[0:0] 1'0 + end + sync always + update \dec58_sgl_pipe $0\dec58_sgl_pipe[0:0] + end + attribute \src "libresoc.v:103952.3-103967.6" + process $proc$libresoc.v:103952$4148 + assign { } { } + assign { } { } + assign $0\dec58_form[4:0] $1\dec58_form[4:0] + attribute \src "libresoc.v:103953.5-103953.29" + switch \initial + attribute \src "libresoc.v:103953.9-103953.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_form[4:0] 5'00101 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_form[4:0] 5'00101 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_form[4:0] 5'00101 + case + assign $1\dec58_form[4:0] 5'00000 + end + sync always + update \dec58_form $0\dec58_form[4:0] + end + attribute \src "libresoc.v:103968.3-103983.6" + process $proc$libresoc.v:103968$4149 + assign { } { } + assign { } { } + assign $0\dec58_in1_sel[2:0] $1\dec58_in1_sel[2:0] + attribute \src "libresoc.v:103969.5-103969.29" + switch \initial + attribute \src "libresoc.v:103969.9-103969.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_in1_sel[2:0] 3'010 + case + assign $1\dec58_in1_sel[2:0] 3'000 + end + sync always + update \dec58_in1_sel $0\dec58_in1_sel[2:0] + end + attribute \src "libresoc.v:103984.3-103999.6" + process $proc$libresoc.v:103984$4150 + assign { } { } + assign { } { } + assign $0\dec58_in2_sel[3:0] $1\dec58_in2_sel[3:0] + attribute \src "libresoc.v:103985.5-103985.29" + switch \initial + attribute \src "libresoc.v:103985.9-103985.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_in2_sel[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_in2_sel[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_in2_sel[3:0] 4'1000 + case + assign $1\dec58_in2_sel[3:0] 4'0000 + end + sync always + update \dec58_in2_sel $0\dec58_in2_sel[3:0] + end + attribute \src "libresoc.v:104000.3-104015.6" + process $proc$libresoc.v:104000$4151 + assign { } { } + assign { } { } + assign $0\dec58_in3_sel[1:0] $1\dec58_in3_sel[1:0] + attribute \src "libresoc.v:104001.5-104001.29" + switch \initial + attribute \src "libresoc.v:104001.9-104001.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_in3_sel[1:0] 2'00 + case + assign $1\dec58_in3_sel[1:0] 2'00 + end + sync always + update \dec58_in3_sel $0\dec58_in3_sel[1:0] + end + attribute \src "libresoc.v:104016.3-104031.6" + process $proc$libresoc.v:104016$4152 + assign { } { } + assign { } { } + assign $0\dec58_out_sel[1:0] $1\dec58_out_sel[1:0] + attribute \src "libresoc.v:104017.5-104017.29" + switch \initial + attribute \src "libresoc.v:104017.9-104017.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_out_sel[1:0] 2'01 + case + assign $1\dec58_out_sel[1:0] 2'00 + end + sync always + update \dec58_out_sel $0\dec58_out_sel[1:0] + end + attribute \src "libresoc.v:104032.3-104047.6" + process $proc$libresoc.v:104032$4153 + assign { } { } + assign { } { } + assign $0\dec58_cr_in[2:0] $1\dec58_cr_in[2:0] + attribute \src "libresoc.v:104033.5-104033.29" + switch \initial + attribute \src "libresoc.v:104033.9-104033.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_cr_in[2:0] 3'000 + case + assign $1\dec58_cr_in[2:0] 3'000 + end + sync always + update \dec58_cr_in $0\dec58_cr_in[2:0] + end + attribute \src "libresoc.v:104048.3-104063.6" + process $proc$libresoc.v:104048$4154 + assign { } { } + assign { } { } + assign $0\dec58_cr_out[2:0] $1\dec58_cr_out[2:0] + attribute \src "libresoc.v:104049.5-104049.29" + switch \initial + attribute \src "libresoc.v:104049.9-104049.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_cr_out[2:0] 3'000 + case + assign $1\dec58_cr_out[2:0] 3'000 + end + sync always + update \dec58_cr_out $0\dec58_cr_out[2:0] + end + connect \opcode_switch \opcode_in [1:0] +end +attribute \src "libresoc.v:104069.1-104640.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec62" +attribute \generator "nMigen" +module \dec62 + attribute \src "libresoc.v:104392.3-104404.6" + wire width 8 $0\dec62_asmcode[7:0] + attribute \src "libresoc.v:104444.3-104456.6" + wire $0\dec62_br[0:0] + attribute \src "libresoc.v:104613.3-104625.6" + wire width 3 $0\dec62_cr_in[2:0] + attribute \src "libresoc.v:104626.3-104638.6" + wire width 3 $0\dec62_cr_out[2:0] + attribute \src "libresoc.v:104379.3-104391.6" + wire width 2 $0\dec62_cry_in[1:0] + attribute \src "libresoc.v:104431.3-104443.6" + wire $0\dec62_cry_out[0:0] + attribute \src "libresoc.v:104548.3-104560.6" + wire width 5 $0\dec62_form[4:0] + attribute \src "libresoc.v:104327.3-104339.6" + wire width 12 $0\dec62_function_unit[11:0] + attribute \src "libresoc.v:104561.3-104573.6" + wire width 3 $0\dec62_in1_sel[2:0] + attribute \src "libresoc.v:104574.3-104586.6" + wire width 4 $0\dec62_in2_sel[3:0] + attribute \src "libresoc.v:104587.3-104599.6" + wire width 2 $0\dec62_in3_sel[1:0] + attribute \src "libresoc.v:104470.3-104482.6" + wire width 7 $0\dec62_internal_op[6:0] + attribute \src "libresoc.v:104405.3-104417.6" + wire $0\dec62_inv_a[0:0] + attribute \src "libresoc.v:104418.3-104430.6" + wire $0\dec62_inv_out[0:0] + attribute \src "libresoc.v:104496.3-104508.6" + wire $0\dec62_is_32b[0:0] + attribute \src "libresoc.v:104340.3-104352.6" + wire width 4 $0\dec62_ldst_len[3:0] + attribute \src "libresoc.v:104522.3-104534.6" + wire $0\dec62_lk[0:0] + attribute \src "libresoc.v:104600.3-104612.6" + wire width 2 $0\dec62_out_sel[1:0] + attribute \src "libresoc.v:104366.3-104378.6" + wire width 2 $0\dec62_rc_sel[1:0] + attribute \src "libresoc.v:104483.3-104495.6" + wire $0\dec62_rsrv[0:0] + attribute \src "libresoc.v:104535.3-104547.6" + wire $0\dec62_sgl_pipe[0:0] + attribute \src "libresoc.v:104509.3-104521.6" + wire $0\dec62_sgn[0:0] + attribute \src "libresoc.v:104457.3-104469.6" + wire $0\dec62_sgn_ext[0:0] + attribute \src "libresoc.v:104353.3-104365.6" + wire width 2 $0\dec62_upd[1:0] + attribute \src "libresoc.v:104070.7-104070.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:104392.3-104404.6" + wire width 8 $1\dec62_asmcode[7:0] + attribute \src "libresoc.v:104444.3-104456.6" + wire $1\dec62_br[0:0] + attribute \src "libresoc.v:104613.3-104625.6" + wire width 3 $1\dec62_cr_in[2:0] + attribute \src "libresoc.v:104626.3-104638.6" + wire width 3 $1\dec62_cr_out[2:0] + attribute \src "libresoc.v:104379.3-104391.6" + wire width 2 $1\dec62_cry_in[1:0] + attribute \src "libresoc.v:104431.3-104443.6" + wire $1\dec62_cry_out[0:0] + attribute \src "libresoc.v:104548.3-104560.6" + wire width 5 $1\dec62_form[4:0] + attribute \src "libresoc.v:104327.3-104339.6" + wire width 12 $1\dec62_function_unit[11:0] + attribute \src "libresoc.v:104561.3-104573.6" + wire width 3 $1\dec62_in1_sel[2:0] + attribute \src "libresoc.v:104574.3-104586.6" + wire width 4 $1\dec62_in2_sel[3:0] + attribute \src "libresoc.v:104587.3-104599.6" + wire width 2 $1\dec62_in3_sel[1:0] + attribute \src "libresoc.v:104470.3-104482.6" + wire width 7 $1\dec62_internal_op[6:0] + attribute \src "libresoc.v:104405.3-104417.6" + wire $1\dec62_inv_a[0:0] + attribute \src "libresoc.v:104418.3-104430.6" + wire $1\dec62_inv_out[0:0] + attribute \src "libresoc.v:104496.3-104508.6" + wire $1\dec62_is_32b[0:0] + attribute \src "libresoc.v:104340.3-104352.6" + wire width 4 $1\dec62_ldst_len[3:0] + attribute \src "libresoc.v:104522.3-104534.6" + wire $1\dec62_lk[0:0] + attribute \src "libresoc.v:104600.3-104612.6" + wire width 2 $1\dec62_out_sel[1:0] + attribute \src "libresoc.v:104366.3-104378.6" + wire width 2 $1\dec62_rc_sel[1:0] + attribute \src "libresoc.v:104483.3-104495.6" + wire $1\dec62_rsrv[0:0] + attribute \src "libresoc.v:104535.3-104547.6" + wire $1\dec62_sgl_pipe[0:0] + attribute \src "libresoc.v:104509.3-104521.6" + wire $1\dec62_sgn[0:0] + attribute \src "libresoc.v:104457.3-104469.6" + wire $1\dec62_sgn_ext[0:0] + attribute \src "libresoc.v:104353.3-104365.6" + wire width 2 $1\dec62_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 output 4 \dec62_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 18 \dec62_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 9 \dec62_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 10 \dec62_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 14 \dec62_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 17 \dec62_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 output 3 \dec62_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \dec62_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \dec62_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 6 \dec62_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 7 \dec62_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \dec62_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 15 \dec62_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 16 \dec62_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 21 \dec62_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 11 \dec62_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 23 \dec62_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 8 \dec62_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 13 \dec62_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 20 \dec62_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 24 \dec62_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 22 \dec62_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 19 \dec62_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 12 \dec62_upd + attribute \src "libresoc.v:104070.7-104070.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 2 \opcode_switch + attribute \src "libresoc.v:104070.7-104070.20" + process $proc$libresoc.v:104070$4180 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:104327.3-104339.6" + process $proc$libresoc.v:104327$4156 + assign { } { } + assign { } { } + assign $0\dec62_function_unit[11:0] $1\dec62_function_unit[11:0] + attribute \src "libresoc.v:104328.5-104328.29" + switch \initial + attribute \src "libresoc.v:104328.9-104328.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_function_unit[11:0] 12'000000000100 + case + assign $1\dec62_function_unit[11:0] 12'000000000000 + end + sync always + update \dec62_function_unit $0\dec62_function_unit[11:0] + end + attribute \src "libresoc.v:104340.3-104352.6" + process $proc$libresoc.v:104340$4157 + assign { } { } + assign { } { } + assign $0\dec62_ldst_len[3:0] $1\dec62_ldst_len[3:0] + attribute \src "libresoc.v:104341.5-104341.29" + switch \initial + attribute \src "libresoc.v:104341.9-104341.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_ldst_len[3:0] 4'1000 + case + assign $1\dec62_ldst_len[3:0] 4'0000 + end + sync always + update \dec62_ldst_len $0\dec62_ldst_len[3:0] + end + attribute \src "libresoc.v:104353.3-104365.6" + process $proc$libresoc.v:104353$4158 + assign { } { } + assign { } { } + assign $0\dec62_upd[1:0] $1\dec62_upd[1:0] + attribute \src "libresoc.v:104354.5-104354.29" + switch \initial + attribute \src "libresoc.v:104354.9-104354.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_upd[1:0] 2'01 + case + assign $1\dec62_upd[1:0] 2'00 + end + sync always + update \dec62_upd $0\dec62_upd[1:0] + end + attribute \src "libresoc.v:104366.3-104378.6" + process $proc$libresoc.v:104366$4159 + assign { } { } + assign { } { } + assign $0\dec62_rc_sel[1:0] $1\dec62_rc_sel[1:0] + attribute \src "libresoc.v:104367.5-104367.29" + switch \initial + attribute \src "libresoc.v:104367.9-104367.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_rc_sel[1:0] 2'00 + case + assign $1\dec62_rc_sel[1:0] 2'00 + end + sync always + update \dec62_rc_sel $0\dec62_rc_sel[1:0] + end + attribute \src "libresoc.v:104379.3-104391.6" + process $proc$libresoc.v:104379$4160 + assign { } { } + assign { } { } + assign $0\dec62_cry_in[1:0] $1\dec62_cry_in[1:0] + attribute \src "libresoc.v:104380.5-104380.29" + switch \initial + attribute \src "libresoc.v:104380.9-104380.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_cry_in[1:0] 2'00 + case + assign $1\dec62_cry_in[1:0] 2'00 + end + sync always + update \dec62_cry_in $0\dec62_cry_in[1:0] + end + attribute \src "libresoc.v:104392.3-104404.6" + process $proc$libresoc.v:104392$4161 + assign { } { } + assign { } { } + assign $0\dec62_asmcode[7:0] $1\dec62_asmcode[7:0] + attribute \src "libresoc.v:104393.5-104393.29" + switch \initial + attribute \src "libresoc.v:104393.9-104393.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_asmcode[7:0] 8'10101100 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_asmcode[7:0] 8'10101111 + case + assign $1\dec62_asmcode[7:0] 8'00000000 + end + sync always + update \dec62_asmcode $0\dec62_asmcode[7:0] + end + attribute \src "libresoc.v:104405.3-104417.6" + process $proc$libresoc.v:104405$4162 + assign { } { } + assign { } { } + assign $0\dec62_inv_a[0:0] $1\dec62_inv_a[0:0] + attribute \src "libresoc.v:104406.5-104406.29" + switch \initial + attribute \src "libresoc.v:104406.9-104406.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_inv_a[0:0] 1'0 + case + assign $1\dec62_inv_a[0:0] 1'0 + end + sync always + update \dec62_inv_a $0\dec62_inv_a[0:0] + end + attribute \src "libresoc.v:104418.3-104430.6" + process $proc$libresoc.v:104418$4163 + assign { } { } + assign { } { } + assign $0\dec62_inv_out[0:0] $1\dec62_inv_out[0:0] + attribute \src "libresoc.v:104419.5-104419.29" + switch \initial + attribute \src "libresoc.v:104419.9-104419.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_inv_out[0:0] 1'0 + case + assign $1\dec62_inv_out[0:0] 1'0 + end + sync always + update \dec62_inv_out $0\dec62_inv_out[0:0] + end + attribute \src "libresoc.v:104431.3-104443.6" + process $proc$libresoc.v:104431$4164 + assign { } { } + assign { } { } + assign $0\dec62_cry_out[0:0] $1\dec62_cry_out[0:0] + attribute \src "libresoc.v:104432.5-104432.29" + switch \initial + attribute \src "libresoc.v:104432.9-104432.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_cry_out[0:0] 1'0 + case + assign $1\dec62_cry_out[0:0] 1'0 + end + sync always + update \dec62_cry_out $0\dec62_cry_out[0:0] + end + attribute \src "libresoc.v:104444.3-104456.6" + process $proc$libresoc.v:104444$4165 + assign { } { } + assign { } { } + assign $0\dec62_br[0:0] $1\dec62_br[0:0] + attribute \src "libresoc.v:104445.5-104445.29" + switch \initial + attribute \src "libresoc.v:104445.9-104445.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_br[0:0] 1'0 + case + assign $1\dec62_br[0:0] 1'0 + end + sync always + update \dec62_br $0\dec62_br[0:0] + end + attribute \src "libresoc.v:104457.3-104469.6" + process $proc$libresoc.v:104457$4166 + assign { } { } + assign { } { } + assign $0\dec62_sgn_ext[0:0] $1\dec62_sgn_ext[0:0] + attribute \src "libresoc.v:104458.5-104458.29" + switch \initial + attribute \src "libresoc.v:104458.9-104458.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_sgn_ext[0:0] 1'0 + case + assign $1\dec62_sgn_ext[0:0] 1'0 + end + sync always + update \dec62_sgn_ext $0\dec62_sgn_ext[0:0] + end + attribute \src "libresoc.v:104470.3-104482.6" + process $proc$libresoc.v:104470$4167 + assign { } { } + assign { } { } + assign $0\dec62_internal_op[6:0] $1\dec62_internal_op[6:0] + attribute \src "libresoc.v:104471.5-104471.29" + switch \initial + attribute \src "libresoc.v:104471.9-104471.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_internal_op[6:0] 7'0100110 + case + assign $1\dec62_internal_op[6:0] 7'0000000 + end + sync always + update \dec62_internal_op $0\dec62_internal_op[6:0] + end + attribute \src "libresoc.v:104483.3-104495.6" + process $proc$libresoc.v:104483$4168 + assign { } { } + assign { } { } + assign $0\dec62_rsrv[0:0] $1\dec62_rsrv[0:0] + attribute \src "libresoc.v:104484.5-104484.29" + switch \initial + attribute \src "libresoc.v:104484.9-104484.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_rsrv[0:0] 1'0 + case + assign $1\dec62_rsrv[0:0] 1'0 + end + sync always + update \dec62_rsrv $0\dec62_rsrv[0:0] + end + attribute \src "libresoc.v:104496.3-104508.6" + process $proc$libresoc.v:104496$4169 + assign { } { } + assign { } { } + assign $0\dec62_is_32b[0:0] $1\dec62_is_32b[0:0] + attribute \src "libresoc.v:104497.5-104497.29" + switch \initial + attribute \src "libresoc.v:104497.9-104497.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_is_32b[0:0] 1'0 + case + assign $1\dec62_is_32b[0:0] 1'0 + end + sync always + update \dec62_is_32b $0\dec62_is_32b[0:0] + end + attribute \src "libresoc.v:104509.3-104521.6" + process $proc$libresoc.v:104509$4170 + assign { } { } + assign { } { } + assign $0\dec62_sgn[0:0] $1\dec62_sgn[0:0] + attribute \src "libresoc.v:104510.5-104510.29" + switch \initial + attribute \src "libresoc.v:104510.9-104510.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_sgn[0:0] 1'0 + case + assign $1\dec62_sgn[0:0] 1'0 + end + sync always + update \dec62_sgn $0\dec62_sgn[0:0] + end + attribute \src "libresoc.v:104522.3-104534.6" + process $proc$libresoc.v:104522$4171 + assign { } { } + assign { } { } + assign $0\dec62_lk[0:0] $1\dec62_lk[0:0] + attribute \src "libresoc.v:104523.5-104523.29" + switch \initial + attribute \src "libresoc.v:104523.9-104523.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_lk[0:0] 1'0 + case + assign $1\dec62_lk[0:0] 1'0 + end + sync always + update \dec62_lk $0\dec62_lk[0:0] + end + attribute \src "libresoc.v:104535.3-104547.6" + process $proc$libresoc.v:104535$4172 + assign { } { } + assign { } { } + assign $0\dec62_sgl_pipe[0:0] $1\dec62_sgl_pipe[0:0] + attribute \src "libresoc.v:104536.5-104536.29" + switch \initial + attribute \src "libresoc.v:104536.9-104536.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_sgl_pipe[0:0] 1'1 + case + assign $1\dec62_sgl_pipe[0:0] 1'0 + end + sync always + update \dec62_sgl_pipe $0\dec62_sgl_pipe[0:0] + end + attribute \src "libresoc.v:104548.3-104560.6" + process $proc$libresoc.v:104548$4173 + assign { } { } + assign { } { } + assign $0\dec62_form[4:0] $1\dec62_form[4:0] + attribute \src "libresoc.v:104549.5-104549.29" + switch \initial + attribute \src "libresoc.v:104549.9-104549.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_form[4:0] 5'00101 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_form[4:0] 5'00101 + case + assign $1\dec62_form[4:0] 5'00000 + end + sync always + update \dec62_form $0\dec62_form[4:0] + end + attribute \src "libresoc.v:104561.3-104573.6" + process $proc$libresoc.v:104561$4174 + assign { } { } + assign { } { } + assign $0\dec62_in1_sel[2:0] $1\dec62_in1_sel[2:0] + attribute \src "libresoc.v:104562.5-104562.29" + switch \initial + attribute \src "libresoc.v:104562.9-104562.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_in1_sel[2:0] 3'010 + case + assign $1\dec62_in1_sel[2:0] 3'000 + end + sync always + update \dec62_in1_sel $0\dec62_in1_sel[2:0] + end + attribute \src "libresoc.v:104574.3-104586.6" + process $proc$libresoc.v:104574$4175 + assign { } { } + assign { } { } + assign $0\dec62_in2_sel[3:0] $1\dec62_in2_sel[3:0] + attribute \src "libresoc.v:104575.5-104575.29" + switch \initial + attribute \src "libresoc.v:104575.9-104575.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_in2_sel[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_in2_sel[3:0] 4'1000 + case + assign $1\dec62_in2_sel[3:0] 4'0000 + end + sync always + update \dec62_in2_sel $0\dec62_in2_sel[3:0] + end + attribute \src "libresoc.v:104587.3-104599.6" + process $proc$libresoc.v:104587$4176 + assign { } { } + assign { } { } + assign $0\dec62_in3_sel[1:0] $1\dec62_in3_sel[1:0] + attribute \src "libresoc.v:104588.5-104588.29" + switch \initial + attribute \src "libresoc.v:104588.9-104588.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_in3_sel[1:0] 2'01 + case + assign $1\dec62_in3_sel[1:0] 2'00 + end + sync always + update \dec62_in3_sel $0\dec62_in3_sel[1:0] + end + attribute \src "libresoc.v:104600.3-104612.6" + process $proc$libresoc.v:104600$4177 + assign { } { } + assign { } { } + assign $0\dec62_out_sel[1:0] $1\dec62_out_sel[1:0] + attribute \src "libresoc.v:104601.5-104601.29" + switch \initial + attribute \src "libresoc.v:104601.9-104601.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_out_sel[1:0] 2'00 + case + assign $1\dec62_out_sel[1:0] 2'00 + end + sync always + update \dec62_out_sel $0\dec62_out_sel[1:0] + end + attribute \src "libresoc.v:104613.3-104625.6" + process $proc$libresoc.v:104613$4178 + assign { } { } + assign { } { } + assign $0\dec62_cr_in[2:0] $1\dec62_cr_in[2:0] + attribute \src "libresoc.v:104614.5-104614.29" + switch \initial + attribute \src "libresoc.v:104614.9-104614.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_cr_in[2:0] 3'000 + case + assign $1\dec62_cr_in[2:0] 3'000 + end + sync always + update \dec62_cr_in $0\dec62_cr_in[2:0] + end + attribute \src "libresoc.v:104626.3-104638.6" + process $proc$libresoc.v:104626$4179 + assign { } { } + assign { } { } + assign $0\dec62_cr_out[2:0] $1\dec62_cr_out[2:0] + attribute \src "libresoc.v:104627.5-104627.29" + switch \initial + attribute \src "libresoc.v:104627.9-104627.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_cr_out[2:0] 3'000 + case + assign $1\dec62_cr_out[2:0] 3'000 + end + sync always + update \dec62_cr_out $0\dec62_cr_out[2:0] + end + connect \opcode_switch \opcode_in [1:0] +end +attribute \src "libresoc.v:104644.1-105177.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_ALU" +attribute \generator "nMigen" +module \dec_ALU + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 18 \ALU_ALU__data_len + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 output 3 \ALU_ALU__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 4 \ALU_ALU__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 5 \ALU_ALU__imm_data__ok + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 14 \ALU_ALU__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 19 \ALU_ALU__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 2 \ALU_ALU__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 10 \ALU_ALU__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 12 \ALU_ALU__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 16 \ALU_ALU__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 17 \ALU_ALU__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 8 \ALU_ALU__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 9 \ALU_ALU__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 15 \ALU_ALU__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 7 \ALU_ALU__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 6 \ALU_ALU__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 13 \ALU_ALU__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 11 \ALU_ALU__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + wire input 1 \bigendian + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_ALU_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_ALU_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_ALU_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 14 \dec_ALU_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_ALU_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_ALU_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 14 \dec_ALU_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 8 \dec_ALU_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 24 \dec_ALU_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire \dec_ALU_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_ALU_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire \dec_ALU_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_ALU_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 16 \dec_ALU_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 16 \dec_ALU_UI + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec_ALU_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec_ALU_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec_ALU_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec_ALU_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \dec_ALU_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec_ALU_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec_ALU_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 \dec_ALU_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec_ALU_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec_ALU_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec_ALU_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec_ALU_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec_ALU_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec_ALU_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 6 \dec_ALU_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \dec_XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \dec_X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \dec_X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:149" + wire \dec_ai_immz_out + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:148" + wire width 3 \dec_ai_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \dec_bi_imm_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_bi_imm_b_ok + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:216" + wire width 4 \dec_bi_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486" + wire width 32 \dec_cr_in_insn_in + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:485" + wire width 3 \dec_cr_in_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_cr_out_cr_bitfield_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:551" + wire width 32 \dec_cr_out_insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:549" + wire \dec_cr_out_rc_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:550" + wire width 3 \dec_cr_out_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_oe_oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_oe_oe_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" + wire width 2 \dec_oe_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \dec_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_rc_rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_rc_rc_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:405" + wire width 2 \dec_rc_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:406" + wire width 32 \insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:443" + wire width 32 \insn_in$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:442" + wire width 32 input 20 \raw_opcode_in + attribute \module_not_derived 1 + attribute \src "libresoc.v:105061.7-105098.4" + cell \dec \dec + connect \ALU_BA \dec_ALU_BA + connect \ALU_BB \dec_ALU_BB + connect \ALU_BC \dec_ALU_BC + connect \ALU_BD \dec_ALU_BD + connect \ALU_BI \dec_ALU_BI + connect \ALU_BT \dec_ALU_BT + connect \ALU_DS \dec_ALU_DS + connect \ALU_FXM \dec_ALU_FXM + connect \ALU_LI \dec_ALU_LI + connect \ALU_OE \dec_ALU_OE + connect \ALU_RA \dec_ALU_RA + connect \ALU_Rc \dec_ALU_Rc + connect \ALU_SH32 \dec_ALU_SH32 + connect \ALU_SI \dec_ALU_SI + connect \ALU_UI \dec_ALU_UI + connect \ALU_cr_in \dec_ALU_cr_in + connect \ALU_cr_out \dec_ALU_cr_out + connect \ALU_cry_in \dec_ALU_cry_in + connect \ALU_cry_out \dec_ALU_cry_out + connect \ALU_function_unit \dec_ALU_function_unit + connect \ALU_in1_sel \dec_ALU_in1_sel + connect \ALU_in2_sel \dec_ALU_in2_sel + connect \ALU_internal_op \dec_ALU_internal_op + connect \ALU_inv_a \dec_ALU_inv_a + connect \ALU_inv_out \dec_ALU_inv_out + connect \ALU_is_32b \dec_ALU_is_32b + connect \ALU_ldst_len \dec_ALU_ldst_len + connect \ALU_rc_sel \dec_ALU_rc_sel + connect \ALU_sgn \dec_ALU_sgn + connect \ALU_sh \dec_ALU_sh + connect \XL_BT \dec_XL_BT + connect \X_BF \dec_X_BF + connect \X_BFA \dec_X_BFA + connect \bigendian \bigendian + connect \opcode_in \dec_opcode_in + connect \raw_opcode_in \raw_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:105099.10-105103.4" + cell \dec_ai \dec_ai + connect \ALU_RA \dec_ALU_RA + connect \immz_out \dec_ai_immz_out + connect \sel_in \dec_ai_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:105104.10-105115.4" + cell \dec_bi \dec_bi + connect \ALU_BD \dec_ALU_BD + connect \ALU_DS \dec_ALU_DS + connect \ALU_LI \dec_ALU_LI + connect \ALU_SH32 \dec_ALU_SH32 + connect \ALU_SI \dec_ALU_SI + connect \ALU_UI \dec_ALU_UI + connect \ALU_sh \dec_ALU_sh + connect \imm_b \dec_bi_imm_b + connect \imm_b_ok \dec_bi_imm_b_ok + connect \sel_in \dec_bi_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:105116.13-105127.4" + cell \dec_cr_in \dec_cr_in + connect \ALU_BA \dec_ALU_BA + connect \ALU_BB \dec_ALU_BB + connect \ALU_BC \dec_ALU_BC + connect \ALU_BI \dec_ALU_BI + connect \ALU_BT \dec_ALU_BT + connect \ALU_FXM \dec_ALU_FXM + connect \ALU_internal_op \dec_ALU_internal_op + connect \X_BFA \dec_X_BFA + connect \insn_in \dec_cr_in_insn_in + connect \sel_in \dec_cr_in_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:105128.14-105137.4" + cell \dec_cr_out \dec_cr_out + connect \ALU_FXM \dec_ALU_FXM + connect \ALU_internal_op \dec_ALU_internal_op + connect \XL_BT \dec_XL_BT + connect \X_BF \dec_X_BF + connect \cr_bitfield_ok \dec_cr_out_cr_bitfield_ok + connect \insn_in \dec_cr_out_insn_in + connect \rc_in \dec_cr_out_rc_in + connect \sel_in \dec_cr_out_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:105138.10-105144.4" + cell \dec_oe \dec_oe + connect \ALU_OE \dec_ALU_OE + connect \ALU_internal_op \dec_ALU_internal_op + connect \oe \dec_oe_oe + connect \oe_ok \dec_oe_oe_ok + connect \sel_in \dec_oe_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:105145.10-105150.4" + cell \dec_rc \dec_rc + connect \ALU_Rc \dec_ALU_Rc + connect \rc \dec_rc_rc + connect \rc_ok \dec_rc_rc_ok + connect \sel_in \dec_rc_sel_in + end + connect \ALU_ALU__is_signed \dec_ALU_sgn + connect \ALU_ALU__is_32bit \dec_ALU_is_32b + connect \ALU_ALU__output_carry \dec_ALU_cry_out + connect \ALU_ALU__input_carry \dec_ALU_cry_in + connect \ALU_ALU__invert_out \dec_ALU_inv_out + connect \ALU_ALU__invert_in \dec_ALU_inv_a + connect \ALU_ALU__data_len \dec_ALU_ldst_len + connect \ALU_ALU__write_cr0 \dec_cr_out_cr_bitfield_ok + connect { \ALU_ALU__oe__ok \ALU_ALU__oe__oe } { \dec_oe_oe_ok \dec_oe_oe } + connect { \ALU_ALU__rc__ok \ALU_ALU__rc__rc } { \dec_rc_rc_ok \dec_rc_rc } + connect { \ALU_ALU__imm_data__ok \ALU_ALU__imm_data__data } { \dec_bi_imm_b_ok \dec_bi_imm_b } + connect \dec_bi_sel_in \dec_ALU_in2_sel + connect \ALU_ALU__zero_a \dec_ai_immz_out + connect \dec_ai_sel_in \dec_ALU_in1_sel + connect \ALU_ALU__fn_unit \dec_ALU_function_unit + connect \ALU_ALU__insn_type \dec_ALU_internal_op + connect \dec_cr_out_rc_in \dec_rc_rc + connect \dec_cr_out_sel_in \dec_ALU_cr_out + connect \dec_cr_in_sel_in \dec_ALU_cr_in + connect \dec_oe_sel_in \dec_ALU_rc_sel + connect \dec_rc_sel_in \dec_ALU_rc_sel + connect \dec_cr_out_insn_in \dec_opcode_in + connect \dec_cr_in_insn_in \dec_opcode_in + connect \insn_in$1 \dec_opcode_in + connect \insn_in \dec_opcode_in + connect \ALU_ALU__insn \dec_opcode_in +end +attribute \src "libresoc.v:105181.1-105633.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_BRANCH" +attribute \generator "nMigen" +module \dec_BRANCH + attribute \src "libresoc.v:105607.3-105616.6" + wire $0\BRANCH_BRANCH__lk[0:0] + attribute \src "libresoc.v:105182.7-105182.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:105607.3-105616.6" + wire $1\BRANCH_BRANCH__lk[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 3 \BRANCH_BRANCH__cia + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 output 5 \BRANCH_BRANCH__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 7 \BRANCH_BRANCH__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 8 \BRANCH_BRANCH__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 6 \BRANCH_BRANCH__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 4 \BRANCH_BRANCH__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 10 \BRANCH_BRANCH__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 9 \BRANCH_BRANCH__lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + wire input 2 \bigendian + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:8" + wire width 64 input 11 \core_pc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_BRANCH_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_BRANCH_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_BRANCH_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 14 \dec_BRANCH_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_BRANCH_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_BRANCH_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 14 \dec_BRANCH_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 8 \dec_BRANCH_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 24 \dec_BRANCH_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire \dec_BRANCH_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire \dec_BRANCH_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire \dec_BRANCH_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_BRANCH_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 16 \dec_BRANCH_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 16 \dec_BRANCH_UI + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec_BRANCH_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec_BRANCH_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \dec_BRANCH_function_unit + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec_BRANCH_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 \dec_BRANCH_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec_BRANCH_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec_BRANCH_lk + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec_BRANCH_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 6 \dec_BRANCH_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \dec_XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \dec_X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \dec_X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \dec_bi_imm_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_bi_imm_b_ok + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:216" + wire width 4 \dec_bi_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486" + wire width 32 \dec_cr_in_insn_in + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:485" + wire width 3 \dec_cr_in_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:551" + wire width 32 \dec_cr_out_insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:549" + wire \dec_cr_out_rc_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:550" + wire width 3 \dec_cr_out_sel_in + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" + wire width 2 \dec_oe_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \dec_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_rc_rc + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:405" + wire width 2 \dec_rc_sel_in + attribute \src "libresoc.v:105182.7-105182.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:406" + wire width 32 \insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:443" + wire width 32 \insn_in$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:442" + wire width 32 input 1 \raw_opcode_in + attribute \module_not_derived 1 + attribute \src "libresoc.v:105532.13-105563.4" + cell \dec$144 \dec + connect \BRANCH_BA \dec_BRANCH_BA + connect \BRANCH_BB \dec_BRANCH_BB + connect \BRANCH_BC \dec_BRANCH_BC + connect \BRANCH_BD \dec_BRANCH_BD + connect \BRANCH_BI \dec_BRANCH_BI + connect \BRANCH_BT \dec_BRANCH_BT + connect \BRANCH_DS \dec_BRANCH_DS + connect \BRANCH_FXM \dec_BRANCH_FXM + connect \BRANCH_LI \dec_BRANCH_LI + connect \BRANCH_LK \dec_BRANCH_LK + connect \BRANCH_OE \dec_BRANCH_OE + connect \BRANCH_Rc \dec_BRANCH_Rc + connect \BRANCH_SH32 \dec_BRANCH_SH32 + connect \BRANCH_SI \dec_BRANCH_SI + connect \BRANCH_UI \dec_BRANCH_UI + connect \BRANCH_cr_in \dec_BRANCH_cr_in + connect \BRANCH_cr_out \dec_BRANCH_cr_out + connect \BRANCH_function_unit \dec_BRANCH_function_unit + connect \BRANCH_in2_sel \dec_BRANCH_in2_sel + connect \BRANCH_internal_op \dec_BRANCH_internal_op + connect \BRANCH_is_32b \dec_BRANCH_is_32b + connect \BRANCH_lk \dec_BRANCH_lk + connect \BRANCH_rc_sel \dec_BRANCH_rc_sel + connect \BRANCH_sh \dec_BRANCH_sh + connect \XL_BT \dec_XL_BT + connect \X_BF \dec_X_BF + connect \X_BFA \dec_X_BFA + connect \bigendian \bigendian + connect \opcode_in \dec_opcode_in + connect \raw_opcode_in \raw_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:105564.16-105575.4" + cell \dec_bi$151 \dec_bi + connect \BRANCH_BD \dec_BRANCH_BD + connect \BRANCH_DS \dec_BRANCH_DS + connect \BRANCH_LI \dec_BRANCH_LI + connect \BRANCH_SH32 \dec_BRANCH_SH32 + connect \BRANCH_SI \dec_BRANCH_SI + connect \BRANCH_UI \dec_BRANCH_UI + connect \BRANCH_sh \dec_BRANCH_sh + connect \imm_b \dec_bi_imm_b + connect \imm_b_ok \dec_bi_imm_b_ok + connect \sel_in \dec_bi_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:105576.19-105587.4" + cell \dec_cr_in$147 \dec_cr_in + connect \BRANCH_BA \dec_BRANCH_BA + connect \BRANCH_BB \dec_BRANCH_BB + connect \BRANCH_BC \dec_BRANCH_BC + connect \BRANCH_BI \dec_BRANCH_BI + connect \BRANCH_BT \dec_BRANCH_BT + connect \BRANCH_FXM \dec_BRANCH_FXM + connect \BRANCH_internal_op \dec_BRANCH_internal_op + connect \X_BFA \dec_X_BFA + connect \insn_in \dec_cr_in_insn_in + connect \sel_in \dec_cr_in_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:105588.20-105596.4" + cell \dec_cr_out$149 \dec_cr_out + connect \BRANCH_FXM \dec_BRANCH_FXM + connect \BRANCH_internal_op \dec_BRANCH_internal_op + connect \XL_BT \dec_XL_BT + connect \X_BF \dec_X_BF + connect \insn_in \dec_cr_out_insn_in + connect \rc_in \dec_cr_out_rc_in + connect \sel_in \dec_cr_out_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:105597.16-105601.4" + cell \dec_oe$146 \dec_oe + connect \BRANCH_OE \dec_BRANCH_OE + connect \BRANCH_internal_op \dec_BRANCH_internal_op + connect \sel_in \dec_oe_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:105602.16-105606.4" + cell \dec_rc$145 \dec_rc + connect \BRANCH_Rc \dec_BRANCH_Rc + connect \rc \dec_rc_rc + connect \sel_in \dec_rc_sel_in + end + attribute \src "libresoc.v:105182.7-105182.20" + process $proc$libresoc.v:105182$4182 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:105607.3-105616.6" + process $proc$libresoc.v:105607$4181 + assign { } { } + assign { } { } + assign $0\BRANCH_BRANCH__lk[0:0] $1\BRANCH_BRANCH__lk[0:0] + attribute \src "libresoc.v:105608.5-105608.29" + switch \initial + attribute \src "libresoc.v:105608.9-105608.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:758" + switch \dec_BRANCH_lk + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\BRANCH_BRANCH__lk[0:0] \dec_BRANCH_LK + case + assign $1\BRANCH_BRANCH__lk[0:0] 1'0 + end + sync always + update \BRANCH_BRANCH__lk $0\BRANCH_BRANCH__lk[0:0] + end + connect \BRANCH_BRANCH__is_32bit \dec_BRANCH_is_32b + connect { \BRANCH_BRANCH__imm_data__ok \BRANCH_BRANCH__imm_data__data } { \dec_bi_imm_b_ok \dec_bi_imm_b } + connect \dec_bi_sel_in \dec_BRANCH_in2_sel + connect \BRANCH_BRANCH__fn_unit \dec_BRANCH_function_unit + connect \BRANCH_BRANCH__insn_type \dec_BRANCH_internal_op + connect \BRANCH_BRANCH__cia \core_pc + connect \dec_cr_out_rc_in \dec_rc_rc + connect \dec_cr_out_sel_in \dec_BRANCH_cr_out + connect \dec_cr_in_sel_in \dec_BRANCH_cr_in + connect \dec_oe_sel_in \dec_BRANCH_rc_sel + connect \dec_rc_sel_in \dec_BRANCH_rc_sel + connect \dec_cr_out_insn_in \dec_opcode_in + connect \dec_cr_in_insn_in \dec_opcode_in + connect \insn_in$1 \dec_opcode_in + connect \insn_in \dec_opcode_in + connect \BRANCH_BRANCH__insn \dec_opcode_in +end +attribute \src "libresoc.v:105637.1-105980.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_CR" +attribute \generator "nMigen" +module \dec_CR + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 output 3 \CR_CR__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 4 \CR_CR__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 2 \CR_CR__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + wire input 1 \bigendian + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_CR_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_CR_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_CR_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_CR_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_CR_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 8 \dec_CR_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire \dec_CR_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire \dec_CR_Rc + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec_CR_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec_CR_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \dec_CR_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 \dec_CR_internal_op + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec_CR_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \dec_XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \dec_X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \dec_X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486" + wire width 32 \dec_cr_in_insn_in + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:485" + wire width 3 \dec_cr_in_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:551" + wire width 32 \dec_cr_out_insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:549" + wire \dec_cr_out_rc_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:550" + wire width 3 \dec_cr_out_sel_in + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" + wire width 2 \dec_oe_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \dec_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_rc_rc + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:405" + wire width 2 \dec_rc_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:406" + wire width 32 \insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:443" + wire width 32 \insn_in$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:442" + wire width 32 input 5 \raw_opcode_in + attribute \module_not_derived 1 + attribute \src "libresoc.v:105916.13-105936.4" + cell \dec$137 \dec + connect \CR_BA \dec_CR_BA + connect \CR_BB \dec_CR_BB + connect \CR_BC \dec_CR_BC + connect \CR_BI \dec_CR_BI + connect \CR_BT \dec_CR_BT + connect \CR_FXM \dec_CR_FXM + connect \CR_OE \dec_CR_OE + connect \CR_Rc \dec_CR_Rc + connect \CR_cr_in \dec_CR_cr_in + connect \CR_cr_out \dec_CR_cr_out + connect \CR_function_unit \dec_CR_function_unit + connect \CR_internal_op \dec_CR_internal_op + connect \CR_rc_sel \dec_CR_rc_sel + connect \XL_BT \dec_XL_BT + connect \X_BF \dec_X_BF + connect \X_BFA \dec_X_BFA + connect \bigendian \bigendian + connect \opcode_in \dec_opcode_in + connect \raw_opcode_in \raw_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:105937.19-105948.4" + cell \dec_cr_in$140 \dec_cr_in + connect \CR_BA \dec_CR_BA + connect \CR_BB \dec_CR_BB + connect \CR_BC \dec_CR_BC + connect \CR_BI \dec_CR_BI + connect \CR_BT \dec_CR_BT + connect \CR_FXM \dec_CR_FXM + connect \CR_internal_op \dec_CR_internal_op + connect \X_BFA \dec_X_BFA + connect \insn_in \dec_cr_in_insn_in + connect \sel_in \dec_cr_in_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:105949.20-105957.4" + cell \dec_cr_out$142 \dec_cr_out + connect \CR_FXM \dec_CR_FXM + connect \CR_internal_op \dec_CR_internal_op + connect \XL_BT \dec_XL_BT + connect \X_BF \dec_X_BF + connect \insn_in \dec_cr_out_insn_in + connect \rc_in \dec_cr_out_rc_in + connect \sel_in \dec_cr_out_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:105958.16-105962.4" + cell \dec_oe$139 \dec_oe + connect \CR_OE \dec_CR_OE + connect \CR_internal_op \dec_CR_internal_op + connect \sel_in \dec_oe_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:105963.16-105967.4" + cell \dec_rc$138 \dec_rc + connect \CR_Rc \dec_CR_Rc + connect \rc \dec_rc_rc + connect \sel_in \dec_rc_sel_in + end + connect \CR_CR__fn_unit \dec_CR_function_unit + connect \CR_CR__insn_type \dec_CR_internal_op + connect \dec_cr_out_rc_in \dec_rc_rc + connect \dec_cr_out_sel_in \dec_CR_cr_out + connect \dec_cr_in_sel_in \dec_CR_cr_in + connect \dec_oe_sel_in \dec_CR_rc_sel + connect \dec_rc_sel_in \dec_CR_rc_sel + connect \dec_cr_out_insn_in \dec_opcode_in + connect \dec_cr_in_insn_in \dec_opcode_in + connect \insn_in$1 \dec_opcode_in + connect \insn_in \dec_opcode_in + connect \CR_CR__insn \dec_opcode_in +end +attribute \src "libresoc.v:105984.1-106517.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_DIV" +attribute \generator "nMigen" +module \dec_DIV + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 18 \DIV_DIV__data_len + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 output 3 \DIV_DIV__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 4 \DIV_DIV__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 5 \DIV_DIV__imm_data__ok + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 12 \DIV_DIV__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 19 \DIV_DIV__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 2 \DIV_DIV__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 10 \DIV_DIV__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 13 \DIV_DIV__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 16 \DIV_DIV__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 17 \DIV_DIV__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 8 \DIV_DIV__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 9 \DIV_DIV__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 15 \DIV_DIV__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 7 \DIV_DIV__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 6 \DIV_DIV__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 14 \DIV_DIV__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 11 \DIV_DIV__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + wire input 1 \bigendian + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_DIV_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_DIV_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_DIV_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 14 \dec_DIV_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_DIV_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_DIV_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 14 \dec_DIV_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 8 \dec_DIV_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 24 \dec_DIV_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire \dec_DIV_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_DIV_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire \dec_DIV_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_DIV_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 16 \dec_DIV_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 16 \dec_DIV_UI + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec_DIV_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec_DIV_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec_DIV_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec_DIV_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \dec_DIV_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec_DIV_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec_DIV_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 \dec_DIV_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec_DIV_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec_DIV_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec_DIV_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec_DIV_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec_DIV_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec_DIV_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 6 \dec_DIV_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \dec_XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \dec_X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \dec_X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:149" + wire \dec_ai_immz_out + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:148" + wire width 3 \dec_ai_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \dec_bi_imm_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_bi_imm_b_ok + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:216" + wire width 4 \dec_bi_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486" + wire width 32 \dec_cr_in_insn_in + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:485" + wire width 3 \dec_cr_in_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_cr_out_cr_bitfield_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:551" + wire width 32 \dec_cr_out_insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:549" + wire \dec_cr_out_rc_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:550" + wire width 3 \dec_cr_out_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_oe_oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_oe_oe_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" + wire width 2 \dec_oe_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \dec_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_rc_rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_rc_rc_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:405" + wire width 2 \dec_rc_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:406" + wire width 32 \insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:443" + wire width 32 \insn_in$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:442" + wire width 32 input 20 \raw_opcode_in + attribute \module_not_derived 1 + attribute \src "libresoc.v:106401.13-106438.4" + cell \dec$168 \dec + connect \DIV_BA \dec_DIV_BA + connect \DIV_BB \dec_DIV_BB + connect \DIV_BC \dec_DIV_BC + connect \DIV_BD \dec_DIV_BD + connect \DIV_BI \dec_DIV_BI + connect \DIV_BT \dec_DIV_BT + connect \DIV_DS \dec_DIV_DS + connect \DIV_FXM \dec_DIV_FXM + connect \DIV_LI \dec_DIV_LI + connect \DIV_OE \dec_DIV_OE + connect \DIV_RA \dec_DIV_RA + connect \DIV_Rc \dec_DIV_Rc + connect \DIV_SH32 \dec_DIV_SH32 + connect \DIV_SI \dec_DIV_SI + connect \DIV_UI \dec_DIV_UI + connect \DIV_cr_in \dec_DIV_cr_in + connect \DIV_cr_out \dec_DIV_cr_out + connect \DIV_cry_in \dec_DIV_cry_in + connect \DIV_cry_out \dec_DIV_cry_out + connect \DIV_function_unit \dec_DIV_function_unit + connect \DIV_in1_sel \dec_DIV_in1_sel + connect \DIV_in2_sel \dec_DIV_in2_sel + connect \DIV_internal_op \dec_DIV_internal_op + connect \DIV_inv_a \dec_DIV_inv_a + connect \DIV_inv_out \dec_DIV_inv_out + connect \DIV_is_32b \dec_DIV_is_32b + connect \DIV_ldst_len \dec_DIV_ldst_len + connect \DIV_rc_sel \dec_DIV_rc_sel + connect \DIV_sgn \dec_DIV_sgn + connect \DIV_sh \dec_DIV_sh + connect \XL_BT \dec_XL_BT + connect \X_BF \dec_X_BF + connect \X_BFA \dec_X_BFA + connect \bigendian \bigendian + connect \opcode_in \dec_opcode_in + connect \raw_opcode_in \raw_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:106439.16-106443.4" + cell \dec_ai$175 \dec_ai + connect \DIV_RA \dec_DIV_RA + connect \immz_out \dec_ai_immz_out + connect \sel_in \dec_ai_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:106444.16-106455.4" + cell \dec_bi$176 \dec_bi + connect \DIV_BD \dec_DIV_BD + connect \DIV_DS \dec_DIV_DS + connect \DIV_LI \dec_DIV_LI + connect \DIV_SH32 \dec_DIV_SH32 + connect \DIV_SI \dec_DIV_SI + connect \DIV_UI \dec_DIV_UI + connect \DIV_sh \dec_DIV_sh + connect \imm_b \dec_bi_imm_b + connect \imm_b_ok \dec_bi_imm_b_ok + connect \sel_in \dec_bi_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:106456.19-106467.4" + cell \dec_cr_in$171 \dec_cr_in + connect \DIV_BA \dec_DIV_BA + connect \DIV_BB \dec_DIV_BB + connect \DIV_BC \dec_DIV_BC + connect \DIV_BI \dec_DIV_BI + connect \DIV_BT \dec_DIV_BT + connect \DIV_FXM \dec_DIV_FXM + connect \DIV_internal_op \dec_DIV_internal_op + connect \X_BFA \dec_X_BFA + connect \insn_in \dec_cr_in_insn_in + connect \sel_in \dec_cr_in_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:106468.20-106477.4" + cell \dec_cr_out$173 \dec_cr_out + connect \DIV_FXM \dec_DIV_FXM + connect \DIV_internal_op \dec_DIV_internal_op + connect \XL_BT \dec_XL_BT + connect \X_BF \dec_X_BF + connect \cr_bitfield_ok \dec_cr_out_cr_bitfield_ok + connect \insn_in \dec_cr_out_insn_in + connect \rc_in \dec_cr_out_rc_in + connect \sel_in \dec_cr_out_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:106478.16-106484.4" + cell \dec_oe$170 \dec_oe + connect \DIV_OE \dec_DIV_OE + connect \DIV_internal_op \dec_DIV_internal_op + connect \oe \dec_oe_oe + connect \oe_ok \dec_oe_oe_ok + connect \sel_in \dec_oe_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:106485.16-106490.4" + cell \dec_rc$169 \dec_rc + connect \DIV_Rc \dec_DIV_Rc + connect \rc \dec_rc_rc + connect \rc_ok \dec_rc_rc_ok + connect \sel_in \dec_rc_sel_in + end + connect \DIV_DIV__is_signed \dec_DIV_sgn + connect \DIV_DIV__is_32bit \dec_DIV_is_32b + connect \DIV_DIV__output_carry \dec_DIV_cry_out + connect \DIV_DIV__input_carry \dec_DIV_cry_in + connect \DIV_DIV__invert_out \dec_DIV_inv_out + connect \DIV_DIV__invert_in \dec_DIV_inv_a + connect \DIV_DIV__data_len \dec_DIV_ldst_len + connect \DIV_DIV__write_cr0 \dec_cr_out_cr_bitfield_ok + connect { \DIV_DIV__oe__ok \DIV_DIV__oe__oe } { \dec_oe_oe_ok \dec_oe_oe } + connect { \DIV_DIV__rc__ok \DIV_DIV__rc__rc } { \dec_rc_rc_ok \dec_rc_rc } + connect { \DIV_DIV__imm_data__ok \DIV_DIV__imm_data__data } { \dec_bi_imm_b_ok \dec_bi_imm_b } + connect \dec_bi_sel_in \dec_DIV_in2_sel + connect \DIV_DIV__zero_a \dec_ai_immz_out + connect \dec_ai_sel_in \dec_DIV_in1_sel + connect \DIV_DIV__fn_unit \dec_DIV_function_unit + connect \DIV_DIV__insn_type \dec_DIV_internal_op + connect \dec_cr_out_rc_in \dec_rc_rc + connect \dec_cr_out_sel_in \dec_DIV_cr_out + connect \dec_cr_in_sel_in \dec_DIV_cr_in + connect \dec_oe_sel_in \dec_DIV_rc_sel + connect \dec_rc_sel_in \dec_DIV_rc_sel + connect \dec_cr_out_insn_in \dec_opcode_in + connect \dec_cr_in_insn_in \dec_opcode_in + connect \insn_in$1 \dec_opcode_in + connect \insn_in \dec_opcode_in + connect \DIV_DIV__insn \dec_opcode_in +end +attribute \src "libresoc.v:106521.1-107044.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_LDST" +attribute \generator "nMigen" +module \dec_LDST + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 14 \LDST_LDST__byte_reverse + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 13 \LDST_LDST__data_len + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 output 3 \LDST_LDST__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 4 \LDST_LDST__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 5 \LDST_LDST__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 17 \LDST_LDST__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 2 \LDST_LDST__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 11 \LDST_LDST__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 12 \LDST_LDST__is_signed + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 16 \LDST_LDST__ldst_mode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 9 \LDST_LDST__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 10 \LDST_LDST__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 8 \LDST_LDST__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 7 \LDST_LDST__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 15 \LDST_LDST__sign_extend + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 6 \LDST_LDST__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + wire input 1 \bigendian + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_LDST_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_LDST_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_LDST_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 14 \dec_LDST_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_LDST_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_LDST_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 14 \dec_LDST_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 8 \dec_LDST_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 24 \dec_LDST_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire \dec_LDST_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_LDST_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire \dec_LDST_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_LDST_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 16 \dec_LDST_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 16 \dec_LDST_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec_LDST_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec_LDST_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec_LDST_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \dec_LDST_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec_LDST_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec_LDST_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 \dec_LDST_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec_LDST_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec_LDST_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec_LDST_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec_LDST_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec_LDST_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 6 \dec_LDST_sh + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec_LDST_upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \dec_XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \dec_X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \dec_X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:149" + wire \dec_ai_immz_out + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:148" + wire width 3 \dec_ai_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \dec_bi_imm_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_bi_imm_b_ok + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:216" + wire width 4 \dec_bi_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486" + wire width 32 \dec_cr_in_insn_in + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:485" + wire width 3 \dec_cr_in_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:551" + wire width 32 \dec_cr_out_insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:549" + wire \dec_cr_out_rc_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:550" + wire width 3 \dec_cr_out_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_oe_oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_oe_oe_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" + wire width 2 \dec_oe_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \dec_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_rc_rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_rc_rc_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:405" + wire width 2 \dec_rc_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:406" + wire width 32 \insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:443" + wire width 32 \insn_in$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:442" + wire width 32 input 18 \raw_opcode_in + attribute \module_not_derived 1 + attribute \src "libresoc.v:106932.13-106968.4" + cell \dec$193 \dec + connect \LDST_BA \dec_LDST_BA + connect \LDST_BB \dec_LDST_BB + connect \LDST_BC \dec_LDST_BC + connect \LDST_BD \dec_LDST_BD + connect \LDST_BI \dec_LDST_BI + connect \LDST_BT \dec_LDST_BT + connect \LDST_DS \dec_LDST_DS + connect \LDST_FXM \dec_LDST_FXM + connect \LDST_LI \dec_LDST_LI + connect \LDST_OE \dec_LDST_OE + connect \LDST_RA \dec_LDST_RA + connect \LDST_Rc \dec_LDST_Rc + connect \LDST_SH32 \dec_LDST_SH32 + connect \LDST_SI \dec_LDST_SI + connect \LDST_UI \dec_LDST_UI + connect \LDST_br \dec_LDST_br + connect \LDST_cr_in \dec_LDST_cr_in + connect \LDST_cr_out \dec_LDST_cr_out + connect \LDST_function_unit \dec_LDST_function_unit + connect \LDST_in1_sel \dec_LDST_in1_sel + connect \LDST_in2_sel \dec_LDST_in2_sel + connect \LDST_internal_op \dec_LDST_internal_op + connect \LDST_is_32b \dec_LDST_is_32b + connect \LDST_ldst_len \dec_LDST_ldst_len + connect \LDST_rc_sel \dec_LDST_rc_sel + connect \LDST_sgn \dec_LDST_sgn + connect \LDST_sgn_ext \dec_LDST_sgn_ext + connect \LDST_sh \dec_LDST_sh + connect \LDST_upd \dec_LDST_upd + connect \XL_BT \dec_XL_BT + connect \X_BF \dec_X_BF + connect \X_BFA \dec_X_BFA + connect \bigendian \bigendian + connect \opcode_in \dec_opcode_in + connect \raw_opcode_in \raw_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:106969.16-106973.4" + cell \dec_ai$200 \dec_ai + connect \LDST_RA \dec_LDST_RA + connect \immz_out \dec_ai_immz_out + connect \sel_in \dec_ai_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:106974.16-106985.4" + cell \dec_bi$201 \dec_bi + connect \LDST_BD \dec_LDST_BD + connect \LDST_DS \dec_LDST_DS + connect \LDST_LI \dec_LDST_LI + connect \LDST_SH32 \dec_LDST_SH32 + connect \LDST_SI \dec_LDST_SI + connect \LDST_UI \dec_LDST_UI + connect \LDST_sh \dec_LDST_sh + connect \imm_b \dec_bi_imm_b + connect \imm_b_ok \dec_bi_imm_b_ok + connect \sel_in \dec_bi_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:106986.19-106997.4" + cell \dec_cr_in$196 \dec_cr_in + connect \LDST_BA \dec_LDST_BA + connect \LDST_BB \dec_LDST_BB + connect \LDST_BC \dec_LDST_BC + connect \LDST_BI \dec_LDST_BI + connect \LDST_BT \dec_LDST_BT + connect \LDST_FXM \dec_LDST_FXM + connect \LDST_internal_op \dec_LDST_internal_op + connect \X_BFA \dec_X_BFA + connect \insn_in \dec_cr_in_insn_in + connect \sel_in \dec_cr_in_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:106998.20-107006.4" + cell \dec_cr_out$198 \dec_cr_out + connect \LDST_FXM \dec_LDST_FXM + connect \LDST_internal_op \dec_LDST_internal_op + connect \XL_BT \dec_XL_BT + connect \X_BF \dec_X_BF + connect \insn_in \dec_cr_out_insn_in + connect \rc_in \dec_cr_out_rc_in + connect \sel_in \dec_cr_out_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:107007.16-107013.4" + cell \dec_oe$195 \dec_oe + connect \LDST_OE \dec_LDST_OE + connect \LDST_internal_op \dec_LDST_internal_op + connect \oe \dec_oe_oe + connect \oe_ok \dec_oe_oe_ok + connect \sel_in \dec_oe_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:107014.16-107019.4" + cell \dec_rc$194 \dec_rc + connect \LDST_Rc \dec_LDST_Rc + connect \rc \dec_rc_rc + connect \rc_ok \dec_rc_rc_ok + connect \sel_in \dec_rc_sel_in + end + connect \LDST_LDST__ldst_mode \dec_LDST_upd + connect \LDST_LDST__sign_extend \dec_LDST_sgn_ext + connect \LDST_LDST__byte_reverse \dec_LDST_br + connect \LDST_LDST__is_signed \dec_LDST_sgn + connect \LDST_LDST__is_32bit \dec_LDST_is_32b + connect \LDST_LDST__data_len \dec_LDST_ldst_len + connect { \LDST_LDST__oe__ok \LDST_LDST__oe__oe } { \dec_oe_oe_ok \dec_oe_oe } + connect { \LDST_LDST__rc__ok \LDST_LDST__rc__rc } { \dec_rc_rc_ok \dec_rc_rc } + connect { \LDST_LDST__imm_data__ok \LDST_LDST__imm_data__data } { \dec_bi_imm_b_ok \dec_bi_imm_b } + connect \dec_bi_sel_in \dec_LDST_in2_sel + connect \LDST_LDST__zero_a \dec_ai_immz_out + connect \dec_ai_sel_in \dec_LDST_in1_sel + connect \LDST_LDST__fn_unit \dec_LDST_function_unit + connect \LDST_LDST__insn_type \dec_LDST_internal_op + connect \dec_cr_out_rc_in \dec_rc_rc + connect \dec_cr_out_sel_in \dec_LDST_cr_out + connect \dec_cr_in_sel_in \dec_LDST_cr_in + connect \dec_oe_sel_in \dec_LDST_rc_sel + connect \dec_rc_sel_in \dec_LDST_rc_sel + connect \dec_cr_out_insn_in \dec_opcode_in + connect \dec_cr_in_insn_in \dec_opcode_in + connect \insn_in$1 \dec_opcode_in + connect \insn_in \dec_opcode_in + connect \LDST_LDST__insn \dec_opcode_in +end +attribute \src "libresoc.v:107048.1-107581.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_LOGICAL" +attribute \generator "nMigen" +module \dec_LOGICAL + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 18 \LOGICAL_LOGICAL__data_len + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 output 3 \LOGICAL_LOGICAL__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 4 \LOGICAL_LOGICAL__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 5 \LOGICAL_LOGICAL__imm_data__ok + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 12 \LOGICAL_LOGICAL__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 19 \LOGICAL_LOGICAL__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 2 \LOGICAL_LOGICAL__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 10 \LOGICAL_LOGICAL__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 13 \LOGICAL_LOGICAL__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 16 \LOGICAL_LOGICAL__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 17 \LOGICAL_LOGICAL__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 8 \LOGICAL_LOGICAL__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 9 \LOGICAL_LOGICAL__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 15 \LOGICAL_LOGICAL__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 7 \LOGICAL_LOGICAL__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 6 \LOGICAL_LOGICAL__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 14 \LOGICAL_LOGICAL__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 11 \LOGICAL_LOGICAL__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + wire input 1 \bigendian + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_LOGICAL_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_LOGICAL_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_LOGICAL_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 14 \dec_LOGICAL_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_LOGICAL_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_LOGICAL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 14 \dec_LOGICAL_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 8 \dec_LOGICAL_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 24 \dec_LOGICAL_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire \dec_LOGICAL_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_LOGICAL_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire \dec_LOGICAL_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_LOGICAL_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 16 \dec_LOGICAL_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 16 \dec_LOGICAL_UI + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec_LOGICAL_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec_LOGICAL_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec_LOGICAL_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec_LOGICAL_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \dec_LOGICAL_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec_LOGICAL_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec_LOGICAL_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 \dec_LOGICAL_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec_LOGICAL_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec_LOGICAL_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec_LOGICAL_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec_LOGICAL_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec_LOGICAL_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec_LOGICAL_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 6 \dec_LOGICAL_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \dec_XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \dec_X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \dec_X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:149" + wire \dec_ai_immz_out + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:148" + wire width 3 \dec_ai_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \dec_bi_imm_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_bi_imm_b_ok + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:216" + wire width 4 \dec_bi_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486" + wire width 32 \dec_cr_in_insn_in + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:485" + wire width 3 \dec_cr_in_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_cr_out_cr_bitfield_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:551" + wire width 32 \dec_cr_out_insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:549" + wire \dec_cr_out_rc_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:550" + wire width 3 \dec_cr_out_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_oe_oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_oe_oe_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" + wire width 2 \dec_oe_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \dec_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_rc_rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_rc_rc_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:405" + wire width 2 \dec_rc_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:406" + wire width 32 \insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:443" + wire width 32 \insn_in$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:442" + wire width 32 input 20 \raw_opcode_in + attribute \module_not_derived 1 + attribute \src "libresoc.v:107465.13-107502.4" + cell \dec$152 \dec + connect \LOGICAL_BA \dec_LOGICAL_BA + connect \LOGICAL_BB \dec_LOGICAL_BB + connect \LOGICAL_BC \dec_LOGICAL_BC + connect \LOGICAL_BD \dec_LOGICAL_BD + connect \LOGICAL_BI \dec_LOGICAL_BI + connect \LOGICAL_BT \dec_LOGICAL_BT + connect \LOGICAL_DS \dec_LOGICAL_DS + connect \LOGICAL_FXM \dec_LOGICAL_FXM + connect \LOGICAL_LI \dec_LOGICAL_LI + connect \LOGICAL_OE \dec_LOGICAL_OE + connect \LOGICAL_RA \dec_LOGICAL_RA + connect \LOGICAL_Rc \dec_LOGICAL_Rc + connect \LOGICAL_SH32 \dec_LOGICAL_SH32 + connect \LOGICAL_SI \dec_LOGICAL_SI + connect \LOGICAL_UI \dec_LOGICAL_UI + connect \LOGICAL_cr_in \dec_LOGICAL_cr_in + connect \LOGICAL_cr_out \dec_LOGICAL_cr_out + connect \LOGICAL_cry_in \dec_LOGICAL_cry_in + connect \LOGICAL_cry_out \dec_LOGICAL_cry_out + connect \LOGICAL_function_unit \dec_LOGICAL_function_unit + connect \LOGICAL_in1_sel \dec_LOGICAL_in1_sel + connect \LOGICAL_in2_sel \dec_LOGICAL_in2_sel + connect \LOGICAL_internal_op \dec_LOGICAL_internal_op + connect \LOGICAL_inv_a \dec_LOGICAL_inv_a + connect \LOGICAL_inv_out \dec_LOGICAL_inv_out + connect \LOGICAL_is_32b \dec_LOGICAL_is_32b + connect \LOGICAL_ldst_len \dec_LOGICAL_ldst_len + connect \LOGICAL_rc_sel \dec_LOGICAL_rc_sel + connect \LOGICAL_sgn \dec_LOGICAL_sgn + connect \LOGICAL_sh \dec_LOGICAL_sh + connect \XL_BT \dec_XL_BT + connect \X_BF \dec_X_BF + connect \X_BFA \dec_X_BFA + connect \bigendian \bigendian + connect \opcode_in \dec_opcode_in + connect \raw_opcode_in \raw_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:107503.16-107507.4" + cell \dec_ai$159 \dec_ai + connect \LOGICAL_RA \dec_LOGICAL_RA + connect \immz_out \dec_ai_immz_out + connect \sel_in \dec_ai_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:107508.16-107519.4" + cell \dec_bi$160 \dec_bi + connect \LOGICAL_BD \dec_LOGICAL_BD + connect \LOGICAL_DS \dec_LOGICAL_DS + connect \LOGICAL_LI \dec_LOGICAL_LI + connect \LOGICAL_SH32 \dec_LOGICAL_SH32 + connect \LOGICAL_SI \dec_LOGICAL_SI + connect \LOGICAL_UI \dec_LOGICAL_UI + connect \LOGICAL_sh \dec_LOGICAL_sh + connect \imm_b \dec_bi_imm_b + connect \imm_b_ok \dec_bi_imm_b_ok + connect \sel_in \dec_bi_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:107520.19-107531.4" + cell \dec_cr_in$155 \dec_cr_in + connect \LOGICAL_BA \dec_LOGICAL_BA + connect \LOGICAL_BB \dec_LOGICAL_BB + connect \LOGICAL_BC \dec_LOGICAL_BC + connect \LOGICAL_BI \dec_LOGICAL_BI + connect \LOGICAL_BT \dec_LOGICAL_BT + connect \LOGICAL_FXM \dec_LOGICAL_FXM + connect \LOGICAL_internal_op \dec_LOGICAL_internal_op + connect \X_BFA \dec_X_BFA + connect \insn_in \dec_cr_in_insn_in + connect \sel_in \dec_cr_in_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:107532.20-107541.4" + cell \dec_cr_out$157 \dec_cr_out + connect \LOGICAL_FXM \dec_LOGICAL_FXM + connect \LOGICAL_internal_op \dec_LOGICAL_internal_op + connect \XL_BT \dec_XL_BT + connect \X_BF \dec_X_BF + connect \cr_bitfield_ok \dec_cr_out_cr_bitfield_ok + connect \insn_in \dec_cr_out_insn_in + connect \rc_in \dec_cr_out_rc_in + connect \sel_in \dec_cr_out_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:107542.16-107548.4" + cell \dec_oe$154 \dec_oe + connect \LOGICAL_OE \dec_LOGICAL_OE + connect \LOGICAL_internal_op \dec_LOGICAL_internal_op + connect \oe \dec_oe_oe + connect \oe_ok \dec_oe_oe_ok + connect \sel_in \dec_oe_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:107549.16-107554.4" + cell \dec_rc$153 \dec_rc + connect \LOGICAL_Rc \dec_LOGICAL_Rc + connect \rc \dec_rc_rc + connect \rc_ok \dec_rc_rc_ok + connect \sel_in \dec_rc_sel_in + end + connect \LOGICAL_LOGICAL__is_signed \dec_LOGICAL_sgn + connect \LOGICAL_LOGICAL__is_32bit \dec_LOGICAL_is_32b + connect \LOGICAL_LOGICAL__output_carry \dec_LOGICAL_cry_out + connect \LOGICAL_LOGICAL__input_carry \dec_LOGICAL_cry_in + connect \LOGICAL_LOGICAL__invert_out \dec_LOGICAL_inv_out + connect \LOGICAL_LOGICAL__invert_in \dec_LOGICAL_inv_a + connect \LOGICAL_LOGICAL__data_len \dec_LOGICAL_ldst_len + connect \LOGICAL_LOGICAL__write_cr0 \dec_cr_out_cr_bitfield_ok + connect { \LOGICAL_LOGICAL__oe__ok \LOGICAL_LOGICAL__oe__oe } { \dec_oe_oe_ok \dec_oe_oe } + connect { \LOGICAL_LOGICAL__rc__ok \LOGICAL_LOGICAL__rc__rc } { \dec_rc_rc_ok \dec_rc_rc } + connect { \LOGICAL_LOGICAL__imm_data__ok \LOGICAL_LOGICAL__imm_data__data } { \dec_bi_imm_b_ok \dec_bi_imm_b } + connect \dec_bi_sel_in \dec_LOGICAL_in2_sel + connect \LOGICAL_LOGICAL__zero_a \dec_ai_immz_out + connect \dec_ai_sel_in \dec_LOGICAL_in1_sel + connect \LOGICAL_LOGICAL__fn_unit \dec_LOGICAL_function_unit + connect \LOGICAL_LOGICAL__insn_type \dec_LOGICAL_internal_op + connect \dec_cr_out_rc_in \dec_rc_rc + connect \dec_cr_out_sel_in \dec_LOGICAL_cr_out + connect \dec_cr_in_sel_in \dec_LOGICAL_cr_in + connect \dec_oe_sel_in \dec_LOGICAL_rc_sel + connect \dec_rc_sel_in \dec_LOGICAL_rc_sel + connect \dec_cr_out_insn_in \dec_opcode_in + connect \dec_cr_in_insn_in \dec_opcode_in + connect \insn_in$1 \dec_opcode_in + connect \insn_in \dec_opcode_in + connect \LOGICAL_LOGICAL__insn \dec_opcode_in +end +attribute \src "libresoc.v:107585.1-108043.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_MUL" +attribute \generator "nMigen" +module \dec_MUL + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 output 3 \MUL_MUL__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 4 \MUL_MUL__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 5 \MUL_MUL__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 13 \MUL_MUL__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 2 \MUL_MUL__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 11 \MUL_MUL__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 12 \MUL_MUL__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 8 \MUL_MUL__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 9 \MUL_MUL__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 7 \MUL_MUL__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 6 \MUL_MUL__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 10 \MUL_MUL__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + wire input 1 \bigendian + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_MUL_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_MUL_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_MUL_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 14 \dec_MUL_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_MUL_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_MUL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 14 \dec_MUL_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 8 \dec_MUL_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 24 \dec_MUL_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire \dec_MUL_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire \dec_MUL_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_MUL_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 16 \dec_MUL_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 16 \dec_MUL_UI + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec_MUL_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec_MUL_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \dec_MUL_function_unit + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec_MUL_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 \dec_MUL_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec_MUL_is_32b + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec_MUL_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec_MUL_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 6 \dec_MUL_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \dec_XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \dec_X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \dec_X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \dec_bi_imm_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_bi_imm_b_ok + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:216" + wire width 4 \dec_bi_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486" + wire width 32 \dec_cr_in_insn_in + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:485" + wire width 3 \dec_cr_in_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_cr_out_cr_bitfield_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:551" + wire width 32 \dec_cr_out_insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:549" + wire \dec_cr_out_rc_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:550" + wire width 3 \dec_cr_out_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_oe_oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_oe_oe_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" + wire width 2 \dec_oe_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \dec_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_rc_rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_rc_rc_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:405" + wire width 2 \dec_rc_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:406" + wire width 32 \insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:443" + wire width 32 \insn_in$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:442" + wire width 32 input 14 \raw_opcode_in + attribute \module_not_derived 1 + attribute \src "libresoc.v:107946.13-107976.4" + cell \dec$177 \dec + connect \MUL_BA \dec_MUL_BA + connect \MUL_BB \dec_MUL_BB + connect \MUL_BC \dec_MUL_BC + connect \MUL_BD \dec_MUL_BD + connect \MUL_BI \dec_MUL_BI + connect \MUL_BT \dec_MUL_BT + connect \MUL_DS \dec_MUL_DS + connect \MUL_FXM \dec_MUL_FXM + connect \MUL_LI \dec_MUL_LI + connect \MUL_OE \dec_MUL_OE + connect \MUL_Rc \dec_MUL_Rc + connect \MUL_SH32 \dec_MUL_SH32 + connect \MUL_SI \dec_MUL_SI + connect \MUL_UI \dec_MUL_UI + connect \MUL_cr_in \dec_MUL_cr_in + connect \MUL_cr_out \dec_MUL_cr_out + connect \MUL_function_unit \dec_MUL_function_unit + connect \MUL_in2_sel \dec_MUL_in2_sel + connect \MUL_internal_op \dec_MUL_internal_op + connect \MUL_is_32b \dec_MUL_is_32b + connect \MUL_rc_sel \dec_MUL_rc_sel + connect \MUL_sgn \dec_MUL_sgn + connect \MUL_sh \dec_MUL_sh + connect \XL_BT \dec_XL_BT + connect \X_BF \dec_X_BF + connect \X_BFA \dec_X_BFA + connect \bigendian \bigendian + connect \opcode_in \dec_opcode_in + connect \raw_opcode_in \raw_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:107977.16-107988.4" + cell \dec_bi$184 \dec_bi + connect \MUL_BD \dec_MUL_BD + connect \MUL_DS \dec_MUL_DS + connect \MUL_LI \dec_MUL_LI + connect \MUL_SH32 \dec_MUL_SH32 + connect \MUL_SI \dec_MUL_SI + connect \MUL_UI \dec_MUL_UI + connect \MUL_sh \dec_MUL_sh + connect \imm_b \dec_bi_imm_b + connect \imm_b_ok \dec_bi_imm_b_ok + connect \sel_in \dec_bi_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:107989.19-108000.4" + cell \dec_cr_in$180 \dec_cr_in + connect \MUL_BA \dec_MUL_BA + connect \MUL_BB \dec_MUL_BB + connect \MUL_BC \dec_MUL_BC + connect \MUL_BI \dec_MUL_BI + connect \MUL_BT \dec_MUL_BT + connect \MUL_FXM \dec_MUL_FXM + connect \MUL_internal_op \dec_MUL_internal_op + connect \X_BFA \dec_X_BFA + connect \insn_in \dec_cr_in_insn_in + connect \sel_in \dec_cr_in_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:108001.20-108010.4" + cell \dec_cr_out$182 \dec_cr_out + connect \MUL_FXM \dec_MUL_FXM + connect \MUL_internal_op \dec_MUL_internal_op + connect \XL_BT \dec_XL_BT + connect \X_BF \dec_X_BF + connect \cr_bitfield_ok \dec_cr_out_cr_bitfield_ok + connect \insn_in \dec_cr_out_insn_in + connect \rc_in \dec_cr_out_rc_in + connect \sel_in \dec_cr_out_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:108011.16-108017.4" + cell \dec_oe$179 \dec_oe + connect \MUL_OE \dec_MUL_OE + connect \MUL_internal_op \dec_MUL_internal_op + connect \oe \dec_oe_oe + connect \oe_ok \dec_oe_oe_ok + connect \sel_in \dec_oe_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:108018.16-108023.4" + cell \dec_rc$178 \dec_rc + connect \MUL_Rc \dec_MUL_Rc + connect \rc \dec_rc_rc + connect \rc_ok \dec_rc_rc_ok + connect \sel_in \dec_rc_sel_in + end + connect \MUL_MUL__is_signed \dec_MUL_sgn + connect \MUL_MUL__is_32bit \dec_MUL_is_32b + connect \MUL_MUL__write_cr0 \dec_cr_out_cr_bitfield_ok + connect { \MUL_MUL__oe__ok \MUL_MUL__oe__oe } { \dec_oe_oe_ok \dec_oe_oe } + connect { \MUL_MUL__rc__ok \MUL_MUL__rc__rc } { \dec_rc_rc_ok \dec_rc_rc } + connect { \MUL_MUL__imm_data__ok \MUL_MUL__imm_data__data } { \dec_bi_imm_b_ok \dec_bi_imm_b } + connect \dec_bi_sel_in \dec_MUL_in2_sel + connect \MUL_MUL__fn_unit \dec_MUL_function_unit + connect \MUL_MUL__insn_type \dec_MUL_internal_op + connect \dec_cr_out_rc_in \dec_rc_rc + connect \dec_cr_out_sel_in \dec_MUL_cr_out + connect \dec_cr_in_sel_in \dec_MUL_cr_in + connect \dec_oe_sel_in \dec_MUL_rc_sel + connect \dec_rc_sel_in \dec_MUL_rc_sel + connect \dec_cr_out_insn_in \dec_opcode_in + connect \dec_cr_in_insn_in \dec_opcode_in + connect \insn_in$1 \dec_opcode_in + connect \insn_in \dec_opcode_in + connect \MUL_MUL__insn \dec_opcode_in +end +attribute \src "libresoc.v:108047.1-108531.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_SHIFT_ROT" +attribute \generator "nMigen" +module \dec_SHIFT_ROT + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 output 3 \SHIFT_ROT_SHIFT_ROT__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 4 \SHIFT_ROT_SHIFT_ROT__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 5 \SHIFT_ROT_SHIFT_ROT__imm_data__ok + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 11 \SHIFT_ROT_SHIFT_ROT__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 13 \SHIFT_ROT_SHIFT_ROT__input_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 17 \SHIFT_ROT_SHIFT_ROT__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 2 \SHIFT_ROT_SHIFT_ROT__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 15 \SHIFT_ROT_SHIFT_ROT__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 16 \SHIFT_ROT_SHIFT_ROT__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 8 \SHIFT_ROT_SHIFT_ROT__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 9 \SHIFT_ROT_SHIFT_ROT__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 12 \SHIFT_ROT_SHIFT_ROT__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 14 \SHIFT_ROT_SHIFT_ROT__output_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 7 \SHIFT_ROT_SHIFT_ROT__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 6 \SHIFT_ROT_SHIFT_ROT__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 10 \SHIFT_ROT_SHIFT_ROT__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + wire input 1 \bigendian + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_SHIFT_ROT_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_SHIFT_ROT_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_SHIFT_ROT_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 14 \dec_SHIFT_ROT_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_SHIFT_ROT_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_SHIFT_ROT_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 14 \dec_SHIFT_ROT_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 8 \dec_SHIFT_ROT_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 24 \dec_SHIFT_ROT_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire \dec_SHIFT_ROT_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire \dec_SHIFT_ROT_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_SHIFT_ROT_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 16 \dec_SHIFT_ROT_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 16 \dec_SHIFT_ROT_UI + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec_SHIFT_ROT_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec_SHIFT_ROT_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec_SHIFT_ROT_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec_SHIFT_ROT_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \dec_SHIFT_ROT_function_unit + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec_SHIFT_ROT_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 \dec_SHIFT_ROT_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec_SHIFT_ROT_is_32b + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec_SHIFT_ROT_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec_SHIFT_ROT_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 6 \dec_SHIFT_ROT_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \dec_XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \dec_X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \dec_X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \dec_bi_imm_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_bi_imm_b_ok + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:216" + wire width 4 \dec_bi_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486" + wire width 32 \dec_cr_in_insn_in + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:485" + wire width 3 \dec_cr_in_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_cr_out_cr_bitfield_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:551" + wire width 32 \dec_cr_out_insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:549" + wire \dec_cr_out_rc_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:550" + wire width 3 \dec_cr_out_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_oe_oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_oe_oe_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" + wire width 2 \dec_oe_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \dec_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_rc_rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_rc_rc_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:405" + wire width 2 \dec_rc_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:406" + wire width 32 \insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:443" + wire width 32 \insn_in$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:442" + wire width 32 input 18 \raw_opcode_in + attribute \module_not_derived 1 + attribute \src "libresoc.v:108428.13-108460.4" + cell \dec$185 \dec + connect \SHIFT_ROT_BA \dec_SHIFT_ROT_BA + connect \SHIFT_ROT_BB \dec_SHIFT_ROT_BB + connect \SHIFT_ROT_BC \dec_SHIFT_ROT_BC + connect \SHIFT_ROT_BD \dec_SHIFT_ROT_BD + connect \SHIFT_ROT_BI \dec_SHIFT_ROT_BI + connect \SHIFT_ROT_BT \dec_SHIFT_ROT_BT + connect \SHIFT_ROT_DS \dec_SHIFT_ROT_DS + connect \SHIFT_ROT_FXM \dec_SHIFT_ROT_FXM + connect \SHIFT_ROT_LI \dec_SHIFT_ROT_LI + connect \SHIFT_ROT_OE \dec_SHIFT_ROT_OE + connect \SHIFT_ROT_Rc \dec_SHIFT_ROT_Rc + connect \SHIFT_ROT_SH32 \dec_SHIFT_ROT_SH32 + connect \SHIFT_ROT_SI \dec_SHIFT_ROT_SI + connect \SHIFT_ROT_UI \dec_SHIFT_ROT_UI + connect \SHIFT_ROT_cr_in \dec_SHIFT_ROT_cr_in + connect \SHIFT_ROT_cr_out \dec_SHIFT_ROT_cr_out + connect \SHIFT_ROT_cry_in \dec_SHIFT_ROT_cry_in + connect \SHIFT_ROT_cry_out \dec_SHIFT_ROT_cry_out + connect \SHIFT_ROT_function_unit \dec_SHIFT_ROT_function_unit + connect \SHIFT_ROT_in2_sel \dec_SHIFT_ROT_in2_sel + connect \SHIFT_ROT_internal_op \dec_SHIFT_ROT_internal_op + connect \SHIFT_ROT_is_32b \dec_SHIFT_ROT_is_32b + connect \SHIFT_ROT_rc_sel \dec_SHIFT_ROT_rc_sel + connect \SHIFT_ROT_sgn \dec_SHIFT_ROT_sgn + connect \SHIFT_ROT_sh \dec_SHIFT_ROT_sh + connect \XL_BT \dec_XL_BT + connect \X_BF \dec_X_BF + connect \X_BFA \dec_X_BFA + connect \bigendian \bigendian + connect \opcode_in \dec_opcode_in + connect \raw_opcode_in \raw_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:108461.16-108472.4" + cell \dec_bi$192 \dec_bi + connect \SHIFT_ROT_BD \dec_SHIFT_ROT_BD + connect \SHIFT_ROT_DS \dec_SHIFT_ROT_DS + connect \SHIFT_ROT_LI \dec_SHIFT_ROT_LI + connect \SHIFT_ROT_SH32 \dec_SHIFT_ROT_SH32 + connect \SHIFT_ROT_SI \dec_SHIFT_ROT_SI + connect \SHIFT_ROT_UI \dec_SHIFT_ROT_UI + connect \SHIFT_ROT_sh \dec_SHIFT_ROT_sh + connect \imm_b \dec_bi_imm_b + connect \imm_b_ok \dec_bi_imm_b_ok + connect \sel_in \dec_bi_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:108473.19-108484.4" + cell \dec_cr_in$188 \dec_cr_in + connect \SHIFT_ROT_BA \dec_SHIFT_ROT_BA + connect \SHIFT_ROT_BB \dec_SHIFT_ROT_BB + connect \SHIFT_ROT_BC \dec_SHIFT_ROT_BC + connect \SHIFT_ROT_BI \dec_SHIFT_ROT_BI + connect \SHIFT_ROT_BT \dec_SHIFT_ROT_BT + connect \SHIFT_ROT_FXM \dec_SHIFT_ROT_FXM + connect \SHIFT_ROT_internal_op \dec_SHIFT_ROT_internal_op + connect \X_BFA \dec_X_BFA + connect \insn_in \dec_cr_in_insn_in + connect \sel_in \dec_cr_in_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:108485.20-108494.4" + cell \dec_cr_out$190 \dec_cr_out + connect \SHIFT_ROT_FXM \dec_SHIFT_ROT_FXM + connect \SHIFT_ROT_internal_op \dec_SHIFT_ROT_internal_op + connect \XL_BT \dec_XL_BT + connect \X_BF \dec_X_BF + connect \cr_bitfield_ok \dec_cr_out_cr_bitfield_ok + connect \insn_in \dec_cr_out_insn_in + connect \rc_in \dec_cr_out_rc_in + connect \sel_in \dec_cr_out_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:108495.16-108501.4" + cell \dec_oe$187 \dec_oe + connect \SHIFT_ROT_OE \dec_SHIFT_ROT_OE + connect \SHIFT_ROT_internal_op \dec_SHIFT_ROT_internal_op + connect \oe \dec_oe_oe + connect \oe_ok \dec_oe_oe_ok + connect \sel_in \dec_oe_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:108502.16-108507.4" + cell \dec_rc$186 \dec_rc + connect \SHIFT_ROT_Rc \dec_SHIFT_ROT_Rc + connect \rc \dec_rc_rc + connect \rc_ok \dec_rc_rc_ok + connect \sel_in \dec_rc_sel_in + end + connect \SHIFT_ROT_SHIFT_ROT__is_signed \dec_SHIFT_ROT_sgn + connect \SHIFT_ROT_SHIFT_ROT__is_32bit \dec_SHIFT_ROT_is_32b + connect \SHIFT_ROT_SHIFT_ROT__output_carry \dec_SHIFT_ROT_cry_out + connect \SHIFT_ROT_SHIFT_ROT__input_carry \dec_SHIFT_ROT_cry_in + connect \SHIFT_ROT_SHIFT_ROT__output_cr \dec_SHIFT_ROT_cr_out [0] + connect \SHIFT_ROT_SHIFT_ROT__input_cr \dec_SHIFT_ROT_cr_in [0] + connect \SHIFT_ROT_SHIFT_ROT__write_cr0 \dec_cr_out_cr_bitfield_ok + connect { \SHIFT_ROT_SHIFT_ROT__oe__ok \SHIFT_ROT_SHIFT_ROT__oe__oe } { \dec_oe_oe_ok \dec_oe_oe } + connect { \SHIFT_ROT_SHIFT_ROT__rc__ok \SHIFT_ROT_SHIFT_ROT__rc__rc } { \dec_rc_rc_ok \dec_rc_rc } + connect { \SHIFT_ROT_SHIFT_ROT__imm_data__ok \SHIFT_ROT_SHIFT_ROT__imm_data__data } { \dec_bi_imm_b_ok \dec_bi_imm_b } + connect \dec_bi_sel_in \dec_SHIFT_ROT_in2_sel + connect \SHIFT_ROT_SHIFT_ROT__fn_unit \dec_SHIFT_ROT_function_unit + connect \SHIFT_ROT_SHIFT_ROT__insn_type \dec_SHIFT_ROT_internal_op + connect \dec_cr_out_rc_in \dec_rc_rc + connect \dec_cr_out_sel_in \dec_SHIFT_ROT_cr_out + connect \dec_cr_in_sel_in \dec_SHIFT_ROT_cr_in + connect \dec_oe_sel_in \dec_SHIFT_ROT_rc_sel + connect \dec_rc_sel_in \dec_SHIFT_ROT_rc_sel + connect \dec_cr_out_insn_in \dec_opcode_in + connect \dec_cr_in_insn_in \dec_opcode_in + connect \insn_in$1 \dec_opcode_in + connect \insn_in \dec_opcode_in + connect \SHIFT_ROT_SHIFT_ROT__insn \dec_opcode_in +end +attribute \src "libresoc.v:108535.1-108884.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_SPR" +attribute \generator "nMigen" +module \dec_SPR + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 output 3 \SPR_SPR__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 4 \SPR_SPR__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 2 \SPR_SPR__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 5 \SPR_SPR__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + wire input 1 \bigendian + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_SPR_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_SPR_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_SPR_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_SPR_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_SPR_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 8 \dec_SPR_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire \dec_SPR_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire \dec_SPR_Rc + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec_SPR_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec_SPR_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \dec_SPR_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 \dec_SPR_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec_SPR_is_32b + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec_SPR_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \dec_XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \dec_X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \dec_X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486" + wire width 32 \dec_cr_in_insn_in + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:485" + wire width 3 \dec_cr_in_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:551" + wire width 32 \dec_cr_out_insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:549" + wire \dec_cr_out_rc_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:550" + wire width 3 \dec_cr_out_sel_in + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" + wire width 2 \dec_oe_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \dec_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_rc_rc + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:405" + wire width 2 \dec_rc_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:406" + wire width 32 \insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:443" + wire width 32 \insn_in$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:442" + wire width 32 input 6 \raw_opcode_in + attribute \module_not_derived 1 + attribute \src "libresoc.v:108818.13-108839.4" + cell \dec$161 \dec + connect \SPR_BA \dec_SPR_BA + connect \SPR_BB \dec_SPR_BB + connect \SPR_BC \dec_SPR_BC + connect \SPR_BI \dec_SPR_BI + connect \SPR_BT \dec_SPR_BT + connect \SPR_FXM \dec_SPR_FXM + connect \SPR_OE \dec_SPR_OE + connect \SPR_Rc \dec_SPR_Rc + connect \SPR_cr_in \dec_SPR_cr_in + connect \SPR_cr_out \dec_SPR_cr_out + connect \SPR_function_unit \dec_SPR_function_unit + connect \SPR_internal_op \dec_SPR_internal_op + connect \SPR_is_32b \dec_SPR_is_32b + connect \SPR_rc_sel \dec_SPR_rc_sel + connect \XL_BT \dec_XL_BT + connect \X_BF \dec_X_BF + connect \X_BFA \dec_X_BFA + connect \bigendian \bigendian + connect \opcode_in \dec_opcode_in + connect \raw_opcode_in \raw_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:108840.19-108851.4" + cell \dec_cr_in$164 \dec_cr_in + connect \SPR_BA \dec_SPR_BA + connect \SPR_BB \dec_SPR_BB + connect \SPR_BC \dec_SPR_BC + connect \SPR_BI \dec_SPR_BI + connect \SPR_BT \dec_SPR_BT + connect \SPR_FXM \dec_SPR_FXM + connect \SPR_internal_op \dec_SPR_internal_op + connect \X_BFA \dec_X_BFA + connect \insn_in \dec_cr_in_insn_in + connect \sel_in \dec_cr_in_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:108852.20-108860.4" + cell \dec_cr_out$166 \dec_cr_out + connect \SPR_FXM \dec_SPR_FXM + connect \SPR_internal_op \dec_SPR_internal_op + connect \XL_BT \dec_XL_BT + connect \X_BF \dec_X_BF + connect \insn_in \dec_cr_out_insn_in + connect \rc_in \dec_cr_out_rc_in + connect \sel_in \dec_cr_out_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:108861.16-108865.4" + cell \dec_oe$163 \dec_oe + connect \SPR_OE \dec_SPR_OE + connect \SPR_internal_op \dec_SPR_internal_op + connect \sel_in \dec_oe_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:108866.16-108870.4" + cell \dec_rc$162 \dec_rc + connect \SPR_Rc \dec_SPR_Rc + connect \rc \dec_rc_rc + connect \sel_in \dec_rc_sel_in + end + connect \SPR_SPR__is_32bit \dec_SPR_is_32b + connect \SPR_SPR__fn_unit \dec_SPR_function_unit + connect \SPR_SPR__insn_type \dec_SPR_internal_op + connect \dec_cr_out_rc_in \dec_rc_rc + connect \dec_cr_out_sel_in \dec_SPR_cr_out + connect \dec_cr_in_sel_in \dec_SPR_cr_in + connect \dec_oe_sel_in \dec_SPR_rc_sel + connect \dec_rc_sel_in \dec_SPR_rc_sel + connect \dec_cr_out_insn_in \dec_opcode_in + connect \dec_cr_in_insn_in \dec_opcode_in + connect \insn_in$1 \dec_opcode_in + connect \insn_in \dec_opcode_in + connect \SPR_SPR__insn \dec_opcode_in +end +attribute \src "libresoc.v:108888.1-109393.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.dec2.dec_a" +attribute \generator "nMigen" +module \dec_a + attribute \src "libresoc.v:109322.3-109357.6" + wire width 3 $0\fast_a[2:0] + attribute \src "libresoc.v:109322.3-109357.6" + wire $0\fast_a_ok[0:0] + attribute \src "libresoc.v:108889.7-108889.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:109290.3-109305.6" + wire width 5 $0\reg_a[4:0] + attribute \src "libresoc.v:109306.3-109321.6" + wire $0\reg_a_ok[0:0] + attribute \src "libresoc.v:109358.3-109368.6" + wire width 10 $0\spr[9:0] + attribute \src "libresoc.v:109380.3-109391.6" + wire width 10 $0\spr_a[9:0] + attribute \src "libresoc.v:109380.3-109391.6" + wire $0\spr_a_ok[0:0] + attribute \src "libresoc.v:109369.3-109379.6" + wire width 10 $0\sprmap_spr_i[9:0] + attribute \src "libresoc.v:109322.3-109357.6" + wire width 3 $1\fast_a[2:0] + attribute \src "libresoc.v:109322.3-109357.6" + wire $1\fast_a_ok[0:0] + attribute \src "libresoc.v:109290.3-109305.6" + wire width 5 $1\reg_a[4:0] + attribute \src "libresoc.v:109306.3-109321.6" + wire $1\reg_a_ok[0:0] + attribute \src "libresoc.v:109358.3-109368.6" + wire width 10 $1\spr[9:0] + attribute \src "libresoc.v:109380.3-109391.6" + wire width 10 $1\spr_a[9:0] + attribute \src "libresoc.v:109380.3-109391.6" + wire $1\spr_a_ok[0:0] + attribute \src "libresoc.v:109369.3-109379.6" + wire width 10 $1\sprmap_spr_i[9:0] + attribute \src "libresoc.v:109322.3-109357.6" + wire width 3 $2\fast_a[2:0] + attribute \src "libresoc.v:109322.3-109357.6" + wire $2\fast_a_ok[0:0] + attribute \src "libresoc.v:109290.3-109305.6" + wire width 5 $2\reg_a[4:0] + attribute \src "libresoc.v:109306.3-109321.6" + wire $2\reg_a_ok[0:0] + attribute \src "libresoc.v:109322.3-109357.6" + wire width 3 $3\fast_a[2:0] + attribute \src "libresoc.v:109322.3-109357.6" + wire $3\fast_a_ok[0:0] + attribute \src "libresoc.v:109274.18-109274.110" + wire $and$libresoc.v:109274$4189_Y + attribute \src "libresoc.v:109279.18-109279.113" + wire $and$libresoc.v:109279$4194_Y + attribute \src "libresoc.v:109282.17-109282.107" + wire $and$libresoc.v:109282$4197_Y + attribute \src "libresoc.v:109269.18-109269.112" + wire $eq$libresoc.v:109269$4184_Y + attribute \src "libresoc.v:109270.18-109270.111" + wire $eq$libresoc.v:109270$4185_Y + attribute \src "libresoc.v:109271.18-109271.112" + wire $eq$libresoc.v:109271$4186_Y + attribute \src "libresoc.v:109273.17-109273.110" + wire $eq$libresoc.v:109273$4188_Y + attribute \src "libresoc.v:109276.18-109276.112" + wire $eq$libresoc.v:109276$4191_Y + attribute \src "libresoc.v:109280.17-109280.111" + wire $eq$libresoc.v:109280$4195_Y + attribute \src "libresoc.v:109272.18-109272.109" + wire $ne$libresoc.v:109272$4187_Y + attribute \src "libresoc.v:109281.17-109281.108" + wire $ne$libresoc.v:109281$4196_Y + attribute \src "libresoc.v:109277.18-109277.105" + wire $not$libresoc.v:109277$4192_Y + attribute \src "libresoc.v:109278.18-109278.108" + wire $not$libresoc.v:109278$4193_Y + attribute \src "libresoc.v:109268.17-109268.107" + wire $or$libresoc.v:109268$4183_Y + attribute \src "libresoc.v:109275.18-109275.110" + wire $or$libresoc.v:109275$4190_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:99" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:106" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:99" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:100" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:101" + wire \$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:101" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:101" + wire \$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:106" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:116" + wire \$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:123" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:123" + wire \$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:100" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:101" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:101" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:101" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 10 \BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 9 \RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 8 \RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 10 input 11 \SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 input 12 \XL_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 output 6 \fast_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 7 \fast_a_ok + attribute \src "libresoc.v:108889.7-108889.15" + wire \initial + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 input 13 \internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:97" + wire width 5 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 output 2 \reg_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 3 \reg_a_ok + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:85" + wire width 3 input 1 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" + wire width 10 \spr + attribute \enum_base_type "SPR" + attribute \enum_value_0000000001 "XER" + attribute \enum_value_0000000011 "DSCR" + attribute \enum_value_0000001000 "LR" + attribute \enum_value_0000001001 "CTR" + attribute \enum_value_0000001101 "AMR" + attribute \enum_value_0000010001 "DSCR_priv" + attribute \enum_value_0000010010 "DSISR" + attribute \enum_value_0000010011 "DAR" + attribute \enum_value_0000010110 "DEC" + attribute \enum_value_0000011010 "SRR0" + attribute \enum_value_0000011011 "SRR1" + attribute \enum_value_0000011100 "CFAR" + attribute \enum_value_0000011101 "AMR_priv" + attribute \enum_value_0000110000 "PIDR" + attribute \enum_value_0000111101 "IAMR" + attribute \enum_value_0010000000 "TFHAR" + attribute \enum_value_0010000001 "TFIAR" + attribute \enum_value_0010000010 "TEXASR" + attribute \enum_value_0010000011 "TEXASRU" + attribute \enum_value_0010001000 "CTRL" + attribute \enum_value_0010010000 "TIDR" + attribute \enum_value_0010011000 "CTRL_priv" + attribute \enum_value_0010011001 "FSCR" + attribute \enum_value_0010011101 "UAMOR" + attribute \enum_value_0010011110 "GSR" + attribute \enum_value_0010011111 "PSPB" + attribute \enum_value_0010110000 "DPDES" + attribute \enum_value_0010110100 "DAWR0" + attribute \enum_value_0010111010 "RPR" + attribute \enum_value_0010111011 "CIABR" + attribute \enum_value_0010111100 "DAWRX0" + attribute \enum_value_0010111110 "HFSCR" + attribute \enum_value_0100000000 "VRSAVE" + attribute \enum_value_0100000011 "SPRG3" + attribute \enum_value_0100001100 "TB" + attribute \enum_value_0100001101 "TBU" + attribute \enum_value_0100010000 "SPRG0_priv" + attribute \enum_value_0100010001 "SPRG1_priv" + attribute \enum_value_0100010010 "SPRG2_priv" + attribute \enum_value_0100010011 "SPRG3_priv" + attribute \enum_value_0100011011 "CIR" + attribute \enum_value_0100011100 "TBL" + attribute \enum_value_0100011101 "TBU_hypv" + attribute \enum_value_0100011110 "TBU40" + attribute \enum_value_0100011111 "PVR" + attribute \enum_value_0100110000 "HSPRG0" + attribute \enum_value_0100110001 "HSPRG1" + attribute \enum_value_0100110010 "HDSISR" + attribute \enum_value_0100110011 "HDAR" + attribute \enum_value_0100110100 "SPURR" + attribute \enum_value_0100110101 "PURR" + attribute \enum_value_0100110110 "HDEC" + attribute \enum_value_0100111001 "HRMOR" + attribute \enum_value_0100111010 "HSRR0" + attribute \enum_value_0100111011 "HSRR1" + attribute \enum_value_0100111110 "LPCR" + attribute \enum_value_0100111111 "LPIDR" + attribute \enum_value_0101010000 "HMER" + attribute \enum_value_0101010001 "HMEER" + attribute \enum_value_0101010010 "PCR" + attribute \enum_value_0101010011 "HEIR" + attribute \enum_value_0101011101 "AMOR" + attribute \enum_value_0110111110 "TIR" + attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1100000000 "SIER" + attribute \enum_value_1100000001 "MMCR2" + attribute \enum_value_1100000010 "MMCRA" + attribute \enum_value_1100000011 "PMC1" + attribute \enum_value_1100000100 "PMC2" + attribute \enum_value_1100000101 "PMC3" + attribute \enum_value_1100000110 "PMC4" + attribute \enum_value_1100000111 "PMC5" + attribute \enum_value_1100001000 "PMC6" + attribute \enum_value_1100001011 "MMCR0" + attribute \enum_value_1100001100 "SIAR" + attribute \enum_value_1100001101 "SDAR" + attribute \enum_value_1100001110 "MMCR1" + attribute \enum_value_1100010000 "SIER_priv" + attribute \enum_value_1100010001 "MMCR2_priv" + attribute \enum_value_1100010010 "MMCRA_priv" + attribute \enum_value_1100010011 "PMC1_priv" + attribute \enum_value_1100010100 "PMC2_priv" + attribute \enum_value_1100010101 "PMC3_priv" + attribute \enum_value_1100010110 "PMC4_priv" + attribute \enum_value_1100010111 "PMC5_priv" + attribute \enum_value_1100011000 "PMC6_priv" + attribute \enum_value_1100011011 "MMCR0_priv" + attribute \enum_value_1100011100 "SIAR_priv" + attribute \enum_value_1100011101 "SDAR_priv" + attribute \enum_value_1100011110 "MMCR1_priv" + attribute \enum_value_1100100000 "BESCRS" + attribute \enum_value_1100100001 "BESCRSU" + attribute \enum_value_1100100010 "BESCRR" + attribute \enum_value_1100100011 "BESCRRU" + attribute \enum_value_1100100100 "EBBHR" + attribute \enum_value_1100100101 "EBBRR" + attribute \enum_value_1100100110 "BESCR" + attribute \enum_value_1100101000 "reserved808" + attribute \enum_value_1100101001 "reserved809" + attribute \enum_value_1100101010 "reserved810" + attribute \enum_value_1100101011 "reserved811" + attribute \enum_value_1100101111 "TAR" + attribute \enum_value_1100110000 "ASDR" + attribute \enum_value_1100110111 "PSSCR" + attribute \enum_value_1101010000 "IC" + attribute \enum_value_1101010001 "VTB" + attribute \enum_value_1101010111 "PSSCR_hypv" + attribute \enum_value_1110000000 "PPR" + attribute \enum_value_1110000010 "PPR32" + attribute \enum_value_1111111111 "PIR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 10 output 4 \spr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 5 \spr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \sprmap_fast_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \sprmap_fast_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:59" + wire width 10 \sprmap_spr_i + attribute \enum_base_type "SPR" + attribute \enum_value_0000000001 "XER" + attribute \enum_value_0000000011 "DSCR" + attribute \enum_value_0000001000 "LR" + attribute \enum_value_0000001001 "CTR" + attribute \enum_value_0000001101 "AMR" + attribute \enum_value_0000010001 "DSCR_priv" + attribute \enum_value_0000010010 "DSISR" + attribute \enum_value_0000010011 "DAR" + attribute \enum_value_0000010110 "DEC" + attribute \enum_value_0000011010 "SRR0" + attribute \enum_value_0000011011 "SRR1" + attribute \enum_value_0000011100 "CFAR" + attribute \enum_value_0000011101 "AMR_priv" + attribute \enum_value_0000110000 "PIDR" + attribute \enum_value_0000111101 "IAMR" + attribute \enum_value_0010000000 "TFHAR" + attribute \enum_value_0010000001 "TFIAR" + attribute \enum_value_0010000010 "TEXASR" + attribute \enum_value_0010000011 "TEXASRU" + attribute \enum_value_0010001000 "CTRL" + attribute \enum_value_0010010000 "TIDR" + attribute \enum_value_0010011000 "CTRL_priv" + attribute \enum_value_0010011001 "FSCR" + attribute \enum_value_0010011101 "UAMOR" + attribute \enum_value_0010011110 "GSR" + attribute \enum_value_0010011111 "PSPB" + attribute \enum_value_0010110000 "DPDES" + attribute \enum_value_0010110100 "DAWR0" + attribute \enum_value_0010111010 "RPR" + attribute \enum_value_0010111011 "CIABR" + attribute \enum_value_0010111100 "DAWRX0" + attribute \enum_value_0010111110 "HFSCR" + attribute \enum_value_0100000000 "VRSAVE" + attribute \enum_value_0100000011 "SPRG3" + attribute \enum_value_0100001100 "TB" + attribute \enum_value_0100001101 "TBU" + attribute \enum_value_0100010000 "SPRG0_priv" + attribute \enum_value_0100010001 "SPRG1_priv" + attribute \enum_value_0100010010 "SPRG2_priv" + attribute \enum_value_0100010011 "SPRG3_priv" + attribute \enum_value_0100011011 "CIR" + attribute \enum_value_0100011100 "TBL" + attribute \enum_value_0100011101 "TBU_hypv" + attribute \enum_value_0100011110 "TBU40" + attribute \enum_value_0100011111 "PVR" + attribute \enum_value_0100110000 "HSPRG0" + attribute \enum_value_0100110001 "HSPRG1" + attribute \enum_value_0100110010 "HDSISR" + attribute \enum_value_0100110011 "HDAR" + attribute \enum_value_0100110100 "SPURR" + attribute \enum_value_0100110101 "PURR" + attribute \enum_value_0100110110 "HDEC" + attribute \enum_value_0100111001 "HRMOR" + attribute \enum_value_0100111010 "HSRR0" + attribute \enum_value_0100111011 "HSRR1" + attribute \enum_value_0100111110 "LPCR" + attribute \enum_value_0100111111 "LPIDR" + attribute \enum_value_0101010000 "HMER" + attribute \enum_value_0101010001 "HMEER" + attribute \enum_value_0101010010 "PCR" + attribute \enum_value_0101010011 "HEIR" + attribute \enum_value_0101011101 "AMOR" + attribute \enum_value_0110111110 "TIR" + attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1100000000 "SIER" + attribute \enum_value_1100000001 "MMCR2" + attribute \enum_value_1100000010 "MMCRA" + attribute \enum_value_1100000011 "PMC1" + attribute \enum_value_1100000100 "PMC2" + attribute \enum_value_1100000101 "PMC3" + attribute \enum_value_1100000110 "PMC4" + attribute \enum_value_1100000111 "PMC5" + attribute \enum_value_1100001000 "PMC6" + attribute \enum_value_1100001011 "MMCR0" + attribute \enum_value_1100001100 "SIAR" + attribute \enum_value_1100001101 "SDAR" + attribute \enum_value_1100001110 "MMCR1" + attribute \enum_value_1100010000 "SIER_priv" + attribute \enum_value_1100010001 "MMCR2_priv" + attribute \enum_value_1100010010 "MMCRA_priv" + attribute \enum_value_1100010011 "PMC1_priv" + attribute \enum_value_1100010100 "PMC2_priv" + attribute \enum_value_1100010101 "PMC3_priv" + attribute \enum_value_1100010110 "PMC4_priv" + attribute \enum_value_1100010111 "PMC5_priv" + attribute \enum_value_1100011000 "PMC6_priv" + attribute \enum_value_1100011011 "MMCR0_priv" + attribute \enum_value_1100011100 "SIAR_priv" + attribute \enum_value_1100011101 "SDAR_priv" + attribute \enum_value_1100011110 "MMCR1_priv" + attribute \enum_value_1100100000 "BESCRS" + attribute \enum_value_1100100001 "BESCRSU" + attribute \enum_value_1100100010 "BESCRR" + attribute \enum_value_1100100011 "BESCRRU" + attribute \enum_value_1100100100 "EBBHR" + attribute \enum_value_1100100101 "EBBRR" + attribute \enum_value_1100100110 "BESCR" + attribute \enum_value_1100101000 "reserved808" + attribute \enum_value_1100101001 "reserved809" + attribute \enum_value_1100101010 "reserved810" + attribute \enum_value_1100101011 "reserved811" + attribute \enum_value_1100101111 "TAR" + attribute \enum_value_1100110000 "ASDR" + attribute \enum_value_1100110111 "PSSCR" + attribute \enum_value_1101010000 "IC" + attribute \enum_value_1101010001 "VTB" + attribute \enum_value_1101010111 "PSSCR_hypv" + attribute \enum_value_1110000000 "PPR" + attribute \enum_value_1110000010 "PPR32" + attribute \enum_value_1111111111 "PIR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 10 \sprmap_spr_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \sprmap_spr_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:101" + cell $and $and$libresoc.v:109274$4189 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$15 + connect \B \$17 + connect \Y $and$libresoc.v:109274$4189_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:123" + cell $and $and$libresoc.v:109279$4194 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \XL_XO [9] + connect \B \$27 + connect \Y $and$libresoc.v:109279$4194_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:101" + cell $and $and$libresoc.v:109282$4197 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \$5 + connect \Y $and$libresoc.v:109282$4197_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:106" + cell $eq $eq$libresoc.v:109269$4184 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \sel_in + connect \B 3'100 + connect \Y $eq$libresoc.v:109269$4184_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:99" + cell $eq $eq$libresoc.v:109270$4185 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \sel_in + connect \B 3'001 + connect \Y $eq$libresoc.v:109270$4185_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:100" + cell $eq $eq$libresoc.v:109271$4186 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \sel_in + connect \B 3'010 + connect \Y $eq$libresoc.v:109271$4186_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:99" + cell $eq $eq$libresoc.v:109273$4188 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \sel_in + connect \B 3'001 + connect \Y $eq$libresoc.v:109273$4188_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:106" + cell $eq $eq$libresoc.v:109276$4191 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \sel_in + connect \B 3'100 + connect \Y $eq$libresoc.v:109276$4191_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:100" + cell $eq $eq$libresoc.v:109280$4195 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \sel_in + connect \B 3'010 + connect \Y $eq$libresoc.v:109280$4195_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:101" + cell $ne $ne$libresoc.v:109272$4187 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \ra + connect \B 5'00000 + connect \Y $ne$libresoc.v:109272$4187_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:101" + cell $ne $ne$libresoc.v:109281$4196 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \ra + connect \B 5'00000 + connect \Y $ne$libresoc.v:109281$4196_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:116" + cell $not $not$libresoc.v:109277$4192 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \BO [2] + connect \Y $not$libresoc.v:109277$4192_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:123" + cell $not $not$libresoc.v:109278$4193 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \XL_XO [5] + connect \Y $not$libresoc.v:109278$4193_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:101" + cell $or $or$libresoc.v:109268$4183 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$1 + connect \B \$7 + connect \Y $or$libresoc.v:109268$4183_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:101" + cell $or $or$libresoc.v:109275$4190 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$13 + connect \B \$19 + connect \Y $or$libresoc.v:109275$4190_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:109283.10-109289.4" + cell \sprmap \sprmap + connect \fast_o \sprmap_fast_o + connect \fast_o_ok \sprmap_fast_o_ok + connect \spr_i \sprmap_spr_i + connect \spr_o \sprmap_spr_o + connect \spr_o_ok \sprmap_spr_o_ok + end + attribute \src "libresoc.v:108889.7-108889.20" + process $proc$libresoc.v:108889$4204 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:109290.3-109305.6" + process $proc$libresoc.v:109290$4198 + assign { } { } + assign { } { } + assign { } { } + assign $0\reg_a[4:0] $2\reg_a[4:0] + attribute \src "libresoc.v:109291.5-109291.29" + switch \initial + attribute \src "libresoc.v:109291.9-109291.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:101" + switch \$9 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\reg_a[4:0] \ra + case + assign $1\reg_a[4:0] 5'00000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:106" + switch \$11 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\reg_a[4:0] \RS + case + assign $2\reg_a[4:0] $1\reg_a[4:0] + end + sync always + update \reg_a $0\reg_a[4:0] + end + attribute \src "libresoc.v:109306.3-109321.6" + process $proc$libresoc.v:109306$4199 + assign { } { } + assign { } { } + assign { } { } + assign $0\reg_a_ok[0:0] $2\reg_a_ok[0:0] + attribute \src "libresoc.v:109307.5-109307.29" + switch \initial + attribute \src "libresoc.v:109307.9-109307.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:101" + switch \$21 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\reg_a_ok[0:0] 1'1 + case + assign $1\reg_a_ok[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:106" + switch \$23 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\reg_a_ok[0:0] 1'1 + case + assign $2\reg_a_ok[0:0] $1\reg_a_ok[0:0] + end + sync always + update \reg_a_ok $0\reg_a_ok[0:0] + end + attribute \src "libresoc.v:109322.3-109357.6" + process $proc$libresoc.v:109322$4200 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fast_a[2:0] $1\fast_a[2:0] + assign $0\fast_a_ok[0:0] $1\fast_a_ok[0:0] + attribute \src "libresoc.v:109323.5-109323.29" + switch \initial + attribute \src "libresoc.v:109323.9-109323.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:112" + switch \internal_op + attribute \src "libresoc.v:0.0-0.0" + case 7'0000111 + assign { } { } + assign { } { } + assign $1\fast_a[2:0] $2\fast_a[2:0] + assign $1\fast_a_ok[0:0] $2\fast_a_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:116" + switch \$25 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $2\fast_a[2:0] 3'000 + assign $2\fast_a_ok[0:0] 1'1 + case + assign $2\fast_a[2:0] 3'000 + assign $2\fast_a_ok[0:0] 1'0 + end + attribute \src "libresoc.v:0.0-0.0" + case 7'0001000 + assign { } { } + assign { } { } + assign $1\fast_a[2:0] $3\fast_a[2:0] + assign $1\fast_a_ok[0:0] $3\fast_a_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:123" + switch \$29 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $3\fast_a[2:0] 3'000 + assign $3\fast_a_ok[0:0] 1'1 + case + assign $3\fast_a[2:0] 3'000 + assign $3\fast_a_ok[0:0] 1'0 + end + attribute \src "libresoc.v:0.0-0.0" + case 7'0101110 + assign { } { } + assign { } { } + assign { $1\fast_a_ok[0:0] $1\fast_a[2:0] } { \sprmap_fast_o_ok \sprmap_fast_o } + case + assign $1\fast_a[2:0] 3'000 + assign $1\fast_a_ok[0:0] 1'0 + end + sync always + update \fast_a $0\fast_a[2:0] + update \fast_a_ok $0\fast_a_ok[0:0] + end + attribute \src "libresoc.v:109358.3-109368.6" + process $proc$libresoc.v:109358$4201 + assign { } { } + assign { } { } + assign $0\spr[9:0] $1\spr[9:0] + attribute \src "libresoc.v:109359.5-109359.29" + switch \initial + attribute \src "libresoc.v:109359.9-109359.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:112" + switch \internal_op + attribute \src "libresoc.v:0.0-0.0" + case 7'0101110 + assign { } { } + assign $1\spr[9:0] { \SPR [4:0] \SPR [9:5] } + case + assign $1\spr[9:0] 10'0000000000 + end + sync always + update \spr $0\spr[9:0] + end + attribute \src "libresoc.v:109369.3-109379.6" + process $proc$libresoc.v:109369$4202 + assign { } { } + assign { } { } + assign $0\sprmap_spr_i[9:0] $1\sprmap_spr_i[9:0] + attribute \src "libresoc.v:109370.5-109370.29" + switch \initial + attribute \src "libresoc.v:109370.9-109370.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:112" + switch \internal_op + attribute \src "libresoc.v:0.0-0.0" + case 7'0101110 + assign { } { } + assign $1\sprmap_spr_i[9:0] \spr + case + assign $1\sprmap_spr_i[9:0] 10'0000000000 + end + sync always + update \sprmap_spr_i $0\sprmap_spr_i[9:0] + end + attribute \src "libresoc.v:109380.3-109391.6" + process $proc$libresoc.v:109380$4203 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\spr_a[9:0] $1\spr_a[9:0] + assign $0\spr_a_ok[0:0] $1\spr_a_ok[0:0] + attribute \src "libresoc.v:109381.5-109381.29" + switch \initial + attribute \src "libresoc.v:109381.9-109381.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:112" + switch \internal_op + attribute \src "libresoc.v:0.0-0.0" + case 7'0101110 + assign { } { } + assign { } { } + assign { $1\spr_a_ok[0:0] $1\spr_a[9:0] } { \sprmap_spr_o_ok \sprmap_spr_o } + case + assign $1\spr_a[9:0] 10'0000000000 + assign $1\spr_a_ok[0:0] 1'0 + end + sync always + update \spr_a $0\spr_a[9:0] + update \spr_a_ok $0\spr_a_ok[0:0] + end + connect \$9 $or$libresoc.v:109268$4183_Y + connect \$11 $eq$libresoc.v:109269$4184_Y + connect \$13 $eq$libresoc.v:109270$4185_Y + connect \$15 $eq$libresoc.v:109271$4186_Y + connect \$17 $ne$libresoc.v:109272$4187_Y + connect \$1 $eq$libresoc.v:109273$4188_Y + connect \$19 $and$libresoc.v:109274$4189_Y + connect \$21 $or$libresoc.v:109275$4190_Y + connect \$23 $eq$libresoc.v:109276$4191_Y + connect \$25 $not$libresoc.v:109277$4192_Y + connect \$27 $not$libresoc.v:109278$4193_Y + connect \$29 $and$libresoc.v:109279$4194_Y + connect \$3 $eq$libresoc.v:109280$4195_Y + connect \$5 $ne$libresoc.v:109281$4196_Y + connect \$7 $and$libresoc.v:109282$4197_Y + connect \ra \RA +end +attribute \src "libresoc.v:109397.1-109434.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_ALU.dec_ai" +attribute \generator "nMigen" +module \dec_ai + attribute \src "libresoc.v:109423.3-109432.6" + wire $0\immz_out[0:0] + attribute \src "libresoc.v:109398.7-109398.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:109423.3-109432.6" + wire $1\immz_out[0:0] + attribute \src "libresoc.v:109422.17-109422.107" + wire $and$libresoc.v:109422$4207_Y + attribute \src "libresoc.v:109420.17-109420.111" + wire $eq$libresoc.v:109420$4205_Y + attribute \src "libresoc.v:109421.17-109421.108" + wire $eq$libresoc.v:109421$4206_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 2 \ALU_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:149" + wire output 1 \immz_out + attribute \src "libresoc.v:109398.7-109398.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:156" + wire width 5 \ra + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:148" + wire width 3 input 3 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" + cell $and $and$libresoc.v:109422$4207 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$1 + connect \B \$3 + connect \Y $and$libresoc.v:109422$4207_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" + cell $eq $eq$libresoc.v:109420$4205 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \sel_in + connect \B 3'010 + connect \Y $eq$libresoc.v:109420$4205_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" + cell $eq $eq$libresoc.v:109421$4206 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \ra + connect \B 5'00000 + connect \Y $eq$libresoc.v:109421$4206_Y + end + attribute \src "libresoc.v:109398.7-109398.20" + process $proc$libresoc.v:109398$4209 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:109423.3-109432.6" + process $proc$libresoc.v:109423$4208 + assign { } { } + assign { } { } + assign $0\immz_out[0:0] $1\immz_out[0:0] + attribute \src "libresoc.v:109424.5-109424.29" + switch \initial + attribute \src "libresoc.v:109424.9-109424.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" + switch \$5 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\immz_out[0:0] 1'1 + case + assign $1\immz_out[0:0] 1'0 + end + sync always + update \immz_out $0\immz_out[0:0] + end + connect \$1 $eq$libresoc.v:109420$4205_Y + connect \$3 $eq$libresoc.v:109421$4206_Y + connect \$5 $and$libresoc.v:109422$4207_Y + connect \ra \ALU_RA +end +attribute \src "libresoc.v:109438.1-109475.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_LOGICAL.dec_ai" +attribute \generator "nMigen" +module \dec_ai$159 + attribute \src "libresoc.v:109464.3-109473.6" + wire $0\immz_out[0:0] + attribute \src "libresoc.v:109439.7-109439.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:109464.3-109473.6" + wire $1\immz_out[0:0] + attribute \src "libresoc.v:109463.17-109463.107" + wire $and$libresoc.v:109463$4212_Y + attribute \src "libresoc.v:109461.17-109461.111" + wire $eq$libresoc.v:109461$4210_Y + attribute \src "libresoc.v:109462.17-109462.108" + wire $eq$libresoc.v:109462$4211_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 2 \LOGICAL_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:149" + wire output 1 \immz_out + attribute \src "libresoc.v:109439.7-109439.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:156" + wire width 5 \ra + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:148" + wire width 3 input 3 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" + cell $and $and$libresoc.v:109463$4212 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$1 + connect \B \$3 + connect \Y $and$libresoc.v:109463$4212_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" + cell $eq $eq$libresoc.v:109461$4210 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \sel_in + connect \B 3'010 + connect \Y $eq$libresoc.v:109461$4210_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" + cell $eq $eq$libresoc.v:109462$4211 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \ra + connect \B 5'00000 + connect \Y $eq$libresoc.v:109462$4211_Y + end + attribute \src "libresoc.v:109439.7-109439.20" + process $proc$libresoc.v:109439$4214 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:109464.3-109473.6" + process $proc$libresoc.v:109464$4213 + assign { } { } + assign { } { } + assign $0\immz_out[0:0] $1\immz_out[0:0] + attribute \src "libresoc.v:109465.5-109465.29" + switch \initial + attribute \src "libresoc.v:109465.9-109465.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" + switch \$5 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\immz_out[0:0] 1'1 + case + assign $1\immz_out[0:0] 1'0 + end + sync always + update \immz_out $0\immz_out[0:0] + end + connect \$1 $eq$libresoc.v:109461$4210_Y + connect \$3 $eq$libresoc.v:109462$4211_Y + connect \$5 $and$libresoc.v:109463$4212_Y + connect \ra \LOGICAL_RA +end +attribute \src "libresoc.v:109479.1-109516.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_DIV.dec_ai" +attribute \generator "nMigen" +module \dec_ai$175 + attribute \src "libresoc.v:109505.3-109514.6" + wire $0\immz_out[0:0] + attribute \src "libresoc.v:109480.7-109480.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:109505.3-109514.6" + wire $1\immz_out[0:0] + attribute \src "libresoc.v:109504.17-109504.107" + wire $and$libresoc.v:109504$4217_Y + attribute \src "libresoc.v:109502.17-109502.111" + wire $eq$libresoc.v:109502$4215_Y + attribute \src "libresoc.v:109503.17-109503.108" + wire $eq$libresoc.v:109503$4216_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 2 \DIV_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:149" + wire output 1 \immz_out + attribute \src "libresoc.v:109480.7-109480.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:156" + wire width 5 \ra + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:148" + wire width 3 input 3 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" + cell $and $and$libresoc.v:109504$4217 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$1 + connect \B \$3 + connect \Y $and$libresoc.v:109504$4217_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" + cell $eq $eq$libresoc.v:109502$4215 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \sel_in + connect \B 3'010 + connect \Y $eq$libresoc.v:109502$4215_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" + cell $eq $eq$libresoc.v:109503$4216 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \ra + connect \B 5'00000 + connect \Y $eq$libresoc.v:109503$4216_Y + end + attribute \src "libresoc.v:109480.7-109480.20" + process $proc$libresoc.v:109480$4219 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:109505.3-109514.6" + process $proc$libresoc.v:109505$4218 + assign { } { } + assign { } { } + assign $0\immz_out[0:0] $1\immz_out[0:0] + attribute \src "libresoc.v:109506.5-109506.29" + switch \initial + attribute \src "libresoc.v:109506.9-109506.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" + switch \$5 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\immz_out[0:0] 1'1 + case + assign $1\immz_out[0:0] 1'0 + end + sync always + update \immz_out $0\immz_out[0:0] + end + connect \$1 $eq$libresoc.v:109502$4215_Y + connect \$3 $eq$libresoc.v:109503$4216_Y + connect \$5 $and$libresoc.v:109504$4217_Y + connect \ra \DIV_RA +end +attribute \src "libresoc.v:109520.1-109557.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_LDST.dec_ai" +attribute \generator "nMigen" +module \dec_ai$200 + attribute \src "libresoc.v:109546.3-109555.6" + wire $0\immz_out[0:0] + attribute \src "libresoc.v:109521.7-109521.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:109546.3-109555.6" + wire $1\immz_out[0:0] + attribute \src "libresoc.v:109545.17-109545.107" + wire $and$libresoc.v:109545$4222_Y + attribute \src "libresoc.v:109543.17-109543.111" + wire $eq$libresoc.v:109543$4220_Y + attribute \src "libresoc.v:109544.17-109544.108" + wire $eq$libresoc.v:109544$4221_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 2 \LDST_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:149" + wire output 1 \immz_out + attribute \src "libresoc.v:109521.7-109521.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:156" + wire width 5 \ra + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:148" + wire width 3 input 3 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" + cell $and $and$libresoc.v:109545$4222 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$1 + connect \B \$3 + connect \Y $and$libresoc.v:109545$4222_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" + cell $eq $eq$libresoc.v:109543$4220 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \sel_in + connect \B 3'010 + connect \Y $eq$libresoc.v:109543$4220_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" + cell $eq $eq$libresoc.v:109544$4221 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \ra + connect \B 5'00000 + connect \Y $eq$libresoc.v:109544$4221_Y + end + attribute \src "libresoc.v:109521.7-109521.20" + process $proc$libresoc.v:109521$4224 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:109546.3-109555.6" + process $proc$libresoc.v:109546$4223 + assign { } { } + assign { } { } + assign $0\immz_out[0:0] $1\immz_out[0:0] + attribute \src "libresoc.v:109547.5-109547.29" + switch \initial + attribute \src "libresoc.v:109547.9-109547.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" + switch \$5 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\immz_out[0:0] 1'1 + case + assign $1\immz_out[0:0] 1'0 + end + sync always + update \immz_out $0\immz_out[0:0] + end + connect \$1 $eq$libresoc.v:109543$4220_Y + connect \$3 $eq$libresoc.v:109544$4221_Y + connect \$5 $and$libresoc.v:109545$4222_Y + connect \ra \LDST_RA +end +attribute \src "libresoc.v:109561.1-109752.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.dec2.dec_b" +attribute \generator "nMigen" +module \dec_b + attribute \src "libresoc.v:109716.3-109733.6" + wire width 3 $0\fast_b[2:0] + attribute \src "libresoc.v:109734.3-109751.6" + wire $0\fast_b_ok[0:0] + attribute \src "libresoc.v:109562.7-109562.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:109686.3-109700.6" + wire width 5 $0\reg_b[4:0] + attribute \src "libresoc.v:109701.3-109715.6" + wire $0\reg_b_ok[0:0] + attribute \src "libresoc.v:109716.3-109733.6" + wire width 3 $1\fast_b[2:0] + attribute \src "libresoc.v:109734.3-109751.6" + wire $1\fast_b_ok[0:0] + attribute \src "libresoc.v:109686.3-109700.6" + wire width 5 $1\reg_b[4:0] + attribute \src "libresoc.v:109701.3-109715.6" + wire $1\reg_b_ok[0:0] + attribute \src "libresoc.v:109716.3-109733.6" + wire width 3 $2\fast_b[2:0] + attribute \src "libresoc.v:109734.3-109751.6" + wire $2\fast_b_ok[0:0] + attribute \src "libresoc.v:109682.17-109682.117" + wire $eq$libresoc.v:109682$4225_Y + attribute \src "libresoc.v:109684.17-109684.117" + wire $eq$libresoc.v:109684$4227_Y + attribute \src "libresoc.v:109683.17-109683.107" + wire $not$libresoc.v:109683$4226_Y + attribute \src "libresoc.v:109685.17-109685.107" + wire $not$libresoc.v:109685$4228_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:198" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:198" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 7 \RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 6 \RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 input 8 \XL_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 output 4 \fast_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 5 \fast_b_ok + attribute \src "libresoc.v:109562.7-109562.15" + wire \initial + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 input 9 \internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 output 2 \reg_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 3 \reg_b_ok + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" + wire width 4 input 1 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:198" + cell $eq $eq$libresoc.v:109682$4225 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \internal_op + connect \B 7'0001000 + connect \Y $eq$libresoc.v:109682$4225_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:198" + cell $eq $eq$libresoc.v:109684$4227 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \internal_op + connect \B 7'0001000 + connect \Y $eq$libresoc.v:109684$4227_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" + cell $not $not$libresoc.v:109683$4226 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \XL_XO [9] + connect \Y $not$libresoc.v:109683$4226_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" + cell $not $not$libresoc.v:109685$4228 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \XL_XO [9] + connect \Y $not$libresoc.v:109685$4228_Y + end + attribute \src "libresoc.v:109562.7-109562.20" + process $proc$libresoc.v:109562$4233 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:109686.3-109700.6" + process $proc$libresoc.v:109686$4229 + assign { } { } + assign { } { } + assign $0\reg_b[4:0] $1\reg_b[4:0] + attribute \src "libresoc.v:109687.5-109687.29" + switch \initial + attribute \src "libresoc.v:109687.9-109687.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:185" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\reg_b[4:0] \RB + attribute \src "libresoc.v:0.0-0.0" + case 4'1101 + assign { } { } + assign $1\reg_b[4:0] \RS + case + assign $1\reg_b[4:0] 5'00000 + end + sync always + update \reg_b $0\reg_b[4:0] + end + attribute \src "libresoc.v:109701.3-109715.6" + process $proc$libresoc.v:109701$4230 + assign { } { } + assign { } { } + assign $0\reg_b_ok[0:0] $1\reg_b_ok[0:0] + attribute \src "libresoc.v:109702.5-109702.29" + switch \initial + attribute \src "libresoc.v:109702.9-109702.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:185" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\reg_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'1101 + assign { } { } + assign $1\reg_b_ok[0:0] 1'1 + case + assign $1\reg_b_ok[0:0] 1'0 + end + sync always + update \reg_b_ok $0\reg_b_ok[0:0] + end + attribute \src "libresoc.v:109716.3-109733.6" + process $proc$libresoc.v:109716$4231 + assign { } { } + assign { } { } + assign $0\fast_b[2:0] $1\fast_b[2:0] + attribute \src "libresoc.v:109717.5-109717.29" + switch \initial + attribute \src "libresoc.v:109717.9-109717.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:198" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fast_b[2:0] $2\fast_b[2:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" + switch { \XL_XO [5] \$3 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $2\fast_b[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $2\fast_b[2:0] 3'010 + case + assign $2\fast_b[2:0] 3'000 + end + case + assign $1\fast_b[2:0] 3'000 + end + sync always + update \fast_b $0\fast_b[2:0] + end + attribute \src "libresoc.v:109734.3-109751.6" + process $proc$libresoc.v:109734$4232 + assign { } { } + assign { } { } + assign $0\fast_b_ok[0:0] $1\fast_b_ok[0:0] + attribute \src "libresoc.v:109735.5-109735.29" + switch \initial + attribute \src "libresoc.v:109735.9-109735.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:198" + switch \$5 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fast_b_ok[0:0] $2\fast_b_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" + switch { \XL_XO [5] \$7 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $2\fast_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $2\fast_b_ok[0:0] 1'1 + case + assign $2\fast_b_ok[0:0] 1'0 + end + case + assign $1\fast_b_ok[0:0] 1'0 + end + sync always + update \fast_b_ok $0\fast_b_ok[0:0] + end + connect \$1 $eq$libresoc.v:109682$4225_Y + connect \$3 $not$libresoc.v:109683$4226_Y + connect \$5 $eq$libresoc.v:109684$4227_Y + connect \$7 $not$libresoc.v:109685$4228_Y +end +attribute \src "libresoc.v:109756.1-110009.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_ALU.dec_bi" +attribute \generator "nMigen" +module \dec_bi + attribute \src "libresoc.v:109983.3-109993.6" + wire width 16 $0\bd[15:0] + attribute \src "libresoc.v:109994.3-110004.6" + wire width 16 $0\ds[15:0] + attribute \src "libresoc.v:109845.3-109891.6" + wire width 64 $0\imm_b[63:0] + attribute \src "libresoc.v:109892.3-109938.6" + wire $0\imm_b_ok[0:0] + attribute \src "libresoc.v:109757.7-109757.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:109972.3-109982.6" + wire width 26 $0\li[25:0] + attribute \src "libresoc.v:109939.3-109949.6" + wire width 16 $0\si[15:0] + attribute \src "libresoc.v:109950.3-109960.6" + wire width 32 $0\si_hi[31:0] + attribute \src "libresoc.v:109961.3-109971.6" + wire width 16 $0\ui[15:0] + attribute \src "libresoc.v:109983.3-109993.6" + wire width 16 $1\bd[15:0] + attribute \src "libresoc.v:109994.3-110004.6" + wire width 16 $1\ds[15:0] + attribute \src "libresoc.v:109845.3-109891.6" + wire width 64 $1\imm_b[63:0] + attribute \src "libresoc.v:109892.3-109938.6" + wire $1\imm_b_ok[0:0] + attribute \src "libresoc.v:109972.3-109982.6" + wire width 26 $1\li[25:0] + attribute \src "libresoc.v:109939.3-109949.6" + wire width 16 $1\si[15:0] + attribute \src "libresoc.v:109950.3-109960.6" + wire width 32 $1\si_hi[31:0] + attribute \src "libresoc.v:109961.3-109971.6" + wire width 16 $1\ui[15:0] + attribute \src "libresoc.v:109835.17-109835.104" + wire width 64 $extend$libresoc.v:109835$4234_Y + attribute \src "libresoc.v:109836.18-109836.107" + wire width 64 $extend$libresoc.v:109836$4236_Y + attribute \src "libresoc.v:109839.17-109839.104" + wire width 64 $extend$libresoc.v:109839$4240_Y + attribute \src "libresoc.v:109843.17-109843.102" + wire width 64 $extend$libresoc.v:109843$4245_Y + attribute \src "libresoc.v:109835.17-109835.104" + wire width 64 $pos$libresoc.v:109835$4235_Y + attribute \src "libresoc.v:109836.18-109836.107" + wire width 64 $pos$libresoc.v:109836$4237_Y + attribute \src "libresoc.v:109839.17-109839.104" + wire width 64 $pos$libresoc.v:109839$4241_Y + attribute \src "libresoc.v:109843.17-109843.102" + wire width 64 $pos$libresoc.v:109843$4246_Y + attribute \src "libresoc.v:109837.18-109837.114" + wire width 47 $sshl$libresoc.v:109837$4238_Y + attribute \src "libresoc.v:109838.18-109838.113" + wire width 27 $sshl$libresoc.v:109838$4239_Y + attribute \src "libresoc.v:109840.18-109840.113" + wire width 17 $sshl$libresoc.v:109840$4242_Y + attribute \src "libresoc.v:109841.18-109841.113" + wire width 17 $sshl$libresoc.v:109841$4243_Y + attribute \src "libresoc.v:109842.17-109842.109" + wire width 47 $sshl$libresoc.v:109842$4244_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 64 \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 64 \$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" + wire width 47 \$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" + wire width 47 \$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:245" + wire width 27 \$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:245" + wire width 27 \$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" + wire width 17 \$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" + wire width 17 \$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" + wire width 17 \$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" + wire width 17 \$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" + wire width 64 \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" + wire width 47 \$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:259" + wire width 64 \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 64 \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 14 input 8 \ALU_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 14 input 9 \ALU_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 24 input 7 \ALU_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 5 \ALU_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 16 input 3 \ALU_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 16 input 4 \ALU_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 6 input 6 \ALU_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:249" + wire width 16 \bd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" + wire width 16 \ds + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 1 \imm_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 2 \imm_b_ok + attribute \src "libresoc.v:109757.7-109757.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + wire width 26 \li + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:216" + wire width 4 input 10 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:229" + wire width 16 \si + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:234" + wire width 32 \si_hi + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" + wire width 16 \ui + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + cell $pos $extend$libresoc.v:109835$4234 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 64 + connect \A \ALU_sh + connect \Y $extend$libresoc.v:109835$4234_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + cell $pos $extend$libresoc.v:109836$4236 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 64 + connect \A \ALU_SH32 + connect \Y $extend$libresoc.v:109836$4236_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + cell $pos $extend$libresoc.v:109839$4240 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \Y_WIDTH 64 + connect \A \ALU_UI + connect \Y $extend$libresoc.v:109839$4240_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" + cell $pos $extend$libresoc.v:109843$4245 + parameter \A_SIGNED 0 + parameter \A_WIDTH 47 + parameter \Y_WIDTH 64 + connect \A \$4 + connect \Y $extend$libresoc.v:109843$4245_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + cell $pos $pos$libresoc.v:109835$4235 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:109835$4234_Y + connect \Y $pos$libresoc.v:109835$4235_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + cell $pos $pos$libresoc.v:109836$4237 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:109836$4236_Y + connect \Y $pos$libresoc.v:109836$4237_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + cell $pos $pos$libresoc.v:109839$4241 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:109839$4240_Y + connect \Y $pos$libresoc.v:109839$4241_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" + cell $pos $pos$libresoc.v:109843$4246 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:109843$4245_Y + connect \Y $pos$libresoc.v:109843$4246_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" + cell $sshl $sshl$libresoc.v:109837$4238 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 47 + connect \A \ALU_SI + connect \B 5'10000 + connect \Y $sshl$libresoc.v:109837$4238_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:245" + cell $sshl $sshl$libresoc.v:109838$4239 + parameter \A_SIGNED 0 + parameter \A_WIDTH 24 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 27 + connect \A \ALU_LI + connect \B 2'10 + connect \Y $sshl$libresoc.v:109838$4239_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" + cell $sshl $sshl$libresoc.v:109840$4242 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 17 + connect \A \ALU_BD + connect \B 2'10 + connect \Y $sshl$libresoc.v:109840$4242_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" + cell $sshl $sshl$libresoc.v:109841$4243 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 17 + connect \A \ALU_DS + connect \B 2'10 + connect \Y $sshl$libresoc.v:109841$4243_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" + cell $sshl $sshl$libresoc.v:109842$4244 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 47 + connect \A \ui + connect \B 5'10000 + connect \Y $sshl$libresoc.v:109842$4244_Y + end + attribute \src "libresoc.v:109757.7-109757.20" + process $proc$libresoc.v:109757$4255 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:109845.3-109891.6" + process $proc$libresoc.v:109845$4247 + assign { } { } + assign { } { } + assign $0\imm_b[63:0] $1\imm_b[63:0] + attribute \src "libresoc.v:109846.5-109846.29" + switch \initial + attribute \src "libresoc.v:109846.9-109846.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\imm_b[63:0] \$1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\imm_b[63:0] { \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si } + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\imm_b[63:0] { \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi } + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\imm_b[63:0] \$3 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\imm_b[63:0] { \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li } + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\imm_b[63:0] { \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd } + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\imm_b[63:0] { \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds } + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\imm_b[63:0] \$7 + attribute \src "libresoc.v:0.0-0.0" + case 4'1010 + assign { } { } + assign $1\imm_b[63:0] \$9 + attribute \src "libresoc.v:0.0-0.0" + case 4'1011 + assign { } { } + assign $1\imm_b[63:0] \$11 + case + assign $1\imm_b[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \imm_b $0\imm_b[63:0] + end + attribute \src "libresoc.v:109892.3-109938.6" + process $proc$libresoc.v:109892$4248 + assign { } { } + assign { } { } + assign $0\imm_b_ok[0:0] $1\imm_b_ok[0:0] + attribute \src "libresoc.v:109893.5-109893.29" + switch \initial + attribute \src "libresoc.v:109893.9-109893.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'1010 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'1011 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + case + assign $1\imm_b_ok[0:0] 1'0 + end + sync always + update \imm_b_ok $0\imm_b_ok[0:0] + end + attribute \src "libresoc.v:109939.3-109949.6" + process $proc$libresoc.v:109939$4249 + assign { } { } + assign { } { } + assign $0\si[15:0] $1\si[15:0] + attribute \src "libresoc.v:109940.5-109940.29" + switch \initial + attribute \src "libresoc.v:109940.9-109940.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\si[15:0] \ALU_SI + case + assign $1\si[15:0] 16'0000000000000000 + end + sync always + update \si $0\si[15:0] + end + attribute \src "libresoc.v:109950.3-109960.6" + process $proc$libresoc.v:109950$4250 + assign { } { } + assign { } { } + assign $0\si_hi[31:0] $1\si_hi[31:0] + attribute \src "libresoc.v:109951.5-109951.29" + switch \initial + attribute \src "libresoc.v:109951.9-109951.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\si_hi[31:0] \$13 [31:0] + case + assign $1\si_hi[31:0] 0 + end + sync always + update \si_hi $0\si_hi[31:0] + end + attribute \src "libresoc.v:109961.3-109971.6" + process $proc$libresoc.v:109961$4251 + assign { } { } + assign { } { } + assign $0\ui[15:0] $1\ui[15:0] + attribute \src "libresoc.v:109962.5-109962.29" + switch \initial + attribute \src "libresoc.v:109962.9-109962.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\ui[15:0] \ALU_UI + case + assign $1\ui[15:0] 16'0000000000000000 + end + sync always + update \ui $0\ui[15:0] + end + attribute \src "libresoc.v:109972.3-109982.6" + process $proc$libresoc.v:109972$4252 + assign { } { } + assign { } { } + assign $0\li[25:0] $1\li[25:0] + attribute \src "libresoc.v:109973.5-109973.29" + switch \initial + attribute \src "libresoc.v:109973.9-109973.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\li[25:0] \$16 [25:0] + case + assign $1\li[25:0] 26'00000000000000000000000000 + end + sync always + update \li $0\li[25:0] + end + attribute \src "libresoc.v:109983.3-109993.6" + process $proc$libresoc.v:109983$4253 + assign { } { } + assign { } { } + assign $0\bd[15:0] $1\bd[15:0] + attribute \src "libresoc.v:109984.5-109984.29" + switch \initial + attribute \src "libresoc.v:109984.9-109984.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\bd[15:0] \$19 [15:0] + case + assign $1\bd[15:0] 16'0000000000000000 + end + sync always + update \bd $0\bd[15:0] + end + attribute \src "libresoc.v:109994.3-110004.6" + process $proc$libresoc.v:109994$4254 + assign { } { } + assign { } { } + assign $0\ds[15:0] $1\ds[15:0] + attribute \src "libresoc.v:109995.5-109995.29" + switch \initial + attribute \src "libresoc.v:109995.9-109995.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\ds[15:0] \$22 [15:0] + case + assign $1\ds[15:0] 16'0000000000000000 + end + sync always + update \ds $0\ds[15:0] + end + connect \$9 $pos$libresoc.v:109835$4235_Y + connect \$11 $pos$libresoc.v:109836$4237_Y + connect \$14 $sshl$libresoc.v:109837$4238_Y + connect \$17 $sshl$libresoc.v:109838$4239_Y + connect \$1 $pos$libresoc.v:109839$4241_Y + connect \$20 $sshl$libresoc.v:109840$4242_Y + connect \$23 $sshl$libresoc.v:109841$4243_Y + connect \$4 $sshl$libresoc.v:109842$4244_Y + connect \$3 $pos$libresoc.v:109843$4246_Y + connect \$7 64'1111111111111111111111111111111111111111111111111111111111111111 + connect \$13 \$14 + connect \$16 \$17 + connect \$19 \$20 + connect \$22 \$23 +end +attribute \src "libresoc.v:110013.1-110266.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_BRANCH.dec_bi" +attribute \generator "nMigen" +module \dec_bi$151 + attribute \src "libresoc.v:110240.3-110250.6" + wire width 16 $0\bd[15:0] + attribute \src "libresoc.v:110251.3-110261.6" + wire width 16 $0\ds[15:0] + attribute \src "libresoc.v:110102.3-110148.6" + wire width 64 $0\imm_b[63:0] + attribute \src "libresoc.v:110149.3-110195.6" + wire $0\imm_b_ok[0:0] + attribute \src "libresoc.v:110014.7-110014.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:110229.3-110239.6" + wire width 26 $0\li[25:0] + attribute \src "libresoc.v:110196.3-110206.6" + wire width 16 $0\si[15:0] + attribute \src "libresoc.v:110207.3-110217.6" + wire width 32 $0\si_hi[31:0] + attribute \src "libresoc.v:110218.3-110228.6" + wire width 16 $0\ui[15:0] + attribute \src "libresoc.v:110240.3-110250.6" + wire width 16 $1\bd[15:0] + attribute \src "libresoc.v:110251.3-110261.6" + wire width 16 $1\ds[15:0] + attribute \src "libresoc.v:110102.3-110148.6" + wire width 64 $1\imm_b[63:0] + attribute \src "libresoc.v:110149.3-110195.6" + wire $1\imm_b_ok[0:0] + attribute \src "libresoc.v:110229.3-110239.6" + wire width 26 $1\li[25:0] + attribute \src "libresoc.v:110196.3-110206.6" + wire width 16 $1\si[15:0] + attribute \src "libresoc.v:110207.3-110217.6" + wire width 32 $1\si_hi[31:0] + attribute \src "libresoc.v:110218.3-110228.6" + wire width 16 $1\ui[15:0] + attribute \src "libresoc.v:110092.17-110092.107" + wire width 64 $extend$libresoc.v:110092$4256_Y + attribute \src "libresoc.v:110093.18-110093.110" + wire width 64 $extend$libresoc.v:110093$4258_Y + attribute \src "libresoc.v:110096.17-110096.107" + wire width 64 $extend$libresoc.v:110096$4262_Y + attribute \src "libresoc.v:110100.17-110100.102" + wire width 64 $extend$libresoc.v:110100$4267_Y + attribute \src "libresoc.v:110092.17-110092.107" + wire width 64 $pos$libresoc.v:110092$4257_Y + attribute \src "libresoc.v:110093.18-110093.110" + wire width 64 $pos$libresoc.v:110093$4259_Y + attribute \src "libresoc.v:110096.17-110096.107" + wire width 64 $pos$libresoc.v:110096$4263_Y + attribute \src "libresoc.v:110100.17-110100.102" + wire width 64 $pos$libresoc.v:110100$4268_Y + attribute \src "libresoc.v:110094.18-110094.117" + wire width 47 $sshl$libresoc.v:110094$4260_Y + attribute \src "libresoc.v:110095.18-110095.116" + wire width 27 $sshl$libresoc.v:110095$4261_Y + attribute \src "libresoc.v:110097.18-110097.116" + wire width 17 $sshl$libresoc.v:110097$4264_Y + attribute \src "libresoc.v:110098.18-110098.116" + wire width 17 $sshl$libresoc.v:110098$4265_Y + attribute \src "libresoc.v:110099.17-110099.109" + wire width 47 $sshl$libresoc.v:110099$4266_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 64 \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 64 \$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" + wire width 47 \$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" + wire width 47 \$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:245" + wire width 27 \$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:245" + wire width 27 \$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" + wire width 17 \$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" + wire width 17 \$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" + wire width 17 \$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" + wire width 17 \$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" + wire width 64 \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" + wire width 47 \$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:259" + wire width 64 \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 64 \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 14 input 8 \BRANCH_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 14 input 9 \BRANCH_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 24 input 7 \BRANCH_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 5 \BRANCH_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 16 input 3 \BRANCH_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 16 input 4 \BRANCH_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 6 input 6 \BRANCH_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:249" + wire width 16 \bd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" + wire width 16 \ds + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 1 \imm_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 2 \imm_b_ok + attribute \src "libresoc.v:110014.7-110014.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + wire width 26 \li + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:216" + wire width 4 input 10 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:229" + wire width 16 \si + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:234" + wire width 32 \si_hi + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" + wire width 16 \ui + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + cell $pos $extend$libresoc.v:110092$4256 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 64 + connect \A \BRANCH_sh + connect \Y $extend$libresoc.v:110092$4256_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + cell $pos $extend$libresoc.v:110093$4258 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 64 + connect \A \BRANCH_SH32 + connect \Y $extend$libresoc.v:110093$4258_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + cell $pos $extend$libresoc.v:110096$4262 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \Y_WIDTH 64 + connect \A \BRANCH_UI + connect \Y $extend$libresoc.v:110096$4262_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" + cell $pos $extend$libresoc.v:110100$4267 + parameter \A_SIGNED 0 + parameter \A_WIDTH 47 + parameter \Y_WIDTH 64 + connect \A \$4 + connect \Y $extend$libresoc.v:110100$4267_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + cell $pos $pos$libresoc.v:110092$4257 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:110092$4256_Y + connect \Y $pos$libresoc.v:110092$4257_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + cell $pos $pos$libresoc.v:110093$4259 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:110093$4258_Y + connect \Y $pos$libresoc.v:110093$4259_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + cell $pos $pos$libresoc.v:110096$4263 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:110096$4262_Y + connect \Y $pos$libresoc.v:110096$4263_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" + cell $pos $pos$libresoc.v:110100$4268 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:110100$4267_Y + connect \Y $pos$libresoc.v:110100$4268_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" + cell $sshl $sshl$libresoc.v:110094$4260 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 47 + connect \A \BRANCH_SI + connect \B 5'10000 + connect \Y $sshl$libresoc.v:110094$4260_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:245" + cell $sshl $sshl$libresoc.v:110095$4261 + parameter \A_SIGNED 0 + parameter \A_WIDTH 24 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 27 + connect \A \BRANCH_LI + connect \B 2'10 + connect \Y $sshl$libresoc.v:110095$4261_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" + cell $sshl $sshl$libresoc.v:110097$4264 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 17 + connect \A \BRANCH_BD + connect \B 2'10 + connect \Y $sshl$libresoc.v:110097$4264_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" + cell $sshl $sshl$libresoc.v:110098$4265 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 17 + connect \A \BRANCH_DS + connect \B 2'10 + connect \Y $sshl$libresoc.v:110098$4265_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" + cell $sshl $sshl$libresoc.v:110099$4266 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 47 + connect \A \ui + connect \B 5'10000 + connect \Y $sshl$libresoc.v:110099$4266_Y + end + attribute \src "libresoc.v:110014.7-110014.20" + process $proc$libresoc.v:110014$4277 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:110102.3-110148.6" + process $proc$libresoc.v:110102$4269 + assign { } { } + assign { } { } + assign $0\imm_b[63:0] $1\imm_b[63:0] + attribute \src "libresoc.v:110103.5-110103.29" + switch \initial + attribute \src "libresoc.v:110103.9-110103.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\imm_b[63:0] \$1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\imm_b[63:0] { \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si } + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\imm_b[63:0] { \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi } + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\imm_b[63:0] \$3 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\imm_b[63:0] { \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li } + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\imm_b[63:0] { \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd } + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\imm_b[63:0] { \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds } + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\imm_b[63:0] \$7 + attribute \src "libresoc.v:0.0-0.0" + case 4'1010 + assign { } { } + assign $1\imm_b[63:0] \$9 + attribute \src "libresoc.v:0.0-0.0" + case 4'1011 + assign { } { } + assign $1\imm_b[63:0] \$11 + case + assign $1\imm_b[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \imm_b $0\imm_b[63:0] + end + attribute \src "libresoc.v:110149.3-110195.6" + process $proc$libresoc.v:110149$4270 + assign { } { } + assign { } { } + assign $0\imm_b_ok[0:0] $1\imm_b_ok[0:0] + attribute \src "libresoc.v:110150.5-110150.29" + switch \initial + attribute \src "libresoc.v:110150.9-110150.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'1010 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'1011 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + case + assign $1\imm_b_ok[0:0] 1'0 + end + sync always + update \imm_b_ok $0\imm_b_ok[0:0] + end + attribute \src "libresoc.v:110196.3-110206.6" + process $proc$libresoc.v:110196$4271 + assign { } { } + assign { } { } + assign $0\si[15:0] $1\si[15:0] + attribute \src "libresoc.v:110197.5-110197.29" + switch \initial + attribute \src "libresoc.v:110197.9-110197.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\si[15:0] \BRANCH_SI + case + assign $1\si[15:0] 16'0000000000000000 + end + sync always + update \si $0\si[15:0] + end + attribute \src "libresoc.v:110207.3-110217.6" + process $proc$libresoc.v:110207$4272 + assign { } { } + assign { } { } + assign $0\si_hi[31:0] $1\si_hi[31:0] + attribute \src "libresoc.v:110208.5-110208.29" + switch \initial + attribute \src "libresoc.v:110208.9-110208.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\si_hi[31:0] \$13 [31:0] + case + assign $1\si_hi[31:0] 0 + end + sync always + update \si_hi $0\si_hi[31:0] + end + attribute \src "libresoc.v:110218.3-110228.6" + process $proc$libresoc.v:110218$4273 + assign { } { } + assign { } { } + assign $0\ui[15:0] $1\ui[15:0] + attribute \src "libresoc.v:110219.5-110219.29" + switch \initial + attribute \src "libresoc.v:110219.9-110219.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\ui[15:0] \BRANCH_UI + case + assign $1\ui[15:0] 16'0000000000000000 + end + sync always + update \ui $0\ui[15:0] + end + attribute \src "libresoc.v:110229.3-110239.6" + process $proc$libresoc.v:110229$4274 + assign { } { } + assign { } { } + assign $0\li[25:0] $1\li[25:0] + attribute \src "libresoc.v:110230.5-110230.29" + switch \initial + attribute \src "libresoc.v:110230.9-110230.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\li[25:0] \$16 [25:0] + case + assign $1\li[25:0] 26'00000000000000000000000000 + end + sync always + update \li $0\li[25:0] + end + attribute \src "libresoc.v:110240.3-110250.6" + process $proc$libresoc.v:110240$4275 + assign { } { } + assign { } { } + assign $0\bd[15:0] $1\bd[15:0] + attribute \src "libresoc.v:110241.5-110241.29" + switch \initial + attribute \src "libresoc.v:110241.9-110241.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\bd[15:0] \$19 [15:0] + case + assign $1\bd[15:0] 16'0000000000000000 + end + sync always + update \bd $0\bd[15:0] + end + attribute \src "libresoc.v:110251.3-110261.6" + process $proc$libresoc.v:110251$4276 + assign { } { } + assign { } { } + assign $0\ds[15:0] $1\ds[15:0] + attribute \src "libresoc.v:110252.5-110252.29" + switch \initial + attribute \src "libresoc.v:110252.9-110252.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\ds[15:0] \$22 [15:0] + case + assign $1\ds[15:0] 16'0000000000000000 + end + sync always + update \ds $0\ds[15:0] + end + connect \$9 $pos$libresoc.v:110092$4257_Y + connect \$11 $pos$libresoc.v:110093$4259_Y + connect \$14 $sshl$libresoc.v:110094$4260_Y + connect \$17 $sshl$libresoc.v:110095$4261_Y + connect \$1 $pos$libresoc.v:110096$4263_Y + connect \$20 $sshl$libresoc.v:110097$4264_Y + connect \$23 $sshl$libresoc.v:110098$4265_Y + connect \$4 $sshl$libresoc.v:110099$4266_Y + connect \$3 $pos$libresoc.v:110100$4268_Y + connect \$7 64'1111111111111111111111111111111111111111111111111111111111111111 + connect \$13 \$14 + connect \$16 \$17 + connect \$19 \$20 + connect \$22 \$23 +end +attribute \src "libresoc.v:110270.1-110523.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_LOGICAL.dec_bi" +attribute \generator "nMigen" +module \dec_bi$160 + attribute \src "libresoc.v:110497.3-110507.6" + wire width 16 $0\bd[15:0] + attribute \src "libresoc.v:110508.3-110518.6" + wire width 16 $0\ds[15:0] + attribute \src "libresoc.v:110359.3-110405.6" + wire width 64 $0\imm_b[63:0] + attribute \src "libresoc.v:110406.3-110452.6" + wire $0\imm_b_ok[0:0] + attribute \src "libresoc.v:110271.7-110271.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:110486.3-110496.6" + wire width 26 $0\li[25:0] + attribute \src "libresoc.v:110453.3-110463.6" + wire width 16 $0\si[15:0] + attribute \src "libresoc.v:110464.3-110474.6" + wire width 32 $0\si_hi[31:0] + attribute \src "libresoc.v:110475.3-110485.6" + wire width 16 $0\ui[15:0] + attribute \src "libresoc.v:110497.3-110507.6" + wire width 16 $1\bd[15:0] + attribute \src "libresoc.v:110508.3-110518.6" + wire width 16 $1\ds[15:0] + attribute \src "libresoc.v:110359.3-110405.6" + wire width 64 $1\imm_b[63:0] + attribute \src "libresoc.v:110406.3-110452.6" + wire $1\imm_b_ok[0:0] + attribute \src "libresoc.v:110486.3-110496.6" + wire width 26 $1\li[25:0] + attribute \src "libresoc.v:110453.3-110463.6" + wire width 16 $1\si[15:0] + attribute \src "libresoc.v:110464.3-110474.6" + wire width 32 $1\si_hi[31:0] + attribute \src "libresoc.v:110475.3-110485.6" + wire width 16 $1\ui[15:0] + attribute \src "libresoc.v:110349.17-110349.108" + wire width 64 $extend$libresoc.v:110349$4278_Y + attribute \src "libresoc.v:110350.18-110350.111" + wire width 64 $extend$libresoc.v:110350$4280_Y + attribute \src "libresoc.v:110353.17-110353.108" + wire width 64 $extend$libresoc.v:110353$4284_Y + attribute \src "libresoc.v:110357.17-110357.102" + wire width 64 $extend$libresoc.v:110357$4289_Y + attribute \src "libresoc.v:110349.17-110349.108" + wire width 64 $pos$libresoc.v:110349$4279_Y + attribute \src "libresoc.v:110350.18-110350.111" + wire width 64 $pos$libresoc.v:110350$4281_Y + attribute \src "libresoc.v:110353.17-110353.108" + wire width 64 $pos$libresoc.v:110353$4285_Y + attribute \src "libresoc.v:110357.17-110357.102" + wire width 64 $pos$libresoc.v:110357$4290_Y + attribute \src "libresoc.v:110351.18-110351.118" + wire width 47 $sshl$libresoc.v:110351$4282_Y + attribute \src "libresoc.v:110352.18-110352.117" + wire width 27 $sshl$libresoc.v:110352$4283_Y + attribute \src "libresoc.v:110354.18-110354.117" + wire width 17 $sshl$libresoc.v:110354$4286_Y + attribute \src "libresoc.v:110355.18-110355.117" + wire width 17 $sshl$libresoc.v:110355$4287_Y + attribute \src "libresoc.v:110356.17-110356.109" + wire width 47 $sshl$libresoc.v:110356$4288_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 64 \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 64 \$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" + wire width 47 \$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" + wire width 47 \$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:245" + wire width 27 \$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:245" + wire width 27 \$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" + wire width 17 \$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" + wire width 17 \$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" + wire width 17 \$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" + wire width 17 \$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" + wire width 64 \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" + wire width 47 \$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:259" + wire width 64 \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 64 \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 14 input 8 \LOGICAL_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 14 input 9 \LOGICAL_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 24 input 7 \LOGICAL_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 5 \LOGICAL_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 16 input 3 \LOGICAL_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 16 input 4 \LOGICAL_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 6 input 6 \LOGICAL_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:249" + wire width 16 \bd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" + wire width 16 \ds + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 1 \imm_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 2 \imm_b_ok + attribute \src "libresoc.v:110271.7-110271.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + wire width 26 \li + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:216" + wire width 4 input 10 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:229" + wire width 16 \si + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:234" + wire width 32 \si_hi + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" + wire width 16 \ui + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + cell $pos $extend$libresoc.v:110349$4278 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 64 + connect \A \LOGICAL_sh + connect \Y $extend$libresoc.v:110349$4278_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + cell $pos $extend$libresoc.v:110350$4280 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 64 + connect \A \LOGICAL_SH32 + connect \Y $extend$libresoc.v:110350$4280_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + cell $pos $extend$libresoc.v:110353$4284 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \Y_WIDTH 64 + connect \A \LOGICAL_UI + connect \Y $extend$libresoc.v:110353$4284_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" + cell $pos $extend$libresoc.v:110357$4289 + parameter \A_SIGNED 0 + parameter \A_WIDTH 47 + parameter \Y_WIDTH 64 + connect \A \$4 + connect \Y $extend$libresoc.v:110357$4289_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + cell $pos $pos$libresoc.v:110349$4279 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:110349$4278_Y + connect \Y $pos$libresoc.v:110349$4279_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + cell $pos $pos$libresoc.v:110350$4281 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:110350$4280_Y + connect \Y $pos$libresoc.v:110350$4281_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + cell $pos $pos$libresoc.v:110353$4285 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:110353$4284_Y + connect \Y $pos$libresoc.v:110353$4285_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" + cell $pos $pos$libresoc.v:110357$4290 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:110357$4289_Y + connect \Y $pos$libresoc.v:110357$4290_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" + cell $sshl $sshl$libresoc.v:110351$4282 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 47 + connect \A \LOGICAL_SI + connect \B 5'10000 + connect \Y $sshl$libresoc.v:110351$4282_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:245" + cell $sshl $sshl$libresoc.v:110352$4283 + parameter \A_SIGNED 0 + parameter \A_WIDTH 24 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 27 + connect \A \LOGICAL_LI + connect \B 2'10 + connect \Y $sshl$libresoc.v:110352$4283_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" + cell $sshl $sshl$libresoc.v:110354$4286 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 17 + connect \A \LOGICAL_BD + connect \B 2'10 + connect \Y $sshl$libresoc.v:110354$4286_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" + cell $sshl $sshl$libresoc.v:110355$4287 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 17 + connect \A \LOGICAL_DS + connect \B 2'10 + connect \Y $sshl$libresoc.v:110355$4287_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" + cell $sshl $sshl$libresoc.v:110356$4288 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 47 + connect \A \ui + connect \B 5'10000 + connect \Y $sshl$libresoc.v:110356$4288_Y + end + attribute \src "libresoc.v:110271.7-110271.20" + process $proc$libresoc.v:110271$4299 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:110359.3-110405.6" + process $proc$libresoc.v:110359$4291 + assign { } { } + assign { } { } + assign $0\imm_b[63:0] $1\imm_b[63:0] + attribute \src "libresoc.v:110360.5-110360.29" + switch \initial + attribute \src "libresoc.v:110360.9-110360.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\imm_b[63:0] \$1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\imm_b[63:0] { \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si } + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\imm_b[63:0] { \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi } + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\imm_b[63:0] \$3 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\imm_b[63:0] { \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li } + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\imm_b[63:0] { \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd } + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\imm_b[63:0] { \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds } + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\imm_b[63:0] \$7 + attribute \src "libresoc.v:0.0-0.0" + case 4'1010 + assign { } { } + assign $1\imm_b[63:0] \$9 + attribute \src "libresoc.v:0.0-0.0" + case 4'1011 + assign { } { } + assign $1\imm_b[63:0] \$11 + case + assign $1\imm_b[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \imm_b $0\imm_b[63:0] + end + attribute \src "libresoc.v:110406.3-110452.6" + process $proc$libresoc.v:110406$4292 + assign { } { } + assign { } { } + assign $0\imm_b_ok[0:0] $1\imm_b_ok[0:0] + attribute \src "libresoc.v:110407.5-110407.29" + switch \initial + attribute \src "libresoc.v:110407.9-110407.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'1010 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'1011 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + case + assign $1\imm_b_ok[0:0] 1'0 + end + sync always + update \imm_b_ok $0\imm_b_ok[0:0] + end + attribute \src "libresoc.v:110453.3-110463.6" + process $proc$libresoc.v:110453$4293 + assign { } { } + assign { } { } + assign $0\si[15:0] $1\si[15:0] + attribute \src "libresoc.v:110454.5-110454.29" + switch \initial + attribute \src "libresoc.v:110454.9-110454.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\si[15:0] \LOGICAL_SI + case + assign $1\si[15:0] 16'0000000000000000 + end + sync always + update \si $0\si[15:0] + end + attribute \src "libresoc.v:110464.3-110474.6" + process $proc$libresoc.v:110464$4294 + assign { } { } + assign { } { } + assign $0\si_hi[31:0] $1\si_hi[31:0] + attribute \src "libresoc.v:110465.5-110465.29" + switch \initial + attribute \src "libresoc.v:110465.9-110465.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\si_hi[31:0] \$13 [31:0] + case + assign $1\si_hi[31:0] 0 + end + sync always + update \si_hi $0\si_hi[31:0] + end + attribute \src "libresoc.v:110475.3-110485.6" + process $proc$libresoc.v:110475$4295 + assign { } { } + assign { } { } + assign $0\ui[15:0] $1\ui[15:0] + attribute \src "libresoc.v:110476.5-110476.29" + switch \initial + attribute \src "libresoc.v:110476.9-110476.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\ui[15:0] \LOGICAL_UI + case + assign $1\ui[15:0] 16'0000000000000000 + end + sync always + update \ui $0\ui[15:0] + end + attribute \src "libresoc.v:110486.3-110496.6" + process $proc$libresoc.v:110486$4296 + assign { } { } + assign { } { } + assign $0\li[25:0] $1\li[25:0] + attribute \src "libresoc.v:110487.5-110487.29" + switch \initial + attribute \src "libresoc.v:110487.9-110487.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\li[25:0] \$16 [25:0] + case + assign $1\li[25:0] 26'00000000000000000000000000 + end + sync always + update \li $0\li[25:0] + end + attribute \src "libresoc.v:110497.3-110507.6" + process $proc$libresoc.v:110497$4297 + assign { } { } + assign { } { } + assign $0\bd[15:0] $1\bd[15:0] + attribute \src "libresoc.v:110498.5-110498.29" + switch \initial + attribute \src "libresoc.v:110498.9-110498.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\bd[15:0] \$19 [15:0] + case + assign $1\bd[15:0] 16'0000000000000000 + end + sync always + update \bd $0\bd[15:0] + end + attribute \src "libresoc.v:110508.3-110518.6" + process $proc$libresoc.v:110508$4298 + assign { } { } + assign { } { } + assign $0\ds[15:0] $1\ds[15:0] + attribute \src "libresoc.v:110509.5-110509.29" + switch \initial + attribute \src "libresoc.v:110509.9-110509.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\ds[15:0] \$22 [15:0] + case + assign $1\ds[15:0] 16'0000000000000000 + end + sync always + update \ds $0\ds[15:0] + end + connect \$9 $pos$libresoc.v:110349$4279_Y + connect \$11 $pos$libresoc.v:110350$4281_Y + connect \$14 $sshl$libresoc.v:110351$4282_Y + connect \$17 $sshl$libresoc.v:110352$4283_Y + connect \$1 $pos$libresoc.v:110353$4285_Y + connect \$20 $sshl$libresoc.v:110354$4286_Y + connect \$23 $sshl$libresoc.v:110355$4287_Y + connect \$4 $sshl$libresoc.v:110356$4288_Y + connect \$3 $pos$libresoc.v:110357$4290_Y + connect \$7 64'1111111111111111111111111111111111111111111111111111111111111111 + connect \$13 \$14 + connect \$16 \$17 + connect \$19 \$20 + connect \$22 \$23 +end +attribute \src "libresoc.v:110527.1-110780.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_DIV.dec_bi" +attribute \generator "nMigen" +module \dec_bi$176 + attribute \src "libresoc.v:110754.3-110764.6" + wire width 16 $0\bd[15:0] + attribute \src "libresoc.v:110765.3-110775.6" + wire width 16 $0\ds[15:0] + attribute \src "libresoc.v:110616.3-110662.6" + wire width 64 $0\imm_b[63:0] + attribute \src "libresoc.v:110663.3-110709.6" + wire $0\imm_b_ok[0:0] + attribute \src "libresoc.v:110528.7-110528.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:110743.3-110753.6" + wire width 26 $0\li[25:0] + attribute \src "libresoc.v:110710.3-110720.6" + wire width 16 $0\si[15:0] + attribute \src "libresoc.v:110721.3-110731.6" + wire width 32 $0\si_hi[31:0] + attribute \src "libresoc.v:110732.3-110742.6" + wire width 16 $0\ui[15:0] + attribute \src "libresoc.v:110754.3-110764.6" + wire width 16 $1\bd[15:0] + attribute \src "libresoc.v:110765.3-110775.6" + wire width 16 $1\ds[15:0] + attribute \src "libresoc.v:110616.3-110662.6" + wire width 64 $1\imm_b[63:0] + attribute \src "libresoc.v:110663.3-110709.6" + wire $1\imm_b_ok[0:0] + attribute \src "libresoc.v:110743.3-110753.6" + wire width 26 $1\li[25:0] + attribute \src "libresoc.v:110710.3-110720.6" + wire width 16 $1\si[15:0] + attribute \src "libresoc.v:110721.3-110731.6" + wire width 32 $1\si_hi[31:0] + attribute \src "libresoc.v:110732.3-110742.6" + wire width 16 $1\ui[15:0] + attribute \src "libresoc.v:110606.17-110606.104" + wire width 64 $extend$libresoc.v:110606$4300_Y + attribute \src "libresoc.v:110607.18-110607.107" + wire width 64 $extend$libresoc.v:110607$4302_Y + attribute \src "libresoc.v:110610.17-110610.104" + wire width 64 $extend$libresoc.v:110610$4306_Y + attribute \src "libresoc.v:110614.17-110614.102" + wire width 64 $extend$libresoc.v:110614$4311_Y + attribute \src "libresoc.v:110606.17-110606.104" + wire width 64 $pos$libresoc.v:110606$4301_Y + attribute \src "libresoc.v:110607.18-110607.107" + wire width 64 $pos$libresoc.v:110607$4303_Y + attribute \src "libresoc.v:110610.17-110610.104" + wire width 64 $pos$libresoc.v:110610$4307_Y + attribute \src "libresoc.v:110614.17-110614.102" + wire width 64 $pos$libresoc.v:110614$4312_Y + attribute \src "libresoc.v:110608.18-110608.114" + wire width 47 $sshl$libresoc.v:110608$4304_Y + attribute \src "libresoc.v:110609.18-110609.113" + wire width 27 $sshl$libresoc.v:110609$4305_Y + attribute \src "libresoc.v:110611.18-110611.113" + wire width 17 $sshl$libresoc.v:110611$4308_Y + attribute \src "libresoc.v:110612.18-110612.113" + wire width 17 $sshl$libresoc.v:110612$4309_Y + attribute \src "libresoc.v:110613.17-110613.109" + wire width 47 $sshl$libresoc.v:110613$4310_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 64 \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 64 \$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" + wire width 47 \$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" + wire width 47 \$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:245" + wire width 27 \$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:245" + wire width 27 \$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" + wire width 17 \$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" + wire width 17 \$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" + wire width 17 \$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" + wire width 17 \$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" + wire width 64 \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" + wire width 47 \$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:259" + wire width 64 \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 64 \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 14 input 8 \DIV_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 14 input 9 \DIV_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 24 input 7 \DIV_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 5 \DIV_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 16 input 3 \DIV_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 16 input 4 \DIV_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 6 input 6 \DIV_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:249" + wire width 16 \bd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" + wire width 16 \ds + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 1 \imm_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 2 \imm_b_ok + attribute \src "libresoc.v:110528.7-110528.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + wire width 26 \li + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:216" + wire width 4 input 10 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:229" + wire width 16 \si + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:234" + wire width 32 \si_hi + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" + wire width 16 \ui + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + cell $pos $extend$libresoc.v:110606$4300 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 64 + connect \A \DIV_sh + connect \Y $extend$libresoc.v:110606$4300_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + cell $pos $extend$libresoc.v:110607$4302 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 64 + connect \A \DIV_SH32 + connect \Y $extend$libresoc.v:110607$4302_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + cell $pos $extend$libresoc.v:110610$4306 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \Y_WIDTH 64 + connect \A \DIV_UI + connect \Y $extend$libresoc.v:110610$4306_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" + cell $pos $extend$libresoc.v:110614$4311 + parameter \A_SIGNED 0 + parameter \A_WIDTH 47 + parameter \Y_WIDTH 64 + connect \A \$4 + connect \Y $extend$libresoc.v:110614$4311_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + cell $pos $pos$libresoc.v:110606$4301 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:110606$4300_Y + connect \Y $pos$libresoc.v:110606$4301_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + cell $pos $pos$libresoc.v:110607$4303 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:110607$4302_Y + connect \Y $pos$libresoc.v:110607$4303_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + cell $pos $pos$libresoc.v:110610$4307 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:110610$4306_Y + connect \Y $pos$libresoc.v:110610$4307_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" + cell $pos $pos$libresoc.v:110614$4312 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:110614$4311_Y + connect \Y $pos$libresoc.v:110614$4312_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" + cell $sshl $sshl$libresoc.v:110608$4304 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 47 + connect \A \DIV_SI + connect \B 5'10000 + connect \Y $sshl$libresoc.v:110608$4304_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:245" + cell $sshl $sshl$libresoc.v:110609$4305 + parameter \A_SIGNED 0 + parameter \A_WIDTH 24 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 27 + connect \A \DIV_LI + connect \B 2'10 + connect \Y $sshl$libresoc.v:110609$4305_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" + cell $sshl $sshl$libresoc.v:110611$4308 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 17 + connect \A \DIV_BD + connect \B 2'10 + connect \Y $sshl$libresoc.v:110611$4308_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" + cell $sshl $sshl$libresoc.v:110612$4309 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 17 + connect \A \DIV_DS + connect \B 2'10 + connect \Y $sshl$libresoc.v:110612$4309_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" + cell $sshl $sshl$libresoc.v:110613$4310 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 47 + connect \A \ui + connect \B 5'10000 + connect \Y $sshl$libresoc.v:110613$4310_Y + end + attribute \src "libresoc.v:110528.7-110528.20" + process $proc$libresoc.v:110528$4321 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:110616.3-110662.6" + process $proc$libresoc.v:110616$4313 + assign { } { } + assign { } { } + assign $0\imm_b[63:0] $1\imm_b[63:0] + attribute \src "libresoc.v:110617.5-110617.29" + switch \initial + attribute \src "libresoc.v:110617.9-110617.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\imm_b[63:0] \$1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\imm_b[63:0] { \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si } + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\imm_b[63:0] { \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi } + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\imm_b[63:0] \$3 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\imm_b[63:0] { \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li } + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\imm_b[63:0] { \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd } + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\imm_b[63:0] { \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds } + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\imm_b[63:0] \$7 + attribute \src "libresoc.v:0.0-0.0" + case 4'1010 + assign { } { } + assign $1\imm_b[63:0] \$9 + attribute \src "libresoc.v:0.0-0.0" + case 4'1011 + assign { } { } + assign $1\imm_b[63:0] \$11 + case + assign $1\imm_b[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \imm_b $0\imm_b[63:0] + end + attribute \src "libresoc.v:110663.3-110709.6" + process $proc$libresoc.v:110663$4314 + assign { } { } + assign { } { } + assign $0\imm_b_ok[0:0] $1\imm_b_ok[0:0] + attribute \src "libresoc.v:110664.5-110664.29" + switch \initial + attribute \src "libresoc.v:110664.9-110664.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'1010 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'1011 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + case + assign $1\imm_b_ok[0:0] 1'0 + end + sync always + update \imm_b_ok $0\imm_b_ok[0:0] + end + attribute \src "libresoc.v:110710.3-110720.6" + process $proc$libresoc.v:110710$4315 + assign { } { } + assign { } { } + assign $0\si[15:0] $1\si[15:0] + attribute \src "libresoc.v:110711.5-110711.29" + switch \initial + attribute \src "libresoc.v:110711.9-110711.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\si[15:0] \DIV_SI + case + assign $1\si[15:0] 16'0000000000000000 + end + sync always + update \si $0\si[15:0] + end + attribute \src "libresoc.v:110721.3-110731.6" + process $proc$libresoc.v:110721$4316 + assign { } { } + assign { } { } + assign $0\si_hi[31:0] $1\si_hi[31:0] + attribute \src "libresoc.v:110722.5-110722.29" + switch \initial + attribute \src "libresoc.v:110722.9-110722.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\si_hi[31:0] \$13 [31:0] + case + assign $1\si_hi[31:0] 0 + end + sync always + update \si_hi $0\si_hi[31:0] + end + attribute \src "libresoc.v:110732.3-110742.6" + process $proc$libresoc.v:110732$4317 + assign { } { } + assign { } { } + assign $0\ui[15:0] $1\ui[15:0] + attribute \src "libresoc.v:110733.5-110733.29" + switch \initial + attribute \src "libresoc.v:110733.9-110733.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\ui[15:0] \DIV_UI + case + assign $1\ui[15:0] 16'0000000000000000 + end + sync always + update \ui $0\ui[15:0] + end + attribute \src "libresoc.v:110743.3-110753.6" + process $proc$libresoc.v:110743$4318 + assign { } { } + assign { } { } + assign $0\li[25:0] $1\li[25:0] + attribute \src "libresoc.v:110744.5-110744.29" + switch \initial + attribute \src "libresoc.v:110744.9-110744.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\li[25:0] \$16 [25:0] + case + assign $1\li[25:0] 26'00000000000000000000000000 + end + sync always + update \li $0\li[25:0] + end + attribute \src "libresoc.v:110754.3-110764.6" + process $proc$libresoc.v:110754$4319 + assign { } { } + assign { } { } + assign $0\bd[15:0] $1\bd[15:0] + attribute \src "libresoc.v:110755.5-110755.29" + switch \initial + attribute \src "libresoc.v:110755.9-110755.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\bd[15:0] \$19 [15:0] + case + assign $1\bd[15:0] 16'0000000000000000 + end + sync always + update \bd $0\bd[15:0] + end + attribute \src "libresoc.v:110765.3-110775.6" + process $proc$libresoc.v:110765$4320 + assign { } { } + assign { } { } + assign $0\ds[15:0] $1\ds[15:0] + attribute \src "libresoc.v:110766.5-110766.29" + switch \initial + attribute \src "libresoc.v:110766.9-110766.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\ds[15:0] \$22 [15:0] + case + assign $1\ds[15:0] 16'0000000000000000 + end + sync always + update \ds $0\ds[15:0] + end + connect \$9 $pos$libresoc.v:110606$4301_Y + connect \$11 $pos$libresoc.v:110607$4303_Y + connect \$14 $sshl$libresoc.v:110608$4304_Y + connect \$17 $sshl$libresoc.v:110609$4305_Y + connect \$1 $pos$libresoc.v:110610$4307_Y + connect \$20 $sshl$libresoc.v:110611$4308_Y + connect \$23 $sshl$libresoc.v:110612$4309_Y + connect \$4 $sshl$libresoc.v:110613$4310_Y + connect \$3 $pos$libresoc.v:110614$4312_Y + connect \$7 64'1111111111111111111111111111111111111111111111111111111111111111 + connect \$13 \$14 + connect \$16 \$17 + connect \$19 \$20 + connect \$22 \$23 +end +attribute \src "libresoc.v:110784.1-111037.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_MUL.dec_bi" +attribute \generator "nMigen" +module \dec_bi$184 + attribute \src "libresoc.v:111011.3-111021.6" + wire width 16 $0\bd[15:0] + attribute \src "libresoc.v:111022.3-111032.6" + wire width 16 $0\ds[15:0] + attribute \src "libresoc.v:110873.3-110919.6" + wire width 64 $0\imm_b[63:0] + attribute \src "libresoc.v:110920.3-110966.6" + wire $0\imm_b_ok[0:0] + attribute \src "libresoc.v:110785.7-110785.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:111000.3-111010.6" + wire width 26 $0\li[25:0] + attribute \src "libresoc.v:110967.3-110977.6" + wire width 16 $0\si[15:0] + attribute \src "libresoc.v:110978.3-110988.6" + wire width 32 $0\si_hi[31:0] + attribute \src "libresoc.v:110989.3-110999.6" + wire width 16 $0\ui[15:0] + attribute \src "libresoc.v:111011.3-111021.6" + wire width 16 $1\bd[15:0] + attribute \src "libresoc.v:111022.3-111032.6" + wire width 16 $1\ds[15:0] + attribute \src "libresoc.v:110873.3-110919.6" + wire width 64 $1\imm_b[63:0] + attribute \src "libresoc.v:110920.3-110966.6" + wire $1\imm_b_ok[0:0] + attribute \src "libresoc.v:111000.3-111010.6" + wire width 26 $1\li[25:0] + attribute \src "libresoc.v:110967.3-110977.6" + wire width 16 $1\si[15:0] + attribute \src "libresoc.v:110978.3-110988.6" + wire width 32 $1\si_hi[31:0] + attribute \src "libresoc.v:110989.3-110999.6" + wire width 16 $1\ui[15:0] + attribute \src "libresoc.v:110863.17-110863.104" + wire width 64 $extend$libresoc.v:110863$4322_Y + attribute \src "libresoc.v:110864.18-110864.107" + wire width 64 $extend$libresoc.v:110864$4324_Y + attribute \src "libresoc.v:110867.17-110867.104" + wire width 64 $extend$libresoc.v:110867$4328_Y + attribute \src "libresoc.v:110871.17-110871.102" + wire width 64 $extend$libresoc.v:110871$4333_Y + attribute \src "libresoc.v:110863.17-110863.104" + wire width 64 $pos$libresoc.v:110863$4323_Y + attribute \src "libresoc.v:110864.18-110864.107" + wire width 64 $pos$libresoc.v:110864$4325_Y + attribute \src "libresoc.v:110867.17-110867.104" + wire width 64 $pos$libresoc.v:110867$4329_Y + attribute \src "libresoc.v:110871.17-110871.102" + wire width 64 $pos$libresoc.v:110871$4334_Y + attribute \src "libresoc.v:110865.18-110865.114" + wire width 47 $sshl$libresoc.v:110865$4326_Y + attribute \src "libresoc.v:110866.18-110866.113" + wire width 27 $sshl$libresoc.v:110866$4327_Y + attribute \src "libresoc.v:110868.18-110868.113" + wire width 17 $sshl$libresoc.v:110868$4330_Y + attribute \src "libresoc.v:110869.18-110869.113" + wire width 17 $sshl$libresoc.v:110869$4331_Y + attribute \src "libresoc.v:110870.17-110870.109" + wire width 47 $sshl$libresoc.v:110870$4332_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 64 \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 64 \$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" + wire width 47 \$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" + wire width 47 \$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:245" + wire width 27 \$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:245" + wire width 27 \$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" + wire width 17 \$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" + wire width 17 \$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" + wire width 17 \$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" + wire width 17 \$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" + wire width 64 \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" + wire width 47 \$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:259" + wire width 64 \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 64 \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 14 input 8 \MUL_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 14 input 9 \MUL_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 24 input 7 \MUL_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 5 \MUL_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 16 input 3 \MUL_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 16 input 4 \MUL_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 6 input 6 \MUL_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:249" + wire width 16 \bd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" + wire width 16 \ds + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 1 \imm_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 2 \imm_b_ok + attribute \src "libresoc.v:110785.7-110785.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + wire width 26 \li + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:216" + wire width 4 input 10 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:229" + wire width 16 \si + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:234" + wire width 32 \si_hi + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" + wire width 16 \ui + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + cell $pos $extend$libresoc.v:110863$4322 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 64 + connect \A \MUL_sh + connect \Y $extend$libresoc.v:110863$4322_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + cell $pos $extend$libresoc.v:110864$4324 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 64 + connect \A \MUL_SH32 + connect \Y $extend$libresoc.v:110864$4324_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + cell $pos $extend$libresoc.v:110867$4328 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \Y_WIDTH 64 + connect \A \MUL_UI + connect \Y $extend$libresoc.v:110867$4328_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" + cell $pos $extend$libresoc.v:110871$4333 + parameter \A_SIGNED 0 + parameter \A_WIDTH 47 + parameter \Y_WIDTH 64 + connect \A \$4 + connect \Y $extend$libresoc.v:110871$4333_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + cell $pos $pos$libresoc.v:110863$4323 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:110863$4322_Y + connect \Y $pos$libresoc.v:110863$4323_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + cell $pos $pos$libresoc.v:110864$4325 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:110864$4324_Y + connect \Y $pos$libresoc.v:110864$4325_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + cell $pos $pos$libresoc.v:110867$4329 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:110867$4328_Y + connect \Y $pos$libresoc.v:110867$4329_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" + cell $pos $pos$libresoc.v:110871$4334 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:110871$4333_Y + connect \Y $pos$libresoc.v:110871$4334_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" + cell $sshl $sshl$libresoc.v:110865$4326 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 47 + connect \A \MUL_SI + connect \B 5'10000 + connect \Y $sshl$libresoc.v:110865$4326_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:245" + cell $sshl $sshl$libresoc.v:110866$4327 + parameter \A_SIGNED 0 + parameter \A_WIDTH 24 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 27 + connect \A \MUL_LI + connect \B 2'10 + connect \Y $sshl$libresoc.v:110866$4327_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" + cell $sshl $sshl$libresoc.v:110868$4330 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 17 + connect \A \MUL_BD + connect \B 2'10 + connect \Y $sshl$libresoc.v:110868$4330_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" + cell $sshl $sshl$libresoc.v:110869$4331 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 17 + connect \A \MUL_DS + connect \B 2'10 + connect \Y $sshl$libresoc.v:110869$4331_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" + cell $sshl $sshl$libresoc.v:110870$4332 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 47 + connect \A \ui + connect \B 5'10000 + connect \Y $sshl$libresoc.v:110870$4332_Y + end + attribute \src "libresoc.v:110785.7-110785.20" + process $proc$libresoc.v:110785$4343 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:110873.3-110919.6" + process $proc$libresoc.v:110873$4335 + assign { } { } + assign { } { } + assign $0\imm_b[63:0] $1\imm_b[63:0] + attribute \src "libresoc.v:110874.5-110874.29" + switch \initial + attribute \src "libresoc.v:110874.9-110874.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\imm_b[63:0] \$1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\imm_b[63:0] { \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si } + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\imm_b[63:0] { \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi } + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\imm_b[63:0] \$3 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\imm_b[63:0] { \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li } + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\imm_b[63:0] { \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd } + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\imm_b[63:0] { \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds } + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\imm_b[63:0] \$7 + attribute \src "libresoc.v:0.0-0.0" + case 4'1010 + assign { } { } + assign $1\imm_b[63:0] \$9 + attribute \src "libresoc.v:0.0-0.0" + case 4'1011 + assign { } { } + assign $1\imm_b[63:0] \$11 + case + assign $1\imm_b[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \imm_b $0\imm_b[63:0] + end + attribute \src "libresoc.v:110920.3-110966.6" + process $proc$libresoc.v:110920$4336 + assign { } { } + assign { } { } + assign $0\imm_b_ok[0:0] $1\imm_b_ok[0:0] + attribute \src "libresoc.v:110921.5-110921.29" + switch \initial + attribute \src "libresoc.v:110921.9-110921.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'1010 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'1011 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + case + assign $1\imm_b_ok[0:0] 1'0 + end + sync always + update \imm_b_ok $0\imm_b_ok[0:0] + end + attribute \src "libresoc.v:110967.3-110977.6" + process $proc$libresoc.v:110967$4337 + assign { } { } + assign { } { } + assign $0\si[15:0] $1\si[15:0] + attribute \src "libresoc.v:110968.5-110968.29" + switch \initial + attribute \src "libresoc.v:110968.9-110968.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\si[15:0] \MUL_SI + case + assign $1\si[15:0] 16'0000000000000000 + end + sync always + update \si $0\si[15:0] + end + attribute \src "libresoc.v:110978.3-110988.6" + process $proc$libresoc.v:110978$4338 + assign { } { } + assign { } { } + assign $0\si_hi[31:0] $1\si_hi[31:0] + attribute \src "libresoc.v:110979.5-110979.29" + switch \initial + attribute \src "libresoc.v:110979.9-110979.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\si_hi[31:0] \$13 [31:0] + case + assign $1\si_hi[31:0] 0 + end + sync always + update \si_hi $0\si_hi[31:0] + end + attribute \src "libresoc.v:110989.3-110999.6" + process $proc$libresoc.v:110989$4339 + assign { } { } + assign { } { } + assign $0\ui[15:0] $1\ui[15:0] + attribute \src "libresoc.v:110990.5-110990.29" + switch \initial + attribute \src "libresoc.v:110990.9-110990.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\ui[15:0] \MUL_UI + case + assign $1\ui[15:0] 16'0000000000000000 + end + sync always + update \ui $0\ui[15:0] + end + attribute \src "libresoc.v:111000.3-111010.6" + process $proc$libresoc.v:111000$4340 + assign { } { } + assign { } { } + assign $0\li[25:0] $1\li[25:0] + attribute \src "libresoc.v:111001.5-111001.29" + switch \initial + attribute \src "libresoc.v:111001.9-111001.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\li[25:0] \$16 [25:0] + case + assign $1\li[25:0] 26'00000000000000000000000000 + end + sync always + update \li $0\li[25:0] + end + attribute \src "libresoc.v:111011.3-111021.6" + process $proc$libresoc.v:111011$4341 + assign { } { } + assign { } { } + assign $0\bd[15:0] $1\bd[15:0] + attribute \src "libresoc.v:111012.5-111012.29" + switch \initial + attribute \src "libresoc.v:111012.9-111012.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\bd[15:0] \$19 [15:0] + case + assign $1\bd[15:0] 16'0000000000000000 + end + sync always + update \bd $0\bd[15:0] + end + attribute \src "libresoc.v:111022.3-111032.6" + process $proc$libresoc.v:111022$4342 + assign { } { } + assign { } { } + assign $0\ds[15:0] $1\ds[15:0] + attribute \src "libresoc.v:111023.5-111023.29" + switch \initial + attribute \src "libresoc.v:111023.9-111023.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\ds[15:0] \$22 [15:0] + case + assign $1\ds[15:0] 16'0000000000000000 + end + sync always + update \ds $0\ds[15:0] + end + connect \$9 $pos$libresoc.v:110863$4323_Y + connect \$11 $pos$libresoc.v:110864$4325_Y + connect \$14 $sshl$libresoc.v:110865$4326_Y + connect \$17 $sshl$libresoc.v:110866$4327_Y + connect \$1 $pos$libresoc.v:110867$4329_Y + connect \$20 $sshl$libresoc.v:110868$4330_Y + connect \$23 $sshl$libresoc.v:110869$4331_Y + connect \$4 $sshl$libresoc.v:110870$4332_Y + connect \$3 $pos$libresoc.v:110871$4334_Y + connect \$7 64'1111111111111111111111111111111111111111111111111111111111111111 + connect \$13 \$14 + connect \$16 \$17 + connect \$19 \$20 + connect \$22 \$23 +end +attribute \src "libresoc.v:111041.1-111294.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_SHIFT_ROT.dec_bi" +attribute \generator "nMigen" +module \dec_bi$192 + attribute \src "libresoc.v:111268.3-111278.6" + wire width 16 $0\bd[15:0] + attribute \src "libresoc.v:111279.3-111289.6" + wire width 16 $0\ds[15:0] + attribute \src "libresoc.v:111130.3-111176.6" + wire width 64 $0\imm_b[63:0] + attribute \src "libresoc.v:111177.3-111223.6" + wire $0\imm_b_ok[0:0] + attribute \src "libresoc.v:111042.7-111042.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:111257.3-111267.6" + wire width 26 $0\li[25:0] + attribute \src "libresoc.v:111224.3-111234.6" + wire width 16 $0\si[15:0] + attribute \src "libresoc.v:111235.3-111245.6" + wire width 32 $0\si_hi[31:0] + attribute \src "libresoc.v:111246.3-111256.6" + wire width 16 $0\ui[15:0] + attribute \src "libresoc.v:111268.3-111278.6" + wire width 16 $1\bd[15:0] + attribute \src "libresoc.v:111279.3-111289.6" + wire width 16 $1\ds[15:0] + attribute \src "libresoc.v:111130.3-111176.6" + wire width 64 $1\imm_b[63:0] + attribute \src "libresoc.v:111177.3-111223.6" + wire $1\imm_b_ok[0:0] + attribute \src "libresoc.v:111257.3-111267.6" + wire width 26 $1\li[25:0] + attribute \src "libresoc.v:111224.3-111234.6" + wire width 16 $1\si[15:0] + attribute \src "libresoc.v:111235.3-111245.6" + wire width 32 $1\si_hi[31:0] + attribute \src "libresoc.v:111246.3-111256.6" + wire width 16 $1\ui[15:0] + attribute \src "libresoc.v:111120.17-111120.110" + wire width 64 $extend$libresoc.v:111120$4344_Y + attribute \src "libresoc.v:111121.18-111121.113" + wire width 64 $extend$libresoc.v:111121$4346_Y + attribute \src "libresoc.v:111124.17-111124.110" + wire width 64 $extend$libresoc.v:111124$4350_Y + attribute \src "libresoc.v:111128.17-111128.102" + wire width 64 $extend$libresoc.v:111128$4355_Y + attribute \src "libresoc.v:111120.17-111120.110" + wire width 64 $pos$libresoc.v:111120$4345_Y + attribute \src "libresoc.v:111121.18-111121.113" + wire width 64 $pos$libresoc.v:111121$4347_Y + attribute \src "libresoc.v:111124.17-111124.110" + wire width 64 $pos$libresoc.v:111124$4351_Y + attribute \src "libresoc.v:111128.17-111128.102" + wire width 64 $pos$libresoc.v:111128$4356_Y + attribute \src "libresoc.v:111122.18-111122.120" + wire width 47 $sshl$libresoc.v:111122$4348_Y + attribute \src "libresoc.v:111123.18-111123.119" + wire width 27 $sshl$libresoc.v:111123$4349_Y + attribute \src "libresoc.v:111125.18-111125.119" + wire width 17 $sshl$libresoc.v:111125$4352_Y + attribute \src "libresoc.v:111126.18-111126.119" + wire width 17 $sshl$libresoc.v:111126$4353_Y + attribute \src "libresoc.v:111127.17-111127.109" + wire width 47 $sshl$libresoc.v:111127$4354_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 64 \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 64 \$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" + wire width 47 \$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" + wire width 47 \$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:245" + wire width 27 \$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:245" + wire width 27 \$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" + wire width 17 \$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" + wire width 17 \$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" + wire width 17 \$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" + wire width 17 \$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" + wire width 64 \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" + wire width 47 \$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:259" + wire width 64 \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 64 \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 14 input 8 \SHIFT_ROT_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 14 input 9 \SHIFT_ROT_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 24 input 7 \SHIFT_ROT_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 5 \SHIFT_ROT_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 16 input 3 \SHIFT_ROT_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 16 input 4 \SHIFT_ROT_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 6 input 6 \SHIFT_ROT_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:249" + wire width 16 \bd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" + wire width 16 \ds + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 1 \imm_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 2 \imm_b_ok + attribute \src "libresoc.v:111042.7-111042.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + wire width 26 \li + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:216" + wire width 4 input 10 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:229" + wire width 16 \si + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:234" + wire width 32 \si_hi + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" + wire width 16 \ui + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + cell $pos $extend$libresoc.v:111120$4344 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 64 + connect \A \SHIFT_ROT_sh + connect \Y $extend$libresoc.v:111120$4344_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + cell $pos $extend$libresoc.v:111121$4346 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 64 + connect \A \SHIFT_ROT_SH32 + connect \Y $extend$libresoc.v:111121$4346_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + cell $pos $extend$libresoc.v:111124$4350 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \Y_WIDTH 64 + connect \A \SHIFT_ROT_UI + connect \Y $extend$libresoc.v:111124$4350_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" + cell $pos $extend$libresoc.v:111128$4355 + parameter \A_SIGNED 0 + parameter \A_WIDTH 47 + parameter \Y_WIDTH 64 + connect \A \$4 + connect \Y $extend$libresoc.v:111128$4355_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + cell $pos $pos$libresoc.v:111120$4345 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:111120$4344_Y + connect \Y $pos$libresoc.v:111120$4345_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + cell $pos $pos$libresoc.v:111121$4347 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:111121$4346_Y + connect \Y $pos$libresoc.v:111121$4347_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + cell $pos $pos$libresoc.v:111124$4351 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:111124$4350_Y + connect \Y $pos$libresoc.v:111124$4351_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" + cell $pos $pos$libresoc.v:111128$4356 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:111128$4355_Y + connect \Y $pos$libresoc.v:111128$4356_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" + cell $sshl $sshl$libresoc.v:111122$4348 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 47 + connect \A \SHIFT_ROT_SI + connect \B 5'10000 + connect \Y $sshl$libresoc.v:111122$4348_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:245" + cell $sshl $sshl$libresoc.v:111123$4349 + parameter \A_SIGNED 0 + parameter \A_WIDTH 24 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 27 + connect \A \SHIFT_ROT_LI + connect \B 2'10 + connect \Y $sshl$libresoc.v:111123$4349_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" + cell $sshl $sshl$libresoc.v:111125$4352 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 17 + connect \A \SHIFT_ROT_BD + connect \B 2'10 + connect \Y $sshl$libresoc.v:111125$4352_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" + cell $sshl $sshl$libresoc.v:111126$4353 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 17 + connect \A \SHIFT_ROT_DS + connect \B 2'10 + connect \Y $sshl$libresoc.v:111126$4353_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" + cell $sshl $sshl$libresoc.v:111127$4354 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 47 + connect \A \ui + connect \B 5'10000 + connect \Y $sshl$libresoc.v:111127$4354_Y + end + attribute \src "libresoc.v:111042.7-111042.20" + process $proc$libresoc.v:111042$4365 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:111130.3-111176.6" + process $proc$libresoc.v:111130$4357 + assign { } { } + assign { } { } + assign $0\imm_b[63:0] $1\imm_b[63:0] + attribute \src "libresoc.v:111131.5-111131.29" + switch \initial + attribute \src "libresoc.v:111131.9-111131.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\imm_b[63:0] \$1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\imm_b[63:0] { \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si } + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\imm_b[63:0] { \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi } + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\imm_b[63:0] \$3 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\imm_b[63:0] { \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li } + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\imm_b[63:0] { \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd } + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\imm_b[63:0] { \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds } + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\imm_b[63:0] \$7 + attribute \src "libresoc.v:0.0-0.0" + case 4'1010 + assign { } { } + assign $1\imm_b[63:0] \$9 + attribute \src "libresoc.v:0.0-0.0" + case 4'1011 + assign { } { } + assign $1\imm_b[63:0] \$11 + case + assign $1\imm_b[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \imm_b $0\imm_b[63:0] + end + attribute \src "libresoc.v:111177.3-111223.6" + process $proc$libresoc.v:111177$4358 + assign { } { } + assign { } { } + assign $0\imm_b_ok[0:0] $1\imm_b_ok[0:0] + attribute \src "libresoc.v:111178.5-111178.29" + switch \initial + attribute \src "libresoc.v:111178.9-111178.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'1010 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'1011 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + case + assign $1\imm_b_ok[0:0] 1'0 + end + sync always + update \imm_b_ok $0\imm_b_ok[0:0] + end + attribute \src "libresoc.v:111224.3-111234.6" + process $proc$libresoc.v:111224$4359 + assign { } { } + assign { } { } + assign $0\si[15:0] $1\si[15:0] + attribute \src "libresoc.v:111225.5-111225.29" + switch \initial + attribute \src "libresoc.v:111225.9-111225.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\si[15:0] \SHIFT_ROT_SI + case + assign $1\si[15:0] 16'0000000000000000 + end + sync always + update \si $0\si[15:0] + end + attribute \src "libresoc.v:111235.3-111245.6" + process $proc$libresoc.v:111235$4360 + assign { } { } + assign { } { } + assign $0\si_hi[31:0] $1\si_hi[31:0] + attribute \src "libresoc.v:111236.5-111236.29" + switch \initial + attribute \src "libresoc.v:111236.9-111236.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\si_hi[31:0] \$13 [31:0] + case + assign $1\si_hi[31:0] 0 + end + sync always + update \si_hi $0\si_hi[31:0] + end + attribute \src "libresoc.v:111246.3-111256.6" + process $proc$libresoc.v:111246$4361 + assign { } { } + assign { } { } + assign $0\ui[15:0] $1\ui[15:0] + attribute \src "libresoc.v:111247.5-111247.29" + switch \initial + attribute \src "libresoc.v:111247.9-111247.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\ui[15:0] \SHIFT_ROT_UI + case + assign $1\ui[15:0] 16'0000000000000000 + end + sync always + update \ui $0\ui[15:0] + end + attribute \src "libresoc.v:111257.3-111267.6" + process $proc$libresoc.v:111257$4362 + assign { } { } + assign { } { } + assign $0\li[25:0] $1\li[25:0] + attribute \src "libresoc.v:111258.5-111258.29" + switch \initial + attribute \src "libresoc.v:111258.9-111258.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\li[25:0] \$16 [25:0] + case + assign $1\li[25:0] 26'00000000000000000000000000 + end + sync always + update \li $0\li[25:0] + end + attribute \src "libresoc.v:111268.3-111278.6" + process $proc$libresoc.v:111268$4363 + assign { } { } + assign { } { } + assign $0\bd[15:0] $1\bd[15:0] + attribute \src "libresoc.v:111269.5-111269.29" + switch \initial + attribute \src "libresoc.v:111269.9-111269.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\bd[15:0] \$19 [15:0] + case + assign $1\bd[15:0] 16'0000000000000000 + end + sync always + update \bd $0\bd[15:0] + end + attribute \src "libresoc.v:111279.3-111289.6" + process $proc$libresoc.v:111279$4364 + assign { } { } + assign { } { } + assign $0\ds[15:0] $1\ds[15:0] + attribute \src "libresoc.v:111280.5-111280.29" + switch \initial + attribute \src "libresoc.v:111280.9-111280.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\ds[15:0] \$22 [15:0] + case + assign $1\ds[15:0] 16'0000000000000000 + end + sync always + update \ds $0\ds[15:0] + end + connect \$9 $pos$libresoc.v:111120$4345_Y + connect \$11 $pos$libresoc.v:111121$4347_Y + connect \$14 $sshl$libresoc.v:111122$4348_Y + connect \$17 $sshl$libresoc.v:111123$4349_Y + connect \$1 $pos$libresoc.v:111124$4351_Y + connect \$20 $sshl$libresoc.v:111125$4352_Y + connect \$23 $sshl$libresoc.v:111126$4353_Y + connect \$4 $sshl$libresoc.v:111127$4354_Y + connect \$3 $pos$libresoc.v:111128$4356_Y + connect \$7 64'1111111111111111111111111111111111111111111111111111111111111111 + connect \$13 \$14 + connect \$16 \$17 + connect \$19 \$20 + connect \$22 \$23 +end +attribute \src "libresoc.v:111298.1-111551.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_LDST.dec_bi" +attribute \generator "nMigen" +module \dec_bi$201 + attribute \src "libresoc.v:111525.3-111535.6" + wire width 16 $0\bd[15:0] + attribute \src "libresoc.v:111536.3-111546.6" + wire width 16 $0\ds[15:0] + attribute \src "libresoc.v:111387.3-111433.6" + wire width 64 $0\imm_b[63:0] + attribute \src "libresoc.v:111434.3-111480.6" + wire $0\imm_b_ok[0:0] + attribute \src "libresoc.v:111299.7-111299.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:111514.3-111524.6" + wire width 26 $0\li[25:0] + attribute \src "libresoc.v:111481.3-111491.6" + wire width 16 $0\si[15:0] + attribute \src "libresoc.v:111492.3-111502.6" + wire width 32 $0\si_hi[31:0] + attribute \src "libresoc.v:111503.3-111513.6" + wire width 16 $0\ui[15:0] + attribute \src "libresoc.v:111525.3-111535.6" + wire width 16 $1\bd[15:0] + attribute \src "libresoc.v:111536.3-111546.6" + wire width 16 $1\ds[15:0] + attribute \src "libresoc.v:111387.3-111433.6" + wire width 64 $1\imm_b[63:0] + attribute \src "libresoc.v:111434.3-111480.6" + wire $1\imm_b_ok[0:0] + attribute \src "libresoc.v:111514.3-111524.6" + wire width 26 $1\li[25:0] + attribute \src "libresoc.v:111481.3-111491.6" + wire width 16 $1\si[15:0] + attribute \src "libresoc.v:111492.3-111502.6" + wire width 32 $1\si_hi[31:0] + attribute \src "libresoc.v:111503.3-111513.6" + wire width 16 $1\ui[15:0] + attribute \src "libresoc.v:111377.17-111377.105" + wire width 64 $extend$libresoc.v:111377$4366_Y + attribute \src "libresoc.v:111378.18-111378.108" + wire width 64 $extend$libresoc.v:111378$4368_Y + attribute \src "libresoc.v:111381.17-111381.105" + wire width 64 $extend$libresoc.v:111381$4372_Y + attribute \src "libresoc.v:111385.17-111385.102" + wire width 64 $extend$libresoc.v:111385$4377_Y + attribute \src "libresoc.v:111377.17-111377.105" + wire width 64 $pos$libresoc.v:111377$4367_Y + attribute \src "libresoc.v:111378.18-111378.108" + wire width 64 $pos$libresoc.v:111378$4369_Y + attribute \src "libresoc.v:111381.17-111381.105" + wire width 64 $pos$libresoc.v:111381$4373_Y + attribute \src "libresoc.v:111385.17-111385.102" + wire width 64 $pos$libresoc.v:111385$4378_Y + attribute \src "libresoc.v:111379.18-111379.115" + wire width 47 $sshl$libresoc.v:111379$4370_Y + attribute \src "libresoc.v:111380.18-111380.114" + wire width 27 $sshl$libresoc.v:111380$4371_Y + attribute \src "libresoc.v:111382.18-111382.114" + wire width 17 $sshl$libresoc.v:111382$4374_Y + attribute \src "libresoc.v:111383.18-111383.114" + wire width 17 $sshl$libresoc.v:111383$4375_Y + attribute \src "libresoc.v:111384.17-111384.109" + wire width 47 $sshl$libresoc.v:111384$4376_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 64 \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 64 \$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" + wire width 47 \$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" + wire width 47 \$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:245" + wire width 27 \$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:245" + wire width 27 \$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" + wire width 17 \$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" + wire width 17 \$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" + wire width 17 \$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" + wire width 17 \$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" + wire width 64 \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" + wire width 47 \$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:259" + wire width 64 \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 64 \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 14 input 8 \LDST_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 14 input 9 \LDST_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 24 input 7 \LDST_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 5 \LDST_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 16 input 3 \LDST_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 16 input 4 \LDST_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 6 input 6 \LDST_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:249" + wire width 16 \bd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" + wire width 16 \ds + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 1 \imm_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 2 \imm_b_ok + attribute \src "libresoc.v:111299.7-111299.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + wire width 26 \li + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:216" + wire width 4 input 10 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:229" + wire width 16 \si + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:234" + wire width 32 \si_hi + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" + wire width 16 \ui + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + cell $pos $extend$libresoc.v:111377$4366 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 64 + connect \A \LDST_sh + connect \Y $extend$libresoc.v:111377$4366_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + cell $pos $extend$libresoc.v:111378$4368 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 64 + connect \A \LDST_SH32 + connect \Y $extend$libresoc.v:111378$4368_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + cell $pos $extend$libresoc.v:111381$4372 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \Y_WIDTH 64 + connect \A \LDST_UI + connect \Y $extend$libresoc.v:111381$4372_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" + cell $pos $extend$libresoc.v:111385$4377 + parameter \A_SIGNED 0 + parameter \A_WIDTH 47 + parameter \Y_WIDTH 64 + connect \A \$4 + connect \Y $extend$libresoc.v:111385$4377_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + cell $pos $pos$libresoc.v:111377$4367 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:111377$4366_Y + connect \Y $pos$libresoc.v:111377$4367_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + cell $pos $pos$libresoc.v:111378$4369 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:111378$4368_Y + connect \Y $pos$libresoc.v:111378$4369_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + cell $pos $pos$libresoc.v:111381$4373 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:111381$4372_Y + connect \Y $pos$libresoc.v:111381$4373_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" + cell $pos $pos$libresoc.v:111385$4378 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:111385$4377_Y + connect \Y $pos$libresoc.v:111385$4378_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" + cell $sshl $sshl$libresoc.v:111379$4370 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 47 + connect \A \LDST_SI + connect \B 5'10000 + connect \Y $sshl$libresoc.v:111379$4370_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:245" + cell $sshl $sshl$libresoc.v:111380$4371 + parameter \A_SIGNED 0 + parameter \A_WIDTH 24 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 27 + connect \A \LDST_LI + connect \B 2'10 + connect \Y $sshl$libresoc.v:111380$4371_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" + cell $sshl $sshl$libresoc.v:111382$4374 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 17 + connect \A \LDST_BD + connect \B 2'10 + connect \Y $sshl$libresoc.v:111382$4374_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" + cell $sshl $sshl$libresoc.v:111383$4375 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 17 + connect \A \LDST_DS + connect \B 2'10 + connect \Y $sshl$libresoc.v:111383$4375_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" + cell $sshl $sshl$libresoc.v:111384$4376 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 47 + connect \A \ui + connect \B 5'10000 + connect \Y $sshl$libresoc.v:111384$4376_Y + end + attribute \src "libresoc.v:111299.7-111299.20" + process $proc$libresoc.v:111299$4387 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:111387.3-111433.6" + process $proc$libresoc.v:111387$4379 + assign { } { } + assign { } { } + assign $0\imm_b[63:0] $1\imm_b[63:0] + attribute \src "libresoc.v:111388.5-111388.29" + switch \initial + attribute \src "libresoc.v:111388.9-111388.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\imm_b[63:0] \$1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\imm_b[63:0] { \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si } + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\imm_b[63:0] { \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi } + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\imm_b[63:0] \$3 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\imm_b[63:0] { \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li } + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\imm_b[63:0] { \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd } + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\imm_b[63:0] { \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds } + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\imm_b[63:0] \$7 + attribute \src "libresoc.v:0.0-0.0" + case 4'1010 + assign { } { } + assign $1\imm_b[63:0] \$9 + attribute \src "libresoc.v:0.0-0.0" + case 4'1011 + assign { } { } + assign $1\imm_b[63:0] \$11 + case + assign $1\imm_b[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \imm_b $0\imm_b[63:0] + end + attribute \src "libresoc.v:111434.3-111480.6" + process $proc$libresoc.v:111434$4380 + assign { } { } + assign { } { } + assign $0\imm_b_ok[0:0] $1\imm_b_ok[0:0] + attribute \src "libresoc.v:111435.5-111435.29" + switch \initial + attribute \src "libresoc.v:111435.9-111435.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'1010 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'1011 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + case + assign $1\imm_b_ok[0:0] 1'0 + end + sync always + update \imm_b_ok $0\imm_b_ok[0:0] + end + attribute \src "libresoc.v:111481.3-111491.6" + process $proc$libresoc.v:111481$4381 + assign { } { } + assign { } { } + assign $0\si[15:0] $1\si[15:0] + attribute \src "libresoc.v:111482.5-111482.29" + switch \initial + attribute \src "libresoc.v:111482.9-111482.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\si[15:0] \LDST_SI + case + assign $1\si[15:0] 16'0000000000000000 + end + sync always + update \si $0\si[15:0] + end + attribute \src "libresoc.v:111492.3-111502.6" + process $proc$libresoc.v:111492$4382 + assign { } { } + assign { } { } + assign $0\si_hi[31:0] $1\si_hi[31:0] + attribute \src "libresoc.v:111493.5-111493.29" + switch \initial + attribute \src "libresoc.v:111493.9-111493.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\si_hi[31:0] \$13 [31:0] + case + assign $1\si_hi[31:0] 0 + end + sync always + update \si_hi $0\si_hi[31:0] + end + attribute \src "libresoc.v:111503.3-111513.6" + process $proc$libresoc.v:111503$4383 + assign { } { } + assign { } { } + assign $0\ui[15:0] $1\ui[15:0] + attribute \src "libresoc.v:111504.5-111504.29" + switch \initial + attribute \src "libresoc.v:111504.9-111504.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\ui[15:0] \LDST_UI + case + assign $1\ui[15:0] 16'0000000000000000 + end + sync always + update \ui $0\ui[15:0] + end + attribute \src "libresoc.v:111514.3-111524.6" + process $proc$libresoc.v:111514$4384 + assign { } { } + assign { } { } + assign $0\li[25:0] $1\li[25:0] + attribute \src "libresoc.v:111515.5-111515.29" + switch \initial + attribute \src "libresoc.v:111515.9-111515.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\li[25:0] \$16 [25:0] + case + assign $1\li[25:0] 26'00000000000000000000000000 + end + sync always + update \li $0\li[25:0] + end + attribute \src "libresoc.v:111525.3-111535.6" + process $proc$libresoc.v:111525$4385 + assign { } { } + assign { } { } + assign $0\bd[15:0] $1\bd[15:0] + attribute \src "libresoc.v:111526.5-111526.29" + switch \initial + attribute \src "libresoc.v:111526.9-111526.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\bd[15:0] \$19 [15:0] + case + assign $1\bd[15:0] 16'0000000000000000 + end + sync always + update \bd $0\bd[15:0] + end + attribute \src "libresoc.v:111536.3-111546.6" + process $proc$libresoc.v:111536$4386 + assign { } { } + assign { } { } + assign $0\ds[15:0] $1\ds[15:0] + attribute \src "libresoc.v:111537.5-111537.29" + switch \initial + attribute \src "libresoc.v:111537.9-111537.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\ds[15:0] \$22 [15:0] + case + assign $1\ds[15:0] 16'0000000000000000 + end + sync always + update \ds $0\ds[15:0] + end + connect \$9 $pos$libresoc.v:111377$4367_Y + connect \$11 $pos$libresoc.v:111378$4369_Y + connect \$14 $sshl$libresoc.v:111379$4370_Y + connect \$17 $sshl$libresoc.v:111380$4371_Y + connect \$1 $pos$libresoc.v:111381$4373_Y + connect \$20 $sshl$libresoc.v:111382$4374_Y + connect \$23 $sshl$libresoc.v:111383$4375_Y + connect \$4 $sshl$libresoc.v:111384$4376_Y + connect \$3 $pos$libresoc.v:111385$4378_Y + connect \$7 64'1111111111111111111111111111111111111111111111111111111111111111 + connect \$13 \$14 + connect \$16 \$17 + connect \$19 \$20 + connect \$22 \$23 +end +attribute \src "libresoc.v:111555.1-111603.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.dec2.dec_c" +attribute \generator "nMigen" +module \dec_c + attribute \src "libresoc.v:111556.7-111556.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:111573.3-111587.6" + wire width 5 $0\reg_c[4:0] + attribute \src "libresoc.v:111588.3-111602.6" + wire $0\reg_c_ok[0:0] + attribute \src "libresoc.v:111573.3-111587.6" + wire width 5 $1\reg_c[4:0] + attribute \src "libresoc.v:111588.3-111602.6" + wire $1\reg_c_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 4 \RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 3 \RS + attribute \src "libresoc.v:111556.7-111556.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 output 1 \reg_c + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 2 \reg_c_ok + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" + wire width 2 input 5 \sel_in + attribute \src "libresoc.v:111556.7-111556.20" + process $proc$libresoc.v:111556$4390 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:111573.3-111587.6" + process $proc$libresoc.v:111573$4388 + assign { } { } + assign { } { } + assign $0\reg_c[4:0] $1\reg_c[4:0] + attribute \src "libresoc.v:111574.5-111574.29" + switch \initial + attribute \src "libresoc.v:111574.9-111574.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:288" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\reg_c[4:0] \RB + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\reg_c[4:0] \RS + case + assign $1\reg_c[4:0] 5'00000 + end + sync always + update \reg_c $0\reg_c[4:0] + end + attribute \src "libresoc.v:111588.3-111602.6" + process $proc$libresoc.v:111588$4389 + assign { } { } + assign { } { } + assign $0\reg_c_ok[0:0] $1\reg_c_ok[0:0] + attribute \src "libresoc.v:111589.5-111589.29" + switch \initial + attribute \src "libresoc.v:111589.9-111589.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:288" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\reg_c_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\reg_c_ok[0:0] 1'1 + case + assign $1\reg_c_ok[0:0] 1'0 + end + sync always + update \reg_c_ok $0\reg_c_ok[0:0] + end +end +attribute \src "libresoc.v:111607.1-111904.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_ALU.dec_cr_in" +attribute \generator "nMigen" +module \dec_cr_in + attribute \src "libresoc.v:111798.3-111824.6" + wire width 3 $0\cr_bitfield[2:0] + attribute \src "libresoc.v:111825.3-111835.6" + wire width 3 $0\cr_bitfield_b[2:0] + attribute \src "libresoc.v:111776.3-111786.6" + wire $0\cr_bitfield_b_ok[0:0] + attribute \src "libresoc.v:111836.3-111846.6" + wire width 3 $0\cr_bitfield_o[2:0] + attribute \src "libresoc.v:111847.3-111857.6" + wire $0\cr_bitfield_o_ok[0:0] + attribute \src "libresoc.v:111749.3-111775.6" + wire $0\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:111885.3-111903.6" + wire width 8 $0\cr_fxm[7:0] + attribute \src "libresoc.v:111787.3-111797.6" + wire $0\cr_fxm_ok[0:0] + attribute \src "libresoc.v:111608.7-111608.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:111858.3-111868.6" + wire $0\move_one[0:0] + attribute \src "libresoc.v:111869.3-111884.6" + wire width 8 $0\ppick_i[7:0] + attribute \src "libresoc.v:111798.3-111824.6" + wire width 3 $1\cr_bitfield[2:0] + attribute \src "libresoc.v:111825.3-111835.6" + wire width 3 $1\cr_bitfield_b[2:0] + attribute \src "libresoc.v:111776.3-111786.6" + wire $1\cr_bitfield_b_ok[0:0] + attribute \src "libresoc.v:111836.3-111846.6" + wire width 3 $1\cr_bitfield_o[2:0] + attribute \src "libresoc.v:111847.3-111857.6" + wire $1\cr_bitfield_o_ok[0:0] + attribute \src "libresoc.v:111749.3-111775.6" + wire $1\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:111885.3-111903.6" + wire width 8 $1\cr_fxm[7:0] + attribute \src "libresoc.v:111787.3-111797.6" + wire $1\cr_fxm_ok[0:0] + attribute \src "libresoc.v:111858.3-111868.6" + wire $1\move_one[0:0] + attribute \src "libresoc.v:111869.3-111884.6" + wire width 8 $1\ppick_i[7:0] + attribute \src "libresoc.v:111885.3-111903.6" + wire width 8 $2\cr_fxm[7:0] + attribute \src "libresoc.v:111869.3-111884.6" + wire width 8 $2\ppick_i[7:0] + attribute \src "libresoc.v:111742.17-111742.112" + wire $and$libresoc.v:111742$4392_Y + attribute \src "libresoc.v:111744.17-111744.112" + wire $and$libresoc.v:111744$4394_Y + attribute \src "libresoc.v:111741.17-111741.121" + wire $eq$libresoc.v:111741$4391_Y + attribute \src "libresoc.v:111743.17-111743.121" + wire $eq$libresoc.v:111743$4393_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 4 \ALU_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 3 \ALU_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 8 \ALU_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 7 \ALU_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 5 \ALU_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 8 input 6 \ALU_FXM + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 input 2 \ALU_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 input 9 \X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \cr_bitfield + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \cr_bitfield_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_bitfield_b_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \cr_bitfield_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_bitfield_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_bitfield_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 8 \cr_fxm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_fxm_ok + attribute \src "libresoc.v:111608.7-111608.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486" + wire width 32 input 10 \insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:527" + wire \move_one + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 \ppick_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 \ppick_o + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:485" + wire width 3 input 1 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + cell $and $and$libresoc.v:111742$4392 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$1 + connect \B \move_one + connect \Y $and$libresoc.v:111742$4392_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + cell $and $and$libresoc.v:111744$4394 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$5 + connect \B \move_one + connect \Y $and$libresoc.v:111744$4394_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + cell $eq $eq$libresoc.v:111741$4391 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \ALU_internal_op + connect \B 7'0101101 + connect \Y $eq$libresoc.v:111741$4391_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + cell $eq $eq$libresoc.v:111743$4393 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \ALU_internal_op + connect \B 7'0101101 + connect \Y $eq$libresoc.v:111743$4393_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:111745.9-111748.4" + cell \ppick \ppick + connect \i \ppick_i + connect \o \ppick_o + end + attribute \src "libresoc.v:111608.7-111608.20" + process $proc$libresoc.v:111608$4405 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:111749.3-111775.6" + process $proc$libresoc.v:111749$4395 + assign { } { } + assign { } { } + assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:111750.5-111750.29" + switch \initial + attribute \src "libresoc.v:111750.9-111750.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 3'101 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + case + assign $1\cr_bitfield_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] + end + attribute \src "libresoc.v:111776.3-111786.6" + process $proc$libresoc.v:111776$4396 + assign { } { } + assign { } { } + assign $0\cr_bitfield_b_ok[0:0] $1\cr_bitfield_b_ok[0:0] + attribute \src "libresoc.v:111777.5-111777.29" + switch \initial + attribute \src "libresoc.v:111777.9-111777.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_b_ok[0:0] 1'1 + case + assign $1\cr_bitfield_b_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_b_ok $0\cr_bitfield_b_ok[0:0] + end + attribute \src "libresoc.v:111787.3-111797.6" + process $proc$libresoc.v:111787$4397 + assign { } { } + assign { } { } + assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] + attribute \src "libresoc.v:111788.5-111788.29" + switch \initial + attribute \src "libresoc.v:111788.9-111788.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\cr_fxm_ok[0:0] 1'1 + case + assign $1\cr_fxm_ok[0:0] 1'0 + end + sync always + update \cr_fxm_ok $0\cr_fxm_ok[0:0] + end + attribute \src "libresoc.v:111798.3-111824.6" + process $proc$libresoc.v:111798$4398 + assign { } { } + assign { } { } + assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] + attribute \src "libresoc.v:111799.5-111799.29" + switch \initial + attribute \src "libresoc.v:111799.9-111799.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\cr_bitfield[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\cr_bitfield[2:0] \ALU_BI [4:2] + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield[2:0] \X_BFA + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield[2:0] \ALU_BA [4:2] + attribute \src "libresoc.v:0.0-0.0" + case 3'101 + assign { } { } + assign $1\cr_bitfield[2:0] \ALU_BC [4:2] + case + assign $1\cr_bitfield[2:0] 3'000 + end + sync always + update \cr_bitfield $0\cr_bitfield[2:0] + end + attribute \src "libresoc.v:111825.3-111835.6" + process $proc$libresoc.v:111825$4399 + assign { } { } + assign { } { } + assign $0\cr_bitfield_b[2:0] $1\cr_bitfield_b[2:0] + attribute \src "libresoc.v:111826.5-111826.29" + switch \initial + attribute \src "libresoc.v:111826.9-111826.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_b[2:0] \ALU_BB [4:2] + case + assign $1\cr_bitfield_b[2:0] 3'000 + end + sync always + update \cr_bitfield_b $0\cr_bitfield_b[2:0] + end + attribute \src "libresoc.v:111836.3-111846.6" + process $proc$libresoc.v:111836$4400 + assign { } { } + assign { } { } + assign $0\cr_bitfield_o[2:0] $1\cr_bitfield_o[2:0] + attribute \src "libresoc.v:111837.5-111837.29" + switch \initial + attribute \src "libresoc.v:111837.9-111837.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_o[2:0] \ALU_BT [4:2] + case + assign $1\cr_bitfield_o[2:0] 3'000 + end + sync always + update \cr_bitfield_o $0\cr_bitfield_o[2:0] + end + attribute \src "libresoc.v:111847.3-111857.6" + process $proc$libresoc.v:111847$4401 + assign { } { } + assign { } { } + assign $0\cr_bitfield_o_ok[0:0] $1\cr_bitfield_o_ok[0:0] + attribute \src "libresoc.v:111848.5-111848.29" + switch \initial + attribute \src "libresoc.v:111848.9-111848.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_o_ok[0:0] 1'1 + case + assign $1\cr_bitfield_o_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_o_ok $0\cr_bitfield_o_ok[0:0] + end + attribute \src "libresoc.v:111858.3-111868.6" + process $proc$libresoc.v:111858$4402 + assign { } { } + assign { } { } + assign $0\move_one[0:0] $1\move_one[0:0] + attribute \src "libresoc.v:111859.5-111859.29" + switch \initial + attribute \src "libresoc.v:111859.9-111859.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\move_one[0:0] \insn_in [20] + case + assign $1\move_one[0:0] 1'0 + end + sync always + update \move_one $0\move_one[0:0] + end + attribute \src "libresoc.v:111869.3-111884.6" + process $proc$libresoc.v:111869$4403 + assign { } { } + assign { } { } + assign $0\ppick_i[7:0] $1\ppick_i[7:0] + attribute \src "libresoc.v:111870.5-111870.29" + switch \initial + attribute \src "libresoc.v:111870.9-111870.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\ppick_i[7:0] $2\ppick_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ppick_i[7:0] \ALU_FXM + case + assign $2\ppick_i[7:0] 8'00000000 + end + case + assign $1\ppick_i[7:0] 8'00000000 + end + sync always + update \ppick_i $0\ppick_i[7:0] + end + attribute \src "libresoc.v:111885.3-111903.6" + process $proc$libresoc.v:111885$4404 + assign { } { } + assign { } { } + assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] + attribute \src "libresoc.v:111886.5-111886.29" + switch \initial + attribute \src "libresoc.v:111886.9-111886.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + switch \$7 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_fxm[7:0] \ppick_o + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cr_fxm[7:0] 8'11111111 + end + case + assign $1\cr_fxm[7:0] 8'00000000 + end + sync always + update \cr_fxm $0\cr_fxm[7:0] + end + connect \$1 $eq$libresoc.v:111741$4391_Y + connect \$3 $and$libresoc.v:111742$4392_Y + connect \$5 $eq$libresoc.v:111743$4393_Y + connect \$7 $and$libresoc.v:111744$4394_Y +end +attribute \src "libresoc.v:111908.1-112205.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_CR.dec_cr_in" +attribute \generator "nMigen" +module \dec_cr_in$140 + attribute \src "libresoc.v:112099.3-112125.6" + wire width 3 $0\cr_bitfield[2:0] + attribute \src "libresoc.v:112126.3-112136.6" + wire width 3 $0\cr_bitfield_b[2:0] + attribute \src "libresoc.v:112077.3-112087.6" + wire $0\cr_bitfield_b_ok[0:0] + attribute \src "libresoc.v:112137.3-112147.6" + wire width 3 $0\cr_bitfield_o[2:0] + attribute \src "libresoc.v:112148.3-112158.6" + wire $0\cr_bitfield_o_ok[0:0] + attribute \src "libresoc.v:112050.3-112076.6" + wire $0\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:112186.3-112204.6" + wire width 8 $0\cr_fxm[7:0] + attribute \src "libresoc.v:112088.3-112098.6" + wire $0\cr_fxm_ok[0:0] + attribute \src "libresoc.v:111909.7-111909.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:112159.3-112169.6" + wire $0\move_one[0:0] + attribute \src "libresoc.v:112170.3-112185.6" + wire width 8 $0\ppick_i[7:0] + attribute \src "libresoc.v:112099.3-112125.6" + wire width 3 $1\cr_bitfield[2:0] + attribute \src "libresoc.v:112126.3-112136.6" + wire width 3 $1\cr_bitfield_b[2:0] + attribute \src "libresoc.v:112077.3-112087.6" + wire $1\cr_bitfield_b_ok[0:0] + attribute \src "libresoc.v:112137.3-112147.6" + wire width 3 $1\cr_bitfield_o[2:0] + attribute \src "libresoc.v:112148.3-112158.6" + wire $1\cr_bitfield_o_ok[0:0] + attribute \src "libresoc.v:112050.3-112076.6" + wire $1\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:112186.3-112204.6" + wire width 8 $1\cr_fxm[7:0] + attribute \src "libresoc.v:112088.3-112098.6" + wire $1\cr_fxm_ok[0:0] + attribute \src "libresoc.v:112159.3-112169.6" + wire $1\move_one[0:0] + attribute \src "libresoc.v:112170.3-112185.6" + wire width 8 $1\ppick_i[7:0] + attribute \src "libresoc.v:112186.3-112204.6" + wire width 8 $2\cr_fxm[7:0] + attribute \src "libresoc.v:112170.3-112185.6" + wire width 8 $2\ppick_i[7:0] + attribute \src "libresoc.v:112043.17-112043.112" + wire $and$libresoc.v:112043$4407_Y + attribute \src "libresoc.v:112045.17-112045.112" + wire $and$libresoc.v:112045$4409_Y + attribute \src "libresoc.v:112042.17-112042.120" + wire $eq$libresoc.v:112042$4406_Y + attribute \src "libresoc.v:112044.17-112044.120" + wire $eq$libresoc.v:112044$4408_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 4 \CR_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 3 \CR_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 8 \CR_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 7 \CR_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 5 \CR_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 8 input 6 \CR_FXM + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 input 2 \CR_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 input 9 \X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \cr_bitfield + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \cr_bitfield_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_bitfield_b_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \cr_bitfield_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_bitfield_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_bitfield_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 8 \cr_fxm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_fxm_ok + attribute \src "libresoc.v:111909.7-111909.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486" + wire width 32 input 10 \insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:527" + wire \move_one + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 \ppick_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 \ppick_o + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:485" + wire width 3 input 1 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + cell $and $and$libresoc.v:112043$4407 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$1 + connect \B \move_one + connect \Y $and$libresoc.v:112043$4407_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + cell $and $and$libresoc.v:112045$4409 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$5 + connect \B \move_one + connect \Y $and$libresoc.v:112045$4409_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + cell $eq $eq$libresoc.v:112042$4406 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \CR_internal_op + connect \B 7'0101101 + connect \Y $eq$libresoc.v:112042$4406_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + cell $eq $eq$libresoc.v:112044$4408 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \CR_internal_op + connect \B 7'0101101 + connect \Y $eq$libresoc.v:112044$4408_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:112046.15-112049.4" + cell \ppick$141 \ppick + connect \i \ppick_i + connect \o \ppick_o + end + attribute \src "libresoc.v:111909.7-111909.20" + process $proc$libresoc.v:111909$4420 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:112050.3-112076.6" + process $proc$libresoc.v:112050$4410 + assign { } { } + assign { } { } + assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:112051.5-112051.29" + switch \initial + attribute \src "libresoc.v:112051.9-112051.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 3'101 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + case + assign $1\cr_bitfield_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] + end + attribute \src "libresoc.v:112077.3-112087.6" + process $proc$libresoc.v:112077$4411 + assign { } { } + assign { } { } + assign $0\cr_bitfield_b_ok[0:0] $1\cr_bitfield_b_ok[0:0] + attribute \src "libresoc.v:112078.5-112078.29" + switch \initial + attribute \src "libresoc.v:112078.9-112078.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_b_ok[0:0] 1'1 + case + assign $1\cr_bitfield_b_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_b_ok $0\cr_bitfield_b_ok[0:0] + end + attribute \src "libresoc.v:112088.3-112098.6" + process $proc$libresoc.v:112088$4412 + assign { } { } + assign { } { } + assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] + attribute \src "libresoc.v:112089.5-112089.29" + switch \initial + attribute \src "libresoc.v:112089.9-112089.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\cr_fxm_ok[0:0] 1'1 + case + assign $1\cr_fxm_ok[0:0] 1'0 + end + sync always + update \cr_fxm_ok $0\cr_fxm_ok[0:0] + end + attribute \src "libresoc.v:112099.3-112125.6" + process $proc$libresoc.v:112099$4413 + assign { } { } + assign { } { } + assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] + attribute \src "libresoc.v:112100.5-112100.29" + switch \initial + attribute \src "libresoc.v:112100.9-112100.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\cr_bitfield[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\cr_bitfield[2:0] \CR_BI [4:2] + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield[2:0] \X_BFA + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield[2:0] \CR_BA [4:2] + attribute \src "libresoc.v:0.0-0.0" + case 3'101 + assign { } { } + assign $1\cr_bitfield[2:0] \CR_BC [4:2] + case + assign $1\cr_bitfield[2:0] 3'000 + end + sync always + update \cr_bitfield $0\cr_bitfield[2:0] + end + attribute \src "libresoc.v:112126.3-112136.6" + process $proc$libresoc.v:112126$4414 + assign { } { } + assign { } { } + assign $0\cr_bitfield_b[2:0] $1\cr_bitfield_b[2:0] + attribute \src "libresoc.v:112127.5-112127.29" + switch \initial + attribute \src "libresoc.v:112127.9-112127.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_b[2:0] \CR_BB [4:2] + case + assign $1\cr_bitfield_b[2:0] 3'000 + end + sync always + update \cr_bitfield_b $0\cr_bitfield_b[2:0] + end + attribute \src "libresoc.v:112137.3-112147.6" + process $proc$libresoc.v:112137$4415 + assign { } { } + assign { } { } + assign $0\cr_bitfield_o[2:0] $1\cr_bitfield_o[2:0] + attribute \src "libresoc.v:112138.5-112138.29" + switch \initial + attribute \src "libresoc.v:112138.9-112138.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_o[2:0] \CR_BT [4:2] + case + assign $1\cr_bitfield_o[2:0] 3'000 + end + sync always + update \cr_bitfield_o $0\cr_bitfield_o[2:0] + end + attribute \src "libresoc.v:112148.3-112158.6" + process $proc$libresoc.v:112148$4416 + assign { } { } + assign { } { } + assign $0\cr_bitfield_o_ok[0:0] $1\cr_bitfield_o_ok[0:0] + attribute \src "libresoc.v:112149.5-112149.29" + switch \initial + attribute \src "libresoc.v:112149.9-112149.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_o_ok[0:0] 1'1 + case + assign $1\cr_bitfield_o_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_o_ok $0\cr_bitfield_o_ok[0:0] + end + attribute \src "libresoc.v:112159.3-112169.6" + process $proc$libresoc.v:112159$4417 + assign { } { } + assign { } { } + assign $0\move_one[0:0] $1\move_one[0:0] + attribute \src "libresoc.v:112160.5-112160.29" + switch \initial + attribute \src "libresoc.v:112160.9-112160.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\move_one[0:0] \insn_in [20] + case + assign $1\move_one[0:0] 1'0 + end + sync always + update \move_one $0\move_one[0:0] + end + attribute \src "libresoc.v:112170.3-112185.6" + process $proc$libresoc.v:112170$4418 + assign { } { } + assign { } { } + assign $0\ppick_i[7:0] $1\ppick_i[7:0] + attribute \src "libresoc.v:112171.5-112171.29" + switch \initial + attribute \src "libresoc.v:112171.9-112171.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\ppick_i[7:0] $2\ppick_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ppick_i[7:0] \CR_FXM + case + assign $2\ppick_i[7:0] 8'00000000 + end + case + assign $1\ppick_i[7:0] 8'00000000 + end + sync always + update \ppick_i $0\ppick_i[7:0] + end + attribute \src "libresoc.v:112186.3-112204.6" + process $proc$libresoc.v:112186$4419 + assign { } { } + assign { } { } + assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] + attribute \src "libresoc.v:112187.5-112187.29" + switch \initial + attribute \src "libresoc.v:112187.9-112187.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + switch \$7 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_fxm[7:0] \ppick_o + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cr_fxm[7:0] 8'11111111 + end + case + assign $1\cr_fxm[7:0] 8'00000000 + end + sync always + update \cr_fxm $0\cr_fxm[7:0] + end + connect \$1 $eq$libresoc.v:112042$4406_Y + connect \$3 $and$libresoc.v:112043$4407_Y + connect \$5 $eq$libresoc.v:112044$4408_Y + connect \$7 $and$libresoc.v:112045$4409_Y +end +attribute \src "libresoc.v:112209.1-112506.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_BRANCH.dec_cr_in" +attribute \generator "nMigen" +module \dec_cr_in$147 + attribute \src "libresoc.v:112400.3-112426.6" + wire width 3 $0\cr_bitfield[2:0] + attribute \src "libresoc.v:112427.3-112437.6" + wire width 3 $0\cr_bitfield_b[2:0] + attribute \src "libresoc.v:112378.3-112388.6" + wire $0\cr_bitfield_b_ok[0:0] + attribute \src "libresoc.v:112438.3-112448.6" + wire width 3 $0\cr_bitfield_o[2:0] + attribute \src "libresoc.v:112449.3-112459.6" + wire $0\cr_bitfield_o_ok[0:0] + attribute \src "libresoc.v:112351.3-112377.6" + wire $0\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:112487.3-112505.6" + wire width 8 $0\cr_fxm[7:0] + attribute \src "libresoc.v:112389.3-112399.6" + wire $0\cr_fxm_ok[0:0] + attribute \src "libresoc.v:112210.7-112210.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:112460.3-112470.6" + wire $0\move_one[0:0] + attribute \src "libresoc.v:112471.3-112486.6" + wire width 8 $0\ppick_i[7:0] + attribute \src "libresoc.v:112400.3-112426.6" + wire width 3 $1\cr_bitfield[2:0] + attribute \src "libresoc.v:112427.3-112437.6" + wire width 3 $1\cr_bitfield_b[2:0] + attribute \src "libresoc.v:112378.3-112388.6" + wire $1\cr_bitfield_b_ok[0:0] + attribute \src "libresoc.v:112438.3-112448.6" + wire width 3 $1\cr_bitfield_o[2:0] + attribute \src "libresoc.v:112449.3-112459.6" + wire $1\cr_bitfield_o_ok[0:0] + attribute \src "libresoc.v:112351.3-112377.6" + wire $1\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:112487.3-112505.6" + wire width 8 $1\cr_fxm[7:0] + attribute \src "libresoc.v:112389.3-112399.6" + wire $1\cr_fxm_ok[0:0] + attribute \src "libresoc.v:112460.3-112470.6" + wire $1\move_one[0:0] + attribute \src "libresoc.v:112471.3-112486.6" + wire width 8 $1\ppick_i[7:0] + attribute \src "libresoc.v:112487.3-112505.6" + wire width 8 $2\cr_fxm[7:0] + attribute \src "libresoc.v:112471.3-112486.6" + wire width 8 $2\ppick_i[7:0] + attribute \src "libresoc.v:112344.17-112344.112" + wire $and$libresoc.v:112344$4422_Y + attribute \src "libresoc.v:112346.17-112346.112" + wire $and$libresoc.v:112346$4424_Y + attribute \src "libresoc.v:112343.17-112343.124" + wire $eq$libresoc.v:112343$4421_Y + attribute \src "libresoc.v:112345.17-112345.124" + wire $eq$libresoc.v:112345$4423_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 4 \BRANCH_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 3 \BRANCH_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 8 \BRANCH_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 7 \BRANCH_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 5 \BRANCH_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 8 input 6 \BRANCH_FXM + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 input 2 \BRANCH_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 input 9 \X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \cr_bitfield + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \cr_bitfield_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_bitfield_b_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \cr_bitfield_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_bitfield_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_bitfield_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 8 \cr_fxm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_fxm_ok + attribute \src "libresoc.v:112210.7-112210.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486" + wire width 32 input 10 \insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:527" + wire \move_one + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 \ppick_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 \ppick_o + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:485" + wire width 3 input 1 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + cell $and $and$libresoc.v:112344$4422 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$1 + connect \B \move_one + connect \Y $and$libresoc.v:112344$4422_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + cell $and $and$libresoc.v:112346$4424 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$5 + connect \B \move_one + connect \Y $and$libresoc.v:112346$4424_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + cell $eq $eq$libresoc.v:112343$4421 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \BRANCH_internal_op + connect \B 7'0101101 + connect \Y $eq$libresoc.v:112343$4421_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + cell $eq $eq$libresoc.v:112345$4423 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \BRANCH_internal_op + connect \B 7'0101101 + connect \Y $eq$libresoc.v:112345$4423_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:112347.15-112350.4" + cell \ppick$148 \ppick + connect \i \ppick_i + connect \o \ppick_o + end + attribute \src "libresoc.v:112210.7-112210.20" + process $proc$libresoc.v:112210$4435 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:112351.3-112377.6" + process $proc$libresoc.v:112351$4425 + assign { } { } + assign { } { } + assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:112352.5-112352.29" + switch \initial + attribute \src "libresoc.v:112352.9-112352.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 3'101 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + case + assign $1\cr_bitfield_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] + end + attribute \src "libresoc.v:112378.3-112388.6" + process $proc$libresoc.v:112378$4426 + assign { } { } + assign { } { } + assign $0\cr_bitfield_b_ok[0:0] $1\cr_bitfield_b_ok[0:0] + attribute \src "libresoc.v:112379.5-112379.29" + switch \initial + attribute \src "libresoc.v:112379.9-112379.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_b_ok[0:0] 1'1 + case + assign $1\cr_bitfield_b_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_b_ok $0\cr_bitfield_b_ok[0:0] + end + attribute \src "libresoc.v:112389.3-112399.6" + process $proc$libresoc.v:112389$4427 + assign { } { } + assign { } { } + assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] + attribute \src "libresoc.v:112390.5-112390.29" + switch \initial + attribute \src "libresoc.v:112390.9-112390.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\cr_fxm_ok[0:0] 1'1 + case + assign $1\cr_fxm_ok[0:0] 1'0 + end + sync always + update \cr_fxm_ok $0\cr_fxm_ok[0:0] + end + attribute \src "libresoc.v:112400.3-112426.6" + process $proc$libresoc.v:112400$4428 + assign { } { } + assign { } { } + assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] + attribute \src "libresoc.v:112401.5-112401.29" + switch \initial + attribute \src "libresoc.v:112401.9-112401.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\cr_bitfield[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\cr_bitfield[2:0] \BRANCH_BI [4:2] + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield[2:0] \X_BFA + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield[2:0] \BRANCH_BA [4:2] + attribute \src "libresoc.v:0.0-0.0" + case 3'101 + assign { } { } + assign $1\cr_bitfield[2:0] \BRANCH_BC [4:2] + case + assign $1\cr_bitfield[2:0] 3'000 + end + sync always + update \cr_bitfield $0\cr_bitfield[2:0] + end + attribute \src "libresoc.v:112427.3-112437.6" + process $proc$libresoc.v:112427$4429 + assign { } { } + assign { } { } + assign $0\cr_bitfield_b[2:0] $1\cr_bitfield_b[2:0] + attribute \src "libresoc.v:112428.5-112428.29" + switch \initial + attribute \src "libresoc.v:112428.9-112428.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_b[2:0] \BRANCH_BB [4:2] + case + assign $1\cr_bitfield_b[2:0] 3'000 + end + sync always + update \cr_bitfield_b $0\cr_bitfield_b[2:0] + end + attribute \src "libresoc.v:112438.3-112448.6" + process $proc$libresoc.v:112438$4430 + assign { } { } + assign { } { } + assign $0\cr_bitfield_o[2:0] $1\cr_bitfield_o[2:0] + attribute \src "libresoc.v:112439.5-112439.29" + switch \initial + attribute \src "libresoc.v:112439.9-112439.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_o[2:0] \BRANCH_BT [4:2] + case + assign $1\cr_bitfield_o[2:0] 3'000 + end + sync always + update \cr_bitfield_o $0\cr_bitfield_o[2:0] + end + attribute \src "libresoc.v:112449.3-112459.6" + process $proc$libresoc.v:112449$4431 + assign { } { } + assign { } { } + assign $0\cr_bitfield_o_ok[0:0] $1\cr_bitfield_o_ok[0:0] + attribute \src "libresoc.v:112450.5-112450.29" + switch \initial + attribute \src "libresoc.v:112450.9-112450.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_o_ok[0:0] 1'1 + case + assign $1\cr_bitfield_o_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_o_ok $0\cr_bitfield_o_ok[0:0] + end + attribute \src "libresoc.v:112460.3-112470.6" + process $proc$libresoc.v:112460$4432 + assign { } { } + assign { } { } + assign $0\move_one[0:0] $1\move_one[0:0] + attribute \src "libresoc.v:112461.5-112461.29" + switch \initial + attribute \src "libresoc.v:112461.9-112461.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\move_one[0:0] \insn_in [20] + case + assign $1\move_one[0:0] 1'0 + end + sync always + update \move_one $0\move_one[0:0] + end + attribute \src "libresoc.v:112471.3-112486.6" + process $proc$libresoc.v:112471$4433 + assign { } { } + assign { } { } + assign $0\ppick_i[7:0] $1\ppick_i[7:0] + attribute \src "libresoc.v:112472.5-112472.29" + switch \initial + attribute \src "libresoc.v:112472.9-112472.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\ppick_i[7:0] $2\ppick_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ppick_i[7:0] \BRANCH_FXM + case + assign $2\ppick_i[7:0] 8'00000000 + end + case + assign $1\ppick_i[7:0] 8'00000000 + end + sync always + update \ppick_i $0\ppick_i[7:0] + end + attribute \src "libresoc.v:112487.3-112505.6" + process $proc$libresoc.v:112487$4434 + assign { } { } + assign { } { } + assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] + attribute \src "libresoc.v:112488.5-112488.29" + switch \initial + attribute \src "libresoc.v:112488.9-112488.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + switch \$7 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_fxm[7:0] \ppick_o + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cr_fxm[7:0] 8'11111111 + end + case + assign $1\cr_fxm[7:0] 8'00000000 + end + sync always + update \cr_fxm $0\cr_fxm[7:0] + end + connect \$1 $eq$libresoc.v:112343$4421_Y + connect \$3 $and$libresoc.v:112344$4422_Y + connect \$5 $eq$libresoc.v:112345$4423_Y + connect \$7 $and$libresoc.v:112346$4424_Y +end +attribute \src "libresoc.v:112510.1-112807.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_LOGICAL.dec_cr_in" +attribute \generator "nMigen" +module \dec_cr_in$155 + attribute \src "libresoc.v:112701.3-112727.6" + wire width 3 $0\cr_bitfield[2:0] + attribute \src "libresoc.v:112728.3-112738.6" + wire width 3 $0\cr_bitfield_b[2:0] + attribute \src "libresoc.v:112679.3-112689.6" + wire $0\cr_bitfield_b_ok[0:0] + attribute \src "libresoc.v:112739.3-112749.6" + wire width 3 $0\cr_bitfield_o[2:0] + attribute \src "libresoc.v:112750.3-112760.6" + wire $0\cr_bitfield_o_ok[0:0] + attribute \src "libresoc.v:112652.3-112678.6" + wire $0\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:112788.3-112806.6" + wire width 8 $0\cr_fxm[7:0] + attribute \src "libresoc.v:112690.3-112700.6" + wire $0\cr_fxm_ok[0:0] + attribute \src "libresoc.v:112511.7-112511.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:112761.3-112771.6" + wire $0\move_one[0:0] + attribute \src "libresoc.v:112772.3-112787.6" + wire width 8 $0\ppick_i[7:0] + attribute \src "libresoc.v:112701.3-112727.6" + wire width 3 $1\cr_bitfield[2:0] + attribute \src "libresoc.v:112728.3-112738.6" + wire width 3 $1\cr_bitfield_b[2:0] + attribute \src "libresoc.v:112679.3-112689.6" + wire $1\cr_bitfield_b_ok[0:0] + attribute \src "libresoc.v:112739.3-112749.6" + wire width 3 $1\cr_bitfield_o[2:0] + attribute \src "libresoc.v:112750.3-112760.6" + wire $1\cr_bitfield_o_ok[0:0] + attribute \src "libresoc.v:112652.3-112678.6" + wire $1\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:112788.3-112806.6" + wire width 8 $1\cr_fxm[7:0] + attribute \src "libresoc.v:112690.3-112700.6" + wire $1\cr_fxm_ok[0:0] + attribute \src "libresoc.v:112761.3-112771.6" + wire $1\move_one[0:0] + attribute \src "libresoc.v:112772.3-112787.6" + wire width 8 $1\ppick_i[7:0] + attribute \src "libresoc.v:112788.3-112806.6" + wire width 8 $2\cr_fxm[7:0] + attribute \src "libresoc.v:112772.3-112787.6" + wire width 8 $2\ppick_i[7:0] + attribute \src "libresoc.v:112645.17-112645.112" + wire $and$libresoc.v:112645$4437_Y + attribute \src "libresoc.v:112647.17-112647.112" + wire $and$libresoc.v:112647$4439_Y + attribute \src "libresoc.v:112644.17-112644.125" + wire $eq$libresoc.v:112644$4436_Y + attribute \src "libresoc.v:112646.17-112646.125" + wire $eq$libresoc.v:112646$4438_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 4 \LOGICAL_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 3 \LOGICAL_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 8 \LOGICAL_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 7 \LOGICAL_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 5 \LOGICAL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 8 input 6 \LOGICAL_FXM + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 input 2 \LOGICAL_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 input 9 \X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \cr_bitfield + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \cr_bitfield_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_bitfield_b_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \cr_bitfield_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_bitfield_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_bitfield_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 8 \cr_fxm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_fxm_ok + attribute \src "libresoc.v:112511.7-112511.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486" + wire width 32 input 10 \insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:527" + wire \move_one + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 \ppick_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 \ppick_o + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:485" + wire width 3 input 1 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + cell $and $and$libresoc.v:112645$4437 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$1 + connect \B \move_one + connect \Y $and$libresoc.v:112645$4437_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + cell $and $and$libresoc.v:112647$4439 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$5 + connect \B \move_one + connect \Y $and$libresoc.v:112647$4439_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + cell $eq $eq$libresoc.v:112644$4436 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \LOGICAL_internal_op + connect \B 7'0101101 + connect \Y $eq$libresoc.v:112644$4436_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + cell $eq $eq$libresoc.v:112646$4438 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \LOGICAL_internal_op + connect \B 7'0101101 + connect \Y $eq$libresoc.v:112646$4438_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:112648.15-112651.4" + cell \ppick$156 \ppick + connect \i \ppick_i + connect \o \ppick_o + end + attribute \src "libresoc.v:112511.7-112511.20" + process $proc$libresoc.v:112511$4450 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:112652.3-112678.6" + process $proc$libresoc.v:112652$4440 + assign { } { } + assign { } { } + assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:112653.5-112653.29" + switch \initial + attribute \src "libresoc.v:112653.9-112653.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 3'101 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + case + assign $1\cr_bitfield_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] + end + attribute \src "libresoc.v:112679.3-112689.6" + process $proc$libresoc.v:112679$4441 + assign { } { } + assign { } { } + assign $0\cr_bitfield_b_ok[0:0] $1\cr_bitfield_b_ok[0:0] + attribute \src "libresoc.v:112680.5-112680.29" + switch \initial + attribute \src "libresoc.v:112680.9-112680.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_b_ok[0:0] 1'1 + case + assign $1\cr_bitfield_b_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_b_ok $0\cr_bitfield_b_ok[0:0] + end + attribute \src "libresoc.v:112690.3-112700.6" + process $proc$libresoc.v:112690$4442 + assign { } { } + assign { } { } + assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] + attribute \src "libresoc.v:112691.5-112691.29" + switch \initial + attribute \src "libresoc.v:112691.9-112691.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\cr_fxm_ok[0:0] 1'1 + case + assign $1\cr_fxm_ok[0:0] 1'0 + end + sync always + update \cr_fxm_ok $0\cr_fxm_ok[0:0] + end + attribute \src "libresoc.v:112701.3-112727.6" + process $proc$libresoc.v:112701$4443 + assign { } { } + assign { } { } + assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] + attribute \src "libresoc.v:112702.5-112702.29" + switch \initial + attribute \src "libresoc.v:112702.9-112702.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\cr_bitfield[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\cr_bitfield[2:0] \LOGICAL_BI [4:2] + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield[2:0] \X_BFA + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield[2:0] \LOGICAL_BA [4:2] + attribute \src "libresoc.v:0.0-0.0" + case 3'101 + assign { } { } + assign $1\cr_bitfield[2:0] \LOGICAL_BC [4:2] + case + assign $1\cr_bitfield[2:0] 3'000 + end + sync always + update \cr_bitfield $0\cr_bitfield[2:0] + end + attribute \src "libresoc.v:112728.3-112738.6" + process $proc$libresoc.v:112728$4444 + assign { } { } + assign { } { } + assign $0\cr_bitfield_b[2:0] $1\cr_bitfield_b[2:0] + attribute \src "libresoc.v:112729.5-112729.29" + switch \initial + attribute \src "libresoc.v:112729.9-112729.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_b[2:0] \LOGICAL_BB [4:2] + case + assign $1\cr_bitfield_b[2:0] 3'000 + end + sync always + update \cr_bitfield_b $0\cr_bitfield_b[2:0] + end + attribute \src "libresoc.v:112739.3-112749.6" + process $proc$libresoc.v:112739$4445 + assign { } { } + assign { } { } + assign $0\cr_bitfield_o[2:0] $1\cr_bitfield_o[2:0] + attribute \src "libresoc.v:112740.5-112740.29" + switch \initial + attribute \src "libresoc.v:112740.9-112740.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_o[2:0] \LOGICAL_BT [4:2] + case + assign $1\cr_bitfield_o[2:0] 3'000 + end + sync always + update \cr_bitfield_o $0\cr_bitfield_o[2:0] + end + attribute \src "libresoc.v:112750.3-112760.6" + process $proc$libresoc.v:112750$4446 + assign { } { } + assign { } { } + assign $0\cr_bitfield_o_ok[0:0] $1\cr_bitfield_o_ok[0:0] + attribute \src "libresoc.v:112751.5-112751.29" + switch \initial + attribute \src "libresoc.v:112751.9-112751.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_o_ok[0:0] 1'1 + case + assign $1\cr_bitfield_o_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_o_ok $0\cr_bitfield_o_ok[0:0] + end + attribute \src "libresoc.v:112761.3-112771.6" + process $proc$libresoc.v:112761$4447 + assign { } { } + assign { } { } + assign $0\move_one[0:0] $1\move_one[0:0] + attribute \src "libresoc.v:112762.5-112762.29" + switch \initial + attribute \src "libresoc.v:112762.9-112762.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\move_one[0:0] \insn_in [20] + case + assign $1\move_one[0:0] 1'0 + end + sync always + update \move_one $0\move_one[0:0] + end + attribute \src "libresoc.v:112772.3-112787.6" + process $proc$libresoc.v:112772$4448 + assign { } { } + assign { } { } + assign $0\ppick_i[7:0] $1\ppick_i[7:0] + attribute \src "libresoc.v:112773.5-112773.29" + switch \initial + attribute \src "libresoc.v:112773.9-112773.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\ppick_i[7:0] $2\ppick_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ppick_i[7:0] \LOGICAL_FXM + case + assign $2\ppick_i[7:0] 8'00000000 + end + case + assign $1\ppick_i[7:0] 8'00000000 + end + sync always + update \ppick_i $0\ppick_i[7:0] + end + attribute \src "libresoc.v:112788.3-112806.6" + process $proc$libresoc.v:112788$4449 + assign { } { } + assign { } { } + assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] + attribute \src "libresoc.v:112789.5-112789.29" + switch \initial + attribute \src "libresoc.v:112789.9-112789.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + switch \$7 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_fxm[7:0] \ppick_o + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cr_fxm[7:0] 8'11111111 + end + case + assign $1\cr_fxm[7:0] 8'00000000 + end + sync always + update \cr_fxm $0\cr_fxm[7:0] + end + connect \$1 $eq$libresoc.v:112644$4436_Y + connect \$3 $and$libresoc.v:112645$4437_Y + connect \$5 $eq$libresoc.v:112646$4438_Y + connect \$7 $and$libresoc.v:112647$4439_Y +end +attribute \src "libresoc.v:112811.1-113108.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_SPR.dec_cr_in" +attribute \generator "nMigen" +module \dec_cr_in$164 + attribute \src "libresoc.v:113002.3-113028.6" + wire width 3 $0\cr_bitfield[2:0] + attribute \src "libresoc.v:113029.3-113039.6" + wire width 3 $0\cr_bitfield_b[2:0] + attribute \src "libresoc.v:112980.3-112990.6" + wire $0\cr_bitfield_b_ok[0:0] + attribute \src "libresoc.v:113040.3-113050.6" + wire width 3 $0\cr_bitfield_o[2:0] + attribute \src "libresoc.v:113051.3-113061.6" + wire $0\cr_bitfield_o_ok[0:0] + attribute \src "libresoc.v:112953.3-112979.6" + wire $0\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:113089.3-113107.6" + wire width 8 $0\cr_fxm[7:0] + attribute \src "libresoc.v:112991.3-113001.6" + wire $0\cr_fxm_ok[0:0] + attribute \src "libresoc.v:112812.7-112812.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:113062.3-113072.6" + wire $0\move_one[0:0] + attribute \src "libresoc.v:113073.3-113088.6" + wire width 8 $0\ppick_i[7:0] + attribute \src "libresoc.v:113002.3-113028.6" + wire width 3 $1\cr_bitfield[2:0] + attribute \src "libresoc.v:113029.3-113039.6" + wire width 3 $1\cr_bitfield_b[2:0] + attribute \src "libresoc.v:112980.3-112990.6" + wire $1\cr_bitfield_b_ok[0:0] + attribute \src "libresoc.v:113040.3-113050.6" + wire width 3 $1\cr_bitfield_o[2:0] + attribute \src "libresoc.v:113051.3-113061.6" + wire $1\cr_bitfield_o_ok[0:0] + attribute \src "libresoc.v:112953.3-112979.6" + wire $1\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:113089.3-113107.6" + wire width 8 $1\cr_fxm[7:0] + attribute \src "libresoc.v:112991.3-113001.6" + wire $1\cr_fxm_ok[0:0] + attribute \src "libresoc.v:113062.3-113072.6" + wire $1\move_one[0:0] + attribute \src "libresoc.v:113073.3-113088.6" + wire width 8 $1\ppick_i[7:0] + attribute \src "libresoc.v:113089.3-113107.6" + wire width 8 $2\cr_fxm[7:0] + attribute \src "libresoc.v:113073.3-113088.6" + wire width 8 $2\ppick_i[7:0] + attribute \src "libresoc.v:112946.17-112946.112" + wire $and$libresoc.v:112946$4452_Y + attribute \src "libresoc.v:112948.17-112948.112" + wire $and$libresoc.v:112948$4454_Y + attribute \src "libresoc.v:112945.17-112945.121" + wire $eq$libresoc.v:112945$4451_Y + attribute \src "libresoc.v:112947.17-112947.121" + wire $eq$libresoc.v:112947$4453_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 4 \SPR_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 3 \SPR_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 8 \SPR_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 7 \SPR_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 5 \SPR_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 8 input 6 \SPR_FXM + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 input 2 \SPR_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 input 9 \X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \cr_bitfield + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \cr_bitfield_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_bitfield_b_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \cr_bitfield_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_bitfield_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_bitfield_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 8 \cr_fxm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_fxm_ok + attribute \src "libresoc.v:112812.7-112812.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486" + wire width 32 input 10 \insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:527" + wire \move_one + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 \ppick_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 \ppick_o + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:485" + wire width 3 input 1 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + cell $and $and$libresoc.v:112946$4452 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$1 + connect \B \move_one + connect \Y $and$libresoc.v:112946$4452_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + cell $and $and$libresoc.v:112948$4454 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$5 + connect \B \move_one + connect \Y $and$libresoc.v:112948$4454_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + cell $eq $eq$libresoc.v:112945$4451 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \SPR_internal_op + connect \B 7'0101101 + connect \Y $eq$libresoc.v:112945$4451_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + cell $eq $eq$libresoc.v:112947$4453 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \SPR_internal_op + connect \B 7'0101101 + connect \Y $eq$libresoc.v:112947$4453_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:112949.15-112952.4" + cell \ppick$165 \ppick + connect \i \ppick_i + connect \o \ppick_o + end + attribute \src "libresoc.v:112812.7-112812.20" + process $proc$libresoc.v:112812$4465 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:112953.3-112979.6" + process $proc$libresoc.v:112953$4455 + assign { } { } + assign { } { } + assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:112954.5-112954.29" + switch \initial + attribute \src "libresoc.v:112954.9-112954.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 3'101 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + case + assign $1\cr_bitfield_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] + end + attribute \src "libresoc.v:112980.3-112990.6" + process $proc$libresoc.v:112980$4456 + assign { } { } + assign { } { } + assign $0\cr_bitfield_b_ok[0:0] $1\cr_bitfield_b_ok[0:0] + attribute \src "libresoc.v:112981.5-112981.29" + switch \initial + attribute \src "libresoc.v:112981.9-112981.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_b_ok[0:0] 1'1 + case + assign $1\cr_bitfield_b_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_b_ok $0\cr_bitfield_b_ok[0:0] + end + attribute \src "libresoc.v:112991.3-113001.6" + process $proc$libresoc.v:112991$4457 + assign { } { } + assign { } { } + assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] + attribute \src "libresoc.v:112992.5-112992.29" + switch \initial + attribute \src "libresoc.v:112992.9-112992.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\cr_fxm_ok[0:0] 1'1 + case + assign $1\cr_fxm_ok[0:0] 1'0 + end + sync always + update \cr_fxm_ok $0\cr_fxm_ok[0:0] + end + attribute \src "libresoc.v:113002.3-113028.6" + process $proc$libresoc.v:113002$4458 + assign { } { } + assign { } { } + assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] + attribute \src "libresoc.v:113003.5-113003.29" + switch \initial + attribute \src "libresoc.v:113003.9-113003.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\cr_bitfield[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\cr_bitfield[2:0] \SPR_BI [4:2] + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield[2:0] \X_BFA + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield[2:0] \SPR_BA [4:2] + attribute \src "libresoc.v:0.0-0.0" + case 3'101 + assign { } { } + assign $1\cr_bitfield[2:0] \SPR_BC [4:2] + case + assign $1\cr_bitfield[2:0] 3'000 + end + sync always + update \cr_bitfield $0\cr_bitfield[2:0] + end + attribute \src "libresoc.v:113029.3-113039.6" + process $proc$libresoc.v:113029$4459 + assign { } { } + assign { } { } + assign $0\cr_bitfield_b[2:0] $1\cr_bitfield_b[2:0] + attribute \src "libresoc.v:113030.5-113030.29" + switch \initial + attribute \src "libresoc.v:113030.9-113030.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_b[2:0] \SPR_BB [4:2] + case + assign $1\cr_bitfield_b[2:0] 3'000 + end + sync always + update \cr_bitfield_b $0\cr_bitfield_b[2:0] + end + attribute \src "libresoc.v:113040.3-113050.6" + process $proc$libresoc.v:113040$4460 + assign { } { } + assign { } { } + assign $0\cr_bitfield_o[2:0] $1\cr_bitfield_o[2:0] + attribute \src "libresoc.v:113041.5-113041.29" + switch \initial + attribute \src "libresoc.v:113041.9-113041.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_o[2:0] \SPR_BT [4:2] + case + assign $1\cr_bitfield_o[2:0] 3'000 + end + sync always + update \cr_bitfield_o $0\cr_bitfield_o[2:0] + end + attribute \src "libresoc.v:113051.3-113061.6" + process $proc$libresoc.v:113051$4461 + assign { } { } + assign { } { } + assign $0\cr_bitfield_o_ok[0:0] $1\cr_bitfield_o_ok[0:0] + attribute \src "libresoc.v:113052.5-113052.29" + switch \initial + attribute \src "libresoc.v:113052.9-113052.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_o_ok[0:0] 1'1 + case + assign $1\cr_bitfield_o_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_o_ok $0\cr_bitfield_o_ok[0:0] + end + attribute \src "libresoc.v:113062.3-113072.6" + process $proc$libresoc.v:113062$4462 + assign { } { } + assign { } { } + assign $0\move_one[0:0] $1\move_one[0:0] + attribute \src "libresoc.v:113063.5-113063.29" + switch \initial + attribute \src "libresoc.v:113063.9-113063.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\move_one[0:0] \insn_in [20] + case + assign $1\move_one[0:0] 1'0 + end + sync always + update \move_one $0\move_one[0:0] + end + attribute \src "libresoc.v:113073.3-113088.6" + process $proc$libresoc.v:113073$4463 + assign { } { } + assign { } { } + assign $0\ppick_i[7:0] $1\ppick_i[7:0] + attribute \src "libresoc.v:113074.5-113074.29" + switch \initial + attribute \src "libresoc.v:113074.9-113074.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\ppick_i[7:0] $2\ppick_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ppick_i[7:0] \SPR_FXM + case + assign $2\ppick_i[7:0] 8'00000000 + end + case + assign $1\ppick_i[7:0] 8'00000000 + end + sync always + update \ppick_i $0\ppick_i[7:0] + end + attribute \src "libresoc.v:113089.3-113107.6" + process $proc$libresoc.v:113089$4464 + assign { } { } + assign { } { } + assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] + attribute \src "libresoc.v:113090.5-113090.29" + switch \initial + attribute \src "libresoc.v:113090.9-113090.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + switch \$7 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_fxm[7:0] \ppick_o + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cr_fxm[7:0] 8'11111111 + end + case + assign $1\cr_fxm[7:0] 8'00000000 + end + sync always + update \cr_fxm $0\cr_fxm[7:0] + end + connect \$1 $eq$libresoc.v:112945$4451_Y + connect \$3 $and$libresoc.v:112946$4452_Y + connect \$5 $eq$libresoc.v:112947$4453_Y + connect \$7 $and$libresoc.v:112948$4454_Y +end +attribute \src "libresoc.v:113112.1-113409.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_DIV.dec_cr_in" +attribute \generator "nMigen" +module \dec_cr_in$171 + attribute \src "libresoc.v:113303.3-113329.6" + wire width 3 $0\cr_bitfield[2:0] + attribute \src "libresoc.v:113330.3-113340.6" + wire width 3 $0\cr_bitfield_b[2:0] + attribute \src "libresoc.v:113281.3-113291.6" + wire $0\cr_bitfield_b_ok[0:0] + attribute \src "libresoc.v:113341.3-113351.6" + wire width 3 $0\cr_bitfield_o[2:0] + attribute \src "libresoc.v:113352.3-113362.6" + wire $0\cr_bitfield_o_ok[0:0] + attribute \src "libresoc.v:113254.3-113280.6" + wire $0\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:113390.3-113408.6" + wire width 8 $0\cr_fxm[7:0] + attribute \src "libresoc.v:113292.3-113302.6" + wire $0\cr_fxm_ok[0:0] + attribute \src "libresoc.v:113113.7-113113.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:113363.3-113373.6" + wire $0\move_one[0:0] + attribute \src "libresoc.v:113374.3-113389.6" + wire width 8 $0\ppick_i[7:0] + attribute \src "libresoc.v:113303.3-113329.6" + wire width 3 $1\cr_bitfield[2:0] + attribute \src "libresoc.v:113330.3-113340.6" + wire width 3 $1\cr_bitfield_b[2:0] + attribute \src "libresoc.v:113281.3-113291.6" + wire $1\cr_bitfield_b_ok[0:0] + attribute \src "libresoc.v:113341.3-113351.6" + wire width 3 $1\cr_bitfield_o[2:0] + attribute \src "libresoc.v:113352.3-113362.6" + wire $1\cr_bitfield_o_ok[0:0] + attribute \src "libresoc.v:113254.3-113280.6" + wire $1\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:113390.3-113408.6" + wire width 8 $1\cr_fxm[7:0] + attribute \src "libresoc.v:113292.3-113302.6" + wire $1\cr_fxm_ok[0:0] + attribute \src "libresoc.v:113363.3-113373.6" + wire $1\move_one[0:0] + attribute \src "libresoc.v:113374.3-113389.6" + wire width 8 $1\ppick_i[7:0] + attribute \src "libresoc.v:113390.3-113408.6" + wire width 8 $2\cr_fxm[7:0] + attribute \src "libresoc.v:113374.3-113389.6" + wire width 8 $2\ppick_i[7:0] + attribute \src "libresoc.v:113247.17-113247.112" + wire $and$libresoc.v:113247$4467_Y + attribute \src "libresoc.v:113249.17-113249.112" + wire $and$libresoc.v:113249$4469_Y + attribute \src "libresoc.v:113246.17-113246.121" + wire $eq$libresoc.v:113246$4466_Y + attribute \src "libresoc.v:113248.17-113248.121" + wire $eq$libresoc.v:113248$4468_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 4 \DIV_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 3 \DIV_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 8 \DIV_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 7 \DIV_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 5 \DIV_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 8 input 6 \DIV_FXM + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 input 2 \DIV_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 input 9 \X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \cr_bitfield + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \cr_bitfield_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_bitfield_b_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \cr_bitfield_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_bitfield_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_bitfield_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 8 \cr_fxm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_fxm_ok + attribute \src "libresoc.v:113113.7-113113.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486" + wire width 32 input 10 \insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:527" + wire \move_one + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 \ppick_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 \ppick_o + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:485" + wire width 3 input 1 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + cell $and $and$libresoc.v:113247$4467 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$1 + connect \B \move_one + connect \Y $and$libresoc.v:113247$4467_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + cell $and $and$libresoc.v:113249$4469 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$5 + connect \B \move_one + connect \Y $and$libresoc.v:113249$4469_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + cell $eq $eq$libresoc.v:113246$4466 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \DIV_internal_op + connect \B 7'0101101 + connect \Y $eq$libresoc.v:113246$4466_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + cell $eq $eq$libresoc.v:113248$4468 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \DIV_internal_op + connect \B 7'0101101 + connect \Y $eq$libresoc.v:113248$4468_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:113250.15-113253.4" + cell \ppick$172 \ppick + connect \i \ppick_i + connect \o \ppick_o + end + attribute \src "libresoc.v:113113.7-113113.20" + process $proc$libresoc.v:113113$4480 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:113254.3-113280.6" + process $proc$libresoc.v:113254$4470 + assign { } { } + assign { } { } + assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:113255.5-113255.29" + switch \initial + attribute \src "libresoc.v:113255.9-113255.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 3'101 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + case + assign $1\cr_bitfield_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] + end + attribute \src "libresoc.v:113281.3-113291.6" + process $proc$libresoc.v:113281$4471 + assign { } { } + assign { } { } + assign $0\cr_bitfield_b_ok[0:0] $1\cr_bitfield_b_ok[0:0] + attribute \src "libresoc.v:113282.5-113282.29" + switch \initial + attribute \src "libresoc.v:113282.9-113282.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_b_ok[0:0] 1'1 + case + assign $1\cr_bitfield_b_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_b_ok $0\cr_bitfield_b_ok[0:0] + end + attribute \src "libresoc.v:113292.3-113302.6" + process $proc$libresoc.v:113292$4472 + assign { } { } + assign { } { } + assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] + attribute \src "libresoc.v:113293.5-113293.29" + switch \initial + attribute \src "libresoc.v:113293.9-113293.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\cr_fxm_ok[0:0] 1'1 + case + assign $1\cr_fxm_ok[0:0] 1'0 + end + sync always + update \cr_fxm_ok $0\cr_fxm_ok[0:0] + end + attribute \src "libresoc.v:113303.3-113329.6" + process $proc$libresoc.v:113303$4473 + assign { } { } + assign { } { } + assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] + attribute \src "libresoc.v:113304.5-113304.29" + switch \initial + attribute \src "libresoc.v:113304.9-113304.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\cr_bitfield[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\cr_bitfield[2:0] \DIV_BI [4:2] + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield[2:0] \X_BFA + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield[2:0] \DIV_BA [4:2] + attribute \src "libresoc.v:0.0-0.0" + case 3'101 + assign { } { } + assign $1\cr_bitfield[2:0] \DIV_BC [4:2] + case + assign $1\cr_bitfield[2:0] 3'000 + end + sync always + update \cr_bitfield $0\cr_bitfield[2:0] + end + attribute \src "libresoc.v:113330.3-113340.6" + process $proc$libresoc.v:113330$4474 + assign { } { } + assign { } { } + assign $0\cr_bitfield_b[2:0] $1\cr_bitfield_b[2:0] + attribute \src "libresoc.v:113331.5-113331.29" + switch \initial + attribute \src "libresoc.v:113331.9-113331.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_b[2:0] \DIV_BB [4:2] + case + assign $1\cr_bitfield_b[2:0] 3'000 + end + sync always + update \cr_bitfield_b $0\cr_bitfield_b[2:0] + end + attribute \src "libresoc.v:113341.3-113351.6" + process $proc$libresoc.v:113341$4475 + assign { } { } + assign { } { } + assign $0\cr_bitfield_o[2:0] $1\cr_bitfield_o[2:0] + attribute \src "libresoc.v:113342.5-113342.29" + switch \initial + attribute \src "libresoc.v:113342.9-113342.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_o[2:0] \DIV_BT [4:2] + case + assign $1\cr_bitfield_o[2:0] 3'000 + end + sync always + update \cr_bitfield_o $0\cr_bitfield_o[2:0] + end + attribute \src "libresoc.v:113352.3-113362.6" + process $proc$libresoc.v:113352$4476 + assign { } { } + assign { } { } + assign $0\cr_bitfield_o_ok[0:0] $1\cr_bitfield_o_ok[0:0] + attribute \src "libresoc.v:113353.5-113353.29" + switch \initial + attribute \src "libresoc.v:113353.9-113353.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_o_ok[0:0] 1'1 + case + assign $1\cr_bitfield_o_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_o_ok $0\cr_bitfield_o_ok[0:0] + end + attribute \src "libresoc.v:113363.3-113373.6" + process $proc$libresoc.v:113363$4477 + assign { } { } + assign { } { } + assign $0\move_one[0:0] $1\move_one[0:0] + attribute \src "libresoc.v:113364.5-113364.29" + switch \initial + attribute \src "libresoc.v:113364.9-113364.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\move_one[0:0] \insn_in [20] + case + assign $1\move_one[0:0] 1'0 + end + sync always + update \move_one $0\move_one[0:0] + end + attribute \src "libresoc.v:113374.3-113389.6" + process $proc$libresoc.v:113374$4478 + assign { } { } + assign { } { } + assign $0\ppick_i[7:0] $1\ppick_i[7:0] + attribute \src "libresoc.v:113375.5-113375.29" + switch \initial + attribute \src "libresoc.v:113375.9-113375.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\ppick_i[7:0] $2\ppick_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ppick_i[7:0] \DIV_FXM + case + assign $2\ppick_i[7:0] 8'00000000 + end + case + assign $1\ppick_i[7:0] 8'00000000 + end + sync always + update \ppick_i $0\ppick_i[7:0] + end + attribute \src "libresoc.v:113390.3-113408.6" + process $proc$libresoc.v:113390$4479 + assign { } { } + assign { } { } + assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] + attribute \src "libresoc.v:113391.5-113391.29" + switch \initial + attribute \src "libresoc.v:113391.9-113391.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + switch \$7 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_fxm[7:0] \ppick_o + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cr_fxm[7:0] 8'11111111 + end + case + assign $1\cr_fxm[7:0] 8'00000000 + end + sync always + update \cr_fxm $0\cr_fxm[7:0] + end + connect \$1 $eq$libresoc.v:113246$4466_Y + connect \$3 $and$libresoc.v:113247$4467_Y + connect \$5 $eq$libresoc.v:113248$4468_Y + connect \$7 $and$libresoc.v:113249$4469_Y +end +attribute \src "libresoc.v:113413.1-113710.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_MUL.dec_cr_in" +attribute \generator "nMigen" +module \dec_cr_in$180 + attribute \src "libresoc.v:113604.3-113630.6" + wire width 3 $0\cr_bitfield[2:0] + attribute \src "libresoc.v:113631.3-113641.6" + wire width 3 $0\cr_bitfield_b[2:0] + attribute \src "libresoc.v:113582.3-113592.6" + wire $0\cr_bitfield_b_ok[0:0] + attribute \src "libresoc.v:113642.3-113652.6" + wire width 3 $0\cr_bitfield_o[2:0] + attribute \src "libresoc.v:113653.3-113663.6" + wire $0\cr_bitfield_o_ok[0:0] + attribute \src "libresoc.v:113555.3-113581.6" + wire $0\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:113691.3-113709.6" + wire width 8 $0\cr_fxm[7:0] + attribute \src "libresoc.v:113593.3-113603.6" + wire $0\cr_fxm_ok[0:0] + attribute \src "libresoc.v:113414.7-113414.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:113664.3-113674.6" + wire $0\move_one[0:0] + attribute \src "libresoc.v:113675.3-113690.6" + wire width 8 $0\ppick_i[7:0] + attribute \src "libresoc.v:113604.3-113630.6" + wire width 3 $1\cr_bitfield[2:0] + attribute \src "libresoc.v:113631.3-113641.6" + wire width 3 $1\cr_bitfield_b[2:0] + attribute \src "libresoc.v:113582.3-113592.6" + wire $1\cr_bitfield_b_ok[0:0] + attribute \src "libresoc.v:113642.3-113652.6" + wire width 3 $1\cr_bitfield_o[2:0] + attribute \src "libresoc.v:113653.3-113663.6" + wire $1\cr_bitfield_o_ok[0:0] + attribute \src "libresoc.v:113555.3-113581.6" + wire $1\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:113691.3-113709.6" + wire width 8 $1\cr_fxm[7:0] + attribute \src "libresoc.v:113593.3-113603.6" + wire $1\cr_fxm_ok[0:0] + attribute \src "libresoc.v:113664.3-113674.6" + wire $1\move_one[0:0] + attribute \src "libresoc.v:113675.3-113690.6" + wire width 8 $1\ppick_i[7:0] + attribute \src "libresoc.v:113691.3-113709.6" + wire width 8 $2\cr_fxm[7:0] + attribute \src "libresoc.v:113675.3-113690.6" + wire width 8 $2\ppick_i[7:0] + attribute \src "libresoc.v:113548.17-113548.112" + wire $and$libresoc.v:113548$4482_Y + attribute \src "libresoc.v:113550.17-113550.112" + wire $and$libresoc.v:113550$4484_Y + attribute \src "libresoc.v:113547.17-113547.121" + wire $eq$libresoc.v:113547$4481_Y + attribute \src "libresoc.v:113549.17-113549.121" + wire $eq$libresoc.v:113549$4483_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 4 \MUL_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 3 \MUL_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 8 \MUL_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 7 \MUL_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 5 \MUL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 8 input 6 \MUL_FXM + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 input 2 \MUL_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 input 9 \X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \cr_bitfield + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \cr_bitfield_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_bitfield_b_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \cr_bitfield_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_bitfield_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_bitfield_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 8 \cr_fxm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_fxm_ok + attribute \src "libresoc.v:113414.7-113414.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486" + wire width 32 input 10 \insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:527" + wire \move_one + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 \ppick_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 \ppick_o + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:485" + wire width 3 input 1 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + cell $and $and$libresoc.v:113548$4482 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$1 + connect \B \move_one + connect \Y $and$libresoc.v:113548$4482_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + cell $and $and$libresoc.v:113550$4484 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$5 + connect \B \move_one + connect \Y $and$libresoc.v:113550$4484_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + cell $eq $eq$libresoc.v:113547$4481 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \MUL_internal_op + connect \B 7'0101101 + connect \Y $eq$libresoc.v:113547$4481_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + cell $eq $eq$libresoc.v:113549$4483 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \MUL_internal_op + connect \B 7'0101101 + connect \Y $eq$libresoc.v:113549$4483_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:113551.15-113554.4" + cell \ppick$181 \ppick + connect \i \ppick_i + connect \o \ppick_o + end + attribute \src "libresoc.v:113414.7-113414.20" + process $proc$libresoc.v:113414$4495 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:113555.3-113581.6" + process $proc$libresoc.v:113555$4485 + assign { } { } + assign { } { } + assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:113556.5-113556.29" + switch \initial + attribute \src "libresoc.v:113556.9-113556.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 3'101 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + case + assign $1\cr_bitfield_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] + end + attribute \src "libresoc.v:113582.3-113592.6" + process $proc$libresoc.v:113582$4486 + assign { } { } + assign { } { } + assign $0\cr_bitfield_b_ok[0:0] $1\cr_bitfield_b_ok[0:0] + attribute \src "libresoc.v:113583.5-113583.29" + switch \initial + attribute \src "libresoc.v:113583.9-113583.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_b_ok[0:0] 1'1 + case + assign $1\cr_bitfield_b_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_b_ok $0\cr_bitfield_b_ok[0:0] + end + attribute \src "libresoc.v:113593.3-113603.6" + process $proc$libresoc.v:113593$4487 + assign { } { } + assign { } { } + assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] + attribute \src "libresoc.v:113594.5-113594.29" + switch \initial + attribute \src "libresoc.v:113594.9-113594.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\cr_fxm_ok[0:0] 1'1 + case + assign $1\cr_fxm_ok[0:0] 1'0 + end + sync always + update \cr_fxm_ok $0\cr_fxm_ok[0:0] + end + attribute \src "libresoc.v:113604.3-113630.6" + process $proc$libresoc.v:113604$4488 + assign { } { } + assign { } { } + assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] + attribute \src "libresoc.v:113605.5-113605.29" + switch \initial + attribute \src "libresoc.v:113605.9-113605.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\cr_bitfield[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\cr_bitfield[2:0] \MUL_BI [4:2] + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield[2:0] \X_BFA + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield[2:0] \MUL_BA [4:2] + attribute \src "libresoc.v:0.0-0.0" + case 3'101 + assign { } { } + assign $1\cr_bitfield[2:0] \MUL_BC [4:2] + case + assign $1\cr_bitfield[2:0] 3'000 + end + sync always + update \cr_bitfield $0\cr_bitfield[2:0] + end + attribute \src "libresoc.v:113631.3-113641.6" + process $proc$libresoc.v:113631$4489 + assign { } { } + assign { } { } + assign $0\cr_bitfield_b[2:0] $1\cr_bitfield_b[2:0] + attribute \src "libresoc.v:113632.5-113632.29" + switch \initial + attribute \src "libresoc.v:113632.9-113632.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_b[2:0] \MUL_BB [4:2] + case + assign $1\cr_bitfield_b[2:0] 3'000 + end + sync always + update \cr_bitfield_b $0\cr_bitfield_b[2:0] + end + attribute \src "libresoc.v:113642.3-113652.6" + process $proc$libresoc.v:113642$4490 + assign { } { } + assign { } { } + assign $0\cr_bitfield_o[2:0] $1\cr_bitfield_o[2:0] + attribute \src "libresoc.v:113643.5-113643.29" + switch \initial + attribute \src "libresoc.v:113643.9-113643.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_o[2:0] \MUL_BT [4:2] + case + assign $1\cr_bitfield_o[2:0] 3'000 + end + sync always + update \cr_bitfield_o $0\cr_bitfield_o[2:0] + end + attribute \src "libresoc.v:113653.3-113663.6" + process $proc$libresoc.v:113653$4491 + assign { } { } + assign { } { } + assign $0\cr_bitfield_o_ok[0:0] $1\cr_bitfield_o_ok[0:0] + attribute \src "libresoc.v:113654.5-113654.29" + switch \initial + attribute \src "libresoc.v:113654.9-113654.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_o_ok[0:0] 1'1 + case + assign $1\cr_bitfield_o_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_o_ok $0\cr_bitfield_o_ok[0:0] + end + attribute \src "libresoc.v:113664.3-113674.6" + process $proc$libresoc.v:113664$4492 + assign { } { } + assign { } { } + assign $0\move_one[0:0] $1\move_one[0:0] + attribute \src "libresoc.v:113665.5-113665.29" + switch \initial + attribute \src "libresoc.v:113665.9-113665.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\move_one[0:0] \insn_in [20] + case + assign $1\move_one[0:0] 1'0 + end + sync always + update \move_one $0\move_one[0:0] + end + attribute \src "libresoc.v:113675.3-113690.6" + process $proc$libresoc.v:113675$4493 + assign { } { } + assign { } { } + assign $0\ppick_i[7:0] $1\ppick_i[7:0] + attribute \src "libresoc.v:113676.5-113676.29" + switch \initial + attribute \src "libresoc.v:113676.9-113676.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\ppick_i[7:0] $2\ppick_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ppick_i[7:0] \MUL_FXM + case + assign $2\ppick_i[7:0] 8'00000000 + end + case + assign $1\ppick_i[7:0] 8'00000000 + end + sync always + update \ppick_i $0\ppick_i[7:0] + end + attribute \src "libresoc.v:113691.3-113709.6" + process $proc$libresoc.v:113691$4494 + assign { } { } + assign { } { } + assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] + attribute \src "libresoc.v:113692.5-113692.29" + switch \initial + attribute \src "libresoc.v:113692.9-113692.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + switch \$7 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_fxm[7:0] \ppick_o + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cr_fxm[7:0] 8'11111111 + end + case + assign $1\cr_fxm[7:0] 8'00000000 + end + sync always + update \cr_fxm $0\cr_fxm[7:0] + end + connect \$1 $eq$libresoc.v:113547$4481_Y + connect \$3 $and$libresoc.v:113548$4482_Y + connect \$5 $eq$libresoc.v:113549$4483_Y + connect \$7 $and$libresoc.v:113550$4484_Y +end +attribute \src "libresoc.v:113714.1-114011.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_SHIFT_ROT.dec_cr_in" +attribute \generator "nMigen" +module \dec_cr_in$188 + attribute \src "libresoc.v:113905.3-113931.6" + wire width 3 $0\cr_bitfield[2:0] + attribute \src "libresoc.v:113932.3-113942.6" + wire width 3 $0\cr_bitfield_b[2:0] + attribute \src "libresoc.v:113883.3-113893.6" + wire $0\cr_bitfield_b_ok[0:0] + attribute \src "libresoc.v:113943.3-113953.6" + wire width 3 $0\cr_bitfield_o[2:0] + attribute \src "libresoc.v:113954.3-113964.6" + wire $0\cr_bitfield_o_ok[0:0] + attribute \src "libresoc.v:113856.3-113882.6" + wire $0\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:113992.3-114010.6" + wire width 8 $0\cr_fxm[7:0] + attribute \src "libresoc.v:113894.3-113904.6" + wire $0\cr_fxm_ok[0:0] + attribute \src "libresoc.v:113715.7-113715.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:113965.3-113975.6" + wire $0\move_one[0:0] + attribute \src "libresoc.v:113976.3-113991.6" + wire width 8 $0\ppick_i[7:0] + attribute \src "libresoc.v:113905.3-113931.6" + wire width 3 $1\cr_bitfield[2:0] + attribute \src "libresoc.v:113932.3-113942.6" + wire width 3 $1\cr_bitfield_b[2:0] + attribute \src "libresoc.v:113883.3-113893.6" + wire $1\cr_bitfield_b_ok[0:0] + attribute \src "libresoc.v:113943.3-113953.6" + wire width 3 $1\cr_bitfield_o[2:0] + attribute \src "libresoc.v:113954.3-113964.6" + wire $1\cr_bitfield_o_ok[0:0] + attribute \src "libresoc.v:113856.3-113882.6" + wire $1\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:113992.3-114010.6" + wire width 8 $1\cr_fxm[7:0] + attribute \src "libresoc.v:113894.3-113904.6" + wire $1\cr_fxm_ok[0:0] + attribute \src "libresoc.v:113965.3-113975.6" + wire $1\move_one[0:0] + attribute \src "libresoc.v:113976.3-113991.6" + wire width 8 $1\ppick_i[7:0] + attribute \src "libresoc.v:113992.3-114010.6" + wire width 8 $2\cr_fxm[7:0] + attribute \src "libresoc.v:113976.3-113991.6" + wire width 8 $2\ppick_i[7:0] + attribute \src "libresoc.v:113849.17-113849.112" + wire $and$libresoc.v:113849$4497_Y + attribute \src "libresoc.v:113851.17-113851.112" + wire $and$libresoc.v:113851$4499_Y + attribute \src "libresoc.v:113848.17-113848.127" + wire $eq$libresoc.v:113848$4496_Y + attribute \src "libresoc.v:113850.17-113850.127" + wire $eq$libresoc.v:113850$4498_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 4 \SHIFT_ROT_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 3 \SHIFT_ROT_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 8 \SHIFT_ROT_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 7 \SHIFT_ROT_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 5 \SHIFT_ROT_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 8 input 6 \SHIFT_ROT_FXM + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 input 2 \SHIFT_ROT_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 input 9 \X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \cr_bitfield + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \cr_bitfield_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_bitfield_b_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \cr_bitfield_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_bitfield_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_bitfield_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 8 \cr_fxm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_fxm_ok + attribute \src "libresoc.v:113715.7-113715.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486" + wire width 32 input 10 \insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:527" + wire \move_one + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 \ppick_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 \ppick_o + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:485" + wire width 3 input 1 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + cell $and $and$libresoc.v:113849$4497 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$1 + connect \B \move_one + connect \Y $and$libresoc.v:113849$4497_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + cell $and $and$libresoc.v:113851$4499 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$5 + connect \B \move_one + connect \Y $and$libresoc.v:113851$4499_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + cell $eq $eq$libresoc.v:113848$4496 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \SHIFT_ROT_internal_op + connect \B 7'0101101 + connect \Y $eq$libresoc.v:113848$4496_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + cell $eq $eq$libresoc.v:113850$4498 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \SHIFT_ROT_internal_op + connect \B 7'0101101 + connect \Y $eq$libresoc.v:113850$4498_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:113852.15-113855.4" + cell \ppick$189 \ppick + connect \i \ppick_i + connect \o \ppick_o + end + attribute \src "libresoc.v:113715.7-113715.20" + process $proc$libresoc.v:113715$4510 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:113856.3-113882.6" + process $proc$libresoc.v:113856$4500 + assign { } { } + assign { } { } + assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:113857.5-113857.29" + switch \initial + attribute \src "libresoc.v:113857.9-113857.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 3'101 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + case + assign $1\cr_bitfield_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] + end + attribute \src "libresoc.v:113883.3-113893.6" + process $proc$libresoc.v:113883$4501 + assign { } { } + assign { } { } + assign $0\cr_bitfield_b_ok[0:0] $1\cr_bitfield_b_ok[0:0] + attribute \src "libresoc.v:113884.5-113884.29" + switch \initial + attribute \src "libresoc.v:113884.9-113884.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_b_ok[0:0] 1'1 + case + assign $1\cr_bitfield_b_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_b_ok $0\cr_bitfield_b_ok[0:0] + end + attribute \src "libresoc.v:113894.3-113904.6" + process $proc$libresoc.v:113894$4502 + assign { } { } + assign { } { } + assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] + attribute \src "libresoc.v:113895.5-113895.29" + switch \initial + attribute \src "libresoc.v:113895.9-113895.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\cr_fxm_ok[0:0] 1'1 + case + assign $1\cr_fxm_ok[0:0] 1'0 + end + sync always + update \cr_fxm_ok $0\cr_fxm_ok[0:0] + end + attribute \src "libresoc.v:113905.3-113931.6" + process $proc$libresoc.v:113905$4503 + assign { } { } + assign { } { } + assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] + attribute \src "libresoc.v:113906.5-113906.29" + switch \initial + attribute \src "libresoc.v:113906.9-113906.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\cr_bitfield[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\cr_bitfield[2:0] \SHIFT_ROT_BI [4:2] + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield[2:0] \X_BFA + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield[2:0] \SHIFT_ROT_BA [4:2] + attribute \src "libresoc.v:0.0-0.0" + case 3'101 + assign { } { } + assign $1\cr_bitfield[2:0] \SHIFT_ROT_BC [4:2] + case + assign $1\cr_bitfield[2:0] 3'000 + end + sync always + update \cr_bitfield $0\cr_bitfield[2:0] + end + attribute \src "libresoc.v:113932.3-113942.6" + process $proc$libresoc.v:113932$4504 + assign { } { } + assign { } { } + assign $0\cr_bitfield_b[2:0] $1\cr_bitfield_b[2:0] + attribute \src "libresoc.v:113933.5-113933.29" + switch \initial + attribute \src "libresoc.v:113933.9-113933.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_b[2:0] \SHIFT_ROT_BB [4:2] + case + assign $1\cr_bitfield_b[2:0] 3'000 + end + sync always + update \cr_bitfield_b $0\cr_bitfield_b[2:0] + end + attribute \src "libresoc.v:113943.3-113953.6" + process $proc$libresoc.v:113943$4505 + assign { } { } + assign { } { } + assign $0\cr_bitfield_o[2:0] $1\cr_bitfield_o[2:0] + attribute \src "libresoc.v:113944.5-113944.29" + switch \initial + attribute \src "libresoc.v:113944.9-113944.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_o[2:0] \SHIFT_ROT_BT [4:2] + case + assign $1\cr_bitfield_o[2:0] 3'000 + end + sync always + update \cr_bitfield_o $0\cr_bitfield_o[2:0] + end + attribute \src "libresoc.v:113954.3-113964.6" + process $proc$libresoc.v:113954$4506 + assign { } { } + assign { } { } + assign $0\cr_bitfield_o_ok[0:0] $1\cr_bitfield_o_ok[0:0] + attribute \src "libresoc.v:113955.5-113955.29" + switch \initial + attribute \src "libresoc.v:113955.9-113955.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_o_ok[0:0] 1'1 + case + assign $1\cr_bitfield_o_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_o_ok $0\cr_bitfield_o_ok[0:0] + end + attribute \src "libresoc.v:113965.3-113975.6" + process $proc$libresoc.v:113965$4507 + assign { } { } + assign { } { } + assign $0\move_one[0:0] $1\move_one[0:0] + attribute \src "libresoc.v:113966.5-113966.29" + switch \initial + attribute \src "libresoc.v:113966.9-113966.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\move_one[0:0] \insn_in [20] + case + assign $1\move_one[0:0] 1'0 + end + sync always + update \move_one $0\move_one[0:0] + end + attribute \src "libresoc.v:113976.3-113991.6" + process $proc$libresoc.v:113976$4508 + assign { } { } + assign { } { } + assign $0\ppick_i[7:0] $1\ppick_i[7:0] + attribute \src "libresoc.v:113977.5-113977.29" + switch \initial + attribute \src "libresoc.v:113977.9-113977.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\ppick_i[7:0] $2\ppick_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ppick_i[7:0] \SHIFT_ROT_FXM + case + assign $2\ppick_i[7:0] 8'00000000 + end + case + assign $1\ppick_i[7:0] 8'00000000 + end + sync always + update \ppick_i $0\ppick_i[7:0] + end + attribute \src "libresoc.v:113992.3-114010.6" + process $proc$libresoc.v:113992$4509 + assign { } { } + assign { } { } + assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] + attribute \src "libresoc.v:113993.5-113993.29" + switch \initial + attribute \src "libresoc.v:113993.9-113993.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + switch \$7 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_fxm[7:0] \ppick_o + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cr_fxm[7:0] 8'11111111 + end + case + assign $1\cr_fxm[7:0] 8'00000000 + end + sync always + update \cr_fxm $0\cr_fxm[7:0] + end + connect \$1 $eq$libresoc.v:113848$4496_Y + connect \$3 $and$libresoc.v:113849$4497_Y + connect \$5 $eq$libresoc.v:113850$4498_Y + connect \$7 $and$libresoc.v:113851$4499_Y +end +attribute \src "libresoc.v:114015.1-114312.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_LDST.dec_cr_in" +attribute \generator "nMigen" +module \dec_cr_in$196 + attribute \src "libresoc.v:114206.3-114232.6" + wire width 3 $0\cr_bitfield[2:0] + attribute \src "libresoc.v:114233.3-114243.6" + wire width 3 $0\cr_bitfield_b[2:0] + attribute \src "libresoc.v:114184.3-114194.6" + wire $0\cr_bitfield_b_ok[0:0] + attribute \src "libresoc.v:114244.3-114254.6" + wire width 3 $0\cr_bitfield_o[2:0] + attribute \src "libresoc.v:114255.3-114265.6" + wire $0\cr_bitfield_o_ok[0:0] + attribute \src "libresoc.v:114157.3-114183.6" + wire $0\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:114293.3-114311.6" + wire width 8 $0\cr_fxm[7:0] + attribute \src "libresoc.v:114195.3-114205.6" + wire $0\cr_fxm_ok[0:0] + attribute \src "libresoc.v:114016.7-114016.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:114266.3-114276.6" + wire $0\move_one[0:0] + attribute \src "libresoc.v:114277.3-114292.6" + wire width 8 $0\ppick_i[7:0] + attribute \src "libresoc.v:114206.3-114232.6" + wire width 3 $1\cr_bitfield[2:0] + attribute \src "libresoc.v:114233.3-114243.6" + wire width 3 $1\cr_bitfield_b[2:0] + attribute \src "libresoc.v:114184.3-114194.6" + wire $1\cr_bitfield_b_ok[0:0] + attribute \src "libresoc.v:114244.3-114254.6" + wire width 3 $1\cr_bitfield_o[2:0] + attribute \src "libresoc.v:114255.3-114265.6" + wire $1\cr_bitfield_o_ok[0:0] + attribute \src "libresoc.v:114157.3-114183.6" + wire $1\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:114293.3-114311.6" + wire width 8 $1\cr_fxm[7:0] + attribute \src "libresoc.v:114195.3-114205.6" + wire $1\cr_fxm_ok[0:0] + attribute \src "libresoc.v:114266.3-114276.6" + wire $1\move_one[0:0] + attribute \src "libresoc.v:114277.3-114292.6" + wire width 8 $1\ppick_i[7:0] + attribute \src "libresoc.v:114293.3-114311.6" + wire width 8 $2\cr_fxm[7:0] + attribute \src "libresoc.v:114277.3-114292.6" + wire width 8 $2\ppick_i[7:0] + attribute \src "libresoc.v:114150.17-114150.112" + wire $and$libresoc.v:114150$4512_Y + attribute \src "libresoc.v:114152.17-114152.112" + wire $and$libresoc.v:114152$4514_Y + attribute \src "libresoc.v:114149.17-114149.122" + wire $eq$libresoc.v:114149$4511_Y + attribute \src "libresoc.v:114151.17-114151.122" + wire $eq$libresoc.v:114151$4513_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 4 \LDST_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 3 \LDST_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 8 \LDST_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 7 \LDST_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 5 \LDST_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 8 input 6 \LDST_FXM + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 input 2 \LDST_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 input 9 \X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \cr_bitfield + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \cr_bitfield_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_bitfield_b_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \cr_bitfield_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_bitfield_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_bitfield_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 8 \cr_fxm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_fxm_ok + attribute \src "libresoc.v:114016.7-114016.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486" + wire width 32 input 10 \insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:527" + wire \move_one + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 \ppick_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 \ppick_o + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:485" + wire width 3 input 1 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + cell $and $and$libresoc.v:114150$4512 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$1 + connect \B \move_one + connect \Y $and$libresoc.v:114150$4512_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + cell $and $and$libresoc.v:114152$4514 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$5 + connect \B \move_one + connect \Y $and$libresoc.v:114152$4514_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + cell $eq $eq$libresoc.v:114149$4511 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \LDST_internal_op + connect \B 7'0101101 + connect \Y $eq$libresoc.v:114149$4511_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + cell $eq $eq$libresoc.v:114151$4513 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \LDST_internal_op + connect \B 7'0101101 + connect \Y $eq$libresoc.v:114151$4513_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:114153.15-114156.4" + cell \ppick$197 \ppick + connect \i \ppick_i + connect \o \ppick_o + end + attribute \src "libresoc.v:114016.7-114016.20" + process $proc$libresoc.v:114016$4525 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:114157.3-114183.6" + process $proc$libresoc.v:114157$4515 + assign { } { } + assign { } { } + assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:114158.5-114158.29" + switch \initial + attribute \src "libresoc.v:114158.9-114158.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 3'101 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + case + assign $1\cr_bitfield_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] + end + attribute \src "libresoc.v:114184.3-114194.6" + process $proc$libresoc.v:114184$4516 + assign { } { } + assign { } { } + assign $0\cr_bitfield_b_ok[0:0] $1\cr_bitfield_b_ok[0:0] + attribute \src "libresoc.v:114185.5-114185.29" + switch \initial + attribute \src "libresoc.v:114185.9-114185.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_b_ok[0:0] 1'1 + case + assign $1\cr_bitfield_b_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_b_ok $0\cr_bitfield_b_ok[0:0] + end + attribute \src "libresoc.v:114195.3-114205.6" + process $proc$libresoc.v:114195$4517 + assign { } { } + assign { } { } + assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] + attribute \src "libresoc.v:114196.5-114196.29" + switch \initial + attribute \src "libresoc.v:114196.9-114196.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\cr_fxm_ok[0:0] 1'1 + case + assign $1\cr_fxm_ok[0:0] 1'0 + end + sync always + update \cr_fxm_ok $0\cr_fxm_ok[0:0] + end + attribute \src "libresoc.v:114206.3-114232.6" + process $proc$libresoc.v:114206$4518 + assign { } { } + assign { } { } + assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] + attribute \src "libresoc.v:114207.5-114207.29" + switch \initial + attribute \src "libresoc.v:114207.9-114207.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\cr_bitfield[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\cr_bitfield[2:0] \LDST_BI [4:2] + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield[2:0] \X_BFA + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield[2:0] \LDST_BA [4:2] + attribute \src "libresoc.v:0.0-0.0" + case 3'101 + assign { } { } + assign $1\cr_bitfield[2:0] \LDST_BC [4:2] + case + assign $1\cr_bitfield[2:0] 3'000 + end + sync always + update \cr_bitfield $0\cr_bitfield[2:0] + end + attribute \src "libresoc.v:114233.3-114243.6" + process $proc$libresoc.v:114233$4519 + assign { } { } + assign { } { } + assign $0\cr_bitfield_b[2:0] $1\cr_bitfield_b[2:0] + attribute \src "libresoc.v:114234.5-114234.29" + switch \initial + attribute \src "libresoc.v:114234.9-114234.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_b[2:0] \LDST_BB [4:2] + case + assign $1\cr_bitfield_b[2:0] 3'000 + end + sync always + update \cr_bitfield_b $0\cr_bitfield_b[2:0] + end + attribute \src "libresoc.v:114244.3-114254.6" + process $proc$libresoc.v:114244$4520 + assign { } { } + assign { } { } + assign $0\cr_bitfield_o[2:0] $1\cr_bitfield_o[2:0] + attribute \src "libresoc.v:114245.5-114245.29" + switch \initial + attribute \src "libresoc.v:114245.9-114245.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_o[2:0] \LDST_BT [4:2] + case + assign $1\cr_bitfield_o[2:0] 3'000 + end + sync always + update \cr_bitfield_o $0\cr_bitfield_o[2:0] + end + attribute \src "libresoc.v:114255.3-114265.6" + process $proc$libresoc.v:114255$4521 + assign { } { } + assign { } { } + assign $0\cr_bitfield_o_ok[0:0] $1\cr_bitfield_o_ok[0:0] + attribute \src "libresoc.v:114256.5-114256.29" + switch \initial + attribute \src "libresoc.v:114256.9-114256.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_o_ok[0:0] 1'1 + case + assign $1\cr_bitfield_o_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_o_ok $0\cr_bitfield_o_ok[0:0] + end + attribute \src "libresoc.v:114266.3-114276.6" + process $proc$libresoc.v:114266$4522 + assign { } { } + assign { } { } + assign $0\move_one[0:0] $1\move_one[0:0] + attribute \src "libresoc.v:114267.5-114267.29" + switch \initial + attribute \src "libresoc.v:114267.9-114267.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\move_one[0:0] \insn_in [20] + case + assign $1\move_one[0:0] 1'0 + end + sync always + update \move_one $0\move_one[0:0] + end + attribute \src "libresoc.v:114277.3-114292.6" + process $proc$libresoc.v:114277$4523 + assign { } { } + assign { } { } + assign $0\ppick_i[7:0] $1\ppick_i[7:0] + attribute \src "libresoc.v:114278.5-114278.29" + switch \initial + attribute \src "libresoc.v:114278.9-114278.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\ppick_i[7:0] $2\ppick_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ppick_i[7:0] \LDST_FXM + case + assign $2\ppick_i[7:0] 8'00000000 + end + case + assign $1\ppick_i[7:0] 8'00000000 + end + sync always + update \ppick_i $0\ppick_i[7:0] + end + attribute \src "libresoc.v:114293.3-114311.6" + process $proc$libresoc.v:114293$4524 + assign { } { } + assign { } { } + assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] + attribute \src "libresoc.v:114294.5-114294.29" + switch \initial + attribute \src "libresoc.v:114294.9-114294.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + switch \$7 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_fxm[7:0] \ppick_o + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cr_fxm[7:0] 8'11111111 + end + case + assign $1\cr_fxm[7:0] 8'00000000 + end + sync always + update \cr_fxm $0\cr_fxm[7:0] + end + connect \$1 $eq$libresoc.v:114149$4511_Y + connect \$3 $and$libresoc.v:114150$4512_Y + connect \$5 $eq$libresoc.v:114151$4513_Y + connect \$7 $and$libresoc.v:114152$4514_Y +end +attribute \src "libresoc.v:114316.1-114621.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.dec2.dec_cr_in" +attribute \generator "nMigen" +module \dec_cr_in$205 + attribute \src "libresoc.v:114515.3-114541.6" + wire width 3 $0\cr_bitfield[2:0] + attribute \src "libresoc.v:114542.3-114552.6" + wire width 3 $0\cr_bitfield_b[2:0] + attribute \src "libresoc.v:114493.3-114503.6" + wire $0\cr_bitfield_b_ok[0:0] + attribute \src "libresoc.v:114553.3-114563.6" + wire width 3 $0\cr_bitfield_o[2:0] + attribute \src "libresoc.v:114564.3-114574.6" + wire $0\cr_bitfield_o_ok[0:0] + attribute \src "libresoc.v:114466.3-114492.6" + wire $0\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:114602.3-114620.6" + wire width 8 $0\cr_fxm[7:0] + attribute \src "libresoc.v:114504.3-114514.6" + wire $0\cr_fxm_ok[0:0] + attribute \src "libresoc.v:114317.7-114317.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:114575.3-114585.6" + wire $0\move_one[0:0] + attribute \src "libresoc.v:114586.3-114601.6" + wire width 8 $0\ppick_i[7:0] + attribute \src "libresoc.v:114515.3-114541.6" + wire width 3 $1\cr_bitfield[2:0] + attribute \src "libresoc.v:114542.3-114552.6" + wire width 3 $1\cr_bitfield_b[2:0] + attribute \src "libresoc.v:114493.3-114503.6" + wire $1\cr_bitfield_b_ok[0:0] + attribute \src "libresoc.v:114553.3-114563.6" + wire width 3 $1\cr_bitfield_o[2:0] + attribute \src "libresoc.v:114564.3-114574.6" + wire $1\cr_bitfield_o_ok[0:0] + attribute \src "libresoc.v:114466.3-114492.6" + wire $1\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:114602.3-114620.6" + wire width 8 $1\cr_fxm[7:0] + attribute \src "libresoc.v:114504.3-114514.6" + wire $1\cr_fxm_ok[0:0] + attribute \src "libresoc.v:114575.3-114585.6" + wire $1\move_one[0:0] + attribute \src "libresoc.v:114586.3-114601.6" + wire width 8 $1\ppick_i[7:0] + attribute \src "libresoc.v:114602.3-114620.6" + wire width 8 $2\cr_fxm[7:0] + attribute \src "libresoc.v:114586.3-114601.6" + wire width 8 $2\ppick_i[7:0] + attribute \src "libresoc.v:114459.17-114459.112" + wire $and$libresoc.v:114459$4527_Y + attribute \src "libresoc.v:114461.17-114461.112" + wire $and$libresoc.v:114461$4529_Y + attribute \src "libresoc.v:114458.17-114458.117" + wire $eq$libresoc.v:114458$4526_Y + attribute \src "libresoc.v:114460.17-114460.117" + wire $eq$libresoc.v:114460$4528_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 12 \BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 11 \BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 16 \BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 15 \BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 13 \BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 8 input 14 \FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 input 17 \X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 output 5 \cr_bitfield + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 output 7 \cr_bitfield_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 8 \cr_bitfield_b_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 output 9 \cr_bitfield_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 10 \cr_bitfield_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 6 \cr_bitfield_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 8 output 3 \cr_fxm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 4 \cr_fxm_ok + attribute \src "libresoc.v:114317.7-114317.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486" + wire width 32 input 18 \insn_in + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 input 2 \internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:527" + wire \move_one + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 \ppick_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 \ppick_o + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:485" + wire width 3 input 1 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + cell $and $and$libresoc.v:114459$4527 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$1 + connect \B \move_one + connect \Y $and$libresoc.v:114459$4527_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + cell $and $and$libresoc.v:114461$4529 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$5 + connect \B \move_one + connect \Y $and$libresoc.v:114461$4529_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + cell $eq $eq$libresoc.v:114458$4526 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \internal_op + connect \B 7'0101101 + connect \Y $eq$libresoc.v:114458$4526_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + cell $eq $eq$libresoc.v:114460$4528 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \internal_op + connect \B 7'0101101 + connect \Y $eq$libresoc.v:114460$4528_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:114462.15-114465.4" + cell \ppick$206 \ppick + connect \i \ppick_i + connect \o \ppick_o + end + attribute \src "libresoc.v:114317.7-114317.20" + process $proc$libresoc.v:114317$4540 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:114466.3-114492.6" + process $proc$libresoc.v:114466$4530 + assign { } { } + assign { } { } + assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:114467.5-114467.29" + switch \initial + attribute \src "libresoc.v:114467.9-114467.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 3'101 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + case + assign $1\cr_bitfield_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] + end + attribute \src "libresoc.v:114493.3-114503.6" + process $proc$libresoc.v:114493$4531 + assign { } { } + assign { } { } + assign $0\cr_bitfield_b_ok[0:0] $1\cr_bitfield_b_ok[0:0] + attribute \src "libresoc.v:114494.5-114494.29" + switch \initial + attribute \src "libresoc.v:114494.9-114494.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_b_ok[0:0] 1'1 + case + assign $1\cr_bitfield_b_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_b_ok $0\cr_bitfield_b_ok[0:0] + end + attribute \src "libresoc.v:114504.3-114514.6" + process $proc$libresoc.v:114504$4532 + assign { } { } + assign { } { } + assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] + attribute \src "libresoc.v:114505.5-114505.29" + switch \initial + attribute \src "libresoc.v:114505.9-114505.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\cr_fxm_ok[0:0] 1'1 + case + assign $1\cr_fxm_ok[0:0] 1'0 + end + sync always + update \cr_fxm_ok $0\cr_fxm_ok[0:0] + end + attribute \src "libresoc.v:114515.3-114541.6" + process $proc$libresoc.v:114515$4533 + assign { } { } + assign { } { } + assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] + attribute \src "libresoc.v:114516.5-114516.29" + switch \initial + attribute \src "libresoc.v:114516.9-114516.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\cr_bitfield[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\cr_bitfield[2:0] \BI [4:2] + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield[2:0] \X_BFA + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield[2:0] \BA [4:2] + attribute \src "libresoc.v:0.0-0.0" + case 3'101 + assign { } { } + assign $1\cr_bitfield[2:0] \BC [4:2] + case + assign $1\cr_bitfield[2:0] 3'000 + end + sync always + update \cr_bitfield $0\cr_bitfield[2:0] + end + attribute \src "libresoc.v:114542.3-114552.6" + process $proc$libresoc.v:114542$4534 + assign { } { } + assign { } { } + assign $0\cr_bitfield_b[2:0] $1\cr_bitfield_b[2:0] + attribute \src "libresoc.v:114543.5-114543.29" + switch \initial + attribute \src "libresoc.v:114543.9-114543.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_b[2:0] \BB [4:2] + case + assign $1\cr_bitfield_b[2:0] 3'000 + end + sync always + update \cr_bitfield_b $0\cr_bitfield_b[2:0] + end + attribute \src "libresoc.v:114553.3-114563.6" + process $proc$libresoc.v:114553$4535 + assign { } { } + assign { } { } + assign $0\cr_bitfield_o[2:0] $1\cr_bitfield_o[2:0] + attribute \src "libresoc.v:114554.5-114554.29" + switch \initial + attribute \src "libresoc.v:114554.9-114554.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_o[2:0] \BT [4:2] + case + assign $1\cr_bitfield_o[2:0] 3'000 + end + sync always + update \cr_bitfield_o $0\cr_bitfield_o[2:0] + end + attribute \src "libresoc.v:114564.3-114574.6" + process $proc$libresoc.v:114564$4536 + assign { } { } + assign { } { } + assign $0\cr_bitfield_o_ok[0:0] $1\cr_bitfield_o_ok[0:0] + attribute \src "libresoc.v:114565.5-114565.29" + switch \initial + attribute \src "libresoc.v:114565.9-114565.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_o_ok[0:0] 1'1 + case + assign $1\cr_bitfield_o_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_o_ok $0\cr_bitfield_o_ok[0:0] + end + attribute \src "libresoc.v:114575.3-114585.6" + process $proc$libresoc.v:114575$4537 + assign { } { } + assign { } { } + assign $0\move_one[0:0] $1\move_one[0:0] + attribute \src "libresoc.v:114576.5-114576.29" + switch \initial + attribute \src "libresoc.v:114576.9-114576.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\move_one[0:0] \insn_in [20] + case + assign $1\move_one[0:0] 1'0 + end + sync always + update \move_one $0\move_one[0:0] + end + attribute \src "libresoc.v:114586.3-114601.6" + process $proc$libresoc.v:114586$4538 + assign { } { } + assign { } { } + assign $0\ppick_i[7:0] $1\ppick_i[7:0] + attribute \src "libresoc.v:114587.5-114587.29" + switch \initial + attribute \src "libresoc.v:114587.9-114587.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\ppick_i[7:0] $2\ppick_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ppick_i[7:0] \FXM + case + assign $2\ppick_i[7:0] 8'00000000 + end + case + assign $1\ppick_i[7:0] 8'00000000 + end + sync always + update \ppick_i $0\ppick_i[7:0] + end + attribute \src "libresoc.v:114602.3-114620.6" + process $proc$libresoc.v:114602$4539 + assign { } { } + assign { } { } + assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] + attribute \src "libresoc.v:114603.5-114603.29" + switch \initial + attribute \src "libresoc.v:114603.9-114603.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + switch \$7 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_fxm[7:0] \ppick_o + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cr_fxm[7:0] 8'11111111 + end + case + assign $1\cr_fxm[7:0] 8'00000000 + end + sync always + update \cr_fxm $0\cr_fxm[7:0] + end + connect \$1 $eq$libresoc.v:114458$4526_Y + connect \$3 $and$libresoc.v:114459$4527_Y + connect \$5 $eq$libresoc.v:114460$4528_Y + connect \$7 $and$libresoc.v:114461$4529_Y +end +attribute \src "libresoc.v:114625.1-114865.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_ALU.dec_cr_out" +attribute \generator "nMigen" +module \dec_cr_out + attribute \src "libresoc.v:114779.3-114797.6" + wire width 3 $0\cr_bitfield[2:0] + attribute \src "libresoc.v:114749.3-114767.6" + wire $0\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:114830.3-114864.6" + wire width 8 $0\cr_fxm[7:0] + attribute \src "libresoc.v:114768.3-114778.6" + wire $0\cr_fxm_ok[0:0] + attribute \src "libresoc.v:114626.7-114626.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:114798.3-114808.6" + wire $0\move_one[0:0] + attribute \src "libresoc.v:114809.3-114829.6" + wire width 8 $0\ppick_i[7:0] + attribute \src "libresoc.v:114779.3-114797.6" + wire width 3 $1\cr_bitfield[2:0] + attribute \src "libresoc.v:114749.3-114767.6" + wire $1\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:114830.3-114864.6" + wire width 8 $1\cr_fxm[7:0] + attribute \src "libresoc.v:114768.3-114778.6" + wire $1\cr_fxm_ok[0:0] + attribute \src "libresoc.v:114798.3-114808.6" + wire $1\move_one[0:0] + attribute \src "libresoc.v:114809.3-114829.6" + wire width 8 $1\ppick_i[7:0] + attribute \src "libresoc.v:114830.3-114864.6" + wire width 8 $2\cr_fxm[7:0] + attribute \src "libresoc.v:114809.3-114829.6" + wire width 8 $2\ppick_i[7:0] + attribute \src "libresoc.v:114830.3-114864.6" + wire width 8 $3\cr_fxm[7:0] + attribute \src "libresoc.v:114809.3-114829.6" + wire width 8 $3\ppick_i[7:0] + attribute \src "libresoc.v:114830.3-114864.6" + wire width 8 $4\cr_fxm[7:0] + attribute \src "libresoc.v:114742.17-114742.121" + wire $eq$libresoc.v:114742$4541_Y + attribute \src "libresoc.v:114743.17-114743.121" + wire $eq$libresoc.v:114743$4542_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 8 input 5 \ALU_FXM + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 input 3 \ALU_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 input 7 \XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 input 6 \X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \cr_bitfield + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 4 \cr_bitfield_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 8 \cr_fxm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_fxm_ok + attribute \src "libresoc.v:114626.7-114626.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:551" + wire width 32 input 8 \insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:578" + wire \move_one + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire \ppick_en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 \ppick_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 \ppick_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:549" + wire input 2 \rc_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:550" + wire width 3 input 1 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + cell $eq $eq$libresoc.v:114742$4541 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \ALU_internal_op + connect \B 7'0110000 + connect \Y $eq$libresoc.v:114742$4541_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + cell $eq $eq$libresoc.v:114743$4542 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \ALU_internal_op + connect \B 7'0110000 + connect \Y $eq$libresoc.v:114743$4542_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:114744.15-114748.4" + cell \ppick$136 \ppick + connect \en_o \ppick_en_o + connect \i \ppick_i + connect \o \ppick_o + end + attribute \src "libresoc.v:114626.7-114626.20" + process $proc$libresoc.v:114626$4549 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:114749.3-114767.6" + process $proc$libresoc.v:114749$4543 + assign { } { } + assign { } { } + assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:114750.5-114750.29" + switch \initial + attribute \src "libresoc.v:114750.9-114750.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\cr_bitfield_ok[0:0] \rc_in + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + case + assign $1\cr_bitfield_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] + end + attribute \src "libresoc.v:114768.3-114778.6" + process $proc$libresoc.v:114768$4544 + assign { } { } + assign { } { } + assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] + attribute \src "libresoc.v:114769.5-114769.29" + switch \initial + attribute \src "libresoc.v:114769.9-114769.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_fxm_ok[0:0] 1'1 + case + assign $1\cr_fxm_ok[0:0] 1'0 + end + sync always + update \cr_fxm_ok $0\cr_fxm_ok[0:0] + end + attribute \src "libresoc.v:114779.3-114797.6" + process $proc$libresoc.v:114779$4545 + assign { } { } + assign { } { } + assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] + attribute \src "libresoc.v:114780.5-114780.29" + switch \initial + attribute \src "libresoc.v:114780.9-114780.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\cr_bitfield[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\cr_bitfield[2:0] \X_BF + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield[2:0] \XL_BT [4:2] + case + assign $1\cr_bitfield[2:0] 3'000 + end + sync always + update \cr_bitfield $0\cr_bitfield[2:0] + end + attribute \src "libresoc.v:114798.3-114808.6" + process $proc$libresoc.v:114798$4546 + assign { } { } + assign { } { } + assign $0\move_one[0:0] $1\move_one[0:0] + attribute \src "libresoc.v:114799.5-114799.29" + switch \initial + attribute \src "libresoc.v:114799.9-114799.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\move_one[0:0] \insn_in [20] + case + assign $1\move_one[0:0] 1'0 + end + sync always + update \move_one $0\move_one[0:0] + end + attribute \src "libresoc.v:114809.3-114829.6" + process $proc$libresoc.v:114809$4547 + assign { } { } + assign { } { } + assign $0\ppick_i[7:0] $1\ppick_i[7:0] + attribute \src "libresoc.v:114810.5-114810.29" + switch \initial + attribute \src "libresoc.v:114810.9-114810.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\ppick_i[7:0] $2\ppick_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ppick_i[7:0] $3\ppick_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:581" + switch \move_one + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\ppick_i[7:0] \ALU_FXM + case + assign $3\ppick_i[7:0] 8'00000000 + end + case + assign $2\ppick_i[7:0] 8'00000000 + end + case + assign $1\ppick_i[7:0] 8'00000000 + end + sync always + update \ppick_i $0\ppick_i[7:0] + end + attribute \src "libresoc.v:114830.3-114864.6" + process $proc$libresoc.v:114830$4548 + assign { } { } + assign { } { } + assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] + attribute \src "libresoc.v:114831.5-114831.29" + switch \initial + attribute \src "libresoc.v:114831.9-114831.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_fxm[7:0] $3\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:581" + switch \move_one + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\cr_fxm[7:0] $4\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:584" + switch \ppick_en_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\cr_fxm[7:0] \ppick_o + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $4\cr_fxm[7:0] 8'00000001 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $3\cr_fxm[7:0] \ALU_FXM + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cr_fxm[7:0] 8'11111111 + end + case + assign $1\cr_fxm[7:0] 8'00000000 + end + sync always + update \cr_fxm $0\cr_fxm[7:0] + end + connect \$1 $eq$libresoc.v:114742$4541_Y + connect \$3 $eq$libresoc.v:114743$4542_Y +end +attribute \src "libresoc.v:114869.1-115108.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_CR.dec_cr_out" +attribute \generator "nMigen" +module \dec_cr_out$142 + attribute \src "libresoc.v:115022.3-115040.6" + wire width 3 $0\cr_bitfield[2:0] + attribute \src "libresoc.v:114992.3-115010.6" + wire $0\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:115073.3-115107.6" + wire width 8 $0\cr_fxm[7:0] + attribute \src "libresoc.v:115011.3-115021.6" + wire $0\cr_fxm_ok[0:0] + attribute \src "libresoc.v:114870.7-114870.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:115041.3-115051.6" + wire $0\move_one[0:0] + attribute \src "libresoc.v:115052.3-115072.6" + wire width 8 $0\ppick_i[7:0] + attribute \src "libresoc.v:115022.3-115040.6" + wire width 3 $1\cr_bitfield[2:0] + attribute \src "libresoc.v:114992.3-115010.6" + wire $1\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:115073.3-115107.6" + wire width 8 $1\cr_fxm[7:0] + attribute \src "libresoc.v:115011.3-115021.6" + wire $1\cr_fxm_ok[0:0] + attribute \src "libresoc.v:115041.3-115051.6" + wire $1\move_one[0:0] + attribute \src "libresoc.v:115052.3-115072.6" + wire width 8 $1\ppick_i[7:0] + attribute \src "libresoc.v:115073.3-115107.6" + wire width 8 $2\cr_fxm[7:0] + attribute \src "libresoc.v:115052.3-115072.6" + wire width 8 $2\ppick_i[7:0] + attribute \src "libresoc.v:115073.3-115107.6" + wire width 8 $3\cr_fxm[7:0] + attribute \src "libresoc.v:115052.3-115072.6" + wire width 8 $3\ppick_i[7:0] + attribute \src "libresoc.v:115073.3-115107.6" + wire width 8 $4\cr_fxm[7:0] + attribute \src "libresoc.v:114985.17-114985.120" + wire $eq$libresoc.v:114985$4550_Y + attribute \src "libresoc.v:114986.17-114986.120" + wire $eq$libresoc.v:114986$4551_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 8 input 4 \CR_FXM + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 input 3 \CR_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 input 6 \XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 input 5 \X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \cr_bitfield + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_bitfield_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 8 \cr_fxm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_fxm_ok + attribute \src "libresoc.v:114870.7-114870.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:551" + wire width 32 input 7 \insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:578" + wire \move_one + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire \ppick_en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 \ppick_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 \ppick_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:549" + wire input 2 \rc_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:550" + wire width 3 input 1 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + cell $eq $eq$libresoc.v:114985$4550 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \CR_internal_op + connect \B 7'0110000 + connect \Y $eq$libresoc.v:114985$4550_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + cell $eq $eq$libresoc.v:114986$4551 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \CR_internal_op + connect \B 7'0110000 + connect \Y $eq$libresoc.v:114986$4551_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:114987.15-114991.4" + cell \ppick$143 \ppick + connect \en_o \ppick_en_o + connect \i \ppick_i + connect \o \ppick_o + end + attribute \src "libresoc.v:114870.7-114870.20" + process $proc$libresoc.v:114870$4558 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:114992.3-115010.6" + process $proc$libresoc.v:114992$4552 + assign { } { } + assign { } { } + assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:114993.5-114993.29" + switch \initial + attribute \src "libresoc.v:114993.9-114993.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\cr_bitfield_ok[0:0] \rc_in + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + case + assign $1\cr_bitfield_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] + end + attribute \src "libresoc.v:115011.3-115021.6" + process $proc$libresoc.v:115011$4553 + assign { } { } + assign { } { } + assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] + attribute \src "libresoc.v:115012.5-115012.29" + switch \initial + attribute \src "libresoc.v:115012.9-115012.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_fxm_ok[0:0] 1'1 + case + assign $1\cr_fxm_ok[0:0] 1'0 + end + sync always + update \cr_fxm_ok $0\cr_fxm_ok[0:0] + end + attribute \src "libresoc.v:115022.3-115040.6" + process $proc$libresoc.v:115022$4554 + assign { } { } + assign { } { } + assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] + attribute \src "libresoc.v:115023.5-115023.29" + switch \initial + attribute \src "libresoc.v:115023.9-115023.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\cr_bitfield[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\cr_bitfield[2:0] \X_BF + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield[2:0] \XL_BT [4:2] + case + assign $1\cr_bitfield[2:0] 3'000 + end + sync always + update \cr_bitfield $0\cr_bitfield[2:0] + end + attribute \src "libresoc.v:115041.3-115051.6" + process $proc$libresoc.v:115041$4555 + assign { } { } + assign { } { } + assign $0\move_one[0:0] $1\move_one[0:0] + attribute \src "libresoc.v:115042.5-115042.29" + switch \initial + attribute \src "libresoc.v:115042.9-115042.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\move_one[0:0] \insn_in [20] + case + assign $1\move_one[0:0] 1'0 + end + sync always + update \move_one $0\move_one[0:0] + end + attribute \src "libresoc.v:115052.3-115072.6" + process $proc$libresoc.v:115052$4556 + assign { } { } + assign { } { } + assign $0\ppick_i[7:0] $1\ppick_i[7:0] + attribute \src "libresoc.v:115053.5-115053.29" + switch \initial + attribute \src "libresoc.v:115053.9-115053.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\ppick_i[7:0] $2\ppick_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ppick_i[7:0] $3\ppick_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:581" + switch \move_one + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\ppick_i[7:0] \CR_FXM + case + assign $3\ppick_i[7:0] 8'00000000 + end + case + assign $2\ppick_i[7:0] 8'00000000 + end + case + assign $1\ppick_i[7:0] 8'00000000 + end + sync always + update \ppick_i $0\ppick_i[7:0] + end + attribute \src "libresoc.v:115073.3-115107.6" + process $proc$libresoc.v:115073$4557 + assign { } { } + assign { } { } + assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] + attribute \src "libresoc.v:115074.5-115074.29" + switch \initial + attribute \src "libresoc.v:115074.9-115074.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_fxm[7:0] $3\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:581" + switch \move_one + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\cr_fxm[7:0] $4\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:584" + switch \ppick_en_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\cr_fxm[7:0] \ppick_o + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $4\cr_fxm[7:0] 8'00000001 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $3\cr_fxm[7:0] \CR_FXM + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cr_fxm[7:0] 8'11111111 + end + case + assign $1\cr_fxm[7:0] 8'00000000 + end + sync always + update \cr_fxm $0\cr_fxm[7:0] + end + connect \$1 $eq$libresoc.v:114985$4550_Y + connect \$3 $eq$libresoc.v:114986$4551_Y +end +attribute \src "libresoc.v:115112.1-115351.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_BRANCH.dec_cr_out" +attribute \generator "nMigen" +module \dec_cr_out$149 + attribute \src "libresoc.v:115265.3-115283.6" + wire width 3 $0\cr_bitfield[2:0] + attribute \src "libresoc.v:115235.3-115253.6" + wire $0\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:115316.3-115350.6" + wire width 8 $0\cr_fxm[7:0] + attribute \src "libresoc.v:115254.3-115264.6" + wire $0\cr_fxm_ok[0:0] + attribute \src "libresoc.v:115113.7-115113.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:115284.3-115294.6" + wire $0\move_one[0:0] + attribute \src "libresoc.v:115295.3-115315.6" + wire width 8 $0\ppick_i[7:0] + attribute \src "libresoc.v:115265.3-115283.6" + wire width 3 $1\cr_bitfield[2:0] + attribute \src "libresoc.v:115235.3-115253.6" + wire $1\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:115316.3-115350.6" + wire width 8 $1\cr_fxm[7:0] + attribute \src "libresoc.v:115254.3-115264.6" + wire $1\cr_fxm_ok[0:0] + attribute \src "libresoc.v:115284.3-115294.6" + wire $1\move_one[0:0] + attribute \src "libresoc.v:115295.3-115315.6" + wire width 8 $1\ppick_i[7:0] + attribute \src "libresoc.v:115316.3-115350.6" + wire width 8 $2\cr_fxm[7:0] + attribute \src "libresoc.v:115295.3-115315.6" + wire width 8 $2\ppick_i[7:0] + attribute \src "libresoc.v:115316.3-115350.6" + wire width 8 $3\cr_fxm[7:0] + attribute \src "libresoc.v:115295.3-115315.6" + wire width 8 $3\ppick_i[7:0] + attribute \src "libresoc.v:115316.3-115350.6" + wire width 8 $4\cr_fxm[7:0] + attribute \src "libresoc.v:115228.17-115228.124" + wire $eq$libresoc.v:115228$4559_Y + attribute \src "libresoc.v:115229.17-115229.124" + wire $eq$libresoc.v:115229$4560_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 8 input 4 \BRANCH_FXM + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 input 3 \BRANCH_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 input 6 \XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 input 5 \X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \cr_bitfield + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_bitfield_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 8 \cr_fxm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_fxm_ok + attribute \src "libresoc.v:115113.7-115113.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:551" + wire width 32 input 7 \insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:578" + wire \move_one + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire \ppick_en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 \ppick_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 \ppick_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:549" + wire input 2 \rc_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:550" + wire width 3 input 1 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + cell $eq $eq$libresoc.v:115228$4559 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \BRANCH_internal_op + connect \B 7'0110000 + connect \Y $eq$libresoc.v:115228$4559_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + cell $eq $eq$libresoc.v:115229$4560 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \BRANCH_internal_op + connect \B 7'0110000 + connect \Y $eq$libresoc.v:115229$4560_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:115230.15-115234.4" + cell \ppick$150 \ppick + connect \en_o \ppick_en_o + connect \i \ppick_i + connect \o \ppick_o + end + attribute \src "libresoc.v:115113.7-115113.20" + process $proc$libresoc.v:115113$4567 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:115235.3-115253.6" + process $proc$libresoc.v:115235$4561 + assign { } { } + assign { } { } + assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:115236.5-115236.29" + switch \initial + attribute \src "libresoc.v:115236.9-115236.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\cr_bitfield_ok[0:0] \rc_in + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + case + assign $1\cr_bitfield_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] + end + attribute \src "libresoc.v:115254.3-115264.6" + process $proc$libresoc.v:115254$4562 + assign { } { } + assign { } { } + assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] + attribute \src "libresoc.v:115255.5-115255.29" + switch \initial + attribute \src "libresoc.v:115255.9-115255.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_fxm_ok[0:0] 1'1 + case + assign $1\cr_fxm_ok[0:0] 1'0 + end + sync always + update \cr_fxm_ok $0\cr_fxm_ok[0:0] + end + attribute \src "libresoc.v:115265.3-115283.6" + process $proc$libresoc.v:115265$4563 + assign { } { } + assign { } { } + assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] + attribute \src "libresoc.v:115266.5-115266.29" + switch \initial + attribute \src "libresoc.v:115266.9-115266.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\cr_bitfield[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\cr_bitfield[2:0] \X_BF + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield[2:0] \XL_BT [4:2] + case + assign $1\cr_bitfield[2:0] 3'000 + end + sync always + update \cr_bitfield $0\cr_bitfield[2:0] + end + attribute \src "libresoc.v:115284.3-115294.6" + process $proc$libresoc.v:115284$4564 + assign { } { } + assign { } { } + assign $0\move_one[0:0] $1\move_one[0:0] + attribute \src "libresoc.v:115285.5-115285.29" + switch \initial + attribute \src "libresoc.v:115285.9-115285.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\move_one[0:0] \insn_in [20] + case + assign $1\move_one[0:0] 1'0 + end + sync always + update \move_one $0\move_one[0:0] + end + attribute \src "libresoc.v:115295.3-115315.6" + process $proc$libresoc.v:115295$4565 + assign { } { } + assign { } { } + assign $0\ppick_i[7:0] $1\ppick_i[7:0] + attribute \src "libresoc.v:115296.5-115296.29" + switch \initial + attribute \src "libresoc.v:115296.9-115296.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\ppick_i[7:0] $2\ppick_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ppick_i[7:0] $3\ppick_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:581" + switch \move_one + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\ppick_i[7:0] \BRANCH_FXM + case + assign $3\ppick_i[7:0] 8'00000000 + end + case + assign $2\ppick_i[7:0] 8'00000000 + end + case + assign $1\ppick_i[7:0] 8'00000000 + end + sync always + update \ppick_i $0\ppick_i[7:0] + end + attribute \src "libresoc.v:115316.3-115350.6" + process $proc$libresoc.v:115316$4566 + assign { } { } + assign { } { } + assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] + attribute \src "libresoc.v:115317.5-115317.29" + switch \initial + attribute \src "libresoc.v:115317.9-115317.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_fxm[7:0] $3\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:581" + switch \move_one + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\cr_fxm[7:0] $4\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:584" + switch \ppick_en_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\cr_fxm[7:0] \ppick_o + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $4\cr_fxm[7:0] 8'00000001 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $3\cr_fxm[7:0] \BRANCH_FXM + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cr_fxm[7:0] 8'11111111 + end + case + assign $1\cr_fxm[7:0] 8'00000000 + end + sync always + update \cr_fxm $0\cr_fxm[7:0] + end + connect \$1 $eq$libresoc.v:115228$4559_Y + connect \$3 $eq$libresoc.v:115229$4560_Y +end +attribute \src "libresoc.v:115355.1-115595.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_LOGICAL.dec_cr_out" +attribute \generator "nMigen" +module \dec_cr_out$157 + attribute \src "libresoc.v:115509.3-115527.6" + wire width 3 $0\cr_bitfield[2:0] + attribute \src "libresoc.v:115479.3-115497.6" + wire $0\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:115560.3-115594.6" + wire width 8 $0\cr_fxm[7:0] + attribute \src "libresoc.v:115498.3-115508.6" + wire $0\cr_fxm_ok[0:0] + attribute \src "libresoc.v:115356.7-115356.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:115528.3-115538.6" + wire $0\move_one[0:0] + attribute \src "libresoc.v:115539.3-115559.6" + wire width 8 $0\ppick_i[7:0] + attribute \src "libresoc.v:115509.3-115527.6" + wire width 3 $1\cr_bitfield[2:0] + attribute \src "libresoc.v:115479.3-115497.6" + wire $1\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:115560.3-115594.6" + wire width 8 $1\cr_fxm[7:0] + attribute \src "libresoc.v:115498.3-115508.6" + wire $1\cr_fxm_ok[0:0] + attribute \src "libresoc.v:115528.3-115538.6" + wire $1\move_one[0:0] + attribute \src "libresoc.v:115539.3-115559.6" + wire width 8 $1\ppick_i[7:0] + attribute \src "libresoc.v:115560.3-115594.6" + wire width 8 $2\cr_fxm[7:0] + attribute \src "libresoc.v:115539.3-115559.6" + wire width 8 $2\ppick_i[7:0] + attribute \src "libresoc.v:115560.3-115594.6" + wire width 8 $3\cr_fxm[7:0] + attribute \src "libresoc.v:115539.3-115559.6" + wire width 8 $3\ppick_i[7:0] + attribute \src "libresoc.v:115560.3-115594.6" + wire width 8 $4\cr_fxm[7:0] + attribute \src "libresoc.v:115472.17-115472.125" + wire $eq$libresoc.v:115472$4568_Y + attribute \src "libresoc.v:115473.17-115473.125" + wire $eq$libresoc.v:115473$4569_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 8 input 5 \LOGICAL_FXM + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 input 3 \LOGICAL_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 input 7 \XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 input 6 \X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \cr_bitfield + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 4 \cr_bitfield_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 8 \cr_fxm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_fxm_ok + attribute \src "libresoc.v:115356.7-115356.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:551" + wire width 32 input 8 \insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:578" + wire \move_one + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire \ppick_en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 \ppick_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 \ppick_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:549" + wire input 2 \rc_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:550" + wire width 3 input 1 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + cell $eq $eq$libresoc.v:115472$4568 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \LOGICAL_internal_op + connect \B 7'0110000 + connect \Y $eq$libresoc.v:115472$4568_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + cell $eq $eq$libresoc.v:115473$4569 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \LOGICAL_internal_op + connect \B 7'0110000 + connect \Y $eq$libresoc.v:115473$4569_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:115474.15-115478.4" + cell \ppick$158 \ppick + connect \en_o \ppick_en_o + connect \i \ppick_i + connect \o \ppick_o + end + attribute \src "libresoc.v:115356.7-115356.20" + process $proc$libresoc.v:115356$4576 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:115479.3-115497.6" + process $proc$libresoc.v:115479$4570 + assign { } { } + assign { } { } + assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:115480.5-115480.29" + switch \initial + attribute \src "libresoc.v:115480.9-115480.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\cr_bitfield_ok[0:0] \rc_in + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + case + assign $1\cr_bitfield_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] + end + attribute \src "libresoc.v:115498.3-115508.6" + process $proc$libresoc.v:115498$4571 + assign { } { } + assign { } { } + assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] + attribute \src "libresoc.v:115499.5-115499.29" + switch \initial + attribute \src "libresoc.v:115499.9-115499.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_fxm_ok[0:0] 1'1 + case + assign $1\cr_fxm_ok[0:0] 1'0 + end + sync always + update \cr_fxm_ok $0\cr_fxm_ok[0:0] + end + attribute \src "libresoc.v:115509.3-115527.6" + process $proc$libresoc.v:115509$4572 + assign { } { } + assign { } { } + assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] + attribute \src "libresoc.v:115510.5-115510.29" + switch \initial + attribute \src "libresoc.v:115510.9-115510.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\cr_bitfield[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\cr_bitfield[2:0] \X_BF + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield[2:0] \XL_BT [4:2] + case + assign $1\cr_bitfield[2:0] 3'000 + end + sync always + update \cr_bitfield $0\cr_bitfield[2:0] + end + attribute \src "libresoc.v:115528.3-115538.6" + process $proc$libresoc.v:115528$4573 + assign { } { } + assign { } { } + assign $0\move_one[0:0] $1\move_one[0:0] + attribute \src "libresoc.v:115529.5-115529.29" + switch \initial + attribute \src "libresoc.v:115529.9-115529.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\move_one[0:0] \insn_in [20] + case + assign $1\move_one[0:0] 1'0 + end + sync always + update \move_one $0\move_one[0:0] + end + attribute \src "libresoc.v:115539.3-115559.6" + process $proc$libresoc.v:115539$4574 + assign { } { } + assign { } { } + assign $0\ppick_i[7:0] $1\ppick_i[7:0] + attribute \src "libresoc.v:115540.5-115540.29" + switch \initial + attribute \src "libresoc.v:115540.9-115540.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\ppick_i[7:0] $2\ppick_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ppick_i[7:0] $3\ppick_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:581" + switch \move_one + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\ppick_i[7:0] \LOGICAL_FXM + case + assign $3\ppick_i[7:0] 8'00000000 + end + case + assign $2\ppick_i[7:0] 8'00000000 + end + case + assign $1\ppick_i[7:0] 8'00000000 + end + sync always + update \ppick_i $0\ppick_i[7:0] + end + attribute \src "libresoc.v:115560.3-115594.6" + process $proc$libresoc.v:115560$4575 + assign { } { } + assign { } { } + assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] + attribute \src "libresoc.v:115561.5-115561.29" + switch \initial + attribute \src "libresoc.v:115561.9-115561.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_fxm[7:0] $3\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:581" + switch \move_one + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\cr_fxm[7:0] $4\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:584" + switch \ppick_en_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\cr_fxm[7:0] \ppick_o + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $4\cr_fxm[7:0] 8'00000001 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $3\cr_fxm[7:0] \LOGICAL_FXM + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cr_fxm[7:0] 8'11111111 + end + case + assign $1\cr_fxm[7:0] 8'00000000 + end + sync always + update \cr_fxm $0\cr_fxm[7:0] + end + connect \$1 $eq$libresoc.v:115472$4568_Y + connect \$3 $eq$libresoc.v:115473$4569_Y +end +attribute \src "libresoc.v:115599.1-115838.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_SPR.dec_cr_out" +attribute \generator "nMigen" +module \dec_cr_out$166 + attribute \src "libresoc.v:115752.3-115770.6" + wire width 3 $0\cr_bitfield[2:0] + attribute \src "libresoc.v:115722.3-115740.6" + wire $0\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:115803.3-115837.6" + wire width 8 $0\cr_fxm[7:0] + attribute \src "libresoc.v:115741.3-115751.6" + wire $0\cr_fxm_ok[0:0] + attribute \src "libresoc.v:115600.7-115600.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:115771.3-115781.6" + wire $0\move_one[0:0] + attribute \src "libresoc.v:115782.3-115802.6" + wire width 8 $0\ppick_i[7:0] + attribute \src "libresoc.v:115752.3-115770.6" + wire width 3 $1\cr_bitfield[2:0] + attribute \src "libresoc.v:115722.3-115740.6" + wire $1\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:115803.3-115837.6" + wire width 8 $1\cr_fxm[7:0] + attribute \src "libresoc.v:115741.3-115751.6" + wire $1\cr_fxm_ok[0:0] + attribute \src "libresoc.v:115771.3-115781.6" + wire $1\move_one[0:0] + attribute \src "libresoc.v:115782.3-115802.6" + wire width 8 $1\ppick_i[7:0] + attribute \src "libresoc.v:115803.3-115837.6" + wire width 8 $2\cr_fxm[7:0] + attribute \src "libresoc.v:115782.3-115802.6" + wire width 8 $2\ppick_i[7:0] + attribute \src "libresoc.v:115803.3-115837.6" + wire width 8 $3\cr_fxm[7:0] + attribute \src "libresoc.v:115782.3-115802.6" + wire width 8 $3\ppick_i[7:0] + attribute \src "libresoc.v:115803.3-115837.6" + wire width 8 $4\cr_fxm[7:0] + attribute \src "libresoc.v:115715.17-115715.121" + wire $eq$libresoc.v:115715$4577_Y + attribute \src "libresoc.v:115716.17-115716.121" + wire $eq$libresoc.v:115716$4578_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 8 input 4 \SPR_FXM + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 input 3 \SPR_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 input 6 \XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 input 5 \X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \cr_bitfield + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_bitfield_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 8 \cr_fxm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_fxm_ok + attribute \src "libresoc.v:115600.7-115600.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:551" + wire width 32 input 7 \insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:578" + wire \move_one + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire \ppick_en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 \ppick_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 \ppick_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:549" + wire input 2 \rc_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:550" + wire width 3 input 1 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + cell $eq $eq$libresoc.v:115715$4577 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \SPR_internal_op + connect \B 7'0110000 + connect \Y $eq$libresoc.v:115715$4577_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + cell $eq $eq$libresoc.v:115716$4578 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \SPR_internal_op + connect \B 7'0110000 + connect \Y $eq$libresoc.v:115716$4578_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:115717.15-115721.4" + cell \ppick$167 \ppick + connect \en_o \ppick_en_o + connect \i \ppick_i + connect \o \ppick_o + end + attribute \src "libresoc.v:115600.7-115600.20" + process $proc$libresoc.v:115600$4585 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:115722.3-115740.6" + process $proc$libresoc.v:115722$4579 + assign { } { } + assign { } { } + assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:115723.5-115723.29" + switch \initial + attribute \src "libresoc.v:115723.9-115723.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\cr_bitfield_ok[0:0] \rc_in + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + case + assign $1\cr_bitfield_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] + end + attribute \src "libresoc.v:115741.3-115751.6" + process $proc$libresoc.v:115741$4580 + assign { } { } + assign { } { } + assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] + attribute \src "libresoc.v:115742.5-115742.29" + switch \initial + attribute \src "libresoc.v:115742.9-115742.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_fxm_ok[0:0] 1'1 + case + assign $1\cr_fxm_ok[0:0] 1'0 + end + sync always + update \cr_fxm_ok $0\cr_fxm_ok[0:0] + end + attribute \src "libresoc.v:115752.3-115770.6" + process $proc$libresoc.v:115752$4581 + assign { } { } + assign { } { } + assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] + attribute \src "libresoc.v:115753.5-115753.29" + switch \initial + attribute \src "libresoc.v:115753.9-115753.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\cr_bitfield[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\cr_bitfield[2:0] \X_BF + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield[2:0] \XL_BT [4:2] + case + assign $1\cr_bitfield[2:0] 3'000 + end + sync always + update \cr_bitfield $0\cr_bitfield[2:0] + end + attribute \src "libresoc.v:115771.3-115781.6" + process $proc$libresoc.v:115771$4582 + assign { } { } + assign { } { } + assign $0\move_one[0:0] $1\move_one[0:0] + attribute \src "libresoc.v:115772.5-115772.29" + switch \initial + attribute \src "libresoc.v:115772.9-115772.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\move_one[0:0] \insn_in [20] + case + assign $1\move_one[0:0] 1'0 + end + sync always + update \move_one $0\move_one[0:0] + end + attribute \src "libresoc.v:115782.3-115802.6" + process $proc$libresoc.v:115782$4583 + assign { } { } + assign { } { } + assign $0\ppick_i[7:0] $1\ppick_i[7:0] + attribute \src "libresoc.v:115783.5-115783.29" + switch \initial + attribute \src "libresoc.v:115783.9-115783.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\ppick_i[7:0] $2\ppick_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ppick_i[7:0] $3\ppick_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:581" + switch \move_one + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\ppick_i[7:0] \SPR_FXM + case + assign $3\ppick_i[7:0] 8'00000000 + end + case + assign $2\ppick_i[7:0] 8'00000000 + end + case + assign $1\ppick_i[7:0] 8'00000000 + end + sync always + update \ppick_i $0\ppick_i[7:0] + end + attribute \src "libresoc.v:115803.3-115837.6" + process $proc$libresoc.v:115803$4584 + assign { } { } + assign { } { } + assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] + attribute \src "libresoc.v:115804.5-115804.29" + switch \initial + attribute \src "libresoc.v:115804.9-115804.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_fxm[7:0] $3\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:581" + switch \move_one + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\cr_fxm[7:0] $4\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:584" + switch \ppick_en_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\cr_fxm[7:0] \ppick_o + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $4\cr_fxm[7:0] 8'00000001 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $3\cr_fxm[7:0] \SPR_FXM + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cr_fxm[7:0] 8'11111111 + end + case + assign $1\cr_fxm[7:0] 8'00000000 + end + sync always + update \cr_fxm $0\cr_fxm[7:0] + end + connect \$1 $eq$libresoc.v:115715$4577_Y + connect \$3 $eq$libresoc.v:115716$4578_Y +end +attribute \src "libresoc.v:115842.1-116082.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_DIV.dec_cr_out" +attribute \generator "nMigen" +module \dec_cr_out$173 + attribute \src "libresoc.v:115996.3-116014.6" + wire width 3 $0\cr_bitfield[2:0] + attribute \src "libresoc.v:115966.3-115984.6" + wire $0\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:116047.3-116081.6" + wire width 8 $0\cr_fxm[7:0] + attribute \src "libresoc.v:115985.3-115995.6" + wire $0\cr_fxm_ok[0:0] + attribute \src "libresoc.v:115843.7-115843.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:116015.3-116025.6" + wire $0\move_one[0:0] + attribute \src "libresoc.v:116026.3-116046.6" + wire width 8 $0\ppick_i[7:0] + attribute \src "libresoc.v:115996.3-116014.6" + wire width 3 $1\cr_bitfield[2:0] + attribute \src "libresoc.v:115966.3-115984.6" + wire $1\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:116047.3-116081.6" + wire width 8 $1\cr_fxm[7:0] + attribute \src "libresoc.v:115985.3-115995.6" + wire $1\cr_fxm_ok[0:0] + attribute \src "libresoc.v:116015.3-116025.6" + wire $1\move_one[0:0] + attribute \src "libresoc.v:116026.3-116046.6" + wire width 8 $1\ppick_i[7:0] + attribute \src "libresoc.v:116047.3-116081.6" + wire width 8 $2\cr_fxm[7:0] + attribute \src "libresoc.v:116026.3-116046.6" + wire width 8 $2\ppick_i[7:0] + attribute \src "libresoc.v:116047.3-116081.6" + wire width 8 $3\cr_fxm[7:0] + attribute \src "libresoc.v:116026.3-116046.6" + wire width 8 $3\ppick_i[7:0] + attribute \src "libresoc.v:116047.3-116081.6" + wire width 8 $4\cr_fxm[7:0] + attribute \src "libresoc.v:115959.17-115959.121" + wire $eq$libresoc.v:115959$4586_Y + attribute \src "libresoc.v:115960.17-115960.121" + wire $eq$libresoc.v:115960$4587_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 8 input 5 \DIV_FXM + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 input 3 \DIV_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 input 7 \XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 input 6 \X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \cr_bitfield + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 4 \cr_bitfield_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 8 \cr_fxm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_fxm_ok + attribute \src "libresoc.v:115843.7-115843.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:551" + wire width 32 input 8 \insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:578" + wire \move_one + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire \ppick_en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 \ppick_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 \ppick_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:549" + wire input 2 \rc_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:550" + wire width 3 input 1 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + cell $eq $eq$libresoc.v:115959$4586 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \DIV_internal_op + connect \B 7'0110000 + connect \Y $eq$libresoc.v:115959$4586_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + cell $eq $eq$libresoc.v:115960$4587 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \DIV_internal_op + connect \B 7'0110000 + connect \Y $eq$libresoc.v:115960$4587_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:115961.15-115965.4" + cell \ppick$174 \ppick + connect \en_o \ppick_en_o + connect \i \ppick_i + connect \o \ppick_o + end + attribute \src "libresoc.v:115843.7-115843.20" + process $proc$libresoc.v:115843$4594 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:115966.3-115984.6" + process $proc$libresoc.v:115966$4588 + assign { } { } + assign { } { } + assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:115967.5-115967.29" + switch \initial + attribute \src "libresoc.v:115967.9-115967.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\cr_bitfield_ok[0:0] \rc_in + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + case + assign $1\cr_bitfield_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] + end + attribute \src "libresoc.v:115985.3-115995.6" + process $proc$libresoc.v:115985$4589 + assign { } { } + assign { } { } + assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] + attribute \src "libresoc.v:115986.5-115986.29" + switch \initial + attribute \src "libresoc.v:115986.9-115986.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_fxm_ok[0:0] 1'1 + case + assign $1\cr_fxm_ok[0:0] 1'0 + end + sync always + update \cr_fxm_ok $0\cr_fxm_ok[0:0] + end + attribute \src "libresoc.v:115996.3-116014.6" + process $proc$libresoc.v:115996$4590 + assign { } { } + assign { } { } + assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] + attribute \src "libresoc.v:115997.5-115997.29" + switch \initial + attribute \src "libresoc.v:115997.9-115997.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\cr_bitfield[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\cr_bitfield[2:0] \X_BF + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield[2:0] \XL_BT [4:2] + case + assign $1\cr_bitfield[2:0] 3'000 + end + sync always + update \cr_bitfield $0\cr_bitfield[2:0] + end + attribute \src "libresoc.v:116015.3-116025.6" + process $proc$libresoc.v:116015$4591 + assign { } { } + assign { } { } + assign $0\move_one[0:0] $1\move_one[0:0] + attribute \src "libresoc.v:116016.5-116016.29" + switch \initial + attribute \src "libresoc.v:116016.9-116016.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\move_one[0:0] \insn_in [20] + case + assign $1\move_one[0:0] 1'0 + end + sync always + update \move_one $0\move_one[0:0] + end + attribute \src "libresoc.v:116026.3-116046.6" + process $proc$libresoc.v:116026$4592 + assign { } { } + assign { } { } + assign $0\ppick_i[7:0] $1\ppick_i[7:0] + attribute \src "libresoc.v:116027.5-116027.29" + switch \initial + attribute \src "libresoc.v:116027.9-116027.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\ppick_i[7:0] $2\ppick_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ppick_i[7:0] $3\ppick_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:581" + switch \move_one + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\ppick_i[7:0] \DIV_FXM + case + assign $3\ppick_i[7:0] 8'00000000 + end + case + assign $2\ppick_i[7:0] 8'00000000 + end + case + assign $1\ppick_i[7:0] 8'00000000 + end + sync always + update \ppick_i $0\ppick_i[7:0] + end + attribute \src "libresoc.v:116047.3-116081.6" + process $proc$libresoc.v:116047$4593 + assign { } { } + assign { } { } + assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] + attribute \src "libresoc.v:116048.5-116048.29" + switch \initial + attribute \src "libresoc.v:116048.9-116048.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_fxm[7:0] $3\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:581" + switch \move_one + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\cr_fxm[7:0] $4\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:584" + switch \ppick_en_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\cr_fxm[7:0] \ppick_o + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $4\cr_fxm[7:0] 8'00000001 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $3\cr_fxm[7:0] \DIV_FXM + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cr_fxm[7:0] 8'11111111 + end + case + assign $1\cr_fxm[7:0] 8'00000000 + end + sync always + update \cr_fxm $0\cr_fxm[7:0] + end + connect \$1 $eq$libresoc.v:115959$4586_Y + connect \$3 $eq$libresoc.v:115960$4587_Y +end +attribute \src "libresoc.v:116086.1-116326.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_MUL.dec_cr_out" +attribute \generator "nMigen" +module \dec_cr_out$182 + attribute \src "libresoc.v:116240.3-116258.6" + wire width 3 $0\cr_bitfield[2:0] + attribute \src "libresoc.v:116210.3-116228.6" + wire $0\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:116291.3-116325.6" + wire width 8 $0\cr_fxm[7:0] + attribute \src "libresoc.v:116229.3-116239.6" + wire $0\cr_fxm_ok[0:0] + attribute \src "libresoc.v:116087.7-116087.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:116259.3-116269.6" + wire $0\move_one[0:0] + attribute \src "libresoc.v:116270.3-116290.6" + wire width 8 $0\ppick_i[7:0] + attribute \src "libresoc.v:116240.3-116258.6" + wire width 3 $1\cr_bitfield[2:0] + attribute \src "libresoc.v:116210.3-116228.6" + wire $1\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:116291.3-116325.6" + wire width 8 $1\cr_fxm[7:0] + attribute \src "libresoc.v:116229.3-116239.6" + wire $1\cr_fxm_ok[0:0] + attribute \src "libresoc.v:116259.3-116269.6" + wire $1\move_one[0:0] + attribute \src "libresoc.v:116270.3-116290.6" + wire width 8 $1\ppick_i[7:0] + attribute \src "libresoc.v:116291.3-116325.6" + wire width 8 $2\cr_fxm[7:0] + attribute \src "libresoc.v:116270.3-116290.6" + wire width 8 $2\ppick_i[7:0] + attribute \src "libresoc.v:116291.3-116325.6" + wire width 8 $3\cr_fxm[7:0] + attribute \src "libresoc.v:116270.3-116290.6" + wire width 8 $3\ppick_i[7:0] + attribute \src "libresoc.v:116291.3-116325.6" + wire width 8 $4\cr_fxm[7:0] + attribute \src "libresoc.v:116203.17-116203.121" + wire $eq$libresoc.v:116203$4595_Y + attribute \src "libresoc.v:116204.17-116204.121" + wire $eq$libresoc.v:116204$4596_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 8 input 5 \MUL_FXM + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 input 3 \MUL_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 input 7 \XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 input 6 \X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \cr_bitfield + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 4 \cr_bitfield_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 8 \cr_fxm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_fxm_ok + attribute \src "libresoc.v:116087.7-116087.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:551" + wire width 32 input 8 \insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:578" + wire \move_one + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire \ppick_en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 \ppick_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 \ppick_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:549" + wire input 2 \rc_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:550" + wire width 3 input 1 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + cell $eq $eq$libresoc.v:116203$4595 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \MUL_internal_op + connect \B 7'0110000 + connect \Y $eq$libresoc.v:116203$4595_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + cell $eq $eq$libresoc.v:116204$4596 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \MUL_internal_op + connect \B 7'0110000 + connect \Y $eq$libresoc.v:116204$4596_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:116205.15-116209.4" + cell \ppick$183 \ppick + connect \en_o \ppick_en_o + connect \i \ppick_i + connect \o \ppick_o + end + attribute \src "libresoc.v:116087.7-116087.20" + process $proc$libresoc.v:116087$4603 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:116210.3-116228.6" + process $proc$libresoc.v:116210$4597 + assign { } { } + assign { } { } + assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:116211.5-116211.29" + switch \initial + attribute \src "libresoc.v:116211.9-116211.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\cr_bitfield_ok[0:0] \rc_in + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + case + assign $1\cr_bitfield_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] + end + attribute \src "libresoc.v:116229.3-116239.6" + process $proc$libresoc.v:116229$4598 + assign { } { } + assign { } { } + assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] + attribute \src "libresoc.v:116230.5-116230.29" + switch \initial + attribute \src "libresoc.v:116230.9-116230.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_fxm_ok[0:0] 1'1 + case + assign $1\cr_fxm_ok[0:0] 1'0 + end + sync always + update \cr_fxm_ok $0\cr_fxm_ok[0:0] + end + attribute \src "libresoc.v:116240.3-116258.6" + process $proc$libresoc.v:116240$4599 + assign { } { } + assign { } { } + assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] + attribute \src "libresoc.v:116241.5-116241.29" + switch \initial + attribute \src "libresoc.v:116241.9-116241.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\cr_bitfield[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\cr_bitfield[2:0] \X_BF + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield[2:0] \XL_BT [4:2] + case + assign $1\cr_bitfield[2:0] 3'000 + end + sync always + update \cr_bitfield $0\cr_bitfield[2:0] + end + attribute \src "libresoc.v:116259.3-116269.6" + process $proc$libresoc.v:116259$4600 + assign { } { } + assign { } { } + assign $0\move_one[0:0] $1\move_one[0:0] + attribute \src "libresoc.v:116260.5-116260.29" + switch \initial + attribute \src "libresoc.v:116260.9-116260.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\move_one[0:0] \insn_in [20] + case + assign $1\move_one[0:0] 1'0 + end + sync always + update \move_one $0\move_one[0:0] + end + attribute \src "libresoc.v:116270.3-116290.6" + process $proc$libresoc.v:116270$4601 + assign { } { } + assign { } { } + assign $0\ppick_i[7:0] $1\ppick_i[7:0] + attribute \src "libresoc.v:116271.5-116271.29" + switch \initial + attribute \src "libresoc.v:116271.9-116271.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\ppick_i[7:0] $2\ppick_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ppick_i[7:0] $3\ppick_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:581" + switch \move_one + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\ppick_i[7:0] \MUL_FXM + case + assign $3\ppick_i[7:0] 8'00000000 + end + case + assign $2\ppick_i[7:0] 8'00000000 + end + case + assign $1\ppick_i[7:0] 8'00000000 + end + sync always + update \ppick_i $0\ppick_i[7:0] + end + attribute \src "libresoc.v:116291.3-116325.6" + process $proc$libresoc.v:116291$4602 + assign { } { } + assign { } { } + assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] + attribute \src "libresoc.v:116292.5-116292.29" + switch \initial + attribute \src "libresoc.v:116292.9-116292.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_fxm[7:0] $3\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:581" + switch \move_one + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\cr_fxm[7:0] $4\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:584" + switch \ppick_en_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\cr_fxm[7:0] \ppick_o + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $4\cr_fxm[7:0] 8'00000001 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $3\cr_fxm[7:0] \MUL_FXM + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cr_fxm[7:0] 8'11111111 + end + case + assign $1\cr_fxm[7:0] 8'00000000 + end + sync always + update \cr_fxm $0\cr_fxm[7:0] + end + connect \$1 $eq$libresoc.v:116203$4595_Y + connect \$3 $eq$libresoc.v:116204$4596_Y +end +attribute \src "libresoc.v:116330.1-116570.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_SHIFT_ROT.dec_cr_out" +attribute \generator "nMigen" +module \dec_cr_out$190 + attribute \src "libresoc.v:116484.3-116502.6" + wire width 3 $0\cr_bitfield[2:0] + attribute \src "libresoc.v:116454.3-116472.6" + wire $0\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:116535.3-116569.6" + wire width 8 $0\cr_fxm[7:0] + attribute \src "libresoc.v:116473.3-116483.6" + wire $0\cr_fxm_ok[0:0] + attribute \src "libresoc.v:116331.7-116331.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:116503.3-116513.6" + wire $0\move_one[0:0] + attribute \src "libresoc.v:116514.3-116534.6" + wire width 8 $0\ppick_i[7:0] + attribute \src "libresoc.v:116484.3-116502.6" + wire width 3 $1\cr_bitfield[2:0] + attribute \src "libresoc.v:116454.3-116472.6" + wire $1\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:116535.3-116569.6" + wire width 8 $1\cr_fxm[7:0] + attribute \src "libresoc.v:116473.3-116483.6" + wire $1\cr_fxm_ok[0:0] + attribute \src "libresoc.v:116503.3-116513.6" + wire $1\move_one[0:0] + attribute \src "libresoc.v:116514.3-116534.6" + wire width 8 $1\ppick_i[7:0] + attribute \src "libresoc.v:116535.3-116569.6" + wire width 8 $2\cr_fxm[7:0] + attribute \src "libresoc.v:116514.3-116534.6" + wire width 8 $2\ppick_i[7:0] + attribute \src "libresoc.v:116535.3-116569.6" + wire width 8 $3\cr_fxm[7:0] + attribute \src "libresoc.v:116514.3-116534.6" + wire width 8 $3\ppick_i[7:0] + attribute \src "libresoc.v:116535.3-116569.6" + wire width 8 $4\cr_fxm[7:0] + attribute \src "libresoc.v:116447.17-116447.127" + wire $eq$libresoc.v:116447$4604_Y + attribute \src "libresoc.v:116448.17-116448.127" + wire $eq$libresoc.v:116448$4605_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 8 input 5 \SHIFT_ROT_FXM + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 input 3 \SHIFT_ROT_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 input 7 \XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 input 6 \X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \cr_bitfield + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 4 \cr_bitfield_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 8 \cr_fxm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_fxm_ok + attribute \src "libresoc.v:116331.7-116331.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:551" + wire width 32 input 8 \insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:578" + wire \move_one + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire \ppick_en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 \ppick_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 \ppick_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:549" + wire input 2 \rc_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:550" + wire width 3 input 1 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + cell $eq $eq$libresoc.v:116447$4604 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \SHIFT_ROT_internal_op + connect \B 7'0110000 + connect \Y $eq$libresoc.v:116447$4604_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + cell $eq $eq$libresoc.v:116448$4605 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \SHIFT_ROT_internal_op + connect \B 7'0110000 + connect \Y $eq$libresoc.v:116448$4605_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:116449.15-116453.4" + cell \ppick$191 \ppick + connect \en_o \ppick_en_o + connect \i \ppick_i + connect \o \ppick_o + end + attribute \src "libresoc.v:116331.7-116331.20" + process $proc$libresoc.v:116331$4612 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:116454.3-116472.6" + process $proc$libresoc.v:116454$4606 + assign { } { } + assign { } { } + assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:116455.5-116455.29" + switch \initial + attribute \src "libresoc.v:116455.9-116455.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\cr_bitfield_ok[0:0] \rc_in + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + case + assign $1\cr_bitfield_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] + end + attribute \src "libresoc.v:116473.3-116483.6" + process $proc$libresoc.v:116473$4607 + assign { } { } + assign { } { } + assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] + attribute \src "libresoc.v:116474.5-116474.29" + switch \initial + attribute \src "libresoc.v:116474.9-116474.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_fxm_ok[0:0] 1'1 + case + assign $1\cr_fxm_ok[0:0] 1'0 + end + sync always + update \cr_fxm_ok $0\cr_fxm_ok[0:0] + end + attribute \src "libresoc.v:116484.3-116502.6" + process $proc$libresoc.v:116484$4608 + assign { } { } + assign { } { } + assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] + attribute \src "libresoc.v:116485.5-116485.29" + switch \initial + attribute \src "libresoc.v:116485.9-116485.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\cr_bitfield[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\cr_bitfield[2:0] \X_BF + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield[2:0] \XL_BT [4:2] + case + assign $1\cr_bitfield[2:0] 3'000 + end + sync always + update \cr_bitfield $0\cr_bitfield[2:0] + end + attribute \src "libresoc.v:116503.3-116513.6" + process $proc$libresoc.v:116503$4609 + assign { } { } + assign { } { } + assign $0\move_one[0:0] $1\move_one[0:0] + attribute \src "libresoc.v:116504.5-116504.29" + switch \initial + attribute \src "libresoc.v:116504.9-116504.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\move_one[0:0] \insn_in [20] + case + assign $1\move_one[0:0] 1'0 + end + sync always + update \move_one $0\move_one[0:0] + end + attribute \src "libresoc.v:116514.3-116534.6" + process $proc$libresoc.v:116514$4610 + assign { } { } + assign { } { } + assign $0\ppick_i[7:0] $1\ppick_i[7:0] + attribute \src "libresoc.v:116515.5-116515.29" + switch \initial + attribute \src "libresoc.v:116515.9-116515.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\ppick_i[7:0] $2\ppick_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ppick_i[7:0] $3\ppick_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:581" + switch \move_one + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\ppick_i[7:0] \SHIFT_ROT_FXM + case + assign $3\ppick_i[7:0] 8'00000000 + end + case + assign $2\ppick_i[7:0] 8'00000000 + end + case + assign $1\ppick_i[7:0] 8'00000000 + end + sync always + update \ppick_i $0\ppick_i[7:0] + end + attribute \src "libresoc.v:116535.3-116569.6" + process $proc$libresoc.v:116535$4611 + assign { } { } + assign { } { } + assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] + attribute \src "libresoc.v:116536.5-116536.29" + switch \initial + attribute \src "libresoc.v:116536.9-116536.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_fxm[7:0] $3\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:581" + switch \move_one + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\cr_fxm[7:0] $4\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:584" + switch \ppick_en_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\cr_fxm[7:0] \ppick_o + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $4\cr_fxm[7:0] 8'00000001 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $3\cr_fxm[7:0] \SHIFT_ROT_FXM + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cr_fxm[7:0] 8'11111111 + end + case + assign $1\cr_fxm[7:0] 8'00000000 + end + sync always + update \cr_fxm $0\cr_fxm[7:0] + end + connect \$1 $eq$libresoc.v:116447$4604_Y + connect \$3 $eq$libresoc.v:116448$4605_Y +end +attribute \src "libresoc.v:116574.1-116813.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_LDST.dec_cr_out" +attribute \generator "nMigen" +module \dec_cr_out$198 + attribute \src "libresoc.v:116727.3-116745.6" + wire width 3 $0\cr_bitfield[2:0] + attribute \src "libresoc.v:116697.3-116715.6" + wire $0\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:116778.3-116812.6" + wire width 8 $0\cr_fxm[7:0] + attribute \src "libresoc.v:116716.3-116726.6" + wire $0\cr_fxm_ok[0:0] + attribute \src "libresoc.v:116575.7-116575.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:116746.3-116756.6" + wire $0\move_one[0:0] + attribute \src "libresoc.v:116757.3-116777.6" + wire width 8 $0\ppick_i[7:0] + attribute \src "libresoc.v:116727.3-116745.6" + wire width 3 $1\cr_bitfield[2:0] + attribute \src "libresoc.v:116697.3-116715.6" + wire $1\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:116778.3-116812.6" + wire width 8 $1\cr_fxm[7:0] + attribute \src "libresoc.v:116716.3-116726.6" + wire $1\cr_fxm_ok[0:0] + attribute \src "libresoc.v:116746.3-116756.6" + wire $1\move_one[0:0] + attribute \src "libresoc.v:116757.3-116777.6" + wire width 8 $1\ppick_i[7:0] + attribute \src "libresoc.v:116778.3-116812.6" + wire width 8 $2\cr_fxm[7:0] + attribute \src "libresoc.v:116757.3-116777.6" + wire width 8 $2\ppick_i[7:0] + attribute \src "libresoc.v:116778.3-116812.6" + wire width 8 $3\cr_fxm[7:0] + attribute \src "libresoc.v:116757.3-116777.6" + wire width 8 $3\ppick_i[7:0] + attribute \src "libresoc.v:116778.3-116812.6" + wire width 8 $4\cr_fxm[7:0] + attribute \src "libresoc.v:116690.17-116690.122" + wire $eq$libresoc.v:116690$4613_Y + attribute \src "libresoc.v:116691.17-116691.122" + wire $eq$libresoc.v:116691$4614_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 8 input 4 \LDST_FXM + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 input 3 \LDST_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 input 6 \XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 input 5 \X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \cr_bitfield + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_bitfield_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 8 \cr_fxm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_fxm_ok + attribute \src "libresoc.v:116575.7-116575.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:551" + wire width 32 input 7 \insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:578" + wire \move_one + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire \ppick_en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 \ppick_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 \ppick_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:549" + wire input 2 \rc_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:550" + wire width 3 input 1 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + cell $eq $eq$libresoc.v:116690$4613 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \LDST_internal_op + connect \B 7'0110000 + connect \Y $eq$libresoc.v:116690$4613_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + cell $eq $eq$libresoc.v:116691$4614 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \LDST_internal_op + connect \B 7'0110000 + connect \Y $eq$libresoc.v:116691$4614_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:116692.15-116696.4" + cell \ppick$199 \ppick + connect \en_o \ppick_en_o + connect \i \ppick_i + connect \o \ppick_o + end + attribute \src "libresoc.v:116575.7-116575.20" + process $proc$libresoc.v:116575$4621 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:116697.3-116715.6" + process $proc$libresoc.v:116697$4615 + assign { } { } + assign { } { } + assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:116698.5-116698.29" + switch \initial + attribute \src "libresoc.v:116698.9-116698.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\cr_bitfield_ok[0:0] \rc_in + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + case + assign $1\cr_bitfield_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] + end + attribute \src "libresoc.v:116716.3-116726.6" + process $proc$libresoc.v:116716$4616 + assign { } { } + assign { } { } + assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] + attribute \src "libresoc.v:116717.5-116717.29" + switch \initial + attribute \src "libresoc.v:116717.9-116717.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_fxm_ok[0:0] 1'1 + case + assign $1\cr_fxm_ok[0:0] 1'0 + end + sync always + update \cr_fxm_ok $0\cr_fxm_ok[0:0] + end + attribute \src "libresoc.v:116727.3-116745.6" + process $proc$libresoc.v:116727$4617 + assign { } { } + assign { } { } + assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] + attribute \src "libresoc.v:116728.5-116728.29" + switch \initial + attribute \src "libresoc.v:116728.9-116728.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\cr_bitfield[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\cr_bitfield[2:0] \X_BF + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield[2:0] \XL_BT [4:2] + case + assign $1\cr_bitfield[2:0] 3'000 + end + sync always + update \cr_bitfield $0\cr_bitfield[2:0] + end + attribute \src "libresoc.v:116746.3-116756.6" + process $proc$libresoc.v:116746$4618 + assign { } { } + assign { } { } + assign $0\move_one[0:0] $1\move_one[0:0] + attribute \src "libresoc.v:116747.5-116747.29" + switch \initial + attribute \src "libresoc.v:116747.9-116747.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\move_one[0:0] \insn_in [20] + case + assign $1\move_one[0:0] 1'0 + end + sync always + update \move_one $0\move_one[0:0] + end + attribute \src "libresoc.v:116757.3-116777.6" + process $proc$libresoc.v:116757$4619 + assign { } { } + assign { } { } + assign $0\ppick_i[7:0] $1\ppick_i[7:0] + attribute \src "libresoc.v:116758.5-116758.29" + switch \initial + attribute \src "libresoc.v:116758.9-116758.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\ppick_i[7:0] $2\ppick_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ppick_i[7:0] $3\ppick_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:581" + switch \move_one + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\ppick_i[7:0] \LDST_FXM + case + assign $3\ppick_i[7:0] 8'00000000 + end + case + assign $2\ppick_i[7:0] 8'00000000 + end + case + assign $1\ppick_i[7:0] 8'00000000 + end + sync always + update \ppick_i $0\ppick_i[7:0] + end + attribute \src "libresoc.v:116778.3-116812.6" + process $proc$libresoc.v:116778$4620 + assign { } { } + assign { } { } + assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] + attribute \src "libresoc.v:116779.5-116779.29" + switch \initial + attribute \src "libresoc.v:116779.9-116779.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_fxm[7:0] $3\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:581" + switch \move_one + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\cr_fxm[7:0] $4\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:584" + switch \ppick_en_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\cr_fxm[7:0] \ppick_o + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $4\cr_fxm[7:0] 8'00000001 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $3\cr_fxm[7:0] \LDST_FXM + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cr_fxm[7:0] 8'11111111 + end + case + assign $1\cr_fxm[7:0] 8'00000000 + end + sync always + update \cr_fxm $0\cr_fxm[7:0] + end + connect \$1 $eq$libresoc.v:116690$4613_Y + connect \$3 $eq$libresoc.v:116691$4614_Y +end +attribute \src "libresoc.v:116817.1-117060.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.dec2.dec_cr_out" +attribute \generator "nMigen" +module \dec_cr_out$207 + attribute \src "libresoc.v:116974.3-116992.6" + wire width 3 $0\cr_bitfield[2:0] + attribute \src "libresoc.v:116944.3-116962.6" + wire $0\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:117025.3-117059.6" + wire width 8 $0\cr_fxm[7:0] + attribute \src "libresoc.v:116963.3-116973.6" + wire $0\cr_fxm_ok[0:0] + attribute \src "libresoc.v:116818.7-116818.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:116993.3-117003.6" + wire $0\move_one[0:0] + attribute \src "libresoc.v:117004.3-117024.6" + wire width 8 $0\ppick_i[7:0] + attribute \src "libresoc.v:116974.3-116992.6" + wire width 3 $1\cr_bitfield[2:0] + attribute \src "libresoc.v:116944.3-116962.6" + wire $1\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:117025.3-117059.6" + wire width 8 $1\cr_fxm[7:0] + attribute \src "libresoc.v:116963.3-116973.6" + wire $1\cr_fxm_ok[0:0] + attribute \src "libresoc.v:116993.3-117003.6" + wire $1\move_one[0:0] + attribute \src "libresoc.v:117004.3-117024.6" + wire width 8 $1\ppick_i[7:0] + attribute \src "libresoc.v:117025.3-117059.6" + wire width 8 $2\cr_fxm[7:0] + attribute \src "libresoc.v:117004.3-117024.6" + wire width 8 $2\ppick_i[7:0] + attribute \src "libresoc.v:117025.3-117059.6" + wire width 8 $3\cr_fxm[7:0] + attribute \src "libresoc.v:117004.3-117024.6" + wire width 8 $3\ppick_i[7:0] + attribute \src "libresoc.v:117025.3-117059.6" + wire width 8 $4\cr_fxm[7:0] + attribute \src "libresoc.v:116937.17-116937.117" + wire $eq$libresoc.v:116937$4622_Y + attribute \src "libresoc.v:116938.17-116938.117" + wire $eq$libresoc.v:116938$4623_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 8 input 8 \FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 input 10 \XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 input 9 \X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 output 6 \cr_bitfield + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 7 \cr_bitfield_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 8 output 4 \cr_fxm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 5 \cr_fxm_ok + attribute \src "libresoc.v:116818.7-116818.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:551" + wire width 32 input 11 \insn_in + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 input 3 \internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:578" + wire \move_one + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire \ppick_en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 \ppick_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 \ppick_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:549" + wire input 2 \rc_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:550" + wire width 3 input 1 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + cell $eq $eq$libresoc.v:116937$4622 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \internal_op + connect \B 7'0110000 + connect \Y $eq$libresoc.v:116937$4622_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + cell $eq $eq$libresoc.v:116938$4623 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \internal_op + connect \B 7'0110000 + connect \Y $eq$libresoc.v:116938$4623_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:116939.15-116943.4" + cell \ppick$208 \ppick + connect \en_o \ppick_en_o + connect \i \ppick_i + connect \o \ppick_o + end + attribute \src "libresoc.v:116818.7-116818.20" + process $proc$libresoc.v:116818$4630 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:116944.3-116962.6" + process $proc$libresoc.v:116944$4624 + assign { } { } + assign { } { } + assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:116945.5-116945.29" + switch \initial + attribute \src "libresoc.v:116945.9-116945.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\cr_bitfield_ok[0:0] \rc_in + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + case + assign $1\cr_bitfield_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] + end + attribute \src "libresoc.v:116963.3-116973.6" + process $proc$libresoc.v:116963$4625 + assign { } { } + assign { } { } + assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] + attribute \src "libresoc.v:116964.5-116964.29" + switch \initial + attribute \src "libresoc.v:116964.9-116964.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_fxm_ok[0:0] 1'1 + case + assign $1\cr_fxm_ok[0:0] 1'0 + end + sync always + update \cr_fxm_ok $0\cr_fxm_ok[0:0] + end + attribute \src "libresoc.v:116974.3-116992.6" + process $proc$libresoc.v:116974$4626 + assign { } { } + assign { } { } + assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] + attribute \src "libresoc.v:116975.5-116975.29" + switch \initial + attribute \src "libresoc.v:116975.9-116975.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\cr_bitfield[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\cr_bitfield[2:0] \X_BF + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield[2:0] \XL_BT [4:2] + case + assign $1\cr_bitfield[2:0] 3'000 + end + sync always + update \cr_bitfield $0\cr_bitfield[2:0] + end + attribute \src "libresoc.v:116993.3-117003.6" + process $proc$libresoc.v:116993$4627 + assign { } { } + assign { } { } + assign $0\move_one[0:0] $1\move_one[0:0] + attribute \src "libresoc.v:116994.5-116994.29" + switch \initial + attribute \src "libresoc.v:116994.9-116994.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\move_one[0:0] \insn_in [20] + case + assign $1\move_one[0:0] 1'0 + end + sync always + update \move_one $0\move_one[0:0] + end + attribute \src "libresoc.v:117004.3-117024.6" + process $proc$libresoc.v:117004$4628 + assign { } { } + assign { } { } + assign $0\ppick_i[7:0] $1\ppick_i[7:0] + attribute \src "libresoc.v:117005.5-117005.29" + switch \initial + attribute \src "libresoc.v:117005.9-117005.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\ppick_i[7:0] $2\ppick_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ppick_i[7:0] $3\ppick_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:581" + switch \move_one + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\ppick_i[7:0] \FXM + case + assign $3\ppick_i[7:0] 8'00000000 + end + case + assign $2\ppick_i[7:0] 8'00000000 + end + case + assign $1\ppick_i[7:0] 8'00000000 + end + sync always + update \ppick_i $0\ppick_i[7:0] + end + attribute \src "libresoc.v:117025.3-117059.6" + process $proc$libresoc.v:117025$4629 + assign { } { } + assign { } { } + assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] + attribute \src "libresoc.v:117026.5-117026.29" + switch \initial + attribute \src "libresoc.v:117026.9-117026.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_fxm[7:0] $3\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:581" + switch \move_one + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\cr_fxm[7:0] $4\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:584" + switch \ppick_en_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\cr_fxm[7:0] \ppick_o + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $4\cr_fxm[7:0] 8'00000001 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $3\cr_fxm[7:0] \FXM + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cr_fxm[7:0] 8'11111111 + end + case + assign $1\cr_fxm[7:0] 8'00000000 + end + sync always + update \cr_fxm $0\cr_fxm[7:0] + end + connect \$1 $eq$libresoc.v:116937$4622_Y + connect \$3 $eq$libresoc.v:116938$4623_Y +end +attribute \src "libresoc.v:117064.1-117541.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.dec2.dec_o" +attribute \generator "nMigen" +module \dec_o + attribute \src "libresoc.v:117502.3-117540.6" + wire width 3 $0\fast_o[2:0] + attribute \src "libresoc.v:117502.3-117540.6" + wire $0\fast_o_ok[0:0] + attribute \src "libresoc.v:117065.7-117065.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:117428.3-117442.6" + wire width 5 $0\reg_o[4:0] + attribute \src "libresoc.v:117443.3-117457.6" + wire $0\reg_o_ok[0:0] + attribute \src "libresoc.v:117458.3-117468.6" + wire width 10 $0\spr[9:0] + attribute \src "libresoc.v:117485.3-117501.6" + wire width 10 $0\spr_o[9:0] + attribute \src "libresoc.v:117485.3-117501.6" + wire $0\spr_o_ok[0:0] + attribute \src "libresoc.v:117469.3-117484.6" + wire width 10 $0\sprmap_spr_i[9:0] + attribute \src "libresoc.v:117502.3-117540.6" + wire width 3 $1\fast_o[2:0] + attribute \src "libresoc.v:117502.3-117540.6" + wire $1\fast_o_ok[0:0] + attribute \src "libresoc.v:117428.3-117442.6" + wire width 5 $1\reg_o[4:0] + attribute \src "libresoc.v:117443.3-117457.6" + wire $1\reg_o_ok[0:0] + attribute \src "libresoc.v:117458.3-117468.6" + wire width 10 $1\spr[9:0] + attribute \src "libresoc.v:117485.3-117501.6" + wire width 10 $1\spr_o[9:0] + attribute \src "libresoc.v:117485.3-117501.6" + wire $1\spr_o_ok[0:0] + attribute \src "libresoc.v:117469.3-117484.6" + wire width 10 $1\sprmap_spr_i[9:0] + attribute \src "libresoc.v:117502.3-117540.6" + wire width 3 $2\fast_o[2:0] + attribute \src "libresoc.v:117502.3-117540.6" + wire $2\fast_o_ok[0:0] + attribute \src "libresoc.v:117485.3-117501.6" + wire width 10 $2\spr_o[9:0] + attribute \src "libresoc.v:117485.3-117501.6" + wire $2\spr_o_ok[0:0] + attribute \src "libresoc.v:117469.3-117484.6" + wire width 10 $2\sprmap_spr_i[9:0] + attribute \src "libresoc.v:117502.3-117540.6" + wire width 3 $3\fast_o[2:0] + attribute \src "libresoc.v:117502.3-117540.6" + wire $3\fast_o_ok[0:0] + attribute \src "libresoc.v:117502.3-117540.6" + wire width 3 $4\fast_o[2:0] + attribute \src "libresoc.v:117502.3-117540.6" + wire $4\fast_o_ok[0:0] + attribute \src "libresoc.v:117417.17-117417.117" + wire $eq$libresoc.v:117417$4631_Y + attribute \src "libresoc.v:117418.17-117418.117" + wire $eq$libresoc.v:117418$4632_Y + attribute \src "libresoc.v:117419.17-117419.117" + wire $eq$libresoc.v:117419$4633_Y + attribute \src "libresoc.v:117420.17-117420.104" + wire $not$libresoc.v:117420$4634_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:332" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:332" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:332" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:341" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 10 \BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 9 \RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 8 \RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 10 input 11 \SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 output 6 \fast_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 7 \fast_o_ok + attribute \src "libresoc.v:117065.7-117065.15" + wire \initial + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 input 12 \internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 output 2 \reg_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 3 \reg_o_ok + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:308" + wire width 2 input 1 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:329" + wire width 10 \spr + attribute \enum_base_type "SPR" + attribute \enum_value_0000000001 "XER" + attribute \enum_value_0000000011 "DSCR" + attribute \enum_value_0000001000 "LR" + attribute \enum_value_0000001001 "CTR" + attribute \enum_value_0000001101 "AMR" + attribute \enum_value_0000010001 "DSCR_priv" + attribute \enum_value_0000010010 "DSISR" + attribute \enum_value_0000010011 "DAR" + attribute \enum_value_0000010110 "DEC" + attribute \enum_value_0000011010 "SRR0" + attribute \enum_value_0000011011 "SRR1" + attribute \enum_value_0000011100 "CFAR" + attribute \enum_value_0000011101 "AMR_priv" + attribute \enum_value_0000110000 "PIDR" + attribute \enum_value_0000111101 "IAMR" + attribute \enum_value_0010000000 "TFHAR" + attribute \enum_value_0010000001 "TFIAR" + attribute \enum_value_0010000010 "TEXASR" + attribute \enum_value_0010000011 "TEXASRU" + attribute \enum_value_0010001000 "CTRL" + attribute \enum_value_0010010000 "TIDR" + attribute \enum_value_0010011000 "CTRL_priv" + attribute \enum_value_0010011001 "FSCR" + attribute \enum_value_0010011101 "UAMOR" + attribute \enum_value_0010011110 "GSR" + attribute \enum_value_0010011111 "PSPB" + attribute \enum_value_0010110000 "DPDES" + attribute \enum_value_0010110100 "DAWR0" + attribute \enum_value_0010111010 "RPR" + attribute \enum_value_0010111011 "CIABR" + attribute \enum_value_0010111100 "DAWRX0" + attribute \enum_value_0010111110 "HFSCR" + attribute \enum_value_0100000000 "VRSAVE" + attribute \enum_value_0100000011 "SPRG3" + attribute \enum_value_0100001100 "TB" + attribute \enum_value_0100001101 "TBU" + attribute \enum_value_0100010000 "SPRG0_priv" + attribute \enum_value_0100010001 "SPRG1_priv" + attribute \enum_value_0100010010 "SPRG2_priv" + attribute \enum_value_0100010011 "SPRG3_priv" + attribute \enum_value_0100011011 "CIR" + attribute \enum_value_0100011100 "TBL" + attribute \enum_value_0100011101 "TBU_hypv" + attribute \enum_value_0100011110 "TBU40" + attribute \enum_value_0100011111 "PVR" + attribute \enum_value_0100110000 "HSPRG0" + attribute \enum_value_0100110001 "HSPRG1" + attribute \enum_value_0100110010 "HDSISR" + attribute \enum_value_0100110011 "HDAR" + attribute \enum_value_0100110100 "SPURR" + attribute \enum_value_0100110101 "PURR" + attribute \enum_value_0100110110 "HDEC" + attribute \enum_value_0100111001 "HRMOR" + attribute \enum_value_0100111010 "HSRR0" + attribute \enum_value_0100111011 "HSRR1" + attribute \enum_value_0100111110 "LPCR" + attribute \enum_value_0100111111 "LPIDR" + attribute \enum_value_0101010000 "HMER" + attribute \enum_value_0101010001 "HMEER" + attribute \enum_value_0101010010 "PCR" + attribute \enum_value_0101010011 "HEIR" + attribute \enum_value_0101011101 "AMOR" + attribute \enum_value_0110111110 "TIR" + attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1100000000 "SIER" + attribute \enum_value_1100000001 "MMCR2" + attribute \enum_value_1100000010 "MMCRA" + attribute \enum_value_1100000011 "PMC1" + attribute \enum_value_1100000100 "PMC2" + attribute \enum_value_1100000101 "PMC3" + attribute \enum_value_1100000110 "PMC4" + attribute \enum_value_1100000111 "PMC5" + attribute \enum_value_1100001000 "PMC6" + attribute \enum_value_1100001011 "MMCR0" + attribute \enum_value_1100001100 "SIAR" + attribute \enum_value_1100001101 "SDAR" + attribute \enum_value_1100001110 "MMCR1" + attribute \enum_value_1100010000 "SIER_priv" + attribute \enum_value_1100010001 "MMCR2_priv" + attribute \enum_value_1100010010 "MMCRA_priv" + attribute \enum_value_1100010011 "PMC1_priv" + attribute \enum_value_1100010100 "PMC2_priv" + attribute \enum_value_1100010101 "PMC3_priv" + attribute \enum_value_1100010110 "PMC4_priv" + attribute \enum_value_1100010111 "PMC5_priv" + attribute \enum_value_1100011000 "PMC6_priv" + attribute \enum_value_1100011011 "MMCR0_priv" + attribute \enum_value_1100011100 "SIAR_priv" + attribute \enum_value_1100011101 "SDAR_priv" + attribute \enum_value_1100011110 "MMCR1_priv" + attribute \enum_value_1100100000 "BESCRS" + attribute \enum_value_1100100001 "BESCRSU" + attribute \enum_value_1100100010 "BESCRR" + attribute \enum_value_1100100011 "BESCRRU" + attribute \enum_value_1100100100 "EBBHR" + attribute \enum_value_1100100101 "EBBRR" + attribute \enum_value_1100100110 "BESCR" + attribute \enum_value_1100101000 "reserved808" + attribute \enum_value_1100101001 "reserved809" + attribute \enum_value_1100101010 "reserved810" + attribute \enum_value_1100101011 "reserved811" + attribute \enum_value_1100101111 "TAR" + attribute \enum_value_1100110000 "ASDR" + attribute \enum_value_1100110111 "PSSCR" + attribute \enum_value_1101010000 "IC" + attribute \enum_value_1101010001 "VTB" + attribute \enum_value_1101010111 "PSSCR_hypv" + attribute \enum_value_1110000000 "PPR" + attribute \enum_value_1110000010 "PPR32" + attribute \enum_value_1111111111 "PIR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 10 output 4 \spr_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 5 \spr_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \sprmap_fast_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \sprmap_fast_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:59" + wire width 10 \sprmap_spr_i + attribute \enum_base_type "SPR" + attribute \enum_value_0000000001 "XER" + attribute \enum_value_0000000011 "DSCR" + attribute \enum_value_0000001000 "LR" + attribute \enum_value_0000001001 "CTR" + attribute \enum_value_0000001101 "AMR" + attribute \enum_value_0000010001 "DSCR_priv" + attribute \enum_value_0000010010 "DSISR" + attribute \enum_value_0000010011 "DAR" + attribute \enum_value_0000010110 "DEC" + attribute \enum_value_0000011010 "SRR0" + attribute \enum_value_0000011011 "SRR1" + attribute \enum_value_0000011100 "CFAR" + attribute \enum_value_0000011101 "AMR_priv" + attribute \enum_value_0000110000 "PIDR" + attribute \enum_value_0000111101 "IAMR" + attribute \enum_value_0010000000 "TFHAR" + attribute \enum_value_0010000001 "TFIAR" + attribute \enum_value_0010000010 "TEXASR" + attribute \enum_value_0010000011 "TEXASRU" + attribute \enum_value_0010001000 "CTRL" + attribute \enum_value_0010010000 "TIDR" + attribute \enum_value_0010011000 "CTRL_priv" + attribute \enum_value_0010011001 "FSCR" + attribute \enum_value_0010011101 "UAMOR" + attribute \enum_value_0010011110 "GSR" + attribute \enum_value_0010011111 "PSPB" + attribute \enum_value_0010110000 "DPDES" + attribute \enum_value_0010110100 "DAWR0" + attribute \enum_value_0010111010 "RPR" + attribute \enum_value_0010111011 "CIABR" + attribute \enum_value_0010111100 "DAWRX0" + attribute \enum_value_0010111110 "HFSCR" + attribute \enum_value_0100000000 "VRSAVE" + attribute \enum_value_0100000011 "SPRG3" + attribute \enum_value_0100001100 "TB" + attribute \enum_value_0100001101 "TBU" + attribute \enum_value_0100010000 "SPRG0_priv" + attribute \enum_value_0100010001 "SPRG1_priv" + attribute \enum_value_0100010010 "SPRG2_priv" + attribute \enum_value_0100010011 "SPRG3_priv" + attribute \enum_value_0100011011 "CIR" + attribute \enum_value_0100011100 "TBL" + attribute \enum_value_0100011101 "TBU_hypv" + attribute \enum_value_0100011110 "TBU40" + attribute \enum_value_0100011111 "PVR" + attribute \enum_value_0100110000 "HSPRG0" + attribute \enum_value_0100110001 "HSPRG1" + attribute \enum_value_0100110010 "HDSISR" + attribute \enum_value_0100110011 "HDAR" + attribute \enum_value_0100110100 "SPURR" + attribute \enum_value_0100110101 "PURR" + attribute \enum_value_0100110110 "HDEC" + attribute \enum_value_0100111001 "HRMOR" + attribute \enum_value_0100111010 "HSRR0" + attribute \enum_value_0100111011 "HSRR1" + attribute \enum_value_0100111110 "LPCR" + attribute \enum_value_0100111111 "LPIDR" + attribute \enum_value_0101010000 "HMER" + attribute \enum_value_0101010001 "HMEER" + attribute \enum_value_0101010010 "PCR" + attribute \enum_value_0101010011 "HEIR" + attribute \enum_value_0101011101 "AMOR" + attribute \enum_value_0110111110 "TIR" + attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1100000000 "SIER" + attribute \enum_value_1100000001 "MMCR2" + attribute \enum_value_1100000010 "MMCRA" + attribute \enum_value_1100000011 "PMC1" + attribute \enum_value_1100000100 "PMC2" + attribute \enum_value_1100000101 "PMC3" + attribute \enum_value_1100000110 "PMC4" + attribute \enum_value_1100000111 "PMC5" + attribute \enum_value_1100001000 "PMC6" + attribute \enum_value_1100001011 "MMCR0" + attribute \enum_value_1100001100 "SIAR" + attribute \enum_value_1100001101 "SDAR" + attribute \enum_value_1100001110 "MMCR1" + attribute \enum_value_1100010000 "SIER_priv" + attribute \enum_value_1100010001 "MMCR2_priv" + attribute \enum_value_1100010010 "MMCRA_priv" + attribute \enum_value_1100010011 "PMC1_priv" + attribute \enum_value_1100010100 "PMC2_priv" + attribute \enum_value_1100010101 "PMC3_priv" + attribute \enum_value_1100010110 "PMC4_priv" + attribute \enum_value_1100010111 "PMC5_priv" + attribute \enum_value_1100011000 "PMC6_priv" + attribute \enum_value_1100011011 "MMCR0_priv" + attribute \enum_value_1100011100 "SIAR_priv" + attribute \enum_value_1100011101 "SDAR_priv" + attribute \enum_value_1100011110 "MMCR1_priv" + attribute \enum_value_1100100000 "BESCRS" + attribute \enum_value_1100100001 "BESCRSU" + attribute \enum_value_1100100010 "BESCRR" + attribute \enum_value_1100100011 "BESCRRU" + attribute \enum_value_1100100100 "EBBHR" + attribute \enum_value_1100100101 "EBBRR" + attribute \enum_value_1100100110 "BESCR" + attribute \enum_value_1100101000 "reserved808" + attribute \enum_value_1100101001 "reserved809" + attribute \enum_value_1100101010 "reserved810" + attribute \enum_value_1100101011 "reserved811" + attribute \enum_value_1100101111 "TAR" + attribute \enum_value_1100110000 "ASDR" + attribute \enum_value_1100110111 "PSSCR" + attribute \enum_value_1101010000 "IC" + attribute \enum_value_1101010001 "VTB" + attribute \enum_value_1101010111 "PSSCR_hypv" + attribute \enum_value_1110000000 "PPR" + attribute \enum_value_1110000010 "PPR32" + attribute \enum_value_1111111111 "PIR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 10 \sprmap_spr_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \sprmap_spr_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:332" + cell $eq $eq$libresoc.v:117417$4631 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \internal_op + connect \B 7'0110001 + connect \Y $eq$libresoc.v:117417$4631_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:332" + cell $eq $eq$libresoc.v:117418$4632 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \internal_op + connect \B 7'0110001 + connect \Y $eq$libresoc.v:117418$4632_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:332" + cell $eq $eq$libresoc.v:117419$4633 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \internal_op + connect \B 7'0110001 + connect \Y $eq$libresoc.v:117419$4633_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:341" + cell $not $not$libresoc.v:117420$4634 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \BO [2] + connect \Y $not$libresoc.v:117420$4634_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:117421.16-117427.4" + cell \sprmap$209 \sprmap + connect \fast_o \sprmap_fast_o + connect \fast_o_ok \sprmap_fast_o_ok + connect \spr_i \sprmap_spr_i + connect \spr_o \sprmap_spr_o + connect \spr_o_ok \sprmap_spr_o_ok + end + attribute \src "libresoc.v:117065.7-117065.20" + process $proc$libresoc.v:117065$4641 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:117428.3-117442.6" + process $proc$libresoc.v:117428$4635 + assign { } { } + assign { } { } + assign $0\reg_o[4:0] $1\reg_o[4:0] + attribute \src "libresoc.v:117429.5-117429.29" + switch \initial + attribute \src "libresoc.v:117429.9-117429.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:321" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\reg_o[4:0] \RT + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\reg_o[4:0] \RA + case + assign $1\reg_o[4:0] 5'00000 + end + sync always + update \reg_o $0\reg_o[4:0] + end + attribute \src "libresoc.v:117443.3-117457.6" + process $proc$libresoc.v:117443$4636 + assign { } { } + assign { } { } + assign $0\reg_o_ok[0:0] $1\reg_o_ok[0:0] + attribute \src "libresoc.v:117444.5-117444.29" + switch \initial + attribute \src "libresoc.v:117444.9-117444.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:321" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\reg_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\reg_o_ok[0:0] 1'1 + case + assign $1\reg_o_ok[0:0] 1'0 + end + sync always + update \reg_o_ok $0\reg_o_ok[0:0] + end + attribute \src "libresoc.v:117458.3-117468.6" + process $proc$libresoc.v:117458$4637 + assign { } { } + assign { } { } + assign $0\spr[9:0] $1\spr[9:0] + attribute \src "libresoc.v:117459.5-117459.29" + switch \initial + attribute \src "libresoc.v:117459.9-117459.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:321" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'11 + assign { } { } + assign $1\spr[9:0] { \SPR [4:0] \SPR [9:5] } + case + assign $1\spr[9:0] 10'0000000000 + end + sync always + update \spr $0\spr[9:0] + end + attribute \src "libresoc.v:117469.3-117484.6" + process $proc$libresoc.v:117469$4638 + assign { } { } + assign { } { } + assign $0\sprmap_spr_i[9:0] $1\sprmap_spr_i[9:0] + attribute \src "libresoc.v:117470.5-117470.29" + switch \initial + attribute \src "libresoc.v:117470.9-117470.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:321" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'11 + assign { } { } + assign $1\sprmap_spr_i[9:0] $2\sprmap_spr_i[9:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:332" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\sprmap_spr_i[9:0] \spr + case + assign $2\sprmap_spr_i[9:0] 10'0000000000 + end + case + assign $1\sprmap_spr_i[9:0] 10'0000000000 + end + sync always + update \sprmap_spr_i $0\sprmap_spr_i[9:0] + end + attribute \src "libresoc.v:117485.3-117501.6" + process $proc$libresoc.v:117485$4639 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\spr_o[9:0] $1\spr_o[9:0] + assign $0\spr_o_ok[0:0] $1\spr_o_ok[0:0] + attribute \src "libresoc.v:117486.5-117486.29" + switch \initial + attribute \src "libresoc.v:117486.9-117486.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:321" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'11 + assign { } { } + assign { } { } + assign $1\spr_o[9:0] $2\spr_o[9:0] + assign $1\spr_o_ok[0:0] $2\spr_o_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:332" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\spr_o_ok[0:0] $2\spr_o[9:0] } { \sprmap_spr_o_ok \sprmap_spr_o } + case + assign $2\spr_o[9:0] 10'0000000000 + assign $2\spr_o_ok[0:0] 1'0 + end + case + assign $1\spr_o[9:0] 10'0000000000 + assign $1\spr_o_ok[0:0] 1'0 + end + sync always + update \spr_o $0\spr_o[9:0] + update \spr_o_ok $0\spr_o_ok[0:0] + end + attribute \src "libresoc.v:117502.3-117540.6" + process $proc$libresoc.v:117502$4640 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fast_o[2:0] $3\fast_o[2:0] + assign $0\fast_o_ok[0:0] $3\fast_o_ok[0:0] + attribute \src "libresoc.v:117503.5-117503.29" + switch \initial + attribute \src "libresoc.v:117503.9-117503.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:321" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'11 + assign { } { } + assign { } { } + assign $1\fast_o[2:0] $2\fast_o[2:0] + assign $1\fast_o_ok[0:0] $2\fast_o_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:332" + switch \$5 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\fast_o_ok[0:0] $2\fast_o[2:0] } { \sprmap_fast_o_ok \sprmap_fast_o } + case + assign $2\fast_o[2:0] 3'000 + assign $2\fast_o_ok[0:0] 1'0 + end + case + assign $1\fast_o[2:0] 3'000 + assign $1\fast_o_ok[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:337" + switch \internal_op + attribute \src "libresoc.v:0.0-0.0" + case 7'0000111 , 7'0001000 + assign { } { } + assign { } { } + assign $3\fast_o[2:0] $4\fast_o[2:0] + assign $3\fast_o_ok[0:0] $4\fast_o_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:341" + switch \$7 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $4\fast_o[2:0] 3'000 + assign $4\fast_o_ok[0:0] 1'1 + case + assign $4\fast_o[2:0] $1\fast_o[2:0] + assign $4\fast_o_ok[0:0] $1\fast_o_ok[0:0] + end + attribute \src "libresoc.v:0.0-0.0" + case 7'1000110 + assign { } { } + assign { } { } + assign $3\fast_o[2:0] 3'011 + assign $3\fast_o_ok[0:0] 1'1 + case + assign $3\fast_o[2:0] $1\fast_o[2:0] + assign $3\fast_o_ok[0:0] $1\fast_o_ok[0:0] + end + sync always + update \fast_o $0\fast_o[2:0] + update \fast_o_ok $0\fast_o_ok[0:0] + end + connect \$1 $eq$libresoc.v:117417$4631_Y + connect \$3 $eq$libresoc.v:117418$4632_Y + connect \$5 $eq$libresoc.v:117419$4633_Y + connect \$7 $not$libresoc.v:117420$4634_Y +end +attribute \src "libresoc.v:117545.1-117706.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.dec2.dec_o2" +attribute \generator "nMigen" +module \dec_o2 + attribute \src "libresoc.v:117666.3-117685.6" + wire width 3 $0\fast_o[2:0] + attribute \src "libresoc.v:117686.3-117705.6" + wire $0\fast_o_ok[0:0] + attribute \src "libresoc.v:117546.7-117546.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:117652.3-117665.6" + wire width 5 $0\reg_o[4:0] + attribute \src "libresoc.v:117652.3-117665.6" + wire $0\reg_o_ok[0:0] + attribute \src "libresoc.v:117666.3-117685.6" + wire width 3 $1\fast_o[2:0] + attribute \src "libresoc.v:117686.3-117705.6" + wire $1\fast_o_ok[0:0] + attribute \src "libresoc.v:117652.3-117665.6" + wire width 5 $1\reg_o[4:0] + attribute \src "libresoc.v:117652.3-117665.6" + wire $1\reg_o_ok[0:0] + attribute \src "libresoc.v:117666.3-117685.6" + wire width 3 $2\fast_o[2:0] + attribute \src "libresoc.v:117686.3-117705.6" + wire $2\fast_o_ok[0:0] + attribute \src "libresoc.v:117650.17-117650.108" + wire $eq$libresoc.v:117650$4642_Y + attribute \src "libresoc.v:117651.17-117651.100" + wire width 6 $extend$libresoc.v:117651$4643_Y + attribute \src "libresoc.v:117651.17-117651.100" + wire width 6 $pos$libresoc.v:117651$4644_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:374" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 6 \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 7 \RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 output 4 \fast_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 5 \fast_o_ok + attribute \src "libresoc.v:117546.7-117546.15" + wire \initial + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 input 8 \internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:363" + wire input 1 \lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 output 2 \reg_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 3 \reg_o_ok + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 input 6 \upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:374" + cell $eq $eq$libresoc.v:117650$4642 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \upd + connect \B 2'01 + connect \Y $eq$libresoc.v:117650$4642_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + cell $pos $extend$libresoc.v:117651$4643 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 6 + connect \A \RA + connect \Y $extend$libresoc.v:117651$4643_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + cell $pos $pos$libresoc.v:117651$4644 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A $extend$libresoc.v:117651$4643_Y + connect \Y $pos$libresoc.v:117651$4644_Y + end + attribute \src "libresoc.v:117546.7-117546.20" + process $proc$libresoc.v:117546$4648 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:117652.3-117665.6" + process $proc$libresoc.v:117652$4645 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\reg_o[4:0] $1\reg_o[4:0] + assign $0\reg_o_ok[0:0] $1\reg_o_ok[0:0] + attribute \src "libresoc.v:117653.5-117653.29" + switch \initial + attribute \src "libresoc.v:117653.9-117653.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:374" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $1\reg_o[4:0] \$3 [4:0] + assign $1\reg_o_ok[0:0] 1'1 + case + assign $1\reg_o[4:0] 5'00000 + assign $1\reg_o_ok[0:0] 1'0 + end + sync always + update \reg_o $0\reg_o[4:0] + update \reg_o_ok $0\reg_o_ok[0:0] + end + attribute \src "libresoc.v:117666.3-117685.6" + process $proc$libresoc.v:117666$4646 + assign { } { } + assign { } { } + assign $0\fast_o[2:0] $1\fast_o[2:0] + attribute \src "libresoc.v:117667.5-117667.29" + switch \initial + attribute \src "libresoc.v:117667.9-117667.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:381" + switch \internal_op + attribute \src "libresoc.v:0.0-0.0" + case 7'0000111 , 7'0000110 , 7'0001000 + assign { } { } + assign $1\fast_o[2:0] $2\fast_o[2:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:385" + switch \lk + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\fast_o[2:0] 3'001 + case + assign $2\fast_o[2:0] 3'000 + end + attribute \src "libresoc.v:0.0-0.0" + case 7'1000110 + assign { } { } + assign $1\fast_o[2:0] 3'100 + case + assign $1\fast_o[2:0] 3'000 + end + sync always + update \fast_o $0\fast_o[2:0] + end + attribute \src "libresoc.v:117686.3-117705.6" + process $proc$libresoc.v:117686$4647 + assign { } { } + assign { } { } + assign $0\fast_o_ok[0:0] $1\fast_o_ok[0:0] + attribute \src "libresoc.v:117687.5-117687.29" + switch \initial + attribute \src "libresoc.v:117687.9-117687.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:381" + switch \internal_op + attribute \src "libresoc.v:0.0-0.0" + case 7'0000111 , 7'0000110 , 7'0001000 + assign { } { } + assign $1\fast_o_ok[0:0] $2\fast_o_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:385" + switch \lk + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\fast_o_ok[0:0] 1'1 + case + assign $2\fast_o_ok[0:0] 1'0 + end + attribute \src "libresoc.v:0.0-0.0" + case 7'1000110 + assign { } { } + assign $1\fast_o_ok[0:0] 1'1 + case + assign $1\fast_o_ok[0:0] 1'0 + end + sync always + update \fast_o_ok $0\fast_o_ok[0:0] + end + connect \$1 $eq$libresoc.v:117650$4642_Y + connect \$3 $pos$libresoc.v:117651$4644_Y +end +attribute \src "libresoc.v:117710.1-117844.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_ALU.dec_oe" +attribute \generator "nMigen" +module \dec_oe + attribute \src "libresoc.v:117711.7-117711.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:117802.3-117822.6" + wire $0\oe[0:0] + attribute \src "libresoc.v:117823.3-117843.6" + wire $0\oe_ok[0:0] + attribute \src "libresoc.v:117802.3-117822.6" + wire $1\oe[0:0] + attribute \src "libresoc.v:117823.3-117843.6" + wire $1\oe_ok[0:0] + attribute \src "libresoc.v:117802.3-117822.6" + wire $2\oe[0:0] + attribute \src "libresoc.v:117823.3-117843.6" + wire $2\oe_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire input 4 \ALU_OE + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 input 1 \ALU_internal_op + attribute \src "libresoc.v:117711.7-117711.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 2 \oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 3 \oe_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" + wire width 2 input 5 \sel_in + attribute \src "libresoc.v:117711.7-117711.20" + process $proc$libresoc.v:117711$4651 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:117802.3-117822.6" + process $proc$libresoc.v:117802$4649 + assign { } { } + assign { } { } + assign $0\oe[0:0] $1\oe[0:0] + attribute \src "libresoc.v:117803.5-117803.29" + switch \initial + attribute \src "libresoc.v:117803.9-117803.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:451" + switch \ALU_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 + assign $1\oe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\oe[0:0] $2\oe[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:468" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $2\oe[0:0] \ALU_OE + case + assign $2\oe[0:0] 1'0 + end + end + sync always + update \oe $0\oe[0:0] + end + attribute \src "libresoc.v:117823.3-117843.6" + process $proc$libresoc.v:117823$4650 + assign { } { } + assign { } { } + assign $0\oe_ok[0:0] $1\oe_ok[0:0] + attribute \src "libresoc.v:117824.5-117824.29" + switch \initial + attribute \src "libresoc.v:117824.9-117824.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:451" + switch \ALU_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 + assign $1\oe_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\oe_ok[0:0] $2\oe_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:468" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $2\oe_ok[0:0] 1'1 + case + assign $2\oe_ok[0:0] 1'0 + end + end + sync always + update \oe_ok $0\oe_ok[0:0] + end +end +attribute \src "libresoc.v:117848.1-117980.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_CR.dec_oe" +attribute \generator "nMigen" +module \dec_oe$139 + attribute \src "libresoc.v:117849.7-117849.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:117938.3-117958.6" + wire $0\oe[0:0] + attribute \src "libresoc.v:117959.3-117979.6" + wire $0\oe_ok[0:0] + attribute \src "libresoc.v:117938.3-117958.6" + wire $1\oe[0:0] + attribute \src "libresoc.v:117959.3-117979.6" + wire $1\oe_ok[0:0] + attribute \src "libresoc.v:117938.3-117958.6" + wire $2\oe[0:0] + attribute \src "libresoc.v:117959.3-117979.6" + wire $2\oe_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire input 2 \CR_OE + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 input 1 \CR_internal_op + attribute \src "libresoc.v:117849.7-117849.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \oe_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" + wire width 2 input 3 \sel_in + attribute \src "libresoc.v:117849.7-117849.20" + process $proc$libresoc.v:117849$4654 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:117938.3-117958.6" + process $proc$libresoc.v:117938$4652 + assign { } { } + assign { } { } + assign $0\oe[0:0] $1\oe[0:0] + attribute \src "libresoc.v:117939.5-117939.29" + switch \initial + attribute \src "libresoc.v:117939.9-117939.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:451" + switch \CR_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 + assign $1\oe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\oe[0:0] $2\oe[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:468" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $2\oe[0:0] \CR_OE + case + assign $2\oe[0:0] 1'0 + end + end + sync always + update \oe $0\oe[0:0] + end + attribute \src "libresoc.v:117959.3-117979.6" + process $proc$libresoc.v:117959$4653 + assign { } { } + assign { } { } + assign $0\oe_ok[0:0] $1\oe_ok[0:0] + attribute \src "libresoc.v:117960.5-117960.29" + switch \initial + attribute \src "libresoc.v:117960.9-117960.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:451" + switch \CR_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 + assign $1\oe_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\oe_ok[0:0] $2\oe_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:468" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $2\oe_ok[0:0] 1'1 + case + assign $2\oe_ok[0:0] 1'0 + end + end + sync always + update \oe_ok $0\oe_ok[0:0] + end +end +attribute \src "libresoc.v:117984.1-118116.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_BRANCH.dec_oe" +attribute \generator "nMigen" +module \dec_oe$146 + attribute \src "libresoc.v:117985.7-117985.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:118074.3-118094.6" + wire $0\oe[0:0] + attribute \src "libresoc.v:118095.3-118115.6" + wire $0\oe_ok[0:0] + attribute \src "libresoc.v:118074.3-118094.6" + wire $1\oe[0:0] + attribute \src "libresoc.v:118095.3-118115.6" + wire $1\oe_ok[0:0] + attribute \src "libresoc.v:118074.3-118094.6" + wire $2\oe[0:0] + attribute \src "libresoc.v:118095.3-118115.6" + wire $2\oe_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire input 2 \BRANCH_OE + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 input 1 \BRANCH_internal_op + attribute \src "libresoc.v:117985.7-117985.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \oe_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" + wire width 2 input 3 \sel_in + attribute \src "libresoc.v:117985.7-117985.20" + process $proc$libresoc.v:117985$4657 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:118074.3-118094.6" + process $proc$libresoc.v:118074$4655 + assign { } { } + assign { } { } + assign $0\oe[0:0] $1\oe[0:0] + attribute \src "libresoc.v:118075.5-118075.29" + switch \initial + attribute \src "libresoc.v:118075.9-118075.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:451" + switch \BRANCH_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 + assign $1\oe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\oe[0:0] $2\oe[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:468" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $2\oe[0:0] \BRANCH_OE + case + assign $2\oe[0:0] 1'0 + end + end + sync always + update \oe $0\oe[0:0] + end + attribute \src "libresoc.v:118095.3-118115.6" + process $proc$libresoc.v:118095$4656 + assign { } { } + assign { } { } + assign $0\oe_ok[0:0] $1\oe_ok[0:0] + attribute \src "libresoc.v:118096.5-118096.29" + switch \initial + attribute \src "libresoc.v:118096.9-118096.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:451" + switch \BRANCH_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 + assign $1\oe_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\oe_ok[0:0] $2\oe_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:468" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $2\oe_ok[0:0] 1'1 + case + assign $2\oe_ok[0:0] 1'0 + end + end + sync always + update \oe_ok $0\oe_ok[0:0] + end +end +attribute \src "libresoc.v:118120.1-118254.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_LOGICAL.dec_oe" +attribute \generator "nMigen" +module \dec_oe$154 + attribute \src "libresoc.v:118121.7-118121.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:118212.3-118232.6" + wire $0\oe[0:0] + attribute \src "libresoc.v:118233.3-118253.6" + wire $0\oe_ok[0:0] + attribute \src "libresoc.v:118212.3-118232.6" + wire $1\oe[0:0] + attribute \src "libresoc.v:118233.3-118253.6" + wire $1\oe_ok[0:0] + attribute \src "libresoc.v:118212.3-118232.6" + wire $2\oe[0:0] + attribute \src "libresoc.v:118233.3-118253.6" + wire $2\oe_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire input 4 \LOGICAL_OE + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 input 1 \LOGICAL_internal_op + attribute \src "libresoc.v:118121.7-118121.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 2 \oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 3 \oe_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" + wire width 2 input 5 \sel_in + attribute \src "libresoc.v:118121.7-118121.20" + process $proc$libresoc.v:118121$4660 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:118212.3-118232.6" + process $proc$libresoc.v:118212$4658 + assign { } { } + assign { } { } + assign $0\oe[0:0] $1\oe[0:0] + attribute \src "libresoc.v:118213.5-118213.29" + switch \initial + attribute \src "libresoc.v:118213.9-118213.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:451" + switch \LOGICAL_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 + assign $1\oe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\oe[0:0] $2\oe[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:468" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $2\oe[0:0] \LOGICAL_OE + case + assign $2\oe[0:0] 1'0 + end + end + sync always + update \oe $0\oe[0:0] + end + attribute \src "libresoc.v:118233.3-118253.6" + process $proc$libresoc.v:118233$4659 + assign { } { } + assign { } { } + assign $0\oe_ok[0:0] $1\oe_ok[0:0] + attribute \src "libresoc.v:118234.5-118234.29" + switch \initial + attribute \src "libresoc.v:118234.9-118234.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:451" + switch \LOGICAL_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 + assign $1\oe_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\oe_ok[0:0] $2\oe_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:468" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $2\oe_ok[0:0] 1'1 + case + assign $2\oe_ok[0:0] 1'0 + end + end + sync always + update \oe_ok $0\oe_ok[0:0] + end +end +attribute \src "libresoc.v:118258.1-118390.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_SPR.dec_oe" +attribute \generator "nMigen" +module \dec_oe$163 + attribute \src "libresoc.v:118259.7-118259.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:118348.3-118368.6" + wire $0\oe[0:0] + attribute \src "libresoc.v:118369.3-118389.6" + wire $0\oe_ok[0:0] + attribute \src "libresoc.v:118348.3-118368.6" + wire $1\oe[0:0] + attribute \src "libresoc.v:118369.3-118389.6" + wire $1\oe_ok[0:0] + attribute \src "libresoc.v:118348.3-118368.6" + wire $2\oe[0:0] + attribute \src "libresoc.v:118369.3-118389.6" + wire $2\oe_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire input 2 \SPR_OE + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 input 1 \SPR_internal_op + attribute \src "libresoc.v:118259.7-118259.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \oe_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" + wire width 2 input 3 \sel_in + attribute \src "libresoc.v:118259.7-118259.20" + process $proc$libresoc.v:118259$4663 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:118348.3-118368.6" + process $proc$libresoc.v:118348$4661 + assign { } { } + assign { } { } + assign $0\oe[0:0] $1\oe[0:0] + attribute \src "libresoc.v:118349.5-118349.29" + switch \initial + attribute \src "libresoc.v:118349.9-118349.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:451" + switch \SPR_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 + assign $1\oe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\oe[0:0] $2\oe[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:468" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $2\oe[0:0] \SPR_OE + case + assign $2\oe[0:0] 1'0 + end + end + sync always + update \oe $0\oe[0:0] + end + attribute \src "libresoc.v:118369.3-118389.6" + process $proc$libresoc.v:118369$4662 + assign { } { } + assign { } { } + assign $0\oe_ok[0:0] $1\oe_ok[0:0] + attribute \src "libresoc.v:118370.5-118370.29" + switch \initial + attribute \src "libresoc.v:118370.9-118370.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:451" + switch \SPR_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 + assign $1\oe_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\oe_ok[0:0] $2\oe_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:468" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $2\oe_ok[0:0] 1'1 + case + assign $2\oe_ok[0:0] 1'0 + end + end + sync always + update \oe_ok $0\oe_ok[0:0] + end +end +attribute \src "libresoc.v:118394.1-118528.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_DIV.dec_oe" +attribute \generator "nMigen" +module \dec_oe$170 + attribute \src "libresoc.v:118395.7-118395.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:118486.3-118506.6" + wire $0\oe[0:0] + attribute \src "libresoc.v:118507.3-118527.6" + wire $0\oe_ok[0:0] + attribute \src "libresoc.v:118486.3-118506.6" + wire $1\oe[0:0] + attribute \src "libresoc.v:118507.3-118527.6" + wire $1\oe_ok[0:0] + attribute \src "libresoc.v:118486.3-118506.6" + wire $2\oe[0:0] + attribute \src "libresoc.v:118507.3-118527.6" + wire $2\oe_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire input 4 \DIV_OE + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 input 1 \DIV_internal_op + attribute \src "libresoc.v:118395.7-118395.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 2 \oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 3 \oe_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" + wire width 2 input 5 \sel_in + attribute \src "libresoc.v:118395.7-118395.20" + process $proc$libresoc.v:118395$4666 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:118486.3-118506.6" + process $proc$libresoc.v:118486$4664 + assign { } { } + assign { } { } + assign $0\oe[0:0] $1\oe[0:0] + attribute \src "libresoc.v:118487.5-118487.29" + switch \initial + attribute \src "libresoc.v:118487.9-118487.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:451" + switch \DIV_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 + assign $1\oe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\oe[0:0] $2\oe[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:468" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $2\oe[0:0] \DIV_OE + case + assign $2\oe[0:0] 1'0 + end + end + sync always + update \oe $0\oe[0:0] + end + attribute \src "libresoc.v:118507.3-118527.6" + process $proc$libresoc.v:118507$4665 + assign { } { } + assign { } { } + assign $0\oe_ok[0:0] $1\oe_ok[0:0] + attribute \src "libresoc.v:118508.5-118508.29" + switch \initial + attribute \src "libresoc.v:118508.9-118508.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:451" + switch \DIV_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 + assign $1\oe_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\oe_ok[0:0] $2\oe_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:468" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $2\oe_ok[0:0] 1'1 + case + assign $2\oe_ok[0:0] 1'0 + end + end + sync always + update \oe_ok $0\oe_ok[0:0] + end +end +attribute \src "libresoc.v:118532.1-118666.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_MUL.dec_oe" +attribute \generator "nMigen" +module \dec_oe$179 + attribute \src "libresoc.v:118533.7-118533.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:118624.3-118644.6" + wire $0\oe[0:0] + attribute \src "libresoc.v:118645.3-118665.6" + wire $0\oe_ok[0:0] + attribute \src "libresoc.v:118624.3-118644.6" + wire $1\oe[0:0] + attribute \src "libresoc.v:118645.3-118665.6" + wire $1\oe_ok[0:0] + attribute \src "libresoc.v:118624.3-118644.6" + wire $2\oe[0:0] + attribute \src "libresoc.v:118645.3-118665.6" + wire $2\oe_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire input 4 \MUL_OE + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 input 1 \MUL_internal_op + attribute \src "libresoc.v:118533.7-118533.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 2 \oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 3 \oe_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" + wire width 2 input 5 \sel_in + attribute \src "libresoc.v:118533.7-118533.20" + process $proc$libresoc.v:118533$4669 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:118624.3-118644.6" + process $proc$libresoc.v:118624$4667 + assign { } { } + assign { } { } + assign $0\oe[0:0] $1\oe[0:0] + attribute \src "libresoc.v:118625.5-118625.29" + switch \initial + attribute \src "libresoc.v:118625.9-118625.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:451" + switch \MUL_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 + assign $1\oe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\oe[0:0] $2\oe[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:468" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $2\oe[0:0] \MUL_OE + case + assign $2\oe[0:0] 1'0 + end + end + sync always + update \oe $0\oe[0:0] + end + attribute \src "libresoc.v:118645.3-118665.6" + process $proc$libresoc.v:118645$4668 + assign { } { } + assign { } { } + assign $0\oe_ok[0:0] $1\oe_ok[0:0] + attribute \src "libresoc.v:118646.5-118646.29" + switch \initial + attribute \src "libresoc.v:118646.9-118646.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:451" + switch \MUL_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 + assign $1\oe_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\oe_ok[0:0] $2\oe_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:468" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $2\oe_ok[0:0] 1'1 + case + assign $2\oe_ok[0:0] 1'0 + end + end + sync always + update \oe_ok $0\oe_ok[0:0] + end +end +attribute \src "libresoc.v:118670.1-118804.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_SHIFT_ROT.dec_oe" +attribute \generator "nMigen" +module \dec_oe$187 + attribute \src "libresoc.v:118671.7-118671.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:118762.3-118782.6" + wire $0\oe[0:0] + attribute \src "libresoc.v:118783.3-118803.6" + wire $0\oe_ok[0:0] + attribute \src "libresoc.v:118762.3-118782.6" + wire $1\oe[0:0] + attribute \src "libresoc.v:118783.3-118803.6" + wire $1\oe_ok[0:0] + attribute \src "libresoc.v:118762.3-118782.6" + wire $2\oe[0:0] + attribute \src "libresoc.v:118783.3-118803.6" + wire $2\oe_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire input 4 \SHIFT_ROT_OE + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 input 1 \SHIFT_ROT_internal_op + attribute \src "libresoc.v:118671.7-118671.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 2 \oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 3 \oe_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" + wire width 2 input 5 \sel_in + attribute \src "libresoc.v:118671.7-118671.20" + process $proc$libresoc.v:118671$4672 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:118762.3-118782.6" + process $proc$libresoc.v:118762$4670 + assign { } { } + assign { } { } + assign $0\oe[0:0] $1\oe[0:0] + attribute \src "libresoc.v:118763.5-118763.29" + switch \initial + attribute \src "libresoc.v:118763.9-118763.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:451" + switch \SHIFT_ROT_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 + assign $1\oe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\oe[0:0] $2\oe[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:468" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $2\oe[0:0] \SHIFT_ROT_OE + case + assign $2\oe[0:0] 1'0 + end + end + sync always + update \oe $0\oe[0:0] + end + attribute \src "libresoc.v:118783.3-118803.6" + process $proc$libresoc.v:118783$4671 + assign { } { } + assign { } { } + assign $0\oe_ok[0:0] $1\oe_ok[0:0] + attribute \src "libresoc.v:118784.5-118784.29" + switch \initial + attribute \src "libresoc.v:118784.9-118784.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:451" + switch \SHIFT_ROT_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 + assign $1\oe_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\oe_ok[0:0] $2\oe_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:468" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $2\oe_ok[0:0] 1'1 + case + assign $2\oe_ok[0:0] 1'0 + end + end + sync always + update \oe_ok $0\oe_ok[0:0] + end +end +attribute \src "libresoc.v:118808.1-118942.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_LDST.dec_oe" +attribute \generator "nMigen" +module \dec_oe$195 + attribute \src "libresoc.v:118809.7-118809.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:118900.3-118920.6" + wire $0\oe[0:0] + attribute \src "libresoc.v:118921.3-118941.6" + wire $0\oe_ok[0:0] + attribute \src "libresoc.v:118900.3-118920.6" + wire $1\oe[0:0] + attribute \src "libresoc.v:118921.3-118941.6" + wire $1\oe_ok[0:0] + attribute \src "libresoc.v:118900.3-118920.6" + wire $2\oe[0:0] + attribute \src "libresoc.v:118921.3-118941.6" + wire $2\oe_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire input 4 \LDST_OE + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 input 1 \LDST_internal_op + attribute \src "libresoc.v:118809.7-118809.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 2 \oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 3 \oe_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" + wire width 2 input 5 \sel_in + attribute \src "libresoc.v:118809.7-118809.20" + process $proc$libresoc.v:118809$4675 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:118900.3-118920.6" + process $proc$libresoc.v:118900$4673 + assign { } { } + assign { } { } + assign $0\oe[0:0] $1\oe[0:0] + attribute \src "libresoc.v:118901.5-118901.29" + switch \initial + attribute \src "libresoc.v:118901.9-118901.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:451" + switch \LDST_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 + assign $1\oe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\oe[0:0] $2\oe[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:468" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $2\oe[0:0] \LDST_OE + case + assign $2\oe[0:0] 1'0 + end + end + sync always + update \oe $0\oe[0:0] + end + attribute \src "libresoc.v:118921.3-118941.6" + process $proc$libresoc.v:118921$4674 + assign { } { } + assign { } { } + assign $0\oe_ok[0:0] $1\oe_ok[0:0] + attribute \src "libresoc.v:118922.5-118922.29" + switch \initial + attribute \src "libresoc.v:118922.9-118922.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:451" + switch \LDST_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 + assign $1\oe_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\oe_ok[0:0] $2\oe_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:468" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $2\oe_ok[0:0] 1'1 + case + assign $2\oe_ok[0:0] 1'0 + end + end + sync always + update \oe_ok $0\oe_ok[0:0] + end +end +attribute \src "libresoc.v:118946.1-119080.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.dec2.dec_oe" +attribute \generator "nMigen" +module \dec_oe$204 + attribute \src "libresoc.v:118947.7-118947.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:119038.3-119058.6" + wire $0\oe[0:0] + attribute \src "libresoc.v:119059.3-119079.6" + wire $0\oe_ok[0:0] + attribute \src "libresoc.v:119038.3-119058.6" + wire $1\oe[0:0] + attribute \src "libresoc.v:119059.3-119079.6" + wire $1\oe_ok[0:0] + attribute \src "libresoc.v:119038.3-119058.6" + wire $2\oe[0:0] + attribute \src "libresoc.v:119059.3-119079.6" + wire $2\oe_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire input 4 \OE + attribute \src "libresoc.v:118947.7-118947.15" + wire \initial + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 input 1 \internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 2 \oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 3 \oe_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" + wire width 2 input 5 \sel_in + attribute \src "libresoc.v:118947.7-118947.20" + process $proc$libresoc.v:118947$4678 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:119038.3-119058.6" + process $proc$libresoc.v:119038$4676 + assign { } { } + assign { } { } + assign $0\oe[0:0] $1\oe[0:0] + attribute \src "libresoc.v:119039.5-119039.29" + switch \initial + attribute \src "libresoc.v:119039.9-119039.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:451" + switch \internal_op + attribute \src "libresoc.v:0.0-0.0" + case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 + assign $1\oe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\oe[0:0] $2\oe[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:468" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $2\oe[0:0] \OE + case + assign $2\oe[0:0] 1'0 + end + end + sync always + update \oe $0\oe[0:0] + end + attribute \src "libresoc.v:119059.3-119079.6" + process $proc$libresoc.v:119059$4677 + assign { } { } + assign { } { } + assign $0\oe_ok[0:0] $1\oe_ok[0:0] + attribute \src "libresoc.v:119060.5-119060.29" + switch \initial + attribute \src "libresoc.v:119060.9-119060.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:451" + switch \internal_op + attribute \src "libresoc.v:0.0-0.0" + case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 + assign $1\oe_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\oe_ok[0:0] $2\oe_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:468" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $2\oe_ok[0:0] 1'1 + case + assign $2\oe_ok[0:0] 1'0 + end + end + sync always + update \oe_ok $0\oe_ok[0:0] + end +end +attribute \src "libresoc.v:119084.1-119138.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_ALU.dec_rc" +attribute \generator "nMigen" +module \dec_rc + attribute \src "libresoc.v:119085.7-119085.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:119100.3-119118.6" + wire $0\rc[0:0] + attribute \src "libresoc.v:119119.3-119137.6" + wire $0\rc_ok[0:0] + attribute \src "libresoc.v:119100.3-119118.6" + wire $1\rc[0:0] + attribute \src "libresoc.v:119119.3-119137.6" + wire $1\rc_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire input 3 \ALU_Rc + attribute \src "libresoc.v:119085.7-119085.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 1 \rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 2 \rc_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:405" + wire width 2 input 4 \sel_in + attribute \src "libresoc.v:119085.7-119085.20" + process $proc$libresoc.v:119085$4681 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:119100.3-119118.6" + process $proc$libresoc.v:119100$4679 + assign { } { } + assign { } { } + assign $0\rc[0:0] $1\rc[0:0] + attribute \src "libresoc.v:119101.5-119101.29" + switch \initial + attribute \src "libresoc.v:119101.9-119101.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:414" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\rc[0:0] \ALU_Rc + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\rc[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\rc[0:0] 1'0 + case + assign $1\rc[0:0] 1'0 + end + sync always + update \rc $0\rc[0:0] + end + attribute \src "libresoc.v:119119.3-119137.6" + process $proc$libresoc.v:119119$4680 + assign { } { } + assign { } { } + assign $0\rc_ok[0:0] $1\rc_ok[0:0] + attribute \src "libresoc.v:119120.5-119120.29" + switch \initial + attribute \src "libresoc.v:119120.9-119120.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:414" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\rc_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\rc_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\rc_ok[0:0] 1'1 + case + assign $1\rc_ok[0:0] 1'0 + end + sync always + update \rc_ok $0\rc_ok[0:0] + end +end +attribute \src "libresoc.v:119142.1-119195.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_CR.dec_rc" +attribute \generator "nMigen" +module \dec_rc$138 + attribute \src "libresoc.v:119143.7-119143.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:119157.3-119175.6" + wire $0\rc[0:0] + attribute \src "libresoc.v:119176.3-119194.6" + wire $0\rc_ok[0:0] + attribute \src "libresoc.v:119157.3-119175.6" + wire $1\rc[0:0] + attribute \src "libresoc.v:119176.3-119194.6" + wire $1\rc_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire input 2 \CR_Rc + attribute \src "libresoc.v:119143.7-119143.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 1 \rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \rc_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:405" + wire width 2 input 3 \sel_in + attribute \src "libresoc.v:119143.7-119143.20" + process $proc$libresoc.v:119143$4684 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:119157.3-119175.6" + process $proc$libresoc.v:119157$4682 + assign { } { } + assign { } { } + assign $0\rc[0:0] $1\rc[0:0] + attribute \src "libresoc.v:119158.5-119158.29" + switch \initial + attribute \src "libresoc.v:119158.9-119158.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:414" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\rc[0:0] \CR_Rc + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\rc[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\rc[0:0] 1'0 + case + assign $1\rc[0:0] 1'0 + end + sync always + update \rc $0\rc[0:0] + end + attribute \src "libresoc.v:119176.3-119194.6" + process $proc$libresoc.v:119176$4683 + assign { } { } + assign { } { } + assign $0\rc_ok[0:0] $1\rc_ok[0:0] + attribute \src "libresoc.v:119177.5-119177.29" + switch \initial + attribute \src "libresoc.v:119177.9-119177.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:414" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\rc_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\rc_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\rc_ok[0:0] 1'1 + case + assign $1\rc_ok[0:0] 1'0 + end + sync always + update \rc_ok $0\rc_ok[0:0] + end +end +attribute \src "libresoc.v:119199.1-119252.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_BRANCH.dec_rc" +attribute \generator "nMigen" +module \dec_rc$145 + attribute \src "libresoc.v:119200.7-119200.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:119214.3-119232.6" + wire $0\rc[0:0] + attribute \src "libresoc.v:119233.3-119251.6" + wire $0\rc_ok[0:0] + attribute \src "libresoc.v:119214.3-119232.6" + wire $1\rc[0:0] + attribute \src "libresoc.v:119233.3-119251.6" + wire $1\rc_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire input 2 \BRANCH_Rc + attribute \src "libresoc.v:119200.7-119200.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 1 \rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \rc_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:405" + wire width 2 input 3 \sel_in + attribute \src "libresoc.v:119200.7-119200.20" + process $proc$libresoc.v:119200$4687 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:119214.3-119232.6" + process $proc$libresoc.v:119214$4685 + assign { } { } + assign { } { } + assign $0\rc[0:0] $1\rc[0:0] + attribute \src "libresoc.v:119215.5-119215.29" + switch \initial + attribute \src "libresoc.v:119215.9-119215.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:414" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\rc[0:0] \BRANCH_Rc + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\rc[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\rc[0:0] 1'0 + case + assign $1\rc[0:0] 1'0 + end + sync always + update \rc $0\rc[0:0] + end + attribute \src "libresoc.v:119233.3-119251.6" + process $proc$libresoc.v:119233$4686 + assign { } { } + assign { } { } + assign $0\rc_ok[0:0] $1\rc_ok[0:0] + attribute \src "libresoc.v:119234.5-119234.29" + switch \initial + attribute \src "libresoc.v:119234.9-119234.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:414" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\rc_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\rc_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\rc_ok[0:0] 1'1 + case + assign $1\rc_ok[0:0] 1'0 + end + sync always + update \rc_ok $0\rc_ok[0:0] + end +end +attribute \src "libresoc.v:119256.1-119310.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_LOGICAL.dec_rc" +attribute \generator "nMigen" +module \dec_rc$153 + attribute \src "libresoc.v:119257.7-119257.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:119272.3-119290.6" + wire $0\rc[0:0] + attribute \src "libresoc.v:119291.3-119309.6" + wire $0\rc_ok[0:0] + attribute \src "libresoc.v:119272.3-119290.6" + wire $1\rc[0:0] + attribute \src "libresoc.v:119291.3-119309.6" + wire $1\rc_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire input 3 \LOGICAL_Rc + attribute \src "libresoc.v:119257.7-119257.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 1 \rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 2 \rc_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:405" + wire width 2 input 4 \sel_in + attribute \src "libresoc.v:119257.7-119257.20" + process $proc$libresoc.v:119257$4690 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:119272.3-119290.6" + process $proc$libresoc.v:119272$4688 + assign { } { } + assign { } { } + assign $0\rc[0:0] $1\rc[0:0] + attribute \src "libresoc.v:119273.5-119273.29" + switch \initial + attribute \src "libresoc.v:119273.9-119273.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:414" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\rc[0:0] \LOGICAL_Rc + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\rc[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\rc[0:0] 1'0 + case + assign $1\rc[0:0] 1'0 + end + sync always + update \rc $0\rc[0:0] + end + attribute \src "libresoc.v:119291.3-119309.6" + process $proc$libresoc.v:119291$4689 + assign { } { } + assign { } { } + assign $0\rc_ok[0:0] $1\rc_ok[0:0] + attribute \src "libresoc.v:119292.5-119292.29" + switch \initial + attribute \src "libresoc.v:119292.9-119292.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:414" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\rc_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\rc_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\rc_ok[0:0] 1'1 + case + assign $1\rc_ok[0:0] 1'0 + end + sync always + update \rc_ok $0\rc_ok[0:0] + end +end +attribute \src "libresoc.v:119314.1-119367.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_SPR.dec_rc" +attribute \generator "nMigen" +module \dec_rc$162 + attribute \src "libresoc.v:119315.7-119315.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:119329.3-119347.6" + wire $0\rc[0:0] + attribute \src "libresoc.v:119348.3-119366.6" + wire $0\rc_ok[0:0] + attribute \src "libresoc.v:119329.3-119347.6" + wire $1\rc[0:0] + attribute \src "libresoc.v:119348.3-119366.6" + wire $1\rc_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire input 2 \SPR_Rc + attribute \src "libresoc.v:119315.7-119315.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 1 \rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \rc_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:405" + wire width 2 input 3 \sel_in + attribute \src "libresoc.v:119315.7-119315.20" + process $proc$libresoc.v:119315$4693 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:119329.3-119347.6" + process $proc$libresoc.v:119329$4691 + assign { } { } + assign { } { } + assign $0\rc[0:0] $1\rc[0:0] + attribute \src "libresoc.v:119330.5-119330.29" + switch \initial + attribute \src "libresoc.v:119330.9-119330.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:414" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\rc[0:0] \SPR_Rc + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\rc[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\rc[0:0] 1'0 + case + assign $1\rc[0:0] 1'0 + end + sync always + update \rc $0\rc[0:0] + end + attribute \src "libresoc.v:119348.3-119366.6" + process $proc$libresoc.v:119348$4692 + assign { } { } + assign { } { } + assign $0\rc_ok[0:0] $1\rc_ok[0:0] + attribute \src "libresoc.v:119349.5-119349.29" + switch \initial + attribute \src "libresoc.v:119349.9-119349.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:414" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\rc_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\rc_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\rc_ok[0:0] 1'1 + case + assign $1\rc_ok[0:0] 1'0 + end + sync always + update \rc_ok $0\rc_ok[0:0] + end +end +attribute \src "libresoc.v:119371.1-119425.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_DIV.dec_rc" +attribute \generator "nMigen" +module \dec_rc$169 + attribute \src "libresoc.v:119372.7-119372.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:119387.3-119405.6" + wire $0\rc[0:0] + attribute \src "libresoc.v:119406.3-119424.6" + wire $0\rc_ok[0:0] + attribute \src "libresoc.v:119387.3-119405.6" + wire $1\rc[0:0] + attribute \src "libresoc.v:119406.3-119424.6" + wire $1\rc_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire input 3 \DIV_Rc + attribute \src "libresoc.v:119372.7-119372.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 1 \rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 2 \rc_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:405" + wire width 2 input 4 \sel_in + attribute \src "libresoc.v:119372.7-119372.20" + process $proc$libresoc.v:119372$4696 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:119387.3-119405.6" + process $proc$libresoc.v:119387$4694 + assign { } { } + assign { } { } + assign $0\rc[0:0] $1\rc[0:0] + attribute \src "libresoc.v:119388.5-119388.29" + switch \initial + attribute \src "libresoc.v:119388.9-119388.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:414" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\rc[0:0] \DIV_Rc + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\rc[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\rc[0:0] 1'0 + case + assign $1\rc[0:0] 1'0 + end + sync always + update \rc $0\rc[0:0] + end + attribute \src "libresoc.v:119406.3-119424.6" + process $proc$libresoc.v:119406$4695 + assign { } { } + assign { } { } + assign $0\rc_ok[0:0] $1\rc_ok[0:0] + attribute \src "libresoc.v:119407.5-119407.29" + switch \initial + attribute \src "libresoc.v:119407.9-119407.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:414" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\rc_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\rc_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\rc_ok[0:0] 1'1 + case + assign $1\rc_ok[0:0] 1'0 + end + sync always + update \rc_ok $0\rc_ok[0:0] + end +end +attribute \src "libresoc.v:119429.1-119483.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_MUL.dec_rc" +attribute \generator "nMigen" +module \dec_rc$178 + attribute \src "libresoc.v:119430.7-119430.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:119445.3-119463.6" + wire $0\rc[0:0] + attribute \src "libresoc.v:119464.3-119482.6" + wire $0\rc_ok[0:0] + attribute \src "libresoc.v:119445.3-119463.6" + wire $1\rc[0:0] + attribute \src "libresoc.v:119464.3-119482.6" + wire $1\rc_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire input 3 \MUL_Rc + attribute \src "libresoc.v:119430.7-119430.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 1 \rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 2 \rc_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:405" + wire width 2 input 4 \sel_in + attribute \src "libresoc.v:119430.7-119430.20" + process $proc$libresoc.v:119430$4699 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:119445.3-119463.6" + process $proc$libresoc.v:119445$4697 + assign { } { } + assign { } { } + assign $0\rc[0:0] $1\rc[0:0] + attribute \src "libresoc.v:119446.5-119446.29" + switch \initial + attribute \src "libresoc.v:119446.9-119446.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:414" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\rc[0:0] \MUL_Rc + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\rc[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\rc[0:0] 1'0 + case + assign $1\rc[0:0] 1'0 + end + sync always + update \rc $0\rc[0:0] + end + attribute \src "libresoc.v:119464.3-119482.6" + process $proc$libresoc.v:119464$4698 + assign { } { } + assign { } { } + assign $0\rc_ok[0:0] $1\rc_ok[0:0] + attribute \src "libresoc.v:119465.5-119465.29" + switch \initial + attribute \src "libresoc.v:119465.9-119465.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:414" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\rc_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\rc_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\rc_ok[0:0] 1'1 + case + assign $1\rc_ok[0:0] 1'0 + end + sync always + update \rc_ok $0\rc_ok[0:0] + end +end +attribute \src "libresoc.v:119487.1-119541.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_SHIFT_ROT.dec_rc" +attribute \generator "nMigen" +module \dec_rc$186 + attribute \src "libresoc.v:119488.7-119488.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:119503.3-119521.6" + wire $0\rc[0:0] + attribute \src "libresoc.v:119522.3-119540.6" + wire $0\rc_ok[0:0] + attribute \src "libresoc.v:119503.3-119521.6" + wire $1\rc[0:0] + attribute \src "libresoc.v:119522.3-119540.6" + wire $1\rc_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire input 3 \SHIFT_ROT_Rc + attribute \src "libresoc.v:119488.7-119488.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 1 \rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 2 \rc_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:405" + wire width 2 input 4 \sel_in + attribute \src "libresoc.v:119488.7-119488.20" + process $proc$libresoc.v:119488$4702 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:119503.3-119521.6" + process $proc$libresoc.v:119503$4700 + assign { } { } + assign { } { } + assign $0\rc[0:0] $1\rc[0:0] + attribute \src "libresoc.v:119504.5-119504.29" + switch \initial + attribute \src "libresoc.v:119504.9-119504.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:414" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\rc[0:0] \SHIFT_ROT_Rc + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\rc[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\rc[0:0] 1'0 + case + assign $1\rc[0:0] 1'0 + end + sync always + update \rc $0\rc[0:0] + end + attribute \src "libresoc.v:119522.3-119540.6" + process $proc$libresoc.v:119522$4701 + assign { } { } + assign { } { } + assign $0\rc_ok[0:0] $1\rc_ok[0:0] + attribute \src "libresoc.v:119523.5-119523.29" + switch \initial + attribute \src "libresoc.v:119523.9-119523.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:414" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\rc_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\rc_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\rc_ok[0:0] 1'1 + case + assign $1\rc_ok[0:0] 1'0 + end + sync always + update \rc_ok $0\rc_ok[0:0] + end +end +attribute \src "libresoc.v:119545.1-119599.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_LDST.dec_rc" +attribute \generator "nMigen" +module \dec_rc$194 + attribute \src "libresoc.v:119546.7-119546.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:119561.3-119579.6" + wire $0\rc[0:0] + attribute \src "libresoc.v:119580.3-119598.6" + wire $0\rc_ok[0:0] + attribute \src "libresoc.v:119561.3-119579.6" + wire $1\rc[0:0] + attribute \src "libresoc.v:119580.3-119598.6" + wire $1\rc_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire input 3 \LDST_Rc + attribute \src "libresoc.v:119546.7-119546.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 1 \rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 2 \rc_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:405" + wire width 2 input 4 \sel_in + attribute \src "libresoc.v:119546.7-119546.20" + process $proc$libresoc.v:119546$4705 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:119561.3-119579.6" + process $proc$libresoc.v:119561$4703 + assign { } { } + assign { } { } + assign $0\rc[0:0] $1\rc[0:0] + attribute \src "libresoc.v:119562.5-119562.29" + switch \initial + attribute \src "libresoc.v:119562.9-119562.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:414" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\rc[0:0] \LDST_Rc + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\rc[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\rc[0:0] 1'0 + case + assign $1\rc[0:0] 1'0 + end + sync always + update \rc $0\rc[0:0] + end + attribute \src "libresoc.v:119580.3-119598.6" + process $proc$libresoc.v:119580$4704 + assign { } { } + assign { } { } + assign $0\rc_ok[0:0] $1\rc_ok[0:0] + attribute \src "libresoc.v:119581.5-119581.29" + switch \initial + attribute \src "libresoc.v:119581.9-119581.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:414" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\rc_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\rc_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\rc_ok[0:0] 1'1 + case + assign $1\rc_ok[0:0] 1'0 + end + sync always + update \rc_ok $0\rc_ok[0:0] + end +end +attribute \src "libresoc.v:119603.1-119657.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.dec2.dec_rc" +attribute \generator "nMigen" +module \dec_rc$203 + attribute \src "libresoc.v:119604.7-119604.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:119619.3-119637.6" + wire $0\rc[0:0] + attribute \src "libresoc.v:119638.3-119656.6" + wire $0\rc_ok[0:0] + attribute \src "libresoc.v:119619.3-119637.6" + wire $1\rc[0:0] + attribute \src "libresoc.v:119638.3-119656.6" + wire $1\rc_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire input 3 \Rc + attribute \src "libresoc.v:119604.7-119604.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 1 \rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 2 \rc_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:405" + wire width 2 input 4 \sel_in + attribute \src "libresoc.v:119604.7-119604.20" + process $proc$libresoc.v:119604$4708 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:119619.3-119637.6" + process $proc$libresoc.v:119619$4706 + assign { } { } + assign { } { } + assign $0\rc[0:0] $1\rc[0:0] + attribute \src "libresoc.v:119620.5-119620.29" + switch \initial + attribute \src "libresoc.v:119620.9-119620.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:414" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\rc[0:0] \Rc + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\rc[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\rc[0:0] 1'0 + case + assign $1\rc[0:0] 1'0 + end + sync always + update \rc $0\rc[0:0] + end + attribute \src "libresoc.v:119638.3-119656.6" + process $proc$libresoc.v:119638$4707 + assign { } { } + assign { } { } + assign $0\rc_ok[0:0] $1\rc_ok[0:0] + attribute \src "libresoc.v:119639.5-119639.29" + switch \initial + attribute \src "libresoc.v:119639.9-119639.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:414" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\rc_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\rc_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\rc_ok[0:0] 1'1 + case + assign $1\rc_ok[0:0] 1'0 + end + sync always + update \rc_ok $0\rc_ok[0:0] + end +end +attribute \src "libresoc.v:119661.1-120899.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.div0" +attribute \generator "nMigen" +module \div0 + attribute \src "libresoc.v:120456.3-120457.25" + wire $0\all_rd_dly[0:0] + attribute \src "libresoc.v:120643.3-120681.6" + wire width 4 $0\alu_div0_logical_op__data_len$next[3:0]$4848 + attribute \src "libresoc.v:120428.3-120429.75" + wire width 4 $0\alu_div0_logical_op__data_len[3:0] + attribute \src "libresoc.v:120643.3-120681.6" + wire width 12 $0\alu_div0_logical_op__fn_unit$next[11:0]$4849 + attribute \src "libresoc.v:120398.3-120399.73" + wire width 12 $0\alu_div0_logical_op__fn_unit[11:0] + attribute \src "libresoc.v:120643.3-120681.6" + wire width 64 $0\alu_div0_logical_op__imm_data__data$next[63:0]$4850 + attribute \src "libresoc.v:120400.3-120401.87" + wire width 64 $0\alu_div0_logical_op__imm_data__data[63:0] + attribute \src "libresoc.v:120643.3-120681.6" + wire $0\alu_div0_logical_op__imm_data__ok$next[0:0]$4851 + attribute \src "libresoc.v:120402.3-120403.83" + wire $0\alu_div0_logical_op__imm_data__ok[0:0] + attribute \src "libresoc.v:120643.3-120681.6" + wire width 2 $0\alu_div0_logical_op__input_carry$next[1:0]$4852 + attribute \src "libresoc.v:120416.3-120417.81" + wire width 2 $0\alu_div0_logical_op__input_carry[1:0] + attribute \src "libresoc.v:120643.3-120681.6" + wire width 32 $0\alu_div0_logical_op__insn$next[31:0]$4853 + attribute \src "libresoc.v:120430.3-120431.67" + wire width 32 $0\alu_div0_logical_op__insn[31:0] + attribute \src "libresoc.v:120643.3-120681.6" + wire width 7 $0\alu_div0_logical_op__insn_type$next[6:0]$4854 + attribute \src "libresoc.v:120396.3-120397.77" + wire width 7 $0\alu_div0_logical_op__insn_type[6:0] + attribute \src "libresoc.v:120643.3-120681.6" + wire $0\alu_div0_logical_op__invert_in$next[0:0]$4855 + attribute \src "libresoc.v:120412.3-120413.77" + wire $0\alu_div0_logical_op__invert_in[0:0] + attribute \src "libresoc.v:120643.3-120681.6" + wire $0\alu_div0_logical_op__invert_out$next[0:0]$4856 + attribute \src "libresoc.v:120418.3-120419.79" + wire $0\alu_div0_logical_op__invert_out[0:0] + attribute \src "libresoc.v:120643.3-120681.6" + wire $0\alu_div0_logical_op__is_32bit$next[0:0]$4857 + attribute \src "libresoc.v:120424.3-120425.75" + wire $0\alu_div0_logical_op__is_32bit[0:0] + attribute \src "libresoc.v:120643.3-120681.6" + wire $0\alu_div0_logical_op__is_signed$next[0:0]$4858 + attribute \src "libresoc.v:120426.3-120427.77" + wire $0\alu_div0_logical_op__is_signed[0:0] + attribute \src "libresoc.v:120643.3-120681.6" + wire $0\alu_div0_logical_op__oe__oe$next[0:0]$4859 + attribute \src "libresoc.v:120408.3-120409.71" + wire $0\alu_div0_logical_op__oe__oe[0:0] + attribute \src "libresoc.v:120643.3-120681.6" + wire $0\alu_div0_logical_op__oe__ok$next[0:0]$4860 + attribute \src "libresoc.v:120410.3-120411.71" + wire $0\alu_div0_logical_op__oe__ok[0:0] + attribute \src "libresoc.v:120643.3-120681.6" + wire $0\alu_div0_logical_op__output_carry$next[0:0]$4861 + attribute \src "libresoc.v:120422.3-120423.83" + wire $0\alu_div0_logical_op__output_carry[0:0] + attribute \src "libresoc.v:120643.3-120681.6" + wire $0\alu_div0_logical_op__rc__ok$next[0:0]$4862 + attribute \src "libresoc.v:120406.3-120407.71" + wire $0\alu_div0_logical_op__rc__ok[0:0] + attribute \src "libresoc.v:120643.3-120681.6" + wire $0\alu_div0_logical_op__rc__rc$next[0:0]$4863 + attribute \src "libresoc.v:120404.3-120405.71" + wire $0\alu_div0_logical_op__rc__rc[0:0] + attribute \src "libresoc.v:120643.3-120681.6" + wire $0\alu_div0_logical_op__write_cr0$next[0:0]$4864 + attribute \src "libresoc.v:120420.3-120421.77" + wire $0\alu_div0_logical_op__write_cr0[0:0] + attribute \src "libresoc.v:120643.3-120681.6" + wire $0\alu_div0_logical_op__zero_a$next[0:0]$4865 + attribute \src "libresoc.v:120414.3-120415.71" + wire $0\alu_div0_logical_op__zero_a[0:0] + attribute \src "libresoc.v:120454.3-120455.40" + wire $0\alu_done_dly[0:0] + attribute \src "libresoc.v:120809.3-120817.6" + wire $0\alu_l_r_alu$next[0:0]$4935 + attribute \src "libresoc.v:120370.3-120371.39" + wire $0\alu_l_r_alu[0:0] + attribute \src "libresoc.v:120800.3-120808.6" + wire $0\alui_l_r_alui$next[0:0]$4932 + attribute \src "libresoc.v:120372.3-120373.43" + wire $0\alui_l_r_alui[0:0] + attribute \src "libresoc.v:120682.3-120703.6" + wire width 64 $0\data_r0__o$next[63:0]$4891 + attribute \src "libresoc.v:120392.3-120393.37" + wire width 64 $0\data_r0__o[63:0] + attribute \src "libresoc.v:120682.3-120703.6" + wire $0\data_r0__o_ok$next[0:0]$4892 + attribute \src "libresoc.v:120394.3-120395.43" + wire $0\data_r0__o_ok[0:0] + attribute \src "libresoc.v:120704.3-120725.6" + wire width 4 $0\data_r1__cr_a$next[3:0]$4899 + attribute \src "libresoc.v:120388.3-120389.43" + wire width 4 $0\data_r1__cr_a[3:0] + attribute \src "libresoc.v:120704.3-120725.6" + wire $0\data_r1__cr_a_ok$next[0:0]$4900 + attribute \src "libresoc.v:120390.3-120391.49" + wire $0\data_r1__cr_a_ok[0:0] + attribute \src "libresoc.v:120726.3-120747.6" + wire width 2 $0\data_r2__xer_ov$next[1:0]$4907 + attribute \src "libresoc.v:120384.3-120385.47" + wire width 2 $0\data_r2__xer_ov[1:0] + attribute \src "libresoc.v:120726.3-120747.6" + wire $0\data_r2__xer_ov_ok$next[0:0]$4908 + attribute \src "libresoc.v:120386.3-120387.53" + wire $0\data_r2__xer_ov_ok[0:0] + attribute \src "libresoc.v:120748.3-120769.6" + wire $0\data_r3__xer_so$next[0:0]$4915 + attribute \src "libresoc.v:120380.3-120381.47" + wire $0\data_r3__xer_so[0:0] + attribute \src "libresoc.v:120748.3-120769.6" + wire $0\data_r3__xer_so_ok$next[0:0]$4916 + attribute \src "libresoc.v:120382.3-120383.53" + wire $0\data_r3__xer_so_ok[0:0] + attribute \src "libresoc.v:120818.3-120827.6" + wire width 64 $0\dest1_o[63:0] + attribute \src "libresoc.v:120828.3-120837.6" + wire width 4 $0\dest2_o[3:0] + attribute \src "libresoc.v:120838.3-120847.6" + wire width 2 $0\dest3_o[1:0] + attribute \src "libresoc.v:120848.3-120857.6" + wire $0\dest4_o[0:0] + attribute \src "libresoc.v:119662.7-119662.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:120598.3-120606.6" + wire $0\opc_l_r_opc$next[0:0]$4833 + attribute \src "libresoc.v:120440.3-120441.39" + wire $0\opc_l_r_opc[0:0] + attribute \src "libresoc.v:120589.3-120597.6" + wire $0\opc_l_s_opc$next[0:0]$4830 + attribute \src "libresoc.v:120442.3-120443.39" + wire $0\opc_l_s_opc[0:0] + attribute \src "libresoc.v:120858.3-120866.6" + wire width 4 $0\prev_wr_go$next[3:0]$4942 + attribute \src "libresoc.v:120452.3-120453.37" + wire width 4 $0\prev_wr_go[3:0] + attribute \src "libresoc.v:120543.3-120552.6" + wire $0\req_done[0:0] + attribute \src "libresoc.v:120634.3-120642.6" + wire width 4 $0\req_l_r_req$next[3:0]$4845 + attribute \src "libresoc.v:120432.3-120433.39" + wire width 4 $0\req_l_r_req[3:0] + attribute \src "libresoc.v:120625.3-120633.6" + wire width 4 $0\req_l_s_req$next[3:0]$4842 + attribute \src "libresoc.v:120434.3-120435.39" + wire width 4 $0\req_l_s_req[3:0] + attribute \src "libresoc.v:120562.3-120570.6" + wire $0\rok_l_r_rdok$next[0:0]$4821 + attribute \src "libresoc.v:120448.3-120449.41" + wire $0\rok_l_r_rdok[0:0] + attribute \src "libresoc.v:120553.3-120561.6" + wire $0\rok_l_s_rdok$next[0:0]$4818 + attribute \src "libresoc.v:120450.3-120451.41" + wire $0\rok_l_s_rdok[0:0] + attribute \src "libresoc.v:120580.3-120588.6" + wire $0\rst_l_r_rst$next[0:0]$4827 + attribute \src "libresoc.v:120444.3-120445.39" + wire $0\rst_l_r_rst[0:0] + attribute \src "libresoc.v:120571.3-120579.6" + wire $0\rst_l_s_rst$next[0:0]$4824 + attribute \src "libresoc.v:120446.3-120447.39" + wire $0\rst_l_s_rst[0:0] + attribute \src "libresoc.v:120616.3-120624.6" + wire width 3 $0\src_l_r_src$next[2:0]$4839 + attribute \src "libresoc.v:120436.3-120437.39" + wire width 3 $0\src_l_r_src[2:0] + attribute \src "libresoc.v:120607.3-120615.6" + wire width 3 $0\src_l_s_src$next[2:0]$4836 + attribute \src "libresoc.v:120438.3-120439.39" + wire width 3 $0\src_l_s_src[2:0] + attribute \src "libresoc.v:120770.3-120779.6" + wire width 64 $0\src_r0$next[63:0]$4923 + attribute \src "libresoc.v:120378.3-120379.29" + wire width 64 $0\src_r0[63:0] + attribute \src "libresoc.v:120780.3-120789.6" + wire width 64 $0\src_r1$next[63:0]$4926 + attribute \src "libresoc.v:120376.3-120377.29" + wire width 64 $0\src_r1[63:0] + attribute \src "libresoc.v:120790.3-120799.6" + wire $0\src_r2$next[0:0]$4929 + attribute \src "libresoc.v:120374.3-120375.29" + wire $0\src_r2[0:0] + attribute \src "libresoc.v:119792.7-119792.24" + wire $1\all_rd_dly[0:0] + attribute \src "libresoc.v:120643.3-120681.6" + wire width 4 $1\alu_div0_logical_op__data_len$next[3:0]$4866 + attribute \src "libresoc.v:119802.13-119802.49" + wire width 4 $1\alu_div0_logical_op__data_len[3:0] + attribute \src "libresoc.v:120643.3-120681.6" + wire width 12 $1\alu_div0_logical_op__fn_unit$next[11:0]$4867 + attribute \src "libresoc.v:119819.14-119819.52" + wire width 12 $1\alu_div0_logical_op__fn_unit[11:0] + attribute \src "libresoc.v:120643.3-120681.6" + wire width 64 $1\alu_div0_logical_op__imm_data__data$next[63:0]$4868 + attribute \src "libresoc.v:119823.14-119823.72" + wire width 64 $1\alu_div0_logical_op__imm_data__data[63:0] + attribute \src "libresoc.v:120643.3-120681.6" + wire $1\alu_div0_logical_op__imm_data__ok$next[0:0]$4869 + attribute \src "libresoc.v:119827.7-119827.47" + wire $1\alu_div0_logical_op__imm_data__ok[0:0] + attribute \src "libresoc.v:120643.3-120681.6" + wire width 2 $1\alu_div0_logical_op__input_carry$next[1:0]$4870 + attribute \src "libresoc.v:119835.13-119835.52" + wire width 2 $1\alu_div0_logical_op__input_carry[1:0] + attribute \src "libresoc.v:120643.3-120681.6" + wire width 32 $1\alu_div0_logical_op__insn$next[31:0]$4871 + attribute \src "libresoc.v:119839.14-119839.47" + wire width 32 $1\alu_div0_logical_op__insn[31:0] + attribute \src "libresoc.v:120643.3-120681.6" + wire width 7 $1\alu_div0_logical_op__insn_type$next[6:0]$4872 + attribute \src "libresoc.v:119917.13-119917.51" + wire width 7 $1\alu_div0_logical_op__insn_type[6:0] + attribute \src "libresoc.v:120643.3-120681.6" + wire $1\alu_div0_logical_op__invert_in$next[0:0]$4873 + attribute \src "libresoc.v:119921.7-119921.44" + wire $1\alu_div0_logical_op__invert_in[0:0] + attribute \src "libresoc.v:120643.3-120681.6" + wire $1\alu_div0_logical_op__invert_out$next[0:0]$4874 + attribute \src "libresoc.v:119925.7-119925.45" + wire $1\alu_div0_logical_op__invert_out[0:0] + attribute \src "libresoc.v:120643.3-120681.6" + wire $1\alu_div0_logical_op__is_32bit$next[0:0]$4875 + attribute \src "libresoc.v:119929.7-119929.43" + wire $1\alu_div0_logical_op__is_32bit[0:0] + attribute \src "libresoc.v:120643.3-120681.6" + wire $1\alu_div0_logical_op__is_signed$next[0:0]$4876 + attribute \src "libresoc.v:119933.7-119933.44" + wire $1\alu_div0_logical_op__is_signed[0:0] + attribute \src "libresoc.v:120643.3-120681.6" + wire $1\alu_div0_logical_op__oe__oe$next[0:0]$4877 + attribute \src "libresoc.v:119937.7-119937.41" + wire $1\alu_div0_logical_op__oe__oe[0:0] + attribute \src "libresoc.v:120643.3-120681.6" + wire $1\alu_div0_logical_op__oe__ok$next[0:0]$4878 + attribute \src "libresoc.v:119941.7-119941.41" + wire $1\alu_div0_logical_op__oe__ok[0:0] + attribute \src "libresoc.v:120643.3-120681.6" + wire $1\alu_div0_logical_op__output_carry$next[0:0]$4879 + attribute \src "libresoc.v:119945.7-119945.47" + wire $1\alu_div0_logical_op__output_carry[0:0] + attribute \src "libresoc.v:120643.3-120681.6" + wire $1\alu_div0_logical_op__rc__ok$next[0:0]$4880 + attribute \src "libresoc.v:119949.7-119949.41" + wire $1\alu_div0_logical_op__rc__ok[0:0] + attribute \src "libresoc.v:120643.3-120681.6" + wire $1\alu_div0_logical_op__rc__rc$next[0:0]$4881 + attribute \src "libresoc.v:119953.7-119953.41" + wire $1\alu_div0_logical_op__rc__rc[0:0] + attribute \src "libresoc.v:120643.3-120681.6" + wire $1\alu_div0_logical_op__write_cr0$next[0:0]$4882 + attribute \src "libresoc.v:119957.7-119957.44" + wire $1\alu_div0_logical_op__write_cr0[0:0] + attribute \src "libresoc.v:120643.3-120681.6" + wire $1\alu_div0_logical_op__zero_a$next[0:0]$4883 + attribute \src "libresoc.v:119961.7-119961.41" + wire $1\alu_div0_logical_op__zero_a[0:0] + attribute \src "libresoc.v:119987.7-119987.26" + wire $1\alu_done_dly[0:0] + attribute \src "libresoc.v:120809.3-120817.6" + wire $1\alu_l_r_alu$next[0:0]$4936 + attribute \src "libresoc.v:119995.7-119995.25" + wire $1\alu_l_r_alu[0:0] + attribute \src "libresoc.v:120800.3-120808.6" + wire $1\alui_l_r_alui$next[0:0]$4933 + attribute \src "libresoc.v:120007.7-120007.27" + wire $1\alui_l_r_alui[0:0] + attribute \src "libresoc.v:120682.3-120703.6" + wire width 64 $1\data_r0__o$next[63:0]$4893 + attribute \src "libresoc.v:120041.14-120041.47" + wire width 64 $1\data_r0__o[63:0] + attribute \src "libresoc.v:120682.3-120703.6" + wire $1\data_r0__o_ok$next[0:0]$4894 + attribute \src "libresoc.v:120045.7-120045.27" + wire $1\data_r0__o_ok[0:0] + attribute \src "libresoc.v:120704.3-120725.6" + wire width 4 $1\data_r1__cr_a$next[3:0]$4901 + attribute \src "libresoc.v:120049.13-120049.33" + wire width 4 $1\data_r1__cr_a[3:0] + attribute \src "libresoc.v:120704.3-120725.6" + wire $1\data_r1__cr_a_ok$next[0:0]$4902 + attribute \src "libresoc.v:120053.7-120053.30" + wire $1\data_r1__cr_a_ok[0:0] + attribute \src "libresoc.v:120726.3-120747.6" + wire width 2 $1\data_r2__xer_ov$next[1:0]$4909 + attribute \src "libresoc.v:120057.13-120057.35" + wire width 2 $1\data_r2__xer_ov[1:0] + attribute \src "libresoc.v:120726.3-120747.6" + wire $1\data_r2__xer_ov_ok$next[0:0]$4910 + attribute \src "libresoc.v:120061.7-120061.32" + wire $1\data_r2__xer_ov_ok[0:0] + attribute \src "libresoc.v:120748.3-120769.6" + wire $1\data_r3__xer_so$next[0:0]$4917 + attribute \src "libresoc.v:120065.7-120065.29" + wire $1\data_r3__xer_so[0:0] + attribute \src "libresoc.v:120748.3-120769.6" + wire $1\data_r3__xer_so_ok$next[0:0]$4918 + attribute \src "libresoc.v:120069.7-120069.32" + wire $1\data_r3__xer_so_ok[0:0] + attribute \src "libresoc.v:120818.3-120827.6" + wire width 64 $1\dest1_o[63:0] + attribute \src "libresoc.v:120828.3-120837.6" + wire width 4 $1\dest2_o[3:0] + attribute \src "libresoc.v:120838.3-120847.6" + wire width 2 $1\dest3_o[1:0] + attribute \src "libresoc.v:120848.3-120857.6" + wire $1\dest4_o[0:0] + attribute \src "libresoc.v:120598.3-120606.6" + wire $1\opc_l_r_opc$next[0:0]$4834 + attribute \src "libresoc.v:120089.7-120089.25" + wire $1\opc_l_r_opc[0:0] + attribute \src "libresoc.v:120589.3-120597.6" + wire $1\opc_l_s_opc$next[0:0]$4831 + attribute \src "libresoc.v:120093.7-120093.25" + wire $1\opc_l_s_opc[0:0] + attribute \src "libresoc.v:120858.3-120866.6" + wire width 4 $1\prev_wr_go$next[3:0]$4943 + attribute \src "libresoc.v:120224.13-120224.30" + wire width 4 $1\prev_wr_go[3:0] + attribute \src "libresoc.v:120543.3-120552.6" + wire $1\req_done[0:0] + attribute \src "libresoc.v:120634.3-120642.6" + wire width 4 $1\req_l_r_req$next[3:0]$4846 + attribute \src "libresoc.v:120232.13-120232.31" + wire width 4 $1\req_l_r_req[3:0] + attribute \src "libresoc.v:120625.3-120633.6" + wire width 4 $1\req_l_s_req$next[3:0]$4843 + attribute \src "libresoc.v:120236.13-120236.31" + wire width 4 $1\req_l_s_req[3:0] + attribute \src "libresoc.v:120562.3-120570.6" + wire $1\rok_l_r_rdok$next[0:0]$4822 + attribute \src "libresoc.v:120248.7-120248.26" + wire $1\rok_l_r_rdok[0:0] + attribute \src "libresoc.v:120553.3-120561.6" + wire $1\rok_l_s_rdok$next[0:0]$4819 + attribute \src "libresoc.v:120252.7-120252.26" + wire $1\rok_l_s_rdok[0:0] + attribute \src "libresoc.v:120580.3-120588.6" + wire $1\rst_l_r_rst$next[0:0]$4828 + attribute \src "libresoc.v:120256.7-120256.25" + wire $1\rst_l_r_rst[0:0] + attribute \src "libresoc.v:120571.3-120579.6" + wire $1\rst_l_s_rst$next[0:0]$4825 + attribute \src "libresoc.v:120260.7-120260.25" + wire $1\rst_l_s_rst[0:0] + attribute \src "libresoc.v:120616.3-120624.6" + wire width 3 $1\src_l_r_src$next[2:0]$4840 + attribute \src "libresoc.v:120274.13-120274.31" + wire width 3 $1\src_l_r_src[2:0] + attribute \src "libresoc.v:120607.3-120615.6" + wire width 3 $1\src_l_s_src$next[2:0]$4837 + attribute \src "libresoc.v:120278.13-120278.31" + wire width 3 $1\src_l_s_src[2:0] + attribute \src "libresoc.v:120770.3-120779.6" + wire width 64 $1\src_r0$next[63:0]$4924 + attribute \src "libresoc.v:120286.14-120286.43" + wire width 64 $1\src_r0[63:0] + attribute \src "libresoc.v:120780.3-120789.6" + wire width 64 $1\src_r1$next[63:0]$4927 + attribute \src "libresoc.v:120290.14-120290.43" + wire width 64 $1\src_r1[63:0] + attribute \src "libresoc.v:120790.3-120799.6" + wire $1\src_r2$next[0:0]$4930 + attribute \src "libresoc.v:120294.7-120294.20" + wire $1\src_r2[0:0] + attribute \src "libresoc.v:120643.3-120681.6" + wire width 64 $2\alu_div0_logical_op__imm_data__data$next[63:0]$4884 + attribute \src "libresoc.v:120643.3-120681.6" + wire $2\alu_div0_logical_op__imm_data__ok$next[0:0]$4885 + attribute \src "libresoc.v:120643.3-120681.6" + wire $2\alu_div0_logical_op__oe__oe$next[0:0]$4886 + attribute \src "libresoc.v:120643.3-120681.6" + wire $2\alu_div0_logical_op__oe__ok$next[0:0]$4887 + attribute \src "libresoc.v:120643.3-120681.6" + wire $2\alu_div0_logical_op__rc__ok$next[0:0]$4888 + attribute \src "libresoc.v:120643.3-120681.6" + wire $2\alu_div0_logical_op__rc__rc$next[0:0]$4889 + attribute \src "libresoc.v:120682.3-120703.6" + wire width 64 $2\data_r0__o$next[63:0]$4895 + attribute \src "libresoc.v:120682.3-120703.6" + wire $2\data_r0__o_ok$next[0:0]$4896 + attribute \src "libresoc.v:120704.3-120725.6" + wire width 4 $2\data_r1__cr_a$next[3:0]$4903 + attribute \src "libresoc.v:120704.3-120725.6" + wire $2\data_r1__cr_a_ok$next[0:0]$4904 + attribute \src "libresoc.v:120726.3-120747.6" + wire width 2 $2\data_r2__xer_ov$next[1:0]$4911 + attribute \src "libresoc.v:120726.3-120747.6" + wire $2\data_r2__xer_ov_ok$next[0:0]$4912 + attribute \src "libresoc.v:120748.3-120769.6" + wire $2\data_r3__xer_so$next[0:0]$4919 + attribute \src "libresoc.v:120748.3-120769.6" + wire $2\data_r3__xer_so_ok$next[0:0]$4920 + attribute \src "libresoc.v:120682.3-120703.6" + wire $3\data_r0__o_ok$next[0:0]$4897 + attribute \src "libresoc.v:120704.3-120725.6" + wire $3\data_r1__cr_a_ok$next[0:0]$4905 + attribute \src "libresoc.v:120726.3-120747.6" + wire $3\data_r2__xer_ov_ok$next[0:0]$4913 + attribute \src "libresoc.v:120748.3-120769.6" + wire $3\data_r3__xer_so_ok$next[0:0]$4921 + attribute \src "libresoc.v:120309.19-120309.133" + wire width 3 $and$libresoc.v:120309$4711_Y + attribute \src "libresoc.v:120311.19-120311.115" + wire width 3 $and$libresoc.v:120311$4713_Y + attribute \src "libresoc.v:120312.18-120312.110" + wire $and$libresoc.v:120312$4714_Y + attribute \src "libresoc.v:120313.19-120313.125" + wire $and$libresoc.v:120313$4715_Y + attribute \src "libresoc.v:120314.19-120314.125" + wire $and$libresoc.v:120314$4716_Y + attribute \src "libresoc.v:120315.19-120315.125" + wire $and$libresoc.v:120315$4717_Y + attribute \src "libresoc.v:120316.19-120316.125" + wire $and$libresoc.v:120316$4718_Y + attribute \src "libresoc.v:120317.19-120317.149" + wire width 4 $and$libresoc.v:120317$4719_Y + attribute \src "libresoc.v:120318.19-120318.121" + wire width 4 $and$libresoc.v:120318$4720_Y + attribute \src "libresoc.v:120319.19-120319.127" + wire $and$libresoc.v:120319$4721_Y + attribute \src "libresoc.v:120320.19-120320.127" + wire $and$libresoc.v:120320$4722_Y + attribute \src "libresoc.v:120321.19-120321.127" + wire $and$libresoc.v:120321$4723_Y + attribute \src "libresoc.v:120322.19-120322.127" + wire $and$libresoc.v:120322$4724_Y + attribute \src "libresoc.v:120324.18-120324.98" + wire $and$libresoc.v:120324$4726_Y + attribute \src "libresoc.v:120326.18-120326.100" + wire $and$libresoc.v:120326$4728_Y + attribute \src "libresoc.v:120327.18-120327.160" + wire width 4 $and$libresoc.v:120327$4729_Y + attribute \src "libresoc.v:120329.18-120329.119" + wire width 4 $and$libresoc.v:120329$4731_Y + attribute \src "libresoc.v:120332.17-120332.123" + wire $and$libresoc.v:120332$4734_Y + attribute \src "libresoc.v:120333.18-120333.116" + wire $and$libresoc.v:120333$4735_Y + attribute \src "libresoc.v:120338.18-120338.113" + wire $and$libresoc.v:120338$4740_Y + attribute \src "libresoc.v:120339.18-120339.125" + wire width 4 $and$libresoc.v:120339$4741_Y + attribute \src "libresoc.v:120341.18-120341.112" + wire $and$libresoc.v:120341$4743_Y + attribute \src "libresoc.v:120343.18-120343.126" + wire $and$libresoc.v:120343$4745_Y + attribute \src "libresoc.v:120344.18-120344.126" + wire $and$libresoc.v:120344$4746_Y + attribute \src "libresoc.v:120345.18-120345.117" + wire $and$libresoc.v:120345$4747_Y + attribute \src "libresoc.v:120351.18-120351.130" + wire $and$libresoc.v:120351$4753_Y + attribute \src "libresoc.v:120352.18-120352.124" + wire width 4 $and$libresoc.v:120352$4754_Y + attribute \src "libresoc.v:120354.18-120354.116" + wire $and$libresoc.v:120354$4756_Y + attribute \src "libresoc.v:120355.18-120355.119" + wire $and$libresoc.v:120355$4757_Y + attribute \src "libresoc.v:120356.18-120356.121" + wire $and$libresoc.v:120356$4758_Y + attribute \src "libresoc.v:120357.18-120357.121" + wire $and$libresoc.v:120357$4759_Y + attribute \src "libresoc.v:120367.18-120367.134" + wire $and$libresoc.v:120367$4769_Y + attribute \src "libresoc.v:120368.18-120368.132" + wire $and$libresoc.v:120368$4770_Y + attribute \src "libresoc.v:120369.18-120369.149" + wire width 3 $and$libresoc.v:120369$4771_Y + attribute \src "libresoc.v:120340.18-120340.113" + wire $eq$libresoc.v:120340$4742_Y + attribute \src "libresoc.v:120342.18-120342.119" + wire $eq$libresoc.v:120342$4744_Y + attribute \src "libresoc.v:120307.19-120307.130" + wire $not$libresoc.v:120307$4709_Y + attribute \src "libresoc.v:120308.19-120308.136" + wire $not$libresoc.v:120308$4710_Y + attribute \src "libresoc.v:120310.19-120310.115" + wire width 3 $not$libresoc.v:120310$4712_Y + attribute \src "libresoc.v:120323.18-120323.97" + wire $not$libresoc.v:120323$4725_Y + attribute \src "libresoc.v:120325.18-120325.99" + wire $not$libresoc.v:120325$4727_Y + attribute \src "libresoc.v:120328.18-120328.113" + wire width 4 $not$libresoc.v:120328$4730_Y + attribute \src "libresoc.v:120331.18-120331.106" + wire $not$libresoc.v:120331$4733_Y + attribute \src "libresoc.v:120337.18-120337.120" + wire $not$libresoc.v:120337$4739_Y + attribute \src "libresoc.v:120348.17-120348.113" + wire width 3 $not$libresoc.v:120348$4750_Y + attribute \src "libresoc.v:120336.18-120336.112" + wire $or$libresoc.v:120336$4738_Y + attribute \src "libresoc.v:120346.18-120346.122" + wire $or$libresoc.v:120346$4748_Y + attribute \src "libresoc.v:120347.18-120347.124" + wire $or$libresoc.v:120347$4749_Y + attribute \src "libresoc.v:120349.18-120349.168" + wire width 4 $or$libresoc.v:120349$4751_Y + attribute \src "libresoc.v:120350.18-120350.155" + wire width 3 $or$libresoc.v:120350$4752_Y + attribute \src "libresoc.v:120353.18-120353.120" + wire width 4 $or$libresoc.v:120353$4755_Y + attribute \src "libresoc.v:120359.17-120359.117" + wire width 3 $or$libresoc.v:120359$4761_Y + attribute \src "libresoc.v:120364.17-120364.104" + wire $reduce_and$libresoc.v:120364$4766_Y + attribute \src "libresoc.v:120330.18-120330.106" + wire $reduce_or$libresoc.v:120330$4732_Y + attribute \src "libresoc.v:120334.18-120334.113" + wire $reduce_or$libresoc.v:120334$4736_Y + attribute \src "libresoc.v:120335.18-120335.112" + wire $reduce_or$libresoc.v:120335$4737_Y + attribute \src "libresoc.v:120358.18-120358.158" + wire $ternary$libresoc.v:120358$4760_Y + attribute \src "libresoc.v:120360.18-120360.159" + wire width 64 $ternary$libresoc.v:120360$4762_Y + attribute \src "libresoc.v:120361.18-120361.164" + wire $ternary$libresoc.v:120361$4763_Y + attribute \src "libresoc.v:120362.18-120362.180" + wire width 64 $ternary$libresoc.v:120362$4764_Y + attribute \src "libresoc.v:120363.18-120363.115" + wire width 64 $ternary$libresoc.v:120363$4765_Y + attribute \src "libresoc.v:120365.18-120365.125" + wire width 64 $ternary$libresoc.v:120365$4767_Y + attribute \src "libresoc.v:120366.18-120366.118" + wire $ternary$libresoc.v:120366$4768_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + wire \$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" + wire \$100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" + wire \$102 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + wire width 3 \$104 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + wire width 3 \$106 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + wire width 3 \$108 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + wire \$110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + wire \$112 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + wire \$114 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + wire \$116 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" + wire width 4 \$118 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" + wire width 4 \$120 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + wire \$122 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + wire \$124 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + wire \$126 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + wire \$128 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire \$14 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire \$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" + wire \$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" + wire width 4 \$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + wire \$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + wire width 4 \$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + wire width 4 \$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + wire \$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + wire \$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + wire \$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + wire \$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + wire \$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + wire \$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + wire width 4 \$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + wire \$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + wire \$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + wire \$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + wire width 3 \$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + wire \$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + wire \$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + wire \$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" + wire \$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" + wire \$58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" + wire width 4 \$60 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" + wire width 3 \$62 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" + wire \$64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" + wire width 4 \$66 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" + wire width 4 \$68 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + wire width 3 \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + wire \$70 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + wire \$72 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + wire \$74 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + wire \$76 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" + wire \$78 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" + wire width 64 \$80 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" + wire \$83 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" + wire width 64 \$86 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 64 \$88 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 64 \$90 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire \$92 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" + wire \$94 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" + wire \$96 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + wire width 3 \$98 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:187" + wire \all_rd + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire \all_rd_dly + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire \all_rd_dly$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:192" + wire \all_rd_pulse + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + wire \all_rd_rise + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \alu_div0_cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \alu_div0_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \alu_div0_logical_op__data_len$next + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \alu_div0_logical_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \alu_div0_logical_op__fn_unit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \alu_div0_logical_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \alu_div0_logical_op__imm_data__data$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_div0_logical_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_div0_logical_op__imm_data__ok$next + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \alu_div0_logical_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \alu_div0_logical_op__input_carry$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \alu_div0_logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \alu_div0_logical_op__insn$next + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \alu_div0_logical_op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \alu_div0_logical_op__insn_type$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_div0_logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_div0_logical_op__invert_in$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_div0_logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_div0_logical_op__invert_out$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_div0_logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_div0_logical_op__is_32bit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_div0_logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_div0_logical_op__is_signed$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_div0_logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_div0_logical_op__oe__oe$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_div0_logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_div0_logical_op__oe__ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_div0_logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_div0_logical_op__output_carry$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_div0_logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_div0_logical_op__rc__ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_div0_logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_div0_logical_op__rc__rc$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_div0_logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_div0_logical_op__write_cr0$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_div0_logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_div0_logical_op__zero_a$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire \alu_div0_n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire \alu_div0_n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \alu_div0_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire \alu_div0_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire \alu_div0_p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \alu_div0_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \alu_div0_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \alu_div0_xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \alu_div0_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \alu_div0_xer_so$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:196" + wire \alu_done + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire \alu_done_dly + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire \alu_done_dly$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + wire \alu_done_rise + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire \alu_l_q_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \alu_l_r_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \alu_l_r_alu$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \alu_l_s_alu + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:197" + wire \alu_pulse + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198" + wire width 4 \alu_pulsem + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire \alui_l_q_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \alui_l_r_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \alui_l_r_alui$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \alui_l_s_alui + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 38 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 37 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 31 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" + wire output 20 \cu_busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:108" + wire \cu_done_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:104" + wire \cu_go_die_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" + wire input 19 \cu_issue_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 input 23 \cu_rd__go_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 output 22 \cu_rd__rel_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" + wire width 3 input 21 \cu_rdmaskn_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:102" + wire \cu_shadown_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 4 input 29 \cu_wr__go_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 4 output 28 \cu_wr__rel_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:97" + wire width 4 \cu_wrmask_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 64 \data_r0__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 64 \data_r0__o$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r0__o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r0__o_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 4 \data_r1__cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 4 \data_r1__cr_a$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r1__cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r1__cr_a_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 2 \data_r2__xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 2 \data_r2__xer_ov$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r2__xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r2__xer_ov_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r3__xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r3__xer_so$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r3__xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r3__xer_so_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 30 \dest1_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 4 output 32 \dest2_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 2 output 34 \dest3_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire output 36 \dest4_o + attribute \src "libresoc.v:119662.7-119662.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 27 \o_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire \opc_l_q_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \opc_l_r_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \opc_l_r_opc$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \opc_l_s_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \opc_l_s_opc$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 17 \oper_i_alu_div0__data_len + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 2 \oper_i_alu_div0__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 3 \oper_i_alu_div0__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 4 \oper_i_alu_div0__imm_data__ok + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 11 \oper_i_alu_div0__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 18 \oper_i_alu_div0__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \oper_i_alu_div0__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \oper_i_alu_div0__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \oper_i_alu_div0__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 15 \oper_i_alu_div0__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 16 \oper_i_alu_div0__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 7 \oper_i_alu_div0__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \oper_i_alu_div0__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \oper_i_alu_div0__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 6 \oper_i_alu_div0__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 5 \oper_i_alu_div0__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \oper_i_alu_div0__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \oper_i_alu_div0__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" + wire width 4 \prev_wr_go + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" + wire width 4 \prev_wr_go$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212" + wire \req_done + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 4 \req_l_q_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 4 \req_l_r_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 4 \req_l_r_req$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 4 \req_l_s_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 4 \req_l_s_req$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226" + wire \reset + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:229" + wire width 3 \reset_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:228" + wire width 4 \reset_w + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire \rok_l_q_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \rok_l_r_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \rok_l_r_rdok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \rok_l_s_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \rok_l_s_rdok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \rst_l_r_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \rst_l_r_rst$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \rst_l_s_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \rst_l_s_rst$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227" + wire \rst_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 24 \src1_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 25 \src2_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire input 26 \src3_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 3 \src_l_q_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 3 \src_l_r_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 3 \src_l_r_src$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 3 \src_l_s_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 3 \src_l_s_src$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:166" + wire width 64 \src_or_imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:166" + wire width 64 \src_or_imm$85 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 64 \src_r0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 64 \src_r0$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 64 \src_r1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 64 \src_r1$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire \src_r2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire \src_r2$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:167" + wire \src_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:167" + wire \src_sel$82 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" + wire \wr_any + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 33 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 35 \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + cell $and $and$libresoc.v:120309$4711 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \$98 + connect \B { 1'1 \$102 \$100 } + connect \Y $and$libresoc.v:120309$4711_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + cell $and $and$libresoc.v:120311$4713 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \$104 + connect \B \$106 + connect \Y $and$libresoc.v:120311$4713_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $and $and$libresoc.v:120312$4714 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$2 + connect \B \$4 + connect \Y $and$libresoc.v:120312$4714_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + cell $and $and$libresoc.v:120313$4715 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_busy_o + connect \B \cu_shadown_i + connect \Y $and$libresoc.v:120313$4715_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + cell $and $and$libresoc.v:120314$4716 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_busy_o + connect \B \cu_shadown_i + connect \Y $and$libresoc.v:120314$4716_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + cell $and $and$libresoc.v:120315$4717 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_busy_o + connect \B \cu_shadown_i + connect \Y $and$libresoc.v:120315$4717_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + cell $and $and$libresoc.v:120316$4718 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_busy_o + connect \B \cu_shadown_i + connect \Y $and$libresoc.v:120316$4718_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" + cell $and $and$libresoc.v:120317$4719 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \req_l_q_req + connect \B { \$110 \$112 \$114 \$116 } + connect \Y $and$libresoc.v:120317$4719_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" + cell $and $and$libresoc.v:120318$4720 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \$118 + connect \B \cu_wrmask_o + connect \Y $and$libresoc.v:120318$4720_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + cell $and $and$libresoc.v:120319$4721 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_wr__go_i [0] + connect \B \cu_busy_o + connect \Y $and$libresoc.v:120319$4721_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + cell $and $and$libresoc.v:120320$4722 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_wr__go_i [1] + connect \B \cu_busy_o + connect \Y $and$libresoc.v:120320$4722_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + cell $and $and$libresoc.v:120321$4723 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_wr__go_i [2] + connect \B \cu_busy_o + connect \Y $and$libresoc.v:120321$4723_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + cell $and $and$libresoc.v:120322$4724 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_wr__go_i [3] + connect \B \cu_busy_o + connect \Y $and$libresoc.v:120322$4724_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $and$libresoc.v:120324$4726 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \all_rd + connect \B \$12 + connect \Y $and$libresoc.v:120324$4726_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $and$libresoc.v:120326$4728 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_done + connect \B \$16 + connect \Y $and$libresoc.v:120326$4728_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" + cell $and $and$libresoc.v:120327$4729 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \cu_wr__go_i + connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } + connect \Y $and$libresoc.v:120327$4729_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $and $and$libresoc.v:120329$4731 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \cu_wr__rel_o + connect \B \$24 + connect \Y $and$libresoc.v:120329$4731_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" + cell $and $and$libresoc.v:120332$4734 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_busy_o + connect \B \rok_l_q_rdok + connect \Y $and$libresoc.v:120332$4734_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $and $and$libresoc.v:120333$4735 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_busy_o + connect \B \$22 + connect \Y $and$libresoc.v:120333$4735_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + cell $and $and$libresoc.v:120338$4740 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_any + connect \B \$38 + connect \Y $and$libresoc.v:120338$4740_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + cell $and $and$libresoc.v:120339$4741 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \req_l_q_req + connect \B \cu_wrmask_o + connect \Y $and$libresoc.v:120339$4741_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + cell $and $and$libresoc.v:120341$4743 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$40 + connect \B \$44 + connect \Y $and$libresoc.v:120341$4743_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + cell $and $and$libresoc.v:120343$4745 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$48 + connect \B \alu_div0_n_ready_i + connect \Y $and$libresoc.v:120343$4745_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + cell $and $and$libresoc.v:120344$4746 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$50 + connect \B \alu_div0_n_valid_o + connect \Y $and$libresoc.v:120344$4746_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + cell $and $and$libresoc.v:120345$4747 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$52 + connect \B \cu_busy_o + connect \Y $and$libresoc.v:120345$4747_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" + cell $and $and$libresoc.v:120351$4753 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_div0_n_valid_o + connect \B \cu_busy_o + connect \Y $and$libresoc.v:120351$4753_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" + cell $and $and$libresoc.v:120352$4754 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \alu_pulsem + connect \B \cu_wrmask_o + connect \Y $and$libresoc.v:120352$4754_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + cell $and $and$libresoc.v:120354$4756 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \o_ok + connect \B \cu_busy_o + connect \Y $and$libresoc.v:120354$4756_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + cell $and $and$libresoc.v:120355$4757 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cr_a_ok + connect \B \cu_busy_o + connect \Y $and$libresoc.v:120355$4757_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + cell $and $and$libresoc.v:120356$4758 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \xer_ov_ok + connect \B \cu_busy_o + connect \Y $and$libresoc.v:120356$4758_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + cell $and $and$libresoc.v:120357$4759 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \xer_so_ok + connect \B \cu_busy_o + connect \Y $and$libresoc.v:120357$4759_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" + cell $and $and$libresoc.v:120367$4769 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_div0_p_ready_o + connect \B \alui_l_q_alui + connect \Y $and$libresoc.v:120367$4769_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" + cell $and $and$libresoc.v:120368$4770 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_div0_n_valid_o + connect \B \alu_l_q_alu + connect \Y $and$libresoc.v:120368$4770_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + cell $and $and$libresoc.v:120369$4771 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \src_l_q_src + connect \B { \cu_busy_o \cu_busy_o \cu_busy_o } + connect \Y $and$libresoc.v:120369$4771_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + cell $eq $eq$libresoc.v:120340$4742 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$42 + connect \B 1'0 + connect \Y $eq$libresoc.v:120340$4742_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + cell $eq $eq$libresoc.v:120342$4744 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_wrmask_o + connect \B 1'0 + connect \Y $eq$libresoc.v:120342$4744_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" + cell $not $not$libresoc.v:120307$4709 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_div0_logical_op__zero_a + connect \Y $not$libresoc.v:120307$4709_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" + cell $not $not$libresoc.v:120308$4710 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_div0_logical_op__imm_data__ok + connect \Y $not$libresoc.v:120308$4710_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + cell $not $not$libresoc.v:120310$4712 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \cu_rdmaskn_i + connect \Y $not$libresoc.v:120310$4712_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $not$libresoc.v:120323$4725 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \all_rd_dly + connect \Y $not$libresoc.v:120323$4725_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $not$libresoc.v:120325$4727 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_done_dly + connect \Y $not$libresoc.v:120325$4727_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $not $not$libresoc.v:120328$4730 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \cu_wrmask_o + connect \Y $not$libresoc.v:120328$4730_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $not $not$libresoc.v:120331$4733 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$23 + connect \Y $not$libresoc.v:120331$4733_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + cell $not $not$libresoc.v:120337$4739 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_div0_n_ready_i + connect \Y $not$libresoc.v:120337$4739_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $not $not$libresoc.v:120348$4750 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \cu_rd__rel_o + connect \Y $not$libresoc.v:120348$4750_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $or $or$libresoc.v:120336$4738 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$32 + connect \B \$34 + connect \Y $or$libresoc.v:120336$4738_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" + cell $or $or$libresoc.v:120346$4748 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \req_done + connect \B \cu_go_die_i + connect \Y $or$libresoc.v:120346$4748_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" + cell $or $or$libresoc.v:120347$4749 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_issue_i + connect \B \cu_go_die_i + connect \Y $or$libresoc.v:120347$4749_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" + cell $or $or$libresoc.v:120349$4751 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \cu_wr__go_i + connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } + connect \Y $or$libresoc.v:120349$4751_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" + cell $or $or$libresoc.v:120350$4752 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \cu_rd__go_i + connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } + connect \Y $or$libresoc.v:120350$4752_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" + cell $or $or$libresoc.v:120353$4755 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \reset_w + connect \B \prev_wr_go + connect \Y $or$libresoc.v:120353$4755_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $or $or$libresoc.v:120359$4761 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \$5 + connect \B \cu_rd__go_i + connect \Y $or$libresoc.v:120359$4761_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $reduce_and $reduce_and$libresoc.v:120364$4766 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \$7 + connect \Y $reduce_and$libresoc.v:120364$4766_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $reduce_or $reduce_or$libresoc.v:120330$4732 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \$26 + connect \Y $reduce_or$libresoc.v:120330$4732_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $reduce_or $reduce_or$libresoc.v:120334$4736 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \cu_wr__go_i + connect \Y $reduce_or$libresoc.v:120334$4736_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $reduce_or $reduce_or$libresoc.v:120335$4737 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \prev_wr_go + connect \Y $reduce_or$libresoc.v:120335$4737_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" + cell $mux $ternary$libresoc.v:120358$4760 + parameter \WIDTH 1 + connect \A \src_l_q_src [0] + connect \B \opc_l_q_opc + connect \S \alu_div0_logical_op__zero_a + connect \Y $ternary$libresoc.v:120358$4760_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" + cell $mux $ternary$libresoc.v:120360$4762 + parameter \WIDTH 64 + connect \A \src1_i + connect \B 64'0000000000000000000000000000000000000000000000000000000000000000 + connect \S \alu_div0_logical_op__zero_a + connect \Y $ternary$libresoc.v:120360$4762_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" + cell $mux $ternary$libresoc.v:120361$4763 + parameter \WIDTH 1 + connect \A \src_l_q_src [1] + connect \B \opc_l_q_opc + connect \S \alu_div0_logical_op__imm_data__ok + connect \Y $ternary$libresoc.v:120361$4763_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" + cell $mux $ternary$libresoc.v:120362$4764 + parameter \WIDTH 64 + connect \A \src2_i + connect \B \alu_div0_logical_op__imm_data__data + connect \S \alu_div0_logical_op__imm_data__ok + connect \Y $ternary$libresoc.v:120362$4764_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $ternary$libresoc.v:120363$4765 + parameter \WIDTH 64 + connect \A \src_r0 + connect \B \src_or_imm + connect \S \src_sel + connect \Y $ternary$libresoc.v:120363$4765_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $ternary$libresoc.v:120365$4767 + parameter \WIDTH 64 + connect \A \src_r1 + connect \B \src_or_imm$85 + connect \S \src_sel$82 + connect \Y $ternary$libresoc.v:120365$4767_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $ternary$libresoc.v:120366$4768 + parameter \WIDTH 1 + connect \A \src_r2 + connect \B \src3_i + connect \S \src_l_q_src [2] + connect \Y $ternary$libresoc.v:120366$4768_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:120458.12-120494.4" + cell \alu_div0 \alu_div0 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cr_a \alu_div0_cr_a + connect \cr_a_ok \cr_a_ok + connect \logical_op__data_len \alu_div0_logical_op__data_len + connect \logical_op__fn_unit \alu_div0_logical_op__fn_unit + connect \logical_op__imm_data__data \alu_div0_logical_op__imm_data__data + connect \logical_op__imm_data__ok \alu_div0_logical_op__imm_data__ok + connect \logical_op__input_carry \alu_div0_logical_op__input_carry + connect \logical_op__insn \alu_div0_logical_op__insn + connect \logical_op__insn_type \alu_div0_logical_op__insn_type + connect \logical_op__invert_in \alu_div0_logical_op__invert_in + connect \logical_op__invert_out \alu_div0_logical_op__invert_out + connect \logical_op__is_32bit \alu_div0_logical_op__is_32bit + connect \logical_op__is_signed \alu_div0_logical_op__is_signed + connect \logical_op__oe__oe \alu_div0_logical_op__oe__oe + connect \logical_op__oe__ok \alu_div0_logical_op__oe__ok + connect \logical_op__output_carry \alu_div0_logical_op__output_carry + connect \logical_op__rc__ok \alu_div0_logical_op__rc__ok + connect \logical_op__rc__rc \alu_div0_logical_op__rc__rc + connect \logical_op__write_cr0 \alu_div0_logical_op__write_cr0 + connect \logical_op__zero_a \alu_div0_logical_op__zero_a + connect \n_ready_i \alu_div0_n_ready_i + connect \n_valid_o \alu_div0_n_valid_o + connect \o \alu_div0_o + connect \o_ok \o_ok + connect \p_ready_o \alu_div0_p_ready_o + connect \p_valid_i \alu_div0_p_valid_i + connect \ra \alu_div0_ra + connect \rb \alu_div0_rb + connect \xer_ov \alu_div0_xer_ov + connect \xer_ov_ok \xer_ov_ok + connect \xer_so \alu_div0_xer_so + connect \xer_so$1 \alu_div0_xer_so$1 + connect \xer_so_ok \xer_so_ok + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:120495.14-120501.4" + cell \alu_l$87 \alu_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_alu \alu_l_q_alu + connect \r_alu \alu_l_r_alu + connect \s_alu \alu_l_s_alu + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:120502.15-120508.4" + cell \alui_l$86 \alui_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_alui \alui_l_q_alui + connect \r_alui \alui_l_r_alui + connect \s_alui \alui_l_s_alui + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:120509.14-120515.4" + cell \opc_l$82 \opc_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_opc \opc_l_q_opc + connect \r_opc \opc_l_r_opc + connect \s_opc \opc_l_s_opc + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:120516.14-120522.4" + cell \req_l$83 \req_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_req \req_l_q_req + connect \r_req \req_l_r_req + connect \s_req \req_l_s_req + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:120523.14-120529.4" + cell \rok_l$85 \rok_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_rdok \rok_l_q_rdok + connect \r_rdok \rok_l_r_rdok + connect \s_rdok \rok_l_s_rdok + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:120530.14-120535.4" + cell \rst_l$84 \rst_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \r_rst \rst_l_r_rst + connect \s_rst \rst_l_s_rst + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:120536.14-120542.4" + cell \src_l$81 \src_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_src \src_l_q_src + connect \r_src \src_l_r_src + connect \s_src \src_l_s_src + end + attribute \src "libresoc.v:119662.7-119662.20" + process $proc$libresoc.v:119662$4944 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:119792.7-119792.24" + process $proc$libresoc.v:119792$4945 + assign { } { } + assign $1\all_rd_dly[0:0] 1'0 + sync always + sync init + update \all_rd_dly $1\all_rd_dly[0:0] + end + attribute \src "libresoc.v:119802.13-119802.49" + process $proc$libresoc.v:119802$4946 + assign { } { } + assign $1\alu_div0_logical_op__data_len[3:0] 4'0000 + sync always + sync init + update \alu_div0_logical_op__data_len $1\alu_div0_logical_op__data_len[3:0] + end + attribute \src "libresoc.v:119819.14-119819.52" + process $proc$libresoc.v:119819$4947 + assign { } { } + assign $1\alu_div0_logical_op__fn_unit[11:0] 12'000000000000 + sync always + sync init + update \alu_div0_logical_op__fn_unit $1\alu_div0_logical_op__fn_unit[11:0] + end + attribute \src "libresoc.v:119823.14-119823.72" + process $proc$libresoc.v:119823$4948 + assign { } { } + assign $1\alu_div0_logical_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \alu_div0_logical_op__imm_data__data $1\alu_div0_logical_op__imm_data__data[63:0] + end + attribute \src "libresoc.v:119827.7-119827.47" + process $proc$libresoc.v:119827$4949 + assign { } { } + assign $1\alu_div0_logical_op__imm_data__ok[0:0] 1'0 + sync always + sync init + update \alu_div0_logical_op__imm_data__ok $1\alu_div0_logical_op__imm_data__ok[0:0] + end + attribute \src "libresoc.v:119835.13-119835.52" + process $proc$libresoc.v:119835$4950 + assign { } { } + assign $1\alu_div0_logical_op__input_carry[1:0] 2'00 + sync always + sync init + update \alu_div0_logical_op__input_carry $1\alu_div0_logical_op__input_carry[1:0] + end + attribute \src "libresoc.v:119839.14-119839.47" + process $proc$libresoc.v:119839$4951 + assign { } { } + assign $1\alu_div0_logical_op__insn[31:0] 0 + sync always + sync init + update \alu_div0_logical_op__insn $1\alu_div0_logical_op__insn[31:0] + end + attribute \src "libresoc.v:119917.13-119917.51" + process $proc$libresoc.v:119917$4952 + assign { } { } + assign $1\alu_div0_logical_op__insn_type[6:0] 7'0000000 + sync always + sync init + update \alu_div0_logical_op__insn_type $1\alu_div0_logical_op__insn_type[6:0] + end + attribute \src "libresoc.v:119921.7-119921.44" + process $proc$libresoc.v:119921$4953 + assign { } { } + assign $1\alu_div0_logical_op__invert_in[0:0] 1'0 + sync always + sync init + update \alu_div0_logical_op__invert_in $1\alu_div0_logical_op__invert_in[0:0] + end + attribute \src "libresoc.v:119925.7-119925.45" + process $proc$libresoc.v:119925$4954 + assign { } { } + assign $1\alu_div0_logical_op__invert_out[0:0] 1'0 + sync always + sync init + update \alu_div0_logical_op__invert_out $1\alu_div0_logical_op__invert_out[0:0] + end + attribute \src "libresoc.v:119929.7-119929.43" + process $proc$libresoc.v:119929$4955 + assign { } { } + assign $1\alu_div0_logical_op__is_32bit[0:0] 1'0 + sync always + sync init + update \alu_div0_logical_op__is_32bit $1\alu_div0_logical_op__is_32bit[0:0] + end + attribute \src "libresoc.v:119933.7-119933.44" + process $proc$libresoc.v:119933$4956 + assign { } { } + assign $1\alu_div0_logical_op__is_signed[0:0] 1'0 + sync always + sync init + update \alu_div0_logical_op__is_signed $1\alu_div0_logical_op__is_signed[0:0] + end + attribute \src "libresoc.v:119937.7-119937.41" + process $proc$libresoc.v:119937$4957 + assign { } { } + assign $1\alu_div0_logical_op__oe__oe[0:0] 1'0 + sync always + sync init + update \alu_div0_logical_op__oe__oe $1\alu_div0_logical_op__oe__oe[0:0] + end + attribute \src "libresoc.v:119941.7-119941.41" + process $proc$libresoc.v:119941$4958 + assign { } { } + assign $1\alu_div0_logical_op__oe__ok[0:0] 1'0 + sync always + sync init + update \alu_div0_logical_op__oe__ok $1\alu_div0_logical_op__oe__ok[0:0] + end + attribute \src "libresoc.v:119945.7-119945.47" + process $proc$libresoc.v:119945$4959 + assign { } { } + assign $1\alu_div0_logical_op__output_carry[0:0] 1'0 + sync always + sync init + update \alu_div0_logical_op__output_carry $1\alu_div0_logical_op__output_carry[0:0] + end + attribute \src "libresoc.v:119949.7-119949.41" + process $proc$libresoc.v:119949$4960 + assign { } { } + assign $1\alu_div0_logical_op__rc__ok[0:0] 1'0 + sync always + sync init + update \alu_div0_logical_op__rc__ok $1\alu_div0_logical_op__rc__ok[0:0] + end + attribute \src "libresoc.v:119953.7-119953.41" + process $proc$libresoc.v:119953$4961 + assign { } { } + assign $1\alu_div0_logical_op__rc__rc[0:0] 1'0 + sync always + sync init + update \alu_div0_logical_op__rc__rc $1\alu_div0_logical_op__rc__rc[0:0] + end + attribute \src "libresoc.v:119957.7-119957.44" + process $proc$libresoc.v:119957$4962 + assign { } { } + assign $1\alu_div0_logical_op__write_cr0[0:0] 1'0 + sync always + sync init + update \alu_div0_logical_op__write_cr0 $1\alu_div0_logical_op__write_cr0[0:0] + end + attribute \src "libresoc.v:119961.7-119961.41" + process $proc$libresoc.v:119961$4963 + assign { } { } + assign $1\alu_div0_logical_op__zero_a[0:0] 1'0 + sync always + sync init + update \alu_div0_logical_op__zero_a $1\alu_div0_logical_op__zero_a[0:0] + end + attribute \src "libresoc.v:119987.7-119987.26" + process $proc$libresoc.v:119987$4964 + assign { } { } + assign $1\alu_done_dly[0:0] 1'0 + sync always + sync init + update \alu_done_dly $1\alu_done_dly[0:0] + end + attribute \src "libresoc.v:119995.7-119995.25" + process $proc$libresoc.v:119995$4965 + assign { } { } + assign $1\alu_l_r_alu[0:0] 1'1 + sync always + sync init + update \alu_l_r_alu $1\alu_l_r_alu[0:0] + end + attribute \src "libresoc.v:120007.7-120007.27" + process $proc$libresoc.v:120007$4966 + assign { } { } + assign $1\alui_l_r_alui[0:0] 1'1 + sync always + sync init + update \alui_l_r_alui $1\alui_l_r_alui[0:0] + end + attribute \src "libresoc.v:120041.14-120041.47" + process $proc$libresoc.v:120041$4967 + assign { } { } + assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \data_r0__o $1\data_r0__o[63:0] + end + attribute \src "libresoc.v:120045.7-120045.27" + process $proc$libresoc.v:120045$4968 + assign { } { } + assign $1\data_r0__o_ok[0:0] 1'0 + sync always + sync init + update \data_r0__o_ok $1\data_r0__o_ok[0:0] + end + attribute \src "libresoc.v:120049.13-120049.33" + process $proc$libresoc.v:120049$4969 + assign { } { } + assign $1\data_r1__cr_a[3:0] 4'0000 + sync always + sync init + update \data_r1__cr_a $1\data_r1__cr_a[3:0] + end + attribute \src "libresoc.v:120053.7-120053.30" + process $proc$libresoc.v:120053$4970 + assign { } { } + assign $1\data_r1__cr_a_ok[0:0] 1'0 + sync always + sync init + update \data_r1__cr_a_ok $1\data_r1__cr_a_ok[0:0] + end + attribute \src "libresoc.v:120057.13-120057.35" + process $proc$libresoc.v:120057$4971 + assign { } { } + assign $1\data_r2__xer_ov[1:0] 2'00 + sync always + sync init + update \data_r2__xer_ov $1\data_r2__xer_ov[1:0] + end + attribute \src "libresoc.v:120061.7-120061.32" + process $proc$libresoc.v:120061$4972 + assign { } { } + assign $1\data_r2__xer_ov_ok[0:0] 1'0 + sync always + sync init + update \data_r2__xer_ov_ok $1\data_r2__xer_ov_ok[0:0] + end + attribute \src "libresoc.v:120065.7-120065.29" + process $proc$libresoc.v:120065$4973 + assign { } { } + assign $1\data_r3__xer_so[0:0] 1'0 + sync always + sync init + update \data_r3__xer_so $1\data_r3__xer_so[0:0] + end + attribute \src "libresoc.v:120069.7-120069.32" + process $proc$libresoc.v:120069$4974 + assign { } { } + assign $1\data_r3__xer_so_ok[0:0] 1'0 + sync always + sync init + update \data_r3__xer_so_ok $1\data_r3__xer_so_ok[0:0] + end + attribute \src "libresoc.v:120089.7-120089.25" + process $proc$libresoc.v:120089$4975 + assign { } { } + assign $1\opc_l_r_opc[0:0] 1'1 + sync always + sync init + update \opc_l_r_opc $1\opc_l_r_opc[0:0] + end + attribute \src "libresoc.v:120093.7-120093.25" + process $proc$libresoc.v:120093$4976 + assign { } { } + assign $1\opc_l_s_opc[0:0] 1'0 + sync always + sync init + update \opc_l_s_opc $1\opc_l_s_opc[0:0] + end + attribute \src "libresoc.v:120224.13-120224.30" + process $proc$libresoc.v:120224$4977 + assign { } { } + assign $1\prev_wr_go[3:0] 4'0000 + sync always + sync init + update \prev_wr_go $1\prev_wr_go[3:0] + end + attribute \src "libresoc.v:120232.13-120232.31" + process $proc$libresoc.v:120232$4978 + assign { } { } + assign $1\req_l_r_req[3:0] 4'1111 + sync always + sync init + update \req_l_r_req $1\req_l_r_req[3:0] + end + attribute \src "libresoc.v:120236.13-120236.31" + process $proc$libresoc.v:120236$4979 + assign { } { } + assign $1\req_l_s_req[3:0] 4'0000 + sync always + sync init + update \req_l_s_req $1\req_l_s_req[3:0] + end + attribute \src "libresoc.v:120248.7-120248.26" + process $proc$libresoc.v:120248$4980 + assign { } { } + assign $1\rok_l_r_rdok[0:0] 1'1 + sync always + sync init + update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] + end + attribute \src "libresoc.v:120252.7-120252.26" + process $proc$libresoc.v:120252$4981 + assign { } { } + assign $1\rok_l_s_rdok[0:0] 1'0 + sync always + sync init + update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] + end + attribute \src "libresoc.v:120256.7-120256.25" + process $proc$libresoc.v:120256$4982 + assign { } { } + assign $1\rst_l_r_rst[0:0] 1'1 + sync always + sync init + update \rst_l_r_rst $1\rst_l_r_rst[0:0] + end + attribute \src "libresoc.v:120260.7-120260.25" + process $proc$libresoc.v:120260$4983 + assign { } { } + assign $1\rst_l_s_rst[0:0] 1'0 + sync always + sync init + update \rst_l_s_rst $1\rst_l_s_rst[0:0] + end + attribute \src "libresoc.v:120274.13-120274.31" + process $proc$libresoc.v:120274$4984 + assign { } { } + assign $1\src_l_r_src[2:0] 3'111 + sync always + sync init + update \src_l_r_src $1\src_l_r_src[2:0] + end + attribute \src "libresoc.v:120278.13-120278.31" + process $proc$libresoc.v:120278$4985 + assign { } { } + assign $1\src_l_s_src[2:0] 3'000 + sync always + sync init + update \src_l_s_src $1\src_l_s_src[2:0] + end + attribute \src "libresoc.v:120286.14-120286.43" + process $proc$libresoc.v:120286$4986 + assign { } { } + assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \src_r0 $1\src_r0[63:0] + end + attribute \src "libresoc.v:120290.14-120290.43" + process $proc$libresoc.v:120290$4987 + assign { } { } + assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \src_r1 $1\src_r1[63:0] + end + attribute \src "libresoc.v:120294.7-120294.20" + process $proc$libresoc.v:120294$4988 + assign { } { } + assign $1\src_r2[0:0] 1'0 + sync always + sync init + update \src_r2 $1\src_r2[0:0] + end + attribute \src "libresoc.v:120370.3-120371.39" + process $proc$libresoc.v:120370$4772 + assign { } { } + assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next + sync posedge \coresync_clk + update \alu_l_r_alu $0\alu_l_r_alu[0:0] + end + attribute \src "libresoc.v:120372.3-120373.43" + process $proc$libresoc.v:120372$4773 + assign { } { } + assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next + sync posedge \coresync_clk + update \alui_l_r_alui $0\alui_l_r_alui[0:0] + end + attribute \src "libresoc.v:120374.3-120375.29" + process $proc$libresoc.v:120374$4774 + assign { } { } + assign $0\src_r2[0:0] \src_r2$next + sync posedge \coresync_clk + update \src_r2 $0\src_r2[0:0] + end + attribute \src "libresoc.v:120376.3-120377.29" + process $proc$libresoc.v:120376$4775 + assign { } { } + assign $0\src_r1[63:0] \src_r1$next + sync posedge \coresync_clk + update \src_r1 $0\src_r1[63:0] + end + attribute \src "libresoc.v:120378.3-120379.29" + process $proc$libresoc.v:120378$4776 + assign { } { } + assign $0\src_r0[63:0] \src_r0$next + sync posedge \coresync_clk + update \src_r0 $0\src_r0[63:0] + end + attribute \src "libresoc.v:120380.3-120381.47" + process $proc$libresoc.v:120380$4777 + assign { } { } + assign $0\data_r3__xer_so[0:0] \data_r3__xer_so$next + sync posedge \coresync_clk + update \data_r3__xer_so $0\data_r3__xer_so[0:0] + end + attribute \src "libresoc.v:120382.3-120383.53" + process $proc$libresoc.v:120382$4778 + assign { } { } + assign $0\data_r3__xer_so_ok[0:0] \data_r3__xer_so_ok$next + sync posedge \coresync_clk + update \data_r3__xer_so_ok $0\data_r3__xer_so_ok[0:0] + end + attribute \src "libresoc.v:120384.3-120385.47" + process $proc$libresoc.v:120384$4779 + assign { } { } + assign $0\data_r2__xer_ov[1:0] \data_r2__xer_ov$next + sync posedge \coresync_clk + update \data_r2__xer_ov $0\data_r2__xer_ov[1:0] + end + attribute \src "libresoc.v:120386.3-120387.53" + process $proc$libresoc.v:120386$4780 + assign { } { } + assign $0\data_r2__xer_ov_ok[0:0] \data_r2__xer_ov_ok$next + sync posedge \coresync_clk + update \data_r2__xer_ov_ok $0\data_r2__xer_ov_ok[0:0] + end + attribute \src "libresoc.v:120388.3-120389.43" + process $proc$libresoc.v:120388$4781 + assign { } { } + assign $0\data_r1__cr_a[3:0] \data_r1__cr_a$next + sync posedge \coresync_clk + update \data_r1__cr_a $0\data_r1__cr_a[3:0] + end + attribute \src "libresoc.v:120390.3-120391.49" + process $proc$libresoc.v:120390$4782 + assign { } { } + assign $0\data_r1__cr_a_ok[0:0] \data_r1__cr_a_ok$next + sync posedge \coresync_clk + update \data_r1__cr_a_ok $0\data_r1__cr_a_ok[0:0] + end + attribute \src "libresoc.v:120392.3-120393.37" + process $proc$libresoc.v:120392$4783 + assign { } { } + assign $0\data_r0__o[63:0] \data_r0__o$next + sync posedge \coresync_clk + update \data_r0__o $0\data_r0__o[63:0] + end + attribute \src "libresoc.v:120394.3-120395.43" + process $proc$libresoc.v:120394$4784 + assign { } { } + assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next + sync posedge \coresync_clk + update \data_r0__o_ok $0\data_r0__o_ok[0:0] + end + attribute \src "libresoc.v:120396.3-120397.77" + process $proc$libresoc.v:120396$4785 + assign { } { } + assign $0\alu_div0_logical_op__insn_type[6:0] \alu_div0_logical_op__insn_type$next + sync posedge \coresync_clk + update \alu_div0_logical_op__insn_type $0\alu_div0_logical_op__insn_type[6:0] + end + attribute \src "libresoc.v:120398.3-120399.73" + process $proc$libresoc.v:120398$4786 + assign { } { } + assign $0\alu_div0_logical_op__fn_unit[11:0] \alu_div0_logical_op__fn_unit$next + sync posedge \coresync_clk + update \alu_div0_logical_op__fn_unit $0\alu_div0_logical_op__fn_unit[11:0] + end + attribute \src "libresoc.v:120400.3-120401.87" + process $proc$libresoc.v:120400$4787 + assign { } { } + assign $0\alu_div0_logical_op__imm_data__data[63:0] \alu_div0_logical_op__imm_data__data$next + sync posedge \coresync_clk + update \alu_div0_logical_op__imm_data__data $0\alu_div0_logical_op__imm_data__data[63:0] + end + attribute \src "libresoc.v:120402.3-120403.83" + process $proc$libresoc.v:120402$4788 + assign { } { } + assign $0\alu_div0_logical_op__imm_data__ok[0:0] \alu_div0_logical_op__imm_data__ok$next + sync posedge \coresync_clk + update \alu_div0_logical_op__imm_data__ok $0\alu_div0_logical_op__imm_data__ok[0:0] + end + attribute \src "libresoc.v:120404.3-120405.71" + process $proc$libresoc.v:120404$4789 + assign { } { } + assign $0\alu_div0_logical_op__rc__rc[0:0] \alu_div0_logical_op__rc__rc$next + sync posedge \coresync_clk + update \alu_div0_logical_op__rc__rc $0\alu_div0_logical_op__rc__rc[0:0] + end + attribute \src "libresoc.v:120406.3-120407.71" + process $proc$libresoc.v:120406$4790 + assign { } { } + assign $0\alu_div0_logical_op__rc__ok[0:0] \alu_div0_logical_op__rc__ok$next + sync posedge \coresync_clk + update \alu_div0_logical_op__rc__ok $0\alu_div0_logical_op__rc__ok[0:0] + end + attribute \src "libresoc.v:120408.3-120409.71" + process $proc$libresoc.v:120408$4791 + assign { } { } + assign $0\alu_div0_logical_op__oe__oe[0:0] \alu_div0_logical_op__oe__oe$next + sync posedge \coresync_clk + update \alu_div0_logical_op__oe__oe $0\alu_div0_logical_op__oe__oe[0:0] + end + attribute \src "libresoc.v:120410.3-120411.71" + process $proc$libresoc.v:120410$4792 + assign { } { } + assign $0\alu_div0_logical_op__oe__ok[0:0] \alu_div0_logical_op__oe__ok$next + sync posedge \coresync_clk + update \alu_div0_logical_op__oe__ok $0\alu_div0_logical_op__oe__ok[0:0] + end + attribute \src "libresoc.v:120412.3-120413.77" + process $proc$libresoc.v:120412$4793 + assign { } { } + assign $0\alu_div0_logical_op__invert_in[0:0] \alu_div0_logical_op__invert_in$next + sync posedge \coresync_clk + update \alu_div0_logical_op__invert_in $0\alu_div0_logical_op__invert_in[0:0] + end + attribute \src "libresoc.v:120414.3-120415.71" + process $proc$libresoc.v:120414$4794 + assign { } { } + assign $0\alu_div0_logical_op__zero_a[0:0] \alu_div0_logical_op__zero_a$next + sync posedge \coresync_clk + update \alu_div0_logical_op__zero_a $0\alu_div0_logical_op__zero_a[0:0] + end + attribute \src "libresoc.v:120416.3-120417.81" + process $proc$libresoc.v:120416$4795 + assign { } { } + assign $0\alu_div0_logical_op__input_carry[1:0] \alu_div0_logical_op__input_carry$next + sync posedge \coresync_clk + update \alu_div0_logical_op__input_carry $0\alu_div0_logical_op__input_carry[1:0] + end + attribute \src "libresoc.v:120418.3-120419.79" + process $proc$libresoc.v:120418$4796 + assign { } { } + assign $0\alu_div0_logical_op__invert_out[0:0] \alu_div0_logical_op__invert_out$next + sync posedge \coresync_clk + update \alu_div0_logical_op__invert_out $0\alu_div0_logical_op__invert_out[0:0] + end + attribute \src "libresoc.v:120420.3-120421.77" + process $proc$libresoc.v:120420$4797 + assign { } { } + assign $0\alu_div0_logical_op__write_cr0[0:0] \alu_div0_logical_op__write_cr0$next + sync posedge \coresync_clk + update \alu_div0_logical_op__write_cr0 $0\alu_div0_logical_op__write_cr0[0:0] + end + attribute \src "libresoc.v:120422.3-120423.83" + process $proc$libresoc.v:120422$4798 + assign { } { } + assign $0\alu_div0_logical_op__output_carry[0:0] \alu_div0_logical_op__output_carry$next + sync posedge \coresync_clk + update \alu_div0_logical_op__output_carry $0\alu_div0_logical_op__output_carry[0:0] + end + attribute \src "libresoc.v:120424.3-120425.75" + process $proc$libresoc.v:120424$4799 + assign { } { } + assign $0\alu_div0_logical_op__is_32bit[0:0] \alu_div0_logical_op__is_32bit$next + sync posedge \coresync_clk + update \alu_div0_logical_op__is_32bit $0\alu_div0_logical_op__is_32bit[0:0] + end + attribute \src "libresoc.v:120426.3-120427.77" + process $proc$libresoc.v:120426$4800 + assign { } { } + assign $0\alu_div0_logical_op__is_signed[0:0] \alu_div0_logical_op__is_signed$next + sync posedge \coresync_clk + update \alu_div0_logical_op__is_signed $0\alu_div0_logical_op__is_signed[0:0] + end + attribute \src "libresoc.v:120428.3-120429.75" + process $proc$libresoc.v:120428$4801 + assign { } { } + assign $0\alu_div0_logical_op__data_len[3:0] \alu_div0_logical_op__data_len$next + sync posedge \coresync_clk + update \alu_div0_logical_op__data_len $0\alu_div0_logical_op__data_len[3:0] + end + attribute \src "libresoc.v:120430.3-120431.67" + process $proc$libresoc.v:120430$4802 + assign { } { } + assign $0\alu_div0_logical_op__insn[31:0] \alu_div0_logical_op__insn$next + sync posedge \coresync_clk + update \alu_div0_logical_op__insn $0\alu_div0_logical_op__insn[31:0] + end + attribute \src "libresoc.v:120432.3-120433.39" + process $proc$libresoc.v:120432$4803 + assign { } { } + assign $0\req_l_r_req[3:0] \req_l_r_req$next + sync posedge \coresync_clk + update \req_l_r_req $0\req_l_r_req[3:0] + end + attribute \src "libresoc.v:120434.3-120435.39" + process $proc$libresoc.v:120434$4804 + assign { } { } + assign $0\req_l_s_req[3:0] \req_l_s_req$next + sync posedge \coresync_clk + update \req_l_s_req $0\req_l_s_req[3:0] + end + attribute \src "libresoc.v:120436.3-120437.39" + process $proc$libresoc.v:120436$4805 + assign { } { } + assign $0\src_l_r_src[2:0] \src_l_r_src$next + sync posedge \coresync_clk + update \src_l_r_src $0\src_l_r_src[2:0] + end + attribute \src "libresoc.v:120438.3-120439.39" + process $proc$libresoc.v:120438$4806 + assign { } { } + assign $0\src_l_s_src[2:0] \src_l_s_src$next + sync posedge \coresync_clk + update \src_l_s_src $0\src_l_s_src[2:0] + end + attribute \src "libresoc.v:120440.3-120441.39" + process $proc$libresoc.v:120440$4807 + assign { } { } + assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next + sync posedge \coresync_clk + update \opc_l_r_opc $0\opc_l_r_opc[0:0] + end + attribute \src "libresoc.v:120442.3-120443.39" + process $proc$libresoc.v:120442$4808 + assign { } { } + assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next + sync posedge \coresync_clk + update \opc_l_s_opc $0\opc_l_s_opc[0:0] + end + attribute \src "libresoc.v:120444.3-120445.39" + process $proc$libresoc.v:120444$4809 + assign { } { } + assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next + sync posedge \coresync_clk + update \rst_l_r_rst $0\rst_l_r_rst[0:0] + end + attribute \src "libresoc.v:120446.3-120447.39" + process $proc$libresoc.v:120446$4810 + assign { } { } + assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next + sync posedge \coresync_clk + update \rst_l_s_rst $0\rst_l_s_rst[0:0] + end + attribute \src "libresoc.v:120448.3-120449.41" + process $proc$libresoc.v:120448$4811 + assign { } { } + assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next + sync posedge \coresync_clk + update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] + end + attribute \src "libresoc.v:120450.3-120451.41" + process $proc$libresoc.v:120450$4812 + assign { } { } + assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next + sync posedge \coresync_clk + update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] + end + attribute \src "libresoc.v:120452.3-120453.37" + process $proc$libresoc.v:120452$4813 + assign { } { } + assign $0\prev_wr_go[3:0] \prev_wr_go$next + sync posedge \coresync_clk + update \prev_wr_go $0\prev_wr_go[3:0] + end + attribute \src "libresoc.v:120454.3-120455.40" + process $proc$libresoc.v:120454$4814 + assign { } { } + assign $0\alu_done_dly[0:0] \alu_div0_n_valid_o + sync posedge \coresync_clk + update \alu_done_dly $0\alu_done_dly[0:0] + end + attribute \src "libresoc.v:120456.3-120457.25" + process $proc$libresoc.v:120456$4815 + assign { } { } + assign $0\all_rd_dly[0:0] \$10 + sync posedge \coresync_clk + update \all_rd_dly $0\all_rd_dly[0:0] + end + attribute \src "libresoc.v:120543.3-120552.6" + process $proc$libresoc.v:120543$4816 + assign { } { } + assign { } { } + assign $0\req_done[0:0] $1\req_done[0:0] + attribute \src "libresoc.v:120544.5-120544.29" + switch \initial + attribute \src "libresoc.v:120544.9-120544.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + switch \$54 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\req_done[0:0] 1'1 + case + assign $1\req_done[0:0] \$46 + end + sync always + update \req_done $0\req_done[0:0] + end + attribute \src "libresoc.v:120553.3-120561.6" + process $proc$libresoc.v:120553$4817 + assign { } { } + assign { } { } + assign $0\rok_l_s_rdok$next[0:0]$4818 $1\rok_l_s_rdok$next[0:0]$4819 + attribute \src "libresoc.v:120554.5-120554.29" + switch \initial + attribute \src "libresoc.v:120554.9-120554.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rok_l_s_rdok$next[0:0]$4819 1'0 + case + assign $1\rok_l_s_rdok$next[0:0]$4819 \cu_issue_i + end + sync always + update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$4818 + end + attribute \src "libresoc.v:120562.3-120570.6" + process $proc$libresoc.v:120562$4820 + assign { } { } + assign { } { } + assign $0\rok_l_r_rdok$next[0:0]$4821 $1\rok_l_r_rdok$next[0:0]$4822 + attribute \src "libresoc.v:120563.5-120563.29" + switch \initial + attribute \src "libresoc.v:120563.9-120563.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rok_l_r_rdok$next[0:0]$4822 1'1 + case + assign $1\rok_l_r_rdok$next[0:0]$4822 \$64 + end + sync always + update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$4821 + end + attribute \src "libresoc.v:120571.3-120579.6" + process $proc$libresoc.v:120571$4823 + assign { } { } + assign { } { } + assign $0\rst_l_s_rst$next[0:0]$4824 $1\rst_l_s_rst$next[0:0]$4825 + attribute \src "libresoc.v:120572.5-120572.29" + switch \initial + attribute \src "libresoc.v:120572.9-120572.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rst_l_s_rst$next[0:0]$4825 1'0 + case + assign $1\rst_l_s_rst$next[0:0]$4825 \all_rd + end + sync always + update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$4824 + end + attribute \src "libresoc.v:120580.3-120588.6" + process $proc$libresoc.v:120580$4826 + assign { } { } + assign { } { } + assign $0\rst_l_r_rst$next[0:0]$4827 $1\rst_l_r_rst$next[0:0]$4828 + attribute \src "libresoc.v:120581.5-120581.29" + switch \initial + attribute \src "libresoc.v:120581.9-120581.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rst_l_r_rst$next[0:0]$4828 1'1 + case + assign $1\rst_l_r_rst$next[0:0]$4828 \rst_r + end + sync always + update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$4827 + end + attribute \src "libresoc.v:120589.3-120597.6" + process $proc$libresoc.v:120589$4829 + assign { } { } + assign { } { } + assign $0\opc_l_s_opc$next[0:0]$4830 $1\opc_l_s_opc$next[0:0]$4831 + attribute \src "libresoc.v:120590.5-120590.29" + switch \initial + attribute \src "libresoc.v:120590.9-120590.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\opc_l_s_opc$next[0:0]$4831 1'0 + case + assign $1\opc_l_s_opc$next[0:0]$4831 \cu_issue_i + end + sync always + update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$4830 + end + attribute \src "libresoc.v:120598.3-120606.6" + process $proc$libresoc.v:120598$4832 + assign { } { } + assign { } { } + assign $0\opc_l_r_opc$next[0:0]$4833 $1\opc_l_r_opc$next[0:0]$4834 + attribute \src "libresoc.v:120599.5-120599.29" + switch \initial + attribute \src "libresoc.v:120599.9-120599.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\opc_l_r_opc$next[0:0]$4834 1'1 + case + assign $1\opc_l_r_opc$next[0:0]$4834 \req_done + end + sync always + update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$4833 + end + attribute \src "libresoc.v:120607.3-120615.6" + process $proc$libresoc.v:120607$4835 + assign { } { } + assign { } { } + assign $0\src_l_s_src$next[2:0]$4836 $1\src_l_s_src$next[2:0]$4837 + attribute \src "libresoc.v:120608.5-120608.29" + switch \initial + attribute \src "libresoc.v:120608.9-120608.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_l_s_src$next[2:0]$4837 3'000 + case + assign $1\src_l_s_src$next[2:0]$4837 { \cu_issue_i \cu_issue_i \cu_issue_i } + end + sync always + update \src_l_s_src$next $0\src_l_s_src$next[2:0]$4836 + end + attribute \src "libresoc.v:120616.3-120624.6" + process $proc$libresoc.v:120616$4838 + assign { } { } + assign { } { } + assign $0\src_l_r_src$next[2:0]$4839 $1\src_l_r_src$next[2:0]$4840 + attribute \src "libresoc.v:120617.5-120617.29" + switch \initial + attribute \src "libresoc.v:120617.9-120617.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_l_r_src$next[2:0]$4840 3'111 + case + assign $1\src_l_r_src$next[2:0]$4840 \reset_r + end + sync always + update \src_l_r_src$next $0\src_l_r_src$next[2:0]$4839 + end + attribute \src "libresoc.v:120625.3-120633.6" + process $proc$libresoc.v:120625$4841 + assign { } { } + assign { } { } + assign $0\req_l_s_req$next[3:0]$4842 $1\req_l_s_req$next[3:0]$4843 + attribute \src "libresoc.v:120626.5-120626.29" + switch \initial + attribute \src "libresoc.v:120626.9-120626.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\req_l_s_req$next[3:0]$4843 4'0000 + case + assign $1\req_l_s_req$next[3:0]$4843 \$66 + end + sync always + update \req_l_s_req$next $0\req_l_s_req$next[3:0]$4842 + end + attribute \src "libresoc.v:120634.3-120642.6" + process $proc$libresoc.v:120634$4844 + assign { } { } + assign { } { } + assign $0\req_l_r_req$next[3:0]$4845 $1\req_l_r_req$next[3:0]$4846 + attribute \src "libresoc.v:120635.5-120635.29" + switch \initial + attribute \src "libresoc.v:120635.9-120635.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\req_l_r_req$next[3:0]$4846 4'1111 + case + assign $1\req_l_r_req$next[3:0]$4846 \$68 + end + sync always + update \req_l_r_req$next $0\req_l_r_req$next[3:0]$4845 + end + attribute \src "libresoc.v:120643.3-120681.6" + process $proc$libresoc.v:120643$4847 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\alu_div0_logical_op__data_len$next[3:0]$4848 $1\alu_div0_logical_op__data_len$next[3:0]$4866 + assign $0\alu_div0_logical_op__fn_unit$next[11:0]$4849 $1\alu_div0_logical_op__fn_unit$next[11:0]$4867 + assign { } { } + assign { } { } + assign $0\alu_div0_logical_op__input_carry$next[1:0]$4852 $1\alu_div0_logical_op__input_carry$next[1:0]$4870 + assign $0\alu_div0_logical_op__insn$next[31:0]$4853 $1\alu_div0_logical_op__insn$next[31:0]$4871 + assign $0\alu_div0_logical_op__insn_type$next[6:0]$4854 $1\alu_div0_logical_op__insn_type$next[6:0]$4872 + assign $0\alu_div0_logical_op__invert_in$next[0:0]$4855 $1\alu_div0_logical_op__invert_in$next[0:0]$4873 + assign $0\alu_div0_logical_op__invert_out$next[0:0]$4856 $1\alu_div0_logical_op__invert_out$next[0:0]$4874 + assign $0\alu_div0_logical_op__is_32bit$next[0:0]$4857 $1\alu_div0_logical_op__is_32bit$next[0:0]$4875 + assign $0\alu_div0_logical_op__is_signed$next[0:0]$4858 $1\alu_div0_logical_op__is_signed$next[0:0]$4876 + assign { } { } + assign { } { } + assign $0\alu_div0_logical_op__output_carry$next[0:0]$4861 $1\alu_div0_logical_op__output_carry$next[0:0]$4879 + assign { } { } + assign { } { } + assign $0\alu_div0_logical_op__write_cr0$next[0:0]$4864 $1\alu_div0_logical_op__write_cr0$next[0:0]$4882 + assign $0\alu_div0_logical_op__zero_a$next[0:0]$4865 $1\alu_div0_logical_op__zero_a$next[0:0]$4883 + assign $0\alu_div0_logical_op__imm_data__data$next[63:0]$4850 $2\alu_div0_logical_op__imm_data__data$next[63:0]$4884 + assign $0\alu_div0_logical_op__imm_data__ok$next[0:0]$4851 $2\alu_div0_logical_op__imm_data__ok$next[0:0]$4885 + assign $0\alu_div0_logical_op__oe__oe$next[0:0]$4859 $2\alu_div0_logical_op__oe__oe$next[0:0]$4886 + assign $0\alu_div0_logical_op__oe__ok$next[0:0]$4860 $2\alu_div0_logical_op__oe__ok$next[0:0]$4887 + assign $0\alu_div0_logical_op__rc__ok$next[0:0]$4862 $2\alu_div0_logical_op__rc__ok$next[0:0]$4888 + assign $0\alu_div0_logical_op__rc__rc$next[0:0]$4863 $2\alu_div0_logical_op__rc__rc$next[0:0]$4889 + attribute \src "libresoc.v:120644.5-120644.29" + switch \initial + attribute \src "libresoc.v:120644.9-120644.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\alu_div0_logical_op__insn$next[31:0]$4871 $1\alu_div0_logical_op__data_len$next[3:0]$4866 $1\alu_div0_logical_op__is_signed$next[0:0]$4876 $1\alu_div0_logical_op__is_32bit$next[0:0]$4875 $1\alu_div0_logical_op__output_carry$next[0:0]$4879 $1\alu_div0_logical_op__write_cr0$next[0:0]$4882 $1\alu_div0_logical_op__invert_out$next[0:0]$4874 $1\alu_div0_logical_op__input_carry$next[1:0]$4870 $1\alu_div0_logical_op__zero_a$next[0:0]$4883 $1\alu_div0_logical_op__invert_in$next[0:0]$4873 $1\alu_div0_logical_op__oe__ok$next[0:0]$4878 $1\alu_div0_logical_op__oe__oe$next[0:0]$4877 $1\alu_div0_logical_op__rc__ok$next[0:0]$4880 $1\alu_div0_logical_op__rc__rc$next[0:0]$4881 $1\alu_div0_logical_op__imm_data__ok$next[0:0]$4869 $1\alu_div0_logical_op__imm_data__data$next[63:0]$4868 $1\alu_div0_logical_op__fn_unit$next[11:0]$4867 $1\alu_div0_logical_op__insn_type$next[6:0]$4872 } { \oper_i_alu_div0__insn \oper_i_alu_div0__data_len \oper_i_alu_div0__is_signed \oper_i_alu_div0__is_32bit \oper_i_alu_div0__output_carry \oper_i_alu_div0__write_cr0 \oper_i_alu_div0__invert_out \oper_i_alu_div0__input_carry \oper_i_alu_div0__zero_a \oper_i_alu_div0__invert_in \oper_i_alu_div0__oe__ok \oper_i_alu_div0__oe__oe \oper_i_alu_div0__rc__ok \oper_i_alu_div0__rc__rc \oper_i_alu_div0__imm_data__ok \oper_i_alu_div0__imm_data__data \oper_i_alu_div0__fn_unit \oper_i_alu_div0__insn_type } + case + assign $1\alu_div0_logical_op__data_len$next[3:0]$4866 \alu_div0_logical_op__data_len + assign $1\alu_div0_logical_op__fn_unit$next[11:0]$4867 \alu_div0_logical_op__fn_unit + assign $1\alu_div0_logical_op__imm_data__data$next[63:0]$4868 \alu_div0_logical_op__imm_data__data + assign $1\alu_div0_logical_op__imm_data__ok$next[0:0]$4869 \alu_div0_logical_op__imm_data__ok + assign $1\alu_div0_logical_op__input_carry$next[1:0]$4870 \alu_div0_logical_op__input_carry + assign $1\alu_div0_logical_op__insn$next[31:0]$4871 \alu_div0_logical_op__insn + assign $1\alu_div0_logical_op__insn_type$next[6:0]$4872 \alu_div0_logical_op__insn_type + assign $1\alu_div0_logical_op__invert_in$next[0:0]$4873 \alu_div0_logical_op__invert_in + assign $1\alu_div0_logical_op__invert_out$next[0:0]$4874 \alu_div0_logical_op__invert_out + assign $1\alu_div0_logical_op__is_32bit$next[0:0]$4875 \alu_div0_logical_op__is_32bit + assign $1\alu_div0_logical_op__is_signed$next[0:0]$4876 \alu_div0_logical_op__is_signed + assign $1\alu_div0_logical_op__oe__oe$next[0:0]$4877 \alu_div0_logical_op__oe__oe + assign $1\alu_div0_logical_op__oe__ok$next[0:0]$4878 \alu_div0_logical_op__oe__ok + assign $1\alu_div0_logical_op__output_carry$next[0:0]$4879 \alu_div0_logical_op__output_carry + assign $1\alu_div0_logical_op__rc__ok$next[0:0]$4880 \alu_div0_logical_op__rc__ok + assign $1\alu_div0_logical_op__rc__rc$next[0:0]$4881 \alu_div0_logical_op__rc__rc + assign $1\alu_div0_logical_op__write_cr0$next[0:0]$4882 \alu_div0_logical_op__write_cr0 + assign $1\alu_div0_logical_op__zero_a$next[0:0]$4883 \alu_div0_logical_op__zero_a + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $2\alu_div0_logical_op__imm_data__data$next[63:0]$4884 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\alu_div0_logical_op__imm_data__ok$next[0:0]$4885 1'0 + assign $2\alu_div0_logical_op__rc__rc$next[0:0]$4889 1'0 + assign $2\alu_div0_logical_op__rc__ok$next[0:0]$4888 1'0 + assign $2\alu_div0_logical_op__oe__oe$next[0:0]$4886 1'0 + assign $2\alu_div0_logical_op__oe__ok$next[0:0]$4887 1'0 + case + assign $2\alu_div0_logical_op__imm_data__data$next[63:0]$4884 $1\alu_div0_logical_op__imm_data__data$next[63:0]$4868 + assign $2\alu_div0_logical_op__imm_data__ok$next[0:0]$4885 $1\alu_div0_logical_op__imm_data__ok$next[0:0]$4869 + assign $2\alu_div0_logical_op__oe__oe$next[0:0]$4886 $1\alu_div0_logical_op__oe__oe$next[0:0]$4877 + assign $2\alu_div0_logical_op__oe__ok$next[0:0]$4887 $1\alu_div0_logical_op__oe__ok$next[0:0]$4878 + assign $2\alu_div0_logical_op__rc__ok$next[0:0]$4888 $1\alu_div0_logical_op__rc__ok$next[0:0]$4880 + assign $2\alu_div0_logical_op__rc__rc$next[0:0]$4889 $1\alu_div0_logical_op__rc__rc$next[0:0]$4881 + end + sync always + update \alu_div0_logical_op__data_len$next $0\alu_div0_logical_op__data_len$next[3:0]$4848 + update \alu_div0_logical_op__fn_unit$next $0\alu_div0_logical_op__fn_unit$next[11:0]$4849 + update \alu_div0_logical_op__imm_data__data$next $0\alu_div0_logical_op__imm_data__data$next[63:0]$4850 + update \alu_div0_logical_op__imm_data__ok$next $0\alu_div0_logical_op__imm_data__ok$next[0:0]$4851 + update \alu_div0_logical_op__input_carry$next $0\alu_div0_logical_op__input_carry$next[1:0]$4852 + update \alu_div0_logical_op__insn$next $0\alu_div0_logical_op__insn$next[31:0]$4853 + update \alu_div0_logical_op__insn_type$next $0\alu_div0_logical_op__insn_type$next[6:0]$4854 + update \alu_div0_logical_op__invert_in$next $0\alu_div0_logical_op__invert_in$next[0:0]$4855 + update \alu_div0_logical_op__invert_out$next $0\alu_div0_logical_op__invert_out$next[0:0]$4856 + update \alu_div0_logical_op__is_32bit$next $0\alu_div0_logical_op__is_32bit$next[0:0]$4857 + update \alu_div0_logical_op__is_signed$next $0\alu_div0_logical_op__is_signed$next[0:0]$4858 + update \alu_div0_logical_op__oe__oe$next $0\alu_div0_logical_op__oe__oe$next[0:0]$4859 + update \alu_div0_logical_op__oe__ok$next $0\alu_div0_logical_op__oe__ok$next[0:0]$4860 + update \alu_div0_logical_op__output_carry$next $0\alu_div0_logical_op__output_carry$next[0:0]$4861 + update \alu_div0_logical_op__rc__ok$next $0\alu_div0_logical_op__rc__ok$next[0:0]$4862 + update \alu_div0_logical_op__rc__rc$next $0\alu_div0_logical_op__rc__rc$next[0:0]$4863 + update \alu_div0_logical_op__write_cr0$next $0\alu_div0_logical_op__write_cr0$next[0:0]$4864 + update \alu_div0_logical_op__zero_a$next $0\alu_div0_logical_op__zero_a$next[0:0]$4865 + end + attribute \src "libresoc.v:120682.3-120703.6" + process $proc$libresoc.v:120682$4890 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r0__o$next[63:0]$4891 $2\data_r0__o$next[63:0]$4895 + assign { } { } + assign $0\data_r0__o_ok$next[0:0]$4892 $3\data_r0__o_ok$next[0:0]$4897 + attribute \src "libresoc.v:120683.5-120683.29" + switch \initial + attribute \src "libresoc.v:120683.9-120683.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r0__o_ok$next[0:0]$4894 $1\data_r0__o$next[63:0]$4893 } { \o_ok \alu_div0_o } + case + assign $1\data_r0__o$next[63:0]$4893 \data_r0__o + assign $1\data_r0__o_ok$next[0:0]$4894 \data_r0__o_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r0__o_ok$next[0:0]$4896 $2\data_r0__o$next[63:0]$4895 } 65'00000000000000000000000000000000000000000000000000000000000000000 + case + assign $2\data_r0__o$next[63:0]$4895 $1\data_r0__o$next[63:0]$4893 + assign $2\data_r0__o_ok$next[0:0]$4896 $1\data_r0__o_ok$next[0:0]$4894 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r0__o_ok$next[0:0]$4897 1'0 + case + assign $3\data_r0__o_ok$next[0:0]$4897 $2\data_r0__o_ok$next[0:0]$4896 + end + sync always + update \data_r0__o$next $0\data_r0__o$next[63:0]$4891 + update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$4892 + end + attribute \src "libresoc.v:120704.3-120725.6" + process $proc$libresoc.v:120704$4898 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r1__cr_a$next[3:0]$4899 $2\data_r1__cr_a$next[3:0]$4903 + assign { } { } + assign $0\data_r1__cr_a_ok$next[0:0]$4900 $3\data_r1__cr_a_ok$next[0:0]$4905 + attribute \src "libresoc.v:120705.5-120705.29" + switch \initial + attribute \src "libresoc.v:120705.9-120705.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r1__cr_a_ok$next[0:0]$4902 $1\data_r1__cr_a$next[3:0]$4901 } { \cr_a_ok \alu_div0_cr_a } + case + assign $1\data_r1__cr_a$next[3:0]$4901 \data_r1__cr_a + assign $1\data_r1__cr_a_ok$next[0:0]$4902 \data_r1__cr_a_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r1__cr_a_ok$next[0:0]$4904 $2\data_r1__cr_a$next[3:0]$4903 } 5'00000 + case + assign $2\data_r1__cr_a$next[3:0]$4903 $1\data_r1__cr_a$next[3:0]$4901 + assign $2\data_r1__cr_a_ok$next[0:0]$4904 $1\data_r1__cr_a_ok$next[0:0]$4902 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r1__cr_a_ok$next[0:0]$4905 1'0 + case + assign $3\data_r1__cr_a_ok$next[0:0]$4905 $2\data_r1__cr_a_ok$next[0:0]$4904 + end + sync always + update \data_r1__cr_a$next $0\data_r1__cr_a$next[3:0]$4899 + update \data_r1__cr_a_ok$next $0\data_r1__cr_a_ok$next[0:0]$4900 + end + attribute \src "libresoc.v:120726.3-120747.6" + process $proc$libresoc.v:120726$4906 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r2__xer_ov$next[1:0]$4907 $2\data_r2__xer_ov$next[1:0]$4911 + assign { } { } + assign $0\data_r2__xer_ov_ok$next[0:0]$4908 $3\data_r2__xer_ov_ok$next[0:0]$4913 + attribute \src "libresoc.v:120727.5-120727.29" + switch \initial + attribute \src "libresoc.v:120727.9-120727.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r2__xer_ov_ok$next[0:0]$4910 $1\data_r2__xer_ov$next[1:0]$4909 } { \xer_ov_ok \alu_div0_xer_ov } + case + assign $1\data_r2__xer_ov$next[1:0]$4909 \data_r2__xer_ov + assign $1\data_r2__xer_ov_ok$next[0:0]$4910 \data_r2__xer_ov_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r2__xer_ov_ok$next[0:0]$4912 $2\data_r2__xer_ov$next[1:0]$4911 } 3'000 + case + assign $2\data_r2__xer_ov$next[1:0]$4911 $1\data_r2__xer_ov$next[1:0]$4909 + assign $2\data_r2__xer_ov_ok$next[0:0]$4912 $1\data_r2__xer_ov_ok$next[0:0]$4910 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r2__xer_ov_ok$next[0:0]$4913 1'0 + case + assign $3\data_r2__xer_ov_ok$next[0:0]$4913 $2\data_r2__xer_ov_ok$next[0:0]$4912 + end + sync always + update \data_r2__xer_ov$next $0\data_r2__xer_ov$next[1:0]$4907 + update \data_r2__xer_ov_ok$next $0\data_r2__xer_ov_ok$next[0:0]$4908 + end + attribute \src "libresoc.v:120748.3-120769.6" + process $proc$libresoc.v:120748$4914 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r3__xer_so$next[0:0]$4915 $2\data_r3__xer_so$next[0:0]$4919 + assign { } { } + assign $0\data_r3__xer_so_ok$next[0:0]$4916 $3\data_r3__xer_so_ok$next[0:0]$4921 + attribute \src "libresoc.v:120749.5-120749.29" + switch \initial + attribute \src "libresoc.v:120749.9-120749.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r3__xer_so_ok$next[0:0]$4918 $1\data_r3__xer_so$next[0:0]$4917 } { \xer_so_ok \alu_div0_xer_so } + case + assign $1\data_r3__xer_so$next[0:0]$4917 \data_r3__xer_so + assign $1\data_r3__xer_so_ok$next[0:0]$4918 \data_r3__xer_so_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r3__xer_so_ok$next[0:0]$4920 $2\data_r3__xer_so$next[0:0]$4919 } 2'00 + case + assign $2\data_r3__xer_so$next[0:0]$4919 $1\data_r3__xer_so$next[0:0]$4917 + assign $2\data_r3__xer_so_ok$next[0:0]$4920 $1\data_r3__xer_so_ok$next[0:0]$4918 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r3__xer_so_ok$next[0:0]$4921 1'0 + case + assign $3\data_r3__xer_so_ok$next[0:0]$4921 $2\data_r3__xer_so_ok$next[0:0]$4920 + end + sync always + update \data_r3__xer_so$next $0\data_r3__xer_so$next[0:0]$4915 + update \data_r3__xer_so_ok$next $0\data_r3__xer_so_ok$next[0:0]$4916 + end + attribute \src "libresoc.v:120770.3-120779.6" + process $proc$libresoc.v:120770$4922 + assign { } { } + assign { } { } + assign $0\src_r0$next[63:0]$4923 $1\src_r0$next[63:0]$4924 + attribute \src "libresoc.v:120771.5-120771.29" + switch \initial + attribute \src "libresoc.v:120771.9-120771.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch \src_sel + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r0$next[63:0]$4924 \src_or_imm + case + assign $1\src_r0$next[63:0]$4924 \src_r0 + end + sync always + update \src_r0$next $0\src_r0$next[63:0]$4923 + end + attribute \src "libresoc.v:120780.3-120789.6" + process $proc$libresoc.v:120780$4925 + assign { } { } + assign { } { } + assign $0\src_r1$next[63:0]$4926 $1\src_r1$next[63:0]$4927 + attribute \src "libresoc.v:120781.5-120781.29" + switch \initial + attribute \src "libresoc.v:120781.9-120781.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch \src_sel$82 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r1$next[63:0]$4927 \src_or_imm$85 + case + assign $1\src_r1$next[63:0]$4927 \src_r1 + end + sync always + update \src_r1$next $0\src_r1$next[63:0]$4926 + end + attribute \src "libresoc.v:120790.3-120799.6" + process $proc$libresoc.v:120790$4928 + assign { } { } + assign { } { } + assign $0\src_r2$next[0:0]$4929 $1\src_r2$next[0:0]$4930 + attribute \src "libresoc.v:120791.5-120791.29" + switch \initial + attribute \src "libresoc.v:120791.9-120791.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch \src_l_q_src [2] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r2$next[0:0]$4930 \src3_i + case + assign $1\src_r2$next[0:0]$4930 \src_r2 + end + sync always + update \src_r2$next $0\src_r2$next[0:0]$4929 + end + attribute \src "libresoc.v:120800.3-120808.6" + process $proc$libresoc.v:120800$4931 + assign { } { } + assign { } { } + assign $0\alui_l_r_alui$next[0:0]$4932 $1\alui_l_r_alui$next[0:0]$4933 + attribute \src "libresoc.v:120801.5-120801.29" + switch \initial + attribute \src "libresoc.v:120801.9-120801.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\alui_l_r_alui$next[0:0]$4933 1'1 + case + assign $1\alui_l_r_alui$next[0:0]$4933 \$94 + end + sync always + update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$4932 + end + attribute \src "libresoc.v:120809.3-120817.6" + process $proc$libresoc.v:120809$4934 + assign { } { } + assign { } { } + assign $0\alu_l_r_alu$next[0:0]$4935 $1\alu_l_r_alu$next[0:0]$4936 + attribute \src "libresoc.v:120810.5-120810.29" + switch \initial + attribute \src "libresoc.v:120810.9-120810.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\alu_l_r_alu$next[0:0]$4936 1'1 + case + assign $1\alu_l_r_alu$next[0:0]$4936 \$96 + end + sync always + update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$4935 + end + attribute \src "libresoc.v:120818.3-120827.6" + process $proc$libresoc.v:120818$4937 + assign { } { } + assign { } { } + assign $0\dest1_o[63:0] $1\dest1_o[63:0] + attribute \src "libresoc.v:120819.5-120819.29" + switch \initial + attribute \src "libresoc.v:120819.9-120819.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$122 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest1_o[63:0] \data_r0__o + case + assign $1\dest1_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \dest1_o $0\dest1_o[63:0] + end + attribute \src "libresoc.v:120828.3-120837.6" + process $proc$libresoc.v:120828$4938 + assign { } { } + assign { } { } + assign $0\dest2_o[3:0] $1\dest2_o[3:0] + attribute \src "libresoc.v:120829.5-120829.29" + switch \initial + attribute \src "libresoc.v:120829.9-120829.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$124 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest2_o[3:0] \data_r1__cr_a + case + assign $1\dest2_o[3:0] 4'0000 + end + sync always + update \dest2_o $0\dest2_o[3:0] + end + attribute \src "libresoc.v:120838.3-120847.6" + process $proc$libresoc.v:120838$4939 + assign { } { } + assign { } { } + assign $0\dest3_o[1:0] $1\dest3_o[1:0] + attribute \src "libresoc.v:120839.5-120839.29" + switch \initial + attribute \src "libresoc.v:120839.9-120839.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$126 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest3_o[1:0] \data_r2__xer_ov + case + assign $1\dest3_o[1:0] 2'00 + end + sync always + update \dest3_o $0\dest3_o[1:0] + end + attribute \src "libresoc.v:120848.3-120857.6" + process $proc$libresoc.v:120848$4940 + assign { } { } + assign { } { } + assign $0\dest4_o[0:0] $1\dest4_o[0:0] + attribute \src "libresoc.v:120849.5-120849.29" + switch \initial + attribute \src "libresoc.v:120849.9-120849.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$128 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest4_o[0:0] \data_r3__xer_so + case + assign $1\dest4_o[0:0] 1'0 + end + sync always + update \dest4_o $0\dest4_o[0:0] + end + attribute \src "libresoc.v:120858.3-120866.6" + process $proc$libresoc.v:120858$4941 + assign { } { } + assign { } { } + assign $0\prev_wr_go$next[3:0]$4942 $1\prev_wr_go$next[3:0]$4943 + attribute \src "libresoc.v:120859.5-120859.29" + switch \initial + attribute \src "libresoc.v:120859.9-120859.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\prev_wr_go$next[3:0]$4943 4'0000 + case + assign $1\prev_wr_go$next[3:0]$4943 \$20 + end + sync always + update \prev_wr_go$next $0\prev_wr_go$next[3:0]$4942 + end + connect \$100 $not$libresoc.v:120307$4709_Y + connect \$102 $not$libresoc.v:120308$4710_Y + connect \$104 $and$libresoc.v:120309$4711_Y + connect \$106 $not$libresoc.v:120310$4712_Y + connect \$108 $and$libresoc.v:120311$4713_Y + connect \$10 $and$libresoc.v:120312$4714_Y + connect \$110 $and$libresoc.v:120313$4715_Y + connect \$112 $and$libresoc.v:120314$4716_Y + connect \$114 $and$libresoc.v:120315$4717_Y + connect \$116 $and$libresoc.v:120316$4718_Y + connect \$118 $and$libresoc.v:120317$4719_Y + connect \$120 $and$libresoc.v:120318$4720_Y + connect \$122 $and$libresoc.v:120319$4721_Y + connect \$124 $and$libresoc.v:120320$4722_Y + connect \$126 $and$libresoc.v:120321$4723_Y + connect \$128 $and$libresoc.v:120322$4724_Y + connect \$12 $not$libresoc.v:120323$4725_Y + connect \$14 $and$libresoc.v:120324$4726_Y + connect \$16 $not$libresoc.v:120325$4727_Y + connect \$18 $and$libresoc.v:120326$4728_Y + connect \$20 $and$libresoc.v:120327$4729_Y + connect \$24 $not$libresoc.v:120328$4730_Y + connect \$26 $and$libresoc.v:120329$4731_Y + connect \$23 $reduce_or$libresoc.v:120330$4732_Y + connect \$22 $not$libresoc.v:120331$4733_Y + connect \$2 $and$libresoc.v:120332$4734_Y + connect \$30 $and$libresoc.v:120333$4735_Y + connect \$32 $reduce_or$libresoc.v:120334$4736_Y + connect \$34 $reduce_or$libresoc.v:120335$4737_Y + connect \$36 $or$libresoc.v:120336$4738_Y + connect \$38 $not$libresoc.v:120337$4739_Y + connect \$40 $and$libresoc.v:120338$4740_Y + connect \$42 $and$libresoc.v:120339$4741_Y + connect \$44 $eq$libresoc.v:120340$4742_Y + connect \$46 $and$libresoc.v:120341$4743_Y + connect \$48 $eq$libresoc.v:120342$4744_Y + connect \$50 $and$libresoc.v:120343$4745_Y + connect \$52 $and$libresoc.v:120344$4746_Y + connect \$54 $and$libresoc.v:120345$4747_Y + connect \$56 $or$libresoc.v:120346$4748_Y + connect \$58 $or$libresoc.v:120347$4749_Y + connect \$5 $not$libresoc.v:120348$4750_Y + connect \$60 $or$libresoc.v:120349$4751_Y + connect \$62 $or$libresoc.v:120350$4752_Y + connect \$64 $and$libresoc.v:120351$4753_Y + connect \$66 $and$libresoc.v:120352$4754_Y + connect \$68 $or$libresoc.v:120353$4755_Y + connect \$70 $and$libresoc.v:120354$4756_Y + connect \$72 $and$libresoc.v:120355$4757_Y + connect \$74 $and$libresoc.v:120356$4758_Y + connect \$76 $and$libresoc.v:120357$4759_Y + connect \$78 $ternary$libresoc.v:120358$4760_Y + connect \$7 $or$libresoc.v:120359$4761_Y + connect \$80 $ternary$libresoc.v:120360$4762_Y + connect \$83 $ternary$libresoc.v:120361$4763_Y + connect \$86 $ternary$libresoc.v:120362$4764_Y + connect \$88 $ternary$libresoc.v:120363$4765_Y + connect \$4 $reduce_and$libresoc.v:120364$4766_Y + connect \$90 $ternary$libresoc.v:120365$4767_Y + connect \$92 $ternary$libresoc.v:120366$4768_Y + connect \$94 $and$libresoc.v:120367$4769_Y + connect \$96 $and$libresoc.v:120368$4770_Y + connect \$98 $and$libresoc.v:120369$4771_Y + connect \cu_go_die_i 1'0 + connect \cu_shadown_i 1'1 + connect \cu_wr__rel_o \$120 + connect \cu_rd__rel_o \$108 + connect \cu_busy_o \opc_l_q_opc + connect \alu_l_s_alu \all_rd_pulse + connect \alu_div0_n_ready_i \alu_l_q_alu + connect \alui_l_s_alui \all_rd_pulse + connect \alu_div0_p_valid_i \alui_l_q_alui + connect \alu_div0_xer_so$1 \$92 + connect \alu_div0_rb \$90 + connect \alu_div0_ra \$88 + connect \src_or_imm$85 \$86 + connect \src_sel$82 \$83 + connect \src_or_imm \$80 + connect \src_sel \$78 + connect \cu_wrmask_o { \$76 \$74 \$72 \$70 } + connect \reset_r \$62 + connect \reset_w \$60 + connect \rst_r \$58 + connect \reset \$56 + connect \wr_any \$36 + connect \cu_done_o \$30 + connect \alu_pulsem { \alu_pulse \alu_pulse \alu_pulse \alu_pulse } + connect \alu_pulse \alu_done_rise + connect \alu_done_rise \$18 + connect \alu_done_dly$next \alu_done + connect \alu_done \alu_div0_n_valid_o + connect \all_rd_pulse \all_rd_rise + connect \all_rd_rise \$14 + connect \all_rd_dly$next \all_rd + connect \all_rd \$10 +end +attribute \src "libresoc.v:120903.1-120912.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_0.div_state_init" +attribute \generator "nMigen" +module \div_state_init + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:89" + wire width 128 input 3 \dividend + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:105" + wire width 128 output 2 \o_dividend_quotient + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:103" + wire width 7 output 1 \o_q_bits_known + connect \o_dividend_quotient \dividend + connect \o_q_bits_known 7'0000000 +end +attribute \src "libresoc.v:120916.1-120998.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_0.div_state_next" +attribute \generator "nMigen" +module \div_state_next + attribute \src "libresoc.v:120917.7-120917.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:120982.3-120993.6" + wire width 128 $0\o_dividend_quotient[127:0] + attribute \src "libresoc.v:120970.3-120981.6" + wire width 7 $0\o_q_bits_known[6:0] + attribute \src "libresoc.v:120958.3-120969.6" + wire width 128 $0\value[127:0] + attribute \src "libresoc.v:120982.3-120993.6" + wire width 128 $1\o_dividend_quotient[127:0] + attribute \src "libresoc.v:120970.3-120981.6" + wire width 7 $1\o_q_bits_known[6:0] + attribute \src "libresoc.v:120958.3-120969.6" + wire width 128 $1\value[127:0] + attribute \src "libresoc.v:120952.18-120952.106" + wire width 8 $add$libresoc.v:120952$4989_Y + attribute \src "libresoc.v:120953.18-120953.109" + wire $eq$libresoc.v:120953$4990_Y + attribute \src "libresoc.v:120957.17-120957.108" + wire $eq$libresoc.v:120957$4994_Y + attribute \src "libresoc.v:120956.17-120956.101" + wire $not$libresoc.v:120956$4993_Y + attribute \src "libresoc.v:120954.17-120954.101" + wire width 127 $sshl$libresoc.v:120954$4991_Y + attribute \src "libresoc.v:120955.17-120955.109" + wire width 129 $sub$libresoc.v:120955$4992_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:67" + wire width 129 \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:81" + wire width 8 \$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:81" + wire width 8 \$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:109" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:67" + wire width 127 \$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:67" + wire width 129 \$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:70" + wire \$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:109" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:64" + wire width 128 \difference + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:59" + wire width 64 input 4 \divisor + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:105" + wire width 128 input 3 \i_dividend_quotient + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:103" + wire width 7 input 2 \i_q_bits_known + attribute \src "libresoc.v:120917.7-120917.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:68" + wire \next_quotient_bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:105" + wire width 128 output 5 \o_dividend_quotient + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:103" + wire width 7 output 1 \o_q_bits_known + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:71" + wire width 128 \value + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:81" + cell $add $add$libresoc.v:120952$4989 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 8 + connect \A \i_q_bits_known + connect \B 1'1 + connect \Y $add$libresoc.v:120952$4989_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:109" + cell $eq $eq$libresoc.v:120953$4990 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \i_q_bits_known + connect \B 7'1000000 + connect \Y $eq$libresoc.v:120953$4990_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:109" + cell $eq $eq$libresoc.v:120957$4994 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \i_q_bits_known + connect \B 7'1000000 + connect \Y $eq$libresoc.v:120957$4994_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:70" + cell $not $not$libresoc.v:120956$4993 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \difference [127] + connect \Y $not$libresoc.v:120956$4993_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:67" + cell $sshl $sshl$libresoc.v:120954$4991 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 127 + connect \A \divisor + connect \B 6'111111 + connect \Y $sshl$libresoc.v:120954$4991_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:67" + cell $sub $sub$libresoc.v:120955$4992 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 127 + parameter \Y_WIDTH 129 + connect \A \i_dividend_quotient + connect \B \$2 + connect \Y $sub$libresoc.v:120955$4992_Y + end + attribute \src "libresoc.v:120917.7-120917.20" + process $proc$libresoc.v:120917$4998 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:120958.3-120969.6" + process $proc$libresoc.v:120958$4995 + assign { } { } + assign $0\value[127:0] $1\value[127:0] + attribute \src "libresoc.v:120959.5-120959.29" + switch \initial + attribute \src "libresoc.v:120959.9-120959.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:72" + switch \next_quotient_bit + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\value[127:0] \difference + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\value[127:0] \i_dividend_quotient + end + sync always + update \value $0\value[127:0] + end + attribute \src "libresoc.v:120970.3-120981.6" + process $proc$libresoc.v:120970$4996 + assign { } { } + assign $0\o_q_bits_known[6:0] $1\o_q_bits_known[6:0] + attribute \src "libresoc.v:120971.5-120971.29" + switch \initial + attribute \src "libresoc.v:120971.9-120971.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:77" + switch \$8 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\o_q_bits_known[6:0] \i_q_bits_known + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\o_q_bits_known[6:0] \$10 [6:0] + end + sync always + update \o_q_bits_known $0\o_q_bits_known[6:0] + end + attribute \src "libresoc.v:120982.3-120993.6" + process $proc$libresoc.v:120982$4997 + assign { } { } + assign $0\o_dividend_quotient[127:0] $1\o_dividend_quotient[127:0] + attribute \src "libresoc.v:120983.5-120983.29" + switch \initial + attribute \src "libresoc.v:120983.9-120983.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:77" + switch \$13 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\o_dividend_quotient[127:0] \i_dividend_quotient + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\o_dividend_quotient[127:0] { \value [126:0] \next_quotient_bit } + end + sync always + update \o_dividend_quotient $0\o_dividend_quotient[127:0] + end + connect \$11 $add$libresoc.v:120952$4989_Y + connect \$13 $eq$libresoc.v:120953$4990_Y + connect \$2 $sshl$libresoc.v:120954$4991_Y + connect \$4 $sub$libresoc.v:120955$4992_Y + connect \$6 $not$libresoc.v:120956$4993_Y + connect \$8 $eq$libresoc.v:120957$4994_Y + connect \$1 \$4 + connect \$10 \$11 + connect \next_quotient_bit \$6 + connect \difference \$4 [127:0] +end +attribute \src "libresoc.v:121002.1-121173.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fast" +attribute \generator "nMigen" +module \fast + attribute \src "libresoc.v:121097.3-121103.6" + wire width 3 $0$memwr$\memory$libresoc.v:121101$5007_ADDR[2:0]$5015 + attribute \src "libresoc.v:121097.3-121103.6" + wire width 64 $0$memwr$\memory$libresoc.v:121101$5007_DATA[63:0]$5016 + attribute \src "libresoc.v:121097.3-121103.6" + wire width 64 $0$memwr$\memory$libresoc.v:121101$5007_EN[63:0]$5017 + attribute \src "libresoc.v:121097.3-121103.6" + wire width 3 $0$memwr$\memory$libresoc.v:121102$5008_ADDR[2:0]$5018 + attribute \src "libresoc.v:121097.3-121103.6" + wire width 64 $0$memwr$\memory$libresoc.v:121102$5008_DATA[63:0]$5019 + attribute \src "libresoc.v:121097.3-121103.6" + wire width 64 $0$memwr$\memory$libresoc.v:121102$5008_EN[63:0]$5020 + attribute \src "libresoc.v:121097.3-121103.6" + wire width 3 $0\_0_[2:0] + attribute \src "libresoc.v:121097.3-121103.6" + wire width 3 $0\_1_[2:0] + attribute \src "libresoc.v:121097.3-121103.6" + wire width 3 $0\_2_[2:0] + attribute \src "libresoc.v:121003.7-121003.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:121154.3-121163.6" + wire width 64 $0\issue__data_o[63:0] + attribute \src "libresoc.v:121126.3-121134.6" + wire $0\ren_delay$10$next[0:0]$5029 + attribute \src "libresoc.v:121079.3-121080.43" + wire $0\ren_delay$10[0:0]$5012 + attribute \src "libresoc.v:121054.7-121054.28" + wire $0\ren_delay$10[0:0]$5049 + attribute \src "libresoc.v:121145.3-121153.6" + wire $0\ren_delay$11$next[0:0]$5033 + attribute \src "libresoc.v:121077.3-121078.43" + wire $0\ren_delay$11[0:0]$5010 + attribute \src "libresoc.v:121058.7-121058.28" + wire $0\ren_delay$11[0:0]$5051 + attribute \src "libresoc.v:121107.3-121115.6" + wire $0\ren_delay$next[0:0]$5025 + attribute \src "libresoc.v:121081.3-121082.35" + wire $0\ren_delay[0:0] + attribute \src "libresoc.v:121116.3-121125.6" + wire width 64 $0\src1__data_o[63:0] + attribute \src "libresoc.v:121135.3-121144.6" + wire width 64 $0\src2__data_o[63:0] + attribute \src "libresoc.v:121154.3-121163.6" + wire width 64 $1\issue__data_o[63:0] + attribute \src "libresoc.v:121126.3-121134.6" + wire $1\ren_delay$10$next[0:0]$5030 + attribute \src "libresoc.v:121145.3-121153.6" + wire $1\ren_delay$11$next[0:0]$5034 + attribute \src "libresoc.v:121107.3-121115.6" + wire $1\ren_delay$next[0:0]$5026 + attribute \src "libresoc.v:121052.7-121052.23" + wire $1\ren_delay[0:0] + attribute \src "libresoc.v:121116.3-121125.6" + wire width 64 $1\src1__data_o[63:0] + attribute \src "libresoc.v:121135.3-121144.6" + wire width 64 $1\src2__data_o[63:0] + attribute \src "libresoc.v:121104.26-121104.32" + wire width 64 $memrd$\memory$libresoc.v:121104$5021_DATA + attribute \src "libresoc.v:121105.30-121105.36" + wire width 64 $memrd$\memory$libresoc.v:121105$5022_DATA + attribute \src "libresoc.v:121106.30-121106.36" + wire width 64 $memrd$\memory$libresoc.v:121106$5023_DATA + attribute \src "libresoc.v:0.0-0.0" + wire width 3 $memwr$\memory$libresoc.v:121101$5007_ADDR + attribute \src "libresoc.v:0.0-0.0" + wire width 64 $memwr$\memory$libresoc.v:121101$5007_DATA + attribute \src "libresoc.v:0.0-0.0" + wire width 64 $memwr$\memory$libresoc.v:121101$5007_EN + attribute \src "libresoc.v:0.0-0.0" + wire width 3 $memwr$\memory$libresoc.v:121102$5008_ADDR + attribute \src "libresoc.v:0.0-0.0" + wire width 64 $memwr$\memory$libresoc.v:121102$5008_DATA + attribute \src "libresoc.v:0.0-0.0" + wire width 64 $memwr$\memory$libresoc.v:121102$5008_EN + attribute \src "libresoc.v:121094.13-121094.16" + wire width 3 \_0_ + attribute \src "libresoc.v:121095.13-121095.16" + wire width 3 \_1_ + attribute \src "libresoc.v:121096.13-121096.16" + wire width 3 \_2_ + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 17 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 16 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 3 input 14 \dest1__addr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 input 13 \dest1__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 15 \dest1__wen + attribute \src "libresoc.v:121003.7-121003.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 3 input 1 \issue__addr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 3 input 4 \issue__addr$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 input 6 \issue__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 output 3 \issue__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 2 \issue__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 5 \issue__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" + wire width 3 \memory_r_addr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" + wire width 3 \memory_r_addr$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" + wire width 3 \memory_r_addr$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" + wire width 64 \memory_r_data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" + wire width 64 \memory_r_data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" + wire width 64 \memory_r_data$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" + wire width 3 \memory_w_addr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" + wire width 3 \memory_w_addr$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" + wire width 64 \memory_w_data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" + wire width 64 \memory_w_data$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" + wire \memory_w_en + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" + wire \memory_w_en$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" + wire \ren_delay + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" + wire \ren_delay$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" + wire \ren_delay$10$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" + wire \ren_delay$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" + wire \ren_delay$11$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" + wire \ren_delay$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 3 input 8 \src1__addr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 output 7 \src1__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 9 \src1__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 3 input 11 \src2__addr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 output 10 \src2__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 12 \src2__ren + attribute \src "libresoc.v:121083.14-121083.20" + memory width 64 size 8 \memory + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5036 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5036 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 0 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5037 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5037 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 1 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5038 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5038 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 2 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5039 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5039 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 3 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5040 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5040 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 4 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5041 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5041 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 5 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5042 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5042 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 6 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5043 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5043 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 7 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:121104.26-121104.32" + cell $memrd $memrd$\memory$libresoc.v:121104$5021 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\memory" + parameter \TRANSPARENT 0 + parameter \WIDTH 64 + connect \ADDR \_0_ + connect \CLK 1'x + connect \DATA $memrd$\memory$libresoc.v:121104$5021_DATA + connect \EN 1'x + end + attribute \src "libresoc.v:121105.30-121105.36" + cell $memrd $memrd$\memory$libresoc.v:121105$5022 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\memory" + parameter \TRANSPARENT 0 + parameter \WIDTH 64 + connect \ADDR \_1_ + connect \CLK 1'x + connect \DATA $memrd$\memory$libresoc.v:121105$5022_DATA + connect \EN 1'x + end + attribute \src "libresoc.v:121106.30-121106.36" + cell $memrd $memrd$\memory$libresoc.v:121106$5023 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\memory" + parameter \TRANSPARENT 0 + parameter \WIDTH 64 + connect \ADDR \_2_ + connect \CLK 1'x + connect \DATA $memrd$\memory$libresoc.v:121106$5023_DATA + connect \EN 1'x + end + attribute \src "libresoc.v:0.0-0.0" + cell $memwr $memwr$\memory$libresoc.v:0$5044 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\memory" + parameter \PRIORITY 5044 + parameter \WIDTH 64 + connect \ADDR $memwr$\memory$libresoc.v:121101$5007_ADDR + connect \CLK 1'x + connect \DATA $memwr$\memory$libresoc.v:121101$5007_DATA + connect \EN $memwr$\memory$libresoc.v:121101$5007_EN + end + attribute \src "libresoc.v:0.0-0.0" + cell $memwr $memwr$\memory$libresoc.v:0$5045 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\memory" + parameter \PRIORITY 5045 + parameter \WIDTH 64 + connect \ADDR $memwr$\memory$libresoc.v:121102$5008_ADDR + connect \CLK 1'x + connect \DATA $memwr$\memory$libresoc.v:121102$5008_DATA + connect \EN $memwr$\memory$libresoc.v:121102$5008_EN + end + attribute \src "libresoc.v:0.0-0.0" + process $proc$libresoc.v:0$5052 + sync always + sync init + end + attribute \src "libresoc.v:121003.7-121003.20" + process $proc$libresoc.v:121003$5046 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:121052.7-121052.23" + process $proc$libresoc.v:121052$5047 + assign { } { } + assign $1\ren_delay[0:0] 1'0 + sync always + sync init + update \ren_delay $1\ren_delay[0:0] + end + attribute \src "libresoc.v:121054.7-121054.28" + process $proc$libresoc.v:121054$5048 + assign { } { } + assign $0\ren_delay$10[0:0]$5049 1'0 + sync always + sync init + update \ren_delay$10 $0\ren_delay$10[0:0]$5049 + end + attribute \src "libresoc.v:121058.7-121058.28" + process $proc$libresoc.v:121058$5050 + assign { } { } + assign $0\ren_delay$11[0:0]$5051 1'0 + sync always + sync init + update \ren_delay$11 $0\ren_delay$11[0:0]$5051 + end + attribute \src "libresoc.v:121077.3-121078.43" + process $proc$libresoc.v:121077$5009 + assign { } { } + assign $0\ren_delay$11[0:0]$5010 \ren_delay$11$next + sync posedge \coresync_clk + update \ren_delay$11 $0\ren_delay$11[0:0]$5010 + end + attribute \src "libresoc.v:121079.3-121080.43" + process $proc$libresoc.v:121079$5011 + assign { } { } + assign $0\ren_delay$10[0:0]$5012 \ren_delay$10$next + sync posedge \coresync_clk + update \ren_delay$10 $0\ren_delay$10[0:0]$5012 + end + attribute \src "libresoc.v:121081.3-121082.35" + process $proc$libresoc.v:121081$5013 + assign { } { } + assign $0\ren_delay[0:0] \ren_delay$next + sync posedge \coresync_clk + update \ren_delay $0\ren_delay[0:0] + end + attribute \src "libresoc.v:121097.3-121103.6" + process $proc$libresoc.v:121097$5014 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\memory$libresoc.v:121102$5008_ADDR[2:0]$5018 3'xxx + assign $0$memwr$\memory$libresoc.v:121102$5008_DATA[63:0]$5019 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\memory$libresoc.v:121102$5008_EN[63:0]$5020 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\memory$libresoc.v:121101$5007_ADDR[2:0]$5015 3'xxx + assign $0$memwr$\memory$libresoc.v:121101$5007_DATA[63:0]$5016 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\memory$libresoc.v:121101$5007_EN[63:0]$5017 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\_0_[2:0] \src1__addr + assign $0\_1_[2:0] \src2__addr + assign $0\_2_[2:0] \issue__addr + attribute \src "libresoc.v:121101.5-121101.62" + switch \issue__wen + attribute \src "libresoc.v:121101.9-121101.19" + case 1'1 + assign $0$memwr$\memory$libresoc.v:121101$5007_ADDR[2:0]$5015 \issue__addr$1 + assign $0$memwr$\memory$libresoc.v:121101$5007_DATA[63:0]$5016 \issue__data_i + assign $0$memwr$\memory$libresoc.v:121101$5007_EN[63:0]$5017 64'1111111111111111111111111111111111111111111111111111111111111111 + case + end + attribute \src "libresoc.v:121102.5-121102.58" + switch \dest1__wen + attribute \src "libresoc.v:121102.9-121102.19" + case 1'1 + assign $0$memwr$\memory$libresoc.v:121102$5008_ADDR[2:0]$5018 \dest1__addr + assign $0$memwr$\memory$libresoc.v:121102$5008_DATA[63:0]$5019 \dest1__data_i + assign $0$memwr$\memory$libresoc.v:121102$5008_EN[63:0]$5020 64'1111111111111111111111111111111111111111111111111111111111111111 + case + end + sync posedge \coresync_clk + update \_0_ $0\_0_[2:0] + update \_1_ $0\_1_[2:0] + update \_2_ $0\_2_[2:0] + update $memwr$\memory$libresoc.v:121101$5007_ADDR $0$memwr$\memory$libresoc.v:121101$5007_ADDR[2:0]$5015 + update $memwr$\memory$libresoc.v:121101$5007_DATA $0$memwr$\memory$libresoc.v:121101$5007_DATA[63:0]$5016 + update $memwr$\memory$libresoc.v:121101$5007_EN $0$memwr$\memory$libresoc.v:121101$5007_EN[63:0]$5017 + update $memwr$\memory$libresoc.v:121102$5008_ADDR $0$memwr$\memory$libresoc.v:121102$5008_ADDR[2:0]$5018 + update $memwr$\memory$libresoc.v:121102$5008_DATA $0$memwr$\memory$libresoc.v:121102$5008_DATA[63:0]$5019 + update $memwr$\memory$libresoc.v:121102$5008_EN $0$memwr$\memory$libresoc.v:121102$5008_EN[63:0]$5020 + end + attribute \src "libresoc.v:121107.3-121115.6" + process $proc$libresoc.v:121107$5024 + assign { } { } + assign { } { } + assign $0\ren_delay$next[0:0]$5025 $1\ren_delay$next[0:0]$5026 + attribute \src "libresoc.v:121108.5-121108.29" + switch \initial + attribute \src "libresoc.v:121108.9-121108.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ren_delay$next[0:0]$5026 1'0 + case + assign $1\ren_delay$next[0:0]$5026 \src1__ren + end + sync always + update \ren_delay$next $0\ren_delay$next[0:0]$5025 + end + attribute \src "libresoc.v:121116.3-121125.6" + process $proc$libresoc.v:121116$5027 + assign { } { } + assign { } { } + assign $0\src1__data_o[63:0] $1\src1__data_o[63:0] + attribute \src "libresoc.v:121117.5-121117.29" + switch \initial + attribute \src "libresoc.v:121117.9-121117.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" + switch \ren_delay + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src1__data_o[63:0] \memory_r_data + case + assign $1\src1__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \src1__data_o $0\src1__data_o[63:0] + end + attribute \src "libresoc.v:121126.3-121134.6" + process $proc$libresoc.v:121126$5028 + assign { } { } + assign { } { } + assign $0\ren_delay$10$next[0:0]$5029 $1\ren_delay$10$next[0:0]$5030 + attribute \src "libresoc.v:121127.5-121127.29" + switch \initial + attribute \src "libresoc.v:121127.9-121127.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ren_delay$10$next[0:0]$5030 1'0 + case + assign $1\ren_delay$10$next[0:0]$5030 \src2__ren + end + sync always + update \ren_delay$10$next $0\ren_delay$10$next[0:0]$5029 + end + attribute \src "libresoc.v:121135.3-121144.6" + process $proc$libresoc.v:121135$5031 + assign { } { } + assign { } { } + assign $0\src2__data_o[63:0] $1\src2__data_o[63:0] + attribute \src "libresoc.v:121136.5-121136.29" + switch \initial + attribute \src "libresoc.v:121136.9-121136.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" + switch \ren_delay$10 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src2__data_o[63:0] \memory_r_data$4 + case + assign $1\src2__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \src2__data_o $0\src2__data_o[63:0] + end + attribute \src "libresoc.v:121145.3-121153.6" + process $proc$libresoc.v:121145$5032 + assign { } { } + assign { } { } + assign $0\ren_delay$11$next[0:0]$5033 $1\ren_delay$11$next[0:0]$5034 + attribute \src "libresoc.v:121146.5-121146.29" + switch \initial + attribute \src "libresoc.v:121146.9-121146.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ren_delay$11$next[0:0]$5034 1'0 + case + assign $1\ren_delay$11$next[0:0]$5034 \issue__ren + end + sync always + update \ren_delay$11$next $0\ren_delay$11$next[0:0]$5033 + end + attribute \src "libresoc.v:121154.3-121163.6" + process $proc$libresoc.v:121154$5035 + assign { } { } + assign { } { } + assign $0\issue__data_o[63:0] $1\issue__data_o[63:0] + attribute \src "libresoc.v:121155.5-121155.29" + switch \initial + attribute \src "libresoc.v:121155.9-121155.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" + switch \ren_delay$11 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\issue__data_o[63:0] \memory_r_data$6 + case + assign $1\issue__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \issue__data_o $0\issue__data_o[63:0] + end + connect \memory_r_data $memrd$\memory$libresoc.v:121104$5021_DATA + connect \memory_r_data$4 $memrd$\memory$libresoc.v:121105$5022_DATA + connect \memory_r_data$6 $memrd$\memory$libresoc.v:121106$5023_DATA + connect \memory_w_data$9 \issue__data_i + connect \memory_w_en$7 \issue__wen + connect \memory_w_addr$8 \issue__addr$1 + connect \memory_w_data \dest1__data_i + connect \memory_w_en \dest1__wen + connect \memory_w_addr \dest1__addr + connect \memory_r_addr$5 \issue__addr + connect \memory_r_addr$3 \src2__addr + connect \memory_r_addr \src1__addr +end +attribute \src "libresoc.v:121177.1-123070.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus" +attribute \generator "nMigen" +module \fus + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 321 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 308 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 254 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 255 \cr_a_ok$110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 256 \cr_a_ok$111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 257 \cr_a_ok$112 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 258 \cr_a_ok$113 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 259 \cr_a_ok$114 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire input 2 \cu_ad__go_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire output 3 \cu_ad__rel_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" + wire output 24 \cu_busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" + wire output 73 \cu_busy_o$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" + wire output 80 \cu_busy_o$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" + wire output 101 \cu_busy_o$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" + wire output 30 \cu_busy_o$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" + wire output 116 \cu_busy_o$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" + wire output 135 \cu_busy_o$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" + wire output 154 \cu_busy_o$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" + wire output 41 \cu_busy_o$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" + wire output 52 \cu_busy_o$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" + wire input 23 \cu_issue_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" + wire input 29 \cu_issue_i$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" + wire input 72 \cu_issue_i$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" + wire input 79 \cu_issue_i$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" + wire input 100 \cu_issue_i$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" + wire input 115 \cu_issue_i$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" + wire input 134 \cu_issue_i$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" + wire input 153 \cu_issue_i$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" + wire input 40 \cu_issue_i$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" + wire input 51 \cu_issue_i$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 4 input 157 \cu_rd__go_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 6 input 160 \cu_rd__go_i$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 4 input 163 \cu_rd__go_i$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 input 166 \cu_rd__go_i$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 6 input 169 \cu_rd__go_i$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 input 172 \cu_rd__go_i$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 input 175 \cu_rd__go_i$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 5 input 178 \cu_rd__go_i$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 input 181 \cu_rd__go_i$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 input 206 \cu_rd__go_i$70 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 4 output 156 \cu_rd__rel_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 6 output 159 \cu_rd__rel_o$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 4 output 162 \cu_rd__rel_o$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 output 165 \cu_rd__rel_o$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 6 output 168 \cu_rd__rel_o$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 output 171 \cu_rd__rel_o$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 output 174 \cu_rd__rel_o$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 5 output 177 \cu_rd__rel_o$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 output 180 \cu_rd__rel_o$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 output 205 \cu_rd__rel_o$69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" + wire width 4 input 25 \cu_rdmaskn_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" + wire width 3 input 74 \cu_rdmaskn_i$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" + wire width 6 input 81 \cu_rdmaskn_i$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" + wire width 3 input 102 \cu_rdmaskn_i$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" + wire width 3 input 117 \cu_rdmaskn_i$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" + wire width 5 input 136 \cu_rdmaskn_i$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" + wire width 3 input 155 \cu_rdmaskn_i$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" + wire width 6 input 31 \cu_rdmaskn_i$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" + wire width 3 input 42 \cu_rdmaskn_i$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" + wire width 4 input 53 \cu_rdmaskn_i$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire input 4 \cu_st__go_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire output 1 \cu_st__rel_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 5 input 218 \cu_wr__go_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 input 239 \cu_wr__go_i$100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 2 input 241 \cu_wr__go_i$102 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 input 290 \cu_wr__go_i$137 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 input 221 \cu_wr__go_i$82 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 5 input 224 \cu_wr__go_i$85 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 2 input 227 \cu_wr__go_i$88 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 6 input 230 \cu_wr__go_i$91 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 4 input 233 \cu_wr__go_i$94 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 4 input 236 \cu_wr__go_i$97 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 5 output 217 \cu_wr__rel_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 2 output 240 \cu_wr__rel_o$101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 output 289 \cu_wr__rel_o$136 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 output 220 \cu_wr__rel_o$81 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 5 output 223 \cu_wr__rel_o$84 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 2 output 226 \cu_wr__rel_o$87 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 6 output 229 \cu_wr__rel_o$90 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 4 output 232 \cu_wr__rel_o$93 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 4 output 235 \cu_wr__rel_o$96 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 output 238 \cu_wr__rel_o$99 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 242 \dest1_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 243 \dest1_o$103 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 244 \dest1_o$104 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 245 \dest1_o$105 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 246 \dest1_o$106 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 247 \dest1_o$107 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 248 \dest1_o$108 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 249 \dest1_o$109 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 295 \dest1_o$141 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 32 output 253 \dest2_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 4 output 260 \dest2_o$115 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 4 output 262 \dest2_o$116 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 4 output 263 \dest2_o$117 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 4 output 264 \dest2_o$118 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 4 output 265 \dest2_o$119 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 296 \dest2_o$142 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 298 \dest2_o$144 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 307 \dest2_o$150 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 4 output 261 \dest3_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 2 output 269 \dest3_o$122 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 2 output 271 \dest3_o$123 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 2 output 278 \dest3_o$127 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 2 output 279 \dest3_o$128 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 297 \dest3_o$143 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 299 \dest3_o$145 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 302 \dest3_o$147 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 2 output 276 \dest4_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire output 285 \dest4_o$133 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire output 286 \dest4_o$134 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire output 287 \dest4_o$135 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 303 \dest4_o$148 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 2 output 277 \dest5_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire output 284 \dest5_o$132 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 305 \dest5_o$149 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 2 output 270 \dest6_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 251 \ea + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 288 \fast1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 291 \fast1_ok$138 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 292 \fast1_ok$139 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 293 \fast2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 294 \fast2_ok$140 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 252 \full_cr_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:110" + wire input 315 \ldst_port0_addr_exc_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 96 output 313 \ldst_port0_addr_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 314 \ldst_port0_addr_i_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:109" + wire input 316 \ldst_port0_addr_ok_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:105" + wire input 309 \ldst_port0_busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102" + wire width 4 output 312 \ldst_port0_data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:98" + wire output 310 \ldst_port0_is_ld_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" + wire output 311 \ldst_port0_is_st_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 input 317 \ldst_port0_ld_data_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire input 318 \ldst_port0_ld_data_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 319 \ldst_port0_st_data_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 320 \ldst_port0_st_data_i_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 304 \msr_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 300 \nia_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 301 \nia_ok$146 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 250 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 216 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 219 \o_ok$80 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 222 \o_ok$83 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 225 \o_ok$86 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 228 \o_ok$89 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 231 \o_ok$92 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 234 \o_ok$95 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 237 \o_ok$98 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 21 \oper_i_alu_alu0__data_len + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 6 \oper_i_alu_alu0__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 7 \oper_i_alu_alu0__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \oper_i_alu_alu0__imm_data__ok + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 17 \oper_i_alu_alu0__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 22 \oper_i_alu_alu0__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 5 \oper_i_alu_alu0__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \oper_i_alu_alu0__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 15 \oper_i_alu_alu0__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 19 \oper_i_alu_alu0__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 20 \oper_i_alu_alu0__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 11 \oper_i_alu_alu0__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \oper_i_alu_alu0__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 18 \oper_i_alu_alu0__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \oper_i_alu_alu0__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \oper_i_alu_alu0__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 16 \oper_i_alu_alu0__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \oper_i_alu_alu0__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 32 \oper_i_alu_branch0__cia + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 34 \oper_i_alu_branch0__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 36 \oper_i_alu_branch0__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 37 \oper_i_alu_branch0__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 35 \oper_i_alu_branch0__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 33 \oper_i_alu_branch0__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 39 \oper_i_alu_branch0__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 38 \oper_i_alu_branch0__lk + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 27 \oper_i_alu_cr0__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 28 \oper_i_alu_cr0__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 26 \oper_i_alu_cr0__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 98 \oper_i_alu_div0__data_len + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 83 \oper_i_alu_div0__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 84 \oper_i_alu_div0__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 85 \oper_i_alu_div0__imm_data__ok + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 92 \oper_i_alu_div0__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 99 \oper_i_alu_div0__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 82 \oper_i_alu_div0__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 90 \oper_i_alu_div0__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 93 \oper_i_alu_div0__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 96 \oper_i_alu_div0__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 97 \oper_i_alu_div0__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 88 \oper_i_alu_div0__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 89 \oper_i_alu_div0__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 95 \oper_i_alu_div0__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 87 \oper_i_alu_div0__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 86 \oper_i_alu_div0__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 94 \oper_i_alu_div0__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 91 \oper_i_alu_div0__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 70 \oper_i_alu_logical0__data_len + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 55 \oper_i_alu_logical0__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 56 \oper_i_alu_logical0__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 57 \oper_i_alu_logical0__imm_data__ok + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 64 \oper_i_alu_logical0__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 71 \oper_i_alu_logical0__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 54 \oper_i_alu_logical0__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 62 \oper_i_alu_logical0__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 65 \oper_i_alu_logical0__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 68 \oper_i_alu_logical0__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 69 \oper_i_alu_logical0__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 60 \oper_i_alu_logical0__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 61 \oper_i_alu_logical0__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 67 \oper_i_alu_logical0__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 59 \oper_i_alu_logical0__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 58 \oper_i_alu_logical0__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 66 \oper_i_alu_logical0__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 63 \oper_i_alu_logical0__zero_a + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 104 \oper_i_alu_mul0__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 105 \oper_i_alu_mul0__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 106 \oper_i_alu_mul0__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 114 \oper_i_alu_mul0__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 103 \oper_i_alu_mul0__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 112 \oper_i_alu_mul0__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 113 \oper_i_alu_mul0__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 109 \oper_i_alu_mul0__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 110 \oper_i_alu_mul0__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 108 \oper_i_alu_mul0__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 107 \oper_i_alu_mul0__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 111 \oper_i_alu_mul0__write_cr0 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 119 \oper_i_alu_shift_rot0__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 120 \oper_i_alu_shift_rot0__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 121 \oper_i_alu_shift_rot0__imm_data__ok + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 127 \oper_i_alu_shift_rot0__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 129 \oper_i_alu_shift_rot0__input_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 133 \oper_i_alu_shift_rot0__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 118 \oper_i_alu_shift_rot0__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 131 \oper_i_alu_shift_rot0__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 132 \oper_i_alu_shift_rot0__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 124 \oper_i_alu_shift_rot0__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 125 \oper_i_alu_shift_rot0__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 128 \oper_i_alu_shift_rot0__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 130 \oper_i_alu_shift_rot0__output_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 123 \oper_i_alu_shift_rot0__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 122 \oper_i_alu_shift_rot0__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 126 \oper_i_alu_shift_rot0__write_cr0 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 76 \oper_i_alu_spr0__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 77 \oper_i_alu_spr0__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 75 \oper_i_alu_spr0__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 78 \oper_i_alu_spr0__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 47 \oper_i_alu_trap0__cia + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 44 \oper_i_alu_trap0__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 45 \oper_i_alu_trap0__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 43 \oper_i_alu_trap0__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 48 \oper_i_alu_trap0__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 46 \oper_i_alu_trap0__msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 input 50 \oper_i_alu_trap0__trapaddr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 49 \oper_i_alu_trap0__traptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 149 \oper_i_ldst_ldst0__byte_reverse + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 148 \oper_i_ldst_ldst0__data_len + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 138 \oper_i_ldst_ldst0__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 139 \oper_i_ldst_ldst0__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 140 \oper_i_ldst_ldst0__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 152 \oper_i_ldst_ldst0__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 137 \oper_i_ldst_ldst0__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 146 \oper_i_ldst_ldst0__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 147 \oper_i_ldst_ldst0__is_signed + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 151 \oper_i_ldst_ldst0__ldst_mode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 144 \oper_i_ldst_ldst0__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 145 \oper_i_ldst_ldst0__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 143 \oper_i_ldst_ldst0__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 142 \oper_i_ldst_ldst0__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 150 \oper_i_ldst_ldst0__sign_extend + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 141 \oper_i_ldst_ldst0__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 306 \spr1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 158 \src1_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 161 \src1_i$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 164 \src1_i$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 167 \src1_i$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 170 \src1_i$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 173 \src1_i$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 176 \src1_i$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 179 \src1_i$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 182 \src1_i$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 210 \src1_i$74 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 183 \src2_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 184 \src2_i$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 185 \src2_i$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 186 \src2_i$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 187 \src2_i$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 188 \src2_i$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 189 \src2_i$57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 190 \src2_i$58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 213 \src2_i$77 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 215 \src2_i$79 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 191 \src3_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 192 \src3_i$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire input 193 \src3_i$60 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire input 194 \src3_i$61 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire input 196 \src3_i$62 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire input 197 \src3_i$63 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 32 input 203 \src3_i$67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 4 input 207 \src3_i$71 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 211 \src3_i$75 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 212 \src3_i$76 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire input 195 \src4_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire input 198 \src4_i$64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 2 input 199 \src4_i$65 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 4 input 204 \src4_i$68 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 214 \src4_i$78 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 2 input 201 \src5_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 2 input 202 \src5_i$66 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 4 input 208 \src5_i$72 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 2 input 200 \src6_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 4 input 209 \src6_i$73 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 266 \xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 267 \xer_ca_ok$120 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 268 \xer_ca_ok$121 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 272 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 273 \xer_ov_ok$124 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 274 \xer_ov_ok$125 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 275 \xer_ov_ok$126 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 280 \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 281 \xer_so_ok$129 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 282 \xer_so_ok$130 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 283 \xer_so_ok$131 + attribute \module_not_derived 1 + attribute \src "libresoc.v:122711.8-122753.4" + cell \alu0 \alu0 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cr_a_ok \cr_a_ok + connect \cu_busy_o \cu_busy_o + connect \cu_issue_i \cu_issue_i + connect \cu_rd__go_i \cu_rd__go_i + connect \cu_rd__rel_o \cu_rd__rel_o + connect \cu_rdmaskn_i \cu_rdmaskn_i + connect \cu_wr__go_i \cu_wr__go_i + connect \cu_wr__rel_o \cu_wr__rel_o + connect \dest1_o \dest1_o + connect \dest2_o \dest2_o$115 + connect \dest3_o \dest3_o$122 + connect \dest4_o \dest4_o + connect \dest5_o \dest5_o$132 + connect \o_ok \o_ok + connect \oper_i_alu_alu0__data_len \oper_i_alu_alu0__data_len + connect \oper_i_alu_alu0__fn_unit \oper_i_alu_alu0__fn_unit + connect \oper_i_alu_alu0__imm_data__data \oper_i_alu_alu0__imm_data__data + connect \oper_i_alu_alu0__imm_data__ok \oper_i_alu_alu0__imm_data__ok + connect \oper_i_alu_alu0__input_carry \oper_i_alu_alu0__input_carry + connect \oper_i_alu_alu0__insn \oper_i_alu_alu0__insn + connect \oper_i_alu_alu0__insn_type \oper_i_alu_alu0__insn_type + connect \oper_i_alu_alu0__invert_in \oper_i_alu_alu0__invert_in + connect \oper_i_alu_alu0__invert_out \oper_i_alu_alu0__invert_out + connect \oper_i_alu_alu0__is_32bit \oper_i_alu_alu0__is_32bit + connect \oper_i_alu_alu0__is_signed \oper_i_alu_alu0__is_signed + connect \oper_i_alu_alu0__oe__oe \oper_i_alu_alu0__oe__oe + connect \oper_i_alu_alu0__oe__ok \oper_i_alu_alu0__oe__ok + connect \oper_i_alu_alu0__output_carry \oper_i_alu_alu0__output_carry + connect \oper_i_alu_alu0__rc__ok \oper_i_alu_alu0__rc__ok + connect \oper_i_alu_alu0__rc__rc \oper_i_alu_alu0__rc__rc + connect \oper_i_alu_alu0__write_cr0 \oper_i_alu_alu0__write_cr0 + connect \oper_i_alu_alu0__zero_a \oper_i_alu_alu0__zero_a + connect \src1_i \src1_i + connect \src2_i \src2_i + connect \src3_i \src3_i$60 + connect \src4_i \src4_i$65 + connect \xer_ca_ok \xer_ca_ok + connect \xer_ov_ok \xer_ov_ok + connect \xer_so_ok \xer_so_ok + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:122754.11-122781.4" + cell \branch0 \branch0 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cu_busy_o \cu_busy_o$5 + connect \cu_issue_i \cu_issue_i$4 + connect \cu_rd__go_i \cu_rd__go_i$70 + connect \cu_rd__rel_o \cu_rd__rel_o$69 + connect \cu_rdmaskn_i \cu_rdmaskn_i$6 + connect \cu_wr__go_i \cu_wr__go_i$137 + connect \cu_wr__rel_o \cu_wr__rel_o$136 + connect \dest1_o \dest1_o$141 + connect \dest2_o \dest2_o$144 + connect \dest3_o \dest3_o$147 + connect \fast1_ok \fast1_ok + connect \fast2_ok \fast2_ok + connect \nia_ok \nia_ok + connect \oper_i_alu_branch0__cia \oper_i_alu_branch0__cia + connect \oper_i_alu_branch0__fn_unit \oper_i_alu_branch0__fn_unit + connect \oper_i_alu_branch0__imm_data__data \oper_i_alu_branch0__imm_data__data + connect \oper_i_alu_branch0__imm_data__ok \oper_i_alu_branch0__imm_data__ok + connect \oper_i_alu_branch0__insn \oper_i_alu_branch0__insn + connect \oper_i_alu_branch0__insn_type \oper_i_alu_branch0__insn_type + connect \oper_i_alu_branch0__is_32bit \oper_i_alu_branch0__is_32bit + connect \oper_i_alu_branch0__lk \oper_i_alu_branch0__lk + connect \src1_i \src1_i$74 + connect \src2_i \src2_i$77 + connect \src3_i \src3_i$71 + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:122782.7-122807.4" + cell \cr0 \cr0 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cr_a_ok \cr_a_ok$110 + connect \cu_busy_o \cu_busy_o$2 + connect \cu_issue_i \cu_issue_i$1 + connect \cu_rd__go_i \cu_rd__go_i$29 + connect \cu_rd__rel_o \cu_rd__rel_o$28 + connect \cu_rdmaskn_i \cu_rdmaskn_i$3 + connect \cu_wr__go_i \cu_wr__go_i$82 + connect \cu_wr__rel_o \cu_wr__rel_o$81 + connect \dest1_o \dest1_o$103 + connect \dest2_o \dest2_o + connect \dest3_o \dest3_o + connect \full_cr_ok \full_cr_ok + connect \o_ok \o_ok$80 + connect \oper_i_alu_cr0__fn_unit \oper_i_alu_cr0__fn_unit + connect \oper_i_alu_cr0__insn \oper_i_alu_cr0__insn + connect \oper_i_alu_cr0__insn_type \oper_i_alu_cr0__insn_type + connect \src1_i \src1_i$30 + connect \src2_i \src2_i$52 + connect \src3_i \src3_i$67 + connect \src4_i \src4_i$68 + connect \src5_i \src5_i$72 + connect \src6_i \src6_i$73 + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:122808.8-122847.4" + cell \div0 \div0 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cr_a_ok \cr_a_ok$112 + connect \cu_busy_o \cu_busy_o$17 + connect \cu_issue_i \cu_issue_i$16 + connect \cu_rd__go_i \cu_rd__go_i$41 + connect \cu_rd__rel_o \cu_rd__rel_o$40 + connect \cu_rdmaskn_i \cu_rdmaskn_i$18 + connect \cu_wr__go_i \cu_wr__go_i$94 + connect \cu_wr__rel_o \cu_wr__rel_o$93 + connect \dest1_o \dest1_o$107 + connect \dest2_o \dest2_o$117 + connect \dest3_o \dest3_o$127 + connect \dest4_o \dest4_o$134 + connect \o_ok \o_ok$92 + connect \oper_i_alu_div0__data_len \oper_i_alu_div0__data_len + connect \oper_i_alu_div0__fn_unit \oper_i_alu_div0__fn_unit + connect \oper_i_alu_div0__imm_data__data \oper_i_alu_div0__imm_data__data + connect \oper_i_alu_div0__imm_data__ok \oper_i_alu_div0__imm_data__ok + connect \oper_i_alu_div0__input_carry \oper_i_alu_div0__input_carry + connect \oper_i_alu_div0__insn \oper_i_alu_div0__insn + connect \oper_i_alu_div0__insn_type \oper_i_alu_div0__insn_type + connect \oper_i_alu_div0__invert_in \oper_i_alu_div0__invert_in + connect \oper_i_alu_div0__invert_out \oper_i_alu_div0__invert_out + connect \oper_i_alu_div0__is_32bit \oper_i_alu_div0__is_32bit + connect \oper_i_alu_div0__is_signed \oper_i_alu_div0__is_signed + connect \oper_i_alu_div0__oe__oe \oper_i_alu_div0__oe__oe + connect \oper_i_alu_div0__oe__ok \oper_i_alu_div0__oe__ok + connect \oper_i_alu_div0__output_carry \oper_i_alu_div0__output_carry + connect \oper_i_alu_div0__rc__ok \oper_i_alu_div0__rc__ok + connect \oper_i_alu_div0__rc__rc \oper_i_alu_div0__rc__rc + connect \oper_i_alu_div0__write_cr0 \oper_i_alu_div0__write_cr0 + connect \oper_i_alu_div0__zero_a \oper_i_alu_div0__zero_a + connect \src1_i \src1_i$42 + connect \src2_i \src2_i$55 + connect \src3_i \src3_i$62 + connect \xer_ov_ok \xer_ov_ok$125 + connect \xer_so_ok \xer_so_ok$130 + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:122848.9-122895.4" + cell \ldst0 \ldst0 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cu_ad__go_i \cu_ad__go_i + connect \cu_ad__rel_o \cu_ad__rel_o + connect \cu_busy_o \cu_busy_o$26 + connect \cu_issue_i \cu_issue_i$25 + connect \cu_rd__go_i \cu_rd__go_i$50 + connect \cu_rd__rel_o \cu_rd__rel_o$49 + connect \cu_rdmaskn_i \cu_rdmaskn_i$27 + connect \cu_st__go_i \cu_st__go_i + connect \cu_st__rel_o \cu_st__rel_o + connect \cu_wr__go_i \cu_wr__go_i$102 + connect \cu_wr__rel_o \cu_wr__rel_o$101 + connect \ea \ea + connect \ldst_port0_addr_exc_o \ldst_port0_addr_exc_o + connect \ldst_port0_addr_i \ldst_port0_addr_i + connect \ldst_port0_addr_i_ok \ldst_port0_addr_i_ok + connect \ldst_port0_addr_ok_o \ldst_port0_addr_ok_o + connect \ldst_port0_busy_o \ldst_port0_busy_o + connect \ldst_port0_data_len \ldst_port0_data_len + connect \ldst_port0_is_ld_i \ldst_port0_is_ld_i + connect \ldst_port0_is_st_i \ldst_port0_is_st_i + connect \ldst_port0_ld_data_o \ldst_port0_ld_data_o + connect \ldst_port0_ld_data_o_ok \ldst_port0_ld_data_o_ok + connect \ldst_port0_st_data_i \ldst_port0_st_data_i + connect \ldst_port0_st_data_i_ok \ldst_port0_st_data_i_ok + connect \o \o + connect \oper_i_ldst_ldst0__byte_reverse \oper_i_ldst_ldst0__byte_reverse + connect \oper_i_ldst_ldst0__data_len \oper_i_ldst_ldst0__data_len + connect \oper_i_ldst_ldst0__fn_unit \oper_i_ldst_ldst0__fn_unit + connect \oper_i_ldst_ldst0__imm_data__data \oper_i_ldst_ldst0__imm_data__data + connect \oper_i_ldst_ldst0__imm_data__ok \oper_i_ldst_ldst0__imm_data__ok + connect \oper_i_ldst_ldst0__insn \oper_i_ldst_ldst0__insn + connect \oper_i_ldst_ldst0__insn_type \oper_i_ldst_ldst0__insn_type + connect \oper_i_ldst_ldst0__is_32bit \oper_i_ldst_ldst0__is_32bit + connect \oper_i_ldst_ldst0__is_signed \oper_i_ldst_ldst0__is_signed + connect \oper_i_ldst_ldst0__ldst_mode \oper_i_ldst_ldst0__ldst_mode + connect \oper_i_ldst_ldst0__oe__oe \oper_i_ldst_ldst0__oe__oe + connect \oper_i_ldst_ldst0__oe__ok \oper_i_ldst_ldst0__oe__ok + connect \oper_i_ldst_ldst0__rc__ok \oper_i_ldst_ldst0__rc__ok + connect \oper_i_ldst_ldst0__rc__rc \oper_i_ldst_ldst0__rc__rc + connect \oper_i_ldst_ldst0__sign_extend \oper_i_ldst_ldst0__sign_extend + connect \oper_i_ldst_ldst0__zero_a \oper_i_ldst_ldst0__zero_a + connect \src1_i \src1_i$51 + connect \src2_i \src2_i$58 + connect \src3_i \src3_i$59 + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:122896.12-122931.4" + cell \logical0 \logical0 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cr_a_ok \cr_a_ok$111 + connect \cu_busy_o \cu_busy_o$11 + connect \cu_issue_i \cu_issue_i$10 + connect \cu_rd__go_i \cu_rd__go_i$35 + connect \cu_rd__rel_o \cu_rd__rel_o$34 + connect \cu_rdmaskn_i \cu_rdmaskn_i$12 + connect \cu_wr__go_i \cu_wr__go_i$88 + connect \cu_wr__rel_o \cu_wr__rel_o$87 + connect \dest1_o \dest1_o$105 + connect \dest2_o \dest2_o$116 + connect \o_ok \o_ok$86 + connect \oper_i_alu_logical0__data_len \oper_i_alu_logical0__data_len + connect \oper_i_alu_logical0__fn_unit \oper_i_alu_logical0__fn_unit + connect \oper_i_alu_logical0__imm_data__data \oper_i_alu_logical0__imm_data__data + connect \oper_i_alu_logical0__imm_data__ok \oper_i_alu_logical0__imm_data__ok + connect \oper_i_alu_logical0__input_carry \oper_i_alu_logical0__input_carry + connect \oper_i_alu_logical0__insn \oper_i_alu_logical0__insn + connect \oper_i_alu_logical0__insn_type \oper_i_alu_logical0__insn_type + connect \oper_i_alu_logical0__invert_in \oper_i_alu_logical0__invert_in + connect \oper_i_alu_logical0__invert_out \oper_i_alu_logical0__invert_out + connect \oper_i_alu_logical0__is_32bit \oper_i_alu_logical0__is_32bit + connect \oper_i_alu_logical0__is_signed \oper_i_alu_logical0__is_signed + connect \oper_i_alu_logical0__oe__oe \oper_i_alu_logical0__oe__oe + connect \oper_i_alu_logical0__oe__ok \oper_i_alu_logical0__oe__ok + connect \oper_i_alu_logical0__output_carry \oper_i_alu_logical0__output_carry + connect \oper_i_alu_logical0__rc__ok \oper_i_alu_logical0__rc__ok + connect \oper_i_alu_logical0__rc__rc \oper_i_alu_logical0__rc__rc + connect \oper_i_alu_logical0__write_cr0 \oper_i_alu_logical0__write_cr0 + connect \oper_i_alu_logical0__zero_a \oper_i_alu_logical0__zero_a + connect \src1_i \src1_i$36 + connect \src2_i \src2_i$54 + connect \src3_i \src3_i$61 + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:122932.8-122965.4" + cell \mul0 \mul0 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cr_a_ok \cr_a_ok$113 + connect \cu_busy_o \cu_busy_o$20 + connect \cu_issue_i \cu_issue_i$19 + connect \cu_rd__go_i \cu_rd__go_i$44 + connect \cu_rd__rel_o \cu_rd__rel_o$43 + connect \cu_rdmaskn_i \cu_rdmaskn_i$21 + connect \cu_wr__go_i \cu_wr__go_i$97 + connect \cu_wr__rel_o \cu_wr__rel_o$96 + connect \dest1_o \dest1_o$108 + connect \dest2_o \dest2_o$118 + connect \dest3_o \dest3_o$128 + connect \dest4_o \dest4_o$135 + connect \o_ok \o_ok$95 + connect \oper_i_alu_mul0__fn_unit \oper_i_alu_mul0__fn_unit + connect \oper_i_alu_mul0__imm_data__data \oper_i_alu_mul0__imm_data__data + connect \oper_i_alu_mul0__imm_data__ok \oper_i_alu_mul0__imm_data__ok + connect \oper_i_alu_mul0__insn \oper_i_alu_mul0__insn + connect \oper_i_alu_mul0__insn_type \oper_i_alu_mul0__insn_type + connect \oper_i_alu_mul0__is_32bit \oper_i_alu_mul0__is_32bit + connect \oper_i_alu_mul0__is_signed \oper_i_alu_mul0__is_signed + connect \oper_i_alu_mul0__oe__oe \oper_i_alu_mul0__oe__oe + connect \oper_i_alu_mul0__oe__ok \oper_i_alu_mul0__oe__ok + connect \oper_i_alu_mul0__rc__ok \oper_i_alu_mul0__rc__ok + connect \oper_i_alu_mul0__rc__rc \oper_i_alu_mul0__rc__rc + connect \oper_i_alu_mul0__write_cr0 \oper_i_alu_mul0__write_cr0 + connect \src1_i \src1_i$45 + connect \src2_i \src2_i$56 + connect \src3_i \src3_i$63 + connect \xer_ov_ok \xer_ov_ok$126 + connect \xer_so_ok \xer_so_ok$131 + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:122966.13-123003.4" + cell \shiftrot0 \shiftrot0 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cr_a_ok \cr_a_ok$114 + connect \cu_busy_o \cu_busy_o$23 + connect \cu_issue_i \cu_issue_i$22 + connect \cu_rd__go_i \cu_rd__go_i$47 + connect \cu_rd__rel_o \cu_rd__rel_o$46 + connect \cu_rdmaskn_i \cu_rdmaskn_i$24 + connect \cu_wr__go_i \cu_wr__go_i$100 + connect \cu_wr__rel_o \cu_wr__rel_o$99 + connect \dest1_o \dest1_o$109 + connect \dest2_o \dest2_o$119 + connect \dest3_o \dest3_o$123 + connect \o_ok \o_ok$98 + connect \oper_i_alu_shift_rot0__fn_unit \oper_i_alu_shift_rot0__fn_unit + connect \oper_i_alu_shift_rot0__imm_data__data \oper_i_alu_shift_rot0__imm_data__data + connect \oper_i_alu_shift_rot0__imm_data__ok \oper_i_alu_shift_rot0__imm_data__ok + connect \oper_i_alu_shift_rot0__input_carry \oper_i_alu_shift_rot0__input_carry + connect \oper_i_alu_shift_rot0__input_cr \oper_i_alu_shift_rot0__input_cr + connect \oper_i_alu_shift_rot0__insn \oper_i_alu_shift_rot0__insn + connect \oper_i_alu_shift_rot0__insn_type \oper_i_alu_shift_rot0__insn_type + connect \oper_i_alu_shift_rot0__is_32bit \oper_i_alu_shift_rot0__is_32bit + connect \oper_i_alu_shift_rot0__is_signed \oper_i_alu_shift_rot0__is_signed + connect \oper_i_alu_shift_rot0__oe__oe \oper_i_alu_shift_rot0__oe__oe + connect \oper_i_alu_shift_rot0__oe__ok \oper_i_alu_shift_rot0__oe__ok + connect \oper_i_alu_shift_rot0__output_carry \oper_i_alu_shift_rot0__output_carry + connect \oper_i_alu_shift_rot0__output_cr \oper_i_alu_shift_rot0__output_cr + connect \oper_i_alu_shift_rot0__rc__ok \oper_i_alu_shift_rot0__rc__ok + connect \oper_i_alu_shift_rot0__rc__rc \oper_i_alu_shift_rot0__rc__rc + connect \oper_i_alu_shift_rot0__write_cr0 \oper_i_alu_shift_rot0__write_cr0 + connect \src1_i \src1_i$48 + connect \src2_i \src2_i$57 + connect \src3_i \src3_i + connect \src4_i \src4_i$64 + connect \src5_i \src5_i + connect \xer_ca_ok \xer_ca_ok$121 + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:123004.8-123036.4" + cell \spr0 \spr0 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cu_busy_o \cu_busy_o$14 + connect \cu_issue_i \cu_issue_i$13 + connect \cu_rd__go_i \cu_rd__go_i$38 + connect \cu_rd__rel_o \cu_rd__rel_o$37 + connect \cu_rdmaskn_i \cu_rdmaskn_i$15 + connect \cu_wr__go_i \cu_wr__go_i$91 + connect \cu_wr__rel_o \cu_wr__rel_o$90 + connect \dest1_o \dest1_o$106 + connect \dest2_o \dest2_o$150 + connect \dest3_o \dest3_o$143 + connect \dest4_o \dest4_o$133 + connect \dest5_o \dest5_o + connect \dest6_o \dest6_o + connect \fast1_ok \fast1_ok$139 + connect \o_ok \o_ok$89 + connect \oper_i_alu_spr0__fn_unit \oper_i_alu_spr0__fn_unit + connect \oper_i_alu_spr0__insn \oper_i_alu_spr0__insn + connect \oper_i_alu_spr0__insn_type \oper_i_alu_spr0__insn_type + connect \oper_i_alu_spr0__is_32bit \oper_i_alu_spr0__is_32bit + connect \spr1_ok \spr1_ok + connect \src1_i \src1_i$39 + connect \src2_i \src2_i$79 + connect \src3_i \src3_i$76 + connect \src4_i \src4_i + connect \src5_i \src5_i$66 + connect \src6_i \src6_i + connect \xer_ca_ok \xer_ca_ok$120 + connect \xer_ov_ok \xer_ov_ok$124 + connect \xer_so_ok \xer_so_ok$129 + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:123037.9-123069.4" + cell \trap0 \trap0 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cu_busy_o \cu_busy_o$8 + connect \cu_issue_i \cu_issue_i$7 + connect \cu_rd__go_i \cu_rd__go_i$32 + connect \cu_rd__rel_o \cu_rd__rel_o$31 + connect \cu_rdmaskn_i \cu_rdmaskn_i$9 + connect \cu_wr__go_i \cu_wr__go_i$85 + connect \cu_wr__rel_o \cu_wr__rel_o$84 + connect \dest1_o \dest1_o$104 + connect \dest2_o \dest2_o$142 + connect \dest3_o \dest3_o$145 + connect \dest4_o \dest4_o$148 + connect \dest5_o \dest5_o$149 + connect \fast1_ok \fast1_ok$138 + connect \fast2_ok \fast2_ok$140 + connect \msr_ok \msr_ok + connect \nia_ok \nia_ok$146 + connect \o_ok \o_ok$83 + connect \oper_i_alu_trap0__cia \oper_i_alu_trap0__cia + connect \oper_i_alu_trap0__fn_unit \oper_i_alu_trap0__fn_unit + connect \oper_i_alu_trap0__insn \oper_i_alu_trap0__insn + connect \oper_i_alu_trap0__insn_type \oper_i_alu_trap0__insn_type + connect \oper_i_alu_trap0__is_32bit \oper_i_alu_trap0__is_32bit + connect \oper_i_alu_trap0__msr \oper_i_alu_trap0__msr + connect \oper_i_alu_trap0__trapaddr \oper_i_alu_trap0__trapaddr + connect \oper_i_alu_trap0__traptype \oper_i_alu_trap0__traptype + connect \src1_i \src1_i$33 + connect \src2_i \src2_i$53 + connect \src3_i \src3_i$75 + connect \src4_i \src4_i$78 + end +end +attribute \src "libresoc.v:123074.1-123132.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.l0.l0.idx_l" +attribute \generator "nMigen" +module \idx_l + attribute \src "libresoc.v:123075.7-123075.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:123120.3-123128.6" + wire $0\q_int$next[0:0]$5063 + attribute \src "libresoc.v:123118.3-123119.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:123120.3-123128.6" + wire $1\q_int$next[0:0]$5064 + attribute \src "libresoc.v:123099.7-123099.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:123110.17-123110.96" + wire $and$libresoc.v:123110$5053_Y + attribute \src "libresoc.v:123115.17-123115.96" + wire $and$libresoc.v:123115$5058_Y + attribute \src "libresoc.v:123112.18-123112.95" + wire $not$libresoc.v:123112$5055_Y + attribute \src "libresoc.v:123114.17-123114.94" + wire $not$libresoc.v:123114$5057_Y + attribute \src "libresoc.v:123117.17-123117.94" + wire $not$libresoc.v:123117$5060_Y + attribute \src "libresoc.v:123111.18-123111.100" + wire $or$libresoc.v:123111$5054_Y + attribute \src "libresoc.v:123113.18-123113.101" + wire $or$libresoc.v:123113$5056_Y + attribute \src "libresoc.v:123116.17-123116.99" + wire $or$libresoc.v:123116$5059_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 1 \coresync_rst + attribute \src "libresoc.v:123075.7-123075.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 2 \q_idx_l + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_idx_l + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_idx_l + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 4 \r_idx_l + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 3 \s_idx_l + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$libresoc.v:123110$5053 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:123110$5053_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:123115$5058 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:123115$5058_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:123112$5055 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_idx_l + connect \Y $not$libresoc.v:123112$5055_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:123114$5057 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_idx_l + connect \Y $not$libresoc.v:123114$5057_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:123117$5060 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_idx_l + connect \Y $not$libresoc.v:123117$5060_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:123111$5054 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_idx_l + connect \Y $or$libresoc.v:123111$5054_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:123113$5056 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_idx_l + connect \B \q_int + connect \Y $or$libresoc.v:123113$5056_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:123116$5059 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_idx_l + connect \Y $or$libresoc.v:123116$5059_Y + end + attribute \src "libresoc.v:123075.7-123075.20" + process $proc$libresoc.v:123075$5065 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:123099.7-123099.19" + process $proc$libresoc.v:123099$5066 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:123118.3-123119.27" + process $proc$libresoc.v:123118$5061 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:123120.3-123128.6" + process $proc$libresoc.v:123120$5062 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$5063 $1\q_int$next[0:0]$5064 + attribute \src "libresoc.v:123121.5-123121.29" + switch \initial + attribute \src "libresoc.v:123121.9-123121.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$5064 1'0 + case + assign $1\q_int$next[0:0]$5064 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$5063 + end + connect \$9 $and$libresoc.v:123110$5053_Y + connect \$11 $or$libresoc.v:123111$5054_Y + connect \$13 $not$libresoc.v:123112$5055_Y + connect \$15 $or$libresoc.v:123113$5056_Y + connect \$1 $not$libresoc.v:123114$5057_Y + connect \$3 $and$libresoc.v:123115$5058_Y + connect \$5 $or$libresoc.v:123116$5059_Y + connect \$7 $not$libresoc.v:123117$5060_Y + connect \qlq_idx_l \$15 + connect \qn_idx_l \$13 + connect \q_idx_l \$11 +end +attribute \src "libresoc.v:123136.1-123458.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.imem" +attribute \generator "nMigen" +module \imem + attribute \src "libresoc.v:123415.3-123429.6" + wire width 45 $0\f_badaddr_o$next[44:0]$5129 + attribute \src "libresoc.v:123276.3-123277.39" + wire width 45 $0\f_badaddr_o[44:0] + attribute \src "libresoc.v:123430.3-123441.6" + wire $0\f_busy_o[0:0] + attribute \src "libresoc.v:123397.3-123414.6" + wire $0\f_fetch_err_o$next[0:0]$5125 + attribute \src "libresoc.v:123278.3-123279.43" + wire $0\f_fetch_err_o[0:0] + attribute \src "libresoc.v:123442.3-123454.6" + wire width 64 $0\f_instr_o[63:0] + attribute \src "libresoc.v:123379.3-123396.6" + wire width 45 $0\ibus__adr$next[44:0]$5121 + attribute \src "libresoc.v:123280.3-123281.35" + wire width 45 $0\ibus__adr[44:0] + attribute \src "libresoc.v:123290.3-123312.6" + wire $0\ibus__cyc$next[0:0]$5101 + attribute \src "libresoc.v:123288.3-123289.35" + wire $0\ibus__cyc[0:0] + attribute \src "libresoc.v:123336.3-123358.6" + wire width 8 $0\ibus__sel$next[7:0]$5111 + attribute \src "libresoc.v:123284.3-123285.35" + wire width 8 $0\ibus__sel[7:0] + attribute \src "libresoc.v:123313.3-123335.6" + wire $0\ibus__stb$next[0:0]$5106 + attribute \src "libresoc.v:123286.3-123287.35" + wire $0\ibus__stb[0:0] + attribute \src "libresoc.v:123359.3-123378.6" + wire width 64 $0\ibus_rdata$next[63:0]$5116 + attribute \src "libresoc.v:123282.3-123283.37" + wire width 64 $0\ibus_rdata[63:0] + attribute \src "libresoc.v:123137.7-123137.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:123415.3-123429.6" + wire width 45 $1\f_badaddr_o$next[44:0]$5130 + attribute \src "libresoc.v:123201.14-123201.44" + wire width 45 $1\f_badaddr_o[44:0] + attribute \src "libresoc.v:123430.3-123441.6" + wire $1\f_busy_o[0:0] + attribute \src "libresoc.v:123397.3-123414.6" + wire $1\f_fetch_err_o$next[0:0]$5126 + attribute \src "libresoc.v:123208.7-123208.27" + wire $1\f_fetch_err_o[0:0] + attribute \src "libresoc.v:123442.3-123454.6" + wire width 64 $1\f_instr_o[63:0] + attribute \src "libresoc.v:123379.3-123396.6" + wire width 45 $1\ibus__adr$next[44:0]$5122 + attribute \src "libresoc.v:123222.14-123222.42" + wire width 45 $1\ibus__adr[44:0] + attribute \src "libresoc.v:123290.3-123312.6" + wire $1\ibus__cyc$next[0:0]$5102 + attribute \src "libresoc.v:123227.7-123227.23" + wire $1\ibus__cyc[0:0] + attribute \src "libresoc.v:123336.3-123358.6" + wire width 8 $1\ibus__sel$next[7:0]$5112 + attribute \src "libresoc.v:123236.13-123236.30" + wire width 8 $1\ibus__sel[7:0] + attribute \src "libresoc.v:123313.3-123335.6" + wire $1\ibus__stb$next[0:0]$5107 + attribute \src "libresoc.v:123241.7-123241.23" + wire $1\ibus__stb[0:0] + attribute \src "libresoc.v:123359.3-123378.6" + wire width 64 $1\ibus_rdata$next[63:0]$5117 + attribute \src "libresoc.v:123245.14-123245.47" + wire width 64 $1\ibus_rdata[63:0] + attribute \src "libresoc.v:123415.3-123429.6" + wire width 45 $2\f_badaddr_o$next[44:0]$5131 + attribute \src "libresoc.v:123397.3-123414.6" + wire $2\f_fetch_err_o$next[0:0]$5127 + attribute \src "libresoc.v:123379.3-123396.6" + wire width 45 $2\ibus__adr$next[44:0]$5123 + attribute \src "libresoc.v:123290.3-123312.6" + wire $2\ibus__cyc$next[0:0]$5103 + attribute \src "libresoc.v:123336.3-123358.6" + wire width 8 $2\ibus__sel$next[7:0]$5113 + attribute \src "libresoc.v:123313.3-123335.6" + wire $2\ibus__stb$next[0:0]$5108 + attribute \src "libresoc.v:123359.3-123378.6" + wire width 64 $2\ibus_rdata$next[63:0]$5118 + attribute \src "libresoc.v:123290.3-123312.6" + wire $3\ibus__cyc$next[0:0]$5104 + attribute \src "libresoc.v:123336.3-123358.6" + wire width 8 $3\ibus__sel$next[7:0]$5114 + attribute \src "libresoc.v:123313.3-123335.6" + wire $3\ibus__stb$next[0:0]$5109 + attribute \src "libresoc.v:123359.3-123378.6" + wire width 64 $3\ibus_rdata$next[63:0]$5119 + attribute \src "libresoc.v:123252.18-123252.110" + wire $and$libresoc.v:123252$5069_Y + attribute \src "libresoc.v:123258.18-123258.110" + wire $and$libresoc.v:123258$5075_Y + attribute \src "libresoc.v:123263.18-123263.110" + wire $and$libresoc.v:123263$5080_Y + attribute \src "libresoc.v:123266.17-123266.108" + wire $and$libresoc.v:123266$5083_Y + attribute \src "libresoc.v:123269.18-123269.110" + wire $and$libresoc.v:123269$5086_Y + attribute \src "libresoc.v:123270.18-123270.115" + wire $and$libresoc.v:123270$5087_Y + attribute \src "libresoc.v:123272.18-123272.115" + wire $and$libresoc.v:123272$5089_Y + attribute \src "libresoc.v:123251.18-123251.105" + wire $not$libresoc.v:123251$5068_Y + attribute \src "libresoc.v:123254.18-123254.105" + wire $not$libresoc.v:123254$5071_Y + attribute \src "libresoc.v:123255.17-123255.104" + wire $not$libresoc.v:123255$5072_Y + attribute \src "libresoc.v:123257.18-123257.105" + wire $not$libresoc.v:123257$5074_Y + attribute \src "libresoc.v:123260.18-123260.105" + wire $not$libresoc.v:123260$5077_Y + attribute \src "libresoc.v:123262.18-123262.105" + wire $not$libresoc.v:123262$5079_Y + attribute \src "libresoc.v:123265.18-123265.105" + wire $not$libresoc.v:123265$5082_Y + attribute \src "libresoc.v:123268.18-123268.105" + wire $not$libresoc.v:123268$5085_Y + attribute \src "libresoc.v:123271.18-123271.105" + wire $not$libresoc.v:123271$5088_Y + attribute \src "libresoc.v:123273.18-123273.105" + wire $not$libresoc.v:123273$5090_Y + attribute \src "libresoc.v:123275.17-123275.104" + wire $not$libresoc.v:123275$5092_Y + attribute \src "libresoc.v:123250.17-123250.103" + wire $or$libresoc.v:123250$5067_Y + attribute \src "libresoc.v:123253.18-123253.115" + wire $or$libresoc.v:123253$5070_Y + attribute \src "libresoc.v:123256.18-123256.106" + wire $or$libresoc.v:123256$5073_Y + attribute \src "libresoc.v:123259.18-123259.115" + wire $or$libresoc.v:123259$5076_Y + attribute \src "libresoc.v:123261.18-123261.106" + wire $or$libresoc.v:123261$5078_Y + attribute \src "libresoc.v:123264.18-123264.115" + wire $or$libresoc.v:123264$5081_Y + attribute \src "libresoc.v:123267.18-123267.106" + wire $or$libresoc.v:123267$5084_Y + attribute \src "libresoc.v:123274.17-123274.114" + wire $or$libresoc.v:123274$5091_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + wire \$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" + wire \$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + wire \$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + wire \$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" + wire \$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + wire \$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + wire \$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + wire \$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" + wire \$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" + wire \$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:76" + wire \$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:81" + wire \$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:76" + wire \$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:81" + wire \$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:31" + wire \a_busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:24" + wire width 48 input 1 \a_pc_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:25" + wire \a_stall_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:26" + wire input 2 \a_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:151" + wire input 14 \clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:35" + wire width 45 \f_badaddr_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:35" + wire width 45 \f_badaddr_o$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:32" + wire output 4 \f_busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:34" + wire \f_fetch_err_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:34" + wire \f_fetch_err_o$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:33" + wire width 64 output 5 \f_instr_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:27" + wire \f_stall_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:28" + wire input 3 \f_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire input 8 \ibus__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire width 45 output 13 \ibus__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire width 45 \ibus__adr$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire output 7 \ibus__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire \ibus__cyc$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire width 64 input 12 \ibus__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire input 9 \ibus__err + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire width 8 output 11 \ibus__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire width 8 \ibus__sel$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire output 10 \ibus__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire \ibus__stb$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:59" + wire width 64 \ibus_rdata + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:59" + wire width 64 \ibus_rdata$next + attribute \src "libresoc.v:123137.7-123137.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:151" + wire input 6 \rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" + cell $and $and$libresoc.v:123252$5069 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \a_valid_i + connect \B \$11 + connect \Y $and$libresoc.v:123252$5069_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" + cell $and $and$libresoc.v:123258$5075 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \a_valid_i + connect \B \$21 + connect \Y $and$libresoc.v:123258$5075_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" + cell $and $and$libresoc.v:123263$5080 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \a_valid_i + connect \B \$31 + connect \Y $and$libresoc.v:123263$5080_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" + cell $and $and$libresoc.v:123266$5083 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \a_valid_i + connect \B \$1 + connect \Y $and$libresoc.v:123266$5083_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" + cell $and $and$libresoc.v:123269$5086 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \a_valid_i + connect \B \$41 + connect \Y $and$libresoc.v:123269$5086_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:76" + cell $and $and$libresoc.v:123270$5087 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ibus__cyc + connect \B \ibus__err + connect \Y $and$libresoc.v:123270$5087_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:76" + cell $and $and$libresoc.v:123272$5089 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ibus__cyc + connect \B \ibus__err + connect \Y $and$libresoc.v:123272$5089_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" + cell $not $not$libresoc.v:123251$5068 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \a_stall_i + connect \Y $not$libresoc.v:123251$5068_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + cell $not $not$libresoc.v:123254$5071 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \f_valid_i + connect \Y $not$libresoc.v:123254$5071_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" + cell $not $not$libresoc.v:123255$5072 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \a_stall_i + connect \Y $not$libresoc.v:123255$5072_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" + cell $not $not$libresoc.v:123257$5074 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \a_stall_i + connect \Y $not$libresoc.v:123257$5074_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + cell $not $not$libresoc.v:123260$5077 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \f_valid_i + connect \Y $not$libresoc.v:123260$5077_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" + cell $not $not$libresoc.v:123262$5079 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \a_stall_i + connect \Y $not$libresoc.v:123262$5079_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + cell $not $not$libresoc.v:123265$5082 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \f_valid_i + connect \Y $not$libresoc.v:123265$5082_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" + cell $not $not$libresoc.v:123268$5085 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \a_stall_i + connect \Y $not$libresoc.v:123268$5085_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:81" + cell $not $not$libresoc.v:123271$5088 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \f_stall_i + connect \Y $not$libresoc.v:123271$5088_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:81" + cell $not $not$libresoc.v:123273$5090 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \f_stall_i + connect \Y $not$libresoc.v:123273$5090_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + cell $not $not$libresoc.v:123275$5092 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \f_valid_i + connect \Y $not$libresoc.v:123275$5092_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + cell $or $or$libresoc.v:123250$5067 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$5 + connect \B \$7 + connect \Y $or$libresoc.v:123250$5067_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + cell $or $or$libresoc.v:123253$5070 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ibus__ack + connect \B \ibus__err + connect \Y $or$libresoc.v:123253$5070_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + cell $or $or$libresoc.v:123256$5073 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$15 + connect \B \$17 + connect \Y $or$libresoc.v:123256$5073_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + cell $or $or$libresoc.v:123259$5076 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ibus__ack + connect \B \ibus__err + connect \Y $or$libresoc.v:123259$5076_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + cell $or $or$libresoc.v:123261$5078 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$25 + connect \B \$27 + connect \Y $or$libresoc.v:123261$5078_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + cell $or $or$libresoc.v:123264$5081 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ibus__ack + connect \B \ibus__err + connect \Y $or$libresoc.v:123264$5081_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + cell $or $or$libresoc.v:123267$5084 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$35 + connect \B \$37 + connect \Y $or$libresoc.v:123267$5084_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + cell $or $or$libresoc.v:123274$5091 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ibus__ack + connect \B \ibus__err + connect \Y $or$libresoc.v:123274$5091_Y + end + attribute \src "libresoc.v:123137.7-123137.20" + process $proc$libresoc.v:123137$5134 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:123201.14-123201.44" + process $proc$libresoc.v:123201$5135 + assign { } { } + assign $1\f_badaddr_o[44:0] 45'000000000000000000000000000000000000000000000 + sync always + sync init + update \f_badaddr_o $1\f_badaddr_o[44:0] + end + attribute \src "libresoc.v:123208.7-123208.27" + process $proc$libresoc.v:123208$5136 + assign { } { } + assign $1\f_fetch_err_o[0:0] 1'0 + sync always + sync init + update \f_fetch_err_o $1\f_fetch_err_o[0:0] + end + attribute \src "libresoc.v:123222.14-123222.42" + process $proc$libresoc.v:123222$5137 + assign { } { } + assign $1\ibus__adr[44:0] 45'000000000000000000000000000000000000000000000 + sync always + sync init + update \ibus__adr $1\ibus__adr[44:0] + end + attribute \src "libresoc.v:123227.7-123227.23" + process $proc$libresoc.v:123227$5138 + assign { } { } + assign $1\ibus__cyc[0:0] 1'0 + sync always + sync init + update \ibus__cyc $1\ibus__cyc[0:0] + end + attribute \src "libresoc.v:123236.13-123236.30" + process $proc$libresoc.v:123236$5139 + assign { } { } + assign $1\ibus__sel[7:0] 8'00000000 + sync always + sync init + update \ibus__sel $1\ibus__sel[7:0] + end + attribute \src "libresoc.v:123241.7-123241.23" + process $proc$libresoc.v:123241$5140 + assign { } { } + assign $1\ibus__stb[0:0] 1'0 + sync always + sync init + update \ibus__stb $1\ibus__stb[0:0] + end + attribute \src "libresoc.v:123245.14-123245.47" + process $proc$libresoc.v:123245$5141 + assign { } { } + assign $1\ibus_rdata[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \ibus_rdata $1\ibus_rdata[63:0] + end + attribute \src "libresoc.v:123276.3-123277.39" + process $proc$libresoc.v:123276$5093 + assign { } { } + assign $0\f_badaddr_o[44:0] \f_badaddr_o$next + sync posedge \clk + update \f_badaddr_o $0\f_badaddr_o[44:0] + end + attribute \src "libresoc.v:123278.3-123279.43" + process $proc$libresoc.v:123278$5094 + assign { } { } + assign $0\f_fetch_err_o[0:0] \f_fetch_err_o$next + sync posedge \clk + update \f_fetch_err_o $0\f_fetch_err_o[0:0] + end + attribute \src "libresoc.v:123280.3-123281.35" + process $proc$libresoc.v:123280$5095 + assign { } { } + assign $0\ibus__adr[44:0] \ibus__adr$next + sync posedge \clk + update \ibus__adr $0\ibus__adr[44:0] + end + attribute \src "libresoc.v:123282.3-123283.37" + process $proc$libresoc.v:123282$5096 + assign { } { } + assign $0\ibus_rdata[63:0] \ibus_rdata$next + sync posedge \clk + update \ibus_rdata $0\ibus_rdata[63:0] + end + attribute \src "libresoc.v:123284.3-123285.35" + process $proc$libresoc.v:123284$5097 + assign { } { } + assign $0\ibus__sel[7:0] \ibus__sel$next + sync posedge \clk + update \ibus__sel $0\ibus__sel[7:0] + end + attribute \src "libresoc.v:123286.3-123287.35" + process $proc$libresoc.v:123286$5098 + assign { } { } + assign $0\ibus__stb[0:0] \ibus__stb$next + sync posedge \clk + update \ibus__stb $0\ibus__stb[0:0] + end + attribute \src "libresoc.v:123288.3-123289.35" + process $proc$libresoc.v:123288$5099 + assign { } { } + assign $0\ibus__cyc[0:0] \ibus__cyc$next + sync posedge \clk + update \ibus__cyc $0\ibus__cyc[0:0] + end + attribute \src "libresoc.v:123290.3-123312.6" + process $proc$libresoc.v:123290$5100 + assign { } { } + assign { } { } + assign { } { } + assign $0\ibus__cyc$next[0:0]$5101 $3\ibus__cyc$next[0:0]$5104 + attribute \src "libresoc.v:123291.5-123291.29" + switch \initial + attribute \src "libresoc.v:123291.9-123291.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:60" + switch { \$3 \ibus__cyc } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\ibus__cyc$next[0:0]$5102 $2\ibus__cyc$next[0:0]$5103 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + switch \$9 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ibus__cyc$next[0:0]$5103 1'0 + case + assign $2\ibus__cyc$next[0:0]$5103 \ibus__cyc + end + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\ibus__cyc$next[0:0]$5102 1'1 + case + assign $1\ibus__cyc$next[0:0]$5102 \ibus__cyc + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\ibus__cyc$next[0:0]$5104 1'0 + case + assign $3\ibus__cyc$next[0:0]$5104 $1\ibus__cyc$next[0:0]$5102 + end + sync always + update \ibus__cyc$next $0\ibus__cyc$next[0:0]$5101 + end + attribute \src "libresoc.v:123313.3-123335.6" + process $proc$libresoc.v:123313$5105 + assign { } { } + assign { } { } + assign { } { } + assign $0\ibus__stb$next[0:0]$5106 $3\ibus__stb$next[0:0]$5109 + attribute \src "libresoc.v:123314.5-123314.29" + switch \initial + attribute \src "libresoc.v:123314.9-123314.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:60" + switch { \$13 \ibus__cyc } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\ibus__stb$next[0:0]$5107 $2\ibus__stb$next[0:0]$5108 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + switch \$19 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ibus__stb$next[0:0]$5108 1'0 + case + assign $2\ibus__stb$next[0:0]$5108 \ibus__stb + end + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\ibus__stb$next[0:0]$5107 1'1 + case + assign $1\ibus__stb$next[0:0]$5107 \ibus__stb + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\ibus__stb$next[0:0]$5109 1'0 + case + assign $3\ibus__stb$next[0:0]$5109 $1\ibus__stb$next[0:0]$5107 + end + sync always + update \ibus__stb$next $0\ibus__stb$next[0:0]$5106 + end + attribute \src "libresoc.v:123336.3-123358.6" + process $proc$libresoc.v:123336$5110 + assign { } { } + assign { } { } + assign { } { } + assign $0\ibus__sel$next[7:0]$5111 $3\ibus__sel$next[7:0]$5114 + attribute \src "libresoc.v:123337.5-123337.29" + switch \initial + attribute \src "libresoc.v:123337.9-123337.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:60" + switch { \$23 \ibus__cyc } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\ibus__sel$next[7:0]$5112 $2\ibus__sel$next[7:0]$5113 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + switch \$29 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ibus__sel$next[7:0]$5113 8'00000000 + case + assign $2\ibus__sel$next[7:0]$5113 \ibus__sel + end + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\ibus__sel$next[7:0]$5112 8'11111111 + case + assign $1\ibus__sel$next[7:0]$5112 \ibus__sel + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\ibus__sel$next[7:0]$5114 8'00000000 + case + assign $3\ibus__sel$next[7:0]$5114 $1\ibus__sel$next[7:0]$5112 + end + sync always + update \ibus__sel$next $0\ibus__sel$next[7:0]$5111 + end + attribute \src "libresoc.v:123359.3-123378.6" + process $proc$libresoc.v:123359$5115 + assign { } { } + assign { } { } + assign { } { } + assign $0\ibus_rdata$next[63:0]$5116 $3\ibus_rdata$next[63:0]$5119 + attribute \src "libresoc.v:123360.5-123360.29" + switch \initial + attribute \src "libresoc.v:123360.9-123360.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:60" + switch { \$33 \ibus__cyc } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\ibus_rdata$next[63:0]$5117 $2\ibus_rdata$next[63:0]$5118 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + switch \$39 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ibus_rdata$next[63:0]$5118 \ibus__dat_r + case + assign $2\ibus_rdata$next[63:0]$5118 \ibus_rdata + end + case + assign $1\ibus_rdata$next[63:0]$5117 \ibus_rdata + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\ibus_rdata$next[63:0]$5119 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $3\ibus_rdata$next[63:0]$5119 $1\ibus_rdata$next[63:0]$5117 + end + sync always + update \ibus_rdata$next $0\ibus_rdata$next[63:0]$5116 + end + attribute \src "libresoc.v:123379.3-123396.6" + process $proc$libresoc.v:123379$5120 + assign { } { } + assign { } { } + assign { } { } + assign $0\ibus__adr$next[44:0]$5121 $2\ibus__adr$next[44:0]$5123 + attribute \src "libresoc.v:123380.5-123380.29" + switch \initial + attribute \src "libresoc.v:123380.9-123380.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:60" + switch { \$43 \ibus__cyc } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign $1\ibus__adr$next[44:0]$5122 \ibus__adr + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\ibus__adr$next[44:0]$5122 \a_pc_i [47:3] + case + assign $1\ibus__adr$next[44:0]$5122 \ibus__adr + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ibus__adr$next[44:0]$5123 45'000000000000000000000000000000000000000000000 + case + assign $2\ibus__adr$next[44:0]$5123 $1\ibus__adr$next[44:0]$5122 + end + sync always + update \ibus__adr$next $0\ibus__adr$next[44:0]$5121 + end + attribute \src "libresoc.v:123397.3-123414.6" + process $proc$libresoc.v:123397$5124 + assign { } { } + assign { } { } + assign { } { } + assign $0\f_fetch_err_o$next[0:0]$5125 $2\f_fetch_err_o$next[0:0]$5127 + attribute \src "libresoc.v:123398.5-123398.29" + switch \initial + attribute \src "libresoc.v:123398.9-123398.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:76" + switch { \$47 \$45 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\f_fetch_err_o$next[0:0]$5126 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\f_fetch_err_o$next[0:0]$5126 1'0 + case + assign $1\f_fetch_err_o$next[0:0]$5126 \f_fetch_err_o + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\f_fetch_err_o$next[0:0]$5127 1'0 + case + assign $2\f_fetch_err_o$next[0:0]$5127 $1\f_fetch_err_o$next[0:0]$5126 + end + sync always + update \f_fetch_err_o$next $0\f_fetch_err_o$next[0:0]$5125 + end + attribute \src "libresoc.v:123415.3-123429.6" + process $proc$libresoc.v:123415$5128 + assign { } { } + assign { } { } + assign { } { } + assign $0\f_badaddr_o$next[44:0]$5129 $2\f_badaddr_o$next[44:0]$5131 + attribute \src "libresoc.v:123416.5-123416.29" + switch \initial + attribute \src "libresoc.v:123416.9-123416.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:76" + switch { \$51 \$49 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\f_badaddr_o$next[44:0]$5130 \ibus__adr + case + assign $1\f_badaddr_o$next[44:0]$5130 \f_badaddr_o + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\f_badaddr_o$next[44:0]$5131 45'000000000000000000000000000000000000000000000 + case + assign $2\f_badaddr_o$next[44:0]$5131 $1\f_badaddr_o$next[44:0]$5130 + end + sync always + update \f_badaddr_o$next $0\f_badaddr_o$next[44:0]$5129 + end + attribute \src "libresoc.v:123430.3-123441.6" + process $proc$libresoc.v:123430$5132 + assign { } { } + assign $0\f_busy_o[0:0] $1\f_busy_o[0:0] + attribute \src "libresoc.v:123431.5-123431.29" + switch \initial + attribute \src "libresoc.v:123431.9-123431.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86" + switch \f_fetch_err_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\f_busy_o[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\f_busy_o[0:0] \ibus__cyc + end + sync always + update \f_busy_o $0\f_busy_o[0:0] + end + attribute \src "libresoc.v:123442.3-123454.6" + process $proc$libresoc.v:123442$5133 + assign { } { } + assign { } { } + assign $0\f_instr_o[63:0] $1\f_instr_o[63:0] + attribute \src "libresoc.v:123443.5-123443.29" + switch \initial + attribute \src "libresoc.v:123443.9-123443.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86" + switch \f_fetch_err_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $1\f_instr_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\f_instr_o[63:0] \ibus_rdata + end + sync always + update \f_instr_o $0\f_instr_o[63:0] + end + connect \$9 $or$libresoc.v:123250$5067_Y + connect \$11 $not$libresoc.v:123251$5068_Y + connect \$13 $and$libresoc.v:123252$5069_Y + connect \$15 $or$libresoc.v:123253$5070_Y + connect \$17 $not$libresoc.v:123254$5071_Y + connect \$1 $not$libresoc.v:123255$5072_Y + connect \$19 $or$libresoc.v:123256$5073_Y + connect \$21 $not$libresoc.v:123257$5074_Y + connect \$23 $and$libresoc.v:123258$5075_Y + connect \$25 $or$libresoc.v:123259$5076_Y + connect \$27 $not$libresoc.v:123260$5077_Y + connect \$29 $or$libresoc.v:123261$5078_Y + connect \$31 $not$libresoc.v:123262$5079_Y + connect \$33 $and$libresoc.v:123263$5080_Y + connect \$35 $or$libresoc.v:123264$5081_Y + connect \$37 $not$libresoc.v:123265$5082_Y + connect \$3 $and$libresoc.v:123266$5083_Y + connect \$39 $or$libresoc.v:123267$5084_Y + connect \$41 $not$libresoc.v:123268$5085_Y + connect \$43 $and$libresoc.v:123269$5086_Y + connect \$45 $and$libresoc.v:123270$5087_Y + connect \$47 $not$libresoc.v:123271$5088_Y + connect \$49 $and$libresoc.v:123272$5089_Y + connect \$51 $not$libresoc.v:123273$5090_Y + connect \$5 $or$libresoc.v:123274$5091_Y + connect \$7 $not$libresoc.v:123275$5092_Y + connect \a_stall_i 1'0 + connect \f_stall_i 1'0 + connect \a_busy_o \ibus__cyc +end +attribute \src "libresoc.v:123462.1-123783.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alu_alu0.pipe1.input" +attribute \generator "nMigen" +module \input + attribute \src "libresoc.v:123746.3-123757.6" + wire width 64 $0\a[63:0] + attribute \src "libresoc.v:123463.7-123463.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:123758.3-123776.6" + wire width 2 $0\xer_ca$23[1:0]$5145 + attribute \src "libresoc.v:123746.3-123757.6" + wire width 64 $1\a[63:0] + attribute \src "libresoc.v:123758.3-123776.6" + wire width 2 $1\xer_ca$23[1:0]$5146 + attribute \src "libresoc.v:123745.18-123745.100" + wire width 64 $not$libresoc.v:123745$5142_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28" + wire width 64 \$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:20" + wire width 64 \a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 17 \alu_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 40 \alu_op__data_len$18 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 2 \alu_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 output 25 \alu_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 3 \alu_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 26 \alu_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 4 \alu_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 27 \alu_op__imm_data__ok$5 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 13 \alu_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 36 \alu_op__input_carry$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 18 \alu_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 41 \alu_op__insn$19 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \alu_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 24 \alu_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \alu_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 32 \alu_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 11 \alu_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 34 \alu_op__invert_out$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 15 \alu_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 38 \alu_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 16 \alu_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 39 \alu_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 7 \alu_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 30 \alu_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \alu_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 31 \alu_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \alu_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 37 \alu_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 6 \alu_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 29 \alu_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 5 \alu_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 28 \alu_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \alu_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 35 \alu_op__write_cr0$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \alu_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 33 \alu_op__zero_a$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:39" + wire width 64 \b + attribute \src "libresoc.v:123463.7-123463.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 46 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 23 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 19 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 42 \ra$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 20 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 43 \rb$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 input 22 \xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 output 45 \xer_ca$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 21 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire output 44 \xer_so$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28" + cell $not $not$libresoc.v:123745$5142 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \ra + connect \Y $not$libresoc.v:123745$5142_Y + end + attribute \src "libresoc.v:123463.7-123463.20" + process $proc$libresoc.v:123463$5147 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:123746.3-123757.6" + process $proc$libresoc.v:123746$5143 + assign { } { } + assign $0\a[63:0] $1\a[63:0] + attribute \src "libresoc.v:123747.5-123747.29" + switch \initial + attribute \src "libresoc.v:123747.9-123747.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:27" + switch \alu_op__invert_in + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\a[63:0] \$24 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\a[63:0] \ra + end + sync always + update \a $0\a[63:0] + end + attribute \src "libresoc.v:123758.3-123776.6" + process $proc$libresoc.v:123758$5144 + assign { } { } + assign { } { } + assign $0\xer_ca$23[1:0]$5145 $1\xer_ca$23[1:0]$5146 + attribute \src "libresoc.v:123759.5-123759.29" + switch \initial + attribute \src "libresoc.v:123759.9-123759.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:55" + switch \alu_op__input_carry + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\xer_ca$23[1:0]$5146 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\xer_ca$23[1:0]$5146 2'11 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\xer_ca$23[1:0]$5146 \xer_ca + case + assign $1\xer_ca$23[1:0]$5146 2'00 + end + sync always + update \xer_ca$23 $0\xer_ca$23[1:0]$5145 + end + connect \$24 $not$libresoc.v:123745$5142_Y + connect { \alu_op__insn$19 \alu_op__data_len$18 \alu_op__is_signed$17 \alu_op__is_32bit$16 \alu_op__output_carry$15 \alu_op__input_carry$14 \alu_op__write_cr0$13 \alu_op__invert_out$12 \alu_op__zero_a$11 \alu_op__invert_in$10 \alu_op__oe__ok$9 \alu_op__oe__oe$8 \alu_op__rc__ok$7 \alu_op__rc__rc$6 \alu_op__imm_data__ok$5 \alu_op__imm_data__data$4 \alu_op__fn_unit$3 \alu_op__insn_type$2 } { \alu_op__insn \alu_op__data_len \alu_op__is_signed \alu_op__is_32bit \alu_op__output_carry \alu_op__input_carry \alu_op__write_cr0 \alu_op__invert_out \alu_op__zero_a \alu_op__invert_in \alu_op__oe__ok \alu_op__oe__oe \alu_op__rc__ok \alu_op__rc__rc \alu_op__imm_data__ok \alu_op__imm_data__data \alu_op__fn_unit \alu_op__insn_type } + connect \muxid$1 \muxid + connect \xer_so$22 \xer_so + connect \rb$21 \rb + connect \b \rb + connect \ra$20 \a +end +attribute \src "libresoc.v:123787.1-124091.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.pipe1.input" +attribute \generator "nMigen" +module \input$110 + attribute \src "libresoc.v:123788.7-123788.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:124064.3-124082.6" + wire width 2 $0\xer_ca$22[1:0]$5149 + attribute \src "libresoc.v:124064.3-124082.6" + wire width 2 $1\xer_ca$22[1:0]$5150 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:20" + wire width 64 \a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:39" + wire width 64 \b + attribute \src "libresoc.v:123788.7-123788.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 44 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 22 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 17 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 39 \ra$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 18 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 40 \rb$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 19 \rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 41 \rc$20 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 2 \sr_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 output 24 \sr_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 3 \sr_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 25 \sr_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 4 \sr_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 26 \sr_op__imm_data__ok$5 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 10 \sr_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 32 \sr_op__input_carry$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \sr_op__input_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 34 \sr_op__input_cr$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 16 \sr_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 38 \sr_op__insn$17 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \sr_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 23 \sr_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \sr_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 36 \sr_op__is_32bit$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 15 \sr_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 37 \sr_op__is_signed$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 7 \sr_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 29 \sr_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \sr_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 30 \sr_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 11 \sr_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 33 \sr_op__output_carry$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \sr_op__output_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 35 \sr_op__output_cr$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 6 \sr_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 28 \sr_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 5 \sr_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 27 \sr_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \sr_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 31 \sr_op__write_cr0$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 input 21 \xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 output 43 \xer_ca$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 20 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire output 42 \xer_so$21 + attribute \src "libresoc.v:123788.7-123788.20" + process $proc$libresoc.v:123788$5151 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:124064.3-124082.6" + process $proc$libresoc.v:124064$5148 + assign { } { } + assign { } { } + assign $0\xer_ca$22[1:0]$5149 $1\xer_ca$22[1:0]$5150 + attribute \src "libresoc.v:124065.5-124065.29" + switch \initial + attribute \src "libresoc.v:124065.9-124065.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:55" + switch \sr_op__input_carry + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\xer_ca$22[1:0]$5150 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\xer_ca$22[1:0]$5150 2'11 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\xer_ca$22[1:0]$5150 \xer_ca + case + assign $1\xer_ca$22[1:0]$5150 2'00 + end + sync always + update \xer_ca$22 $0\xer_ca$22[1:0]$5149 + end + connect \rc$20 \rc + connect { \sr_op__insn$17 \sr_op__is_signed$16 \sr_op__is_32bit$15 \sr_op__output_cr$14 \sr_op__input_cr$13 \sr_op__output_carry$12 \sr_op__input_carry$11 \sr_op__write_cr0$10 \sr_op__oe__ok$9 \sr_op__oe__oe$8 \sr_op__rc__ok$7 \sr_op__rc__rc$6 \sr_op__imm_data__ok$5 \sr_op__imm_data__data$4 \sr_op__fn_unit$3 \sr_op__insn_type$2 } { \sr_op__insn \sr_op__is_signed \sr_op__is_32bit \sr_op__output_cr \sr_op__input_cr \sr_op__output_carry \sr_op__input_carry \sr_op__write_cr0 \sr_op__oe__ok \sr_op__oe__oe \sr_op__rc__ok \sr_op__rc__rc \sr_op__imm_data__ok \sr_op__imm_data__data \sr_op__fn_unit \sr_op__insn_type } + connect \muxid$1 \muxid + connect \xer_so$21 \xer_so + connect \rb$19 \b + connect \b \rb + connect \ra$18 \a + connect \a \ra +end +attribute \src "libresoc.v:124095.1-124392.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_logical0.logical_pipe1.input" +attribute \generator "nMigen" +module \input$47 + attribute \src "libresoc.v:124374.3-124385.6" + wire width 64 $0\b[63:0] + attribute \src "libresoc.v:124096.7-124096.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:124374.3-124385.6" + wire width 64 $1\b[63:0] + attribute \src "libresoc.v:124373.18-124373.100" + wire width 64 $not$libresoc.v:124373$5152_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:43" + wire width 64 \$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:20" + wire width 64 \a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:39" + wire width 64 \b + attribute \src "libresoc.v:124096.7-124096.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 17 \logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 39 \logical_op__data_len$18 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 2 \logical_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 output 24 \logical_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 3 \logical_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 25 \logical_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 4 \logical_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 26 \logical_op__imm_data__ok$5 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 11 \logical_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 33 \logical_op__input_carry$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 18 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 40 \logical_op__insn$19 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \logical_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 23 \logical_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 31 \logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 34 \logical_op__invert_out$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 15 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 37 \logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 16 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 38 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 7 \logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 29 \logical_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 30 \logical_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 36 \logical_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 6 \logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 28 \logical_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 5 \logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 27 \logical_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 35 \logical_op__write_cr0$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 32 \logical_op__zero_a$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 44 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 22 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 19 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 41 \ra$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 20 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 42 \rb$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 21 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire output 43 \xer_so$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:43" + cell $not $not$libresoc.v:124373$5152 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \rb + connect \Y $not$libresoc.v:124373$5152_Y + end + attribute \src "libresoc.v:124096.7-124096.20" + process $proc$libresoc.v:124096$5154 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:124374.3-124385.6" + process $proc$libresoc.v:124374$5153 + assign { } { } + assign $0\b[63:0] $1\b[63:0] + attribute \src "libresoc.v:124375.5-124375.29" + switch \initial + attribute \src "libresoc.v:124375.9-124375.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:42" + switch \logical_op__invert_in + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\b[63:0] \$23 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\b[63:0] \rb + end + sync always + update \b $0\b[63:0] + end + connect \$23 $not$libresoc.v:124373$5152_Y + connect { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } + connect \muxid$1 \muxid + connect \xer_so$22 \xer_so + connect \rb$21 \b + connect \ra$20 \a + connect \a \ra +end +attribute \src "libresoc.v:124396.1-124693.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_start.input" +attribute \generator "nMigen" +module \input$75 + attribute \src "libresoc.v:124675.3-124686.6" + wire width 64 $0\a[63:0] + attribute \src "libresoc.v:124397.7-124397.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:124675.3-124686.6" + wire width 64 $1\a[63:0] + attribute \src "libresoc.v:124674.18-124674.100" + wire width 64 $not$libresoc.v:124674$5155_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28" + wire width 64 \$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:20" + wire width 64 \a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:39" + wire width 64 \b + attribute \src "libresoc.v:124397.7-124397.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 17 \logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 39 \logical_op__data_len$18 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 2 \logical_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 output 24 \logical_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 3 \logical_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 25 \logical_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 4 \logical_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 26 \logical_op__imm_data__ok$5 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 11 \logical_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 33 \logical_op__input_carry$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 18 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 40 \logical_op__insn$19 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \logical_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 23 \logical_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 31 \logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 34 \logical_op__invert_out$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 15 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 37 \logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 16 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 38 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 7 \logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 29 \logical_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 30 \logical_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 36 \logical_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 6 \logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 28 \logical_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 5 \logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 27 \logical_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 35 \logical_op__write_cr0$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 32 \logical_op__zero_a$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 44 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 22 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 19 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 41 \ra$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 20 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 42 \rb$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 21 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire output 43 \xer_so$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28" + cell $not $not$libresoc.v:124674$5155 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \ra + connect \Y $not$libresoc.v:124674$5155_Y + end + attribute \src "libresoc.v:124397.7-124397.20" + process $proc$libresoc.v:124397$5157 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:124675.3-124686.6" + process $proc$libresoc.v:124675$5156 + assign { } { } + assign $0\a[63:0] $1\a[63:0] + attribute \src "libresoc.v:124676.5-124676.29" + switch \initial + attribute \src "libresoc.v:124676.9-124676.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:27" + switch \logical_op__invert_in + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\a[63:0] \$23 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\a[63:0] \ra + end + sync always + update \a $0\a[63:0] + end + connect \$23 $not$libresoc.v:124674$5155_Y + connect { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } + connect \muxid$1 \muxid + connect \xer_so$22 \xer_so + connect \rb$21 \rb + connect \b \rb + connect \ra$20 \a +end +attribute \src "libresoc.v:124697.1-124947.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe1.input" +attribute \generator "nMigen" +module \input$92 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:20" + wire width 64 \a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:39" + wire width 64 \b + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 2 \mul_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 output 18 \mul_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 3 \mul_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 19 \mul_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 4 \mul_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 20 \mul_op__imm_data__ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 12 \mul_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 28 \mul_op__insn$13 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \mul_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 17 \mul_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \mul_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 26 \mul_op__is_32bit$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 11 \mul_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 27 \mul_op__is_signed$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 7 \mul_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 23 \mul_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \mul_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 24 \mul_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 6 \mul_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 22 \mul_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 5 \mul_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 21 \mul_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \mul_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 25 \mul_op__write_cr0$10 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 32 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 16 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 13 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 29 \ra$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 14 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 30 \rb$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 15 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire output 31 \xer_so$16 + connect { \mul_op__insn$13 \mul_op__is_signed$12 \mul_op__is_32bit$11 \mul_op__write_cr0$10 \mul_op__oe__ok$9 \mul_op__oe__oe$8 \mul_op__rc__ok$7 \mul_op__rc__rc$6 \mul_op__imm_data__ok$5 \mul_op__imm_data__data$4 \mul_op__fn_unit$3 \mul_op__insn_type$2 } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__oe__ok \mul_op__oe__oe \mul_op__rc__ok \mul_op__rc__rc \mul_op__imm_data__ok \mul_op__imm_data__data \mul_op__fn_unit \mul_op__insn_type } + connect \muxid$1 \muxid + connect \xer_so$16 \xer_so + connect \rb$15 \rb + connect \b \rb + connect \ra$14 \a + connect \a \ra +end +attribute \src "libresoc.v:124951.1-125170.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.int" +attribute \generator "nMigen" +module \int + attribute \src "libresoc.v:125076.3-125082.6" + wire width 5 $0$memwr$\memory$libresoc.v:125081$5190_ADDR[4:0]$5199 + attribute \src "libresoc.v:125076.3-125082.6" + wire width 64 $0$memwr$\memory$libresoc.v:125081$5190_DATA[63:0]$5200 + attribute \src "libresoc.v:125076.3-125082.6" + wire width 64 $0$memwr$\memory$libresoc.v:125081$5190_EN[63:0]$5201 + attribute \src "libresoc.v:125076.3-125082.6" + wire width 5 $0\_0_[4:0] + attribute \src "libresoc.v:125076.3-125082.6" + wire width 5 $0\_1_[4:0] + attribute \src "libresoc.v:125076.3-125082.6" + wire width 5 $0\_2_[4:0] + attribute \src "libresoc.v:125076.3-125082.6" + wire width 5 $0\_3_[4:0] + attribute \src "libresoc.v:125105.3-125114.6" + wire width 64 $0\dmi__data_o[63:0] + attribute \src "libresoc.v:124952.7-124952.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:125096.3-125104.6" + wire $0\ren_delay$10$next[0:0]$5210 + attribute \src "libresoc.v:125029.3-125030.43" + wire $0\ren_delay$10[0:0]$5192 + attribute \src "libresoc.v:124995.7-124995.28" + wire $0\ren_delay$10[0:0]$5258 + attribute \src "libresoc.v:125125.3-125133.6" + wire $0\ren_delay$8$next[0:0]$5215 + attribute \src "libresoc.v:125033.3-125034.41" + wire $0\ren_delay$8[0:0]$5196 + attribute \src "libresoc.v:124999.7-124999.27" + wire $0\ren_delay$8[0:0]$5260 + attribute \src "libresoc.v:125144.3-125152.6" + wire $0\ren_delay$9$next[0:0]$5219 + attribute \src "libresoc.v:125031.3-125032.41" + wire $0\ren_delay$9[0:0]$5194 + attribute \src "libresoc.v:125003.7-125003.27" + wire $0\ren_delay$9[0:0]$5262 + attribute \src "libresoc.v:125087.3-125095.6" + wire $0\ren_delay$next[0:0]$5207 + attribute \src "libresoc.v:125035.3-125036.35" + wire $0\ren_delay[0:0] + attribute \src "libresoc.v:125115.3-125124.6" + wire width 64 $0\src1__data_o[63:0] + attribute \src "libresoc.v:125134.3-125143.6" + wire width 64 $0\src2__data_o[63:0] + attribute \src "libresoc.v:125153.3-125162.6" + wire width 64 $0\src3__data_o[63:0] + attribute \src "libresoc.v:125105.3-125114.6" + wire width 64 $1\dmi__data_o[63:0] + attribute \src "libresoc.v:125096.3-125104.6" + wire $1\ren_delay$10$next[0:0]$5211 + attribute \src "libresoc.v:125125.3-125133.6" + wire $1\ren_delay$8$next[0:0]$5216 + attribute \src "libresoc.v:125144.3-125152.6" + wire $1\ren_delay$9$next[0:0]$5220 + attribute \src "libresoc.v:125087.3-125095.6" + wire $1\ren_delay$next[0:0]$5208 + attribute \src "libresoc.v:124993.7-124993.23" + wire $1\ren_delay[0:0] + attribute \src "libresoc.v:125115.3-125124.6" + wire width 64 $1\src1__data_o[63:0] + attribute \src "libresoc.v:125134.3-125143.6" + wire width 64 $1\src2__data_o[63:0] + attribute \src "libresoc.v:125153.3-125162.6" + wire width 64 $1\src3__data_o[63:0] + attribute \src "libresoc.v:125083.26-125083.32" + wire width 64 $memrd$\memory$libresoc.v:125083$5202_DATA + attribute \src "libresoc.v:125084.30-125084.36" + wire width 64 $memrd$\memory$libresoc.v:125084$5203_DATA + attribute \src "libresoc.v:125085.30-125085.36" + wire width 64 $memrd$\memory$libresoc.v:125085$5204_DATA + attribute \src "libresoc.v:125086.30-125086.36" + wire width 64 $memrd$\memory$libresoc.v:125086$5205_DATA + attribute \src "libresoc.v:0.0-0.0" + wire width 5 $memwr$\memory$libresoc.v:125081$5190_ADDR + attribute \src "libresoc.v:0.0-0.0" + wire width 64 $memwr$\memory$libresoc.v:125081$5190_DATA + attribute \src "libresoc.v:0.0-0.0" + wire width 64 $memwr$\memory$libresoc.v:125081$5190_EN + attribute \src "libresoc.v:125072.13-125072.16" + wire width 5 \_0_ + attribute \src "libresoc.v:125073.13-125073.16" + wire width 5 \_1_ + attribute \src "libresoc.v:125074.13-125074.16" + wire width 5 \_2_ + attribute \src "libresoc.v:125075.13-125075.16" + wire width 5 \_3_ + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 17 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 16 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 5 input 14 \dest1__addr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 input 13 \dest1__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 15 \dest1__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 5 input 1 \dmi__addr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 output 3 \dmi__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 2 \dmi__ren + attribute \src "libresoc.v:124952.7-124952.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" + wire width 5 \memory_r_addr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" + wire width 5 \memory_r_addr$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" + wire width 5 \memory_r_addr$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" + wire width 5 \memory_r_addr$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" + wire width 64 \memory_r_data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" + wire width 64 \memory_r_data$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" + wire width 64 \memory_r_data$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" + wire width 64 \memory_r_data$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" + wire width 5 \memory_w_addr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" + wire width 64 \memory_w_data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" + wire \memory_w_en + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" + wire \ren_delay + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" + wire \ren_delay$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" + wire \ren_delay$10$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" + wire \ren_delay$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" + wire \ren_delay$8$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" + wire \ren_delay$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" + wire \ren_delay$9$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" + wire \ren_delay$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 5 input 5 \src1__addr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 output 4 \src1__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 6 \src1__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 5 input 8 \src2__addr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 output 7 \src2__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 9 \src2__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 5 input 11 \src3__addr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 output 10 \src3__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 12 \src3__ren + attribute \src "libresoc.v:125037.14-125037.20" + memory width 64 size 32 \memory + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5222 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5222 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 0 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5223 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5223 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 1 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5224 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5224 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 2 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5225 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5225 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 3 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5226 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5226 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 4 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5227 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5227 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 5 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5228 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5228 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 6 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5229 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5229 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 7 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5230 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5230 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 8 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5231 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5231 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 9 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5232 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5232 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 10 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5233 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5233 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 11 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5234 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5234 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 12 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5235 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5235 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 13 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5236 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5236 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 14 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5237 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5237 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 15 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5238 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5238 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 16 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5239 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5239 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 17 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5240 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5240 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 18 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5241 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5241 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 19 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5242 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5242 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 20 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5243 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5243 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 21 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5244 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5244 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 22 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5245 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5245 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 23 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5246 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5246 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 24 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5247 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5247 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 25 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5248 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5248 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 26 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5249 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5249 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 27 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5250 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5250 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 28 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5251 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5251 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 29 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5252 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5252 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 30 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5253 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5253 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 31 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:125083.26-125083.32" + cell $memrd $memrd$\memory$libresoc.v:125083$5202 + parameter \ABITS 5 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\memory" + parameter \TRANSPARENT 0 + parameter \WIDTH 64 + connect \ADDR \_0_ + connect \CLK 1'x + connect \DATA $memrd$\memory$libresoc.v:125083$5202_DATA + connect \EN 1'x + end + attribute \src "libresoc.v:125084.30-125084.36" + cell $memrd $memrd$\memory$libresoc.v:125084$5203 + parameter \ABITS 5 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\memory" + parameter \TRANSPARENT 0 + parameter \WIDTH 64 + connect \ADDR \_1_ + connect \CLK 1'x + connect \DATA $memrd$\memory$libresoc.v:125084$5203_DATA + connect \EN 1'x + end + attribute \src "libresoc.v:125085.30-125085.36" + cell $memrd $memrd$\memory$libresoc.v:125085$5204 + parameter \ABITS 5 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\memory" + parameter \TRANSPARENT 0 + parameter \WIDTH 64 + connect \ADDR \_2_ + connect \CLK 1'x + connect \DATA $memrd$\memory$libresoc.v:125085$5204_DATA + connect \EN 1'x + end + attribute \src "libresoc.v:125086.30-125086.36" + cell $memrd $memrd$\memory$libresoc.v:125086$5205 + parameter \ABITS 5 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\memory" + parameter \TRANSPARENT 0 + parameter \WIDTH 64 + connect \ADDR \_3_ + connect \CLK 1'x + connect \DATA $memrd$\memory$libresoc.v:125086$5205_DATA + connect \EN 1'x + end + attribute \src "libresoc.v:0.0-0.0" + cell $memwr $memwr$\memory$libresoc.v:0$5254 + parameter \ABITS 5 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\memory" + parameter \PRIORITY 5254 + parameter \WIDTH 64 + connect \ADDR $memwr$\memory$libresoc.v:125081$5190_ADDR + connect \CLK 1'x + connect \DATA $memwr$\memory$libresoc.v:125081$5190_DATA + connect \EN $memwr$\memory$libresoc.v:125081$5190_EN + end + attribute \src "libresoc.v:0.0-0.0" + process $proc$libresoc.v:0$5263 + sync always + sync init + end + attribute \src "libresoc.v:124952.7-124952.20" + process $proc$libresoc.v:124952$5255 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:124993.7-124993.23" + process $proc$libresoc.v:124993$5256 + assign { } { } + assign $1\ren_delay[0:0] 1'0 + sync always + sync init + update \ren_delay $1\ren_delay[0:0] + end + attribute \src "libresoc.v:124995.7-124995.28" + process $proc$libresoc.v:124995$5257 + assign { } { } + assign $0\ren_delay$10[0:0]$5258 1'0 + sync always + sync init + update \ren_delay$10 $0\ren_delay$10[0:0]$5258 + end + attribute \src "libresoc.v:124999.7-124999.27" + process $proc$libresoc.v:124999$5259 + assign { } { } + assign $0\ren_delay$8[0:0]$5260 1'0 + sync always + sync init + update \ren_delay$8 $0\ren_delay$8[0:0]$5260 + end + attribute \src "libresoc.v:125003.7-125003.27" + process $proc$libresoc.v:125003$5261 + assign { } { } + assign $0\ren_delay$9[0:0]$5262 1'0 + sync always + sync init + update \ren_delay$9 $0\ren_delay$9[0:0]$5262 + end + attribute \src "libresoc.v:125029.3-125030.43" + process $proc$libresoc.v:125029$5191 + assign { } { } + assign $0\ren_delay$10[0:0]$5192 \ren_delay$10$next + sync posedge \coresync_clk + update \ren_delay$10 $0\ren_delay$10[0:0]$5192 + end + attribute \src "libresoc.v:125031.3-125032.41" + process $proc$libresoc.v:125031$5193 + assign { } { } + assign $0\ren_delay$9[0:0]$5194 \ren_delay$9$next + sync posedge \coresync_clk + update \ren_delay$9 $0\ren_delay$9[0:0]$5194 + end + attribute \src "libresoc.v:125033.3-125034.41" + process $proc$libresoc.v:125033$5195 + assign { } { } + assign $0\ren_delay$8[0:0]$5196 \ren_delay$8$next + sync posedge \coresync_clk + update \ren_delay$8 $0\ren_delay$8[0:0]$5196 + end + attribute \src "libresoc.v:125035.3-125036.35" + process $proc$libresoc.v:125035$5197 + assign { } { } + assign $0\ren_delay[0:0] \ren_delay$next + sync posedge \coresync_clk + update \ren_delay $0\ren_delay[0:0] + end + attribute \src "libresoc.v:125076.3-125082.6" + process $proc$libresoc.v:125076$5198 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\memory$libresoc.v:125081$5190_ADDR[4:0]$5199 5'xxxxx + assign $0$memwr$\memory$libresoc.v:125081$5190_DATA[63:0]$5200 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\memory$libresoc.v:125081$5190_EN[63:0]$5201 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\_0_[4:0] \src1__addr + assign $0\_1_[4:0] \src2__addr + assign $0\_2_[4:0] \src3__addr + assign $0\_3_[4:0] \dmi__addr + attribute \src "libresoc.v:125081.5-125081.58" + switch \dest1__wen + attribute \src "libresoc.v:125081.9-125081.19" + case 1'1 + assign $0$memwr$\memory$libresoc.v:125081$5190_ADDR[4:0]$5199 \dest1__addr + assign $0$memwr$\memory$libresoc.v:125081$5190_DATA[63:0]$5200 \dest1__data_i + assign $0$memwr$\memory$libresoc.v:125081$5190_EN[63:0]$5201 64'1111111111111111111111111111111111111111111111111111111111111111 + case + end + sync posedge \coresync_clk + update \_0_ $0\_0_[4:0] + update \_1_ $0\_1_[4:0] + update \_2_ $0\_2_[4:0] + update \_3_ $0\_3_[4:0] + update $memwr$\memory$libresoc.v:125081$5190_ADDR $0$memwr$\memory$libresoc.v:125081$5190_ADDR[4:0]$5199 + update $memwr$\memory$libresoc.v:125081$5190_DATA $0$memwr$\memory$libresoc.v:125081$5190_DATA[63:0]$5200 + update $memwr$\memory$libresoc.v:125081$5190_EN $0$memwr$\memory$libresoc.v:125081$5190_EN[63:0]$5201 + end + attribute \src "libresoc.v:125087.3-125095.6" + process $proc$libresoc.v:125087$5206 + assign { } { } + assign { } { } + assign $0\ren_delay$next[0:0]$5207 $1\ren_delay$next[0:0]$5208 + attribute \src "libresoc.v:125088.5-125088.29" + switch \initial + attribute \src "libresoc.v:125088.9-125088.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ren_delay$next[0:0]$5208 1'0 + case + assign $1\ren_delay$next[0:0]$5208 \src1__ren + end + sync always + update \ren_delay$next $0\ren_delay$next[0:0]$5207 + end + attribute \src "libresoc.v:125096.3-125104.6" + process $proc$libresoc.v:125096$5209 + assign { } { } + assign { } { } + assign $0\ren_delay$10$next[0:0]$5210 $1\ren_delay$10$next[0:0]$5211 + attribute \src "libresoc.v:125097.5-125097.29" + switch \initial + attribute \src "libresoc.v:125097.9-125097.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ren_delay$10$next[0:0]$5211 1'0 + case + assign $1\ren_delay$10$next[0:0]$5211 \dmi__ren + end + sync always + update \ren_delay$10$next $0\ren_delay$10$next[0:0]$5210 + end + attribute \src "libresoc.v:125105.3-125114.6" + process $proc$libresoc.v:125105$5212 + assign { } { } + assign { } { } + assign $0\dmi__data_o[63:0] $1\dmi__data_o[63:0] + attribute \src "libresoc.v:125106.5-125106.29" + switch \initial + attribute \src "libresoc.v:125106.9-125106.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" + switch \ren_delay$10 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dmi__data_o[63:0] \memory_r_data$7 + case + assign $1\dmi__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \dmi__data_o $0\dmi__data_o[63:0] + end + attribute \src "libresoc.v:125115.3-125124.6" + process $proc$libresoc.v:125115$5213 + assign { } { } + assign { } { } + assign $0\src1__data_o[63:0] $1\src1__data_o[63:0] + attribute \src "libresoc.v:125116.5-125116.29" + switch \initial + attribute \src "libresoc.v:125116.9-125116.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" + switch \ren_delay + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src1__data_o[63:0] \memory_r_data + case + assign $1\src1__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \src1__data_o $0\src1__data_o[63:0] + end + attribute \src "libresoc.v:125125.3-125133.6" + process $proc$libresoc.v:125125$5214 + assign { } { } + assign { } { } + assign $0\ren_delay$8$next[0:0]$5215 $1\ren_delay$8$next[0:0]$5216 + attribute \src "libresoc.v:125126.5-125126.29" + switch \initial + attribute \src "libresoc.v:125126.9-125126.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ren_delay$8$next[0:0]$5216 1'0 + case + assign $1\ren_delay$8$next[0:0]$5216 \src2__ren + end + sync always + update \ren_delay$8$next $0\ren_delay$8$next[0:0]$5215 + end + attribute \src "libresoc.v:125134.3-125143.6" + process $proc$libresoc.v:125134$5217 + assign { } { } + assign { } { } + assign $0\src2__data_o[63:0] $1\src2__data_o[63:0] + attribute \src "libresoc.v:125135.5-125135.29" + switch \initial + attribute \src "libresoc.v:125135.9-125135.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" + switch \ren_delay$8 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src2__data_o[63:0] \memory_r_data$3 + case + assign $1\src2__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \src2__data_o $0\src2__data_o[63:0] + end + attribute \src "libresoc.v:125144.3-125152.6" + process $proc$libresoc.v:125144$5218 + assign { } { } + assign { } { } + assign $0\ren_delay$9$next[0:0]$5219 $1\ren_delay$9$next[0:0]$5220 + attribute \src "libresoc.v:125145.5-125145.29" + switch \initial + attribute \src "libresoc.v:125145.9-125145.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ren_delay$9$next[0:0]$5220 1'0 + case + assign $1\ren_delay$9$next[0:0]$5220 \src3__ren + end + sync always + update \ren_delay$9$next $0\ren_delay$9$next[0:0]$5219 + end + attribute \src "libresoc.v:125153.3-125162.6" + process $proc$libresoc.v:125153$5221 + assign { } { } + assign { } { } + assign $0\src3__data_o[63:0] $1\src3__data_o[63:0] + attribute \src "libresoc.v:125154.5-125154.29" + switch \initial + attribute \src "libresoc.v:125154.9-125154.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" + switch \ren_delay$9 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src3__data_o[63:0] \memory_r_data$5 + case + assign $1\src3__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \src3__data_o $0\src3__data_o[63:0] + end + connect \memory_r_data $memrd$\memory$libresoc.v:125083$5202_DATA + connect \memory_r_data$3 $memrd$\memory$libresoc.v:125084$5203_DATA + connect \memory_r_data$5 $memrd$\memory$libresoc.v:125085$5204_DATA + connect \memory_r_data$7 $memrd$\memory$libresoc.v:125086$5205_DATA + connect \memory_w_data \dest1__data_i + connect \memory_w_en \dest1__wen + connect \memory_w_addr \dest1__addr + connect \memory_r_addr$6 \dmi__addr + connect \memory_r_addr$4 \src3__addr + connect \memory_r_addr$2 \src2__addr + connect \memory_r_addr \src1__addr +end +attribute \src "libresoc.v:125174.1-126925.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.jtag" +attribute \generator "nMigen" +module \jtag + attribute \src "libresoc.v:126201.3-126224.6" + wire $0\TAP_bus__tdo[0:0] + attribute \src "libresoc.v:126562.3-126577.6" + wire $0\TAP_tdo[0:0] + attribute \src "libresoc.v:126359.3-126391.6" + wire width 4 $0\dmi0_addr_i$next[3:0]$5475 + attribute \src "libresoc.v:126065.3-126066.39" + wire width 4 $0\dmi0_addr_i[3:0] + attribute \src "libresoc.v:126785.3-126801.6" + wire $0\dmi0_addrsr__oe$next[0:0]$5558 + attribute \src "libresoc.v:126085.3-126086.47" + wire $0\dmi0_addrsr__oe[0:0] + attribute \src "libresoc.v:126802.3-126822.6" + wire width 8 $0\dmi0_addrsr_reg$next[7:0]$5562 + attribute \src "libresoc.v:126083.3-126084.47" + wire width 8 $0\dmi0_addrsr_reg[7:0] + attribute \src "libresoc.v:126767.3-126775.6" + wire $0\dmi0_addrsr_update_core$next[0:0]$5552 + attribute \src "libresoc.v:126089.3-126090.63" + wire $0\dmi0_addrsr_update_core[0:0] + attribute \src "libresoc.v:126776.3-126784.6" + wire $0\dmi0_addrsr_update_core_prev$next[0:0]$5555 + attribute \src "libresoc.v:126087.3-126088.73" + wire $0\dmi0_addrsr_update_core_prev[0:0] + attribute \src "libresoc.v:126472.3-126492.6" + wire width 64 $0\dmi0_datasr__i$next[63:0]$5493 + attribute \src "libresoc.v:126059.3-126060.45" + wire width 64 $0\dmi0_datasr__i[63:0] + attribute \src "libresoc.v:126163.3-126179.6" + wire width 2 $0\dmi0_datasr__oe$next[1:0]$5442 + attribute \src "libresoc.v:126077.3-126078.47" + wire width 2 $0\dmi0_datasr__oe[1:0] + attribute \src "libresoc.v:126180.3-126200.6" + wire width 64 $0\dmi0_datasr_reg$next[63:0]$5446 + attribute \src "libresoc.v:126075.3-126076.47" + wire width 64 $0\dmi0_datasr_reg[63:0] + attribute \src "libresoc.v:126823.3-126831.6" + wire $0\dmi0_datasr_update_core$next[0:0]$5567 + attribute \src "libresoc.v:126081.3-126082.63" + wire $0\dmi0_datasr_update_core[0:0] + attribute \src "libresoc.v:126154.3-126162.6" + wire $0\dmi0_datasr_update_core_prev$next[0:0]$5439 + attribute \src "libresoc.v:126079.3-126080.73" + wire $0\dmi0_datasr_update_core_prev[0:0] + attribute \src "libresoc.v:126445.3-126471.6" + wire width 64 $0\dmi0_din$next[63:0]$5488 + attribute \src "libresoc.v:126061.3-126062.33" + wire width 64 $0\dmi0_din[63:0] + attribute \src "libresoc.v:126392.3-126444.6" + wire width 3 $0\fsm_state$275$next[2:0]$5481 + attribute \src "libresoc.v:126063.3-126064.45" + wire width 3 $0\fsm_state$275[2:0]$5410 + attribute \src "libresoc.v:125576.13-125576.35" + wire width 3 $0\fsm_state$275[2:0]$5583 + attribute \src "libresoc.v:126258.3-126310.6" + wire width 3 $0\fsm_state$next[2:0]$5458 + attribute \src "libresoc.v:126071.3-126072.35" + wire width 3 $0\fsm_state[2:0] + attribute \src "libresoc.v:125175.7-125175.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:126578.3-126598.6" + wire width 50 $0\io_bd$next[49:0]$5503 + attribute \src "libresoc.v:126115.3-126116.27" + wire width 50 $0\io_bd[49:0] + attribute \src "libresoc.v:126493.3-126561.6" + wire width 50 $0\io_sr$next[49:0]$5498 + attribute \src "libresoc.v:126117.3-126118.27" + wire width 50 $0\io_sr[49:0] + attribute \src "libresoc.v:126225.3-126257.6" + wire width 29 $0\jtag_wb__adr$next[28:0]$5452 + attribute \src "libresoc.v:126073.3-126074.41" + wire width 29 $0\jtag_wb__adr[28:0] + attribute \src "libresoc.v:126311.3-126337.6" + wire width 64 $0\jtag_wb__dat_w$next[63:0]$5465 + attribute \src "libresoc.v:126069.3-126070.45" + wire width 64 $0\jtag_wb__dat_w[63:0] + attribute \src "libresoc.v:126673.3-126689.6" + wire $0\jtag_wb_addrsr__oe$next[0:0]$5528 + attribute \src "libresoc.v:126101.3-126102.53" + wire $0\jtag_wb_addrsr__oe[0:0] + attribute \src "libresoc.v:126690.3-126710.6" + wire width 29 $0\jtag_wb_addrsr_reg$next[28:0]$5532 + attribute \src "libresoc.v:126099.3-126100.53" + wire width 29 $0\jtag_wb_addrsr_reg[28:0] + attribute \src "libresoc.v:126655.3-126663.6" + wire $0\jtag_wb_addrsr_update_core$next[0:0]$5522 + attribute \src "libresoc.v:126105.3-126106.69" + wire $0\jtag_wb_addrsr_update_core[0:0] + attribute \src "libresoc.v:126664.3-126672.6" + wire $0\jtag_wb_addrsr_update_core_prev$next[0:0]$5525 + attribute \src "libresoc.v:126103.3-126104.79" + wire $0\jtag_wb_addrsr_update_core_prev[0:0] + attribute \src "libresoc.v:126338.3-126358.6" + wire width 64 $0\jtag_wb_datasr__i$next[63:0]$5470 + attribute \src "libresoc.v:126067.3-126068.51" + wire width 64 $0\jtag_wb_datasr__i[63:0] + attribute \src "libresoc.v:126729.3-126745.6" + wire width 2 $0\jtag_wb_datasr__oe$next[1:0]$5543 + attribute \src "libresoc.v:126093.3-126094.53" + wire width 2 $0\jtag_wb_datasr__oe[1:0] + attribute \src "libresoc.v:126746.3-126766.6" + wire width 64 $0\jtag_wb_datasr_reg$next[63:0]$5547 + attribute \src "libresoc.v:126091.3-126092.53" + wire width 64 $0\jtag_wb_datasr_reg[63:0] + attribute \src "libresoc.v:126711.3-126719.6" + wire $0\jtag_wb_datasr_update_core$next[0:0]$5537 + attribute \src "libresoc.v:126097.3-126098.69" + wire $0\jtag_wb_datasr_update_core[0:0] + attribute \src "libresoc.v:126720.3-126728.6" + wire $0\jtag_wb_datasr_update_core_prev$next[0:0]$5540 + attribute \src "libresoc.v:126095.3-126096.79" + wire $0\jtag_wb_datasr_update_core_prev[0:0] + attribute \src "libresoc.v:126617.3-126633.6" + wire $0\sr0__oe$next[0:0]$5513 + attribute \src "libresoc.v:126109.3-126110.31" + wire $0\sr0__oe[0:0] + attribute \src "libresoc.v:126634.3-126654.6" + wire width 3 $0\sr0_reg$next[2:0]$5517 + attribute \src "libresoc.v:126107.3-126108.31" + wire width 3 $0\sr0_reg[2:0] + attribute \src "libresoc.v:126599.3-126607.6" + wire $0\sr0_update_core$next[0:0]$5507 + attribute \src "libresoc.v:126113.3-126114.47" + wire $0\sr0_update_core[0:0] + attribute \src "libresoc.v:126608.3-126616.6" + wire $0\sr0_update_core_prev$next[0:0]$5510 + attribute \src "libresoc.v:126111.3-126112.57" + wire $0\sr0_update_core_prev[0:0] + attribute \src "libresoc.v:126201.3-126224.6" + wire $1\TAP_bus__tdo[0:0] + attribute \src "libresoc.v:126562.3-126577.6" + wire $1\TAP_tdo[0:0] + attribute \src "libresoc.v:126359.3-126391.6" + wire width 4 $1\dmi0_addr_i$next[3:0]$5476 + attribute \src "libresoc.v:125501.13-125501.31" + wire width 4 $1\dmi0_addr_i[3:0] + attribute \src "libresoc.v:126785.3-126801.6" + wire $1\dmi0_addrsr__oe$next[0:0]$5559 + attribute \src "libresoc.v:125509.7-125509.29" + wire $1\dmi0_addrsr__oe[0:0] + attribute \src "libresoc.v:126802.3-126822.6" + wire width 8 $1\dmi0_addrsr_reg$next[7:0]$5563 + attribute \src "libresoc.v:125517.13-125517.36" + wire width 8 $1\dmi0_addrsr_reg[7:0] + attribute \src "libresoc.v:126767.3-126775.6" + wire $1\dmi0_addrsr_update_core$next[0:0]$5553 + attribute \src "libresoc.v:125525.7-125525.37" + wire $1\dmi0_addrsr_update_core[0:0] + attribute \src "libresoc.v:126776.3-126784.6" + wire $1\dmi0_addrsr_update_core_prev$next[0:0]$5556 + attribute \src "libresoc.v:125529.7-125529.42" + wire $1\dmi0_addrsr_update_core_prev[0:0] + attribute \src "libresoc.v:126472.3-126492.6" + wire width 64 $1\dmi0_datasr__i$next[63:0]$5494 + attribute \src "libresoc.v:125533.14-125533.51" + wire width 64 $1\dmi0_datasr__i[63:0] + attribute \src "libresoc.v:126163.3-126179.6" + wire width 2 $1\dmi0_datasr__oe$next[1:0]$5443 + attribute \src "libresoc.v:125539.13-125539.35" + wire width 2 $1\dmi0_datasr__oe[1:0] + attribute \src "libresoc.v:126180.3-126200.6" + wire width 64 $1\dmi0_datasr_reg$next[63:0]$5447 + attribute \src "libresoc.v:125547.14-125547.52" + wire width 64 $1\dmi0_datasr_reg[63:0] + attribute \src "libresoc.v:126823.3-126831.6" + wire $1\dmi0_datasr_update_core$next[0:0]$5568 + attribute \src "libresoc.v:125555.7-125555.37" + wire $1\dmi0_datasr_update_core[0:0] + attribute \src "libresoc.v:126154.3-126162.6" + wire $1\dmi0_datasr_update_core_prev$next[0:0]$5440 + attribute \src "libresoc.v:125559.7-125559.42" + wire $1\dmi0_datasr_update_core_prev[0:0] + attribute \src "libresoc.v:126445.3-126471.6" + wire width 64 $1\dmi0_din$next[63:0]$5489 + attribute \src "libresoc.v:125564.14-125564.45" + wire width 64 $1\dmi0_din[63:0] + attribute \src "libresoc.v:126392.3-126444.6" + wire width 3 $1\fsm_state$275$next[2:0]$5482 + attribute \src "libresoc.v:126258.3-126310.6" + wire width 3 $1\fsm_state$next[2:0]$5459 + attribute \src "libresoc.v:125574.13-125574.29" + wire width 3 $1\fsm_state[2:0] + attribute \src "libresoc.v:126578.3-126598.6" + wire width 50 $1\io_bd$next[49:0]$5504 + attribute \src "libresoc.v:125774.14-125774.39" + wire width 50 $1\io_bd[49:0] + attribute \src "libresoc.v:126493.3-126561.6" + wire width 50 $1\io_sr$next[49:0]$5499 + attribute \src "libresoc.v:125786.14-125786.39" + wire width 50 $1\io_sr[49:0] + attribute \src "libresoc.v:126225.3-126257.6" + wire width 29 $1\jtag_wb__adr$next[28:0]$5453 + attribute \src "libresoc.v:125795.14-125795.41" + wire width 29 $1\jtag_wb__adr[28:0] + attribute \src "libresoc.v:126311.3-126337.6" + wire width 64 $1\jtag_wb__dat_w$next[63:0]$5466 + attribute \src "libresoc.v:125804.14-125804.51" + wire width 64 $1\jtag_wb__dat_w[63:0] + attribute \src "libresoc.v:126673.3-126689.6" + wire $1\jtag_wb_addrsr__oe$next[0:0]$5529 + attribute \src "libresoc.v:125818.7-125818.32" + wire $1\jtag_wb_addrsr__oe[0:0] + attribute \src "libresoc.v:126690.3-126710.6" + wire width 29 $1\jtag_wb_addrsr_reg$next[28:0]$5533 + attribute \src "libresoc.v:125826.14-125826.47" + wire width 29 $1\jtag_wb_addrsr_reg[28:0] + attribute \src "libresoc.v:126655.3-126663.6" + wire $1\jtag_wb_addrsr_update_core$next[0:0]$5523 + attribute \src "libresoc.v:125834.7-125834.40" + wire $1\jtag_wb_addrsr_update_core[0:0] + attribute \src "libresoc.v:126664.3-126672.6" + wire $1\jtag_wb_addrsr_update_core_prev$next[0:0]$5526 + attribute \src "libresoc.v:125838.7-125838.45" + wire $1\jtag_wb_addrsr_update_core_prev[0:0] + attribute \src "libresoc.v:126338.3-126358.6" + wire width 64 $1\jtag_wb_datasr__i$next[63:0]$5471 + attribute \src "libresoc.v:125842.14-125842.54" + wire width 64 $1\jtag_wb_datasr__i[63:0] + attribute \src "libresoc.v:126729.3-126745.6" + wire width 2 $1\jtag_wb_datasr__oe$next[1:0]$5544 + attribute \src "libresoc.v:125848.13-125848.38" + wire width 2 $1\jtag_wb_datasr__oe[1:0] + attribute \src "libresoc.v:126746.3-126766.6" + wire width 64 $1\jtag_wb_datasr_reg$next[63:0]$5548 + attribute \src "libresoc.v:125856.14-125856.55" + wire width 64 $1\jtag_wb_datasr_reg[63:0] + attribute \src "libresoc.v:126711.3-126719.6" + wire $1\jtag_wb_datasr_update_core$next[0:0]$5538 + attribute \src "libresoc.v:125864.7-125864.40" + wire $1\jtag_wb_datasr_update_core[0:0] + attribute \src "libresoc.v:126720.3-126728.6" + wire $1\jtag_wb_datasr_update_core_prev$next[0:0]$5541 + attribute \src "libresoc.v:125868.7-125868.45" + wire $1\jtag_wb_datasr_update_core_prev[0:0] + attribute \src "libresoc.v:126617.3-126633.6" + wire $1\sr0__oe$next[0:0]$5514 + attribute \src "libresoc.v:125886.7-125886.21" + wire $1\sr0__oe[0:0] + attribute \src "libresoc.v:126634.3-126654.6" + wire width 3 $1\sr0_reg$next[2:0]$5518 + attribute \src "libresoc.v:125894.13-125894.27" + wire width 3 $1\sr0_reg[2:0] + attribute \src "libresoc.v:126599.3-126607.6" + wire $1\sr0_update_core$next[0:0]$5508 + attribute \src "libresoc.v:125902.7-125902.29" + wire $1\sr0_update_core[0:0] + attribute \src "libresoc.v:126608.3-126616.6" + wire $1\sr0_update_core_prev$next[0:0]$5511 + attribute \src "libresoc.v:125906.7-125906.34" + wire $1\sr0_update_core_prev[0:0] + attribute \src "libresoc.v:126359.3-126391.6" + wire width 4 $2\dmi0_addr_i$next[3:0]$5477 + attribute \src "libresoc.v:126785.3-126801.6" + wire $2\dmi0_addrsr__oe$next[0:0]$5560 + attribute \src "libresoc.v:126802.3-126822.6" + wire width 8 $2\dmi0_addrsr_reg$next[7:0]$5564 + attribute \src "libresoc.v:126472.3-126492.6" + wire width 64 $2\dmi0_datasr__i$next[63:0]$5495 + attribute \src "libresoc.v:126163.3-126179.6" + wire width 2 $2\dmi0_datasr__oe$next[1:0]$5444 + attribute \src "libresoc.v:126180.3-126200.6" + wire width 64 $2\dmi0_datasr_reg$next[63:0]$5448 + attribute \src "libresoc.v:126445.3-126471.6" + wire width 64 $2\dmi0_din$next[63:0]$5490 + attribute \src "libresoc.v:126392.3-126444.6" + wire width 3 $2\fsm_state$275$next[2:0]$5483 + attribute \src "libresoc.v:126258.3-126310.6" + wire width 3 $2\fsm_state$next[2:0]$5460 + attribute \src "libresoc.v:126578.3-126598.6" + wire width 50 $2\io_bd$next[49:0]$5505 + attribute \src "libresoc.v:126493.3-126561.6" + wire width 50 $2\io_sr$next[49:0]$5500 + attribute \src "libresoc.v:126225.3-126257.6" + wire width 29 $2\jtag_wb__adr$next[28:0]$5454 + attribute \src "libresoc.v:126311.3-126337.6" + wire width 64 $2\jtag_wb__dat_w$next[63:0]$5467 + attribute \src "libresoc.v:126673.3-126689.6" + wire $2\jtag_wb_addrsr__oe$next[0:0]$5530 + attribute \src "libresoc.v:126690.3-126710.6" + wire width 29 $2\jtag_wb_addrsr_reg$next[28:0]$5534 + attribute \src "libresoc.v:126338.3-126358.6" + wire width 64 $2\jtag_wb_datasr__i$next[63:0]$5472 + attribute \src "libresoc.v:126729.3-126745.6" + wire width 2 $2\jtag_wb_datasr__oe$next[1:0]$5545 + attribute \src "libresoc.v:126746.3-126766.6" + wire width 64 $2\jtag_wb_datasr_reg$next[63:0]$5549 + attribute \src "libresoc.v:126617.3-126633.6" + wire $2\sr0__oe$next[0:0]$5515 + attribute \src "libresoc.v:126634.3-126654.6" + wire width 3 $2\sr0_reg$next[2:0]$5519 + attribute \src "libresoc.v:126359.3-126391.6" + wire width 4 $3\dmi0_addr_i$next[3:0]$5478 + attribute \src "libresoc.v:126802.3-126822.6" + wire width 8 $3\dmi0_addrsr_reg$next[7:0]$5565 + attribute \src "libresoc.v:126472.3-126492.6" + wire width 64 $3\dmi0_datasr__i$next[63:0]$5496 + attribute \src "libresoc.v:126180.3-126200.6" + wire width 64 $3\dmi0_datasr_reg$next[63:0]$5449 + attribute \src "libresoc.v:126445.3-126471.6" + wire width 64 $3\dmi0_din$next[63:0]$5491 + attribute \src "libresoc.v:126392.3-126444.6" + wire width 3 $3\fsm_state$275$next[2:0]$5484 + attribute \src "libresoc.v:126258.3-126310.6" + wire width 3 $3\fsm_state$next[2:0]$5461 + attribute \src "libresoc.v:126225.3-126257.6" + wire width 29 $3\jtag_wb__adr$next[28:0]$5455 + attribute \src "libresoc.v:126311.3-126337.6" + wire width 64 $3\jtag_wb__dat_w$next[63:0]$5468 + attribute \src "libresoc.v:126690.3-126710.6" + wire width 29 $3\jtag_wb_addrsr_reg$next[28:0]$5535 + attribute \src "libresoc.v:126338.3-126358.6" + wire width 64 $3\jtag_wb_datasr__i$next[63:0]$5473 + attribute \src "libresoc.v:126746.3-126766.6" + wire width 64 $3\jtag_wb_datasr_reg$next[63:0]$5550 + attribute \src "libresoc.v:126634.3-126654.6" + wire width 3 $3\sr0_reg$next[2:0]$5520 + attribute \src "libresoc.v:126359.3-126391.6" + wire width 4 $4\dmi0_addr_i$next[3:0]$5479 + attribute \src "libresoc.v:126392.3-126444.6" + wire width 3 $4\fsm_state$275$next[2:0]$5485 + attribute \src "libresoc.v:126258.3-126310.6" + wire width 3 $4\fsm_state$next[2:0]$5462 + attribute \src "libresoc.v:126225.3-126257.6" + wire width 29 $4\jtag_wb__adr$next[28:0]$5456 + attribute \src "libresoc.v:126392.3-126444.6" + wire width 3 $5\fsm_state$275$next[2:0]$5486 + attribute \src "libresoc.v:126258.3-126310.6" + wire width 3 $5\fsm_state$next[2:0]$5463 + attribute \src "libresoc.v:126011.19-126011.110" + wire width 30 $add$libresoc.v:126011$5358_Y + attribute \src "libresoc.v:126012.19-126012.110" + wire width 30 $add$libresoc.v:126012$5359_Y + attribute \src "libresoc.v:126019.19-126019.109" + wire width 5 $add$libresoc.v:126019$5367_Y + attribute \src "libresoc.v:126020.19-126020.109" + wire width 5 $add$libresoc.v:126020$5368_Y + attribute \src "libresoc.v:125944.19-125944.110" + wire $and$libresoc.v:125944$5291_Y + attribute \src "libresoc.v:125951.19-125951.110" + wire $and$libresoc.v:125951$5298_Y + attribute \src "libresoc.v:125954.19-125954.114" + wire $and$libresoc.v:125954$5301_Y + attribute \src "libresoc.v:125956.19-125956.112" + wire $and$libresoc.v:125956$5303_Y + attribute \src "libresoc.v:125958.19-125958.113" + wire $and$libresoc.v:125958$5305_Y + attribute \src "libresoc.v:125960.19-125960.121" + wire $and$libresoc.v:125960$5307_Y + attribute \src "libresoc.v:125964.19-125964.114" + wire $and$libresoc.v:125964$5311_Y + attribute \src "libresoc.v:125966.19-125966.112" + wire $and$libresoc.v:125966$5313_Y + attribute \src "libresoc.v:125968.19-125968.113" + wire $and$libresoc.v:125968$5315_Y + attribute \src "libresoc.v:125970.19-125970.132" + wire $and$libresoc.v:125970$5317_Y + attribute \src "libresoc.v:125973.18-125973.108" + wire $and$libresoc.v:125973$5320_Y + attribute \src "libresoc.v:125976.19-125976.114" + wire $and$libresoc.v:125976$5323_Y + attribute \src "libresoc.v:125978.19-125978.112" + wire $and$libresoc.v:125978$5325_Y + attribute \src "libresoc.v:125980.19-125980.113" + wire $and$libresoc.v:125980$5327_Y + attribute \src "libresoc.v:125982.19-125982.132" + wire $and$libresoc.v:125982$5329_Y + attribute \src "libresoc.v:125984.18-125984.110" + wire $and$libresoc.v:125984$5331_Y + attribute \src "libresoc.v:125986.19-125986.114" + wire $and$libresoc.v:125986$5333_Y + attribute \src "libresoc.v:125988.19-125988.112" + wire $and$libresoc.v:125988$5335_Y + attribute \src "libresoc.v:125990.19-125990.113" + wire $and$libresoc.v:125990$5337_Y + attribute \src "libresoc.v:125992.19-125992.129" + wire $and$libresoc.v:125992$5339_Y + attribute \src "libresoc.v:125997.19-125997.114" + wire $and$libresoc.v:125997$5344_Y + attribute \src "libresoc.v:125999.19-125999.112" + wire $and$libresoc.v:125999$5346_Y + attribute \src "libresoc.v:126001.19-126001.113" + wire $and$libresoc.v:126001$5348_Y + attribute \src "libresoc.v:126003.19-126003.129" + wire $and$libresoc.v:126003$5350_Y + attribute \src "libresoc.v:126023.18-126023.108" + wire $and$libresoc.v:126023$5371_Y + attribute \src "libresoc.v:126024.18-126024.111" + wire $and$libresoc.v:126024$5372_Y + attribute \src "libresoc.v:126048.17-126048.110" + wire $and$libresoc.v:126048$5396_Y + attribute \src "libresoc.v:125917.17-125917.110" + wire $eq$libresoc.v:125917$5264_Y + attribute \src "libresoc.v:125928.18-125928.111" + wire $eq$libresoc.v:125928$5275_Y + attribute \src "libresoc.v:125941.19-125941.112" + wire $eq$libresoc.v:125941$5288_Y + attribute \src "libresoc.v:125942.19-125942.112" + wire $eq$libresoc.v:125942$5289_Y + attribute \src "libresoc.v:125945.19-125945.112" + wire $eq$libresoc.v:125945$5292_Y + attribute \src "libresoc.v:125946.19-125946.112" + wire $eq$libresoc.v:125946$5293_Y + attribute \src "libresoc.v:125948.19-125948.112" + wire $eq$libresoc.v:125948$5295_Y + attribute \src "libresoc.v:125950.18-125950.111" + wire $eq$libresoc.v:125950$5297_Y + attribute \src "libresoc.v:125952.19-125952.112" + wire $eq$libresoc.v:125952$5299_Y + attribute \src "libresoc.v:125962.19-125962.112" + wire $eq$libresoc.v:125962$5309_Y + attribute \src "libresoc.v:125971.19-125971.112" + wire $eq$libresoc.v:125971$5318_Y + attribute \src "libresoc.v:125972.17-125972.110" + wire $eq$libresoc.v:125972$5319_Y + attribute \src "libresoc.v:125974.19-125974.112" + wire $eq$libresoc.v:125974$5321_Y + attribute \src "libresoc.v:125983.19-125983.112" + wire $eq$libresoc.v:125983$5330_Y + attribute \src "libresoc.v:125993.19-125993.112" + wire $eq$libresoc.v:125993$5340_Y + attribute \src "libresoc.v:125994.19-125994.112" + wire $eq$libresoc.v:125994$5341_Y + attribute \src "libresoc.v:125995.18-125995.111" + wire $eq$libresoc.v:125995$5342_Y + attribute \src "libresoc.v:126004.19-126004.108" + wire $eq$libresoc.v:126004$5351_Y + attribute \src "libresoc.v:126006.18-126006.111" + wire $eq$libresoc.v:126006$5353_Y + attribute \src "libresoc.v:126007.19-126007.108" + wire $eq$libresoc.v:126007$5354_Y + attribute \src "libresoc.v:126008.19-126008.108" + wire $eq$libresoc.v:126008$5355_Y + attribute \src "libresoc.v:126010.19-126010.108" + wire $eq$libresoc.v:126010$5357_Y + attribute \src "libresoc.v:126014.19-126014.114" + wire $eq$libresoc.v:126014$5362_Y + attribute \src "libresoc.v:126015.19-126015.114" + wire $eq$libresoc.v:126015$5363_Y + attribute \src "libresoc.v:126018.19-126018.114" + wire $eq$libresoc.v:126018$5366_Y + attribute \src "libresoc.v:126021.18-126021.111" + wire $eq$libresoc.v:126021$5369_Y + attribute \src "libresoc.v:126025.18-126025.111" + wire $eq$libresoc.v:126025$5373_Y + attribute \src "libresoc.v:126026.17-126026.110" + wire $eq$libresoc.v:126026$5374_Y + attribute \src "libresoc.v:126027.18-126027.111" + wire $eq$libresoc.v:126027$5375_Y + attribute \src "libresoc.v:126013.19-126013.98" + wire width 8 $extend$libresoc.v:126013$5360_Y + attribute \src "libresoc.v:125953.19-125953.109" + wire $ne$libresoc.v:125953$5300_Y + attribute \src "libresoc.v:125955.19-125955.109" + wire $ne$libresoc.v:125955$5302_Y + attribute \src "libresoc.v:125957.19-125957.109" + wire $ne$libresoc.v:125957$5304_Y + attribute \src "libresoc.v:125963.19-125963.120" + wire $ne$libresoc.v:125963$5310_Y + attribute \src "libresoc.v:125965.19-125965.120" + wire $ne$libresoc.v:125965$5312_Y + attribute \src "libresoc.v:125967.19-125967.120" + wire $ne$libresoc.v:125967$5314_Y + attribute \src "libresoc.v:125975.19-125975.120" + wire $ne$libresoc.v:125975$5322_Y + attribute \src "libresoc.v:125977.19-125977.120" + wire $ne$libresoc.v:125977$5324_Y + attribute \src "libresoc.v:125979.19-125979.120" + wire $ne$libresoc.v:125979$5326_Y + attribute \src "libresoc.v:125985.19-125985.117" + wire $ne$libresoc.v:125985$5332_Y + attribute \src "libresoc.v:125987.19-125987.117" + wire $ne$libresoc.v:125987$5334_Y + attribute \src "libresoc.v:125989.19-125989.117" + wire $ne$libresoc.v:125989$5336_Y + attribute \src "libresoc.v:125996.19-125996.117" + wire $ne$libresoc.v:125996$5343_Y + attribute \src "libresoc.v:125998.19-125998.117" + wire $ne$libresoc.v:125998$5345_Y + attribute \src "libresoc.v:126000.19-126000.117" + wire $ne$libresoc.v:126000$5347_Y + attribute \src "libresoc.v:125959.19-125959.110" + wire $not$libresoc.v:125959$5306_Y + attribute \src "libresoc.v:125969.19-125969.121" + wire $not$libresoc.v:125969$5316_Y + attribute \src "libresoc.v:125981.19-125981.121" + wire $not$libresoc.v:125981$5328_Y + attribute \src "libresoc.v:125991.19-125991.118" + wire $not$libresoc.v:125991$5338_Y + attribute \src "libresoc.v:126002.19-126002.118" + wire $not$libresoc.v:126002$5349_Y + attribute \src "libresoc.v:126005.19-126005.98" + wire $not$libresoc.v:126005$5352_Y + attribute \src "libresoc.v:125939.18-125939.103" + wire $or$libresoc.v:125939$5286_Y + attribute \src "libresoc.v:125943.19-125943.107" + wire $or$libresoc.v:125943$5290_Y + attribute \src "libresoc.v:125947.19-125947.107" + wire $or$libresoc.v:125947$5294_Y + attribute \src "libresoc.v:125949.19-125949.107" + wire $or$libresoc.v:125949$5296_Y + attribute \src "libresoc.v:125961.18-125961.104" + wire $or$libresoc.v:125961$5308_Y + attribute \src "libresoc.v:126009.19-126009.105" + wire $or$libresoc.v:126009$5356_Y + attribute \src "libresoc.v:126016.18-126016.104" + wire $or$libresoc.v:126016$5364_Y + attribute \src "libresoc.v:126017.19-126017.105" + wire $or$libresoc.v:126017$5365_Y + attribute \src "libresoc.v:126022.18-126022.104" + wire $or$libresoc.v:126022$5370_Y + attribute \src "libresoc.v:126037.17-126037.101" + wire $or$libresoc.v:126037$5385_Y + attribute \src "libresoc.v:126013.19-126013.98" + wire width 8 $pos$libresoc.v:126013$5361_Y + attribute \src "libresoc.v:125918.18-125918.135" + wire $ternary$libresoc.v:125918$5265_Y + attribute \src "libresoc.v:125919.19-125919.135" + wire $ternary$libresoc.v:125919$5266_Y + attribute \src "libresoc.v:125920.19-125920.136" + wire $ternary$libresoc.v:125920$5267_Y + attribute \src "libresoc.v:125921.19-125921.137" + wire $ternary$libresoc.v:125921$5268_Y + attribute \src "libresoc.v:125922.19-125922.136" + wire $ternary$libresoc.v:125922$5269_Y + attribute \src "libresoc.v:125923.19-125923.137" + wire $ternary$libresoc.v:125923$5270_Y + attribute \src "libresoc.v:125924.19-125924.137" + wire $ternary$libresoc.v:125924$5271_Y + attribute \src "libresoc.v:125925.19-125925.136" + wire $ternary$libresoc.v:125925$5272_Y + attribute \src "libresoc.v:125926.19-125926.137" + wire $ternary$libresoc.v:125926$5273_Y + attribute \src "libresoc.v:125927.19-125927.137" + wire $ternary$libresoc.v:125927$5274_Y + attribute \src "libresoc.v:125929.19-125929.136" + wire $ternary$libresoc.v:125929$5276_Y + attribute \src "libresoc.v:125930.19-125930.137" + wire $ternary$libresoc.v:125930$5277_Y + attribute \src "libresoc.v:125931.19-125931.137" + wire $ternary$libresoc.v:125931$5278_Y + attribute \src "libresoc.v:125932.19-125932.136" + wire $ternary$libresoc.v:125932$5279_Y + attribute \src "libresoc.v:125933.19-125933.137" + wire $ternary$libresoc.v:125933$5280_Y + attribute \src "libresoc.v:125934.19-125934.137" + wire $ternary$libresoc.v:125934$5281_Y + attribute \src "libresoc.v:125935.19-125935.136" + wire $ternary$libresoc.v:125935$5282_Y + attribute \src "libresoc.v:125936.19-125936.137" + wire $ternary$libresoc.v:125936$5283_Y + attribute \src "libresoc.v:125937.19-125937.137" + wire $ternary$libresoc.v:125937$5284_Y + attribute \src "libresoc.v:125938.19-125938.136" + wire $ternary$libresoc.v:125938$5285_Y + attribute \src "libresoc.v:125940.19-125940.137" + wire $ternary$libresoc.v:125940$5287_Y + attribute \src "libresoc.v:126028.18-126028.130" + wire $ternary$libresoc.v:126028$5376_Y + attribute \src "libresoc.v:126029.18-126029.131" + wire $ternary$libresoc.v:126029$5377_Y + attribute \src "libresoc.v:126030.18-126030.134" + wire $ternary$libresoc.v:126030$5378_Y + attribute \src "libresoc.v:126031.18-126031.133" + wire $ternary$libresoc.v:126031$5379_Y + attribute \src "libresoc.v:126032.18-126032.134" + wire $ternary$libresoc.v:126032$5380_Y + attribute \src "libresoc.v:126033.18-126033.134" + wire $ternary$libresoc.v:126033$5381_Y + attribute \src "libresoc.v:126034.18-126034.133" + wire $ternary$libresoc.v:126034$5382_Y + attribute \src "libresoc.v:126035.18-126035.134" + wire $ternary$libresoc.v:126035$5383_Y + attribute \src "libresoc.v:126036.18-126036.134" + wire $ternary$libresoc.v:126036$5384_Y + attribute \src "libresoc.v:126038.18-126038.133" + wire $ternary$libresoc.v:126038$5386_Y + attribute \src "libresoc.v:126039.18-126039.135" + wire $ternary$libresoc.v:126039$5387_Y + attribute \src "libresoc.v:126040.18-126040.135" + wire $ternary$libresoc.v:126040$5388_Y + attribute \src "libresoc.v:126041.18-126041.134" + wire $ternary$libresoc.v:126041$5389_Y + attribute \src "libresoc.v:126042.18-126042.135" + wire $ternary$libresoc.v:126042$5390_Y + attribute \src "libresoc.v:126043.18-126043.135" + wire $ternary$libresoc.v:126043$5391_Y + attribute \src "libresoc.v:126044.18-126044.134" + wire $ternary$libresoc.v:126044$5392_Y + attribute \src "libresoc.v:126045.18-126045.135" + wire $ternary$libresoc.v:126045$5393_Y + attribute \src "libresoc.v:126046.18-126046.135" + wire $ternary$libresoc.v:126046$5394_Y + attribute \src "libresoc.v:126047.18-126047.134" + wire $ternary$libresoc.v:126047$5395_Y + attribute \src "libresoc.v:126049.18-126049.135" + wire $ternary$libresoc.v:126049$5397_Y + attribute \src "libresoc.v:126050.18-126050.135" + wire $ternary$libresoc.v:126050$5398_Y + attribute \src "libresoc.v:126051.18-126051.134" + wire $ternary$libresoc.v:126051$5399_Y + attribute \src "libresoc.v:126052.18-126052.135" + wire $ternary$libresoc.v:126052$5400_Y + attribute \src "libresoc.v:126053.18-126053.135" + wire $ternary$libresoc.v:126053$5401_Y + attribute \src "libresoc.v:126054.18-126054.134" + wire $ternary$libresoc.v:126054$5402_Y + attribute \src "libresoc.v:126055.18-126055.135" + wire $ternary$libresoc.v:126055$5403_Y + attribute \src "libresoc.v:126056.18-126056.135" + wire $ternary$libresoc.v:126056$5404_Y + attribute \src "libresoc.v:126057.18-126057.134" + wire $ternary$libresoc.v:126057$5405_Y + attribute \src "libresoc.v:126058.18-126058.135" + wire $ternary$libresoc.v:126058$5406_Y + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" + wire \$101 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" + wire \$103 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + wire \$105 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" + wire \$107 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" + wire \$109 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + wire \$111 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" + wire \$113 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" + wire \$115 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + wire \$117 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" + wire \$119 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" + wire \$121 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + wire \$123 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" + wire \$125 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" + wire \$127 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + wire \$129 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" + wire \$131 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" + wire \$133 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + wire \$135 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" + wire \$137 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" + wire \$139 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" + wire \$141 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" + wire \$143 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" + wire \$145 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" + wire \$147 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" + wire \$149 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:379" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" + wire \$151 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" + wire \$153 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:379" + wire \$155 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:380" + wire \$157 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:380" + wire \$159 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:538" + wire \$161 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:539" + wire \$163 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:539" + wire \$165 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:540" + wire \$167 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:540" + wire \$169 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:380" + wire \$17 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:541" + wire \$171 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:541" + wire \$173 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:553" + wire \$175 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:553" + wire \$177 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:538" + wire \$179 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:539" + wire \$181 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:539" + wire \$183 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:540" + wire \$185 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:540" + wire \$187 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:541" + wire \$189 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:380" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:541" + wire \$191 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:553" + wire \$193 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:553" + wire \$195 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:538" + wire \$197 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:538" + wire \$199 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:539" + wire \$201 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:539" + wire \$203 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:540" + wire \$205 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:540" + wire \$207 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:541" + wire \$209 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:383" + wire \$21 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:541" + wire \$211 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:553" + wire \$213 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:553" + wire \$215 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:538" + wire \$217 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:539" + wire \$219 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:539" + wire \$221 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:540" + wire \$223 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:540" + wire \$225 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:541" + wire \$227 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:541" + wire \$229 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:553" + wire \$231 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:553" + wire \$233 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:538" + wire \$235 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:538" + wire \$237 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:539" + wire \$239 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:539" + wire \$241 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:540" + wire \$243 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:540" + wire \$245 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:541" + wire \$247 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:541" + wire \$249 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" + wire \$25 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:553" + wire \$251 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:553" + wire \$253 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:229" + wire \$255 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:229" + wire \$256 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:230" + wire \$259 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:230" + wire \$261 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:230" + wire \$263 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:231" + wire \$265 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:201" + wire width 30 \$267 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:201" + wire width 30 \$268 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:225" + wire width 30 \$270 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:225" + wire width 30 \$271 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:57" + wire width 8 \$273 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:182" + wire \$276 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:182" + wire \$278 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:182" + wire \$280 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:183" + wire \$282 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:153" + wire width 5 \$284 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:153" + wire width 5 \$285 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:177" + wire width 5 \$287 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:177" + wire width 5 \$288 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:379" + wire \$29 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:380" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:380" + wire \$33 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:384" + wire \$35 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:385" + wire \$37 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:386" + wire \$39 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:475" + wire \$41 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:472" + wire \$43 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + wire \$45 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" + wire \$47 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" + wire \$49 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + wire \$51 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" + wire \$53 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" + wire \$55 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + wire \$57 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" + wire \$59 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" + wire \$61 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + wire \$63 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" + wire \$65 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" + wire \$67 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + wire \$69 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:382" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" + wire \$71 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" + wire \$73 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + wire \$75 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" + wire \$77 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" + wire \$79 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + wire \$81 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" + wire \$83 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" + wire \$85 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + wire \$87 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" + wire \$89 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" + wire \$91 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + wire \$93 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" + wire \$95 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" + wire \$97 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + wire \$99 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:39" + wire input 118 \TAP_bus__tck + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:39" + wire input 58 \TAP_bus__tdi + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:39" + wire output 109 \TAP_bus__tdo + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:39" + wire input 119 \TAP_bus__tms + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:394" + wire \TAP_tdo + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:25" + wire \_fsm_capture + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:24" + wire \_fsm_isdr + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:23" + wire \_fsm_isir + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:26" + wire \_fsm_shift + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:27" + wire \_fsm_update + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:215" + wire \_idblock_TAP_id_tdo + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:128" + wire width 4 \_irblock_ir + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:129" + wire \_irblock_tdo + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:151" + wire input 6 \clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:62" + wire input 4 \dmi0_ack_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:57" + wire width 4 output 120 \dmi0_addr_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:57" + wire width 4 \dmi0_addr_i$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:130" + wire width 8 \dmi0_addrsr__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:130" + wire width 8 \dmi0_addrsr__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:130" + wire \dmi0_addrsr__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:130" + wire \dmi0_addrsr__oe$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:534" + wire \dmi0_addrsr_capture + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:533" + wire \dmi0_addrsr_isir + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:530" + wire width 8 \dmi0_addrsr_reg + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:530" + wire width 8 \dmi0_addrsr_reg$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:535" + wire \dmi0_addrsr_shift + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:536" + wire \dmi0_addrsr_update + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:547" + wire \dmi0_addrsr_update_core + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:547" + wire \dmi0_addrsr_update_core$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:548" + wire \dmi0_addrsr_update_core_prev + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:548" + wire \dmi0_addrsr_update_core_prev$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:132" + wire width 64 \dmi0_datasr__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:132" + wire width 64 \dmi0_datasr__i$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:132" + wire width 64 \dmi0_datasr__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:132" + wire width 2 \dmi0_datasr__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:132" + wire width 2 \dmi0_datasr__oe$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:534" + wire \dmi0_datasr_capture + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:533" + wire width 2 \dmi0_datasr_isir + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:530" + wire width 64 \dmi0_datasr_reg + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:530" + wire width 64 \dmi0_datasr_reg$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:535" + wire \dmi0_datasr_shift + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:536" + wire \dmi0_datasr_update + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:547" + wire \dmi0_datasr_update_core + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:547" + wire \dmi0_datasr_update_core$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:548" + wire \dmi0_datasr_update_core_prev + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:548" + wire \dmi0_datasr_update_core_prev$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:58" + wire width 64 output 3 \dmi0_din + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:58" + wire width 64 \dmi0_din$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:59" + wire width 64 input 5 \dmi0_dout + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:60" + wire output 1 \dmi0_req_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:61" + wire output 2 \dmi0_we_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:194" + wire width 3 \fsm_state + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:144" + wire width 3 \fsm_state$275 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:144" + wire width 3 \fsm_state$275$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:194" + wire width 3 \fsm_state$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 61 \gpio_gpio0__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 11 \gpio_gpio0__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 12 \gpio_gpio0__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 10 \gpio_gpio0__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 62 \gpio_gpio0__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 63 \gpio_gpio0__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 91 \gpio_gpio10__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 41 \gpio_gpio10__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 42 \gpio_gpio10__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 40 \gpio_gpio10__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 92 \gpio_gpio10__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 93 \gpio_gpio10__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 94 \gpio_gpio11__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 44 \gpio_gpio11__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 45 \gpio_gpio11__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 43 \gpio_gpio11__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 95 \gpio_gpio11__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 96 \gpio_gpio11__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 97 \gpio_gpio12__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 47 \gpio_gpio12__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 48 \gpio_gpio12__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 46 \gpio_gpio12__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 98 \gpio_gpio12__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 99 \gpio_gpio12__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 100 \gpio_gpio13__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 50 \gpio_gpio13__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 51 \gpio_gpio13__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 49 \gpio_gpio13__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 101 \gpio_gpio13__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 102 \gpio_gpio13__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 103 \gpio_gpio14__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 53 \gpio_gpio14__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 54 \gpio_gpio14__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 52 \gpio_gpio14__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 104 \gpio_gpio14__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 105 \gpio_gpio14__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 106 \gpio_gpio15__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 56 \gpio_gpio15__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 57 \gpio_gpio15__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 55 \gpio_gpio15__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 107 \gpio_gpio15__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 108 \gpio_gpio15__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 64 \gpio_gpio1__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 14 \gpio_gpio1__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 15 \gpio_gpio1__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 13 \gpio_gpio1__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 65 \gpio_gpio1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 66 \gpio_gpio1__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 67 \gpio_gpio2__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 17 \gpio_gpio2__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 18 \gpio_gpio2__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 16 \gpio_gpio2__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 68 \gpio_gpio2__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 69 \gpio_gpio2__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 70 \gpio_gpio3__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 20 \gpio_gpio3__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 21 \gpio_gpio3__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 19 \gpio_gpio3__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 71 \gpio_gpio3__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 72 \gpio_gpio3__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 73 \gpio_gpio4__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 23 \gpio_gpio4__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 24 \gpio_gpio4__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 22 \gpio_gpio4__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 74 \gpio_gpio4__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 75 \gpio_gpio4__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 76 \gpio_gpio5__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 26 \gpio_gpio5__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 27 \gpio_gpio5__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 25 \gpio_gpio5__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 77 \gpio_gpio5__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 78 \gpio_gpio5__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 79 \gpio_gpio6__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 29 \gpio_gpio6__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 30 \gpio_gpio6__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 28 \gpio_gpio6__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 80 \gpio_gpio6__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 81 \gpio_gpio6__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 82 \gpio_gpio7__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 32 \gpio_gpio7__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 33 \gpio_gpio7__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 31 \gpio_gpio7__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 83 \gpio_gpio7__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 84 \gpio_gpio7__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 85 \gpio_gpio8__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 35 \gpio_gpio8__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 36 \gpio_gpio8__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 34 \gpio_gpio8__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 86 \gpio_gpio8__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 87 \gpio_gpio8__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 88 \gpio_gpio9__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 38 \gpio_gpio9__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 39 \gpio_gpio9__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 37 \gpio_gpio9__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 89 \gpio_gpio9__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 90 \gpio_gpio9__pad__oe + attribute \src "libresoc.v:125175.7-125175.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:437" + wire width 50 \io_bd + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:437" + wire width 50 \io_bd$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" + wire \io_bd2core + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:376" + wire \io_bd2io + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:373" + wire \io_capture + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:374" + wire \io_shift + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:436" + wire width 50 \io_sr + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:436" + wire width 50 \io_sr$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:375" + wire \io_update + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:89" + wire input 116 \jtag_wb__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:89" + wire width 29 output 110 \jtag_wb__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:89" + wire width 29 \jtag_wb__adr$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:89" + wire output 112 \jtag_wb__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:89" + wire width 64 input 117 \jtag_wb__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:89" + wire width 64 output 115 \jtag_wb__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:89" + wire width 64 \jtag_wb__dat_w$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:89" + wire output 111 \jtag_wb__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:89" + wire output 113 \jtag_wb__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:89" + wire output 114 \jtag_wb__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:78" + wire width 29 \jtag_wb_addrsr__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:78" + wire width 29 \jtag_wb_addrsr__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:78" + wire \jtag_wb_addrsr__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:78" + wire \jtag_wb_addrsr__oe$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:534" + wire \jtag_wb_addrsr_capture + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:533" + wire \jtag_wb_addrsr_isir + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:530" + wire width 29 \jtag_wb_addrsr_reg + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:530" + wire width 29 \jtag_wb_addrsr_reg$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:535" + wire \jtag_wb_addrsr_shift + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:536" + wire \jtag_wb_addrsr_update + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:547" + wire \jtag_wb_addrsr_update_core + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:547" + wire \jtag_wb_addrsr_update_core$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:548" + wire \jtag_wb_addrsr_update_core_prev + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:548" + wire \jtag_wb_addrsr_update_core_prev$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:82" + wire width 64 \jtag_wb_datasr__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:82" + wire width 64 \jtag_wb_datasr__i$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:82" + wire width 64 \jtag_wb_datasr__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:82" + wire width 2 \jtag_wb_datasr__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:82" + wire width 2 \jtag_wb_datasr__oe$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:534" + wire \jtag_wb_datasr_capture + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:533" + wire width 2 \jtag_wb_datasr_isir + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:530" + wire width 64 \jtag_wb_datasr_reg + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:530" + wire width 64 \jtag_wb_datasr_reg$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:535" + wire \jtag_wb_datasr_shift + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:536" + wire \jtag_wb_datasr_update + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:547" + wire \jtag_wb_datasr_update_core + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:547" + wire \jtag_wb_datasr_update_core$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:548" + wire \jtag_wb_datasr_update_core_prev + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:548" + wire \jtag_wb_datasr_update_core_prev$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:30" + wire \negjtag_clk + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:30" + wire \negjtag_rst + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:29" + wire \posjtag_clk + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:29" + wire \posjtag_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:151" + wire input 7 \rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:52" + wire width 3 \sr0__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:52" + wire width 3 \sr0__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:52" + wire \sr0__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:52" + wire \sr0__oe$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:534" + wire \sr0_capture + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:533" + wire \sr0_isir + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:530" + wire width 3 \sr0_reg + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:530" + wire width 3 \sr0_reg$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:535" + wire \sr0_shift + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:536" + wire \sr0_update + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:547" + wire \sr0_update_core + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:547" + wire \sr0_update_core$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:548" + wire \sr0_update_core_prev + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:548" + wire \sr0_update_core_prev$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 60 \uart_rx__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 9 \uart_rx__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 8 \uart_tx__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 59 \uart_tx__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:201" + cell $add $add$libresoc.v:126011$5358 + parameter \A_SIGNED 0 + parameter \A_WIDTH 29 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 30 + connect \A \jtag_wb__adr + connect \B 1'1 + connect \Y $add$libresoc.v:126011$5358_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:225" + cell $add $add$libresoc.v:126012$5359 + parameter \A_SIGNED 0 + parameter \A_WIDTH 29 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 30 + connect \A \jtag_wb__adr + connect \B 1'1 + connect \Y $add$libresoc.v:126012$5359_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:153" + cell $add $add$libresoc.v:126019$5367 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 5 + connect \A \dmi0_addr_i + connect \B 1'1 + connect \Y $add$libresoc.v:126019$5367_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:177" + cell $add $add$libresoc.v:126020$5368 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 5 + connect \A \dmi0_addr_i + connect \B 1'1 + connect \Y $add$libresoc.v:126020$5368_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" + cell $and $and$libresoc.v:125944$5291 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \_fsm_isdr + connect \B \$145 + connect \Y $and$libresoc.v:125944$5291_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:380" + cell $and $and$libresoc.v:125951$5298 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \_fsm_isdr + connect \B \$157 + connect \Y $and$libresoc.v:125951$5298_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:539" + cell $and $and$libresoc.v:125954$5301 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$163 + connect \B \_fsm_capture + connect \Y $and$libresoc.v:125954$5301_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:540" + cell $and $and$libresoc.v:125956$5303 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$167 + connect \B \_fsm_shift + connect \Y $and$libresoc.v:125956$5303_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:541" + cell $and $and$libresoc.v:125958$5305 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$171 + connect \B \_fsm_update + connect \Y $and$libresoc.v:125958$5305_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:553" + cell $and $and$libresoc.v:125960$5307 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \sr0_update_core_prev + connect \B \$175 + connect \Y $and$libresoc.v:125960$5307_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:539" + cell $and $and$libresoc.v:125964$5311 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$181 + connect \B \_fsm_capture + connect \Y $and$libresoc.v:125964$5311_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:540" + cell $and $and$libresoc.v:125966$5313 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$185 + connect \B \_fsm_shift + connect \Y $and$libresoc.v:125966$5313_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:541" + cell $and $and$libresoc.v:125968$5315 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$189 + connect \B \_fsm_update + connect \Y $and$libresoc.v:125968$5315_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:553" + cell $and $and$libresoc.v:125970$5317 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \jtag_wb_addrsr_update_core_prev + connect \B \$193 + connect \Y $and$libresoc.v:125970$5317_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:380" + cell $and $and$libresoc.v:125973$5320 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \_fsm_isdr + connect \B \$17 + connect \Y $and$libresoc.v:125973$5320_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:539" + cell $and $and$libresoc.v:125976$5323 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$201 + connect \B \_fsm_capture + connect \Y $and$libresoc.v:125976$5323_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:540" + cell $and $and$libresoc.v:125978$5325 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$205 + connect \B \_fsm_shift + connect \Y $and$libresoc.v:125978$5325_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:541" + cell $and $and$libresoc.v:125980$5327 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$209 + connect \B \_fsm_update + connect \Y $and$libresoc.v:125980$5327_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:553" + cell $and $and$libresoc.v:125982$5329 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \jtag_wb_datasr_update_core_prev + connect \B \$213 + connect \Y $and$libresoc.v:125982$5329_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:383" + cell $and $and$libresoc.v:125984$5331 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$19 + connect \B \_fsm_shift + connect \Y $and$libresoc.v:125984$5331_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:539" + cell $and $and$libresoc.v:125986$5333 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$219 + connect \B \_fsm_capture + connect \Y $and$libresoc.v:125986$5333_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:540" + cell $and $and$libresoc.v:125988$5335 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$223 + connect \B \_fsm_shift + connect \Y $and$libresoc.v:125988$5335_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:541" + cell $and $and$libresoc.v:125990$5337 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$227 + connect \B \_fsm_update + connect \Y $and$libresoc.v:125990$5337_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:553" + cell $and $and$libresoc.v:125992$5339 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi0_addrsr_update_core_prev + connect \B \$231 + connect \Y $and$libresoc.v:125992$5339_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:539" + cell $and $and$libresoc.v:125997$5344 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$239 + connect \B \_fsm_capture + connect \Y $and$libresoc.v:125997$5344_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:540" + cell $and $and$libresoc.v:125999$5346 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$243 + connect \B \_fsm_shift + connect \Y $and$libresoc.v:125999$5346_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:541" + cell $and $and$libresoc.v:126001$5348 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$247 + connect \B \_fsm_update + connect \Y $and$libresoc.v:126001$5348_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:553" + cell $and $and$libresoc.v:126003$5350 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi0_datasr_update_core_prev + connect \B \$251 + connect \Y $and$libresoc.v:126003$5350_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:380" + cell $and $and$libresoc.v:126023$5371 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \_fsm_isdr + connect \B \$31 + connect \Y $and$libresoc.v:126023$5371_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:384" + cell $and $and$libresoc.v:126024$5372 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$33 + connect \B \_fsm_update + connect \Y $and$libresoc.v:126024$5372_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:382" + cell $and $and$libresoc.v:126048$5396 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$5 + connect \B \_fsm_capture + connect \Y $and$libresoc.v:126048$5396_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" + cell $eq $eq$libresoc.v:125917$5264 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \_irblock_ir + connect \B 1'0 + connect \Y $eq$libresoc.v:125917$5264_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" + cell $eq $eq$libresoc.v:125928$5275 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \_irblock_ir + connect \B 2'10 + connect \Y $eq$libresoc.v:125928$5275_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" + cell $eq $eq$libresoc.v:125941$5288 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \_irblock_ir + connect \B 1'1 + connect \Y $eq$libresoc.v:125941$5288_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" + cell $eq $eq$libresoc.v:125942$5289 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \_irblock_ir + connect \B 4'1111 + connect \Y $eq$libresoc.v:125942$5289_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" + cell $eq $eq$libresoc.v:125945$5292 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \_irblock_ir + connect \B 1'0 + connect \Y $eq$libresoc.v:125945$5292_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" + cell $eq $eq$libresoc.v:125946$5293 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \_irblock_ir + connect \B 2'10 + connect \Y $eq$libresoc.v:125946$5293_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:379" + cell $eq $eq$libresoc.v:125948$5295 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \_irblock_ir + connect \B 2'10 + connect \Y $eq$libresoc.v:125948$5295_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:379" + cell $eq $eq$libresoc.v:125950$5297 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \_irblock_ir + connect \B 2'10 + connect \Y $eq$libresoc.v:125950$5297_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:538" + cell $eq $eq$libresoc.v:125952$5299 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \_irblock_ir + connect \B 3'100 + connect \Y $eq$libresoc.v:125952$5299_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:538" + cell $eq $eq$libresoc.v:125962$5309 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \_irblock_ir + connect \B 3'101 + connect \Y $eq$libresoc.v:125962$5309_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:538" + cell $eq $eq$libresoc.v:125971$5318 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \_irblock_ir + connect \B 3'110 + connect \Y $eq$libresoc.v:125971$5318_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" + cell $eq $eq$libresoc.v:125972$5319 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \_irblock_ir + connect \B 1'0 + connect \Y $eq$libresoc.v:125972$5319_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:538" + cell $eq $eq$libresoc.v:125974$5321 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \_irblock_ir + connect \B 3'111 + connect \Y $eq$libresoc.v:125974$5321_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:538" + cell $eq $eq$libresoc.v:125983$5330 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \_irblock_ir + connect \B 4'1000 + connect \Y $eq$libresoc.v:125983$5330_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:538" + cell $eq $eq$libresoc.v:125993$5340 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \_irblock_ir + connect \B 4'1001 + connect \Y $eq$libresoc.v:125993$5340_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:538" + cell $eq $eq$libresoc.v:125994$5341 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \_irblock_ir + connect \B 4'1010 + connect \Y $eq$libresoc.v:125994$5341_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" + cell $eq $eq$libresoc.v:125995$5342 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \_irblock_ir + connect \B 1'0 + connect \Y $eq$libresoc.v:125995$5342_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:229" + cell $eq $eq$libresoc.v:126004$5351 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fsm_state + connect \B 1'0 + connect \Y $eq$libresoc.v:126004$5351_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" + cell $eq $eq$libresoc.v:126006$5353 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \_irblock_ir + connect \B 2'10 + connect \Y $eq$libresoc.v:126006$5353_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:230" + cell $eq $eq$libresoc.v:126007$5354 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fsm_state + connect \B 1'1 + connect \Y $eq$libresoc.v:126007$5354_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:230" + cell $eq $eq$libresoc.v:126008$5355 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \fsm_state + connect \B 2'10 + connect \Y $eq$libresoc.v:126008$5355_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:231" + cell $eq $eq$libresoc.v:126010$5357 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \fsm_state + connect \B 2'10 + connect \Y $eq$libresoc.v:126010$5357_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:182" + cell $eq $eq$libresoc.v:126014$5362 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fsm_state$275 + connect \B 1'1 + connect \Y $eq$libresoc.v:126014$5362_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:182" + cell $eq $eq$libresoc.v:126015$5363 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \fsm_state$275 + connect \B 2'10 + connect \Y $eq$libresoc.v:126015$5363_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:183" + cell $eq $eq$libresoc.v:126018$5366 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \fsm_state$275 + connect \B 2'10 + connect \Y $eq$libresoc.v:126018$5366_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:379" + cell $eq $eq$libresoc.v:126021$5369 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \_irblock_ir + connect \B 2'10 + connect \Y $eq$libresoc.v:126021$5369_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:385" + cell $eq $eq$libresoc.v:126025$5373 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \_irblock_ir + connect \B 1'0 + connect \Y $eq$libresoc.v:126025$5373_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" + cell $eq $eq$libresoc.v:126026$5374 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \_irblock_ir + connect \B 2'10 + connect \Y $eq$libresoc.v:126026$5374_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:386" + cell $eq $eq$libresoc.v:126027$5375 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \_irblock_ir + connect \B 1'0 + connect \Y $eq$libresoc.v:126027$5375_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:57" + cell $pos $extend$libresoc.v:126013$5360 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 8 + connect \A \dmi0_addr_i + connect \Y $extend$libresoc.v:126013$5360_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:539" + cell $ne $ne$libresoc.v:125953$5300 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \sr0_isir + connect \B 1'0 + connect \Y $ne$libresoc.v:125953$5300_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:540" + cell $ne $ne$libresoc.v:125955$5302 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \sr0_isir + connect \B 1'0 + connect \Y $ne$libresoc.v:125955$5302_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:541" + cell $ne $ne$libresoc.v:125957$5304 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \sr0_isir + connect \B 1'0 + connect \Y $ne$libresoc.v:125957$5304_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:539" + cell $ne $ne$libresoc.v:125963$5310 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \jtag_wb_addrsr_isir + connect \B 1'0 + connect \Y $ne$libresoc.v:125963$5310_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:540" + cell $ne $ne$libresoc.v:125965$5312 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \jtag_wb_addrsr_isir + connect \B 1'0 + connect \Y $ne$libresoc.v:125965$5312_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:541" + cell $ne $ne$libresoc.v:125967$5314 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \jtag_wb_addrsr_isir + connect \B 1'0 + connect \Y $ne$libresoc.v:125967$5314_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:539" + cell $ne $ne$libresoc.v:125975$5322 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \jtag_wb_datasr_isir + connect \B 1'0 + connect \Y $ne$libresoc.v:125975$5322_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:540" + cell $ne $ne$libresoc.v:125977$5324 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \jtag_wb_datasr_isir + connect \B 1'0 + connect \Y $ne$libresoc.v:125977$5324_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:541" + cell $ne $ne$libresoc.v:125979$5326 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \jtag_wb_datasr_isir + connect \B 1'0 + connect \Y $ne$libresoc.v:125979$5326_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:539" + cell $ne $ne$libresoc.v:125985$5332 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi0_addrsr_isir + connect \B 1'0 + connect \Y $ne$libresoc.v:125985$5332_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:540" + cell $ne $ne$libresoc.v:125987$5334 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi0_addrsr_isir + connect \B 1'0 + connect \Y $ne$libresoc.v:125987$5334_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:541" + cell $ne $ne$libresoc.v:125989$5336 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi0_addrsr_isir + connect \B 1'0 + connect \Y $ne$libresoc.v:125989$5336_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:539" + cell $ne $ne$libresoc.v:125996$5343 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi0_datasr_isir + connect \B 1'0 + connect \Y $ne$libresoc.v:125996$5343_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:540" + cell $ne $ne$libresoc.v:125998$5345 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi0_datasr_isir + connect \B 1'0 + connect \Y $ne$libresoc.v:125998$5345_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:541" + cell $ne $ne$libresoc.v:126000$5347 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi0_datasr_isir + connect \B 1'0 + connect \Y $ne$libresoc.v:126000$5347_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:553" + cell $not $not$libresoc.v:125959$5306 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \sr0_update_core + connect \Y $not$libresoc.v:125959$5306_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:553" + cell $not $not$libresoc.v:125969$5316 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \jtag_wb_addrsr_update_core + connect \Y $not$libresoc.v:125969$5316_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:553" + cell $not $not$libresoc.v:125981$5328 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \jtag_wb_datasr_update_core + connect \Y $not$libresoc.v:125981$5328_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:553" + cell $not $not$libresoc.v:125991$5338 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi0_addrsr_update_core + connect \Y $not$libresoc.v:125991$5338_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:553" + cell $not $not$libresoc.v:126002$5349 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi0_datasr_update_core + connect \Y $not$libresoc.v:126002$5349_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:229" + cell $not $not$libresoc.v:126005$5352 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$256 + connect \Y $not$libresoc.v:126005$5352_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" + cell $or $or$libresoc.v:125939$5286 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \$11 + connect \Y $or$libresoc.v:125939$5286_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" + cell $or $or$libresoc.v:125943$5290 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$141 + connect \B \$143 + connect \Y $or$libresoc.v:125943$5290_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" + cell $or $or$libresoc.v:125947$5294 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$149 + connect \B \$151 + connect \Y $or$libresoc.v:125947$5294_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:380" + cell $or $or$libresoc.v:125949$5296 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$153 + connect \B \$155 + connect \Y $or$libresoc.v:125949$5296_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:380" + cell $or $or$libresoc.v:125961$5308 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$13 + connect \B \$15 + connect \Y $or$libresoc.v:125961$5308_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:230" + cell $or $or$libresoc.v:126009$5356 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$259 + connect \B \$261 + connect \Y $or$libresoc.v:126009$5356_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" + cell $or $or$libresoc.v:126016$5364 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$23 + connect \B \$25 + connect \Y $or$libresoc.v:126016$5364_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:182" + cell $or $or$libresoc.v:126017$5365 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$276 + connect \B \$278 + connect \Y $or$libresoc.v:126017$5365_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:380" + cell $or $or$libresoc.v:126022$5370 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$27 + connect \B \$29 + connect \Y $or$libresoc.v:126022$5370_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" + cell $or $or$libresoc.v:126037$5385 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$1 + connect \B \$3 + connect \Y $or$libresoc.v:126037$5385_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:57" + cell $pos $pos$libresoc.v:126013$5361 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $extend$libresoc.v:126013$5360_Y + connect \Y $pos$libresoc.v:126013$5361_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + cell $mux $ternary$libresoc.v:125918$5265 + parameter \WIDTH 1 + connect \A \gpio_gpio9__pad__i + connect \B \io_bd [29] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:125918$5265_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" + cell $mux $ternary$libresoc.v:125919$5266 + parameter \WIDTH 1 + connect \A \gpio_gpio9__core__o + connect \B \io_bd [30] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:125919$5266_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" + cell $mux $ternary$libresoc.v:125920$5267 + parameter \WIDTH 1 + connect \A \gpio_gpio9__core__oe + connect \B \io_bd [31] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:125920$5267_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + cell $mux $ternary$libresoc.v:125921$5268 + parameter \WIDTH 1 + connect \A \gpio_gpio10__pad__i + connect \B \io_bd [32] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:125921$5268_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" + cell $mux $ternary$libresoc.v:125922$5269 + parameter \WIDTH 1 + connect \A \gpio_gpio10__core__o + connect \B \io_bd [33] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:125922$5269_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" + cell $mux $ternary$libresoc.v:125923$5270 + parameter \WIDTH 1 + connect \A \gpio_gpio10__core__oe + connect \B \io_bd [34] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:125923$5270_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + cell $mux $ternary$libresoc.v:125924$5271 + parameter \WIDTH 1 + connect \A \gpio_gpio11__pad__i + connect \B \io_bd [35] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:125924$5271_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" + cell $mux $ternary$libresoc.v:125925$5272 + parameter \WIDTH 1 + connect \A \gpio_gpio11__core__o + connect \B \io_bd [36] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:125925$5272_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" + cell $mux $ternary$libresoc.v:125926$5273 + parameter \WIDTH 1 + connect \A \gpio_gpio11__core__oe + connect \B \io_bd [37] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:125926$5273_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + cell $mux $ternary$libresoc.v:125927$5274 + parameter \WIDTH 1 + connect \A \gpio_gpio12__pad__i + connect \B \io_bd [38] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:125927$5274_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" + cell $mux $ternary$libresoc.v:125929$5276 + parameter \WIDTH 1 + connect \A \gpio_gpio12__core__o + connect \B \io_bd [39] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:125929$5276_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" + cell $mux $ternary$libresoc.v:125930$5277 + parameter \WIDTH 1 + connect \A \gpio_gpio12__core__oe + connect \B \io_bd [40] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:125930$5277_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + cell $mux $ternary$libresoc.v:125931$5278 + parameter \WIDTH 1 + connect \A \gpio_gpio13__pad__i + connect \B \io_bd [41] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:125931$5278_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" + cell $mux $ternary$libresoc.v:125932$5279 + parameter \WIDTH 1 + connect \A \gpio_gpio13__core__o + connect \B \io_bd [42] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:125932$5279_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" + cell $mux $ternary$libresoc.v:125933$5280 + parameter \WIDTH 1 + connect \A \gpio_gpio13__core__oe + connect \B \io_bd [43] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:125933$5280_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + cell $mux $ternary$libresoc.v:125934$5281 + parameter \WIDTH 1 + connect \A \gpio_gpio14__pad__i + connect \B \io_bd [44] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:125934$5281_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" + cell $mux $ternary$libresoc.v:125935$5282 + parameter \WIDTH 1 + connect \A \gpio_gpio14__core__o + connect \B \io_bd [45] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:125935$5282_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" + cell $mux $ternary$libresoc.v:125936$5283 + parameter \WIDTH 1 + connect \A \gpio_gpio14__core__oe + connect \B \io_bd [46] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:125936$5283_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + cell $mux $ternary$libresoc.v:125937$5284 + parameter \WIDTH 1 + connect \A \gpio_gpio15__pad__i + connect \B \io_bd [47] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:125937$5284_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" + cell $mux $ternary$libresoc.v:125938$5285 + parameter \WIDTH 1 + connect \A \gpio_gpio15__core__o + connect \B \io_bd [48] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:125938$5285_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" + cell $mux $ternary$libresoc.v:125940$5287 + parameter \WIDTH 1 + connect \A \gpio_gpio15__core__oe + connect \B \io_bd [49] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:125940$5287_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:475" + cell $mux $ternary$libresoc.v:126028$5376 + parameter \WIDTH 1 + connect \A \uart_tx__core__o + connect \B \io_bd [0] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:126028$5376_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:472" + cell $mux $ternary$libresoc.v:126029$5377 + parameter \WIDTH 1 + connect \A \uart_rx__pad__i + connect \B \io_bd [1] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:126029$5377_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + cell $mux $ternary$libresoc.v:126030$5378 + parameter \WIDTH 1 + connect \A \gpio_gpio0__pad__i + connect \B \io_bd [2] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:126030$5378_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" + cell $mux $ternary$libresoc.v:126031$5379 + parameter \WIDTH 1 + connect \A \gpio_gpio0__core__o + connect \B \io_bd [3] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:126031$5379_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" + cell $mux $ternary$libresoc.v:126032$5380 + parameter \WIDTH 1 + connect \A \gpio_gpio0__core__oe + connect \B \io_bd [4] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:126032$5380_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + cell $mux $ternary$libresoc.v:126033$5381 + parameter \WIDTH 1 + connect \A \gpio_gpio1__pad__i + connect \B \io_bd [5] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:126033$5381_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" + cell $mux $ternary$libresoc.v:126034$5382 + parameter \WIDTH 1 + connect \A \gpio_gpio1__core__o + connect \B \io_bd [6] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:126034$5382_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" + cell $mux $ternary$libresoc.v:126035$5383 + parameter \WIDTH 1 + connect \A \gpio_gpio1__core__oe + connect \B \io_bd [7] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:126035$5383_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + cell $mux $ternary$libresoc.v:126036$5384 + parameter \WIDTH 1 + connect \A \gpio_gpio2__pad__i + connect \B \io_bd [8] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:126036$5384_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" + cell $mux $ternary$libresoc.v:126038$5386 + parameter \WIDTH 1 + connect \A \gpio_gpio2__core__o + connect \B \io_bd [9] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:126038$5386_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" + cell $mux $ternary$libresoc.v:126039$5387 + parameter \WIDTH 1 + connect \A \gpio_gpio2__core__oe + connect \B \io_bd [10] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:126039$5387_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + cell $mux $ternary$libresoc.v:126040$5388 + parameter \WIDTH 1 + connect \A \gpio_gpio3__pad__i + connect \B \io_bd [11] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:126040$5388_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" + cell $mux $ternary$libresoc.v:126041$5389 + parameter \WIDTH 1 + connect \A \gpio_gpio3__core__o + connect \B \io_bd [12] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:126041$5389_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" + cell $mux $ternary$libresoc.v:126042$5390 + parameter \WIDTH 1 + connect \A \gpio_gpio3__core__oe + connect \B \io_bd [13] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:126042$5390_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + cell $mux $ternary$libresoc.v:126043$5391 + parameter \WIDTH 1 + connect \A \gpio_gpio4__pad__i + connect \B \io_bd [14] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:126043$5391_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" + cell $mux $ternary$libresoc.v:126044$5392 + parameter \WIDTH 1 + connect \A \gpio_gpio4__core__o + connect \B \io_bd [15] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:126044$5392_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" + cell $mux $ternary$libresoc.v:126045$5393 + parameter \WIDTH 1 + connect \A \gpio_gpio4__core__oe + connect \B \io_bd [16] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:126045$5393_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + cell $mux $ternary$libresoc.v:126046$5394 + parameter \WIDTH 1 + connect \A \gpio_gpio5__pad__i + connect \B \io_bd [17] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:126046$5394_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" + cell $mux $ternary$libresoc.v:126047$5395 + parameter \WIDTH 1 + connect \A \gpio_gpio5__core__o + connect \B \io_bd [18] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:126047$5395_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" + cell $mux $ternary$libresoc.v:126049$5397 + parameter \WIDTH 1 + connect \A \gpio_gpio5__core__oe + connect \B \io_bd [19] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:126049$5397_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + cell $mux $ternary$libresoc.v:126050$5398 + parameter \WIDTH 1 + connect \A \gpio_gpio6__pad__i + connect \B \io_bd [20] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:126050$5398_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" + cell $mux $ternary$libresoc.v:126051$5399 + parameter \WIDTH 1 + connect \A \gpio_gpio6__core__o + connect \B \io_bd [21] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:126051$5399_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" + cell $mux $ternary$libresoc.v:126052$5400 + parameter \WIDTH 1 + connect \A \gpio_gpio6__core__oe + connect \B \io_bd [22] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:126052$5400_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + cell $mux $ternary$libresoc.v:126053$5401 + parameter \WIDTH 1 + connect \A \gpio_gpio7__pad__i + connect \B \io_bd [23] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:126053$5401_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" + cell $mux $ternary$libresoc.v:126054$5402 + parameter \WIDTH 1 + connect \A \gpio_gpio7__core__o + connect \B \io_bd [24] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:126054$5402_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" + cell $mux $ternary$libresoc.v:126055$5403 + parameter \WIDTH 1 + connect \A \gpio_gpio7__core__oe + connect \B \io_bd [25] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:126055$5403_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + cell $mux $ternary$libresoc.v:126056$5404 + parameter \WIDTH 1 + connect \A \gpio_gpio8__pad__i + connect \B \io_bd [26] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:126056$5404_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" + cell $mux $ternary$libresoc.v:126057$5405 + parameter \WIDTH 1 + connect \A \gpio_gpio8__core__o + connect \B \io_bd [27] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:126057$5405_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" + cell $mux $ternary$libresoc.v:126058$5406 + parameter \WIDTH 1 + connect \A \gpio_gpio8__core__oe + connect \B \io_bd [28] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:126058$5406_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:126119.8-126131.4" + cell \_fsm \_fsm + connect \TAP_bus__tck \TAP_bus__tck + connect \TAP_bus__tms \TAP_bus__tms + connect \capture \_fsm_capture + connect \isdr \_fsm_isdr + connect \isir \_fsm_isir + connect \negjtag_clk \negjtag_clk + connect \negjtag_rst \negjtag_rst + connect \posjtag_clk \posjtag_clk + connect \posjtag_rst \posjtag_rst + connect \shift \_fsm_shift + connect \update \_fsm_update + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:126132.12-126142.4" + cell \_idblock \_idblock + connect \TAP_bus__tdi \TAP_bus__tdi + connect \TAP_id_tdo \_idblock_TAP_id_tdo + connect \capture \_fsm_capture + connect \ir \_irblock_ir + connect \isdr \_fsm_isdr + connect \posjtag_clk \posjtag_clk + connect \posjtag_rst \posjtag_rst + connect \shift \_fsm_shift + connect \update \_fsm_update + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:126143.12-126153.4" + cell \_irblock \_irblock + connect \TAP_bus__tdi \TAP_bus__tdi + connect \capture \_fsm_capture + connect \ir \_irblock_ir + connect \isir \_fsm_isir + connect \posjtag_clk \posjtag_clk + connect \posjtag_rst \posjtag_rst + connect \shift \_fsm_shift + connect \tdo \_irblock_tdo + connect \update \_fsm_update + end + attribute \src "libresoc.v:125175.7-125175.20" + process $proc$libresoc.v:125175$5569 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:125501.13-125501.31" + process $proc$libresoc.v:125501$5570 + assign { } { } + assign $1\dmi0_addr_i[3:0] 4'0000 + sync always + sync init + update \dmi0_addr_i $1\dmi0_addr_i[3:0] + end + attribute \src "libresoc.v:125509.7-125509.29" + process $proc$libresoc.v:125509$5571 + assign { } { } + assign $1\dmi0_addrsr__oe[0:0] 1'0 + sync always + sync init + update \dmi0_addrsr__oe $1\dmi0_addrsr__oe[0:0] + end + attribute \src "libresoc.v:125517.13-125517.36" + process $proc$libresoc.v:125517$5572 + assign { } { } + assign $1\dmi0_addrsr_reg[7:0] 8'00000000 + sync always + sync init + update \dmi0_addrsr_reg $1\dmi0_addrsr_reg[7:0] + end + attribute \src "libresoc.v:125525.7-125525.37" + process $proc$libresoc.v:125525$5573 + assign { } { } + assign $1\dmi0_addrsr_update_core[0:0] 1'0 + sync always + sync init + update \dmi0_addrsr_update_core $1\dmi0_addrsr_update_core[0:0] + end + attribute \src "libresoc.v:125529.7-125529.42" + process $proc$libresoc.v:125529$5574 + assign { } { } + assign $1\dmi0_addrsr_update_core_prev[0:0] 1'0 + sync always + sync init + update \dmi0_addrsr_update_core_prev $1\dmi0_addrsr_update_core_prev[0:0] + end + attribute \src "libresoc.v:125533.14-125533.51" + process $proc$libresoc.v:125533$5575 + assign { } { } + assign $1\dmi0_datasr__i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \dmi0_datasr__i $1\dmi0_datasr__i[63:0] + end + attribute \src "libresoc.v:125539.13-125539.35" + process $proc$libresoc.v:125539$5576 + assign { } { } + assign $1\dmi0_datasr__oe[1:0] 2'00 + sync always + sync init + update \dmi0_datasr__oe $1\dmi0_datasr__oe[1:0] + end + attribute \src "libresoc.v:125547.14-125547.52" + process $proc$libresoc.v:125547$5577 + assign { } { } + assign $1\dmi0_datasr_reg[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \dmi0_datasr_reg $1\dmi0_datasr_reg[63:0] + end + attribute \src "libresoc.v:125555.7-125555.37" + process $proc$libresoc.v:125555$5578 + assign { } { } + assign $1\dmi0_datasr_update_core[0:0] 1'0 + sync always + sync init + update \dmi0_datasr_update_core $1\dmi0_datasr_update_core[0:0] + end + attribute \src "libresoc.v:125559.7-125559.42" + process $proc$libresoc.v:125559$5579 + assign { } { } + assign $1\dmi0_datasr_update_core_prev[0:0] 1'0 + sync always + sync init + update \dmi0_datasr_update_core_prev $1\dmi0_datasr_update_core_prev[0:0] + end + attribute \src "libresoc.v:125564.14-125564.45" + process $proc$libresoc.v:125564$5580 + assign { } { } + assign $1\dmi0_din[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \dmi0_din $1\dmi0_din[63:0] + end + attribute \src "libresoc.v:125574.13-125574.29" + process $proc$libresoc.v:125574$5581 + assign { } { } + assign $1\fsm_state[2:0] 3'000 + sync always + sync init + update \fsm_state $1\fsm_state[2:0] + end + attribute \src "libresoc.v:125576.13-125576.35" + process $proc$libresoc.v:125576$5582 + assign { } { } + assign $0\fsm_state$275[2:0]$5583 3'000 + sync always + sync init + update \fsm_state$275 $0\fsm_state$275[2:0]$5583 + end + attribute \src "libresoc.v:125774.14-125774.39" + process $proc$libresoc.v:125774$5584 + assign { } { } + assign $1\io_bd[49:0] 50'00000000000000000000000000000000000000000000000000 + sync always + sync init + update \io_bd $1\io_bd[49:0] + end + attribute \src "libresoc.v:125786.14-125786.39" + process $proc$libresoc.v:125786$5585 + assign { } { } + assign $1\io_sr[49:0] 50'00000000000000000000000000000000000000000000000000 + sync always + sync init + update \io_sr $1\io_sr[49:0] + end + attribute \src "libresoc.v:125795.14-125795.41" + process $proc$libresoc.v:125795$5586 + assign { } { } + assign $1\jtag_wb__adr[28:0] 29'00000000000000000000000000000 + sync always + sync init + update \jtag_wb__adr $1\jtag_wb__adr[28:0] + end + attribute \src "libresoc.v:125804.14-125804.51" + process $proc$libresoc.v:125804$5587 + assign { } { } + assign $1\jtag_wb__dat_w[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \jtag_wb__dat_w $1\jtag_wb__dat_w[63:0] + end + attribute \src "libresoc.v:125818.7-125818.32" + process $proc$libresoc.v:125818$5588 + assign { } { } + assign $1\jtag_wb_addrsr__oe[0:0] 1'0 + sync always + sync init + update \jtag_wb_addrsr__oe $1\jtag_wb_addrsr__oe[0:0] + end + attribute \src "libresoc.v:125826.14-125826.47" + process $proc$libresoc.v:125826$5589 + assign { } { } + assign $1\jtag_wb_addrsr_reg[28:0] 29'00000000000000000000000000000 + sync always + sync init + update \jtag_wb_addrsr_reg $1\jtag_wb_addrsr_reg[28:0] + end + attribute \src "libresoc.v:125834.7-125834.40" + process $proc$libresoc.v:125834$5590 + assign { } { } + assign $1\jtag_wb_addrsr_update_core[0:0] 1'0 + sync always + sync init + update \jtag_wb_addrsr_update_core $1\jtag_wb_addrsr_update_core[0:0] + end + attribute \src "libresoc.v:125838.7-125838.45" + process $proc$libresoc.v:125838$5591 + assign { } { } + assign $1\jtag_wb_addrsr_update_core_prev[0:0] 1'0 + sync always + sync init + update \jtag_wb_addrsr_update_core_prev $1\jtag_wb_addrsr_update_core_prev[0:0] + end + attribute \src "libresoc.v:125842.14-125842.54" + process $proc$libresoc.v:125842$5592 + assign { } { } + assign $1\jtag_wb_datasr__i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \jtag_wb_datasr__i $1\jtag_wb_datasr__i[63:0] + end + attribute \src "libresoc.v:125848.13-125848.38" + process $proc$libresoc.v:125848$5593 + assign { } { } + assign $1\jtag_wb_datasr__oe[1:0] 2'00 + sync always + sync init + update \jtag_wb_datasr__oe $1\jtag_wb_datasr__oe[1:0] + end + attribute \src "libresoc.v:125856.14-125856.55" + process $proc$libresoc.v:125856$5594 + assign { } { } + assign $1\jtag_wb_datasr_reg[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \jtag_wb_datasr_reg $1\jtag_wb_datasr_reg[63:0] + end + attribute \src "libresoc.v:125864.7-125864.40" + process $proc$libresoc.v:125864$5595 + assign { } { } + assign $1\jtag_wb_datasr_update_core[0:0] 1'0 + sync always + sync init + update \jtag_wb_datasr_update_core $1\jtag_wb_datasr_update_core[0:0] + end + attribute \src "libresoc.v:125868.7-125868.45" + process $proc$libresoc.v:125868$5596 + assign { } { } + assign $1\jtag_wb_datasr_update_core_prev[0:0] 1'0 + sync always + sync init + update \jtag_wb_datasr_update_core_prev $1\jtag_wb_datasr_update_core_prev[0:0] + end + attribute \src "libresoc.v:125886.7-125886.21" + process $proc$libresoc.v:125886$5597 + assign { } { } + assign $1\sr0__oe[0:0] 1'0 + sync always + sync init + update \sr0__oe $1\sr0__oe[0:0] + end + attribute \src "libresoc.v:125894.13-125894.27" + process $proc$libresoc.v:125894$5598 + assign { } { } + assign $1\sr0_reg[2:0] 3'000 + sync always + sync init + update \sr0_reg $1\sr0_reg[2:0] + end + attribute \src "libresoc.v:125902.7-125902.29" + process $proc$libresoc.v:125902$5599 + assign { } { } + assign $1\sr0_update_core[0:0] 1'0 + sync always + sync init + update \sr0_update_core $1\sr0_update_core[0:0] + end + attribute \src "libresoc.v:125906.7-125906.34" + process $proc$libresoc.v:125906$5600 + assign { } { } + assign $1\sr0_update_core_prev[0:0] 1'0 + sync always + sync init + update \sr0_update_core_prev $1\sr0_update_core_prev[0:0] + end + attribute \src "libresoc.v:126059.3-126060.45" + process $proc$libresoc.v:126059$5407 + assign { } { } + assign $0\dmi0_datasr__i[63:0] \dmi0_datasr__i$next + sync posedge \clk + update \dmi0_datasr__i $0\dmi0_datasr__i[63:0] + end + attribute \src "libresoc.v:126061.3-126062.33" + process $proc$libresoc.v:126061$5408 + assign { } { } + assign $0\dmi0_din[63:0] \dmi0_din$next + sync posedge \clk + update \dmi0_din $0\dmi0_din[63:0] + end + attribute \src "libresoc.v:126063.3-126064.45" + process $proc$libresoc.v:126063$5409 + assign { } { } + assign $0\fsm_state$275[2:0]$5410 \fsm_state$275$next + sync posedge \clk + update \fsm_state$275 $0\fsm_state$275[2:0]$5410 + end + attribute \src "libresoc.v:126065.3-126066.39" + process $proc$libresoc.v:126065$5411 + assign { } { } + assign $0\dmi0_addr_i[3:0] \dmi0_addr_i$next + sync posedge \clk + update \dmi0_addr_i $0\dmi0_addr_i[3:0] + end + attribute \src "libresoc.v:126067.3-126068.51" + process $proc$libresoc.v:126067$5412 + assign { } { } + assign $0\jtag_wb_datasr__i[63:0] \jtag_wb_datasr__i$next + sync posedge \clk + update \jtag_wb_datasr__i $0\jtag_wb_datasr__i[63:0] + end + attribute \src "libresoc.v:126069.3-126070.45" + process $proc$libresoc.v:126069$5413 + assign { } { } + assign $0\jtag_wb__dat_w[63:0] \jtag_wb__dat_w$next + sync posedge \clk + update \jtag_wb__dat_w $0\jtag_wb__dat_w[63:0] + end + attribute \src "libresoc.v:126071.3-126072.35" + process $proc$libresoc.v:126071$5414 + assign { } { } + assign $0\fsm_state[2:0] \fsm_state$next + sync posedge \clk + update \fsm_state $0\fsm_state[2:0] + end + attribute \src "libresoc.v:126073.3-126074.41" + process $proc$libresoc.v:126073$5415 + assign { } { } + assign $0\jtag_wb__adr[28:0] \jtag_wb__adr$next + sync posedge \clk + update \jtag_wb__adr $0\jtag_wb__adr[28:0] + end + attribute \src "libresoc.v:126075.3-126076.47" + process $proc$libresoc.v:126075$5416 + assign { } { } + assign $0\dmi0_datasr_reg[63:0] \dmi0_datasr_reg$next + sync posedge \posjtag_clk + update \dmi0_datasr_reg $0\dmi0_datasr_reg[63:0] + end + attribute \src "libresoc.v:126077.3-126078.47" + process $proc$libresoc.v:126077$5417 + assign { } { } + assign $0\dmi0_datasr__oe[1:0] \dmi0_datasr__oe$next + sync posedge \clk + update \dmi0_datasr__oe $0\dmi0_datasr__oe[1:0] + end + attribute \src "libresoc.v:126079.3-126080.73" + process $proc$libresoc.v:126079$5418 + assign { } { } + assign $0\dmi0_datasr_update_core_prev[0:0] \dmi0_datasr_update_core_prev$next + sync posedge \clk + update \dmi0_datasr_update_core_prev $0\dmi0_datasr_update_core_prev[0:0] + end + attribute \src "libresoc.v:126081.3-126082.63" + process $proc$libresoc.v:126081$5419 + assign { } { } + assign $0\dmi0_datasr_update_core[0:0] \dmi0_datasr_update_core$next + sync posedge \clk + update \dmi0_datasr_update_core $0\dmi0_datasr_update_core[0:0] + end + attribute \src "libresoc.v:126083.3-126084.47" + process $proc$libresoc.v:126083$5420 + assign { } { } + assign $0\dmi0_addrsr_reg[7:0] \dmi0_addrsr_reg$next + sync posedge \posjtag_clk + update \dmi0_addrsr_reg $0\dmi0_addrsr_reg[7:0] + end + attribute \src "libresoc.v:126085.3-126086.47" + process $proc$libresoc.v:126085$5421 + assign { } { } + assign $0\dmi0_addrsr__oe[0:0] \dmi0_addrsr__oe$next + sync posedge \clk + update \dmi0_addrsr__oe $0\dmi0_addrsr__oe[0:0] + end + attribute \src "libresoc.v:126087.3-126088.73" + process $proc$libresoc.v:126087$5422 + assign { } { } + assign $0\dmi0_addrsr_update_core_prev[0:0] \dmi0_addrsr_update_core_prev$next + sync posedge \clk + update \dmi0_addrsr_update_core_prev $0\dmi0_addrsr_update_core_prev[0:0] + end + attribute \src "libresoc.v:126089.3-126090.63" + process $proc$libresoc.v:126089$5423 + assign { } { } + assign $0\dmi0_addrsr_update_core[0:0] \dmi0_addrsr_update_core$next + sync posedge \clk + update \dmi0_addrsr_update_core $0\dmi0_addrsr_update_core[0:0] + end + attribute \src "libresoc.v:126091.3-126092.53" + process $proc$libresoc.v:126091$5424 + assign { } { } + assign $0\jtag_wb_datasr_reg[63:0] \jtag_wb_datasr_reg$next + sync posedge \posjtag_clk + update \jtag_wb_datasr_reg $0\jtag_wb_datasr_reg[63:0] + end + attribute \src "libresoc.v:126093.3-126094.53" + process $proc$libresoc.v:126093$5425 + assign { } { } + assign $0\jtag_wb_datasr__oe[1:0] \jtag_wb_datasr__oe$next + sync posedge \clk + update \jtag_wb_datasr__oe $0\jtag_wb_datasr__oe[1:0] + end + attribute \src "libresoc.v:126095.3-126096.79" + process $proc$libresoc.v:126095$5426 + assign { } { } + assign $0\jtag_wb_datasr_update_core_prev[0:0] \jtag_wb_datasr_update_core_prev$next + sync posedge \clk + update \jtag_wb_datasr_update_core_prev $0\jtag_wb_datasr_update_core_prev[0:0] + end + attribute \src "libresoc.v:126097.3-126098.69" + process $proc$libresoc.v:126097$5427 + assign { } { } + assign $0\jtag_wb_datasr_update_core[0:0] \jtag_wb_datasr_update_core$next + sync posedge \clk + update \jtag_wb_datasr_update_core $0\jtag_wb_datasr_update_core[0:0] + end + attribute \src "libresoc.v:126099.3-126100.53" + process $proc$libresoc.v:126099$5428 + assign { } { } + assign $0\jtag_wb_addrsr_reg[28:0] \jtag_wb_addrsr_reg$next + sync posedge \posjtag_clk + update \jtag_wb_addrsr_reg $0\jtag_wb_addrsr_reg[28:0] + end + attribute \src "libresoc.v:126101.3-126102.53" + process $proc$libresoc.v:126101$5429 + assign { } { } + assign $0\jtag_wb_addrsr__oe[0:0] \jtag_wb_addrsr__oe$next + sync posedge \clk + update \jtag_wb_addrsr__oe $0\jtag_wb_addrsr__oe[0:0] + end + attribute \src "libresoc.v:126103.3-126104.79" + process $proc$libresoc.v:126103$5430 + assign { } { } + assign $0\jtag_wb_addrsr_update_core_prev[0:0] \jtag_wb_addrsr_update_core_prev$next + sync posedge \clk + update \jtag_wb_addrsr_update_core_prev $0\jtag_wb_addrsr_update_core_prev[0:0] + end + attribute \src "libresoc.v:126105.3-126106.69" + process $proc$libresoc.v:126105$5431 + assign { } { } + assign $0\jtag_wb_addrsr_update_core[0:0] \jtag_wb_addrsr_update_core$next + sync posedge \clk + update \jtag_wb_addrsr_update_core $0\jtag_wb_addrsr_update_core[0:0] + end + attribute \src "libresoc.v:126107.3-126108.31" + process $proc$libresoc.v:126107$5432 + assign { } { } + assign $0\sr0_reg[2:0] \sr0_reg$next + sync posedge \posjtag_clk + update \sr0_reg $0\sr0_reg[2:0] + end + attribute \src "libresoc.v:126109.3-126110.31" + process $proc$libresoc.v:126109$5433 + assign { } { } + assign $0\sr0__oe[0:0] \sr0__oe$next + sync posedge \clk + update \sr0__oe $0\sr0__oe[0:0] + end + attribute \src "libresoc.v:126111.3-126112.57" + process $proc$libresoc.v:126111$5434 + assign { } { } + assign $0\sr0_update_core_prev[0:0] \sr0_update_core_prev$next + sync posedge \clk + update \sr0_update_core_prev $0\sr0_update_core_prev[0:0] + end + attribute \src "libresoc.v:126113.3-126114.47" + process $proc$libresoc.v:126113$5435 + assign { } { } + assign $0\sr0_update_core[0:0] \sr0_update_core$next + sync posedge \clk + update \sr0_update_core $0\sr0_update_core[0:0] + end + attribute \src "libresoc.v:126115.3-126116.27" + process $proc$libresoc.v:126115$5436 + assign { } { } + assign $0\io_bd[49:0] \io_bd$next + sync negedge \negjtag_clk + update \io_bd $0\io_bd[49:0] + end + attribute \src "libresoc.v:126117.3-126118.27" + process $proc$libresoc.v:126117$5437 + assign { } { } + assign $0\io_sr[49:0] \io_sr$next + sync posedge \posjtag_clk + update \io_sr $0\io_sr[49:0] + end + attribute \src "libresoc.v:126154.3-126162.6" + process $proc$libresoc.v:126154$5438 + assign { } { } + assign { } { } + assign $0\dmi0_datasr_update_core_prev$next[0:0]$5439 $1\dmi0_datasr_update_core_prev$next[0:0]$5440 + attribute \src "libresoc.v:126155.5-126155.29" + switch \initial + attribute \src "libresoc.v:126155.9-126155.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dmi0_datasr_update_core_prev$next[0:0]$5440 1'0 + case + assign $1\dmi0_datasr_update_core_prev$next[0:0]$5440 \dmi0_datasr_update_core + end + sync always + update \dmi0_datasr_update_core_prev$next $0\dmi0_datasr_update_core_prev$next[0:0]$5439 + end + attribute \src "libresoc.v:126163.3-126179.6" + process $proc$libresoc.v:126163$5441 + assign { } { } + assign { } { } + assign $0\dmi0_datasr__oe$next[1:0]$5442 $2\dmi0_datasr__oe$next[1:0]$5444 + attribute \src "libresoc.v:126164.5-126164.29" + switch \initial + attribute \src "libresoc.v:126164.9-126164.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:553" + switch \$253 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dmi0_datasr__oe$next[1:0]$5443 \dmi0_datasr_isir + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\dmi0_datasr__oe$next[1:0]$5443 2'00 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\dmi0_datasr__oe$next[1:0]$5444 2'00 + case + assign $2\dmi0_datasr__oe$next[1:0]$5444 $1\dmi0_datasr__oe$next[1:0]$5443 + end + sync always + update \dmi0_datasr__oe$next $0\dmi0_datasr__oe$next[1:0]$5442 + end + attribute \src "libresoc.v:126180.3-126200.6" + process $proc$libresoc.v:126180$5445 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\dmi0_datasr_reg$next[63:0]$5446 $3\dmi0_datasr_reg$next[63:0]$5449 + attribute \src "libresoc.v:126181.5-126181.29" + switch \initial + attribute \src "libresoc.v:126181.9-126181.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:559" + switch \dmi0_datasr_shift + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dmi0_datasr_reg$next[63:0]$5447 { \TAP_bus__tdi \dmi0_datasr_reg [63:1] } + case + assign $1\dmi0_datasr_reg$next[63:0]$5447 \dmi0_datasr_reg + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:561" + switch \dmi0_datasr_capture + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\dmi0_datasr_reg$next[63:0]$5448 \dmi0_datasr__i + case + assign $2\dmi0_datasr_reg$next[63:0]$5448 $1\dmi0_datasr_reg$next[63:0]$5447 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \posjtag_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\dmi0_datasr_reg$next[63:0]$5449 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $3\dmi0_datasr_reg$next[63:0]$5449 $2\dmi0_datasr_reg$next[63:0]$5448 + end + sync always + update \dmi0_datasr_reg$next $0\dmi0_datasr_reg$next[63:0]$5446 + end + attribute \src "libresoc.v:126201.3-126224.6" + process $proc$libresoc.v:126201$5450 + assign { } { } + assign $0\TAP_bus__tdo[0:0] $1\TAP_bus__tdo[0:0] + attribute \src "libresoc.v:126202.5-126202.29" + switch \initial + attribute \src "libresoc.v:126202.9-126202.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:571" + switch { \dmi0_datasr_shift \dmi0_addrsr_shift \jtag_wb_datasr_shift \jtag_wb_addrsr_shift \sr0_shift } + attribute \src "libresoc.v:0.0-0.0" + case 5'----1 + assign { } { } + assign $1\TAP_bus__tdo[0:0] \sr0_reg [0] + attribute \src "libresoc.v:0.0-0.0" + case 5'---1- + assign { } { } + assign $1\TAP_bus__tdo[0:0] \jtag_wb_addrsr_reg [0] + attribute \src "libresoc.v:0.0-0.0" + case 5'--1-- + assign { } { } + assign $1\TAP_bus__tdo[0:0] \jtag_wb_datasr_reg [0] + attribute \src "libresoc.v:0.0-0.0" + case 5'-1--- + assign { } { } + assign $1\TAP_bus__tdo[0:0] \dmi0_addrsr_reg [0] + attribute \src "libresoc.v:0.0-0.0" + case 5'1---- + assign { } { } + assign $1\TAP_bus__tdo[0:0] \dmi0_datasr_reg [0] + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\TAP_bus__tdo[0:0] \TAP_tdo + end + sync always + update \TAP_bus__tdo $0\TAP_bus__tdo[0:0] + end + attribute \src "libresoc.v:126225.3-126257.6" + process $proc$libresoc.v:126225$5451 + assign { } { } + assign { } { } + assign { } { } + assign $0\jtag_wb__adr$next[28:0]$5452 $4\jtag_wb__adr$next[28:0]$5456 + attribute \src "libresoc.v:126226.5-126226.29" + switch \initial + attribute \src "libresoc.v:126226.9-126226.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:194" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 3'000 + assign { } { } + assign $1\jtag_wb__adr$next[28:0]$5453 $2\jtag_wb__adr$next[28:0]$5454 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:196" + switch { \jtag_wb_datasr__oe \jtag_wb_addrsr__oe } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign { } { } + assign $2\jtag_wb__adr$next[28:0]$5454 \jtag_wb_addrsr__o + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- + assign { } { } + assign $2\jtag_wb__adr$next[28:0]$5454 \$267 [28:0] + case + assign $2\jtag_wb__adr$next[28:0]$5454 \jtag_wb__adr + end + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\jtag_wb__adr$next[28:0]$5453 $3\jtag_wb__adr$next[28:0]$5455 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:224" + switch \jtag_wb__ack + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\jtag_wb__adr$next[28:0]$5455 \$270 [28:0] + case + assign $3\jtag_wb__adr$next[28:0]$5455 \jtag_wb__adr + end + case + assign $1\jtag_wb__adr$next[28:0]$5453 \jtag_wb__adr + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\jtag_wb__adr$next[28:0]$5456 29'00000000000000000000000000000 + case + assign $4\jtag_wb__adr$next[28:0]$5456 $1\jtag_wb__adr$next[28:0]$5453 + end + sync always + update \jtag_wb__adr$next $0\jtag_wb__adr$next[28:0]$5452 + end + attribute \src "libresoc.v:126258.3-126310.6" + process $proc$libresoc.v:126258$5457 + assign { } { } + assign { } { } + assign { } { } + assign $0\fsm_state$next[2:0]$5458 $5\fsm_state$next[2:0]$5463 + attribute \src "libresoc.v:126259.5-126259.29" + switch \initial + attribute \src "libresoc.v:126259.9-126259.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:194" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 3'000 + assign { } { } + assign $1\fsm_state$next[2:0]$5459 $2\fsm_state$next[2:0]$5460 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:196" + switch { \jtag_wb_datasr__oe \jtag_wb_addrsr__oe } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign { } { } + assign $2\fsm_state$next[2:0]$5460 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- + assign { } { } + assign $2\fsm_state$next[2:0]$5460 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 3'1-- + assign { } { } + assign $2\fsm_state$next[2:0]$5460 3'010 + case + assign $2\fsm_state$next[2:0]$5460 \fsm_state + end + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\fsm_state$next[2:0]$5459 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\fsm_state$next[2:0]$5459 $3\fsm_state$next[2:0]$5461 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:213" + switch \jtag_wb__ack + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fsm_state$next[2:0]$5461 3'000 + case + assign $3\fsm_state$next[2:0]$5461 \fsm_state + end + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\fsm_state$next[2:0]$5459 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\fsm_state$next[2:0]$5459 $4\fsm_state$next[2:0]$5462 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:224" + switch \jtag_wb__ack + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\fsm_state$next[2:0]$5462 3'001 + case + assign $4\fsm_state$next[2:0]$5462 \fsm_state + end + case + assign $1\fsm_state$next[2:0]$5459 \fsm_state + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\fsm_state$next[2:0]$5463 3'000 + case + assign $5\fsm_state$next[2:0]$5463 $1\fsm_state$next[2:0]$5459 + end + sync always + update \fsm_state$next $0\fsm_state$next[2:0]$5458 + end + attribute \src "libresoc.v:126311.3-126337.6" + process $proc$libresoc.v:126311$5464 + assign { } { } + assign { } { } + assign { } { } + assign $0\jtag_wb__dat_w$next[63:0]$5465 $3\jtag_wb__dat_w$next[63:0]$5468 + attribute \src "libresoc.v:126312.5-126312.29" + switch \initial + attribute \src "libresoc.v:126312.9-126312.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:194" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 3'000 + assign { } { } + assign $1\jtag_wb__dat_w$next[63:0]$5466 $2\jtag_wb__dat_w$next[63:0]$5467 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:196" + switch { \jtag_wb_datasr__oe \jtag_wb_addrsr__oe } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign $2\jtag_wb__dat_w$next[63:0]$5467 \jtag_wb__dat_w + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- + assign $2\jtag_wb__dat_w$next[63:0]$5467 \jtag_wb__dat_w + attribute \src "libresoc.v:0.0-0.0" + case 3'1-- + assign { } { } + assign $2\jtag_wb__dat_w$next[63:0]$5467 \jtag_wb_datasr__o + case + assign $2\jtag_wb__dat_w$next[63:0]$5467 \jtag_wb__dat_w + end + case + assign $1\jtag_wb__dat_w$next[63:0]$5466 \jtag_wb__dat_w + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\jtag_wb__dat_w$next[63:0]$5468 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $3\jtag_wb__dat_w$next[63:0]$5468 $1\jtag_wb__dat_w$next[63:0]$5466 + end + sync always + update \jtag_wb__dat_w$next $0\jtag_wb__dat_w$next[63:0]$5465 + end + attribute \src "libresoc.v:126338.3-126358.6" + process $proc$libresoc.v:126338$5469 + assign { } { } + assign { } { } + assign { } { } + assign $0\jtag_wb_datasr__i$next[63:0]$5470 $3\jtag_wb_datasr__i$next[63:0]$5473 + attribute \src "libresoc.v:126339.5-126339.29" + switch \initial + attribute \src "libresoc.v:126339.9-126339.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:194" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\jtag_wb_datasr__i$next[63:0]$5471 $2\jtag_wb_datasr__i$next[63:0]$5472 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:213" + switch \jtag_wb__ack + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\jtag_wb_datasr__i$next[63:0]$5472 \jtag_wb__dat_r + case + assign $2\jtag_wb_datasr__i$next[63:0]$5472 \jtag_wb_datasr__i + end + case + assign $1\jtag_wb_datasr__i$next[63:0]$5471 \jtag_wb_datasr__i + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\jtag_wb_datasr__i$next[63:0]$5473 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $3\jtag_wb_datasr__i$next[63:0]$5473 $1\jtag_wb_datasr__i$next[63:0]$5471 + end + sync always + update \jtag_wb_datasr__i$next $0\jtag_wb_datasr__i$next[63:0]$5470 + end + attribute \src "libresoc.v:126359.3-126391.6" + process $proc$libresoc.v:126359$5474 + assign { } { } + assign { } { } + assign { } { } + assign $0\dmi0_addr_i$next[3:0]$5475 $4\dmi0_addr_i$next[3:0]$5479 + attribute \src "libresoc.v:126360.5-126360.29" + switch \initial + attribute \src "libresoc.v:126360.9-126360.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:144" + switch \fsm_state$275 + attribute \src "libresoc.v:0.0-0.0" + case 3'000 + assign { } { } + assign $1\dmi0_addr_i$next[3:0]$5476 $2\dmi0_addr_i$next[3:0]$5477 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:148" + switch { \dmi0_datasr__oe \dmi0_addrsr__oe } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign { } { } + assign $2\dmi0_addr_i$next[3:0]$5477 \dmi0_addrsr__o [3:0] + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- + assign { } { } + assign $2\dmi0_addr_i$next[3:0]$5477 \$284 [3:0] + case + assign $2\dmi0_addr_i$next[3:0]$5477 \dmi0_addr_i + end + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\dmi0_addr_i$next[3:0]$5476 $3\dmi0_addr_i$next[3:0]$5478 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:176" + switch \dmi0_ack_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\dmi0_addr_i$next[3:0]$5478 \$287 [3:0] + case + assign $3\dmi0_addr_i$next[3:0]$5478 \dmi0_addr_i + end + case + assign $1\dmi0_addr_i$next[3:0]$5476 \dmi0_addr_i + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\dmi0_addr_i$next[3:0]$5479 4'0000 + case + assign $4\dmi0_addr_i$next[3:0]$5479 $1\dmi0_addr_i$next[3:0]$5476 + end + sync always + update \dmi0_addr_i$next $0\dmi0_addr_i$next[3:0]$5475 + end + attribute \src "libresoc.v:126392.3-126444.6" + process $proc$libresoc.v:126392$5480 + assign { } { } + assign { } { } + assign { } { } + assign $0\fsm_state$275$next[2:0]$5481 $5\fsm_state$275$next[2:0]$5486 + attribute \src "libresoc.v:126393.5-126393.29" + switch \initial + attribute \src "libresoc.v:126393.9-126393.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:144" + switch \fsm_state$275 + attribute \src "libresoc.v:0.0-0.0" + case 3'000 + assign { } { } + assign $1\fsm_state$275$next[2:0]$5482 $2\fsm_state$275$next[2:0]$5483 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:148" + switch { \dmi0_datasr__oe \dmi0_addrsr__oe } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign { } { } + assign $2\fsm_state$275$next[2:0]$5483 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- + assign { } { } + assign $2\fsm_state$275$next[2:0]$5483 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 3'1-- + assign { } { } + assign $2\fsm_state$275$next[2:0]$5483 3'010 + case + assign $2\fsm_state$275$next[2:0]$5483 \fsm_state$275 + end + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\fsm_state$275$next[2:0]$5482 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\fsm_state$275$next[2:0]$5482 $3\fsm_state$275$next[2:0]$5484 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:165" + switch \dmi0_ack_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fsm_state$275$next[2:0]$5484 3'000 + case + assign $3\fsm_state$275$next[2:0]$5484 \fsm_state$275 + end + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\fsm_state$275$next[2:0]$5482 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\fsm_state$275$next[2:0]$5482 $4\fsm_state$275$next[2:0]$5485 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:176" + switch \dmi0_ack_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\fsm_state$275$next[2:0]$5485 3'001 + case + assign $4\fsm_state$275$next[2:0]$5485 \fsm_state$275 + end + case + assign $1\fsm_state$275$next[2:0]$5482 \fsm_state$275 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\fsm_state$275$next[2:0]$5486 3'000 + case + assign $5\fsm_state$275$next[2:0]$5486 $1\fsm_state$275$next[2:0]$5482 + end + sync always + update \fsm_state$275$next $0\fsm_state$275$next[2:0]$5481 + end + attribute \src "libresoc.v:126445.3-126471.6" + process $proc$libresoc.v:126445$5487 + assign { } { } + assign { } { } + assign { } { } + assign $0\dmi0_din$next[63:0]$5488 $3\dmi0_din$next[63:0]$5491 + attribute \src "libresoc.v:126446.5-126446.29" + switch \initial + attribute \src "libresoc.v:126446.9-126446.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:144" + switch \fsm_state$275 + attribute \src "libresoc.v:0.0-0.0" + case 3'000 + assign { } { } + assign $1\dmi0_din$next[63:0]$5489 $2\dmi0_din$next[63:0]$5490 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:148" + switch { \dmi0_datasr__oe \dmi0_addrsr__oe } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign $2\dmi0_din$next[63:0]$5490 \dmi0_din + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- + assign $2\dmi0_din$next[63:0]$5490 \dmi0_din + attribute \src "libresoc.v:0.0-0.0" + case 3'1-- + assign { } { } + assign $2\dmi0_din$next[63:0]$5490 \dmi0_datasr__o + case + assign $2\dmi0_din$next[63:0]$5490 \dmi0_din + end + case + assign $1\dmi0_din$next[63:0]$5489 \dmi0_din + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\dmi0_din$next[63:0]$5491 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $3\dmi0_din$next[63:0]$5491 $1\dmi0_din$next[63:0]$5489 + end + sync always + update \dmi0_din$next $0\dmi0_din$next[63:0]$5488 + end + attribute \src "libresoc.v:126472.3-126492.6" + process $proc$libresoc.v:126472$5492 + assign { } { } + assign { } { } + assign { } { } + assign $0\dmi0_datasr__i$next[63:0]$5493 $3\dmi0_datasr__i$next[63:0]$5496 + attribute \src "libresoc.v:126473.5-126473.29" + switch \initial + attribute \src "libresoc.v:126473.9-126473.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:144" + switch \fsm_state$275 + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\dmi0_datasr__i$next[63:0]$5494 $2\dmi0_datasr__i$next[63:0]$5495 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:165" + switch \dmi0_ack_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\dmi0_datasr__i$next[63:0]$5495 \dmi0_dout + case + assign $2\dmi0_datasr__i$next[63:0]$5495 \dmi0_datasr__i + end + case + assign $1\dmi0_datasr__i$next[63:0]$5494 \dmi0_datasr__i + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\dmi0_datasr__i$next[63:0]$5496 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $3\dmi0_datasr__i$next[63:0]$5496 $1\dmi0_datasr__i$next[63:0]$5494 + end + sync always + update \dmi0_datasr__i$next $0\dmi0_datasr__i$next[63:0]$5493 + end + attribute \src "libresoc.v:126493.3-126561.6" + process $proc$libresoc.v:126493$5497 + assign { } { } + assign { } { } + assign { } { } + assign $0\io_sr$next[49:0]$5498 $2\io_sr$next[49:0]$5500 + attribute \src "libresoc.v:126494.5-126494.29" + switch \initial + attribute \src "libresoc.v:126494.9-126494.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:439" + switch { \io_update \io_shift \io_capture } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign { } { } + assign $1\io_sr$next[49:0]$5499 [0] \uart_tx__core__o + assign $1\io_sr$next[49:0]$5499 [1] \uart_rx__pad__i + assign $1\io_sr$next[49:0]$5499 [2] \gpio_gpio0__pad__i + assign $1\io_sr$next[49:0]$5499 [3] \gpio_gpio0__core__o + assign $1\io_sr$next[49:0]$5499 [4] \gpio_gpio0__core__oe + assign $1\io_sr$next[49:0]$5499 [5] \gpio_gpio1__pad__i + assign $1\io_sr$next[49:0]$5499 [6] \gpio_gpio1__core__o + assign $1\io_sr$next[49:0]$5499 [7] \gpio_gpio1__core__oe + assign $1\io_sr$next[49:0]$5499 [8] \gpio_gpio2__pad__i + assign $1\io_sr$next[49:0]$5499 [9] \gpio_gpio2__core__o + assign $1\io_sr$next[49:0]$5499 [10] \gpio_gpio2__core__oe + assign $1\io_sr$next[49:0]$5499 [11] \gpio_gpio3__pad__i + assign $1\io_sr$next[49:0]$5499 [12] \gpio_gpio3__core__o + assign $1\io_sr$next[49:0]$5499 [13] \gpio_gpio3__core__oe + assign $1\io_sr$next[49:0]$5499 [14] \gpio_gpio4__pad__i + assign $1\io_sr$next[49:0]$5499 [15] \gpio_gpio4__core__o + assign $1\io_sr$next[49:0]$5499 [16] \gpio_gpio4__core__oe + assign $1\io_sr$next[49:0]$5499 [17] \gpio_gpio5__pad__i + assign $1\io_sr$next[49:0]$5499 [18] \gpio_gpio5__core__o + assign $1\io_sr$next[49:0]$5499 [19] \gpio_gpio5__core__oe + assign $1\io_sr$next[49:0]$5499 [20] \gpio_gpio6__pad__i + assign $1\io_sr$next[49:0]$5499 [21] \gpio_gpio6__core__o + assign $1\io_sr$next[49:0]$5499 [22] \gpio_gpio6__core__oe + assign $1\io_sr$next[49:0]$5499 [23] \gpio_gpio7__pad__i + assign $1\io_sr$next[49:0]$5499 [24] \gpio_gpio7__core__o + assign $1\io_sr$next[49:0]$5499 [25] \gpio_gpio7__core__oe + assign $1\io_sr$next[49:0]$5499 [26] \gpio_gpio8__pad__i + assign $1\io_sr$next[49:0]$5499 [27] \gpio_gpio8__core__o + assign $1\io_sr$next[49:0]$5499 [28] \gpio_gpio8__core__oe + assign $1\io_sr$next[49:0]$5499 [29] \gpio_gpio9__pad__i + assign $1\io_sr$next[49:0]$5499 [30] \gpio_gpio9__core__o + assign $1\io_sr$next[49:0]$5499 [31] \gpio_gpio9__core__oe + assign $1\io_sr$next[49:0]$5499 [32] \gpio_gpio10__pad__i + assign $1\io_sr$next[49:0]$5499 [33] \gpio_gpio10__core__o + assign $1\io_sr$next[49:0]$5499 [34] \gpio_gpio10__core__oe + assign $1\io_sr$next[49:0]$5499 [35] \gpio_gpio11__pad__i + assign $1\io_sr$next[49:0]$5499 [36] \gpio_gpio11__core__o + assign $1\io_sr$next[49:0]$5499 [37] \gpio_gpio11__core__oe + assign $1\io_sr$next[49:0]$5499 [38] \gpio_gpio12__pad__i + assign $1\io_sr$next[49:0]$5499 [39] \gpio_gpio12__core__o + assign $1\io_sr$next[49:0]$5499 [40] \gpio_gpio12__core__oe + assign $1\io_sr$next[49:0]$5499 [41] \gpio_gpio13__pad__i + assign $1\io_sr$next[49:0]$5499 [42] \gpio_gpio13__core__o + assign $1\io_sr$next[49:0]$5499 [43] \gpio_gpio13__core__oe + assign $1\io_sr$next[49:0]$5499 [44] \gpio_gpio14__pad__i + assign $1\io_sr$next[49:0]$5499 [45] \gpio_gpio14__core__o + assign $1\io_sr$next[49:0]$5499 [46] \gpio_gpio14__core__oe + assign $1\io_sr$next[49:0]$5499 [47] \gpio_gpio15__pad__i + assign $1\io_sr$next[49:0]$5499 [48] \gpio_gpio15__core__o + assign $1\io_sr$next[49:0]$5499 [49] \gpio_gpio15__core__oe + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- + assign { } { } + assign $1\io_sr$next[49:0]$5499 { \io_sr [48:0] \TAP_bus__tdi } + case + assign $1\io_sr$next[49:0]$5499 \io_sr + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \posjtag_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\io_sr$next[49:0]$5500 50'00000000000000000000000000000000000000000000000000 + case + assign $2\io_sr$next[49:0]$5500 $1\io_sr$next[49:0]$5499 + end + sync always + update \io_sr$next $0\io_sr$next[49:0]$5498 + end + attribute \src "libresoc.v:126562.3-126577.6" + process $proc$libresoc.v:126562$5501 + assign { } { } + assign { } { } + assign $0\TAP_tdo[0:0] $1\TAP_tdo[0:0] + attribute \src "libresoc.v:126563.5-126563.29" + switch \initial + attribute \src "libresoc.v:126563.9-126563.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:395" + switch { \$159 \$147 \_fsm_isir } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign { } { } + assign $1\TAP_tdo[0:0] \_irblock_tdo + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- + assign { } { } + assign $1\TAP_tdo[0:0] \_idblock_TAP_id_tdo + attribute \src "libresoc.v:0.0-0.0" + case 3'1-- + assign { } { } + assign $1\TAP_tdo[0:0] \io_sr [49] + case + assign $1\TAP_tdo[0:0] 1'0 + end + sync always + update \TAP_tdo $0\TAP_tdo[0:0] + end + attribute \src "libresoc.v:126578.3-126598.6" + process $proc$libresoc.v:126578$5502 + assign { } { } + assign { } { } + assign { } { } + assign $0\io_bd$next[49:0]$5503 $2\io_bd$next[49:0]$5505 + attribute \src "libresoc.v:126579.5-126579.29" + switch \initial + attribute \src "libresoc.v:126579.9-126579.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:439" + switch { \io_update \io_shift \io_capture } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign $1\io_bd$next[49:0]$5504 \io_bd + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- + assign $1\io_bd$next[49:0]$5504 \io_bd + attribute \src "libresoc.v:0.0-0.0" + case 3'1-- + assign { } { } + assign $1\io_bd$next[49:0]$5504 \io_sr + case + assign $1\io_bd$next[49:0]$5504 \io_bd + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \negjtag_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\io_bd$next[49:0]$5505 50'00000000000000000000000000000000000000000000000000 + case + assign $2\io_bd$next[49:0]$5505 $1\io_bd$next[49:0]$5504 + end + sync always + update \io_bd$next $0\io_bd$next[49:0]$5503 + end + attribute \src "libresoc.v:126599.3-126607.6" + process $proc$libresoc.v:126599$5506 + assign { } { } + assign { } { } + assign $0\sr0_update_core$next[0:0]$5507 $1\sr0_update_core$next[0:0]$5508 + attribute \src "libresoc.v:126600.5-126600.29" + switch \initial + attribute \src "libresoc.v:126600.9-126600.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\sr0_update_core$next[0:0]$5508 1'0 + case + assign $1\sr0_update_core$next[0:0]$5508 \sr0_update + end + sync always + update \sr0_update_core$next $0\sr0_update_core$next[0:0]$5507 + end + attribute \src "libresoc.v:126608.3-126616.6" + process $proc$libresoc.v:126608$5509 + assign { } { } + assign { } { } + assign $0\sr0_update_core_prev$next[0:0]$5510 $1\sr0_update_core_prev$next[0:0]$5511 + attribute \src "libresoc.v:126609.5-126609.29" + switch \initial + attribute \src "libresoc.v:126609.9-126609.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\sr0_update_core_prev$next[0:0]$5511 1'0 + case + assign $1\sr0_update_core_prev$next[0:0]$5511 \sr0_update_core + end + sync always + update \sr0_update_core_prev$next $0\sr0_update_core_prev$next[0:0]$5510 + end + attribute \src "libresoc.v:126617.3-126633.6" + process $proc$libresoc.v:126617$5512 + assign { } { } + assign { } { } + assign $0\sr0__oe$next[0:0]$5513 $2\sr0__oe$next[0:0]$5515 + attribute \src "libresoc.v:126618.5-126618.29" + switch \initial + attribute \src "libresoc.v:126618.9-126618.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:553" + switch \$177 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\sr0__oe$next[0:0]$5514 \sr0_isir + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\sr0__oe$next[0:0]$5514 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\sr0__oe$next[0:0]$5515 1'0 + case + assign $2\sr0__oe$next[0:0]$5515 $1\sr0__oe$next[0:0]$5514 + end + sync always + update \sr0__oe$next $0\sr0__oe$next[0:0]$5513 + end + attribute \src "libresoc.v:126634.3-126654.6" + process $proc$libresoc.v:126634$5516 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\sr0_reg$next[2:0]$5517 $3\sr0_reg$next[2:0]$5520 + attribute \src "libresoc.v:126635.5-126635.29" + switch \initial + attribute \src "libresoc.v:126635.9-126635.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:559" + switch \sr0_shift + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\sr0_reg$next[2:0]$5518 { \TAP_bus__tdi \sr0_reg [2:1] } + case + assign $1\sr0_reg$next[2:0]$5518 \sr0_reg + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:561" + switch \sr0_capture + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\sr0_reg$next[2:0]$5519 \sr0__i + case + assign $2\sr0_reg$next[2:0]$5519 $1\sr0_reg$next[2:0]$5518 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \posjtag_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\sr0_reg$next[2:0]$5520 3'000 + case + assign $3\sr0_reg$next[2:0]$5520 $2\sr0_reg$next[2:0]$5519 + end + sync always + update \sr0_reg$next $0\sr0_reg$next[2:0]$5517 + end + attribute \src "libresoc.v:126655.3-126663.6" + process $proc$libresoc.v:126655$5521 + assign { } { } + assign { } { } + assign $0\jtag_wb_addrsr_update_core$next[0:0]$5522 $1\jtag_wb_addrsr_update_core$next[0:0]$5523 + attribute \src "libresoc.v:126656.5-126656.29" + switch \initial + attribute \src "libresoc.v:126656.9-126656.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\jtag_wb_addrsr_update_core$next[0:0]$5523 1'0 + case + assign $1\jtag_wb_addrsr_update_core$next[0:0]$5523 \jtag_wb_addrsr_update + end + sync always + update \jtag_wb_addrsr_update_core$next $0\jtag_wb_addrsr_update_core$next[0:0]$5522 + end + attribute \src "libresoc.v:126664.3-126672.6" + process $proc$libresoc.v:126664$5524 + assign { } { } + assign { } { } + assign $0\jtag_wb_addrsr_update_core_prev$next[0:0]$5525 $1\jtag_wb_addrsr_update_core_prev$next[0:0]$5526 + attribute \src "libresoc.v:126665.5-126665.29" + switch \initial + attribute \src "libresoc.v:126665.9-126665.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\jtag_wb_addrsr_update_core_prev$next[0:0]$5526 1'0 + case + assign $1\jtag_wb_addrsr_update_core_prev$next[0:0]$5526 \jtag_wb_addrsr_update_core + end + sync always + update \jtag_wb_addrsr_update_core_prev$next $0\jtag_wb_addrsr_update_core_prev$next[0:0]$5525 + end + attribute \src "libresoc.v:126673.3-126689.6" + process $proc$libresoc.v:126673$5527 + assign { } { } + assign { } { } + assign $0\jtag_wb_addrsr__oe$next[0:0]$5528 $2\jtag_wb_addrsr__oe$next[0:0]$5530 + attribute \src "libresoc.v:126674.5-126674.29" + switch \initial + attribute \src "libresoc.v:126674.9-126674.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:553" + switch \$195 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\jtag_wb_addrsr__oe$next[0:0]$5529 \jtag_wb_addrsr_isir + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\jtag_wb_addrsr__oe$next[0:0]$5529 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\jtag_wb_addrsr__oe$next[0:0]$5530 1'0 + case + assign $2\jtag_wb_addrsr__oe$next[0:0]$5530 $1\jtag_wb_addrsr__oe$next[0:0]$5529 + end + sync always + update \jtag_wb_addrsr__oe$next $0\jtag_wb_addrsr__oe$next[0:0]$5528 + end + attribute \src "libresoc.v:126690.3-126710.6" + process $proc$libresoc.v:126690$5531 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\jtag_wb_addrsr_reg$next[28:0]$5532 $3\jtag_wb_addrsr_reg$next[28:0]$5535 + attribute \src "libresoc.v:126691.5-126691.29" + switch \initial + attribute \src "libresoc.v:126691.9-126691.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:559" + switch \jtag_wb_addrsr_shift + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\jtag_wb_addrsr_reg$next[28:0]$5533 { \TAP_bus__tdi \jtag_wb_addrsr_reg [28:1] } + case + assign $1\jtag_wb_addrsr_reg$next[28:0]$5533 \jtag_wb_addrsr_reg + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:561" + switch \jtag_wb_addrsr_capture + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\jtag_wb_addrsr_reg$next[28:0]$5534 \jtag_wb_addrsr__i + case + assign $2\jtag_wb_addrsr_reg$next[28:0]$5534 $1\jtag_wb_addrsr_reg$next[28:0]$5533 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \posjtag_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\jtag_wb_addrsr_reg$next[28:0]$5535 29'00000000000000000000000000000 + case + assign $3\jtag_wb_addrsr_reg$next[28:0]$5535 $2\jtag_wb_addrsr_reg$next[28:0]$5534 + end + sync always + update \jtag_wb_addrsr_reg$next $0\jtag_wb_addrsr_reg$next[28:0]$5532 + end + attribute \src "libresoc.v:126711.3-126719.6" + process $proc$libresoc.v:126711$5536 + assign { } { } + assign { } { } + assign $0\jtag_wb_datasr_update_core$next[0:0]$5537 $1\jtag_wb_datasr_update_core$next[0:0]$5538 + attribute \src "libresoc.v:126712.5-126712.29" + switch \initial + attribute \src "libresoc.v:126712.9-126712.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\jtag_wb_datasr_update_core$next[0:0]$5538 1'0 + case + assign $1\jtag_wb_datasr_update_core$next[0:0]$5538 \jtag_wb_datasr_update + end + sync always + update \jtag_wb_datasr_update_core$next $0\jtag_wb_datasr_update_core$next[0:0]$5537 + end + attribute \src "libresoc.v:126720.3-126728.6" + process $proc$libresoc.v:126720$5539 + assign { } { } + assign { } { } + assign $0\jtag_wb_datasr_update_core_prev$next[0:0]$5540 $1\jtag_wb_datasr_update_core_prev$next[0:0]$5541 + attribute \src "libresoc.v:126721.5-126721.29" + switch \initial + attribute \src "libresoc.v:126721.9-126721.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\jtag_wb_datasr_update_core_prev$next[0:0]$5541 1'0 + case + assign $1\jtag_wb_datasr_update_core_prev$next[0:0]$5541 \jtag_wb_datasr_update_core + end + sync always + update \jtag_wb_datasr_update_core_prev$next $0\jtag_wb_datasr_update_core_prev$next[0:0]$5540 + end + attribute \src "libresoc.v:126729.3-126745.6" + process $proc$libresoc.v:126729$5542 + assign { } { } + assign { } { } + assign $0\jtag_wb_datasr__oe$next[1:0]$5543 $2\jtag_wb_datasr__oe$next[1:0]$5545 + attribute \src "libresoc.v:126730.5-126730.29" + switch \initial + attribute \src "libresoc.v:126730.9-126730.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:553" + switch \$215 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\jtag_wb_datasr__oe$next[1:0]$5544 \jtag_wb_datasr_isir + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\jtag_wb_datasr__oe$next[1:0]$5544 2'00 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\jtag_wb_datasr__oe$next[1:0]$5545 2'00 + case + assign $2\jtag_wb_datasr__oe$next[1:0]$5545 $1\jtag_wb_datasr__oe$next[1:0]$5544 + end + sync always + update \jtag_wb_datasr__oe$next $0\jtag_wb_datasr__oe$next[1:0]$5543 + end + attribute \src "libresoc.v:126746.3-126766.6" + process $proc$libresoc.v:126746$5546 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\jtag_wb_datasr_reg$next[63:0]$5547 $3\jtag_wb_datasr_reg$next[63:0]$5550 + attribute \src "libresoc.v:126747.5-126747.29" + switch \initial + attribute \src "libresoc.v:126747.9-126747.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:559" + switch \jtag_wb_datasr_shift + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\jtag_wb_datasr_reg$next[63:0]$5548 { \TAP_bus__tdi \jtag_wb_datasr_reg [63:1] } + case + assign $1\jtag_wb_datasr_reg$next[63:0]$5548 \jtag_wb_datasr_reg + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:561" + switch \jtag_wb_datasr_capture + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\jtag_wb_datasr_reg$next[63:0]$5549 \jtag_wb_datasr__i + case + assign $2\jtag_wb_datasr_reg$next[63:0]$5549 $1\jtag_wb_datasr_reg$next[63:0]$5548 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \posjtag_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\jtag_wb_datasr_reg$next[63:0]$5550 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $3\jtag_wb_datasr_reg$next[63:0]$5550 $2\jtag_wb_datasr_reg$next[63:0]$5549 + end + sync always + update \jtag_wb_datasr_reg$next $0\jtag_wb_datasr_reg$next[63:0]$5547 + end + attribute \src "libresoc.v:126767.3-126775.6" + process $proc$libresoc.v:126767$5551 + assign { } { } + assign { } { } + assign $0\dmi0_addrsr_update_core$next[0:0]$5552 $1\dmi0_addrsr_update_core$next[0:0]$5553 + attribute \src "libresoc.v:126768.5-126768.29" + switch \initial + attribute \src "libresoc.v:126768.9-126768.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dmi0_addrsr_update_core$next[0:0]$5553 1'0 + case + assign $1\dmi0_addrsr_update_core$next[0:0]$5553 \dmi0_addrsr_update + end + sync always + update \dmi0_addrsr_update_core$next $0\dmi0_addrsr_update_core$next[0:0]$5552 + end + attribute \src "libresoc.v:126776.3-126784.6" + process $proc$libresoc.v:126776$5554 + assign { } { } + assign { } { } + assign $0\dmi0_addrsr_update_core_prev$next[0:0]$5555 $1\dmi0_addrsr_update_core_prev$next[0:0]$5556 + attribute \src "libresoc.v:126777.5-126777.29" + switch \initial + attribute \src "libresoc.v:126777.9-126777.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dmi0_addrsr_update_core_prev$next[0:0]$5556 1'0 + case + assign $1\dmi0_addrsr_update_core_prev$next[0:0]$5556 \dmi0_addrsr_update_core + end + sync always + update \dmi0_addrsr_update_core_prev$next $0\dmi0_addrsr_update_core_prev$next[0:0]$5555 + end + attribute \src "libresoc.v:126785.3-126801.6" + process $proc$libresoc.v:126785$5557 + assign { } { } + assign { } { } + assign $0\dmi0_addrsr__oe$next[0:0]$5558 $2\dmi0_addrsr__oe$next[0:0]$5560 + attribute \src "libresoc.v:126786.5-126786.29" + switch \initial + attribute \src "libresoc.v:126786.9-126786.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:553" + switch \$233 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dmi0_addrsr__oe$next[0:0]$5559 \dmi0_addrsr_isir + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\dmi0_addrsr__oe$next[0:0]$5559 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\dmi0_addrsr__oe$next[0:0]$5560 1'0 + case + assign $2\dmi0_addrsr__oe$next[0:0]$5560 $1\dmi0_addrsr__oe$next[0:0]$5559 + end + sync always + update \dmi0_addrsr__oe$next $0\dmi0_addrsr__oe$next[0:0]$5558 + end + attribute \src "libresoc.v:126802.3-126822.6" + process $proc$libresoc.v:126802$5561 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\dmi0_addrsr_reg$next[7:0]$5562 $3\dmi0_addrsr_reg$next[7:0]$5565 + attribute \src "libresoc.v:126803.5-126803.29" + switch \initial + attribute \src "libresoc.v:126803.9-126803.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:559" + switch \dmi0_addrsr_shift + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dmi0_addrsr_reg$next[7:0]$5563 { \TAP_bus__tdi \dmi0_addrsr_reg [7:1] } + case + assign $1\dmi0_addrsr_reg$next[7:0]$5563 \dmi0_addrsr_reg + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:561" + switch \dmi0_addrsr_capture + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\dmi0_addrsr_reg$next[7:0]$5564 \dmi0_addrsr__i + case + assign $2\dmi0_addrsr_reg$next[7:0]$5564 $1\dmi0_addrsr_reg$next[7:0]$5563 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \posjtag_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\dmi0_addrsr_reg$next[7:0]$5565 8'00000000 + case + assign $3\dmi0_addrsr_reg$next[7:0]$5565 $2\dmi0_addrsr_reg$next[7:0]$5564 + end + sync always + update \dmi0_addrsr_reg$next $0\dmi0_addrsr_reg$next[7:0]$5562 + end + attribute \src "libresoc.v:126823.3-126831.6" + process $proc$libresoc.v:126823$5566 + assign { } { } + assign { } { } + assign $0\dmi0_datasr_update_core$next[0:0]$5567 $1\dmi0_datasr_update_core$next[0:0]$5568 + attribute \src "libresoc.v:126824.5-126824.29" + switch \initial + attribute \src "libresoc.v:126824.9-126824.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dmi0_datasr_update_core$next[0:0]$5568 1'0 + case + assign $1\dmi0_datasr_update_core$next[0:0]$5568 \dmi0_datasr_update + end + sync always + update \dmi0_datasr_update_core$next $0\dmi0_datasr_update_core$next[0:0]$5567 + end + connect \$9 $eq$libresoc.v:125917$5264_Y + connect \$99 $ternary$libresoc.v:125918$5265_Y + connect \$101 $ternary$libresoc.v:125919$5266_Y + connect \$103 $ternary$libresoc.v:125920$5267_Y + connect \$105 $ternary$libresoc.v:125921$5268_Y + connect \$107 $ternary$libresoc.v:125922$5269_Y + connect \$109 $ternary$libresoc.v:125923$5270_Y + connect \$111 $ternary$libresoc.v:125924$5271_Y + connect \$113 $ternary$libresoc.v:125925$5272_Y + connect \$115 $ternary$libresoc.v:125926$5273_Y + connect \$117 $ternary$libresoc.v:125927$5274_Y + connect \$11 $eq$libresoc.v:125928$5275_Y + connect \$119 $ternary$libresoc.v:125929$5276_Y + connect \$121 $ternary$libresoc.v:125930$5277_Y + connect \$123 $ternary$libresoc.v:125931$5278_Y + connect \$125 $ternary$libresoc.v:125932$5279_Y + connect \$127 $ternary$libresoc.v:125933$5280_Y + connect \$129 $ternary$libresoc.v:125934$5281_Y + connect \$131 $ternary$libresoc.v:125935$5282_Y + connect \$133 $ternary$libresoc.v:125936$5283_Y + connect \$135 $ternary$libresoc.v:125937$5284_Y + connect \$137 $ternary$libresoc.v:125938$5285_Y + connect \$13 $or$libresoc.v:125939$5286_Y + connect \$139 $ternary$libresoc.v:125940$5287_Y + connect \$141 $eq$libresoc.v:125941$5288_Y + connect \$143 $eq$libresoc.v:125942$5289_Y + connect \$145 $or$libresoc.v:125943$5290_Y + connect \$147 $and$libresoc.v:125944$5291_Y + connect \$149 $eq$libresoc.v:125945$5292_Y + connect \$151 $eq$libresoc.v:125946$5293_Y + connect \$153 $or$libresoc.v:125947$5294_Y + connect \$155 $eq$libresoc.v:125948$5295_Y + connect \$157 $or$libresoc.v:125949$5296_Y + connect \$15 $eq$libresoc.v:125950$5297_Y + connect \$159 $and$libresoc.v:125951$5298_Y + connect \$161 $eq$libresoc.v:125952$5299_Y + connect \$163 $ne$libresoc.v:125953$5300_Y + connect \$165 $and$libresoc.v:125954$5301_Y + connect \$167 $ne$libresoc.v:125955$5302_Y + connect \$169 $and$libresoc.v:125956$5303_Y + connect \$171 $ne$libresoc.v:125957$5304_Y + connect \$173 $and$libresoc.v:125958$5305_Y + connect \$175 $not$libresoc.v:125959$5306_Y + connect \$177 $and$libresoc.v:125960$5307_Y + connect \$17 $or$libresoc.v:125961$5308_Y + connect \$179 $eq$libresoc.v:125962$5309_Y + connect \$181 $ne$libresoc.v:125963$5310_Y + connect \$183 $and$libresoc.v:125964$5311_Y + connect \$185 $ne$libresoc.v:125965$5312_Y + connect \$187 $and$libresoc.v:125966$5313_Y + connect \$189 $ne$libresoc.v:125967$5314_Y + connect \$191 $and$libresoc.v:125968$5315_Y + connect \$193 $not$libresoc.v:125969$5316_Y + connect \$195 $and$libresoc.v:125970$5317_Y + connect \$197 $eq$libresoc.v:125971$5318_Y + connect \$1 $eq$libresoc.v:125972$5319_Y + connect \$19 $and$libresoc.v:125973$5320_Y + connect \$199 $eq$libresoc.v:125974$5321_Y + connect \$201 $ne$libresoc.v:125975$5322_Y + connect \$203 $and$libresoc.v:125976$5323_Y + connect \$205 $ne$libresoc.v:125977$5324_Y + connect \$207 $and$libresoc.v:125978$5325_Y + connect \$209 $ne$libresoc.v:125979$5326_Y + connect \$211 $and$libresoc.v:125980$5327_Y + connect \$213 $not$libresoc.v:125981$5328_Y + connect \$215 $and$libresoc.v:125982$5329_Y + connect \$217 $eq$libresoc.v:125983$5330_Y + connect \$21 $and$libresoc.v:125984$5331_Y + connect \$219 $ne$libresoc.v:125985$5332_Y + connect \$221 $and$libresoc.v:125986$5333_Y + connect \$223 $ne$libresoc.v:125987$5334_Y + connect \$225 $and$libresoc.v:125988$5335_Y + connect \$227 $ne$libresoc.v:125989$5336_Y + connect \$229 $and$libresoc.v:125990$5337_Y + connect \$231 $not$libresoc.v:125991$5338_Y + connect \$233 $and$libresoc.v:125992$5339_Y + connect \$235 $eq$libresoc.v:125993$5340_Y + connect \$237 $eq$libresoc.v:125994$5341_Y + connect \$23 $eq$libresoc.v:125995$5342_Y + connect \$239 $ne$libresoc.v:125996$5343_Y + connect \$241 $and$libresoc.v:125997$5344_Y + connect \$243 $ne$libresoc.v:125998$5345_Y + connect \$245 $and$libresoc.v:125999$5346_Y + connect \$247 $ne$libresoc.v:126000$5347_Y + connect \$249 $and$libresoc.v:126001$5348_Y + connect \$251 $not$libresoc.v:126002$5349_Y + connect \$253 $and$libresoc.v:126003$5350_Y + connect \$256 $eq$libresoc.v:126004$5351_Y + connect \$255 $not$libresoc.v:126005$5352_Y + connect \$25 $eq$libresoc.v:126006$5353_Y + connect \$259 $eq$libresoc.v:126007$5354_Y + connect \$261 $eq$libresoc.v:126008$5355_Y + connect \$263 $or$libresoc.v:126009$5356_Y + connect \$265 $eq$libresoc.v:126010$5357_Y + connect \$268 $add$libresoc.v:126011$5358_Y + connect \$271 $add$libresoc.v:126012$5359_Y + connect \$273 $pos$libresoc.v:126013$5361_Y + connect \$276 $eq$libresoc.v:126014$5362_Y + connect \$278 $eq$libresoc.v:126015$5363_Y + connect \$27 $or$libresoc.v:126016$5364_Y + connect \$280 $or$libresoc.v:126017$5365_Y + connect \$282 $eq$libresoc.v:126018$5366_Y + connect \$285 $add$libresoc.v:126019$5367_Y + connect \$288 $add$libresoc.v:126020$5368_Y + connect \$29 $eq$libresoc.v:126021$5369_Y + connect \$31 $or$libresoc.v:126022$5370_Y + connect \$33 $and$libresoc.v:126023$5371_Y + connect \$35 $and$libresoc.v:126024$5372_Y + connect \$37 $eq$libresoc.v:126025$5373_Y + connect \$3 $eq$libresoc.v:126026$5374_Y + connect \$39 $eq$libresoc.v:126027$5375_Y + connect \$41 $ternary$libresoc.v:126028$5376_Y + connect \$43 $ternary$libresoc.v:126029$5377_Y + connect \$45 $ternary$libresoc.v:126030$5378_Y + connect \$47 $ternary$libresoc.v:126031$5379_Y + connect \$49 $ternary$libresoc.v:126032$5380_Y + connect \$51 $ternary$libresoc.v:126033$5381_Y + connect \$53 $ternary$libresoc.v:126034$5382_Y + connect \$55 $ternary$libresoc.v:126035$5383_Y + connect \$57 $ternary$libresoc.v:126036$5384_Y + connect \$5 $or$libresoc.v:126037$5385_Y + connect \$59 $ternary$libresoc.v:126038$5386_Y + connect \$61 $ternary$libresoc.v:126039$5387_Y + connect \$63 $ternary$libresoc.v:126040$5388_Y + connect \$65 $ternary$libresoc.v:126041$5389_Y + connect \$67 $ternary$libresoc.v:126042$5390_Y + connect \$69 $ternary$libresoc.v:126043$5391_Y + connect \$71 $ternary$libresoc.v:126044$5392_Y + connect \$73 $ternary$libresoc.v:126045$5393_Y + connect \$75 $ternary$libresoc.v:126046$5394_Y + connect \$77 $ternary$libresoc.v:126047$5395_Y + connect \$7 $and$libresoc.v:126048$5396_Y + connect \$79 $ternary$libresoc.v:126049$5397_Y + connect \$81 $ternary$libresoc.v:126050$5398_Y + connect \$83 $ternary$libresoc.v:126051$5399_Y + connect \$85 $ternary$libresoc.v:126052$5400_Y + connect \$87 $ternary$libresoc.v:126053$5401_Y + connect \$89 $ternary$libresoc.v:126054$5402_Y + connect \$91 $ternary$libresoc.v:126055$5403_Y + connect \$93 $ternary$libresoc.v:126056$5404_Y + connect \$95 $ternary$libresoc.v:126057$5405_Y + connect \$97 $ternary$libresoc.v:126058$5406_Y + connect \$267 \$268 + connect \$270 \$271 + connect \$284 \$285 + connect \$287 \$288 + connect \sr0__i \sr0__o + connect \dmi0_we_i \$282 + connect \dmi0_req_i \$280 + connect \dmi0_addrsr__i \$273 + connect \jtag_wb__we \$265 + connect \jtag_wb__stb \$263 + connect \jtag_wb__cyc \$255 + connect \jtag_wb__sel 1'1 + connect \jtag_wb_addrsr__i \jtag_wb__adr + connect \dmi0_datasr_update \$249 + connect \dmi0_datasr_shift \$245 + connect \dmi0_datasr_capture \$241 + connect \dmi0_datasr_isir { \$237 \$235 } + connect \dmi0_datasr__o \dmi0_datasr_reg + connect \dmi0_addrsr_update \$229 + connect \dmi0_addrsr_shift \$225 + connect \dmi0_addrsr_capture \$221 + connect \dmi0_addrsr_isir \$217 + connect \dmi0_addrsr__o \dmi0_addrsr_reg + connect \jtag_wb_datasr_update \$211 + connect \jtag_wb_datasr_shift \$207 + connect \jtag_wb_datasr_capture \$203 + connect \jtag_wb_datasr_isir { \$199 \$197 } + connect \jtag_wb_datasr__o \jtag_wb_datasr_reg + connect \jtag_wb_addrsr_update \$191 + connect \jtag_wb_addrsr_shift \$187 + connect \jtag_wb_addrsr_capture \$183 + connect \jtag_wb_addrsr_isir \$179 + connect \jtag_wb_addrsr__o \jtag_wb_addrsr_reg + connect \sr0_update \$173 + connect \sr0_shift \$169 + connect \sr0_capture \$165 + connect \sr0_isir \$161 + connect \sr0__o \sr0_reg + connect \gpio_gpio15__pad__oe \$139 + connect \gpio_gpio15__pad__o \$137 + connect \gpio_gpio15__core__i \$135 + connect \gpio_gpio14__pad__oe \$133 + connect \gpio_gpio14__pad__o \$131 + connect \gpio_gpio14__core__i \$129 + connect \gpio_gpio13__pad__oe \$127 + connect \gpio_gpio13__pad__o \$125 + connect \gpio_gpio13__core__i \$123 + connect \gpio_gpio12__pad__oe \$121 + connect \gpio_gpio12__pad__o \$119 + connect \gpio_gpio12__core__i \$117 + connect \gpio_gpio11__pad__oe \$115 + connect \gpio_gpio11__pad__o \$113 + connect \gpio_gpio11__core__i \$111 + connect \gpio_gpio10__pad__oe \$109 + connect \gpio_gpio10__pad__o \$107 + connect \gpio_gpio10__core__i \$105 + connect \gpio_gpio9__pad__oe \$103 + connect \gpio_gpio9__pad__o \$101 + connect \gpio_gpio9__core__i \$99 + connect \gpio_gpio8__pad__oe \$97 + connect \gpio_gpio8__pad__o \$95 + connect \gpio_gpio8__core__i \$93 + connect \gpio_gpio7__pad__oe \$91 + connect \gpio_gpio7__pad__o \$89 + connect \gpio_gpio7__core__i \$87 + connect \gpio_gpio6__pad__oe \$85 + connect \gpio_gpio6__pad__o \$83 + connect \gpio_gpio6__core__i \$81 + connect \gpio_gpio5__pad__oe \$79 + connect \gpio_gpio5__pad__o \$77 + connect \gpio_gpio5__core__i \$75 + connect \gpio_gpio4__pad__oe \$73 + connect \gpio_gpio4__pad__o \$71 + connect \gpio_gpio4__core__i \$69 + connect \gpio_gpio3__pad__oe \$67 + connect \gpio_gpio3__pad__o \$65 + connect \gpio_gpio3__core__i \$63 + connect \gpio_gpio2__pad__oe \$61 + connect \gpio_gpio2__pad__o \$59 + connect \gpio_gpio2__core__i \$57 + connect \gpio_gpio1__pad__oe \$55 + connect \gpio_gpio1__pad__o \$53 + connect \gpio_gpio1__core__i \$51 + connect \gpio_gpio0__pad__oe \$49 + connect \gpio_gpio0__pad__o \$47 + connect \gpio_gpio0__core__i \$45 + connect \uart_rx__core__i \$43 + connect \uart_tx__pad__o \$41 + connect \io_bd2core \$39 + connect \io_bd2io \$37 + connect \io_update \$35 + connect \io_shift \$21 + connect \io_capture \$7 +end +attribute \src "libresoc.v:126929.1-127094.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.l0" +attribute \generator "nMigen" +module \l0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 23 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire input 15 \dbus__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 45 output 20 \dbus__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire output 14 \dbus__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 64 input 19 \dbus__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 64 output 22 \dbus__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire input 16 \dbus__err + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 8 output 18 \dbus__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire output 17 \dbus__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire output 21 \dbus__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:110" + wire output 8 \ldst_port0_addr_exc_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 96 input 6 \ldst_port0_addr_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire input 7 \ldst_port0_addr_i_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:109" + wire output 9 \ldst_port0_addr_ok_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:105" + wire output 2 \ldst_port0_busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102" + wire width 4 input 5 \ldst_port0_data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:98" + wire input 3 \ldst_port0_is_ld_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" + wire input 4 \ldst_port0_is_st_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 10 \ldst_port0_ld_data_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 11 \ldst_port0_ld_data_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 input 12 \ldst_port0_st_data_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire input 13 \ldst_port0_st_data_i_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:110" + wire \pimem_ldst_port0_addr_exc_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 48 \pimem_ldst_port0_addr_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \pimem_ldst_port0_addr_i_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:109" + wire \pimem_ldst_port0_addr_ok_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:105" + wire \pimem_ldst_port0_busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102" + wire width 4 \pimem_ldst_port0_data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:98" + wire \pimem_ldst_port0_is_ld_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" + wire \pimem_ldst_port0_is_st_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \pimem_ldst_port0_ld_data_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \pimem_ldst_port0_ld_data_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \pimem_ldst_port0_st_data_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \pimem_ldst_port0_st_data_i_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:62" + wire width 64 \pimem_m_ld_data_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:54" + wire \pimem_m_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:43" + wire width 48 \pimem_x_addr_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:59" + wire \pimem_x_busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:45" + wire \pimem_x_ld_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:44" + wire width 8 \pimem_x_mask_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:47" + wire width 64 \pimem_x_st_data_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:46" + wire \pimem_x_st_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:50" + wire \pimem_x_valid_i + attribute \module_not_derived 1 + attribute \src "libresoc.v:127018.12-127045.4" + cell \l0$127 \l0 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \ldst_port0_addr_exc_o \ldst_port0_addr_exc_o + connect \ldst_port0_addr_exc_o$12 \pimem_ldst_port0_addr_exc_o + connect \ldst_port0_addr_i \ldst_port0_addr_i + connect \ldst_port0_addr_i$5 \pimem_ldst_port0_addr_i + connect \ldst_port0_addr_i_ok \ldst_port0_addr_i_ok + connect \ldst_port0_addr_i_ok$6 \pimem_ldst_port0_addr_i_ok + connect \ldst_port0_addr_ok_o \ldst_port0_addr_ok_o + connect \ldst_port0_addr_ok_o$7 \pimem_ldst_port0_addr_ok_o + connect \ldst_port0_busy_o \ldst_port0_busy_o + connect \ldst_port0_busy_o$3 \pimem_ldst_port0_busy_o + connect \ldst_port0_data_len \ldst_port0_data_len + connect \ldst_port0_data_len$4 \pimem_ldst_port0_data_len + connect \ldst_port0_is_ld_i \ldst_port0_is_ld_i + connect \ldst_port0_is_ld_i$1 \pimem_ldst_port0_is_ld_i + connect \ldst_port0_is_st_i \ldst_port0_is_st_i + connect \ldst_port0_is_st_i$2 \pimem_ldst_port0_is_st_i + connect \ldst_port0_ld_data_o \ldst_port0_ld_data_o + connect \ldst_port0_ld_data_o$8 \pimem_ldst_port0_ld_data_o + connect \ldst_port0_ld_data_o_ok \ldst_port0_ld_data_o_ok + connect \ldst_port0_ld_data_o_ok$9 \pimem_ldst_port0_ld_data_o_ok + connect \ldst_port0_st_data_i \ldst_port0_st_data_i + connect \ldst_port0_st_data_i$11 \pimem_ldst_port0_st_data_i + connect \ldst_port0_st_data_i_ok \ldst_port0_st_data_i_ok + connect \ldst_port0_st_data_i_ok$10 \pimem_ldst_port0_st_data_i_ok + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:127046.9-127067.4" + cell \lsmem \lsmem + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \dbus__ack \dbus__ack + connect \dbus__adr \dbus__adr + connect \dbus__cyc \dbus__cyc + connect \dbus__dat_r \dbus__dat_r + connect \dbus__dat_w \dbus__dat_w + connect \dbus__err \dbus__err + connect \dbus__sel \dbus__sel + connect \dbus__stb \dbus__stb + connect \dbus__we \dbus__we + connect \m_ld_data_o \pimem_m_ld_data_o + connect \m_valid_i \pimem_m_valid_i + connect \x_addr_i \pimem_x_addr_i + connect \x_busy_o \pimem_x_busy_o + connect \x_ld_i \pimem_x_ld_i + connect \x_mask_i \pimem_x_mask_i + connect \x_st_data_i \pimem_x_st_data_i + connect \x_st_i \pimem_x_st_i + connect \x_valid_i \pimem_x_valid_i + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:127068.9-127092.4" + cell \pimem \pimem + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \ldst_port0_addr_exc_o \pimem_ldst_port0_addr_exc_o + connect \ldst_port0_addr_i \pimem_ldst_port0_addr_i + connect \ldst_port0_addr_i_ok \pimem_ldst_port0_addr_i_ok + connect \ldst_port0_addr_ok_o \pimem_ldst_port0_addr_ok_o + connect \ldst_port0_busy_o \pimem_ldst_port0_busy_o + connect \ldst_port0_data_len \pimem_ldst_port0_data_len + connect \ldst_port0_is_ld_i \pimem_ldst_port0_is_ld_i + connect \ldst_port0_is_st_i \pimem_ldst_port0_is_st_i + connect \ldst_port0_ld_data_o \pimem_ldst_port0_ld_data_o + connect \ldst_port0_ld_data_o_ok \pimem_ldst_port0_ld_data_o_ok + connect \ldst_port0_st_data_i \pimem_ldst_port0_st_data_i + connect \ldst_port0_st_data_i_ok \pimem_ldst_port0_st_data_i_ok + connect \m_ld_data_o \pimem_m_ld_data_o + connect \m_valid_i \pimem_m_valid_i + connect \x_addr_i \pimem_x_addr_i + connect \x_busy_o \pimem_x_busy_o + connect \x_ld_i \pimem_x_ld_i + connect \x_mask_i \pimem_x_mask_i + connect \x_st_data_i \pimem_x_st_data_i + connect \x_st_i \pimem_x_st_i + connect \x_valid_i \pimem_x_valid_i + end + connect \pimem_ldst_port0_addr_exc_o 1'0 +end +attribute \src "libresoc.v:127098.1-127412.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.l0.l0" +attribute \generator "nMigen" +module \l0$127 + attribute \src "libresoc.v:127307.3-127321.6" + wire $0\idx_l$16$next[0:0]$5624 + attribute \src "libresoc.v:127214.3-127215.35" + wire $0\idx_l$16[0:0]$5607 + attribute \src "libresoc.v:127119.7-127119.24" + wire $0\idx_l$16[0:0]$5643 + attribute \src "libresoc.v:127322.3-127331.6" + wire $0\idx_l_r_idx_l[0:0] + attribute \src "libresoc.v:127332.3-127341.6" + wire $0\idx_l_s_idx_l[0:0] + attribute \src "libresoc.v:127099.7-127099.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:127297.3-127306.6" + wire $0\ldst_port0_addr_exc_o[0:0] + attribute \src "libresoc.v:127235.3-127244.6" + wire width 48 $0\ldst_port0_addr_i$5[47:0]$5609 + attribute \src "libresoc.v:127245.3-127254.6" + wire $0\ldst_port0_addr_i_ok$6[0:0]$5612 + attribute \src "libresoc.v:127287.3-127296.6" + wire $0\ldst_port0_addr_ok_o[0:0] + attribute \src "libresoc.v:127277.3-127286.6" + wire $0\ldst_port0_busy_o[0:0] + attribute \src "libresoc.v:127387.3-127396.6" + wire width 4 $0\ldst_port0_data_len$4[3:0]$5638 + attribute \src "libresoc.v:127397.3-127406.6" + wire $0\ldst_port0_go_die_i[0:0] + attribute \src "libresoc.v:127367.3-127376.6" + wire $0\ldst_port0_is_ld_i$1[0:0]$5632 + attribute \src "libresoc.v:127377.3-127386.6" + wire $0\ldst_port0_is_st_i$2[0:0]$5635 + attribute \src "libresoc.v:127266.3-127276.6" + wire width 64 $0\ldst_port0_ld_data_o[63:0] + attribute \src "libresoc.v:127266.3-127276.6" + wire $0\ldst_port0_ld_data_o_ok[0:0] + attribute \src "libresoc.v:127255.3-127265.6" + wire width 64 $0\ldst_port0_st_data_i$11[63:0]$5615 + attribute \src "libresoc.v:127255.3-127265.6" + wire $0\ldst_port0_st_data_i_ok$10[0:0]$5616 + attribute \src "libresoc.v:127212.3-127213.36" + wire $0\reset_delay[0:0] + attribute \src "libresoc.v:127357.3-127366.6" + wire $0\reset_l_r_reset[0:0] + attribute \src "libresoc.v:127342.3-127356.6" + wire $0\reset_l_s_reset[0:0] + attribute \src "libresoc.v:127307.3-127321.6" + wire $1\idx_l$16$next[0:0]$5625 + attribute \src "libresoc.v:127322.3-127331.6" + wire $1\idx_l_r_idx_l[0:0] + attribute \src "libresoc.v:127332.3-127341.6" + wire $1\idx_l_s_idx_l[0:0] + attribute \src "libresoc.v:127297.3-127306.6" + wire $1\ldst_port0_addr_exc_o[0:0] + attribute \src "libresoc.v:127235.3-127244.6" + wire width 48 $1\ldst_port0_addr_i$5[47:0]$5610 + attribute \src "libresoc.v:127245.3-127254.6" + wire $1\ldst_port0_addr_i_ok$6[0:0]$5613 + attribute \src "libresoc.v:127287.3-127296.6" + wire $1\ldst_port0_addr_ok_o[0:0] + attribute \src "libresoc.v:127277.3-127286.6" + wire $1\ldst_port0_busy_o[0:0] + attribute \src "libresoc.v:127387.3-127396.6" + wire width 4 $1\ldst_port0_data_len$4[3:0]$5639 + attribute \src "libresoc.v:127397.3-127406.6" + wire $1\ldst_port0_go_die_i[0:0] + attribute \src "libresoc.v:127367.3-127376.6" + wire $1\ldst_port0_is_ld_i$1[0:0]$5633 + attribute \src "libresoc.v:127377.3-127386.6" + wire $1\ldst_port0_is_st_i$2[0:0]$5636 + attribute \src "libresoc.v:127266.3-127276.6" + wire width 64 $1\ldst_port0_ld_data_o[63:0] + attribute \src "libresoc.v:127266.3-127276.6" + wire $1\ldst_port0_ld_data_o_ok[0:0] + attribute \src "libresoc.v:127255.3-127265.6" + wire width 64 $1\ldst_port0_st_data_i$11[63:0]$5617 + attribute \src "libresoc.v:127255.3-127265.6" + wire $1\ldst_port0_st_data_i_ok$10[0:0]$5618 + attribute \src "libresoc.v:127199.7-127199.25" + wire $1\reset_delay[0:0] + attribute \src "libresoc.v:127357.3-127366.6" + wire $1\reset_l_r_reset[0:0] + attribute \src "libresoc.v:127342.3-127356.6" + wire $1\reset_l_s_reset[0:0] + attribute \src "libresoc.v:127307.3-127321.6" + wire $2\idx_l$16$next[0:0]$5626 + attribute \src "libresoc.v:127342.3-127356.6" + wire $2\reset_l_s_reset[0:0] + attribute \src "libresoc.v:127210.18-127210.103" + wire $not$libresoc.v:127210$5603_Y + attribute \src "libresoc.v:127211.18-127211.117" + wire $not$libresoc.v:127211$5604_Y + attribute \src "libresoc.v:127208.18-127208.134" + wire $or$libresoc.v:127208$5601_Y + attribute \src "libresoc.v:127209.18-127209.120" + wire $ternary$libresoc.v:127209$5602_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:262" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire \$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:278" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:288" + wire \$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:128" + wire width 96 \$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:128" + wire width 96 \$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 26 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire \idx_l$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire \idx_l$16$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire \idx_l_q_idx_l + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \idx_l_r_idx_l + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \idx_l_s_idx_l + attribute \src "libresoc.v:127099.7-127099.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:110" + wire output 8 \ldst_port0_addr_exc_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:110" + wire input 25 \ldst_port0_addr_exc_o$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 96 input 6 \ldst_port0_addr_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 48 output 18 \ldst_port0_addr_i$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire input 7 \ldst_port0_addr_i_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 19 \ldst_port0_addr_i_ok$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:109" + wire output 9 \ldst_port0_addr_ok_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:109" + wire input 20 \ldst_port0_addr_ok_o$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:105" + wire output 2 \ldst_port0_busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:105" + wire input 16 \ldst_port0_busy_o$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102" + wire width 4 input 5 \ldst_port0_data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102" + wire width 4 output 17 \ldst_port0_data_len$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:106" + wire \ldst_port0_go_die_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:106" + wire \ldst_port0_go_die_i$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:98" + wire input 3 \ldst_port0_is_ld_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:98" + wire output 14 \ldst_port0_is_ld_i$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" + wire input 4 \ldst_port0_is_st_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" + wire output 15 \ldst_port0_is_st_i$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 10 \ldst_port0_ld_data_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 input 21 \ldst_port0_ld_data_o$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 11 \ldst_port0_ld_data_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire input 22 \ldst_port0_ld_data_o_ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 input 12 \ldst_port0_st_data_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 24 \ldst_port0_st_data_i$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire input 13 \ldst_port0_st_data_i_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 23 \ldst_port0_st_data_i_ok$10 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire \pick_i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire \pick_n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire \pick_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:292" + wire \reset_delay + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:292" + wire \reset_delay$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire \reset_l_q_reset + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \reset_l_r_reset + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \reset_l_s_reset + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:278" + cell $not $not$libresoc.v:127210$5603 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \pick_n + connect \Y $not$libresoc.v:127210$5603_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:288" + cell $not $not$libresoc.v:127211$5604 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ldst_port0_busy_o$3 + connect \Y $not$libresoc.v:127211$5604_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:262" + cell $or $or$libresoc.v:127208$5601 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ldst_port0_is_ld_i + connect \B \ldst_port0_is_st_i + connect \Y $or$libresoc.v:127208$5601_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $ternary$libresoc.v:127209$5602 + parameter \WIDTH 1 + connect \A \idx_l$16 + connect \B \pick_o + connect \S \idx_l_q_idx_l + connect \Y $ternary$libresoc.v:127209$5602_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:127216.9-127222.4" + cell \idx_l \idx_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_idx_l \idx_l_q_idx_l + connect \r_idx_l \idx_l_r_idx_l + connect \s_idx_l \idx_l_s_idx_l + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:127223.8-127227.4" + cell \pick \pick + connect \i \pick_i + connect \n \pick_n + connect \o \pick_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:127228.17-127234.4" + cell \reset_l$128 \reset_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_reset \reset_l_q_reset + connect \r_reset \reset_l_r_reset + connect \s_reset \reset_l_s_reset + end + attribute \src "libresoc.v:127099.7-127099.20" + process $proc$libresoc.v:127099$5641 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:127119.7-127119.24" + process $proc$libresoc.v:127119$5642 + assign { } { } + assign $0\idx_l$16[0:0]$5643 1'0 + sync always + sync init + update \idx_l$16 $0\idx_l$16[0:0]$5643 + end + attribute \src "libresoc.v:127199.7-127199.25" + process $proc$libresoc.v:127199$5644 + assign { } { } + assign $1\reset_delay[0:0] 1'0 + sync always + sync init + update \reset_delay $1\reset_delay[0:0] + end + attribute \src "libresoc.v:127212.3-127213.36" + process $proc$libresoc.v:127212$5605 + assign { } { } + assign $0\reset_delay[0:0] \reset_l_q_reset + sync posedge \coresync_clk + update \reset_delay $0\reset_delay[0:0] + end + attribute \src "libresoc.v:127214.3-127215.35" + process $proc$libresoc.v:127214$5606 + assign { } { } + assign $0\idx_l$16[0:0]$5607 \idx_l$16$next + sync posedge \coresync_clk + update \idx_l$16 $0\idx_l$16[0:0]$5607 + end + attribute \src "libresoc.v:127235.3-127244.6" + process $proc$libresoc.v:127235$5608 + assign { } { } + assign { } { } + assign $0\ldst_port0_addr_i$5[47:0]$5609 $1\ldst_port0_addr_i$5[47:0]$5610 + attribute \src "libresoc.v:127236.5-127236.29" + switch \initial + attribute \src "libresoc.v:127236.9-127236.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" + switch \idx_l_q_idx_l + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ldst_port0_addr_i$5[47:0]$5610 \$25 [47:0] + case + assign $1\ldst_port0_addr_i$5[47:0]$5610 48'000000000000000000000000000000000000000000000000 + end + sync always + update \ldst_port0_addr_i$5 $0\ldst_port0_addr_i$5[47:0]$5609 + end + attribute \src "libresoc.v:127245.3-127254.6" + process $proc$libresoc.v:127245$5611 + assign { } { } + assign { } { } + assign $0\ldst_port0_addr_i_ok$6[0:0]$5612 $1\ldst_port0_addr_i_ok$6[0:0]$5613 + attribute \src "libresoc.v:127246.5-127246.29" + switch \initial + attribute \src "libresoc.v:127246.9-127246.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" + switch \idx_l_q_idx_l + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ldst_port0_addr_i_ok$6[0:0]$5613 \ldst_port0_addr_i_ok + case + assign $1\ldst_port0_addr_i_ok$6[0:0]$5613 1'0 + end + sync always + update \ldst_port0_addr_i_ok$6 $0\ldst_port0_addr_i_ok$6[0:0]$5612 + end + attribute \src "libresoc.v:127255.3-127265.6" + process $proc$libresoc.v:127255$5614 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\ldst_port0_st_data_i$11[63:0]$5615 $1\ldst_port0_st_data_i$11[63:0]$5617 + assign $0\ldst_port0_st_data_i_ok$10[0:0]$5616 $1\ldst_port0_st_data_i_ok$10[0:0]$5618 + attribute \src "libresoc.v:127256.5-127256.29" + switch \initial + attribute \src "libresoc.v:127256.9-127256.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" + switch \idx_l_q_idx_l + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\ldst_port0_st_data_i_ok$10[0:0]$5618 $1\ldst_port0_st_data_i$11[63:0]$5617 } { \ldst_port0_st_data_i_ok \ldst_port0_st_data_i } + case + assign $1\ldst_port0_st_data_i$11[63:0]$5617 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\ldst_port0_st_data_i_ok$10[0:0]$5618 1'0 + end + sync always + update \ldst_port0_st_data_i$11 $0\ldst_port0_st_data_i$11[63:0]$5615 + update \ldst_port0_st_data_i_ok$10 $0\ldst_port0_st_data_i_ok$10[0:0]$5616 + end + attribute \src "libresoc.v:127266.3-127276.6" + process $proc$libresoc.v:127266$5619 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\ldst_port0_ld_data_o[63:0] $1\ldst_port0_ld_data_o[63:0] + assign $0\ldst_port0_ld_data_o_ok[0:0] $1\ldst_port0_ld_data_o_ok[0:0] + attribute \src "libresoc.v:127267.5-127267.29" + switch \initial + attribute \src "libresoc.v:127267.9-127267.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" + switch \idx_l_q_idx_l + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\ldst_port0_ld_data_o_ok[0:0] $1\ldst_port0_ld_data_o[63:0] } { \ldst_port0_ld_data_o_ok$9 \ldst_port0_ld_data_o$8 } + case + assign $1\ldst_port0_ld_data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\ldst_port0_ld_data_o_ok[0:0] 1'0 + end + sync always + update \ldst_port0_ld_data_o $0\ldst_port0_ld_data_o[63:0] + update \ldst_port0_ld_data_o_ok $0\ldst_port0_ld_data_o_ok[0:0] + end + attribute \src "libresoc.v:127277.3-127286.6" + process $proc$libresoc.v:127277$5620 + assign { } { } + assign { } { } + assign $0\ldst_port0_busy_o[0:0] $1\ldst_port0_busy_o[0:0] + attribute \src "libresoc.v:127278.5-127278.29" + switch \initial + attribute \src "libresoc.v:127278.9-127278.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" + switch \idx_l_q_idx_l + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ldst_port0_busy_o[0:0] \ldst_port0_busy_o$3 + case + assign $1\ldst_port0_busy_o[0:0] 1'0 + end + sync always + update \ldst_port0_busy_o $0\ldst_port0_busy_o[0:0] + end + attribute \src "libresoc.v:127287.3-127296.6" + process $proc$libresoc.v:127287$5621 + assign { } { } + assign { } { } + assign $0\ldst_port0_addr_ok_o[0:0] $1\ldst_port0_addr_ok_o[0:0] + attribute \src "libresoc.v:127288.5-127288.29" + switch \initial + attribute \src "libresoc.v:127288.9-127288.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" + switch \idx_l_q_idx_l + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ldst_port0_addr_ok_o[0:0] \ldst_port0_addr_ok_o$7 + case + assign $1\ldst_port0_addr_ok_o[0:0] 1'0 + end + sync always + update \ldst_port0_addr_ok_o $0\ldst_port0_addr_ok_o[0:0] + end + attribute \src "libresoc.v:127297.3-127306.6" + process $proc$libresoc.v:127297$5622 + assign { } { } + assign { } { } + assign $0\ldst_port0_addr_exc_o[0:0] $1\ldst_port0_addr_exc_o[0:0] + attribute \src "libresoc.v:127298.5-127298.29" + switch \initial + attribute \src "libresoc.v:127298.9-127298.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" + switch \idx_l_q_idx_l + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ldst_port0_addr_exc_o[0:0] \ldst_port0_addr_exc_o$12 + case + assign $1\ldst_port0_addr_exc_o[0:0] 1'0 + end + sync always + update \ldst_port0_addr_exc_o $0\ldst_port0_addr_exc_o[0:0] + end + attribute \src "libresoc.v:127307.3-127321.6" + process $proc$libresoc.v:127307$5623 + assign { } { } + assign { } { } + assign { } { } + assign $0\idx_l$16$next[0:0]$5624 $2\idx_l$16$next[0:0]$5626 + attribute \src "libresoc.v:127308.5-127308.29" + switch \initial + attribute \src "libresoc.v:127308.9-127308.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch \idx_l_q_idx_l + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\idx_l$16$next[0:0]$5625 \pick_o + case + assign $1\idx_l$16$next[0:0]$5625 \idx_l$16 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\idx_l$16$next[0:0]$5626 1'0 + case + assign $2\idx_l$16$next[0:0]$5626 $1\idx_l$16$next[0:0]$5625 + end + sync always + update \idx_l$16$next $0\idx_l$16$next[0:0]$5624 + end + attribute \src "libresoc.v:127322.3-127331.6" + process $proc$libresoc.v:127322$5627 + assign { } { } + assign { } { } + assign $0\idx_l_r_idx_l[0:0] $1\idx_l_r_idx_l[0:0] + attribute \src "libresoc.v:127323.5-127323.29" + switch \initial + attribute \src "libresoc.v:127323.9-127323.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:296" + switch \reset_l_q_reset + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\idx_l_r_idx_l[0:0] 1'1 + case + assign $1\idx_l_r_idx_l[0:0] 1'1 + end + sync always + update \idx_l_r_idx_l $0\idx_l_r_idx_l[0:0] + end + attribute \src "libresoc.v:127332.3-127341.6" + process $proc$libresoc.v:127332$5628 + assign { } { } + assign { } { } + assign $0\idx_l_s_idx_l[0:0] $1\idx_l_s_idx_l[0:0] + attribute \src "libresoc.v:127333.5-127333.29" + switch \initial + attribute \src "libresoc.v:127333.9-127333.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:278" + switch \$19 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\idx_l_s_idx_l[0:0] 1'1 + case + assign $1\idx_l_s_idx_l[0:0] 1'0 + end + sync always + update \idx_l_s_idx_l $0\idx_l_s_idx_l[0:0] + end + attribute \src "libresoc.v:127342.3-127356.6" + process $proc$libresoc.v:127342$5629 + assign { } { } + assign { } { } + assign $0\reset_l_s_reset[0:0] $1\reset_l_s_reset[0:0] + attribute \src "libresoc.v:127343.5-127343.29" + switch \initial + attribute \src "libresoc.v:127343.9-127343.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" + switch \idx_l_q_idx_l + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\reset_l_s_reset[0:0] $2\reset_l_s_reset[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:288" + switch \$21 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\reset_l_s_reset[0:0] 1'1 + case + assign $2\reset_l_s_reset[0:0] 1'0 + end + case + assign $1\reset_l_s_reset[0:0] 1'0 + end + sync always + update \reset_l_s_reset $0\reset_l_s_reset[0:0] + end + attribute \src "libresoc.v:127357.3-127366.6" + process $proc$libresoc.v:127357$5630 + assign { } { } + assign { } { } + assign $0\reset_l_r_reset[0:0] $1\reset_l_r_reset[0:0] + attribute \src "libresoc.v:127358.5-127358.29" + switch \initial + attribute \src "libresoc.v:127358.9-127358.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:296" + switch \reset_l_q_reset + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\reset_l_r_reset[0:0] 1'1 + case + assign $1\reset_l_r_reset[0:0] 1'0 + end + sync always + update \reset_l_r_reset $0\reset_l_r_reset[0:0] + end + attribute \src "libresoc.v:127367.3-127376.6" + process $proc$libresoc.v:127367$5631 + assign { } { } + assign { } { } + assign $0\ldst_port0_is_ld_i$1[0:0]$5632 $1\ldst_port0_is_ld_i$1[0:0]$5633 + attribute \src "libresoc.v:127368.5-127368.29" + switch \initial + attribute \src "libresoc.v:127368.9-127368.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" + switch \idx_l_q_idx_l + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ldst_port0_is_ld_i$1[0:0]$5633 \ldst_port0_is_ld_i + case + assign $1\ldst_port0_is_ld_i$1[0:0]$5633 1'0 + end + sync always + update \ldst_port0_is_ld_i$1 $0\ldst_port0_is_ld_i$1[0:0]$5632 + end + attribute \src "libresoc.v:127377.3-127386.6" + process $proc$libresoc.v:127377$5634 + assign { } { } + assign { } { } + assign $0\ldst_port0_is_st_i$2[0:0]$5635 $1\ldst_port0_is_st_i$2[0:0]$5636 + attribute \src "libresoc.v:127378.5-127378.29" + switch \initial + attribute \src "libresoc.v:127378.9-127378.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" + switch \idx_l_q_idx_l + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ldst_port0_is_st_i$2[0:0]$5636 \ldst_port0_is_st_i + case + assign $1\ldst_port0_is_st_i$2[0:0]$5636 1'0 + end + sync always + update \ldst_port0_is_st_i$2 $0\ldst_port0_is_st_i$2[0:0]$5635 + end + attribute \src "libresoc.v:127387.3-127396.6" + process $proc$libresoc.v:127387$5637 + assign { } { } + assign { } { } + assign $0\ldst_port0_data_len$4[3:0]$5638 $1\ldst_port0_data_len$4[3:0]$5639 + attribute \src "libresoc.v:127388.5-127388.29" + switch \initial + attribute \src "libresoc.v:127388.9-127388.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" + switch \idx_l_q_idx_l + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ldst_port0_data_len$4[3:0]$5639 \ldst_port0_data_len + case + assign $1\ldst_port0_data_len$4[3:0]$5639 4'0000 + end + sync always + update \ldst_port0_data_len$4 $0\ldst_port0_data_len$4[3:0]$5638 + end + attribute \src "libresoc.v:127397.3-127406.6" + process $proc$libresoc.v:127397$5640 + assign { } { } + assign { } { } + assign $0\ldst_port0_go_die_i[0:0] $1\ldst_port0_go_die_i[0:0] + attribute \src "libresoc.v:127398.5-127398.29" + switch \initial + attribute \src "libresoc.v:127398.9-127398.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" + switch \idx_l_q_idx_l + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ldst_port0_go_die_i[0:0] \ldst_port0_go_die_i$23 + case + assign $1\ldst_port0_go_die_i[0:0] 1'0 + end + sync always + update \ldst_port0_go_die_i $0\ldst_port0_go_die_i[0:0] + end + connect \$13 $or$libresoc.v:127208$5601_Y + connect \$17 $ternary$libresoc.v:127209$5602_Y + connect \$19 $not$libresoc.v:127210$5603_Y + connect \$21 $not$libresoc.v:127211$5604_Y + connect \$15 \$17 + connect \$25 \ldst_port0_addr_i + connect \ldst_port0_go_die_i$23 1'0 + connect \reset_delay$next \reset_l_q_reset + connect \pick_i \$13 +end +attribute \src "libresoc.v:127416.1-127474.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.l0.pimem.ld_active" +attribute \generator "nMigen" +module \ld_active + attribute \src "libresoc.v:127417.7-127417.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:127462.3-127470.6" + wire $0\q_int$next[0:0]$5655 + attribute \src "libresoc.v:127460.3-127461.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:127462.3-127470.6" + wire $1\q_int$next[0:0]$5656 + attribute \src "libresoc.v:127439.7-127439.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:127452.17-127452.96" + wire $and$libresoc.v:127452$5645_Y + attribute \src "libresoc.v:127457.17-127457.96" + wire $and$libresoc.v:127457$5650_Y + attribute \src "libresoc.v:127454.18-127454.99" + wire $not$libresoc.v:127454$5647_Y + attribute \src "libresoc.v:127456.17-127456.98" + wire $not$libresoc.v:127456$5649_Y + attribute \src "libresoc.v:127459.17-127459.98" + wire $not$libresoc.v:127459$5652_Y + attribute \src "libresoc.v:127453.18-127453.104" + wire $or$libresoc.v:127453$5646_Y + attribute \src "libresoc.v:127455.18-127455.105" + wire $or$libresoc.v:127455$5648_Y + attribute \src "libresoc.v:127458.17-127458.103" + wire $or$libresoc.v:127458$5651_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 1 \coresync_rst + attribute \src "libresoc.v:127417.7-127417.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 4 \q_ld_active + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_ld_active + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_ld_active + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 2 \r_ld_active + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 3 \s_ld_active + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$libresoc.v:127452$5645 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:127452$5645_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:127457$5650 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:127457$5650_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:127454$5647 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_ld_active + connect \Y $not$libresoc.v:127454$5647_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:127456$5649 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_ld_active + connect \Y $not$libresoc.v:127456$5649_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:127459$5652 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_ld_active + connect \Y $not$libresoc.v:127459$5652_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:127453$5646 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_ld_active + connect \Y $or$libresoc.v:127453$5646_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:127455$5648 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_ld_active + connect \B \q_int + connect \Y $or$libresoc.v:127455$5648_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:127458$5651 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_ld_active + connect \Y $or$libresoc.v:127458$5651_Y + end + attribute \src "libresoc.v:127417.7-127417.20" + process $proc$libresoc.v:127417$5657 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:127439.7-127439.19" + process $proc$libresoc.v:127439$5658 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:127460.3-127461.27" + process $proc$libresoc.v:127460$5653 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:127462.3-127470.6" + process $proc$libresoc.v:127462$5654 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$5655 $1\q_int$next[0:0]$5656 + attribute \src "libresoc.v:127463.5-127463.29" + switch \initial + attribute \src "libresoc.v:127463.9-127463.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$5656 1'0 + case + assign $1\q_int$next[0:0]$5656 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$5655 + end + connect \$9 $and$libresoc.v:127452$5645_Y + connect \$11 $or$libresoc.v:127453$5646_Y + connect \$13 $not$libresoc.v:127454$5647_Y + connect \$15 $or$libresoc.v:127455$5648_Y + connect \$1 $not$libresoc.v:127456$5649_Y + connect \$3 $and$libresoc.v:127457$5650_Y + connect \$5 $or$libresoc.v:127458$5651_Y + connect \$7 $not$libresoc.v:127459$5652_Y + connect \qlq_ld_active \$15 + connect \qn_ld_active \$13 + connect \q_ld_active \$11 +end +attribute \src "libresoc.v:127478.1-128807.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0" +attribute \generator "nMigen" +module \ldst0 + attribute \src "libresoc.v:128462.3-128470.6" + wire $0\adr_l_r_adr$next[0:0]$5801 + attribute \src "libresoc.v:128344.3-128345.39" + wire $0\adr_l_r_adr[0:0] + attribute \src "libresoc.v:128290.3-128291.21" + wire $0\alu_ok[0:0] + attribute \src "libresoc.v:128627.3-128636.6" + wire width 64 $0\dest1_o[63:0] + attribute \src "libresoc.v:128637.3-128646.6" + wire width 64 $0\dest2_o[63:0] + attribute \src "libresoc.v:128617.3-128626.6" + wire width 64 $0\ea_r$next[63:0]$5889 + attribute \src "libresoc.v:128292.3-128293.25" + wire width 64 $0\ea_r[63:0] + attribute \src "libresoc.v:127479.7-127479.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:128692.3-128711.6" + wire width 64 $0\ldd_o[63:0] + attribute \src "libresoc.v:128656.3-128679.6" + wire width 64 $0\lddata_r[63:0] + attribute \src "libresoc.v:128559.3-128568.6" + wire width 64 $0\ldo_r$next[63:0]$5874 + attribute \src "libresoc.v:128300.3-128301.27" + wire width 64 $0\ldo_r[63:0] + attribute \src "libresoc.v:128288.3-128289.33" + wire width 96 $0\ldst_port0_addr_i[95:0] + attribute \src "libresoc.v:128647.3-128655.6" + wire $0\ldst_port0_addr_i_ok$next[0:0]$5894 + attribute \src "libresoc.v:128286.3-128287.57" + wire $0\ldst_port0_addr_i_ok[0:0] + attribute \src "libresoc.v:128736.3-128747.6" + wire width 64 $0\ldst_port0_st_data_i[63:0] + attribute \src "libresoc.v:128507.3-128515.6" + wire $0\lsd_l_r_lsd$next[0:0]$5816 + attribute \src "libresoc.v:128334.3-128335.39" + wire $0\lsd_l_r_lsd[0:0] + attribute \src "libresoc.v:128435.3-128443.6" + wire $0\opc_l_r_opc$next[0:0]$5792 + attribute \src "libresoc.v:128350.3-128351.39" + wire $0\opc_l_r_opc[0:0] + attribute \src "libresoc.v:128426.3-128434.6" + wire $0\opc_l_s_opc$next[0:0]$5789 + attribute \src "libresoc.v:128352.3-128353.39" + wire $0\opc_l_s_opc[0:0] + attribute \src "libresoc.v:128516.3-128558.6" + wire $0\oper_r__byte_reverse$next[0:0]$5819 + attribute \src "libresoc.v:128326.3-128327.57" + wire $0\oper_r__byte_reverse[0:0] + attribute \src "libresoc.v:128516.3-128558.6" + wire width 4 $0\oper_r__data_len$next[3:0]$5820 + attribute \src "libresoc.v:128324.3-128325.49" + wire width 4 $0\oper_r__data_len[3:0] + attribute \src "libresoc.v:128516.3-128558.6" + wire width 12 $0\oper_r__fn_unit$next[11:0]$5821 + attribute \src "libresoc.v:128304.3-128305.47" + wire width 12 $0\oper_r__fn_unit[11:0] + attribute \src "libresoc.v:128516.3-128558.6" + wire width 64 $0\oper_r__imm_data__data$next[63:0]$5822 + attribute \src "libresoc.v:128306.3-128307.61" + wire width 64 $0\oper_r__imm_data__data[63:0] + attribute \src "libresoc.v:128516.3-128558.6" + wire $0\oper_r__imm_data__ok$next[0:0]$5823 + attribute \src "libresoc.v:128308.3-128309.57" + wire $0\oper_r__imm_data__ok[0:0] + attribute \src "libresoc.v:128516.3-128558.6" + wire width 32 $0\oper_r__insn$next[31:0]$5824 + attribute \src "libresoc.v:128332.3-128333.41" + wire width 32 $0\oper_r__insn[31:0] + attribute \src "libresoc.v:128516.3-128558.6" + wire width 7 $0\oper_r__insn_type$next[6:0]$5825 + attribute \src "libresoc.v:128302.3-128303.51" + wire width 7 $0\oper_r__insn_type[6:0] + attribute \src "libresoc.v:128516.3-128558.6" + wire $0\oper_r__is_32bit$next[0:0]$5826 + attribute \src "libresoc.v:128320.3-128321.49" + wire $0\oper_r__is_32bit[0:0] + attribute \src "libresoc.v:128516.3-128558.6" + wire $0\oper_r__is_signed$next[0:0]$5827 + attribute \src "libresoc.v:128322.3-128323.51" + wire $0\oper_r__is_signed[0:0] + attribute \src "libresoc.v:128516.3-128558.6" + wire width 2 $0\oper_r__ldst_mode$next[1:0]$5828 + attribute \src "libresoc.v:128330.3-128331.51" + wire width 2 $0\oper_r__ldst_mode[1:0] + attribute \src "libresoc.v:128516.3-128558.6" + wire $0\oper_r__oe__oe$next[0:0]$5829 + attribute \src "libresoc.v:128316.3-128317.45" + wire $0\oper_r__oe__oe[0:0] + attribute \src "libresoc.v:128516.3-128558.6" + wire $0\oper_r__oe__ok$next[0:0]$5830 + attribute \src "libresoc.v:128318.3-128319.45" + wire $0\oper_r__oe__ok[0:0] + attribute \src "libresoc.v:128516.3-128558.6" + wire $0\oper_r__rc__ok$next[0:0]$5831 + attribute \src "libresoc.v:128314.3-128315.45" + wire $0\oper_r__rc__ok[0:0] + attribute \src "libresoc.v:128516.3-128558.6" + wire $0\oper_r__rc__rc$next[0:0]$5832 + attribute \src "libresoc.v:128312.3-128313.45" + wire $0\oper_r__rc__rc[0:0] + attribute \src "libresoc.v:128516.3-128558.6" + wire $0\oper_r__sign_extend$next[0:0]$5833 + attribute \src "libresoc.v:128328.3-128329.55" + wire $0\oper_r__sign_extend[0:0] + attribute \src "libresoc.v:128516.3-128558.6" + wire $0\oper_r__zero_a$next[0:0]$5834 + attribute \src "libresoc.v:128310.3-128311.45" + wire $0\oper_r__zero_a[0:0] + attribute \src "libresoc.v:128354.3-128355.28" + wire $0\p_st_go[0:0] + attribute \src "libresoc.v:128680.3-128691.6" + wire width 64 $0\revnorev[63:0] + attribute \src "libresoc.v:128453.3-128461.6" + wire width 3 $0\src_l_r_src$next[2:0]$5798 + attribute \src "libresoc.v:128346.3-128347.39" + wire width 3 $0\src_l_r_src[2:0] + attribute \src "libresoc.v:128444.3-128452.6" + wire width 3 $0\src_l_s_src$next[2:0]$5795 + attribute \src "libresoc.v:128348.3-128349.39" + wire width 3 $0\src_l_s_src[2:0] + attribute \src "libresoc.v:128569.3-128584.6" + wire width 64 $0\src_r0$next[63:0]$5877 + attribute \src "libresoc.v:128298.3-128299.29" + wire width 64 $0\src_r0[63:0] + attribute \src "libresoc.v:128585.3-128600.6" + wire width 64 $0\src_r1$next[63:0]$5881 + attribute \src "libresoc.v:128296.3-128297.29" + wire width 64 $0\src_r1[63:0] + attribute \src "libresoc.v:128601.3-128616.6" + wire width 64 $0\src_r2$next[63:0]$5885 + attribute \src "libresoc.v:128294.3-128295.29" + wire width 64 $0\src_r2[63:0] + attribute \src "libresoc.v:128712.3-128735.6" + wire width 64 $0\stdata_r[63:0] + attribute \src "libresoc.v:128498.3-128506.6" + wire $0\sto_l_r_sto$next[0:0]$5813 + attribute \src "libresoc.v:128336.3-128337.39" + wire $0\sto_l_r_sto[0:0] + attribute \src "libresoc.v:128489.3-128497.6" + wire $0\upd_l_r_upd$next[0:0]$5810 + attribute \src "libresoc.v:128338.3-128339.39" + wire $0\upd_l_r_upd[0:0] + attribute \src "libresoc.v:128480.3-128488.6" + wire $0\upd_l_s_upd$next[0:0]$5807 + attribute \src "libresoc.v:128340.3-128341.39" + wire $0\upd_l_s_upd[0:0] + attribute \src "libresoc.v:128471.3-128479.6" + wire $0\wri_l_r_wri$next[0:0]$5804 + attribute \src "libresoc.v:128342.3-128343.39" + wire $0\wri_l_r_wri[0:0] + attribute \src "libresoc.v:128462.3-128470.6" + wire $1\adr_l_r_adr$next[0:0]$5802 + attribute \src "libresoc.v:127677.7-127677.25" + wire $1\adr_l_r_adr[0:0] + attribute \src "libresoc.v:127691.7-127691.20" + wire $1\alu_ok[0:0] + attribute \src "libresoc.v:128627.3-128636.6" + wire width 64 $1\dest1_o[63:0] + attribute \src "libresoc.v:128637.3-128646.6" + wire width 64 $1\dest2_o[63:0] + attribute \src "libresoc.v:128617.3-128626.6" + wire width 64 $1\ea_r$next[63:0]$5890 + attribute \src "libresoc.v:127737.14-127737.41" + wire width 64 $1\ea_r[63:0] + attribute \src "libresoc.v:128692.3-128711.6" + wire width 64 $1\ldd_o[63:0] + attribute \src "libresoc.v:128656.3-128679.6" + wire width 64 $1\lddata_r[63:0] + attribute \src "libresoc.v:128559.3-128568.6" + wire width 64 $1\ldo_r$next[63:0]$5875 + attribute \src "libresoc.v:127751.14-127751.42" + wire width 64 $1\ldo_r[63:0] + attribute \src "libresoc.v:127758.14-127758.62" + wire width 96 $1\ldst_port0_addr_i[95:0] + attribute \src "libresoc.v:128647.3-128655.6" + wire $1\ldst_port0_addr_i_ok$next[0:0]$5895 + attribute \src "libresoc.v:127763.7-127763.34" + wire $1\ldst_port0_addr_i_ok[0:0] + attribute \src "libresoc.v:128736.3-128747.6" + wire width 64 $1\ldst_port0_st_data_i[63:0] + attribute \src "libresoc.v:128507.3-128515.6" + wire $1\lsd_l_r_lsd$next[0:0]$5817 + attribute \src "libresoc.v:127796.7-127796.25" + wire $1\lsd_l_r_lsd[0:0] + attribute \src "libresoc.v:128435.3-128443.6" + wire $1\opc_l_r_opc$next[0:0]$5793 + attribute \src "libresoc.v:127810.7-127810.25" + wire $1\opc_l_r_opc[0:0] + attribute \src "libresoc.v:128426.3-128434.6" + wire $1\opc_l_s_opc$next[0:0]$5790 + attribute \src "libresoc.v:127814.7-127814.25" + wire $1\opc_l_s_opc[0:0] + attribute \src "libresoc.v:128516.3-128558.6" + wire $1\oper_r__byte_reverse$next[0:0]$5835 + attribute \src "libresoc.v:127942.7-127942.34" + wire $1\oper_r__byte_reverse[0:0] + attribute \src "libresoc.v:128516.3-128558.6" + wire width 4 $1\oper_r__data_len$next[3:0]$5836 + attribute \src "libresoc.v:127946.13-127946.36" + wire width 4 $1\oper_r__data_len[3:0] + attribute \src "libresoc.v:128516.3-128558.6" + wire width 12 $1\oper_r__fn_unit$next[11:0]$5837 + attribute \src "libresoc.v:127963.14-127963.39" + wire width 12 $1\oper_r__fn_unit[11:0] + attribute \src "libresoc.v:128516.3-128558.6" + wire width 64 $1\oper_r__imm_data__data$next[63:0]$5838 + attribute \src "libresoc.v:127967.14-127967.59" + wire width 64 $1\oper_r__imm_data__data[63:0] + attribute \src "libresoc.v:128516.3-128558.6" + wire $1\oper_r__imm_data__ok$next[0:0]$5839 + attribute \src "libresoc.v:127971.7-127971.34" + wire $1\oper_r__imm_data__ok[0:0] + attribute \src "libresoc.v:128516.3-128558.6" + wire width 32 $1\oper_r__insn$next[31:0]$5840 + attribute \src "libresoc.v:127975.14-127975.34" + wire width 32 $1\oper_r__insn[31:0] + attribute \src "libresoc.v:128516.3-128558.6" + wire width 7 $1\oper_r__insn_type$next[6:0]$5841 + attribute \src "libresoc.v:128053.13-128053.38" + wire width 7 $1\oper_r__insn_type[6:0] + attribute \src "libresoc.v:128516.3-128558.6" + wire $1\oper_r__is_32bit$next[0:0]$5842 + attribute \src "libresoc.v:128057.7-128057.30" + wire $1\oper_r__is_32bit[0:0] + attribute \src "libresoc.v:128516.3-128558.6" + wire $1\oper_r__is_signed$next[0:0]$5843 + attribute \src "libresoc.v:128061.7-128061.31" + wire $1\oper_r__is_signed[0:0] + attribute \src "libresoc.v:128516.3-128558.6" + wire width 2 $1\oper_r__ldst_mode$next[1:0]$5844 + attribute \src "libresoc.v:128070.13-128070.37" + wire width 2 $1\oper_r__ldst_mode[1:0] + attribute \src "libresoc.v:128516.3-128558.6" + wire $1\oper_r__oe__oe$next[0:0]$5845 + attribute \src "libresoc.v:128074.7-128074.28" + wire $1\oper_r__oe__oe[0:0] + attribute \src "libresoc.v:128516.3-128558.6" + wire $1\oper_r__oe__ok$next[0:0]$5846 + attribute \src "libresoc.v:128078.7-128078.28" + wire $1\oper_r__oe__ok[0:0] + attribute \src "libresoc.v:128516.3-128558.6" + wire $1\oper_r__rc__ok$next[0:0]$5847 + attribute \src "libresoc.v:128082.7-128082.28" + wire $1\oper_r__rc__ok[0:0] + attribute \src "libresoc.v:128516.3-128558.6" + wire $1\oper_r__rc__rc$next[0:0]$5848 + attribute \src "libresoc.v:128086.7-128086.28" + wire $1\oper_r__rc__rc[0:0] + attribute \src "libresoc.v:128516.3-128558.6" + wire $1\oper_r__sign_extend$next[0:0]$5849 + attribute \src "libresoc.v:128090.7-128090.33" + wire $1\oper_r__sign_extend[0:0] + attribute \src "libresoc.v:128516.3-128558.6" + wire $1\oper_r__zero_a$next[0:0]$5850 + attribute \src "libresoc.v:128094.7-128094.28" + wire $1\oper_r__zero_a[0:0] + attribute \src "libresoc.v:128098.7-128098.21" + wire $1\p_st_go[0:0] + attribute \src "libresoc.v:128680.3-128691.6" + wire width 64 $1\revnorev[63:0] + attribute \src "libresoc.v:128453.3-128461.6" + wire width 3 $1\src_l_r_src$next[2:0]$5799 + attribute \src "libresoc.v:128140.13-128140.31" + wire width 3 $1\src_l_r_src[2:0] + attribute \src "libresoc.v:128444.3-128452.6" + wire width 3 $1\src_l_s_src$next[2:0]$5796 + attribute \src "libresoc.v:128144.13-128144.31" + wire width 3 $1\src_l_s_src[2:0] + attribute \src "libresoc.v:128569.3-128584.6" + wire width 64 $1\src_r0$next[63:0]$5878 + attribute \src "libresoc.v:128148.14-128148.43" + wire width 64 $1\src_r0[63:0] + attribute \src "libresoc.v:128585.3-128600.6" + wire width 64 $1\src_r1$next[63:0]$5882 + attribute \src "libresoc.v:128152.14-128152.43" + wire width 64 $1\src_r1[63:0] + attribute \src "libresoc.v:128601.3-128616.6" + wire width 64 $1\src_r2$next[63:0]$5886 + attribute \src "libresoc.v:128156.14-128156.43" + wire width 64 $1\src_r2[63:0] + attribute \src "libresoc.v:128712.3-128735.6" + wire width 64 $1\stdata_r[63:0] + attribute \src "libresoc.v:128498.3-128506.6" + wire $1\sto_l_r_sto$next[0:0]$5814 + attribute \src "libresoc.v:128166.7-128166.25" + wire $1\sto_l_r_sto[0:0] + attribute \src "libresoc.v:128489.3-128497.6" + wire $1\upd_l_r_upd$next[0:0]$5811 + attribute \src "libresoc.v:128176.7-128176.25" + wire $1\upd_l_r_upd[0:0] + attribute \src "libresoc.v:128480.3-128488.6" + wire $1\upd_l_s_upd$next[0:0]$5808 + attribute \src "libresoc.v:128180.7-128180.25" + wire $1\upd_l_s_upd[0:0] + attribute \src "libresoc.v:128471.3-128479.6" + wire $1\wri_l_r_wri$next[0:0]$5805 + attribute \src "libresoc.v:128190.7-128190.25" + wire $1\wri_l_r_wri[0:0] + attribute \src "libresoc.v:128692.3-128711.6" + wire width 64 $2\ldd_o[63:0] + attribute \src "libresoc.v:128656.3-128679.6" + wire width 64 $2\lddata_r[63:0] + attribute \src "libresoc.v:128516.3-128558.6" + wire $2\oper_r__byte_reverse$next[0:0]$5851 + attribute \src "libresoc.v:128516.3-128558.6" + wire width 4 $2\oper_r__data_len$next[3:0]$5852 + attribute \src "libresoc.v:128516.3-128558.6" + wire width 12 $2\oper_r__fn_unit$next[11:0]$5853 + attribute \src "libresoc.v:128516.3-128558.6" + wire width 64 $2\oper_r__imm_data__data$next[63:0]$5854 + attribute \src "libresoc.v:128516.3-128558.6" + wire $2\oper_r__imm_data__ok$next[0:0]$5855 + attribute \src "libresoc.v:128516.3-128558.6" + wire width 32 $2\oper_r__insn$next[31:0]$5856 + attribute \src "libresoc.v:128516.3-128558.6" + wire width 7 $2\oper_r__insn_type$next[6:0]$5857 + attribute \src "libresoc.v:128516.3-128558.6" + wire $2\oper_r__is_32bit$next[0:0]$5858 + attribute \src "libresoc.v:128516.3-128558.6" + wire $2\oper_r__is_signed$next[0:0]$5859 + attribute \src "libresoc.v:128516.3-128558.6" + wire width 2 $2\oper_r__ldst_mode$next[1:0]$5860 + attribute \src "libresoc.v:128516.3-128558.6" + wire $2\oper_r__oe__oe$next[0:0]$5861 + attribute \src "libresoc.v:128516.3-128558.6" + wire $2\oper_r__oe__ok$next[0:0]$5862 + attribute \src "libresoc.v:128516.3-128558.6" + wire $2\oper_r__rc__ok$next[0:0]$5863 + attribute \src "libresoc.v:128516.3-128558.6" + wire $2\oper_r__rc__rc$next[0:0]$5864 + attribute \src "libresoc.v:128516.3-128558.6" + wire $2\oper_r__sign_extend$next[0:0]$5865 + attribute \src "libresoc.v:128516.3-128558.6" + wire $2\oper_r__zero_a$next[0:0]$5866 + attribute \src "libresoc.v:128569.3-128584.6" + wire width 64 $2\src_r0$next[63:0]$5879 + attribute \src "libresoc.v:128585.3-128600.6" + wire width 64 $2\src_r1$next[63:0]$5883 + attribute \src "libresoc.v:128601.3-128616.6" + wire width 64 $2\src_r2$next[63:0]$5887 + attribute \src "libresoc.v:128712.3-128735.6" + wire width 64 $2\stdata_r[63:0] + attribute \src "libresoc.v:128516.3-128558.6" + wire width 64 $3\oper_r__imm_data__data$next[63:0]$5867 + attribute \src "libresoc.v:128516.3-128558.6" + wire $3\oper_r__imm_data__ok$next[0:0]$5868 + attribute \src "libresoc.v:128516.3-128558.6" + wire $3\oper_r__oe__oe$next[0:0]$5869 + attribute \src "libresoc.v:128516.3-128558.6" + wire $3\oper_r__oe__ok$next[0:0]$5870 + attribute \src "libresoc.v:128516.3-128558.6" + wire $3\oper_r__rc__ok$next[0:0]$5871 + attribute \src "libresoc.v:128516.3-128558.6" + wire $3\oper_r__rc__rc$next[0:0]$5872 + attribute \src "libresoc.v:128269.18-128269.124" + wire width 65 $add$libresoc.v:128269$5736_Y + attribute \src "libresoc.v:128196.18-128196.124" + wire $and$libresoc.v:128196$5660_Y + attribute \src "libresoc.v:128197.19-128197.117" + wire $and$libresoc.v:128197$5661_Y + attribute \src "libresoc.v:128198.19-128198.119" + wire $and$libresoc.v:128198$5662_Y + attribute \src "libresoc.v:128199.19-128199.123" + wire $and$libresoc.v:128199$5663_Y + attribute \src "libresoc.v:128200.19-128200.123" + wire $and$libresoc.v:128200$5664_Y + attribute \src "libresoc.v:128201.19-128201.120" + wire $and$libresoc.v:128201$5665_Y + attribute \src "libresoc.v:128202.19-128202.123" + wire $and$libresoc.v:128202$5666_Y + attribute \src "libresoc.v:128203.19-128203.119" + wire $and$libresoc.v:128203$5667_Y + attribute \src "libresoc.v:128204.19-128204.123" + wire $and$libresoc.v:128204$5668_Y + attribute \src "libresoc.v:128205.19-128205.125" + wire $and$libresoc.v:128205$5669_Y + attribute \src "libresoc.v:128208.19-128208.116" + wire $and$libresoc.v:128208$5672_Y + attribute \src "libresoc.v:128209.19-128209.120" + wire $and$libresoc.v:128209$5673_Y + attribute \src "libresoc.v:128210.19-128210.123" + wire $and$libresoc.v:128210$5674_Y + attribute \src "libresoc.v:128214.19-128214.125" + wire $and$libresoc.v:128214$5678_Y + attribute \src "libresoc.v:128215.19-128215.123" + wire $and$libresoc.v:128215$5679_Y + attribute \src "libresoc.v:128220.19-128220.116" + wire $and$libresoc.v:128220$5684_Y + attribute \src "libresoc.v:128222.19-128222.116" + wire $and$libresoc.v:128222$5686_Y + attribute \src "libresoc.v:128225.19-128225.118" + wire $and$libresoc.v:128225$5689_Y + attribute \src "libresoc.v:128227.19-128227.125" + wire $and$libresoc.v:128227$5691_Y + attribute \src "libresoc.v:128230.19-128230.160" + wire width 3 $and$libresoc.v:128230$5694_Y + attribute \src "libresoc.v:128231.19-128231.122" + wire $and$libresoc.v:128231$5695_Y + attribute \src "libresoc.v:128232.19-128232.122" + wire $and$libresoc.v:128232$5696_Y + attribute \src "libresoc.v:128234.19-128234.122" + wire $and$libresoc.v:128234$5699_Y + attribute \src "libresoc.v:128244.18-128244.123" + wire $and$libresoc.v:128244$5711_Y + attribute \src "libresoc.v:128245.18-128245.123" + wire $and$libresoc.v:128245$5712_Y + attribute \src "libresoc.v:128247.18-128247.114" + wire $and$libresoc.v:128247$5714_Y + attribute \src "libresoc.v:128249.18-128249.113" + wire $and$libresoc.v:128249$5716_Y + attribute \src "libresoc.v:128252.18-128252.113" + wire $and$libresoc.v:128252$5719_Y + attribute \src "libresoc.v:128257.18-128257.113" + wire $and$libresoc.v:128257$5724_Y + attribute \src "libresoc.v:128260.18-128260.119" + wire $and$libresoc.v:128260$5727_Y + attribute \src "libresoc.v:128270.18-128270.150" + wire width 3 $and$libresoc.v:128270$5737_Y + attribute \src "libresoc.v:128272.18-128272.113" + wire width 3 $and$libresoc.v:128272$5739_Y + attribute \src "libresoc.v:128274.18-128274.113" + wire width 3 $and$libresoc.v:128274$5741_Y + attribute \src "libresoc.v:128276.18-128276.127" + wire $and$libresoc.v:128276$5743_Y + attribute \src "libresoc.v:128277.18-128277.117" + wire $and$libresoc.v:128277$5744_Y + attribute \src "libresoc.v:128281.18-128281.117" + wire $and$libresoc.v:128281$5748_Y + attribute \src "libresoc.v:128283.18-128283.117" + wire $and$libresoc.v:128283$5750_Y + attribute \src "libresoc.v:128284.18-128284.124" + wire $and$libresoc.v:128284$5751_Y + attribute \src "libresoc.v:128285.18-128285.118" + wire $and$libresoc.v:128285$5752_Y + attribute \src "libresoc.v:128207.19-128207.127" + wire $eq$libresoc.v:128207$5671_Y + attribute \src "libresoc.v:128226.19-128226.127" + wire $eq$libresoc.v:128226$5690_Y + attribute \src "libresoc.v:128228.18-128228.127" + wire $eq$libresoc.v:128228$5692_Y + attribute \src "libresoc.v:128229.19-128229.127" + wire $eq$libresoc.v:128229$5693_Y + attribute \src "libresoc.v:128238.19-128238.126" + wire $eq$libresoc.v:128238$5704_Y + attribute \src "libresoc.v:128239.18-128239.127" + wire $eq$libresoc.v:128239$5705_Y + attribute \src "libresoc.v:128251.18-128251.126" + wire $eq$libresoc.v:128251$5718_Y + attribute \src "libresoc.v:128256.18-128256.126" + wire $eq$libresoc.v:128256$5723_Y + attribute \src "libresoc.v:128233.19-128233.110" + wire width 96 $extend$libresoc.v:128233$5697_Y + attribute \src "libresoc.v:128235.19-128235.116" + wire width 64 $extend$libresoc.v:128235$5700_Y + attribute \src "libresoc.v:128240.19-128240.102" + wire width 64 $extend$libresoc.v:128240$5706_Y + attribute \src "libresoc.v:128219.19-128219.109" + wire $not$libresoc.v:128219$5683_Y + attribute \src "libresoc.v:128223.19-128223.121" + wire $not$libresoc.v:128223$5687_Y + attribute \src "libresoc.v:128246.18-128246.112" + wire $not$libresoc.v:128246$5713_Y + attribute \src "libresoc.v:128248.18-128248.110" + wire $not$libresoc.v:128248$5715_Y + attribute \src "libresoc.v:128250.18-128250.120" + wire $not$libresoc.v:128250$5717_Y + attribute \src "libresoc.v:128255.18-128255.120" + wire $not$libresoc.v:128255$5722_Y + attribute \src "libresoc.v:128271.18-128271.143" + wire width 2 $not$libresoc.v:128271$5738_Y + attribute \src "libresoc.v:128273.18-128273.115" + wire width 3 $not$libresoc.v:128273$5740_Y + attribute \src "libresoc.v:128280.18-128280.107" + wire $not$libresoc.v:128280$5747_Y + attribute \src "libresoc.v:128282.18-128282.118" + wire $not$libresoc.v:128282$5749_Y + attribute \src "libresoc.v:128195.17-128195.125" + wire $or$libresoc.v:128195$5659_Y + attribute \src "libresoc.v:128206.18-128206.156" + wire width 3 $or$libresoc.v:128206$5670_Y + attribute \src "libresoc.v:128211.19-128211.123" + wire $or$libresoc.v:128211$5675_Y + attribute \src "libresoc.v:128212.19-128212.125" + wire $or$libresoc.v:128212$5676_Y + attribute \src "libresoc.v:128213.19-128213.125" + wire $or$libresoc.v:128213$5677_Y + attribute \src "libresoc.v:128216.19-128216.132" + wire $or$libresoc.v:128216$5680_Y + attribute \src "libresoc.v:128217.18-128217.126" + wire $or$libresoc.v:128217$5681_Y + attribute \src "libresoc.v:128218.19-128218.126" + wire $or$libresoc.v:128218$5682_Y + attribute \src "libresoc.v:128221.19-128221.125" + wire $or$libresoc.v:128221$5685_Y + attribute \src "libresoc.v:128224.19-128224.119" + wire $or$libresoc.v:128224$5688_Y + attribute \src "libresoc.v:128243.17-128243.124" + wire $or$libresoc.v:128243$5710_Y + attribute \src "libresoc.v:128253.18-128253.116" + wire $or$libresoc.v:128253$5720_Y + attribute \src "libresoc.v:128254.17-128254.123" + wire $or$libresoc.v:128254$5721_Y + attribute \src "libresoc.v:128258.18-128258.116" + wire $or$libresoc.v:128258$5725_Y + attribute \src "libresoc.v:128259.18-128259.127" + wire width 2 $or$libresoc.v:128259$5726_Y + attribute \src "libresoc.v:128261.18-128261.118" + wire $or$libresoc.v:128261$5728_Y + attribute \src "libresoc.v:128262.18-128262.118" + wire $or$libresoc.v:128262$5729_Y + attribute \src "libresoc.v:128263.18-128263.114" + wire $or$libresoc.v:128263$5730_Y + attribute \src "libresoc.v:128265.17-128265.128" + wire $or$libresoc.v:128265$5732_Y + attribute \src "libresoc.v:128275.17-128275.128" + wire $or$libresoc.v:128275$5742_Y + attribute \src "libresoc.v:128278.18-128278.132" + wire $or$libresoc.v:128278$5745_Y + attribute \src "libresoc.v:128279.18-128279.134" + wire $or$libresoc.v:128279$5746_Y + attribute \src "libresoc.v:128233.19-128233.110" + wire width 96 $pos$libresoc.v:128233$5698_Y + attribute \src "libresoc.v:128235.19-128235.116" + wire width 64 $pos$libresoc.v:128235$5701_Y + attribute \src "libresoc.v:128236.19-128236.148" + wire width 64 $pos$libresoc.v:128236$5702_Y + attribute \src "libresoc.v:128237.19-128237.206" + wire width 64 $pos$libresoc.v:128237$5703_Y + attribute \src "libresoc.v:128240.19-128240.102" + wire width 64 $pos$libresoc.v:128240$5707_Y + attribute \src "libresoc.v:128241.19-128241.120" + wire width 64 $pos$libresoc.v:128241$5708_Y + attribute \src "libresoc.v:128242.19-128242.150" + wire width 64 $pos$libresoc.v:128242$5709_Y + attribute \src "libresoc.v:128264.18-128264.107" + wire width 64 $ternary$libresoc.v:128264$5731_Y + attribute \src "libresoc.v:128266.18-128266.112" + wire width 64 $ternary$libresoc.v:128266$5733_Y + attribute \src "libresoc.v:128267.18-128267.147" + wire width 64 $ternary$libresoc.v:128267$5734_Y + attribute \src "libresoc.v:128268.18-128268.155" + wire width 64 $ternary$libresoc.v:128268$5735_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:294" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:445" + wire \$101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:445" + wire \$103 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:446" + wire \$105 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:450" + wire \$107 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:450" + wire \$109 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:299" + wire width 3 \$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:450" + wire \$111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:450" + wire \$113 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:450" + wire \$115 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:454" + wire \$117 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:309" + wire \$119 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:454" + wire \$121 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:454" + wire \$123 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:454" + wire \$125 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:458" + wire \$127 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:458" + wire \$129 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:300" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:458" + wire \$131 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:461" + wire \$133 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:461" + wire \$135 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:461" + wire \$137 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:461" + wire \$138 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:461" + wire \$140 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:461" + wire \$143 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462" + wire \$145 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462" + wire \$147 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:464" + wire \$149 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:307" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:464" + wire \$151 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:464" + wire \$153 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:309" + wire \$155 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:476" + wire \$157 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:481" + wire width 3 \$159 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:309" + wire \$160 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:481" + wire width 3 \$162 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:488" + wire \$164 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:489" + wire \$166 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:399" + wire width 96 \$168 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:308" + wire \$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:493" + wire \$170 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:28" + wire width 64 \$172 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:28" + wire width 64 \$174 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:28" + wire width 64 \$176 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:510" + wire \$178 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:28" + wire width 64 \$180 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:28" + wire width 64 \$182 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:28" + wire width 64 \$184 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:311" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:312" + wire \$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:343" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:343" + wire \$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:343" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:343" + wire \$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:295" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:359" + wire width 2 \$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:356" + wire \$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:309" + wire \$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:356" + wire \$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:356" + wire \$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:356" + wire \$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:309" + wire \$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:356" + wire \$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:356" + wire \$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:359" + wire width 2 \$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:296" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:366" + wire \$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:367" + wire \$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:371" + wire \$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:371" + wire \$56 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 64 \$58 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 64 \$60 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:405" + wire width 64 \$62 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:410" + wire width 64 \$64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:413" + wire width 65 \$66 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:413" + wire width 65 \$67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:427" + wire width 3 \$69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:297" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:427" + wire width 2 \$71 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:427" + wire width 3 \$73 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:427" + wire width 3 \$75 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:427" + wire width 3 \$77 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:436" + wire \$79 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:436" + wire \$81 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:430" + wire \$83 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:433" + wire \$85 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:433" + wire \$86 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:433" + wire \$89 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:298" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:439" + wire \$91 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:439" + wire \$93 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:442" + wire \$95 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:442" + wire \$97 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:445" + wire \$99 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:107" + wire \addr_exc_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:271" + wire \addr_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:399" + wire width 64 \addr_r + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire \adr_l_q_adr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \adr_l_r_adr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \adr_l_r_adr$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \adr_l_s_adr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire \alu_l_q_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \alu_l_r_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \alu_l_s_alu + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:279" + wire width 64 \alu_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:270" + wire \alu_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:270" + wire \alu_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:269" + wire \alu_valid + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 46 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 33 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire input 2 \cu_ad__go_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire output 3 \cu_ad__rel_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" + wire output 22 \cu_busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:108" + wire \cu_done_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:104" + wire \cu_go_die_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" + wire input 21 \cu_issue_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 input 25 \cu_rd__go_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 output 24 \cu_rd__rel_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" + wire width 3 input 23 \cu_rdmaskn_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:102" + wire \cu_shadown_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire input 4 \cu_st__go_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire output 1 \cu_st__rel_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 2 input 30 \cu_wr__go_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 2 output 29 \cu_wr__rel_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:97" + wire width 2 \cu_wrmask_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 \dest1_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 \dest2_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 32 \ea + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 64 \ea_r + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 64 \ea_r$next + attribute \src "libresoc.v:127479.7-127479.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:109" + wire \ld_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:272" + wire \ld_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:280" + wire width 64 \ldd_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:384" + wire width 64 \ldd_r + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:11" + wire width 64 \lddata_r + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 64 \ldo_r + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 64 \ldo_r$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:110" + wire input 40 \ldst_port0_addr_exc_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 96 output 38 \ldst_port0_addr_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 96 \ldst_port0_addr_i$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 39 \ldst_port0_addr_i_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \ldst_port0_addr_i_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:109" + wire input 41 \ldst_port0_addr_ok_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:105" + wire input 34 \ldst_port0_busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102" + wire width 4 output 37 \ldst_port0_data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:98" + wire output 35 \ldst_port0_is_ld_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" + wire output 36 \ldst_port0_is_st_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 input 42 \ldst_port0_ld_data_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire input 43 \ldst_port0_ld_data_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 44 \ldst_port0_st_data_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 45 \ldst_port0_st_data_i_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:113" + wire \load_mem_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \lod_l_qn_lod + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \lod_l_r_lod + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \lod_l_s_lod + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire \lsd_l_q_lsd + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \lsd_l_r_lsd + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \lsd_l_r_lsd$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \lsd_l_s_lsd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 31 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:265" + wire \op_is_ld + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:266" + wire \op_is_st + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire \opc_l_q_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \opc_l_r_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \opc_l_r_opc$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \opc_l_s_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \opc_l_s_opc$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 17 \oper_i_ldst_ldst0__byte_reverse + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 16 \oper_i_ldst_ldst0__data_len + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 6 \oper_i_ldst_ldst0__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 7 \oper_i_ldst_ldst0__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \oper_i_ldst_ldst0__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 20 \oper_i_ldst_ldst0__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 5 \oper_i_ldst_ldst0__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \oper_i_ldst_ldst0__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 15 \oper_i_ldst_ldst0__is_signed + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 19 \oper_i_ldst_ldst0__ldst_mode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \oper_i_ldst_ldst0__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \oper_i_ldst_ldst0__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 11 \oper_i_ldst_ldst0__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \oper_i_ldst_ldst0__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 18 \oper_i_ldst_ldst0__sign_extend + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \oper_i_ldst_ldst0__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \oper_r__byte_reverse + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \oper_r__byte_reverse$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \oper_r__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \oper_r__data_len$next + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \oper_r__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \oper_r__fn_unit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \oper_r__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \oper_r__imm_data__data$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \oper_r__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \oper_r__imm_data__ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \oper_r__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \oper_r__insn$next + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \oper_r__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \oper_r__insn_type$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \oper_r__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \oper_r__is_32bit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \oper_r__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \oper_r__is_signed$next + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \oper_r__ldst_mode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \oper_r__ldst_mode$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \oper_r__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \oper_r__oe__oe$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \oper_r__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \oper_r__oe__ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \oper_r__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \oper_r__rc__ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \oper_r__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \oper_r__rc__rc$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \oper_r__sign_extend + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \oper_r__sign_extend$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \oper_r__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \oper_r__zero_a$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:302" + wire \p_st_go + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:302" + wire \p_st_go$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:275" + wire \rd_done + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:274" + wire \rda_any + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:289" + wire \reset_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:290" + wire \reset_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:286" + wire \reset_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:291" + wire width 3 \reset_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:292" + wire \reset_s + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:288" + wire \reset_u + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:287" + wire \reset_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:498" + wire width 64 \revnorev + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire \rst_l_q_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \rst_l_r_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \rst_l_s_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 26 \src1_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:404" + wire width 64 \src1_or_z + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 27 \src2_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:409" + wire width 64 \src2_or_imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 28 \src3_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 3 \src_l_q_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 3 \src_l_r_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 3 \src_l_r_src$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 3 \src_l_s_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 3 \src_l_s_src$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:391" + wire width 64 \src_r0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:391" + wire width 64 \src_r0$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:391" + wire width 64 \src_r1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:391" + wire width 64 \src_r1$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:391" + wire width 64 \src_r2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:391" + wire width 64 \src_r2$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:110" + wire \st_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:11" + wire width 64 \stdata_r + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire \sto_l_q_sto + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \sto_l_r_sto + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \sto_l_r_sto$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \sto_l_s_sto + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:114" + wire \stwd_mem_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire \upd_l_q_upd + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \upd_l_r_upd + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \upd_l_r_upd$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \upd_l_s_upd + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \upd_l_s_upd$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:273" + wire \wr_any + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:276" + wire \wr_reset + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire \wri_l_q_wri + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \wri_l_r_wri + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \wri_l_r_wri$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \wri_l_s_wri + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:413" + cell $add $add$libresoc.v:128269$5736 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \src1_or_z + connect \B \src2_or_imm + connect \Y $add$libresoc.v:128269$5736_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:445" + cell $and $and$libresoc.v:128196$5660 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \sto_l_q_sto + connect \B \cu_busy_o + connect \Y $and$libresoc.v:128196$5660_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:445" + cell $and $and$libresoc.v:128197$5661 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$99 + connect \B \rd_done + connect \Y $and$libresoc.v:128197$5661_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:445" + cell $and $and$libresoc.v:128198$5662 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$101 + connect \B \op_is_st + connect \Y $and$libresoc.v:128198$5662_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:446" + cell $and $and$libresoc.v:128199$5663 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$103 + connect \B \cu_shadown_i + connect \Y $and$libresoc.v:128199$5663_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:450" + cell $and $and$libresoc.v:128200$5664 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \rd_done + connect \B \wri_l_q_wri + connect \Y $and$libresoc.v:128200$5664_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:450" + cell $and $and$libresoc.v:128201$5665 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$107 + connect \B \cu_busy_o + connect \Y $and$libresoc.v:128201$5665_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:450" + cell $and $and$libresoc.v:128202$5666 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$109 + connect \B \lod_l_qn_lod + connect \Y $and$libresoc.v:128202$5666_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:450" + cell $and $and$libresoc.v:128203$5667 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$111 + connect \B \op_is_ld + connect \Y $and$libresoc.v:128203$5667_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:450" + cell $and $and$libresoc.v:128204$5668 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$113 + connect \B \cu_shadown_i + connect \Y $and$libresoc.v:128204$5668_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:454" + cell $and $and$libresoc.v:128205$5669 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \upd_l_q_upd + connect \B \cu_busy_o + connect \Y $and$libresoc.v:128205$5669_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:454" + cell $and $and$libresoc.v:128208$5672 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$117 + connect \B \$119 + connect \Y $and$libresoc.v:128208$5672_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:454" + cell $and $and$libresoc.v:128209$5673 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$121 + connect \B \alu_valid + connect \Y $and$libresoc.v:128209$5673_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:454" + cell $and $and$libresoc.v:128210$5674 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$123 + connect \B \cu_shadown_i + connect \Y $and$libresoc.v:128210$5674_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:461" + cell $and $and$libresoc.v:128214$5678 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \rst_l_q_rst + connect \B \cu_busy_o + connect \Y $and$libresoc.v:128214$5678_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:461" + cell $and $and$libresoc.v:128215$5679 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$133 + connect \B \cu_shadown_i + connect \Y $and$libresoc.v:128215$5679_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:461" + cell $and $and$libresoc.v:128220$5684 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$135 + connect \B \$137 + connect \Y $and$libresoc.v:128220$5684_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462" + cell $and $and$libresoc.v:128222$5686 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$143 + connect \B \$145 + connect \Y $and$libresoc.v:128222$5686_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:464" + cell $and $and$libresoc.v:128225$5689 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_reset + connect \B \$151 + connect \Y $and$libresoc.v:128225$5689_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:476" + cell $and $and$libresoc.v:128227$5691 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$155 + connect \B \cu_wr__go_i [1] + connect \Y $and$libresoc.v:128227$5691_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:481" + cell $and $and$libresoc.v:128230$5694 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { \cu_busy_o \cu_busy_o \cu_busy_o } + connect \B { 1'0 \$160 \op_is_ld } + connect \Y $and$libresoc.v:128230$5694_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:488" + cell $and $and$libresoc.v:128231$5695 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \op_is_ld + connect \B \cu_busy_o + connect \Y $and$libresoc.v:128231$5695_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:489" + cell $and $and$libresoc.v:128232$5696 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \op_is_st + connect \B \cu_busy_o + connect \Y $and$libresoc.v:128232$5696_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:493" + cell $and $and$libresoc.v:128234$5699 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_ok + connect \B \lsd_l_q_lsd + connect \Y $and$libresoc.v:128234$5699_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:311" + cell $and $and$libresoc.v:128244$5711 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \op_is_ld + connect \B \cu_ad__go_i + connect \Y $and$libresoc.v:128244$5711_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:312" + cell $and $and$libresoc.v:128245$5712 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \op_is_st + connect \B \cu_st__go_i + connect \Y $and$libresoc.v:128245$5712_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:343" + cell $and $and$libresoc.v:128247$5714 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_ok + connect \B \$23 + connect \Y $and$libresoc.v:128247$5714_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:343" + cell $and $and$libresoc.v:128249$5716 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$25 + connect \B \$27 + connect \Y $and$libresoc.v:128249$5716_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:356" + cell $and $and$libresoc.v:128252$5719 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$32 + connect \B \$34 + connect \Y $and$libresoc.v:128252$5719_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:356" + cell $and $and$libresoc.v:128257$5724 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$40 + connect \B \$42 + connect \Y $and$libresoc.v:128257$5724_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:366" + cell $and $and$libresoc.v:128260$5727 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \addr_ok + connect \B \op_is_st + connect \Y $and$libresoc.v:128260$5727_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:427" + cell $and $and$libresoc.v:128270$5737 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \src_l_q_src + connect \B { \cu_busy_o \cu_busy_o \cu_busy_o } + connect \Y $and$libresoc.v:128270$5737_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:427" + cell $and $and$libresoc.v:128272$5739 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 3 + connect \A \$69 + connect \B \$71 + connect \Y $and$libresoc.v:128272$5739_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:427" + cell $and $and$libresoc.v:128274$5741 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \$73 + connect \B \$75 + connect \Y $and$libresoc.v:128274$5741_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:436" + cell $and $and$libresoc.v:128276$5743 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \src_l_q_src [2] + connect \B \cu_busy_o + connect \Y $and$libresoc.v:128276$5743_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:436" + cell $and $and$libresoc.v:128277$5744 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$79 + connect \B \op_is_st + connect \Y $and$libresoc.v:128277$5744_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:433" + cell $and $and$libresoc.v:128281$5748 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_busy_o + connect \B \$85 + connect \Y $and$libresoc.v:128281$5748_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:439" + cell $and $and$libresoc.v:128283$5750 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_valid + connect \B \$91 + connect \Y $and$libresoc.v:128283$5750_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:442" + cell $and $and$libresoc.v:128284$5751 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_valid + connect \B \adr_l_q_adr + connect \Y $and$libresoc.v:128284$5751_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:442" + cell $and $and$libresoc.v:128285$5752 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$95 + connect \B \cu_busy_o + connect \Y $and$libresoc.v:128285$5752_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:309" + cell $eq $eq$libresoc.v:128207$5671 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \oper_r__ldst_mode + connect \B 2'01 + connect \Y $eq$libresoc.v:128207$5671_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:309" + cell $eq $eq$libresoc.v:128226$5690 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \oper_r__ldst_mode + connect \B 2'01 + connect \Y $eq$libresoc.v:128226$5690_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:307" + cell $eq $eq$libresoc.v:128228$5692 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \oper_r__insn_type + connect \B 7'0100110 + connect \Y $eq$libresoc.v:128228$5692_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:309" + cell $eq $eq$libresoc.v:128229$5693 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \oper_r__ldst_mode + connect \B 2'01 + connect \Y $eq$libresoc.v:128229$5693_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:510" + cell $eq $eq$libresoc.v:128238$5704 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \oper_r__data_len + connect \B 2'10 + connect \Y $eq$libresoc.v:128238$5704_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:308" + cell $eq $eq$libresoc.v:128239$5705 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \oper_r__insn_type + connect \B 7'0100101 + connect \Y $eq$libresoc.v:128239$5705_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:309" + cell $eq $eq$libresoc.v:128251$5718 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \oper_r__ldst_mode + connect \B 2'01 + connect \Y $eq$libresoc.v:128251$5718_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:309" + cell $eq $eq$libresoc.v:128256$5723 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \oper_r__ldst_mode + connect \B 2'01 + connect \Y $eq$libresoc.v:128256$5723_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:399" + cell $pos $extend$libresoc.v:128233$5697 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 96 + connect \A \addr_r + connect \Y $extend$libresoc.v:128233$5697_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:28" + cell $pos $extend$libresoc.v:128235$5700 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 64 + connect \A \ldst_port0_ld_data_o [7:0] + connect \Y $extend$libresoc.v:128235$5700_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:28" + cell $pos $extend$libresoc.v:128240$5706 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 64 + connect \A \src_r2 [7:0] + connect \Y $extend$libresoc.v:128240$5706_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:461" + cell $not $not$libresoc.v:128219$5683 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$140 + connect \Y $not$libresoc.v:128219$5683_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:464" + cell $not $not$libresoc.v:128223$5687 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ldst_port0_busy_o + connect \Y $not$libresoc.v:128223$5687_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:343" + cell $not $not$libresoc.v:128246$5713 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_valid + connect \Y $not$libresoc.v:128246$5713_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:343" + cell $not $not$libresoc.v:128248$5715 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \rda_any + connect \Y $not$libresoc.v:128248$5715_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:356" + cell $not $not$libresoc.v:128250$5717 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ldst_port0_busy_o + connect \Y $not$libresoc.v:128250$5717_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:356" + cell $not $not$libresoc.v:128255$5722 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ldst_port0_busy_o + connect \Y $not$libresoc.v:128255$5722_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:427" + cell $not $not$libresoc.v:128271$5738 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A { \oper_r__imm_data__ok \oper_r__zero_a } + connect \Y $not$libresoc.v:128271$5738_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:427" + cell $not $not$libresoc.v:128273$5740 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \cu_rdmaskn_i + connect \Y $not$libresoc.v:128273$5740_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:433" + cell $not $not$libresoc.v:128280$5747 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$86 + connect \Y $not$libresoc.v:128280$5747_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:439" + cell $not $not$libresoc.v:128282$5749 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_rd__rel_o [2] + connect \Y $not$libresoc.v:128282$5749_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:298" + cell $or $or$libresoc.v:128195$5659 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_st__go_i + connect \B \cu_go_die_i + connect \Y $or$libresoc.v:128195$5659_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:299" + cell $or $or$libresoc.v:128206$5670 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \cu_rd__go_i + connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } + connect \Y $or$libresoc.v:128206$5670_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:458" + cell $or $or$libresoc.v:128211$5675 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_st__go_i + connect \B \p_st_go + connect \Y $or$libresoc.v:128211$5675_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:458" + cell $or $or$libresoc.v:128212$5676 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$127 + connect \B \cu_wr__go_i [0] + connect \Y $or$libresoc.v:128212$5676_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:458" + cell $or $or$libresoc.v:128213$5677 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$129 + connect \B \cu_wr__go_i [1] + connect \Y $or$libresoc.v:128213$5677_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:461" + cell $or $or$libresoc.v:128216$5680 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_st__rel_o + connect \B \cu_wr__rel_o [0] + connect \Y $or$libresoc.v:128216$5680_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:300" + cell $or $or$libresoc.v:128217$5681 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_ad__go_i + connect \B \cu_go_die_i + connect \Y $or$libresoc.v:128217$5681_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:461" + cell $or $or$libresoc.v:128218$5682 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$138 + connect \B \cu_wr__rel_o [1] + connect \Y $or$libresoc.v:128218$5682_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462" + cell $or $or$libresoc.v:128221$5685 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \lod_l_qn_lod + connect \B \op_is_st + connect \Y $or$libresoc.v:128221$5685_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:464" + cell $or $or$libresoc.v:128224$5688 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$149 + connect \B \op_is_ld + connect \Y $or$libresoc.v:128224$5688_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:294" + cell $or $or$libresoc.v:128243$5710 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_issue_i + connect \B \cu_go_die_i + connect \Y $or$libresoc.v:128243$5710_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:356" + cell $or $or$libresoc.v:128253$5720 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_reset + connect \B \$36 + connect \Y $or$libresoc.v:128253$5720_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:295" + cell $or $or$libresoc.v:128254$5721 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_done_o + connect \B \cu_go_die_i + connect \Y $or$libresoc.v:128254$5721_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:356" + cell $or $or$libresoc.v:128258$5725 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_reset + connect \B \$44 + connect \Y $or$libresoc.v:128258$5725_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:359" + cell $or $or$libresoc.v:128259$5726 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \reset_w + connect \B { \$38 \$46 } + connect \Y $or$libresoc.v:128259$5726_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:367" + cell $or $or$libresoc.v:128261$5728 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \reset_s + connect \B \p_st_go + connect \Y $or$libresoc.v:128261$5728_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:371" + cell $or $or$libresoc.v:128262$5729 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \reset_s + connect \B \p_st_go + connect \Y $or$libresoc.v:128262$5729_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:371" + cell $or $or$libresoc.v:128263$5730 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$54 + connect \B \ld_ok + connect \Y $or$libresoc.v:128263$5730_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:296" + cell $or $or$libresoc.v:128265$5732 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_wr__go_i [0] + connect \B \cu_go_die_i + connect \Y $or$libresoc.v:128265$5732_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:297" + cell $or $or$libresoc.v:128275$5742 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_wr__go_i [1] + connect \B \cu_go_die_i + connect \Y $or$libresoc.v:128275$5742_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:430" + cell $or $or$libresoc.v:128278$5745 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_rd__go_i [0] + connect \B \cu_rd__go_i [1] + connect \Y $or$libresoc.v:128278$5745_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:433" + cell $or $or$libresoc.v:128279$5746 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_rd__rel_o [0] + connect \B \cu_rd__rel_o [1] + connect \Y $or$libresoc.v:128279$5746_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:399" + cell $pos $pos$libresoc.v:128233$5698 + parameter \A_SIGNED 0 + parameter \A_WIDTH 96 + parameter \Y_WIDTH 96 + connect \A $extend$libresoc.v:128233$5697_Y + connect \Y $pos$libresoc.v:128233$5698_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:28" + cell $pos $pos$libresoc.v:128235$5701 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:128235$5700_Y + connect \Y $pos$libresoc.v:128235$5701_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:28" + cell $pos $pos$libresoc.v:128236$5702 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A { 48'000000000000000000000000000000000000000000000000 \ldst_port0_ld_data_o [7:0] \ldst_port0_ld_data_o [15:8] } + connect \Y $pos$libresoc.v:128236$5702_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:28" + cell $pos $pos$libresoc.v:128237$5703 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A { 32'00000000000000000000000000000000 \ldst_port0_ld_data_o [7:0] \ldst_port0_ld_data_o [15:8] \ldst_port0_ld_data_o [23:16] \ldst_port0_ld_data_o [31:24] } + connect \Y $pos$libresoc.v:128237$5703_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:28" + cell $pos $pos$libresoc.v:128240$5707 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:128240$5706_Y + connect \Y $pos$libresoc.v:128240$5707_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:28" + cell $pos $pos$libresoc.v:128241$5708 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A { 48'000000000000000000000000000000000000000000000000 \src_r2 [7:0] \src_r2 [15:8] } + connect \Y $pos$libresoc.v:128241$5708_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:28" + cell $pos $pos$libresoc.v:128242$5709 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A { 32'00000000000000000000000000000000 \src_r2 [7:0] \src_r2 [15:8] \src_r2 [23:16] \src_r2 [31:24] } + connect \Y $pos$libresoc.v:128242$5709_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $ternary$libresoc.v:128264$5731 + parameter \WIDTH 64 + connect \A \ldo_r + connect \B \ldd_o + connect \S \ld_ok + connect \Y $ternary$libresoc.v:128264$5731_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $ternary$libresoc.v:128266$5733 + parameter \WIDTH 64 + connect \A \ea_r + connect \B \alu_o + connect \S \alu_l_q_alu + connect \Y $ternary$libresoc.v:128266$5733_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:405" + cell $mux $ternary$libresoc.v:128267$5734 + parameter \WIDTH 64 + connect \A \src_r0 + connect \B 64'0000000000000000000000000000000000000000000000000000000000000000 + connect \S \oper_r__zero_a + connect \Y $ternary$libresoc.v:128267$5734_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:410" + cell $mux $ternary$libresoc.v:128268$5735 + parameter \WIDTH 64 + connect \A \src_r1 + connect \B \oper_r__imm_data__data + connect \S \oper_r__imm_data__ok + connect \Y $ternary$libresoc.v:128268$5735_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:128356.9-128362.4" + cell \adr_l \adr_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_adr \adr_l_q_adr + connect \r_adr \adr_l_r_adr + connect \s_adr \adr_l_s_adr + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:128363.15-128369.4" + cell \alu_l$125 \alu_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_alu \alu_l_q_alu + connect \r_alu \alu_l_r_alu + connect \s_alu \alu_l_s_alu + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:128370.9-128376.4" + cell \lod_l \lod_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \qn_lod \lod_l_qn_lod + connect \r_lod \lod_l_r_lod + connect \s_lod \lod_l_s_lod + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:128377.9-128383.4" + cell \lsd_l \lsd_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_lsd \lsd_l_q_lsd + connect \r_lsd \lsd_l_r_lsd + connect \s_lsd \lsd_l_s_lsd + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:128384.15-128390.4" + cell \opc_l$123 \opc_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_opc \opc_l_q_opc + connect \r_opc \opc_l_r_opc + connect \s_opc \opc_l_s_opc + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:128391.15-128397.4" + cell \rst_l$126 \rst_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_rst \rst_l_q_rst + connect \r_rst \rst_l_r_rst + connect \s_rst \rst_l_s_rst + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:128398.15-128404.4" + cell \src_l$124 \src_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_src \src_l_q_src + connect \r_src \src_l_r_src + connect \s_src \src_l_s_src + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:128405.9-128411.4" + cell \sto_l \sto_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_sto \sto_l_q_sto + connect \r_sto \sto_l_r_sto + connect \s_sto \sto_l_s_sto + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:128412.9-128418.4" + cell \upd_l \upd_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_upd \upd_l_q_upd + connect \r_upd \upd_l_r_upd + connect \s_upd \upd_l_s_upd + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:128419.9-128425.4" + cell \wri_l \wri_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_wri \wri_l_q_wri + connect \r_wri \wri_l_r_wri + connect \s_wri \wri_l_s_wri + end + attribute \src "libresoc.v:127479.7-127479.20" + process $proc$libresoc.v:127479$5901 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:127677.7-127677.25" + process $proc$libresoc.v:127677$5902 + assign { } { } + assign $1\adr_l_r_adr[0:0] 1'1 + sync always + sync init + update \adr_l_r_adr $1\adr_l_r_adr[0:0] + end + attribute \src "libresoc.v:127691.7-127691.20" + process $proc$libresoc.v:127691$5903 + assign { } { } + assign $1\alu_ok[0:0] 1'0 + sync always + sync init + update \alu_ok $1\alu_ok[0:0] + end + attribute \src "libresoc.v:127737.14-127737.41" + process $proc$libresoc.v:127737$5904 + assign { } { } + assign $1\ea_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \ea_r $1\ea_r[63:0] + end + attribute \src "libresoc.v:127751.14-127751.42" + process $proc$libresoc.v:127751$5905 + assign { } { } + assign $1\ldo_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \ldo_r $1\ldo_r[63:0] + end + attribute \src "libresoc.v:127758.14-127758.62" + process $proc$libresoc.v:127758$5906 + assign { } { } + assign $1\ldst_port0_addr_i[95:0] 96'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \ldst_port0_addr_i $1\ldst_port0_addr_i[95:0] + end + attribute \src "libresoc.v:127763.7-127763.34" + process $proc$libresoc.v:127763$5907 + assign { } { } + assign $1\ldst_port0_addr_i_ok[0:0] 1'0 + sync always + sync init + update \ldst_port0_addr_i_ok $1\ldst_port0_addr_i_ok[0:0] + end + attribute \src "libresoc.v:127796.7-127796.25" + process $proc$libresoc.v:127796$5908 + assign { } { } + assign $1\lsd_l_r_lsd[0:0] 1'1 + sync always + sync init + update \lsd_l_r_lsd $1\lsd_l_r_lsd[0:0] + end + attribute \src "libresoc.v:127810.7-127810.25" + process $proc$libresoc.v:127810$5909 + assign { } { } + assign $1\opc_l_r_opc[0:0] 1'1 + sync always + sync init + update \opc_l_r_opc $1\opc_l_r_opc[0:0] + end + attribute \src "libresoc.v:127814.7-127814.25" + process $proc$libresoc.v:127814$5910 + assign { } { } + assign $1\opc_l_s_opc[0:0] 1'0 + sync always + sync init + update \opc_l_s_opc $1\opc_l_s_opc[0:0] + end + attribute \src "libresoc.v:127942.7-127942.34" + process $proc$libresoc.v:127942$5911 + assign { } { } + assign $1\oper_r__byte_reverse[0:0] 1'0 + sync always + sync init + update \oper_r__byte_reverse $1\oper_r__byte_reverse[0:0] + end + attribute \src "libresoc.v:127946.13-127946.36" + process $proc$libresoc.v:127946$5912 + assign { } { } + assign $1\oper_r__data_len[3:0] 4'0000 + sync always + sync init + update \oper_r__data_len $1\oper_r__data_len[3:0] + end + attribute \src "libresoc.v:127963.14-127963.39" + process $proc$libresoc.v:127963$5913 + assign { } { } + assign $1\oper_r__fn_unit[11:0] 12'000000000000 + sync always + sync init + update \oper_r__fn_unit $1\oper_r__fn_unit[11:0] + end + attribute \src "libresoc.v:127967.14-127967.59" + process $proc$libresoc.v:127967$5914 + assign { } { } + assign $1\oper_r__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \oper_r__imm_data__data $1\oper_r__imm_data__data[63:0] + end + attribute \src "libresoc.v:127971.7-127971.34" + process $proc$libresoc.v:127971$5915 + assign { } { } + assign $1\oper_r__imm_data__ok[0:0] 1'0 + sync always + sync init + update \oper_r__imm_data__ok $1\oper_r__imm_data__ok[0:0] + end + attribute \src "libresoc.v:127975.14-127975.34" + process $proc$libresoc.v:127975$5916 + assign { } { } + assign $1\oper_r__insn[31:0] 0 + sync always + sync init + update \oper_r__insn $1\oper_r__insn[31:0] + end + attribute \src "libresoc.v:128053.13-128053.38" + process $proc$libresoc.v:128053$5917 + assign { } { } + assign $1\oper_r__insn_type[6:0] 7'0000000 + sync always + sync init + update \oper_r__insn_type $1\oper_r__insn_type[6:0] + end + attribute \src "libresoc.v:128057.7-128057.30" + process $proc$libresoc.v:128057$5918 + assign { } { } + assign $1\oper_r__is_32bit[0:0] 1'0 + sync always + sync init + update \oper_r__is_32bit $1\oper_r__is_32bit[0:0] + end + attribute \src "libresoc.v:128061.7-128061.31" + process $proc$libresoc.v:128061$5919 + assign { } { } + assign $1\oper_r__is_signed[0:0] 1'0 + sync always + sync init + update \oper_r__is_signed $1\oper_r__is_signed[0:0] + end + attribute \src "libresoc.v:128070.13-128070.37" + process $proc$libresoc.v:128070$5920 + assign { } { } + assign $1\oper_r__ldst_mode[1:0] 2'00 + sync always + sync init + update \oper_r__ldst_mode $1\oper_r__ldst_mode[1:0] + end + attribute \src "libresoc.v:128074.7-128074.28" + process $proc$libresoc.v:128074$5921 + assign { } { } + assign $1\oper_r__oe__oe[0:0] 1'0 + sync always + sync init + update \oper_r__oe__oe $1\oper_r__oe__oe[0:0] + end + attribute \src "libresoc.v:128078.7-128078.28" + process $proc$libresoc.v:128078$5922 + assign { } { } + assign $1\oper_r__oe__ok[0:0] 1'0 + sync always + sync init + update \oper_r__oe__ok $1\oper_r__oe__ok[0:0] + end + attribute \src "libresoc.v:128082.7-128082.28" + process $proc$libresoc.v:128082$5923 + assign { } { } + assign $1\oper_r__rc__ok[0:0] 1'0 + sync always + sync init + update \oper_r__rc__ok $1\oper_r__rc__ok[0:0] + end + attribute \src "libresoc.v:128086.7-128086.28" + process $proc$libresoc.v:128086$5924 + assign { } { } + assign $1\oper_r__rc__rc[0:0] 1'0 + sync always + sync init + update \oper_r__rc__rc $1\oper_r__rc__rc[0:0] + end + attribute \src "libresoc.v:128090.7-128090.33" + process $proc$libresoc.v:128090$5925 + assign { } { } + assign $1\oper_r__sign_extend[0:0] 1'0 + sync always + sync init + update \oper_r__sign_extend $1\oper_r__sign_extend[0:0] + end + attribute \src "libresoc.v:128094.7-128094.28" + process $proc$libresoc.v:128094$5926 + assign { } { } + assign $1\oper_r__zero_a[0:0] 1'0 + sync always + sync init + update \oper_r__zero_a $1\oper_r__zero_a[0:0] + end + attribute \src "libresoc.v:128098.7-128098.21" + process $proc$libresoc.v:128098$5927 + assign { } { } + assign $1\p_st_go[0:0] 1'0 + sync always + sync init + update \p_st_go $1\p_st_go[0:0] + end + attribute \src "libresoc.v:128140.13-128140.31" + process $proc$libresoc.v:128140$5928 + assign { } { } + assign $1\src_l_r_src[2:0] 3'111 + sync always + sync init + update \src_l_r_src $1\src_l_r_src[2:0] + end + attribute \src "libresoc.v:128144.13-128144.31" + process $proc$libresoc.v:128144$5929 + assign { } { } + assign $1\src_l_s_src[2:0] 3'000 + sync always + sync init + update \src_l_s_src $1\src_l_s_src[2:0] + end + attribute \src "libresoc.v:128148.14-128148.43" + process $proc$libresoc.v:128148$5930 + assign { } { } + assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \src_r0 $1\src_r0[63:0] + end + attribute \src "libresoc.v:128152.14-128152.43" + process $proc$libresoc.v:128152$5931 + assign { } { } + assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \src_r1 $1\src_r1[63:0] + end + attribute \src "libresoc.v:128156.14-128156.43" + process $proc$libresoc.v:128156$5932 + assign { } { } + assign $1\src_r2[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \src_r2 $1\src_r2[63:0] + end + attribute \src "libresoc.v:128166.7-128166.25" + process $proc$libresoc.v:128166$5933 + assign { } { } + assign $1\sto_l_r_sto[0:0] 1'1 + sync always + sync init + update \sto_l_r_sto $1\sto_l_r_sto[0:0] + end + attribute \src "libresoc.v:128176.7-128176.25" + process $proc$libresoc.v:128176$5934 + assign { } { } + assign $1\upd_l_r_upd[0:0] 1'1 + sync always + sync init + update \upd_l_r_upd $1\upd_l_r_upd[0:0] + end + attribute \src "libresoc.v:128180.7-128180.25" + process $proc$libresoc.v:128180$5935 + assign { } { } + assign $1\upd_l_s_upd[0:0] 1'0 + sync always + sync init + update \upd_l_s_upd $1\upd_l_s_upd[0:0] + end + attribute \src "libresoc.v:128190.7-128190.25" + process $proc$libresoc.v:128190$5936 + assign { } { } + assign $1\wri_l_r_wri[0:0] 1'1 + sync always + sync init + update \wri_l_r_wri $1\wri_l_r_wri[0:0] + end + attribute \src "libresoc.v:128286.3-128287.57" + process $proc$libresoc.v:128286$5753 + assign { } { } + assign $0\ldst_port0_addr_i_ok[0:0] \ldst_port0_addr_i_ok$next + sync posedge \coresync_clk + update \ldst_port0_addr_i_ok $0\ldst_port0_addr_i_ok[0:0] + end + attribute \src "libresoc.v:128288.3-128289.33" + process $proc$libresoc.v:128288$5754 + assign { } { } + assign $0\ldst_port0_addr_i[95:0] \$168 + sync posedge \coresync_clk + update \ldst_port0_addr_i $0\ldst_port0_addr_i[95:0] + end + attribute \src "libresoc.v:128290.3-128291.21" + process $proc$libresoc.v:128290$5755 + assign { } { } + assign $0\alu_ok[0:0] \$89 + sync posedge \coresync_clk + update \alu_ok $0\alu_ok[0:0] + end + attribute \src "libresoc.v:128292.3-128293.25" + process $proc$libresoc.v:128292$5756 + assign { } { } + assign $0\ea_r[63:0] \ea_r$next + sync posedge \coresync_clk + update \ea_r $0\ea_r[63:0] + end + attribute \src "libresoc.v:128294.3-128295.29" + process $proc$libresoc.v:128294$5757 + assign { } { } + assign $0\src_r2[63:0] \src_r2$next + sync posedge \coresync_clk + update \src_r2 $0\src_r2[63:0] + end + attribute \src "libresoc.v:128296.3-128297.29" + process $proc$libresoc.v:128296$5758 + assign { } { } + assign $0\src_r1[63:0] \src_r1$next + sync posedge \coresync_clk + update \src_r1 $0\src_r1[63:0] + end + attribute \src "libresoc.v:128298.3-128299.29" + process $proc$libresoc.v:128298$5759 + assign { } { } + assign $0\src_r0[63:0] \src_r0$next + sync posedge \coresync_clk + update \src_r0 $0\src_r0[63:0] + end + attribute \src "libresoc.v:128300.3-128301.27" + process $proc$libresoc.v:128300$5760 + assign { } { } + assign $0\ldo_r[63:0] \ldo_r$next + sync posedge \coresync_clk + update \ldo_r $0\ldo_r[63:0] + end + attribute \src "libresoc.v:128302.3-128303.51" + process $proc$libresoc.v:128302$5761 + assign { } { } + assign $0\oper_r__insn_type[6:0] \oper_r__insn_type$next + sync posedge \coresync_clk + update \oper_r__insn_type $0\oper_r__insn_type[6:0] + end + attribute \src "libresoc.v:128304.3-128305.47" + process $proc$libresoc.v:128304$5762 + assign { } { } + assign $0\oper_r__fn_unit[11:0] \oper_r__fn_unit$next + sync posedge \coresync_clk + update \oper_r__fn_unit $0\oper_r__fn_unit[11:0] + end + attribute \src "libresoc.v:128306.3-128307.61" + process $proc$libresoc.v:128306$5763 + assign { } { } + assign $0\oper_r__imm_data__data[63:0] \oper_r__imm_data__data$next + sync posedge \coresync_clk + update \oper_r__imm_data__data $0\oper_r__imm_data__data[63:0] + end + attribute \src "libresoc.v:128308.3-128309.57" + process $proc$libresoc.v:128308$5764 + assign { } { } + assign $0\oper_r__imm_data__ok[0:0] \oper_r__imm_data__ok$next + sync posedge \coresync_clk + update \oper_r__imm_data__ok $0\oper_r__imm_data__ok[0:0] + end + attribute \src "libresoc.v:128310.3-128311.45" + process $proc$libresoc.v:128310$5765 + assign { } { } + assign $0\oper_r__zero_a[0:0] \oper_r__zero_a$next + sync posedge \coresync_clk + update \oper_r__zero_a $0\oper_r__zero_a[0:0] + end + attribute \src "libresoc.v:128312.3-128313.45" + process $proc$libresoc.v:128312$5766 + assign { } { } + assign $0\oper_r__rc__rc[0:0] \oper_r__rc__rc$next + sync posedge \coresync_clk + update \oper_r__rc__rc $0\oper_r__rc__rc[0:0] + end + attribute \src "libresoc.v:128314.3-128315.45" + process $proc$libresoc.v:128314$5767 + assign { } { } + assign $0\oper_r__rc__ok[0:0] \oper_r__rc__ok$next + sync posedge \coresync_clk + update \oper_r__rc__ok $0\oper_r__rc__ok[0:0] + end + attribute \src "libresoc.v:128316.3-128317.45" + process $proc$libresoc.v:128316$5768 + assign { } { } + assign $0\oper_r__oe__oe[0:0] \oper_r__oe__oe$next + sync posedge \coresync_clk + update \oper_r__oe__oe $0\oper_r__oe__oe[0:0] + end + attribute \src "libresoc.v:128318.3-128319.45" + process $proc$libresoc.v:128318$5769 + assign { } { } + assign $0\oper_r__oe__ok[0:0] \oper_r__oe__ok$next + sync posedge \coresync_clk + update \oper_r__oe__ok $0\oper_r__oe__ok[0:0] + end + attribute \src "libresoc.v:128320.3-128321.49" + process $proc$libresoc.v:128320$5770 + assign { } { } + assign $0\oper_r__is_32bit[0:0] \oper_r__is_32bit$next + sync posedge \coresync_clk + update \oper_r__is_32bit $0\oper_r__is_32bit[0:0] + end + attribute \src "libresoc.v:128322.3-128323.51" + process $proc$libresoc.v:128322$5771 + assign { } { } + assign $0\oper_r__is_signed[0:0] \oper_r__is_signed$next + sync posedge \coresync_clk + update \oper_r__is_signed $0\oper_r__is_signed[0:0] + end + attribute \src "libresoc.v:128324.3-128325.49" + process $proc$libresoc.v:128324$5772 + assign { } { } + assign $0\oper_r__data_len[3:0] \oper_r__data_len$next + sync posedge \coresync_clk + update \oper_r__data_len $0\oper_r__data_len[3:0] + end + attribute \src "libresoc.v:128326.3-128327.57" + process $proc$libresoc.v:128326$5773 + assign { } { } + assign $0\oper_r__byte_reverse[0:0] \oper_r__byte_reverse$next + sync posedge \coresync_clk + update \oper_r__byte_reverse $0\oper_r__byte_reverse[0:0] + end + attribute \src "libresoc.v:128328.3-128329.55" + process $proc$libresoc.v:128328$5774 + assign { } { } + assign $0\oper_r__sign_extend[0:0] \oper_r__sign_extend$next + sync posedge \coresync_clk + update \oper_r__sign_extend $0\oper_r__sign_extend[0:0] + end + attribute \src "libresoc.v:128330.3-128331.51" + process $proc$libresoc.v:128330$5775 + assign { } { } + assign $0\oper_r__ldst_mode[1:0] \oper_r__ldst_mode$next + sync posedge \coresync_clk + update \oper_r__ldst_mode $0\oper_r__ldst_mode[1:0] + end + attribute \src "libresoc.v:128332.3-128333.41" + process $proc$libresoc.v:128332$5776 + assign { } { } + assign $0\oper_r__insn[31:0] \oper_r__insn$next + sync posedge \coresync_clk + update \oper_r__insn $0\oper_r__insn[31:0] + end + attribute \src "libresoc.v:128334.3-128335.39" + process $proc$libresoc.v:128334$5777 + assign { } { } + assign $0\lsd_l_r_lsd[0:0] \lsd_l_r_lsd$next + sync posedge \coresync_clk + update \lsd_l_r_lsd $0\lsd_l_r_lsd[0:0] + end + attribute \src "libresoc.v:128336.3-128337.39" + process $proc$libresoc.v:128336$5778 + assign { } { } + assign $0\sto_l_r_sto[0:0] \sto_l_r_sto$next + sync posedge \coresync_clk + update \sto_l_r_sto $0\sto_l_r_sto[0:0] + end + attribute \src "libresoc.v:128338.3-128339.39" + process $proc$libresoc.v:128338$5779 + assign { } { } + assign $0\upd_l_r_upd[0:0] \upd_l_r_upd$next + sync posedge \coresync_clk + update \upd_l_r_upd $0\upd_l_r_upd[0:0] + end + attribute \src "libresoc.v:128340.3-128341.39" + process $proc$libresoc.v:128340$5780 + assign { } { } + assign $0\upd_l_s_upd[0:0] \upd_l_s_upd$next + sync posedge \coresync_clk + update \upd_l_s_upd $0\upd_l_s_upd[0:0] + end + attribute \src "libresoc.v:128342.3-128343.39" + process $proc$libresoc.v:128342$5781 + assign { } { } + assign $0\wri_l_r_wri[0:0] \wri_l_r_wri$next + sync posedge \coresync_clk + update \wri_l_r_wri $0\wri_l_r_wri[0:0] + end + attribute \src "libresoc.v:128344.3-128345.39" + process $proc$libresoc.v:128344$5782 + assign { } { } + assign $0\adr_l_r_adr[0:0] \adr_l_r_adr$next + sync posedge \coresync_clk + update \adr_l_r_adr $0\adr_l_r_adr[0:0] + end + attribute \src "libresoc.v:128346.3-128347.39" + process $proc$libresoc.v:128346$5783 + assign { } { } + assign $0\src_l_r_src[2:0] \src_l_r_src$next + sync posedge \coresync_clk + update \src_l_r_src $0\src_l_r_src[2:0] + end + attribute \src "libresoc.v:128348.3-128349.39" + process $proc$libresoc.v:128348$5784 + assign { } { } + assign $0\src_l_s_src[2:0] \src_l_s_src$next + sync posedge \coresync_clk + update \src_l_s_src $0\src_l_s_src[2:0] + end + attribute \src "libresoc.v:128350.3-128351.39" + process $proc$libresoc.v:128350$5785 + assign { } { } + assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next + sync posedge \coresync_clk + update \opc_l_r_opc $0\opc_l_r_opc[0:0] + end + attribute \src "libresoc.v:128352.3-128353.39" + process $proc$libresoc.v:128352$5786 + assign { } { } + assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next + sync posedge \coresync_clk + update \opc_l_s_opc $0\opc_l_s_opc[0:0] + end + attribute \src "libresoc.v:128354.3-128355.28" + process $proc$libresoc.v:128354$5787 + assign { } { } + assign $0\p_st_go[0:0] \cu_st__go_i + sync posedge \coresync_clk + update \p_st_go $0\p_st_go[0:0] + end + attribute \src "libresoc.v:128426.3-128434.6" + process $proc$libresoc.v:128426$5788 + assign { } { } + assign { } { } + assign $0\opc_l_s_opc$next[0:0]$5789 $1\opc_l_s_opc$next[0:0]$5790 + attribute \src "libresoc.v:128427.5-128427.29" + switch \initial + attribute \src "libresoc.v:128427.9-128427.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\opc_l_s_opc$next[0:0]$5790 1'0 + case + assign $1\opc_l_s_opc$next[0:0]$5790 \cu_issue_i + end + sync always + update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$5789 + end + attribute \src "libresoc.v:128435.3-128443.6" + process $proc$libresoc.v:128435$5791 + assign { } { } + assign { } { } + assign $0\opc_l_r_opc$next[0:0]$5792 $1\opc_l_r_opc$next[0:0]$5793 + attribute \src "libresoc.v:128436.5-128436.29" + switch \initial + attribute \src "libresoc.v:128436.9-128436.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\opc_l_r_opc$next[0:0]$5793 1'1 + case + assign $1\opc_l_r_opc$next[0:0]$5793 \reset_o + end + sync always + update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$5792 + end + attribute \src "libresoc.v:128444.3-128452.6" + process $proc$libresoc.v:128444$5794 + assign { } { } + assign { } { } + assign $0\src_l_s_src$next[2:0]$5795 $1\src_l_s_src$next[2:0]$5796 + attribute \src "libresoc.v:128445.5-128445.29" + switch \initial + attribute \src "libresoc.v:128445.9-128445.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_l_s_src$next[2:0]$5796 3'000 + case + assign $1\src_l_s_src$next[2:0]$5796 { \cu_issue_i \cu_issue_i \cu_issue_i } + end + sync always + update \src_l_s_src$next $0\src_l_s_src$next[2:0]$5795 + end + attribute \src "libresoc.v:128453.3-128461.6" + process $proc$libresoc.v:128453$5797 + assign { } { } + assign { } { } + assign $0\src_l_r_src$next[2:0]$5798 $1\src_l_r_src$next[2:0]$5799 + attribute \src "libresoc.v:128454.5-128454.29" + switch \initial + attribute \src "libresoc.v:128454.9-128454.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_l_r_src$next[2:0]$5799 3'111 + case + assign $1\src_l_r_src$next[2:0]$5799 \reset_r + end + sync always + update \src_l_r_src$next $0\src_l_r_src$next[2:0]$5798 + end + attribute \src "libresoc.v:128462.3-128470.6" + process $proc$libresoc.v:128462$5800 + assign { } { } + assign { } { } + assign $0\adr_l_r_adr$next[0:0]$5801 $1\adr_l_r_adr$next[0:0]$5802 + attribute \src "libresoc.v:128463.5-128463.29" + switch \initial + attribute \src "libresoc.v:128463.9-128463.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\adr_l_r_adr$next[0:0]$5802 1'1 + case + assign $1\adr_l_r_adr$next[0:0]$5802 \reset_a + end + sync always + update \adr_l_r_adr$next $0\adr_l_r_adr$next[0:0]$5801 + end + attribute \src "libresoc.v:128471.3-128479.6" + process $proc$libresoc.v:128471$5803 + assign { } { } + assign { } { } + assign $0\wri_l_r_wri$next[0:0]$5804 $1\wri_l_r_wri$next[0:0]$5805 + attribute \src "libresoc.v:128472.5-128472.29" + switch \initial + attribute \src "libresoc.v:128472.9-128472.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wri_l_r_wri$next[0:0]$5805 1'1 + case + assign $1\wri_l_r_wri$next[0:0]$5805 \$31 [0] + end + sync always + update \wri_l_r_wri$next $0\wri_l_r_wri$next[0:0]$5804 + end + attribute \src "libresoc.v:128480.3-128488.6" + process $proc$libresoc.v:128480$5806 + assign { } { } + assign { } { } + assign $0\upd_l_s_upd$next[0:0]$5807 $1\upd_l_s_upd$next[0:0]$5808 + attribute \src "libresoc.v:128481.5-128481.29" + switch \initial + attribute \src "libresoc.v:128481.9-128481.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\upd_l_s_upd$next[0:0]$5808 1'0 + case + assign $1\upd_l_s_upd$next[0:0]$5808 \reset_i + end + sync always + update \upd_l_s_upd$next $0\upd_l_s_upd$next[0:0]$5807 + end + attribute \src "libresoc.v:128489.3-128497.6" + process $proc$libresoc.v:128489$5809 + assign { } { } + assign { } { } + assign $0\upd_l_r_upd$next[0:0]$5810 $1\upd_l_r_upd$next[0:0]$5811 + attribute \src "libresoc.v:128490.5-128490.29" + switch \initial + attribute \src "libresoc.v:128490.9-128490.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\upd_l_r_upd$next[0:0]$5811 1'1 + case + assign $1\upd_l_r_upd$next[0:0]$5811 \reset_u + end + sync always + update \upd_l_r_upd$next $0\upd_l_r_upd$next[0:0]$5810 + end + attribute \src "libresoc.v:128498.3-128506.6" + process $proc$libresoc.v:128498$5812 + assign { } { } + assign { } { } + assign $0\sto_l_r_sto$next[0:0]$5813 $1\sto_l_r_sto$next[0:0]$5814 + attribute \src "libresoc.v:128499.5-128499.29" + switch \initial + attribute \src "libresoc.v:128499.9-128499.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\sto_l_r_sto$next[0:0]$5814 1'1 + case + assign $1\sto_l_r_sto$next[0:0]$5814 \$52 + end + sync always + update \sto_l_r_sto$next $0\sto_l_r_sto$next[0:0]$5813 + end + attribute \src "libresoc.v:128507.3-128515.6" + process $proc$libresoc.v:128507$5815 + assign { } { } + assign { } { } + assign $0\lsd_l_r_lsd$next[0:0]$5816 $1\lsd_l_r_lsd$next[0:0]$5817 + attribute \src "libresoc.v:128508.5-128508.29" + switch \initial + attribute \src "libresoc.v:128508.9-128508.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\lsd_l_r_lsd$next[0:0]$5817 1'1 + case + assign $1\lsd_l_r_lsd$next[0:0]$5817 \$56 + end + sync always + update \lsd_l_r_lsd$next $0\lsd_l_r_lsd$next[0:0]$5816 + end + attribute \src "libresoc.v:128516.3-128558.6" + process $proc$libresoc.v:128516$5818 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\oper_r__byte_reverse$next[0:0]$5819 $2\oper_r__byte_reverse$next[0:0]$5851 + assign $0\oper_r__data_len$next[3:0]$5820 $2\oper_r__data_len$next[3:0]$5852 + assign $0\oper_r__fn_unit$next[11:0]$5821 $2\oper_r__fn_unit$next[11:0]$5853 + assign { } { } + assign { } { } + assign $0\oper_r__insn$next[31:0]$5824 $2\oper_r__insn$next[31:0]$5856 + assign $0\oper_r__insn_type$next[6:0]$5825 $2\oper_r__insn_type$next[6:0]$5857 + assign $0\oper_r__is_32bit$next[0:0]$5826 $2\oper_r__is_32bit$next[0:0]$5858 + assign $0\oper_r__is_signed$next[0:0]$5827 $2\oper_r__is_signed$next[0:0]$5859 + assign $0\oper_r__ldst_mode$next[1:0]$5828 $2\oper_r__ldst_mode$next[1:0]$5860 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\oper_r__sign_extend$next[0:0]$5833 $2\oper_r__sign_extend$next[0:0]$5865 + assign $0\oper_r__zero_a$next[0:0]$5834 $2\oper_r__zero_a$next[0:0]$5866 + assign $0\oper_r__imm_data__data$next[63:0]$5822 $3\oper_r__imm_data__data$next[63:0]$5867 + assign $0\oper_r__imm_data__ok$next[0:0]$5823 $3\oper_r__imm_data__ok$next[0:0]$5868 + assign $0\oper_r__oe__oe$next[0:0]$5829 $3\oper_r__oe__oe$next[0:0]$5869 + assign $0\oper_r__oe__ok$next[0:0]$5830 $3\oper_r__oe__ok$next[0:0]$5870 + assign $0\oper_r__rc__ok$next[0:0]$5831 $3\oper_r__rc__ok$next[0:0]$5871 + assign $0\oper_r__rc__rc$next[0:0]$5832 $3\oper_r__rc__rc$next[0:0]$5872 + attribute \src "libresoc.v:128517.5-128517.29" + switch \initial + attribute \src "libresoc.v:128517.9-128517.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:378" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\oper_r__insn$next[31:0]$5840 $1\oper_r__ldst_mode$next[1:0]$5844 $1\oper_r__sign_extend$next[0:0]$5849 $1\oper_r__byte_reverse$next[0:0]$5835 $1\oper_r__data_len$next[3:0]$5836 $1\oper_r__is_signed$next[0:0]$5843 $1\oper_r__is_32bit$next[0:0]$5842 $1\oper_r__oe__ok$next[0:0]$5846 $1\oper_r__oe__oe$next[0:0]$5845 $1\oper_r__rc__ok$next[0:0]$5847 $1\oper_r__rc__rc$next[0:0]$5848 $1\oper_r__zero_a$next[0:0]$5850 $1\oper_r__imm_data__ok$next[0:0]$5839 $1\oper_r__imm_data__data$next[63:0]$5838 $1\oper_r__fn_unit$next[11:0]$5837 $1\oper_r__insn_type$next[6:0]$5841 } { \oper_i_ldst_ldst0__insn \oper_i_ldst_ldst0__ldst_mode \oper_i_ldst_ldst0__sign_extend \oper_i_ldst_ldst0__byte_reverse \oper_i_ldst_ldst0__data_len \oper_i_ldst_ldst0__is_signed \oper_i_ldst_ldst0__is_32bit \oper_i_ldst_ldst0__oe__ok \oper_i_ldst_ldst0__oe__oe \oper_i_ldst_ldst0__rc__ok \oper_i_ldst_ldst0__rc__rc \oper_i_ldst_ldst0__zero_a \oper_i_ldst_ldst0__imm_data__ok \oper_i_ldst_ldst0__imm_data__data \oper_i_ldst_ldst0__fn_unit \oper_i_ldst_ldst0__insn_type } + case + assign $1\oper_r__byte_reverse$next[0:0]$5835 \oper_r__byte_reverse + assign $1\oper_r__data_len$next[3:0]$5836 \oper_r__data_len + assign $1\oper_r__fn_unit$next[11:0]$5837 \oper_r__fn_unit + assign $1\oper_r__imm_data__data$next[63:0]$5838 \oper_r__imm_data__data + assign $1\oper_r__imm_data__ok$next[0:0]$5839 \oper_r__imm_data__ok + assign $1\oper_r__insn$next[31:0]$5840 \oper_r__insn + assign $1\oper_r__insn_type$next[6:0]$5841 \oper_r__insn_type + assign $1\oper_r__is_32bit$next[0:0]$5842 \oper_r__is_32bit + assign $1\oper_r__is_signed$next[0:0]$5843 \oper_r__is_signed + assign $1\oper_r__ldst_mode$next[1:0]$5844 \oper_r__ldst_mode + assign $1\oper_r__oe__oe$next[0:0]$5845 \oper_r__oe__oe + assign $1\oper_r__oe__ok$next[0:0]$5846 \oper_r__oe__ok + assign $1\oper_r__rc__ok$next[0:0]$5847 \oper_r__rc__ok + assign $1\oper_r__rc__rc$next[0:0]$5848 \oper_r__rc__rc + assign $1\oper_r__sign_extend$next[0:0]$5849 \oper_r__sign_extend + assign $1\oper_r__zero_a$next[0:0]$5850 \oper_r__zero_a + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:380" + switch \cu_done_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $2\oper_r__insn$next[31:0]$5856 $2\oper_r__ldst_mode$next[1:0]$5860 $2\oper_r__sign_extend$next[0:0]$5865 $2\oper_r__byte_reverse$next[0:0]$5851 $2\oper_r__data_len$next[3:0]$5852 $2\oper_r__is_signed$next[0:0]$5859 $2\oper_r__is_32bit$next[0:0]$5858 $2\oper_r__oe__ok$next[0:0]$5862 $2\oper_r__oe__oe$next[0:0]$5861 $2\oper_r__rc__ok$next[0:0]$5863 $2\oper_r__rc__rc$next[0:0]$5864 $2\oper_r__zero_a$next[0:0]$5866 $2\oper_r__imm_data__ok$next[0:0]$5855 $2\oper_r__imm_data__data$next[63:0]$5854 $2\oper_r__fn_unit$next[11:0]$5853 $2\oper_r__insn_type$next[6:0]$5857 } 131'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + case + assign $2\oper_r__byte_reverse$next[0:0]$5851 $1\oper_r__byte_reverse$next[0:0]$5835 + assign $2\oper_r__data_len$next[3:0]$5852 $1\oper_r__data_len$next[3:0]$5836 + assign $2\oper_r__fn_unit$next[11:0]$5853 $1\oper_r__fn_unit$next[11:0]$5837 + assign $2\oper_r__imm_data__data$next[63:0]$5854 $1\oper_r__imm_data__data$next[63:0]$5838 + assign $2\oper_r__imm_data__ok$next[0:0]$5855 $1\oper_r__imm_data__ok$next[0:0]$5839 + assign $2\oper_r__insn$next[31:0]$5856 $1\oper_r__insn$next[31:0]$5840 + assign $2\oper_r__insn_type$next[6:0]$5857 $1\oper_r__insn_type$next[6:0]$5841 + assign $2\oper_r__is_32bit$next[0:0]$5858 $1\oper_r__is_32bit$next[0:0]$5842 + assign $2\oper_r__is_signed$next[0:0]$5859 $1\oper_r__is_signed$next[0:0]$5843 + assign $2\oper_r__ldst_mode$next[1:0]$5860 $1\oper_r__ldst_mode$next[1:0]$5844 + assign $2\oper_r__oe__oe$next[0:0]$5861 $1\oper_r__oe__oe$next[0:0]$5845 + assign $2\oper_r__oe__ok$next[0:0]$5862 $1\oper_r__oe__ok$next[0:0]$5846 + assign $2\oper_r__rc__ok$next[0:0]$5863 $1\oper_r__rc__ok$next[0:0]$5847 + assign $2\oper_r__rc__rc$next[0:0]$5864 $1\oper_r__rc__rc$next[0:0]$5848 + assign $2\oper_r__sign_extend$next[0:0]$5865 $1\oper_r__sign_extend$next[0:0]$5849 + assign $2\oper_r__zero_a$next[0:0]$5866 $1\oper_r__zero_a$next[0:0]$5850 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $3\oper_r__imm_data__data$next[63:0]$5867 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\oper_r__imm_data__ok$next[0:0]$5868 1'0 + assign $3\oper_r__rc__rc$next[0:0]$5872 1'0 + assign $3\oper_r__rc__ok$next[0:0]$5871 1'0 + assign $3\oper_r__oe__oe$next[0:0]$5869 1'0 + assign $3\oper_r__oe__ok$next[0:0]$5870 1'0 + case + assign $3\oper_r__imm_data__data$next[63:0]$5867 $2\oper_r__imm_data__data$next[63:0]$5854 + assign $3\oper_r__imm_data__ok$next[0:0]$5868 $2\oper_r__imm_data__ok$next[0:0]$5855 + assign $3\oper_r__oe__oe$next[0:0]$5869 $2\oper_r__oe__oe$next[0:0]$5861 + assign $3\oper_r__oe__ok$next[0:0]$5870 $2\oper_r__oe__ok$next[0:0]$5862 + assign $3\oper_r__rc__ok$next[0:0]$5871 $2\oper_r__rc__ok$next[0:0]$5863 + assign $3\oper_r__rc__rc$next[0:0]$5872 $2\oper_r__rc__rc$next[0:0]$5864 + end + sync always + update \oper_r__byte_reverse$next $0\oper_r__byte_reverse$next[0:0]$5819 + update \oper_r__data_len$next $0\oper_r__data_len$next[3:0]$5820 + update \oper_r__fn_unit$next $0\oper_r__fn_unit$next[11:0]$5821 + update \oper_r__imm_data__data$next $0\oper_r__imm_data__data$next[63:0]$5822 + update \oper_r__imm_data__ok$next $0\oper_r__imm_data__ok$next[0:0]$5823 + update \oper_r__insn$next $0\oper_r__insn$next[31:0]$5824 + update \oper_r__insn_type$next $0\oper_r__insn_type$next[6:0]$5825 + update \oper_r__is_32bit$next $0\oper_r__is_32bit$next[0:0]$5826 + update \oper_r__is_signed$next $0\oper_r__is_signed$next[0:0]$5827 + update \oper_r__ldst_mode$next $0\oper_r__ldst_mode$next[1:0]$5828 + update \oper_r__oe__oe$next $0\oper_r__oe__oe$next[0:0]$5829 + update \oper_r__oe__ok$next $0\oper_r__oe__ok$next[0:0]$5830 + update \oper_r__rc__ok$next $0\oper_r__rc__ok$next[0:0]$5831 + update \oper_r__rc__rc$next $0\oper_r__rc__rc$next[0:0]$5832 + update \oper_r__sign_extend$next $0\oper_r__sign_extend$next[0:0]$5833 + update \oper_r__zero_a$next $0\oper_r__zero_a$next[0:0]$5834 + end + attribute \src "libresoc.v:128559.3-128568.6" + process $proc$libresoc.v:128559$5873 + assign { } { } + assign { } { } + assign $0\ldo_r$next[63:0]$5874 $1\ldo_r$next[63:0]$5875 + attribute \src "libresoc.v:128560.5-128560.29" + switch \initial + attribute \src "libresoc.v:128560.9-128560.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch \ld_ok + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ldo_r$next[63:0]$5875 \ldd_o + case + assign $1\ldo_r$next[63:0]$5875 \ldo_r + end + sync always + update \ldo_r$next $0\ldo_r$next[63:0]$5874 + end + attribute \src "libresoc.v:128569.3-128584.6" + process $proc$libresoc.v:128569$5876 + assign { } { } + assign { } { } + assign { } { } + assign $0\src_r0$next[63:0]$5877 $2\src_r0$next[63:0]$5879 + attribute \src "libresoc.v:128570.5-128570.29" + switch \initial + attribute \src "libresoc.v:128570.9-128570.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:392" + switch \cu_rd__go_i [0] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r0$next[63:0]$5878 \src1_i + case + assign $1\src_r0$next[63:0]$5878 \src_r0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:394" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src_r0$next[63:0]$5879 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $2\src_r0$next[63:0]$5879 $1\src_r0$next[63:0]$5878 + end + sync always + update \src_r0$next $0\src_r0$next[63:0]$5877 + end + attribute \src "libresoc.v:128585.3-128600.6" + process $proc$libresoc.v:128585$5880 + assign { } { } + assign { } { } + assign { } { } + assign $0\src_r1$next[63:0]$5881 $2\src_r1$next[63:0]$5883 + attribute \src "libresoc.v:128586.5-128586.29" + switch \initial + attribute \src "libresoc.v:128586.9-128586.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:392" + switch \cu_rd__go_i [1] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r1$next[63:0]$5882 \src2_i + case + assign $1\src_r1$next[63:0]$5882 \src_r1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:394" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src_r1$next[63:0]$5883 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $2\src_r1$next[63:0]$5883 $1\src_r1$next[63:0]$5882 + end + sync always + update \src_r1$next $0\src_r1$next[63:0]$5881 + end + attribute \src "libresoc.v:128601.3-128616.6" + process $proc$libresoc.v:128601$5884 + assign { } { } + assign { } { } + assign { } { } + assign $0\src_r2$next[63:0]$5885 $2\src_r2$next[63:0]$5887 + attribute \src "libresoc.v:128602.5-128602.29" + switch \initial + attribute \src "libresoc.v:128602.9-128602.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:392" + switch \cu_rd__go_i [2] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r2$next[63:0]$5886 \src3_i + case + assign $1\src_r2$next[63:0]$5886 \src_r2 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:394" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src_r2$next[63:0]$5887 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $2\src_r2$next[63:0]$5887 $1\src_r2$next[63:0]$5886 + end + sync always + update \src_r2$next $0\src_r2$next[63:0]$5885 + end + attribute \src "libresoc.v:128617.3-128626.6" + process $proc$libresoc.v:128617$5888 + assign { } { } + assign { } { } + assign $0\ea_r$next[63:0]$5889 $1\ea_r$next[63:0]$5890 + attribute \src "libresoc.v:128618.5-128618.29" + switch \initial + attribute \src "libresoc.v:128618.9-128618.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch \alu_l_q_alu + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ea_r$next[63:0]$5890 \alu_o + case + assign $1\ea_r$next[63:0]$5890 \ea_r + end + sync always + update \ea_r$next $0\ea_r$next[63:0]$5889 + end + attribute \src "libresoc.v:128627.3-128636.6" + process $proc$libresoc.v:128627$5891 + assign { } { } + assign { } { } + assign $0\dest1_o[63:0] $1\dest1_o[63:0] + attribute \src "libresoc.v:128628.5-128628.29" + switch \initial + attribute \src "libresoc.v:128628.9-128628.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:471" + switch \cu_wr__go_i [0] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest1_o[63:0] \ldd_r + case + assign $1\dest1_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \dest1_o $0\dest1_o[63:0] + end + attribute \src "libresoc.v:128637.3-128646.6" + process $proc$libresoc.v:128637$5892 + assign { } { } + assign { } { } + assign $0\dest2_o[63:0] $1\dest2_o[63:0] + attribute \src "libresoc.v:128638.5-128638.29" + switch \initial + attribute \src "libresoc.v:128638.9-128638.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:476" + switch \$157 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest2_o[63:0] \addr_r + case + assign $1\dest2_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \dest2_o $0\dest2_o[63:0] + end + attribute \src "libresoc.v:128647.3-128655.6" + process $proc$libresoc.v:128647$5893 + assign { } { } + assign { } { } + assign $0\ldst_port0_addr_i_ok$next[0:0]$5894 $1\ldst_port0_addr_i_ok$next[0:0]$5895 + attribute \src "libresoc.v:128648.5-128648.29" + switch \initial + attribute \src "libresoc.v:128648.9-128648.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ldst_port0_addr_i_ok$next[0:0]$5895 1'0 + case + assign $1\ldst_port0_addr_i_ok$next[0:0]$5895 \$170 + end + sync always + update \ldst_port0_addr_i_ok$next $0\ldst_port0_addr_i_ok$next[0:0]$5894 + end + attribute \src "libresoc.v:128656.3-128679.6" + process $proc$libresoc.v:128656$5896 + assign { } { } + assign { } { } + assign $0\lddata_r[63:0] $1\lddata_r[63:0] + attribute \src "libresoc.v:128657.5-128657.29" + switch \initial + attribute \src "libresoc.v:128657.9-128657.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:499" + switch \oper_r__byte_reverse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\lddata_r[63:0] $2\lddata_r[63:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:22" + switch \oper_r__data_len + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $2\lddata_r[63:0] \$172 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $2\lddata_r[63:0] \$174 + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $2\lddata_r[63:0] \$176 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $2\lddata_r[63:0] { \ldst_port0_ld_data_o [7:0] \ldst_port0_ld_data_o [15:8] \ldst_port0_ld_data_o [23:16] \ldst_port0_ld_data_o [31:24] \ldst_port0_ld_data_o [39:32] \ldst_port0_ld_data_o [47:40] \ldst_port0_ld_data_o [55:48] \ldst_port0_ld_data_o [63:56] } + case + assign $2\lddata_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + case + assign $1\lddata_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \lddata_r $0\lddata_r[63:0] + end + attribute \src "libresoc.v:128680.3-128691.6" + process $proc$libresoc.v:128680$5897 + assign { } { } + assign $0\revnorev[63:0] $1\revnorev[63:0] + attribute \src "libresoc.v:128681.5-128681.29" + switch \initial + attribute \src "libresoc.v:128681.9-128681.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:499" + switch \oper_r__byte_reverse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\revnorev[63:0] \lddata_r + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\revnorev[63:0] \ldst_port0_ld_data_o + end + sync always + update \revnorev $0\revnorev[63:0] + end + attribute \src "libresoc.v:128692.3-128711.6" + process $proc$libresoc.v:128692$5898 + assign { } { } + assign $0\ldd_o[63:0] $1\ldd_o[63:0] + attribute \src "libresoc.v:128693.5-128693.29" + switch \initial + attribute \src "libresoc.v:128693.9-128693.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:508" + switch \oper_r__sign_extend + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ldd_o[63:0] $2\ldd_o[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:510" + switch \$178 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ldd_o[63:0] { \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15:0] } + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\ldd_o[63:0] { \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31:0] } + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\ldd_o[63:0] \revnorev + end + sync always + update \ldd_o $0\ldd_o[63:0] + end + attribute \src "libresoc.v:128712.3-128735.6" + process $proc$libresoc.v:128712$5899 + assign { } { } + assign { } { } + assign $0\stdata_r[63:0] $1\stdata_r[63:0] + attribute \src "libresoc.v:128713.5-128713.29" + switch \initial + attribute \src "libresoc.v:128713.9-128713.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:522" + switch \oper_r__byte_reverse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\stdata_r[63:0] $2\stdata_r[63:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:22" + switch \oper_r__data_len + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $2\stdata_r[63:0] \$180 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $2\stdata_r[63:0] \$182 + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $2\stdata_r[63:0] \$184 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $2\stdata_r[63:0] { \src_r2 [7:0] \src_r2 [15:8] \src_r2 [23:16] \src_r2 [31:24] \src_r2 [39:32] \src_r2 [47:40] \src_r2 [55:48] \src_r2 [63:56] } + case + assign $2\stdata_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + case + assign $1\stdata_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \stdata_r $0\stdata_r[63:0] + end + attribute \src "libresoc.v:128736.3-128747.6" + process $proc$libresoc.v:128736$5900 + assign { } { } + assign $0\ldst_port0_st_data_i[63:0] $1\ldst_port0_st_data_i[63:0] + attribute \src "libresoc.v:128737.5-128737.29" + switch \initial + attribute \src "libresoc.v:128737.9-128737.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:522" + switch \oper_r__byte_reverse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ldst_port0_st_data_i[63:0] \stdata_r + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\ldst_port0_st_data_i[63:0] \src_r2 + end + sync always + update \ldst_port0_st_data_i $0\ldst_port0_st_data_i[63:0] + end + connect \$9 $or$libresoc.v:128195$5659_Y + connect \$99 $and$libresoc.v:128196$5660_Y + connect \$101 $and$libresoc.v:128197$5661_Y + connect \$103 $and$libresoc.v:128198$5662_Y + connect \$105 $and$libresoc.v:128199$5663_Y + connect \$107 $and$libresoc.v:128200$5664_Y + connect \$109 $and$libresoc.v:128201$5665_Y + connect \$111 $and$libresoc.v:128202$5666_Y + connect \$113 $and$libresoc.v:128203$5667_Y + connect \$115 $and$libresoc.v:128204$5668_Y + connect \$117 $and$libresoc.v:128205$5669_Y + connect \$11 $or$libresoc.v:128206$5670_Y + connect \$119 $eq$libresoc.v:128207$5671_Y + connect \$121 $and$libresoc.v:128208$5672_Y + connect \$123 $and$libresoc.v:128209$5673_Y + connect \$125 $and$libresoc.v:128210$5674_Y + connect \$127 $or$libresoc.v:128211$5675_Y + connect \$129 $or$libresoc.v:128212$5676_Y + connect \$131 $or$libresoc.v:128213$5677_Y + connect \$133 $and$libresoc.v:128214$5678_Y + connect \$135 $and$libresoc.v:128215$5679_Y + connect \$138 $or$libresoc.v:128216$5680_Y + connect \$13 $or$libresoc.v:128217$5681_Y + connect \$140 $or$libresoc.v:128218$5682_Y + connect \$137 $not$libresoc.v:128219$5683_Y + connect \$143 $and$libresoc.v:128220$5684_Y + connect \$145 $or$libresoc.v:128221$5685_Y + connect \$147 $and$libresoc.v:128222$5686_Y + connect \$149 $not$libresoc.v:128223$5687_Y + connect \$151 $or$libresoc.v:128224$5688_Y + connect \$153 $and$libresoc.v:128225$5689_Y + connect \$155 $eq$libresoc.v:128226$5690_Y + connect \$157 $and$libresoc.v:128227$5691_Y + connect \$15 $eq$libresoc.v:128228$5692_Y + connect \$160 $eq$libresoc.v:128229$5693_Y + connect \$162 $and$libresoc.v:128230$5694_Y + connect \$164 $and$libresoc.v:128231$5695_Y + connect \$166 $and$libresoc.v:128232$5696_Y + connect \$168 $pos$libresoc.v:128233$5698_Y + connect \$170 $and$libresoc.v:128234$5699_Y + connect \$172 $pos$libresoc.v:128235$5701_Y + connect \$174 $pos$libresoc.v:128236$5702_Y + connect \$176 $pos$libresoc.v:128237$5703_Y + connect \$178 $eq$libresoc.v:128238$5704_Y + connect \$17 $eq$libresoc.v:128239$5705_Y + connect \$180 $pos$libresoc.v:128240$5707_Y + connect \$182 $pos$libresoc.v:128241$5708_Y + connect \$184 $pos$libresoc.v:128242$5709_Y + connect \$1 $or$libresoc.v:128243$5710_Y + connect \$19 $and$libresoc.v:128244$5711_Y + connect \$21 $and$libresoc.v:128245$5712_Y + connect \$23 $not$libresoc.v:128246$5713_Y + connect \$25 $and$libresoc.v:128247$5714_Y + connect \$27 $not$libresoc.v:128248$5715_Y + connect \$29 $and$libresoc.v:128249$5716_Y + connect \$32 $not$libresoc.v:128250$5717_Y + connect \$34 $eq$libresoc.v:128251$5718_Y + connect \$36 $and$libresoc.v:128252$5719_Y + connect \$38 $or$libresoc.v:128253$5720_Y + connect \$3 $or$libresoc.v:128254$5721_Y + connect \$40 $not$libresoc.v:128255$5722_Y + connect \$42 $eq$libresoc.v:128256$5723_Y + connect \$44 $and$libresoc.v:128257$5724_Y + connect \$46 $or$libresoc.v:128258$5725_Y + connect \$48 $or$libresoc.v:128259$5726_Y + connect \$50 $and$libresoc.v:128260$5727_Y + connect \$52 $or$libresoc.v:128261$5728_Y + connect \$54 $or$libresoc.v:128262$5729_Y + connect \$56 $or$libresoc.v:128263$5730_Y + connect \$58 $ternary$libresoc.v:128264$5731_Y + connect \$5 $or$libresoc.v:128265$5732_Y + connect \$60 $ternary$libresoc.v:128266$5733_Y + connect \$62 $ternary$libresoc.v:128267$5734_Y + connect \$64 $ternary$libresoc.v:128268$5735_Y + connect \$67 $add$libresoc.v:128269$5736_Y + connect \$69 $and$libresoc.v:128270$5737_Y + connect \$71 $not$libresoc.v:128271$5738_Y + connect \$73 $and$libresoc.v:128272$5739_Y + connect \$75 $not$libresoc.v:128273$5740_Y + connect \$77 $and$libresoc.v:128274$5741_Y + connect \$7 $or$libresoc.v:128275$5742_Y + connect \$79 $and$libresoc.v:128276$5743_Y + connect \$81 $and$libresoc.v:128277$5744_Y + connect \$83 $or$libresoc.v:128278$5745_Y + connect \$86 $or$libresoc.v:128279$5746_Y + connect \$85 $not$libresoc.v:128280$5747_Y + connect \$89 $and$libresoc.v:128281$5748_Y + connect \$91 $not$libresoc.v:128282$5749_Y + connect \$93 $and$libresoc.v:128283$5750_Y + connect \$95 $and$libresoc.v:128284$5751_Y + connect \$97 $and$libresoc.v:128285$5752_Y + connect \$31 \$48 + connect \$66 \$67 + connect \$159 \$162 + connect \cu_go_die_i 1'0 + connect \cu_shadown_i 1'1 + connect \ldst_port0_st_data_i_ok \cu_st__go_i + connect \ld_ok \ldst_port0_ld_data_o_ok + connect \addr_ok \ldst_port0_addr_ok_o + connect \addr_exc_o \ldst_port0_addr_exc_o + connect \ldst_port0_addr_i$next \$168 + connect \ldst_port0_data_len \oper_r__data_len + connect \ldst_port0_is_st_i \$166 + connect \ldst_port0_is_ld_i \$164 + connect \cu_wrmask_o \$162 [1:0] + connect \ea \dest2_o + connect \o \dest1_o + connect \cu_done_o \$153 + connect \wr_reset \$147 + connect \wr_any \$131 + connect \cu_wr__rel_o [1] \$125 + connect \cu_wr__rel_o [0] \$115 + connect \cu_st__rel_o \$105 + connect \cu_ad__rel_o \$97 + connect \rd_done \$93 + connect \alu_valid \$89 + connect \rda_any \$83 + connect \cu_rd__rel_o [2] \$81 + connect \cu_rd__rel_o [1:0] \$77 [1:0] + connect \cu_busy_o \opc_l_q_opc + connect \alu_ok$next \alu_valid + connect \alu_o \$67 [63:0] + connect \src2_or_imm \$64 + connect \src1_or_z \$62 + connect \addr_r \$60 + connect \ldd_r \$58 + connect \rst_l_r_rst \cu_issue_i + connect \rst_l_s_rst \addr_ok + connect \lsd_l_s_lsd \cu_issue_i + connect \sto_l_s_sto \$50 + connect \wri_l_s_wri \cu_issue_i + connect \lod_l_r_lod \ld_ok + connect \lod_l_s_lod \reset_i + connect \adr_l_s_adr \reset_i + connect \alu_l_r_alu \$29 + connect \alu_l_s_alu \reset_i + connect \st_o \op_is_st + connect \ld_o \op_is_ld + connect \stwd_mem_o \$21 + connect \load_mem_o \$19 + connect \op_is_ld \$17 + connect \op_is_st \$15 + connect \p_st_go$next \cu_st__go_i + connect \reset_a \$13 + connect \reset_r \$11 + connect \reset_s \$9 + connect \reset_u \$7 + connect \reset_w \$5 + connect \reset_o \$3 + connect \reset_i \$1 +end +attribute \src "libresoc.v:128811.1-129398.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.pipe1.main.rotator.left_mask" +attribute \generator "nMigen" +module \left_mask + attribute \src "libresoc.v:128812.7-128812.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:129010.3-129397.6" + wire width 64 $0\mask[63:0] + attribute \src "libresoc.v:129010.3-129397.6" + wire $10\mask[9:9] + attribute \src "libresoc.v:129010.3-129397.6" + wire $11\mask[10:10] + attribute \src "libresoc.v:129010.3-129397.6" + wire $12\mask[11:11] + attribute \src "libresoc.v:129010.3-129397.6" + wire $13\mask[12:12] + attribute \src "libresoc.v:129010.3-129397.6" + wire $14\mask[13:13] + attribute \src "libresoc.v:129010.3-129397.6" + wire $15\mask[14:14] + attribute \src "libresoc.v:129010.3-129397.6" + wire $16\mask[15:15] + attribute \src "libresoc.v:129010.3-129397.6" + wire $17\mask[16:16] + attribute \src "libresoc.v:129010.3-129397.6" + wire $18\mask[17:17] + attribute \src "libresoc.v:129010.3-129397.6" + wire $19\mask[18:18] + attribute \src "libresoc.v:129010.3-129397.6" + wire $1\mask[0:0] + attribute \src "libresoc.v:129010.3-129397.6" + wire $20\mask[19:19] + attribute \src "libresoc.v:129010.3-129397.6" + wire $21\mask[20:20] + attribute \src "libresoc.v:129010.3-129397.6" + wire $22\mask[21:21] + attribute \src "libresoc.v:129010.3-129397.6" + wire $23\mask[22:22] + attribute \src "libresoc.v:129010.3-129397.6" + wire $24\mask[23:23] + attribute \src "libresoc.v:129010.3-129397.6" + wire $25\mask[24:24] + attribute \src "libresoc.v:129010.3-129397.6" + wire $26\mask[25:25] + attribute \src "libresoc.v:129010.3-129397.6" + wire $27\mask[26:26] + attribute \src "libresoc.v:129010.3-129397.6" + wire $28\mask[27:27] + attribute \src "libresoc.v:129010.3-129397.6" + wire $29\mask[28:28] + attribute \src "libresoc.v:129010.3-129397.6" + wire $2\mask[1:1] + attribute \src "libresoc.v:129010.3-129397.6" + wire $30\mask[29:29] + attribute \src "libresoc.v:129010.3-129397.6" + wire $31\mask[30:30] + attribute \src "libresoc.v:129010.3-129397.6" + wire $32\mask[31:31] + attribute \src "libresoc.v:129010.3-129397.6" + wire $33\mask[32:32] + attribute \src "libresoc.v:129010.3-129397.6" + wire $34\mask[33:33] + attribute \src "libresoc.v:129010.3-129397.6" + wire $35\mask[34:34] + attribute \src "libresoc.v:129010.3-129397.6" + wire $36\mask[35:35] + attribute \src "libresoc.v:129010.3-129397.6" + wire $37\mask[36:36] + attribute \src "libresoc.v:129010.3-129397.6" + wire $38\mask[37:37] + attribute \src "libresoc.v:129010.3-129397.6" + wire $39\mask[38:38] + attribute \src "libresoc.v:129010.3-129397.6" + wire $3\mask[2:2] + attribute \src "libresoc.v:129010.3-129397.6" + wire $40\mask[39:39] + attribute \src "libresoc.v:129010.3-129397.6" + wire $41\mask[40:40] + attribute \src "libresoc.v:129010.3-129397.6" + wire $42\mask[41:41] + attribute \src "libresoc.v:129010.3-129397.6" + wire $43\mask[42:42] + attribute \src "libresoc.v:129010.3-129397.6" + wire $44\mask[43:43] + attribute \src "libresoc.v:129010.3-129397.6" + wire $45\mask[44:44] + attribute \src "libresoc.v:129010.3-129397.6" + wire $46\mask[45:45] + attribute \src "libresoc.v:129010.3-129397.6" + wire $47\mask[46:46] + attribute \src "libresoc.v:129010.3-129397.6" + wire $48\mask[47:47] + attribute \src "libresoc.v:129010.3-129397.6" + wire $49\mask[48:48] + attribute \src "libresoc.v:129010.3-129397.6" + wire $4\mask[3:3] + attribute \src "libresoc.v:129010.3-129397.6" + wire $50\mask[49:49] + attribute \src "libresoc.v:129010.3-129397.6" + wire $51\mask[50:50] + attribute \src "libresoc.v:129010.3-129397.6" + wire $52\mask[51:51] + attribute \src "libresoc.v:129010.3-129397.6" + wire $53\mask[52:52] + attribute \src "libresoc.v:129010.3-129397.6" + wire $54\mask[53:53] + attribute \src "libresoc.v:129010.3-129397.6" + wire $55\mask[54:54] + attribute \src "libresoc.v:129010.3-129397.6" + wire $56\mask[55:55] + attribute \src "libresoc.v:129010.3-129397.6" + wire $57\mask[56:56] + attribute \src "libresoc.v:129010.3-129397.6" + wire $58\mask[57:57] + attribute \src "libresoc.v:129010.3-129397.6" + wire $59\mask[58:58] + attribute \src "libresoc.v:129010.3-129397.6" + wire $5\mask[4:4] + attribute \src "libresoc.v:129010.3-129397.6" + wire $60\mask[59:59] + attribute \src "libresoc.v:129010.3-129397.6" + wire $61\mask[60:60] + attribute \src "libresoc.v:129010.3-129397.6" + wire $62\mask[61:61] + attribute \src "libresoc.v:129010.3-129397.6" + wire $63\mask[62:62] + attribute \src "libresoc.v:129010.3-129397.6" + wire $64\mask[63:63] + attribute \src "libresoc.v:129010.3-129397.6" + wire $6\mask[5:5] + attribute \src "libresoc.v:129010.3-129397.6" + wire $7\mask[6:6] + attribute \src "libresoc.v:129010.3-129397.6" + wire $8\mask[7:7] + attribute \src "libresoc.v:129010.3-129397.6" + wire $9\mask[8:8] + attribute \src "libresoc.v:128946.17-128946.96" + wire $gt$libresoc.v:128946$5937_Y + attribute \src "libresoc.v:128947.18-128947.98" + wire $gt$libresoc.v:128947$5938_Y + attribute \src "libresoc.v:128948.19-128948.99" + wire $gt$libresoc.v:128948$5939_Y + attribute \src "libresoc.v:128949.19-128949.99" + wire $gt$libresoc.v:128949$5940_Y + attribute \src "libresoc.v:128950.19-128950.99" + wire $gt$libresoc.v:128950$5941_Y + attribute \src "libresoc.v:128951.19-128951.99" + wire $gt$libresoc.v:128951$5942_Y + attribute \src "libresoc.v:128952.19-128952.99" + wire $gt$libresoc.v:128952$5943_Y + attribute \src "libresoc.v:128953.19-128953.99" + wire $gt$libresoc.v:128953$5944_Y + attribute \src "libresoc.v:128954.19-128954.99" + wire $gt$libresoc.v:128954$5945_Y + attribute \src "libresoc.v:128955.19-128955.99" + wire $gt$libresoc.v:128955$5946_Y + attribute \src "libresoc.v:128956.19-128956.99" + wire $gt$libresoc.v:128956$5947_Y + attribute \src "libresoc.v:128957.18-128957.97" + wire $gt$libresoc.v:128957$5948_Y + attribute \src "libresoc.v:128958.19-128958.99" + wire $gt$libresoc.v:128958$5949_Y + attribute \src "libresoc.v:128959.19-128959.99" + wire $gt$libresoc.v:128959$5950_Y + attribute \src "libresoc.v:128960.19-128960.99" + wire $gt$libresoc.v:128960$5951_Y + attribute \src "libresoc.v:128961.19-128961.99" + wire $gt$libresoc.v:128961$5952_Y + attribute \src "libresoc.v:128962.19-128962.99" + wire $gt$libresoc.v:128962$5953_Y + attribute \src "libresoc.v:128963.18-128963.97" + wire $gt$libresoc.v:128963$5954_Y + attribute \src "libresoc.v:128964.18-128964.97" + wire $gt$libresoc.v:128964$5955_Y + attribute \src "libresoc.v:128965.18-128965.97" + wire $gt$libresoc.v:128965$5956_Y + attribute \src "libresoc.v:128966.17-128966.96" + wire $gt$libresoc.v:128966$5957_Y + attribute \src "libresoc.v:128967.18-128967.97" + wire $gt$libresoc.v:128967$5958_Y + attribute \src "libresoc.v:128968.18-128968.97" + wire $gt$libresoc.v:128968$5959_Y + attribute \src "libresoc.v:128969.18-128969.97" + wire $gt$libresoc.v:128969$5960_Y + attribute \src "libresoc.v:128970.18-128970.97" + wire $gt$libresoc.v:128970$5961_Y + attribute \src "libresoc.v:128971.18-128971.97" + wire $gt$libresoc.v:128971$5962_Y + attribute \src "libresoc.v:128972.18-128972.97" + wire $gt$libresoc.v:128972$5963_Y + attribute \src "libresoc.v:128973.18-128973.97" + wire $gt$libresoc.v:128973$5964_Y + attribute \src "libresoc.v:128974.18-128974.98" + wire $gt$libresoc.v:128974$5965_Y + attribute \src "libresoc.v:128975.18-128975.98" + wire $gt$libresoc.v:128975$5966_Y + attribute \src "libresoc.v:128976.18-128976.98" + wire $gt$libresoc.v:128976$5967_Y + attribute \src "libresoc.v:128977.17-128977.96" + wire $gt$libresoc.v:128977$5968_Y + attribute \src "libresoc.v:128978.18-128978.98" + wire $gt$libresoc.v:128978$5969_Y + attribute \src "libresoc.v:128979.18-128979.98" + wire $gt$libresoc.v:128979$5970_Y + attribute \src "libresoc.v:128980.18-128980.98" + wire $gt$libresoc.v:128980$5971_Y + attribute \src "libresoc.v:128981.18-128981.98" + wire $gt$libresoc.v:128981$5972_Y + attribute \src "libresoc.v:128982.18-128982.98" + wire $gt$libresoc.v:128982$5973_Y + attribute \src "libresoc.v:128983.18-128983.98" + wire $gt$libresoc.v:128983$5974_Y + attribute \src "libresoc.v:128984.18-128984.98" + wire $gt$libresoc.v:128984$5975_Y + attribute \src "libresoc.v:128985.18-128985.98" + wire $gt$libresoc.v:128985$5976_Y + attribute \src "libresoc.v:128986.18-128986.98" + wire $gt$libresoc.v:128986$5977_Y + attribute \src "libresoc.v:128987.18-128987.98" + wire $gt$libresoc.v:128987$5978_Y + attribute \src "libresoc.v:128988.17-128988.96" + wire $gt$libresoc.v:128988$5979_Y + attribute \src "libresoc.v:128989.18-128989.98" + wire $gt$libresoc.v:128989$5980_Y + attribute \src "libresoc.v:128990.18-128990.98" + wire $gt$libresoc.v:128990$5981_Y + attribute \src "libresoc.v:128991.18-128991.98" + wire $gt$libresoc.v:128991$5982_Y + attribute \src "libresoc.v:128992.18-128992.98" + wire $gt$libresoc.v:128992$5983_Y + attribute \src "libresoc.v:128993.18-128993.98" + wire $gt$libresoc.v:128993$5984_Y + attribute \src "libresoc.v:128994.18-128994.98" + wire $gt$libresoc.v:128994$5985_Y + attribute \src "libresoc.v:128995.18-128995.98" + wire $gt$libresoc.v:128995$5986_Y + attribute \src "libresoc.v:128996.18-128996.98" + wire $gt$libresoc.v:128996$5987_Y + attribute \src "libresoc.v:128997.18-128997.98" + wire $gt$libresoc.v:128997$5988_Y + attribute \src "libresoc.v:128998.18-128998.98" + wire $gt$libresoc.v:128998$5989_Y + attribute \src "libresoc.v:128999.17-128999.96" + wire $gt$libresoc.v:128999$5990_Y + attribute \src "libresoc.v:129000.18-129000.98" + wire $gt$libresoc.v:129000$5991_Y + attribute \src "libresoc.v:129001.18-129001.98" + wire $gt$libresoc.v:129001$5992_Y + attribute \src "libresoc.v:129002.18-129002.98" + wire $gt$libresoc.v:129002$5993_Y + attribute \src "libresoc.v:129003.18-129003.98" + wire $gt$libresoc.v:129003$5994_Y + attribute \src "libresoc.v:129004.18-129004.98" + wire $gt$libresoc.v:129004$5995_Y + attribute \src "libresoc.v:129005.18-129005.98" + wire $gt$libresoc.v:129005$5996_Y + attribute \src "libresoc.v:129006.18-129006.98" + wire $gt$libresoc.v:129006$5997_Y + attribute \src "libresoc.v:129007.18-129007.98" + wire $gt$libresoc.v:129007$5998_Y + attribute \src "libresoc.v:129008.18-129008.98" + wire $gt$libresoc.v:129008$5999_Y + attribute \src "libresoc.v:129009.18-129009.98" + wire $gt$libresoc.v:129009$6000_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$101 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$103 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$105 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$107 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$109 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$111 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$113 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$115 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$117 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$119 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$121 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$123 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$125 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$127 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$17 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$21 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$25 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$29 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$33 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$35 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$37 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$39 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$41 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$43 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$45 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$47 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$49 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$51 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$53 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$55 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$57 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$59 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$61 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$63 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$65 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$67 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$69 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$71 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$73 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$75 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$77 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$79 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$81 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$83 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$85 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$87 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$89 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$91 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$93 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$95 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$97 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$99 + attribute \src "libresoc.v:128812.7-128812.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:12" + wire width 64 output 1 \mask + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:11" + wire width 7 input 2 \shift + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:128946$5937 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 3'100 + connect \Y $gt$libresoc.v:128946$5937_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:128947$5938 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'110001 + connect \Y $gt$libresoc.v:128947$5938_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:128948$5939 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'110010 + connect \Y $gt$libresoc.v:128948$5939_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:128949$5940 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'110011 + connect \Y $gt$libresoc.v:128949$5940_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:128950$5941 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'110100 + connect \Y $gt$libresoc.v:128950$5941_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:128951$5942 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'110101 + connect \Y $gt$libresoc.v:128951$5942_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:128952$5943 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'110110 + connect \Y $gt$libresoc.v:128952$5943_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:128953$5944 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'110111 + connect \Y $gt$libresoc.v:128953$5944_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:128954$5945 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'111000 + connect \Y $gt$libresoc.v:128954$5945_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:128955$5946 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'111001 + connect \Y $gt$libresoc.v:128955$5946_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:128956$5947 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'111010 + connect \Y $gt$libresoc.v:128956$5947_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:128957$5948 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 3'101 + connect \Y $gt$libresoc.v:128957$5948_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:128958$5949 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'111011 + connect \Y $gt$libresoc.v:128958$5949_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:128959$5950 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'111100 + connect \Y $gt$libresoc.v:128959$5950_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:128960$5951 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'111101 + connect \Y $gt$libresoc.v:128960$5951_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:128961$5952 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'111110 + connect \Y $gt$libresoc.v:128961$5952_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:128962$5953 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'111111 + connect \Y $gt$libresoc.v:128962$5953_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:128963$5954 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 3'110 + connect \Y $gt$libresoc.v:128963$5954_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:128964$5955 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 3'111 + connect \Y $gt$libresoc.v:128964$5955_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:128965$5956 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 4'1000 + connect \Y $gt$libresoc.v:128965$5956_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:128966$5957 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 1'0 + connect \Y $gt$libresoc.v:128966$5957_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:128967$5958 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 4'1001 + connect \Y $gt$libresoc.v:128967$5958_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:128968$5959 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 4'1010 + connect \Y $gt$libresoc.v:128968$5959_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:128969$5960 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 4'1011 + connect \Y $gt$libresoc.v:128969$5960_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:128970$5961 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 4'1100 + connect \Y $gt$libresoc.v:128970$5961_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:128971$5962 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 4'1101 + connect \Y $gt$libresoc.v:128971$5962_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:128972$5963 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 4'1110 + connect \Y $gt$libresoc.v:128972$5963_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:128973$5964 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 4'1111 + connect \Y $gt$libresoc.v:128973$5964_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:128974$5965 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'10000 + connect \Y $gt$libresoc.v:128974$5965_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:128975$5966 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'10001 + connect \Y $gt$libresoc.v:128975$5966_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:128976$5967 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'10010 + connect \Y $gt$libresoc.v:128976$5967_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:128977$5968 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 1'1 + connect \Y $gt$libresoc.v:128977$5968_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:128978$5969 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'10011 + connect \Y $gt$libresoc.v:128978$5969_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:128979$5970 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'10100 + connect \Y $gt$libresoc.v:128979$5970_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:128980$5971 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'10101 + connect \Y $gt$libresoc.v:128980$5971_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:128981$5972 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'10110 + connect \Y $gt$libresoc.v:128981$5972_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:128982$5973 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'10111 + connect \Y $gt$libresoc.v:128982$5973_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:128983$5974 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'11000 + connect \Y $gt$libresoc.v:128983$5974_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:128984$5975 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'11001 + connect \Y $gt$libresoc.v:128984$5975_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:128985$5976 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'11010 + connect \Y $gt$libresoc.v:128985$5976_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:128986$5977 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'11011 + connect \Y $gt$libresoc.v:128986$5977_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:128987$5978 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'11100 + connect \Y $gt$libresoc.v:128987$5978_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:128988$5979 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 2'10 + connect \Y $gt$libresoc.v:128988$5979_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:128989$5980 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'11101 + connect \Y $gt$libresoc.v:128989$5980_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:128990$5981 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'11110 + connect \Y $gt$libresoc.v:128990$5981_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:128991$5982 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'11111 + connect \Y $gt$libresoc.v:128991$5982_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:128992$5983 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'100000 + connect \Y $gt$libresoc.v:128992$5983_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:128993$5984 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'100001 + connect \Y $gt$libresoc.v:128993$5984_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:128994$5985 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'100010 + connect \Y $gt$libresoc.v:128994$5985_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:128995$5986 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'100011 + connect \Y $gt$libresoc.v:128995$5986_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:128996$5987 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'100100 + connect \Y $gt$libresoc.v:128996$5987_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:128997$5988 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'100101 + connect \Y $gt$libresoc.v:128997$5988_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:128998$5989 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'100110 + connect \Y $gt$libresoc.v:128998$5989_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:128999$5990 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 2'11 + connect \Y $gt$libresoc.v:128999$5990_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:129000$5991 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'100111 + connect \Y $gt$libresoc.v:129000$5991_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:129001$5992 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'101000 + connect \Y $gt$libresoc.v:129001$5992_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:129002$5993 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'101001 + connect \Y $gt$libresoc.v:129002$5993_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:129003$5994 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'101010 + connect \Y $gt$libresoc.v:129003$5994_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:129004$5995 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'101011 + connect \Y $gt$libresoc.v:129004$5995_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:129005$5996 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'101100 + connect \Y $gt$libresoc.v:129005$5996_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:129006$5997 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'101101 + connect \Y $gt$libresoc.v:129006$5997_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:129007$5998 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'101110 + connect \Y $gt$libresoc.v:129007$5998_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:129008$5999 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'101111 + connect \Y $gt$libresoc.v:129008$5999_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:129009$6000 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'110000 + connect \Y $gt$libresoc.v:129009$6000_Y + end + attribute \src "libresoc.v:128812.7-128812.20" + process $proc$libresoc.v:128812$6002 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:129010.3-129397.6" + process $proc$libresoc.v:129010$6001 + assign { } { } + assign { } { } + assign $0\mask[63:0] [0] $1\mask[0:0] + assign $0\mask[63:0] [1] $2\mask[1:1] + assign $0\mask[63:0] [2] $3\mask[2:2] + assign $0\mask[63:0] [3] $4\mask[3:3] + assign $0\mask[63:0] [4] $5\mask[4:4] + assign $0\mask[63:0] [5] $6\mask[5:5] + assign $0\mask[63:0] [6] $7\mask[6:6] + assign $0\mask[63:0] [7] $8\mask[7:7] + assign $0\mask[63:0] [8] $9\mask[8:8] + assign $0\mask[63:0] [9] $10\mask[9:9] + assign $0\mask[63:0] [10] $11\mask[10:10] + assign $0\mask[63:0] [11] $12\mask[11:11] + assign $0\mask[63:0] [12] $13\mask[12:12] + assign $0\mask[63:0] [13] $14\mask[13:13] + assign $0\mask[63:0] [14] $15\mask[14:14] + assign $0\mask[63:0] [15] $16\mask[15:15] + assign $0\mask[63:0] [16] $17\mask[16:16] + assign $0\mask[63:0] [17] $18\mask[17:17] + assign $0\mask[63:0] [18] $19\mask[18:18] + assign $0\mask[63:0] [19] $20\mask[19:19] + assign $0\mask[63:0] [20] $21\mask[20:20] + assign $0\mask[63:0] [21] $22\mask[21:21] + assign $0\mask[63:0] [22] $23\mask[22:22] + assign $0\mask[63:0] [23] $24\mask[23:23] + assign $0\mask[63:0] [24] $25\mask[24:24] + assign $0\mask[63:0] [25] $26\mask[25:25] + assign $0\mask[63:0] [26] $27\mask[26:26] + assign $0\mask[63:0] [27] $28\mask[27:27] + assign $0\mask[63:0] [28] $29\mask[28:28] + assign $0\mask[63:0] [29] $30\mask[29:29] + assign $0\mask[63:0] [30] $31\mask[30:30] + assign $0\mask[63:0] [31] $32\mask[31:31] + assign $0\mask[63:0] [32] $33\mask[32:32] + assign $0\mask[63:0] [33] $34\mask[33:33] + assign $0\mask[63:0] [34] $35\mask[34:34] + assign $0\mask[63:0] [35] $36\mask[35:35] + assign $0\mask[63:0] [36] $37\mask[36:36] + assign $0\mask[63:0] [37] $38\mask[37:37] + assign $0\mask[63:0] [38] $39\mask[38:38] + assign $0\mask[63:0] [39] $40\mask[39:39] + assign $0\mask[63:0] [40] $41\mask[40:40] + assign $0\mask[63:0] [41] $42\mask[41:41] + assign $0\mask[63:0] [42] $43\mask[42:42] + assign $0\mask[63:0] [43] $44\mask[43:43] + assign $0\mask[63:0] [44] $45\mask[44:44] + assign $0\mask[63:0] [45] $46\mask[45:45] + assign $0\mask[63:0] [46] $47\mask[46:46] + assign $0\mask[63:0] [47] $48\mask[47:47] + assign $0\mask[63:0] [48] $49\mask[48:48] + assign $0\mask[63:0] [49] $50\mask[49:49] + assign $0\mask[63:0] [50] $51\mask[50:50] + assign $0\mask[63:0] [51] $52\mask[51:51] + assign $0\mask[63:0] [52] $53\mask[52:52] + assign $0\mask[63:0] [53] $54\mask[53:53] + assign $0\mask[63:0] [54] $55\mask[54:54] + assign $0\mask[63:0] [55] $56\mask[55:55] + assign $0\mask[63:0] [56] $57\mask[56:56] + assign $0\mask[63:0] [57] $58\mask[57:57] + assign $0\mask[63:0] [58] $59\mask[58:58] + assign $0\mask[63:0] [59] $60\mask[59:59] + assign $0\mask[63:0] [60] $61\mask[60:60] + assign $0\mask[63:0] [61] $62\mask[61:61] + assign $0\mask[63:0] [62] $63\mask[62:62] + assign $0\mask[63:0] [63] $64\mask[63:63] + attribute \src "libresoc.v:129011.5-129011.29" + switch \initial + attribute \src "libresoc.v:129011.9-129011.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\mask[0:0] 1'1 + case + assign $1\mask[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\mask[1:1] 1'1 + case + assign $2\mask[1:1] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$5 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\mask[2:2] 1'1 + case + assign $3\mask[2:2] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$7 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\mask[3:3] 1'1 + case + assign $4\mask[3:3] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$9 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\mask[4:4] 1'1 + case + assign $5\mask[4:4] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$11 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\mask[5:5] 1'1 + case + assign $6\mask[5:5] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$13 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\mask[6:6] 1'1 + case + assign $7\mask[6:6] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$15 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $8\mask[7:7] 1'1 + case + assign $8\mask[7:7] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$17 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $9\mask[8:8] 1'1 + case + assign $9\mask[8:8] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$19 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $10\mask[9:9] 1'1 + case + assign $10\mask[9:9] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$21 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $11\mask[10:10] 1'1 + case + assign $11\mask[10:10] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$23 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $12\mask[11:11] 1'1 + case + assign $12\mask[11:11] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$25 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $13\mask[12:12] 1'1 + case + assign $13\mask[12:12] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$27 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $14\mask[13:13] 1'1 + case + assign $14\mask[13:13] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$29 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $15\mask[14:14] 1'1 + case + assign $15\mask[14:14] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$31 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $16\mask[15:15] 1'1 + case + assign $16\mask[15:15] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$33 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $17\mask[16:16] 1'1 + case + assign $17\mask[16:16] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$35 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $18\mask[17:17] 1'1 + case + assign $18\mask[17:17] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$37 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $19\mask[18:18] 1'1 + case + assign $19\mask[18:18] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$39 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $20\mask[19:19] 1'1 + case + assign $20\mask[19:19] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$41 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $21\mask[20:20] 1'1 + case + assign $21\mask[20:20] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$43 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $22\mask[21:21] 1'1 + case + assign $22\mask[21:21] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$45 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $23\mask[22:22] 1'1 + case + assign $23\mask[22:22] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$47 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $24\mask[23:23] 1'1 + case + assign $24\mask[23:23] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$49 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $25\mask[24:24] 1'1 + case + assign $25\mask[24:24] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$51 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $26\mask[25:25] 1'1 + case + assign $26\mask[25:25] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$53 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $27\mask[26:26] 1'1 + case + assign $27\mask[26:26] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$55 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $28\mask[27:27] 1'1 + case + assign $28\mask[27:27] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$57 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $29\mask[28:28] 1'1 + case + assign $29\mask[28:28] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$59 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $30\mask[29:29] 1'1 + case + assign $30\mask[29:29] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$61 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $31\mask[30:30] 1'1 + case + assign $31\mask[30:30] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$63 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $32\mask[31:31] 1'1 + case + assign $32\mask[31:31] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$65 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $33\mask[32:32] 1'1 + case + assign $33\mask[32:32] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$67 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $34\mask[33:33] 1'1 + case + assign $34\mask[33:33] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$69 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $35\mask[34:34] 1'1 + case + assign $35\mask[34:34] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$71 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $36\mask[35:35] 1'1 + case + assign $36\mask[35:35] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$73 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $37\mask[36:36] 1'1 + case + assign $37\mask[36:36] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$75 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $38\mask[37:37] 1'1 + case + assign $38\mask[37:37] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$77 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $39\mask[38:38] 1'1 + case + assign $39\mask[38:38] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$79 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $40\mask[39:39] 1'1 + case + assign $40\mask[39:39] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$81 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $41\mask[40:40] 1'1 + case + assign $41\mask[40:40] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$83 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $42\mask[41:41] 1'1 + case + assign $42\mask[41:41] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$85 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $43\mask[42:42] 1'1 + case + assign $43\mask[42:42] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$87 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $44\mask[43:43] 1'1 + case + assign $44\mask[43:43] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$89 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $45\mask[44:44] 1'1 + case + assign $45\mask[44:44] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$91 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $46\mask[45:45] 1'1 + case + assign $46\mask[45:45] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$93 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $47\mask[46:46] 1'1 + case + assign $47\mask[46:46] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$95 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $48\mask[47:47] 1'1 + case + assign $48\mask[47:47] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$97 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $49\mask[48:48] 1'1 + case + assign $49\mask[48:48] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$99 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $50\mask[49:49] 1'1 + case + assign $50\mask[49:49] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$101 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $51\mask[50:50] 1'1 + case + assign $51\mask[50:50] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$103 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $52\mask[51:51] 1'1 + case + assign $52\mask[51:51] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$105 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $53\mask[52:52] 1'1 + case + assign $53\mask[52:52] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$107 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $54\mask[53:53] 1'1 + case + assign $54\mask[53:53] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$109 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $55\mask[54:54] 1'1 + case + assign $55\mask[54:54] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$111 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $56\mask[55:55] 1'1 + case + assign $56\mask[55:55] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$113 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $57\mask[56:56] 1'1 + case + assign $57\mask[56:56] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$115 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $58\mask[57:57] 1'1 + case + assign $58\mask[57:57] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$117 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $59\mask[58:58] 1'1 + case + assign $59\mask[58:58] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$119 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $60\mask[59:59] 1'1 + case + assign $60\mask[59:59] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$121 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $61\mask[60:60] 1'1 + case + assign $61\mask[60:60] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$123 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $62\mask[61:61] 1'1 + case + assign $62\mask[61:61] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$125 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $63\mask[62:62] 1'1 + case + assign $63\mask[62:62] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$127 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $64\mask[63:63] 1'1 + case + assign $64\mask[63:63] 1'0 + end + sync always + update \mask $0\mask[63:0] + end + connect \$9 $gt$libresoc.v:128946$5937_Y + connect \$99 $gt$libresoc.v:128947$5938_Y + connect \$101 $gt$libresoc.v:128948$5939_Y + connect \$103 $gt$libresoc.v:128949$5940_Y + connect \$105 $gt$libresoc.v:128950$5941_Y + connect \$107 $gt$libresoc.v:128951$5942_Y + connect \$109 $gt$libresoc.v:128952$5943_Y + connect \$111 $gt$libresoc.v:128953$5944_Y + connect \$113 $gt$libresoc.v:128954$5945_Y + connect \$115 $gt$libresoc.v:128955$5946_Y + connect \$117 $gt$libresoc.v:128956$5947_Y + connect \$11 $gt$libresoc.v:128957$5948_Y + connect \$119 $gt$libresoc.v:128958$5949_Y + connect \$121 $gt$libresoc.v:128959$5950_Y + connect \$123 $gt$libresoc.v:128960$5951_Y + connect \$125 $gt$libresoc.v:128961$5952_Y + connect \$127 $gt$libresoc.v:128962$5953_Y + connect \$13 $gt$libresoc.v:128963$5954_Y + connect \$15 $gt$libresoc.v:128964$5955_Y + connect \$17 $gt$libresoc.v:128965$5956_Y + connect \$1 $gt$libresoc.v:128966$5957_Y + connect \$19 $gt$libresoc.v:128967$5958_Y + connect \$21 $gt$libresoc.v:128968$5959_Y + connect \$23 $gt$libresoc.v:128969$5960_Y + connect \$25 $gt$libresoc.v:128970$5961_Y + connect \$27 $gt$libresoc.v:128971$5962_Y + connect \$29 $gt$libresoc.v:128972$5963_Y + connect \$31 $gt$libresoc.v:128973$5964_Y + connect \$33 $gt$libresoc.v:128974$5965_Y + connect \$35 $gt$libresoc.v:128975$5966_Y + connect \$37 $gt$libresoc.v:128976$5967_Y + connect \$3 $gt$libresoc.v:128977$5968_Y + connect \$39 $gt$libresoc.v:128978$5969_Y + connect \$41 $gt$libresoc.v:128979$5970_Y + connect \$43 $gt$libresoc.v:128980$5971_Y + connect \$45 $gt$libresoc.v:128981$5972_Y + connect \$47 $gt$libresoc.v:128982$5973_Y + connect \$49 $gt$libresoc.v:128983$5974_Y + connect \$51 $gt$libresoc.v:128984$5975_Y + connect \$53 $gt$libresoc.v:128985$5976_Y + connect \$55 $gt$libresoc.v:128986$5977_Y + connect \$57 $gt$libresoc.v:128987$5978_Y + connect \$5 $gt$libresoc.v:128988$5979_Y + connect \$59 $gt$libresoc.v:128989$5980_Y + connect \$61 $gt$libresoc.v:128990$5981_Y + connect \$63 $gt$libresoc.v:128991$5982_Y + connect \$65 $gt$libresoc.v:128992$5983_Y + connect \$67 $gt$libresoc.v:128993$5984_Y + connect \$69 $gt$libresoc.v:128994$5985_Y + connect \$71 $gt$libresoc.v:128995$5986_Y + connect \$73 $gt$libresoc.v:128996$5987_Y + connect \$75 $gt$libresoc.v:128997$5988_Y + connect \$77 $gt$libresoc.v:128998$5989_Y + connect \$7 $gt$libresoc.v:128999$5990_Y + connect \$79 $gt$libresoc.v:129000$5991_Y + connect \$81 $gt$libresoc.v:129001$5992_Y + connect \$83 $gt$libresoc.v:129002$5993_Y + connect \$85 $gt$libresoc.v:129003$5994_Y + connect \$87 $gt$libresoc.v:129004$5995_Y + connect \$89 $gt$libresoc.v:129005$5996_Y + connect \$91 $gt$libresoc.v:129006$5997_Y + connect \$93 $gt$libresoc.v:129007$5998_Y + connect \$95 $gt$libresoc.v:129008$5999_Y + connect \$97 $gt$libresoc.v:129009$6000_Y +end +attribute \src "libresoc.v:129402.1-129431.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.l0.pimem.lenexp" +attribute \generator "nMigen" +module \lenexp + attribute \src "libresoc.v:129426.17-129426.101" + wire width 64 $extend$libresoc.v:129426$6006_Y + attribute \src "libresoc.v:129426.17-129426.101" + wire width 64 $pos$libresoc.v:129426$6007_Y + attribute \src "libresoc.v:129423.17-129423.111" + wire width 20 $sshl$libresoc.v:129423$6003_Y + attribute \src "libresoc.v:129425.17-129425.113" + wire width 32 $sshl$libresoc.v:129425$6005_Y + attribute \src "libresoc.v:129424.17-129424.107" + wire width 21 $sub$libresoc.v:129424$6004_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150" + wire width 21 \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150" + wire width 20 \$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150" + wire width 21 \$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:151" + wire width 64 \$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:151" + wire width 32 \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:131" + wire width 4 input 1 \addr_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:148" + wire width 17 \binlen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:130" + wire width 4 input 4 \len_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:132" + wire width 64 output 2 \lexp_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:134" + wire width 176 output 3 \rexp_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:151" + cell $pos $extend$libresoc.v:129426$6006 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \Y_WIDTH 64 + connect \A \$7 + connect \Y $extend$libresoc.v:129426$6006_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:151" + cell $pos $pos$libresoc.v:129426$6007 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:129426$6006_Y + connect \Y $pos$libresoc.v:129426$6007_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150" + cell $sshl $sshl$libresoc.v:129423$6003 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 20 + connect \A 5'00001 + connect \B \len_i + connect \Y $sshl$libresoc.v:129423$6003_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:151" + cell $sshl $sshl$libresoc.v:129425$6005 + parameter \A_SIGNED 0 + parameter \A_WIDTH 17 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 32 + connect \A \binlen + connect \B \addr_i + connect \Y $sshl$libresoc.v:129425$6005_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150" + cell $sub $sub$libresoc.v:129424$6004 + parameter \A_SIGNED 0 + parameter \A_WIDTH 20 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 21 + connect \A \$2 + connect \B 1'1 + connect \Y $sub$libresoc.v:129424$6004_Y + end + connect \$2 $sshl$libresoc.v:129423$6003_Y + connect \$4 $sub$libresoc.v:129424$6004_Y + connect \$7 $sshl$libresoc.v:129425$6005_Y + connect \$6 $pos$libresoc.v:129426$6007_Y + connect \$1 \$4 + connect \rexp_o { \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21:20] \lexp_o [20] \lexp_o [20] \lexp_o [20] \lexp_o [20] \lexp_o [20] \lexp_o [20] \lexp_o [20:19] \lexp_o [19] \lexp_o [19] \lexp_o [19] \lexp_o [19] \lexp_o [19] \lexp_o [19] \lexp_o [19:18] \lexp_o [18] \lexp_o [18] \lexp_o [18] \lexp_o [18] \lexp_o [18] \lexp_o [18] \lexp_o [18:17] \lexp_o [17] \lexp_o [17] \lexp_o [17] \lexp_o [17] \lexp_o [17] \lexp_o [17] \lexp_o [17:16] \lexp_o [16] \lexp_o [16] \lexp_o [16] \lexp_o [16] \lexp_o [16] \lexp_o [16] \lexp_o [16:15] \lexp_o [15] \lexp_o [15] \lexp_o [15] \lexp_o [15] \lexp_o [15] \lexp_o [15] \lexp_o [15:14] \lexp_o [14] \lexp_o [14] \lexp_o [14] \lexp_o [14] \lexp_o [14] \lexp_o [14] \lexp_o [14:13] \lexp_o [13] \lexp_o [13] \lexp_o [13] \lexp_o [13] \lexp_o [13] \lexp_o [13] \lexp_o [13:12] \lexp_o [12] \lexp_o [12] \lexp_o [12] \lexp_o [12] \lexp_o [12] \lexp_o [12] \lexp_o [12:11] \lexp_o [11] \lexp_o [11] \lexp_o [11] \lexp_o [11] \lexp_o [11] \lexp_o [11] \lexp_o [11:10] \lexp_o [10] \lexp_o [10] \lexp_o [10] \lexp_o [10] \lexp_o [10] \lexp_o [10] \lexp_o [10:9] \lexp_o [9] \lexp_o [9] \lexp_o [9] \lexp_o [9] \lexp_o [9] \lexp_o [9] \lexp_o [9:8] \lexp_o [8] \lexp_o [8] \lexp_o [8] \lexp_o [8] \lexp_o [8] \lexp_o [8] \lexp_o [8:7] \lexp_o [7] \lexp_o [7] \lexp_o [7] \lexp_o [7] \lexp_o [7] \lexp_o [7] \lexp_o [7:6] \lexp_o [6] \lexp_o [6] \lexp_o [6] \lexp_o [6] \lexp_o [6] \lexp_o [6] \lexp_o [6:5] \lexp_o [5] \lexp_o [5] \lexp_o [5] \lexp_o [5] \lexp_o [5] \lexp_o [5] \lexp_o [5:4] \lexp_o [4] \lexp_o [4] \lexp_o [4] \lexp_o [4] \lexp_o [4] \lexp_o [4] \lexp_o [4:3] \lexp_o [3] \lexp_o [3] \lexp_o [3] \lexp_o [3] \lexp_o [3] \lexp_o [3] \lexp_o [3:2] \lexp_o [2] \lexp_o [2] \lexp_o [2] \lexp_o [2] \lexp_o [2] \lexp_o [2] \lexp_o [2:1] \lexp_o [1] \lexp_o [1] \lexp_o [1] \lexp_o [1] \lexp_o [1] \lexp_o [1] \lexp_o [1:0] \lexp_o [0] \lexp_o [0] \lexp_o [0] \lexp_o [0] \lexp_o [0] \lexp_o [0] \lexp_o [0] } + connect \lexp_o \$6 + connect \binlen \$4 [16:0] +end +attribute \src "libresoc.v:129435.1-129493.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.lod_l" +attribute \generator "nMigen" +module \lod_l + attribute \src "libresoc.v:129436.7-129436.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:129481.3-129489.6" + wire $0\q_int$next[0:0]$6018 + attribute \src "libresoc.v:129479.3-129480.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:129481.3-129489.6" + wire $1\q_int$next[0:0]$6019 + attribute \src "libresoc.v:129458.7-129458.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:129471.17-129471.96" + wire $and$libresoc.v:129471$6008_Y + attribute \src "libresoc.v:129476.17-129476.96" + wire $and$libresoc.v:129476$6013_Y + attribute \src "libresoc.v:129473.18-129473.93" + wire $not$libresoc.v:129473$6010_Y + attribute \src "libresoc.v:129475.17-129475.92" + wire $not$libresoc.v:129475$6012_Y + attribute \src "libresoc.v:129478.17-129478.92" + wire $not$libresoc.v:129478$6015_Y + attribute \src "libresoc.v:129472.18-129472.98" + wire $or$libresoc.v:129472$6009_Y + attribute \src "libresoc.v:129474.18-129474.99" + wire $or$libresoc.v:129474$6011_Y + attribute \src "libresoc.v:129477.17-129477.97" + wire $or$libresoc.v:129477$6014_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 1 \coresync_rst + attribute \src "libresoc.v:129436.7-129436.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire \q_lod + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_lod + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire output 4 \qn_lod + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_lod + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 2 \s_lod + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$libresoc.v:129471$6008 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:129471$6008_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:129476$6013 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:129476$6013_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:129473$6010 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_lod + connect \Y $not$libresoc.v:129473$6010_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:129475$6012 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_lod + connect \Y $not$libresoc.v:129475$6012_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:129478$6015 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_lod + connect \Y $not$libresoc.v:129478$6015_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:129472$6009 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_lod + connect \Y $or$libresoc.v:129472$6009_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:129474$6011 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_lod + connect \B \q_int + connect \Y $or$libresoc.v:129474$6011_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:129477$6014 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_lod + connect \Y $or$libresoc.v:129477$6014_Y + end + attribute \src "libresoc.v:129436.7-129436.20" + process $proc$libresoc.v:129436$6020 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:129458.7-129458.19" + process $proc$libresoc.v:129458$6021 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:129479.3-129480.27" + process $proc$libresoc.v:129479$6016 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:129481.3-129489.6" + process $proc$libresoc.v:129481$6017 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$6018 $1\q_int$next[0:0]$6019 + attribute \src "libresoc.v:129482.5-129482.29" + switch \initial + attribute \src "libresoc.v:129482.9-129482.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$6019 1'0 + case + assign $1\q_int$next[0:0]$6019 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$6018 + end + connect \$9 $and$libresoc.v:129471$6008_Y + connect \$11 $or$libresoc.v:129472$6009_Y + connect \$13 $not$libresoc.v:129473$6010_Y + connect \$15 $or$libresoc.v:129474$6011_Y + connect \$1 $not$libresoc.v:129475$6012_Y + connect \$3 $and$libresoc.v:129476$6013_Y + connect \$5 $or$libresoc.v:129477$6014_Y + connect \$7 $not$libresoc.v:129478$6015_Y + connect \qlq_lod \$15 + connect \qn_lod \$13 + connect \q_lod \$11 +end +attribute \src "libresoc.v:129497.1-130611.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.logical0" +attribute \generator "nMigen" +module \logical0 + attribute \src "libresoc.v:130236.3-130237.24" + wire $0\all_rd_dly[0:0] + attribute \src "libresoc.v:130234.3-130235.44" + wire $0\alu_done_dly[0:0] + attribute \src "libresoc.v:130541.3-130549.6" + wire $0\alu_l_r_alu$next[0:0]$6222 + attribute \src "libresoc.v:130158.3-130159.39" + wire $0\alu_l_r_alu[0:0] + attribute \src "libresoc.v:130419.3-130457.6" + wire width 4 $0\alu_logical0_logical_op__data_len$next[3:0]$6151 + attribute \src "libresoc.v:130208.3-130209.83" + wire width 4 $0\alu_logical0_logical_op__data_len[3:0] + attribute \src "libresoc.v:130419.3-130457.6" + wire width 12 $0\alu_logical0_logical_op__fn_unit$next[11:0]$6152 + attribute \src "libresoc.v:130178.3-130179.81" + wire width 12 $0\alu_logical0_logical_op__fn_unit[11:0] + attribute \src "libresoc.v:130419.3-130457.6" + wire width 64 $0\alu_logical0_logical_op__imm_data__data$next[63:0]$6153 + attribute \src "libresoc.v:130180.3-130181.95" + wire width 64 $0\alu_logical0_logical_op__imm_data__data[63:0] + attribute \src "libresoc.v:130419.3-130457.6" + wire $0\alu_logical0_logical_op__imm_data__ok$next[0:0]$6154 + attribute \src "libresoc.v:130182.3-130183.91" + wire $0\alu_logical0_logical_op__imm_data__ok[0:0] + attribute \src "libresoc.v:130419.3-130457.6" + wire width 2 $0\alu_logical0_logical_op__input_carry$next[1:0]$6155 + attribute \src "libresoc.v:130196.3-130197.89" + wire width 2 $0\alu_logical0_logical_op__input_carry[1:0] + attribute \src "libresoc.v:130419.3-130457.6" + wire width 32 $0\alu_logical0_logical_op__insn$next[31:0]$6156 + attribute \src "libresoc.v:130210.3-130211.75" + wire width 32 $0\alu_logical0_logical_op__insn[31:0] + attribute \src "libresoc.v:130419.3-130457.6" + wire width 7 $0\alu_logical0_logical_op__insn_type$next[6:0]$6157 + attribute \src "libresoc.v:130176.3-130177.85" + wire width 7 $0\alu_logical0_logical_op__insn_type[6:0] + attribute \src "libresoc.v:130419.3-130457.6" + wire $0\alu_logical0_logical_op__invert_in$next[0:0]$6158 + attribute \src "libresoc.v:130192.3-130193.85" + wire $0\alu_logical0_logical_op__invert_in[0:0] + attribute \src "libresoc.v:130419.3-130457.6" + wire $0\alu_logical0_logical_op__invert_out$next[0:0]$6159 + attribute \src "libresoc.v:130198.3-130199.87" + wire $0\alu_logical0_logical_op__invert_out[0:0] + attribute \src "libresoc.v:130419.3-130457.6" + wire $0\alu_logical0_logical_op__is_32bit$next[0:0]$6160 + attribute \src "libresoc.v:130204.3-130205.83" + wire $0\alu_logical0_logical_op__is_32bit[0:0] + attribute \src "libresoc.v:130419.3-130457.6" + wire $0\alu_logical0_logical_op__is_signed$next[0:0]$6161 + attribute \src "libresoc.v:130206.3-130207.85" + wire $0\alu_logical0_logical_op__is_signed[0:0] + attribute \src "libresoc.v:130419.3-130457.6" + wire $0\alu_logical0_logical_op__oe__oe$next[0:0]$6162 + attribute \src "libresoc.v:130188.3-130189.79" + wire $0\alu_logical0_logical_op__oe__oe[0:0] + attribute \src "libresoc.v:130419.3-130457.6" + wire $0\alu_logical0_logical_op__oe__ok$next[0:0]$6163 + attribute \src "libresoc.v:130190.3-130191.79" + wire $0\alu_logical0_logical_op__oe__ok[0:0] + attribute \src "libresoc.v:130419.3-130457.6" + wire $0\alu_logical0_logical_op__output_carry$next[0:0]$6164 + attribute \src "libresoc.v:130202.3-130203.91" + wire $0\alu_logical0_logical_op__output_carry[0:0] + attribute \src "libresoc.v:130419.3-130457.6" + wire $0\alu_logical0_logical_op__rc__ok$next[0:0]$6165 + attribute \src "libresoc.v:130186.3-130187.79" + wire $0\alu_logical0_logical_op__rc__ok[0:0] + attribute \src "libresoc.v:130419.3-130457.6" + wire $0\alu_logical0_logical_op__rc__rc$next[0:0]$6166 + attribute \src "libresoc.v:130184.3-130185.79" + wire $0\alu_logical0_logical_op__rc__rc[0:0] + attribute \src "libresoc.v:130419.3-130457.6" + wire $0\alu_logical0_logical_op__write_cr0$next[0:0]$6167 + attribute \src "libresoc.v:130200.3-130201.85" + wire $0\alu_logical0_logical_op__write_cr0[0:0] + attribute \src "libresoc.v:130419.3-130457.6" + wire $0\alu_logical0_logical_op__zero_a$next[0:0]$6168 + attribute \src "libresoc.v:130194.3-130195.79" + wire $0\alu_logical0_logical_op__zero_a[0:0] + attribute \src "libresoc.v:130532.3-130540.6" + wire $0\alui_l_r_alui$next[0:0]$6219 + attribute \src "libresoc.v:130160.3-130161.43" + wire $0\alui_l_r_alui[0:0] + attribute \src "libresoc.v:130458.3-130479.6" + wire width 64 $0\data_r0__o$next[63:0]$6194 + attribute \src "libresoc.v:130172.3-130173.37" + wire width 64 $0\data_r0__o[63:0] + attribute \src "libresoc.v:130458.3-130479.6" + wire $0\data_r0__o_ok$next[0:0]$6195 + attribute \src "libresoc.v:130174.3-130175.43" + wire $0\data_r0__o_ok[0:0] + attribute \src "libresoc.v:130480.3-130501.6" + wire width 4 $0\data_r1__cr_a$next[3:0]$6202 + attribute \src "libresoc.v:130168.3-130169.43" + wire width 4 $0\data_r1__cr_a[3:0] + attribute \src "libresoc.v:130480.3-130501.6" + wire $0\data_r1__cr_a_ok$next[0:0]$6203 + attribute \src "libresoc.v:130170.3-130171.49" + wire $0\data_r1__cr_a_ok[0:0] + attribute \src "libresoc.v:130550.3-130559.6" + wire width 64 $0\dest1_o[63:0] + attribute \src "libresoc.v:130560.3-130569.6" + wire width 4 $0\dest2_o[3:0] + attribute \src "libresoc.v:129498.7-129498.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:130374.3-130382.6" + wire $0\opc_l_r_opc$next[0:0]$6136 + attribute \src "libresoc.v:130220.3-130221.39" + wire $0\opc_l_r_opc[0:0] + attribute \src "libresoc.v:130365.3-130373.6" + wire $0\opc_l_s_opc$next[0:0]$6133 + attribute \src "libresoc.v:130222.3-130223.39" + wire $0\opc_l_s_opc[0:0] + attribute \src "libresoc.v:130570.3-130578.6" + wire width 2 $0\prev_wr_go$next[1:0]$6227 + attribute \src "libresoc.v:130232.3-130233.37" + wire width 2 $0\prev_wr_go[1:0] + attribute \src "libresoc.v:130319.3-130328.6" + wire $0\req_done[0:0] + attribute \src "libresoc.v:130410.3-130418.6" + wire width 2 $0\req_l_r_req$next[1:0]$6148 + attribute \src "libresoc.v:130212.3-130213.39" + wire width 2 $0\req_l_r_req[1:0] + attribute \src "libresoc.v:130401.3-130409.6" + wire width 2 $0\req_l_s_req$next[1:0]$6145 + attribute \src "libresoc.v:130214.3-130215.39" + wire width 2 $0\req_l_s_req[1:0] + attribute \src "libresoc.v:130338.3-130346.6" + wire $0\rok_l_r_rdok$next[0:0]$6124 + attribute \src "libresoc.v:130228.3-130229.41" + wire $0\rok_l_r_rdok[0:0] + attribute \src "libresoc.v:130329.3-130337.6" + wire $0\rok_l_s_rdok$next[0:0]$6121 + attribute \src "libresoc.v:130230.3-130231.41" + wire $0\rok_l_s_rdok[0:0] + attribute \src "libresoc.v:130356.3-130364.6" + wire $0\rst_l_r_rst$next[0:0]$6130 + attribute \src "libresoc.v:130224.3-130225.39" + wire $0\rst_l_r_rst[0:0] + attribute \src "libresoc.v:130347.3-130355.6" + wire $0\rst_l_s_rst$next[0:0]$6127 + attribute \src "libresoc.v:130226.3-130227.39" + wire $0\rst_l_s_rst[0:0] + attribute \src "libresoc.v:130392.3-130400.6" + wire width 3 $0\src_l_r_src$next[2:0]$6142 + attribute \src "libresoc.v:130216.3-130217.39" + wire width 3 $0\src_l_r_src[2:0] + attribute \src "libresoc.v:130383.3-130391.6" + wire width 3 $0\src_l_s_src$next[2:0]$6139 + attribute \src "libresoc.v:130218.3-130219.39" + wire width 3 $0\src_l_s_src[2:0] + attribute \src "libresoc.v:130502.3-130511.6" + wire width 64 $0\src_r0$next[63:0]$6210 + attribute \src "libresoc.v:130166.3-130167.29" + wire width 64 $0\src_r0[63:0] + attribute \src "libresoc.v:130512.3-130521.6" + wire width 64 $0\src_r1$next[63:0]$6213 + attribute \src "libresoc.v:130164.3-130165.29" + wire width 64 $0\src_r1[63:0] + attribute \src "libresoc.v:130522.3-130531.6" + wire $0\src_r2$next[0:0]$6216 + attribute \src "libresoc.v:130162.3-130163.29" + wire $0\src_r2[0:0] + attribute \src "libresoc.v:129616.7-129616.24" + wire $1\all_rd_dly[0:0] + attribute \src "libresoc.v:129626.7-129626.26" + wire $1\alu_done_dly[0:0] + attribute \src "libresoc.v:130541.3-130549.6" + wire $1\alu_l_r_alu$next[0:0]$6223 + attribute \src "libresoc.v:129634.7-129634.25" + wire $1\alu_l_r_alu[0:0] + attribute \src "libresoc.v:130419.3-130457.6" + wire width 4 $1\alu_logical0_logical_op__data_len$next[3:0]$6169 + attribute \src "libresoc.v:129642.13-129642.53" + wire width 4 $1\alu_logical0_logical_op__data_len[3:0] + attribute \src "libresoc.v:130419.3-130457.6" + wire width 12 $1\alu_logical0_logical_op__fn_unit$next[11:0]$6170 + attribute \src "libresoc.v:129659.14-129659.56" + wire width 12 $1\alu_logical0_logical_op__fn_unit[11:0] + attribute \src "libresoc.v:130419.3-130457.6" + wire width 64 $1\alu_logical0_logical_op__imm_data__data$next[63:0]$6171 + attribute \src "libresoc.v:129663.14-129663.76" + wire width 64 $1\alu_logical0_logical_op__imm_data__data[63:0] + attribute \src "libresoc.v:130419.3-130457.6" + wire $1\alu_logical0_logical_op__imm_data__ok$next[0:0]$6172 + attribute \src "libresoc.v:129667.7-129667.51" + wire $1\alu_logical0_logical_op__imm_data__ok[0:0] + attribute \src "libresoc.v:130419.3-130457.6" + wire width 2 $1\alu_logical0_logical_op__input_carry$next[1:0]$6173 + attribute \src "libresoc.v:129675.13-129675.56" + wire width 2 $1\alu_logical0_logical_op__input_carry[1:0] + attribute \src "libresoc.v:130419.3-130457.6" + wire width 32 $1\alu_logical0_logical_op__insn$next[31:0]$6174 + attribute \src "libresoc.v:129679.14-129679.51" + wire width 32 $1\alu_logical0_logical_op__insn[31:0] + attribute \src "libresoc.v:130419.3-130457.6" + wire width 7 $1\alu_logical0_logical_op__insn_type$next[6:0]$6175 + attribute \src "libresoc.v:129757.13-129757.55" + wire width 7 $1\alu_logical0_logical_op__insn_type[6:0] + attribute \src "libresoc.v:130419.3-130457.6" + wire $1\alu_logical0_logical_op__invert_in$next[0:0]$6176 + attribute \src "libresoc.v:129761.7-129761.48" + wire $1\alu_logical0_logical_op__invert_in[0:0] + attribute \src "libresoc.v:130419.3-130457.6" + wire $1\alu_logical0_logical_op__invert_out$next[0:0]$6177 + attribute \src "libresoc.v:129765.7-129765.49" + wire $1\alu_logical0_logical_op__invert_out[0:0] + attribute \src "libresoc.v:130419.3-130457.6" + wire $1\alu_logical0_logical_op__is_32bit$next[0:0]$6178 + attribute \src "libresoc.v:129769.7-129769.47" + wire $1\alu_logical0_logical_op__is_32bit[0:0] + attribute \src "libresoc.v:130419.3-130457.6" + wire $1\alu_logical0_logical_op__is_signed$next[0:0]$6179 + attribute \src "libresoc.v:129773.7-129773.48" + wire $1\alu_logical0_logical_op__is_signed[0:0] + attribute \src "libresoc.v:130419.3-130457.6" + wire $1\alu_logical0_logical_op__oe__oe$next[0:0]$6180 + attribute \src "libresoc.v:129777.7-129777.45" + wire $1\alu_logical0_logical_op__oe__oe[0:0] + attribute \src "libresoc.v:130419.3-130457.6" + wire $1\alu_logical0_logical_op__oe__ok$next[0:0]$6181 + attribute \src "libresoc.v:129781.7-129781.45" + wire $1\alu_logical0_logical_op__oe__ok[0:0] + attribute \src "libresoc.v:130419.3-130457.6" + wire $1\alu_logical0_logical_op__output_carry$next[0:0]$6182 + attribute \src "libresoc.v:129785.7-129785.51" + wire $1\alu_logical0_logical_op__output_carry[0:0] + attribute \src "libresoc.v:130419.3-130457.6" + wire $1\alu_logical0_logical_op__rc__ok$next[0:0]$6183 + attribute \src "libresoc.v:129789.7-129789.45" + wire $1\alu_logical0_logical_op__rc__ok[0:0] + attribute \src "libresoc.v:130419.3-130457.6" + wire $1\alu_logical0_logical_op__rc__rc$next[0:0]$6184 + attribute \src "libresoc.v:129793.7-129793.45" + wire $1\alu_logical0_logical_op__rc__rc[0:0] + attribute \src "libresoc.v:130419.3-130457.6" + wire $1\alu_logical0_logical_op__write_cr0$next[0:0]$6185 + attribute \src "libresoc.v:129797.7-129797.48" + wire $1\alu_logical0_logical_op__write_cr0[0:0] + attribute \src "libresoc.v:130419.3-130457.6" + wire $1\alu_logical0_logical_op__zero_a$next[0:0]$6186 + attribute \src "libresoc.v:129801.7-129801.45" + wire $1\alu_logical0_logical_op__zero_a[0:0] + attribute \src "libresoc.v:130532.3-130540.6" + wire $1\alui_l_r_alui$next[0:0]$6220 + attribute \src "libresoc.v:129827.7-129827.27" + wire $1\alui_l_r_alui[0:0] + attribute \src "libresoc.v:130458.3-130479.6" + wire width 64 $1\data_r0__o$next[63:0]$6196 + attribute \src "libresoc.v:129861.14-129861.47" + wire width 64 $1\data_r0__o[63:0] + attribute \src "libresoc.v:130458.3-130479.6" + wire $1\data_r0__o_ok$next[0:0]$6197 + attribute \src "libresoc.v:129865.7-129865.27" + wire $1\data_r0__o_ok[0:0] + attribute \src "libresoc.v:130480.3-130501.6" + wire width 4 $1\data_r1__cr_a$next[3:0]$6204 + attribute \src "libresoc.v:129869.13-129869.33" + wire width 4 $1\data_r1__cr_a[3:0] + attribute \src "libresoc.v:130480.3-130501.6" + wire $1\data_r1__cr_a_ok$next[0:0]$6205 + attribute \src "libresoc.v:129873.7-129873.30" + wire $1\data_r1__cr_a_ok[0:0] + attribute \src "libresoc.v:130550.3-130559.6" + wire width 64 $1\dest1_o[63:0] + attribute \src "libresoc.v:130560.3-130569.6" + wire width 4 $1\dest2_o[3:0] + attribute \src "libresoc.v:130374.3-130382.6" + wire $1\opc_l_r_opc$next[0:0]$6137 + attribute \src "libresoc.v:129887.7-129887.25" + wire $1\opc_l_r_opc[0:0] + attribute \src "libresoc.v:130365.3-130373.6" + wire $1\opc_l_s_opc$next[0:0]$6134 + attribute \src "libresoc.v:129891.7-129891.25" + wire $1\opc_l_s_opc[0:0] + attribute \src "libresoc.v:130570.3-130578.6" + wire width 2 $1\prev_wr_go$next[1:0]$6228 + attribute \src "libresoc.v:130022.13-130022.30" + wire width 2 $1\prev_wr_go[1:0] + attribute \src "libresoc.v:130319.3-130328.6" + wire $1\req_done[0:0] + attribute \src "libresoc.v:130410.3-130418.6" + wire width 2 $1\req_l_r_req$next[1:0]$6149 + attribute \src "libresoc.v:130030.13-130030.31" + wire width 2 $1\req_l_r_req[1:0] + attribute \src "libresoc.v:130401.3-130409.6" + wire width 2 $1\req_l_s_req$next[1:0]$6146 + attribute \src "libresoc.v:130034.13-130034.31" + wire width 2 $1\req_l_s_req[1:0] + attribute \src "libresoc.v:130338.3-130346.6" + wire $1\rok_l_r_rdok$next[0:0]$6125 + attribute \src "libresoc.v:130046.7-130046.26" + wire $1\rok_l_r_rdok[0:0] + attribute \src "libresoc.v:130329.3-130337.6" + wire $1\rok_l_s_rdok$next[0:0]$6122 + attribute \src "libresoc.v:130050.7-130050.26" + wire $1\rok_l_s_rdok[0:0] + attribute \src "libresoc.v:130356.3-130364.6" + wire $1\rst_l_r_rst$next[0:0]$6131 + attribute \src "libresoc.v:130054.7-130054.25" + wire $1\rst_l_r_rst[0:0] + attribute \src "libresoc.v:130347.3-130355.6" + wire $1\rst_l_s_rst$next[0:0]$6128 + attribute \src "libresoc.v:130058.7-130058.25" + wire $1\rst_l_s_rst[0:0] + attribute \src "libresoc.v:130392.3-130400.6" + wire width 3 $1\src_l_r_src$next[2:0]$6143 + attribute \src "libresoc.v:130072.13-130072.31" + wire width 3 $1\src_l_r_src[2:0] + attribute \src "libresoc.v:130383.3-130391.6" + wire width 3 $1\src_l_s_src$next[2:0]$6140 + attribute \src "libresoc.v:130076.13-130076.31" + wire width 3 $1\src_l_s_src[2:0] + attribute \src "libresoc.v:130502.3-130511.6" + wire width 64 $1\src_r0$next[63:0]$6211 + attribute \src "libresoc.v:130084.14-130084.43" + wire width 64 $1\src_r0[63:0] + attribute \src "libresoc.v:130512.3-130521.6" + wire width 64 $1\src_r1$next[63:0]$6214 + attribute \src "libresoc.v:130088.14-130088.43" + wire width 64 $1\src_r1[63:0] + attribute \src "libresoc.v:130522.3-130531.6" + wire $1\src_r2$next[0:0]$6217 + attribute \src "libresoc.v:130092.7-130092.20" + wire $1\src_r2[0:0] + attribute \src "libresoc.v:130419.3-130457.6" + wire width 64 $2\alu_logical0_logical_op__imm_data__data$next[63:0]$6187 + attribute \src "libresoc.v:130419.3-130457.6" + wire $2\alu_logical0_logical_op__imm_data__ok$next[0:0]$6188 + attribute \src "libresoc.v:130419.3-130457.6" + wire $2\alu_logical0_logical_op__oe__oe$next[0:0]$6189 + attribute \src "libresoc.v:130419.3-130457.6" + wire $2\alu_logical0_logical_op__oe__ok$next[0:0]$6190 + attribute \src "libresoc.v:130419.3-130457.6" + wire $2\alu_logical0_logical_op__rc__ok$next[0:0]$6191 + attribute \src "libresoc.v:130419.3-130457.6" + wire $2\alu_logical0_logical_op__rc__rc$next[0:0]$6192 + attribute \src "libresoc.v:130458.3-130479.6" + wire width 64 $2\data_r0__o$next[63:0]$6198 + attribute \src "libresoc.v:130458.3-130479.6" + wire $2\data_r0__o_ok$next[0:0]$6199 + attribute \src "libresoc.v:130480.3-130501.6" + wire width 4 $2\data_r1__cr_a$next[3:0]$6206 + attribute \src "libresoc.v:130480.3-130501.6" + wire $2\data_r1__cr_a_ok$next[0:0]$6207 + attribute \src "libresoc.v:130458.3-130479.6" + wire $3\data_r0__o_ok$next[0:0]$6200 + attribute \src "libresoc.v:130480.3-130501.6" + wire $3\data_r1__cr_a_ok$next[0:0]$6208 + attribute \src "libresoc.v:130101.17-130101.109" + wire $and$libresoc.v:130101$6022_Y + attribute \src "libresoc.v:130102.18-130102.130" + wire width 3 $and$libresoc.v:130102$6023_Y + attribute \src "libresoc.v:130104.19-130104.114" + wire width 3 $and$libresoc.v:130104$6025_Y + attribute \src "libresoc.v:130105.19-130105.125" + wire $and$libresoc.v:130105$6026_Y + attribute \src "libresoc.v:130106.19-130106.125" + wire $and$libresoc.v:130106$6027_Y + attribute \src "libresoc.v:130107.19-130107.133" + wire width 2 $and$libresoc.v:130107$6028_Y + attribute \src "libresoc.v:130108.19-130108.121" + wire width 2 $and$libresoc.v:130108$6029_Y + attribute \src "libresoc.v:130109.19-130109.127" + wire $and$libresoc.v:130109$6030_Y + attribute \src "libresoc.v:130110.19-130110.127" + wire $and$libresoc.v:130110$6031_Y + attribute \src "libresoc.v:130112.18-130112.98" + wire $and$libresoc.v:130112$6033_Y + attribute \src "libresoc.v:130114.18-130114.100" + wire $and$libresoc.v:130114$6035_Y + attribute \src "libresoc.v:130115.17-130115.123" + wire $and$libresoc.v:130115$6036_Y + attribute \src "libresoc.v:130116.18-130116.138" + wire width 2 $and$libresoc.v:130116$6037_Y + attribute \src "libresoc.v:130118.18-130118.119" + wire width 2 $and$libresoc.v:130118$6039_Y + attribute \src "libresoc.v:130121.18-130121.116" + wire $and$libresoc.v:130121$6042_Y + attribute \src "libresoc.v:130126.18-130126.113" + wire $and$libresoc.v:130126$6047_Y + attribute \src "libresoc.v:130127.18-130127.125" + wire width 2 $and$libresoc.v:130127$6048_Y + attribute \src "libresoc.v:130129.18-130129.112" + wire $and$libresoc.v:130129$6050_Y + attribute \src "libresoc.v:130132.18-130132.130" + wire $and$libresoc.v:130132$6053_Y + attribute \src "libresoc.v:130133.18-130133.130" + wire $and$libresoc.v:130133$6054_Y + attribute \src "libresoc.v:130134.18-130134.117" + wire $and$libresoc.v:130134$6055_Y + attribute \src "libresoc.v:130139.18-130139.134" + wire $and$libresoc.v:130139$6060_Y + attribute \src "libresoc.v:130140.18-130140.124" + wire width 2 $and$libresoc.v:130140$6061_Y + attribute \src "libresoc.v:130143.18-130143.116" + wire $and$libresoc.v:130143$6064_Y + attribute \src "libresoc.v:130144.18-130144.119" + wire $and$libresoc.v:130144$6065_Y + attribute \src "libresoc.v:130153.18-130153.138" + wire $and$libresoc.v:130153$6074_Y + attribute \src "libresoc.v:130154.18-130154.136" + wire $and$libresoc.v:130154$6075_Y + attribute \src "libresoc.v:130155.18-130155.149" + wire width 3 $and$libresoc.v:130155$6076_Y + attribute \src "libresoc.v:130128.18-130128.113" + wire $eq$libresoc.v:130128$6049_Y + attribute \src "libresoc.v:130130.18-130130.119" + wire $eq$libresoc.v:130130$6051_Y + attribute \src "libresoc.v:130103.19-130103.115" + wire width 3 $not$libresoc.v:130103$6024_Y + attribute \src "libresoc.v:130111.18-130111.97" + wire $not$libresoc.v:130111$6032_Y + attribute \src "libresoc.v:130113.18-130113.99" + wire $not$libresoc.v:130113$6034_Y + attribute \src "libresoc.v:130117.18-130117.113" + wire width 2 $not$libresoc.v:130117$6038_Y + attribute \src "libresoc.v:130120.18-130120.106" + wire $not$libresoc.v:130120$6041_Y + attribute \src "libresoc.v:130125.18-130125.124" + wire $not$libresoc.v:130125$6046_Y + attribute \src "libresoc.v:130131.17-130131.113" + wire width 3 $not$libresoc.v:130131$6052_Y + attribute \src "libresoc.v:130156.18-130156.133" + wire $not$libresoc.v:130156$6077_Y + attribute \src "libresoc.v:130157.18-130157.139" + wire $not$libresoc.v:130157$6078_Y + attribute \src "libresoc.v:130124.18-130124.112" + wire $or$libresoc.v:130124$6045_Y + attribute \src "libresoc.v:130135.18-130135.122" + wire $or$libresoc.v:130135$6056_Y + attribute \src "libresoc.v:130136.18-130136.124" + wire $or$libresoc.v:130136$6057_Y + attribute \src "libresoc.v:130137.18-130137.142" + wire width 2 $or$libresoc.v:130137$6058_Y + attribute \src "libresoc.v:130138.18-130138.155" + wire width 3 $or$libresoc.v:130138$6059_Y + attribute \src "libresoc.v:130141.18-130141.120" + wire width 2 $or$libresoc.v:130141$6062_Y + attribute \src "libresoc.v:130142.17-130142.117" + wire width 3 $or$libresoc.v:130142$6063_Y + attribute \src "libresoc.v:130148.17-130148.104" + wire $reduce_and$libresoc.v:130148$6069_Y + attribute \src "libresoc.v:130119.18-130119.106" + wire $reduce_or$libresoc.v:130119$6040_Y + attribute \src "libresoc.v:130122.18-130122.113" + wire $reduce_or$libresoc.v:130122$6043_Y + attribute \src "libresoc.v:130123.18-130123.112" + wire $reduce_or$libresoc.v:130123$6044_Y + attribute \src "libresoc.v:130145.18-130145.162" + wire $ternary$libresoc.v:130145$6066_Y + attribute \src "libresoc.v:130146.18-130146.163" + wire width 64 $ternary$libresoc.v:130146$6067_Y + attribute \src "libresoc.v:130147.18-130147.168" + wire $ternary$libresoc.v:130147$6068_Y + attribute \src "libresoc.v:130149.18-130149.188" + wire width 64 $ternary$libresoc.v:130149$6070_Y + attribute \src "libresoc.v:130150.18-130150.115" + wire width 64 $ternary$libresoc.v:130150$6071_Y + attribute \src "libresoc.v:130151.18-130151.125" + wire width 64 $ternary$libresoc.v:130151$6072_Y + attribute \src "libresoc.v:130152.18-130152.118" + wire $ternary$libresoc.v:130152$6073_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + wire width 3 \$101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + wire width 3 \$103 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + wire \$105 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + wire \$107 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" + wire width 2 \$109 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" + wire width 2 \$111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + wire \$113 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + wire \$115 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire \$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" + wire width 2 \$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + wire \$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + wire \$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + wire width 2 \$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + wire width 2 \$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + wire \$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + wire \$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + wire \$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + wire \$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + wire \$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + wire width 3 \$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + wire width 2 \$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + wire \$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + wire \$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + wire \$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + wire \$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + wire \$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + wire \$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" + wire \$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" + wire \$57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" + wire width 2 \$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + wire width 3 \$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" + wire width 3 \$61 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" + wire \$63 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" + wire width 2 \$65 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" + wire width 2 \$67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + wire \$69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + wire \$71 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" + wire \$73 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" + wire width 64 \$75 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" + wire \$78 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" + wire width 64 \$81 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 64 \$83 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 64 \$85 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire \$87 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" + wire \$89 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" + wire \$91 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + wire width 3 \$93 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" + wire \$95 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" + wire \$97 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + wire width 3 \$99 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:187" + wire \all_rd + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire \all_rd_dly + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire \all_rd_dly$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:192" + wire \all_rd_pulse + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + wire \all_rd_rise + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:196" + wire \alu_done + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire \alu_done_dly + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire \alu_done_dly$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + wire \alu_done_rise + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire \alu_l_q_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \alu_l_r_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \alu_l_r_alu$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \alu_l_s_alu + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \alu_logical0_cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \alu_logical0_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \alu_logical0_logical_op__data_len$next + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \alu_logical0_logical_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \alu_logical0_logical_op__fn_unit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \alu_logical0_logical_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \alu_logical0_logical_op__imm_data__data$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_logical0_logical_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_logical0_logical_op__imm_data__ok$next + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \alu_logical0_logical_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \alu_logical0_logical_op__input_carry$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \alu_logical0_logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \alu_logical0_logical_op__insn$next + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \alu_logical0_logical_op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \alu_logical0_logical_op__insn_type$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_logical0_logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_logical0_logical_op__invert_in$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_logical0_logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_logical0_logical_op__invert_out$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_logical0_logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_logical0_logical_op__is_32bit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_logical0_logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_logical0_logical_op__is_signed$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_logical0_logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_logical0_logical_op__oe__oe$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_logical0_logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_logical0_logical_op__oe__ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_logical0_logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_logical0_logical_op__output_carry$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_logical0_logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_logical0_logical_op__rc__ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_logical0_logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_logical0_logical_op__rc__rc$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_logical0_logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_logical0_logical_op__write_cr0$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_logical0_logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_logical0_logical_op__zero_a$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire \alu_logical0_n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire \alu_logical0_n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \alu_logical0_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire \alu_logical0_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire \alu_logical0_p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \alu_logical0_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \alu_logical0_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \alu_logical0_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:197" + wire \alu_pulse + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198" + wire width 2 \alu_pulsem + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire \alui_l_q_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \alui_l_r_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \alui_l_r_alui$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \alui_l_s_alui + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 34 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 33 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 31 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" + wire output 20 \cu_busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:108" + wire \cu_done_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:104" + wire \cu_go_die_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" + wire input 19 \cu_issue_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 input 23 \cu_rd__go_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 output 22 \cu_rd__rel_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" + wire width 3 input 21 \cu_rdmaskn_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:102" + wire \cu_shadown_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 2 input 29 \cu_wr__go_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 2 output 28 \cu_wr__rel_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:97" + wire width 2 \cu_wrmask_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 64 \data_r0__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 64 \data_r0__o$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r0__o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r0__o_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 4 \data_r1__cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 4 \data_r1__cr_a$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r1__cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r1__cr_a_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 30 \dest1_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 4 output 32 \dest2_o + attribute \src "libresoc.v:129498.7-129498.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 27 \o_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire \opc_l_q_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \opc_l_r_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \opc_l_r_opc$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \opc_l_s_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \opc_l_s_opc$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 17 \oper_i_alu_logical0__data_len + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 2 \oper_i_alu_logical0__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 3 \oper_i_alu_logical0__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 4 \oper_i_alu_logical0__imm_data__ok + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 11 \oper_i_alu_logical0__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 18 \oper_i_alu_logical0__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \oper_i_alu_logical0__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \oper_i_alu_logical0__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \oper_i_alu_logical0__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 15 \oper_i_alu_logical0__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 16 \oper_i_alu_logical0__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 7 \oper_i_alu_logical0__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \oper_i_alu_logical0__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \oper_i_alu_logical0__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 6 \oper_i_alu_logical0__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 5 \oper_i_alu_logical0__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \oper_i_alu_logical0__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \oper_i_alu_logical0__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" + wire width 2 \prev_wr_go + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" + wire width 2 \prev_wr_go$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212" + wire \req_done + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 2 \req_l_q_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 2 \req_l_r_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 2 \req_l_r_req$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 2 \req_l_s_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 2 \req_l_s_req$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226" + wire \reset + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:229" + wire width 3 \reset_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:228" + wire width 2 \reset_w + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire \rok_l_q_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \rok_l_r_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \rok_l_r_rdok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \rok_l_s_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \rok_l_s_rdok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \rst_l_r_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \rst_l_r_rst$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \rst_l_s_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \rst_l_s_rst$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227" + wire \rst_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 24 \src1_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 25 \src2_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire input 26 \src3_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 3 \src_l_q_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 3 \src_l_r_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 3 \src_l_r_src$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 3 \src_l_s_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 3 \src_l_s_src$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:166" + wire width 64 \src_or_imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:166" + wire width 64 \src_or_imm$80 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 64 \src_r0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 64 \src_r0$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 64 \src_r1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 64 \src_r1$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire \src_r2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire \src_r2$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:167" + wire \src_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:167" + wire \src_sel$77 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" + wire \wr_any + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $and $and$libresoc.v:130101$6022 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$1 + connect \B \$3 + connect \Y $and$libresoc.v:130101$6022_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + cell $and $and$libresoc.v:130102$6023 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \$93 + connect \B { 1'1 \$97 \$95 } + connect \Y $and$libresoc.v:130102$6023_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + cell $and $and$libresoc.v:130104$6025 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \$99 + connect \B \$101 + connect \Y $and$libresoc.v:130104$6025_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + cell $and $and$libresoc.v:130105$6026 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_busy_o + connect \B \cu_shadown_i + connect \Y $and$libresoc.v:130105$6026_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + cell $and $and$libresoc.v:130106$6027 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_busy_o + connect \B \cu_shadown_i + connect \Y $and$libresoc.v:130106$6027_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" + cell $and $and$libresoc.v:130107$6028 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \req_l_q_req + connect \B { \$105 \$107 } + connect \Y $and$libresoc.v:130107$6028_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" + cell $and $and$libresoc.v:130108$6029 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \$109 + connect \B \cu_wrmask_o + connect \Y $and$libresoc.v:130108$6029_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + cell $and $and$libresoc.v:130109$6030 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_wr__go_i [0] + connect \B \cu_busy_o + connect \Y $and$libresoc.v:130109$6030_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + cell $and $and$libresoc.v:130110$6031 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_wr__go_i [1] + connect \B \cu_busy_o + connect \Y $and$libresoc.v:130110$6031_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $and$libresoc.v:130112$6033 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \all_rd + connect \B \$11 + connect \Y $and$libresoc.v:130112$6033_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $and$libresoc.v:130114$6035 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_done + connect \B \$15 + connect \Y $and$libresoc.v:130114$6035_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" + cell $and $and$libresoc.v:130115$6036 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_busy_o + connect \B \rok_l_q_rdok + connect \Y $and$libresoc.v:130115$6036_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" + cell $and $and$libresoc.v:130116$6037 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \cu_wr__go_i + connect \B { \cu_busy_o \cu_busy_o } + connect \Y $and$libresoc.v:130116$6037_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $and $and$libresoc.v:130118$6039 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \cu_wr__rel_o + connect \B \$23 + connect \Y $and$libresoc.v:130118$6039_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $and $and$libresoc.v:130121$6042 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_busy_o + connect \B \$21 + connect \Y $and$libresoc.v:130121$6042_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + cell $and $and$libresoc.v:130126$6047 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_any + connect \B \$37 + connect \Y $and$libresoc.v:130126$6047_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + cell $and $and$libresoc.v:130127$6048 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \req_l_q_req + connect \B \cu_wrmask_o + connect \Y $and$libresoc.v:130127$6048_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + cell $and $and$libresoc.v:130129$6050 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$39 + connect \B \$43 + connect \Y $and$libresoc.v:130129$6050_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + cell $and $and$libresoc.v:130132$6053 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$47 + connect \B \alu_logical0_n_ready_i + connect \Y $and$libresoc.v:130132$6053_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + cell $and $and$libresoc.v:130133$6054 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$49 + connect \B \alu_logical0_n_valid_o + connect \Y $and$libresoc.v:130133$6054_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + cell $and $and$libresoc.v:130134$6055 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$51 + connect \B \cu_busy_o + connect \Y $and$libresoc.v:130134$6055_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" + cell $and $and$libresoc.v:130139$6060 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_logical0_n_valid_o + connect \B \cu_busy_o + connect \Y $and$libresoc.v:130139$6060_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" + cell $and $and$libresoc.v:130140$6061 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \alu_pulsem + connect \B \cu_wrmask_o + connect \Y $and$libresoc.v:130140$6061_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + cell $and $and$libresoc.v:130143$6064 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \o_ok + connect \B \cu_busy_o + connect \Y $and$libresoc.v:130143$6064_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + cell $and $and$libresoc.v:130144$6065 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cr_a_ok + connect \B \cu_busy_o + connect \Y $and$libresoc.v:130144$6065_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" + cell $and $and$libresoc.v:130153$6074 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_logical0_p_ready_o + connect \B \alui_l_q_alui + connect \Y $and$libresoc.v:130153$6074_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" + cell $and $and$libresoc.v:130154$6075 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_logical0_n_valid_o + connect \B \alu_l_q_alu + connect \Y $and$libresoc.v:130154$6075_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + cell $and $and$libresoc.v:130155$6076 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \src_l_q_src + connect \B { \cu_busy_o \cu_busy_o \cu_busy_o } + connect \Y $and$libresoc.v:130155$6076_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + cell $eq $eq$libresoc.v:130128$6049 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$41 + connect \B 1'0 + connect \Y $eq$libresoc.v:130128$6049_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + cell $eq $eq$libresoc.v:130130$6051 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_wrmask_o + connect \B 1'0 + connect \Y $eq$libresoc.v:130130$6051_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + cell $not $not$libresoc.v:130103$6024 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \cu_rdmaskn_i + connect \Y $not$libresoc.v:130103$6024_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $not$libresoc.v:130111$6032 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \all_rd_dly + connect \Y $not$libresoc.v:130111$6032_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $not$libresoc.v:130113$6034 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_done_dly + connect \Y $not$libresoc.v:130113$6034_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $not $not$libresoc.v:130117$6038 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \cu_wrmask_o + connect \Y $not$libresoc.v:130117$6038_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $not $not$libresoc.v:130120$6041 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$22 + connect \Y $not$libresoc.v:130120$6041_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + cell $not $not$libresoc.v:130125$6046 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_logical0_n_ready_i + connect \Y $not$libresoc.v:130125$6046_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $not $not$libresoc.v:130131$6052 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \cu_rd__rel_o + connect \Y $not$libresoc.v:130131$6052_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" + cell $not $not$libresoc.v:130156$6077 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_logical0_logical_op__zero_a + connect \Y $not$libresoc.v:130156$6077_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" + cell $not $not$libresoc.v:130157$6078 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_logical0_logical_op__imm_data__ok + connect \Y $not$libresoc.v:130157$6078_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $or $or$libresoc.v:130124$6045 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$31 + connect \B \$33 + connect \Y $or$libresoc.v:130124$6045_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" + cell $or $or$libresoc.v:130135$6056 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \req_done + connect \B \cu_go_die_i + connect \Y $or$libresoc.v:130135$6056_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" + cell $or $or$libresoc.v:130136$6057 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_issue_i + connect \B \cu_go_die_i + connect \Y $or$libresoc.v:130136$6057_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" + cell $or $or$libresoc.v:130137$6058 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \cu_wr__go_i + connect \B { \cu_go_die_i \cu_go_die_i } + connect \Y $or$libresoc.v:130137$6058_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" + cell $or $or$libresoc.v:130138$6059 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \cu_rd__go_i + connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } + connect \Y $or$libresoc.v:130138$6059_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" + cell $or $or$libresoc.v:130141$6062 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \reset_w + connect \B \prev_wr_go + connect \Y $or$libresoc.v:130141$6062_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $or $or$libresoc.v:130142$6063 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \$4 + connect \B \cu_rd__go_i + connect \Y $or$libresoc.v:130142$6063_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $reduce_and $reduce_and$libresoc.v:130148$6069 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \$6 + connect \Y $reduce_and$libresoc.v:130148$6069_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $reduce_or $reduce_or$libresoc.v:130119$6040 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \$25 + connect \Y $reduce_or$libresoc.v:130119$6040_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $reduce_or $reduce_or$libresoc.v:130122$6043 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \cu_wr__go_i + connect \Y $reduce_or$libresoc.v:130122$6043_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $reduce_or $reduce_or$libresoc.v:130123$6044 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \prev_wr_go + connect \Y $reduce_or$libresoc.v:130123$6044_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" + cell $mux $ternary$libresoc.v:130145$6066 + parameter \WIDTH 1 + connect \A \src_l_q_src [0] + connect \B \opc_l_q_opc + connect \S \alu_logical0_logical_op__zero_a + connect \Y $ternary$libresoc.v:130145$6066_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" + cell $mux $ternary$libresoc.v:130146$6067 + parameter \WIDTH 64 + connect \A \src1_i + connect \B 64'0000000000000000000000000000000000000000000000000000000000000000 + connect \S \alu_logical0_logical_op__zero_a + connect \Y $ternary$libresoc.v:130146$6067_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" + cell $mux $ternary$libresoc.v:130147$6068 + parameter \WIDTH 1 + connect \A \src_l_q_src [1] + connect \B \opc_l_q_opc + connect \S \alu_logical0_logical_op__imm_data__ok + connect \Y $ternary$libresoc.v:130147$6068_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" + cell $mux $ternary$libresoc.v:130149$6070 + parameter \WIDTH 64 + connect \A \src2_i + connect \B \alu_logical0_logical_op__imm_data__data + connect \S \alu_logical0_logical_op__imm_data__ok + connect \Y $ternary$libresoc.v:130149$6070_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $ternary$libresoc.v:130150$6071 + parameter \WIDTH 64 + connect \A \src_r0 + connect \B \src_or_imm + connect \S \src_sel + connect \Y $ternary$libresoc.v:130150$6071_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $ternary$libresoc.v:130151$6072 + parameter \WIDTH 64 + connect \A \src_r1 + connect \B \src_or_imm$80 + connect \S \src_sel$77 + connect \Y $ternary$libresoc.v:130151$6072_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $ternary$libresoc.v:130152$6073 + parameter \WIDTH 1 + connect \A \src_r2 + connect \B \src3_i + connect \S \src_l_q_src [2] + connect \Y $ternary$libresoc.v:130152$6073_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:130238.14-130244.4" + cell \alu_l$58 \alu_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_alu \alu_l_q_alu + connect \r_alu \alu_l_r_alu + connect \s_alu \alu_l_s_alu + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:130245.16-130277.4" + cell \alu_logical0 \alu_logical0 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cr_a \alu_logical0_cr_a + connect \cr_a_ok \cr_a_ok + connect \logical_op__data_len \alu_logical0_logical_op__data_len + connect \logical_op__fn_unit \alu_logical0_logical_op__fn_unit + connect \logical_op__imm_data__data \alu_logical0_logical_op__imm_data__data + connect \logical_op__imm_data__ok \alu_logical0_logical_op__imm_data__ok + connect \logical_op__input_carry \alu_logical0_logical_op__input_carry + connect \logical_op__insn \alu_logical0_logical_op__insn + connect \logical_op__insn_type \alu_logical0_logical_op__insn_type + connect \logical_op__invert_in \alu_logical0_logical_op__invert_in + connect \logical_op__invert_out \alu_logical0_logical_op__invert_out + connect \logical_op__is_32bit \alu_logical0_logical_op__is_32bit + connect \logical_op__is_signed \alu_logical0_logical_op__is_signed + connect \logical_op__oe__oe \alu_logical0_logical_op__oe__oe + connect \logical_op__oe__ok \alu_logical0_logical_op__oe__ok + connect \logical_op__output_carry \alu_logical0_logical_op__output_carry + connect \logical_op__rc__ok \alu_logical0_logical_op__rc__ok + connect \logical_op__rc__rc \alu_logical0_logical_op__rc__rc + connect \logical_op__write_cr0 \alu_logical0_logical_op__write_cr0 + connect \logical_op__zero_a \alu_logical0_logical_op__zero_a + connect \n_ready_i \alu_logical0_n_ready_i + connect \n_valid_o \alu_logical0_n_valid_o + connect \o \alu_logical0_o + connect \o_ok \o_ok + connect \p_ready_o \alu_logical0_p_ready_o + connect \p_valid_i \alu_logical0_p_valid_i + connect \ra \alu_logical0_ra + connect \rb \alu_logical0_rb + connect \xer_so \alu_logical0_xer_so + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:130278.15-130284.4" + cell \alui_l$57 \alui_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_alui \alui_l_q_alui + connect \r_alui \alui_l_r_alui + connect \s_alui \alui_l_s_alui + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:130285.14-130291.4" + cell \opc_l$53 \opc_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_opc \opc_l_q_opc + connect \r_opc \opc_l_r_opc + connect \s_opc \opc_l_s_opc + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:130292.14-130298.4" + cell \req_l$54 \req_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_req \req_l_q_req + connect \r_req \req_l_r_req + connect \s_req \req_l_s_req + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:130299.14-130305.4" + cell \rok_l$56 \rok_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_rdok \rok_l_q_rdok + connect \r_rdok \rok_l_r_rdok + connect \s_rdok \rok_l_s_rdok + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:130306.14-130311.4" + cell \rst_l$55 \rst_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \r_rst \rst_l_r_rst + connect \s_rst \rst_l_s_rst + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:130312.14-130318.4" + cell \src_l$52 \src_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_src \src_l_q_src + connect \r_src \src_l_r_src + connect \s_src \src_l_s_src + end + attribute \src "libresoc.v:129498.7-129498.20" + process $proc$libresoc.v:129498$6229 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:129616.7-129616.24" + process $proc$libresoc.v:129616$6230 + assign { } { } + assign $1\all_rd_dly[0:0] 1'0 + sync always + sync init + update \all_rd_dly $1\all_rd_dly[0:0] + end + attribute \src "libresoc.v:129626.7-129626.26" + process $proc$libresoc.v:129626$6231 + assign { } { } + assign $1\alu_done_dly[0:0] 1'0 + sync always + sync init + update \alu_done_dly $1\alu_done_dly[0:0] + end + attribute \src "libresoc.v:129634.7-129634.25" + process $proc$libresoc.v:129634$6232 + assign { } { } + assign $1\alu_l_r_alu[0:0] 1'1 + sync always + sync init + update \alu_l_r_alu $1\alu_l_r_alu[0:0] + end + attribute \src "libresoc.v:129642.13-129642.53" + process $proc$libresoc.v:129642$6233 + assign { } { } + assign $1\alu_logical0_logical_op__data_len[3:0] 4'0000 + sync always + sync init + update \alu_logical0_logical_op__data_len $1\alu_logical0_logical_op__data_len[3:0] + end + attribute \src "libresoc.v:129659.14-129659.56" + process $proc$libresoc.v:129659$6234 + assign { } { } + assign $1\alu_logical0_logical_op__fn_unit[11:0] 12'000000000000 + sync always + sync init + update \alu_logical0_logical_op__fn_unit $1\alu_logical0_logical_op__fn_unit[11:0] + end + attribute \src "libresoc.v:129663.14-129663.76" + process $proc$libresoc.v:129663$6235 + assign { } { } + assign $1\alu_logical0_logical_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \alu_logical0_logical_op__imm_data__data $1\alu_logical0_logical_op__imm_data__data[63:0] + end + attribute \src "libresoc.v:129667.7-129667.51" + process $proc$libresoc.v:129667$6236 + assign { } { } + assign $1\alu_logical0_logical_op__imm_data__ok[0:0] 1'0 + sync always + sync init + update \alu_logical0_logical_op__imm_data__ok $1\alu_logical0_logical_op__imm_data__ok[0:0] + end + attribute \src "libresoc.v:129675.13-129675.56" + process $proc$libresoc.v:129675$6237 + assign { } { } + assign $1\alu_logical0_logical_op__input_carry[1:0] 2'00 + sync always + sync init + update \alu_logical0_logical_op__input_carry $1\alu_logical0_logical_op__input_carry[1:0] + end + attribute \src "libresoc.v:129679.14-129679.51" + process $proc$libresoc.v:129679$6238 + assign { } { } + assign $1\alu_logical0_logical_op__insn[31:0] 0 + sync always + sync init + update \alu_logical0_logical_op__insn $1\alu_logical0_logical_op__insn[31:0] + end + attribute \src "libresoc.v:129757.13-129757.55" + process $proc$libresoc.v:129757$6239 + assign { } { } + assign $1\alu_logical0_logical_op__insn_type[6:0] 7'0000000 + sync always + sync init + update \alu_logical0_logical_op__insn_type $1\alu_logical0_logical_op__insn_type[6:0] + end + attribute \src "libresoc.v:129761.7-129761.48" + process $proc$libresoc.v:129761$6240 + assign { } { } + assign $1\alu_logical0_logical_op__invert_in[0:0] 1'0 + sync always + sync init + update \alu_logical0_logical_op__invert_in $1\alu_logical0_logical_op__invert_in[0:0] + end + attribute \src "libresoc.v:129765.7-129765.49" + process $proc$libresoc.v:129765$6241 + assign { } { } + assign $1\alu_logical0_logical_op__invert_out[0:0] 1'0 + sync always + sync init + update \alu_logical0_logical_op__invert_out $1\alu_logical0_logical_op__invert_out[0:0] + end + attribute \src "libresoc.v:129769.7-129769.47" + process $proc$libresoc.v:129769$6242 + assign { } { } + assign $1\alu_logical0_logical_op__is_32bit[0:0] 1'0 + sync always + sync init + update \alu_logical0_logical_op__is_32bit $1\alu_logical0_logical_op__is_32bit[0:0] + end + attribute \src "libresoc.v:129773.7-129773.48" + process $proc$libresoc.v:129773$6243 + assign { } { } + assign $1\alu_logical0_logical_op__is_signed[0:0] 1'0 + sync always + sync init + update \alu_logical0_logical_op__is_signed $1\alu_logical0_logical_op__is_signed[0:0] + end + attribute \src "libresoc.v:129777.7-129777.45" + process $proc$libresoc.v:129777$6244 + assign { } { } + assign $1\alu_logical0_logical_op__oe__oe[0:0] 1'0 + sync always + sync init + update \alu_logical0_logical_op__oe__oe $1\alu_logical0_logical_op__oe__oe[0:0] + end + attribute \src "libresoc.v:129781.7-129781.45" + process $proc$libresoc.v:129781$6245 + assign { } { } + assign $1\alu_logical0_logical_op__oe__ok[0:0] 1'0 + sync always + sync init + update \alu_logical0_logical_op__oe__ok $1\alu_logical0_logical_op__oe__ok[0:0] + end + attribute \src "libresoc.v:129785.7-129785.51" + process $proc$libresoc.v:129785$6246 + assign { } { } + assign $1\alu_logical0_logical_op__output_carry[0:0] 1'0 + sync always + sync init + update \alu_logical0_logical_op__output_carry $1\alu_logical0_logical_op__output_carry[0:0] + end + attribute \src "libresoc.v:129789.7-129789.45" + process $proc$libresoc.v:129789$6247 + assign { } { } + assign $1\alu_logical0_logical_op__rc__ok[0:0] 1'0 + sync always + sync init + update \alu_logical0_logical_op__rc__ok $1\alu_logical0_logical_op__rc__ok[0:0] + end + attribute \src "libresoc.v:129793.7-129793.45" + process $proc$libresoc.v:129793$6248 + assign { } { } + assign $1\alu_logical0_logical_op__rc__rc[0:0] 1'0 + sync always + sync init + update \alu_logical0_logical_op__rc__rc $1\alu_logical0_logical_op__rc__rc[0:0] + end + attribute \src "libresoc.v:129797.7-129797.48" + process $proc$libresoc.v:129797$6249 + assign { } { } + assign $1\alu_logical0_logical_op__write_cr0[0:0] 1'0 + sync always + sync init + update \alu_logical0_logical_op__write_cr0 $1\alu_logical0_logical_op__write_cr0[0:0] + end + attribute \src "libresoc.v:129801.7-129801.45" + process $proc$libresoc.v:129801$6250 + assign { } { } + assign $1\alu_logical0_logical_op__zero_a[0:0] 1'0 + sync always + sync init + update \alu_logical0_logical_op__zero_a $1\alu_logical0_logical_op__zero_a[0:0] + end + attribute \src "libresoc.v:129827.7-129827.27" + process $proc$libresoc.v:129827$6251 + assign { } { } + assign $1\alui_l_r_alui[0:0] 1'1 + sync always + sync init + update \alui_l_r_alui $1\alui_l_r_alui[0:0] + end + attribute \src "libresoc.v:129861.14-129861.47" + process $proc$libresoc.v:129861$6252 + assign { } { } + assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \data_r0__o $1\data_r0__o[63:0] + end + attribute \src "libresoc.v:129865.7-129865.27" + process $proc$libresoc.v:129865$6253 + assign { } { } + assign $1\data_r0__o_ok[0:0] 1'0 + sync always + sync init + update \data_r0__o_ok $1\data_r0__o_ok[0:0] + end + attribute \src "libresoc.v:129869.13-129869.33" + process $proc$libresoc.v:129869$6254 + assign { } { } + assign $1\data_r1__cr_a[3:0] 4'0000 + sync always + sync init + update \data_r1__cr_a $1\data_r1__cr_a[3:0] + end + attribute \src "libresoc.v:129873.7-129873.30" + process $proc$libresoc.v:129873$6255 + assign { } { } + assign $1\data_r1__cr_a_ok[0:0] 1'0 + sync always + sync init + update \data_r1__cr_a_ok $1\data_r1__cr_a_ok[0:0] + end + attribute \src "libresoc.v:129887.7-129887.25" + process $proc$libresoc.v:129887$6256 + assign { } { } + assign $1\opc_l_r_opc[0:0] 1'1 + sync always + sync init + update \opc_l_r_opc $1\opc_l_r_opc[0:0] + end + attribute \src "libresoc.v:129891.7-129891.25" + process $proc$libresoc.v:129891$6257 + assign { } { } + assign $1\opc_l_s_opc[0:0] 1'0 + sync always + sync init + update \opc_l_s_opc $1\opc_l_s_opc[0:0] + end + attribute \src "libresoc.v:130022.13-130022.30" + process $proc$libresoc.v:130022$6258 + assign { } { } + assign $1\prev_wr_go[1:0] 2'00 + sync always + sync init + update \prev_wr_go $1\prev_wr_go[1:0] + end + attribute \src "libresoc.v:130030.13-130030.31" + process $proc$libresoc.v:130030$6259 + assign { } { } + assign $1\req_l_r_req[1:0] 2'11 + sync always + sync init + update \req_l_r_req $1\req_l_r_req[1:0] + end + attribute \src "libresoc.v:130034.13-130034.31" + process $proc$libresoc.v:130034$6260 + assign { } { } + assign $1\req_l_s_req[1:0] 2'00 + sync always + sync init + update \req_l_s_req $1\req_l_s_req[1:0] + end + attribute \src "libresoc.v:130046.7-130046.26" + process $proc$libresoc.v:130046$6261 + assign { } { } + assign $1\rok_l_r_rdok[0:0] 1'1 + sync always + sync init + update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] + end + attribute \src "libresoc.v:130050.7-130050.26" + process $proc$libresoc.v:130050$6262 + assign { } { } + assign $1\rok_l_s_rdok[0:0] 1'0 + sync always + sync init + update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] + end + attribute \src "libresoc.v:130054.7-130054.25" + process $proc$libresoc.v:130054$6263 + assign { } { } + assign $1\rst_l_r_rst[0:0] 1'1 + sync always + sync init + update \rst_l_r_rst $1\rst_l_r_rst[0:0] + end + attribute \src "libresoc.v:130058.7-130058.25" + process $proc$libresoc.v:130058$6264 + assign { } { } + assign $1\rst_l_s_rst[0:0] 1'0 + sync always + sync init + update \rst_l_s_rst $1\rst_l_s_rst[0:0] + end + attribute \src "libresoc.v:130072.13-130072.31" + process $proc$libresoc.v:130072$6265 + assign { } { } + assign $1\src_l_r_src[2:0] 3'111 + sync always + sync init + update \src_l_r_src $1\src_l_r_src[2:0] + end + attribute \src "libresoc.v:130076.13-130076.31" + process $proc$libresoc.v:130076$6266 + assign { } { } + assign $1\src_l_s_src[2:0] 3'000 + sync always + sync init + update \src_l_s_src $1\src_l_s_src[2:0] + end + attribute \src "libresoc.v:130084.14-130084.43" + process $proc$libresoc.v:130084$6267 + assign { } { } + assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \src_r0 $1\src_r0[63:0] + end + attribute \src "libresoc.v:130088.14-130088.43" + process $proc$libresoc.v:130088$6268 + assign { } { } + assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \src_r1 $1\src_r1[63:0] + end + attribute \src "libresoc.v:130092.7-130092.20" + process $proc$libresoc.v:130092$6269 + assign { } { } + assign $1\src_r2[0:0] 1'0 + sync always + sync init + update \src_r2 $1\src_r2[0:0] + end + attribute \src "libresoc.v:130158.3-130159.39" + process $proc$libresoc.v:130158$6079 + assign { } { } + assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next + sync posedge \coresync_clk + update \alu_l_r_alu $0\alu_l_r_alu[0:0] + end + attribute \src "libresoc.v:130160.3-130161.43" + process $proc$libresoc.v:130160$6080 + assign { } { } + assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next + sync posedge \coresync_clk + update \alui_l_r_alui $0\alui_l_r_alui[0:0] + end + attribute \src "libresoc.v:130162.3-130163.29" + process $proc$libresoc.v:130162$6081 + assign { } { } + assign $0\src_r2[0:0] \src_r2$next + sync posedge \coresync_clk + update \src_r2 $0\src_r2[0:0] + end + attribute \src "libresoc.v:130164.3-130165.29" + process $proc$libresoc.v:130164$6082 + assign { } { } + assign $0\src_r1[63:0] \src_r1$next + sync posedge \coresync_clk + update \src_r1 $0\src_r1[63:0] + end + attribute \src "libresoc.v:130166.3-130167.29" + process $proc$libresoc.v:130166$6083 + assign { } { } + assign $0\src_r0[63:0] \src_r0$next + sync posedge \coresync_clk + update \src_r0 $0\src_r0[63:0] + end + attribute \src "libresoc.v:130168.3-130169.43" + process $proc$libresoc.v:130168$6084 + assign { } { } + assign $0\data_r1__cr_a[3:0] \data_r1__cr_a$next + sync posedge \coresync_clk + update \data_r1__cr_a $0\data_r1__cr_a[3:0] + end + attribute \src "libresoc.v:130170.3-130171.49" + process $proc$libresoc.v:130170$6085 + assign { } { } + assign $0\data_r1__cr_a_ok[0:0] \data_r1__cr_a_ok$next + sync posedge \coresync_clk + update \data_r1__cr_a_ok $0\data_r1__cr_a_ok[0:0] + end + attribute \src "libresoc.v:130172.3-130173.37" + process $proc$libresoc.v:130172$6086 + assign { } { } + assign $0\data_r0__o[63:0] \data_r0__o$next + sync posedge \coresync_clk + update \data_r0__o $0\data_r0__o[63:0] + end + attribute \src "libresoc.v:130174.3-130175.43" + process $proc$libresoc.v:130174$6087 + assign { } { } + assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next + sync posedge \coresync_clk + update \data_r0__o_ok $0\data_r0__o_ok[0:0] + end + attribute \src "libresoc.v:130176.3-130177.85" + process $proc$libresoc.v:130176$6088 + assign { } { } + assign $0\alu_logical0_logical_op__insn_type[6:0] \alu_logical0_logical_op__insn_type$next + sync posedge \coresync_clk + update \alu_logical0_logical_op__insn_type $0\alu_logical0_logical_op__insn_type[6:0] + end + attribute \src "libresoc.v:130178.3-130179.81" + process $proc$libresoc.v:130178$6089 + assign { } { } + assign $0\alu_logical0_logical_op__fn_unit[11:0] \alu_logical0_logical_op__fn_unit$next + sync posedge \coresync_clk + update \alu_logical0_logical_op__fn_unit $0\alu_logical0_logical_op__fn_unit[11:0] + end + attribute \src "libresoc.v:130180.3-130181.95" + process $proc$libresoc.v:130180$6090 + assign { } { } + assign $0\alu_logical0_logical_op__imm_data__data[63:0] \alu_logical0_logical_op__imm_data__data$next + sync posedge \coresync_clk + update \alu_logical0_logical_op__imm_data__data $0\alu_logical0_logical_op__imm_data__data[63:0] + end + attribute \src "libresoc.v:130182.3-130183.91" + process $proc$libresoc.v:130182$6091 + assign { } { } + assign $0\alu_logical0_logical_op__imm_data__ok[0:0] \alu_logical0_logical_op__imm_data__ok$next + sync posedge \coresync_clk + update \alu_logical0_logical_op__imm_data__ok $0\alu_logical0_logical_op__imm_data__ok[0:0] + end + attribute \src "libresoc.v:130184.3-130185.79" + process $proc$libresoc.v:130184$6092 + assign { } { } + assign $0\alu_logical0_logical_op__rc__rc[0:0] \alu_logical0_logical_op__rc__rc$next + sync posedge \coresync_clk + update \alu_logical0_logical_op__rc__rc $0\alu_logical0_logical_op__rc__rc[0:0] + end + attribute \src "libresoc.v:130186.3-130187.79" + process $proc$libresoc.v:130186$6093 + assign { } { } + assign $0\alu_logical0_logical_op__rc__ok[0:0] \alu_logical0_logical_op__rc__ok$next + sync posedge \coresync_clk + update \alu_logical0_logical_op__rc__ok $0\alu_logical0_logical_op__rc__ok[0:0] + end + attribute \src "libresoc.v:130188.3-130189.79" + process $proc$libresoc.v:130188$6094 + assign { } { } + assign $0\alu_logical0_logical_op__oe__oe[0:0] \alu_logical0_logical_op__oe__oe$next + sync posedge \coresync_clk + update \alu_logical0_logical_op__oe__oe $0\alu_logical0_logical_op__oe__oe[0:0] + end + attribute \src "libresoc.v:130190.3-130191.79" + process $proc$libresoc.v:130190$6095 + assign { } { } + assign $0\alu_logical0_logical_op__oe__ok[0:0] \alu_logical0_logical_op__oe__ok$next + sync posedge \coresync_clk + update \alu_logical0_logical_op__oe__ok $0\alu_logical0_logical_op__oe__ok[0:0] + end + attribute \src "libresoc.v:130192.3-130193.85" + process $proc$libresoc.v:130192$6096 + assign { } { } + assign $0\alu_logical0_logical_op__invert_in[0:0] \alu_logical0_logical_op__invert_in$next + sync posedge \coresync_clk + update \alu_logical0_logical_op__invert_in $0\alu_logical0_logical_op__invert_in[0:0] + end + attribute \src "libresoc.v:130194.3-130195.79" + process $proc$libresoc.v:130194$6097 + assign { } { } + assign $0\alu_logical0_logical_op__zero_a[0:0] \alu_logical0_logical_op__zero_a$next + sync posedge \coresync_clk + update \alu_logical0_logical_op__zero_a $0\alu_logical0_logical_op__zero_a[0:0] + end + attribute \src "libresoc.v:130196.3-130197.89" + process $proc$libresoc.v:130196$6098 + assign { } { } + assign $0\alu_logical0_logical_op__input_carry[1:0] \alu_logical0_logical_op__input_carry$next + sync posedge \coresync_clk + update \alu_logical0_logical_op__input_carry $0\alu_logical0_logical_op__input_carry[1:0] + end + attribute \src "libresoc.v:130198.3-130199.87" + process $proc$libresoc.v:130198$6099 + assign { } { } + assign $0\alu_logical0_logical_op__invert_out[0:0] \alu_logical0_logical_op__invert_out$next + sync posedge \coresync_clk + update \alu_logical0_logical_op__invert_out $0\alu_logical0_logical_op__invert_out[0:0] + end + attribute \src "libresoc.v:130200.3-130201.85" + process $proc$libresoc.v:130200$6100 + assign { } { } + assign $0\alu_logical0_logical_op__write_cr0[0:0] \alu_logical0_logical_op__write_cr0$next + sync posedge \coresync_clk + update \alu_logical0_logical_op__write_cr0 $0\alu_logical0_logical_op__write_cr0[0:0] + end + attribute \src "libresoc.v:130202.3-130203.91" + process $proc$libresoc.v:130202$6101 + assign { } { } + assign $0\alu_logical0_logical_op__output_carry[0:0] \alu_logical0_logical_op__output_carry$next + sync posedge \coresync_clk + update \alu_logical0_logical_op__output_carry $0\alu_logical0_logical_op__output_carry[0:0] + end + attribute \src "libresoc.v:130204.3-130205.83" + process $proc$libresoc.v:130204$6102 + assign { } { } + assign $0\alu_logical0_logical_op__is_32bit[0:0] \alu_logical0_logical_op__is_32bit$next + sync posedge \coresync_clk + update \alu_logical0_logical_op__is_32bit $0\alu_logical0_logical_op__is_32bit[0:0] + end + attribute \src "libresoc.v:130206.3-130207.85" + process $proc$libresoc.v:130206$6103 + assign { } { } + assign $0\alu_logical0_logical_op__is_signed[0:0] \alu_logical0_logical_op__is_signed$next + sync posedge \coresync_clk + update \alu_logical0_logical_op__is_signed $0\alu_logical0_logical_op__is_signed[0:0] + end + attribute \src "libresoc.v:130208.3-130209.83" + process $proc$libresoc.v:130208$6104 + assign { } { } + assign $0\alu_logical0_logical_op__data_len[3:0] \alu_logical0_logical_op__data_len$next + sync posedge \coresync_clk + update \alu_logical0_logical_op__data_len $0\alu_logical0_logical_op__data_len[3:0] + end + attribute \src "libresoc.v:130210.3-130211.75" + process $proc$libresoc.v:130210$6105 + assign { } { } + assign $0\alu_logical0_logical_op__insn[31:0] \alu_logical0_logical_op__insn$next + sync posedge \coresync_clk + update \alu_logical0_logical_op__insn $0\alu_logical0_logical_op__insn[31:0] + end + attribute \src "libresoc.v:130212.3-130213.39" + process $proc$libresoc.v:130212$6106 + assign { } { } + assign $0\req_l_r_req[1:0] \req_l_r_req$next + sync posedge \coresync_clk + update \req_l_r_req $0\req_l_r_req[1:0] + end + attribute \src "libresoc.v:130214.3-130215.39" + process $proc$libresoc.v:130214$6107 + assign { } { } + assign $0\req_l_s_req[1:0] \req_l_s_req$next + sync posedge \coresync_clk + update \req_l_s_req $0\req_l_s_req[1:0] + end + attribute \src "libresoc.v:130216.3-130217.39" + process $proc$libresoc.v:130216$6108 + assign { } { } + assign $0\src_l_r_src[2:0] \src_l_r_src$next + sync posedge \coresync_clk + update \src_l_r_src $0\src_l_r_src[2:0] + end + attribute \src "libresoc.v:130218.3-130219.39" + process $proc$libresoc.v:130218$6109 + assign { } { } + assign $0\src_l_s_src[2:0] \src_l_s_src$next + sync posedge \coresync_clk + update \src_l_s_src $0\src_l_s_src[2:0] + end + attribute \src "libresoc.v:130220.3-130221.39" + process $proc$libresoc.v:130220$6110 + assign { } { } + assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next + sync posedge \coresync_clk + update \opc_l_r_opc $0\opc_l_r_opc[0:0] + end + attribute \src "libresoc.v:130222.3-130223.39" + process $proc$libresoc.v:130222$6111 + assign { } { } + assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next + sync posedge \coresync_clk + update \opc_l_s_opc $0\opc_l_s_opc[0:0] + end + attribute \src "libresoc.v:130224.3-130225.39" + process $proc$libresoc.v:130224$6112 + assign { } { } + assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next + sync posedge \coresync_clk + update \rst_l_r_rst $0\rst_l_r_rst[0:0] + end + attribute \src "libresoc.v:130226.3-130227.39" + process $proc$libresoc.v:130226$6113 + assign { } { } + assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next + sync posedge \coresync_clk + update \rst_l_s_rst $0\rst_l_s_rst[0:0] + end + attribute \src "libresoc.v:130228.3-130229.41" + process $proc$libresoc.v:130228$6114 + assign { } { } + assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next + sync posedge \coresync_clk + update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] + end + attribute \src "libresoc.v:130230.3-130231.41" + process $proc$libresoc.v:130230$6115 + assign { } { } + assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next + sync posedge \coresync_clk + update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] + end + attribute \src "libresoc.v:130232.3-130233.37" + process $proc$libresoc.v:130232$6116 + assign { } { } + assign $0\prev_wr_go[1:0] \prev_wr_go$next + sync posedge \coresync_clk + update \prev_wr_go $0\prev_wr_go[1:0] + end + attribute \src "libresoc.v:130234.3-130235.44" + process $proc$libresoc.v:130234$6117 + assign { } { } + assign $0\alu_done_dly[0:0] \alu_logical0_n_valid_o + sync posedge \coresync_clk + update \alu_done_dly $0\alu_done_dly[0:0] + end + attribute \src "libresoc.v:130236.3-130237.24" + process $proc$libresoc.v:130236$6118 + assign { } { } + assign $0\all_rd_dly[0:0] \$9 + sync posedge \coresync_clk + update \all_rd_dly $0\all_rd_dly[0:0] + end + attribute \src "libresoc.v:130319.3-130328.6" + process $proc$libresoc.v:130319$6119 + assign { } { } + assign { } { } + assign $0\req_done[0:0] $1\req_done[0:0] + attribute \src "libresoc.v:130320.5-130320.29" + switch \initial + attribute \src "libresoc.v:130320.9-130320.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + switch \$53 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\req_done[0:0] 1'1 + case + assign $1\req_done[0:0] \$45 + end + sync always + update \req_done $0\req_done[0:0] + end + attribute \src "libresoc.v:130329.3-130337.6" + process $proc$libresoc.v:130329$6120 + assign { } { } + assign { } { } + assign $0\rok_l_s_rdok$next[0:0]$6121 $1\rok_l_s_rdok$next[0:0]$6122 + attribute \src "libresoc.v:130330.5-130330.29" + switch \initial + attribute \src "libresoc.v:130330.9-130330.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rok_l_s_rdok$next[0:0]$6122 1'0 + case + assign $1\rok_l_s_rdok$next[0:0]$6122 \cu_issue_i + end + sync always + update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$6121 + end + attribute \src "libresoc.v:130338.3-130346.6" + process $proc$libresoc.v:130338$6123 + assign { } { } + assign { } { } + assign $0\rok_l_r_rdok$next[0:0]$6124 $1\rok_l_r_rdok$next[0:0]$6125 + attribute \src "libresoc.v:130339.5-130339.29" + switch \initial + attribute \src "libresoc.v:130339.9-130339.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rok_l_r_rdok$next[0:0]$6125 1'1 + case + assign $1\rok_l_r_rdok$next[0:0]$6125 \$63 + end + sync always + update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$6124 + end + attribute \src "libresoc.v:130347.3-130355.6" + process $proc$libresoc.v:130347$6126 + assign { } { } + assign { } { } + assign $0\rst_l_s_rst$next[0:0]$6127 $1\rst_l_s_rst$next[0:0]$6128 + attribute \src "libresoc.v:130348.5-130348.29" + switch \initial + attribute \src "libresoc.v:130348.9-130348.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rst_l_s_rst$next[0:0]$6128 1'0 + case + assign $1\rst_l_s_rst$next[0:0]$6128 \all_rd + end + sync always + update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$6127 + end + attribute \src "libresoc.v:130356.3-130364.6" + process $proc$libresoc.v:130356$6129 + assign { } { } + assign { } { } + assign $0\rst_l_r_rst$next[0:0]$6130 $1\rst_l_r_rst$next[0:0]$6131 + attribute \src "libresoc.v:130357.5-130357.29" + switch \initial + attribute \src "libresoc.v:130357.9-130357.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rst_l_r_rst$next[0:0]$6131 1'1 + case + assign $1\rst_l_r_rst$next[0:0]$6131 \rst_r + end + sync always + update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$6130 + end + attribute \src "libresoc.v:130365.3-130373.6" + process $proc$libresoc.v:130365$6132 + assign { } { } + assign { } { } + assign $0\opc_l_s_opc$next[0:0]$6133 $1\opc_l_s_opc$next[0:0]$6134 + attribute \src "libresoc.v:130366.5-130366.29" + switch \initial + attribute \src "libresoc.v:130366.9-130366.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\opc_l_s_opc$next[0:0]$6134 1'0 + case + assign $1\opc_l_s_opc$next[0:0]$6134 \cu_issue_i + end + sync always + update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$6133 + end + attribute \src "libresoc.v:130374.3-130382.6" + process $proc$libresoc.v:130374$6135 + assign { } { } + assign { } { } + assign $0\opc_l_r_opc$next[0:0]$6136 $1\opc_l_r_opc$next[0:0]$6137 + attribute \src "libresoc.v:130375.5-130375.29" + switch \initial + attribute \src "libresoc.v:130375.9-130375.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\opc_l_r_opc$next[0:0]$6137 1'1 + case + assign $1\opc_l_r_opc$next[0:0]$6137 \req_done + end + sync always + update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$6136 + end + attribute \src "libresoc.v:130383.3-130391.6" + process $proc$libresoc.v:130383$6138 + assign { } { } + assign { } { } + assign $0\src_l_s_src$next[2:0]$6139 $1\src_l_s_src$next[2:0]$6140 + attribute \src "libresoc.v:130384.5-130384.29" + switch \initial + attribute \src "libresoc.v:130384.9-130384.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_l_s_src$next[2:0]$6140 3'000 + case + assign $1\src_l_s_src$next[2:0]$6140 { \cu_issue_i \cu_issue_i \cu_issue_i } + end + sync always + update \src_l_s_src$next $0\src_l_s_src$next[2:0]$6139 + end + attribute \src "libresoc.v:130392.3-130400.6" + process $proc$libresoc.v:130392$6141 + assign { } { } + assign { } { } + assign $0\src_l_r_src$next[2:0]$6142 $1\src_l_r_src$next[2:0]$6143 + attribute \src "libresoc.v:130393.5-130393.29" + switch \initial + attribute \src "libresoc.v:130393.9-130393.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_l_r_src$next[2:0]$6143 3'111 + case + assign $1\src_l_r_src$next[2:0]$6143 \reset_r + end + sync always + update \src_l_r_src$next $0\src_l_r_src$next[2:0]$6142 + end + attribute \src "libresoc.v:130401.3-130409.6" + process $proc$libresoc.v:130401$6144 + assign { } { } + assign { } { } + assign $0\req_l_s_req$next[1:0]$6145 $1\req_l_s_req$next[1:0]$6146 + attribute \src "libresoc.v:130402.5-130402.29" + switch \initial + attribute \src "libresoc.v:130402.9-130402.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\req_l_s_req$next[1:0]$6146 2'00 + case + assign $1\req_l_s_req$next[1:0]$6146 \$65 + end + sync always + update \req_l_s_req$next $0\req_l_s_req$next[1:0]$6145 + end + attribute \src "libresoc.v:130410.3-130418.6" + process $proc$libresoc.v:130410$6147 + assign { } { } + assign { } { } + assign $0\req_l_r_req$next[1:0]$6148 $1\req_l_r_req$next[1:0]$6149 + attribute \src "libresoc.v:130411.5-130411.29" + switch \initial + attribute \src "libresoc.v:130411.9-130411.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\req_l_r_req$next[1:0]$6149 2'11 + case + assign $1\req_l_r_req$next[1:0]$6149 \$67 + end + sync always + update \req_l_r_req$next $0\req_l_r_req$next[1:0]$6148 + end + attribute \src "libresoc.v:130419.3-130457.6" + process $proc$libresoc.v:130419$6150 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\alu_logical0_logical_op__data_len$next[3:0]$6151 $1\alu_logical0_logical_op__data_len$next[3:0]$6169 + assign $0\alu_logical0_logical_op__fn_unit$next[11:0]$6152 $1\alu_logical0_logical_op__fn_unit$next[11:0]$6170 + assign { } { } + assign { } { } + assign $0\alu_logical0_logical_op__input_carry$next[1:0]$6155 $1\alu_logical0_logical_op__input_carry$next[1:0]$6173 + assign $0\alu_logical0_logical_op__insn$next[31:0]$6156 $1\alu_logical0_logical_op__insn$next[31:0]$6174 + assign $0\alu_logical0_logical_op__insn_type$next[6:0]$6157 $1\alu_logical0_logical_op__insn_type$next[6:0]$6175 + assign $0\alu_logical0_logical_op__invert_in$next[0:0]$6158 $1\alu_logical0_logical_op__invert_in$next[0:0]$6176 + assign $0\alu_logical0_logical_op__invert_out$next[0:0]$6159 $1\alu_logical0_logical_op__invert_out$next[0:0]$6177 + assign $0\alu_logical0_logical_op__is_32bit$next[0:0]$6160 $1\alu_logical0_logical_op__is_32bit$next[0:0]$6178 + assign $0\alu_logical0_logical_op__is_signed$next[0:0]$6161 $1\alu_logical0_logical_op__is_signed$next[0:0]$6179 + assign { } { } + assign { } { } + assign $0\alu_logical0_logical_op__output_carry$next[0:0]$6164 $1\alu_logical0_logical_op__output_carry$next[0:0]$6182 + assign { } { } + assign { } { } + assign $0\alu_logical0_logical_op__write_cr0$next[0:0]$6167 $1\alu_logical0_logical_op__write_cr0$next[0:0]$6185 + assign $0\alu_logical0_logical_op__zero_a$next[0:0]$6168 $1\alu_logical0_logical_op__zero_a$next[0:0]$6186 + assign $0\alu_logical0_logical_op__imm_data__data$next[63:0]$6153 $2\alu_logical0_logical_op__imm_data__data$next[63:0]$6187 + assign $0\alu_logical0_logical_op__imm_data__ok$next[0:0]$6154 $2\alu_logical0_logical_op__imm_data__ok$next[0:0]$6188 + assign $0\alu_logical0_logical_op__oe__oe$next[0:0]$6162 $2\alu_logical0_logical_op__oe__oe$next[0:0]$6189 + assign $0\alu_logical0_logical_op__oe__ok$next[0:0]$6163 $2\alu_logical0_logical_op__oe__ok$next[0:0]$6190 + assign $0\alu_logical0_logical_op__rc__ok$next[0:0]$6165 $2\alu_logical0_logical_op__rc__ok$next[0:0]$6191 + assign $0\alu_logical0_logical_op__rc__rc$next[0:0]$6166 $2\alu_logical0_logical_op__rc__rc$next[0:0]$6192 + attribute \src "libresoc.v:130420.5-130420.29" + switch \initial + attribute \src "libresoc.v:130420.9-130420.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\alu_logical0_logical_op__insn$next[31:0]$6174 $1\alu_logical0_logical_op__data_len$next[3:0]$6169 $1\alu_logical0_logical_op__is_signed$next[0:0]$6179 $1\alu_logical0_logical_op__is_32bit$next[0:0]$6178 $1\alu_logical0_logical_op__output_carry$next[0:0]$6182 $1\alu_logical0_logical_op__write_cr0$next[0:0]$6185 $1\alu_logical0_logical_op__invert_out$next[0:0]$6177 $1\alu_logical0_logical_op__input_carry$next[1:0]$6173 $1\alu_logical0_logical_op__zero_a$next[0:0]$6186 $1\alu_logical0_logical_op__invert_in$next[0:0]$6176 $1\alu_logical0_logical_op__oe__ok$next[0:0]$6181 $1\alu_logical0_logical_op__oe__oe$next[0:0]$6180 $1\alu_logical0_logical_op__rc__ok$next[0:0]$6183 $1\alu_logical0_logical_op__rc__rc$next[0:0]$6184 $1\alu_logical0_logical_op__imm_data__ok$next[0:0]$6172 $1\alu_logical0_logical_op__imm_data__data$next[63:0]$6171 $1\alu_logical0_logical_op__fn_unit$next[11:0]$6170 $1\alu_logical0_logical_op__insn_type$next[6:0]$6175 } { \oper_i_alu_logical0__insn \oper_i_alu_logical0__data_len \oper_i_alu_logical0__is_signed \oper_i_alu_logical0__is_32bit \oper_i_alu_logical0__output_carry \oper_i_alu_logical0__write_cr0 \oper_i_alu_logical0__invert_out \oper_i_alu_logical0__input_carry \oper_i_alu_logical0__zero_a \oper_i_alu_logical0__invert_in \oper_i_alu_logical0__oe__ok \oper_i_alu_logical0__oe__oe \oper_i_alu_logical0__rc__ok \oper_i_alu_logical0__rc__rc \oper_i_alu_logical0__imm_data__ok \oper_i_alu_logical0__imm_data__data \oper_i_alu_logical0__fn_unit \oper_i_alu_logical0__insn_type } + case + assign $1\alu_logical0_logical_op__data_len$next[3:0]$6169 \alu_logical0_logical_op__data_len + assign $1\alu_logical0_logical_op__fn_unit$next[11:0]$6170 \alu_logical0_logical_op__fn_unit + assign $1\alu_logical0_logical_op__imm_data__data$next[63:0]$6171 \alu_logical0_logical_op__imm_data__data + assign $1\alu_logical0_logical_op__imm_data__ok$next[0:0]$6172 \alu_logical0_logical_op__imm_data__ok + assign $1\alu_logical0_logical_op__input_carry$next[1:0]$6173 \alu_logical0_logical_op__input_carry + assign $1\alu_logical0_logical_op__insn$next[31:0]$6174 \alu_logical0_logical_op__insn + assign $1\alu_logical0_logical_op__insn_type$next[6:0]$6175 \alu_logical0_logical_op__insn_type + assign $1\alu_logical0_logical_op__invert_in$next[0:0]$6176 \alu_logical0_logical_op__invert_in + assign $1\alu_logical0_logical_op__invert_out$next[0:0]$6177 \alu_logical0_logical_op__invert_out + assign $1\alu_logical0_logical_op__is_32bit$next[0:0]$6178 \alu_logical0_logical_op__is_32bit + assign $1\alu_logical0_logical_op__is_signed$next[0:0]$6179 \alu_logical0_logical_op__is_signed + assign $1\alu_logical0_logical_op__oe__oe$next[0:0]$6180 \alu_logical0_logical_op__oe__oe + assign $1\alu_logical0_logical_op__oe__ok$next[0:0]$6181 \alu_logical0_logical_op__oe__ok + assign $1\alu_logical0_logical_op__output_carry$next[0:0]$6182 \alu_logical0_logical_op__output_carry + assign $1\alu_logical0_logical_op__rc__ok$next[0:0]$6183 \alu_logical0_logical_op__rc__ok + assign $1\alu_logical0_logical_op__rc__rc$next[0:0]$6184 \alu_logical0_logical_op__rc__rc + assign $1\alu_logical0_logical_op__write_cr0$next[0:0]$6185 \alu_logical0_logical_op__write_cr0 + assign $1\alu_logical0_logical_op__zero_a$next[0:0]$6186 \alu_logical0_logical_op__zero_a + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $2\alu_logical0_logical_op__imm_data__data$next[63:0]$6187 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\alu_logical0_logical_op__imm_data__ok$next[0:0]$6188 1'0 + assign $2\alu_logical0_logical_op__rc__rc$next[0:0]$6192 1'0 + assign $2\alu_logical0_logical_op__rc__ok$next[0:0]$6191 1'0 + assign $2\alu_logical0_logical_op__oe__oe$next[0:0]$6189 1'0 + assign $2\alu_logical0_logical_op__oe__ok$next[0:0]$6190 1'0 + case + assign $2\alu_logical0_logical_op__imm_data__data$next[63:0]$6187 $1\alu_logical0_logical_op__imm_data__data$next[63:0]$6171 + assign $2\alu_logical0_logical_op__imm_data__ok$next[0:0]$6188 $1\alu_logical0_logical_op__imm_data__ok$next[0:0]$6172 + assign $2\alu_logical0_logical_op__oe__oe$next[0:0]$6189 $1\alu_logical0_logical_op__oe__oe$next[0:0]$6180 + assign $2\alu_logical0_logical_op__oe__ok$next[0:0]$6190 $1\alu_logical0_logical_op__oe__ok$next[0:0]$6181 + assign $2\alu_logical0_logical_op__rc__ok$next[0:0]$6191 $1\alu_logical0_logical_op__rc__ok$next[0:0]$6183 + assign $2\alu_logical0_logical_op__rc__rc$next[0:0]$6192 $1\alu_logical0_logical_op__rc__rc$next[0:0]$6184 + end + sync always + update \alu_logical0_logical_op__data_len$next $0\alu_logical0_logical_op__data_len$next[3:0]$6151 + update \alu_logical0_logical_op__fn_unit$next $0\alu_logical0_logical_op__fn_unit$next[11:0]$6152 + update \alu_logical0_logical_op__imm_data__data$next $0\alu_logical0_logical_op__imm_data__data$next[63:0]$6153 + update \alu_logical0_logical_op__imm_data__ok$next $0\alu_logical0_logical_op__imm_data__ok$next[0:0]$6154 + update \alu_logical0_logical_op__input_carry$next $0\alu_logical0_logical_op__input_carry$next[1:0]$6155 + update \alu_logical0_logical_op__insn$next $0\alu_logical0_logical_op__insn$next[31:0]$6156 + update \alu_logical0_logical_op__insn_type$next $0\alu_logical0_logical_op__insn_type$next[6:0]$6157 + update \alu_logical0_logical_op__invert_in$next $0\alu_logical0_logical_op__invert_in$next[0:0]$6158 + update \alu_logical0_logical_op__invert_out$next $0\alu_logical0_logical_op__invert_out$next[0:0]$6159 + update \alu_logical0_logical_op__is_32bit$next $0\alu_logical0_logical_op__is_32bit$next[0:0]$6160 + update \alu_logical0_logical_op__is_signed$next $0\alu_logical0_logical_op__is_signed$next[0:0]$6161 + update \alu_logical0_logical_op__oe__oe$next $0\alu_logical0_logical_op__oe__oe$next[0:0]$6162 + update \alu_logical0_logical_op__oe__ok$next $0\alu_logical0_logical_op__oe__ok$next[0:0]$6163 + update \alu_logical0_logical_op__output_carry$next $0\alu_logical0_logical_op__output_carry$next[0:0]$6164 + update \alu_logical0_logical_op__rc__ok$next $0\alu_logical0_logical_op__rc__ok$next[0:0]$6165 + update \alu_logical0_logical_op__rc__rc$next $0\alu_logical0_logical_op__rc__rc$next[0:0]$6166 + update \alu_logical0_logical_op__write_cr0$next $0\alu_logical0_logical_op__write_cr0$next[0:0]$6167 + update \alu_logical0_logical_op__zero_a$next $0\alu_logical0_logical_op__zero_a$next[0:0]$6168 + end + attribute \src "libresoc.v:130458.3-130479.6" + process $proc$libresoc.v:130458$6193 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r0__o$next[63:0]$6194 $2\data_r0__o$next[63:0]$6198 + assign { } { } + assign $0\data_r0__o_ok$next[0:0]$6195 $3\data_r0__o_ok$next[0:0]$6200 + attribute \src "libresoc.v:130459.5-130459.29" + switch \initial + attribute \src "libresoc.v:130459.9-130459.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r0__o_ok$next[0:0]$6197 $1\data_r0__o$next[63:0]$6196 } { \o_ok \alu_logical0_o } + case + assign $1\data_r0__o$next[63:0]$6196 \data_r0__o + assign $1\data_r0__o_ok$next[0:0]$6197 \data_r0__o_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r0__o_ok$next[0:0]$6199 $2\data_r0__o$next[63:0]$6198 } 65'00000000000000000000000000000000000000000000000000000000000000000 + case + assign $2\data_r0__o$next[63:0]$6198 $1\data_r0__o$next[63:0]$6196 + assign $2\data_r0__o_ok$next[0:0]$6199 $1\data_r0__o_ok$next[0:0]$6197 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r0__o_ok$next[0:0]$6200 1'0 + case + assign $3\data_r0__o_ok$next[0:0]$6200 $2\data_r0__o_ok$next[0:0]$6199 + end + sync always + update \data_r0__o$next $0\data_r0__o$next[63:0]$6194 + update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$6195 + end + attribute \src "libresoc.v:130480.3-130501.6" + process $proc$libresoc.v:130480$6201 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r1__cr_a$next[3:0]$6202 $2\data_r1__cr_a$next[3:0]$6206 + assign { } { } + assign $0\data_r1__cr_a_ok$next[0:0]$6203 $3\data_r1__cr_a_ok$next[0:0]$6208 + attribute \src "libresoc.v:130481.5-130481.29" + switch \initial + attribute \src "libresoc.v:130481.9-130481.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r1__cr_a_ok$next[0:0]$6205 $1\data_r1__cr_a$next[3:0]$6204 } { \cr_a_ok \alu_logical0_cr_a } + case + assign $1\data_r1__cr_a$next[3:0]$6204 \data_r1__cr_a + assign $1\data_r1__cr_a_ok$next[0:0]$6205 \data_r1__cr_a_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r1__cr_a_ok$next[0:0]$6207 $2\data_r1__cr_a$next[3:0]$6206 } 5'00000 + case + assign $2\data_r1__cr_a$next[3:0]$6206 $1\data_r1__cr_a$next[3:0]$6204 + assign $2\data_r1__cr_a_ok$next[0:0]$6207 $1\data_r1__cr_a_ok$next[0:0]$6205 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r1__cr_a_ok$next[0:0]$6208 1'0 + case + assign $3\data_r1__cr_a_ok$next[0:0]$6208 $2\data_r1__cr_a_ok$next[0:0]$6207 + end + sync always + update \data_r1__cr_a$next $0\data_r1__cr_a$next[3:0]$6202 + update \data_r1__cr_a_ok$next $0\data_r1__cr_a_ok$next[0:0]$6203 + end + attribute \src "libresoc.v:130502.3-130511.6" + process $proc$libresoc.v:130502$6209 + assign { } { } + assign { } { } + assign $0\src_r0$next[63:0]$6210 $1\src_r0$next[63:0]$6211 + attribute \src "libresoc.v:130503.5-130503.29" + switch \initial + attribute \src "libresoc.v:130503.9-130503.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch \src_sel + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r0$next[63:0]$6211 \src_or_imm + case + assign $1\src_r0$next[63:0]$6211 \src_r0 + end + sync always + update \src_r0$next $0\src_r0$next[63:0]$6210 + end + attribute \src "libresoc.v:130512.3-130521.6" + process $proc$libresoc.v:130512$6212 + assign { } { } + assign { } { } + assign $0\src_r1$next[63:0]$6213 $1\src_r1$next[63:0]$6214 + attribute \src "libresoc.v:130513.5-130513.29" + switch \initial + attribute \src "libresoc.v:130513.9-130513.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch \src_sel$77 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r1$next[63:0]$6214 \src_or_imm$80 + case + assign $1\src_r1$next[63:0]$6214 \src_r1 + end + sync always + update \src_r1$next $0\src_r1$next[63:0]$6213 + end + attribute \src "libresoc.v:130522.3-130531.6" + process $proc$libresoc.v:130522$6215 + assign { } { } + assign { } { } + assign $0\src_r2$next[0:0]$6216 $1\src_r2$next[0:0]$6217 + attribute \src "libresoc.v:130523.5-130523.29" + switch \initial + attribute \src "libresoc.v:130523.9-130523.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch \src_l_q_src [2] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r2$next[0:0]$6217 \src3_i + case + assign $1\src_r2$next[0:0]$6217 \src_r2 + end + sync always + update \src_r2$next $0\src_r2$next[0:0]$6216 + end + attribute \src "libresoc.v:130532.3-130540.6" + process $proc$libresoc.v:130532$6218 + assign { } { } + assign { } { } + assign $0\alui_l_r_alui$next[0:0]$6219 $1\alui_l_r_alui$next[0:0]$6220 + attribute \src "libresoc.v:130533.5-130533.29" + switch \initial + attribute \src "libresoc.v:130533.9-130533.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\alui_l_r_alui$next[0:0]$6220 1'1 + case + assign $1\alui_l_r_alui$next[0:0]$6220 \$89 + end + sync always + update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$6219 + end + attribute \src "libresoc.v:130541.3-130549.6" + process $proc$libresoc.v:130541$6221 + assign { } { } + assign { } { } + assign $0\alu_l_r_alu$next[0:0]$6222 $1\alu_l_r_alu$next[0:0]$6223 + attribute \src "libresoc.v:130542.5-130542.29" + switch \initial + attribute \src "libresoc.v:130542.9-130542.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\alu_l_r_alu$next[0:0]$6223 1'1 + case + assign $1\alu_l_r_alu$next[0:0]$6223 \$91 + end + sync always + update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$6222 + end + attribute \src "libresoc.v:130550.3-130559.6" + process $proc$libresoc.v:130550$6224 + assign { } { } + assign { } { } + assign $0\dest1_o[63:0] $1\dest1_o[63:0] + attribute \src "libresoc.v:130551.5-130551.29" + switch \initial + attribute \src "libresoc.v:130551.9-130551.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$113 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest1_o[63:0] \data_r0__o + case + assign $1\dest1_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \dest1_o $0\dest1_o[63:0] + end + attribute \src "libresoc.v:130560.3-130569.6" + process $proc$libresoc.v:130560$6225 + assign { } { } + assign { } { } + assign $0\dest2_o[3:0] $1\dest2_o[3:0] + attribute \src "libresoc.v:130561.5-130561.29" + switch \initial + attribute \src "libresoc.v:130561.9-130561.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$115 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest2_o[3:0] \data_r1__cr_a + case + assign $1\dest2_o[3:0] 4'0000 + end + sync always + update \dest2_o $0\dest2_o[3:0] + end + attribute \src "libresoc.v:130570.3-130578.6" + process $proc$libresoc.v:130570$6226 + assign { } { } + assign { } { } + assign $0\prev_wr_go$next[1:0]$6227 $1\prev_wr_go$next[1:0]$6228 + attribute \src "libresoc.v:130571.5-130571.29" + switch \initial + attribute \src "libresoc.v:130571.9-130571.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\prev_wr_go$next[1:0]$6228 2'00 + case + assign $1\prev_wr_go$next[1:0]$6228 \$19 + end + sync always + update \prev_wr_go$next $0\prev_wr_go$next[1:0]$6227 + end + connect \$9 $and$libresoc.v:130101$6022_Y + connect \$99 $and$libresoc.v:130102$6023_Y + connect \$101 $not$libresoc.v:130103$6024_Y + connect \$103 $and$libresoc.v:130104$6025_Y + connect \$105 $and$libresoc.v:130105$6026_Y + connect \$107 $and$libresoc.v:130106$6027_Y + connect \$109 $and$libresoc.v:130107$6028_Y + connect \$111 $and$libresoc.v:130108$6029_Y + connect \$113 $and$libresoc.v:130109$6030_Y + connect \$115 $and$libresoc.v:130110$6031_Y + connect \$11 $not$libresoc.v:130111$6032_Y + connect \$13 $and$libresoc.v:130112$6033_Y + connect \$15 $not$libresoc.v:130113$6034_Y + connect \$17 $and$libresoc.v:130114$6035_Y + connect \$1 $and$libresoc.v:130115$6036_Y + connect \$19 $and$libresoc.v:130116$6037_Y + connect \$23 $not$libresoc.v:130117$6038_Y + connect \$25 $and$libresoc.v:130118$6039_Y + connect \$22 $reduce_or$libresoc.v:130119$6040_Y + connect \$21 $not$libresoc.v:130120$6041_Y + connect \$29 $and$libresoc.v:130121$6042_Y + connect \$31 $reduce_or$libresoc.v:130122$6043_Y + connect \$33 $reduce_or$libresoc.v:130123$6044_Y + connect \$35 $or$libresoc.v:130124$6045_Y + connect \$37 $not$libresoc.v:130125$6046_Y + connect \$39 $and$libresoc.v:130126$6047_Y + connect \$41 $and$libresoc.v:130127$6048_Y + connect \$43 $eq$libresoc.v:130128$6049_Y + connect \$45 $and$libresoc.v:130129$6050_Y + connect \$47 $eq$libresoc.v:130130$6051_Y + connect \$4 $not$libresoc.v:130131$6052_Y + connect \$49 $and$libresoc.v:130132$6053_Y + connect \$51 $and$libresoc.v:130133$6054_Y + connect \$53 $and$libresoc.v:130134$6055_Y + connect \$55 $or$libresoc.v:130135$6056_Y + connect \$57 $or$libresoc.v:130136$6057_Y + connect \$59 $or$libresoc.v:130137$6058_Y + connect \$61 $or$libresoc.v:130138$6059_Y + connect \$63 $and$libresoc.v:130139$6060_Y + connect \$65 $and$libresoc.v:130140$6061_Y + connect \$67 $or$libresoc.v:130141$6062_Y + connect \$6 $or$libresoc.v:130142$6063_Y + connect \$69 $and$libresoc.v:130143$6064_Y + connect \$71 $and$libresoc.v:130144$6065_Y + connect \$73 $ternary$libresoc.v:130145$6066_Y + connect \$75 $ternary$libresoc.v:130146$6067_Y + connect \$78 $ternary$libresoc.v:130147$6068_Y + connect \$3 $reduce_and$libresoc.v:130148$6069_Y + connect \$81 $ternary$libresoc.v:130149$6070_Y + connect \$83 $ternary$libresoc.v:130150$6071_Y + connect \$85 $ternary$libresoc.v:130151$6072_Y + connect \$87 $ternary$libresoc.v:130152$6073_Y + connect \$89 $and$libresoc.v:130153$6074_Y + connect \$91 $and$libresoc.v:130154$6075_Y + connect \$93 $and$libresoc.v:130155$6076_Y + connect \$95 $not$libresoc.v:130156$6077_Y + connect \$97 $not$libresoc.v:130157$6078_Y + connect \cu_go_die_i 1'0 + connect \cu_shadown_i 1'1 + connect \cu_wr__rel_o \$111 + connect \cu_rd__rel_o \$103 + connect \cu_busy_o \opc_l_q_opc + connect \alu_l_s_alu \all_rd_pulse + connect \alu_logical0_n_ready_i \alu_l_q_alu + connect \alui_l_s_alui \all_rd_pulse + connect \alu_logical0_p_valid_i \alui_l_q_alui + connect \alu_logical0_xer_so \$87 + connect \alu_logical0_rb \$85 + connect \alu_logical0_ra \$83 + connect \src_or_imm$80 \$81 + connect \src_sel$77 \$78 + connect \src_or_imm \$75 + connect \src_sel \$73 + connect \cu_wrmask_o { \$71 \$69 } + connect \reset_r \$61 + connect \reset_w \$59 + connect \rst_r \$57 + connect \reset \$55 + connect \wr_any \$35 + connect \cu_done_o \$29 + connect \alu_pulsem { \alu_pulse \alu_pulse } + connect \alu_pulse \alu_done_rise + connect \alu_done_rise \$17 + connect \alu_done_dly$next \alu_done + connect \alu_done \alu_logical0_n_valid_o + connect \all_rd_pulse \all_rd_rise + connect \all_rd_rise \$13 + connect \all_rd_dly$next \all_rd + connect \all_rd \$9 +end +attribute \src "libresoc.v:130615.1-131985.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_logical0.logical_pipe1" +attribute \generator "nMigen" +module \logical_pipe1 + attribute \src "libresoc.v:131924.3-131942.6" + wire width 4 $0\cr_a$next[3:0]$6354 + attribute \src "libresoc.v:131684.3-131685.25" + wire width 4 $0\cr_a[3:0] + attribute \src "libresoc.v:131924.3-131942.6" + wire $0\cr_a_ok$next[0:0]$6355 + attribute \src "libresoc.v:131686.3-131687.31" + wire $0\cr_a_ok[0:0] + attribute \src "libresoc.v:130616.7-130616.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:131863.3-131904.6" + wire width 4 $0\logical_op__data_len$next[3:0]$6305 + attribute \src "libresoc.v:131724.3-131725.57" + wire width 4 $0\logical_op__data_len[3:0] + attribute \src "libresoc.v:131863.3-131904.6" + wire width 12 $0\logical_op__fn_unit$next[11:0]$6306 + attribute \src "libresoc.v:131694.3-131695.55" + wire width 12 $0\logical_op__fn_unit[11:0] + attribute \src "libresoc.v:131863.3-131904.6" + wire width 64 $0\logical_op__imm_data__data$next[63:0]$6307 + attribute \src "libresoc.v:131696.3-131697.69" + wire width 64 $0\logical_op__imm_data__data[63:0] + attribute \src "libresoc.v:131863.3-131904.6" + wire $0\logical_op__imm_data__ok$next[0:0]$6308 + attribute \src "libresoc.v:131698.3-131699.65" + wire $0\logical_op__imm_data__ok[0:0] + attribute \src "libresoc.v:131863.3-131904.6" + wire width 2 $0\logical_op__input_carry$next[1:0]$6309 + attribute \src "libresoc.v:131712.3-131713.63" + wire width 2 $0\logical_op__input_carry[1:0] + attribute \src "libresoc.v:131863.3-131904.6" + wire width 32 $0\logical_op__insn$next[31:0]$6310 + attribute \src "libresoc.v:131726.3-131727.49" + wire width 32 $0\logical_op__insn[31:0] + attribute \src "libresoc.v:131863.3-131904.6" + wire width 7 $0\logical_op__insn_type$next[6:0]$6311 + attribute \src "libresoc.v:131692.3-131693.59" + wire width 7 $0\logical_op__insn_type[6:0] + attribute \src "libresoc.v:131863.3-131904.6" + wire $0\logical_op__invert_in$next[0:0]$6312 + attribute \src "libresoc.v:131708.3-131709.59" + wire $0\logical_op__invert_in[0:0] + attribute \src "libresoc.v:131863.3-131904.6" + wire $0\logical_op__invert_out$next[0:0]$6313 + attribute \src "libresoc.v:131714.3-131715.61" + wire $0\logical_op__invert_out[0:0] + attribute \src "libresoc.v:131863.3-131904.6" + wire $0\logical_op__is_32bit$next[0:0]$6314 + attribute \src "libresoc.v:131720.3-131721.57" + wire $0\logical_op__is_32bit[0:0] + attribute \src "libresoc.v:131863.3-131904.6" + wire $0\logical_op__is_signed$next[0:0]$6315 + attribute \src "libresoc.v:131722.3-131723.59" + wire $0\logical_op__is_signed[0:0] + attribute \src "libresoc.v:131863.3-131904.6" + wire $0\logical_op__oe__oe$next[0:0]$6316 + attribute \src "libresoc.v:131704.3-131705.53" + wire $0\logical_op__oe__oe[0:0] + attribute \src "libresoc.v:131863.3-131904.6" + wire $0\logical_op__oe__ok$next[0:0]$6317 + attribute \src "libresoc.v:131706.3-131707.53" + wire $0\logical_op__oe__ok[0:0] + attribute \src "libresoc.v:131863.3-131904.6" + wire $0\logical_op__output_carry$next[0:0]$6318 + attribute \src "libresoc.v:131718.3-131719.65" + wire $0\logical_op__output_carry[0:0] + attribute \src "libresoc.v:131863.3-131904.6" + wire $0\logical_op__rc__ok$next[0:0]$6319 + attribute \src "libresoc.v:131702.3-131703.53" + wire $0\logical_op__rc__ok[0:0] + attribute \src "libresoc.v:131863.3-131904.6" + wire $0\logical_op__rc__rc$next[0:0]$6320 + attribute \src "libresoc.v:131700.3-131701.53" + wire $0\logical_op__rc__rc[0:0] + attribute \src "libresoc.v:131863.3-131904.6" + wire $0\logical_op__write_cr0$next[0:0]$6321 + attribute \src "libresoc.v:131716.3-131717.59" + wire $0\logical_op__write_cr0[0:0] + attribute \src "libresoc.v:131863.3-131904.6" + wire $0\logical_op__zero_a$next[0:0]$6322 + attribute \src "libresoc.v:131710.3-131711.53" + wire $0\logical_op__zero_a[0:0] + attribute \src "libresoc.v:131850.3-131862.6" + wire width 2 $0\muxid$next[1:0]$6302 + attribute \src "libresoc.v:131728.3-131729.27" + wire width 2 $0\muxid[1:0] + attribute \src "libresoc.v:131905.3-131923.6" + wire width 64 $0\o$next[63:0]$6348 + attribute \src "libresoc.v:131688.3-131689.19" + wire width 64 $0\o[63:0] + attribute \src "libresoc.v:131905.3-131923.6" + wire $0\o_ok$next[0:0]$6349 + attribute \src "libresoc.v:131690.3-131691.25" + wire $0\o_ok[0:0] + attribute \src "libresoc.v:131832.3-131849.6" + wire $0\r_busy$next[0:0]$6298 + attribute \src "libresoc.v:131730.3-131731.29" + wire $0\r_busy[0:0] + attribute \src "libresoc.v:131943.3-131961.6" + wire $0\xer_so$next[0:0]$6360 + attribute \src "libresoc.v:131680.3-131681.29" + wire $0\xer_so[0:0] + attribute \src "libresoc.v:131943.3-131961.6" + wire $0\xer_so_ok$next[0:0]$6361 + attribute \src "libresoc.v:131682.3-131683.35" + wire $0\xer_so_ok[0:0] + attribute \src "libresoc.v:131924.3-131942.6" + wire width 4 $1\cr_a$next[3:0]$6356 + attribute \src "libresoc.v:130625.13-130625.24" + wire width 4 $1\cr_a[3:0] + attribute \src "libresoc.v:131924.3-131942.6" + wire $1\cr_a_ok$next[0:0]$6357 + attribute \src "libresoc.v:130634.7-130634.21" + wire $1\cr_a_ok[0:0] + attribute \src "libresoc.v:131863.3-131904.6" + wire width 4 $1\logical_op__data_len$next[3:0]$6323 + attribute \src "libresoc.v:130913.13-130913.40" + wire width 4 $1\logical_op__data_len[3:0] + attribute \src "libresoc.v:131863.3-131904.6" + wire width 12 $1\logical_op__fn_unit$next[11:0]$6324 + attribute \src "libresoc.v:130935.14-130935.43" + wire width 12 $1\logical_op__fn_unit[11:0] + attribute \src "libresoc.v:131863.3-131904.6" + wire width 64 $1\logical_op__imm_data__data$next[63:0]$6325 + attribute \src "libresoc.v:130970.14-130970.63" + wire width 64 $1\logical_op__imm_data__data[63:0] + attribute \src "libresoc.v:131863.3-131904.6" + wire $1\logical_op__imm_data__ok$next[0:0]$6326 + attribute \src "libresoc.v:130979.7-130979.38" + wire $1\logical_op__imm_data__ok[0:0] + attribute \src "libresoc.v:131863.3-131904.6" + wire width 2 $1\logical_op__input_carry$next[1:0]$6327 + attribute \src "libresoc.v:130992.13-130992.43" + wire width 2 $1\logical_op__input_carry[1:0] + attribute \src "libresoc.v:131863.3-131904.6" + wire width 32 $1\logical_op__insn$next[31:0]$6328 + attribute \src "libresoc.v:131009.14-131009.38" + wire width 32 $1\logical_op__insn[31:0] + attribute \src "libresoc.v:131863.3-131904.6" + wire width 7 $1\logical_op__insn_type$next[6:0]$6329 + attribute \src "libresoc.v:131092.13-131092.42" + wire width 7 $1\logical_op__insn_type[6:0] + attribute \src "libresoc.v:131863.3-131904.6" + wire $1\logical_op__invert_in$next[0:0]$6330 + attribute \src "libresoc.v:131249.7-131249.35" + wire $1\logical_op__invert_in[0:0] + attribute \src "libresoc.v:131863.3-131904.6" + wire $1\logical_op__invert_out$next[0:0]$6331 + attribute \src "libresoc.v:131258.7-131258.36" + wire $1\logical_op__invert_out[0:0] + attribute \src "libresoc.v:131863.3-131904.6" + wire $1\logical_op__is_32bit$next[0:0]$6332 + attribute \src "libresoc.v:131267.7-131267.34" + wire $1\logical_op__is_32bit[0:0] + attribute \src "libresoc.v:131863.3-131904.6" + wire $1\logical_op__is_signed$next[0:0]$6333 + attribute \src "libresoc.v:131276.7-131276.35" + wire $1\logical_op__is_signed[0:0] + attribute \src "libresoc.v:131863.3-131904.6" + wire $1\logical_op__oe__oe$next[0:0]$6334 + attribute \src "libresoc.v:131285.7-131285.32" + wire $1\logical_op__oe__oe[0:0] + attribute \src "libresoc.v:131863.3-131904.6" + wire $1\logical_op__oe__ok$next[0:0]$6335 + attribute \src "libresoc.v:131294.7-131294.32" + wire $1\logical_op__oe__ok[0:0] + attribute \src "libresoc.v:131863.3-131904.6" + wire $1\logical_op__output_carry$next[0:0]$6336 + attribute \src "libresoc.v:131303.7-131303.38" + wire $1\logical_op__output_carry[0:0] + attribute \src "libresoc.v:131863.3-131904.6" + wire $1\logical_op__rc__ok$next[0:0]$6337 + attribute \src "libresoc.v:131312.7-131312.32" + wire $1\logical_op__rc__ok[0:0] + attribute \src "libresoc.v:131863.3-131904.6" + wire $1\logical_op__rc__rc$next[0:0]$6338 + attribute \src "libresoc.v:131321.7-131321.32" + wire $1\logical_op__rc__rc[0:0] + attribute \src "libresoc.v:131863.3-131904.6" + wire $1\logical_op__write_cr0$next[0:0]$6339 + attribute \src "libresoc.v:131330.7-131330.35" + wire $1\logical_op__write_cr0[0:0] + attribute \src "libresoc.v:131863.3-131904.6" + wire $1\logical_op__zero_a$next[0:0]$6340 + attribute \src "libresoc.v:131339.7-131339.32" + wire $1\logical_op__zero_a[0:0] + attribute \src "libresoc.v:131850.3-131862.6" + wire width 2 $1\muxid$next[1:0]$6303 + attribute \src "libresoc.v:131618.13-131618.25" + wire width 2 $1\muxid[1:0] + attribute \src "libresoc.v:131905.3-131923.6" + wire width 64 $1\o$next[63:0]$6350 + attribute \src "libresoc.v:131633.14-131633.38" + wire width 64 $1\o[63:0] + attribute \src "libresoc.v:131905.3-131923.6" + wire $1\o_ok$next[0:0]$6351 + attribute \src "libresoc.v:131640.7-131640.18" + wire $1\o_ok[0:0] + attribute \src "libresoc.v:131832.3-131849.6" + wire $1\r_busy$next[0:0]$6299 + attribute \src "libresoc.v:131654.7-131654.20" + wire $1\r_busy[0:0] + attribute \src "libresoc.v:131943.3-131961.6" + wire $1\xer_so$next[0:0]$6362 + attribute \src "libresoc.v:131663.7-131663.20" + wire $1\xer_so[0:0] + attribute \src "libresoc.v:131943.3-131961.6" + wire $1\xer_so_ok$next[0:0]$6363 + attribute \src "libresoc.v:131672.7-131672.23" + wire $1\xer_so_ok[0:0] + attribute \src "libresoc.v:131924.3-131942.6" + wire $2\cr_a_ok$next[0:0]$6358 + attribute \src "libresoc.v:131863.3-131904.6" + wire width 64 $2\logical_op__imm_data__data$next[63:0]$6341 + attribute \src "libresoc.v:131863.3-131904.6" + wire $2\logical_op__imm_data__ok$next[0:0]$6342 + attribute \src "libresoc.v:131863.3-131904.6" + wire $2\logical_op__oe__oe$next[0:0]$6343 + attribute \src "libresoc.v:131863.3-131904.6" + wire $2\logical_op__oe__ok$next[0:0]$6344 + attribute \src "libresoc.v:131863.3-131904.6" + wire $2\logical_op__rc__ok$next[0:0]$6345 + attribute \src "libresoc.v:131863.3-131904.6" + wire $2\logical_op__rc__rc$next[0:0]$6346 + attribute \src "libresoc.v:131905.3-131923.6" + wire $2\o_ok$next[0:0]$6352 + attribute \src "libresoc.v:131832.3-131849.6" + wire $2\r_busy$next[0:0]$6300 + attribute \src "libresoc.v:131943.3-131961.6" + wire $2\xer_so_ok$next[0:0]$6364 + attribute \src "libresoc.v:131679.18-131679.118" + wire $and$libresoc.v:131679$6270_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + wire \$64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 53 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 output 25 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \cr_a$87 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \cr_a$89 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \cr_a$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 26 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_a_ok$88 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_a_ok$90 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_a_ok$next + attribute \src "libresoc.v:130616.7-130616.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \input_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \input_logical_op__data_len$38 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \input_logical_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \input_logical_op__fn_unit$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \input_logical_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \input_logical_op__imm_data__data$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__imm_data__ok$25 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \input_logical_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \input_logical_op__input_carry$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \input_logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \input_logical_op__insn$39 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \input_logical_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \input_logical_op__insn_type$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__invert_in$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__invert_out$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__is_32bit$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__is_signed$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__oe__oe$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__oe__ok$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__output_carry$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__rc__ok$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__rc__rc$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__write_cr0$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__zero_a$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \input_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \input_muxid$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_ra$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_rb$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \input_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \input_xer_so$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 21 \logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 48 \logical_op__data_len$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \logical_op__data_len$83 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \logical_op__data_len$next + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 output 6 \logical_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 33 \logical_op__fn_unit$3 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \logical_op__fn_unit$68 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \logical_op__fn_unit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 7 \logical_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 34 \logical_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \logical_op__imm_data__data$69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \logical_op__imm_data__data$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 8 \logical_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 35 \logical_op__imm_data__ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__imm_data__ok$70 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__imm_data__ok$next + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 15 \logical_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 42 \logical_op__input_carry$12 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \logical_op__input_carry$77 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \logical_op__input_carry$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 22 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 49 \logical_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \logical_op__insn$84 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \logical_op__insn$next + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 5 \logical_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 32 \logical_op__insn_type$2 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \logical_op__insn_type$67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \logical_op__insn_type$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 13 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 40 \logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_in$75 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_in$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 16 \logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 43 \logical_op__invert_out$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_out$78 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_out$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 19 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 46 \logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_32bit$81 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_32bit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 20 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 47 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_signed$82 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_signed$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 11 \logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__oe$73 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 38 \logical_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__oe$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 12 \logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__ok$74 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 39 \logical_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 18 \logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 45 \logical_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__output_carry$80 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__output_carry$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 10 \logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 37 \logical_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__ok$72 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 9 \logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 36 \logical_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__rc$71 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__rc$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 17 \logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 44 \logical_op__write_cr0$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__write_cr0$79 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__write_cr0$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 14 \logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 41 \logical_op__zero_a$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__zero_a$76 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__zero_a$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \main_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \main_logical_op__data_len$60 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \main_logical_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \main_logical_op__fn_unit$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \main_logical_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \main_logical_op__imm_data__data$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_logical_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_logical_op__imm_data__ok$47 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \main_logical_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \main_logical_op__input_carry$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \main_logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \main_logical_op__insn$61 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \main_logical_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \main_logical_op__insn_type$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_logical_op__invert_in$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_logical_op__invert_out$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_logical_op__is_32bit$58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_logical_op__is_signed$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_logical_op__oe__oe$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_logical_op__oe__ok$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_logical_op__output_carry$57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_logical_op__rc__ok$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_logical_op__rc__rc$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_logical_op__write_cr0$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_logical_op__zero_a$53 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \main_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \main_muxid$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \main_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \main_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \main_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \main_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \main_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \main_xer_so$62 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 4 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 31 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$66 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" + wire \n_i_rdy_data + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire input 3 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire output 2 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 23 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \o$85 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \o$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 24 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \o_ok$86 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \o_ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire output 30 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire input 29 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" + wire \p_valid_i$63 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire \r_busy$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 50 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 51 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 27 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 52 \xer_so$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \xer_so$91 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \xer_so$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 28 \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \xer_so_ok$92 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \xer_so_ok$93 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \xer_so_ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + cell $and $and$libresoc.v:131679$6270 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i$63 + connect \B \p_ready_o + connect \Y $and$libresoc.v:131679$6270_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:131732.14-131777.4" + cell \input$47 \input + connect \logical_op__data_len \input_logical_op__data_len + connect \logical_op__data_len$18 \input_logical_op__data_len$38 + connect \logical_op__fn_unit \input_logical_op__fn_unit + connect \logical_op__fn_unit$3 \input_logical_op__fn_unit$23 + connect \logical_op__imm_data__data \input_logical_op__imm_data__data + connect \logical_op__imm_data__data$4 \input_logical_op__imm_data__data$24 + connect \logical_op__imm_data__ok \input_logical_op__imm_data__ok + connect \logical_op__imm_data__ok$5 \input_logical_op__imm_data__ok$25 + connect \logical_op__input_carry \input_logical_op__input_carry + connect \logical_op__input_carry$12 \input_logical_op__input_carry$32 + connect \logical_op__insn \input_logical_op__insn + connect \logical_op__insn$19 \input_logical_op__insn$39 + connect \logical_op__insn_type \input_logical_op__insn_type + connect \logical_op__insn_type$2 \input_logical_op__insn_type$22 + connect \logical_op__invert_in \input_logical_op__invert_in + connect \logical_op__invert_in$10 \input_logical_op__invert_in$30 + connect \logical_op__invert_out \input_logical_op__invert_out + connect \logical_op__invert_out$13 \input_logical_op__invert_out$33 + connect \logical_op__is_32bit \input_logical_op__is_32bit + connect \logical_op__is_32bit$16 \input_logical_op__is_32bit$36 + connect \logical_op__is_signed \input_logical_op__is_signed + connect \logical_op__is_signed$17 \input_logical_op__is_signed$37 + connect \logical_op__oe__oe \input_logical_op__oe__oe + connect \logical_op__oe__oe$8 \input_logical_op__oe__oe$28 + connect \logical_op__oe__ok \input_logical_op__oe__ok + connect \logical_op__oe__ok$9 \input_logical_op__oe__ok$29 + connect \logical_op__output_carry \input_logical_op__output_carry + connect \logical_op__output_carry$15 \input_logical_op__output_carry$35 + connect \logical_op__rc__ok \input_logical_op__rc__ok + connect \logical_op__rc__ok$7 \input_logical_op__rc__ok$27 + connect \logical_op__rc__rc \input_logical_op__rc__rc + connect \logical_op__rc__rc$6 \input_logical_op__rc__rc$26 + connect \logical_op__write_cr0 \input_logical_op__write_cr0 + connect \logical_op__write_cr0$14 \input_logical_op__write_cr0$34 + connect \logical_op__zero_a \input_logical_op__zero_a + connect \logical_op__zero_a$11 \input_logical_op__zero_a$31 + connect \muxid \input_muxid + connect \muxid$1 \input_muxid$21 + connect \ra \input_ra + connect \ra$20 \input_ra$40 + connect \rb \input_rb + connect \rb$21 \input_rb$41 + connect \xer_so \input_xer_so + connect \xer_so$22 \input_xer_so$42 + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:131778.13-131823.4" + cell \main$48 \main + connect \logical_op__data_len \main_logical_op__data_len + connect \logical_op__data_len$18 \main_logical_op__data_len$60 + connect \logical_op__fn_unit \main_logical_op__fn_unit + connect \logical_op__fn_unit$3 \main_logical_op__fn_unit$45 + connect \logical_op__imm_data__data \main_logical_op__imm_data__data + connect \logical_op__imm_data__data$4 \main_logical_op__imm_data__data$46 + connect \logical_op__imm_data__ok \main_logical_op__imm_data__ok + connect \logical_op__imm_data__ok$5 \main_logical_op__imm_data__ok$47 + connect \logical_op__input_carry \main_logical_op__input_carry + connect \logical_op__input_carry$12 \main_logical_op__input_carry$54 + connect \logical_op__insn \main_logical_op__insn + connect \logical_op__insn$19 \main_logical_op__insn$61 + connect \logical_op__insn_type \main_logical_op__insn_type + connect \logical_op__insn_type$2 \main_logical_op__insn_type$44 + connect \logical_op__invert_in \main_logical_op__invert_in + connect \logical_op__invert_in$10 \main_logical_op__invert_in$52 + connect \logical_op__invert_out \main_logical_op__invert_out + connect \logical_op__invert_out$13 \main_logical_op__invert_out$55 + connect \logical_op__is_32bit \main_logical_op__is_32bit + connect \logical_op__is_32bit$16 \main_logical_op__is_32bit$58 + connect \logical_op__is_signed \main_logical_op__is_signed + connect \logical_op__is_signed$17 \main_logical_op__is_signed$59 + connect \logical_op__oe__oe \main_logical_op__oe__oe + connect \logical_op__oe__oe$8 \main_logical_op__oe__oe$50 + connect \logical_op__oe__ok \main_logical_op__oe__ok + connect \logical_op__oe__ok$9 \main_logical_op__oe__ok$51 + connect \logical_op__output_carry \main_logical_op__output_carry + connect \logical_op__output_carry$15 \main_logical_op__output_carry$57 + connect \logical_op__rc__ok \main_logical_op__rc__ok + connect \logical_op__rc__ok$7 \main_logical_op__rc__ok$49 + connect \logical_op__rc__rc \main_logical_op__rc__rc + connect \logical_op__rc__rc$6 \main_logical_op__rc__rc$48 + connect \logical_op__write_cr0 \main_logical_op__write_cr0 + connect \logical_op__write_cr0$14 \main_logical_op__write_cr0$56 + connect \logical_op__zero_a \main_logical_op__zero_a + connect \logical_op__zero_a$11 \main_logical_op__zero_a$53 + connect \muxid \main_muxid + connect \muxid$1 \main_muxid$43 + connect \o \main_o + connect \o_ok \main_o_ok + connect \ra \main_ra + connect \rb \main_rb + connect \xer_so \main_xer_so + connect \xer_so$20 \main_xer_so$62 + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:131824.10-131827.4" + cell \n$46 \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:131828.10-131831.4" + cell \p$45 \p + connect \p_ready_o \p_ready_o + connect \p_valid_i \p_valid_i + end + attribute \src "libresoc.v:130616.7-130616.20" + process $proc$libresoc.v:130616$6365 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:130625.13-130625.24" + process $proc$libresoc.v:130625$6366 + assign { } { } + assign $1\cr_a[3:0] 4'0000 + sync always + sync init + update \cr_a $1\cr_a[3:0] + end + attribute \src "libresoc.v:130634.7-130634.21" + process $proc$libresoc.v:130634$6367 + assign { } { } + assign $1\cr_a_ok[0:0] 1'0 + sync always + sync init + update \cr_a_ok $1\cr_a_ok[0:0] + end + attribute \src "libresoc.v:130913.13-130913.40" + process $proc$libresoc.v:130913$6368 + assign { } { } + assign $1\logical_op__data_len[3:0] 4'0000 + sync always + sync init + update \logical_op__data_len $1\logical_op__data_len[3:0] + end + attribute \src "libresoc.v:130935.14-130935.43" + process $proc$libresoc.v:130935$6369 + assign { } { } + assign $1\logical_op__fn_unit[11:0] 12'000000000000 + sync always + sync init + update \logical_op__fn_unit $1\logical_op__fn_unit[11:0] + end + attribute \src "libresoc.v:130970.14-130970.63" + process $proc$libresoc.v:130970$6370 + assign { } { } + assign $1\logical_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \logical_op__imm_data__data $1\logical_op__imm_data__data[63:0] + end + attribute \src "libresoc.v:130979.7-130979.38" + process $proc$libresoc.v:130979$6371 + assign { } { } + assign $1\logical_op__imm_data__ok[0:0] 1'0 + sync always + sync init + update \logical_op__imm_data__ok $1\logical_op__imm_data__ok[0:0] + end + attribute \src "libresoc.v:130992.13-130992.43" + process $proc$libresoc.v:130992$6372 + assign { } { } + assign $1\logical_op__input_carry[1:0] 2'00 + sync always + sync init + update \logical_op__input_carry $1\logical_op__input_carry[1:0] + end + attribute \src "libresoc.v:131009.14-131009.38" + process $proc$libresoc.v:131009$6373 + assign { } { } + assign $1\logical_op__insn[31:0] 0 + sync always + sync init + update \logical_op__insn $1\logical_op__insn[31:0] + end + attribute \src "libresoc.v:131092.13-131092.42" + process $proc$libresoc.v:131092$6374 + assign { } { } + assign $1\logical_op__insn_type[6:0] 7'0000000 + sync always + sync init + update \logical_op__insn_type $1\logical_op__insn_type[6:0] + end + attribute \src "libresoc.v:131249.7-131249.35" + process $proc$libresoc.v:131249$6375 + assign { } { } + assign $1\logical_op__invert_in[0:0] 1'0 + sync always + sync init + update \logical_op__invert_in $1\logical_op__invert_in[0:0] + end + attribute \src "libresoc.v:131258.7-131258.36" + process $proc$libresoc.v:131258$6376 + assign { } { } + assign $1\logical_op__invert_out[0:0] 1'0 + sync always + sync init + update \logical_op__invert_out $1\logical_op__invert_out[0:0] + end + attribute \src "libresoc.v:131267.7-131267.34" + process $proc$libresoc.v:131267$6377 + assign { } { } + assign $1\logical_op__is_32bit[0:0] 1'0 + sync always + sync init + update \logical_op__is_32bit $1\logical_op__is_32bit[0:0] + end + attribute \src "libresoc.v:131276.7-131276.35" + process $proc$libresoc.v:131276$6378 + assign { } { } + assign $1\logical_op__is_signed[0:0] 1'0 + sync always + sync init + update \logical_op__is_signed $1\logical_op__is_signed[0:0] + end + attribute \src "libresoc.v:131285.7-131285.32" + process $proc$libresoc.v:131285$6379 + assign { } { } + assign $1\logical_op__oe__oe[0:0] 1'0 + sync always + sync init + update \logical_op__oe__oe $1\logical_op__oe__oe[0:0] + end + attribute \src "libresoc.v:131294.7-131294.32" + process $proc$libresoc.v:131294$6380 + assign { } { } + assign $1\logical_op__oe__ok[0:0] 1'0 + sync always + sync init + update \logical_op__oe__ok $1\logical_op__oe__ok[0:0] + end + attribute \src "libresoc.v:131303.7-131303.38" + process $proc$libresoc.v:131303$6381 + assign { } { } + assign $1\logical_op__output_carry[0:0] 1'0 + sync always + sync init + update \logical_op__output_carry $1\logical_op__output_carry[0:0] + end + attribute \src "libresoc.v:131312.7-131312.32" + process $proc$libresoc.v:131312$6382 + assign { } { } + assign $1\logical_op__rc__ok[0:0] 1'0 + sync always + sync init + update \logical_op__rc__ok $1\logical_op__rc__ok[0:0] + end + attribute \src "libresoc.v:131321.7-131321.32" + process $proc$libresoc.v:131321$6383 + assign { } { } + assign $1\logical_op__rc__rc[0:0] 1'0 + sync always + sync init + update \logical_op__rc__rc $1\logical_op__rc__rc[0:0] + end + attribute \src "libresoc.v:131330.7-131330.35" + process $proc$libresoc.v:131330$6384 + assign { } { } + assign $1\logical_op__write_cr0[0:0] 1'0 + sync always + sync init + update \logical_op__write_cr0 $1\logical_op__write_cr0[0:0] + end + attribute \src "libresoc.v:131339.7-131339.32" + process $proc$libresoc.v:131339$6385 + assign { } { } + assign $1\logical_op__zero_a[0:0] 1'0 + sync always + sync init + update \logical_op__zero_a $1\logical_op__zero_a[0:0] + end + attribute \src "libresoc.v:131618.13-131618.25" + process $proc$libresoc.v:131618$6386 + assign { } { } + assign $1\muxid[1:0] 2'00 + sync always + sync init + update \muxid $1\muxid[1:0] + end + attribute \src "libresoc.v:131633.14-131633.38" + process $proc$libresoc.v:131633$6387 + assign { } { } + assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \o $1\o[63:0] + end + attribute \src "libresoc.v:131640.7-131640.18" + process $proc$libresoc.v:131640$6388 + assign { } { } + assign $1\o_ok[0:0] 1'0 + sync always + sync init + update \o_ok $1\o_ok[0:0] + end + attribute \src "libresoc.v:131654.7-131654.20" + process $proc$libresoc.v:131654$6389 + assign { } { } + assign $1\r_busy[0:0] 1'0 + sync always + sync init + update \r_busy $1\r_busy[0:0] + end + attribute \src "libresoc.v:131663.7-131663.20" + process $proc$libresoc.v:131663$6390 + assign { } { } + assign $1\xer_so[0:0] 1'0 + sync always + sync init + update \xer_so $1\xer_so[0:0] + end + attribute \src "libresoc.v:131672.7-131672.23" + process $proc$libresoc.v:131672$6391 + assign { } { } + assign $1\xer_so_ok[0:0] 1'0 + sync always + sync init + update \xer_so_ok $1\xer_so_ok[0:0] + end + attribute \src "libresoc.v:131680.3-131681.29" + process $proc$libresoc.v:131680$6271 + assign { } { } + assign $0\xer_so[0:0] \xer_so$next + sync posedge \coresync_clk + update \xer_so $0\xer_so[0:0] + end + attribute \src "libresoc.v:131682.3-131683.35" + process $proc$libresoc.v:131682$6272 + assign { } { } + assign $0\xer_so_ok[0:0] \xer_so_ok$next + sync posedge \coresync_clk + update \xer_so_ok $0\xer_so_ok[0:0] + end + attribute \src "libresoc.v:131684.3-131685.25" + process $proc$libresoc.v:131684$6273 + assign { } { } + assign $0\cr_a[3:0] \cr_a$next + sync posedge \coresync_clk + update \cr_a $0\cr_a[3:0] + end + attribute \src "libresoc.v:131686.3-131687.31" + process $proc$libresoc.v:131686$6274 + assign { } { } + assign $0\cr_a_ok[0:0] \cr_a_ok$next + sync posedge \coresync_clk + update \cr_a_ok $0\cr_a_ok[0:0] + end + attribute \src "libresoc.v:131688.3-131689.19" + process $proc$libresoc.v:131688$6275 + assign { } { } + assign $0\o[63:0] \o$next + sync posedge \coresync_clk + update \o $0\o[63:0] + end + attribute \src "libresoc.v:131690.3-131691.25" + process $proc$libresoc.v:131690$6276 + assign { } { } + assign $0\o_ok[0:0] \o_ok$next + sync posedge \coresync_clk + update \o_ok $0\o_ok[0:0] + end + attribute \src "libresoc.v:131692.3-131693.59" + process $proc$libresoc.v:131692$6277 + assign { } { } + assign $0\logical_op__insn_type[6:0] \logical_op__insn_type$next + sync posedge \coresync_clk + update \logical_op__insn_type $0\logical_op__insn_type[6:0] + end + attribute \src "libresoc.v:131694.3-131695.55" + process $proc$libresoc.v:131694$6278 + assign { } { } + assign $0\logical_op__fn_unit[11:0] \logical_op__fn_unit$next + sync posedge \coresync_clk + update \logical_op__fn_unit $0\logical_op__fn_unit[11:0] + end + attribute \src "libresoc.v:131696.3-131697.69" + process $proc$libresoc.v:131696$6279 + assign { } { } + assign $0\logical_op__imm_data__data[63:0] \logical_op__imm_data__data$next + sync posedge \coresync_clk + update \logical_op__imm_data__data $0\logical_op__imm_data__data[63:0] + end + attribute \src "libresoc.v:131698.3-131699.65" + process $proc$libresoc.v:131698$6280 + assign { } { } + assign $0\logical_op__imm_data__ok[0:0] \logical_op__imm_data__ok$next + sync posedge \coresync_clk + update \logical_op__imm_data__ok $0\logical_op__imm_data__ok[0:0] + end + attribute \src "libresoc.v:131700.3-131701.53" + process $proc$libresoc.v:131700$6281 + assign { } { } + assign $0\logical_op__rc__rc[0:0] \logical_op__rc__rc$next + sync posedge \coresync_clk + update \logical_op__rc__rc $0\logical_op__rc__rc[0:0] + end + attribute \src "libresoc.v:131702.3-131703.53" + process $proc$libresoc.v:131702$6282 + assign { } { } + assign $0\logical_op__rc__ok[0:0] \logical_op__rc__ok$next + sync posedge \coresync_clk + update \logical_op__rc__ok $0\logical_op__rc__ok[0:0] + end + attribute \src "libresoc.v:131704.3-131705.53" + process $proc$libresoc.v:131704$6283 + assign { } { } + assign $0\logical_op__oe__oe[0:0] \logical_op__oe__oe$next + sync posedge \coresync_clk + update \logical_op__oe__oe $0\logical_op__oe__oe[0:0] + end + attribute \src "libresoc.v:131706.3-131707.53" + process $proc$libresoc.v:131706$6284 + assign { } { } + assign $0\logical_op__oe__ok[0:0] \logical_op__oe__ok$next + sync posedge \coresync_clk + update \logical_op__oe__ok $0\logical_op__oe__ok[0:0] + end + attribute \src "libresoc.v:131708.3-131709.59" + process $proc$libresoc.v:131708$6285 + assign { } { } + assign $0\logical_op__invert_in[0:0] \logical_op__invert_in$next + sync posedge \coresync_clk + update \logical_op__invert_in $0\logical_op__invert_in[0:0] + end + attribute \src "libresoc.v:131710.3-131711.53" + process $proc$libresoc.v:131710$6286 + assign { } { } + assign $0\logical_op__zero_a[0:0] \logical_op__zero_a$next + sync posedge \coresync_clk + update \logical_op__zero_a $0\logical_op__zero_a[0:0] + end + attribute \src "libresoc.v:131712.3-131713.63" + process $proc$libresoc.v:131712$6287 + assign { } { } + assign $0\logical_op__input_carry[1:0] \logical_op__input_carry$next + sync posedge \coresync_clk + update \logical_op__input_carry $0\logical_op__input_carry[1:0] + end + attribute \src "libresoc.v:131714.3-131715.61" + process $proc$libresoc.v:131714$6288 + assign { } { } + assign $0\logical_op__invert_out[0:0] \logical_op__invert_out$next + sync posedge \coresync_clk + update \logical_op__invert_out $0\logical_op__invert_out[0:0] + end + attribute \src "libresoc.v:131716.3-131717.59" + process $proc$libresoc.v:131716$6289 + assign { } { } + assign $0\logical_op__write_cr0[0:0] \logical_op__write_cr0$next + sync posedge \coresync_clk + update \logical_op__write_cr0 $0\logical_op__write_cr0[0:0] + end + attribute \src "libresoc.v:131718.3-131719.65" + process $proc$libresoc.v:131718$6290 + assign { } { } + assign $0\logical_op__output_carry[0:0] \logical_op__output_carry$next + sync posedge \coresync_clk + update \logical_op__output_carry $0\logical_op__output_carry[0:0] + end + attribute \src "libresoc.v:131720.3-131721.57" + process $proc$libresoc.v:131720$6291 + assign { } { } + assign $0\logical_op__is_32bit[0:0] \logical_op__is_32bit$next + sync posedge \coresync_clk + update \logical_op__is_32bit $0\logical_op__is_32bit[0:0] + end + attribute \src "libresoc.v:131722.3-131723.59" + process $proc$libresoc.v:131722$6292 + assign { } { } + assign $0\logical_op__is_signed[0:0] \logical_op__is_signed$next + sync posedge \coresync_clk + update \logical_op__is_signed $0\logical_op__is_signed[0:0] + end + attribute \src "libresoc.v:131724.3-131725.57" + process $proc$libresoc.v:131724$6293 + assign { } { } + assign $0\logical_op__data_len[3:0] \logical_op__data_len$next + sync posedge \coresync_clk + update \logical_op__data_len $0\logical_op__data_len[3:0] + end + attribute \src "libresoc.v:131726.3-131727.49" + process $proc$libresoc.v:131726$6294 + assign { } { } + assign $0\logical_op__insn[31:0] \logical_op__insn$next + sync posedge \coresync_clk + update \logical_op__insn $0\logical_op__insn[31:0] + end + attribute \src "libresoc.v:131728.3-131729.27" + process $proc$libresoc.v:131728$6295 + assign { } { } + assign $0\muxid[1:0] \muxid$next + sync posedge \coresync_clk + update \muxid $0\muxid[1:0] + end + attribute \src "libresoc.v:131730.3-131731.29" + process $proc$libresoc.v:131730$6296 + assign { } { } + assign $0\r_busy[0:0] \r_busy$next + sync posedge \coresync_clk + update \r_busy $0\r_busy[0:0] + end + attribute \src "libresoc.v:131832.3-131849.6" + process $proc$libresoc.v:131832$6297 + assign { } { } + assign { } { } + assign { } { } + assign $0\r_busy$next[0:0]$6298 $2\r_busy$next[0:0]$6300 + attribute \src "libresoc.v:131833.5-131833.29" + switch \initial + attribute \src "libresoc.v:131833.9-131833.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\r_busy$next[0:0]$6299 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\r_busy$next[0:0]$6299 1'0 + case + assign $1\r_busy$next[0:0]$6299 \r_busy + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r_busy$next[0:0]$6300 1'0 + case + assign $2\r_busy$next[0:0]$6300 $1\r_busy$next[0:0]$6299 + end + sync always + update \r_busy$next $0\r_busy$next[0:0]$6298 + end + attribute \src "libresoc.v:131850.3-131862.6" + process $proc$libresoc.v:131850$6301 + assign { } { } + assign { } { } + assign $0\muxid$next[1:0]$6302 $1\muxid$next[1:0]$6303 + attribute \src "libresoc.v:131851.5-131851.29" + switch \initial + attribute \src "libresoc.v:131851.9-131851.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\muxid$next[1:0]$6303 \muxid$66 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\muxid$next[1:0]$6303 \muxid$66 + case + assign $1\muxid$next[1:0]$6303 \muxid + end + sync always + update \muxid$next $0\muxid$next[1:0]$6302 + end + attribute \src "libresoc.v:131863.3-131904.6" + process $proc$libresoc.v:131863$6304 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\logical_op__data_len$next[3:0]$6305 $1\logical_op__data_len$next[3:0]$6323 + assign $0\logical_op__fn_unit$next[11:0]$6306 $1\logical_op__fn_unit$next[11:0]$6324 + assign { } { } + assign { } { } + assign $0\logical_op__input_carry$next[1:0]$6309 $1\logical_op__input_carry$next[1:0]$6327 + assign $0\logical_op__insn$next[31:0]$6310 $1\logical_op__insn$next[31:0]$6328 + assign $0\logical_op__insn_type$next[6:0]$6311 $1\logical_op__insn_type$next[6:0]$6329 + assign $0\logical_op__invert_in$next[0:0]$6312 $1\logical_op__invert_in$next[0:0]$6330 + assign $0\logical_op__invert_out$next[0:0]$6313 $1\logical_op__invert_out$next[0:0]$6331 + assign $0\logical_op__is_32bit$next[0:0]$6314 $1\logical_op__is_32bit$next[0:0]$6332 + assign $0\logical_op__is_signed$next[0:0]$6315 $1\logical_op__is_signed$next[0:0]$6333 + assign { } { } + assign { } { } + assign $0\logical_op__output_carry$next[0:0]$6318 $1\logical_op__output_carry$next[0:0]$6336 + assign { } { } + assign { } { } + assign $0\logical_op__write_cr0$next[0:0]$6321 $1\logical_op__write_cr0$next[0:0]$6339 + assign $0\logical_op__zero_a$next[0:0]$6322 $1\logical_op__zero_a$next[0:0]$6340 + assign $0\logical_op__imm_data__data$next[63:0]$6307 $2\logical_op__imm_data__data$next[63:0]$6341 + assign $0\logical_op__imm_data__ok$next[0:0]$6308 $2\logical_op__imm_data__ok$next[0:0]$6342 + assign $0\logical_op__oe__oe$next[0:0]$6316 $2\logical_op__oe__oe$next[0:0]$6343 + assign $0\logical_op__oe__ok$next[0:0]$6317 $2\logical_op__oe__ok$next[0:0]$6344 + assign $0\logical_op__rc__ok$next[0:0]$6319 $2\logical_op__rc__ok$next[0:0]$6345 + assign $0\logical_op__rc__rc$next[0:0]$6320 $2\logical_op__rc__rc$next[0:0]$6346 + attribute \src "libresoc.v:131864.5-131864.29" + switch \initial + attribute \src "libresoc.v:131864.9-131864.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\logical_op__insn$next[31:0]$6328 $1\logical_op__data_len$next[3:0]$6323 $1\logical_op__is_signed$next[0:0]$6333 $1\logical_op__is_32bit$next[0:0]$6332 $1\logical_op__output_carry$next[0:0]$6336 $1\logical_op__write_cr0$next[0:0]$6339 $1\logical_op__invert_out$next[0:0]$6331 $1\logical_op__input_carry$next[1:0]$6327 $1\logical_op__zero_a$next[0:0]$6340 $1\logical_op__invert_in$next[0:0]$6330 $1\logical_op__oe__ok$next[0:0]$6335 $1\logical_op__oe__oe$next[0:0]$6334 $1\logical_op__rc__ok$next[0:0]$6337 $1\logical_op__rc__rc$next[0:0]$6338 $1\logical_op__imm_data__ok$next[0:0]$6326 $1\logical_op__imm_data__data$next[63:0]$6325 $1\logical_op__fn_unit$next[11:0]$6324 $1\logical_op__insn_type$next[6:0]$6329 } { \logical_op__insn$84 \logical_op__data_len$83 \logical_op__is_signed$82 \logical_op__is_32bit$81 \logical_op__output_carry$80 \logical_op__write_cr0$79 \logical_op__invert_out$78 \logical_op__input_carry$77 \logical_op__zero_a$76 \logical_op__invert_in$75 \logical_op__oe__ok$74 \logical_op__oe__oe$73 \logical_op__rc__ok$72 \logical_op__rc__rc$71 \logical_op__imm_data__ok$70 \logical_op__imm_data__data$69 \logical_op__fn_unit$68 \logical_op__insn_type$67 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\logical_op__insn$next[31:0]$6328 $1\logical_op__data_len$next[3:0]$6323 $1\logical_op__is_signed$next[0:0]$6333 $1\logical_op__is_32bit$next[0:0]$6332 $1\logical_op__output_carry$next[0:0]$6336 $1\logical_op__write_cr0$next[0:0]$6339 $1\logical_op__invert_out$next[0:0]$6331 $1\logical_op__input_carry$next[1:0]$6327 $1\logical_op__zero_a$next[0:0]$6340 $1\logical_op__invert_in$next[0:0]$6330 $1\logical_op__oe__ok$next[0:0]$6335 $1\logical_op__oe__oe$next[0:0]$6334 $1\logical_op__rc__ok$next[0:0]$6337 $1\logical_op__rc__rc$next[0:0]$6338 $1\logical_op__imm_data__ok$next[0:0]$6326 $1\logical_op__imm_data__data$next[63:0]$6325 $1\logical_op__fn_unit$next[11:0]$6324 $1\logical_op__insn_type$next[6:0]$6329 } { \logical_op__insn$84 \logical_op__data_len$83 \logical_op__is_signed$82 \logical_op__is_32bit$81 \logical_op__output_carry$80 \logical_op__write_cr0$79 \logical_op__invert_out$78 \logical_op__input_carry$77 \logical_op__zero_a$76 \logical_op__invert_in$75 \logical_op__oe__ok$74 \logical_op__oe__oe$73 \logical_op__rc__ok$72 \logical_op__rc__rc$71 \logical_op__imm_data__ok$70 \logical_op__imm_data__data$69 \logical_op__fn_unit$68 \logical_op__insn_type$67 } + case + assign $1\logical_op__data_len$next[3:0]$6323 \logical_op__data_len + assign $1\logical_op__fn_unit$next[11:0]$6324 \logical_op__fn_unit + assign $1\logical_op__imm_data__data$next[63:0]$6325 \logical_op__imm_data__data + assign $1\logical_op__imm_data__ok$next[0:0]$6326 \logical_op__imm_data__ok + assign $1\logical_op__input_carry$next[1:0]$6327 \logical_op__input_carry + assign $1\logical_op__insn$next[31:0]$6328 \logical_op__insn + assign $1\logical_op__insn_type$next[6:0]$6329 \logical_op__insn_type + assign $1\logical_op__invert_in$next[0:0]$6330 \logical_op__invert_in + assign $1\logical_op__invert_out$next[0:0]$6331 \logical_op__invert_out + assign $1\logical_op__is_32bit$next[0:0]$6332 \logical_op__is_32bit + assign $1\logical_op__is_signed$next[0:0]$6333 \logical_op__is_signed + assign $1\logical_op__oe__oe$next[0:0]$6334 \logical_op__oe__oe + assign $1\logical_op__oe__ok$next[0:0]$6335 \logical_op__oe__ok + assign $1\logical_op__output_carry$next[0:0]$6336 \logical_op__output_carry + assign $1\logical_op__rc__ok$next[0:0]$6337 \logical_op__rc__ok + assign $1\logical_op__rc__rc$next[0:0]$6338 \logical_op__rc__rc + assign $1\logical_op__write_cr0$next[0:0]$6339 \logical_op__write_cr0 + assign $1\logical_op__zero_a$next[0:0]$6340 \logical_op__zero_a + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $2\logical_op__imm_data__data$next[63:0]$6341 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\logical_op__imm_data__ok$next[0:0]$6342 1'0 + assign $2\logical_op__rc__rc$next[0:0]$6346 1'0 + assign $2\logical_op__rc__ok$next[0:0]$6345 1'0 + assign $2\logical_op__oe__oe$next[0:0]$6343 1'0 + assign $2\logical_op__oe__ok$next[0:0]$6344 1'0 + case + assign $2\logical_op__imm_data__data$next[63:0]$6341 $1\logical_op__imm_data__data$next[63:0]$6325 + assign $2\logical_op__imm_data__ok$next[0:0]$6342 $1\logical_op__imm_data__ok$next[0:0]$6326 + assign $2\logical_op__oe__oe$next[0:0]$6343 $1\logical_op__oe__oe$next[0:0]$6334 + assign $2\logical_op__oe__ok$next[0:0]$6344 $1\logical_op__oe__ok$next[0:0]$6335 + assign $2\logical_op__rc__ok$next[0:0]$6345 $1\logical_op__rc__ok$next[0:0]$6337 + assign $2\logical_op__rc__rc$next[0:0]$6346 $1\logical_op__rc__rc$next[0:0]$6338 + end + sync always + update \logical_op__data_len$next $0\logical_op__data_len$next[3:0]$6305 + update \logical_op__fn_unit$next $0\logical_op__fn_unit$next[11:0]$6306 + update \logical_op__imm_data__data$next $0\logical_op__imm_data__data$next[63:0]$6307 + update \logical_op__imm_data__ok$next $0\logical_op__imm_data__ok$next[0:0]$6308 + update \logical_op__input_carry$next $0\logical_op__input_carry$next[1:0]$6309 + update \logical_op__insn$next $0\logical_op__insn$next[31:0]$6310 + update \logical_op__insn_type$next $0\logical_op__insn_type$next[6:0]$6311 + update \logical_op__invert_in$next $0\logical_op__invert_in$next[0:0]$6312 + update \logical_op__invert_out$next $0\logical_op__invert_out$next[0:0]$6313 + update \logical_op__is_32bit$next $0\logical_op__is_32bit$next[0:0]$6314 + update \logical_op__is_signed$next $0\logical_op__is_signed$next[0:0]$6315 + update \logical_op__oe__oe$next $0\logical_op__oe__oe$next[0:0]$6316 + update \logical_op__oe__ok$next $0\logical_op__oe__ok$next[0:0]$6317 + update \logical_op__output_carry$next $0\logical_op__output_carry$next[0:0]$6318 + update \logical_op__rc__ok$next $0\logical_op__rc__ok$next[0:0]$6319 + update \logical_op__rc__rc$next $0\logical_op__rc__rc$next[0:0]$6320 + update \logical_op__write_cr0$next $0\logical_op__write_cr0$next[0:0]$6321 + update \logical_op__zero_a$next $0\logical_op__zero_a$next[0:0]$6322 + end + attribute \src "libresoc.v:131905.3-131923.6" + process $proc$libresoc.v:131905$6347 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\o$next[63:0]$6348 $1\o$next[63:0]$6350 + assign { } { } + assign $0\o_ok$next[0:0]$6349 $2\o_ok$next[0:0]$6352 + attribute \src "libresoc.v:131906.5-131906.29" + switch \initial + attribute \src "libresoc.v:131906.9-131906.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\o_ok$next[0:0]$6351 $1\o$next[63:0]$6350 } { \o_ok$86 \o$85 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\o_ok$next[0:0]$6351 $1\o$next[63:0]$6350 } { \o_ok$86 \o$85 } + case + assign $1\o$next[63:0]$6350 \o + assign $1\o_ok$next[0:0]$6351 \o_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\o_ok$next[0:0]$6352 1'0 + case + assign $2\o_ok$next[0:0]$6352 $1\o_ok$next[0:0]$6351 + end + sync always + update \o$next $0\o$next[63:0]$6348 + update \o_ok$next $0\o_ok$next[0:0]$6349 + end + attribute \src "libresoc.v:131924.3-131942.6" + process $proc$libresoc.v:131924$6353 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\cr_a$next[3:0]$6354 $1\cr_a$next[3:0]$6356 + assign { } { } + assign $0\cr_a_ok$next[0:0]$6355 $2\cr_a_ok$next[0:0]$6358 + attribute \src "libresoc.v:131925.5-131925.29" + switch \initial + attribute \src "libresoc.v:131925.9-131925.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\cr_a_ok$next[0:0]$6357 $1\cr_a$next[3:0]$6356 } { \cr_a_ok$88 \cr_a$87 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\cr_a_ok$next[0:0]$6357 $1\cr_a$next[3:0]$6356 } { \cr_a_ok$88 \cr_a$87 } + case + assign $1\cr_a$next[3:0]$6356 \cr_a + assign $1\cr_a_ok$next[0:0]$6357 \cr_a_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_a_ok$next[0:0]$6358 1'0 + case + assign $2\cr_a_ok$next[0:0]$6358 $1\cr_a_ok$next[0:0]$6357 + end + sync always + update \cr_a$next $0\cr_a$next[3:0]$6354 + update \cr_a_ok$next $0\cr_a_ok$next[0:0]$6355 + end + attribute \src "libresoc.v:131943.3-131961.6" + process $proc$libresoc.v:131943$6359 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\xer_so$next[0:0]$6360 $1\xer_so$next[0:0]$6362 + assign { } { } + assign $0\xer_so_ok$next[0:0]$6361 $2\xer_so_ok$next[0:0]$6364 + attribute \src "libresoc.v:131944.5-131944.29" + switch \initial + attribute \src "libresoc.v:131944.9-131944.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\xer_so_ok$next[0:0]$6363 $1\xer_so$next[0:0]$6362 } { \xer_so_ok$92 \xer_so$91 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\xer_so_ok$next[0:0]$6363 $1\xer_so$next[0:0]$6362 } { \xer_so_ok$92 \xer_so$91 } + case + assign $1\xer_so$next[0:0]$6362 \xer_so + assign $1\xer_so_ok$next[0:0]$6363 \xer_so_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\xer_so_ok$next[0:0]$6364 1'0 + case + assign $2\xer_so_ok$next[0:0]$6364 $1\xer_so_ok$next[0:0]$6363 + end + sync always + update \xer_so$next $0\xer_so$next[0:0]$6360 + update \xer_so_ok$next $0\xer_so_ok$next[0:0]$6361 + end + connect \$64 $and$libresoc.v:131679$6270_Y + connect \cr_a$89 4'0000 + connect \cr_a_ok$90 1'0 + connect \xer_so_ok$93 1'0 + connect \p_ready_o \n_i_rdy_data + connect \n_valid_o \r_busy + connect { \xer_so_ok$92 \xer_so$91 } { 1'0 \main_xer_so$62 } + connect { \cr_a_ok$88 \cr_a$87 } 5'00000 + connect { \o_ok$86 \o$85 } { \main_o_ok \main_o } + connect { \logical_op__insn$84 \logical_op__data_len$83 \logical_op__is_signed$82 \logical_op__is_32bit$81 \logical_op__output_carry$80 \logical_op__write_cr0$79 \logical_op__invert_out$78 \logical_op__input_carry$77 \logical_op__zero_a$76 \logical_op__invert_in$75 \logical_op__oe__ok$74 \logical_op__oe__oe$73 \logical_op__rc__ok$72 \logical_op__rc__rc$71 \logical_op__imm_data__ok$70 \logical_op__imm_data__data$69 \logical_op__fn_unit$68 \logical_op__insn_type$67 } { \main_logical_op__insn$61 \main_logical_op__data_len$60 \main_logical_op__is_signed$59 \main_logical_op__is_32bit$58 \main_logical_op__output_carry$57 \main_logical_op__write_cr0$56 \main_logical_op__invert_out$55 \main_logical_op__input_carry$54 \main_logical_op__zero_a$53 \main_logical_op__invert_in$52 \main_logical_op__oe__ok$51 \main_logical_op__oe__oe$50 \main_logical_op__rc__ok$49 \main_logical_op__rc__rc$48 \main_logical_op__imm_data__ok$47 \main_logical_op__imm_data__data$46 \main_logical_op__fn_unit$45 \main_logical_op__insn_type$44 } + connect \muxid$66 \main_muxid$43 + connect \p_valid_i_p_ready_o \$64 + connect \n_i_rdy_data \n_ready_i + connect \p_valid_i$63 \p_valid_i + connect \main_xer_so \input_xer_so$42 + connect \main_rb \input_rb$41 + connect \main_ra \input_ra$40 + connect { \main_logical_op__insn \main_logical_op__data_len \main_logical_op__is_signed \main_logical_op__is_32bit \main_logical_op__output_carry \main_logical_op__write_cr0 \main_logical_op__invert_out \main_logical_op__input_carry \main_logical_op__zero_a \main_logical_op__invert_in \main_logical_op__oe__ok \main_logical_op__oe__oe \main_logical_op__rc__ok \main_logical_op__rc__rc \main_logical_op__imm_data__ok \main_logical_op__imm_data__data \main_logical_op__fn_unit \main_logical_op__insn_type } { \input_logical_op__insn$39 \input_logical_op__data_len$38 \input_logical_op__is_signed$37 \input_logical_op__is_32bit$36 \input_logical_op__output_carry$35 \input_logical_op__write_cr0$34 \input_logical_op__invert_out$33 \input_logical_op__input_carry$32 \input_logical_op__zero_a$31 \input_logical_op__invert_in$30 \input_logical_op__oe__ok$29 \input_logical_op__oe__oe$28 \input_logical_op__rc__ok$27 \input_logical_op__rc__rc$26 \input_logical_op__imm_data__ok$25 \input_logical_op__imm_data__data$24 \input_logical_op__fn_unit$23 \input_logical_op__insn_type$22 } + connect \main_muxid \input_muxid$21 + connect \input_xer_so \xer_so$20 + connect \input_rb \rb + connect \input_ra \ra + connect { \input_logical_op__insn \input_logical_op__data_len \input_logical_op__is_signed \input_logical_op__is_32bit \input_logical_op__output_carry \input_logical_op__write_cr0 \input_logical_op__invert_out \input_logical_op__input_carry \input_logical_op__zero_a \input_logical_op__invert_in \input_logical_op__oe__ok \input_logical_op__oe__oe \input_logical_op__rc__ok \input_logical_op__rc__rc \input_logical_op__imm_data__ok \input_logical_op__imm_data__data \input_logical_op__fn_unit \input_logical_op__insn_type } { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } + connect \input_muxid \muxid$1 +end +attribute \src "libresoc.v:131989.1-133007.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_logical0.logical_pipe2" +attribute \generator "nMigen" +module \logical_pipe2 + attribute \src "libresoc.v:132974.3-132992.6" + wire width 4 $0\cr_a$22$next[3:0]$6497 + attribute \src "libresoc.v:132778.3-132779.33" + wire width 4 $0\cr_a$22[3:0]$6394 + attribute \src "libresoc.v:132001.13-132001.29" + wire width 4 $0\cr_a$22[3:0]$6504 + attribute \src "libresoc.v:132974.3-132992.6" + wire $0\cr_a_ok$23$next[0:0]$6498 + attribute \src "libresoc.v:132780.3-132781.39" + wire $0\cr_a_ok$23[0:0]$6396 + attribute \src "libresoc.v:132010.7-132010.26" + wire $0\cr_a_ok$23[0:0]$6506 + attribute \src "libresoc.v:131990.7-131990.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:132913.3-132954.6" + wire width 4 $0\logical_op__data_len$18$next[3:0]$6448 + attribute \src "libresoc.v:132818.3-132819.65" + wire width 4 $0\logical_op__data_len$18[3:0]$6434 + attribute \src "libresoc.v:132021.13-132021.45" + wire width 4 $0\logical_op__data_len$18[3:0]$6508 + attribute \src "libresoc.v:132913.3-132954.6" + wire width 12 $0\logical_op__fn_unit$3$next[11:0]$6449 + attribute \src "libresoc.v:132788.3-132789.61" + wire width 12 $0\logical_op__fn_unit$3[11:0]$6404 + attribute \src "libresoc.v:132056.14-132056.47" + wire width 12 $0\logical_op__fn_unit$3[11:0]$6510 + attribute \src "libresoc.v:132913.3-132954.6" + wire width 64 $0\logical_op__imm_data__data$4$next[63:0]$6450 + attribute \src "libresoc.v:132790.3-132791.75" + wire width 64 $0\logical_op__imm_data__data$4[63:0]$6406 + attribute \src "libresoc.v:132078.14-132078.67" + wire width 64 $0\logical_op__imm_data__data$4[63:0]$6512 + attribute \src "libresoc.v:132913.3-132954.6" + wire $0\logical_op__imm_data__ok$5$next[0:0]$6451 + attribute \src "libresoc.v:132792.3-132793.71" + wire $0\logical_op__imm_data__ok$5[0:0]$6408 + attribute \src "libresoc.v:132087.7-132087.42" + wire $0\logical_op__imm_data__ok$5[0:0]$6514 + attribute \src "libresoc.v:132913.3-132954.6" + wire width 2 $0\logical_op__input_carry$12$next[1:0]$6452 + attribute \src "libresoc.v:132806.3-132807.71" + wire width 2 $0\logical_op__input_carry$12[1:0]$6422 + attribute \src "libresoc.v:132104.13-132104.48" + wire width 2 $0\logical_op__input_carry$12[1:0]$6516 + attribute \src "libresoc.v:132913.3-132954.6" + wire width 32 $0\logical_op__insn$19$next[31:0]$6453 + attribute \src "libresoc.v:132820.3-132821.57" + wire width 32 $0\logical_op__insn$19[31:0]$6436 + attribute \src "libresoc.v:132117.14-132117.43" + wire width 32 $0\logical_op__insn$19[31:0]$6518 + attribute \src "libresoc.v:132913.3-132954.6" + wire width 7 $0\logical_op__insn_type$2$next[6:0]$6454 + attribute \src "libresoc.v:132786.3-132787.65" + wire width 7 $0\logical_op__insn_type$2[6:0]$6402 + attribute \src "libresoc.v:132274.13-132274.46" + wire width 7 $0\logical_op__insn_type$2[6:0]$6520 + attribute \src "libresoc.v:132913.3-132954.6" + wire $0\logical_op__invert_in$10$next[0:0]$6455 + attribute \src "libresoc.v:132802.3-132803.67" + wire $0\logical_op__invert_in$10[0:0]$6418 + attribute \src "libresoc.v:132357.7-132357.40" + wire $0\logical_op__invert_in$10[0:0]$6522 + attribute \src "libresoc.v:132913.3-132954.6" + wire $0\logical_op__invert_out$13$next[0:0]$6456 + attribute \src "libresoc.v:132808.3-132809.69" + wire $0\logical_op__invert_out$13[0:0]$6424 + attribute \src "libresoc.v:132366.7-132366.41" + wire $0\logical_op__invert_out$13[0:0]$6524 + attribute \src "libresoc.v:132913.3-132954.6" + wire $0\logical_op__is_32bit$16$next[0:0]$6457 + attribute \src "libresoc.v:132814.3-132815.65" + wire $0\logical_op__is_32bit$16[0:0]$6430 + attribute \src "libresoc.v:132375.7-132375.39" + wire $0\logical_op__is_32bit$16[0:0]$6526 + attribute \src "libresoc.v:132913.3-132954.6" + wire $0\logical_op__is_signed$17$next[0:0]$6458 + attribute \src "libresoc.v:132816.3-132817.67" + wire $0\logical_op__is_signed$17[0:0]$6432 + attribute \src "libresoc.v:132384.7-132384.40" + wire $0\logical_op__is_signed$17[0:0]$6528 + attribute \src "libresoc.v:132913.3-132954.6" + wire $0\logical_op__oe__oe$8$next[0:0]$6459 + attribute \src "libresoc.v:132798.3-132799.59" + wire $0\logical_op__oe__oe$8[0:0]$6414 + attribute \src "libresoc.v:132395.7-132395.36" + wire $0\logical_op__oe__oe$8[0:0]$6530 + attribute \src "libresoc.v:132913.3-132954.6" + wire $0\logical_op__oe__ok$9$next[0:0]$6460 + attribute \src "libresoc.v:132800.3-132801.59" + wire $0\logical_op__oe__ok$9[0:0]$6416 + attribute \src "libresoc.v:132404.7-132404.36" + wire $0\logical_op__oe__ok$9[0:0]$6532 + attribute \src "libresoc.v:132913.3-132954.6" + wire $0\logical_op__output_carry$15$next[0:0]$6461 + attribute \src "libresoc.v:132812.3-132813.73" + wire $0\logical_op__output_carry$15[0:0]$6428 + attribute \src "libresoc.v:132411.7-132411.43" + wire $0\logical_op__output_carry$15[0:0]$6534 + attribute \src "libresoc.v:132913.3-132954.6" + wire $0\logical_op__rc__ok$7$next[0:0]$6462 + attribute \src "libresoc.v:132796.3-132797.59" + wire $0\logical_op__rc__ok$7[0:0]$6412 + attribute \src "libresoc.v:132422.7-132422.36" + wire $0\logical_op__rc__ok$7[0:0]$6536 + attribute \src "libresoc.v:132913.3-132954.6" + wire $0\logical_op__rc__rc$6$next[0:0]$6463 + attribute \src "libresoc.v:132794.3-132795.59" + wire $0\logical_op__rc__rc$6[0:0]$6410 + attribute \src "libresoc.v:132431.7-132431.36" + wire $0\logical_op__rc__rc$6[0:0]$6538 + attribute \src "libresoc.v:132913.3-132954.6" + wire $0\logical_op__write_cr0$14$next[0:0]$6464 + attribute \src "libresoc.v:132810.3-132811.67" + wire $0\logical_op__write_cr0$14[0:0]$6426 + attribute \src "libresoc.v:132438.7-132438.40" + wire $0\logical_op__write_cr0$14[0:0]$6540 + attribute \src "libresoc.v:132913.3-132954.6" + wire $0\logical_op__zero_a$11$next[0:0]$6465 + attribute \src "libresoc.v:132804.3-132805.61" + wire $0\logical_op__zero_a$11[0:0]$6420 + attribute \src "libresoc.v:132447.7-132447.37" + wire $0\logical_op__zero_a$11[0:0]$6542 + attribute \src "libresoc.v:132900.3-132912.6" + wire width 2 $0\muxid$1$next[1:0]$6445 + attribute \src "libresoc.v:132822.3-132823.33" + wire width 2 $0\muxid$1[1:0]$6438 + attribute \src "libresoc.v:132456.13-132456.29" + wire width 2 $0\muxid$1[1:0]$6544 + attribute \src "libresoc.v:132955.3-132973.6" + wire width 64 $0\o$20$next[63:0]$6491 + attribute \src "libresoc.v:132782.3-132783.27" + wire width 64 $0\o$20[63:0]$6398 + attribute \src "libresoc.v:132471.14-132471.43" + wire width 64 $0\o$20[63:0]$6546 + attribute \src "libresoc.v:132955.3-132973.6" + wire $0\o_ok$21$next[0:0]$6492 + attribute \src "libresoc.v:132784.3-132785.33" + wire $0\o_ok$21[0:0]$6400 + attribute \src "libresoc.v:132480.7-132480.23" + wire $0\o_ok$21[0:0]$6548 + attribute \src "libresoc.v:132882.3-132899.6" + wire $0\r_busy$next[0:0]$6441 + attribute \src "libresoc.v:132824.3-132825.29" + wire $0\r_busy[0:0] + attribute \src "libresoc.v:132974.3-132992.6" + wire width 4 $1\cr_a$22$next[3:0]$6499 + attribute \src "libresoc.v:132974.3-132992.6" + wire $1\cr_a_ok$23$next[0:0]$6500 + attribute \src "libresoc.v:132913.3-132954.6" + wire width 4 $1\logical_op__data_len$18$next[3:0]$6466 + attribute \src "libresoc.v:132913.3-132954.6" + wire width 12 $1\logical_op__fn_unit$3$next[11:0]$6467 + attribute \src "libresoc.v:132913.3-132954.6" + wire width 64 $1\logical_op__imm_data__data$4$next[63:0]$6468 + attribute \src "libresoc.v:132913.3-132954.6" + wire $1\logical_op__imm_data__ok$5$next[0:0]$6469 + attribute \src "libresoc.v:132913.3-132954.6" + wire width 2 $1\logical_op__input_carry$12$next[1:0]$6470 + attribute \src "libresoc.v:132913.3-132954.6" + wire width 32 $1\logical_op__insn$19$next[31:0]$6471 + attribute \src "libresoc.v:132913.3-132954.6" + wire width 7 $1\logical_op__insn_type$2$next[6:0]$6472 + attribute \src "libresoc.v:132913.3-132954.6" + wire $1\logical_op__invert_in$10$next[0:0]$6473 + attribute \src "libresoc.v:132913.3-132954.6" + wire $1\logical_op__invert_out$13$next[0:0]$6474 + attribute \src "libresoc.v:132913.3-132954.6" + wire $1\logical_op__is_32bit$16$next[0:0]$6475 + attribute \src "libresoc.v:132913.3-132954.6" + wire $1\logical_op__is_signed$17$next[0:0]$6476 + attribute \src "libresoc.v:132913.3-132954.6" + wire $1\logical_op__oe__oe$8$next[0:0]$6477 + attribute \src "libresoc.v:132913.3-132954.6" + wire $1\logical_op__oe__ok$9$next[0:0]$6478 + attribute \src "libresoc.v:132913.3-132954.6" + wire $1\logical_op__output_carry$15$next[0:0]$6479 + attribute \src "libresoc.v:132913.3-132954.6" + wire $1\logical_op__rc__ok$7$next[0:0]$6480 + attribute \src "libresoc.v:132913.3-132954.6" + wire $1\logical_op__rc__rc$6$next[0:0]$6481 + attribute \src "libresoc.v:132913.3-132954.6" + wire $1\logical_op__write_cr0$14$next[0:0]$6482 + attribute \src "libresoc.v:132913.3-132954.6" + wire $1\logical_op__zero_a$11$next[0:0]$6483 + attribute \src "libresoc.v:132900.3-132912.6" + wire width 2 $1\muxid$1$next[1:0]$6446 + attribute \src "libresoc.v:132955.3-132973.6" + wire width 64 $1\o$20$next[63:0]$6493 + attribute \src "libresoc.v:132955.3-132973.6" + wire $1\o_ok$21$next[0:0]$6494 + attribute \src "libresoc.v:132882.3-132899.6" + wire $1\r_busy$next[0:0]$6442 + attribute \src "libresoc.v:132768.7-132768.20" + wire $1\r_busy[0:0] + attribute \src "libresoc.v:132974.3-132992.6" + wire $2\cr_a_ok$23$next[0:0]$6501 + attribute \src "libresoc.v:132913.3-132954.6" + wire width 64 $2\logical_op__imm_data__data$4$next[63:0]$6484 + attribute \src "libresoc.v:132913.3-132954.6" + wire $2\logical_op__imm_data__ok$5$next[0:0]$6485 + attribute \src "libresoc.v:132913.3-132954.6" + wire $2\logical_op__oe__oe$8$next[0:0]$6486 + attribute \src "libresoc.v:132913.3-132954.6" + wire $2\logical_op__oe__ok$9$next[0:0]$6487 + attribute \src "libresoc.v:132913.3-132954.6" + wire $2\logical_op__rc__ok$7$next[0:0]$6488 + attribute \src "libresoc.v:132913.3-132954.6" + wire $2\logical_op__rc__rc$6$next[0:0]$6489 + attribute \src "libresoc.v:132955.3-132973.6" + wire $2\o_ok$21$next[0:0]$6495 + attribute \src "libresoc.v:132882.3-132899.6" + wire $2\r_busy$next[0:0]$6443 + attribute \src "libresoc.v:132777.18-132777.118" + wire $and$libresoc.v:132777$6392_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + wire \$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 54 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 input 25 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 output 52 \cr_a$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \cr_a$22$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \cr_a$72 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire input 26 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 53 \cr_a_ok$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_a_ok$23$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_a_ok$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_a_ok$73 + attribute \src "libresoc.v:131990.7-131990.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 21 \logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 48 \logical_op__data_len$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \logical_op__data_len$18$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \logical_op__data_len$68 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 6 \logical_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 output 33 \logical_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \logical_op__fn_unit$3$next + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \logical_op__fn_unit$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 7 \logical_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 34 \logical_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \logical_op__imm_data__data$4$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \logical_op__imm_data__data$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \logical_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 35 \logical_op__imm_data__ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__imm_data__ok$5$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__imm_data__ok$55 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 15 \logical_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 42 \logical_op__input_carry$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \logical_op__input_carry$12$next + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \logical_op__input_carry$62 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 22 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 49 \logical_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \logical_op__insn$19$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \logical_op__insn$69 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 5 \logical_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 32 \logical_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \logical_op__insn_type$2$next + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \logical_op__insn_type$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 40 \logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_in$10$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_in$60 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 16 \logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 43 \logical_op__invert_out$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_out$13$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_out$63 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 19 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 46 \logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_32bit$16$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_32bit$66 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 20 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 47 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_signed$17$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_signed$67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 11 \logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__oe$58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 38 \logical_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__oe$8$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__ok$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 39 \logical_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__ok$9$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 18 \logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 45 \logical_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__output_carry$15$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__output_carry$65 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__ok$57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 37 \logical_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__ok$7$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__rc$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 36 \logical_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__rc$6$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 17 \logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 44 \logical_op__write_cr0$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__write_cr0$14$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__write_cr0$64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 41 \logical_op__zero_a$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__zero_a$11$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__zero_a$61 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 4 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 31 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$1$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$51 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" + wire \n_i_rdy_data + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire input 30 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire output 29 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 input 23 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 50 \o$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \o$20$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \o$70 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire input 24 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 51 \o_ok$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \o_ok$21$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \o_ok$71 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \output_cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \output_cr_a$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \output_cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \output_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \output_logical_op__data_len$41 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \output_logical_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \output_logical_op__fn_unit$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \output_logical_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \output_logical_op__imm_data__data$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__imm_data__ok$28 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \output_logical_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \output_logical_op__input_carry$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \output_logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \output_logical_op__insn$42 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \output_logical_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \output_logical_op__insn_type$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__invert_in$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__invert_out$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__is_32bit$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__is_signed$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__oe__oe$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__oe__ok$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__output_carry$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__rc__ok$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__rc__rc$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__write_cr0$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__zero_a$34 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \output_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \output_muxid$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \output_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \output_o$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \output_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \output_o_ok$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \output_xer_so + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire output 3 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" + wire \p_valid_i$48 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire \r_busy$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire input 27 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire input 28 \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \xer_so_ok$47 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + cell $and $and$libresoc.v:132777$6392 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i$48 + connect \B \p_ready_o + connect \Y $and$libresoc.v:132777$6392_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:132826.10-132829.4" + cell \n$50 \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:132830.15-132877.4" + cell \output$51 \output + connect \cr_a \output_cr_a + connect \cr_a$22 \output_cr_a$45 + connect \cr_a_ok \output_cr_a_ok + connect \logical_op__data_len \output_logical_op__data_len + connect \logical_op__data_len$18 \output_logical_op__data_len$41 + connect \logical_op__fn_unit \output_logical_op__fn_unit + connect \logical_op__fn_unit$3 \output_logical_op__fn_unit$26 + connect \logical_op__imm_data__data \output_logical_op__imm_data__data + connect \logical_op__imm_data__data$4 \output_logical_op__imm_data__data$27 + connect \logical_op__imm_data__ok \output_logical_op__imm_data__ok + connect \logical_op__imm_data__ok$5 \output_logical_op__imm_data__ok$28 + connect \logical_op__input_carry \output_logical_op__input_carry + connect \logical_op__input_carry$12 \output_logical_op__input_carry$35 + connect \logical_op__insn \output_logical_op__insn + connect \logical_op__insn$19 \output_logical_op__insn$42 + connect \logical_op__insn_type \output_logical_op__insn_type + connect \logical_op__insn_type$2 \output_logical_op__insn_type$25 + connect \logical_op__invert_in \output_logical_op__invert_in + connect \logical_op__invert_in$10 \output_logical_op__invert_in$33 + connect \logical_op__invert_out \output_logical_op__invert_out + connect \logical_op__invert_out$13 \output_logical_op__invert_out$36 + connect \logical_op__is_32bit \output_logical_op__is_32bit + connect \logical_op__is_32bit$16 \output_logical_op__is_32bit$39 + connect \logical_op__is_signed \output_logical_op__is_signed + connect \logical_op__is_signed$17 \output_logical_op__is_signed$40 + connect \logical_op__oe__oe \output_logical_op__oe__oe + connect \logical_op__oe__oe$8 \output_logical_op__oe__oe$31 + connect \logical_op__oe__ok \output_logical_op__oe__ok + connect \logical_op__oe__ok$9 \output_logical_op__oe__ok$32 + connect \logical_op__output_carry \output_logical_op__output_carry + connect \logical_op__output_carry$15 \output_logical_op__output_carry$38 + connect \logical_op__rc__ok \output_logical_op__rc__ok + connect \logical_op__rc__ok$7 \output_logical_op__rc__ok$30 + connect \logical_op__rc__rc \output_logical_op__rc__rc + connect \logical_op__rc__rc$6 \output_logical_op__rc__rc$29 + connect \logical_op__write_cr0 \output_logical_op__write_cr0 + connect \logical_op__write_cr0$14 \output_logical_op__write_cr0$37 + connect \logical_op__zero_a \output_logical_op__zero_a + connect \logical_op__zero_a$11 \output_logical_op__zero_a$34 + connect \muxid \output_muxid + connect \muxid$1 \output_muxid$24 + connect \o \output_o + connect \o$20 \output_o$43 + connect \o_ok \output_o_ok + connect \o_ok$21 \output_o_ok$44 + connect \xer_so \output_xer_so + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:132878.10-132881.4" + cell \p$49 \p + connect \p_ready_o \p_ready_o + connect \p_valid_i \p_valid_i + end + attribute \src "libresoc.v:131990.7-131990.20" + process $proc$libresoc.v:131990$6502 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:132001.13-132001.29" + process $proc$libresoc.v:132001$6503 + assign { } { } + assign $0\cr_a$22[3:0]$6504 4'0000 + sync always + sync init + update \cr_a$22 $0\cr_a$22[3:0]$6504 + end + attribute \src "libresoc.v:132010.7-132010.26" + process $proc$libresoc.v:132010$6505 + assign { } { } + assign $0\cr_a_ok$23[0:0]$6506 1'0 + sync always + sync init + update \cr_a_ok$23 $0\cr_a_ok$23[0:0]$6506 + end + attribute \src "libresoc.v:132021.13-132021.45" + process $proc$libresoc.v:132021$6507 + assign { } { } + assign $0\logical_op__data_len$18[3:0]$6508 4'0000 + sync always + sync init + update \logical_op__data_len$18 $0\logical_op__data_len$18[3:0]$6508 + end + attribute \src "libresoc.v:132056.14-132056.47" + process $proc$libresoc.v:132056$6509 + assign { } { } + assign $0\logical_op__fn_unit$3[11:0]$6510 12'000000000000 + sync always + sync init + update \logical_op__fn_unit$3 $0\logical_op__fn_unit$3[11:0]$6510 + end + attribute \src "libresoc.v:132078.14-132078.67" + process $proc$libresoc.v:132078$6511 + assign { } { } + assign $0\logical_op__imm_data__data$4[63:0]$6512 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \logical_op__imm_data__data$4 $0\logical_op__imm_data__data$4[63:0]$6512 + end + attribute \src "libresoc.v:132087.7-132087.42" + process $proc$libresoc.v:132087$6513 + assign { } { } + assign $0\logical_op__imm_data__ok$5[0:0]$6514 1'0 + sync always + sync init + update \logical_op__imm_data__ok$5 $0\logical_op__imm_data__ok$5[0:0]$6514 + end + attribute \src "libresoc.v:132104.13-132104.48" + process $proc$libresoc.v:132104$6515 + assign { } { } + assign $0\logical_op__input_carry$12[1:0]$6516 2'00 + sync always + sync init + update \logical_op__input_carry$12 $0\logical_op__input_carry$12[1:0]$6516 + end + attribute \src "libresoc.v:132117.14-132117.43" + process $proc$libresoc.v:132117$6517 + assign { } { } + assign $0\logical_op__insn$19[31:0]$6518 0 + sync always + sync init + update \logical_op__insn$19 $0\logical_op__insn$19[31:0]$6518 + end + attribute \src "libresoc.v:132274.13-132274.46" + process $proc$libresoc.v:132274$6519 + assign { } { } + assign $0\logical_op__insn_type$2[6:0]$6520 7'0000000 + sync always + sync init + update \logical_op__insn_type$2 $0\logical_op__insn_type$2[6:0]$6520 + end + attribute \src "libresoc.v:132357.7-132357.40" + process $proc$libresoc.v:132357$6521 + assign { } { } + assign $0\logical_op__invert_in$10[0:0]$6522 1'0 + sync always + sync init + update \logical_op__invert_in$10 $0\logical_op__invert_in$10[0:0]$6522 + end + attribute \src "libresoc.v:132366.7-132366.41" + process $proc$libresoc.v:132366$6523 + assign { } { } + assign $0\logical_op__invert_out$13[0:0]$6524 1'0 + sync always + sync init + update \logical_op__invert_out$13 $0\logical_op__invert_out$13[0:0]$6524 + end + attribute \src "libresoc.v:132375.7-132375.39" + process $proc$libresoc.v:132375$6525 + assign { } { } + assign $0\logical_op__is_32bit$16[0:0]$6526 1'0 + sync always + sync init + update \logical_op__is_32bit$16 $0\logical_op__is_32bit$16[0:0]$6526 + end + attribute \src "libresoc.v:132384.7-132384.40" + process $proc$libresoc.v:132384$6527 + assign { } { } + assign $0\logical_op__is_signed$17[0:0]$6528 1'0 + sync always + sync init + update \logical_op__is_signed$17 $0\logical_op__is_signed$17[0:0]$6528 + end + attribute \src "libresoc.v:132395.7-132395.36" + process $proc$libresoc.v:132395$6529 + assign { } { } + assign $0\logical_op__oe__oe$8[0:0]$6530 1'0 + sync always + sync init + update \logical_op__oe__oe$8 $0\logical_op__oe__oe$8[0:0]$6530 + end + attribute \src "libresoc.v:132404.7-132404.36" + process $proc$libresoc.v:132404$6531 + assign { } { } + assign $0\logical_op__oe__ok$9[0:0]$6532 1'0 + sync always + sync init + update \logical_op__oe__ok$9 $0\logical_op__oe__ok$9[0:0]$6532 + end + attribute \src "libresoc.v:132411.7-132411.43" + process $proc$libresoc.v:132411$6533 + assign { } { } + assign $0\logical_op__output_carry$15[0:0]$6534 1'0 + sync always + sync init + update \logical_op__output_carry$15 $0\logical_op__output_carry$15[0:0]$6534 + end + attribute \src "libresoc.v:132422.7-132422.36" + process $proc$libresoc.v:132422$6535 + assign { } { } + assign $0\logical_op__rc__ok$7[0:0]$6536 1'0 + sync always + sync init + update \logical_op__rc__ok$7 $0\logical_op__rc__ok$7[0:0]$6536 + end + attribute \src "libresoc.v:132431.7-132431.36" + process $proc$libresoc.v:132431$6537 + assign { } { } + assign $0\logical_op__rc__rc$6[0:0]$6538 1'0 + sync always + sync init + update \logical_op__rc__rc$6 $0\logical_op__rc__rc$6[0:0]$6538 + end + attribute \src "libresoc.v:132438.7-132438.40" + process $proc$libresoc.v:132438$6539 + assign { } { } + assign $0\logical_op__write_cr0$14[0:0]$6540 1'0 + sync always + sync init + update \logical_op__write_cr0$14 $0\logical_op__write_cr0$14[0:0]$6540 + end + attribute \src "libresoc.v:132447.7-132447.37" + process $proc$libresoc.v:132447$6541 + assign { } { } + assign $0\logical_op__zero_a$11[0:0]$6542 1'0 + sync always + sync init + update \logical_op__zero_a$11 $0\logical_op__zero_a$11[0:0]$6542 + end + attribute \src "libresoc.v:132456.13-132456.29" + process $proc$libresoc.v:132456$6543 + assign { } { } + assign $0\muxid$1[1:0]$6544 2'00 + sync always + sync init + update \muxid$1 $0\muxid$1[1:0]$6544 + end + attribute \src "libresoc.v:132471.14-132471.43" + process $proc$libresoc.v:132471$6545 + assign { } { } + assign $0\o$20[63:0]$6546 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \o$20 $0\o$20[63:0]$6546 + end + attribute \src "libresoc.v:132480.7-132480.23" + process $proc$libresoc.v:132480$6547 + assign { } { } + assign $0\o_ok$21[0:0]$6548 1'0 + sync always + sync init + update \o_ok$21 $0\o_ok$21[0:0]$6548 + end + attribute \src "libresoc.v:132768.7-132768.20" + process $proc$libresoc.v:132768$6549 + assign { } { } + assign $1\r_busy[0:0] 1'0 + sync always + sync init + update \r_busy $1\r_busy[0:0] + end + attribute \src "libresoc.v:132778.3-132779.33" + process $proc$libresoc.v:132778$6393 + assign { } { } + assign $0\cr_a$22[3:0]$6394 \cr_a$22$next + sync posedge \coresync_clk + update \cr_a$22 $0\cr_a$22[3:0]$6394 + end + attribute \src "libresoc.v:132780.3-132781.39" + process $proc$libresoc.v:132780$6395 + assign { } { } + assign $0\cr_a_ok$23[0:0]$6396 \cr_a_ok$23$next + sync posedge \coresync_clk + update \cr_a_ok$23 $0\cr_a_ok$23[0:0]$6396 + end + attribute \src "libresoc.v:132782.3-132783.27" + process $proc$libresoc.v:132782$6397 + assign { } { } + assign $0\o$20[63:0]$6398 \o$20$next + sync posedge \coresync_clk + update \o$20 $0\o$20[63:0]$6398 + end + attribute \src "libresoc.v:132784.3-132785.33" + process $proc$libresoc.v:132784$6399 + assign { } { } + assign $0\o_ok$21[0:0]$6400 \o_ok$21$next + sync posedge \coresync_clk + update \o_ok$21 $0\o_ok$21[0:0]$6400 + end + attribute \src "libresoc.v:132786.3-132787.65" + process $proc$libresoc.v:132786$6401 + assign { } { } + assign $0\logical_op__insn_type$2[6:0]$6402 \logical_op__insn_type$2$next + sync posedge \coresync_clk + update \logical_op__insn_type$2 $0\logical_op__insn_type$2[6:0]$6402 + end + attribute \src "libresoc.v:132788.3-132789.61" + process $proc$libresoc.v:132788$6403 + assign { } { } + assign $0\logical_op__fn_unit$3[11:0]$6404 \logical_op__fn_unit$3$next + sync posedge \coresync_clk + update \logical_op__fn_unit$3 $0\logical_op__fn_unit$3[11:0]$6404 + end + attribute \src "libresoc.v:132790.3-132791.75" + process $proc$libresoc.v:132790$6405 + assign { } { } + assign $0\logical_op__imm_data__data$4[63:0]$6406 \logical_op__imm_data__data$4$next + sync posedge \coresync_clk + update \logical_op__imm_data__data$4 $0\logical_op__imm_data__data$4[63:0]$6406 + end + attribute \src "libresoc.v:132792.3-132793.71" + process $proc$libresoc.v:132792$6407 + assign { } { } + assign $0\logical_op__imm_data__ok$5[0:0]$6408 \logical_op__imm_data__ok$5$next + sync posedge \coresync_clk + update \logical_op__imm_data__ok$5 $0\logical_op__imm_data__ok$5[0:0]$6408 + end + attribute \src "libresoc.v:132794.3-132795.59" + process $proc$libresoc.v:132794$6409 + assign { } { } + assign $0\logical_op__rc__rc$6[0:0]$6410 \logical_op__rc__rc$6$next + sync posedge \coresync_clk + update \logical_op__rc__rc$6 $0\logical_op__rc__rc$6[0:0]$6410 + end + attribute \src "libresoc.v:132796.3-132797.59" + process $proc$libresoc.v:132796$6411 + assign { } { } + assign $0\logical_op__rc__ok$7[0:0]$6412 \logical_op__rc__ok$7$next + sync posedge \coresync_clk + update \logical_op__rc__ok$7 $0\logical_op__rc__ok$7[0:0]$6412 + end + attribute \src "libresoc.v:132798.3-132799.59" + process $proc$libresoc.v:132798$6413 + assign { } { } + assign $0\logical_op__oe__oe$8[0:0]$6414 \logical_op__oe__oe$8$next + sync posedge \coresync_clk + update \logical_op__oe__oe$8 $0\logical_op__oe__oe$8[0:0]$6414 + end + attribute \src "libresoc.v:132800.3-132801.59" + process $proc$libresoc.v:132800$6415 + assign { } { } + assign $0\logical_op__oe__ok$9[0:0]$6416 \logical_op__oe__ok$9$next + sync posedge \coresync_clk + update \logical_op__oe__ok$9 $0\logical_op__oe__ok$9[0:0]$6416 + end + attribute \src "libresoc.v:132802.3-132803.67" + process $proc$libresoc.v:132802$6417 + assign { } { } + assign $0\logical_op__invert_in$10[0:0]$6418 \logical_op__invert_in$10$next + sync posedge \coresync_clk + update \logical_op__invert_in$10 $0\logical_op__invert_in$10[0:0]$6418 + end + attribute \src "libresoc.v:132804.3-132805.61" + process $proc$libresoc.v:132804$6419 + assign { } { } + assign $0\logical_op__zero_a$11[0:0]$6420 \logical_op__zero_a$11$next + sync posedge \coresync_clk + update \logical_op__zero_a$11 $0\logical_op__zero_a$11[0:0]$6420 + end + attribute \src "libresoc.v:132806.3-132807.71" + process $proc$libresoc.v:132806$6421 + assign { } { } + assign $0\logical_op__input_carry$12[1:0]$6422 \logical_op__input_carry$12$next + sync posedge \coresync_clk + update \logical_op__input_carry$12 $0\logical_op__input_carry$12[1:0]$6422 + end + attribute \src "libresoc.v:132808.3-132809.69" + process $proc$libresoc.v:132808$6423 + assign { } { } + assign $0\logical_op__invert_out$13[0:0]$6424 \logical_op__invert_out$13$next + sync posedge \coresync_clk + update \logical_op__invert_out$13 $0\logical_op__invert_out$13[0:0]$6424 + end + attribute \src "libresoc.v:132810.3-132811.67" + process $proc$libresoc.v:132810$6425 + assign { } { } + assign $0\logical_op__write_cr0$14[0:0]$6426 \logical_op__write_cr0$14$next + sync posedge \coresync_clk + update \logical_op__write_cr0$14 $0\logical_op__write_cr0$14[0:0]$6426 + end + attribute \src "libresoc.v:132812.3-132813.73" + process $proc$libresoc.v:132812$6427 + assign { } { } + assign $0\logical_op__output_carry$15[0:0]$6428 \logical_op__output_carry$15$next + sync posedge \coresync_clk + update \logical_op__output_carry$15 $0\logical_op__output_carry$15[0:0]$6428 + end + attribute \src "libresoc.v:132814.3-132815.65" + process $proc$libresoc.v:132814$6429 + assign { } { } + assign $0\logical_op__is_32bit$16[0:0]$6430 \logical_op__is_32bit$16$next + sync posedge \coresync_clk + update \logical_op__is_32bit$16 $0\logical_op__is_32bit$16[0:0]$6430 + end + attribute \src "libresoc.v:132816.3-132817.67" + process $proc$libresoc.v:132816$6431 + assign { } { } + assign $0\logical_op__is_signed$17[0:0]$6432 \logical_op__is_signed$17$next + sync posedge \coresync_clk + update \logical_op__is_signed$17 $0\logical_op__is_signed$17[0:0]$6432 + end + attribute \src "libresoc.v:132818.3-132819.65" + process $proc$libresoc.v:132818$6433 + assign { } { } + assign $0\logical_op__data_len$18[3:0]$6434 \logical_op__data_len$18$next + sync posedge \coresync_clk + update \logical_op__data_len$18 $0\logical_op__data_len$18[3:0]$6434 + end + attribute \src "libresoc.v:132820.3-132821.57" + process $proc$libresoc.v:132820$6435 + assign { } { } + assign $0\logical_op__insn$19[31:0]$6436 \logical_op__insn$19$next + sync posedge \coresync_clk + update \logical_op__insn$19 $0\logical_op__insn$19[31:0]$6436 + end + attribute \src "libresoc.v:132822.3-132823.33" + process $proc$libresoc.v:132822$6437 + assign { } { } + assign $0\muxid$1[1:0]$6438 \muxid$1$next + sync posedge \coresync_clk + update \muxid$1 $0\muxid$1[1:0]$6438 + end + attribute \src "libresoc.v:132824.3-132825.29" + process $proc$libresoc.v:132824$6439 + assign { } { } + assign $0\r_busy[0:0] \r_busy$next + sync posedge \coresync_clk + update \r_busy $0\r_busy[0:0] + end + attribute \src "libresoc.v:132882.3-132899.6" + process $proc$libresoc.v:132882$6440 + assign { } { } + assign { } { } + assign { } { } + assign $0\r_busy$next[0:0]$6441 $2\r_busy$next[0:0]$6443 + attribute \src "libresoc.v:132883.5-132883.29" + switch \initial + attribute \src "libresoc.v:132883.9-132883.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\r_busy$next[0:0]$6442 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\r_busy$next[0:0]$6442 1'0 + case + assign $1\r_busy$next[0:0]$6442 \r_busy + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r_busy$next[0:0]$6443 1'0 + case + assign $2\r_busy$next[0:0]$6443 $1\r_busy$next[0:0]$6442 + end + sync always + update \r_busy$next $0\r_busy$next[0:0]$6441 + end + attribute \src "libresoc.v:132900.3-132912.6" + process $proc$libresoc.v:132900$6444 + assign { } { } + assign { } { } + assign $0\muxid$1$next[1:0]$6445 $1\muxid$1$next[1:0]$6446 + attribute \src "libresoc.v:132901.5-132901.29" + switch \initial + attribute \src "libresoc.v:132901.9-132901.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\muxid$1$next[1:0]$6446 \muxid$51 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\muxid$1$next[1:0]$6446 \muxid$51 + case + assign $1\muxid$1$next[1:0]$6446 \muxid$1 + end + sync always + update \muxid$1$next $0\muxid$1$next[1:0]$6445 + end + attribute \src "libresoc.v:132913.3-132954.6" + process $proc$libresoc.v:132913$6447 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\logical_op__data_len$18$next[3:0]$6448 $1\logical_op__data_len$18$next[3:0]$6466 + assign $0\logical_op__fn_unit$3$next[11:0]$6449 $1\logical_op__fn_unit$3$next[11:0]$6467 + assign { } { } + assign { } { } + assign $0\logical_op__input_carry$12$next[1:0]$6452 $1\logical_op__input_carry$12$next[1:0]$6470 + assign $0\logical_op__insn$19$next[31:0]$6453 $1\logical_op__insn$19$next[31:0]$6471 + assign $0\logical_op__insn_type$2$next[6:0]$6454 $1\logical_op__insn_type$2$next[6:0]$6472 + assign $0\logical_op__invert_in$10$next[0:0]$6455 $1\logical_op__invert_in$10$next[0:0]$6473 + assign $0\logical_op__invert_out$13$next[0:0]$6456 $1\logical_op__invert_out$13$next[0:0]$6474 + assign $0\logical_op__is_32bit$16$next[0:0]$6457 $1\logical_op__is_32bit$16$next[0:0]$6475 + assign $0\logical_op__is_signed$17$next[0:0]$6458 $1\logical_op__is_signed$17$next[0:0]$6476 + assign { } { } + assign { } { } + assign $0\logical_op__output_carry$15$next[0:0]$6461 $1\logical_op__output_carry$15$next[0:0]$6479 + assign { } { } + assign { } { } + assign $0\logical_op__write_cr0$14$next[0:0]$6464 $1\logical_op__write_cr0$14$next[0:0]$6482 + assign $0\logical_op__zero_a$11$next[0:0]$6465 $1\logical_op__zero_a$11$next[0:0]$6483 + assign $0\logical_op__imm_data__data$4$next[63:0]$6450 $2\logical_op__imm_data__data$4$next[63:0]$6484 + assign $0\logical_op__imm_data__ok$5$next[0:0]$6451 $2\logical_op__imm_data__ok$5$next[0:0]$6485 + assign $0\logical_op__oe__oe$8$next[0:0]$6459 $2\logical_op__oe__oe$8$next[0:0]$6486 + assign $0\logical_op__oe__ok$9$next[0:0]$6460 $2\logical_op__oe__ok$9$next[0:0]$6487 + assign $0\logical_op__rc__ok$7$next[0:0]$6462 $2\logical_op__rc__ok$7$next[0:0]$6488 + assign $0\logical_op__rc__rc$6$next[0:0]$6463 $2\logical_op__rc__rc$6$next[0:0]$6489 + attribute \src "libresoc.v:132914.5-132914.29" + switch \initial + attribute \src "libresoc.v:132914.9-132914.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\logical_op__insn$19$next[31:0]$6471 $1\logical_op__data_len$18$next[3:0]$6466 $1\logical_op__is_signed$17$next[0:0]$6476 $1\logical_op__is_32bit$16$next[0:0]$6475 $1\logical_op__output_carry$15$next[0:0]$6479 $1\logical_op__write_cr0$14$next[0:0]$6482 $1\logical_op__invert_out$13$next[0:0]$6474 $1\logical_op__input_carry$12$next[1:0]$6470 $1\logical_op__zero_a$11$next[0:0]$6483 $1\logical_op__invert_in$10$next[0:0]$6473 $1\logical_op__oe__ok$9$next[0:0]$6478 $1\logical_op__oe__oe$8$next[0:0]$6477 $1\logical_op__rc__ok$7$next[0:0]$6480 $1\logical_op__rc__rc$6$next[0:0]$6481 $1\logical_op__imm_data__ok$5$next[0:0]$6469 $1\logical_op__imm_data__data$4$next[63:0]$6468 $1\logical_op__fn_unit$3$next[11:0]$6467 $1\logical_op__insn_type$2$next[6:0]$6472 } { \logical_op__insn$69 \logical_op__data_len$68 \logical_op__is_signed$67 \logical_op__is_32bit$66 \logical_op__output_carry$65 \logical_op__write_cr0$64 \logical_op__invert_out$63 \logical_op__input_carry$62 \logical_op__zero_a$61 \logical_op__invert_in$60 \logical_op__oe__ok$59 \logical_op__oe__oe$58 \logical_op__rc__ok$57 \logical_op__rc__rc$56 \logical_op__imm_data__ok$55 \logical_op__imm_data__data$54 \logical_op__fn_unit$53 \logical_op__insn_type$52 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\logical_op__insn$19$next[31:0]$6471 $1\logical_op__data_len$18$next[3:0]$6466 $1\logical_op__is_signed$17$next[0:0]$6476 $1\logical_op__is_32bit$16$next[0:0]$6475 $1\logical_op__output_carry$15$next[0:0]$6479 $1\logical_op__write_cr0$14$next[0:0]$6482 $1\logical_op__invert_out$13$next[0:0]$6474 $1\logical_op__input_carry$12$next[1:0]$6470 $1\logical_op__zero_a$11$next[0:0]$6483 $1\logical_op__invert_in$10$next[0:0]$6473 $1\logical_op__oe__ok$9$next[0:0]$6478 $1\logical_op__oe__oe$8$next[0:0]$6477 $1\logical_op__rc__ok$7$next[0:0]$6480 $1\logical_op__rc__rc$6$next[0:0]$6481 $1\logical_op__imm_data__ok$5$next[0:0]$6469 $1\logical_op__imm_data__data$4$next[63:0]$6468 $1\logical_op__fn_unit$3$next[11:0]$6467 $1\logical_op__insn_type$2$next[6:0]$6472 } { \logical_op__insn$69 \logical_op__data_len$68 \logical_op__is_signed$67 \logical_op__is_32bit$66 \logical_op__output_carry$65 \logical_op__write_cr0$64 \logical_op__invert_out$63 \logical_op__input_carry$62 \logical_op__zero_a$61 \logical_op__invert_in$60 \logical_op__oe__ok$59 \logical_op__oe__oe$58 \logical_op__rc__ok$57 \logical_op__rc__rc$56 \logical_op__imm_data__ok$55 \logical_op__imm_data__data$54 \logical_op__fn_unit$53 \logical_op__insn_type$52 } + case + assign $1\logical_op__data_len$18$next[3:0]$6466 \logical_op__data_len$18 + assign $1\logical_op__fn_unit$3$next[11:0]$6467 \logical_op__fn_unit$3 + assign $1\logical_op__imm_data__data$4$next[63:0]$6468 \logical_op__imm_data__data$4 + assign $1\logical_op__imm_data__ok$5$next[0:0]$6469 \logical_op__imm_data__ok$5 + assign $1\logical_op__input_carry$12$next[1:0]$6470 \logical_op__input_carry$12 + assign $1\logical_op__insn$19$next[31:0]$6471 \logical_op__insn$19 + assign $1\logical_op__insn_type$2$next[6:0]$6472 \logical_op__insn_type$2 + assign $1\logical_op__invert_in$10$next[0:0]$6473 \logical_op__invert_in$10 + assign $1\logical_op__invert_out$13$next[0:0]$6474 \logical_op__invert_out$13 + assign $1\logical_op__is_32bit$16$next[0:0]$6475 \logical_op__is_32bit$16 + assign $1\logical_op__is_signed$17$next[0:0]$6476 \logical_op__is_signed$17 + assign $1\logical_op__oe__oe$8$next[0:0]$6477 \logical_op__oe__oe$8 + assign $1\logical_op__oe__ok$9$next[0:0]$6478 \logical_op__oe__ok$9 + assign $1\logical_op__output_carry$15$next[0:0]$6479 \logical_op__output_carry$15 + assign $1\logical_op__rc__ok$7$next[0:0]$6480 \logical_op__rc__ok$7 + assign $1\logical_op__rc__rc$6$next[0:0]$6481 \logical_op__rc__rc$6 + assign $1\logical_op__write_cr0$14$next[0:0]$6482 \logical_op__write_cr0$14 + assign $1\logical_op__zero_a$11$next[0:0]$6483 \logical_op__zero_a$11 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $2\logical_op__imm_data__data$4$next[63:0]$6484 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\logical_op__imm_data__ok$5$next[0:0]$6485 1'0 + assign $2\logical_op__rc__rc$6$next[0:0]$6489 1'0 + assign $2\logical_op__rc__ok$7$next[0:0]$6488 1'0 + assign $2\logical_op__oe__oe$8$next[0:0]$6486 1'0 + assign $2\logical_op__oe__ok$9$next[0:0]$6487 1'0 + case + assign $2\logical_op__imm_data__data$4$next[63:0]$6484 $1\logical_op__imm_data__data$4$next[63:0]$6468 + assign $2\logical_op__imm_data__ok$5$next[0:0]$6485 $1\logical_op__imm_data__ok$5$next[0:0]$6469 + assign $2\logical_op__oe__oe$8$next[0:0]$6486 $1\logical_op__oe__oe$8$next[0:0]$6477 + assign $2\logical_op__oe__ok$9$next[0:0]$6487 $1\logical_op__oe__ok$9$next[0:0]$6478 + assign $2\logical_op__rc__ok$7$next[0:0]$6488 $1\logical_op__rc__ok$7$next[0:0]$6480 + assign $2\logical_op__rc__rc$6$next[0:0]$6489 $1\logical_op__rc__rc$6$next[0:0]$6481 + end + sync always + update \logical_op__data_len$18$next $0\logical_op__data_len$18$next[3:0]$6448 + update \logical_op__fn_unit$3$next $0\logical_op__fn_unit$3$next[11:0]$6449 + update \logical_op__imm_data__data$4$next $0\logical_op__imm_data__data$4$next[63:0]$6450 + update \logical_op__imm_data__ok$5$next $0\logical_op__imm_data__ok$5$next[0:0]$6451 + update \logical_op__input_carry$12$next $0\logical_op__input_carry$12$next[1:0]$6452 + update \logical_op__insn$19$next $0\logical_op__insn$19$next[31:0]$6453 + update \logical_op__insn_type$2$next $0\logical_op__insn_type$2$next[6:0]$6454 + update \logical_op__invert_in$10$next $0\logical_op__invert_in$10$next[0:0]$6455 + update \logical_op__invert_out$13$next $0\logical_op__invert_out$13$next[0:0]$6456 + update \logical_op__is_32bit$16$next $0\logical_op__is_32bit$16$next[0:0]$6457 + update \logical_op__is_signed$17$next $0\logical_op__is_signed$17$next[0:0]$6458 + update \logical_op__oe__oe$8$next $0\logical_op__oe__oe$8$next[0:0]$6459 + update \logical_op__oe__ok$9$next $0\logical_op__oe__ok$9$next[0:0]$6460 + update \logical_op__output_carry$15$next $0\logical_op__output_carry$15$next[0:0]$6461 + update \logical_op__rc__ok$7$next $0\logical_op__rc__ok$7$next[0:0]$6462 + update \logical_op__rc__rc$6$next $0\logical_op__rc__rc$6$next[0:0]$6463 + update \logical_op__write_cr0$14$next $0\logical_op__write_cr0$14$next[0:0]$6464 + update \logical_op__zero_a$11$next $0\logical_op__zero_a$11$next[0:0]$6465 + end + attribute \src "libresoc.v:132955.3-132973.6" + process $proc$libresoc.v:132955$6490 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\o$20$next[63:0]$6491 $1\o$20$next[63:0]$6493 + assign { } { } + assign $0\o_ok$21$next[0:0]$6492 $2\o_ok$21$next[0:0]$6495 + attribute \src "libresoc.v:132956.5-132956.29" + switch \initial + attribute \src "libresoc.v:132956.9-132956.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\o_ok$21$next[0:0]$6494 $1\o$20$next[63:0]$6493 } { \o_ok$71 \o$70 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\o_ok$21$next[0:0]$6494 $1\o$20$next[63:0]$6493 } { \o_ok$71 \o$70 } + case + assign $1\o$20$next[63:0]$6493 \o$20 + assign $1\o_ok$21$next[0:0]$6494 \o_ok$21 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\o_ok$21$next[0:0]$6495 1'0 + case + assign $2\o_ok$21$next[0:0]$6495 $1\o_ok$21$next[0:0]$6494 + end + sync always + update \o$20$next $0\o$20$next[63:0]$6491 + update \o_ok$21$next $0\o_ok$21$next[0:0]$6492 + end + attribute \src "libresoc.v:132974.3-132992.6" + process $proc$libresoc.v:132974$6496 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\cr_a$22$next[3:0]$6497 $1\cr_a$22$next[3:0]$6499 + assign { } { } + assign $0\cr_a_ok$23$next[0:0]$6498 $2\cr_a_ok$23$next[0:0]$6501 + attribute \src "libresoc.v:132975.5-132975.29" + switch \initial + attribute \src "libresoc.v:132975.9-132975.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\cr_a_ok$23$next[0:0]$6500 $1\cr_a$22$next[3:0]$6499 } { \cr_a_ok$73 \cr_a$72 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\cr_a_ok$23$next[0:0]$6500 $1\cr_a$22$next[3:0]$6499 } { \cr_a_ok$73 \cr_a$72 } + case + assign $1\cr_a$22$next[3:0]$6499 \cr_a$22 + assign $1\cr_a_ok$23$next[0:0]$6500 \cr_a_ok$23 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_a_ok$23$next[0:0]$6501 1'0 + case + assign $2\cr_a_ok$23$next[0:0]$6501 $1\cr_a_ok$23$next[0:0]$6500 + end + sync always + update \cr_a$22$next $0\cr_a$22$next[3:0]$6497 + update \cr_a_ok$23$next $0\cr_a_ok$23$next[0:0]$6498 + end + connect \$49 $and$libresoc.v:132777$6392_Y + connect \p_ready_o \n_i_rdy_data + connect \n_valid_o \r_busy + connect { \cr_a_ok$73 \cr_a$72 } { \output_cr_a_ok \output_cr_a$45 } + connect { \o_ok$71 \o$70 } { \output_o_ok$44 \output_o$43 } + connect { \logical_op__insn$69 \logical_op__data_len$68 \logical_op__is_signed$67 \logical_op__is_32bit$66 \logical_op__output_carry$65 \logical_op__write_cr0$64 \logical_op__invert_out$63 \logical_op__input_carry$62 \logical_op__zero_a$61 \logical_op__invert_in$60 \logical_op__oe__ok$59 \logical_op__oe__oe$58 \logical_op__rc__ok$57 \logical_op__rc__rc$56 \logical_op__imm_data__ok$55 \logical_op__imm_data__data$54 \logical_op__fn_unit$53 \logical_op__insn_type$52 } { \output_logical_op__insn$42 \output_logical_op__data_len$41 \output_logical_op__is_signed$40 \output_logical_op__is_32bit$39 \output_logical_op__output_carry$38 \output_logical_op__write_cr0$37 \output_logical_op__invert_out$36 \output_logical_op__input_carry$35 \output_logical_op__zero_a$34 \output_logical_op__invert_in$33 \output_logical_op__oe__ok$32 \output_logical_op__oe__oe$31 \output_logical_op__rc__ok$30 \output_logical_op__rc__rc$29 \output_logical_op__imm_data__ok$28 \output_logical_op__imm_data__data$27 \output_logical_op__fn_unit$26 \output_logical_op__insn_type$25 } + connect \muxid$51 \output_muxid$24 + connect \p_valid_i_p_ready_o \$49 + connect \n_i_rdy_data \n_ready_i + connect \p_valid_i$48 \p_valid_i + connect { \xer_so_ok$47 \output_xer_so } { \xer_so_ok \xer_so } + connect { \cr_a_ok$46 \output_cr_a } { \cr_a_ok \cr_a } + connect { \output_o_ok \output_o } { \o_ok \o } + connect { \output_logical_op__insn \output_logical_op__data_len \output_logical_op__is_signed \output_logical_op__is_32bit \output_logical_op__output_carry \output_logical_op__write_cr0 \output_logical_op__invert_out \output_logical_op__input_carry \output_logical_op__zero_a \output_logical_op__invert_in \output_logical_op__oe__ok \output_logical_op__oe__oe \output_logical_op__rc__ok \output_logical_op__rc__rc \output_logical_op__imm_data__ok \output_logical_op__imm_data__data \output_logical_op__fn_unit \output_logical_op__insn_type } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } + connect \output_muxid \muxid +end +attribute \src "ls180.v:4.1-10282.10" +attribute \cells_not_processed 1 +module \ls180 + attribute \src "ls180.v:9977.1-9987.4" + wire width 7 $0$memwr$\mem$ls180.v:9979$1_ADDR[6:0]$2683 + attribute \src "ls180.v:9977.1-9987.4" + wire width 32 $0$memwr$\mem$ls180.v:9979$1_DATA[31:0]$2684 + attribute \src "ls180.v:9977.1-9987.4" + wire width 32 $0$memwr$\mem$ls180.v:9979$1_EN[31:0]$2685 + attribute \src "ls180.v:9977.1-9987.4" + wire width 7 $0$memwr$\mem$ls180.v:9981$2_ADDR[6:0]$2686 + attribute \src "ls180.v:9977.1-9987.4" + wire width 32 $0$memwr$\mem$ls180.v:9981$2_DATA[31:0]$2687 + attribute \src "ls180.v:9977.1-9987.4" + wire width 32 $0$memwr$\mem$ls180.v:9981$2_EN[31:0]$2688 + attribute \src "ls180.v:9977.1-9987.4" + wire width 7 $0$memwr$\mem$ls180.v:9983$3_ADDR[6:0]$2689 + attribute \src "ls180.v:9977.1-9987.4" + wire width 32 $0$memwr$\mem$ls180.v:9983$3_DATA[31:0]$2690 + attribute \src "ls180.v:9977.1-9987.4" + wire width 32 $0$memwr$\mem$ls180.v:9983$3_EN[31:0]$2691 + attribute \src "ls180.v:9977.1-9987.4" + wire width 7 $0$memwr$\mem$ls180.v:9985$4_ADDR[6:0]$2692 + attribute \src "ls180.v:9977.1-9987.4" + wire width 32 $0$memwr$\mem$ls180.v:9985$4_DATA[31:0]$2693 + attribute \src "ls180.v:9977.1-9987.4" + wire width 32 $0$memwr$\mem$ls180.v:9985$4_EN[31:0]$2694 + attribute \src "ls180.v:9997.1-10001.4" + wire width 3 $0$memwr$\storage$ls180.v:9999$5_ADDR[2:0]$2697 + attribute \src "ls180.v:9997.1-10001.4" + wire width 25 $0$memwr$\storage$ls180.v:9999$5_DATA[24:0]$2698 + attribute \src "ls180.v:9997.1-10001.4" + wire width 25 $0$memwr$\storage$ls180.v:9999$5_EN[24:0]$2699 + attribute \src "ls180.v:10011.1-10015.4" + wire width 3 $0$memwr$\storage_1$ls180.v:10013$6_ADDR[2:0]$2704 + attribute \src "ls180.v:10011.1-10015.4" + wire width 25 $0$memwr$\storage_1$ls180.v:10013$6_DATA[24:0]$2705 + attribute \src "ls180.v:10011.1-10015.4" + wire width 25 $0$memwr$\storage_1$ls180.v:10013$6_EN[24:0]$2706 + attribute \src "ls180.v:10025.1-10029.4" + wire width 3 $0$memwr$\storage_2$ls180.v:10027$7_ADDR[2:0]$2711 + attribute \src "ls180.v:10025.1-10029.4" + wire width 25 $0$memwr$\storage_2$ls180.v:10027$7_DATA[24:0]$2712 + attribute \src "ls180.v:10025.1-10029.4" + wire width 25 $0$memwr$\storage_2$ls180.v:10027$7_EN[24:0]$2713 + attribute \src "ls180.v:10039.1-10043.4" + wire width 3 $0$memwr$\storage_3$ls180.v:10041$8_ADDR[2:0]$2718 + attribute \src "ls180.v:10039.1-10043.4" + wire width 25 $0$memwr$\storage_3$ls180.v:10041$8_DATA[24:0]$2719 + attribute \src "ls180.v:10039.1-10043.4" + wire width 25 $0$memwr$\storage_3$ls180.v:10041$8_EN[24:0]$2720 + attribute \src "ls180.v:10054.1-10058.4" + wire width 4 $0$memwr$\storage_4$ls180.v:10056$9_ADDR[3:0]$2725 + attribute \src "ls180.v:10054.1-10058.4" + wire width 10 $0$memwr$\storage_4$ls180.v:10056$9_DATA[9:0]$2726 + attribute \src "ls180.v:10054.1-10058.4" + wire width 10 $0$memwr$\storage_4$ls180.v:10056$9_EN[9:0]$2727 + attribute \src "ls180.v:10071.1-10075.4" + wire width 4 $0$memwr$\storage_5$ls180.v:10073$10_ADDR[3:0]$2732 + attribute \src "ls180.v:10071.1-10075.4" + wire width 10 $0$memwr$\storage_5$ls180.v:10073$10_DATA[9:0]$2733 + attribute \src "ls180.v:10071.1-10075.4" + wire width 10 $0$memwr$\storage_5$ls180.v:10073$10_EN[9:0]$2734 + attribute \src "ls180.v:10087.1-10091.4" + wire width 5 $0$memwr$\storage_6$ls180.v:10089$11_ADDR[4:0]$2739 + attribute \src "ls180.v:10087.1-10091.4" + wire width 10 $0$memwr$\storage_6$ls180.v:10089$11_DATA[9:0]$2740 + attribute \src "ls180.v:10087.1-10091.4" + wire width 10 $0$memwr$\storage_6$ls180.v:10089$11_EN[9:0]$2741 + attribute \src "ls180.v:10101.1-10105.4" + wire width 5 $0$memwr$\storage_7$ls180.v:10103$12_ADDR[4:0]$2746 + attribute \src "ls180.v:10101.1-10105.4" + wire width 10 $0$memwr$\storage_7$ls180.v:10103$12_DATA[9:0]$2747 + attribute \src "ls180.v:10101.1-10105.4" + wire width 10 $0$memwr$\storage_7$ls180.v:10103$12_EN[9:0]$2748 + attribute \src "ls180.v:3175.1-3268.4" + wire width 3 $0\builder_bankmachine0_next_state[2:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 3 $0\builder_bankmachine0_state[2:0] + attribute \src "ls180.v:3332.1-3425.4" + wire width 3 $0\builder_bankmachine1_next_state[2:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 3 $0\builder_bankmachine1_state[2:0] + attribute \src "ls180.v:3489.1-3582.4" + wire width 3 $0\builder_bankmachine2_next_state[2:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 3 $0\builder_bankmachine2_state[2:0] + attribute \src "ls180.v:3646.1-3739.4" + wire width 3 $0\builder_bankmachine3_next_state[2:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 3 $0\builder_bankmachine3_state[2:0] + attribute \src "ls180.v:6448.1-6464.4" + wire $0\builder_comb_rhs_array_muxed0[0:0] + attribute \src "ls180.v:6669.1-6685.4" + wire $0\builder_comb_rhs_array_muxed10[0:0] + attribute \src "ls180.v:6686.1-6702.4" + wire $0\builder_comb_rhs_array_muxed11[0:0] + attribute \src "ls180.v:6754.1-6761.4" + wire width 22 $0\builder_comb_rhs_array_muxed12[21:0] + attribute \src "ls180.v:6762.1-6769.4" + wire $0\builder_comb_rhs_array_muxed13[0:0] + attribute \src "ls180.v:6770.1-6777.4" + wire $0\builder_comb_rhs_array_muxed14[0:0] + attribute \src "ls180.v:6778.1-6785.4" + wire width 22 $0\builder_comb_rhs_array_muxed15[21:0] + attribute \src "ls180.v:6786.1-6793.4" + wire $0\builder_comb_rhs_array_muxed16[0:0] + attribute \src "ls180.v:6794.1-6801.4" + wire $0\builder_comb_rhs_array_muxed17[0:0] + attribute \src "ls180.v:6802.1-6809.4" + wire width 22 $0\builder_comb_rhs_array_muxed18[21:0] + attribute \src "ls180.v:6810.1-6817.4" + wire $0\builder_comb_rhs_array_muxed19[0:0] + attribute \src "ls180.v:6465.1-6481.4" + wire width 13 $0\builder_comb_rhs_array_muxed1[12:0] + attribute \src "ls180.v:6818.1-6825.4" + wire $0\builder_comb_rhs_array_muxed20[0:0] + attribute \src "ls180.v:6826.1-6833.4" + wire width 22 $0\builder_comb_rhs_array_muxed21[21:0] + attribute \src "ls180.v:6834.1-6841.4" + wire $0\builder_comb_rhs_array_muxed22[0:0] + attribute \src "ls180.v:6842.1-6849.4" + wire $0\builder_comb_rhs_array_muxed23[0:0] + attribute \src "ls180.v:6850.1-6869.4" + wire width 32 $0\builder_comb_rhs_array_muxed24[31:0] + attribute \src "ls180.v:6870.1-6889.4" + wire width 32 $0\builder_comb_rhs_array_muxed25[31:0] + attribute \src "ls180.v:6890.1-6909.4" + wire width 4 $0\builder_comb_rhs_array_muxed26[3:0] + attribute \src "ls180.v:6910.1-6929.4" + wire $0\builder_comb_rhs_array_muxed27[0:0] + attribute \src "ls180.v:6930.1-6949.4" + wire $0\builder_comb_rhs_array_muxed28[0:0] + attribute \src "ls180.v:6950.1-6969.4" + wire $0\builder_comb_rhs_array_muxed29[0:0] + attribute \src "ls180.v:6482.1-6498.4" + wire width 2 $0\builder_comb_rhs_array_muxed2[1:0] + attribute \src "ls180.v:6970.1-6989.4" + wire width 3 $0\builder_comb_rhs_array_muxed30[2:0] + attribute \src "ls180.v:6990.1-7009.4" + wire width 2 $0\builder_comb_rhs_array_muxed31[1:0] + attribute \src "ls180.v:6499.1-6515.4" + wire $0\builder_comb_rhs_array_muxed3[0:0] + attribute \src "ls180.v:6516.1-6532.4" + wire $0\builder_comb_rhs_array_muxed4[0:0] + attribute \src "ls180.v:6533.1-6549.4" + wire $0\builder_comb_rhs_array_muxed5[0:0] + attribute \src "ls180.v:6601.1-6617.4" + wire $0\builder_comb_rhs_array_muxed6[0:0] + attribute \src "ls180.v:6618.1-6634.4" + wire width 13 $0\builder_comb_rhs_array_muxed7[12:0] + attribute \src "ls180.v:6635.1-6651.4" + wire width 2 $0\builder_comb_rhs_array_muxed8[1:0] + attribute \src "ls180.v:6652.1-6668.4" + wire $0\builder_comb_rhs_array_muxed9[0:0] + attribute \src "ls180.v:6550.1-6566.4" + wire $0\builder_comb_t_array_muxed0[0:0] + attribute \src "ls180.v:6567.1-6583.4" + wire $0\builder_comb_t_array_muxed1[0:0] + attribute \src "ls180.v:6584.1-6600.4" + wire $0\builder_comb_t_array_muxed2[0:0] + attribute \src "ls180.v:6703.1-6719.4" + wire $0\builder_comb_t_array_muxed3[0:0] + attribute \src "ls180.v:6720.1-6736.4" + wire $0\builder_comb_t_array_muxed4[0:0] + attribute \src "ls180.v:6737.1-6753.4" + wire $0\builder_comb_t_array_muxed5[0:0] + attribute \src "ls180.v:2739.1-2785.4" + wire $0\builder_converter0_next_state[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\builder_converter0_state[0:0] + attribute \src "ls180.v:2799.1-2845.4" + wire $0\builder_converter1_next_state[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\builder_converter1_state[0:0] + attribute \src "ls180.v:2859.1-2905.4" + wire $0\builder_converter2_next_state[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\builder_converter2_state[0:0] + attribute \src "ls180.v:3992.1-4038.4" + wire $0\builder_converter_next_state[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\builder_converter_state[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 20 $0\builder_count[19:0] + attribute \src "ls180.v:5705.1-5716.4" + wire $0\builder_error[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 3 $0\builder_grant[2:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 8 $0\builder_interface0_bank_bus_dat_r[7:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 8 $0\builder_interface10_bank_bus_dat_r[7:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 8 $0\builder_interface11_bank_bus_dat_r[7:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 8 $0\builder_interface12_bank_bus_dat_r[7:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 8 $0\builder_interface13_bank_bus_dat_r[7:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 8 $0\builder_interface1_bank_bus_dat_r[7:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 8 $0\builder_interface2_bank_bus_dat_r[7:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 8 $0\builder_interface3_bank_bus_dat_r[7:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 8 $0\builder_interface4_bank_bus_dat_r[7:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 8 $0\builder_interface5_bank_bus_dat_r[7:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 8 $0\builder_interface6_bank_bus_dat_r[7:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 8 $0\builder_interface7_bank_bus_dat_r[7:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 8 $0\builder_interface8_bank_bus_dat_r[7:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 8 $0\builder_interface9_bank_bus_dat_r[7:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 14 $0\builder_libresocsim_adr[13:0] + attribute \src "ls180.v:5594.1-5630.4" + wire width 14 $0\builder_libresocsim_adr_next_value1[13:0] + attribute \src "ls180.v:5594.1-5630.4" + wire $0\builder_libresocsim_adr_next_value_ce1[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 8 $0\builder_libresocsim_dat_w[7:0] + attribute \src "ls180.v:5594.1-5630.4" + wire width 8 $0\builder_libresocsim_dat_w_next_value0[7:0] + attribute \src "ls180.v:5594.1-5630.4" + wire $0\builder_libresocsim_dat_w_next_value_ce0[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\builder_libresocsim_we[0:0] + attribute \src "ls180.v:5594.1-5630.4" + wire $0\builder_libresocsim_we_next_value2[0:0] + attribute \src "ls180.v:5594.1-5630.4" + wire $0\builder_libresocsim_we_next_value_ce2[0:0] + attribute \src "ls180.v:5594.1-5630.4" + wire $0\builder_libresocsim_wishbone_ack[0:0] + attribute \src "ls180.v:5594.1-5630.4" + wire width 32 $0\builder_libresocsim_wishbone_dat_r[31:0] + attribute \src "ls180.v:1841.5-1841.44" + wire $0\builder_libresocsim_wishbone_err[0:0] + attribute \src "ls180.v:1730.5-1730.27" + wire $0\builder_locked0[0:0] + attribute \src "ls180.v:1731.5-1731.27" + wire $0\builder_locked1[0:0] + attribute \src "ls180.v:1732.5-1732.27" + wire $0\builder_locked2[0:0] + attribute \src "ls180.v:1733.5-1733.27" + wire $0\builder_locked3[0:0] + attribute \src "ls180.v:3864.1-3936.4" + wire width 3 $0\builder_multiplexer_next_state[2:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 3 $0\builder_multiplexer_state[2:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\builder_multiregimpl0_regs0[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\builder_multiregimpl0_regs1[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\builder_multiregimpl10_regs0[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\builder_multiregimpl10_regs1[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\builder_multiregimpl11_regs0[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\builder_multiregimpl11_regs1[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\builder_multiregimpl12_regs0[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\builder_multiregimpl12_regs1[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\builder_multiregimpl13_regs0[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\builder_multiregimpl13_regs1[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\builder_multiregimpl14_regs0[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\builder_multiregimpl14_regs1[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\builder_multiregimpl15_regs0[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\builder_multiregimpl15_regs1[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\builder_multiregimpl16_regs0[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\builder_multiregimpl16_regs1[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\builder_multiregimpl1_regs0[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\builder_multiregimpl1_regs1[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\builder_multiregimpl2_regs0[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\builder_multiregimpl2_regs1[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\builder_multiregimpl3_regs0[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\builder_multiregimpl3_regs1[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\builder_multiregimpl4_regs0[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\builder_multiregimpl4_regs1[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\builder_multiregimpl5_regs0[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\builder_multiregimpl5_regs1[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\builder_multiregimpl6_regs0[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\builder_multiregimpl6_regs1[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\builder_multiregimpl7_regs0[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\builder_multiregimpl7_regs1[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\builder_multiregimpl8_regs0[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\builder_multiregimpl8_regs1[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\builder_multiregimpl9_regs0[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\builder_multiregimpl9_regs1[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\builder_new_master_rdata_valid0[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\builder_new_master_rdata_valid1[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\builder_new_master_rdata_valid2[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\builder_new_master_rdata_valid3[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\builder_new_master_wdata_ready[0:0] + attribute \src "ls180.v:5594.1-5630.4" + wire width 2 $0\builder_next_state[1:0] + attribute \src "ls180.v:3081.1-3111.4" + wire width 2 $0\builder_refresher_next_state[1:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 2 $0\builder_refresher_state[1:0] + attribute \src "ls180.v:5345.1-5384.4" + wire width 2 $0\builder_sdblock2memdma_next_state[1:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 2 $0\builder_sdblock2memdma_state[1:0] + attribute \src "ls180.v:4912.1-4991.4" + wire $0\builder_sdcore_crcupstreaminserter_next_state[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\builder_sdcore_crcupstreaminserter_state[0:0] + attribute \src "ls180.v:5094.1-5284.4" + wire width 3 $0\builder_sdcore_fsm_next_state[2:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 3 $0\builder_sdcore_fsm_state[2:0] + attribute \src "ls180.v:5404.1-5441.4" + wire $0\builder_sdmem2blockdma_fsm_next_state[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\builder_sdmem2blockdma_fsm_state[0:0] + attribute \src "ls180.v:5442.1-5478.4" + wire width 2 $0\builder_sdmem2blockdma_resetinserter_next_state[1:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 2 $0\builder_sdmem2blockdma_resetinserter_state[1:0] + attribute \src "ls180.v:4587.1-4659.4" + wire width 3 $0\builder_sdphy_fsm_next_state[2:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 3 $0\builder_sdphy_fsm_state[2:0] + attribute \src "ls180.v:4432.1-4525.4" + wire width 3 $0\builder_sdphy_sdphycmdr_next_state[2:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 3 $0\builder_sdphy_sdphycmdr_state[2:0] + attribute \src "ls180.v:4322.1-4398.4" + wire width 2 $0\builder_sdphy_sdphycmdw_next_state[1:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 2 $0\builder_sdphy_sdphycmdw_state[1:0] + attribute \src "ls180.v:4559.1-4586.4" + wire $0\builder_sdphy_sdphycrcr_next_state[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\builder_sdphy_sdphycrcr_state[0:0] + attribute \src "ls180.v:4693.1-4794.4" + wire width 3 $0\builder_sdphy_sdphydatar_next_state[2:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 3 $0\builder_sdphy_sdphydatar_state[2:0] + attribute \src "ls180.v:4288.1-4321.4" + wire $0\builder_sdphy_sdphyinit_next_state[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\builder_sdphy_sdphyinit_state[0:0] + attribute \src "ls180.v:5705.1-5716.4" + wire $0\builder_shared_ack[0:0] + attribute \src "ls180.v:5705.1-5716.4" + wire width 32 $0\builder_shared_dat_r[31:0] + attribute \src "ls180.v:5655.1-5662.4" + wire width 5 $0\builder_slave_sel[4:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 5 $0\builder_slave_sel_r[4:0] + attribute \src "ls180.v:4182.1-4230.4" + wire width 2 $0\builder_spimaster0_next_state[1:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 2 $0\builder_spimaster0_state[1:0] + attribute \src "ls180.v:5545.1-5593.4" + wire width 2 $0\builder_spimaster1_next_state[1:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 2 $0\builder_spimaster1_state[1:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 2 $0\builder_state[1:0] + attribute \src "ls180.v:7129.1-7157.4" + wire $0\builder_sync_f_array_muxed0[0:0] + attribute \src "ls180.v:7158.1-7186.4" + wire $0\builder_sync_f_array_muxed1[0:0] + attribute \src "ls180.v:7010.1-7026.4" + wire width 2 $0\builder_sync_rhs_array_muxed0[1:0] + attribute \src "ls180.v:7027.1-7043.4" + wire width 13 $0\builder_sync_rhs_array_muxed1[12:0] + attribute \src "ls180.v:7044.1-7060.4" + wire $0\builder_sync_rhs_array_muxed2[0:0] + attribute \src "ls180.v:7061.1-7077.4" + wire $0\builder_sync_rhs_array_muxed3[0:0] + attribute \src "ls180.v:7078.1-7094.4" + wire $0\builder_sync_rhs_array_muxed4[0:0] + attribute \src "ls180.v:7095.1-7111.4" + wire $0\builder_sync_rhs_array_muxed5[0:0] + attribute \src "ls180.v:7112.1-7128.4" + wire $0\builder_sync_rhs_array_muxed6[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 16 $0\libresocsim_clk_divider1[15:0] + attribute \src "ls180.v:5545.1-5593.4" + wire $0\libresocsim_clk_enable[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\libresocsim_control_re[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 16 $0\libresocsim_control_storage[15:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 3 $0\libresocsim_count[2:0] + attribute \src "ls180.v:5545.1-5593.4" + wire width 3 $0\libresocsim_count_spimaster1_next_value[2:0] + attribute \src "ls180.v:5545.1-5593.4" + wire $0\libresocsim_count_spimaster1_next_value_ce[0:0] + attribute \src "ls180.v:5545.1-5593.4" + wire $0\libresocsim_cs_enable[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\libresocsim_cs_re[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\libresocsim_cs_storage[0:0] + attribute \src "ls180.v:5545.1-5593.4" + wire $0\libresocsim_done0[0:0] + attribute \src "ls180.v:5545.1-5593.4" + wire $0\libresocsim_irq[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\libresocsim_loopback_re[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\libresocsim_loopback_storage[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 8 $0\libresocsim_miso[7:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 8 $0\libresocsim_miso_data[7:0] + attribute \src "ls180.v:5545.1-5593.4" + wire $0\libresocsim_miso_latch[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 8 $0\libresocsim_mosi_data[7:0] + attribute \src "ls180.v:5545.1-5593.4" + wire $0\libresocsim_mosi_latch[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\libresocsim_mosi_re[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 3 $0\libresocsim_mosi_sel[2:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 8 $0\libresocsim_mosi_storage[7:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\libresocsim_re[0:0] + attribute \src "ls180.v:6262.1-6267.4" + wire $0\libresocsim_start1[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 16 $0\libresocsim_storage[15:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_cmd_consumed[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_converter_counter[0:0] + attribute \src "ls180.v:3992.1-4038.4" + wire $0\main_converter_counter_converter_next_value[0:0] + attribute \src "ls180.v:3992.1-4038.4" + wire $0\main_converter_counter_converter_next_value_ce[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 32 $0\main_converter_dat_r[31:0] + attribute \src "ls180.v:3992.1-4038.4" + wire $0\main_converter_skip[0:0] + attribute \src "ls180.v:7287.1-7357.4" + wire width 16 $0\main_dfi_p0_rddata[15:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_dfi_p0_rddata_valid[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 42 $0\main_dummy[41:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_gpio_oe_re[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 16 $0\main_gpio_oe_storage[15:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_gpio_out_re[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 16 $0\main_gpio_out_storage[15:0] + attribute \src "ls180.v:7244.1-7262.4" + wire width 16 $0\main_gpio_status[15:0] + attribute \src "ls180.v:7283.1-7285.4" + wire $0\main_int_rst[0:0] + attribute \src "ls180.v:1480.11-1480.41" + wire width 2 $0\main_interface0_bus_bte[1:0] + attribute \src "ls180.v:1479.11-1479.41" + wire width 3 $0\main_interface0_bus_cti[2:0] + attribute \src "ls180.v:5404.1-5441.4" + wire width 32 $0\main_interface1_bus_adr[31:0] + attribute \src "ls180.v:1571.11-1571.41" + wire width 2 $0\main_interface1_bus_bte[1:0] + attribute \src "ls180.v:1570.11-1570.41" + wire width 3 $0\main_interface1_bus_cti[2:0] + attribute \src "ls180.v:5404.1-5441.4" + wire $0\main_interface1_bus_cyc[0:0] + attribute \src "ls180.v:1563.12-1563.45" + wire width 32 $0\main_interface1_bus_dat_w[31:0] + attribute \src "ls180.v:5404.1-5441.4" + wire width 4 $0\main_interface1_bus_sel[3:0] + attribute \src "ls180.v:5404.1-5441.4" + wire $0\main_interface1_bus_stb[0:0] + attribute \src "ls180.v:5404.1-5441.4" + wire $0\main_interface1_bus_we[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 32 $0\main_libresocsim_bus_errors[31:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_libresocsim_converter0_counter[0:0] + attribute \src "ls180.v:2739.1-2785.4" + wire $0\main_libresocsim_converter0_counter_converter0_next_value[0:0] + attribute \src "ls180.v:2739.1-2785.4" + wire $0\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 64 $0\main_libresocsim_converter0_dat_r[63:0] + attribute \src "ls180.v:2739.1-2785.4" + wire $0\main_libresocsim_converter0_skip[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_libresocsim_converter1_counter[0:0] + attribute \src "ls180.v:2799.1-2845.4" + wire $0\main_libresocsim_converter1_counter_converter1_next_value[0:0] + attribute \src "ls180.v:2799.1-2845.4" + wire $0\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 64 $0\main_libresocsim_converter1_dat_r[63:0] + attribute \src "ls180.v:2799.1-2845.4" + wire $0\main_libresocsim_converter1_skip[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_libresocsim_converter2_counter[0:0] + attribute \src "ls180.v:2859.1-2905.4" + wire $0\main_libresocsim_converter2_counter_converter2_next_value[0:0] + attribute \src "ls180.v:2859.1-2905.4" + wire $0\main_libresocsim_converter2_counter_converter2_next_value_ce[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 64 $0\main_libresocsim_converter2_dat_r[63:0] + attribute \src "ls180.v:2859.1-2905.4" + wire $0\main_libresocsim_converter2_skip[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_libresocsim_en_re[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_libresocsim_en_storage[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_libresocsim_eventmanager_re[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_libresocsim_eventmanager_storage[0:0] + attribute \src "ls180.v:2739.1-2785.4" + wire width 30 $0\main_libresocsim_interface0_converted_interface_adr[29:0] + attribute \src "ls180.v:139.11-139.69" + wire width 2 $0\main_libresocsim_interface0_converted_interface_bte[1:0] + attribute \src "ls180.v:138.11-138.69" + wire width 3 $0\main_libresocsim_interface0_converted_interface_cti[2:0] + attribute \src "ls180.v:2739.1-2785.4" + wire $0\main_libresocsim_interface0_converted_interface_cyc[0:0] + attribute \src "ls180.v:2727.1-2737.4" + wire width 32 $0\main_libresocsim_interface0_converted_interface_dat_w[31:0] + attribute \src "ls180.v:2739.1-2785.4" + wire width 4 $0\main_libresocsim_interface0_converted_interface_sel[3:0] + attribute \src "ls180.v:2739.1-2785.4" + wire $0\main_libresocsim_interface0_converted_interface_stb[0:0] + attribute \src "ls180.v:2739.1-2785.4" + wire $0\main_libresocsim_interface0_converted_interface_we[0:0] + attribute \src "ls180.v:2799.1-2845.4" + wire width 30 $0\main_libresocsim_interface1_converted_interface_adr[29:0] + attribute \src "ls180.v:154.11-154.69" + wire width 2 $0\main_libresocsim_interface1_converted_interface_bte[1:0] + attribute \src "ls180.v:153.11-153.69" + wire width 3 $0\main_libresocsim_interface1_converted_interface_cti[2:0] + attribute \src "ls180.v:2799.1-2845.4" + wire $0\main_libresocsim_interface1_converted_interface_cyc[0:0] + attribute \src "ls180.v:2787.1-2797.4" + wire width 32 $0\main_libresocsim_interface1_converted_interface_dat_w[31:0] + attribute \src "ls180.v:2799.1-2845.4" + wire width 4 $0\main_libresocsim_interface1_converted_interface_sel[3:0] + attribute \src "ls180.v:2799.1-2845.4" + wire $0\main_libresocsim_interface1_converted_interface_stb[0:0] + attribute \src "ls180.v:2799.1-2845.4" + wire $0\main_libresocsim_interface1_converted_interface_we[0:0] + attribute \src "ls180.v:2859.1-2905.4" + wire width 30 $0\main_libresocsim_interface2_converted_interface_adr[29:0] + attribute \src "ls180.v:169.11-169.69" + wire width 2 $0\main_libresocsim_interface2_converted_interface_bte[1:0] + attribute \src "ls180.v:168.11-168.69" + wire width 3 $0\main_libresocsim_interface2_converted_interface_cti[2:0] + attribute \src "ls180.v:2859.1-2905.4" + wire $0\main_libresocsim_interface2_converted_interface_cyc[0:0] + attribute \src "ls180.v:2847.1-2857.4" + wire width 32 $0\main_libresocsim_interface2_converted_interface_dat_w[31:0] + attribute \src "ls180.v:2859.1-2905.4" + wire width 4 $0\main_libresocsim_interface2_converted_interface_sel[3:0] + attribute \src "ls180.v:2859.1-2905.4" + wire $0\main_libresocsim_interface2_converted_interface_stb[0:0] + attribute \src "ls180.v:2859.1-2905.4" + wire $0\main_libresocsim_interface2_converted_interface_we[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_libresocsim_libresoc_constraintmanager0_uart0_tx[0:0] + attribute \src "ls180.v:2799.1-2845.4" + wire $0\main_libresocsim_libresoc_dbus_ack[0:0] + attribute \src "ls180.v:70.5-70.46" + wire $0\main_libresocsim_libresoc_dbus_err[0:0] + attribute \src "ls180.v:2739.1-2785.4" + wire $0\main_libresocsim_libresoc_ibus_ack[0:0] + attribute \src "ls180.v:81.5-81.46" + wire $0\main_libresocsim_libresoc_ibus_err[0:0] + attribute \src "ls180.v:2720.1-2725.4" + wire width 16 $0\main_libresocsim_libresoc_interrupt[15:0] + attribute \src "ls180.v:2859.1-2905.4" + wire $0\main_libresocsim_libresoc_jtag_wb_ack[0:0] + attribute \src "ls180.v:112.5-112.49" + wire $0\main_libresocsim_libresoc_jtag_wb_err[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_libresocsim_load_re[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 32 $0\main_libresocsim_load_storage[31:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_libresocsim_ram_bus_ack[0:0] + attribute \src "ls180.v:185.5-185.40" + wire $0\main_libresocsim_ram_bus_err[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_libresocsim_reload_re[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 32 $0\main_libresocsim_reload_storage[31:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_libresocsim_reset_re[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_libresocsim_reset_storage[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_libresocsim_scratch_re[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 32 $0\main_libresocsim_scratch_storage[31:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_libresocsim_update_value_re[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_libresocsim_update_value_storage[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 32 $0\main_libresocsim_value[31:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 32 $0\main_libresocsim_value_status[31:0] + attribute \src "ls180.v:2908.1-2914.4" + wire width 4 $0\main_libresocsim_we[3:0] + attribute \src "ls180.v:2920.1-2925.4" + wire $0\main_libresocsim_zero_clear[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_libresocsim_zero_old_trigger[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_libresocsim_zero_pending[0:0] + attribute \src "ls180.v:3992.1-4038.4" + wire width 30 $0\main_litedram_wb_adr[29:0] + attribute \src "ls180.v:3992.1-4038.4" + wire $0\main_litedram_wb_cyc[0:0] + attribute \src "ls180.v:3980.1-3990.4" + wire width 16 $0\main_litedram_wb_dat_w[15:0] + attribute \src "ls180.v:3992.1-4038.4" + wire width 2 $0\main_litedram_wb_sel[1:0] + attribute \src "ls180.v:3992.1-4038.4" + wire $0\main_litedram_wb_stb[0:0] + attribute \src "ls180.v:3992.1-4038.4" + wire $0\main_litedram_wb_we[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 32 $0\main_phase_accumulator_rx[31:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 32 $0\main_phase_accumulator_tx[31:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 32 $0\main_pwm0_counter[31:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_pwm0_enable_re[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_pwm0_enable_storage[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_pwm0_period_re[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 32 $0\main_pwm0_period_storage[31:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_pwm0_width_re[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 32 $0\main_pwm0_width_storage[31:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 32 $0\main_pwm1_counter[31:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_pwm1_enable_re[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_pwm1_enable_storage[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_pwm1_period_re[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 32 $0\main_pwm1_period_storage[31:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_pwm1_width_re[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 32 $0\main_pwm1_width_storage[31:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 3 $0\main_rddata_en[2:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_re[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 4 $0\main_rx_bitcount[3:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_rx_busy[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_rx_r[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 8 $0\main_rx_reg[7:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 2 $0\main_sdblock2mem_converter_demux[1:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_sdblock2mem_converter_source_first[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_sdblock2mem_converter_source_last[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 32 $0\main_sdblock2mem_converter_source_payload_data[31:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 3 $0\main_sdblock2mem_converter_source_payload_valid_token_count[2:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_sdblock2mem_converter_strobe_all[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 5 $0\main_sdblock2mem_fifo_consume[4:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 6 $0\main_sdblock2mem_fifo_level[5:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 5 $0\main_sdblock2mem_fifo_produce[4:0] + attribute \src "ls180.v:1504.5-1504.41" + wire $0\main_sdblock2mem_fifo_replace[0:0] + attribute \src "ls180.v:5312.1-5319.4" + wire width 5 $0\main_sdblock2mem_fifo_wrport_adr[4:0] + attribute \src "ls180.v:5345.1-5384.4" + wire width 32 $0\main_sdblock2mem_sink_sink_payload_address[31:0] + attribute \src "ls180.v:5345.1-5384.4" + wire width 32 $0\main_sdblock2mem_sink_sink_payload_data1[31:0] + attribute \src "ls180.v:5345.1-5384.4" + wire $0\main_sdblock2mem_sink_sink_valid1[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_sdblock2mem_wishbonedmawriter_base_re[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 64 $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_sdblock2mem_wishbonedmawriter_enable_re[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_sdblock2mem_wishbonedmawriter_length_re[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 32 $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 32 $0\main_sdblock2mem_wishbonedmawriter_offset[31:0] + attribute \src "ls180.v:5345.1-5384.4" + wire width 32 $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] + attribute \src "ls180.v:5345.1-5384.4" + wire $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] + attribute \src "ls180.v:5345.1-5384.4" + wire $0\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] + attribute \src "ls180.v:5345.1-5384.4" + wire $0\main_sdblock2mem_wishbonedmawriter_status[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_sdcore_block_count_re[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 32 $0\main_sdcore_block_count_storage[31:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_sdcore_block_length_re[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 10 $0\main_sdcore_block_length_storage[9:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_sdcore_cmd_argument_re[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 32 $0\main_sdcore_cmd_argument_storage[31:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_sdcore_cmd_command_re[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 32 $0\main_sdcore_cmd_command_storage[31:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 3 $0\main_sdcore_cmd_count[2:0] + attribute \src "ls180.v:5094.1-5284.4" + wire width 3 $0\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] + attribute \src "ls180.v:5094.1-5284.4" + wire $0\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_sdcore_cmd_done[0:0] + attribute \src "ls180.v:5094.1-5284.4" + wire $0\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] + attribute \src "ls180.v:5094.1-5284.4" + wire $0\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_sdcore_cmd_error[0:0] + attribute \src "ls180.v:5094.1-5284.4" + wire $0\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] + attribute \src "ls180.v:5094.1-5284.4" + wire $0\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 128 $0\main_sdcore_cmd_response_status[127:0] + attribute \src "ls180.v:5094.1-5284.4" + wire width 128 $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] + attribute \src "ls180.v:5094.1-5284.4" + wire $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] + attribute \src "ls180.v:1313.5-1313.34" + wire $0\main_sdcore_cmd_send_w[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_sdcore_cmd_timeout[0:0] + attribute \src "ls180.v:5094.1-5284.4" + wire $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] + attribute \src "ls180.v:5094.1-5284.4" + wire $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 4 $0\main_sdcore_crc16_checker_cnt[3:0] + attribute \src "ls180.v:5000.1-5007.4" + wire $0\main_sdcore_crc16_checker_crc0_clr[0:0] + attribute \src "ls180.v:5056.1-5063.4" + wire width 16 $0\main_sdcore_crc16_checker_crc0_crc[15:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 16 $0\main_sdcore_crc16_checker_crc0_crcreg0[15:0] + attribute \src "ls180.v:5010.1-5017.4" + wire $0\main_sdcore_crc16_checker_crc1_clr[0:0] + attribute \src "ls180.v:5066.1-5073.4" + wire width 16 $0\main_sdcore_crc16_checker_crc1_crc[15:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 16 $0\main_sdcore_crc16_checker_crc1_crcreg0[15:0] + attribute \src "ls180.v:5020.1-5027.4" + wire $0\main_sdcore_crc16_checker_crc2_clr[0:0] + attribute \src "ls180.v:5076.1-5083.4" + wire width 16 $0\main_sdcore_crc16_checker_crc2_crc[15:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 16 $0\main_sdcore_crc16_checker_crc2_crcreg0[15:0] + attribute \src "ls180.v:5030.1-5037.4" + wire $0\main_sdcore_crc16_checker_crc3_clr[0:0] + attribute \src "ls180.v:5086.1-5093.4" + wire width 16 $0\main_sdcore_crc16_checker_crc3_crc[15:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 16 $0\main_sdcore_crc16_checker_crc3_crcreg0[15:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 16 $0\main_sdcore_crc16_checker_crctmp0[15:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 16 $0\main_sdcore_crc16_checker_crctmp1[15:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 16 $0\main_sdcore_crc16_checker_crctmp2[15:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 16 $0\main_sdcore_crc16_checker_crctmp3[15:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 16 $0\main_sdcore_crc16_checker_fifo0[15:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 16 $0\main_sdcore_crc16_checker_fifo1[15:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 16 $0\main_sdcore_crc16_checker_fifo2[15:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 16 $0\main_sdcore_crc16_checker_fifo3[15:0] + attribute \src "ls180.v:5094.1-5284.4" + wire $0\main_sdcore_crc16_checker_sink_first[0:0] + attribute \src "ls180.v:5094.1-5284.4" + wire $0\main_sdcore_crc16_checker_sink_last[0:0] + attribute \src "ls180.v:5094.1-5284.4" + wire width 8 $0\main_sdcore_crc16_checker_sink_payload_data[7:0] + attribute \src "ls180.v:5045.1-5052.4" + wire $0\main_sdcore_crc16_checker_sink_ready[0:0] + attribute \src "ls180.v:5094.1-5284.4" + wire $0\main_sdcore_crc16_checker_sink_valid[0:0] + attribute \src "ls180.v:1419.5-1419.50" + wire $0\main_sdcore_crc16_checker_source_first[0:0] + attribute \src "ls180.v:5039.1-5044.4" + wire $0\main_sdcore_crc16_checker_source_valid[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 8 $0\main_sdcore_crc16_checker_val[7:0] + attribute \src "ls180.v:4992.1-4997.4" + wire $0\main_sdcore_crc16_checker_valid[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 3 $0\main_sdcore_crc16_inserter_cnt[2:0] + attribute \src "ls180.v:4912.1-4991.4" + wire width 3 $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] + attribute \src "ls180.v:4912.1-4991.4" + wire $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] + attribute \src "ls180.v:4874.1-4881.4" + wire width 16 $0\main_sdcore_crc16_inserter_crc0_crc[15:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 16 $0\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] + attribute \src "ls180.v:4884.1-4891.4" + wire width 16 $0\main_sdcore_crc16_inserter_crc1_crc[15:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 16 $0\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] + attribute \src "ls180.v:4894.1-4901.4" + wire width 16 $0\main_sdcore_crc16_inserter_crc2_crc[15:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 16 $0\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] + attribute \src "ls180.v:4904.1-4911.4" + wire width 16 $0\main_sdcore_crc16_inserter_crc3_crc[15:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 16 $0\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 16 $0\main_sdcore_crc16_inserter_crctmp0[15:0] + attribute \src "ls180.v:4912.1-4991.4" + wire width 16 $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] + attribute \src "ls180.v:4912.1-4991.4" + wire $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 16 $0\main_sdcore_crc16_inserter_crctmp1[15:0] + attribute \src "ls180.v:4912.1-4991.4" + wire width 16 $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] + attribute \src "ls180.v:4912.1-4991.4" + wire $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 16 $0\main_sdcore_crc16_inserter_crctmp2[15:0] + attribute \src "ls180.v:4912.1-4991.4" + wire width 16 $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] + attribute \src "ls180.v:4912.1-4991.4" + wire $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 16 $0\main_sdcore_crc16_inserter_crctmp3[15:0] + attribute \src "ls180.v:4912.1-4991.4" + wire width 16 $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] + attribute \src "ls180.v:4912.1-4991.4" + wire $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] + attribute \src "ls180.v:4912.1-4991.4" + wire $0\main_sdcore_crc16_inserter_sink_ready[0:0] + attribute \src "ls180.v:1376.5-1376.51" + wire $0\main_sdcore_crc16_inserter_source_first[0:0] + attribute \src "ls180.v:4912.1-4991.4" + wire $0\main_sdcore_crc16_inserter_source_last[0:0] + attribute \src "ls180.v:4912.1-4991.4" + wire width 8 $0\main_sdcore_crc16_inserter_source_payload_data[7:0] + attribute \src "ls180.v:5094.1-5284.4" + wire $0\main_sdcore_crc16_inserter_source_ready[0:0] + attribute \src "ls180.v:4912.1-4991.4" + wire $0\main_sdcore_crc16_inserter_source_valid[0:0] + attribute \src "ls180.v:4852.1-4859.4" + wire width 7 $0\main_sdcore_crc7_inserter_crc[6:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 7 $0\main_sdcore_crc7_inserter_crcreg0[6:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 32 $0\main_sdcore_data_count[31:0] + attribute \src "ls180.v:5094.1-5284.4" + wire width 32 $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] + attribute \src "ls180.v:5094.1-5284.4" + wire $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_sdcore_data_done[0:0] + attribute \src "ls180.v:5094.1-5284.4" + wire $0\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] + attribute \src "ls180.v:5094.1-5284.4" + wire $0\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_sdcore_data_error[0:0] + attribute \src "ls180.v:5094.1-5284.4" + wire $0\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] + attribute \src "ls180.v:5094.1-5284.4" + wire $0\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_sdcore_data_timeout[0:0] + attribute \src "ls180.v:5094.1-5284.4" + wire $0\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] + attribute \src "ls180.v:5094.1-5284.4" + wire $0\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 2 $0\main_sdmem2block_converter_mux[1:0] + attribute \src "ls180.v:5490.1-5506.4" + wire width 8 $0\main_sdmem2block_converter_source_payload_data[7:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_sdmem2block_dma_base_re[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 64 $0\main_sdmem2block_dma_base_storage[63:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 32 $0\main_sdmem2block_dma_data[31:0] + attribute \src "ls180.v:5404.1-5441.4" + wire width 32 $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[31:0] + attribute \src "ls180.v:5404.1-5441.4" + wire $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] + attribute \src "ls180.v:5442.1-5478.4" + wire $0\main_sdmem2block_dma_done_status[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_sdmem2block_dma_enable_re[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_sdmem2block_dma_enable_storage[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_sdmem2block_dma_length_re[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 32 $0\main_sdmem2block_dma_length_storage[31:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_sdmem2block_dma_loop_re[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_sdmem2block_dma_loop_storage[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 32 $0\main_sdmem2block_dma_offset[31:0] + attribute \src "ls180.v:5442.1-5478.4" + wire width 32 $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] + attribute \src "ls180.v:5442.1-5478.4" + wire $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] + attribute \src "ls180.v:5442.1-5478.4" + wire $0\main_sdmem2block_dma_sink_last[0:0] + attribute \src "ls180.v:5442.1-5478.4" + wire width 32 $0\main_sdmem2block_dma_sink_payload_address[31:0] + attribute \src "ls180.v:5404.1-5441.4" + wire $0\main_sdmem2block_dma_sink_ready[0:0] + attribute \src "ls180.v:5442.1-5478.4" + wire $0\main_sdmem2block_dma_sink_valid[0:0] + attribute \src "ls180.v:1584.5-1584.45" + wire $0\main_sdmem2block_dma_source_first[0:0] + attribute \src "ls180.v:5404.1-5441.4" + wire $0\main_sdmem2block_dma_source_last[0:0] + attribute \src "ls180.v:5404.1-5441.4" + wire width 32 $0\main_sdmem2block_dma_source_payload_data[31:0] + attribute \src "ls180.v:5404.1-5441.4" + wire $0\main_sdmem2block_dma_source_valid[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 5 $0\main_sdmem2block_fifo_consume[4:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 6 $0\main_sdmem2block_fifo_level[5:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 5 $0\main_sdmem2block_fifo_produce[4:0] + attribute \src "ls180.v:1640.5-1640.41" + wire $0\main_sdmem2block_fifo_replace[0:0] + attribute \src "ls180.v:5520.1-5527.4" + wire width 5 $0\main_sdmem2block_fifo_wrport_adr[4:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_sdphy_clocker_clk0[0:0] + attribute \src "ls180.v:4258.1-4286.4" + wire $0\main_sdphy_clocker_clk1[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_sdphy_clocker_clk_d[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 9 $0\main_sdphy_clocker_clks[8:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_sdphy_clocker_re[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 9 $0\main_sdphy_clocker_storage[8:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_sdphy_cmdr_cmdr_buf_source_first[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_sdphy_cmdr_cmdr_buf_source_last[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 8 $0\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 3 $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] + attribute \src "ls180.v:1105.5-1105.53" + wire $0\main_sdphy_cmdr_cmdr_converter_sink_first[0:0] + attribute \src "ls180.v:1106.5-1106.52" + wire $0\main_sdphy_cmdr_cmdr_converter_sink_last[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 8 $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 4 $0\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] + attribute \src "ls180.v:1086.5-1086.46" + wire $0\main_sdphy_cmdr_cmdr_pads_in_ready[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_sdphy_cmdr_cmdr_reset[0:0] + attribute \src "ls180.v:4432.1-4525.4" + wire $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] + attribute \src "ls180.v:4432.1-4525.4" + wire $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_sdphy_cmdr_cmdr_run[0:0] + attribute \src "ls180.v:4432.1-4525.4" + wire $0\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 8 $0\main_sdphy_cmdr_count[7:0] + attribute \src "ls180.v:4432.1-4525.4" + wire width 8 $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] + attribute \src "ls180.v:4432.1-4525.4" + wire $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] + attribute \src "ls180.v:1059.5-1059.49" + wire $0\main_sdphy_cmdr_pads_in_pads_in_first[0:0] + attribute \src "ls180.v:1060.5-1060.48" + wire $0\main_sdphy_cmdr_pads_in_pads_in_last[0:0] + attribute \src "ls180.v:1061.5-1061.55" + wire $0\main_sdphy_cmdr_pads_in_pads_in_payload_clk[0:0] + attribute \src "ls180.v:1063.5-1063.57" + wire $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_o[0:0] + attribute \src "ls180.v:1064.5-1064.58" + wire $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_oe[0:0] + attribute \src "ls180.v:1066.11-1066.64" + wire width 4 $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_o[3:0] + attribute \src "ls180.v:1067.5-1067.59" + wire $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_oe[0:0] + attribute \src "ls180.v:4432.1-4525.4" + wire $0\main_sdphy_cmdr_pads_out_payload_clk[0:0] + attribute \src "ls180.v:4432.1-4525.4" + wire $0\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] + attribute \src "ls180.v:4432.1-4525.4" + wire $0\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] + attribute \src "ls180.v:1072.11-1072.57" + wire width 4 $0\main_sdphy_cmdr_pads_out_payload_data_o[3:0] + attribute \src "ls180.v:1073.5-1073.52" + wire $0\main_sdphy_cmdr_pads_out_payload_data_oe[0:0] + attribute \src "ls180.v:5094.1-5284.4" + wire $0\main_sdphy_cmdr_sink_last[0:0] + attribute \src "ls180.v:5094.1-5284.4" + wire width 8 $0\main_sdphy_cmdr_sink_payload_length[7:0] + attribute \src "ls180.v:4432.1-4525.4" + wire $0\main_sdphy_cmdr_sink_ready[0:0] + attribute \src "ls180.v:5094.1-5284.4" + wire $0\main_sdphy_cmdr_sink_valid[0:0] + attribute \src "ls180.v:4432.1-4525.4" + wire $0\main_sdphy_cmdr_source_last[0:0] + attribute \src "ls180.v:4432.1-4525.4" + wire width 8 $0\main_sdphy_cmdr_source_payload_data[7:0] + attribute \src "ls180.v:4432.1-4525.4" + wire width 3 $0\main_sdphy_cmdr_source_payload_status[2:0] + attribute \src "ls180.v:5094.1-5284.4" + wire $0\main_sdphy_cmdr_source_ready[0:0] + attribute \src "ls180.v:4432.1-4525.4" + wire $0\main_sdphy_cmdr_source_valid[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 32 $0\main_sdphy_cmdr_timeout[31:0] + attribute \src "ls180.v:4432.1-4525.4" + wire width 32 $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] + attribute \src "ls180.v:4432.1-4525.4" + wire $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 8 $0\main_sdphy_cmdw_count[7:0] + attribute \src "ls180.v:4322.1-4398.4" + wire width 8 $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] + attribute \src "ls180.v:4322.1-4398.4" + wire $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] + attribute \src "ls180.v:4322.1-4398.4" + wire $0\main_sdphy_cmdw_done[0:0] + attribute \src "ls180.v:4322.1-4398.4" + wire $0\main_sdphy_cmdw_pads_out_payload_clk[0:0] + attribute \src "ls180.v:4322.1-4398.4" + wire $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] + attribute \src "ls180.v:4322.1-4398.4" + wire $0\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] + attribute \src "ls180.v:1049.11-1049.57" + wire width 4 $0\main_sdphy_cmdw_pads_out_payload_data_o[3:0] + attribute \src "ls180.v:1050.5-1050.52" + wire $0\main_sdphy_cmdw_pads_out_payload_data_oe[0:0] + attribute \src "ls180.v:5094.1-5284.4" + wire $0\main_sdphy_cmdw_sink_last[0:0] + attribute \src "ls180.v:5094.1-5284.4" + wire width 8 $0\main_sdphy_cmdw_sink_payload_data[7:0] + attribute \src "ls180.v:4322.1-4398.4" + wire $0\main_sdphy_cmdw_sink_ready[0:0] + attribute \src "ls180.v:5094.1-5284.4" + wire $0\main_sdphy_cmdw_sink_valid[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 10 $0\main_sdphy_datar_count[9:0] + attribute \src "ls180.v:4693.1-4794.4" + wire width 10 $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] + attribute \src "ls180.v:4693.1-4794.4" + wire $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_sdphy_datar_datar_buf_source_first[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_sdphy_datar_datar_buf_source_last[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 8 $0\main_sdphy_datar_datar_buf_source_payload_data[7:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_sdphy_datar_datar_buf_source_valid[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_sdphy_datar_datar_converter_demux[0:0] + attribute \src "ls180.v:1261.5-1261.55" + wire $0\main_sdphy_datar_datar_converter_sink_first[0:0] + attribute \src "ls180.v:1262.5-1262.54" + wire $0\main_sdphy_datar_datar_converter_sink_last[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_sdphy_datar_datar_converter_source_first[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_sdphy_datar_datar_converter_source_last[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 8 $0\main_sdphy_datar_datar_converter_source_payload_data[7:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 2 $0\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_sdphy_datar_datar_converter_strobe_all[0:0] + attribute \src "ls180.v:1242.5-1242.48" + wire $0\main_sdphy_datar_datar_pads_in_ready[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_sdphy_datar_datar_reset[0:0] + attribute \src "ls180.v:4693.1-4794.4" + wire $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] + attribute \src "ls180.v:4693.1-4794.4" + wire $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_sdphy_datar_datar_run[0:0] + attribute \src "ls180.v:4693.1-4794.4" + wire $0\main_sdphy_datar_datar_source_source_ready0[0:0] + attribute \src "ls180.v:1213.5-1213.50" + wire $0\main_sdphy_datar_pads_in_pads_in_first[0:0] + attribute \src "ls180.v:1214.5-1214.49" + wire $0\main_sdphy_datar_pads_in_pads_in_last[0:0] + attribute \src "ls180.v:1215.5-1215.56" + wire $0\main_sdphy_datar_pads_in_pads_in_payload_clk[0:0] + attribute \src "ls180.v:1217.5-1217.58" + wire $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_o[0:0] + attribute \src "ls180.v:1218.5-1218.59" + wire $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_oe[0:0] + attribute \src "ls180.v:1220.11-1220.65" + wire width 4 $0\main_sdphy_datar_pads_in_pads_in_payload_data_o[3:0] + attribute \src "ls180.v:1221.5-1221.60" + wire $0\main_sdphy_datar_pads_in_pads_in_payload_data_oe[0:0] + attribute \src "ls180.v:4693.1-4794.4" + wire $0\main_sdphy_datar_pads_out_payload_clk[0:0] + attribute \src "ls180.v:1224.5-1224.51" + wire $0\main_sdphy_datar_pads_out_payload_cmd_o[0:0] + attribute \src "ls180.v:1225.5-1225.52" + wire $0\main_sdphy_datar_pads_out_payload_cmd_oe[0:0] + attribute \src "ls180.v:1226.11-1226.58" + wire width 4 $0\main_sdphy_datar_pads_out_payload_data_o[3:0] + attribute \src "ls180.v:1227.5-1227.53" + wire $0\main_sdphy_datar_pads_out_payload_data_oe[0:0] + attribute \src "ls180.v:5094.1-5284.4" + wire $0\main_sdphy_datar_sink_last[0:0] + attribute \src "ls180.v:5094.1-5284.4" + wire width 10 $0\main_sdphy_datar_sink_payload_block_length[9:0] + attribute \src "ls180.v:4693.1-4794.4" + wire $0\main_sdphy_datar_sink_ready[0:0] + attribute \src "ls180.v:5094.1-5284.4" + wire $0\main_sdphy_datar_sink_valid[0:0] + attribute \src "ls180.v:1234.5-1234.41" + wire $0\main_sdphy_datar_source_first[0:0] + attribute \src "ls180.v:4693.1-4794.4" + wire $0\main_sdphy_datar_source_last[0:0] + attribute \src "ls180.v:4693.1-4794.4" + wire width 8 $0\main_sdphy_datar_source_payload_data[7:0] + attribute \src "ls180.v:4693.1-4794.4" + wire width 3 $0\main_sdphy_datar_source_payload_status[2:0] + attribute \src "ls180.v:5094.1-5284.4" + wire $0\main_sdphy_datar_source_ready[0:0] + attribute \src "ls180.v:4693.1-4794.4" + wire $0\main_sdphy_datar_source_valid[0:0] + attribute \src "ls180.v:4693.1-4794.4" + wire $0\main_sdphy_datar_stop[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 32 $0\main_sdphy_datar_timeout[31:0] + attribute \src "ls180.v:4693.1-4794.4" + wire width 32 $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] + attribute \src "ls180.v:4693.1-4794.4" + wire $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 8 $0\main_sdphy_dataw_count[7:0] + attribute \src "ls180.v:4587.1-4659.4" + wire width 8 $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] + attribute \src "ls180.v:4587.1-4659.4" + wire $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_sdphy_dataw_crcr_buf_source_first[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_sdphy_dataw_crcr_buf_source_last[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 8 $0\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_sdphy_dataw_crcr_buf_source_valid[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 3 $0\main_sdphy_dataw_crcr_converter_demux[2:0] + attribute \src "ls180.v:1183.5-1183.54" + wire $0\main_sdphy_dataw_crcr_converter_sink_first[0:0] + attribute \src "ls180.v:1184.5-1184.53" + wire $0\main_sdphy_dataw_crcr_converter_sink_last[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_sdphy_dataw_crcr_converter_source_first[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_sdphy_dataw_crcr_converter_source_last[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 8 $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 4 $0\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_sdphy_dataw_crcr_converter_strobe_all[0:0] + attribute \src "ls180.v:1164.5-1164.47" + wire $0\main_sdphy_dataw_crcr_pads_in_ready[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_sdphy_dataw_crcr_reset[0:0] + attribute \src "ls180.v:4559.1-4586.4" + wire $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] + attribute \src "ls180.v:4559.1-4586.4" + wire $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_sdphy_dataw_crcr_run[0:0] + attribute \src "ls180.v:4559.1-4586.4" + wire $0\main_sdphy_dataw_crcr_source_source_ready0[0:0] + attribute \src "ls180.v:4559.1-4586.4" + wire $0\main_sdphy_dataw_error[0:0] + attribute \src "ls180.v:1151.5-1151.50" + wire $0\main_sdphy_dataw_pads_in_pads_in_first[0:0] + attribute \src "ls180.v:1152.5-1152.49" + wire $0\main_sdphy_dataw_pads_in_pads_in_last[0:0] + attribute \src "ls180.v:1153.5-1153.56" + wire $0\main_sdphy_dataw_pads_in_pads_in_payload_clk[0:0] + attribute \src "ls180.v:1154.5-1154.58" + wire $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_i[0:0] + attribute \src "ls180.v:1155.5-1155.58" + wire $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_o[0:0] + attribute \src "ls180.v:1156.5-1156.59" + wire $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_oe[0:0] + attribute \src "ls180.v:1157.11-1157.65" + wire width 4 $0\main_sdphy_dataw_pads_in_pads_in_payload_data_i[3:0] + attribute \src "ls180.v:1158.11-1158.65" + wire width 4 $0\main_sdphy_dataw_pads_in_pads_in_payload_data_o[3:0] + attribute \src "ls180.v:1159.5-1159.60" + wire $0\main_sdphy_dataw_pads_in_pads_in_payload_data_oe[0:0] + attribute \src "ls180.v:1149.5-1149.50" + wire $0\main_sdphy_dataw_pads_in_pads_in_valid[0:0] + attribute \src "ls180.v:4587.1-4659.4" + wire $0\main_sdphy_dataw_pads_out_payload_clk[0:0] + attribute \src "ls180.v:1138.5-1138.51" + wire $0\main_sdphy_dataw_pads_out_payload_cmd_o[0:0] + attribute \src "ls180.v:1139.5-1139.52" + wire $0\main_sdphy_dataw_pads_out_payload_cmd_oe[0:0] + attribute \src "ls180.v:4587.1-4659.4" + wire width 4 $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] + attribute \src "ls180.v:4587.1-4659.4" + wire $0\main_sdphy_dataw_pads_out_payload_data_oe[0:0] + attribute \src "ls180.v:5094.1-5284.4" + wire $0\main_sdphy_dataw_sink_first[0:0] + attribute \src "ls180.v:5094.1-5284.4" + wire $0\main_sdphy_dataw_sink_last[0:0] + attribute \src "ls180.v:5094.1-5284.4" + wire width 8 $0\main_sdphy_dataw_sink_payload_data[7:0] + attribute \src "ls180.v:4587.1-4659.4" + wire $0\main_sdphy_dataw_sink_ready[0:0] + attribute \src "ls180.v:5094.1-5284.4" + wire $0\main_sdphy_dataw_sink_valid[0:0] + attribute \src "ls180.v:4587.1-4659.4" + wire $0\main_sdphy_dataw_start[0:0] + attribute \src "ls180.v:4587.1-4659.4" + wire $0\main_sdphy_dataw_stop[0:0] + attribute \src "ls180.v:4559.1-4586.4" + wire $0\main_sdphy_dataw_valid[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 8 $0\main_sdphy_init_count[7:0] + attribute \src "ls180.v:4288.1-4321.4" + wire width 8 $0\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] + attribute \src "ls180.v:4288.1-4321.4" + wire $0\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] + attribute \src "ls180.v:1031.5-1031.40" + wire $0\main_sdphy_init_initialize_w[0:0] + attribute \src "ls180.v:4288.1-4321.4" + wire $0\main_sdphy_init_pads_out_payload_clk[0:0] + attribute \src "ls180.v:4288.1-4321.4" + wire $0\main_sdphy_init_pads_out_payload_cmd_o[0:0] + attribute \src "ls180.v:4288.1-4321.4" + wire $0\main_sdphy_init_pads_out_payload_cmd_oe[0:0] + attribute \src "ls180.v:4288.1-4321.4" + wire width 4 $0\main_sdphy_init_pads_out_payload_data_o[3:0] + attribute \src "ls180.v:4288.1-4321.4" + wire $0\main_sdphy_init_pads_out_payload_data_oe[0:0] + attribute \src "ls180.v:7287.1-7357.4" + wire $0\main_sdphy_sdpads_cmd_i[0:0] + attribute \src "ls180.v:7287.1-7357.4" + wire width 4 $0\main_sdphy_sdpads_data_i[3:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_sdram_address_re[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 13 $0\main_sdram_address_storage[12:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_sdram_baddress_re[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 2 $0\main_sdram_baddress_storage[1:0] + attribute \src "ls180.v:3137.1-3144.4" + wire $0\main_sdram_bankmachine0_auto_precharge[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 3 $0\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 4 $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 3 $0\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] + attribute \src "ls180.v:417.5-417.64" + wire $0\main_sdram_bankmachine0_cmd_buffer_lookahead_replace[0:0] + attribute \src "ls180.v:400.5-400.67" + wire $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first[0:0] + attribute \src "ls180.v:401.5-401.66" + wire $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last[0:0] + attribute \src "ls180.v:3159.1-3166.4" + wire width 3 $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 22 $0\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] + attribute \src "ls180.v:3126.1-3133.4" + wire width 13 $0\main_sdram_bankmachine0_cmd_payload_a[12:0] + attribute \src "ls180.v:3175.1-3268.4" + wire $0\main_sdram_bankmachine0_cmd_payload_cas[0:0] + attribute \src "ls180.v:3175.1-3268.4" + wire $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] + attribute \src "ls180.v:3175.1-3268.4" + wire $0\main_sdram_bankmachine0_cmd_payload_is_read[0:0] + attribute \src "ls180.v:3175.1-3268.4" + wire $0\main_sdram_bankmachine0_cmd_payload_is_write[0:0] + attribute \src "ls180.v:3175.1-3268.4" + wire $0\main_sdram_bankmachine0_cmd_payload_ras[0:0] + attribute \src "ls180.v:3175.1-3268.4" + wire $0\main_sdram_bankmachine0_cmd_payload_we[0:0] + attribute \src "ls180.v:3824.1-3832.4" + wire $0\main_sdram_bankmachine0_cmd_ready[0:0] + attribute \src "ls180.v:3175.1-3268.4" + wire $0\main_sdram_bankmachine0_cmd_valid[0:0] + attribute \src "ls180.v:3175.1-3268.4" + wire $0\main_sdram_bankmachine0_refresh_gnt[0:0] + attribute \src "ls180.v:3175.1-3268.4" + wire $0\main_sdram_bankmachine0_req_rdata_valid[0:0] + attribute \src "ls180.v:3175.1-3268.4" + wire $0\main_sdram_bankmachine0_req_wdata_ready[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 13 $0\main_sdram_bankmachine0_row[12:0] + attribute \src "ls180.v:3175.1-3268.4" + wire $0\main_sdram_bankmachine0_row_close[0:0] + attribute \src "ls180.v:3175.1-3268.4" + wire $0\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] + attribute \src "ls180.v:3175.1-3268.4" + wire $0\main_sdram_bankmachine0_row_open[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_sdram_bankmachine0_row_opened[0:0] + attribute \src "ls180.v:459.32-459.76" + wire $0\main_sdram_bankmachine0_trascon_ready[0:0] + attribute \src "ls180.v:457.32-457.75" + wire $0\main_sdram_bankmachine0_trccon_ready[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 3 $0\main_sdram_bankmachine0_twtpcon_count[2:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_sdram_bankmachine0_twtpcon_ready[0:0] + attribute \src "ls180.v:3294.1-3301.4" + wire $0\main_sdram_bankmachine1_auto_precharge[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 3 $0\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 4 $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 3 $0\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] + attribute \src "ls180.v:499.5-499.64" + wire $0\main_sdram_bankmachine1_cmd_buffer_lookahead_replace[0:0] + attribute \src "ls180.v:482.5-482.67" + wire $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first[0:0] + attribute \src "ls180.v:483.5-483.66" + wire $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last[0:0] + attribute \src "ls180.v:3316.1-3323.4" + wire width 3 $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 22 $0\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] + attribute \src "ls180.v:3283.1-3290.4" + wire width 13 $0\main_sdram_bankmachine1_cmd_payload_a[12:0] + attribute \src "ls180.v:3332.1-3425.4" + wire $0\main_sdram_bankmachine1_cmd_payload_cas[0:0] + attribute \src "ls180.v:3332.1-3425.4" + wire $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] + attribute \src "ls180.v:3332.1-3425.4" + wire $0\main_sdram_bankmachine1_cmd_payload_is_read[0:0] + attribute \src "ls180.v:3332.1-3425.4" + wire $0\main_sdram_bankmachine1_cmd_payload_is_write[0:0] + attribute \src "ls180.v:3332.1-3425.4" + wire $0\main_sdram_bankmachine1_cmd_payload_ras[0:0] + attribute \src "ls180.v:3332.1-3425.4" + wire $0\main_sdram_bankmachine1_cmd_payload_we[0:0] + attribute \src "ls180.v:3833.1-3841.4" + wire $0\main_sdram_bankmachine1_cmd_ready[0:0] + attribute \src "ls180.v:3332.1-3425.4" + wire $0\main_sdram_bankmachine1_cmd_valid[0:0] + attribute \src "ls180.v:3332.1-3425.4" + wire $0\main_sdram_bankmachine1_refresh_gnt[0:0] + attribute \src "ls180.v:3332.1-3425.4" + wire $0\main_sdram_bankmachine1_req_rdata_valid[0:0] + attribute \src "ls180.v:3332.1-3425.4" + wire $0\main_sdram_bankmachine1_req_wdata_ready[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 13 $0\main_sdram_bankmachine1_row[12:0] + attribute \src "ls180.v:3332.1-3425.4" + wire $0\main_sdram_bankmachine1_row_close[0:0] + attribute \src "ls180.v:3332.1-3425.4" + wire $0\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] + attribute \src "ls180.v:3332.1-3425.4" + wire $0\main_sdram_bankmachine1_row_open[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_sdram_bankmachine1_row_opened[0:0] + attribute \src "ls180.v:541.32-541.76" + wire $0\main_sdram_bankmachine1_trascon_ready[0:0] + attribute \src "ls180.v:539.32-539.75" + wire $0\main_sdram_bankmachine1_trccon_ready[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 3 $0\main_sdram_bankmachine1_twtpcon_count[2:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_sdram_bankmachine1_twtpcon_ready[0:0] + attribute \src "ls180.v:3451.1-3458.4" + wire $0\main_sdram_bankmachine2_auto_precharge[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 3 $0\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 4 $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 3 $0\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] + attribute \src "ls180.v:581.5-581.64" + wire $0\main_sdram_bankmachine2_cmd_buffer_lookahead_replace[0:0] + attribute \src "ls180.v:564.5-564.67" + wire $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first[0:0] + attribute \src "ls180.v:565.5-565.66" + wire $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last[0:0] + attribute \src "ls180.v:3473.1-3480.4" + wire width 3 $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 22 $0\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] + attribute \src "ls180.v:3440.1-3447.4" + wire width 13 $0\main_sdram_bankmachine2_cmd_payload_a[12:0] + attribute \src "ls180.v:3489.1-3582.4" + wire $0\main_sdram_bankmachine2_cmd_payload_cas[0:0] + attribute \src "ls180.v:3489.1-3582.4" + wire $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] + attribute \src "ls180.v:3489.1-3582.4" + wire $0\main_sdram_bankmachine2_cmd_payload_is_read[0:0] + attribute \src "ls180.v:3489.1-3582.4" + wire $0\main_sdram_bankmachine2_cmd_payload_is_write[0:0] + attribute \src "ls180.v:3489.1-3582.4" + wire $0\main_sdram_bankmachine2_cmd_payload_ras[0:0] + attribute \src "ls180.v:3489.1-3582.4" + wire $0\main_sdram_bankmachine2_cmd_payload_we[0:0] + attribute \src "ls180.v:3842.1-3850.4" + wire $0\main_sdram_bankmachine2_cmd_ready[0:0] + attribute \src "ls180.v:3489.1-3582.4" + wire $0\main_sdram_bankmachine2_cmd_valid[0:0] + attribute \src "ls180.v:3489.1-3582.4" + wire $0\main_sdram_bankmachine2_refresh_gnt[0:0] + attribute \src "ls180.v:3489.1-3582.4" + wire $0\main_sdram_bankmachine2_req_rdata_valid[0:0] + attribute \src "ls180.v:3489.1-3582.4" + wire $0\main_sdram_bankmachine2_req_wdata_ready[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 13 $0\main_sdram_bankmachine2_row[12:0] + attribute \src "ls180.v:3489.1-3582.4" + wire $0\main_sdram_bankmachine2_row_close[0:0] + attribute \src "ls180.v:3489.1-3582.4" + wire $0\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] + attribute \src "ls180.v:3489.1-3582.4" + wire $0\main_sdram_bankmachine2_row_open[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_sdram_bankmachine2_row_opened[0:0] + attribute \src "ls180.v:623.32-623.76" + wire $0\main_sdram_bankmachine2_trascon_ready[0:0] + attribute \src "ls180.v:621.32-621.75" + wire $0\main_sdram_bankmachine2_trccon_ready[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 3 $0\main_sdram_bankmachine2_twtpcon_count[2:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_sdram_bankmachine2_twtpcon_ready[0:0] + attribute \src "ls180.v:3608.1-3615.4" + wire $0\main_sdram_bankmachine3_auto_precharge[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 3 $0\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 4 $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 3 $0\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] + attribute \src "ls180.v:663.5-663.64" + wire $0\main_sdram_bankmachine3_cmd_buffer_lookahead_replace[0:0] + attribute \src "ls180.v:646.5-646.67" + wire $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first[0:0] + attribute \src "ls180.v:647.5-647.66" + wire $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last[0:0] + attribute \src "ls180.v:3630.1-3637.4" + wire width 3 $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 22 $0\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] + attribute \src "ls180.v:3597.1-3604.4" + wire width 13 $0\main_sdram_bankmachine3_cmd_payload_a[12:0] + attribute \src "ls180.v:3646.1-3739.4" + wire $0\main_sdram_bankmachine3_cmd_payload_cas[0:0] + attribute \src "ls180.v:3646.1-3739.4" + wire $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] + attribute \src "ls180.v:3646.1-3739.4" + wire $0\main_sdram_bankmachine3_cmd_payload_is_read[0:0] + attribute \src "ls180.v:3646.1-3739.4" + wire $0\main_sdram_bankmachine3_cmd_payload_is_write[0:0] + attribute \src "ls180.v:3646.1-3739.4" + wire $0\main_sdram_bankmachine3_cmd_payload_ras[0:0] + attribute \src "ls180.v:3646.1-3739.4" + wire $0\main_sdram_bankmachine3_cmd_payload_we[0:0] + attribute \src "ls180.v:3851.1-3859.4" + wire $0\main_sdram_bankmachine3_cmd_ready[0:0] + attribute \src "ls180.v:3646.1-3739.4" + wire $0\main_sdram_bankmachine3_cmd_valid[0:0] + attribute \src "ls180.v:3646.1-3739.4" + wire $0\main_sdram_bankmachine3_refresh_gnt[0:0] + attribute \src "ls180.v:3646.1-3739.4" + wire $0\main_sdram_bankmachine3_req_rdata_valid[0:0] + attribute \src "ls180.v:3646.1-3739.4" + wire $0\main_sdram_bankmachine3_req_wdata_ready[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 13 $0\main_sdram_bankmachine3_row[12:0] + attribute \src "ls180.v:3646.1-3739.4" + wire $0\main_sdram_bankmachine3_row_close[0:0] + attribute \src "ls180.v:3646.1-3739.4" + wire $0\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] + attribute \src "ls180.v:3646.1-3739.4" + wire $0\main_sdram_bankmachine3_row_open[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_sdram_bankmachine3_row_opened[0:0] + attribute \src "ls180.v:705.32-705.76" + wire $0\main_sdram_bankmachine3_trascon_ready[0:0] + attribute \src "ls180.v:703.32-703.75" + wire $0\main_sdram_bankmachine3_trccon_ready[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 3 $0\main_sdram_bankmachine3_twtpcon_count[2:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_sdram_bankmachine3_twtpcon_ready[0:0] + attribute \src "ls180.v:3773.1-3778.4" + wire $0\main_sdram_choose_cmd_cmd_payload_cas[0:0] + attribute \src "ls180.v:3779.1-3784.4" + wire $0\main_sdram_choose_cmd_cmd_payload_ras[0:0] + attribute \src "ls180.v:3785.1-3790.4" + wire $0\main_sdram_choose_cmd_cmd_payload_we[0:0] + attribute \src "ls180.v:713.5-713.43" + wire $0\main_sdram_choose_cmd_cmd_ready[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 2 $0\main_sdram_choose_cmd_grant[1:0] + attribute \src "ls180.v:3759.1-3765.4" + wire width 4 $0\main_sdram_choose_cmd_valids[3:0] + attribute \src "ls180.v:711.5-711.48" + wire $0\main_sdram_choose_cmd_want_activates[0:0] + attribute \src "ls180.v:710.5-710.43" + wire $0\main_sdram_choose_cmd_want_cmds[0:0] + attribute \src "ls180.v:708.5-708.44" + wire $0\main_sdram_choose_cmd_want_reads[0:0] + attribute \src "ls180.v:709.5-709.45" + wire $0\main_sdram_choose_cmd_want_writes[0:0] + attribute \src "ls180.v:3806.1-3811.4" + wire $0\main_sdram_choose_req_cmd_payload_cas[0:0] + attribute \src "ls180.v:3812.1-3817.4" + wire $0\main_sdram_choose_req_cmd_payload_ras[0:0] + attribute \src "ls180.v:3818.1-3823.4" + wire $0\main_sdram_choose_req_cmd_payload_we[0:0] + attribute \src "ls180.v:3864.1-3936.4" + wire $0\main_sdram_choose_req_cmd_ready[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 2 $0\main_sdram_choose_req_grant[1:0] + attribute \src "ls180.v:3792.1-3798.4" + wire width 4 $0\main_sdram_choose_req_valids[3:0] + attribute \src "ls180.v:3864.1-3936.4" + wire $0\main_sdram_choose_req_want_activates[0:0] + attribute \src "ls180.v:3864.1-3936.4" + wire $0\main_sdram_choose_req_want_reads[0:0] + attribute \src "ls180.v:3864.1-3936.4" + wire $0\main_sdram_choose_req_want_writes[0:0] + attribute \src "ls180.v:3081.1-3111.4" + wire $0\main_sdram_cmd_last[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 13 $0\main_sdram_cmd_payload_a[12:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 2 $0\main_sdram_cmd_payload_ba[1:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_sdram_cmd_payload_cas[0:0] + attribute \src "ls180.v:361.5-361.42" + wire $0\main_sdram_cmd_payload_is_read[0:0] + attribute \src "ls180.v:362.5-362.43" + wire $0\main_sdram_cmd_payload_is_write[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_sdram_cmd_payload_ras[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_sdram_cmd_payload_we[0:0] + attribute \src "ls180.v:3864.1-3936.4" + wire $0\main_sdram_cmd_ready[0:0] + attribute \src "ls180.v:3081.1-3111.4" + wire $0\main_sdram_cmd_valid[0:0] + attribute \src "ls180.v:297.5-297.38" + wire $0\main_sdram_command_issue_w[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_sdram_command_re[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 6 $0\main_sdram_command_storage[5:0] + attribute \src "ls180.v:346.5-346.35" + wire $0\main_sdram_dfi_p0_act_n[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 13 $0\main_sdram_dfi_p0_address[12:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 2 $0\main_sdram_dfi_p0_bank[1:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_sdram_dfi_p0_cas_n[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_sdram_dfi_p0_cs_n[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_sdram_dfi_p0_ras_n[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_sdram_dfi_p0_rddata_en[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_sdram_dfi_p0_we_n[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_sdram_dfi_p0_wrdata_en[0:0] + attribute \src "ls180.v:3864.1-3936.4" + wire $0\main_sdram_en0[0:0] + attribute \src "ls180.v:3864.1-3936.4" + wire $0\main_sdram_en1[0:0] + attribute \src "ls180.v:3960.1-3973.4" + wire width 16 $0\main_sdram_interface_wdata[15:0] + attribute \src "ls180.v:3960.1-3973.4" + wire width 2 $0\main_sdram_interface_wdata_we[1:0] + attribute \src "ls180.v:247.5-247.36" + wire $0\main_sdram_inti_p0_act_n[0:0] + attribute \src "ls180.v:3022.1-3038.4" + wire $0\main_sdram_inti_p0_cas_n[0:0] + attribute \src "ls180.v:3022.1-3038.4" + wire $0\main_sdram_inti_p0_cs_n[0:0] + attribute \src "ls180.v:3022.1-3038.4" + wire $0\main_sdram_inti_p0_ras_n[0:0] + attribute \src "ls180.v:2964.1-3018.4" + wire width 16 $0\main_sdram_inti_p0_rddata[15:0] + attribute \src "ls180.v:2964.1-3018.4" + wire $0\main_sdram_inti_p0_rddata_valid[0:0] + attribute \src "ls180.v:3022.1-3038.4" + wire $0\main_sdram_inti_p0_we_n[0:0] + attribute \src "ls180.v:2964.1-3018.4" + wire $0\main_sdram_master_p0_act_n[0:0] + attribute \src "ls180.v:2964.1-3018.4" + wire width 13 $0\main_sdram_master_p0_address[12:0] + attribute \src "ls180.v:2964.1-3018.4" + wire width 2 $0\main_sdram_master_p0_bank[1:0] + attribute \src "ls180.v:2964.1-3018.4" + wire $0\main_sdram_master_p0_cas_n[0:0] + attribute \src "ls180.v:2964.1-3018.4" + wire $0\main_sdram_master_p0_cke[0:0] + attribute \src "ls180.v:2964.1-3018.4" + wire $0\main_sdram_master_p0_cs_n[0:0] + attribute \src "ls180.v:2964.1-3018.4" + wire $0\main_sdram_master_p0_odt[0:0] + attribute \src "ls180.v:2964.1-3018.4" + wire $0\main_sdram_master_p0_ras_n[0:0] + attribute \src "ls180.v:2964.1-3018.4" + wire $0\main_sdram_master_p0_rddata_en[0:0] + attribute \src "ls180.v:2964.1-3018.4" + wire $0\main_sdram_master_p0_reset_n[0:0] + attribute \src "ls180.v:2964.1-3018.4" + wire $0\main_sdram_master_p0_we_n[0:0] + attribute \src "ls180.v:2964.1-3018.4" + wire width 16 $0\main_sdram_master_p0_wrdata[15:0] + attribute \src "ls180.v:2964.1-3018.4" + wire $0\main_sdram_master_p0_wrdata_en[0:0] + attribute \src "ls180.v:2964.1-3018.4" + wire width 2 $0\main_sdram_master_p0_wrdata_mask[1:0] + attribute \src "ls180.v:744.12-744.36" + wire width 13 $0\main_sdram_nop_a[12:0] + attribute \src "ls180.v:745.11-745.35" + wire width 2 $0\main_sdram_nop_ba[1:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_sdram_postponer_count[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_sdram_postponer_req_o[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_sdram_re[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_sdram_sequencer_count[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 4 $0\main_sdram_sequencer_counter[3:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_sdram_sequencer_done1[0:0] + attribute \src "ls180.v:3081.1-3111.4" + wire $0\main_sdram_sequencer_start0[0:0] + attribute \src "ls180.v:2964.1-3018.4" + wire width 16 $0\main_sdram_slave_p0_rddata[15:0] + attribute \src "ls180.v:2964.1-3018.4" + wire $0\main_sdram_slave_p0_rddata_valid[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 16 $0\main_sdram_status[15:0] + attribute \src "ls180.v:747.5-747.31" + wire $0\main_sdram_steerer0[0:0] + attribute \src "ls180.v:748.5-748.31" + wire $0\main_sdram_steerer1[0:0] + attribute \src "ls180.v:3864.1-3936.4" + wire width 2 $0\main_sdram_steerer_sel[1:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 4 $0\main_sdram_storage[3:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_sdram_tccdcon_count[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_sdram_tccdcon_ready[0:0] + attribute \src "ls180.v:752.32-752.63" + wire $0\main_sdram_tfawcon_ready[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 5 $0\main_sdram_time0[4:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 4 $0\main_sdram_time1[3:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 10 $0\main_sdram_timer_count1[9:0] + attribute \src "ls180.v:750.32-750.63" + wire $0\main_sdram_trrdcon_ready[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 3 $0\main_sdram_twtrcon_count[2:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_sdram_twtrcon_ready[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_sdram_wrdata_re[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 16 $0\main_sdram_wrdata_storage[15:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_sink_ready[0:0] + attribute \src "ls180.v:823.5-823.29" + wire $0\main_source_first[0:0] + attribute \src "ls180.v:824.5-824.28" + wire $0\main_source_last[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 8 $0\main_source_payload_data[7:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_source_valid[0:0] + attribute \src "ls180.v:968.12-968.48" + wire width 16 $0\main_spi_master_clk_divider0[15:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 16 $0\main_spi_master_clk_divider1[15:0] + attribute \src "ls180.v:4182.1-4230.4" + wire $0\main_spi_master_clk_enable[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_spi_master_control_re[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 16 $0\main_spi_master_control_storage[15:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 3 $0\main_spi_master_count[2:0] + attribute \src "ls180.v:4182.1-4230.4" + wire width 3 $0\main_spi_master_count_spimaster0_next_value[2:0] + attribute \src "ls180.v:4182.1-4230.4" + wire $0\main_spi_master_count_spimaster0_next_value_ce[0:0] + attribute \src "ls180.v:4182.1-4230.4" + wire $0\main_spi_master_cs_enable[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_spi_master_cs_re[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_spi_master_cs_storage[0:0] + attribute \src "ls180.v:4182.1-4230.4" + wire $0\main_spi_master_done0[0:0] + attribute \src "ls180.v:4182.1-4230.4" + wire $0\main_spi_master_irq[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_spi_master_loopback_re[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_spi_master_loopback_storage[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 8 $0\main_spi_master_miso[7:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 8 $0\main_spi_master_miso_data[7:0] + attribute \src "ls180.v:4182.1-4230.4" + wire $0\main_spi_master_miso_latch[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 8 $0\main_spi_master_mosi_data[7:0] + attribute \src "ls180.v:4182.1-4230.4" + wire $0\main_spi_master_mosi_latch[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_spi_master_mosi_re[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 3 $0\main_spi_master_mosi_sel[2:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 8 $0\main_spi_master_mosi_storage[7:0] + attribute \src "ls180.v:6216.1-6221.4" + wire $0\main_spi_master_start1[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 32 $0\main_storage[31:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 4 $0\main_tx_bitcount[3:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_tx_busy[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 8 $0\main_tx_reg[7:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_uart_clk_rxen[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_uart_clk_txen[0:0] + attribute \src "ls180.v:4100.1-4104.4" + wire width 2 $0\main_uart_eventmanager_pending_w[1:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_uart_eventmanager_re[0:0] + attribute \src "ls180.v:4089.1-4093.4" + wire width 2 $0\main_uart_eventmanager_status_w[1:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 2 $0\main_uart_eventmanager_storage[1:0] + attribute \src "ls180.v:950.5-950.27" + wire $0\main_uart_reset[0:0] + attribute \src "ls180.v:4094.1-4099.4" + wire $0\main_uart_rx_clear[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 4 $0\main_uart_rx_fifo_consume[3:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 5 $0\main_uart_rx_fifo_level0[4:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 4 $0\main_uart_rx_fifo_produce[3:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_uart_rx_fifo_readable[0:0] + attribute \src "ls180.v:932.5-932.37" + wire $0\main_uart_rx_fifo_replace[0:0] + attribute \src "ls180.v:4152.1-4159.4" + wire width 4 $0\main_uart_rx_fifo_wrport_adr[3:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_uart_rx_old_trigger[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_uart_rx_pending[0:0] + attribute \src "ls180.v:4083.1-4088.4" + wire $0\main_uart_tx_clear[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 4 $0\main_uart_tx_fifo_consume[3:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 5 $0\main_uart_tx_fifo_level0[4:0] + attribute \src "ls180.v:7359.1-9973.4" + wire width 4 $0\main_uart_tx_fifo_produce[3:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_uart_tx_fifo_readable[0:0] + attribute \src "ls180.v:895.5-895.37" + wire $0\main_uart_tx_fifo_replace[0:0] + attribute \src "ls180.v:878.5-878.40" + wire $0\main_uart_tx_fifo_sink_first[0:0] + attribute \src "ls180.v:879.5-879.39" + wire $0\main_uart_tx_fifo_sink_last[0:0] + attribute \src "ls180.v:4122.1-4129.4" + wire width 4 $0\main_uart_tx_fifo_wrport_adr[3:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_uart_tx_old_trigger[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_uart_tx_pending[0:0] + attribute \src "ls180.v:3992.1-4038.4" + wire $0\main_wb_sdram_ack[0:0] + attribute \src "ls180.v:791.5-791.29" + wire $0\main_wb_sdram_err[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\main_wdata_consumed[0:0] + attribute \src "ls180.v:9977.1-9987.4" + wire width 7 $0\memadr[6:0] + attribute \src "ls180.v:9997.1-10001.4" + wire width 25 $0\memdat[24:0] + attribute \src "ls180.v:10011.1-10015.4" + wire width 25 $0\memdat_1[24:0] + attribute \src "ls180.v:10025.1-10029.4" + wire width 25 $0\memdat_2[24:0] + attribute \src "ls180.v:10039.1-10043.4" + wire width 25 $0\memdat_3[24:0] + attribute \src "ls180.v:10054.1-10058.4" + wire width 10 $0\memdat_4[9:0] + attribute \src "ls180.v:10060.1-10063.4" + wire width 10 $0\memdat_5[9:0] + attribute \src "ls180.v:10071.1-10075.4" + wire width 10 $0\memdat_6[9:0] + attribute \src "ls180.v:10077.1-10080.4" + wire width 10 $0\memdat_7[9:0] + attribute \src "ls180.v:10087.1-10091.4" + wire width 10 $0\memdat_8[9:0] + attribute \src "ls180.v:10101.1-10105.4" + wire width 10 $0\memdat_9[9:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\pwm0[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\pwm1[0:0] + attribute \src "ls180.v:7287.1-7357.4" + wire $0\sdcard_clk[0:0] + attribute \src "ls180.v:7287.1-7357.4" + wire $0\sdcard_cmd_o[0:0] + attribute \src "ls180.v:7287.1-7357.4" + wire $0\sdcard_cmd_oe[0:0] + attribute \src "ls180.v:7287.1-7357.4" + wire width 4 $0\sdcard_data_o[3:0] + attribute \src "ls180.v:7287.1-7357.4" + wire $0\sdcard_data_oe[0:0] + attribute \src "ls180.v:7287.1-7357.4" + wire width 13 $0\sdram_a[12:0] + attribute \src "ls180.v:7287.1-7357.4" + wire width 2 $0\sdram_ba[1:0] + attribute \src "ls180.v:7287.1-7357.4" + wire $0\sdram_cas_n[0:0] + attribute \src "ls180.v:7287.1-7357.4" + wire $0\sdram_cke[0:0] + attribute \src "ls180.v:7287.1-7357.4" + wire $0\sdram_clock[0:0] + attribute \src "ls180.v:7287.1-7357.4" + wire $0\sdram_cs_n[0:0] + attribute \src "ls180.v:7287.1-7357.4" + wire width 2 $0\sdram_dm[1:0] + attribute \src "ls180.v:7287.1-7357.4" + wire width 16 $0\sdram_dq_o[15:0] + attribute \src "ls180.v:7287.1-7357.4" + wire $0\sdram_dq_oe[0:0] + attribute \src "ls180.v:7287.1-7357.4" + wire $0\sdram_ras_n[0:0] + attribute \src "ls180.v:7287.1-7357.4" + wire $0\sdram_we_n[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\spi_master_clk[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\spi_master_cs_n[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\spi_master_mosi[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\spisdcard_clk[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\spisdcard_cs_n[0:0] + attribute \src "ls180.v:7359.1-9973.4" + wire $0\spisdcard_mosi[0:0] + attribute \src "ls180.v:1709.11-1709.49" + wire width 3 $1\builder_bankmachine0_next_state[2:0] + attribute \src "ls180.v:1708.11-1708.44" + wire width 3 $1\builder_bankmachine0_state[2:0] + attribute \src "ls180.v:1711.11-1711.49" + wire width 3 $1\builder_bankmachine1_next_state[2:0] + attribute \src "ls180.v:1710.11-1710.44" + wire width 3 $1\builder_bankmachine1_state[2:0] + attribute \src "ls180.v:1713.11-1713.49" + wire width 3 $1\builder_bankmachine2_next_state[2:0] + attribute \src "ls180.v:1712.11-1712.44" + wire width 3 $1\builder_bankmachine2_state[2:0] + attribute \src "ls180.v:1715.11-1715.49" + wire width 3 $1\builder_bankmachine3_next_state[2:0] + attribute \src "ls180.v:1714.11-1714.44" + wire width 3 $1\builder_bankmachine3_state[2:0] + attribute \src "ls180.v:2547.5-2547.41" + wire $1\builder_comb_rhs_array_muxed0[0:0] + attribute \src "ls180.v:2560.5-2560.42" + wire $1\builder_comb_rhs_array_muxed10[0:0] + attribute \src "ls180.v:2561.5-2561.42" + wire $1\builder_comb_rhs_array_muxed11[0:0] + attribute \src "ls180.v:2565.12-2565.50" + wire width 22 $1\builder_comb_rhs_array_muxed12[21:0] + attribute \src "ls180.v:2566.5-2566.42" + wire $1\builder_comb_rhs_array_muxed13[0:0] + attribute \src "ls180.v:2567.5-2567.42" + wire $1\builder_comb_rhs_array_muxed14[0:0] + attribute \src "ls180.v:2568.12-2568.50" + wire width 22 $1\builder_comb_rhs_array_muxed15[21:0] + attribute \src "ls180.v:2569.5-2569.42" + wire $1\builder_comb_rhs_array_muxed16[0:0] + attribute \src "ls180.v:2570.5-2570.42" + wire $1\builder_comb_rhs_array_muxed17[0:0] + attribute \src "ls180.v:2571.12-2571.50" + wire width 22 $1\builder_comb_rhs_array_muxed18[21:0] + attribute \src "ls180.v:2572.5-2572.42" + wire $1\builder_comb_rhs_array_muxed19[0:0] + attribute \src "ls180.v:2548.12-2548.49" + wire width 13 $1\builder_comb_rhs_array_muxed1[12:0] + attribute \src "ls180.v:2573.5-2573.42" + wire $1\builder_comb_rhs_array_muxed20[0:0] + attribute \src "ls180.v:2574.12-2574.50" + wire width 22 $1\builder_comb_rhs_array_muxed21[21:0] + attribute \src "ls180.v:2575.5-2575.42" + wire $1\builder_comb_rhs_array_muxed22[0:0] + attribute \src "ls180.v:2576.5-2576.42" + wire $1\builder_comb_rhs_array_muxed23[0:0] + attribute \src "ls180.v:2577.12-2577.50" + wire width 32 $1\builder_comb_rhs_array_muxed24[31:0] + attribute \src "ls180.v:2578.12-2578.50" + wire width 32 $1\builder_comb_rhs_array_muxed25[31:0] + attribute \src "ls180.v:2579.11-2579.48" + wire width 4 $1\builder_comb_rhs_array_muxed26[3:0] + attribute \src "ls180.v:2580.5-2580.42" + wire $1\builder_comb_rhs_array_muxed27[0:0] + attribute \src "ls180.v:2581.5-2581.42" + wire $1\builder_comb_rhs_array_muxed28[0:0] + attribute \src "ls180.v:2582.5-2582.42" + wire $1\builder_comb_rhs_array_muxed29[0:0] + attribute \src "ls180.v:2549.11-2549.47" + wire width 2 $1\builder_comb_rhs_array_muxed2[1:0] + attribute \src "ls180.v:2583.11-2583.48" + wire width 3 $1\builder_comb_rhs_array_muxed30[2:0] + attribute \src "ls180.v:2584.11-2584.48" + wire width 2 $1\builder_comb_rhs_array_muxed31[1:0] + attribute \src "ls180.v:2550.5-2550.41" + wire $1\builder_comb_rhs_array_muxed3[0:0] + attribute \src "ls180.v:2551.5-2551.41" + wire $1\builder_comb_rhs_array_muxed4[0:0] + attribute \src "ls180.v:2552.5-2552.41" + wire $1\builder_comb_rhs_array_muxed5[0:0] + attribute \src "ls180.v:2556.5-2556.41" + wire $1\builder_comb_rhs_array_muxed6[0:0] + attribute \src "ls180.v:2557.12-2557.49" + wire width 13 $1\builder_comb_rhs_array_muxed7[12:0] + attribute \src "ls180.v:2558.11-2558.47" + wire width 2 $1\builder_comb_rhs_array_muxed8[1:0] + attribute \src "ls180.v:2559.5-2559.41" + wire $1\builder_comb_rhs_array_muxed9[0:0] + attribute \src "ls180.v:2553.5-2553.39" + wire $1\builder_comb_t_array_muxed0[0:0] + attribute \src "ls180.v:2554.5-2554.39" + wire $1\builder_comb_t_array_muxed1[0:0] + attribute \src "ls180.v:2555.5-2555.39" + wire $1\builder_comb_t_array_muxed2[0:0] + attribute \src "ls180.v:2562.5-2562.39" + wire $1\builder_comb_t_array_muxed3[0:0] + attribute \src "ls180.v:2563.5-2563.39" + wire $1\builder_comb_t_array_muxed4[0:0] + attribute \src "ls180.v:2564.5-2564.39" + wire $1\builder_comb_t_array_muxed5[0:0] + attribute \src "ls180.v:1695.5-1695.41" + wire $1\builder_converter0_next_state[0:0] + attribute \src "ls180.v:1694.5-1694.36" + wire $1\builder_converter0_state[0:0] + attribute \src "ls180.v:1699.5-1699.41" + wire $1\builder_converter1_next_state[0:0] + attribute \src "ls180.v:1698.5-1698.36" + wire $1\builder_converter1_state[0:0] + attribute \src "ls180.v:1703.5-1703.41" + wire $1\builder_converter2_next_state[0:0] + attribute \src "ls180.v:1702.5-1702.36" + wire $1\builder_converter2_state[0:0] + attribute \src "ls180.v:1740.5-1740.40" + wire $1\builder_converter_next_state[0:0] + attribute \src "ls180.v:1739.5-1739.35" + wire $1\builder_converter_state[0:0] + attribute \src "ls180.v:1860.12-1860.39" + wire width 20 $1\builder_count[19:0] + attribute \src "ls180.v:1857.5-1857.25" + wire $1\builder_error[0:0] + attribute \src "ls180.v:1854.11-1854.31" + wire width 3 $1\builder_grant[2:0] + attribute \src "ls180.v:1864.11-1864.51" + wire width 8 $1\builder_interface0_bank_bus_dat_r[7:0] + attribute \src "ls180.v:2386.11-2386.52" + wire width 8 $1\builder_interface10_bank_bus_dat_r[7:0] + attribute \src "ls180.v:2427.11-2427.52" + wire width 8 $1\builder_interface11_bank_bus_dat_r[7:0] + attribute \src "ls180.v:2492.11-2492.52" + wire width 8 $1\builder_interface12_bank_bus_dat_r[7:0] + attribute \src "ls180.v:2517.11-2517.52" + wire width 8 $1\builder_interface13_bank_bus_dat_r[7:0] + attribute \src "ls180.v:1905.11-1905.51" + wire width 8 $1\builder_interface1_bank_bus_dat_r[7:0] + attribute \src "ls180.v:1934.11-1934.51" + wire width 8 $1\builder_interface2_bank_bus_dat_r[7:0] + attribute \src "ls180.v:1975.11-1975.51" + wire width 8 $1\builder_interface3_bank_bus_dat_r[7:0] + attribute \src "ls180.v:2016.11-2016.51" + wire width 8 $1\builder_interface4_bank_bus_dat_r[7:0] + attribute \src "ls180.v:2081.11-2081.51" + wire width 8 $1\builder_interface5_bank_bus_dat_r[7:0] + attribute \src "ls180.v:2214.11-2214.51" + wire width 8 $1\builder_interface6_bank_bus_dat_r[7:0] + attribute \src "ls180.v:2295.11-2295.51" + wire width 8 $1\builder_interface7_bank_bus_dat_r[7:0] + attribute \src "ls180.v:2312.11-2312.51" + wire width 8 $1\builder_interface8_bank_bus_dat_r[7:0] + attribute \src "ls180.v:2353.11-2353.51" + wire width 8 $1\builder_interface9_bank_bus_dat_r[7:0] + attribute \src "ls180.v:1827.12-1827.43" + wire width 14 $1\builder_libresocsim_adr[13:0] + attribute \src "ls180.v:2543.12-2543.55" + wire width 14 $1\builder_libresocsim_adr_next_value1[13:0] + attribute \src "ls180.v:2544.5-2544.50" + wire $1\builder_libresocsim_adr_next_value_ce1[0:0] + attribute \src "ls180.v:1829.11-1829.43" + wire width 8 $1\builder_libresocsim_dat_w[7:0] + attribute \src "ls180.v:2541.11-2541.55" + wire width 8 $1\builder_libresocsim_dat_w_next_value0[7:0] + attribute \src "ls180.v:2542.5-2542.52" + wire $1\builder_libresocsim_dat_w_next_value_ce0[0:0] + attribute \src "ls180.v:1828.5-1828.34" + wire $1\builder_libresocsim_we[0:0] + attribute \src "ls180.v:2545.5-2545.46" + wire $1\builder_libresocsim_we_next_value2[0:0] + attribute \src "ls180.v:2546.5-2546.49" + wire $1\builder_libresocsim_we_next_value_ce2[0:0] + attribute \src "ls180.v:1837.5-1837.44" + wire $1\builder_libresocsim_wishbone_ack[0:0] + attribute \src "ls180.v:1833.12-1833.54" + wire width 32 $1\builder_libresocsim_wishbone_dat_r[31:0] + attribute \src "ls180.v:1717.11-1717.48" + wire width 3 $1\builder_multiplexer_next_state[2:0] + attribute \src "ls180.v:1716.11-1716.43" + wire width 3 $1\builder_multiplexer_state[2:0] + attribute \src "ls180.v:2650.32-2650.66" + wire $1\builder_multiregimpl0_regs0[0:0] + attribute \src "ls180.v:2651.32-2651.66" + wire $1\builder_multiregimpl0_regs1[0:0] + attribute \src "ls180.v:2670.32-2670.67" + wire $1\builder_multiregimpl10_regs0[0:0] + attribute \src "ls180.v:2671.32-2671.67" + wire $1\builder_multiregimpl10_regs1[0:0] + attribute \src "ls180.v:2672.32-2672.67" + wire $1\builder_multiregimpl11_regs0[0:0] + attribute \src "ls180.v:2673.32-2673.67" + wire $1\builder_multiregimpl11_regs1[0:0] + attribute \src "ls180.v:2674.32-2674.67" + wire $1\builder_multiregimpl12_regs0[0:0] + attribute \src "ls180.v:2675.32-2675.67" + wire $1\builder_multiregimpl12_regs1[0:0] + attribute \src "ls180.v:2676.32-2676.67" + wire $1\builder_multiregimpl13_regs0[0:0] + attribute \src "ls180.v:2677.32-2677.67" + wire $1\builder_multiregimpl13_regs1[0:0] + attribute \src "ls180.v:2678.32-2678.67" + wire $1\builder_multiregimpl14_regs0[0:0] + attribute \src "ls180.v:2679.32-2679.67" + wire $1\builder_multiregimpl14_regs1[0:0] + attribute \src "ls180.v:2680.32-2680.67" + wire $1\builder_multiregimpl15_regs0[0:0] + attribute \src "ls180.v:2681.32-2681.67" + wire $1\builder_multiregimpl15_regs1[0:0] + attribute \src "ls180.v:2682.32-2682.67" + wire $1\builder_multiregimpl16_regs0[0:0] + attribute \src "ls180.v:2683.32-2683.67" + wire $1\builder_multiregimpl16_regs1[0:0] + attribute \src "ls180.v:2652.32-2652.66" + wire $1\builder_multiregimpl1_regs0[0:0] + attribute \src "ls180.v:2653.32-2653.66" + wire $1\builder_multiregimpl1_regs1[0:0] + attribute \src "ls180.v:2654.32-2654.66" + wire $1\builder_multiregimpl2_regs0[0:0] + attribute \src "ls180.v:2655.32-2655.66" + wire $1\builder_multiregimpl2_regs1[0:0] + attribute \src "ls180.v:2656.32-2656.66" + wire $1\builder_multiregimpl3_regs0[0:0] + attribute \src "ls180.v:2657.32-2657.66" + wire $1\builder_multiregimpl3_regs1[0:0] + attribute \src "ls180.v:2658.32-2658.66" + wire $1\builder_multiregimpl4_regs0[0:0] + attribute \src "ls180.v:2659.32-2659.66" + wire $1\builder_multiregimpl4_regs1[0:0] + attribute \src "ls180.v:2660.32-2660.66" + wire $1\builder_multiregimpl5_regs0[0:0] + attribute \src "ls180.v:2661.32-2661.66" + wire $1\builder_multiregimpl5_regs1[0:0] + attribute \src "ls180.v:2662.32-2662.66" + wire $1\builder_multiregimpl6_regs0[0:0] + attribute \src "ls180.v:2663.32-2663.66" + wire $1\builder_multiregimpl6_regs1[0:0] + attribute \src "ls180.v:2664.32-2664.66" + wire $1\builder_multiregimpl7_regs0[0:0] + attribute \src "ls180.v:2665.32-2665.66" + wire $1\builder_multiregimpl7_regs1[0:0] + attribute \src "ls180.v:2666.32-2666.66" + wire $1\builder_multiregimpl8_regs0[0:0] + attribute \src "ls180.v:2667.32-2667.66" + wire $1\builder_multiregimpl8_regs1[0:0] + attribute \src "ls180.v:2668.32-2668.66" + wire $1\builder_multiregimpl9_regs0[0:0] + attribute \src "ls180.v:2669.32-2669.66" + wire $1\builder_multiregimpl9_regs1[0:0] + attribute \src "ls180.v:1735.5-1735.43" + wire $1\builder_new_master_rdata_valid0[0:0] + attribute \src "ls180.v:1736.5-1736.43" + wire $1\builder_new_master_rdata_valid1[0:0] + attribute \src "ls180.v:1737.5-1737.43" + wire $1\builder_new_master_rdata_valid2[0:0] + attribute \src "ls180.v:1738.5-1738.43" + wire $1\builder_new_master_rdata_valid3[0:0] + attribute \src "ls180.v:1734.5-1734.42" + wire $1\builder_new_master_wdata_ready[0:0] + attribute \src "ls180.v:2540.11-2540.36" + wire width 2 $1\builder_next_state[1:0] + attribute \src "ls180.v:1707.11-1707.46" + wire width 2 $1\builder_refresher_next_state[1:0] + attribute \src "ls180.v:1706.11-1706.41" + wire width 2 $1\builder_refresher_state[1:0] + attribute \src "ls180.v:1812.11-1812.51" + wire width 2 $1\builder_sdblock2memdma_next_state[1:0] + attribute \src "ls180.v:1811.11-1811.46" + wire width 2 $1\builder_sdblock2memdma_state[1:0] + attribute \src "ls180.v:1780.5-1780.57" + wire $1\builder_sdcore_crcupstreaminserter_next_state[0:0] + attribute \src "ls180.v:1779.5-1779.52" + wire $1\builder_sdcore_crcupstreaminserter_state[0:0] + attribute \src "ls180.v:1792.11-1792.47" + wire width 3 $1\builder_sdcore_fsm_next_state[2:0] + attribute \src "ls180.v:1791.11-1791.42" + wire width 3 $1\builder_sdcore_fsm_state[2:0] + attribute \src "ls180.v:1816.5-1816.49" + wire $1\builder_sdmem2blockdma_fsm_next_state[0:0] + attribute \src "ls180.v:1815.5-1815.44" + wire $1\builder_sdmem2blockdma_fsm_state[0:0] + attribute \src "ls180.v:1820.11-1820.65" + wire width 2 $1\builder_sdmem2blockdma_resetinserter_next_state[1:0] + attribute \src "ls180.v:1819.11-1819.60" + wire width 2 $1\builder_sdmem2blockdma_resetinserter_state[1:0] + attribute \src "ls180.v:1768.11-1768.46" + wire width 3 $1\builder_sdphy_fsm_next_state[2:0] + attribute \src "ls180.v:1767.11-1767.41" + wire width 3 $1\builder_sdphy_fsm_state[2:0] + attribute \src "ls180.v:1756.11-1756.52" + wire width 3 $1\builder_sdphy_sdphycmdr_next_state[2:0] + attribute \src "ls180.v:1755.11-1755.47" + wire width 3 $1\builder_sdphy_sdphycmdr_state[2:0] + attribute \src "ls180.v:1752.11-1752.52" + wire width 2 $1\builder_sdphy_sdphycmdw_next_state[1:0] + attribute \src "ls180.v:1751.11-1751.47" + wire width 2 $1\builder_sdphy_sdphycmdw_state[1:0] + attribute \src "ls180.v:1764.5-1764.46" + wire $1\builder_sdphy_sdphycrcr_next_state[0:0] + attribute \src "ls180.v:1763.5-1763.41" + wire $1\builder_sdphy_sdphycrcr_state[0:0] + attribute \src "ls180.v:1772.11-1772.53" + wire width 3 $1\builder_sdphy_sdphydatar_next_state[2:0] + attribute \src "ls180.v:1771.11-1771.48" + wire width 3 $1\builder_sdphy_sdphydatar_state[2:0] + attribute \src "ls180.v:1748.5-1748.46" + wire $1\builder_sdphy_sdphyinit_next_state[0:0] + attribute \src "ls180.v:1747.5-1747.41" + wire $1\builder_sdphy_sdphyinit_state[0:0] + attribute \src "ls180.v:1848.5-1848.30" + wire $1\builder_shared_ack[0:0] + attribute \src "ls180.v:1844.12-1844.40" + wire width 32 $1\builder_shared_dat_r[31:0] + attribute \src "ls180.v:1855.11-1855.35" + wire width 5 $1\builder_slave_sel[4:0] + attribute \src "ls180.v:1856.11-1856.37" + wire width 5 $1\builder_slave_sel_r[4:0] + attribute \src "ls180.v:1744.11-1744.47" + wire width 2 $1\builder_spimaster0_next_state[1:0] + attribute \src "ls180.v:1743.11-1743.42" + wire width 2 $1\builder_spimaster0_state[1:0] + attribute \src "ls180.v:1824.11-1824.47" + wire width 2 $1\builder_spimaster1_next_state[1:0] + attribute \src "ls180.v:1823.11-1823.42" + wire width 2 $1\builder_spimaster1_state[1:0] + attribute \src "ls180.v:2539.11-2539.31" + wire width 2 $1\builder_state[1:0] + attribute \src "ls180.v:2592.5-2592.39" + wire $1\builder_sync_f_array_muxed0[0:0] + attribute \src "ls180.v:2593.5-2593.39" + wire $1\builder_sync_f_array_muxed1[0:0] + attribute \src "ls180.v:2585.11-2585.47" + wire width 2 $1\builder_sync_rhs_array_muxed0[1:0] + attribute \src "ls180.v:2586.12-2586.49" + wire width 13 $1\builder_sync_rhs_array_muxed1[12:0] + attribute \src "ls180.v:2587.5-2587.41" + wire $1\builder_sync_rhs_array_muxed2[0:0] + attribute \src "ls180.v:2588.5-2588.41" + wire $1\builder_sync_rhs_array_muxed3[0:0] + attribute \src "ls180.v:2589.5-2589.41" + wire $1\builder_sync_rhs_array_muxed4[0:0] + attribute \src "ls180.v:2590.5-2590.41" + wire $1\builder_sync_rhs_array_muxed5[0:0] + attribute \src "ls180.v:2591.5-2591.41" + wire $1\builder_sync_rhs_array_muxed6[0:0] + attribute \src "ls180.v:1686.12-1686.44" + wire width 16 $1\libresocsim_clk_divider1[15:0] + attribute \src "ls180.v:1681.5-1681.34" + wire $1\libresocsim_clk_enable[0:0] + attribute \src "ls180.v:1668.5-1668.34" + wire $1\libresocsim_control_re[0:0] + attribute \src "ls180.v:1667.12-1667.47" + wire width 16 $1\libresocsim_control_storage[15:0] + attribute \src "ls180.v:1683.11-1683.35" + wire width 3 $1\libresocsim_count[2:0] + attribute \src "ls180.v:1825.11-1825.57" + wire width 3 $1\libresocsim_count_spimaster1_next_value[2:0] + attribute \src "ls180.v:1826.5-1826.54" + wire $1\libresocsim_count_spimaster1_next_value_ce[0:0] + attribute \src "ls180.v:1682.5-1682.33" + wire $1\libresocsim_cs_enable[0:0] + attribute \src "ls180.v:1678.5-1678.29" + wire $1\libresocsim_cs_re[0:0] + attribute \src "ls180.v:1677.5-1677.34" + wire $1\libresocsim_cs_storage[0:0] + attribute \src "ls180.v:1658.5-1658.29" + wire $1\libresocsim_done0[0:0] + attribute \src "ls180.v:1659.5-1659.27" + wire $1\libresocsim_irq[0:0] + attribute \src "ls180.v:1680.5-1680.35" + wire $1\libresocsim_loopback_re[0:0] + attribute \src "ls180.v:1679.5-1679.40" + wire $1\libresocsim_loopback_storage[0:0] + attribute \src "ls180.v:1661.11-1661.34" + wire width 8 $1\libresocsim_miso[7:0] + attribute \src "ls180.v:1691.11-1691.39" + wire width 8 $1\libresocsim_miso_data[7:0] + attribute \src "ls180.v:1685.5-1685.34" + wire $1\libresocsim_miso_latch[0:0] + attribute \src "ls180.v:1689.11-1689.39" + wire width 8 $1\libresocsim_mosi_data[7:0] + attribute \src "ls180.v:1684.5-1684.34" + wire $1\libresocsim_mosi_latch[0:0] + attribute \src "ls180.v:1673.5-1673.31" + wire $1\libresocsim_mosi_re[0:0] + attribute \src "ls180.v:1690.11-1690.38" + wire width 3 $1\libresocsim_mosi_sel[2:0] + attribute \src "ls180.v:1672.11-1672.42" + wire width 8 $1\libresocsim_mosi_storage[7:0] + attribute \src "ls180.v:1693.5-1693.26" + wire $1\libresocsim_re[0:0] + attribute \src "ls180.v:1665.5-1665.30" + wire $1\libresocsim_start1[0:0] + attribute \src "ls180.v:1692.12-1692.41" + wire width 16 $1\libresocsim_storage[15:0] + attribute \src "ls180.v:804.5-804.29" + wire $1\main_cmd_consumed[0:0] + attribute \src "ls180.v:801.5-801.34" + wire $1\main_converter_counter[0:0] + attribute \src "ls180.v:1741.5-1741.55" + wire $1\main_converter_counter_converter_next_value[0:0] + attribute \src "ls180.v:1742.5-1742.58" + wire $1\main_converter_counter_converter_next_value_ce[0:0] + attribute \src "ls180.v:803.12-803.40" + wire width 32 $1\main_converter_dat_r[31:0] + attribute \src "ls180.v:800.5-800.31" + wire $1\main_converter_skip[0:0] + attribute \src "ls180.v:235.12-235.38" + wire width 16 $1\main_dfi_p0_rddata[15:0] + attribute \src "ls180.v:236.5-236.36" + wire $1\main_dfi_p0_rddata_valid[0:0] + attribute \src "ls180.v:997.12-997.30" + wire width 42 $1\main_dummy[41:0] + attribute \src "ls180.v:952.5-952.27" + wire $1\main_gpio_oe_re[0:0] + attribute \src "ls180.v:951.12-951.40" + wire width 16 $1\main_gpio_oe_storage[15:0] + attribute \src "ls180.v:956.5-956.28" + wire $1\main_gpio_out_re[0:0] + attribute \src "ls180.v:955.12-955.41" + wire width 16 $1\main_gpio_out_storage[15:0] + attribute \src "ls180.v:953.12-953.36" + wire width 16 $1\main_gpio_status[15:0] + attribute \src "ls180.v:220.5-220.24" + wire $1\main_int_rst[0:0] + attribute \src "ls180.v:1562.12-1562.43" + wire width 32 $1\main_interface1_bus_adr[31:0] + attribute \src "ls180.v:1566.5-1566.35" + wire $1\main_interface1_bus_cyc[0:0] + attribute \src "ls180.v:1565.11-1565.41" + wire width 4 $1\main_interface1_bus_sel[3:0] + attribute \src "ls180.v:1567.5-1567.35" + wire $1\main_interface1_bus_stb[0:0] + attribute \src "ls180.v:1569.5-1569.34" + wire $1\main_interface1_bus_we[0:0] + attribute \src "ls180.v:57.12-57.47" + wire width 32 $1\main_libresocsim_bus_errors[31:0] + attribute \src "ls180.v:142.5-142.47" + wire $1\main_libresocsim_converter0_counter[0:0] + attribute \src "ls180.v:1696.5-1696.69" + wire $1\main_libresocsim_converter0_counter_converter0_next_value[0:0] + attribute \src "ls180.v:1697.5-1697.72" + wire $1\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0] + attribute \src "ls180.v:144.12-144.53" + wire width 64 $1\main_libresocsim_converter0_dat_r[63:0] + attribute \src "ls180.v:141.5-141.44" + wire $1\main_libresocsim_converter0_skip[0:0] + attribute \src "ls180.v:157.5-157.47" + wire $1\main_libresocsim_converter1_counter[0:0] + attribute \src "ls180.v:1700.5-1700.69" + wire $1\main_libresocsim_converter1_counter_converter1_next_value[0:0] + attribute \src "ls180.v:1701.5-1701.72" + wire $1\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0] + attribute \src "ls180.v:159.12-159.53" + wire width 64 $1\main_libresocsim_converter1_dat_r[63:0] + attribute \src "ls180.v:156.5-156.44" + wire $1\main_libresocsim_converter1_skip[0:0] + attribute \src "ls180.v:172.5-172.47" + wire $1\main_libresocsim_converter2_counter[0:0] + attribute \src "ls180.v:1704.5-1704.69" + wire $1\main_libresocsim_converter2_counter_converter2_next_value[0:0] + attribute \src "ls180.v:1705.5-1705.72" + wire $1\main_libresocsim_converter2_counter_converter2_next_value_ce[0:0] + attribute \src "ls180.v:174.12-174.53" + wire width 64 $1\main_libresocsim_converter2_dat_r[63:0] + attribute \src "ls180.v:171.5-171.44" + wire $1\main_libresocsim_converter2_skip[0:0] + attribute \src "ls180.v:195.5-195.34" + wire $1\main_libresocsim_en_re[0:0] + attribute \src "ls180.v:194.5-194.39" + wire $1\main_libresocsim_en_storage[0:0] + attribute \src "ls180.v:215.5-215.44" + wire $1\main_libresocsim_eventmanager_re[0:0] + attribute \src "ls180.v:214.5-214.49" + wire $1\main_libresocsim_eventmanager_storage[0:0] + attribute \src "ls180.v:130.12-130.71" + wire width 30 $1\main_libresocsim_interface0_converted_interface_adr[29:0] + attribute \src "ls180.v:134.5-134.63" + wire $1\main_libresocsim_interface0_converted_interface_cyc[0:0] + attribute \src "ls180.v:131.12-131.73" + wire width 32 $1\main_libresocsim_interface0_converted_interface_dat_w[31:0] + attribute \src "ls180.v:133.11-133.69" + wire width 4 $1\main_libresocsim_interface0_converted_interface_sel[3:0] + attribute \src "ls180.v:135.5-135.63" + wire $1\main_libresocsim_interface0_converted_interface_stb[0:0] + attribute \src "ls180.v:137.5-137.62" + wire $1\main_libresocsim_interface0_converted_interface_we[0:0] + attribute \src "ls180.v:145.12-145.71" + wire width 30 $1\main_libresocsim_interface1_converted_interface_adr[29:0] + attribute \src "ls180.v:149.5-149.63" + wire $1\main_libresocsim_interface1_converted_interface_cyc[0:0] + attribute \src "ls180.v:146.12-146.73" + wire width 32 $1\main_libresocsim_interface1_converted_interface_dat_w[31:0] + attribute \src "ls180.v:148.11-148.69" + wire width 4 $1\main_libresocsim_interface1_converted_interface_sel[3:0] + attribute \src "ls180.v:150.5-150.63" + wire $1\main_libresocsim_interface1_converted_interface_stb[0:0] + attribute \src "ls180.v:152.5-152.62" + wire $1\main_libresocsim_interface1_converted_interface_we[0:0] + attribute \src "ls180.v:160.12-160.71" + wire width 30 $1\main_libresocsim_interface2_converted_interface_adr[29:0] + attribute \src "ls180.v:164.5-164.63" + wire $1\main_libresocsim_interface2_converted_interface_cyc[0:0] + attribute \src "ls180.v:161.12-161.73" + wire width 32 $1\main_libresocsim_interface2_converted_interface_dat_w[31:0] + attribute \src "ls180.v:163.11-163.69" + wire width 4 $1\main_libresocsim_interface2_converted_interface_sel[3:0] + attribute \src "ls180.v:165.5-165.63" + wire $1\main_libresocsim_interface2_converted_interface_stb[0:0] + attribute \src "ls180.v:167.5-167.62" + wire $1\main_libresocsim_interface2_converted_interface_we[0:0] + attribute \src "ls180.v:120.5-120.65" + wire $1\main_libresocsim_libresoc_constraintmanager0_uart0_tx[0:0] + attribute \src "ls180.v:66.5-66.46" + wire $1\main_libresocsim_libresoc_dbus_ack[0:0] + attribute \src "ls180.v:77.5-77.46" + wire $1\main_libresocsim_libresoc_ibus_ack[0:0] + attribute \src "ls180.v:59.12-59.55" + wire width 16 $1\main_libresocsim_libresoc_interrupt[15:0] + attribute \src "ls180.v:110.5-110.49" + wire $1\main_libresocsim_libresoc_jtag_wb_ack[0:0] + attribute \src "ls180.v:191.5-191.36" + wire $1\main_libresocsim_load_re[0:0] + attribute \src "ls180.v:190.12-190.49" + wire width 32 $1\main_libresocsim_load_storage[31:0] + attribute \src "ls180.v:181.5-181.40" + wire $1\main_libresocsim_ram_bus_ack[0:0] + attribute \src "ls180.v:193.5-193.38" + wire $1\main_libresocsim_reload_re[0:0] + attribute \src "ls180.v:192.12-192.51" + wire width 32 $1\main_libresocsim_reload_storage[31:0] + attribute \src "ls180.v:50.5-50.37" + wire $1\main_libresocsim_reset_re[0:0] + attribute \src "ls180.v:49.5-49.42" + wire $1\main_libresocsim_reset_storage[0:0] + attribute \src "ls180.v:52.5-52.39" + wire $1\main_libresocsim_scratch_re[0:0] + attribute \src "ls180.v:51.12-51.60" + wire width 32 $1\main_libresocsim_scratch_storage[31:0] + attribute \src "ls180.v:197.5-197.44" + wire $1\main_libresocsim_update_value_re[0:0] + attribute \src "ls180.v:196.5-196.49" + wire $1\main_libresocsim_update_value_storage[0:0] + attribute \src "ls180.v:216.12-216.42" + wire width 32 $1\main_libresocsim_value[31:0] + attribute \src "ls180.v:198.12-198.49" + wire width 32 $1\main_libresocsim_value_status[31:0] + attribute \src "ls180.v:188.11-188.37" + wire width 4 $1\main_libresocsim_we[3:0] + attribute \src "ls180.v:204.5-204.39" + wire $1\main_libresocsim_zero_clear[0:0] + attribute \src "ls180.v:205.5-205.45" + wire $1\main_libresocsim_zero_old_trigger[0:0] + attribute \src "ls180.v:202.5-202.41" + wire $1\main_libresocsim_zero_pending[0:0] + attribute \src "ls180.v:792.12-792.40" + wire width 30 $1\main_litedram_wb_adr[29:0] + attribute \src "ls180.v:796.5-796.32" + wire $1\main_litedram_wb_cyc[0:0] + attribute \src "ls180.v:793.12-793.42" + wire width 16 $1\main_litedram_wb_dat_w[15:0] + attribute \src "ls180.v:795.11-795.38" + wire width 2 $1\main_litedram_wb_sel[1:0] + attribute \src "ls180.v:797.5-797.32" + wire $1\main_litedram_wb_stb[0:0] + attribute \src "ls180.v:799.5-799.31" + wire $1\main_litedram_wb_we[0:0] + attribute \src "ls180.v:827.12-827.45" + wire width 32 $1\main_phase_accumulator_rx[31:0] + attribute \src "ls180.v:817.12-817.45" + wire width 32 $1\main_phase_accumulator_tx[31:0] + attribute \src "ls180.v:1001.12-1001.37" + wire width 32 $1\main_pwm0_counter[31:0] + attribute \src "ls180.v:1003.5-1003.31" + wire $1\main_pwm0_enable_re[0:0] + attribute \src "ls180.v:1002.5-1002.36" + wire $1\main_pwm0_enable_storage[0:0] + attribute \src "ls180.v:1007.5-1007.31" + wire $1\main_pwm0_period_re[0:0] + attribute \src "ls180.v:1006.12-1006.44" + wire width 32 $1\main_pwm0_period_storage[31:0] + attribute \src "ls180.v:1005.5-1005.30" + wire $1\main_pwm0_width_re[0:0] + attribute \src "ls180.v:1004.12-1004.43" + wire width 32 $1\main_pwm0_width_storage[31:0] + attribute \src "ls180.v:1011.12-1011.37" + wire width 32 $1\main_pwm1_counter[31:0] + attribute \src "ls180.v:1013.5-1013.31" + wire $1\main_pwm1_enable_re[0:0] + attribute \src "ls180.v:1012.5-1012.36" + wire $1\main_pwm1_enable_storage[0:0] + attribute \src "ls180.v:1017.5-1017.31" + wire $1\main_pwm1_period_re[0:0] + attribute \src "ls180.v:1016.12-1016.44" + wire width 32 $1\main_pwm1_period_storage[31:0] + attribute \src "ls180.v:1015.5-1015.30" + wire $1\main_pwm1_width_re[0:0] + attribute \src "ls180.v:1014.12-1014.43" + wire width 32 $1\main_pwm1_width_storage[31:0] + attribute \src "ls180.v:237.11-237.32" + wire width 3 $1\main_rddata_en[2:0] + attribute \src "ls180.v:810.5-810.19" + wire $1\main_re[0:0] + attribute \src "ls180.v:831.11-831.34" + wire width 4 $1\main_rx_bitcount[3:0] + attribute \src "ls180.v:832.5-832.24" + wire $1\main_rx_busy[0:0] + attribute \src "ls180.v:829.5-829.21" + wire $1\main_rx_r[0:0] + attribute \src "ls180.v:830.11-830.29" + wire width 8 $1\main_rx_reg[7:0] + attribute \src "ls180.v:1531.11-1531.50" + wire width 2 $1\main_sdblock2mem_converter_demux[1:0] + attribute \src "ls180.v:1527.5-1527.51" + wire $1\main_sdblock2mem_converter_source_first[0:0] + attribute \src "ls180.v:1528.5-1528.50" + wire $1\main_sdblock2mem_converter_source_last[0:0] + attribute \src "ls180.v:1529.12-1529.66" + wire width 32 $1\main_sdblock2mem_converter_source_payload_data[31:0] + attribute \src "ls180.v:1530.11-1530.77" + wire width 3 $1\main_sdblock2mem_converter_source_payload_valid_token_count[2:0] + attribute \src "ls180.v:1533.5-1533.49" + wire $1\main_sdblock2mem_converter_strobe_all[0:0] + attribute \src "ls180.v:1506.11-1506.47" + wire width 5 $1\main_sdblock2mem_fifo_consume[4:0] + attribute \src "ls180.v:1503.11-1503.45" + wire width 6 $1\main_sdblock2mem_fifo_level[5:0] + attribute \src "ls180.v:1505.11-1505.47" + wire width 5 $1\main_sdblock2mem_fifo_produce[4:0] + attribute \src "ls180.v:1507.11-1507.50" + wire width 5 $1\main_sdblock2mem_fifo_wrport_adr[4:0] + attribute \src "ls180.v:1541.12-1541.62" + wire width 32 $1\main_sdblock2mem_sink_sink_payload_address[31:0] + attribute \src "ls180.v:1542.12-1542.60" + wire width 32 $1\main_sdblock2mem_sink_sink_payload_data1[31:0] + attribute \src "ls180.v:1539.5-1539.45" + wire $1\main_sdblock2mem_sink_sink_valid1[0:0] + attribute \src "ls180.v:1549.5-1549.54" + wire $1\main_sdblock2mem_wishbonedmawriter_base_re[0:0] + attribute \src "ls180.v:1548.12-1548.67" + wire width 64 $1\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] + attribute \src "ls180.v:1553.5-1553.56" + wire $1\main_sdblock2mem_wishbonedmawriter_enable_re[0:0] + attribute \src "ls180.v:1552.5-1552.61" + wire $1\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] + attribute \src "ls180.v:1551.5-1551.56" + wire $1\main_sdblock2mem_wishbonedmawriter_length_re[0:0] + attribute \src "ls180.v:1550.12-1550.69" + wire width 32 $1\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] + attribute \src "ls180.v:1557.5-1557.54" + wire $1\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] + attribute \src "ls180.v:1556.5-1556.59" + wire $1\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] + attribute \src "ls180.v:1559.12-1559.61" + wire width 32 $1\main_sdblock2mem_wishbonedmawriter_offset[31:0] + attribute \src "ls180.v:1813.12-1813.87" + wire width 32 $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] + attribute \src "ls180.v:1814.5-1814.82" + wire $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] + attribute \src "ls180.v:1544.5-1544.57" + wire $1\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] + attribute \src "ls180.v:1554.5-1554.53" + wire $1\main_sdblock2mem_wishbonedmawriter_status[0:0] + attribute \src "ls180.v:1323.5-1323.38" + wire $1\main_sdcore_block_count_re[0:0] + attribute \src "ls180.v:1322.12-1322.51" + wire width 32 $1\main_sdcore_block_count_storage[31:0] + attribute \src "ls180.v:1321.5-1321.39" + wire $1\main_sdcore_block_length_re[0:0] + attribute \src "ls180.v:1320.11-1320.51" + wire width 10 $1\main_sdcore_block_length_storage[9:0] + attribute \src "ls180.v:1307.5-1307.39" + wire $1\main_sdcore_cmd_argument_re[0:0] + attribute \src "ls180.v:1306.12-1306.52" + wire width 32 $1\main_sdcore_cmd_argument_storage[31:0] + attribute \src "ls180.v:1309.5-1309.38" + wire $1\main_sdcore_cmd_command_re[0:0] + attribute \src "ls180.v:1308.12-1308.51" + wire width 32 $1\main_sdcore_cmd_command_storage[31:0] + attribute \src "ls180.v:1462.11-1462.39" + wire width 3 $1\main_sdcore_cmd_count[2:0] + attribute \src "ls180.v:1797.11-1797.62" + wire width 3 $1\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] + attribute \src "ls180.v:1798.5-1798.59" + wire $1\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] + attribute \src "ls180.v:1463.5-1463.32" + wire $1\main_sdcore_cmd_done[0:0] + attribute \src "ls180.v:1793.5-1793.55" + wire $1\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] + attribute \src "ls180.v:1794.5-1794.58" + wire $1\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] + attribute \src "ls180.v:1464.5-1464.33" + wire $1\main_sdcore_cmd_error[0:0] + attribute \src "ls180.v:1801.5-1801.56" + wire $1\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] + attribute \src "ls180.v:1802.5-1802.59" + wire $1\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] + attribute \src "ls180.v:1314.13-1314.53" + wire width 128 $1\main_sdcore_cmd_response_status[127:0] + attribute \src "ls180.v:1809.13-1809.76" + wire width 128 $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] + attribute \src "ls180.v:1810.5-1810.69" + wire $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] + attribute \src "ls180.v:1465.5-1465.35" + wire $1\main_sdcore_cmd_timeout[0:0] + attribute \src "ls180.v:1803.5-1803.58" + wire $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] + attribute \src "ls180.v:1804.5-1804.61" + wire $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] + attribute \src "ls180.v:1423.11-1423.47" + wire width 4 $1\main_sdcore_crc16_checker_cnt[3:0] + attribute \src "ls180.v:1429.5-1429.46" + wire $1\main_sdcore_crc16_checker_crc0_clr[0:0] + attribute \src "ls180.v:1428.12-1428.54" + wire width 16 $1\main_sdcore_crc16_checker_crc0_crc[15:0] + attribute \src "ls180.v:1424.12-1424.58" + wire width 16 $1\main_sdcore_crc16_checker_crc0_crcreg0[15:0] + attribute \src "ls180.v:1436.5-1436.46" + wire $1\main_sdcore_crc16_checker_crc1_clr[0:0] + attribute \src "ls180.v:1435.12-1435.54" + wire width 16 $1\main_sdcore_crc16_checker_crc1_crc[15:0] + attribute \src "ls180.v:1431.12-1431.58" + wire width 16 $1\main_sdcore_crc16_checker_crc1_crcreg0[15:0] + attribute \src "ls180.v:1443.5-1443.46" + wire $1\main_sdcore_crc16_checker_crc2_clr[0:0] + attribute \src "ls180.v:1442.12-1442.54" + wire width 16 $1\main_sdcore_crc16_checker_crc2_crc[15:0] + attribute \src "ls180.v:1438.12-1438.58" + wire width 16 $1\main_sdcore_crc16_checker_crc2_crcreg0[15:0] + attribute \src "ls180.v:1450.5-1450.46" + wire $1\main_sdcore_crc16_checker_crc3_clr[0:0] + attribute \src "ls180.v:1449.12-1449.54" + wire width 16 $1\main_sdcore_crc16_checker_crc3_crc[15:0] + attribute \src "ls180.v:1445.12-1445.58" + wire width 16 $1\main_sdcore_crc16_checker_crc3_crcreg0[15:0] + attribute \src "ls180.v:1452.12-1452.53" + wire width 16 $1\main_sdcore_crc16_checker_crctmp0[15:0] + attribute \src "ls180.v:1453.12-1453.53" + wire width 16 $1\main_sdcore_crc16_checker_crctmp1[15:0] + attribute \src "ls180.v:1454.12-1454.53" + wire width 16 $1\main_sdcore_crc16_checker_crctmp2[15:0] + attribute \src "ls180.v:1455.12-1455.53" + wire width 16 $1\main_sdcore_crc16_checker_crctmp3[15:0] + attribute \src "ls180.v:1457.12-1457.51" + wire width 16 $1\main_sdcore_crc16_checker_fifo0[15:0] + attribute \src "ls180.v:1458.12-1458.51" + wire width 16 $1\main_sdcore_crc16_checker_fifo1[15:0] + attribute \src "ls180.v:1459.12-1459.51" + wire width 16 $1\main_sdcore_crc16_checker_fifo2[15:0] + attribute \src "ls180.v:1460.12-1460.51" + wire width 16 $1\main_sdcore_crc16_checker_fifo3[15:0] + attribute \src "ls180.v:1414.5-1414.48" + wire $1\main_sdcore_crc16_checker_sink_first[0:0] + attribute \src "ls180.v:1415.5-1415.47" + wire $1\main_sdcore_crc16_checker_sink_last[0:0] + attribute \src "ls180.v:1416.11-1416.61" + wire width 8 $1\main_sdcore_crc16_checker_sink_payload_data[7:0] + attribute \src "ls180.v:1413.5-1413.48" + wire $1\main_sdcore_crc16_checker_sink_ready[0:0] + attribute \src "ls180.v:1412.5-1412.48" + wire $1\main_sdcore_crc16_checker_sink_valid[0:0] + attribute \src "ls180.v:1417.5-1417.50" + wire $1\main_sdcore_crc16_checker_source_valid[0:0] + attribute \src "ls180.v:1422.11-1422.47" + wire width 8 $1\main_sdcore_crc16_checker_val[7:0] + attribute \src "ls180.v:1456.5-1456.43" + wire $1\main_sdcore_crc16_checker_valid[0:0] + attribute \src "ls180.v:1379.11-1379.48" + wire width 3 $1\main_sdcore_crc16_inserter_cnt[2:0] + attribute \src "ls180.v:1789.11-1789.87" + wire width 3 $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] + attribute \src "ls180.v:1790.5-1790.84" + wire $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] + attribute \src "ls180.v:1384.12-1384.55" + wire width 16 $1\main_sdcore_crc16_inserter_crc0_crc[15:0] + attribute \src "ls180.v:1380.12-1380.59" + wire width 16 $1\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] + attribute \src "ls180.v:1391.12-1391.55" + wire width 16 $1\main_sdcore_crc16_inserter_crc1_crc[15:0] + attribute \src "ls180.v:1387.12-1387.59" + wire width 16 $1\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] + attribute \src "ls180.v:1398.12-1398.55" + wire width 16 $1\main_sdcore_crc16_inserter_crc2_crc[15:0] + attribute \src "ls180.v:1394.12-1394.59" + wire width 16 $1\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] + attribute \src "ls180.v:1405.12-1405.55" + wire width 16 $1\main_sdcore_crc16_inserter_crc3_crc[15:0] + attribute \src "ls180.v:1401.12-1401.59" + wire width 16 $1\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] + attribute \src "ls180.v:1408.12-1408.54" + wire width 16 $1\main_sdcore_crc16_inserter_crctmp0[15:0] + attribute \src "ls180.v:1781.12-1781.93" + wire width 16 $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] + attribute \src "ls180.v:1782.5-1782.88" + wire $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] + attribute \src "ls180.v:1409.12-1409.54" + wire width 16 $1\main_sdcore_crc16_inserter_crctmp1[15:0] + attribute \src "ls180.v:1783.12-1783.93" + wire width 16 $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] + attribute \src "ls180.v:1784.5-1784.88" + wire $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] + attribute \src "ls180.v:1410.12-1410.54" + wire width 16 $1\main_sdcore_crc16_inserter_crctmp2[15:0] + attribute \src "ls180.v:1785.12-1785.93" + wire width 16 $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] + attribute \src "ls180.v:1786.5-1786.88" + wire $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] + attribute \src "ls180.v:1411.12-1411.54" + wire width 16 $1\main_sdcore_crc16_inserter_crctmp3[15:0] + attribute \src "ls180.v:1787.12-1787.93" + wire width 16 $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] + attribute \src "ls180.v:1788.5-1788.88" + wire $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] + attribute \src "ls180.v:1370.5-1370.49" + wire $1\main_sdcore_crc16_inserter_sink_ready[0:0] + attribute \src "ls180.v:1377.5-1377.50" + wire $1\main_sdcore_crc16_inserter_source_last[0:0] + attribute \src "ls180.v:1378.11-1378.64" + wire width 8 $1\main_sdcore_crc16_inserter_source_payload_data[7:0] + attribute \src "ls180.v:1375.5-1375.51" + wire $1\main_sdcore_crc16_inserter_source_ready[0:0] + attribute \src "ls180.v:1374.5-1374.51" + wire $1\main_sdcore_crc16_inserter_source_valid[0:0] + attribute \src "ls180.v:1366.11-1366.47" + wire width 7 $1\main_sdcore_crc7_inserter_crc[6:0] + attribute \src "ls180.v:1324.11-1324.51" + wire width 7 $1\main_sdcore_crc7_inserter_crcreg0[6:0] + attribute \src "ls180.v:1467.12-1467.42" + wire width 32 $1\main_sdcore_data_count[31:0] + attribute \src "ls180.v:1799.12-1799.65" + wire width 32 $1\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] + attribute \src "ls180.v:1800.5-1800.60" + wire $1\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] + attribute \src "ls180.v:1468.5-1468.33" + wire $1\main_sdcore_data_done[0:0] + attribute \src "ls180.v:1795.5-1795.56" + wire $1\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] + attribute \src "ls180.v:1796.5-1796.59" + wire $1\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] + attribute \src "ls180.v:1469.5-1469.34" + wire $1\main_sdcore_data_error[0:0] + attribute \src "ls180.v:1805.5-1805.57" + wire $1\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] + attribute \src "ls180.v:1806.5-1806.60" + wire $1\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] + attribute \src "ls180.v:1470.5-1470.36" + wire $1\main_sdcore_data_timeout[0:0] + attribute \src "ls180.v:1807.5-1807.59" + wire $1\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] + attribute \src "ls180.v:1808.5-1808.62" + wire $1\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] + attribute \src "ls180.v:1615.11-1615.48" + wire width 2 $1\main_sdmem2block_converter_mux[1:0] + attribute \src "ls180.v:1613.11-1613.64" + wire width 8 $1\main_sdmem2block_converter_source_payload_data[7:0] + attribute \src "ls180.v:1589.5-1589.40" + wire $1\main_sdmem2block_dma_base_re[0:0] + attribute \src "ls180.v:1588.12-1588.53" + wire width 64 $1\main_sdmem2block_dma_base_storage[63:0] + attribute \src "ls180.v:1587.12-1587.45" + wire width 32 $1\main_sdmem2block_dma_data[31:0] + attribute \src "ls180.v:1817.12-1817.75" + wire width 32 $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[31:0] + attribute \src "ls180.v:1818.5-1818.70" + wire $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] + attribute \src "ls180.v:1594.5-1594.44" + wire $1\main_sdmem2block_dma_done_status[0:0] + attribute \src "ls180.v:1593.5-1593.42" + wire $1\main_sdmem2block_dma_enable_re[0:0] + attribute \src "ls180.v:1592.5-1592.47" + wire $1\main_sdmem2block_dma_enable_storage[0:0] + attribute \src "ls180.v:1591.5-1591.42" + wire $1\main_sdmem2block_dma_length_re[0:0] + attribute \src "ls180.v:1590.12-1590.55" + wire width 32 $1\main_sdmem2block_dma_length_storage[31:0] + attribute \src "ls180.v:1597.5-1597.40" + wire $1\main_sdmem2block_dma_loop_re[0:0] + attribute \src "ls180.v:1596.5-1596.45" + wire $1\main_sdmem2block_dma_loop_storage[0:0] + attribute \src "ls180.v:1601.12-1601.47" + wire width 32 $1\main_sdmem2block_dma_offset[31:0] + attribute \src "ls180.v:1821.12-1821.87" + wire width 32 $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] + attribute \src "ls180.v:1822.5-1822.82" + wire $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] + attribute \src "ls180.v:1580.5-1580.42" + wire $1\main_sdmem2block_dma_sink_last[0:0] + attribute \src "ls180.v:1581.12-1581.61" + wire width 32 $1\main_sdmem2block_dma_sink_payload_address[31:0] + attribute \src "ls180.v:1579.5-1579.43" + wire $1\main_sdmem2block_dma_sink_ready[0:0] + attribute \src "ls180.v:1578.5-1578.43" + wire $1\main_sdmem2block_dma_sink_valid[0:0] + attribute \src "ls180.v:1585.5-1585.44" + wire $1\main_sdmem2block_dma_source_last[0:0] + attribute \src "ls180.v:1586.12-1586.60" + wire width 32 $1\main_sdmem2block_dma_source_payload_data[31:0] + attribute \src "ls180.v:1582.5-1582.45" + wire $1\main_sdmem2block_dma_source_valid[0:0] + attribute \src "ls180.v:1642.11-1642.47" + wire width 5 $1\main_sdmem2block_fifo_consume[4:0] + attribute \src "ls180.v:1639.11-1639.45" + wire width 6 $1\main_sdmem2block_fifo_level[5:0] + attribute \src "ls180.v:1641.11-1641.47" + wire width 5 $1\main_sdmem2block_fifo_produce[4:0] + attribute \src "ls180.v:1643.11-1643.50" + wire width 5 $1\main_sdmem2block_fifo_wrport_adr[4:0] + attribute \src "ls180.v:1023.5-1023.35" + wire $1\main_sdphy_clocker_clk0[0:0] + attribute \src "ls180.v:1026.5-1026.35" + wire $1\main_sdphy_clocker_clk1[0:0] + attribute \src "ls180.v:1027.5-1027.36" + wire $1\main_sdphy_clocker_clk_d[0:0] + attribute \src "ls180.v:1025.11-1025.41" + wire width 9 $1\main_sdphy_clocker_clks[8:0] + attribute \src "ls180.v:1021.5-1021.33" + wire $1\main_sdphy_clocker_re[0:0] + attribute \src "ls180.v:1020.11-1020.46" + wire width 9 $1\main_sdphy_clocker_storage[8:0] + attribute \src "ls180.v:1129.5-1129.49" + wire $1\main_sdphy_cmdr_cmdr_buf_source_first[0:0] + attribute \src "ls180.v:1130.5-1130.48" + wire $1\main_sdphy_cmdr_cmdr_buf_source_last[0:0] + attribute \src "ls180.v:1131.11-1131.62" + wire width 8 $1\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] + attribute \src "ls180.v:1127.5-1127.49" + wire $1\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] + attribute \src "ls180.v:1114.11-1114.54" + wire width 3 $1\main_sdphy_cmdr_cmdr_converter_demux[2:0] + attribute \src "ls180.v:1110.5-1110.55" + wire $1\main_sdphy_cmdr_cmdr_converter_source_first[0:0] + attribute \src "ls180.v:1111.5-1111.54" + wire $1\main_sdphy_cmdr_cmdr_converter_source_last[0:0] + attribute \src "ls180.v:1112.11-1112.68" + wire width 8 $1\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] + attribute \src "ls180.v:1113.11-1113.81" + wire width 4 $1\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] + attribute \src "ls180.v:1116.5-1116.53" + wire $1\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] + attribute \src "ls180.v:1132.5-1132.38" + wire $1\main_sdphy_cmdr_cmdr_reset[0:0] + attribute \src "ls180.v:1761.5-1761.66" + wire $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] + attribute \src "ls180.v:1762.5-1762.69" + wire $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] + attribute \src "ls180.v:1102.5-1102.36" + wire $1\main_sdphy_cmdr_cmdr_run[0:0] + attribute \src "ls180.v:1097.5-1097.53" + wire $1\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] + attribute \src "ls180.v:1084.11-1084.39" + wire width 8 $1\main_sdphy_cmdr_count[7:0] + attribute \src "ls180.v:1757.11-1757.67" + wire width 8 $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] + attribute \src "ls180.v:1758.5-1758.64" + wire $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] + attribute \src "ls180.v:1069.5-1069.48" + wire $1\main_sdphy_cmdr_pads_out_payload_clk[0:0] + attribute \src "ls180.v:1070.5-1070.50" + wire $1\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] + attribute \src "ls180.v:1071.5-1071.51" + wire $1\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] + attribute \src "ls180.v:1076.5-1076.37" + wire $1\main_sdphy_cmdr_sink_last[0:0] + attribute \src "ls180.v:1077.11-1077.53" + wire width 8 $1\main_sdphy_cmdr_sink_payload_length[7:0] + attribute \src "ls180.v:1075.5-1075.38" + wire $1\main_sdphy_cmdr_sink_ready[0:0] + attribute \src "ls180.v:1074.5-1074.38" + wire $1\main_sdphy_cmdr_sink_valid[0:0] + attribute \src "ls180.v:1080.5-1080.39" + wire $1\main_sdphy_cmdr_source_last[0:0] + attribute \src "ls180.v:1081.11-1081.53" + wire width 8 $1\main_sdphy_cmdr_source_payload_data[7:0] + attribute \src "ls180.v:1082.11-1082.55" + wire width 3 $1\main_sdphy_cmdr_source_payload_status[2:0] + attribute \src "ls180.v:1079.5-1079.40" + wire $1\main_sdphy_cmdr_source_ready[0:0] + attribute \src "ls180.v:1078.5-1078.40" + wire $1\main_sdphy_cmdr_source_valid[0:0] + attribute \src "ls180.v:1083.12-1083.48" + wire width 32 $1\main_sdphy_cmdr_timeout[31:0] + attribute \src "ls180.v:1759.12-1759.71" + wire width 32 $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] + attribute \src "ls180.v:1760.5-1760.66" + wire $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] + attribute \src "ls180.v:1056.11-1056.39" + wire width 8 $1\main_sdphy_cmdw_count[7:0] + attribute \src "ls180.v:1753.11-1753.66" + wire width 8 $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] + attribute \src "ls180.v:1754.5-1754.63" + wire $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] + attribute \src "ls180.v:1055.5-1055.32" + wire $1\main_sdphy_cmdw_done[0:0] + attribute \src "ls180.v:1046.5-1046.48" + wire $1\main_sdphy_cmdw_pads_out_payload_clk[0:0] + attribute \src "ls180.v:1047.5-1047.50" + wire $1\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] + attribute \src "ls180.v:1048.5-1048.51" + wire $1\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] + attribute \src "ls180.v:1053.5-1053.37" + wire $1\main_sdphy_cmdw_sink_last[0:0] + attribute \src "ls180.v:1054.11-1054.51" + wire width 8 $1\main_sdphy_cmdw_sink_payload_data[7:0] + attribute \src "ls180.v:1052.5-1052.38" + wire $1\main_sdphy_cmdw_sink_ready[0:0] + attribute \src "ls180.v:1051.5-1051.38" + wire $1\main_sdphy_cmdw_sink_valid[0:0] + attribute \src "ls180.v:1240.11-1240.41" + wire width 10 $1\main_sdphy_datar_count[9:0] + attribute \src "ls180.v:1773.11-1773.70" + wire width 10 $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] + attribute \src "ls180.v:1774.5-1774.66" + wire $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] + attribute \src "ls180.v:1285.5-1285.51" + wire $1\main_sdphy_datar_datar_buf_source_first[0:0] + attribute \src "ls180.v:1286.5-1286.50" + wire $1\main_sdphy_datar_datar_buf_source_last[0:0] + attribute \src "ls180.v:1287.11-1287.64" + wire width 8 $1\main_sdphy_datar_datar_buf_source_payload_data[7:0] + attribute \src "ls180.v:1283.5-1283.51" + wire $1\main_sdphy_datar_datar_buf_source_valid[0:0] + attribute \src "ls180.v:1270.5-1270.50" + wire $1\main_sdphy_datar_datar_converter_demux[0:0] + attribute \src "ls180.v:1266.5-1266.57" + wire $1\main_sdphy_datar_datar_converter_source_first[0:0] + attribute \src "ls180.v:1267.5-1267.56" + wire $1\main_sdphy_datar_datar_converter_source_last[0:0] + attribute \src "ls180.v:1268.11-1268.70" + wire width 8 $1\main_sdphy_datar_datar_converter_source_payload_data[7:0] + attribute \src "ls180.v:1269.11-1269.83" + wire width 2 $1\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] + attribute \src "ls180.v:1272.5-1272.55" + wire $1\main_sdphy_datar_datar_converter_strobe_all[0:0] + attribute \src "ls180.v:1288.5-1288.40" + wire $1\main_sdphy_datar_datar_reset[0:0] + attribute \src "ls180.v:1777.5-1777.69" + wire $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] + attribute \src "ls180.v:1778.5-1778.72" + wire $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] + attribute \src "ls180.v:1258.5-1258.38" + wire $1\main_sdphy_datar_datar_run[0:0] + attribute \src "ls180.v:1253.5-1253.55" + wire $1\main_sdphy_datar_datar_source_source_ready0[0:0] + attribute \src "ls180.v:1223.5-1223.49" + wire $1\main_sdphy_datar_pads_out_payload_clk[0:0] + attribute \src "ls180.v:1230.5-1230.38" + wire $1\main_sdphy_datar_sink_last[0:0] + attribute \src "ls180.v:1231.11-1231.61" + wire width 10 $1\main_sdphy_datar_sink_payload_block_length[9:0] + attribute \src "ls180.v:1229.5-1229.39" + wire $1\main_sdphy_datar_sink_ready[0:0] + attribute \src "ls180.v:1228.5-1228.39" + wire $1\main_sdphy_datar_sink_valid[0:0] + attribute \src "ls180.v:1235.5-1235.40" + wire $1\main_sdphy_datar_source_last[0:0] + attribute \src "ls180.v:1236.11-1236.54" + wire width 8 $1\main_sdphy_datar_source_payload_data[7:0] + attribute \src "ls180.v:1237.11-1237.56" + wire width 3 $1\main_sdphy_datar_source_payload_status[2:0] + attribute \src "ls180.v:1233.5-1233.41" + wire $1\main_sdphy_datar_source_ready[0:0] + attribute \src "ls180.v:1232.5-1232.41" + wire $1\main_sdphy_datar_source_valid[0:0] + attribute \src "ls180.v:1238.5-1238.33" + wire $1\main_sdphy_datar_stop[0:0] + attribute \src "ls180.v:1239.12-1239.49" + wire width 32 $1\main_sdphy_datar_timeout[31:0] + attribute \src "ls180.v:1775.12-1775.73" + wire width 32 $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] + attribute \src "ls180.v:1776.5-1776.68" + wire $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] + attribute \src "ls180.v:1148.11-1148.40" + wire width 8 $1\main_sdphy_dataw_count[7:0] + attribute \src "ls180.v:1769.11-1769.61" + wire width 8 $1\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] + attribute \src "ls180.v:1770.5-1770.58" + wire $1\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] + attribute \src "ls180.v:1207.5-1207.50" + wire $1\main_sdphy_dataw_crcr_buf_source_first[0:0] + attribute \src "ls180.v:1208.5-1208.49" + wire $1\main_sdphy_dataw_crcr_buf_source_last[0:0] + attribute \src "ls180.v:1209.11-1209.63" + wire width 8 $1\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] + attribute \src "ls180.v:1205.5-1205.50" + wire $1\main_sdphy_dataw_crcr_buf_source_valid[0:0] + attribute \src "ls180.v:1192.11-1192.55" + wire width 3 $1\main_sdphy_dataw_crcr_converter_demux[2:0] + attribute \src "ls180.v:1188.5-1188.56" + wire $1\main_sdphy_dataw_crcr_converter_source_first[0:0] + attribute \src "ls180.v:1189.5-1189.55" + wire $1\main_sdphy_dataw_crcr_converter_source_last[0:0] + attribute \src "ls180.v:1190.11-1190.69" + wire width 8 $1\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] + attribute \src "ls180.v:1191.11-1191.82" + wire width 4 $1\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] + attribute \src "ls180.v:1194.5-1194.54" + wire $1\main_sdphy_dataw_crcr_converter_strobe_all[0:0] + attribute \src "ls180.v:1210.5-1210.39" + wire $1\main_sdphy_dataw_crcr_reset[0:0] + attribute \src "ls180.v:1765.5-1765.66" + wire $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] + attribute \src "ls180.v:1766.5-1766.69" + wire $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] + attribute \src "ls180.v:1180.5-1180.37" + wire $1\main_sdphy_dataw_crcr_run[0:0] + attribute \src "ls180.v:1175.5-1175.54" + wire $1\main_sdphy_dataw_crcr_source_source_ready0[0:0] + attribute \src "ls180.v:1162.5-1162.34" + wire $1\main_sdphy_dataw_error[0:0] + attribute \src "ls180.v:1137.5-1137.49" + wire $1\main_sdphy_dataw_pads_out_payload_clk[0:0] + attribute \src "ls180.v:1140.11-1140.58" + wire width 4 $1\main_sdphy_dataw_pads_out_payload_data_o[3:0] + attribute \src "ls180.v:1141.5-1141.53" + wire $1\main_sdphy_dataw_pads_out_payload_data_oe[0:0] + attribute \src "ls180.v:1144.5-1144.39" + wire $1\main_sdphy_dataw_sink_first[0:0] + attribute \src "ls180.v:1145.5-1145.38" + wire $1\main_sdphy_dataw_sink_last[0:0] + attribute \src "ls180.v:1146.11-1146.52" + wire width 8 $1\main_sdphy_dataw_sink_payload_data[7:0] + attribute \src "ls180.v:1143.5-1143.39" + wire $1\main_sdphy_dataw_sink_ready[0:0] + attribute \src "ls180.v:1142.5-1142.39" + wire $1\main_sdphy_dataw_sink_valid[0:0] + attribute \src "ls180.v:1160.5-1160.34" + wire $1\main_sdphy_dataw_start[0:0] + attribute \src "ls180.v:1147.5-1147.33" + wire $1\main_sdphy_dataw_stop[0:0] + attribute \src "ls180.v:1161.5-1161.34" + wire $1\main_sdphy_dataw_valid[0:0] + attribute \src "ls180.v:1041.11-1041.39" + wire width 8 $1\main_sdphy_init_count[7:0] + attribute \src "ls180.v:1749.11-1749.66" + wire width 8 $1\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] + attribute \src "ls180.v:1750.5-1750.63" + wire $1\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] + attribute \src "ls180.v:1036.5-1036.48" + wire $1\main_sdphy_init_pads_out_payload_clk[0:0] + attribute \src "ls180.v:1037.5-1037.50" + wire $1\main_sdphy_init_pads_out_payload_cmd_o[0:0] + attribute \src "ls180.v:1038.5-1038.51" + wire $1\main_sdphy_init_pads_out_payload_cmd_oe[0:0] + attribute \src "ls180.v:1039.11-1039.57" + wire width 4 $1\main_sdphy_init_pads_out_payload_data_o[3:0] + attribute \src "ls180.v:1040.5-1040.52" + wire $1\main_sdphy_init_pads_out_payload_data_oe[0:0] + attribute \src "ls180.v:1290.5-1290.35" + wire $1\main_sdphy_sdpads_cmd_i[0:0] + attribute \src "ls180.v:1293.11-1293.42" + wire width 4 $1\main_sdphy_sdpads_data_i[3:0] + attribute \src "ls180.v:299.5-299.33" + wire $1\main_sdram_address_re[0:0] + attribute \src "ls180.v:298.12-298.46" + wire width 13 $1\main_sdram_address_storage[12:0] + attribute \src "ls180.v:301.5-301.34" + wire $1\main_sdram_baddress_re[0:0] + attribute \src "ls180.v:300.11-300.45" + wire width 2 $1\main_sdram_baddress_storage[1:0] + attribute \src "ls180.v:397.5-397.50" + wire $1\main_sdram_bankmachine0_auto_precharge[0:0] + attribute \src "ls180.v:419.11-419.70" + wire width 3 $1\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] + attribute \src "ls180.v:416.11-416.68" + wire width 4 $1\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] + attribute \src "ls180.v:418.11-418.70" + wire width 3 $1\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] + attribute \src "ls180.v:420.11-420.73" + wire width 3 $1\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] + attribute \src "ls180.v:443.5-443.59" + wire $1\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] + attribute \src "ls180.v:444.5-444.58" + wire $1\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] + attribute \src "ls180.v:446.12-446.74" + wire width 22 $1\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] + attribute \src "ls180.v:445.5-445.64" + wire $1\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] + attribute \src "ls180.v:441.5-441.59" + wire $1\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] + attribute \src "ls180.v:389.12-389.57" + wire width 13 $1\main_sdram_bankmachine0_cmd_payload_a[12:0] + attribute \src "ls180.v:391.5-391.51" + wire $1\main_sdram_bankmachine0_cmd_payload_cas[0:0] + attribute \src "ls180.v:394.5-394.54" + wire $1\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] + attribute \src "ls180.v:395.5-395.55" + wire $1\main_sdram_bankmachine0_cmd_payload_is_read[0:0] + attribute \src "ls180.v:396.5-396.56" + wire $1\main_sdram_bankmachine0_cmd_payload_is_write[0:0] + attribute \src "ls180.v:392.5-392.51" + wire $1\main_sdram_bankmachine0_cmd_payload_ras[0:0] + attribute \src "ls180.v:393.5-393.50" + wire $1\main_sdram_bankmachine0_cmd_payload_we[0:0] + attribute \src "ls180.v:388.5-388.45" + wire $1\main_sdram_bankmachine0_cmd_ready[0:0] + attribute \src "ls180.v:387.5-387.45" + wire $1\main_sdram_bankmachine0_cmd_valid[0:0] + attribute \src "ls180.v:386.5-386.47" + wire $1\main_sdram_bankmachine0_refresh_gnt[0:0] + attribute \src "ls180.v:384.5-384.51" + wire $1\main_sdram_bankmachine0_req_rdata_valid[0:0] + attribute \src "ls180.v:383.5-383.51" + wire $1\main_sdram_bankmachine0_req_wdata_ready[0:0] + attribute \src "ls180.v:447.12-447.47" + wire width 13 $1\main_sdram_bankmachine0_row[12:0] + attribute \src "ls180.v:451.5-451.45" + wire $1\main_sdram_bankmachine0_row_close[0:0] + attribute \src "ls180.v:452.5-452.54" + wire $1\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] + attribute \src "ls180.v:450.5-450.44" + wire $1\main_sdram_bankmachine0_row_open[0:0] + attribute \src "ls180.v:448.5-448.46" + wire $1\main_sdram_bankmachine0_row_opened[0:0] + attribute \src "ls180.v:455.11-455.55" + wire width 3 $1\main_sdram_bankmachine0_twtpcon_count[2:0] + attribute \src "ls180.v:454.32-454.76" + wire $1\main_sdram_bankmachine0_twtpcon_ready[0:0] + attribute \src "ls180.v:479.5-479.50" + wire $1\main_sdram_bankmachine1_auto_precharge[0:0] + attribute \src "ls180.v:501.11-501.70" + wire width 3 $1\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] + attribute \src "ls180.v:498.11-498.68" + wire width 4 $1\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] + attribute \src "ls180.v:500.11-500.70" + wire width 3 $1\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] + attribute \src "ls180.v:502.11-502.73" + wire width 3 $1\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] + attribute \src "ls180.v:525.5-525.59" + wire $1\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] + attribute \src "ls180.v:526.5-526.58" + wire $1\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] + attribute \src "ls180.v:528.12-528.74" + wire width 22 $1\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] + attribute \src "ls180.v:527.5-527.64" + wire $1\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] + attribute \src "ls180.v:523.5-523.59" + wire $1\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] + attribute \src "ls180.v:471.12-471.57" + wire width 13 $1\main_sdram_bankmachine1_cmd_payload_a[12:0] + attribute \src "ls180.v:473.5-473.51" + wire $1\main_sdram_bankmachine1_cmd_payload_cas[0:0] + attribute \src "ls180.v:476.5-476.54" + wire $1\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] + attribute \src "ls180.v:477.5-477.55" + wire $1\main_sdram_bankmachine1_cmd_payload_is_read[0:0] + attribute \src "ls180.v:478.5-478.56" + wire $1\main_sdram_bankmachine1_cmd_payload_is_write[0:0] + attribute \src "ls180.v:474.5-474.51" + wire $1\main_sdram_bankmachine1_cmd_payload_ras[0:0] + attribute \src "ls180.v:475.5-475.50" + wire $1\main_sdram_bankmachine1_cmd_payload_we[0:0] + attribute \src "ls180.v:470.5-470.45" + wire $1\main_sdram_bankmachine1_cmd_ready[0:0] + attribute \src "ls180.v:469.5-469.45" + wire $1\main_sdram_bankmachine1_cmd_valid[0:0] + attribute \src "ls180.v:468.5-468.47" + wire $1\main_sdram_bankmachine1_refresh_gnt[0:0] + attribute \src "ls180.v:466.5-466.51" + wire $1\main_sdram_bankmachine1_req_rdata_valid[0:0] + attribute \src "ls180.v:465.5-465.51" + wire $1\main_sdram_bankmachine1_req_wdata_ready[0:0] + attribute \src "ls180.v:529.12-529.47" + wire width 13 $1\main_sdram_bankmachine1_row[12:0] + attribute \src "ls180.v:533.5-533.45" + wire $1\main_sdram_bankmachine1_row_close[0:0] + attribute \src "ls180.v:534.5-534.54" + wire $1\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] + attribute \src "ls180.v:532.5-532.44" + wire $1\main_sdram_bankmachine1_row_open[0:0] + attribute \src "ls180.v:530.5-530.46" + wire $1\main_sdram_bankmachine1_row_opened[0:0] + attribute \src "ls180.v:537.11-537.55" + wire width 3 $1\main_sdram_bankmachine1_twtpcon_count[2:0] + attribute \src "ls180.v:536.32-536.76" + wire $1\main_sdram_bankmachine1_twtpcon_ready[0:0] + attribute \src "ls180.v:561.5-561.50" + wire $1\main_sdram_bankmachine2_auto_precharge[0:0] + attribute \src "ls180.v:583.11-583.70" + wire width 3 $1\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] + attribute \src "ls180.v:580.11-580.68" + wire width 4 $1\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] + attribute \src "ls180.v:582.11-582.70" + wire width 3 $1\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] + attribute \src "ls180.v:584.11-584.73" + wire width 3 $1\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] + attribute \src "ls180.v:607.5-607.59" + wire $1\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] + attribute \src "ls180.v:608.5-608.58" + wire $1\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] + attribute \src "ls180.v:610.12-610.74" + wire width 22 $1\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] + attribute \src "ls180.v:609.5-609.64" + wire $1\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] + attribute \src "ls180.v:605.5-605.59" + wire $1\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] + attribute \src "ls180.v:553.12-553.57" + wire width 13 $1\main_sdram_bankmachine2_cmd_payload_a[12:0] + attribute \src "ls180.v:555.5-555.51" + wire $1\main_sdram_bankmachine2_cmd_payload_cas[0:0] + attribute \src "ls180.v:558.5-558.54" + wire $1\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] + attribute \src "ls180.v:559.5-559.55" + wire $1\main_sdram_bankmachine2_cmd_payload_is_read[0:0] + attribute \src "ls180.v:560.5-560.56" + wire $1\main_sdram_bankmachine2_cmd_payload_is_write[0:0] + attribute \src "ls180.v:556.5-556.51" + wire $1\main_sdram_bankmachine2_cmd_payload_ras[0:0] + attribute \src "ls180.v:557.5-557.50" + wire $1\main_sdram_bankmachine2_cmd_payload_we[0:0] + attribute \src "ls180.v:552.5-552.45" + wire $1\main_sdram_bankmachine2_cmd_ready[0:0] + attribute \src "ls180.v:551.5-551.45" + wire $1\main_sdram_bankmachine2_cmd_valid[0:0] + attribute \src "ls180.v:550.5-550.47" + wire $1\main_sdram_bankmachine2_refresh_gnt[0:0] + attribute \src "ls180.v:548.5-548.51" + wire $1\main_sdram_bankmachine2_req_rdata_valid[0:0] + attribute \src "ls180.v:547.5-547.51" + wire $1\main_sdram_bankmachine2_req_wdata_ready[0:0] + attribute \src "ls180.v:611.12-611.47" + wire width 13 $1\main_sdram_bankmachine2_row[12:0] + attribute \src "ls180.v:615.5-615.45" + wire $1\main_sdram_bankmachine2_row_close[0:0] + attribute \src "ls180.v:616.5-616.54" + wire $1\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] + attribute \src "ls180.v:614.5-614.44" + wire $1\main_sdram_bankmachine2_row_open[0:0] + attribute \src "ls180.v:612.5-612.46" + wire $1\main_sdram_bankmachine2_row_opened[0:0] + attribute \src "ls180.v:619.11-619.55" + wire width 3 $1\main_sdram_bankmachine2_twtpcon_count[2:0] + attribute \src "ls180.v:618.32-618.76" + wire $1\main_sdram_bankmachine2_twtpcon_ready[0:0] + attribute \src "ls180.v:643.5-643.50" + wire $1\main_sdram_bankmachine3_auto_precharge[0:0] + attribute \src "ls180.v:665.11-665.70" + wire width 3 $1\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] + attribute \src "ls180.v:662.11-662.68" + wire width 4 $1\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] + attribute \src "ls180.v:664.11-664.70" + wire width 3 $1\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] + attribute \src "ls180.v:666.11-666.73" + wire width 3 $1\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] + attribute \src "ls180.v:689.5-689.59" + wire $1\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] + attribute \src "ls180.v:690.5-690.58" + wire $1\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] + attribute \src "ls180.v:692.12-692.74" + wire width 22 $1\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] + attribute \src "ls180.v:691.5-691.64" + wire $1\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] + attribute \src "ls180.v:687.5-687.59" + wire $1\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] + attribute \src "ls180.v:635.12-635.57" + wire width 13 $1\main_sdram_bankmachine3_cmd_payload_a[12:0] + attribute \src "ls180.v:637.5-637.51" + wire $1\main_sdram_bankmachine3_cmd_payload_cas[0:0] + attribute \src "ls180.v:640.5-640.54" + wire $1\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] + attribute \src "ls180.v:641.5-641.55" + wire $1\main_sdram_bankmachine3_cmd_payload_is_read[0:0] + attribute \src "ls180.v:642.5-642.56" + wire $1\main_sdram_bankmachine3_cmd_payload_is_write[0:0] + attribute \src "ls180.v:638.5-638.51" + wire $1\main_sdram_bankmachine3_cmd_payload_ras[0:0] + attribute \src "ls180.v:639.5-639.50" + wire $1\main_sdram_bankmachine3_cmd_payload_we[0:0] + attribute \src "ls180.v:634.5-634.45" + wire $1\main_sdram_bankmachine3_cmd_ready[0:0] + attribute \src "ls180.v:633.5-633.45" + wire $1\main_sdram_bankmachine3_cmd_valid[0:0] + attribute \src "ls180.v:632.5-632.47" + wire $1\main_sdram_bankmachine3_refresh_gnt[0:0] + attribute \src "ls180.v:630.5-630.51" + wire $1\main_sdram_bankmachine3_req_rdata_valid[0:0] + attribute \src "ls180.v:629.5-629.51" + wire $1\main_sdram_bankmachine3_req_wdata_ready[0:0] + attribute \src "ls180.v:693.12-693.47" + wire width 13 $1\main_sdram_bankmachine3_row[12:0] + attribute \src "ls180.v:697.5-697.45" + wire $1\main_sdram_bankmachine3_row_close[0:0] + attribute \src "ls180.v:698.5-698.54" + wire $1\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] + attribute \src "ls180.v:696.5-696.44" + wire $1\main_sdram_bankmachine3_row_open[0:0] + attribute \src "ls180.v:694.5-694.46" + wire $1\main_sdram_bankmachine3_row_opened[0:0] + attribute \src "ls180.v:701.11-701.55" + wire width 3 $1\main_sdram_bankmachine3_twtpcon_count[2:0] + attribute \src "ls180.v:700.32-700.76" + wire $1\main_sdram_bankmachine3_twtpcon_ready[0:0] + attribute \src "ls180.v:716.5-716.49" + wire $1\main_sdram_choose_cmd_cmd_payload_cas[0:0] + attribute \src "ls180.v:717.5-717.49" + wire $1\main_sdram_choose_cmd_cmd_payload_ras[0:0] + attribute \src "ls180.v:718.5-718.48" + wire $1\main_sdram_choose_cmd_cmd_payload_we[0:0] + attribute \src "ls180.v:724.11-724.45" + wire width 2 $1\main_sdram_choose_cmd_grant[1:0] + attribute \src "ls180.v:722.11-722.46" + wire width 4 $1\main_sdram_choose_cmd_valids[3:0] + attribute \src "ls180.v:734.5-734.49" + wire $1\main_sdram_choose_req_cmd_payload_cas[0:0] + attribute \src "ls180.v:735.5-735.49" + wire $1\main_sdram_choose_req_cmd_payload_ras[0:0] + attribute \src "ls180.v:736.5-736.48" + wire $1\main_sdram_choose_req_cmd_payload_we[0:0] + attribute \src "ls180.v:731.5-731.43" + wire $1\main_sdram_choose_req_cmd_ready[0:0] + attribute \src "ls180.v:742.11-742.45" + wire width 2 $1\main_sdram_choose_req_grant[1:0] + attribute \src "ls180.v:740.11-740.46" + wire width 4 $1\main_sdram_choose_req_valids[3:0] + attribute \src "ls180.v:729.5-729.48" + wire $1\main_sdram_choose_req_want_activates[0:0] + attribute \src "ls180.v:726.5-726.44" + wire $1\main_sdram_choose_req_want_reads[0:0] + attribute \src "ls180.v:727.5-727.45" + wire $1\main_sdram_choose_req_want_writes[0:0] + attribute \src "ls180.v:355.5-355.31" + wire $1\main_sdram_cmd_last[0:0] + attribute \src "ls180.v:356.12-356.44" + wire width 13 $1\main_sdram_cmd_payload_a[12:0] + attribute \src "ls180.v:357.11-357.43" + wire width 2 $1\main_sdram_cmd_payload_ba[1:0] + attribute \src "ls180.v:358.5-358.38" + wire $1\main_sdram_cmd_payload_cas[0:0] + attribute \src "ls180.v:359.5-359.38" + wire $1\main_sdram_cmd_payload_ras[0:0] + attribute \src "ls180.v:360.5-360.37" + wire $1\main_sdram_cmd_payload_we[0:0] + attribute \src "ls180.v:354.5-354.32" + wire $1\main_sdram_cmd_ready[0:0] + attribute \src "ls180.v:353.5-353.32" + wire $1\main_sdram_cmd_valid[0:0] + attribute \src "ls180.v:293.5-293.33" + wire $1\main_sdram_command_re[0:0] + attribute \src "ls180.v:292.11-292.44" + wire width 6 $1\main_sdram_command_storage[5:0] + attribute \src "ls180.v:337.12-337.45" + wire width 13 $1\main_sdram_dfi_p0_address[12:0] + attribute \src "ls180.v:338.11-338.40" + wire width 2 $1\main_sdram_dfi_p0_bank[1:0] + attribute \src "ls180.v:339.5-339.35" + wire $1\main_sdram_dfi_p0_cas_n[0:0] + attribute \src "ls180.v:340.5-340.34" + wire $1\main_sdram_dfi_p0_cs_n[0:0] + attribute \src "ls180.v:341.5-341.35" + wire $1\main_sdram_dfi_p0_ras_n[0:0] + attribute \src "ls180.v:350.5-350.39" + wire $1\main_sdram_dfi_p0_rddata_en[0:0] + attribute \src "ls180.v:342.5-342.34" + wire $1\main_sdram_dfi_p0_we_n[0:0] + attribute \src "ls180.v:348.5-348.39" + wire $1\main_sdram_dfi_p0_wrdata_en[0:0] + attribute \src "ls180.v:761.5-761.26" + wire $1\main_sdram_en0[0:0] + attribute \src "ls180.v:764.5-764.26" + wire $1\main_sdram_en1[0:0] + attribute \src "ls180.v:334.12-334.46" + wire width 16 $1\main_sdram_interface_wdata[15:0] + attribute \src "ls180.v:335.11-335.47" + wire width 2 $1\main_sdram_interface_wdata_we[1:0] + attribute \src "ls180.v:240.5-240.36" + wire $1\main_sdram_inti_p0_cas_n[0:0] + attribute \src "ls180.v:241.5-241.35" + wire $1\main_sdram_inti_p0_cs_n[0:0] + attribute \src "ls180.v:242.5-242.36" + wire $1\main_sdram_inti_p0_ras_n[0:0] + attribute \src "ls180.v:252.12-252.45" + wire width 16 $1\main_sdram_inti_p0_rddata[15:0] + attribute \src "ls180.v:253.5-253.43" + wire $1\main_sdram_inti_p0_rddata_valid[0:0] + attribute \src "ls180.v:243.5-243.35" + wire $1\main_sdram_inti_p0_we_n[0:0] + attribute \src "ls180.v:279.5-279.38" + wire $1\main_sdram_master_p0_act_n[0:0] + attribute \src "ls180.v:270.12-270.48" + wire width 13 $1\main_sdram_master_p0_address[12:0] + attribute \src "ls180.v:271.11-271.43" + wire width 2 $1\main_sdram_master_p0_bank[1:0] + attribute \src "ls180.v:272.5-272.38" + wire $1\main_sdram_master_p0_cas_n[0:0] + attribute \src "ls180.v:276.5-276.36" + wire $1\main_sdram_master_p0_cke[0:0] + attribute \src "ls180.v:273.5-273.37" + wire $1\main_sdram_master_p0_cs_n[0:0] + attribute \src "ls180.v:277.5-277.36" + wire $1\main_sdram_master_p0_odt[0:0] + attribute \src "ls180.v:274.5-274.38" + wire $1\main_sdram_master_p0_ras_n[0:0] + attribute \src "ls180.v:283.5-283.42" + wire $1\main_sdram_master_p0_rddata_en[0:0] + attribute \src "ls180.v:278.5-278.40" + wire $1\main_sdram_master_p0_reset_n[0:0] + attribute \src "ls180.v:275.5-275.37" + wire $1\main_sdram_master_p0_we_n[0:0] + attribute \src "ls180.v:280.12-280.47" + wire width 16 $1\main_sdram_master_p0_wrdata[15:0] + attribute \src "ls180.v:281.5-281.42" + wire $1\main_sdram_master_p0_wrdata_en[0:0] + attribute \src "ls180.v:282.11-282.50" + wire width 2 $1\main_sdram_master_p0_wrdata_mask[1:0] + attribute \src "ls180.v:371.5-371.38" + wire $1\main_sdram_postponer_count[0:0] + attribute \src "ls180.v:370.5-370.38" + wire $1\main_sdram_postponer_req_o[0:0] + attribute \src "ls180.v:291.5-291.25" + wire $1\main_sdram_re[0:0] + attribute \src "ls180.v:377.5-377.38" + wire $1\main_sdram_sequencer_count[0:0] + attribute \src "ls180.v:376.11-376.46" + wire width 4 $1\main_sdram_sequencer_counter[3:0] + attribute \src "ls180.v:375.5-375.38" + wire $1\main_sdram_sequencer_done1[0:0] + attribute \src "ls180.v:372.5-372.39" + wire $1\main_sdram_sequencer_start0[0:0] + attribute \src "ls180.v:268.12-268.46" + wire width 16 $1\main_sdram_slave_p0_rddata[15:0] + attribute \src "ls180.v:269.5-269.44" + wire $1\main_sdram_slave_p0_rddata_valid[0:0] + attribute \src "ls180.v:304.12-304.37" + wire width 16 $1\main_sdram_status[15:0] + attribute \src "ls180.v:746.11-746.40" + wire width 2 $1\main_sdram_steerer_sel[1:0] + attribute \src "ls180.v:290.11-290.36" + wire width 4 $1\main_sdram_storage[3:0] + attribute \src "ls180.v:755.5-755.36" + wire $1\main_sdram_tccdcon_count[0:0] + attribute \src "ls180.v:754.32-754.63" + wire $1\main_sdram_tccdcon_ready[0:0] + attribute \src "ls180.v:763.11-763.34" + wire width 5 $1\main_sdram_time0[4:0] + attribute \src "ls180.v:766.11-766.34" + wire width 4 $1\main_sdram_time1[3:0] + attribute \src "ls180.v:368.11-368.44" + wire width 10 $1\main_sdram_timer_count1[9:0] + attribute \src "ls180.v:758.11-758.42" + wire width 3 $1\main_sdram_twtrcon_count[2:0] + attribute \src "ls180.v:757.32-757.63" + wire $1\main_sdram_twtrcon_ready[0:0] + attribute \src "ls180.v:303.5-303.32" + wire $1\main_sdram_wrdata_re[0:0] + attribute \src "ls180.v:302.12-302.45" + wire width 16 $1\main_sdram_wrdata_storage[15:0] + attribute \src "ls180.v:812.5-812.27" + wire $1\main_sink_ready[0:0] + attribute \src "ls180.v:825.11-825.42" + wire width 8 $1\main_source_payload_data[7:0] + attribute \src "ls180.v:821.5-821.29" + wire $1\main_source_valid[0:0] + attribute \src "ls180.v:990.12-990.48" + wire width 16 $1\main_spi_master_clk_divider1[15:0] + attribute \src "ls180.v:985.5-985.38" + wire $1\main_spi_master_clk_enable[0:0] + attribute \src "ls180.v:972.5-972.38" + wire $1\main_spi_master_control_re[0:0] + attribute \src "ls180.v:971.12-971.51" + wire width 16 $1\main_spi_master_control_storage[15:0] + attribute \src "ls180.v:987.11-987.39" + wire width 3 $1\main_spi_master_count[2:0] + attribute \src "ls180.v:1745.11-1745.61" + wire width 3 $1\main_spi_master_count_spimaster0_next_value[2:0] + attribute \src "ls180.v:1746.5-1746.58" + wire $1\main_spi_master_count_spimaster0_next_value_ce[0:0] + attribute \src "ls180.v:986.5-986.37" + wire $1\main_spi_master_cs_enable[0:0] + attribute \src "ls180.v:982.5-982.33" + wire $1\main_spi_master_cs_re[0:0] + attribute \src "ls180.v:981.5-981.38" + wire $1\main_spi_master_cs_storage[0:0] + attribute \src "ls180.v:962.5-962.33" + wire $1\main_spi_master_done0[0:0] + attribute \src "ls180.v:963.5-963.31" + wire $1\main_spi_master_irq[0:0] + attribute \src "ls180.v:984.5-984.39" + wire $1\main_spi_master_loopback_re[0:0] + attribute \src "ls180.v:983.5-983.44" + wire $1\main_spi_master_loopback_storage[0:0] + attribute \src "ls180.v:965.11-965.38" + wire width 8 $1\main_spi_master_miso[7:0] + attribute \src "ls180.v:995.11-995.43" + wire width 8 $1\main_spi_master_miso_data[7:0] + attribute \src "ls180.v:989.5-989.38" + wire $1\main_spi_master_miso_latch[0:0] + attribute \src "ls180.v:993.11-993.43" + wire width 8 $1\main_spi_master_mosi_data[7:0] + attribute \src "ls180.v:988.5-988.38" + wire $1\main_spi_master_mosi_latch[0:0] + attribute \src "ls180.v:977.5-977.35" + wire $1\main_spi_master_mosi_re[0:0] + attribute \src "ls180.v:994.11-994.42" + wire width 3 $1\main_spi_master_mosi_sel[2:0] + attribute \src "ls180.v:976.11-976.46" + wire width 8 $1\main_spi_master_mosi_storage[7:0] + attribute \src "ls180.v:969.5-969.34" + wire $1\main_spi_master_start1[0:0] + attribute \src "ls180.v:809.12-809.38" + wire width 32 $1\main_storage[31:0] + attribute \src "ls180.v:819.11-819.34" + wire width 4 $1\main_tx_bitcount[3:0] + attribute \src "ls180.v:820.5-820.24" + wire $1\main_tx_busy[0:0] + attribute \src "ls180.v:818.11-818.29" + wire width 8 $1\main_tx_reg[7:0] + attribute \src "ls180.v:826.5-826.30" + wire $1\main_uart_clk_rxen[0:0] + attribute \src "ls180.v:816.5-816.30" + wire $1\main_uart_clk_txen[0:0] + attribute \src "ls180.v:859.11-859.50" + wire width 2 $1\main_uart_eventmanager_pending_w[1:0] + attribute \src "ls180.v:861.5-861.37" + wire $1\main_uart_eventmanager_re[0:0] + attribute \src "ls180.v:855.11-855.49" + wire width 2 $1\main_uart_eventmanager_status_w[1:0] + attribute \src "ls180.v:860.11-860.48" + wire width 2 $1\main_uart_eventmanager_storage[1:0] + attribute \src "ls180.v:850.5-850.30" + wire $1\main_uart_rx_clear[0:0] + attribute \src "ls180.v:934.11-934.43" + wire width 4 $1\main_uart_rx_fifo_consume[3:0] + attribute \src "ls180.v:931.11-931.42" + wire width 5 $1\main_uart_rx_fifo_level0[4:0] + attribute \src "ls180.v:933.11-933.43" + wire width 4 $1\main_uart_rx_fifo_produce[3:0] + attribute \src "ls180.v:924.5-924.38" + wire $1\main_uart_rx_fifo_readable[0:0] + attribute \src "ls180.v:935.11-935.46" + wire width 4 $1\main_uart_rx_fifo_wrport_adr[3:0] + attribute \src "ls180.v:851.5-851.36" + wire $1\main_uart_rx_old_trigger[0:0] + attribute \src "ls180.v:848.5-848.32" + wire $1\main_uart_rx_pending[0:0] + attribute \src "ls180.v:845.5-845.30" + wire $1\main_uart_tx_clear[0:0] + attribute \src "ls180.v:897.11-897.43" + wire width 4 $1\main_uart_tx_fifo_consume[3:0] + attribute \src "ls180.v:894.11-894.42" + wire width 5 $1\main_uart_tx_fifo_level0[4:0] + attribute \src "ls180.v:896.11-896.43" + wire width 4 $1\main_uart_tx_fifo_produce[3:0] + attribute \src "ls180.v:887.5-887.38" + wire $1\main_uart_tx_fifo_readable[0:0] + attribute \src "ls180.v:898.11-898.46" + wire width 4 $1\main_uart_tx_fifo_wrport_adr[3:0] + attribute \src "ls180.v:846.5-846.36" + wire $1\main_uart_tx_old_trigger[0:0] + attribute \src "ls180.v:843.5-843.32" + wire $1\main_uart_tx_pending[0:0] + attribute \src "ls180.v:787.5-787.29" + wire $1\main_wb_sdram_ack[0:0] + attribute \src "ls180.v:805.5-805.31" + wire $1\main_wdata_consumed[0:0] + attribute \src "ls180.v:2768.68-2768.110" + wire $add$ls180.v:2768$22_Y + attribute \src "ls180.v:2828.68-2828.110" + wire $add$ls180.v:2828$33_Y + attribute \src "ls180.v:2888.68-2888.110" + wire $add$ls180.v:2888$44_Y + attribute \src "ls180.v:4021.54-4021.83" + wire $add$ls180.v:4021$537_Y + attribute \src "ls180.v:4121.36-4121.89" + wire width 5 $add$ls180.v:4121$583_Y + attribute \src "ls180.v:4151.36-4151.89" + wire width 5 $add$ls180.v:4151$594_Y + attribute \src "ls180.v:4206.53-4206.81" + wire width 3 $add$ls180.v:4206$607_Y + attribute \src "ls180.v:4306.58-4306.86" + wire width 8 $add$ls180.v:4306$635_Y + attribute \src "ls180.v:4363.58-4363.86" + wire width 8 $add$ls180.v:4363$638_Y + attribute \src "ls180.v:4380.58-4380.86" + wire width 8 $add$ls180.v:4380$640_Y + attribute \src "ls180.v:4473.59-4473.87" + wire width 8 $add$ls180.v:4473$657_Y + attribute \src "ls180.v:4498.59-4498.87" + wire width 8 $add$ls180.v:4498$660_Y + attribute \src "ls180.v:4620.53-4620.82" + wire width 8 $add$ls180.v:4620$677_Y + attribute \src "ls180.v:4731.65-4731.114" + wire width 10 $add$ls180.v:4731$691_Y + attribute \src "ls180.v:4736.62-4736.91" + wire width 10 $add$ls180.v:4736$694_Y + attribute \src "ls180.v:4762.61-4762.90" + wire width 10 $add$ls180.v:4762$697_Y + attribute \src "ls180.v:4966.80-4966.117" + wire width 3 $add$ls180.v:4966$882_Y + attribute \src "ls180.v:5160.54-5160.82" + wire width 3 $add$ls180.v:5160$957_Y + attribute \src "ls180.v:5212.55-5212.84" + wire width 32 $add$ls180.v:5212$967_Y + attribute \src "ls180.v:5238.57-5238.86" + wire width 32 $add$ls180.v:5238$975_Y + attribute \src "ls180.v:5359.51-5359.134" + wire width 32 $add$ls180.v:5359$991_Y + attribute \src "ls180.v:5362.77-5362.125" + wire width 32 $add$ls180.v:5362$993_Y + attribute \src "ls180.v:5455.50-5455.105" + wire width 32 $add$ls180.v:5455$1002_Y + attribute \src "ls180.v:5457.77-5457.111" + wire width 32 $add$ls180.v:5457$1003_Y + attribute \src "ls180.v:5569.49-5569.73" + wire width 3 $add$ls180.v:5569$1022_Y + attribute \src "ls180.v:7437.36-7437.70" + wire width 32 $add$ls180.v:7437$2405_Y + attribute \src "ls180.v:7522.37-7522.72" + wire width 4 $add$ls180.v:7522$2426_Y + attribute \src "ls180.v:7539.60-7539.119" + wire width 3 $add$ls180.v:7539$2430_Y + attribute \src "ls180.v:7542.60-7542.119" + wire width 3 $add$ls180.v:7542$2431_Y + attribute \src "ls180.v:7546.59-7546.116" + wire width 4 $add$ls180.v:7546$2436_Y + attribute \src "ls180.v:7585.60-7585.119" + wire width 3 $add$ls180.v:7585$2446_Y + attribute \src "ls180.v:7588.60-7588.119" + wire width 3 $add$ls180.v:7588$2447_Y + attribute \src "ls180.v:7592.59-7592.116" + wire width 4 $add$ls180.v:7592$2452_Y + attribute \src "ls180.v:7631.60-7631.119" + wire width 3 $add$ls180.v:7631$2462_Y + attribute \src "ls180.v:7634.60-7634.119" + wire width 3 $add$ls180.v:7634$2463_Y + attribute \src "ls180.v:7638.59-7638.116" + wire width 4 $add$ls180.v:7638$2468_Y + attribute \src "ls180.v:7677.60-7677.119" + wire width 3 $add$ls180.v:7677$2478_Y + attribute \src "ls180.v:7680.60-7680.119" + wire width 3 $add$ls180.v:7680$2479_Y + attribute \src "ls180.v:7684.59-7684.116" + wire width 4 $add$ls180.v:7684$2484_Y + attribute \src "ls180.v:7914.25-7914.48" + wire width 4 $add$ls180.v:7914$2538_Y + attribute \src "ls180.v:7930.55-7930.95" + wire width 33 $add$ls180.v:7930$2541_Y + attribute \src "ls180.v:7943.25-7943.48" + wire width 4 $add$ls180.v:7943$2545_Y + attribute \src "ls180.v:7962.55-7962.95" + wire width 33 $add$ls180.v:7962$2548_Y + attribute \src "ls180.v:7988.33-7988.65" + wire width 4 $add$ls180.v:7988$2556_Y + attribute \src "ls180.v:7991.33-7991.65" + wire width 4 $add$ls180.v:7991$2557_Y + attribute \src "ls180.v:7995.33-7995.64" + wire width 5 $add$ls180.v:7995$2562_Y + attribute \src "ls180.v:8010.33-8010.65" + wire width 4 $add$ls180.v:8010$2567_Y + attribute \src "ls180.v:8013.33-8013.65" + wire width 4 $add$ls180.v:8013$2568_Y + attribute \src "ls180.v:8017.33-8017.64" + wire width 5 $add$ls180.v:8017$2573_Y + attribute \src "ls180.v:8038.35-8038.70" + wire width 16 $add$ls180.v:8038$2575_Y + attribute \src "ls180.v:8074.25-8074.49" + wire width 32 $add$ls180.v:8074$2580_Y + attribute \src "ls180.v:8088.25-8088.49" + wire width 32 $add$ls180.v:8088$2584_Y + attribute \src "ls180.v:8102.31-8102.61" + wire width 9 $add$ls180.v:8102$2589_Y + attribute \src "ls180.v:8125.45-8125.88" + wire width 3 $add$ls180.v:8125$2593_Y + attribute \src "ls180.v:8171.71-8171.114" + wire width 4 $add$ls180.v:8171$2599_Y + attribute \src "ls180.v:8206.46-8206.90" + wire width 3 $add$ls180.v:8206$2605_Y + attribute \src "ls180.v:8252.72-8252.116" + wire width 4 $add$ls180.v:8252$2611_Y + attribute \src "ls180.v:8285.47-8285.92" + wire $add$ls180.v:8285$2617_Y + attribute \src "ls180.v:8313.73-8313.118" + wire width 2 $add$ls180.v:8313$2623_Y + attribute \src "ls180.v:8425.39-8425.75" + wire width 4 $add$ls180.v:8425$2636_Y + attribute \src "ls180.v:8486.37-8486.73" + wire width 5 $add$ls180.v:8486$2640_Y + attribute \src "ls180.v:8489.37-8489.73" + wire width 5 $add$ls180.v:8489$2641_Y + attribute \src "ls180.v:8493.36-8493.70" + wire width 6 $add$ls180.v:8493$2646_Y + attribute \src "ls180.v:8508.41-8508.80" + wire width 2 $add$ls180.v:8508$2650_Y + attribute \src "ls180.v:8542.67-8542.106" + wire width 3 $add$ls180.v:8542$2656_Y + attribute \src "ls180.v:8568.39-8568.76" + wire width 2 $add$ls180.v:8568$2658_Y + attribute \src "ls180.v:8572.37-8572.73" + wire width 5 $add$ls180.v:8572$2662_Y + attribute \src "ls180.v:8575.37-8575.73" + wire width 5 $add$ls180.v:8575$2663_Y + attribute \src "ls180.v:8579.36-8579.70" + wire width 6 $add$ls180.v:8579$2668_Y + attribute \src "ls180.v:8586.31-8586.62" + wire width 16 $add$ls180.v:8586$2670_Y + attribute \src "ls180.v:2762.9-2762.80" + wire $and$ls180.v:2762$17_Y + attribute \src "ls180.v:2780.9-2780.80" + wire $and$ls180.v:2780$24_Y + attribute \src "ls180.v:2822.9-2822.80" + wire $and$ls180.v:2822$28_Y + attribute \src "ls180.v:2840.9-2840.80" + wire $and$ls180.v:2840$35_Y + attribute \src "ls180.v:2882.9-2882.86" + wire $and$ls180.v:2882$39_Y + attribute \src "ls180.v:2900.9-2900.86" + wire $and$ls180.v:2900$46_Y + attribute \src "ls180.v:2910.31-2910.90" + wire $and$ls180.v:2910$48_Y + attribute \src "ls180.v:2910.30-2910.121" + wire $and$ls180.v:2910$49_Y + attribute \src "ls180.v:2910.29-2910.156" + wire $and$ls180.v:2910$50_Y + attribute \src "ls180.v:2911.31-2911.90" + wire $and$ls180.v:2911$51_Y + attribute \src "ls180.v:2911.30-2911.121" + wire $and$ls180.v:2911$52_Y + attribute \src "ls180.v:2911.29-2911.156" + wire $and$ls180.v:2911$53_Y + attribute \src "ls180.v:2912.31-2912.90" + wire $and$ls180.v:2912$54_Y + attribute \src "ls180.v:2912.30-2912.121" + wire $and$ls180.v:2912$55_Y + attribute \src "ls180.v:2912.29-2912.156" + wire $and$ls180.v:2912$56_Y + attribute \src "ls180.v:2913.31-2913.90" + wire $and$ls180.v:2913$57_Y + attribute \src "ls180.v:2913.30-2913.121" + wire $and$ls180.v:2913$58_Y + attribute \src "ls180.v:2913.29-2913.156" + wire $and$ls180.v:2913$59_Y + attribute \src "ls180.v:2922.7-2922.89" + wire $and$ls180.v:2922$62_Y + attribute \src "ls180.v:2927.32-2927.111" + wire $and$ls180.v:2927$63_Y + attribute \src "ls180.v:3041.40-3041.99" + wire $and$ls180.v:3041$70_Y + attribute \src "ls180.v:3042.40-3042.99" + wire $and$ls180.v:3042$71_Y + attribute \src "ls180.v:3080.38-3080.103" + wire $and$ls180.v:3080$77_Y + attribute \src "ls180.v:3134.50-3134.119" + wire $and$ls180.v:3134$85_Y + attribute \src "ls180.v:3134.49-3134.167" + wire $and$ls180.v:3134$86_Y + attribute \src "ls180.v:3135.49-3135.118" + wire $and$ls180.v:3135$87_Y + attribute \src "ls180.v:3135.48-3135.154" + wire $and$ls180.v:3135$88_Y + attribute \src "ls180.v:3136.50-3136.119" + wire $and$ls180.v:3136$89_Y + attribute \src "ls180.v:3136.49-3136.155" + wire $and$ls180.v:3136$90_Y + attribute \src "ls180.v:3139.7-3139.114" + wire $and$ls180.v:3139$92_Y + attribute \src "ls180.v:3168.66-3168.246" + wire $and$ls180.v:3168$98_Y + attribute \src "ls180.v:3169.64-3169.187" + wire $and$ls180.v:3169$99_Y + attribute \src "ls180.v:3193.9-3193.86" + wire $and$ls180.v:3193$105_Y + attribute \src "ls180.v:3205.9-3205.86" + wire $and$ls180.v:3205$106_Y + attribute \src "ls180.v:3255.13-3255.87" + wire $and$ls180.v:3255$108_Y + attribute \src "ls180.v:3291.50-3291.119" + wire $and$ls180.v:3291$115_Y + attribute \src "ls180.v:3291.49-3291.167" + wire $and$ls180.v:3291$116_Y + attribute \src "ls180.v:3292.49-3292.118" + wire $and$ls180.v:3292$117_Y + attribute \src "ls180.v:3292.48-3292.154" + wire $and$ls180.v:3292$118_Y + attribute \src "ls180.v:3293.50-3293.119" + wire $and$ls180.v:3293$119_Y + attribute \src "ls180.v:3293.49-3293.155" + wire $and$ls180.v:3293$120_Y + attribute \src "ls180.v:3296.7-3296.114" + wire $and$ls180.v:3296$122_Y + attribute \src "ls180.v:3325.66-3325.246" + wire $and$ls180.v:3325$128_Y + attribute \src "ls180.v:3326.64-3326.187" + wire $and$ls180.v:3326$129_Y + attribute \src "ls180.v:3350.9-3350.86" + wire $and$ls180.v:3350$135_Y + attribute \src "ls180.v:3362.9-3362.86" + wire $and$ls180.v:3362$136_Y + attribute \src "ls180.v:3412.13-3412.87" + wire $and$ls180.v:3412$138_Y + attribute \src "ls180.v:3448.50-3448.119" + wire $and$ls180.v:3448$145_Y + attribute \src "ls180.v:3448.49-3448.167" + wire $and$ls180.v:3448$146_Y + attribute \src "ls180.v:3449.49-3449.118" + wire $and$ls180.v:3449$147_Y + attribute \src "ls180.v:3449.48-3449.154" + wire $and$ls180.v:3449$148_Y + attribute \src "ls180.v:3450.50-3450.119" + wire $and$ls180.v:3450$149_Y + attribute \src "ls180.v:3450.49-3450.155" + wire $and$ls180.v:3450$150_Y + attribute \src "ls180.v:3453.7-3453.114" + wire $and$ls180.v:3453$152_Y + attribute \src "ls180.v:3482.66-3482.246" + wire $and$ls180.v:3482$158_Y + attribute \src "ls180.v:3483.64-3483.187" + wire $and$ls180.v:3483$159_Y + attribute \src "ls180.v:3507.9-3507.86" + wire $and$ls180.v:3507$165_Y + attribute \src "ls180.v:3519.9-3519.86" + wire $and$ls180.v:3519$166_Y + attribute \src "ls180.v:3569.13-3569.87" + wire $and$ls180.v:3569$168_Y + attribute \src "ls180.v:3605.50-3605.119" + wire $and$ls180.v:3605$175_Y + attribute \src "ls180.v:3605.49-3605.167" + wire $and$ls180.v:3605$176_Y + attribute \src "ls180.v:3606.49-3606.118" + wire $and$ls180.v:3606$177_Y + attribute \src "ls180.v:3606.48-3606.154" + wire $and$ls180.v:3606$178_Y + attribute \src "ls180.v:3607.50-3607.119" + wire $and$ls180.v:3607$179_Y + attribute \src "ls180.v:3607.49-3607.155" + wire $and$ls180.v:3607$180_Y + attribute \src "ls180.v:3610.7-3610.114" + wire $and$ls180.v:3610$182_Y + attribute \src "ls180.v:3639.66-3639.246" + wire $and$ls180.v:3639$188_Y + attribute \src "ls180.v:3640.64-3640.187" + wire $and$ls180.v:3640$189_Y + attribute \src "ls180.v:3664.9-3664.86" + wire $and$ls180.v:3664$195_Y + attribute \src "ls180.v:3676.9-3676.86" + wire $and$ls180.v:3676$196_Y + attribute \src "ls180.v:3726.13-3726.87" + wire $and$ls180.v:3726$198_Y + attribute \src "ls180.v:3741.37-3741.102" + wire $and$ls180.v:3741$199_Y + attribute \src "ls180.v:3741.108-3741.188" + wire $and$ls180.v:3741$201_Y + attribute \src "ls180.v:3741.107-3741.231" + wire $and$ls180.v:3741$203_Y + attribute \src "ls180.v:3741.36-3741.232" + wire $and$ls180.v:3741$204_Y + attribute \src "ls180.v:3742.37-3742.102" + wire $and$ls180.v:3742$205_Y + attribute \src "ls180.v:3742.108-3742.188" + wire $and$ls180.v:3742$207_Y + attribute \src "ls180.v:3742.107-3742.231" + wire $and$ls180.v:3742$209_Y + attribute \src "ls180.v:3742.36-3742.232" + wire $and$ls180.v:3742$210_Y + attribute \src "ls180.v:3743.34-3743.85" + wire $and$ls180.v:3743$211_Y + attribute \src "ls180.v:3744.37-3744.102" + wire $and$ls180.v:3744$212_Y + attribute \src "ls180.v:3744.36-3744.194" + wire $and$ls180.v:3744$214_Y + attribute \src "ls180.v:3746.37-3746.102" + wire $and$ls180.v:3746$215_Y + attribute \src "ls180.v:3746.36-3746.148" + wire $and$ls180.v:3746$216_Y + attribute \src "ls180.v:3747.40-3747.119" + wire $and$ls180.v:3747$217_Y + attribute \src "ls180.v:3747.124-3747.203" + wire $and$ls180.v:3747$218_Y + attribute \src "ls180.v:3747.209-3747.288" + wire $and$ls180.v:3747$220_Y + attribute \src "ls180.v:3747.294-3747.373" + wire $and$ls180.v:3747$222_Y + attribute \src "ls180.v:3748.41-3748.121" + wire $and$ls180.v:3748$224_Y + attribute \src "ls180.v:3748.126-3748.206" + wire $and$ls180.v:3748$225_Y + attribute \src "ls180.v:3748.212-3748.292" + wire $and$ls180.v:3748$227_Y + attribute \src "ls180.v:3748.298-3748.378" + wire $and$ls180.v:3748$229_Y + attribute \src "ls180.v:3755.38-3755.111" + wire $and$ls180.v:3755$233_Y + attribute \src "ls180.v:3755.37-3755.150" + wire $and$ls180.v:3755$234_Y + attribute \src "ls180.v:3755.36-3755.189" + wire $and$ls180.v:3755$235_Y + attribute \src "ls180.v:3761.77-3761.153" + wire $and$ls180.v:3761$238_Y + attribute \src "ls180.v:3761.162-3761.246" + wire $and$ls180.v:3761$240_Y + attribute \src "ls180.v:3761.161-3761.291" + wire $and$ls180.v:3761$242_Y + attribute \src "ls180.v:3761.76-3761.333" + wire $and$ls180.v:3761$245_Y + attribute \src "ls180.v:3761.338-3761.505" + wire $and$ls180.v:3761$248_Y + attribute \src "ls180.v:3761.38-3761.507" + wire $and$ls180.v:3761$250_Y + attribute \src "ls180.v:3762.77-3762.153" + wire $and$ls180.v:3762$251_Y + attribute \src "ls180.v:3762.162-3762.246" + wire $and$ls180.v:3762$253_Y + attribute \src "ls180.v:3762.161-3762.291" + wire $and$ls180.v:3762$255_Y + attribute \src "ls180.v:3762.76-3762.333" + wire $and$ls180.v:3762$258_Y + attribute \src "ls180.v:3762.338-3762.505" + wire $and$ls180.v:3762$261_Y + attribute \src "ls180.v:3762.38-3762.507" + wire $and$ls180.v:3762$263_Y + attribute \src "ls180.v:3763.77-3763.153" + wire $and$ls180.v:3763$264_Y + attribute \src "ls180.v:3763.162-3763.246" + wire $and$ls180.v:3763$266_Y + attribute \src "ls180.v:3763.161-3763.291" + wire $and$ls180.v:3763$268_Y + attribute \src "ls180.v:3763.76-3763.333" + wire $and$ls180.v:3763$271_Y + attribute \src "ls180.v:3763.338-3763.505" + wire $and$ls180.v:3763$274_Y + attribute \src "ls180.v:3763.38-3763.507" + wire $and$ls180.v:3763$276_Y + attribute \src "ls180.v:3764.77-3764.153" + wire $and$ls180.v:3764$277_Y + attribute \src "ls180.v:3764.162-3764.246" + wire $and$ls180.v:3764$279_Y + attribute \src "ls180.v:3764.161-3764.291" + wire $and$ls180.v:3764$281_Y + attribute \src "ls180.v:3764.76-3764.333" + wire $and$ls180.v:3764$284_Y + attribute \src "ls180.v:3764.338-3764.505" + wire $and$ls180.v:3764$287_Y + attribute \src "ls180.v:3764.38-3764.507" + wire $and$ls180.v:3764$289_Y + attribute \src "ls180.v:3794.77-3794.153" + wire $and$ls180.v:3794$296_Y + attribute \src "ls180.v:3794.162-3794.246" + wire $and$ls180.v:3794$298_Y + attribute \src "ls180.v:3794.161-3794.291" + wire $and$ls180.v:3794$300_Y + attribute \src "ls180.v:3794.76-3794.333" + wire $and$ls180.v:3794$303_Y + attribute \src "ls180.v:3794.338-3794.505" + wire $and$ls180.v:3794$306_Y + attribute \src "ls180.v:3794.38-3794.507" + wire $and$ls180.v:3794$308_Y + attribute \src "ls180.v:3795.77-3795.153" + wire $and$ls180.v:3795$309_Y + attribute \src "ls180.v:3795.162-3795.246" + wire $and$ls180.v:3795$311_Y + attribute \src "ls180.v:3795.161-3795.291" + wire $and$ls180.v:3795$313_Y + attribute \src "ls180.v:3795.76-3795.333" + wire $and$ls180.v:3795$316_Y + attribute \src "ls180.v:3795.338-3795.505" + wire $and$ls180.v:3795$319_Y + attribute \src "ls180.v:3795.38-3795.507" + wire $and$ls180.v:3795$321_Y + attribute \src "ls180.v:3796.77-3796.153" + wire $and$ls180.v:3796$322_Y + attribute \src "ls180.v:3796.162-3796.246" + wire $and$ls180.v:3796$324_Y + attribute \src "ls180.v:3796.161-3796.291" + wire $and$ls180.v:3796$326_Y + attribute \src "ls180.v:3796.76-3796.333" + wire $and$ls180.v:3796$329_Y + attribute \src "ls180.v:3796.338-3796.505" + wire $and$ls180.v:3796$332_Y + attribute \src "ls180.v:3796.38-3796.507" + wire $and$ls180.v:3796$334_Y + attribute \src "ls180.v:3797.77-3797.153" + wire $and$ls180.v:3797$335_Y + attribute \src "ls180.v:3797.162-3797.246" + wire $and$ls180.v:3797$337_Y + attribute \src "ls180.v:3797.161-3797.291" + wire $and$ls180.v:3797$339_Y + attribute \src "ls180.v:3797.76-3797.333" + wire $and$ls180.v:3797$342_Y + attribute \src "ls180.v:3797.338-3797.505" + wire $and$ls180.v:3797$345_Y + attribute \src "ls180.v:3797.38-3797.507" + wire $and$ls180.v:3797$347_Y + attribute \src "ls180.v:3826.8-3826.73" + wire $and$ls180.v:3826$352_Y + attribute \src "ls180.v:3826.7-3826.114" + wire $and$ls180.v:3826$354_Y + attribute \src "ls180.v:3829.8-3829.73" + wire $and$ls180.v:3829$355_Y + attribute \src "ls180.v:3829.7-3829.114" + wire $and$ls180.v:3829$357_Y + attribute \src "ls180.v:3835.8-3835.73" + wire $and$ls180.v:3835$359_Y + attribute \src "ls180.v:3835.7-3835.114" + wire $and$ls180.v:3835$361_Y + attribute \src "ls180.v:3838.8-3838.73" + wire $and$ls180.v:3838$362_Y + attribute \src "ls180.v:3838.7-3838.114" + wire $and$ls180.v:3838$364_Y + attribute \src "ls180.v:3844.8-3844.73" + wire $and$ls180.v:3844$366_Y + attribute \src "ls180.v:3844.7-3844.114" + wire $and$ls180.v:3844$368_Y + attribute \src "ls180.v:3847.8-3847.73" + wire $and$ls180.v:3847$369_Y + attribute \src "ls180.v:3847.7-3847.114" + wire $and$ls180.v:3847$371_Y + attribute \src "ls180.v:3853.8-3853.73" + wire $and$ls180.v:3853$373_Y + attribute \src "ls180.v:3853.7-3853.114" + wire $and$ls180.v:3853$375_Y + attribute \src "ls180.v:3856.8-3856.73" + wire $and$ls180.v:3856$376_Y + attribute \src "ls180.v:3856.7-3856.114" + wire $and$ls180.v:3856$378_Y + attribute \src "ls180.v:3881.71-3881.151" + wire $and$ls180.v:3881$383_Y + attribute \src "ls180.v:3881.70-3881.194" + wire $and$ls180.v:3881$385_Y + attribute \src "ls180.v:3881.41-3881.222" + wire $and$ls180.v:3881$388_Y + attribute \src "ls180.v:3919.71-3919.151" + wire $and$ls180.v:3919$392_Y + attribute \src "ls180.v:3919.70-3919.194" + wire $and$ls180.v:3919$394_Y + attribute \src "ls180.v:3919.41-3919.222" + wire $and$ls180.v:3919$397_Y + attribute \src "ls180.v:3937.110-3937.179" + wire $and$ls180.v:3937$402_Y + attribute \src "ls180.v:3937.185-3937.254" + wire $and$ls180.v:3937$405_Y + attribute \src "ls180.v:3937.260-3937.329" + wire $and$ls180.v:3937$408_Y + attribute \src "ls180.v:3937.41-3937.332" + wire $and$ls180.v:3937$411_Y + attribute \src "ls180.v:3937.40-3937.355" + wire $and$ls180.v:3937$412_Y + attribute \src "ls180.v:3938.34-3938.106" + wire $and$ls180.v:3938$415_Y + attribute \src "ls180.v:3942.110-3942.179" + wire $and$ls180.v:3942$418_Y + attribute \src "ls180.v:3942.185-3942.254" + wire $and$ls180.v:3942$421_Y + attribute \src "ls180.v:3942.260-3942.329" + wire $and$ls180.v:3942$424_Y + attribute \src "ls180.v:3942.41-3942.332" + wire $and$ls180.v:3942$427_Y + attribute \src "ls180.v:3942.40-3942.355" + wire $and$ls180.v:3942$428_Y + attribute \src "ls180.v:3943.34-3943.106" + wire $and$ls180.v:3943$431_Y + attribute \src "ls180.v:3947.110-3947.179" + wire $and$ls180.v:3947$434_Y + attribute \src "ls180.v:3947.185-3947.254" + wire $and$ls180.v:3947$437_Y + attribute \src "ls180.v:3947.260-3947.329" + wire $and$ls180.v:3947$440_Y + attribute \src "ls180.v:3947.41-3947.332" + wire $and$ls180.v:3947$443_Y + attribute \src "ls180.v:3947.40-3947.355" + wire $and$ls180.v:3947$444_Y + attribute \src "ls180.v:3948.34-3948.106" + wire $and$ls180.v:3948$447_Y + attribute \src "ls180.v:3952.110-3952.179" + wire $and$ls180.v:3952$450_Y + attribute \src "ls180.v:3952.185-3952.254" + wire $and$ls180.v:3952$453_Y + attribute \src "ls180.v:3952.260-3952.329" + wire $and$ls180.v:3952$456_Y + attribute \src "ls180.v:3952.41-3952.332" + wire $and$ls180.v:3952$459_Y + attribute \src "ls180.v:3952.40-3952.355" + wire $and$ls180.v:3952$460_Y + attribute \src "ls180.v:3953.34-3953.106" + wire $and$ls180.v:3953$463_Y + attribute \src "ls180.v:3957.151-3957.220" + wire $and$ls180.v:3957$467_Y + attribute \src "ls180.v:3957.226-3957.295" + wire $and$ls180.v:3957$470_Y + attribute \src "ls180.v:3957.301-3957.370" + wire $and$ls180.v:3957$473_Y + attribute \src "ls180.v:3957.82-3957.373" + wire $and$ls180.v:3957$476_Y + attribute \src "ls180.v:3957.43-3957.374" + wire $and$ls180.v:3957$477_Y + attribute \src "ls180.v:3957.42-3957.410" + wire $and$ls180.v:3957$478_Y + attribute \src "ls180.v:3957.525-3957.594" + wire $and$ls180.v:3957$483_Y + attribute \src "ls180.v:3957.600-3957.669" + wire $and$ls180.v:3957$486_Y + attribute \src "ls180.v:3957.675-3957.744" + wire $and$ls180.v:3957$489_Y + attribute \src "ls180.v:3957.456-3957.747" + wire $and$ls180.v:3957$492_Y + attribute \src "ls180.v:3957.417-3957.748" + wire $and$ls180.v:3957$493_Y + attribute \src "ls180.v:3957.416-3957.784" + wire $and$ls180.v:3957$494_Y + attribute \src "ls180.v:3957.899-3957.968" + wire $and$ls180.v:3957$499_Y + attribute \src "ls180.v:3957.974-3957.1043" + wire $and$ls180.v:3957$502_Y + attribute \src "ls180.v:3957.1049-3957.1118" + wire $and$ls180.v:3957$505_Y + attribute \src "ls180.v:3957.830-3957.1121" + wire $and$ls180.v:3957$508_Y + attribute \src "ls180.v:3957.791-3957.1122" + wire $and$ls180.v:3957$509_Y + attribute \src "ls180.v:3957.790-3957.1158" + wire $and$ls180.v:3957$510_Y + attribute \src "ls180.v:3957.1273-3957.1342" + wire $and$ls180.v:3957$515_Y + attribute \src "ls180.v:3957.1348-3957.1417" + wire $and$ls180.v:3957$518_Y + attribute \src "ls180.v:3957.1423-3957.1492" + wire $and$ls180.v:3957$521_Y + attribute \src "ls180.v:3957.1204-3957.1495" + wire $and$ls180.v:3957$524_Y + attribute \src "ls180.v:3957.1165-3957.1496" + wire $and$ls180.v:3957$525_Y + attribute \src "ls180.v:3957.1164-3957.1532" + wire $and$ls180.v:3957$526_Y + attribute \src "ls180.v:4015.9-4015.46" + wire $and$ls180.v:4015$532_Y + attribute \src "ls180.v:4033.9-4033.46" + wire $and$ls180.v:4033$539_Y + attribute \src "ls180.v:4046.32-4046.75" + wire $and$ls180.v:4046$543_Y + attribute \src "ls180.v:4046.31-4046.99" + wire $and$ls180.v:4046$545_Y + attribute \src "ls180.v:4047.34-4047.102" + wire $and$ls180.v:4047$547_Y + attribute \src "ls180.v:4047.33-4047.128" + wire $and$ls180.v:4047$549_Y + attribute \src "ls180.v:4048.33-4048.104" + wire $and$ls180.v:4048$552_Y + attribute \src "ls180.v:4049.49-4049.85" + wire $and$ls180.v:4049$553_Y + attribute \src "ls180.v:4049.90-4049.129" + wire $and$ls180.v:4049$555_Y + attribute \src "ls180.v:4049.32-4049.131" + wire $and$ls180.v:4049$557_Y + attribute \src "ls180.v:4050.25-4050.66" + wire $and$ls180.v:4050$558_Y + attribute \src "ls180.v:4051.27-4051.72" + wire $and$ls180.v:4051$560_Y + attribute \src "ls180.v:4052.26-4052.71" + wire $and$ls180.v:4052$562_Y + attribute \src "ls180.v:4081.64-4081.88" + wire $and$ls180.v:4081$568_Y + attribute \src "ls180.v:4085.7-4085.78" + wire $and$ls180.v:4085$572_Y + attribute \src "ls180.v:4096.7-4096.78" + wire $and$ls180.v:4096$575_Y + attribute \src "ls180.v:4105.26-4105.97" + wire $and$ls180.v:4105$577_Y + attribute \src "ls180.v:4105.102-4105.173" + wire $and$ls180.v:4105$578_Y + attribute \src "ls180.v:4120.41-4120.133" + wire $and$ls180.v:4120$582_Y + attribute \src "ls180.v:4131.39-4131.136" + wire $and$ls180.v:4131$587_Y + attribute \src "ls180.v:4132.37-4132.104" + wire $and$ls180.v:4132$588_Y + attribute \src "ls180.v:4150.41-4150.133" + wire $and$ls180.v:4150$593_Y + attribute \src "ls180.v:4161.39-4161.136" + wire $and$ls180.v:4161$598_Y + attribute \src "ls180.v:4162.37-4162.104" + wire $and$ls180.v:4162$599_Y + attribute \src "ls180.v:4287.33-4287.86" + wire $and$ls180.v:4287$633_Y + attribute \src "ls180.v:4391.9-4391.68" + wire $and$ls180.v:4391$642_Y + attribute \src "ls180.v:4411.53-4411.145" + wire $and$ls180.v:4411$645_Y + attribute \src "ls180.v:4430.52-4430.137" + wire $and$ls180.v:4430$648_Y + attribute \src "ls180.v:4471.9-4471.68" + wire $and$ls180.v:4471$656_Y + attribute \src "ls180.v:4509.9-4509.68" + wire $and$ls180.v:4509$662_Y + attribute \src "ls180.v:4518.10-4518.69" + wire $and$ls180.v:4518$663_Y + attribute \src "ls180.v:4518.9-4518.93" + wire $and$ls180.v:4518$664_Y + attribute \src "ls180.v:4538.54-4538.117" + wire $and$ls180.v:4538$666_Y + attribute \src "ls180.v:4557.53-4557.140" + wire $and$ls180.v:4557$669_Y + attribute \src "ls180.v:4654.9-4654.70" + wire $and$ls180.v:4654$679_Y + attribute \src "ls180.v:4672.55-4672.120" + wire $and$ls180.v:4672$681_Y + attribute \src "ls180.v:4691.54-4691.143" + wire $and$ls180.v:4691$684_Y + attribute \src "ls180.v:4773.9-4773.70" + wire $and$ls180.v:4773$699_Y + attribute \src "ls180.v:4780.9-4780.70" + wire $and$ls180.v:4780$700_Y + attribute \src "ls180.v:4861.48-4861.124" + wire $and$ls180.v:4861$823_Y + attribute \src "ls180.v:4861.47-4861.165" + wire $and$ls180.v:4861$824_Y + attribute \src "ls180.v:4862.50-4862.127" + wire $and$ls180.v:4862$825_Y + attribute \src "ls180.v:4864.48-4864.124" + wire $and$ls180.v:4864$826_Y + attribute \src "ls180.v:4864.47-4864.165" + wire $and$ls180.v:4864$827_Y + attribute \src "ls180.v:4865.50-4865.127" + wire $and$ls180.v:4865$828_Y + attribute \src "ls180.v:4867.48-4867.124" + wire $and$ls180.v:4867$829_Y + attribute \src "ls180.v:4867.47-4867.165" + wire $and$ls180.v:4867$830_Y + attribute \src "ls180.v:4868.50-4868.127" + wire $and$ls180.v:4868$831_Y + attribute \src "ls180.v:4870.48-4870.124" + wire $and$ls180.v:4870$832_Y + attribute \src "ls180.v:4870.47-4870.165" + wire $and$ls180.v:4870$833_Y + attribute \src "ls180.v:4871.50-4871.127" + wire $and$ls180.v:4871$834_Y + attribute \src "ls180.v:4984.10-4984.86" + wire $and$ls180.v:4984$883_Y + attribute \src "ls180.v:4984.9-4984.127" + wire $and$ls180.v:4984$884_Y + attribute \src "ls180.v:4994.9-4994.152" + wire $and$ls180.v:4994$888_Y + attribute \src "ls180.v:4994.8-4994.226" + wire $and$ls180.v:4994$890_Y + attribute \src "ls180.v:4994.7-4994.300" + wire $and$ls180.v:4994$892_Y + attribute \src "ls180.v:4999.49-4999.124" + wire $and$ls180.v:4999$893_Y + attribute \src "ls180.v:5009.49-5009.124" + wire $and$ls180.v:5009$896_Y + attribute \src "ls180.v:5019.49-5019.124" + wire $and$ls180.v:5019$899_Y + attribute \src "ls180.v:5029.49-5029.124" + wire $and$ls180.v:5029$902_Y + attribute \src "ls180.v:5041.7-5041.84" + wire $and$ls180.v:5041$907_Y + attribute \src "ls180.v:5159.9-5159.64" + wire $and$ls180.v:5159$956_Y + attribute \src "ls180.v:5211.10-5211.66" + wire $and$ls180.v:5211$965_Y + attribute \src "ls180.v:5211.9-5211.97" + wire $and$ls180.v:5211$966_Y + attribute \src "ls180.v:5237.11-5237.71" + wire $and$ls180.v:5237$974_Y + attribute \src "ls180.v:5321.43-5321.152" + wire $and$ls180.v:5321$982_Y + attribute \src "ls180.v:5322.41-5322.116" + wire $and$ls180.v:5322$983_Y + attribute \src "ls180.v:5334.48-5334.125" + wire $and$ls180.v:5334$988_Y + attribute \src "ls180.v:5361.9-5361.102" + wire $and$ls180.v:5361$992_Y + attribute \src "ls180.v:5434.9-5434.58" + wire $and$ls180.v:5434$998_Y + attribute \src "ls180.v:5487.51-5487.123" + wire $and$ls180.v:5487$1006_Y + attribute \src "ls180.v:5488.50-5488.120" + wire $and$ls180.v:5488$1007_Y + attribute \src "ls180.v:5489.49-5489.122" + wire $and$ls180.v:5489$1008_Y + attribute \src "ls180.v:5529.43-5529.152" + wire $and$ls180.v:5529$1013_Y + attribute \src "ls180.v:5530.41-5530.116" + wire $and$ls180.v:5530$1014_Y + attribute \src "ls180.v:5621.9-5621.76" + wire $and$ls180.v:5621$1026_Y + attribute \src "ls180.v:5624.44-5624.120" + wire $and$ls180.v:5624$1028_Y + attribute \src "ls180.v:5644.63-5644.107" + wire $and$ls180.v:5644$1030_Y + attribute \src "ls180.v:5645.63-5645.107" + wire $and$ls180.v:5645$1032_Y + attribute \src "ls180.v:5646.63-5646.107" + wire $and$ls180.v:5646$1034_Y + attribute \src "ls180.v:5647.35-5647.79" + wire $and$ls180.v:5647$1036_Y + attribute \src "ls180.v:5648.35-5648.79" + wire $and$ls180.v:5648$1038_Y + attribute \src "ls180.v:5649.63-5649.107" + wire $and$ls180.v:5649$1040_Y + attribute \src "ls180.v:5650.63-5650.107" + wire $and$ls180.v:5650$1042_Y + attribute \src "ls180.v:5651.63-5651.107" + wire $and$ls180.v:5651$1044_Y + attribute \src "ls180.v:5652.35-5652.79" + wire $and$ls180.v:5652$1046_Y + attribute \src "ls180.v:5653.35-5653.79" + wire $and$ls180.v:5653$1048_Y + attribute \src "ls180.v:5698.40-5698.81" + wire $and$ls180.v:5698$1055_Y + attribute \src "ls180.v:5699.50-5699.91" + wire $and$ls180.v:5699$1056_Y + attribute \src "ls180.v:5700.50-5700.91" + wire $and$ls180.v:5700$1057_Y + attribute \src "ls180.v:5701.29-5701.70" + wire $and$ls180.v:5701$1058_Y + attribute \src "ls180.v:5702.44-5702.85" + wire $and$ls180.v:5702$1059_Y + attribute \src "ls180.v:5704.25-5704.64" + wire $and$ls180.v:5704$1064_Y + attribute \src "ls180.v:5704.24-5704.89" + wire $and$ls180.v:5704$1066_Y + attribute \src "ls180.v:5710.31-5710.92" + wire width 32 $and$ls180.v:5710$1072_Y + attribute \src "ls180.v:5710.97-5710.168" + wire width 32 $and$ls180.v:5710$1073_Y + attribute \src "ls180.v:5710.174-5710.245" + wire width 32 $and$ls180.v:5710$1075_Y + attribute \src "ls180.v:5710.251-5710.301" + wire width 32 $and$ls180.v:5710$1077_Y + attribute \src "ls180.v:5710.307-5710.372" + wire width 32 $and$ls180.v:5710$1079_Y + attribute \src "ls180.v:5720.39-5720.92" + wire $and$ls180.v:5720$1083_Y + attribute \src "ls180.v:5720.38-5720.142" + wire $and$ls180.v:5720$1085_Y + attribute \src "ls180.v:5721.39-5721.95" + wire $and$ls180.v:5721$1087_Y + attribute \src "ls180.v:5721.38-5721.145" + wire $and$ls180.v:5721$1089_Y + attribute \src "ls180.v:5723.41-5723.94" + wire $and$ls180.v:5723$1090_Y + attribute \src "ls180.v:5723.40-5723.144" + wire $and$ls180.v:5723$1092_Y + attribute \src "ls180.v:5724.41-5724.97" + wire $and$ls180.v:5724$1094_Y + attribute \src "ls180.v:5724.40-5724.147" + wire $and$ls180.v:5724$1096_Y + attribute \src "ls180.v:5726.41-5726.94" + wire $and$ls180.v:5726$1097_Y + attribute \src "ls180.v:5726.40-5726.144" + wire $and$ls180.v:5726$1099_Y + attribute \src "ls180.v:5727.41-5727.97" + wire $and$ls180.v:5727$1101_Y + attribute \src "ls180.v:5727.40-5727.147" + wire $and$ls180.v:5727$1103_Y + attribute \src "ls180.v:5729.41-5729.94" + wire $and$ls180.v:5729$1104_Y + attribute \src "ls180.v:5729.40-5729.144" + wire $and$ls180.v:5729$1106_Y + attribute \src "ls180.v:5730.41-5730.97" + wire $and$ls180.v:5730$1108_Y + attribute \src "ls180.v:5730.40-5730.147" + wire $and$ls180.v:5730$1110_Y + attribute \src "ls180.v:5732.41-5732.94" + wire $and$ls180.v:5732$1111_Y + attribute \src "ls180.v:5732.40-5732.144" + wire $and$ls180.v:5732$1113_Y + attribute \src "ls180.v:5733.41-5733.97" + wire $and$ls180.v:5733$1115_Y + attribute \src "ls180.v:5733.40-5733.147" + wire $and$ls180.v:5733$1117_Y + attribute \src "ls180.v:5735.44-5735.97" + wire $and$ls180.v:5735$1118_Y + attribute \src "ls180.v:5735.43-5735.147" + wire $and$ls180.v:5735$1120_Y + attribute \src "ls180.v:5736.44-5736.100" + wire $and$ls180.v:5736$1122_Y + attribute \src "ls180.v:5736.43-5736.150" + wire $and$ls180.v:5736$1124_Y + attribute \src "ls180.v:5738.44-5738.97" + wire $and$ls180.v:5738$1125_Y + attribute \src "ls180.v:5738.43-5738.147" + wire $and$ls180.v:5738$1127_Y + attribute \src "ls180.v:5739.44-5739.100" + wire $and$ls180.v:5739$1129_Y + attribute \src "ls180.v:5739.43-5739.150" + wire $and$ls180.v:5739$1131_Y + attribute \src "ls180.v:5741.44-5741.97" + wire $and$ls180.v:5741$1132_Y + attribute \src "ls180.v:5741.43-5741.147" + wire $and$ls180.v:5741$1134_Y + attribute \src "ls180.v:5742.44-5742.100" + wire $and$ls180.v:5742$1136_Y + attribute \src "ls180.v:5742.43-5742.150" + wire $and$ls180.v:5742$1138_Y + attribute \src "ls180.v:5744.44-5744.97" + wire $and$ls180.v:5744$1139_Y + attribute \src "ls180.v:5744.43-5744.147" + wire $and$ls180.v:5744$1141_Y + attribute \src "ls180.v:5745.44-5745.100" + wire $and$ls180.v:5745$1143_Y + attribute \src "ls180.v:5745.43-5745.150" + wire $and$ls180.v:5745$1145_Y + attribute \src "ls180.v:5758.36-5758.89" + wire $and$ls180.v:5758$1147_Y + attribute \src "ls180.v:5758.35-5758.139" + wire $and$ls180.v:5758$1149_Y + attribute \src "ls180.v:5759.36-5759.92" + wire $and$ls180.v:5759$1151_Y + attribute \src "ls180.v:5759.35-5759.142" + wire $and$ls180.v:5759$1153_Y + attribute \src "ls180.v:5761.36-5761.89" + wire $and$ls180.v:5761$1154_Y + attribute \src "ls180.v:5761.35-5761.139" + wire $and$ls180.v:5761$1156_Y + attribute \src "ls180.v:5762.36-5762.92" + wire $and$ls180.v:5762$1158_Y + attribute \src "ls180.v:5762.35-5762.142" + wire $and$ls180.v:5762$1160_Y + attribute \src "ls180.v:5764.36-5764.89" + wire $and$ls180.v:5764$1161_Y + attribute \src "ls180.v:5764.35-5764.139" + wire $and$ls180.v:5764$1163_Y + attribute \src "ls180.v:5765.36-5765.92" + wire $and$ls180.v:5765$1165_Y + attribute \src "ls180.v:5765.35-5765.142" + wire $and$ls180.v:5765$1167_Y + attribute \src "ls180.v:5767.36-5767.89" + wire $and$ls180.v:5767$1168_Y + attribute \src "ls180.v:5767.35-5767.139" + wire $and$ls180.v:5767$1170_Y + attribute \src "ls180.v:5768.36-5768.92" + wire $and$ls180.v:5768$1172_Y + attribute \src "ls180.v:5768.35-5768.142" + wire $and$ls180.v:5768$1174_Y + attribute \src "ls180.v:5770.37-5770.90" + wire $and$ls180.v:5770$1175_Y + attribute \src "ls180.v:5770.36-5770.140" + wire $and$ls180.v:5770$1177_Y + attribute \src "ls180.v:5771.37-5771.93" + wire $and$ls180.v:5771$1179_Y + attribute \src "ls180.v:5771.36-5771.143" + wire $and$ls180.v:5771$1181_Y + attribute \src "ls180.v:5773.37-5773.90" + wire $and$ls180.v:5773$1182_Y + attribute \src "ls180.v:5773.36-5773.140" + wire $and$ls180.v:5773$1184_Y + attribute \src "ls180.v:5774.37-5774.93" + wire $and$ls180.v:5774$1186_Y + attribute \src "ls180.v:5774.36-5774.143" + wire $and$ls180.v:5774$1188_Y + attribute \src "ls180.v:5784.40-5784.93" + wire $and$ls180.v:5784$1190_Y + attribute \src "ls180.v:5784.39-5784.143" + wire $and$ls180.v:5784$1192_Y + attribute \src "ls180.v:5785.40-5785.96" + wire $and$ls180.v:5785$1194_Y + attribute \src "ls180.v:5785.39-5785.146" + wire $and$ls180.v:5785$1196_Y + attribute \src "ls180.v:5787.39-5787.92" + wire $and$ls180.v:5787$1197_Y + attribute \src "ls180.v:5787.38-5787.142" + wire $and$ls180.v:5787$1199_Y + attribute \src "ls180.v:5788.39-5788.95" + wire $and$ls180.v:5788$1201_Y + attribute \src "ls180.v:5788.38-5788.145" + wire $and$ls180.v:5788$1203_Y + attribute \src "ls180.v:5790.39-5790.92" + wire $and$ls180.v:5790$1204_Y + attribute \src "ls180.v:5790.38-5790.142" + wire $and$ls180.v:5790$1206_Y + attribute \src "ls180.v:5791.39-5791.95" + wire $and$ls180.v:5791$1208_Y + attribute \src "ls180.v:5791.38-5791.145" + wire $and$ls180.v:5791$1210_Y + attribute \src "ls180.v:5793.39-5793.92" + wire $and$ls180.v:5793$1211_Y + attribute \src "ls180.v:5793.38-5793.142" + wire $and$ls180.v:5793$1213_Y + attribute \src "ls180.v:5794.39-5794.95" + wire $and$ls180.v:5794$1215_Y + attribute \src "ls180.v:5794.38-5794.145" + wire $and$ls180.v:5794$1217_Y + attribute \src "ls180.v:5796.39-5796.92" + wire $and$ls180.v:5796$1218_Y + attribute \src "ls180.v:5796.38-5796.142" + wire $and$ls180.v:5796$1220_Y + attribute \src "ls180.v:5797.39-5797.95" + wire $and$ls180.v:5797$1222_Y + attribute \src "ls180.v:5797.38-5797.145" + wire $and$ls180.v:5797$1224_Y + attribute \src "ls180.v:5799.40-5799.93" + wire $and$ls180.v:5799$1225_Y + attribute \src "ls180.v:5799.39-5799.143" + wire $and$ls180.v:5799$1227_Y + attribute \src "ls180.v:5800.40-5800.96" + wire $and$ls180.v:5800$1229_Y + attribute \src "ls180.v:5800.39-5800.146" + wire $and$ls180.v:5800$1231_Y + attribute \src "ls180.v:5802.40-5802.93" + wire $and$ls180.v:5802$1232_Y + attribute \src "ls180.v:5802.39-5802.143" + wire $and$ls180.v:5802$1234_Y + attribute \src "ls180.v:5803.40-5803.96" + wire $and$ls180.v:5803$1236_Y + attribute \src "ls180.v:5803.39-5803.146" + wire $and$ls180.v:5803$1238_Y + attribute \src "ls180.v:5805.40-5805.93" + wire $and$ls180.v:5805$1239_Y + attribute \src "ls180.v:5805.39-5805.143" + wire $and$ls180.v:5805$1241_Y + attribute \src "ls180.v:5806.40-5806.96" + wire $and$ls180.v:5806$1243_Y + attribute \src "ls180.v:5806.39-5806.146" + wire $and$ls180.v:5806$1245_Y + attribute \src "ls180.v:5808.40-5808.93" + wire $and$ls180.v:5808$1246_Y + attribute \src "ls180.v:5808.39-5808.143" + wire $and$ls180.v:5808$1248_Y + attribute \src "ls180.v:5809.40-5809.96" + wire $and$ls180.v:5809$1250_Y + attribute \src "ls180.v:5809.39-5809.146" + wire $and$ls180.v:5809$1252_Y + attribute \src "ls180.v:5821.40-5821.93" + wire $and$ls180.v:5821$1254_Y + attribute \src "ls180.v:5821.39-5821.143" + wire $and$ls180.v:5821$1256_Y + attribute \src "ls180.v:5822.40-5822.96" + wire $and$ls180.v:5822$1258_Y + attribute \src "ls180.v:5822.39-5822.146" + wire $and$ls180.v:5822$1260_Y + attribute \src "ls180.v:5824.39-5824.92" + wire $and$ls180.v:5824$1261_Y + attribute \src "ls180.v:5824.38-5824.142" + wire $and$ls180.v:5824$1263_Y + attribute \src "ls180.v:5825.39-5825.95" + wire $and$ls180.v:5825$1265_Y + attribute \src "ls180.v:5825.38-5825.145" + wire $and$ls180.v:5825$1267_Y + attribute \src "ls180.v:5827.39-5827.92" + wire $and$ls180.v:5827$1268_Y + attribute \src "ls180.v:5827.38-5827.142" + wire $and$ls180.v:5827$1270_Y + attribute \src "ls180.v:5828.39-5828.95" + wire $and$ls180.v:5828$1272_Y + attribute \src "ls180.v:5828.38-5828.145" + wire $and$ls180.v:5828$1274_Y + attribute \src "ls180.v:5830.39-5830.92" + wire $and$ls180.v:5830$1275_Y + attribute \src "ls180.v:5830.38-5830.142" + wire $and$ls180.v:5830$1277_Y + attribute \src "ls180.v:5831.39-5831.95" + wire $and$ls180.v:5831$1279_Y + attribute \src "ls180.v:5831.38-5831.145" + wire $and$ls180.v:5831$1281_Y + attribute \src "ls180.v:5833.39-5833.92" + wire $and$ls180.v:5833$1282_Y + attribute \src "ls180.v:5833.38-5833.142" + wire $and$ls180.v:5833$1284_Y + attribute \src "ls180.v:5834.39-5834.95" + wire $and$ls180.v:5834$1286_Y + attribute \src "ls180.v:5834.38-5834.145" + wire $and$ls180.v:5834$1288_Y + attribute \src "ls180.v:5836.40-5836.93" + wire $and$ls180.v:5836$1289_Y + attribute \src "ls180.v:5836.39-5836.143" + wire $and$ls180.v:5836$1291_Y + attribute \src "ls180.v:5837.40-5837.96" + wire $and$ls180.v:5837$1293_Y + attribute \src "ls180.v:5837.39-5837.146" + wire $and$ls180.v:5837$1295_Y + attribute \src "ls180.v:5839.40-5839.93" + wire $and$ls180.v:5839$1296_Y + attribute \src "ls180.v:5839.39-5839.143" + wire $and$ls180.v:5839$1298_Y + attribute \src "ls180.v:5840.40-5840.96" + wire $and$ls180.v:5840$1300_Y + attribute \src "ls180.v:5840.39-5840.146" + wire $and$ls180.v:5840$1302_Y + attribute \src "ls180.v:5842.40-5842.93" + wire $and$ls180.v:5842$1303_Y + attribute \src "ls180.v:5842.39-5842.143" + wire $and$ls180.v:5842$1305_Y + attribute \src "ls180.v:5843.40-5843.96" + wire $and$ls180.v:5843$1307_Y + attribute \src "ls180.v:5843.39-5843.146" + wire $and$ls180.v:5843$1309_Y + attribute \src "ls180.v:5845.40-5845.93" + wire $and$ls180.v:5845$1310_Y + attribute \src "ls180.v:5845.39-5845.143" + wire $and$ls180.v:5845$1312_Y + attribute \src "ls180.v:5846.40-5846.96" + wire $and$ls180.v:5846$1314_Y + attribute \src "ls180.v:5846.39-5846.146" + wire $and$ls180.v:5846$1316_Y + attribute \src "ls180.v:5858.42-5858.95" + wire $and$ls180.v:5858$1318_Y + attribute \src "ls180.v:5858.41-5858.145" + wire $and$ls180.v:5858$1320_Y + attribute \src "ls180.v:5859.42-5859.98" + wire $and$ls180.v:5859$1322_Y + attribute \src "ls180.v:5859.41-5859.148" + wire $and$ls180.v:5859$1324_Y + attribute \src "ls180.v:5861.42-5861.95" + wire $and$ls180.v:5861$1325_Y + attribute \src "ls180.v:5861.41-5861.145" + wire $and$ls180.v:5861$1327_Y + attribute \src "ls180.v:5862.42-5862.98" + wire $and$ls180.v:5862$1329_Y + attribute \src "ls180.v:5862.41-5862.148" + wire $and$ls180.v:5862$1331_Y + attribute \src "ls180.v:5864.42-5864.95" + wire $and$ls180.v:5864$1332_Y + attribute \src "ls180.v:5864.41-5864.145" + wire $and$ls180.v:5864$1334_Y + attribute \src "ls180.v:5865.42-5865.98" + wire $and$ls180.v:5865$1336_Y + attribute \src "ls180.v:5865.41-5865.148" + wire $and$ls180.v:5865$1338_Y + attribute \src "ls180.v:5867.42-5867.95" + wire $and$ls180.v:5867$1339_Y + attribute \src "ls180.v:5867.41-5867.145" + wire $and$ls180.v:5867$1341_Y + attribute \src "ls180.v:5868.42-5868.98" + wire $and$ls180.v:5868$1343_Y + attribute \src "ls180.v:5868.41-5868.148" + wire $and$ls180.v:5868$1345_Y + attribute \src "ls180.v:5870.42-5870.95" + wire $and$ls180.v:5870$1346_Y + attribute \src "ls180.v:5870.41-5870.145" + wire $and$ls180.v:5870$1348_Y + attribute \src "ls180.v:5871.42-5871.98" + wire $and$ls180.v:5871$1350_Y + attribute \src "ls180.v:5871.41-5871.148" + wire $and$ls180.v:5871$1352_Y + attribute \src "ls180.v:5873.42-5873.95" + wire $and$ls180.v:5873$1353_Y + attribute \src "ls180.v:5873.41-5873.145" + wire $and$ls180.v:5873$1355_Y + attribute \src "ls180.v:5874.42-5874.98" + wire $and$ls180.v:5874$1357_Y + attribute \src "ls180.v:5874.41-5874.148" + wire $and$ls180.v:5874$1359_Y + attribute \src "ls180.v:5876.42-5876.95" + wire $and$ls180.v:5876$1360_Y + attribute \src "ls180.v:5876.41-5876.145" + wire $and$ls180.v:5876$1362_Y + attribute \src "ls180.v:5877.42-5877.98" + wire $and$ls180.v:5877$1364_Y + attribute \src "ls180.v:5877.41-5877.148" + wire $and$ls180.v:5877$1366_Y + attribute \src "ls180.v:5879.42-5879.95" + wire $and$ls180.v:5879$1367_Y + attribute \src "ls180.v:5879.41-5879.145" + wire $and$ls180.v:5879$1369_Y + attribute \src "ls180.v:5880.42-5880.98" + wire $and$ls180.v:5880$1371_Y + attribute \src "ls180.v:5880.41-5880.148" + wire $and$ls180.v:5880$1373_Y + attribute \src "ls180.v:5882.44-5882.97" + wire $and$ls180.v:5882$1374_Y + attribute \src "ls180.v:5882.43-5882.147" + wire $and$ls180.v:5882$1376_Y + attribute \src "ls180.v:5883.44-5883.100" + wire $and$ls180.v:5883$1378_Y + attribute \src "ls180.v:5883.43-5883.150" + wire $and$ls180.v:5883$1380_Y + attribute \src "ls180.v:5885.44-5885.97" + wire $and$ls180.v:5885$1381_Y + attribute \src "ls180.v:5885.43-5885.147" + wire $and$ls180.v:5885$1383_Y + attribute \src "ls180.v:5886.44-5886.100" + wire $and$ls180.v:5886$1385_Y + attribute \src "ls180.v:5886.43-5886.150" + wire $and$ls180.v:5886$1387_Y + attribute \src "ls180.v:5888.44-5888.97" + wire $and$ls180.v:5888$1388_Y + attribute \src "ls180.v:5888.43-5888.148" + wire $and$ls180.v:5888$1390_Y + attribute \src "ls180.v:5889.44-5889.100" + wire $and$ls180.v:5889$1392_Y + attribute \src "ls180.v:5889.43-5889.151" + wire $and$ls180.v:5889$1394_Y + attribute \src "ls180.v:5891.44-5891.97" + wire $and$ls180.v:5891$1395_Y + attribute \src "ls180.v:5891.43-5891.148" + wire $and$ls180.v:5891$1397_Y + attribute \src "ls180.v:5892.44-5892.100" + wire $and$ls180.v:5892$1399_Y + attribute \src "ls180.v:5892.43-5892.151" + wire $and$ls180.v:5892$1401_Y + attribute \src "ls180.v:5894.44-5894.97" + wire $and$ls180.v:5894$1402_Y + attribute \src "ls180.v:5894.43-5894.148" + wire $and$ls180.v:5894$1404_Y + attribute \src "ls180.v:5895.44-5895.100" + wire $and$ls180.v:5895$1406_Y + attribute \src "ls180.v:5895.43-5895.151" + wire $and$ls180.v:5895$1408_Y + attribute \src "ls180.v:5897.41-5897.94" + wire $and$ls180.v:5897$1409_Y + attribute \src "ls180.v:5897.40-5897.145" + wire $and$ls180.v:5897$1411_Y + attribute \src "ls180.v:5898.41-5898.97" + wire $and$ls180.v:5898$1413_Y + attribute \src "ls180.v:5898.40-5898.148" + wire $and$ls180.v:5898$1415_Y + attribute \src "ls180.v:5900.42-5900.95" + wire $and$ls180.v:5900$1416_Y + attribute \src "ls180.v:5900.41-5900.146" + wire $and$ls180.v:5900$1418_Y + attribute \src "ls180.v:5901.42-5901.98" + wire $and$ls180.v:5901$1420_Y + attribute \src "ls180.v:5901.41-5901.149" + wire $and$ls180.v:5901$1422_Y + attribute \src "ls180.v:5920.46-5920.99" + wire $and$ls180.v:5920$1424_Y + attribute \src "ls180.v:5920.45-5920.149" + wire $and$ls180.v:5920$1426_Y + attribute \src "ls180.v:5921.46-5921.102" + wire $and$ls180.v:5921$1428_Y + attribute \src "ls180.v:5921.45-5921.152" + wire $and$ls180.v:5921$1430_Y + attribute \src "ls180.v:5923.46-5923.99" + wire $and$ls180.v:5923$1431_Y + attribute \src "ls180.v:5923.45-5923.149" + wire $and$ls180.v:5923$1433_Y + attribute \src "ls180.v:5924.46-5924.102" + wire $and$ls180.v:5924$1435_Y + attribute \src "ls180.v:5924.45-5924.152" + wire $and$ls180.v:5924$1437_Y + attribute \src "ls180.v:5926.46-5926.99" + wire $and$ls180.v:5926$1438_Y + attribute \src "ls180.v:5926.45-5926.149" + wire $and$ls180.v:5926$1440_Y + attribute \src "ls180.v:5927.46-5927.102" + wire $and$ls180.v:5927$1442_Y + attribute \src "ls180.v:5927.45-5927.152" + wire $and$ls180.v:5927$1444_Y + attribute \src "ls180.v:5929.46-5929.99" + wire $and$ls180.v:5929$1445_Y + attribute \src "ls180.v:5929.45-5929.149" + wire $and$ls180.v:5929$1447_Y + attribute \src "ls180.v:5930.46-5930.102" + wire $and$ls180.v:5930$1449_Y + attribute \src "ls180.v:5930.45-5930.152" + wire $and$ls180.v:5930$1451_Y + attribute \src "ls180.v:5932.45-5932.98" + wire $and$ls180.v:5932$1452_Y + attribute \src "ls180.v:5932.44-5932.148" + wire $and$ls180.v:5932$1454_Y + attribute \src "ls180.v:5933.45-5933.101" + wire $and$ls180.v:5933$1456_Y + attribute \src "ls180.v:5933.44-5933.151" + wire $and$ls180.v:5933$1458_Y + attribute \src "ls180.v:5935.45-5935.98" + wire $and$ls180.v:5935$1459_Y + attribute \src "ls180.v:5935.44-5935.148" + wire $and$ls180.v:5935$1461_Y + attribute \src "ls180.v:5936.45-5936.101" + wire $and$ls180.v:5936$1463_Y + attribute \src "ls180.v:5936.44-5936.151" + wire $and$ls180.v:5936$1465_Y + attribute \src "ls180.v:5938.45-5938.98" + wire $and$ls180.v:5938$1466_Y + attribute \src "ls180.v:5938.44-5938.148" + wire $and$ls180.v:5938$1468_Y + attribute \src "ls180.v:5939.45-5939.101" + wire $and$ls180.v:5939$1470_Y + attribute \src "ls180.v:5939.44-5939.151" + wire $and$ls180.v:5939$1472_Y + attribute \src "ls180.v:5941.45-5941.98" + wire $and$ls180.v:5941$1473_Y + attribute \src "ls180.v:5941.44-5941.148" + wire $and$ls180.v:5941$1475_Y + attribute \src "ls180.v:5942.45-5942.101" + wire $and$ls180.v:5942$1477_Y + attribute \src "ls180.v:5942.44-5942.151" + wire $and$ls180.v:5942$1479_Y + attribute \src "ls180.v:5944.36-5944.89" + wire $and$ls180.v:5944$1480_Y + attribute \src "ls180.v:5944.35-5944.139" + wire $and$ls180.v:5944$1482_Y + attribute \src "ls180.v:5945.36-5945.92" + wire $and$ls180.v:5945$1484_Y + attribute \src "ls180.v:5945.35-5945.142" + wire $and$ls180.v:5945$1486_Y + attribute \src "ls180.v:5947.47-5947.100" + wire $and$ls180.v:5947$1487_Y + attribute \src "ls180.v:5947.46-5947.150" + wire $and$ls180.v:5947$1489_Y + attribute \src "ls180.v:5948.47-5948.103" + wire $and$ls180.v:5948$1491_Y + attribute \src "ls180.v:5948.46-5948.153" + wire $and$ls180.v:5948$1493_Y + attribute \src "ls180.v:5950.47-5950.100" + wire $and$ls180.v:5950$1494_Y + attribute \src "ls180.v:5950.46-5950.151" + wire $and$ls180.v:5950$1496_Y + attribute \src "ls180.v:5951.47-5951.103" + wire $and$ls180.v:5951$1498_Y + attribute \src "ls180.v:5951.46-5951.154" + wire $and$ls180.v:5951$1500_Y + attribute \src "ls180.v:5953.47-5953.100" + wire $and$ls180.v:5953$1501_Y + attribute \src "ls180.v:5953.46-5953.151" + wire $and$ls180.v:5953$1503_Y + attribute \src "ls180.v:5954.47-5954.103" + wire $and$ls180.v:5954$1505_Y + attribute \src "ls180.v:5954.46-5954.154" + wire $and$ls180.v:5954$1507_Y + attribute \src "ls180.v:5956.47-5956.100" + wire $and$ls180.v:5956$1508_Y + attribute \src "ls180.v:5956.46-5956.151" + wire $and$ls180.v:5956$1510_Y + attribute \src "ls180.v:5957.47-5957.103" + wire $and$ls180.v:5957$1512_Y + attribute \src "ls180.v:5957.46-5957.154" + wire $and$ls180.v:5957$1514_Y + attribute \src "ls180.v:5959.47-5959.100" + wire $and$ls180.v:5959$1515_Y + attribute \src "ls180.v:5959.46-5959.151" + wire $and$ls180.v:5959$1517_Y + attribute \src "ls180.v:5960.47-5960.103" + wire $and$ls180.v:5960$1519_Y + attribute \src "ls180.v:5960.46-5960.154" + wire $and$ls180.v:5960$1521_Y + attribute \src "ls180.v:5962.47-5962.100" + wire $and$ls180.v:5962$1522_Y + attribute \src "ls180.v:5962.46-5962.151" + wire $and$ls180.v:5962$1524_Y + attribute \src "ls180.v:5963.47-5963.103" + wire $and$ls180.v:5963$1526_Y + attribute \src "ls180.v:5963.46-5963.154" + wire $and$ls180.v:5963$1528_Y + attribute \src "ls180.v:5965.46-5965.99" + wire $and$ls180.v:5965$1529_Y + attribute \src "ls180.v:5965.45-5965.150" + wire $and$ls180.v:5965$1531_Y + attribute \src "ls180.v:5966.46-5966.102" + wire $and$ls180.v:5966$1533_Y + attribute \src "ls180.v:5966.45-5966.153" + wire $and$ls180.v:5966$1535_Y + attribute \src "ls180.v:5968.46-5968.99" + wire $and$ls180.v:5968$1536_Y + attribute \src "ls180.v:5968.45-5968.150" + wire $and$ls180.v:5968$1538_Y + attribute \src "ls180.v:5969.46-5969.102" + wire $and$ls180.v:5969$1540_Y + attribute \src "ls180.v:5969.45-5969.153" + wire $and$ls180.v:5969$1542_Y + attribute \src "ls180.v:5971.46-5971.99" + wire $and$ls180.v:5971$1543_Y + attribute \src "ls180.v:5971.45-5971.150" + wire $and$ls180.v:5971$1545_Y + attribute \src "ls180.v:5972.46-5972.102" + wire $and$ls180.v:5972$1547_Y + attribute \src "ls180.v:5972.45-5972.153" + wire $and$ls180.v:5972$1549_Y + attribute \src "ls180.v:5974.46-5974.99" + wire $and$ls180.v:5974$1550_Y + attribute \src "ls180.v:5974.45-5974.150" + wire $and$ls180.v:5974$1552_Y + attribute \src "ls180.v:5975.46-5975.102" + wire $and$ls180.v:5975$1554_Y + attribute \src "ls180.v:5975.45-5975.153" + wire $and$ls180.v:5975$1556_Y + attribute \src "ls180.v:5977.46-5977.99" + wire $and$ls180.v:5977$1557_Y + attribute \src "ls180.v:5977.45-5977.150" + wire $and$ls180.v:5977$1559_Y + attribute \src "ls180.v:5978.46-5978.102" + wire $and$ls180.v:5978$1561_Y + attribute \src "ls180.v:5978.45-5978.153" + wire $and$ls180.v:5978$1563_Y + attribute \src "ls180.v:5980.46-5980.99" + wire $and$ls180.v:5980$1564_Y + attribute \src "ls180.v:5980.45-5980.150" + wire $and$ls180.v:5980$1566_Y + attribute \src "ls180.v:5981.46-5981.102" + wire $and$ls180.v:5981$1568_Y + attribute \src "ls180.v:5981.45-5981.153" + wire $and$ls180.v:5981$1570_Y + attribute \src "ls180.v:5983.46-5983.99" + wire $and$ls180.v:5983$1571_Y + attribute \src "ls180.v:5983.45-5983.150" + wire $and$ls180.v:5983$1573_Y + attribute \src "ls180.v:5984.46-5984.102" + wire $and$ls180.v:5984$1575_Y + attribute \src "ls180.v:5984.45-5984.153" + wire $and$ls180.v:5984$1577_Y + attribute \src "ls180.v:5986.46-5986.99" + wire $and$ls180.v:5986$1578_Y + attribute \src "ls180.v:5986.45-5986.150" + wire $and$ls180.v:5986$1580_Y + attribute \src "ls180.v:5987.46-5987.102" + wire $and$ls180.v:5987$1582_Y + attribute \src "ls180.v:5987.45-5987.153" + wire $and$ls180.v:5987$1584_Y + attribute \src "ls180.v:5989.46-5989.99" + wire $and$ls180.v:5989$1585_Y + attribute \src "ls180.v:5989.45-5989.150" + wire $and$ls180.v:5989$1587_Y + attribute \src "ls180.v:5990.46-5990.102" + wire $and$ls180.v:5990$1589_Y + attribute \src "ls180.v:5990.45-5990.153" + wire $and$ls180.v:5990$1591_Y + attribute \src "ls180.v:5992.46-5992.99" + wire $and$ls180.v:5992$1592_Y + attribute \src "ls180.v:5992.45-5992.150" + wire $and$ls180.v:5992$1594_Y + attribute \src "ls180.v:5993.46-5993.102" + wire $and$ls180.v:5993$1596_Y + attribute \src "ls180.v:5993.45-5993.153" + wire $and$ls180.v:5993$1598_Y + attribute \src "ls180.v:5995.42-5995.95" + wire $and$ls180.v:5995$1599_Y + attribute \src "ls180.v:5995.41-5995.146" + wire $and$ls180.v:5995$1601_Y + attribute \src "ls180.v:5996.42-5996.98" + wire $and$ls180.v:5996$1603_Y + attribute \src "ls180.v:5996.41-5996.149" + wire $and$ls180.v:5996$1605_Y + attribute \src "ls180.v:5998.43-5998.96" + wire $and$ls180.v:5998$1606_Y + attribute \src "ls180.v:5998.42-5998.147" + wire $and$ls180.v:5998$1608_Y + attribute \src "ls180.v:5999.43-5999.99" + wire $and$ls180.v:5999$1610_Y + attribute \src "ls180.v:5999.42-5999.150" + wire $and$ls180.v:5999$1612_Y + attribute \src "ls180.v:6001.46-6001.99" + wire $and$ls180.v:6001$1613_Y + attribute \src "ls180.v:6001.45-6001.150" + wire $and$ls180.v:6001$1615_Y + attribute \src "ls180.v:6002.46-6002.102" + wire $and$ls180.v:6002$1617_Y + attribute \src "ls180.v:6002.45-6002.153" + wire $and$ls180.v:6002$1619_Y + attribute \src "ls180.v:6004.46-6004.99" + wire $and$ls180.v:6004$1620_Y + attribute \src "ls180.v:6004.45-6004.150" + wire $and$ls180.v:6004$1622_Y + attribute \src "ls180.v:6005.46-6005.102" + wire $and$ls180.v:6005$1624_Y + attribute \src "ls180.v:6005.45-6005.153" + wire $and$ls180.v:6005$1626_Y + attribute \src "ls180.v:6007.45-6007.98" + wire $and$ls180.v:6007$1627_Y + attribute \src "ls180.v:6007.44-6007.149" + wire $and$ls180.v:6007$1629_Y + attribute \src "ls180.v:6008.45-6008.101" + wire $and$ls180.v:6008$1631_Y + attribute \src "ls180.v:6008.44-6008.152" + wire $and$ls180.v:6008$1633_Y + attribute \src "ls180.v:6010.45-6010.98" + wire $and$ls180.v:6010$1634_Y + attribute \src "ls180.v:6010.44-6010.149" + wire $and$ls180.v:6010$1636_Y + attribute \src "ls180.v:6011.45-6011.101" + wire $and$ls180.v:6011$1638_Y + attribute \src "ls180.v:6011.44-6011.152" + wire $and$ls180.v:6011$1640_Y + attribute \src "ls180.v:6013.45-6013.98" + wire $and$ls180.v:6013$1641_Y + attribute \src "ls180.v:6013.44-6013.149" + wire $and$ls180.v:6013$1643_Y + attribute \src "ls180.v:6014.45-6014.101" + wire $and$ls180.v:6014$1645_Y + attribute \src "ls180.v:6014.44-6014.152" + wire $and$ls180.v:6014$1647_Y + attribute \src "ls180.v:6016.45-6016.98" + wire $and$ls180.v:6016$1648_Y + attribute \src "ls180.v:6016.44-6016.149" + wire $and$ls180.v:6016$1650_Y + attribute \src "ls180.v:6017.45-6017.101" + wire $and$ls180.v:6017$1652_Y + attribute \src "ls180.v:6017.44-6017.152" + wire $and$ls180.v:6017$1654_Y + attribute \src "ls180.v:6055.42-6055.95" + wire $and$ls180.v:6055$1656_Y + attribute \src "ls180.v:6055.41-6055.145" + wire $and$ls180.v:6055$1658_Y + attribute \src "ls180.v:6056.42-6056.98" + wire $and$ls180.v:6056$1660_Y + attribute \src "ls180.v:6056.41-6056.148" + wire $and$ls180.v:6056$1662_Y + attribute \src "ls180.v:6058.42-6058.95" + wire $and$ls180.v:6058$1663_Y + attribute \src "ls180.v:6058.41-6058.145" + wire $and$ls180.v:6058$1665_Y + attribute \src "ls180.v:6059.42-6059.98" + wire $and$ls180.v:6059$1667_Y + attribute \src "ls180.v:6059.41-6059.148" + wire $and$ls180.v:6059$1669_Y + attribute \src "ls180.v:6061.42-6061.95" + wire $and$ls180.v:6061$1670_Y + attribute \src "ls180.v:6061.41-6061.145" + wire $and$ls180.v:6061$1672_Y + attribute \src "ls180.v:6062.42-6062.98" + wire $and$ls180.v:6062$1674_Y + attribute \src "ls180.v:6062.41-6062.148" + wire $and$ls180.v:6062$1676_Y + attribute \src "ls180.v:6064.42-6064.95" + wire $and$ls180.v:6064$1677_Y + attribute \src "ls180.v:6064.41-6064.145" + wire $and$ls180.v:6064$1679_Y + attribute \src "ls180.v:6065.42-6065.98" + wire $and$ls180.v:6065$1681_Y + attribute \src "ls180.v:6065.41-6065.148" + wire $and$ls180.v:6065$1683_Y + attribute \src "ls180.v:6067.42-6067.95" + wire $and$ls180.v:6067$1684_Y + attribute \src "ls180.v:6067.41-6067.145" + wire $and$ls180.v:6067$1686_Y + attribute \src "ls180.v:6068.42-6068.98" + wire $and$ls180.v:6068$1688_Y + attribute \src "ls180.v:6068.41-6068.148" + wire $and$ls180.v:6068$1690_Y + attribute \src "ls180.v:6070.42-6070.95" + wire $and$ls180.v:6070$1691_Y + attribute \src "ls180.v:6070.41-6070.145" + wire $and$ls180.v:6070$1693_Y + attribute \src "ls180.v:6071.42-6071.98" + wire $and$ls180.v:6071$1695_Y + attribute \src "ls180.v:6071.41-6071.148" + wire $and$ls180.v:6071$1697_Y + attribute \src "ls180.v:6073.42-6073.95" + wire $and$ls180.v:6073$1698_Y + attribute \src "ls180.v:6073.41-6073.145" + wire $and$ls180.v:6073$1700_Y + attribute \src "ls180.v:6074.42-6074.98" + wire $and$ls180.v:6074$1702_Y + attribute \src "ls180.v:6074.41-6074.148" + wire $and$ls180.v:6074$1704_Y + attribute \src "ls180.v:6076.42-6076.95" + wire $and$ls180.v:6076$1705_Y + attribute \src "ls180.v:6076.41-6076.145" + wire $and$ls180.v:6076$1707_Y + attribute \src "ls180.v:6077.42-6077.98" + wire $and$ls180.v:6077$1709_Y + attribute \src "ls180.v:6077.41-6077.148" + wire $and$ls180.v:6077$1711_Y + attribute \src "ls180.v:6079.44-6079.97" + wire $and$ls180.v:6079$1712_Y + attribute \src "ls180.v:6079.43-6079.147" + wire $and$ls180.v:6079$1714_Y + attribute \src "ls180.v:6080.44-6080.100" + wire $and$ls180.v:6080$1716_Y + attribute \src "ls180.v:6080.43-6080.150" + wire $and$ls180.v:6080$1718_Y + attribute \src "ls180.v:6082.44-6082.97" + wire $and$ls180.v:6082$1719_Y + attribute \src "ls180.v:6082.43-6082.147" + wire $and$ls180.v:6082$1721_Y + attribute \src "ls180.v:6083.44-6083.100" + wire $and$ls180.v:6083$1723_Y + attribute \src "ls180.v:6083.43-6083.150" + wire $and$ls180.v:6083$1725_Y + attribute \src "ls180.v:6085.44-6085.97" + wire $and$ls180.v:6085$1726_Y + attribute \src "ls180.v:6085.43-6085.148" + wire $and$ls180.v:6085$1728_Y + attribute \src "ls180.v:6086.44-6086.100" + wire $and$ls180.v:6086$1730_Y + attribute \src "ls180.v:6086.43-6086.151" + wire $and$ls180.v:6086$1732_Y + attribute \src "ls180.v:6088.44-6088.97" + wire $and$ls180.v:6088$1733_Y + attribute \src "ls180.v:6088.43-6088.148" + wire $and$ls180.v:6088$1735_Y + attribute \src "ls180.v:6089.44-6089.100" + wire $and$ls180.v:6089$1737_Y + attribute \src "ls180.v:6089.43-6089.151" + wire $and$ls180.v:6089$1739_Y + attribute \src "ls180.v:6091.44-6091.97" + wire $and$ls180.v:6091$1740_Y + attribute \src "ls180.v:6091.43-6091.148" + wire $and$ls180.v:6091$1742_Y + attribute \src "ls180.v:6092.44-6092.100" + wire $and$ls180.v:6092$1744_Y + attribute \src "ls180.v:6092.43-6092.151" + wire $and$ls180.v:6092$1746_Y + attribute \src "ls180.v:6094.41-6094.94" + wire $and$ls180.v:6094$1747_Y + attribute \src "ls180.v:6094.40-6094.145" + wire $and$ls180.v:6094$1749_Y + attribute \src "ls180.v:6095.41-6095.97" + wire $and$ls180.v:6095$1751_Y + attribute \src "ls180.v:6095.40-6095.148" + wire $and$ls180.v:6095$1753_Y + attribute \src "ls180.v:6097.42-6097.95" + wire $and$ls180.v:6097$1754_Y + attribute \src "ls180.v:6097.41-6097.146" + wire $and$ls180.v:6097$1756_Y + attribute \src "ls180.v:6098.42-6098.98" + wire $and$ls180.v:6098$1758_Y + attribute \src "ls180.v:6098.41-6098.149" + wire $and$ls180.v:6098$1760_Y + attribute \src "ls180.v:6100.44-6100.97" + wire $and$ls180.v:6100$1761_Y + attribute \src "ls180.v:6100.43-6100.148" + wire $and$ls180.v:6100$1763_Y + attribute \src "ls180.v:6101.44-6101.100" + wire $and$ls180.v:6101$1765_Y + attribute \src "ls180.v:6101.43-6101.151" + wire $and$ls180.v:6101$1767_Y + attribute \src "ls180.v:6103.44-6103.97" + wire $and$ls180.v:6103$1768_Y + attribute \src "ls180.v:6103.43-6103.148" + wire $and$ls180.v:6103$1770_Y + attribute \src "ls180.v:6104.44-6104.100" + wire $and$ls180.v:6104$1772_Y + attribute \src "ls180.v:6104.43-6104.151" + wire $and$ls180.v:6104$1774_Y + attribute \src "ls180.v:6106.44-6106.97" + wire $and$ls180.v:6106$1775_Y + attribute \src "ls180.v:6106.43-6106.148" + wire $and$ls180.v:6106$1777_Y + attribute \src "ls180.v:6107.44-6107.100" + wire $and$ls180.v:6107$1779_Y + attribute \src "ls180.v:6107.43-6107.151" + wire $and$ls180.v:6107$1781_Y + attribute \src "ls180.v:6109.44-6109.97" + wire $and$ls180.v:6109$1782_Y + attribute \src "ls180.v:6109.43-6109.148" + wire $and$ls180.v:6109$1784_Y + attribute \src "ls180.v:6110.44-6110.100" + wire $and$ls180.v:6110$1786_Y + attribute \src "ls180.v:6110.43-6110.151" + wire $and$ls180.v:6110$1788_Y + attribute \src "ls180.v:6134.44-6134.97" + wire $and$ls180.v:6134$1790_Y + attribute \src "ls180.v:6134.43-6134.147" + wire $and$ls180.v:6134$1792_Y + attribute \src "ls180.v:6135.44-6135.100" + wire $and$ls180.v:6135$1794_Y + attribute \src "ls180.v:6135.43-6135.150" + wire $and$ls180.v:6135$1796_Y + attribute \src "ls180.v:6137.49-6137.102" + wire $and$ls180.v:6137$1797_Y + attribute \src "ls180.v:6137.48-6137.152" + wire $and$ls180.v:6137$1799_Y + attribute \src "ls180.v:6138.49-6138.105" + wire $and$ls180.v:6138$1801_Y + attribute \src "ls180.v:6138.48-6138.155" + wire $and$ls180.v:6138$1803_Y + attribute \src "ls180.v:6140.49-6140.102" + wire $and$ls180.v:6140$1804_Y + attribute \src "ls180.v:6140.48-6140.152" + wire $and$ls180.v:6140$1806_Y + attribute \src "ls180.v:6141.49-6141.105" + wire $and$ls180.v:6141$1808_Y + attribute \src "ls180.v:6141.48-6141.155" + wire $and$ls180.v:6141$1810_Y + attribute \src "ls180.v:6143.42-6143.95" + wire $and$ls180.v:6143$1811_Y + attribute \src "ls180.v:6143.41-6143.145" + wire $and$ls180.v:6143$1813_Y + attribute \src "ls180.v:6144.42-6144.98" + wire $and$ls180.v:6144$1815_Y + attribute \src "ls180.v:6144.41-6144.148" + wire $and$ls180.v:6144$1817_Y + attribute \src "ls180.v:6151.46-6151.99" + wire $and$ls180.v:6151$1819_Y + attribute \src "ls180.v:6151.45-6151.149" + wire $and$ls180.v:6151$1821_Y + attribute \src "ls180.v:6152.46-6152.102" + wire $and$ls180.v:6152$1823_Y + attribute \src "ls180.v:6152.45-6152.152" + wire $and$ls180.v:6152$1825_Y + attribute \src "ls180.v:6154.50-6154.103" + wire $and$ls180.v:6154$1826_Y + attribute \src "ls180.v:6154.49-6154.153" + wire $and$ls180.v:6154$1828_Y + attribute \src "ls180.v:6155.50-6155.106" + wire $and$ls180.v:6155$1830_Y + attribute \src "ls180.v:6155.49-6155.156" + wire $and$ls180.v:6155$1832_Y + attribute \src "ls180.v:6157.40-6157.93" + wire $and$ls180.v:6157$1833_Y + attribute \src "ls180.v:6157.39-6157.143" + wire $and$ls180.v:6157$1835_Y + attribute \src "ls180.v:6158.40-6158.96" + wire $and$ls180.v:6158$1837_Y + attribute \src "ls180.v:6158.39-6158.146" + wire $and$ls180.v:6158$1839_Y + attribute \src "ls180.v:6160.50-6160.103" + wire $and$ls180.v:6160$1840_Y + attribute \src "ls180.v:6160.49-6160.153" + wire $and$ls180.v:6160$1842_Y + attribute \src "ls180.v:6161.50-6161.106" + wire $and$ls180.v:6161$1844_Y + attribute \src "ls180.v:6161.49-6161.156" + wire $and$ls180.v:6161$1846_Y + attribute \src "ls180.v:6163.50-6163.103" + wire $and$ls180.v:6163$1847_Y + attribute \src "ls180.v:6163.49-6163.153" + wire $and$ls180.v:6163$1849_Y + attribute \src "ls180.v:6164.50-6164.106" + wire $and$ls180.v:6164$1851_Y + attribute \src "ls180.v:6164.49-6164.156" + wire $and$ls180.v:6164$1853_Y + attribute \src "ls180.v:6166.51-6166.104" + wire $and$ls180.v:6166$1854_Y + attribute \src "ls180.v:6166.50-6166.154" + wire $and$ls180.v:6166$1856_Y + attribute \src "ls180.v:6167.51-6167.107" + wire $and$ls180.v:6167$1858_Y + attribute \src "ls180.v:6167.50-6167.157" + wire $and$ls180.v:6167$1860_Y + attribute \src "ls180.v:6169.49-6169.102" + wire $and$ls180.v:6169$1861_Y + attribute \src "ls180.v:6169.48-6169.152" + wire $and$ls180.v:6169$1863_Y + attribute \src "ls180.v:6170.49-6170.105" + wire $and$ls180.v:6170$1865_Y + attribute \src "ls180.v:6170.48-6170.155" + wire $and$ls180.v:6170$1867_Y + attribute \src "ls180.v:6172.49-6172.102" + wire $and$ls180.v:6172$1868_Y + attribute \src "ls180.v:6172.48-6172.152" + wire $and$ls180.v:6172$1870_Y + attribute \src "ls180.v:6173.49-6173.105" + wire $and$ls180.v:6173$1872_Y + attribute \src "ls180.v:6173.48-6173.155" + wire $and$ls180.v:6173$1874_Y + attribute \src "ls180.v:6175.49-6175.102" + wire $and$ls180.v:6175$1875_Y + attribute \src "ls180.v:6175.48-6175.152" + wire $and$ls180.v:6175$1877_Y + attribute \src "ls180.v:6176.49-6176.105" + wire $and$ls180.v:6176$1879_Y + attribute \src "ls180.v:6176.48-6176.155" + wire $and$ls180.v:6176$1881_Y + attribute \src "ls180.v:6178.49-6178.102" + wire $and$ls180.v:6178$1882_Y + attribute \src "ls180.v:6178.48-6178.152" + wire $and$ls180.v:6178$1884_Y + attribute \src "ls180.v:6179.49-6179.105" + wire $and$ls180.v:6179$1886_Y + attribute \src "ls180.v:6179.48-6179.155" + wire $and$ls180.v:6179$1888_Y + attribute \src "ls180.v:6196.41-6196.94" + wire $and$ls180.v:6196$1890_Y + attribute \src "ls180.v:6196.40-6196.144" + wire $and$ls180.v:6196$1892_Y + attribute \src "ls180.v:6197.41-6197.97" + wire $and$ls180.v:6197$1894_Y + attribute \src "ls180.v:6197.40-6197.147" + wire $and$ls180.v:6197$1896_Y + attribute \src "ls180.v:6199.41-6199.94" + wire $and$ls180.v:6199$1897_Y + attribute \src "ls180.v:6199.40-6199.144" + wire $and$ls180.v:6199$1899_Y + attribute \src "ls180.v:6200.41-6200.97" + wire $and$ls180.v:6200$1901_Y + attribute \src "ls180.v:6200.40-6200.147" + wire $and$ls180.v:6200$1903_Y + attribute \src "ls180.v:6202.39-6202.92" + wire $and$ls180.v:6202$1904_Y + attribute \src "ls180.v:6202.38-6202.142" + wire $and$ls180.v:6202$1906_Y + attribute \src "ls180.v:6203.39-6203.95" + wire $and$ls180.v:6203$1908_Y + attribute \src "ls180.v:6203.38-6203.145" + wire $and$ls180.v:6203$1910_Y + attribute \src "ls180.v:6205.38-6205.91" + wire $and$ls180.v:6205$1911_Y + attribute \src "ls180.v:6205.37-6205.141" + wire $and$ls180.v:6205$1913_Y + attribute \src "ls180.v:6206.38-6206.94" + wire $and$ls180.v:6206$1915_Y + attribute \src "ls180.v:6206.37-6206.144" + wire $and$ls180.v:6206$1917_Y + attribute \src "ls180.v:6208.37-6208.90" + wire $and$ls180.v:6208$1918_Y + attribute \src "ls180.v:6208.36-6208.140" + wire $and$ls180.v:6208$1920_Y + attribute \src "ls180.v:6209.37-6209.93" + wire $and$ls180.v:6209$1922_Y + attribute \src "ls180.v:6209.36-6209.143" + wire $and$ls180.v:6209$1924_Y + attribute \src "ls180.v:6211.36-6211.89" + wire $and$ls180.v:6211$1925_Y + attribute \src "ls180.v:6211.35-6211.139" + wire $and$ls180.v:6211$1927_Y + attribute \src "ls180.v:6212.36-6212.92" + wire $and$ls180.v:6212$1929_Y + attribute \src "ls180.v:6212.35-6212.142" + wire $and$ls180.v:6212$1931_Y + attribute \src "ls180.v:6214.42-6214.95" + wire $and$ls180.v:6214$1932_Y + attribute \src "ls180.v:6214.41-6214.145" + wire $and$ls180.v:6214$1934_Y + attribute \src "ls180.v:6215.42-6215.98" + wire $and$ls180.v:6215$1936_Y + attribute \src "ls180.v:6215.41-6215.148" + wire $and$ls180.v:6215$1938_Y + attribute \src "ls180.v:6236.42-6236.97" + wire $and$ls180.v:6236$1941_Y + attribute \src "ls180.v:6236.41-6236.148" + wire $and$ls180.v:6236$1943_Y + attribute \src "ls180.v:6237.42-6237.100" + wire $and$ls180.v:6237$1945_Y + attribute \src "ls180.v:6237.41-6237.151" + wire $and$ls180.v:6237$1947_Y + attribute \src "ls180.v:6239.42-6239.97" + wire $and$ls180.v:6239$1948_Y + attribute \src "ls180.v:6239.41-6239.148" + wire $and$ls180.v:6239$1950_Y + attribute \src "ls180.v:6240.42-6240.100" + wire $and$ls180.v:6240$1952_Y + attribute \src "ls180.v:6240.41-6240.151" + wire $and$ls180.v:6240$1954_Y + attribute \src "ls180.v:6242.40-6242.95" + wire $and$ls180.v:6242$1955_Y + attribute \src "ls180.v:6242.39-6242.146" + wire $and$ls180.v:6242$1957_Y + attribute \src "ls180.v:6243.40-6243.98" + wire $and$ls180.v:6243$1959_Y + attribute \src "ls180.v:6243.39-6243.149" + wire $and$ls180.v:6243$1961_Y + attribute \src "ls180.v:6245.39-6245.94" + wire $and$ls180.v:6245$1962_Y + attribute \src "ls180.v:6245.38-6245.145" + wire $and$ls180.v:6245$1964_Y + attribute \src "ls180.v:6246.39-6246.97" + wire $and$ls180.v:6246$1966_Y + attribute \src "ls180.v:6246.38-6246.148" + wire $and$ls180.v:6246$1968_Y + attribute \src "ls180.v:6248.38-6248.93" + wire $and$ls180.v:6248$1969_Y + attribute \src "ls180.v:6248.37-6248.144" + wire $and$ls180.v:6248$1971_Y + attribute \src "ls180.v:6249.38-6249.96" + wire $and$ls180.v:6249$1973_Y + attribute \src "ls180.v:6249.37-6249.147" + wire $and$ls180.v:6249$1975_Y + attribute \src "ls180.v:6251.37-6251.92" + wire $and$ls180.v:6251$1976_Y + attribute \src "ls180.v:6251.36-6251.143" + wire $and$ls180.v:6251$1978_Y + attribute \src "ls180.v:6252.37-6252.95" + wire $and$ls180.v:6252$1980_Y + attribute \src "ls180.v:6252.36-6252.146" + wire $and$ls180.v:6252$1982_Y + attribute \src "ls180.v:6254.43-6254.98" + wire $and$ls180.v:6254$1983_Y + attribute \src "ls180.v:6254.42-6254.149" + wire $and$ls180.v:6254$1985_Y + attribute \src "ls180.v:6255.43-6255.101" + wire $and$ls180.v:6255$1987_Y + attribute \src "ls180.v:6255.42-6255.152" + wire $and$ls180.v:6255$1989_Y + attribute \src "ls180.v:6257.46-6257.101" + wire $and$ls180.v:6257$1990_Y + attribute \src "ls180.v:6257.45-6257.152" + wire $and$ls180.v:6257$1992_Y + attribute \src "ls180.v:6258.46-6258.104" + wire $and$ls180.v:6258$1994_Y + attribute \src "ls180.v:6258.45-6258.155" + wire $and$ls180.v:6258$1996_Y + attribute \src "ls180.v:6260.46-6260.101" + wire $and$ls180.v:6260$1997_Y + attribute \src "ls180.v:6260.45-6260.152" + wire $and$ls180.v:6260$1999_Y + attribute \src "ls180.v:6261.46-6261.104" + wire $and$ls180.v:6261$2001_Y + attribute \src "ls180.v:6261.45-6261.155" + wire $and$ls180.v:6261$2003_Y + attribute \src "ls180.v:6284.39-6284.94" + wire $and$ls180.v:6284$2006_Y + attribute \src "ls180.v:6284.38-6284.145" + wire $and$ls180.v:6284$2008_Y + attribute \src "ls180.v:6285.39-6285.97" + wire $and$ls180.v:6285$2010_Y + attribute \src "ls180.v:6285.38-6285.148" + wire $and$ls180.v:6285$2012_Y + attribute \src "ls180.v:6287.39-6287.94" + wire $and$ls180.v:6287$2013_Y + attribute \src "ls180.v:6287.38-6287.145" + wire $and$ls180.v:6287$2015_Y + attribute \src "ls180.v:6288.39-6288.97" + wire $and$ls180.v:6288$2017_Y + attribute \src "ls180.v:6288.38-6288.148" + wire $and$ls180.v:6288$2019_Y + attribute \src "ls180.v:6290.39-6290.94" + wire $and$ls180.v:6290$2020_Y + attribute \src "ls180.v:6290.38-6290.145" + wire $and$ls180.v:6290$2022_Y + attribute \src "ls180.v:6291.39-6291.97" + wire $and$ls180.v:6291$2024_Y + attribute \src "ls180.v:6291.38-6291.148" + wire $and$ls180.v:6291$2026_Y + attribute \src "ls180.v:6293.39-6293.94" + wire $and$ls180.v:6293$2027_Y + attribute \src "ls180.v:6293.38-6293.145" + wire $and$ls180.v:6293$2029_Y + attribute \src "ls180.v:6294.39-6294.97" + wire $and$ls180.v:6294$2031_Y + attribute \src "ls180.v:6294.38-6294.148" + wire $and$ls180.v:6294$2033_Y + attribute \src "ls180.v:6296.41-6296.96" + wire $and$ls180.v:6296$2034_Y + attribute \src "ls180.v:6296.40-6296.147" + wire $and$ls180.v:6296$2036_Y + attribute \src "ls180.v:6297.41-6297.99" + wire $and$ls180.v:6297$2038_Y + attribute \src "ls180.v:6297.40-6297.150" + wire $and$ls180.v:6297$2040_Y + attribute \src "ls180.v:6299.41-6299.96" + wire $and$ls180.v:6299$2041_Y + attribute \src "ls180.v:6299.40-6299.147" + wire $and$ls180.v:6299$2043_Y + attribute \src "ls180.v:6300.41-6300.99" + wire $and$ls180.v:6300$2045_Y + attribute \src "ls180.v:6300.40-6300.150" + wire $and$ls180.v:6300$2047_Y + attribute \src "ls180.v:6302.41-6302.96" + wire $and$ls180.v:6302$2048_Y + attribute \src "ls180.v:6302.40-6302.147" + wire $and$ls180.v:6302$2050_Y + attribute \src "ls180.v:6303.41-6303.99" + wire $and$ls180.v:6303$2052_Y + attribute \src "ls180.v:6303.40-6303.150" + wire $and$ls180.v:6303$2054_Y + attribute \src "ls180.v:6305.41-6305.96" + wire $and$ls180.v:6305$2055_Y + attribute \src "ls180.v:6305.40-6305.147" + wire $and$ls180.v:6305$2057_Y + attribute \src "ls180.v:6306.41-6306.99" + wire $and$ls180.v:6306$2059_Y + attribute \src "ls180.v:6306.40-6306.150" + wire $and$ls180.v:6306$2061_Y + attribute \src "ls180.v:6308.37-6308.92" + wire $and$ls180.v:6308$2062_Y + attribute \src "ls180.v:6308.36-6308.143" + wire $and$ls180.v:6308$2064_Y + attribute \src "ls180.v:6309.37-6309.95" + wire $and$ls180.v:6309$2066_Y + attribute \src "ls180.v:6309.36-6309.146" + wire $and$ls180.v:6309$2068_Y + attribute \src "ls180.v:6311.47-6311.102" + wire $and$ls180.v:6311$2069_Y + attribute \src "ls180.v:6311.46-6311.153" + wire $and$ls180.v:6311$2071_Y + attribute \src "ls180.v:6312.47-6312.105" + wire $and$ls180.v:6312$2073_Y + attribute \src "ls180.v:6312.46-6312.156" + wire $and$ls180.v:6312$2075_Y + attribute \src "ls180.v:6314.40-6314.95" + wire $and$ls180.v:6314$2076_Y + attribute \src "ls180.v:6314.39-6314.147" + wire $and$ls180.v:6314$2078_Y + attribute \src "ls180.v:6315.40-6315.98" + wire $and$ls180.v:6315$2080_Y + attribute \src "ls180.v:6315.39-6315.150" + wire $and$ls180.v:6315$2082_Y + attribute \src "ls180.v:6317.40-6317.95" + wire $and$ls180.v:6317$2083_Y + attribute \src "ls180.v:6317.39-6317.147" + wire $and$ls180.v:6317$2085_Y + attribute \src "ls180.v:6318.40-6318.98" + wire $and$ls180.v:6318$2087_Y + attribute \src "ls180.v:6318.39-6318.150" + wire $and$ls180.v:6318$2089_Y + attribute \src "ls180.v:6320.40-6320.95" + wire $and$ls180.v:6320$2090_Y + attribute \src "ls180.v:6320.39-6320.147" + wire $and$ls180.v:6320$2092_Y + attribute \src "ls180.v:6321.40-6321.98" + wire $and$ls180.v:6321$2094_Y + attribute \src "ls180.v:6321.39-6321.150" + wire $and$ls180.v:6321$2096_Y + attribute \src "ls180.v:6323.40-6323.95" + wire $and$ls180.v:6323$2097_Y + attribute \src "ls180.v:6323.39-6323.147" + wire $and$ls180.v:6323$2099_Y + attribute \src "ls180.v:6324.40-6324.98" + wire $and$ls180.v:6324$2101_Y + attribute \src "ls180.v:6324.39-6324.150" + wire $and$ls180.v:6324$2103_Y + attribute \src "ls180.v:6326.52-6326.107" + wire $and$ls180.v:6326$2104_Y + attribute \src "ls180.v:6326.51-6326.159" + wire $and$ls180.v:6326$2106_Y + attribute \src "ls180.v:6327.52-6327.110" + wire $and$ls180.v:6327$2108_Y + attribute \src "ls180.v:6327.51-6327.162" + wire $and$ls180.v:6327$2110_Y + attribute \src "ls180.v:6329.53-6329.108" + wire $and$ls180.v:6329$2111_Y + attribute \src "ls180.v:6329.52-6329.160" + wire $and$ls180.v:6329$2113_Y + attribute \src "ls180.v:6330.53-6330.111" + wire $and$ls180.v:6330$2115_Y + attribute \src "ls180.v:6330.52-6330.163" + wire $and$ls180.v:6330$2117_Y + attribute \src "ls180.v:6332.44-6332.99" + wire $and$ls180.v:6332$2118_Y + attribute \src "ls180.v:6332.43-6332.151" + wire $and$ls180.v:6332$2120_Y + attribute \src "ls180.v:6333.44-6333.102" + wire $and$ls180.v:6333$2122_Y + attribute \src "ls180.v:6333.43-6333.154" + wire $and$ls180.v:6333$2124_Y + attribute \src "ls180.v:6352.30-6352.85" + wire $and$ls180.v:6352$2126_Y + attribute \src "ls180.v:6352.29-6352.136" + wire $and$ls180.v:6352$2128_Y + attribute \src "ls180.v:6353.30-6353.88" + wire $and$ls180.v:6353$2130_Y + attribute \src "ls180.v:6353.29-6353.139" + wire $and$ls180.v:6353$2132_Y + attribute \src "ls180.v:6355.40-6355.95" + wire $and$ls180.v:6355$2133_Y + attribute \src "ls180.v:6355.39-6355.146" + wire $and$ls180.v:6355$2135_Y + attribute \src "ls180.v:6356.40-6356.98" + wire $and$ls180.v:6356$2137_Y + attribute \src "ls180.v:6356.39-6356.149" + wire $and$ls180.v:6356$2139_Y + attribute \src "ls180.v:6358.41-6358.96" + wire $and$ls180.v:6358$2140_Y + attribute \src "ls180.v:6358.40-6358.147" + wire $and$ls180.v:6358$2142_Y + attribute \src "ls180.v:6359.41-6359.99" + wire $and$ls180.v:6359$2144_Y + attribute \src "ls180.v:6359.40-6359.150" + wire $and$ls180.v:6359$2146_Y + attribute \src "ls180.v:6361.45-6361.100" + wire $and$ls180.v:6361$2147_Y + attribute \src "ls180.v:6361.44-6361.151" + wire $and$ls180.v:6361$2149_Y + attribute \src "ls180.v:6362.45-6362.103" + wire $and$ls180.v:6362$2151_Y + attribute \src "ls180.v:6362.44-6362.154" + wire $and$ls180.v:6362$2153_Y + attribute \src "ls180.v:6364.46-6364.101" + wire $and$ls180.v:6364$2154_Y + attribute \src "ls180.v:6364.45-6364.152" + wire $and$ls180.v:6364$2156_Y + attribute \src "ls180.v:6365.46-6365.104" + wire $and$ls180.v:6365$2158_Y + attribute \src "ls180.v:6365.45-6365.155" + wire $and$ls180.v:6365$2160_Y + attribute \src "ls180.v:6367.44-6367.99" + wire $and$ls180.v:6367$2161_Y + attribute \src "ls180.v:6367.43-6367.150" + wire $and$ls180.v:6367$2163_Y + attribute \src "ls180.v:6368.44-6368.102" + wire $and$ls180.v:6368$2165_Y + attribute \src "ls180.v:6368.43-6368.153" + wire $and$ls180.v:6368$2167_Y + attribute \src "ls180.v:6370.41-6370.96" + wire $and$ls180.v:6370$2168_Y + attribute \src "ls180.v:6370.40-6370.147" + wire $and$ls180.v:6370$2170_Y + attribute \src "ls180.v:6371.41-6371.99" + wire $and$ls180.v:6371$2172_Y + attribute \src "ls180.v:6371.40-6371.150" + wire $and$ls180.v:6371$2174_Y + attribute \src "ls180.v:6373.40-6373.95" + wire $and$ls180.v:6373$2175_Y + attribute \src "ls180.v:6373.39-6373.146" + wire $and$ls180.v:6373$2177_Y + attribute \src "ls180.v:6374.40-6374.98" + wire $and$ls180.v:6374$2179_Y + attribute \src "ls180.v:6374.39-6374.149" + wire $and$ls180.v:6374$2181_Y + attribute \src "ls180.v:6386.46-6386.101" + wire $and$ls180.v:6386$2183_Y + attribute \src "ls180.v:6386.45-6386.152" + wire $and$ls180.v:6386$2185_Y + attribute \src "ls180.v:6387.46-6387.104" + wire $and$ls180.v:6387$2187_Y + attribute \src "ls180.v:6387.45-6387.155" + wire $and$ls180.v:6387$2189_Y + attribute \src "ls180.v:6389.46-6389.101" + wire $and$ls180.v:6389$2190_Y + attribute \src "ls180.v:6389.45-6389.152" + wire $and$ls180.v:6389$2192_Y + attribute \src "ls180.v:6390.46-6390.104" + wire $and$ls180.v:6390$2194_Y + attribute \src "ls180.v:6390.45-6390.155" + wire $and$ls180.v:6390$2196_Y + attribute \src "ls180.v:6392.46-6392.101" + wire $and$ls180.v:6392$2197_Y + attribute \src "ls180.v:6392.45-6392.152" + wire $and$ls180.v:6392$2199_Y + attribute \src "ls180.v:6393.46-6393.104" + wire $and$ls180.v:6393$2201_Y + attribute \src "ls180.v:6393.45-6393.155" + wire $and$ls180.v:6393$2203_Y + attribute \src "ls180.v:6395.46-6395.101" + wire $and$ls180.v:6395$2204_Y + attribute \src "ls180.v:6395.45-6395.152" + wire $and$ls180.v:6395$2206_Y + attribute \src "ls180.v:6396.46-6396.104" + wire $and$ls180.v:6396$2208_Y + attribute \src "ls180.v:6396.45-6396.155" + wire $and$ls180.v:6396$2210_Y + attribute \src "ls180.v:6774.109-6774.178" + wire $and$ls180.v:6774$2247_Y + attribute \src "ls180.v:6774.184-6774.253" + wire $and$ls180.v:6774$2250_Y + attribute \src "ls180.v:6774.259-6774.328" + wire $and$ls180.v:6774$2253_Y + attribute \src "ls180.v:6774.40-6774.331" + wire $and$ls180.v:6774$2256_Y + attribute \src "ls180.v:6774.39-6774.354" + wire $and$ls180.v:6774$2257_Y + attribute \src "ls180.v:6798.109-6798.178" + wire $and$ls180.v:6798$2263_Y + attribute \src "ls180.v:6798.184-6798.253" + wire $and$ls180.v:6798$2266_Y + attribute \src "ls180.v:6798.259-6798.328" + wire $and$ls180.v:6798$2269_Y + attribute \src "ls180.v:6798.40-6798.331" + wire $and$ls180.v:6798$2272_Y + attribute \src "ls180.v:6798.39-6798.354" + wire $and$ls180.v:6798$2273_Y + attribute \src "ls180.v:6822.109-6822.178" + wire $and$ls180.v:6822$2279_Y + attribute \src "ls180.v:6822.184-6822.253" + wire $and$ls180.v:6822$2282_Y + attribute \src "ls180.v:6822.259-6822.328" + wire $and$ls180.v:6822$2285_Y + attribute \src "ls180.v:6822.40-6822.331" + wire $and$ls180.v:6822$2288_Y + attribute \src "ls180.v:6822.39-6822.354" + wire $and$ls180.v:6822$2289_Y + attribute \src "ls180.v:6846.109-6846.178" + wire $and$ls180.v:6846$2295_Y + attribute \src "ls180.v:6846.184-6846.253" + wire $and$ls180.v:6846$2298_Y + attribute \src "ls180.v:6846.259-6846.328" + wire $and$ls180.v:6846$2301_Y + attribute \src "ls180.v:6846.40-6846.331" + wire $and$ls180.v:6846$2304_Y + attribute \src "ls180.v:6846.39-6846.354" + wire $and$ls180.v:6846$2305_Y + attribute \src "ls180.v:7051.39-7051.104" + wire $and$ls180.v:7051$2317_Y + attribute \src "ls180.v:7051.38-7051.145" + wire $and$ls180.v:7051$2318_Y + attribute \src "ls180.v:7054.39-7054.104" + wire $and$ls180.v:7054$2319_Y + attribute \src "ls180.v:7054.38-7054.145" + wire $and$ls180.v:7054$2320_Y + attribute \src "ls180.v:7057.39-7057.82" + wire $and$ls180.v:7057$2321_Y + attribute \src "ls180.v:7057.38-7057.112" + wire $and$ls180.v:7057$2322_Y + attribute \src "ls180.v:7068.39-7068.104" + wire $and$ls180.v:7068$2324_Y + attribute \src "ls180.v:7068.38-7068.145" + wire $and$ls180.v:7068$2325_Y + attribute \src "ls180.v:7071.39-7071.104" + wire $and$ls180.v:7071$2326_Y + attribute \src "ls180.v:7071.38-7071.145" + wire $and$ls180.v:7071$2327_Y + attribute \src "ls180.v:7074.39-7074.82" + wire $and$ls180.v:7074$2328_Y + attribute \src "ls180.v:7074.38-7074.112" + wire $and$ls180.v:7074$2329_Y + attribute \src "ls180.v:7085.39-7085.104" + wire $and$ls180.v:7085$2331_Y + attribute \src "ls180.v:7085.38-7085.144" + wire $and$ls180.v:7085$2332_Y + attribute \src "ls180.v:7088.39-7088.104" + wire $and$ls180.v:7088$2333_Y + attribute \src "ls180.v:7088.38-7088.144" + wire $and$ls180.v:7088$2334_Y + attribute \src "ls180.v:7091.39-7091.82" + wire $and$ls180.v:7091$2335_Y + attribute \src "ls180.v:7091.38-7091.111" + wire $and$ls180.v:7091$2336_Y + attribute \src "ls180.v:7102.39-7102.104" + wire $and$ls180.v:7102$2338_Y + attribute \src "ls180.v:7102.38-7102.149" + wire $and$ls180.v:7102$2339_Y + attribute \src "ls180.v:7105.39-7105.104" + wire $and$ls180.v:7105$2340_Y + attribute \src "ls180.v:7105.38-7105.149" + wire $and$ls180.v:7105$2341_Y + attribute \src "ls180.v:7108.39-7108.82" + wire $and$ls180.v:7108$2342_Y + attribute \src "ls180.v:7108.38-7108.116" + wire $and$ls180.v:7108$2343_Y + attribute \src "ls180.v:7119.39-7119.104" + wire $and$ls180.v:7119$2345_Y + attribute \src "ls180.v:7119.38-7119.150" + wire $and$ls180.v:7119$2346_Y + attribute \src "ls180.v:7122.39-7122.104" + wire $and$ls180.v:7122$2347_Y + attribute \src "ls180.v:7122.38-7122.150" + wire $and$ls180.v:7122$2348_Y + attribute \src "ls180.v:7125.39-7125.82" + wire $and$ls180.v:7125$2349_Y + attribute \src "ls180.v:7125.38-7125.117" + wire $and$ls180.v:7125$2350_Y + attribute \src "ls180.v:7344.17-7344.67" + wire $and$ls180.v:7344$2357_Y + attribute \src "ls180.v:7441.8-7441.67" + wire $and$ls180.v:7441$2406_Y + attribute \src "ls180.v:7441.7-7441.102" + wire $and$ls180.v:7441$2408_Y + attribute \src "ls180.v:7460.7-7460.75" + wire $and$ls180.v:7460$2412_Y + attribute \src "ls180.v:7468.7-7468.56" + wire $and$ls180.v:7468$2414_Y + attribute \src "ls180.v:7496.7-7496.75" + wire $and$ls180.v:7496$2421_Y + attribute \src "ls180.v:7538.8-7538.131" + wire $and$ls180.v:7538$2427_Y + attribute \src "ls180.v:7538.7-7538.190" + wire $and$ls180.v:7538$2429_Y + attribute \src "ls180.v:7544.8-7544.131" + wire $and$ls180.v:7544$2432_Y + attribute \src "ls180.v:7544.7-7544.190" + wire $and$ls180.v:7544$2434_Y + attribute \src "ls180.v:7584.8-7584.131" + wire $and$ls180.v:7584$2443_Y + attribute \src "ls180.v:7584.7-7584.190" + wire $and$ls180.v:7584$2445_Y + attribute \src "ls180.v:7590.8-7590.131" + wire $and$ls180.v:7590$2448_Y + attribute \src "ls180.v:7590.7-7590.190" + wire $and$ls180.v:7590$2450_Y + attribute \src "ls180.v:7630.8-7630.131" + wire $and$ls180.v:7630$2459_Y + attribute \src "ls180.v:7630.7-7630.190" + wire $and$ls180.v:7630$2461_Y + attribute \src "ls180.v:7636.8-7636.131" + wire $and$ls180.v:7636$2464_Y + attribute \src "ls180.v:7636.7-7636.190" + wire $and$ls180.v:7636$2466_Y + attribute \src "ls180.v:7676.8-7676.131" + wire $and$ls180.v:7676$2475_Y + attribute \src "ls180.v:7676.7-7676.190" + wire $and$ls180.v:7676$2477_Y + attribute \src "ls180.v:7682.8-7682.131" + wire $and$ls180.v:7682$2480_Y + attribute \src "ls180.v:7682.7-7682.190" + wire $and$ls180.v:7682$2482_Y + attribute \src "ls180.v:7879.48-7879.124" + wire $and$ls180.v:7879$2507_Y + attribute \src "ls180.v:7879.130-7879.206" + wire $and$ls180.v:7879$2510_Y + attribute \src "ls180.v:7879.212-7879.288" + wire $and$ls180.v:7879$2513_Y + attribute \src "ls180.v:7879.294-7879.370" + wire $and$ls180.v:7879$2516_Y + attribute \src "ls180.v:7880.49-7880.125" + wire $and$ls180.v:7880$2519_Y + attribute \src "ls180.v:7880.131-7880.207" + wire $and$ls180.v:7880$2522_Y + attribute \src "ls180.v:7880.213-7880.289" + wire $and$ls180.v:7880$2525_Y + attribute \src "ls180.v:7880.295-7880.371" + wire $and$ls180.v:7880$2528_Y + attribute \src "ls180.v:7899.8-7899.49" + wire $and$ls180.v:7899$2531_Y + attribute \src "ls180.v:7902.8-7902.53" + wire $and$ls180.v:7902$2532_Y + attribute \src "ls180.v:7907.8-7907.41" + wire $and$ls180.v:7907$2534_Y + attribute \src "ls180.v:7907.7-7907.63" + wire $and$ls180.v:7907$2536_Y + attribute \src "ls180.v:7913.8-7913.41" + wire $and$ls180.v:7913$2537_Y + attribute \src "ls180.v:7937.8-7937.30" + wire $and$ls180.v:7937$2544_Y + attribute \src "ls180.v:7970.7-7970.57" + wire $and$ls180.v:7970$2550_Y + attribute \src "ls180.v:7977.7-7977.57" + wire $and$ls180.v:7977$2552_Y + attribute \src "ls180.v:7987.8-7987.75" + wire $and$ls180.v:7987$2553_Y + attribute \src "ls180.v:7987.7-7987.107" + wire $and$ls180.v:7987$2555_Y + attribute \src "ls180.v:7993.8-7993.75" + wire $and$ls180.v:7993$2558_Y + attribute \src "ls180.v:7993.7-7993.107" + wire $and$ls180.v:7993$2560_Y + attribute \src "ls180.v:8009.8-8009.75" + wire $and$ls180.v:8009$2564_Y + attribute \src "ls180.v:8009.7-8009.107" + wire $and$ls180.v:8009$2566_Y + attribute \src "ls180.v:8015.8-8015.75" + wire $and$ls180.v:8015$2569_Y + attribute \src "ls180.v:8015.7-8015.107" + wire $and$ls180.v:8015$2571_Y + attribute \src "ls180.v:8128.7-8128.96" + wire $and$ls180.v:8128$2594_Y + attribute \src "ls180.v:8129.8-8129.93" + wire $and$ls180.v:8129$2595_Y + attribute \src "ls180.v:8137.8-8137.93" + wire $and$ls180.v:8137$2596_Y + attribute \src "ls180.v:8209.7-8209.98" + wire $and$ls180.v:8209$2606_Y + attribute \src "ls180.v:8210.8-8210.95" + wire $and$ls180.v:8210$2607_Y + attribute \src "ls180.v:8218.8-8218.95" + wire $and$ls180.v:8218$2608_Y + attribute \src "ls180.v:8288.7-8288.100" + wire $and$ls180.v:8288$2618_Y + attribute \src "ls180.v:8289.8-8289.97" + wire $and$ls180.v:8289$2619_Y + attribute \src "ls180.v:8297.8-8297.97" + wire $and$ls180.v:8297$2620_Y + attribute \src "ls180.v:8388.7-8388.82" + wire $and$ls180.v:8388$2626_Y + attribute \src "ls180.v:8391.7-8391.82" + wire $and$ls180.v:8391$2627_Y + attribute \src "ls180.v:8394.7-8394.82" + wire $and$ls180.v:8394$2628_Y + attribute \src "ls180.v:8397.7-8397.82" + wire $and$ls180.v:8397$2629_Y + attribute \src "ls180.v:8400.7-8400.82" + wire $and$ls180.v:8400$2630_Y + attribute \src "ls180.v:8405.7-8405.82" + wire $and$ls180.v:8405$2631_Y + attribute \src "ls180.v:8410.7-8410.82" + wire $and$ls180.v:8410$2632_Y + attribute \src "ls180.v:8415.7-8415.82" + wire $and$ls180.v:8415$2633_Y + attribute \src "ls180.v:8420.7-8420.82" + wire $and$ls180.v:8420$2634_Y + attribute \src "ls180.v:8485.8-8485.83" + wire $and$ls180.v:8485$2637_Y + attribute \src "ls180.v:8485.7-8485.119" + wire $and$ls180.v:8485$2639_Y + attribute \src "ls180.v:8491.8-8491.83" + wire $and$ls180.v:8491$2642_Y + attribute \src "ls180.v:8491.7-8491.119" + wire $and$ls180.v:8491$2644_Y + attribute \src "ls180.v:8511.7-8511.88" + wire $and$ls180.v:8511$2651_Y + attribute \src "ls180.v:8512.8-8512.85" + wire $and$ls180.v:8512$2652_Y + attribute \src "ls180.v:8520.8-8520.85" + wire $and$ls180.v:8520$2653_Y + attribute \src "ls180.v:8564.7-8564.88" + wire $and$ls180.v:8564$2657_Y + attribute \src "ls180.v:8571.8-8571.83" + wire $and$ls180.v:8571$2659_Y + attribute \src "ls180.v:8571.7-8571.119" + wire $and$ls180.v:8571$2661_Y + attribute \src "ls180.v:8577.8-8577.83" + wire $and$ls180.v:8577$2664_Y + attribute \src "ls180.v:8577.7-8577.119" + wire $and$ls180.v:8577$2666_Y + attribute \src "ls180.v:2763.42-2763.101" + wire $eq$ls180.v:2763$18_Y + attribute \src "ls180.v:2770.11-2770.54" + wire $eq$ls180.v:2770$23_Y + attribute \src "ls180.v:2823.42-2823.101" + wire $eq$ls180.v:2823$29_Y + attribute \src "ls180.v:2830.11-2830.54" + wire $eq$ls180.v:2830$34_Y + attribute \src "ls180.v:2883.42-2883.101" + wire $eq$ls180.v:2883$40_Y + attribute \src "ls180.v:2890.11-2890.54" + wire $eq$ls180.v:2890$45_Y + attribute \src "ls180.v:3076.34-3076.65" + wire $eq$ls180.v:3076$73_Y + attribute \src "ls180.v:3080.68-3080.102" + wire $eq$ls180.v:3080$76_Y + attribute \src "ls180.v:3124.43-3124.134" + wire $eq$ls180.v:3124$81_Y + attribute \src "ls180.v:3141.47-3141.88" + wire $eq$ls180.v:3141$94_Y + attribute \src "ls180.v:3281.43-3281.134" + wire $eq$ls180.v:3281$111_Y + attribute \src "ls180.v:3298.47-3298.88" + wire $eq$ls180.v:3298$124_Y + attribute \src "ls180.v:3438.43-3438.134" + wire $eq$ls180.v:3438$141_Y + attribute \src "ls180.v:3455.47-3455.88" + wire $eq$ls180.v:3455$154_Y + attribute \src "ls180.v:3595.43-3595.134" + wire $eq$ls180.v:3595$171_Y + attribute \src "ls180.v:3612.47-3612.88" + wire $eq$ls180.v:3612$184_Y + attribute \src "ls180.v:3749.32-3749.56" + wire $eq$ls180.v:3749$231_Y + attribute \src "ls180.v:3750.32-3750.56" + wire $eq$ls180.v:3750$232_Y + attribute \src "ls180.v:3761.339-3761.418" + wire $eq$ls180.v:3761$246_Y + attribute \src "ls180.v:3761.423-3761.504" + wire $eq$ls180.v:3761$247_Y + attribute \src "ls180.v:3762.339-3762.418" + wire $eq$ls180.v:3762$259_Y + attribute \src "ls180.v:3762.423-3762.504" + wire $eq$ls180.v:3762$260_Y + attribute \src "ls180.v:3763.339-3763.418" + wire $eq$ls180.v:3763$272_Y + attribute \src "ls180.v:3763.423-3763.504" + wire $eq$ls180.v:3763$273_Y + attribute \src "ls180.v:3764.339-3764.418" + wire $eq$ls180.v:3764$285_Y + attribute \src "ls180.v:3764.423-3764.504" + wire $eq$ls180.v:3764$286_Y + attribute \src "ls180.v:3794.339-3794.418" + wire $eq$ls180.v:3794$304_Y + attribute \src "ls180.v:3794.423-3794.504" + wire $eq$ls180.v:3794$305_Y + attribute \src "ls180.v:3795.339-3795.418" + wire $eq$ls180.v:3795$317_Y + attribute \src "ls180.v:3795.423-3795.504" + wire $eq$ls180.v:3795$318_Y + attribute \src "ls180.v:3796.339-3796.418" + wire $eq$ls180.v:3796$330_Y + attribute \src "ls180.v:3796.423-3796.504" + wire $eq$ls180.v:3796$331_Y + attribute \src "ls180.v:3797.339-3797.418" + wire $eq$ls180.v:3797$343_Y + attribute \src "ls180.v:3797.423-3797.504" + wire $eq$ls180.v:3797$344_Y + attribute \src "ls180.v:3826.78-3826.113" + wire $eq$ls180.v:3826$353_Y + attribute \src "ls180.v:3829.78-3829.113" + wire $eq$ls180.v:3829$356_Y + attribute \src "ls180.v:3835.78-3835.113" + wire $eq$ls180.v:3835$360_Y + attribute \src "ls180.v:3838.78-3838.113" + wire $eq$ls180.v:3838$363_Y + attribute \src "ls180.v:3844.78-3844.113" + wire $eq$ls180.v:3844$367_Y + attribute \src "ls180.v:3847.78-3847.113" + wire $eq$ls180.v:3847$370_Y + attribute \src "ls180.v:3853.78-3853.113" + wire $eq$ls180.v:3853$374_Y + attribute \src "ls180.v:3856.78-3856.113" + wire $eq$ls180.v:3856$377_Y + attribute \src "ls180.v:3937.42-3937.82" + wire $eq$ls180.v:3937$400_Y + attribute \src "ls180.v:3937.145-3937.178" + wire $eq$ls180.v:3937$401_Y + attribute \src "ls180.v:3937.220-3937.253" + wire $eq$ls180.v:3937$404_Y + attribute \src "ls180.v:3937.295-3937.328" + wire $eq$ls180.v:3937$407_Y + attribute \src "ls180.v:3942.42-3942.82" + wire $eq$ls180.v:3942$416_Y + attribute \src "ls180.v:3942.145-3942.178" + wire $eq$ls180.v:3942$417_Y + attribute \src "ls180.v:3942.220-3942.253" + wire $eq$ls180.v:3942$420_Y + attribute \src "ls180.v:3942.295-3942.328" + wire $eq$ls180.v:3942$423_Y + attribute \src "ls180.v:3947.42-3947.82" + wire $eq$ls180.v:3947$432_Y + attribute \src "ls180.v:3947.145-3947.178" + wire $eq$ls180.v:3947$433_Y + attribute \src "ls180.v:3947.220-3947.253" + wire $eq$ls180.v:3947$436_Y + attribute \src "ls180.v:3947.295-3947.328" + wire $eq$ls180.v:3947$439_Y + attribute \src "ls180.v:3952.42-3952.82" + wire $eq$ls180.v:3952$448_Y + attribute \src "ls180.v:3952.145-3952.178" + wire $eq$ls180.v:3952$449_Y + attribute \src "ls180.v:3952.220-3952.253" + wire $eq$ls180.v:3952$452_Y + attribute \src "ls180.v:3952.295-3952.328" + wire $eq$ls180.v:3952$455_Y + attribute \src "ls180.v:3957.44-3957.77" + wire $eq$ls180.v:3957$464_Y + attribute \src "ls180.v:3957.83-3957.123" + wire $eq$ls180.v:3957$465_Y + attribute \src "ls180.v:3957.186-3957.219" + wire $eq$ls180.v:3957$466_Y + attribute \src "ls180.v:3957.261-3957.294" + wire $eq$ls180.v:3957$469_Y + attribute \src "ls180.v:3957.336-3957.369" + wire $eq$ls180.v:3957$472_Y + attribute \src "ls180.v:3957.418-3957.451" + wire $eq$ls180.v:3957$480_Y + attribute \src "ls180.v:3957.457-3957.497" + wire $eq$ls180.v:3957$481_Y + attribute \src "ls180.v:3957.560-3957.593" + wire $eq$ls180.v:3957$482_Y + attribute \src "ls180.v:3957.635-3957.668" + wire $eq$ls180.v:3957$485_Y + attribute \src "ls180.v:3957.710-3957.743" + wire $eq$ls180.v:3957$488_Y + attribute \src "ls180.v:3957.792-3957.825" + wire $eq$ls180.v:3957$496_Y + attribute \src "ls180.v:3957.831-3957.871" + wire $eq$ls180.v:3957$497_Y + attribute \src "ls180.v:3957.934-3957.967" + wire $eq$ls180.v:3957$498_Y + attribute \src "ls180.v:3957.1009-3957.1042" + wire $eq$ls180.v:3957$501_Y + attribute \src "ls180.v:3957.1084-3957.1117" + wire $eq$ls180.v:3957$504_Y + attribute \src "ls180.v:3957.1166-3957.1199" + wire $eq$ls180.v:3957$512_Y + attribute \src "ls180.v:3957.1205-3957.1245" + wire $eq$ls180.v:3957$513_Y + attribute \src "ls180.v:3957.1308-3957.1341" + wire $eq$ls180.v:3957$514_Y + attribute \src "ls180.v:3957.1383-3957.1416" + wire $eq$ls180.v:3957$517_Y + attribute \src "ls180.v:3957.1458-3957.1491" + wire $eq$ls180.v:3957$520_Y + attribute \src "ls180.v:4016.29-4016.57" + wire $eq$ls180.v:4016$533_Y + attribute \src "ls180.v:4023.11-4023.41" + wire $eq$ls180.v:4023$538_Y + attribute \src "ls180.v:4180.36-4180.111" + wire $eq$ls180.v:4180$603_Y + attribute \src "ls180.v:4181.36-4181.105" + wire $eq$ls180.v:4181$605_Y + attribute \src "ls180.v:4208.10-4208.67" + wire $eq$ls180.v:4208$609_Y + attribute \src "ls180.v:4308.10-4308.40" + wire $eq$ls180.v:4308$636_Y + attribute \src "ls180.v:4365.10-4365.39" + wire $eq$ls180.v:4365$639_Y + attribute \src "ls180.v:4382.10-4382.39" + wire $eq$ls180.v:4382$641_Y + attribute \src "ls180.v:4410.38-4410.88" + wire $eq$ls180.v:4410$643_Y + attribute \src "ls180.v:4460.9-4460.40" + wire $eq$ls180.v:4460$653_Y + attribute \src "ls180.v:4469.36-4469.105" + wire $eq$ls180.v:4469$655_Y + attribute \src "ls180.v:4488.9-4488.40" + wire $eq$ls180.v:4488$659_Y + attribute \src "ls180.v:4500.10-4500.39" + wire $eq$ls180.v:4500$661_Y + attribute \src "ls180.v:4537.39-4537.94" + wire $eq$ls180.v:4537$665_Y + attribute \src "ls180.v:4574.32-4574.89" + wire $eq$ls180.v:4574$674_Y + attribute \src "ls180.v:4622.10-4622.40" + wire $eq$ls180.v:4622$678_Y + attribute \src "ls180.v:4671.40-4671.98" + wire $eq$ls180.v:4671$680_Y + attribute \src "ls180.v:4722.9-4722.41" + wire $eq$ls180.v:4722$690_Y + attribute \src "ls180.v:4731.37-4731.123" + wire $eq$ls180.v:4731$693_Y + attribute \src "ls180.v:4754.9-4754.41" + wire $eq$ls180.v:4754$696_Y + attribute \src "ls180.v:4764.10-4764.41" + wire $eq$ls180.v:4764$698_Y + attribute \src "ls180.v:4933.9-4933.47" + wire $eq$ls180.v:4933$880_Y + attribute \src "ls180.v:4963.10-4963.48" + wire $eq$ls180.v:4963$881_Y + attribute \src "ls180.v:4994.10-4994.78" + wire $eq$ls180.v:4994$886_Y + attribute \src "ls180.v:4994.83-4994.151" + wire $eq$ls180.v:4994$887_Y + attribute \src "ls180.v:4994.157-4994.225" + wire $eq$ls180.v:4994$889_Y + attribute \src "ls180.v:4994.231-4994.299" + wire $eq$ls180.v:4994$891_Y + attribute \src "ls180.v:5002.7-5002.44" + wire $eq$ls180.v:5002$895_Y + attribute \src "ls180.v:5012.7-5012.44" + wire $eq$ls180.v:5012$898_Y + attribute \src "ls180.v:5022.7-5022.44" + wire $eq$ls180.v:5022$901_Y + attribute \src "ls180.v:5032.7-5032.44" + wire $eq$ls180.v:5032$904_Y + attribute \src "ls180.v:5156.36-5156.64" + wire $eq$ls180.v:5156$955_Y + attribute \src "ls180.v:5162.10-5162.39" + wire $eq$ls180.v:5162$958_Y + attribute \src "ls180.v:5163.11-5163.39" + wire $eq$ls180.v:5163$959_Y + attribute \src "ls180.v:5175.34-5175.63" + wire $eq$ls180.v:5175$960_Y + attribute \src "ls180.v:5176.9-5176.37" + wire $eq$ls180.v:5176$961_Y + attribute \src "ls180.v:5183.10-5183.55" + wire $eq$ls180.v:5183$962_Y + attribute \src "ls180.v:5189.12-5189.41" + wire $eq$ls180.v:5189$963_Y + attribute \src "ls180.v:5192.13-5192.42" + wire $eq$ls180.v:5192$964_Y + attribute \src "ls180.v:5214.10-5214.76" + wire $eq$ls180.v:5214$969_Y + attribute \src "ls180.v:5229.35-5229.101" + wire $eq$ls180.v:5229$972_Y + attribute \src "ls180.v:5231.10-5231.56" + wire $eq$ls180.v:5231$973_Y + attribute \src "ls180.v:5240.12-5240.78" + wire $eq$ls180.v:5240$977_Y + attribute \src "ls180.v:5247.11-5247.57" + wire $eq$ls180.v:5247$978_Y + attribute \src "ls180.v:5364.10-5364.105" + wire $eq$ls180.v:5364$995_Y + attribute \src "ls180.v:5454.39-5454.106" + wire $eq$ls180.v:5454$1001_Y + attribute \src "ls180.v:5484.44-5484.82" + wire $eq$ls180.v:5484$1004_Y + attribute \src "ls180.v:5485.43-5485.81" + wire $eq$ls180.v:5485$1005_Y + attribute \src "ls180.v:5542.32-5542.99" + wire $eq$ls180.v:5542$1018_Y + attribute \src "ls180.v:5543.32-5543.93" + wire $eq$ls180.v:5543$1020_Y + attribute \src "ls180.v:5571.10-5571.59" + wire $eq$ls180.v:5571$1024_Y + attribute \src "ls180.v:5644.85-5644.106" + wire $eq$ls180.v:5644$1029_Y + attribute \src "ls180.v:5645.85-5645.106" + wire $eq$ls180.v:5645$1031_Y + attribute \src "ls180.v:5646.85-5646.106" + wire $eq$ls180.v:5646$1033_Y + attribute \src "ls180.v:5647.57-5647.78" + wire $eq$ls180.v:5647$1035_Y + attribute \src "ls180.v:5648.57-5648.78" + wire $eq$ls180.v:5648$1037_Y + attribute \src "ls180.v:5649.85-5649.106" + wire $eq$ls180.v:5649$1039_Y + attribute \src "ls180.v:5650.85-5650.106" + wire $eq$ls180.v:5650$1041_Y + attribute \src "ls180.v:5651.85-5651.106" + wire $eq$ls180.v:5651$1043_Y + attribute \src "ls180.v:5652.57-5652.78" + wire $eq$ls180.v:5652$1045_Y + attribute \src "ls180.v:5653.57-5653.78" + wire $eq$ls180.v:5653$1047_Y + attribute \src "ls180.v:5657.27-5657.59" + wire $eq$ls180.v:5657$1050_Y + attribute \src "ls180.v:5658.27-5658.68" + wire $eq$ls180.v:5658$1051_Y + attribute \src "ls180.v:5659.27-5659.66" + wire $eq$ls180.v:5659$1052_Y + attribute \src "ls180.v:5660.27-5660.61" + wire $eq$ls180.v:5660$1053_Y + attribute \src "ls180.v:5661.27-5661.65" + wire $eq$ls180.v:5661$1054_Y + attribute \src "ls180.v:5717.24-5717.45" + wire $eq$ls180.v:5717$1081_Y + attribute \src "ls180.v:5718.32-5718.77" + wire $eq$ls180.v:5718$1082_Y + attribute \src "ls180.v:5720.97-5720.141" + wire $eq$ls180.v:5720$1084_Y + attribute \src "ls180.v:5721.100-5721.144" + wire $eq$ls180.v:5721$1088_Y + attribute \src "ls180.v:5723.99-5723.143" + wire $eq$ls180.v:5723$1091_Y + attribute \src "ls180.v:5724.102-5724.146" + wire $eq$ls180.v:5724$1095_Y + attribute \src "ls180.v:5726.99-5726.143" + wire $eq$ls180.v:5726$1098_Y + attribute \src "ls180.v:5727.102-5727.146" + wire $eq$ls180.v:5727$1102_Y + attribute \src "ls180.v:5729.99-5729.143" + wire $eq$ls180.v:5729$1105_Y + attribute \src "ls180.v:5730.102-5730.146" + wire $eq$ls180.v:5730$1109_Y + attribute \src "ls180.v:5732.99-5732.143" + wire $eq$ls180.v:5732$1112_Y + attribute \src "ls180.v:5733.102-5733.146" + wire $eq$ls180.v:5733$1116_Y + attribute \src "ls180.v:5735.102-5735.146" + wire $eq$ls180.v:5735$1119_Y + attribute \src "ls180.v:5736.105-5736.149" + wire $eq$ls180.v:5736$1123_Y + attribute \src "ls180.v:5738.102-5738.146" + wire $eq$ls180.v:5738$1126_Y + attribute \src "ls180.v:5739.105-5739.149" + wire $eq$ls180.v:5739$1130_Y + attribute \src "ls180.v:5741.102-5741.146" + wire $eq$ls180.v:5741$1133_Y + attribute \src "ls180.v:5742.105-5742.149" + wire $eq$ls180.v:5742$1137_Y + attribute \src "ls180.v:5744.102-5744.146" + wire $eq$ls180.v:5744$1140_Y + attribute \src "ls180.v:5745.105-5745.149" + wire $eq$ls180.v:5745$1144_Y + attribute \src "ls180.v:5756.32-5756.77" + wire $eq$ls180.v:5756$1146_Y + attribute \src "ls180.v:5758.94-5758.138" + wire $eq$ls180.v:5758$1148_Y + attribute \src "ls180.v:5759.97-5759.141" + wire $eq$ls180.v:5759$1152_Y + attribute \src "ls180.v:5761.94-5761.138" + wire $eq$ls180.v:5761$1155_Y + attribute \src "ls180.v:5762.97-5762.141" + wire $eq$ls180.v:5762$1159_Y + attribute \src "ls180.v:5764.94-5764.138" + wire $eq$ls180.v:5764$1162_Y + attribute \src "ls180.v:5765.97-5765.141" + wire $eq$ls180.v:5765$1166_Y + attribute \src "ls180.v:5767.94-5767.138" + wire $eq$ls180.v:5767$1169_Y + attribute \src "ls180.v:5768.97-5768.141" + wire $eq$ls180.v:5768$1173_Y + attribute \src "ls180.v:5770.95-5770.139" + wire $eq$ls180.v:5770$1176_Y + attribute \src "ls180.v:5771.98-5771.142" + wire $eq$ls180.v:5771$1180_Y + attribute \src "ls180.v:5773.95-5773.139" + wire $eq$ls180.v:5773$1183_Y + attribute \src "ls180.v:5774.98-5774.142" + wire $eq$ls180.v:5774$1187_Y + attribute \src "ls180.v:5782.32-5782.77" + wire $eq$ls180.v:5782$1189_Y + attribute \src "ls180.v:5784.98-5784.142" + wire $eq$ls180.v:5784$1191_Y + attribute \src "ls180.v:5785.101-5785.145" + wire $eq$ls180.v:5785$1195_Y + attribute \src "ls180.v:5787.97-5787.141" + wire $eq$ls180.v:5787$1198_Y + attribute \src "ls180.v:5788.100-5788.144" + wire $eq$ls180.v:5788$1202_Y + attribute \src "ls180.v:5790.97-5790.141" + wire $eq$ls180.v:5790$1205_Y + attribute \src "ls180.v:5791.100-5791.144" + wire $eq$ls180.v:5791$1209_Y + attribute \src "ls180.v:5793.97-5793.141" + wire $eq$ls180.v:5793$1212_Y + attribute \src "ls180.v:5794.100-5794.144" + wire $eq$ls180.v:5794$1216_Y + attribute \src "ls180.v:5796.97-5796.141" + wire $eq$ls180.v:5796$1219_Y + attribute \src "ls180.v:5797.100-5797.144" + wire $eq$ls180.v:5797$1223_Y + attribute \src "ls180.v:5799.98-5799.142" + wire $eq$ls180.v:5799$1226_Y + attribute \src "ls180.v:5800.101-5800.145" + wire $eq$ls180.v:5800$1230_Y + attribute \src "ls180.v:5802.98-5802.142" + wire $eq$ls180.v:5802$1233_Y + attribute \src "ls180.v:5803.101-5803.145" + wire $eq$ls180.v:5803$1237_Y + attribute \src "ls180.v:5805.98-5805.142" + wire $eq$ls180.v:5805$1240_Y + attribute \src "ls180.v:5806.101-5806.145" + wire $eq$ls180.v:5806$1244_Y + attribute \src "ls180.v:5808.98-5808.142" + wire $eq$ls180.v:5808$1247_Y + attribute \src "ls180.v:5809.101-5809.145" + wire $eq$ls180.v:5809$1251_Y + attribute \src "ls180.v:5819.32-5819.77" + wire $eq$ls180.v:5819$1253_Y + attribute \src "ls180.v:5821.98-5821.142" + wire $eq$ls180.v:5821$1255_Y + attribute \src "ls180.v:5822.101-5822.145" + wire $eq$ls180.v:5822$1259_Y + attribute \src "ls180.v:5824.97-5824.141" + wire $eq$ls180.v:5824$1262_Y + attribute \src "ls180.v:5825.100-5825.144" + wire $eq$ls180.v:5825$1266_Y + attribute \src "ls180.v:5827.97-5827.141" + wire $eq$ls180.v:5827$1269_Y + attribute \src "ls180.v:5828.100-5828.144" + wire $eq$ls180.v:5828$1273_Y + attribute \src "ls180.v:5830.97-5830.141" + wire $eq$ls180.v:5830$1276_Y + attribute \src "ls180.v:5831.100-5831.144" + wire $eq$ls180.v:5831$1280_Y + attribute \src "ls180.v:5833.97-5833.141" + wire $eq$ls180.v:5833$1283_Y + attribute \src "ls180.v:5834.100-5834.144" + wire $eq$ls180.v:5834$1287_Y + attribute \src "ls180.v:5836.98-5836.142" + wire $eq$ls180.v:5836$1290_Y + attribute \src "ls180.v:5837.101-5837.145" + wire $eq$ls180.v:5837$1294_Y + attribute \src "ls180.v:5839.98-5839.142" + wire $eq$ls180.v:5839$1297_Y + attribute \src "ls180.v:5840.101-5840.145" + wire $eq$ls180.v:5840$1301_Y + attribute \src "ls180.v:5842.98-5842.142" + wire $eq$ls180.v:5842$1304_Y + attribute \src "ls180.v:5843.101-5843.145" + wire $eq$ls180.v:5843$1308_Y + attribute \src "ls180.v:5845.98-5845.142" + wire $eq$ls180.v:5845$1311_Y + attribute \src "ls180.v:5846.101-5846.145" + wire $eq$ls180.v:5846$1315_Y + attribute \src "ls180.v:5856.32-5856.78" + wire $eq$ls180.v:5856$1317_Y + attribute \src "ls180.v:5858.100-5858.144" + wire $eq$ls180.v:5858$1319_Y + attribute \src "ls180.v:5859.103-5859.147" + wire $eq$ls180.v:5859$1323_Y + attribute \src "ls180.v:5861.100-5861.144" + wire $eq$ls180.v:5861$1326_Y + attribute \src "ls180.v:5862.103-5862.147" + wire $eq$ls180.v:5862$1330_Y + attribute \src "ls180.v:5864.100-5864.144" + wire $eq$ls180.v:5864$1333_Y + attribute \src "ls180.v:5865.103-5865.147" + wire $eq$ls180.v:5865$1337_Y + attribute \src "ls180.v:5867.100-5867.144" + wire $eq$ls180.v:5867$1340_Y + attribute \src "ls180.v:5868.103-5868.147" + wire $eq$ls180.v:5868$1344_Y + attribute \src "ls180.v:5870.100-5870.144" + wire $eq$ls180.v:5870$1347_Y + attribute \src "ls180.v:5871.103-5871.147" + wire $eq$ls180.v:5871$1351_Y + attribute \src "ls180.v:5873.100-5873.144" + wire $eq$ls180.v:5873$1354_Y + attribute \src "ls180.v:5874.103-5874.147" + wire $eq$ls180.v:5874$1358_Y + attribute \src "ls180.v:5876.100-5876.144" + wire $eq$ls180.v:5876$1361_Y + attribute \src "ls180.v:5877.103-5877.147" + wire $eq$ls180.v:5877$1365_Y + attribute \src "ls180.v:5879.100-5879.144" + wire $eq$ls180.v:5879$1368_Y + attribute \src "ls180.v:5880.103-5880.147" + wire $eq$ls180.v:5880$1372_Y + attribute \src "ls180.v:5882.102-5882.146" + wire $eq$ls180.v:5882$1375_Y + attribute \src "ls180.v:5883.105-5883.149" + wire $eq$ls180.v:5883$1379_Y + attribute \src "ls180.v:5885.102-5885.146" + wire $eq$ls180.v:5885$1382_Y + attribute \src "ls180.v:5886.105-5886.149" + wire $eq$ls180.v:5886$1386_Y + attribute \src "ls180.v:5888.102-5888.147" + wire $eq$ls180.v:5888$1389_Y + attribute \src "ls180.v:5889.105-5889.150" + wire $eq$ls180.v:5889$1393_Y + attribute \src "ls180.v:5891.102-5891.147" + wire $eq$ls180.v:5891$1396_Y + attribute \src "ls180.v:5892.105-5892.150" + wire $eq$ls180.v:5892$1400_Y + attribute \src "ls180.v:5894.102-5894.147" + wire $eq$ls180.v:5894$1403_Y + attribute \src "ls180.v:5895.105-5895.150" + wire $eq$ls180.v:5895$1407_Y + attribute \src "ls180.v:5897.99-5897.144" + wire $eq$ls180.v:5897$1410_Y + attribute \src "ls180.v:5898.102-5898.147" + wire $eq$ls180.v:5898$1414_Y + attribute \src "ls180.v:5900.100-5900.145" + wire $eq$ls180.v:5900$1417_Y + attribute \src "ls180.v:5901.103-5901.148" + wire $eq$ls180.v:5901$1421_Y + attribute \src "ls180.v:5918.32-5918.78" + wire $eq$ls180.v:5918$1423_Y + attribute \src "ls180.v:5920.104-5920.148" + wire $eq$ls180.v:5920$1425_Y + attribute \src "ls180.v:5921.107-5921.151" + wire $eq$ls180.v:5921$1429_Y + attribute \src "ls180.v:5923.104-5923.148" + wire $eq$ls180.v:5923$1432_Y + attribute \src "ls180.v:5924.107-5924.151" + wire $eq$ls180.v:5924$1436_Y + attribute \src "ls180.v:5926.104-5926.148" + wire $eq$ls180.v:5926$1439_Y + attribute \src "ls180.v:5927.107-5927.151" + wire $eq$ls180.v:5927$1443_Y + attribute \src "ls180.v:5929.104-5929.148" + wire $eq$ls180.v:5929$1446_Y + attribute \src "ls180.v:5930.107-5930.151" + wire $eq$ls180.v:5930$1450_Y + attribute \src "ls180.v:5932.103-5932.147" + wire $eq$ls180.v:5932$1453_Y + attribute \src "ls180.v:5933.106-5933.150" + wire $eq$ls180.v:5933$1457_Y + attribute \src "ls180.v:5935.103-5935.147" + wire $eq$ls180.v:5935$1460_Y + attribute \src "ls180.v:5936.106-5936.150" + wire $eq$ls180.v:5936$1464_Y + attribute \src "ls180.v:5938.103-5938.147" + wire $eq$ls180.v:5938$1467_Y + attribute \src "ls180.v:5939.106-5939.150" + wire $eq$ls180.v:5939$1471_Y + attribute \src "ls180.v:5941.103-5941.147" + wire $eq$ls180.v:5941$1474_Y + attribute \src "ls180.v:5942.106-5942.150" + wire $eq$ls180.v:5942$1478_Y + attribute \src "ls180.v:5944.94-5944.138" + wire $eq$ls180.v:5944$1481_Y + attribute \src "ls180.v:5945.97-5945.141" + wire $eq$ls180.v:5945$1485_Y + attribute \src "ls180.v:5947.105-5947.149" + wire $eq$ls180.v:5947$1488_Y + attribute \src "ls180.v:5948.108-5948.152" + wire $eq$ls180.v:5948$1492_Y + attribute \src "ls180.v:5950.105-5950.150" + wire $eq$ls180.v:5950$1495_Y + attribute \src "ls180.v:5951.108-5951.153" + wire $eq$ls180.v:5951$1499_Y + attribute \src "ls180.v:5953.105-5953.150" + wire $eq$ls180.v:5953$1502_Y + attribute \src "ls180.v:5954.108-5954.153" + wire $eq$ls180.v:5954$1506_Y + attribute \src "ls180.v:5956.105-5956.150" + wire $eq$ls180.v:5956$1509_Y + attribute \src "ls180.v:5957.108-5957.153" + wire $eq$ls180.v:5957$1513_Y + attribute \src "ls180.v:5959.105-5959.150" + wire $eq$ls180.v:5959$1516_Y + attribute \src "ls180.v:5960.108-5960.153" + wire $eq$ls180.v:5960$1520_Y + attribute \src "ls180.v:5962.105-5962.150" + wire $eq$ls180.v:5962$1523_Y + attribute \src "ls180.v:5963.108-5963.153" + wire $eq$ls180.v:5963$1527_Y + attribute \src "ls180.v:5965.104-5965.149" + wire $eq$ls180.v:5965$1530_Y + attribute \src "ls180.v:5966.107-5966.152" + wire $eq$ls180.v:5966$1534_Y + attribute \src "ls180.v:5968.104-5968.149" + wire $eq$ls180.v:5968$1537_Y + attribute \src "ls180.v:5969.107-5969.152" + wire $eq$ls180.v:5969$1541_Y + attribute \src "ls180.v:5971.104-5971.149" + wire $eq$ls180.v:5971$1544_Y + attribute \src "ls180.v:5972.107-5972.152" + wire $eq$ls180.v:5972$1548_Y + attribute \src "ls180.v:5974.104-5974.149" + wire $eq$ls180.v:5974$1551_Y + attribute \src "ls180.v:5975.107-5975.152" + wire $eq$ls180.v:5975$1555_Y + attribute \src "ls180.v:5977.104-5977.149" + wire $eq$ls180.v:5977$1558_Y + attribute \src "ls180.v:5978.107-5978.152" + wire $eq$ls180.v:5978$1562_Y + attribute \src "ls180.v:5980.104-5980.149" + wire $eq$ls180.v:5980$1565_Y + attribute \src "ls180.v:5981.107-5981.152" + wire $eq$ls180.v:5981$1569_Y + attribute \src "ls180.v:5983.104-5983.149" + wire $eq$ls180.v:5983$1572_Y + attribute \src "ls180.v:5984.107-5984.152" + wire $eq$ls180.v:5984$1576_Y + attribute \src "ls180.v:5986.104-5986.149" + wire $eq$ls180.v:5986$1579_Y + attribute \src "ls180.v:5987.107-5987.152" + wire $eq$ls180.v:5987$1583_Y + attribute \src "ls180.v:5989.104-5989.149" + wire $eq$ls180.v:5989$1586_Y + attribute \src "ls180.v:5990.107-5990.152" + wire $eq$ls180.v:5990$1590_Y + attribute \src "ls180.v:5992.104-5992.149" + wire $eq$ls180.v:5992$1593_Y + attribute \src "ls180.v:5993.107-5993.152" + wire $eq$ls180.v:5993$1597_Y + attribute \src "ls180.v:5995.100-5995.145" + wire $eq$ls180.v:5995$1600_Y + attribute \src "ls180.v:5996.103-5996.148" + wire $eq$ls180.v:5996$1604_Y + attribute \src "ls180.v:5998.101-5998.146" + wire $eq$ls180.v:5998$1607_Y + attribute \src "ls180.v:5999.104-5999.149" + wire $eq$ls180.v:5999$1611_Y + attribute \src "ls180.v:6001.104-6001.149" + wire $eq$ls180.v:6001$1614_Y + attribute \src "ls180.v:6002.107-6002.152" + wire $eq$ls180.v:6002$1618_Y + attribute \src "ls180.v:6004.104-6004.149" + wire $eq$ls180.v:6004$1621_Y + attribute \src "ls180.v:6005.107-6005.152" + wire $eq$ls180.v:6005$1625_Y + attribute \src "ls180.v:6007.103-6007.148" + wire $eq$ls180.v:6007$1628_Y + attribute \src "ls180.v:6008.106-6008.151" + wire $eq$ls180.v:6008$1632_Y + attribute \src "ls180.v:6010.103-6010.148" + wire $eq$ls180.v:6010$1635_Y + attribute \src "ls180.v:6011.106-6011.151" + wire $eq$ls180.v:6011$1639_Y + attribute \src "ls180.v:6013.103-6013.148" + wire $eq$ls180.v:6013$1642_Y + attribute \src "ls180.v:6014.106-6014.151" + wire $eq$ls180.v:6014$1646_Y + attribute \src "ls180.v:6016.103-6016.148" + wire $eq$ls180.v:6016$1649_Y + attribute \src "ls180.v:6017.106-6017.151" + wire $eq$ls180.v:6017$1653_Y + attribute \src "ls180.v:6053.32-6053.78" + wire $eq$ls180.v:6053$1655_Y + attribute \src "ls180.v:6055.100-6055.144" + wire $eq$ls180.v:6055$1657_Y + attribute \src "ls180.v:6056.103-6056.147" + wire $eq$ls180.v:6056$1661_Y + attribute \src "ls180.v:6058.100-6058.144" + wire $eq$ls180.v:6058$1664_Y + attribute \src "ls180.v:6059.103-6059.147" + wire $eq$ls180.v:6059$1668_Y + attribute \src "ls180.v:6061.100-6061.144" + wire $eq$ls180.v:6061$1671_Y + attribute \src "ls180.v:6062.103-6062.147" + wire $eq$ls180.v:6062$1675_Y + attribute \src "ls180.v:6064.100-6064.144" + wire $eq$ls180.v:6064$1678_Y + attribute \src "ls180.v:6065.103-6065.147" + wire $eq$ls180.v:6065$1682_Y + attribute \src "ls180.v:6067.100-6067.144" + wire $eq$ls180.v:6067$1685_Y + attribute \src "ls180.v:6068.103-6068.147" + wire $eq$ls180.v:6068$1689_Y + attribute \src "ls180.v:6070.100-6070.144" + wire $eq$ls180.v:6070$1692_Y + attribute \src "ls180.v:6071.103-6071.147" + wire $eq$ls180.v:6071$1696_Y + attribute \src "ls180.v:6073.100-6073.144" + wire $eq$ls180.v:6073$1699_Y + attribute \src "ls180.v:6074.103-6074.147" + wire $eq$ls180.v:6074$1703_Y + attribute \src "ls180.v:6076.100-6076.144" + wire $eq$ls180.v:6076$1706_Y + attribute \src "ls180.v:6077.103-6077.147" + wire $eq$ls180.v:6077$1710_Y + attribute \src "ls180.v:6079.102-6079.146" + wire $eq$ls180.v:6079$1713_Y + attribute \src "ls180.v:6080.105-6080.149" + wire $eq$ls180.v:6080$1717_Y + attribute \src "ls180.v:6082.102-6082.146" + wire $eq$ls180.v:6082$1720_Y + attribute \src "ls180.v:6083.105-6083.149" + wire $eq$ls180.v:6083$1724_Y + attribute \src "ls180.v:6085.102-6085.147" + wire $eq$ls180.v:6085$1727_Y + attribute \src "ls180.v:6086.105-6086.150" + wire $eq$ls180.v:6086$1731_Y + attribute \src "ls180.v:6088.102-6088.147" + wire $eq$ls180.v:6088$1734_Y + attribute \src "ls180.v:6089.105-6089.150" + wire $eq$ls180.v:6089$1738_Y + attribute \src "ls180.v:6091.102-6091.147" + wire $eq$ls180.v:6091$1741_Y + attribute \src "ls180.v:6092.105-6092.150" + wire $eq$ls180.v:6092$1745_Y + attribute \src "ls180.v:6094.99-6094.144" + wire $eq$ls180.v:6094$1748_Y + attribute \src "ls180.v:6095.102-6095.147" + wire $eq$ls180.v:6095$1752_Y + attribute \src "ls180.v:6097.100-6097.145" + wire $eq$ls180.v:6097$1755_Y + attribute \src "ls180.v:6098.103-6098.148" + wire $eq$ls180.v:6098$1759_Y + attribute \src "ls180.v:6100.102-6100.147" + wire $eq$ls180.v:6100$1762_Y + attribute \src "ls180.v:6101.105-6101.150" + wire $eq$ls180.v:6101$1766_Y + attribute \src "ls180.v:6103.102-6103.147" + wire $eq$ls180.v:6103$1769_Y + attribute \src "ls180.v:6104.105-6104.150" + wire $eq$ls180.v:6104$1773_Y + attribute \src "ls180.v:6106.102-6106.147" + wire $eq$ls180.v:6106$1776_Y + attribute \src "ls180.v:6107.105-6107.150" + wire $eq$ls180.v:6107$1780_Y + attribute \src "ls180.v:6109.102-6109.147" + wire $eq$ls180.v:6109$1783_Y + attribute \src "ls180.v:6110.105-6110.150" + wire $eq$ls180.v:6110$1787_Y + attribute \src "ls180.v:6132.32-6132.78" + wire $eq$ls180.v:6132$1789_Y + attribute \src "ls180.v:6134.102-6134.146" + wire $eq$ls180.v:6134$1791_Y + attribute \src "ls180.v:6135.105-6135.149" + wire $eq$ls180.v:6135$1795_Y + attribute \src "ls180.v:6137.107-6137.151" + wire $eq$ls180.v:6137$1798_Y + attribute \src "ls180.v:6138.110-6138.154" + wire $eq$ls180.v:6138$1802_Y + attribute \src "ls180.v:6140.107-6140.151" + wire $eq$ls180.v:6140$1805_Y + attribute \src "ls180.v:6141.110-6141.154" + wire $eq$ls180.v:6141$1809_Y + attribute \src "ls180.v:6143.100-6143.144" + wire $eq$ls180.v:6143$1812_Y + attribute \src "ls180.v:6144.103-6144.147" + wire $eq$ls180.v:6144$1816_Y + attribute \src "ls180.v:6149.32-6149.77" + wire $eq$ls180.v:6149$1818_Y + attribute \src "ls180.v:6151.104-6151.148" + wire $eq$ls180.v:6151$1820_Y + attribute \src "ls180.v:6152.107-6152.151" + wire $eq$ls180.v:6152$1824_Y + attribute \src "ls180.v:6154.108-6154.152" + wire $eq$ls180.v:6154$1827_Y + attribute \src "ls180.v:6155.111-6155.155" + wire $eq$ls180.v:6155$1831_Y + attribute \src "ls180.v:6157.98-6157.142" + wire $eq$ls180.v:6157$1834_Y + attribute \src "ls180.v:6158.101-6158.145" + wire $eq$ls180.v:6158$1838_Y + attribute \src "ls180.v:6160.108-6160.152" + wire $eq$ls180.v:6160$1841_Y + attribute \src "ls180.v:6161.111-6161.155" + wire $eq$ls180.v:6161$1845_Y + attribute \src "ls180.v:6163.108-6163.152" + wire $eq$ls180.v:6163$1848_Y + attribute \src "ls180.v:6164.111-6164.155" + wire $eq$ls180.v:6164$1852_Y + attribute \src "ls180.v:6166.109-6166.153" + wire $eq$ls180.v:6166$1855_Y + attribute \src "ls180.v:6167.112-6167.156" + wire $eq$ls180.v:6167$1859_Y + attribute \src "ls180.v:6169.107-6169.151" + wire $eq$ls180.v:6169$1862_Y + attribute \src "ls180.v:6170.110-6170.154" + wire $eq$ls180.v:6170$1866_Y + attribute \src "ls180.v:6172.107-6172.151" + wire $eq$ls180.v:6172$1869_Y + attribute \src "ls180.v:6173.110-6173.154" + wire $eq$ls180.v:6173$1873_Y + attribute \src "ls180.v:6175.107-6175.151" + wire $eq$ls180.v:6175$1876_Y + attribute \src "ls180.v:6176.110-6176.154" + wire $eq$ls180.v:6176$1880_Y + attribute \src "ls180.v:6178.107-6178.151" + wire $eq$ls180.v:6178$1883_Y + attribute \src "ls180.v:6179.110-6179.154" + wire $eq$ls180.v:6179$1887_Y + attribute \src "ls180.v:6194.32-6194.77" + wire $eq$ls180.v:6194$1889_Y + attribute \src "ls180.v:6196.99-6196.143" + wire $eq$ls180.v:6196$1891_Y + attribute \src "ls180.v:6197.102-6197.146" + wire $eq$ls180.v:6197$1895_Y + attribute \src "ls180.v:6199.99-6199.143" + wire $eq$ls180.v:6199$1898_Y + attribute \src "ls180.v:6200.102-6200.146" + wire $eq$ls180.v:6200$1902_Y + attribute \src "ls180.v:6202.97-6202.141" + wire $eq$ls180.v:6202$1905_Y + attribute \src "ls180.v:6203.100-6203.144" + wire $eq$ls180.v:6203$1909_Y + attribute \src "ls180.v:6205.96-6205.140" + wire $eq$ls180.v:6205$1912_Y + attribute \src "ls180.v:6206.99-6206.143" + wire $eq$ls180.v:6206$1916_Y + attribute \src "ls180.v:6208.95-6208.139" + wire $eq$ls180.v:6208$1919_Y + attribute \src "ls180.v:6209.98-6209.142" + wire $eq$ls180.v:6209$1923_Y + attribute \src "ls180.v:6211.94-6211.138" + wire $eq$ls180.v:6211$1926_Y + attribute \src "ls180.v:6212.97-6212.141" + wire $eq$ls180.v:6212$1930_Y + attribute \src "ls180.v:6214.100-6214.144" + wire $eq$ls180.v:6214$1933_Y + attribute \src "ls180.v:6215.103-6215.147" + wire $eq$ls180.v:6215$1937_Y + attribute \src "ls180.v:6234.33-6234.80" + wire $eq$ls180.v:6234$1940_Y + attribute \src "ls180.v:6236.102-6236.147" + wire $eq$ls180.v:6236$1942_Y + attribute \src "ls180.v:6237.105-6237.150" + wire $eq$ls180.v:6237$1946_Y + attribute \src "ls180.v:6239.102-6239.147" + wire $eq$ls180.v:6239$1949_Y + attribute \src "ls180.v:6240.105-6240.150" + wire $eq$ls180.v:6240$1953_Y + attribute \src "ls180.v:6242.100-6242.145" + wire $eq$ls180.v:6242$1956_Y + attribute \src "ls180.v:6243.103-6243.148" + wire $eq$ls180.v:6243$1960_Y + attribute \src "ls180.v:6245.99-6245.144" + wire $eq$ls180.v:6245$1963_Y + attribute \src "ls180.v:6246.102-6246.147" + wire $eq$ls180.v:6246$1967_Y + attribute \src "ls180.v:6248.98-6248.143" + wire $eq$ls180.v:6248$1970_Y + attribute \src "ls180.v:6249.101-6249.146" + wire $eq$ls180.v:6249$1974_Y + attribute \src "ls180.v:6251.97-6251.142" + wire $eq$ls180.v:6251$1977_Y + attribute \src "ls180.v:6252.100-6252.145" + wire $eq$ls180.v:6252$1981_Y + attribute \src "ls180.v:6254.103-6254.148" + wire $eq$ls180.v:6254$1984_Y + attribute \src "ls180.v:6255.106-6255.151" + wire $eq$ls180.v:6255$1988_Y + attribute \src "ls180.v:6257.106-6257.151" + wire $eq$ls180.v:6257$1991_Y + attribute \src "ls180.v:6258.109-6258.154" + wire $eq$ls180.v:6258$1995_Y + attribute \src "ls180.v:6260.106-6260.151" + wire $eq$ls180.v:6260$1998_Y + attribute \src "ls180.v:6261.109-6261.154" + wire $eq$ls180.v:6261$2002_Y + attribute \src "ls180.v:6282.33-6282.79" + wire $eq$ls180.v:6282$2005_Y + attribute \src "ls180.v:6284.99-6284.144" + wire $eq$ls180.v:6284$2007_Y + attribute \src "ls180.v:6285.102-6285.147" + wire $eq$ls180.v:6285$2011_Y + attribute \src "ls180.v:6287.99-6287.144" + wire $eq$ls180.v:6287$2014_Y + attribute \src "ls180.v:6288.102-6288.147" + wire $eq$ls180.v:6288$2018_Y + attribute \src "ls180.v:6290.99-6290.144" + wire $eq$ls180.v:6290$2021_Y + attribute \src "ls180.v:6291.102-6291.147" + wire $eq$ls180.v:6291$2025_Y + attribute \src "ls180.v:6293.99-6293.144" + wire $eq$ls180.v:6293$2028_Y + attribute \src "ls180.v:6294.102-6294.147" + wire $eq$ls180.v:6294$2032_Y + attribute \src "ls180.v:6296.101-6296.146" + wire $eq$ls180.v:6296$2035_Y + attribute \src "ls180.v:6297.104-6297.149" + wire $eq$ls180.v:6297$2039_Y + attribute \src "ls180.v:6299.101-6299.146" + wire $eq$ls180.v:6299$2042_Y + attribute \src "ls180.v:6300.104-6300.149" + wire $eq$ls180.v:6300$2046_Y + attribute \src "ls180.v:6302.101-6302.146" + wire $eq$ls180.v:6302$2049_Y + attribute \src "ls180.v:6303.104-6303.149" + wire $eq$ls180.v:6303$2053_Y + attribute \src "ls180.v:6305.101-6305.146" + wire $eq$ls180.v:6305$2056_Y + attribute \src "ls180.v:6306.104-6306.149" + wire $eq$ls180.v:6306$2060_Y + attribute \src "ls180.v:6308.97-6308.142" + wire $eq$ls180.v:6308$2063_Y + attribute \src "ls180.v:6309.100-6309.145" + wire $eq$ls180.v:6309$2067_Y + attribute \src "ls180.v:6311.107-6311.152" + wire $eq$ls180.v:6311$2070_Y + attribute \src "ls180.v:6312.110-6312.155" + wire $eq$ls180.v:6312$2074_Y + attribute \src "ls180.v:6314.100-6314.146" + wire $eq$ls180.v:6314$2077_Y + attribute \src "ls180.v:6315.103-6315.149" + wire $eq$ls180.v:6315$2081_Y + attribute \src "ls180.v:6317.100-6317.146" + wire $eq$ls180.v:6317$2084_Y + attribute \src "ls180.v:6318.103-6318.149" + wire $eq$ls180.v:6318$2088_Y + attribute \src "ls180.v:6320.100-6320.146" + wire $eq$ls180.v:6320$2091_Y + attribute \src "ls180.v:6321.103-6321.149" + wire $eq$ls180.v:6321$2095_Y + attribute \src "ls180.v:6323.100-6323.146" + wire $eq$ls180.v:6323$2098_Y + attribute \src "ls180.v:6324.103-6324.149" + wire $eq$ls180.v:6324$2102_Y + attribute \src "ls180.v:6326.112-6326.158" + wire $eq$ls180.v:6326$2105_Y + attribute \src "ls180.v:6327.115-6327.161" + wire $eq$ls180.v:6327$2109_Y + attribute \src "ls180.v:6329.113-6329.159" + wire $eq$ls180.v:6329$2112_Y + attribute \src "ls180.v:6330.116-6330.162" + wire $eq$ls180.v:6330$2116_Y + attribute \src "ls180.v:6332.104-6332.150" + wire $eq$ls180.v:6332$2119_Y + attribute \src "ls180.v:6333.107-6333.153" + wire $eq$ls180.v:6333$2123_Y + attribute \src "ls180.v:6350.33-6350.79" + wire $eq$ls180.v:6350$2125_Y + attribute \src "ls180.v:6352.90-6352.135" + wire $eq$ls180.v:6352$2127_Y + attribute \src "ls180.v:6353.93-6353.138" + wire $eq$ls180.v:6353$2131_Y + attribute \src "ls180.v:6355.100-6355.145" + wire $eq$ls180.v:6355$2134_Y + attribute \src "ls180.v:6356.103-6356.148" + wire $eq$ls180.v:6356$2138_Y + attribute \src "ls180.v:6358.101-6358.146" + wire $eq$ls180.v:6358$2141_Y + attribute \src "ls180.v:6359.104-6359.149" + wire $eq$ls180.v:6359$2145_Y + attribute \src "ls180.v:6361.105-6361.150" + wire $eq$ls180.v:6361$2148_Y + attribute \src "ls180.v:6362.108-6362.153" + wire $eq$ls180.v:6362$2152_Y + attribute \src "ls180.v:6364.106-6364.151" + wire $eq$ls180.v:6364$2155_Y + attribute \src "ls180.v:6365.109-6365.154" + wire $eq$ls180.v:6365$2159_Y + attribute \src "ls180.v:6367.104-6367.149" + wire $eq$ls180.v:6367$2162_Y + attribute \src "ls180.v:6368.107-6368.152" + wire $eq$ls180.v:6368$2166_Y + attribute \src "ls180.v:6370.101-6370.146" + wire $eq$ls180.v:6370$2169_Y + attribute \src "ls180.v:6371.104-6371.149" + wire $eq$ls180.v:6371$2173_Y + attribute \src "ls180.v:6373.100-6373.145" + wire $eq$ls180.v:6373$2176_Y + attribute \src "ls180.v:6374.103-6374.148" + wire $eq$ls180.v:6374$2180_Y + attribute \src "ls180.v:6384.33-6384.79" + wire $eq$ls180.v:6384$2182_Y + attribute \src "ls180.v:6386.106-6386.151" + wire $eq$ls180.v:6386$2184_Y + attribute \src "ls180.v:6387.109-6387.154" + wire $eq$ls180.v:6387$2188_Y + attribute \src "ls180.v:6389.106-6389.151" + wire $eq$ls180.v:6389$2191_Y + attribute \src "ls180.v:6390.109-6390.154" + wire $eq$ls180.v:6390$2195_Y + attribute \src "ls180.v:6392.106-6392.151" + wire $eq$ls180.v:6392$2198_Y + attribute \src "ls180.v:6393.109-6393.154" + wire $eq$ls180.v:6393$2202_Y + attribute \src "ls180.v:6395.106-6395.151" + wire $eq$ls180.v:6395$2205_Y + attribute \src "ls180.v:6396.109-6396.154" + wire $eq$ls180.v:6396$2209_Y + attribute \src "ls180.v:6774.41-6774.81" + wire $eq$ls180.v:6774$2245_Y + attribute \src "ls180.v:6774.144-6774.177" + wire $eq$ls180.v:6774$2246_Y + attribute \src "ls180.v:6774.219-6774.252" + wire $eq$ls180.v:6774$2249_Y + attribute \src "ls180.v:6774.294-6774.327" + wire $eq$ls180.v:6774$2252_Y + attribute \src "ls180.v:6798.41-6798.81" + wire $eq$ls180.v:6798$2261_Y + attribute \src "ls180.v:6798.144-6798.177" + wire $eq$ls180.v:6798$2262_Y + attribute \src "ls180.v:6798.219-6798.252" + wire $eq$ls180.v:6798$2265_Y + attribute \src "ls180.v:6798.294-6798.327" + wire $eq$ls180.v:6798$2268_Y + attribute \src "ls180.v:6822.41-6822.81" + wire $eq$ls180.v:6822$2277_Y + attribute \src "ls180.v:6822.144-6822.177" + wire $eq$ls180.v:6822$2278_Y + attribute \src "ls180.v:6822.219-6822.252" + wire $eq$ls180.v:6822$2281_Y + attribute \src "ls180.v:6822.294-6822.327" + wire $eq$ls180.v:6822$2284_Y + attribute \src "ls180.v:6846.41-6846.81" + wire $eq$ls180.v:6846$2293_Y + attribute \src "ls180.v:6846.144-6846.177" + wire $eq$ls180.v:6846$2294_Y + attribute \src "ls180.v:6846.219-6846.252" + wire $eq$ls180.v:6846$2297_Y + attribute \src "ls180.v:6846.294-6846.327" + wire $eq$ls180.v:6846$2300_Y + attribute \src "ls180.v:7445.8-7445.38" + wire $eq$ls180.v:7445$2409_Y + attribute \src "ls180.v:7476.8-7476.42" + wire $eq$ls180.v:7476$2417_Y + attribute \src "ls180.v:7496.38-7496.74" + wire $eq$ls180.v:7496$2420_Y + attribute \src "ls180.v:7503.7-7503.43" + wire $eq$ls180.v:7503$2422_Y + attribute \src "ls180.v:7510.7-7510.43" + wire $eq$ls180.v:7510$2423_Y + attribute \src "ls180.v:7518.7-7518.43" + wire $eq$ls180.v:7518$2424_Y + attribute \src "ls180.v:7570.9-7570.54" + wire $eq$ls180.v:7570$2442_Y + attribute \src "ls180.v:7616.9-7616.54" + wire $eq$ls180.v:7616$2458_Y + attribute \src "ls180.v:7662.9-7662.54" + wire $eq$ls180.v:7662$2474_Y + attribute \src "ls180.v:7708.9-7708.54" + wire $eq$ls180.v:7708$2490_Y + attribute \src "ls180.v:7858.9-7858.41" + wire $eq$ls180.v:7858$2502_Y + attribute \src "ls180.v:7873.9-7873.41" + wire $eq$ls180.v:7873$2505_Y + attribute \src "ls180.v:7879.49-7879.82" + wire $eq$ls180.v:7879$2506_Y + attribute \src "ls180.v:7879.131-7879.164" + wire $eq$ls180.v:7879$2509_Y + attribute \src "ls180.v:7879.213-7879.246" + wire $eq$ls180.v:7879$2512_Y + attribute \src "ls180.v:7879.295-7879.328" + wire $eq$ls180.v:7879$2515_Y + attribute \src "ls180.v:7880.50-7880.83" + wire $eq$ls180.v:7880$2518_Y + attribute \src "ls180.v:7880.132-7880.165" + wire $eq$ls180.v:7880$2521_Y + attribute \src "ls180.v:7880.214-7880.247" + wire $eq$ls180.v:7880$2524_Y + attribute \src "ls180.v:7880.296-7880.329" + wire $eq$ls180.v:7880$2527_Y + attribute \src "ls180.v:7915.9-7915.33" + wire $eq$ls180.v:7915$2539_Y + attribute \src "ls180.v:7918.10-7918.34" + wire $eq$ls180.v:7918$2540_Y + attribute \src "ls180.v:7944.9-7944.33" + wire $eq$ls180.v:7944$2546_Y + attribute \src "ls180.v:7949.10-7949.34" + wire $eq$ls180.v:7949$2547_Y + attribute \src "ls180.v:8121.9-8121.53" + wire $eq$ls180.v:8121$2591_Y + attribute \src "ls180.v:8202.9-8202.54" + wire $eq$ls180.v:8202$2603_Y + attribute \src "ls180.v:8281.9-8281.55" + wire $eq$ls180.v:8281$2615_Y + attribute \src "ls180.v:8504.9-8504.49" + wire $eq$ls180.v:8504$2648_Y + attribute \src "ls180.v:8080.8-8080.54" + wire $ge$ls180.v:8080$2583_Y + attribute \src "ls180.v:8094.8-8094.54" + wire $ge$ls180.v:8094$2587_Y + attribute \src "ls180.v:5041.47-5041.83" + wire $gt$ls180.v:5041$906_Y + attribute \src "ls180.v:5047.7-5047.43" + wire $lt$ls180.v:5047$909_Y + attribute \src "ls180.v:8075.8-8075.43" + wire $lt$ls180.v:8075$2581_Y + attribute \src "ls180.v:8089.8-8089.43" + wire $lt$ls180.v:8089$2585_Y + attribute \src "ls180.v:9989.33-9989.36" + wire width 32 $memrd$\mem$ls180.v:9989$2695_DATA + attribute \src "ls180.v:10000.12-10000.19" + wire width 25 $memrd$\storage$ls180.v:10000$2700_DATA + attribute \src "ls180.v:10007.68-10007.75" + wire width 25 $memrd$\storage$ls180.v:10007$2702_DATA + attribute \src "ls180.v:10014.14-10014.23" + wire width 25 $memrd$\storage_1$ls180.v:10014$2707_DATA + attribute \src "ls180.v:10021.68-10021.77" + wire width 25 $memrd$\storage_1$ls180.v:10021$2709_DATA + attribute \src "ls180.v:10028.14-10028.23" + wire width 25 $memrd$\storage_2$ls180.v:10028$2714_DATA + attribute \src "ls180.v:10035.68-10035.77" + wire width 25 $memrd$\storage_2$ls180.v:10035$2716_DATA + attribute \src "ls180.v:10042.14-10042.23" + wire width 25 $memrd$\storage_3$ls180.v:10042$2721_DATA + attribute \src "ls180.v:10049.68-10049.77" + wire width 25 $memrd$\storage_3$ls180.v:10049$2723_DATA + attribute \src "ls180.v:10057.14-10057.23" + wire width 10 $memrd$\storage_4$ls180.v:10057$2728_DATA + attribute \src "ls180.v:10062.15-10062.24" + wire width 10 $memrd$\storage_4$ls180.v:10062$2730_DATA + attribute \src "ls180.v:10074.14-10074.23" + wire width 10 $memrd$\storage_5$ls180.v:10074$2735_DATA + attribute \src "ls180.v:10079.15-10079.24" + wire width 10 $memrd$\storage_5$ls180.v:10079$2737_DATA + attribute \src "ls180.v:10090.14-10090.23" + wire width 10 $memrd$\storage_6$ls180.v:10090$2742_DATA + attribute \src "ls180.v:10097.45-10097.54" + wire width 10 $memrd$\storage_6$ls180.v:10097$2744_DATA + attribute \src "ls180.v:10104.14-10104.23" + wire width 10 $memrd$\storage_7$ls180.v:10104$2749_DATA + attribute \src "ls180.v:10111.45-10111.54" + wire width 10 $memrd$\storage_7$ls180.v:10111$2751_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 7 $memwr$\mem$ls180.v:9979$1_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 32 $memwr$\mem$ls180.v:9979$1_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 32 $memwr$\mem$ls180.v:9979$1_EN + attribute \src "ls180.v:0.0-0.0" + wire width 7 $memwr$\mem$ls180.v:9981$2_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 32 $memwr$\mem$ls180.v:9981$2_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 32 $memwr$\mem$ls180.v:9981$2_EN + attribute \src "ls180.v:0.0-0.0" + wire width 7 $memwr$\mem$ls180.v:9983$3_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 32 $memwr$\mem$ls180.v:9983$3_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 32 $memwr$\mem$ls180.v:9983$3_EN + attribute \src "ls180.v:0.0-0.0" + wire width 7 $memwr$\mem$ls180.v:9985$4_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 32 $memwr$\mem$ls180.v:9985$4_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 32 $memwr$\mem$ls180.v:9985$4_EN + attribute \src "ls180.v:0.0-0.0" + wire width 3 $memwr$\storage$ls180.v:9999$5_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 25 $memwr$\storage$ls180.v:9999$5_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 25 $memwr$\storage$ls180.v:9999$5_EN + attribute \src "ls180.v:0.0-0.0" + wire width 3 $memwr$\storage_1$ls180.v:10013$6_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 25 $memwr$\storage_1$ls180.v:10013$6_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 25 $memwr$\storage_1$ls180.v:10013$6_EN + attribute \src "ls180.v:0.0-0.0" + wire width 3 $memwr$\storage_2$ls180.v:10027$7_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 25 $memwr$\storage_2$ls180.v:10027$7_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 25 $memwr$\storage_2$ls180.v:10027$7_EN + attribute \src "ls180.v:0.0-0.0" + wire width 3 $memwr$\storage_3$ls180.v:10041$8_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 25 $memwr$\storage_3$ls180.v:10041$8_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 25 $memwr$\storage_3$ls180.v:10041$8_EN + attribute \src "ls180.v:0.0-0.0" + wire width 4 $memwr$\storage_4$ls180.v:10056$9_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 10 $memwr$\storage_4$ls180.v:10056$9_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 10 $memwr$\storage_4$ls180.v:10056$9_EN + attribute \src "ls180.v:0.0-0.0" + wire width 4 $memwr$\storage_5$ls180.v:10073$10_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 10 $memwr$\storage_5$ls180.v:10073$10_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 10 $memwr$\storage_5$ls180.v:10073$10_EN + attribute \src "ls180.v:0.0-0.0" + wire width 5 $memwr$\storage_6$ls180.v:10089$11_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 10 $memwr$\storage_6$ls180.v:10089$11_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 10 $memwr$\storage_6$ls180.v:10089$11_EN + attribute \src "ls180.v:0.0-0.0" + wire width 5 $memwr$\storage_7$ls180.v:10103$12_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 10 $memwr$\storage_7$ls180.v:10103$12_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 10 $memwr$\storage_7$ls180.v:10103$12_EN + attribute \src "ls180.v:2918.41-2918.71" + wire $ne$ls180.v:2918$60_Y + attribute \src "ls180.v:3079.70-3079.104" + wire $ne$ls180.v:3079$74_Y + attribute \src "ls180.v:3140.8-3140.142" + wire $ne$ls180.v:3140$93_Y + attribute \src "ls180.v:3172.75-3172.133" + wire $ne$ls180.v:3172$100_Y + attribute \src "ls180.v:3173.75-3173.133" + wire $ne$ls180.v:3173$101_Y + attribute \src "ls180.v:3297.8-3297.142" + wire $ne$ls180.v:3297$123_Y + attribute \src "ls180.v:3329.75-3329.133" + wire $ne$ls180.v:3329$130_Y + attribute \src "ls180.v:3330.75-3330.133" + wire $ne$ls180.v:3330$131_Y + attribute \src "ls180.v:3454.8-3454.142" + wire $ne$ls180.v:3454$153_Y + attribute \src "ls180.v:3486.75-3486.133" + wire $ne$ls180.v:3486$160_Y + attribute \src "ls180.v:3487.75-3487.133" + wire $ne$ls180.v:3487$161_Y + attribute \src "ls180.v:3611.8-3611.142" + wire $ne$ls180.v:3611$183_Y + attribute \src "ls180.v:3643.75-3643.133" + wire $ne$ls180.v:3643$190_Y + attribute \src "ls180.v:3644.75-3644.133" + wire $ne$ls180.v:3644$191_Y + attribute \src "ls180.v:4136.47-4136.80" + wire $ne$ls180.v:4136$589_Y + attribute \src "ls180.v:4137.47-4137.79" + wire $ne$ls180.v:4137$590_Y + attribute \src "ls180.v:4166.47-4166.80" + wire $ne$ls180.v:4166$600_Y + attribute \src "ls180.v:4167.47-4167.79" + wire $ne$ls180.v:4167$601_Y + attribute \src "ls180.v:4573.32-4573.89" + wire $ne$ls180.v:4573$673_Y + attribute \src "ls180.v:5220.10-5220.56" + wire $ne$ls180.v:5220$970_Y + attribute \src "ls180.v:5325.51-5325.87" + wire $ne$ls180.v:5325$984_Y + attribute \src "ls180.v:5326.51-5326.86" + wire $ne$ls180.v:5326$985_Y + attribute \src "ls180.v:5533.51-5533.87" + wire $ne$ls180.v:5533$1015_Y + attribute \src "ls180.v:5534.51-5534.86" + wire $ne$ls180.v:5534$1016_Y + attribute \src "ls180.v:5624.79-5624.119" + wire $ne$ls180.v:5624$1027_Y + attribute \src "ls180.v:7435.7-7435.52" + wire $ne$ls180.v:7435$2404_Y + attribute \src "ls180.v:7485.9-7485.43" + wire $ne$ls180.v:7485$2418_Y + attribute \src "ls180.v:7521.8-7521.44" + wire $ne$ls180.v:7521$2425_Y + attribute \src "ls180.v:8424.9-8424.47" + wire $ne$ls180.v:8424$2635_Y + attribute \src "ls180.v:2726.45-2726.80" + wire $not$ls180.v:2726$14_Y + attribute \src "ls180.v:2765.61-2765.94" + wire $not$ls180.v:2765$19_Y + attribute \src "ls180.v:2766.61-2766.94" + wire $not$ls180.v:2766$20_Y + attribute \src "ls180.v:2786.45-2786.80" + wire $not$ls180.v:2786$25_Y + attribute \src "ls180.v:2825.61-2825.94" + wire $not$ls180.v:2825$30_Y + attribute \src "ls180.v:2826.61-2826.94" + wire $not$ls180.v:2826$31_Y + attribute \src "ls180.v:2846.45-2846.83" + wire $not$ls180.v:2846$36_Y + attribute \src "ls180.v:2885.61-2885.94" + wire $not$ls180.v:2885$41_Y + attribute \src "ls180.v:2886.61-2886.94" + wire $not$ls180.v:2886$42_Y + attribute \src "ls180.v:3028.34-3028.64" + wire $not$ls180.v:3028$66_Y + attribute \src "ls180.v:3029.31-3029.61" + wire $not$ls180.v:3029$67_Y + attribute \src "ls180.v:3030.32-3030.62" + wire $not$ls180.v:3030$68_Y + attribute \src "ls180.v:3031.32-3031.62" + wire $not$ls180.v:3031$69_Y + attribute \src "ls180.v:3073.33-3073.56" + wire $not$ls180.v:3073$72_Y + attribute \src "ls180.v:3174.58-3174.106" + wire $not$ls180.v:3174$102_Y + attribute \src "ls180.v:3228.9-3228.45" + wire $not$ls180.v:3228$107_Y + attribute \src "ls180.v:3331.58-3331.106" + wire $not$ls180.v:3331$132_Y + attribute \src "ls180.v:3385.9-3385.45" + wire $not$ls180.v:3385$137_Y + attribute \src "ls180.v:3488.58-3488.106" + wire $not$ls180.v:3488$162_Y + attribute \src "ls180.v:3542.9-3542.45" + wire $not$ls180.v:3542$167_Y + attribute \src "ls180.v:3645.58-3645.106" + wire $not$ls180.v:3645$192_Y + attribute \src "ls180.v:3699.9-3699.45" + wire $not$ls180.v:3699$197_Y + attribute \src "ls180.v:3741.149-3741.187" + wire $not$ls180.v:3741$200_Y + attribute \src "ls180.v:3741.193-3741.230" + wire $not$ls180.v:3741$202_Y + attribute \src "ls180.v:3742.149-3742.187" + wire $not$ls180.v:3742$206_Y + attribute \src "ls180.v:3742.193-3742.230" + wire $not$ls180.v:3742$208_Y + attribute \src "ls180.v:3758.43-3758.73" + wire width 2 $not$ls180.v:3758$236_Y + attribute \src "ls180.v:3761.205-3761.245" + wire $not$ls180.v:3761$239_Y + attribute \src "ls180.v:3761.251-3761.290" + wire $not$ls180.v:3761$241_Y + attribute \src "ls180.v:3761.159-3761.292" + wire $not$ls180.v:3761$243_Y + attribute \src "ls180.v:3762.205-3762.245" + wire $not$ls180.v:3762$252_Y + attribute \src "ls180.v:3762.251-3762.290" + wire $not$ls180.v:3762$254_Y + attribute \src "ls180.v:3762.159-3762.292" + wire $not$ls180.v:3762$256_Y + attribute \src "ls180.v:3763.205-3763.245" + wire $not$ls180.v:3763$265_Y + attribute \src "ls180.v:3763.251-3763.290" + wire $not$ls180.v:3763$267_Y + attribute \src "ls180.v:3763.159-3763.292" + wire $not$ls180.v:3763$269_Y + attribute \src "ls180.v:3764.205-3764.245" + wire $not$ls180.v:3764$278_Y + attribute \src "ls180.v:3764.251-3764.290" + wire $not$ls180.v:3764$280_Y + attribute \src "ls180.v:3764.159-3764.292" + wire $not$ls180.v:3764$282_Y + attribute \src "ls180.v:3791.71-3791.103" + wire $not$ls180.v:3791$293_Y + attribute \src "ls180.v:3794.205-3794.245" + wire $not$ls180.v:3794$297_Y + attribute \src "ls180.v:3794.251-3794.290" + wire $not$ls180.v:3794$299_Y + attribute \src "ls180.v:3794.159-3794.292" + wire $not$ls180.v:3794$301_Y + attribute \src "ls180.v:3795.205-3795.245" + wire $not$ls180.v:3795$310_Y + attribute \src "ls180.v:3795.251-3795.290" + wire $not$ls180.v:3795$312_Y + attribute \src "ls180.v:3795.159-3795.292" + wire $not$ls180.v:3795$314_Y + attribute \src "ls180.v:3796.205-3796.245" + wire $not$ls180.v:3796$323_Y + attribute \src "ls180.v:3796.251-3796.290" + wire $not$ls180.v:3796$325_Y + attribute \src "ls180.v:3796.159-3796.292" + wire $not$ls180.v:3796$327_Y + attribute \src "ls180.v:3797.205-3797.245" + wire $not$ls180.v:3797$336_Y + attribute \src "ls180.v:3797.251-3797.290" + wire $not$ls180.v:3797$338_Y + attribute \src "ls180.v:3797.159-3797.292" + wire $not$ls180.v:3797$340_Y + attribute \src "ls180.v:3860.71-3860.103" + wire $not$ls180.v:3860$379_Y + attribute \src "ls180.v:3881.112-3881.150" + wire $not$ls180.v:3881$382_Y + attribute \src "ls180.v:3881.156-3881.193" + wire $not$ls180.v:3881$384_Y + attribute \src "ls180.v:3881.68-3881.195" + wire $not$ls180.v:3881$386_Y + attribute \src "ls180.v:3889.11-3889.38" + wire $not$ls180.v:3889$389_Y + attribute \src "ls180.v:3919.112-3919.150" + wire $not$ls180.v:3919$391_Y + attribute \src "ls180.v:3919.156-3919.193" + wire $not$ls180.v:3919$393_Y + attribute \src "ls180.v:3919.68-3919.195" + wire $not$ls180.v:3919$395_Y + attribute \src "ls180.v:3927.11-3927.37" + wire $not$ls180.v:3927$398_Y + attribute \src "ls180.v:3937.87-3937.331" + wire $not$ls180.v:3937$410_Y + attribute \src "ls180.v:3938.35-3938.68" + wire $not$ls180.v:3938$413_Y + attribute \src "ls180.v:3938.73-3938.105" + wire $not$ls180.v:3938$414_Y + attribute \src "ls180.v:3942.87-3942.331" + wire $not$ls180.v:3942$426_Y + attribute \src "ls180.v:3943.35-3943.68" + wire $not$ls180.v:3943$429_Y + attribute \src "ls180.v:3943.73-3943.105" + wire $not$ls180.v:3943$430_Y + attribute \src "ls180.v:3947.87-3947.331" + wire $not$ls180.v:3947$442_Y + attribute \src "ls180.v:3948.35-3948.68" + wire $not$ls180.v:3948$445_Y + attribute \src "ls180.v:3948.73-3948.105" + wire $not$ls180.v:3948$446_Y + attribute \src "ls180.v:3952.87-3952.331" + wire $not$ls180.v:3952$458_Y + attribute \src "ls180.v:3953.35-3953.68" + wire $not$ls180.v:3953$461_Y + attribute \src "ls180.v:3953.73-3953.105" + wire $not$ls180.v:3953$462_Y + attribute \src "ls180.v:3957.128-3957.372" + wire $not$ls180.v:3957$475_Y + attribute \src "ls180.v:3957.502-3957.746" + wire $not$ls180.v:3957$491_Y + attribute \src "ls180.v:3957.876-3957.1120" + wire $not$ls180.v:3957$507_Y + attribute \src "ls180.v:3957.1250-3957.1494" + wire $not$ls180.v:3957$523_Y + attribute \src "ls180.v:3979.32-3979.50" + wire $not$ls180.v:3979$529_Y + attribute \src "ls180.v:4018.30-4018.50" + wire $not$ls180.v:4018$534_Y + attribute \src "ls180.v:4019.30-4019.50" + wire $not$ls180.v:4019$535_Y + attribute \src "ls180.v:4044.27-4044.48" + wire $not$ls180.v:4044$541_Y + attribute \src "ls180.v:4045.30-4045.50" + wire $not$ls180.v:4045$542_Y + attribute \src "ls180.v:4046.80-4046.98" + wire $not$ls180.v:4046$544_Y + attribute \src "ls180.v:4047.107-4047.127" + wire $not$ls180.v:4047$548_Y + attribute \src "ls180.v:4048.78-4048.103" + wire $not$ls180.v:4048$551_Y + attribute \src "ls180.v:4049.91-4049.111" + wire $not$ls180.v:4049$554_Y + attribute \src "ls180.v:4065.35-4065.64" + wire $not$ls180.v:4065$563_Y + attribute \src "ls180.v:4066.36-4066.67" + wire $not$ls180.v:4066$564_Y + attribute \src "ls180.v:4072.32-4072.61" + wire $not$ls180.v:4072$565_Y + attribute \src "ls180.v:4078.36-4078.67" + wire $not$ls180.v:4078$566_Y + attribute \src "ls180.v:4079.35-4079.64" + wire $not$ls180.v:4079$567_Y + attribute \src "ls180.v:4082.32-4082.63" + wire $not$ls180.v:4082$570_Y + attribute \src "ls180.v:4120.81-4120.108" + wire $not$ls180.v:4120$580_Y + attribute \src "ls180.v:4150.81-4150.108" + wire $not$ls180.v:4150$591_Y + attribute \src "ls180.v:4287.60-4287.85" + wire $not$ls180.v:4287$632_Y + attribute \src "ls180.v:4428.54-4428.96" + wire $not$ls180.v:4428$646_Y + attribute \src "ls180.v:4431.48-4431.86" + wire $not$ls180.v:4431$649_Y + attribute \src "ls180.v:4555.55-4555.98" + wire $not$ls180.v:4555$667_Y + attribute \src "ls180.v:4558.49-4558.88" + wire $not$ls180.v:4558$670_Y + attribute \src "ls180.v:4608.30-4608.58" + wire $not$ls180.v:4608$676_Y + attribute \src "ls180.v:4689.56-4689.100" + wire $not$ls180.v:4689$682_Y + attribute \src "ls180.v:4692.50-4692.90" + wire $not$ls180.v:4692$685_Y + attribute \src "ls180.v:4808.42-4808.74" + wire $not$ls180.v:4808$701_Y + attribute \src "ls180.v:5332.50-5332.88" + wire $not$ls180.v:5332$986_Y + attribute \src "ls180.v:5344.52-5344.102" + wire $not$ls180.v:5344$989_Y + attribute \src "ls180.v:5403.38-5403.74" + wire $not$ls180.v:5403$996_Y + attribute \src "ls180.v:5704.69-5704.88" + wire $not$ls180.v:5704$1065_Y + attribute \src "ls180.v:5721.63-5721.94" + wire $not$ls180.v:5721$1086_Y + attribute \src "ls180.v:5724.65-5724.96" + wire $not$ls180.v:5724$1093_Y + attribute \src "ls180.v:5727.65-5727.96" + wire $not$ls180.v:5727$1100_Y + attribute \src "ls180.v:5730.65-5730.96" + wire $not$ls180.v:5730$1107_Y + attribute \src "ls180.v:5733.65-5733.96" + wire $not$ls180.v:5733$1114_Y + attribute \src "ls180.v:5736.68-5736.99" + wire $not$ls180.v:5736$1121_Y + attribute \src "ls180.v:5739.68-5739.99" + wire $not$ls180.v:5739$1128_Y + attribute \src "ls180.v:5742.68-5742.99" + wire $not$ls180.v:5742$1135_Y + attribute \src "ls180.v:5745.68-5745.99" + wire $not$ls180.v:5745$1142_Y + attribute \src "ls180.v:5759.60-5759.91" + wire $not$ls180.v:5759$1150_Y + attribute \src "ls180.v:5762.60-5762.91" + wire $not$ls180.v:5762$1157_Y + attribute \src "ls180.v:5765.60-5765.91" + wire $not$ls180.v:5765$1164_Y + attribute \src "ls180.v:5768.60-5768.91" + wire $not$ls180.v:5768$1171_Y + attribute \src "ls180.v:5771.61-5771.92" + wire $not$ls180.v:5771$1178_Y + attribute \src "ls180.v:5774.61-5774.92" + wire $not$ls180.v:5774$1185_Y + attribute \src "ls180.v:5785.64-5785.95" + wire $not$ls180.v:5785$1193_Y + attribute \src "ls180.v:5788.63-5788.94" + wire $not$ls180.v:5788$1200_Y + attribute \src "ls180.v:5791.63-5791.94" + wire $not$ls180.v:5791$1207_Y + attribute \src "ls180.v:5794.63-5794.94" + wire $not$ls180.v:5794$1214_Y + attribute \src "ls180.v:5797.63-5797.94" + wire $not$ls180.v:5797$1221_Y + attribute \src "ls180.v:5800.64-5800.95" + wire $not$ls180.v:5800$1228_Y + attribute \src "ls180.v:5803.64-5803.95" + wire $not$ls180.v:5803$1235_Y + attribute \src "ls180.v:5806.64-5806.95" + wire $not$ls180.v:5806$1242_Y + attribute \src "ls180.v:5809.64-5809.95" + wire $not$ls180.v:5809$1249_Y + attribute \src "ls180.v:5822.64-5822.95" + wire $not$ls180.v:5822$1257_Y + attribute \src "ls180.v:5825.63-5825.94" + wire $not$ls180.v:5825$1264_Y + attribute \src "ls180.v:5828.63-5828.94" + wire $not$ls180.v:5828$1271_Y + attribute \src "ls180.v:5831.63-5831.94" + wire $not$ls180.v:5831$1278_Y + attribute \src "ls180.v:5834.63-5834.94" + wire $not$ls180.v:5834$1285_Y + attribute \src "ls180.v:5837.64-5837.95" + wire $not$ls180.v:5837$1292_Y + attribute \src "ls180.v:5840.64-5840.95" + wire $not$ls180.v:5840$1299_Y + attribute \src "ls180.v:5843.64-5843.95" + wire $not$ls180.v:5843$1306_Y + attribute \src "ls180.v:5846.64-5846.95" + wire $not$ls180.v:5846$1313_Y + attribute \src "ls180.v:5859.66-5859.97" + wire $not$ls180.v:5859$1321_Y + attribute \src "ls180.v:5862.66-5862.97" + wire $not$ls180.v:5862$1328_Y + attribute \src "ls180.v:5865.66-5865.97" + wire $not$ls180.v:5865$1335_Y + attribute \src "ls180.v:5868.66-5868.97" + wire $not$ls180.v:5868$1342_Y + attribute \src "ls180.v:5871.66-5871.97" + wire $not$ls180.v:5871$1349_Y + attribute \src "ls180.v:5874.66-5874.97" + wire $not$ls180.v:5874$1356_Y + attribute \src "ls180.v:5877.66-5877.97" + wire $not$ls180.v:5877$1363_Y + attribute \src "ls180.v:5880.66-5880.97" + wire $not$ls180.v:5880$1370_Y + attribute \src "ls180.v:5883.68-5883.99" + wire $not$ls180.v:5883$1377_Y + attribute \src "ls180.v:5886.68-5886.99" + wire $not$ls180.v:5886$1384_Y + attribute \src "ls180.v:5889.68-5889.99" + wire $not$ls180.v:5889$1391_Y + attribute \src "ls180.v:5892.68-5892.99" + wire $not$ls180.v:5892$1398_Y + attribute \src "ls180.v:5895.68-5895.99" + wire $not$ls180.v:5895$1405_Y + attribute \src "ls180.v:5898.65-5898.96" + wire $not$ls180.v:5898$1412_Y + attribute \src "ls180.v:5901.66-5901.97" + wire $not$ls180.v:5901$1419_Y + attribute \src "ls180.v:5921.70-5921.101" + wire $not$ls180.v:5921$1427_Y + attribute \src "ls180.v:5924.70-5924.101" + wire $not$ls180.v:5924$1434_Y + attribute \src "ls180.v:5927.70-5927.101" + wire $not$ls180.v:5927$1441_Y + attribute \src "ls180.v:5930.70-5930.101" + wire $not$ls180.v:5930$1448_Y + attribute \src "ls180.v:5933.69-5933.100" + wire $not$ls180.v:5933$1455_Y + attribute \src "ls180.v:5936.69-5936.100" + wire $not$ls180.v:5936$1462_Y + attribute \src "ls180.v:5939.69-5939.100" + wire $not$ls180.v:5939$1469_Y + attribute \src "ls180.v:5942.69-5942.100" + wire $not$ls180.v:5942$1476_Y + attribute \src "ls180.v:5945.60-5945.91" + wire $not$ls180.v:5945$1483_Y + attribute \src "ls180.v:5948.71-5948.102" + wire $not$ls180.v:5948$1490_Y + attribute \src "ls180.v:5951.71-5951.102" + wire $not$ls180.v:5951$1497_Y + attribute \src "ls180.v:5954.71-5954.102" + wire $not$ls180.v:5954$1504_Y + attribute \src "ls180.v:5957.71-5957.102" + wire $not$ls180.v:5957$1511_Y + attribute \src "ls180.v:5960.71-5960.102" + wire $not$ls180.v:5960$1518_Y + attribute \src "ls180.v:5963.71-5963.102" + wire $not$ls180.v:5963$1525_Y + attribute \src "ls180.v:5966.70-5966.101" + wire $not$ls180.v:5966$1532_Y + attribute \src "ls180.v:5969.70-5969.101" + wire $not$ls180.v:5969$1539_Y + attribute \src "ls180.v:5972.70-5972.101" + wire $not$ls180.v:5972$1546_Y + attribute \src "ls180.v:5975.70-5975.101" + wire $not$ls180.v:5975$1553_Y + attribute \src "ls180.v:5978.70-5978.101" + wire $not$ls180.v:5978$1560_Y + attribute \src "ls180.v:5981.70-5981.101" + wire $not$ls180.v:5981$1567_Y + attribute \src "ls180.v:5984.70-5984.101" + wire $not$ls180.v:5984$1574_Y + attribute \src "ls180.v:5987.70-5987.101" + wire $not$ls180.v:5987$1581_Y + attribute \src "ls180.v:5990.70-5990.101" + wire $not$ls180.v:5990$1588_Y + attribute \src "ls180.v:5993.70-5993.101" + wire $not$ls180.v:5993$1595_Y + attribute \src "ls180.v:5996.66-5996.97" + wire $not$ls180.v:5996$1602_Y + attribute \src "ls180.v:5999.67-5999.98" + wire $not$ls180.v:5999$1609_Y + attribute \src "ls180.v:6002.70-6002.101" + wire $not$ls180.v:6002$1616_Y + attribute \src "ls180.v:6005.70-6005.101" + wire $not$ls180.v:6005$1623_Y + attribute \src "ls180.v:6008.69-6008.100" + wire $not$ls180.v:6008$1630_Y + attribute \src "ls180.v:6011.69-6011.100" + wire $not$ls180.v:6011$1637_Y + attribute \src "ls180.v:6014.69-6014.100" + wire $not$ls180.v:6014$1644_Y + attribute \src "ls180.v:6017.69-6017.100" + wire $not$ls180.v:6017$1651_Y + attribute \src "ls180.v:6056.66-6056.97" + wire $not$ls180.v:6056$1659_Y + attribute \src "ls180.v:6059.66-6059.97" + wire $not$ls180.v:6059$1666_Y + attribute \src "ls180.v:6062.66-6062.97" + wire $not$ls180.v:6062$1673_Y + attribute \src "ls180.v:6065.66-6065.97" + wire $not$ls180.v:6065$1680_Y + attribute \src "ls180.v:6068.66-6068.97" + wire $not$ls180.v:6068$1687_Y + attribute \src "ls180.v:6071.66-6071.97" + wire $not$ls180.v:6071$1694_Y + attribute \src "ls180.v:6074.66-6074.97" + wire $not$ls180.v:6074$1701_Y + attribute \src "ls180.v:6077.66-6077.97" + wire $not$ls180.v:6077$1708_Y + attribute \src "ls180.v:6080.68-6080.99" + wire $not$ls180.v:6080$1715_Y + attribute \src "ls180.v:6083.68-6083.99" + wire $not$ls180.v:6083$1722_Y + attribute \src "ls180.v:6086.68-6086.99" + wire $not$ls180.v:6086$1729_Y + attribute \src "ls180.v:6089.68-6089.99" + wire $not$ls180.v:6089$1736_Y + attribute \src "ls180.v:6092.68-6092.99" + wire $not$ls180.v:6092$1743_Y + attribute \src "ls180.v:6095.65-6095.96" + wire $not$ls180.v:6095$1750_Y + attribute \src "ls180.v:6098.66-6098.97" + wire $not$ls180.v:6098$1757_Y + attribute \src "ls180.v:6101.68-6101.99" + wire $not$ls180.v:6101$1764_Y + attribute \src "ls180.v:6104.68-6104.99" + wire $not$ls180.v:6104$1771_Y + attribute \src "ls180.v:6107.68-6107.99" + wire $not$ls180.v:6107$1778_Y + attribute \src "ls180.v:6110.68-6110.99" + wire $not$ls180.v:6110$1785_Y + attribute \src "ls180.v:6135.68-6135.99" + wire $not$ls180.v:6135$1793_Y + attribute \src "ls180.v:6138.73-6138.104" + wire $not$ls180.v:6138$1800_Y + attribute \src "ls180.v:6141.73-6141.104" + wire $not$ls180.v:6141$1807_Y + attribute \src "ls180.v:6144.66-6144.97" + wire $not$ls180.v:6144$1814_Y + attribute \src "ls180.v:6152.70-6152.101" + wire $not$ls180.v:6152$1822_Y + attribute \src "ls180.v:6155.74-6155.105" + wire $not$ls180.v:6155$1829_Y + attribute \src "ls180.v:6158.64-6158.95" + wire $not$ls180.v:6158$1836_Y + attribute \src "ls180.v:6161.74-6161.105" + wire $not$ls180.v:6161$1843_Y + attribute \src "ls180.v:6164.74-6164.105" + wire $not$ls180.v:6164$1850_Y + attribute \src "ls180.v:6167.75-6167.106" + wire $not$ls180.v:6167$1857_Y + attribute \src "ls180.v:6170.73-6170.104" + wire $not$ls180.v:6170$1864_Y + attribute \src "ls180.v:6173.73-6173.104" + wire $not$ls180.v:6173$1871_Y + attribute \src "ls180.v:6176.73-6176.104" + wire $not$ls180.v:6176$1878_Y + attribute \src "ls180.v:6179.73-6179.104" + wire $not$ls180.v:6179$1885_Y + attribute \src "ls180.v:6197.65-6197.96" + wire $not$ls180.v:6197$1893_Y + attribute \src "ls180.v:6200.65-6200.96" + wire $not$ls180.v:6200$1900_Y + attribute \src "ls180.v:6203.63-6203.94" + wire $not$ls180.v:6203$1907_Y + attribute \src "ls180.v:6206.62-6206.93" + wire $not$ls180.v:6206$1914_Y + attribute \src "ls180.v:6209.61-6209.92" + wire $not$ls180.v:6209$1921_Y + attribute \src "ls180.v:6212.60-6212.91" + wire $not$ls180.v:6212$1928_Y + attribute \src "ls180.v:6215.66-6215.97" + wire $not$ls180.v:6215$1935_Y + attribute \src "ls180.v:6237.67-6237.99" + wire $not$ls180.v:6237$1944_Y + attribute \src "ls180.v:6240.67-6240.99" + wire $not$ls180.v:6240$1951_Y + attribute \src "ls180.v:6243.65-6243.97" + wire $not$ls180.v:6243$1958_Y + attribute \src "ls180.v:6246.64-6246.96" + wire $not$ls180.v:6246$1965_Y + attribute \src "ls180.v:6249.63-6249.95" + wire $not$ls180.v:6249$1972_Y + attribute \src "ls180.v:6252.62-6252.94" + wire $not$ls180.v:6252$1979_Y + attribute \src "ls180.v:6255.68-6255.100" + wire $not$ls180.v:6255$1986_Y + attribute \src "ls180.v:6258.71-6258.103" + wire $not$ls180.v:6258$1993_Y + attribute \src "ls180.v:6261.71-6261.103" + wire $not$ls180.v:6261$2000_Y + attribute \src "ls180.v:6285.64-6285.96" + wire $not$ls180.v:6285$2009_Y + attribute \src "ls180.v:6288.64-6288.96" + wire $not$ls180.v:6288$2016_Y + attribute \src "ls180.v:6291.64-6291.96" + wire $not$ls180.v:6291$2023_Y + attribute \src "ls180.v:6294.64-6294.96" + wire $not$ls180.v:6294$2030_Y + attribute \src "ls180.v:6297.66-6297.98" + wire $not$ls180.v:6297$2037_Y + attribute \src "ls180.v:6300.66-6300.98" + wire $not$ls180.v:6300$2044_Y + attribute \src "ls180.v:6303.66-6303.98" + wire $not$ls180.v:6303$2051_Y + attribute \src "ls180.v:6306.66-6306.98" + wire $not$ls180.v:6306$2058_Y + attribute \src "ls180.v:6309.62-6309.94" + wire $not$ls180.v:6309$2065_Y + attribute \src "ls180.v:6312.72-6312.104" + wire $not$ls180.v:6312$2072_Y + attribute \src "ls180.v:6315.65-6315.97" + wire $not$ls180.v:6315$2079_Y + attribute \src "ls180.v:6318.65-6318.97" + wire $not$ls180.v:6318$2086_Y + attribute \src "ls180.v:6321.65-6321.97" + wire $not$ls180.v:6321$2093_Y + attribute \src "ls180.v:6324.65-6324.97" + wire $not$ls180.v:6324$2100_Y + attribute \src "ls180.v:6327.77-6327.109" + wire $not$ls180.v:6327$2107_Y + attribute \src "ls180.v:6330.78-6330.110" + wire $not$ls180.v:6330$2114_Y + attribute \src "ls180.v:6333.69-6333.101" + wire $not$ls180.v:6333$2121_Y + attribute \src "ls180.v:6353.55-6353.87" + wire $not$ls180.v:6353$2129_Y + attribute \src "ls180.v:6356.65-6356.97" + wire $not$ls180.v:6356$2136_Y + attribute \src "ls180.v:6359.66-6359.98" + wire $not$ls180.v:6359$2143_Y + attribute \src "ls180.v:6362.70-6362.102" + wire $not$ls180.v:6362$2150_Y + attribute \src "ls180.v:6365.71-6365.103" + wire $not$ls180.v:6365$2157_Y + attribute \src "ls180.v:6368.69-6368.101" + wire $not$ls180.v:6368$2164_Y + attribute \src "ls180.v:6371.66-6371.98" + wire $not$ls180.v:6371$2171_Y + attribute \src "ls180.v:6374.65-6374.97" + wire $not$ls180.v:6374$2178_Y + attribute \src "ls180.v:6387.71-6387.103" + wire $not$ls180.v:6387$2186_Y + attribute \src "ls180.v:6390.71-6390.103" + wire $not$ls180.v:6390$2193_Y + attribute \src "ls180.v:6393.71-6393.103" + wire $not$ls180.v:6393$2200_Y + attribute \src "ls180.v:6396.71-6396.103" + wire $not$ls180.v:6396$2207_Y + attribute \src "ls180.v:6774.86-6774.330" + wire $not$ls180.v:6774$2255_Y + attribute \src "ls180.v:6798.86-6798.330" + wire $not$ls180.v:6798$2271_Y + attribute \src "ls180.v:6822.86-6822.330" + wire $not$ls180.v:6822$2287_Y + attribute \src "ls180.v:6846.86-6846.330" + wire $not$ls180.v:6846$2303_Y + attribute \src "ls180.v:7344.18-7344.42" + wire $not$ls180.v:7344$2356_Y + attribute \src "ls180.v:7441.72-7441.101" + wire $not$ls180.v:7441$2407_Y + attribute \src "ls180.v:7460.8-7460.38" + wire $not$ls180.v:7460$2411_Y + attribute \src "ls180.v:7468.32-7468.55" + wire $not$ls180.v:7468$2413_Y + attribute \src "ls180.v:7538.136-7538.189" + wire $not$ls180.v:7538$2428_Y + attribute \src "ls180.v:7544.136-7544.189" + wire $not$ls180.v:7544$2433_Y + attribute \src "ls180.v:7545.8-7545.61" + wire $not$ls180.v:7545$2435_Y + attribute \src "ls180.v:7553.8-7553.56" + wire $not$ls180.v:7553$2438_Y + attribute \src "ls180.v:7568.8-7568.46" + wire $not$ls180.v:7568$2440_Y + attribute \src "ls180.v:7584.136-7584.189" + wire $not$ls180.v:7584$2444_Y + attribute \src "ls180.v:7590.136-7590.189" + wire $not$ls180.v:7590$2449_Y + attribute \src "ls180.v:7591.8-7591.61" + wire $not$ls180.v:7591$2451_Y + attribute \src "ls180.v:7599.8-7599.56" + wire $not$ls180.v:7599$2454_Y + attribute \src "ls180.v:7614.8-7614.46" + wire $not$ls180.v:7614$2456_Y + attribute \src "ls180.v:7630.136-7630.189" + wire $not$ls180.v:7630$2460_Y + attribute \src "ls180.v:7636.136-7636.189" + wire $not$ls180.v:7636$2465_Y + attribute \src "ls180.v:7637.8-7637.61" + wire $not$ls180.v:7637$2467_Y + attribute \src "ls180.v:7645.8-7645.56" + wire $not$ls180.v:7645$2470_Y + attribute \src "ls180.v:7660.8-7660.46" + wire $not$ls180.v:7660$2472_Y + attribute \src "ls180.v:7676.136-7676.189" + wire $not$ls180.v:7676$2476_Y + attribute \src "ls180.v:7682.136-7682.189" + wire $not$ls180.v:7682$2481_Y + attribute \src "ls180.v:7683.8-7683.61" + wire $not$ls180.v:7683$2483_Y + attribute \src "ls180.v:7691.8-7691.56" + wire $not$ls180.v:7691$2486_Y + attribute \src "ls180.v:7706.8-7706.46" + wire $not$ls180.v:7706$2488_Y + attribute \src "ls180.v:7714.7-7714.22" + wire $not$ls180.v:7714$2491_Y + attribute \src "ls180.v:7717.8-7717.29" + wire $not$ls180.v:7717$2492_Y + attribute \src "ls180.v:7721.7-7721.22" + wire $not$ls180.v:7721$2494_Y + attribute \src "ls180.v:7724.8-7724.29" + wire $not$ls180.v:7724$2495_Y + attribute \src "ls180.v:7843.30-7843.60" + wire $not$ls180.v:7843$2497_Y + attribute \src "ls180.v:7844.30-7844.60" + wire $not$ls180.v:7844$2498_Y + attribute \src "ls180.v:7845.29-7845.59" + wire $not$ls180.v:7845$2499_Y + attribute \src "ls180.v:7856.8-7856.33" + wire $not$ls180.v:7856$2500_Y + attribute \src "ls180.v:7871.8-7871.33" + wire $not$ls180.v:7871$2503_Y + attribute \src "ls180.v:7907.27-7907.40" + wire $not$ls180.v:7907$2533_Y + attribute \src "ls180.v:7907.46-7907.62" + wire $not$ls180.v:7907$2535_Y + attribute \src "ls180.v:7936.7-7936.20" + wire $not$ls180.v:7936$2542_Y + attribute \src "ls180.v:7937.9-7937.17" + wire $not$ls180.v:7937$2543_Y + attribute \src "ls180.v:7970.8-7970.29" + wire $not$ls180.v:7970$2549_Y + attribute \src "ls180.v:7977.8-7977.29" + wire $not$ls180.v:7977$2551_Y + attribute \src "ls180.v:7987.80-7987.106" + wire $not$ls180.v:7987$2554_Y + attribute \src "ls180.v:7993.80-7993.106" + wire $not$ls180.v:7993$2559_Y + attribute \src "ls180.v:7994.8-7994.34" + wire $not$ls180.v:7994$2561_Y + attribute \src "ls180.v:8009.80-8009.106" + wire $not$ls180.v:8009$2565_Y + attribute \src "ls180.v:8015.80-8015.106" + wire $not$ls180.v:8015$2570_Y + attribute \src "ls180.v:8016.8-8016.34" + wire $not$ls180.v:8016$2572_Y + attribute \src "ls180.v:8047.23-8047.42" + wire $not$ls180.v:8047$2576_Y + attribute \src "ls180.v:8047.47-8047.73" + wire $not$ls180.v:8047$2577_Y + attribute \src "ls180.v:8101.7-8101.31" + wire $not$ls180.v:8101$2588_Y + attribute \src "ls180.v:8173.8-8173.46" + wire $not$ls180.v:8173$2600_Y + attribute \src "ls180.v:8254.8-8254.47" + wire $not$ls180.v:8254$2612_Y + attribute \src "ls180.v:8315.8-8315.48" + wire $not$ls180.v:8315$2624_Y + attribute \src "ls180.v:8485.88-8485.118" + wire $not$ls180.v:8485$2638_Y + attribute \src "ls180.v:8491.88-8491.118" + wire $not$ls180.v:8491$2643_Y + attribute \src "ls180.v:8492.8-8492.38" + wire $not$ls180.v:8492$2645_Y + attribute \src "ls180.v:8571.88-8571.118" + wire $not$ls180.v:8571$2660_Y + attribute \src "ls180.v:8577.88-8577.118" + wire $not$ls180.v:8577$2665_Y + attribute \src "ls180.v:8578.8-8578.38" + wire $not$ls180.v:8578$2667_Y + attribute \src "ls180.v:8595.22-8595.37" + wire $not$ls180.v:8595$2671_Y + attribute \src "ls180.v:8595.42-8595.64" + wire $not$ls180.v:8595$2672_Y + attribute \src "ls180.v:8633.9-8633.28" + wire $not$ls180.v:8633$2675_Y + attribute \src "ls180.v:8652.9-8652.28" + wire $not$ls180.v:8652$2676_Y + attribute \src "ls180.v:8671.9-8671.28" + wire $not$ls180.v:8671$2677_Y + attribute \src "ls180.v:8690.9-8690.28" + wire $not$ls180.v:8690$2678_Y + attribute \src "ls180.v:8709.9-8709.28" + wire $not$ls180.v:8709$2679_Y + attribute \src "ls180.v:8730.8-8730.21" + wire $not$ls180.v:8730$2680_Y + attribute \src "ls180.v:10195.8-10195.51" + wire $or$ls180.v:10195$2752_Y + attribute \src "ls180.v:2767.10-2767.96" + wire $or$ls180.v:2767$21_Y + attribute \src "ls180.v:2827.10-2827.96" + wire $or$ls180.v:2827$32_Y + attribute \src "ls180.v:2887.10-2887.96" + wire $or$ls180.v:2887$43_Y + attribute \src "ls180.v:3079.39-3079.105" + wire $or$ls180.v:3079$75_Y + attribute \src "ls180.v:3122.59-3122.140" + wire $or$ls180.v:3122$79_Y + attribute \src "ls180.v:3123.44-3123.151" + wire $or$ls180.v:3123$80_Y + attribute \src "ls180.v:3131.45-3131.170" + wire width 13 $or$ls180.v:3131$84_Y + attribute \src "ls180.v:3168.127-3168.245" + wire $or$ls180.v:3168$97_Y + attribute \src "ls180.v:3174.57-3174.157" + wire $or$ls180.v:3174$103_Y + attribute \src "ls180.v:3279.59-3279.140" + wire $or$ls180.v:3279$109_Y + attribute \src "ls180.v:3280.44-3280.151" + wire $or$ls180.v:3280$110_Y + attribute \src "ls180.v:3288.45-3288.170" + wire width 13 $or$ls180.v:3288$114_Y + attribute \src "ls180.v:3325.127-3325.245" + wire $or$ls180.v:3325$127_Y + attribute \src "ls180.v:3331.57-3331.157" + wire $or$ls180.v:3331$133_Y + attribute \src "ls180.v:3436.59-3436.140" + wire $or$ls180.v:3436$139_Y + attribute \src "ls180.v:3437.44-3437.151" + wire $or$ls180.v:3437$140_Y + attribute \src "ls180.v:3445.45-3445.170" + wire width 13 $or$ls180.v:3445$144_Y + attribute \src "ls180.v:3482.127-3482.245" + wire $or$ls180.v:3482$157_Y + attribute \src "ls180.v:3488.57-3488.157" + wire $or$ls180.v:3488$163_Y + attribute \src "ls180.v:3593.59-3593.140" + wire $or$ls180.v:3593$169_Y + attribute \src "ls180.v:3594.44-3594.151" + wire $or$ls180.v:3594$170_Y + attribute \src "ls180.v:3602.45-3602.170" + wire width 13 $or$ls180.v:3602$174_Y + attribute \src "ls180.v:3639.127-3639.245" + wire $or$ls180.v:3639$187_Y + attribute \src "ls180.v:3645.57-3645.157" + wire $or$ls180.v:3645$193_Y + attribute \src "ls180.v:3744.107-3744.193" + wire $or$ls180.v:3744$213_Y + attribute \src "ls180.v:3747.39-3747.204" + wire $or$ls180.v:3747$219_Y + attribute \src "ls180.v:3747.38-3747.289" + wire $or$ls180.v:3747$221_Y + attribute \src "ls180.v:3747.37-3747.374" + wire $or$ls180.v:3747$223_Y + attribute \src "ls180.v:3748.40-3748.207" + wire $or$ls180.v:3748$226_Y + attribute \src "ls180.v:3748.39-3748.293" + wire $or$ls180.v:3748$228_Y + attribute \src "ls180.v:3748.38-3748.379" + wire $or$ls180.v:3748$230_Y + attribute \src "ls180.v:3761.158-3761.332" + wire $or$ls180.v:3761$244_Y + attribute \src "ls180.v:3761.75-3761.506" + wire $or$ls180.v:3761$249_Y + attribute \src "ls180.v:3762.158-3762.332" + wire $or$ls180.v:3762$257_Y + attribute \src "ls180.v:3762.75-3762.506" + wire $or$ls180.v:3762$262_Y + attribute \src "ls180.v:3763.158-3763.332" + wire $or$ls180.v:3763$270_Y + attribute \src "ls180.v:3763.75-3763.506" + wire $or$ls180.v:3763$275_Y + attribute \src "ls180.v:3764.158-3764.332" + wire $or$ls180.v:3764$283_Y + attribute \src "ls180.v:3764.75-3764.506" + wire $or$ls180.v:3764$288_Y + attribute \src "ls180.v:3791.36-3791.104" + wire $or$ls180.v:3791$294_Y + attribute \src "ls180.v:3794.158-3794.332" + wire $or$ls180.v:3794$302_Y + attribute \src "ls180.v:3794.75-3794.506" + wire $or$ls180.v:3794$307_Y + attribute \src "ls180.v:3795.158-3795.332" + wire $or$ls180.v:3795$315_Y + attribute \src "ls180.v:3795.75-3795.506" + wire $or$ls180.v:3795$320_Y + attribute \src "ls180.v:3796.158-3796.332" + wire $or$ls180.v:3796$328_Y + attribute \src "ls180.v:3796.75-3796.506" + wire $or$ls180.v:3796$333_Y + attribute \src "ls180.v:3797.158-3797.332" + wire $or$ls180.v:3797$341_Y + attribute \src "ls180.v:3797.75-3797.506" + wire $or$ls180.v:3797$346_Y + attribute \src "ls180.v:3860.36-3860.104" + wire $or$ls180.v:3860$380_Y + attribute \src "ls180.v:3881.67-3881.221" + wire $or$ls180.v:3881$387_Y + attribute \src "ls180.v:3889.10-3889.62" + wire $or$ls180.v:3889$390_Y + attribute \src "ls180.v:3919.67-3919.221" + wire $or$ls180.v:3919$396_Y + attribute \src "ls180.v:3927.10-3927.61" + wire $or$ls180.v:3927$399_Y + attribute \src "ls180.v:3937.91-3937.180" + wire $or$ls180.v:3937$403_Y + attribute \src "ls180.v:3937.90-3937.255" + wire $or$ls180.v:3937$406_Y + attribute \src "ls180.v:3937.89-3937.330" + wire $or$ls180.v:3937$409_Y + attribute \src "ls180.v:3942.91-3942.180" + wire $or$ls180.v:3942$419_Y + attribute \src "ls180.v:3942.90-3942.255" + wire $or$ls180.v:3942$422_Y + attribute \src "ls180.v:3942.89-3942.330" + wire $or$ls180.v:3942$425_Y + attribute \src "ls180.v:3947.91-3947.180" + wire $or$ls180.v:3947$435_Y + attribute \src "ls180.v:3947.90-3947.255" + wire $or$ls180.v:3947$438_Y + attribute \src "ls180.v:3947.89-3947.330" + wire $or$ls180.v:3947$441_Y + attribute \src "ls180.v:3952.91-3952.180" + wire $or$ls180.v:3952$451_Y + attribute \src "ls180.v:3952.90-3952.255" + wire $or$ls180.v:3952$454_Y + attribute \src "ls180.v:3952.89-3952.330" + wire $or$ls180.v:3952$457_Y + attribute \src "ls180.v:3957.132-3957.221" + wire $or$ls180.v:3957$468_Y + attribute \src "ls180.v:3957.131-3957.296" + wire $or$ls180.v:3957$471_Y + attribute \src "ls180.v:3957.130-3957.371" + wire $or$ls180.v:3957$474_Y + attribute \src "ls180.v:3957.34-3957.411" + wire $or$ls180.v:3957$479_Y + attribute \src "ls180.v:3957.506-3957.595" + wire $or$ls180.v:3957$484_Y + attribute \src "ls180.v:3957.505-3957.670" + wire $or$ls180.v:3957$487_Y + attribute \src "ls180.v:3957.504-3957.745" + wire $or$ls180.v:3957$490_Y + attribute \src "ls180.v:3957.33-3957.785" + wire $or$ls180.v:3957$495_Y + attribute \src "ls180.v:3957.880-3957.969" + wire $or$ls180.v:3957$500_Y + attribute \src "ls180.v:3957.879-3957.1044" + wire $or$ls180.v:3957$503_Y + attribute \src "ls180.v:3957.878-3957.1119" + wire $or$ls180.v:3957$506_Y + attribute \src "ls180.v:3957.32-3957.1159" + wire $or$ls180.v:3957$511_Y + attribute \src "ls180.v:3957.1254-3957.1343" + wire $or$ls180.v:3957$516_Y + attribute \src "ls180.v:3957.1253-3957.1418" + wire $or$ls180.v:3957$519_Y + attribute \src "ls180.v:3957.1252-3957.1493" + wire $or$ls180.v:3957$522_Y + attribute \src "ls180.v:3957.31-3957.1533" + wire $or$ls180.v:3957$527_Y + attribute \src "ls180.v:4020.10-4020.52" + wire $or$ls180.v:4020$536_Y + attribute \src "ls180.v:4047.35-4047.74" + wire $or$ls180.v:4047$546_Y + attribute \src "ls180.v:4048.34-4048.73" + wire $or$ls180.v:4048$550_Y + attribute \src "ls180.v:4049.48-4049.130" + wire $or$ls180.v:4049$556_Y + attribute \src "ls180.v:4050.24-4050.87" + wire $or$ls180.v:4050$559_Y + attribute \src "ls180.v:4051.26-4051.95" + wire $or$ls180.v:4051$561_Y + attribute \src "ls180.v:4081.42-4081.89" + wire $or$ls180.v:4081$569_Y + attribute \src "ls180.v:4105.25-4105.174" + wire $or$ls180.v:4105$579_Y + attribute \src "ls180.v:4120.80-4120.132" + wire $or$ls180.v:4120$581_Y + attribute \src "ls180.v:4131.72-4131.135" + wire $or$ls180.v:4131$586_Y + attribute \src "ls180.v:4150.80-4150.132" + wire $or$ls180.v:4150$592_Y + attribute \src "ls180.v:4161.72-4161.135" + wire $or$ls180.v:4161$597_Y + attribute \src "ls180.v:4232.36-4232.111" + wire $or$ls180.v:4232$610_Y + attribute \src "ls180.v:4232.35-4232.151" + wire $or$ls180.v:4232$611_Y + attribute \src "ls180.v:4232.34-4232.192" + wire $or$ls180.v:4232$612_Y + attribute \src "ls180.v:4232.33-4232.233" + wire $or$ls180.v:4232$613_Y + attribute \src "ls180.v:4233.39-4233.120" + wire $or$ls180.v:4233$614_Y + attribute \src "ls180.v:4233.38-4233.163" + wire $or$ls180.v:4233$615_Y + attribute \src "ls180.v:4233.37-4233.207" + wire $or$ls180.v:4233$616_Y + attribute \src "ls180.v:4233.36-4233.251" + wire $or$ls180.v:4233$617_Y + attribute \src "ls180.v:4234.38-4234.117" + wire $or$ls180.v:4234$618_Y + attribute \src "ls180.v:4234.37-4234.159" + wire $or$ls180.v:4234$619_Y + attribute \src "ls180.v:4234.36-4234.202" + wire $or$ls180.v:4234$620_Y + attribute \src "ls180.v:4234.35-4234.245" + wire $or$ls180.v:4234$621_Y + attribute \src "ls180.v:4235.40-4235.123" + wire $or$ls180.v:4235$622_Y + attribute \src "ls180.v:4235.39-4235.167" + wire $or$ls180.v:4235$623_Y + attribute \src "ls180.v:4235.38-4235.212" + wire $or$ls180.v:4235$624_Y + attribute \src "ls180.v:4235.37-4235.257" + wire $or$ls180.v:4235$625_Y + attribute \src "ls180.v:4236.39-4236.120" + wire width 4 $or$ls180.v:4236$626_Y + attribute \src "ls180.v:4236.38-4236.163" + wire width 4 $or$ls180.v:4236$627_Y + attribute \src "ls180.v:4236.37-4236.207" + wire width 4 $or$ls180.v:4236$628_Y + attribute \src "ls180.v:4236.36-4236.251" + wire width 4 $or$ls180.v:4236$629_Y + attribute \src "ls180.v:4257.35-4257.80" + wire $or$ls180.v:4257$630_Y + attribute \src "ls180.v:4411.91-4411.144" + wire $or$ls180.v:4411$644_Y + attribute \src "ls180.v:4428.53-4428.143" + wire $or$ls180.v:4428$647_Y + attribute \src "ls180.v:4431.47-4431.127" + wire $or$ls180.v:4431$650_Y + attribute \src "ls180.v:4555.54-4555.146" + wire $or$ls180.v:4555$668_Y + attribute \src "ls180.v:4558.48-4558.130" + wire $or$ls180.v:4558$671_Y + attribute \src "ls180.v:4689.55-4689.149" + wire $or$ls180.v:4689$683_Y + attribute \src "ls180.v:4692.49-4692.133" + wire $or$ls180.v:4692$686_Y + attribute \src "ls180.v:5321.80-5321.151" + wire $or$ls180.v:5321$981_Y + attribute \src "ls180.v:5332.49-5332.131" + wire $or$ls180.v:5332$987_Y + attribute \src "ls180.v:5529.80-5529.151" + wire $or$ls180.v:5529$1012_Y + attribute \src "ls180.v:5703.33-5703.102" + wire $or$ls180.v:5703$1060_Y + attribute \src "ls180.v:5703.32-5703.144" + wire $or$ls180.v:5703$1061_Y + attribute \src "ls180.v:5703.31-5703.165" + wire $or$ls180.v:5703$1062_Y + attribute \src "ls180.v:5703.30-5703.201" + wire $or$ls180.v:5703$1063_Y + attribute \src "ls180.v:5709.28-5709.97" + wire $or$ls180.v:5709$1068_Y + attribute \src "ls180.v:5709.27-5709.139" + wire $or$ls180.v:5709$1069_Y + attribute \src "ls180.v:5709.26-5709.160" + wire $or$ls180.v:5709$1070_Y + attribute \src "ls180.v:5709.25-5709.196" + wire $or$ls180.v:5709$1071_Y + attribute \src "ls180.v:5710.30-5710.169" + wire width 32 $or$ls180.v:5710$1074_Y + attribute \src "ls180.v:5710.29-5710.246" + wire width 32 $or$ls180.v:5710$1076_Y + attribute \src "ls180.v:5710.28-5710.302" + wire width 32 $or$ls180.v:5710$1078_Y + attribute \src "ls180.v:5710.27-5710.373" + wire width 32 $or$ls180.v:5710$1080_Y + attribute \src "ls180.v:6447.54-6447.123" + wire width 8 $or$ls180.v:6447$2211_Y + attribute \src "ls180.v:6447.53-6447.160" + wire width 8 $or$ls180.v:6447$2212_Y + attribute \src "ls180.v:6447.52-6447.197" + wire width 8 $or$ls180.v:6447$2213_Y + attribute \src "ls180.v:6447.51-6447.234" + wire width 8 $or$ls180.v:6447$2214_Y + attribute \src "ls180.v:6447.50-6447.271" + wire width 8 $or$ls180.v:6447$2215_Y + attribute \src "ls180.v:6447.49-6447.308" + wire width 8 $or$ls180.v:6447$2216_Y + attribute \src "ls180.v:6447.48-6447.345" + wire width 8 $or$ls180.v:6447$2217_Y + attribute \src "ls180.v:6447.47-6447.382" + wire width 8 $or$ls180.v:6447$2218_Y + attribute \src "ls180.v:6447.46-6447.419" + wire width 8 $or$ls180.v:6447$2219_Y + attribute \src "ls180.v:6447.45-6447.457" + wire width 8 $or$ls180.v:6447$2220_Y + attribute \src "ls180.v:6447.44-6447.495" + wire width 8 $or$ls180.v:6447$2221_Y + attribute \src "ls180.v:6447.43-6447.533" + wire width 8 $or$ls180.v:6447$2222_Y + attribute \src "ls180.v:6447.42-6447.571" + wire width 8 $or$ls180.v:6447$2223_Y + attribute \src "ls180.v:6774.90-6774.179" + wire $or$ls180.v:6774$2248_Y + attribute \src "ls180.v:6774.89-6774.254" + wire $or$ls180.v:6774$2251_Y + attribute \src "ls180.v:6774.88-6774.329" + wire $or$ls180.v:6774$2254_Y + attribute \src "ls180.v:6798.90-6798.179" + wire $or$ls180.v:6798$2264_Y + attribute \src "ls180.v:6798.89-6798.254" + wire $or$ls180.v:6798$2267_Y + attribute \src "ls180.v:6798.88-6798.329" + wire $or$ls180.v:6798$2270_Y + attribute \src "ls180.v:6822.90-6822.179" + wire $or$ls180.v:6822$2280_Y + attribute \src "ls180.v:6822.89-6822.254" + wire $or$ls180.v:6822$2283_Y + attribute \src "ls180.v:6822.88-6822.329" + wire $or$ls180.v:6822$2286_Y + attribute \src "ls180.v:6846.90-6846.179" + wire $or$ls180.v:6846$2296_Y + attribute \src "ls180.v:6846.89-6846.254" + wire $or$ls180.v:6846$2299_Y + attribute \src "ls180.v:6846.88-6846.329" + wire $or$ls180.v:6846$2302_Y + attribute \src "ls180.v:7360.20-7360.71" + wire $or$ls180.v:7360$2359_Y + attribute \src "ls180.v:7361.20-7361.71" + wire $or$ls180.v:7361$2360_Y + attribute \src "ls180.v:7362.20-7362.71" + wire $or$ls180.v:7362$2361_Y + attribute \src "ls180.v:7363.20-7363.71" + wire $or$ls180.v:7363$2362_Y + attribute \src "ls180.v:7364.20-7364.71" + wire $or$ls180.v:7364$2363_Y + attribute \src "ls180.v:7365.20-7365.71" + wire $or$ls180.v:7365$2364_Y + attribute \src "ls180.v:7366.20-7366.71" + wire $or$ls180.v:7366$2365_Y + attribute \src "ls180.v:7367.20-7367.71" + wire $or$ls180.v:7367$2366_Y + attribute \src "ls180.v:7368.20-7368.71" + wire $or$ls180.v:7368$2367_Y + attribute \src "ls180.v:7369.20-7369.71" + wire $or$ls180.v:7369$2368_Y + attribute \src "ls180.v:7370.21-7370.73" + wire $or$ls180.v:7370$2369_Y + attribute \src "ls180.v:7371.21-7371.73" + wire $or$ls180.v:7371$2370_Y + attribute \src "ls180.v:7372.21-7372.73" + wire $or$ls180.v:7372$2371_Y + attribute \src "ls180.v:7373.21-7373.73" + wire $or$ls180.v:7373$2372_Y + attribute \src "ls180.v:7374.21-7374.73" + wire $or$ls180.v:7374$2373_Y + attribute \src "ls180.v:7375.21-7375.73" + wire $or$ls180.v:7375$2374_Y + attribute \src "ls180.v:7376.21-7376.73" + wire $or$ls180.v:7376$2375_Y + attribute \src "ls180.v:7377.21-7377.73" + wire $or$ls180.v:7377$2376_Y + attribute \src "ls180.v:7378.21-7378.73" + wire $or$ls180.v:7378$2377_Y + attribute \src "ls180.v:7379.21-7379.73" + wire $or$ls180.v:7379$2378_Y + attribute \src "ls180.v:7380.21-7380.73" + wire $or$ls180.v:7380$2379_Y + attribute \src "ls180.v:7381.21-7381.73" + wire $or$ls180.v:7381$2380_Y + attribute \src "ls180.v:7382.21-7382.73" + wire $or$ls180.v:7382$2381_Y + attribute \src "ls180.v:7383.21-7383.73" + wire $or$ls180.v:7383$2382_Y + attribute \src "ls180.v:7384.21-7384.73" + wire $or$ls180.v:7384$2383_Y + attribute \src "ls180.v:7385.21-7385.73" + wire $or$ls180.v:7385$2384_Y + attribute \src "ls180.v:7386.21-7386.73" + wire $or$ls180.v:7386$2385_Y + attribute \src "ls180.v:7387.21-7387.73" + wire $or$ls180.v:7387$2386_Y + attribute \src "ls180.v:7388.21-7388.73" + wire $or$ls180.v:7388$2387_Y + attribute \src "ls180.v:7389.21-7389.73" + wire $or$ls180.v:7389$2388_Y + attribute \src "ls180.v:7390.21-7390.73" + wire $or$ls180.v:7390$2389_Y + attribute \src "ls180.v:7391.21-7391.73" + wire $or$ls180.v:7391$2390_Y + attribute \src "ls180.v:7392.21-7392.73" + wire $or$ls180.v:7392$2391_Y + attribute \src "ls180.v:7393.21-7393.73" + wire $or$ls180.v:7393$2392_Y + attribute \src "ls180.v:7394.21-7394.73" + wire $or$ls180.v:7394$2393_Y + attribute \src "ls180.v:7395.21-7395.73" + wire $or$ls180.v:7395$2394_Y + attribute \src "ls180.v:7396.21-7396.73" + wire $or$ls180.v:7396$2395_Y + attribute \src "ls180.v:7397.21-7397.73" + wire $or$ls180.v:7397$2396_Y + attribute \src "ls180.v:7398.21-7398.73" + wire $or$ls180.v:7398$2397_Y + attribute \src "ls180.v:7399.21-7399.73" + wire $or$ls180.v:7399$2398_Y + attribute \src "ls180.v:7400.21-7400.73" + wire $or$ls180.v:7400$2399_Y + attribute \src "ls180.v:7401.21-7401.73" + wire $or$ls180.v:7401$2400_Y + attribute \src "ls180.v:7402.7-7402.93" + wire $or$ls180.v:7402$2401_Y + attribute \src "ls180.v:7413.7-7413.93" + wire $or$ls180.v:7413$2402_Y + attribute \src "ls180.v:7424.7-7424.93" + wire $or$ls180.v:7424$2403_Y + attribute \src "ls180.v:7553.7-7553.107" + wire $or$ls180.v:7553$2439_Y + attribute \src "ls180.v:7599.7-7599.107" + wire $or$ls180.v:7599$2455_Y + attribute \src "ls180.v:7645.7-7645.107" + wire $or$ls180.v:7645$2471_Y + attribute \src "ls180.v:7691.7-7691.107" + wire $or$ls180.v:7691$2487_Y + attribute \src "ls180.v:7879.40-7879.125" + wire $or$ls180.v:7879$2508_Y + attribute \src "ls180.v:7879.39-7879.207" + wire $or$ls180.v:7879$2511_Y + attribute \src "ls180.v:7879.38-7879.289" + wire $or$ls180.v:7879$2514_Y + attribute \src "ls180.v:7879.37-7879.371" + wire $or$ls180.v:7879$2517_Y + attribute \src "ls180.v:7880.41-7880.126" + wire $or$ls180.v:7880$2520_Y + attribute \src "ls180.v:7880.40-7880.208" + wire $or$ls180.v:7880$2523_Y + attribute \src "ls180.v:7880.39-7880.290" + wire $or$ls180.v:7880$2526_Y + attribute \src "ls180.v:7880.38-7880.372" + wire $or$ls180.v:7880$2529_Y + attribute \src "ls180.v:7884.7-7884.49" + wire $or$ls180.v:7884$2530_Y + attribute \src "ls180.v:8047.22-8047.74" + wire $or$ls180.v:8047$2578_Y + attribute \src "ls180.v:8115.32-8115.85" + wire $or$ls180.v:8115$2590_Y + attribute \src "ls180.v:8121.8-8121.97" + wire $or$ls180.v:8121$2592_Y + attribute \src "ls180.v:8138.52-8138.139" + wire $or$ls180.v:8138$2597_Y + attribute \src "ls180.v:8139.51-8139.136" + wire $or$ls180.v:8139$2598_Y + attribute \src "ls180.v:8173.7-8173.87" + wire $or$ls180.v:8173$2601_Y + attribute \src "ls180.v:8196.33-8196.88" + wire $or$ls180.v:8196$2602_Y + attribute \src "ls180.v:8202.8-8202.99" + wire $or$ls180.v:8202$2604_Y + attribute \src "ls180.v:8219.53-8219.142" + wire $or$ls180.v:8219$2609_Y + attribute \src "ls180.v:8220.52-8220.139" + wire $or$ls180.v:8220$2610_Y + attribute \src "ls180.v:8254.7-8254.89" + wire $or$ls180.v:8254$2613_Y + attribute \src "ls180.v:8275.34-8275.91" + wire $or$ls180.v:8275$2614_Y + attribute \src "ls180.v:8281.8-8281.101" + wire $or$ls180.v:8281$2616_Y + attribute \src "ls180.v:8298.54-8298.145" + wire $or$ls180.v:8298$2621_Y + attribute \src "ls180.v:8299.53-8299.142" + wire $or$ls180.v:8299$2622_Y + attribute \src "ls180.v:8315.7-8315.91" + wire $or$ls180.v:8315$2625_Y + attribute \src "ls180.v:8504.8-8504.89" + wire $or$ls180.v:8504$2649_Y + attribute \src "ls180.v:8521.48-8521.127" + wire $or$ls180.v:8521$2654_Y + attribute \src "ls180.v:8522.47-8522.124" + wire $or$ls180.v:8522$2655_Y + attribute \src "ls180.v:8595.21-8595.65" + wire $or$ls180.v:8595$2673_Y + attribute \src "ls180.v:3131.46-3131.94" + wire width 13 $sshl$ls180.v:3131$83_Y + attribute \src "ls180.v:3288.46-3288.94" + wire width 13 $sshl$ls180.v:3288$113_Y + attribute \src "ls180.v:3445.46-3445.94" + wire width 13 $sshl$ls180.v:3445$143_Y + attribute \src "ls180.v:3602.46-3602.94" + wire width 13 $sshl$ls180.v:3602$173_Y + attribute \src "ls180.v:3162.63-3162.122" + wire width 3 $sub$ls180.v:3162$96_Y + attribute \src "ls180.v:3319.63-3319.122" + wire width 3 $sub$ls180.v:3319$126_Y + attribute \src "ls180.v:3476.63-3476.122" + wire width 3 $sub$ls180.v:3476$156_Y + attribute \src "ls180.v:3633.63-3633.122" + wire width 3 $sub$ls180.v:3633$186_Y + attribute \src "ls180.v:4039.38-4039.75" + wire width 31 $sub$ls180.v:4039$540_Y + attribute \src "ls180.v:4125.36-4125.68" + wire width 4 $sub$ls180.v:4125$585_Y + attribute \src "ls180.v:4155.36-4155.68" + wire width 4 $sub$ls180.v:4155$596_Y + attribute \src "ls180.v:4180.69-4180.110" + wire width 16 $sub$ls180.v:4180$602_Y + attribute \src "ls180.v:4181.69-4181.104" + wire width 16 $sub$ls180.v:4181$604_Y + attribute \src "ls180.v:4208.36-4208.66" + wire width 8 $sub$ls180.v:4208$608_Y + attribute \src "ls180.v:4458.60-4458.90" + wire width 32 $sub$ls180.v:4458$652_Y + attribute \src "ls180.v:4469.62-4469.104" + wire width 8 $sub$ls180.v:4469$654_Y + attribute \src "ls180.v:4486.60-4486.90" + wire width 32 $sub$ls180.v:4486$658_Y + attribute \src "ls180.v:4715.62-4715.93" + wire width 32 $sub$ls180.v:4715$688_Y + attribute \src "ls180.v:4720.62-4720.93" + wire width 32 $sub$ls180.v:4720$689_Y + attribute \src "ls180.v:4731.64-4731.122" + wire width 10 $sub$ls180.v:4731$692_Y + attribute \src "ls180.v:4752.62-4752.93" + wire width 32 $sub$ls180.v:4752$695_Y + attribute \src "ls180.v:5214.37-5214.75" + wire width 32 $sub$ls180.v:5214$968_Y + attribute \src "ls180.v:5229.62-5229.100" + wire width 32 $sub$ls180.v:5229$971_Y + attribute \src "ls180.v:5240.39-5240.77" + wire width 32 $sub$ls180.v:5240$976_Y + attribute \src "ls180.v:5315.40-5315.76" + wire width 5 $sub$ls180.v:5315$980_Y + attribute \src "ls180.v:5364.56-5364.104" + wire width 32 $sub$ls180.v:5364$994_Y + attribute \src "ls180.v:5454.71-5454.105" + wire width 32 $sub$ls180.v:5454$1000_Y + attribute \src "ls180.v:5523.40-5523.76" + wire width 5 $sub$ls180.v:5523$1011_Y + attribute \src "ls180.v:5542.61-5542.98" + wire width 16 $sub$ls180.v:5542$1017_Y + attribute \src "ls180.v:5543.61-5543.92" + wire width 16 $sub$ls180.v:5543$1019_Y + attribute \src "ls180.v:5571.32-5571.58" + wire width 8 $sub$ls180.v:5571$1023_Y + attribute \src "ls180.v:7448.31-7448.60" + wire width 32 $sub$ls180.v:7448$2410_Y + attribute \src "ls180.v:7469.31-7469.61" + wire width 10 $sub$ls180.v:7469$2415_Y + attribute \src "ls180.v:7475.34-7475.67" + wire $sub$ls180.v:7475$2416_Y + attribute \src "ls180.v:7486.36-7486.69" + wire $sub$ls180.v:7486$2419_Y + attribute \src "ls180.v:7550.59-7550.116" + wire width 4 $sub$ls180.v:7550$2437_Y + attribute \src "ls180.v:7569.46-7569.90" + wire width 3 $sub$ls180.v:7569$2441_Y + attribute \src "ls180.v:7596.59-7596.116" + wire width 4 $sub$ls180.v:7596$2453_Y + attribute \src "ls180.v:7615.46-7615.90" + wire width 3 $sub$ls180.v:7615$2457_Y + attribute \src "ls180.v:7642.59-7642.116" + wire width 4 $sub$ls180.v:7642$2469_Y + attribute \src "ls180.v:7661.46-7661.90" + wire width 3 $sub$ls180.v:7661$2473_Y + attribute \src "ls180.v:7688.59-7688.116" + wire width 4 $sub$ls180.v:7688$2485_Y + attribute \src "ls180.v:7707.46-7707.90" + wire width 3 $sub$ls180.v:7707$2489_Y + attribute \src "ls180.v:7718.25-7718.48" + wire width 5 $sub$ls180.v:7718$2493_Y + attribute \src "ls180.v:7725.25-7725.48" + wire width 4 $sub$ls180.v:7725$2496_Y + attribute \src "ls180.v:7857.33-7857.64" + wire $sub$ls180.v:7857$2501_Y + attribute \src "ls180.v:7872.33-7872.64" + wire width 3 $sub$ls180.v:7872$2504_Y + attribute \src "ls180.v:7999.33-7999.64" + wire width 5 $sub$ls180.v:7999$2563_Y + attribute \src "ls180.v:8021.33-8021.64" + wire width 5 $sub$ls180.v:8021$2574_Y + attribute \src "ls180.v:8056.33-8056.64" + wire width 3 $sub$ls180.v:8056$2579_Y + attribute \src "ls180.v:8080.30-8080.53" + wire width 32 $sub$ls180.v:8080$2582_Y + attribute \src "ls180.v:8094.30-8094.53" + wire width 32 $sub$ls180.v:8094$2586_Y + attribute \src "ls180.v:8497.36-8497.70" + wire width 6 $sub$ls180.v:8497$2647_Y + attribute \src "ls180.v:8583.36-8583.70" + wire width 6 $sub$ls180.v:8583$2669_Y + attribute \src "ls180.v:8604.29-8604.56" + wire width 3 $sub$ls180.v:8604$2674_Y + attribute \src "ls180.v:8731.22-8731.42" + wire width 20 $sub$ls180.v:8731$2681_Y + attribute \src "ls180.v:4812.353-4812.425" + wire $xor$ls180.v:4812$702_Y + attribute \src "ls180.v:4812.200-4812.272" + wire $xor$ls180.v:4812$703_Y + attribute \src "ls180.v:4812.160-4812.273" + wire $xor$ls180.v:4812$704_Y + attribute \src "ls180.v:4813.353-4813.425" + wire $xor$ls180.v:4813$705_Y + attribute \src "ls180.v:4813.200-4813.272" + wire $xor$ls180.v:4813$706_Y + attribute \src "ls180.v:4813.160-4813.273" + wire $xor$ls180.v:4813$707_Y + attribute \src "ls180.v:4814.353-4814.425" + wire $xor$ls180.v:4814$708_Y + attribute \src "ls180.v:4814.200-4814.272" + wire $xor$ls180.v:4814$709_Y + attribute \src "ls180.v:4814.160-4814.273" + wire $xor$ls180.v:4814$710_Y + attribute \src "ls180.v:4815.353-4815.425" + wire $xor$ls180.v:4815$711_Y + attribute \src "ls180.v:4815.200-4815.272" + wire $xor$ls180.v:4815$712_Y + attribute \src "ls180.v:4815.160-4815.273" + wire $xor$ls180.v:4815$713_Y + attribute \src "ls180.v:4816.353-4816.425" + wire $xor$ls180.v:4816$714_Y + attribute \src "ls180.v:4816.200-4816.272" + wire $xor$ls180.v:4816$715_Y + attribute \src "ls180.v:4816.160-4816.273" + wire $xor$ls180.v:4816$716_Y + attribute \src "ls180.v:4817.353-4817.425" + wire $xor$ls180.v:4817$717_Y + attribute \src "ls180.v:4817.200-4817.272" + wire $xor$ls180.v:4817$718_Y + attribute \src "ls180.v:4817.160-4817.273" + wire $xor$ls180.v:4817$719_Y + attribute \src "ls180.v:4818.353-4818.425" + wire $xor$ls180.v:4818$720_Y + attribute \src "ls180.v:4818.200-4818.272" + wire $xor$ls180.v:4818$721_Y + attribute \src "ls180.v:4818.160-4818.273" + wire $xor$ls180.v:4818$722_Y + attribute \src "ls180.v:4819.353-4819.425" + wire $xor$ls180.v:4819$723_Y + attribute \src "ls180.v:4819.200-4819.272" + wire $xor$ls180.v:4819$724_Y + attribute \src "ls180.v:4819.160-4819.273" + wire $xor$ls180.v:4819$725_Y + attribute \src "ls180.v:4820.353-4820.425" + wire $xor$ls180.v:4820$726_Y + attribute \src "ls180.v:4820.200-4820.272" + wire $xor$ls180.v:4820$727_Y + attribute \src "ls180.v:4820.160-4820.273" + wire $xor$ls180.v:4820$728_Y + attribute \src "ls180.v:4821.354-4821.426" + wire $xor$ls180.v:4821$729_Y + attribute \src "ls180.v:4821.201-4821.273" + wire $xor$ls180.v:4821$730_Y + attribute \src "ls180.v:4821.161-4821.274" + wire $xor$ls180.v:4821$731_Y + attribute \src "ls180.v:4822.361-4822.434" + wire $xor$ls180.v:4822$732_Y + attribute \src "ls180.v:4822.205-4822.278" + wire $xor$ls180.v:4822$733_Y + attribute \src "ls180.v:4822.164-4822.279" + wire $xor$ls180.v:4822$734_Y + attribute \src "ls180.v:4823.361-4823.434" + wire $xor$ls180.v:4823$735_Y + attribute \src "ls180.v:4823.205-4823.278" + wire $xor$ls180.v:4823$736_Y + attribute \src "ls180.v:4823.164-4823.279" + wire $xor$ls180.v:4823$737_Y + attribute \src "ls180.v:4824.361-4824.434" + wire $xor$ls180.v:4824$738_Y + attribute \src "ls180.v:4824.205-4824.278" + wire $xor$ls180.v:4824$739_Y + attribute \src "ls180.v:4824.164-4824.279" + wire $xor$ls180.v:4824$740_Y + attribute \src "ls180.v:4825.361-4825.434" + wire $xor$ls180.v:4825$741_Y + attribute \src "ls180.v:4825.205-4825.278" + wire $xor$ls180.v:4825$742_Y + attribute \src "ls180.v:4825.164-4825.279" + wire $xor$ls180.v:4825$743_Y + attribute \src "ls180.v:4826.361-4826.434" + wire $xor$ls180.v:4826$744_Y + attribute \src "ls180.v:4826.205-4826.278" + wire $xor$ls180.v:4826$745_Y + attribute \src "ls180.v:4826.164-4826.279" + wire $xor$ls180.v:4826$746_Y + attribute \src "ls180.v:4827.361-4827.434" + wire $xor$ls180.v:4827$747_Y + attribute \src "ls180.v:4827.205-4827.278" + wire $xor$ls180.v:4827$748_Y + attribute \src "ls180.v:4827.164-4827.279" + wire $xor$ls180.v:4827$749_Y + attribute \src "ls180.v:4828.361-4828.434" + wire $xor$ls180.v:4828$750_Y + attribute \src "ls180.v:4828.205-4828.278" + wire $xor$ls180.v:4828$751_Y + attribute \src "ls180.v:4828.164-4828.279" + wire $xor$ls180.v:4828$752_Y + attribute \src "ls180.v:4829.361-4829.434" + wire $xor$ls180.v:4829$753_Y + attribute \src "ls180.v:4829.205-4829.278" + wire $xor$ls180.v:4829$754_Y + attribute \src "ls180.v:4829.164-4829.279" + wire $xor$ls180.v:4829$755_Y + attribute \src "ls180.v:4830.361-4830.434" + wire $xor$ls180.v:4830$756_Y + attribute \src "ls180.v:4830.205-4830.278" + wire $xor$ls180.v:4830$757_Y + attribute \src "ls180.v:4830.164-4830.279" + wire $xor$ls180.v:4830$758_Y + attribute \src "ls180.v:4831.361-4831.434" + wire $xor$ls180.v:4831$759_Y + attribute \src "ls180.v:4831.205-4831.278" + wire $xor$ls180.v:4831$760_Y + attribute \src "ls180.v:4831.164-4831.279" + wire $xor$ls180.v:4831$761_Y + attribute \src "ls180.v:4832.361-4832.434" + wire $xor$ls180.v:4832$762_Y + attribute \src "ls180.v:4832.205-4832.278" + wire $xor$ls180.v:4832$763_Y + attribute \src "ls180.v:4832.164-4832.279" + wire $xor$ls180.v:4832$764_Y + attribute \src "ls180.v:4833.361-4833.434" + wire $xor$ls180.v:4833$765_Y + attribute \src "ls180.v:4833.205-4833.278" + wire $xor$ls180.v:4833$766_Y + attribute \src "ls180.v:4833.164-4833.279" + wire $xor$ls180.v:4833$767_Y + attribute \src "ls180.v:4834.361-4834.434" + wire $xor$ls180.v:4834$768_Y + attribute \src "ls180.v:4834.205-4834.278" + wire $xor$ls180.v:4834$769_Y + attribute \src "ls180.v:4834.164-4834.279" + wire $xor$ls180.v:4834$770_Y + attribute \src "ls180.v:4835.361-4835.434" + wire $xor$ls180.v:4835$771_Y + attribute \src "ls180.v:4835.205-4835.278" + wire $xor$ls180.v:4835$772_Y + attribute \src "ls180.v:4835.164-4835.279" + wire $xor$ls180.v:4835$773_Y + attribute \src "ls180.v:4836.361-4836.434" + wire $xor$ls180.v:4836$774_Y + attribute \src "ls180.v:4836.205-4836.278" + wire $xor$ls180.v:4836$775_Y + attribute \src "ls180.v:4836.164-4836.279" + wire $xor$ls180.v:4836$776_Y + attribute \src "ls180.v:4837.361-4837.434" + wire $xor$ls180.v:4837$777_Y + attribute \src "ls180.v:4837.205-4837.278" + wire $xor$ls180.v:4837$778_Y + attribute \src "ls180.v:4837.164-4837.279" + wire $xor$ls180.v:4837$779_Y + attribute \src "ls180.v:4838.361-4838.434" + wire $xor$ls180.v:4838$780_Y + attribute \src "ls180.v:4838.205-4838.278" + wire $xor$ls180.v:4838$781_Y + attribute \src "ls180.v:4838.164-4838.279" + wire $xor$ls180.v:4838$782_Y + attribute \src "ls180.v:4839.361-4839.434" + wire $xor$ls180.v:4839$783_Y + attribute \src "ls180.v:4839.205-4839.278" + wire $xor$ls180.v:4839$784_Y + attribute \src "ls180.v:4839.164-4839.279" + wire $xor$ls180.v:4839$785_Y + attribute \src "ls180.v:4840.361-4840.434" + wire $xor$ls180.v:4840$786_Y + attribute \src "ls180.v:4840.205-4840.278" + wire $xor$ls180.v:4840$787_Y + attribute \src "ls180.v:4840.164-4840.279" + wire $xor$ls180.v:4840$788_Y + attribute \src "ls180.v:4841.361-4841.434" + wire $xor$ls180.v:4841$789_Y + attribute \src "ls180.v:4841.205-4841.278" + wire $xor$ls180.v:4841$790_Y + attribute \src "ls180.v:4841.164-4841.279" + wire $xor$ls180.v:4841$791_Y + attribute \src "ls180.v:4842.360-4842.432" + wire $xor$ls180.v:4842$792_Y + attribute \src "ls180.v:4842.205-4842.277" + wire $xor$ls180.v:4842$793_Y + attribute \src "ls180.v:4842.164-4842.278" + wire $xor$ls180.v:4842$794_Y + attribute \src "ls180.v:4843.360-4843.432" + wire $xor$ls180.v:4843$795_Y + attribute \src "ls180.v:4843.205-4843.277" + wire $xor$ls180.v:4843$796_Y + attribute \src "ls180.v:4843.164-4843.278" + wire $xor$ls180.v:4843$797_Y + attribute \src "ls180.v:4844.360-4844.432" + wire $xor$ls180.v:4844$798_Y + attribute \src "ls180.v:4844.205-4844.277" + wire $xor$ls180.v:4844$799_Y + attribute \src "ls180.v:4844.164-4844.278" + wire $xor$ls180.v:4844$800_Y + attribute \src "ls180.v:4845.360-4845.432" + wire $xor$ls180.v:4845$801_Y + attribute \src "ls180.v:4845.205-4845.277" + wire $xor$ls180.v:4845$802_Y + attribute \src "ls180.v:4845.164-4845.278" + wire $xor$ls180.v:4845$803_Y + attribute \src "ls180.v:4846.360-4846.432" + wire $xor$ls180.v:4846$804_Y + attribute \src "ls180.v:4846.205-4846.277" + wire $xor$ls180.v:4846$805_Y + attribute \src "ls180.v:4846.164-4846.278" + wire $xor$ls180.v:4846$806_Y + attribute \src "ls180.v:4847.360-4847.432" + wire $xor$ls180.v:4847$807_Y + attribute \src "ls180.v:4847.205-4847.277" + wire $xor$ls180.v:4847$808_Y + attribute \src "ls180.v:4847.164-4847.278" + wire $xor$ls180.v:4847$809_Y + attribute \src "ls180.v:4848.360-4848.432" + wire $xor$ls180.v:4848$810_Y + attribute \src "ls180.v:4848.205-4848.277" + wire $xor$ls180.v:4848$811_Y + attribute \src "ls180.v:4848.164-4848.278" + wire $xor$ls180.v:4848$812_Y + attribute \src "ls180.v:4849.360-4849.432" + wire $xor$ls180.v:4849$813_Y + attribute \src "ls180.v:4849.205-4849.277" + wire $xor$ls180.v:4849$814_Y + attribute \src "ls180.v:4849.164-4849.278" + wire $xor$ls180.v:4849$815_Y + attribute \src "ls180.v:4850.360-4850.432" + wire $xor$ls180.v:4850$816_Y + attribute \src "ls180.v:4850.205-4850.277" + wire $xor$ls180.v:4850$817_Y + attribute \src "ls180.v:4850.164-4850.278" + wire $xor$ls180.v:4850$818_Y + attribute \src "ls180.v:4851.360-4851.432" + wire $xor$ls180.v:4851$819_Y + attribute \src "ls180.v:4851.205-4851.277" + wire $xor$ls180.v:4851$820_Y + attribute \src "ls180.v:4851.164-4851.278" + wire $xor$ls180.v:4851$821_Y + attribute \src "ls180.v:4872.899-4872.983" + wire $xor$ls180.v:4872$835_Y + attribute \src "ls180.v:4872.634-4872.718" + wire $xor$ls180.v:4872$836_Y + attribute \src "ls180.v:4872.588-4872.719" + wire $xor$ls180.v:4872$837_Y + attribute \src "ls180.v:4872.234-4872.318" + wire $xor$ls180.v:4872$838_Y + attribute \src "ls180.v:4872.187-4872.319" + wire $xor$ls180.v:4872$839_Y + attribute \src "ls180.v:4873.899-4873.983" + wire $xor$ls180.v:4873$840_Y + attribute \src "ls180.v:4873.634-4873.718" + wire $xor$ls180.v:4873$841_Y + attribute \src "ls180.v:4873.588-4873.719" + wire $xor$ls180.v:4873$842_Y + attribute \src "ls180.v:4873.234-4873.318" + wire $xor$ls180.v:4873$843_Y + attribute \src "ls180.v:4873.187-4873.319" + wire $xor$ls180.v:4873$844_Y + attribute \src "ls180.v:4882.899-4882.983" + wire $xor$ls180.v:4882$846_Y + attribute \src "ls180.v:4882.634-4882.718" + wire $xor$ls180.v:4882$847_Y + attribute \src "ls180.v:4882.588-4882.719" + wire $xor$ls180.v:4882$848_Y + attribute \src "ls180.v:4882.234-4882.318" + wire $xor$ls180.v:4882$849_Y + attribute \src "ls180.v:4882.187-4882.319" + wire $xor$ls180.v:4882$850_Y + attribute \src "ls180.v:4883.899-4883.983" + wire $xor$ls180.v:4883$851_Y + attribute \src "ls180.v:4883.634-4883.718" + wire $xor$ls180.v:4883$852_Y + attribute \src "ls180.v:4883.588-4883.719" + wire $xor$ls180.v:4883$853_Y + attribute \src "ls180.v:4883.234-4883.318" + wire $xor$ls180.v:4883$854_Y + attribute \src "ls180.v:4883.187-4883.319" + wire $xor$ls180.v:4883$855_Y + attribute \src "ls180.v:4892.899-4892.983" + wire $xor$ls180.v:4892$857_Y + attribute \src "ls180.v:4892.634-4892.718" + wire $xor$ls180.v:4892$858_Y + attribute \src "ls180.v:4892.588-4892.719" + wire $xor$ls180.v:4892$859_Y + attribute \src "ls180.v:4892.234-4892.318" + wire $xor$ls180.v:4892$860_Y + attribute \src "ls180.v:4892.187-4892.319" + wire $xor$ls180.v:4892$861_Y + attribute \src "ls180.v:4893.899-4893.983" + wire $xor$ls180.v:4893$862_Y + attribute \src "ls180.v:4893.634-4893.718" + wire $xor$ls180.v:4893$863_Y + attribute \src "ls180.v:4893.588-4893.719" + wire $xor$ls180.v:4893$864_Y + attribute \src "ls180.v:4893.234-4893.318" + wire $xor$ls180.v:4893$865_Y + attribute \src "ls180.v:4893.187-4893.319" + wire $xor$ls180.v:4893$866_Y + attribute \src "ls180.v:4902.899-4902.983" + wire $xor$ls180.v:4902$868_Y + attribute \src "ls180.v:4902.634-4902.718" + wire $xor$ls180.v:4902$869_Y + attribute \src "ls180.v:4902.588-4902.719" + wire $xor$ls180.v:4902$870_Y + attribute \src "ls180.v:4902.234-4902.318" + wire $xor$ls180.v:4902$871_Y + attribute \src "ls180.v:4902.187-4902.319" + wire $xor$ls180.v:4902$872_Y + attribute \src "ls180.v:4903.899-4903.983" + wire $xor$ls180.v:4903$873_Y + attribute \src "ls180.v:4903.634-4903.718" + wire $xor$ls180.v:4903$874_Y + attribute \src "ls180.v:4903.588-4903.719" + wire $xor$ls180.v:4903$875_Y + attribute \src "ls180.v:4903.234-4903.318" + wire $xor$ls180.v:4903$876_Y + attribute \src "ls180.v:4903.187-4903.319" + wire $xor$ls180.v:4903$877_Y + attribute \src "ls180.v:5054.879-5054.961" + wire $xor$ls180.v:5054$910_Y + attribute \src "ls180.v:5054.620-5054.702" + wire $xor$ls180.v:5054$911_Y + attribute \src "ls180.v:5054.575-5054.703" + wire $xor$ls180.v:5054$912_Y + attribute \src "ls180.v:5054.229-5054.311" + wire $xor$ls180.v:5054$913_Y + attribute \src "ls180.v:5054.183-5054.312" + wire $xor$ls180.v:5054$914_Y + attribute \src "ls180.v:5055.879-5055.961" + wire $xor$ls180.v:5055$915_Y + attribute \src "ls180.v:5055.620-5055.702" + wire $xor$ls180.v:5055$916_Y + attribute \src "ls180.v:5055.575-5055.703" + wire $xor$ls180.v:5055$917_Y + attribute \src "ls180.v:5055.229-5055.311" + wire $xor$ls180.v:5055$918_Y + attribute \src "ls180.v:5055.183-5055.312" + wire $xor$ls180.v:5055$919_Y + attribute \src "ls180.v:5064.879-5064.961" + wire $xor$ls180.v:5064$921_Y + attribute \src "ls180.v:5064.620-5064.702" + wire $xor$ls180.v:5064$922_Y + attribute \src "ls180.v:5064.575-5064.703" + wire $xor$ls180.v:5064$923_Y + attribute \src "ls180.v:5064.229-5064.311" + wire $xor$ls180.v:5064$924_Y + attribute \src "ls180.v:5064.183-5064.312" + wire $xor$ls180.v:5064$925_Y + attribute \src "ls180.v:5065.879-5065.961" + wire $xor$ls180.v:5065$926_Y + attribute \src "ls180.v:5065.620-5065.702" + wire $xor$ls180.v:5065$927_Y + attribute \src "ls180.v:5065.575-5065.703" + wire $xor$ls180.v:5065$928_Y + attribute \src "ls180.v:5065.229-5065.311" + wire $xor$ls180.v:5065$929_Y + attribute \src "ls180.v:5065.183-5065.312" + wire $xor$ls180.v:5065$930_Y + attribute \src "ls180.v:5074.879-5074.961" + wire $xor$ls180.v:5074$932_Y + attribute \src "ls180.v:5074.620-5074.702" + wire $xor$ls180.v:5074$933_Y + attribute \src "ls180.v:5074.575-5074.703" + wire $xor$ls180.v:5074$934_Y + attribute \src "ls180.v:5074.229-5074.311" + wire $xor$ls180.v:5074$935_Y + attribute \src "ls180.v:5074.183-5074.312" + wire $xor$ls180.v:5074$936_Y + attribute \src "ls180.v:5075.879-5075.961" + wire $xor$ls180.v:5075$937_Y + attribute \src "ls180.v:5075.620-5075.702" + wire $xor$ls180.v:5075$938_Y + attribute \src "ls180.v:5075.575-5075.703" + wire $xor$ls180.v:5075$939_Y + attribute \src "ls180.v:5075.229-5075.311" + wire $xor$ls180.v:5075$940_Y + attribute \src "ls180.v:5075.183-5075.312" + wire $xor$ls180.v:5075$941_Y + attribute \src "ls180.v:5084.879-5084.961" + wire $xor$ls180.v:5084$943_Y + attribute \src "ls180.v:5084.620-5084.702" + wire $xor$ls180.v:5084$944_Y + attribute \src "ls180.v:5084.575-5084.703" + wire $xor$ls180.v:5084$945_Y + attribute \src "ls180.v:5084.229-5084.311" + wire $xor$ls180.v:5084$946_Y + attribute \src "ls180.v:5084.183-5084.312" + wire $xor$ls180.v:5084$947_Y + attribute \src "ls180.v:5085.879-5085.961" + wire $xor$ls180.v:5085$948_Y + attribute \src "ls180.v:5085.620-5085.702" + wire $xor$ls180.v:5085$949_Y + attribute \src "ls180.v:5085.575-5085.703" + wire $xor$ls180.v:5085$950_Y + attribute \src "ls180.v:5085.229-5085.311" + wire $xor$ls180.v:5085$951_Y + attribute \src "ls180.v:5085.183-5085.312" + wire $xor$ls180.v:5085$952_Y + attribute \src "ls180.v:1709.11-1709.42" + wire width 3 \builder_bankmachine0_next_state + attribute \src "ls180.v:1708.11-1708.37" + wire width 3 \builder_bankmachine0_state + attribute \src "ls180.v:1711.11-1711.42" + wire width 3 \builder_bankmachine1_next_state + attribute \src "ls180.v:1710.11-1710.37" + wire width 3 \builder_bankmachine1_state + attribute \src "ls180.v:1713.11-1713.42" + wire width 3 \builder_bankmachine2_next_state + attribute \src "ls180.v:1712.11-1712.37" + wire width 3 \builder_bankmachine2_state + attribute \src "ls180.v:1715.11-1715.42" + wire width 3 \builder_bankmachine3_next_state + attribute \src "ls180.v:1714.11-1714.37" + wire width 3 \builder_bankmachine3_state + attribute \src "ls180.v:2547.5-2547.34" + wire \builder_comb_rhs_array_muxed0 + attribute \src "ls180.v:2548.12-2548.41" + wire width 13 \builder_comb_rhs_array_muxed1 + attribute \src "ls180.v:2560.5-2560.35" + wire \builder_comb_rhs_array_muxed10 + attribute \src "ls180.v:2561.5-2561.35" + wire \builder_comb_rhs_array_muxed11 + attribute \src "ls180.v:2565.12-2565.42" + wire width 22 \builder_comb_rhs_array_muxed12 + attribute \src "ls180.v:2566.5-2566.35" + wire \builder_comb_rhs_array_muxed13 + attribute \src "ls180.v:2567.5-2567.35" + wire \builder_comb_rhs_array_muxed14 + attribute \src "ls180.v:2568.12-2568.42" + wire width 22 \builder_comb_rhs_array_muxed15 + attribute \src "ls180.v:2569.5-2569.35" + wire \builder_comb_rhs_array_muxed16 + attribute \src "ls180.v:2570.5-2570.35" + wire \builder_comb_rhs_array_muxed17 + attribute \src "ls180.v:2571.12-2571.42" + wire width 22 \builder_comb_rhs_array_muxed18 + attribute \src "ls180.v:2572.5-2572.35" + wire \builder_comb_rhs_array_muxed19 + attribute \src "ls180.v:2549.11-2549.40" + wire width 2 \builder_comb_rhs_array_muxed2 + attribute \src "ls180.v:2573.5-2573.35" + wire \builder_comb_rhs_array_muxed20 + attribute \src "ls180.v:2574.12-2574.42" + wire width 22 \builder_comb_rhs_array_muxed21 + attribute \src "ls180.v:2575.5-2575.35" + wire \builder_comb_rhs_array_muxed22 + attribute \src "ls180.v:2576.5-2576.35" + wire \builder_comb_rhs_array_muxed23 + attribute \src "ls180.v:2577.12-2577.42" + wire width 32 \builder_comb_rhs_array_muxed24 + attribute \src "ls180.v:2578.12-2578.42" + wire width 32 \builder_comb_rhs_array_muxed25 + attribute \src "ls180.v:2579.11-2579.41" + wire width 4 \builder_comb_rhs_array_muxed26 + attribute \src "ls180.v:2580.5-2580.35" + wire \builder_comb_rhs_array_muxed27 + attribute \src "ls180.v:2581.5-2581.35" + wire \builder_comb_rhs_array_muxed28 + attribute \src "ls180.v:2582.5-2582.35" + wire \builder_comb_rhs_array_muxed29 + attribute \src "ls180.v:2550.5-2550.34" + wire \builder_comb_rhs_array_muxed3 + attribute \src "ls180.v:2583.11-2583.41" + wire width 3 \builder_comb_rhs_array_muxed30 + attribute \src "ls180.v:2584.11-2584.41" + wire width 2 \builder_comb_rhs_array_muxed31 + attribute \src "ls180.v:2551.5-2551.34" + wire \builder_comb_rhs_array_muxed4 + attribute \src "ls180.v:2552.5-2552.34" + wire \builder_comb_rhs_array_muxed5 + attribute \src "ls180.v:2556.5-2556.34" + wire \builder_comb_rhs_array_muxed6 + attribute \src "ls180.v:2557.12-2557.41" + wire width 13 \builder_comb_rhs_array_muxed7 + attribute \src "ls180.v:2558.11-2558.40" + wire width 2 \builder_comb_rhs_array_muxed8 + attribute \src "ls180.v:2559.5-2559.34" + wire \builder_comb_rhs_array_muxed9 + attribute \src "ls180.v:2553.5-2553.32" + wire \builder_comb_t_array_muxed0 + attribute \src "ls180.v:2554.5-2554.32" + wire \builder_comb_t_array_muxed1 + attribute \src "ls180.v:2555.5-2555.32" + wire \builder_comb_t_array_muxed2 + attribute \src "ls180.v:2562.5-2562.32" + wire \builder_comb_t_array_muxed3 + attribute \src "ls180.v:2563.5-2563.32" + wire \builder_comb_t_array_muxed4 + attribute \src "ls180.v:2564.5-2564.32" + wire \builder_comb_t_array_muxed5 + attribute \src "ls180.v:1695.5-1695.34" + wire \builder_converter0_next_state + attribute \src "ls180.v:1694.5-1694.29" + wire \builder_converter0_state + attribute \src "ls180.v:1699.5-1699.34" + wire \builder_converter1_next_state + attribute \src "ls180.v:1698.5-1698.29" + wire \builder_converter1_state + attribute \src "ls180.v:1703.5-1703.34" + wire \builder_converter2_next_state + attribute \src "ls180.v:1702.5-1702.29" + wire \builder_converter2_state + attribute \src "ls180.v:1740.5-1740.33" + wire \builder_converter_next_state + attribute \src "ls180.v:1739.5-1739.28" + wire \builder_converter_state + attribute \src "ls180.v:1860.12-1860.25" + wire width 20 \builder_count + attribute \src "ls180.v:2535.13-2535.41" + wire width 14 \builder_csr_interconnect_adr + attribute \src "ls180.v:2538.12-2538.42" + wire width 8 \builder_csr_interconnect_dat_r + attribute \src "ls180.v:2537.12-2537.42" + wire width 8 \builder_csr_interconnect_dat_w + attribute \src "ls180.v:2536.6-2536.33" + wire \builder_csr_interconnect_we + attribute \src "ls180.v:1898.12-1898.42" + wire width 8 \builder_csrbank0_bus_errors0_r + attribute \src "ls180.v:1897.6-1897.37" + wire \builder_csrbank0_bus_errors0_re + attribute \src "ls180.v:1900.12-1900.42" + wire width 8 \builder_csrbank0_bus_errors0_w + attribute \src "ls180.v:1899.6-1899.37" + wire \builder_csrbank0_bus_errors0_we + attribute \src "ls180.v:1894.12-1894.42" + wire width 8 \builder_csrbank0_bus_errors1_r + attribute \src "ls180.v:1893.6-1893.37" + wire \builder_csrbank0_bus_errors1_re + attribute \src "ls180.v:1896.12-1896.42" + wire width 8 \builder_csrbank0_bus_errors1_w + attribute \src "ls180.v:1895.6-1895.37" + wire \builder_csrbank0_bus_errors1_we + attribute \src "ls180.v:1890.12-1890.42" + wire width 8 \builder_csrbank0_bus_errors2_r + attribute \src "ls180.v:1889.6-1889.37" + wire \builder_csrbank0_bus_errors2_re + attribute \src "ls180.v:1892.12-1892.42" + wire width 8 \builder_csrbank0_bus_errors2_w + attribute \src "ls180.v:1891.6-1891.37" + wire \builder_csrbank0_bus_errors2_we + attribute \src "ls180.v:1886.12-1886.42" + wire width 8 \builder_csrbank0_bus_errors3_r + attribute \src "ls180.v:1885.6-1885.37" + wire \builder_csrbank0_bus_errors3_re + attribute \src "ls180.v:1888.12-1888.42" + wire width 8 \builder_csrbank0_bus_errors3_w + attribute \src "ls180.v:1887.6-1887.37" + wire \builder_csrbank0_bus_errors3_we + attribute \src "ls180.v:1866.6-1866.31" + wire \builder_csrbank0_reset0_r + attribute \src "ls180.v:1865.6-1865.32" + wire \builder_csrbank0_reset0_re + attribute \src "ls180.v:1868.6-1868.31" + wire \builder_csrbank0_reset0_w + attribute \src "ls180.v:1867.6-1867.32" + wire \builder_csrbank0_reset0_we + attribute \src "ls180.v:1882.12-1882.39" + wire width 8 \builder_csrbank0_scratch0_r + attribute \src "ls180.v:1881.6-1881.34" + wire \builder_csrbank0_scratch0_re + attribute \src "ls180.v:1884.12-1884.39" + wire width 8 \builder_csrbank0_scratch0_w + attribute \src "ls180.v:1883.6-1883.34" + wire \builder_csrbank0_scratch0_we + attribute \src "ls180.v:1878.12-1878.39" + wire width 8 \builder_csrbank0_scratch1_r + attribute \src "ls180.v:1877.6-1877.34" + wire \builder_csrbank0_scratch1_re + attribute \src "ls180.v:1880.12-1880.39" + wire width 8 \builder_csrbank0_scratch1_w + attribute \src "ls180.v:1879.6-1879.34" + wire \builder_csrbank0_scratch1_we + attribute \src "ls180.v:1874.12-1874.39" + wire width 8 \builder_csrbank0_scratch2_r + attribute \src "ls180.v:1873.6-1873.34" + wire \builder_csrbank0_scratch2_re + attribute \src "ls180.v:1876.12-1876.39" + wire width 8 \builder_csrbank0_scratch2_w + attribute \src "ls180.v:1875.6-1875.34" + wire \builder_csrbank0_scratch2_we + attribute \src "ls180.v:1870.12-1870.39" + wire width 8 \builder_csrbank0_scratch3_r + attribute \src "ls180.v:1869.6-1869.34" + wire \builder_csrbank0_scratch3_re + attribute \src "ls180.v:1872.12-1872.39" + wire width 8 \builder_csrbank0_scratch3_w + attribute \src "ls180.v:1871.6-1871.34" + wire \builder_csrbank0_scratch3_we + attribute \src "ls180.v:1901.6-1901.26" + wire \builder_csrbank0_sel + attribute \src "ls180.v:2420.12-2420.44" + wire width 8 \builder_csrbank10_clk_divider0_r + attribute \src "ls180.v:2419.6-2419.39" + wire \builder_csrbank10_clk_divider0_re + attribute \src "ls180.v:2422.12-2422.44" + wire width 8 \builder_csrbank10_clk_divider0_w + attribute \src "ls180.v:2421.6-2421.39" + wire \builder_csrbank10_clk_divider0_we + attribute \src "ls180.v:2416.12-2416.44" + wire width 8 \builder_csrbank10_clk_divider1_r + attribute \src "ls180.v:2415.6-2415.39" + wire \builder_csrbank10_clk_divider1_re + attribute \src "ls180.v:2418.12-2418.44" + wire width 8 \builder_csrbank10_clk_divider1_w + attribute \src "ls180.v:2417.6-2417.39" + wire \builder_csrbank10_clk_divider1_we + attribute \src "ls180.v:2392.12-2392.40" + wire width 8 \builder_csrbank10_control0_r + attribute \src "ls180.v:2391.6-2391.35" + wire \builder_csrbank10_control0_re + attribute \src "ls180.v:2394.12-2394.40" + wire width 8 \builder_csrbank10_control0_w + attribute \src "ls180.v:2393.6-2393.35" + wire \builder_csrbank10_control0_we + attribute \src "ls180.v:2388.12-2388.40" + wire width 8 \builder_csrbank10_control1_r + attribute \src "ls180.v:2387.6-2387.35" + wire \builder_csrbank10_control1_re + attribute \src "ls180.v:2390.12-2390.40" + wire width 8 \builder_csrbank10_control1_w + attribute \src "ls180.v:2389.6-2389.35" + wire \builder_csrbank10_control1_we + attribute \src "ls180.v:2408.6-2408.29" + wire \builder_csrbank10_cs0_r + attribute \src "ls180.v:2407.6-2407.30" + wire \builder_csrbank10_cs0_re + attribute \src "ls180.v:2410.6-2410.29" + wire \builder_csrbank10_cs0_w + attribute \src "ls180.v:2409.6-2409.30" + wire \builder_csrbank10_cs0_we + attribute \src "ls180.v:2412.6-2412.35" + wire \builder_csrbank10_loopback0_r + attribute \src "ls180.v:2411.6-2411.36" + wire \builder_csrbank10_loopback0_re + attribute \src "ls180.v:2414.6-2414.35" + wire \builder_csrbank10_loopback0_w + attribute \src "ls180.v:2413.6-2413.36" + wire \builder_csrbank10_loopback0_we + attribute \src "ls180.v:2404.12-2404.36" + wire width 8 \builder_csrbank10_miso_r + attribute \src "ls180.v:2403.6-2403.31" + wire \builder_csrbank10_miso_re + attribute \src "ls180.v:2406.12-2406.36" + wire width 8 \builder_csrbank10_miso_w + attribute \src "ls180.v:2405.6-2405.31" + wire \builder_csrbank10_miso_we + attribute \src "ls180.v:2400.12-2400.37" + wire width 8 \builder_csrbank10_mosi0_r + attribute \src "ls180.v:2399.6-2399.32" + wire \builder_csrbank10_mosi0_re + attribute \src "ls180.v:2402.12-2402.37" + wire width 8 \builder_csrbank10_mosi0_w + attribute \src "ls180.v:2401.6-2401.32" + wire \builder_csrbank10_mosi0_we + attribute \src "ls180.v:2423.6-2423.27" + wire \builder_csrbank10_sel + attribute \src "ls180.v:2396.6-2396.32" + wire \builder_csrbank10_status_r + attribute \src "ls180.v:2395.6-2395.33" + wire \builder_csrbank10_status_re + attribute \src "ls180.v:2398.6-2398.32" + wire \builder_csrbank10_status_w + attribute \src "ls180.v:2397.6-2397.33" + wire \builder_csrbank10_status_we + attribute \src "ls180.v:2461.6-2461.29" + wire \builder_csrbank11_en0_r + attribute \src "ls180.v:2460.6-2460.30" + wire \builder_csrbank11_en0_re + attribute \src "ls180.v:2463.6-2463.29" + wire \builder_csrbank11_en0_w + attribute \src "ls180.v:2462.6-2462.30" + wire \builder_csrbank11_en0_we + attribute \src "ls180.v:2485.6-2485.36" + wire \builder_csrbank11_ev_enable0_r + attribute \src "ls180.v:2484.6-2484.37" + wire \builder_csrbank11_ev_enable0_re + attribute \src "ls180.v:2487.6-2487.36" + wire \builder_csrbank11_ev_enable0_w + attribute \src "ls180.v:2486.6-2486.37" + wire \builder_csrbank11_ev_enable0_we + attribute \src "ls180.v:2441.12-2441.37" + wire width 8 \builder_csrbank11_load0_r + attribute \src "ls180.v:2440.6-2440.32" + wire \builder_csrbank11_load0_re + attribute \src "ls180.v:2443.12-2443.37" + wire width 8 \builder_csrbank11_load0_w + attribute \src "ls180.v:2442.6-2442.32" + wire \builder_csrbank11_load0_we + attribute \src "ls180.v:2437.12-2437.37" + wire width 8 \builder_csrbank11_load1_r + attribute \src "ls180.v:2436.6-2436.32" + wire \builder_csrbank11_load1_re + attribute \src "ls180.v:2439.12-2439.37" + wire width 8 \builder_csrbank11_load1_w + attribute \src "ls180.v:2438.6-2438.32" + wire \builder_csrbank11_load1_we + attribute \src "ls180.v:2433.12-2433.37" + wire width 8 \builder_csrbank11_load2_r + attribute \src "ls180.v:2432.6-2432.32" + wire \builder_csrbank11_load2_re + attribute \src "ls180.v:2435.12-2435.37" + wire width 8 \builder_csrbank11_load2_w + attribute \src "ls180.v:2434.6-2434.32" + wire \builder_csrbank11_load2_we + attribute \src "ls180.v:2429.12-2429.37" + wire width 8 \builder_csrbank11_load3_r + attribute \src "ls180.v:2428.6-2428.32" + wire \builder_csrbank11_load3_re + attribute \src "ls180.v:2431.12-2431.37" + wire width 8 \builder_csrbank11_load3_w + attribute \src "ls180.v:2430.6-2430.32" + wire \builder_csrbank11_load3_we + attribute \src "ls180.v:2457.12-2457.39" + wire width 8 \builder_csrbank11_reload0_r + attribute \src "ls180.v:2456.6-2456.34" + wire \builder_csrbank11_reload0_re + attribute \src "ls180.v:2459.12-2459.39" + wire width 8 \builder_csrbank11_reload0_w + attribute \src "ls180.v:2458.6-2458.34" + wire \builder_csrbank11_reload0_we + attribute \src "ls180.v:2453.12-2453.39" + wire width 8 \builder_csrbank11_reload1_r + attribute \src "ls180.v:2452.6-2452.34" + wire \builder_csrbank11_reload1_re + attribute \src "ls180.v:2455.12-2455.39" + wire width 8 \builder_csrbank11_reload1_w + attribute \src "ls180.v:2454.6-2454.34" + wire \builder_csrbank11_reload1_we + attribute \src "ls180.v:2449.12-2449.39" + wire width 8 \builder_csrbank11_reload2_r + attribute \src "ls180.v:2448.6-2448.34" + wire \builder_csrbank11_reload2_re + attribute \src "ls180.v:2451.12-2451.39" + wire width 8 \builder_csrbank11_reload2_w + attribute \src "ls180.v:2450.6-2450.34" + wire \builder_csrbank11_reload2_we + attribute \src "ls180.v:2445.12-2445.39" + wire width 8 \builder_csrbank11_reload3_r + attribute \src "ls180.v:2444.6-2444.34" + wire \builder_csrbank11_reload3_re + attribute \src "ls180.v:2447.12-2447.39" + wire width 8 \builder_csrbank11_reload3_w + attribute \src "ls180.v:2446.6-2446.34" + wire \builder_csrbank11_reload3_we + attribute \src "ls180.v:2488.6-2488.27" + wire \builder_csrbank11_sel + attribute \src "ls180.v:2465.6-2465.39" + wire \builder_csrbank11_update_value0_r + attribute \src "ls180.v:2464.6-2464.40" + wire \builder_csrbank11_update_value0_re + attribute \src "ls180.v:2467.6-2467.39" + wire \builder_csrbank11_update_value0_w + attribute \src "ls180.v:2466.6-2466.40" + wire \builder_csrbank11_update_value0_we + attribute \src "ls180.v:2481.12-2481.38" + wire width 8 \builder_csrbank11_value0_r + attribute \src "ls180.v:2480.6-2480.33" + wire \builder_csrbank11_value0_re + attribute \src "ls180.v:2483.12-2483.38" + wire width 8 \builder_csrbank11_value0_w + attribute \src "ls180.v:2482.6-2482.33" + wire \builder_csrbank11_value0_we + attribute \src "ls180.v:2477.12-2477.38" + wire width 8 \builder_csrbank11_value1_r + attribute \src "ls180.v:2476.6-2476.33" + wire \builder_csrbank11_value1_re + attribute \src "ls180.v:2479.12-2479.38" + wire width 8 \builder_csrbank11_value1_w + attribute \src "ls180.v:2478.6-2478.33" + wire \builder_csrbank11_value1_we + attribute \src "ls180.v:2473.12-2473.38" + wire width 8 \builder_csrbank11_value2_r + attribute \src "ls180.v:2472.6-2472.33" + wire \builder_csrbank11_value2_re + attribute \src "ls180.v:2475.12-2475.38" + wire width 8 \builder_csrbank11_value2_w + attribute \src "ls180.v:2474.6-2474.33" + wire \builder_csrbank11_value2_we + attribute \src "ls180.v:2469.12-2469.38" + wire width 8 \builder_csrbank11_value3_r + attribute \src "ls180.v:2468.6-2468.33" + wire \builder_csrbank11_value3_re + attribute \src "ls180.v:2471.12-2471.38" + wire width 8 \builder_csrbank11_value3_w + attribute \src "ls180.v:2470.6-2470.33" + wire \builder_csrbank11_value3_we + attribute \src "ls180.v:2502.12-2502.42" + wire width 2 \builder_csrbank12_ev_enable0_r + attribute \src "ls180.v:2501.6-2501.37" + wire \builder_csrbank12_ev_enable0_re + attribute \src "ls180.v:2504.12-2504.42" + wire width 2 \builder_csrbank12_ev_enable0_w + attribute \src "ls180.v:2503.6-2503.37" + wire \builder_csrbank12_ev_enable0_we + attribute \src "ls180.v:2498.6-2498.33" + wire \builder_csrbank12_rxempty_r + attribute \src "ls180.v:2497.6-2497.34" + wire \builder_csrbank12_rxempty_re + attribute \src "ls180.v:2500.6-2500.33" + wire \builder_csrbank12_rxempty_w + attribute \src "ls180.v:2499.6-2499.34" + wire \builder_csrbank12_rxempty_we + attribute \src "ls180.v:2510.6-2510.32" + wire \builder_csrbank12_rxfull_r + attribute \src "ls180.v:2509.6-2509.33" + wire \builder_csrbank12_rxfull_re + attribute \src "ls180.v:2512.6-2512.32" + wire \builder_csrbank12_rxfull_w + attribute \src "ls180.v:2511.6-2511.33" + wire \builder_csrbank12_rxfull_we + attribute \src "ls180.v:2513.6-2513.27" + wire \builder_csrbank12_sel + attribute \src "ls180.v:2506.6-2506.33" + wire \builder_csrbank12_txempty_r + attribute \src "ls180.v:2505.6-2505.34" + wire \builder_csrbank12_txempty_re + attribute \src "ls180.v:2508.6-2508.33" + wire \builder_csrbank12_txempty_w + attribute \src "ls180.v:2507.6-2507.34" + wire \builder_csrbank12_txempty_we + attribute \src "ls180.v:2494.6-2494.32" + wire \builder_csrbank12_txfull_r + attribute \src "ls180.v:2493.6-2493.33" + wire \builder_csrbank12_txfull_re + attribute \src "ls180.v:2496.6-2496.32" + wire \builder_csrbank12_txfull_w + attribute \src "ls180.v:2495.6-2495.33" + wire \builder_csrbank12_txfull_we + attribute \src "ls180.v:2534.6-2534.27" + wire \builder_csrbank13_sel + attribute \src "ls180.v:2531.12-2531.44" + wire width 8 \builder_csrbank13_tuning_word0_r + attribute \src "ls180.v:2530.6-2530.39" + wire \builder_csrbank13_tuning_word0_re + attribute \src "ls180.v:2533.12-2533.44" + wire width 8 \builder_csrbank13_tuning_word0_w + attribute \src "ls180.v:2532.6-2532.39" + wire \builder_csrbank13_tuning_word0_we + attribute \src "ls180.v:2527.12-2527.44" + wire width 8 \builder_csrbank13_tuning_word1_r + attribute \src "ls180.v:2526.6-2526.39" + wire \builder_csrbank13_tuning_word1_re + attribute \src "ls180.v:2529.12-2529.44" + wire width 8 \builder_csrbank13_tuning_word1_w + attribute \src "ls180.v:2528.6-2528.39" + wire \builder_csrbank13_tuning_word1_we + attribute \src "ls180.v:2523.12-2523.44" + wire width 8 \builder_csrbank13_tuning_word2_r + attribute \src "ls180.v:2522.6-2522.39" + wire \builder_csrbank13_tuning_word2_re + attribute \src "ls180.v:2525.12-2525.44" + wire width 8 \builder_csrbank13_tuning_word2_w + attribute \src "ls180.v:2524.6-2524.39" + wire \builder_csrbank13_tuning_word2_we + attribute \src "ls180.v:2519.12-2519.44" + wire width 8 \builder_csrbank13_tuning_word3_r + attribute \src "ls180.v:2518.6-2518.39" + wire \builder_csrbank13_tuning_word3_re + attribute \src "ls180.v:2521.12-2521.44" + wire width 8 \builder_csrbank13_tuning_word3_w + attribute \src "ls180.v:2520.6-2520.39" + wire \builder_csrbank13_tuning_word3_we + attribute \src "ls180.v:1919.12-1919.34" + wire width 8 \builder_csrbank1_in0_r + attribute \src "ls180.v:1918.6-1918.29" + wire \builder_csrbank1_in0_re + attribute \src "ls180.v:1921.12-1921.34" + wire width 8 \builder_csrbank1_in0_w + attribute \src "ls180.v:1920.6-1920.29" + wire \builder_csrbank1_in0_we + attribute \src "ls180.v:1915.12-1915.34" + wire width 8 \builder_csrbank1_in1_r + attribute \src "ls180.v:1914.6-1914.29" + wire \builder_csrbank1_in1_re + attribute \src "ls180.v:1917.12-1917.34" + wire width 8 \builder_csrbank1_in1_w + attribute \src "ls180.v:1916.6-1916.29" + wire \builder_csrbank1_in1_we + attribute \src "ls180.v:1911.12-1911.34" + wire width 8 \builder_csrbank1_oe0_r + attribute \src "ls180.v:1910.6-1910.29" + wire \builder_csrbank1_oe0_re + attribute \src "ls180.v:1913.12-1913.34" + wire width 8 \builder_csrbank1_oe0_w + attribute \src "ls180.v:1912.6-1912.29" + wire \builder_csrbank1_oe0_we + attribute \src "ls180.v:1907.12-1907.34" + wire width 8 \builder_csrbank1_oe1_r + attribute \src "ls180.v:1906.6-1906.29" + wire \builder_csrbank1_oe1_re + attribute \src "ls180.v:1909.12-1909.34" + wire width 8 \builder_csrbank1_oe1_w + attribute \src "ls180.v:1908.6-1908.29" + wire \builder_csrbank1_oe1_we + attribute \src "ls180.v:1927.12-1927.35" + wire width 8 \builder_csrbank1_out0_r + attribute \src "ls180.v:1926.6-1926.30" + wire \builder_csrbank1_out0_re + attribute \src "ls180.v:1929.12-1929.35" + wire width 8 \builder_csrbank1_out0_w + attribute \src "ls180.v:1928.6-1928.30" + wire \builder_csrbank1_out0_we + attribute \src "ls180.v:1923.12-1923.35" + wire width 8 \builder_csrbank1_out1_r + attribute \src "ls180.v:1922.6-1922.30" + wire \builder_csrbank1_out1_re + attribute \src "ls180.v:1925.12-1925.35" + wire width 8 \builder_csrbank1_out1_w + attribute \src "ls180.v:1924.6-1924.30" + wire \builder_csrbank1_out1_we + attribute \src "ls180.v:1930.6-1930.26" + wire \builder_csrbank1_sel + attribute \src "ls180.v:1936.6-1936.32" + wire \builder_csrbank2_enable0_r + attribute \src "ls180.v:1935.6-1935.33" + wire \builder_csrbank2_enable0_re + attribute \src "ls180.v:1938.6-1938.32" + wire \builder_csrbank2_enable0_w + attribute \src "ls180.v:1937.6-1937.33" + wire \builder_csrbank2_enable0_we + attribute \src "ls180.v:1968.12-1968.38" + wire width 8 \builder_csrbank2_period0_r + attribute \src "ls180.v:1967.6-1967.33" + wire \builder_csrbank2_period0_re + attribute \src "ls180.v:1970.12-1970.38" + wire width 8 \builder_csrbank2_period0_w + attribute \src "ls180.v:1969.6-1969.33" + wire \builder_csrbank2_period0_we + attribute \src "ls180.v:1964.12-1964.38" + wire width 8 \builder_csrbank2_period1_r + attribute \src "ls180.v:1963.6-1963.33" + wire \builder_csrbank2_period1_re + attribute \src "ls180.v:1966.12-1966.38" + wire width 8 \builder_csrbank2_period1_w + attribute \src "ls180.v:1965.6-1965.33" + wire \builder_csrbank2_period1_we + attribute \src "ls180.v:1960.12-1960.38" + wire width 8 \builder_csrbank2_period2_r + attribute \src "ls180.v:1959.6-1959.33" + wire \builder_csrbank2_period2_re + attribute \src "ls180.v:1962.12-1962.38" + wire width 8 \builder_csrbank2_period2_w + attribute \src "ls180.v:1961.6-1961.33" + wire \builder_csrbank2_period2_we + attribute \src "ls180.v:1956.12-1956.38" + wire width 8 \builder_csrbank2_period3_r + attribute \src "ls180.v:1955.6-1955.33" + wire \builder_csrbank2_period3_re + attribute \src "ls180.v:1958.12-1958.38" + wire width 8 \builder_csrbank2_period3_w + attribute \src "ls180.v:1957.6-1957.33" + wire \builder_csrbank2_period3_we + attribute \src "ls180.v:1971.6-1971.26" + wire \builder_csrbank2_sel + attribute \src "ls180.v:1952.12-1952.37" + wire width 8 \builder_csrbank2_width0_r + attribute \src "ls180.v:1951.6-1951.32" + wire \builder_csrbank2_width0_re + attribute \src "ls180.v:1954.12-1954.37" + wire width 8 \builder_csrbank2_width0_w + attribute \src "ls180.v:1953.6-1953.32" + wire \builder_csrbank2_width0_we + attribute \src "ls180.v:1948.12-1948.37" + wire width 8 \builder_csrbank2_width1_r + attribute \src "ls180.v:1947.6-1947.32" + wire \builder_csrbank2_width1_re + attribute \src "ls180.v:1950.12-1950.37" + wire width 8 \builder_csrbank2_width1_w + attribute \src "ls180.v:1949.6-1949.32" + wire \builder_csrbank2_width1_we + attribute \src "ls180.v:1944.12-1944.37" + wire width 8 \builder_csrbank2_width2_r + attribute \src "ls180.v:1943.6-1943.32" + wire \builder_csrbank2_width2_re + attribute \src "ls180.v:1946.12-1946.37" + wire width 8 \builder_csrbank2_width2_w + attribute \src "ls180.v:1945.6-1945.32" + wire \builder_csrbank2_width2_we + attribute \src "ls180.v:1940.12-1940.37" + wire width 8 \builder_csrbank2_width3_r + attribute \src "ls180.v:1939.6-1939.32" + wire \builder_csrbank2_width3_re + attribute \src "ls180.v:1942.12-1942.37" + wire width 8 \builder_csrbank2_width3_w + attribute \src "ls180.v:1941.6-1941.32" + wire \builder_csrbank2_width3_we + attribute \src "ls180.v:1977.6-1977.32" + wire \builder_csrbank3_enable0_r + attribute \src "ls180.v:1976.6-1976.33" + wire \builder_csrbank3_enable0_re + attribute \src "ls180.v:1979.6-1979.32" + wire \builder_csrbank3_enable0_w + attribute \src "ls180.v:1978.6-1978.33" + wire \builder_csrbank3_enable0_we + attribute \src "ls180.v:2009.12-2009.38" + wire width 8 \builder_csrbank3_period0_r + attribute \src "ls180.v:2008.6-2008.33" + wire \builder_csrbank3_period0_re + attribute \src "ls180.v:2011.12-2011.38" + wire width 8 \builder_csrbank3_period0_w + attribute \src "ls180.v:2010.6-2010.33" + wire \builder_csrbank3_period0_we + attribute \src "ls180.v:2005.12-2005.38" + wire width 8 \builder_csrbank3_period1_r + attribute \src "ls180.v:2004.6-2004.33" + wire \builder_csrbank3_period1_re + attribute \src "ls180.v:2007.12-2007.38" + wire width 8 \builder_csrbank3_period1_w + attribute \src "ls180.v:2006.6-2006.33" + wire \builder_csrbank3_period1_we + attribute \src "ls180.v:2001.12-2001.38" + wire width 8 \builder_csrbank3_period2_r + attribute \src "ls180.v:2000.6-2000.33" + wire \builder_csrbank3_period2_re + attribute \src "ls180.v:2003.12-2003.38" + wire width 8 \builder_csrbank3_period2_w + attribute \src "ls180.v:2002.6-2002.33" + wire \builder_csrbank3_period2_we + attribute \src "ls180.v:1997.12-1997.38" + wire width 8 \builder_csrbank3_period3_r + attribute \src "ls180.v:1996.6-1996.33" + wire \builder_csrbank3_period3_re + attribute \src "ls180.v:1999.12-1999.38" + wire width 8 \builder_csrbank3_period3_w + attribute \src "ls180.v:1998.6-1998.33" + wire \builder_csrbank3_period3_we + attribute \src "ls180.v:2012.6-2012.26" + wire \builder_csrbank3_sel + attribute \src "ls180.v:1993.12-1993.37" + wire width 8 \builder_csrbank3_width0_r + attribute \src "ls180.v:1992.6-1992.32" + wire \builder_csrbank3_width0_re + attribute \src "ls180.v:1995.12-1995.37" + wire width 8 \builder_csrbank3_width0_w + attribute \src "ls180.v:1994.6-1994.32" + wire \builder_csrbank3_width0_we + attribute \src "ls180.v:1989.12-1989.37" + wire width 8 \builder_csrbank3_width1_r + attribute \src "ls180.v:1988.6-1988.32" + wire \builder_csrbank3_width1_re + attribute \src "ls180.v:1991.12-1991.37" + wire width 8 \builder_csrbank3_width1_w + attribute \src "ls180.v:1990.6-1990.32" + wire \builder_csrbank3_width1_we + attribute \src "ls180.v:1985.12-1985.37" + wire width 8 \builder_csrbank3_width2_r + attribute \src "ls180.v:1984.6-1984.32" + wire \builder_csrbank3_width2_re + attribute \src "ls180.v:1987.12-1987.37" + wire width 8 \builder_csrbank3_width2_w + attribute \src "ls180.v:1986.6-1986.32" + wire \builder_csrbank3_width2_we + attribute \src "ls180.v:1981.12-1981.37" + wire width 8 \builder_csrbank3_width3_r + attribute \src "ls180.v:1980.6-1980.32" + wire \builder_csrbank3_width3_re + attribute \src "ls180.v:1983.12-1983.37" + wire width 8 \builder_csrbank3_width3_w + attribute \src "ls180.v:1982.6-1982.32" + wire \builder_csrbank3_width3_we + attribute \src "ls180.v:2046.12-2046.40" + wire width 8 \builder_csrbank4_dma_base0_r + attribute \src "ls180.v:2045.6-2045.35" + wire \builder_csrbank4_dma_base0_re + attribute \src "ls180.v:2048.12-2048.40" + wire width 8 \builder_csrbank4_dma_base0_w + attribute \src "ls180.v:2047.6-2047.35" + wire \builder_csrbank4_dma_base0_we + attribute \src "ls180.v:2042.12-2042.40" + wire width 8 \builder_csrbank4_dma_base1_r + attribute \src "ls180.v:2041.6-2041.35" + wire \builder_csrbank4_dma_base1_re + attribute \src "ls180.v:2044.12-2044.40" + wire width 8 \builder_csrbank4_dma_base1_w + attribute \src "ls180.v:2043.6-2043.35" + wire \builder_csrbank4_dma_base1_we + attribute \src "ls180.v:2038.12-2038.40" + wire width 8 \builder_csrbank4_dma_base2_r + attribute \src "ls180.v:2037.6-2037.35" + wire \builder_csrbank4_dma_base2_re + attribute \src "ls180.v:2040.12-2040.40" + wire width 8 \builder_csrbank4_dma_base2_w + attribute \src "ls180.v:2039.6-2039.35" + wire \builder_csrbank4_dma_base2_we + attribute \src "ls180.v:2034.12-2034.40" + wire width 8 \builder_csrbank4_dma_base3_r + attribute \src "ls180.v:2033.6-2033.35" + wire \builder_csrbank4_dma_base3_re + attribute \src "ls180.v:2036.12-2036.40" + wire width 8 \builder_csrbank4_dma_base3_w + attribute \src "ls180.v:2035.6-2035.35" + wire \builder_csrbank4_dma_base3_we + attribute \src "ls180.v:2030.12-2030.40" + wire width 8 \builder_csrbank4_dma_base4_r + attribute \src "ls180.v:2029.6-2029.35" + wire \builder_csrbank4_dma_base4_re + attribute \src "ls180.v:2032.12-2032.40" + wire width 8 \builder_csrbank4_dma_base4_w + attribute \src "ls180.v:2031.6-2031.35" + wire \builder_csrbank4_dma_base4_we + attribute \src "ls180.v:2026.12-2026.40" + wire width 8 \builder_csrbank4_dma_base5_r + attribute \src "ls180.v:2025.6-2025.35" + wire \builder_csrbank4_dma_base5_re + attribute \src "ls180.v:2028.12-2028.40" + wire width 8 \builder_csrbank4_dma_base5_w + attribute \src "ls180.v:2027.6-2027.35" + wire \builder_csrbank4_dma_base5_we + attribute \src "ls180.v:2022.12-2022.40" + wire width 8 \builder_csrbank4_dma_base6_r + attribute \src "ls180.v:2021.6-2021.35" + wire \builder_csrbank4_dma_base6_re + attribute \src "ls180.v:2024.12-2024.40" + wire width 8 \builder_csrbank4_dma_base6_w + attribute \src "ls180.v:2023.6-2023.35" + wire \builder_csrbank4_dma_base6_we + attribute \src "ls180.v:2018.12-2018.40" + wire width 8 \builder_csrbank4_dma_base7_r + attribute \src "ls180.v:2017.6-2017.35" + wire \builder_csrbank4_dma_base7_re + attribute \src "ls180.v:2020.12-2020.40" + wire width 8 \builder_csrbank4_dma_base7_w + attribute \src "ls180.v:2019.6-2019.35" + wire \builder_csrbank4_dma_base7_we + attribute \src "ls180.v:2070.6-2070.33" + wire \builder_csrbank4_dma_done_r + attribute \src "ls180.v:2069.6-2069.34" + wire \builder_csrbank4_dma_done_re + attribute \src "ls180.v:2072.6-2072.33" + wire \builder_csrbank4_dma_done_w + attribute \src "ls180.v:2071.6-2071.34" + wire \builder_csrbank4_dma_done_we + attribute \src "ls180.v:2066.6-2066.36" + wire \builder_csrbank4_dma_enable0_r + attribute \src "ls180.v:2065.6-2065.37" + wire \builder_csrbank4_dma_enable0_re + attribute \src "ls180.v:2068.6-2068.36" + wire \builder_csrbank4_dma_enable0_w + attribute \src "ls180.v:2067.6-2067.37" + wire \builder_csrbank4_dma_enable0_we + attribute \src "ls180.v:2062.12-2062.42" + wire width 8 \builder_csrbank4_dma_length0_r + attribute \src "ls180.v:2061.6-2061.37" + wire \builder_csrbank4_dma_length0_re + attribute \src "ls180.v:2064.12-2064.42" + wire width 8 \builder_csrbank4_dma_length0_w + attribute \src "ls180.v:2063.6-2063.37" + wire \builder_csrbank4_dma_length0_we + attribute \src "ls180.v:2058.12-2058.42" + wire width 8 \builder_csrbank4_dma_length1_r + attribute \src "ls180.v:2057.6-2057.37" + wire \builder_csrbank4_dma_length1_re + attribute \src "ls180.v:2060.12-2060.42" + wire width 8 \builder_csrbank4_dma_length1_w + attribute \src "ls180.v:2059.6-2059.37" + wire \builder_csrbank4_dma_length1_we + attribute \src "ls180.v:2054.12-2054.42" + wire width 8 \builder_csrbank4_dma_length2_r + attribute \src "ls180.v:2053.6-2053.37" + wire \builder_csrbank4_dma_length2_re + attribute \src "ls180.v:2056.12-2056.42" + wire width 8 \builder_csrbank4_dma_length2_w + attribute \src "ls180.v:2055.6-2055.37" + wire \builder_csrbank4_dma_length2_we + attribute \src "ls180.v:2050.12-2050.42" + wire width 8 \builder_csrbank4_dma_length3_r + attribute \src "ls180.v:2049.6-2049.37" + wire \builder_csrbank4_dma_length3_re + attribute \src "ls180.v:2052.12-2052.42" + wire width 8 \builder_csrbank4_dma_length3_w + attribute \src "ls180.v:2051.6-2051.37" + wire \builder_csrbank4_dma_length3_we + attribute \src "ls180.v:2074.6-2074.34" + wire \builder_csrbank4_dma_loop0_r + attribute \src "ls180.v:2073.6-2073.35" + wire \builder_csrbank4_dma_loop0_re + attribute \src "ls180.v:2076.6-2076.34" + wire \builder_csrbank4_dma_loop0_w + attribute \src "ls180.v:2075.6-2075.35" + wire \builder_csrbank4_dma_loop0_we + attribute \src "ls180.v:2077.6-2077.26" + wire \builder_csrbank4_sel + attribute \src "ls180.v:2207.12-2207.43" + wire width 8 \builder_csrbank5_block_count0_r + attribute \src "ls180.v:2206.6-2206.38" + wire \builder_csrbank5_block_count0_re + attribute \src "ls180.v:2209.12-2209.43" + wire width 8 \builder_csrbank5_block_count0_w + attribute \src "ls180.v:2208.6-2208.38" + wire \builder_csrbank5_block_count0_we + attribute \src "ls180.v:2203.12-2203.43" + wire width 8 \builder_csrbank5_block_count1_r + attribute \src "ls180.v:2202.6-2202.38" + wire \builder_csrbank5_block_count1_re + attribute \src "ls180.v:2205.12-2205.43" + wire width 8 \builder_csrbank5_block_count1_w + attribute \src "ls180.v:2204.6-2204.38" + wire \builder_csrbank5_block_count1_we + attribute \src "ls180.v:2199.12-2199.43" + wire width 8 \builder_csrbank5_block_count2_r + attribute \src "ls180.v:2198.6-2198.38" + wire \builder_csrbank5_block_count2_re + attribute \src "ls180.v:2201.12-2201.43" + wire width 8 \builder_csrbank5_block_count2_w + attribute \src "ls180.v:2200.6-2200.38" + wire \builder_csrbank5_block_count2_we + attribute \src "ls180.v:2195.12-2195.43" + wire width 8 \builder_csrbank5_block_count3_r + attribute \src "ls180.v:2194.6-2194.38" + wire \builder_csrbank5_block_count3_re + attribute \src "ls180.v:2197.12-2197.43" + wire width 8 \builder_csrbank5_block_count3_w + attribute \src "ls180.v:2196.6-2196.38" + wire \builder_csrbank5_block_count3_we + attribute \src "ls180.v:2191.12-2191.44" + wire width 8 \builder_csrbank5_block_length0_r + attribute \src "ls180.v:2190.6-2190.39" + wire \builder_csrbank5_block_length0_re + attribute \src "ls180.v:2193.12-2193.44" + wire width 8 \builder_csrbank5_block_length0_w + attribute \src "ls180.v:2192.6-2192.39" + wire \builder_csrbank5_block_length0_we + attribute \src "ls180.v:2187.12-2187.44" + wire width 2 \builder_csrbank5_block_length1_r + attribute \src "ls180.v:2186.6-2186.39" + wire \builder_csrbank5_block_length1_re + attribute \src "ls180.v:2189.12-2189.44" + wire width 2 \builder_csrbank5_block_length1_w + attribute \src "ls180.v:2188.6-2188.39" + wire \builder_csrbank5_block_length1_we + attribute \src "ls180.v:2095.12-2095.44" + wire width 8 \builder_csrbank5_cmd_argument0_r + attribute \src "ls180.v:2094.6-2094.39" + wire \builder_csrbank5_cmd_argument0_re + attribute \src "ls180.v:2097.12-2097.44" + wire width 8 \builder_csrbank5_cmd_argument0_w + attribute \src "ls180.v:2096.6-2096.39" + wire \builder_csrbank5_cmd_argument0_we + attribute \src "ls180.v:2091.12-2091.44" + wire width 8 \builder_csrbank5_cmd_argument1_r + attribute \src "ls180.v:2090.6-2090.39" + wire \builder_csrbank5_cmd_argument1_re + attribute \src "ls180.v:2093.12-2093.44" + wire width 8 \builder_csrbank5_cmd_argument1_w + attribute \src "ls180.v:2092.6-2092.39" + wire \builder_csrbank5_cmd_argument1_we + attribute \src "ls180.v:2087.12-2087.44" + wire width 8 \builder_csrbank5_cmd_argument2_r + attribute \src "ls180.v:2086.6-2086.39" + wire \builder_csrbank5_cmd_argument2_re + attribute \src "ls180.v:2089.12-2089.44" + wire width 8 \builder_csrbank5_cmd_argument2_w + attribute \src "ls180.v:2088.6-2088.39" + wire \builder_csrbank5_cmd_argument2_we + attribute \src "ls180.v:2083.12-2083.44" + wire width 8 \builder_csrbank5_cmd_argument3_r + attribute \src "ls180.v:2082.6-2082.39" + wire \builder_csrbank5_cmd_argument3_re + attribute \src "ls180.v:2085.12-2085.44" + wire width 8 \builder_csrbank5_cmd_argument3_w + attribute \src "ls180.v:2084.6-2084.39" + wire \builder_csrbank5_cmd_argument3_we + attribute \src "ls180.v:2111.12-2111.43" + wire width 8 \builder_csrbank5_cmd_command0_r + attribute \src "ls180.v:2110.6-2110.38" + wire \builder_csrbank5_cmd_command0_re + attribute \src "ls180.v:2113.12-2113.43" + wire width 8 \builder_csrbank5_cmd_command0_w + attribute \src "ls180.v:2112.6-2112.38" + wire \builder_csrbank5_cmd_command0_we + attribute \src "ls180.v:2107.12-2107.43" + wire width 8 \builder_csrbank5_cmd_command1_r + attribute \src "ls180.v:2106.6-2106.38" + wire \builder_csrbank5_cmd_command1_re + attribute \src "ls180.v:2109.12-2109.43" + wire width 8 \builder_csrbank5_cmd_command1_w + attribute \src "ls180.v:2108.6-2108.38" + wire \builder_csrbank5_cmd_command1_we + attribute \src "ls180.v:2103.12-2103.43" + wire width 8 \builder_csrbank5_cmd_command2_r + attribute \src "ls180.v:2102.6-2102.38" + wire \builder_csrbank5_cmd_command2_re + attribute \src "ls180.v:2105.12-2105.43" + wire width 8 \builder_csrbank5_cmd_command2_w + attribute \src "ls180.v:2104.6-2104.38" + wire \builder_csrbank5_cmd_command2_we + attribute \src "ls180.v:2099.12-2099.43" + wire width 8 \builder_csrbank5_cmd_command3_r + attribute \src "ls180.v:2098.6-2098.38" + wire \builder_csrbank5_cmd_command3_re + attribute \src "ls180.v:2101.12-2101.43" + wire width 8 \builder_csrbank5_cmd_command3_w + attribute \src "ls180.v:2100.6-2100.38" + wire \builder_csrbank5_cmd_command3_we + attribute \src "ls180.v:2179.12-2179.40" + wire width 4 \builder_csrbank5_cmd_event_r + attribute \src "ls180.v:2178.6-2178.35" + wire \builder_csrbank5_cmd_event_re + attribute \src "ls180.v:2181.12-2181.40" + wire width 4 \builder_csrbank5_cmd_event_w + attribute \src "ls180.v:2180.6-2180.35" + wire \builder_csrbank5_cmd_event_we + attribute \src "ls180.v:2175.12-2175.44" + wire width 8 \builder_csrbank5_cmd_response0_r + attribute \src "ls180.v:2174.6-2174.39" + wire \builder_csrbank5_cmd_response0_re + attribute \src "ls180.v:2177.12-2177.44" + wire width 8 \builder_csrbank5_cmd_response0_w + attribute \src "ls180.v:2176.6-2176.39" + wire \builder_csrbank5_cmd_response0_we + attribute \src "ls180.v:2135.12-2135.45" + wire width 8 \builder_csrbank5_cmd_response10_r + attribute \src "ls180.v:2134.6-2134.40" + wire \builder_csrbank5_cmd_response10_re + attribute \src "ls180.v:2137.12-2137.45" + wire width 8 \builder_csrbank5_cmd_response10_w + attribute \src "ls180.v:2136.6-2136.40" + wire \builder_csrbank5_cmd_response10_we + attribute \src "ls180.v:2131.12-2131.45" + wire width 8 \builder_csrbank5_cmd_response11_r + attribute \src "ls180.v:2130.6-2130.40" + wire \builder_csrbank5_cmd_response11_re + attribute \src "ls180.v:2133.12-2133.45" + wire width 8 \builder_csrbank5_cmd_response11_w + attribute \src "ls180.v:2132.6-2132.40" + wire \builder_csrbank5_cmd_response11_we + attribute \src "ls180.v:2127.12-2127.45" + wire width 8 \builder_csrbank5_cmd_response12_r + attribute \src "ls180.v:2126.6-2126.40" + wire \builder_csrbank5_cmd_response12_re + attribute \src "ls180.v:2129.12-2129.45" + wire width 8 \builder_csrbank5_cmd_response12_w + attribute \src "ls180.v:2128.6-2128.40" + wire \builder_csrbank5_cmd_response12_we + attribute \src "ls180.v:2123.12-2123.45" + wire width 8 \builder_csrbank5_cmd_response13_r + attribute \src "ls180.v:2122.6-2122.40" + wire \builder_csrbank5_cmd_response13_re + attribute \src "ls180.v:2125.12-2125.45" + wire width 8 \builder_csrbank5_cmd_response13_w + attribute \src "ls180.v:2124.6-2124.40" + wire \builder_csrbank5_cmd_response13_we + attribute \src "ls180.v:2119.12-2119.45" + wire width 8 \builder_csrbank5_cmd_response14_r + attribute \src "ls180.v:2118.6-2118.40" + wire \builder_csrbank5_cmd_response14_re + attribute \src "ls180.v:2121.12-2121.45" + wire width 8 \builder_csrbank5_cmd_response14_w + attribute \src "ls180.v:2120.6-2120.40" + wire \builder_csrbank5_cmd_response14_we + attribute \src "ls180.v:2115.12-2115.45" + wire width 8 \builder_csrbank5_cmd_response15_r + attribute \src "ls180.v:2114.6-2114.40" + wire \builder_csrbank5_cmd_response15_re + attribute \src "ls180.v:2117.12-2117.45" + wire width 8 \builder_csrbank5_cmd_response15_w + attribute \src "ls180.v:2116.6-2116.40" + wire \builder_csrbank5_cmd_response15_we + attribute \src "ls180.v:2171.12-2171.44" + wire width 8 \builder_csrbank5_cmd_response1_r + attribute \src "ls180.v:2170.6-2170.39" + wire \builder_csrbank5_cmd_response1_re + attribute \src "ls180.v:2173.12-2173.44" + wire width 8 \builder_csrbank5_cmd_response1_w + attribute \src "ls180.v:2172.6-2172.39" + wire \builder_csrbank5_cmd_response1_we + attribute \src "ls180.v:2167.12-2167.44" + wire width 8 \builder_csrbank5_cmd_response2_r + attribute \src "ls180.v:2166.6-2166.39" + wire \builder_csrbank5_cmd_response2_re + attribute \src "ls180.v:2169.12-2169.44" + wire width 8 \builder_csrbank5_cmd_response2_w + attribute \src "ls180.v:2168.6-2168.39" + wire \builder_csrbank5_cmd_response2_we + attribute \src "ls180.v:2163.12-2163.44" + wire width 8 \builder_csrbank5_cmd_response3_r + attribute \src "ls180.v:2162.6-2162.39" + wire \builder_csrbank5_cmd_response3_re + attribute \src "ls180.v:2165.12-2165.44" + wire width 8 \builder_csrbank5_cmd_response3_w + attribute \src "ls180.v:2164.6-2164.39" + wire \builder_csrbank5_cmd_response3_we + attribute \src "ls180.v:2159.12-2159.44" + wire width 8 \builder_csrbank5_cmd_response4_r + attribute \src "ls180.v:2158.6-2158.39" + wire \builder_csrbank5_cmd_response4_re + attribute \src "ls180.v:2161.12-2161.44" + wire width 8 \builder_csrbank5_cmd_response4_w + attribute \src "ls180.v:2160.6-2160.39" + wire \builder_csrbank5_cmd_response4_we + attribute \src "ls180.v:2155.12-2155.44" + wire width 8 \builder_csrbank5_cmd_response5_r + attribute \src "ls180.v:2154.6-2154.39" + wire \builder_csrbank5_cmd_response5_re + attribute \src "ls180.v:2157.12-2157.44" + wire width 8 \builder_csrbank5_cmd_response5_w + attribute \src "ls180.v:2156.6-2156.39" + wire \builder_csrbank5_cmd_response5_we + attribute \src "ls180.v:2151.12-2151.44" + wire width 8 \builder_csrbank5_cmd_response6_r + attribute \src "ls180.v:2150.6-2150.39" + wire \builder_csrbank5_cmd_response6_re + attribute \src "ls180.v:2153.12-2153.44" + wire width 8 \builder_csrbank5_cmd_response6_w + attribute \src "ls180.v:2152.6-2152.39" + wire \builder_csrbank5_cmd_response6_we + attribute \src "ls180.v:2147.12-2147.44" + wire width 8 \builder_csrbank5_cmd_response7_r + attribute \src "ls180.v:2146.6-2146.39" + wire \builder_csrbank5_cmd_response7_re + attribute \src "ls180.v:2149.12-2149.44" + wire width 8 \builder_csrbank5_cmd_response7_w + attribute \src "ls180.v:2148.6-2148.39" + wire \builder_csrbank5_cmd_response7_we + attribute \src "ls180.v:2143.12-2143.44" + wire width 8 \builder_csrbank5_cmd_response8_r + attribute \src "ls180.v:2142.6-2142.39" + wire \builder_csrbank5_cmd_response8_re + attribute \src "ls180.v:2145.12-2145.44" + wire width 8 \builder_csrbank5_cmd_response8_w + attribute \src "ls180.v:2144.6-2144.39" + wire \builder_csrbank5_cmd_response8_we + attribute \src "ls180.v:2139.12-2139.44" + wire width 8 \builder_csrbank5_cmd_response9_r + attribute \src "ls180.v:2138.6-2138.39" + wire \builder_csrbank5_cmd_response9_re + attribute \src "ls180.v:2141.12-2141.44" + wire width 8 \builder_csrbank5_cmd_response9_w + attribute \src "ls180.v:2140.6-2140.39" + wire \builder_csrbank5_cmd_response9_we + attribute \src "ls180.v:2183.12-2183.41" + wire width 4 \builder_csrbank5_data_event_r + attribute \src "ls180.v:2182.6-2182.36" + wire \builder_csrbank5_data_event_re + attribute \src "ls180.v:2185.12-2185.41" + wire width 4 \builder_csrbank5_data_event_w + attribute \src "ls180.v:2184.6-2184.36" + wire \builder_csrbank5_data_event_we + attribute \src "ls180.v:2210.6-2210.26" + wire \builder_csrbank5_sel + attribute \src "ls180.v:2244.12-2244.40" + wire width 8 \builder_csrbank6_dma_base0_r + attribute \src "ls180.v:2243.6-2243.35" + wire \builder_csrbank6_dma_base0_re + attribute \src "ls180.v:2246.12-2246.40" + wire width 8 \builder_csrbank6_dma_base0_w + attribute \src "ls180.v:2245.6-2245.35" + wire \builder_csrbank6_dma_base0_we + attribute \src "ls180.v:2240.12-2240.40" + wire width 8 \builder_csrbank6_dma_base1_r + attribute \src "ls180.v:2239.6-2239.35" + wire \builder_csrbank6_dma_base1_re + attribute \src "ls180.v:2242.12-2242.40" + wire width 8 \builder_csrbank6_dma_base1_w + attribute \src "ls180.v:2241.6-2241.35" + wire \builder_csrbank6_dma_base1_we + attribute \src "ls180.v:2236.12-2236.40" + wire width 8 \builder_csrbank6_dma_base2_r + attribute \src "ls180.v:2235.6-2235.35" + wire \builder_csrbank6_dma_base2_re + attribute \src "ls180.v:2238.12-2238.40" + wire width 8 \builder_csrbank6_dma_base2_w + attribute \src "ls180.v:2237.6-2237.35" + wire \builder_csrbank6_dma_base2_we + attribute \src "ls180.v:2232.12-2232.40" + wire width 8 \builder_csrbank6_dma_base3_r + attribute \src "ls180.v:2231.6-2231.35" + wire \builder_csrbank6_dma_base3_re + attribute \src "ls180.v:2234.12-2234.40" + wire width 8 \builder_csrbank6_dma_base3_w + attribute \src "ls180.v:2233.6-2233.35" + wire \builder_csrbank6_dma_base3_we + attribute \src "ls180.v:2228.12-2228.40" + wire width 8 \builder_csrbank6_dma_base4_r + attribute \src "ls180.v:2227.6-2227.35" + wire \builder_csrbank6_dma_base4_re + attribute \src "ls180.v:2230.12-2230.40" + wire width 8 \builder_csrbank6_dma_base4_w + attribute \src "ls180.v:2229.6-2229.35" + wire \builder_csrbank6_dma_base4_we + attribute \src "ls180.v:2224.12-2224.40" + wire width 8 \builder_csrbank6_dma_base5_r + attribute \src "ls180.v:2223.6-2223.35" + wire \builder_csrbank6_dma_base5_re + attribute \src "ls180.v:2226.12-2226.40" + wire width 8 \builder_csrbank6_dma_base5_w + attribute \src "ls180.v:2225.6-2225.35" + wire \builder_csrbank6_dma_base5_we + attribute \src "ls180.v:2220.12-2220.40" + wire width 8 \builder_csrbank6_dma_base6_r + attribute \src "ls180.v:2219.6-2219.35" + wire \builder_csrbank6_dma_base6_re + attribute \src "ls180.v:2222.12-2222.40" + wire width 8 \builder_csrbank6_dma_base6_w + attribute \src "ls180.v:2221.6-2221.35" + wire \builder_csrbank6_dma_base6_we + attribute \src "ls180.v:2216.12-2216.40" + wire width 8 \builder_csrbank6_dma_base7_r + attribute \src "ls180.v:2215.6-2215.35" + wire \builder_csrbank6_dma_base7_re + attribute \src "ls180.v:2218.12-2218.40" + wire width 8 \builder_csrbank6_dma_base7_w + attribute \src "ls180.v:2217.6-2217.35" + wire \builder_csrbank6_dma_base7_we + attribute \src "ls180.v:2268.6-2268.33" + wire \builder_csrbank6_dma_done_r + attribute \src "ls180.v:2267.6-2267.34" + wire \builder_csrbank6_dma_done_re + attribute \src "ls180.v:2270.6-2270.33" + wire \builder_csrbank6_dma_done_w + attribute \src "ls180.v:2269.6-2269.34" + wire \builder_csrbank6_dma_done_we + attribute \src "ls180.v:2264.6-2264.36" + wire \builder_csrbank6_dma_enable0_r + attribute \src "ls180.v:2263.6-2263.37" + wire \builder_csrbank6_dma_enable0_re + attribute \src "ls180.v:2266.6-2266.36" + wire \builder_csrbank6_dma_enable0_w + attribute \src "ls180.v:2265.6-2265.37" + wire \builder_csrbank6_dma_enable0_we + attribute \src "ls180.v:2260.12-2260.42" + wire width 8 \builder_csrbank6_dma_length0_r + attribute \src "ls180.v:2259.6-2259.37" + wire \builder_csrbank6_dma_length0_re + attribute \src "ls180.v:2262.12-2262.42" + wire width 8 \builder_csrbank6_dma_length0_w + attribute \src "ls180.v:2261.6-2261.37" + wire \builder_csrbank6_dma_length0_we + attribute \src "ls180.v:2256.12-2256.42" + wire width 8 \builder_csrbank6_dma_length1_r + attribute \src "ls180.v:2255.6-2255.37" + wire \builder_csrbank6_dma_length1_re + attribute \src "ls180.v:2258.12-2258.42" + wire width 8 \builder_csrbank6_dma_length1_w + attribute \src "ls180.v:2257.6-2257.37" + wire \builder_csrbank6_dma_length1_we + attribute \src "ls180.v:2252.12-2252.42" + wire width 8 \builder_csrbank6_dma_length2_r + attribute \src "ls180.v:2251.6-2251.37" + wire \builder_csrbank6_dma_length2_re + attribute \src "ls180.v:2254.12-2254.42" + wire width 8 \builder_csrbank6_dma_length2_w + attribute \src "ls180.v:2253.6-2253.37" + wire \builder_csrbank6_dma_length2_we + attribute \src "ls180.v:2248.12-2248.42" + wire width 8 \builder_csrbank6_dma_length3_r + attribute \src "ls180.v:2247.6-2247.37" + wire \builder_csrbank6_dma_length3_re + attribute \src "ls180.v:2250.12-2250.42" + wire width 8 \builder_csrbank6_dma_length3_w + attribute \src "ls180.v:2249.6-2249.37" + wire \builder_csrbank6_dma_length3_we + attribute \src "ls180.v:2272.6-2272.34" + wire \builder_csrbank6_dma_loop0_r + attribute \src "ls180.v:2271.6-2271.35" + wire \builder_csrbank6_dma_loop0_re + attribute \src "ls180.v:2274.6-2274.34" + wire \builder_csrbank6_dma_loop0_w + attribute \src "ls180.v:2273.6-2273.35" + wire \builder_csrbank6_dma_loop0_we + attribute \src "ls180.v:2288.12-2288.42" + wire width 8 \builder_csrbank6_dma_offset0_r + attribute \src "ls180.v:2287.6-2287.37" + wire \builder_csrbank6_dma_offset0_re + attribute \src "ls180.v:2290.12-2290.42" + wire width 8 \builder_csrbank6_dma_offset0_w + attribute \src "ls180.v:2289.6-2289.37" + wire \builder_csrbank6_dma_offset0_we + attribute \src "ls180.v:2284.12-2284.42" + wire width 8 \builder_csrbank6_dma_offset1_r + attribute \src "ls180.v:2283.6-2283.37" + wire \builder_csrbank6_dma_offset1_re + attribute \src "ls180.v:2286.12-2286.42" + wire width 8 \builder_csrbank6_dma_offset1_w + attribute \src "ls180.v:2285.6-2285.37" + wire \builder_csrbank6_dma_offset1_we + attribute \src "ls180.v:2280.12-2280.42" + wire width 8 \builder_csrbank6_dma_offset2_r + attribute \src "ls180.v:2279.6-2279.37" + wire \builder_csrbank6_dma_offset2_re + attribute \src "ls180.v:2282.12-2282.42" + wire width 8 \builder_csrbank6_dma_offset2_w + attribute \src "ls180.v:2281.6-2281.37" + wire \builder_csrbank6_dma_offset2_we + attribute \src "ls180.v:2276.12-2276.42" + wire width 8 \builder_csrbank6_dma_offset3_r + attribute \src "ls180.v:2275.6-2275.37" + wire \builder_csrbank6_dma_offset3_re + attribute \src "ls180.v:2278.12-2278.42" + wire width 8 \builder_csrbank6_dma_offset3_w + attribute \src "ls180.v:2277.6-2277.37" + wire \builder_csrbank6_dma_offset3_we + attribute \src "ls180.v:2291.6-2291.26" + wire \builder_csrbank6_sel + attribute \src "ls180.v:2297.6-2297.36" + wire \builder_csrbank7_card_detect_r + attribute \src "ls180.v:2296.6-2296.37" + wire \builder_csrbank7_card_detect_re + attribute \src "ls180.v:2299.6-2299.36" + wire \builder_csrbank7_card_detect_w + attribute \src "ls180.v:2298.6-2298.37" + wire \builder_csrbank7_card_detect_we + attribute \src "ls180.v:2305.12-2305.47" + wire width 8 \builder_csrbank7_clocker_divider0_r + attribute \src "ls180.v:2304.6-2304.42" + wire \builder_csrbank7_clocker_divider0_re + attribute \src "ls180.v:2307.12-2307.47" + wire width 8 \builder_csrbank7_clocker_divider0_w + attribute \src "ls180.v:2306.6-2306.42" + wire \builder_csrbank7_clocker_divider0_we + attribute \src "ls180.v:2301.6-2301.41" + wire \builder_csrbank7_clocker_divider1_r + attribute \src "ls180.v:2300.6-2300.42" + wire \builder_csrbank7_clocker_divider1_re + attribute \src "ls180.v:2303.6-2303.41" + wire \builder_csrbank7_clocker_divider1_w + attribute \src "ls180.v:2302.6-2302.42" + wire \builder_csrbank7_clocker_divider1_we + attribute \src "ls180.v:2308.6-2308.26" + wire \builder_csrbank7_sel + attribute \src "ls180.v:2314.12-2314.44" + wire width 4 \builder_csrbank8_dfii_control0_r + attribute \src "ls180.v:2313.6-2313.39" + wire \builder_csrbank8_dfii_control0_re + attribute \src "ls180.v:2316.12-2316.44" + wire width 4 \builder_csrbank8_dfii_control0_w + attribute \src "ls180.v:2315.6-2315.39" + wire \builder_csrbank8_dfii_control0_we + attribute \src "ls180.v:2326.12-2326.48" + wire width 8 \builder_csrbank8_dfii_pi0_address0_r + attribute \src "ls180.v:2325.6-2325.43" + wire \builder_csrbank8_dfii_pi0_address0_re + attribute \src "ls180.v:2328.12-2328.48" + wire width 8 \builder_csrbank8_dfii_pi0_address0_w + attribute \src "ls180.v:2327.6-2327.43" + wire \builder_csrbank8_dfii_pi0_address0_we + attribute \src "ls180.v:2322.12-2322.48" + wire width 5 \builder_csrbank8_dfii_pi0_address1_r + attribute \src "ls180.v:2321.6-2321.43" + wire \builder_csrbank8_dfii_pi0_address1_re + attribute \src "ls180.v:2324.12-2324.48" + wire width 5 \builder_csrbank8_dfii_pi0_address1_w + attribute \src "ls180.v:2323.6-2323.43" + wire \builder_csrbank8_dfii_pi0_address1_we + attribute \src "ls180.v:2330.12-2330.49" + wire width 2 \builder_csrbank8_dfii_pi0_baddress0_r + attribute \src "ls180.v:2329.6-2329.44" + wire \builder_csrbank8_dfii_pi0_baddress0_re + attribute \src "ls180.v:2332.12-2332.49" + wire width 2 \builder_csrbank8_dfii_pi0_baddress0_w + attribute \src "ls180.v:2331.6-2331.44" + wire \builder_csrbank8_dfii_pi0_baddress0_we + attribute \src "ls180.v:2318.12-2318.48" + wire width 6 \builder_csrbank8_dfii_pi0_command0_r + attribute \src "ls180.v:2317.6-2317.43" + wire \builder_csrbank8_dfii_pi0_command0_re + attribute \src "ls180.v:2320.12-2320.48" + wire width 6 \builder_csrbank8_dfii_pi0_command0_w + attribute \src "ls180.v:2319.6-2319.43" + wire \builder_csrbank8_dfii_pi0_command0_we + attribute \src "ls180.v:2346.12-2346.47" + wire width 8 \builder_csrbank8_dfii_pi0_rddata0_r + attribute \src "ls180.v:2345.6-2345.42" + wire \builder_csrbank8_dfii_pi0_rddata0_re + attribute \src "ls180.v:2348.12-2348.47" + wire width 8 \builder_csrbank8_dfii_pi0_rddata0_w + attribute \src "ls180.v:2347.6-2347.42" + wire \builder_csrbank8_dfii_pi0_rddata0_we + attribute \src "ls180.v:2342.12-2342.47" + wire width 8 \builder_csrbank8_dfii_pi0_rddata1_r + attribute \src "ls180.v:2341.6-2341.42" + wire \builder_csrbank8_dfii_pi0_rddata1_re + attribute \src "ls180.v:2344.12-2344.47" + wire width 8 \builder_csrbank8_dfii_pi0_rddata1_w + attribute \src "ls180.v:2343.6-2343.42" + wire \builder_csrbank8_dfii_pi0_rddata1_we + attribute \src "ls180.v:2338.12-2338.47" + wire width 8 \builder_csrbank8_dfii_pi0_wrdata0_r + attribute \src "ls180.v:2337.6-2337.42" + wire \builder_csrbank8_dfii_pi0_wrdata0_re + attribute \src "ls180.v:2340.12-2340.47" + wire width 8 \builder_csrbank8_dfii_pi0_wrdata0_w + attribute \src "ls180.v:2339.6-2339.42" + wire \builder_csrbank8_dfii_pi0_wrdata0_we + attribute \src "ls180.v:2334.12-2334.47" + wire width 8 \builder_csrbank8_dfii_pi0_wrdata1_r + attribute \src "ls180.v:2333.6-2333.42" + wire \builder_csrbank8_dfii_pi0_wrdata1_re + attribute \src "ls180.v:2336.12-2336.47" + wire width 8 \builder_csrbank8_dfii_pi0_wrdata1_w + attribute \src "ls180.v:2335.6-2335.42" + wire \builder_csrbank8_dfii_pi0_wrdata1_we + attribute \src "ls180.v:2349.6-2349.26" + wire \builder_csrbank8_sel + attribute \src "ls180.v:2359.12-2359.39" + wire width 8 \builder_csrbank9_control0_r + attribute \src "ls180.v:2358.6-2358.34" + wire \builder_csrbank9_control0_re + attribute \src "ls180.v:2361.12-2361.39" + wire width 8 \builder_csrbank9_control0_w + attribute \src "ls180.v:2360.6-2360.34" + wire \builder_csrbank9_control0_we + attribute \src "ls180.v:2355.12-2355.39" + wire width 8 \builder_csrbank9_control1_r + attribute \src "ls180.v:2354.6-2354.34" + wire \builder_csrbank9_control1_re + attribute \src "ls180.v:2357.12-2357.39" + wire width 8 \builder_csrbank9_control1_w + attribute \src "ls180.v:2356.6-2356.34" + wire \builder_csrbank9_control1_we + attribute \src "ls180.v:2375.6-2375.28" + wire \builder_csrbank9_cs0_r + attribute \src "ls180.v:2374.6-2374.29" + wire \builder_csrbank9_cs0_re + attribute \src "ls180.v:2377.6-2377.28" + wire \builder_csrbank9_cs0_w + attribute \src "ls180.v:2376.6-2376.29" + wire \builder_csrbank9_cs0_we + attribute \src "ls180.v:2379.6-2379.34" + wire \builder_csrbank9_loopback0_r + attribute \src "ls180.v:2378.6-2378.35" + wire \builder_csrbank9_loopback0_re + attribute \src "ls180.v:2381.6-2381.34" + wire \builder_csrbank9_loopback0_w + attribute \src "ls180.v:2380.6-2380.35" + wire \builder_csrbank9_loopback0_we + attribute \src "ls180.v:2371.12-2371.35" + wire width 8 \builder_csrbank9_miso_r + attribute \src "ls180.v:2370.6-2370.30" + wire \builder_csrbank9_miso_re + attribute \src "ls180.v:2373.12-2373.35" + wire width 8 \builder_csrbank9_miso_w + attribute \src "ls180.v:2372.6-2372.30" + wire \builder_csrbank9_miso_we + attribute \src "ls180.v:2367.12-2367.36" + wire width 8 \builder_csrbank9_mosi0_r + attribute \src "ls180.v:2366.6-2366.31" + wire \builder_csrbank9_mosi0_re + attribute \src "ls180.v:2369.12-2369.36" + wire width 8 \builder_csrbank9_mosi0_w + attribute \src "ls180.v:2368.6-2368.31" + wire \builder_csrbank9_mosi0_we + attribute \src "ls180.v:2382.6-2382.26" + wire \builder_csrbank9_sel + attribute \src "ls180.v:2363.6-2363.31" + wire \builder_csrbank9_status_r + attribute \src "ls180.v:2362.6-2362.32" + wire \builder_csrbank9_status_re + attribute \src "ls180.v:2365.6-2365.31" + wire \builder_csrbank9_status_w + attribute \src "ls180.v:2364.6-2364.32" + wire \builder_csrbank9_status_we + attribute \src "ls180.v:1859.6-1859.18" + wire \builder_done + attribute \src "ls180.v:1857.5-1857.18" + wire \builder_error + attribute \src "ls180.v:1854.11-1854.24" + wire width 3 \builder_grant + attribute \src "ls180.v:1861.13-1861.44" + wire width 14 \builder_interface0_bank_bus_adr + attribute \src "ls180.v:1864.11-1864.44" + wire width 8 \builder_interface0_bank_bus_dat_r + attribute \src "ls180.v:1863.12-1863.45" + wire width 8 \builder_interface0_bank_bus_dat_w + attribute \src "ls180.v:1862.6-1862.36" + wire \builder_interface0_bank_bus_we + attribute \src "ls180.v:2383.13-2383.45" + wire width 14 \builder_interface10_bank_bus_adr + attribute \src "ls180.v:2386.11-2386.45" + wire width 8 \builder_interface10_bank_bus_dat_r + attribute \src "ls180.v:2385.12-2385.46" + wire width 8 \builder_interface10_bank_bus_dat_w + attribute \src "ls180.v:2384.6-2384.37" + wire \builder_interface10_bank_bus_we + attribute \src "ls180.v:2424.13-2424.45" + wire width 14 \builder_interface11_bank_bus_adr + attribute \src "ls180.v:2427.11-2427.45" + wire width 8 \builder_interface11_bank_bus_dat_r + attribute \src "ls180.v:2426.12-2426.46" + wire width 8 \builder_interface11_bank_bus_dat_w + attribute \src "ls180.v:2425.6-2425.37" + wire \builder_interface11_bank_bus_we + attribute \src "ls180.v:2489.13-2489.45" + wire width 14 \builder_interface12_bank_bus_adr + attribute \src "ls180.v:2492.11-2492.45" + wire width 8 \builder_interface12_bank_bus_dat_r + attribute \src "ls180.v:2491.12-2491.46" + wire width 8 \builder_interface12_bank_bus_dat_w + attribute \src "ls180.v:2490.6-2490.37" + wire \builder_interface12_bank_bus_we + attribute \src "ls180.v:2514.13-2514.45" + wire width 14 \builder_interface13_bank_bus_adr + attribute \src "ls180.v:2517.11-2517.45" + wire width 8 \builder_interface13_bank_bus_dat_r + attribute \src "ls180.v:2516.12-2516.46" + wire width 8 \builder_interface13_bank_bus_dat_w + attribute \src "ls180.v:2515.6-2515.37" + wire \builder_interface13_bank_bus_we + attribute \src "ls180.v:1902.13-1902.44" + wire width 14 \builder_interface1_bank_bus_adr + attribute \src "ls180.v:1905.11-1905.44" + wire width 8 \builder_interface1_bank_bus_dat_r + attribute \src "ls180.v:1904.12-1904.45" + wire width 8 \builder_interface1_bank_bus_dat_w + attribute \src "ls180.v:1903.6-1903.36" + wire \builder_interface1_bank_bus_we + attribute \src "ls180.v:1931.13-1931.44" + wire width 14 \builder_interface2_bank_bus_adr + attribute \src "ls180.v:1934.11-1934.44" + wire width 8 \builder_interface2_bank_bus_dat_r + attribute \src "ls180.v:1933.12-1933.45" + wire width 8 \builder_interface2_bank_bus_dat_w + attribute \src "ls180.v:1932.6-1932.36" + wire \builder_interface2_bank_bus_we + attribute \src "ls180.v:1972.13-1972.44" + wire width 14 \builder_interface3_bank_bus_adr + attribute \src "ls180.v:1975.11-1975.44" + wire width 8 \builder_interface3_bank_bus_dat_r + attribute \src "ls180.v:1974.12-1974.45" + wire width 8 \builder_interface3_bank_bus_dat_w + attribute \src "ls180.v:1973.6-1973.36" + wire \builder_interface3_bank_bus_we + attribute \src "ls180.v:2013.13-2013.44" + wire width 14 \builder_interface4_bank_bus_adr + attribute \src "ls180.v:2016.11-2016.44" + wire width 8 \builder_interface4_bank_bus_dat_r + attribute \src "ls180.v:2015.12-2015.45" + wire width 8 \builder_interface4_bank_bus_dat_w + attribute \src "ls180.v:2014.6-2014.36" + wire \builder_interface4_bank_bus_we + attribute \src "ls180.v:2078.13-2078.44" + wire width 14 \builder_interface5_bank_bus_adr + attribute \src "ls180.v:2081.11-2081.44" + wire width 8 \builder_interface5_bank_bus_dat_r + attribute \src "ls180.v:2080.12-2080.45" + wire width 8 \builder_interface5_bank_bus_dat_w + attribute \src "ls180.v:2079.6-2079.36" + wire \builder_interface5_bank_bus_we + attribute \src "ls180.v:2211.13-2211.44" + wire width 14 \builder_interface6_bank_bus_adr + attribute \src "ls180.v:2214.11-2214.44" + wire width 8 \builder_interface6_bank_bus_dat_r + attribute \src "ls180.v:2213.12-2213.45" + wire width 8 \builder_interface6_bank_bus_dat_w + attribute \src "ls180.v:2212.6-2212.36" + wire \builder_interface6_bank_bus_we + attribute \src "ls180.v:2292.13-2292.44" + wire width 14 \builder_interface7_bank_bus_adr + attribute \src "ls180.v:2295.11-2295.44" + wire width 8 \builder_interface7_bank_bus_dat_r + attribute \src "ls180.v:2294.12-2294.45" + wire width 8 \builder_interface7_bank_bus_dat_w + attribute \src "ls180.v:2293.6-2293.36" + wire \builder_interface7_bank_bus_we + attribute \src "ls180.v:2309.13-2309.44" + wire width 14 \builder_interface8_bank_bus_adr + attribute \src "ls180.v:2312.11-2312.44" + wire width 8 \builder_interface8_bank_bus_dat_r + attribute \src "ls180.v:2311.12-2311.45" + wire width 8 \builder_interface8_bank_bus_dat_w + attribute \src "ls180.v:2310.6-2310.36" + wire \builder_interface8_bank_bus_we + attribute \src "ls180.v:2350.13-2350.44" + wire width 14 \builder_interface9_bank_bus_adr + attribute \src "ls180.v:2353.11-2353.44" + wire width 8 \builder_interface9_bank_bus_dat_r + attribute \src "ls180.v:2352.12-2352.45" + wire width 8 \builder_interface9_bank_bus_dat_w + attribute \src "ls180.v:2351.6-2351.36" + wire \builder_interface9_bank_bus_we + attribute \src "ls180.v:1827.12-1827.35" + wire width 14 \builder_libresocsim_adr + attribute \src "ls180.v:2543.12-2543.47" + wire width 14 \builder_libresocsim_adr_next_value1 + attribute \src "ls180.v:2544.5-2544.43" + wire \builder_libresocsim_adr_next_value_ce1 + attribute \src "ls180.v:1830.12-1830.37" + wire width 8 \builder_libresocsim_dat_r + attribute \src "ls180.v:1829.11-1829.36" + wire width 8 \builder_libresocsim_dat_w + attribute \src "ls180.v:2541.11-2541.48" + wire width 8 \builder_libresocsim_dat_w_next_value0 + attribute \src "ls180.v:2542.5-2542.45" + wire \builder_libresocsim_dat_w_next_value_ce0 + attribute \src "ls180.v:1828.5-1828.27" + wire \builder_libresocsim_we + attribute \src "ls180.v:2545.5-2545.39" + wire \builder_libresocsim_we_next_value2 + attribute \src "ls180.v:2546.5-2546.42" + wire \builder_libresocsim_we_next_value_ce2 + attribute \src "ls180.v:1837.5-1837.37" + wire \builder_libresocsim_wishbone_ack + attribute \src "ls180.v:1831.13-1831.45" + wire width 30 \builder_libresocsim_wishbone_adr + attribute \src "ls180.v:1840.12-1840.44" + wire width 2 \builder_libresocsim_wishbone_bte + attribute \src "ls180.v:1839.12-1839.44" + wire width 3 \builder_libresocsim_wishbone_cti + attribute \src "ls180.v:1835.6-1835.38" + wire \builder_libresocsim_wishbone_cyc + attribute \src "ls180.v:1833.12-1833.46" + wire width 32 \builder_libresocsim_wishbone_dat_r + attribute \src "ls180.v:1832.13-1832.47" + wire width 32 \builder_libresocsim_wishbone_dat_w + attribute \src "ls180.v:1841.5-1841.37" + wire \builder_libresocsim_wishbone_err + attribute \src "ls180.v:1834.12-1834.44" + wire width 4 \builder_libresocsim_wishbone_sel + attribute \src "ls180.v:1836.6-1836.38" + wire \builder_libresocsim_wishbone_stb + attribute \src "ls180.v:1838.6-1838.37" + wire \builder_libresocsim_wishbone_we + attribute \src "ls180.v:1730.5-1730.20" + wire \builder_locked0 + attribute \src "ls180.v:1731.5-1731.20" + wire \builder_locked1 + attribute \src "ls180.v:1732.5-1732.20" + wire \builder_locked2 + attribute \src "ls180.v:1733.5-1733.20" + wire \builder_locked3 + attribute \src "ls180.v:1717.11-1717.41" + wire width 3 \builder_multiplexer_next_state + attribute \src "ls180.v:1716.11-1716.36" + wire width 3 \builder_multiplexer_state + attribute \no_retiming "true" + attribute \src "ls180.v:2650.32-2650.59" + wire \builder_multiregimpl0_regs0 + attribute \no_retiming "true" + attribute \src "ls180.v:2651.32-2651.59" + wire \builder_multiregimpl0_regs1 + attribute \no_retiming "true" + attribute \src "ls180.v:2670.32-2670.60" + wire \builder_multiregimpl10_regs0 + attribute \no_retiming "true" + attribute \src "ls180.v:2671.32-2671.60" + wire \builder_multiregimpl10_regs1 + attribute \no_retiming "true" + attribute \src "ls180.v:2672.32-2672.60" + wire \builder_multiregimpl11_regs0 + attribute \no_retiming "true" + attribute \src "ls180.v:2673.32-2673.60" + wire \builder_multiregimpl11_regs1 + attribute \no_retiming "true" + attribute \src "ls180.v:2674.32-2674.60" + wire \builder_multiregimpl12_regs0 + attribute \no_retiming "true" + attribute \src "ls180.v:2675.32-2675.60" + wire \builder_multiregimpl12_regs1 + attribute \no_retiming "true" + attribute \src "ls180.v:2676.32-2676.60" + wire \builder_multiregimpl13_regs0 + attribute \no_retiming "true" + attribute \src "ls180.v:2677.32-2677.60" + wire \builder_multiregimpl13_regs1 + attribute \no_retiming "true" + attribute \src "ls180.v:2678.32-2678.60" + wire \builder_multiregimpl14_regs0 + attribute \no_retiming "true" + attribute \src "ls180.v:2679.32-2679.60" + wire \builder_multiregimpl14_regs1 + attribute \no_retiming "true" + attribute \src "ls180.v:2680.32-2680.60" + wire \builder_multiregimpl15_regs0 + attribute \no_retiming "true" + attribute \src "ls180.v:2681.32-2681.60" + wire \builder_multiregimpl15_regs1 + attribute \no_retiming "true" + attribute \src "ls180.v:2682.32-2682.60" + wire \builder_multiregimpl16_regs0 + attribute \no_retiming "true" + attribute \src "ls180.v:2683.32-2683.60" + wire \builder_multiregimpl16_regs1 + attribute \no_retiming "true" + attribute \src "ls180.v:2652.32-2652.59" + wire \builder_multiregimpl1_regs0 + attribute \no_retiming "true" + attribute \src "ls180.v:2653.32-2653.59" + wire \builder_multiregimpl1_regs1 + attribute \no_retiming "true" + attribute \src "ls180.v:2654.32-2654.59" + wire \builder_multiregimpl2_regs0 + attribute \no_retiming "true" + attribute \src "ls180.v:2655.32-2655.59" + wire \builder_multiregimpl2_regs1 + attribute \no_retiming "true" + attribute \src "ls180.v:2656.32-2656.59" + wire \builder_multiregimpl3_regs0 + attribute \no_retiming "true" + attribute \src "ls180.v:2657.32-2657.59" + wire \builder_multiregimpl3_regs1 + attribute \no_retiming "true" + attribute \src "ls180.v:2658.32-2658.59" + wire \builder_multiregimpl4_regs0 + attribute \no_retiming "true" + attribute \src "ls180.v:2659.32-2659.59" + wire \builder_multiregimpl4_regs1 + attribute \no_retiming "true" + attribute \src "ls180.v:2660.32-2660.59" + wire \builder_multiregimpl5_regs0 + attribute \no_retiming "true" + attribute \src "ls180.v:2661.32-2661.59" + wire \builder_multiregimpl5_regs1 + attribute \no_retiming "true" + attribute \src "ls180.v:2662.32-2662.59" + wire \builder_multiregimpl6_regs0 + attribute \no_retiming "true" + attribute \src "ls180.v:2663.32-2663.59" + wire \builder_multiregimpl6_regs1 + attribute \no_retiming "true" + attribute \src "ls180.v:2664.32-2664.59" + wire \builder_multiregimpl7_regs0 + attribute \no_retiming "true" + attribute \src "ls180.v:2665.32-2665.59" + wire \builder_multiregimpl7_regs1 + attribute \no_retiming "true" + attribute \src "ls180.v:2666.32-2666.59" + wire \builder_multiregimpl8_regs0 + attribute \no_retiming "true" + attribute \src "ls180.v:2667.32-2667.59" + wire \builder_multiregimpl8_regs1 + attribute \no_retiming "true" + attribute \src "ls180.v:2668.32-2668.59" + wire \builder_multiregimpl9_regs0 + attribute \no_retiming "true" + attribute \src "ls180.v:2669.32-2669.59" + wire \builder_multiregimpl9_regs1 + attribute \src "ls180.v:1735.5-1735.36" + wire \builder_new_master_rdata_valid0 + attribute \src "ls180.v:1736.5-1736.36" + wire \builder_new_master_rdata_valid1 + attribute \src "ls180.v:1737.5-1737.36" + wire \builder_new_master_rdata_valid2 + attribute \src "ls180.v:1738.5-1738.36" + wire \builder_new_master_rdata_valid3 + attribute \src "ls180.v:1734.5-1734.35" + wire \builder_new_master_wdata_ready + attribute \src "ls180.v:2540.11-2540.29" + wire width 2 \builder_next_state + attribute \src "ls180.v:1707.11-1707.39" + wire width 2 \builder_refresher_next_state + attribute \src "ls180.v:1706.11-1706.34" + wire width 2 \builder_refresher_state + attribute \src "ls180.v:1853.12-1853.27" + wire width 5 \builder_request + attribute \src "ls180.v:1720.6-1720.28" + wire \builder_roundrobin0_ce + attribute \src "ls180.v:1719.6-1719.31" + wire \builder_roundrobin0_grant + attribute \src "ls180.v:1718.6-1718.33" + wire \builder_roundrobin0_request + attribute \src "ls180.v:1723.6-1723.28" + wire \builder_roundrobin1_ce + attribute \src "ls180.v:1722.6-1722.31" + wire \builder_roundrobin1_grant + attribute \src "ls180.v:1721.6-1721.33" + wire \builder_roundrobin1_request + attribute \src "ls180.v:1726.6-1726.28" + wire \builder_roundrobin2_ce + attribute \src "ls180.v:1725.6-1725.31" + wire \builder_roundrobin2_grant + attribute \src "ls180.v:1724.6-1724.33" + wire \builder_roundrobin2_request + attribute \src "ls180.v:1729.6-1729.28" + wire \builder_roundrobin3_ce + attribute \src "ls180.v:1728.6-1728.31" + wire \builder_roundrobin3_grant + attribute \src "ls180.v:1727.6-1727.33" + wire \builder_roundrobin3_request + attribute \src "ls180.v:1812.11-1812.44" + wire width 2 \builder_sdblock2memdma_next_state + attribute \src "ls180.v:1811.11-1811.39" + wire width 2 \builder_sdblock2memdma_state + attribute \src "ls180.v:1780.5-1780.50" + wire \builder_sdcore_crcupstreaminserter_next_state + attribute \src "ls180.v:1779.5-1779.45" + wire \builder_sdcore_crcupstreaminserter_state + attribute \src "ls180.v:1792.11-1792.40" + wire width 3 \builder_sdcore_fsm_next_state + attribute \src "ls180.v:1791.11-1791.35" + wire width 3 \builder_sdcore_fsm_state + attribute \src "ls180.v:1816.5-1816.42" + wire \builder_sdmem2blockdma_fsm_next_state + attribute \src "ls180.v:1815.5-1815.37" + wire \builder_sdmem2blockdma_fsm_state + attribute \src "ls180.v:1820.11-1820.58" + wire width 2 \builder_sdmem2blockdma_resetinserter_next_state + attribute \src "ls180.v:1819.11-1819.53" + wire width 2 \builder_sdmem2blockdma_resetinserter_state + attribute \src "ls180.v:1768.11-1768.39" + wire width 3 \builder_sdphy_fsm_next_state + attribute \src "ls180.v:1767.11-1767.34" + wire width 3 \builder_sdphy_fsm_state + attribute \src "ls180.v:1756.11-1756.45" + wire width 3 \builder_sdphy_sdphycmdr_next_state + attribute \src "ls180.v:1755.11-1755.40" + wire width 3 \builder_sdphy_sdphycmdr_state + attribute \src "ls180.v:1752.11-1752.45" + wire width 2 \builder_sdphy_sdphycmdw_next_state + attribute \src "ls180.v:1751.11-1751.40" + wire width 2 \builder_sdphy_sdphycmdw_state + attribute \src "ls180.v:1764.5-1764.39" + wire \builder_sdphy_sdphycrcr_next_state + attribute \src "ls180.v:1763.5-1763.34" + wire \builder_sdphy_sdphycrcr_state + attribute \src "ls180.v:1772.11-1772.46" + wire width 3 \builder_sdphy_sdphydatar_next_state + attribute \src "ls180.v:1771.11-1771.41" + wire width 3 \builder_sdphy_sdphydatar_state + attribute \src "ls180.v:1748.5-1748.39" + wire \builder_sdphy_sdphyinit_next_state + attribute \src "ls180.v:1747.5-1747.34" + wire \builder_sdphy_sdphyinit_state + attribute \src "ls180.v:1848.5-1848.23" + wire \builder_shared_ack + attribute \src "ls180.v:1842.13-1842.31" + wire width 30 \builder_shared_adr + attribute \src "ls180.v:1851.12-1851.30" + wire width 2 \builder_shared_bte + attribute \src "ls180.v:1850.12-1850.30" + wire width 3 \builder_shared_cti + attribute \src "ls180.v:1846.6-1846.24" + wire \builder_shared_cyc + attribute \src "ls180.v:1844.12-1844.32" + wire width 32 \builder_shared_dat_r + attribute \src "ls180.v:1843.13-1843.33" + wire width 32 \builder_shared_dat_w + attribute \src "ls180.v:1852.6-1852.24" + wire \builder_shared_err + attribute \src "ls180.v:1845.12-1845.30" + wire width 4 \builder_shared_sel + attribute \src "ls180.v:1847.6-1847.24" + wire \builder_shared_stb + attribute \src "ls180.v:1849.6-1849.23" + wire \builder_shared_we + attribute \src "ls180.v:1855.11-1855.28" + wire width 5 \builder_slave_sel + attribute \src "ls180.v:1856.11-1856.30" + wire width 5 \builder_slave_sel_r + attribute \src "ls180.v:1744.11-1744.40" + wire width 2 \builder_spimaster0_next_state + attribute \src "ls180.v:1743.11-1743.35" + wire width 2 \builder_spimaster0_state + attribute \src "ls180.v:1824.11-1824.40" + wire width 2 \builder_spimaster1_next_state + attribute \src "ls180.v:1823.11-1823.35" + wire width 2 \builder_spimaster1_state + attribute \src "ls180.v:2539.11-2539.24" + wire width 2 \builder_state + attribute \src "ls180.v:2592.5-2592.32" + wire \builder_sync_f_array_muxed0 + attribute \src "ls180.v:2593.5-2593.32" + wire \builder_sync_f_array_muxed1 + attribute \src "ls180.v:2585.11-2585.40" + wire width 2 \builder_sync_rhs_array_muxed0 + attribute \src "ls180.v:2586.12-2586.41" + wire width 13 \builder_sync_rhs_array_muxed1 + attribute \src "ls180.v:2587.5-2587.34" + wire \builder_sync_rhs_array_muxed2 + attribute \src "ls180.v:2588.5-2588.34" + wire \builder_sync_rhs_array_muxed3 + attribute \src "ls180.v:2589.5-2589.34" + wire \builder_sync_rhs_array_muxed4 + attribute \src "ls180.v:2590.5-2590.34" + wire \builder_sync_rhs_array_muxed5 + attribute \src "ls180.v:2591.5-2591.34" + wire \builder_sync_rhs_array_muxed6 + attribute \src "ls180.v:1858.6-1858.18" + wire \builder_wait + attribute \src "ls180.v:28.19-28.23" + wire width 3 input 24 \eint + attribute \src "ls180.v:21.20-21.26" + wire width 16 input 17 \gpio_i + attribute \src "ls180.v:22.21-22.27" + wire width 16 output 18 \gpio_o + attribute \src "ls180.v:23.21-23.28" + wire width 16 output 19 \gpio_oe + attribute \src "ls180.v:30.13-30.21" + wire input 26 \jtag_tck + attribute \src "ls180.v:31.13-31.21" + wire input 27 \jtag_tdi + attribute \src "ls180.v:32.14-32.22" + wire output 28 \jtag_tdo + attribute \src "ls180.v:29.13-29.21" + wire input 25 \jtag_tms + attribute \src "ls180.v:1664.13-1664.37" + wire width 16 \libresocsim_clk_divider0 + attribute \src "ls180.v:1686.12-1686.36" + wire width 16 \libresocsim_clk_divider1 + attribute \src "ls180.v:1681.5-1681.27" + wire \libresocsim_clk_enable + attribute \src "ls180.v:1688.6-1688.26" + wire \libresocsim_clk_fall + attribute \src "ls180.v:1687.6-1687.26" + wire \libresocsim_clk_rise + attribute \src "ls180.v:1668.5-1668.27" + wire \libresocsim_control_re + attribute \src "ls180.v:1667.12-1667.39" + wire width 16 \libresocsim_control_storage + attribute \src "ls180.v:1683.11-1683.28" + wire width 3 \libresocsim_count + attribute \src "ls180.v:1825.11-1825.50" + wire width 3 \libresocsim_count_spimaster1_next_value + attribute \src "ls180.v:1826.5-1826.47" + wire \libresocsim_count_spimaster1_next_value_ce + attribute \src "ls180.v:1662.6-1662.20" + wire \libresocsim_cs + attribute \src "ls180.v:1682.5-1682.26" + wire \libresocsim_cs_enable + attribute \src "ls180.v:1678.5-1678.22" + wire \libresocsim_cs_re + attribute \src "ls180.v:1677.5-1677.27" + wire \libresocsim_cs_storage + attribute \src "ls180.v:1658.5-1658.22" + wire \libresocsim_done0 + attribute \src "ls180.v:1669.6-1669.23" + wire \libresocsim_done1 + attribute \src "ls180.v:1659.5-1659.20" + wire \libresocsim_irq + attribute \src "ls180.v:1657.12-1657.31" + wire width 8 \libresocsim_length0 + attribute \src "ls180.v:1666.12-1666.31" + wire width 8 \libresocsim_length1 + attribute \src "ls180.v:1663.6-1663.26" + wire \libresocsim_loopback + attribute \src "ls180.v:1680.5-1680.28" + wire \libresocsim_loopback_re + attribute \src "ls180.v:1679.5-1679.33" + wire \libresocsim_loopback_storage + attribute \src "ls180.v:1661.11-1661.27" + wire width 8 \libresocsim_miso + attribute \src "ls180.v:1691.11-1691.32" + wire width 8 \libresocsim_miso_data + attribute \src "ls180.v:1685.5-1685.27" + wire \libresocsim_miso_latch + attribute \src "ls180.v:1674.12-1674.35" + wire width 8 \libresocsim_miso_status + attribute \src "ls180.v:1675.6-1675.25" + wire \libresocsim_miso_we + attribute \src "ls180.v:1660.12-1660.28" + wire width 8 \libresocsim_mosi + attribute \src "ls180.v:1689.11-1689.32" + wire width 8 \libresocsim_mosi_data + attribute \src "ls180.v:1684.5-1684.27" + wire \libresocsim_mosi_latch + attribute \src "ls180.v:1673.5-1673.24" + wire \libresocsim_mosi_re + attribute \src "ls180.v:1690.11-1690.31" + wire width 3 \libresocsim_mosi_sel + attribute \src "ls180.v:1672.11-1672.35" + wire width 8 \libresocsim_mosi_storage + attribute \src "ls180.v:1693.5-1693.19" + wire \libresocsim_re + attribute \src "ls180.v:1676.6-1676.21" + wire \libresocsim_sel + attribute \src "ls180.v:1656.6-1656.24" + wire \libresocsim_start0 + attribute \src "ls180.v:1665.5-1665.23" + wire \libresocsim_start1 + attribute \src "ls180.v:1670.6-1670.31" + wire \libresocsim_status_status + attribute \src "ls180.v:1671.6-1671.27" + wire \libresocsim_status_we + attribute \src "ls180.v:1692.12-1692.31" + wire width 16 \libresocsim_storage + attribute \src "ls180.v:806.6-806.18" + wire \main_ack_cmd + attribute \src "ls180.v:808.6-808.20" + wire \main_ack_rdata + attribute \src "ls180.v:807.6-807.20" + wire \main_ack_wdata + attribute \src "ls180.v:804.5-804.22" + wire \main_cmd_consumed + attribute \src "ls180.v:801.5-801.27" + wire \main_converter_counter + attribute \src "ls180.v:1741.5-1741.48" + wire \main_converter_counter_converter_next_value + attribute \src "ls180.v:1742.5-1742.51" + wire \main_converter_counter_converter_next_value_ce + attribute \src "ls180.v:803.12-803.32" + wire width 32 \main_converter_dat_r + attribute \src "ls180.v:802.6-802.26" + wire \main_converter_reset + attribute \src "ls180.v:800.5-800.24" + wire \main_converter_skip + attribute \src "ls180.v:230.6-230.23" + wire \main_dfi_p0_act_n + attribute \src "ls180.v:221.13-221.32" + wire width 13 \main_dfi_p0_address + attribute \src "ls180.v:222.12-222.28" + wire width 2 \main_dfi_p0_bank + attribute \src "ls180.v:223.6-223.23" + wire \main_dfi_p0_cas_n + attribute \src "ls180.v:227.6-227.21" + wire \main_dfi_p0_cke + attribute \src "ls180.v:224.6-224.22" + wire \main_dfi_p0_cs_n + attribute \src "ls180.v:228.6-228.21" + wire \main_dfi_p0_odt + attribute \src "ls180.v:225.6-225.23" + wire \main_dfi_p0_ras_n + attribute \src "ls180.v:235.12-235.30" + wire width 16 \main_dfi_p0_rddata + attribute \src "ls180.v:234.6-234.27" + wire \main_dfi_p0_rddata_en + attribute \src "ls180.v:236.5-236.29" + wire \main_dfi_p0_rddata_valid + attribute \src "ls180.v:229.6-229.25" + wire \main_dfi_p0_reset_n + attribute \src "ls180.v:226.6-226.22" + wire \main_dfi_p0_we_n + attribute \src "ls180.v:231.13-231.31" + wire width 16 \main_dfi_p0_wrdata + attribute \src "ls180.v:232.6-232.27" + wire \main_dfi_p0_wrdata_en + attribute \src "ls180.v:233.12-233.35" + wire width 2 \main_dfi_p0_wrdata_mask + attribute \src "ls180.v:997.12-997.22" + wire width 42 \main_dummy + attribute \src "ls180.v:952.5-952.20" + wire \main_gpio_oe_re + attribute \src "ls180.v:951.12-951.32" + wire width 16 \main_gpio_oe_storage + attribute \src "ls180.v:956.5-956.21" + wire \main_gpio_out_re + attribute \src "ls180.v:955.12-955.33" + wire width 16 \main_gpio_out_storage + attribute \src "ls180.v:957.13-957.29" + wire width 16 \main_gpio_pads_i + attribute \src "ls180.v:958.13-958.29" + wire width 16 \main_gpio_pads_o + attribute \src "ls180.v:959.13-959.30" + wire width 16 \main_gpio_pads_oe + attribute \src "ls180.v:953.12-953.28" + wire width 16 \main_gpio_status + attribute \src "ls180.v:954.6-954.18" + wire \main_gpio_we + attribute \src "ls180.v:220.5-220.17" + wire \main_int_rst + attribute \src "ls180.v:1477.6-1477.29" + wire \main_interface0_bus_ack + attribute \src "ls180.v:1471.13-1471.36" + wire width 32 \main_interface0_bus_adr + attribute \src "ls180.v:1480.11-1480.34" + wire width 2 \main_interface0_bus_bte + attribute \src "ls180.v:1479.11-1479.34" + wire width 3 \main_interface0_bus_cti + attribute \src "ls180.v:1475.6-1475.29" + wire \main_interface0_bus_cyc + attribute \src "ls180.v:1473.13-1473.38" + wire width 32 \main_interface0_bus_dat_r + attribute \src "ls180.v:1472.13-1472.38" + wire width 32 \main_interface0_bus_dat_w + attribute \src "ls180.v:1481.6-1481.29" + wire \main_interface0_bus_err + attribute \src "ls180.v:1474.12-1474.35" + wire width 4 \main_interface0_bus_sel + attribute \src "ls180.v:1476.6-1476.29" + wire \main_interface0_bus_stb + attribute \src "ls180.v:1478.6-1478.28" + wire \main_interface0_bus_we + attribute \src "ls180.v:1568.6-1568.29" + wire \main_interface1_bus_ack + attribute \src "ls180.v:1562.12-1562.35" + wire width 32 \main_interface1_bus_adr + attribute \src "ls180.v:1571.11-1571.34" + wire width 2 \main_interface1_bus_bte + attribute \src "ls180.v:1570.11-1570.34" + wire width 3 \main_interface1_bus_cti + attribute \src "ls180.v:1566.5-1566.28" + wire \main_interface1_bus_cyc + attribute \src "ls180.v:1564.13-1564.38" + wire width 32 \main_interface1_bus_dat_r + attribute \src "ls180.v:1563.12-1563.37" + wire width 32 \main_interface1_bus_dat_w + attribute \src "ls180.v:1572.6-1572.29" + wire \main_interface1_bus_err + attribute \src "ls180.v:1565.11-1565.34" + wire width 4 \main_interface1_bus_sel + attribute \src "ls180.v:1567.5-1567.28" + wire \main_interface1_bus_stb + attribute \src "ls180.v:1569.5-1569.27" + wire \main_interface1_bus_we + attribute \src "ls180.v:186.12-186.32" + wire width 7 \main_libresocsim_adr + attribute \src "ls180.v:56.6-56.32" + wire \main_libresocsim_bus_error + attribute \src "ls180.v:57.12-57.39" + wire width 32 \main_libresocsim_bus_errors + attribute \src "ls180.v:53.13-53.47" + wire width 32 \main_libresocsim_bus_errors_status + attribute \src "ls180.v:54.6-54.36" + wire \main_libresocsim_bus_errors_we + attribute \src "ls180.v:142.5-142.40" + wire \main_libresocsim_converter0_counter + attribute \src "ls180.v:1696.5-1696.62" + wire \main_libresocsim_converter0_counter_converter0_next_value + attribute \src "ls180.v:1697.5-1697.65" + wire \main_libresocsim_converter0_counter_converter0_next_value_ce + attribute \src "ls180.v:144.12-144.45" + wire width 64 \main_libresocsim_converter0_dat_r + attribute \src "ls180.v:143.6-143.39" + wire \main_libresocsim_converter0_reset + attribute \src "ls180.v:141.5-141.37" + wire \main_libresocsim_converter0_skip + attribute \src "ls180.v:157.5-157.40" + wire \main_libresocsim_converter1_counter + attribute \src "ls180.v:1700.5-1700.62" + wire \main_libresocsim_converter1_counter_converter1_next_value + attribute \src "ls180.v:1701.5-1701.65" + wire \main_libresocsim_converter1_counter_converter1_next_value_ce + attribute \src "ls180.v:159.12-159.45" + wire width 64 \main_libresocsim_converter1_dat_r + attribute \src "ls180.v:158.6-158.39" + wire \main_libresocsim_converter1_reset + attribute \src "ls180.v:156.5-156.37" + wire \main_libresocsim_converter1_skip + attribute \src "ls180.v:172.5-172.40" + wire \main_libresocsim_converter2_counter + attribute \src "ls180.v:1704.5-1704.62" + wire \main_libresocsim_converter2_counter_converter2_next_value + attribute \src "ls180.v:1705.5-1705.65" + wire \main_libresocsim_converter2_counter_converter2_next_value_ce + attribute \src "ls180.v:174.12-174.45" + wire width 64 \main_libresocsim_converter2_dat_r + attribute \src "ls180.v:173.6-173.39" + wire \main_libresocsim_converter2_reset + attribute \src "ls180.v:171.5-171.37" + wire \main_libresocsim_converter2_skip + attribute \src "ls180.v:187.13-187.35" + wire width 32 \main_libresocsim_dat_r + attribute \src "ls180.v:189.13-189.35" + wire width 32 \main_libresocsim_dat_w + attribute \src "ls180.v:195.5-195.27" + wire \main_libresocsim_en_re + attribute \src "ls180.v:194.5-194.32" + wire \main_libresocsim_en_storage + attribute \src "ls180.v:211.6-211.45" + wire \main_libresocsim_eventmanager_pending_r + attribute \src "ls180.v:210.6-210.46" + wire \main_libresocsim_eventmanager_pending_re + attribute \src "ls180.v:213.6-213.45" + wire \main_libresocsim_eventmanager_pending_w + attribute \src "ls180.v:212.6-212.46" + wire \main_libresocsim_eventmanager_pending_we + attribute \src "ls180.v:215.5-215.37" + wire \main_libresocsim_eventmanager_re + attribute \src "ls180.v:207.6-207.44" + wire \main_libresocsim_eventmanager_status_r + attribute \src "ls180.v:206.6-206.45" + wire \main_libresocsim_eventmanager_status_re + attribute \src "ls180.v:209.6-209.44" + wire \main_libresocsim_eventmanager_status_w + attribute \src "ls180.v:208.6-208.45" + wire \main_libresocsim_eventmanager_status_we + attribute \src "ls180.v:214.5-214.42" + wire \main_libresocsim_eventmanager_storage + attribute \src "ls180.v:136.6-136.57" + wire \main_libresocsim_interface0_converted_interface_ack + attribute \src "ls180.v:130.12-130.63" + wire width 30 \main_libresocsim_interface0_converted_interface_adr + attribute \src "ls180.v:139.11-139.62" + wire width 2 \main_libresocsim_interface0_converted_interface_bte + attribute \src "ls180.v:138.11-138.62" + wire width 3 \main_libresocsim_interface0_converted_interface_cti + attribute \src "ls180.v:134.5-134.56" + wire \main_libresocsim_interface0_converted_interface_cyc + attribute \src "ls180.v:132.13-132.66" + wire width 32 \main_libresocsim_interface0_converted_interface_dat_r + attribute \src "ls180.v:131.12-131.65" + wire width 32 \main_libresocsim_interface0_converted_interface_dat_w + attribute \src "ls180.v:140.6-140.57" + wire \main_libresocsim_interface0_converted_interface_err + attribute \src "ls180.v:133.11-133.62" + wire width 4 \main_libresocsim_interface0_converted_interface_sel + attribute \src "ls180.v:135.5-135.56" + wire \main_libresocsim_interface0_converted_interface_stb + attribute \src "ls180.v:137.5-137.55" + wire \main_libresocsim_interface0_converted_interface_we + attribute \src "ls180.v:151.6-151.57" + wire \main_libresocsim_interface1_converted_interface_ack + attribute \src "ls180.v:145.12-145.63" + wire width 30 \main_libresocsim_interface1_converted_interface_adr + attribute \src "ls180.v:154.11-154.62" + wire width 2 \main_libresocsim_interface1_converted_interface_bte + attribute \src "ls180.v:153.11-153.62" + wire width 3 \main_libresocsim_interface1_converted_interface_cti + attribute \src "ls180.v:149.5-149.56" + wire \main_libresocsim_interface1_converted_interface_cyc + attribute \src "ls180.v:147.13-147.66" + wire width 32 \main_libresocsim_interface1_converted_interface_dat_r + attribute \src "ls180.v:146.12-146.65" + wire width 32 \main_libresocsim_interface1_converted_interface_dat_w + attribute \src "ls180.v:155.6-155.57" + wire \main_libresocsim_interface1_converted_interface_err + attribute \src "ls180.v:148.11-148.62" + wire width 4 \main_libresocsim_interface1_converted_interface_sel + attribute \src "ls180.v:150.5-150.56" + wire \main_libresocsim_interface1_converted_interface_stb + attribute \src "ls180.v:152.5-152.55" + wire \main_libresocsim_interface1_converted_interface_we + attribute \src "ls180.v:166.6-166.57" + wire \main_libresocsim_interface2_converted_interface_ack + attribute \src "ls180.v:160.12-160.63" + wire width 30 \main_libresocsim_interface2_converted_interface_adr + attribute \src "ls180.v:169.11-169.62" + wire width 2 \main_libresocsim_interface2_converted_interface_bte + attribute \src "ls180.v:168.11-168.62" + wire width 3 \main_libresocsim_interface2_converted_interface_cti + attribute \src "ls180.v:164.5-164.56" + wire \main_libresocsim_interface2_converted_interface_cyc + attribute \src "ls180.v:162.13-162.66" + wire width 32 \main_libresocsim_interface2_converted_interface_dat_r + attribute \src "ls180.v:161.12-161.65" + wire width 32 \main_libresocsim_interface2_converted_interface_dat_w + attribute \src "ls180.v:170.6-170.57" + wire \main_libresocsim_interface2_converted_interface_err + attribute \src "ls180.v:163.11-163.62" + wire width 4 \main_libresocsim_interface2_converted_interface_sel + attribute \src "ls180.v:165.5-165.56" + wire \main_libresocsim_interface2_converted_interface_stb + attribute \src "ls180.v:167.5-167.55" + wire \main_libresocsim_interface2_converted_interface_we + attribute \src "ls180.v:200.6-200.26" + wire \main_libresocsim_irq + attribute \src "ls180.v:117.6-117.32" + wire \main_libresocsim_libresoc0 + attribute \src "ls180.v:118.6-118.32" + wire \main_libresocsim_libresoc1 + attribute \src "ls180.v:119.13-119.39" + wire width 64 \main_libresocsim_libresoc2 + attribute \src "ls180.v:122.13-122.65" + wire width 16 \main_libresocsim_libresoc_constraintmanager0_gpio0_i + attribute \src "ls180.v:123.13-123.65" + wire width 16 \main_libresocsim_libresoc_constraintmanager0_gpio0_o + attribute \src "ls180.v:124.13-124.66" + wire width 16 \main_libresocsim_libresoc_constraintmanager0_gpio0_oe + attribute \src "ls180.v:121.6-121.59" + wire \main_libresocsim_libresoc_constraintmanager0_uart0_rx + attribute \src "ls180.v:120.5-120.58" + wire \main_libresocsim_libresoc_constraintmanager0_uart0_tx + attribute \src "ls180.v:127.13-127.65" + wire width 16 \main_libresocsim_libresoc_constraintmanager1_gpio0_i + attribute \src "ls180.v:128.13-128.65" + wire width 16 \main_libresocsim_libresoc_constraintmanager1_gpio0_o + attribute \src "ls180.v:129.13-129.66" + wire width 16 \main_libresocsim_libresoc_constraintmanager1_gpio0_oe + attribute \src "ls180.v:126.6-126.59" + wire \main_libresocsim_libresoc_constraintmanager1_uart0_rx + attribute \src "ls180.v:125.6-125.59" + wire \main_libresocsim_libresoc_constraintmanager1_uart0_tx + attribute \src "ls180.v:66.5-66.39" + wire \main_libresocsim_libresoc_dbus_ack + attribute \src "ls180.v:60.13-60.47" + wire width 29 \main_libresocsim_libresoc_dbus_adr + attribute \src "ls180.v:69.12-69.46" + wire width 2 \main_libresocsim_libresoc_dbus_bte + attribute \src "ls180.v:68.12-68.46" + wire width 3 \main_libresocsim_libresoc_dbus_cti + attribute \src "ls180.v:64.6-64.40" + wire \main_libresocsim_libresoc_dbus_cyc + attribute \src "ls180.v:62.13-62.49" + wire width 64 \main_libresocsim_libresoc_dbus_dat_r + attribute \src "ls180.v:61.13-61.49" + wire width 64 \main_libresocsim_libresoc_dbus_dat_w + attribute \src "ls180.v:70.5-70.39" + wire \main_libresocsim_libresoc_dbus_err + attribute \src "ls180.v:63.12-63.46" + wire width 8 \main_libresocsim_libresoc_dbus_sel + attribute \src "ls180.v:65.6-65.40" + wire \main_libresocsim_libresoc_dbus_stb + attribute \src "ls180.v:67.6-67.39" + wire \main_libresocsim_libresoc_dbus_we + attribute \src "ls180.v:77.5-77.39" + wire \main_libresocsim_libresoc_ibus_ack + attribute \src "ls180.v:71.13-71.47" + wire width 29 \main_libresocsim_libresoc_ibus_adr + attribute \src "ls180.v:80.12-80.46" + wire width 2 \main_libresocsim_libresoc_ibus_bte + attribute \src "ls180.v:79.12-79.46" + wire width 3 \main_libresocsim_libresoc_ibus_cti + attribute \src "ls180.v:75.6-75.40" + wire \main_libresocsim_libresoc_ibus_cyc + attribute \src "ls180.v:73.13-73.49" + wire width 64 \main_libresocsim_libresoc_ibus_dat_r + attribute \src "ls180.v:72.13-72.49" + wire width 64 \main_libresocsim_libresoc_ibus_dat_w + attribute \src "ls180.v:81.5-81.39" + wire \main_libresocsim_libresoc_ibus_err + attribute \src "ls180.v:74.12-74.46" + wire width 8 \main_libresocsim_libresoc_ibus_sel + attribute \src "ls180.v:76.6-76.40" + wire \main_libresocsim_libresoc_ibus_stb + attribute \src "ls180.v:78.6-78.39" + wire \main_libresocsim_libresoc_ibus_we + attribute \src "ls180.v:59.12-59.47" + wire width 16 \main_libresocsim_libresoc_interrupt + attribute \src "ls180.v:113.6-113.40" + wire \main_libresocsim_libresoc_jtag_tck + attribute \src "ls180.v:115.6-115.40" + wire \main_libresocsim_libresoc_jtag_tdi + attribute \src "ls180.v:116.6-116.40" + wire \main_libresocsim_libresoc_jtag_tdo + attribute \src "ls180.v:114.6-114.40" + wire \main_libresocsim_libresoc_jtag_tms + attribute \src "ls180.v:110.5-110.42" + wire \main_libresocsim_libresoc_jtag_wb_ack + attribute \src "ls180.v:104.13-104.50" + wire width 29 \main_libresocsim_libresoc_jtag_wb_adr + attribute \src "ls180.v:108.6-108.43" + wire \main_libresocsim_libresoc_jtag_wb_cyc + attribute \src "ls180.v:106.13-106.52" + wire width 64 \main_libresocsim_libresoc_jtag_wb_dat_r + attribute \src "ls180.v:105.13-105.52" + wire width 64 \main_libresocsim_libresoc_jtag_wb_dat_w + attribute \src "ls180.v:112.5-112.42" + wire \main_libresocsim_libresoc_jtag_wb_err + attribute \src "ls180.v:107.12-107.49" + wire width 8 \main_libresocsim_libresoc_jtag_wb_sel + attribute \src "ls180.v:109.6-109.43" + wire \main_libresocsim_libresoc_jtag_wb_stb + attribute \src "ls180.v:111.6-111.42" + wire \main_libresocsim_libresoc_jtag_wb_we + attribute \src "ls180.v:58.6-58.37" + wire \main_libresocsim_libresoc_reset + attribute \src "ls180.v:88.6-88.44" + wire \main_libresocsim_libresoc_xics_icp_ack + attribute \src "ls180.v:82.13-82.51" + wire width 30 \main_libresocsim_libresoc_xics_icp_adr + attribute \src "ls180.v:91.12-91.50" + wire width 2 \main_libresocsim_libresoc_xics_icp_bte + attribute \src "ls180.v:90.12-90.50" + wire width 3 \main_libresocsim_libresoc_xics_icp_cti + attribute \src "ls180.v:86.6-86.44" + wire \main_libresocsim_libresoc_xics_icp_cyc + attribute \src "ls180.v:84.13-84.53" + wire width 32 \main_libresocsim_libresoc_xics_icp_dat_r + attribute \src "ls180.v:83.13-83.53" + wire width 32 \main_libresocsim_libresoc_xics_icp_dat_w + attribute \src "ls180.v:92.6-92.44" + wire \main_libresocsim_libresoc_xics_icp_err + attribute \src "ls180.v:85.12-85.50" + wire width 4 \main_libresocsim_libresoc_xics_icp_sel + attribute \src "ls180.v:87.6-87.44" + wire \main_libresocsim_libresoc_xics_icp_stb + attribute \src "ls180.v:89.6-89.43" + wire \main_libresocsim_libresoc_xics_icp_we + attribute \src "ls180.v:99.6-99.44" + wire \main_libresocsim_libresoc_xics_ics_ack + attribute \src "ls180.v:93.13-93.51" + wire width 30 \main_libresocsim_libresoc_xics_ics_adr + attribute \src "ls180.v:102.12-102.50" + wire width 2 \main_libresocsim_libresoc_xics_ics_bte + attribute \src "ls180.v:101.12-101.50" + wire width 3 \main_libresocsim_libresoc_xics_ics_cti + attribute \src "ls180.v:97.6-97.44" + wire \main_libresocsim_libresoc_xics_ics_cyc + attribute \src "ls180.v:95.13-95.53" + wire width 32 \main_libresocsim_libresoc_xics_ics_dat_r + attribute \src "ls180.v:94.13-94.53" + wire width 32 \main_libresocsim_libresoc_xics_ics_dat_w + attribute \src "ls180.v:103.6-103.44" + wire \main_libresocsim_libresoc_xics_ics_err + attribute \src "ls180.v:96.12-96.50" + wire width 4 \main_libresocsim_libresoc_xics_ics_sel + attribute \src "ls180.v:98.6-98.44" + wire \main_libresocsim_libresoc_xics_ics_stb + attribute \src "ls180.v:100.6-100.43" + wire \main_libresocsim_libresoc_xics_ics_we + attribute \src "ls180.v:191.5-191.29" + wire \main_libresocsim_load_re + attribute \src "ls180.v:190.12-190.41" + wire width 32 \main_libresocsim_load_storage + attribute \src "ls180.v:181.5-181.33" + wire \main_libresocsim_ram_bus_ack + attribute \src "ls180.v:175.13-175.41" + wire width 30 \main_libresocsim_ram_bus_adr + attribute \src "ls180.v:184.12-184.40" + wire width 2 \main_libresocsim_ram_bus_bte + attribute \src "ls180.v:183.12-183.40" + wire width 3 \main_libresocsim_ram_bus_cti + attribute \src "ls180.v:179.6-179.34" + wire \main_libresocsim_ram_bus_cyc + attribute \src "ls180.v:177.13-177.43" + wire width 32 \main_libresocsim_ram_bus_dat_r + attribute \src "ls180.v:176.13-176.43" + wire width 32 \main_libresocsim_ram_bus_dat_w + attribute \src "ls180.v:185.5-185.33" + wire \main_libresocsim_ram_bus_err + attribute \src "ls180.v:178.12-178.40" + wire width 4 \main_libresocsim_ram_bus_sel + attribute \src "ls180.v:180.6-180.34" + wire \main_libresocsim_ram_bus_stb + attribute \src "ls180.v:182.6-182.33" + wire \main_libresocsim_ram_bus_we + attribute \src "ls180.v:193.5-193.31" + wire \main_libresocsim_reload_re + attribute \src "ls180.v:192.12-192.43" + wire width 32 \main_libresocsim_reload_storage + attribute \src "ls180.v:55.6-55.28" + wire \main_libresocsim_reset + attribute \src "ls180.v:50.5-50.30" + wire \main_libresocsim_reset_re + attribute \src "ls180.v:49.5-49.35" + wire \main_libresocsim_reset_storage + attribute \src "ls180.v:52.5-52.32" + wire \main_libresocsim_scratch_re + attribute \src "ls180.v:51.12-51.44" + wire width 32 \main_libresocsim_scratch_storage + attribute \src "ls180.v:197.5-197.37" + wire \main_libresocsim_update_value_re + attribute \src "ls180.v:196.5-196.42" + wire \main_libresocsim_update_value_storage + attribute \src "ls180.v:216.12-216.34" + wire width 32 \main_libresocsim_value + attribute \src "ls180.v:198.12-198.41" + wire width 32 \main_libresocsim_value_status + attribute \src "ls180.v:199.6-199.31" + wire \main_libresocsim_value_we + attribute \src "ls180.v:188.11-188.30" + wire width 4 \main_libresocsim_we + attribute \src "ls180.v:204.5-204.32" + wire \main_libresocsim_zero_clear + attribute \src "ls180.v:205.5-205.38" + wire \main_libresocsim_zero_old_trigger + attribute \src "ls180.v:202.5-202.34" + wire \main_libresocsim_zero_pending + attribute \src "ls180.v:201.6-201.34" + wire \main_libresocsim_zero_status + attribute \src "ls180.v:203.6-203.35" + wire \main_libresocsim_zero_trigger + attribute \src "ls180.v:798.6-798.26" + wire \main_litedram_wb_ack + attribute \src "ls180.v:792.12-792.32" + wire width 30 \main_litedram_wb_adr + attribute \src "ls180.v:796.5-796.25" + wire \main_litedram_wb_cyc + attribute \src "ls180.v:794.13-794.35" + wire width 16 \main_litedram_wb_dat_r + attribute \src "ls180.v:793.12-793.34" + wire width 16 \main_litedram_wb_dat_w + attribute \src "ls180.v:795.11-795.31" + wire width 2 \main_litedram_wb_sel + attribute \src "ls180.v:797.5-797.25" + wire \main_litedram_wb_stb + attribute \src "ls180.v:799.5-799.24" + wire \main_litedram_wb_we + attribute \src "ls180.v:996.13-996.20" + wire width 42 \main_nc + attribute \src "ls180.v:827.12-827.37" + wire width 32 \main_phase_accumulator_rx + attribute \src "ls180.v:817.12-817.37" + wire width 32 \main_phase_accumulator_tx + attribute \src "ls180.v:771.6-771.24" + wire \main_port_cmd_last + attribute \src "ls180.v:773.13-773.39" + wire width 24 \main_port_cmd_payload_addr + attribute \src "ls180.v:772.6-772.30" + wire \main_port_cmd_payload_we + attribute \src "ls180.v:770.6-770.25" + wire \main_port_cmd_ready + attribute \src "ls180.v:769.6-769.25" + wire \main_port_cmd_valid + attribute \src "ls180.v:768.6-768.21" + wire \main_port_flush + attribute \src "ls180.v:780.13-780.41" + wire width 16 \main_port_rdata_payload_data + attribute \src "ls180.v:779.6-779.27" + wire \main_port_rdata_ready + attribute \src "ls180.v:778.6-778.27" + wire \main_port_rdata_valid + attribute \src "ls180.v:776.13-776.41" + wire width 16 \main_port_wdata_payload_data + attribute \src "ls180.v:777.12-777.38" + wire width 2 \main_port_wdata_payload_we + attribute \src "ls180.v:775.6-775.27" + wire \main_port_wdata_ready + attribute \src "ls180.v:774.6-774.27" + wire \main_port_wdata_valid + attribute \src "ls180.v:1001.12-1001.29" + wire width 32 \main_pwm0_counter + attribute \src "ls180.v:998.6-998.22" + wire \main_pwm0_enable + attribute \src "ls180.v:1003.5-1003.24" + wire \main_pwm0_enable_re + attribute \src "ls180.v:1002.5-1002.29" + wire \main_pwm0_enable_storage + attribute \src "ls180.v:1000.13-1000.29" + wire width 32 \main_pwm0_period + attribute \src "ls180.v:1007.5-1007.24" + wire \main_pwm0_period_re + attribute \src "ls180.v:1006.12-1006.36" + wire width 32 \main_pwm0_period_storage + attribute \src "ls180.v:999.13-999.28" + wire width 32 \main_pwm0_width + attribute \src "ls180.v:1005.5-1005.23" + wire \main_pwm0_width_re + attribute \src "ls180.v:1004.12-1004.35" + wire width 32 \main_pwm0_width_storage + attribute \src "ls180.v:1011.12-1011.29" + wire width 32 \main_pwm1_counter + attribute \src "ls180.v:1008.6-1008.22" + wire \main_pwm1_enable + attribute \src "ls180.v:1013.5-1013.24" + wire \main_pwm1_enable_re + attribute \src "ls180.v:1012.5-1012.29" + wire \main_pwm1_enable_storage + attribute \src "ls180.v:1010.13-1010.29" + wire width 32 \main_pwm1_period + attribute \src "ls180.v:1017.5-1017.24" + wire \main_pwm1_period_re + attribute \src "ls180.v:1016.12-1016.36" + wire width 32 \main_pwm1_period_storage + attribute \src "ls180.v:1009.13-1009.28" + wire width 32 \main_pwm1_width + attribute \src "ls180.v:1015.5-1015.23" + wire \main_pwm1_width_re + attribute \src "ls180.v:1014.12-1014.35" + wire width 32 \main_pwm1_width_storage + attribute \src "ls180.v:237.11-237.25" + wire width 3 \main_rddata_en + attribute \src "ls180.v:810.5-810.12" + wire \main_re + attribute \src "ls180.v:828.6-828.13" + wire \main_rx + attribute \src "ls180.v:831.11-831.27" + wire width 4 \main_rx_bitcount + attribute \src "ls180.v:832.5-832.17" + wire \main_rx_busy + attribute \src "ls180.v:829.5-829.14" + wire \main_rx_r + attribute \src "ls180.v:830.11-830.22" + wire width 8 \main_rx_reg + attribute \src "ls180.v:1531.11-1531.43" + wire width 2 \main_sdblock2mem_converter_demux + attribute \src "ls180.v:1532.6-1532.42" + wire \main_sdblock2mem_converter_load_part + attribute \src "ls180.v:1522.6-1522.43" + wire \main_sdblock2mem_converter_sink_first + attribute \src "ls180.v:1523.6-1523.42" + wire \main_sdblock2mem_converter_sink_last + attribute \src "ls180.v:1524.12-1524.56" + wire width 8 \main_sdblock2mem_converter_sink_payload_data + attribute \src "ls180.v:1521.6-1521.43" + wire \main_sdblock2mem_converter_sink_ready + attribute \src "ls180.v:1520.6-1520.43" + wire \main_sdblock2mem_converter_sink_valid + attribute \src "ls180.v:1527.5-1527.44" + wire \main_sdblock2mem_converter_source_first + attribute \src "ls180.v:1528.5-1528.43" + wire \main_sdblock2mem_converter_source_last + attribute \src "ls180.v:1529.12-1529.58" + wire width 32 \main_sdblock2mem_converter_source_payload_data + attribute \src "ls180.v:1530.11-1530.70" + wire width 3 \main_sdblock2mem_converter_source_payload_valid_token_count + attribute \src "ls180.v:1526.6-1526.45" + wire \main_sdblock2mem_converter_source_ready + attribute \src "ls180.v:1525.6-1525.45" + wire \main_sdblock2mem_converter_source_valid + attribute \src "ls180.v:1533.5-1533.42" + wire \main_sdblock2mem_converter_strobe_all + attribute \src "ls180.v:1506.11-1506.40" + wire width 5 \main_sdblock2mem_fifo_consume + attribute \src "ls180.v:1511.6-1511.35" + wire \main_sdblock2mem_fifo_do_read + attribute \src "ls180.v:1515.6-1515.41" + wire \main_sdblock2mem_fifo_fifo_in_first + attribute \src "ls180.v:1516.6-1516.40" + wire \main_sdblock2mem_fifo_fifo_in_last + attribute \src "ls180.v:1514.12-1514.54" + wire width 8 \main_sdblock2mem_fifo_fifo_in_payload_data + attribute \src "ls180.v:1518.6-1518.42" + wire \main_sdblock2mem_fifo_fifo_out_first + attribute \src "ls180.v:1519.6-1519.41" + wire \main_sdblock2mem_fifo_fifo_out_last + attribute \src "ls180.v:1517.12-1517.55" + wire width 8 \main_sdblock2mem_fifo_fifo_out_payload_data + attribute \src "ls180.v:1503.11-1503.38" + wire width 6 \main_sdblock2mem_fifo_level + attribute \src "ls180.v:1505.11-1505.40" + wire width 5 \main_sdblock2mem_fifo_produce + attribute \src "ls180.v:1512.12-1512.44" + wire width 5 \main_sdblock2mem_fifo_rdport_adr + attribute \src "ls180.v:1513.12-1513.46" + wire width 10 \main_sdblock2mem_fifo_rdport_dat_r + attribute \src "ls180.v:1504.5-1504.34" + wire \main_sdblock2mem_fifo_replace + attribute \src "ls180.v:1489.6-1489.38" + wire \main_sdblock2mem_fifo_sink_first + attribute \src "ls180.v:1490.6-1490.37" + wire \main_sdblock2mem_fifo_sink_last + attribute \src "ls180.v:1491.12-1491.51" + wire width 8 \main_sdblock2mem_fifo_sink_payload_data + attribute \src "ls180.v:1488.6-1488.38" + wire \main_sdblock2mem_fifo_sink_ready + attribute \src "ls180.v:1487.6-1487.38" + wire \main_sdblock2mem_fifo_sink_valid + attribute \src "ls180.v:1494.6-1494.40" + wire \main_sdblock2mem_fifo_source_first + attribute \src "ls180.v:1495.6-1495.39" + wire \main_sdblock2mem_fifo_source_last + attribute \src "ls180.v:1496.12-1496.53" + wire width 8 \main_sdblock2mem_fifo_source_payload_data + attribute \src "ls180.v:1493.6-1493.40" + wire \main_sdblock2mem_fifo_source_ready + attribute \src "ls180.v:1492.6-1492.40" + wire \main_sdblock2mem_fifo_source_valid + attribute \src "ls180.v:1501.12-1501.46" + wire width 10 \main_sdblock2mem_fifo_syncfifo_din + attribute \src "ls180.v:1502.12-1502.47" + wire width 10 \main_sdblock2mem_fifo_syncfifo_dout + attribute \src "ls180.v:1499.6-1499.39" + wire \main_sdblock2mem_fifo_syncfifo_re + attribute \src "ls180.v:1500.6-1500.45" + wire \main_sdblock2mem_fifo_syncfifo_readable + attribute \src "ls180.v:1497.6-1497.39" + wire \main_sdblock2mem_fifo_syncfifo_we + attribute \src "ls180.v:1498.6-1498.45" + wire \main_sdblock2mem_fifo_syncfifo_writable + attribute \src "ls180.v:1507.11-1507.43" + wire width 5 \main_sdblock2mem_fifo_wrport_adr + attribute \src "ls180.v:1508.12-1508.46" + wire width 10 \main_sdblock2mem_fifo_wrport_dat_r + attribute \src "ls180.v:1510.12-1510.46" + wire width 10 \main_sdblock2mem_fifo_wrport_dat_w + attribute \src "ls180.v:1509.6-1509.37" + wire \main_sdblock2mem_fifo_wrport_we + attribute \src "ls180.v:1484.6-1484.38" + wire \main_sdblock2mem_sink_sink_first + attribute \src "ls180.v:1485.6-1485.37" + wire \main_sdblock2mem_sink_sink_last + attribute \src "ls180.v:1541.12-1541.54" + wire width 32 \main_sdblock2mem_sink_sink_payload_address + attribute \src "ls180.v:1486.12-1486.52" + wire width 8 \main_sdblock2mem_sink_sink_payload_data0 + attribute \src "ls180.v:1542.12-1542.52" + wire width 32 \main_sdblock2mem_sink_sink_payload_data1 + attribute \src "ls180.v:1483.6-1483.39" + wire \main_sdblock2mem_sink_sink_ready0 + attribute \src "ls180.v:1540.6-1540.39" + wire \main_sdblock2mem_sink_sink_ready1 + attribute \src "ls180.v:1482.6-1482.39" + wire \main_sdblock2mem_sink_sink_valid0 + attribute \src "ls180.v:1539.5-1539.38" + wire \main_sdblock2mem_sink_sink_valid1 + attribute \src "ls180.v:1536.6-1536.42" + wire \main_sdblock2mem_source_source_first + attribute \src "ls180.v:1537.6-1537.41" + wire \main_sdblock2mem_source_source_last + attribute \src "ls180.v:1538.13-1538.56" + wire width 32 \main_sdblock2mem_source_source_payload_data + attribute \src "ls180.v:1535.6-1535.42" + wire \main_sdblock2mem_source_source_ready + attribute \src "ls180.v:1534.6-1534.42" + wire \main_sdblock2mem_source_source_valid + attribute \src "ls180.v:1558.13-1558.52" + wire width 32 \main_sdblock2mem_wishbonedmawriter_base + attribute \src "ls180.v:1549.5-1549.47" + wire \main_sdblock2mem_wishbonedmawriter_base_re + attribute \src "ls180.v:1548.12-1548.59" + wire width 64 \main_sdblock2mem_wishbonedmawriter_base_storage + attribute \src "ls180.v:1553.5-1553.49" + wire \main_sdblock2mem_wishbonedmawriter_enable_re + attribute \src "ls180.v:1552.5-1552.54" + wire \main_sdblock2mem_wishbonedmawriter_enable_storage + attribute \src "ls180.v:1560.13-1560.54" + wire width 32 \main_sdblock2mem_wishbonedmawriter_length + attribute \src "ls180.v:1551.5-1551.49" + wire \main_sdblock2mem_wishbonedmawriter_length_re + attribute \src "ls180.v:1550.12-1550.61" + wire width 32 \main_sdblock2mem_wishbonedmawriter_length_storage + attribute \src "ls180.v:1557.5-1557.47" + wire \main_sdblock2mem_wishbonedmawriter_loop_re + attribute \src "ls180.v:1556.5-1556.52" + wire \main_sdblock2mem_wishbonedmawriter_loop_storage + attribute \src "ls180.v:1559.12-1559.53" + wire width 32 \main_sdblock2mem_wishbonedmawriter_offset + attribute \src "ls180.v:1813.12-1813.79" + wire width 32 \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value + attribute \src "ls180.v:1814.5-1814.75" + wire \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce + attribute \src "ls180.v:1561.6-1561.46" + wire \main_sdblock2mem_wishbonedmawriter_reset + attribute \src "ls180.v:1545.6-1545.51" + wire \main_sdblock2mem_wishbonedmawriter_sink_first + attribute \src "ls180.v:1546.6-1546.50" + wire \main_sdblock2mem_wishbonedmawriter_sink_last + attribute \src "ls180.v:1547.13-1547.65" + wire width 32 \main_sdblock2mem_wishbonedmawriter_sink_payload_data + attribute \src "ls180.v:1544.5-1544.50" + wire \main_sdblock2mem_wishbonedmawriter_sink_ready + attribute \src "ls180.v:1543.6-1543.51" + wire \main_sdblock2mem_wishbonedmawriter_sink_valid + attribute \src "ls180.v:1554.5-1554.46" + wire \main_sdblock2mem_wishbonedmawriter_status + attribute \src "ls180.v:1555.6-1555.43" + wire \main_sdblock2mem_wishbonedmawriter_we + attribute \src "ls180.v:1323.5-1323.31" + wire \main_sdcore_block_count_re + attribute \src "ls180.v:1322.12-1322.43" + wire width 32 \main_sdcore_block_count_storage + attribute \src "ls180.v:1321.5-1321.32" + wire \main_sdcore_block_length_re + attribute \src "ls180.v:1320.11-1320.43" + wire width 10 \main_sdcore_block_length_storage + attribute \src "ls180.v:1307.5-1307.32" + wire \main_sdcore_cmd_argument_re + attribute \src "ls180.v:1306.12-1306.44" + wire width 32 \main_sdcore_cmd_argument_storage + attribute \src "ls180.v:1309.5-1309.31" + wire \main_sdcore_cmd_command_re + attribute \src "ls180.v:1308.12-1308.43" + wire width 32 \main_sdcore_cmd_command_storage + attribute \src "ls180.v:1462.11-1462.32" + wire width 3 \main_sdcore_cmd_count + attribute \src "ls180.v:1797.11-1797.55" + wire width 3 \main_sdcore_cmd_count_sdcore_fsm_next_value2 + attribute \src "ls180.v:1798.5-1798.52" + wire \main_sdcore_cmd_count_sdcore_fsm_next_value_ce2 + attribute \src "ls180.v:1463.5-1463.25" + wire \main_sdcore_cmd_done + attribute \src "ls180.v:1793.5-1793.48" + wire \main_sdcore_cmd_done_sdcore_fsm_next_value0 + attribute \src "ls180.v:1794.5-1794.51" + wire \main_sdcore_cmd_done_sdcore_fsm_next_value_ce0 + attribute \src "ls180.v:1464.5-1464.26" + wire \main_sdcore_cmd_error + attribute \src "ls180.v:1801.5-1801.49" + wire \main_sdcore_cmd_error_sdcore_fsm_next_value4 + attribute \src "ls180.v:1802.5-1802.52" + wire \main_sdcore_cmd_error_sdcore_fsm_next_value_ce4 + attribute \src "ls180.v:1316.12-1316.40" + wire width 4 \main_sdcore_cmd_event_status + attribute \src "ls180.v:1317.6-1317.30" + wire \main_sdcore_cmd_event_we + attribute \src "ls180.v:1314.13-1314.44" + wire width 128 \main_sdcore_cmd_response_status + attribute \src "ls180.v:1809.13-1809.67" + wire width 128 \main_sdcore_cmd_response_status_sdcore_fsm_next_value8 + attribute \src "ls180.v:1810.5-1810.62" + wire \main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8 + attribute \src "ls180.v:1315.6-1315.33" + wire \main_sdcore_cmd_response_we + attribute \src "ls180.v:1311.6-1311.28" + wire \main_sdcore_cmd_send_r + attribute \src "ls180.v:1310.6-1310.29" + wire \main_sdcore_cmd_send_re + attribute \src "ls180.v:1313.5-1313.27" + wire \main_sdcore_cmd_send_w + attribute \src "ls180.v:1312.6-1312.29" + wire \main_sdcore_cmd_send_we + attribute \src "ls180.v:1465.5-1465.28" + wire \main_sdcore_cmd_timeout + attribute \src "ls180.v:1803.5-1803.51" + wire \main_sdcore_cmd_timeout_sdcore_fsm_next_value5 + attribute \src "ls180.v:1804.5-1804.54" + wire \main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5 + attribute \src "ls180.v:1461.12-1461.32" + wire width 2 \main_sdcore_cmd_type + attribute \src "ls180.v:1423.11-1423.40" + wire width 4 \main_sdcore_crc16_checker_cnt + attribute \src "ls180.v:1429.5-1429.39" + wire \main_sdcore_crc16_checker_crc0_clr + attribute \src "ls180.v:1428.12-1428.46" + wire width 16 \main_sdcore_crc16_checker_crc0_crc + attribute \src "ls180.v:1424.12-1424.50" + wire width 16 \main_sdcore_crc16_checker_crc0_crcreg0 + attribute \src "ls180.v:1425.13-1425.51" + wire width 16 \main_sdcore_crc16_checker_crc0_crcreg1 + attribute \src "ls180.v:1426.13-1426.51" + wire width 16 \main_sdcore_crc16_checker_crc0_crcreg2 + attribute \src "ls180.v:1430.6-1430.43" + wire \main_sdcore_crc16_checker_crc0_enable + attribute \src "ls180.v:1427.12-1427.46" + wire width 2 \main_sdcore_crc16_checker_crc0_val + attribute \src "ls180.v:1436.5-1436.39" + wire \main_sdcore_crc16_checker_crc1_clr + attribute \src "ls180.v:1435.12-1435.46" + wire width 16 \main_sdcore_crc16_checker_crc1_crc + attribute \src "ls180.v:1431.12-1431.50" + wire width 16 \main_sdcore_crc16_checker_crc1_crcreg0 + attribute \src "ls180.v:1432.13-1432.51" + wire width 16 \main_sdcore_crc16_checker_crc1_crcreg1 + attribute \src "ls180.v:1433.13-1433.51" + wire width 16 \main_sdcore_crc16_checker_crc1_crcreg2 + attribute \src "ls180.v:1437.6-1437.43" + wire \main_sdcore_crc16_checker_crc1_enable + attribute \src "ls180.v:1434.12-1434.46" + wire width 2 \main_sdcore_crc16_checker_crc1_val + attribute \src "ls180.v:1443.5-1443.39" + wire \main_sdcore_crc16_checker_crc2_clr + attribute \src "ls180.v:1442.12-1442.46" + wire width 16 \main_sdcore_crc16_checker_crc2_crc + attribute \src "ls180.v:1438.12-1438.50" + wire width 16 \main_sdcore_crc16_checker_crc2_crcreg0 + attribute \src "ls180.v:1439.13-1439.51" + wire width 16 \main_sdcore_crc16_checker_crc2_crcreg1 + attribute \src "ls180.v:1440.13-1440.51" + wire width 16 \main_sdcore_crc16_checker_crc2_crcreg2 + attribute \src "ls180.v:1444.6-1444.43" + wire \main_sdcore_crc16_checker_crc2_enable + attribute \src "ls180.v:1441.12-1441.46" + wire width 2 \main_sdcore_crc16_checker_crc2_val + attribute \src "ls180.v:1450.5-1450.39" + wire \main_sdcore_crc16_checker_crc3_clr + attribute \src "ls180.v:1449.12-1449.46" + wire width 16 \main_sdcore_crc16_checker_crc3_crc + attribute \src "ls180.v:1445.12-1445.50" + wire width 16 \main_sdcore_crc16_checker_crc3_crcreg0 + attribute \src "ls180.v:1446.13-1446.51" + wire width 16 \main_sdcore_crc16_checker_crc3_crcreg1 + attribute \src "ls180.v:1447.13-1447.51" + wire width 16 \main_sdcore_crc16_checker_crc3_crcreg2 + attribute \src "ls180.v:1451.6-1451.43" + wire \main_sdcore_crc16_checker_crc3_enable + attribute \src "ls180.v:1448.12-1448.46" + wire width 2 \main_sdcore_crc16_checker_crc3_val + attribute \src "ls180.v:1452.12-1452.45" + wire width 16 \main_sdcore_crc16_checker_crctmp0 + attribute \src "ls180.v:1453.12-1453.45" + wire width 16 \main_sdcore_crc16_checker_crctmp1 + attribute \src "ls180.v:1454.12-1454.45" + wire width 16 \main_sdcore_crc16_checker_crctmp2 + attribute \src "ls180.v:1455.12-1455.45" + wire width 16 \main_sdcore_crc16_checker_crctmp3 + attribute \src "ls180.v:1457.12-1457.43" + wire width 16 \main_sdcore_crc16_checker_fifo0 + attribute \src "ls180.v:1458.12-1458.43" + wire width 16 \main_sdcore_crc16_checker_fifo1 + attribute \src "ls180.v:1459.12-1459.43" + wire width 16 \main_sdcore_crc16_checker_fifo2 + attribute \src "ls180.v:1460.12-1460.43" + wire width 16 \main_sdcore_crc16_checker_fifo3 + attribute \src "ls180.v:1414.5-1414.41" + wire \main_sdcore_crc16_checker_sink_first + attribute \src "ls180.v:1415.5-1415.40" + wire \main_sdcore_crc16_checker_sink_last + attribute \src "ls180.v:1416.11-1416.54" + wire width 8 \main_sdcore_crc16_checker_sink_payload_data + attribute \src "ls180.v:1413.5-1413.41" + wire \main_sdcore_crc16_checker_sink_ready + attribute \src "ls180.v:1412.5-1412.41" + wire \main_sdcore_crc16_checker_sink_valid + attribute \src "ls180.v:1419.5-1419.43" + wire \main_sdcore_crc16_checker_source_first + attribute \src "ls180.v:1420.6-1420.43" + wire \main_sdcore_crc16_checker_source_last + attribute \src "ls180.v:1421.12-1421.57" + wire width 8 \main_sdcore_crc16_checker_source_payload_data + attribute \src "ls180.v:1418.6-1418.44" + wire \main_sdcore_crc16_checker_source_ready + attribute \src "ls180.v:1417.5-1417.43" + wire \main_sdcore_crc16_checker_source_valid + attribute \src "ls180.v:1422.11-1422.40" + wire width 8 \main_sdcore_crc16_checker_val + attribute \src "ls180.v:1456.5-1456.36" + wire \main_sdcore_crc16_checker_valid + attribute \src "ls180.v:1379.11-1379.41" + wire width 3 \main_sdcore_crc16_inserter_cnt + attribute \src "ls180.v:1789.11-1789.80" + wire width 3 \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4 + attribute \src "ls180.v:1790.5-1790.77" + wire \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4 + attribute \src "ls180.v:1385.6-1385.41" + wire \main_sdcore_crc16_inserter_crc0_clr + attribute \src "ls180.v:1384.12-1384.47" + wire width 16 \main_sdcore_crc16_inserter_crc0_crc + attribute \src "ls180.v:1380.12-1380.51" + wire width 16 \main_sdcore_crc16_inserter_crc0_crcreg0 + attribute \src "ls180.v:1381.13-1381.52" + wire width 16 \main_sdcore_crc16_inserter_crc0_crcreg1 + attribute \src "ls180.v:1382.13-1382.52" + wire width 16 \main_sdcore_crc16_inserter_crc0_crcreg2 + attribute \src "ls180.v:1386.6-1386.44" + wire \main_sdcore_crc16_inserter_crc0_enable + attribute \src "ls180.v:1383.12-1383.47" + wire width 2 \main_sdcore_crc16_inserter_crc0_val + attribute \src "ls180.v:1392.6-1392.41" + wire \main_sdcore_crc16_inserter_crc1_clr + attribute \src "ls180.v:1391.12-1391.47" + wire width 16 \main_sdcore_crc16_inserter_crc1_crc + attribute \src "ls180.v:1387.12-1387.51" + wire width 16 \main_sdcore_crc16_inserter_crc1_crcreg0 + attribute \src "ls180.v:1388.13-1388.52" + wire width 16 \main_sdcore_crc16_inserter_crc1_crcreg1 + attribute \src "ls180.v:1389.13-1389.52" + wire width 16 \main_sdcore_crc16_inserter_crc1_crcreg2 + attribute \src "ls180.v:1393.6-1393.44" + wire \main_sdcore_crc16_inserter_crc1_enable + attribute \src "ls180.v:1390.12-1390.47" + wire width 2 \main_sdcore_crc16_inserter_crc1_val + attribute \src "ls180.v:1399.6-1399.41" + wire \main_sdcore_crc16_inserter_crc2_clr + attribute \src "ls180.v:1398.12-1398.47" + wire width 16 \main_sdcore_crc16_inserter_crc2_crc + attribute \src "ls180.v:1394.12-1394.51" + wire width 16 \main_sdcore_crc16_inserter_crc2_crcreg0 + attribute \src "ls180.v:1395.13-1395.52" + wire width 16 \main_sdcore_crc16_inserter_crc2_crcreg1 + attribute \src "ls180.v:1396.13-1396.52" + wire width 16 \main_sdcore_crc16_inserter_crc2_crcreg2 + attribute \src "ls180.v:1400.6-1400.44" + wire \main_sdcore_crc16_inserter_crc2_enable + attribute \src "ls180.v:1397.12-1397.47" + wire width 2 \main_sdcore_crc16_inserter_crc2_val + attribute \src "ls180.v:1406.6-1406.41" + wire \main_sdcore_crc16_inserter_crc3_clr + attribute \src "ls180.v:1405.12-1405.47" + wire width 16 \main_sdcore_crc16_inserter_crc3_crc + attribute \src "ls180.v:1401.12-1401.51" + wire width 16 \main_sdcore_crc16_inserter_crc3_crcreg0 + attribute \src "ls180.v:1402.13-1402.52" + wire width 16 \main_sdcore_crc16_inserter_crc3_crcreg1 + attribute \src "ls180.v:1403.13-1403.52" + wire width 16 \main_sdcore_crc16_inserter_crc3_crcreg2 + attribute \src "ls180.v:1407.6-1407.44" + wire \main_sdcore_crc16_inserter_crc3_enable + attribute \src "ls180.v:1404.12-1404.47" + wire width 2 \main_sdcore_crc16_inserter_crc3_val + attribute \src "ls180.v:1408.12-1408.46" + wire width 16 \main_sdcore_crc16_inserter_crctmp0 + attribute \src "ls180.v:1781.12-1781.85" + wire width 16 \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0 + attribute \src "ls180.v:1782.5-1782.81" + wire \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0 + attribute \src "ls180.v:1409.12-1409.46" + wire width 16 \main_sdcore_crc16_inserter_crctmp1 + attribute \src "ls180.v:1783.12-1783.85" + wire width 16 \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1 + attribute \src "ls180.v:1784.5-1784.81" + wire \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1 + attribute \src "ls180.v:1410.12-1410.46" + wire width 16 \main_sdcore_crc16_inserter_crctmp2 + attribute \src "ls180.v:1785.12-1785.85" + wire width 16 \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2 + attribute \src "ls180.v:1786.5-1786.81" + wire \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2 + attribute \src "ls180.v:1411.12-1411.46" + wire width 16 \main_sdcore_crc16_inserter_crctmp3 + attribute \src "ls180.v:1787.12-1787.85" + wire width 16 \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3 + attribute \src "ls180.v:1788.5-1788.81" + wire \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3 + attribute \src "ls180.v:1371.6-1371.43" + wire \main_sdcore_crc16_inserter_sink_first + attribute \src "ls180.v:1372.6-1372.42" + wire \main_sdcore_crc16_inserter_sink_last + attribute \src "ls180.v:1373.12-1373.56" + wire width 8 \main_sdcore_crc16_inserter_sink_payload_data + attribute \src "ls180.v:1370.5-1370.42" + wire \main_sdcore_crc16_inserter_sink_ready + attribute \src "ls180.v:1369.6-1369.43" + wire \main_sdcore_crc16_inserter_sink_valid + attribute \src "ls180.v:1376.5-1376.44" + wire \main_sdcore_crc16_inserter_source_first + attribute \src "ls180.v:1377.5-1377.43" + wire \main_sdcore_crc16_inserter_source_last + attribute \src "ls180.v:1378.11-1378.57" + wire width 8 \main_sdcore_crc16_inserter_source_payload_data + attribute \src "ls180.v:1375.5-1375.44" + wire \main_sdcore_crc16_inserter_source_ready + attribute \src "ls180.v:1374.5-1374.44" + wire \main_sdcore_crc16_inserter_source_valid + attribute \src "ls180.v:1367.6-1367.35" + wire \main_sdcore_crc7_inserter_clr + attribute \src "ls180.v:1366.11-1366.40" + wire width 7 \main_sdcore_crc7_inserter_crc + attribute \src "ls180.v:1324.11-1324.44" + wire width 7 \main_sdcore_crc7_inserter_crcreg0 + attribute \src "ls180.v:1325.12-1325.45" + wire width 7 \main_sdcore_crc7_inserter_crcreg1 + attribute \src "ls180.v:1334.12-1334.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg10 + attribute \src "ls180.v:1335.12-1335.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg11 + attribute \src "ls180.v:1336.12-1336.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg12 + attribute \src "ls180.v:1337.12-1337.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg13 + attribute \src "ls180.v:1338.12-1338.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg14 + attribute \src "ls180.v:1339.12-1339.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg15 + attribute \src "ls180.v:1340.12-1340.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg16 + attribute \src "ls180.v:1341.12-1341.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg17 + attribute \src "ls180.v:1342.12-1342.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg18 + attribute \src "ls180.v:1343.12-1343.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg19 + attribute \src "ls180.v:1326.12-1326.45" + wire width 7 \main_sdcore_crc7_inserter_crcreg2 + attribute \src "ls180.v:1344.12-1344.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg20 + attribute \src "ls180.v:1345.12-1345.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg21 + attribute \src "ls180.v:1346.12-1346.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg22 + attribute \src "ls180.v:1347.12-1347.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg23 + attribute \src "ls180.v:1348.12-1348.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg24 + attribute \src "ls180.v:1349.12-1349.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg25 + attribute \src "ls180.v:1350.12-1350.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg26 + attribute \src "ls180.v:1351.12-1351.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg27 + attribute \src "ls180.v:1352.12-1352.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg28 + attribute \src "ls180.v:1353.12-1353.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg29 + attribute \src "ls180.v:1327.12-1327.45" + wire width 7 \main_sdcore_crc7_inserter_crcreg3 + attribute \src "ls180.v:1354.12-1354.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg30 + attribute \src "ls180.v:1355.12-1355.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg31 + attribute \src "ls180.v:1356.12-1356.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg32 + attribute \src "ls180.v:1357.12-1357.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg33 + attribute \src "ls180.v:1358.12-1358.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg34 + attribute \src "ls180.v:1359.12-1359.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg35 + attribute \src "ls180.v:1360.12-1360.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg36 + attribute \src "ls180.v:1361.12-1361.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg37 + attribute \src "ls180.v:1362.12-1362.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg38 + attribute \src "ls180.v:1363.12-1363.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg39 + attribute \src "ls180.v:1328.12-1328.45" + wire width 7 \main_sdcore_crc7_inserter_crcreg4 + attribute \src "ls180.v:1364.12-1364.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg40 + attribute \src "ls180.v:1329.12-1329.45" + wire width 7 \main_sdcore_crc7_inserter_crcreg5 + attribute \src "ls180.v:1330.12-1330.45" + wire width 7 \main_sdcore_crc7_inserter_crcreg6 + attribute \src "ls180.v:1331.12-1331.45" + wire width 7 \main_sdcore_crc7_inserter_crcreg7 + attribute \src "ls180.v:1332.12-1332.45" + wire width 7 \main_sdcore_crc7_inserter_crcreg8 + attribute \src "ls180.v:1333.12-1333.45" + wire width 7 \main_sdcore_crc7_inserter_crcreg9 + attribute \src "ls180.v:1368.6-1368.38" + wire \main_sdcore_crc7_inserter_enable + attribute \src "ls180.v:1365.13-1365.42" + wire width 40 \main_sdcore_crc7_inserter_val + attribute \src "ls180.v:1467.12-1467.34" + wire width 32 \main_sdcore_data_count + attribute \src "ls180.v:1799.12-1799.57" + wire width 32 \main_sdcore_data_count_sdcore_fsm_next_value3 + attribute \src "ls180.v:1800.5-1800.53" + wire \main_sdcore_data_count_sdcore_fsm_next_value_ce3 + attribute \src "ls180.v:1468.5-1468.26" + wire \main_sdcore_data_done + attribute \src "ls180.v:1795.5-1795.49" + wire \main_sdcore_data_done_sdcore_fsm_next_value1 + attribute \src "ls180.v:1796.5-1796.52" + wire \main_sdcore_data_done_sdcore_fsm_next_value_ce1 + attribute \src "ls180.v:1469.5-1469.27" + wire \main_sdcore_data_error + attribute \src "ls180.v:1805.5-1805.50" + wire \main_sdcore_data_error_sdcore_fsm_next_value6 + attribute \src "ls180.v:1806.5-1806.53" + wire \main_sdcore_data_error_sdcore_fsm_next_value_ce6 + attribute \src "ls180.v:1318.12-1318.41" + wire width 4 \main_sdcore_data_event_status + attribute \src "ls180.v:1319.6-1319.31" + wire \main_sdcore_data_event_we + attribute \src "ls180.v:1470.5-1470.29" + wire \main_sdcore_data_timeout + attribute \src "ls180.v:1807.5-1807.52" + wire \main_sdcore_data_timeout_sdcore_fsm_next_value7 + attribute \src "ls180.v:1808.5-1808.55" + wire \main_sdcore_data_timeout_sdcore_fsm_next_value_ce7 + attribute \src "ls180.v:1466.12-1466.33" + wire width 2 \main_sdcore_data_type + attribute \src "ls180.v:1298.6-1298.33" + wire \main_sdcore_sink_sink_first + attribute \src "ls180.v:1299.6-1299.32" + wire \main_sdcore_sink_sink_last + attribute \src "ls180.v:1300.12-1300.46" + wire width 8 \main_sdcore_sink_sink_payload_data + attribute \src "ls180.v:1297.6-1297.33" + wire \main_sdcore_sink_sink_ready + attribute \src "ls180.v:1296.6-1296.33" + wire \main_sdcore_sink_sink_valid + attribute \src "ls180.v:1303.6-1303.37" + wire \main_sdcore_source_source_first + attribute \src "ls180.v:1304.6-1304.36" + wire \main_sdcore_source_source_last + attribute \src "ls180.v:1305.12-1305.50" + wire width 8 \main_sdcore_source_source_payload_data + attribute \src "ls180.v:1302.6-1302.37" + wire \main_sdcore_source_source_ready + attribute \src "ls180.v:1301.6-1301.37" + wire \main_sdcore_source_source_valid + attribute \src "ls180.v:1616.6-1616.38" + wire \main_sdmem2block_converter_first + attribute \src "ls180.v:1617.6-1617.37" + wire \main_sdmem2block_converter_last + attribute \src "ls180.v:1615.11-1615.41" + wire width 2 \main_sdmem2block_converter_mux + attribute \src "ls180.v:1606.6-1606.43" + wire \main_sdmem2block_converter_sink_first + attribute \src "ls180.v:1607.6-1607.42" + wire \main_sdmem2block_converter_sink_last + attribute \src "ls180.v:1608.13-1608.57" + wire width 32 \main_sdmem2block_converter_sink_payload_data + attribute \src "ls180.v:1605.6-1605.43" + wire \main_sdmem2block_converter_sink_ready + attribute \src "ls180.v:1604.6-1604.43" + wire \main_sdmem2block_converter_sink_valid + attribute \src "ls180.v:1611.6-1611.45" + wire \main_sdmem2block_converter_source_first + attribute \src "ls180.v:1612.6-1612.44" + wire \main_sdmem2block_converter_source_last + attribute \src "ls180.v:1613.11-1613.57" + wire width 8 \main_sdmem2block_converter_source_payload_data + attribute \src "ls180.v:1614.6-1614.65" + wire \main_sdmem2block_converter_source_payload_valid_token_count + attribute \src "ls180.v:1610.6-1610.45" + wire \main_sdmem2block_converter_source_ready + attribute \src "ls180.v:1609.6-1609.45" + wire \main_sdmem2block_converter_source_valid + attribute \src "ls180.v:1600.13-1600.38" + wire width 32 \main_sdmem2block_dma_base + attribute \src "ls180.v:1589.5-1589.33" + wire \main_sdmem2block_dma_base_re + attribute \src "ls180.v:1588.12-1588.45" + wire width 64 \main_sdmem2block_dma_base_storage + attribute \src "ls180.v:1587.12-1587.37" + wire width 32 \main_sdmem2block_dma_data + attribute \src "ls180.v:1817.12-1817.67" + wire width 32 \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value + attribute \src "ls180.v:1818.5-1818.63" + wire \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce + attribute \src "ls180.v:1594.5-1594.37" + wire \main_sdmem2block_dma_done_status + attribute \src "ls180.v:1595.6-1595.34" + wire \main_sdmem2block_dma_done_we + attribute \src "ls180.v:1593.5-1593.35" + wire \main_sdmem2block_dma_enable_re + attribute \src "ls180.v:1592.5-1592.40" + wire \main_sdmem2block_dma_enable_storage + attribute \src "ls180.v:1602.13-1602.40" + wire width 32 \main_sdmem2block_dma_length + attribute \src "ls180.v:1591.5-1591.35" + wire \main_sdmem2block_dma_length_re + attribute \src "ls180.v:1590.12-1590.47" + wire width 32 \main_sdmem2block_dma_length_storage + attribute \src "ls180.v:1597.5-1597.33" + wire \main_sdmem2block_dma_loop_re + attribute \src "ls180.v:1596.5-1596.38" + wire \main_sdmem2block_dma_loop_storage + attribute \src "ls180.v:1601.12-1601.39" + wire width 32 \main_sdmem2block_dma_offset + attribute \src "ls180.v:1821.12-1821.79" + wire width 32 \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value + attribute \src "ls180.v:1822.5-1822.75" + wire \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce + attribute \src "ls180.v:1598.13-1598.47" + wire width 32 \main_sdmem2block_dma_offset_status + attribute \src "ls180.v:1599.6-1599.36" + wire \main_sdmem2block_dma_offset_we + attribute \src "ls180.v:1603.6-1603.32" + wire \main_sdmem2block_dma_reset + attribute \src "ls180.v:1580.5-1580.35" + wire \main_sdmem2block_dma_sink_last + attribute \src "ls180.v:1581.12-1581.53" + wire width 32 \main_sdmem2block_dma_sink_payload_address + attribute \src "ls180.v:1579.5-1579.36" + wire \main_sdmem2block_dma_sink_ready + attribute \src "ls180.v:1578.5-1578.36" + wire \main_sdmem2block_dma_sink_valid + attribute \src "ls180.v:1584.5-1584.38" + wire \main_sdmem2block_dma_source_first + attribute \src "ls180.v:1585.5-1585.37" + wire \main_sdmem2block_dma_source_last + attribute \src "ls180.v:1586.12-1586.52" + wire width 32 \main_sdmem2block_dma_source_payload_data + attribute \src "ls180.v:1583.6-1583.39" + wire \main_sdmem2block_dma_source_ready + attribute \src "ls180.v:1582.5-1582.38" + wire \main_sdmem2block_dma_source_valid + attribute \src "ls180.v:1642.11-1642.40" + wire width 5 \main_sdmem2block_fifo_consume + attribute \src "ls180.v:1647.6-1647.35" + wire \main_sdmem2block_fifo_do_read + attribute \src "ls180.v:1651.6-1651.41" + wire \main_sdmem2block_fifo_fifo_in_first + attribute \src "ls180.v:1652.6-1652.40" + wire \main_sdmem2block_fifo_fifo_in_last + attribute \src "ls180.v:1650.12-1650.54" + wire width 8 \main_sdmem2block_fifo_fifo_in_payload_data + attribute \src "ls180.v:1654.6-1654.42" + wire \main_sdmem2block_fifo_fifo_out_first + attribute \src "ls180.v:1655.6-1655.41" + wire \main_sdmem2block_fifo_fifo_out_last + attribute \src "ls180.v:1653.12-1653.55" + wire width 8 \main_sdmem2block_fifo_fifo_out_payload_data + attribute \src "ls180.v:1639.11-1639.38" + wire width 6 \main_sdmem2block_fifo_level + attribute \src "ls180.v:1641.11-1641.40" + wire width 5 \main_sdmem2block_fifo_produce + attribute \src "ls180.v:1648.12-1648.44" + wire width 5 \main_sdmem2block_fifo_rdport_adr + attribute \src "ls180.v:1649.12-1649.46" + wire width 10 \main_sdmem2block_fifo_rdport_dat_r + attribute \src "ls180.v:1640.5-1640.34" + wire \main_sdmem2block_fifo_replace + attribute \src "ls180.v:1625.6-1625.38" + wire \main_sdmem2block_fifo_sink_first + attribute \src "ls180.v:1626.6-1626.37" + wire \main_sdmem2block_fifo_sink_last + attribute \src "ls180.v:1627.12-1627.51" + wire width 8 \main_sdmem2block_fifo_sink_payload_data + attribute \src "ls180.v:1624.6-1624.38" + wire \main_sdmem2block_fifo_sink_ready + attribute \src "ls180.v:1623.6-1623.38" + wire \main_sdmem2block_fifo_sink_valid + attribute \src "ls180.v:1630.6-1630.40" + wire \main_sdmem2block_fifo_source_first + attribute \src "ls180.v:1631.6-1631.39" + wire \main_sdmem2block_fifo_source_last + attribute \src "ls180.v:1632.12-1632.53" + wire width 8 \main_sdmem2block_fifo_source_payload_data + attribute \src "ls180.v:1629.6-1629.40" + wire \main_sdmem2block_fifo_source_ready + attribute \src "ls180.v:1628.6-1628.40" + wire \main_sdmem2block_fifo_source_valid + attribute \src "ls180.v:1637.12-1637.46" + wire width 10 \main_sdmem2block_fifo_syncfifo_din + attribute \src "ls180.v:1638.12-1638.47" + wire width 10 \main_sdmem2block_fifo_syncfifo_dout + attribute \src "ls180.v:1635.6-1635.39" + wire \main_sdmem2block_fifo_syncfifo_re + attribute \src "ls180.v:1636.6-1636.45" + wire \main_sdmem2block_fifo_syncfifo_readable + attribute \src "ls180.v:1633.6-1633.39" + wire \main_sdmem2block_fifo_syncfifo_we + attribute \src "ls180.v:1634.6-1634.45" + wire \main_sdmem2block_fifo_syncfifo_writable + attribute \src "ls180.v:1643.11-1643.43" + wire width 5 \main_sdmem2block_fifo_wrport_adr + attribute \src "ls180.v:1644.12-1644.46" + wire width 10 \main_sdmem2block_fifo_wrport_dat_r + attribute \src "ls180.v:1646.12-1646.46" + wire width 10 \main_sdmem2block_fifo_wrport_dat_w + attribute \src "ls180.v:1645.6-1645.37" + wire \main_sdmem2block_fifo_wrport_we + attribute \src "ls180.v:1575.6-1575.43" + wire \main_sdmem2block_source_source_first0 + attribute \src "ls180.v:1620.6-1620.43" + wire \main_sdmem2block_source_source_first1 + attribute \src "ls180.v:1576.6-1576.42" + wire \main_sdmem2block_source_source_last0 + attribute \src "ls180.v:1621.6-1621.42" + wire \main_sdmem2block_source_source_last1 + attribute \src "ls180.v:1577.12-1577.56" + wire width 8 \main_sdmem2block_source_source_payload_data0 + attribute \src "ls180.v:1622.12-1622.56" + wire width 8 \main_sdmem2block_source_source_payload_data1 + attribute \src "ls180.v:1574.6-1574.43" + wire \main_sdmem2block_source_source_ready0 + attribute \src "ls180.v:1619.6-1619.43" + wire \main_sdmem2block_source_source_ready1 + attribute \src "ls180.v:1573.6-1573.43" + wire \main_sdmem2block_source_source_valid0 + attribute \src "ls180.v:1618.6-1618.43" + wire \main_sdmem2block_source_source_valid1 + attribute \src "ls180.v:1024.6-1024.27" + wire \main_sdphy_clocker_ce + attribute \src "ls180.v:1023.5-1023.28" + wire \main_sdphy_clocker_clk0 + attribute \src "ls180.v:1026.5-1026.28" + wire \main_sdphy_clocker_clk1 + attribute \src "ls180.v:1027.5-1027.29" + wire \main_sdphy_clocker_clk_d + attribute \src "ls180.v:1025.11-1025.34" + wire width 9 \main_sdphy_clocker_clks + attribute \src "ls180.v:1021.5-1021.26" + wire \main_sdphy_clocker_re + attribute \src "ls180.v:1022.6-1022.29" + wire \main_sdphy_clocker_stop + attribute \src "ls180.v:1020.11-1020.37" + wire width 9 \main_sdphy_clocker_storage + attribute \src "ls180.v:1124.6-1124.41" + wire \main_sdphy_cmdr_cmdr_buf_sink_first + attribute \src "ls180.v:1125.6-1125.40" + wire \main_sdphy_cmdr_cmdr_buf_sink_last + attribute \src "ls180.v:1126.12-1126.54" + wire width 8 \main_sdphy_cmdr_cmdr_buf_sink_payload_data + attribute \src "ls180.v:1123.6-1123.41" + wire \main_sdphy_cmdr_cmdr_buf_sink_ready + attribute \src "ls180.v:1122.6-1122.41" + wire \main_sdphy_cmdr_cmdr_buf_sink_valid + attribute \src "ls180.v:1129.5-1129.42" + wire \main_sdphy_cmdr_cmdr_buf_source_first + attribute \src "ls180.v:1130.5-1130.41" + wire \main_sdphy_cmdr_cmdr_buf_source_last + attribute \src "ls180.v:1131.11-1131.55" + wire width 8 \main_sdphy_cmdr_cmdr_buf_source_payload_data + attribute \src "ls180.v:1128.6-1128.43" + wire \main_sdphy_cmdr_cmdr_buf_source_ready + attribute \src "ls180.v:1127.5-1127.42" + wire \main_sdphy_cmdr_cmdr_buf_source_valid + attribute \src "ls180.v:1114.11-1114.47" + wire width 3 \main_sdphy_cmdr_cmdr_converter_demux + attribute \src "ls180.v:1115.6-1115.46" + wire \main_sdphy_cmdr_cmdr_converter_load_part + attribute \src "ls180.v:1105.5-1105.46" + wire \main_sdphy_cmdr_cmdr_converter_sink_first + attribute \src "ls180.v:1106.5-1106.45" + wire \main_sdphy_cmdr_cmdr_converter_sink_last + attribute \src "ls180.v:1107.6-1107.54" + wire \main_sdphy_cmdr_cmdr_converter_sink_payload_data + attribute \src "ls180.v:1104.6-1104.47" + wire \main_sdphy_cmdr_cmdr_converter_sink_ready + attribute \src "ls180.v:1103.6-1103.47" + wire \main_sdphy_cmdr_cmdr_converter_sink_valid + attribute \src "ls180.v:1110.5-1110.48" + wire \main_sdphy_cmdr_cmdr_converter_source_first + attribute \src "ls180.v:1111.5-1111.47" + wire \main_sdphy_cmdr_cmdr_converter_source_last + attribute \src "ls180.v:1112.11-1112.61" + wire width 8 \main_sdphy_cmdr_cmdr_converter_source_payload_data + attribute \src "ls180.v:1113.11-1113.74" + wire width 4 \main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count + attribute \src "ls180.v:1109.6-1109.49" + wire \main_sdphy_cmdr_cmdr_converter_source_ready + attribute \src "ls180.v:1108.6-1108.49" + wire \main_sdphy_cmdr_cmdr_converter_source_valid + attribute \src "ls180.v:1116.5-1116.46" + wire \main_sdphy_cmdr_cmdr_converter_strobe_all + attribute \src "ls180.v:1087.6-1087.40" + wire \main_sdphy_cmdr_cmdr_pads_in_first + attribute \src "ls180.v:1088.6-1088.39" + wire \main_sdphy_cmdr_cmdr_pads_in_last + attribute \src "ls180.v:1089.6-1089.46" + wire \main_sdphy_cmdr_cmdr_pads_in_payload_clk + attribute \src "ls180.v:1090.6-1090.48" + wire \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_i + attribute \src "ls180.v:1091.6-1091.48" + wire \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_o + attribute \src "ls180.v:1092.6-1092.49" + wire \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_oe + attribute \src "ls180.v:1093.12-1093.55" + wire width 4 \main_sdphy_cmdr_cmdr_pads_in_payload_data_i + attribute \src "ls180.v:1094.12-1094.55" + wire width 4 \main_sdphy_cmdr_cmdr_pads_in_payload_data_o + attribute \src "ls180.v:1095.6-1095.50" + wire \main_sdphy_cmdr_cmdr_pads_in_payload_data_oe + attribute \src "ls180.v:1086.5-1086.39" + wire \main_sdphy_cmdr_cmdr_pads_in_ready + attribute \src "ls180.v:1085.6-1085.40" + wire \main_sdphy_cmdr_cmdr_pads_in_valid + attribute \src "ls180.v:1132.5-1132.31" + wire \main_sdphy_cmdr_cmdr_reset + attribute \src "ls180.v:1761.5-1761.59" + wire \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2 + attribute \src "ls180.v:1762.5-1762.62" + wire \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2 + attribute \src "ls180.v:1102.5-1102.29" + wire \main_sdphy_cmdr_cmdr_run + attribute \src "ls180.v:1098.6-1098.47" + wire \main_sdphy_cmdr_cmdr_source_source_first0 + attribute \src "ls180.v:1119.6-1119.47" + wire \main_sdphy_cmdr_cmdr_source_source_first1 + attribute \src "ls180.v:1099.6-1099.46" + wire \main_sdphy_cmdr_cmdr_source_source_last0 + attribute \src "ls180.v:1120.6-1120.46" + wire \main_sdphy_cmdr_cmdr_source_source_last1 + attribute \src "ls180.v:1100.12-1100.60" + wire width 8 \main_sdphy_cmdr_cmdr_source_source_payload_data0 + attribute \src "ls180.v:1121.12-1121.60" + wire width 8 \main_sdphy_cmdr_cmdr_source_source_payload_data1 + attribute \src "ls180.v:1097.5-1097.46" + wire \main_sdphy_cmdr_cmdr_source_source_ready0 + attribute \src "ls180.v:1118.6-1118.47" + wire \main_sdphy_cmdr_cmdr_source_source_ready1 + attribute \src "ls180.v:1096.6-1096.47" + wire \main_sdphy_cmdr_cmdr_source_source_valid0 + attribute \src "ls180.v:1117.6-1117.47" + wire \main_sdphy_cmdr_cmdr_source_source_valid1 + attribute \src "ls180.v:1101.6-1101.32" + wire \main_sdphy_cmdr_cmdr_start + attribute \src "ls180.v:1084.11-1084.32" + wire width 8 \main_sdphy_cmdr_count + attribute \src "ls180.v:1757.11-1757.60" + wire width 8 \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0 + attribute \src "ls180.v:1758.5-1758.57" + wire \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0 + attribute \src "ls180.v:1059.5-1059.42" + wire \main_sdphy_cmdr_pads_in_pads_in_first + attribute \src "ls180.v:1060.5-1060.41" + wire \main_sdphy_cmdr_pads_in_pads_in_last + attribute \src "ls180.v:1061.5-1061.48" + wire \main_sdphy_cmdr_pads_in_pads_in_payload_clk + attribute \src "ls180.v:1062.6-1062.51" + wire \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_i + attribute \src "ls180.v:1063.5-1063.50" + wire \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_o + attribute \src "ls180.v:1064.5-1064.51" + wire \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_oe + attribute \src "ls180.v:1065.12-1065.58" + wire width 4 \main_sdphy_cmdr_pads_in_pads_in_payload_data_i + attribute \src "ls180.v:1066.11-1066.57" + wire width 4 \main_sdphy_cmdr_pads_in_pads_in_payload_data_o + attribute \src "ls180.v:1067.5-1067.52" + wire \main_sdphy_cmdr_pads_in_pads_in_payload_data_oe + attribute \src "ls180.v:1058.6-1058.43" + wire \main_sdphy_cmdr_pads_in_pads_in_ready + attribute \src "ls180.v:1057.6-1057.43" + wire \main_sdphy_cmdr_pads_in_pads_in_valid + attribute \src "ls180.v:1069.5-1069.41" + wire \main_sdphy_cmdr_pads_out_payload_clk + attribute \src "ls180.v:1070.5-1070.43" + wire \main_sdphy_cmdr_pads_out_payload_cmd_o + attribute \src "ls180.v:1071.5-1071.44" + wire \main_sdphy_cmdr_pads_out_payload_cmd_oe + attribute \src "ls180.v:1072.11-1072.50" + wire width 4 \main_sdphy_cmdr_pads_out_payload_data_o + attribute \src "ls180.v:1073.5-1073.45" + wire \main_sdphy_cmdr_pads_out_payload_data_oe + attribute \src "ls180.v:1068.6-1068.36" + wire \main_sdphy_cmdr_pads_out_ready + attribute \src "ls180.v:1076.5-1076.30" + wire \main_sdphy_cmdr_sink_last + attribute \src "ls180.v:1077.11-1077.46" + wire width 8 \main_sdphy_cmdr_sink_payload_length + attribute \src "ls180.v:1075.5-1075.31" + wire \main_sdphy_cmdr_sink_ready + attribute \src "ls180.v:1074.5-1074.31" + wire \main_sdphy_cmdr_sink_valid + attribute \src "ls180.v:1080.5-1080.32" + wire \main_sdphy_cmdr_source_last + attribute \src "ls180.v:1081.11-1081.46" + wire width 8 \main_sdphy_cmdr_source_payload_data + attribute \src "ls180.v:1082.11-1082.48" + wire width 3 \main_sdphy_cmdr_source_payload_status + attribute \src "ls180.v:1079.5-1079.33" + wire \main_sdphy_cmdr_source_ready + attribute \src "ls180.v:1078.5-1078.33" + wire \main_sdphy_cmdr_source_valid + attribute \src "ls180.v:1083.12-1083.35" + wire width 32 \main_sdphy_cmdr_timeout + attribute \src "ls180.v:1759.12-1759.63" + wire width 32 \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1 + attribute \src "ls180.v:1760.5-1760.59" + wire \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1 + attribute \src "ls180.v:1056.11-1056.32" + wire width 8 \main_sdphy_cmdw_count + attribute \src "ls180.v:1753.11-1753.59" + wire width 8 \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value + attribute \src "ls180.v:1754.5-1754.56" + wire \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce + attribute \src "ls180.v:1055.5-1055.25" + wire \main_sdphy_cmdw_done + attribute \src "ls180.v:1043.6-1043.43" + wire \main_sdphy_cmdw_pads_in_payload_cmd_i + attribute \src "ls180.v:1044.12-1044.50" + wire width 4 \main_sdphy_cmdw_pads_in_payload_data_i + attribute \src "ls180.v:1042.6-1042.35" + wire \main_sdphy_cmdw_pads_in_valid + attribute \src "ls180.v:1046.5-1046.41" + wire \main_sdphy_cmdw_pads_out_payload_clk + attribute \src "ls180.v:1047.5-1047.43" + wire \main_sdphy_cmdw_pads_out_payload_cmd_o + attribute \src "ls180.v:1048.5-1048.44" + wire \main_sdphy_cmdw_pads_out_payload_cmd_oe + attribute \src "ls180.v:1049.11-1049.50" + wire width 4 \main_sdphy_cmdw_pads_out_payload_data_o + attribute \src "ls180.v:1050.5-1050.45" + wire \main_sdphy_cmdw_pads_out_payload_data_oe + attribute \src "ls180.v:1045.6-1045.36" + wire \main_sdphy_cmdw_pads_out_ready + attribute \src "ls180.v:1053.5-1053.30" + wire \main_sdphy_cmdw_sink_last + attribute \src "ls180.v:1054.11-1054.44" + wire width 8 \main_sdphy_cmdw_sink_payload_data + attribute \src "ls180.v:1052.5-1052.31" + wire \main_sdphy_cmdw_sink_ready + attribute \src "ls180.v:1051.5-1051.31" + wire \main_sdphy_cmdw_sink_valid + attribute \src "ls180.v:1240.11-1240.33" + wire width 10 \main_sdphy_datar_count + attribute \src "ls180.v:1773.11-1773.62" + wire width 10 \main_sdphy_datar_count_sdphy_sdphydatar_next_value0 + attribute \src "ls180.v:1774.5-1774.59" + wire \main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0 + attribute \src "ls180.v:1280.6-1280.43" + wire \main_sdphy_datar_datar_buf_sink_first + attribute \src "ls180.v:1281.6-1281.42" + wire \main_sdphy_datar_datar_buf_sink_last + attribute \src "ls180.v:1282.12-1282.56" + wire width 8 \main_sdphy_datar_datar_buf_sink_payload_data + attribute \src "ls180.v:1279.6-1279.43" + wire \main_sdphy_datar_datar_buf_sink_ready + attribute \src "ls180.v:1278.6-1278.43" + wire \main_sdphy_datar_datar_buf_sink_valid + attribute \src "ls180.v:1285.5-1285.44" + wire \main_sdphy_datar_datar_buf_source_first + attribute \src "ls180.v:1286.5-1286.43" + wire \main_sdphy_datar_datar_buf_source_last + attribute \src "ls180.v:1287.11-1287.57" + wire width 8 \main_sdphy_datar_datar_buf_source_payload_data + attribute \src "ls180.v:1284.6-1284.45" + wire \main_sdphy_datar_datar_buf_source_ready + attribute \src "ls180.v:1283.5-1283.44" + wire \main_sdphy_datar_datar_buf_source_valid + attribute \src "ls180.v:1270.5-1270.43" + wire \main_sdphy_datar_datar_converter_demux + attribute \src "ls180.v:1271.6-1271.48" + wire \main_sdphy_datar_datar_converter_load_part + attribute \src "ls180.v:1261.5-1261.48" + wire \main_sdphy_datar_datar_converter_sink_first + attribute \src "ls180.v:1262.5-1262.47" + wire \main_sdphy_datar_datar_converter_sink_last + attribute \src "ls180.v:1263.12-1263.62" + wire width 4 \main_sdphy_datar_datar_converter_sink_payload_data + attribute \src "ls180.v:1260.6-1260.49" + wire \main_sdphy_datar_datar_converter_sink_ready + attribute \src "ls180.v:1259.6-1259.49" + wire \main_sdphy_datar_datar_converter_sink_valid + attribute \src "ls180.v:1266.5-1266.50" + wire \main_sdphy_datar_datar_converter_source_first + attribute \src "ls180.v:1267.5-1267.49" + wire \main_sdphy_datar_datar_converter_source_last + attribute \src "ls180.v:1268.11-1268.63" + wire width 8 \main_sdphy_datar_datar_converter_source_payload_data + attribute \src "ls180.v:1269.11-1269.76" + wire width 2 \main_sdphy_datar_datar_converter_source_payload_valid_token_count + attribute \src "ls180.v:1265.6-1265.51" + wire \main_sdphy_datar_datar_converter_source_ready + attribute \src "ls180.v:1264.6-1264.51" + wire \main_sdphy_datar_datar_converter_source_valid + attribute \src "ls180.v:1272.5-1272.48" + wire \main_sdphy_datar_datar_converter_strobe_all + attribute \src "ls180.v:1243.6-1243.42" + wire \main_sdphy_datar_datar_pads_in_first + attribute \src "ls180.v:1244.6-1244.41" + wire \main_sdphy_datar_datar_pads_in_last + attribute \src "ls180.v:1245.6-1245.48" + wire \main_sdphy_datar_datar_pads_in_payload_clk + attribute \src "ls180.v:1246.6-1246.50" + wire \main_sdphy_datar_datar_pads_in_payload_cmd_i + attribute \src "ls180.v:1247.6-1247.50" + wire \main_sdphy_datar_datar_pads_in_payload_cmd_o + attribute \src "ls180.v:1248.6-1248.51" + wire \main_sdphy_datar_datar_pads_in_payload_cmd_oe + attribute \src "ls180.v:1249.12-1249.57" + wire width 4 \main_sdphy_datar_datar_pads_in_payload_data_i + attribute \src "ls180.v:1250.12-1250.57" + wire width 4 \main_sdphy_datar_datar_pads_in_payload_data_o + attribute \src "ls180.v:1251.6-1251.52" + wire \main_sdphy_datar_datar_pads_in_payload_data_oe + attribute \src "ls180.v:1242.5-1242.41" + wire \main_sdphy_datar_datar_pads_in_ready + attribute \src "ls180.v:1241.6-1241.42" + wire \main_sdphy_datar_datar_pads_in_valid + attribute \src "ls180.v:1288.5-1288.33" + wire \main_sdphy_datar_datar_reset + attribute \src "ls180.v:1777.5-1777.62" + wire \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2 + attribute \src "ls180.v:1778.5-1778.65" + wire \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2 + attribute \src "ls180.v:1258.5-1258.31" + wire \main_sdphy_datar_datar_run + attribute \src "ls180.v:1254.6-1254.49" + wire \main_sdphy_datar_datar_source_source_first0 + attribute \src "ls180.v:1275.6-1275.49" + wire \main_sdphy_datar_datar_source_source_first1 + attribute \src "ls180.v:1255.6-1255.48" + wire \main_sdphy_datar_datar_source_source_last0 + attribute \src "ls180.v:1276.6-1276.48" + wire \main_sdphy_datar_datar_source_source_last1 + attribute \src "ls180.v:1256.12-1256.62" + wire width 8 \main_sdphy_datar_datar_source_source_payload_data0 + attribute \src "ls180.v:1277.12-1277.62" + wire width 8 \main_sdphy_datar_datar_source_source_payload_data1 + attribute \src "ls180.v:1253.5-1253.48" + wire \main_sdphy_datar_datar_source_source_ready0 + attribute \src "ls180.v:1274.6-1274.49" + wire \main_sdphy_datar_datar_source_source_ready1 + attribute \src "ls180.v:1252.6-1252.49" + wire \main_sdphy_datar_datar_source_source_valid0 + attribute \src "ls180.v:1273.6-1273.49" + wire \main_sdphy_datar_datar_source_source_valid1 + attribute \src "ls180.v:1257.6-1257.34" + wire \main_sdphy_datar_datar_start + attribute \src "ls180.v:1213.5-1213.43" + wire \main_sdphy_datar_pads_in_pads_in_first + attribute \src "ls180.v:1214.5-1214.42" + wire \main_sdphy_datar_pads_in_pads_in_last + attribute \src "ls180.v:1215.5-1215.49" + wire \main_sdphy_datar_pads_in_pads_in_payload_clk + attribute \src "ls180.v:1216.6-1216.52" + wire \main_sdphy_datar_pads_in_pads_in_payload_cmd_i + attribute \src "ls180.v:1217.5-1217.51" + wire \main_sdphy_datar_pads_in_pads_in_payload_cmd_o + attribute \src "ls180.v:1218.5-1218.52" + wire \main_sdphy_datar_pads_in_pads_in_payload_cmd_oe + attribute \src "ls180.v:1219.12-1219.59" + wire width 4 \main_sdphy_datar_pads_in_pads_in_payload_data_i + attribute \src "ls180.v:1220.11-1220.58" + wire width 4 \main_sdphy_datar_pads_in_pads_in_payload_data_o + attribute \src "ls180.v:1221.5-1221.53" + wire \main_sdphy_datar_pads_in_pads_in_payload_data_oe + attribute \src "ls180.v:1212.6-1212.44" + wire \main_sdphy_datar_pads_in_pads_in_ready + attribute \src "ls180.v:1211.6-1211.44" + wire \main_sdphy_datar_pads_in_pads_in_valid + attribute \src "ls180.v:1223.5-1223.42" + wire \main_sdphy_datar_pads_out_payload_clk + attribute \src "ls180.v:1224.5-1224.44" + wire \main_sdphy_datar_pads_out_payload_cmd_o + attribute \src "ls180.v:1225.5-1225.45" + wire \main_sdphy_datar_pads_out_payload_cmd_oe + attribute \src "ls180.v:1226.11-1226.51" + wire width 4 \main_sdphy_datar_pads_out_payload_data_o + attribute \src "ls180.v:1227.5-1227.46" + wire \main_sdphy_datar_pads_out_payload_data_oe + attribute \src "ls180.v:1222.6-1222.37" + wire \main_sdphy_datar_pads_out_ready + attribute \src "ls180.v:1230.5-1230.31" + wire \main_sdphy_datar_sink_last + attribute \src "ls180.v:1231.11-1231.53" + wire width 10 \main_sdphy_datar_sink_payload_block_length + attribute \src "ls180.v:1229.5-1229.32" + wire \main_sdphy_datar_sink_ready + attribute \src "ls180.v:1228.5-1228.32" + wire \main_sdphy_datar_sink_valid + attribute \src "ls180.v:1234.5-1234.34" + wire \main_sdphy_datar_source_first + attribute \src "ls180.v:1235.5-1235.33" + wire \main_sdphy_datar_source_last + attribute \src "ls180.v:1236.11-1236.47" + wire width 8 \main_sdphy_datar_source_payload_data + attribute \src "ls180.v:1237.11-1237.49" + wire width 3 \main_sdphy_datar_source_payload_status + attribute \src "ls180.v:1233.5-1233.34" + wire \main_sdphy_datar_source_ready + attribute \src "ls180.v:1232.5-1232.34" + wire \main_sdphy_datar_source_valid + attribute \src "ls180.v:1238.5-1238.26" + wire \main_sdphy_datar_stop + attribute \src "ls180.v:1239.12-1239.36" + wire width 32 \main_sdphy_datar_timeout + attribute \src "ls180.v:1775.12-1775.65" + wire width 32 \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1 + attribute \src "ls180.v:1776.5-1776.61" + wire \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1 + attribute \src "ls180.v:1148.11-1148.33" + wire width 8 \main_sdphy_dataw_count + attribute \src "ls180.v:1769.11-1769.54" + wire width 8 \main_sdphy_dataw_count_sdphy_fsm_next_value + attribute \src "ls180.v:1770.5-1770.51" + wire \main_sdphy_dataw_count_sdphy_fsm_next_value_ce + attribute \src "ls180.v:1202.6-1202.42" + wire \main_sdphy_dataw_crcr_buf_sink_first + attribute \src "ls180.v:1203.6-1203.41" + wire \main_sdphy_dataw_crcr_buf_sink_last + attribute \src "ls180.v:1204.12-1204.55" + wire width 8 \main_sdphy_dataw_crcr_buf_sink_payload_data + attribute \src "ls180.v:1201.6-1201.42" + wire \main_sdphy_dataw_crcr_buf_sink_ready + attribute \src "ls180.v:1200.6-1200.42" + wire \main_sdphy_dataw_crcr_buf_sink_valid + attribute \src "ls180.v:1207.5-1207.43" + wire \main_sdphy_dataw_crcr_buf_source_first + attribute \src "ls180.v:1208.5-1208.42" + wire \main_sdphy_dataw_crcr_buf_source_last + attribute \src "ls180.v:1209.11-1209.56" + wire width 8 \main_sdphy_dataw_crcr_buf_source_payload_data + attribute \src "ls180.v:1206.6-1206.44" + wire \main_sdphy_dataw_crcr_buf_source_ready + attribute \src "ls180.v:1205.5-1205.43" + wire \main_sdphy_dataw_crcr_buf_source_valid + attribute \src "ls180.v:1192.11-1192.48" + wire width 3 \main_sdphy_dataw_crcr_converter_demux + attribute \src "ls180.v:1193.6-1193.47" + wire \main_sdphy_dataw_crcr_converter_load_part + attribute \src "ls180.v:1183.5-1183.47" + wire \main_sdphy_dataw_crcr_converter_sink_first + attribute \src "ls180.v:1184.5-1184.46" + wire \main_sdphy_dataw_crcr_converter_sink_last + attribute \src "ls180.v:1185.6-1185.55" + wire \main_sdphy_dataw_crcr_converter_sink_payload_data + attribute \src "ls180.v:1182.6-1182.48" + wire \main_sdphy_dataw_crcr_converter_sink_ready + attribute \src "ls180.v:1181.6-1181.48" + wire \main_sdphy_dataw_crcr_converter_sink_valid + attribute \src "ls180.v:1188.5-1188.49" + wire \main_sdphy_dataw_crcr_converter_source_first + attribute \src "ls180.v:1189.5-1189.48" + wire \main_sdphy_dataw_crcr_converter_source_last + attribute \src "ls180.v:1190.11-1190.62" + wire width 8 \main_sdphy_dataw_crcr_converter_source_payload_data + attribute \src "ls180.v:1191.11-1191.75" + wire width 4 \main_sdphy_dataw_crcr_converter_source_payload_valid_token_count + attribute \src "ls180.v:1187.6-1187.50" + wire \main_sdphy_dataw_crcr_converter_source_ready + attribute \src "ls180.v:1186.6-1186.50" + wire \main_sdphy_dataw_crcr_converter_source_valid + attribute \src "ls180.v:1194.5-1194.47" + wire \main_sdphy_dataw_crcr_converter_strobe_all + attribute \src "ls180.v:1165.6-1165.41" + wire \main_sdphy_dataw_crcr_pads_in_first + attribute \src "ls180.v:1166.6-1166.40" + wire \main_sdphy_dataw_crcr_pads_in_last + attribute \src "ls180.v:1167.6-1167.47" + wire \main_sdphy_dataw_crcr_pads_in_payload_clk + attribute \src "ls180.v:1168.6-1168.49" + wire \main_sdphy_dataw_crcr_pads_in_payload_cmd_i + attribute \src "ls180.v:1169.6-1169.49" + wire \main_sdphy_dataw_crcr_pads_in_payload_cmd_o + attribute \src "ls180.v:1170.6-1170.50" + wire \main_sdphy_dataw_crcr_pads_in_payload_cmd_oe + attribute \src "ls180.v:1171.12-1171.56" + wire width 4 \main_sdphy_dataw_crcr_pads_in_payload_data_i + attribute \src "ls180.v:1172.12-1172.56" + wire width 4 \main_sdphy_dataw_crcr_pads_in_payload_data_o + attribute \src "ls180.v:1173.6-1173.51" + wire \main_sdphy_dataw_crcr_pads_in_payload_data_oe + attribute \src "ls180.v:1164.5-1164.40" + wire \main_sdphy_dataw_crcr_pads_in_ready + attribute \src "ls180.v:1163.6-1163.41" + wire \main_sdphy_dataw_crcr_pads_in_valid + attribute \src "ls180.v:1210.5-1210.32" + wire \main_sdphy_dataw_crcr_reset + attribute \src "ls180.v:1765.5-1765.59" + wire \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value + attribute \src "ls180.v:1766.5-1766.62" + wire \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce + attribute \src "ls180.v:1180.5-1180.30" + wire \main_sdphy_dataw_crcr_run + attribute \src "ls180.v:1176.6-1176.48" + wire \main_sdphy_dataw_crcr_source_source_first0 + attribute \src "ls180.v:1197.6-1197.48" + wire \main_sdphy_dataw_crcr_source_source_first1 + attribute \src "ls180.v:1177.6-1177.47" + wire \main_sdphy_dataw_crcr_source_source_last0 + attribute \src "ls180.v:1198.6-1198.47" + wire \main_sdphy_dataw_crcr_source_source_last1 + attribute \src "ls180.v:1178.12-1178.61" + wire width 8 \main_sdphy_dataw_crcr_source_source_payload_data0 + attribute \src "ls180.v:1199.12-1199.61" + wire width 8 \main_sdphy_dataw_crcr_source_source_payload_data1 + attribute \src "ls180.v:1175.5-1175.47" + wire \main_sdphy_dataw_crcr_source_source_ready0 + attribute \src "ls180.v:1196.6-1196.48" + wire \main_sdphy_dataw_crcr_source_source_ready1 + attribute \src "ls180.v:1174.6-1174.48" + wire \main_sdphy_dataw_crcr_source_source_valid0 + attribute \src "ls180.v:1195.6-1195.48" + wire \main_sdphy_dataw_crcr_source_source_valid1 + attribute \src "ls180.v:1179.6-1179.33" + wire \main_sdphy_dataw_crcr_start + attribute \src "ls180.v:1162.5-1162.27" + wire \main_sdphy_dataw_error + attribute \src "ls180.v:1151.5-1151.43" + wire \main_sdphy_dataw_pads_in_pads_in_first + attribute \src "ls180.v:1152.5-1152.42" + wire \main_sdphy_dataw_pads_in_pads_in_last + attribute \src "ls180.v:1153.5-1153.49" + wire \main_sdphy_dataw_pads_in_pads_in_payload_clk + attribute \src "ls180.v:1154.5-1154.51" + wire \main_sdphy_dataw_pads_in_pads_in_payload_cmd_i + attribute \src "ls180.v:1155.5-1155.51" + wire \main_sdphy_dataw_pads_in_pads_in_payload_cmd_o + attribute \src "ls180.v:1156.5-1156.52" + wire \main_sdphy_dataw_pads_in_pads_in_payload_cmd_oe + attribute \src "ls180.v:1157.11-1157.58" + wire width 4 \main_sdphy_dataw_pads_in_pads_in_payload_data_i + attribute \src "ls180.v:1158.11-1158.58" + wire width 4 \main_sdphy_dataw_pads_in_pads_in_payload_data_o + attribute \src "ls180.v:1159.5-1159.53" + wire \main_sdphy_dataw_pads_in_pads_in_payload_data_oe + attribute \src "ls180.v:1150.6-1150.44" + wire \main_sdphy_dataw_pads_in_pads_in_ready + attribute \src "ls180.v:1149.5-1149.43" + wire \main_sdphy_dataw_pads_in_pads_in_valid + attribute \src "ls180.v:1134.6-1134.44" + wire \main_sdphy_dataw_pads_in_payload_cmd_i + attribute \src "ls180.v:1135.12-1135.51" + wire width 4 \main_sdphy_dataw_pads_in_payload_data_i + attribute \src "ls180.v:1133.6-1133.36" + wire \main_sdphy_dataw_pads_in_valid + attribute \src "ls180.v:1137.5-1137.42" + wire \main_sdphy_dataw_pads_out_payload_clk + attribute \src "ls180.v:1138.5-1138.44" + wire \main_sdphy_dataw_pads_out_payload_cmd_o + attribute \src "ls180.v:1139.5-1139.45" + wire \main_sdphy_dataw_pads_out_payload_cmd_oe + attribute \src "ls180.v:1140.11-1140.51" + wire width 4 \main_sdphy_dataw_pads_out_payload_data_o + attribute \src "ls180.v:1141.5-1141.46" + wire \main_sdphy_dataw_pads_out_payload_data_oe + attribute \src "ls180.v:1136.6-1136.37" + wire \main_sdphy_dataw_pads_out_ready + attribute \src "ls180.v:1144.5-1144.32" + wire \main_sdphy_dataw_sink_first + attribute \src "ls180.v:1145.5-1145.31" + wire \main_sdphy_dataw_sink_last + attribute \src "ls180.v:1146.11-1146.45" + wire width 8 \main_sdphy_dataw_sink_payload_data + attribute \src "ls180.v:1143.5-1143.32" + wire \main_sdphy_dataw_sink_ready + attribute \src "ls180.v:1142.5-1142.32" + wire \main_sdphy_dataw_sink_valid + attribute \src "ls180.v:1160.5-1160.27" + wire \main_sdphy_dataw_start + attribute \src "ls180.v:1147.5-1147.26" + wire \main_sdphy_dataw_stop + attribute \src "ls180.v:1161.5-1161.27" + wire \main_sdphy_dataw_valid + attribute \src "ls180.v:1041.11-1041.32" + wire width 8 \main_sdphy_init_count + attribute \src "ls180.v:1749.11-1749.59" + wire width 8 \main_sdphy_init_count_sdphy_sdphyinit_next_value + attribute \src "ls180.v:1750.5-1750.56" + wire \main_sdphy_init_count_sdphy_sdphyinit_next_value_ce + attribute \src "ls180.v:1029.6-1029.34" + wire \main_sdphy_init_initialize_r + attribute \src "ls180.v:1028.6-1028.35" + wire \main_sdphy_init_initialize_re + attribute \src "ls180.v:1031.5-1031.33" + wire \main_sdphy_init_initialize_w + attribute \src "ls180.v:1030.6-1030.35" + wire \main_sdphy_init_initialize_we + attribute \src "ls180.v:1033.6-1033.43" + wire \main_sdphy_init_pads_in_payload_cmd_i + attribute \src "ls180.v:1034.12-1034.50" + wire width 4 \main_sdphy_init_pads_in_payload_data_i + attribute \src "ls180.v:1032.6-1032.35" + wire \main_sdphy_init_pads_in_valid + attribute \src "ls180.v:1036.5-1036.41" + wire \main_sdphy_init_pads_out_payload_clk + attribute \src "ls180.v:1037.5-1037.43" + wire \main_sdphy_init_pads_out_payload_cmd_o + attribute \src "ls180.v:1038.5-1038.44" + wire \main_sdphy_init_pads_out_payload_cmd_oe + attribute \src "ls180.v:1039.11-1039.50" + wire width 4 \main_sdphy_init_pads_out_payload_data_o + attribute \src "ls180.v:1040.5-1040.45" + wire \main_sdphy_init_pads_out_payload_data_oe + attribute \src "ls180.v:1035.6-1035.36" + wire \main_sdphy_init_pads_out_ready + attribute \src "ls180.v:1289.6-1289.27" + wire \main_sdphy_sdpads_clk + attribute \src "ls180.v:1290.5-1290.28" + wire \main_sdphy_sdpads_cmd_i + attribute \src "ls180.v:1291.6-1291.29" + wire \main_sdphy_sdpads_cmd_o + attribute \src "ls180.v:1292.6-1292.30" + wire \main_sdphy_sdpads_cmd_oe + attribute \src "ls180.v:1293.11-1293.35" + wire width 4 \main_sdphy_sdpads_data_i + attribute \src "ls180.v:1294.12-1294.36" + wire width 4 \main_sdphy_sdpads_data_o + attribute \src "ls180.v:1295.6-1295.31" + wire \main_sdphy_sdpads_data_oe + attribute \src "ls180.v:1018.6-1018.23" + wire \main_sdphy_status + attribute \src "ls180.v:1019.6-1019.19" + wire \main_sdphy_we + attribute \src "ls180.v:299.5-299.26" + wire \main_sdram_address_re + attribute \src "ls180.v:298.12-298.38" + wire width 13 \main_sdram_address_storage + attribute \src "ls180.v:301.5-301.27" + wire \main_sdram_baddress_re + attribute \src "ls180.v:300.11-300.38" + wire width 2 \main_sdram_baddress_storage + attribute \src "ls180.v:397.5-397.43" + wire \main_sdram_bankmachine0_auto_precharge + attribute \src "ls180.v:419.11-419.63" + wire width 3 \main_sdram_bankmachine0_cmd_buffer_lookahead_consume + attribute \src "ls180.v:424.6-424.58" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read + attribute \src "ls180.v:429.6-429.64" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first + attribute \src "ls180.v:430.6-430.63" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last + attribute \src "ls180.v:428.13-428.78" + wire width 22 \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr + attribute \src "ls180.v:427.6-427.69" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we + attribute \src "ls180.v:433.6-433.65" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first + attribute \src "ls180.v:434.6-434.64" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last + attribute \src "ls180.v:432.13-432.79" + wire width 22 \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr + attribute \src "ls180.v:431.6-431.70" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we + attribute \src "ls180.v:416.11-416.61" + wire width 4 \main_sdram_bankmachine0_cmd_buffer_lookahead_level + attribute \src "ls180.v:418.11-418.63" + wire width 3 \main_sdram_bankmachine0_cmd_buffer_lookahead_produce + attribute \src "ls180.v:425.12-425.67" + wire width 3 \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr + attribute \src "ls180.v:426.13-426.70" + wire width 25 \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r + attribute \src "ls180.v:417.5-417.57" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_replace + attribute \src "ls180.v:400.5-400.60" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first + attribute \src "ls180.v:401.5-401.59" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last + attribute \src "ls180.v:403.13-403.75" + wire width 22 \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr + attribute \src "ls180.v:402.6-402.66" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we + attribute \src "ls180.v:399.6-399.61" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_ready + attribute \src "ls180.v:398.6-398.61" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_valid + attribute \src "ls180.v:406.6-406.63" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_source_first + attribute \src "ls180.v:407.6-407.62" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_source_last + attribute \src "ls180.v:409.13-409.77" + wire width 22 \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr + attribute \src "ls180.v:408.6-408.68" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we + attribute \src "ls180.v:405.6-405.63" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_source_ready + attribute \src "ls180.v:404.6-404.63" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_source_valid + attribute \src "ls180.v:414.13-414.71" + wire width 25 \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din + attribute \src "ls180.v:415.13-415.72" + wire width 25 \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout + attribute \src "ls180.v:412.6-412.63" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re + attribute \src "ls180.v:413.6-413.69" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable + attribute \src "ls180.v:410.6-410.63" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we + attribute \src "ls180.v:411.6-411.69" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable + attribute \src "ls180.v:420.11-420.66" + wire width 3 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr + attribute \src "ls180.v:421.13-421.70" + wire width 25 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_r + attribute \src "ls180.v:423.13-423.70" + wire width 25 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w + attribute \src "ls180.v:422.6-422.60" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we + attribute \src "ls180.v:437.6-437.51" + wire \main_sdram_bankmachine0_cmd_buffer_sink_first + attribute \src "ls180.v:438.6-438.50" + wire \main_sdram_bankmachine0_cmd_buffer_sink_last + attribute \src "ls180.v:440.13-440.65" + wire width 22 \main_sdram_bankmachine0_cmd_buffer_sink_payload_addr + attribute \src "ls180.v:439.6-439.56" + wire \main_sdram_bankmachine0_cmd_buffer_sink_payload_we + attribute \src "ls180.v:436.6-436.51" + wire \main_sdram_bankmachine0_cmd_buffer_sink_ready + attribute \src "ls180.v:435.6-435.51" + wire \main_sdram_bankmachine0_cmd_buffer_sink_valid + attribute \src "ls180.v:443.5-443.52" + wire \main_sdram_bankmachine0_cmd_buffer_source_first + attribute \src "ls180.v:444.5-444.51" + wire \main_sdram_bankmachine0_cmd_buffer_source_last + attribute \src "ls180.v:446.12-446.66" + wire width 22 \main_sdram_bankmachine0_cmd_buffer_source_payload_addr + attribute \src "ls180.v:445.5-445.57" + wire \main_sdram_bankmachine0_cmd_buffer_source_payload_we + attribute \src "ls180.v:442.6-442.53" + wire \main_sdram_bankmachine0_cmd_buffer_source_ready + attribute \src "ls180.v:441.5-441.52" + wire \main_sdram_bankmachine0_cmd_buffer_source_valid + attribute \src "ls180.v:389.12-389.49" + wire width 13 \main_sdram_bankmachine0_cmd_payload_a + attribute \src "ls180.v:390.12-390.50" + wire width 2 \main_sdram_bankmachine0_cmd_payload_ba + attribute \src "ls180.v:391.5-391.44" + wire \main_sdram_bankmachine0_cmd_payload_cas + attribute \src "ls180.v:394.5-394.47" + wire \main_sdram_bankmachine0_cmd_payload_is_cmd + attribute \src "ls180.v:395.5-395.48" + wire \main_sdram_bankmachine0_cmd_payload_is_read + attribute \src "ls180.v:396.5-396.49" + wire \main_sdram_bankmachine0_cmd_payload_is_write + attribute \src "ls180.v:392.5-392.44" + wire \main_sdram_bankmachine0_cmd_payload_ras + attribute \src "ls180.v:393.5-393.43" + wire \main_sdram_bankmachine0_cmd_payload_we + attribute \src "ls180.v:388.5-388.38" + wire \main_sdram_bankmachine0_cmd_ready + attribute \src "ls180.v:387.5-387.38" + wire \main_sdram_bankmachine0_cmd_valid + attribute \src "ls180.v:386.5-386.40" + wire \main_sdram_bankmachine0_refresh_gnt + attribute \src "ls180.v:385.6-385.41" + wire \main_sdram_bankmachine0_refresh_req + attribute \src "ls180.v:381.13-381.45" + wire width 22 \main_sdram_bankmachine0_req_addr + attribute \src "ls180.v:382.6-382.38" + wire \main_sdram_bankmachine0_req_lock + attribute \src "ls180.v:384.5-384.44" + wire \main_sdram_bankmachine0_req_rdata_valid + attribute \src "ls180.v:379.6-379.39" + wire \main_sdram_bankmachine0_req_ready + attribute \src "ls180.v:378.6-378.39" + wire \main_sdram_bankmachine0_req_valid + attribute \src "ls180.v:383.5-383.44" + wire \main_sdram_bankmachine0_req_wdata_ready + attribute \src "ls180.v:380.6-380.36" + wire \main_sdram_bankmachine0_req_we + attribute \src "ls180.v:447.12-447.39" + wire width 13 \main_sdram_bankmachine0_row + attribute \src "ls180.v:451.5-451.38" + wire \main_sdram_bankmachine0_row_close + attribute \src "ls180.v:452.5-452.47" + wire \main_sdram_bankmachine0_row_col_n_addr_sel + attribute \src "ls180.v:449.6-449.37" + wire \main_sdram_bankmachine0_row_hit + attribute \src "ls180.v:450.5-450.37" + wire \main_sdram_bankmachine0_row_open + attribute \src "ls180.v:448.5-448.39" + wire \main_sdram_bankmachine0_row_opened + attribute \no_retiming "true" + attribute \src "ls180.v:459.32-459.69" + wire \main_sdram_bankmachine0_trascon_ready + attribute \src "ls180.v:458.6-458.43" + wire \main_sdram_bankmachine0_trascon_valid + attribute \no_retiming "true" + attribute \src "ls180.v:457.32-457.68" + wire \main_sdram_bankmachine0_trccon_ready + attribute \src "ls180.v:456.6-456.42" + wire \main_sdram_bankmachine0_trccon_valid + attribute \src "ls180.v:455.11-455.48" + wire width 3 \main_sdram_bankmachine0_twtpcon_count + attribute \no_retiming "true" + attribute \src "ls180.v:454.32-454.69" + wire \main_sdram_bankmachine0_twtpcon_ready + attribute \src "ls180.v:453.6-453.43" + wire \main_sdram_bankmachine0_twtpcon_valid + attribute \src "ls180.v:479.5-479.43" + wire \main_sdram_bankmachine1_auto_precharge + attribute \src "ls180.v:501.11-501.63" + wire width 3 \main_sdram_bankmachine1_cmd_buffer_lookahead_consume + attribute \src "ls180.v:506.6-506.58" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read + attribute \src "ls180.v:511.6-511.64" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first + attribute \src "ls180.v:512.6-512.63" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last + attribute \src "ls180.v:510.13-510.78" + wire width 22 \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr + attribute \src "ls180.v:509.6-509.69" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we + attribute \src "ls180.v:515.6-515.65" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first + attribute \src "ls180.v:516.6-516.64" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last + attribute \src "ls180.v:514.13-514.79" + wire width 22 \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr + attribute \src "ls180.v:513.6-513.70" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we + attribute \src "ls180.v:498.11-498.61" + wire width 4 \main_sdram_bankmachine1_cmd_buffer_lookahead_level + attribute \src "ls180.v:500.11-500.63" + wire width 3 \main_sdram_bankmachine1_cmd_buffer_lookahead_produce + attribute \src "ls180.v:507.12-507.67" + wire width 3 \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr + attribute \src "ls180.v:508.13-508.70" + wire width 25 \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r + attribute \src "ls180.v:499.5-499.57" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_replace + attribute \src "ls180.v:482.5-482.60" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first + attribute \src "ls180.v:483.5-483.59" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last + attribute \src "ls180.v:485.13-485.75" + wire width 22 \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr + attribute \src "ls180.v:484.6-484.66" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we + attribute \src "ls180.v:481.6-481.61" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_ready + attribute \src "ls180.v:480.6-480.61" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_valid + attribute \src "ls180.v:488.6-488.63" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_source_first + attribute \src "ls180.v:489.6-489.62" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_source_last + attribute \src "ls180.v:491.13-491.77" + wire width 22 \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr + attribute \src "ls180.v:490.6-490.68" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we + attribute \src "ls180.v:487.6-487.63" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_source_ready + attribute \src "ls180.v:486.6-486.63" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_source_valid + attribute \src "ls180.v:496.13-496.71" + wire width 25 \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din + attribute \src "ls180.v:497.13-497.72" + wire width 25 \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout + attribute \src "ls180.v:494.6-494.63" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re + attribute \src "ls180.v:495.6-495.69" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable + attribute \src "ls180.v:492.6-492.63" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we + attribute \src "ls180.v:493.6-493.69" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable + attribute \src "ls180.v:502.11-502.66" + wire width 3 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr + attribute \src "ls180.v:503.13-503.70" + wire width 25 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_r + attribute \src "ls180.v:505.13-505.70" + wire width 25 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w + attribute \src "ls180.v:504.6-504.60" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we + attribute \src "ls180.v:519.6-519.51" + wire \main_sdram_bankmachine1_cmd_buffer_sink_first + attribute \src "ls180.v:520.6-520.50" + wire \main_sdram_bankmachine1_cmd_buffer_sink_last + attribute \src "ls180.v:522.13-522.65" + wire width 22 \main_sdram_bankmachine1_cmd_buffer_sink_payload_addr + attribute \src "ls180.v:521.6-521.56" + wire \main_sdram_bankmachine1_cmd_buffer_sink_payload_we + attribute \src "ls180.v:518.6-518.51" + wire \main_sdram_bankmachine1_cmd_buffer_sink_ready + attribute \src "ls180.v:517.6-517.51" + wire \main_sdram_bankmachine1_cmd_buffer_sink_valid + attribute \src "ls180.v:525.5-525.52" + wire \main_sdram_bankmachine1_cmd_buffer_source_first + attribute \src "ls180.v:526.5-526.51" + wire \main_sdram_bankmachine1_cmd_buffer_source_last + attribute \src "ls180.v:528.12-528.66" + wire width 22 \main_sdram_bankmachine1_cmd_buffer_source_payload_addr + attribute \src "ls180.v:527.5-527.57" + wire \main_sdram_bankmachine1_cmd_buffer_source_payload_we + attribute \src "ls180.v:524.6-524.53" + wire \main_sdram_bankmachine1_cmd_buffer_source_ready + attribute \src "ls180.v:523.5-523.52" + wire \main_sdram_bankmachine1_cmd_buffer_source_valid + attribute \src "ls180.v:471.12-471.49" + wire width 13 \main_sdram_bankmachine1_cmd_payload_a + attribute \src "ls180.v:472.12-472.50" + wire width 2 \main_sdram_bankmachine1_cmd_payload_ba + attribute \src "ls180.v:473.5-473.44" + wire \main_sdram_bankmachine1_cmd_payload_cas + attribute \src "ls180.v:476.5-476.47" + wire \main_sdram_bankmachine1_cmd_payload_is_cmd + attribute \src "ls180.v:477.5-477.48" + wire \main_sdram_bankmachine1_cmd_payload_is_read + attribute \src "ls180.v:478.5-478.49" + wire \main_sdram_bankmachine1_cmd_payload_is_write + attribute \src "ls180.v:474.5-474.44" + wire \main_sdram_bankmachine1_cmd_payload_ras + attribute \src "ls180.v:475.5-475.43" + wire \main_sdram_bankmachine1_cmd_payload_we + attribute \src "ls180.v:470.5-470.38" + wire \main_sdram_bankmachine1_cmd_ready + attribute \src "ls180.v:469.5-469.38" + wire \main_sdram_bankmachine1_cmd_valid + attribute \src "ls180.v:468.5-468.40" + wire \main_sdram_bankmachine1_refresh_gnt + attribute \src "ls180.v:467.6-467.41" + wire \main_sdram_bankmachine1_refresh_req + attribute \src "ls180.v:463.13-463.45" + wire width 22 \main_sdram_bankmachine1_req_addr + attribute \src "ls180.v:464.6-464.38" + wire \main_sdram_bankmachine1_req_lock + attribute \src "ls180.v:466.5-466.44" + wire \main_sdram_bankmachine1_req_rdata_valid + attribute \src "ls180.v:461.6-461.39" + wire \main_sdram_bankmachine1_req_ready + attribute \src "ls180.v:460.6-460.39" + wire \main_sdram_bankmachine1_req_valid + attribute \src "ls180.v:465.5-465.44" + wire \main_sdram_bankmachine1_req_wdata_ready + attribute \src "ls180.v:462.6-462.36" + wire \main_sdram_bankmachine1_req_we + attribute \src "ls180.v:529.12-529.39" + wire width 13 \main_sdram_bankmachine1_row + attribute \src "ls180.v:533.5-533.38" + wire \main_sdram_bankmachine1_row_close + attribute \src "ls180.v:534.5-534.47" + wire \main_sdram_bankmachine1_row_col_n_addr_sel + attribute \src "ls180.v:531.6-531.37" + wire \main_sdram_bankmachine1_row_hit + attribute \src "ls180.v:532.5-532.37" + wire \main_sdram_bankmachine1_row_open + attribute \src "ls180.v:530.5-530.39" + wire \main_sdram_bankmachine1_row_opened + attribute \no_retiming "true" + attribute \src "ls180.v:541.32-541.69" + wire \main_sdram_bankmachine1_trascon_ready + attribute \src "ls180.v:540.6-540.43" + wire \main_sdram_bankmachine1_trascon_valid + attribute \no_retiming "true" + attribute \src "ls180.v:539.32-539.68" + wire \main_sdram_bankmachine1_trccon_ready + attribute \src "ls180.v:538.6-538.42" + wire \main_sdram_bankmachine1_trccon_valid + attribute \src "ls180.v:537.11-537.48" + wire width 3 \main_sdram_bankmachine1_twtpcon_count + attribute \no_retiming "true" + attribute \src "ls180.v:536.32-536.69" + wire \main_sdram_bankmachine1_twtpcon_ready + attribute \src "ls180.v:535.6-535.43" + wire \main_sdram_bankmachine1_twtpcon_valid + attribute \src "ls180.v:561.5-561.43" + wire \main_sdram_bankmachine2_auto_precharge + attribute \src "ls180.v:583.11-583.63" + wire width 3 \main_sdram_bankmachine2_cmd_buffer_lookahead_consume + attribute \src "ls180.v:588.6-588.58" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read + attribute \src "ls180.v:593.6-593.64" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first + attribute \src "ls180.v:594.6-594.63" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last + attribute \src "ls180.v:592.13-592.78" + wire width 22 \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr + attribute \src "ls180.v:591.6-591.69" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we + attribute \src "ls180.v:597.6-597.65" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first + attribute \src "ls180.v:598.6-598.64" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last + attribute \src "ls180.v:596.13-596.79" + wire width 22 \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr + attribute \src "ls180.v:595.6-595.70" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we + attribute \src "ls180.v:580.11-580.61" + wire width 4 \main_sdram_bankmachine2_cmd_buffer_lookahead_level + attribute \src "ls180.v:582.11-582.63" + wire width 3 \main_sdram_bankmachine2_cmd_buffer_lookahead_produce + attribute \src "ls180.v:589.12-589.67" + wire width 3 \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr + attribute \src "ls180.v:590.13-590.70" + wire width 25 \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r + attribute \src "ls180.v:581.5-581.57" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_replace + attribute \src "ls180.v:564.5-564.60" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first + attribute \src "ls180.v:565.5-565.59" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last + attribute \src "ls180.v:567.13-567.75" + wire width 22 \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr + attribute \src "ls180.v:566.6-566.66" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we + attribute \src "ls180.v:563.6-563.61" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_ready + attribute \src "ls180.v:562.6-562.61" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_valid + attribute \src "ls180.v:570.6-570.63" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_source_first + attribute \src "ls180.v:571.6-571.62" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_source_last + attribute \src "ls180.v:573.13-573.77" + wire width 22 \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr + attribute \src "ls180.v:572.6-572.68" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we + attribute \src "ls180.v:569.6-569.63" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_source_ready + attribute \src "ls180.v:568.6-568.63" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_source_valid + attribute \src "ls180.v:578.13-578.71" + wire width 25 \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din + attribute \src "ls180.v:579.13-579.72" + wire width 25 \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout + attribute \src "ls180.v:576.6-576.63" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re + attribute \src "ls180.v:577.6-577.69" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable + attribute \src "ls180.v:574.6-574.63" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we + attribute \src "ls180.v:575.6-575.69" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable + attribute \src "ls180.v:584.11-584.66" + wire width 3 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr + attribute \src "ls180.v:585.13-585.70" + wire width 25 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_r + attribute \src "ls180.v:587.13-587.70" + wire width 25 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w + attribute \src "ls180.v:586.6-586.60" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_we + attribute \src "ls180.v:601.6-601.51" + wire \main_sdram_bankmachine2_cmd_buffer_sink_first + attribute \src "ls180.v:602.6-602.50" + wire \main_sdram_bankmachine2_cmd_buffer_sink_last + attribute \src "ls180.v:604.13-604.65" + wire width 22 \main_sdram_bankmachine2_cmd_buffer_sink_payload_addr + attribute \src "ls180.v:603.6-603.56" + wire \main_sdram_bankmachine2_cmd_buffer_sink_payload_we + attribute \src "ls180.v:600.6-600.51" + wire \main_sdram_bankmachine2_cmd_buffer_sink_ready + attribute \src "ls180.v:599.6-599.51" + wire \main_sdram_bankmachine2_cmd_buffer_sink_valid + attribute \src "ls180.v:607.5-607.52" + wire \main_sdram_bankmachine2_cmd_buffer_source_first + attribute \src "ls180.v:608.5-608.51" + wire \main_sdram_bankmachine2_cmd_buffer_source_last + attribute \src "ls180.v:610.12-610.66" + wire width 22 \main_sdram_bankmachine2_cmd_buffer_source_payload_addr + attribute \src "ls180.v:609.5-609.57" + wire \main_sdram_bankmachine2_cmd_buffer_source_payload_we + attribute \src "ls180.v:606.6-606.53" + wire \main_sdram_bankmachine2_cmd_buffer_source_ready + attribute \src "ls180.v:605.5-605.52" + wire \main_sdram_bankmachine2_cmd_buffer_source_valid + attribute \src "ls180.v:553.12-553.49" + wire width 13 \main_sdram_bankmachine2_cmd_payload_a + attribute \src "ls180.v:554.12-554.50" + wire width 2 \main_sdram_bankmachine2_cmd_payload_ba + attribute \src "ls180.v:555.5-555.44" + wire \main_sdram_bankmachine2_cmd_payload_cas + attribute \src "ls180.v:558.5-558.47" + wire \main_sdram_bankmachine2_cmd_payload_is_cmd + attribute \src "ls180.v:559.5-559.48" + wire \main_sdram_bankmachine2_cmd_payload_is_read + attribute \src "ls180.v:560.5-560.49" + wire \main_sdram_bankmachine2_cmd_payload_is_write + attribute \src "ls180.v:556.5-556.44" + wire \main_sdram_bankmachine2_cmd_payload_ras + attribute \src "ls180.v:557.5-557.43" + wire \main_sdram_bankmachine2_cmd_payload_we + attribute \src "ls180.v:552.5-552.38" + wire \main_sdram_bankmachine2_cmd_ready + attribute \src "ls180.v:551.5-551.38" + wire \main_sdram_bankmachine2_cmd_valid + attribute \src "ls180.v:550.5-550.40" + wire \main_sdram_bankmachine2_refresh_gnt + attribute \src "ls180.v:549.6-549.41" + wire \main_sdram_bankmachine2_refresh_req + attribute \src "ls180.v:545.13-545.45" + wire width 22 \main_sdram_bankmachine2_req_addr + attribute \src "ls180.v:546.6-546.38" + wire \main_sdram_bankmachine2_req_lock + attribute \src "ls180.v:548.5-548.44" + wire \main_sdram_bankmachine2_req_rdata_valid + attribute \src "ls180.v:543.6-543.39" + wire \main_sdram_bankmachine2_req_ready + attribute \src "ls180.v:542.6-542.39" + wire \main_sdram_bankmachine2_req_valid + attribute \src "ls180.v:547.5-547.44" + wire \main_sdram_bankmachine2_req_wdata_ready + attribute \src "ls180.v:544.6-544.36" + wire \main_sdram_bankmachine2_req_we + attribute \src "ls180.v:611.12-611.39" + wire width 13 \main_sdram_bankmachine2_row + attribute \src "ls180.v:615.5-615.38" + wire \main_sdram_bankmachine2_row_close + attribute \src "ls180.v:616.5-616.47" + wire \main_sdram_bankmachine2_row_col_n_addr_sel + attribute \src "ls180.v:613.6-613.37" + wire \main_sdram_bankmachine2_row_hit + attribute \src "ls180.v:614.5-614.37" + wire \main_sdram_bankmachine2_row_open + attribute \src "ls180.v:612.5-612.39" + wire \main_sdram_bankmachine2_row_opened + attribute \no_retiming "true" + attribute \src "ls180.v:623.32-623.69" + wire \main_sdram_bankmachine2_trascon_ready + attribute \src "ls180.v:622.6-622.43" + wire \main_sdram_bankmachine2_trascon_valid + attribute \no_retiming "true" + attribute \src "ls180.v:621.32-621.68" + wire \main_sdram_bankmachine2_trccon_ready + attribute \src "ls180.v:620.6-620.42" + wire \main_sdram_bankmachine2_trccon_valid + attribute \src "ls180.v:619.11-619.48" + wire width 3 \main_sdram_bankmachine2_twtpcon_count + attribute \no_retiming "true" + attribute \src "ls180.v:618.32-618.69" + wire \main_sdram_bankmachine2_twtpcon_ready + attribute \src "ls180.v:617.6-617.43" + wire \main_sdram_bankmachine2_twtpcon_valid + attribute \src "ls180.v:643.5-643.43" + wire \main_sdram_bankmachine3_auto_precharge + attribute \src "ls180.v:665.11-665.63" + wire width 3 \main_sdram_bankmachine3_cmd_buffer_lookahead_consume + attribute \src "ls180.v:670.6-670.58" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read + attribute \src "ls180.v:675.6-675.64" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first + attribute \src "ls180.v:676.6-676.63" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last + attribute \src "ls180.v:674.13-674.78" + wire width 22 \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr + attribute \src "ls180.v:673.6-673.69" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we + attribute \src "ls180.v:679.6-679.65" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first + attribute \src "ls180.v:680.6-680.64" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last + attribute \src "ls180.v:678.13-678.79" + wire width 22 \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr + attribute \src "ls180.v:677.6-677.70" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we + attribute \src "ls180.v:662.11-662.61" + wire width 4 \main_sdram_bankmachine3_cmd_buffer_lookahead_level + attribute \src "ls180.v:664.11-664.63" + wire width 3 \main_sdram_bankmachine3_cmd_buffer_lookahead_produce + attribute \src "ls180.v:671.12-671.67" + wire width 3 \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr + attribute \src "ls180.v:672.13-672.70" + wire width 25 \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r + attribute \src "ls180.v:663.5-663.57" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_replace + attribute \src "ls180.v:646.5-646.60" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first + attribute \src "ls180.v:647.5-647.59" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last + attribute \src "ls180.v:649.13-649.75" + wire width 22 \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr + attribute \src "ls180.v:648.6-648.66" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we + attribute \src "ls180.v:645.6-645.61" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_ready + attribute \src "ls180.v:644.6-644.61" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_valid + attribute \src "ls180.v:652.6-652.63" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_source_first + attribute \src "ls180.v:653.6-653.62" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_source_last + attribute \src "ls180.v:655.13-655.77" + wire width 22 \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr + attribute \src "ls180.v:654.6-654.68" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we + attribute \src "ls180.v:651.6-651.63" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_source_ready + attribute \src "ls180.v:650.6-650.63" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_source_valid + attribute \src "ls180.v:660.13-660.71" + wire width 25 \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din + attribute \src "ls180.v:661.13-661.72" + wire width 25 \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout + attribute \src "ls180.v:658.6-658.63" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re + attribute \src "ls180.v:659.6-659.69" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable + attribute \src "ls180.v:656.6-656.63" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we + attribute \src "ls180.v:657.6-657.69" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable + attribute \src "ls180.v:666.11-666.66" + wire width 3 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr + attribute \src "ls180.v:667.13-667.70" + wire width 25 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_r + attribute \src "ls180.v:669.13-669.70" + wire width 25 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w + attribute \src "ls180.v:668.6-668.60" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_we + attribute \src "ls180.v:683.6-683.51" + wire \main_sdram_bankmachine3_cmd_buffer_sink_first + attribute \src "ls180.v:684.6-684.50" + wire \main_sdram_bankmachine3_cmd_buffer_sink_last + attribute \src "ls180.v:686.13-686.65" + wire width 22 \main_sdram_bankmachine3_cmd_buffer_sink_payload_addr + attribute \src "ls180.v:685.6-685.56" + wire \main_sdram_bankmachine3_cmd_buffer_sink_payload_we + attribute \src "ls180.v:682.6-682.51" + wire \main_sdram_bankmachine3_cmd_buffer_sink_ready + attribute \src "ls180.v:681.6-681.51" + wire \main_sdram_bankmachine3_cmd_buffer_sink_valid + attribute \src "ls180.v:689.5-689.52" + wire \main_sdram_bankmachine3_cmd_buffer_source_first + attribute \src "ls180.v:690.5-690.51" + wire \main_sdram_bankmachine3_cmd_buffer_source_last + attribute \src "ls180.v:692.12-692.66" + wire width 22 \main_sdram_bankmachine3_cmd_buffer_source_payload_addr + attribute \src "ls180.v:691.5-691.57" + wire \main_sdram_bankmachine3_cmd_buffer_source_payload_we + attribute \src "ls180.v:688.6-688.53" + wire \main_sdram_bankmachine3_cmd_buffer_source_ready + attribute \src "ls180.v:687.5-687.52" + wire \main_sdram_bankmachine3_cmd_buffer_source_valid + attribute \src "ls180.v:635.12-635.49" + wire width 13 \main_sdram_bankmachine3_cmd_payload_a + attribute \src "ls180.v:636.12-636.50" + wire width 2 \main_sdram_bankmachine3_cmd_payload_ba + attribute \src "ls180.v:637.5-637.44" + wire \main_sdram_bankmachine3_cmd_payload_cas + attribute \src "ls180.v:640.5-640.47" + wire \main_sdram_bankmachine3_cmd_payload_is_cmd + attribute \src "ls180.v:641.5-641.48" + wire \main_sdram_bankmachine3_cmd_payload_is_read + attribute \src "ls180.v:642.5-642.49" + wire \main_sdram_bankmachine3_cmd_payload_is_write + attribute \src "ls180.v:638.5-638.44" + wire \main_sdram_bankmachine3_cmd_payload_ras + attribute \src "ls180.v:639.5-639.43" + wire \main_sdram_bankmachine3_cmd_payload_we + attribute \src "ls180.v:634.5-634.38" + wire \main_sdram_bankmachine3_cmd_ready + attribute \src "ls180.v:633.5-633.38" + wire \main_sdram_bankmachine3_cmd_valid + attribute \src "ls180.v:632.5-632.40" + wire \main_sdram_bankmachine3_refresh_gnt + attribute \src "ls180.v:631.6-631.41" + wire \main_sdram_bankmachine3_refresh_req + attribute \src "ls180.v:627.13-627.45" + wire width 22 \main_sdram_bankmachine3_req_addr + attribute \src "ls180.v:628.6-628.38" + wire \main_sdram_bankmachine3_req_lock + attribute \src "ls180.v:630.5-630.44" + wire \main_sdram_bankmachine3_req_rdata_valid + attribute \src "ls180.v:625.6-625.39" + wire \main_sdram_bankmachine3_req_ready + attribute \src "ls180.v:624.6-624.39" + wire \main_sdram_bankmachine3_req_valid + attribute \src "ls180.v:629.5-629.44" + wire \main_sdram_bankmachine3_req_wdata_ready + attribute \src "ls180.v:626.6-626.36" + wire \main_sdram_bankmachine3_req_we + attribute \src "ls180.v:693.12-693.39" + wire width 13 \main_sdram_bankmachine3_row + attribute \src "ls180.v:697.5-697.38" + wire \main_sdram_bankmachine3_row_close + attribute \src "ls180.v:698.5-698.47" + wire \main_sdram_bankmachine3_row_col_n_addr_sel + attribute \src "ls180.v:695.6-695.37" + wire \main_sdram_bankmachine3_row_hit + attribute \src "ls180.v:696.5-696.37" + wire \main_sdram_bankmachine3_row_open + attribute \src "ls180.v:694.5-694.39" + wire \main_sdram_bankmachine3_row_opened + attribute \no_retiming "true" + attribute \src "ls180.v:705.32-705.69" + wire \main_sdram_bankmachine3_trascon_ready + attribute \src "ls180.v:704.6-704.43" + wire \main_sdram_bankmachine3_trascon_valid + attribute \no_retiming "true" + attribute \src "ls180.v:703.32-703.68" + wire \main_sdram_bankmachine3_trccon_ready + attribute \src "ls180.v:702.6-702.42" + wire \main_sdram_bankmachine3_trccon_valid + attribute \src "ls180.v:701.11-701.48" + wire width 3 \main_sdram_bankmachine3_twtpcon_count + attribute \no_retiming "true" + attribute \src "ls180.v:700.32-700.69" + wire \main_sdram_bankmachine3_twtpcon_ready + attribute \src "ls180.v:699.6-699.43" + wire \main_sdram_bankmachine3_twtpcon_valid + attribute \src "ls180.v:707.6-707.28" + wire \main_sdram_cas_allowed + attribute \src "ls180.v:725.6-725.30" + wire \main_sdram_choose_cmd_ce + attribute \src "ls180.v:714.13-714.48" + wire width 13 \main_sdram_choose_cmd_cmd_payload_a + attribute \src "ls180.v:715.12-715.48" + wire width 2 \main_sdram_choose_cmd_cmd_payload_ba + attribute \src "ls180.v:716.5-716.42" + wire \main_sdram_choose_cmd_cmd_payload_cas + attribute \src "ls180.v:719.6-719.46" + wire \main_sdram_choose_cmd_cmd_payload_is_cmd + attribute \src "ls180.v:720.6-720.47" + wire \main_sdram_choose_cmd_cmd_payload_is_read + attribute \src "ls180.v:721.6-721.48" + wire \main_sdram_choose_cmd_cmd_payload_is_write + attribute \src "ls180.v:717.5-717.42" + wire \main_sdram_choose_cmd_cmd_payload_ras + attribute \src "ls180.v:718.5-718.41" + wire \main_sdram_choose_cmd_cmd_payload_we + attribute \src "ls180.v:713.5-713.36" + wire \main_sdram_choose_cmd_cmd_ready + attribute \src "ls180.v:712.6-712.37" + wire \main_sdram_choose_cmd_cmd_valid + attribute \src "ls180.v:724.11-724.38" + wire width 2 \main_sdram_choose_cmd_grant + attribute \src "ls180.v:723.12-723.41" + wire width 4 \main_sdram_choose_cmd_request + attribute \src "ls180.v:722.11-722.39" + wire width 4 \main_sdram_choose_cmd_valids + attribute \src "ls180.v:711.5-711.41" + wire \main_sdram_choose_cmd_want_activates + attribute \src "ls180.v:710.5-710.36" + wire \main_sdram_choose_cmd_want_cmds + attribute \src "ls180.v:708.5-708.37" + wire \main_sdram_choose_cmd_want_reads + attribute \src "ls180.v:709.5-709.38" + wire \main_sdram_choose_cmd_want_writes + attribute \src "ls180.v:743.6-743.30" + wire \main_sdram_choose_req_ce + attribute \src "ls180.v:732.13-732.48" + wire width 13 \main_sdram_choose_req_cmd_payload_a + attribute \src "ls180.v:733.12-733.48" + wire width 2 \main_sdram_choose_req_cmd_payload_ba + attribute \src "ls180.v:734.5-734.42" + wire \main_sdram_choose_req_cmd_payload_cas + attribute \src "ls180.v:737.6-737.46" + wire \main_sdram_choose_req_cmd_payload_is_cmd + attribute \src "ls180.v:738.6-738.47" + wire \main_sdram_choose_req_cmd_payload_is_read + attribute \src "ls180.v:739.6-739.48" + wire \main_sdram_choose_req_cmd_payload_is_write + attribute \src "ls180.v:735.5-735.42" + wire \main_sdram_choose_req_cmd_payload_ras + attribute \src "ls180.v:736.5-736.41" + wire \main_sdram_choose_req_cmd_payload_we + attribute \src "ls180.v:731.5-731.36" + wire \main_sdram_choose_req_cmd_ready + attribute \src "ls180.v:730.6-730.37" + wire \main_sdram_choose_req_cmd_valid + attribute \src "ls180.v:742.11-742.38" + wire width 2 \main_sdram_choose_req_grant + attribute \src "ls180.v:741.12-741.41" + wire width 4 \main_sdram_choose_req_request + attribute \src "ls180.v:740.11-740.39" + wire width 4 \main_sdram_choose_req_valids + attribute \src "ls180.v:729.5-729.41" + wire \main_sdram_choose_req_want_activates + attribute \src "ls180.v:728.6-728.37" + wire \main_sdram_choose_req_want_cmds + attribute \src "ls180.v:726.5-726.37" + wire \main_sdram_choose_req_want_reads + attribute \src "ls180.v:727.5-727.38" + wire \main_sdram_choose_req_want_writes + attribute \src "ls180.v:287.6-287.20" + wire \main_sdram_cke + attribute \src "ls180.v:355.5-355.24" + wire \main_sdram_cmd_last + attribute \src "ls180.v:356.12-356.36" + wire width 13 \main_sdram_cmd_payload_a + attribute \src "ls180.v:357.11-357.36" + wire width 2 \main_sdram_cmd_payload_ba + attribute \src "ls180.v:358.5-358.31" + wire \main_sdram_cmd_payload_cas + attribute \src "ls180.v:361.5-361.35" + wire \main_sdram_cmd_payload_is_read + attribute \src "ls180.v:362.5-362.36" + wire \main_sdram_cmd_payload_is_write + attribute \src "ls180.v:359.5-359.31" + wire \main_sdram_cmd_payload_ras + attribute \src "ls180.v:360.5-360.30" + wire \main_sdram_cmd_payload_we + attribute \src "ls180.v:354.5-354.25" + wire \main_sdram_cmd_ready + attribute \src "ls180.v:353.5-353.25" + wire \main_sdram_cmd_valid + attribute \src "ls180.v:295.6-295.32" + wire \main_sdram_command_issue_r + attribute \src "ls180.v:294.6-294.33" + wire \main_sdram_command_issue_re + attribute \src "ls180.v:297.5-297.31" + wire \main_sdram_command_issue_w + attribute \src "ls180.v:296.6-296.33" + wire \main_sdram_command_issue_we + attribute \src "ls180.v:293.5-293.26" + wire \main_sdram_command_re + attribute \src "ls180.v:292.11-292.37" + wire width 6 \main_sdram_command_storage + attribute \src "ls180.v:346.5-346.28" + wire \main_sdram_dfi_p0_act_n + attribute \src "ls180.v:337.12-337.37" + wire width 13 \main_sdram_dfi_p0_address + attribute \src "ls180.v:338.11-338.33" + wire width 2 \main_sdram_dfi_p0_bank + attribute \src "ls180.v:339.5-339.28" + wire \main_sdram_dfi_p0_cas_n + attribute \src "ls180.v:343.6-343.27" + wire \main_sdram_dfi_p0_cke + attribute \src "ls180.v:340.5-340.27" + wire \main_sdram_dfi_p0_cs_n + attribute \src "ls180.v:344.6-344.27" + wire \main_sdram_dfi_p0_odt + attribute \src "ls180.v:341.5-341.28" + wire \main_sdram_dfi_p0_ras_n + attribute \src "ls180.v:351.13-351.37" + wire width 16 \main_sdram_dfi_p0_rddata + attribute \src "ls180.v:350.5-350.32" + wire \main_sdram_dfi_p0_rddata_en + attribute \src "ls180.v:352.6-352.36" + wire \main_sdram_dfi_p0_rddata_valid + attribute \src "ls180.v:345.6-345.31" + wire \main_sdram_dfi_p0_reset_n + attribute \src "ls180.v:342.5-342.27" + wire \main_sdram_dfi_p0_we_n + attribute \src "ls180.v:347.13-347.37" + wire width 16 \main_sdram_dfi_p0_wrdata + attribute \src "ls180.v:348.5-348.32" + wire \main_sdram_dfi_p0_wrdata_en + attribute \src "ls180.v:349.12-349.41" + wire width 2 \main_sdram_dfi_p0_wrdata_mask + attribute \src "ls180.v:761.5-761.19" + wire \main_sdram_en0 + attribute \src "ls180.v:764.5-764.19" + wire \main_sdram_en1 + attribute \src "ls180.v:767.6-767.30" + wire \main_sdram_go_to_refresh + attribute \src "ls180.v:309.13-309.44" + wire width 22 \main_sdram_interface_bank0_addr + attribute \src "ls180.v:310.6-310.37" + wire \main_sdram_interface_bank0_lock + attribute \src "ls180.v:312.6-312.44" + wire \main_sdram_interface_bank0_rdata_valid + attribute \src "ls180.v:307.6-307.38" + wire \main_sdram_interface_bank0_ready + attribute \src "ls180.v:306.6-306.38" + wire \main_sdram_interface_bank0_valid + attribute \src "ls180.v:311.6-311.44" + wire \main_sdram_interface_bank0_wdata_ready + attribute \src "ls180.v:308.6-308.35" + wire \main_sdram_interface_bank0_we + attribute \src "ls180.v:316.13-316.44" + wire width 22 \main_sdram_interface_bank1_addr + attribute \src "ls180.v:317.6-317.37" + wire \main_sdram_interface_bank1_lock + attribute \src "ls180.v:319.6-319.44" + wire \main_sdram_interface_bank1_rdata_valid + attribute \src "ls180.v:314.6-314.38" + wire \main_sdram_interface_bank1_ready + attribute \src "ls180.v:313.6-313.38" + wire \main_sdram_interface_bank1_valid + attribute \src "ls180.v:318.6-318.44" + wire \main_sdram_interface_bank1_wdata_ready + attribute \src "ls180.v:315.6-315.35" + wire \main_sdram_interface_bank1_we + attribute \src "ls180.v:323.13-323.44" + wire width 22 \main_sdram_interface_bank2_addr + attribute \src "ls180.v:324.6-324.37" + wire \main_sdram_interface_bank2_lock + attribute \src "ls180.v:326.6-326.44" + wire \main_sdram_interface_bank2_rdata_valid + attribute \src "ls180.v:321.6-321.38" + wire \main_sdram_interface_bank2_ready + attribute \src "ls180.v:320.6-320.38" + wire \main_sdram_interface_bank2_valid + attribute \src "ls180.v:325.6-325.44" + wire \main_sdram_interface_bank2_wdata_ready + attribute \src "ls180.v:322.6-322.35" + wire \main_sdram_interface_bank2_we + attribute \src "ls180.v:330.13-330.44" + wire width 22 \main_sdram_interface_bank3_addr + attribute \src "ls180.v:331.6-331.37" + wire \main_sdram_interface_bank3_lock + attribute \src "ls180.v:333.6-333.44" + wire \main_sdram_interface_bank3_rdata_valid + attribute \src "ls180.v:328.6-328.38" + wire \main_sdram_interface_bank3_ready + attribute \src "ls180.v:327.6-327.38" + wire \main_sdram_interface_bank3_valid + attribute \src "ls180.v:332.6-332.44" + wire \main_sdram_interface_bank3_wdata_ready + attribute \src "ls180.v:329.6-329.35" + wire \main_sdram_interface_bank3_we + attribute \src "ls180.v:336.13-336.39" + wire width 16 \main_sdram_interface_rdata + attribute \src "ls180.v:334.12-334.38" + wire width 16 \main_sdram_interface_wdata + attribute \src "ls180.v:335.11-335.40" + wire width 2 \main_sdram_interface_wdata_we + attribute \src "ls180.v:247.5-247.29" + wire \main_sdram_inti_p0_act_n + attribute \src "ls180.v:238.13-238.39" + wire width 13 \main_sdram_inti_p0_address + attribute \src "ls180.v:239.12-239.35" + wire width 2 \main_sdram_inti_p0_bank + attribute \src "ls180.v:240.5-240.29" + wire \main_sdram_inti_p0_cas_n + attribute \src "ls180.v:244.6-244.28" + wire \main_sdram_inti_p0_cke + attribute \src "ls180.v:241.5-241.28" + wire \main_sdram_inti_p0_cs_n + attribute \src "ls180.v:245.6-245.28" + wire \main_sdram_inti_p0_odt + attribute \src "ls180.v:242.5-242.29" + wire \main_sdram_inti_p0_ras_n + attribute \src "ls180.v:252.12-252.37" + wire width 16 \main_sdram_inti_p0_rddata + attribute \src "ls180.v:251.6-251.34" + wire \main_sdram_inti_p0_rddata_en + attribute \src "ls180.v:253.5-253.36" + wire \main_sdram_inti_p0_rddata_valid + attribute \src "ls180.v:246.6-246.32" + wire \main_sdram_inti_p0_reset_n + attribute \src "ls180.v:243.5-243.28" + wire \main_sdram_inti_p0_we_n + attribute \src "ls180.v:248.13-248.38" + wire width 16 \main_sdram_inti_p0_wrdata + attribute \src "ls180.v:249.6-249.34" + wire \main_sdram_inti_p0_wrdata_en + attribute \src "ls180.v:250.12-250.42" + wire width 2 \main_sdram_inti_p0_wrdata_mask + attribute \src "ls180.v:279.5-279.31" + wire \main_sdram_master_p0_act_n + attribute \src "ls180.v:270.12-270.40" + wire width 13 \main_sdram_master_p0_address + attribute \src "ls180.v:271.11-271.36" + wire width 2 \main_sdram_master_p0_bank + attribute \src "ls180.v:272.5-272.31" + wire \main_sdram_master_p0_cas_n + attribute \src "ls180.v:276.5-276.29" + wire \main_sdram_master_p0_cke + attribute \src "ls180.v:273.5-273.30" + wire \main_sdram_master_p0_cs_n + attribute \src "ls180.v:277.5-277.29" + wire \main_sdram_master_p0_odt + attribute \src "ls180.v:274.5-274.31" + wire \main_sdram_master_p0_ras_n + attribute \src "ls180.v:284.13-284.40" + wire width 16 \main_sdram_master_p0_rddata + attribute \src "ls180.v:283.5-283.35" + wire \main_sdram_master_p0_rddata_en + attribute \src "ls180.v:285.6-285.39" + wire \main_sdram_master_p0_rddata_valid + attribute \src "ls180.v:278.5-278.33" + wire \main_sdram_master_p0_reset_n + attribute \src "ls180.v:275.5-275.30" + wire \main_sdram_master_p0_we_n + attribute \src "ls180.v:280.12-280.39" + wire width 16 \main_sdram_master_p0_wrdata + attribute \src "ls180.v:281.5-281.35" + wire \main_sdram_master_p0_wrdata_en + attribute \src "ls180.v:282.11-282.43" + wire width 2 \main_sdram_master_p0_wrdata_mask + attribute \src "ls180.v:762.6-762.26" + wire \main_sdram_max_time0 + attribute \src "ls180.v:765.6-765.26" + wire \main_sdram_max_time1 + attribute \src "ls180.v:744.12-744.28" + wire width 13 \main_sdram_nop_a + attribute \src "ls180.v:745.11-745.28" + wire width 2 \main_sdram_nop_ba + attribute \src "ls180.v:288.6-288.20" + wire \main_sdram_odt + attribute \src "ls180.v:371.5-371.31" + wire \main_sdram_postponer_count + attribute \src "ls180.v:369.6-369.32" + wire \main_sdram_postponer_req_i + attribute \src "ls180.v:370.5-370.31" + wire \main_sdram_postponer_req_o + attribute \src "ls180.v:706.6-706.28" + wire \main_sdram_ras_allowed + attribute \src "ls180.v:291.5-291.18" + wire \main_sdram_re + attribute \src "ls180.v:759.6-759.31" + wire \main_sdram_read_available + attribute \src "ls180.v:289.6-289.24" + wire \main_sdram_reset_n + attribute \src "ls180.v:286.6-286.20" + wire \main_sdram_sel + attribute \src "ls180.v:377.5-377.31" + wire \main_sdram_sequencer_count + attribute \src "ls180.v:376.11-376.39" + wire width 4 \main_sdram_sequencer_counter + attribute \src "ls180.v:373.6-373.32" + wire \main_sdram_sequencer_done0 + attribute \src "ls180.v:375.5-375.31" + wire \main_sdram_sequencer_done1 + attribute \src "ls180.v:372.5-372.32" + wire \main_sdram_sequencer_start0 + attribute \src "ls180.v:374.6-374.33" + wire \main_sdram_sequencer_start1 + attribute \src "ls180.v:263.6-263.31" + wire \main_sdram_slave_p0_act_n + attribute \src "ls180.v:254.13-254.40" + wire width 13 \main_sdram_slave_p0_address + attribute \src "ls180.v:255.12-255.36" + wire width 2 \main_sdram_slave_p0_bank + attribute \src "ls180.v:256.6-256.31" + wire \main_sdram_slave_p0_cas_n + attribute \src "ls180.v:260.6-260.29" + wire \main_sdram_slave_p0_cke + attribute \src "ls180.v:257.6-257.30" + wire \main_sdram_slave_p0_cs_n + attribute \src "ls180.v:261.6-261.29" + wire \main_sdram_slave_p0_odt + attribute \src "ls180.v:258.6-258.31" + wire \main_sdram_slave_p0_ras_n + attribute \src "ls180.v:268.12-268.38" + wire width 16 \main_sdram_slave_p0_rddata + attribute \src "ls180.v:267.6-267.35" + wire \main_sdram_slave_p0_rddata_en + attribute \src "ls180.v:269.5-269.37" + wire \main_sdram_slave_p0_rddata_valid + attribute \src "ls180.v:262.6-262.33" + wire \main_sdram_slave_p0_reset_n + attribute \src "ls180.v:259.6-259.30" + wire \main_sdram_slave_p0_we_n + attribute \src "ls180.v:264.13-264.39" + wire width 16 \main_sdram_slave_p0_wrdata + attribute \src "ls180.v:265.6-265.35" + wire \main_sdram_slave_p0_wrdata_en + attribute \src "ls180.v:266.12-266.43" + wire width 2 \main_sdram_slave_p0_wrdata_mask + attribute \src "ls180.v:304.12-304.29" + wire width 16 \main_sdram_status + attribute \src "ls180.v:747.5-747.24" + wire \main_sdram_steerer0 + attribute \src "ls180.v:748.5-748.24" + wire \main_sdram_steerer1 + attribute \src "ls180.v:746.11-746.33" + wire width 2 \main_sdram_steerer_sel + attribute \src "ls180.v:290.11-290.29" + wire width 4 \main_sdram_storage + attribute \src "ls180.v:755.5-755.29" + wire \main_sdram_tccdcon_count + attribute \no_retiming "true" + attribute \src "ls180.v:754.32-754.56" + wire \main_sdram_tccdcon_ready + attribute \src "ls180.v:753.6-753.30" + wire \main_sdram_tccdcon_valid + attribute \no_retiming "true" + attribute \src "ls180.v:752.32-752.56" + wire \main_sdram_tfawcon_ready + attribute \src "ls180.v:751.6-751.30" + wire \main_sdram_tfawcon_valid + attribute \src "ls180.v:763.11-763.27" + wire width 5 \main_sdram_time0 + attribute \src "ls180.v:766.11-766.27" + wire width 4 \main_sdram_time1 + attribute \src "ls180.v:366.12-366.35" + wire width 10 \main_sdram_timer_count0 + attribute \src "ls180.v:368.11-368.34" + wire width 10 \main_sdram_timer_count1 + attribute \src "ls180.v:365.6-365.28" + wire \main_sdram_timer_done0 + attribute \src "ls180.v:367.6-367.28" + wire \main_sdram_timer_done1 + attribute \src "ls180.v:364.6-364.27" + wire \main_sdram_timer_wait + attribute \no_retiming "true" + attribute \src "ls180.v:750.32-750.56" + wire \main_sdram_trrdcon_ready + attribute \src "ls180.v:749.6-749.30" + wire \main_sdram_trrdcon_valid + attribute \src "ls180.v:758.11-758.35" + wire width 3 \main_sdram_twtrcon_count + attribute \no_retiming "true" + attribute \src "ls180.v:757.32-757.56" + wire \main_sdram_twtrcon_ready + attribute \src "ls180.v:756.6-756.30" + wire \main_sdram_twtrcon_valid + attribute \src "ls180.v:363.6-363.30" + wire \main_sdram_wants_refresh + attribute \src "ls180.v:305.6-305.19" + wire \main_sdram_we + attribute \src "ls180.v:303.5-303.25" + wire \main_sdram_wrdata_re + attribute \src "ls180.v:302.12-302.37" + wire width 16 \main_sdram_wrdata_storage + attribute \src "ls180.v:760.6-760.32" + wire \main_sdram_write_available + attribute \src "ls180.v:813.6-813.21" + wire \main_sink_first + attribute \src "ls180.v:814.6-814.20" + wire \main_sink_last + attribute \src "ls180.v:815.12-815.34" + wire width 8 \main_sink_payload_data + attribute \src "ls180.v:812.5-812.20" + wire \main_sink_ready + attribute \src "ls180.v:811.6-811.21" + wire \main_sink_valid + attribute \src "ls180.v:823.5-823.22" + wire \main_source_first + attribute \src "ls180.v:824.5-824.21" + wire \main_source_last + attribute \src "ls180.v:825.11-825.35" + wire width 8 \main_source_payload_data + attribute \src "ls180.v:822.6-822.23" + wire \main_source_ready + attribute \src "ls180.v:821.5-821.22" + wire \main_source_valid + attribute \src "ls180.v:968.12-968.40" + wire width 16 \main_spi_master_clk_divider0 + attribute \src "ls180.v:990.12-990.40" + wire width 16 \main_spi_master_clk_divider1 + attribute \src "ls180.v:985.5-985.31" + wire \main_spi_master_clk_enable + attribute \src "ls180.v:992.6-992.30" + wire \main_spi_master_clk_fall + attribute \src "ls180.v:991.6-991.30" + wire \main_spi_master_clk_rise + attribute \src "ls180.v:972.5-972.31" + wire \main_spi_master_control_re + attribute \src "ls180.v:971.12-971.43" + wire width 16 \main_spi_master_control_storage + attribute \src "ls180.v:987.11-987.32" + wire width 3 \main_spi_master_count + attribute \src "ls180.v:1745.11-1745.54" + wire width 3 \main_spi_master_count_spimaster0_next_value + attribute \src "ls180.v:1746.5-1746.51" + wire \main_spi_master_count_spimaster0_next_value_ce + attribute \src "ls180.v:966.6-966.24" + wire \main_spi_master_cs + attribute \src "ls180.v:986.5-986.30" + wire \main_spi_master_cs_enable + attribute \src "ls180.v:982.5-982.26" + wire \main_spi_master_cs_re + attribute \src "ls180.v:981.5-981.31" + wire \main_spi_master_cs_storage + attribute \src "ls180.v:962.5-962.26" + wire \main_spi_master_done0 + attribute \src "ls180.v:973.6-973.27" + wire \main_spi_master_done1 + attribute \src "ls180.v:963.5-963.24" + wire \main_spi_master_irq + attribute \src "ls180.v:961.12-961.35" + wire width 8 \main_spi_master_length0 + attribute \src "ls180.v:970.12-970.35" + wire width 8 \main_spi_master_length1 + attribute \src "ls180.v:967.6-967.30" + wire \main_spi_master_loopback + attribute \src "ls180.v:984.5-984.32" + wire \main_spi_master_loopback_re + attribute \src "ls180.v:983.5-983.37" + wire \main_spi_master_loopback_storage + attribute \src "ls180.v:965.11-965.31" + wire width 8 \main_spi_master_miso + attribute \src "ls180.v:995.11-995.36" + wire width 8 \main_spi_master_miso_data + attribute \src "ls180.v:989.5-989.31" + wire \main_spi_master_miso_latch + attribute \src "ls180.v:978.12-978.39" + wire width 8 \main_spi_master_miso_status + attribute \src "ls180.v:979.6-979.29" + wire \main_spi_master_miso_we + attribute \src "ls180.v:964.12-964.32" + wire width 8 \main_spi_master_mosi + attribute \src "ls180.v:993.11-993.36" + wire width 8 \main_spi_master_mosi_data + attribute \src "ls180.v:988.5-988.31" + wire \main_spi_master_mosi_latch + attribute \src "ls180.v:977.5-977.28" + wire \main_spi_master_mosi_re + attribute \src "ls180.v:994.11-994.35" + wire width 3 \main_spi_master_mosi_sel + attribute \src "ls180.v:976.11-976.39" + wire width 8 \main_spi_master_mosi_storage + attribute \src "ls180.v:980.6-980.25" + wire \main_spi_master_sel + attribute \src "ls180.v:960.6-960.28" + wire \main_spi_master_start0 + attribute \src "ls180.v:969.5-969.27" + wire \main_spi_master_start1 + attribute \src "ls180.v:974.6-974.35" + wire \main_spi_master_status_status + attribute \src "ls180.v:975.6-975.31" + wire \main_spi_master_status_we + attribute \src "ls180.v:809.12-809.24" + wire width 32 \main_storage + attribute \src "ls180.v:819.11-819.27" + wire width 4 \main_tx_bitcount + attribute \src "ls180.v:820.5-820.17" + wire \main_tx_busy + attribute \src "ls180.v:818.11-818.22" + wire width 8 \main_tx_reg + attribute \src "ls180.v:826.5-826.23" + wire \main_uart_clk_rxen + attribute \src "ls180.v:816.5-816.23" + wire \main_uart_clk_txen + attribute \src "ls180.v:857.12-857.44" + wire width 2 \main_uart_eventmanager_pending_r + attribute \src "ls180.v:856.6-856.39" + wire \main_uart_eventmanager_pending_re + attribute \src "ls180.v:859.11-859.43" + wire width 2 \main_uart_eventmanager_pending_w + attribute \src "ls180.v:858.6-858.39" + wire \main_uart_eventmanager_pending_we + attribute \src "ls180.v:861.5-861.30" + wire \main_uart_eventmanager_re + attribute \src "ls180.v:853.12-853.43" + wire width 2 \main_uart_eventmanager_status_r + attribute \src "ls180.v:852.6-852.38" + wire \main_uart_eventmanager_status_re + attribute \src "ls180.v:855.11-855.42" + wire width 2 \main_uart_eventmanager_status_w + attribute \src "ls180.v:854.6-854.38" + wire \main_uart_eventmanager_status_we + attribute \src "ls180.v:860.11-860.41" + wire width 2 \main_uart_eventmanager_storage + attribute \src "ls180.v:841.6-841.19" + wire \main_uart_irq + attribute \src "ls180.v:950.5-950.20" + wire \main_uart_reset + attribute \src "ls180.v:850.5-850.23" + wire \main_uart_rx_clear + attribute \src "ls180.v:934.11-934.36" + wire width 4 \main_uart_rx_fifo_consume + attribute \src "ls180.v:939.6-939.31" + wire \main_uart_rx_fifo_do_read + attribute \src "ls180.v:945.6-945.37" + wire \main_uart_rx_fifo_fifo_in_first + attribute \src "ls180.v:946.6-946.36" + wire \main_uart_rx_fifo_fifo_in_last + attribute \src "ls180.v:944.12-944.50" + wire width 8 \main_uart_rx_fifo_fifo_in_payload_data + attribute \src "ls180.v:948.6-948.38" + wire \main_uart_rx_fifo_fifo_out_first + attribute \src "ls180.v:949.6-949.37" + wire \main_uart_rx_fifo_fifo_out_last + attribute \src "ls180.v:947.12-947.51" + wire width 8 \main_uart_rx_fifo_fifo_out_payload_data + attribute \src "ls180.v:931.11-931.35" + wire width 5 \main_uart_rx_fifo_level0 + attribute \src "ls180.v:943.12-943.36" + wire width 5 \main_uart_rx_fifo_level1 + attribute \src "ls180.v:933.11-933.36" + wire width 4 \main_uart_rx_fifo_produce + attribute \src "ls180.v:940.12-940.40" + wire width 4 \main_uart_rx_fifo_rdport_adr + attribute \src "ls180.v:941.12-941.42" + wire width 10 \main_uart_rx_fifo_rdport_dat_r + attribute \src "ls180.v:942.6-942.33" + wire \main_uart_rx_fifo_rdport_re + attribute \src "ls180.v:923.6-923.26" + wire \main_uart_rx_fifo_re + attribute \src "ls180.v:924.5-924.31" + wire \main_uart_rx_fifo_readable + attribute \src "ls180.v:932.5-932.30" + wire \main_uart_rx_fifo_replace + attribute \src "ls180.v:915.6-915.34" + wire \main_uart_rx_fifo_sink_first + attribute \src "ls180.v:916.6-916.33" + wire \main_uart_rx_fifo_sink_last + attribute \src "ls180.v:917.12-917.47" + wire width 8 \main_uart_rx_fifo_sink_payload_data + attribute \src "ls180.v:914.6-914.34" + wire \main_uart_rx_fifo_sink_ready + attribute \src "ls180.v:913.6-913.34" + wire \main_uart_rx_fifo_sink_valid + attribute \src "ls180.v:920.6-920.36" + wire \main_uart_rx_fifo_source_first + attribute \src "ls180.v:921.6-921.35" + wire \main_uart_rx_fifo_source_last + attribute \src "ls180.v:922.12-922.49" + wire width 8 \main_uart_rx_fifo_source_payload_data + attribute \src "ls180.v:919.6-919.36" + wire \main_uart_rx_fifo_source_ready + attribute \src "ls180.v:918.6-918.36" + wire \main_uart_rx_fifo_source_valid + attribute \src "ls180.v:929.12-929.42" + wire width 10 \main_uart_rx_fifo_syncfifo_din + attribute \src "ls180.v:930.12-930.43" + wire width 10 \main_uart_rx_fifo_syncfifo_dout + attribute \src "ls180.v:927.6-927.35" + wire \main_uart_rx_fifo_syncfifo_re + attribute \src "ls180.v:928.6-928.41" + wire \main_uart_rx_fifo_syncfifo_readable + attribute \src "ls180.v:925.6-925.35" + wire \main_uart_rx_fifo_syncfifo_we + attribute \src "ls180.v:926.6-926.41" + wire \main_uart_rx_fifo_syncfifo_writable + attribute \src "ls180.v:935.11-935.39" + wire width 4 \main_uart_rx_fifo_wrport_adr + attribute \src "ls180.v:936.12-936.42" + wire width 10 \main_uart_rx_fifo_wrport_dat_r + attribute \src "ls180.v:938.12-938.42" + wire width 10 \main_uart_rx_fifo_wrport_dat_w + attribute \src "ls180.v:937.6-937.33" + wire \main_uart_rx_fifo_wrport_we + attribute \src "ls180.v:851.5-851.29" + wire \main_uart_rx_old_trigger + attribute \src "ls180.v:848.5-848.25" + wire \main_uart_rx_pending + attribute \src "ls180.v:847.6-847.25" + wire \main_uart_rx_status + attribute \src "ls180.v:849.6-849.26" + wire \main_uart_rx_trigger + attribute \src "ls180.v:839.6-839.30" + wire \main_uart_rxempty_status + attribute \src "ls180.v:840.6-840.26" + wire \main_uart_rxempty_we + attribute \src "ls180.v:864.6-864.29" + wire \main_uart_rxfull_status + attribute \src "ls180.v:865.6-865.25" + wire \main_uart_rxfull_we + attribute \src "ls180.v:834.12-834.28" + wire width 8 \main_uart_rxtx_r + attribute \src "ls180.v:833.6-833.23" + wire \main_uart_rxtx_re + attribute \src "ls180.v:836.12-836.28" + wire width 8 \main_uart_rxtx_w + attribute \src "ls180.v:835.6-835.23" + wire \main_uart_rxtx_we + attribute \src "ls180.v:845.5-845.23" + wire \main_uart_tx_clear + attribute \src "ls180.v:897.11-897.36" + wire width 4 \main_uart_tx_fifo_consume + attribute \src "ls180.v:902.6-902.31" + wire \main_uart_tx_fifo_do_read + attribute \src "ls180.v:908.6-908.37" + wire \main_uart_tx_fifo_fifo_in_first + attribute \src "ls180.v:909.6-909.36" + wire \main_uart_tx_fifo_fifo_in_last + attribute \src "ls180.v:907.12-907.50" + wire width 8 \main_uart_tx_fifo_fifo_in_payload_data + attribute \src "ls180.v:911.6-911.38" + wire \main_uart_tx_fifo_fifo_out_first + attribute \src "ls180.v:912.6-912.37" + wire \main_uart_tx_fifo_fifo_out_last + attribute \src "ls180.v:910.12-910.51" + wire width 8 \main_uart_tx_fifo_fifo_out_payload_data + attribute \src "ls180.v:894.11-894.35" + wire width 5 \main_uart_tx_fifo_level0 + attribute \src "ls180.v:906.12-906.36" + wire width 5 \main_uart_tx_fifo_level1 + attribute \src "ls180.v:896.11-896.36" + wire width 4 \main_uart_tx_fifo_produce + attribute \src "ls180.v:903.12-903.40" + wire width 4 \main_uart_tx_fifo_rdport_adr + attribute \src "ls180.v:904.12-904.42" + wire width 10 \main_uart_tx_fifo_rdport_dat_r + attribute \src "ls180.v:905.6-905.33" + wire \main_uart_tx_fifo_rdport_re + attribute \src "ls180.v:886.6-886.26" + wire \main_uart_tx_fifo_re + attribute \src "ls180.v:887.5-887.31" + wire \main_uart_tx_fifo_readable + attribute \src "ls180.v:895.5-895.30" + wire \main_uart_tx_fifo_replace + attribute \src "ls180.v:878.5-878.33" + wire \main_uart_tx_fifo_sink_first + attribute \src "ls180.v:879.5-879.32" + wire \main_uart_tx_fifo_sink_last + attribute \src "ls180.v:880.12-880.47" + wire width 8 \main_uart_tx_fifo_sink_payload_data + attribute \src "ls180.v:877.6-877.34" + wire \main_uart_tx_fifo_sink_ready + attribute \src "ls180.v:876.6-876.34" + wire \main_uart_tx_fifo_sink_valid + attribute \src "ls180.v:883.6-883.36" + wire \main_uart_tx_fifo_source_first + attribute \src "ls180.v:884.6-884.35" + wire \main_uart_tx_fifo_source_last + attribute \src "ls180.v:885.12-885.49" + wire width 8 \main_uart_tx_fifo_source_payload_data + attribute \src "ls180.v:882.6-882.36" + wire \main_uart_tx_fifo_source_ready + attribute \src "ls180.v:881.6-881.36" + wire \main_uart_tx_fifo_source_valid + attribute \src "ls180.v:892.12-892.42" + wire width 10 \main_uart_tx_fifo_syncfifo_din + attribute \src "ls180.v:893.12-893.43" + wire width 10 \main_uart_tx_fifo_syncfifo_dout + attribute \src "ls180.v:890.6-890.35" + wire \main_uart_tx_fifo_syncfifo_re + attribute \src "ls180.v:891.6-891.41" + wire \main_uart_tx_fifo_syncfifo_readable + attribute \src "ls180.v:888.6-888.35" + wire \main_uart_tx_fifo_syncfifo_we + attribute \src "ls180.v:889.6-889.41" + wire \main_uart_tx_fifo_syncfifo_writable + attribute \src "ls180.v:898.11-898.39" + wire width 4 \main_uart_tx_fifo_wrport_adr + attribute \src "ls180.v:899.12-899.42" + wire width 10 \main_uart_tx_fifo_wrport_dat_r + attribute \src "ls180.v:901.12-901.42" + wire width 10 \main_uart_tx_fifo_wrport_dat_w + attribute \src "ls180.v:900.6-900.33" + wire \main_uart_tx_fifo_wrport_we + attribute \src "ls180.v:846.5-846.29" + wire \main_uart_tx_old_trigger + attribute \src "ls180.v:843.5-843.25" + wire \main_uart_tx_pending + attribute \src "ls180.v:842.6-842.25" + wire \main_uart_tx_status + attribute \src "ls180.v:844.6-844.26" + wire \main_uart_tx_trigger + attribute \src "ls180.v:862.6-862.30" + wire \main_uart_txempty_status + attribute \src "ls180.v:863.6-863.26" + wire \main_uart_txempty_we + attribute \src "ls180.v:837.6-837.29" + wire \main_uart_txfull_status + attribute \src "ls180.v:838.6-838.25" + wire \main_uart_txfull_we + attribute \src "ls180.v:868.6-868.31" + wire \main_uart_uart_sink_first + attribute \src "ls180.v:869.6-869.30" + wire \main_uart_uart_sink_last + attribute \src "ls180.v:870.12-870.44" + wire width 8 \main_uart_uart_sink_payload_data + attribute \src "ls180.v:867.6-867.31" + wire \main_uart_uart_sink_ready + attribute \src "ls180.v:866.6-866.31" + wire \main_uart_uart_sink_valid + attribute \src "ls180.v:873.6-873.33" + wire \main_uart_uart_source_first + attribute \src "ls180.v:874.6-874.32" + wire \main_uart_uart_source_last + attribute \src "ls180.v:875.12-875.46" + wire width 8 \main_uart_uart_source_payload_data + attribute \src "ls180.v:872.6-872.33" + wire \main_uart_uart_source_ready + attribute \src "ls180.v:871.6-871.33" + wire \main_uart_uart_source_valid + attribute \src "ls180.v:787.5-787.22" + wire \main_wb_sdram_ack + attribute \src "ls180.v:781.13-781.30" + wire width 30 \main_wb_sdram_adr + attribute \src "ls180.v:790.12-790.29" + wire width 2 \main_wb_sdram_bte + attribute \src "ls180.v:789.12-789.29" + wire width 3 \main_wb_sdram_cti + attribute \src "ls180.v:785.6-785.23" + wire \main_wb_sdram_cyc + attribute \src "ls180.v:783.13-783.32" + wire width 32 \main_wb_sdram_dat_r + attribute \src "ls180.v:782.13-782.32" + wire width 32 \main_wb_sdram_dat_w + attribute \src "ls180.v:791.5-791.22" + wire \main_wb_sdram_err + attribute \src "ls180.v:784.12-784.29" + wire width 4 \main_wb_sdram_sel + attribute \src "ls180.v:786.6-786.23" + wire \main_wb_sdram_stb + attribute \src "ls180.v:788.6-788.22" + wire \main_wb_sdram_we + attribute \src "ls180.v:805.5-805.24" + wire \main_wdata_consumed + attribute \src "ls180.v:9976.11-9976.17" + wire width 7 \memadr + attribute \src "ls180.v:9996.12-9996.18" + wire width 25 \memdat + attribute \src "ls180.v:10010.12-10010.20" + wire width 25 \memdat_1 + attribute \src "ls180.v:10024.12-10024.20" + wire width 25 \memdat_2 + attribute \src "ls180.v:10038.12-10038.20" + wire width 25 \memdat_3 + attribute \src "ls180.v:10052.11-10052.19" + wire width 10 \memdat_4 + attribute \src "ls180.v:10053.11-10053.19" + wire width 10 \memdat_5 + attribute \src "ls180.v:10069.11-10069.19" + wire width 10 \memdat_6 + attribute \src "ls180.v:10070.11-10070.19" + wire width 10 \memdat_7 + attribute \src "ls180.v:10086.11-10086.19" + wire width 10 \memdat_8 + attribute \src "ls180.v:10100.11-10100.19" + wire width 10 \memdat_9 + attribute \src "ls180.v:33.20-33.22" + wire width 42 input 29 \nc + attribute \src "ls180.v:219.6-219.13" + wire \por_clk + attribute \src "ls180.v:34.13-34.17" + wire output 30 \pwm0 + attribute \src "ls180.v:35.13-35.17" + wire output 31 \pwm1 + attribute \src "ls180.v:36.13-36.23" + wire output 32 \sdcard_clk + attribute \src "ls180.v:37.13-37.25" + wire input 33 \sdcard_cmd_i + attribute \src "ls180.v:38.13-38.25" + wire output 34 \sdcard_cmd_o + attribute \src "ls180.v:39.13-39.26" + wire output 35 \sdcard_cmd_oe + attribute \src "ls180.v:40.19-40.32" + wire width 4 input 36 \sdcard_data_i + attribute \src "ls180.v:41.19-41.32" + wire width 4 output 37 \sdcard_data_o + attribute \src "ls180.v:42.13-42.27" + wire output 38 \sdcard_data_oe + attribute \src "ls180.v:7.20-7.27" + wire width 13 output 3 \sdram_a + attribute \src "ls180.v:16.19-16.27" + wire width 2 output 12 \sdram_ba + attribute \src "ls180.v:13.13-13.24" + wire output 9 \sdram_cas_n + attribute \src "ls180.v:15.13-15.22" + wire output 11 \sdram_cke + attribute \src "ls180.v:18.13-18.24" + wire output 14 \sdram_clock + attribute \src "ls180.v:14.13-14.23" + wire output 10 \sdram_cs_n + attribute \src "ls180.v:17.19-17.27" + wire width 2 output 13 \sdram_dm + attribute \src "ls180.v:8.20-8.30" + wire width 16 input 4 \sdram_dq_i + attribute \src "ls180.v:9.20-9.30" + wire width 16 output 5 \sdram_dq_o + attribute \src "ls180.v:10.13-10.24" + wire output 6 \sdram_dq_oe + attribute \src "ls180.v:12.13-12.24" + wire output 8 \sdram_ras_n + attribute \src "ls180.v:11.13-11.23" + wire output 7 \sdram_we_n + attribute \src "ls180.v:2594.6-2594.15" + wire \sdrio_clk + attribute \src "ls180.v:2595.6-2595.17" + wire \sdrio_clk_1 + attribute \src "ls180.v:2604.6-2604.18" + wire \sdrio_clk_10 + attribute \src "ls180.v:2605.6-2605.18" + wire \sdrio_clk_11 + attribute \src "ls180.v:2606.6-2606.18" + wire \sdrio_clk_12 + attribute \src "ls180.v:2607.6-2607.18" + wire \sdrio_clk_13 + attribute \src "ls180.v:2608.6-2608.18" + wire \sdrio_clk_14 + attribute \src "ls180.v:2609.6-2609.18" + wire \sdrio_clk_15 + attribute \src "ls180.v:2610.6-2610.18" + wire \sdrio_clk_16 + attribute \src "ls180.v:2611.6-2611.18" + wire \sdrio_clk_17 + attribute \src "ls180.v:2612.6-2612.18" + wire \sdrio_clk_18 + attribute \src "ls180.v:2613.6-2613.18" + wire \sdrio_clk_19 + attribute \src "ls180.v:2596.6-2596.17" + wire \sdrio_clk_2 + attribute \src "ls180.v:2614.6-2614.18" + wire \sdrio_clk_20 + attribute \src "ls180.v:2615.6-2615.18" + wire \sdrio_clk_21 + attribute \src "ls180.v:2616.6-2616.18" + wire \sdrio_clk_22 + attribute \src "ls180.v:2617.6-2617.18" + wire \sdrio_clk_23 + attribute \src "ls180.v:2618.6-2618.18" + wire \sdrio_clk_24 + attribute \src "ls180.v:2619.6-2619.18" + wire \sdrio_clk_25 + attribute \src "ls180.v:2620.6-2620.18" + wire \sdrio_clk_26 + attribute \src "ls180.v:2621.6-2621.18" + wire \sdrio_clk_27 + attribute \src "ls180.v:2622.6-2622.18" + wire \sdrio_clk_28 + attribute \src "ls180.v:2623.6-2623.18" + wire \sdrio_clk_29 + attribute \src "ls180.v:2597.6-2597.17" + wire \sdrio_clk_3 + attribute \src "ls180.v:2624.6-2624.18" + wire \sdrio_clk_30 + attribute \src "ls180.v:2625.6-2625.18" + wire \sdrio_clk_31 + attribute \src "ls180.v:2626.6-2626.18" + wire \sdrio_clk_32 + attribute \src "ls180.v:2627.6-2627.18" + wire \sdrio_clk_33 + attribute \src "ls180.v:2628.6-2628.18" + wire \sdrio_clk_34 + attribute \src "ls180.v:2629.6-2629.18" + wire \sdrio_clk_35 + attribute \src "ls180.v:2630.6-2630.18" + wire \sdrio_clk_36 + attribute \src "ls180.v:2631.6-2631.18" + wire \sdrio_clk_37 + attribute \src "ls180.v:2632.6-2632.18" + wire \sdrio_clk_38 + attribute \src "ls180.v:2633.6-2633.18" + wire \sdrio_clk_39 + attribute \src "ls180.v:2598.6-2598.17" + wire \sdrio_clk_4 + attribute \src "ls180.v:2634.6-2634.18" + wire \sdrio_clk_40 + attribute \src "ls180.v:2635.6-2635.18" + wire \sdrio_clk_41 + attribute \src "ls180.v:2636.6-2636.18" + wire \sdrio_clk_42 + attribute \src "ls180.v:2637.6-2637.18" + wire \sdrio_clk_43 + attribute \src "ls180.v:2638.6-2638.18" + wire \sdrio_clk_44 + attribute \src "ls180.v:2639.6-2639.18" + wire \sdrio_clk_45 + attribute \src "ls180.v:2640.6-2640.18" + wire \sdrio_clk_46 + attribute \src "ls180.v:2641.6-2641.18" + wire \sdrio_clk_47 + attribute \src "ls180.v:2642.6-2642.18" + wire \sdrio_clk_48 + attribute \src "ls180.v:2643.6-2643.18" + wire \sdrio_clk_49 + attribute \src "ls180.v:2599.6-2599.17" + wire \sdrio_clk_5 + attribute \src "ls180.v:2644.6-2644.18" + wire \sdrio_clk_50 + attribute \src "ls180.v:2645.6-2645.18" + wire \sdrio_clk_51 + attribute \src "ls180.v:2646.6-2646.18" + wire \sdrio_clk_52 + attribute \src "ls180.v:2647.6-2647.18" + wire \sdrio_clk_53 + attribute \src "ls180.v:2648.6-2648.18" + wire \sdrio_clk_54 + attribute \src "ls180.v:2649.6-2649.18" + wire \sdrio_clk_55 + attribute \src "ls180.v:2684.6-2684.18" + wire \sdrio_clk_56 + attribute \src "ls180.v:2685.6-2685.18" + wire \sdrio_clk_57 + attribute \src "ls180.v:2686.6-2686.18" + wire \sdrio_clk_58 + attribute \src "ls180.v:2687.6-2687.18" + wire \sdrio_clk_59 + attribute \src "ls180.v:2600.6-2600.17" + wire \sdrio_clk_6 + attribute \src "ls180.v:2688.6-2688.18" + wire \sdrio_clk_60 + attribute \src "ls180.v:2689.6-2689.18" + wire \sdrio_clk_61 + attribute \src "ls180.v:2690.6-2690.18" + wire \sdrio_clk_62 + attribute \src "ls180.v:2691.6-2691.18" + wire \sdrio_clk_63 + attribute \src "ls180.v:2692.6-2692.18" + wire \sdrio_clk_64 + attribute \src "ls180.v:2693.6-2693.18" + wire \sdrio_clk_65 + attribute \src "ls180.v:2694.6-2694.18" + wire \sdrio_clk_66 + attribute \src "ls180.v:2695.6-2695.18" + wire \sdrio_clk_67 + attribute \src "ls180.v:2696.6-2696.18" + wire \sdrio_clk_68 + attribute \src "ls180.v:2601.6-2601.17" + wire \sdrio_clk_7 + attribute \src "ls180.v:2602.6-2602.17" + wire \sdrio_clk_8 + attribute \src "ls180.v:2603.6-2603.17" + wire \sdrio_clk_9 + attribute \src "ls180.v:24.13-24.27" + wire output 20 \spi_master_clk + attribute \src "ls180.v:26.13-26.28" + wire output 22 \spi_master_cs_n + attribute \src "ls180.v:27.13-27.28" + wire input 23 \spi_master_miso + attribute \src "ls180.v:25.13-25.28" + wire output 21 \spi_master_mosi + attribute \src "ls180.v:43.13-43.26" + wire output 39 \spisdcard_clk + attribute \src "ls180.v:45.13-45.27" + wire output 41 \spisdcard_cs_n + attribute \src "ls180.v:46.13-46.27" + wire input 42 \spisdcard_miso + attribute \src "ls180.v:44.13-44.27" + wire output 40 \spisdcard_mosi + attribute \src "ls180.v:5.13-5.20" + wire input 1 \sys_clk + attribute \src "ls180.v:217.6-217.15" + wire \sys_clk_1 + attribute \src "ls180.v:6.13-6.20" + wire input 2 \sys_rst + attribute \src "ls180.v:218.6-218.15" + wire \sys_rst_1 + attribute \src "ls180.v:20.13-20.20" + wire input 16 \uart_rx + attribute \src "ls180.v:19.14-19.21" + wire output 15 \uart_tx + attribute \src "ls180.v:9975.12-9975.15" + memory width 32 size 128 \mem + attribute \src "ls180.v:9995.12-9995.19" + memory width 25 size 8 \storage + attribute \src "ls180.v:10009.12-10009.21" + memory width 25 size 8 \storage_1 + attribute \src "ls180.v:10023.12-10023.21" + memory width 25 size 8 \storage_2 + attribute \src "ls180.v:10037.12-10037.21" + memory width 25 size 8 \storage_3 + attribute \src "ls180.v:10051.11-10051.20" + memory width 10 size 16 \storage_4 + attribute \src "ls180.v:10068.11-10068.20" + memory width 10 size 16 \storage_5 + attribute \src "ls180.v:10085.11-10085.20" + memory width 10 size 32 \storage_6 + attribute \src "ls180.v:10099.11-10099.20" + memory width 10 size 32 \storage_7 + attribute \src "ls180.v:2768.68-2768.110" + cell $add $add$ls180.v:2768$22 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_converter0_counter + connect \B 1'1 + connect \Y $add$ls180.v:2768$22_Y + end + attribute \src "ls180.v:2828.68-2828.110" + cell $add $add$ls180.v:2828$33 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_converter1_counter + connect \B 1'1 + connect \Y $add$ls180.v:2828$33_Y + end + attribute \src "ls180.v:2888.68-2888.110" + cell $add $add$ls180.v:2888$44 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_converter2_counter + connect \B 1'1 + connect \Y $add$ls180.v:2888$44_Y + end + attribute \src "ls180.v:4021.54-4021.83" + cell $add $add$ls180.v:4021$537 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_converter_counter + connect \B 1'1 + connect \Y $add$ls180.v:4021$537_Y + end + attribute \src "ls180.v:4121.36-4121.89" + cell $add $add$ls180.v:4121$583 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 5 + connect \A \main_uart_tx_fifo_level0 + connect \B \main_uart_tx_fifo_readable + connect \Y $add$ls180.v:4121$583_Y + end + attribute \src "ls180.v:4151.36-4151.89" + cell $add $add$ls180.v:4151$594 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 5 + connect \A \main_uart_rx_fifo_level0 + connect \B \main_uart_rx_fifo_readable + connect \Y $add$ls180.v:4151$594_Y + end + attribute \src "ls180.v:4206.53-4206.81" + cell $add $add$ls180.v:4206$607 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_spi_master_count + connect \B 1'1 + connect \Y $add$ls180.v:4206$607_Y + end + attribute \src "ls180.v:4306.58-4306.86" + cell $add $add$ls180.v:4306$635 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 8 + connect \A \main_sdphy_init_count + connect \B 1'1 + connect \Y $add$ls180.v:4306$635_Y + end + attribute \src "ls180.v:4363.58-4363.86" + cell $add $add$ls180.v:4363$638 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 8 + connect \A \main_sdphy_cmdw_count + connect \B 1'1 + connect \Y $add$ls180.v:4363$638_Y + end + attribute \src "ls180.v:4380.58-4380.86" + cell $add $add$ls180.v:4380$640 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 8 + connect \A \main_sdphy_cmdw_count + connect \B 1'1 + connect \Y $add$ls180.v:4380$640_Y + end + attribute \src "ls180.v:4473.59-4473.87" + cell $add $add$ls180.v:4473$657 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 8 + connect \A \main_sdphy_cmdr_count + connect \B 1'1 + connect \Y $add$ls180.v:4473$657_Y + end + attribute \src "ls180.v:4498.59-4498.87" + cell $add $add$ls180.v:4498$660 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 8 + connect \A \main_sdphy_cmdr_count + connect \B 1'1 + connect \Y $add$ls180.v:4498$660_Y + end + attribute \src "ls180.v:4620.53-4620.82" + cell $add $add$ls180.v:4620$677 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 8 + connect \A \main_sdphy_dataw_count + connect \B 1'1 + connect \Y $add$ls180.v:4620$677_Y + end + attribute \src "ls180.v:4731.65-4731.114" + cell $add $add$ls180.v:4731$691 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 10 + connect \A \main_sdphy_datar_sink_payload_block_length + connect \B 4'1000 + connect \Y $add$ls180.v:4731$691_Y + end + attribute \src "ls180.v:4736.62-4736.91" + cell $add $add$ls180.v:4736$694 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 10 + connect \A \main_sdphy_datar_count + connect \B 1'1 + connect \Y $add$ls180.v:4736$694_Y + end + attribute \src "ls180.v:4762.61-4762.90" + cell $add $add$ls180.v:4762$697 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 10 + connect \A \main_sdphy_datar_count + connect \B 1'1 + connect \Y $add$ls180.v:4762$697_Y + end + attribute \src "ls180.v:4966.80-4966.117" + cell $add $add$ls180.v:4966$882 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdcore_crc16_inserter_cnt + connect \B 1'1 + connect \Y $add$ls180.v:4966$882_Y + end + attribute \src "ls180.v:5160.54-5160.82" + cell $add $add$ls180.v:5160$957 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdcore_cmd_count + connect \B 1'1 + connect \Y $add$ls180.v:5160$957_Y + end + attribute \src "ls180.v:5212.55-5212.84" + cell $add $add$ls180.v:5212$967 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_sdcore_data_count + connect \B 1'1 + connect \Y $add$ls180.v:5212$967_Y + end + attribute \src "ls180.v:5238.57-5238.86" + cell $add $add$ls180.v:5238$975 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_sdcore_data_count + connect \B 1'1 + connect \Y $add$ls180.v:5238$975_Y + end + attribute \src "ls180.v:5359.51-5359.134" + cell $add $add$ls180.v:5359$991 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A \main_sdblock2mem_wishbonedmawriter_base + connect \B \main_sdblock2mem_wishbonedmawriter_offset + connect \Y $add$ls180.v:5359$991_Y + end + attribute \src "ls180.v:5362.77-5362.125" + cell $add $add$ls180.v:5362$993 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_sdblock2mem_wishbonedmawriter_offset + connect \B 1'1 + connect \Y $add$ls180.v:5362$993_Y + end + attribute \src "ls180.v:5455.50-5455.105" + cell $add $add$ls180.v:5455$1002 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A \main_sdmem2block_dma_base + connect \B \main_sdmem2block_dma_offset + connect \Y $add$ls180.v:5455$1002_Y + end + attribute \src "ls180.v:5457.77-5457.111" + cell $add $add$ls180.v:5457$1003 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_sdmem2block_dma_offset + connect \B 1'1 + connect \Y $add$ls180.v:5457$1003_Y + end + attribute \src "ls180.v:5569.49-5569.73" + cell $add $add$ls180.v:5569$1022 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \libresocsim_count + connect \B 1'1 + connect \Y $add$ls180.v:5569$1022_Y + end + attribute \src "ls180.v:7437.36-7437.70" + cell $add $add$ls180.v:7437$2405 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_libresocsim_bus_errors + connect \B 1'1 + connect \Y $add$ls180.v:7437$2405_Y + end + attribute \src "ls180.v:7522.37-7522.72" + cell $add $add$ls180.v:7522$2426 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_sdram_sequencer_counter + connect \B 1'1 + connect \Y $add$ls180.v:7522$2426_Y + end + attribute \src "ls180.v:7539.60-7539.119" + cell $add $add$ls180.v:7539$2430 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_produce + connect \B 1'1 + connect \Y $add$ls180.v:7539$2430_Y + end + attribute \src "ls180.v:7542.60-7542.119" + cell $add $add$ls180.v:7542$2431 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_consume + connect \B 1'1 + connect \Y $add$ls180.v:7542$2431_Y + end + attribute \src "ls180.v:7546.59-7546.116" + cell $add $add$ls180.v:7546$2436 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_level + connect \B 1'1 + connect \Y $add$ls180.v:7546$2436_Y + end + attribute \src "ls180.v:7585.60-7585.119" + cell $add $add$ls180.v:7585$2446 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_produce + connect \B 1'1 + connect \Y $add$ls180.v:7585$2446_Y + end + attribute \src "ls180.v:7588.60-7588.119" + cell $add $add$ls180.v:7588$2447 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_consume + connect \B 1'1 + connect \Y $add$ls180.v:7588$2447_Y + end + attribute \src "ls180.v:7592.59-7592.116" + cell $add $add$ls180.v:7592$2452 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_level + connect \B 1'1 + connect \Y $add$ls180.v:7592$2452_Y + end + attribute \src "ls180.v:7631.60-7631.119" + cell $add $add$ls180.v:7631$2462 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_produce + connect \B 1'1 + connect \Y $add$ls180.v:7631$2462_Y + end + attribute \src "ls180.v:7634.60-7634.119" + cell $add $add$ls180.v:7634$2463 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_consume + connect \B 1'1 + connect \Y $add$ls180.v:7634$2463_Y + end + attribute \src "ls180.v:7638.59-7638.116" + cell $add $add$ls180.v:7638$2468 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_level + connect \B 1'1 + connect \Y $add$ls180.v:7638$2468_Y + end + attribute \src "ls180.v:7677.60-7677.119" + cell $add $add$ls180.v:7677$2478 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_produce + connect \B 1'1 + connect \Y $add$ls180.v:7677$2478_Y + end + attribute \src "ls180.v:7680.60-7680.119" + cell $add $add$ls180.v:7680$2479 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_consume + connect \B 1'1 + connect \Y $add$ls180.v:7680$2479_Y + end + attribute \src "ls180.v:7684.59-7684.116" + cell $add $add$ls180.v:7684$2484 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_level + connect \B 1'1 + connect \Y $add$ls180.v:7684$2484_Y + end + attribute \src "ls180.v:7914.25-7914.48" + cell $add $add$ls180.v:7914$2538 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_tx_bitcount + connect \B 1'1 + connect \Y $add$ls180.v:7914$2538_Y + end + attribute \src "ls180.v:7930.55-7930.95" + cell $add $add$ls180.v:7930$2541 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 33 + connect \A \main_phase_accumulator_tx + connect \B \main_storage + connect \Y $add$ls180.v:7930$2541_Y + end + attribute \src "ls180.v:7943.25-7943.48" + cell $add $add$ls180.v:7943$2545 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_rx_bitcount + connect \B 1'1 + connect \Y $add$ls180.v:7943$2545_Y + end + attribute \src "ls180.v:7962.55-7962.95" + cell $add $add$ls180.v:7962$2548 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 33 + connect \A \main_phase_accumulator_rx + connect \B \main_storage + connect \Y $add$ls180.v:7962$2548_Y + end + attribute \src "ls180.v:7988.33-7988.65" + cell $add $add$ls180.v:7988$2556 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_uart_tx_fifo_produce + connect \B 1'1 + connect \Y $add$ls180.v:7988$2556_Y + end + attribute \src "ls180.v:7991.33-7991.65" + cell $add $add$ls180.v:7991$2557 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_uart_tx_fifo_consume + connect \B 1'1 + connect \Y $add$ls180.v:7991$2557_Y + end + attribute \src "ls180.v:7995.33-7995.64" + cell $add $add$ls180.v:7995$2562 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 5 + connect \A \main_uart_tx_fifo_level0 + connect \B 1'1 + connect \Y $add$ls180.v:7995$2562_Y + end + attribute \src "ls180.v:8010.33-8010.65" + cell $add $add$ls180.v:8010$2567 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_uart_rx_fifo_produce + connect \B 1'1 + connect \Y $add$ls180.v:8010$2567_Y + end + attribute \src "ls180.v:8013.33-8013.65" + cell $add $add$ls180.v:8013$2568 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_uart_rx_fifo_consume + connect \B 1'1 + connect \Y $add$ls180.v:8013$2568_Y + end + attribute \src "ls180.v:8017.33-8017.64" + cell $add $add$ls180.v:8017$2573 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 5 + connect \A \main_uart_rx_fifo_level0 + connect \B 1'1 + connect \Y $add$ls180.v:8017$2573_Y + end + attribute \src "ls180.v:8038.35-8038.70" + cell $add $add$ls180.v:8038$2575 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 16 + connect \A \main_spi_master_clk_divider1 + connect \B 1'1 + connect \Y $add$ls180.v:8038$2575_Y + end + attribute \src "ls180.v:8074.25-8074.49" + cell $add $add$ls180.v:8074$2580 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_pwm0_counter + connect \B 1'1 + connect \Y $add$ls180.v:8074$2580_Y + end + attribute \src "ls180.v:8088.25-8088.49" + cell $add $add$ls180.v:8088$2584 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_pwm1_counter + connect \B 1'1 + connect \Y $add$ls180.v:8088$2584_Y + end + attribute \src "ls180.v:8102.31-8102.61" + cell $add $add$ls180.v:8102$2589 + parameter \A_SIGNED 0 + parameter \A_WIDTH 9 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 9 + connect \A \main_sdphy_clocker_clks + connect \B 1'1 + connect \Y $add$ls180.v:8102$2589_Y + end + attribute \src "ls180.v:8125.45-8125.88" + cell $add $add$ls180.v:8125$2593 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdphy_cmdr_cmdr_converter_demux + connect \B 1'1 + connect \Y $add$ls180.v:8125$2593_Y + end + attribute \src "ls180.v:8171.71-8171.114" + cell $add $add$ls180.v:8171$2599 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_sdphy_cmdr_cmdr_converter_demux + connect \B 1'1 + connect \Y $add$ls180.v:8171$2599_Y + end + attribute \src "ls180.v:8206.46-8206.90" + cell $add $add$ls180.v:8206$2605 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdphy_dataw_crcr_converter_demux + connect \B 1'1 + connect \Y $add$ls180.v:8206$2605_Y + end + attribute \src "ls180.v:8252.72-8252.116" + cell $add $add$ls180.v:8252$2611 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_sdphy_dataw_crcr_converter_demux + connect \B 1'1 + connect \Y $add$ls180.v:8252$2611_Y + end + attribute \src "ls180.v:8285.47-8285.92" + cell $add $add$ls180.v:8285$2617 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_datar_converter_demux + connect \B 1'1 + connect \Y $add$ls180.v:8285$2617_Y + end + attribute \src "ls180.v:8313.73-8313.118" + cell $add $add$ls180.v:8313$2623 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 2 + connect \A \main_sdphy_datar_datar_converter_demux + connect \B 1'1 + connect \Y $add$ls180.v:8313$2623_Y + end + attribute \src "ls180.v:8425.39-8425.75" + cell $add $add$ls180.v:8425$2636 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_sdcore_crc16_checker_cnt + connect \B 1'1 + connect \Y $add$ls180.v:8425$2636_Y + end + attribute \src "ls180.v:8486.37-8486.73" + cell $add $add$ls180.v:8486$2640 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 5 + connect \A \main_sdblock2mem_fifo_produce + connect \B 1'1 + connect \Y $add$ls180.v:8486$2640_Y + end + attribute \src "ls180.v:8489.37-8489.73" + cell $add $add$ls180.v:8489$2641 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 5 + connect \A \main_sdblock2mem_fifo_consume + connect \B 1'1 + connect \Y $add$ls180.v:8489$2641_Y + end + attribute \src "ls180.v:8493.36-8493.70" + cell $add $add$ls180.v:8493$2646 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 6 + connect \A \main_sdblock2mem_fifo_level + connect \B 1'1 + connect \Y $add$ls180.v:8493$2646_Y + end + attribute \src "ls180.v:8508.41-8508.80" + cell $add $add$ls180.v:8508$2650 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 2 + connect \A \main_sdblock2mem_converter_demux + connect \B 1'1 + connect \Y $add$ls180.v:8508$2650_Y + end + attribute \src "ls180.v:8542.67-8542.106" + cell $add $add$ls180.v:8542$2656 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdblock2mem_converter_demux + connect \B 1'1 + connect \Y $add$ls180.v:8542$2656_Y + end + attribute \src "ls180.v:8568.39-8568.76" + cell $add $add$ls180.v:8568$2658 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 2 + connect \A \main_sdmem2block_converter_mux + connect \B 1'1 + connect \Y $add$ls180.v:8568$2658_Y + end + attribute \src "ls180.v:8572.37-8572.73" + cell $add $add$ls180.v:8572$2662 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 5 + connect \A \main_sdmem2block_fifo_produce + connect \B 1'1 + connect \Y $add$ls180.v:8572$2662_Y + end + attribute \src "ls180.v:8575.37-8575.73" + cell $add $add$ls180.v:8575$2663 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 5 + connect \A \main_sdmem2block_fifo_consume + connect \B 1'1 + connect \Y $add$ls180.v:8575$2663_Y + end + attribute \src "ls180.v:8579.36-8579.70" + cell $add $add$ls180.v:8579$2668 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 6 + connect \A \main_sdmem2block_fifo_level + connect \B 1'1 + connect \Y $add$ls180.v:8579$2668_Y + end + attribute \src "ls180.v:8586.31-8586.62" + cell $add $add$ls180.v:8586$2670 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 16 + connect \A \libresocsim_clk_divider1 + connect \B 1'1 + connect \Y $add$ls180.v:8586$2670_Y + end + attribute \src "ls180.v:2762.9-2762.80" + cell $and $and$ls180.v:2762$17 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_libresoc_ibus_stb + connect \B \main_libresocsim_libresoc_ibus_cyc + connect \Y $and$ls180.v:2762$17_Y + end + attribute \src "ls180.v:2780.9-2780.80" + cell $and $and$ls180.v:2780$24 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_libresoc_ibus_stb + connect \B \main_libresocsim_libresoc_ibus_cyc + connect \Y $and$ls180.v:2780$24_Y + end + attribute \src "ls180.v:2822.9-2822.80" + cell $and $and$ls180.v:2822$28 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_libresoc_dbus_stb + connect \B \main_libresocsim_libresoc_dbus_cyc + connect \Y $and$ls180.v:2822$28_Y + end + attribute \src "ls180.v:2840.9-2840.80" + cell $and $and$ls180.v:2840$35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_libresoc_dbus_stb + connect \B \main_libresocsim_libresoc_dbus_cyc + connect \Y $and$ls180.v:2840$35_Y + end + attribute \src "ls180.v:2882.9-2882.86" + cell $and $and$ls180.v:2882$39 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_libresoc_jtag_wb_stb + connect \B \main_libresocsim_libresoc_jtag_wb_cyc + connect \Y $and$ls180.v:2882$39_Y + end + attribute \src "ls180.v:2900.9-2900.86" + cell $and $and$ls180.v:2900$46 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_libresoc_jtag_wb_stb + connect \B \main_libresocsim_libresoc_jtag_wb_cyc + connect \Y $and$ls180.v:2900$46_Y + end + attribute \src "ls180.v:2910.31-2910.90" + cell $and $and$ls180.v:2910$48 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_ram_bus_cyc + connect \B \main_libresocsim_ram_bus_stb + connect \Y $and$ls180.v:2910$48_Y + end + attribute \src "ls180.v:2910.30-2910.121" + cell $and $and$ls180.v:2910$49 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:2910$48_Y + connect \B \main_libresocsim_ram_bus_we + connect \Y $and$ls180.v:2910$49_Y + end + attribute \src "ls180.v:2910.29-2910.156" + cell $and $and$ls180.v:2910$50 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:2910$49_Y + connect \B \main_libresocsim_ram_bus_sel [0] + connect \Y $and$ls180.v:2910$50_Y + end + attribute \src "ls180.v:2911.31-2911.90" + cell $and $and$ls180.v:2911$51 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_ram_bus_cyc + connect \B \main_libresocsim_ram_bus_stb + connect \Y $and$ls180.v:2911$51_Y + end + attribute \src "ls180.v:2911.30-2911.121" + cell $and $and$ls180.v:2911$52 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:2911$51_Y + connect \B \main_libresocsim_ram_bus_we + connect \Y $and$ls180.v:2911$52_Y + end + attribute \src "ls180.v:2911.29-2911.156" + cell $and $and$ls180.v:2911$53 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:2911$52_Y + connect \B \main_libresocsim_ram_bus_sel [1] + connect \Y $and$ls180.v:2911$53_Y + end + attribute \src "ls180.v:2912.31-2912.90" + cell $and $and$ls180.v:2912$54 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_ram_bus_cyc + connect \B \main_libresocsim_ram_bus_stb + connect \Y $and$ls180.v:2912$54_Y + end + attribute \src "ls180.v:2912.30-2912.121" + cell $and $and$ls180.v:2912$55 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:2912$54_Y + connect \B \main_libresocsim_ram_bus_we + connect \Y $and$ls180.v:2912$55_Y + end + attribute \src "ls180.v:2912.29-2912.156" + cell $and $and$ls180.v:2912$56 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:2912$55_Y + connect \B \main_libresocsim_ram_bus_sel [2] + connect \Y $and$ls180.v:2912$56_Y + end + attribute \src "ls180.v:2913.31-2913.90" + cell $and $and$ls180.v:2913$57 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_ram_bus_cyc + connect \B \main_libresocsim_ram_bus_stb + connect \Y $and$ls180.v:2913$57_Y + end + attribute \src "ls180.v:2913.30-2913.121" + cell $and $and$ls180.v:2913$58 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:2913$57_Y + connect \B \main_libresocsim_ram_bus_we + connect \Y $and$ls180.v:2913$58_Y + end + attribute \src "ls180.v:2913.29-2913.156" + cell $and $and$ls180.v:2913$59 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:2913$58_Y + connect \B \main_libresocsim_ram_bus_sel [3] + connect \Y $and$ls180.v:2913$59_Y + end + attribute \src "ls180.v:2922.7-2922.89" + cell $and $and$ls180.v:2922$62 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_eventmanager_pending_re + connect \B \main_libresocsim_eventmanager_pending_r + connect \Y $and$ls180.v:2922$62_Y + end + attribute \src "ls180.v:2927.32-2927.111" + cell $and $and$ls180.v:2927$63 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_eventmanager_pending_w + connect \B \main_libresocsim_eventmanager_storage + connect \Y $and$ls180.v:2927$63_Y + end + attribute \src "ls180.v:3041.40-3041.99" + cell $and $and$ls180.v:3041$70 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_command_issue_re + connect \B \main_sdram_command_storage [4] + connect \Y $and$ls180.v:3041$70_Y + end + attribute \src "ls180.v:3042.40-3042.99" + cell $and $and$ls180.v:3042$71 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_command_issue_re + connect \B \main_sdram_command_storage [5] + connect \Y $and$ls180.v:3042$71_Y + end + attribute \src "ls180.v:3080.38-3080.103" + cell $and $and$ls180.v:3080$77 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_sequencer_done1 + connect \B $eq$ls180.v:3080$76_Y + connect \Y $and$ls180.v:3080$77_Y + end + attribute \src "ls180.v:3134.50-3134.119" + cell $and $and$ls180.v:3134$85 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_valid + connect \B \main_sdram_bankmachine0_cmd_ready + connect \Y $and$ls180.v:3134$85_Y + end + attribute \src "ls180.v:3134.49-3134.167" + cell $and $and$ls180.v:3134$86 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3134$85_Y + connect \B \main_sdram_bankmachine0_cmd_payload_is_write + connect \Y $and$ls180.v:3134$86_Y + end + attribute \src "ls180.v:3135.49-3135.118" + cell $and $and$ls180.v:3135$87 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_valid + connect \B \main_sdram_bankmachine0_cmd_ready + connect \Y $and$ls180.v:3135$87_Y + end + attribute \src "ls180.v:3135.48-3135.154" + cell $and $and$ls180.v:3135$88 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3135$87_Y + connect \B \main_sdram_bankmachine0_row_open + connect \Y $and$ls180.v:3135$88_Y + end + attribute \src "ls180.v:3136.50-3136.119" + cell $and $and$ls180.v:3136$89 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_valid + connect \B \main_sdram_bankmachine0_cmd_ready + connect \Y $and$ls180.v:3136$89_Y + end + attribute \src "ls180.v:3136.49-3136.155" + cell $and $and$ls180.v:3136$90 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3136$89_Y + connect \B \main_sdram_bankmachine0_row_open + connect \Y $and$ls180.v:3136$90_Y + end + attribute \src "ls180.v:3139.7-3139.114" + cell $and $and$ls180.v:3139$92 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_source_valid + connect \B \main_sdram_bankmachine0_cmd_buffer_source_valid + connect \Y $and$ls180.v:3139$92_Y + end + attribute \src "ls180.v:3168.66-3168.246" + cell $and $and$ls180.v:3168$98 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we + connect \B $or$ls180.v:3168$97_Y + connect \Y $and$ls180.v:3168$98_Y + end + attribute \src "ls180.v:3169.64-3169.187" + cell $and $and$ls180.v:3169$99 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable + connect \B \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re + connect \Y $and$ls180.v:3169$99_Y + end + attribute \src "ls180.v:3193.9-3193.86" + cell $and $and$ls180.v:3193$105 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_twtpcon_ready + connect \B \main_sdram_bankmachine0_trascon_ready + connect \Y $and$ls180.v:3193$105_Y + end + attribute \src "ls180.v:3205.9-3205.86" + cell $and $and$ls180.v:3205$106 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_twtpcon_ready + connect \B \main_sdram_bankmachine0_trascon_ready + connect \Y $and$ls180.v:3205$106_Y + end + attribute \src "ls180.v:3255.13-3255.87" + cell $and $and$ls180.v:3255$108 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_ready + connect \B \main_sdram_bankmachine0_auto_precharge + connect \Y $and$ls180.v:3255$108_Y + end + attribute \src "ls180.v:3291.50-3291.119" + cell $and $and$ls180.v:3291$115 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_valid + connect \B \main_sdram_bankmachine1_cmd_ready + connect \Y $and$ls180.v:3291$115_Y + end + attribute \src "ls180.v:3291.49-3291.167" + cell $and $and$ls180.v:3291$116 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3291$115_Y + connect \B \main_sdram_bankmachine1_cmd_payload_is_write + connect \Y $and$ls180.v:3291$116_Y + end + attribute \src "ls180.v:3292.49-3292.118" + cell $and $and$ls180.v:3292$117 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_valid + connect \B \main_sdram_bankmachine1_cmd_ready + connect \Y $and$ls180.v:3292$117_Y + end + attribute \src "ls180.v:3292.48-3292.154" + cell $and $and$ls180.v:3292$118 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3292$117_Y + connect \B \main_sdram_bankmachine1_row_open + connect \Y $and$ls180.v:3292$118_Y + end + attribute \src "ls180.v:3293.50-3293.119" + cell $and $and$ls180.v:3293$119 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_valid + connect \B \main_sdram_bankmachine1_cmd_ready + connect \Y $and$ls180.v:3293$119_Y + end + attribute \src "ls180.v:3293.49-3293.155" + cell $and $and$ls180.v:3293$120 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3293$119_Y + connect \B \main_sdram_bankmachine1_row_open + connect \Y $and$ls180.v:3293$120_Y + end + attribute \src "ls180.v:3296.7-3296.114" + cell $and $and$ls180.v:3296$122 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_source_valid + connect \B \main_sdram_bankmachine1_cmd_buffer_source_valid + connect \Y $and$ls180.v:3296$122_Y + end + attribute \src "ls180.v:3325.66-3325.246" + cell $and $and$ls180.v:3325$128 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we + connect \B $or$ls180.v:3325$127_Y + connect \Y $and$ls180.v:3325$128_Y + end + attribute \src "ls180.v:3326.64-3326.187" + cell $and $and$ls180.v:3326$129 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable + connect \B \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re + connect \Y $and$ls180.v:3326$129_Y + end + attribute \src "ls180.v:3350.9-3350.86" + cell $and $and$ls180.v:3350$135 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_twtpcon_ready + connect \B \main_sdram_bankmachine1_trascon_ready + connect \Y $and$ls180.v:3350$135_Y + end + attribute \src "ls180.v:3362.9-3362.86" + cell $and $and$ls180.v:3362$136 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_twtpcon_ready + connect \B \main_sdram_bankmachine1_trascon_ready + connect \Y $and$ls180.v:3362$136_Y + end + attribute \src "ls180.v:3412.13-3412.87" + cell $and $and$ls180.v:3412$138 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_ready + connect \B \main_sdram_bankmachine1_auto_precharge + connect \Y $and$ls180.v:3412$138_Y + end + attribute \src "ls180.v:3448.50-3448.119" + cell $and $and$ls180.v:3448$145 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_valid + connect \B \main_sdram_bankmachine2_cmd_ready + connect \Y $and$ls180.v:3448$145_Y + end + attribute \src "ls180.v:3448.49-3448.167" + cell $and $and$ls180.v:3448$146 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3448$145_Y + connect \B \main_sdram_bankmachine2_cmd_payload_is_write + connect \Y $and$ls180.v:3448$146_Y + end + attribute \src "ls180.v:3449.49-3449.118" + cell $and $and$ls180.v:3449$147 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_valid + connect \B \main_sdram_bankmachine2_cmd_ready + connect \Y $and$ls180.v:3449$147_Y + end + attribute \src "ls180.v:3449.48-3449.154" + cell $and $and$ls180.v:3449$148 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3449$147_Y + connect \B \main_sdram_bankmachine2_row_open + connect \Y $and$ls180.v:3449$148_Y + end + attribute \src "ls180.v:3450.50-3450.119" + cell $and $and$ls180.v:3450$149 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_valid + connect \B \main_sdram_bankmachine2_cmd_ready + connect \Y $and$ls180.v:3450$149_Y + end + attribute \src "ls180.v:3450.49-3450.155" + cell $and $and$ls180.v:3450$150 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3450$149_Y + connect \B \main_sdram_bankmachine2_row_open + connect \Y $and$ls180.v:3450$150_Y + end + attribute \src "ls180.v:3453.7-3453.114" + cell $and $and$ls180.v:3453$152 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_source_valid + connect \B \main_sdram_bankmachine2_cmd_buffer_source_valid + connect \Y $and$ls180.v:3453$152_Y + end + attribute \src "ls180.v:3482.66-3482.246" + cell $and $and$ls180.v:3482$158 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we + connect \B $or$ls180.v:3482$157_Y + connect \Y $and$ls180.v:3482$158_Y + end + attribute \src "ls180.v:3483.64-3483.187" + cell $and $and$ls180.v:3483$159 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable + connect \B \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re + connect \Y $and$ls180.v:3483$159_Y + end + attribute \src "ls180.v:3507.9-3507.86" + cell $and $and$ls180.v:3507$165 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_twtpcon_ready + connect \B \main_sdram_bankmachine2_trascon_ready + connect \Y $and$ls180.v:3507$165_Y + end + attribute \src "ls180.v:3519.9-3519.86" + cell $and $and$ls180.v:3519$166 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_twtpcon_ready + connect \B \main_sdram_bankmachine2_trascon_ready + connect \Y $and$ls180.v:3519$166_Y + end + attribute \src "ls180.v:3569.13-3569.87" + cell $and $and$ls180.v:3569$168 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_ready + connect \B \main_sdram_bankmachine2_auto_precharge + connect \Y $and$ls180.v:3569$168_Y + end + attribute \src "ls180.v:3605.50-3605.119" + cell $and $and$ls180.v:3605$175 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_valid + connect \B \main_sdram_bankmachine3_cmd_ready + connect \Y $and$ls180.v:3605$175_Y + end + attribute \src "ls180.v:3605.49-3605.167" + cell $and $and$ls180.v:3605$176 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3605$175_Y + connect \B \main_sdram_bankmachine3_cmd_payload_is_write + connect \Y $and$ls180.v:3605$176_Y + end + attribute \src "ls180.v:3606.49-3606.118" + cell $and $and$ls180.v:3606$177 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_valid + connect \B \main_sdram_bankmachine3_cmd_ready + connect \Y $and$ls180.v:3606$177_Y + end + attribute \src "ls180.v:3606.48-3606.154" + cell $and $and$ls180.v:3606$178 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3606$177_Y + connect \B \main_sdram_bankmachine3_row_open + connect \Y $and$ls180.v:3606$178_Y + end + attribute \src "ls180.v:3607.50-3607.119" + cell $and $and$ls180.v:3607$179 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_valid + connect \B \main_sdram_bankmachine3_cmd_ready + connect \Y $and$ls180.v:3607$179_Y + end + attribute \src "ls180.v:3607.49-3607.155" + cell $and $and$ls180.v:3607$180 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3607$179_Y + connect \B \main_sdram_bankmachine3_row_open + connect \Y $and$ls180.v:3607$180_Y + end + attribute \src "ls180.v:3610.7-3610.114" + cell $and $and$ls180.v:3610$182 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_source_valid + connect \B \main_sdram_bankmachine3_cmd_buffer_source_valid + connect \Y $and$ls180.v:3610$182_Y + end + attribute \src "ls180.v:3639.66-3639.246" + cell $and $and$ls180.v:3639$188 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we + connect \B $or$ls180.v:3639$187_Y + connect \Y $and$ls180.v:3639$188_Y + end + attribute \src "ls180.v:3640.64-3640.187" + cell $and $and$ls180.v:3640$189 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable + connect \B \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re + connect \Y $and$ls180.v:3640$189_Y + end + attribute \src "ls180.v:3664.9-3664.86" + cell $and $and$ls180.v:3664$195 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_twtpcon_ready + connect \B \main_sdram_bankmachine3_trascon_ready + connect \Y $and$ls180.v:3664$195_Y + end + attribute \src "ls180.v:3676.9-3676.86" + cell $and $and$ls180.v:3676$196 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_twtpcon_ready + connect \B \main_sdram_bankmachine3_trascon_ready + connect \Y $and$ls180.v:3676$196_Y + end + attribute \src "ls180.v:3726.13-3726.87" + cell $and $and$ls180.v:3726$198 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_ready + connect \B \main_sdram_bankmachine3_auto_precharge + connect \Y $and$ls180.v:3726$198_Y + end + attribute \src "ls180.v:3741.37-3741.102" + cell $and $and$ls180.v:3741$199 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:3741$199_Y + end + attribute \src "ls180.v:3741.108-3741.188" + cell $and $and$ls180.v:3741$201 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_payload_ras + connect \B $not$ls180.v:3741$200_Y + connect \Y $and$ls180.v:3741$201_Y + end + attribute \src "ls180.v:3741.107-3741.231" + cell $and $and$ls180.v:3741$203 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3741$201_Y + connect \B $not$ls180.v:3741$202_Y + connect \Y $and$ls180.v:3741$203_Y + end + attribute \src "ls180.v:3741.36-3741.232" + cell $and $and$ls180.v:3741$204 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3741$199_Y + connect \B $and$ls180.v:3741$203_Y + connect \Y $and$ls180.v:3741$204_Y + end + attribute \src "ls180.v:3742.37-3742.102" + cell $and $and$ls180.v:3742$205 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:3742$205_Y + end + attribute \src "ls180.v:3742.108-3742.188" + cell $and $and$ls180.v:3742$207 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_payload_ras + connect \B $not$ls180.v:3742$206_Y + connect \Y $and$ls180.v:3742$207_Y + end + attribute \src "ls180.v:3742.107-3742.231" + cell $and $and$ls180.v:3742$209 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3742$207_Y + connect \B $not$ls180.v:3742$208_Y + connect \Y $and$ls180.v:3742$209_Y + end + attribute \src "ls180.v:3742.36-3742.232" + cell $and $and$ls180.v:3742$210 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3742$205_Y + connect \B $and$ls180.v:3742$209_Y + connect \Y $and$ls180.v:3742$210_Y + end + attribute \src "ls180.v:3743.34-3743.85" + cell $and $and$ls180.v:3743$211 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_trrdcon_ready + connect \B \main_sdram_tfawcon_ready + connect \Y $and$ls180.v:3743$211_Y + end + attribute \src "ls180.v:3744.37-3744.102" + cell $and $and$ls180.v:3744$212 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:3744$212_Y + end + attribute \src "ls180.v:3744.36-3744.194" + cell $and $and$ls180.v:3744$214 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3744$212_Y + connect \B $or$ls180.v:3744$213_Y + connect \Y $and$ls180.v:3744$214_Y + end + attribute \src "ls180.v:3746.37-3746.102" + cell $and $and$ls180.v:3746$215 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:3746$215_Y + end + attribute \src "ls180.v:3746.36-3746.148" + cell $and $and$ls180.v:3746$216 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3746$215_Y + connect \B \main_sdram_choose_req_cmd_payload_is_write + connect \Y $and$ls180.v:3746$216_Y + end + attribute \src "ls180.v:3747.40-3747.119" + cell $and $and$ls180.v:3747$217 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_valid + connect \B \main_sdram_bankmachine0_cmd_payload_is_read + connect \Y $and$ls180.v:3747$217_Y + end + attribute \src "ls180.v:3747.124-3747.203" + cell $and $and$ls180.v:3747$218 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_valid + connect \B \main_sdram_bankmachine1_cmd_payload_is_read + connect \Y $and$ls180.v:3747$218_Y + end + attribute \src "ls180.v:3747.209-3747.288" + cell $and $and$ls180.v:3747$220 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_valid + connect \B \main_sdram_bankmachine2_cmd_payload_is_read + connect \Y $and$ls180.v:3747$220_Y + end + attribute \src "ls180.v:3747.294-3747.373" + cell $and $and$ls180.v:3747$222 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_valid + connect \B \main_sdram_bankmachine3_cmd_payload_is_read + connect \Y $and$ls180.v:3747$222_Y + end + attribute \src "ls180.v:3748.41-3748.121" + cell $and $and$ls180.v:3748$224 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_valid + connect \B \main_sdram_bankmachine0_cmd_payload_is_write + connect \Y $and$ls180.v:3748$224_Y + end + attribute \src "ls180.v:3748.126-3748.206" + cell $and $and$ls180.v:3748$225 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_valid + connect \B \main_sdram_bankmachine1_cmd_payload_is_write + connect \Y $and$ls180.v:3748$225_Y + end + attribute \src "ls180.v:3748.212-3748.292" + cell $and $and$ls180.v:3748$227 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_valid + connect \B \main_sdram_bankmachine2_cmd_payload_is_write + connect \Y $and$ls180.v:3748$227_Y + end + attribute \src "ls180.v:3748.298-3748.378" + cell $and $and$ls180.v:3748$229 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_valid + connect \B \main_sdram_bankmachine3_cmd_payload_is_write + connect \Y $and$ls180.v:3748$229_Y + end + attribute \src "ls180.v:3755.38-3755.111" + cell $and $and$ls180.v:3755$233 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_refresh_gnt + connect \B \main_sdram_bankmachine1_refresh_gnt + connect \Y $and$ls180.v:3755$233_Y + end + attribute \src "ls180.v:3755.37-3755.150" + cell $and $and$ls180.v:3755$234 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3755$233_Y + connect \B \main_sdram_bankmachine2_refresh_gnt + connect \Y $and$ls180.v:3755$234_Y + end + attribute \src "ls180.v:3755.36-3755.189" + cell $and $and$ls180.v:3755$235 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3755$234_Y + connect \B \main_sdram_bankmachine3_refresh_gnt + connect \Y $and$ls180.v:3755$235_Y + end + attribute \src "ls180.v:3761.77-3761.153" + cell $and $and$ls180.v:3761$238 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_payload_is_cmd + connect \B \main_sdram_choose_cmd_want_cmds + connect \Y $and$ls180.v:3761$238_Y + end + attribute \src "ls180.v:3761.162-3761.246" + cell $and $and$ls180.v:3761$240 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_payload_ras + connect \B $not$ls180.v:3761$239_Y + connect \Y $and$ls180.v:3761$240_Y + end + attribute \src "ls180.v:3761.161-3761.291" + cell $and $and$ls180.v:3761$242 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3761$240_Y + connect \B $not$ls180.v:3761$241_Y + connect \Y $and$ls180.v:3761$242_Y + end + attribute \src "ls180.v:3761.76-3761.333" + cell $and $and$ls180.v:3761$245 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3761$238_Y + connect \B $or$ls180.v:3761$244_Y + connect \Y $and$ls180.v:3761$245_Y + end + attribute \src "ls180.v:3761.338-3761.505" + cell $and $and$ls180.v:3761$248 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:3761$246_Y + connect \B $eq$ls180.v:3761$247_Y + connect \Y $and$ls180.v:3761$248_Y + end + attribute \src "ls180.v:3761.38-3761.507" + cell $and $and$ls180.v:3761$250 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_valid + connect \B $or$ls180.v:3761$249_Y + connect \Y $and$ls180.v:3761$250_Y + end + attribute \src "ls180.v:3762.77-3762.153" + cell $and $and$ls180.v:3762$251 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_payload_is_cmd + connect \B \main_sdram_choose_cmd_want_cmds + connect \Y $and$ls180.v:3762$251_Y + end + attribute \src "ls180.v:3762.162-3762.246" + cell $and $and$ls180.v:3762$253 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_payload_ras + connect \B $not$ls180.v:3762$252_Y + connect \Y $and$ls180.v:3762$253_Y + end + attribute \src "ls180.v:3762.161-3762.291" + cell $and $and$ls180.v:3762$255 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3762$253_Y + connect \B $not$ls180.v:3762$254_Y + connect \Y $and$ls180.v:3762$255_Y + end + attribute \src "ls180.v:3762.76-3762.333" + cell $and $and$ls180.v:3762$258 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3762$251_Y + connect \B $or$ls180.v:3762$257_Y + connect \Y $and$ls180.v:3762$258_Y + end + attribute \src "ls180.v:3762.338-3762.505" + cell $and $and$ls180.v:3762$261 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:3762$259_Y + connect \B $eq$ls180.v:3762$260_Y + connect \Y $and$ls180.v:3762$261_Y + end + attribute \src "ls180.v:3762.38-3762.507" + cell $and $and$ls180.v:3762$263 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_valid + connect \B $or$ls180.v:3762$262_Y + connect \Y $and$ls180.v:3762$263_Y + end + attribute \src "ls180.v:3763.77-3763.153" + cell $and $and$ls180.v:3763$264 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_payload_is_cmd + connect \B \main_sdram_choose_cmd_want_cmds + connect \Y $and$ls180.v:3763$264_Y + end + attribute \src "ls180.v:3763.162-3763.246" + cell $and $and$ls180.v:3763$266 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_payload_ras + connect \B $not$ls180.v:3763$265_Y + connect \Y $and$ls180.v:3763$266_Y + end + attribute \src "ls180.v:3763.161-3763.291" + cell $and $and$ls180.v:3763$268 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3763$266_Y + connect \B $not$ls180.v:3763$267_Y + connect \Y $and$ls180.v:3763$268_Y + end + attribute \src "ls180.v:3763.76-3763.333" + cell $and $and$ls180.v:3763$271 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3763$264_Y + connect \B $or$ls180.v:3763$270_Y + connect \Y $and$ls180.v:3763$271_Y + end + attribute \src "ls180.v:3763.338-3763.505" + cell $and $and$ls180.v:3763$274 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:3763$272_Y + connect \B $eq$ls180.v:3763$273_Y + connect \Y $and$ls180.v:3763$274_Y + end + attribute \src "ls180.v:3763.38-3763.507" + cell $and $and$ls180.v:3763$276 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_valid + connect \B $or$ls180.v:3763$275_Y + connect \Y $and$ls180.v:3763$276_Y + end + attribute \src "ls180.v:3764.77-3764.153" + cell $and $and$ls180.v:3764$277 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_payload_is_cmd + connect \B \main_sdram_choose_cmd_want_cmds + connect \Y $and$ls180.v:3764$277_Y + end + attribute \src "ls180.v:3764.162-3764.246" + cell $and $and$ls180.v:3764$279 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_payload_ras + connect \B $not$ls180.v:3764$278_Y + connect \Y $and$ls180.v:3764$279_Y + end + attribute \src "ls180.v:3764.161-3764.291" + cell $and $and$ls180.v:3764$281 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3764$279_Y + connect \B $not$ls180.v:3764$280_Y + connect \Y $and$ls180.v:3764$281_Y + end + attribute \src "ls180.v:3764.76-3764.333" + cell $and $and$ls180.v:3764$284 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3764$277_Y + connect \B $or$ls180.v:3764$283_Y + connect \Y $and$ls180.v:3764$284_Y + end + attribute \src "ls180.v:3764.338-3764.505" + cell $and $and$ls180.v:3764$287 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:3764$285_Y + connect \B $eq$ls180.v:3764$286_Y + connect \Y $and$ls180.v:3764$287_Y + end + attribute \src "ls180.v:3764.38-3764.507" + cell $and $and$ls180.v:3764$289 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_valid + connect \B $or$ls180.v:3764$288_Y + connect \Y $and$ls180.v:3764$289_Y + end + attribute \src "ls180.v:3794.77-3794.153" + cell $and $and$ls180.v:3794$296 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_payload_is_cmd + connect \B \main_sdram_choose_req_want_cmds + connect \Y $and$ls180.v:3794$296_Y + end + attribute \src "ls180.v:3794.162-3794.246" + cell $and $and$ls180.v:3794$298 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_payload_ras + connect \B $not$ls180.v:3794$297_Y + connect \Y $and$ls180.v:3794$298_Y + end + attribute \src "ls180.v:3794.161-3794.291" + cell $and $and$ls180.v:3794$300 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3794$298_Y + connect \B $not$ls180.v:3794$299_Y + connect \Y $and$ls180.v:3794$300_Y + end + attribute \src "ls180.v:3794.76-3794.333" + cell $and $and$ls180.v:3794$303 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3794$296_Y + connect \B $or$ls180.v:3794$302_Y + connect \Y $and$ls180.v:3794$303_Y + end + attribute \src "ls180.v:3794.338-3794.505" + cell $and $and$ls180.v:3794$306 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:3794$304_Y + connect \B $eq$ls180.v:3794$305_Y + connect \Y $and$ls180.v:3794$306_Y + end + attribute \src "ls180.v:3794.38-3794.507" + cell $and $and$ls180.v:3794$308 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_valid + connect \B $or$ls180.v:3794$307_Y + connect \Y $and$ls180.v:3794$308_Y + end + attribute \src "ls180.v:3795.77-3795.153" + cell $and $and$ls180.v:3795$309 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_payload_is_cmd + connect \B \main_sdram_choose_req_want_cmds + connect \Y $and$ls180.v:3795$309_Y + end + attribute \src "ls180.v:3795.162-3795.246" + cell $and $and$ls180.v:3795$311 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_payload_ras + connect \B $not$ls180.v:3795$310_Y + connect \Y $and$ls180.v:3795$311_Y + end + attribute \src "ls180.v:3795.161-3795.291" + cell $and $and$ls180.v:3795$313 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3795$311_Y + connect \B $not$ls180.v:3795$312_Y + connect \Y $and$ls180.v:3795$313_Y + end + attribute \src "ls180.v:3795.76-3795.333" + cell $and $and$ls180.v:3795$316 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3795$309_Y + connect \B $or$ls180.v:3795$315_Y + connect \Y $and$ls180.v:3795$316_Y + end + attribute \src "ls180.v:3795.338-3795.505" + cell $and $and$ls180.v:3795$319 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:3795$317_Y + connect \B $eq$ls180.v:3795$318_Y + connect \Y $and$ls180.v:3795$319_Y + end + attribute \src "ls180.v:3795.38-3795.507" + cell $and $and$ls180.v:3795$321 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_valid + connect \B $or$ls180.v:3795$320_Y + connect \Y $and$ls180.v:3795$321_Y + end + attribute \src "ls180.v:3796.77-3796.153" + cell $and $and$ls180.v:3796$322 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_payload_is_cmd + connect \B \main_sdram_choose_req_want_cmds + connect \Y $and$ls180.v:3796$322_Y + end + attribute \src "ls180.v:3796.162-3796.246" + cell $and $and$ls180.v:3796$324 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_payload_ras + connect \B $not$ls180.v:3796$323_Y + connect \Y $and$ls180.v:3796$324_Y + end + attribute \src "ls180.v:3796.161-3796.291" + cell $and $and$ls180.v:3796$326 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3796$324_Y + connect \B $not$ls180.v:3796$325_Y + connect \Y $and$ls180.v:3796$326_Y + end + attribute \src "ls180.v:3796.76-3796.333" + cell $and $and$ls180.v:3796$329 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3796$322_Y + connect \B $or$ls180.v:3796$328_Y + connect \Y $and$ls180.v:3796$329_Y + end + attribute \src "ls180.v:3796.338-3796.505" + cell $and $and$ls180.v:3796$332 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:3796$330_Y + connect \B $eq$ls180.v:3796$331_Y + connect \Y $and$ls180.v:3796$332_Y + end + attribute \src "ls180.v:3796.38-3796.507" + cell $and $and$ls180.v:3796$334 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_valid + connect \B $or$ls180.v:3796$333_Y + connect \Y $and$ls180.v:3796$334_Y + end + attribute \src "ls180.v:3797.77-3797.153" + cell $and $and$ls180.v:3797$335 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_payload_is_cmd + connect \B \main_sdram_choose_req_want_cmds + connect \Y $and$ls180.v:3797$335_Y + end + attribute \src "ls180.v:3797.162-3797.246" + cell $and $and$ls180.v:3797$337 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_payload_ras + connect \B $not$ls180.v:3797$336_Y + connect \Y $and$ls180.v:3797$337_Y + end + attribute \src "ls180.v:3797.161-3797.291" + cell $and $and$ls180.v:3797$339 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3797$337_Y + connect \B $not$ls180.v:3797$338_Y + connect \Y $and$ls180.v:3797$339_Y + end + attribute \src "ls180.v:3797.76-3797.333" + cell $and $and$ls180.v:3797$342 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3797$335_Y + connect \B $or$ls180.v:3797$341_Y + connect \Y $and$ls180.v:3797$342_Y + end + attribute \src "ls180.v:3797.338-3797.505" + cell $and $and$ls180.v:3797$345 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:3797$343_Y + connect \B $eq$ls180.v:3797$344_Y + connect \Y $and$ls180.v:3797$345_Y + end + attribute \src "ls180.v:3797.38-3797.507" + cell $and $and$ls180.v:3797$347 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_valid + connect \B $or$ls180.v:3797$346_Y + connect \Y $and$ls180.v:3797$347_Y + end + attribute \src "ls180.v:3826.8-3826.73" + cell $and $and$ls180.v:3826$352 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_cmd_cmd_valid + connect \B \main_sdram_choose_cmd_cmd_ready + connect \Y $and$ls180.v:3826$352_Y + end + attribute \src "ls180.v:3826.7-3826.114" + cell $and $and$ls180.v:3826$354 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3826$352_Y + connect \B $eq$ls180.v:3826$353_Y + connect \Y $and$ls180.v:3826$354_Y + end + attribute \src "ls180.v:3829.8-3829.73" + cell $and $and$ls180.v:3829$355 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:3829$355_Y + end + attribute \src "ls180.v:3829.7-3829.114" + cell $and $and$ls180.v:3829$357 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3829$355_Y + connect \B $eq$ls180.v:3829$356_Y + connect \Y $and$ls180.v:3829$357_Y + end + attribute \src "ls180.v:3835.8-3835.73" + cell $and $and$ls180.v:3835$359 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_cmd_cmd_valid + connect \B \main_sdram_choose_cmd_cmd_ready + connect \Y $and$ls180.v:3835$359_Y + end + attribute \src "ls180.v:3835.7-3835.114" + cell $and $and$ls180.v:3835$361 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3835$359_Y + connect \B $eq$ls180.v:3835$360_Y + connect \Y $and$ls180.v:3835$361_Y + end + attribute \src "ls180.v:3838.8-3838.73" + cell $and $and$ls180.v:3838$362 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:3838$362_Y + end + attribute \src "ls180.v:3838.7-3838.114" + cell $and $and$ls180.v:3838$364 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3838$362_Y + connect \B $eq$ls180.v:3838$363_Y + connect \Y $and$ls180.v:3838$364_Y + end + attribute \src "ls180.v:3844.8-3844.73" + cell $and $and$ls180.v:3844$366 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_cmd_cmd_valid + connect \B \main_sdram_choose_cmd_cmd_ready + connect \Y $and$ls180.v:3844$366_Y + end + attribute \src "ls180.v:3844.7-3844.114" + cell $and $and$ls180.v:3844$368 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3844$366_Y + connect \B $eq$ls180.v:3844$367_Y + connect \Y $and$ls180.v:3844$368_Y + end + attribute \src "ls180.v:3847.8-3847.73" + cell $and $and$ls180.v:3847$369 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:3847$369_Y + end + attribute \src "ls180.v:3847.7-3847.114" + cell $and $and$ls180.v:3847$371 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3847$369_Y + connect \B $eq$ls180.v:3847$370_Y + connect \Y $and$ls180.v:3847$371_Y + end + attribute \src "ls180.v:3853.8-3853.73" + cell $and $and$ls180.v:3853$373 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_cmd_cmd_valid + connect \B \main_sdram_choose_cmd_cmd_ready + connect \Y $and$ls180.v:3853$373_Y + end + attribute \src "ls180.v:3853.7-3853.114" + cell $and $and$ls180.v:3853$375 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3853$373_Y + connect \B $eq$ls180.v:3853$374_Y + connect \Y $and$ls180.v:3853$375_Y + end + attribute \src "ls180.v:3856.8-3856.73" + cell $and $and$ls180.v:3856$376 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:3856$376_Y + end + attribute \src "ls180.v:3856.7-3856.114" + cell $and $and$ls180.v:3856$378 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3856$376_Y + connect \B $eq$ls180.v:3856$377_Y + connect \Y $and$ls180.v:3856$378_Y + end + attribute \src "ls180.v:3881.71-3881.151" + cell $and $and$ls180.v:3881$383 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_payload_ras + connect \B $not$ls180.v:3881$382_Y + connect \Y $and$ls180.v:3881$383_Y + end + attribute \src "ls180.v:3881.70-3881.194" + cell $and $and$ls180.v:3881$385 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3881$383_Y + connect \B $not$ls180.v:3881$384_Y + connect \Y $and$ls180.v:3881$385_Y + end + attribute \src "ls180.v:3881.41-3881.222" + cell $and $and$ls180.v:3881$388 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_cas_allowed + connect \B $or$ls180.v:3881$387_Y + connect \Y $and$ls180.v:3881$388_Y + end + attribute \src "ls180.v:3919.71-3919.151" + cell $and $and$ls180.v:3919$392 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_payload_ras + connect \B $not$ls180.v:3919$391_Y + connect \Y $and$ls180.v:3919$392_Y + end + attribute \src "ls180.v:3919.70-3919.194" + cell $and $and$ls180.v:3919$394 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3919$392_Y + connect \B $not$ls180.v:3919$393_Y + connect \Y $and$ls180.v:3919$394_Y + end + attribute \src "ls180.v:3919.41-3919.222" + cell $and $and$ls180.v:3919$397 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_cas_allowed + connect \B $or$ls180.v:3919$396_Y + connect \Y $and$ls180.v:3919$397_Y + end + attribute \src "ls180.v:3937.110-3937.179" + cell $and $and$ls180.v:3937$402 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank1_lock + connect \B $eq$ls180.v:3937$401_Y + connect \Y $and$ls180.v:3937$402_Y + end + attribute \src "ls180.v:3937.185-3937.254" + cell $and $and$ls180.v:3937$405 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank2_lock + connect \B $eq$ls180.v:3937$404_Y + connect \Y $and$ls180.v:3937$405_Y + end + attribute \src "ls180.v:3937.260-3937.329" + cell $and $and$ls180.v:3937$408 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank3_lock + connect \B $eq$ls180.v:3937$407_Y + connect \Y $and$ls180.v:3937$408_Y + end + attribute \src "ls180.v:3937.41-3937.332" + cell $and $and$ls180.v:3937$411 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:3937$400_Y + connect \B $not$ls180.v:3937$410_Y + connect \Y $and$ls180.v:3937$411_Y + end + attribute \src "ls180.v:3937.40-3937.355" + cell $and $and$ls180.v:3937$412 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3937$411_Y + connect \B \main_port_cmd_valid + connect \Y $and$ls180.v:3937$412_Y + end + attribute \src "ls180.v:3938.34-3938.106" + cell $and $and$ls180.v:3938$415 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:3938$413_Y + connect \B $not$ls180.v:3938$414_Y + connect \Y $and$ls180.v:3938$415_Y + end + attribute \src "ls180.v:3942.110-3942.179" + cell $and $and$ls180.v:3942$418 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank0_lock + connect \B $eq$ls180.v:3942$417_Y + connect \Y $and$ls180.v:3942$418_Y + end + attribute \src "ls180.v:3942.185-3942.254" + cell $and $and$ls180.v:3942$421 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank2_lock + connect \B $eq$ls180.v:3942$420_Y + connect \Y $and$ls180.v:3942$421_Y + end + attribute \src "ls180.v:3942.260-3942.329" + cell $and $and$ls180.v:3942$424 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank3_lock + connect \B $eq$ls180.v:3942$423_Y + connect \Y $and$ls180.v:3942$424_Y + end + attribute \src "ls180.v:3942.41-3942.332" + cell $and $and$ls180.v:3942$427 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:3942$416_Y + connect \B $not$ls180.v:3942$426_Y + connect \Y $and$ls180.v:3942$427_Y + end + attribute \src "ls180.v:3942.40-3942.355" + cell $and $and$ls180.v:3942$428 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3942$427_Y + connect \B \main_port_cmd_valid + connect \Y $and$ls180.v:3942$428_Y + end + attribute \src "ls180.v:3943.34-3943.106" + cell $and $and$ls180.v:3943$431 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:3943$429_Y + connect \B $not$ls180.v:3943$430_Y + connect \Y $and$ls180.v:3943$431_Y + end + attribute \src "ls180.v:3947.110-3947.179" + cell $and $and$ls180.v:3947$434 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank0_lock + connect \B $eq$ls180.v:3947$433_Y + connect \Y $and$ls180.v:3947$434_Y + end + attribute \src "ls180.v:3947.185-3947.254" + cell $and $and$ls180.v:3947$437 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank1_lock + connect \B $eq$ls180.v:3947$436_Y + connect \Y $and$ls180.v:3947$437_Y + end + attribute \src "ls180.v:3947.260-3947.329" + cell $and $and$ls180.v:3947$440 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank3_lock + connect \B $eq$ls180.v:3947$439_Y + connect \Y $and$ls180.v:3947$440_Y + end + attribute \src "ls180.v:3947.41-3947.332" + cell $and $and$ls180.v:3947$443 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:3947$432_Y + connect \B $not$ls180.v:3947$442_Y + connect \Y $and$ls180.v:3947$443_Y + end + attribute \src "ls180.v:3947.40-3947.355" + cell $and $and$ls180.v:3947$444 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3947$443_Y + connect \B \main_port_cmd_valid + connect \Y $and$ls180.v:3947$444_Y + end + attribute \src "ls180.v:3948.34-3948.106" + cell $and $and$ls180.v:3948$447 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:3948$445_Y + connect \B $not$ls180.v:3948$446_Y + connect \Y $and$ls180.v:3948$447_Y + end + attribute \src "ls180.v:3952.110-3952.179" + cell $and $and$ls180.v:3952$450 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank0_lock + connect \B $eq$ls180.v:3952$449_Y + connect \Y $and$ls180.v:3952$450_Y + end + attribute \src "ls180.v:3952.185-3952.254" + cell $and $and$ls180.v:3952$453 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank1_lock + connect \B $eq$ls180.v:3952$452_Y + connect \Y $and$ls180.v:3952$453_Y + end + attribute \src "ls180.v:3952.260-3952.329" + cell $and $and$ls180.v:3952$456 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank2_lock + connect \B $eq$ls180.v:3952$455_Y + connect \Y $and$ls180.v:3952$456_Y + end + attribute \src "ls180.v:3952.41-3952.332" + cell $and $and$ls180.v:3952$459 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:3952$448_Y + connect \B $not$ls180.v:3952$458_Y + connect \Y $and$ls180.v:3952$459_Y + end + attribute \src "ls180.v:3952.40-3952.355" + cell $and $and$ls180.v:3952$460 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3952$459_Y + connect \B \main_port_cmd_valid + connect \Y $and$ls180.v:3952$460_Y + end + attribute \src "ls180.v:3953.34-3953.106" + cell $and $and$ls180.v:3953$463 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:3953$461_Y + connect \B $not$ls180.v:3953$462_Y + connect \Y $and$ls180.v:3953$463_Y + end + attribute \src "ls180.v:3957.151-3957.220" + cell $and $and$ls180.v:3957$467 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank1_lock + connect \B $eq$ls180.v:3957$466_Y + connect \Y $and$ls180.v:3957$467_Y + end + attribute \src "ls180.v:3957.226-3957.295" + cell $and $and$ls180.v:3957$470 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank2_lock + connect \B $eq$ls180.v:3957$469_Y + connect \Y $and$ls180.v:3957$470_Y + end + attribute \src "ls180.v:3957.301-3957.370" + cell $and $and$ls180.v:3957$473 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank3_lock + connect \B $eq$ls180.v:3957$472_Y + connect \Y $and$ls180.v:3957$473_Y + end + attribute \src "ls180.v:3957.82-3957.373" + cell $and $and$ls180.v:3957$476 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:3957$465_Y + connect \B $not$ls180.v:3957$475_Y + connect \Y $and$ls180.v:3957$476_Y + end + attribute \src "ls180.v:3957.43-3957.374" + cell $and $and$ls180.v:3957$477 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:3957$464_Y + connect \B $and$ls180.v:3957$476_Y + connect \Y $and$ls180.v:3957$477_Y + end + attribute \src "ls180.v:3957.42-3957.410" + cell $and $and$ls180.v:3957$478 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3957$477_Y + connect \B \main_sdram_interface_bank0_ready + connect \Y $and$ls180.v:3957$478_Y + end + attribute \src "ls180.v:3957.525-3957.594" + cell $and $and$ls180.v:3957$483 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank0_lock + connect \B $eq$ls180.v:3957$482_Y + connect \Y $and$ls180.v:3957$483_Y + end + attribute \src "ls180.v:3957.600-3957.669" + cell $and $and$ls180.v:3957$486 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank2_lock + connect \B $eq$ls180.v:3957$485_Y + connect \Y $and$ls180.v:3957$486_Y + end + attribute \src "ls180.v:3957.675-3957.744" + cell $and $and$ls180.v:3957$489 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank3_lock + connect \B $eq$ls180.v:3957$488_Y + connect \Y $and$ls180.v:3957$489_Y + end + attribute \src "ls180.v:3957.456-3957.747" + cell $and $and$ls180.v:3957$492 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:3957$481_Y + connect \B $not$ls180.v:3957$491_Y + connect \Y $and$ls180.v:3957$492_Y + end + attribute \src "ls180.v:3957.417-3957.748" + cell $and $and$ls180.v:3957$493 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:3957$480_Y + connect \B $and$ls180.v:3957$492_Y + connect \Y $and$ls180.v:3957$493_Y + end + attribute \src "ls180.v:3957.416-3957.784" + cell $and $and$ls180.v:3957$494 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3957$493_Y + connect \B \main_sdram_interface_bank1_ready + connect \Y $and$ls180.v:3957$494_Y + end + attribute \src "ls180.v:3957.899-3957.968" + cell $and $and$ls180.v:3957$499 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank0_lock + connect \B $eq$ls180.v:3957$498_Y + connect \Y $and$ls180.v:3957$499_Y + end + attribute \src "ls180.v:3957.974-3957.1043" + cell $and $and$ls180.v:3957$502 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank1_lock + connect \B $eq$ls180.v:3957$501_Y + connect \Y $and$ls180.v:3957$502_Y + end + attribute \src "ls180.v:3957.1049-3957.1118" + cell $and $and$ls180.v:3957$505 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank3_lock + connect \B $eq$ls180.v:3957$504_Y + connect \Y $and$ls180.v:3957$505_Y + end + attribute \src "ls180.v:3957.830-3957.1121" + cell $and $and$ls180.v:3957$508 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:3957$497_Y + connect \B $not$ls180.v:3957$507_Y + connect \Y $and$ls180.v:3957$508_Y + end + attribute \src "ls180.v:3957.791-3957.1122" + cell $and $and$ls180.v:3957$509 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:3957$496_Y + connect \B $and$ls180.v:3957$508_Y + connect \Y $and$ls180.v:3957$509_Y + end + attribute \src "ls180.v:3957.790-3957.1158" + cell $and $and$ls180.v:3957$510 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3957$509_Y + connect \B \main_sdram_interface_bank2_ready + connect \Y $and$ls180.v:3957$510_Y + end + attribute \src "ls180.v:3957.1273-3957.1342" + cell $and $and$ls180.v:3957$515 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank0_lock + connect \B $eq$ls180.v:3957$514_Y + connect \Y $and$ls180.v:3957$515_Y + end + attribute \src "ls180.v:3957.1348-3957.1417" + cell $and $and$ls180.v:3957$518 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank1_lock + connect \B $eq$ls180.v:3957$517_Y + connect \Y $and$ls180.v:3957$518_Y + end + attribute \src "ls180.v:3957.1423-3957.1492" + cell $and $and$ls180.v:3957$521 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank2_lock + connect \B $eq$ls180.v:3957$520_Y + connect \Y $and$ls180.v:3957$521_Y + end + attribute \src "ls180.v:3957.1204-3957.1495" + cell $and $and$ls180.v:3957$524 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:3957$513_Y + connect \B $not$ls180.v:3957$523_Y + connect \Y $and$ls180.v:3957$524_Y + end + attribute \src "ls180.v:3957.1165-3957.1496" + cell $and $and$ls180.v:3957$525 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:3957$512_Y + connect \B $and$ls180.v:3957$524_Y + connect \Y $and$ls180.v:3957$525_Y + end + attribute \src "ls180.v:3957.1164-3957.1532" + cell $and $and$ls180.v:3957$526 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3957$525_Y + connect \B \main_sdram_interface_bank3_ready + connect \Y $and$ls180.v:3957$526_Y + end + attribute \src "ls180.v:4015.9-4015.46" + cell $and $and$ls180.v:4015$532 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_wb_sdram_stb + connect \B \main_wb_sdram_cyc + connect \Y $and$ls180.v:4015$532_Y + end + attribute \src "ls180.v:4033.9-4033.46" + cell $and $and$ls180.v:4033$539 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_wb_sdram_stb + connect \B \main_wb_sdram_cyc + connect \Y $and$ls180.v:4033$539_Y + end + attribute \src "ls180.v:4046.32-4046.75" + cell $and $and$ls180.v:4046$543 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_litedram_wb_cyc + connect \B \main_litedram_wb_stb + connect \Y $and$ls180.v:4046$543_Y + end + attribute \src "ls180.v:4046.31-4046.99" + cell $and $and$ls180.v:4046$545 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4046$543_Y + connect \B $not$ls180.v:4046$544_Y + connect \Y $and$ls180.v:4046$545_Y + end + attribute \src "ls180.v:4047.34-4047.102" + cell $and $and$ls180.v:4047$547 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4047$546_Y + connect \B \main_port_cmd_payload_we + connect \Y $and$ls180.v:4047$547_Y + end + attribute \src "ls180.v:4047.33-4047.128" + cell $and $and$ls180.v:4047$549 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4047$547_Y + connect \B $not$ls180.v:4047$548_Y + connect \Y $and$ls180.v:4047$549_Y + end + attribute \src "ls180.v:4048.33-4048.104" + cell $and $and$ls180.v:4048$552 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4048$550_Y + connect \B $not$ls180.v:4048$551_Y + connect \Y $and$ls180.v:4048$552_Y + end + attribute \src "ls180.v:4049.49-4049.85" + cell $and $and$ls180.v:4049$553 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_litedram_wb_we + connect \B \main_ack_wdata + connect \Y $and$ls180.v:4049$553_Y + end + attribute \src "ls180.v:4049.90-4049.129" + cell $and $and$ls180.v:4049$555 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:4049$554_Y + connect \B \main_ack_rdata + connect \Y $and$ls180.v:4049$555_Y + end + attribute \src "ls180.v:4049.32-4049.131" + cell $and $and$ls180.v:4049$557 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_ack_cmd + connect \B $or$ls180.v:4049$556_Y + connect \Y $and$ls180.v:4049$557_Y + end + attribute \src "ls180.v:4050.25-4050.66" + cell $and $and$ls180.v:4050$558 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_valid + connect \B \main_port_cmd_ready + connect \Y $and$ls180.v:4050$558_Y + end + attribute \src "ls180.v:4051.27-4051.72" + cell $and $and$ls180.v:4051$560 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_port_wdata_valid + connect \B \main_port_wdata_ready + connect \Y $and$ls180.v:4051$560_Y + end + attribute \src "ls180.v:4052.26-4052.71" + cell $and $and$ls180.v:4052$562 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_port_rdata_valid + connect \B \main_port_rdata_ready + connect \Y $and$ls180.v:4052$562_Y + end + attribute \src "ls180.v:4081.64-4081.88" + cell $and $and$ls180.v:4081$568 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A 1'0 + connect \B \main_uart_rxtx_we + connect \Y $and$ls180.v:4081$568_Y + end + attribute \src "ls180.v:4085.7-4085.78" + cell $and $and$ls180.v:4085$572 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_eventmanager_pending_re + connect \B \main_uart_eventmanager_pending_r [0] + connect \Y $and$ls180.v:4085$572_Y + end + attribute \src "ls180.v:4096.7-4096.78" + cell $and $and$ls180.v:4096$575 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_eventmanager_pending_re + connect \B \main_uart_eventmanager_pending_r [1] + connect \Y $and$ls180.v:4096$575_Y + end + attribute \src "ls180.v:4105.26-4105.97" + cell $and $and$ls180.v:4105$577 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_eventmanager_pending_w [0] + connect \B \main_uart_eventmanager_storage [0] + connect \Y $and$ls180.v:4105$577_Y + end + attribute \src "ls180.v:4105.102-4105.173" + cell $and $and$ls180.v:4105$578 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_eventmanager_pending_w [1] + connect \B \main_uart_eventmanager_storage [1] + connect \Y $and$ls180.v:4105$578_Y + end + attribute \src "ls180.v:4120.41-4120.133" + cell $and $and$ls180.v:4120$582 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_tx_fifo_syncfifo_readable + connect \B $or$ls180.v:4120$581_Y + connect \Y $and$ls180.v:4120$582_Y + end + attribute \src "ls180.v:4131.39-4131.136" + cell $and $and$ls180.v:4131$587 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_tx_fifo_syncfifo_we + connect \B $or$ls180.v:4131$586_Y + connect \Y $and$ls180.v:4131$587_Y + end + attribute \src "ls180.v:4132.37-4132.104" + cell $and $and$ls180.v:4132$588 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_tx_fifo_syncfifo_readable + connect \B \main_uart_tx_fifo_syncfifo_re + connect \Y $and$ls180.v:4132$588_Y + end + attribute \src "ls180.v:4150.41-4150.133" + cell $and $and$ls180.v:4150$593 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_rx_fifo_syncfifo_readable + connect \B $or$ls180.v:4150$592_Y + connect \Y $and$ls180.v:4150$593_Y + end + attribute \src "ls180.v:4161.39-4161.136" + cell $and $and$ls180.v:4161$598 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_rx_fifo_syncfifo_we + connect \B $or$ls180.v:4161$597_Y + connect \Y $and$ls180.v:4161$598_Y + end + attribute \src "ls180.v:4162.37-4162.104" + cell $and $and$ls180.v:4162$599 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_rx_fifo_syncfifo_readable + connect \B \main_uart_rx_fifo_syncfifo_re + connect \Y $and$ls180.v:4162$599_Y + end + attribute \src "ls180.v:4287.33-4287.86" + cell $and $and$ls180.v:4287$633 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_clocker_clk1 + connect \B $not$ls180.v:4287$632_Y + connect \Y $and$ls180.v:4287$633_Y + end + attribute \src "ls180.v:4391.9-4391.68" + cell $and $and$ls180.v:4391$642 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdw_sink_valid + connect \B \main_sdphy_cmdw_pads_out_ready + connect \Y $and$ls180.v:4391$642_Y + end + attribute \src "ls180.v:4411.53-4411.145" + cell $and $and$ls180.v:4411$645 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_cmdr_pads_in_valid + connect \B $or$ls180.v:4411$644_Y + connect \Y $and$ls180.v:4411$645_Y + end + attribute \src "ls180.v:4430.52-4430.137" + cell $and $and$ls180.v:4430$648 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_cmdr_converter_sink_valid + connect \B \main_sdphy_cmdr_cmdr_converter_sink_ready + connect \Y $and$ls180.v:4430$648_Y + end + attribute \src "ls180.v:4471.9-4471.68" + cell $and $and$ls180.v:4471$656 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_source_valid + connect \B \main_sdphy_cmdr_source_ready + connect \Y $and$ls180.v:4471$656_Y + end + attribute \src "ls180.v:4509.9-4509.68" + cell $and $and$ls180.v:4509$662 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_source_valid + connect \B \main_sdphy_cmdr_source_ready + connect \Y $and$ls180.v:4509$662_Y + end + attribute \src "ls180.v:4518.10-4518.69" + cell $and $and$ls180.v:4518$663 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_sink_valid + connect \B \main_sdphy_cmdr_pads_out_ready + connect \Y $and$ls180.v:4518$663_Y + end + attribute \src "ls180.v:4518.9-4518.93" + cell $and $and$ls180.v:4518$664 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4518$663_Y + connect \B \main_sdphy_cmdw_done + connect \Y $and$ls180.v:4518$664_Y + end + attribute \src "ls180.v:4538.54-4538.117" + cell $and $and$ls180.v:4538$666 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_crcr_pads_in_valid + connect \B \main_sdphy_dataw_crcr_run + connect \Y $and$ls180.v:4538$666_Y + end + attribute \src "ls180.v:4557.53-4557.140" + cell $and $and$ls180.v:4557$669 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_crcr_converter_sink_valid + connect \B \main_sdphy_dataw_crcr_converter_sink_ready + connect \Y $and$ls180.v:4557$669_Y + end + attribute \src "ls180.v:4654.9-4654.70" + cell $and $and$ls180.v:4654$679 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_sink_valid + connect \B \main_sdphy_dataw_pads_out_ready + connect \Y $and$ls180.v:4654$679_Y + end + attribute \src "ls180.v:4672.55-4672.120" + cell $and $and$ls180.v:4672$681 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_datar_pads_in_valid + connect \B \main_sdphy_datar_datar_run + connect \Y $and$ls180.v:4672$681_Y + end + attribute \src "ls180.v:4691.54-4691.143" + cell $and $and$ls180.v:4691$684 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_datar_converter_sink_valid + connect \B \main_sdphy_datar_datar_converter_sink_ready + connect \Y $and$ls180.v:4691$684_Y + end + attribute \src "ls180.v:4773.9-4773.70" + cell $and $and$ls180.v:4773$699 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_source_valid + connect \B \main_sdphy_datar_source_ready + connect \Y $and$ls180.v:4773$699_Y + end + attribute \src "ls180.v:4780.9-4780.70" + cell $and $and$ls180.v:4780$700 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_sink_valid + connect \B \main_sdphy_datar_pads_out_ready + connect \Y $and$ls180.v:4780$700_Y + end + attribute \src "ls180.v:4861.48-4861.124" + cell $and $and$ls180.v:4861$823 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_sink_last + connect \B \main_sdcore_crc16_inserter_sink_valid + connect \Y $and$ls180.v:4861$823_Y + end + attribute \src "ls180.v:4861.47-4861.165" + cell $and $and$ls180.v:4861$824 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4861$823_Y + connect \B \main_sdcore_crc16_inserter_sink_ready + connect \Y $and$ls180.v:4861$824_Y + end + attribute \src "ls180.v:4862.50-4862.127" + cell $and $and$ls180.v:4862$825 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_sink_valid + connect \B \main_sdcore_crc16_inserter_sink_ready + connect \Y $and$ls180.v:4862$825_Y + end + attribute \src "ls180.v:4864.48-4864.124" + cell $and $and$ls180.v:4864$826 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_sink_last + connect \B \main_sdcore_crc16_inserter_sink_valid + connect \Y $and$ls180.v:4864$826_Y + end + attribute \src "ls180.v:4864.47-4864.165" + cell $and $and$ls180.v:4864$827 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4864$826_Y + connect \B \main_sdcore_crc16_inserter_sink_ready + connect \Y $and$ls180.v:4864$827_Y + end + attribute \src "ls180.v:4865.50-4865.127" + cell $and $and$ls180.v:4865$828 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_sink_valid + connect \B \main_sdcore_crc16_inserter_sink_ready + connect \Y $and$ls180.v:4865$828_Y + end + attribute \src "ls180.v:4867.48-4867.124" + cell $and $and$ls180.v:4867$829 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_sink_last + connect \B \main_sdcore_crc16_inserter_sink_valid + connect \Y $and$ls180.v:4867$829_Y + end + attribute \src "ls180.v:4867.47-4867.165" + cell $and $and$ls180.v:4867$830 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4867$829_Y + connect \B \main_sdcore_crc16_inserter_sink_ready + connect \Y $and$ls180.v:4867$830_Y + end + attribute \src "ls180.v:4868.50-4868.127" + cell $and $and$ls180.v:4868$831 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_sink_valid + connect \B \main_sdcore_crc16_inserter_sink_ready + connect \Y $and$ls180.v:4868$831_Y + end + attribute \src "ls180.v:4870.48-4870.124" + cell $and $and$ls180.v:4870$832 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_sink_last + connect \B \main_sdcore_crc16_inserter_sink_valid + connect \Y $and$ls180.v:4870$832_Y + end + attribute \src "ls180.v:4870.47-4870.165" + cell $and $and$ls180.v:4870$833 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4870$832_Y + connect \B \main_sdcore_crc16_inserter_sink_ready + connect \Y $and$ls180.v:4870$833_Y + end + attribute \src "ls180.v:4871.50-4871.127" + cell $and $and$ls180.v:4871$834 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_sink_valid + connect \B \main_sdcore_crc16_inserter_sink_ready + connect \Y $and$ls180.v:4871$834_Y + end + attribute \src "ls180.v:4984.10-4984.86" + cell $and $and$ls180.v:4984$883 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_sink_valid + connect \B \main_sdcore_crc16_inserter_sink_last + connect \Y $and$ls180.v:4984$883_Y + end + attribute \src "ls180.v:4984.9-4984.127" + cell $and $and$ls180.v:4984$884 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4984$883_Y + connect \B \main_sdcore_crc16_inserter_sink_ready + connect \Y $and$ls180.v:4984$884_Y + end + attribute \src "ls180.v:4994.9-4994.152" + cell $and $and$ls180.v:4994$888 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:4994$886_Y + connect \B $eq$ls180.v:4994$887_Y + connect \Y $and$ls180.v:4994$888_Y + end + attribute \src "ls180.v:4994.8-4994.226" + cell $and $and$ls180.v:4994$890 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4994$888_Y + connect \B $eq$ls180.v:4994$889_Y + connect \Y $and$ls180.v:4994$890_Y + end + attribute \src "ls180.v:4994.7-4994.300" + cell $and $and$ls180.v:4994$892 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4994$890_Y + connect \B $eq$ls180.v:4994$891_Y + connect \Y $and$ls180.v:4994$892_Y + end + attribute \src "ls180.v:4999.49-4999.124" + cell $and $and$ls180.v:4999$893 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_sink_valid + connect \B \main_sdcore_crc16_checker_sink_ready + connect \Y $and$ls180.v:4999$893_Y + end + attribute \src "ls180.v:5009.49-5009.124" + cell $and $and$ls180.v:5009$896 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_sink_valid + connect \B \main_sdcore_crc16_checker_sink_ready + connect \Y $and$ls180.v:5009$896_Y + end + attribute \src "ls180.v:5019.49-5019.124" + cell $and $and$ls180.v:5019$899 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_sink_valid + connect \B \main_sdcore_crc16_checker_sink_ready + connect \Y $and$ls180.v:5019$899_Y + end + attribute \src "ls180.v:5029.49-5029.124" + cell $and $and$ls180.v:5029$902 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_sink_valid + connect \B \main_sdcore_crc16_checker_sink_ready + connect \Y $and$ls180.v:5029$902_Y + end + attribute \src "ls180.v:5041.7-5041.84" + cell $and $and$ls180.v:5041$907 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_sink_valid + connect \B $gt$ls180.v:5041$906_Y + connect \Y $and$ls180.v:5041$907_Y + end + attribute \src "ls180.v:5159.9-5159.64" + cell $and $and$ls180.v:5159$956 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdw_sink_valid + connect \B \main_sdphy_cmdw_sink_ready + connect \Y $and$ls180.v:5159$956_Y + end + attribute \src "ls180.v:5211.10-5211.66" + cell $and $and$ls180.v:5211$965 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_sink_valid + connect \B \main_sdphy_dataw_sink_last + connect \Y $and$ls180.v:5211$965_Y + end + attribute \src "ls180.v:5211.9-5211.97" + cell $and $and$ls180.v:5211$966 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5211$965_Y + connect \B \main_sdphy_dataw_sink_ready + connect \Y $and$ls180.v:5211$966_Y + end + attribute \src "ls180.v:5237.11-5237.71" + cell $and $and$ls180.v:5237$974 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_source_last + connect \B \main_sdphy_datar_source_ready + connect \Y $and$ls180.v:5237$974_Y + end + attribute \src "ls180.v:5321.43-5321.152" + cell $and $and$ls180.v:5321$982 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_fifo_syncfifo_we + connect \B $or$ls180.v:5321$981_Y + connect \Y $and$ls180.v:5321$982_Y + end + attribute \src "ls180.v:5322.41-5322.116" + cell $and $and$ls180.v:5322$983 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_fifo_syncfifo_readable + connect \B \main_sdblock2mem_fifo_syncfifo_re + connect \Y $and$ls180.v:5322$983_Y + end + attribute \src "ls180.v:5334.48-5334.125" + cell $and $and$ls180.v:5334$988 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_converter_sink_valid + connect \B \main_sdblock2mem_converter_sink_ready + connect \Y $and$ls180.v:5334$988_Y + end + attribute \src "ls180.v:5361.9-5361.102" + cell $and $and$ls180.v:5361$992 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_wishbonedmawriter_sink_valid + connect \B \main_sdblock2mem_wishbonedmawriter_sink_ready + connect \Y $and$ls180.v:5361$992_Y + end + attribute \src "ls180.v:5434.9-5434.58" + cell $and $and$ls180.v:5434$998 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface1_bus_stb + connect \B \main_interface1_bus_ack + connect \Y $and$ls180.v:5434$998_Y + end + attribute \src "ls180.v:5487.51-5487.123" + cell $and $and$ls180.v:5487$1006 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_converter_sink_first + connect \B \main_sdmem2block_converter_first + connect \Y $and$ls180.v:5487$1006_Y + end + attribute \src "ls180.v:5488.50-5488.120" + cell $and $and$ls180.v:5488$1007 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_converter_sink_last + connect \B \main_sdmem2block_converter_last + connect \Y $and$ls180.v:5488$1007_Y + end + attribute \src "ls180.v:5489.49-5489.122" + cell $and $and$ls180.v:5489$1008 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_converter_last + connect \B \main_sdmem2block_converter_source_ready + connect \Y $and$ls180.v:5489$1008_Y + end + attribute \src "ls180.v:5529.43-5529.152" + cell $and $and$ls180.v:5529$1013 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_fifo_syncfifo_we + connect \B $or$ls180.v:5529$1012_Y + connect \Y $and$ls180.v:5529$1013_Y + end + attribute \src "ls180.v:5530.41-5530.116" + cell $and $and$ls180.v:5530$1014 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_fifo_syncfifo_readable + connect \B \main_sdmem2block_fifo_syncfifo_re + connect \Y $and$ls180.v:5530$1014_Y + end + attribute \src "ls180.v:5621.9-5621.76" + cell $and $and$ls180.v:5621$1026 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_libresocsim_wishbone_cyc + connect \B \builder_libresocsim_wishbone_stb + connect \Y $and$ls180.v:5621$1026_Y + end + attribute \src "ls180.v:5624.44-5624.120" + cell $and $and$ls180.v:5624$1028 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_libresocsim_wishbone_we + connect \B $ne$ls180.v:5624$1027_Y + connect \Y $and$ls180.v:5624$1028_Y + end + attribute \src "ls180.v:5644.63-5644.107" + cell $and $and$ls180.v:5644$1030 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_ack + connect \B $eq$ls180.v:5644$1029_Y + connect \Y $and$ls180.v:5644$1030_Y + end + attribute \src "ls180.v:5645.63-5645.107" + cell $and $and$ls180.v:5645$1032 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_ack + connect \B $eq$ls180.v:5645$1031_Y + connect \Y $and$ls180.v:5645$1032_Y + end + attribute \src "ls180.v:5646.63-5646.107" + cell $and $and$ls180.v:5646$1034 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_ack + connect \B $eq$ls180.v:5646$1033_Y + connect \Y $and$ls180.v:5646$1034_Y + end + attribute \src "ls180.v:5647.35-5647.79" + cell $and $and$ls180.v:5647$1036 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_ack + connect \B $eq$ls180.v:5647$1035_Y + connect \Y $and$ls180.v:5647$1036_Y + end + attribute \src "ls180.v:5648.35-5648.79" + cell $and $and$ls180.v:5648$1038 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_ack + connect \B $eq$ls180.v:5648$1037_Y + connect \Y $and$ls180.v:5648$1038_Y + end + attribute \src "ls180.v:5649.63-5649.107" + cell $and $and$ls180.v:5649$1040 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_err + connect \B $eq$ls180.v:5649$1039_Y + connect \Y $and$ls180.v:5649$1040_Y + end + attribute \src "ls180.v:5650.63-5650.107" + cell $and $and$ls180.v:5650$1042 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_err + connect \B $eq$ls180.v:5650$1041_Y + connect \Y $and$ls180.v:5650$1042_Y + end + attribute \src "ls180.v:5651.63-5651.107" + cell $and $and$ls180.v:5651$1044 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_err + connect \B $eq$ls180.v:5651$1043_Y + connect \Y $and$ls180.v:5651$1044_Y + end + attribute \src "ls180.v:5652.35-5652.79" + cell $and $and$ls180.v:5652$1046 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_err + connect \B $eq$ls180.v:5652$1045_Y + connect \Y $and$ls180.v:5652$1046_Y + end + attribute \src "ls180.v:5653.35-5653.79" + cell $and $and$ls180.v:5653$1048 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_err + connect \B $eq$ls180.v:5653$1047_Y + connect \Y $and$ls180.v:5653$1048_Y + end + attribute \src "ls180.v:5698.40-5698.81" + cell $and $and$ls180.v:5698$1055 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_cyc + connect \B \builder_slave_sel [0] + connect \Y $and$ls180.v:5698$1055_Y + end + attribute \src "ls180.v:5699.50-5699.91" + cell $and $and$ls180.v:5699$1056 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_cyc + connect \B \builder_slave_sel [1] + connect \Y $and$ls180.v:5699$1056_Y + end + attribute \src "ls180.v:5700.50-5700.91" + cell $and $and$ls180.v:5700$1057 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_cyc + connect \B \builder_slave_sel [2] + connect \Y $and$ls180.v:5700$1057_Y + end + attribute \src "ls180.v:5701.29-5701.70" + cell $and $and$ls180.v:5701$1058 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_cyc + connect \B \builder_slave_sel [3] + connect \Y $and$ls180.v:5701$1058_Y + end + attribute \src "ls180.v:5702.44-5702.85" + cell $and $and$ls180.v:5702$1059 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_cyc + connect \B \builder_slave_sel [4] + connect \Y $and$ls180.v:5702$1059_Y + end + attribute \src "ls180.v:5704.25-5704.64" + cell $and $and$ls180.v:5704$1064 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_stb + connect \B \builder_shared_cyc + connect \Y $and$ls180.v:5704$1064_Y + end + attribute \src "ls180.v:5704.24-5704.89" + cell $and $and$ls180.v:5704$1066 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5704$1064_Y + connect \B $not$ls180.v:5704$1065_Y + connect \Y $and$ls180.v:5704$1066_Y + end + attribute \src "ls180.v:5710.31-5710.92" + cell $and $and$ls180.v:5710$1072 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A { \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] } + connect \B \main_libresocsim_ram_bus_dat_r + connect \Y $and$ls180.v:5710$1072_Y + end + attribute \src "ls180.v:5710.97-5710.168" + cell $and $and$ls180.v:5710$1073 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A { \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] } + connect \B \main_libresocsim_libresoc_xics_icp_dat_r + connect \Y $and$ls180.v:5710$1073_Y + end + attribute \src "ls180.v:5710.174-5710.245" + cell $and $and$ls180.v:5710$1075 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A { \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] } + connect \B \main_libresocsim_libresoc_xics_ics_dat_r + connect \Y $and$ls180.v:5710$1075_Y + end + attribute \src "ls180.v:5710.251-5710.301" + cell $and $and$ls180.v:5710$1077 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A { \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] } + connect \B \main_wb_sdram_dat_r + connect \Y $and$ls180.v:5710$1077_Y + end + attribute \src "ls180.v:5710.307-5710.372" + cell $and $and$ls180.v:5710$1079 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A { \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] } + connect \B \builder_libresocsim_wishbone_dat_r + connect \Y $and$ls180.v:5710$1079_Y + end + attribute \src "ls180.v:5720.39-5720.92" + cell $and $and$ls180.v:5720$1083 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B \builder_interface0_bank_bus_we + connect \Y $and$ls180.v:5720$1083_Y + end + attribute \src "ls180.v:5720.38-5720.142" + cell $and $and$ls180.v:5720$1085 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5720$1083_Y + connect \B $eq$ls180.v:5720$1084_Y + connect \Y $and$ls180.v:5720$1085_Y + end + attribute \src "ls180.v:5721.39-5721.95" + cell $and $and$ls180.v:5721$1087 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B $not$ls180.v:5721$1086_Y + connect \Y $and$ls180.v:5721$1087_Y + end + attribute \src "ls180.v:5721.38-5721.145" + cell $and $and$ls180.v:5721$1089 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5721$1087_Y + connect \B $eq$ls180.v:5721$1088_Y + connect \Y $and$ls180.v:5721$1089_Y + end + attribute \src "ls180.v:5723.41-5723.94" + cell $and $and$ls180.v:5723$1090 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B \builder_interface0_bank_bus_we + connect \Y $and$ls180.v:5723$1090_Y + end + attribute \src "ls180.v:5723.40-5723.144" + cell $and $and$ls180.v:5723$1092 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5723$1090_Y + connect \B $eq$ls180.v:5723$1091_Y + connect \Y $and$ls180.v:5723$1092_Y + end + attribute \src "ls180.v:5724.41-5724.97" + cell $and $and$ls180.v:5724$1094 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B $not$ls180.v:5724$1093_Y + connect \Y $and$ls180.v:5724$1094_Y + end + attribute \src "ls180.v:5724.40-5724.147" + cell $and $and$ls180.v:5724$1096 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5724$1094_Y + connect \B $eq$ls180.v:5724$1095_Y + connect \Y $and$ls180.v:5724$1096_Y + end + attribute \src "ls180.v:5726.41-5726.94" + cell $and $and$ls180.v:5726$1097 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B \builder_interface0_bank_bus_we + connect \Y $and$ls180.v:5726$1097_Y + end + attribute \src "ls180.v:5726.40-5726.144" + cell $and $and$ls180.v:5726$1099 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5726$1097_Y + connect \B $eq$ls180.v:5726$1098_Y + connect \Y $and$ls180.v:5726$1099_Y + end + attribute \src "ls180.v:5727.41-5727.97" + cell $and $and$ls180.v:5727$1101 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B $not$ls180.v:5727$1100_Y + connect \Y $and$ls180.v:5727$1101_Y + end + attribute \src "ls180.v:5727.40-5727.147" + cell $and $and$ls180.v:5727$1103 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5727$1101_Y + connect \B $eq$ls180.v:5727$1102_Y + connect \Y $and$ls180.v:5727$1103_Y + end + attribute \src "ls180.v:5729.41-5729.94" + cell $and $and$ls180.v:5729$1104 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B \builder_interface0_bank_bus_we + connect \Y $and$ls180.v:5729$1104_Y + end + attribute \src "ls180.v:5729.40-5729.144" + cell $and $and$ls180.v:5729$1106 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5729$1104_Y + connect \B $eq$ls180.v:5729$1105_Y + connect \Y $and$ls180.v:5729$1106_Y + end + attribute \src "ls180.v:5730.41-5730.97" + cell $and $and$ls180.v:5730$1108 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B $not$ls180.v:5730$1107_Y + connect \Y $and$ls180.v:5730$1108_Y + end + attribute \src "ls180.v:5730.40-5730.147" + cell $and $and$ls180.v:5730$1110 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5730$1108_Y + connect \B $eq$ls180.v:5730$1109_Y + connect \Y $and$ls180.v:5730$1110_Y + end + attribute \src "ls180.v:5732.41-5732.94" + cell $and $and$ls180.v:5732$1111 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B \builder_interface0_bank_bus_we + connect \Y $and$ls180.v:5732$1111_Y + end + attribute \src "ls180.v:5732.40-5732.144" + cell $and $and$ls180.v:5732$1113 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5732$1111_Y + connect \B $eq$ls180.v:5732$1112_Y + connect \Y $and$ls180.v:5732$1113_Y + end + attribute \src "ls180.v:5733.41-5733.97" + cell $and $and$ls180.v:5733$1115 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B $not$ls180.v:5733$1114_Y + connect \Y $and$ls180.v:5733$1115_Y + end + attribute \src "ls180.v:5733.40-5733.147" + cell $and $and$ls180.v:5733$1117 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5733$1115_Y + connect \B $eq$ls180.v:5733$1116_Y + connect \Y $and$ls180.v:5733$1117_Y + end + attribute \src "ls180.v:5735.44-5735.97" + cell $and $and$ls180.v:5735$1118 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B \builder_interface0_bank_bus_we + connect \Y $and$ls180.v:5735$1118_Y + end + attribute \src "ls180.v:5735.43-5735.147" + cell $and $and$ls180.v:5735$1120 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5735$1118_Y + connect \B $eq$ls180.v:5735$1119_Y + connect \Y $and$ls180.v:5735$1120_Y + end + attribute \src "ls180.v:5736.44-5736.100" + cell $and $and$ls180.v:5736$1122 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B $not$ls180.v:5736$1121_Y + connect \Y $and$ls180.v:5736$1122_Y + end + attribute \src "ls180.v:5736.43-5736.150" + cell $and $and$ls180.v:5736$1124 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5736$1122_Y + connect \B $eq$ls180.v:5736$1123_Y + connect \Y $and$ls180.v:5736$1124_Y + end + attribute \src "ls180.v:5738.44-5738.97" + cell $and $and$ls180.v:5738$1125 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B \builder_interface0_bank_bus_we + connect \Y $and$ls180.v:5738$1125_Y + end + attribute \src "ls180.v:5738.43-5738.147" + cell $and $and$ls180.v:5738$1127 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5738$1125_Y + connect \B $eq$ls180.v:5738$1126_Y + connect \Y $and$ls180.v:5738$1127_Y + end + attribute \src "ls180.v:5739.44-5739.100" + cell $and $and$ls180.v:5739$1129 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B $not$ls180.v:5739$1128_Y + connect \Y $and$ls180.v:5739$1129_Y + end + attribute \src "ls180.v:5739.43-5739.150" + cell $and $and$ls180.v:5739$1131 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5739$1129_Y + connect \B $eq$ls180.v:5739$1130_Y + connect \Y $and$ls180.v:5739$1131_Y + end + attribute \src "ls180.v:5741.44-5741.97" + cell $and $and$ls180.v:5741$1132 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B \builder_interface0_bank_bus_we + connect \Y $and$ls180.v:5741$1132_Y + end + attribute \src "ls180.v:5741.43-5741.147" + cell $and $and$ls180.v:5741$1134 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5741$1132_Y + connect \B $eq$ls180.v:5741$1133_Y + connect \Y $and$ls180.v:5741$1134_Y + end + attribute \src "ls180.v:5742.44-5742.100" + cell $and $and$ls180.v:5742$1136 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B $not$ls180.v:5742$1135_Y + connect \Y $and$ls180.v:5742$1136_Y + end + attribute \src "ls180.v:5742.43-5742.150" + cell $and $and$ls180.v:5742$1138 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5742$1136_Y + connect \B $eq$ls180.v:5742$1137_Y + connect \Y $and$ls180.v:5742$1138_Y + end + attribute \src "ls180.v:5744.44-5744.97" + cell $and $and$ls180.v:5744$1139 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B \builder_interface0_bank_bus_we + connect \Y $and$ls180.v:5744$1139_Y + end + attribute \src "ls180.v:5744.43-5744.147" + cell $and $and$ls180.v:5744$1141 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5744$1139_Y + connect \B $eq$ls180.v:5744$1140_Y + connect \Y $and$ls180.v:5744$1141_Y + end + attribute \src "ls180.v:5745.44-5745.100" + cell $and $and$ls180.v:5745$1143 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B $not$ls180.v:5745$1142_Y + connect \Y $and$ls180.v:5745$1143_Y + end + attribute \src "ls180.v:5745.43-5745.150" + cell $and $and$ls180.v:5745$1145 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5745$1143_Y + connect \B $eq$ls180.v:5745$1144_Y + connect \Y $and$ls180.v:5745$1145_Y + end + attribute \src "ls180.v:5758.36-5758.89" + cell $and $and$ls180.v:5758$1147 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank1_sel + connect \B \builder_interface1_bank_bus_we + connect \Y $and$ls180.v:5758$1147_Y + end + attribute \src "ls180.v:5758.35-5758.139" + cell $and $and$ls180.v:5758$1149 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5758$1147_Y + connect \B $eq$ls180.v:5758$1148_Y + connect \Y $and$ls180.v:5758$1149_Y + end + attribute \src "ls180.v:5759.36-5759.92" + cell $and $and$ls180.v:5759$1151 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank1_sel + connect \B $not$ls180.v:5759$1150_Y + connect \Y $and$ls180.v:5759$1151_Y + end + attribute \src "ls180.v:5759.35-5759.142" + cell $and $and$ls180.v:5759$1153 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5759$1151_Y + connect \B $eq$ls180.v:5759$1152_Y + connect \Y $and$ls180.v:5759$1153_Y + end + attribute \src "ls180.v:5761.36-5761.89" + cell $and $and$ls180.v:5761$1154 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank1_sel + connect \B \builder_interface1_bank_bus_we + connect \Y $and$ls180.v:5761$1154_Y + end + attribute \src "ls180.v:5761.35-5761.139" + cell $and $and$ls180.v:5761$1156 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5761$1154_Y + connect \B $eq$ls180.v:5761$1155_Y + connect \Y $and$ls180.v:5761$1156_Y + end + attribute \src "ls180.v:5762.36-5762.92" + cell $and $and$ls180.v:5762$1158 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank1_sel + connect \B $not$ls180.v:5762$1157_Y + connect \Y $and$ls180.v:5762$1158_Y + end + attribute \src "ls180.v:5762.35-5762.142" + cell $and $and$ls180.v:5762$1160 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5762$1158_Y + connect \B $eq$ls180.v:5762$1159_Y + connect \Y $and$ls180.v:5762$1160_Y + end + attribute \src "ls180.v:5764.36-5764.89" + cell $and $and$ls180.v:5764$1161 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank1_sel + connect \B \builder_interface1_bank_bus_we + connect \Y $and$ls180.v:5764$1161_Y + end + attribute \src "ls180.v:5764.35-5764.139" + cell $and $and$ls180.v:5764$1163 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5764$1161_Y + connect \B $eq$ls180.v:5764$1162_Y + connect \Y $and$ls180.v:5764$1163_Y + end + attribute \src "ls180.v:5765.36-5765.92" + cell $and $and$ls180.v:5765$1165 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank1_sel + connect \B $not$ls180.v:5765$1164_Y + connect \Y $and$ls180.v:5765$1165_Y + end + attribute \src "ls180.v:5765.35-5765.142" + cell $and $and$ls180.v:5765$1167 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5765$1165_Y + connect \B $eq$ls180.v:5765$1166_Y + connect \Y $and$ls180.v:5765$1167_Y + end + attribute \src "ls180.v:5767.36-5767.89" + cell $and $and$ls180.v:5767$1168 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank1_sel + connect \B \builder_interface1_bank_bus_we + connect \Y $and$ls180.v:5767$1168_Y + end + attribute \src "ls180.v:5767.35-5767.139" + cell $and $and$ls180.v:5767$1170 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5767$1168_Y + connect \B $eq$ls180.v:5767$1169_Y + connect \Y $and$ls180.v:5767$1170_Y + end + attribute \src "ls180.v:5768.36-5768.92" + cell $and $and$ls180.v:5768$1172 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank1_sel + connect \B $not$ls180.v:5768$1171_Y + connect \Y $and$ls180.v:5768$1172_Y + end + attribute \src "ls180.v:5768.35-5768.142" + cell $and $and$ls180.v:5768$1174 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5768$1172_Y + connect \B $eq$ls180.v:5768$1173_Y + connect \Y $and$ls180.v:5768$1174_Y + end + attribute \src "ls180.v:5770.37-5770.90" + cell $and $and$ls180.v:5770$1175 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank1_sel + connect \B \builder_interface1_bank_bus_we + connect \Y $and$ls180.v:5770$1175_Y + end + attribute \src "ls180.v:5770.36-5770.140" + cell $and $and$ls180.v:5770$1177 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5770$1175_Y + connect \B $eq$ls180.v:5770$1176_Y + connect \Y $and$ls180.v:5770$1177_Y + end + attribute \src "ls180.v:5771.37-5771.93" + cell $and $and$ls180.v:5771$1179 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank1_sel + connect \B $not$ls180.v:5771$1178_Y + connect \Y $and$ls180.v:5771$1179_Y + end + attribute \src "ls180.v:5771.36-5771.143" + cell $and $and$ls180.v:5771$1181 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5771$1179_Y + connect \B $eq$ls180.v:5771$1180_Y + connect \Y $and$ls180.v:5771$1181_Y + end + attribute \src "ls180.v:5773.37-5773.90" + cell $and $and$ls180.v:5773$1182 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank1_sel + connect \B \builder_interface1_bank_bus_we + connect \Y $and$ls180.v:5773$1182_Y + end + attribute \src "ls180.v:5773.36-5773.140" + cell $and $and$ls180.v:5773$1184 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5773$1182_Y + connect \B $eq$ls180.v:5773$1183_Y + connect \Y $and$ls180.v:5773$1184_Y + end + attribute \src "ls180.v:5774.37-5774.93" + cell $and $and$ls180.v:5774$1186 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank1_sel + connect \B $not$ls180.v:5774$1185_Y + connect \Y $and$ls180.v:5774$1186_Y + end + attribute \src "ls180.v:5774.36-5774.143" + cell $and $and$ls180.v:5774$1188 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5774$1186_Y + connect \B $eq$ls180.v:5774$1187_Y + connect \Y $and$ls180.v:5774$1188_Y + end + attribute \src "ls180.v:5784.40-5784.93" + cell $and $and$ls180.v:5784$1190 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank2_sel + connect \B \builder_interface2_bank_bus_we + connect \Y $and$ls180.v:5784$1190_Y + end + attribute \src "ls180.v:5784.39-5784.143" + cell $and $and$ls180.v:5784$1192 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5784$1190_Y + connect \B $eq$ls180.v:5784$1191_Y + connect \Y $and$ls180.v:5784$1192_Y + end + attribute \src "ls180.v:5785.40-5785.96" + cell $and $and$ls180.v:5785$1194 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank2_sel + connect \B $not$ls180.v:5785$1193_Y + connect \Y $and$ls180.v:5785$1194_Y + end + attribute \src "ls180.v:5785.39-5785.146" + cell $and $and$ls180.v:5785$1196 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5785$1194_Y + connect \B $eq$ls180.v:5785$1195_Y + connect \Y $and$ls180.v:5785$1196_Y + end + attribute \src "ls180.v:5787.39-5787.92" + cell $and $and$ls180.v:5787$1197 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank2_sel + connect \B \builder_interface2_bank_bus_we + connect \Y $and$ls180.v:5787$1197_Y + end + attribute \src "ls180.v:5787.38-5787.142" + cell $and $and$ls180.v:5787$1199 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5787$1197_Y + connect \B $eq$ls180.v:5787$1198_Y + connect \Y $and$ls180.v:5787$1199_Y + end + attribute \src "ls180.v:5788.39-5788.95" + cell $and $and$ls180.v:5788$1201 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank2_sel + connect \B $not$ls180.v:5788$1200_Y + connect \Y $and$ls180.v:5788$1201_Y + end + attribute \src "ls180.v:5788.38-5788.145" + cell $and $and$ls180.v:5788$1203 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5788$1201_Y + connect \B $eq$ls180.v:5788$1202_Y + connect \Y $and$ls180.v:5788$1203_Y + end + attribute \src "ls180.v:5790.39-5790.92" + cell $and $and$ls180.v:5790$1204 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank2_sel + connect \B \builder_interface2_bank_bus_we + connect \Y $and$ls180.v:5790$1204_Y + end + attribute \src "ls180.v:5790.38-5790.142" + cell $and $and$ls180.v:5790$1206 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5790$1204_Y + connect \B $eq$ls180.v:5790$1205_Y + connect \Y $and$ls180.v:5790$1206_Y + end + attribute \src "ls180.v:5791.39-5791.95" + cell $and $and$ls180.v:5791$1208 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank2_sel + connect \B $not$ls180.v:5791$1207_Y + connect \Y $and$ls180.v:5791$1208_Y + end + attribute \src "ls180.v:5791.38-5791.145" + cell $and $and$ls180.v:5791$1210 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5791$1208_Y + connect \B $eq$ls180.v:5791$1209_Y + connect \Y $and$ls180.v:5791$1210_Y + end + attribute \src "ls180.v:5793.39-5793.92" + cell $and $and$ls180.v:5793$1211 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank2_sel + connect \B \builder_interface2_bank_bus_we + connect \Y $and$ls180.v:5793$1211_Y + end + attribute \src "ls180.v:5793.38-5793.142" + cell $and $and$ls180.v:5793$1213 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5793$1211_Y + connect \B $eq$ls180.v:5793$1212_Y + connect \Y $and$ls180.v:5793$1213_Y + end + attribute \src "ls180.v:5794.39-5794.95" + cell $and $and$ls180.v:5794$1215 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank2_sel + connect \B $not$ls180.v:5794$1214_Y + connect \Y $and$ls180.v:5794$1215_Y + end + attribute \src "ls180.v:5794.38-5794.145" + cell $and $and$ls180.v:5794$1217 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5794$1215_Y + connect \B $eq$ls180.v:5794$1216_Y + connect \Y $and$ls180.v:5794$1217_Y + end + attribute \src "ls180.v:5796.39-5796.92" + cell $and $and$ls180.v:5796$1218 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank2_sel + connect \B \builder_interface2_bank_bus_we + connect \Y $and$ls180.v:5796$1218_Y + end + attribute \src "ls180.v:5796.38-5796.142" + cell $and $and$ls180.v:5796$1220 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5796$1218_Y + connect \B $eq$ls180.v:5796$1219_Y + connect \Y $and$ls180.v:5796$1220_Y + end + attribute \src "ls180.v:5797.39-5797.95" + cell $and $and$ls180.v:5797$1222 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank2_sel + connect \B $not$ls180.v:5797$1221_Y + connect \Y $and$ls180.v:5797$1222_Y + end + attribute \src "ls180.v:5797.38-5797.145" + cell $and $and$ls180.v:5797$1224 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5797$1222_Y + connect \B $eq$ls180.v:5797$1223_Y + connect \Y $and$ls180.v:5797$1224_Y + end + attribute \src "ls180.v:5799.40-5799.93" + cell $and $and$ls180.v:5799$1225 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank2_sel + connect \B \builder_interface2_bank_bus_we + connect \Y $and$ls180.v:5799$1225_Y + end + attribute \src "ls180.v:5799.39-5799.143" + cell $and $and$ls180.v:5799$1227 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5799$1225_Y + connect \B $eq$ls180.v:5799$1226_Y + connect \Y $and$ls180.v:5799$1227_Y + end + attribute \src "ls180.v:5800.40-5800.96" + cell $and $and$ls180.v:5800$1229 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank2_sel + connect \B $not$ls180.v:5800$1228_Y + connect \Y $and$ls180.v:5800$1229_Y + end + attribute \src "ls180.v:5800.39-5800.146" + cell $and $and$ls180.v:5800$1231 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5800$1229_Y + connect \B $eq$ls180.v:5800$1230_Y + connect \Y $and$ls180.v:5800$1231_Y + end + attribute \src "ls180.v:5802.40-5802.93" + cell $and $and$ls180.v:5802$1232 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank2_sel + connect \B \builder_interface2_bank_bus_we + connect \Y $and$ls180.v:5802$1232_Y + end + attribute \src "ls180.v:5802.39-5802.143" + cell $and $and$ls180.v:5802$1234 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5802$1232_Y + connect \B $eq$ls180.v:5802$1233_Y + connect \Y $and$ls180.v:5802$1234_Y + end + attribute \src "ls180.v:5803.40-5803.96" + cell $and $and$ls180.v:5803$1236 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank2_sel + connect \B $not$ls180.v:5803$1235_Y + connect \Y $and$ls180.v:5803$1236_Y + end + attribute \src "ls180.v:5803.39-5803.146" + cell $and $and$ls180.v:5803$1238 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5803$1236_Y + connect \B $eq$ls180.v:5803$1237_Y + connect \Y $and$ls180.v:5803$1238_Y + end + attribute \src "ls180.v:5805.40-5805.93" + cell $and $and$ls180.v:5805$1239 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank2_sel + connect \B \builder_interface2_bank_bus_we + connect \Y $and$ls180.v:5805$1239_Y + end + attribute \src "ls180.v:5805.39-5805.143" + cell $and $and$ls180.v:5805$1241 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5805$1239_Y + connect \B $eq$ls180.v:5805$1240_Y + connect \Y $and$ls180.v:5805$1241_Y + end + attribute \src "ls180.v:5806.40-5806.96" + cell $and $and$ls180.v:5806$1243 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank2_sel + connect \B $not$ls180.v:5806$1242_Y + connect \Y $and$ls180.v:5806$1243_Y + end + attribute \src "ls180.v:5806.39-5806.146" + cell $and $and$ls180.v:5806$1245 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5806$1243_Y + connect \B $eq$ls180.v:5806$1244_Y + connect \Y $and$ls180.v:5806$1245_Y + end + attribute \src "ls180.v:5808.40-5808.93" + cell $and $and$ls180.v:5808$1246 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank2_sel + connect \B \builder_interface2_bank_bus_we + connect \Y $and$ls180.v:5808$1246_Y + end + attribute \src "ls180.v:5808.39-5808.143" + cell $and $and$ls180.v:5808$1248 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5808$1246_Y + connect \B $eq$ls180.v:5808$1247_Y + connect \Y $and$ls180.v:5808$1248_Y + end + attribute \src "ls180.v:5809.40-5809.96" + cell $and $and$ls180.v:5809$1250 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank2_sel + connect \B $not$ls180.v:5809$1249_Y + connect \Y $and$ls180.v:5809$1250_Y + end + attribute \src "ls180.v:5809.39-5809.146" + cell $and $and$ls180.v:5809$1252 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5809$1250_Y + connect \B $eq$ls180.v:5809$1251_Y + connect \Y $and$ls180.v:5809$1252_Y + end + attribute \src "ls180.v:5821.40-5821.93" + cell $and $and$ls180.v:5821$1254 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B \builder_interface3_bank_bus_we + connect \Y $and$ls180.v:5821$1254_Y + end + attribute \src "ls180.v:5821.39-5821.143" + cell $and $and$ls180.v:5821$1256 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5821$1254_Y + connect \B $eq$ls180.v:5821$1255_Y + connect \Y $and$ls180.v:5821$1256_Y + end + attribute \src "ls180.v:5822.40-5822.96" + cell $and $and$ls180.v:5822$1258 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B $not$ls180.v:5822$1257_Y + connect \Y $and$ls180.v:5822$1258_Y + end + attribute \src "ls180.v:5822.39-5822.146" + cell $and $and$ls180.v:5822$1260 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5822$1258_Y + connect \B $eq$ls180.v:5822$1259_Y + connect \Y $and$ls180.v:5822$1260_Y + end + attribute \src "ls180.v:5824.39-5824.92" + cell $and $and$ls180.v:5824$1261 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B \builder_interface3_bank_bus_we + connect \Y $and$ls180.v:5824$1261_Y + end + attribute \src "ls180.v:5824.38-5824.142" + cell $and $and$ls180.v:5824$1263 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5824$1261_Y + connect \B $eq$ls180.v:5824$1262_Y + connect \Y $and$ls180.v:5824$1263_Y + end + attribute \src "ls180.v:5825.39-5825.95" + cell $and $and$ls180.v:5825$1265 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B $not$ls180.v:5825$1264_Y + connect \Y $and$ls180.v:5825$1265_Y + end + attribute \src "ls180.v:5825.38-5825.145" + cell $and $and$ls180.v:5825$1267 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5825$1265_Y + connect \B $eq$ls180.v:5825$1266_Y + connect \Y $and$ls180.v:5825$1267_Y + end + attribute \src "ls180.v:5827.39-5827.92" + cell $and $and$ls180.v:5827$1268 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B \builder_interface3_bank_bus_we + connect \Y $and$ls180.v:5827$1268_Y + end + attribute \src "ls180.v:5827.38-5827.142" + cell $and $and$ls180.v:5827$1270 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5827$1268_Y + connect \B $eq$ls180.v:5827$1269_Y + connect \Y $and$ls180.v:5827$1270_Y + end + attribute \src "ls180.v:5828.39-5828.95" + cell $and $and$ls180.v:5828$1272 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B $not$ls180.v:5828$1271_Y + connect \Y $and$ls180.v:5828$1272_Y + end + attribute \src "ls180.v:5828.38-5828.145" + cell $and $and$ls180.v:5828$1274 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5828$1272_Y + connect \B $eq$ls180.v:5828$1273_Y + connect \Y $and$ls180.v:5828$1274_Y + end + attribute \src "ls180.v:5830.39-5830.92" + cell $and $and$ls180.v:5830$1275 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B \builder_interface3_bank_bus_we + connect \Y $and$ls180.v:5830$1275_Y + end + attribute \src "ls180.v:5830.38-5830.142" + cell $and $and$ls180.v:5830$1277 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5830$1275_Y + connect \B $eq$ls180.v:5830$1276_Y + connect \Y $and$ls180.v:5830$1277_Y + end + attribute \src "ls180.v:5831.39-5831.95" + cell $and $and$ls180.v:5831$1279 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B $not$ls180.v:5831$1278_Y + connect \Y $and$ls180.v:5831$1279_Y + end + attribute \src "ls180.v:5831.38-5831.145" + cell $and $and$ls180.v:5831$1281 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5831$1279_Y + connect \B $eq$ls180.v:5831$1280_Y + connect \Y $and$ls180.v:5831$1281_Y + end + attribute \src "ls180.v:5833.39-5833.92" + cell $and $and$ls180.v:5833$1282 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B \builder_interface3_bank_bus_we + connect \Y $and$ls180.v:5833$1282_Y + end + attribute \src "ls180.v:5833.38-5833.142" + cell $and $and$ls180.v:5833$1284 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5833$1282_Y + connect \B $eq$ls180.v:5833$1283_Y + connect \Y $and$ls180.v:5833$1284_Y + end + attribute \src "ls180.v:5834.39-5834.95" + cell $and $and$ls180.v:5834$1286 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B $not$ls180.v:5834$1285_Y + connect \Y $and$ls180.v:5834$1286_Y + end + attribute \src "ls180.v:5834.38-5834.145" + cell $and $and$ls180.v:5834$1288 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5834$1286_Y + connect \B $eq$ls180.v:5834$1287_Y + connect \Y $and$ls180.v:5834$1288_Y + end + attribute \src "ls180.v:5836.40-5836.93" + cell $and $and$ls180.v:5836$1289 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B \builder_interface3_bank_bus_we + connect \Y $and$ls180.v:5836$1289_Y + end + attribute \src "ls180.v:5836.39-5836.143" + cell $and $and$ls180.v:5836$1291 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5836$1289_Y + connect \B $eq$ls180.v:5836$1290_Y + connect \Y $and$ls180.v:5836$1291_Y + end + attribute \src "ls180.v:5837.40-5837.96" + cell $and $and$ls180.v:5837$1293 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B $not$ls180.v:5837$1292_Y + connect \Y $and$ls180.v:5837$1293_Y + end + attribute \src "ls180.v:5837.39-5837.146" + cell $and $and$ls180.v:5837$1295 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5837$1293_Y + connect \B $eq$ls180.v:5837$1294_Y + connect \Y $and$ls180.v:5837$1295_Y + end + attribute \src "ls180.v:5839.40-5839.93" + cell $and $and$ls180.v:5839$1296 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B \builder_interface3_bank_bus_we + connect \Y $and$ls180.v:5839$1296_Y + end + attribute \src "ls180.v:5839.39-5839.143" + cell $and $and$ls180.v:5839$1298 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5839$1296_Y + connect \B $eq$ls180.v:5839$1297_Y + connect \Y $and$ls180.v:5839$1298_Y + end + attribute \src "ls180.v:5840.40-5840.96" + cell $and $and$ls180.v:5840$1300 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B $not$ls180.v:5840$1299_Y + connect \Y $and$ls180.v:5840$1300_Y + end + attribute \src "ls180.v:5840.39-5840.146" + cell $and $and$ls180.v:5840$1302 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5840$1300_Y + connect \B $eq$ls180.v:5840$1301_Y + connect \Y $and$ls180.v:5840$1302_Y + end + attribute \src "ls180.v:5842.40-5842.93" + cell $and $and$ls180.v:5842$1303 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B \builder_interface3_bank_bus_we + connect \Y $and$ls180.v:5842$1303_Y + end + attribute \src "ls180.v:5842.39-5842.143" + cell $and $and$ls180.v:5842$1305 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5842$1303_Y + connect \B $eq$ls180.v:5842$1304_Y + connect \Y $and$ls180.v:5842$1305_Y + end + attribute \src "ls180.v:5843.40-5843.96" + cell $and $and$ls180.v:5843$1307 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B $not$ls180.v:5843$1306_Y + connect \Y $and$ls180.v:5843$1307_Y + end + attribute \src "ls180.v:5843.39-5843.146" + cell $and $and$ls180.v:5843$1309 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5843$1307_Y + connect \B $eq$ls180.v:5843$1308_Y + connect \Y $and$ls180.v:5843$1309_Y + end + attribute \src "ls180.v:5845.40-5845.93" + cell $and $and$ls180.v:5845$1310 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B \builder_interface3_bank_bus_we + connect \Y $and$ls180.v:5845$1310_Y + end + attribute \src "ls180.v:5845.39-5845.143" + cell $and $and$ls180.v:5845$1312 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5845$1310_Y + connect \B $eq$ls180.v:5845$1311_Y + connect \Y $and$ls180.v:5845$1312_Y + end + attribute \src "ls180.v:5846.40-5846.96" + cell $and $and$ls180.v:5846$1314 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B $not$ls180.v:5846$1313_Y + connect \Y $and$ls180.v:5846$1314_Y + end + attribute \src "ls180.v:5846.39-5846.146" + cell $and $and$ls180.v:5846$1316 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5846$1314_Y + connect \B $eq$ls180.v:5846$1315_Y + connect \Y $and$ls180.v:5846$1316_Y + end + attribute \src "ls180.v:5858.42-5858.95" + cell $and $and$ls180.v:5858$1318 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B \builder_interface4_bank_bus_we + connect \Y $and$ls180.v:5858$1318_Y + end + attribute \src "ls180.v:5858.41-5858.145" + cell $and $and$ls180.v:5858$1320 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5858$1318_Y + connect \B $eq$ls180.v:5858$1319_Y + connect \Y $and$ls180.v:5858$1320_Y + end + attribute \src "ls180.v:5859.42-5859.98" + cell $and $and$ls180.v:5859$1322 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B $not$ls180.v:5859$1321_Y + connect \Y $and$ls180.v:5859$1322_Y + end + attribute \src "ls180.v:5859.41-5859.148" + cell $and $and$ls180.v:5859$1324 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5859$1322_Y + connect \B $eq$ls180.v:5859$1323_Y + connect \Y $and$ls180.v:5859$1324_Y + end + attribute \src "ls180.v:5861.42-5861.95" + cell $and $and$ls180.v:5861$1325 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B \builder_interface4_bank_bus_we + connect \Y $and$ls180.v:5861$1325_Y + end + attribute \src "ls180.v:5861.41-5861.145" + cell $and $and$ls180.v:5861$1327 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5861$1325_Y + connect \B $eq$ls180.v:5861$1326_Y + connect \Y $and$ls180.v:5861$1327_Y + end + attribute \src "ls180.v:5862.42-5862.98" + cell $and $and$ls180.v:5862$1329 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B $not$ls180.v:5862$1328_Y + connect \Y $and$ls180.v:5862$1329_Y + end + attribute \src "ls180.v:5862.41-5862.148" + cell $and $and$ls180.v:5862$1331 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5862$1329_Y + connect \B $eq$ls180.v:5862$1330_Y + connect \Y $and$ls180.v:5862$1331_Y + end + attribute \src "ls180.v:5864.42-5864.95" + cell $and $and$ls180.v:5864$1332 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B \builder_interface4_bank_bus_we + connect \Y $and$ls180.v:5864$1332_Y + end + attribute \src "ls180.v:5864.41-5864.145" + cell $and $and$ls180.v:5864$1334 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5864$1332_Y + connect \B $eq$ls180.v:5864$1333_Y + connect \Y $and$ls180.v:5864$1334_Y + end + attribute \src "ls180.v:5865.42-5865.98" + cell $and $and$ls180.v:5865$1336 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B $not$ls180.v:5865$1335_Y + connect \Y $and$ls180.v:5865$1336_Y + end + attribute \src "ls180.v:5865.41-5865.148" + cell $and $and$ls180.v:5865$1338 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5865$1336_Y + connect \B $eq$ls180.v:5865$1337_Y + connect \Y $and$ls180.v:5865$1338_Y + end + attribute \src "ls180.v:5867.42-5867.95" + cell $and $and$ls180.v:5867$1339 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B \builder_interface4_bank_bus_we + connect \Y $and$ls180.v:5867$1339_Y + end + attribute \src "ls180.v:5867.41-5867.145" + cell $and $and$ls180.v:5867$1341 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5867$1339_Y + connect \B $eq$ls180.v:5867$1340_Y + connect \Y $and$ls180.v:5867$1341_Y + end + attribute \src "ls180.v:5868.42-5868.98" + cell $and $and$ls180.v:5868$1343 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B $not$ls180.v:5868$1342_Y + connect \Y $and$ls180.v:5868$1343_Y + end + attribute \src "ls180.v:5868.41-5868.148" + cell $and $and$ls180.v:5868$1345 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5868$1343_Y + connect \B $eq$ls180.v:5868$1344_Y + connect \Y $and$ls180.v:5868$1345_Y + end + attribute \src "ls180.v:5870.42-5870.95" + cell $and $and$ls180.v:5870$1346 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B \builder_interface4_bank_bus_we + connect \Y $and$ls180.v:5870$1346_Y + end + attribute \src "ls180.v:5870.41-5870.145" + cell $and $and$ls180.v:5870$1348 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5870$1346_Y + connect \B $eq$ls180.v:5870$1347_Y + connect \Y $and$ls180.v:5870$1348_Y + end + attribute \src "ls180.v:5871.42-5871.98" + cell $and $and$ls180.v:5871$1350 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B $not$ls180.v:5871$1349_Y + connect \Y $and$ls180.v:5871$1350_Y + end + attribute \src "ls180.v:5871.41-5871.148" + cell $and $and$ls180.v:5871$1352 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5871$1350_Y + connect \B $eq$ls180.v:5871$1351_Y + connect \Y $and$ls180.v:5871$1352_Y + end + attribute \src "ls180.v:5873.42-5873.95" + cell $and $and$ls180.v:5873$1353 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B \builder_interface4_bank_bus_we + connect \Y $and$ls180.v:5873$1353_Y + end + attribute \src "ls180.v:5873.41-5873.145" + cell $and $and$ls180.v:5873$1355 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5873$1353_Y + connect \B $eq$ls180.v:5873$1354_Y + connect \Y $and$ls180.v:5873$1355_Y + end + attribute \src "ls180.v:5874.42-5874.98" + cell $and $and$ls180.v:5874$1357 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B $not$ls180.v:5874$1356_Y + connect \Y $and$ls180.v:5874$1357_Y + end + attribute \src "ls180.v:5874.41-5874.148" + cell $and $and$ls180.v:5874$1359 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5874$1357_Y + connect \B $eq$ls180.v:5874$1358_Y + connect \Y $and$ls180.v:5874$1359_Y + end + attribute \src "ls180.v:5876.42-5876.95" + cell $and $and$ls180.v:5876$1360 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B \builder_interface4_bank_bus_we + connect \Y $and$ls180.v:5876$1360_Y + end + attribute \src "ls180.v:5876.41-5876.145" + cell $and $and$ls180.v:5876$1362 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5876$1360_Y + connect \B $eq$ls180.v:5876$1361_Y + connect \Y $and$ls180.v:5876$1362_Y + end + attribute \src "ls180.v:5877.42-5877.98" + cell $and $and$ls180.v:5877$1364 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B $not$ls180.v:5877$1363_Y + connect \Y $and$ls180.v:5877$1364_Y + end + attribute \src "ls180.v:5877.41-5877.148" + cell $and $and$ls180.v:5877$1366 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5877$1364_Y + connect \B $eq$ls180.v:5877$1365_Y + connect \Y $and$ls180.v:5877$1366_Y + end + attribute \src "ls180.v:5879.42-5879.95" + cell $and $and$ls180.v:5879$1367 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B \builder_interface4_bank_bus_we + connect \Y $and$ls180.v:5879$1367_Y + end + attribute \src "ls180.v:5879.41-5879.145" + cell $and $and$ls180.v:5879$1369 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5879$1367_Y + connect \B $eq$ls180.v:5879$1368_Y + connect \Y $and$ls180.v:5879$1369_Y + end + attribute \src "ls180.v:5880.42-5880.98" + cell $and $and$ls180.v:5880$1371 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B $not$ls180.v:5880$1370_Y + connect \Y $and$ls180.v:5880$1371_Y + end + attribute \src "ls180.v:5880.41-5880.148" + cell $and $and$ls180.v:5880$1373 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5880$1371_Y + connect \B $eq$ls180.v:5880$1372_Y + connect \Y $and$ls180.v:5880$1373_Y + end + attribute \src "ls180.v:5882.44-5882.97" + cell $and $and$ls180.v:5882$1374 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B \builder_interface4_bank_bus_we + connect \Y $and$ls180.v:5882$1374_Y + end + attribute \src "ls180.v:5882.43-5882.147" + cell $and $and$ls180.v:5882$1376 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5882$1374_Y + connect \B $eq$ls180.v:5882$1375_Y + connect \Y $and$ls180.v:5882$1376_Y + end + attribute \src "ls180.v:5883.44-5883.100" + cell $and $and$ls180.v:5883$1378 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B $not$ls180.v:5883$1377_Y + connect \Y $and$ls180.v:5883$1378_Y + end + attribute \src "ls180.v:5883.43-5883.150" + cell $and $and$ls180.v:5883$1380 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5883$1378_Y + connect \B $eq$ls180.v:5883$1379_Y + connect \Y $and$ls180.v:5883$1380_Y + end + attribute \src "ls180.v:5885.44-5885.97" + cell $and $and$ls180.v:5885$1381 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B \builder_interface4_bank_bus_we + connect \Y $and$ls180.v:5885$1381_Y + end + attribute \src "ls180.v:5885.43-5885.147" + cell $and $and$ls180.v:5885$1383 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5885$1381_Y + connect \B $eq$ls180.v:5885$1382_Y + connect \Y $and$ls180.v:5885$1383_Y + end + attribute \src "ls180.v:5886.44-5886.100" + cell $and $and$ls180.v:5886$1385 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B $not$ls180.v:5886$1384_Y + connect \Y $and$ls180.v:5886$1385_Y + end + attribute \src "ls180.v:5886.43-5886.150" + cell $and $and$ls180.v:5886$1387 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5886$1385_Y + connect \B $eq$ls180.v:5886$1386_Y + connect \Y $and$ls180.v:5886$1387_Y + end + attribute \src "ls180.v:5888.44-5888.97" + cell $and $and$ls180.v:5888$1388 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B \builder_interface4_bank_bus_we + connect \Y $and$ls180.v:5888$1388_Y + end + attribute \src "ls180.v:5888.43-5888.148" + cell $and $and$ls180.v:5888$1390 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5888$1388_Y + connect \B $eq$ls180.v:5888$1389_Y + connect \Y $and$ls180.v:5888$1390_Y + end + attribute \src "ls180.v:5889.44-5889.100" + cell $and $and$ls180.v:5889$1392 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B $not$ls180.v:5889$1391_Y + connect \Y $and$ls180.v:5889$1392_Y + end + attribute \src "ls180.v:5889.43-5889.151" + cell $and $and$ls180.v:5889$1394 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5889$1392_Y + connect \B $eq$ls180.v:5889$1393_Y + connect \Y $and$ls180.v:5889$1394_Y + end + attribute \src "ls180.v:5891.44-5891.97" + cell $and $and$ls180.v:5891$1395 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B \builder_interface4_bank_bus_we + connect \Y $and$ls180.v:5891$1395_Y + end + attribute \src "ls180.v:5891.43-5891.148" + cell $and $and$ls180.v:5891$1397 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5891$1395_Y + connect \B $eq$ls180.v:5891$1396_Y + connect \Y $and$ls180.v:5891$1397_Y + end + attribute \src "ls180.v:5892.44-5892.100" + cell $and $and$ls180.v:5892$1399 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B $not$ls180.v:5892$1398_Y + connect \Y $and$ls180.v:5892$1399_Y + end + attribute \src "ls180.v:5892.43-5892.151" + cell $and $and$ls180.v:5892$1401 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5892$1399_Y + connect \B $eq$ls180.v:5892$1400_Y + connect \Y $and$ls180.v:5892$1401_Y + end + attribute \src "ls180.v:5894.44-5894.97" + cell $and $and$ls180.v:5894$1402 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B \builder_interface4_bank_bus_we + connect \Y $and$ls180.v:5894$1402_Y + end + attribute \src "ls180.v:5894.43-5894.148" + cell $and $and$ls180.v:5894$1404 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5894$1402_Y + connect \B $eq$ls180.v:5894$1403_Y + connect \Y $and$ls180.v:5894$1404_Y + end + attribute \src "ls180.v:5895.44-5895.100" + cell $and $and$ls180.v:5895$1406 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B $not$ls180.v:5895$1405_Y + connect \Y $and$ls180.v:5895$1406_Y + end + attribute \src "ls180.v:5895.43-5895.151" + cell $and $and$ls180.v:5895$1408 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5895$1406_Y + connect \B $eq$ls180.v:5895$1407_Y + connect \Y $and$ls180.v:5895$1408_Y + end + attribute \src "ls180.v:5897.41-5897.94" + cell $and $and$ls180.v:5897$1409 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B \builder_interface4_bank_bus_we + connect \Y $and$ls180.v:5897$1409_Y + end + attribute \src "ls180.v:5897.40-5897.145" + cell $and $and$ls180.v:5897$1411 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5897$1409_Y + connect \B $eq$ls180.v:5897$1410_Y + connect \Y $and$ls180.v:5897$1411_Y + end + attribute \src "ls180.v:5898.41-5898.97" + cell $and $and$ls180.v:5898$1413 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B $not$ls180.v:5898$1412_Y + connect \Y $and$ls180.v:5898$1413_Y + end + attribute \src "ls180.v:5898.40-5898.148" + cell $and $and$ls180.v:5898$1415 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5898$1413_Y + connect \B $eq$ls180.v:5898$1414_Y + connect \Y $and$ls180.v:5898$1415_Y + end + attribute \src "ls180.v:5900.42-5900.95" + cell $and $and$ls180.v:5900$1416 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B \builder_interface4_bank_bus_we + connect \Y $and$ls180.v:5900$1416_Y + end + attribute \src "ls180.v:5900.41-5900.146" + cell $and $and$ls180.v:5900$1418 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5900$1416_Y + connect \B $eq$ls180.v:5900$1417_Y + connect \Y $and$ls180.v:5900$1418_Y + end + attribute \src "ls180.v:5901.42-5901.98" + cell $and $and$ls180.v:5901$1420 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B $not$ls180.v:5901$1419_Y + connect \Y $and$ls180.v:5901$1420_Y + end + attribute \src "ls180.v:5901.41-5901.149" + cell $and $and$ls180.v:5901$1422 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5901$1420_Y + connect \B $eq$ls180.v:5901$1421_Y + connect \Y $and$ls180.v:5901$1422_Y + end + attribute \src "ls180.v:5920.46-5920.99" + cell $and $and$ls180.v:5920$1424 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:5920$1424_Y + end + attribute \src "ls180.v:5920.45-5920.149" + cell $and $and$ls180.v:5920$1426 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5920$1424_Y + connect \B $eq$ls180.v:5920$1425_Y + connect \Y $and$ls180.v:5920$1426_Y + end + attribute \src "ls180.v:5921.46-5921.102" + cell $and $and$ls180.v:5921$1428 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:5921$1427_Y + connect \Y $and$ls180.v:5921$1428_Y + end + attribute \src "ls180.v:5921.45-5921.152" + cell $and $and$ls180.v:5921$1430 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5921$1428_Y + connect \B $eq$ls180.v:5921$1429_Y + connect \Y $and$ls180.v:5921$1430_Y + end + attribute \src "ls180.v:5923.46-5923.99" + cell $and $and$ls180.v:5923$1431 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:5923$1431_Y + end + attribute \src "ls180.v:5923.45-5923.149" + cell $and $and$ls180.v:5923$1433 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5923$1431_Y + connect \B $eq$ls180.v:5923$1432_Y + connect \Y $and$ls180.v:5923$1433_Y + end + attribute \src "ls180.v:5924.46-5924.102" + cell $and $and$ls180.v:5924$1435 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:5924$1434_Y + connect \Y $and$ls180.v:5924$1435_Y + end + attribute \src "ls180.v:5924.45-5924.152" + cell $and $and$ls180.v:5924$1437 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5924$1435_Y + connect \B $eq$ls180.v:5924$1436_Y + connect \Y $and$ls180.v:5924$1437_Y + end + attribute \src "ls180.v:5926.46-5926.99" + cell $and $and$ls180.v:5926$1438 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:5926$1438_Y + end + attribute \src "ls180.v:5926.45-5926.149" + cell $and $and$ls180.v:5926$1440 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5926$1438_Y + connect \B $eq$ls180.v:5926$1439_Y + connect \Y $and$ls180.v:5926$1440_Y + end + attribute \src "ls180.v:5927.46-5927.102" + cell $and $and$ls180.v:5927$1442 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:5927$1441_Y + connect \Y $and$ls180.v:5927$1442_Y + end + attribute \src "ls180.v:5927.45-5927.152" + cell $and $and$ls180.v:5927$1444 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5927$1442_Y + connect \B $eq$ls180.v:5927$1443_Y + connect \Y $and$ls180.v:5927$1444_Y + end + attribute \src "ls180.v:5929.46-5929.99" + cell $and $and$ls180.v:5929$1445 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:5929$1445_Y + end + attribute \src "ls180.v:5929.45-5929.149" + cell $and $and$ls180.v:5929$1447 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5929$1445_Y + connect \B $eq$ls180.v:5929$1446_Y + connect \Y $and$ls180.v:5929$1447_Y + end + attribute \src "ls180.v:5930.46-5930.102" + cell $and $and$ls180.v:5930$1449 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:5930$1448_Y + connect \Y $and$ls180.v:5930$1449_Y + end + attribute \src "ls180.v:5930.45-5930.152" + cell $and $and$ls180.v:5930$1451 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5930$1449_Y + connect \B $eq$ls180.v:5930$1450_Y + connect \Y $and$ls180.v:5930$1451_Y + end + attribute \src "ls180.v:5932.45-5932.98" + cell $and $and$ls180.v:5932$1452 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:5932$1452_Y + end + attribute \src "ls180.v:5932.44-5932.148" + cell $and $and$ls180.v:5932$1454 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5932$1452_Y + connect \B $eq$ls180.v:5932$1453_Y + connect \Y $and$ls180.v:5932$1454_Y + end + attribute \src "ls180.v:5933.45-5933.101" + cell $and $and$ls180.v:5933$1456 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:5933$1455_Y + connect \Y $and$ls180.v:5933$1456_Y + end + attribute \src "ls180.v:5933.44-5933.151" + cell $and $and$ls180.v:5933$1458 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5933$1456_Y + connect \B $eq$ls180.v:5933$1457_Y + connect \Y $and$ls180.v:5933$1458_Y + end + attribute \src "ls180.v:5935.45-5935.98" + cell $and $and$ls180.v:5935$1459 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:5935$1459_Y + end + attribute \src "ls180.v:5935.44-5935.148" + cell $and $and$ls180.v:5935$1461 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5935$1459_Y + connect \B $eq$ls180.v:5935$1460_Y + connect \Y $and$ls180.v:5935$1461_Y + end + attribute \src "ls180.v:5936.45-5936.101" + cell $and $and$ls180.v:5936$1463 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:5936$1462_Y + connect \Y $and$ls180.v:5936$1463_Y + end + attribute \src "ls180.v:5936.44-5936.151" + cell $and $and$ls180.v:5936$1465 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5936$1463_Y + connect \B $eq$ls180.v:5936$1464_Y + connect \Y $and$ls180.v:5936$1465_Y + end + attribute \src "ls180.v:5938.45-5938.98" + cell $and $and$ls180.v:5938$1466 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:5938$1466_Y + end + attribute \src "ls180.v:5938.44-5938.148" + cell $and $and$ls180.v:5938$1468 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5938$1466_Y + connect \B $eq$ls180.v:5938$1467_Y + connect \Y $and$ls180.v:5938$1468_Y + end + attribute \src "ls180.v:5939.45-5939.101" + cell $and $and$ls180.v:5939$1470 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:5939$1469_Y + connect \Y $and$ls180.v:5939$1470_Y + end + attribute \src "ls180.v:5939.44-5939.151" + cell $and $and$ls180.v:5939$1472 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5939$1470_Y + connect \B $eq$ls180.v:5939$1471_Y + connect \Y $and$ls180.v:5939$1472_Y + end + attribute \src "ls180.v:5941.45-5941.98" + cell $and $and$ls180.v:5941$1473 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:5941$1473_Y + end + attribute \src "ls180.v:5941.44-5941.148" + cell $and $and$ls180.v:5941$1475 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5941$1473_Y + connect \B $eq$ls180.v:5941$1474_Y + connect \Y $and$ls180.v:5941$1475_Y + end + attribute \src "ls180.v:5942.45-5942.101" + cell $and $and$ls180.v:5942$1477 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:5942$1476_Y + connect \Y $and$ls180.v:5942$1477_Y + end + attribute \src "ls180.v:5942.44-5942.151" + cell $and $and$ls180.v:5942$1479 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5942$1477_Y + connect \B $eq$ls180.v:5942$1478_Y + connect \Y $and$ls180.v:5942$1479_Y + end + attribute \src "ls180.v:5944.36-5944.89" + cell $and $and$ls180.v:5944$1480 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:5944$1480_Y + end + attribute \src "ls180.v:5944.35-5944.139" + cell $and $and$ls180.v:5944$1482 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5944$1480_Y + connect \B $eq$ls180.v:5944$1481_Y + connect \Y $and$ls180.v:5944$1482_Y + end + attribute \src "ls180.v:5945.36-5945.92" + cell $and $and$ls180.v:5945$1484 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:5945$1483_Y + connect \Y $and$ls180.v:5945$1484_Y + end + attribute \src "ls180.v:5945.35-5945.142" + cell $and $and$ls180.v:5945$1486 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5945$1484_Y + connect \B $eq$ls180.v:5945$1485_Y + connect \Y $and$ls180.v:5945$1486_Y + end + attribute \src "ls180.v:5947.47-5947.100" + cell $and $and$ls180.v:5947$1487 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:5947$1487_Y + end + attribute \src "ls180.v:5947.46-5947.150" + cell $and $and$ls180.v:5947$1489 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5947$1487_Y + connect \B $eq$ls180.v:5947$1488_Y + connect \Y $and$ls180.v:5947$1489_Y + end + attribute \src "ls180.v:5948.47-5948.103" + cell $and $and$ls180.v:5948$1491 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:5948$1490_Y + connect \Y $and$ls180.v:5948$1491_Y + end + attribute \src "ls180.v:5948.46-5948.153" + cell $and $and$ls180.v:5948$1493 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5948$1491_Y + connect \B $eq$ls180.v:5948$1492_Y + connect \Y $and$ls180.v:5948$1493_Y + end + attribute \src "ls180.v:5950.47-5950.100" + cell $and $and$ls180.v:5950$1494 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:5950$1494_Y + end + attribute \src "ls180.v:5950.46-5950.151" + cell $and $and$ls180.v:5950$1496 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5950$1494_Y + connect \B $eq$ls180.v:5950$1495_Y + connect \Y $and$ls180.v:5950$1496_Y + end + attribute \src "ls180.v:5951.47-5951.103" + cell $and $and$ls180.v:5951$1498 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:5951$1497_Y + connect \Y $and$ls180.v:5951$1498_Y + end + attribute \src "ls180.v:5951.46-5951.154" + cell $and $and$ls180.v:5951$1500 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5951$1498_Y + connect \B $eq$ls180.v:5951$1499_Y + connect \Y $and$ls180.v:5951$1500_Y + end + attribute \src "ls180.v:5953.47-5953.100" + cell $and $and$ls180.v:5953$1501 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:5953$1501_Y + end + attribute \src "ls180.v:5953.46-5953.151" + cell $and $and$ls180.v:5953$1503 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5953$1501_Y + connect \B $eq$ls180.v:5953$1502_Y + connect \Y $and$ls180.v:5953$1503_Y + end + attribute \src "ls180.v:5954.47-5954.103" + cell $and $and$ls180.v:5954$1505 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:5954$1504_Y + connect \Y $and$ls180.v:5954$1505_Y + end + attribute \src "ls180.v:5954.46-5954.154" + cell $and $and$ls180.v:5954$1507 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5954$1505_Y + connect \B $eq$ls180.v:5954$1506_Y + connect \Y $and$ls180.v:5954$1507_Y + end + attribute \src "ls180.v:5956.47-5956.100" + cell $and $and$ls180.v:5956$1508 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:5956$1508_Y + end + attribute \src "ls180.v:5956.46-5956.151" + cell $and $and$ls180.v:5956$1510 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5956$1508_Y + connect \B $eq$ls180.v:5956$1509_Y + connect \Y $and$ls180.v:5956$1510_Y + end + attribute \src "ls180.v:5957.47-5957.103" + cell $and $and$ls180.v:5957$1512 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:5957$1511_Y + connect \Y $and$ls180.v:5957$1512_Y + end + attribute \src "ls180.v:5957.46-5957.154" + cell $and $and$ls180.v:5957$1514 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5957$1512_Y + connect \B $eq$ls180.v:5957$1513_Y + connect \Y $and$ls180.v:5957$1514_Y + end + attribute \src "ls180.v:5959.47-5959.100" + cell $and $and$ls180.v:5959$1515 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:5959$1515_Y + end + attribute \src "ls180.v:5959.46-5959.151" + cell $and $and$ls180.v:5959$1517 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5959$1515_Y + connect \B $eq$ls180.v:5959$1516_Y + connect \Y $and$ls180.v:5959$1517_Y + end + attribute \src "ls180.v:5960.47-5960.103" + cell $and $and$ls180.v:5960$1519 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:5960$1518_Y + connect \Y $and$ls180.v:5960$1519_Y + end + attribute \src "ls180.v:5960.46-5960.154" + cell $and $and$ls180.v:5960$1521 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5960$1519_Y + connect \B $eq$ls180.v:5960$1520_Y + connect \Y $and$ls180.v:5960$1521_Y + end + attribute \src "ls180.v:5962.47-5962.100" + cell $and $and$ls180.v:5962$1522 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:5962$1522_Y + end + attribute \src "ls180.v:5962.46-5962.151" + cell $and $and$ls180.v:5962$1524 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5962$1522_Y + connect \B $eq$ls180.v:5962$1523_Y + connect \Y $and$ls180.v:5962$1524_Y + end + attribute \src "ls180.v:5963.47-5963.103" + cell $and $and$ls180.v:5963$1526 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:5963$1525_Y + connect \Y $and$ls180.v:5963$1526_Y + end + attribute \src "ls180.v:5963.46-5963.154" + cell $and $and$ls180.v:5963$1528 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5963$1526_Y + connect \B $eq$ls180.v:5963$1527_Y + connect \Y $and$ls180.v:5963$1528_Y + end + attribute \src "ls180.v:5965.46-5965.99" + cell $and $and$ls180.v:5965$1529 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:5965$1529_Y + end + attribute \src "ls180.v:5965.45-5965.150" + cell $and $and$ls180.v:5965$1531 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5965$1529_Y + connect \B $eq$ls180.v:5965$1530_Y + connect \Y $and$ls180.v:5965$1531_Y + end + attribute \src "ls180.v:5966.46-5966.102" + cell $and $and$ls180.v:5966$1533 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:5966$1532_Y + connect \Y $and$ls180.v:5966$1533_Y + end + attribute \src "ls180.v:5966.45-5966.153" + cell $and $and$ls180.v:5966$1535 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5966$1533_Y + connect \B $eq$ls180.v:5966$1534_Y + connect \Y $and$ls180.v:5966$1535_Y + end + attribute \src "ls180.v:5968.46-5968.99" + cell $and $and$ls180.v:5968$1536 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:5968$1536_Y + end + attribute \src "ls180.v:5968.45-5968.150" + cell $and $and$ls180.v:5968$1538 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5968$1536_Y + connect \B $eq$ls180.v:5968$1537_Y + connect \Y $and$ls180.v:5968$1538_Y + end + attribute \src "ls180.v:5969.46-5969.102" + cell $and $and$ls180.v:5969$1540 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:5969$1539_Y + connect \Y $and$ls180.v:5969$1540_Y + end + attribute \src "ls180.v:5969.45-5969.153" + cell $and $and$ls180.v:5969$1542 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5969$1540_Y + connect \B $eq$ls180.v:5969$1541_Y + connect \Y $and$ls180.v:5969$1542_Y + end + attribute \src "ls180.v:5971.46-5971.99" + cell $and $and$ls180.v:5971$1543 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:5971$1543_Y + end + attribute \src "ls180.v:5971.45-5971.150" + cell $and $and$ls180.v:5971$1545 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5971$1543_Y + connect \B $eq$ls180.v:5971$1544_Y + connect \Y $and$ls180.v:5971$1545_Y + end + attribute \src "ls180.v:5972.46-5972.102" + cell $and $and$ls180.v:5972$1547 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:5972$1546_Y + connect \Y $and$ls180.v:5972$1547_Y + end + attribute \src "ls180.v:5972.45-5972.153" + cell $and $and$ls180.v:5972$1549 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5972$1547_Y + connect \B $eq$ls180.v:5972$1548_Y + connect \Y $and$ls180.v:5972$1549_Y + end + attribute \src "ls180.v:5974.46-5974.99" + cell $and $and$ls180.v:5974$1550 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:5974$1550_Y + end + attribute \src "ls180.v:5974.45-5974.150" + cell $and $and$ls180.v:5974$1552 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5974$1550_Y + connect \B $eq$ls180.v:5974$1551_Y + connect \Y $and$ls180.v:5974$1552_Y + end + attribute \src "ls180.v:5975.46-5975.102" + cell $and $and$ls180.v:5975$1554 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:5975$1553_Y + connect \Y $and$ls180.v:5975$1554_Y + end + attribute \src "ls180.v:5975.45-5975.153" + cell $and $and$ls180.v:5975$1556 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5975$1554_Y + connect \B $eq$ls180.v:5975$1555_Y + connect \Y $and$ls180.v:5975$1556_Y + end + attribute \src "ls180.v:5977.46-5977.99" + cell $and $and$ls180.v:5977$1557 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:5977$1557_Y + end + attribute \src "ls180.v:5977.45-5977.150" + cell $and $and$ls180.v:5977$1559 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5977$1557_Y + connect \B $eq$ls180.v:5977$1558_Y + connect \Y $and$ls180.v:5977$1559_Y + end + attribute \src "ls180.v:5978.46-5978.102" + cell $and $and$ls180.v:5978$1561 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:5978$1560_Y + connect \Y $and$ls180.v:5978$1561_Y + end + attribute \src "ls180.v:5978.45-5978.153" + cell $and $and$ls180.v:5978$1563 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5978$1561_Y + connect \B $eq$ls180.v:5978$1562_Y + connect \Y $and$ls180.v:5978$1563_Y + end + attribute \src "ls180.v:5980.46-5980.99" + cell $and $and$ls180.v:5980$1564 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:5980$1564_Y + end + attribute \src "ls180.v:5980.45-5980.150" + cell $and $and$ls180.v:5980$1566 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5980$1564_Y + connect \B $eq$ls180.v:5980$1565_Y + connect \Y $and$ls180.v:5980$1566_Y + end + attribute \src "ls180.v:5981.46-5981.102" + cell $and $and$ls180.v:5981$1568 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:5981$1567_Y + connect \Y $and$ls180.v:5981$1568_Y + end + attribute \src "ls180.v:5981.45-5981.153" + cell $and $and$ls180.v:5981$1570 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5981$1568_Y + connect \B $eq$ls180.v:5981$1569_Y + connect \Y $and$ls180.v:5981$1570_Y + end + attribute \src "ls180.v:5983.46-5983.99" + cell $and $and$ls180.v:5983$1571 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:5983$1571_Y + end + attribute \src "ls180.v:5983.45-5983.150" + cell $and $and$ls180.v:5983$1573 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5983$1571_Y + connect \B $eq$ls180.v:5983$1572_Y + connect \Y $and$ls180.v:5983$1573_Y + end + attribute \src "ls180.v:5984.46-5984.102" + cell $and $and$ls180.v:5984$1575 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:5984$1574_Y + connect \Y $and$ls180.v:5984$1575_Y + end + attribute \src "ls180.v:5984.45-5984.153" + cell $and $and$ls180.v:5984$1577 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5984$1575_Y + connect \B $eq$ls180.v:5984$1576_Y + connect \Y $and$ls180.v:5984$1577_Y + end + attribute \src "ls180.v:5986.46-5986.99" + cell $and $and$ls180.v:5986$1578 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:5986$1578_Y + end + attribute \src "ls180.v:5986.45-5986.150" + cell $and $and$ls180.v:5986$1580 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5986$1578_Y + connect \B $eq$ls180.v:5986$1579_Y + connect \Y $and$ls180.v:5986$1580_Y + end + attribute \src "ls180.v:5987.46-5987.102" + cell $and $and$ls180.v:5987$1582 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:5987$1581_Y + connect \Y $and$ls180.v:5987$1582_Y + end + attribute \src "ls180.v:5987.45-5987.153" + cell $and $and$ls180.v:5987$1584 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5987$1582_Y + connect \B $eq$ls180.v:5987$1583_Y + connect \Y $and$ls180.v:5987$1584_Y + end + attribute \src "ls180.v:5989.46-5989.99" + cell $and $and$ls180.v:5989$1585 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:5989$1585_Y + end + attribute \src "ls180.v:5989.45-5989.150" + cell $and $and$ls180.v:5989$1587 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5989$1585_Y + connect \B $eq$ls180.v:5989$1586_Y + connect \Y $and$ls180.v:5989$1587_Y + end + attribute \src "ls180.v:5990.46-5990.102" + cell $and $and$ls180.v:5990$1589 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:5990$1588_Y + connect \Y $and$ls180.v:5990$1589_Y + end + attribute \src "ls180.v:5990.45-5990.153" + cell $and $and$ls180.v:5990$1591 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5990$1589_Y + connect \B $eq$ls180.v:5990$1590_Y + connect \Y $and$ls180.v:5990$1591_Y + end + attribute \src "ls180.v:5992.46-5992.99" + cell $and $and$ls180.v:5992$1592 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:5992$1592_Y + end + attribute \src "ls180.v:5992.45-5992.150" + cell $and $and$ls180.v:5992$1594 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5992$1592_Y + connect \B $eq$ls180.v:5992$1593_Y + connect \Y $and$ls180.v:5992$1594_Y + end + attribute \src "ls180.v:5993.46-5993.102" + cell $and $and$ls180.v:5993$1596 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:5993$1595_Y + connect \Y $and$ls180.v:5993$1596_Y + end + attribute \src "ls180.v:5993.45-5993.153" + cell $and $and$ls180.v:5993$1598 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5993$1596_Y + connect \B $eq$ls180.v:5993$1597_Y + connect \Y $and$ls180.v:5993$1598_Y + end + attribute \src "ls180.v:5995.42-5995.95" + cell $and $and$ls180.v:5995$1599 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:5995$1599_Y + end + attribute \src "ls180.v:5995.41-5995.146" + cell $and $and$ls180.v:5995$1601 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5995$1599_Y + connect \B $eq$ls180.v:5995$1600_Y + connect \Y $and$ls180.v:5995$1601_Y + end + attribute \src "ls180.v:5996.42-5996.98" + cell $and $and$ls180.v:5996$1603 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:5996$1602_Y + connect \Y $and$ls180.v:5996$1603_Y + end + attribute \src "ls180.v:5996.41-5996.149" + cell $and $and$ls180.v:5996$1605 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5996$1603_Y + connect \B $eq$ls180.v:5996$1604_Y + connect \Y $and$ls180.v:5996$1605_Y + end + attribute \src "ls180.v:5998.43-5998.96" + cell $and $and$ls180.v:5998$1606 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:5998$1606_Y + end + attribute \src "ls180.v:5998.42-5998.147" + cell $and $and$ls180.v:5998$1608 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5998$1606_Y + connect \B $eq$ls180.v:5998$1607_Y + connect \Y $and$ls180.v:5998$1608_Y + end + attribute \src "ls180.v:5999.43-5999.99" + cell $and $and$ls180.v:5999$1610 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:5999$1609_Y + connect \Y $and$ls180.v:5999$1610_Y + end + attribute \src "ls180.v:5999.42-5999.150" + cell $and $and$ls180.v:5999$1612 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5999$1610_Y + connect \B $eq$ls180.v:5999$1611_Y + connect \Y $and$ls180.v:5999$1612_Y + end + attribute \src "ls180.v:6001.46-6001.99" + cell $and $and$ls180.v:6001$1613 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:6001$1613_Y + end + attribute \src "ls180.v:6001.45-6001.150" + cell $and $and$ls180.v:6001$1615 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6001$1613_Y + connect \B $eq$ls180.v:6001$1614_Y + connect \Y $and$ls180.v:6001$1615_Y + end + attribute \src "ls180.v:6002.46-6002.102" + cell $and $and$ls180.v:6002$1617 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:6002$1616_Y + connect \Y $and$ls180.v:6002$1617_Y + end + attribute \src "ls180.v:6002.45-6002.153" + cell $and $and$ls180.v:6002$1619 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6002$1617_Y + connect \B $eq$ls180.v:6002$1618_Y + connect \Y $and$ls180.v:6002$1619_Y + end + attribute \src "ls180.v:6004.46-6004.99" + cell $and $and$ls180.v:6004$1620 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:6004$1620_Y + end + attribute \src "ls180.v:6004.45-6004.150" + cell $and $and$ls180.v:6004$1622 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6004$1620_Y + connect \B $eq$ls180.v:6004$1621_Y + connect \Y $and$ls180.v:6004$1622_Y + end + attribute \src "ls180.v:6005.46-6005.102" + cell $and $and$ls180.v:6005$1624 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:6005$1623_Y + connect \Y $and$ls180.v:6005$1624_Y + end + attribute \src "ls180.v:6005.45-6005.153" + cell $and $and$ls180.v:6005$1626 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6005$1624_Y + connect \B $eq$ls180.v:6005$1625_Y + connect \Y $and$ls180.v:6005$1626_Y + end + attribute \src "ls180.v:6007.45-6007.98" + cell $and $and$ls180.v:6007$1627 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:6007$1627_Y + end + attribute \src "ls180.v:6007.44-6007.149" + cell $and $and$ls180.v:6007$1629 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6007$1627_Y + connect \B $eq$ls180.v:6007$1628_Y + connect \Y $and$ls180.v:6007$1629_Y + end + attribute \src "ls180.v:6008.45-6008.101" + cell $and $and$ls180.v:6008$1631 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:6008$1630_Y + connect \Y $and$ls180.v:6008$1631_Y + end + attribute \src "ls180.v:6008.44-6008.152" + cell $and $and$ls180.v:6008$1633 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6008$1631_Y + connect \B $eq$ls180.v:6008$1632_Y + connect \Y $and$ls180.v:6008$1633_Y + end + attribute \src "ls180.v:6010.45-6010.98" + cell $and $and$ls180.v:6010$1634 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:6010$1634_Y + end + attribute \src "ls180.v:6010.44-6010.149" + cell $and $and$ls180.v:6010$1636 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6010$1634_Y + connect \B $eq$ls180.v:6010$1635_Y + connect \Y $and$ls180.v:6010$1636_Y + end + attribute \src "ls180.v:6011.45-6011.101" + cell $and $and$ls180.v:6011$1638 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:6011$1637_Y + connect \Y $and$ls180.v:6011$1638_Y + end + attribute \src "ls180.v:6011.44-6011.152" + cell $and $and$ls180.v:6011$1640 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6011$1638_Y + connect \B $eq$ls180.v:6011$1639_Y + connect \Y $and$ls180.v:6011$1640_Y + end + attribute \src "ls180.v:6013.45-6013.98" + cell $and $and$ls180.v:6013$1641 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:6013$1641_Y + end + attribute \src "ls180.v:6013.44-6013.149" + cell $and $and$ls180.v:6013$1643 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6013$1641_Y + connect \B $eq$ls180.v:6013$1642_Y + connect \Y $and$ls180.v:6013$1643_Y + end + attribute \src "ls180.v:6014.45-6014.101" + cell $and $and$ls180.v:6014$1645 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:6014$1644_Y + connect \Y $and$ls180.v:6014$1645_Y + end + attribute \src "ls180.v:6014.44-6014.152" + cell $and $and$ls180.v:6014$1647 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6014$1645_Y + connect \B $eq$ls180.v:6014$1646_Y + connect \Y $and$ls180.v:6014$1647_Y + end + attribute \src "ls180.v:6016.45-6016.98" + cell $and $and$ls180.v:6016$1648 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:6016$1648_Y + end + attribute \src "ls180.v:6016.44-6016.149" + cell $and $and$ls180.v:6016$1650 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6016$1648_Y + connect \B $eq$ls180.v:6016$1649_Y + connect \Y $and$ls180.v:6016$1650_Y + end + attribute \src "ls180.v:6017.45-6017.101" + cell $and $and$ls180.v:6017$1652 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:6017$1651_Y + connect \Y $and$ls180.v:6017$1652_Y + end + attribute \src "ls180.v:6017.44-6017.152" + cell $and $and$ls180.v:6017$1654 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6017$1652_Y + connect \B $eq$ls180.v:6017$1653_Y + connect \Y $and$ls180.v:6017$1654_Y + end + attribute \src "ls180.v:6055.42-6055.95" + cell $and $and$ls180.v:6055$1656 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6055$1656_Y + end + attribute \src "ls180.v:6055.41-6055.145" + cell $and $and$ls180.v:6055$1658 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6055$1656_Y + connect \B $eq$ls180.v:6055$1657_Y + connect \Y $and$ls180.v:6055$1658_Y + end + attribute \src "ls180.v:6056.42-6056.98" + cell $and $and$ls180.v:6056$1660 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6056$1659_Y + connect \Y $and$ls180.v:6056$1660_Y + end + attribute \src "ls180.v:6056.41-6056.148" + cell $and $and$ls180.v:6056$1662 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6056$1660_Y + connect \B $eq$ls180.v:6056$1661_Y + connect \Y $and$ls180.v:6056$1662_Y + end + attribute \src "ls180.v:6058.42-6058.95" + cell $and $and$ls180.v:6058$1663 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6058$1663_Y + end + attribute \src "ls180.v:6058.41-6058.145" + cell $and $and$ls180.v:6058$1665 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6058$1663_Y + connect \B $eq$ls180.v:6058$1664_Y + connect \Y $and$ls180.v:6058$1665_Y + end + attribute \src "ls180.v:6059.42-6059.98" + cell $and $and$ls180.v:6059$1667 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6059$1666_Y + connect \Y $and$ls180.v:6059$1667_Y + end + attribute \src "ls180.v:6059.41-6059.148" + cell $and $and$ls180.v:6059$1669 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6059$1667_Y + connect \B $eq$ls180.v:6059$1668_Y + connect \Y $and$ls180.v:6059$1669_Y + end + attribute \src "ls180.v:6061.42-6061.95" + cell $and $and$ls180.v:6061$1670 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6061$1670_Y + end + attribute \src "ls180.v:6061.41-6061.145" + cell $and $and$ls180.v:6061$1672 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6061$1670_Y + connect \B $eq$ls180.v:6061$1671_Y + connect \Y $and$ls180.v:6061$1672_Y + end + attribute \src "ls180.v:6062.42-6062.98" + cell $and $and$ls180.v:6062$1674 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6062$1673_Y + connect \Y $and$ls180.v:6062$1674_Y + end + attribute \src "ls180.v:6062.41-6062.148" + cell $and $and$ls180.v:6062$1676 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6062$1674_Y + connect \B $eq$ls180.v:6062$1675_Y + connect \Y $and$ls180.v:6062$1676_Y + end + attribute \src "ls180.v:6064.42-6064.95" + cell $and $and$ls180.v:6064$1677 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6064$1677_Y + end + attribute \src "ls180.v:6064.41-6064.145" + cell $and $and$ls180.v:6064$1679 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6064$1677_Y + connect \B $eq$ls180.v:6064$1678_Y + connect \Y $and$ls180.v:6064$1679_Y + end + attribute \src "ls180.v:6065.42-6065.98" + cell $and $and$ls180.v:6065$1681 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6065$1680_Y + connect \Y $and$ls180.v:6065$1681_Y + end + attribute \src "ls180.v:6065.41-6065.148" + cell $and $and$ls180.v:6065$1683 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6065$1681_Y + connect \B $eq$ls180.v:6065$1682_Y + connect \Y $and$ls180.v:6065$1683_Y + end + attribute \src "ls180.v:6067.42-6067.95" + cell $and $and$ls180.v:6067$1684 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6067$1684_Y + end + attribute \src "ls180.v:6067.41-6067.145" + cell $and $and$ls180.v:6067$1686 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6067$1684_Y + connect \B $eq$ls180.v:6067$1685_Y + connect \Y $and$ls180.v:6067$1686_Y + end + attribute \src "ls180.v:6068.42-6068.98" + cell $and $and$ls180.v:6068$1688 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6068$1687_Y + connect \Y $and$ls180.v:6068$1688_Y + end + attribute \src "ls180.v:6068.41-6068.148" + cell $and $and$ls180.v:6068$1690 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6068$1688_Y + connect \B $eq$ls180.v:6068$1689_Y + connect \Y $and$ls180.v:6068$1690_Y + end + attribute \src "ls180.v:6070.42-6070.95" + cell $and $and$ls180.v:6070$1691 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6070$1691_Y + end + attribute \src "ls180.v:6070.41-6070.145" + cell $and $and$ls180.v:6070$1693 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6070$1691_Y + connect \B $eq$ls180.v:6070$1692_Y + connect \Y $and$ls180.v:6070$1693_Y + end + attribute \src "ls180.v:6071.42-6071.98" + cell $and $and$ls180.v:6071$1695 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6071$1694_Y + connect \Y $and$ls180.v:6071$1695_Y + end + attribute \src "ls180.v:6071.41-6071.148" + cell $and $and$ls180.v:6071$1697 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6071$1695_Y + connect \B $eq$ls180.v:6071$1696_Y + connect \Y $and$ls180.v:6071$1697_Y + end + attribute \src "ls180.v:6073.42-6073.95" + cell $and $and$ls180.v:6073$1698 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6073$1698_Y + end + attribute \src "ls180.v:6073.41-6073.145" + cell $and $and$ls180.v:6073$1700 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6073$1698_Y + connect \B $eq$ls180.v:6073$1699_Y + connect \Y $and$ls180.v:6073$1700_Y + end + attribute \src "ls180.v:6074.42-6074.98" + cell $and $and$ls180.v:6074$1702 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6074$1701_Y + connect \Y $and$ls180.v:6074$1702_Y + end + attribute \src "ls180.v:6074.41-6074.148" + cell $and $and$ls180.v:6074$1704 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6074$1702_Y + connect \B $eq$ls180.v:6074$1703_Y + connect \Y $and$ls180.v:6074$1704_Y + end + attribute \src "ls180.v:6076.42-6076.95" + cell $and $and$ls180.v:6076$1705 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6076$1705_Y + end + attribute \src "ls180.v:6076.41-6076.145" + cell $and $and$ls180.v:6076$1707 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6076$1705_Y + connect \B $eq$ls180.v:6076$1706_Y + connect \Y $and$ls180.v:6076$1707_Y + end + attribute \src "ls180.v:6077.42-6077.98" + cell $and $and$ls180.v:6077$1709 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6077$1708_Y + connect \Y $and$ls180.v:6077$1709_Y + end + attribute \src "ls180.v:6077.41-6077.148" + cell $and $and$ls180.v:6077$1711 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6077$1709_Y + connect \B $eq$ls180.v:6077$1710_Y + connect \Y $and$ls180.v:6077$1711_Y + end + attribute \src "ls180.v:6079.44-6079.97" + cell $and $and$ls180.v:6079$1712 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6079$1712_Y + end + attribute \src "ls180.v:6079.43-6079.147" + cell $and $and$ls180.v:6079$1714 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6079$1712_Y + connect \B $eq$ls180.v:6079$1713_Y + connect \Y $and$ls180.v:6079$1714_Y + end + attribute \src "ls180.v:6080.44-6080.100" + cell $and $and$ls180.v:6080$1716 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6080$1715_Y + connect \Y $and$ls180.v:6080$1716_Y + end + attribute \src "ls180.v:6080.43-6080.150" + cell $and $and$ls180.v:6080$1718 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6080$1716_Y + connect \B $eq$ls180.v:6080$1717_Y + connect \Y $and$ls180.v:6080$1718_Y + end + attribute \src "ls180.v:6082.44-6082.97" + cell $and $and$ls180.v:6082$1719 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6082$1719_Y + end + attribute \src "ls180.v:6082.43-6082.147" + cell $and $and$ls180.v:6082$1721 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6082$1719_Y + connect \B $eq$ls180.v:6082$1720_Y + connect \Y $and$ls180.v:6082$1721_Y + end + attribute \src "ls180.v:6083.44-6083.100" + cell $and $and$ls180.v:6083$1723 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6083$1722_Y + connect \Y $and$ls180.v:6083$1723_Y + end + attribute \src "ls180.v:6083.43-6083.150" + cell $and $and$ls180.v:6083$1725 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6083$1723_Y + connect \B $eq$ls180.v:6083$1724_Y + connect \Y $and$ls180.v:6083$1725_Y + end + attribute \src "ls180.v:6085.44-6085.97" + cell $and $and$ls180.v:6085$1726 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6085$1726_Y + end + attribute \src "ls180.v:6085.43-6085.148" + cell $and $and$ls180.v:6085$1728 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6085$1726_Y + connect \B $eq$ls180.v:6085$1727_Y + connect \Y $and$ls180.v:6085$1728_Y + end + attribute \src "ls180.v:6086.44-6086.100" + cell $and $and$ls180.v:6086$1730 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6086$1729_Y + connect \Y $and$ls180.v:6086$1730_Y + end + attribute \src "ls180.v:6086.43-6086.151" + cell $and $and$ls180.v:6086$1732 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6086$1730_Y + connect \B $eq$ls180.v:6086$1731_Y + connect \Y $and$ls180.v:6086$1732_Y + end + attribute \src "ls180.v:6088.44-6088.97" + cell $and $and$ls180.v:6088$1733 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6088$1733_Y + end + attribute \src "ls180.v:6088.43-6088.148" + cell $and $and$ls180.v:6088$1735 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6088$1733_Y + connect \B $eq$ls180.v:6088$1734_Y + connect \Y $and$ls180.v:6088$1735_Y + end + attribute \src "ls180.v:6089.44-6089.100" + cell $and $and$ls180.v:6089$1737 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6089$1736_Y + connect \Y $and$ls180.v:6089$1737_Y + end + attribute \src "ls180.v:6089.43-6089.151" + cell $and $and$ls180.v:6089$1739 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6089$1737_Y + connect \B $eq$ls180.v:6089$1738_Y + connect \Y $and$ls180.v:6089$1739_Y + end + attribute \src "ls180.v:6091.44-6091.97" + cell $and $and$ls180.v:6091$1740 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6091$1740_Y + end + attribute \src "ls180.v:6091.43-6091.148" + cell $and $and$ls180.v:6091$1742 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6091$1740_Y + connect \B $eq$ls180.v:6091$1741_Y + connect \Y $and$ls180.v:6091$1742_Y + end + attribute \src "ls180.v:6092.44-6092.100" + cell $and $and$ls180.v:6092$1744 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6092$1743_Y + connect \Y $and$ls180.v:6092$1744_Y + end + attribute \src "ls180.v:6092.43-6092.151" + cell $and $and$ls180.v:6092$1746 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6092$1744_Y + connect \B $eq$ls180.v:6092$1745_Y + connect \Y $and$ls180.v:6092$1746_Y + end + attribute \src "ls180.v:6094.41-6094.94" + cell $and $and$ls180.v:6094$1747 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6094$1747_Y + end + attribute \src "ls180.v:6094.40-6094.145" + cell $and $and$ls180.v:6094$1749 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6094$1747_Y + connect \B $eq$ls180.v:6094$1748_Y + connect \Y $and$ls180.v:6094$1749_Y + end + attribute \src "ls180.v:6095.41-6095.97" + cell $and $and$ls180.v:6095$1751 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6095$1750_Y + connect \Y $and$ls180.v:6095$1751_Y + end + attribute \src "ls180.v:6095.40-6095.148" + cell $and $and$ls180.v:6095$1753 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6095$1751_Y + connect \B $eq$ls180.v:6095$1752_Y + connect \Y $and$ls180.v:6095$1753_Y + end + attribute \src "ls180.v:6097.42-6097.95" + cell $and $and$ls180.v:6097$1754 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6097$1754_Y + end + attribute \src "ls180.v:6097.41-6097.146" + cell $and $and$ls180.v:6097$1756 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6097$1754_Y + connect \B $eq$ls180.v:6097$1755_Y + connect \Y $and$ls180.v:6097$1756_Y + end + attribute \src "ls180.v:6098.42-6098.98" + cell $and $and$ls180.v:6098$1758 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6098$1757_Y + connect \Y $and$ls180.v:6098$1758_Y + end + attribute \src "ls180.v:6098.41-6098.149" + cell $and $and$ls180.v:6098$1760 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6098$1758_Y + connect \B $eq$ls180.v:6098$1759_Y + connect \Y $and$ls180.v:6098$1760_Y + end + attribute \src "ls180.v:6100.44-6100.97" + cell $and $and$ls180.v:6100$1761 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6100$1761_Y + end + attribute \src "ls180.v:6100.43-6100.148" + cell $and $and$ls180.v:6100$1763 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6100$1761_Y + connect \B $eq$ls180.v:6100$1762_Y + connect \Y $and$ls180.v:6100$1763_Y + end + attribute \src "ls180.v:6101.44-6101.100" + cell $and $and$ls180.v:6101$1765 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6101$1764_Y + connect \Y $and$ls180.v:6101$1765_Y + end + attribute \src "ls180.v:6101.43-6101.151" + cell $and $and$ls180.v:6101$1767 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6101$1765_Y + connect \B $eq$ls180.v:6101$1766_Y + connect \Y $and$ls180.v:6101$1767_Y + end + attribute \src "ls180.v:6103.44-6103.97" + cell $and $and$ls180.v:6103$1768 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6103$1768_Y + end + attribute \src "ls180.v:6103.43-6103.148" + cell $and $and$ls180.v:6103$1770 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6103$1768_Y + connect \B $eq$ls180.v:6103$1769_Y + connect \Y $and$ls180.v:6103$1770_Y + end + attribute \src "ls180.v:6104.44-6104.100" + cell $and $and$ls180.v:6104$1772 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6104$1771_Y + connect \Y $and$ls180.v:6104$1772_Y + end + attribute \src "ls180.v:6104.43-6104.151" + cell $and $and$ls180.v:6104$1774 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6104$1772_Y + connect \B $eq$ls180.v:6104$1773_Y + connect \Y $and$ls180.v:6104$1774_Y + end + attribute \src "ls180.v:6106.44-6106.97" + cell $and $and$ls180.v:6106$1775 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6106$1775_Y + end + attribute \src "ls180.v:6106.43-6106.148" + cell $and $and$ls180.v:6106$1777 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6106$1775_Y + connect \B $eq$ls180.v:6106$1776_Y + connect \Y $and$ls180.v:6106$1777_Y + end + attribute \src "ls180.v:6107.44-6107.100" + cell $and $and$ls180.v:6107$1779 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6107$1778_Y + connect \Y $and$ls180.v:6107$1779_Y + end + attribute \src "ls180.v:6107.43-6107.151" + cell $and $and$ls180.v:6107$1781 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6107$1779_Y + connect \B $eq$ls180.v:6107$1780_Y + connect \Y $and$ls180.v:6107$1781_Y + end + attribute \src "ls180.v:6109.44-6109.97" + cell $and $and$ls180.v:6109$1782 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6109$1782_Y + end + attribute \src "ls180.v:6109.43-6109.148" + cell $and $and$ls180.v:6109$1784 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6109$1782_Y + connect \B $eq$ls180.v:6109$1783_Y + connect \Y $and$ls180.v:6109$1784_Y + end + attribute \src "ls180.v:6110.44-6110.100" + cell $and $and$ls180.v:6110$1786 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6110$1785_Y + connect \Y $and$ls180.v:6110$1786_Y + end + attribute \src "ls180.v:6110.43-6110.151" + cell $and $and$ls180.v:6110$1788 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6110$1786_Y + connect \B $eq$ls180.v:6110$1787_Y + connect \Y $and$ls180.v:6110$1788_Y + end + attribute \src "ls180.v:6134.44-6134.97" + cell $and $and$ls180.v:6134$1790 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B \builder_interface7_bank_bus_we + connect \Y $and$ls180.v:6134$1790_Y + end + attribute \src "ls180.v:6134.43-6134.147" + cell $and $and$ls180.v:6134$1792 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6134$1790_Y + connect \B $eq$ls180.v:6134$1791_Y + connect \Y $and$ls180.v:6134$1792_Y + end + attribute \src "ls180.v:6135.44-6135.100" + cell $and $and$ls180.v:6135$1794 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B $not$ls180.v:6135$1793_Y + connect \Y $and$ls180.v:6135$1794_Y + end + attribute \src "ls180.v:6135.43-6135.150" + cell $and $and$ls180.v:6135$1796 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6135$1794_Y + connect \B $eq$ls180.v:6135$1795_Y + connect \Y $and$ls180.v:6135$1796_Y + end + attribute \src "ls180.v:6137.49-6137.102" + cell $and $and$ls180.v:6137$1797 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B \builder_interface7_bank_bus_we + connect \Y $and$ls180.v:6137$1797_Y + end + attribute \src "ls180.v:6137.48-6137.152" + cell $and $and$ls180.v:6137$1799 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6137$1797_Y + connect \B $eq$ls180.v:6137$1798_Y + connect \Y $and$ls180.v:6137$1799_Y + end + attribute \src "ls180.v:6138.49-6138.105" + cell $and $and$ls180.v:6138$1801 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B $not$ls180.v:6138$1800_Y + connect \Y $and$ls180.v:6138$1801_Y + end + attribute \src "ls180.v:6138.48-6138.155" + cell $and $and$ls180.v:6138$1803 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6138$1801_Y + connect \B $eq$ls180.v:6138$1802_Y + connect \Y $and$ls180.v:6138$1803_Y + end + attribute \src "ls180.v:6140.49-6140.102" + cell $and $and$ls180.v:6140$1804 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B \builder_interface7_bank_bus_we + connect \Y $and$ls180.v:6140$1804_Y + end + attribute \src "ls180.v:6140.48-6140.152" + cell $and $and$ls180.v:6140$1806 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6140$1804_Y + connect \B $eq$ls180.v:6140$1805_Y + connect \Y $and$ls180.v:6140$1806_Y + end + attribute \src "ls180.v:6141.49-6141.105" + cell $and $and$ls180.v:6141$1808 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B $not$ls180.v:6141$1807_Y + connect \Y $and$ls180.v:6141$1808_Y + end + attribute \src "ls180.v:6141.48-6141.155" + cell $and $and$ls180.v:6141$1810 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6141$1808_Y + connect \B $eq$ls180.v:6141$1809_Y + connect \Y $and$ls180.v:6141$1810_Y + end + attribute \src "ls180.v:6143.42-6143.95" + cell $and $and$ls180.v:6143$1811 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B \builder_interface7_bank_bus_we + connect \Y $and$ls180.v:6143$1811_Y + end + attribute \src "ls180.v:6143.41-6143.145" + cell $and $and$ls180.v:6143$1813 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6143$1811_Y + connect \B $eq$ls180.v:6143$1812_Y + connect \Y $and$ls180.v:6143$1813_Y + end + attribute \src "ls180.v:6144.42-6144.98" + cell $and $and$ls180.v:6144$1815 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B $not$ls180.v:6144$1814_Y + connect \Y $and$ls180.v:6144$1815_Y + end + attribute \src "ls180.v:6144.41-6144.148" + cell $and $and$ls180.v:6144$1817 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6144$1815_Y + connect \B $eq$ls180.v:6144$1816_Y + connect \Y $and$ls180.v:6144$1817_Y + end + attribute \src "ls180.v:6151.46-6151.99" + cell $and $and$ls180.v:6151$1819 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank8_sel + connect \B \builder_interface8_bank_bus_we + connect \Y $and$ls180.v:6151$1819_Y + end + attribute \src "ls180.v:6151.45-6151.149" + cell $and $and$ls180.v:6151$1821 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6151$1819_Y + connect \B $eq$ls180.v:6151$1820_Y + connect \Y $and$ls180.v:6151$1821_Y + end + attribute \src "ls180.v:6152.46-6152.102" + cell $and $and$ls180.v:6152$1823 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank8_sel + connect \B $not$ls180.v:6152$1822_Y + connect \Y $and$ls180.v:6152$1823_Y + end + attribute \src "ls180.v:6152.45-6152.152" + cell $and $and$ls180.v:6152$1825 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6152$1823_Y + connect \B $eq$ls180.v:6152$1824_Y + connect \Y $and$ls180.v:6152$1825_Y + end + attribute \src "ls180.v:6154.50-6154.103" + cell $and $and$ls180.v:6154$1826 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank8_sel + connect \B \builder_interface8_bank_bus_we + connect \Y $and$ls180.v:6154$1826_Y + end + attribute \src "ls180.v:6154.49-6154.153" + cell $and $and$ls180.v:6154$1828 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6154$1826_Y + connect \B $eq$ls180.v:6154$1827_Y + connect \Y $and$ls180.v:6154$1828_Y + end + attribute \src "ls180.v:6155.50-6155.106" + cell $and $and$ls180.v:6155$1830 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank8_sel + connect \B $not$ls180.v:6155$1829_Y + connect \Y $and$ls180.v:6155$1830_Y + end + attribute \src "ls180.v:6155.49-6155.156" + cell $and $and$ls180.v:6155$1832 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6155$1830_Y + connect \B $eq$ls180.v:6155$1831_Y + connect \Y $and$ls180.v:6155$1832_Y + end + attribute \src "ls180.v:6157.40-6157.93" + cell $and $and$ls180.v:6157$1833 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank8_sel + connect \B \builder_interface8_bank_bus_we + connect \Y $and$ls180.v:6157$1833_Y + end + attribute \src "ls180.v:6157.39-6157.143" + cell $and $and$ls180.v:6157$1835 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6157$1833_Y + connect \B $eq$ls180.v:6157$1834_Y + connect \Y $and$ls180.v:6157$1835_Y + end + attribute \src "ls180.v:6158.40-6158.96" + cell $and $and$ls180.v:6158$1837 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank8_sel + connect \B $not$ls180.v:6158$1836_Y + connect \Y $and$ls180.v:6158$1837_Y + end + attribute \src "ls180.v:6158.39-6158.146" + cell $and $and$ls180.v:6158$1839 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6158$1837_Y + connect \B $eq$ls180.v:6158$1838_Y + connect \Y $and$ls180.v:6158$1839_Y + end + attribute \src "ls180.v:6160.50-6160.103" + cell $and $and$ls180.v:6160$1840 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank8_sel + connect \B \builder_interface8_bank_bus_we + connect \Y $and$ls180.v:6160$1840_Y + end + attribute \src "ls180.v:6160.49-6160.153" + cell $and $and$ls180.v:6160$1842 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6160$1840_Y + connect \B $eq$ls180.v:6160$1841_Y + connect \Y $and$ls180.v:6160$1842_Y + end + attribute \src "ls180.v:6161.50-6161.106" + cell $and $and$ls180.v:6161$1844 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank8_sel + connect \B $not$ls180.v:6161$1843_Y + connect \Y $and$ls180.v:6161$1844_Y + end + attribute \src "ls180.v:6161.49-6161.156" + cell $and $and$ls180.v:6161$1846 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6161$1844_Y + connect \B $eq$ls180.v:6161$1845_Y + connect \Y $and$ls180.v:6161$1846_Y + end + attribute \src "ls180.v:6163.50-6163.103" + cell $and $and$ls180.v:6163$1847 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank8_sel + connect \B \builder_interface8_bank_bus_we + connect \Y $and$ls180.v:6163$1847_Y + end + attribute \src "ls180.v:6163.49-6163.153" + cell $and $and$ls180.v:6163$1849 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6163$1847_Y + connect \B $eq$ls180.v:6163$1848_Y + connect \Y $and$ls180.v:6163$1849_Y + end + attribute \src "ls180.v:6164.50-6164.106" + cell $and $and$ls180.v:6164$1851 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank8_sel + connect \B $not$ls180.v:6164$1850_Y + connect \Y $and$ls180.v:6164$1851_Y + end + attribute \src "ls180.v:6164.49-6164.156" + cell $and $and$ls180.v:6164$1853 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6164$1851_Y + connect \B $eq$ls180.v:6164$1852_Y + connect \Y $and$ls180.v:6164$1853_Y + end + attribute \src "ls180.v:6166.51-6166.104" + cell $and $and$ls180.v:6166$1854 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank8_sel + connect \B \builder_interface8_bank_bus_we + connect \Y $and$ls180.v:6166$1854_Y + end + attribute \src "ls180.v:6166.50-6166.154" + cell $and $and$ls180.v:6166$1856 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6166$1854_Y + connect \B $eq$ls180.v:6166$1855_Y + connect \Y $and$ls180.v:6166$1856_Y + end + attribute \src "ls180.v:6167.51-6167.107" + cell $and $and$ls180.v:6167$1858 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank8_sel + connect \B $not$ls180.v:6167$1857_Y + connect \Y $and$ls180.v:6167$1858_Y + end + attribute \src "ls180.v:6167.50-6167.157" + cell $and $and$ls180.v:6167$1860 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6167$1858_Y + connect \B $eq$ls180.v:6167$1859_Y + connect \Y $and$ls180.v:6167$1860_Y + end + attribute \src "ls180.v:6169.49-6169.102" + cell $and $and$ls180.v:6169$1861 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank8_sel + connect \B \builder_interface8_bank_bus_we + connect \Y $and$ls180.v:6169$1861_Y + end + attribute \src "ls180.v:6169.48-6169.152" + cell $and $and$ls180.v:6169$1863 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6169$1861_Y + connect \B $eq$ls180.v:6169$1862_Y + connect \Y $and$ls180.v:6169$1863_Y + end + attribute \src "ls180.v:6170.49-6170.105" + cell $and $and$ls180.v:6170$1865 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank8_sel + connect \B $not$ls180.v:6170$1864_Y + connect \Y $and$ls180.v:6170$1865_Y + end + attribute \src "ls180.v:6170.48-6170.155" + cell $and $and$ls180.v:6170$1867 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6170$1865_Y + connect \B $eq$ls180.v:6170$1866_Y + connect \Y $and$ls180.v:6170$1867_Y + end + attribute \src "ls180.v:6172.49-6172.102" + cell $and $and$ls180.v:6172$1868 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank8_sel + connect \B \builder_interface8_bank_bus_we + connect \Y $and$ls180.v:6172$1868_Y + end + attribute \src "ls180.v:6172.48-6172.152" + cell $and $and$ls180.v:6172$1870 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6172$1868_Y + connect \B $eq$ls180.v:6172$1869_Y + connect \Y $and$ls180.v:6172$1870_Y + end + attribute \src "ls180.v:6173.49-6173.105" + cell $and $and$ls180.v:6173$1872 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank8_sel + connect \B $not$ls180.v:6173$1871_Y + connect \Y $and$ls180.v:6173$1872_Y + end + attribute \src "ls180.v:6173.48-6173.155" + cell $and $and$ls180.v:6173$1874 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6173$1872_Y + connect \B $eq$ls180.v:6173$1873_Y + connect \Y $and$ls180.v:6173$1874_Y + end + attribute \src "ls180.v:6175.49-6175.102" + cell $and $and$ls180.v:6175$1875 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank8_sel + connect \B \builder_interface8_bank_bus_we + connect \Y $and$ls180.v:6175$1875_Y + end + attribute \src "ls180.v:6175.48-6175.152" + cell $and $and$ls180.v:6175$1877 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6175$1875_Y + connect \B $eq$ls180.v:6175$1876_Y + connect \Y $and$ls180.v:6175$1877_Y + end + attribute \src "ls180.v:6176.49-6176.105" + cell $and $and$ls180.v:6176$1879 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank8_sel + connect \B $not$ls180.v:6176$1878_Y + connect \Y $and$ls180.v:6176$1879_Y + end + attribute \src "ls180.v:6176.48-6176.155" + cell $and $and$ls180.v:6176$1881 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6176$1879_Y + connect \B $eq$ls180.v:6176$1880_Y + connect \Y $and$ls180.v:6176$1881_Y + end + attribute \src "ls180.v:6178.49-6178.102" + cell $and $and$ls180.v:6178$1882 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank8_sel + connect \B \builder_interface8_bank_bus_we + connect \Y $and$ls180.v:6178$1882_Y + end + attribute \src "ls180.v:6178.48-6178.152" + cell $and $and$ls180.v:6178$1884 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6178$1882_Y + connect \B $eq$ls180.v:6178$1883_Y + connect \Y $and$ls180.v:6178$1884_Y + end + attribute \src "ls180.v:6179.49-6179.105" + cell $and $and$ls180.v:6179$1886 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank8_sel + connect \B $not$ls180.v:6179$1885_Y + connect \Y $and$ls180.v:6179$1886_Y + end + attribute \src "ls180.v:6179.48-6179.155" + cell $and $and$ls180.v:6179$1888 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6179$1886_Y + connect \B $eq$ls180.v:6179$1887_Y + connect \Y $and$ls180.v:6179$1888_Y + end + attribute \src "ls180.v:6196.41-6196.94" + cell $and $and$ls180.v:6196$1890 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B \builder_interface9_bank_bus_we + connect \Y $and$ls180.v:6196$1890_Y + end + attribute \src "ls180.v:6196.40-6196.144" + cell $and $and$ls180.v:6196$1892 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6196$1890_Y + connect \B $eq$ls180.v:6196$1891_Y + connect \Y $and$ls180.v:6196$1892_Y + end + attribute \src "ls180.v:6197.41-6197.97" + cell $and $and$ls180.v:6197$1894 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B $not$ls180.v:6197$1893_Y + connect \Y $and$ls180.v:6197$1894_Y + end + attribute \src "ls180.v:6197.40-6197.147" + cell $and $and$ls180.v:6197$1896 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6197$1894_Y + connect \B $eq$ls180.v:6197$1895_Y + connect \Y $and$ls180.v:6197$1896_Y + end + attribute \src "ls180.v:6199.41-6199.94" + cell $and $and$ls180.v:6199$1897 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B \builder_interface9_bank_bus_we + connect \Y $and$ls180.v:6199$1897_Y + end + attribute \src "ls180.v:6199.40-6199.144" + cell $and $and$ls180.v:6199$1899 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6199$1897_Y + connect \B $eq$ls180.v:6199$1898_Y + connect \Y $and$ls180.v:6199$1899_Y + end + attribute \src "ls180.v:6200.41-6200.97" + cell $and $and$ls180.v:6200$1901 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B $not$ls180.v:6200$1900_Y + connect \Y $and$ls180.v:6200$1901_Y + end + attribute \src "ls180.v:6200.40-6200.147" + cell $and $and$ls180.v:6200$1903 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6200$1901_Y + connect \B $eq$ls180.v:6200$1902_Y + connect \Y $and$ls180.v:6200$1903_Y + end + attribute \src "ls180.v:6202.39-6202.92" + cell $and $and$ls180.v:6202$1904 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B \builder_interface9_bank_bus_we + connect \Y $and$ls180.v:6202$1904_Y + end + attribute \src "ls180.v:6202.38-6202.142" + cell $and $and$ls180.v:6202$1906 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6202$1904_Y + connect \B $eq$ls180.v:6202$1905_Y + connect \Y $and$ls180.v:6202$1906_Y + end + attribute \src "ls180.v:6203.39-6203.95" + cell $and $and$ls180.v:6203$1908 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B $not$ls180.v:6203$1907_Y + connect \Y $and$ls180.v:6203$1908_Y + end + attribute \src "ls180.v:6203.38-6203.145" + cell $and $and$ls180.v:6203$1910 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6203$1908_Y + connect \B $eq$ls180.v:6203$1909_Y + connect \Y $and$ls180.v:6203$1910_Y + end + attribute \src "ls180.v:6205.38-6205.91" + cell $and $and$ls180.v:6205$1911 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B \builder_interface9_bank_bus_we + connect \Y $and$ls180.v:6205$1911_Y + end + attribute \src "ls180.v:6205.37-6205.141" + cell $and $and$ls180.v:6205$1913 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6205$1911_Y + connect \B $eq$ls180.v:6205$1912_Y + connect \Y $and$ls180.v:6205$1913_Y + end + attribute \src "ls180.v:6206.38-6206.94" + cell $and $and$ls180.v:6206$1915 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B $not$ls180.v:6206$1914_Y + connect \Y $and$ls180.v:6206$1915_Y + end + attribute \src "ls180.v:6206.37-6206.144" + cell $and $and$ls180.v:6206$1917 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6206$1915_Y + connect \B $eq$ls180.v:6206$1916_Y + connect \Y $and$ls180.v:6206$1917_Y + end + attribute \src "ls180.v:6208.37-6208.90" + cell $and $and$ls180.v:6208$1918 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B \builder_interface9_bank_bus_we + connect \Y $and$ls180.v:6208$1918_Y + end + attribute \src "ls180.v:6208.36-6208.140" + cell $and $and$ls180.v:6208$1920 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6208$1918_Y + connect \B $eq$ls180.v:6208$1919_Y + connect \Y $and$ls180.v:6208$1920_Y + end + attribute \src "ls180.v:6209.37-6209.93" + cell $and $and$ls180.v:6209$1922 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B $not$ls180.v:6209$1921_Y + connect \Y $and$ls180.v:6209$1922_Y + end + attribute \src "ls180.v:6209.36-6209.143" + cell $and $and$ls180.v:6209$1924 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6209$1922_Y + connect \B $eq$ls180.v:6209$1923_Y + connect \Y $and$ls180.v:6209$1924_Y + end + attribute \src "ls180.v:6211.36-6211.89" + cell $and $and$ls180.v:6211$1925 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B \builder_interface9_bank_bus_we + connect \Y $and$ls180.v:6211$1925_Y + end + attribute \src "ls180.v:6211.35-6211.139" + cell $and $and$ls180.v:6211$1927 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6211$1925_Y + connect \B $eq$ls180.v:6211$1926_Y + connect \Y $and$ls180.v:6211$1927_Y + end + attribute \src "ls180.v:6212.36-6212.92" + cell $and $and$ls180.v:6212$1929 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B $not$ls180.v:6212$1928_Y + connect \Y $and$ls180.v:6212$1929_Y + end + attribute \src "ls180.v:6212.35-6212.142" + cell $and $and$ls180.v:6212$1931 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6212$1929_Y + connect \B $eq$ls180.v:6212$1930_Y + connect \Y $and$ls180.v:6212$1931_Y + end + attribute \src "ls180.v:6214.42-6214.95" + cell $and $and$ls180.v:6214$1932 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B \builder_interface9_bank_bus_we + connect \Y $and$ls180.v:6214$1932_Y + end + attribute \src "ls180.v:6214.41-6214.145" + cell $and $and$ls180.v:6214$1934 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6214$1932_Y + connect \B $eq$ls180.v:6214$1933_Y + connect \Y $and$ls180.v:6214$1934_Y + end + attribute \src "ls180.v:6215.42-6215.98" + cell $and $and$ls180.v:6215$1936 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B $not$ls180.v:6215$1935_Y + connect \Y $and$ls180.v:6215$1936_Y + end + attribute \src "ls180.v:6215.41-6215.148" + cell $and $and$ls180.v:6215$1938 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6215$1936_Y + connect \B $eq$ls180.v:6215$1937_Y + connect \Y $and$ls180.v:6215$1938_Y + end + attribute \src "ls180.v:6236.42-6236.97" + cell $and $and$ls180.v:6236$1941 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank10_sel + connect \B \builder_interface10_bank_bus_we + connect \Y $and$ls180.v:6236$1941_Y + end + attribute \src "ls180.v:6236.41-6236.148" + cell $and $and$ls180.v:6236$1943 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6236$1941_Y + connect \B $eq$ls180.v:6236$1942_Y + connect \Y $and$ls180.v:6236$1943_Y + end + attribute \src "ls180.v:6237.42-6237.100" + cell $and $and$ls180.v:6237$1945 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank10_sel + connect \B $not$ls180.v:6237$1944_Y + connect \Y $and$ls180.v:6237$1945_Y + end + attribute \src "ls180.v:6237.41-6237.151" + cell $and $and$ls180.v:6237$1947 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6237$1945_Y + connect \B $eq$ls180.v:6237$1946_Y + connect \Y $and$ls180.v:6237$1947_Y + end + attribute \src "ls180.v:6239.42-6239.97" + cell $and $and$ls180.v:6239$1948 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank10_sel + connect \B \builder_interface10_bank_bus_we + connect \Y $and$ls180.v:6239$1948_Y + end + attribute \src "ls180.v:6239.41-6239.148" + cell $and $and$ls180.v:6239$1950 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6239$1948_Y + connect \B $eq$ls180.v:6239$1949_Y + connect \Y $and$ls180.v:6239$1950_Y + end + attribute \src "ls180.v:6240.42-6240.100" + cell $and $and$ls180.v:6240$1952 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank10_sel + connect \B $not$ls180.v:6240$1951_Y + connect \Y $and$ls180.v:6240$1952_Y + end + attribute \src "ls180.v:6240.41-6240.151" + cell $and $and$ls180.v:6240$1954 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6240$1952_Y + connect \B $eq$ls180.v:6240$1953_Y + connect \Y $and$ls180.v:6240$1954_Y + end + attribute \src "ls180.v:6242.40-6242.95" + cell $and $and$ls180.v:6242$1955 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank10_sel + connect \B \builder_interface10_bank_bus_we + connect \Y $and$ls180.v:6242$1955_Y + end + attribute \src "ls180.v:6242.39-6242.146" + cell $and $and$ls180.v:6242$1957 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6242$1955_Y + connect \B $eq$ls180.v:6242$1956_Y + connect \Y $and$ls180.v:6242$1957_Y + end + attribute \src "ls180.v:6243.40-6243.98" + cell $and $and$ls180.v:6243$1959 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank10_sel + connect \B $not$ls180.v:6243$1958_Y + connect \Y $and$ls180.v:6243$1959_Y + end + attribute \src "ls180.v:6243.39-6243.149" + cell $and $and$ls180.v:6243$1961 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6243$1959_Y + connect \B $eq$ls180.v:6243$1960_Y + connect \Y $and$ls180.v:6243$1961_Y + end + attribute \src "ls180.v:6245.39-6245.94" + cell $and $and$ls180.v:6245$1962 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank10_sel + connect \B \builder_interface10_bank_bus_we + connect \Y $and$ls180.v:6245$1962_Y + end + attribute \src "ls180.v:6245.38-6245.145" + cell $and $and$ls180.v:6245$1964 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6245$1962_Y + connect \B $eq$ls180.v:6245$1963_Y + connect \Y $and$ls180.v:6245$1964_Y + end + attribute \src "ls180.v:6246.39-6246.97" + cell $and $and$ls180.v:6246$1966 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank10_sel + connect \B $not$ls180.v:6246$1965_Y + connect \Y $and$ls180.v:6246$1966_Y + end + attribute \src "ls180.v:6246.38-6246.148" + cell $and $and$ls180.v:6246$1968 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6246$1966_Y + connect \B $eq$ls180.v:6246$1967_Y + connect \Y $and$ls180.v:6246$1968_Y + end + attribute \src "ls180.v:6248.38-6248.93" + cell $and $and$ls180.v:6248$1969 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank10_sel + connect \B \builder_interface10_bank_bus_we + connect \Y $and$ls180.v:6248$1969_Y + end + attribute \src "ls180.v:6248.37-6248.144" + cell $and $and$ls180.v:6248$1971 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6248$1969_Y + connect \B $eq$ls180.v:6248$1970_Y + connect \Y $and$ls180.v:6248$1971_Y + end + attribute \src "ls180.v:6249.38-6249.96" + cell $and $and$ls180.v:6249$1973 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank10_sel + connect \B $not$ls180.v:6249$1972_Y + connect \Y $and$ls180.v:6249$1973_Y + end + attribute \src "ls180.v:6249.37-6249.147" + cell $and $and$ls180.v:6249$1975 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6249$1973_Y + connect \B $eq$ls180.v:6249$1974_Y + connect \Y $and$ls180.v:6249$1975_Y + end + attribute \src "ls180.v:6251.37-6251.92" + cell $and $and$ls180.v:6251$1976 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank10_sel + connect \B \builder_interface10_bank_bus_we + connect \Y $and$ls180.v:6251$1976_Y + end + attribute \src "ls180.v:6251.36-6251.143" + cell $and $and$ls180.v:6251$1978 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6251$1976_Y + connect \B $eq$ls180.v:6251$1977_Y + connect \Y $and$ls180.v:6251$1978_Y + end + attribute \src "ls180.v:6252.37-6252.95" + cell $and $and$ls180.v:6252$1980 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank10_sel + connect \B $not$ls180.v:6252$1979_Y + connect \Y $and$ls180.v:6252$1980_Y + end + attribute \src "ls180.v:6252.36-6252.146" + cell $and $and$ls180.v:6252$1982 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6252$1980_Y + connect \B $eq$ls180.v:6252$1981_Y + connect \Y $and$ls180.v:6252$1982_Y + end + attribute \src "ls180.v:6254.43-6254.98" + cell $and $and$ls180.v:6254$1983 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank10_sel + connect \B \builder_interface10_bank_bus_we + connect \Y $and$ls180.v:6254$1983_Y + end + attribute \src "ls180.v:6254.42-6254.149" + cell $and $and$ls180.v:6254$1985 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6254$1983_Y + connect \B $eq$ls180.v:6254$1984_Y + connect \Y $and$ls180.v:6254$1985_Y + end + attribute \src "ls180.v:6255.43-6255.101" + cell $and $and$ls180.v:6255$1987 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank10_sel + connect \B $not$ls180.v:6255$1986_Y + connect \Y $and$ls180.v:6255$1987_Y + end + attribute \src "ls180.v:6255.42-6255.152" + cell $and $and$ls180.v:6255$1989 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6255$1987_Y + connect \B $eq$ls180.v:6255$1988_Y + connect \Y $and$ls180.v:6255$1989_Y + end + attribute \src "ls180.v:6257.46-6257.101" + cell $and $and$ls180.v:6257$1990 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank10_sel + connect \B \builder_interface10_bank_bus_we + connect \Y $and$ls180.v:6257$1990_Y + end + attribute \src "ls180.v:6257.45-6257.152" + cell $and $and$ls180.v:6257$1992 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6257$1990_Y + connect \B $eq$ls180.v:6257$1991_Y + connect \Y $and$ls180.v:6257$1992_Y + end + attribute \src "ls180.v:6258.46-6258.104" + cell $and $and$ls180.v:6258$1994 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank10_sel + connect \B $not$ls180.v:6258$1993_Y + connect \Y $and$ls180.v:6258$1994_Y + end + attribute \src "ls180.v:6258.45-6258.155" + cell $and $and$ls180.v:6258$1996 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6258$1994_Y + connect \B $eq$ls180.v:6258$1995_Y + connect \Y $and$ls180.v:6258$1996_Y + end + attribute \src "ls180.v:6260.46-6260.101" + cell $and $and$ls180.v:6260$1997 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank10_sel + connect \B \builder_interface10_bank_bus_we + connect \Y $and$ls180.v:6260$1997_Y + end + attribute \src "ls180.v:6260.45-6260.152" + cell $and $and$ls180.v:6260$1999 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6260$1997_Y + connect \B $eq$ls180.v:6260$1998_Y + connect \Y $and$ls180.v:6260$1999_Y + end + attribute \src "ls180.v:6261.46-6261.104" + cell $and $and$ls180.v:6261$2001 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank10_sel + connect \B $not$ls180.v:6261$2000_Y + connect \Y $and$ls180.v:6261$2001_Y + end + attribute \src "ls180.v:6261.45-6261.155" + cell $and $and$ls180.v:6261$2003 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6261$2001_Y + connect \B $eq$ls180.v:6261$2002_Y + connect \Y $and$ls180.v:6261$2003_Y + end + attribute \src "ls180.v:6284.39-6284.94" + cell $and $and$ls180.v:6284$2006 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B \builder_interface11_bank_bus_we + connect \Y $and$ls180.v:6284$2006_Y + end + attribute \src "ls180.v:6284.38-6284.145" + cell $and $and$ls180.v:6284$2008 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6284$2006_Y + connect \B $eq$ls180.v:6284$2007_Y + connect \Y $and$ls180.v:6284$2008_Y + end + attribute \src "ls180.v:6285.39-6285.97" + cell $and $and$ls180.v:6285$2010 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B $not$ls180.v:6285$2009_Y + connect \Y $and$ls180.v:6285$2010_Y + end + attribute \src "ls180.v:6285.38-6285.148" + cell $and $and$ls180.v:6285$2012 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6285$2010_Y + connect \B $eq$ls180.v:6285$2011_Y + connect \Y $and$ls180.v:6285$2012_Y + end + attribute \src "ls180.v:6287.39-6287.94" + cell $and $and$ls180.v:6287$2013 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B \builder_interface11_bank_bus_we + connect \Y $and$ls180.v:6287$2013_Y + end + attribute \src "ls180.v:6287.38-6287.145" + cell $and $and$ls180.v:6287$2015 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6287$2013_Y + connect \B $eq$ls180.v:6287$2014_Y + connect \Y $and$ls180.v:6287$2015_Y + end + attribute \src "ls180.v:6288.39-6288.97" + cell $and $and$ls180.v:6288$2017 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B $not$ls180.v:6288$2016_Y + connect \Y $and$ls180.v:6288$2017_Y + end + attribute \src "ls180.v:6288.38-6288.148" + cell $and $and$ls180.v:6288$2019 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6288$2017_Y + connect \B $eq$ls180.v:6288$2018_Y + connect \Y $and$ls180.v:6288$2019_Y + end + attribute \src "ls180.v:6290.39-6290.94" + cell $and $and$ls180.v:6290$2020 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B \builder_interface11_bank_bus_we + connect \Y $and$ls180.v:6290$2020_Y + end + attribute \src "ls180.v:6290.38-6290.145" + cell $and $and$ls180.v:6290$2022 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6290$2020_Y + connect \B $eq$ls180.v:6290$2021_Y + connect \Y $and$ls180.v:6290$2022_Y + end + attribute \src "ls180.v:6291.39-6291.97" + cell $and $and$ls180.v:6291$2024 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B $not$ls180.v:6291$2023_Y + connect \Y $and$ls180.v:6291$2024_Y + end + attribute \src "ls180.v:6291.38-6291.148" + cell $and $and$ls180.v:6291$2026 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6291$2024_Y + connect \B $eq$ls180.v:6291$2025_Y + connect \Y $and$ls180.v:6291$2026_Y + end + attribute \src "ls180.v:6293.39-6293.94" + cell $and $and$ls180.v:6293$2027 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B \builder_interface11_bank_bus_we + connect \Y $and$ls180.v:6293$2027_Y + end + attribute \src "ls180.v:6293.38-6293.145" + cell $and $and$ls180.v:6293$2029 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6293$2027_Y + connect \B $eq$ls180.v:6293$2028_Y + connect \Y $and$ls180.v:6293$2029_Y + end + attribute \src "ls180.v:6294.39-6294.97" + cell $and $and$ls180.v:6294$2031 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B $not$ls180.v:6294$2030_Y + connect \Y $and$ls180.v:6294$2031_Y + end + attribute \src "ls180.v:6294.38-6294.148" + cell $and $and$ls180.v:6294$2033 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6294$2031_Y + connect \B $eq$ls180.v:6294$2032_Y + connect \Y $and$ls180.v:6294$2033_Y + end + attribute \src "ls180.v:6296.41-6296.96" + cell $and $and$ls180.v:6296$2034 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B \builder_interface11_bank_bus_we + connect \Y $and$ls180.v:6296$2034_Y + end + attribute \src "ls180.v:6296.40-6296.147" + cell $and $and$ls180.v:6296$2036 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6296$2034_Y + connect \B $eq$ls180.v:6296$2035_Y + connect \Y $and$ls180.v:6296$2036_Y + end + attribute \src "ls180.v:6297.41-6297.99" + cell $and $and$ls180.v:6297$2038 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B $not$ls180.v:6297$2037_Y + connect \Y $and$ls180.v:6297$2038_Y + end + attribute \src "ls180.v:6297.40-6297.150" + cell $and $and$ls180.v:6297$2040 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6297$2038_Y + connect \B $eq$ls180.v:6297$2039_Y + connect \Y $and$ls180.v:6297$2040_Y + end + attribute \src "ls180.v:6299.41-6299.96" + cell $and $and$ls180.v:6299$2041 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B \builder_interface11_bank_bus_we + connect \Y $and$ls180.v:6299$2041_Y + end + attribute \src "ls180.v:6299.40-6299.147" + cell $and $and$ls180.v:6299$2043 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6299$2041_Y + connect \B $eq$ls180.v:6299$2042_Y + connect \Y $and$ls180.v:6299$2043_Y + end + attribute \src "ls180.v:6300.41-6300.99" + cell $and $and$ls180.v:6300$2045 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B $not$ls180.v:6300$2044_Y + connect \Y $and$ls180.v:6300$2045_Y + end + attribute \src "ls180.v:6300.40-6300.150" + cell $and $and$ls180.v:6300$2047 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6300$2045_Y + connect \B $eq$ls180.v:6300$2046_Y + connect \Y $and$ls180.v:6300$2047_Y + end + attribute \src "ls180.v:6302.41-6302.96" + cell $and $and$ls180.v:6302$2048 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B \builder_interface11_bank_bus_we + connect \Y $and$ls180.v:6302$2048_Y + end + attribute \src "ls180.v:6302.40-6302.147" + cell $and $and$ls180.v:6302$2050 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6302$2048_Y + connect \B $eq$ls180.v:6302$2049_Y + connect \Y $and$ls180.v:6302$2050_Y + end + attribute \src "ls180.v:6303.41-6303.99" + cell $and $and$ls180.v:6303$2052 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B $not$ls180.v:6303$2051_Y + connect \Y $and$ls180.v:6303$2052_Y + end + attribute \src "ls180.v:6303.40-6303.150" + cell $and $and$ls180.v:6303$2054 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6303$2052_Y + connect \B $eq$ls180.v:6303$2053_Y + connect \Y $and$ls180.v:6303$2054_Y + end + attribute \src "ls180.v:6305.41-6305.96" + cell $and $and$ls180.v:6305$2055 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B \builder_interface11_bank_bus_we + connect \Y $and$ls180.v:6305$2055_Y + end + attribute \src "ls180.v:6305.40-6305.147" + cell $and $and$ls180.v:6305$2057 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6305$2055_Y + connect \B $eq$ls180.v:6305$2056_Y + connect \Y $and$ls180.v:6305$2057_Y + end + attribute \src "ls180.v:6306.41-6306.99" + cell $and $and$ls180.v:6306$2059 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B $not$ls180.v:6306$2058_Y + connect \Y $and$ls180.v:6306$2059_Y + end + attribute \src "ls180.v:6306.40-6306.150" + cell $and $and$ls180.v:6306$2061 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6306$2059_Y + connect \B $eq$ls180.v:6306$2060_Y + connect \Y $and$ls180.v:6306$2061_Y + end + attribute \src "ls180.v:6308.37-6308.92" + cell $and $and$ls180.v:6308$2062 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B \builder_interface11_bank_bus_we + connect \Y $and$ls180.v:6308$2062_Y + end + attribute \src "ls180.v:6308.36-6308.143" + cell $and $and$ls180.v:6308$2064 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6308$2062_Y + connect \B $eq$ls180.v:6308$2063_Y + connect \Y $and$ls180.v:6308$2064_Y + end + attribute \src "ls180.v:6309.37-6309.95" + cell $and $and$ls180.v:6309$2066 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B $not$ls180.v:6309$2065_Y + connect \Y $and$ls180.v:6309$2066_Y + end + attribute \src "ls180.v:6309.36-6309.146" + cell $and $and$ls180.v:6309$2068 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6309$2066_Y + connect \B $eq$ls180.v:6309$2067_Y + connect \Y $and$ls180.v:6309$2068_Y + end + attribute \src "ls180.v:6311.47-6311.102" + cell $and $and$ls180.v:6311$2069 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B \builder_interface11_bank_bus_we + connect \Y $and$ls180.v:6311$2069_Y + end + attribute \src "ls180.v:6311.46-6311.153" + cell $and $and$ls180.v:6311$2071 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6311$2069_Y + connect \B $eq$ls180.v:6311$2070_Y + connect \Y $and$ls180.v:6311$2071_Y + end + attribute \src "ls180.v:6312.47-6312.105" + cell $and $and$ls180.v:6312$2073 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B $not$ls180.v:6312$2072_Y + connect \Y $and$ls180.v:6312$2073_Y + end + attribute \src "ls180.v:6312.46-6312.156" + cell $and $and$ls180.v:6312$2075 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6312$2073_Y + connect \B $eq$ls180.v:6312$2074_Y + connect \Y $and$ls180.v:6312$2075_Y + end + attribute \src "ls180.v:6314.40-6314.95" + cell $and $and$ls180.v:6314$2076 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B \builder_interface11_bank_bus_we + connect \Y $and$ls180.v:6314$2076_Y + end + attribute \src "ls180.v:6314.39-6314.147" + cell $and $and$ls180.v:6314$2078 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6314$2076_Y + connect \B $eq$ls180.v:6314$2077_Y + connect \Y $and$ls180.v:6314$2078_Y + end + attribute \src "ls180.v:6315.40-6315.98" + cell $and $and$ls180.v:6315$2080 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B $not$ls180.v:6315$2079_Y + connect \Y $and$ls180.v:6315$2080_Y + end + attribute \src "ls180.v:6315.39-6315.150" + cell $and $and$ls180.v:6315$2082 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6315$2080_Y + connect \B $eq$ls180.v:6315$2081_Y + connect \Y $and$ls180.v:6315$2082_Y + end + attribute \src "ls180.v:6317.40-6317.95" + cell $and $and$ls180.v:6317$2083 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B \builder_interface11_bank_bus_we + connect \Y $and$ls180.v:6317$2083_Y + end + attribute \src "ls180.v:6317.39-6317.147" + cell $and $and$ls180.v:6317$2085 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6317$2083_Y + connect \B $eq$ls180.v:6317$2084_Y + connect \Y $and$ls180.v:6317$2085_Y + end + attribute \src "ls180.v:6318.40-6318.98" + cell $and $and$ls180.v:6318$2087 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B $not$ls180.v:6318$2086_Y + connect \Y $and$ls180.v:6318$2087_Y + end + attribute \src "ls180.v:6318.39-6318.150" + cell $and $and$ls180.v:6318$2089 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6318$2087_Y + connect \B $eq$ls180.v:6318$2088_Y + connect \Y $and$ls180.v:6318$2089_Y + end + attribute \src "ls180.v:6320.40-6320.95" + cell $and $and$ls180.v:6320$2090 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B \builder_interface11_bank_bus_we + connect \Y $and$ls180.v:6320$2090_Y + end + attribute \src "ls180.v:6320.39-6320.147" + cell $and $and$ls180.v:6320$2092 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6320$2090_Y + connect \B $eq$ls180.v:6320$2091_Y + connect \Y $and$ls180.v:6320$2092_Y + end + attribute \src "ls180.v:6321.40-6321.98" + cell $and $and$ls180.v:6321$2094 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B $not$ls180.v:6321$2093_Y + connect \Y $and$ls180.v:6321$2094_Y + end + attribute \src "ls180.v:6321.39-6321.150" + cell $and $and$ls180.v:6321$2096 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6321$2094_Y + connect \B $eq$ls180.v:6321$2095_Y + connect \Y $and$ls180.v:6321$2096_Y + end + attribute \src "ls180.v:6323.40-6323.95" + cell $and $and$ls180.v:6323$2097 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B \builder_interface11_bank_bus_we + connect \Y $and$ls180.v:6323$2097_Y + end + attribute \src "ls180.v:6323.39-6323.147" + cell $and $and$ls180.v:6323$2099 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6323$2097_Y + connect \B $eq$ls180.v:6323$2098_Y + connect \Y $and$ls180.v:6323$2099_Y + end + attribute \src "ls180.v:6324.40-6324.98" + cell $and $and$ls180.v:6324$2101 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B $not$ls180.v:6324$2100_Y + connect \Y $and$ls180.v:6324$2101_Y + end + attribute \src "ls180.v:6324.39-6324.150" + cell $and $and$ls180.v:6324$2103 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6324$2101_Y + connect \B $eq$ls180.v:6324$2102_Y + connect \Y $and$ls180.v:6324$2103_Y + end + attribute \src "ls180.v:6326.52-6326.107" + cell $and $and$ls180.v:6326$2104 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B \builder_interface11_bank_bus_we + connect \Y $and$ls180.v:6326$2104_Y + end + attribute \src "ls180.v:6326.51-6326.159" + cell $and $and$ls180.v:6326$2106 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6326$2104_Y + connect \B $eq$ls180.v:6326$2105_Y + connect \Y $and$ls180.v:6326$2106_Y + end + attribute \src "ls180.v:6327.52-6327.110" + cell $and $and$ls180.v:6327$2108 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B $not$ls180.v:6327$2107_Y + connect \Y $and$ls180.v:6327$2108_Y + end + attribute \src "ls180.v:6327.51-6327.162" + cell $and $and$ls180.v:6327$2110 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6327$2108_Y + connect \B $eq$ls180.v:6327$2109_Y + connect \Y $and$ls180.v:6327$2110_Y + end + attribute \src "ls180.v:6329.53-6329.108" + cell $and $and$ls180.v:6329$2111 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B \builder_interface11_bank_bus_we + connect \Y $and$ls180.v:6329$2111_Y + end + attribute \src "ls180.v:6329.52-6329.160" + cell $and $and$ls180.v:6329$2113 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6329$2111_Y + connect \B $eq$ls180.v:6329$2112_Y + connect \Y $and$ls180.v:6329$2113_Y + end + attribute \src "ls180.v:6330.53-6330.111" + cell $and $and$ls180.v:6330$2115 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B $not$ls180.v:6330$2114_Y + connect \Y $and$ls180.v:6330$2115_Y + end + attribute \src "ls180.v:6330.52-6330.163" + cell $and $and$ls180.v:6330$2117 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6330$2115_Y + connect \B $eq$ls180.v:6330$2116_Y + connect \Y $and$ls180.v:6330$2117_Y + end + attribute \src "ls180.v:6332.44-6332.99" + cell $and $and$ls180.v:6332$2118 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B \builder_interface11_bank_bus_we + connect \Y $and$ls180.v:6332$2118_Y + end + attribute \src "ls180.v:6332.43-6332.151" + cell $and $and$ls180.v:6332$2120 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6332$2118_Y + connect \B $eq$ls180.v:6332$2119_Y + connect \Y $and$ls180.v:6332$2120_Y + end + attribute \src "ls180.v:6333.44-6333.102" + cell $and $and$ls180.v:6333$2122 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B $not$ls180.v:6333$2121_Y + connect \Y $and$ls180.v:6333$2122_Y + end + attribute \src "ls180.v:6333.43-6333.154" + cell $and $and$ls180.v:6333$2124 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6333$2122_Y + connect \B $eq$ls180.v:6333$2123_Y + connect \Y $and$ls180.v:6333$2124_Y + end + attribute \src "ls180.v:6352.30-6352.85" + cell $and $and$ls180.v:6352$2126 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B \builder_interface12_bank_bus_we + connect \Y $and$ls180.v:6352$2126_Y + end + attribute \src "ls180.v:6352.29-6352.136" + cell $and $and$ls180.v:6352$2128 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6352$2126_Y + connect \B $eq$ls180.v:6352$2127_Y + connect \Y $and$ls180.v:6352$2128_Y + end + attribute \src "ls180.v:6353.30-6353.88" + cell $and $and$ls180.v:6353$2130 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B $not$ls180.v:6353$2129_Y + connect \Y $and$ls180.v:6353$2130_Y + end + attribute \src "ls180.v:6353.29-6353.139" + cell $and $and$ls180.v:6353$2132 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6353$2130_Y + connect \B $eq$ls180.v:6353$2131_Y + connect \Y $and$ls180.v:6353$2132_Y + end + attribute \src "ls180.v:6355.40-6355.95" + cell $and $and$ls180.v:6355$2133 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B \builder_interface12_bank_bus_we + connect \Y $and$ls180.v:6355$2133_Y + end + attribute \src "ls180.v:6355.39-6355.146" + cell $and $and$ls180.v:6355$2135 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6355$2133_Y + connect \B $eq$ls180.v:6355$2134_Y + connect \Y $and$ls180.v:6355$2135_Y + end + attribute \src "ls180.v:6356.40-6356.98" + cell $and $and$ls180.v:6356$2137 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B $not$ls180.v:6356$2136_Y + connect \Y $and$ls180.v:6356$2137_Y + end + attribute \src "ls180.v:6356.39-6356.149" + cell $and $and$ls180.v:6356$2139 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6356$2137_Y + connect \B $eq$ls180.v:6356$2138_Y + connect \Y $and$ls180.v:6356$2139_Y + end + attribute \src "ls180.v:6358.41-6358.96" + cell $and $and$ls180.v:6358$2140 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B \builder_interface12_bank_bus_we + connect \Y $and$ls180.v:6358$2140_Y + end + attribute \src "ls180.v:6358.40-6358.147" + cell $and $and$ls180.v:6358$2142 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6358$2140_Y + connect \B $eq$ls180.v:6358$2141_Y + connect \Y $and$ls180.v:6358$2142_Y + end + attribute \src "ls180.v:6359.41-6359.99" + cell $and $and$ls180.v:6359$2144 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B $not$ls180.v:6359$2143_Y + connect \Y $and$ls180.v:6359$2144_Y + end + attribute \src "ls180.v:6359.40-6359.150" + cell $and $and$ls180.v:6359$2146 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6359$2144_Y + connect \B $eq$ls180.v:6359$2145_Y + connect \Y $and$ls180.v:6359$2146_Y + end + attribute \src "ls180.v:6361.45-6361.100" + cell $and $and$ls180.v:6361$2147 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B \builder_interface12_bank_bus_we + connect \Y $and$ls180.v:6361$2147_Y + end + attribute \src "ls180.v:6361.44-6361.151" + cell $and $and$ls180.v:6361$2149 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6361$2147_Y + connect \B $eq$ls180.v:6361$2148_Y + connect \Y $and$ls180.v:6361$2149_Y + end + attribute \src "ls180.v:6362.45-6362.103" + cell $and $and$ls180.v:6362$2151 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B $not$ls180.v:6362$2150_Y + connect \Y $and$ls180.v:6362$2151_Y + end + attribute \src "ls180.v:6362.44-6362.154" + cell $and $and$ls180.v:6362$2153 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6362$2151_Y + connect \B $eq$ls180.v:6362$2152_Y + connect \Y $and$ls180.v:6362$2153_Y + end + attribute \src "ls180.v:6364.46-6364.101" + cell $and $and$ls180.v:6364$2154 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B \builder_interface12_bank_bus_we + connect \Y $and$ls180.v:6364$2154_Y + end + attribute \src "ls180.v:6364.45-6364.152" + cell $and $and$ls180.v:6364$2156 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6364$2154_Y + connect \B $eq$ls180.v:6364$2155_Y + connect \Y $and$ls180.v:6364$2156_Y + end + attribute \src "ls180.v:6365.46-6365.104" + cell $and $and$ls180.v:6365$2158 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B $not$ls180.v:6365$2157_Y + connect \Y $and$ls180.v:6365$2158_Y + end + attribute \src "ls180.v:6365.45-6365.155" + cell $and $and$ls180.v:6365$2160 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6365$2158_Y + connect \B $eq$ls180.v:6365$2159_Y + connect \Y $and$ls180.v:6365$2160_Y + end + attribute \src "ls180.v:6367.44-6367.99" + cell $and $and$ls180.v:6367$2161 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B \builder_interface12_bank_bus_we + connect \Y $and$ls180.v:6367$2161_Y + end + attribute \src "ls180.v:6367.43-6367.150" + cell $and $and$ls180.v:6367$2163 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6367$2161_Y + connect \B $eq$ls180.v:6367$2162_Y + connect \Y $and$ls180.v:6367$2163_Y + end + attribute \src "ls180.v:6368.44-6368.102" + cell $and $and$ls180.v:6368$2165 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B $not$ls180.v:6368$2164_Y + connect \Y $and$ls180.v:6368$2165_Y + end + attribute \src "ls180.v:6368.43-6368.153" + cell $and $and$ls180.v:6368$2167 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6368$2165_Y + connect \B $eq$ls180.v:6368$2166_Y + connect \Y $and$ls180.v:6368$2167_Y + end + attribute \src "ls180.v:6370.41-6370.96" + cell $and $and$ls180.v:6370$2168 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B \builder_interface12_bank_bus_we + connect \Y $and$ls180.v:6370$2168_Y + end + attribute \src "ls180.v:6370.40-6370.147" + cell $and $and$ls180.v:6370$2170 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6370$2168_Y + connect \B $eq$ls180.v:6370$2169_Y + connect \Y $and$ls180.v:6370$2170_Y + end + attribute \src "ls180.v:6371.41-6371.99" + cell $and $and$ls180.v:6371$2172 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B $not$ls180.v:6371$2171_Y + connect \Y $and$ls180.v:6371$2172_Y + end + attribute \src "ls180.v:6371.40-6371.150" + cell $and $and$ls180.v:6371$2174 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6371$2172_Y + connect \B $eq$ls180.v:6371$2173_Y + connect \Y $and$ls180.v:6371$2174_Y + end + attribute \src "ls180.v:6373.40-6373.95" + cell $and $and$ls180.v:6373$2175 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B \builder_interface12_bank_bus_we + connect \Y $and$ls180.v:6373$2175_Y + end + attribute \src "ls180.v:6373.39-6373.146" + cell $and $and$ls180.v:6373$2177 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6373$2175_Y + connect \B $eq$ls180.v:6373$2176_Y + connect \Y $and$ls180.v:6373$2177_Y + end + attribute \src "ls180.v:6374.40-6374.98" + cell $and $and$ls180.v:6374$2179 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B $not$ls180.v:6374$2178_Y + connect \Y $and$ls180.v:6374$2179_Y + end + attribute \src "ls180.v:6374.39-6374.149" + cell $and $and$ls180.v:6374$2181 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6374$2179_Y + connect \B $eq$ls180.v:6374$2180_Y + connect \Y $and$ls180.v:6374$2181_Y + end + attribute \src "ls180.v:6386.46-6386.101" + cell $and $and$ls180.v:6386$2183 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank13_sel + connect \B \builder_interface13_bank_bus_we + connect \Y $and$ls180.v:6386$2183_Y + end + attribute \src "ls180.v:6386.45-6386.152" + cell $and $and$ls180.v:6386$2185 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6386$2183_Y + connect \B $eq$ls180.v:6386$2184_Y + connect \Y $and$ls180.v:6386$2185_Y + end + attribute \src "ls180.v:6387.46-6387.104" + cell $and $and$ls180.v:6387$2187 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank13_sel + connect \B $not$ls180.v:6387$2186_Y + connect \Y $and$ls180.v:6387$2187_Y + end + attribute \src "ls180.v:6387.45-6387.155" + cell $and $and$ls180.v:6387$2189 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6387$2187_Y + connect \B $eq$ls180.v:6387$2188_Y + connect \Y $and$ls180.v:6387$2189_Y + end + attribute \src "ls180.v:6389.46-6389.101" + cell $and $and$ls180.v:6389$2190 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank13_sel + connect \B \builder_interface13_bank_bus_we + connect \Y $and$ls180.v:6389$2190_Y + end + attribute \src "ls180.v:6389.45-6389.152" + cell $and $and$ls180.v:6389$2192 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6389$2190_Y + connect \B $eq$ls180.v:6389$2191_Y + connect \Y $and$ls180.v:6389$2192_Y + end + attribute \src "ls180.v:6390.46-6390.104" + cell $and $and$ls180.v:6390$2194 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank13_sel + connect \B $not$ls180.v:6390$2193_Y + connect \Y $and$ls180.v:6390$2194_Y + end + attribute \src "ls180.v:6390.45-6390.155" + cell $and $and$ls180.v:6390$2196 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6390$2194_Y + connect \B $eq$ls180.v:6390$2195_Y + connect \Y $and$ls180.v:6390$2196_Y + end + attribute \src "ls180.v:6392.46-6392.101" + cell $and $and$ls180.v:6392$2197 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank13_sel + connect \B \builder_interface13_bank_bus_we + connect \Y $and$ls180.v:6392$2197_Y + end + attribute \src "ls180.v:6392.45-6392.152" + cell $and $and$ls180.v:6392$2199 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6392$2197_Y + connect \B $eq$ls180.v:6392$2198_Y + connect \Y $and$ls180.v:6392$2199_Y + end + attribute \src "ls180.v:6393.46-6393.104" + cell $and $and$ls180.v:6393$2201 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank13_sel + connect \B $not$ls180.v:6393$2200_Y + connect \Y $and$ls180.v:6393$2201_Y + end + attribute \src "ls180.v:6393.45-6393.155" + cell $and $and$ls180.v:6393$2203 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6393$2201_Y + connect \B $eq$ls180.v:6393$2202_Y + connect \Y $and$ls180.v:6393$2203_Y + end + attribute \src "ls180.v:6395.46-6395.101" + cell $and $and$ls180.v:6395$2204 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank13_sel + connect \B \builder_interface13_bank_bus_we + connect \Y $and$ls180.v:6395$2204_Y + end + attribute \src "ls180.v:6395.45-6395.152" + cell $and $and$ls180.v:6395$2206 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6395$2204_Y + connect \B $eq$ls180.v:6395$2205_Y + connect \Y $and$ls180.v:6395$2206_Y + end + attribute \src "ls180.v:6396.46-6396.104" + cell $and $and$ls180.v:6396$2208 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank13_sel + connect \B $not$ls180.v:6396$2207_Y + connect \Y $and$ls180.v:6396$2208_Y + end + attribute \src "ls180.v:6396.45-6396.155" + cell $and $and$ls180.v:6396$2210 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6396$2208_Y + connect \B $eq$ls180.v:6396$2209_Y + connect \Y $and$ls180.v:6396$2210_Y + end + attribute \src "ls180.v:6774.109-6774.178" + cell $and $and$ls180.v:6774$2247 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank1_lock + connect \B $eq$ls180.v:6774$2246_Y + connect \Y $and$ls180.v:6774$2247_Y + end + attribute \src "ls180.v:6774.184-6774.253" + cell $and $and$ls180.v:6774$2250 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank2_lock + connect \B $eq$ls180.v:6774$2249_Y + connect \Y $and$ls180.v:6774$2250_Y + end + attribute \src "ls180.v:6774.259-6774.328" + cell $and $and$ls180.v:6774$2253 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank3_lock + connect \B $eq$ls180.v:6774$2252_Y + connect \Y $and$ls180.v:6774$2253_Y + end + attribute \src "ls180.v:6774.40-6774.331" + cell $and $and$ls180.v:6774$2256 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:6774$2245_Y + connect \B $not$ls180.v:6774$2255_Y + connect \Y $and$ls180.v:6774$2256_Y + end + attribute \src "ls180.v:6774.39-6774.354" + cell $and $and$ls180.v:6774$2257 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6774$2256_Y + connect \B \main_port_cmd_valid + connect \Y $and$ls180.v:6774$2257_Y + end + attribute \src "ls180.v:6798.109-6798.178" + cell $and $and$ls180.v:6798$2263 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank0_lock + connect \B $eq$ls180.v:6798$2262_Y + connect \Y $and$ls180.v:6798$2263_Y + end + attribute \src "ls180.v:6798.184-6798.253" + cell $and $and$ls180.v:6798$2266 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank2_lock + connect \B $eq$ls180.v:6798$2265_Y + connect \Y $and$ls180.v:6798$2266_Y + end + attribute \src "ls180.v:6798.259-6798.328" + cell $and $and$ls180.v:6798$2269 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank3_lock + connect \B $eq$ls180.v:6798$2268_Y + connect \Y $and$ls180.v:6798$2269_Y + end + attribute \src "ls180.v:6798.40-6798.331" + cell $and $and$ls180.v:6798$2272 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:6798$2261_Y + connect \B $not$ls180.v:6798$2271_Y + connect \Y $and$ls180.v:6798$2272_Y + end + attribute \src "ls180.v:6798.39-6798.354" + cell $and $and$ls180.v:6798$2273 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6798$2272_Y + connect \B \main_port_cmd_valid + connect \Y $and$ls180.v:6798$2273_Y + end + attribute \src "ls180.v:6822.109-6822.178" + cell $and $and$ls180.v:6822$2279 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank0_lock + connect \B $eq$ls180.v:6822$2278_Y + connect \Y $and$ls180.v:6822$2279_Y + end + attribute \src "ls180.v:6822.184-6822.253" + cell $and $and$ls180.v:6822$2282 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank1_lock + connect \B $eq$ls180.v:6822$2281_Y + connect \Y $and$ls180.v:6822$2282_Y + end + attribute \src "ls180.v:6822.259-6822.328" + cell $and $and$ls180.v:6822$2285 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank3_lock + connect \B $eq$ls180.v:6822$2284_Y + connect \Y $and$ls180.v:6822$2285_Y + end + attribute \src "ls180.v:6822.40-6822.331" + cell $and $and$ls180.v:6822$2288 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:6822$2277_Y + connect \B $not$ls180.v:6822$2287_Y + connect \Y $and$ls180.v:6822$2288_Y + end + attribute \src "ls180.v:6822.39-6822.354" + cell $and $and$ls180.v:6822$2289 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6822$2288_Y + connect \B \main_port_cmd_valid + connect \Y $and$ls180.v:6822$2289_Y + end + attribute \src "ls180.v:6846.109-6846.178" + cell $and $and$ls180.v:6846$2295 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank0_lock + connect \B $eq$ls180.v:6846$2294_Y + connect \Y $and$ls180.v:6846$2295_Y + end + attribute \src "ls180.v:6846.184-6846.253" + cell $and $and$ls180.v:6846$2298 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank1_lock + connect \B $eq$ls180.v:6846$2297_Y + connect \Y $and$ls180.v:6846$2298_Y + end + attribute \src "ls180.v:6846.259-6846.328" + cell $and $and$ls180.v:6846$2301 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank2_lock + connect \B $eq$ls180.v:6846$2300_Y + connect \Y $and$ls180.v:6846$2301_Y + end + attribute \src "ls180.v:6846.40-6846.331" + cell $and $and$ls180.v:6846$2304 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:6846$2293_Y + connect \B $not$ls180.v:6846$2303_Y + connect \Y $and$ls180.v:6846$2304_Y + end + attribute \src "ls180.v:6846.39-6846.354" + cell $and $and$ls180.v:6846$2305 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6846$2304_Y + connect \B \main_port_cmd_valid + connect \Y $and$ls180.v:6846$2305_Y + end + attribute \src "ls180.v:7051.39-7051.104" + cell $and $and$ls180.v:7051$2317 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:7051$2317_Y + end + attribute \src "ls180.v:7051.38-7051.145" + cell $and $and$ls180.v:7051$2318 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7051$2317_Y + connect \B \main_sdram_choose_req_cmd_payload_cas + connect \Y $and$ls180.v:7051$2318_Y + end + attribute \src "ls180.v:7054.39-7054.104" + cell $and $and$ls180.v:7054$2319 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:7054$2319_Y + end + attribute \src "ls180.v:7054.38-7054.145" + cell $and $and$ls180.v:7054$2320 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7054$2319_Y + connect \B \main_sdram_choose_req_cmd_payload_cas + connect \Y $and$ls180.v:7054$2320_Y + end + attribute \src "ls180.v:7057.39-7057.82" + cell $and $and$ls180.v:7057$2321 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_cmd_valid + connect \B \main_sdram_cmd_ready + connect \Y $and$ls180.v:7057$2321_Y + end + attribute \src "ls180.v:7057.38-7057.112" + cell $and $and$ls180.v:7057$2322 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7057$2321_Y + connect \B \main_sdram_cmd_payload_cas + connect \Y $and$ls180.v:7057$2322_Y + end + attribute \src "ls180.v:7068.39-7068.104" + cell $and $and$ls180.v:7068$2324 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:7068$2324_Y + end + attribute \src "ls180.v:7068.38-7068.145" + cell $and $and$ls180.v:7068$2325 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7068$2324_Y + connect \B \main_sdram_choose_req_cmd_payload_ras + connect \Y $and$ls180.v:7068$2325_Y + end + attribute \src "ls180.v:7071.39-7071.104" + cell $and $and$ls180.v:7071$2326 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:7071$2326_Y + end + attribute \src "ls180.v:7071.38-7071.145" + cell $and $and$ls180.v:7071$2327 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7071$2326_Y + connect \B \main_sdram_choose_req_cmd_payload_ras + connect \Y $and$ls180.v:7071$2327_Y + end + attribute \src "ls180.v:7074.39-7074.82" + cell $and $and$ls180.v:7074$2328 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_cmd_valid + connect \B \main_sdram_cmd_ready + connect \Y $and$ls180.v:7074$2328_Y + end + attribute \src "ls180.v:7074.38-7074.112" + cell $and $and$ls180.v:7074$2329 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7074$2328_Y + connect \B \main_sdram_cmd_payload_ras + connect \Y $and$ls180.v:7074$2329_Y + end + attribute \src "ls180.v:7085.39-7085.104" + cell $and $and$ls180.v:7085$2331 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:7085$2331_Y + end + attribute \src "ls180.v:7085.38-7085.144" + cell $and $and$ls180.v:7085$2332 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7085$2331_Y + connect \B \main_sdram_choose_req_cmd_payload_we + connect \Y $and$ls180.v:7085$2332_Y + end + attribute \src "ls180.v:7088.39-7088.104" + cell $and $and$ls180.v:7088$2333 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:7088$2333_Y + end + attribute \src "ls180.v:7088.38-7088.144" + cell $and $and$ls180.v:7088$2334 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7088$2333_Y + connect \B \main_sdram_choose_req_cmd_payload_we + connect \Y $and$ls180.v:7088$2334_Y + end + attribute \src "ls180.v:7091.39-7091.82" + cell $and $and$ls180.v:7091$2335 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_cmd_valid + connect \B \main_sdram_cmd_ready + connect \Y $and$ls180.v:7091$2335_Y + end + attribute \src "ls180.v:7091.38-7091.111" + cell $and $and$ls180.v:7091$2336 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7091$2335_Y + connect \B \main_sdram_cmd_payload_we + connect \Y $and$ls180.v:7091$2336_Y + end + attribute \src "ls180.v:7102.39-7102.104" + cell $and $and$ls180.v:7102$2338 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:7102$2338_Y + end + attribute \src "ls180.v:7102.38-7102.149" + cell $and $and$ls180.v:7102$2339 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7102$2338_Y + connect \B \main_sdram_choose_req_cmd_payload_is_read + connect \Y $and$ls180.v:7102$2339_Y + end + attribute \src "ls180.v:7105.39-7105.104" + cell $and $and$ls180.v:7105$2340 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:7105$2340_Y + end + attribute \src "ls180.v:7105.38-7105.149" + cell $and $and$ls180.v:7105$2341 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7105$2340_Y + connect \B \main_sdram_choose_req_cmd_payload_is_read + connect \Y $and$ls180.v:7105$2341_Y + end + attribute \src "ls180.v:7108.39-7108.82" + cell $and $and$ls180.v:7108$2342 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_cmd_valid + connect \B \main_sdram_cmd_ready + connect \Y $and$ls180.v:7108$2342_Y + end + attribute \src "ls180.v:7108.38-7108.116" + cell $and $and$ls180.v:7108$2343 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7108$2342_Y + connect \B \main_sdram_cmd_payload_is_read + connect \Y $and$ls180.v:7108$2343_Y + end + attribute \src "ls180.v:7119.39-7119.104" + cell $and $and$ls180.v:7119$2345 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:7119$2345_Y + end + attribute \src "ls180.v:7119.38-7119.150" + cell $and $and$ls180.v:7119$2346 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7119$2345_Y + connect \B \main_sdram_choose_req_cmd_payload_is_write + connect \Y $and$ls180.v:7119$2346_Y + end + attribute \src "ls180.v:7122.39-7122.104" + cell $and $and$ls180.v:7122$2347 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:7122$2347_Y + end + attribute \src "ls180.v:7122.38-7122.150" + cell $and $and$ls180.v:7122$2348 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7122$2347_Y + connect \B \main_sdram_choose_req_cmd_payload_is_write + connect \Y $and$ls180.v:7122$2348_Y + end + attribute \src "ls180.v:7125.39-7125.82" + cell $and $and$ls180.v:7125$2349 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_cmd_valid + connect \B \main_sdram_cmd_ready + connect \Y $and$ls180.v:7125$2349_Y + end + attribute \src "ls180.v:7125.38-7125.117" + cell $and $and$ls180.v:7125$2350 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7125$2349_Y + connect \B \main_sdram_cmd_payload_is_write + connect \Y $and$ls180.v:7125$2350_Y + end + attribute \src "ls180.v:7344.17-7344.67" + cell $and $and$ls180.v:7344$2357 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:7344$2356_Y + connect \B \main_sdphy_sdpads_clk + connect \Y $and$ls180.v:7344$2357_Y + end + attribute \src "ls180.v:7441.8-7441.67" + cell $and $and$ls180.v:7441$2406 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_ram_bus_cyc + connect \B \main_libresocsim_ram_bus_stb + connect \Y $and$ls180.v:7441$2406_Y + end + attribute \src "ls180.v:7441.7-7441.102" + cell $and $and$ls180.v:7441$2408 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7441$2406_Y + connect \B $not$ls180.v:7441$2407_Y + connect \Y $and$ls180.v:7441$2408_Y + end + attribute \src "ls180.v:7460.7-7460.75" + cell $and $and$ls180.v:7460$2412 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:7460$2411_Y + connect \B \main_libresocsim_zero_old_trigger + connect \Y $and$ls180.v:7460$2412_Y + end + attribute \src "ls180.v:7468.7-7468.56" + cell $and $and$ls180.v:7468$2414 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_timer_wait + connect \B $not$ls180.v:7468$2413_Y + connect \Y $and$ls180.v:7468$2414_Y + end + attribute \src "ls180.v:7496.7-7496.75" + cell $and $and$ls180.v:7496$2421 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_sequencer_start1 + connect \B $eq$ls180.v:7496$2420_Y + connect \Y $and$ls180.v:7496$2421_Y + end + attribute \src "ls180.v:7538.8-7538.131" + cell $and $and$ls180.v:7538$2427 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we + connect \B \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable + connect \Y $and$ls180.v:7538$2427_Y + end + attribute \src "ls180.v:7538.7-7538.190" + cell $and $and$ls180.v:7538$2429 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7538$2427_Y + connect \B $not$ls180.v:7538$2428_Y + connect \Y $and$ls180.v:7538$2429_Y + end + attribute \src "ls180.v:7544.8-7544.131" + cell $and $and$ls180.v:7544$2432 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we + connect \B \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable + connect \Y $and$ls180.v:7544$2432_Y + end + attribute \src "ls180.v:7544.7-7544.190" + cell $and $and$ls180.v:7544$2434 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7544$2432_Y + connect \B $not$ls180.v:7544$2433_Y + connect \Y $and$ls180.v:7544$2434_Y + end + attribute \src "ls180.v:7584.8-7584.131" + cell $and $and$ls180.v:7584$2443 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we + connect \B \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable + connect \Y $and$ls180.v:7584$2443_Y + end + attribute \src "ls180.v:7584.7-7584.190" + cell $and $and$ls180.v:7584$2445 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7584$2443_Y + connect \B $not$ls180.v:7584$2444_Y + connect \Y $and$ls180.v:7584$2445_Y + end + attribute \src "ls180.v:7590.8-7590.131" + cell $and $and$ls180.v:7590$2448 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we + connect \B \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable + connect \Y $and$ls180.v:7590$2448_Y + end + attribute \src "ls180.v:7590.7-7590.190" + cell $and $and$ls180.v:7590$2450 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7590$2448_Y + connect \B $not$ls180.v:7590$2449_Y + connect \Y $and$ls180.v:7590$2450_Y + end + attribute \src "ls180.v:7630.8-7630.131" + cell $and $and$ls180.v:7630$2459 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we + connect \B \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable + connect \Y $and$ls180.v:7630$2459_Y + end + attribute \src "ls180.v:7630.7-7630.190" + cell $and $and$ls180.v:7630$2461 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7630$2459_Y + connect \B $not$ls180.v:7630$2460_Y + connect \Y $and$ls180.v:7630$2461_Y + end + attribute \src "ls180.v:7636.8-7636.131" + cell $and $and$ls180.v:7636$2464 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we + connect \B \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable + connect \Y $and$ls180.v:7636$2464_Y + end + attribute \src "ls180.v:7636.7-7636.190" + cell $and $and$ls180.v:7636$2466 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7636$2464_Y + connect \B $not$ls180.v:7636$2465_Y + connect \Y $and$ls180.v:7636$2466_Y + end + attribute \src "ls180.v:7676.8-7676.131" + cell $and $and$ls180.v:7676$2475 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we + connect \B \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable + connect \Y $and$ls180.v:7676$2475_Y + end + attribute \src "ls180.v:7676.7-7676.190" + cell $and $and$ls180.v:7676$2477 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7676$2475_Y + connect \B $not$ls180.v:7676$2476_Y + connect \Y $and$ls180.v:7676$2477_Y + end + attribute \src "ls180.v:7682.8-7682.131" + cell $and $and$ls180.v:7682$2480 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we + connect \B \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable + connect \Y $and$ls180.v:7682$2480_Y + end + attribute \src "ls180.v:7682.7-7682.190" + cell $and $and$ls180.v:7682$2482 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7682$2480_Y + connect \B $not$ls180.v:7682$2481_Y + connect \Y $and$ls180.v:7682$2482_Y + end + attribute \src "ls180.v:7879.48-7879.124" + cell $and $and$ls180.v:7879$2507 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:7879$2506_Y + connect \B \main_sdram_interface_bank0_wdata_ready + connect \Y $and$ls180.v:7879$2507_Y + end + attribute \src "ls180.v:7879.130-7879.206" + cell $and $and$ls180.v:7879$2510 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:7879$2509_Y + connect \B \main_sdram_interface_bank1_wdata_ready + connect \Y $and$ls180.v:7879$2510_Y + end + attribute \src "ls180.v:7879.212-7879.288" + cell $and $and$ls180.v:7879$2513 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:7879$2512_Y + connect \B \main_sdram_interface_bank2_wdata_ready + connect \Y $and$ls180.v:7879$2513_Y + end + attribute \src "ls180.v:7879.294-7879.370" + cell $and $and$ls180.v:7879$2516 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:7879$2515_Y + connect \B \main_sdram_interface_bank3_wdata_ready + connect \Y $and$ls180.v:7879$2516_Y + end + attribute \src "ls180.v:7880.49-7880.125" + cell $and $and$ls180.v:7880$2519 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:7880$2518_Y + connect \B \main_sdram_interface_bank0_rdata_valid + connect \Y $and$ls180.v:7880$2519_Y + end + attribute \src "ls180.v:7880.131-7880.207" + cell $and $and$ls180.v:7880$2522 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:7880$2521_Y + connect \B \main_sdram_interface_bank1_rdata_valid + connect \Y $and$ls180.v:7880$2522_Y + end + attribute \src "ls180.v:7880.213-7880.289" + cell $and $and$ls180.v:7880$2525 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:7880$2524_Y + connect \B \main_sdram_interface_bank2_rdata_valid + connect \Y $and$ls180.v:7880$2525_Y + end + attribute \src "ls180.v:7880.295-7880.371" + cell $and $and$ls180.v:7880$2528 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:7880$2527_Y + connect \B \main_sdram_interface_bank3_rdata_valid + connect \Y $and$ls180.v:7880$2528_Y + end + attribute \src "ls180.v:7899.8-7899.49" + cell $and $and$ls180.v:7899$2531 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_valid + connect \B \main_port_cmd_ready + connect \Y $and$ls180.v:7899$2531_Y + end + attribute \src "ls180.v:7902.8-7902.53" + cell $and $and$ls180.v:7902$2532 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_port_wdata_valid + connect \B \main_port_wdata_ready + connect \Y $and$ls180.v:7902$2532_Y + end + attribute \src "ls180.v:7907.8-7907.41" + cell $and $and$ls180.v:7907$2534 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sink_valid + connect \B $not$ls180.v:7907$2533_Y + connect \Y $and$ls180.v:7907$2534_Y + end + attribute \src "ls180.v:7907.7-7907.63" + cell $and $and$ls180.v:7907$2536 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7907$2534_Y + connect \B $not$ls180.v:7907$2535_Y + connect \Y $and$ls180.v:7907$2536_Y + end + attribute \src "ls180.v:7913.8-7913.41" + cell $and $and$ls180.v:7913$2537 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_clk_txen + connect \B \main_tx_busy + connect \Y $and$ls180.v:7913$2537_Y + end + attribute \src "ls180.v:7937.8-7937.30" + cell $and $and$ls180.v:7937$2544 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:7937$2543_Y + connect \B \main_rx_r + connect \Y $and$ls180.v:7937$2544_Y + end + attribute \src "ls180.v:7970.7-7970.57" + cell $and $and$ls180.v:7970$2550 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:7970$2549_Y + connect \B \main_uart_tx_old_trigger + connect \Y $and$ls180.v:7970$2550_Y + end + attribute \src "ls180.v:7977.7-7977.57" + cell $and $and$ls180.v:7977$2552 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:7977$2551_Y + connect \B \main_uart_rx_old_trigger + connect \Y $and$ls180.v:7977$2552_Y + end + attribute \src "ls180.v:7987.8-7987.75" + cell $and $and$ls180.v:7987$2553 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_tx_fifo_syncfifo_we + connect \B \main_uart_tx_fifo_syncfifo_writable + connect \Y $and$ls180.v:7987$2553_Y + end + attribute \src "ls180.v:7987.7-7987.107" + cell $and $and$ls180.v:7987$2555 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7987$2553_Y + connect \B $not$ls180.v:7987$2554_Y + connect \Y $and$ls180.v:7987$2555_Y + end + attribute \src "ls180.v:7993.8-7993.75" + cell $and $and$ls180.v:7993$2558 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_tx_fifo_syncfifo_we + connect \B \main_uart_tx_fifo_syncfifo_writable + connect \Y $and$ls180.v:7993$2558_Y + end + attribute \src "ls180.v:7993.7-7993.107" + cell $and $and$ls180.v:7993$2560 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7993$2558_Y + connect \B $not$ls180.v:7993$2559_Y + connect \Y $and$ls180.v:7993$2560_Y + end + attribute \src "ls180.v:8009.8-8009.75" + cell $and $and$ls180.v:8009$2564 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_rx_fifo_syncfifo_we + connect \B \main_uart_rx_fifo_syncfifo_writable + connect \Y $and$ls180.v:8009$2564_Y + end + attribute \src "ls180.v:8009.7-8009.107" + cell $and $and$ls180.v:8009$2566 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:8009$2564_Y + connect \B $not$ls180.v:8009$2565_Y + connect \Y $and$ls180.v:8009$2566_Y + end + attribute \src "ls180.v:8015.8-8015.75" + cell $and $and$ls180.v:8015$2569 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_rx_fifo_syncfifo_we + connect \B \main_uart_rx_fifo_syncfifo_writable + connect \Y $and$ls180.v:8015$2569_Y + end + attribute \src "ls180.v:8015.7-8015.107" + cell $and $and$ls180.v:8015$2571 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:8015$2569_Y + connect \B $not$ls180.v:8015$2570_Y + connect \Y $and$ls180.v:8015$2571_Y + end + attribute \src "ls180.v:8128.7-8128.96" + cell $and $and$ls180.v:8128$2594 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_cmdr_converter_source_valid + connect \B \main_sdphy_cmdr_cmdr_converter_source_ready + connect \Y $and$ls180.v:8128$2594_Y + end + attribute \src "ls180.v:8129.8-8129.93" + cell $and $and$ls180.v:8129$2595 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_cmdr_converter_sink_valid + connect \B \main_sdphy_cmdr_cmdr_converter_sink_ready + connect \Y $and$ls180.v:8129$2595_Y + end + attribute \src "ls180.v:8137.8-8137.93" + cell $and $and$ls180.v:8137$2596 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_cmdr_converter_sink_valid + connect \B \main_sdphy_cmdr_cmdr_converter_sink_ready + connect \Y $and$ls180.v:8137$2596_Y + end + attribute \src "ls180.v:8209.7-8209.98" + cell $and $and$ls180.v:8209$2606 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_crcr_converter_source_valid + connect \B \main_sdphy_dataw_crcr_converter_source_ready + connect \Y $and$ls180.v:8209$2606_Y + end + attribute \src "ls180.v:8210.8-8210.95" + cell $and $and$ls180.v:8210$2607 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_crcr_converter_sink_valid + connect \B \main_sdphy_dataw_crcr_converter_sink_ready + connect \Y $and$ls180.v:8210$2607_Y + end + attribute \src "ls180.v:8218.8-8218.95" + cell $and $and$ls180.v:8218$2608 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_crcr_converter_sink_valid + connect \B \main_sdphy_dataw_crcr_converter_sink_ready + connect \Y $and$ls180.v:8218$2608_Y + end + attribute \src "ls180.v:8288.7-8288.100" + cell $and $and$ls180.v:8288$2618 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_datar_converter_source_valid + connect \B \main_sdphy_datar_datar_converter_source_ready + connect \Y $and$ls180.v:8288$2618_Y + end + attribute \src "ls180.v:8289.8-8289.97" + cell $and $and$ls180.v:8289$2619 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_datar_converter_sink_valid + connect \B \main_sdphy_datar_datar_converter_sink_ready + connect \Y $and$ls180.v:8289$2619_Y + end + attribute \src "ls180.v:8297.8-8297.97" + cell $and $and$ls180.v:8297$2620 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_datar_converter_sink_valid + connect \B \main_sdphy_datar_datar_converter_sink_ready + connect \Y $and$ls180.v:8297$2620_Y + end + attribute \src "ls180.v:8388.7-8388.82" + cell $and $and$ls180.v:8388$2626 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_sink_ready + connect \B \main_sdcore_crc16_checker_sink_valid + connect \Y $and$ls180.v:8388$2626_Y + end + attribute \src "ls180.v:8391.7-8391.82" + cell $and $and$ls180.v:8391$2627 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_sink_ready + connect \B \main_sdcore_crc16_checker_sink_valid + connect \Y $and$ls180.v:8391$2627_Y + end + attribute \src "ls180.v:8394.7-8394.82" + cell $and $and$ls180.v:8394$2628 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_sink_ready + connect \B \main_sdcore_crc16_checker_sink_valid + connect \Y $and$ls180.v:8394$2628_Y + end + attribute \src "ls180.v:8397.7-8397.82" + cell $and $and$ls180.v:8397$2629 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_sink_ready + connect \B \main_sdcore_crc16_checker_sink_valid + connect \Y $and$ls180.v:8397$2629_Y + end + attribute \src "ls180.v:8400.7-8400.82" + cell $and $and$ls180.v:8400$2630 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_sink_valid + connect \B \main_sdcore_crc16_checker_sink_ready + connect \Y $and$ls180.v:8400$2630_Y + end + attribute \src "ls180.v:8405.7-8405.82" + cell $and $and$ls180.v:8405$2631 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_sink_valid + connect \B \main_sdcore_crc16_checker_sink_ready + connect \Y $and$ls180.v:8405$2631_Y + end + attribute \src "ls180.v:8410.7-8410.82" + cell $and $and$ls180.v:8410$2632 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_sink_valid + connect \B \main_sdcore_crc16_checker_sink_ready + connect \Y $and$ls180.v:8410$2632_Y + end + attribute \src "ls180.v:8415.7-8415.82" + cell $and $and$ls180.v:8415$2633 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_sink_valid + connect \B \main_sdcore_crc16_checker_sink_ready + connect \Y $and$ls180.v:8415$2633_Y + end + attribute \src "ls180.v:8420.7-8420.82" + cell $and $and$ls180.v:8420$2634 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_sink_valid + connect \B \main_sdcore_crc16_checker_sink_ready + connect \Y $and$ls180.v:8420$2634_Y + end + attribute \src "ls180.v:8485.8-8485.83" + cell $and $and$ls180.v:8485$2637 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_fifo_syncfifo_we + connect \B \main_sdblock2mem_fifo_syncfifo_writable + connect \Y $and$ls180.v:8485$2637_Y + end + attribute \src "ls180.v:8485.7-8485.119" + cell $and $and$ls180.v:8485$2639 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:8485$2637_Y + connect \B $not$ls180.v:8485$2638_Y + connect \Y $and$ls180.v:8485$2639_Y + end + attribute \src "ls180.v:8491.8-8491.83" + cell $and $and$ls180.v:8491$2642 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_fifo_syncfifo_we + connect \B \main_sdblock2mem_fifo_syncfifo_writable + connect \Y $and$ls180.v:8491$2642_Y + end + attribute \src "ls180.v:8491.7-8491.119" + cell $and $and$ls180.v:8491$2644 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:8491$2642_Y + connect \B $not$ls180.v:8491$2643_Y + connect \Y $and$ls180.v:8491$2644_Y + end + attribute \src "ls180.v:8511.7-8511.88" + cell $and $and$ls180.v:8511$2651 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_converter_source_valid + connect \B \main_sdblock2mem_converter_source_ready + connect \Y $and$ls180.v:8511$2651_Y + end + attribute \src "ls180.v:8512.8-8512.85" + cell $and $and$ls180.v:8512$2652 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_converter_sink_valid + connect \B \main_sdblock2mem_converter_sink_ready + connect \Y $and$ls180.v:8512$2652_Y + end + attribute \src "ls180.v:8520.8-8520.85" + cell $and $and$ls180.v:8520$2653 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_converter_sink_valid + connect \B \main_sdblock2mem_converter_sink_ready + connect \Y $and$ls180.v:8520$2653_Y + end + attribute \src "ls180.v:8564.7-8564.88" + cell $and $and$ls180.v:8564$2657 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_converter_source_valid + connect \B \main_sdmem2block_converter_source_ready + connect \Y $and$ls180.v:8564$2657_Y + end + attribute \src "ls180.v:8571.8-8571.83" + cell $and $and$ls180.v:8571$2659 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_fifo_syncfifo_we + connect \B \main_sdmem2block_fifo_syncfifo_writable + connect \Y $and$ls180.v:8571$2659_Y + end + attribute \src "ls180.v:8571.7-8571.119" + cell $and $and$ls180.v:8571$2661 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:8571$2659_Y + connect \B $not$ls180.v:8571$2660_Y + connect \Y $and$ls180.v:8571$2661_Y + end + attribute \src "ls180.v:8577.8-8577.83" + cell $and $and$ls180.v:8577$2664 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_fifo_syncfifo_we + connect \B \main_sdmem2block_fifo_syncfifo_writable + connect \Y $and$ls180.v:8577$2664_Y + end + attribute \src "ls180.v:8577.7-8577.119" + cell $and $and$ls180.v:8577$2666 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:8577$2664_Y + connect \B $not$ls180.v:8577$2665_Y + connect \Y $and$ls180.v:8577$2666_Y + end + attribute \src "ls180.v:2763.42-2763.101" + cell $eq $eq$ls180.v:2763$18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_interface0_converted_interface_sel + connect \B 1'0 + connect \Y $eq$ls180.v:2763$18_Y + end + attribute \src "ls180.v:2770.11-2770.54" + cell $eq $eq$ls180.v:2770$23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_converter0_counter + connect \B 1'1 + connect \Y $eq$ls180.v:2770$23_Y + end + attribute \src "ls180.v:2823.42-2823.101" + cell $eq $eq$ls180.v:2823$29 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_interface1_converted_interface_sel + connect \B 1'0 + connect \Y $eq$ls180.v:2823$29_Y + end + attribute \src "ls180.v:2830.11-2830.54" + cell $eq $eq$ls180.v:2830$34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_converter1_counter + connect \B 1'1 + connect \Y $eq$ls180.v:2830$34_Y + end + attribute \src "ls180.v:2883.42-2883.101" + cell $eq $eq$ls180.v:2883$40 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_interface2_converted_interface_sel + connect \B 1'0 + connect \Y $eq$ls180.v:2883$40_Y + end + attribute \src "ls180.v:2890.11-2890.54" + cell $eq $eq$ls180.v:2890$45 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_converter2_counter + connect \B 1'1 + connect \Y $eq$ls180.v:2890$45_Y + end + attribute \src "ls180.v:3076.34-3076.65" + cell $eq $eq$ls180.v:3076$73 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_timer_count1 + connect \B 1'0 + connect \Y $eq$ls180.v:3076$73_Y + end + attribute \src "ls180.v:3080.68-3080.102" + cell $eq $eq$ls180.v:3080$76 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_sequencer_count + connect \B 1'0 + connect \Y $eq$ls180.v:3080$76_Y + end + attribute \src "ls180.v:3124.43-3124.134" + cell $eq $eq$ls180.v:3124$81 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_row + connect \B \main_sdram_bankmachine0_cmd_buffer_source_payload_addr [21:9] + connect \Y $eq$ls180.v:3124$81_Y + end + attribute \src "ls180.v:3141.47-3141.88" + cell $eq $eq$ls180.v:3141$94 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_row_close + connect \B 1'0 + connect \Y $eq$ls180.v:3141$94_Y + end + attribute \src "ls180.v:3281.43-3281.134" + cell $eq $eq$ls180.v:3281$111 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_row + connect \B \main_sdram_bankmachine1_cmd_buffer_source_payload_addr [21:9] + connect \Y $eq$ls180.v:3281$111_Y + end + attribute \src "ls180.v:3298.47-3298.88" + cell $eq $eq$ls180.v:3298$124 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_row_close + connect \B 1'0 + connect \Y $eq$ls180.v:3298$124_Y + end + attribute \src "ls180.v:3438.43-3438.134" + cell $eq $eq$ls180.v:3438$141 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_row + connect \B \main_sdram_bankmachine2_cmd_buffer_source_payload_addr [21:9] + connect \Y $eq$ls180.v:3438$141_Y + end + attribute \src "ls180.v:3455.47-3455.88" + cell $eq $eq$ls180.v:3455$154 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_row_close + connect \B 1'0 + connect \Y $eq$ls180.v:3455$154_Y + end + attribute \src "ls180.v:3595.43-3595.134" + cell $eq $eq$ls180.v:3595$171 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_row + connect \B \main_sdram_bankmachine3_cmd_buffer_source_payload_addr [21:9] + connect \Y $eq$ls180.v:3595$171_Y + end + attribute \src "ls180.v:3612.47-3612.88" + cell $eq $eq$ls180.v:3612$184 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_row_close + connect \B 1'0 + connect \Y $eq$ls180.v:3612$184_Y + end + attribute \src "ls180.v:3749.32-3749.56" + cell $eq $eq$ls180.v:3749$231 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_time0 + connect \B 1'0 + connect \Y $eq$ls180.v:3749$231_Y + end + attribute \src "ls180.v:3750.32-3750.56" + cell $eq $eq$ls180.v:3750$232 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_time1 + connect \B 1'0 + connect \Y $eq$ls180.v:3750$232_Y + end + attribute \src "ls180.v:3761.339-3761.418" + cell $eq $eq$ls180.v:3761$246 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_payload_is_read + connect \B \main_sdram_choose_cmd_want_reads + connect \Y $eq$ls180.v:3761$246_Y + end + attribute \src "ls180.v:3761.423-3761.504" + cell $eq $eq$ls180.v:3761$247 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_payload_is_write + connect \B \main_sdram_choose_cmd_want_writes + connect \Y $eq$ls180.v:3761$247_Y + end + attribute \src "ls180.v:3762.339-3762.418" + cell $eq $eq$ls180.v:3762$259 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_payload_is_read + connect \B \main_sdram_choose_cmd_want_reads + connect \Y $eq$ls180.v:3762$259_Y + end + attribute \src "ls180.v:3762.423-3762.504" + cell $eq $eq$ls180.v:3762$260 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_payload_is_write + connect \B \main_sdram_choose_cmd_want_writes + connect \Y $eq$ls180.v:3762$260_Y + end + attribute \src "ls180.v:3763.339-3763.418" + cell $eq $eq$ls180.v:3763$272 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_payload_is_read + connect \B \main_sdram_choose_cmd_want_reads + connect \Y $eq$ls180.v:3763$272_Y + end + attribute \src "ls180.v:3763.423-3763.504" + cell $eq $eq$ls180.v:3763$273 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_payload_is_write + connect \B \main_sdram_choose_cmd_want_writes + connect \Y $eq$ls180.v:3763$273_Y + end + attribute \src "ls180.v:3764.339-3764.418" + cell $eq $eq$ls180.v:3764$285 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_payload_is_read + connect \B \main_sdram_choose_cmd_want_reads + connect \Y $eq$ls180.v:3764$285_Y + end + attribute \src "ls180.v:3764.423-3764.504" + cell $eq $eq$ls180.v:3764$286 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_payload_is_write + connect \B \main_sdram_choose_cmd_want_writes + connect \Y $eq$ls180.v:3764$286_Y + end + attribute \src "ls180.v:3794.339-3794.418" + cell $eq $eq$ls180.v:3794$304 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_payload_is_read + connect \B \main_sdram_choose_req_want_reads + connect \Y $eq$ls180.v:3794$304_Y + end + attribute \src "ls180.v:3794.423-3794.504" + cell $eq $eq$ls180.v:3794$305 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_payload_is_write + connect \B \main_sdram_choose_req_want_writes + connect \Y $eq$ls180.v:3794$305_Y + end + attribute \src "ls180.v:3795.339-3795.418" + cell $eq $eq$ls180.v:3795$317 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_payload_is_read + connect \B \main_sdram_choose_req_want_reads + connect \Y $eq$ls180.v:3795$317_Y + end + attribute \src "ls180.v:3795.423-3795.504" + cell $eq $eq$ls180.v:3795$318 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_payload_is_write + connect \B \main_sdram_choose_req_want_writes + connect \Y $eq$ls180.v:3795$318_Y + end + attribute \src "ls180.v:3796.339-3796.418" + cell $eq $eq$ls180.v:3796$330 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_payload_is_read + connect \B \main_sdram_choose_req_want_reads + connect \Y $eq$ls180.v:3796$330_Y + end + attribute \src "ls180.v:3796.423-3796.504" + cell $eq $eq$ls180.v:3796$331 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_payload_is_write + connect \B \main_sdram_choose_req_want_writes + connect \Y $eq$ls180.v:3796$331_Y + end + attribute \src "ls180.v:3797.339-3797.418" + cell $eq $eq$ls180.v:3797$343 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_payload_is_read + connect \B \main_sdram_choose_req_want_reads + connect \Y $eq$ls180.v:3797$343_Y + end + attribute \src "ls180.v:3797.423-3797.504" + cell $eq $eq$ls180.v:3797$344 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_payload_is_write + connect \B \main_sdram_choose_req_want_writes + connect \Y $eq$ls180.v:3797$344_Y + end + attribute \src "ls180.v:3826.78-3826.113" + cell $eq $eq$ls180.v:3826$353 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_cmd_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3826$353_Y + end + attribute \src "ls180.v:3829.78-3829.113" + cell $eq $eq$ls180.v:3829$356 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3829$356_Y + end + attribute \src "ls180.v:3835.78-3835.113" + cell $eq $eq$ls180.v:3835$360 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_cmd_grant + connect \B 1'1 + connect \Y $eq$ls180.v:3835$360_Y + end + attribute \src "ls180.v:3838.78-3838.113" + cell $eq $eq$ls180.v:3838$363 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_grant + connect \B 1'1 + connect \Y $eq$ls180.v:3838$363_Y + end + attribute \src "ls180.v:3844.78-3844.113" + cell $eq $eq$ls180.v:3844$367 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_cmd_grant + connect \B 2'10 + connect \Y $eq$ls180.v:3844$367_Y + end + attribute \src "ls180.v:3847.78-3847.113" + cell $eq $eq$ls180.v:3847$370 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_grant + connect \B 2'10 + connect \Y $eq$ls180.v:3847$370_Y + end + attribute \src "ls180.v:3853.78-3853.113" + cell $eq $eq$ls180.v:3853$374 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_cmd_grant + connect \B 2'11 + connect \Y $eq$ls180.v:3853$374_Y + end + attribute \src "ls180.v:3856.78-3856.113" + cell $eq $eq$ls180.v:3856$377 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_grant + connect \B 2'11 + connect \Y $eq$ls180.v:3856$377_Y + end + attribute \src "ls180.v:3937.42-3937.82" + cell $eq $eq$ls180.v:3937$400 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_payload_addr [10:9] + connect \B 1'0 + connect \Y $eq$ls180.v:3937$400_Y + end + attribute \src "ls180.v:3937.145-3937.178" + cell $eq $eq$ls180.v:3937$401 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin1_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3937$401_Y + end + attribute \src "ls180.v:3937.220-3937.253" + cell $eq $eq$ls180.v:3937$404 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin2_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3937$404_Y + end + attribute \src "ls180.v:3937.295-3937.328" + cell $eq $eq$ls180.v:3937$407 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin3_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3937$407_Y + end + attribute \src "ls180.v:3942.42-3942.82" + cell $eq $eq$ls180.v:3942$416 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_payload_addr [10:9] + connect \B 1'1 + connect \Y $eq$ls180.v:3942$416_Y + end + attribute \src "ls180.v:3942.145-3942.178" + cell $eq $eq$ls180.v:3942$417 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin0_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3942$417_Y + end + attribute \src "ls180.v:3942.220-3942.253" + cell $eq $eq$ls180.v:3942$420 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin2_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3942$420_Y + end + attribute \src "ls180.v:3942.295-3942.328" + cell $eq $eq$ls180.v:3942$423 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin3_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3942$423_Y + end + attribute \src "ls180.v:3947.42-3947.82" + cell $eq $eq$ls180.v:3947$432 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_payload_addr [10:9] + connect \B 2'10 + connect \Y $eq$ls180.v:3947$432_Y + end + attribute \src "ls180.v:3947.145-3947.178" + cell $eq $eq$ls180.v:3947$433 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin0_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3947$433_Y + end + attribute \src "ls180.v:3947.220-3947.253" + cell $eq $eq$ls180.v:3947$436 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin1_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3947$436_Y + end + attribute \src "ls180.v:3947.295-3947.328" + cell $eq $eq$ls180.v:3947$439 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin3_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3947$439_Y + end + attribute \src "ls180.v:3952.42-3952.82" + cell $eq $eq$ls180.v:3952$448 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_payload_addr [10:9] + connect \B 2'11 + connect \Y $eq$ls180.v:3952$448_Y + end + attribute \src "ls180.v:3952.145-3952.178" + cell $eq $eq$ls180.v:3952$449 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin0_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3952$449_Y + end + attribute \src "ls180.v:3952.220-3952.253" + cell $eq $eq$ls180.v:3952$452 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin1_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3952$452_Y + end + attribute \src "ls180.v:3952.295-3952.328" + cell $eq $eq$ls180.v:3952$455 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin2_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3952$455_Y + end + attribute \src "ls180.v:3957.44-3957.77" + cell $eq $eq$ls180.v:3957$464 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin0_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3957$464_Y + end + attribute \src "ls180.v:3957.83-3957.123" + cell $eq $eq$ls180.v:3957$465 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_payload_addr [10:9] + connect \B 1'0 + connect \Y $eq$ls180.v:3957$465_Y + end + attribute \src "ls180.v:3957.186-3957.219" + cell $eq $eq$ls180.v:3957$466 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin1_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3957$466_Y + end + attribute \src "ls180.v:3957.261-3957.294" + cell $eq $eq$ls180.v:3957$469 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin2_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3957$469_Y + end + attribute \src "ls180.v:3957.336-3957.369" + cell $eq $eq$ls180.v:3957$472 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin3_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3957$472_Y + end + attribute \src "ls180.v:3957.418-3957.451" + cell $eq $eq$ls180.v:3957$480 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin1_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3957$480_Y + end + attribute \src "ls180.v:3957.457-3957.497" + cell $eq $eq$ls180.v:3957$481 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_payload_addr [10:9] + connect \B 1'1 + connect \Y $eq$ls180.v:3957$481_Y + end + attribute \src "ls180.v:3957.560-3957.593" + cell $eq $eq$ls180.v:3957$482 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin0_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3957$482_Y + end + attribute \src "ls180.v:3957.635-3957.668" + cell $eq $eq$ls180.v:3957$485 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin2_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3957$485_Y + end + attribute \src "ls180.v:3957.710-3957.743" + cell $eq $eq$ls180.v:3957$488 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin3_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3957$488_Y + end + attribute \src "ls180.v:3957.792-3957.825" + cell $eq $eq$ls180.v:3957$496 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin2_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3957$496_Y + end + attribute \src "ls180.v:3957.831-3957.871" + cell $eq $eq$ls180.v:3957$497 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_payload_addr [10:9] + connect \B 2'10 + connect \Y $eq$ls180.v:3957$497_Y + end + attribute \src "ls180.v:3957.934-3957.967" + cell $eq $eq$ls180.v:3957$498 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin0_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3957$498_Y + end + attribute \src "ls180.v:3957.1009-3957.1042" + cell $eq $eq$ls180.v:3957$501 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin1_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3957$501_Y + end + attribute \src "ls180.v:3957.1084-3957.1117" + cell $eq $eq$ls180.v:3957$504 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin3_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3957$504_Y + end + attribute \src "ls180.v:3957.1166-3957.1199" + cell $eq $eq$ls180.v:3957$512 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin3_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3957$512_Y + end + attribute \src "ls180.v:3957.1205-3957.1245" + cell $eq $eq$ls180.v:3957$513 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_payload_addr [10:9] + connect \B 2'11 + connect \Y $eq$ls180.v:3957$513_Y + end + attribute \src "ls180.v:3957.1308-3957.1341" + cell $eq $eq$ls180.v:3957$514 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin0_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3957$514_Y + end + attribute \src "ls180.v:3957.1383-3957.1416" + cell $eq $eq$ls180.v:3957$517 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin1_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3957$517_Y + end + attribute \src "ls180.v:3957.1458-3957.1491" + cell $eq $eq$ls180.v:3957$520 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin2_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3957$520_Y + end + attribute \src "ls180.v:4016.29-4016.57" + cell $eq $eq$ls180.v:4016$533 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_litedram_wb_sel + connect \B 1'0 + connect \Y $eq$ls180.v:4016$533_Y + end + attribute \src "ls180.v:4023.11-4023.41" + cell $eq $eq$ls180.v:4023$538 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_converter_counter + connect \B 1'1 + connect \Y $eq$ls180.v:4023$538_Y + end + attribute \src "ls180.v:4180.36-4180.111" + cell $eq $eq$ls180.v:4180$603 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 16 + parameter \Y_WIDTH 1 + connect \A \main_spi_master_clk_divider1 + connect \B $sub$ls180.v:4180$602_Y + connect \Y $eq$ls180.v:4180$603_Y + end + attribute \src "ls180.v:4181.36-4181.105" + cell $eq $eq$ls180.v:4181$605 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 16 + parameter \Y_WIDTH 1 + connect \A \main_spi_master_clk_divider1 + connect \B $sub$ls180.v:4181$604_Y + connect \Y $eq$ls180.v:4181$605_Y + end + attribute \src "ls180.v:4208.10-4208.67" + cell $eq $eq$ls180.v:4208$609 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \main_spi_master_count + connect \B $sub$ls180.v:4208$608_Y + connect \Y $eq$ls180.v:4208$609_Y + end + attribute \src "ls180.v:4308.10-4308.40" + cell $eq $eq$ls180.v:4308$636 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_init_count + connect \B 7'1001111 + connect \Y $eq$ls180.v:4308$636_Y + end + attribute \src "ls180.v:4365.10-4365.39" + cell $eq $eq$ls180.v:4365$639 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdw_count + connect \B 3'111 + connect \Y $eq$ls180.v:4365$639_Y + end + attribute \src "ls180.v:4382.10-4382.39" + cell $eq $eq$ls180.v:4382$641 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdw_count + connect \B 3'111 + connect \Y $eq$ls180.v:4382$641_Y + end + attribute \src "ls180.v:4410.38-4410.88" + cell $eq $eq$ls180.v:4410$643 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_i + connect \B 1'0 + connect \Y $eq$ls180.v:4410$643_Y + end + attribute \src "ls180.v:4460.9-4460.40" + cell $eq $eq$ls180.v:4460$653 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_timeout + connect \B 1'0 + connect \Y $eq$ls180.v:4460$653_Y + end + attribute \src "ls180.v:4469.36-4469.105" + cell $eq $eq$ls180.v:4469$655 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_count + connect \B $sub$ls180.v:4469$654_Y + connect \Y $eq$ls180.v:4469$655_Y + end + attribute \src "ls180.v:4488.9-4488.40" + cell $eq $eq$ls180.v:4488$659 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_timeout + connect \B 1'0 + connect \Y $eq$ls180.v:4488$659_Y + end + attribute \src "ls180.v:4500.10-4500.39" + cell $eq $eq$ls180.v:4500$661 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_count + connect \B 3'111 + connect \Y $eq$ls180.v:4500$661_Y + end + attribute \src "ls180.v:4537.39-4537.94" + cell $eq $eq$ls180.v:4537$665 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_crcr_pads_in_payload_data_i [0] + connect \B 1'0 + connect \Y $eq$ls180.v:4537$665_Y + end + attribute \src "ls180.v:4574.32-4574.89" + cell $eq $eq$ls180.v:4574$674 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_crcr_source_source_payload_data0 + connect \B 3'101 + connect \Y $eq$ls180.v:4574$674_Y + end + attribute \src "ls180.v:4622.10-4622.40" + cell $eq $eq$ls180.v:4622$678 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_count + connect \B 1'1 + connect \Y $eq$ls180.v:4622$678_Y + end + attribute \src "ls180.v:4671.40-4671.98" + cell $eq $eq$ls180.v:4671$680 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_datar_pads_in_payload_data_i + connect \B 1'0 + connect \Y $eq$ls180.v:4671$680_Y + end + attribute \src "ls180.v:4722.9-4722.41" + cell $eq $eq$ls180.v:4722$690 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_timeout + connect \B 1'0 + connect \Y $eq$ls180.v:4722$690_Y + end + attribute \src "ls180.v:4731.37-4731.123" + cell $eq $eq$ls180.v:4731$693 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 10 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_count + connect \B $sub$ls180.v:4731$692_Y + connect \Y $eq$ls180.v:4731$693_Y + end + attribute \src "ls180.v:4754.9-4754.41" + cell $eq $eq$ls180.v:4754$696 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_timeout + connect \B 1'0 + connect \Y $eq$ls180.v:4754$696_Y + end + attribute \src "ls180.v:4764.10-4764.41" + cell $eq $eq$ls180.v:4764$698 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_count + connect \B 6'100111 + connect \Y $eq$ls180.v:4764$698_Y + end + attribute \src "ls180.v:4933.9-4933.47" + cell $eq $eq$ls180.v:4933$880 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_cnt + connect \B 3'111 + connect \Y $eq$ls180.v:4933$880_Y + end + attribute \src "ls180.v:4963.10-4963.48" + cell $eq $eq$ls180.v:4963$881 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_cnt + connect \B 3'111 + connect \Y $eq$ls180.v:4963$881_Y + end + attribute \src "ls180.v:4994.10-4994.78" + cell $eq $eq$ls180.v:4994$886 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 16 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_fifo0 + connect \B \main_sdcore_crc16_checker_crctmp0 + connect \Y $eq$ls180.v:4994$886_Y + end + attribute \src "ls180.v:4994.83-4994.151" + cell $eq $eq$ls180.v:4994$887 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 16 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_fifo1 + connect \B \main_sdcore_crc16_checker_crctmp1 + connect \Y $eq$ls180.v:4994$887_Y + end + attribute \src "ls180.v:4994.157-4994.225" + cell $eq $eq$ls180.v:4994$889 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 16 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_fifo2 + connect \B \main_sdcore_crc16_checker_crctmp2 + connect \Y $eq$ls180.v:4994$889_Y + end + attribute \src "ls180.v:4994.231-4994.299" + cell $eq $eq$ls180.v:4994$891 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 16 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_fifo3 + connect \B \main_sdcore_crc16_checker_crctmp3 + connect \Y $eq$ls180.v:4994$891_Y + end + attribute \src "ls180.v:5002.7-5002.44" + cell $eq $eq$ls180.v:5002$895 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_cnt + connect \B 3'111 + connect \Y $eq$ls180.v:5002$895_Y + end + attribute \src "ls180.v:5012.7-5012.44" + cell $eq $eq$ls180.v:5012$898 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_cnt + connect \B 3'111 + connect \Y $eq$ls180.v:5012$898_Y + end + attribute \src "ls180.v:5022.7-5022.44" + cell $eq $eq$ls180.v:5022$901 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_cnt + connect \B 3'111 + connect \Y $eq$ls180.v:5022$901_Y + end + attribute \src "ls180.v:5032.7-5032.44" + cell $eq $eq$ls180.v:5032$904 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_cnt + connect \B 3'111 + connect \Y $eq$ls180.v:5032$904_Y + end + attribute \src "ls180.v:5156.36-5156.64" + cell $eq $eq$ls180.v:5156$955 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_cmd_type + connect \B 1'0 + connect \Y $eq$ls180.v:5156$955_Y + end + attribute \src "ls180.v:5162.10-5162.39" + cell $eq $eq$ls180.v:5162$958 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_cmd_count + connect \B 3'101 + connect \Y $eq$ls180.v:5162$958_Y + end + attribute \src "ls180.v:5163.11-5163.39" + cell $eq $eq$ls180.v:5163$959 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_cmd_type + connect \B 1'0 + connect \Y $eq$ls180.v:5163$959_Y + end + attribute \src "ls180.v:5175.34-5175.63" + cell $eq $eq$ls180.v:5175$960 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_data_type + connect \B 1'0 + connect \Y $eq$ls180.v:5175$960_Y + end + attribute \src "ls180.v:5176.9-5176.37" + cell $eq $eq$ls180.v:5176$961 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_cmd_type + connect \B 2'10 + connect \Y $eq$ls180.v:5176$961_Y + end + attribute \src "ls180.v:5183.10-5183.55" + cell $eq $eq$ls180.v:5183$962 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_source_payload_status + connect \B 1'1 + connect \Y $eq$ls180.v:5183$962_Y + end + attribute \src "ls180.v:5189.12-5189.41" + cell $eq $eq$ls180.v:5189$963 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_data_type + connect \B 2'10 + connect \Y $eq$ls180.v:5189$963_Y + end + attribute \src "ls180.v:5192.13-5192.42" + cell $eq $eq$ls180.v:5192$964 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_data_type + connect \B 1'1 + connect \Y $eq$ls180.v:5192$964_Y + end + attribute \src "ls180.v:5214.10-5214.76" + cell $eq $eq$ls180.v:5214$969 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_data_count + connect \B $sub$ls180.v:5214$968_Y + connect \Y $eq$ls180.v:5214$969_Y + end + attribute \src "ls180.v:5229.35-5229.101" + cell $eq $eq$ls180.v:5229$972 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_data_count + connect \B $sub$ls180.v:5229$971_Y + connect \Y $eq$ls180.v:5229$972_Y + end + attribute \src "ls180.v:5231.10-5231.56" + cell $eq $eq$ls180.v:5231$973 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_source_payload_status + connect \B 1'0 + connect \Y $eq$ls180.v:5231$973_Y + end + attribute \src "ls180.v:5240.12-5240.78" + cell $eq $eq$ls180.v:5240$977 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_data_count + connect \B $sub$ls180.v:5240$976_Y + connect \Y $eq$ls180.v:5240$977_Y + end + attribute \src "ls180.v:5247.11-5247.57" + cell $eq $eq$ls180.v:5247$978 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_source_payload_status + connect \B 1'1 + connect \Y $eq$ls180.v:5247$978_Y + end + attribute \src "ls180.v:5364.10-5364.105" + cell $eq $eq$ls180.v:5364$995 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_wishbonedmawriter_offset + connect \B $sub$ls180.v:5364$994_Y + connect \Y $eq$ls180.v:5364$995_Y + end + attribute \src "ls180.v:5454.39-5454.106" + cell $eq $eq$ls180.v:5454$1001 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_dma_offset + connect \B $sub$ls180.v:5454$1000_Y + connect \Y $eq$ls180.v:5454$1001_Y + end + attribute \src "ls180.v:5484.44-5484.82" + cell $eq $eq$ls180.v:5484$1004 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_converter_mux + connect \B 1'0 + connect \Y $eq$ls180.v:5484$1004_Y + end + attribute \src "ls180.v:5485.43-5485.81" + cell $eq $eq$ls180.v:5485$1005 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_converter_mux + connect \B 2'11 + connect \Y $eq$ls180.v:5485$1005_Y + end + attribute \src "ls180.v:5542.32-5542.99" + cell $eq $eq$ls180.v:5542$1018 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 16 + parameter \Y_WIDTH 1 + connect \A \libresocsim_clk_divider1 + connect \B $sub$ls180.v:5542$1017_Y + connect \Y $eq$ls180.v:5542$1018_Y + end + attribute \src "ls180.v:5543.32-5543.93" + cell $eq $eq$ls180.v:5543$1020 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 16 + parameter \Y_WIDTH 1 + connect \A \libresocsim_clk_divider1 + connect \B $sub$ls180.v:5543$1019_Y + connect \Y $eq$ls180.v:5543$1020_Y + end + attribute \src "ls180.v:5571.10-5571.59" + cell $eq $eq$ls180.v:5571$1024 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \libresocsim_count + connect \B $sub$ls180.v:5571$1023_Y + connect \Y $eq$ls180.v:5571$1024_Y + end + attribute \src "ls180.v:5644.85-5644.106" + cell $eq $eq$ls180.v:5644$1029 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_grant + connect \B 1'0 + connect \Y $eq$ls180.v:5644$1029_Y + end + attribute \src "ls180.v:5645.85-5645.106" + cell $eq $eq$ls180.v:5645$1031 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_grant + connect \B 1'1 + connect \Y $eq$ls180.v:5645$1031_Y + end + attribute \src "ls180.v:5646.85-5646.106" + cell $eq $eq$ls180.v:5646$1033 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_grant + connect \B 2'10 + connect \Y $eq$ls180.v:5646$1033_Y + end + attribute \src "ls180.v:5647.57-5647.78" + cell $eq $eq$ls180.v:5647$1035 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_grant + connect \B 2'11 + connect \Y $eq$ls180.v:5647$1035_Y + end + attribute \src "ls180.v:5648.57-5648.78" + cell $eq $eq$ls180.v:5648$1037 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_grant + connect \B 3'100 + connect \Y $eq$ls180.v:5648$1037_Y + end + attribute \src "ls180.v:5649.85-5649.106" + cell $eq $eq$ls180.v:5649$1039 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_grant + connect \B 1'0 + connect \Y $eq$ls180.v:5649$1039_Y + end + attribute \src "ls180.v:5650.85-5650.106" + cell $eq $eq$ls180.v:5650$1041 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_grant + connect \B 1'1 + connect \Y $eq$ls180.v:5650$1041_Y + end + attribute \src "ls180.v:5651.85-5651.106" + cell $eq $eq$ls180.v:5651$1043 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_grant + connect \B 2'10 + connect \Y $eq$ls180.v:5651$1043_Y + end + attribute \src "ls180.v:5652.57-5652.78" + cell $eq $eq$ls180.v:5652$1045 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_grant + connect \B 2'11 + connect \Y $eq$ls180.v:5652$1045_Y + end + attribute \src "ls180.v:5653.57-5653.78" + cell $eq $eq$ls180.v:5653$1047 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_grant + connect \B 3'100 + connect \Y $eq$ls180.v:5653$1047_Y + end + attribute \src "ls180.v:5657.27-5657.59" + cell $eq $eq$ls180.v:5657$1050 + parameter \A_SIGNED 0 + parameter \A_WIDTH 23 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_adr [29:7] + connect \B 1'0 + connect \Y $eq$ls180.v:5657$1050_Y + end + attribute \src "ls180.v:5658.27-5658.68" + cell $eq $eq$ls180.v:5658$1051 + parameter \A_SIGNED 0 + parameter \A_WIDTH 27 + parameter \B_SIGNED 0 + parameter \B_WIDTH 27 + parameter \Y_WIDTH 1 + connect \A \builder_shared_adr [29:3] + connect \B 27'110000000000000100000000000 + connect \Y $eq$ls180.v:5658$1051_Y + end + attribute \src "ls180.v:5659.27-5659.66" + cell $eq $eq$ls180.v:5659$1052 + parameter \A_SIGNED 0 + parameter \A_WIDTH 20 + parameter \B_SIGNED 0 + parameter \B_WIDTH 20 + parameter \Y_WIDTH 1 + connect \A \builder_shared_adr [29:10] + connect \B 20'11000000000000010001 + connect \Y $eq$ls180.v:5659$1052_Y + end + attribute \src "ls180.v:5660.27-5660.61" + cell $eq $eq$ls180.v:5660$1053 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \builder_shared_adr [29:23] + connect \B 7'1001000 + connect \Y $eq$ls180.v:5660$1053_Y + end + attribute \src "ls180.v:5661.27-5661.65" + cell $eq $eq$ls180.v:5661$1054 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 16 + parameter \Y_WIDTH 1 + connect \A \builder_shared_adr [29:14] + connect \B 16'1100000000000000 + connect \Y $eq$ls180.v:5661$1054_Y + end + attribute \src "ls180.v:5717.24-5717.45" + cell $eq $eq$ls180.v:5717$1081 + parameter \A_SIGNED 0 + parameter \A_WIDTH 20 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_count + connect \B 1'0 + connect \Y $eq$ls180.v:5717$1081_Y + end + attribute \src "ls180.v:5718.32-5718.77" + cell $eq $eq$ls180.v:5718$1082 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [13:9] + connect \B 1'0 + connect \Y $eq$ls180.v:5718$1082_Y + end + attribute \src "ls180.v:5720.97-5720.141" + cell $eq $eq$ls180.v:5720$1084 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 1'0 + connect \Y $eq$ls180.v:5720$1084_Y + end + attribute \src "ls180.v:5721.100-5721.144" + cell $eq $eq$ls180.v:5721$1088 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 1'0 + connect \Y $eq$ls180.v:5721$1088_Y + end + attribute \src "ls180.v:5723.99-5723.143" + cell $eq $eq$ls180.v:5723$1091 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 1'1 + connect \Y $eq$ls180.v:5723$1091_Y + end + attribute \src "ls180.v:5724.102-5724.146" + cell $eq $eq$ls180.v:5724$1095 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 1'1 + connect \Y $eq$ls180.v:5724$1095_Y + end + attribute \src "ls180.v:5726.99-5726.143" + cell $eq $eq$ls180.v:5726$1098 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 2'10 + connect \Y $eq$ls180.v:5726$1098_Y + end + attribute \src "ls180.v:5727.102-5727.146" + cell $eq $eq$ls180.v:5727$1102 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 2'10 + connect \Y $eq$ls180.v:5727$1102_Y + end + attribute \src "ls180.v:5729.99-5729.143" + cell $eq $eq$ls180.v:5729$1105 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 2'11 + connect \Y $eq$ls180.v:5729$1105_Y + end + attribute \src "ls180.v:5730.102-5730.146" + cell $eq $eq$ls180.v:5730$1109 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 2'11 + connect \Y $eq$ls180.v:5730$1109_Y + end + attribute \src "ls180.v:5732.99-5732.143" + cell $eq $eq$ls180.v:5732$1112 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 3'100 + connect \Y $eq$ls180.v:5732$1112_Y + end + attribute \src "ls180.v:5733.102-5733.146" + cell $eq $eq$ls180.v:5733$1116 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 3'100 + connect \Y $eq$ls180.v:5733$1116_Y + end + attribute \src "ls180.v:5735.102-5735.146" + cell $eq $eq$ls180.v:5735$1119 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 3'101 + connect \Y $eq$ls180.v:5735$1119_Y + end + attribute \src "ls180.v:5736.105-5736.149" + cell $eq $eq$ls180.v:5736$1123 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 3'101 + connect \Y $eq$ls180.v:5736$1123_Y + end + attribute \src "ls180.v:5738.102-5738.146" + cell $eq $eq$ls180.v:5738$1126 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 3'110 + connect \Y $eq$ls180.v:5738$1126_Y + end + attribute \src "ls180.v:5739.105-5739.149" + cell $eq $eq$ls180.v:5739$1130 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 3'110 + connect \Y $eq$ls180.v:5739$1130_Y + end + attribute \src "ls180.v:5741.102-5741.146" + cell $eq $eq$ls180.v:5741$1133 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 3'111 + connect \Y $eq$ls180.v:5741$1133_Y + end + attribute \src "ls180.v:5742.105-5742.149" + cell $eq $eq$ls180.v:5742$1137 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 3'111 + connect \Y $eq$ls180.v:5742$1137_Y + end + attribute \src "ls180.v:5744.102-5744.146" + cell $eq $eq$ls180.v:5744$1140 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:5744$1140_Y + end + attribute \src "ls180.v:5745.105-5745.149" + cell $eq $eq$ls180.v:5745$1144 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:5745$1144_Y + end + attribute \src "ls180.v:5756.32-5756.77" + cell $eq $eq$ls180.v:5756$1146 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_adr [13:9] + connect \B 3'110 + connect \Y $eq$ls180.v:5756$1146_Y + end + attribute \src "ls180.v:5758.94-5758.138" + cell $eq $eq$ls180.v:5758$1148 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_adr [2:0] + connect \B 1'0 + connect \Y $eq$ls180.v:5758$1148_Y + end + attribute \src "ls180.v:5759.97-5759.141" + cell $eq $eq$ls180.v:5759$1152 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_adr [2:0] + connect \B 1'0 + connect \Y $eq$ls180.v:5759$1152_Y + end + attribute \src "ls180.v:5761.94-5761.138" + cell $eq $eq$ls180.v:5761$1155 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_adr [2:0] + connect \B 1'1 + connect \Y $eq$ls180.v:5761$1155_Y + end + attribute \src "ls180.v:5762.97-5762.141" + cell $eq $eq$ls180.v:5762$1159 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_adr [2:0] + connect \B 1'1 + connect \Y $eq$ls180.v:5762$1159_Y + end + attribute \src "ls180.v:5764.94-5764.138" + cell $eq $eq$ls180.v:5764$1162 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_adr [2:0] + connect \B 2'10 + connect \Y $eq$ls180.v:5764$1162_Y + end + attribute \src "ls180.v:5765.97-5765.141" + cell $eq $eq$ls180.v:5765$1166 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_adr [2:0] + connect \B 2'10 + connect \Y $eq$ls180.v:5765$1166_Y + end + attribute \src "ls180.v:5767.94-5767.138" + cell $eq $eq$ls180.v:5767$1169 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_adr [2:0] + connect \B 2'11 + connect \Y $eq$ls180.v:5767$1169_Y + end + attribute \src "ls180.v:5768.97-5768.141" + cell $eq $eq$ls180.v:5768$1173 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_adr [2:0] + connect \B 2'11 + connect \Y $eq$ls180.v:5768$1173_Y + end + attribute \src "ls180.v:5770.95-5770.139" + cell $eq $eq$ls180.v:5770$1176 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_adr [2:0] + connect \B 3'100 + connect \Y $eq$ls180.v:5770$1176_Y + end + attribute \src "ls180.v:5771.98-5771.142" + cell $eq $eq$ls180.v:5771$1180 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_adr [2:0] + connect \B 3'100 + connect \Y $eq$ls180.v:5771$1180_Y + end + attribute \src "ls180.v:5773.95-5773.139" + cell $eq $eq$ls180.v:5773$1183 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_adr [2:0] + connect \B 3'101 + connect \Y $eq$ls180.v:5773$1183_Y + end + attribute \src "ls180.v:5774.98-5774.142" + cell $eq $eq$ls180.v:5774$1187 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_adr [2:0] + connect \B 3'101 + connect \Y $eq$ls180.v:5774$1187_Y + end + attribute \src "ls180.v:5782.32-5782.77" + cell $eq $eq$ls180.v:5782$1189 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface2_bank_bus_adr [13:9] + connect \B 4'1000 + connect \Y $eq$ls180.v:5782$1189_Y + end + attribute \src "ls180.v:5784.98-5784.142" + cell $eq $eq$ls180.v:5784$1191 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface2_bank_bus_adr [3:0] + connect \B 1'0 + connect \Y $eq$ls180.v:5784$1191_Y + end + attribute \src "ls180.v:5785.101-5785.145" + cell $eq $eq$ls180.v:5785$1195 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface2_bank_bus_adr [3:0] + connect \B 1'0 + connect \Y $eq$ls180.v:5785$1195_Y + end + attribute \src "ls180.v:5787.97-5787.141" + cell $eq $eq$ls180.v:5787$1198 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface2_bank_bus_adr [3:0] + connect \B 1'1 + connect \Y $eq$ls180.v:5787$1198_Y + end + attribute \src "ls180.v:5788.100-5788.144" + cell $eq $eq$ls180.v:5788$1202 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface2_bank_bus_adr [3:0] + connect \B 1'1 + connect \Y $eq$ls180.v:5788$1202_Y + end + attribute \src "ls180.v:5790.97-5790.141" + cell $eq $eq$ls180.v:5790$1205 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface2_bank_bus_adr [3:0] + connect \B 2'10 + connect \Y $eq$ls180.v:5790$1205_Y + end + attribute \src "ls180.v:5791.100-5791.144" + cell $eq $eq$ls180.v:5791$1209 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface2_bank_bus_adr [3:0] + connect \B 2'10 + connect \Y $eq$ls180.v:5791$1209_Y + end + attribute \src "ls180.v:5793.97-5793.141" + cell $eq $eq$ls180.v:5793$1212 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface2_bank_bus_adr [3:0] + connect \B 2'11 + connect \Y $eq$ls180.v:5793$1212_Y + end + attribute \src "ls180.v:5794.100-5794.144" + cell $eq $eq$ls180.v:5794$1216 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface2_bank_bus_adr [3:0] + connect \B 2'11 + connect \Y $eq$ls180.v:5794$1216_Y + end + attribute \src "ls180.v:5796.97-5796.141" + cell $eq $eq$ls180.v:5796$1219 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface2_bank_bus_adr [3:0] + connect \B 3'100 + connect \Y $eq$ls180.v:5796$1219_Y + end + attribute \src "ls180.v:5797.100-5797.144" + cell $eq $eq$ls180.v:5797$1223 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface2_bank_bus_adr [3:0] + connect \B 3'100 + connect \Y $eq$ls180.v:5797$1223_Y + end + attribute \src "ls180.v:5799.98-5799.142" + cell $eq $eq$ls180.v:5799$1226 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface2_bank_bus_adr [3:0] + connect \B 3'101 + connect \Y $eq$ls180.v:5799$1226_Y + end + attribute \src "ls180.v:5800.101-5800.145" + cell $eq $eq$ls180.v:5800$1230 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface2_bank_bus_adr [3:0] + connect \B 3'101 + connect \Y $eq$ls180.v:5800$1230_Y + end + attribute \src "ls180.v:5802.98-5802.142" + cell $eq $eq$ls180.v:5802$1233 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface2_bank_bus_adr [3:0] + connect \B 3'110 + connect \Y $eq$ls180.v:5802$1233_Y + end + attribute \src "ls180.v:5803.101-5803.145" + cell $eq $eq$ls180.v:5803$1237 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface2_bank_bus_adr [3:0] + connect \B 3'110 + connect \Y $eq$ls180.v:5803$1237_Y + end + attribute \src "ls180.v:5805.98-5805.142" + cell $eq $eq$ls180.v:5805$1240 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface2_bank_bus_adr [3:0] + connect \B 3'111 + connect \Y $eq$ls180.v:5805$1240_Y + end + attribute \src "ls180.v:5806.101-5806.145" + cell $eq $eq$ls180.v:5806$1244 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface2_bank_bus_adr [3:0] + connect \B 3'111 + connect \Y $eq$ls180.v:5806$1244_Y + end + attribute \src "ls180.v:5808.98-5808.142" + cell $eq $eq$ls180.v:5808$1247 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface2_bank_bus_adr [3:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:5808$1247_Y + end + attribute \src "ls180.v:5809.101-5809.145" + cell $eq $eq$ls180.v:5809$1251 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface2_bank_bus_adr [3:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:5809$1251_Y + end + attribute \src "ls180.v:5819.32-5819.77" + cell $eq $eq$ls180.v:5819$1253 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [13:9] + connect \B 4'1001 + connect \Y $eq$ls180.v:5819$1253_Y + end + attribute \src "ls180.v:5821.98-5821.142" + cell $eq $eq$ls180.v:5821$1255 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 1'0 + connect \Y $eq$ls180.v:5821$1255_Y + end + attribute \src "ls180.v:5822.101-5822.145" + cell $eq $eq$ls180.v:5822$1259 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 1'0 + connect \Y $eq$ls180.v:5822$1259_Y + end + attribute \src "ls180.v:5824.97-5824.141" + cell $eq $eq$ls180.v:5824$1262 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 1'1 + connect \Y $eq$ls180.v:5824$1262_Y + end + attribute \src "ls180.v:5825.100-5825.144" + cell $eq $eq$ls180.v:5825$1266 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 1'1 + connect \Y $eq$ls180.v:5825$1266_Y + end + attribute \src "ls180.v:5827.97-5827.141" + cell $eq $eq$ls180.v:5827$1269 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 2'10 + connect \Y $eq$ls180.v:5827$1269_Y + end + attribute \src "ls180.v:5828.100-5828.144" + cell $eq $eq$ls180.v:5828$1273 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 2'10 + connect \Y $eq$ls180.v:5828$1273_Y + end + attribute \src "ls180.v:5830.97-5830.141" + cell $eq $eq$ls180.v:5830$1276 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 2'11 + connect \Y $eq$ls180.v:5830$1276_Y + end + attribute \src "ls180.v:5831.100-5831.144" + cell $eq $eq$ls180.v:5831$1280 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 2'11 + connect \Y $eq$ls180.v:5831$1280_Y + end + attribute \src "ls180.v:5833.97-5833.141" + cell $eq $eq$ls180.v:5833$1283 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 3'100 + connect \Y $eq$ls180.v:5833$1283_Y + end + attribute \src "ls180.v:5834.100-5834.144" + cell $eq $eq$ls180.v:5834$1287 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 3'100 + connect \Y $eq$ls180.v:5834$1287_Y + end + attribute \src "ls180.v:5836.98-5836.142" + cell $eq $eq$ls180.v:5836$1290 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 3'101 + connect \Y $eq$ls180.v:5836$1290_Y + end + attribute \src "ls180.v:5837.101-5837.145" + cell $eq $eq$ls180.v:5837$1294 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 3'101 + connect \Y $eq$ls180.v:5837$1294_Y + end + attribute \src "ls180.v:5839.98-5839.142" + cell $eq $eq$ls180.v:5839$1297 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 3'110 + connect \Y $eq$ls180.v:5839$1297_Y + end + attribute \src "ls180.v:5840.101-5840.145" + cell $eq $eq$ls180.v:5840$1301 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 3'110 + connect \Y $eq$ls180.v:5840$1301_Y + end + attribute \src "ls180.v:5842.98-5842.142" + cell $eq $eq$ls180.v:5842$1304 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 3'111 + connect \Y $eq$ls180.v:5842$1304_Y + end + attribute \src "ls180.v:5843.101-5843.145" + cell $eq $eq$ls180.v:5843$1308 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 3'111 + connect \Y $eq$ls180.v:5843$1308_Y + end + attribute \src "ls180.v:5845.98-5845.142" + cell $eq $eq$ls180.v:5845$1311 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:5845$1311_Y + end + attribute \src "ls180.v:5846.101-5846.145" + cell $eq $eq$ls180.v:5846$1315 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:5846$1315_Y + end + attribute \src "ls180.v:5856.32-5856.78" + cell $eq $eq$ls180.v:5856$1317 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [13:9] + connect \B 4'1100 + connect \Y $eq$ls180.v:5856$1317_Y + end + attribute \src "ls180.v:5858.100-5858.144" + cell $eq $eq$ls180.v:5858$1319 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 1'0 + connect \Y $eq$ls180.v:5858$1319_Y + end + attribute \src "ls180.v:5859.103-5859.147" + cell $eq $eq$ls180.v:5859$1323 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 1'0 + connect \Y $eq$ls180.v:5859$1323_Y + end + attribute \src "ls180.v:5861.100-5861.144" + cell $eq $eq$ls180.v:5861$1326 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 1'1 + connect \Y $eq$ls180.v:5861$1326_Y + end + attribute \src "ls180.v:5862.103-5862.147" + cell $eq $eq$ls180.v:5862$1330 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 1'1 + connect \Y $eq$ls180.v:5862$1330_Y + end + attribute \src "ls180.v:5864.100-5864.144" + cell $eq $eq$ls180.v:5864$1333 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 2'10 + connect \Y $eq$ls180.v:5864$1333_Y + end + attribute \src "ls180.v:5865.103-5865.147" + cell $eq $eq$ls180.v:5865$1337 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 2'10 + connect \Y $eq$ls180.v:5865$1337_Y + end + attribute \src "ls180.v:5867.100-5867.144" + cell $eq $eq$ls180.v:5867$1340 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 2'11 + connect \Y $eq$ls180.v:5867$1340_Y + end + attribute \src "ls180.v:5868.103-5868.147" + cell $eq $eq$ls180.v:5868$1344 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 2'11 + connect \Y $eq$ls180.v:5868$1344_Y + end + attribute \src "ls180.v:5870.100-5870.144" + cell $eq $eq$ls180.v:5870$1347 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 3'100 + connect \Y $eq$ls180.v:5870$1347_Y + end + attribute \src "ls180.v:5871.103-5871.147" + cell $eq $eq$ls180.v:5871$1351 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 3'100 + connect \Y $eq$ls180.v:5871$1351_Y + end + attribute \src "ls180.v:5873.100-5873.144" + cell $eq $eq$ls180.v:5873$1354 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 3'101 + connect \Y $eq$ls180.v:5873$1354_Y + end + attribute \src "ls180.v:5874.103-5874.147" + cell $eq $eq$ls180.v:5874$1358 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 3'101 + connect \Y $eq$ls180.v:5874$1358_Y + end + attribute \src "ls180.v:5876.100-5876.144" + cell $eq $eq$ls180.v:5876$1361 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 3'110 + connect \Y $eq$ls180.v:5876$1361_Y + end + attribute \src "ls180.v:5877.103-5877.147" + cell $eq $eq$ls180.v:5877$1365 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 3'110 + connect \Y $eq$ls180.v:5877$1365_Y + end + attribute \src "ls180.v:5879.100-5879.144" + cell $eq $eq$ls180.v:5879$1368 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 3'111 + connect \Y $eq$ls180.v:5879$1368_Y + end + attribute \src "ls180.v:5880.103-5880.147" + cell $eq $eq$ls180.v:5880$1372 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 3'111 + connect \Y $eq$ls180.v:5880$1372_Y + end + attribute \src "ls180.v:5882.102-5882.146" + cell $eq $eq$ls180.v:5882$1375 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:5882$1375_Y + end + attribute \src "ls180.v:5883.105-5883.149" + cell $eq $eq$ls180.v:5883$1379 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:5883$1379_Y + end + attribute \src "ls180.v:5885.102-5885.146" + cell $eq $eq$ls180.v:5885$1382 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 4'1001 + connect \Y $eq$ls180.v:5885$1382_Y + end + attribute \src "ls180.v:5886.105-5886.149" + cell $eq $eq$ls180.v:5886$1386 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 4'1001 + connect \Y $eq$ls180.v:5886$1386_Y + end + attribute \src "ls180.v:5888.102-5888.147" + cell $eq $eq$ls180.v:5888$1389 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 4'1010 + connect \Y $eq$ls180.v:5888$1389_Y + end + attribute \src "ls180.v:5889.105-5889.150" + cell $eq $eq$ls180.v:5889$1393 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 4'1010 + connect \Y $eq$ls180.v:5889$1393_Y + end + attribute \src "ls180.v:5891.102-5891.147" + cell $eq $eq$ls180.v:5891$1396 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 4'1011 + connect \Y $eq$ls180.v:5891$1396_Y + end + attribute \src "ls180.v:5892.105-5892.150" + cell $eq $eq$ls180.v:5892$1400 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 4'1011 + connect \Y $eq$ls180.v:5892$1400_Y + end + attribute \src "ls180.v:5894.102-5894.147" + cell $eq $eq$ls180.v:5894$1403 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 4'1100 + connect \Y $eq$ls180.v:5894$1403_Y + end + attribute \src "ls180.v:5895.105-5895.150" + cell $eq $eq$ls180.v:5895$1407 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 4'1100 + connect \Y $eq$ls180.v:5895$1407_Y + end + attribute \src "ls180.v:5897.99-5897.144" + cell $eq $eq$ls180.v:5897$1410 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 4'1101 + connect \Y $eq$ls180.v:5897$1410_Y + end + attribute \src "ls180.v:5898.102-5898.147" + cell $eq $eq$ls180.v:5898$1414 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 4'1101 + connect \Y $eq$ls180.v:5898$1414_Y + end + attribute \src "ls180.v:5900.100-5900.145" + cell $eq $eq$ls180.v:5900$1417 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 4'1110 + connect \Y $eq$ls180.v:5900$1417_Y + end + attribute \src "ls180.v:5901.103-5901.148" + cell $eq $eq$ls180.v:5901$1421 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 4'1110 + connect \Y $eq$ls180.v:5901$1421_Y + end + attribute \src "ls180.v:5918.32-5918.78" + cell $eq $eq$ls180.v:5918$1423 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [13:9] + connect \B 4'1011 + connect \Y $eq$ls180.v:5918$1423_Y + end + attribute \src "ls180.v:5920.104-5920.148" + cell $eq $eq$ls180.v:5920$1425 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [5:0] + connect \B 1'0 + connect \Y $eq$ls180.v:5920$1425_Y + end + attribute \src "ls180.v:5921.107-5921.151" + cell $eq $eq$ls180.v:5921$1429 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [5:0] + connect \B 1'0 + connect \Y $eq$ls180.v:5921$1429_Y + end + attribute \src "ls180.v:5923.104-5923.148" + cell $eq $eq$ls180.v:5923$1432 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [5:0] + connect \B 1'1 + connect \Y $eq$ls180.v:5923$1432_Y + end + attribute \src "ls180.v:5924.107-5924.151" + cell $eq $eq$ls180.v:5924$1436 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [5:0] + connect \B 1'1 + connect \Y $eq$ls180.v:5924$1436_Y + end + attribute \src "ls180.v:5926.104-5926.148" + cell $eq $eq$ls180.v:5926$1439 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [5:0] + connect \B 2'10 + connect \Y $eq$ls180.v:5926$1439_Y + end + attribute \src "ls180.v:5927.107-5927.151" + cell $eq $eq$ls180.v:5927$1443 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [5:0] + connect \B 2'10 + connect \Y $eq$ls180.v:5927$1443_Y + end + attribute \src "ls180.v:5929.104-5929.148" + cell $eq $eq$ls180.v:5929$1446 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [5:0] + connect \B 2'11 + connect \Y $eq$ls180.v:5929$1446_Y + end + attribute \src "ls180.v:5930.107-5930.151" + cell $eq $eq$ls180.v:5930$1450 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [5:0] + connect \B 2'11 + connect \Y $eq$ls180.v:5930$1450_Y + end + attribute \src "ls180.v:5932.103-5932.147" + cell $eq $eq$ls180.v:5932$1453 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [5:0] + connect \B 3'100 + connect \Y $eq$ls180.v:5932$1453_Y + end + attribute \src "ls180.v:5933.106-5933.150" + cell $eq $eq$ls180.v:5933$1457 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [5:0] + connect \B 3'100 + connect \Y $eq$ls180.v:5933$1457_Y + end + attribute \src "ls180.v:5935.103-5935.147" + cell $eq $eq$ls180.v:5935$1460 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [5:0] + connect \B 3'101 + connect \Y $eq$ls180.v:5935$1460_Y + end + attribute \src "ls180.v:5936.106-5936.150" + cell $eq $eq$ls180.v:5936$1464 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [5:0] + connect \B 3'101 + connect \Y $eq$ls180.v:5936$1464_Y + end + attribute \src "ls180.v:5938.103-5938.147" + cell $eq $eq$ls180.v:5938$1467 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [5:0] + connect \B 3'110 + connect \Y $eq$ls180.v:5938$1467_Y + end + attribute \src "ls180.v:5939.106-5939.150" + cell $eq $eq$ls180.v:5939$1471 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [5:0] + connect \B 3'110 + connect \Y $eq$ls180.v:5939$1471_Y + end + attribute \src "ls180.v:5941.103-5941.147" + cell $eq $eq$ls180.v:5941$1474 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [5:0] + connect \B 3'111 + connect \Y $eq$ls180.v:5941$1474_Y + end + attribute \src "ls180.v:5942.106-5942.150" + cell $eq $eq$ls180.v:5942$1478 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [5:0] + connect \B 3'111 + connect \Y $eq$ls180.v:5942$1478_Y + end + attribute \src "ls180.v:5944.94-5944.138" + cell $eq $eq$ls180.v:5944$1481 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [5:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:5944$1481_Y + end + attribute \src "ls180.v:5945.97-5945.141" + cell $eq $eq$ls180.v:5945$1485 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [5:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:5945$1485_Y + end + attribute \src "ls180.v:5947.105-5947.149" + cell $eq $eq$ls180.v:5947$1488 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [5:0] + connect \B 4'1001 + connect \Y $eq$ls180.v:5947$1488_Y + end + attribute \src "ls180.v:5948.108-5948.152" + cell $eq $eq$ls180.v:5948$1492 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [5:0] + connect \B 4'1001 + connect \Y $eq$ls180.v:5948$1492_Y + end + attribute \src "ls180.v:5950.105-5950.150" + cell $eq $eq$ls180.v:5950$1495 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [5:0] + connect \B 4'1010 + connect \Y $eq$ls180.v:5950$1495_Y + end + attribute \src "ls180.v:5951.108-5951.153" + cell $eq $eq$ls180.v:5951$1499 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [5:0] + connect \B 4'1010 + connect \Y $eq$ls180.v:5951$1499_Y + end + attribute \src "ls180.v:5953.105-5953.150" + cell $eq $eq$ls180.v:5953$1502 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [5:0] + connect \B 4'1011 + connect \Y $eq$ls180.v:5953$1502_Y + end + attribute \src "ls180.v:5954.108-5954.153" + cell $eq $eq$ls180.v:5954$1506 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [5:0] + connect \B 4'1011 + connect \Y $eq$ls180.v:5954$1506_Y + end + attribute \src "ls180.v:5956.105-5956.150" + cell $eq $eq$ls180.v:5956$1509 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [5:0] + connect \B 4'1100 + connect \Y $eq$ls180.v:5956$1509_Y + end + attribute \src "ls180.v:5957.108-5957.153" + cell $eq $eq$ls180.v:5957$1513 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [5:0] + connect \B 4'1100 + connect \Y $eq$ls180.v:5957$1513_Y + end + attribute \src "ls180.v:5959.105-5959.150" + cell $eq $eq$ls180.v:5959$1516 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [5:0] + connect \B 4'1101 + connect \Y $eq$ls180.v:5959$1516_Y + end + attribute \src "ls180.v:5960.108-5960.153" + cell $eq $eq$ls180.v:5960$1520 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [5:0] + connect \B 4'1101 + connect \Y $eq$ls180.v:5960$1520_Y + end + attribute \src "ls180.v:5962.105-5962.150" + cell $eq $eq$ls180.v:5962$1523 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [5:0] + connect \B 4'1110 + connect \Y $eq$ls180.v:5962$1523_Y + end + attribute \src "ls180.v:5963.108-5963.153" + cell $eq $eq$ls180.v:5963$1527 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [5:0] + connect \B 4'1110 + connect \Y $eq$ls180.v:5963$1527_Y + end + attribute \src "ls180.v:5965.104-5965.149" + cell $eq $eq$ls180.v:5965$1530 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [5:0] + connect \B 4'1111 + connect \Y $eq$ls180.v:5965$1530_Y + end + attribute \src "ls180.v:5966.107-5966.152" + cell $eq $eq$ls180.v:5966$1534 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [5:0] + connect \B 4'1111 + connect \Y $eq$ls180.v:5966$1534_Y + end + attribute \src "ls180.v:5968.104-5968.149" + cell $eq $eq$ls180.v:5968$1537 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [5:0] + connect \B 5'10000 + connect \Y $eq$ls180.v:5968$1537_Y + end + attribute \src "ls180.v:5969.107-5969.152" + cell $eq $eq$ls180.v:5969$1541 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [5:0] + connect \B 5'10000 + connect \Y $eq$ls180.v:5969$1541_Y + end + attribute \src "ls180.v:5971.104-5971.149" + cell $eq $eq$ls180.v:5971$1544 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [5:0] + connect \B 5'10001 + connect \Y $eq$ls180.v:5971$1544_Y + end + attribute \src "ls180.v:5972.107-5972.152" + cell $eq $eq$ls180.v:5972$1548 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [5:0] + connect \B 5'10001 + connect \Y $eq$ls180.v:5972$1548_Y + end + attribute \src "ls180.v:5974.104-5974.149" + cell $eq $eq$ls180.v:5974$1551 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [5:0] + connect \B 5'10010 + connect \Y $eq$ls180.v:5974$1551_Y + end + attribute \src "ls180.v:5975.107-5975.152" + cell $eq $eq$ls180.v:5975$1555 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [5:0] + connect \B 5'10010 + connect \Y $eq$ls180.v:5975$1555_Y + end + attribute \src "ls180.v:5977.104-5977.149" + cell $eq $eq$ls180.v:5977$1558 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [5:0] + connect \B 5'10011 + connect \Y $eq$ls180.v:5977$1558_Y + end + attribute \src "ls180.v:5978.107-5978.152" + cell $eq $eq$ls180.v:5978$1562 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [5:0] + connect \B 5'10011 + connect \Y $eq$ls180.v:5978$1562_Y + end + attribute \src "ls180.v:5980.104-5980.149" + cell $eq $eq$ls180.v:5980$1565 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [5:0] + connect \B 5'10100 + connect \Y $eq$ls180.v:5980$1565_Y + end + attribute \src "ls180.v:5981.107-5981.152" + cell $eq $eq$ls180.v:5981$1569 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [5:0] + connect \B 5'10100 + connect \Y $eq$ls180.v:5981$1569_Y + end + attribute \src "ls180.v:5983.104-5983.149" + cell $eq $eq$ls180.v:5983$1572 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [5:0] + connect \B 5'10101 + connect \Y $eq$ls180.v:5983$1572_Y + end + attribute \src "ls180.v:5984.107-5984.152" + cell $eq $eq$ls180.v:5984$1576 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [5:0] + connect \B 5'10101 + connect \Y $eq$ls180.v:5984$1576_Y + end + attribute \src "ls180.v:5986.104-5986.149" + cell $eq $eq$ls180.v:5986$1579 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [5:0] + connect \B 5'10110 + connect \Y $eq$ls180.v:5986$1579_Y + end + attribute \src "ls180.v:5987.107-5987.152" + cell $eq $eq$ls180.v:5987$1583 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [5:0] + connect \B 5'10110 + connect \Y $eq$ls180.v:5987$1583_Y + end + attribute \src "ls180.v:5989.104-5989.149" + cell $eq $eq$ls180.v:5989$1586 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [5:0] + connect \B 5'10111 + connect \Y $eq$ls180.v:5989$1586_Y + end + attribute \src "ls180.v:5990.107-5990.152" + cell $eq $eq$ls180.v:5990$1590 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [5:0] + connect \B 5'10111 + connect \Y $eq$ls180.v:5990$1590_Y + end + attribute \src "ls180.v:5992.104-5992.149" + cell $eq $eq$ls180.v:5992$1593 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [5:0] + connect \B 5'11000 + connect \Y $eq$ls180.v:5992$1593_Y + end + attribute \src "ls180.v:5993.107-5993.152" + cell $eq $eq$ls180.v:5993$1597 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [5:0] + connect \B 5'11000 + connect \Y $eq$ls180.v:5993$1597_Y + end + attribute \src "ls180.v:5995.100-5995.145" + cell $eq $eq$ls180.v:5995$1600 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [5:0] + connect \B 5'11001 + connect \Y $eq$ls180.v:5995$1600_Y + end + attribute \src "ls180.v:5996.103-5996.148" + cell $eq $eq$ls180.v:5996$1604 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [5:0] + connect \B 5'11001 + connect \Y $eq$ls180.v:5996$1604_Y + end + attribute \src "ls180.v:5998.101-5998.146" + cell $eq $eq$ls180.v:5998$1607 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [5:0] + connect \B 5'11010 + connect \Y $eq$ls180.v:5998$1607_Y + end + attribute \src "ls180.v:5999.104-5999.149" + cell $eq $eq$ls180.v:5999$1611 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [5:0] + connect \B 5'11010 + connect \Y $eq$ls180.v:5999$1611_Y + end + attribute \src "ls180.v:6001.104-6001.149" + cell $eq $eq$ls180.v:6001$1614 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [5:0] + connect \B 5'11011 + connect \Y $eq$ls180.v:6001$1614_Y + end + attribute \src "ls180.v:6002.107-6002.152" + cell $eq $eq$ls180.v:6002$1618 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [5:0] + connect \B 5'11011 + connect \Y $eq$ls180.v:6002$1618_Y + end + attribute \src "ls180.v:6004.104-6004.149" + cell $eq $eq$ls180.v:6004$1621 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [5:0] + connect \B 5'11100 + connect \Y $eq$ls180.v:6004$1621_Y + end + attribute \src "ls180.v:6005.107-6005.152" + cell $eq $eq$ls180.v:6005$1625 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [5:0] + connect \B 5'11100 + connect \Y $eq$ls180.v:6005$1625_Y + end + attribute \src "ls180.v:6007.103-6007.148" + cell $eq $eq$ls180.v:6007$1628 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [5:0] + connect \B 5'11101 + connect \Y $eq$ls180.v:6007$1628_Y + end + attribute \src "ls180.v:6008.106-6008.151" + cell $eq $eq$ls180.v:6008$1632 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [5:0] + connect \B 5'11101 + connect \Y $eq$ls180.v:6008$1632_Y + end + attribute \src "ls180.v:6010.103-6010.148" + cell $eq $eq$ls180.v:6010$1635 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [5:0] + connect \B 5'11110 + connect \Y $eq$ls180.v:6010$1635_Y + end + attribute \src "ls180.v:6011.106-6011.151" + cell $eq $eq$ls180.v:6011$1639 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [5:0] + connect \B 5'11110 + connect \Y $eq$ls180.v:6011$1639_Y + end + attribute \src "ls180.v:6013.103-6013.148" + cell $eq $eq$ls180.v:6013$1642 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [5:0] + connect \B 5'11111 + connect \Y $eq$ls180.v:6013$1642_Y + end + attribute \src "ls180.v:6014.106-6014.151" + cell $eq $eq$ls180.v:6014$1646 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [5:0] + connect \B 5'11111 + connect \Y $eq$ls180.v:6014$1646_Y + end + attribute \src "ls180.v:6016.103-6016.148" + cell $eq $eq$ls180.v:6016$1649 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [5:0] + connect \B 6'100000 + connect \Y $eq$ls180.v:6016$1649_Y + end + attribute \src "ls180.v:6017.106-6017.151" + cell $eq $eq$ls180.v:6017$1653 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [5:0] + connect \B 6'100000 + connect \Y $eq$ls180.v:6017$1653_Y + end + attribute \src "ls180.v:6053.32-6053.78" + cell $eq $eq$ls180.v:6053$1655 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [13:9] + connect \B 4'1101 + connect \Y $eq$ls180.v:6053$1655_Y + end + attribute \src "ls180.v:6055.100-6055.144" + cell $eq $eq$ls180.v:6055$1657 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [4:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6055$1657_Y + end + attribute \src "ls180.v:6056.103-6056.147" + cell $eq $eq$ls180.v:6056$1661 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [4:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6056$1661_Y + end + attribute \src "ls180.v:6058.100-6058.144" + cell $eq $eq$ls180.v:6058$1664 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [4:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6058$1664_Y + end + attribute \src "ls180.v:6059.103-6059.147" + cell $eq $eq$ls180.v:6059$1668 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [4:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6059$1668_Y + end + attribute \src "ls180.v:6061.100-6061.144" + cell $eq $eq$ls180.v:6061$1671 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [4:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6061$1671_Y + end + attribute \src "ls180.v:6062.103-6062.147" + cell $eq $eq$ls180.v:6062$1675 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [4:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6062$1675_Y + end + attribute \src "ls180.v:6064.100-6064.144" + cell $eq $eq$ls180.v:6064$1678 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [4:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6064$1678_Y + end + attribute \src "ls180.v:6065.103-6065.147" + cell $eq $eq$ls180.v:6065$1682 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [4:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6065$1682_Y + end + attribute \src "ls180.v:6067.100-6067.144" + cell $eq $eq$ls180.v:6067$1685 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [4:0] + connect \B 3'100 + connect \Y $eq$ls180.v:6067$1685_Y + end + attribute \src "ls180.v:6068.103-6068.147" + cell $eq $eq$ls180.v:6068$1689 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [4:0] + connect \B 3'100 + connect \Y $eq$ls180.v:6068$1689_Y + end + attribute \src "ls180.v:6070.100-6070.144" + cell $eq $eq$ls180.v:6070$1692 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [4:0] + connect \B 3'101 + connect \Y $eq$ls180.v:6070$1692_Y + end + attribute \src "ls180.v:6071.103-6071.147" + cell $eq $eq$ls180.v:6071$1696 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [4:0] + connect \B 3'101 + connect \Y $eq$ls180.v:6071$1696_Y + end + attribute \src "ls180.v:6073.100-6073.144" + cell $eq $eq$ls180.v:6073$1699 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [4:0] + connect \B 3'110 + connect \Y $eq$ls180.v:6073$1699_Y + end + attribute \src "ls180.v:6074.103-6074.147" + cell $eq $eq$ls180.v:6074$1703 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [4:0] + connect \B 3'110 + connect \Y $eq$ls180.v:6074$1703_Y + end + attribute \src "ls180.v:6076.100-6076.144" + cell $eq $eq$ls180.v:6076$1706 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [4:0] + connect \B 3'111 + connect \Y $eq$ls180.v:6076$1706_Y + end + attribute \src "ls180.v:6077.103-6077.147" + cell $eq $eq$ls180.v:6077$1710 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [4:0] + connect \B 3'111 + connect \Y $eq$ls180.v:6077$1710_Y + end + attribute \src "ls180.v:6079.102-6079.146" + cell $eq $eq$ls180.v:6079$1713 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [4:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:6079$1713_Y + end + attribute \src "ls180.v:6080.105-6080.149" + cell $eq $eq$ls180.v:6080$1717 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [4:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:6080$1717_Y + end + attribute \src "ls180.v:6082.102-6082.146" + cell $eq $eq$ls180.v:6082$1720 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [4:0] + connect \B 4'1001 + connect \Y $eq$ls180.v:6082$1720_Y + end + attribute \src "ls180.v:6083.105-6083.149" + cell $eq $eq$ls180.v:6083$1724 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [4:0] + connect \B 4'1001 + connect \Y $eq$ls180.v:6083$1724_Y + end + attribute \src "ls180.v:6085.102-6085.147" + cell $eq $eq$ls180.v:6085$1727 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [4:0] + connect \B 4'1010 + connect \Y $eq$ls180.v:6085$1727_Y + end + attribute \src "ls180.v:6086.105-6086.150" + cell $eq $eq$ls180.v:6086$1731 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [4:0] + connect \B 4'1010 + connect \Y $eq$ls180.v:6086$1731_Y + end + attribute \src "ls180.v:6088.102-6088.147" + cell $eq $eq$ls180.v:6088$1734 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [4:0] + connect \B 4'1011 + connect \Y $eq$ls180.v:6088$1734_Y + end + attribute \src "ls180.v:6089.105-6089.150" + cell $eq $eq$ls180.v:6089$1738 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [4:0] + connect \B 4'1011 + connect \Y $eq$ls180.v:6089$1738_Y + end + attribute \src "ls180.v:6091.102-6091.147" + cell $eq $eq$ls180.v:6091$1741 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [4:0] + connect \B 4'1100 + connect \Y $eq$ls180.v:6091$1741_Y + end + attribute \src "ls180.v:6092.105-6092.150" + cell $eq $eq$ls180.v:6092$1745 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [4:0] + connect \B 4'1100 + connect \Y $eq$ls180.v:6092$1745_Y + end + attribute \src "ls180.v:6094.99-6094.144" + cell $eq $eq$ls180.v:6094$1748 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [4:0] + connect \B 4'1101 + connect \Y $eq$ls180.v:6094$1748_Y + end + attribute \src "ls180.v:6095.102-6095.147" + cell $eq $eq$ls180.v:6095$1752 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [4:0] + connect \B 4'1101 + connect \Y $eq$ls180.v:6095$1752_Y + end + attribute \src "ls180.v:6097.100-6097.145" + cell $eq $eq$ls180.v:6097$1755 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [4:0] + connect \B 4'1110 + connect \Y $eq$ls180.v:6097$1755_Y + end + attribute \src "ls180.v:6098.103-6098.148" + cell $eq $eq$ls180.v:6098$1759 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [4:0] + connect \B 4'1110 + connect \Y $eq$ls180.v:6098$1759_Y + end + attribute \src "ls180.v:6100.102-6100.147" + cell $eq $eq$ls180.v:6100$1762 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [4:0] + connect \B 4'1111 + connect \Y $eq$ls180.v:6100$1762_Y + end + attribute \src "ls180.v:6101.105-6101.150" + cell $eq $eq$ls180.v:6101$1766 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [4:0] + connect \B 4'1111 + connect \Y $eq$ls180.v:6101$1766_Y + end + attribute \src "ls180.v:6103.102-6103.147" + cell $eq $eq$ls180.v:6103$1769 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [4:0] + connect \B 5'10000 + connect \Y $eq$ls180.v:6103$1769_Y + end + attribute \src "ls180.v:6104.105-6104.150" + cell $eq $eq$ls180.v:6104$1773 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [4:0] + connect \B 5'10000 + connect \Y $eq$ls180.v:6104$1773_Y + end + attribute \src "ls180.v:6106.102-6106.147" + cell $eq $eq$ls180.v:6106$1776 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [4:0] + connect \B 5'10001 + connect \Y $eq$ls180.v:6106$1776_Y + end + attribute \src "ls180.v:6107.105-6107.150" + cell $eq $eq$ls180.v:6107$1780 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [4:0] + connect \B 5'10001 + connect \Y $eq$ls180.v:6107$1780_Y + end + attribute \src "ls180.v:6109.102-6109.147" + cell $eq $eq$ls180.v:6109$1783 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [4:0] + connect \B 5'10010 + connect \Y $eq$ls180.v:6109$1783_Y + end + attribute \src "ls180.v:6110.105-6110.150" + cell $eq $eq$ls180.v:6110$1787 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [4:0] + connect \B 5'10010 + connect \Y $eq$ls180.v:6110$1787_Y + end + attribute \src "ls180.v:6132.32-6132.78" + cell $eq $eq$ls180.v:6132$1789 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [13:9] + connect \B 4'1010 + connect \Y $eq$ls180.v:6132$1789_Y + end + attribute \src "ls180.v:6134.102-6134.146" + cell $eq $eq$ls180.v:6134$1791 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [1:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6134$1791_Y + end + attribute \src "ls180.v:6135.105-6135.149" + cell $eq $eq$ls180.v:6135$1795 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [1:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6135$1795_Y + end + attribute \src "ls180.v:6137.107-6137.151" + cell $eq $eq$ls180.v:6137$1798 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [1:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6137$1798_Y + end + attribute \src "ls180.v:6138.110-6138.154" + cell $eq $eq$ls180.v:6138$1802 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [1:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6138$1802_Y + end + attribute \src "ls180.v:6140.107-6140.151" + cell $eq $eq$ls180.v:6140$1805 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [1:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6140$1805_Y + end + attribute \src "ls180.v:6141.110-6141.154" + cell $eq $eq$ls180.v:6141$1809 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [1:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6141$1809_Y + end + attribute \src "ls180.v:6143.100-6143.144" + cell $eq $eq$ls180.v:6143$1812 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [1:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6143$1812_Y + end + attribute \src "ls180.v:6144.103-6144.147" + cell $eq $eq$ls180.v:6144$1816 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [1:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6144$1816_Y + end + attribute \src "ls180.v:6149.32-6149.77" + cell $eq $eq$ls180.v:6149$1818 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_adr [13:9] + connect \B 2'11 + connect \Y $eq$ls180.v:6149$1818_Y + end + attribute \src "ls180.v:6151.104-6151.148" + cell $eq $eq$ls180.v:6151$1820 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_adr [3:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6151$1820_Y + end + attribute \src "ls180.v:6152.107-6152.151" + cell $eq $eq$ls180.v:6152$1824 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_adr [3:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6152$1824_Y + end + attribute \src "ls180.v:6154.108-6154.152" + cell $eq $eq$ls180.v:6154$1827 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_adr [3:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6154$1827_Y + end + attribute \src "ls180.v:6155.111-6155.155" + cell $eq $eq$ls180.v:6155$1831 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_adr [3:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6155$1831_Y + end + attribute \src "ls180.v:6157.98-6157.142" + cell $eq $eq$ls180.v:6157$1834 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_adr [3:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6157$1834_Y + end + attribute \src "ls180.v:6158.101-6158.145" + cell $eq $eq$ls180.v:6158$1838 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_adr [3:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6158$1838_Y + end + attribute \src "ls180.v:6160.108-6160.152" + cell $eq $eq$ls180.v:6160$1841 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_adr [3:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6160$1841_Y + end + attribute \src "ls180.v:6161.111-6161.155" + cell $eq $eq$ls180.v:6161$1845 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_adr [3:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6161$1845_Y + end + attribute \src "ls180.v:6163.108-6163.152" + cell $eq $eq$ls180.v:6163$1848 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_adr [3:0] + connect \B 3'100 + connect \Y $eq$ls180.v:6163$1848_Y + end + attribute \src "ls180.v:6164.111-6164.155" + cell $eq $eq$ls180.v:6164$1852 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_adr [3:0] + connect \B 3'100 + connect \Y $eq$ls180.v:6164$1852_Y + end + attribute \src "ls180.v:6166.109-6166.153" + cell $eq $eq$ls180.v:6166$1855 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_adr [3:0] + connect \B 3'101 + connect \Y $eq$ls180.v:6166$1855_Y + end + attribute \src "ls180.v:6167.112-6167.156" + cell $eq $eq$ls180.v:6167$1859 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_adr [3:0] + connect \B 3'101 + connect \Y $eq$ls180.v:6167$1859_Y + end + attribute \src "ls180.v:6169.107-6169.151" + cell $eq $eq$ls180.v:6169$1862 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_adr [3:0] + connect \B 3'110 + connect \Y $eq$ls180.v:6169$1862_Y + end + attribute \src "ls180.v:6170.110-6170.154" + cell $eq $eq$ls180.v:6170$1866 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_adr [3:0] + connect \B 3'110 + connect \Y $eq$ls180.v:6170$1866_Y + end + attribute \src "ls180.v:6172.107-6172.151" + cell $eq $eq$ls180.v:6172$1869 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_adr [3:0] + connect \B 3'111 + connect \Y $eq$ls180.v:6172$1869_Y + end + attribute \src "ls180.v:6173.110-6173.154" + cell $eq $eq$ls180.v:6173$1873 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_adr [3:0] + connect \B 3'111 + connect \Y $eq$ls180.v:6173$1873_Y + end + attribute \src "ls180.v:6175.107-6175.151" + cell $eq $eq$ls180.v:6175$1876 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_adr [3:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:6175$1876_Y + end + attribute \src "ls180.v:6176.110-6176.154" + cell $eq $eq$ls180.v:6176$1880 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_adr [3:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:6176$1880_Y + end + attribute \src "ls180.v:6178.107-6178.151" + cell $eq $eq$ls180.v:6178$1883 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_adr [3:0] + connect \B 4'1001 + connect \Y $eq$ls180.v:6178$1883_Y + end + attribute \src "ls180.v:6179.110-6179.154" + cell $eq $eq$ls180.v:6179$1887 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_adr [3:0] + connect \B 4'1001 + connect \Y $eq$ls180.v:6179$1887_Y + end + attribute \src "ls180.v:6194.32-6194.77" + cell $eq $eq$ls180.v:6194$1889 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [13:9] + connect \B 3'111 + connect \Y $eq$ls180.v:6194$1889_Y + end + attribute \src "ls180.v:6196.99-6196.143" + cell $eq $eq$ls180.v:6196$1891 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [2:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6196$1891_Y + end + attribute \src "ls180.v:6197.102-6197.146" + cell $eq $eq$ls180.v:6197$1895 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [2:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6197$1895_Y + end + attribute \src "ls180.v:6199.99-6199.143" + cell $eq $eq$ls180.v:6199$1898 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [2:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6199$1898_Y + end + attribute \src "ls180.v:6200.102-6200.146" + cell $eq $eq$ls180.v:6200$1902 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [2:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6200$1902_Y + end + attribute \src "ls180.v:6202.97-6202.141" + cell $eq $eq$ls180.v:6202$1905 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [2:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6202$1905_Y + end + attribute \src "ls180.v:6203.100-6203.144" + cell $eq $eq$ls180.v:6203$1909 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [2:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6203$1909_Y + end + attribute \src "ls180.v:6205.96-6205.140" + cell $eq $eq$ls180.v:6205$1912 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [2:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6205$1912_Y + end + attribute \src "ls180.v:6206.99-6206.143" + cell $eq $eq$ls180.v:6206$1916 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [2:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6206$1916_Y + end + attribute \src "ls180.v:6208.95-6208.139" + cell $eq $eq$ls180.v:6208$1919 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [2:0] + connect \B 3'100 + connect \Y $eq$ls180.v:6208$1919_Y + end + attribute \src "ls180.v:6209.98-6209.142" + cell $eq $eq$ls180.v:6209$1923 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [2:0] + connect \B 3'100 + connect \Y $eq$ls180.v:6209$1923_Y + end + attribute \src "ls180.v:6211.94-6211.138" + cell $eq $eq$ls180.v:6211$1926 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [2:0] + connect \B 3'101 + connect \Y $eq$ls180.v:6211$1926_Y + end + attribute \src "ls180.v:6212.97-6212.141" + cell $eq $eq$ls180.v:6212$1930 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [2:0] + connect \B 3'101 + connect \Y $eq$ls180.v:6212$1930_Y + end + attribute \src "ls180.v:6214.100-6214.144" + cell $eq $eq$ls180.v:6214$1933 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [2:0] + connect \B 3'110 + connect \Y $eq$ls180.v:6214$1933_Y + end + attribute \src "ls180.v:6215.103-6215.147" + cell $eq $eq$ls180.v:6215$1937 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [2:0] + connect \B 3'110 + connect \Y $eq$ls180.v:6215$1937_Y + end + attribute \src "ls180.v:6234.33-6234.80" + cell $eq $eq$ls180.v:6234$1940 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [13:9] + connect \B 4'1110 + connect \Y $eq$ls180.v:6234$1940_Y + end + attribute \src "ls180.v:6236.102-6236.147" + cell $eq $eq$ls180.v:6236$1942 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [3:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6236$1942_Y + end + attribute \src "ls180.v:6237.105-6237.150" + cell $eq $eq$ls180.v:6237$1946 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [3:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6237$1946_Y + end + attribute \src "ls180.v:6239.102-6239.147" + cell $eq $eq$ls180.v:6239$1949 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [3:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6239$1949_Y + end + attribute \src "ls180.v:6240.105-6240.150" + cell $eq $eq$ls180.v:6240$1953 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [3:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6240$1953_Y + end + attribute \src "ls180.v:6242.100-6242.145" + cell $eq $eq$ls180.v:6242$1956 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [3:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6242$1956_Y + end + attribute \src "ls180.v:6243.103-6243.148" + cell $eq $eq$ls180.v:6243$1960 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [3:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6243$1960_Y + end + attribute \src "ls180.v:6245.99-6245.144" + cell $eq $eq$ls180.v:6245$1963 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [3:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6245$1963_Y + end + attribute \src "ls180.v:6246.102-6246.147" + cell $eq $eq$ls180.v:6246$1967 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [3:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6246$1967_Y + end + attribute \src "ls180.v:6248.98-6248.143" + cell $eq $eq$ls180.v:6248$1970 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [3:0] + connect \B 3'100 + connect \Y $eq$ls180.v:6248$1970_Y + end + attribute \src "ls180.v:6249.101-6249.146" + cell $eq $eq$ls180.v:6249$1974 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [3:0] + connect \B 3'100 + connect \Y $eq$ls180.v:6249$1974_Y + end + attribute \src "ls180.v:6251.97-6251.142" + cell $eq $eq$ls180.v:6251$1977 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [3:0] + connect \B 3'101 + connect \Y $eq$ls180.v:6251$1977_Y + end + attribute \src "ls180.v:6252.100-6252.145" + cell $eq $eq$ls180.v:6252$1981 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [3:0] + connect \B 3'101 + connect \Y $eq$ls180.v:6252$1981_Y + end + attribute \src "ls180.v:6254.103-6254.148" + cell $eq $eq$ls180.v:6254$1984 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [3:0] + connect \B 3'110 + connect \Y $eq$ls180.v:6254$1984_Y + end + attribute \src "ls180.v:6255.106-6255.151" + cell $eq $eq$ls180.v:6255$1988 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [3:0] + connect \B 3'110 + connect \Y $eq$ls180.v:6255$1988_Y + end + attribute \src "ls180.v:6257.106-6257.151" + cell $eq $eq$ls180.v:6257$1991 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [3:0] + connect \B 3'111 + connect \Y $eq$ls180.v:6257$1991_Y + end + attribute \src "ls180.v:6258.109-6258.154" + cell $eq $eq$ls180.v:6258$1995 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [3:0] + connect \B 3'111 + connect \Y $eq$ls180.v:6258$1995_Y + end + attribute \src "ls180.v:6260.106-6260.151" + cell $eq $eq$ls180.v:6260$1998 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [3:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:6260$1998_Y + end + attribute \src "ls180.v:6261.109-6261.154" + cell $eq $eq$ls180.v:6261$2002 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [3:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:6261$2002_Y + end + attribute \src "ls180.v:6282.33-6282.79" + cell $eq $eq$ls180.v:6282$2005 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [13:9] + connect \B 2'10 + connect \Y $eq$ls180.v:6282$2005_Y + end + attribute \src "ls180.v:6284.99-6284.144" + cell $eq $eq$ls180.v:6284$2007 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [4:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6284$2007_Y + end + attribute \src "ls180.v:6285.102-6285.147" + cell $eq $eq$ls180.v:6285$2011 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [4:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6285$2011_Y + end + attribute \src "ls180.v:6287.99-6287.144" + cell $eq $eq$ls180.v:6287$2014 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [4:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6287$2014_Y + end + attribute \src "ls180.v:6288.102-6288.147" + cell $eq $eq$ls180.v:6288$2018 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [4:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6288$2018_Y + end + attribute \src "ls180.v:6290.99-6290.144" + cell $eq $eq$ls180.v:6290$2021 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [4:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6290$2021_Y + end + attribute \src "ls180.v:6291.102-6291.147" + cell $eq $eq$ls180.v:6291$2025 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [4:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6291$2025_Y + end + attribute \src "ls180.v:6293.99-6293.144" + cell $eq $eq$ls180.v:6293$2028 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [4:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6293$2028_Y + end + attribute \src "ls180.v:6294.102-6294.147" + cell $eq $eq$ls180.v:6294$2032 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [4:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6294$2032_Y + end + attribute \src "ls180.v:6296.101-6296.146" + cell $eq $eq$ls180.v:6296$2035 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [4:0] + connect \B 3'100 + connect \Y $eq$ls180.v:6296$2035_Y + end + attribute \src "ls180.v:6297.104-6297.149" + cell $eq $eq$ls180.v:6297$2039 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [4:0] + connect \B 3'100 + connect \Y $eq$ls180.v:6297$2039_Y + end + attribute \src "ls180.v:6299.101-6299.146" + cell $eq $eq$ls180.v:6299$2042 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [4:0] + connect \B 3'101 + connect \Y $eq$ls180.v:6299$2042_Y + end + attribute \src "ls180.v:6300.104-6300.149" + cell $eq $eq$ls180.v:6300$2046 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [4:0] + connect \B 3'101 + connect \Y $eq$ls180.v:6300$2046_Y + end + attribute \src "ls180.v:6302.101-6302.146" + cell $eq $eq$ls180.v:6302$2049 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [4:0] + connect \B 3'110 + connect \Y $eq$ls180.v:6302$2049_Y + end + attribute \src "ls180.v:6303.104-6303.149" + cell $eq $eq$ls180.v:6303$2053 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [4:0] + connect \B 3'110 + connect \Y $eq$ls180.v:6303$2053_Y + end + attribute \src "ls180.v:6305.101-6305.146" + cell $eq $eq$ls180.v:6305$2056 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [4:0] + connect \B 3'111 + connect \Y $eq$ls180.v:6305$2056_Y + end + attribute \src "ls180.v:6306.104-6306.149" + cell $eq $eq$ls180.v:6306$2060 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [4:0] + connect \B 3'111 + connect \Y $eq$ls180.v:6306$2060_Y + end + attribute \src "ls180.v:6308.97-6308.142" + cell $eq $eq$ls180.v:6308$2063 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [4:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:6308$2063_Y + end + attribute \src "ls180.v:6309.100-6309.145" + cell $eq $eq$ls180.v:6309$2067 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [4:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:6309$2067_Y + end + attribute \src "ls180.v:6311.107-6311.152" + cell $eq $eq$ls180.v:6311$2070 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [4:0] + connect \B 4'1001 + connect \Y $eq$ls180.v:6311$2070_Y + end + attribute \src "ls180.v:6312.110-6312.155" + cell $eq $eq$ls180.v:6312$2074 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [4:0] + connect \B 4'1001 + connect \Y $eq$ls180.v:6312$2074_Y + end + attribute \src "ls180.v:6314.100-6314.146" + cell $eq $eq$ls180.v:6314$2077 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [4:0] + connect \B 4'1010 + connect \Y $eq$ls180.v:6314$2077_Y + end + attribute \src "ls180.v:6315.103-6315.149" + cell $eq $eq$ls180.v:6315$2081 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [4:0] + connect \B 4'1010 + connect \Y $eq$ls180.v:6315$2081_Y + end + attribute \src "ls180.v:6317.100-6317.146" + cell $eq $eq$ls180.v:6317$2084 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [4:0] + connect \B 4'1011 + connect \Y $eq$ls180.v:6317$2084_Y + end + attribute \src "ls180.v:6318.103-6318.149" + cell $eq $eq$ls180.v:6318$2088 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [4:0] + connect \B 4'1011 + connect \Y $eq$ls180.v:6318$2088_Y + end + attribute \src "ls180.v:6320.100-6320.146" + cell $eq $eq$ls180.v:6320$2091 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [4:0] + connect \B 4'1100 + connect \Y $eq$ls180.v:6320$2091_Y + end + attribute \src "ls180.v:6321.103-6321.149" + cell $eq $eq$ls180.v:6321$2095 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [4:0] + connect \B 4'1100 + connect \Y $eq$ls180.v:6321$2095_Y + end + attribute \src "ls180.v:6323.100-6323.146" + cell $eq $eq$ls180.v:6323$2098 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [4:0] + connect \B 4'1101 + connect \Y $eq$ls180.v:6323$2098_Y + end + attribute \src "ls180.v:6324.103-6324.149" + cell $eq $eq$ls180.v:6324$2102 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [4:0] + connect \B 4'1101 + connect \Y $eq$ls180.v:6324$2102_Y + end + attribute \src "ls180.v:6326.112-6326.158" + cell $eq $eq$ls180.v:6326$2105 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [4:0] + connect \B 4'1110 + connect \Y $eq$ls180.v:6326$2105_Y + end + attribute \src "ls180.v:6327.115-6327.161" + cell $eq $eq$ls180.v:6327$2109 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [4:0] + connect \B 4'1110 + connect \Y $eq$ls180.v:6327$2109_Y + end + attribute \src "ls180.v:6329.113-6329.159" + cell $eq $eq$ls180.v:6329$2112 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [4:0] + connect \B 4'1111 + connect \Y $eq$ls180.v:6329$2112_Y + end + attribute \src "ls180.v:6330.116-6330.162" + cell $eq $eq$ls180.v:6330$2116 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [4:0] + connect \B 4'1111 + connect \Y $eq$ls180.v:6330$2116_Y + end + attribute \src "ls180.v:6332.104-6332.150" + cell $eq $eq$ls180.v:6332$2119 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [4:0] + connect \B 5'10000 + connect \Y $eq$ls180.v:6332$2119_Y + end + attribute \src "ls180.v:6333.107-6333.153" + cell $eq $eq$ls180.v:6333$2123 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [4:0] + connect \B 5'10000 + connect \Y $eq$ls180.v:6333$2123_Y + end + attribute \src "ls180.v:6350.33-6350.79" + cell $eq $eq$ls180.v:6350$2125 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [13:9] + connect \B 3'101 + connect \Y $eq$ls180.v:6350$2125_Y + end + attribute \src "ls180.v:6352.90-6352.135" + cell $eq $eq$ls180.v:6352$2127 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [2:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6352$2127_Y + end + attribute \src "ls180.v:6353.93-6353.138" + cell $eq $eq$ls180.v:6353$2131 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [2:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6353$2131_Y + end + attribute \src "ls180.v:6355.100-6355.145" + cell $eq $eq$ls180.v:6355$2134 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [2:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6355$2134_Y + end + attribute \src "ls180.v:6356.103-6356.148" + cell $eq $eq$ls180.v:6356$2138 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [2:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6356$2138_Y + end + attribute \src "ls180.v:6358.101-6358.146" + cell $eq $eq$ls180.v:6358$2141 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [2:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6358$2141_Y + end + attribute \src "ls180.v:6359.104-6359.149" + cell $eq $eq$ls180.v:6359$2145 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [2:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6359$2145_Y + end + attribute \src "ls180.v:6361.105-6361.150" + cell $eq $eq$ls180.v:6361$2148 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [2:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6361$2148_Y + end + attribute \src "ls180.v:6362.108-6362.153" + cell $eq $eq$ls180.v:6362$2152 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [2:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6362$2152_Y + end + attribute \src "ls180.v:6364.106-6364.151" + cell $eq $eq$ls180.v:6364$2155 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [2:0] + connect \B 3'100 + connect \Y $eq$ls180.v:6364$2155_Y + end + attribute \src "ls180.v:6365.109-6365.154" + cell $eq $eq$ls180.v:6365$2159 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [2:0] + connect \B 3'100 + connect \Y $eq$ls180.v:6365$2159_Y + end + attribute \src "ls180.v:6367.104-6367.149" + cell $eq $eq$ls180.v:6367$2162 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [2:0] + connect \B 3'101 + connect \Y $eq$ls180.v:6367$2162_Y + end + attribute \src "ls180.v:6368.107-6368.152" + cell $eq $eq$ls180.v:6368$2166 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [2:0] + connect \B 3'101 + connect \Y $eq$ls180.v:6368$2166_Y + end + attribute \src "ls180.v:6370.101-6370.146" + cell $eq $eq$ls180.v:6370$2169 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [2:0] + connect \B 3'110 + connect \Y $eq$ls180.v:6370$2169_Y + end + attribute \src "ls180.v:6371.104-6371.149" + cell $eq $eq$ls180.v:6371$2173 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [2:0] + connect \B 3'110 + connect \Y $eq$ls180.v:6371$2173_Y + end + attribute \src "ls180.v:6373.100-6373.145" + cell $eq $eq$ls180.v:6373$2176 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [2:0] + connect \B 3'111 + connect \Y $eq$ls180.v:6373$2176_Y + end + attribute \src "ls180.v:6374.103-6374.148" + cell $eq $eq$ls180.v:6374$2180 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [2:0] + connect \B 3'111 + connect \Y $eq$ls180.v:6374$2180_Y + end + attribute \src "ls180.v:6384.33-6384.79" + cell $eq $eq$ls180.v:6384$2182 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_adr [13:9] + connect \B 3'100 + connect \Y $eq$ls180.v:6384$2182_Y + end + attribute \src "ls180.v:6386.106-6386.151" + cell $eq $eq$ls180.v:6386$2184 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_adr [1:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6386$2184_Y + end + attribute \src "ls180.v:6387.109-6387.154" + cell $eq $eq$ls180.v:6387$2188 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_adr [1:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6387$2188_Y + end + attribute \src "ls180.v:6389.106-6389.151" + cell $eq $eq$ls180.v:6389$2191 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_adr [1:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6389$2191_Y + end + attribute \src "ls180.v:6390.109-6390.154" + cell $eq $eq$ls180.v:6390$2195 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_adr [1:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6390$2195_Y + end + attribute \src "ls180.v:6392.106-6392.151" + cell $eq $eq$ls180.v:6392$2198 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_adr [1:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6392$2198_Y + end + attribute \src "ls180.v:6393.109-6393.154" + cell $eq $eq$ls180.v:6393$2202 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_adr [1:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6393$2202_Y + end + attribute \src "ls180.v:6395.106-6395.151" + cell $eq $eq$ls180.v:6395$2205 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_adr [1:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6395$2205_Y + end + attribute \src "ls180.v:6396.109-6396.154" + cell $eq $eq$ls180.v:6396$2209 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_adr [1:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6396$2209_Y + end + attribute \src "ls180.v:6774.41-6774.81" + cell $eq $eq$ls180.v:6774$2245 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_payload_addr [10:9] + connect \B 1'0 + connect \Y $eq$ls180.v:6774$2245_Y + end + attribute \src "ls180.v:6774.144-6774.177" + cell $eq $eq$ls180.v:6774$2246 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin1_grant + connect \B 1'0 + connect \Y $eq$ls180.v:6774$2246_Y + end + attribute \src "ls180.v:6774.219-6774.252" + cell $eq $eq$ls180.v:6774$2249 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin2_grant + connect \B 1'0 + connect \Y $eq$ls180.v:6774$2249_Y + end + attribute \src "ls180.v:6774.294-6774.327" + cell $eq $eq$ls180.v:6774$2252 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin3_grant + connect \B 1'0 + connect \Y $eq$ls180.v:6774$2252_Y + end + attribute \src "ls180.v:6798.41-6798.81" + cell $eq $eq$ls180.v:6798$2261 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_payload_addr [10:9] + connect \B 1'1 + connect \Y $eq$ls180.v:6798$2261_Y + end + attribute \src "ls180.v:6798.144-6798.177" + cell $eq $eq$ls180.v:6798$2262 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin0_grant + connect \B 1'0 + connect \Y $eq$ls180.v:6798$2262_Y + end + attribute \src "ls180.v:6798.219-6798.252" + cell $eq $eq$ls180.v:6798$2265 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin2_grant + connect \B 1'0 + connect \Y $eq$ls180.v:6798$2265_Y + end + attribute \src "ls180.v:6798.294-6798.327" + cell $eq $eq$ls180.v:6798$2268 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin3_grant + connect \B 1'0 + connect \Y $eq$ls180.v:6798$2268_Y + end + attribute \src "ls180.v:6822.41-6822.81" + cell $eq $eq$ls180.v:6822$2277 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_payload_addr [10:9] + connect \B 2'10 + connect \Y $eq$ls180.v:6822$2277_Y + end + attribute \src "ls180.v:6822.144-6822.177" + cell $eq $eq$ls180.v:6822$2278 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin0_grant + connect \B 1'0 + connect \Y $eq$ls180.v:6822$2278_Y + end + attribute \src "ls180.v:6822.219-6822.252" + cell $eq $eq$ls180.v:6822$2281 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin1_grant + connect \B 1'0 + connect \Y $eq$ls180.v:6822$2281_Y + end + attribute \src "ls180.v:6822.294-6822.327" + cell $eq $eq$ls180.v:6822$2284 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin3_grant + connect \B 1'0 + connect \Y $eq$ls180.v:6822$2284_Y + end + attribute \src "ls180.v:6846.41-6846.81" + cell $eq $eq$ls180.v:6846$2293 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_payload_addr [10:9] + connect \B 2'11 + connect \Y $eq$ls180.v:6846$2293_Y + end + attribute \src "ls180.v:6846.144-6846.177" + cell $eq $eq$ls180.v:6846$2294 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin0_grant + connect \B 1'0 + connect \Y $eq$ls180.v:6846$2294_Y + end + attribute \src "ls180.v:6846.219-6846.252" + cell $eq $eq$ls180.v:6846$2297 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin1_grant + connect \B 1'0 + connect \Y $eq$ls180.v:6846$2297_Y + end + attribute \src "ls180.v:6846.294-6846.327" + cell $eq $eq$ls180.v:6846$2300 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin2_grant + connect \B 1'0 + connect \Y $eq$ls180.v:6846$2300_Y + end + attribute \src "ls180.v:7445.8-7445.38" + cell $eq $eq$ls180.v:7445$2409 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_value + connect \B 1'0 + connect \Y $eq$ls180.v:7445$2409_Y + end + attribute \src "ls180.v:7476.8-7476.42" + cell $eq $eq$ls180.v:7476$2417 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_postponer_count + connect \B 1'0 + connect \Y $eq$ls180.v:7476$2417_Y + end + attribute \src "ls180.v:7496.38-7496.74" + cell $eq $eq$ls180.v:7496$2420 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_sequencer_counter + connect \B 1'0 + connect \Y $eq$ls180.v:7496$2420_Y + end + attribute \src "ls180.v:7503.7-7503.43" + cell $eq $eq$ls180.v:7503$2422 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \main_sdram_sequencer_counter + connect \B 2'10 + connect \Y $eq$ls180.v:7503$2422_Y + end + attribute \src "ls180.v:7510.7-7510.43" + cell $eq $eq$ls180.v:7510$2423 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \main_sdram_sequencer_counter + connect \B 4'1000 + connect \Y $eq$ls180.v:7510$2423_Y + end + attribute \src "ls180.v:7518.7-7518.43" + cell $eq $eq$ls180.v:7518$2424 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \main_sdram_sequencer_counter + connect \B 4'1000 + connect \Y $eq$ls180.v:7518$2424_Y + end + attribute \src "ls180.v:7570.9-7570.54" + cell $eq $eq$ls180.v:7570$2442 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_twtpcon_count + connect \B 1'1 + connect \Y $eq$ls180.v:7570$2442_Y + end + attribute \src "ls180.v:7616.9-7616.54" + cell $eq $eq$ls180.v:7616$2458 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_twtpcon_count + connect \B 1'1 + connect \Y $eq$ls180.v:7616$2458_Y + end + attribute \src "ls180.v:7662.9-7662.54" + cell $eq $eq$ls180.v:7662$2474 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_twtpcon_count + connect \B 1'1 + connect \Y $eq$ls180.v:7662$2474_Y + end + attribute \src "ls180.v:7708.9-7708.54" + cell $eq $eq$ls180.v:7708$2490 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_twtpcon_count + connect \B 1'1 + connect \Y $eq$ls180.v:7708$2490_Y + end + attribute \src "ls180.v:7858.9-7858.41" + cell $eq $eq$ls180.v:7858$2502 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_tccdcon_count + connect \B 1'1 + connect \Y $eq$ls180.v:7858$2502_Y + end + attribute \src "ls180.v:7873.9-7873.41" + cell $eq $eq$ls180.v:7873$2505 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_twtrcon_count + connect \B 1'1 + connect \Y $eq$ls180.v:7873$2505_Y + end + attribute \src "ls180.v:7879.49-7879.82" + cell $eq $eq$ls180.v:7879$2506 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin0_grant + connect \B 1'0 + connect \Y $eq$ls180.v:7879$2506_Y + end + attribute \src "ls180.v:7879.131-7879.164" + cell $eq $eq$ls180.v:7879$2509 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin1_grant + connect \B 1'0 + connect \Y $eq$ls180.v:7879$2509_Y + end + attribute \src "ls180.v:7879.213-7879.246" + cell $eq $eq$ls180.v:7879$2512 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin2_grant + connect \B 1'0 + connect \Y $eq$ls180.v:7879$2512_Y + end + attribute \src "ls180.v:7879.295-7879.328" + cell $eq $eq$ls180.v:7879$2515 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin3_grant + connect \B 1'0 + connect \Y $eq$ls180.v:7879$2515_Y + end + attribute \src "ls180.v:7880.50-7880.83" + cell $eq $eq$ls180.v:7880$2518 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin0_grant + connect \B 1'0 + connect \Y $eq$ls180.v:7880$2518_Y + end + attribute \src "ls180.v:7880.132-7880.165" + cell $eq $eq$ls180.v:7880$2521 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin1_grant + connect \B 1'0 + connect \Y $eq$ls180.v:7880$2521_Y + end + attribute \src "ls180.v:7880.214-7880.247" + cell $eq $eq$ls180.v:7880$2524 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin2_grant + connect \B 1'0 + connect \Y $eq$ls180.v:7880$2524_Y + end + attribute \src "ls180.v:7880.296-7880.329" + cell $eq $eq$ls180.v:7880$2527 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin3_grant + connect \B 1'0 + connect \Y $eq$ls180.v:7880$2527_Y + end + attribute \src "ls180.v:7915.9-7915.33" + cell $eq $eq$ls180.v:7915$2539 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \main_tx_bitcount + connect \B 4'1000 + connect \Y $eq$ls180.v:7915$2539_Y + end + attribute \src "ls180.v:7918.10-7918.34" + cell $eq $eq$ls180.v:7918$2540 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \main_tx_bitcount + connect \B 4'1001 + connect \Y $eq$ls180.v:7918$2540_Y + end + attribute \src "ls180.v:7944.9-7944.33" + cell $eq $eq$ls180.v:7944$2546 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_rx_bitcount + connect \B 1'0 + connect \Y $eq$ls180.v:7944$2546_Y + end + attribute \src "ls180.v:7949.10-7949.34" + cell $eq $eq$ls180.v:7949$2547 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \main_rx_bitcount + connect \B 4'1001 + connect \Y $eq$ls180.v:7949$2547_Y + end + attribute \src "ls180.v:8121.9-8121.53" + cell $eq $eq$ls180.v:8121$2591 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_cmdr_converter_demux + connect \B 3'111 + connect \Y $eq$ls180.v:8121$2591_Y + end + attribute \src "ls180.v:8202.9-8202.54" + cell $eq $eq$ls180.v:8202$2603 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_crcr_converter_demux + connect \B 3'111 + connect \Y $eq$ls180.v:8202$2603_Y + end + attribute \src "ls180.v:8281.9-8281.55" + cell $eq $eq$ls180.v:8281$2615 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_datar_converter_demux + connect \B 1'1 + connect \Y $eq$ls180.v:8281$2615_Y + end + attribute \src "ls180.v:8504.9-8504.49" + cell $eq $eq$ls180.v:8504$2648 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_converter_demux + connect \B 2'11 + connect \Y $eq$ls180.v:8504$2648_Y + end + attribute \src "ls180.v:8080.8-8080.54" + cell $ge $ge$ls180.v:8080$2583 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 1 + connect \A \main_pwm0_counter + connect \B $sub$ls180.v:8080$2582_Y + connect \Y $ge$ls180.v:8080$2583_Y + end + attribute \src "ls180.v:8094.8-8094.54" + cell $ge $ge$ls180.v:8094$2587 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 1 + connect \A \main_pwm1_counter + connect \B $sub$ls180.v:8094$2586_Y + connect \Y $ge$ls180.v:8094$2587_Y + end + attribute \src "ls180.v:5041.47-5041.83" + cell $gt $gt$ls180.v:5041$906 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_cnt + connect \B 3'111 + connect \Y $gt$ls180.v:5041$906_Y + end + attribute \src "ls180.v:5047.7-5047.43" + cell $lt $lt$ls180.v:5047$909 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_cnt + connect \B 4'1000 + connect \Y $lt$ls180.v:5047$909_Y + end + attribute \src "ls180.v:8075.8-8075.43" + cell $lt $lt$ls180.v:8075$2581 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 1 + connect \A \main_pwm0_counter + connect \B \main_pwm0_width + connect \Y $lt$ls180.v:8075$2581_Y + end + attribute \src "ls180.v:8089.8-8089.43" + cell $lt $lt$ls180.v:8089$2585 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 1 + connect \A \main_pwm1_counter + connect \B \main_pwm1_width + connect \Y $lt$ls180.v:8089$2585_Y + end + attribute \src "ls180.v:9989.33-9989.36" + cell $memrd $memrd$\mem$ls180.v:9989$2695 + parameter \ABITS 7 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem" + parameter \TRANSPARENT 0 + parameter \WIDTH 32 + connect \ADDR \memadr + connect \CLK 1'x + connect \DATA $memrd$\mem$ls180.v:9989$2695_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10000.12-10000.19" + cell $memrd $memrd$\storage$ls180.v:10000$2700 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage" + parameter \TRANSPARENT 0 + parameter \WIDTH 25 + connect \ADDR \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage$ls180.v:10000$2700_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10007.68-10007.75" + cell $memrd $memrd$\storage$ls180.v:10007$2702 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage" + parameter \TRANSPARENT 0 + parameter \WIDTH 25 + connect \ADDR \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage$ls180.v:10007$2702_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10014.14-10014.23" + cell $memrd $memrd$\storage_1$ls180.v:10014$2707 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_1" + parameter \TRANSPARENT 0 + parameter \WIDTH 25 + connect \ADDR \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_1$ls180.v:10014$2707_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10021.68-10021.77" + cell $memrd $memrd$\storage_1$ls180.v:10021$2709 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_1" + parameter \TRANSPARENT 0 + parameter \WIDTH 25 + connect \ADDR \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_1$ls180.v:10021$2709_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10028.14-10028.23" + cell $memrd $memrd$\storage_2$ls180.v:10028$2714 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_2" + parameter \TRANSPARENT 0 + parameter \WIDTH 25 + connect \ADDR \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_2$ls180.v:10028$2714_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10035.68-10035.77" + cell $memrd $memrd$\storage_2$ls180.v:10035$2716 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_2" + parameter \TRANSPARENT 0 + parameter \WIDTH 25 + connect \ADDR \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_2$ls180.v:10035$2716_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10042.14-10042.23" + cell $memrd $memrd$\storage_3$ls180.v:10042$2721 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_3" + parameter \TRANSPARENT 0 + parameter \WIDTH 25 + connect \ADDR \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_3$ls180.v:10042$2721_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10049.68-10049.77" + cell $memrd $memrd$\storage_3$ls180.v:10049$2723 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_3" + parameter \TRANSPARENT 0 + parameter \WIDTH 25 + connect \ADDR \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_3$ls180.v:10049$2723_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10057.14-10057.23" + cell $memrd $memrd$\storage_4$ls180.v:10057$2728 + parameter \ABITS 4 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_4" + parameter \TRANSPARENT 0 + parameter \WIDTH 10 + connect \ADDR \main_uart_tx_fifo_wrport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_4$ls180.v:10057$2728_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10062.15-10062.24" + cell $memrd $memrd$\storage_4$ls180.v:10062$2730 + parameter \ABITS 4 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_4" + parameter \TRANSPARENT 0 + parameter \WIDTH 10 + connect \ADDR \main_uart_tx_fifo_rdport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_4$ls180.v:10062$2730_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10074.14-10074.23" + cell $memrd $memrd$\storage_5$ls180.v:10074$2735 + parameter \ABITS 4 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_5" + parameter \TRANSPARENT 0 + parameter \WIDTH 10 + connect \ADDR \main_uart_rx_fifo_wrport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_5$ls180.v:10074$2735_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10079.15-10079.24" + cell $memrd $memrd$\storage_5$ls180.v:10079$2737 + parameter \ABITS 4 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_5" + parameter \TRANSPARENT 0 + parameter \WIDTH 10 + connect \ADDR \main_uart_rx_fifo_rdport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_5$ls180.v:10079$2737_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10090.14-10090.23" + cell $memrd $memrd$\storage_6$ls180.v:10090$2742 + parameter \ABITS 5 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_6" + parameter \TRANSPARENT 0 + parameter \WIDTH 10 + connect \ADDR \main_sdblock2mem_fifo_wrport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_6$ls180.v:10090$2742_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10097.45-10097.54" + cell $memrd $memrd$\storage_6$ls180.v:10097$2744 + parameter \ABITS 5 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_6" + parameter \TRANSPARENT 0 + parameter \WIDTH 10 + connect \ADDR \main_sdblock2mem_fifo_rdport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_6$ls180.v:10097$2744_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10104.14-10104.23" + cell $memrd $memrd$\storage_7$ls180.v:10104$2749 + parameter \ABITS 5 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_7" + parameter \TRANSPARENT 0 + parameter \WIDTH 10 + connect \ADDR \main_sdmem2block_fifo_wrport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_7$ls180.v:10104$2749_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10111.45-10111.54" + cell $memrd $memrd$\storage_7$ls180.v:10111$2751 + parameter \ABITS 5 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_7" + parameter \TRANSPARENT 0 + parameter \WIDTH 10 + connect \ADDR \main_sdmem2block_fifo_rdport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_7$ls180.v:10111$2751_DATA + connect \EN 1'x + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem$ls180.v:0$2753 + parameter \ABITS 7 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem" + parameter \PRIORITY 2753 + parameter \WIDTH 32 + connect \ADDR $memwr$\mem$ls180.v:9979$1_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem$ls180.v:9979$1_DATA + connect \EN $memwr$\mem$ls180.v:9979$1_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem$ls180.v:0$2754 + parameter \ABITS 7 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem" + parameter \PRIORITY 2754 + parameter \WIDTH 32 + connect \ADDR $memwr$\mem$ls180.v:9981$2_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem$ls180.v:9981$2_DATA + connect \EN $memwr$\mem$ls180.v:9981$2_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem$ls180.v:0$2755 + parameter \ABITS 7 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem" + parameter \PRIORITY 2755 + parameter \WIDTH 32 + connect \ADDR $memwr$\mem$ls180.v:9983$3_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem$ls180.v:9983$3_DATA + connect \EN $memwr$\mem$ls180.v:9983$3_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem$ls180.v:0$2756 + parameter \ABITS 7 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem" + parameter \PRIORITY 2756 + parameter \WIDTH 32 + connect \ADDR $memwr$\mem$ls180.v:9985$4_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem$ls180.v:9985$4_DATA + connect \EN $memwr$\mem$ls180.v:9985$4_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\storage$ls180.v:0$2757 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage" + parameter \PRIORITY 2757 + parameter \WIDTH 25 + connect \ADDR $memwr$\storage$ls180.v:9999$5_ADDR + connect \CLK 1'x + connect \DATA $memwr$\storage$ls180.v:9999$5_DATA + connect \EN $memwr$\storage$ls180.v:9999$5_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\storage_1$ls180.v:0$2758 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_1" + parameter \PRIORITY 2758 + parameter \WIDTH 25 + connect \ADDR $memwr$\storage_1$ls180.v:10013$6_ADDR + connect \CLK 1'x + connect \DATA $memwr$\storage_1$ls180.v:10013$6_DATA + connect \EN $memwr$\storage_1$ls180.v:10013$6_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\storage_2$ls180.v:0$2759 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_2" + parameter \PRIORITY 2759 + parameter \WIDTH 25 + connect \ADDR $memwr$\storage_2$ls180.v:10027$7_ADDR + connect \CLK 1'x + connect \DATA $memwr$\storage_2$ls180.v:10027$7_DATA + connect \EN $memwr$\storage_2$ls180.v:10027$7_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\storage_3$ls180.v:0$2760 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_3" + parameter \PRIORITY 2760 + parameter \WIDTH 25 + connect \ADDR $memwr$\storage_3$ls180.v:10041$8_ADDR + connect \CLK 1'x + connect \DATA $memwr$\storage_3$ls180.v:10041$8_DATA + connect \EN $memwr$\storage_3$ls180.v:10041$8_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\storage_4$ls180.v:0$2761 + parameter \ABITS 4 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_4" + parameter \PRIORITY 2761 + parameter \WIDTH 10 + connect \ADDR $memwr$\storage_4$ls180.v:10056$9_ADDR + connect \CLK 1'x + connect \DATA $memwr$\storage_4$ls180.v:10056$9_DATA + connect \EN $memwr$\storage_4$ls180.v:10056$9_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\storage_5$ls180.v:0$2762 + parameter \ABITS 4 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_5" + parameter \PRIORITY 2762 + parameter \WIDTH 10 + connect \ADDR $memwr$\storage_5$ls180.v:10073$10_ADDR + connect \CLK 1'x + connect \DATA $memwr$\storage_5$ls180.v:10073$10_DATA + connect \EN $memwr$\storage_5$ls180.v:10073$10_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\storage_6$ls180.v:0$2763 + parameter \ABITS 5 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_6" + parameter \PRIORITY 2763 + parameter \WIDTH 10 + connect \ADDR $memwr$\storage_6$ls180.v:10089$11_ADDR + connect \CLK 1'x + connect \DATA $memwr$\storage_6$ls180.v:10089$11_DATA + connect \EN $memwr$\storage_6$ls180.v:10089$11_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\storage_7$ls180.v:0$2764 + parameter \ABITS 5 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_7" + parameter \PRIORITY 2764 + parameter \WIDTH 10 + connect \ADDR $memwr$\storage_7$ls180.v:10103$12_ADDR + connect \CLK 1'x + connect \DATA $memwr$\storage_7$ls180.v:10103$12_DATA + connect \EN $memwr$\storage_7$ls180.v:10103$12_EN + end + attribute \src "ls180.v:2918.41-2918.71" + cell $ne $ne$ls180.v:2918$60 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_value + connect \B 1'0 + connect \Y $ne$ls180.v:2918$60_Y + end + attribute \src "ls180.v:3079.70-3079.104" + cell $ne $ne$ls180.v:3079$74 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_sequencer_count + connect \B 1'0 + connect \Y $ne$ls180.v:3079$74_Y + end + attribute \src "ls180.v:3140.8-3140.142" + cell $ne $ne$ls180.v:3140$93 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr [21:9] + connect \B \main_sdram_bankmachine0_cmd_buffer_source_payload_addr [21:9] + connect \Y $ne$ls180.v:3140$93_Y + end + attribute \src "ls180.v:3172.75-3172.133" + cell $ne $ne$ls180.v:3172$100 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_level + connect \B 4'1000 + connect \Y $ne$ls180.v:3172$100_Y + end + attribute \src "ls180.v:3173.75-3173.133" + cell $ne $ne$ls180.v:3173$101 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_level + connect \B 1'0 + connect \Y $ne$ls180.v:3173$101_Y + end + attribute \src "ls180.v:3297.8-3297.142" + cell $ne $ne$ls180.v:3297$123 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr [21:9] + connect \B \main_sdram_bankmachine1_cmd_buffer_source_payload_addr [21:9] + connect \Y $ne$ls180.v:3297$123_Y + end + attribute \src "ls180.v:3329.75-3329.133" + cell $ne $ne$ls180.v:3329$130 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_level + connect \B 4'1000 + connect \Y $ne$ls180.v:3329$130_Y + end + attribute \src "ls180.v:3330.75-3330.133" + cell $ne $ne$ls180.v:3330$131 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_level + connect \B 1'0 + connect \Y $ne$ls180.v:3330$131_Y + end + attribute \src "ls180.v:3454.8-3454.142" + cell $ne $ne$ls180.v:3454$153 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr [21:9] + connect \B \main_sdram_bankmachine2_cmd_buffer_source_payload_addr [21:9] + connect \Y $ne$ls180.v:3454$153_Y + end + attribute \src "ls180.v:3486.75-3486.133" + cell $ne $ne$ls180.v:3486$160 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_level + connect \B 4'1000 + connect \Y $ne$ls180.v:3486$160_Y + end + attribute \src "ls180.v:3487.75-3487.133" + cell $ne $ne$ls180.v:3487$161 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_level + connect \B 1'0 + connect \Y $ne$ls180.v:3487$161_Y + end + attribute \src "ls180.v:3611.8-3611.142" + cell $ne $ne$ls180.v:3611$183 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr [21:9] + connect \B \main_sdram_bankmachine3_cmd_buffer_source_payload_addr [21:9] + connect \Y $ne$ls180.v:3611$183_Y + end + attribute \src "ls180.v:3643.75-3643.133" + cell $ne $ne$ls180.v:3643$190 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_level + connect \B 4'1000 + connect \Y $ne$ls180.v:3643$190_Y + end + attribute \src "ls180.v:3644.75-3644.133" + cell $ne $ne$ls180.v:3644$191 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_level + connect \B 1'0 + connect \Y $ne$ls180.v:3644$191_Y + end + attribute \src "ls180.v:4136.47-4136.80" + cell $ne $ne$ls180.v:4136$589 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \main_uart_tx_fifo_level0 + connect \B 5'10000 + connect \Y $ne$ls180.v:4136$589_Y + end + attribute \src "ls180.v:4137.47-4137.79" + cell $ne $ne$ls180.v:4137$590 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_tx_fifo_level0 + connect \B 1'0 + connect \Y $ne$ls180.v:4137$590_Y + end + attribute \src "ls180.v:4166.47-4166.80" + cell $ne $ne$ls180.v:4166$600 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \main_uart_rx_fifo_level0 + connect \B 5'10000 + connect \Y $ne$ls180.v:4166$600_Y + end + attribute \src "ls180.v:4167.47-4167.79" + cell $ne $ne$ls180.v:4167$601 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_rx_fifo_level0 + connect \B 1'0 + connect \Y $ne$ls180.v:4167$601_Y + end + attribute \src "ls180.v:4573.32-4573.89" + cell $ne $ne$ls180.v:4573$673 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_crcr_source_source_payload_data0 + connect \B 3'101 + connect \Y $ne$ls180.v:4573$673_Y + end + attribute \src "ls180.v:5220.10-5220.56" + cell $ne $ne$ls180.v:5220$970 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_source_payload_status + connect \B 2'10 + connect \Y $ne$ls180.v:5220$970_Y + end + attribute \src "ls180.v:5325.51-5325.87" + cell $ne $ne$ls180.v:5325$984 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_fifo_level + connect \B 6'100000 + connect \Y $ne$ls180.v:5325$984_Y + end + attribute \src "ls180.v:5326.51-5326.86" + cell $ne $ne$ls180.v:5326$985 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_fifo_level + connect \B 1'0 + connect \Y $ne$ls180.v:5326$985_Y + end + attribute \src "ls180.v:5533.51-5533.87" + cell $ne $ne$ls180.v:5533$1015 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_fifo_level + connect \B 6'100000 + connect \Y $ne$ls180.v:5533$1015_Y + end + attribute \src "ls180.v:5534.51-5534.86" + cell $ne $ne$ls180.v:5534$1016 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_fifo_level + connect \B 1'0 + connect \Y $ne$ls180.v:5534$1016_Y + end + attribute \src "ls180.v:5624.79-5624.119" + cell $ne $ne$ls180.v:5624$1027 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_libresocsim_wishbone_sel + connect \B 1'0 + connect \Y $ne$ls180.v:5624$1027_Y + end + attribute \src "ls180.v:7435.7-7435.52" + cell $ne $ne$ls180.v:7435$2404 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_bus_errors + connect \B 32'11111111111111111111111111111111 + connect \Y $ne$ls180.v:7435$2404_Y + end + attribute \src "ls180.v:7485.9-7485.43" + cell $ne $ne$ls180.v:7485$2418 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_sequencer_count + connect \B 1'0 + connect \Y $ne$ls180.v:7485$2418_Y + end + attribute \src "ls180.v:7521.8-7521.44" + cell $ne $ne$ls180.v:7521$2425 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_sequencer_counter + connect \B 1'0 + connect \Y $ne$ls180.v:7521$2425_Y + end + attribute \src "ls180.v:8424.9-8424.47" + cell $ne $ne$ls180.v:8424$2635 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_cnt + connect \B 4'1010 + connect \Y $ne$ls180.v:8424$2635_Y + end + attribute \src "ls180.v:2726.45-2726.80" + cell $not $not$ls180.v:2726$14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_libresoc_ibus_cyc + connect \Y $not$ls180.v:2726$14_Y + end + attribute \src "ls180.v:2765.61-2765.94" + cell $not $not$ls180.v:2765$19 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_converter0_skip + connect \Y $not$ls180.v:2765$19_Y + end + attribute \src "ls180.v:2766.61-2766.94" + cell $not $not$ls180.v:2766$20 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_converter0_skip + connect \Y $not$ls180.v:2766$20_Y + end + attribute \src "ls180.v:2786.45-2786.80" + cell $not $not$ls180.v:2786$25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_libresoc_dbus_cyc + connect \Y $not$ls180.v:2786$25_Y + end + attribute \src "ls180.v:2825.61-2825.94" + cell $not $not$ls180.v:2825$30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_converter1_skip + connect \Y $not$ls180.v:2825$30_Y + end + attribute \src "ls180.v:2826.61-2826.94" + cell $not $not$ls180.v:2826$31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_converter1_skip + connect \Y $not$ls180.v:2826$31_Y + end + attribute \src "ls180.v:2846.45-2846.83" + cell $not $not$ls180.v:2846$36 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_libresoc_jtag_wb_cyc + connect \Y $not$ls180.v:2846$36_Y + end + attribute \src "ls180.v:2885.61-2885.94" + cell $not $not$ls180.v:2885$41 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_converter2_skip + connect \Y $not$ls180.v:2885$41_Y + end + attribute \src "ls180.v:2886.61-2886.94" + cell $not $not$ls180.v:2886$42 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_converter2_skip + connect \Y $not$ls180.v:2886$42_Y + end + attribute \src "ls180.v:3028.34-3028.64" + cell $not $not$ls180.v:3028$66 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_command_storage [0] + connect \Y $not$ls180.v:3028$66_Y + end + attribute \src "ls180.v:3029.31-3029.61" + cell $not $not$ls180.v:3029$67 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_command_storage [1] + connect \Y $not$ls180.v:3029$67_Y + end + attribute \src "ls180.v:3030.32-3030.62" + cell $not $not$ls180.v:3030$68 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_command_storage [2] + connect \Y $not$ls180.v:3030$68_Y + end + attribute \src "ls180.v:3031.32-3031.62" + cell $not $not$ls180.v:3031$69 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_command_storage [3] + connect \Y $not$ls180.v:3031$69_Y + end + attribute \src "ls180.v:3073.33-3073.56" + cell $not $not$ls180.v:3073$72 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_timer_done0 + connect \Y $not$ls180.v:3073$72_Y + end + attribute \src "ls180.v:3174.58-3174.106" + cell $not $not$ls180.v:3174$102 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_buffer_source_valid + connect \Y $not$ls180.v:3174$102_Y + end + attribute \src "ls180.v:3228.9-3228.45" + cell $not $not$ls180.v:3228$107 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_refresh_req + connect \Y $not$ls180.v:3228$107_Y + end + attribute \src "ls180.v:3331.58-3331.106" + cell $not $not$ls180.v:3331$132 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_buffer_source_valid + connect \Y $not$ls180.v:3331$132_Y + end + attribute \src "ls180.v:3385.9-3385.45" + cell $not $not$ls180.v:3385$137 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_refresh_req + connect \Y $not$ls180.v:3385$137_Y + end + attribute \src "ls180.v:3488.58-3488.106" + cell $not $not$ls180.v:3488$162 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_buffer_source_valid + connect \Y $not$ls180.v:3488$162_Y + end + attribute \src "ls180.v:3542.9-3542.45" + cell $not $not$ls180.v:3542$167 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_refresh_req + connect \Y $not$ls180.v:3542$167_Y + end + attribute \src "ls180.v:3645.58-3645.106" + cell $not $not$ls180.v:3645$192 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_buffer_source_valid + connect \Y $not$ls180.v:3645$192_Y + end + attribute \src "ls180.v:3699.9-3699.45" + cell $not $not$ls180.v:3699$197 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_refresh_req + connect \Y $not$ls180.v:3699$197_Y + end + attribute \src "ls180.v:3741.149-3741.187" + cell $not $not$ls180.v:3741$200 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_payload_cas + connect \Y $not$ls180.v:3741$200_Y + end + attribute \src "ls180.v:3741.193-3741.230" + cell $not $not$ls180.v:3741$202 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_payload_we + connect \Y $not$ls180.v:3741$202_Y + end + attribute \src "ls180.v:3742.149-3742.187" + cell $not $not$ls180.v:3742$206 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_payload_cas + connect \Y $not$ls180.v:3742$206_Y + end + attribute \src "ls180.v:3742.193-3742.230" + cell $not $not$ls180.v:3742$208 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_payload_we + connect \Y $not$ls180.v:3742$208_Y + end + attribute \src "ls180.v:3758.43-3758.73" + cell $not $not$ls180.v:3758$236 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \main_sdram_interface_wdata_we + connect \Y $not$ls180.v:3758$236_Y + end + attribute \src "ls180.v:3761.205-3761.245" + cell $not $not$ls180.v:3761$239 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_payload_cas + connect \Y $not$ls180.v:3761$239_Y + end + attribute \src "ls180.v:3761.251-3761.290" + cell $not $not$ls180.v:3761$241 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_payload_we + connect \Y $not$ls180.v:3761$241_Y + end + attribute \src "ls180.v:3761.159-3761.292" + cell $not $not$ls180.v:3761$243 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3761$242_Y + connect \Y $not$ls180.v:3761$243_Y + end + attribute \src "ls180.v:3762.205-3762.245" + cell $not $not$ls180.v:3762$252 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_payload_cas + connect \Y $not$ls180.v:3762$252_Y + end + attribute \src "ls180.v:3762.251-3762.290" + cell $not $not$ls180.v:3762$254 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_payload_we + connect \Y $not$ls180.v:3762$254_Y + end + attribute \src "ls180.v:3762.159-3762.292" + cell $not $not$ls180.v:3762$256 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3762$255_Y + connect \Y $not$ls180.v:3762$256_Y + end + attribute \src "ls180.v:3763.205-3763.245" + cell $not $not$ls180.v:3763$265 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_payload_cas + connect \Y $not$ls180.v:3763$265_Y + end + attribute \src "ls180.v:3763.251-3763.290" + cell $not $not$ls180.v:3763$267 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_payload_we + connect \Y $not$ls180.v:3763$267_Y + end + attribute \src "ls180.v:3763.159-3763.292" + cell $not $not$ls180.v:3763$269 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3763$268_Y + connect \Y $not$ls180.v:3763$269_Y + end + attribute \src "ls180.v:3764.205-3764.245" + cell $not $not$ls180.v:3764$278 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_payload_cas + connect \Y $not$ls180.v:3764$278_Y + end + attribute \src "ls180.v:3764.251-3764.290" + cell $not $not$ls180.v:3764$280 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_payload_we + connect \Y $not$ls180.v:3764$280_Y + end + attribute \src "ls180.v:3764.159-3764.292" + cell $not $not$ls180.v:3764$282 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3764$281_Y + connect \Y $not$ls180.v:3764$282_Y + end + attribute \src "ls180.v:3791.71-3791.103" + cell $not $not$ls180.v:3791$293 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_cmd_cmd_valid + connect \Y $not$ls180.v:3791$293_Y + end + attribute \src "ls180.v:3794.205-3794.245" + cell $not $not$ls180.v:3794$297 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_payload_cas + connect \Y $not$ls180.v:3794$297_Y + end + attribute \src "ls180.v:3794.251-3794.290" + cell $not $not$ls180.v:3794$299 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_payload_we + connect \Y $not$ls180.v:3794$299_Y + end + attribute \src "ls180.v:3794.159-3794.292" + cell $not $not$ls180.v:3794$301 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3794$300_Y + connect \Y $not$ls180.v:3794$301_Y + end + attribute \src "ls180.v:3795.205-3795.245" + cell $not $not$ls180.v:3795$310 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_payload_cas + connect \Y $not$ls180.v:3795$310_Y + end + attribute \src "ls180.v:3795.251-3795.290" + cell $not $not$ls180.v:3795$312 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_payload_we + connect \Y $not$ls180.v:3795$312_Y + end + attribute \src "ls180.v:3795.159-3795.292" + cell $not $not$ls180.v:3795$314 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3795$313_Y + connect \Y $not$ls180.v:3795$314_Y + end + attribute \src "ls180.v:3796.205-3796.245" + cell $not $not$ls180.v:3796$323 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_payload_cas + connect \Y $not$ls180.v:3796$323_Y + end + attribute \src "ls180.v:3796.251-3796.290" + cell $not $not$ls180.v:3796$325 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_payload_we + connect \Y $not$ls180.v:3796$325_Y + end + attribute \src "ls180.v:3796.159-3796.292" + cell $not $not$ls180.v:3796$327 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3796$326_Y + connect \Y $not$ls180.v:3796$327_Y + end + attribute \src "ls180.v:3797.205-3797.245" + cell $not $not$ls180.v:3797$336 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_payload_cas + connect \Y $not$ls180.v:3797$336_Y + end + attribute \src "ls180.v:3797.251-3797.290" + cell $not $not$ls180.v:3797$338 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_payload_we + connect \Y $not$ls180.v:3797$338_Y + end + attribute \src "ls180.v:3797.159-3797.292" + cell $not $not$ls180.v:3797$340 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3797$339_Y + connect \Y $not$ls180.v:3797$340_Y + end + attribute \src "ls180.v:3860.71-3860.103" + cell $not $not$ls180.v:3860$379 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \Y $not$ls180.v:3860$379_Y + end + attribute \src "ls180.v:3881.112-3881.150" + cell $not $not$ls180.v:3881$382 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_payload_cas + connect \Y $not$ls180.v:3881$382_Y + end + attribute \src "ls180.v:3881.156-3881.193" + cell $not $not$ls180.v:3881$384 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_payload_we + connect \Y $not$ls180.v:3881$384_Y + end + attribute \src "ls180.v:3881.68-3881.195" + cell $not $not$ls180.v:3881$386 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3881$385_Y + connect \Y $not$ls180.v:3881$386_Y + end + attribute \src "ls180.v:3889.11-3889.38" + cell $not $not$ls180.v:3889$389 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_write_available + connect \Y $not$ls180.v:3889$389_Y + end + attribute \src "ls180.v:3919.112-3919.150" + cell $not $not$ls180.v:3919$391 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_payload_cas + connect \Y $not$ls180.v:3919$391_Y + end + attribute \src "ls180.v:3919.156-3919.193" + cell $not $not$ls180.v:3919$393 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_payload_we + connect \Y $not$ls180.v:3919$393_Y + end + attribute \src "ls180.v:3919.68-3919.195" + cell $not $not$ls180.v:3919$395 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3919$394_Y + connect \Y $not$ls180.v:3919$395_Y + end + attribute \src "ls180.v:3927.11-3927.37" + cell $not $not$ls180.v:3927$398 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_read_available + connect \Y $not$ls180.v:3927$398_Y + end + attribute \src "ls180.v:3937.87-3937.331" + cell $not $not$ls180.v:3937$410 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:3937$409_Y + connect \Y $not$ls180.v:3937$410_Y + end + attribute \src "ls180.v:3938.35-3938.68" + cell $not $not$ls180.v:3938$413 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank0_valid + connect \Y $not$ls180.v:3938$413_Y + end + attribute \src "ls180.v:3938.73-3938.105" + cell $not $not$ls180.v:3938$414 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank0_lock + connect \Y $not$ls180.v:3938$414_Y + end + attribute \src "ls180.v:3942.87-3942.331" + cell $not $not$ls180.v:3942$426 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:3942$425_Y + connect \Y $not$ls180.v:3942$426_Y + end + attribute \src "ls180.v:3943.35-3943.68" + cell $not $not$ls180.v:3943$429 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank1_valid + connect \Y $not$ls180.v:3943$429_Y + end + attribute \src "ls180.v:3943.73-3943.105" + cell $not $not$ls180.v:3943$430 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank1_lock + connect \Y $not$ls180.v:3943$430_Y + end + attribute \src "ls180.v:3947.87-3947.331" + cell $not $not$ls180.v:3947$442 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:3947$441_Y + connect \Y $not$ls180.v:3947$442_Y + end + attribute \src "ls180.v:3948.35-3948.68" + cell $not $not$ls180.v:3948$445 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank2_valid + connect \Y $not$ls180.v:3948$445_Y + end + attribute \src "ls180.v:3948.73-3948.105" + cell $not $not$ls180.v:3948$446 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank2_lock + connect \Y $not$ls180.v:3948$446_Y + end + attribute \src "ls180.v:3952.87-3952.331" + cell $not $not$ls180.v:3952$458 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:3952$457_Y + connect \Y $not$ls180.v:3952$458_Y + end + attribute \src "ls180.v:3953.35-3953.68" + cell $not $not$ls180.v:3953$461 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank3_valid + connect \Y $not$ls180.v:3953$461_Y + end + attribute \src "ls180.v:3953.73-3953.105" + cell $not $not$ls180.v:3953$462 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank3_lock + connect \Y $not$ls180.v:3953$462_Y + end + attribute \src "ls180.v:3957.128-3957.372" + cell $not $not$ls180.v:3957$475 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:3957$474_Y + connect \Y $not$ls180.v:3957$475_Y + end + attribute \src "ls180.v:3957.502-3957.746" + cell $not $not$ls180.v:3957$491 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:3957$490_Y + connect \Y $not$ls180.v:3957$491_Y + end + attribute \src "ls180.v:3957.876-3957.1120" + cell $not $not$ls180.v:3957$507 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:3957$506_Y + connect \Y $not$ls180.v:3957$507_Y + end + attribute \src "ls180.v:3957.1250-3957.1494" + cell $not $not$ls180.v:3957$523 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:3957$522_Y + connect \Y $not$ls180.v:3957$523_Y + end + attribute \src "ls180.v:3979.32-3979.50" + cell $not $not$ls180.v:3979$529 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_wb_sdram_cyc + connect \Y $not$ls180.v:3979$529_Y + end + attribute \src "ls180.v:4018.30-4018.50" + cell $not $not$ls180.v:4018$534 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_converter_skip + connect \Y $not$ls180.v:4018$534_Y + end + attribute \src "ls180.v:4019.30-4019.50" + cell $not $not$ls180.v:4019$535 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_converter_skip + connect \Y $not$ls180.v:4019$535_Y + end + attribute \src "ls180.v:4044.27-4044.48" + cell $not $not$ls180.v:4044$541 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_litedram_wb_cyc + connect \Y $not$ls180.v:4044$541_Y + end + attribute \src "ls180.v:4045.30-4045.50" + cell $not $not$ls180.v:4045$542 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_litedram_wb_we + connect \Y $not$ls180.v:4045$542_Y + end + attribute \src "ls180.v:4046.80-4046.98" + cell $not $not$ls180.v:4046$544 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_cmd_consumed + connect \Y $not$ls180.v:4046$544_Y + end + attribute \src "ls180.v:4047.107-4047.127" + cell $not $not$ls180.v:4047$548 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_wdata_consumed + connect \Y $not$ls180.v:4047$548_Y + end + attribute \src "ls180.v:4048.78-4048.103" + cell $not $not$ls180.v:4048$551 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_payload_we + connect \Y $not$ls180.v:4048$551_Y + end + attribute \src "ls180.v:4049.91-4049.111" + cell $not $not$ls180.v:4049$554 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_litedram_wb_we + connect \Y $not$ls180.v:4049$554_Y + end + attribute \src "ls180.v:4065.35-4065.64" + cell $not $not$ls180.v:4065$563 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_tx_fifo_sink_ready + connect \Y $not$ls180.v:4065$563_Y + end + attribute \src "ls180.v:4066.36-4066.67" + cell $not $not$ls180.v:4066$564 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_tx_fifo_source_valid + connect \Y $not$ls180.v:4066$564_Y + end + attribute \src "ls180.v:4072.32-4072.61" + cell $not $not$ls180.v:4072$565 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_tx_fifo_sink_ready + connect \Y $not$ls180.v:4072$565_Y + end + attribute \src "ls180.v:4078.36-4078.67" + cell $not $not$ls180.v:4078$566 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_rx_fifo_source_valid + connect \Y $not$ls180.v:4078$566_Y + end + attribute \src "ls180.v:4079.35-4079.64" + cell $not $not$ls180.v:4079$567 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_rx_fifo_sink_ready + connect \Y $not$ls180.v:4079$567_Y + end + attribute \src "ls180.v:4082.32-4082.63" + cell $not $not$ls180.v:4082$570 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_rx_fifo_source_valid + connect \Y $not$ls180.v:4082$570_Y + end + attribute \src "ls180.v:4120.81-4120.108" + cell $not $not$ls180.v:4120$580 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_tx_fifo_readable + connect \Y $not$ls180.v:4120$580_Y + end + attribute \src "ls180.v:4150.81-4150.108" + cell $not $not$ls180.v:4150$591 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_rx_fifo_readable + connect \Y $not$ls180.v:4150$591_Y + end + attribute \src "ls180.v:4287.60-4287.85" + cell $not $not$ls180.v:4287$632 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_clocker_clk_d + connect \Y $not$ls180.v:4287$632_Y + end + attribute \src "ls180.v:4428.54-4428.96" + cell $not $not$ls180.v:4428$646 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_cmdr_converter_strobe_all + connect \Y $not$ls180.v:4428$646_Y + end + attribute \src "ls180.v:4431.48-4431.86" + cell $not $not$ls180.v:4431$649 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_cmdr_buf_source_valid + connect \Y $not$ls180.v:4431$649_Y + end + attribute \src "ls180.v:4555.55-4555.98" + cell $not $not$ls180.v:4555$667 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_crcr_converter_strobe_all + connect \Y $not$ls180.v:4555$667_Y + end + attribute \src "ls180.v:4558.49-4558.88" + cell $not $not$ls180.v:4558$670 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_crcr_buf_source_valid + connect \Y $not$ls180.v:4558$670_Y + end + attribute \src "ls180.v:4608.30-4608.58" + cell $not $not$ls180.v:4608$676 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_sink_valid + connect \Y $not$ls180.v:4608$676_Y + end + attribute \src "ls180.v:4689.56-4689.100" + cell $not $not$ls180.v:4689$682 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_datar_converter_strobe_all + connect \Y $not$ls180.v:4689$682_Y + end + attribute \src "ls180.v:4692.50-4692.90" + cell $not $not$ls180.v:4692$685 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_datar_buf_source_valid + connect \Y $not$ls180.v:4692$685_Y + end + attribute \src "ls180.v:4808.42-4808.74" + cell $not $not$ls180.v:4808$701 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_valid + connect \Y $not$ls180.v:4808$701_Y + end + attribute \src "ls180.v:5332.50-5332.88" + cell $not $not$ls180.v:5332$986 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_converter_strobe_all + connect \Y $not$ls180.v:5332$986_Y + end + attribute \src "ls180.v:5344.52-5344.102" + cell $not $not$ls180.v:5344$989 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_wishbonedmawriter_enable_storage + connect \Y $not$ls180.v:5344$989_Y + end + attribute \src "ls180.v:5403.38-5403.74" + cell $not $not$ls180.v:5403$996 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_dma_enable_storage + connect \Y $not$ls180.v:5403$996_Y + end + attribute \src "ls180.v:5704.69-5704.88" + cell $not $not$ls180.v:5704$1065 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_ack + connect \Y $not$ls180.v:5704$1065_Y + end + attribute \src "ls180.v:5721.63-5721.94" + cell $not $not$ls180.v:5721$1086 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_we + connect \Y $not$ls180.v:5721$1086_Y + end + attribute \src "ls180.v:5724.65-5724.96" + cell $not $not$ls180.v:5724$1093 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_we + connect \Y $not$ls180.v:5724$1093_Y + end + attribute \src "ls180.v:5727.65-5727.96" + cell $not $not$ls180.v:5727$1100 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_we + connect \Y $not$ls180.v:5727$1100_Y + end + attribute \src "ls180.v:5730.65-5730.96" + cell $not $not$ls180.v:5730$1107 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_we + connect \Y $not$ls180.v:5730$1107_Y + end + attribute \src "ls180.v:5733.65-5733.96" + cell $not $not$ls180.v:5733$1114 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_we + connect \Y $not$ls180.v:5733$1114_Y + end + attribute \src "ls180.v:5736.68-5736.99" + cell $not $not$ls180.v:5736$1121 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_we + connect \Y $not$ls180.v:5736$1121_Y + end + attribute \src "ls180.v:5739.68-5739.99" + cell $not $not$ls180.v:5739$1128 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_we + connect \Y $not$ls180.v:5739$1128_Y + end + attribute \src "ls180.v:5742.68-5742.99" + cell $not $not$ls180.v:5742$1135 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_we + connect \Y $not$ls180.v:5742$1135_Y + end + attribute \src "ls180.v:5745.68-5745.99" + cell $not $not$ls180.v:5745$1142 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_we + connect \Y $not$ls180.v:5745$1142_Y + end + attribute \src "ls180.v:5759.60-5759.91" + cell $not $not$ls180.v:5759$1150 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_we + connect \Y $not$ls180.v:5759$1150_Y + end + attribute \src "ls180.v:5762.60-5762.91" + cell $not $not$ls180.v:5762$1157 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_we + connect \Y $not$ls180.v:5762$1157_Y + end + attribute \src "ls180.v:5765.60-5765.91" + cell $not $not$ls180.v:5765$1164 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_we + connect \Y $not$ls180.v:5765$1164_Y + end + attribute \src "ls180.v:5768.60-5768.91" + cell $not $not$ls180.v:5768$1171 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_we + connect \Y $not$ls180.v:5768$1171_Y + end + attribute \src "ls180.v:5771.61-5771.92" + cell $not $not$ls180.v:5771$1178 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_we + connect \Y $not$ls180.v:5771$1178_Y + end + attribute \src "ls180.v:5774.61-5774.92" + cell $not $not$ls180.v:5774$1185 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_we + connect \Y $not$ls180.v:5774$1185_Y + end + attribute \src "ls180.v:5785.64-5785.95" + cell $not $not$ls180.v:5785$1193 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface2_bank_bus_we + connect \Y $not$ls180.v:5785$1193_Y + end + attribute \src "ls180.v:5788.63-5788.94" + cell $not $not$ls180.v:5788$1200 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface2_bank_bus_we + connect \Y $not$ls180.v:5788$1200_Y + end + attribute \src "ls180.v:5791.63-5791.94" + cell $not $not$ls180.v:5791$1207 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface2_bank_bus_we + connect \Y $not$ls180.v:5791$1207_Y + end + attribute \src "ls180.v:5794.63-5794.94" + cell $not $not$ls180.v:5794$1214 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface2_bank_bus_we + connect \Y $not$ls180.v:5794$1214_Y + end + attribute \src "ls180.v:5797.63-5797.94" + cell $not $not$ls180.v:5797$1221 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface2_bank_bus_we + connect \Y $not$ls180.v:5797$1221_Y + end + attribute \src "ls180.v:5800.64-5800.95" + cell $not $not$ls180.v:5800$1228 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface2_bank_bus_we + connect \Y $not$ls180.v:5800$1228_Y + end + attribute \src "ls180.v:5803.64-5803.95" + cell $not $not$ls180.v:5803$1235 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface2_bank_bus_we + connect \Y $not$ls180.v:5803$1235_Y + end + attribute \src "ls180.v:5806.64-5806.95" + cell $not $not$ls180.v:5806$1242 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface2_bank_bus_we + connect \Y $not$ls180.v:5806$1242_Y + end + attribute \src "ls180.v:5809.64-5809.95" + cell $not $not$ls180.v:5809$1249 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface2_bank_bus_we + connect \Y $not$ls180.v:5809$1249_Y + end + attribute \src "ls180.v:5822.64-5822.95" + cell $not $not$ls180.v:5822$1257 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_we + connect \Y $not$ls180.v:5822$1257_Y + end + attribute \src "ls180.v:5825.63-5825.94" + cell $not $not$ls180.v:5825$1264 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_we + connect \Y $not$ls180.v:5825$1264_Y + end + attribute \src "ls180.v:5828.63-5828.94" + cell $not $not$ls180.v:5828$1271 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_we + connect \Y $not$ls180.v:5828$1271_Y + end + attribute \src "ls180.v:5831.63-5831.94" + cell $not $not$ls180.v:5831$1278 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_we + connect \Y $not$ls180.v:5831$1278_Y + end + attribute \src "ls180.v:5834.63-5834.94" + cell $not $not$ls180.v:5834$1285 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_we + connect \Y $not$ls180.v:5834$1285_Y + end + attribute \src "ls180.v:5837.64-5837.95" + cell $not $not$ls180.v:5837$1292 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_we + connect \Y $not$ls180.v:5837$1292_Y + end + attribute \src "ls180.v:5840.64-5840.95" + cell $not $not$ls180.v:5840$1299 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_we + connect \Y $not$ls180.v:5840$1299_Y + end + attribute \src "ls180.v:5843.64-5843.95" + cell $not $not$ls180.v:5843$1306 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_we + connect \Y $not$ls180.v:5843$1306_Y + end + attribute \src "ls180.v:5846.64-5846.95" + cell $not $not$ls180.v:5846$1313 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_we + connect \Y $not$ls180.v:5846$1313_Y + end + attribute \src "ls180.v:5859.66-5859.97" + cell $not $not$ls180.v:5859$1321 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_we + connect \Y $not$ls180.v:5859$1321_Y + end + attribute \src "ls180.v:5862.66-5862.97" + cell $not $not$ls180.v:5862$1328 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_we + connect \Y $not$ls180.v:5862$1328_Y + end + attribute \src "ls180.v:5865.66-5865.97" + cell $not $not$ls180.v:5865$1335 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_we + connect \Y $not$ls180.v:5865$1335_Y + end + attribute \src "ls180.v:5868.66-5868.97" + cell $not $not$ls180.v:5868$1342 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_we + connect \Y $not$ls180.v:5868$1342_Y + end + attribute \src "ls180.v:5871.66-5871.97" + cell $not $not$ls180.v:5871$1349 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_we + connect \Y $not$ls180.v:5871$1349_Y + end + attribute \src "ls180.v:5874.66-5874.97" + cell $not $not$ls180.v:5874$1356 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_we + connect \Y $not$ls180.v:5874$1356_Y + end + attribute \src "ls180.v:5877.66-5877.97" + cell $not $not$ls180.v:5877$1363 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_we + connect \Y $not$ls180.v:5877$1363_Y + end + attribute \src "ls180.v:5880.66-5880.97" + cell $not $not$ls180.v:5880$1370 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_we + connect \Y $not$ls180.v:5880$1370_Y + end + attribute \src "ls180.v:5883.68-5883.99" + cell $not $not$ls180.v:5883$1377 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_we + connect \Y $not$ls180.v:5883$1377_Y + end + attribute \src "ls180.v:5886.68-5886.99" + cell $not $not$ls180.v:5886$1384 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_we + connect \Y $not$ls180.v:5886$1384_Y + end + attribute \src "ls180.v:5889.68-5889.99" + cell $not $not$ls180.v:5889$1391 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_we + connect \Y $not$ls180.v:5889$1391_Y + end + attribute \src "ls180.v:5892.68-5892.99" + cell $not $not$ls180.v:5892$1398 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_we + connect \Y $not$ls180.v:5892$1398_Y + end + attribute \src "ls180.v:5895.68-5895.99" + cell $not $not$ls180.v:5895$1405 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_we + connect \Y $not$ls180.v:5895$1405_Y + end + attribute \src "ls180.v:5898.65-5898.96" + cell $not $not$ls180.v:5898$1412 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_we + connect \Y $not$ls180.v:5898$1412_Y + end + attribute \src "ls180.v:5901.66-5901.97" + cell $not $not$ls180.v:5901$1419 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_we + connect \Y $not$ls180.v:5901$1419_Y + end + attribute \src "ls180.v:5921.70-5921.101" + cell $not $not$ls180.v:5921$1427 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:5921$1427_Y + end + attribute \src "ls180.v:5924.70-5924.101" + cell $not $not$ls180.v:5924$1434 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:5924$1434_Y + end + attribute \src "ls180.v:5927.70-5927.101" + cell $not $not$ls180.v:5927$1441 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:5927$1441_Y + end + attribute \src "ls180.v:5930.70-5930.101" + cell $not $not$ls180.v:5930$1448 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:5930$1448_Y + end + attribute \src "ls180.v:5933.69-5933.100" + cell $not $not$ls180.v:5933$1455 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:5933$1455_Y + end + attribute \src "ls180.v:5936.69-5936.100" + cell $not $not$ls180.v:5936$1462 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:5936$1462_Y + end + attribute \src "ls180.v:5939.69-5939.100" + cell $not $not$ls180.v:5939$1469 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:5939$1469_Y + end + attribute \src "ls180.v:5942.69-5942.100" + cell $not $not$ls180.v:5942$1476 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:5942$1476_Y + end + attribute \src "ls180.v:5945.60-5945.91" + cell $not $not$ls180.v:5945$1483 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:5945$1483_Y + end + attribute \src "ls180.v:5948.71-5948.102" + cell $not $not$ls180.v:5948$1490 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:5948$1490_Y + end + attribute \src "ls180.v:5951.71-5951.102" + cell $not $not$ls180.v:5951$1497 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:5951$1497_Y + end + attribute \src "ls180.v:5954.71-5954.102" + cell $not $not$ls180.v:5954$1504 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:5954$1504_Y + end + attribute \src "ls180.v:5957.71-5957.102" + cell $not $not$ls180.v:5957$1511 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:5957$1511_Y + end + attribute \src "ls180.v:5960.71-5960.102" + cell $not $not$ls180.v:5960$1518 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:5960$1518_Y + end + attribute \src "ls180.v:5963.71-5963.102" + cell $not $not$ls180.v:5963$1525 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:5963$1525_Y + end + attribute \src "ls180.v:5966.70-5966.101" + cell $not $not$ls180.v:5966$1532 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:5966$1532_Y + end + attribute \src "ls180.v:5969.70-5969.101" + cell $not $not$ls180.v:5969$1539 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:5969$1539_Y + end + attribute \src "ls180.v:5972.70-5972.101" + cell $not $not$ls180.v:5972$1546 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:5972$1546_Y + end + attribute \src "ls180.v:5975.70-5975.101" + cell $not $not$ls180.v:5975$1553 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:5975$1553_Y + end + attribute \src "ls180.v:5978.70-5978.101" + cell $not $not$ls180.v:5978$1560 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:5978$1560_Y + end + attribute \src "ls180.v:5981.70-5981.101" + cell $not $not$ls180.v:5981$1567 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:5981$1567_Y + end + attribute \src "ls180.v:5984.70-5984.101" + cell $not $not$ls180.v:5984$1574 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:5984$1574_Y + end + attribute \src "ls180.v:5987.70-5987.101" + cell $not $not$ls180.v:5987$1581 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:5987$1581_Y + end + attribute \src "ls180.v:5990.70-5990.101" + cell $not $not$ls180.v:5990$1588 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:5990$1588_Y + end + attribute \src "ls180.v:5993.70-5993.101" + cell $not $not$ls180.v:5993$1595 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:5993$1595_Y + end + attribute \src "ls180.v:5996.66-5996.97" + cell $not $not$ls180.v:5996$1602 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:5996$1602_Y + end + attribute \src "ls180.v:5999.67-5999.98" + cell $not $not$ls180.v:5999$1609 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:5999$1609_Y + end + attribute \src "ls180.v:6002.70-6002.101" + cell $not $not$ls180.v:6002$1616 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:6002$1616_Y + end + attribute \src "ls180.v:6005.70-6005.101" + cell $not $not$ls180.v:6005$1623 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:6005$1623_Y + end + attribute \src "ls180.v:6008.69-6008.100" + cell $not $not$ls180.v:6008$1630 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:6008$1630_Y + end + attribute \src "ls180.v:6011.69-6011.100" + cell $not $not$ls180.v:6011$1637 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:6011$1637_Y + end + attribute \src "ls180.v:6014.69-6014.100" + cell $not $not$ls180.v:6014$1644 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:6014$1644_Y + end + attribute \src "ls180.v:6017.69-6017.100" + cell $not $not$ls180.v:6017$1651 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:6017$1651_Y + end + attribute \src "ls180.v:6056.66-6056.97" + cell $not $not$ls180.v:6056$1659 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6056$1659_Y + end + attribute \src "ls180.v:6059.66-6059.97" + cell $not $not$ls180.v:6059$1666 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6059$1666_Y + end + attribute \src "ls180.v:6062.66-6062.97" + cell $not $not$ls180.v:6062$1673 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6062$1673_Y + end + attribute \src "ls180.v:6065.66-6065.97" + cell $not $not$ls180.v:6065$1680 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6065$1680_Y + end + attribute \src "ls180.v:6068.66-6068.97" + cell $not $not$ls180.v:6068$1687 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6068$1687_Y + end + attribute \src "ls180.v:6071.66-6071.97" + cell $not $not$ls180.v:6071$1694 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6071$1694_Y + end + attribute \src "ls180.v:6074.66-6074.97" + cell $not $not$ls180.v:6074$1701 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6074$1701_Y + end + attribute \src "ls180.v:6077.66-6077.97" + cell $not $not$ls180.v:6077$1708 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6077$1708_Y + end + attribute \src "ls180.v:6080.68-6080.99" + cell $not $not$ls180.v:6080$1715 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6080$1715_Y + end + attribute \src "ls180.v:6083.68-6083.99" + cell $not $not$ls180.v:6083$1722 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6083$1722_Y + end + attribute \src "ls180.v:6086.68-6086.99" + cell $not $not$ls180.v:6086$1729 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6086$1729_Y + end + attribute \src "ls180.v:6089.68-6089.99" + cell $not $not$ls180.v:6089$1736 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6089$1736_Y + end + attribute \src "ls180.v:6092.68-6092.99" + cell $not $not$ls180.v:6092$1743 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6092$1743_Y + end + attribute \src "ls180.v:6095.65-6095.96" + cell $not $not$ls180.v:6095$1750 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6095$1750_Y + end + attribute \src "ls180.v:6098.66-6098.97" + cell $not $not$ls180.v:6098$1757 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6098$1757_Y + end + attribute \src "ls180.v:6101.68-6101.99" + cell $not $not$ls180.v:6101$1764 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6101$1764_Y + end + attribute \src "ls180.v:6104.68-6104.99" + cell $not $not$ls180.v:6104$1771 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6104$1771_Y + end + attribute \src "ls180.v:6107.68-6107.99" + cell $not $not$ls180.v:6107$1778 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6107$1778_Y + end + attribute \src "ls180.v:6110.68-6110.99" + cell $not $not$ls180.v:6110$1785 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6110$1785_Y + end + attribute \src "ls180.v:6135.68-6135.99" + cell $not $not$ls180.v:6135$1793 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_we + connect \Y $not$ls180.v:6135$1793_Y + end + attribute \src "ls180.v:6138.73-6138.104" + cell $not $not$ls180.v:6138$1800 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_we + connect \Y $not$ls180.v:6138$1800_Y + end + attribute \src "ls180.v:6141.73-6141.104" + cell $not $not$ls180.v:6141$1807 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_we + connect \Y $not$ls180.v:6141$1807_Y + end + attribute \src "ls180.v:6144.66-6144.97" + cell $not $not$ls180.v:6144$1814 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_we + connect \Y $not$ls180.v:6144$1814_Y + end + attribute \src "ls180.v:6152.70-6152.101" + cell $not $not$ls180.v:6152$1822 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_we + connect \Y $not$ls180.v:6152$1822_Y + end + attribute \src "ls180.v:6155.74-6155.105" + cell $not $not$ls180.v:6155$1829 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_we + connect \Y $not$ls180.v:6155$1829_Y + end + attribute \src "ls180.v:6158.64-6158.95" + cell $not $not$ls180.v:6158$1836 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_we + connect \Y $not$ls180.v:6158$1836_Y + end + attribute \src "ls180.v:6161.74-6161.105" + cell $not $not$ls180.v:6161$1843 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_we + connect \Y $not$ls180.v:6161$1843_Y + end + attribute \src "ls180.v:6164.74-6164.105" + cell $not $not$ls180.v:6164$1850 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_we + connect \Y $not$ls180.v:6164$1850_Y + end + attribute \src "ls180.v:6167.75-6167.106" + cell $not $not$ls180.v:6167$1857 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_we + connect \Y $not$ls180.v:6167$1857_Y + end + attribute \src "ls180.v:6170.73-6170.104" + cell $not $not$ls180.v:6170$1864 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_we + connect \Y $not$ls180.v:6170$1864_Y + end + attribute \src "ls180.v:6173.73-6173.104" + cell $not $not$ls180.v:6173$1871 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_we + connect \Y $not$ls180.v:6173$1871_Y + end + attribute \src "ls180.v:6176.73-6176.104" + cell $not $not$ls180.v:6176$1878 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_we + connect \Y $not$ls180.v:6176$1878_Y + end + attribute \src "ls180.v:6179.73-6179.104" + cell $not $not$ls180.v:6179$1885 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_we + connect \Y $not$ls180.v:6179$1885_Y + end + attribute \src "ls180.v:6197.65-6197.96" + cell $not $not$ls180.v:6197$1893 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_we + connect \Y $not$ls180.v:6197$1893_Y + end + attribute \src "ls180.v:6200.65-6200.96" + cell $not $not$ls180.v:6200$1900 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_we + connect \Y $not$ls180.v:6200$1900_Y + end + attribute \src "ls180.v:6203.63-6203.94" + cell $not $not$ls180.v:6203$1907 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_we + connect \Y $not$ls180.v:6203$1907_Y + end + attribute \src "ls180.v:6206.62-6206.93" + cell $not $not$ls180.v:6206$1914 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_we + connect \Y $not$ls180.v:6206$1914_Y + end + attribute \src "ls180.v:6209.61-6209.92" + cell $not $not$ls180.v:6209$1921 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_we + connect \Y $not$ls180.v:6209$1921_Y + end + attribute \src "ls180.v:6212.60-6212.91" + cell $not $not$ls180.v:6212$1928 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_we + connect \Y $not$ls180.v:6212$1928_Y + end + attribute \src "ls180.v:6215.66-6215.97" + cell $not $not$ls180.v:6215$1935 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_we + connect \Y $not$ls180.v:6215$1935_Y + end + attribute \src "ls180.v:6237.67-6237.99" + cell $not $not$ls180.v:6237$1944 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_we + connect \Y $not$ls180.v:6237$1944_Y + end + attribute \src "ls180.v:6240.67-6240.99" + cell $not $not$ls180.v:6240$1951 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_we + connect \Y $not$ls180.v:6240$1951_Y + end + attribute \src "ls180.v:6243.65-6243.97" + cell $not $not$ls180.v:6243$1958 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_we + connect \Y $not$ls180.v:6243$1958_Y + end + attribute \src "ls180.v:6246.64-6246.96" + cell $not $not$ls180.v:6246$1965 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_we + connect \Y $not$ls180.v:6246$1965_Y + end + attribute \src "ls180.v:6249.63-6249.95" + cell $not $not$ls180.v:6249$1972 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_we + connect \Y $not$ls180.v:6249$1972_Y + end + attribute \src "ls180.v:6252.62-6252.94" + cell $not $not$ls180.v:6252$1979 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_we + connect \Y $not$ls180.v:6252$1979_Y + end + attribute \src "ls180.v:6255.68-6255.100" + cell $not $not$ls180.v:6255$1986 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_we + connect \Y $not$ls180.v:6255$1986_Y + end + attribute \src "ls180.v:6258.71-6258.103" + cell $not $not$ls180.v:6258$1993 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_we + connect \Y $not$ls180.v:6258$1993_Y + end + attribute \src "ls180.v:6261.71-6261.103" + cell $not $not$ls180.v:6261$2000 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_we + connect \Y $not$ls180.v:6261$2000_Y + end + attribute \src "ls180.v:6285.64-6285.96" + cell $not $not$ls180.v:6285$2009 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_we + connect \Y $not$ls180.v:6285$2009_Y + end + attribute \src "ls180.v:6288.64-6288.96" + cell $not $not$ls180.v:6288$2016 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_we + connect \Y $not$ls180.v:6288$2016_Y + end + attribute \src "ls180.v:6291.64-6291.96" + cell $not $not$ls180.v:6291$2023 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_we + connect \Y $not$ls180.v:6291$2023_Y + end + attribute \src "ls180.v:6294.64-6294.96" + cell $not $not$ls180.v:6294$2030 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_we + connect \Y $not$ls180.v:6294$2030_Y + end + attribute \src "ls180.v:6297.66-6297.98" + cell $not $not$ls180.v:6297$2037 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_we + connect \Y $not$ls180.v:6297$2037_Y + end + attribute \src "ls180.v:6300.66-6300.98" + cell $not $not$ls180.v:6300$2044 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_we + connect \Y $not$ls180.v:6300$2044_Y + end + attribute \src "ls180.v:6303.66-6303.98" + cell $not $not$ls180.v:6303$2051 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_we + connect \Y $not$ls180.v:6303$2051_Y + end + attribute \src "ls180.v:6306.66-6306.98" + cell $not $not$ls180.v:6306$2058 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_we + connect \Y $not$ls180.v:6306$2058_Y + end + attribute \src "ls180.v:6309.62-6309.94" + cell $not $not$ls180.v:6309$2065 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_we + connect \Y $not$ls180.v:6309$2065_Y + end + attribute \src "ls180.v:6312.72-6312.104" + cell $not $not$ls180.v:6312$2072 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_we + connect \Y $not$ls180.v:6312$2072_Y + end + attribute \src "ls180.v:6315.65-6315.97" + cell $not $not$ls180.v:6315$2079 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_we + connect \Y $not$ls180.v:6315$2079_Y + end + attribute \src "ls180.v:6318.65-6318.97" + cell $not $not$ls180.v:6318$2086 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_we + connect \Y $not$ls180.v:6318$2086_Y + end + attribute \src "ls180.v:6321.65-6321.97" + cell $not $not$ls180.v:6321$2093 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_we + connect \Y $not$ls180.v:6321$2093_Y + end + attribute \src "ls180.v:6324.65-6324.97" + cell $not $not$ls180.v:6324$2100 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_we + connect \Y $not$ls180.v:6324$2100_Y + end + attribute \src "ls180.v:6327.77-6327.109" + cell $not $not$ls180.v:6327$2107 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_we + connect \Y $not$ls180.v:6327$2107_Y + end + attribute \src "ls180.v:6330.78-6330.110" + cell $not $not$ls180.v:6330$2114 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_we + connect \Y $not$ls180.v:6330$2114_Y + end + attribute \src "ls180.v:6333.69-6333.101" + cell $not $not$ls180.v:6333$2121 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_we + connect \Y $not$ls180.v:6333$2121_Y + end + attribute \src "ls180.v:6353.55-6353.87" + cell $not $not$ls180.v:6353$2129 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_we + connect \Y $not$ls180.v:6353$2129_Y + end + attribute \src "ls180.v:6356.65-6356.97" + cell $not $not$ls180.v:6356$2136 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_we + connect \Y $not$ls180.v:6356$2136_Y + end + attribute \src "ls180.v:6359.66-6359.98" + cell $not $not$ls180.v:6359$2143 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_we + connect \Y $not$ls180.v:6359$2143_Y + end + attribute \src "ls180.v:6362.70-6362.102" + cell $not $not$ls180.v:6362$2150 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_we + connect \Y $not$ls180.v:6362$2150_Y + end + attribute \src "ls180.v:6365.71-6365.103" + cell $not $not$ls180.v:6365$2157 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_we + connect \Y $not$ls180.v:6365$2157_Y + end + attribute \src "ls180.v:6368.69-6368.101" + cell $not $not$ls180.v:6368$2164 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_we + connect \Y $not$ls180.v:6368$2164_Y + end + attribute \src "ls180.v:6371.66-6371.98" + cell $not $not$ls180.v:6371$2171 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_we + connect \Y $not$ls180.v:6371$2171_Y + end + attribute \src "ls180.v:6374.65-6374.97" + cell $not $not$ls180.v:6374$2178 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_we + connect \Y $not$ls180.v:6374$2178_Y + end + attribute \src "ls180.v:6387.71-6387.103" + cell $not $not$ls180.v:6387$2186 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_we + connect \Y $not$ls180.v:6387$2186_Y + end + attribute \src "ls180.v:6390.71-6390.103" + cell $not $not$ls180.v:6390$2193 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_we + connect \Y $not$ls180.v:6390$2193_Y + end + attribute \src "ls180.v:6393.71-6393.103" + cell $not $not$ls180.v:6393$2200 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_we + connect \Y $not$ls180.v:6393$2200_Y + end + attribute \src "ls180.v:6396.71-6396.103" + cell $not $not$ls180.v:6396$2207 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_we + connect \Y $not$ls180.v:6396$2207_Y + end + attribute \src "ls180.v:6774.86-6774.330" + cell $not $not$ls180.v:6774$2255 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:6774$2254_Y + connect \Y $not$ls180.v:6774$2255_Y + end + attribute \src "ls180.v:6798.86-6798.330" + cell $not $not$ls180.v:6798$2271 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:6798$2270_Y + connect \Y $not$ls180.v:6798$2271_Y + end + attribute \src "ls180.v:6822.86-6822.330" + cell $not $not$ls180.v:6822$2287 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:6822$2286_Y + connect \Y $not$ls180.v:6822$2287_Y + end + attribute \src "ls180.v:6846.86-6846.330" + cell $not $not$ls180.v:6846$2303 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:6846$2302_Y + connect \Y $not$ls180.v:6846$2303_Y + end + attribute \src "ls180.v:7344.18-7344.42" + cell $not $not$ls180.v:7344$2356 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_clocker_clk0 + connect \Y $not$ls180.v:7344$2356_Y + end + attribute \src "ls180.v:7441.72-7441.101" + cell $not $not$ls180.v:7441$2407 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_ram_bus_ack + connect \Y $not$ls180.v:7441$2407_Y + end + attribute \src "ls180.v:7460.8-7460.38" + cell $not $not$ls180.v:7460$2411 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_zero_trigger + connect \Y $not$ls180.v:7460$2411_Y + end + attribute \src "ls180.v:7468.32-7468.55" + cell $not $not$ls180.v:7468$2413 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_timer_done0 + connect \Y $not$ls180.v:7468$2413_Y + end + attribute \src "ls180.v:7538.136-7538.189" + cell $not $not$ls180.v:7538$2428 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_replace + connect \Y $not$ls180.v:7538$2428_Y + end + attribute \src "ls180.v:7544.136-7544.189" + cell $not $not$ls180.v:7544$2433 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_replace + connect \Y $not$ls180.v:7544$2433_Y + end + attribute \src "ls180.v:7545.8-7545.61" + cell $not $not$ls180.v:7545$2435 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read + connect \Y $not$ls180.v:7545$2435_Y + end + attribute \src "ls180.v:7553.8-7553.56" + cell $not $not$ls180.v:7553$2438 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_buffer_source_valid + connect \Y $not$ls180.v:7553$2438_Y + end + attribute \src "ls180.v:7568.8-7568.46" + cell $not $not$ls180.v:7568$2440 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_twtpcon_ready + connect \Y $not$ls180.v:7568$2440_Y + end + attribute \src "ls180.v:7584.136-7584.189" + cell $not $not$ls180.v:7584$2444 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_replace + connect \Y $not$ls180.v:7584$2444_Y + end + attribute \src "ls180.v:7590.136-7590.189" + cell $not $not$ls180.v:7590$2449 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_replace + connect \Y $not$ls180.v:7590$2449_Y + end + attribute \src "ls180.v:7591.8-7591.61" + cell $not $not$ls180.v:7591$2451 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read + connect \Y $not$ls180.v:7591$2451_Y + end + attribute \src "ls180.v:7599.8-7599.56" + cell $not $not$ls180.v:7599$2454 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_buffer_source_valid + connect \Y $not$ls180.v:7599$2454_Y + end + attribute \src "ls180.v:7614.8-7614.46" + cell $not $not$ls180.v:7614$2456 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_twtpcon_ready + connect \Y $not$ls180.v:7614$2456_Y + end + attribute \src "ls180.v:7630.136-7630.189" + cell $not $not$ls180.v:7630$2460 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_replace + connect \Y $not$ls180.v:7630$2460_Y + end + attribute \src "ls180.v:7636.136-7636.189" + cell $not $not$ls180.v:7636$2465 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_replace + connect \Y $not$ls180.v:7636$2465_Y + end + attribute \src "ls180.v:7637.8-7637.61" + cell $not $not$ls180.v:7637$2467 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read + connect \Y $not$ls180.v:7637$2467_Y + end + attribute \src "ls180.v:7645.8-7645.56" + cell $not $not$ls180.v:7645$2470 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_buffer_source_valid + connect \Y $not$ls180.v:7645$2470_Y + end + attribute \src "ls180.v:7660.8-7660.46" + cell $not $not$ls180.v:7660$2472 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_twtpcon_ready + connect \Y $not$ls180.v:7660$2472_Y + end + attribute \src "ls180.v:7676.136-7676.189" + cell $not $not$ls180.v:7676$2476 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_replace + connect \Y $not$ls180.v:7676$2476_Y + end + attribute \src "ls180.v:7682.136-7682.189" + cell $not $not$ls180.v:7682$2481 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_replace + connect \Y $not$ls180.v:7682$2481_Y + end + attribute \src "ls180.v:7683.8-7683.61" + cell $not $not$ls180.v:7683$2483 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read + connect \Y $not$ls180.v:7683$2483_Y + end + attribute \src "ls180.v:7691.8-7691.56" + cell $not $not$ls180.v:7691$2486 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_buffer_source_valid + connect \Y $not$ls180.v:7691$2486_Y + end + attribute \src "ls180.v:7706.8-7706.46" + cell $not $not$ls180.v:7706$2488 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_twtpcon_ready + connect \Y $not$ls180.v:7706$2488_Y + end + attribute \src "ls180.v:7714.7-7714.22" + cell $not $not$ls180.v:7714$2491 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_en0 + connect \Y $not$ls180.v:7714$2491_Y + end + attribute \src "ls180.v:7717.8-7717.29" + cell $not $not$ls180.v:7717$2492 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_max_time0 + connect \Y $not$ls180.v:7717$2492_Y + end + attribute \src "ls180.v:7721.7-7721.22" + cell $not $not$ls180.v:7721$2494 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_en1 + connect \Y $not$ls180.v:7721$2494_Y + end + attribute \src "ls180.v:7724.8-7724.29" + cell $not $not$ls180.v:7724$2495 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_max_time1 + connect \Y $not$ls180.v:7724$2495_Y + end + attribute \src "ls180.v:7843.30-7843.60" + cell $not $not$ls180.v:7843$2497 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_sync_rhs_array_muxed2 + connect \Y $not$ls180.v:7843$2497_Y + end + attribute \src "ls180.v:7844.30-7844.60" + cell $not $not$ls180.v:7844$2498 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_sync_rhs_array_muxed3 + connect \Y $not$ls180.v:7844$2498_Y + end + attribute \src "ls180.v:7845.29-7845.59" + cell $not $not$ls180.v:7845$2499 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_sync_rhs_array_muxed4 + connect \Y $not$ls180.v:7845$2499_Y + end + attribute \src "ls180.v:7856.8-7856.33" + cell $not $not$ls180.v:7856$2500 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_tccdcon_ready + connect \Y $not$ls180.v:7856$2500_Y + end + attribute \src "ls180.v:7871.8-7871.33" + cell $not $not$ls180.v:7871$2503 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_twtrcon_ready + connect \Y $not$ls180.v:7871$2503_Y + end + attribute \src "ls180.v:7907.27-7907.40" + cell $not $not$ls180.v:7907$2533 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_tx_busy + connect \Y $not$ls180.v:7907$2533_Y + end + attribute \src "ls180.v:7907.46-7907.62" + cell $not $not$ls180.v:7907$2535 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sink_ready + connect \Y $not$ls180.v:7907$2535_Y + end + attribute \src "ls180.v:7936.7-7936.20" + cell $not $not$ls180.v:7936$2542 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_rx_busy + connect \Y $not$ls180.v:7936$2542_Y + end + attribute \src "ls180.v:7937.9-7937.17" + cell $not $not$ls180.v:7937$2543 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_rx + connect \Y $not$ls180.v:7937$2543_Y + end + attribute \src "ls180.v:7970.8-7970.29" + cell $not $not$ls180.v:7970$2549 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_tx_trigger + connect \Y $not$ls180.v:7970$2549_Y + end + attribute \src "ls180.v:7977.8-7977.29" + cell $not $not$ls180.v:7977$2551 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_rx_trigger + connect \Y $not$ls180.v:7977$2551_Y + end + attribute \src "ls180.v:7987.80-7987.106" + cell $not $not$ls180.v:7987$2554 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_tx_fifo_replace + connect \Y $not$ls180.v:7987$2554_Y + end + attribute \src "ls180.v:7993.80-7993.106" + cell $not $not$ls180.v:7993$2559 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_tx_fifo_replace + connect \Y $not$ls180.v:7993$2559_Y + end + attribute \src "ls180.v:7994.8-7994.34" + cell $not $not$ls180.v:7994$2561 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_tx_fifo_do_read + connect \Y $not$ls180.v:7994$2561_Y + end + attribute \src "ls180.v:8009.80-8009.106" + cell $not $not$ls180.v:8009$2565 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_rx_fifo_replace + connect \Y $not$ls180.v:8009$2565_Y + end + attribute \src "ls180.v:8015.80-8015.106" + cell $not $not$ls180.v:8015$2570 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_rx_fifo_replace + connect \Y $not$ls180.v:8015$2570_Y + end + attribute \src "ls180.v:8016.8-8016.34" + cell $not $not$ls180.v:8016$2572 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_rx_fifo_do_read + connect \Y $not$ls180.v:8016$2572_Y + end + attribute \src "ls180.v:8047.23-8047.42" + cell $not $not$ls180.v:8047$2576 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_spi_master_cs + connect \Y $not$ls180.v:8047$2576_Y + end + attribute \src "ls180.v:8047.47-8047.73" + cell $not $not$ls180.v:8047$2577 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_spi_master_cs_enable + connect \Y $not$ls180.v:8047$2577_Y + end + attribute \src "ls180.v:8101.7-8101.31" + cell $not $not$ls180.v:8101$2588 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_clocker_stop + connect \Y $not$ls180.v:8101$2588_Y + end + attribute \src "ls180.v:8173.8-8173.46" + cell $not $not$ls180.v:8173$2600 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_cmdr_buf_source_valid + connect \Y $not$ls180.v:8173$2600_Y + end + attribute \src "ls180.v:8254.8-8254.47" + cell $not $not$ls180.v:8254$2612 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_crcr_buf_source_valid + connect \Y $not$ls180.v:8254$2612_Y + end + attribute \src "ls180.v:8315.8-8315.48" + cell $not $not$ls180.v:8315$2624 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_datar_buf_source_valid + connect \Y $not$ls180.v:8315$2624_Y + end + attribute \src "ls180.v:8485.88-8485.118" + cell $not $not$ls180.v:8485$2638 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_fifo_replace + connect \Y $not$ls180.v:8485$2638_Y + end + attribute \src "ls180.v:8491.88-8491.118" + cell $not $not$ls180.v:8491$2643 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_fifo_replace + connect \Y $not$ls180.v:8491$2643_Y + end + attribute \src "ls180.v:8492.8-8492.38" + cell $not $not$ls180.v:8492$2645 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_fifo_do_read + connect \Y $not$ls180.v:8492$2645_Y + end + attribute \src "ls180.v:8571.88-8571.118" + cell $not $not$ls180.v:8571$2660 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_fifo_replace + connect \Y $not$ls180.v:8571$2660_Y + end + attribute \src "ls180.v:8577.88-8577.118" + cell $not $not$ls180.v:8577$2665 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_fifo_replace + connect \Y $not$ls180.v:8577$2665_Y + end + attribute \src "ls180.v:8578.8-8578.38" + cell $not $not$ls180.v:8578$2667 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_fifo_do_read + connect \Y $not$ls180.v:8578$2667_Y + end + attribute \src "ls180.v:8595.22-8595.37" + cell $not $not$ls180.v:8595$2671 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_cs + connect \Y $not$ls180.v:8595$2671_Y + end + attribute \src "ls180.v:8595.42-8595.64" + cell $not $not$ls180.v:8595$2672 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_cs_enable + connect \Y $not$ls180.v:8595$2672_Y + end + attribute \src "ls180.v:8633.9-8633.28" + cell $not $not$ls180.v:8633$2675 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_request [0] + connect \Y $not$ls180.v:8633$2675_Y + end + attribute \src "ls180.v:8652.9-8652.28" + cell $not $not$ls180.v:8652$2676 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_request [1] + connect \Y $not$ls180.v:8652$2676_Y + end + attribute \src "ls180.v:8671.9-8671.28" + cell $not $not$ls180.v:8671$2677 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_request [2] + connect \Y $not$ls180.v:8671$2677_Y + end + attribute \src "ls180.v:8690.9-8690.28" + cell $not $not$ls180.v:8690$2678 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_request [3] + connect \Y $not$ls180.v:8690$2678_Y + end + attribute \src "ls180.v:8709.9-8709.28" + cell $not $not$ls180.v:8709$2679 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_request [4] + connect \Y $not$ls180.v:8709$2679_Y + end + attribute \src "ls180.v:8730.8-8730.21" + cell $not $not$ls180.v:8730$2680 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_done + connect \Y $not$ls180.v:8730$2680_Y + end + attribute \src "ls180.v:10195.8-10195.51" + cell $or $or$ls180.v:10195$2752 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \sys_rst_1 + connect \B \main_libresocsim_libresoc_reset + connect \Y $or$ls180.v:10195$2752_Y + end + attribute \src "ls180.v:2767.10-2767.96" + cell $or $or$ls180.v:2767$21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_interface0_converted_interface_ack + connect \B \main_libresocsim_converter0_skip + connect \Y $or$ls180.v:2767$21_Y + end + attribute \src "ls180.v:2827.10-2827.96" + cell $or $or$ls180.v:2827$32 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_interface1_converted_interface_ack + connect \B \main_libresocsim_converter1_skip + connect \Y $or$ls180.v:2827$32_Y + end + attribute \src "ls180.v:2887.10-2887.96" + cell $or $or$ls180.v:2887$43 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_interface2_converted_interface_ack + connect \B \main_libresocsim_converter2_skip + connect \Y $or$ls180.v:2887$43_Y + end + attribute \src "ls180.v:3079.39-3079.105" + cell $or $or$ls180.v:3079$75 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_sequencer_start0 + connect \B $ne$ls180.v:3079$74_Y + connect \Y $or$ls180.v:3079$75_Y + end + attribute \src "ls180.v:3122.59-3122.140" + cell $or $or$ls180.v:3122$79 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_req_wdata_ready + connect \B \main_sdram_bankmachine0_req_rdata_valid + connect \Y $or$ls180.v:3122$79_Y + end + attribute \src "ls180.v:3123.44-3123.151" + cell $or $or$ls180.v:3123$80 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_source_valid + connect \B \main_sdram_bankmachine0_cmd_buffer_source_valid + connect \Y $or$ls180.v:3123$80_Y + end + attribute \src "ls180.v:3131.45-3131.170" + cell $or $or$ls180.v:3131$84 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 13 + connect \A $sshl$ls180.v:3131$83_Y + connect \B { 4'0000 \main_sdram_bankmachine0_cmd_buffer_source_payload_addr [8:0] } + connect \Y $or$ls180.v:3131$84_Y + end + attribute \src "ls180.v:3168.127-3168.245" + cell $or $or$ls180.v:3168$97 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable + connect \B \main_sdram_bankmachine0_cmd_buffer_lookahead_replace + connect \Y $or$ls180.v:3168$97_Y + end + attribute \src "ls180.v:3174.57-3174.157" + cell $or $or$ls180.v:3174$103 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:3174$102_Y + connect \B \main_sdram_bankmachine0_cmd_buffer_source_ready + connect \Y $or$ls180.v:3174$103_Y + end + attribute \src "ls180.v:3279.59-3279.140" + cell $or $or$ls180.v:3279$109 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_req_wdata_ready + connect \B \main_sdram_bankmachine1_req_rdata_valid + connect \Y $or$ls180.v:3279$109_Y + end + attribute \src "ls180.v:3280.44-3280.151" + cell $or $or$ls180.v:3280$110 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_source_valid + connect \B \main_sdram_bankmachine1_cmd_buffer_source_valid + connect \Y $or$ls180.v:3280$110_Y + end + attribute \src "ls180.v:3288.45-3288.170" + cell $or $or$ls180.v:3288$114 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 13 + connect \A $sshl$ls180.v:3288$113_Y + connect \B { 4'0000 \main_sdram_bankmachine1_cmd_buffer_source_payload_addr [8:0] } + connect \Y $or$ls180.v:3288$114_Y + end + attribute \src "ls180.v:3325.127-3325.245" + cell $or $or$ls180.v:3325$127 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable + connect \B \main_sdram_bankmachine1_cmd_buffer_lookahead_replace + connect \Y $or$ls180.v:3325$127_Y + end + attribute \src "ls180.v:3331.57-3331.157" + cell $or $or$ls180.v:3331$133 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:3331$132_Y + connect \B \main_sdram_bankmachine1_cmd_buffer_source_ready + connect \Y $or$ls180.v:3331$133_Y + end + attribute \src "ls180.v:3436.59-3436.140" + cell $or $or$ls180.v:3436$139 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_req_wdata_ready + connect \B \main_sdram_bankmachine2_req_rdata_valid + connect \Y $or$ls180.v:3436$139_Y + end + attribute \src "ls180.v:3437.44-3437.151" + cell $or $or$ls180.v:3437$140 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_source_valid + connect \B \main_sdram_bankmachine2_cmd_buffer_source_valid + connect \Y $or$ls180.v:3437$140_Y + end + attribute \src "ls180.v:3445.45-3445.170" + cell $or $or$ls180.v:3445$144 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 13 + connect \A $sshl$ls180.v:3445$143_Y + connect \B { 4'0000 \main_sdram_bankmachine2_cmd_buffer_source_payload_addr [8:0] } + connect \Y $or$ls180.v:3445$144_Y + end + attribute \src "ls180.v:3482.127-3482.245" + cell $or $or$ls180.v:3482$157 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable + connect \B \main_sdram_bankmachine2_cmd_buffer_lookahead_replace + connect \Y $or$ls180.v:3482$157_Y + end + attribute \src "ls180.v:3488.57-3488.157" + cell $or $or$ls180.v:3488$163 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:3488$162_Y + connect \B \main_sdram_bankmachine2_cmd_buffer_source_ready + connect \Y $or$ls180.v:3488$163_Y + end + attribute \src "ls180.v:3593.59-3593.140" + cell $or $or$ls180.v:3593$169 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_req_wdata_ready + connect \B \main_sdram_bankmachine3_req_rdata_valid + connect \Y $or$ls180.v:3593$169_Y + end + attribute \src "ls180.v:3594.44-3594.151" + cell $or $or$ls180.v:3594$170 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_source_valid + connect \B \main_sdram_bankmachine3_cmd_buffer_source_valid + connect \Y $or$ls180.v:3594$170_Y + end + attribute \src "ls180.v:3602.45-3602.170" + cell $or $or$ls180.v:3602$174 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 13 + connect \A $sshl$ls180.v:3602$173_Y + connect \B { 4'0000 \main_sdram_bankmachine3_cmd_buffer_source_payload_addr [8:0] } + connect \Y $or$ls180.v:3602$174_Y + end + attribute \src "ls180.v:3639.127-3639.245" + cell $or $or$ls180.v:3639$187 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable + connect \B \main_sdram_bankmachine3_cmd_buffer_lookahead_replace + connect \Y $or$ls180.v:3639$187_Y + end + attribute \src "ls180.v:3645.57-3645.157" + cell $or $or$ls180.v:3645$193 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:3645$192_Y + connect \B \main_sdram_bankmachine3_cmd_buffer_source_ready + connect \Y $or$ls180.v:3645$193_Y + end + attribute \src "ls180.v:3744.107-3744.193" + cell $or $or$ls180.v:3744$213 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_payload_is_write + connect \B \main_sdram_choose_req_cmd_payload_is_read + connect \Y $or$ls180.v:3744$213_Y + end + attribute \src "ls180.v:3747.39-3747.204" + cell $or $or$ls180.v:3747$219 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3747$217_Y + connect \B $and$ls180.v:3747$218_Y + connect \Y $or$ls180.v:3747$219_Y + end + attribute \src "ls180.v:3747.38-3747.289" + cell $or $or$ls180.v:3747$221 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:3747$219_Y + connect \B $and$ls180.v:3747$220_Y + connect \Y $or$ls180.v:3747$221_Y + end + attribute \src "ls180.v:3747.37-3747.374" + cell $or $or$ls180.v:3747$223 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:3747$221_Y + connect \B $and$ls180.v:3747$222_Y + connect \Y $or$ls180.v:3747$223_Y + end + attribute \src "ls180.v:3748.40-3748.207" + cell $or $or$ls180.v:3748$226 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3748$224_Y + connect \B $and$ls180.v:3748$225_Y + connect \Y $or$ls180.v:3748$226_Y + end + attribute \src "ls180.v:3748.39-3748.293" + cell $or $or$ls180.v:3748$228 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:3748$226_Y + connect \B $and$ls180.v:3748$227_Y + connect \Y $or$ls180.v:3748$228_Y + end + attribute \src "ls180.v:3748.38-3748.379" + cell $or $or$ls180.v:3748$230 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:3748$228_Y + connect \B $and$ls180.v:3748$229_Y + connect \Y $or$ls180.v:3748$230_Y + end + attribute \src "ls180.v:3761.158-3761.332" + cell $or $or$ls180.v:3761$244 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:3761$243_Y + connect \B \main_sdram_choose_cmd_want_activates + connect \Y $or$ls180.v:3761$244_Y + end + attribute \src "ls180.v:3761.75-3761.506" + cell $or $or$ls180.v:3761$249 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3761$245_Y + connect \B $and$ls180.v:3761$248_Y + connect \Y $or$ls180.v:3761$249_Y + end + attribute \src "ls180.v:3762.158-3762.332" + cell $or $or$ls180.v:3762$257 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:3762$256_Y + connect \B \main_sdram_choose_cmd_want_activates + connect \Y $or$ls180.v:3762$257_Y + end + attribute \src "ls180.v:3762.75-3762.506" + cell $or $or$ls180.v:3762$262 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3762$258_Y + connect \B $and$ls180.v:3762$261_Y + connect \Y $or$ls180.v:3762$262_Y + end + attribute \src "ls180.v:3763.158-3763.332" + cell $or $or$ls180.v:3763$270 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:3763$269_Y + connect \B \main_sdram_choose_cmd_want_activates + connect \Y $or$ls180.v:3763$270_Y + end + attribute \src "ls180.v:3763.75-3763.506" + cell $or $or$ls180.v:3763$275 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3763$271_Y + connect \B $and$ls180.v:3763$274_Y + connect \Y $or$ls180.v:3763$275_Y + end + attribute \src "ls180.v:3764.158-3764.332" + cell $or $or$ls180.v:3764$283 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:3764$282_Y + connect \B \main_sdram_choose_cmd_want_activates + connect \Y $or$ls180.v:3764$283_Y + end + attribute \src "ls180.v:3764.75-3764.506" + cell $or $or$ls180.v:3764$288 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3764$284_Y + connect \B $and$ls180.v:3764$287_Y + connect \Y $or$ls180.v:3764$288_Y + end + attribute \src "ls180.v:3791.36-3791.104" + cell $or $or$ls180.v:3791$294 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_cmd_cmd_ready + connect \B $not$ls180.v:3791$293_Y + connect \Y $or$ls180.v:3791$294_Y + end + attribute \src "ls180.v:3794.158-3794.332" + cell $or $or$ls180.v:3794$302 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:3794$301_Y + connect \B \main_sdram_choose_req_want_activates + connect \Y $or$ls180.v:3794$302_Y + end + attribute \src "ls180.v:3794.75-3794.506" + cell $or $or$ls180.v:3794$307 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3794$303_Y + connect \B $and$ls180.v:3794$306_Y + connect \Y $or$ls180.v:3794$307_Y + end + attribute \src "ls180.v:3795.158-3795.332" + cell $or $or$ls180.v:3795$315 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:3795$314_Y + connect \B \main_sdram_choose_req_want_activates + connect \Y $or$ls180.v:3795$315_Y + end + attribute \src "ls180.v:3795.75-3795.506" + cell $or $or$ls180.v:3795$320 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3795$316_Y + connect \B $and$ls180.v:3795$319_Y + connect \Y $or$ls180.v:3795$320_Y + end + attribute \src "ls180.v:3796.158-3796.332" + cell $or $or$ls180.v:3796$328 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:3796$327_Y + connect \B \main_sdram_choose_req_want_activates + connect \Y $or$ls180.v:3796$328_Y + end + attribute \src "ls180.v:3796.75-3796.506" + cell $or $or$ls180.v:3796$333 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3796$329_Y + connect \B $and$ls180.v:3796$332_Y + connect \Y $or$ls180.v:3796$333_Y + end + attribute \src "ls180.v:3797.158-3797.332" + cell $or $or$ls180.v:3797$341 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:3797$340_Y + connect \B \main_sdram_choose_req_want_activates + connect \Y $or$ls180.v:3797$341_Y + end + attribute \src "ls180.v:3797.75-3797.506" + cell $or $or$ls180.v:3797$346 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3797$342_Y + connect \B $and$ls180.v:3797$345_Y + connect \Y $or$ls180.v:3797$346_Y + end + attribute \src "ls180.v:3860.36-3860.104" + cell $or $or$ls180.v:3860$380 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_ready + connect \B $not$ls180.v:3860$379_Y + connect \Y $or$ls180.v:3860$380_Y + end + attribute \src "ls180.v:3881.67-3881.221" + cell $or $or$ls180.v:3881$387 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:3881$386_Y + connect \B \main_sdram_ras_allowed + connect \Y $or$ls180.v:3881$387_Y + end + attribute \src "ls180.v:3889.10-3889.62" + cell $or $or$ls180.v:3889$390 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:3889$389_Y + connect \B \main_sdram_max_time1 + connect \Y $or$ls180.v:3889$390_Y + end + attribute \src "ls180.v:3919.67-3919.221" + cell $or $or$ls180.v:3919$396 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:3919$395_Y + connect \B \main_sdram_ras_allowed + connect \Y $or$ls180.v:3919$396_Y + end + attribute \src "ls180.v:3927.10-3927.61" + cell $or $or$ls180.v:3927$399 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:3927$398_Y + connect \B \main_sdram_max_time0 + connect \Y $or$ls180.v:3927$399_Y + end + attribute \src "ls180.v:3937.91-3937.180" + cell $or $or$ls180.v:3937$403 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_locked0 + connect \B $and$ls180.v:3937$402_Y + connect \Y $or$ls180.v:3937$403_Y + end + attribute \src "ls180.v:3937.90-3937.255" + cell $or $or$ls180.v:3937$406 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:3937$403_Y + connect \B $and$ls180.v:3937$405_Y + connect \Y $or$ls180.v:3937$406_Y + end + attribute \src "ls180.v:3937.89-3937.330" + cell $or $or$ls180.v:3937$409 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:3937$406_Y + connect \B $and$ls180.v:3937$408_Y + connect \Y $or$ls180.v:3937$409_Y + end + attribute \src "ls180.v:3942.91-3942.180" + cell $or $or$ls180.v:3942$419 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_locked1 + connect \B $and$ls180.v:3942$418_Y + connect \Y $or$ls180.v:3942$419_Y + end + attribute \src "ls180.v:3942.90-3942.255" + cell $or $or$ls180.v:3942$422 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:3942$419_Y + connect \B $and$ls180.v:3942$421_Y + connect \Y $or$ls180.v:3942$422_Y + end + attribute \src "ls180.v:3942.89-3942.330" + cell $or $or$ls180.v:3942$425 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:3942$422_Y + connect \B $and$ls180.v:3942$424_Y + connect \Y $or$ls180.v:3942$425_Y + end + attribute \src "ls180.v:3947.91-3947.180" + cell $or $or$ls180.v:3947$435 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_locked2 + connect \B $and$ls180.v:3947$434_Y + connect \Y $or$ls180.v:3947$435_Y + end + attribute \src "ls180.v:3947.90-3947.255" + cell $or $or$ls180.v:3947$438 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:3947$435_Y + connect \B $and$ls180.v:3947$437_Y + connect \Y $or$ls180.v:3947$438_Y + end + attribute \src "ls180.v:3947.89-3947.330" + cell $or $or$ls180.v:3947$441 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:3947$438_Y + connect \B $and$ls180.v:3947$440_Y + connect \Y $or$ls180.v:3947$441_Y + end + attribute \src "ls180.v:3952.91-3952.180" + cell $or $or$ls180.v:3952$451 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_locked3 + connect \B $and$ls180.v:3952$450_Y + connect \Y $or$ls180.v:3952$451_Y + end + attribute \src "ls180.v:3952.90-3952.255" + cell $or $or$ls180.v:3952$454 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:3952$451_Y + connect \B $and$ls180.v:3952$453_Y + connect \Y $or$ls180.v:3952$454_Y + end + attribute \src "ls180.v:3952.89-3952.330" + cell $or $or$ls180.v:3952$457 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:3952$454_Y + connect \B $and$ls180.v:3952$456_Y + connect \Y $or$ls180.v:3952$457_Y + end + attribute \src "ls180.v:3957.132-3957.221" + cell $or $or$ls180.v:3957$468 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_locked0 + connect \B $and$ls180.v:3957$467_Y + connect \Y $or$ls180.v:3957$468_Y + end + attribute \src "ls180.v:3957.131-3957.296" + cell $or $or$ls180.v:3957$471 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:3957$468_Y + connect \B $and$ls180.v:3957$470_Y + connect \Y $or$ls180.v:3957$471_Y + end + attribute \src "ls180.v:3957.130-3957.371" + cell $or $or$ls180.v:3957$474 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:3957$471_Y + connect \B $and$ls180.v:3957$473_Y + connect \Y $or$ls180.v:3957$474_Y + end + attribute \src "ls180.v:3957.34-3957.411" + cell $or $or$ls180.v:3957$479 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A 1'0 + connect \B $and$ls180.v:3957$478_Y + connect \Y $or$ls180.v:3957$479_Y + end + attribute \src "ls180.v:3957.506-3957.595" + cell $or $or$ls180.v:3957$484 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_locked1 + connect \B $and$ls180.v:3957$483_Y + connect \Y $or$ls180.v:3957$484_Y + end + attribute \src "ls180.v:3957.505-3957.670" + cell $or $or$ls180.v:3957$487 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:3957$484_Y + connect \B $and$ls180.v:3957$486_Y + connect \Y $or$ls180.v:3957$487_Y + end + attribute \src "ls180.v:3957.504-3957.745" + cell $or $or$ls180.v:3957$490 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:3957$487_Y + connect \B $and$ls180.v:3957$489_Y + connect \Y $or$ls180.v:3957$490_Y + end + attribute \src "ls180.v:3957.33-3957.785" + cell $or $or$ls180.v:3957$495 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:3957$479_Y + connect \B $and$ls180.v:3957$494_Y + connect \Y $or$ls180.v:3957$495_Y + end + attribute \src "ls180.v:3957.880-3957.969" + cell $or $or$ls180.v:3957$500 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_locked2 + connect \B $and$ls180.v:3957$499_Y + connect \Y $or$ls180.v:3957$500_Y + end + attribute \src "ls180.v:3957.879-3957.1044" + cell $or $or$ls180.v:3957$503 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:3957$500_Y + connect \B $and$ls180.v:3957$502_Y + connect \Y $or$ls180.v:3957$503_Y + end + attribute \src "ls180.v:3957.878-3957.1119" + cell $or $or$ls180.v:3957$506 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:3957$503_Y + connect \B $and$ls180.v:3957$505_Y + connect \Y $or$ls180.v:3957$506_Y + end + attribute \src "ls180.v:3957.32-3957.1159" + cell $or $or$ls180.v:3957$511 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:3957$495_Y + connect \B $and$ls180.v:3957$510_Y + connect \Y $or$ls180.v:3957$511_Y + end + attribute \src "ls180.v:3957.1254-3957.1343" + cell $or $or$ls180.v:3957$516 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_locked3 + connect \B $and$ls180.v:3957$515_Y + connect \Y $or$ls180.v:3957$516_Y + end + attribute \src "ls180.v:3957.1253-3957.1418" + cell $or $or$ls180.v:3957$519 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:3957$516_Y + connect \B $and$ls180.v:3957$518_Y + connect \Y $or$ls180.v:3957$519_Y + end + attribute \src "ls180.v:3957.1252-3957.1493" + cell $or $or$ls180.v:3957$522 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:3957$519_Y + connect \B $and$ls180.v:3957$521_Y + connect \Y $or$ls180.v:3957$522_Y + end + attribute \src "ls180.v:3957.31-3957.1533" + cell $or $or$ls180.v:3957$527 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:3957$511_Y + connect \B $and$ls180.v:3957$526_Y + connect \Y $or$ls180.v:3957$527_Y + end + attribute \src "ls180.v:4020.10-4020.52" + cell $or $or$ls180.v:4020$536 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_litedram_wb_ack + connect \B \main_converter_skip + connect \Y $or$ls180.v:4020$536_Y + end + attribute \src "ls180.v:4047.35-4047.74" + cell $or $or$ls180.v:4047$546 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_valid + connect \B \main_cmd_consumed + connect \Y $or$ls180.v:4047$546_Y + end + attribute \src "ls180.v:4048.34-4048.73" + cell $or $or$ls180.v:4048$550 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_valid + connect \B \main_cmd_consumed + connect \Y $or$ls180.v:4048$550_Y + end + attribute \src "ls180.v:4049.48-4049.130" + cell $or $or$ls180.v:4049$556 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4049$553_Y + connect \B $and$ls180.v:4049$555_Y + connect \Y $or$ls180.v:4049$556_Y + end + attribute \src "ls180.v:4050.24-4050.87" + cell $or $or$ls180.v:4050$559 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4050$558_Y + connect \B \main_cmd_consumed + connect \Y $or$ls180.v:4050$559_Y + end + attribute \src "ls180.v:4051.26-4051.95" + cell $or $or$ls180.v:4051$561 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4051$560_Y + connect \B \main_wdata_consumed + connect \Y $or$ls180.v:4051$561_Y + end + attribute \src "ls180.v:4081.42-4081.89" + cell $or $or$ls180.v:4081$569 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_rx_clear + connect \B $and$ls180.v:4081$568_Y + connect \Y $or$ls180.v:4081$569_Y + end + attribute \src "ls180.v:4105.25-4105.174" + cell $or $or$ls180.v:4105$579 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4105$577_Y + connect \B $and$ls180.v:4105$578_Y + connect \Y $or$ls180.v:4105$579_Y + end + attribute \src "ls180.v:4120.80-4120.132" + cell $or $or$ls180.v:4120$581 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:4120$580_Y + connect \B \main_uart_tx_fifo_re + connect \Y $or$ls180.v:4120$581_Y + end + attribute \src "ls180.v:4131.72-4131.135" + cell $or $or$ls180.v:4131$586 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_tx_fifo_syncfifo_writable + connect \B \main_uart_tx_fifo_replace + connect \Y $or$ls180.v:4131$586_Y + end + attribute \src "ls180.v:4150.80-4150.132" + cell $or $or$ls180.v:4150$592 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:4150$591_Y + connect \B \main_uart_rx_fifo_re + connect \Y $or$ls180.v:4150$592_Y + end + attribute \src "ls180.v:4161.72-4161.135" + cell $or $or$ls180.v:4161$597 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_rx_fifo_syncfifo_writable + connect \B \main_uart_rx_fifo_replace + connect \Y $or$ls180.v:4161$597_Y + end + attribute \src "ls180.v:4232.36-4232.111" + cell $or $or$ls180.v:4232$610 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_init_pads_out_payload_clk + connect \B \main_sdphy_cmdw_pads_out_payload_clk + connect \Y $or$ls180.v:4232$610_Y + end + attribute \src "ls180.v:4232.35-4232.151" + cell $or $or$ls180.v:4232$611 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4232$610_Y + connect \B \main_sdphy_cmdr_pads_out_payload_clk + connect \Y $or$ls180.v:4232$611_Y + end + attribute \src "ls180.v:4232.34-4232.192" + cell $or $or$ls180.v:4232$612 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4232$611_Y + connect \B \main_sdphy_dataw_pads_out_payload_clk + connect \Y $or$ls180.v:4232$612_Y + end + attribute \src "ls180.v:4232.33-4232.233" + cell $or $or$ls180.v:4232$613 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4232$612_Y + connect \B \main_sdphy_datar_pads_out_payload_clk + connect \Y $or$ls180.v:4232$613_Y + end + attribute \src "ls180.v:4233.39-4233.120" + cell $or $or$ls180.v:4233$614 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_init_pads_out_payload_cmd_oe + connect \B \main_sdphy_cmdw_pads_out_payload_cmd_oe + connect \Y $or$ls180.v:4233$614_Y + end + attribute \src "ls180.v:4233.38-4233.163" + cell $or $or$ls180.v:4233$615 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4233$614_Y + connect \B \main_sdphy_cmdr_pads_out_payload_cmd_oe + connect \Y $or$ls180.v:4233$615_Y + end + attribute \src "ls180.v:4233.37-4233.207" + cell $or $or$ls180.v:4233$616 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4233$615_Y + connect \B \main_sdphy_dataw_pads_out_payload_cmd_oe + connect \Y $or$ls180.v:4233$616_Y + end + attribute \src "ls180.v:4233.36-4233.251" + cell $or $or$ls180.v:4233$617 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4233$616_Y + connect \B \main_sdphy_datar_pads_out_payload_cmd_oe + connect \Y $or$ls180.v:4233$617_Y + end + attribute \src "ls180.v:4234.38-4234.117" + cell $or $or$ls180.v:4234$618 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_init_pads_out_payload_cmd_o + connect \B \main_sdphy_cmdw_pads_out_payload_cmd_o + connect \Y $or$ls180.v:4234$618_Y + end + attribute \src "ls180.v:4234.37-4234.159" + cell $or $or$ls180.v:4234$619 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4234$618_Y + connect \B \main_sdphy_cmdr_pads_out_payload_cmd_o + connect \Y $or$ls180.v:4234$619_Y + end + attribute \src "ls180.v:4234.36-4234.202" + cell $or $or$ls180.v:4234$620 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4234$619_Y + connect \B \main_sdphy_dataw_pads_out_payload_cmd_o + connect \Y $or$ls180.v:4234$620_Y + end + attribute \src "ls180.v:4234.35-4234.245" + cell $or $or$ls180.v:4234$621 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4234$620_Y + connect \B \main_sdphy_datar_pads_out_payload_cmd_o + connect \Y $or$ls180.v:4234$621_Y + end + attribute \src "ls180.v:4235.40-4235.123" + cell $or $or$ls180.v:4235$622 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_init_pads_out_payload_data_oe + connect \B \main_sdphy_cmdw_pads_out_payload_data_oe + connect \Y $or$ls180.v:4235$622_Y + end + attribute \src "ls180.v:4235.39-4235.167" + cell $or $or$ls180.v:4235$623 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4235$622_Y + connect \B \main_sdphy_cmdr_pads_out_payload_data_oe + connect \Y $or$ls180.v:4235$623_Y + end + attribute \src "ls180.v:4235.38-4235.212" + cell $or $or$ls180.v:4235$624 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4235$623_Y + connect \B \main_sdphy_dataw_pads_out_payload_data_oe + connect \Y $or$ls180.v:4235$624_Y + end + attribute \src "ls180.v:4235.37-4235.257" + cell $or $or$ls180.v:4235$625 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4235$624_Y + connect \B \main_sdphy_datar_pads_out_payload_data_oe + connect \Y $or$ls180.v:4235$625_Y + end + attribute \src "ls180.v:4236.39-4236.120" + cell $or $or$ls180.v:4236$626 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \main_sdphy_init_pads_out_payload_data_o + connect \B \main_sdphy_cmdw_pads_out_payload_data_o + connect \Y $or$ls180.v:4236$626_Y + end + attribute \src "ls180.v:4236.38-4236.163" + cell $or $or$ls180.v:4236$627 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A $or$ls180.v:4236$626_Y + connect \B \main_sdphy_cmdr_pads_out_payload_data_o + connect \Y $or$ls180.v:4236$627_Y + end + attribute \src "ls180.v:4236.37-4236.207" + cell $or $or$ls180.v:4236$628 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A $or$ls180.v:4236$627_Y + connect \B \main_sdphy_dataw_pads_out_payload_data_o + connect \Y $or$ls180.v:4236$628_Y + end + attribute \src "ls180.v:4236.36-4236.251" + cell $or $or$ls180.v:4236$629 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A $or$ls180.v:4236$628_Y + connect \B \main_sdphy_datar_pads_out_payload_data_o + connect \Y $or$ls180.v:4236$629_Y + end + attribute \src "ls180.v:4257.35-4257.80" + cell $or $or$ls180.v:4257$630 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_stop + connect \B \main_sdphy_datar_stop + connect \Y $or$ls180.v:4257$630_Y + end + attribute \src "ls180.v:4411.91-4411.144" + cell $or $or$ls180.v:4411$644 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_cmdr_start + connect \B \main_sdphy_cmdr_cmdr_run + connect \Y $or$ls180.v:4411$644_Y + end + attribute \src "ls180.v:4428.53-4428.143" + cell $or $or$ls180.v:4428$647 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:4428$646_Y + connect \B \main_sdphy_cmdr_cmdr_converter_source_ready + connect \Y $or$ls180.v:4428$647_Y + end + attribute \src "ls180.v:4431.47-4431.127" + cell $or $or$ls180.v:4431$650 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:4431$649_Y + connect \B \main_sdphy_cmdr_cmdr_buf_source_ready + connect \Y $or$ls180.v:4431$650_Y + end + attribute \src "ls180.v:4555.54-4555.146" + cell $or $or$ls180.v:4555$668 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:4555$667_Y + connect \B \main_sdphy_dataw_crcr_converter_source_ready + connect \Y $or$ls180.v:4555$668_Y + end + attribute \src "ls180.v:4558.48-4558.130" + cell $or $or$ls180.v:4558$671 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:4558$670_Y + connect \B \main_sdphy_dataw_crcr_buf_source_ready + connect \Y $or$ls180.v:4558$671_Y + end + attribute \src "ls180.v:4689.55-4689.149" + cell $or $or$ls180.v:4689$683 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:4689$682_Y + connect \B \main_sdphy_datar_datar_converter_source_ready + connect \Y $or$ls180.v:4689$683_Y + end + attribute \src "ls180.v:4692.49-4692.133" + cell $or $or$ls180.v:4692$686 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:4692$685_Y + connect \B \main_sdphy_datar_datar_buf_source_ready + connect \Y $or$ls180.v:4692$686_Y + end + attribute \src "ls180.v:5321.80-5321.151" + cell $or $or$ls180.v:5321$981 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_fifo_syncfifo_writable + connect \B \main_sdblock2mem_fifo_replace + connect \Y $or$ls180.v:5321$981_Y + end + attribute \src "ls180.v:5332.49-5332.131" + cell $or $or$ls180.v:5332$987 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:5332$986_Y + connect \B \main_sdblock2mem_converter_source_ready + connect \Y $or$ls180.v:5332$987_Y + end + attribute \src "ls180.v:5529.80-5529.151" + cell $or $or$ls180.v:5529$1012 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_fifo_syncfifo_writable + connect \B \main_sdmem2block_fifo_replace + connect \Y $or$ls180.v:5529$1012_Y + end + attribute \src "ls180.v:5703.33-5703.102" + cell $or $or$ls180.v:5703$1060 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_ram_bus_err + connect \B \main_libresocsim_libresoc_xics_icp_err + connect \Y $or$ls180.v:5703$1060_Y + end + attribute \src "ls180.v:5703.32-5703.144" + cell $or $or$ls180.v:5703$1061 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:5703$1060_Y + connect \B \main_libresocsim_libresoc_xics_ics_err + connect \Y $or$ls180.v:5703$1061_Y + end + attribute \src "ls180.v:5703.31-5703.165" + cell $or $or$ls180.v:5703$1062 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:5703$1061_Y + connect \B \main_wb_sdram_err + connect \Y $or$ls180.v:5703$1062_Y + end + attribute \src "ls180.v:5703.30-5703.201" + cell $or $or$ls180.v:5703$1063 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:5703$1062_Y + connect \B \builder_libresocsim_wishbone_err + connect \Y $or$ls180.v:5703$1063_Y + end + attribute \src "ls180.v:5709.28-5709.97" + cell $or $or$ls180.v:5709$1068 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_ram_bus_ack + connect \B \main_libresocsim_libresoc_xics_icp_ack + connect \Y $or$ls180.v:5709$1068_Y + end + attribute \src "ls180.v:5709.27-5709.139" + cell $or $or$ls180.v:5709$1069 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:5709$1068_Y + connect \B \main_libresocsim_libresoc_xics_ics_ack + connect \Y $or$ls180.v:5709$1069_Y + end + attribute \src "ls180.v:5709.26-5709.160" + cell $or $or$ls180.v:5709$1070 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:5709$1069_Y + connect \B \main_wb_sdram_ack + connect \Y $or$ls180.v:5709$1070_Y + end + attribute \src "ls180.v:5709.25-5709.196" + cell $or $or$ls180.v:5709$1071 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:5709$1070_Y + connect \B \builder_libresocsim_wishbone_ack + connect \Y $or$ls180.v:5709$1071_Y + end + attribute \src "ls180.v:5710.30-5710.169" + cell $or $or$ls180.v:5710$1074 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A $and$ls180.v:5710$1072_Y + connect \B $and$ls180.v:5710$1073_Y + connect \Y $or$ls180.v:5710$1074_Y + end + attribute \src "ls180.v:5710.29-5710.246" + cell $or $or$ls180.v:5710$1076 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A $or$ls180.v:5710$1074_Y + connect \B $and$ls180.v:5710$1075_Y + connect \Y $or$ls180.v:5710$1076_Y + end + attribute \src "ls180.v:5710.28-5710.302" + cell $or $or$ls180.v:5710$1078 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A $or$ls180.v:5710$1076_Y + connect \B $and$ls180.v:5710$1077_Y + connect \Y $or$ls180.v:5710$1078_Y + end + attribute \src "ls180.v:5710.27-5710.373" + cell $or $or$ls180.v:5710$1080 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A $or$ls180.v:5710$1078_Y + connect \B $and$ls180.v:5710$1079_Y + connect \Y $or$ls180.v:5710$1080_Y + end + attribute \src "ls180.v:6447.54-6447.123" + cell $or $or$ls180.v:6447$2211 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A \builder_interface0_bank_bus_dat_r + connect \B \builder_interface1_bank_bus_dat_r + connect \Y $or$ls180.v:6447$2211_Y + end + attribute \src "ls180.v:6447.53-6447.160" + cell $or $or$ls180.v:6447$2212 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $or$ls180.v:6447$2211_Y + connect \B \builder_interface2_bank_bus_dat_r + connect \Y $or$ls180.v:6447$2212_Y + end + attribute \src "ls180.v:6447.52-6447.197" + cell $or $or$ls180.v:6447$2213 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $or$ls180.v:6447$2212_Y + connect \B \builder_interface3_bank_bus_dat_r + connect \Y $or$ls180.v:6447$2213_Y + end + attribute \src "ls180.v:6447.51-6447.234" + cell $or $or$ls180.v:6447$2214 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $or$ls180.v:6447$2213_Y + connect \B \builder_interface4_bank_bus_dat_r + connect \Y $or$ls180.v:6447$2214_Y + end + attribute \src "ls180.v:6447.50-6447.271" + cell $or $or$ls180.v:6447$2215 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $or$ls180.v:6447$2214_Y + connect \B \builder_interface5_bank_bus_dat_r + connect \Y $or$ls180.v:6447$2215_Y + end + attribute \src "ls180.v:6447.49-6447.308" + cell $or $or$ls180.v:6447$2216 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $or$ls180.v:6447$2215_Y + connect \B \builder_interface6_bank_bus_dat_r + connect \Y $or$ls180.v:6447$2216_Y + end + attribute \src "ls180.v:6447.48-6447.345" + cell $or $or$ls180.v:6447$2217 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $or$ls180.v:6447$2216_Y + connect \B \builder_interface7_bank_bus_dat_r + connect \Y $or$ls180.v:6447$2217_Y + end + attribute \src "ls180.v:6447.47-6447.382" + cell $or $or$ls180.v:6447$2218 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $or$ls180.v:6447$2217_Y + connect \B \builder_interface8_bank_bus_dat_r + connect \Y $or$ls180.v:6447$2218_Y + end + attribute \src "ls180.v:6447.46-6447.419" + cell $or $or$ls180.v:6447$2219 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $or$ls180.v:6447$2218_Y + connect \B \builder_interface9_bank_bus_dat_r + connect \Y $or$ls180.v:6447$2219_Y + end + attribute \src "ls180.v:6447.45-6447.457" + cell $or $or$ls180.v:6447$2220 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $or$ls180.v:6447$2219_Y + connect \B \builder_interface10_bank_bus_dat_r + connect \Y $or$ls180.v:6447$2220_Y + end + attribute \src "ls180.v:6447.44-6447.495" + cell $or $or$ls180.v:6447$2221 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $or$ls180.v:6447$2220_Y + connect \B \builder_interface11_bank_bus_dat_r + connect \Y $or$ls180.v:6447$2221_Y + end + attribute \src "ls180.v:6447.43-6447.533" + cell $or $or$ls180.v:6447$2222 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $or$ls180.v:6447$2221_Y + connect \B \builder_interface12_bank_bus_dat_r + connect \Y $or$ls180.v:6447$2222_Y + end + attribute \src "ls180.v:6447.42-6447.571" + cell $or $or$ls180.v:6447$2223 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $or$ls180.v:6447$2222_Y + connect \B \builder_interface13_bank_bus_dat_r + connect \Y $or$ls180.v:6447$2223_Y + end + attribute \src "ls180.v:6774.90-6774.179" + cell $or $or$ls180.v:6774$2248 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_locked0 + connect \B $and$ls180.v:6774$2247_Y + connect \Y $or$ls180.v:6774$2248_Y + end + attribute \src "ls180.v:6774.89-6774.254" + cell $or $or$ls180.v:6774$2251 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:6774$2248_Y + connect \B $and$ls180.v:6774$2250_Y + connect \Y $or$ls180.v:6774$2251_Y + end + attribute \src "ls180.v:6774.88-6774.329" + cell $or $or$ls180.v:6774$2254 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:6774$2251_Y + connect \B $and$ls180.v:6774$2253_Y + connect \Y $or$ls180.v:6774$2254_Y + end + attribute \src "ls180.v:6798.90-6798.179" + cell $or $or$ls180.v:6798$2264 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_locked1 + connect \B $and$ls180.v:6798$2263_Y + connect \Y $or$ls180.v:6798$2264_Y + end + attribute \src "ls180.v:6798.89-6798.254" + cell $or $or$ls180.v:6798$2267 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:6798$2264_Y + connect \B $and$ls180.v:6798$2266_Y + connect \Y $or$ls180.v:6798$2267_Y + end + attribute \src "ls180.v:6798.88-6798.329" + cell $or $or$ls180.v:6798$2270 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:6798$2267_Y + connect \B $and$ls180.v:6798$2269_Y + connect \Y $or$ls180.v:6798$2270_Y + end + attribute \src "ls180.v:6822.90-6822.179" + cell $or $or$ls180.v:6822$2280 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_locked2 + connect \B $and$ls180.v:6822$2279_Y + connect \Y $or$ls180.v:6822$2280_Y + end + attribute \src "ls180.v:6822.89-6822.254" + cell $or $or$ls180.v:6822$2283 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:6822$2280_Y + connect \B $and$ls180.v:6822$2282_Y + connect \Y $or$ls180.v:6822$2283_Y + end + attribute \src "ls180.v:6822.88-6822.329" + cell $or $or$ls180.v:6822$2286 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:6822$2283_Y + connect \B $and$ls180.v:6822$2285_Y + connect \Y $or$ls180.v:6822$2286_Y + end + attribute \src "ls180.v:6846.90-6846.179" + cell $or $or$ls180.v:6846$2296 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_locked3 + connect \B $and$ls180.v:6846$2295_Y + connect \Y $or$ls180.v:6846$2296_Y + end + attribute \src "ls180.v:6846.89-6846.254" + cell $or $or$ls180.v:6846$2299 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:6846$2296_Y + connect \B $and$ls180.v:6846$2298_Y + connect \Y $or$ls180.v:6846$2299_Y + end + attribute \src "ls180.v:6846.88-6846.329" + cell $or $or$ls180.v:6846$2302 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:6846$2299_Y + connect \B $and$ls180.v:6846$2301_Y + connect \Y $or$ls180.v:6846$2302_Y + end + attribute \src "ls180.v:7360.20-7360.71" + cell $or $or$ls180.v:7360$2359 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [0] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7360$2359_Y + end + attribute \src "ls180.v:7361.20-7361.71" + cell $or $or$ls180.v:7361$2360 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [1] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7361$2360_Y + end + attribute \src "ls180.v:7362.20-7362.71" + cell $or $or$ls180.v:7362$2361 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [2] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7362$2361_Y + end + attribute \src "ls180.v:7363.20-7363.71" + cell $or $or$ls180.v:7363$2362 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [3] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7363$2362_Y + end + attribute \src "ls180.v:7364.20-7364.71" + cell $or $or$ls180.v:7364$2363 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [4] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7364$2363_Y + end + attribute \src "ls180.v:7365.20-7365.71" + cell $or $or$ls180.v:7365$2364 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [5] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7365$2364_Y + end + attribute \src "ls180.v:7366.20-7366.71" + cell $or $or$ls180.v:7366$2365 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [6] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7366$2365_Y + end + attribute \src "ls180.v:7367.20-7367.71" + cell $or $or$ls180.v:7367$2366 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [7] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7367$2366_Y + end + attribute \src "ls180.v:7368.20-7368.71" + cell $or $or$ls180.v:7368$2367 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [8] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7368$2367_Y + end + attribute \src "ls180.v:7369.20-7369.71" + cell $or $or$ls180.v:7369$2368 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [9] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7369$2368_Y + end + attribute \src "ls180.v:7370.21-7370.73" + cell $or $or$ls180.v:7370$2369 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [10] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7370$2369_Y + end + attribute \src "ls180.v:7371.21-7371.73" + cell $or $or$ls180.v:7371$2370 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [11] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7371$2370_Y + end + attribute \src "ls180.v:7372.21-7372.73" + cell $or $or$ls180.v:7372$2371 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [12] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7372$2371_Y + end + attribute \src "ls180.v:7373.21-7373.73" + cell $or $or$ls180.v:7373$2372 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [13] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7373$2372_Y + end + attribute \src "ls180.v:7374.21-7374.73" + cell $or $or$ls180.v:7374$2373 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [14] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7374$2373_Y + end + attribute \src "ls180.v:7375.21-7375.73" + cell $or $or$ls180.v:7375$2374 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [15] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7375$2374_Y + end + attribute \src "ls180.v:7376.21-7376.73" + cell $or $or$ls180.v:7376$2375 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [16] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7376$2375_Y + end + attribute \src "ls180.v:7377.21-7377.73" + cell $or $or$ls180.v:7377$2376 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [17] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7377$2376_Y + end + attribute \src "ls180.v:7378.21-7378.73" + cell $or $or$ls180.v:7378$2377 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [18] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7378$2377_Y + end + attribute \src "ls180.v:7379.21-7379.73" + cell $or $or$ls180.v:7379$2378 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [19] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7379$2378_Y + end + attribute \src "ls180.v:7380.21-7380.73" + cell $or $or$ls180.v:7380$2379 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [20] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7380$2379_Y + end + attribute \src "ls180.v:7381.21-7381.73" + cell $or $or$ls180.v:7381$2380 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [21] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7381$2380_Y + end + attribute \src "ls180.v:7382.21-7382.73" + cell $or $or$ls180.v:7382$2381 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [22] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7382$2381_Y + end + attribute \src "ls180.v:7383.21-7383.73" + cell $or $or$ls180.v:7383$2382 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [23] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7383$2382_Y + end + attribute \src "ls180.v:7384.21-7384.73" + cell $or $or$ls180.v:7384$2383 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [24] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7384$2383_Y + end + attribute \src "ls180.v:7385.21-7385.73" + cell $or $or$ls180.v:7385$2384 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [25] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7385$2384_Y + end + attribute \src "ls180.v:7386.21-7386.73" + cell $or $or$ls180.v:7386$2385 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [26] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7386$2385_Y + end + attribute \src "ls180.v:7387.21-7387.73" + cell $or $or$ls180.v:7387$2386 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [27] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7387$2386_Y + end + attribute \src "ls180.v:7388.21-7388.73" + cell $or $or$ls180.v:7388$2387 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [28] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7388$2387_Y + end + attribute \src "ls180.v:7389.21-7389.73" + cell $or $or$ls180.v:7389$2388 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [29] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7389$2388_Y + end + attribute \src "ls180.v:7390.21-7390.73" + cell $or $or$ls180.v:7390$2389 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [30] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7390$2389_Y + end + attribute \src "ls180.v:7391.21-7391.73" + cell $or $or$ls180.v:7391$2390 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [31] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7391$2390_Y + end + attribute \src "ls180.v:7392.21-7392.73" + cell $or $or$ls180.v:7392$2391 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [32] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7392$2391_Y + end + attribute \src "ls180.v:7393.21-7393.73" + cell $or $or$ls180.v:7393$2392 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [33] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7393$2392_Y + end + attribute \src "ls180.v:7394.21-7394.73" + cell $or $or$ls180.v:7394$2393 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [34] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7394$2393_Y + end + attribute \src "ls180.v:7395.21-7395.73" + cell $or $or$ls180.v:7395$2394 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [35] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7395$2394_Y + end + attribute \src "ls180.v:7396.21-7396.73" + cell $or $or$ls180.v:7396$2395 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [36] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7396$2395_Y + end + attribute \src "ls180.v:7397.21-7397.73" + cell $or $or$ls180.v:7397$2396 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [37] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7397$2396_Y + end + attribute \src "ls180.v:7398.21-7398.73" + cell $or $or$ls180.v:7398$2397 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [38] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7398$2397_Y + end + attribute \src "ls180.v:7399.21-7399.73" + cell $or $or$ls180.v:7399$2398 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [39] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7399$2398_Y + end + attribute \src "ls180.v:7400.21-7400.73" + cell $or $or$ls180.v:7400$2399 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [40] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7400$2399_Y + end + attribute \src "ls180.v:7401.21-7401.73" + cell $or $or$ls180.v:7401$2400 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [41] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7401$2400_Y + end + attribute \src "ls180.v:7402.7-7402.93" + cell $or $or$ls180.v:7402$2401 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_interface0_converted_interface_ack + connect \B \main_libresocsim_converter0_skip + connect \Y $or$ls180.v:7402$2401_Y + end + attribute \src "ls180.v:7413.7-7413.93" + cell $or $or$ls180.v:7413$2402 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_interface1_converted_interface_ack + connect \B \main_libresocsim_converter1_skip + connect \Y $or$ls180.v:7413$2402_Y + end + attribute \src "ls180.v:7424.7-7424.93" + cell $or $or$ls180.v:7424$2403 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_interface2_converted_interface_ack + connect \B \main_libresocsim_converter2_skip + connect \Y $or$ls180.v:7424$2403_Y + end + attribute \src "ls180.v:7553.7-7553.107" + cell $or $or$ls180.v:7553$2439 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:7553$2438_Y + connect \B \main_sdram_bankmachine0_cmd_buffer_source_ready + connect \Y $or$ls180.v:7553$2439_Y + end + attribute \src "ls180.v:7599.7-7599.107" + cell $or $or$ls180.v:7599$2455 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:7599$2454_Y + connect \B \main_sdram_bankmachine1_cmd_buffer_source_ready + connect \Y $or$ls180.v:7599$2455_Y + end + attribute \src "ls180.v:7645.7-7645.107" + cell $or $or$ls180.v:7645$2471 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:7645$2470_Y + connect \B \main_sdram_bankmachine2_cmd_buffer_source_ready + connect \Y $or$ls180.v:7645$2471_Y + end + attribute \src "ls180.v:7691.7-7691.107" + cell $or $or$ls180.v:7691$2487 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:7691$2486_Y + connect \B \main_sdram_bankmachine3_cmd_buffer_source_ready + connect \Y $or$ls180.v:7691$2487_Y + end + attribute \src "ls180.v:7879.40-7879.125" + cell $or $or$ls180.v:7879$2508 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A 1'0 + connect \B $and$ls180.v:7879$2507_Y + connect \Y $or$ls180.v:7879$2508_Y + end + attribute \src "ls180.v:7879.39-7879.207" + cell $or $or$ls180.v:7879$2511 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:7879$2508_Y + connect \B $and$ls180.v:7879$2510_Y + connect \Y $or$ls180.v:7879$2511_Y + end + attribute \src "ls180.v:7879.38-7879.289" + cell $or $or$ls180.v:7879$2514 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:7879$2511_Y + connect \B $and$ls180.v:7879$2513_Y + connect \Y $or$ls180.v:7879$2514_Y + end + attribute \src "ls180.v:7879.37-7879.371" + cell $or $or$ls180.v:7879$2517 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:7879$2514_Y + connect \B $and$ls180.v:7879$2516_Y + connect \Y $or$ls180.v:7879$2517_Y + end + attribute \src "ls180.v:7880.41-7880.126" + cell $or $or$ls180.v:7880$2520 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A 1'0 + connect \B $and$ls180.v:7880$2519_Y + connect \Y $or$ls180.v:7880$2520_Y + end + attribute \src "ls180.v:7880.40-7880.208" + cell $or $or$ls180.v:7880$2523 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:7880$2520_Y + connect \B $and$ls180.v:7880$2522_Y + connect \Y $or$ls180.v:7880$2523_Y + end + attribute \src "ls180.v:7880.39-7880.290" + cell $or $or$ls180.v:7880$2526 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:7880$2523_Y + connect \B $and$ls180.v:7880$2525_Y + connect \Y $or$ls180.v:7880$2526_Y + end + attribute \src "ls180.v:7880.38-7880.372" + cell $or $or$ls180.v:7880$2529 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:7880$2526_Y + connect \B $and$ls180.v:7880$2528_Y + connect \Y $or$ls180.v:7880$2529_Y + end + attribute \src "ls180.v:7884.7-7884.49" + cell $or $or$ls180.v:7884$2530 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_litedram_wb_ack + connect \B \main_converter_skip + connect \Y $or$ls180.v:7884$2530_Y + end + attribute \src "ls180.v:8047.22-8047.74" + cell $or $or$ls180.v:8047$2578 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:8047$2576_Y + connect \B $not$ls180.v:8047$2577_Y + connect \Y $or$ls180.v:8047$2578_Y + end + attribute \src "ls180.v:8115.32-8115.85" + cell $or $or$ls180.v:8115$2590 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_cmdr_start + connect \B \main_sdphy_cmdr_cmdr_run + connect \Y $or$ls180.v:8115$2590_Y + end + attribute \src "ls180.v:8121.8-8121.97" + cell $or $or$ls180.v:8121$2592 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:8121$2591_Y + connect \B \main_sdphy_cmdr_cmdr_converter_sink_last + connect \Y $or$ls180.v:8121$2592_Y + end + attribute \src "ls180.v:8138.52-8138.139" + cell $or $or$ls180.v:8138$2597 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_cmdr_converter_sink_first + connect \B \main_sdphy_cmdr_cmdr_converter_source_first + connect \Y $or$ls180.v:8138$2597_Y + end + attribute \src "ls180.v:8139.51-8139.136" + cell $or $or$ls180.v:8139$2598 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_cmdr_converter_sink_last + connect \B \main_sdphy_cmdr_cmdr_converter_source_last + connect \Y $or$ls180.v:8139$2598_Y + end + attribute \src "ls180.v:8173.7-8173.87" + cell $or $or$ls180.v:8173$2601 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:8173$2600_Y + connect \B \main_sdphy_cmdr_cmdr_buf_source_ready + connect \Y $or$ls180.v:8173$2601_Y + end + attribute \src "ls180.v:8196.33-8196.88" + cell $or $or$ls180.v:8196$2602 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_crcr_start + connect \B \main_sdphy_dataw_crcr_run + connect \Y $or$ls180.v:8196$2602_Y + end + attribute \src "ls180.v:8202.8-8202.99" + cell $or $or$ls180.v:8202$2604 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:8202$2603_Y + connect \B \main_sdphy_dataw_crcr_converter_sink_last + connect \Y $or$ls180.v:8202$2604_Y + end + attribute \src "ls180.v:8219.53-8219.142" + cell $or $or$ls180.v:8219$2609 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_crcr_converter_sink_first + connect \B \main_sdphy_dataw_crcr_converter_source_first + connect \Y $or$ls180.v:8219$2609_Y + end + attribute \src "ls180.v:8220.52-8220.139" + cell $or $or$ls180.v:8220$2610 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_crcr_converter_sink_last + connect \B \main_sdphy_dataw_crcr_converter_source_last + connect \Y $or$ls180.v:8220$2610_Y + end + attribute \src "ls180.v:8254.7-8254.89" + cell $or $or$ls180.v:8254$2613 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:8254$2612_Y + connect \B \main_sdphy_dataw_crcr_buf_source_ready + connect \Y $or$ls180.v:8254$2613_Y + end + attribute \src "ls180.v:8275.34-8275.91" + cell $or $or$ls180.v:8275$2614 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_datar_start + connect \B \main_sdphy_datar_datar_run + connect \Y $or$ls180.v:8275$2614_Y + end + attribute \src "ls180.v:8281.8-8281.101" + cell $or $or$ls180.v:8281$2616 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:8281$2615_Y + connect \B \main_sdphy_datar_datar_converter_sink_last + connect \Y $or$ls180.v:8281$2616_Y + end + attribute \src "ls180.v:8298.54-8298.145" + cell $or $or$ls180.v:8298$2621 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_datar_converter_sink_first + connect \B \main_sdphy_datar_datar_converter_source_first + connect \Y $or$ls180.v:8298$2621_Y + end + attribute \src "ls180.v:8299.53-8299.142" + cell $or $or$ls180.v:8299$2622 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_datar_converter_sink_last + connect \B \main_sdphy_datar_datar_converter_source_last + connect \Y $or$ls180.v:8299$2622_Y + end + attribute \src "ls180.v:8315.7-8315.91" + cell $or $or$ls180.v:8315$2625 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:8315$2624_Y + connect \B \main_sdphy_datar_datar_buf_source_ready + connect \Y $or$ls180.v:8315$2625_Y + end + attribute \src "ls180.v:8504.8-8504.89" + cell $or $or$ls180.v:8504$2649 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:8504$2648_Y + connect \B \main_sdblock2mem_converter_sink_last + connect \Y $or$ls180.v:8504$2649_Y + end + attribute \src "ls180.v:8521.48-8521.127" + cell $or $or$ls180.v:8521$2654 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_converter_sink_first + connect \B \main_sdblock2mem_converter_source_first + connect \Y $or$ls180.v:8521$2654_Y + end + attribute \src "ls180.v:8522.47-8522.124" + cell $or $or$ls180.v:8522$2655 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_converter_sink_last + connect \B \main_sdblock2mem_converter_source_last + connect \Y $or$ls180.v:8522$2655_Y + end + attribute \src "ls180.v:8595.21-8595.65" + cell $or $or$ls180.v:8595$2673 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:8595$2671_Y + connect \B $not$ls180.v:8595$2672_Y + connect \Y $or$ls180.v:8595$2673_Y + end + attribute \src "ls180.v:3131.46-3131.94" + cell $sshl $sshl$ls180.v:3131$83 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 13 + connect \A \main_sdram_bankmachine0_auto_precharge + connect \B 4'1010 + connect \Y $sshl$ls180.v:3131$83_Y + end + attribute \src "ls180.v:3288.46-3288.94" + cell $sshl $sshl$ls180.v:3288$113 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 13 + connect \A \main_sdram_bankmachine1_auto_precharge + connect \B 4'1010 + connect \Y $sshl$ls180.v:3288$113_Y + end + attribute \src "ls180.v:3445.46-3445.94" + cell $sshl $sshl$ls180.v:3445$143 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 13 + connect \A \main_sdram_bankmachine2_auto_precharge + connect \B 4'1010 + connect \Y $sshl$ls180.v:3445$143_Y + end + attribute \src "ls180.v:3602.46-3602.94" + cell $sshl $sshl$ls180.v:3602$173 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 13 + connect \A \main_sdram_bankmachine3_auto_precharge + connect \B 4'1010 + connect \Y $sshl$ls180.v:3602$173_Y + end + attribute \src "ls180.v:3162.63-3162.122" + cell $sub $sub$ls180.v:3162$96 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_produce + connect \B 1'1 + connect \Y $sub$ls180.v:3162$96_Y + end + attribute \src "ls180.v:3319.63-3319.122" + cell $sub $sub$ls180.v:3319$126 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_produce + connect \B 1'1 + connect \Y $sub$ls180.v:3319$126_Y + end + attribute \src "ls180.v:3476.63-3476.122" + cell $sub $sub$ls180.v:3476$156 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_produce + connect \B 1'1 + connect \Y $sub$ls180.v:3476$156_Y + end + attribute \src "ls180.v:3633.63-3633.122" + cell $sub $sub$ls180.v:3633$186 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_produce + connect \B 1'1 + connect \Y $sub$ls180.v:3633$186_Y + end + attribute \src "ls180.v:4039.38-4039.75" + cell $sub $sub$ls180.v:4039$540 + parameter \A_SIGNED 0 + parameter \A_WIDTH 30 + parameter \B_SIGNED 0 + parameter \B_WIDTH 31 + parameter \Y_WIDTH 31 + connect \A \main_litedram_wb_adr + connect \B 31'1001000000000000000000000000000 + connect \Y $sub$ls180.v:4039$540_Y + end + attribute \src "ls180.v:4125.36-4125.68" + cell $sub $sub$ls180.v:4125$585 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_uart_tx_fifo_produce + connect \B 1'1 + connect \Y $sub$ls180.v:4125$585_Y + end + attribute \src "ls180.v:4155.36-4155.68" + cell $sub $sub$ls180.v:4155$596 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_uart_rx_fifo_produce + connect \B 1'1 + connect \Y $sub$ls180.v:4155$596_Y + end + attribute \src "ls180.v:4180.69-4180.110" + cell $sub $sub$ls180.v:4180$602 + parameter \A_SIGNED 0 + parameter \A_WIDTH 15 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 16 + connect \A \main_spi_master_clk_divider0 [15:1] + connect \B 1'1 + connect \Y $sub$ls180.v:4180$602_Y + end + attribute \src "ls180.v:4181.69-4181.104" + cell $sub $sub$ls180.v:4181$604 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 16 + connect \A \main_spi_master_clk_divider0 + connect \B 1'1 + connect \Y $sub$ls180.v:4181$604_Y + end + attribute \src "ls180.v:4208.36-4208.66" + cell $sub $sub$ls180.v:4208$608 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 8 + connect \A \main_spi_master_length0 + connect \B 1'1 + connect \Y $sub$ls180.v:4208$608_Y + end + attribute \src "ls180.v:4458.60-4458.90" + cell $sub $sub$ls180.v:4458$652 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_sdphy_cmdr_timeout + connect \B 1'1 + connect \Y $sub$ls180.v:4458$652_Y + end + attribute \src "ls180.v:4469.62-4469.104" + cell $sub $sub$ls180.v:4469$654 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 8 + connect \A \main_sdphy_cmdr_sink_payload_length + connect \B 1'1 + connect \Y $sub$ls180.v:4469$654_Y + end + attribute \src "ls180.v:4486.60-4486.90" + cell $sub $sub$ls180.v:4486$658 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_sdphy_cmdr_timeout + connect \B 1'1 + connect \Y $sub$ls180.v:4486$658_Y + end + attribute \src "ls180.v:4715.62-4715.93" + cell $sub $sub$ls180.v:4715$688 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_sdphy_datar_timeout + connect \B 1'1 + connect \Y $sub$ls180.v:4715$688_Y + end + attribute \src "ls180.v:4720.62-4720.93" + cell $sub $sub$ls180.v:4720$689 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_sdphy_datar_timeout + connect \B 1'1 + connect \Y $sub$ls180.v:4720$689_Y + end + attribute \src "ls180.v:4731.64-4731.122" + cell $sub $sub$ls180.v:4731$692 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 10 + connect \A $add$ls180.v:4731$691_Y + connect \B 1'1 + connect \Y $sub$ls180.v:4731$692_Y + end + attribute \src "ls180.v:4752.62-4752.93" + cell $sub $sub$ls180.v:4752$695 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_sdphy_datar_timeout + connect \B 1'1 + connect \Y $sub$ls180.v:4752$695_Y + end + attribute \src "ls180.v:5214.37-5214.75" + cell $sub $sub$ls180.v:5214$968 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_sdcore_block_count_storage + connect \B 1'1 + connect \Y $sub$ls180.v:5214$968_Y + end + attribute \src "ls180.v:5229.62-5229.100" + cell $sub $sub$ls180.v:5229$971 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_sdcore_block_count_storage + connect \B 1'1 + connect \Y $sub$ls180.v:5229$971_Y + end + attribute \src "ls180.v:5240.39-5240.77" + cell $sub $sub$ls180.v:5240$976 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_sdcore_block_count_storage + connect \B 1'1 + connect \Y $sub$ls180.v:5240$976_Y + end + attribute \src "ls180.v:5315.40-5315.76" + cell $sub $sub$ls180.v:5315$980 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 5 + connect \A \main_sdblock2mem_fifo_produce + connect \B 1'1 + connect \Y $sub$ls180.v:5315$980_Y + end + attribute \src "ls180.v:5364.56-5364.104" + cell $sub $sub$ls180.v:5364$994 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_sdblock2mem_wishbonedmawriter_length + connect \B 1'1 + connect \Y $sub$ls180.v:5364$994_Y + end + attribute \src "ls180.v:5454.71-5454.105" + cell $sub $sub$ls180.v:5454$1000 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_sdmem2block_dma_length + connect \B 1'1 + connect \Y $sub$ls180.v:5454$1000_Y + end + attribute \src "ls180.v:5523.40-5523.76" + cell $sub $sub$ls180.v:5523$1011 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 5 + connect \A \main_sdmem2block_fifo_produce + connect \B 1'1 + connect \Y $sub$ls180.v:5523$1011_Y + end + attribute \src "ls180.v:5542.61-5542.98" + cell $sub $sub$ls180.v:5542$1017 + parameter \A_SIGNED 0 + parameter \A_WIDTH 15 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 16 + connect \A \libresocsim_clk_divider0 [15:1] + connect \B 1'1 + connect \Y $sub$ls180.v:5542$1017_Y + end + attribute \src "ls180.v:5543.61-5543.92" + cell $sub $sub$ls180.v:5543$1019 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 16 + connect \A \libresocsim_clk_divider0 + connect \B 1'1 + connect \Y $sub$ls180.v:5543$1019_Y + end + attribute \src "ls180.v:5571.32-5571.58" + cell $sub $sub$ls180.v:5571$1023 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 8 + connect \A \libresocsim_length0 + connect \B 1'1 + connect \Y $sub$ls180.v:5571$1023_Y + end + attribute \src "ls180.v:7448.31-7448.60" + cell $sub $sub$ls180.v:7448$2410 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_libresocsim_value + connect \B 1'1 + connect \Y $sub$ls180.v:7448$2410_Y + end + attribute \src "ls180.v:7469.31-7469.61" + cell $sub $sub$ls180.v:7469$2415 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 10 + connect \A \main_sdram_timer_count1 + connect \B 1'1 + connect \Y $sub$ls180.v:7469$2415_Y + end + attribute \src "ls180.v:7475.34-7475.67" + cell $sub $sub$ls180.v:7475$2416 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_postponer_count + connect \B 1'1 + connect \Y $sub$ls180.v:7475$2416_Y + end + attribute \src "ls180.v:7486.36-7486.69" + cell $sub $sub$ls180.v:7486$2419 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_sequencer_count + connect \B 1'1 + connect \Y $sub$ls180.v:7486$2419_Y + end + attribute \src "ls180.v:7550.59-7550.116" + cell $sub $sub$ls180.v:7550$2437 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_level + connect \B 1'1 + connect \Y $sub$ls180.v:7550$2437_Y + end + attribute \src "ls180.v:7569.46-7569.90" + cell $sub $sub$ls180.v:7569$2441 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine0_twtpcon_count + connect \B 1'1 + connect \Y $sub$ls180.v:7569$2441_Y + end + attribute \src "ls180.v:7596.59-7596.116" + cell $sub $sub$ls180.v:7596$2453 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_level + connect \B 1'1 + connect \Y $sub$ls180.v:7596$2453_Y + end + attribute \src "ls180.v:7615.46-7615.90" + cell $sub $sub$ls180.v:7615$2457 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine1_twtpcon_count + connect \B 1'1 + connect \Y $sub$ls180.v:7615$2457_Y + end + attribute \src "ls180.v:7642.59-7642.116" + cell $sub $sub$ls180.v:7642$2469 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_level + connect \B 1'1 + connect \Y $sub$ls180.v:7642$2469_Y + end + attribute \src "ls180.v:7661.46-7661.90" + cell $sub $sub$ls180.v:7661$2473 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine2_twtpcon_count + connect \B 1'1 + connect \Y $sub$ls180.v:7661$2473_Y + end + attribute \src "ls180.v:7688.59-7688.116" + cell $sub $sub$ls180.v:7688$2485 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_level + connect \B 1'1 + connect \Y $sub$ls180.v:7688$2485_Y + end + attribute \src "ls180.v:7707.46-7707.90" + cell $sub $sub$ls180.v:7707$2489 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine3_twtpcon_count + connect \B 1'1 + connect \Y $sub$ls180.v:7707$2489_Y + end + attribute \src "ls180.v:7718.25-7718.48" + cell $sub $sub$ls180.v:7718$2493 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 5 + connect \A \main_sdram_time0 + connect \B 1'1 + connect \Y $sub$ls180.v:7718$2493_Y + end + attribute \src "ls180.v:7725.25-7725.48" + cell $sub $sub$ls180.v:7725$2496 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_sdram_time1 + connect \B 1'1 + connect \Y $sub$ls180.v:7725$2496_Y + end + attribute \src "ls180.v:7857.33-7857.64" + cell $sub $sub$ls180.v:7857$2501 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_tccdcon_count + connect \B 1'1 + connect \Y $sub$ls180.v:7857$2501_Y + end + attribute \src "ls180.v:7872.33-7872.64" + cell $sub $sub$ls180.v:7872$2504 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_twtrcon_count + connect \B 1'1 + connect \Y $sub$ls180.v:7872$2504_Y + end + attribute \src "ls180.v:7999.33-7999.64" + cell $sub $sub$ls180.v:7999$2563 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 5 + connect \A \main_uart_tx_fifo_level0 + connect \B 1'1 + connect \Y $sub$ls180.v:7999$2563_Y + end + attribute \src "ls180.v:8021.33-8021.64" + cell $sub $sub$ls180.v:8021$2574 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 5 + connect \A \main_uart_rx_fifo_level0 + connect \B 1'1 + connect \Y $sub$ls180.v:8021$2574_Y + end + attribute \src "ls180.v:8056.33-8056.64" + cell $sub $sub$ls180.v:8056$2579 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_spi_master_mosi_sel + connect \B 1'1 + connect \Y $sub$ls180.v:8056$2579_Y + end + attribute \src "ls180.v:8080.30-8080.53" + cell $sub $sub$ls180.v:8080$2582 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_pwm0_period + connect \B 1'1 + connect \Y $sub$ls180.v:8080$2582_Y + end + attribute \src "ls180.v:8094.30-8094.53" + cell $sub $sub$ls180.v:8094$2586 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_pwm1_period + connect \B 1'1 + connect \Y $sub$ls180.v:8094$2586_Y + end + attribute \src "ls180.v:8497.36-8497.70" + cell $sub $sub$ls180.v:8497$2647 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 6 + connect \A \main_sdblock2mem_fifo_level + connect \B 1'1 + connect \Y $sub$ls180.v:8497$2647_Y + end + attribute \src "ls180.v:8583.36-8583.70" + cell $sub $sub$ls180.v:8583$2669 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 6 + connect \A \main_sdmem2block_fifo_level + connect \B 1'1 + connect \Y $sub$ls180.v:8583$2669_Y + end + attribute \src "ls180.v:8604.29-8604.56" + cell $sub $sub$ls180.v:8604$2674 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \libresocsim_mosi_sel + connect \B 1'1 + connect \Y $sub$ls180.v:8604$2674_Y + end + attribute \src "ls180.v:8731.22-8731.42" + cell $sub $sub$ls180.v:8731$2681 + parameter \A_SIGNED 0 + parameter \A_WIDTH 20 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 20 + connect \A \builder_count + connect \B 1'1 + connect \Y $sub$ls180.v:8731$2681_Y + end + attribute \src "ls180.v:4812.353-4812.425" + cell $xor $xor$ls180.v:4812$702 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [39] + connect \B \main_sdcore_crc7_inserter_crcreg0 [6] + connect \Y $xor$ls180.v:4812$702_Y + end + attribute \src "ls180.v:4812.200-4812.272" + cell $xor $xor$ls180.v:4812$703 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [39] + connect \B \main_sdcore_crc7_inserter_crcreg0 [6] + connect \Y $xor$ls180.v:4812$703_Y + end + attribute \src "ls180.v:4812.160-4812.273" + cell $xor $xor$ls180.v:4812$704 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg0 [2] + connect \B $xor$ls180.v:4812$703_Y + connect \Y $xor$ls180.v:4812$704_Y + end + attribute \src "ls180.v:4813.353-4813.425" + cell $xor $xor$ls180.v:4813$705 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [38] + connect \B \main_sdcore_crc7_inserter_crcreg1 [6] + connect \Y $xor$ls180.v:4813$705_Y + end + attribute \src "ls180.v:4813.200-4813.272" + cell $xor $xor$ls180.v:4813$706 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [38] + connect \B \main_sdcore_crc7_inserter_crcreg1 [6] + connect \Y $xor$ls180.v:4813$706_Y + end + attribute \src "ls180.v:4813.160-4813.273" + cell $xor $xor$ls180.v:4813$707 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg1 [2] + connect \B $xor$ls180.v:4813$706_Y + connect \Y $xor$ls180.v:4813$707_Y + end + attribute \src "ls180.v:4814.353-4814.425" + cell $xor $xor$ls180.v:4814$708 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [37] + connect \B \main_sdcore_crc7_inserter_crcreg2 [6] + connect \Y $xor$ls180.v:4814$708_Y + end + attribute \src "ls180.v:4814.200-4814.272" + cell $xor $xor$ls180.v:4814$709 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [37] + connect \B \main_sdcore_crc7_inserter_crcreg2 [6] + connect \Y $xor$ls180.v:4814$709_Y + end + attribute \src "ls180.v:4814.160-4814.273" + cell $xor $xor$ls180.v:4814$710 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg2 [2] + connect \B $xor$ls180.v:4814$709_Y + connect \Y $xor$ls180.v:4814$710_Y + end + attribute \src "ls180.v:4815.353-4815.425" + cell $xor $xor$ls180.v:4815$711 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [36] + connect \B \main_sdcore_crc7_inserter_crcreg3 [6] + connect \Y $xor$ls180.v:4815$711_Y + end + attribute \src "ls180.v:4815.200-4815.272" + cell $xor $xor$ls180.v:4815$712 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [36] + connect \B \main_sdcore_crc7_inserter_crcreg3 [6] + connect \Y $xor$ls180.v:4815$712_Y + end + attribute \src "ls180.v:4815.160-4815.273" + cell $xor $xor$ls180.v:4815$713 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg3 [2] + connect \B $xor$ls180.v:4815$712_Y + connect \Y $xor$ls180.v:4815$713_Y + end + attribute \src "ls180.v:4816.353-4816.425" + cell $xor $xor$ls180.v:4816$714 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [35] + connect \B \main_sdcore_crc7_inserter_crcreg4 [6] + connect \Y $xor$ls180.v:4816$714_Y + end + attribute \src "ls180.v:4816.200-4816.272" + cell $xor $xor$ls180.v:4816$715 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [35] + connect \B \main_sdcore_crc7_inserter_crcreg4 [6] + connect \Y $xor$ls180.v:4816$715_Y + end + attribute \src "ls180.v:4816.160-4816.273" + cell $xor $xor$ls180.v:4816$716 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg4 [2] + connect \B $xor$ls180.v:4816$715_Y + connect \Y $xor$ls180.v:4816$716_Y + end + attribute \src "ls180.v:4817.353-4817.425" + cell $xor $xor$ls180.v:4817$717 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [34] + connect \B \main_sdcore_crc7_inserter_crcreg5 [6] + connect \Y $xor$ls180.v:4817$717_Y + end + attribute \src "ls180.v:4817.200-4817.272" + cell $xor $xor$ls180.v:4817$718 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [34] + connect \B \main_sdcore_crc7_inserter_crcreg5 [6] + connect \Y $xor$ls180.v:4817$718_Y + end + attribute \src "ls180.v:4817.160-4817.273" + cell $xor $xor$ls180.v:4817$719 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg5 [2] + connect \B $xor$ls180.v:4817$718_Y + connect \Y $xor$ls180.v:4817$719_Y + end + attribute \src "ls180.v:4818.353-4818.425" + cell $xor $xor$ls180.v:4818$720 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [33] + connect \B \main_sdcore_crc7_inserter_crcreg6 [6] + connect \Y $xor$ls180.v:4818$720_Y + end + attribute \src "ls180.v:4818.200-4818.272" + cell $xor $xor$ls180.v:4818$721 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [33] + connect \B \main_sdcore_crc7_inserter_crcreg6 [6] + connect \Y $xor$ls180.v:4818$721_Y + end + attribute \src "ls180.v:4818.160-4818.273" + cell $xor $xor$ls180.v:4818$722 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg6 [2] + connect \B $xor$ls180.v:4818$721_Y + connect \Y $xor$ls180.v:4818$722_Y + end + attribute \src "ls180.v:4819.353-4819.425" + cell $xor $xor$ls180.v:4819$723 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [32] + connect \B \main_sdcore_crc7_inserter_crcreg7 [6] + connect \Y $xor$ls180.v:4819$723_Y + end + attribute \src "ls180.v:4819.200-4819.272" + cell $xor $xor$ls180.v:4819$724 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [32] + connect \B \main_sdcore_crc7_inserter_crcreg7 [6] + connect \Y $xor$ls180.v:4819$724_Y + end + attribute \src "ls180.v:4819.160-4819.273" + cell $xor $xor$ls180.v:4819$725 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg7 [2] + connect \B $xor$ls180.v:4819$724_Y + connect \Y $xor$ls180.v:4819$725_Y + end + attribute \src "ls180.v:4820.353-4820.425" + cell $xor $xor$ls180.v:4820$726 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [31] + connect \B \main_sdcore_crc7_inserter_crcreg8 [6] + connect \Y $xor$ls180.v:4820$726_Y + end + attribute \src "ls180.v:4820.200-4820.272" + cell $xor $xor$ls180.v:4820$727 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [31] + connect \B \main_sdcore_crc7_inserter_crcreg8 [6] + connect \Y $xor$ls180.v:4820$727_Y + end + attribute \src "ls180.v:4820.160-4820.273" + cell $xor $xor$ls180.v:4820$728 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg8 [2] + connect \B $xor$ls180.v:4820$727_Y + connect \Y $xor$ls180.v:4820$728_Y + end + attribute \src "ls180.v:4821.354-4821.426" + cell $xor $xor$ls180.v:4821$729 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [30] + connect \B \main_sdcore_crc7_inserter_crcreg9 [6] + connect \Y $xor$ls180.v:4821$729_Y + end + attribute \src "ls180.v:4821.201-4821.273" + cell $xor $xor$ls180.v:4821$730 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [30] + connect \B \main_sdcore_crc7_inserter_crcreg9 [6] + connect \Y $xor$ls180.v:4821$730_Y + end + attribute \src "ls180.v:4821.161-4821.274" + cell $xor $xor$ls180.v:4821$731 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg9 [2] + connect \B $xor$ls180.v:4821$730_Y + connect \Y $xor$ls180.v:4821$731_Y + end + attribute \src "ls180.v:4822.361-4822.434" + cell $xor $xor$ls180.v:4822$732 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [29] + connect \B \main_sdcore_crc7_inserter_crcreg10 [6] + connect \Y $xor$ls180.v:4822$732_Y + end + attribute \src "ls180.v:4822.205-4822.278" + cell $xor $xor$ls180.v:4822$733 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [29] + connect \B \main_sdcore_crc7_inserter_crcreg10 [6] + connect \Y $xor$ls180.v:4822$733_Y + end + attribute \src "ls180.v:4822.164-4822.279" + cell $xor $xor$ls180.v:4822$734 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg10 [2] + connect \B $xor$ls180.v:4822$733_Y + connect \Y $xor$ls180.v:4822$734_Y + end + attribute \src "ls180.v:4823.361-4823.434" + cell $xor $xor$ls180.v:4823$735 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [28] + connect \B \main_sdcore_crc7_inserter_crcreg11 [6] + connect \Y $xor$ls180.v:4823$735_Y + end + attribute \src "ls180.v:4823.205-4823.278" + cell $xor $xor$ls180.v:4823$736 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [28] + connect \B \main_sdcore_crc7_inserter_crcreg11 [6] + connect \Y $xor$ls180.v:4823$736_Y + end + attribute \src "ls180.v:4823.164-4823.279" + cell $xor $xor$ls180.v:4823$737 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg11 [2] + connect \B $xor$ls180.v:4823$736_Y + connect \Y $xor$ls180.v:4823$737_Y + end + attribute \src "ls180.v:4824.361-4824.434" + cell $xor $xor$ls180.v:4824$738 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [27] + connect \B \main_sdcore_crc7_inserter_crcreg12 [6] + connect \Y $xor$ls180.v:4824$738_Y + end + attribute \src "ls180.v:4824.205-4824.278" + cell $xor $xor$ls180.v:4824$739 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [27] + connect \B \main_sdcore_crc7_inserter_crcreg12 [6] + connect \Y $xor$ls180.v:4824$739_Y + end + attribute \src "ls180.v:4824.164-4824.279" + cell $xor $xor$ls180.v:4824$740 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg12 [2] + connect \B $xor$ls180.v:4824$739_Y + connect \Y $xor$ls180.v:4824$740_Y + end + attribute \src "ls180.v:4825.361-4825.434" + cell $xor $xor$ls180.v:4825$741 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [26] + connect \B \main_sdcore_crc7_inserter_crcreg13 [6] + connect \Y $xor$ls180.v:4825$741_Y + end + attribute \src "ls180.v:4825.205-4825.278" + cell $xor $xor$ls180.v:4825$742 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [26] + connect \B \main_sdcore_crc7_inserter_crcreg13 [6] + connect \Y $xor$ls180.v:4825$742_Y + end + attribute \src "ls180.v:4825.164-4825.279" + cell $xor $xor$ls180.v:4825$743 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg13 [2] + connect \B $xor$ls180.v:4825$742_Y + connect \Y $xor$ls180.v:4825$743_Y + end + attribute \src "ls180.v:4826.361-4826.434" + cell $xor $xor$ls180.v:4826$744 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [25] + connect \B \main_sdcore_crc7_inserter_crcreg14 [6] + connect \Y $xor$ls180.v:4826$744_Y + end + attribute \src "ls180.v:4826.205-4826.278" + cell $xor $xor$ls180.v:4826$745 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [25] + connect \B \main_sdcore_crc7_inserter_crcreg14 [6] + connect \Y $xor$ls180.v:4826$745_Y + end + attribute \src "ls180.v:4826.164-4826.279" + cell $xor $xor$ls180.v:4826$746 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg14 [2] + connect \B $xor$ls180.v:4826$745_Y + connect \Y $xor$ls180.v:4826$746_Y + end + attribute \src "ls180.v:4827.361-4827.434" + cell $xor $xor$ls180.v:4827$747 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [24] + connect \B \main_sdcore_crc7_inserter_crcreg15 [6] + connect \Y $xor$ls180.v:4827$747_Y + end + attribute \src "ls180.v:4827.205-4827.278" + cell $xor $xor$ls180.v:4827$748 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [24] + connect \B \main_sdcore_crc7_inserter_crcreg15 [6] + connect \Y $xor$ls180.v:4827$748_Y + end + attribute \src "ls180.v:4827.164-4827.279" + cell $xor $xor$ls180.v:4827$749 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg15 [2] + connect \B $xor$ls180.v:4827$748_Y + connect \Y $xor$ls180.v:4827$749_Y + end + attribute \src "ls180.v:4828.361-4828.434" + cell $xor $xor$ls180.v:4828$750 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [23] + connect \B \main_sdcore_crc7_inserter_crcreg16 [6] + connect \Y $xor$ls180.v:4828$750_Y + end + attribute \src "ls180.v:4828.205-4828.278" + cell $xor $xor$ls180.v:4828$751 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [23] + connect \B \main_sdcore_crc7_inserter_crcreg16 [6] + connect \Y $xor$ls180.v:4828$751_Y + end + attribute \src "ls180.v:4828.164-4828.279" + cell $xor $xor$ls180.v:4828$752 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg16 [2] + connect \B $xor$ls180.v:4828$751_Y + connect \Y $xor$ls180.v:4828$752_Y + end + attribute \src "ls180.v:4829.361-4829.434" + cell $xor $xor$ls180.v:4829$753 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [22] + connect \B \main_sdcore_crc7_inserter_crcreg17 [6] + connect \Y $xor$ls180.v:4829$753_Y + end + attribute \src "ls180.v:4829.205-4829.278" + cell $xor $xor$ls180.v:4829$754 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [22] + connect \B \main_sdcore_crc7_inserter_crcreg17 [6] + connect \Y $xor$ls180.v:4829$754_Y + end + attribute \src "ls180.v:4829.164-4829.279" + cell $xor $xor$ls180.v:4829$755 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg17 [2] + connect \B $xor$ls180.v:4829$754_Y + connect \Y $xor$ls180.v:4829$755_Y + end + attribute \src "ls180.v:4830.361-4830.434" + cell $xor $xor$ls180.v:4830$756 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [21] + connect \B \main_sdcore_crc7_inserter_crcreg18 [6] + connect \Y $xor$ls180.v:4830$756_Y + end + attribute \src "ls180.v:4830.205-4830.278" + cell $xor $xor$ls180.v:4830$757 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [21] + connect \B \main_sdcore_crc7_inserter_crcreg18 [6] + connect \Y $xor$ls180.v:4830$757_Y + end + attribute \src "ls180.v:4830.164-4830.279" + cell $xor $xor$ls180.v:4830$758 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg18 [2] + connect \B $xor$ls180.v:4830$757_Y + connect \Y $xor$ls180.v:4830$758_Y + end + attribute \src "ls180.v:4831.361-4831.434" + cell $xor $xor$ls180.v:4831$759 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [20] + connect \B \main_sdcore_crc7_inserter_crcreg19 [6] + connect \Y $xor$ls180.v:4831$759_Y + end + attribute \src "ls180.v:4831.205-4831.278" + cell $xor $xor$ls180.v:4831$760 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [20] + connect \B \main_sdcore_crc7_inserter_crcreg19 [6] + connect \Y $xor$ls180.v:4831$760_Y + end + attribute \src "ls180.v:4831.164-4831.279" + cell $xor $xor$ls180.v:4831$761 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg19 [2] + connect \B $xor$ls180.v:4831$760_Y + connect \Y $xor$ls180.v:4831$761_Y + end + attribute \src "ls180.v:4832.361-4832.434" + cell $xor $xor$ls180.v:4832$762 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [19] + connect \B \main_sdcore_crc7_inserter_crcreg20 [6] + connect \Y $xor$ls180.v:4832$762_Y + end + attribute \src "ls180.v:4832.205-4832.278" + cell $xor $xor$ls180.v:4832$763 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [19] + connect \B \main_sdcore_crc7_inserter_crcreg20 [6] + connect \Y $xor$ls180.v:4832$763_Y + end + attribute \src "ls180.v:4832.164-4832.279" + cell $xor $xor$ls180.v:4832$764 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg20 [2] + connect \B $xor$ls180.v:4832$763_Y + connect \Y $xor$ls180.v:4832$764_Y + end + attribute \src "ls180.v:4833.361-4833.434" + cell $xor $xor$ls180.v:4833$765 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [18] + connect \B \main_sdcore_crc7_inserter_crcreg21 [6] + connect \Y $xor$ls180.v:4833$765_Y + end + attribute \src "ls180.v:4833.205-4833.278" + cell $xor $xor$ls180.v:4833$766 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [18] + connect \B \main_sdcore_crc7_inserter_crcreg21 [6] + connect \Y $xor$ls180.v:4833$766_Y + end + attribute \src "ls180.v:4833.164-4833.279" + cell $xor $xor$ls180.v:4833$767 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg21 [2] + connect \B $xor$ls180.v:4833$766_Y + connect \Y $xor$ls180.v:4833$767_Y + end + attribute \src "ls180.v:4834.361-4834.434" + cell $xor $xor$ls180.v:4834$768 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [17] + connect \B \main_sdcore_crc7_inserter_crcreg22 [6] + connect \Y $xor$ls180.v:4834$768_Y + end + attribute \src "ls180.v:4834.205-4834.278" + cell $xor $xor$ls180.v:4834$769 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [17] + connect \B \main_sdcore_crc7_inserter_crcreg22 [6] + connect \Y $xor$ls180.v:4834$769_Y + end + attribute \src "ls180.v:4834.164-4834.279" + cell $xor $xor$ls180.v:4834$770 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg22 [2] + connect \B $xor$ls180.v:4834$769_Y + connect \Y $xor$ls180.v:4834$770_Y + end + attribute \src "ls180.v:4835.361-4835.434" + cell $xor $xor$ls180.v:4835$771 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [16] + connect \B \main_sdcore_crc7_inserter_crcreg23 [6] + connect \Y $xor$ls180.v:4835$771_Y + end + attribute \src "ls180.v:4835.205-4835.278" + cell $xor $xor$ls180.v:4835$772 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [16] + connect \B \main_sdcore_crc7_inserter_crcreg23 [6] + connect \Y $xor$ls180.v:4835$772_Y + end + attribute \src "ls180.v:4835.164-4835.279" + cell $xor $xor$ls180.v:4835$773 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg23 [2] + connect \B $xor$ls180.v:4835$772_Y + connect \Y $xor$ls180.v:4835$773_Y + end + attribute \src "ls180.v:4836.361-4836.434" + cell $xor $xor$ls180.v:4836$774 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [15] + connect \B \main_sdcore_crc7_inserter_crcreg24 [6] + connect \Y $xor$ls180.v:4836$774_Y + end + attribute \src "ls180.v:4836.205-4836.278" + cell $xor $xor$ls180.v:4836$775 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [15] + connect \B \main_sdcore_crc7_inserter_crcreg24 [6] + connect \Y $xor$ls180.v:4836$775_Y + end + attribute \src "ls180.v:4836.164-4836.279" + cell $xor $xor$ls180.v:4836$776 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg24 [2] + connect \B $xor$ls180.v:4836$775_Y + connect \Y $xor$ls180.v:4836$776_Y + end + attribute \src "ls180.v:4837.361-4837.434" + cell $xor $xor$ls180.v:4837$777 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [14] + connect \B \main_sdcore_crc7_inserter_crcreg25 [6] + connect \Y $xor$ls180.v:4837$777_Y + end + attribute \src "ls180.v:4837.205-4837.278" + cell $xor $xor$ls180.v:4837$778 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [14] + connect \B \main_sdcore_crc7_inserter_crcreg25 [6] + connect \Y $xor$ls180.v:4837$778_Y + end + attribute \src "ls180.v:4837.164-4837.279" + cell $xor $xor$ls180.v:4837$779 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg25 [2] + connect \B $xor$ls180.v:4837$778_Y + connect \Y $xor$ls180.v:4837$779_Y + end + attribute \src "ls180.v:4838.361-4838.434" + cell $xor $xor$ls180.v:4838$780 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [13] + connect \B \main_sdcore_crc7_inserter_crcreg26 [6] + connect \Y $xor$ls180.v:4838$780_Y + end + attribute \src "ls180.v:4838.205-4838.278" + cell $xor $xor$ls180.v:4838$781 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [13] + connect \B \main_sdcore_crc7_inserter_crcreg26 [6] + connect \Y $xor$ls180.v:4838$781_Y + end + attribute \src "ls180.v:4838.164-4838.279" + cell $xor $xor$ls180.v:4838$782 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg26 [2] + connect \B $xor$ls180.v:4838$781_Y + connect \Y $xor$ls180.v:4838$782_Y + end + attribute \src "ls180.v:4839.361-4839.434" + cell $xor $xor$ls180.v:4839$783 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [12] + connect \B \main_sdcore_crc7_inserter_crcreg27 [6] + connect \Y $xor$ls180.v:4839$783_Y + end + attribute \src "ls180.v:4839.205-4839.278" + cell $xor $xor$ls180.v:4839$784 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [12] + connect \B \main_sdcore_crc7_inserter_crcreg27 [6] + connect \Y $xor$ls180.v:4839$784_Y + end + attribute \src "ls180.v:4839.164-4839.279" + cell $xor $xor$ls180.v:4839$785 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg27 [2] + connect \B $xor$ls180.v:4839$784_Y + connect \Y $xor$ls180.v:4839$785_Y + end + attribute \src "ls180.v:4840.361-4840.434" + cell $xor $xor$ls180.v:4840$786 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [11] + connect \B \main_sdcore_crc7_inserter_crcreg28 [6] + connect \Y $xor$ls180.v:4840$786_Y + end + attribute \src "ls180.v:4840.205-4840.278" + cell $xor $xor$ls180.v:4840$787 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [11] + connect \B \main_sdcore_crc7_inserter_crcreg28 [6] + connect \Y $xor$ls180.v:4840$787_Y + end + attribute \src "ls180.v:4840.164-4840.279" + cell $xor $xor$ls180.v:4840$788 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg28 [2] + connect \B $xor$ls180.v:4840$787_Y + connect \Y $xor$ls180.v:4840$788_Y + end + attribute \src "ls180.v:4841.361-4841.434" + cell $xor $xor$ls180.v:4841$789 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [10] + connect \B \main_sdcore_crc7_inserter_crcreg29 [6] + connect \Y $xor$ls180.v:4841$789_Y + end + attribute \src "ls180.v:4841.205-4841.278" + cell $xor $xor$ls180.v:4841$790 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [10] + connect \B \main_sdcore_crc7_inserter_crcreg29 [6] + connect \Y $xor$ls180.v:4841$790_Y + end + attribute \src "ls180.v:4841.164-4841.279" + cell $xor $xor$ls180.v:4841$791 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg29 [2] + connect \B $xor$ls180.v:4841$790_Y + connect \Y $xor$ls180.v:4841$791_Y + end + attribute \src "ls180.v:4842.360-4842.432" + cell $xor $xor$ls180.v:4842$792 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [9] + connect \B \main_sdcore_crc7_inserter_crcreg30 [6] + connect \Y $xor$ls180.v:4842$792_Y + end + attribute \src "ls180.v:4842.205-4842.277" + cell $xor $xor$ls180.v:4842$793 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [9] + connect \B \main_sdcore_crc7_inserter_crcreg30 [6] + connect \Y $xor$ls180.v:4842$793_Y + end + attribute \src "ls180.v:4842.164-4842.278" + cell $xor $xor$ls180.v:4842$794 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg30 [2] + connect \B $xor$ls180.v:4842$793_Y + connect \Y $xor$ls180.v:4842$794_Y + end + attribute \src "ls180.v:4843.360-4843.432" + cell $xor $xor$ls180.v:4843$795 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [8] + connect \B \main_sdcore_crc7_inserter_crcreg31 [6] + connect \Y $xor$ls180.v:4843$795_Y + end + attribute \src "ls180.v:4843.205-4843.277" + cell $xor $xor$ls180.v:4843$796 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [8] + connect \B \main_sdcore_crc7_inserter_crcreg31 [6] + connect \Y $xor$ls180.v:4843$796_Y + end + attribute \src "ls180.v:4843.164-4843.278" + cell $xor $xor$ls180.v:4843$797 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg31 [2] + connect \B $xor$ls180.v:4843$796_Y + connect \Y $xor$ls180.v:4843$797_Y + end + attribute \src "ls180.v:4844.360-4844.432" + cell $xor $xor$ls180.v:4844$798 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [7] + connect \B \main_sdcore_crc7_inserter_crcreg32 [6] + connect \Y $xor$ls180.v:4844$798_Y + end + attribute \src "ls180.v:4844.205-4844.277" + cell $xor $xor$ls180.v:4844$799 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [7] + connect \B \main_sdcore_crc7_inserter_crcreg32 [6] + connect \Y $xor$ls180.v:4844$799_Y + end + attribute \src "ls180.v:4844.164-4844.278" + cell $xor $xor$ls180.v:4844$800 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg32 [2] + connect \B $xor$ls180.v:4844$799_Y + connect \Y $xor$ls180.v:4844$800_Y + end + attribute \src "ls180.v:4845.360-4845.432" + cell $xor $xor$ls180.v:4845$801 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [6] + connect \B \main_sdcore_crc7_inserter_crcreg33 [6] + connect \Y $xor$ls180.v:4845$801_Y + end + attribute \src "ls180.v:4845.205-4845.277" + cell $xor $xor$ls180.v:4845$802 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [6] + connect \B \main_sdcore_crc7_inserter_crcreg33 [6] + connect \Y $xor$ls180.v:4845$802_Y + end + attribute \src "ls180.v:4845.164-4845.278" + cell $xor $xor$ls180.v:4845$803 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg33 [2] + connect \B $xor$ls180.v:4845$802_Y + connect \Y $xor$ls180.v:4845$803_Y + end + attribute \src "ls180.v:4846.360-4846.432" + cell $xor $xor$ls180.v:4846$804 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [5] + connect \B \main_sdcore_crc7_inserter_crcreg34 [6] + connect \Y $xor$ls180.v:4846$804_Y + end + attribute \src "ls180.v:4846.205-4846.277" + cell $xor $xor$ls180.v:4846$805 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [5] + connect \B \main_sdcore_crc7_inserter_crcreg34 [6] + connect \Y $xor$ls180.v:4846$805_Y + end + attribute \src "ls180.v:4846.164-4846.278" + cell $xor $xor$ls180.v:4846$806 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg34 [2] + connect \B $xor$ls180.v:4846$805_Y + connect \Y $xor$ls180.v:4846$806_Y + end + attribute \src "ls180.v:4847.360-4847.432" + cell $xor $xor$ls180.v:4847$807 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [4] + connect \B \main_sdcore_crc7_inserter_crcreg35 [6] + connect \Y $xor$ls180.v:4847$807_Y + end + attribute \src "ls180.v:4847.205-4847.277" + cell $xor $xor$ls180.v:4847$808 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [4] + connect \B \main_sdcore_crc7_inserter_crcreg35 [6] + connect \Y $xor$ls180.v:4847$808_Y + end + attribute \src "ls180.v:4847.164-4847.278" + cell $xor $xor$ls180.v:4847$809 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg35 [2] + connect \B $xor$ls180.v:4847$808_Y + connect \Y $xor$ls180.v:4847$809_Y + end + attribute \src "ls180.v:4848.360-4848.432" + cell $xor $xor$ls180.v:4848$810 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [3] + connect \B \main_sdcore_crc7_inserter_crcreg36 [6] + connect \Y $xor$ls180.v:4848$810_Y + end + attribute \src "ls180.v:4848.205-4848.277" + cell $xor $xor$ls180.v:4848$811 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [3] + connect \B \main_sdcore_crc7_inserter_crcreg36 [6] + connect \Y $xor$ls180.v:4848$811_Y + end + attribute \src "ls180.v:4848.164-4848.278" + cell $xor $xor$ls180.v:4848$812 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg36 [2] + connect \B $xor$ls180.v:4848$811_Y + connect \Y $xor$ls180.v:4848$812_Y + end + attribute \src "ls180.v:4849.360-4849.432" + cell $xor $xor$ls180.v:4849$813 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [2] + connect \B \main_sdcore_crc7_inserter_crcreg37 [6] + connect \Y $xor$ls180.v:4849$813_Y + end + attribute \src "ls180.v:4849.205-4849.277" + cell $xor $xor$ls180.v:4849$814 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [2] + connect \B \main_sdcore_crc7_inserter_crcreg37 [6] + connect \Y $xor$ls180.v:4849$814_Y + end + attribute \src "ls180.v:4849.164-4849.278" + cell $xor $xor$ls180.v:4849$815 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg37 [2] + connect \B $xor$ls180.v:4849$814_Y + connect \Y $xor$ls180.v:4849$815_Y + end + attribute \src "ls180.v:4850.360-4850.432" + cell $xor $xor$ls180.v:4850$816 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [1] + connect \B \main_sdcore_crc7_inserter_crcreg38 [6] + connect \Y $xor$ls180.v:4850$816_Y + end + attribute \src "ls180.v:4850.205-4850.277" + cell $xor $xor$ls180.v:4850$817 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [1] + connect \B \main_sdcore_crc7_inserter_crcreg38 [6] + connect \Y $xor$ls180.v:4850$817_Y + end + attribute \src "ls180.v:4850.164-4850.278" + cell $xor $xor$ls180.v:4850$818 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg38 [2] + connect \B $xor$ls180.v:4850$817_Y + connect \Y $xor$ls180.v:4850$818_Y + end + attribute \src "ls180.v:4851.360-4851.432" + cell $xor $xor$ls180.v:4851$819 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [0] + connect \B \main_sdcore_crc7_inserter_crcreg39 [6] + connect \Y $xor$ls180.v:4851$819_Y + end + attribute \src "ls180.v:4851.205-4851.277" + cell $xor $xor$ls180.v:4851$820 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [0] + connect \B \main_sdcore_crc7_inserter_crcreg39 [6] + connect \Y $xor$ls180.v:4851$820_Y + end + attribute \src "ls180.v:4851.164-4851.278" + cell $xor $xor$ls180.v:4851$821 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg39 [2] + connect \B $xor$ls180.v:4851$820_Y + connect \Y $xor$ls180.v:4851$821_Y + end + attribute \src "ls180.v:4872.899-4872.983" + cell $xor $xor$ls180.v:4872$835 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc0_val [1] + connect \B \main_sdcore_crc16_inserter_crc0_crcreg0 [15] + connect \Y $xor$ls180.v:4872$835_Y + end + attribute \src "ls180.v:4872.634-4872.718" + cell $xor $xor$ls180.v:4872$836 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc0_val [1] + connect \B \main_sdcore_crc16_inserter_crc0_crcreg0 [15] + connect \Y $xor$ls180.v:4872$836_Y + end + attribute \src "ls180.v:4872.588-4872.719" + cell $xor $xor$ls180.v:4872$837 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc0_crcreg0 [4] + connect \B $xor$ls180.v:4872$836_Y + connect \Y $xor$ls180.v:4872$837_Y + end + attribute \src "ls180.v:4872.234-4872.318" + cell $xor $xor$ls180.v:4872$838 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc0_val [1] + connect \B \main_sdcore_crc16_inserter_crc0_crcreg0 [15] + connect \Y $xor$ls180.v:4872$838_Y + end + attribute \src "ls180.v:4872.187-4872.319" + cell $xor $xor$ls180.v:4872$839 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc0_crcreg0 [11] + connect \B $xor$ls180.v:4872$838_Y + connect \Y $xor$ls180.v:4872$839_Y + end + attribute \src "ls180.v:4873.899-4873.983" + cell $xor $xor$ls180.v:4873$840 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc0_val [0] + connect \B \main_sdcore_crc16_inserter_crc0_crcreg1 [15] + connect \Y $xor$ls180.v:4873$840_Y + end + attribute \src "ls180.v:4873.634-4873.718" + cell $xor $xor$ls180.v:4873$841 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc0_val [0] + connect \B \main_sdcore_crc16_inserter_crc0_crcreg1 [15] + connect \Y $xor$ls180.v:4873$841_Y + end + attribute \src "ls180.v:4873.588-4873.719" + cell $xor $xor$ls180.v:4873$842 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc0_crcreg1 [4] + connect \B $xor$ls180.v:4873$841_Y + connect \Y $xor$ls180.v:4873$842_Y + end + attribute \src "ls180.v:4873.234-4873.318" + cell $xor $xor$ls180.v:4873$843 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc0_val [0] + connect \B \main_sdcore_crc16_inserter_crc0_crcreg1 [15] + connect \Y $xor$ls180.v:4873$843_Y + end + attribute \src "ls180.v:4873.187-4873.319" + cell $xor $xor$ls180.v:4873$844 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc0_crcreg1 [11] + connect \B $xor$ls180.v:4873$843_Y + connect \Y $xor$ls180.v:4873$844_Y + end + attribute \src "ls180.v:4882.899-4882.983" + cell $xor $xor$ls180.v:4882$846 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc1_val [1] + connect \B \main_sdcore_crc16_inserter_crc1_crcreg0 [15] + connect \Y $xor$ls180.v:4882$846_Y + end + attribute \src "ls180.v:4882.634-4882.718" + cell $xor $xor$ls180.v:4882$847 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc1_val [1] + connect \B \main_sdcore_crc16_inserter_crc1_crcreg0 [15] + connect \Y $xor$ls180.v:4882$847_Y + end + attribute \src "ls180.v:4882.588-4882.719" + cell $xor $xor$ls180.v:4882$848 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc1_crcreg0 [4] + connect \B $xor$ls180.v:4882$847_Y + connect \Y $xor$ls180.v:4882$848_Y + end + attribute \src "ls180.v:4882.234-4882.318" + cell $xor $xor$ls180.v:4882$849 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc1_val [1] + connect \B \main_sdcore_crc16_inserter_crc1_crcreg0 [15] + connect \Y $xor$ls180.v:4882$849_Y + end + attribute \src "ls180.v:4882.187-4882.319" + cell $xor $xor$ls180.v:4882$850 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc1_crcreg0 [11] + connect \B $xor$ls180.v:4882$849_Y + connect \Y $xor$ls180.v:4882$850_Y + end + attribute \src "ls180.v:4883.899-4883.983" + cell $xor $xor$ls180.v:4883$851 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc1_val [0] + connect \B \main_sdcore_crc16_inserter_crc1_crcreg1 [15] + connect \Y $xor$ls180.v:4883$851_Y + end + attribute \src "ls180.v:4883.634-4883.718" + cell $xor $xor$ls180.v:4883$852 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc1_val [0] + connect \B \main_sdcore_crc16_inserter_crc1_crcreg1 [15] + connect \Y $xor$ls180.v:4883$852_Y + end + attribute \src "ls180.v:4883.588-4883.719" + cell $xor $xor$ls180.v:4883$853 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc1_crcreg1 [4] + connect \B $xor$ls180.v:4883$852_Y + connect \Y $xor$ls180.v:4883$853_Y + end + attribute \src "ls180.v:4883.234-4883.318" + cell $xor $xor$ls180.v:4883$854 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc1_val [0] + connect \B \main_sdcore_crc16_inserter_crc1_crcreg1 [15] + connect \Y $xor$ls180.v:4883$854_Y + end + attribute \src "ls180.v:4883.187-4883.319" + cell $xor $xor$ls180.v:4883$855 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc1_crcreg1 [11] + connect \B $xor$ls180.v:4883$854_Y + connect \Y $xor$ls180.v:4883$855_Y + end + attribute \src "ls180.v:4892.899-4892.983" + cell $xor $xor$ls180.v:4892$857 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc2_val [1] + connect \B \main_sdcore_crc16_inserter_crc2_crcreg0 [15] + connect \Y $xor$ls180.v:4892$857_Y + end + attribute \src "ls180.v:4892.634-4892.718" + cell $xor $xor$ls180.v:4892$858 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc2_val [1] + connect \B \main_sdcore_crc16_inserter_crc2_crcreg0 [15] + connect \Y $xor$ls180.v:4892$858_Y + end + attribute \src "ls180.v:4892.588-4892.719" + cell $xor $xor$ls180.v:4892$859 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc2_crcreg0 [4] + connect \B $xor$ls180.v:4892$858_Y + connect \Y $xor$ls180.v:4892$859_Y + end + attribute \src "ls180.v:4892.234-4892.318" + cell $xor $xor$ls180.v:4892$860 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc2_val [1] + connect \B \main_sdcore_crc16_inserter_crc2_crcreg0 [15] + connect \Y $xor$ls180.v:4892$860_Y + end + attribute \src "ls180.v:4892.187-4892.319" + cell $xor $xor$ls180.v:4892$861 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc2_crcreg0 [11] + connect \B $xor$ls180.v:4892$860_Y + connect \Y $xor$ls180.v:4892$861_Y + end + attribute \src "ls180.v:4893.899-4893.983" + cell $xor $xor$ls180.v:4893$862 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc2_val [0] + connect \B \main_sdcore_crc16_inserter_crc2_crcreg1 [15] + connect \Y $xor$ls180.v:4893$862_Y + end + attribute \src "ls180.v:4893.634-4893.718" + cell $xor $xor$ls180.v:4893$863 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc2_val [0] + connect \B \main_sdcore_crc16_inserter_crc2_crcreg1 [15] + connect \Y $xor$ls180.v:4893$863_Y + end + attribute \src "ls180.v:4893.588-4893.719" + cell $xor $xor$ls180.v:4893$864 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc2_crcreg1 [4] + connect \B $xor$ls180.v:4893$863_Y + connect \Y $xor$ls180.v:4893$864_Y + end + attribute \src "ls180.v:4893.234-4893.318" + cell $xor $xor$ls180.v:4893$865 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc2_val [0] + connect \B \main_sdcore_crc16_inserter_crc2_crcreg1 [15] + connect \Y $xor$ls180.v:4893$865_Y + end + attribute \src "ls180.v:4893.187-4893.319" + cell $xor $xor$ls180.v:4893$866 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc2_crcreg1 [11] + connect \B $xor$ls180.v:4893$865_Y + connect \Y $xor$ls180.v:4893$866_Y + end + attribute \src "ls180.v:4902.899-4902.983" + cell $xor $xor$ls180.v:4902$868 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc3_val [1] + connect \B \main_sdcore_crc16_inserter_crc3_crcreg0 [15] + connect \Y $xor$ls180.v:4902$868_Y + end + attribute \src "ls180.v:4902.634-4902.718" + cell $xor $xor$ls180.v:4902$869 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc3_val [1] + connect \B \main_sdcore_crc16_inserter_crc3_crcreg0 [15] + connect \Y $xor$ls180.v:4902$869_Y + end + attribute \src "ls180.v:4902.588-4902.719" + cell $xor $xor$ls180.v:4902$870 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc3_crcreg0 [4] + connect \B $xor$ls180.v:4902$869_Y + connect \Y $xor$ls180.v:4902$870_Y + end + attribute \src "ls180.v:4902.234-4902.318" + cell $xor $xor$ls180.v:4902$871 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc3_val [1] + connect \B \main_sdcore_crc16_inserter_crc3_crcreg0 [15] + connect \Y $xor$ls180.v:4902$871_Y + end + attribute \src "ls180.v:4902.187-4902.319" + cell $xor $xor$ls180.v:4902$872 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc3_crcreg0 [11] + connect \B $xor$ls180.v:4902$871_Y + connect \Y $xor$ls180.v:4902$872_Y + end + attribute \src "ls180.v:4903.899-4903.983" + cell $xor $xor$ls180.v:4903$873 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc3_val [0] + connect \B \main_sdcore_crc16_inserter_crc3_crcreg1 [15] + connect \Y $xor$ls180.v:4903$873_Y + end + attribute \src "ls180.v:4903.634-4903.718" + cell $xor $xor$ls180.v:4903$874 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc3_val [0] + connect \B \main_sdcore_crc16_inserter_crc3_crcreg1 [15] + connect \Y $xor$ls180.v:4903$874_Y + end + attribute \src "ls180.v:4903.588-4903.719" + cell $xor $xor$ls180.v:4903$875 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc3_crcreg1 [4] + connect \B $xor$ls180.v:4903$874_Y + connect \Y $xor$ls180.v:4903$875_Y + end + attribute \src "ls180.v:4903.234-4903.318" + cell $xor $xor$ls180.v:4903$876 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc3_val [0] + connect \B \main_sdcore_crc16_inserter_crc3_crcreg1 [15] + connect \Y $xor$ls180.v:4903$876_Y + end + attribute \src "ls180.v:4903.187-4903.319" + cell $xor $xor$ls180.v:4903$877 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc3_crcreg1 [11] + connect \B $xor$ls180.v:4903$876_Y + connect \Y $xor$ls180.v:4903$877_Y + end + attribute \src "ls180.v:5054.879-5054.961" + cell $xor $xor$ls180.v:5054$910 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc0_val [1] + connect \B \main_sdcore_crc16_checker_crc0_crcreg0 [15] + connect \Y $xor$ls180.v:5054$910_Y + end + attribute \src "ls180.v:5054.620-5054.702" + cell $xor $xor$ls180.v:5054$911 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc0_val [1] + connect \B \main_sdcore_crc16_checker_crc0_crcreg0 [15] + connect \Y $xor$ls180.v:5054$911_Y + end + attribute \src "ls180.v:5054.575-5054.703" + cell $xor $xor$ls180.v:5054$912 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc0_crcreg0 [4] + connect \B $xor$ls180.v:5054$911_Y + connect \Y $xor$ls180.v:5054$912_Y + end + attribute \src "ls180.v:5054.229-5054.311" + cell $xor $xor$ls180.v:5054$913 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc0_val [1] + connect \B \main_sdcore_crc16_checker_crc0_crcreg0 [15] + connect \Y $xor$ls180.v:5054$913_Y + end + attribute \src "ls180.v:5054.183-5054.312" + cell $xor $xor$ls180.v:5054$914 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc0_crcreg0 [11] + connect \B $xor$ls180.v:5054$913_Y + connect \Y $xor$ls180.v:5054$914_Y + end + attribute \src "ls180.v:5055.879-5055.961" + cell $xor $xor$ls180.v:5055$915 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc0_val [0] + connect \B \main_sdcore_crc16_checker_crc0_crcreg1 [15] + connect \Y $xor$ls180.v:5055$915_Y + end + attribute \src "ls180.v:5055.620-5055.702" + cell $xor $xor$ls180.v:5055$916 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc0_val [0] + connect \B \main_sdcore_crc16_checker_crc0_crcreg1 [15] + connect \Y $xor$ls180.v:5055$916_Y + end + attribute \src "ls180.v:5055.575-5055.703" + cell $xor $xor$ls180.v:5055$917 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc0_crcreg1 [4] + connect \B $xor$ls180.v:5055$916_Y + connect \Y $xor$ls180.v:5055$917_Y + end + attribute \src "ls180.v:5055.229-5055.311" + cell $xor $xor$ls180.v:5055$918 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc0_val [0] + connect \B \main_sdcore_crc16_checker_crc0_crcreg1 [15] + connect \Y $xor$ls180.v:5055$918_Y + end + attribute \src "ls180.v:5055.183-5055.312" + cell $xor $xor$ls180.v:5055$919 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc0_crcreg1 [11] + connect \B $xor$ls180.v:5055$918_Y + connect \Y $xor$ls180.v:5055$919_Y + end + attribute \src "ls180.v:5064.879-5064.961" + cell $xor $xor$ls180.v:5064$921 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc1_val [1] + connect \B \main_sdcore_crc16_checker_crc1_crcreg0 [15] + connect \Y $xor$ls180.v:5064$921_Y + end + attribute \src "ls180.v:5064.620-5064.702" + cell $xor $xor$ls180.v:5064$922 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc1_val [1] + connect \B \main_sdcore_crc16_checker_crc1_crcreg0 [15] + connect \Y $xor$ls180.v:5064$922_Y + end + attribute \src "ls180.v:5064.575-5064.703" + cell $xor $xor$ls180.v:5064$923 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc1_crcreg0 [4] + connect \B $xor$ls180.v:5064$922_Y + connect \Y $xor$ls180.v:5064$923_Y + end + attribute \src "ls180.v:5064.229-5064.311" + cell $xor $xor$ls180.v:5064$924 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc1_val [1] + connect \B \main_sdcore_crc16_checker_crc1_crcreg0 [15] + connect \Y $xor$ls180.v:5064$924_Y + end + attribute \src "ls180.v:5064.183-5064.312" + cell $xor $xor$ls180.v:5064$925 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc1_crcreg0 [11] + connect \B $xor$ls180.v:5064$924_Y + connect \Y $xor$ls180.v:5064$925_Y + end + attribute \src "ls180.v:5065.879-5065.961" + cell $xor $xor$ls180.v:5065$926 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc1_val [0] + connect \B \main_sdcore_crc16_checker_crc1_crcreg1 [15] + connect \Y $xor$ls180.v:5065$926_Y + end + attribute \src "ls180.v:5065.620-5065.702" + cell $xor $xor$ls180.v:5065$927 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc1_val [0] + connect \B \main_sdcore_crc16_checker_crc1_crcreg1 [15] + connect \Y $xor$ls180.v:5065$927_Y + end + attribute \src "ls180.v:5065.575-5065.703" + cell $xor $xor$ls180.v:5065$928 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc1_crcreg1 [4] + connect \B $xor$ls180.v:5065$927_Y + connect \Y $xor$ls180.v:5065$928_Y + end + attribute \src "ls180.v:5065.229-5065.311" + cell $xor $xor$ls180.v:5065$929 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc1_val [0] + connect \B \main_sdcore_crc16_checker_crc1_crcreg1 [15] + connect \Y $xor$ls180.v:5065$929_Y + end + attribute \src "ls180.v:5065.183-5065.312" + cell $xor $xor$ls180.v:5065$930 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc1_crcreg1 [11] + connect \B $xor$ls180.v:5065$929_Y + connect \Y $xor$ls180.v:5065$930_Y + end + attribute \src "ls180.v:5074.879-5074.961" + cell $xor $xor$ls180.v:5074$932 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc2_val [1] + connect \B \main_sdcore_crc16_checker_crc2_crcreg0 [15] + connect \Y $xor$ls180.v:5074$932_Y + end + attribute \src "ls180.v:5074.620-5074.702" + cell $xor $xor$ls180.v:5074$933 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc2_val [1] + connect \B \main_sdcore_crc16_checker_crc2_crcreg0 [15] + connect \Y $xor$ls180.v:5074$933_Y + end + attribute \src "ls180.v:5074.575-5074.703" + cell $xor $xor$ls180.v:5074$934 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc2_crcreg0 [4] + connect \B $xor$ls180.v:5074$933_Y + connect \Y $xor$ls180.v:5074$934_Y + end + attribute \src "ls180.v:5074.229-5074.311" + cell $xor $xor$ls180.v:5074$935 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc2_val [1] + connect \B \main_sdcore_crc16_checker_crc2_crcreg0 [15] + connect \Y $xor$ls180.v:5074$935_Y + end + attribute \src "ls180.v:5074.183-5074.312" + cell $xor $xor$ls180.v:5074$936 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc2_crcreg0 [11] + connect \B $xor$ls180.v:5074$935_Y + connect \Y $xor$ls180.v:5074$936_Y + end + attribute \src "ls180.v:5075.879-5075.961" + cell $xor $xor$ls180.v:5075$937 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc2_val [0] + connect \B \main_sdcore_crc16_checker_crc2_crcreg1 [15] + connect \Y $xor$ls180.v:5075$937_Y + end + attribute \src "ls180.v:5075.620-5075.702" + cell $xor $xor$ls180.v:5075$938 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc2_val [0] + connect \B \main_sdcore_crc16_checker_crc2_crcreg1 [15] + connect \Y $xor$ls180.v:5075$938_Y + end + attribute \src "ls180.v:5075.575-5075.703" + cell $xor $xor$ls180.v:5075$939 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc2_crcreg1 [4] + connect \B $xor$ls180.v:5075$938_Y + connect \Y $xor$ls180.v:5075$939_Y + end + attribute \src "ls180.v:5075.229-5075.311" + cell $xor $xor$ls180.v:5075$940 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc2_val [0] + connect \B \main_sdcore_crc16_checker_crc2_crcreg1 [15] + connect \Y $xor$ls180.v:5075$940_Y + end + attribute \src "ls180.v:5075.183-5075.312" + cell $xor $xor$ls180.v:5075$941 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc2_crcreg1 [11] + connect \B $xor$ls180.v:5075$940_Y + connect \Y $xor$ls180.v:5075$941_Y + end + attribute \src "ls180.v:5084.879-5084.961" + cell $xor $xor$ls180.v:5084$943 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc3_val [1] + connect \B \main_sdcore_crc16_checker_crc3_crcreg0 [15] + connect \Y $xor$ls180.v:5084$943_Y + end + attribute \src "ls180.v:5084.620-5084.702" + cell $xor $xor$ls180.v:5084$944 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc3_val [1] + connect \B \main_sdcore_crc16_checker_crc3_crcreg0 [15] + connect \Y $xor$ls180.v:5084$944_Y + end + attribute \src "ls180.v:5084.575-5084.703" + cell $xor $xor$ls180.v:5084$945 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc3_crcreg0 [4] + connect \B $xor$ls180.v:5084$944_Y + connect \Y $xor$ls180.v:5084$945_Y + end + attribute \src "ls180.v:5084.229-5084.311" + cell $xor $xor$ls180.v:5084$946 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc3_val [1] + connect \B \main_sdcore_crc16_checker_crc3_crcreg0 [15] + connect \Y $xor$ls180.v:5084$946_Y + end + attribute \src "ls180.v:5084.183-5084.312" + cell $xor $xor$ls180.v:5084$947 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc3_crcreg0 [11] + connect \B $xor$ls180.v:5084$946_Y + connect \Y $xor$ls180.v:5084$947_Y + end + attribute \src "ls180.v:5085.879-5085.961" + cell $xor $xor$ls180.v:5085$948 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc3_val [0] + connect \B \main_sdcore_crc16_checker_crc3_crcreg1 [15] + connect \Y $xor$ls180.v:5085$948_Y + end + attribute \src "ls180.v:5085.620-5085.702" + cell $xor $xor$ls180.v:5085$949 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc3_val [0] + connect \B \main_sdcore_crc16_checker_crc3_crcreg1 [15] + connect \Y $xor$ls180.v:5085$949_Y + end + attribute \src "ls180.v:5085.575-5085.703" + cell $xor $xor$ls180.v:5085$950 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc3_crcreg1 [4] + connect \B $xor$ls180.v:5085$949_Y + connect \Y $xor$ls180.v:5085$950_Y + end + attribute \src "ls180.v:5085.229-5085.311" + cell $xor $xor$ls180.v:5085$951 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc3_val [0] + connect \B \main_sdcore_crc16_checker_crc3_crcreg1 [15] + connect \Y $xor$ls180.v:5085$951_Y + end + attribute \src "ls180.v:5085.183-5085.312" + cell $xor $xor$ls180.v:5085$952 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc3_crcreg1 [11] + connect \B $xor$ls180.v:5085$951_Y + connect \Y $xor$ls180.v:5085$952_Y + end + attribute \module_not_derived 1 + attribute \src "ls180.v:10113.13-10280.2" + cell \test_issuer \test_issuer + connect \TAP_bus__tck \main_libresocsim_libresoc_jtag_tck + connect \TAP_bus__tdi \main_libresocsim_libresoc_jtag_tdi + connect \TAP_bus__tdo \main_libresocsim_libresoc_jtag_tdo + connect \TAP_bus__tms \main_libresocsim_libresoc_jtag_tms + connect \busy_o \main_libresocsim_libresoc0 + connect \clk \sys_clk_1 + connect \core_bigendian_i 1'0 + connect \dbus__ack \main_libresocsim_libresoc_dbus_ack + connect \dbus__adr \main_libresocsim_libresoc_dbus_adr + connect \dbus__bte \main_libresocsim_libresoc_dbus_bte + connect \dbus__cti \main_libresocsim_libresoc_dbus_cti + connect \dbus__cyc \main_libresocsim_libresoc_dbus_cyc + connect \dbus__dat_r \main_libresocsim_libresoc_dbus_dat_r + connect \dbus__dat_w \main_libresocsim_libresoc_dbus_dat_w + connect \dbus__err \main_libresocsim_libresoc_dbus_err + connect \dbus__sel \main_libresocsim_libresoc_dbus_sel + connect \dbus__stb \main_libresocsim_libresoc_dbus_stb + connect \dbus__we \main_libresocsim_libresoc_dbus_we + connect \gpio_gpio0__core__i \main_libresocsim_libresoc_constraintmanager0_gpio0_i [0] + connect \gpio_gpio0__core__o \main_libresocsim_libresoc_constraintmanager0_gpio0_o [0] + connect \gpio_gpio0__core__oe \main_libresocsim_libresoc_constraintmanager0_gpio0_oe [0] + connect \gpio_gpio0__pad__i \main_libresocsim_libresoc_constraintmanager1_gpio0_i [0] + connect \gpio_gpio0__pad__o \main_libresocsim_libresoc_constraintmanager1_gpio0_o [0] + connect \gpio_gpio0__pad__oe \main_libresocsim_libresoc_constraintmanager1_gpio0_oe [0] + connect \gpio_gpio10__core__i \main_libresocsim_libresoc_constraintmanager0_gpio0_i [10] + connect \gpio_gpio10__core__o \main_libresocsim_libresoc_constraintmanager0_gpio0_o [10] + connect \gpio_gpio10__core__oe \main_libresocsim_libresoc_constraintmanager0_gpio0_oe [10] + connect \gpio_gpio10__pad__i \main_libresocsim_libresoc_constraintmanager1_gpio0_i [10] + connect \gpio_gpio10__pad__o \main_libresocsim_libresoc_constraintmanager1_gpio0_o [10] + connect \gpio_gpio10__pad__oe \main_libresocsim_libresoc_constraintmanager1_gpio0_oe [10] + connect \gpio_gpio11__core__i \main_libresocsim_libresoc_constraintmanager0_gpio0_i [11] + connect \gpio_gpio11__core__o \main_libresocsim_libresoc_constraintmanager0_gpio0_o [11] + connect \gpio_gpio11__core__oe \main_libresocsim_libresoc_constraintmanager0_gpio0_oe [11] + connect \gpio_gpio11__pad__i \main_libresocsim_libresoc_constraintmanager1_gpio0_i [11] + connect \gpio_gpio11__pad__o \main_libresocsim_libresoc_constraintmanager1_gpio0_o [11] + connect \gpio_gpio11__pad__oe \main_libresocsim_libresoc_constraintmanager1_gpio0_oe [11] + connect \gpio_gpio12__core__i \main_libresocsim_libresoc_constraintmanager0_gpio0_i [12] + connect \gpio_gpio12__core__o \main_libresocsim_libresoc_constraintmanager0_gpio0_o [12] + connect \gpio_gpio12__core__oe \main_libresocsim_libresoc_constraintmanager0_gpio0_oe [12] + connect \gpio_gpio12__pad__i \main_libresocsim_libresoc_constraintmanager1_gpio0_i [12] + connect \gpio_gpio12__pad__o \main_libresocsim_libresoc_constraintmanager1_gpio0_o [12] + connect \gpio_gpio12__pad__oe \main_libresocsim_libresoc_constraintmanager1_gpio0_oe [12] + connect \gpio_gpio13__core__i \main_libresocsim_libresoc_constraintmanager0_gpio0_i [13] + connect \gpio_gpio13__core__o \main_libresocsim_libresoc_constraintmanager0_gpio0_o [13] + connect \gpio_gpio13__core__oe \main_libresocsim_libresoc_constraintmanager0_gpio0_oe [13] + connect \gpio_gpio13__pad__i \main_libresocsim_libresoc_constraintmanager1_gpio0_i [13] + connect \gpio_gpio13__pad__o \main_libresocsim_libresoc_constraintmanager1_gpio0_o [13] + connect \gpio_gpio13__pad__oe \main_libresocsim_libresoc_constraintmanager1_gpio0_oe [13] + connect \gpio_gpio14__core__i \main_libresocsim_libresoc_constraintmanager0_gpio0_i [14] + connect \gpio_gpio14__core__o \main_libresocsim_libresoc_constraintmanager0_gpio0_o [14] + connect \gpio_gpio14__core__oe \main_libresocsim_libresoc_constraintmanager0_gpio0_oe [14] + connect \gpio_gpio14__pad__i \main_libresocsim_libresoc_constraintmanager1_gpio0_i [14] + connect \gpio_gpio14__pad__o \main_libresocsim_libresoc_constraintmanager1_gpio0_o [14] + connect \gpio_gpio14__pad__oe \main_libresocsim_libresoc_constraintmanager1_gpio0_oe [14] + connect \gpio_gpio15__core__i \main_libresocsim_libresoc_constraintmanager0_gpio0_i [15] + connect \gpio_gpio15__core__o \main_libresocsim_libresoc_constraintmanager0_gpio0_o [15] + connect \gpio_gpio15__core__oe \main_libresocsim_libresoc_constraintmanager0_gpio0_oe [15] + connect \gpio_gpio15__pad__i \main_libresocsim_libresoc_constraintmanager1_gpio0_i [15] + connect \gpio_gpio15__pad__o \main_libresocsim_libresoc_constraintmanager1_gpio0_o [15] + connect \gpio_gpio15__pad__oe \main_libresocsim_libresoc_constraintmanager1_gpio0_oe [15] + connect \gpio_gpio1__core__i \main_libresocsim_libresoc_constraintmanager0_gpio0_i [1] + connect \gpio_gpio1__core__o \main_libresocsim_libresoc_constraintmanager0_gpio0_o [1] + connect \gpio_gpio1__core__oe \main_libresocsim_libresoc_constraintmanager0_gpio0_oe [1] + connect \gpio_gpio1__pad__i \main_libresocsim_libresoc_constraintmanager1_gpio0_i [1] + connect \gpio_gpio1__pad__o \main_libresocsim_libresoc_constraintmanager1_gpio0_o [1] + connect \gpio_gpio1__pad__oe \main_libresocsim_libresoc_constraintmanager1_gpio0_oe [1] + connect \gpio_gpio2__core__i \main_libresocsim_libresoc_constraintmanager0_gpio0_i [2] + connect \gpio_gpio2__core__o \main_libresocsim_libresoc_constraintmanager0_gpio0_o [2] + connect \gpio_gpio2__core__oe \main_libresocsim_libresoc_constraintmanager0_gpio0_oe [2] + connect \gpio_gpio2__pad__i \main_libresocsim_libresoc_constraintmanager1_gpio0_i [2] + connect \gpio_gpio2__pad__o \main_libresocsim_libresoc_constraintmanager1_gpio0_o [2] + connect \gpio_gpio2__pad__oe \main_libresocsim_libresoc_constraintmanager1_gpio0_oe [2] + connect \gpio_gpio3__core__i \main_libresocsim_libresoc_constraintmanager0_gpio0_i [3] + connect \gpio_gpio3__core__o \main_libresocsim_libresoc_constraintmanager0_gpio0_o [3] + connect \gpio_gpio3__core__oe \main_libresocsim_libresoc_constraintmanager0_gpio0_oe [3] + connect \gpio_gpio3__pad__i \main_libresocsim_libresoc_constraintmanager1_gpio0_i [3] + connect \gpio_gpio3__pad__o \main_libresocsim_libresoc_constraintmanager1_gpio0_o [3] + connect \gpio_gpio3__pad__oe \main_libresocsim_libresoc_constraintmanager1_gpio0_oe [3] + connect \gpio_gpio4__core__i \main_libresocsim_libresoc_constraintmanager0_gpio0_i [4] + connect \gpio_gpio4__core__o \main_libresocsim_libresoc_constraintmanager0_gpio0_o [4] + connect \gpio_gpio4__core__oe \main_libresocsim_libresoc_constraintmanager0_gpio0_oe [4] + connect \gpio_gpio4__pad__i \main_libresocsim_libresoc_constraintmanager1_gpio0_i [4] + connect \gpio_gpio4__pad__o \main_libresocsim_libresoc_constraintmanager1_gpio0_o [4] + connect \gpio_gpio4__pad__oe \main_libresocsim_libresoc_constraintmanager1_gpio0_oe [4] + connect \gpio_gpio5__core__i \main_libresocsim_libresoc_constraintmanager0_gpio0_i [5] + connect \gpio_gpio5__core__o \main_libresocsim_libresoc_constraintmanager0_gpio0_o [5] + connect \gpio_gpio5__core__oe \main_libresocsim_libresoc_constraintmanager0_gpio0_oe [5] + connect \gpio_gpio5__pad__i \main_libresocsim_libresoc_constraintmanager1_gpio0_i [5] + connect \gpio_gpio5__pad__o \main_libresocsim_libresoc_constraintmanager1_gpio0_o [5] + connect \gpio_gpio5__pad__oe \main_libresocsim_libresoc_constraintmanager1_gpio0_oe [5] + connect \gpio_gpio6__core__i \main_libresocsim_libresoc_constraintmanager0_gpio0_i [6] + connect \gpio_gpio6__core__o \main_libresocsim_libresoc_constraintmanager0_gpio0_o [6] + connect \gpio_gpio6__core__oe \main_libresocsim_libresoc_constraintmanager0_gpio0_oe [6] + connect \gpio_gpio6__pad__i \main_libresocsim_libresoc_constraintmanager1_gpio0_i [6] + connect \gpio_gpio6__pad__o \main_libresocsim_libresoc_constraintmanager1_gpio0_o [6] + connect \gpio_gpio6__pad__oe \main_libresocsim_libresoc_constraintmanager1_gpio0_oe [6] + connect \gpio_gpio7__core__i \main_libresocsim_libresoc_constraintmanager0_gpio0_i [7] + connect \gpio_gpio7__core__o \main_libresocsim_libresoc_constraintmanager0_gpio0_o [7] + connect \gpio_gpio7__core__oe \main_libresocsim_libresoc_constraintmanager0_gpio0_oe [7] + connect \gpio_gpio7__pad__i \main_libresocsim_libresoc_constraintmanager1_gpio0_i [7] + connect \gpio_gpio7__pad__o \main_libresocsim_libresoc_constraintmanager1_gpio0_o [7] + connect \gpio_gpio7__pad__oe \main_libresocsim_libresoc_constraintmanager1_gpio0_oe [7] + connect \gpio_gpio8__core__i \main_libresocsim_libresoc_constraintmanager0_gpio0_i [8] + connect \gpio_gpio8__core__o \main_libresocsim_libresoc_constraintmanager0_gpio0_o [8] + connect \gpio_gpio8__core__oe \main_libresocsim_libresoc_constraintmanager0_gpio0_oe [8] + connect \gpio_gpio8__pad__i \main_libresocsim_libresoc_constraintmanager1_gpio0_i [8] + connect \gpio_gpio8__pad__o \main_libresocsim_libresoc_constraintmanager1_gpio0_o [8] + connect \gpio_gpio8__pad__oe \main_libresocsim_libresoc_constraintmanager1_gpio0_oe [8] + connect \gpio_gpio9__core__i \main_libresocsim_libresoc_constraintmanager0_gpio0_i [9] + connect \gpio_gpio9__core__o \main_libresocsim_libresoc_constraintmanager0_gpio0_o [9] + connect \gpio_gpio9__core__oe \main_libresocsim_libresoc_constraintmanager0_gpio0_oe [9] + connect \gpio_gpio9__pad__i \main_libresocsim_libresoc_constraintmanager1_gpio0_i [9] + connect \gpio_gpio9__pad__o \main_libresocsim_libresoc_constraintmanager1_gpio0_o [9] + connect \gpio_gpio9__pad__oe \main_libresocsim_libresoc_constraintmanager1_gpio0_oe [9] + connect \ibus__ack \main_libresocsim_libresoc_ibus_ack + connect \ibus__adr \main_libresocsim_libresoc_ibus_adr + connect \ibus__bte \main_libresocsim_libresoc_ibus_bte + connect \ibus__cti \main_libresocsim_libresoc_ibus_cti + connect \ibus__cyc \main_libresocsim_libresoc_ibus_cyc + connect \ibus__dat_r \main_libresocsim_libresoc_ibus_dat_r + connect \ibus__dat_w \main_libresocsim_libresoc_ibus_dat_w + connect \ibus__err \main_libresocsim_libresoc_ibus_err + connect \ibus__sel \main_libresocsim_libresoc_ibus_sel + connect \ibus__stb \main_libresocsim_libresoc_ibus_stb + connect \ibus__we \main_libresocsim_libresoc_ibus_we + connect \icp_wb__ack \main_libresocsim_libresoc_xics_icp_ack + connect \icp_wb__adr \main_libresocsim_libresoc_xics_icp_adr + connect \icp_wb__bte \main_libresocsim_libresoc_xics_icp_bte + connect \icp_wb__cti \main_libresocsim_libresoc_xics_icp_cti + connect \icp_wb__cyc \main_libresocsim_libresoc_xics_icp_cyc + connect \icp_wb__dat_r \main_libresocsim_libresoc_xics_icp_dat_r + connect \icp_wb__dat_w \main_libresocsim_libresoc_xics_icp_dat_w + connect \icp_wb__err \main_libresocsim_libresoc_xics_icp_err + connect \icp_wb__sel \main_libresocsim_libresoc_xics_icp_sel + connect \icp_wb__stb \main_libresocsim_libresoc_xics_icp_stb + connect \icp_wb__we \main_libresocsim_libresoc_xics_icp_we + connect \ics_wb__ack \main_libresocsim_libresoc_xics_ics_ack + connect \ics_wb__adr \main_libresocsim_libresoc_xics_ics_adr + connect \ics_wb__bte \main_libresocsim_libresoc_xics_ics_bte + connect \ics_wb__cti \main_libresocsim_libresoc_xics_ics_cti + connect \ics_wb__cyc \main_libresocsim_libresoc_xics_ics_cyc + connect \ics_wb__dat_r \main_libresocsim_libresoc_xics_ics_dat_r + connect \ics_wb__dat_w \main_libresocsim_libresoc_xics_ics_dat_w + connect \ics_wb__err \main_libresocsim_libresoc_xics_ics_err + connect \ics_wb__sel \main_libresocsim_libresoc_xics_ics_sel + connect \ics_wb__stb \main_libresocsim_libresoc_xics_ics_stb + connect \ics_wb__we \main_libresocsim_libresoc_xics_ics_we + connect \int_level_i \main_libresocsim_libresoc_interrupt + connect \jtag_wb__ack \main_libresocsim_libresoc_jtag_wb_ack + connect \jtag_wb__adr \main_libresocsim_libresoc_jtag_wb_adr + connect \jtag_wb__cyc \main_libresocsim_libresoc_jtag_wb_cyc + connect \jtag_wb__dat_r \main_libresocsim_libresoc_jtag_wb_dat_r + connect \jtag_wb__dat_w \main_libresocsim_libresoc_jtag_wb_dat_w + connect \jtag_wb__err \main_libresocsim_libresoc_jtag_wb_err + connect \jtag_wb__sel \main_libresocsim_libresoc_jtag_wb_sel + connect \jtag_wb__stb \main_libresocsim_libresoc_jtag_wb_stb + connect \jtag_wb__we \main_libresocsim_libresoc_jtag_wb_we + connect \memerr_o \main_libresocsim_libresoc1 + connect \pc_i 1'0 + connect \pc_i_ok 1'0 + connect \pc_o \main_libresocsim_libresoc2 + connect \rst $or$ls180.v:10195$2752_Y + connect \uart_rx__core__i \main_libresocsim_libresoc_constraintmanager0_uart0_rx + connect \uart_rx__pad__i \main_libresocsim_libresoc_constraintmanager1_uart0_rx + connect \uart_tx__core__o \main_libresocsim_libresoc_constraintmanager0_uart0_tx + connect \uart_tx__pad__o \main_libresocsim_libresoc_constraintmanager1_uart0_tx + end + attribute \src "ls180.v:0.0-0.0" + process $proc$ls180.v:0$3701 + sync always + sync init + end + attribute \src "ls180.v:10003.1-10004.4" + process $proc$ls180.v:10003$2701 + sync posedge \sys_clk_1 + end + attribute \src "ls180.v:1001.12-1001.37" + process $proc$ls180.v:1001$3150 + assign { } { } + assign $1\main_pwm0_counter[31:0] 0 + sync always + sync init + update \main_pwm0_counter $1\main_pwm0_counter[31:0] + end + attribute \src "ls180.v:10011.1-10015.4" + process $proc$ls180.v:10011$2703 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\storage_1$ls180.v:10013$6_ADDR[2:0]$2704 3'xxx + assign $0$memwr$\storage_1$ls180.v:10013$6_DATA[24:0]$2705 25'xxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\storage_1$ls180.v:10013$6_EN[24:0]$2706 25'0000000000000000000000000 + assign $0\memdat_1[24:0] $memrd$\storage_1$ls180.v:10014$2707_DATA + attribute \src "ls180.v:10012.2-10013.131" + switch \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we + attribute \src "ls180.v:10012.6-10012.60" + case 1'1 + assign $0$memwr$\storage_1$ls180.v:10013$6_ADDR[2:0]$2704 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr + assign $0$memwr$\storage_1$ls180.v:10013$6_DATA[24:0]$2705 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w + assign $0$memwr$\storage_1$ls180.v:10013$6_EN[24:0]$2706 25'1111111111111111111111111 + case + end + sync posedge \sys_clk_1 + update \memdat_1 $0\memdat_1[24:0] + update $memwr$\storage_1$ls180.v:10013$6_ADDR $0$memwr$\storage_1$ls180.v:10013$6_ADDR[2:0]$2704 + update $memwr$\storage_1$ls180.v:10013$6_DATA $0$memwr$\storage_1$ls180.v:10013$6_DATA[24:0]$2705 + update $memwr$\storage_1$ls180.v:10013$6_EN $0$memwr$\storage_1$ls180.v:10013$6_EN[24:0]$2706 + end + attribute \src "ls180.v:10017.1-10018.4" + process $proc$ls180.v:10017$2708 + sync posedge \sys_clk_1 + end + attribute \src "ls180.v:1002.5-1002.36" + process $proc$ls180.v:1002$3151 + assign { } { } + assign $1\main_pwm0_enable_storage[0:0] 1'0 + sync always + sync init + update \main_pwm0_enable_storage $1\main_pwm0_enable_storage[0:0] + end + attribute \src "ls180.v:10025.1-10029.4" + process $proc$ls180.v:10025$2710 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\storage_2$ls180.v:10027$7_ADDR[2:0]$2711 3'xxx + assign $0$memwr$\storage_2$ls180.v:10027$7_DATA[24:0]$2712 25'xxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\storage_2$ls180.v:10027$7_EN[24:0]$2713 25'0000000000000000000000000 + assign $0\memdat_2[24:0] $memrd$\storage_2$ls180.v:10028$2714_DATA + attribute \src "ls180.v:10026.2-10027.131" + switch \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_we + attribute \src "ls180.v:10026.6-10026.60" + case 1'1 + assign $0$memwr$\storage_2$ls180.v:10027$7_ADDR[2:0]$2711 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr + assign $0$memwr$\storage_2$ls180.v:10027$7_DATA[24:0]$2712 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w + assign $0$memwr$\storage_2$ls180.v:10027$7_EN[24:0]$2713 25'1111111111111111111111111 + case + end + sync posedge \sys_clk_1 + update \memdat_2 $0\memdat_2[24:0] + update $memwr$\storage_2$ls180.v:10027$7_ADDR $0$memwr$\storage_2$ls180.v:10027$7_ADDR[2:0]$2711 + update $memwr$\storage_2$ls180.v:10027$7_DATA $0$memwr$\storage_2$ls180.v:10027$7_DATA[24:0]$2712 + update $memwr$\storage_2$ls180.v:10027$7_EN $0$memwr$\storage_2$ls180.v:10027$7_EN[24:0]$2713 + end + attribute \src "ls180.v:1003.5-1003.31" + process $proc$ls180.v:1003$3152 + assign { } { } + assign $1\main_pwm0_enable_re[0:0] 1'0 + sync always + sync init + update \main_pwm0_enable_re $1\main_pwm0_enable_re[0:0] + end + attribute \src "ls180.v:10031.1-10032.4" + process $proc$ls180.v:10031$2715 + sync posedge \sys_clk_1 + end + attribute \src "ls180.v:10039.1-10043.4" + process $proc$ls180.v:10039$2717 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\storage_3$ls180.v:10041$8_ADDR[2:0]$2718 3'xxx + assign $0$memwr$\storage_3$ls180.v:10041$8_DATA[24:0]$2719 25'xxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\storage_3$ls180.v:10041$8_EN[24:0]$2720 25'0000000000000000000000000 + assign $0\memdat_3[24:0] $memrd$\storage_3$ls180.v:10042$2721_DATA + attribute \src "ls180.v:10040.2-10041.131" + switch \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_we + attribute \src "ls180.v:10040.6-10040.60" + case 1'1 + assign $0$memwr$\storage_3$ls180.v:10041$8_ADDR[2:0]$2718 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr + assign $0$memwr$\storage_3$ls180.v:10041$8_DATA[24:0]$2719 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w + assign $0$memwr$\storage_3$ls180.v:10041$8_EN[24:0]$2720 25'1111111111111111111111111 + case + end + sync posedge \sys_clk_1 + update \memdat_3 $0\memdat_3[24:0] + update $memwr$\storage_3$ls180.v:10041$8_ADDR $0$memwr$\storage_3$ls180.v:10041$8_ADDR[2:0]$2718 + update $memwr$\storage_3$ls180.v:10041$8_DATA $0$memwr$\storage_3$ls180.v:10041$8_DATA[24:0]$2719 + update $memwr$\storage_3$ls180.v:10041$8_EN $0$memwr$\storage_3$ls180.v:10041$8_EN[24:0]$2720 + end + attribute \src "ls180.v:1004.12-1004.43" + process $proc$ls180.v:1004$3153 + assign { } { } + assign $1\main_pwm0_width_storage[31:0] 0 + sync always + sync init + update \main_pwm0_width_storage $1\main_pwm0_width_storage[31:0] + end + attribute \src "ls180.v:10045.1-10046.4" + process $proc$ls180.v:10045$2722 + sync posedge \sys_clk_1 + end + attribute \src "ls180.v:1005.5-1005.30" + process $proc$ls180.v:1005$3154 + assign { } { } + assign $1\main_pwm0_width_re[0:0] 1'0 + sync always + sync init + update \main_pwm0_width_re $1\main_pwm0_width_re[0:0] + end + attribute \src "ls180.v:10054.1-10058.4" + process $proc$ls180.v:10054$2724 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\storage_4$ls180.v:10056$9_ADDR[3:0]$2725 4'xxxx + assign $0$memwr$\storage_4$ls180.v:10056$9_DATA[9:0]$2726 10'xxxxxxxxxx + assign $0$memwr$\storage_4$ls180.v:10056$9_EN[9:0]$2727 10'0000000000 + assign $0\memdat_4[9:0] $memrd$\storage_4$ls180.v:10057$2728_DATA + attribute \src "ls180.v:10055.2-10056.77" + switch \main_uart_tx_fifo_wrport_we + attribute \src "ls180.v:10055.6-10055.33" + case 1'1 + assign $0$memwr$\storage_4$ls180.v:10056$9_ADDR[3:0]$2725 \main_uart_tx_fifo_wrport_adr + assign $0$memwr$\storage_4$ls180.v:10056$9_DATA[9:0]$2726 \main_uart_tx_fifo_wrport_dat_w + assign $0$memwr$\storage_4$ls180.v:10056$9_EN[9:0]$2727 10'1111111111 + case + end + sync posedge \sys_clk_1 + update \memdat_4 $0\memdat_4[9:0] + update $memwr$\storage_4$ls180.v:10056$9_ADDR $0$memwr$\storage_4$ls180.v:10056$9_ADDR[3:0]$2725 + update $memwr$\storage_4$ls180.v:10056$9_DATA $0$memwr$\storage_4$ls180.v:10056$9_DATA[9:0]$2726 + update $memwr$\storage_4$ls180.v:10056$9_EN $0$memwr$\storage_4$ls180.v:10056$9_EN[9:0]$2727 + end + attribute \src "ls180.v:1006.12-1006.44" + process $proc$ls180.v:1006$3155 + assign { } { } + assign $1\main_pwm0_period_storage[31:0] 0 + sync always + sync init + update \main_pwm0_period_storage $1\main_pwm0_period_storage[31:0] + end + attribute \src "ls180.v:10060.1-10063.4" + process $proc$ls180.v:10060$2729 + assign $0\memdat_5[9:0] \memdat_5 + attribute \src "ls180.v:10061.2-10062.55" + switch \main_uart_tx_fifo_rdport_re + attribute \src "ls180.v:10061.6-10061.33" + case 1'1 + assign $0\memdat_5[9:0] $memrd$\storage_4$ls180.v:10062$2730_DATA + case + end + sync posedge \sys_clk_1 + update \memdat_5 $0\memdat_5[9:0] + end + attribute \src "ls180.v:1007.5-1007.31" + process $proc$ls180.v:1007$3156 + assign { } { } + assign $1\main_pwm0_period_re[0:0] 1'0 + sync always + sync init + update \main_pwm0_period_re $1\main_pwm0_period_re[0:0] + end + attribute \src "ls180.v:10071.1-10075.4" + process $proc$ls180.v:10071$2731 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\storage_5$ls180.v:10073$10_ADDR[3:0]$2732 4'xxxx + assign $0$memwr$\storage_5$ls180.v:10073$10_DATA[9:0]$2733 10'xxxxxxxxxx + assign $0$memwr$\storage_5$ls180.v:10073$10_EN[9:0]$2734 10'0000000000 + assign $0\memdat_6[9:0] $memrd$\storage_5$ls180.v:10074$2735_DATA + attribute \src "ls180.v:10072.2-10073.77" + switch \main_uart_rx_fifo_wrport_we + attribute \src "ls180.v:10072.6-10072.33" + case 1'1 + assign $0$memwr$\storage_5$ls180.v:10073$10_ADDR[3:0]$2732 \main_uart_rx_fifo_wrport_adr + assign $0$memwr$\storage_5$ls180.v:10073$10_DATA[9:0]$2733 \main_uart_rx_fifo_wrport_dat_w + assign $0$memwr$\storage_5$ls180.v:10073$10_EN[9:0]$2734 10'1111111111 + case + end + sync posedge \sys_clk_1 + update \memdat_6 $0\memdat_6[9:0] + update $memwr$\storage_5$ls180.v:10073$10_ADDR $0$memwr$\storage_5$ls180.v:10073$10_ADDR[3:0]$2732 + update $memwr$\storage_5$ls180.v:10073$10_DATA $0$memwr$\storage_5$ls180.v:10073$10_DATA[9:0]$2733 + update $memwr$\storage_5$ls180.v:10073$10_EN $0$memwr$\storage_5$ls180.v:10073$10_EN[9:0]$2734 + end + attribute \src "ls180.v:10077.1-10080.4" + process $proc$ls180.v:10077$2736 + assign $0\memdat_7[9:0] \memdat_7 + attribute \src "ls180.v:10078.2-10079.55" + switch \main_uart_rx_fifo_rdport_re + attribute \src "ls180.v:10078.6-10078.33" + case 1'1 + assign $0\memdat_7[9:0] $memrd$\storage_5$ls180.v:10079$2737_DATA + case + end + sync posedge \sys_clk_1 + update \memdat_7 $0\memdat_7[9:0] + end + attribute \src "ls180.v:10087.1-10091.4" + process $proc$ls180.v:10087$2738 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\storage_6$ls180.v:10089$11_ADDR[4:0]$2739 5'xxxxx + assign $0$memwr$\storage_6$ls180.v:10089$11_DATA[9:0]$2740 10'xxxxxxxxxx + assign $0$memwr$\storage_6$ls180.v:10089$11_EN[9:0]$2741 10'0000000000 + assign $0\memdat_8[9:0] $memrd$\storage_6$ls180.v:10090$2742_DATA + attribute \src "ls180.v:10088.2-10089.85" + switch \main_sdblock2mem_fifo_wrport_we + attribute \src "ls180.v:10088.6-10088.37" + case 1'1 + assign $0$memwr$\storage_6$ls180.v:10089$11_ADDR[4:0]$2739 \main_sdblock2mem_fifo_wrport_adr + assign $0$memwr$\storage_6$ls180.v:10089$11_DATA[9:0]$2740 \main_sdblock2mem_fifo_wrport_dat_w + assign $0$memwr$\storage_6$ls180.v:10089$11_EN[9:0]$2741 10'1111111111 + case + end + sync posedge \sys_clk_1 + update \memdat_8 $0\memdat_8[9:0] + update $memwr$\storage_6$ls180.v:10089$11_ADDR $0$memwr$\storage_6$ls180.v:10089$11_ADDR[4:0]$2739 + update $memwr$\storage_6$ls180.v:10089$11_DATA $0$memwr$\storage_6$ls180.v:10089$11_DATA[9:0]$2740 + update $memwr$\storage_6$ls180.v:10089$11_EN $0$memwr$\storage_6$ls180.v:10089$11_EN[9:0]$2741 + end + attribute \src "ls180.v:10093.1-10094.4" + process $proc$ls180.v:10093$2743 + sync posedge \sys_clk_1 + end + attribute \src "ls180.v:10101.1-10105.4" + process $proc$ls180.v:10101$2745 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\storage_7$ls180.v:10103$12_ADDR[4:0]$2746 5'xxxxx + assign $0$memwr$\storage_7$ls180.v:10103$12_DATA[9:0]$2747 10'xxxxxxxxxx + assign $0$memwr$\storage_7$ls180.v:10103$12_EN[9:0]$2748 10'0000000000 + assign $0\memdat_9[9:0] $memrd$\storage_7$ls180.v:10104$2749_DATA + attribute \src "ls180.v:10102.2-10103.85" + switch \main_sdmem2block_fifo_wrport_we + attribute \src "ls180.v:10102.6-10102.37" + case 1'1 + assign $0$memwr$\storage_7$ls180.v:10103$12_ADDR[4:0]$2746 \main_sdmem2block_fifo_wrport_adr + assign $0$memwr$\storage_7$ls180.v:10103$12_DATA[9:0]$2747 \main_sdmem2block_fifo_wrport_dat_w + assign $0$memwr$\storage_7$ls180.v:10103$12_EN[9:0]$2748 10'1111111111 + case + end + sync posedge \sys_clk_1 + update \memdat_9 $0\memdat_9[9:0] + update $memwr$\storage_7$ls180.v:10103$12_ADDR $0$memwr$\storage_7$ls180.v:10103$12_ADDR[4:0]$2746 + update $memwr$\storage_7$ls180.v:10103$12_DATA $0$memwr$\storage_7$ls180.v:10103$12_DATA[9:0]$2747 + update $memwr$\storage_7$ls180.v:10103$12_EN $0$memwr$\storage_7$ls180.v:10103$12_EN[9:0]$2748 + end + attribute \src "ls180.v:10107.1-10108.4" + process $proc$ls180.v:10107$2750 + sync posedge \sys_clk_1 + end + attribute \src "ls180.v:1011.12-1011.37" + process $proc$ls180.v:1011$3157 + assign { } { } + assign $1\main_pwm1_counter[31:0] 0 + sync always + sync init + update \main_pwm1_counter $1\main_pwm1_counter[31:0] + end + attribute \src "ls180.v:1012.5-1012.36" + process $proc$ls180.v:1012$3158 + assign { } { } + assign $1\main_pwm1_enable_storage[0:0] 1'0 + sync always + sync init + update \main_pwm1_enable_storage $1\main_pwm1_enable_storage[0:0] + end + attribute \src "ls180.v:1013.5-1013.31" + process $proc$ls180.v:1013$3159 + assign { } { } + assign $1\main_pwm1_enable_re[0:0] 1'0 + sync always + sync init + update \main_pwm1_enable_re $1\main_pwm1_enable_re[0:0] + end + attribute \src "ls180.v:1014.12-1014.43" + process $proc$ls180.v:1014$3160 + assign { } { } + assign $1\main_pwm1_width_storage[31:0] 0 + sync always + sync init + update \main_pwm1_width_storage $1\main_pwm1_width_storage[31:0] + end + attribute \src "ls180.v:1015.5-1015.30" + process $proc$ls180.v:1015$3161 + assign { } { } + assign $1\main_pwm1_width_re[0:0] 1'0 + sync always + sync init + update \main_pwm1_width_re $1\main_pwm1_width_re[0:0] + end + attribute \src "ls180.v:1016.12-1016.44" + process $proc$ls180.v:1016$3162 + assign { } { } + assign $1\main_pwm1_period_storage[31:0] 0 + sync always + sync init + update \main_pwm1_period_storage $1\main_pwm1_period_storage[31:0] + end + attribute \src "ls180.v:1017.5-1017.31" + process $proc$ls180.v:1017$3163 + assign { } { } + assign $1\main_pwm1_period_re[0:0] 1'0 + sync always + sync init + update \main_pwm1_period_re $1\main_pwm1_period_re[0:0] + end + attribute \src "ls180.v:1020.11-1020.46" + process $proc$ls180.v:1020$3164 + assign { } { } + assign $1\main_sdphy_clocker_storage[8:0] 9'100000000 + sync always + sync init + update \main_sdphy_clocker_storage $1\main_sdphy_clocker_storage[8:0] + end + attribute \src "ls180.v:1021.5-1021.33" + process $proc$ls180.v:1021$3165 + assign { } { } + assign $1\main_sdphy_clocker_re[0:0] 1'0 + sync always + sync init + update \main_sdphy_clocker_re $1\main_sdphy_clocker_re[0:0] + end + attribute \src "ls180.v:1023.5-1023.35" + process $proc$ls180.v:1023$3166 + assign { } { } + assign $1\main_sdphy_clocker_clk0[0:0] 1'0 + sync always + sync init + update \main_sdphy_clocker_clk0 $1\main_sdphy_clocker_clk0[0:0] + end + attribute \src "ls180.v:1025.11-1025.41" + process $proc$ls180.v:1025$3167 + assign { } { } + assign $1\main_sdphy_clocker_clks[8:0] 9'000000000 + sync always + sync init + update \main_sdphy_clocker_clks $1\main_sdphy_clocker_clks[8:0] + end + attribute \src "ls180.v:1026.5-1026.35" + process $proc$ls180.v:1026$3168 + assign { } { } + assign $1\main_sdphy_clocker_clk1[0:0] 1'0 + sync always + sync init + update \main_sdphy_clocker_clk1 $1\main_sdphy_clocker_clk1[0:0] + end + attribute \src "ls180.v:1027.5-1027.36" + process $proc$ls180.v:1027$3169 + assign { } { } + assign $1\main_sdphy_clocker_clk_d[0:0] 1'0 + sync always + sync init + update \main_sdphy_clocker_clk_d $1\main_sdphy_clocker_clk_d[0:0] + end + attribute \src "ls180.v:1031.5-1031.40" + process $proc$ls180.v:1031$3170 + assign { } { } + assign $0\main_sdphy_init_initialize_w[0:0] 1'0 + sync always + update \main_sdphy_init_initialize_w $0\main_sdphy_init_initialize_w[0:0] + sync init + end + attribute \src "ls180.v:1036.5-1036.48" + process $proc$ls180.v:1036$3171 + assign { } { } + assign $1\main_sdphy_init_pads_out_payload_clk[0:0] 1'0 + sync always + sync init + update \main_sdphy_init_pads_out_payload_clk $1\main_sdphy_init_pads_out_payload_clk[0:0] + end + attribute \src "ls180.v:1037.5-1037.50" + process $proc$ls180.v:1037$3172 + assign { } { } + assign $1\main_sdphy_init_pads_out_payload_cmd_o[0:0] 1'0 + sync always + sync init + update \main_sdphy_init_pads_out_payload_cmd_o $1\main_sdphy_init_pads_out_payload_cmd_o[0:0] + end + attribute \src "ls180.v:1038.5-1038.51" + process $proc$ls180.v:1038$3173 + assign { } { } + assign $1\main_sdphy_init_pads_out_payload_cmd_oe[0:0] 1'0 + sync always + sync init + update \main_sdphy_init_pads_out_payload_cmd_oe $1\main_sdphy_init_pads_out_payload_cmd_oe[0:0] + end + attribute \src "ls180.v:1039.11-1039.57" + process $proc$ls180.v:1039$3174 + assign { } { } + assign $1\main_sdphy_init_pads_out_payload_data_o[3:0] 4'0000 + sync always + sync init + update \main_sdphy_init_pads_out_payload_data_o $1\main_sdphy_init_pads_out_payload_data_o[3:0] + end + attribute \src "ls180.v:1040.5-1040.52" + process $proc$ls180.v:1040$3175 + assign { } { } + assign $1\main_sdphy_init_pads_out_payload_data_oe[0:0] 1'0 + sync always + sync init + update \main_sdphy_init_pads_out_payload_data_oe $1\main_sdphy_init_pads_out_payload_data_oe[0:0] + end + attribute \src "ls180.v:1041.11-1041.39" + process $proc$ls180.v:1041$3176 + assign { } { } + assign $1\main_sdphy_init_count[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_init_count $1\main_sdphy_init_count[7:0] + end + attribute \src "ls180.v:1046.5-1046.48" + process $proc$ls180.v:1046$3177 + assign { } { } + assign $1\main_sdphy_cmdw_pads_out_payload_clk[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdw_pads_out_payload_clk $1\main_sdphy_cmdw_pads_out_payload_clk[0:0] + end + attribute \src "ls180.v:1047.5-1047.50" + process $proc$ls180.v:1047$3178 + assign { } { } + assign $1\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdw_pads_out_payload_cmd_o $1\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] + end + attribute \src "ls180.v:1048.5-1048.51" + process $proc$ls180.v:1048$3179 + assign { } { } + assign $1\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdw_pads_out_payload_cmd_oe $1\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] + end + attribute \src "ls180.v:1049.11-1049.57" + process $proc$ls180.v:1049$3180 + assign { } { } + assign $0\main_sdphy_cmdw_pads_out_payload_data_o[3:0] 4'0000 + sync always + update \main_sdphy_cmdw_pads_out_payload_data_o $0\main_sdphy_cmdw_pads_out_payload_data_o[3:0] + sync init + end + attribute \src "ls180.v:1050.5-1050.52" + process $proc$ls180.v:1050$3181 + assign { } { } + assign $0\main_sdphy_cmdw_pads_out_payload_data_oe[0:0] 1'0 + sync always + update \main_sdphy_cmdw_pads_out_payload_data_oe $0\main_sdphy_cmdw_pads_out_payload_data_oe[0:0] + sync init + end + attribute \src "ls180.v:1051.5-1051.38" + process $proc$ls180.v:1051$3182 + assign { } { } + assign $1\main_sdphy_cmdw_sink_valid[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdw_sink_valid $1\main_sdphy_cmdw_sink_valid[0:0] + end + attribute \src "ls180.v:1052.5-1052.38" + process $proc$ls180.v:1052$3183 + assign { } { } + assign $1\main_sdphy_cmdw_sink_ready[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdw_sink_ready $1\main_sdphy_cmdw_sink_ready[0:0] + end + attribute \src "ls180.v:1053.5-1053.37" + process $proc$ls180.v:1053$3184 + assign { } { } + assign $1\main_sdphy_cmdw_sink_last[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdw_sink_last $1\main_sdphy_cmdw_sink_last[0:0] + end + attribute \src "ls180.v:1054.11-1054.51" + process $proc$ls180.v:1054$3185 + assign { } { } + assign $1\main_sdphy_cmdw_sink_payload_data[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_cmdw_sink_payload_data $1\main_sdphy_cmdw_sink_payload_data[7:0] + end + attribute \src "ls180.v:1055.5-1055.32" + process $proc$ls180.v:1055$3186 + assign { } { } + assign $1\main_sdphy_cmdw_done[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdw_done $1\main_sdphy_cmdw_done[0:0] + end + attribute \src "ls180.v:1056.11-1056.39" + process $proc$ls180.v:1056$3187 + assign { } { } + assign $1\main_sdphy_cmdw_count[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_cmdw_count $1\main_sdphy_cmdw_count[7:0] + end + attribute \src "ls180.v:1059.5-1059.49" + process $proc$ls180.v:1059$3188 + assign { } { } + assign $0\main_sdphy_cmdr_pads_in_pads_in_first[0:0] 1'0 + sync always + update \main_sdphy_cmdr_pads_in_pads_in_first $0\main_sdphy_cmdr_pads_in_pads_in_first[0:0] + sync init + end + attribute \src "ls180.v:1060.5-1060.48" + process $proc$ls180.v:1060$3189 + assign { } { } + assign $0\main_sdphy_cmdr_pads_in_pads_in_last[0:0] 1'0 + sync always + update \main_sdphy_cmdr_pads_in_pads_in_last $0\main_sdphy_cmdr_pads_in_pads_in_last[0:0] + sync init + end + attribute \src "ls180.v:1061.5-1061.55" + process $proc$ls180.v:1061$3190 + assign { } { } + assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_clk[0:0] 1'0 + sync always + update \main_sdphy_cmdr_pads_in_pads_in_payload_clk $0\main_sdphy_cmdr_pads_in_pads_in_payload_clk[0:0] + sync init + end + attribute \src "ls180.v:1063.5-1063.57" + process $proc$ls180.v:1063$3191 + assign { } { } + assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_o[0:0] 1'0 + sync always + update \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_o $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_o[0:0] + sync init + end + attribute \src "ls180.v:1064.5-1064.58" + process $proc$ls180.v:1064$3192 + assign { } { } + assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_oe[0:0] 1'0 + sync always + update \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_oe $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_oe[0:0] + sync init + end + attribute \src "ls180.v:1066.11-1066.64" + process $proc$ls180.v:1066$3193 + assign { } { } + assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_o[3:0] 4'0000 + sync always + update \main_sdphy_cmdr_pads_in_pads_in_payload_data_o $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_o[3:0] + sync init + end + attribute \src "ls180.v:1067.5-1067.59" + process $proc$ls180.v:1067$3194 + assign { } { } + assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_oe[0:0] 1'0 + sync always + update \main_sdphy_cmdr_pads_in_pads_in_payload_data_oe $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_oe[0:0] + sync init + end + attribute \src "ls180.v:1069.5-1069.48" + process $proc$ls180.v:1069$3195 + assign { } { } + assign $1\main_sdphy_cmdr_pads_out_payload_clk[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_pads_out_payload_clk $1\main_sdphy_cmdr_pads_out_payload_clk[0:0] + end + attribute \src "ls180.v:1070.5-1070.50" + process $proc$ls180.v:1070$3196 + assign { } { } + assign $1\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_pads_out_payload_cmd_o $1\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] + end + attribute \src "ls180.v:1071.5-1071.51" + process $proc$ls180.v:1071$3197 + assign { } { } + assign $1\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_pads_out_payload_cmd_oe $1\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] + end + attribute \src "ls180.v:1072.11-1072.57" + process $proc$ls180.v:1072$3198 + assign { } { } + assign $0\main_sdphy_cmdr_pads_out_payload_data_o[3:0] 4'0000 + sync always + update \main_sdphy_cmdr_pads_out_payload_data_o $0\main_sdphy_cmdr_pads_out_payload_data_o[3:0] + sync init + end + attribute \src "ls180.v:1073.5-1073.52" + process $proc$ls180.v:1073$3199 + assign { } { } + assign $0\main_sdphy_cmdr_pads_out_payload_data_oe[0:0] 1'0 + sync always + update \main_sdphy_cmdr_pads_out_payload_data_oe $0\main_sdphy_cmdr_pads_out_payload_data_oe[0:0] + sync init + end + attribute \src "ls180.v:1074.5-1074.38" + process $proc$ls180.v:1074$3200 + assign { } { } + assign $1\main_sdphy_cmdr_sink_valid[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_sink_valid $1\main_sdphy_cmdr_sink_valid[0:0] + end + attribute \src "ls180.v:1075.5-1075.38" + process $proc$ls180.v:1075$3201 + assign { } { } + assign $1\main_sdphy_cmdr_sink_ready[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_sink_ready $1\main_sdphy_cmdr_sink_ready[0:0] + end + attribute \src "ls180.v:1076.5-1076.37" + process $proc$ls180.v:1076$3202 + assign { } { } + assign $1\main_sdphy_cmdr_sink_last[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_sink_last $1\main_sdphy_cmdr_sink_last[0:0] + end + attribute \src "ls180.v:1077.11-1077.53" + process $proc$ls180.v:1077$3203 + assign { } { } + assign $1\main_sdphy_cmdr_sink_payload_length[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_cmdr_sink_payload_length $1\main_sdphy_cmdr_sink_payload_length[7:0] + end + attribute \src "ls180.v:1078.5-1078.40" + process $proc$ls180.v:1078$3204 + assign { } { } + assign $1\main_sdphy_cmdr_source_valid[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_source_valid $1\main_sdphy_cmdr_source_valid[0:0] + end + attribute \src "ls180.v:1079.5-1079.40" + process $proc$ls180.v:1079$3205 + assign { } { } + assign $1\main_sdphy_cmdr_source_ready[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_source_ready $1\main_sdphy_cmdr_source_ready[0:0] + end + attribute \src "ls180.v:1080.5-1080.39" + process $proc$ls180.v:1080$3206 + assign { } { } + assign $1\main_sdphy_cmdr_source_last[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_source_last $1\main_sdphy_cmdr_source_last[0:0] + end + attribute \src "ls180.v:1081.11-1081.53" + process $proc$ls180.v:1081$3207 + assign { } { } + assign $1\main_sdphy_cmdr_source_payload_data[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_cmdr_source_payload_data $1\main_sdphy_cmdr_source_payload_data[7:0] + end + attribute \src "ls180.v:1082.11-1082.55" + process $proc$ls180.v:1082$3208 + assign { } { } + assign $1\main_sdphy_cmdr_source_payload_status[2:0] 3'000 + sync always + sync init + update \main_sdphy_cmdr_source_payload_status $1\main_sdphy_cmdr_source_payload_status[2:0] + end + attribute \src "ls180.v:1083.12-1083.48" + process $proc$ls180.v:1083$3209 + assign { } { } + assign $1\main_sdphy_cmdr_timeout[31:0] 500000 + sync always + sync init + update \main_sdphy_cmdr_timeout $1\main_sdphy_cmdr_timeout[31:0] + end + attribute \src "ls180.v:1084.11-1084.39" + process $proc$ls180.v:1084$3210 + assign { } { } + assign $1\main_sdphy_cmdr_count[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_cmdr_count $1\main_sdphy_cmdr_count[7:0] + end + attribute \src "ls180.v:1086.5-1086.46" + process $proc$ls180.v:1086$3211 + assign { } { } + assign $0\main_sdphy_cmdr_cmdr_pads_in_ready[0:0] 1'0 + sync always + update \main_sdphy_cmdr_cmdr_pads_in_ready $0\main_sdphy_cmdr_cmdr_pads_in_ready[0:0] + sync init + end + attribute \src "ls180.v:1097.5-1097.53" + process $proc$ls180.v:1097$3212 + assign { } { } + assign $1\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_cmdr_source_source_ready0 $1\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] + end + attribute \src "ls180.v:110.5-110.49" + process $proc$ls180.v:110$2775 + assign { } { } + assign $1\main_libresocsim_libresoc_jtag_wb_ack[0:0] 1'0 + sync always + sync init + update \main_libresocsim_libresoc_jtag_wb_ack $1\main_libresocsim_libresoc_jtag_wb_ack[0:0] + end + attribute \src "ls180.v:1102.5-1102.36" + process $proc$ls180.v:1102$3213 + assign { } { } + assign $1\main_sdphy_cmdr_cmdr_run[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_cmdr_run $1\main_sdphy_cmdr_cmdr_run[0:0] + end + attribute \src "ls180.v:1105.5-1105.53" + process $proc$ls180.v:1105$3214 + assign { } { } + assign $0\main_sdphy_cmdr_cmdr_converter_sink_first[0:0] 1'0 + sync always + update \main_sdphy_cmdr_cmdr_converter_sink_first $0\main_sdphy_cmdr_cmdr_converter_sink_first[0:0] + sync init + end + attribute \src "ls180.v:1106.5-1106.52" + process $proc$ls180.v:1106$3215 + assign { } { } + assign $0\main_sdphy_cmdr_cmdr_converter_sink_last[0:0] 1'0 + sync always + update \main_sdphy_cmdr_cmdr_converter_sink_last $0\main_sdphy_cmdr_cmdr_converter_sink_last[0:0] + sync init + end + attribute \src "ls180.v:1110.5-1110.55" + process $proc$ls180.v:1110$3216 + assign { } { } + assign $1\main_sdphy_cmdr_cmdr_converter_source_first[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_cmdr_converter_source_first $1\main_sdphy_cmdr_cmdr_converter_source_first[0:0] + end + attribute \src "ls180.v:1111.5-1111.54" + process $proc$ls180.v:1111$3217 + assign { } { } + assign $1\main_sdphy_cmdr_cmdr_converter_source_last[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_cmdr_converter_source_last $1\main_sdphy_cmdr_cmdr_converter_source_last[0:0] + end + attribute \src "ls180.v:1112.11-1112.68" + process $proc$ls180.v:1112$3218 + assign { } { } + assign $1\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_cmdr_cmdr_converter_source_payload_data $1\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] + end + attribute \src "ls180.v:1113.11-1113.81" + process $proc$ls180.v:1113$3219 + assign { } { } + assign $1\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] 4'0000 + sync always + sync init + update \main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count $1\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] + end + attribute \src "ls180.v:1114.11-1114.54" + process $proc$ls180.v:1114$3220 + assign { } { } + assign $1\main_sdphy_cmdr_cmdr_converter_demux[2:0] 3'000 + sync always + sync init + update \main_sdphy_cmdr_cmdr_converter_demux $1\main_sdphy_cmdr_cmdr_converter_demux[2:0] + end + attribute \src "ls180.v:1116.5-1116.53" + process $proc$ls180.v:1116$3221 + assign { } { } + assign $1\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_cmdr_converter_strobe_all $1\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] + end + attribute \src "ls180.v:112.5-112.49" + process $proc$ls180.v:112$2776 + assign { } { } + assign $0\main_libresocsim_libresoc_jtag_wb_err[0:0] 1'0 + sync always + update \main_libresocsim_libresoc_jtag_wb_err $0\main_libresocsim_libresoc_jtag_wb_err[0:0] + sync init + end + attribute \src "ls180.v:1127.5-1127.49" + process $proc$ls180.v:1127$3222 + assign { } { } + assign $1\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_cmdr_buf_source_valid $1\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] + end + attribute \src "ls180.v:1129.5-1129.49" + process $proc$ls180.v:1129$3223 + assign { } { } + assign $1\main_sdphy_cmdr_cmdr_buf_source_first[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_cmdr_buf_source_first $1\main_sdphy_cmdr_cmdr_buf_source_first[0:0] + end + attribute \src "ls180.v:1130.5-1130.48" + process $proc$ls180.v:1130$3224 + assign { } { } + assign $1\main_sdphy_cmdr_cmdr_buf_source_last[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_cmdr_buf_source_last $1\main_sdphy_cmdr_cmdr_buf_source_last[0:0] + end + attribute \src "ls180.v:1131.11-1131.62" + process $proc$ls180.v:1131$3225 + assign { } { } + assign $1\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_cmdr_cmdr_buf_source_payload_data $1\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] + end + attribute \src "ls180.v:1132.5-1132.38" + process $proc$ls180.v:1132$3226 + assign { } { } + assign $1\main_sdphy_cmdr_cmdr_reset[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_cmdr_reset $1\main_sdphy_cmdr_cmdr_reset[0:0] + end + attribute \src "ls180.v:1137.5-1137.49" + process $proc$ls180.v:1137$3227 + assign { } { } + assign $1\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_pads_out_payload_clk $1\main_sdphy_dataw_pads_out_payload_clk[0:0] + end + attribute \src "ls180.v:1138.5-1138.51" + process $proc$ls180.v:1138$3228 + assign { } { } + assign $0\main_sdphy_dataw_pads_out_payload_cmd_o[0:0] 1'0 + sync always + update \main_sdphy_dataw_pads_out_payload_cmd_o $0\main_sdphy_dataw_pads_out_payload_cmd_o[0:0] + sync init + end + attribute \src "ls180.v:1139.5-1139.52" + process $proc$ls180.v:1139$3229 + assign { } { } + assign $0\main_sdphy_dataw_pads_out_payload_cmd_oe[0:0] 1'0 + sync always + update \main_sdphy_dataw_pads_out_payload_cmd_oe $0\main_sdphy_dataw_pads_out_payload_cmd_oe[0:0] + sync init + end + attribute \src "ls180.v:1140.11-1140.58" + process $proc$ls180.v:1140$3230 + assign { } { } + assign $1\main_sdphy_dataw_pads_out_payload_data_o[3:0] 4'0000 + sync always + sync init + update \main_sdphy_dataw_pads_out_payload_data_o $1\main_sdphy_dataw_pads_out_payload_data_o[3:0] + end + attribute \src "ls180.v:1141.5-1141.53" + process $proc$ls180.v:1141$3231 + assign { } { } + assign $1\main_sdphy_dataw_pads_out_payload_data_oe[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_pads_out_payload_data_oe $1\main_sdphy_dataw_pads_out_payload_data_oe[0:0] + end + attribute \src "ls180.v:1142.5-1142.39" + process $proc$ls180.v:1142$3232 + assign { } { } + assign $1\main_sdphy_dataw_sink_valid[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_sink_valid $1\main_sdphy_dataw_sink_valid[0:0] + end + attribute \src "ls180.v:1143.5-1143.39" + process $proc$ls180.v:1143$3233 + assign { } { } + assign $1\main_sdphy_dataw_sink_ready[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_sink_ready $1\main_sdphy_dataw_sink_ready[0:0] + end + attribute \src "ls180.v:1144.5-1144.39" + process $proc$ls180.v:1144$3234 + assign { } { } + assign $1\main_sdphy_dataw_sink_first[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_sink_first $1\main_sdphy_dataw_sink_first[0:0] + end + attribute \src "ls180.v:1145.5-1145.38" + process $proc$ls180.v:1145$3235 + assign { } { } + assign $1\main_sdphy_dataw_sink_last[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_sink_last $1\main_sdphy_dataw_sink_last[0:0] + end + attribute \src "ls180.v:1146.11-1146.52" + process $proc$ls180.v:1146$3236 + assign { } { } + assign $1\main_sdphy_dataw_sink_payload_data[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_dataw_sink_payload_data $1\main_sdphy_dataw_sink_payload_data[7:0] + end + attribute \src "ls180.v:1147.5-1147.33" + process $proc$ls180.v:1147$3237 + assign { } { } + assign $1\main_sdphy_dataw_stop[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_stop $1\main_sdphy_dataw_stop[0:0] + end + attribute \src "ls180.v:1148.11-1148.40" + process $proc$ls180.v:1148$3238 + assign { } { } + assign $1\main_sdphy_dataw_count[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_dataw_count $1\main_sdphy_dataw_count[7:0] + end + attribute \src "ls180.v:1149.5-1149.50" + process $proc$ls180.v:1149$3239 + assign { } { } + assign $0\main_sdphy_dataw_pads_in_pads_in_valid[0:0] 1'0 + sync always + update \main_sdphy_dataw_pads_in_pads_in_valid $0\main_sdphy_dataw_pads_in_pads_in_valid[0:0] + sync init + end + attribute \src "ls180.v:1151.5-1151.50" + process $proc$ls180.v:1151$3240 + assign { } { } + assign $0\main_sdphy_dataw_pads_in_pads_in_first[0:0] 1'0 + sync always + update \main_sdphy_dataw_pads_in_pads_in_first $0\main_sdphy_dataw_pads_in_pads_in_first[0:0] + sync init + end + attribute \src "ls180.v:1152.5-1152.49" + process $proc$ls180.v:1152$3241 + assign { } { } + assign $0\main_sdphy_dataw_pads_in_pads_in_last[0:0] 1'0 + sync always + update \main_sdphy_dataw_pads_in_pads_in_last $0\main_sdphy_dataw_pads_in_pads_in_last[0:0] + sync init + end + attribute \src "ls180.v:1153.5-1153.56" + process $proc$ls180.v:1153$3242 + assign { } { } + assign $0\main_sdphy_dataw_pads_in_pads_in_payload_clk[0:0] 1'0 + sync always + update \main_sdphy_dataw_pads_in_pads_in_payload_clk $0\main_sdphy_dataw_pads_in_pads_in_payload_clk[0:0] + sync init + end + attribute \src "ls180.v:1154.5-1154.58" + process $proc$ls180.v:1154$3243 + assign { } { } + assign $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_i[0:0] 1'0 + sync always + update \main_sdphy_dataw_pads_in_pads_in_payload_cmd_i $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_i[0:0] + sync init + end + attribute \src "ls180.v:1155.5-1155.58" + process $proc$ls180.v:1155$3244 + assign { } { } + assign $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_o[0:0] 1'0 + sync always + update \main_sdphy_dataw_pads_in_pads_in_payload_cmd_o $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_o[0:0] + sync init + end + attribute \src "ls180.v:1156.5-1156.59" + process $proc$ls180.v:1156$3245 + assign { } { } + assign $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_oe[0:0] 1'0 + sync always + update \main_sdphy_dataw_pads_in_pads_in_payload_cmd_oe $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_oe[0:0] + sync init + end + attribute \src "ls180.v:1157.11-1157.65" + process $proc$ls180.v:1157$3246 + assign { } { } + assign $0\main_sdphy_dataw_pads_in_pads_in_payload_data_i[3:0] 4'0000 + sync always + update \main_sdphy_dataw_pads_in_pads_in_payload_data_i $0\main_sdphy_dataw_pads_in_pads_in_payload_data_i[3:0] + sync init + end + attribute \src "ls180.v:1158.11-1158.65" + process $proc$ls180.v:1158$3247 + assign { } { } + assign $0\main_sdphy_dataw_pads_in_pads_in_payload_data_o[3:0] 4'0000 + sync always + update \main_sdphy_dataw_pads_in_pads_in_payload_data_o $0\main_sdphy_dataw_pads_in_pads_in_payload_data_o[3:0] + sync init + end + attribute \src "ls180.v:1159.5-1159.60" + process $proc$ls180.v:1159$3248 + assign { } { } + assign $0\main_sdphy_dataw_pads_in_pads_in_payload_data_oe[0:0] 1'0 + sync always + update \main_sdphy_dataw_pads_in_pads_in_payload_data_oe $0\main_sdphy_dataw_pads_in_pads_in_payload_data_oe[0:0] + sync init + end + attribute \src "ls180.v:1160.5-1160.34" + process $proc$ls180.v:1160$3249 + assign { } { } + assign $1\main_sdphy_dataw_start[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_start $1\main_sdphy_dataw_start[0:0] + end + attribute \src "ls180.v:1161.5-1161.34" + process $proc$ls180.v:1161$3250 + assign { } { } + assign $1\main_sdphy_dataw_valid[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_valid $1\main_sdphy_dataw_valid[0:0] + end + attribute \src "ls180.v:1162.5-1162.34" + process $proc$ls180.v:1162$3251 + assign { } { } + assign $1\main_sdphy_dataw_error[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_error $1\main_sdphy_dataw_error[0:0] + end + attribute \src "ls180.v:1164.5-1164.47" + process $proc$ls180.v:1164$3252 + assign { } { } + assign $0\main_sdphy_dataw_crcr_pads_in_ready[0:0] 1'0 + sync always + update \main_sdphy_dataw_crcr_pads_in_ready $0\main_sdphy_dataw_crcr_pads_in_ready[0:0] + sync init + end + attribute \src "ls180.v:1175.5-1175.54" + process $proc$ls180.v:1175$3253 + assign { } { } + assign $1\main_sdphy_dataw_crcr_source_source_ready0[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_crcr_source_source_ready0 $1\main_sdphy_dataw_crcr_source_source_ready0[0:0] + end + attribute \src "ls180.v:1180.5-1180.37" + process $proc$ls180.v:1180$3254 + assign { } { } + assign $1\main_sdphy_dataw_crcr_run[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_crcr_run $1\main_sdphy_dataw_crcr_run[0:0] + end + attribute \src "ls180.v:1183.5-1183.54" + process $proc$ls180.v:1183$3255 + assign { } { } + assign $0\main_sdphy_dataw_crcr_converter_sink_first[0:0] 1'0 + sync always + update \main_sdphy_dataw_crcr_converter_sink_first $0\main_sdphy_dataw_crcr_converter_sink_first[0:0] + sync init + end + attribute \src "ls180.v:1184.5-1184.53" + process $proc$ls180.v:1184$3256 + assign { } { } + assign $0\main_sdphy_dataw_crcr_converter_sink_last[0:0] 1'0 + sync always + update \main_sdphy_dataw_crcr_converter_sink_last $0\main_sdphy_dataw_crcr_converter_sink_last[0:0] + sync init + end + attribute \src "ls180.v:1188.5-1188.56" + process $proc$ls180.v:1188$3257 + assign { } { } + assign $1\main_sdphy_dataw_crcr_converter_source_first[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_crcr_converter_source_first $1\main_sdphy_dataw_crcr_converter_source_first[0:0] + end + attribute \src "ls180.v:1189.5-1189.55" + process $proc$ls180.v:1189$3258 + assign { } { } + assign $1\main_sdphy_dataw_crcr_converter_source_last[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_crcr_converter_source_last $1\main_sdphy_dataw_crcr_converter_source_last[0:0] + end + attribute \src "ls180.v:1190.11-1190.69" + process $proc$ls180.v:1190$3259 + assign { } { } + assign $1\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_dataw_crcr_converter_source_payload_data $1\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] + end + attribute \src "ls180.v:1191.11-1191.82" + process $proc$ls180.v:1191$3260 + assign { } { } + assign $1\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] 4'0000 + sync always + sync init + update \main_sdphy_dataw_crcr_converter_source_payload_valid_token_count $1\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] + end + attribute \src "ls180.v:1192.11-1192.55" + process $proc$ls180.v:1192$3261 + assign { } { } + assign $1\main_sdphy_dataw_crcr_converter_demux[2:0] 3'000 + sync always + sync init + update \main_sdphy_dataw_crcr_converter_demux $1\main_sdphy_dataw_crcr_converter_demux[2:0] + end + attribute \src "ls180.v:1194.5-1194.54" + process $proc$ls180.v:1194$3262 + assign { } { } + assign $1\main_sdphy_dataw_crcr_converter_strobe_all[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_crcr_converter_strobe_all $1\main_sdphy_dataw_crcr_converter_strobe_all[0:0] + end + attribute \src "ls180.v:120.5-120.65" + process $proc$ls180.v:120$2777 + assign { } { } + assign $1\main_libresocsim_libresoc_constraintmanager0_uart0_tx[0:0] 1'1 + sync always + sync init + update \main_libresocsim_libresoc_constraintmanager0_uart0_tx $1\main_libresocsim_libresoc_constraintmanager0_uart0_tx[0:0] + end + attribute \src "ls180.v:1205.5-1205.50" + process $proc$ls180.v:1205$3263 + assign { } { } + assign $1\main_sdphy_dataw_crcr_buf_source_valid[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_crcr_buf_source_valid $1\main_sdphy_dataw_crcr_buf_source_valid[0:0] + end + attribute \src "ls180.v:1207.5-1207.50" + process $proc$ls180.v:1207$3264 + assign { } { } + assign $1\main_sdphy_dataw_crcr_buf_source_first[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_crcr_buf_source_first $1\main_sdphy_dataw_crcr_buf_source_first[0:0] + end + attribute \src "ls180.v:1208.5-1208.49" + process $proc$ls180.v:1208$3265 + assign { } { } + assign $1\main_sdphy_dataw_crcr_buf_source_last[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_crcr_buf_source_last $1\main_sdphy_dataw_crcr_buf_source_last[0:0] + end + attribute \src "ls180.v:1209.11-1209.63" + process $proc$ls180.v:1209$3266 + assign { } { } + assign $1\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_dataw_crcr_buf_source_payload_data $1\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] + end + attribute \src "ls180.v:1210.5-1210.39" + process $proc$ls180.v:1210$3267 + assign { } { } + assign $1\main_sdphy_dataw_crcr_reset[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_crcr_reset $1\main_sdphy_dataw_crcr_reset[0:0] + end + attribute \src "ls180.v:1213.5-1213.50" + process $proc$ls180.v:1213$3268 + assign { } { } + assign $0\main_sdphy_datar_pads_in_pads_in_first[0:0] 1'0 + sync always + update \main_sdphy_datar_pads_in_pads_in_first $0\main_sdphy_datar_pads_in_pads_in_first[0:0] + sync init + end + attribute \src "ls180.v:1214.5-1214.49" + process $proc$ls180.v:1214$3269 + assign { } { } + assign $0\main_sdphy_datar_pads_in_pads_in_last[0:0] 1'0 + sync always + update \main_sdphy_datar_pads_in_pads_in_last $0\main_sdphy_datar_pads_in_pads_in_last[0:0] + sync init + end + attribute \src "ls180.v:1215.5-1215.56" + process $proc$ls180.v:1215$3270 + assign { } { } + assign $0\main_sdphy_datar_pads_in_pads_in_payload_clk[0:0] 1'0 + sync always + update \main_sdphy_datar_pads_in_pads_in_payload_clk $0\main_sdphy_datar_pads_in_pads_in_payload_clk[0:0] + sync init + end + attribute \src "ls180.v:1217.5-1217.58" + process $proc$ls180.v:1217$3271 + assign { } { } + assign $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_o[0:0] 1'0 + sync always + update \main_sdphy_datar_pads_in_pads_in_payload_cmd_o $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_o[0:0] + sync init + end + attribute \src "ls180.v:1218.5-1218.59" + process $proc$ls180.v:1218$3272 + assign { } { } + assign $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_oe[0:0] 1'0 + sync always + update \main_sdphy_datar_pads_in_pads_in_payload_cmd_oe $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_oe[0:0] + sync init + end + attribute \src "ls180.v:1220.11-1220.65" + process $proc$ls180.v:1220$3273 + assign { } { } + assign $0\main_sdphy_datar_pads_in_pads_in_payload_data_o[3:0] 4'0000 + sync always + update \main_sdphy_datar_pads_in_pads_in_payload_data_o $0\main_sdphy_datar_pads_in_pads_in_payload_data_o[3:0] + sync init + end + attribute \src "ls180.v:1221.5-1221.60" + process $proc$ls180.v:1221$3274 + assign { } { } + assign $0\main_sdphy_datar_pads_in_pads_in_payload_data_oe[0:0] 1'0 + sync always + update \main_sdphy_datar_pads_in_pads_in_payload_data_oe $0\main_sdphy_datar_pads_in_pads_in_payload_data_oe[0:0] + sync init + end + attribute \src "ls180.v:1223.5-1223.49" + process $proc$ls180.v:1223$3275 + assign { } { } + assign $1\main_sdphy_datar_pads_out_payload_clk[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_pads_out_payload_clk $1\main_sdphy_datar_pads_out_payload_clk[0:0] + end + attribute \src "ls180.v:1224.5-1224.51" + process $proc$ls180.v:1224$3276 + assign { } { } + assign $0\main_sdphy_datar_pads_out_payload_cmd_o[0:0] 1'0 + sync always + update \main_sdphy_datar_pads_out_payload_cmd_o $0\main_sdphy_datar_pads_out_payload_cmd_o[0:0] + sync init + end + attribute \src "ls180.v:1225.5-1225.52" + process $proc$ls180.v:1225$3277 + assign { } { } + assign $0\main_sdphy_datar_pads_out_payload_cmd_oe[0:0] 1'0 + sync always + update \main_sdphy_datar_pads_out_payload_cmd_oe $0\main_sdphy_datar_pads_out_payload_cmd_oe[0:0] + sync init + end + attribute \src "ls180.v:1226.11-1226.58" + process $proc$ls180.v:1226$3278 + assign { } { } + assign $0\main_sdphy_datar_pads_out_payload_data_o[3:0] 4'0000 + sync always + update \main_sdphy_datar_pads_out_payload_data_o $0\main_sdphy_datar_pads_out_payload_data_o[3:0] + sync init + end + attribute \src "ls180.v:1227.5-1227.53" + process $proc$ls180.v:1227$3279 + assign { } { } + assign $0\main_sdphy_datar_pads_out_payload_data_oe[0:0] 1'0 + sync always + update \main_sdphy_datar_pads_out_payload_data_oe $0\main_sdphy_datar_pads_out_payload_data_oe[0:0] + sync init + end + attribute \src "ls180.v:1228.5-1228.39" + process $proc$ls180.v:1228$3280 + assign { } { } + assign $1\main_sdphy_datar_sink_valid[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_sink_valid $1\main_sdphy_datar_sink_valid[0:0] + end + attribute \src "ls180.v:1229.5-1229.39" + process $proc$ls180.v:1229$3281 + assign { } { } + assign $1\main_sdphy_datar_sink_ready[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_sink_ready $1\main_sdphy_datar_sink_ready[0:0] + end + attribute \src "ls180.v:1230.5-1230.38" + process $proc$ls180.v:1230$3282 + assign { } { } + assign $1\main_sdphy_datar_sink_last[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_sink_last $1\main_sdphy_datar_sink_last[0:0] + end + attribute \src "ls180.v:1231.11-1231.61" + process $proc$ls180.v:1231$3283 + assign { } { } + assign $1\main_sdphy_datar_sink_payload_block_length[9:0] 10'0000000000 + sync always + sync init + update \main_sdphy_datar_sink_payload_block_length $1\main_sdphy_datar_sink_payload_block_length[9:0] + end + attribute \src "ls180.v:1232.5-1232.41" + process $proc$ls180.v:1232$3284 + assign { } { } + assign $1\main_sdphy_datar_source_valid[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_source_valid $1\main_sdphy_datar_source_valid[0:0] + end + attribute \src "ls180.v:1233.5-1233.41" + process $proc$ls180.v:1233$3285 + assign { } { } + assign $1\main_sdphy_datar_source_ready[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_source_ready $1\main_sdphy_datar_source_ready[0:0] + end + attribute \src "ls180.v:1234.5-1234.41" + process $proc$ls180.v:1234$3286 + assign { } { } + assign $0\main_sdphy_datar_source_first[0:0] 1'0 + sync always + update \main_sdphy_datar_source_first $0\main_sdphy_datar_source_first[0:0] + sync init + end + attribute \src "ls180.v:1235.5-1235.40" + process $proc$ls180.v:1235$3287 + assign { } { } + assign $1\main_sdphy_datar_source_last[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_source_last $1\main_sdphy_datar_source_last[0:0] + end + attribute \src "ls180.v:1236.11-1236.54" + process $proc$ls180.v:1236$3288 + assign { } { } + assign $1\main_sdphy_datar_source_payload_data[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_datar_source_payload_data $1\main_sdphy_datar_source_payload_data[7:0] + end + attribute \src "ls180.v:1237.11-1237.56" + process $proc$ls180.v:1237$3289 + assign { } { } + assign $1\main_sdphy_datar_source_payload_status[2:0] 3'000 + sync always + sync init + update \main_sdphy_datar_source_payload_status $1\main_sdphy_datar_source_payload_status[2:0] + end + attribute \src "ls180.v:1238.5-1238.33" + process $proc$ls180.v:1238$3290 + assign { } { } + assign $1\main_sdphy_datar_stop[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_stop $1\main_sdphy_datar_stop[0:0] + end + attribute \src "ls180.v:1239.12-1239.49" + process $proc$ls180.v:1239$3291 + assign { } { } + assign $1\main_sdphy_datar_timeout[31:0] 500000 + sync always + sync init + update \main_sdphy_datar_timeout $1\main_sdphy_datar_timeout[31:0] + end + attribute \src "ls180.v:1240.11-1240.41" + process $proc$ls180.v:1240$3292 + assign { } { } + assign $1\main_sdphy_datar_count[9:0] 10'0000000000 + sync always + sync init + update \main_sdphy_datar_count $1\main_sdphy_datar_count[9:0] + end + attribute \src "ls180.v:1242.5-1242.48" + process $proc$ls180.v:1242$3293 + assign { } { } + assign $0\main_sdphy_datar_datar_pads_in_ready[0:0] 1'0 + sync always + update \main_sdphy_datar_datar_pads_in_ready $0\main_sdphy_datar_datar_pads_in_ready[0:0] + sync init + end + attribute \src "ls180.v:1253.5-1253.55" + process $proc$ls180.v:1253$3294 + assign { } { } + assign $1\main_sdphy_datar_datar_source_source_ready0[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_datar_source_source_ready0 $1\main_sdphy_datar_datar_source_source_ready0[0:0] + end + attribute \src "ls180.v:1258.5-1258.38" + process $proc$ls180.v:1258$3295 + assign { } { } + assign $1\main_sdphy_datar_datar_run[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_datar_run $1\main_sdphy_datar_datar_run[0:0] + end + attribute \src "ls180.v:1261.5-1261.55" + process $proc$ls180.v:1261$3296 + assign { } { } + assign $0\main_sdphy_datar_datar_converter_sink_first[0:0] 1'0 + sync always + update \main_sdphy_datar_datar_converter_sink_first $0\main_sdphy_datar_datar_converter_sink_first[0:0] + sync init + end + attribute \src "ls180.v:1262.5-1262.54" + process $proc$ls180.v:1262$3297 + assign { } { } + assign $0\main_sdphy_datar_datar_converter_sink_last[0:0] 1'0 + sync always + update \main_sdphy_datar_datar_converter_sink_last $0\main_sdphy_datar_datar_converter_sink_last[0:0] + sync init + end + attribute \src "ls180.v:1266.5-1266.57" + process $proc$ls180.v:1266$3298 + assign { } { } + assign $1\main_sdphy_datar_datar_converter_source_first[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_datar_converter_source_first $1\main_sdphy_datar_datar_converter_source_first[0:0] + end + attribute \src "ls180.v:1267.5-1267.56" + process $proc$ls180.v:1267$3299 + assign { } { } + assign $1\main_sdphy_datar_datar_converter_source_last[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_datar_converter_source_last $1\main_sdphy_datar_datar_converter_source_last[0:0] + end + attribute \src "ls180.v:1268.11-1268.70" + process $proc$ls180.v:1268$3300 + assign { } { } + assign $1\main_sdphy_datar_datar_converter_source_payload_data[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_datar_datar_converter_source_payload_data $1\main_sdphy_datar_datar_converter_source_payload_data[7:0] + end + attribute \src "ls180.v:1269.11-1269.83" + process $proc$ls180.v:1269$3301 + assign { } { } + assign $1\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] 2'00 + sync always + sync init + update \main_sdphy_datar_datar_converter_source_payload_valid_token_count $1\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] + end + attribute \src "ls180.v:1270.5-1270.50" + process $proc$ls180.v:1270$3302 + assign { } { } + assign $1\main_sdphy_datar_datar_converter_demux[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_datar_converter_demux $1\main_sdphy_datar_datar_converter_demux[0:0] + end + attribute \src "ls180.v:1272.5-1272.55" + process $proc$ls180.v:1272$3303 + assign { } { } + assign $1\main_sdphy_datar_datar_converter_strobe_all[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_datar_converter_strobe_all $1\main_sdphy_datar_datar_converter_strobe_all[0:0] + end + attribute \src "ls180.v:1283.5-1283.51" + process $proc$ls180.v:1283$3304 + assign { } { } + assign $1\main_sdphy_datar_datar_buf_source_valid[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_datar_buf_source_valid $1\main_sdphy_datar_datar_buf_source_valid[0:0] + end + attribute \src "ls180.v:1285.5-1285.51" + process $proc$ls180.v:1285$3305 + assign { } { } + assign $1\main_sdphy_datar_datar_buf_source_first[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_datar_buf_source_first $1\main_sdphy_datar_datar_buf_source_first[0:0] + end + attribute \src "ls180.v:1286.5-1286.50" + process $proc$ls180.v:1286$3306 + assign { } { } + assign $1\main_sdphy_datar_datar_buf_source_last[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_datar_buf_source_last $1\main_sdphy_datar_datar_buf_source_last[0:0] + end + attribute \src "ls180.v:1287.11-1287.64" + process $proc$ls180.v:1287$3307 + assign { } { } + assign $1\main_sdphy_datar_datar_buf_source_payload_data[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_datar_datar_buf_source_payload_data $1\main_sdphy_datar_datar_buf_source_payload_data[7:0] + end + attribute \src "ls180.v:1288.5-1288.40" + process $proc$ls180.v:1288$3308 + assign { } { } + assign $1\main_sdphy_datar_datar_reset[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_datar_reset $1\main_sdphy_datar_datar_reset[0:0] + end + attribute \src "ls180.v:1290.5-1290.35" + process $proc$ls180.v:1290$3309 + assign { } { } + assign $1\main_sdphy_sdpads_cmd_i[0:0] 1'0 + sync always + sync init + update \main_sdphy_sdpads_cmd_i $1\main_sdphy_sdpads_cmd_i[0:0] + end + attribute \src "ls180.v:1293.11-1293.42" + process $proc$ls180.v:1293$3310 + assign { } { } + assign $1\main_sdphy_sdpads_data_i[3:0] 4'0000 + sync always + sync init + update \main_sdphy_sdpads_data_i $1\main_sdphy_sdpads_data_i[3:0] + end + attribute \src "ls180.v:130.12-130.71" + process $proc$ls180.v:130$2778 + assign { } { } + assign $1\main_libresocsim_interface0_converted_interface_adr[29:0] 30'000000000000000000000000000000 + sync always + sync init + update \main_libresocsim_interface0_converted_interface_adr $1\main_libresocsim_interface0_converted_interface_adr[29:0] + end + attribute \src "ls180.v:1306.12-1306.52" + process $proc$ls180.v:1306$3311 + assign { } { } + assign $1\main_sdcore_cmd_argument_storage[31:0] 0 + sync always + sync init + update \main_sdcore_cmd_argument_storage $1\main_sdcore_cmd_argument_storage[31:0] + end + attribute \src "ls180.v:1307.5-1307.39" + process $proc$ls180.v:1307$3312 + assign { } { } + assign $1\main_sdcore_cmd_argument_re[0:0] 1'0 + sync always + sync init + update \main_sdcore_cmd_argument_re $1\main_sdcore_cmd_argument_re[0:0] + end + attribute \src "ls180.v:1308.12-1308.51" + process $proc$ls180.v:1308$3313 + assign { } { } + assign $1\main_sdcore_cmd_command_storage[31:0] 0 + sync always + sync init + update \main_sdcore_cmd_command_storage $1\main_sdcore_cmd_command_storage[31:0] + end + attribute \src "ls180.v:1309.5-1309.38" + process $proc$ls180.v:1309$3314 + assign { } { } + assign $1\main_sdcore_cmd_command_re[0:0] 1'0 + sync always + sync init + update \main_sdcore_cmd_command_re $1\main_sdcore_cmd_command_re[0:0] + end + attribute \src "ls180.v:131.12-131.73" + process $proc$ls180.v:131$2779 + assign { } { } + assign $1\main_libresocsim_interface0_converted_interface_dat_w[31:0] 0 + sync always + sync init + update \main_libresocsim_interface0_converted_interface_dat_w $1\main_libresocsim_interface0_converted_interface_dat_w[31:0] + end + attribute \src "ls180.v:1313.5-1313.34" + process $proc$ls180.v:1313$3315 + assign { } { } + assign $0\main_sdcore_cmd_send_w[0:0] 1'0 + sync always + update \main_sdcore_cmd_send_w $0\main_sdcore_cmd_send_w[0:0] + sync init + end + attribute \src "ls180.v:1314.13-1314.53" + process $proc$ls180.v:1314$3316 + assign { } { } + assign $1\main_sdcore_cmd_response_status[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \main_sdcore_cmd_response_status $1\main_sdcore_cmd_response_status[127:0] + end + attribute \src "ls180.v:1320.11-1320.51" + process $proc$ls180.v:1320$3317 + assign { } { } + assign $1\main_sdcore_block_length_storage[9:0] 10'0000000000 + sync always + sync init + update \main_sdcore_block_length_storage $1\main_sdcore_block_length_storage[9:0] + end + attribute \src "ls180.v:1321.5-1321.39" + process $proc$ls180.v:1321$3318 + assign { } { } + assign $1\main_sdcore_block_length_re[0:0] 1'0 + sync always + sync init + update \main_sdcore_block_length_re $1\main_sdcore_block_length_re[0:0] + end + attribute \src "ls180.v:1322.12-1322.51" + process $proc$ls180.v:1322$3319 + assign { } { } + assign $1\main_sdcore_block_count_storage[31:0] 0 + sync always + sync init + update \main_sdcore_block_count_storage $1\main_sdcore_block_count_storage[31:0] + end + attribute \src "ls180.v:1323.5-1323.38" + process $proc$ls180.v:1323$3320 + assign { } { } + assign $1\main_sdcore_block_count_re[0:0] 1'0 + sync always + sync init + update \main_sdcore_block_count_re $1\main_sdcore_block_count_re[0:0] + end + attribute \src "ls180.v:1324.11-1324.51" + process $proc$ls180.v:1324$3321 + assign { } { } + assign $1\main_sdcore_crc7_inserter_crcreg0[6:0] 7'0000000 + sync always + sync init + update \main_sdcore_crc7_inserter_crcreg0 $1\main_sdcore_crc7_inserter_crcreg0[6:0] + end + attribute \src "ls180.v:133.11-133.69" + process $proc$ls180.v:133$2780 + assign { } { } + assign $1\main_libresocsim_interface0_converted_interface_sel[3:0] 4'0000 + sync always + sync init + update \main_libresocsim_interface0_converted_interface_sel $1\main_libresocsim_interface0_converted_interface_sel[3:0] + end + attribute \src "ls180.v:134.5-134.63" + process $proc$ls180.v:134$2781 + assign { } { } + assign $1\main_libresocsim_interface0_converted_interface_cyc[0:0] 1'0 + sync always + sync init + update \main_libresocsim_interface0_converted_interface_cyc $1\main_libresocsim_interface0_converted_interface_cyc[0:0] + end + attribute \src "ls180.v:135.5-135.63" + process $proc$ls180.v:135$2782 + assign { } { } + assign $1\main_libresocsim_interface0_converted_interface_stb[0:0] 1'0 + sync always + sync init + update \main_libresocsim_interface0_converted_interface_stb $1\main_libresocsim_interface0_converted_interface_stb[0:0] + end + attribute \src "ls180.v:1366.11-1366.47" + process $proc$ls180.v:1366$3322 + assign { } { } + assign $1\main_sdcore_crc7_inserter_crc[6:0] 7'0000000 + sync always + sync init + update \main_sdcore_crc7_inserter_crc $1\main_sdcore_crc7_inserter_crc[6:0] + end + attribute \src "ls180.v:137.5-137.62" + process $proc$ls180.v:137$2783 + assign { } { } + assign $1\main_libresocsim_interface0_converted_interface_we[0:0] 1'0 + sync always + sync init + update \main_libresocsim_interface0_converted_interface_we $1\main_libresocsim_interface0_converted_interface_we[0:0] + end + attribute \src "ls180.v:1370.5-1370.49" + process $proc$ls180.v:1370$3323 + assign { } { } + assign $1\main_sdcore_crc16_inserter_sink_ready[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_inserter_sink_ready $1\main_sdcore_crc16_inserter_sink_ready[0:0] + end + attribute \src "ls180.v:1374.5-1374.51" + process $proc$ls180.v:1374$3324 + assign { } { } + assign $1\main_sdcore_crc16_inserter_source_valid[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_inserter_source_valid $1\main_sdcore_crc16_inserter_source_valid[0:0] + end + attribute \src "ls180.v:1375.5-1375.51" + process $proc$ls180.v:1375$3325 + assign { } { } + assign $1\main_sdcore_crc16_inserter_source_ready[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_inserter_source_ready $1\main_sdcore_crc16_inserter_source_ready[0:0] + end + attribute \src "ls180.v:1376.5-1376.51" + process $proc$ls180.v:1376$3326 + assign { } { } + assign $0\main_sdcore_crc16_inserter_source_first[0:0] 1'0 + sync always + update \main_sdcore_crc16_inserter_source_first $0\main_sdcore_crc16_inserter_source_first[0:0] + sync init + end + attribute \src "ls180.v:1377.5-1377.50" + process $proc$ls180.v:1377$3327 + assign { } { } + assign $1\main_sdcore_crc16_inserter_source_last[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_inserter_source_last $1\main_sdcore_crc16_inserter_source_last[0:0] + end + attribute \src "ls180.v:1378.11-1378.64" + process $proc$ls180.v:1378$3328 + assign { } { } + assign $1\main_sdcore_crc16_inserter_source_payload_data[7:0] 8'00000000 + sync always + sync init + update \main_sdcore_crc16_inserter_source_payload_data $1\main_sdcore_crc16_inserter_source_payload_data[7:0] + end + attribute \src "ls180.v:1379.11-1379.48" + process $proc$ls180.v:1379$3329 + assign { } { } + assign $1\main_sdcore_crc16_inserter_cnt[2:0] 3'000 + sync always + sync init + update \main_sdcore_crc16_inserter_cnt $1\main_sdcore_crc16_inserter_cnt[2:0] + end + attribute \src "ls180.v:138.11-138.69" + process $proc$ls180.v:138$2784 + assign { } { } + assign $0\main_libresocsim_interface0_converted_interface_cti[2:0] 3'000 + sync always + update \main_libresocsim_interface0_converted_interface_cti $0\main_libresocsim_interface0_converted_interface_cti[2:0] + sync init + end + attribute \src "ls180.v:1380.12-1380.59" + process $proc$ls180.v:1380$3330 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_inserter_crc0_crcreg0 $1\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] + end + attribute \src "ls180.v:1384.12-1384.55" + process $proc$ls180.v:1384$3331 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crc0_crc[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_inserter_crc0_crc $1\main_sdcore_crc16_inserter_crc0_crc[15:0] + end + attribute \src "ls180.v:1387.12-1387.59" + process $proc$ls180.v:1387$3332 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_inserter_crc1_crcreg0 $1\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] + end + attribute \src "ls180.v:139.11-139.69" + process $proc$ls180.v:139$2785 + assign { } { } + assign $0\main_libresocsim_interface0_converted_interface_bte[1:0] 2'00 + sync always + update \main_libresocsim_interface0_converted_interface_bte $0\main_libresocsim_interface0_converted_interface_bte[1:0] + sync init + end + attribute \src "ls180.v:1391.12-1391.55" + process $proc$ls180.v:1391$3333 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crc1_crc[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_inserter_crc1_crc $1\main_sdcore_crc16_inserter_crc1_crc[15:0] + end + attribute \src "ls180.v:1394.12-1394.59" + process $proc$ls180.v:1394$3334 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_inserter_crc2_crcreg0 $1\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] + end + attribute \src "ls180.v:1398.12-1398.55" + process $proc$ls180.v:1398$3335 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crc2_crc[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_inserter_crc2_crc $1\main_sdcore_crc16_inserter_crc2_crc[15:0] + end + attribute \src "ls180.v:1401.12-1401.59" + process $proc$ls180.v:1401$3336 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_inserter_crc3_crcreg0 $1\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] + end + attribute \src "ls180.v:1405.12-1405.55" + process $proc$ls180.v:1405$3337 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crc3_crc[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_inserter_crc3_crc $1\main_sdcore_crc16_inserter_crc3_crc[15:0] + end + attribute \src "ls180.v:1408.12-1408.54" + process $proc$ls180.v:1408$3338 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crctmp0[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_inserter_crctmp0 $1\main_sdcore_crc16_inserter_crctmp0[15:0] + end + attribute \src "ls180.v:1409.12-1409.54" + process $proc$ls180.v:1409$3339 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crctmp1[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_inserter_crctmp1 $1\main_sdcore_crc16_inserter_crctmp1[15:0] + end + attribute \src "ls180.v:141.5-141.44" + process $proc$ls180.v:141$2786 + assign { } { } + assign $1\main_libresocsim_converter0_skip[0:0] 1'0 + sync always + sync init + update \main_libresocsim_converter0_skip $1\main_libresocsim_converter0_skip[0:0] + end + attribute \src "ls180.v:1410.12-1410.54" + process $proc$ls180.v:1410$3340 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crctmp2[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_inserter_crctmp2 $1\main_sdcore_crc16_inserter_crctmp2[15:0] + end + attribute \src "ls180.v:1411.12-1411.54" + process $proc$ls180.v:1411$3341 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crctmp3[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_inserter_crctmp3 $1\main_sdcore_crc16_inserter_crctmp3[15:0] + end + attribute \src "ls180.v:1412.5-1412.48" + process $proc$ls180.v:1412$3342 + assign { } { } + assign $1\main_sdcore_crc16_checker_sink_valid[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_checker_sink_valid $1\main_sdcore_crc16_checker_sink_valid[0:0] + end + attribute \src "ls180.v:1413.5-1413.48" + process $proc$ls180.v:1413$3343 + assign { } { } + assign $1\main_sdcore_crc16_checker_sink_ready[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_checker_sink_ready $1\main_sdcore_crc16_checker_sink_ready[0:0] + end + attribute \src "ls180.v:1414.5-1414.48" + process $proc$ls180.v:1414$3344 + assign { } { } + assign $1\main_sdcore_crc16_checker_sink_first[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_checker_sink_first $1\main_sdcore_crc16_checker_sink_first[0:0] + end + attribute \src "ls180.v:1415.5-1415.47" + process $proc$ls180.v:1415$3345 + assign { } { } + assign $1\main_sdcore_crc16_checker_sink_last[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_checker_sink_last $1\main_sdcore_crc16_checker_sink_last[0:0] + end + attribute \src "ls180.v:1416.11-1416.61" + process $proc$ls180.v:1416$3346 + assign { } { } + assign $1\main_sdcore_crc16_checker_sink_payload_data[7:0] 8'00000000 + sync always + sync init + update \main_sdcore_crc16_checker_sink_payload_data $1\main_sdcore_crc16_checker_sink_payload_data[7:0] + end + attribute \src "ls180.v:1417.5-1417.50" + process $proc$ls180.v:1417$3347 + assign { } { } + assign $1\main_sdcore_crc16_checker_source_valid[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_checker_source_valid $1\main_sdcore_crc16_checker_source_valid[0:0] + end + attribute \src "ls180.v:1419.5-1419.50" + process $proc$ls180.v:1419$3348 + assign { } { } + assign $0\main_sdcore_crc16_checker_source_first[0:0] 1'0 + sync always + update \main_sdcore_crc16_checker_source_first $0\main_sdcore_crc16_checker_source_first[0:0] + sync init + end + attribute \src "ls180.v:142.5-142.47" + process $proc$ls180.v:142$2787 + assign { } { } + assign $1\main_libresocsim_converter0_counter[0:0] 1'0 + sync always + sync init + update \main_libresocsim_converter0_counter $1\main_libresocsim_converter0_counter[0:0] + end + attribute \src "ls180.v:1422.11-1422.47" + process $proc$ls180.v:1422$3349 + assign { } { } + assign $1\main_sdcore_crc16_checker_val[7:0] 8'00000000 + sync always + sync init + update \main_sdcore_crc16_checker_val $1\main_sdcore_crc16_checker_val[7:0] + end + attribute \src "ls180.v:1423.11-1423.47" + process $proc$ls180.v:1423$3350 + assign { } { } + assign $1\main_sdcore_crc16_checker_cnt[3:0] 4'0000 + sync always + sync init + update \main_sdcore_crc16_checker_cnt $1\main_sdcore_crc16_checker_cnt[3:0] + end + attribute \src "ls180.v:1424.12-1424.58" + process $proc$ls180.v:1424$3351 + assign { } { } + assign $1\main_sdcore_crc16_checker_crc0_crcreg0[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_checker_crc0_crcreg0 $1\main_sdcore_crc16_checker_crc0_crcreg0[15:0] + end + attribute \src "ls180.v:1428.12-1428.54" + process $proc$ls180.v:1428$3352 + assign { } { } + assign $1\main_sdcore_crc16_checker_crc0_crc[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_checker_crc0_crc $1\main_sdcore_crc16_checker_crc0_crc[15:0] + end + attribute \src "ls180.v:1429.5-1429.46" + process $proc$ls180.v:1429$3353 + assign { } { } + assign $1\main_sdcore_crc16_checker_crc0_clr[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_checker_crc0_clr $1\main_sdcore_crc16_checker_crc0_clr[0:0] + end + attribute \src "ls180.v:1431.12-1431.58" + process $proc$ls180.v:1431$3354 + assign { } { } + assign $1\main_sdcore_crc16_checker_crc1_crcreg0[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_checker_crc1_crcreg0 $1\main_sdcore_crc16_checker_crc1_crcreg0[15:0] + end + attribute \src "ls180.v:1435.12-1435.54" + process $proc$ls180.v:1435$3355 + assign { } { } + assign $1\main_sdcore_crc16_checker_crc1_crc[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_checker_crc1_crc $1\main_sdcore_crc16_checker_crc1_crc[15:0] + end + attribute \src "ls180.v:1436.5-1436.46" + process $proc$ls180.v:1436$3356 + assign { } { } + assign $1\main_sdcore_crc16_checker_crc1_clr[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_checker_crc1_clr $1\main_sdcore_crc16_checker_crc1_clr[0:0] + end + attribute \src "ls180.v:1438.12-1438.58" + process $proc$ls180.v:1438$3357 + assign { } { } + assign $1\main_sdcore_crc16_checker_crc2_crcreg0[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_checker_crc2_crcreg0 $1\main_sdcore_crc16_checker_crc2_crcreg0[15:0] + end + attribute \src "ls180.v:144.12-144.53" + process $proc$ls180.v:144$2788 + assign { } { } + assign $1\main_libresocsim_converter0_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \main_libresocsim_converter0_dat_r $1\main_libresocsim_converter0_dat_r[63:0] + end + attribute \src "ls180.v:1442.12-1442.54" + process $proc$ls180.v:1442$3358 + assign { } { } + assign $1\main_sdcore_crc16_checker_crc2_crc[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_checker_crc2_crc $1\main_sdcore_crc16_checker_crc2_crc[15:0] + end + attribute \src "ls180.v:1443.5-1443.46" + process $proc$ls180.v:1443$3359 + assign { } { } + assign $1\main_sdcore_crc16_checker_crc2_clr[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_checker_crc2_clr $1\main_sdcore_crc16_checker_crc2_clr[0:0] + end + attribute \src "ls180.v:1445.12-1445.58" + process $proc$ls180.v:1445$3360 + assign { } { } + assign $1\main_sdcore_crc16_checker_crc3_crcreg0[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_checker_crc3_crcreg0 $1\main_sdcore_crc16_checker_crc3_crcreg0[15:0] + end + attribute \src "ls180.v:1449.12-1449.54" + process $proc$ls180.v:1449$3361 + assign { } { } + assign $1\main_sdcore_crc16_checker_crc3_crc[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_checker_crc3_crc $1\main_sdcore_crc16_checker_crc3_crc[15:0] + end + attribute \src "ls180.v:145.12-145.71" + process $proc$ls180.v:145$2789 + assign { } { } + assign $1\main_libresocsim_interface1_converted_interface_adr[29:0] 30'000000000000000000000000000000 + sync always + sync init + update \main_libresocsim_interface1_converted_interface_adr $1\main_libresocsim_interface1_converted_interface_adr[29:0] + end + attribute \src "ls180.v:1450.5-1450.46" + process $proc$ls180.v:1450$3362 + assign { } { } + assign $1\main_sdcore_crc16_checker_crc3_clr[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_checker_crc3_clr $1\main_sdcore_crc16_checker_crc3_clr[0:0] + end + attribute \src "ls180.v:1452.12-1452.53" + process $proc$ls180.v:1452$3363 + assign { } { } + assign $1\main_sdcore_crc16_checker_crctmp0[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_checker_crctmp0 $1\main_sdcore_crc16_checker_crctmp0[15:0] + end + attribute \src "ls180.v:1453.12-1453.53" + process $proc$ls180.v:1453$3364 + assign { } { } + assign $1\main_sdcore_crc16_checker_crctmp1[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_checker_crctmp1 $1\main_sdcore_crc16_checker_crctmp1[15:0] + end + attribute \src "ls180.v:1454.12-1454.53" + process $proc$ls180.v:1454$3365 + assign { } { } + assign $1\main_sdcore_crc16_checker_crctmp2[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_checker_crctmp2 $1\main_sdcore_crc16_checker_crctmp2[15:0] + end + attribute \src "ls180.v:1455.12-1455.53" + process $proc$ls180.v:1455$3366 + assign { } { } + assign $1\main_sdcore_crc16_checker_crctmp3[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_checker_crctmp3 $1\main_sdcore_crc16_checker_crctmp3[15:0] + end + attribute \src "ls180.v:1456.5-1456.43" + process $proc$ls180.v:1456$3367 + assign { } { } + assign $1\main_sdcore_crc16_checker_valid[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_checker_valid $1\main_sdcore_crc16_checker_valid[0:0] + end + attribute \src "ls180.v:1457.12-1457.51" + process $proc$ls180.v:1457$3368 + assign { } { } + assign $1\main_sdcore_crc16_checker_fifo0[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_checker_fifo0 $1\main_sdcore_crc16_checker_fifo0[15:0] + end + attribute \src "ls180.v:1458.12-1458.51" + process $proc$ls180.v:1458$3369 + assign { } { } + assign $1\main_sdcore_crc16_checker_fifo1[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_checker_fifo1 $1\main_sdcore_crc16_checker_fifo1[15:0] + end + attribute \src "ls180.v:1459.12-1459.51" + process $proc$ls180.v:1459$3370 + assign { } { } + assign $1\main_sdcore_crc16_checker_fifo2[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_checker_fifo2 $1\main_sdcore_crc16_checker_fifo2[15:0] + end + attribute \src "ls180.v:146.12-146.73" + process $proc$ls180.v:146$2790 + assign { } { } + assign $1\main_libresocsim_interface1_converted_interface_dat_w[31:0] 0 + sync always + sync init + update \main_libresocsim_interface1_converted_interface_dat_w $1\main_libresocsim_interface1_converted_interface_dat_w[31:0] + end + attribute \src "ls180.v:1460.12-1460.51" + process $proc$ls180.v:1460$3371 + assign { } { } + assign $1\main_sdcore_crc16_checker_fifo3[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_checker_fifo3 $1\main_sdcore_crc16_checker_fifo3[15:0] + end + attribute \src "ls180.v:1462.11-1462.39" + process $proc$ls180.v:1462$3372 + assign { } { } + assign $1\main_sdcore_cmd_count[2:0] 3'000 + sync always + sync init + update \main_sdcore_cmd_count $1\main_sdcore_cmd_count[2:0] + end + attribute \src "ls180.v:1463.5-1463.32" + process $proc$ls180.v:1463$3373 + assign { } { } + assign $1\main_sdcore_cmd_done[0:0] 1'0 + sync always + sync init + update \main_sdcore_cmd_done $1\main_sdcore_cmd_done[0:0] + end + attribute \src "ls180.v:1464.5-1464.33" + process $proc$ls180.v:1464$3374 + assign { } { } + assign $1\main_sdcore_cmd_error[0:0] 1'0 + sync always + sync init + update \main_sdcore_cmd_error $1\main_sdcore_cmd_error[0:0] + end + attribute \src "ls180.v:1465.5-1465.35" + process $proc$ls180.v:1465$3375 + assign { } { } + assign $1\main_sdcore_cmd_timeout[0:0] 1'0 + sync always + sync init + update \main_sdcore_cmd_timeout $1\main_sdcore_cmd_timeout[0:0] + end + attribute \src "ls180.v:1467.12-1467.42" + process $proc$ls180.v:1467$3376 + assign { } { } + assign $1\main_sdcore_data_count[31:0] 0 + sync always + sync init + update \main_sdcore_data_count $1\main_sdcore_data_count[31:0] + end + attribute \src "ls180.v:1468.5-1468.33" + process $proc$ls180.v:1468$3377 + assign { } { } + assign $1\main_sdcore_data_done[0:0] 1'0 + sync always + sync init + update \main_sdcore_data_done $1\main_sdcore_data_done[0:0] + end + attribute \src "ls180.v:1469.5-1469.34" + process $proc$ls180.v:1469$3378 + assign { } { } + assign $1\main_sdcore_data_error[0:0] 1'0 + sync always + sync init + update \main_sdcore_data_error $1\main_sdcore_data_error[0:0] + end + attribute \src "ls180.v:1470.5-1470.36" + process $proc$ls180.v:1470$3379 + assign { } { } + assign $1\main_sdcore_data_timeout[0:0] 1'0 + sync always + sync init + update \main_sdcore_data_timeout $1\main_sdcore_data_timeout[0:0] + end + attribute \src "ls180.v:1479.11-1479.41" + process $proc$ls180.v:1479$3380 + assign { } { } + assign $0\main_interface0_bus_cti[2:0] 3'000 + sync always + update \main_interface0_bus_cti $0\main_interface0_bus_cti[2:0] + sync init + end + attribute \src "ls180.v:148.11-148.69" + process $proc$ls180.v:148$2791 + assign { } { } + assign $1\main_libresocsim_interface1_converted_interface_sel[3:0] 4'0000 + sync always + sync init + update \main_libresocsim_interface1_converted_interface_sel $1\main_libresocsim_interface1_converted_interface_sel[3:0] + end + attribute \src "ls180.v:1480.11-1480.41" + process $proc$ls180.v:1480$3381 + assign { } { } + assign $0\main_interface0_bus_bte[1:0] 2'00 + sync always + update \main_interface0_bus_bte $0\main_interface0_bus_bte[1:0] + sync init + end + attribute \src "ls180.v:149.5-149.63" + process $proc$ls180.v:149$2792 + assign { } { } + assign $1\main_libresocsim_interface1_converted_interface_cyc[0:0] 1'0 + sync always + sync init + update \main_libresocsim_interface1_converted_interface_cyc $1\main_libresocsim_interface1_converted_interface_cyc[0:0] + end + attribute \src "ls180.v:150.5-150.63" + process $proc$ls180.v:150$2793 + assign { } { } + assign $1\main_libresocsim_interface1_converted_interface_stb[0:0] 1'0 + sync always + sync init + update \main_libresocsim_interface1_converted_interface_stb $1\main_libresocsim_interface1_converted_interface_stb[0:0] + end + attribute \src "ls180.v:1503.11-1503.45" + process $proc$ls180.v:1503$3382 + assign { } { } + assign $1\main_sdblock2mem_fifo_level[5:0] 6'000000 + sync always + sync init + update \main_sdblock2mem_fifo_level $1\main_sdblock2mem_fifo_level[5:0] + end + attribute \src "ls180.v:1504.5-1504.41" + process $proc$ls180.v:1504$3383 + assign { } { } + assign $0\main_sdblock2mem_fifo_replace[0:0] 1'0 + sync always + update \main_sdblock2mem_fifo_replace $0\main_sdblock2mem_fifo_replace[0:0] + sync init + end + attribute \src "ls180.v:1505.11-1505.47" + process $proc$ls180.v:1505$3384 + assign { } { } + assign $1\main_sdblock2mem_fifo_produce[4:0] 5'00000 + sync always + sync init + update \main_sdblock2mem_fifo_produce $1\main_sdblock2mem_fifo_produce[4:0] + end + attribute \src "ls180.v:1506.11-1506.47" + process $proc$ls180.v:1506$3385 + assign { } { } + assign $1\main_sdblock2mem_fifo_consume[4:0] 5'00000 + sync always + sync init + update \main_sdblock2mem_fifo_consume $1\main_sdblock2mem_fifo_consume[4:0] + end + attribute \src "ls180.v:1507.11-1507.50" + process $proc$ls180.v:1507$3386 + assign { } { } + assign $1\main_sdblock2mem_fifo_wrport_adr[4:0] 5'00000 + sync always + sync init + update \main_sdblock2mem_fifo_wrport_adr $1\main_sdblock2mem_fifo_wrport_adr[4:0] + end + attribute \src "ls180.v:152.5-152.62" + process $proc$ls180.v:152$2794 + assign { } { } + assign $1\main_libresocsim_interface1_converted_interface_we[0:0] 1'0 + sync always + sync init + update \main_libresocsim_interface1_converted_interface_we $1\main_libresocsim_interface1_converted_interface_we[0:0] + end + attribute \src "ls180.v:1527.5-1527.51" + process $proc$ls180.v:1527$3387 + assign { } { } + assign $1\main_sdblock2mem_converter_source_first[0:0] 1'0 + sync always + sync init + update \main_sdblock2mem_converter_source_first $1\main_sdblock2mem_converter_source_first[0:0] + end + attribute \src "ls180.v:1528.5-1528.50" + process $proc$ls180.v:1528$3388 + assign { } { } + assign $1\main_sdblock2mem_converter_source_last[0:0] 1'0 + sync always + sync init + update \main_sdblock2mem_converter_source_last $1\main_sdblock2mem_converter_source_last[0:0] + end + attribute \src "ls180.v:1529.12-1529.66" + process $proc$ls180.v:1529$3389 + assign { } { } + assign $1\main_sdblock2mem_converter_source_payload_data[31:0] 0 + sync always + sync init + update \main_sdblock2mem_converter_source_payload_data $1\main_sdblock2mem_converter_source_payload_data[31:0] + end + attribute \src "ls180.v:153.11-153.69" + process $proc$ls180.v:153$2795 + assign { } { } + assign $0\main_libresocsim_interface1_converted_interface_cti[2:0] 3'000 + sync always + update \main_libresocsim_interface1_converted_interface_cti $0\main_libresocsim_interface1_converted_interface_cti[2:0] + sync init + end + attribute \src "ls180.v:1530.11-1530.77" + process $proc$ls180.v:1530$3390 + assign { } { } + assign $1\main_sdblock2mem_converter_source_payload_valid_token_count[2:0] 3'000 + sync always + sync init + update \main_sdblock2mem_converter_source_payload_valid_token_count $1\main_sdblock2mem_converter_source_payload_valid_token_count[2:0] + end + attribute \src "ls180.v:1531.11-1531.50" + process $proc$ls180.v:1531$3391 + assign { } { } + assign $1\main_sdblock2mem_converter_demux[1:0] 2'00 + sync always + sync init + update \main_sdblock2mem_converter_demux $1\main_sdblock2mem_converter_demux[1:0] + end + attribute \src "ls180.v:1533.5-1533.49" + process $proc$ls180.v:1533$3392 + assign { } { } + assign $1\main_sdblock2mem_converter_strobe_all[0:0] 1'0 + sync always + sync init + update \main_sdblock2mem_converter_strobe_all $1\main_sdblock2mem_converter_strobe_all[0:0] + end + attribute \src "ls180.v:1539.5-1539.45" + process $proc$ls180.v:1539$3393 + assign { } { } + assign $1\main_sdblock2mem_sink_sink_valid1[0:0] 1'0 + sync always + sync init + update \main_sdblock2mem_sink_sink_valid1 $1\main_sdblock2mem_sink_sink_valid1[0:0] + end + attribute \src "ls180.v:154.11-154.69" + process $proc$ls180.v:154$2796 + assign { } { } + assign $0\main_libresocsim_interface1_converted_interface_bte[1:0] 2'00 + sync always + update \main_libresocsim_interface1_converted_interface_bte $0\main_libresocsim_interface1_converted_interface_bte[1:0] + sync init + end + attribute \src "ls180.v:1541.12-1541.62" + process $proc$ls180.v:1541$3394 + assign { } { } + assign $1\main_sdblock2mem_sink_sink_payload_address[31:0] 0 + sync always + sync init + update \main_sdblock2mem_sink_sink_payload_address $1\main_sdblock2mem_sink_sink_payload_address[31:0] + end + attribute \src "ls180.v:1542.12-1542.60" + process $proc$ls180.v:1542$3395 + assign { } { } + assign $1\main_sdblock2mem_sink_sink_payload_data1[31:0] 0 + sync always + sync init + update \main_sdblock2mem_sink_sink_payload_data1 $1\main_sdblock2mem_sink_sink_payload_data1[31:0] + end + attribute \src "ls180.v:1544.5-1544.57" + process $proc$ls180.v:1544$3396 + assign { } { } + assign $1\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] 1'0 + sync always + sync init + update \main_sdblock2mem_wishbonedmawriter_sink_ready $1\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] + end + attribute \src "ls180.v:1548.12-1548.67" + process $proc$ls180.v:1548$3397 + assign { } { } + assign $1\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \main_sdblock2mem_wishbonedmawriter_base_storage $1\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] + end + attribute \src "ls180.v:1549.5-1549.54" + process $proc$ls180.v:1549$3398 + assign { } { } + assign $1\main_sdblock2mem_wishbonedmawriter_base_re[0:0] 1'0 + sync always + sync init + update \main_sdblock2mem_wishbonedmawriter_base_re $1\main_sdblock2mem_wishbonedmawriter_base_re[0:0] + end + attribute \src "ls180.v:1550.12-1550.69" + process $proc$ls180.v:1550$3399 + assign { } { } + assign $1\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] 0 + sync always + sync init + update \main_sdblock2mem_wishbonedmawriter_length_storage $1\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] + end + attribute \src "ls180.v:1551.5-1551.56" + process $proc$ls180.v:1551$3400 + assign { } { } + assign $1\main_sdblock2mem_wishbonedmawriter_length_re[0:0] 1'0 + sync always + sync init + update \main_sdblock2mem_wishbonedmawriter_length_re $1\main_sdblock2mem_wishbonedmawriter_length_re[0:0] + end + attribute \src "ls180.v:1552.5-1552.61" + process $proc$ls180.v:1552$3401 + assign { } { } + assign $1\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] 1'0 + sync always + sync init + update \main_sdblock2mem_wishbonedmawriter_enable_storage $1\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] + end + attribute \src "ls180.v:1553.5-1553.56" + process $proc$ls180.v:1553$3402 + assign { } { } + assign $1\main_sdblock2mem_wishbonedmawriter_enable_re[0:0] 1'0 + sync always + sync init + update \main_sdblock2mem_wishbonedmawriter_enable_re $1\main_sdblock2mem_wishbonedmawriter_enable_re[0:0] + end + attribute \src "ls180.v:1554.5-1554.53" + process $proc$ls180.v:1554$3403 + assign { } { } + assign $1\main_sdblock2mem_wishbonedmawriter_status[0:0] 1'0 + sync always + sync init + update \main_sdblock2mem_wishbonedmawriter_status $1\main_sdblock2mem_wishbonedmawriter_status[0:0] + end + attribute \src "ls180.v:1556.5-1556.59" + process $proc$ls180.v:1556$3404 + assign { } { } + assign $1\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] 1'0 + sync always + sync init + update \main_sdblock2mem_wishbonedmawriter_loop_storage $1\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] + end + attribute \src "ls180.v:1557.5-1557.54" + process $proc$ls180.v:1557$3405 + assign { } { } + assign $1\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] 1'0 + sync always + sync init + update \main_sdblock2mem_wishbonedmawriter_loop_re $1\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] + end + attribute \src "ls180.v:1559.12-1559.61" + process $proc$ls180.v:1559$3406 + assign { } { } + assign $1\main_sdblock2mem_wishbonedmawriter_offset[31:0] 0 + sync always + sync init + update \main_sdblock2mem_wishbonedmawriter_offset $1\main_sdblock2mem_wishbonedmawriter_offset[31:0] + end + attribute \src "ls180.v:156.5-156.44" + process $proc$ls180.v:156$2797 + assign { } { } + assign $1\main_libresocsim_converter1_skip[0:0] 1'0 + sync always + sync init + update \main_libresocsim_converter1_skip $1\main_libresocsim_converter1_skip[0:0] + end + attribute \src "ls180.v:1562.12-1562.43" + process $proc$ls180.v:1562$3407 + assign { } { } + assign $1\main_interface1_bus_adr[31:0] 0 + sync always + sync init + update \main_interface1_bus_adr $1\main_interface1_bus_adr[31:0] + end + attribute \src "ls180.v:1563.12-1563.45" + process $proc$ls180.v:1563$3408 + assign { } { } + assign $0\main_interface1_bus_dat_w[31:0] 0 + sync always + update \main_interface1_bus_dat_w $0\main_interface1_bus_dat_w[31:0] + sync init + end + attribute \src "ls180.v:1565.11-1565.41" + process $proc$ls180.v:1565$3409 + assign { } { } + assign $1\main_interface1_bus_sel[3:0] 4'0000 + sync always + sync init + update \main_interface1_bus_sel $1\main_interface1_bus_sel[3:0] + end + attribute \src "ls180.v:1566.5-1566.35" + process $proc$ls180.v:1566$3410 + assign { } { } + assign $1\main_interface1_bus_cyc[0:0] 1'0 + sync always + sync init + update \main_interface1_bus_cyc $1\main_interface1_bus_cyc[0:0] + end + attribute \src "ls180.v:1567.5-1567.35" + process $proc$ls180.v:1567$3411 + assign { } { } + assign $1\main_interface1_bus_stb[0:0] 1'0 + sync always + sync init + update \main_interface1_bus_stb $1\main_interface1_bus_stb[0:0] + end + attribute \src "ls180.v:1569.5-1569.34" + process $proc$ls180.v:1569$3412 + assign { } { } + assign $1\main_interface1_bus_we[0:0] 1'0 + sync always + sync init + update \main_interface1_bus_we $1\main_interface1_bus_we[0:0] + end + attribute \src "ls180.v:157.5-157.47" + process $proc$ls180.v:157$2798 + assign { } { } + assign $1\main_libresocsim_converter1_counter[0:0] 1'0 + sync always + sync init + update \main_libresocsim_converter1_counter $1\main_libresocsim_converter1_counter[0:0] + end + attribute \src "ls180.v:1570.11-1570.41" + process $proc$ls180.v:1570$3413 + assign { } { } + assign $0\main_interface1_bus_cti[2:0] 3'000 + sync always + update \main_interface1_bus_cti $0\main_interface1_bus_cti[2:0] + sync init + end + attribute \src "ls180.v:1571.11-1571.41" + process $proc$ls180.v:1571$3414 + assign { } { } + assign $0\main_interface1_bus_bte[1:0] 2'00 + sync always + update \main_interface1_bus_bte $0\main_interface1_bus_bte[1:0] + sync init + end + attribute \src "ls180.v:1578.5-1578.43" + process $proc$ls180.v:1578$3415 + assign { } { } + assign $1\main_sdmem2block_dma_sink_valid[0:0] 1'0 + sync always + sync init + update \main_sdmem2block_dma_sink_valid $1\main_sdmem2block_dma_sink_valid[0:0] + end + attribute \src "ls180.v:1579.5-1579.43" + process $proc$ls180.v:1579$3416 + assign { } { } + assign $1\main_sdmem2block_dma_sink_ready[0:0] 1'0 + sync always + sync init + update \main_sdmem2block_dma_sink_ready $1\main_sdmem2block_dma_sink_ready[0:0] + end + attribute \src "ls180.v:1580.5-1580.42" + process $proc$ls180.v:1580$3417 + assign { } { } + assign $1\main_sdmem2block_dma_sink_last[0:0] 1'0 + sync always + sync init + update \main_sdmem2block_dma_sink_last $1\main_sdmem2block_dma_sink_last[0:0] + end + attribute \src "ls180.v:1581.12-1581.61" + process $proc$ls180.v:1581$3418 + assign { } { } + assign $1\main_sdmem2block_dma_sink_payload_address[31:0] 0 + sync always + sync init + update \main_sdmem2block_dma_sink_payload_address $1\main_sdmem2block_dma_sink_payload_address[31:0] + end + attribute \src "ls180.v:1582.5-1582.45" + process $proc$ls180.v:1582$3419 + assign { } { } + assign $1\main_sdmem2block_dma_source_valid[0:0] 1'0 + sync always + sync init + update \main_sdmem2block_dma_source_valid $1\main_sdmem2block_dma_source_valid[0:0] + end + attribute \src "ls180.v:1584.5-1584.45" + process $proc$ls180.v:1584$3420 + assign { } { } + assign $0\main_sdmem2block_dma_source_first[0:0] 1'0 + sync always + update \main_sdmem2block_dma_source_first $0\main_sdmem2block_dma_source_first[0:0] + sync init + end + attribute \src "ls180.v:1585.5-1585.44" + process $proc$ls180.v:1585$3421 + assign { } { } + assign $1\main_sdmem2block_dma_source_last[0:0] 1'0 + sync always + sync init + update \main_sdmem2block_dma_source_last $1\main_sdmem2block_dma_source_last[0:0] + end + attribute \src "ls180.v:1586.12-1586.60" + process $proc$ls180.v:1586$3422 + assign { } { } + assign $1\main_sdmem2block_dma_source_payload_data[31:0] 0 + sync always + sync init + update \main_sdmem2block_dma_source_payload_data $1\main_sdmem2block_dma_source_payload_data[31:0] + end + attribute \src "ls180.v:1587.12-1587.45" + process $proc$ls180.v:1587$3423 + assign { } { } + assign $1\main_sdmem2block_dma_data[31:0] 0 + sync always + sync init + update \main_sdmem2block_dma_data $1\main_sdmem2block_dma_data[31:0] + end + attribute \src "ls180.v:1588.12-1588.53" + process $proc$ls180.v:1588$3424 + assign { } { } + assign $1\main_sdmem2block_dma_base_storage[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \main_sdmem2block_dma_base_storage $1\main_sdmem2block_dma_base_storage[63:0] + end + attribute \src "ls180.v:1589.5-1589.40" + process $proc$ls180.v:1589$3425 + assign { } { } + assign $1\main_sdmem2block_dma_base_re[0:0] 1'0 + sync always + sync init + update \main_sdmem2block_dma_base_re $1\main_sdmem2block_dma_base_re[0:0] + end + attribute \src "ls180.v:159.12-159.53" + process $proc$ls180.v:159$2799 + assign { } { } + assign $1\main_libresocsim_converter1_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \main_libresocsim_converter1_dat_r $1\main_libresocsim_converter1_dat_r[63:0] + end + attribute \src "ls180.v:1590.12-1590.55" + process $proc$ls180.v:1590$3426 + assign { } { } + assign $1\main_sdmem2block_dma_length_storage[31:0] 0 + sync always + sync init + update \main_sdmem2block_dma_length_storage $1\main_sdmem2block_dma_length_storage[31:0] + end + attribute \src "ls180.v:1591.5-1591.42" + process $proc$ls180.v:1591$3427 + assign { } { } + assign $1\main_sdmem2block_dma_length_re[0:0] 1'0 + sync always + sync init + update \main_sdmem2block_dma_length_re $1\main_sdmem2block_dma_length_re[0:0] + end + attribute \src "ls180.v:1592.5-1592.47" + process $proc$ls180.v:1592$3428 + assign { } { } + assign $1\main_sdmem2block_dma_enable_storage[0:0] 1'0 + sync always + sync init + update \main_sdmem2block_dma_enable_storage $1\main_sdmem2block_dma_enable_storage[0:0] + end + attribute \src "ls180.v:1593.5-1593.42" + process $proc$ls180.v:1593$3429 + assign { } { } + assign $1\main_sdmem2block_dma_enable_re[0:0] 1'0 + sync always + sync init + update \main_sdmem2block_dma_enable_re $1\main_sdmem2block_dma_enable_re[0:0] + end + attribute \src "ls180.v:1594.5-1594.44" + process $proc$ls180.v:1594$3430 + assign { } { } + assign $1\main_sdmem2block_dma_done_status[0:0] 1'0 + sync always + sync init + update \main_sdmem2block_dma_done_status $1\main_sdmem2block_dma_done_status[0:0] + end + attribute \src "ls180.v:1596.5-1596.45" + process $proc$ls180.v:1596$3431 + assign { } { } + assign $1\main_sdmem2block_dma_loop_storage[0:0] 1'0 + sync always + sync init + update \main_sdmem2block_dma_loop_storage $1\main_sdmem2block_dma_loop_storage[0:0] + end + attribute \src "ls180.v:1597.5-1597.40" + process $proc$ls180.v:1597$3432 + assign { } { } + assign $1\main_sdmem2block_dma_loop_re[0:0] 1'0 + sync always + sync init + update \main_sdmem2block_dma_loop_re $1\main_sdmem2block_dma_loop_re[0:0] + end + attribute \src "ls180.v:160.12-160.71" + process $proc$ls180.v:160$2800 + assign { } { } + assign $1\main_libresocsim_interface2_converted_interface_adr[29:0] 30'000000000000000000000000000000 + sync always + sync init + update \main_libresocsim_interface2_converted_interface_adr $1\main_libresocsim_interface2_converted_interface_adr[29:0] + end + attribute \src "ls180.v:1601.12-1601.47" + process $proc$ls180.v:1601$3433 + assign { } { } + assign $1\main_sdmem2block_dma_offset[31:0] 0 + sync always + sync init + update \main_sdmem2block_dma_offset $1\main_sdmem2block_dma_offset[31:0] + end + attribute \src "ls180.v:161.12-161.73" + process $proc$ls180.v:161$2801 + assign { } { } + assign $1\main_libresocsim_interface2_converted_interface_dat_w[31:0] 0 + sync always + sync init + update \main_libresocsim_interface2_converted_interface_dat_w $1\main_libresocsim_interface2_converted_interface_dat_w[31:0] + end + attribute \src "ls180.v:1613.11-1613.64" + process $proc$ls180.v:1613$3434 + assign { } { } + assign $1\main_sdmem2block_converter_source_payload_data[7:0] 8'00000000 + sync always + sync init + update \main_sdmem2block_converter_source_payload_data $1\main_sdmem2block_converter_source_payload_data[7:0] + end + attribute \src "ls180.v:1615.11-1615.48" + process $proc$ls180.v:1615$3435 + assign { } { } + assign $1\main_sdmem2block_converter_mux[1:0] 2'00 + sync always + sync init + update \main_sdmem2block_converter_mux $1\main_sdmem2block_converter_mux[1:0] + end + attribute \src "ls180.v:163.11-163.69" + process $proc$ls180.v:163$2802 + assign { } { } + assign $1\main_libresocsim_interface2_converted_interface_sel[3:0] 4'0000 + sync always + sync init + update \main_libresocsim_interface2_converted_interface_sel $1\main_libresocsim_interface2_converted_interface_sel[3:0] + end + attribute \src "ls180.v:1639.11-1639.45" + process $proc$ls180.v:1639$3436 + assign { } { } + assign $1\main_sdmem2block_fifo_level[5:0] 6'000000 + sync always + sync init + update \main_sdmem2block_fifo_level $1\main_sdmem2block_fifo_level[5:0] + end + attribute \src "ls180.v:164.5-164.63" + process $proc$ls180.v:164$2803 + assign { } { } + assign $1\main_libresocsim_interface2_converted_interface_cyc[0:0] 1'0 + sync always + sync init + update \main_libresocsim_interface2_converted_interface_cyc $1\main_libresocsim_interface2_converted_interface_cyc[0:0] + end + attribute \src "ls180.v:1640.5-1640.41" + process $proc$ls180.v:1640$3437 + assign { } { } + assign $0\main_sdmem2block_fifo_replace[0:0] 1'0 + sync always + update \main_sdmem2block_fifo_replace $0\main_sdmem2block_fifo_replace[0:0] + sync init + end + attribute \src "ls180.v:1641.11-1641.47" + process $proc$ls180.v:1641$3438 + assign { } { } + assign $1\main_sdmem2block_fifo_produce[4:0] 5'00000 + sync always + sync init + update \main_sdmem2block_fifo_produce $1\main_sdmem2block_fifo_produce[4:0] + end + attribute \src "ls180.v:1642.11-1642.47" + process $proc$ls180.v:1642$3439 + assign { } { } + assign $1\main_sdmem2block_fifo_consume[4:0] 5'00000 + sync always + sync init + update \main_sdmem2block_fifo_consume $1\main_sdmem2block_fifo_consume[4:0] + end + attribute \src "ls180.v:1643.11-1643.50" + process $proc$ls180.v:1643$3440 + assign { } { } + assign $1\main_sdmem2block_fifo_wrport_adr[4:0] 5'00000 + sync always + sync init + update \main_sdmem2block_fifo_wrport_adr $1\main_sdmem2block_fifo_wrport_adr[4:0] + end + attribute \src "ls180.v:165.5-165.63" + process $proc$ls180.v:165$2804 + assign { } { } + assign $1\main_libresocsim_interface2_converted_interface_stb[0:0] 1'0 + sync always + sync init + update \main_libresocsim_interface2_converted_interface_stb $1\main_libresocsim_interface2_converted_interface_stb[0:0] + end + attribute \src "ls180.v:1658.5-1658.29" + process $proc$ls180.v:1658$3441 + assign { } { } + assign $1\libresocsim_done0[0:0] 1'0 + sync always + sync init + update \libresocsim_done0 $1\libresocsim_done0[0:0] + end + attribute \src "ls180.v:1659.5-1659.27" + process $proc$ls180.v:1659$3442 + assign { } { } + assign $1\libresocsim_irq[0:0] 1'0 + sync always + sync init + update \libresocsim_irq $1\libresocsim_irq[0:0] + end + attribute \src "ls180.v:1661.11-1661.34" + process $proc$ls180.v:1661$3443 + assign { } { } + assign $1\libresocsim_miso[7:0] 8'00000000 + sync always + sync init + update \libresocsim_miso $1\libresocsim_miso[7:0] + end + attribute \src "ls180.v:1665.5-1665.30" + process $proc$ls180.v:1665$3444 + assign { } { } + assign $1\libresocsim_start1[0:0] 1'0 + sync always + sync init + update \libresocsim_start1 $1\libresocsim_start1[0:0] + end + attribute \src "ls180.v:1667.12-1667.47" + process $proc$ls180.v:1667$3445 + assign { } { } + assign $1\libresocsim_control_storage[15:0] 16'0000000000000000 + sync always + sync init + update \libresocsim_control_storage $1\libresocsim_control_storage[15:0] + end + attribute \src "ls180.v:1668.5-1668.34" + process $proc$ls180.v:1668$3446 + assign { } { } + assign $1\libresocsim_control_re[0:0] 1'0 + sync always + sync init + update \libresocsim_control_re $1\libresocsim_control_re[0:0] + end + attribute \src "ls180.v:167.5-167.62" + process $proc$ls180.v:167$2805 + assign { } { } + assign $1\main_libresocsim_interface2_converted_interface_we[0:0] 1'0 + sync always + sync init + update \main_libresocsim_interface2_converted_interface_we $1\main_libresocsim_interface2_converted_interface_we[0:0] + end + attribute \src "ls180.v:1672.11-1672.42" + process $proc$ls180.v:1672$3447 + assign { } { } + assign $1\libresocsim_mosi_storage[7:0] 8'00000000 + sync always + sync init + update \libresocsim_mosi_storage $1\libresocsim_mosi_storage[7:0] + end + attribute \src "ls180.v:1673.5-1673.31" + process $proc$ls180.v:1673$3448 + assign { } { } + assign $1\libresocsim_mosi_re[0:0] 1'0 + sync always + sync init + update \libresocsim_mosi_re $1\libresocsim_mosi_re[0:0] + end + attribute \src "ls180.v:1677.5-1677.34" + process $proc$ls180.v:1677$3449 + assign { } { } + assign $1\libresocsim_cs_storage[0:0] 1'1 + sync always + sync init + update \libresocsim_cs_storage $1\libresocsim_cs_storage[0:0] + end + attribute \src "ls180.v:1678.5-1678.29" + process $proc$ls180.v:1678$3450 + assign { } { } + assign $1\libresocsim_cs_re[0:0] 1'0 + sync always + sync init + update \libresocsim_cs_re $1\libresocsim_cs_re[0:0] + end + attribute \src "ls180.v:1679.5-1679.40" + process $proc$ls180.v:1679$3451 + assign { } { } + assign $1\libresocsim_loopback_storage[0:0] 1'0 + sync always + sync init + update \libresocsim_loopback_storage $1\libresocsim_loopback_storage[0:0] + end + attribute \src "ls180.v:168.11-168.69" + process $proc$ls180.v:168$2806 + assign { } { } + assign $0\main_libresocsim_interface2_converted_interface_cti[2:0] 3'000 + sync always + update \main_libresocsim_interface2_converted_interface_cti $0\main_libresocsim_interface2_converted_interface_cti[2:0] + sync init + end + attribute \src "ls180.v:1680.5-1680.35" + process $proc$ls180.v:1680$3452 + assign { } { } + assign $1\libresocsim_loopback_re[0:0] 1'0 + sync always + sync init + update \libresocsim_loopback_re $1\libresocsim_loopback_re[0:0] + end + attribute \src "ls180.v:1681.5-1681.34" + process $proc$ls180.v:1681$3453 + assign { } { } + assign $1\libresocsim_clk_enable[0:0] 1'0 + sync always + sync init + update \libresocsim_clk_enable $1\libresocsim_clk_enable[0:0] + end + attribute \src "ls180.v:1682.5-1682.33" + process $proc$ls180.v:1682$3454 + assign { } { } + assign $1\libresocsim_cs_enable[0:0] 1'0 + sync always + sync init + update \libresocsim_cs_enable $1\libresocsim_cs_enable[0:0] + end + attribute \src "ls180.v:1683.11-1683.35" + process $proc$ls180.v:1683$3455 + assign { } { } + assign $1\libresocsim_count[2:0] 3'000 + sync always + sync init + update \libresocsim_count $1\libresocsim_count[2:0] + end + attribute \src "ls180.v:1684.5-1684.34" + process $proc$ls180.v:1684$3456 + assign { } { } + assign $1\libresocsim_mosi_latch[0:0] 1'0 + sync always + sync init + update \libresocsim_mosi_latch $1\libresocsim_mosi_latch[0:0] + end + attribute \src "ls180.v:1685.5-1685.34" + process $proc$ls180.v:1685$3457 + assign { } { } + assign $1\libresocsim_miso_latch[0:0] 1'0 + sync always + sync init + update \libresocsim_miso_latch $1\libresocsim_miso_latch[0:0] + end + attribute \src "ls180.v:1686.12-1686.44" + process $proc$ls180.v:1686$3458 + assign { } { } + assign $1\libresocsim_clk_divider1[15:0] 16'0000000000000000 + sync always + sync init + update \libresocsim_clk_divider1 $1\libresocsim_clk_divider1[15:0] + end + attribute \src "ls180.v:1689.11-1689.39" + process $proc$ls180.v:1689$3459 + assign { } { } + assign $1\libresocsim_mosi_data[7:0] 8'00000000 + sync always + sync init + update \libresocsim_mosi_data $1\libresocsim_mosi_data[7:0] + end + attribute \src "ls180.v:169.11-169.69" + process $proc$ls180.v:169$2807 + assign { } { } + assign $0\main_libresocsim_interface2_converted_interface_bte[1:0] 2'00 + sync always + update \main_libresocsim_interface2_converted_interface_bte $0\main_libresocsim_interface2_converted_interface_bte[1:0] + sync init + end + attribute \src "ls180.v:1690.11-1690.38" + process $proc$ls180.v:1690$3460 + assign { } { } + assign $1\libresocsim_mosi_sel[2:0] 3'000 + sync always + sync init + update \libresocsim_mosi_sel $1\libresocsim_mosi_sel[2:0] + end + attribute \src "ls180.v:1691.11-1691.39" + process $proc$ls180.v:1691$3461 + assign { } { } + assign $1\libresocsim_miso_data[7:0] 8'00000000 + sync always + sync init + update \libresocsim_miso_data $1\libresocsim_miso_data[7:0] + end + attribute \src "ls180.v:1692.12-1692.41" + process $proc$ls180.v:1692$3462 + assign { } { } + assign $1\libresocsim_storage[15:0] 16'0000000001111101 + sync always + sync init + update \libresocsim_storage $1\libresocsim_storage[15:0] + end + attribute \src "ls180.v:1693.5-1693.26" + process $proc$ls180.v:1693$3463 + assign { } { } + assign $1\libresocsim_re[0:0] 1'0 + sync always + sync init + update \libresocsim_re $1\libresocsim_re[0:0] + end + attribute \src "ls180.v:1694.5-1694.36" + process $proc$ls180.v:1694$3464 + assign { } { } + assign $1\builder_converter0_state[0:0] 1'0 + sync always + sync init + update \builder_converter0_state $1\builder_converter0_state[0:0] + end + attribute \src "ls180.v:1695.5-1695.41" + process $proc$ls180.v:1695$3465 + assign { } { } + assign $1\builder_converter0_next_state[0:0] 1'0 + sync always + sync init + update \builder_converter0_next_state $1\builder_converter0_next_state[0:0] + end + attribute \src "ls180.v:1696.5-1696.69" + process $proc$ls180.v:1696$3466 + assign { } { } + assign $1\main_libresocsim_converter0_counter_converter0_next_value[0:0] 1'0 + sync always + sync init + update \main_libresocsim_converter0_counter_converter0_next_value $1\main_libresocsim_converter0_counter_converter0_next_value[0:0] + end + attribute \src "ls180.v:1697.5-1697.72" + process $proc$ls180.v:1697$3467 + assign { } { } + assign $1\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0] 1'0 + sync always + sync init + update \main_libresocsim_converter0_counter_converter0_next_value_ce $1\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0] + end + attribute \src "ls180.v:1698.5-1698.36" + process $proc$ls180.v:1698$3468 + assign { } { } + assign $1\builder_converter1_state[0:0] 1'0 + sync always + sync init + update \builder_converter1_state $1\builder_converter1_state[0:0] + end + attribute \src "ls180.v:1699.5-1699.41" + process $proc$ls180.v:1699$3469 + assign { } { } + assign $1\builder_converter1_next_state[0:0] 1'0 + sync always + sync init + update \builder_converter1_next_state $1\builder_converter1_next_state[0:0] + end + attribute \src "ls180.v:1700.5-1700.69" + process $proc$ls180.v:1700$3470 + assign { } { } + assign $1\main_libresocsim_converter1_counter_converter1_next_value[0:0] 1'0 + sync always + sync init + update \main_libresocsim_converter1_counter_converter1_next_value $1\main_libresocsim_converter1_counter_converter1_next_value[0:0] + end + attribute \src "ls180.v:1701.5-1701.72" + process $proc$ls180.v:1701$3471 + assign { } { } + assign $1\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0] 1'0 + sync always + sync init + update \main_libresocsim_converter1_counter_converter1_next_value_ce $1\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0] + end + attribute \src "ls180.v:1702.5-1702.36" + process $proc$ls180.v:1702$3472 + assign { } { } + assign $1\builder_converter2_state[0:0] 1'0 + sync always + sync init + update \builder_converter2_state $1\builder_converter2_state[0:0] + end + attribute \src "ls180.v:1703.5-1703.41" + process $proc$ls180.v:1703$3473 + assign { } { } + assign $1\builder_converter2_next_state[0:0] 1'0 + sync always + sync init + update \builder_converter2_next_state $1\builder_converter2_next_state[0:0] + end + attribute \src "ls180.v:1704.5-1704.69" + process $proc$ls180.v:1704$3474 + assign { } { } + assign $1\main_libresocsim_converter2_counter_converter2_next_value[0:0] 1'0 + sync always + sync init + update \main_libresocsim_converter2_counter_converter2_next_value $1\main_libresocsim_converter2_counter_converter2_next_value[0:0] + end + attribute \src "ls180.v:1705.5-1705.72" + process $proc$ls180.v:1705$3475 + assign { } { } + assign $1\main_libresocsim_converter2_counter_converter2_next_value_ce[0:0] 1'0 + sync always + sync init + update \main_libresocsim_converter2_counter_converter2_next_value_ce $1\main_libresocsim_converter2_counter_converter2_next_value_ce[0:0] + end + attribute \src "ls180.v:1706.11-1706.41" + process $proc$ls180.v:1706$3476 + assign { } { } + assign $1\builder_refresher_state[1:0] 2'00 + sync always + sync init + update \builder_refresher_state $1\builder_refresher_state[1:0] + end + attribute \src "ls180.v:1707.11-1707.46" + process $proc$ls180.v:1707$3477 + assign { } { } + assign $1\builder_refresher_next_state[1:0] 2'00 + sync always + sync init + update \builder_refresher_next_state $1\builder_refresher_next_state[1:0] + end + attribute \src "ls180.v:1708.11-1708.44" + process $proc$ls180.v:1708$3478 + assign { } { } + assign $1\builder_bankmachine0_state[2:0] 3'000 + sync always + sync init + update \builder_bankmachine0_state $1\builder_bankmachine0_state[2:0] + end + attribute \src "ls180.v:1709.11-1709.49" + process $proc$ls180.v:1709$3479 + assign { } { } + assign $1\builder_bankmachine0_next_state[2:0] 3'000 + sync always + sync init + update \builder_bankmachine0_next_state $1\builder_bankmachine0_next_state[2:0] + end + attribute \src "ls180.v:171.5-171.44" + process $proc$ls180.v:171$2808 + assign { } { } + assign $1\main_libresocsim_converter2_skip[0:0] 1'0 + sync always + sync init + update \main_libresocsim_converter2_skip $1\main_libresocsim_converter2_skip[0:0] + end + attribute \src "ls180.v:1710.11-1710.44" + process $proc$ls180.v:1710$3480 + assign { } { } + assign $1\builder_bankmachine1_state[2:0] 3'000 + sync always + sync init + update \builder_bankmachine1_state $1\builder_bankmachine1_state[2:0] + end + attribute \src "ls180.v:1711.11-1711.49" + process $proc$ls180.v:1711$3481 + assign { } { } + assign $1\builder_bankmachine1_next_state[2:0] 3'000 + sync always + sync init + update \builder_bankmachine1_next_state $1\builder_bankmachine1_next_state[2:0] + end + attribute \src "ls180.v:1712.11-1712.44" + process $proc$ls180.v:1712$3482 + assign { } { } + assign $1\builder_bankmachine2_state[2:0] 3'000 + sync always + sync init + update \builder_bankmachine2_state $1\builder_bankmachine2_state[2:0] + end + attribute \src "ls180.v:1713.11-1713.49" + process $proc$ls180.v:1713$3483 + assign { } { } + assign $1\builder_bankmachine2_next_state[2:0] 3'000 + sync always + sync init + update \builder_bankmachine2_next_state $1\builder_bankmachine2_next_state[2:0] + end + attribute \src "ls180.v:1714.11-1714.44" + process $proc$ls180.v:1714$3484 + assign { } { } + assign $1\builder_bankmachine3_state[2:0] 3'000 + sync always + sync init + update \builder_bankmachine3_state $1\builder_bankmachine3_state[2:0] + end + attribute \src "ls180.v:1715.11-1715.49" + process $proc$ls180.v:1715$3485 + assign { } { } + assign $1\builder_bankmachine3_next_state[2:0] 3'000 + sync always + sync init + update \builder_bankmachine3_next_state $1\builder_bankmachine3_next_state[2:0] + end + attribute \src "ls180.v:1716.11-1716.43" + process $proc$ls180.v:1716$3486 + assign { } { } + assign $1\builder_multiplexer_state[2:0] 3'000 + sync always + sync init + update \builder_multiplexer_state $1\builder_multiplexer_state[2:0] + end + attribute \src "ls180.v:1717.11-1717.48" + process $proc$ls180.v:1717$3487 + assign { } { } + assign $1\builder_multiplexer_next_state[2:0] 3'000 + sync always + sync init + update \builder_multiplexer_next_state $1\builder_multiplexer_next_state[2:0] + end + attribute \src "ls180.v:172.5-172.47" + process $proc$ls180.v:172$2809 + assign { } { } + assign $1\main_libresocsim_converter2_counter[0:0] 1'0 + sync always + sync init + update \main_libresocsim_converter2_counter $1\main_libresocsim_converter2_counter[0:0] + end + attribute \src "ls180.v:1730.5-1730.27" + process $proc$ls180.v:1730$3488 + assign { } { } + assign $0\builder_locked0[0:0] 1'0 + sync always + update \builder_locked0 $0\builder_locked0[0:0] + sync init + end + attribute \src "ls180.v:1731.5-1731.27" + process $proc$ls180.v:1731$3489 + assign { } { } + assign $0\builder_locked1[0:0] 1'0 + sync always + update \builder_locked1 $0\builder_locked1[0:0] + sync init + end + attribute \src "ls180.v:1732.5-1732.27" + process $proc$ls180.v:1732$3490 + assign { } { } + assign $0\builder_locked2[0:0] 1'0 + sync always + update \builder_locked2 $0\builder_locked2[0:0] + sync init + end + attribute \src "ls180.v:1733.5-1733.27" + process $proc$ls180.v:1733$3491 + assign { } { } + assign $0\builder_locked3[0:0] 1'0 + sync always + update \builder_locked3 $0\builder_locked3[0:0] + sync init + end + attribute \src "ls180.v:1734.5-1734.42" + process $proc$ls180.v:1734$3492 + assign { } { } + assign $1\builder_new_master_wdata_ready[0:0] 1'0 + sync always + sync init + update \builder_new_master_wdata_ready $1\builder_new_master_wdata_ready[0:0] + end + attribute \src "ls180.v:1735.5-1735.43" + process $proc$ls180.v:1735$3493 + assign { } { } + assign $1\builder_new_master_rdata_valid0[0:0] 1'0 + sync always + sync init + update \builder_new_master_rdata_valid0 $1\builder_new_master_rdata_valid0[0:0] + end + attribute \src "ls180.v:1736.5-1736.43" + process $proc$ls180.v:1736$3494 + assign { } { } + assign $1\builder_new_master_rdata_valid1[0:0] 1'0 + sync always + sync init + update \builder_new_master_rdata_valid1 $1\builder_new_master_rdata_valid1[0:0] + end + attribute \src "ls180.v:1737.5-1737.43" + process $proc$ls180.v:1737$3495 + assign { } { } + assign $1\builder_new_master_rdata_valid2[0:0] 1'0 + sync always + sync init + update \builder_new_master_rdata_valid2 $1\builder_new_master_rdata_valid2[0:0] + end + attribute \src "ls180.v:1738.5-1738.43" + process $proc$ls180.v:1738$3496 + assign { } { } + assign $1\builder_new_master_rdata_valid3[0:0] 1'0 + sync always + sync init + update \builder_new_master_rdata_valid3 $1\builder_new_master_rdata_valid3[0:0] + end + attribute \src "ls180.v:1739.5-1739.35" + process $proc$ls180.v:1739$3497 + assign { } { } + assign $1\builder_converter_state[0:0] 1'0 + sync always + sync init + update \builder_converter_state $1\builder_converter_state[0:0] + end + attribute \src "ls180.v:174.12-174.53" + process $proc$ls180.v:174$2810 + assign { } { } + assign $1\main_libresocsim_converter2_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \main_libresocsim_converter2_dat_r $1\main_libresocsim_converter2_dat_r[63:0] + end + attribute \src "ls180.v:1740.5-1740.40" + process $proc$ls180.v:1740$3498 + assign { } { } + assign $1\builder_converter_next_state[0:0] 1'0 + sync always + sync init + update \builder_converter_next_state $1\builder_converter_next_state[0:0] + end + attribute \src "ls180.v:1741.5-1741.55" + process $proc$ls180.v:1741$3499 + assign { } { } + assign $1\main_converter_counter_converter_next_value[0:0] 1'0 + sync always + sync init + update \main_converter_counter_converter_next_value $1\main_converter_counter_converter_next_value[0:0] + end + attribute \src "ls180.v:1742.5-1742.58" + process $proc$ls180.v:1742$3500 + assign { } { } + assign $1\main_converter_counter_converter_next_value_ce[0:0] 1'0 + sync always + sync init + update \main_converter_counter_converter_next_value_ce $1\main_converter_counter_converter_next_value_ce[0:0] + end + attribute \src "ls180.v:1743.11-1743.42" + process $proc$ls180.v:1743$3501 + assign { } { } + assign $1\builder_spimaster0_state[1:0] 2'00 + sync always + sync init + update \builder_spimaster0_state $1\builder_spimaster0_state[1:0] + end + attribute \src "ls180.v:1744.11-1744.47" + process $proc$ls180.v:1744$3502 + assign { } { } + assign $1\builder_spimaster0_next_state[1:0] 2'00 + sync always + sync init + update \builder_spimaster0_next_state $1\builder_spimaster0_next_state[1:0] + end + attribute \src "ls180.v:1745.11-1745.61" + process $proc$ls180.v:1745$3503 + assign { } { } + assign $1\main_spi_master_count_spimaster0_next_value[2:0] 3'000 + sync always + sync init + update \main_spi_master_count_spimaster0_next_value $1\main_spi_master_count_spimaster0_next_value[2:0] + end + attribute \src "ls180.v:1746.5-1746.58" + process $proc$ls180.v:1746$3504 + assign { } { } + assign $1\main_spi_master_count_spimaster0_next_value_ce[0:0] 1'0 + sync always + sync init + update \main_spi_master_count_spimaster0_next_value_ce $1\main_spi_master_count_spimaster0_next_value_ce[0:0] + end + attribute \src "ls180.v:1747.5-1747.41" + process $proc$ls180.v:1747$3505 + assign { } { } + assign $1\builder_sdphy_sdphyinit_state[0:0] 1'0 + sync always + sync init + update \builder_sdphy_sdphyinit_state $1\builder_sdphy_sdphyinit_state[0:0] + end + attribute \src "ls180.v:1748.5-1748.46" + process $proc$ls180.v:1748$3506 + assign { } { } + assign $1\builder_sdphy_sdphyinit_next_state[0:0] 1'0 + sync always + sync init + update \builder_sdphy_sdphyinit_next_state $1\builder_sdphy_sdphyinit_next_state[0:0] + end + attribute \src "ls180.v:1749.11-1749.66" + process $proc$ls180.v:1749$3507 + assign { } { } + assign $1\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_init_count_sdphy_sdphyinit_next_value $1\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] + end + attribute \src "ls180.v:1750.5-1750.63" + process $proc$ls180.v:1750$3508 + assign { } { } + assign $1\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] 1'0 + sync always + sync init + update \main_sdphy_init_count_sdphy_sdphyinit_next_value_ce $1\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] + end + attribute \src "ls180.v:1751.11-1751.47" + process $proc$ls180.v:1751$3509 + assign { } { } + assign $1\builder_sdphy_sdphycmdw_state[1:0] 2'00 + sync always + sync init + update \builder_sdphy_sdphycmdw_state $1\builder_sdphy_sdphycmdw_state[1:0] + end + attribute \src "ls180.v:1752.11-1752.52" + process $proc$ls180.v:1752$3510 + assign { } { } + assign $1\builder_sdphy_sdphycmdw_next_state[1:0] 2'00 + sync always + sync init + update \builder_sdphy_sdphycmdw_next_state $1\builder_sdphy_sdphycmdw_next_state[1:0] + end + attribute \src "ls180.v:1753.11-1753.66" + process $proc$ls180.v:1753$3511 + assign { } { } + assign $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] + end + attribute \src "ls180.v:1754.5-1754.63" + process $proc$ls180.v:1754$3512 + assign { } { } + assign $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] + end + attribute \src "ls180.v:1755.11-1755.47" + process $proc$ls180.v:1755$3513 + assign { } { } + assign $1\builder_sdphy_sdphycmdr_state[2:0] 3'000 + sync always + sync init + update \builder_sdphy_sdphycmdr_state $1\builder_sdphy_sdphycmdr_state[2:0] + end + attribute \src "ls180.v:1756.11-1756.52" + process $proc$ls180.v:1756$3514 + assign { } { } + assign $1\builder_sdphy_sdphycmdr_next_state[2:0] 3'000 + sync always + sync init + update \builder_sdphy_sdphycmdr_next_state $1\builder_sdphy_sdphycmdr_next_state[2:0] + end + attribute \src "ls180.v:1757.11-1757.67" + process $proc$ls180.v:1757$3515 + assign { } { } + assign $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0 $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] + end + attribute \src "ls180.v:1758.5-1758.64" + process $proc$ls180.v:1758$3516 + assign { } { } + assign $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0 $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] + end + attribute \src "ls180.v:1759.12-1759.71" + process $proc$ls180.v:1759$3517 + assign { } { } + assign $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] 0 + sync always + sync init + update \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1 $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] + end + attribute \src "ls180.v:1760.5-1760.66" + process $proc$ls180.v:1760$3518 + assign { } { } + assign $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1 $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] + end + attribute \src "ls180.v:1761.5-1761.66" + process $proc$ls180.v:1761$3519 + assign { } { } + assign $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2 $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] + end + attribute \src "ls180.v:1762.5-1762.69" + process $proc$ls180.v:1762$3520 + assign { } { } + assign $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2 $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] + end + attribute \src "ls180.v:1763.5-1763.41" + process $proc$ls180.v:1763$3521 + assign { } { } + assign $1\builder_sdphy_sdphycrcr_state[0:0] 1'0 + sync always + sync init + update \builder_sdphy_sdphycrcr_state $1\builder_sdphy_sdphycrcr_state[0:0] + end + attribute \src "ls180.v:1764.5-1764.46" + process $proc$ls180.v:1764$3522 + assign { } { } + assign $1\builder_sdphy_sdphycrcr_next_state[0:0] 1'0 + sync always + sync init + update \builder_sdphy_sdphycrcr_next_state $1\builder_sdphy_sdphycrcr_next_state[0:0] + end + attribute \src "ls180.v:1765.5-1765.66" + process $proc$ls180.v:1765$3523 + assign { } { } + assign $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] + end + attribute \src "ls180.v:1766.5-1766.69" + process $proc$ls180.v:1766$3524 + assign { } { } + assign $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] + end + attribute \src "ls180.v:1767.11-1767.41" + process $proc$ls180.v:1767$3525 + assign { } { } + assign $1\builder_sdphy_fsm_state[2:0] 3'000 + sync always + sync init + update \builder_sdphy_fsm_state $1\builder_sdphy_fsm_state[2:0] + end + attribute \src "ls180.v:1768.11-1768.46" + process $proc$ls180.v:1768$3526 + assign { } { } + assign $1\builder_sdphy_fsm_next_state[2:0] 3'000 + sync always + sync init + update \builder_sdphy_fsm_next_state $1\builder_sdphy_fsm_next_state[2:0] + end + attribute \src "ls180.v:1769.11-1769.61" + process $proc$ls180.v:1769$3527 + assign { } { } + assign $1\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_dataw_count_sdphy_fsm_next_value $1\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] + end + attribute \src "ls180.v:1770.5-1770.58" + process $proc$ls180.v:1770$3528 + assign { } { } + assign $1\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_count_sdphy_fsm_next_value_ce $1\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] + end + attribute \src "ls180.v:1771.11-1771.48" + process $proc$ls180.v:1771$3529 + assign { } { } + assign $1\builder_sdphy_sdphydatar_state[2:0] 3'000 + sync always + sync init + update \builder_sdphy_sdphydatar_state $1\builder_sdphy_sdphydatar_state[2:0] + end + attribute \src "ls180.v:1772.11-1772.53" + process $proc$ls180.v:1772$3530 + assign { } { } + assign $1\builder_sdphy_sdphydatar_next_state[2:0] 3'000 + sync always + sync init + update \builder_sdphy_sdphydatar_next_state $1\builder_sdphy_sdphydatar_next_state[2:0] + end + attribute \src "ls180.v:1773.11-1773.70" + process $proc$ls180.v:1773$3531 + assign { } { } + assign $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] 10'0000000000 + sync always + sync init + update \main_sdphy_datar_count_sdphy_sdphydatar_next_value0 $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] + end + attribute \src "ls180.v:1774.5-1774.66" + process $proc$ls180.v:1774$3532 + assign { } { } + assign $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0 $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] + end + attribute \src "ls180.v:1775.12-1775.73" + process $proc$ls180.v:1775$3533 + assign { } { } + assign $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] 0 + sync always + sync init + update \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1 $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] + end + attribute \src "ls180.v:1776.5-1776.68" + process $proc$ls180.v:1776$3534 + assign { } { } + assign $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1 $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] + end + attribute \src "ls180.v:1777.5-1777.69" + process $proc$ls180.v:1777$3535 + assign { } { } + assign $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2 $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] + end + attribute \src "ls180.v:1778.5-1778.72" + process $proc$ls180.v:1778$3536 + assign { } { } + assign $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2 $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] + end + attribute \src "ls180.v:1779.5-1779.52" + process $proc$ls180.v:1779$3537 + assign { } { } + assign $1\builder_sdcore_crcupstreaminserter_state[0:0] 1'0 + sync always + sync init + update \builder_sdcore_crcupstreaminserter_state $1\builder_sdcore_crcupstreaminserter_state[0:0] + end + attribute \src "ls180.v:1780.5-1780.57" + process $proc$ls180.v:1780$3538 + assign { } { } + assign $1\builder_sdcore_crcupstreaminserter_next_state[0:0] 1'0 + sync always + sync init + update \builder_sdcore_crcupstreaminserter_next_state $1\builder_sdcore_crcupstreaminserter_next_state[0:0] + end + attribute \src "ls180.v:1781.12-1781.93" + process $proc$ls180.v:1781$3539 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0 $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] + end + attribute \src "ls180.v:1782.5-1782.88" + process $proc$ls180.v:1782$3540 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0 $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] + end + attribute \src "ls180.v:1783.12-1783.93" + process $proc$ls180.v:1783$3541 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1 $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] + end + attribute \src "ls180.v:1784.5-1784.88" + process $proc$ls180.v:1784$3542 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1 $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] + end + attribute \src "ls180.v:1785.12-1785.93" + process $proc$ls180.v:1785$3543 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2 $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] + end + attribute \src "ls180.v:1786.5-1786.88" + process $proc$ls180.v:1786$3544 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2 $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] + end + attribute \src "ls180.v:1787.12-1787.93" + process $proc$ls180.v:1787$3545 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3 $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] + end + attribute \src "ls180.v:1788.5-1788.88" + process $proc$ls180.v:1788$3546 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3 $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] + end + attribute \src "ls180.v:1789.11-1789.87" + process $proc$ls180.v:1789$3547 + assign { } { } + assign $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] 3'000 + sync always + sync init + update \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4 $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] + end + attribute \src "ls180.v:1790.5-1790.84" + process $proc$ls180.v:1790$3548 + assign { } { } + assign $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4 $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] + end + attribute \src "ls180.v:1791.11-1791.42" + process $proc$ls180.v:1791$3549 + assign { } { } + assign $1\builder_sdcore_fsm_state[2:0] 3'000 + sync always + sync init + update \builder_sdcore_fsm_state $1\builder_sdcore_fsm_state[2:0] + end + attribute \src "ls180.v:1792.11-1792.47" + process $proc$ls180.v:1792$3550 + assign { } { } + assign $1\builder_sdcore_fsm_next_state[2:0] 3'000 + sync always + sync init + update \builder_sdcore_fsm_next_state $1\builder_sdcore_fsm_next_state[2:0] + end + attribute \src "ls180.v:1793.5-1793.55" + process $proc$ls180.v:1793$3551 + assign { } { } + assign $1\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] 1'0 + sync always + sync init + update \main_sdcore_cmd_done_sdcore_fsm_next_value0 $1\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] + end + attribute \src "ls180.v:1794.5-1794.58" + process $proc$ls180.v:1794$3552 + assign { } { } + assign $1\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] 1'0 + sync always + sync init + update \main_sdcore_cmd_done_sdcore_fsm_next_value_ce0 $1\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] + end + attribute \src "ls180.v:1795.5-1795.56" + process $proc$ls180.v:1795$3553 + assign { } { } + assign $1\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] 1'0 + sync always + sync init + update \main_sdcore_data_done_sdcore_fsm_next_value1 $1\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] + end + attribute \src "ls180.v:1796.5-1796.59" + process $proc$ls180.v:1796$3554 + assign { } { } + assign $1\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] 1'0 + sync always + sync init + update \main_sdcore_data_done_sdcore_fsm_next_value_ce1 $1\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] + end + attribute \src "ls180.v:1797.11-1797.62" + process $proc$ls180.v:1797$3555 + assign { } { } + assign $1\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] 3'000 + sync always + sync init + update \main_sdcore_cmd_count_sdcore_fsm_next_value2 $1\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] + end + attribute \src "ls180.v:1798.5-1798.59" + process $proc$ls180.v:1798$3556 + assign { } { } + assign $1\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] 1'0 + sync always + sync init + update \main_sdcore_cmd_count_sdcore_fsm_next_value_ce2 $1\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] + end + attribute \src "ls180.v:1799.12-1799.65" + process $proc$ls180.v:1799$3557 + assign { } { } + assign $1\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] 0 + sync always + sync init + update \main_sdcore_data_count_sdcore_fsm_next_value3 $1\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] + end + attribute \src "ls180.v:1800.5-1800.60" + process $proc$ls180.v:1800$3558 + assign { } { } + assign $1\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'0 + sync always + sync init + update \main_sdcore_data_count_sdcore_fsm_next_value_ce3 $1\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] + end + attribute \src "ls180.v:1801.5-1801.56" + process $proc$ls180.v:1801$3559 + assign { } { } + assign $1\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] 1'0 + sync always + sync init + update \main_sdcore_cmd_error_sdcore_fsm_next_value4 $1\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] + end + attribute \src "ls180.v:1802.5-1802.59" + process $proc$ls180.v:1802$3560 + assign { } { } + assign $1\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] 1'0 + sync always + sync init + update \main_sdcore_cmd_error_sdcore_fsm_next_value_ce4 $1\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] + end + attribute \src "ls180.v:1803.5-1803.58" + process $proc$ls180.v:1803$3561 + assign { } { } + assign $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] 1'0 + sync always + sync init + update \main_sdcore_cmd_timeout_sdcore_fsm_next_value5 $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] + end + attribute \src "ls180.v:1804.5-1804.61" + process $proc$ls180.v:1804$3562 + assign { } { } + assign $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] 1'0 + sync always + sync init + update \main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5 $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] + end + attribute \src "ls180.v:1805.5-1805.57" + process $proc$ls180.v:1805$3563 + assign { } { } + assign $1\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] 1'0 + sync always + sync init + update \main_sdcore_data_error_sdcore_fsm_next_value6 $1\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] + end + attribute \src "ls180.v:1806.5-1806.60" + process $proc$ls180.v:1806$3564 + assign { } { } + assign $1\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] 1'0 + sync always + sync init + update \main_sdcore_data_error_sdcore_fsm_next_value_ce6 $1\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] + end + attribute \src "ls180.v:1807.5-1807.59" + process $proc$ls180.v:1807$3565 + assign { } { } + assign $1\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] 1'0 + sync always + sync init + update \main_sdcore_data_timeout_sdcore_fsm_next_value7 $1\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] + end + attribute \src "ls180.v:1808.5-1808.62" + process $proc$ls180.v:1808$3566 + assign { } { } + assign $1\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] 1'0 + sync always + sync init + update \main_sdcore_data_timeout_sdcore_fsm_next_value_ce7 $1\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] + end + attribute \src "ls180.v:1809.13-1809.76" + process $proc$ls180.v:1809$3567 + assign { } { } + assign $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \main_sdcore_cmd_response_status_sdcore_fsm_next_value8 $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] + end + attribute \src "ls180.v:181.5-181.40" + process $proc$ls180.v:181$2811 + assign { } { } + assign $1\main_libresocsim_ram_bus_ack[0:0] 1'0 + sync always + sync init + update \main_libresocsim_ram_bus_ack $1\main_libresocsim_ram_bus_ack[0:0] + end + attribute \src "ls180.v:1810.5-1810.69" + process $proc$ls180.v:1810$3568 + assign { } { } + assign $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] 1'0 + sync always + sync init + update \main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8 $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] + end + attribute \src "ls180.v:1811.11-1811.46" + process $proc$ls180.v:1811$3569 + assign { } { } + assign $1\builder_sdblock2memdma_state[1:0] 2'00 + sync always + sync init + update \builder_sdblock2memdma_state $1\builder_sdblock2memdma_state[1:0] + end + attribute \src "ls180.v:1812.11-1812.51" + process $proc$ls180.v:1812$3570 + assign { } { } + assign $1\builder_sdblock2memdma_next_state[1:0] 2'00 + sync always + sync init + update \builder_sdblock2memdma_next_state $1\builder_sdblock2memdma_next_state[1:0] + end + attribute \src "ls180.v:1813.12-1813.87" + process $proc$ls180.v:1813$3571 + assign { } { } + assign $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] 0 + sync always + sync init + update \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] + end + attribute \src "ls180.v:1814.5-1814.82" + process $proc$ls180.v:1814$3572 + assign { } { } + assign $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] 1'0 + sync always + sync init + update \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] + end + attribute \src "ls180.v:1815.5-1815.44" + process $proc$ls180.v:1815$3573 + assign { } { } + assign $1\builder_sdmem2blockdma_fsm_state[0:0] 1'0 + sync always + sync init + update \builder_sdmem2blockdma_fsm_state $1\builder_sdmem2blockdma_fsm_state[0:0] + end + attribute \src "ls180.v:1816.5-1816.49" + process $proc$ls180.v:1816$3574 + assign { } { } + assign $1\builder_sdmem2blockdma_fsm_next_state[0:0] 1'0 + sync always + sync init + update \builder_sdmem2blockdma_fsm_next_state $1\builder_sdmem2blockdma_fsm_next_state[0:0] + end + attribute \src "ls180.v:1817.12-1817.75" + process $proc$ls180.v:1817$3575 + assign { } { } + assign $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[31:0] 0 + sync always + sync init + update \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[31:0] + end + attribute \src "ls180.v:1818.5-1818.70" + process $proc$ls180.v:1818$3576 + assign { } { } + assign $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] 1'0 + sync always + sync init + update \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] + end + attribute \src "ls180.v:1819.11-1819.60" + process $proc$ls180.v:1819$3577 + assign { } { } + assign $1\builder_sdmem2blockdma_resetinserter_state[1:0] 2'00 + sync always + sync init + update \builder_sdmem2blockdma_resetinserter_state $1\builder_sdmem2blockdma_resetinserter_state[1:0] + end + attribute \src "ls180.v:1820.11-1820.65" + process $proc$ls180.v:1820$3578 + assign { } { } + assign $1\builder_sdmem2blockdma_resetinserter_next_state[1:0] 2'00 + sync always + sync init + update \builder_sdmem2blockdma_resetinserter_next_state $1\builder_sdmem2blockdma_resetinserter_next_state[1:0] + end + attribute \src "ls180.v:1821.12-1821.87" + process $proc$ls180.v:1821$3579 + assign { } { } + assign $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] 0 + sync always + sync init + update \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] + end + attribute \src "ls180.v:1822.5-1822.82" + process $proc$ls180.v:1822$3580 + assign { } { } + assign $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] 1'0 + sync always + sync init + update \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] + end + attribute \src "ls180.v:1823.11-1823.42" + process $proc$ls180.v:1823$3581 + assign { } { } + assign $1\builder_spimaster1_state[1:0] 2'00 + sync always + sync init + update \builder_spimaster1_state $1\builder_spimaster1_state[1:0] + end + attribute \src "ls180.v:1824.11-1824.47" + process $proc$ls180.v:1824$3582 + assign { } { } + assign $1\builder_spimaster1_next_state[1:0] 2'00 + sync always + sync init + update \builder_spimaster1_next_state $1\builder_spimaster1_next_state[1:0] + end + attribute \src "ls180.v:1825.11-1825.57" + process $proc$ls180.v:1825$3583 + assign { } { } + assign $1\libresocsim_count_spimaster1_next_value[2:0] 3'000 + sync always + sync init + update \libresocsim_count_spimaster1_next_value $1\libresocsim_count_spimaster1_next_value[2:0] + end + attribute \src "ls180.v:1826.5-1826.54" + process $proc$ls180.v:1826$3584 + assign { } { } + assign $1\libresocsim_count_spimaster1_next_value_ce[0:0] 1'0 + sync always + sync init + update \libresocsim_count_spimaster1_next_value_ce $1\libresocsim_count_spimaster1_next_value_ce[0:0] + end + attribute \src "ls180.v:1827.12-1827.43" + process $proc$ls180.v:1827$3585 + assign { } { } + assign $1\builder_libresocsim_adr[13:0] 14'00000000000000 + sync always + sync init + update \builder_libresocsim_adr $1\builder_libresocsim_adr[13:0] + end + attribute \src "ls180.v:1828.5-1828.34" + process $proc$ls180.v:1828$3586 + assign { } { } + assign $1\builder_libresocsim_we[0:0] 1'0 + sync always + sync init + update \builder_libresocsim_we $1\builder_libresocsim_we[0:0] + end + attribute \src "ls180.v:1829.11-1829.43" + process $proc$ls180.v:1829$3587 + assign { } { } + assign $1\builder_libresocsim_dat_w[7:0] 8'00000000 + sync always + sync init + update \builder_libresocsim_dat_w $1\builder_libresocsim_dat_w[7:0] + end + attribute \src "ls180.v:1833.12-1833.54" + process $proc$ls180.v:1833$3588 + assign { } { } + assign $1\builder_libresocsim_wishbone_dat_r[31:0] 0 + sync always + sync init + update \builder_libresocsim_wishbone_dat_r $1\builder_libresocsim_wishbone_dat_r[31:0] + end + attribute \src "ls180.v:1837.5-1837.44" + process $proc$ls180.v:1837$3589 + assign { } { } + assign $1\builder_libresocsim_wishbone_ack[0:0] 1'0 + sync always + sync init + update \builder_libresocsim_wishbone_ack $1\builder_libresocsim_wishbone_ack[0:0] + end + attribute \src "ls180.v:1841.5-1841.44" + process $proc$ls180.v:1841$3590 + assign { } { } + assign $0\builder_libresocsim_wishbone_err[0:0] 1'0 + sync always + update \builder_libresocsim_wishbone_err $0\builder_libresocsim_wishbone_err[0:0] + sync init + end + attribute \src "ls180.v:1844.12-1844.40" + process $proc$ls180.v:1844$3591 + assign { } { } + assign $1\builder_shared_dat_r[31:0] 0 + sync always + sync init + update \builder_shared_dat_r $1\builder_shared_dat_r[31:0] + end + attribute \src "ls180.v:1848.5-1848.30" + process $proc$ls180.v:1848$3592 + assign { } { } + assign $1\builder_shared_ack[0:0] 1'0 + sync always + sync init + update \builder_shared_ack $1\builder_shared_ack[0:0] + end + attribute \src "ls180.v:185.5-185.40" + process $proc$ls180.v:185$2812 + assign { } { } + assign $0\main_libresocsim_ram_bus_err[0:0] 1'0 + sync always + update \main_libresocsim_ram_bus_err $0\main_libresocsim_ram_bus_err[0:0] + sync init + end + attribute \src "ls180.v:1854.11-1854.31" + process $proc$ls180.v:1854$3593 + assign { } { } + assign $1\builder_grant[2:0] 3'000 + sync always + sync init + update \builder_grant $1\builder_grant[2:0] + end + attribute \src "ls180.v:1855.11-1855.35" + process $proc$ls180.v:1855$3594 + assign { } { } + assign $1\builder_slave_sel[4:0] 5'00000 + sync always + sync init + update \builder_slave_sel $1\builder_slave_sel[4:0] + end + attribute \src "ls180.v:1856.11-1856.37" + process $proc$ls180.v:1856$3595 + assign { } { } + assign $1\builder_slave_sel_r[4:0] 5'00000 + sync always + sync init + update \builder_slave_sel_r $1\builder_slave_sel_r[4:0] + end + attribute \src "ls180.v:1857.5-1857.25" + process $proc$ls180.v:1857$3596 + assign { } { } + assign $1\builder_error[0:0] 1'0 + sync always + sync init + update \builder_error $1\builder_error[0:0] + end + attribute \src "ls180.v:1860.12-1860.39" + process $proc$ls180.v:1860$3597 + assign { } { } + assign $1\builder_count[19:0] 20'11110100001001000000 + sync always + sync init + update \builder_count $1\builder_count[19:0] + end + attribute \src "ls180.v:1864.11-1864.51" + process $proc$ls180.v:1864$3598 + assign { } { } + assign $1\builder_interface0_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \builder_interface0_bank_bus_dat_r $1\builder_interface0_bank_bus_dat_r[7:0] + end + attribute \src "ls180.v:188.11-188.37" + process $proc$ls180.v:188$2813 + assign { } { } + assign $1\main_libresocsim_we[3:0] 4'0000 + sync always + sync init + update \main_libresocsim_we $1\main_libresocsim_we[3:0] + end + attribute \src "ls180.v:190.12-190.49" + process $proc$ls180.v:190$2814 + assign { } { } + assign $1\main_libresocsim_load_storage[31:0] 0 + sync always + sync init + update \main_libresocsim_load_storage $1\main_libresocsim_load_storage[31:0] + end + attribute \src "ls180.v:1905.11-1905.51" + process $proc$ls180.v:1905$3599 + assign { } { } + assign $1\builder_interface1_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \builder_interface1_bank_bus_dat_r $1\builder_interface1_bank_bus_dat_r[7:0] + end + attribute \src "ls180.v:191.5-191.36" + process $proc$ls180.v:191$2815 + assign { } { } + assign $1\main_libresocsim_load_re[0:0] 1'0 + sync always + sync init + update \main_libresocsim_load_re $1\main_libresocsim_load_re[0:0] + end + attribute \src "ls180.v:192.12-192.51" + process $proc$ls180.v:192$2816 + assign { } { } + assign $1\main_libresocsim_reload_storage[31:0] 0 + sync always + sync init + update \main_libresocsim_reload_storage $1\main_libresocsim_reload_storage[31:0] + end + attribute \src "ls180.v:193.5-193.38" + process $proc$ls180.v:193$2817 + assign { } { } + assign $1\main_libresocsim_reload_re[0:0] 1'0 + sync always + sync init + update \main_libresocsim_reload_re $1\main_libresocsim_reload_re[0:0] + end + attribute \src "ls180.v:1934.11-1934.51" + process $proc$ls180.v:1934$3600 + assign { } { } + assign $1\builder_interface2_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \builder_interface2_bank_bus_dat_r $1\builder_interface2_bank_bus_dat_r[7:0] + end + attribute \src "ls180.v:194.5-194.39" + process $proc$ls180.v:194$2818 + assign { } { } + assign $1\main_libresocsim_en_storage[0:0] 1'0 + sync always + sync init + update \main_libresocsim_en_storage $1\main_libresocsim_en_storage[0:0] + end + attribute \src "ls180.v:195.5-195.34" + process $proc$ls180.v:195$2819 + assign { } { } + assign $1\main_libresocsim_en_re[0:0] 1'0 + sync always + sync init + update \main_libresocsim_en_re $1\main_libresocsim_en_re[0:0] + end + attribute \src "ls180.v:196.5-196.49" + process $proc$ls180.v:196$2820 + assign { } { } + assign $1\main_libresocsim_update_value_storage[0:0] 1'0 + sync always + sync init + update \main_libresocsim_update_value_storage $1\main_libresocsim_update_value_storage[0:0] + end + attribute \src "ls180.v:197.5-197.44" + process $proc$ls180.v:197$2821 + assign { } { } + assign $1\main_libresocsim_update_value_re[0:0] 1'0 + sync always + sync init + update \main_libresocsim_update_value_re $1\main_libresocsim_update_value_re[0:0] + end + attribute \src "ls180.v:1975.11-1975.51" + process $proc$ls180.v:1975$3601 + assign { } { } + assign $1\builder_interface3_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \builder_interface3_bank_bus_dat_r $1\builder_interface3_bank_bus_dat_r[7:0] + end + attribute \src "ls180.v:198.12-198.49" + process $proc$ls180.v:198$2822 + assign { } { } + assign $1\main_libresocsim_value_status[31:0] 0 + sync always + sync init + update \main_libresocsim_value_status $1\main_libresocsim_value_status[31:0] + end + attribute \src "ls180.v:2016.11-2016.51" + process $proc$ls180.v:2016$3602 + assign { } { } + assign $1\builder_interface4_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \builder_interface4_bank_bus_dat_r $1\builder_interface4_bank_bus_dat_r[7:0] + end + attribute \src "ls180.v:202.5-202.41" + process $proc$ls180.v:202$2823 + assign { } { } + assign $1\main_libresocsim_zero_pending[0:0] 1'0 + sync always + sync init + update \main_libresocsim_zero_pending $1\main_libresocsim_zero_pending[0:0] + end + attribute \src "ls180.v:204.5-204.39" + process $proc$ls180.v:204$2824 + assign { } { } + assign $1\main_libresocsim_zero_clear[0:0] 1'0 + sync always + sync init + update \main_libresocsim_zero_clear $1\main_libresocsim_zero_clear[0:0] + end + attribute \src "ls180.v:205.5-205.45" + process $proc$ls180.v:205$2825 + assign { } { } + assign $1\main_libresocsim_zero_old_trigger[0:0] 1'0 + sync always + sync init + update \main_libresocsim_zero_old_trigger $1\main_libresocsim_zero_old_trigger[0:0] + end + attribute \src "ls180.v:2081.11-2081.51" + process $proc$ls180.v:2081$3603 + assign { } { } + assign $1\builder_interface5_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \builder_interface5_bank_bus_dat_r $1\builder_interface5_bank_bus_dat_r[7:0] + end + attribute \src "ls180.v:214.5-214.49" + process $proc$ls180.v:214$2826 + assign { } { } + assign $1\main_libresocsim_eventmanager_storage[0:0] 1'0 + sync always + sync init + update \main_libresocsim_eventmanager_storage $1\main_libresocsim_eventmanager_storage[0:0] + end + attribute \src "ls180.v:215.5-215.44" + process $proc$ls180.v:215$2827 + assign { } { } + assign $1\main_libresocsim_eventmanager_re[0:0] 1'0 + sync always + sync init + update \main_libresocsim_eventmanager_re $1\main_libresocsim_eventmanager_re[0:0] + end + attribute \src "ls180.v:216.12-216.42" + process $proc$ls180.v:216$2828 + assign { } { } + assign $1\main_libresocsim_value[31:0] 0 + sync always + sync init + update \main_libresocsim_value $1\main_libresocsim_value[31:0] + end + attribute \src "ls180.v:220.5-220.24" + process $proc$ls180.v:220$2829 + assign { } { } + assign $1\main_int_rst[0:0] 1'1 + sync always + sync init + update \main_int_rst $1\main_int_rst[0:0] + end + attribute \src "ls180.v:2214.11-2214.51" + process $proc$ls180.v:2214$3604 + assign { } { } + assign $1\builder_interface6_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \builder_interface6_bank_bus_dat_r $1\builder_interface6_bank_bus_dat_r[7:0] + end + attribute \src "ls180.v:2295.11-2295.51" + process $proc$ls180.v:2295$3605 + assign { } { } + assign $1\builder_interface7_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \builder_interface7_bank_bus_dat_r $1\builder_interface7_bank_bus_dat_r[7:0] + end + attribute \src "ls180.v:2312.11-2312.51" + process $proc$ls180.v:2312$3606 + assign { } { } + assign $1\builder_interface8_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \builder_interface8_bank_bus_dat_r $1\builder_interface8_bank_bus_dat_r[7:0] + end + attribute \src "ls180.v:235.12-235.38" + process $proc$ls180.v:235$2830 + assign { } { } + assign $1\main_dfi_p0_rddata[15:0] 16'0000000000000000 + sync always + sync init + update \main_dfi_p0_rddata $1\main_dfi_p0_rddata[15:0] + end + attribute \src "ls180.v:2353.11-2353.51" + process $proc$ls180.v:2353$3607 + assign { } { } + assign $1\builder_interface9_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \builder_interface9_bank_bus_dat_r $1\builder_interface9_bank_bus_dat_r[7:0] + end + attribute \src "ls180.v:236.5-236.36" + process $proc$ls180.v:236$2831 + assign { } { } + assign $1\main_dfi_p0_rddata_valid[0:0] 1'0 + sync always + sync init + update \main_dfi_p0_rddata_valid $1\main_dfi_p0_rddata_valid[0:0] + end + attribute \src "ls180.v:237.11-237.32" + process $proc$ls180.v:237$2832 + assign { } { } + assign $1\main_rddata_en[2:0] 3'000 + sync always + sync init + update \main_rddata_en $1\main_rddata_en[2:0] + end + attribute \src "ls180.v:2386.11-2386.52" + process $proc$ls180.v:2386$3608 + assign { } { } + assign $1\builder_interface10_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \builder_interface10_bank_bus_dat_r $1\builder_interface10_bank_bus_dat_r[7:0] + end + attribute \src "ls180.v:240.5-240.36" + process $proc$ls180.v:240$2833 + assign { } { } + assign $1\main_sdram_inti_p0_cas_n[0:0] 1'1 + sync always + sync init + update \main_sdram_inti_p0_cas_n $1\main_sdram_inti_p0_cas_n[0:0] + end + attribute \src "ls180.v:241.5-241.35" + process $proc$ls180.v:241$2834 + assign { } { } + assign $1\main_sdram_inti_p0_cs_n[0:0] 1'1 + sync always + sync init + update \main_sdram_inti_p0_cs_n $1\main_sdram_inti_p0_cs_n[0:0] + end + attribute \src "ls180.v:242.5-242.36" + process $proc$ls180.v:242$2835 + assign { } { } + assign $1\main_sdram_inti_p0_ras_n[0:0] 1'1 + sync always + sync init + update \main_sdram_inti_p0_ras_n $1\main_sdram_inti_p0_ras_n[0:0] + end + attribute \src "ls180.v:2427.11-2427.52" + process $proc$ls180.v:2427$3609 + assign { } { } + assign $1\builder_interface11_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \builder_interface11_bank_bus_dat_r $1\builder_interface11_bank_bus_dat_r[7:0] + end + attribute \src "ls180.v:243.5-243.35" + process $proc$ls180.v:243$2836 + assign { } { } + assign $1\main_sdram_inti_p0_we_n[0:0] 1'1 + sync always + sync init + update \main_sdram_inti_p0_we_n $1\main_sdram_inti_p0_we_n[0:0] + end + attribute \src "ls180.v:247.5-247.36" + process $proc$ls180.v:247$2837 + assign { } { } + assign $0\main_sdram_inti_p0_act_n[0:0] 1'1 + sync always + update \main_sdram_inti_p0_act_n $0\main_sdram_inti_p0_act_n[0:0] + sync init + end + attribute \src "ls180.v:2492.11-2492.52" + process $proc$ls180.v:2492$3610 + assign { } { } + assign $1\builder_interface12_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \builder_interface12_bank_bus_dat_r $1\builder_interface12_bank_bus_dat_r[7:0] + end + attribute \src "ls180.v:2517.11-2517.52" + process $proc$ls180.v:2517$3611 + assign { } { } + assign $1\builder_interface13_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \builder_interface13_bank_bus_dat_r $1\builder_interface13_bank_bus_dat_r[7:0] + end + attribute \src "ls180.v:252.12-252.45" + process $proc$ls180.v:252$2838 + assign { } { } + assign $1\main_sdram_inti_p0_rddata[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdram_inti_p0_rddata $1\main_sdram_inti_p0_rddata[15:0] + end + attribute \src "ls180.v:253.5-253.43" + process $proc$ls180.v:253$2839 + assign { } { } + assign $1\main_sdram_inti_p0_rddata_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_inti_p0_rddata_valid $1\main_sdram_inti_p0_rddata_valid[0:0] + end + attribute \src "ls180.v:2539.11-2539.31" + process $proc$ls180.v:2539$3612 + assign { } { } + assign $1\builder_state[1:0] 2'00 + sync always + sync init + update \builder_state $1\builder_state[1:0] + end + attribute \src "ls180.v:2540.11-2540.36" + process $proc$ls180.v:2540$3613 + assign { } { } + assign $1\builder_next_state[1:0] 2'00 + sync always + sync init + update \builder_next_state $1\builder_next_state[1:0] + end + attribute \src "ls180.v:2541.11-2541.55" + process $proc$ls180.v:2541$3614 + assign { } { } + assign $1\builder_libresocsim_dat_w_next_value0[7:0] 8'00000000 + sync always + sync init + update \builder_libresocsim_dat_w_next_value0 $1\builder_libresocsim_dat_w_next_value0[7:0] + end + attribute \src "ls180.v:2542.5-2542.52" + process $proc$ls180.v:2542$3615 + assign { } { } + assign $1\builder_libresocsim_dat_w_next_value_ce0[0:0] 1'0 + sync always + sync init + update \builder_libresocsim_dat_w_next_value_ce0 $1\builder_libresocsim_dat_w_next_value_ce0[0:0] + end + attribute \src "ls180.v:2543.12-2543.55" + process $proc$ls180.v:2543$3616 + assign { } { } + assign $1\builder_libresocsim_adr_next_value1[13:0] 14'00000000000000 + sync always + sync init + update \builder_libresocsim_adr_next_value1 $1\builder_libresocsim_adr_next_value1[13:0] + end + attribute \src "ls180.v:2544.5-2544.50" + process $proc$ls180.v:2544$3617 + assign { } { } + assign $1\builder_libresocsim_adr_next_value_ce1[0:0] 1'0 + sync always + sync init + update \builder_libresocsim_adr_next_value_ce1 $1\builder_libresocsim_adr_next_value_ce1[0:0] + end + attribute \src "ls180.v:2545.5-2545.46" + process $proc$ls180.v:2545$3618 + assign { } { } + assign $1\builder_libresocsim_we_next_value2[0:0] 1'0 + sync always + sync init + update \builder_libresocsim_we_next_value2 $1\builder_libresocsim_we_next_value2[0:0] + end + attribute \src "ls180.v:2546.5-2546.49" + process $proc$ls180.v:2546$3619 + assign { } { } + assign $1\builder_libresocsim_we_next_value_ce2[0:0] 1'0 + sync always + sync init + update \builder_libresocsim_we_next_value_ce2 $1\builder_libresocsim_we_next_value_ce2[0:0] + end + attribute \src "ls180.v:2547.5-2547.41" + process $proc$ls180.v:2547$3620 + assign { } { } + assign $1\builder_comb_rhs_array_muxed0[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed0 $1\builder_comb_rhs_array_muxed0[0:0] + end + attribute \src "ls180.v:2548.12-2548.49" + process $proc$ls180.v:2548$3621 + assign { } { } + assign $1\builder_comb_rhs_array_muxed1[12:0] 13'0000000000000 + sync always + sync init + update \builder_comb_rhs_array_muxed1 $1\builder_comb_rhs_array_muxed1[12:0] + end + attribute \src "ls180.v:2549.11-2549.47" + process $proc$ls180.v:2549$3622 + assign { } { } + assign $1\builder_comb_rhs_array_muxed2[1:0] 2'00 + sync always + sync init + update \builder_comb_rhs_array_muxed2 $1\builder_comb_rhs_array_muxed2[1:0] + end + attribute \src "ls180.v:2550.5-2550.41" + process $proc$ls180.v:2550$3623 + assign { } { } + assign $1\builder_comb_rhs_array_muxed3[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed3 $1\builder_comb_rhs_array_muxed3[0:0] + end + attribute \src "ls180.v:2551.5-2551.41" + process $proc$ls180.v:2551$3624 + assign { } { } + assign $1\builder_comb_rhs_array_muxed4[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed4 $1\builder_comb_rhs_array_muxed4[0:0] + end + attribute \src "ls180.v:2552.5-2552.41" + process $proc$ls180.v:2552$3625 + assign { } { } + assign $1\builder_comb_rhs_array_muxed5[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed5 $1\builder_comb_rhs_array_muxed5[0:0] + end + attribute \src "ls180.v:2553.5-2553.39" + process $proc$ls180.v:2553$3626 + assign { } { } + assign $1\builder_comb_t_array_muxed0[0:0] 1'0 + sync always + sync init + update \builder_comb_t_array_muxed0 $1\builder_comb_t_array_muxed0[0:0] + end + attribute \src "ls180.v:2554.5-2554.39" + process $proc$ls180.v:2554$3627 + assign { } { } + assign $1\builder_comb_t_array_muxed1[0:0] 1'0 + sync always + sync init + update \builder_comb_t_array_muxed1 $1\builder_comb_t_array_muxed1[0:0] + end + attribute \src "ls180.v:2555.5-2555.39" + process $proc$ls180.v:2555$3628 + assign { } { } + assign $1\builder_comb_t_array_muxed2[0:0] 1'0 + sync always + sync init + update \builder_comb_t_array_muxed2 $1\builder_comb_t_array_muxed2[0:0] + end + attribute \src "ls180.v:2556.5-2556.41" + process $proc$ls180.v:2556$3629 + assign { } { } + assign $1\builder_comb_rhs_array_muxed6[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed6 $1\builder_comb_rhs_array_muxed6[0:0] + end + attribute \src "ls180.v:2557.12-2557.49" + process $proc$ls180.v:2557$3630 + assign { } { } + assign $1\builder_comb_rhs_array_muxed7[12:0] 13'0000000000000 + sync always + sync init + update \builder_comb_rhs_array_muxed7 $1\builder_comb_rhs_array_muxed7[12:0] + end + attribute \src "ls180.v:2558.11-2558.47" + process $proc$ls180.v:2558$3631 + assign { } { } + assign $1\builder_comb_rhs_array_muxed8[1:0] 2'00 + sync always + sync init + update \builder_comb_rhs_array_muxed8 $1\builder_comb_rhs_array_muxed8[1:0] + end + attribute \src "ls180.v:2559.5-2559.41" + process $proc$ls180.v:2559$3632 + assign { } { } + assign $1\builder_comb_rhs_array_muxed9[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed9 $1\builder_comb_rhs_array_muxed9[0:0] + end + attribute \src "ls180.v:2560.5-2560.42" + process $proc$ls180.v:2560$3633 + assign { } { } + assign $1\builder_comb_rhs_array_muxed10[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed10 $1\builder_comb_rhs_array_muxed10[0:0] + end + attribute \src "ls180.v:2561.5-2561.42" + process $proc$ls180.v:2561$3634 + assign { } { } + assign $1\builder_comb_rhs_array_muxed11[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed11 $1\builder_comb_rhs_array_muxed11[0:0] + end + attribute \src "ls180.v:2562.5-2562.39" + process $proc$ls180.v:2562$3635 + assign { } { } + assign $1\builder_comb_t_array_muxed3[0:0] 1'0 + sync always + sync init + update \builder_comb_t_array_muxed3 $1\builder_comb_t_array_muxed3[0:0] + end + attribute \src "ls180.v:2563.5-2563.39" + process $proc$ls180.v:2563$3636 + assign { } { } + assign $1\builder_comb_t_array_muxed4[0:0] 1'0 + sync always + sync init + update \builder_comb_t_array_muxed4 $1\builder_comb_t_array_muxed4[0:0] + end + attribute \src "ls180.v:2564.5-2564.39" + process $proc$ls180.v:2564$3637 + assign { } { } + assign $1\builder_comb_t_array_muxed5[0:0] 1'0 + sync always + sync init + update \builder_comb_t_array_muxed5 $1\builder_comb_t_array_muxed5[0:0] + end + attribute \src "ls180.v:2565.12-2565.50" + process $proc$ls180.v:2565$3638 + assign { } { } + assign $1\builder_comb_rhs_array_muxed12[21:0] 22'0000000000000000000000 + sync always + sync init + update \builder_comb_rhs_array_muxed12 $1\builder_comb_rhs_array_muxed12[21:0] + end + attribute \src "ls180.v:2566.5-2566.42" + process $proc$ls180.v:2566$3639 + assign { } { } + assign $1\builder_comb_rhs_array_muxed13[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed13 $1\builder_comb_rhs_array_muxed13[0:0] + end + attribute \src "ls180.v:2567.5-2567.42" + process $proc$ls180.v:2567$3640 + assign { } { } + assign $1\builder_comb_rhs_array_muxed14[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed14 $1\builder_comb_rhs_array_muxed14[0:0] + end + attribute \src "ls180.v:2568.12-2568.50" + process $proc$ls180.v:2568$3641 + assign { } { } + assign $1\builder_comb_rhs_array_muxed15[21:0] 22'0000000000000000000000 + sync always + sync init + update \builder_comb_rhs_array_muxed15 $1\builder_comb_rhs_array_muxed15[21:0] + end + attribute \src "ls180.v:2569.5-2569.42" + process $proc$ls180.v:2569$3642 + assign { } { } + assign $1\builder_comb_rhs_array_muxed16[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed16 $1\builder_comb_rhs_array_muxed16[0:0] + end + attribute \src "ls180.v:2570.5-2570.42" + process $proc$ls180.v:2570$3643 + assign { } { } + assign $1\builder_comb_rhs_array_muxed17[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed17 $1\builder_comb_rhs_array_muxed17[0:0] + end + attribute \src "ls180.v:2571.12-2571.50" + process $proc$ls180.v:2571$3644 + assign { } { } + assign $1\builder_comb_rhs_array_muxed18[21:0] 22'0000000000000000000000 + sync always + sync init + update \builder_comb_rhs_array_muxed18 $1\builder_comb_rhs_array_muxed18[21:0] + end + attribute \src "ls180.v:2572.5-2572.42" + process $proc$ls180.v:2572$3645 + assign { } { } + assign $1\builder_comb_rhs_array_muxed19[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed19 $1\builder_comb_rhs_array_muxed19[0:0] + end + attribute \src "ls180.v:2573.5-2573.42" + process $proc$ls180.v:2573$3646 + assign { } { } + assign $1\builder_comb_rhs_array_muxed20[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed20 $1\builder_comb_rhs_array_muxed20[0:0] + end + attribute \src "ls180.v:2574.12-2574.50" + process $proc$ls180.v:2574$3647 + assign { } { } + assign $1\builder_comb_rhs_array_muxed21[21:0] 22'0000000000000000000000 + sync always + sync init + update \builder_comb_rhs_array_muxed21 $1\builder_comb_rhs_array_muxed21[21:0] + end + attribute \src "ls180.v:2575.5-2575.42" + process $proc$ls180.v:2575$3648 + assign { } { } + assign $1\builder_comb_rhs_array_muxed22[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed22 $1\builder_comb_rhs_array_muxed22[0:0] + end + attribute \src "ls180.v:2576.5-2576.42" + process $proc$ls180.v:2576$3649 + assign { } { } + assign $1\builder_comb_rhs_array_muxed23[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed23 $1\builder_comb_rhs_array_muxed23[0:0] + end + attribute \src "ls180.v:2577.12-2577.50" + process $proc$ls180.v:2577$3650 + assign { } { } + assign $1\builder_comb_rhs_array_muxed24[31:0] 0 + sync always + sync init + update \builder_comb_rhs_array_muxed24 $1\builder_comb_rhs_array_muxed24[31:0] + end + attribute \src "ls180.v:2578.12-2578.50" + process $proc$ls180.v:2578$3651 + assign { } { } + assign $1\builder_comb_rhs_array_muxed25[31:0] 0 + sync always + sync init + update \builder_comb_rhs_array_muxed25 $1\builder_comb_rhs_array_muxed25[31:0] + end + attribute \src "ls180.v:2579.11-2579.48" + process $proc$ls180.v:2579$3652 + assign { } { } + assign $1\builder_comb_rhs_array_muxed26[3:0] 4'0000 + sync always + sync init + update \builder_comb_rhs_array_muxed26 $1\builder_comb_rhs_array_muxed26[3:0] + end + attribute \src "ls180.v:2580.5-2580.42" + process $proc$ls180.v:2580$3653 + assign { } { } + assign $1\builder_comb_rhs_array_muxed27[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed27 $1\builder_comb_rhs_array_muxed27[0:0] + end + attribute \src "ls180.v:2581.5-2581.42" + process $proc$ls180.v:2581$3654 + assign { } { } + assign $1\builder_comb_rhs_array_muxed28[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed28 $1\builder_comb_rhs_array_muxed28[0:0] + end + attribute \src "ls180.v:2582.5-2582.42" + process $proc$ls180.v:2582$3655 + assign { } { } + assign $1\builder_comb_rhs_array_muxed29[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed29 $1\builder_comb_rhs_array_muxed29[0:0] + end + attribute \src "ls180.v:2583.11-2583.48" + process $proc$ls180.v:2583$3656 + assign { } { } + assign $1\builder_comb_rhs_array_muxed30[2:0] 3'000 + sync always + sync init + update \builder_comb_rhs_array_muxed30 $1\builder_comb_rhs_array_muxed30[2:0] + end + attribute \src "ls180.v:2584.11-2584.48" + process $proc$ls180.v:2584$3657 + assign { } { } + assign $1\builder_comb_rhs_array_muxed31[1:0] 2'00 + sync always + sync init + update \builder_comb_rhs_array_muxed31 $1\builder_comb_rhs_array_muxed31[1:0] + end + attribute \src "ls180.v:2585.11-2585.47" + process $proc$ls180.v:2585$3658 + assign { } { } + assign $1\builder_sync_rhs_array_muxed0[1:0] 2'00 + sync always + sync init + update \builder_sync_rhs_array_muxed0 $1\builder_sync_rhs_array_muxed0[1:0] + end + attribute \src "ls180.v:2586.12-2586.49" + process $proc$ls180.v:2586$3659 + assign { } { } + assign $1\builder_sync_rhs_array_muxed1[12:0] 13'0000000000000 + sync always + sync init + update \builder_sync_rhs_array_muxed1 $1\builder_sync_rhs_array_muxed1[12:0] + end + attribute \src "ls180.v:2587.5-2587.41" + process $proc$ls180.v:2587$3660 + assign { } { } + assign $1\builder_sync_rhs_array_muxed2[0:0] 1'0 + sync always + sync init + update \builder_sync_rhs_array_muxed2 $1\builder_sync_rhs_array_muxed2[0:0] + end + attribute \src "ls180.v:2588.5-2588.41" + process $proc$ls180.v:2588$3661 + assign { } { } + assign $1\builder_sync_rhs_array_muxed3[0:0] 1'0 + sync always + sync init + update \builder_sync_rhs_array_muxed3 $1\builder_sync_rhs_array_muxed3[0:0] + end + attribute \src "ls180.v:2589.5-2589.41" + process $proc$ls180.v:2589$3662 + assign { } { } + assign $1\builder_sync_rhs_array_muxed4[0:0] 1'0 + sync always + sync init + update \builder_sync_rhs_array_muxed4 $1\builder_sync_rhs_array_muxed4[0:0] + end + attribute \src "ls180.v:2590.5-2590.41" + process $proc$ls180.v:2590$3663 + assign { } { } + assign $1\builder_sync_rhs_array_muxed5[0:0] 1'0 + sync always + sync init + update \builder_sync_rhs_array_muxed5 $1\builder_sync_rhs_array_muxed5[0:0] + end + attribute \src "ls180.v:2591.5-2591.41" + process $proc$ls180.v:2591$3664 + assign { } { } + assign $1\builder_sync_rhs_array_muxed6[0:0] 1'0 + sync always + sync init + update \builder_sync_rhs_array_muxed6 $1\builder_sync_rhs_array_muxed6[0:0] + end + attribute \src "ls180.v:2592.5-2592.39" + process $proc$ls180.v:2592$3665 + assign { } { } + assign $1\builder_sync_f_array_muxed0[0:0] 1'0 + sync always + sync init + update \builder_sync_f_array_muxed0 $1\builder_sync_f_array_muxed0[0:0] + end + attribute \src "ls180.v:2593.5-2593.39" + process $proc$ls180.v:2593$3666 + assign { } { } + assign $1\builder_sync_f_array_muxed1[0:0] 1'0 + sync always + sync init + update \builder_sync_f_array_muxed1 $1\builder_sync_f_array_muxed1[0:0] + end + attribute \src "ls180.v:2650.32-2650.66" + process $proc$ls180.v:2650$3667 + assign { } { } + assign $1\builder_multiregimpl0_regs0[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl0_regs0 $1\builder_multiregimpl0_regs0[0:0] + end + attribute \src "ls180.v:2651.32-2651.66" + process $proc$ls180.v:2651$3668 + assign { } { } + assign $1\builder_multiregimpl0_regs1[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl0_regs1 $1\builder_multiregimpl0_regs1[0:0] + end + attribute \src "ls180.v:2652.32-2652.66" + process $proc$ls180.v:2652$3669 + assign { } { } + assign $1\builder_multiregimpl1_regs0[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl1_regs0 $1\builder_multiregimpl1_regs0[0:0] + end + attribute \src "ls180.v:2653.32-2653.66" + process $proc$ls180.v:2653$3670 + assign { } { } + assign $1\builder_multiregimpl1_regs1[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl1_regs1 $1\builder_multiregimpl1_regs1[0:0] + end + attribute \src "ls180.v:2654.32-2654.66" + process $proc$ls180.v:2654$3671 + assign { } { } + assign $1\builder_multiregimpl2_regs0[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl2_regs0 $1\builder_multiregimpl2_regs0[0:0] + end + attribute \src "ls180.v:2655.32-2655.66" + process $proc$ls180.v:2655$3672 + assign { } { } + assign $1\builder_multiregimpl2_regs1[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl2_regs1 $1\builder_multiregimpl2_regs1[0:0] + end + attribute \src "ls180.v:2656.32-2656.66" + process $proc$ls180.v:2656$3673 + assign { } { } + assign $1\builder_multiregimpl3_regs0[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl3_regs0 $1\builder_multiregimpl3_regs0[0:0] + end + attribute \src "ls180.v:2657.32-2657.66" + process $proc$ls180.v:2657$3674 + assign { } { } + assign $1\builder_multiregimpl3_regs1[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl3_regs1 $1\builder_multiregimpl3_regs1[0:0] + end + attribute \src "ls180.v:2658.32-2658.66" + process $proc$ls180.v:2658$3675 + assign { } { } + assign $1\builder_multiregimpl4_regs0[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl4_regs0 $1\builder_multiregimpl4_regs0[0:0] + end + attribute \src "ls180.v:2659.32-2659.66" + process $proc$ls180.v:2659$3676 + assign { } { } + assign $1\builder_multiregimpl4_regs1[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl4_regs1 $1\builder_multiregimpl4_regs1[0:0] + end + attribute \src "ls180.v:2660.32-2660.66" + process $proc$ls180.v:2660$3677 + assign { } { } + assign $1\builder_multiregimpl5_regs0[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl5_regs0 $1\builder_multiregimpl5_regs0[0:0] + end + attribute \src "ls180.v:2661.32-2661.66" + process $proc$ls180.v:2661$3678 + assign { } { } + assign $1\builder_multiregimpl5_regs1[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl5_regs1 $1\builder_multiregimpl5_regs1[0:0] + end + attribute \src "ls180.v:2662.32-2662.66" + process $proc$ls180.v:2662$3679 + assign { } { } + assign $1\builder_multiregimpl6_regs0[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl6_regs0 $1\builder_multiregimpl6_regs0[0:0] + end + attribute \src "ls180.v:2663.32-2663.66" + process $proc$ls180.v:2663$3680 + assign { } { } + assign $1\builder_multiregimpl6_regs1[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl6_regs1 $1\builder_multiregimpl6_regs1[0:0] + end + attribute \src "ls180.v:2664.32-2664.66" + process $proc$ls180.v:2664$3681 + assign { } { } + assign $1\builder_multiregimpl7_regs0[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl7_regs0 $1\builder_multiregimpl7_regs0[0:0] + end + attribute \src "ls180.v:2665.32-2665.66" + process $proc$ls180.v:2665$3682 + assign { } { } + assign $1\builder_multiregimpl7_regs1[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl7_regs1 $1\builder_multiregimpl7_regs1[0:0] + end + attribute \src "ls180.v:2666.32-2666.66" + process $proc$ls180.v:2666$3683 + assign { } { } + assign $1\builder_multiregimpl8_regs0[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl8_regs0 $1\builder_multiregimpl8_regs0[0:0] + end + attribute \src "ls180.v:2667.32-2667.66" + process $proc$ls180.v:2667$3684 + assign { } { } + assign $1\builder_multiregimpl8_regs1[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl8_regs1 $1\builder_multiregimpl8_regs1[0:0] + end + attribute \src "ls180.v:2668.32-2668.66" + process $proc$ls180.v:2668$3685 + assign { } { } + assign $1\builder_multiregimpl9_regs0[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl9_regs0 $1\builder_multiregimpl9_regs0[0:0] + end + attribute \src "ls180.v:2669.32-2669.66" + process $proc$ls180.v:2669$3686 + assign { } { } + assign $1\builder_multiregimpl9_regs1[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl9_regs1 $1\builder_multiregimpl9_regs1[0:0] + end + attribute \src "ls180.v:2670.32-2670.67" + process $proc$ls180.v:2670$3687 + assign { } { } + assign $1\builder_multiregimpl10_regs0[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl10_regs0 $1\builder_multiregimpl10_regs0[0:0] + end + attribute \src "ls180.v:2671.32-2671.67" + process $proc$ls180.v:2671$3688 + assign { } { } + assign $1\builder_multiregimpl10_regs1[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl10_regs1 $1\builder_multiregimpl10_regs1[0:0] + end + attribute \src "ls180.v:2672.32-2672.67" + process $proc$ls180.v:2672$3689 + assign { } { } + assign $1\builder_multiregimpl11_regs0[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl11_regs0 $1\builder_multiregimpl11_regs0[0:0] + end + attribute \src "ls180.v:2673.32-2673.67" + process $proc$ls180.v:2673$3690 + assign { } { } + assign $1\builder_multiregimpl11_regs1[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl11_regs1 $1\builder_multiregimpl11_regs1[0:0] + end + attribute \src "ls180.v:2674.32-2674.67" + process $proc$ls180.v:2674$3691 + assign { } { } + assign $1\builder_multiregimpl12_regs0[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl12_regs0 $1\builder_multiregimpl12_regs0[0:0] + end + attribute \src "ls180.v:2675.32-2675.67" + process $proc$ls180.v:2675$3692 + assign { } { } + assign $1\builder_multiregimpl12_regs1[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl12_regs1 $1\builder_multiregimpl12_regs1[0:0] + end + attribute \src "ls180.v:2676.32-2676.67" + process $proc$ls180.v:2676$3693 + assign { } { } + assign $1\builder_multiregimpl13_regs0[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl13_regs0 $1\builder_multiregimpl13_regs0[0:0] + end + attribute \src "ls180.v:2677.32-2677.67" + process $proc$ls180.v:2677$3694 + assign { } { } + assign $1\builder_multiregimpl13_regs1[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl13_regs1 $1\builder_multiregimpl13_regs1[0:0] + end + attribute \src "ls180.v:2678.32-2678.67" + process $proc$ls180.v:2678$3695 + assign { } { } + assign $1\builder_multiregimpl14_regs0[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl14_regs0 $1\builder_multiregimpl14_regs0[0:0] + end + attribute \src "ls180.v:2679.32-2679.67" + process $proc$ls180.v:2679$3696 + assign { } { } + assign $1\builder_multiregimpl14_regs1[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl14_regs1 $1\builder_multiregimpl14_regs1[0:0] + end + attribute \src "ls180.v:268.12-268.46" + process $proc$ls180.v:268$2840 + assign { } { } + assign $1\main_sdram_slave_p0_rddata[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdram_slave_p0_rddata $1\main_sdram_slave_p0_rddata[15:0] + end + attribute \src "ls180.v:2680.32-2680.67" + process $proc$ls180.v:2680$3697 + assign { } { } + assign $1\builder_multiregimpl15_regs0[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl15_regs0 $1\builder_multiregimpl15_regs0[0:0] + end + attribute \src "ls180.v:2681.32-2681.67" + process $proc$ls180.v:2681$3698 + assign { } { } + assign $1\builder_multiregimpl15_regs1[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl15_regs1 $1\builder_multiregimpl15_regs1[0:0] + end + attribute \src "ls180.v:2682.32-2682.67" + process $proc$ls180.v:2682$3699 + assign { } { } + assign $1\builder_multiregimpl16_regs0[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl16_regs0 $1\builder_multiregimpl16_regs0[0:0] + end + attribute \src "ls180.v:2683.32-2683.67" + process $proc$ls180.v:2683$3700 + assign { } { } + assign $1\builder_multiregimpl16_regs1[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl16_regs1 $1\builder_multiregimpl16_regs1[0:0] + end + attribute \src "ls180.v:269.5-269.44" + process $proc$ls180.v:269$2841 + assign { } { } + assign $1\main_sdram_slave_p0_rddata_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_slave_p0_rddata_valid $1\main_sdram_slave_p0_rddata_valid[0:0] + end + attribute \src "ls180.v:270.12-270.48" + process $proc$ls180.v:270$2842 + assign { } { } + assign $1\main_sdram_master_p0_address[12:0] 13'0000000000000 + sync always + sync init + update \main_sdram_master_p0_address $1\main_sdram_master_p0_address[12:0] + end + attribute \src "ls180.v:271.11-271.43" + process $proc$ls180.v:271$2843 + assign { } { } + assign $1\main_sdram_master_p0_bank[1:0] 2'00 + sync always + sync init + update \main_sdram_master_p0_bank $1\main_sdram_master_p0_bank[1:0] + end + attribute \src "ls180.v:272.5-272.38" + process $proc$ls180.v:272$2844 + assign { } { } + assign $1\main_sdram_master_p0_cas_n[0:0] 1'1 + sync always + sync init + update \main_sdram_master_p0_cas_n $1\main_sdram_master_p0_cas_n[0:0] + end + attribute \src "ls180.v:2720.1-2725.4" + process $proc$ls180.v:2720$13 + assign { } { } + assign $0\main_libresocsim_libresoc_interrupt[15:0] [11:2] 10'0000000000 + assign $0\main_libresocsim_libresoc_interrupt[15:0] [15:12] { 1'0 \eint } + assign $0\main_libresocsim_libresoc_interrupt[15:0] [0] \main_libresocsim_irq + assign $0\main_libresocsim_libresoc_interrupt[15:0] [1] \main_uart_irq + sync always + update \main_libresocsim_libresoc_interrupt $0\main_libresocsim_libresoc_interrupt[15:0] + end + attribute \src "ls180.v:2727.1-2737.4" + process $proc$ls180.v:2727$15 + assign { } { } + assign $0\main_libresocsim_interface0_converted_interface_dat_w[31:0] 0 + attribute \src "ls180.v:2729.2-2736.9" + switch \main_libresocsim_converter0_counter + attribute \src "ls180.v:0.0-0.0" + case 1'0 + assign $0\main_libresocsim_interface0_converted_interface_dat_w[31:0] \main_libresocsim_libresoc_ibus_dat_w [31:0] + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\main_libresocsim_interface0_converted_interface_dat_w[31:0] \main_libresocsim_libresoc_ibus_dat_w [63:32] + case + end + sync always + update \main_libresocsim_interface0_converted_interface_dat_w $0\main_libresocsim_interface0_converted_interface_dat_w[31:0] + end + attribute \src "ls180.v:273.5-273.37" + process $proc$ls180.v:273$2845 + assign { } { } + assign $1\main_sdram_master_p0_cs_n[0:0] 1'1 + sync always + sync init + update \main_sdram_master_p0_cs_n $1\main_sdram_master_p0_cs_n[0:0] + end + attribute \src "ls180.v:2739.1-2785.4" + process $proc$ls180.v:2739$16 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0] 1'0 + assign $0\main_libresocsim_interface0_converted_interface_we[0:0] 1'0 + assign $0\main_libresocsim_libresoc_ibus_ack[0:0] 1'0 + assign $0\main_libresocsim_converter0_skip[0:0] 1'0 + assign $0\main_libresocsim_interface0_converted_interface_adr[29:0] 30'000000000000000000000000000000 + assign $0\main_libresocsim_interface0_converted_interface_sel[3:0] 4'0000 + assign { } { } + assign $0\main_libresocsim_interface0_converted_interface_cyc[0:0] 1'0 + assign $0\main_libresocsim_converter0_counter_converter0_next_value[0:0] 1'0 + assign $0\main_libresocsim_interface0_converted_interface_stb[0:0] 1'0 + assign $0\builder_converter0_next_state[0:0] \builder_converter0_state + attribute \src "ls180.v:2751.2-2784.9" + switch \builder_converter0_state + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\main_libresocsim_interface0_converted_interface_adr[29:0] { \main_libresocsim_libresoc_ibus_adr \main_libresocsim_converter0_counter } + attribute \src "ls180.v:2754.4-2761.11" + switch \main_libresocsim_converter0_counter + attribute \src "ls180.v:0.0-0.0" + case 1'0 + assign $0\main_libresocsim_interface0_converted_interface_sel[3:0] \main_libresocsim_libresoc_ibus_sel [3:0] + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\main_libresocsim_interface0_converted_interface_sel[3:0] \main_libresocsim_libresoc_ibus_sel [7:4] + case + end + attribute \src "ls180.v:2762.4-2775.7" + switch $and$ls180.v:2762$17_Y + attribute \src "ls180.v:2762.8-2762.81" + case 1'1 + assign $0\main_libresocsim_converter0_skip[0:0] $eq$ls180.v:2763$18_Y + assign $0\main_libresocsim_interface0_converted_interface_we[0:0] \main_libresocsim_libresoc_ibus_we + assign $0\main_libresocsim_interface0_converted_interface_cyc[0:0] $not$ls180.v:2765$19_Y + assign $0\main_libresocsim_interface0_converted_interface_stb[0:0] $not$ls180.v:2766$20_Y + attribute \src "ls180.v:2767.5-2774.8" + switch $or$ls180.v:2767$21_Y + attribute \src "ls180.v:2767.9-2767.97" + case 1'1 + assign $0\main_libresocsim_converter0_counter_converter0_next_value[0:0] $add$ls180.v:2768$22_Y + assign $0\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:2770.6-2773.9" + switch $eq$ls180.v:2770$23_Y + attribute \src "ls180.v:2770.10-2770.55" + case 1'1 + assign $0\main_libresocsim_libresoc_ibus_ack[0:0] 1'1 + assign $0\builder_converter0_next_state[0:0] 1'0 + case + end + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_libresocsim_converter0_counter_converter0_next_value[0:0] 1'0 + assign $0\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:2780.4-2782.7" + switch $and$ls180.v:2780$24_Y + attribute \src "ls180.v:2780.8-2780.81" + case 1'1 + assign $0\builder_converter0_next_state[0:0] 1'1 + case + end + end + sync always + update \main_libresocsim_libresoc_ibus_ack $0\main_libresocsim_libresoc_ibus_ack[0:0] + update \main_libresocsim_interface0_converted_interface_adr $0\main_libresocsim_interface0_converted_interface_adr[29:0] + update \main_libresocsim_interface0_converted_interface_sel $0\main_libresocsim_interface0_converted_interface_sel[3:0] + update \main_libresocsim_interface0_converted_interface_cyc $0\main_libresocsim_interface0_converted_interface_cyc[0:0] + update \main_libresocsim_interface0_converted_interface_stb $0\main_libresocsim_interface0_converted_interface_stb[0:0] + update \main_libresocsim_interface0_converted_interface_we $0\main_libresocsim_interface0_converted_interface_we[0:0] + update \main_libresocsim_converter0_skip $0\main_libresocsim_converter0_skip[0:0] + update \builder_converter0_next_state $0\builder_converter0_next_state[0:0] + update \main_libresocsim_converter0_counter_converter0_next_value $0\main_libresocsim_converter0_counter_converter0_next_value[0:0] + update \main_libresocsim_converter0_counter_converter0_next_value_ce $0\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0] + end + attribute \src "ls180.v:274.5-274.38" + process $proc$ls180.v:274$2846 + assign { } { } + assign $1\main_sdram_master_p0_ras_n[0:0] 1'1 + sync always + sync init + update \main_sdram_master_p0_ras_n $1\main_sdram_master_p0_ras_n[0:0] + end + attribute \src "ls180.v:275.5-275.37" + process $proc$ls180.v:275$2847 + assign { } { } + assign $1\main_sdram_master_p0_we_n[0:0] 1'1 + sync always + sync init + update \main_sdram_master_p0_we_n $1\main_sdram_master_p0_we_n[0:0] + end + attribute \src "ls180.v:276.5-276.36" + process $proc$ls180.v:276$2848 + assign { } { } + assign $1\main_sdram_master_p0_cke[0:0] 1'0 + sync always + sync init + update \main_sdram_master_p0_cke $1\main_sdram_master_p0_cke[0:0] + end + attribute \src "ls180.v:277.5-277.36" + process $proc$ls180.v:277$2849 + assign { } { } + assign $1\main_sdram_master_p0_odt[0:0] 1'0 + sync always + sync init + update \main_sdram_master_p0_odt $1\main_sdram_master_p0_odt[0:0] + end + attribute \src "ls180.v:278.5-278.40" + process $proc$ls180.v:278$2850 + assign { } { } + assign $1\main_sdram_master_p0_reset_n[0:0] 1'0 + sync always + sync init + update \main_sdram_master_p0_reset_n $1\main_sdram_master_p0_reset_n[0:0] + end + attribute \src "ls180.v:2787.1-2797.4" + process $proc$ls180.v:2787$26 + assign { } { } + assign $0\main_libresocsim_interface1_converted_interface_dat_w[31:0] 0 + attribute \src "ls180.v:2789.2-2796.9" + switch \main_libresocsim_converter1_counter + attribute \src "ls180.v:0.0-0.0" + case 1'0 + assign $0\main_libresocsim_interface1_converted_interface_dat_w[31:0] \main_libresocsim_libresoc_dbus_dat_w [31:0] + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\main_libresocsim_interface1_converted_interface_dat_w[31:0] \main_libresocsim_libresoc_dbus_dat_w [63:32] + case + end + sync always + update \main_libresocsim_interface1_converted_interface_dat_w $0\main_libresocsim_interface1_converted_interface_dat_w[31:0] + end + attribute \src "ls180.v:279.5-279.38" + process $proc$ls180.v:279$2851 + assign { } { } + assign $1\main_sdram_master_p0_act_n[0:0] 1'1 + sync always + sync init + update \main_sdram_master_p0_act_n $1\main_sdram_master_p0_act_n[0:0] + end + attribute \src "ls180.v:2799.1-2845.4" + process $proc$ls180.v:2799$27 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_libresocsim_converter1_skip[0:0] 1'0 + assign $0\main_libresocsim_interface1_converted_interface_adr[29:0] 30'000000000000000000000000000000 + assign $0\main_libresocsim_interface1_converted_interface_we[0:0] 1'0 + assign $0\main_libresocsim_libresoc_dbus_ack[0:0] 1'0 + assign $0\main_libresocsim_interface1_converted_interface_sel[3:0] 4'0000 + assign $0\main_libresocsim_interface1_converted_interface_cyc[0:0] 1'0 + assign $0\main_libresocsim_interface1_converted_interface_stb[0:0] 1'0 + assign { } { } + assign $0\main_libresocsim_converter1_counter_converter1_next_value[0:0] 1'0 + assign $0\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0] 1'0 + assign $0\builder_converter1_next_state[0:0] \builder_converter1_state + attribute \src "ls180.v:2811.2-2844.9" + switch \builder_converter1_state + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\main_libresocsim_interface1_converted_interface_adr[29:0] { \main_libresocsim_libresoc_dbus_adr \main_libresocsim_converter1_counter } + attribute \src "ls180.v:2814.4-2821.11" + switch \main_libresocsim_converter1_counter + attribute \src "ls180.v:0.0-0.0" + case 1'0 + assign $0\main_libresocsim_interface1_converted_interface_sel[3:0] \main_libresocsim_libresoc_dbus_sel [3:0] + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\main_libresocsim_interface1_converted_interface_sel[3:0] \main_libresocsim_libresoc_dbus_sel [7:4] + case + end + attribute \src "ls180.v:2822.4-2835.7" + switch $and$ls180.v:2822$28_Y + attribute \src "ls180.v:2822.8-2822.81" + case 1'1 + assign $0\main_libresocsim_converter1_skip[0:0] $eq$ls180.v:2823$29_Y + assign $0\main_libresocsim_interface1_converted_interface_we[0:0] \main_libresocsim_libresoc_dbus_we + assign $0\main_libresocsim_interface1_converted_interface_cyc[0:0] $not$ls180.v:2825$30_Y + assign $0\main_libresocsim_interface1_converted_interface_stb[0:0] $not$ls180.v:2826$31_Y + attribute \src "ls180.v:2827.5-2834.8" + switch $or$ls180.v:2827$32_Y + attribute \src "ls180.v:2827.9-2827.97" + case 1'1 + assign $0\main_libresocsim_converter1_counter_converter1_next_value[0:0] $add$ls180.v:2828$33_Y + assign $0\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:2830.6-2833.9" + switch $eq$ls180.v:2830$34_Y + attribute \src "ls180.v:2830.10-2830.55" + case 1'1 + assign $0\main_libresocsim_libresoc_dbus_ack[0:0] 1'1 + assign $0\builder_converter1_next_state[0:0] 1'0 + case + end + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_libresocsim_converter1_counter_converter1_next_value[0:0] 1'0 + assign $0\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:2840.4-2842.7" + switch $and$ls180.v:2840$35_Y + attribute \src "ls180.v:2840.8-2840.81" + case 1'1 + assign $0\builder_converter1_next_state[0:0] 1'1 + case + end + end + sync always + update \main_libresocsim_libresoc_dbus_ack $0\main_libresocsim_libresoc_dbus_ack[0:0] + update \main_libresocsim_interface1_converted_interface_adr $0\main_libresocsim_interface1_converted_interface_adr[29:0] + update \main_libresocsim_interface1_converted_interface_sel $0\main_libresocsim_interface1_converted_interface_sel[3:0] + update \main_libresocsim_interface1_converted_interface_cyc $0\main_libresocsim_interface1_converted_interface_cyc[0:0] + update \main_libresocsim_interface1_converted_interface_stb $0\main_libresocsim_interface1_converted_interface_stb[0:0] + update \main_libresocsim_interface1_converted_interface_we $0\main_libresocsim_interface1_converted_interface_we[0:0] + update \main_libresocsim_converter1_skip $0\main_libresocsim_converter1_skip[0:0] + update \builder_converter1_next_state $0\builder_converter1_next_state[0:0] + update \main_libresocsim_converter1_counter_converter1_next_value $0\main_libresocsim_converter1_counter_converter1_next_value[0:0] + update \main_libresocsim_converter1_counter_converter1_next_value_ce $0\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0] + end + attribute \src "ls180.v:280.12-280.47" + process $proc$ls180.v:280$2852 + assign { } { } + assign $1\main_sdram_master_p0_wrdata[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdram_master_p0_wrdata $1\main_sdram_master_p0_wrdata[15:0] + end + attribute \src "ls180.v:281.5-281.42" + process $proc$ls180.v:281$2853 + assign { } { } + assign $1\main_sdram_master_p0_wrdata_en[0:0] 1'0 + sync always + sync init + update \main_sdram_master_p0_wrdata_en $1\main_sdram_master_p0_wrdata_en[0:0] + end + attribute \src "ls180.v:282.11-282.50" + process $proc$ls180.v:282$2854 + assign { } { } + assign $1\main_sdram_master_p0_wrdata_mask[1:0] 2'00 + sync always + sync init + update \main_sdram_master_p0_wrdata_mask $1\main_sdram_master_p0_wrdata_mask[1:0] + end + attribute \src "ls180.v:283.5-283.42" + process $proc$ls180.v:283$2855 + assign { } { } + assign $1\main_sdram_master_p0_rddata_en[0:0] 1'0 + sync always + sync init + update \main_sdram_master_p0_rddata_en $1\main_sdram_master_p0_rddata_en[0:0] + end + attribute \src "ls180.v:2847.1-2857.4" + process $proc$ls180.v:2847$37 + assign { } { } + assign $0\main_libresocsim_interface2_converted_interface_dat_w[31:0] 0 + attribute \src "ls180.v:2849.2-2856.9" + switch \main_libresocsim_converter2_counter + attribute \src "ls180.v:0.0-0.0" + case 1'0 + assign $0\main_libresocsim_interface2_converted_interface_dat_w[31:0] \main_libresocsim_libresoc_jtag_wb_dat_w [31:0] + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\main_libresocsim_interface2_converted_interface_dat_w[31:0] \main_libresocsim_libresoc_jtag_wb_dat_w [63:32] + case + end + sync always + update \main_libresocsim_interface2_converted_interface_dat_w $0\main_libresocsim_interface2_converted_interface_dat_w[31:0] + end + attribute \src "ls180.v:2859.1-2905.4" + process $proc$ls180.v:2859$38 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_libresocsim_interface2_converted_interface_adr[29:0] 30'000000000000000000000000000000 + assign $0\main_libresocsim_libresoc_jtag_wb_ack[0:0] 1'0 + assign $0\main_libresocsim_interface2_converted_interface_sel[3:0] 4'0000 + assign $0\main_libresocsim_interface2_converted_interface_cyc[0:0] 1'0 + assign $0\main_libresocsim_interface2_converted_interface_stb[0:0] 1'0 + assign $0\main_libresocsim_interface2_converted_interface_we[0:0] 1'0 + assign { } { } + assign $0\main_libresocsim_converter2_counter_converter2_next_value[0:0] 1'0 + assign $0\main_libresocsim_converter2_counter_converter2_next_value_ce[0:0] 1'0 + assign $0\main_libresocsim_converter2_skip[0:0] 1'0 + assign $0\builder_converter2_next_state[0:0] \builder_converter2_state + attribute \src "ls180.v:2871.2-2904.9" + switch \builder_converter2_state + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\main_libresocsim_interface2_converted_interface_adr[29:0] { \main_libresocsim_libresoc_jtag_wb_adr \main_libresocsim_converter2_counter } + attribute \src "ls180.v:2874.4-2881.11" + switch \main_libresocsim_converter2_counter + attribute \src "ls180.v:0.0-0.0" + case 1'0 + assign $0\main_libresocsim_interface2_converted_interface_sel[3:0] \main_libresocsim_libresoc_jtag_wb_sel [3:0] + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\main_libresocsim_interface2_converted_interface_sel[3:0] \main_libresocsim_libresoc_jtag_wb_sel [7:4] + case + end + attribute \src "ls180.v:2882.4-2895.7" + switch $and$ls180.v:2882$39_Y + attribute \src "ls180.v:2882.8-2882.87" + case 1'1 + assign $0\main_libresocsim_converter2_skip[0:0] $eq$ls180.v:2883$40_Y + assign $0\main_libresocsim_interface2_converted_interface_we[0:0] \main_libresocsim_libresoc_jtag_wb_we + assign $0\main_libresocsim_interface2_converted_interface_cyc[0:0] $not$ls180.v:2885$41_Y + assign $0\main_libresocsim_interface2_converted_interface_stb[0:0] $not$ls180.v:2886$42_Y + attribute \src "ls180.v:2887.5-2894.8" + switch $or$ls180.v:2887$43_Y + attribute \src "ls180.v:2887.9-2887.97" + case 1'1 + assign $0\main_libresocsim_converter2_counter_converter2_next_value[0:0] $add$ls180.v:2888$44_Y + assign $0\main_libresocsim_converter2_counter_converter2_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:2890.6-2893.9" + switch $eq$ls180.v:2890$45_Y + attribute \src "ls180.v:2890.10-2890.55" + case 1'1 + assign $0\main_libresocsim_libresoc_jtag_wb_ack[0:0] 1'1 + assign $0\builder_converter2_next_state[0:0] 1'0 + case + end + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_libresocsim_converter2_counter_converter2_next_value[0:0] 1'0 + assign $0\main_libresocsim_converter2_counter_converter2_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:2900.4-2902.7" + switch $and$ls180.v:2900$46_Y + attribute \src "ls180.v:2900.8-2900.87" + case 1'1 + assign $0\builder_converter2_next_state[0:0] 1'1 + case + end + end + sync always + update \main_libresocsim_libresoc_jtag_wb_ack $0\main_libresocsim_libresoc_jtag_wb_ack[0:0] + update \main_libresocsim_interface2_converted_interface_adr $0\main_libresocsim_interface2_converted_interface_adr[29:0] + update \main_libresocsim_interface2_converted_interface_sel $0\main_libresocsim_interface2_converted_interface_sel[3:0] + update \main_libresocsim_interface2_converted_interface_cyc $0\main_libresocsim_interface2_converted_interface_cyc[0:0] + update \main_libresocsim_interface2_converted_interface_stb $0\main_libresocsim_interface2_converted_interface_stb[0:0] + update \main_libresocsim_interface2_converted_interface_we $0\main_libresocsim_interface2_converted_interface_we[0:0] + update \main_libresocsim_converter2_skip $0\main_libresocsim_converter2_skip[0:0] + update \builder_converter2_next_state $0\builder_converter2_next_state[0:0] + update \main_libresocsim_converter2_counter_converter2_next_value $0\main_libresocsim_converter2_counter_converter2_next_value[0:0] + update \main_libresocsim_converter2_counter_converter2_next_value_ce $0\main_libresocsim_converter2_counter_converter2_next_value_ce[0:0] + end + attribute \src "ls180.v:290.11-290.36" + process $proc$ls180.v:290$2856 + assign { } { } + assign $1\main_sdram_storage[3:0] 4'0001 + sync always + sync init + update \main_sdram_storage $1\main_sdram_storage[3:0] + end + attribute \src "ls180.v:2908.1-2914.4" + process $proc$ls180.v:2908$47 + assign { } { } + assign { } { } + assign $0\main_libresocsim_we[3:0] [0] $and$ls180.v:2910$50_Y + assign $0\main_libresocsim_we[3:0] [1] $and$ls180.v:2911$53_Y + assign $0\main_libresocsim_we[3:0] [2] $and$ls180.v:2912$56_Y + assign $0\main_libresocsim_we[3:0] [3] $and$ls180.v:2913$59_Y + sync always + update \main_libresocsim_we $0\main_libresocsim_we[3:0] + end + attribute \src "ls180.v:291.5-291.25" + process $proc$ls180.v:291$2857 + assign { } { } + assign $1\main_sdram_re[0:0] 1'0 + sync always + sync init + update \main_sdram_re $1\main_sdram_re[0:0] + end + attribute \src "ls180.v:292.11-292.44" + process $proc$ls180.v:292$2858 + assign { } { } + assign $1\main_sdram_command_storage[5:0] 6'000000 + sync always + sync init + update \main_sdram_command_storage $1\main_sdram_command_storage[5:0] + end + attribute \src "ls180.v:2920.1-2925.4" + process $proc$ls180.v:2920$61 + assign { } { } + assign $0\main_libresocsim_zero_clear[0:0] 1'0 + attribute \src "ls180.v:2922.2-2924.5" + switch $and$ls180.v:2922$62_Y + attribute \src "ls180.v:2922.6-2922.90" + case 1'1 + assign $0\main_libresocsim_zero_clear[0:0] 1'1 + case + end + sync always + update \main_libresocsim_zero_clear $0\main_libresocsim_zero_clear[0:0] + end + attribute \src "ls180.v:293.5-293.33" + process $proc$ls180.v:293$2859 + assign { } { } + assign $1\main_sdram_command_re[0:0] 1'0 + sync always + sync init + update \main_sdram_command_re $1\main_sdram_command_re[0:0] + end + attribute \src "ls180.v:2964.1-3018.4" + process $proc$ls180.v:2964$64 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdram_master_p0_bank[1:0] 2'00 + assign $0\main_sdram_master_p0_cas_n[0:0] 1'1 + assign $0\main_sdram_master_p0_cs_n[0:0] 1'1 + assign $0\main_sdram_master_p0_ras_n[0:0] 1'1 + assign $0\main_sdram_master_p0_we_n[0:0] 1'1 + assign $0\main_sdram_master_p0_cke[0:0] 1'0 + assign $0\main_sdram_master_p0_odt[0:0] 1'0 + assign $0\main_sdram_master_p0_reset_n[0:0] 1'0 + assign $0\main_sdram_master_p0_act_n[0:0] 1'1 + assign $0\main_sdram_inti_p0_rddata[15:0] 16'0000000000000000 + assign $0\main_sdram_master_p0_wrdata[15:0] 16'0000000000000000 + assign $0\main_sdram_inti_p0_rddata_valid[0:0] 1'0 + assign $0\main_sdram_master_p0_wrdata_en[0:0] 1'0 + assign $0\main_sdram_master_p0_wrdata_mask[1:0] 2'00 + assign $0\main_sdram_master_p0_rddata_en[0:0] 1'0 + assign $0\main_sdram_slave_p0_rddata[15:0] 16'0000000000000000 + assign $0\main_sdram_slave_p0_rddata_valid[0:0] 1'0 + assign $0\main_sdram_master_p0_address[12:0] 13'0000000000000 + attribute \src "ls180.v:2983.2-3017.5" + switch \main_sdram_sel + attribute \src "ls180.v:2983.6-2983.20" + case 1'1 + assign $0\main_sdram_master_p0_address[12:0] \main_sdram_slave_p0_address + assign $0\main_sdram_master_p0_bank[1:0] \main_sdram_slave_p0_bank + assign $0\main_sdram_master_p0_cas_n[0:0] \main_sdram_slave_p0_cas_n + assign $0\main_sdram_master_p0_cs_n[0:0] \main_sdram_slave_p0_cs_n + assign $0\main_sdram_master_p0_ras_n[0:0] \main_sdram_slave_p0_ras_n + assign $0\main_sdram_master_p0_we_n[0:0] \main_sdram_slave_p0_we_n + assign $0\main_sdram_master_p0_cke[0:0] \main_sdram_slave_p0_cke + assign $0\main_sdram_master_p0_odt[0:0] \main_sdram_slave_p0_odt + assign $0\main_sdram_master_p0_reset_n[0:0] \main_sdram_slave_p0_reset_n + assign $0\main_sdram_master_p0_act_n[0:0] \main_sdram_slave_p0_act_n + assign $0\main_sdram_master_p0_wrdata[15:0] \main_sdram_slave_p0_wrdata + assign $0\main_sdram_master_p0_wrdata_en[0:0] \main_sdram_slave_p0_wrdata_en + assign $0\main_sdram_master_p0_wrdata_mask[1:0] \main_sdram_slave_p0_wrdata_mask + assign $0\main_sdram_master_p0_rddata_en[0:0] \main_sdram_slave_p0_rddata_en + assign $0\main_sdram_slave_p0_rddata[15:0] \main_sdram_master_p0_rddata + assign $0\main_sdram_slave_p0_rddata_valid[0:0] \main_sdram_master_p0_rddata_valid + attribute \src "ls180.v:3000.6-3000.10" + case + assign $0\main_sdram_master_p0_address[12:0] \main_sdram_inti_p0_address + assign $0\main_sdram_master_p0_bank[1:0] \main_sdram_inti_p0_bank + assign $0\main_sdram_master_p0_cas_n[0:0] \main_sdram_inti_p0_cas_n + assign $0\main_sdram_master_p0_cs_n[0:0] \main_sdram_inti_p0_cs_n + assign $0\main_sdram_master_p0_ras_n[0:0] \main_sdram_inti_p0_ras_n + assign $0\main_sdram_master_p0_we_n[0:0] \main_sdram_inti_p0_we_n + assign $0\main_sdram_master_p0_cke[0:0] \main_sdram_inti_p0_cke + assign $0\main_sdram_master_p0_odt[0:0] \main_sdram_inti_p0_odt + assign $0\main_sdram_master_p0_reset_n[0:0] \main_sdram_inti_p0_reset_n + assign $0\main_sdram_master_p0_act_n[0:0] \main_sdram_inti_p0_act_n + assign $0\main_sdram_master_p0_wrdata[15:0] \main_sdram_inti_p0_wrdata + assign $0\main_sdram_master_p0_wrdata_en[0:0] \main_sdram_inti_p0_wrdata_en + assign $0\main_sdram_master_p0_wrdata_mask[1:0] \main_sdram_inti_p0_wrdata_mask + assign $0\main_sdram_master_p0_rddata_en[0:0] \main_sdram_inti_p0_rddata_en + assign $0\main_sdram_inti_p0_rddata[15:0] \main_sdram_master_p0_rddata + assign $0\main_sdram_inti_p0_rddata_valid[0:0] \main_sdram_master_p0_rddata_valid + end + sync always + update \main_sdram_inti_p0_rddata $0\main_sdram_inti_p0_rddata[15:0] + update \main_sdram_inti_p0_rddata_valid $0\main_sdram_inti_p0_rddata_valid[0:0] + update \main_sdram_slave_p0_rddata $0\main_sdram_slave_p0_rddata[15:0] + update \main_sdram_slave_p0_rddata_valid $0\main_sdram_slave_p0_rddata_valid[0:0] + update \main_sdram_master_p0_address $0\main_sdram_master_p0_address[12:0] + update \main_sdram_master_p0_bank $0\main_sdram_master_p0_bank[1:0] + update \main_sdram_master_p0_cas_n $0\main_sdram_master_p0_cas_n[0:0] + update \main_sdram_master_p0_cs_n $0\main_sdram_master_p0_cs_n[0:0] + update \main_sdram_master_p0_ras_n $0\main_sdram_master_p0_ras_n[0:0] + update \main_sdram_master_p0_we_n $0\main_sdram_master_p0_we_n[0:0] + update \main_sdram_master_p0_cke $0\main_sdram_master_p0_cke[0:0] + update \main_sdram_master_p0_odt $0\main_sdram_master_p0_odt[0:0] + update \main_sdram_master_p0_reset_n $0\main_sdram_master_p0_reset_n[0:0] + update \main_sdram_master_p0_act_n $0\main_sdram_master_p0_act_n[0:0] + update \main_sdram_master_p0_wrdata $0\main_sdram_master_p0_wrdata[15:0] + update \main_sdram_master_p0_wrdata_en $0\main_sdram_master_p0_wrdata_en[0:0] + update \main_sdram_master_p0_wrdata_mask $0\main_sdram_master_p0_wrdata_mask[1:0] + update \main_sdram_master_p0_rddata_en $0\main_sdram_master_p0_rddata_en[0:0] + end + attribute \src "ls180.v:297.5-297.38" + process $proc$ls180.v:297$2860 + assign { } { } + assign $0\main_sdram_command_issue_w[0:0] 1'0 + sync always + update \main_sdram_command_issue_w $0\main_sdram_command_issue_w[0:0] + sync init + end + attribute \src "ls180.v:298.12-298.46" + process $proc$ls180.v:298$2861 + assign { } { } + assign $1\main_sdram_address_storage[12:0] 13'0000000000000 + sync always + sync init + update \main_sdram_address_storage $1\main_sdram_address_storage[12:0] + end + attribute \src "ls180.v:299.5-299.33" + process $proc$ls180.v:299$2862 + assign { } { } + assign $1\main_sdram_address_re[0:0] 1'0 + sync always + sync init + update \main_sdram_address_re $1\main_sdram_address_re[0:0] + end + attribute \src "ls180.v:300.11-300.45" + process $proc$ls180.v:300$2863 + assign { } { } + assign $1\main_sdram_baddress_storage[1:0] 2'00 + sync always + sync init + update \main_sdram_baddress_storage $1\main_sdram_baddress_storage[1:0] + end + attribute \src "ls180.v:301.5-301.34" + process $proc$ls180.v:301$2864 + assign { } { } + assign $1\main_sdram_baddress_re[0:0] 1'0 + sync always + sync init + update \main_sdram_baddress_re $1\main_sdram_baddress_re[0:0] + end + attribute \src "ls180.v:302.12-302.45" + process $proc$ls180.v:302$2865 + assign { } { } + assign $1\main_sdram_wrdata_storage[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdram_wrdata_storage $1\main_sdram_wrdata_storage[15:0] + end + attribute \src "ls180.v:3022.1-3038.4" + process $proc$ls180.v:3022$65 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdram_inti_p0_cas_n[0:0] 1'1 + assign $0\main_sdram_inti_p0_cs_n[0:0] 1'1 + assign $0\main_sdram_inti_p0_ras_n[0:0] 1'1 + assign $0\main_sdram_inti_p0_we_n[0:0] 1'1 + attribute \src "ls180.v:3027.2-3037.5" + switch \main_sdram_command_issue_re + attribute \src "ls180.v:3027.6-3027.33" + case 1'1 + assign $0\main_sdram_inti_p0_cs_n[0:0] $not$ls180.v:3028$66_Y + assign $0\main_sdram_inti_p0_we_n[0:0] $not$ls180.v:3029$67_Y + assign $0\main_sdram_inti_p0_cas_n[0:0] $not$ls180.v:3030$68_Y + assign $0\main_sdram_inti_p0_ras_n[0:0] $not$ls180.v:3031$69_Y + attribute \src "ls180.v:3032.6-3032.10" + case + assign $0\main_sdram_inti_p0_cs_n[0:0] 1'1 + assign $0\main_sdram_inti_p0_we_n[0:0] 1'1 + assign $0\main_sdram_inti_p0_cas_n[0:0] 1'1 + assign $0\main_sdram_inti_p0_ras_n[0:0] 1'1 + end + sync always + update \main_sdram_inti_p0_cas_n $0\main_sdram_inti_p0_cas_n[0:0] + update \main_sdram_inti_p0_cs_n $0\main_sdram_inti_p0_cs_n[0:0] + update \main_sdram_inti_p0_ras_n $0\main_sdram_inti_p0_ras_n[0:0] + update \main_sdram_inti_p0_we_n $0\main_sdram_inti_p0_we_n[0:0] + end + attribute \src "ls180.v:303.5-303.32" + process $proc$ls180.v:303$2866 + assign { } { } + assign $1\main_sdram_wrdata_re[0:0] 1'0 + sync always + sync init + update \main_sdram_wrdata_re $1\main_sdram_wrdata_re[0:0] + end + attribute \src "ls180.v:304.12-304.37" + process $proc$ls180.v:304$2867 + assign { } { } + assign $1\main_sdram_status[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdram_status $1\main_sdram_status[15:0] + end + attribute \src "ls180.v:3081.1-3111.4" + process $proc$ls180.v:3081$78 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdram_cmd_last[0:0] 1'0 + assign $0\main_sdram_sequencer_start0[0:0] 1'0 + assign $0\main_sdram_cmd_valid[0:0] 1'0 + assign $0\builder_refresher_next_state[1:0] \builder_refresher_state + attribute \src "ls180.v:3087.2-3110.9" + switch \builder_refresher_state + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\main_sdram_cmd_valid[0:0] 1'1 + attribute \src "ls180.v:3090.4-3093.7" + switch \main_sdram_cmd_ready + attribute \src "ls180.v:3090.8-3090.28" + case 1'1 + assign $0\main_sdram_sequencer_start0[0:0] 1'1 + assign $0\builder_refresher_next_state[1:0] 2'10 + case + end + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\main_sdram_cmd_valid[0:0] 1'1 + attribute \src "ls180.v:3097.4-3101.7" + switch \main_sdram_sequencer_done0 + attribute \src "ls180.v:3097.8-3097.34" + case 1'1 + assign $0\main_sdram_cmd_valid[0:0] 1'0 + assign $0\main_sdram_cmd_last[0:0] 1'1 + assign $0\builder_refresher_next_state[1:0] 2'00 + case + end + attribute \src "ls180.v:0.0-0.0" + case + attribute \src "ls180.v:3104.4-3108.7" + switch 1'1 + attribute \src "ls180.v:3104.8-3104.12" + case 1'1 + attribute \src "ls180.v:3105.5-3107.8" + switch \main_sdram_wants_refresh + attribute \src "ls180.v:3105.9-3105.33" + case 1'1 + assign $0\builder_refresher_next_state[1:0] 2'01 + case + end + case + end + end + sync always + update \main_sdram_cmd_valid $0\main_sdram_cmd_valid[0:0] + update \main_sdram_cmd_last $0\main_sdram_cmd_last[0:0] + update \main_sdram_sequencer_start0 $0\main_sdram_sequencer_start0[0:0] + update \builder_refresher_next_state $0\builder_refresher_next_state[1:0] + end + attribute \src "ls180.v:3126.1-3133.4" + process $proc$ls180.v:3126$82 + assign { } { } + assign $0\main_sdram_bankmachine0_cmd_payload_a[12:0] 13'0000000000000 + attribute \src "ls180.v:3128.2-3132.5" + switch \main_sdram_bankmachine0_row_col_n_addr_sel + attribute \src "ls180.v:3128.6-3128.48" + case 1'1 + assign $0\main_sdram_bankmachine0_cmd_payload_a[12:0] \main_sdram_bankmachine0_cmd_buffer_source_payload_addr [21:9] + attribute \src "ls180.v:3130.6-3130.10" + case + assign $0\main_sdram_bankmachine0_cmd_payload_a[12:0] $or$ls180.v:3131$84_Y + end + sync always + update \main_sdram_bankmachine0_cmd_payload_a $0\main_sdram_bankmachine0_cmd_payload_a[12:0] + end + attribute \src "ls180.v:3137.1-3144.4" + process $proc$ls180.v:3137$91 + assign { } { } + assign $0\main_sdram_bankmachine0_auto_precharge[0:0] 1'0 + attribute \src "ls180.v:3139.2-3143.5" + switch $and$ls180.v:3139$92_Y + attribute \src "ls180.v:3139.6-3139.115" + case 1'1 + attribute \src "ls180.v:3140.3-3142.6" + switch $ne$ls180.v:3140$93_Y + attribute \src "ls180.v:3140.7-3140.143" + case 1'1 + assign $0\main_sdram_bankmachine0_auto_precharge[0:0] $eq$ls180.v:3141$94_Y + case + end + case + end + sync always + update \main_sdram_bankmachine0_auto_precharge $0\main_sdram_bankmachine0_auto_precharge[0:0] + end + attribute \src "ls180.v:3159.1-3166.4" + process $proc$ls180.v:3159$95 + assign { } { } + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 + attribute \src "ls180.v:3161.2-3165.5" + switch \main_sdram_bankmachine0_cmd_buffer_lookahead_replace + attribute \src "ls180.v:3161.6-3161.58" + case 1'1 + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3162$96_Y + attribute \src "ls180.v:3163.6-3163.10" + case + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] \main_sdram_bankmachine0_cmd_buffer_lookahead_produce + end + sync always + update \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] + end + attribute \src "ls180.v:3175.1-3268.4" + process $proc$ls180.v:3175$104 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdram_bankmachine0_row_open[0:0] 1'0 + assign $0\main_sdram_bankmachine0_row_close[0:0] 1'0 + assign $0\main_sdram_bankmachine0_cmd_payload_cas[0:0] 1'0 + assign $0\main_sdram_bankmachine0_cmd_payload_ras[0:0] 1'0 + assign $0\main_sdram_bankmachine0_cmd_payload_we[0:0] 1'0 + assign $0\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] 1'0 + assign $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'0 + assign $0\main_sdram_bankmachine0_cmd_payload_is_read[0:0] 1'0 + assign $0\main_sdram_bankmachine0_cmd_payload_is_write[0:0] 1'0 + assign $0\main_sdram_bankmachine0_req_wdata_ready[0:0] 1'0 + assign $0\main_sdram_bankmachine0_req_rdata_valid[0:0] 1'0 + assign $0\main_sdram_bankmachine0_refresh_gnt[0:0] 1'0 + assign $0\main_sdram_bankmachine0_cmd_valid[0:0] 1'0 + assign $0\builder_bankmachine0_next_state[2:0] \builder_bankmachine0_state + attribute \src "ls180.v:3191.2-3267.9" + switch \builder_bankmachine0_state + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\main_sdram_bankmachine0_row_close[0:0] 1'1 + attribute \src "ls180.v:3193.4-3201.7" + switch $and$ls180.v:3193$105_Y + attribute \src "ls180.v:3193.8-3193.87" + case 1'1 + assign $0\main_sdram_bankmachine0_cmd_valid[0:0] 1'1 + assign $0\main_sdram_bankmachine0_cmd_payload_ras[0:0] 1'1 + assign $0\main_sdram_bankmachine0_cmd_payload_we[0:0] 1'1 + assign $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'1 + attribute \src "ls180.v:3195.5-3197.8" + switch \main_sdram_bankmachine0_cmd_ready + attribute \src "ls180.v:3195.9-3195.42" + case 1'1 + assign $0\builder_bankmachine0_next_state[2:0] 3'101 + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\main_sdram_bankmachine0_row_close[0:0] 1'1 + attribute \src "ls180.v:3205.4-3207.7" + switch $and$ls180.v:3205$106_Y + attribute \src "ls180.v:3205.8-3205.87" + case 1'1 + assign $0\builder_bankmachine0_next_state[2:0] 3'101 + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'011 + attribute \src "ls180.v:3211.4-3220.7" + switch \main_sdram_bankmachine0_trccon_ready + attribute \src "ls180.v:3211.8-3211.44" + case 1'1 + assign $0\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] 1'1 + assign $0\main_sdram_bankmachine0_row_open[0:0] 1'1 + assign $0\main_sdram_bankmachine0_cmd_valid[0:0] 1'1 + assign $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'1 + assign $0\main_sdram_bankmachine0_cmd_payload_ras[0:0] 1'1 + attribute \src "ls180.v:3216.5-3218.8" + switch \main_sdram_bankmachine0_cmd_ready + attribute \src "ls180.v:3216.9-3216.42" + case 1'1 + assign $0\builder_bankmachine0_next_state[2:0] 3'110 + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\main_sdram_bankmachine0_row_close[0:0] 1'1 + assign $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'1 + attribute \src "ls180.v:3223.4-3225.7" + switch \main_sdram_bankmachine0_twtpcon_ready + attribute \src "ls180.v:3223.8-3223.45" + case 1'1 + assign $0\main_sdram_bankmachine0_refresh_gnt[0:0] 1'1 + case + end + attribute \src "ls180.v:3228.4-3230.7" + switch $not$ls180.v:3228$107_Y + attribute \src "ls180.v:3228.8-3228.46" + case 1'1 + assign $0\builder_bankmachine0_next_state[2:0] 3'000 + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'101 + assign $0\builder_bankmachine0_next_state[2:0] 3'011 + attribute \src "ls180.v:0.0-0.0" + case 3'110 + assign $0\builder_bankmachine0_next_state[2:0] 3'000 + attribute \src "ls180.v:0.0-0.0" + case + attribute \src "ls180.v:3239.4-3265.7" + switch \main_sdram_bankmachine0_refresh_req + attribute \src "ls180.v:3239.8-3239.43" + case 1'1 + assign $0\builder_bankmachine0_next_state[2:0] 3'100 + attribute \src "ls180.v:3241.8-3241.12" + case + attribute \src "ls180.v:3242.5-3264.8" + switch \main_sdram_bankmachine0_cmd_buffer_source_valid + attribute \src "ls180.v:3242.9-3242.56" + case 1'1 + attribute \src "ls180.v:3243.6-3263.9" + switch \main_sdram_bankmachine0_row_opened + attribute \src "ls180.v:3243.10-3243.44" + case 1'1 + attribute \src "ls180.v:3244.7-3260.10" + switch \main_sdram_bankmachine0_row_hit + attribute \src "ls180.v:3244.11-3244.42" + case 1'1 + assign $0\main_sdram_bankmachine0_cmd_valid[0:0] 1'1 + assign $0\main_sdram_bankmachine0_cmd_payload_cas[0:0] 1'1 + attribute \src "ls180.v:3246.8-3253.11" + switch \main_sdram_bankmachine0_cmd_buffer_source_payload_we + attribute \src "ls180.v:3246.12-3246.64" + case 1'1 + assign $0\main_sdram_bankmachine0_req_wdata_ready[0:0] \main_sdram_bankmachine0_cmd_ready + assign $0\main_sdram_bankmachine0_cmd_payload_is_write[0:0] 1'1 + assign $0\main_sdram_bankmachine0_cmd_payload_we[0:0] 1'1 + attribute \src "ls180.v:3250.12-3250.16" + case + assign $0\main_sdram_bankmachine0_req_rdata_valid[0:0] \main_sdram_bankmachine0_cmd_ready + assign $0\main_sdram_bankmachine0_cmd_payload_is_read[0:0] 1'1 + end + attribute \src "ls180.v:3255.8-3257.11" + switch $and$ls180.v:3255$108_Y + attribute \src "ls180.v:3255.12-3255.88" + case 1'1 + assign $0\builder_bankmachine0_next_state[2:0] 3'010 + case + end + attribute \src "ls180.v:3258.11-3258.15" + case + assign $0\builder_bankmachine0_next_state[2:0] 3'001 + end + attribute \src "ls180.v:3261.10-3261.14" + case + assign $0\builder_bankmachine0_next_state[2:0] 3'011 + end + case + end + end + end + sync always + update \main_sdram_bankmachine0_req_wdata_ready $0\main_sdram_bankmachine0_req_wdata_ready[0:0] + update \main_sdram_bankmachine0_req_rdata_valid $0\main_sdram_bankmachine0_req_rdata_valid[0:0] + update \main_sdram_bankmachine0_refresh_gnt $0\main_sdram_bankmachine0_refresh_gnt[0:0] + update \main_sdram_bankmachine0_cmd_valid $0\main_sdram_bankmachine0_cmd_valid[0:0] + update \main_sdram_bankmachine0_cmd_payload_cas $0\main_sdram_bankmachine0_cmd_payload_cas[0:0] + update \main_sdram_bankmachine0_cmd_payload_ras $0\main_sdram_bankmachine0_cmd_payload_ras[0:0] + update \main_sdram_bankmachine0_cmd_payload_we $0\main_sdram_bankmachine0_cmd_payload_we[0:0] + update \main_sdram_bankmachine0_cmd_payload_is_cmd $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] + update \main_sdram_bankmachine0_cmd_payload_is_read $0\main_sdram_bankmachine0_cmd_payload_is_read[0:0] + update \main_sdram_bankmachine0_cmd_payload_is_write $0\main_sdram_bankmachine0_cmd_payload_is_write[0:0] + update \main_sdram_bankmachine0_row_open $0\main_sdram_bankmachine0_row_open[0:0] + update \main_sdram_bankmachine0_row_close $0\main_sdram_bankmachine0_row_close[0:0] + update \main_sdram_bankmachine0_row_col_n_addr_sel $0\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] + update \builder_bankmachine0_next_state $0\builder_bankmachine0_next_state[2:0] + end + attribute \src "ls180.v:3283.1-3290.4" + process $proc$ls180.v:3283$112 + assign { } { } + assign $0\main_sdram_bankmachine1_cmd_payload_a[12:0] 13'0000000000000 + attribute \src "ls180.v:3285.2-3289.5" + switch \main_sdram_bankmachine1_row_col_n_addr_sel + attribute \src "ls180.v:3285.6-3285.48" + case 1'1 + assign $0\main_sdram_bankmachine1_cmd_payload_a[12:0] \main_sdram_bankmachine1_cmd_buffer_source_payload_addr [21:9] + attribute \src "ls180.v:3287.6-3287.10" + case + assign $0\main_sdram_bankmachine1_cmd_payload_a[12:0] $or$ls180.v:3288$114_Y + end + sync always + update \main_sdram_bankmachine1_cmd_payload_a $0\main_sdram_bankmachine1_cmd_payload_a[12:0] + end + attribute \src "ls180.v:3294.1-3301.4" + process $proc$ls180.v:3294$121 + assign { } { } + assign $0\main_sdram_bankmachine1_auto_precharge[0:0] 1'0 + attribute \src "ls180.v:3296.2-3300.5" + switch $and$ls180.v:3296$122_Y + attribute \src "ls180.v:3296.6-3296.115" + case 1'1 + attribute \src "ls180.v:3297.3-3299.6" + switch $ne$ls180.v:3297$123_Y + attribute \src "ls180.v:3297.7-3297.143" + case 1'1 + assign $0\main_sdram_bankmachine1_auto_precharge[0:0] $eq$ls180.v:3298$124_Y + case + end + case + end + sync always + update \main_sdram_bankmachine1_auto_precharge $0\main_sdram_bankmachine1_auto_precharge[0:0] + end + attribute \src "ls180.v:3316.1-3323.4" + process $proc$ls180.v:3316$125 + assign { } { } + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 + attribute \src "ls180.v:3318.2-3322.5" + switch \main_sdram_bankmachine1_cmd_buffer_lookahead_replace + attribute \src "ls180.v:3318.6-3318.58" + case 1'1 + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3319$126_Y + attribute \src "ls180.v:3320.6-3320.10" + case + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] \main_sdram_bankmachine1_cmd_buffer_lookahead_produce + end + sync always + update \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] + end + attribute \src "ls180.v:3332.1-3425.4" + process $proc$ls180.v:3332$134 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdram_bankmachine1_req_rdata_valid[0:0] 1'0 + assign $0\main_sdram_bankmachine1_refresh_gnt[0:0] 1'0 + assign $0\main_sdram_bankmachine1_cmd_valid[0:0] 1'0 + assign $0\main_sdram_bankmachine1_row_open[0:0] 1'0 + assign $0\main_sdram_bankmachine1_row_close[0:0] 1'0 + assign $0\main_sdram_bankmachine1_cmd_payload_cas[0:0] 1'0 + assign $0\main_sdram_bankmachine1_cmd_payload_ras[0:0] 1'0 + assign $0\main_sdram_bankmachine1_cmd_payload_we[0:0] 1'0 + assign $0\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] 1'0 + assign $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'0 + assign $0\main_sdram_bankmachine1_cmd_payload_is_read[0:0] 1'0 + assign $0\main_sdram_bankmachine1_cmd_payload_is_write[0:0] 1'0 + assign $0\main_sdram_bankmachine1_req_wdata_ready[0:0] 1'0 + assign { } { } + assign $0\builder_bankmachine1_next_state[2:0] \builder_bankmachine1_state + attribute \src "ls180.v:3348.2-3424.9" + switch \builder_bankmachine1_state + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\main_sdram_bankmachine1_row_close[0:0] 1'1 + attribute \src "ls180.v:3350.4-3358.7" + switch $and$ls180.v:3350$135_Y + attribute \src "ls180.v:3350.8-3350.87" + case 1'1 + assign $0\main_sdram_bankmachine1_cmd_valid[0:0] 1'1 + assign $0\main_sdram_bankmachine1_cmd_payload_ras[0:0] 1'1 + assign $0\main_sdram_bankmachine1_cmd_payload_we[0:0] 1'1 + assign $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'1 + attribute \src "ls180.v:3352.5-3354.8" + switch \main_sdram_bankmachine1_cmd_ready + attribute \src "ls180.v:3352.9-3352.42" + case 1'1 + assign $0\builder_bankmachine1_next_state[2:0] 3'101 + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\main_sdram_bankmachine1_row_close[0:0] 1'1 + attribute \src "ls180.v:3362.4-3364.7" + switch $and$ls180.v:3362$136_Y + attribute \src "ls180.v:3362.8-3362.87" + case 1'1 + assign $0\builder_bankmachine1_next_state[2:0] 3'101 + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'011 + attribute \src "ls180.v:3368.4-3377.7" + switch \main_sdram_bankmachine1_trccon_ready + attribute \src "ls180.v:3368.8-3368.44" + case 1'1 + assign $0\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] 1'1 + assign $0\main_sdram_bankmachine1_row_open[0:0] 1'1 + assign $0\main_sdram_bankmachine1_cmd_valid[0:0] 1'1 + assign $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'1 + assign $0\main_sdram_bankmachine1_cmd_payload_ras[0:0] 1'1 + attribute \src "ls180.v:3373.5-3375.8" + switch \main_sdram_bankmachine1_cmd_ready + attribute \src "ls180.v:3373.9-3373.42" + case 1'1 + assign $0\builder_bankmachine1_next_state[2:0] 3'110 + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\main_sdram_bankmachine1_row_close[0:0] 1'1 + assign $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'1 + attribute \src "ls180.v:3380.4-3382.7" + switch \main_sdram_bankmachine1_twtpcon_ready + attribute \src "ls180.v:3380.8-3380.45" + case 1'1 + assign $0\main_sdram_bankmachine1_refresh_gnt[0:0] 1'1 + case + end + attribute \src "ls180.v:3385.4-3387.7" + switch $not$ls180.v:3385$137_Y + attribute \src "ls180.v:3385.8-3385.46" + case 1'1 + assign $0\builder_bankmachine1_next_state[2:0] 3'000 + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'101 + assign $0\builder_bankmachine1_next_state[2:0] 3'011 + attribute \src "ls180.v:0.0-0.0" + case 3'110 + assign $0\builder_bankmachine1_next_state[2:0] 3'000 + attribute \src "ls180.v:0.0-0.0" + case + attribute \src "ls180.v:3396.4-3422.7" + switch \main_sdram_bankmachine1_refresh_req + attribute \src "ls180.v:3396.8-3396.43" + case 1'1 + assign $0\builder_bankmachine1_next_state[2:0] 3'100 + attribute \src "ls180.v:3398.8-3398.12" + case + attribute \src "ls180.v:3399.5-3421.8" + switch \main_sdram_bankmachine1_cmd_buffer_source_valid + attribute \src "ls180.v:3399.9-3399.56" + case 1'1 + attribute \src "ls180.v:3400.6-3420.9" + switch \main_sdram_bankmachine1_row_opened + attribute \src "ls180.v:3400.10-3400.44" + case 1'1 + attribute \src "ls180.v:3401.7-3417.10" + switch \main_sdram_bankmachine1_row_hit + attribute \src "ls180.v:3401.11-3401.42" + case 1'1 + assign $0\main_sdram_bankmachine1_cmd_valid[0:0] 1'1 + assign $0\main_sdram_bankmachine1_cmd_payload_cas[0:0] 1'1 + attribute \src "ls180.v:3403.8-3410.11" + switch \main_sdram_bankmachine1_cmd_buffer_source_payload_we + attribute \src "ls180.v:3403.12-3403.64" + case 1'1 + assign $0\main_sdram_bankmachine1_req_wdata_ready[0:0] \main_sdram_bankmachine1_cmd_ready + assign $0\main_sdram_bankmachine1_cmd_payload_is_write[0:0] 1'1 + assign $0\main_sdram_bankmachine1_cmd_payload_we[0:0] 1'1 + attribute \src "ls180.v:3407.12-3407.16" + case + assign $0\main_sdram_bankmachine1_req_rdata_valid[0:0] \main_sdram_bankmachine1_cmd_ready + assign $0\main_sdram_bankmachine1_cmd_payload_is_read[0:0] 1'1 + end + attribute \src "ls180.v:3412.8-3414.11" + switch $and$ls180.v:3412$138_Y + attribute \src "ls180.v:3412.12-3412.88" + case 1'1 + assign $0\builder_bankmachine1_next_state[2:0] 3'010 + case + end + attribute \src "ls180.v:3415.11-3415.15" + case + assign $0\builder_bankmachine1_next_state[2:0] 3'001 + end + attribute \src "ls180.v:3418.10-3418.14" + case + assign $0\builder_bankmachine1_next_state[2:0] 3'011 + end + case + end + end + end + sync always + update \main_sdram_bankmachine1_req_wdata_ready $0\main_sdram_bankmachine1_req_wdata_ready[0:0] + update \main_sdram_bankmachine1_req_rdata_valid $0\main_sdram_bankmachine1_req_rdata_valid[0:0] + update \main_sdram_bankmachine1_refresh_gnt $0\main_sdram_bankmachine1_refresh_gnt[0:0] + update \main_sdram_bankmachine1_cmd_valid $0\main_sdram_bankmachine1_cmd_valid[0:0] + update \main_sdram_bankmachine1_cmd_payload_cas $0\main_sdram_bankmachine1_cmd_payload_cas[0:0] + update \main_sdram_bankmachine1_cmd_payload_ras $0\main_sdram_bankmachine1_cmd_payload_ras[0:0] + update \main_sdram_bankmachine1_cmd_payload_we $0\main_sdram_bankmachine1_cmd_payload_we[0:0] + update \main_sdram_bankmachine1_cmd_payload_is_cmd $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] + update \main_sdram_bankmachine1_cmd_payload_is_read $0\main_sdram_bankmachine1_cmd_payload_is_read[0:0] + update \main_sdram_bankmachine1_cmd_payload_is_write $0\main_sdram_bankmachine1_cmd_payload_is_write[0:0] + update \main_sdram_bankmachine1_row_open $0\main_sdram_bankmachine1_row_open[0:0] + update \main_sdram_bankmachine1_row_close $0\main_sdram_bankmachine1_row_close[0:0] + update \main_sdram_bankmachine1_row_col_n_addr_sel $0\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] + update \builder_bankmachine1_next_state $0\builder_bankmachine1_next_state[2:0] + end + attribute \src "ls180.v:334.12-334.46" + process $proc$ls180.v:334$2868 + assign { } { } + assign $1\main_sdram_interface_wdata[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdram_interface_wdata $1\main_sdram_interface_wdata[15:0] + end + attribute \src "ls180.v:335.11-335.47" + process $proc$ls180.v:335$2869 + assign { } { } + assign $1\main_sdram_interface_wdata_we[1:0] 2'00 + sync always + sync init + update \main_sdram_interface_wdata_we $1\main_sdram_interface_wdata_we[1:0] + end + attribute \src "ls180.v:337.12-337.45" + process $proc$ls180.v:337$2870 + assign { } { } + assign $1\main_sdram_dfi_p0_address[12:0] 13'0000000000000 + sync always + sync init + update \main_sdram_dfi_p0_address $1\main_sdram_dfi_p0_address[12:0] + end + attribute \src "ls180.v:338.11-338.40" + process $proc$ls180.v:338$2871 + assign { } { } + assign $1\main_sdram_dfi_p0_bank[1:0] 2'00 + sync always + sync init + update \main_sdram_dfi_p0_bank $1\main_sdram_dfi_p0_bank[1:0] + end + attribute \src "ls180.v:339.5-339.35" + process $proc$ls180.v:339$2872 + assign { } { } + assign $1\main_sdram_dfi_p0_cas_n[0:0] 1'1 + sync always + sync init + update \main_sdram_dfi_p0_cas_n $1\main_sdram_dfi_p0_cas_n[0:0] + end + attribute \src "ls180.v:340.5-340.34" + process $proc$ls180.v:340$2873 + assign { } { } + assign $1\main_sdram_dfi_p0_cs_n[0:0] 1'1 + sync always + sync init + update \main_sdram_dfi_p0_cs_n $1\main_sdram_dfi_p0_cs_n[0:0] + end + attribute \src "ls180.v:341.5-341.35" + process $proc$ls180.v:341$2874 + assign { } { } + assign $1\main_sdram_dfi_p0_ras_n[0:0] 1'1 + sync always + sync init + update \main_sdram_dfi_p0_ras_n $1\main_sdram_dfi_p0_ras_n[0:0] + end + attribute \src "ls180.v:342.5-342.34" + process $proc$ls180.v:342$2875 + assign { } { } + assign $1\main_sdram_dfi_p0_we_n[0:0] 1'1 + sync always + sync init + update \main_sdram_dfi_p0_we_n $1\main_sdram_dfi_p0_we_n[0:0] + end + attribute \src "ls180.v:3440.1-3447.4" + process $proc$ls180.v:3440$142 + assign { } { } + assign $0\main_sdram_bankmachine2_cmd_payload_a[12:0] 13'0000000000000 + attribute \src "ls180.v:3442.2-3446.5" + switch \main_sdram_bankmachine2_row_col_n_addr_sel + attribute \src "ls180.v:3442.6-3442.48" + case 1'1 + assign $0\main_sdram_bankmachine2_cmd_payload_a[12:0] \main_sdram_bankmachine2_cmd_buffer_source_payload_addr [21:9] + attribute \src "ls180.v:3444.6-3444.10" + case + assign $0\main_sdram_bankmachine2_cmd_payload_a[12:0] $or$ls180.v:3445$144_Y + end + sync always + update \main_sdram_bankmachine2_cmd_payload_a $0\main_sdram_bankmachine2_cmd_payload_a[12:0] + end + attribute \src "ls180.v:3451.1-3458.4" + process $proc$ls180.v:3451$151 + assign { } { } + assign $0\main_sdram_bankmachine2_auto_precharge[0:0] 1'0 + attribute \src "ls180.v:3453.2-3457.5" + switch $and$ls180.v:3453$152_Y + attribute \src "ls180.v:3453.6-3453.115" + case 1'1 + attribute \src "ls180.v:3454.3-3456.6" + switch $ne$ls180.v:3454$153_Y + attribute \src "ls180.v:3454.7-3454.143" + case 1'1 + assign $0\main_sdram_bankmachine2_auto_precharge[0:0] $eq$ls180.v:3455$154_Y + case + end + case + end + sync always + update \main_sdram_bankmachine2_auto_precharge $0\main_sdram_bankmachine2_auto_precharge[0:0] + end + attribute \src "ls180.v:346.5-346.35" + process $proc$ls180.v:346$2876 + assign { } { } + assign $0\main_sdram_dfi_p0_act_n[0:0] 1'1 + sync always + update \main_sdram_dfi_p0_act_n $0\main_sdram_dfi_p0_act_n[0:0] + sync init + end + attribute \src "ls180.v:3473.1-3480.4" + process $proc$ls180.v:3473$155 + assign { } { } + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 + attribute \src "ls180.v:3475.2-3479.5" + switch \main_sdram_bankmachine2_cmd_buffer_lookahead_replace + attribute \src "ls180.v:3475.6-3475.58" + case 1'1 + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3476$156_Y + attribute \src "ls180.v:3477.6-3477.10" + case + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] \main_sdram_bankmachine2_cmd_buffer_lookahead_produce + end + sync always + update \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] + end + attribute \src "ls180.v:348.5-348.39" + process $proc$ls180.v:348$2877 + assign { } { } + assign $1\main_sdram_dfi_p0_wrdata_en[0:0] 1'0 + sync always + sync init + update \main_sdram_dfi_p0_wrdata_en $1\main_sdram_dfi_p0_wrdata_en[0:0] + end + attribute \src "ls180.v:3489.1-3582.4" + process $proc$ls180.v:3489$164 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdram_bankmachine2_cmd_payload_is_write[0:0] 1'0 + assign $0\main_sdram_bankmachine2_req_wdata_ready[0:0] 1'0 + assign $0\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] 1'0 + assign $0\main_sdram_bankmachine2_req_rdata_valid[0:0] 1'0 + assign $0\main_sdram_bankmachine2_refresh_gnt[0:0] 1'0 + assign $0\main_sdram_bankmachine2_cmd_valid[0:0] 1'0 + assign $0\main_sdram_bankmachine2_row_open[0:0] 1'0 + assign $0\main_sdram_bankmachine2_row_close[0:0] 1'0 + assign $0\main_sdram_bankmachine2_cmd_payload_ras[0:0] 1'0 + assign $0\main_sdram_bankmachine2_cmd_payload_cas[0:0] 1'0 + assign { } { } + assign $0\main_sdram_bankmachine2_cmd_payload_we[0:0] 1'0 + assign $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'0 + assign $0\main_sdram_bankmachine2_cmd_payload_is_read[0:0] 1'0 + assign $0\builder_bankmachine2_next_state[2:0] \builder_bankmachine2_state + attribute \src "ls180.v:3505.2-3581.9" + switch \builder_bankmachine2_state + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\main_sdram_bankmachine2_row_close[0:0] 1'1 + attribute \src "ls180.v:3507.4-3515.7" + switch $and$ls180.v:3507$165_Y + attribute \src "ls180.v:3507.8-3507.87" + case 1'1 + assign $0\main_sdram_bankmachine2_cmd_valid[0:0] 1'1 + assign $0\main_sdram_bankmachine2_cmd_payload_ras[0:0] 1'1 + assign $0\main_sdram_bankmachine2_cmd_payload_we[0:0] 1'1 + assign $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'1 + attribute \src "ls180.v:3509.5-3511.8" + switch \main_sdram_bankmachine2_cmd_ready + attribute \src "ls180.v:3509.9-3509.42" + case 1'1 + assign $0\builder_bankmachine2_next_state[2:0] 3'101 + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\main_sdram_bankmachine2_row_close[0:0] 1'1 + attribute \src "ls180.v:3519.4-3521.7" + switch $and$ls180.v:3519$166_Y + attribute \src "ls180.v:3519.8-3519.87" + case 1'1 + assign $0\builder_bankmachine2_next_state[2:0] 3'101 + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'011 + attribute \src "ls180.v:3525.4-3534.7" + switch \main_sdram_bankmachine2_trccon_ready + attribute \src "ls180.v:3525.8-3525.44" + case 1'1 + assign $0\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] 1'1 + assign $0\main_sdram_bankmachine2_row_open[0:0] 1'1 + assign $0\main_sdram_bankmachine2_cmd_valid[0:0] 1'1 + assign $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'1 + assign $0\main_sdram_bankmachine2_cmd_payload_ras[0:0] 1'1 + attribute \src "ls180.v:3530.5-3532.8" + switch \main_sdram_bankmachine2_cmd_ready + attribute \src "ls180.v:3530.9-3530.42" + case 1'1 + assign $0\builder_bankmachine2_next_state[2:0] 3'110 + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\main_sdram_bankmachine2_row_close[0:0] 1'1 + assign $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'1 + attribute \src "ls180.v:3537.4-3539.7" + switch \main_sdram_bankmachine2_twtpcon_ready + attribute \src "ls180.v:3537.8-3537.45" + case 1'1 + assign $0\main_sdram_bankmachine2_refresh_gnt[0:0] 1'1 + case + end + attribute \src "ls180.v:3542.4-3544.7" + switch $not$ls180.v:3542$167_Y + attribute \src "ls180.v:3542.8-3542.46" + case 1'1 + assign $0\builder_bankmachine2_next_state[2:0] 3'000 + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'101 + assign $0\builder_bankmachine2_next_state[2:0] 3'011 + attribute \src "ls180.v:0.0-0.0" + case 3'110 + assign $0\builder_bankmachine2_next_state[2:0] 3'000 + attribute \src "ls180.v:0.0-0.0" + case + attribute \src "ls180.v:3553.4-3579.7" + switch \main_sdram_bankmachine2_refresh_req + attribute \src "ls180.v:3553.8-3553.43" + case 1'1 + assign $0\builder_bankmachine2_next_state[2:0] 3'100 + attribute \src "ls180.v:3555.8-3555.12" + case + attribute \src "ls180.v:3556.5-3578.8" + switch \main_sdram_bankmachine2_cmd_buffer_source_valid + attribute \src "ls180.v:3556.9-3556.56" + case 1'1 + attribute \src "ls180.v:3557.6-3577.9" + switch \main_sdram_bankmachine2_row_opened + attribute \src "ls180.v:3557.10-3557.44" + case 1'1 + attribute \src "ls180.v:3558.7-3574.10" + switch \main_sdram_bankmachine2_row_hit + attribute \src "ls180.v:3558.11-3558.42" + case 1'1 + assign $0\main_sdram_bankmachine2_cmd_valid[0:0] 1'1 + assign $0\main_sdram_bankmachine2_cmd_payload_cas[0:0] 1'1 + attribute \src "ls180.v:3560.8-3567.11" + switch \main_sdram_bankmachine2_cmd_buffer_source_payload_we + attribute \src "ls180.v:3560.12-3560.64" + case 1'1 + assign $0\main_sdram_bankmachine2_req_wdata_ready[0:0] \main_sdram_bankmachine2_cmd_ready + assign $0\main_sdram_bankmachine2_cmd_payload_is_write[0:0] 1'1 + assign $0\main_sdram_bankmachine2_cmd_payload_we[0:0] 1'1 + attribute \src "ls180.v:3564.12-3564.16" + case + assign $0\main_sdram_bankmachine2_req_rdata_valid[0:0] \main_sdram_bankmachine2_cmd_ready + assign $0\main_sdram_bankmachine2_cmd_payload_is_read[0:0] 1'1 + end + attribute \src "ls180.v:3569.8-3571.11" + switch $and$ls180.v:3569$168_Y + attribute \src "ls180.v:3569.12-3569.88" + case 1'1 + assign $0\builder_bankmachine2_next_state[2:0] 3'010 + case + end + attribute \src "ls180.v:3572.11-3572.15" + case + assign $0\builder_bankmachine2_next_state[2:0] 3'001 + end + attribute \src "ls180.v:3575.10-3575.14" + case + assign $0\builder_bankmachine2_next_state[2:0] 3'011 + end + case + end + end + end + sync always + update \main_sdram_bankmachine2_req_wdata_ready $0\main_sdram_bankmachine2_req_wdata_ready[0:0] + update \main_sdram_bankmachine2_req_rdata_valid $0\main_sdram_bankmachine2_req_rdata_valid[0:0] + update \main_sdram_bankmachine2_refresh_gnt $0\main_sdram_bankmachine2_refresh_gnt[0:0] + update \main_sdram_bankmachine2_cmd_valid $0\main_sdram_bankmachine2_cmd_valid[0:0] + update \main_sdram_bankmachine2_cmd_payload_cas $0\main_sdram_bankmachine2_cmd_payload_cas[0:0] + update \main_sdram_bankmachine2_cmd_payload_ras $0\main_sdram_bankmachine2_cmd_payload_ras[0:0] + update \main_sdram_bankmachine2_cmd_payload_we $0\main_sdram_bankmachine2_cmd_payload_we[0:0] + update \main_sdram_bankmachine2_cmd_payload_is_cmd $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] + update \main_sdram_bankmachine2_cmd_payload_is_read $0\main_sdram_bankmachine2_cmd_payload_is_read[0:0] + update \main_sdram_bankmachine2_cmd_payload_is_write $0\main_sdram_bankmachine2_cmd_payload_is_write[0:0] + update \main_sdram_bankmachine2_row_open $0\main_sdram_bankmachine2_row_open[0:0] + update \main_sdram_bankmachine2_row_close $0\main_sdram_bankmachine2_row_close[0:0] + update \main_sdram_bankmachine2_row_col_n_addr_sel $0\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] + update \builder_bankmachine2_next_state $0\builder_bankmachine2_next_state[2:0] + end + attribute \src "ls180.v:350.5-350.39" + process $proc$ls180.v:350$2878 + assign { } { } + assign $1\main_sdram_dfi_p0_rddata_en[0:0] 1'0 + sync always + sync init + update \main_sdram_dfi_p0_rddata_en $1\main_sdram_dfi_p0_rddata_en[0:0] + end + attribute \src "ls180.v:353.5-353.32" + process $proc$ls180.v:353$2879 + assign { } { } + assign $1\main_sdram_cmd_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_cmd_valid $1\main_sdram_cmd_valid[0:0] + end + attribute \src "ls180.v:354.5-354.32" + process $proc$ls180.v:354$2880 + assign { } { } + assign $1\main_sdram_cmd_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_cmd_ready $1\main_sdram_cmd_ready[0:0] + end + attribute \src "ls180.v:355.5-355.31" + process $proc$ls180.v:355$2881 + assign { } { } + assign $1\main_sdram_cmd_last[0:0] 1'0 + sync always + sync init + update \main_sdram_cmd_last $1\main_sdram_cmd_last[0:0] + end + attribute \src "ls180.v:356.12-356.44" + process $proc$ls180.v:356$2882 + assign { } { } + assign $1\main_sdram_cmd_payload_a[12:0] 13'0000000000000 + sync always + sync init + update \main_sdram_cmd_payload_a $1\main_sdram_cmd_payload_a[12:0] + end + attribute \src "ls180.v:357.11-357.43" + process $proc$ls180.v:357$2883 + assign { } { } + assign $1\main_sdram_cmd_payload_ba[1:0] 2'00 + sync always + sync init + update \main_sdram_cmd_payload_ba $1\main_sdram_cmd_payload_ba[1:0] + end + attribute \src "ls180.v:358.5-358.38" + process $proc$ls180.v:358$2884 + assign { } { } + assign $1\main_sdram_cmd_payload_cas[0:0] 1'0 + sync always + sync init + update \main_sdram_cmd_payload_cas $1\main_sdram_cmd_payload_cas[0:0] + end + attribute \src "ls180.v:359.5-359.38" + process $proc$ls180.v:359$2885 + assign { } { } + assign $1\main_sdram_cmd_payload_ras[0:0] 1'0 + sync always + sync init + update \main_sdram_cmd_payload_ras $1\main_sdram_cmd_payload_ras[0:0] + end + attribute \src "ls180.v:3597.1-3604.4" + process $proc$ls180.v:3597$172 + assign { } { } + assign $0\main_sdram_bankmachine3_cmd_payload_a[12:0] 13'0000000000000 + attribute \src "ls180.v:3599.2-3603.5" + switch \main_sdram_bankmachine3_row_col_n_addr_sel + attribute \src "ls180.v:3599.6-3599.48" + case 1'1 + assign $0\main_sdram_bankmachine3_cmd_payload_a[12:0] \main_sdram_bankmachine3_cmd_buffer_source_payload_addr [21:9] + attribute \src "ls180.v:3601.6-3601.10" + case + assign $0\main_sdram_bankmachine3_cmd_payload_a[12:0] $or$ls180.v:3602$174_Y + end + sync always + update \main_sdram_bankmachine3_cmd_payload_a $0\main_sdram_bankmachine3_cmd_payload_a[12:0] + end + attribute \src "ls180.v:360.5-360.37" + process $proc$ls180.v:360$2886 + assign { } { } + assign $1\main_sdram_cmd_payload_we[0:0] 1'0 + sync always + sync init + update \main_sdram_cmd_payload_we $1\main_sdram_cmd_payload_we[0:0] + end + attribute \src "ls180.v:3608.1-3615.4" + process $proc$ls180.v:3608$181 + assign { } { } + assign $0\main_sdram_bankmachine3_auto_precharge[0:0] 1'0 + attribute \src "ls180.v:3610.2-3614.5" + switch $and$ls180.v:3610$182_Y + attribute \src "ls180.v:3610.6-3610.115" + case 1'1 + attribute \src "ls180.v:3611.3-3613.6" + switch $ne$ls180.v:3611$183_Y + attribute \src "ls180.v:3611.7-3611.143" + case 1'1 + assign $0\main_sdram_bankmachine3_auto_precharge[0:0] $eq$ls180.v:3612$184_Y + case + end + case + end + sync always + update \main_sdram_bankmachine3_auto_precharge $0\main_sdram_bankmachine3_auto_precharge[0:0] + end + attribute \src "ls180.v:361.5-361.42" + process $proc$ls180.v:361$2887 + assign { } { } + assign $0\main_sdram_cmd_payload_is_read[0:0] 1'0 + sync always + update \main_sdram_cmd_payload_is_read $0\main_sdram_cmd_payload_is_read[0:0] + sync init + end + attribute \src "ls180.v:362.5-362.43" + process $proc$ls180.v:362$2888 + assign { } { } + assign $0\main_sdram_cmd_payload_is_write[0:0] 1'0 + sync always + update \main_sdram_cmd_payload_is_write $0\main_sdram_cmd_payload_is_write[0:0] + sync init + end + attribute \src "ls180.v:3630.1-3637.4" + process $proc$ls180.v:3630$185 + assign { } { } + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 + attribute \src "ls180.v:3632.2-3636.5" + switch \main_sdram_bankmachine3_cmd_buffer_lookahead_replace + attribute \src "ls180.v:3632.6-3632.58" + case 1'1 + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3633$186_Y + attribute \src "ls180.v:3634.6-3634.10" + case + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] \main_sdram_bankmachine3_cmd_buffer_lookahead_produce + end + sync always + update \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] + end + attribute \src "ls180.v:3646.1-3739.4" + process $proc$ls180.v:3646$194 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdram_bankmachine3_cmd_payload_ras[0:0] 1'0 + assign $0\main_sdram_bankmachine3_cmd_payload_we[0:0] 1'0 + assign $0\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] 1'0 + assign $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'0 + assign $0\main_sdram_bankmachine3_cmd_payload_is_read[0:0] 1'0 + assign $0\main_sdram_bankmachine3_cmd_payload_is_write[0:0] 1'0 + assign $0\main_sdram_bankmachine3_req_wdata_ready[0:0] 1'0 + assign $0\main_sdram_bankmachine3_req_rdata_valid[0:0] 1'0 + assign $0\main_sdram_bankmachine3_refresh_gnt[0:0] 1'0 + assign $0\main_sdram_bankmachine3_cmd_valid[0:0] 1'0 + assign { } { } + assign $0\main_sdram_bankmachine3_row_open[0:0] 1'0 + assign $0\main_sdram_bankmachine3_row_close[0:0] 1'0 + assign $0\main_sdram_bankmachine3_cmd_payload_cas[0:0] 1'0 + assign $0\builder_bankmachine3_next_state[2:0] \builder_bankmachine3_state + attribute \src "ls180.v:3662.2-3738.9" + switch \builder_bankmachine3_state + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\main_sdram_bankmachine3_row_close[0:0] 1'1 + attribute \src "ls180.v:3664.4-3672.7" + switch $and$ls180.v:3664$195_Y + attribute \src "ls180.v:3664.8-3664.87" + case 1'1 + assign $0\main_sdram_bankmachine3_cmd_valid[0:0] 1'1 + assign $0\main_sdram_bankmachine3_cmd_payload_ras[0:0] 1'1 + assign $0\main_sdram_bankmachine3_cmd_payload_we[0:0] 1'1 + assign $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'1 + attribute \src "ls180.v:3666.5-3668.8" + switch \main_sdram_bankmachine3_cmd_ready + attribute \src "ls180.v:3666.9-3666.42" + case 1'1 + assign $0\builder_bankmachine3_next_state[2:0] 3'101 + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\main_sdram_bankmachine3_row_close[0:0] 1'1 + attribute \src "ls180.v:3676.4-3678.7" + switch $and$ls180.v:3676$196_Y + attribute \src "ls180.v:3676.8-3676.87" + case 1'1 + assign $0\builder_bankmachine3_next_state[2:0] 3'101 + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'011 + attribute \src "ls180.v:3682.4-3691.7" + switch \main_sdram_bankmachine3_trccon_ready + attribute \src "ls180.v:3682.8-3682.44" + case 1'1 + assign $0\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] 1'1 + assign $0\main_sdram_bankmachine3_row_open[0:0] 1'1 + assign $0\main_sdram_bankmachine3_cmd_valid[0:0] 1'1 + assign $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'1 + assign $0\main_sdram_bankmachine3_cmd_payload_ras[0:0] 1'1 + attribute \src "ls180.v:3687.5-3689.8" + switch \main_sdram_bankmachine3_cmd_ready + attribute \src "ls180.v:3687.9-3687.42" + case 1'1 + assign $0\builder_bankmachine3_next_state[2:0] 3'110 + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\main_sdram_bankmachine3_row_close[0:0] 1'1 + assign $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'1 + attribute \src "ls180.v:3694.4-3696.7" + switch \main_sdram_bankmachine3_twtpcon_ready + attribute \src "ls180.v:3694.8-3694.45" + case 1'1 + assign $0\main_sdram_bankmachine3_refresh_gnt[0:0] 1'1 + case + end + attribute \src "ls180.v:3699.4-3701.7" + switch $not$ls180.v:3699$197_Y + attribute \src "ls180.v:3699.8-3699.46" + case 1'1 + assign $0\builder_bankmachine3_next_state[2:0] 3'000 + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'101 + assign $0\builder_bankmachine3_next_state[2:0] 3'011 + attribute \src "ls180.v:0.0-0.0" + case 3'110 + assign $0\builder_bankmachine3_next_state[2:0] 3'000 + attribute \src "ls180.v:0.0-0.0" + case + attribute \src "ls180.v:3710.4-3736.7" + switch \main_sdram_bankmachine3_refresh_req + attribute \src "ls180.v:3710.8-3710.43" + case 1'1 + assign $0\builder_bankmachine3_next_state[2:0] 3'100 + attribute \src "ls180.v:3712.8-3712.12" + case + attribute \src "ls180.v:3713.5-3735.8" + switch \main_sdram_bankmachine3_cmd_buffer_source_valid + attribute \src "ls180.v:3713.9-3713.56" + case 1'1 + attribute \src "ls180.v:3714.6-3734.9" + switch \main_sdram_bankmachine3_row_opened + attribute \src "ls180.v:3714.10-3714.44" + case 1'1 + attribute \src "ls180.v:3715.7-3731.10" + switch \main_sdram_bankmachine3_row_hit + attribute \src "ls180.v:3715.11-3715.42" + case 1'1 + assign $0\main_sdram_bankmachine3_cmd_valid[0:0] 1'1 + assign $0\main_sdram_bankmachine3_cmd_payload_cas[0:0] 1'1 + attribute \src "ls180.v:3717.8-3724.11" + switch \main_sdram_bankmachine3_cmd_buffer_source_payload_we + attribute \src "ls180.v:3717.12-3717.64" + case 1'1 + assign $0\main_sdram_bankmachine3_req_wdata_ready[0:0] \main_sdram_bankmachine3_cmd_ready + assign $0\main_sdram_bankmachine3_cmd_payload_is_write[0:0] 1'1 + assign $0\main_sdram_bankmachine3_cmd_payload_we[0:0] 1'1 + attribute \src "ls180.v:3721.12-3721.16" + case + assign $0\main_sdram_bankmachine3_req_rdata_valid[0:0] \main_sdram_bankmachine3_cmd_ready + assign $0\main_sdram_bankmachine3_cmd_payload_is_read[0:0] 1'1 + end + attribute \src "ls180.v:3726.8-3728.11" + switch $and$ls180.v:3726$198_Y + attribute \src "ls180.v:3726.12-3726.88" + case 1'1 + assign $0\builder_bankmachine3_next_state[2:0] 3'010 + case + end + attribute \src "ls180.v:3729.11-3729.15" + case + assign $0\builder_bankmachine3_next_state[2:0] 3'001 + end + attribute \src "ls180.v:3732.10-3732.14" + case + assign $0\builder_bankmachine3_next_state[2:0] 3'011 + end + case + end + end + end + sync always + update \main_sdram_bankmachine3_req_wdata_ready $0\main_sdram_bankmachine3_req_wdata_ready[0:0] + update \main_sdram_bankmachine3_req_rdata_valid $0\main_sdram_bankmachine3_req_rdata_valid[0:0] + update \main_sdram_bankmachine3_refresh_gnt $0\main_sdram_bankmachine3_refresh_gnt[0:0] + update \main_sdram_bankmachine3_cmd_valid $0\main_sdram_bankmachine3_cmd_valid[0:0] + update \main_sdram_bankmachine3_cmd_payload_cas $0\main_sdram_bankmachine3_cmd_payload_cas[0:0] + update \main_sdram_bankmachine3_cmd_payload_ras $0\main_sdram_bankmachine3_cmd_payload_ras[0:0] + update \main_sdram_bankmachine3_cmd_payload_we $0\main_sdram_bankmachine3_cmd_payload_we[0:0] + update \main_sdram_bankmachine3_cmd_payload_is_cmd $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] + update \main_sdram_bankmachine3_cmd_payload_is_read $0\main_sdram_bankmachine3_cmd_payload_is_read[0:0] + update \main_sdram_bankmachine3_cmd_payload_is_write $0\main_sdram_bankmachine3_cmd_payload_is_write[0:0] + update \main_sdram_bankmachine3_row_open $0\main_sdram_bankmachine3_row_open[0:0] + update \main_sdram_bankmachine3_row_close $0\main_sdram_bankmachine3_row_close[0:0] + update \main_sdram_bankmachine3_row_col_n_addr_sel $0\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] + update \builder_bankmachine3_next_state $0\builder_bankmachine3_next_state[2:0] + end + attribute \src "ls180.v:368.11-368.44" + process $proc$ls180.v:368$2889 + assign { } { } + assign $1\main_sdram_timer_count1[9:0] 10'1100001101 + sync always + sync init + update \main_sdram_timer_count1 $1\main_sdram_timer_count1[9:0] + end + attribute \src "ls180.v:370.5-370.38" + process $proc$ls180.v:370$2890 + assign { } { } + assign $1\main_sdram_postponer_req_o[0:0] 1'0 + sync always + sync init + update \main_sdram_postponer_req_o $1\main_sdram_postponer_req_o[0:0] + end + attribute \src "ls180.v:371.5-371.38" + process $proc$ls180.v:371$2891 + assign { } { } + assign $1\main_sdram_postponer_count[0:0] 1'0 + sync always + sync init + update \main_sdram_postponer_count $1\main_sdram_postponer_count[0:0] + end + attribute \src "ls180.v:372.5-372.39" + process $proc$ls180.v:372$2892 + assign { } { } + assign $1\main_sdram_sequencer_start0[0:0] 1'0 + sync always + sync init + update \main_sdram_sequencer_start0 $1\main_sdram_sequencer_start0[0:0] + end + attribute \src "ls180.v:375.5-375.38" + process $proc$ls180.v:375$2893 + assign { } { } + assign $1\main_sdram_sequencer_done1[0:0] 1'0 + sync always + sync init + update \main_sdram_sequencer_done1 $1\main_sdram_sequencer_done1[0:0] + end + attribute \src "ls180.v:3759.1-3765.4" + process $proc$ls180.v:3759$237 + assign { } { } + assign { } { } + assign $0\main_sdram_choose_cmd_valids[3:0] [0] $and$ls180.v:3761$250_Y + assign $0\main_sdram_choose_cmd_valids[3:0] [1] $and$ls180.v:3762$263_Y + assign $0\main_sdram_choose_cmd_valids[3:0] [2] $and$ls180.v:3763$276_Y + assign $0\main_sdram_choose_cmd_valids[3:0] [3] $and$ls180.v:3764$289_Y + sync always + update \main_sdram_choose_cmd_valids $0\main_sdram_choose_cmd_valids[3:0] + end + attribute \src "ls180.v:376.11-376.46" + process $proc$ls180.v:376$2894 + assign { } { } + assign $1\main_sdram_sequencer_counter[3:0] 4'0000 + sync always + sync init + update \main_sdram_sequencer_counter $1\main_sdram_sequencer_counter[3:0] + end + attribute \src "ls180.v:377.5-377.38" + process $proc$ls180.v:377$2895 + assign { } { } + assign $1\main_sdram_sequencer_count[0:0] 1'0 + sync always + sync init + update \main_sdram_sequencer_count $1\main_sdram_sequencer_count[0:0] + end + attribute \src "ls180.v:3773.1-3778.4" + process $proc$ls180.v:3773$290 + assign { } { } + assign $0\main_sdram_choose_cmd_cmd_payload_cas[0:0] 1'0 + attribute \src "ls180.v:3775.2-3777.5" + switch \main_sdram_choose_cmd_cmd_valid + attribute \src "ls180.v:3775.6-3775.37" + case 1'1 + assign $0\main_sdram_choose_cmd_cmd_payload_cas[0:0] \builder_comb_t_array_muxed0 + case + end + sync always + update \main_sdram_choose_cmd_cmd_payload_cas $0\main_sdram_choose_cmd_cmd_payload_cas[0:0] + end + attribute \src "ls180.v:3779.1-3784.4" + process $proc$ls180.v:3779$291 + assign { } { } + assign $0\main_sdram_choose_cmd_cmd_payload_ras[0:0] 1'0 + attribute \src "ls180.v:3781.2-3783.5" + switch \main_sdram_choose_cmd_cmd_valid + attribute \src "ls180.v:3781.6-3781.37" + case 1'1 + assign $0\main_sdram_choose_cmd_cmd_payload_ras[0:0] \builder_comb_t_array_muxed1 + case + end + sync always + update \main_sdram_choose_cmd_cmd_payload_ras $0\main_sdram_choose_cmd_cmd_payload_ras[0:0] + end + attribute \src "ls180.v:3785.1-3790.4" + process $proc$ls180.v:3785$292 + assign { } { } + assign $0\main_sdram_choose_cmd_cmd_payload_we[0:0] 1'0 + attribute \src "ls180.v:3787.2-3789.5" + switch \main_sdram_choose_cmd_cmd_valid + attribute \src "ls180.v:3787.6-3787.37" + case 1'1 + assign $0\main_sdram_choose_cmd_cmd_payload_we[0:0] \builder_comb_t_array_muxed2 + case + end + sync always + update \main_sdram_choose_cmd_cmd_payload_we $0\main_sdram_choose_cmd_cmd_payload_we[0:0] + end + attribute \src "ls180.v:3792.1-3798.4" + process $proc$ls180.v:3792$295 + assign { } { } + assign { } { } + assign $0\main_sdram_choose_req_valids[3:0] [0] $and$ls180.v:3794$308_Y + assign $0\main_sdram_choose_req_valids[3:0] [1] $and$ls180.v:3795$321_Y + assign $0\main_sdram_choose_req_valids[3:0] [2] $and$ls180.v:3796$334_Y + assign $0\main_sdram_choose_req_valids[3:0] [3] $and$ls180.v:3797$347_Y + sync always + update \main_sdram_choose_req_valids $0\main_sdram_choose_req_valids[3:0] + end + attribute \src "ls180.v:3806.1-3811.4" + process $proc$ls180.v:3806$348 + assign { } { } + assign $0\main_sdram_choose_req_cmd_payload_cas[0:0] 1'0 + attribute \src "ls180.v:3808.2-3810.5" + switch \main_sdram_choose_req_cmd_valid + attribute \src "ls180.v:3808.6-3808.37" + case 1'1 + assign $0\main_sdram_choose_req_cmd_payload_cas[0:0] \builder_comb_t_array_muxed3 + case + end + sync always + update \main_sdram_choose_req_cmd_payload_cas $0\main_sdram_choose_req_cmd_payload_cas[0:0] + end + attribute \src "ls180.v:3812.1-3817.4" + process $proc$ls180.v:3812$349 + assign { } { } + assign $0\main_sdram_choose_req_cmd_payload_ras[0:0] 1'0 + attribute \src "ls180.v:3814.2-3816.5" + switch \main_sdram_choose_req_cmd_valid + attribute \src "ls180.v:3814.6-3814.37" + case 1'1 + assign $0\main_sdram_choose_req_cmd_payload_ras[0:0] \builder_comb_t_array_muxed4 + case + end + sync always + update \main_sdram_choose_req_cmd_payload_ras $0\main_sdram_choose_req_cmd_payload_ras[0:0] + end + attribute \src "ls180.v:3818.1-3823.4" + process $proc$ls180.v:3818$350 + assign { } { } + assign $0\main_sdram_choose_req_cmd_payload_we[0:0] 1'0 + attribute \src "ls180.v:3820.2-3822.5" + switch \main_sdram_choose_req_cmd_valid + attribute \src "ls180.v:3820.6-3820.37" + case 1'1 + assign $0\main_sdram_choose_req_cmd_payload_we[0:0] \builder_comb_t_array_muxed5 + case + end + sync always + update \main_sdram_choose_req_cmd_payload_we $0\main_sdram_choose_req_cmd_payload_we[0:0] + end + attribute \src "ls180.v:3824.1-3832.4" + process $proc$ls180.v:3824$351 + assign { } { } + assign $0\main_sdram_bankmachine0_cmd_ready[0:0] 1'0 + attribute \src "ls180.v:3826.2-3828.5" + switch $and$ls180.v:3826$354_Y + attribute \src "ls180.v:3826.6-3826.115" + case 1'1 + assign $0\main_sdram_bankmachine0_cmd_ready[0:0] 1'1 + case + end + attribute \src "ls180.v:3829.2-3831.5" + switch $and$ls180.v:3829$357_Y + attribute \src "ls180.v:3829.6-3829.115" + case 1'1 + assign $0\main_sdram_bankmachine0_cmd_ready[0:0] 1'1 + case + end + sync always + update \main_sdram_bankmachine0_cmd_ready $0\main_sdram_bankmachine0_cmd_ready[0:0] + end + attribute \src "ls180.v:383.5-383.51" + process $proc$ls180.v:383$2896 + assign { } { } + assign $1\main_sdram_bankmachine0_req_wdata_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_req_wdata_ready $1\main_sdram_bankmachine0_req_wdata_ready[0:0] + end + attribute \src "ls180.v:3833.1-3841.4" + process $proc$ls180.v:3833$358 + assign { } { } + assign $0\main_sdram_bankmachine1_cmd_ready[0:0] 1'0 + attribute \src "ls180.v:3835.2-3837.5" + switch $and$ls180.v:3835$361_Y + attribute \src "ls180.v:3835.6-3835.115" + case 1'1 + assign $0\main_sdram_bankmachine1_cmd_ready[0:0] 1'1 + case + end + attribute \src "ls180.v:3838.2-3840.5" + switch $and$ls180.v:3838$364_Y + attribute \src "ls180.v:3838.6-3838.115" + case 1'1 + assign $0\main_sdram_bankmachine1_cmd_ready[0:0] 1'1 + case + end + sync always + update \main_sdram_bankmachine1_cmd_ready $0\main_sdram_bankmachine1_cmd_ready[0:0] + end + attribute \src "ls180.v:384.5-384.51" + process $proc$ls180.v:384$2897 + assign { } { } + assign $1\main_sdram_bankmachine0_req_rdata_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_req_rdata_valid $1\main_sdram_bankmachine0_req_rdata_valid[0:0] + end + attribute \src "ls180.v:3842.1-3850.4" + process $proc$ls180.v:3842$365 + assign { } { } + assign $0\main_sdram_bankmachine2_cmd_ready[0:0] 1'0 + attribute \src "ls180.v:3844.2-3846.5" + switch $and$ls180.v:3844$368_Y + attribute \src "ls180.v:3844.6-3844.115" + case 1'1 + assign $0\main_sdram_bankmachine2_cmd_ready[0:0] 1'1 + case + end + attribute \src "ls180.v:3847.2-3849.5" + switch $and$ls180.v:3847$371_Y + attribute \src "ls180.v:3847.6-3847.115" + case 1'1 + assign $0\main_sdram_bankmachine2_cmd_ready[0:0] 1'1 + case + end + sync always + update \main_sdram_bankmachine2_cmd_ready $0\main_sdram_bankmachine2_cmd_ready[0:0] + end + attribute \src "ls180.v:3851.1-3859.4" + process $proc$ls180.v:3851$372 + assign { } { } + assign $0\main_sdram_bankmachine3_cmd_ready[0:0] 1'0 + attribute \src "ls180.v:3853.2-3855.5" + switch $and$ls180.v:3853$375_Y + attribute \src "ls180.v:3853.6-3853.115" + case 1'1 + assign $0\main_sdram_bankmachine3_cmd_ready[0:0] 1'1 + case + end + attribute \src "ls180.v:3856.2-3858.5" + switch $and$ls180.v:3856$378_Y + attribute \src "ls180.v:3856.6-3856.115" + case 1'1 + assign $0\main_sdram_bankmachine3_cmd_ready[0:0] 1'1 + case + end + sync always + update \main_sdram_bankmachine3_cmd_ready $0\main_sdram_bankmachine3_cmd_ready[0:0] + end + attribute \src "ls180.v:386.5-386.47" + process $proc$ls180.v:386$2898 + assign { } { } + assign $1\main_sdram_bankmachine0_refresh_gnt[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_refresh_gnt $1\main_sdram_bankmachine0_refresh_gnt[0:0] + end + attribute \src "ls180.v:3864.1-3936.4" + process $proc$ls180.v:3864$381 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdram_en1[0:0] 1'0 + assign $0\main_sdram_choose_req_want_reads[0:0] 1'0 + assign $0\main_sdram_choose_req_want_writes[0:0] 1'0 + assign { } { } + assign { } { } + assign $0\main_sdram_cmd_ready[0:0] 1'0 + assign $0\main_sdram_steerer_sel[1:0] 2'00 + assign $0\main_sdram_choose_req_cmd_ready[0:0] 1'0 + assign $0\main_sdram_en0[0:0] 1'0 + assign $0\main_sdram_choose_req_want_activates[0:0] \main_sdram_ras_allowed + assign $0\builder_multiplexer_next_state[2:0] \builder_multiplexer_state + attribute \src "ls180.v:3876.2-3935.9" + switch \builder_multiplexer_state + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\main_sdram_en1[0:0] 1'1 + assign $0\main_sdram_choose_req_want_writes[0:0] 1'1 + assign $0\main_sdram_steerer_sel[1:0] 2'10 + attribute \src "ls180.v:3880.4-3886.7" + switch 1'1 + attribute \src "ls180.v:3880.8-3880.12" + case 1'1 + assign $0\main_sdram_choose_req_cmd_ready[0:0] $and$ls180.v:3881$388_Y + case + end + attribute \src "ls180.v:3888.4-3892.7" + switch \main_sdram_read_available + attribute \src "ls180.v:3888.8-3888.33" + case 1'1 + attribute \src "ls180.v:3889.5-3891.8" + switch $or$ls180.v:3889$390_Y + attribute \src "ls180.v:3889.9-3889.63" + case 1'1 + assign $0\builder_multiplexer_next_state[2:0] 3'011 + case + end + case + end + attribute \src "ls180.v:3893.4-3895.7" + switch \main_sdram_go_to_refresh + attribute \src "ls180.v:3893.8-3893.32" + case 1'1 + assign $0\builder_multiplexer_next_state[2:0] 3'010 + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\main_sdram_steerer_sel[1:0] 2'11 + assign $0\main_sdram_cmd_ready[0:0] 1'1 + attribute \src "ls180.v:3900.4-3902.7" + switch \main_sdram_cmd_last + attribute \src "ls180.v:3900.8-3900.27" + case 1'1 + assign $0\builder_multiplexer_next_state[2:0] 3'000 + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'011 + attribute \src "ls180.v:3905.4-3907.7" + switch \main_sdram_twtrcon_ready + attribute \src "ls180.v:3905.8-3905.32" + case 1'1 + assign $0\builder_multiplexer_next_state[2:0] 3'000 + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\builder_multiplexer_next_state[2:0] 3'101 + attribute \src "ls180.v:0.0-0.0" + case 3'101 + assign $0\builder_multiplexer_next_state[2:0] 3'001 + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_sdram_en0[0:0] 1'1 + assign $0\main_sdram_choose_req_want_reads[0:0] 1'1 + assign $0\main_sdram_steerer_sel[1:0] 2'10 + attribute \src "ls180.v:3918.4-3924.7" + switch 1'1 + attribute \src "ls180.v:3918.8-3918.12" + case 1'1 + assign $0\main_sdram_choose_req_cmd_ready[0:0] $and$ls180.v:3919$397_Y + case + end + attribute \src "ls180.v:3926.4-3930.7" + switch \main_sdram_write_available + attribute \src "ls180.v:3926.8-3926.34" + case 1'1 + attribute \src "ls180.v:3927.5-3929.8" + switch $or$ls180.v:3927$399_Y + attribute \src "ls180.v:3927.9-3927.62" + case 1'1 + assign $0\builder_multiplexer_next_state[2:0] 3'100 + case + end + case + end + attribute \src "ls180.v:3931.4-3933.7" + switch \main_sdram_go_to_refresh + attribute \src "ls180.v:3931.8-3931.32" + case 1'1 + assign $0\builder_multiplexer_next_state[2:0] 3'010 + case + end + end + sync always + update \main_sdram_cmd_ready $0\main_sdram_cmd_ready[0:0] + update \main_sdram_choose_req_want_reads $0\main_sdram_choose_req_want_reads[0:0] + update \main_sdram_choose_req_want_writes $0\main_sdram_choose_req_want_writes[0:0] + update \main_sdram_choose_req_want_activates $0\main_sdram_choose_req_want_activates[0:0] + update \main_sdram_choose_req_cmd_ready $0\main_sdram_choose_req_cmd_ready[0:0] + update \main_sdram_steerer_sel $0\main_sdram_steerer_sel[1:0] + update \main_sdram_en0 $0\main_sdram_en0[0:0] + update \main_sdram_en1 $0\main_sdram_en1[0:0] + update \builder_multiplexer_next_state $0\builder_multiplexer_next_state[2:0] + end + attribute \src "ls180.v:387.5-387.45" + process $proc$ls180.v:387$2899 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_cmd_valid $1\main_sdram_bankmachine0_cmd_valid[0:0] + end + attribute \src "ls180.v:388.5-388.45" + process $proc$ls180.v:388$2900 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_cmd_ready $1\main_sdram_bankmachine0_cmd_ready[0:0] + end + attribute \src "ls180.v:389.12-389.57" + process $proc$ls180.v:389$2901 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_payload_a[12:0] 13'0000000000000 + sync always + sync init + update \main_sdram_bankmachine0_cmd_payload_a $1\main_sdram_bankmachine0_cmd_payload_a[12:0] + end + attribute \src "ls180.v:391.5-391.51" + process $proc$ls180.v:391$2902 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_payload_cas[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_cmd_payload_cas $1\main_sdram_bankmachine0_cmd_payload_cas[0:0] + end + attribute \src "ls180.v:392.5-392.51" + process $proc$ls180.v:392$2903 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_payload_ras[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_cmd_payload_ras $1\main_sdram_bankmachine0_cmd_payload_ras[0:0] + end + attribute \src "ls180.v:393.5-393.50" + process $proc$ls180.v:393$2904 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_payload_we[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_cmd_payload_we $1\main_sdram_bankmachine0_cmd_payload_we[0:0] + end + attribute \src "ls180.v:394.5-394.54" + process $proc$ls180.v:394$2905 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_cmd_payload_is_cmd $1\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] + end + attribute \src "ls180.v:395.5-395.55" + process $proc$ls180.v:395$2906 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_payload_is_read[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_cmd_payload_is_read $1\main_sdram_bankmachine0_cmd_payload_is_read[0:0] + end + attribute \src "ls180.v:396.5-396.56" + process $proc$ls180.v:396$2907 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_payload_is_write[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_cmd_payload_is_write $1\main_sdram_bankmachine0_cmd_payload_is_write[0:0] + end + attribute \src "ls180.v:3960.1-3973.4" + process $proc$ls180.v:3960$528 + assign { } { } + assign { } { } + assign $0\main_sdram_interface_wdata[15:0] 16'0000000000000000 + assign $0\main_sdram_interface_wdata_we[1:0] 2'00 + attribute \src "ls180.v:3963.2-3972.9" + switch \builder_new_master_wdata_ready + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\main_sdram_interface_wdata[15:0] \main_port_wdata_payload_data + assign $0\main_sdram_interface_wdata_we[1:0] \main_port_wdata_payload_we + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_sdram_interface_wdata[15:0] 16'0000000000000000 + assign $0\main_sdram_interface_wdata_we[1:0] 2'00 + end + sync always + update \main_sdram_interface_wdata $0\main_sdram_interface_wdata[15:0] + update \main_sdram_interface_wdata_we $0\main_sdram_interface_wdata_we[1:0] + end + attribute \src "ls180.v:397.5-397.50" + process $proc$ls180.v:397$2908 + assign { } { } + assign $1\main_sdram_bankmachine0_auto_precharge[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_auto_precharge $1\main_sdram_bankmachine0_auto_precharge[0:0] + end + attribute \src "ls180.v:3980.1-3990.4" + process $proc$ls180.v:3980$530 + assign { } { } + assign $0\main_litedram_wb_dat_w[15:0] 16'0000000000000000 + attribute \src "ls180.v:3982.2-3989.9" + switch \main_converter_counter + attribute \src "ls180.v:0.0-0.0" + case 1'0 + assign $0\main_litedram_wb_dat_w[15:0] \main_wb_sdram_dat_w [15:0] + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\main_litedram_wb_dat_w[15:0] \main_wb_sdram_dat_w [31:16] + case + end + sync always + update \main_litedram_wb_dat_w $0\main_litedram_wb_dat_w[15:0] + end + attribute \src "ls180.v:3992.1-4038.4" + process $proc$ls180.v:3992$531 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_litedram_wb_adr[29:0] 30'000000000000000000000000000000 + assign $0\main_wb_sdram_ack[0:0] 1'0 + assign $0\main_litedram_wb_sel[1:0] 2'00 + assign $0\main_litedram_wb_cyc[0:0] 1'0 + assign $0\main_litedram_wb_stb[0:0] 1'0 + assign $0\main_litedram_wb_we[0:0] 1'0 + assign { } { } + assign $0\main_converter_counter_converter_next_value[0:0] 1'0 + assign $0\main_converter_skip[0:0] 1'0 + assign $0\main_converter_counter_converter_next_value_ce[0:0] 1'0 + assign $0\builder_converter_next_state[0:0] \builder_converter_state + attribute \src "ls180.v:4004.2-4037.9" + switch \builder_converter_state + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\main_litedram_wb_adr[29:0] { \main_wb_sdram_adr [28:0] \main_converter_counter } + attribute \src "ls180.v:4007.4-4014.11" + switch \main_converter_counter + attribute \src "ls180.v:0.0-0.0" + case 1'0 + assign $0\main_litedram_wb_sel[1:0] \main_wb_sdram_sel [1:0] + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\main_litedram_wb_sel[1:0] \main_wb_sdram_sel [3:2] + case + end + attribute \src "ls180.v:4015.4-4028.7" + switch $and$ls180.v:4015$532_Y + attribute \src "ls180.v:4015.8-4015.47" + case 1'1 + assign $0\main_converter_skip[0:0] $eq$ls180.v:4016$533_Y + assign $0\main_litedram_wb_we[0:0] \main_wb_sdram_we + assign $0\main_litedram_wb_cyc[0:0] $not$ls180.v:4018$534_Y + assign $0\main_litedram_wb_stb[0:0] $not$ls180.v:4019$535_Y + attribute \src "ls180.v:4020.5-4027.8" + switch $or$ls180.v:4020$536_Y + attribute \src "ls180.v:4020.9-4020.53" + case 1'1 + assign $0\main_converter_counter_converter_next_value[0:0] $add$ls180.v:4021$537_Y + assign $0\main_converter_counter_converter_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:4023.6-4026.9" + switch $eq$ls180.v:4023$538_Y + attribute \src "ls180.v:4023.10-4023.42" + case 1'1 + assign $0\main_wb_sdram_ack[0:0] 1'1 + assign $0\builder_converter_next_state[0:0] 1'0 + case + end + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_converter_counter_converter_next_value[0:0] 1'0 + assign $0\main_converter_counter_converter_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:4033.4-4035.7" + switch $and$ls180.v:4033$539_Y + attribute \src "ls180.v:4033.8-4033.47" + case 1'1 + assign $0\builder_converter_next_state[0:0] 1'1 + case + end + end + sync always + update \main_wb_sdram_ack $0\main_wb_sdram_ack[0:0] + update \main_litedram_wb_adr $0\main_litedram_wb_adr[29:0] + update \main_litedram_wb_sel $0\main_litedram_wb_sel[1:0] + update \main_litedram_wb_cyc $0\main_litedram_wb_cyc[0:0] + update \main_litedram_wb_stb $0\main_litedram_wb_stb[0:0] + update \main_litedram_wb_we $0\main_litedram_wb_we[0:0] + update \main_converter_skip $0\main_converter_skip[0:0] + update \builder_converter_next_state $0\builder_converter_next_state[0:0] + update \main_converter_counter_converter_next_value $0\main_converter_counter_converter_next_value[0:0] + update \main_converter_counter_converter_next_value_ce $0\main_converter_counter_converter_next_value_ce[0:0] + end + attribute \src "ls180.v:400.5-400.67" + process $proc$ls180.v:400$2909 + assign { } { } + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first[0:0] 1'0 + sync always + update \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first[0:0] + sync init + end + attribute \src "ls180.v:401.5-401.66" + process $proc$ls180.v:401$2910 + assign { } { } + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last[0:0] 1'0 + sync always + update \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last[0:0] + sync init + end + attribute \src "ls180.v:4083.1-4088.4" + process $proc$ls180.v:4083$571 + assign { } { } + assign $0\main_uart_tx_clear[0:0] 1'0 + attribute \src "ls180.v:4085.2-4087.5" + switch $and$ls180.v:4085$572_Y + attribute \src "ls180.v:4085.6-4085.79" + case 1'1 + assign $0\main_uart_tx_clear[0:0] 1'1 + case + end + sync always + update \main_uart_tx_clear $0\main_uart_tx_clear[0:0] + end + attribute \src "ls180.v:4089.1-4093.4" + process $proc$ls180.v:4089$573 + assign { } { } + assign { } { } + assign $0\main_uart_eventmanager_status_w[1:0] [0] \main_uart_tx_status + assign $0\main_uart_eventmanager_status_w[1:0] [1] \main_uart_rx_status + sync always + update \main_uart_eventmanager_status_w $0\main_uart_eventmanager_status_w[1:0] + end + attribute \src "ls180.v:4094.1-4099.4" + process $proc$ls180.v:4094$574 + assign { } { } + assign $0\main_uart_rx_clear[0:0] 1'0 + attribute \src "ls180.v:4096.2-4098.5" + switch $and$ls180.v:4096$575_Y + attribute \src "ls180.v:4096.6-4096.79" + case 1'1 + assign $0\main_uart_rx_clear[0:0] 1'1 + case + end + sync always + update \main_uart_rx_clear $0\main_uart_rx_clear[0:0] + end + attribute \src "ls180.v:4100.1-4104.4" + process $proc$ls180.v:4100$576 + assign { } { } + assign { } { } + assign $0\main_uart_eventmanager_pending_w[1:0] [0] \main_uart_tx_pending + assign $0\main_uart_eventmanager_pending_w[1:0] [1] \main_uart_rx_pending + sync always + update \main_uart_eventmanager_pending_w $0\main_uart_eventmanager_pending_w[1:0] + end + attribute \src "ls180.v:4122.1-4129.4" + process $proc$ls180.v:4122$584 + assign { } { } + assign $0\main_uart_tx_fifo_wrport_adr[3:0] 4'0000 + attribute \src "ls180.v:4124.2-4128.5" + switch \main_uart_tx_fifo_replace + attribute \src "ls180.v:4124.6-4124.31" + case 1'1 + assign $0\main_uart_tx_fifo_wrport_adr[3:0] $sub$ls180.v:4125$585_Y + attribute \src "ls180.v:4126.6-4126.10" + case + assign $0\main_uart_tx_fifo_wrport_adr[3:0] \main_uart_tx_fifo_produce + end + sync always + update \main_uart_tx_fifo_wrport_adr $0\main_uart_tx_fifo_wrport_adr[3:0] + end + attribute \src "ls180.v:4152.1-4159.4" + process $proc$ls180.v:4152$595 + assign { } { } + assign $0\main_uart_rx_fifo_wrport_adr[3:0] 4'0000 + attribute \src "ls180.v:4154.2-4158.5" + switch \main_uart_rx_fifo_replace + attribute \src "ls180.v:4154.6-4154.31" + case 1'1 + assign $0\main_uart_rx_fifo_wrport_adr[3:0] $sub$ls180.v:4155$596_Y + attribute \src "ls180.v:4156.6-4156.10" + case + assign $0\main_uart_rx_fifo_wrport_adr[3:0] \main_uart_rx_fifo_produce + end + sync always + update \main_uart_rx_fifo_wrport_adr $0\main_uart_rx_fifo_wrport_adr[3:0] + end + attribute \src "ls180.v:416.11-416.68" + process $proc$ls180.v:416$2911 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] 4'0000 + sync always + sync init + update \main_sdram_bankmachine0_cmd_buffer_lookahead_level $1\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] + end + attribute \src "ls180.v:417.5-417.64" + process $proc$ls180.v:417$2912 + assign { } { } + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_replace[0:0] 1'0 + sync always + update \main_sdram_bankmachine0_cmd_buffer_lookahead_replace $0\main_sdram_bankmachine0_cmd_buffer_lookahead_replace[0:0] + sync init + end + attribute \src "ls180.v:418.11-418.70" + process $proc$ls180.v:418$2913 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine0_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] + end + attribute \src "ls180.v:4182.1-4230.4" + process $proc$ls180.v:4182$606 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_spi_master_count_spimaster0_next_value[2:0] 3'000 + assign $0\main_spi_master_miso_latch[0:0] 1'0 + assign $0\main_spi_master_clk_enable[0:0] 1'0 + assign $0\main_spi_master_irq[0:0] 1'0 + assign $0\main_spi_master_cs_enable[0:0] 1'0 + assign { } { } + assign $0\main_spi_master_mosi_latch[0:0] 1'0 + assign $0\main_spi_master_done0[0:0] 1'0 + assign $0\main_spi_master_count_spimaster0_next_value_ce[0:0] 1'0 + assign $0\builder_spimaster0_next_state[1:0] \builder_spimaster0_state + attribute \src "ls180.v:4193.2-4229.9" + switch \builder_spimaster0_state + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\main_spi_master_count_spimaster0_next_value[2:0] 3'000 + assign $0\main_spi_master_count_spimaster0_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:4197.4-4200.7" + switch \main_spi_master_clk_fall + attribute \src "ls180.v:4197.8-4197.32" + case 1'1 + assign $0\main_spi_master_cs_enable[0:0] 1'1 + assign $0\builder_spimaster0_next_state[1:0] 2'10 + case + end + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\main_spi_master_clk_enable[0:0] 1'1 + assign $0\main_spi_master_cs_enable[0:0] 1'1 + attribute \src "ls180.v:4205.4-4211.7" + switch \main_spi_master_clk_fall + attribute \src "ls180.v:4205.8-4205.32" + case 1'1 + assign $0\main_spi_master_count_spimaster0_next_value[2:0] $add$ls180.v:4206$607_Y + assign $0\main_spi_master_count_spimaster0_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:4208.5-4210.8" + switch $eq$ls180.v:4208$609_Y + attribute \src "ls180.v:4208.9-4208.68" + case 1'1 + assign $0\builder_spimaster0_next_state[1:0] 2'11 + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 2'11 + assign $0\main_spi_master_cs_enable[0:0] 1'1 + attribute \src "ls180.v:4215.4-4219.7" + switch \main_spi_master_clk_rise + attribute \src "ls180.v:4215.8-4215.32" + case 1'1 + assign $0\main_spi_master_miso_latch[0:0] 1'1 + assign $0\main_spi_master_irq[0:0] 1'1 + assign $0\builder_spimaster0_next_state[1:0] 2'00 + case + end + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_spi_master_done0[0:0] 1'1 + attribute \src "ls180.v:4223.4-4227.7" + switch \main_spi_master_start0 + attribute \src "ls180.v:4223.8-4223.30" + case 1'1 + assign $0\main_spi_master_done0[0:0] 1'0 + assign $0\main_spi_master_mosi_latch[0:0] 1'1 + assign $0\builder_spimaster0_next_state[1:0] 2'01 + case + end + end + sync always + update \main_spi_master_done0 $0\main_spi_master_done0[0:0] + update \main_spi_master_irq $0\main_spi_master_irq[0:0] + update \main_spi_master_clk_enable $0\main_spi_master_clk_enable[0:0] + update \main_spi_master_cs_enable $0\main_spi_master_cs_enable[0:0] + update \main_spi_master_mosi_latch $0\main_spi_master_mosi_latch[0:0] + update \main_spi_master_miso_latch $0\main_spi_master_miso_latch[0:0] + update \builder_spimaster0_next_state $0\builder_spimaster0_next_state[1:0] + update \main_spi_master_count_spimaster0_next_value $0\main_spi_master_count_spimaster0_next_value[2:0] + update \main_spi_master_count_spimaster0_next_value_ce $0\main_spi_master_count_spimaster0_next_value_ce[0:0] + end + attribute \src "ls180.v:419.11-419.70" + process $proc$ls180.v:419$2914 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine0_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] + end + attribute \src "ls180.v:420.11-420.73" + process $proc$ls180.v:420$2915 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr $1\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] + end + attribute \src "ls180.v:4258.1-4286.4" + process $proc$ls180.v:4258$631 + assign { } { } + assign $0\main_sdphy_clocker_clk1[0:0] 1'0 + attribute \src "ls180.v:4260.2-4285.9" + switch \main_sdphy_clocker_storage + attribute \src "ls180.v:0.0-0.0" + case 9'000000100 + assign $0\main_sdphy_clocker_clk1[0:0] \main_sdphy_clocker_clks [1] + attribute \src "ls180.v:0.0-0.0" + case 9'000001000 + assign $0\main_sdphy_clocker_clk1[0:0] \main_sdphy_clocker_clks [2] + attribute \src "ls180.v:0.0-0.0" + case 9'000010000 + assign $0\main_sdphy_clocker_clk1[0:0] \main_sdphy_clocker_clks [3] + attribute \src "ls180.v:0.0-0.0" + case 9'000100000 + assign $0\main_sdphy_clocker_clk1[0:0] \main_sdphy_clocker_clks [4] + attribute \src "ls180.v:0.0-0.0" + case 9'001000000 + assign $0\main_sdphy_clocker_clk1[0:0] \main_sdphy_clocker_clks [5] + attribute \src "ls180.v:0.0-0.0" + case 9'010000000 + assign $0\main_sdphy_clocker_clk1[0:0] \main_sdphy_clocker_clks [6] + attribute \src "ls180.v:0.0-0.0" + case 9'100000000 + assign $0\main_sdphy_clocker_clk1[0:0] \main_sdphy_clocker_clks [7] + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_sdphy_clocker_clk1[0:0] \main_sdphy_clocker_clks [0] + end + sync always + update \main_sdphy_clocker_clk1 $0\main_sdphy_clocker_clk1[0:0] + end + attribute \src "ls180.v:4288.1-4321.4" + process $proc$ls180.v:4288$634 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdphy_init_pads_out_payload_cmd_oe[0:0] 1'0 + assign $0\main_sdphy_init_pads_out_payload_data_o[3:0] 4'0000 + assign $0\main_sdphy_init_pads_out_payload_data_oe[0:0] 1'0 + assign { } { } + assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] 8'00000000 + assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] 1'0 + assign $0\main_sdphy_init_pads_out_payload_clk[0:0] 1'0 + assign $0\main_sdphy_init_pads_out_payload_cmd_o[0:0] 1'0 + assign $0\builder_sdphy_sdphyinit_next_state[0:0] \builder_sdphy_sdphyinit_state + attribute \src "ls180.v:4298.2-4320.9" + switch \builder_sdphy_sdphyinit_state + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\main_sdphy_init_pads_out_payload_clk[0:0] 1'1 + assign $0\main_sdphy_init_pads_out_payload_cmd_oe[0:0] 1'1 + assign $0\main_sdphy_init_pads_out_payload_cmd_o[0:0] 1'1 + assign $0\main_sdphy_init_pads_out_payload_data_oe[0:0] 1'1 + assign $0\main_sdphy_init_pads_out_payload_data_o[3:0] 4'1111 + attribute \src "ls180.v:4305.4-4311.7" + switch \main_sdphy_init_pads_out_ready + attribute \src "ls180.v:4305.8-4305.38" + case 1'1 + assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] $add$ls180.v:4306$635_Y + assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:4308.5-4310.8" + switch $eq$ls180.v:4308$636_Y + attribute \src "ls180.v:4308.9-4308.41" + case 1'1 + assign $0\builder_sdphy_sdphyinit_next_state[0:0] 1'0 + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] 8'00000000 + assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:4316.4-4318.7" + switch \main_sdphy_init_initialize_re + attribute \src "ls180.v:4316.8-4316.37" + case 1'1 + assign $0\builder_sdphy_sdphyinit_next_state[0:0] 1'1 + case + end + end + sync always + update \main_sdphy_init_pads_out_payload_clk $0\main_sdphy_init_pads_out_payload_clk[0:0] + update \main_sdphy_init_pads_out_payload_cmd_o $0\main_sdphy_init_pads_out_payload_cmd_o[0:0] + update \main_sdphy_init_pads_out_payload_cmd_oe $0\main_sdphy_init_pads_out_payload_cmd_oe[0:0] + update \main_sdphy_init_pads_out_payload_data_o $0\main_sdphy_init_pads_out_payload_data_o[3:0] + update \main_sdphy_init_pads_out_payload_data_oe $0\main_sdphy_init_pads_out_payload_data_oe[0:0] + update \builder_sdphy_sdphyinit_next_state $0\builder_sdphy_sdphyinit_next_state[0:0] + update \main_sdphy_init_count_sdphy_sdphyinit_next_value $0\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] + update \main_sdphy_init_count_sdphy_sdphyinit_next_value_ce $0\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] + end + attribute \src "ls180.v:4322.1-4398.4" + process $proc$ls180.v:4322$637 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] 8'00000000 + assign $0\main_sdphy_cmdw_sink_ready[0:0] 1'0 + assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] 1'0 + assign $0\main_sdphy_cmdw_done[0:0] 1'0 + assign $0\main_sdphy_cmdw_pads_out_payload_clk[0:0] 1'0 + assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] 1'0 + assign $0\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] 1'0 + assign $0\builder_sdphy_sdphycmdw_next_state[1:0] \builder_sdphy_sdphycmdw_state + attribute \src "ls180.v:4332.2-4397.9" + switch \builder_sdphy_sdphycmdw_state + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\main_sdphy_cmdw_pads_out_payload_clk[0:0] 1'1 + assign $0\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] 1'1 + attribute \src "ls180.v:4336.4-4361.11" + switch \main_sdphy_cmdw_count + attribute \src "ls180.v:0.0-0.0" + case 8'00000000 + assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] \main_sdphy_cmdw_sink_payload_data [7] + attribute \src "ls180.v:0.0-0.0" + case 8'00000001 + assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] \main_sdphy_cmdw_sink_payload_data [6] + attribute \src "ls180.v:0.0-0.0" + case 8'00000010 + assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] \main_sdphy_cmdw_sink_payload_data [5] + attribute \src "ls180.v:0.0-0.0" + case 8'00000011 + assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] \main_sdphy_cmdw_sink_payload_data [4] + attribute \src "ls180.v:0.0-0.0" + case 8'00000100 + assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] \main_sdphy_cmdw_sink_payload_data [3] + attribute \src "ls180.v:0.0-0.0" + case 8'00000101 + assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] \main_sdphy_cmdw_sink_payload_data [2] + attribute \src "ls180.v:0.0-0.0" + case 8'00000110 + assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] \main_sdphy_cmdw_sink_payload_data [1] + attribute \src "ls180.v:0.0-0.0" + case 8'00000111 + assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] \main_sdphy_cmdw_sink_payload_data [0] + case + end + attribute \src "ls180.v:4362.4-4373.7" + switch \main_sdphy_cmdw_pads_out_ready + attribute \src "ls180.v:4362.8-4362.38" + case 1'1 + assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] $add$ls180.v:4363$638_Y + assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:4365.5-4372.8" + switch $eq$ls180.v:4365$639_Y + attribute \src "ls180.v:4365.9-4365.40" + case 1'1 + attribute \src "ls180.v:4366.6-4371.9" + switch \main_sdphy_cmdw_sink_last + attribute \src "ls180.v:4366.10-4366.35" + case 1'1 + assign $0\builder_sdphy_sdphycmdw_next_state[1:0] 2'10 + attribute \src "ls180.v:4368.10-4368.14" + case + assign $0\main_sdphy_cmdw_sink_ready[0:0] 1'1 + assign $0\builder_sdphy_sdphycmdw_next_state[1:0] 2'00 + end + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\main_sdphy_cmdw_pads_out_payload_clk[0:0] 1'1 + assign $0\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] 1'1 + assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] 1'1 + attribute \src "ls180.v:4379.4-4386.7" + switch \main_sdphy_cmdw_pads_out_ready + attribute \src "ls180.v:4379.8-4379.38" + case 1'1 + assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] $add$ls180.v:4380$640_Y + assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:4382.5-4385.8" + switch $eq$ls180.v:4382$641_Y + attribute \src "ls180.v:4382.9-4382.40" + case 1'1 + assign $0\main_sdphy_cmdw_sink_ready[0:0] 1'1 + assign $0\builder_sdphy_sdphycmdw_next_state[1:0] 2'00 + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] 8'00000000 + assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:4391.4-4395.7" + switch $and$ls180.v:4391$642_Y + attribute \src "ls180.v:4391.8-4391.69" + case 1'1 + assign $0\builder_sdphy_sdphycmdw_next_state[1:0] 2'01 + attribute \src "ls180.v:4393.8-4393.12" + case + assign $0\main_sdphy_cmdw_done[0:0] 1'1 + end + end + sync always + update \main_sdphy_cmdw_pads_out_payload_clk $0\main_sdphy_cmdw_pads_out_payload_clk[0:0] + update \main_sdphy_cmdw_pads_out_payload_cmd_o $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] + update \main_sdphy_cmdw_pads_out_payload_cmd_oe $0\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] + update \main_sdphy_cmdw_sink_ready $0\main_sdphy_cmdw_sink_ready[0:0] + update \main_sdphy_cmdw_done $0\main_sdphy_cmdw_done[0:0] + update \builder_sdphy_sdphycmdw_next_state $0\builder_sdphy_sdphycmdw_next_state[1:0] + update \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] + update \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] + end + attribute \src "ls180.v:441.5-441.59" + process $proc$ls180.v:441$2916 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_cmd_buffer_source_valid $1\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] + end + attribute \src "ls180.v:443.5-443.59" + process $proc$ls180.v:443$2917 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_cmd_buffer_source_first $1\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] + end + attribute \src "ls180.v:4432.1-4525.4" + process $proc$ls180.v:4432$651 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdphy_cmdr_pads_out_payload_clk[0:0] 1'0 + assign $0\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] 1'0 + assign $0\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] 1'0 + assign $0\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] 1'0 + assign $0\main_sdphy_cmdr_sink_ready[0:0] 1'0 + assign { } { } + assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] 8'00000000 + assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'0 + assign $0\main_sdphy_cmdr_source_valid[0:0] 1'0 + assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] 0 + assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] 1'0 + assign $0\main_sdphy_cmdr_source_last[0:0] 1'0 + assign $0\main_sdphy_cmdr_source_payload_data[7:0] 8'00000000 + assign $0\main_sdphy_cmdr_source_payload_status[2:0] 3'000 + assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] 1'0 + assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] 1'0 + assign $0\builder_sdphy_sdphycmdr_next_state[2:0] \builder_sdphy_sdphycmdr_state + attribute \src "ls180.v:4450.2-4524.9" + switch \builder_sdphy_sdphycmdr_state + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\main_sdphy_cmdr_pads_out_payload_clk[0:0] 1'1 + assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] 1'0 + assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] 1'1 + assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] $sub$ls180.v:4458$652_Y + assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] 1'1 + attribute \src "ls180.v:4455.4-4457.7" + switch \main_sdphy_cmdr_cmdr_source_source_valid0 + attribute \src "ls180.v:4455.8-4455.49" + case 1'1 + assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'010 + case + end + attribute \src "ls180.v:4460.4-4463.7" + switch $eq$ls180.v:4460$653_Y + attribute \src "ls180.v:4460.8-4460.41" + case 1'1 + assign $0\main_sdphy_cmdr_sink_ready[0:0] 1'1 + assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'100 + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\main_sdphy_cmdr_pads_out_payload_clk[0:0] 1'1 + assign $0\main_sdphy_cmdr_source_valid[0:0] \main_sdphy_cmdr_cmdr_source_source_valid0 + assign $0\main_sdphy_cmdr_source_payload_status[2:0] 3'000 + assign $0\main_sdphy_cmdr_source_last[0:0] $eq$ls180.v:4469$655_Y + assign $0\main_sdphy_cmdr_source_payload_data[7:0] \main_sdphy_cmdr_cmdr_source_source_payload_data0 + assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] $sub$ls180.v:4486$658_Y + assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] 1'1 + attribute \src "ls180.v:4471.4-4485.7" + switch $and$ls180.v:4471$656_Y + attribute \src "ls180.v:4471.8-4471.69" + case 1'1 + assign $0\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] 1'1 + assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] $add$ls180.v:4473$657_Y + assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'1 + attribute \src "ls180.v:4475.5-4484.8" + switch \main_sdphy_cmdr_source_last + attribute \src "ls180.v:4475.9-4475.36" + case 1'1 + assign $0\main_sdphy_cmdr_sink_ready[0:0] 1'1 + attribute \src "ls180.v:4477.6-4483.9" + switch \main_sdphy_cmdr_sink_last + attribute \src "ls180.v:4477.10-4477.35" + case 1'1 + assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] 8'00000000 + assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'1 + assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'011 + attribute \src "ls180.v:4481.10-4481.14" + case + assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'000 + end + case + end + case + end + attribute \src "ls180.v:4488.4-4491.7" + switch $eq$ls180.v:4488$659_Y + attribute \src "ls180.v:4488.8-4488.41" + case 1'1 + assign $0\main_sdphy_cmdr_sink_ready[0:0] 1'1 + assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'100 + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\main_sdphy_cmdr_pads_out_payload_clk[0:0] 1'1 + assign $0\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] 1'1 + assign $0\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] 1'1 + attribute \src "ls180.v:4497.4-4503.7" + switch \main_sdphy_cmdr_pads_out_ready + attribute \src "ls180.v:4497.8-4497.38" + case 1'1 + assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] $add$ls180.v:4498$660_Y + assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'1 + attribute \src "ls180.v:4500.5-4502.8" + switch $eq$ls180.v:4500$661_Y + attribute \src "ls180.v:4500.9-4500.40" + case 1'1 + assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'000 + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\main_sdphy_cmdr_source_valid[0:0] 1'1 + assign $0\main_sdphy_cmdr_source_payload_status[2:0] 3'001 + assign $0\main_sdphy_cmdr_source_last[0:0] 1'1 + attribute \src "ls180.v:4509.4-4511.7" + switch $and$ls180.v:4509$662_Y + attribute \src "ls180.v:4509.8-4509.69" + case 1'1 + assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'000 + case + end + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] 8'00000000 + assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'1 + assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] 500000 + assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] 1'1 + attribute \src "ls180.v:4518.4-4522.7" + switch $and$ls180.v:4518$664_Y + attribute \src "ls180.v:4518.8-4518.94" + case 1'1 + assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] 1'1 + assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] 1'1 + assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'001 + case + end + end + sync always + update \main_sdphy_cmdr_pads_out_payload_clk $0\main_sdphy_cmdr_pads_out_payload_clk[0:0] + update \main_sdphy_cmdr_pads_out_payload_cmd_o $0\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] + update \main_sdphy_cmdr_pads_out_payload_cmd_oe $0\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] + update \main_sdphy_cmdr_sink_ready $0\main_sdphy_cmdr_sink_ready[0:0] + update \main_sdphy_cmdr_source_valid $0\main_sdphy_cmdr_source_valid[0:0] + update \main_sdphy_cmdr_source_last $0\main_sdphy_cmdr_source_last[0:0] + update \main_sdphy_cmdr_source_payload_data $0\main_sdphy_cmdr_source_payload_data[7:0] + update \main_sdphy_cmdr_source_payload_status $0\main_sdphy_cmdr_source_payload_status[2:0] + update \main_sdphy_cmdr_cmdr_source_source_ready0 $0\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] + update \builder_sdphy_sdphycmdr_next_state $0\builder_sdphy_sdphycmdr_next_state[2:0] + update \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0 $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] + update \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0 $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] + update \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1 $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] + update \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1 $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] + update \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2 $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] + update \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2 $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] + end + attribute \src "ls180.v:444.5-444.58" + process $proc$ls180.v:444$2918 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_cmd_buffer_source_last $1\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] + end + attribute \src "ls180.v:445.5-445.64" + process $proc$ls180.v:445$2919 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_cmd_buffer_source_payload_we $1\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] + end + attribute \src "ls180.v:446.12-446.74" + process $proc$ls180.v:446$2920 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000 + sync always + sync init + update \main_sdram_bankmachine0_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] + end + attribute \src "ls180.v:447.12-447.47" + process $proc$ls180.v:447$2921 + assign { } { } + assign $1\main_sdram_bankmachine0_row[12:0] 13'0000000000000 + sync always + sync init + update \main_sdram_bankmachine0_row $1\main_sdram_bankmachine0_row[12:0] + end + attribute \src "ls180.v:448.5-448.46" + process $proc$ls180.v:448$2922 + assign { } { } + assign $1\main_sdram_bankmachine0_row_opened[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_row_opened $1\main_sdram_bankmachine0_row_opened[0:0] + end + attribute \src "ls180.v:450.5-450.44" + process $proc$ls180.v:450$2923 + assign { } { } + assign $1\main_sdram_bankmachine0_row_open[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_row_open $1\main_sdram_bankmachine0_row_open[0:0] + end + attribute \src "ls180.v:451.5-451.45" + process $proc$ls180.v:451$2924 + assign { } { } + assign $1\main_sdram_bankmachine0_row_close[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_row_close $1\main_sdram_bankmachine0_row_close[0:0] + end + attribute \src "ls180.v:452.5-452.54" + process $proc$ls180.v:452$2925 + assign { } { } + assign $1\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_row_col_n_addr_sel $1\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] + end + attribute \src "ls180.v:454.32-454.76" + process $proc$ls180.v:454$2926 + assign { } { } + assign $1\main_sdram_bankmachine0_twtpcon_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_twtpcon_ready $1\main_sdram_bankmachine0_twtpcon_ready[0:0] + end + attribute \src "ls180.v:455.11-455.55" + process $proc$ls180.v:455$2927 + assign { } { } + assign $1\main_sdram_bankmachine0_twtpcon_count[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine0_twtpcon_count $1\main_sdram_bankmachine0_twtpcon_count[2:0] + end + attribute \src "ls180.v:4559.1-4586.4" + process $proc$ls180.v:4559$672 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdphy_dataw_crcr_source_source_ready0[0:0] 1'0 + assign { } { } + assign $0\main_sdphy_dataw_error[0:0] 1'0 + assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] 1'0 + assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] 1'0 + assign $0\main_sdphy_dataw_valid[0:0] 1'0 + assign $0\builder_sdphy_sdphycrcr_next_state[0:0] \builder_sdphy_sdphycrcr_state + attribute \src "ls180.v:4567.2-4585.9" + switch \builder_sdphy_sdphycrcr_state + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] 1'0 + assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] 1'1 + assign $0\main_sdphy_dataw_crcr_source_source_ready0[0:0] 1'1 + attribute \src "ls180.v:4572.4-4576.7" + switch \main_sdphy_dataw_crcr_source_source_valid0 + attribute \src "ls180.v:4572.8-4572.50" + case 1'1 + assign $0\main_sdphy_dataw_valid[0:0] $ne$ls180.v:4573$673_Y + assign $0\main_sdphy_dataw_error[0:0] $eq$ls180.v:4574$674_Y + assign $0\builder_sdphy_sdphycrcr_next_state[0:0] 1'0 + case + end + attribute \src "ls180.v:0.0-0.0" + case + attribute \src "ls180.v:4579.4-4583.7" + switch \main_sdphy_dataw_start + attribute \src "ls180.v:4579.8-4579.30" + case 1'1 + assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] 1'1 + assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] 1'1 + assign $0\builder_sdphy_sdphycrcr_next_state[0:0] 1'1 + case + end + end + sync always + update \main_sdphy_dataw_valid $0\main_sdphy_dataw_valid[0:0] + update \main_sdphy_dataw_error $0\main_sdphy_dataw_error[0:0] + update \main_sdphy_dataw_crcr_source_source_ready0 $0\main_sdphy_dataw_crcr_source_source_ready0[0:0] + update \builder_sdphy_sdphycrcr_next_state $0\builder_sdphy_sdphycrcr_next_state[0:0] + update \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] + update \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] + end + attribute \src "ls180.v:457.32-457.75" + process $proc$ls180.v:457$2928 + assign { } { } + assign $0\main_sdram_bankmachine0_trccon_ready[0:0] 1'1 + sync always + update \main_sdram_bankmachine0_trccon_ready $0\main_sdram_bankmachine0_trccon_ready[0:0] + sync init + end + attribute \src "ls180.v:4587.1-4659.4" + process $proc$ls180.v:4587$675 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'0 + assign { } { } + assign $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] 4'0000 + assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] 8'00000000 + assign $0\main_sdphy_dataw_pads_out_payload_data_oe[0:0] 1'0 + assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'0 + assign $0\main_sdphy_dataw_sink_ready[0:0] 1'0 + assign $0\main_sdphy_dataw_start[0:0] 1'0 + assign $0\main_sdphy_dataw_stop[0:0] 1'0 + assign $0\builder_sdphy_fsm_next_state[2:0] \builder_sdphy_fsm_state + attribute \src "ls180.v:4598.2-4658.9" + switch \builder_sdphy_fsm_state + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'1 + assign $0\main_sdphy_dataw_pads_out_payload_data_oe[0:0] 1'1 + assign $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] 4'0000 + attribute \src "ls180.v:4603.4-4605.7" + switch \main_sdphy_dataw_pads_out_ready + attribute \src "ls180.v:4603.8-4603.39" + case 1'1 + assign $0\builder_sdphy_fsm_next_state[2:0] 3'010 + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\main_sdphy_dataw_stop[0:0] $not$ls180.v:4608$676_Y + assign $0\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'1 + assign $0\main_sdphy_dataw_pads_out_payload_data_oe[0:0] 1'1 + attribute \src "ls180.v:4611.4-4618.11" + switch \main_sdphy_dataw_count + attribute \src "ls180.v:0.0-0.0" + case 8'00000000 + assign $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] \main_sdphy_dataw_sink_payload_data [7:4] + attribute \src "ls180.v:0.0-0.0" + case 8'00000001 + assign $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] \main_sdphy_dataw_sink_payload_data [3:0] + case + end + attribute \src "ls180.v:4619.4-4631.7" + switch \main_sdphy_dataw_pads_out_ready + attribute \src "ls180.v:4619.8-4619.39" + case 1'1 + assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] $add$ls180.v:4620$677_Y + assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:4622.5-4630.8" + switch $eq$ls180.v:4622$678_Y + attribute \src "ls180.v:4622.9-4622.41" + case 1'1 + assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] 8'00000000 + assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:4625.6-4629.9" + switch \main_sdphy_dataw_sink_last + attribute \src "ls180.v:4625.10-4625.36" + case 1'1 + assign $0\builder_sdphy_fsm_next_state[2:0] 3'011 + attribute \src "ls180.v:4627.10-4627.14" + case + assign $0\main_sdphy_dataw_sink_ready[0:0] 1'1 + end + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'1 + assign $0\main_sdphy_dataw_pads_out_payload_data_oe[0:0] 1'1 + assign $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] 4'1111 + attribute \src "ls180.v:4637.4-4640.7" + switch \main_sdphy_dataw_pads_out_ready + attribute \src "ls180.v:4637.8-4637.39" + case 1'1 + assign $0\main_sdphy_dataw_start[0:0] 1'1 + assign $0\builder_sdphy_fsm_next_state[2:0] 3'100 + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'1 + attribute \src "ls180.v:4644.4-4649.7" + switch \main_sdphy_dataw_pads_out_ready + attribute \src "ls180.v:4644.8-4644.39" + case 1'1 + attribute \src "ls180.v:4645.5-4648.8" + switch \main_sdphy_dataw_pads_in_payload_data_i [0] + attribute \src "ls180.v:4645.9-4645.51" + case 1'1 + assign $0\main_sdphy_dataw_sink_ready[0:0] 1'1 + assign $0\builder_sdphy_fsm_next_state[2:0] 3'000 + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] 8'00000000 + assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:4654.4-4656.7" + switch $and$ls180.v:4654$679_Y + attribute \src "ls180.v:4654.8-4654.71" + case 1'1 + assign $0\builder_sdphy_fsm_next_state[2:0] 3'001 + case + end + end + sync always + update \main_sdphy_dataw_pads_out_payload_clk $0\main_sdphy_dataw_pads_out_payload_clk[0:0] + update \main_sdphy_dataw_pads_out_payload_data_o $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] + update \main_sdphy_dataw_pads_out_payload_data_oe $0\main_sdphy_dataw_pads_out_payload_data_oe[0:0] + update \main_sdphy_dataw_sink_ready $0\main_sdphy_dataw_sink_ready[0:0] + update \main_sdphy_dataw_stop $0\main_sdphy_dataw_stop[0:0] + update \main_sdphy_dataw_start $0\main_sdphy_dataw_start[0:0] + update \builder_sdphy_fsm_next_state $0\builder_sdphy_fsm_next_state[2:0] + update \main_sdphy_dataw_count_sdphy_fsm_next_value $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] + update \main_sdphy_dataw_count_sdphy_fsm_next_value_ce $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] + end + attribute \src "ls180.v:459.32-459.76" + process $proc$ls180.v:459$2929 + assign { } { } + assign $0\main_sdram_bankmachine0_trascon_ready[0:0] 1'1 + sync always + update \main_sdram_bankmachine0_trascon_ready $0\main_sdram_bankmachine0_trascon_ready[0:0] + sync init + end + attribute \src "ls180.v:465.5-465.51" + process $proc$ls180.v:465$2930 + assign { } { } + assign $1\main_sdram_bankmachine1_req_wdata_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_req_wdata_ready $1\main_sdram_bankmachine1_req_wdata_ready[0:0] + end + attribute \src "ls180.v:466.5-466.51" + process $proc$ls180.v:466$2931 + assign { } { } + assign $1\main_sdram_bankmachine1_req_rdata_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_req_rdata_valid $1\main_sdram_bankmachine1_req_rdata_valid[0:0] + end + attribute \src "ls180.v:468.5-468.47" + process $proc$ls180.v:468$2932 + assign { } { } + assign $1\main_sdram_bankmachine1_refresh_gnt[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_refresh_gnt $1\main_sdram_bankmachine1_refresh_gnt[0:0] + end + attribute \src "ls180.v:469.5-469.45" + process $proc$ls180.v:469$2933 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_cmd_valid $1\main_sdram_bankmachine1_cmd_valid[0:0] + end + attribute \src "ls180.v:4693.1-4794.4" + process $proc$ls180.v:4693$687 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdphy_datar_source_last[0:0] 1'0 + assign $0\main_sdphy_datar_pads_out_payload_clk[0:0] 1'0 + assign $0\main_sdphy_datar_source_payload_data[7:0] 8'00000000 + assign $0\main_sdphy_datar_source_payload_status[2:0] 3'000 + assign $0\main_sdphy_datar_datar_source_source_ready0[0:0] 1'0 + assign $0\main_sdphy_datar_stop[0:0] 1'0 + assign { } { } + assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] 10'0000000000 + assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'0 + assign $0\main_sdphy_datar_sink_ready[0:0] 1'0 + assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] 0 + assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'0 + assign $0\main_sdphy_datar_source_valid[0:0] 1'0 + assign $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] 1'0 + assign $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] 1'0 + assign $0\builder_sdphy_sdphydatar_next_state[2:0] \builder_sdphy_sdphydatar_state + attribute \src "ls180.v:4710.2-4793.9" + switch \builder_sdphy_sdphydatar_state + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\main_sdphy_datar_pads_out_payload_clk[0:0] 1'1 + assign $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] 1'0 + assign $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] 1'1 + assign { } { } + assign { } { } + assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] $sub$ls180.v:4720$689_Y + assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'1 + attribute \src "ls180.v:4717.4-4719.7" + switch \main_sdphy_datar_datar_source_source_valid0 + attribute \src "ls180.v:4717.8-4717.51" + case 1'1 + assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'010 + case + end + attribute \src "ls180.v:4722.4-4725.7" + switch $eq$ls180.v:4722$690_Y + attribute \src "ls180.v:4722.8-4722.42" + case 1'1 + assign $0\main_sdphy_datar_sink_ready[0:0] 1'1 + assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'100 + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\main_sdphy_datar_pads_out_payload_clk[0:0] 1'1 + assign $0\main_sdphy_datar_source_valid[0:0] \main_sdphy_datar_datar_source_source_valid0 + assign $0\main_sdphy_datar_source_payload_status[2:0] 3'000 + assign $0\main_sdphy_datar_source_last[0:0] $eq$ls180.v:4731$693_Y + assign $0\main_sdphy_datar_source_payload_data[7:0] \main_sdphy_datar_datar_source_source_payload_data0 + assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] $sub$ls180.v:4752$695_Y + assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'1 + attribute \src "ls180.v:4733.4-4751.7" + switch \main_sdphy_datar_source_valid + attribute \src "ls180.v:4733.8-4733.37" + case 1'1 + attribute \src "ls180.v:4734.5-4750.8" + switch \main_sdphy_datar_source_ready + attribute \src "ls180.v:4734.9-4734.38" + case 1'1 + assign $0\main_sdphy_datar_datar_source_source_ready0[0:0] 1'1 + assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] $add$ls180.v:4736$694_Y + assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'1 + attribute \src "ls180.v:4738.6-4747.9" + switch \main_sdphy_datar_source_last + attribute \src "ls180.v:4738.10-4738.38" + case 1'1 + assign $0\main_sdphy_datar_sink_ready[0:0] 1'1 + attribute \src "ls180.v:4740.7-4746.10" + switch \main_sdphy_datar_sink_last + attribute \src "ls180.v:4740.11-4740.37" + case 1'1 + assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] 10'0000000000 + assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'1 + assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'011 + attribute \src "ls180.v:4744.11-4744.15" + case + assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'000 + end + case + end + attribute \src "ls180.v:4748.9-4748.13" + case + assign $0\main_sdphy_datar_stop[0:0] 1'1 + end + case + end + attribute \src "ls180.v:4754.4-4757.7" + switch $eq$ls180.v:4754$696_Y + attribute \src "ls180.v:4754.8-4754.42" + case 1'1 + assign $0\main_sdphy_datar_sink_ready[0:0] 1'1 + assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'100 + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\main_sdphy_datar_pads_out_payload_clk[0:0] 1'1 + attribute \src "ls180.v:4761.4-4767.7" + switch \main_sdphy_datar_pads_out_ready + attribute \src "ls180.v:4761.8-4761.39" + case 1'1 + assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] $add$ls180.v:4762$697_Y + assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'1 + attribute \src "ls180.v:4764.5-4766.8" + switch $eq$ls180.v:4764$698_Y + attribute \src "ls180.v:4764.9-4764.42" + case 1'1 + assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'000 + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\main_sdphy_datar_source_valid[0:0] 1'1 + assign $0\main_sdphy_datar_source_payload_status[2:0] 3'001 + assign $0\main_sdphy_datar_source_last[0:0] 1'1 + attribute \src "ls180.v:4773.4-4775.7" + switch $and$ls180.v:4773$699_Y + attribute \src "ls180.v:4773.8-4773.71" + case 1'1 + assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'000 + case + end + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] 10'0000000000 + assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'1 + attribute \src "ls180.v:4780.4-4791.7" + switch $and$ls180.v:4780$700_Y + attribute \src "ls180.v:4780.8-4780.71" + case 1'1 + assign $0\main_sdphy_datar_pads_out_payload_clk[0:0] 1'1 + attribute \src "ls180.v:4782.5-4790.8" + switch \main_sdphy_datar_pads_out_ready + attribute \src "ls180.v:4782.9-4782.40" + case 1'1 + assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] 500000 + assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'1 + assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] 10'0000000000 + assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'1 + assign $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] 1'1 + assign $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] 1'1 + assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'001 + case + end + case + end + end + sync always + update \main_sdphy_datar_pads_out_payload_clk $0\main_sdphy_datar_pads_out_payload_clk[0:0] + update \main_sdphy_datar_sink_ready $0\main_sdphy_datar_sink_ready[0:0] + update \main_sdphy_datar_source_valid $0\main_sdphy_datar_source_valid[0:0] + update \main_sdphy_datar_source_last $0\main_sdphy_datar_source_last[0:0] + update \main_sdphy_datar_source_payload_data $0\main_sdphy_datar_source_payload_data[7:0] + update \main_sdphy_datar_source_payload_status $0\main_sdphy_datar_source_payload_status[2:0] + update \main_sdphy_datar_stop $0\main_sdphy_datar_stop[0:0] + update \main_sdphy_datar_datar_source_source_ready0 $0\main_sdphy_datar_datar_source_source_ready0[0:0] + update \builder_sdphy_sdphydatar_next_state $0\builder_sdphy_sdphydatar_next_state[2:0] + update \main_sdphy_datar_count_sdphy_sdphydatar_next_value0 $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] + update \main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0 $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] + update \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1 $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] + update \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1 $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] + update \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2 $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] + update \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2 $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] + end + attribute \src "ls180.v:470.5-470.45" + process $proc$ls180.v:470$2934 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_cmd_ready $1\main_sdram_bankmachine1_cmd_ready[0:0] + end + attribute \src "ls180.v:471.12-471.57" + process $proc$ls180.v:471$2935 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_payload_a[12:0] 13'0000000000000 + sync always + sync init + update \main_sdram_bankmachine1_cmd_payload_a $1\main_sdram_bankmachine1_cmd_payload_a[12:0] + end + attribute \src "ls180.v:473.5-473.51" + process $proc$ls180.v:473$2936 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_payload_cas[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_cmd_payload_cas $1\main_sdram_bankmachine1_cmd_payload_cas[0:0] + end + attribute \src "ls180.v:474.5-474.51" + process $proc$ls180.v:474$2937 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_payload_ras[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_cmd_payload_ras $1\main_sdram_bankmachine1_cmd_payload_ras[0:0] + end + attribute \src "ls180.v:475.5-475.50" + process $proc$ls180.v:475$2938 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_payload_we[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_cmd_payload_we $1\main_sdram_bankmachine1_cmd_payload_we[0:0] + end + attribute \src "ls180.v:476.5-476.54" + process $proc$ls180.v:476$2939 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_cmd_payload_is_cmd $1\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] + end + attribute \src "ls180.v:477.5-477.55" + process $proc$ls180.v:477$2940 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_payload_is_read[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_cmd_payload_is_read $1\main_sdram_bankmachine1_cmd_payload_is_read[0:0] + end + attribute \src "ls180.v:478.5-478.56" + process $proc$ls180.v:478$2941 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_payload_is_write[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_cmd_payload_is_write $1\main_sdram_bankmachine1_cmd_payload_is_write[0:0] + end + attribute \src "ls180.v:479.5-479.50" + process $proc$ls180.v:479$2942 + assign { } { } + assign $1\main_sdram_bankmachine1_auto_precharge[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_auto_precharge $1\main_sdram_bankmachine1_auto_precharge[0:0] + end + attribute \src "ls180.v:482.5-482.67" + process $proc$ls180.v:482$2943 + assign { } { } + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first[0:0] 1'0 + sync always + update \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first[0:0] + sync init + end + attribute \src "ls180.v:483.5-483.66" + process $proc$ls180.v:483$2944 + assign { } { } + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last[0:0] 1'0 + sync always + update \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last[0:0] + sync init + end + attribute \src "ls180.v:4852.1-4859.4" + process $proc$ls180.v:4852$822 + assign { } { } + assign $0\main_sdcore_crc7_inserter_crc[6:0] 7'0000000 + attribute \src "ls180.v:4854.2-4858.5" + switch \main_sdcore_crc7_inserter_enable + attribute \src "ls180.v:4854.6-4854.38" + case 1'1 + assign $0\main_sdcore_crc7_inserter_crc[6:0] \main_sdcore_crc7_inserter_crcreg40 + attribute \src "ls180.v:4856.6-4856.10" + case + assign $0\main_sdcore_crc7_inserter_crc[6:0] \main_sdcore_crc7_inserter_crcreg0 + end + sync always + update \main_sdcore_crc7_inserter_crc $0\main_sdcore_crc7_inserter_crc[6:0] + end + attribute \src "ls180.v:4874.1-4881.4" + process $proc$ls180.v:4874$845 + assign { } { } + assign $0\main_sdcore_crc16_inserter_crc0_crc[15:0] 16'0000000000000000 + attribute \src "ls180.v:4876.2-4880.5" + switch \main_sdcore_crc16_inserter_crc0_enable + attribute \src "ls180.v:4876.6-4876.44" + case 1'1 + assign $0\main_sdcore_crc16_inserter_crc0_crc[15:0] \main_sdcore_crc16_inserter_crc0_crcreg2 + attribute \src "ls180.v:4878.6-4878.10" + case + assign $0\main_sdcore_crc16_inserter_crc0_crc[15:0] \main_sdcore_crc16_inserter_crc0_crcreg0 + end + sync always + update \main_sdcore_crc16_inserter_crc0_crc $0\main_sdcore_crc16_inserter_crc0_crc[15:0] + end + attribute \src "ls180.v:4884.1-4891.4" + process $proc$ls180.v:4884$856 + assign { } { } + assign $0\main_sdcore_crc16_inserter_crc1_crc[15:0] 16'0000000000000000 + attribute \src "ls180.v:4886.2-4890.5" + switch \main_sdcore_crc16_inserter_crc1_enable + attribute \src "ls180.v:4886.6-4886.44" + case 1'1 + assign $0\main_sdcore_crc16_inserter_crc1_crc[15:0] \main_sdcore_crc16_inserter_crc1_crcreg2 + attribute \src "ls180.v:4888.6-4888.10" + case + assign $0\main_sdcore_crc16_inserter_crc1_crc[15:0] \main_sdcore_crc16_inserter_crc1_crcreg0 + end + sync always + update \main_sdcore_crc16_inserter_crc1_crc $0\main_sdcore_crc16_inserter_crc1_crc[15:0] + end + attribute \src "ls180.v:4894.1-4901.4" + process $proc$ls180.v:4894$867 + assign { } { } + assign $0\main_sdcore_crc16_inserter_crc2_crc[15:0] 16'0000000000000000 + attribute \src "ls180.v:4896.2-4900.5" + switch \main_sdcore_crc16_inserter_crc2_enable + attribute \src "ls180.v:4896.6-4896.44" + case 1'1 + assign $0\main_sdcore_crc16_inserter_crc2_crc[15:0] \main_sdcore_crc16_inserter_crc2_crcreg2 + attribute \src "ls180.v:4898.6-4898.10" + case + assign $0\main_sdcore_crc16_inserter_crc2_crc[15:0] \main_sdcore_crc16_inserter_crc2_crcreg0 + end + sync always + update \main_sdcore_crc16_inserter_crc2_crc $0\main_sdcore_crc16_inserter_crc2_crc[15:0] + end + attribute \src "ls180.v:49.5-49.42" + process $proc$ls180.v:49$2765 + assign { } { } + assign $1\main_libresocsim_reset_storage[0:0] 1'0 + sync always + sync init + update \main_libresocsim_reset_storage $1\main_libresocsim_reset_storage[0:0] + end + attribute \src "ls180.v:4904.1-4911.4" + process $proc$ls180.v:4904$878 + assign { } { } + assign $0\main_sdcore_crc16_inserter_crc3_crc[15:0] 16'0000000000000000 + attribute \src "ls180.v:4906.2-4910.5" + switch \main_sdcore_crc16_inserter_crc3_enable + attribute \src "ls180.v:4906.6-4906.44" + case 1'1 + assign $0\main_sdcore_crc16_inserter_crc3_crc[15:0] \main_sdcore_crc16_inserter_crc3_crcreg2 + attribute \src "ls180.v:4908.6-4908.10" + case + assign $0\main_sdcore_crc16_inserter_crc3_crc[15:0] \main_sdcore_crc16_inserter_crc3_crcreg0 + end + sync always + update \main_sdcore_crc16_inserter_crc3_crc $0\main_sdcore_crc16_inserter_crc3_crc[15:0] + end + attribute \src "ls180.v:4912.1-4991.4" + process $proc$ls180.v:4912$879 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] 3'000 + assign $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] 1'0 + assign $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] 1'0 + assign $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] 1'0 + assign $0\main_sdcore_crc16_inserter_sink_ready[0:0] 1'0 + assign $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] 1'0 + assign $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] 1'0 + assign $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_inserter_source_valid[0:0] 1'0 + assign $0\main_sdcore_crc16_inserter_source_last[0:0] 1'0 + assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] 8'00000000 + assign $0\builder_sdcore_crcupstreaminserter_next_state[0:0] \builder_sdcore_crcupstreaminserter_state + attribute \src "ls180.v:4929.2-4990.9" + switch \builder_sdcore_crcupstreaminserter_state + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\main_sdcore_crc16_inserter_sink_ready[0:0] 1'0 + assign $0\main_sdcore_crc16_inserter_source_valid[0:0] 1'1 + attribute \src "ls180.v:4933.4-4935.7" + switch $eq$ls180.v:4933$880_Y + attribute \src "ls180.v:4933.8-4933.48" + case 1'1 + assign $0\main_sdcore_crc16_inserter_source_last[0:0] 1'1 + case + end + attribute \src "ls180.v:4936.4-4961.11" + switch \main_sdcore_crc16_inserter_cnt + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] { \main_sdcore_crc16_inserter_crctmp3 [15] \main_sdcore_crc16_inserter_crctmp2 [15] \main_sdcore_crc16_inserter_crctmp1 [15] \main_sdcore_crc16_inserter_crctmp0 [15] \main_sdcore_crc16_inserter_crctmp3 [14] \main_sdcore_crc16_inserter_crctmp2 [14] \main_sdcore_crc16_inserter_crctmp1 [14] \main_sdcore_crc16_inserter_crctmp0 [14] } + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] { \main_sdcore_crc16_inserter_crctmp3 [13] \main_sdcore_crc16_inserter_crctmp2 [13] \main_sdcore_crc16_inserter_crctmp1 [13] \main_sdcore_crc16_inserter_crctmp0 [13] \main_sdcore_crc16_inserter_crctmp3 [12] \main_sdcore_crc16_inserter_crctmp2 [12] \main_sdcore_crc16_inserter_crctmp1 [12] \main_sdcore_crc16_inserter_crctmp0 [12] } + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] { \main_sdcore_crc16_inserter_crctmp3 [11] \main_sdcore_crc16_inserter_crctmp2 [11] \main_sdcore_crc16_inserter_crctmp1 [11] \main_sdcore_crc16_inserter_crctmp0 [11] \main_sdcore_crc16_inserter_crctmp3 [10] \main_sdcore_crc16_inserter_crctmp2 [10] \main_sdcore_crc16_inserter_crctmp1 [10] \main_sdcore_crc16_inserter_crctmp0 [10] } + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] { \main_sdcore_crc16_inserter_crctmp3 [9] \main_sdcore_crc16_inserter_crctmp2 [9] \main_sdcore_crc16_inserter_crctmp1 [9] \main_sdcore_crc16_inserter_crctmp0 [9] \main_sdcore_crc16_inserter_crctmp3 [8] \main_sdcore_crc16_inserter_crctmp2 [8] \main_sdcore_crc16_inserter_crctmp1 [8] \main_sdcore_crc16_inserter_crctmp0 [8] } + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] { \main_sdcore_crc16_inserter_crctmp3 [7] \main_sdcore_crc16_inserter_crctmp2 [7] \main_sdcore_crc16_inserter_crctmp1 [7] \main_sdcore_crc16_inserter_crctmp0 [7] \main_sdcore_crc16_inserter_crctmp3 [6] \main_sdcore_crc16_inserter_crctmp2 [6] \main_sdcore_crc16_inserter_crctmp1 [6] \main_sdcore_crc16_inserter_crctmp0 [6] } + attribute \src "ls180.v:0.0-0.0" + case 3'101 + assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] { \main_sdcore_crc16_inserter_crctmp3 [5] \main_sdcore_crc16_inserter_crctmp2 [5] \main_sdcore_crc16_inserter_crctmp1 [5] \main_sdcore_crc16_inserter_crctmp0 [5] \main_sdcore_crc16_inserter_crctmp3 [4] \main_sdcore_crc16_inserter_crctmp2 [4] \main_sdcore_crc16_inserter_crctmp1 [4] \main_sdcore_crc16_inserter_crctmp0 [4] } + attribute \src "ls180.v:0.0-0.0" + case 3'110 + assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] { \main_sdcore_crc16_inserter_crctmp3 [3] \main_sdcore_crc16_inserter_crctmp2 [3] \main_sdcore_crc16_inserter_crctmp1 [3] \main_sdcore_crc16_inserter_crctmp0 [3] \main_sdcore_crc16_inserter_crctmp3 [2] \main_sdcore_crc16_inserter_crctmp2 [2] \main_sdcore_crc16_inserter_crctmp1 [2] \main_sdcore_crc16_inserter_crctmp0 [2] } + attribute \src "ls180.v:0.0-0.0" + case 3'111 + assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] { \main_sdcore_crc16_inserter_crctmp3 [1] \main_sdcore_crc16_inserter_crctmp2 [1] \main_sdcore_crc16_inserter_crctmp1 [1] \main_sdcore_crc16_inserter_crctmp0 [1] \main_sdcore_crc16_inserter_crctmp3 [0] \main_sdcore_crc16_inserter_crctmp2 [0] \main_sdcore_crc16_inserter_crctmp1 [0] \main_sdcore_crc16_inserter_crctmp0 [0] } + case + end + attribute \src "ls180.v:4962.4-4969.7" + switch \main_sdcore_crc16_inserter_source_ready + attribute \src "ls180.v:4962.8-4962.47" + case 1'1 + attribute \src "ls180.v:4963.5-4968.8" + switch $eq$ls180.v:4963$881_Y + attribute \src "ls180.v:4963.9-4963.49" + case 1'1 + assign $0\builder_sdcore_crcupstreaminserter_next_state[0:0] 1'0 + attribute \src "ls180.v:4965.9-4965.13" + case + assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] $add$ls180.v:4966$882_Y + assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] 1'1 + end + case + end + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] \main_sdcore_crc16_inserter_sink_payload_data + assign $0\main_sdcore_crc16_inserter_source_valid[0:0] \main_sdcore_crc16_inserter_sink_valid + assign $0\main_sdcore_crc16_inserter_sink_ready[0:0] \main_sdcore_crc16_inserter_source_ready + assign $0\main_sdcore_crc16_inserter_source_last[0:0] 1'0 + assign $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] \main_sdcore_crc16_inserter_crc0_crc + assign $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] 1'1 + assign $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] \main_sdcore_crc16_inserter_crc1_crc + assign $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] 1'1 + assign $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] \main_sdcore_crc16_inserter_crc2_crc + assign $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] 1'1 + assign $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] \main_sdcore_crc16_inserter_crc3_crc + assign $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] 1'1 + attribute \src "ls180.v:4984.4-4988.7" + switch $and$ls180.v:4984$884_Y + attribute \src "ls180.v:4984.8-4984.128" + case 1'1 + assign $0\builder_sdcore_crcupstreaminserter_next_state[0:0] 1'1 + assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] 3'000 + assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] 1'1 + case + end + end + sync always + update \main_sdcore_crc16_inserter_sink_ready $0\main_sdcore_crc16_inserter_sink_ready[0:0] + update \main_sdcore_crc16_inserter_source_valid $0\main_sdcore_crc16_inserter_source_valid[0:0] + update \main_sdcore_crc16_inserter_source_last $0\main_sdcore_crc16_inserter_source_last[0:0] + update \main_sdcore_crc16_inserter_source_payload_data $0\main_sdcore_crc16_inserter_source_payload_data[7:0] + update \builder_sdcore_crcupstreaminserter_next_state $0\builder_sdcore_crcupstreaminserter_next_state[0:0] + update \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0 $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] + update \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0 $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] + update \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1 $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] + update \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1 $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] + update \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2 $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] + update \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2 $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] + update \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3 $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] + update \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3 $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] + update \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4 $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] + update \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4 $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] + end + attribute \src "ls180.v:498.11-498.68" + process $proc$ls180.v:498$2945 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] 4'0000 + sync always + sync init + update \main_sdram_bankmachine1_cmd_buffer_lookahead_level $1\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] + end + attribute \src "ls180.v:499.5-499.64" + process $proc$ls180.v:499$2946 + assign { } { } + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_replace[0:0] 1'0 + sync always + update \main_sdram_bankmachine1_cmd_buffer_lookahead_replace $0\main_sdram_bankmachine1_cmd_buffer_lookahead_replace[0:0] + sync init + end + attribute \src "ls180.v:4992.1-4997.4" + process $proc$ls180.v:4992$885 + assign { } { } + assign $0\main_sdcore_crc16_checker_valid[0:0] 1'0 + attribute \src "ls180.v:4994.2-4996.5" + switch $and$ls180.v:4994$892_Y + attribute \src "ls180.v:4994.6-4994.301" + case 1'1 + assign $0\main_sdcore_crc16_checker_valid[0:0] 1'1 + case + end + sync always + update \main_sdcore_crc16_checker_valid $0\main_sdcore_crc16_checker_valid[0:0] + end + attribute \src "ls180.v:50.5-50.37" + process $proc$ls180.v:50$2766 + assign { } { } + assign $1\main_libresocsim_reset_re[0:0] 1'0 + sync always + sync init + update \main_libresocsim_reset_re $1\main_libresocsim_reset_re[0:0] + end + attribute \src "ls180.v:500.11-500.70" + process $proc$ls180.v:500$2947 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine1_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] + end + attribute \src "ls180.v:5000.1-5007.4" + process $proc$ls180.v:5000$894 + assign { } { } + assign $0\main_sdcore_crc16_checker_crc0_clr[0:0] 1'0 + attribute \src "ls180.v:5002.2-5006.5" + switch $eq$ls180.v:5002$895_Y + attribute \src "ls180.v:5002.6-5002.45" + case 1'1 + assign $0\main_sdcore_crc16_checker_crc0_clr[0:0] 1'1 + attribute \src "ls180.v:5004.6-5004.10" + case + assign $0\main_sdcore_crc16_checker_crc0_clr[0:0] 1'0 + end + sync always + update \main_sdcore_crc16_checker_crc0_clr $0\main_sdcore_crc16_checker_crc0_clr[0:0] + end + attribute \src "ls180.v:501.11-501.70" + process $proc$ls180.v:501$2948 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine1_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] + end + attribute \src "ls180.v:5010.1-5017.4" + process $proc$ls180.v:5010$897 + assign { } { } + assign $0\main_sdcore_crc16_checker_crc1_clr[0:0] 1'0 + attribute \src "ls180.v:5012.2-5016.5" + switch $eq$ls180.v:5012$898_Y + attribute \src "ls180.v:5012.6-5012.45" + case 1'1 + assign $0\main_sdcore_crc16_checker_crc1_clr[0:0] 1'1 + attribute \src "ls180.v:5014.6-5014.10" + case + assign $0\main_sdcore_crc16_checker_crc1_clr[0:0] 1'0 + end + sync always + update \main_sdcore_crc16_checker_crc1_clr $0\main_sdcore_crc16_checker_crc1_clr[0:0] + end + attribute \src "ls180.v:502.11-502.73" + process $proc$ls180.v:502$2949 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr $1\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] + end + attribute \src "ls180.v:5020.1-5027.4" + process $proc$ls180.v:5020$900 + assign { } { } + assign $0\main_sdcore_crc16_checker_crc2_clr[0:0] 1'0 + attribute \src "ls180.v:5022.2-5026.5" + switch $eq$ls180.v:5022$901_Y + attribute \src "ls180.v:5022.6-5022.45" + case 1'1 + assign $0\main_sdcore_crc16_checker_crc2_clr[0:0] 1'1 + attribute \src "ls180.v:5024.6-5024.10" + case + assign $0\main_sdcore_crc16_checker_crc2_clr[0:0] 1'0 + end + sync always + update \main_sdcore_crc16_checker_crc2_clr $0\main_sdcore_crc16_checker_crc2_clr[0:0] + end + attribute \src "ls180.v:5030.1-5037.4" + process $proc$ls180.v:5030$903 + assign { } { } + assign $0\main_sdcore_crc16_checker_crc3_clr[0:0] 1'0 + attribute \src "ls180.v:5032.2-5036.5" + switch $eq$ls180.v:5032$904_Y + attribute \src "ls180.v:5032.6-5032.45" + case 1'1 + assign $0\main_sdcore_crc16_checker_crc3_clr[0:0] 1'1 + attribute \src "ls180.v:5034.6-5034.10" + case + assign $0\main_sdcore_crc16_checker_crc3_clr[0:0] 1'0 + end + sync always + update \main_sdcore_crc16_checker_crc3_clr $0\main_sdcore_crc16_checker_crc3_clr[0:0] + end + attribute \src "ls180.v:5039.1-5044.4" + process $proc$ls180.v:5039$905 + assign { } { } + assign $0\main_sdcore_crc16_checker_source_valid[0:0] 1'0 + attribute \src "ls180.v:5041.2-5043.5" + switch $and$ls180.v:5041$907_Y + attribute \src "ls180.v:5041.6-5041.85" + case 1'1 + assign $0\main_sdcore_crc16_checker_source_valid[0:0] 1'1 + case + end + sync always + update \main_sdcore_crc16_checker_source_valid $0\main_sdcore_crc16_checker_source_valid[0:0] + end + attribute \src "ls180.v:5045.1-5052.4" + process $proc$ls180.v:5045$908 + assign { } { } + assign $0\main_sdcore_crc16_checker_sink_ready[0:0] 1'0 + attribute \src "ls180.v:5047.2-5051.5" + switch $lt$ls180.v:5047$909_Y + attribute \src "ls180.v:5047.6-5047.44" + case 1'1 + assign $0\main_sdcore_crc16_checker_sink_ready[0:0] 1'1 + attribute \src "ls180.v:5049.6-5049.10" + case + assign $0\main_sdcore_crc16_checker_sink_ready[0:0] \main_sdcore_crc16_checker_source_ready + end + sync always + update \main_sdcore_crc16_checker_sink_ready $0\main_sdcore_crc16_checker_sink_ready[0:0] + end + attribute \src "ls180.v:5056.1-5063.4" + process $proc$ls180.v:5056$920 + assign { } { } + assign $0\main_sdcore_crc16_checker_crc0_crc[15:0] 16'0000000000000000 + attribute \src "ls180.v:5058.2-5062.5" + switch \main_sdcore_crc16_checker_crc0_enable + attribute \src "ls180.v:5058.6-5058.43" + case 1'1 + assign $0\main_sdcore_crc16_checker_crc0_crc[15:0] \main_sdcore_crc16_checker_crc0_crcreg2 + attribute \src "ls180.v:5060.6-5060.10" + case + assign $0\main_sdcore_crc16_checker_crc0_crc[15:0] \main_sdcore_crc16_checker_crc0_crcreg0 + end + sync always + update \main_sdcore_crc16_checker_crc0_crc $0\main_sdcore_crc16_checker_crc0_crc[15:0] + end + attribute \src "ls180.v:5066.1-5073.4" + process $proc$ls180.v:5066$931 + assign { } { } + assign $0\main_sdcore_crc16_checker_crc1_crc[15:0] 16'0000000000000000 + attribute \src "ls180.v:5068.2-5072.5" + switch \main_sdcore_crc16_checker_crc1_enable + attribute \src "ls180.v:5068.6-5068.43" + case 1'1 + assign $0\main_sdcore_crc16_checker_crc1_crc[15:0] \main_sdcore_crc16_checker_crc1_crcreg2 + attribute \src "ls180.v:5070.6-5070.10" + case + assign $0\main_sdcore_crc16_checker_crc1_crc[15:0] \main_sdcore_crc16_checker_crc1_crcreg0 + end + sync always + update \main_sdcore_crc16_checker_crc1_crc $0\main_sdcore_crc16_checker_crc1_crc[15:0] + end + attribute \src "ls180.v:5076.1-5083.4" + process $proc$ls180.v:5076$942 + assign { } { } + assign $0\main_sdcore_crc16_checker_crc2_crc[15:0] 16'0000000000000000 + attribute \src "ls180.v:5078.2-5082.5" + switch \main_sdcore_crc16_checker_crc2_enable + attribute \src "ls180.v:5078.6-5078.43" + case 1'1 + assign $0\main_sdcore_crc16_checker_crc2_crc[15:0] \main_sdcore_crc16_checker_crc2_crcreg2 + attribute \src "ls180.v:5080.6-5080.10" + case + assign $0\main_sdcore_crc16_checker_crc2_crc[15:0] \main_sdcore_crc16_checker_crc2_crcreg0 + end + sync always + update \main_sdcore_crc16_checker_crc2_crc $0\main_sdcore_crc16_checker_crc2_crc[15:0] + end + attribute \src "ls180.v:5086.1-5093.4" + process $proc$ls180.v:5086$953 + assign { } { } + assign $0\main_sdcore_crc16_checker_crc3_crc[15:0] 16'0000000000000000 + attribute \src "ls180.v:5088.2-5092.5" + switch \main_sdcore_crc16_checker_crc3_enable + attribute \src "ls180.v:5088.6-5088.43" + case 1'1 + assign $0\main_sdcore_crc16_checker_crc3_crc[15:0] \main_sdcore_crc16_checker_crc3_crcreg2 + attribute \src "ls180.v:5090.6-5090.10" + case + assign $0\main_sdcore_crc16_checker_crc3_crc[15:0] \main_sdcore_crc16_checker_crc3_crcreg0 + end + sync always + update \main_sdcore_crc16_checker_crc3_crc $0\main_sdcore_crc16_checker_crc3_crc[15:0] + end + attribute \src "ls180.v:5094.1-5284.4" + process $proc$ls180.v:5094$954 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] 1'0 + assign $0\main_sdphy_cmdw_sink_valid[0:0] 1'0 + assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] 3'000 + assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] 1'0 + assign $0\main_sdphy_cmdw_sink_last[0:0] 1'0 + assign $0\main_sdphy_cmdw_sink_payload_data[7:0] 8'00000000 + assign $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] 0 + assign $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'0 + assign $0\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] 1'0 + assign $0\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] 1'0 + assign $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] 1'0 + assign $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] 1'0 + assign $0\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] 1'0 + assign $0\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] 1'0 + assign $0\main_sdcore_crc16_checker_sink_valid[0:0] 1'0 + assign $0\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] 1'0 + assign $0\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] 1'0 + assign $0\main_sdcore_crc16_checker_sink_first[0:0] 1'0 + assign $0\main_sdcore_crc16_checker_sink_last[0:0] 1'0 + assign $0\main_sdcore_crc16_checker_sink_payload_data[7:0] 8'00000000 + assign $0\main_sdcore_crc16_inserter_source_ready[0:0] 1'0 + assign $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] 1'0 + assign $0\main_sdphy_datar_sink_valid[0:0] 1'0 + assign $0\main_sdphy_dataw_sink_valid[0:0] 1'0 + assign $0\main_sdphy_dataw_sink_first[0:0] 1'0 + assign $0\main_sdphy_datar_sink_last[0:0] 1'0 + assign $0\main_sdphy_dataw_sink_last[0:0] 1'0 + assign $0\main_sdphy_datar_sink_payload_block_length[9:0] 10'0000000000 + assign $0\main_sdphy_dataw_sink_payload_data[7:0] 8'00000000 + assign $0\main_sdphy_cmdr_sink_valid[0:0] 1'0 + assign $0\main_sdphy_datar_source_ready[0:0] 1'0 + assign $0\main_sdphy_cmdr_sink_last[0:0] 1'0 + assign $0\main_sdphy_cmdr_sink_payload_length[7:0] 8'00000000 + assign $0\main_sdphy_cmdr_source_ready[0:0] 1'0 + assign { } { } + assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] 1'0 + assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] 1'0 + assign $0\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] 1'0 + assign $0\builder_sdcore_fsm_next_state[2:0] \builder_sdcore_fsm_state + attribute \src "ls180.v:5135.2-5283.9" + switch \builder_sdcore_fsm_state + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\main_sdphy_cmdw_sink_valid[0:0] 1'1 + attribute \src "ls180.v:5138.4-5158.11" + switch \main_sdcore_cmd_count + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\main_sdphy_cmdw_sink_payload_data[7:0] { 2'01 \main_sdcore_cmd_command_storage [13:8] } + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\main_sdphy_cmdw_sink_payload_data[7:0] \main_sdcore_cmd_argument_storage [31:24] + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\main_sdphy_cmdw_sink_payload_data[7:0] \main_sdcore_cmd_argument_storage [23:16] + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\main_sdphy_cmdw_sink_payload_data[7:0] \main_sdcore_cmd_argument_storage [15:8] + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\main_sdphy_cmdw_sink_payload_data[7:0] \main_sdcore_cmd_argument_storage [7:0] + attribute \src "ls180.v:0.0-0.0" + case 3'101 + assign $0\main_sdphy_cmdw_sink_payload_data[7:0] { \main_sdcore_crc7_inserter_crc 1'1 } + assign $0\main_sdphy_cmdw_sink_last[0:0] $eq$ls180.v:5156$955_Y + case + end + attribute \src "ls180.v:5159.4-5171.7" + switch $and$ls180.v:5159$956_Y + attribute \src "ls180.v:5159.8-5159.65" + case 1'1 + assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] $add$ls180.v:5160$957_Y + assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] 1'1 + attribute \src "ls180.v:5162.5-5170.8" + switch $eq$ls180.v:5162$958_Y + attribute \src "ls180.v:5162.9-5162.40" + case 1'1 + attribute \src "ls180.v:5163.6-5169.9" + switch $eq$ls180.v:5163$959_Y + attribute \src "ls180.v:5163.10-5163.40" + case 1'1 + assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] 1'1 + assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] 1'1 + assign $0\builder_sdcore_fsm_next_state[2:0] 3'000 + attribute \src "ls180.v:5167.10-5167.14" + case + assign $0\builder_sdcore_fsm_next_state[2:0] 3'010 + end + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\main_sdphy_cmdr_sink_valid[0:0] 1'1 + assign $0\main_sdphy_cmdr_sink_last[0:0] $eq$ls180.v:5175$960_Y + assign $0\main_sdphy_cmdr_source_ready[0:0] 1'1 + attribute \src "ls180.v:5176.4-5180.7" + switch $eq$ls180.v:5176$961_Y + attribute \src "ls180.v:5176.8-5176.38" + case 1'1 + assign $0\main_sdphy_cmdr_sink_payload_length[7:0] 8'00010001 + attribute \src "ls180.v:5178.8-5178.12" + case + assign $0\main_sdphy_cmdr_sink_payload_length[7:0] 8'00000110 + end + attribute \src "ls180.v:5182.4-5203.7" + switch \main_sdphy_cmdr_source_valid + attribute \src "ls180.v:5182.8-5182.36" + case 1'1 + attribute \src "ls180.v:5183.5-5202.8" + switch $eq$ls180.v:5183$962_Y + attribute \src "ls180.v:5183.9-5183.56" + case 1'1 + assign $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] 1'1 + assign $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] 1'1 + assign $0\builder_sdcore_fsm_next_state[2:0] 3'000 + attribute \src "ls180.v:5187.9-5187.13" + case + attribute \src "ls180.v:5188.6-5201.9" + switch \main_sdphy_cmdr_source_last + attribute \src "ls180.v:5188.10-5188.37" + case 1'1 + attribute \src "ls180.v:5189.7-5197.10" + switch $eq$ls180.v:5189$963_Y + attribute \src "ls180.v:5189.11-5189.42" + case 1'1 + assign $0\builder_sdcore_fsm_next_state[2:0] 3'011 + attribute \src "ls180.v:5191.11-5191.15" + case + attribute \src "ls180.v:5192.8-5196.11" + switch $eq$ls180.v:5192$964_Y + attribute \src "ls180.v:5192.12-5192.43" + case 1'1 + assign $0\builder_sdcore_fsm_next_state[2:0] 3'100 + attribute \src "ls180.v:5194.12-5194.16" + case + assign $0\builder_sdcore_fsm_next_state[2:0] 3'000 + end + end + attribute \src "ls180.v:5198.10-5198.14" + case + assign $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] { \main_sdcore_cmd_response_status [119:0] \main_sdphy_cmdr_source_payload_data } + assign $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] 1'1 + end + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\main_sdphy_dataw_sink_valid[0:0] \main_sdcore_crc16_inserter_source_valid + assign $0\main_sdcore_crc16_inserter_source_ready[0:0] \main_sdphy_dataw_sink_ready + assign $0\main_sdphy_dataw_sink_first[0:0] \main_sdcore_crc16_inserter_source_first + assign $0\main_sdphy_dataw_sink_last[0:0] \main_sdcore_crc16_inserter_source_last + assign $0\main_sdphy_dataw_sink_payload_data[7:0] \main_sdcore_crc16_inserter_source_payload_data + assign $0\main_sdphy_datar_source_ready[0:0] 1'1 + attribute \src "ls180.v:5211.4-5217.7" + switch $and$ls180.v:5211$966_Y + attribute \src "ls180.v:5211.8-5211.98" + case 1'1 + assign $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] $add$ls180.v:5212$967_Y + assign $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'1 + attribute \src "ls180.v:5214.5-5216.8" + switch $eq$ls180.v:5214$969_Y + attribute \src "ls180.v:5214.9-5214.77" + case 1'1 + assign $0\builder_sdcore_fsm_next_state[2:0] 3'000 + case + end + case + end + attribute \src "ls180.v:5219.4-5224.7" + switch \main_sdphy_datar_source_valid + attribute \src "ls180.v:5219.8-5219.37" + case 1'1 + attribute \src "ls180.v:5220.5-5223.8" + switch $ne$ls180.v:5220$970_Y + attribute \src "ls180.v:5220.9-5220.57" + case 1'1 + assign $0\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] 1'1 + assign $0\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] 1'1 + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\main_sdphy_datar_sink_valid[0:0] 1'1 + assign $0\main_sdphy_datar_sink_payload_block_length[9:0] \main_sdcore_block_length_storage + assign $0\main_sdphy_datar_sink_last[0:0] $eq$ls180.v:5229$972_Y + attribute \src "ls180.v:5230.4-5256.7" + switch \main_sdphy_datar_source_valid + attribute \src "ls180.v:5230.8-5230.37" + case 1'1 + attribute \src "ls180.v:5231.5-5255.8" + switch $eq$ls180.v:5231$973_Y + attribute \src "ls180.v:5231.9-5231.57" + case 1'1 + assign $0\main_sdcore_crc16_checker_sink_valid[0:0] \main_sdphy_datar_source_valid + assign $0\main_sdphy_datar_source_ready[0:0] \main_sdcore_crc16_checker_sink_ready + assign $0\main_sdcore_crc16_checker_sink_first[0:0] \main_sdphy_datar_source_first + assign $0\main_sdcore_crc16_checker_sink_last[0:0] \main_sdphy_datar_source_last + assign $0\main_sdcore_crc16_checker_sink_payload_data[7:0] \main_sdphy_datar_source_payload_data + attribute \src "ls180.v:5237.6-5245.9" + switch $and$ls180.v:5237$974_Y + attribute \src "ls180.v:5237.10-5237.72" + case 1'1 + assign $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] $add$ls180.v:5238$975_Y + assign $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'1 + attribute \src "ls180.v:5240.7-5244.10" + switch $eq$ls180.v:5240$977_Y + attribute \src "ls180.v:5240.11-5240.79" + case 1'1 + assign $0\builder_sdcore_fsm_next_state[2:0] 3'000 + attribute \src "ls180.v:5242.11-5242.15" + case + assign $0\builder_sdcore_fsm_next_state[2:0] 3'100 + end + case + end + attribute \src "ls180.v:5246.9-5246.13" + case + attribute \src "ls180.v:5247.6-5254.9" + switch $eq$ls180.v:5247$978_Y + attribute \src "ls180.v:5247.10-5247.58" + case 1'1 + assign $0\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] 1'1 + assign $0\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] 1'1 + assign $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] 0 + assign $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'1 + assign $0\main_sdphy_datar_source_ready[0:0] 1'1 + assign $0\builder_sdcore_fsm_next_state[2:0] 3'000 + case + end + end + case + end + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] 1'1 + assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] 1'1 + assign $0\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] 1'1 + assign $0\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] 1'1 + assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] 3'000 + assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] 1'1 + assign $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] 0 + assign $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'1 + attribute \src "ls180.v:5267.4-5281.7" + switch \main_sdcore_cmd_send_re + attribute \src "ls180.v:5267.8-5267.31" + case 1'1 + assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] 1'0 + assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] 1'1 + assign $0\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] 1'0 + assign $0\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] 1'1 + assign $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] 1'0 + assign $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] 1'1 + assign $0\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] 1'0 + assign $0\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] 1'1 + assign $0\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] 1'0 + assign $0\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] 1'1 + assign $0\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] 1'0 + assign $0\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] 1'1 + assign $0\builder_sdcore_fsm_next_state[2:0] 3'001 + case + end + end + sync always + update \main_sdphy_cmdw_sink_valid $0\main_sdphy_cmdw_sink_valid[0:0] + update \main_sdphy_cmdw_sink_last $0\main_sdphy_cmdw_sink_last[0:0] + update \main_sdphy_cmdw_sink_payload_data $0\main_sdphy_cmdw_sink_payload_data[7:0] + update \main_sdphy_cmdr_sink_valid $0\main_sdphy_cmdr_sink_valid[0:0] + update \main_sdphy_cmdr_sink_last $0\main_sdphy_cmdr_sink_last[0:0] + update \main_sdphy_cmdr_sink_payload_length $0\main_sdphy_cmdr_sink_payload_length[7:0] + update \main_sdphy_cmdr_source_ready $0\main_sdphy_cmdr_source_ready[0:0] + update \main_sdphy_dataw_sink_valid $0\main_sdphy_dataw_sink_valid[0:0] + update \main_sdphy_dataw_sink_first $0\main_sdphy_dataw_sink_first[0:0] + update \main_sdphy_dataw_sink_last $0\main_sdphy_dataw_sink_last[0:0] + update \main_sdphy_dataw_sink_payload_data $0\main_sdphy_dataw_sink_payload_data[7:0] + update \main_sdphy_datar_sink_valid $0\main_sdphy_datar_sink_valid[0:0] + update \main_sdphy_datar_sink_last $0\main_sdphy_datar_sink_last[0:0] + update \main_sdphy_datar_sink_payload_block_length $0\main_sdphy_datar_sink_payload_block_length[9:0] + update \main_sdphy_datar_source_ready $0\main_sdphy_datar_source_ready[0:0] + update \main_sdcore_crc16_inserter_source_ready $0\main_sdcore_crc16_inserter_source_ready[0:0] + update \main_sdcore_crc16_checker_sink_valid $0\main_sdcore_crc16_checker_sink_valid[0:0] + update \main_sdcore_crc16_checker_sink_first $0\main_sdcore_crc16_checker_sink_first[0:0] + update \main_sdcore_crc16_checker_sink_last $0\main_sdcore_crc16_checker_sink_last[0:0] + update \main_sdcore_crc16_checker_sink_payload_data $0\main_sdcore_crc16_checker_sink_payload_data[7:0] + update \builder_sdcore_fsm_next_state $0\builder_sdcore_fsm_next_state[2:0] + update \main_sdcore_cmd_done_sdcore_fsm_next_value0 $0\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] + update \main_sdcore_cmd_done_sdcore_fsm_next_value_ce0 $0\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] + update \main_sdcore_data_done_sdcore_fsm_next_value1 $0\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] + update \main_sdcore_data_done_sdcore_fsm_next_value_ce1 $0\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] + update \main_sdcore_cmd_count_sdcore_fsm_next_value2 $0\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] + update \main_sdcore_cmd_count_sdcore_fsm_next_value_ce2 $0\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] + update \main_sdcore_data_count_sdcore_fsm_next_value3 $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] + update \main_sdcore_data_count_sdcore_fsm_next_value_ce3 $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] + update \main_sdcore_cmd_error_sdcore_fsm_next_value4 $0\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] + update \main_sdcore_cmd_error_sdcore_fsm_next_value_ce4 $0\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] + update \main_sdcore_cmd_timeout_sdcore_fsm_next_value5 $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] + update \main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5 $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] + update \main_sdcore_data_error_sdcore_fsm_next_value6 $0\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] + update \main_sdcore_data_error_sdcore_fsm_next_value_ce6 $0\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] + update \main_sdcore_data_timeout_sdcore_fsm_next_value7 $0\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] + update \main_sdcore_data_timeout_sdcore_fsm_next_value_ce7 $0\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] + update \main_sdcore_cmd_response_status_sdcore_fsm_next_value8 $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] + update \main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8 $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] + end + attribute \src "ls180.v:51.12-51.60" + process $proc$ls180.v:51$2767 + assign { } { } + assign $1\main_libresocsim_scratch_storage[31:0] 305419896 + sync always + sync init + update \main_libresocsim_scratch_storage $1\main_libresocsim_scratch_storage[31:0] + end + attribute \src "ls180.v:52.5-52.39" + process $proc$ls180.v:52$2768 + assign { } { } + assign $1\main_libresocsim_scratch_re[0:0] 1'0 + sync always + sync init + update \main_libresocsim_scratch_re $1\main_libresocsim_scratch_re[0:0] + end + attribute \src "ls180.v:523.5-523.59" + process $proc$ls180.v:523$2950 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_cmd_buffer_source_valid $1\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] + end + attribute \src "ls180.v:525.5-525.59" + process $proc$ls180.v:525$2951 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_cmd_buffer_source_first $1\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] + end + attribute \src "ls180.v:526.5-526.58" + process $proc$ls180.v:526$2952 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_cmd_buffer_source_last $1\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] + end + attribute \src "ls180.v:527.5-527.64" + process $proc$ls180.v:527$2953 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_cmd_buffer_source_payload_we $1\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] + end + attribute \src "ls180.v:528.12-528.74" + process $proc$ls180.v:528$2954 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000 + sync always + sync init + update \main_sdram_bankmachine1_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] + end + attribute \src "ls180.v:529.12-529.47" + process $proc$ls180.v:529$2955 + assign { } { } + assign $1\main_sdram_bankmachine1_row[12:0] 13'0000000000000 + sync always + sync init + update \main_sdram_bankmachine1_row $1\main_sdram_bankmachine1_row[12:0] + end + attribute \src "ls180.v:530.5-530.46" + process $proc$ls180.v:530$2956 + assign { } { } + assign $1\main_sdram_bankmachine1_row_opened[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_row_opened $1\main_sdram_bankmachine1_row_opened[0:0] + end + attribute \src "ls180.v:5312.1-5319.4" + process $proc$ls180.v:5312$979 + assign { } { } + assign $0\main_sdblock2mem_fifo_wrport_adr[4:0] 5'00000 + attribute \src "ls180.v:5314.2-5318.5" + switch \main_sdblock2mem_fifo_replace + attribute \src "ls180.v:5314.6-5314.35" + case 1'1 + assign $0\main_sdblock2mem_fifo_wrport_adr[4:0] $sub$ls180.v:5315$980_Y + attribute \src "ls180.v:5316.6-5316.10" + case + assign $0\main_sdblock2mem_fifo_wrport_adr[4:0] \main_sdblock2mem_fifo_produce + end + sync always + update \main_sdblock2mem_fifo_wrport_adr $0\main_sdblock2mem_fifo_wrport_adr[4:0] + end + attribute \src "ls180.v:532.5-532.44" + process $proc$ls180.v:532$2957 + assign { } { } + assign $1\main_sdram_bankmachine1_row_open[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_row_open $1\main_sdram_bankmachine1_row_open[0:0] + end + attribute \src "ls180.v:533.5-533.45" + process $proc$ls180.v:533$2958 + assign { } { } + assign $1\main_sdram_bankmachine1_row_close[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_row_close $1\main_sdram_bankmachine1_row_close[0:0] + end + attribute \src "ls180.v:534.5-534.54" + process $proc$ls180.v:534$2959 + assign { } { } + assign $1\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_row_col_n_addr_sel $1\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] + end + attribute \src "ls180.v:5345.1-5384.4" + process $proc$ls180.v:5345$990 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdblock2mem_sink_sink_payload_data1[31:0] 0 + assign $0\main_sdblock2mem_wishbonedmawriter_status[0:0] 1'0 + assign $0\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] 1'0 + assign { } { } + assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] 0 + assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] 1'0 + assign $0\main_sdblock2mem_sink_sink_valid1[0:0] 1'0 + assign $0\main_sdblock2mem_sink_sink_payload_address[31:0] 0 + assign $0\builder_sdblock2memdma_next_state[1:0] \builder_sdblock2memdma_state + attribute \src "ls180.v:5355.2-5383.9" + switch \builder_sdblock2memdma_state + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\main_sdblock2mem_sink_sink_valid1[0:0] \main_sdblock2mem_wishbonedmawriter_sink_valid + assign $0\main_sdblock2mem_sink_sink_payload_data1[31:0] \main_sdblock2mem_wishbonedmawriter_sink_payload_data + assign $0\main_sdblock2mem_sink_sink_payload_address[31:0] $add$ls180.v:5359$991_Y + assign $0\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] \main_sdblock2mem_sink_sink_ready1 + attribute \src "ls180.v:5361.4-5372.7" + switch $and$ls180.v:5361$992_Y + attribute \src "ls180.v:5361.8-5361.103" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] $add$ls180.v:5362$993_Y + assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:5364.5-5371.8" + switch $eq$ls180.v:5364$995_Y + attribute \src "ls180.v:5364.9-5364.106" + case 1'1 + attribute \src "ls180.v:5365.6-5370.9" + switch \main_sdblock2mem_wishbonedmawriter_loop_storage + attribute \src "ls180.v:5365.10-5365.57" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] 0 + assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:5368.10-5368.14" + case + assign $0\builder_sdblock2memdma_next_state[1:0] 2'10 + end + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\main_sdblock2mem_wishbonedmawriter_status[0:0] 1'1 + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] 0 + assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] 1'1 + assign $0\builder_sdblock2memdma_next_state[1:0] 2'01 + end + sync always + update \main_sdblock2mem_sink_sink_valid1 $0\main_sdblock2mem_sink_sink_valid1[0:0] + update \main_sdblock2mem_sink_sink_payload_address $0\main_sdblock2mem_sink_sink_payload_address[31:0] + update \main_sdblock2mem_sink_sink_payload_data1 $0\main_sdblock2mem_sink_sink_payload_data1[31:0] + update \main_sdblock2mem_wishbonedmawriter_sink_ready $0\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] + update \main_sdblock2mem_wishbonedmawriter_status $0\main_sdblock2mem_wishbonedmawriter_status[0:0] + update \builder_sdblock2memdma_next_state $0\builder_sdblock2memdma_next_state[1:0] + update \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] + update \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] + end + attribute \src "ls180.v:536.32-536.76" + process $proc$ls180.v:536$2960 + assign { } { } + assign $1\main_sdram_bankmachine1_twtpcon_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_twtpcon_ready $1\main_sdram_bankmachine1_twtpcon_ready[0:0] + end + attribute \src "ls180.v:537.11-537.55" + process $proc$ls180.v:537$2961 + assign { } { } + assign $1\main_sdram_bankmachine1_twtpcon_count[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine1_twtpcon_count $1\main_sdram_bankmachine1_twtpcon_count[2:0] + end + attribute \src "ls180.v:539.32-539.75" + process $proc$ls180.v:539$2962 + assign { } { } + assign $0\main_sdram_bankmachine1_trccon_ready[0:0] 1'1 + sync always + update \main_sdram_bankmachine1_trccon_ready $0\main_sdram_bankmachine1_trccon_ready[0:0] + sync init + end + attribute \src "ls180.v:5404.1-5441.4" + process $proc$ls180.v:5404$997 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_interface1_bus_adr[31:0] 0 + assign $0\main_sdmem2block_dma_sink_ready[0:0] 1'0 + assign { } { } + assign $0\main_interface1_bus_sel[3:0] 4'0000 + assign $0\main_interface1_bus_cyc[0:0] 1'0 + assign $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[31:0] 0 + assign $0\main_interface1_bus_stb[0:0] 1'0 + assign $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] 1'0 + assign $0\main_sdmem2block_dma_source_valid[0:0] 1'0 + assign $0\main_interface1_bus_we[0:0] 1'0 + assign $0\main_sdmem2block_dma_source_last[0:0] 1'0 + assign $0\main_sdmem2block_dma_source_payload_data[31:0] 0 + assign $0\builder_sdmem2blockdma_fsm_next_state[0:0] \builder_sdmem2blockdma_fsm_state + attribute \src "ls180.v:5418.2-5440.9" + switch \builder_sdmem2blockdma_fsm_state + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\main_sdmem2block_dma_source_valid[0:0] 1'1 + assign $0\main_sdmem2block_dma_source_last[0:0] \main_sdmem2block_dma_sink_last + assign $0\main_sdmem2block_dma_source_payload_data[31:0] \main_sdmem2block_dma_data + attribute \src "ls180.v:5423.4-5426.7" + switch \main_sdmem2block_dma_source_ready + attribute \src "ls180.v:5423.8-5423.41" + case 1'1 + assign $0\main_sdmem2block_dma_sink_ready[0:0] 1'1 + assign $0\builder_sdmem2blockdma_fsm_next_state[0:0] 1'0 + case + end + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_interface1_bus_stb[0:0] \main_sdmem2block_dma_sink_valid + assign $0\main_interface1_bus_cyc[0:0] \main_sdmem2block_dma_sink_valid + assign $0\main_interface1_bus_we[0:0] 1'0 + assign $0\main_interface1_bus_sel[3:0] 4'1111 + assign $0\main_interface1_bus_adr[31:0] \main_sdmem2block_dma_sink_payload_address + attribute \src "ls180.v:5434.4-5438.7" + switch $and$ls180.v:5434$998_Y + attribute \src "ls180.v:5434.8-5434.59" + case 1'1 + assign $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[31:0] { \main_interface1_bus_dat_r [7:0] \main_interface1_bus_dat_r [15:8] \main_interface1_bus_dat_r [23:16] \main_interface1_bus_dat_r [31:24] } + assign $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] 1'1 + assign $0\builder_sdmem2blockdma_fsm_next_state[0:0] 1'1 + case + end + end + sync always + update \main_interface1_bus_adr $0\main_interface1_bus_adr[31:0] + update \main_interface1_bus_sel $0\main_interface1_bus_sel[3:0] + update \main_interface1_bus_cyc $0\main_interface1_bus_cyc[0:0] + update \main_interface1_bus_stb $0\main_interface1_bus_stb[0:0] + update \main_interface1_bus_we $0\main_interface1_bus_we[0:0] + update \main_sdmem2block_dma_sink_ready $0\main_sdmem2block_dma_sink_ready[0:0] + update \main_sdmem2block_dma_source_valid $0\main_sdmem2block_dma_source_valid[0:0] + update \main_sdmem2block_dma_source_last $0\main_sdmem2block_dma_source_last[0:0] + update \main_sdmem2block_dma_source_payload_data $0\main_sdmem2block_dma_source_payload_data[31:0] + update \builder_sdmem2blockdma_fsm_next_state $0\builder_sdmem2blockdma_fsm_next_state[0:0] + update \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[31:0] + update \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] + end + attribute \src "ls180.v:541.32-541.76" + process $proc$ls180.v:541$2963 + assign { } { } + assign $0\main_sdram_bankmachine1_trascon_ready[0:0] 1'1 + sync always + update \main_sdram_bankmachine1_trascon_ready $0\main_sdram_bankmachine1_trascon_ready[0:0] + sync init + end + attribute \src "ls180.v:5442.1-5478.4" + process $proc$ls180.v:5442$999 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdmem2block_dma_sink_valid[0:0] 1'0 + assign $0\main_sdmem2block_dma_done_status[0:0] 1'0 + assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] 0 + assign $0\main_sdmem2block_dma_sink_last[0:0] 1'0 + assign { } { } + assign $0\main_sdmem2block_dma_sink_payload_address[31:0] 0 + assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] 1'0 + assign $0\builder_sdmem2blockdma_resetinserter_next_state[1:0] \builder_sdmem2blockdma_resetinserter_state + attribute \src "ls180.v:5451.2-5477.9" + switch \builder_sdmem2blockdma_resetinserter_state + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\main_sdmem2block_dma_sink_valid[0:0] 1'1 + assign $0\main_sdmem2block_dma_sink_last[0:0] $eq$ls180.v:5454$1001_Y + assign $0\main_sdmem2block_dma_sink_payload_address[31:0] $add$ls180.v:5455$1002_Y + attribute \src "ls180.v:5456.4-5467.7" + switch \main_sdmem2block_dma_sink_ready + attribute \src "ls180.v:5456.8-5456.39" + case 1'1 + assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] $add$ls180.v:5457$1003_Y + assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:5459.5-5466.8" + switch \main_sdmem2block_dma_sink_last + attribute \src "ls180.v:5459.9-5459.39" + case 1'1 + attribute \src "ls180.v:5460.6-5465.9" + switch \main_sdmem2block_dma_loop_storage + attribute \src "ls180.v:5460.10-5460.43" + case 1'1 + assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] 0 + assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:5463.10-5463.14" + case + assign $0\builder_sdmem2blockdma_resetinserter_next_state[1:0] 2'10 + end + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\main_sdmem2block_dma_done_status[0:0] 1'1 + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] 0 + assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] 1'1 + assign $0\builder_sdmem2blockdma_resetinserter_next_state[1:0] 2'01 + end + sync always + update \main_sdmem2block_dma_sink_valid $0\main_sdmem2block_dma_sink_valid[0:0] + update \main_sdmem2block_dma_sink_last $0\main_sdmem2block_dma_sink_last[0:0] + update \main_sdmem2block_dma_sink_payload_address $0\main_sdmem2block_dma_sink_payload_address[31:0] + update \main_sdmem2block_dma_done_status $0\main_sdmem2block_dma_done_status[0:0] + update \builder_sdmem2blockdma_resetinserter_next_state $0\builder_sdmem2blockdma_resetinserter_next_state[1:0] + update \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] + update \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] + end + attribute \src "ls180.v:547.5-547.51" + process $proc$ls180.v:547$2964 + assign { } { } + assign $1\main_sdram_bankmachine2_req_wdata_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_req_wdata_ready $1\main_sdram_bankmachine2_req_wdata_ready[0:0] + end + attribute \src "ls180.v:548.5-548.51" + process $proc$ls180.v:548$2965 + assign { } { } + assign $1\main_sdram_bankmachine2_req_rdata_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_req_rdata_valid $1\main_sdram_bankmachine2_req_rdata_valid[0:0] + end + attribute \src "ls180.v:5490.1-5506.4" + process $proc$ls180.v:5490$1009 + assign { } { } + assign $0\main_sdmem2block_converter_source_payload_data[7:0] 8'00000000 + attribute \src "ls180.v:5492.2-5505.9" + switch \main_sdmem2block_converter_mux + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\main_sdmem2block_converter_source_payload_data[7:0] \main_sdmem2block_converter_sink_payload_data [31:24] + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\main_sdmem2block_converter_source_payload_data[7:0] \main_sdmem2block_converter_sink_payload_data [23:16] + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\main_sdmem2block_converter_source_payload_data[7:0] \main_sdmem2block_converter_sink_payload_data [15:8] + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_sdmem2block_converter_source_payload_data[7:0] \main_sdmem2block_converter_sink_payload_data [7:0] + end + sync always + update \main_sdmem2block_converter_source_payload_data $0\main_sdmem2block_converter_source_payload_data[7:0] + end + attribute \src "ls180.v:550.5-550.47" + process $proc$ls180.v:550$2966 + assign { } { } + assign $1\main_sdram_bankmachine2_refresh_gnt[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_refresh_gnt $1\main_sdram_bankmachine2_refresh_gnt[0:0] + end + attribute \src "ls180.v:551.5-551.45" + process $proc$ls180.v:551$2967 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_cmd_valid $1\main_sdram_bankmachine2_cmd_valid[0:0] + end + attribute \src "ls180.v:552.5-552.45" + process $proc$ls180.v:552$2968 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_cmd_ready $1\main_sdram_bankmachine2_cmd_ready[0:0] + end + attribute \src "ls180.v:5520.1-5527.4" + process $proc$ls180.v:5520$1010 + assign { } { } + assign $0\main_sdmem2block_fifo_wrport_adr[4:0] 5'00000 + attribute \src "ls180.v:5522.2-5526.5" + switch \main_sdmem2block_fifo_replace + attribute \src "ls180.v:5522.6-5522.35" + case 1'1 + assign $0\main_sdmem2block_fifo_wrport_adr[4:0] $sub$ls180.v:5523$1011_Y + attribute \src "ls180.v:5524.6-5524.10" + case + assign $0\main_sdmem2block_fifo_wrport_adr[4:0] \main_sdmem2block_fifo_produce + end + sync always + update \main_sdmem2block_fifo_wrport_adr $0\main_sdmem2block_fifo_wrport_adr[4:0] + end + attribute \src "ls180.v:553.12-553.57" + process $proc$ls180.v:553$2969 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_payload_a[12:0] 13'0000000000000 + sync always + sync init + update \main_sdram_bankmachine2_cmd_payload_a $1\main_sdram_bankmachine2_cmd_payload_a[12:0] + end + attribute \src "ls180.v:5545.1-5593.4" + process $proc$ls180.v:5545$1021 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\libresocsim_clk_enable[0:0] 1'0 + assign $0\libresocsim_count_spimaster1_next_value[2:0] 3'000 + assign $0\libresocsim_cs_enable[0:0] 1'0 + assign $0\libresocsim_count_spimaster1_next_value_ce[0:0] 1'0 + assign $0\libresocsim_mosi_latch[0:0] 1'0 + assign $0\libresocsim_done0[0:0] 1'0 + assign $0\libresocsim_irq[0:0] 1'0 + assign $0\libresocsim_miso_latch[0:0] 1'0 + assign $0\builder_spimaster1_next_state[1:0] \builder_spimaster1_state + attribute \src "ls180.v:5556.2-5592.9" + switch \builder_spimaster1_state + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\libresocsim_count_spimaster1_next_value[2:0] 3'000 + assign $0\libresocsim_count_spimaster1_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:5560.4-5563.7" + switch \libresocsim_clk_fall + attribute \src "ls180.v:5560.8-5560.28" + case 1'1 + assign $0\libresocsim_cs_enable[0:0] 1'1 + assign $0\builder_spimaster1_next_state[1:0] 2'10 + case + end + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\libresocsim_clk_enable[0:0] 1'1 + assign $0\libresocsim_cs_enable[0:0] 1'1 + attribute \src "ls180.v:5568.4-5574.7" + switch \libresocsim_clk_fall + attribute \src "ls180.v:5568.8-5568.28" + case 1'1 + assign $0\libresocsim_count_spimaster1_next_value[2:0] $add$ls180.v:5569$1022_Y + assign $0\libresocsim_count_spimaster1_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:5571.5-5573.8" + switch $eq$ls180.v:5571$1024_Y + attribute \src "ls180.v:5571.9-5571.60" + case 1'1 + assign $0\builder_spimaster1_next_state[1:0] 2'11 + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 2'11 + assign $0\libresocsim_cs_enable[0:0] 1'1 + attribute \src "ls180.v:5578.4-5582.7" + switch \libresocsim_clk_rise + attribute \src "ls180.v:5578.8-5578.28" + case 1'1 + assign $0\libresocsim_miso_latch[0:0] 1'1 + assign $0\libresocsim_irq[0:0] 1'1 + assign $0\builder_spimaster1_next_state[1:0] 2'00 + case + end + attribute \src "ls180.v:0.0-0.0" + case + assign $0\libresocsim_done0[0:0] 1'1 + attribute \src "ls180.v:5586.4-5590.7" + switch \libresocsim_start0 + attribute \src "ls180.v:5586.8-5586.26" + case 1'1 + assign $0\libresocsim_done0[0:0] 1'0 + assign $0\libresocsim_mosi_latch[0:0] 1'1 + assign $0\builder_spimaster1_next_state[1:0] 2'01 + case + end + end + sync always + update \libresocsim_done0 $0\libresocsim_done0[0:0] + update \libresocsim_irq $0\libresocsim_irq[0:0] + update \libresocsim_clk_enable $0\libresocsim_clk_enable[0:0] + update \libresocsim_cs_enable $0\libresocsim_cs_enable[0:0] + update \libresocsim_mosi_latch $0\libresocsim_mosi_latch[0:0] + update \libresocsim_miso_latch $0\libresocsim_miso_latch[0:0] + update \builder_spimaster1_next_state $0\builder_spimaster1_next_state[1:0] + update \libresocsim_count_spimaster1_next_value $0\libresocsim_count_spimaster1_next_value[2:0] + update \libresocsim_count_spimaster1_next_value_ce $0\libresocsim_count_spimaster1_next_value_ce[0:0] + end + attribute \src "ls180.v:555.5-555.51" + process $proc$ls180.v:555$2970 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_payload_cas[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_cmd_payload_cas $1\main_sdram_bankmachine2_cmd_payload_cas[0:0] + end + attribute \src "ls180.v:556.5-556.51" + process $proc$ls180.v:556$2971 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_payload_ras[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_cmd_payload_ras $1\main_sdram_bankmachine2_cmd_payload_ras[0:0] + end + attribute \src "ls180.v:557.5-557.50" + process $proc$ls180.v:557$2972 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_payload_we[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_cmd_payload_we $1\main_sdram_bankmachine2_cmd_payload_we[0:0] + end + attribute \src "ls180.v:558.5-558.54" + process $proc$ls180.v:558$2973 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_cmd_payload_is_cmd $1\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] + end + attribute \src "ls180.v:559.5-559.55" + process $proc$ls180.v:559$2974 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_payload_is_read[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_cmd_payload_is_read $1\main_sdram_bankmachine2_cmd_payload_is_read[0:0] + end + attribute \src "ls180.v:5594.1-5630.4" + process $proc$ls180.v:5594$1025 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\builder_libresocsim_dat_w_next_value0[7:0] 8'00000000 + assign $0\builder_libresocsim_dat_w_next_value_ce0[0:0] 1'0 + assign $0\builder_libresocsim_adr_next_value1[13:0] 14'00000000000000 + assign $0\builder_libresocsim_adr_next_value_ce1[0:0] 1'0 + assign $0\builder_libresocsim_we_next_value2[0:0] 1'0 + assign $0\builder_libresocsim_we_next_value_ce2[0:0] 1'0 + assign $0\builder_libresocsim_wishbone_dat_r[31:0] 0 + assign $0\builder_libresocsim_wishbone_ack[0:0] 1'0 + assign $0\builder_next_state[1:0] \builder_state + attribute \src "ls180.v:5605.2-5629.9" + switch \builder_state + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_libresocsim_adr_next_value1[13:0] 14'00000000000000 + assign $0\builder_libresocsim_adr_next_value_ce1[0:0] 1'1 + assign $0\builder_libresocsim_we_next_value2[0:0] 1'0 + assign $0\builder_libresocsim_we_next_value_ce2[0:0] 1'1 + assign $0\builder_next_state[1:0] 2'10 + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_libresocsim_wishbone_ack[0:0] 1'1 + assign $0\builder_libresocsim_wishbone_dat_r[31:0] { 24'000000000000000000000000 \builder_libresocsim_dat_r } + assign $0\builder_next_state[1:0] 2'00 + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_libresocsim_dat_w_next_value0[7:0] \builder_libresocsim_wishbone_dat_w [7:0] + assign $0\builder_libresocsim_dat_w_next_value_ce0[0:0] 1'1 + attribute \src "ls180.v:5621.4-5627.7" + switch $and$ls180.v:5621$1026_Y + attribute \src "ls180.v:5621.8-5621.77" + case 1'1 + assign $0\builder_libresocsim_adr_next_value1[13:0] \builder_libresocsim_wishbone_adr [13:0] + assign $0\builder_libresocsim_adr_next_value_ce1[0:0] 1'1 + assign $0\builder_libresocsim_we_next_value2[0:0] $and$ls180.v:5624$1028_Y + assign $0\builder_libresocsim_we_next_value_ce2[0:0] 1'1 + assign $0\builder_next_state[1:0] 2'01 + case + end + end + sync always + update \builder_libresocsim_wishbone_dat_r $0\builder_libresocsim_wishbone_dat_r[31:0] + update \builder_libresocsim_wishbone_ack $0\builder_libresocsim_wishbone_ack[0:0] + update \builder_next_state $0\builder_next_state[1:0] + update \builder_libresocsim_dat_w_next_value0 $0\builder_libresocsim_dat_w_next_value0[7:0] + update \builder_libresocsim_dat_w_next_value_ce0 $0\builder_libresocsim_dat_w_next_value_ce0[0:0] + update \builder_libresocsim_adr_next_value1 $0\builder_libresocsim_adr_next_value1[13:0] + update \builder_libresocsim_adr_next_value_ce1 $0\builder_libresocsim_adr_next_value_ce1[0:0] + update \builder_libresocsim_we_next_value2 $0\builder_libresocsim_we_next_value2[0:0] + update \builder_libresocsim_we_next_value_ce2 $0\builder_libresocsim_we_next_value_ce2[0:0] + end + attribute \src "ls180.v:560.5-560.56" + process $proc$ls180.v:560$2975 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_payload_is_write[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_cmd_payload_is_write $1\main_sdram_bankmachine2_cmd_payload_is_write[0:0] + end + attribute \src "ls180.v:561.5-561.50" + process $proc$ls180.v:561$2976 + assign { } { } + assign $1\main_sdram_bankmachine2_auto_precharge[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_auto_precharge $1\main_sdram_bankmachine2_auto_precharge[0:0] + end + attribute \src "ls180.v:564.5-564.67" + process $proc$ls180.v:564$2977 + assign { } { } + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first[0:0] 1'0 + sync always + update \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first[0:0] + sync init + end + attribute \src "ls180.v:565.5-565.66" + process $proc$ls180.v:565$2978 + assign { } { } + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last[0:0] 1'0 + sync always + update \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last[0:0] + sync init + end + attribute \src "ls180.v:5655.1-5662.4" + process $proc$ls180.v:5655$1049 + assign { } { } + assign { } { } + assign $0\builder_slave_sel[4:0] [0] $eq$ls180.v:5657$1050_Y + assign $0\builder_slave_sel[4:0] [1] $eq$ls180.v:5658$1051_Y + assign $0\builder_slave_sel[4:0] [2] $eq$ls180.v:5659$1052_Y + assign $0\builder_slave_sel[4:0] [3] $eq$ls180.v:5660$1053_Y + assign $0\builder_slave_sel[4:0] [4] $eq$ls180.v:5661$1054_Y + sync always + update \builder_slave_sel $0\builder_slave_sel[4:0] + end + attribute \src "ls180.v:57.12-57.47" + process $proc$ls180.v:57$2769 + assign { } { } + assign $1\main_libresocsim_bus_errors[31:0] 0 + sync always + sync init + update \main_libresocsim_bus_errors $1\main_libresocsim_bus_errors[31:0] + end + attribute \src "ls180.v:5705.1-5716.4" + process $proc$ls180.v:5705$1067 + assign { } { } + assign { } { } + assign { } { } + assign $0\builder_error[0:0] 1'0 + assign { } { } + assign { } { } + assign $0\builder_shared_ack[0:0] $or$ls180.v:5709$1071_Y + assign $0\builder_shared_dat_r[31:0] $or$ls180.v:5710$1080_Y + attribute \src "ls180.v:5711.2-5715.5" + switch \builder_done + attribute \src "ls180.v:5711.6-5711.18" + case 1'1 + assign $0\builder_shared_dat_r[31:0] 32'11111111111111111111111111111111 + assign $0\builder_shared_ack[0:0] 1'1 + assign $0\builder_error[0:0] 1'1 + case + end + sync always + update \builder_shared_dat_r $0\builder_shared_dat_r[31:0] + update \builder_shared_ack $0\builder_shared_ack[0:0] + update \builder_error $0\builder_error[0:0] + end + attribute \src "ls180.v:580.11-580.68" + process $proc$ls180.v:580$2979 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] 4'0000 + sync always + sync init + update \main_sdram_bankmachine2_cmd_buffer_lookahead_level $1\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] + end + attribute \src "ls180.v:581.5-581.64" + process $proc$ls180.v:581$2980 + assign { } { } + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_replace[0:0] 1'0 + sync always + update \main_sdram_bankmachine2_cmd_buffer_lookahead_replace $0\main_sdram_bankmachine2_cmd_buffer_lookahead_replace[0:0] + sync init + end + attribute \src "ls180.v:582.11-582.70" + process $proc$ls180.v:582$2981 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine2_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] + end + attribute \src "ls180.v:583.11-583.70" + process $proc$ls180.v:583$2982 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine2_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] + end + attribute \src "ls180.v:584.11-584.73" + process $proc$ls180.v:584$2983 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr $1\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] + end + attribute \src "ls180.v:59.12-59.55" + process $proc$ls180.v:59$2770 + assign { } { } + assign $1\main_libresocsim_libresoc_interrupt[15:0] 16'0000000000000000 + sync always + sync init + update \main_libresocsim_libresoc_interrupt $1\main_libresocsim_libresoc_interrupt[15:0] + end + attribute \src "ls180.v:605.5-605.59" + process $proc$ls180.v:605$2984 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_cmd_buffer_source_valid $1\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] + end + attribute \src "ls180.v:607.5-607.59" + process $proc$ls180.v:607$2985 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_cmd_buffer_source_first $1\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] + end + attribute \src "ls180.v:608.5-608.58" + process $proc$ls180.v:608$2986 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_cmd_buffer_source_last $1\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] + end + attribute \src "ls180.v:609.5-609.64" + process $proc$ls180.v:609$2987 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_cmd_buffer_source_payload_we $1\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] + end + attribute \src "ls180.v:610.12-610.74" + process $proc$ls180.v:610$2988 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000 + sync always + sync init + update \main_sdram_bankmachine2_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] + end + attribute \src "ls180.v:611.12-611.47" + process $proc$ls180.v:611$2989 + assign { } { } + assign $1\main_sdram_bankmachine2_row[12:0] 13'0000000000000 + sync always + sync init + update \main_sdram_bankmachine2_row $1\main_sdram_bankmachine2_row[12:0] + end + attribute \src "ls180.v:612.5-612.46" + process $proc$ls180.v:612$2990 + assign { } { } + assign $1\main_sdram_bankmachine2_row_opened[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_row_opened $1\main_sdram_bankmachine2_row_opened[0:0] + end + attribute \src "ls180.v:614.5-614.44" + process $proc$ls180.v:614$2991 + assign { } { } + assign $1\main_sdram_bankmachine2_row_open[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_row_open $1\main_sdram_bankmachine2_row_open[0:0] + end + attribute \src "ls180.v:615.5-615.45" + process $proc$ls180.v:615$2992 + assign { } { } + assign $1\main_sdram_bankmachine2_row_close[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_row_close $1\main_sdram_bankmachine2_row_close[0:0] + end + attribute \src "ls180.v:616.5-616.54" + process $proc$ls180.v:616$2993 + assign { } { } + assign $1\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_row_col_n_addr_sel $1\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] + end + attribute \src "ls180.v:618.32-618.76" + process $proc$ls180.v:618$2994 + assign { } { } + assign $1\main_sdram_bankmachine2_twtpcon_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_twtpcon_ready $1\main_sdram_bankmachine2_twtpcon_ready[0:0] + end + attribute \src "ls180.v:619.11-619.55" + process $proc$ls180.v:619$2995 + assign { } { } + assign $1\main_sdram_bankmachine2_twtpcon_count[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine2_twtpcon_count $1\main_sdram_bankmachine2_twtpcon_count[2:0] + end + attribute \src "ls180.v:621.32-621.75" + process $proc$ls180.v:621$2996 + assign { } { } + assign $0\main_sdram_bankmachine2_trccon_ready[0:0] 1'1 + sync always + update \main_sdram_bankmachine2_trccon_ready $0\main_sdram_bankmachine2_trccon_ready[0:0] + sync init + end + attribute \src "ls180.v:6216.1-6221.4" + process $proc$ls180.v:6216$1939 + assign { } { } + assign $0\main_spi_master_start1[0:0] 1'0 + attribute \src "ls180.v:6218.2-6220.5" + switch \main_spi_master_control_re + attribute \src "ls180.v:6218.6-6218.32" + case 1'1 + assign $0\main_spi_master_start1[0:0] \main_spi_master_control_storage [0] + case + end + sync always + update \main_spi_master_start1 $0\main_spi_master_start1[0:0] + end + attribute \src "ls180.v:623.32-623.76" + process $proc$ls180.v:623$2997 + assign { } { } + assign $0\main_sdram_bankmachine2_trascon_ready[0:0] 1'1 + sync always + update \main_sdram_bankmachine2_trascon_ready $0\main_sdram_bankmachine2_trascon_ready[0:0] + sync init + end + attribute \src "ls180.v:6262.1-6267.4" + process $proc$ls180.v:6262$2004 + assign { } { } + assign $0\libresocsim_start1[0:0] 1'0 + attribute \src "ls180.v:6264.2-6266.5" + switch \libresocsim_control_re + attribute \src "ls180.v:6264.6-6264.28" + case 1'1 + assign $0\libresocsim_start1[0:0] \libresocsim_control_storage [0] + case + end + sync always + update \libresocsim_start1 $0\libresocsim_start1[0:0] + end + attribute \src "ls180.v:629.5-629.51" + process $proc$ls180.v:629$2998 + assign { } { } + assign $1\main_sdram_bankmachine3_req_wdata_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_req_wdata_ready $1\main_sdram_bankmachine3_req_wdata_ready[0:0] + end + attribute \src "ls180.v:630.5-630.51" + process $proc$ls180.v:630$2999 + assign { } { } + assign $1\main_sdram_bankmachine3_req_rdata_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_req_rdata_valid $1\main_sdram_bankmachine3_req_rdata_valid[0:0] + end + attribute \src "ls180.v:632.5-632.47" + process $proc$ls180.v:632$3000 + assign { } { } + assign $1\main_sdram_bankmachine3_refresh_gnt[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_refresh_gnt $1\main_sdram_bankmachine3_refresh_gnt[0:0] + end + attribute \src "ls180.v:633.5-633.45" + process $proc$ls180.v:633$3001 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_valid $1\main_sdram_bankmachine3_cmd_valid[0:0] + end + attribute \src "ls180.v:634.5-634.45" + process $proc$ls180.v:634$3002 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_ready $1\main_sdram_bankmachine3_cmd_ready[0:0] + end + attribute \src "ls180.v:635.12-635.57" + process $proc$ls180.v:635$3003 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_payload_a[12:0] 13'0000000000000 + sync always + sync init + update \main_sdram_bankmachine3_cmd_payload_a $1\main_sdram_bankmachine3_cmd_payload_a[12:0] + end + attribute \src "ls180.v:637.5-637.51" + process $proc$ls180.v:637$3004 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_payload_cas[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_payload_cas $1\main_sdram_bankmachine3_cmd_payload_cas[0:0] + end + attribute \src "ls180.v:638.5-638.51" + process $proc$ls180.v:638$3005 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_payload_ras[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_payload_ras $1\main_sdram_bankmachine3_cmd_payload_ras[0:0] + end + attribute \src "ls180.v:639.5-639.50" + process $proc$ls180.v:639$3006 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_payload_we[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_payload_we $1\main_sdram_bankmachine3_cmd_payload_we[0:0] + end + attribute \src "ls180.v:640.5-640.54" + process $proc$ls180.v:640$3007 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_payload_is_cmd $1\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] + end + attribute \src "ls180.v:641.5-641.55" + process $proc$ls180.v:641$3008 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_payload_is_read[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_payload_is_read $1\main_sdram_bankmachine3_cmd_payload_is_read[0:0] + end + attribute \src "ls180.v:642.5-642.56" + process $proc$ls180.v:642$3009 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_payload_is_write[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_payload_is_write $1\main_sdram_bankmachine3_cmd_payload_is_write[0:0] + end + attribute \src "ls180.v:643.5-643.50" + process $proc$ls180.v:643$3010 + assign { } { } + assign $1\main_sdram_bankmachine3_auto_precharge[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_auto_precharge $1\main_sdram_bankmachine3_auto_precharge[0:0] + end + attribute \src "ls180.v:6448.1-6464.4" + process $proc$ls180.v:6448$2224 + assign { } { } + assign $0\builder_comb_rhs_array_muxed0[0:0] 1'0 + attribute \src "ls180.v:6450.2-6463.9" + switch \main_sdram_choose_cmd_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_rhs_array_muxed0[0:0] \main_sdram_choose_cmd_valids [0] + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_rhs_array_muxed0[0:0] \main_sdram_choose_cmd_valids [1] + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_rhs_array_muxed0[0:0] \main_sdram_choose_cmd_valids [2] + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed0[0:0] \main_sdram_choose_cmd_valids [3] + end + sync always + update \builder_comb_rhs_array_muxed0 $0\builder_comb_rhs_array_muxed0[0:0] + end + attribute \src "ls180.v:646.5-646.67" + process $proc$ls180.v:646$3011 + assign { } { } + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first[0:0] 1'0 + sync always + update \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first[0:0] + sync init + end + attribute \src "ls180.v:6465.1-6481.4" + process $proc$ls180.v:6465$2225 + assign { } { } + assign $0\builder_comb_rhs_array_muxed1[12:0] 13'0000000000000 + attribute \src "ls180.v:6467.2-6480.9" + switch \main_sdram_choose_cmd_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_rhs_array_muxed1[12:0] \main_sdram_bankmachine0_cmd_payload_a + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_rhs_array_muxed1[12:0] \main_sdram_bankmachine1_cmd_payload_a + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_rhs_array_muxed1[12:0] \main_sdram_bankmachine2_cmd_payload_a + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed1[12:0] \main_sdram_bankmachine3_cmd_payload_a + end + sync always + update \builder_comb_rhs_array_muxed1 $0\builder_comb_rhs_array_muxed1[12:0] + end + attribute \src "ls180.v:647.5-647.66" + process $proc$ls180.v:647$3012 + assign { } { } + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last[0:0] 1'0 + sync always + update \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last[0:0] + sync init + end + attribute \src "ls180.v:6482.1-6498.4" + process $proc$ls180.v:6482$2226 + assign { } { } + assign $0\builder_comb_rhs_array_muxed2[1:0] 2'00 + attribute \src "ls180.v:6484.2-6497.9" + switch \main_sdram_choose_cmd_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_rhs_array_muxed2[1:0] \main_sdram_bankmachine0_cmd_payload_ba + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_rhs_array_muxed2[1:0] \main_sdram_bankmachine1_cmd_payload_ba + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_rhs_array_muxed2[1:0] \main_sdram_bankmachine2_cmd_payload_ba + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed2[1:0] \main_sdram_bankmachine3_cmd_payload_ba + end + sync always + update \builder_comb_rhs_array_muxed2 $0\builder_comb_rhs_array_muxed2[1:0] + end + attribute \src "ls180.v:6499.1-6515.4" + process $proc$ls180.v:6499$2227 + assign { } { } + assign $0\builder_comb_rhs_array_muxed3[0:0] 1'0 + attribute \src "ls180.v:6501.2-6514.9" + switch \main_sdram_choose_cmd_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_rhs_array_muxed3[0:0] \main_sdram_bankmachine0_cmd_payload_is_read + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_rhs_array_muxed3[0:0] \main_sdram_bankmachine1_cmd_payload_is_read + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_rhs_array_muxed3[0:0] \main_sdram_bankmachine2_cmd_payload_is_read + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed3[0:0] \main_sdram_bankmachine3_cmd_payload_is_read + end + sync always + update \builder_comb_rhs_array_muxed3 $0\builder_comb_rhs_array_muxed3[0:0] + end + attribute \src "ls180.v:6516.1-6532.4" + process $proc$ls180.v:6516$2228 + assign { } { } + assign $0\builder_comb_rhs_array_muxed4[0:0] 1'0 + attribute \src "ls180.v:6518.2-6531.9" + switch \main_sdram_choose_cmd_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_rhs_array_muxed4[0:0] \main_sdram_bankmachine0_cmd_payload_is_write + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_rhs_array_muxed4[0:0] \main_sdram_bankmachine1_cmd_payload_is_write + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_rhs_array_muxed4[0:0] \main_sdram_bankmachine2_cmd_payload_is_write + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed4[0:0] \main_sdram_bankmachine3_cmd_payload_is_write + end + sync always + update \builder_comb_rhs_array_muxed4 $0\builder_comb_rhs_array_muxed4[0:0] + end + attribute \src "ls180.v:6533.1-6549.4" + process $proc$ls180.v:6533$2229 + assign { } { } + assign $0\builder_comb_rhs_array_muxed5[0:0] 1'0 + attribute \src "ls180.v:6535.2-6548.9" + switch \main_sdram_choose_cmd_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_rhs_array_muxed5[0:0] \main_sdram_bankmachine0_cmd_payload_is_cmd + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_rhs_array_muxed5[0:0] \main_sdram_bankmachine1_cmd_payload_is_cmd + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_rhs_array_muxed5[0:0] \main_sdram_bankmachine2_cmd_payload_is_cmd + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed5[0:0] \main_sdram_bankmachine3_cmd_payload_is_cmd + end + sync always + update \builder_comb_rhs_array_muxed5 $0\builder_comb_rhs_array_muxed5[0:0] + end + attribute \src "ls180.v:6550.1-6566.4" + process $proc$ls180.v:6550$2230 + assign { } { } + assign $0\builder_comb_t_array_muxed0[0:0] 1'0 + attribute \src "ls180.v:6552.2-6565.9" + switch \main_sdram_choose_cmd_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_t_array_muxed0[0:0] \main_sdram_bankmachine0_cmd_payload_cas + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_t_array_muxed0[0:0] \main_sdram_bankmachine1_cmd_payload_cas + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_t_array_muxed0[0:0] \main_sdram_bankmachine2_cmd_payload_cas + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_t_array_muxed0[0:0] \main_sdram_bankmachine3_cmd_payload_cas + end + sync always + update \builder_comb_t_array_muxed0 $0\builder_comb_t_array_muxed0[0:0] + end + attribute \src "ls180.v:6567.1-6583.4" + process $proc$ls180.v:6567$2231 + assign { } { } + assign $0\builder_comb_t_array_muxed1[0:0] 1'0 + attribute \src "ls180.v:6569.2-6582.9" + switch \main_sdram_choose_cmd_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_t_array_muxed1[0:0] \main_sdram_bankmachine0_cmd_payload_ras + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_t_array_muxed1[0:0] \main_sdram_bankmachine1_cmd_payload_ras + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_t_array_muxed1[0:0] \main_sdram_bankmachine2_cmd_payload_ras + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_t_array_muxed1[0:0] \main_sdram_bankmachine3_cmd_payload_ras + end + sync always + update \builder_comb_t_array_muxed1 $0\builder_comb_t_array_muxed1[0:0] + end + attribute \src "ls180.v:6584.1-6600.4" + process $proc$ls180.v:6584$2232 + assign { } { } + assign $0\builder_comb_t_array_muxed2[0:0] 1'0 + attribute \src "ls180.v:6586.2-6599.9" + switch \main_sdram_choose_cmd_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_t_array_muxed2[0:0] \main_sdram_bankmachine0_cmd_payload_we + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_t_array_muxed2[0:0] \main_sdram_bankmachine1_cmd_payload_we + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_t_array_muxed2[0:0] \main_sdram_bankmachine2_cmd_payload_we + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_t_array_muxed2[0:0] \main_sdram_bankmachine3_cmd_payload_we + end + sync always + update \builder_comb_t_array_muxed2 $0\builder_comb_t_array_muxed2[0:0] + end + attribute \src "ls180.v:66.5-66.46" + process $proc$ls180.v:66$2771 + assign { } { } + assign $1\main_libresocsim_libresoc_dbus_ack[0:0] 1'0 + sync always + sync init + update \main_libresocsim_libresoc_dbus_ack $1\main_libresocsim_libresoc_dbus_ack[0:0] + end + attribute \src "ls180.v:6601.1-6617.4" + process $proc$ls180.v:6601$2233 + assign { } { } + assign $0\builder_comb_rhs_array_muxed6[0:0] 1'0 + attribute \src "ls180.v:6603.2-6616.9" + switch \main_sdram_choose_req_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_rhs_array_muxed6[0:0] \main_sdram_choose_req_valids [0] + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_rhs_array_muxed6[0:0] \main_sdram_choose_req_valids [1] + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_rhs_array_muxed6[0:0] \main_sdram_choose_req_valids [2] + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed6[0:0] \main_sdram_choose_req_valids [3] + end + sync always + update \builder_comb_rhs_array_muxed6 $0\builder_comb_rhs_array_muxed6[0:0] + end + attribute \src "ls180.v:6618.1-6634.4" + process $proc$ls180.v:6618$2234 + assign { } { } + assign $0\builder_comb_rhs_array_muxed7[12:0] 13'0000000000000 + attribute \src "ls180.v:6620.2-6633.9" + switch \main_sdram_choose_req_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_rhs_array_muxed7[12:0] \main_sdram_bankmachine0_cmd_payload_a + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_rhs_array_muxed7[12:0] \main_sdram_bankmachine1_cmd_payload_a + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_rhs_array_muxed7[12:0] \main_sdram_bankmachine2_cmd_payload_a + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed7[12:0] \main_sdram_bankmachine3_cmd_payload_a + end + sync always + update \builder_comb_rhs_array_muxed7 $0\builder_comb_rhs_array_muxed7[12:0] + end + attribute \src "ls180.v:662.11-662.68" + process $proc$ls180.v:662$3013 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] 4'0000 + sync always + sync init + update \main_sdram_bankmachine3_cmd_buffer_lookahead_level $1\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] + end + attribute \src "ls180.v:663.5-663.64" + process $proc$ls180.v:663$3014 + assign { } { } + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_replace[0:0] 1'0 + sync always + update \main_sdram_bankmachine3_cmd_buffer_lookahead_replace $0\main_sdram_bankmachine3_cmd_buffer_lookahead_replace[0:0] + sync init + end + attribute \src "ls180.v:6635.1-6651.4" + process $proc$ls180.v:6635$2235 + assign { } { } + assign $0\builder_comb_rhs_array_muxed8[1:0] 2'00 + attribute \src "ls180.v:6637.2-6650.9" + switch \main_sdram_choose_req_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_rhs_array_muxed8[1:0] \main_sdram_bankmachine0_cmd_payload_ba + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_rhs_array_muxed8[1:0] \main_sdram_bankmachine1_cmd_payload_ba + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_rhs_array_muxed8[1:0] \main_sdram_bankmachine2_cmd_payload_ba + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed8[1:0] \main_sdram_bankmachine3_cmd_payload_ba + end + sync always + update \builder_comb_rhs_array_muxed8 $0\builder_comb_rhs_array_muxed8[1:0] + end + attribute \src "ls180.v:664.11-664.70" + process $proc$ls180.v:664$3015 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine3_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] + end + attribute \src "ls180.v:665.11-665.70" + process $proc$ls180.v:665$3016 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine3_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] + end + attribute \src "ls180.v:6652.1-6668.4" + process $proc$ls180.v:6652$2236 + assign { } { } + assign $0\builder_comb_rhs_array_muxed9[0:0] 1'0 + attribute \src "ls180.v:6654.2-6667.9" + switch \main_sdram_choose_req_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_rhs_array_muxed9[0:0] \main_sdram_bankmachine0_cmd_payload_is_read + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_rhs_array_muxed9[0:0] \main_sdram_bankmachine1_cmd_payload_is_read + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_rhs_array_muxed9[0:0] \main_sdram_bankmachine2_cmd_payload_is_read + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed9[0:0] \main_sdram_bankmachine3_cmd_payload_is_read + end + sync always + update \builder_comb_rhs_array_muxed9 $0\builder_comb_rhs_array_muxed9[0:0] + end + attribute \src "ls180.v:666.11-666.73" + process $proc$ls180.v:666$3017 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr $1\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] + end + attribute \src "ls180.v:6669.1-6685.4" + process $proc$ls180.v:6669$2237 + assign { } { } + assign $0\builder_comb_rhs_array_muxed10[0:0] 1'0 + attribute \src "ls180.v:6671.2-6684.9" + switch \main_sdram_choose_req_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_rhs_array_muxed10[0:0] \main_sdram_bankmachine0_cmd_payload_is_write + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_rhs_array_muxed10[0:0] \main_sdram_bankmachine1_cmd_payload_is_write + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_rhs_array_muxed10[0:0] \main_sdram_bankmachine2_cmd_payload_is_write + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed10[0:0] \main_sdram_bankmachine3_cmd_payload_is_write + end + sync always + update \builder_comb_rhs_array_muxed10 $0\builder_comb_rhs_array_muxed10[0:0] + end + attribute \src "ls180.v:6686.1-6702.4" + process $proc$ls180.v:6686$2238 + assign { } { } + assign $0\builder_comb_rhs_array_muxed11[0:0] 1'0 + attribute \src "ls180.v:6688.2-6701.9" + switch \main_sdram_choose_req_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_rhs_array_muxed11[0:0] \main_sdram_bankmachine0_cmd_payload_is_cmd + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_rhs_array_muxed11[0:0] \main_sdram_bankmachine1_cmd_payload_is_cmd + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_rhs_array_muxed11[0:0] \main_sdram_bankmachine2_cmd_payload_is_cmd + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed11[0:0] \main_sdram_bankmachine3_cmd_payload_is_cmd + end + sync always + update \builder_comb_rhs_array_muxed11 $0\builder_comb_rhs_array_muxed11[0:0] + end + attribute \src "ls180.v:6703.1-6719.4" + process $proc$ls180.v:6703$2239 + assign { } { } + assign $0\builder_comb_t_array_muxed3[0:0] 1'0 + attribute \src "ls180.v:6705.2-6718.9" + switch \main_sdram_choose_req_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_t_array_muxed3[0:0] \main_sdram_bankmachine0_cmd_payload_cas + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_t_array_muxed3[0:0] \main_sdram_bankmachine1_cmd_payload_cas + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_t_array_muxed3[0:0] \main_sdram_bankmachine2_cmd_payload_cas + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_t_array_muxed3[0:0] \main_sdram_bankmachine3_cmd_payload_cas + end + sync always + update \builder_comb_t_array_muxed3 $0\builder_comb_t_array_muxed3[0:0] + end + attribute \src "ls180.v:6720.1-6736.4" + process $proc$ls180.v:6720$2240 + assign { } { } + assign $0\builder_comb_t_array_muxed4[0:0] 1'0 + attribute \src "ls180.v:6722.2-6735.9" + switch \main_sdram_choose_req_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_t_array_muxed4[0:0] \main_sdram_bankmachine0_cmd_payload_ras + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_t_array_muxed4[0:0] \main_sdram_bankmachine1_cmd_payload_ras + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_t_array_muxed4[0:0] \main_sdram_bankmachine2_cmd_payload_ras + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_t_array_muxed4[0:0] \main_sdram_bankmachine3_cmd_payload_ras + end + sync always + update \builder_comb_t_array_muxed4 $0\builder_comb_t_array_muxed4[0:0] + end + attribute \src "ls180.v:6737.1-6753.4" + process $proc$ls180.v:6737$2241 + assign { } { } + assign $0\builder_comb_t_array_muxed5[0:0] 1'0 + attribute \src "ls180.v:6739.2-6752.9" + switch \main_sdram_choose_req_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_t_array_muxed5[0:0] \main_sdram_bankmachine0_cmd_payload_we + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_t_array_muxed5[0:0] \main_sdram_bankmachine1_cmd_payload_we + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_t_array_muxed5[0:0] \main_sdram_bankmachine2_cmd_payload_we + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_t_array_muxed5[0:0] \main_sdram_bankmachine3_cmd_payload_we + end + sync always + update \builder_comb_t_array_muxed5 $0\builder_comb_t_array_muxed5[0:0] + end + attribute \src "ls180.v:6754.1-6761.4" + process $proc$ls180.v:6754$2242 + assign { } { } + assign $0\builder_comb_rhs_array_muxed12[21:0] 22'0000000000000000000000 + attribute \src "ls180.v:6756.2-6760.9" + switch \builder_roundrobin0_grant + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed12[21:0] { \main_port_cmd_payload_addr [23:11] \main_port_cmd_payload_addr [8:0] } + end + sync always + update \builder_comb_rhs_array_muxed12 $0\builder_comb_rhs_array_muxed12[21:0] + end + attribute \src "ls180.v:6762.1-6769.4" + process $proc$ls180.v:6762$2243 + assign { } { } + assign $0\builder_comb_rhs_array_muxed13[0:0] 1'0 + attribute \src "ls180.v:6764.2-6768.9" + switch \builder_roundrobin0_grant + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed13[0:0] \main_port_cmd_payload_we + end + sync always + update \builder_comb_rhs_array_muxed13 $0\builder_comb_rhs_array_muxed13[0:0] + end + attribute \src "ls180.v:6770.1-6777.4" + process $proc$ls180.v:6770$2244 + assign { } { } + assign $0\builder_comb_rhs_array_muxed14[0:0] 1'0 + attribute \src "ls180.v:6772.2-6776.9" + switch \builder_roundrobin0_grant + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed14[0:0] $and$ls180.v:6774$2257_Y + end + sync always + update \builder_comb_rhs_array_muxed14 $0\builder_comb_rhs_array_muxed14[0:0] + end + attribute \src "ls180.v:6778.1-6785.4" + process $proc$ls180.v:6778$2258 + assign { } { } + assign $0\builder_comb_rhs_array_muxed15[21:0] 22'0000000000000000000000 + attribute \src "ls180.v:6780.2-6784.9" + switch \builder_roundrobin1_grant + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed15[21:0] { \main_port_cmd_payload_addr [23:11] \main_port_cmd_payload_addr [8:0] } + end + sync always + update \builder_comb_rhs_array_muxed15 $0\builder_comb_rhs_array_muxed15[21:0] + end + attribute \src "ls180.v:6786.1-6793.4" + process $proc$ls180.v:6786$2259 + assign { } { } + assign $0\builder_comb_rhs_array_muxed16[0:0] 1'0 + attribute \src "ls180.v:6788.2-6792.9" + switch \builder_roundrobin1_grant + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed16[0:0] \main_port_cmd_payload_we + end + sync always + update \builder_comb_rhs_array_muxed16 $0\builder_comb_rhs_array_muxed16[0:0] + end + attribute \src "ls180.v:6794.1-6801.4" + process $proc$ls180.v:6794$2260 + assign { } { } + assign $0\builder_comb_rhs_array_muxed17[0:0] 1'0 + attribute \src "ls180.v:6796.2-6800.9" + switch \builder_roundrobin1_grant + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed17[0:0] $and$ls180.v:6798$2273_Y + end + sync always + update \builder_comb_rhs_array_muxed17 $0\builder_comb_rhs_array_muxed17[0:0] + end + attribute \src "ls180.v:6802.1-6809.4" + process $proc$ls180.v:6802$2274 + assign { } { } + assign $0\builder_comb_rhs_array_muxed18[21:0] 22'0000000000000000000000 + attribute \src "ls180.v:6804.2-6808.9" + switch \builder_roundrobin2_grant + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed18[21:0] { \main_port_cmd_payload_addr [23:11] \main_port_cmd_payload_addr [8:0] } + end + sync always + update \builder_comb_rhs_array_muxed18 $0\builder_comb_rhs_array_muxed18[21:0] + end + attribute \src "ls180.v:6810.1-6817.4" + process $proc$ls180.v:6810$2275 + assign { } { } + assign $0\builder_comb_rhs_array_muxed19[0:0] 1'0 + attribute \src "ls180.v:6812.2-6816.9" + switch \builder_roundrobin2_grant + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed19[0:0] \main_port_cmd_payload_we + end + sync always + update \builder_comb_rhs_array_muxed19 $0\builder_comb_rhs_array_muxed19[0:0] + end + attribute \src "ls180.v:6818.1-6825.4" + process $proc$ls180.v:6818$2276 + assign { } { } + assign $0\builder_comb_rhs_array_muxed20[0:0] 1'0 + attribute \src "ls180.v:6820.2-6824.9" + switch \builder_roundrobin2_grant + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed20[0:0] $and$ls180.v:6822$2289_Y + end + sync always + update \builder_comb_rhs_array_muxed20 $0\builder_comb_rhs_array_muxed20[0:0] + end + attribute \src "ls180.v:6826.1-6833.4" + process $proc$ls180.v:6826$2290 + assign { } { } + assign $0\builder_comb_rhs_array_muxed21[21:0] 22'0000000000000000000000 + attribute \src "ls180.v:6828.2-6832.9" + switch \builder_roundrobin3_grant + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed21[21:0] { \main_port_cmd_payload_addr [23:11] \main_port_cmd_payload_addr [8:0] } + end + sync always + update \builder_comb_rhs_array_muxed21 $0\builder_comb_rhs_array_muxed21[21:0] + end + attribute \src "ls180.v:6834.1-6841.4" + process $proc$ls180.v:6834$2291 + assign { } { } + assign $0\builder_comb_rhs_array_muxed22[0:0] 1'0 + attribute \src "ls180.v:6836.2-6840.9" + switch \builder_roundrobin3_grant + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed22[0:0] \main_port_cmd_payload_we + end + sync always + update \builder_comb_rhs_array_muxed22 $0\builder_comb_rhs_array_muxed22[0:0] + end + attribute \src "ls180.v:6842.1-6849.4" + process $proc$ls180.v:6842$2292 + assign { } { } + assign $0\builder_comb_rhs_array_muxed23[0:0] 1'0 + attribute \src "ls180.v:6844.2-6848.9" + switch \builder_roundrobin3_grant + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed23[0:0] $and$ls180.v:6846$2305_Y + end + sync always + update \builder_comb_rhs_array_muxed23 $0\builder_comb_rhs_array_muxed23[0:0] + end + attribute \src "ls180.v:6850.1-6869.4" + process $proc$ls180.v:6850$2306 + assign { } { } + assign $0\builder_comb_rhs_array_muxed24[31:0] 0 + attribute \src "ls180.v:6852.2-6868.9" + switch \builder_grant + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\builder_comb_rhs_array_muxed24[31:0] { 2'00 \main_libresocsim_interface0_converted_interface_adr } + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\builder_comb_rhs_array_muxed24[31:0] { 2'00 \main_libresocsim_interface1_converted_interface_adr } + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\builder_comb_rhs_array_muxed24[31:0] { 2'00 \main_libresocsim_interface2_converted_interface_adr } + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\builder_comb_rhs_array_muxed24[31:0] \main_interface0_bus_adr + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed24[31:0] \main_interface1_bus_adr + end + sync always + update \builder_comb_rhs_array_muxed24 $0\builder_comb_rhs_array_muxed24[31:0] + end + attribute \src "ls180.v:687.5-687.59" + process $proc$ls180.v:687$3018 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_buffer_source_valid $1\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] + end + attribute \src "ls180.v:6870.1-6889.4" + process $proc$ls180.v:6870$2307 + assign { } { } + assign $0\builder_comb_rhs_array_muxed25[31:0] 0 + attribute \src "ls180.v:6872.2-6888.9" + switch \builder_grant + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\builder_comb_rhs_array_muxed25[31:0] \main_libresocsim_interface0_converted_interface_dat_w + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\builder_comb_rhs_array_muxed25[31:0] \main_libresocsim_interface1_converted_interface_dat_w + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\builder_comb_rhs_array_muxed25[31:0] \main_libresocsim_interface2_converted_interface_dat_w + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\builder_comb_rhs_array_muxed25[31:0] \main_interface0_bus_dat_w + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed25[31:0] \main_interface1_bus_dat_w + end + sync always + update \builder_comb_rhs_array_muxed25 $0\builder_comb_rhs_array_muxed25[31:0] + end + attribute \src "ls180.v:689.5-689.59" + process $proc$ls180.v:689$3019 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_buffer_source_first $1\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] + end + attribute \src "ls180.v:6890.1-6909.4" + process $proc$ls180.v:6890$2308 + assign { } { } + assign $0\builder_comb_rhs_array_muxed26[3:0] 4'0000 + attribute \src "ls180.v:6892.2-6908.9" + switch \builder_grant + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\builder_comb_rhs_array_muxed26[3:0] \main_libresocsim_interface0_converted_interface_sel + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\builder_comb_rhs_array_muxed26[3:0] \main_libresocsim_interface1_converted_interface_sel + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\builder_comb_rhs_array_muxed26[3:0] \main_libresocsim_interface2_converted_interface_sel + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\builder_comb_rhs_array_muxed26[3:0] \main_interface0_bus_sel + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed26[3:0] \main_interface1_bus_sel + end + sync always + update \builder_comb_rhs_array_muxed26 $0\builder_comb_rhs_array_muxed26[3:0] + end + attribute \src "ls180.v:690.5-690.58" + process $proc$ls180.v:690$3020 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_buffer_source_last $1\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] + end + attribute \src "ls180.v:691.5-691.64" + process $proc$ls180.v:691$3021 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_buffer_source_payload_we $1\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] + end + attribute \src "ls180.v:6910.1-6929.4" + process $proc$ls180.v:6910$2309 + assign { } { } + assign $0\builder_comb_rhs_array_muxed27[0:0] 1'0 + attribute \src "ls180.v:6912.2-6928.9" + switch \builder_grant + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\builder_comb_rhs_array_muxed27[0:0] \main_libresocsim_interface0_converted_interface_cyc + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\builder_comb_rhs_array_muxed27[0:0] \main_libresocsim_interface1_converted_interface_cyc + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\builder_comb_rhs_array_muxed27[0:0] \main_libresocsim_interface2_converted_interface_cyc + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\builder_comb_rhs_array_muxed27[0:0] \main_interface0_bus_cyc + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed27[0:0] \main_interface1_bus_cyc + end + sync always + update \builder_comb_rhs_array_muxed27 $0\builder_comb_rhs_array_muxed27[0:0] + end + attribute \src "ls180.v:692.12-692.74" + process $proc$ls180.v:692$3022 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000 + sync always + sync init + update \main_sdram_bankmachine3_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] + end + attribute \src "ls180.v:693.12-693.47" + process $proc$ls180.v:693$3023 + assign { } { } + assign $1\main_sdram_bankmachine3_row[12:0] 13'0000000000000 + sync always + sync init + update \main_sdram_bankmachine3_row $1\main_sdram_bankmachine3_row[12:0] + end + attribute \src "ls180.v:6930.1-6949.4" + process $proc$ls180.v:6930$2310 + assign { } { } + assign $0\builder_comb_rhs_array_muxed28[0:0] 1'0 + attribute \src "ls180.v:6932.2-6948.9" + switch \builder_grant + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\builder_comb_rhs_array_muxed28[0:0] \main_libresocsim_interface0_converted_interface_stb + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\builder_comb_rhs_array_muxed28[0:0] \main_libresocsim_interface1_converted_interface_stb + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\builder_comb_rhs_array_muxed28[0:0] \main_libresocsim_interface2_converted_interface_stb + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\builder_comb_rhs_array_muxed28[0:0] \main_interface0_bus_stb + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed28[0:0] \main_interface1_bus_stb + end + sync always + update \builder_comb_rhs_array_muxed28 $0\builder_comb_rhs_array_muxed28[0:0] + end + attribute \src "ls180.v:694.5-694.46" + process $proc$ls180.v:694$3024 + assign { } { } + assign $1\main_sdram_bankmachine3_row_opened[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_row_opened $1\main_sdram_bankmachine3_row_opened[0:0] + end + attribute \src "ls180.v:6950.1-6969.4" + process $proc$ls180.v:6950$2311 + assign { } { } + assign $0\builder_comb_rhs_array_muxed29[0:0] 1'0 + attribute \src "ls180.v:6952.2-6968.9" + switch \builder_grant + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\builder_comb_rhs_array_muxed29[0:0] \main_libresocsim_interface0_converted_interface_we + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\builder_comb_rhs_array_muxed29[0:0] \main_libresocsim_interface1_converted_interface_we + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\builder_comb_rhs_array_muxed29[0:0] \main_libresocsim_interface2_converted_interface_we + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\builder_comb_rhs_array_muxed29[0:0] \main_interface0_bus_we + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed29[0:0] \main_interface1_bus_we + end + sync always + update \builder_comb_rhs_array_muxed29 $0\builder_comb_rhs_array_muxed29[0:0] + end + attribute \src "ls180.v:696.5-696.44" + process $proc$ls180.v:696$3025 + assign { } { } + assign $1\main_sdram_bankmachine3_row_open[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_row_open $1\main_sdram_bankmachine3_row_open[0:0] + end + attribute \src "ls180.v:697.5-697.45" + process $proc$ls180.v:697$3026 + assign { } { } + assign $1\main_sdram_bankmachine3_row_close[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_row_close $1\main_sdram_bankmachine3_row_close[0:0] + end + attribute \src "ls180.v:6970.1-6989.4" + process $proc$ls180.v:6970$2312 + assign { } { } + assign $0\builder_comb_rhs_array_muxed30[2:0] 3'000 + attribute \src "ls180.v:6972.2-6988.9" + switch \builder_grant + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\builder_comb_rhs_array_muxed30[2:0] \main_libresocsim_interface0_converted_interface_cti + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\builder_comb_rhs_array_muxed30[2:0] \main_libresocsim_interface1_converted_interface_cti + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\builder_comb_rhs_array_muxed30[2:0] \main_libresocsim_interface2_converted_interface_cti + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\builder_comb_rhs_array_muxed30[2:0] \main_interface0_bus_cti + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed30[2:0] \main_interface1_bus_cti + end + sync always + update \builder_comb_rhs_array_muxed30 $0\builder_comb_rhs_array_muxed30[2:0] + end + attribute \src "ls180.v:698.5-698.54" + process $proc$ls180.v:698$3027 + assign { } { } + assign $1\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_row_col_n_addr_sel $1\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] + end + attribute \src "ls180.v:6990.1-7009.4" + process $proc$ls180.v:6990$2313 + assign { } { } + assign $0\builder_comb_rhs_array_muxed31[1:0] 2'00 + attribute \src "ls180.v:6992.2-7008.9" + switch \builder_grant + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\builder_comb_rhs_array_muxed31[1:0] \main_libresocsim_interface0_converted_interface_bte + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\builder_comb_rhs_array_muxed31[1:0] \main_libresocsim_interface1_converted_interface_bte + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\builder_comb_rhs_array_muxed31[1:0] \main_libresocsim_interface2_converted_interface_bte + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\builder_comb_rhs_array_muxed31[1:0] \main_interface0_bus_bte + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed31[1:0] \main_interface1_bus_bte + end + sync always + update \builder_comb_rhs_array_muxed31 $0\builder_comb_rhs_array_muxed31[1:0] + end + attribute \src "ls180.v:70.5-70.46" + process $proc$ls180.v:70$2772 + assign { } { } + assign $0\main_libresocsim_libresoc_dbus_err[0:0] 1'0 + sync always + update \main_libresocsim_libresoc_dbus_err $0\main_libresocsim_libresoc_dbus_err[0:0] + sync init + end + attribute \src "ls180.v:700.32-700.76" + process $proc$ls180.v:700$3028 + assign { } { } + assign $1\main_sdram_bankmachine3_twtpcon_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_twtpcon_ready $1\main_sdram_bankmachine3_twtpcon_ready[0:0] + end + attribute \src "ls180.v:701.11-701.55" + process $proc$ls180.v:701$3029 + assign { } { } + assign $1\main_sdram_bankmachine3_twtpcon_count[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine3_twtpcon_count $1\main_sdram_bankmachine3_twtpcon_count[2:0] + end + attribute \src "ls180.v:7010.1-7026.4" + process $proc$ls180.v:7010$2314 + assign { } { } + assign $0\builder_sync_rhs_array_muxed0[1:0] 2'00 + attribute \src "ls180.v:7012.2-7025.9" + switch \main_sdram_steerer_sel + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_sync_rhs_array_muxed0[1:0] \main_sdram_nop_ba + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_sync_rhs_array_muxed0[1:0] \main_sdram_choose_req_cmd_payload_ba + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_sync_rhs_array_muxed0[1:0] \main_sdram_choose_req_cmd_payload_ba + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_sync_rhs_array_muxed0[1:0] \main_sdram_cmd_payload_ba + end + sync always + update \builder_sync_rhs_array_muxed0 $0\builder_sync_rhs_array_muxed0[1:0] + end + attribute \src "ls180.v:7027.1-7043.4" + process $proc$ls180.v:7027$2315 + assign { } { } + assign $0\builder_sync_rhs_array_muxed1[12:0] 13'0000000000000 + attribute \src "ls180.v:7029.2-7042.9" + switch \main_sdram_steerer_sel + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_sync_rhs_array_muxed1[12:0] \main_sdram_nop_a + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_sync_rhs_array_muxed1[12:0] \main_sdram_choose_req_cmd_payload_a + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_sync_rhs_array_muxed1[12:0] \main_sdram_choose_req_cmd_payload_a + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_sync_rhs_array_muxed1[12:0] \main_sdram_cmd_payload_a + end + sync always + update \builder_sync_rhs_array_muxed1 $0\builder_sync_rhs_array_muxed1[12:0] + end + attribute \src "ls180.v:703.32-703.75" + process $proc$ls180.v:703$3030 + assign { } { } + assign $0\main_sdram_bankmachine3_trccon_ready[0:0] 1'1 + sync always + update \main_sdram_bankmachine3_trccon_ready $0\main_sdram_bankmachine3_trccon_ready[0:0] + sync init + end + attribute \src "ls180.v:7044.1-7060.4" + process $proc$ls180.v:7044$2316 + assign { } { } + assign $0\builder_sync_rhs_array_muxed2[0:0] 1'0 + attribute \src "ls180.v:7046.2-7059.9" + switch \main_sdram_steerer_sel + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_sync_rhs_array_muxed2[0:0] 1'0 + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_sync_rhs_array_muxed2[0:0] $and$ls180.v:7051$2318_Y + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_sync_rhs_array_muxed2[0:0] $and$ls180.v:7054$2320_Y + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_sync_rhs_array_muxed2[0:0] $and$ls180.v:7057$2322_Y + end + sync always + update \builder_sync_rhs_array_muxed2 $0\builder_sync_rhs_array_muxed2[0:0] + end + attribute \src "ls180.v:705.32-705.76" + process $proc$ls180.v:705$3031 + assign { } { } + assign $0\main_sdram_bankmachine3_trascon_ready[0:0] 1'1 + sync always + update \main_sdram_bankmachine3_trascon_ready $0\main_sdram_bankmachine3_trascon_ready[0:0] + sync init + end + attribute \src "ls180.v:7061.1-7077.4" + process $proc$ls180.v:7061$2323 + assign { } { } + assign $0\builder_sync_rhs_array_muxed3[0:0] 1'0 + attribute \src "ls180.v:7063.2-7076.9" + switch \main_sdram_steerer_sel + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_sync_rhs_array_muxed3[0:0] 1'0 + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_sync_rhs_array_muxed3[0:0] $and$ls180.v:7068$2325_Y + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_sync_rhs_array_muxed3[0:0] $and$ls180.v:7071$2327_Y + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_sync_rhs_array_muxed3[0:0] $and$ls180.v:7074$2329_Y + end + sync always + update \builder_sync_rhs_array_muxed3 $0\builder_sync_rhs_array_muxed3[0:0] + end + attribute \src "ls180.v:7078.1-7094.4" + process $proc$ls180.v:7078$2330 + assign { } { } + assign $0\builder_sync_rhs_array_muxed4[0:0] 1'0 + attribute \src "ls180.v:7080.2-7093.9" + switch \main_sdram_steerer_sel + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_sync_rhs_array_muxed4[0:0] 1'0 + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_sync_rhs_array_muxed4[0:0] $and$ls180.v:7085$2332_Y + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_sync_rhs_array_muxed4[0:0] $and$ls180.v:7088$2334_Y + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_sync_rhs_array_muxed4[0:0] $and$ls180.v:7091$2336_Y + end + sync always + update \builder_sync_rhs_array_muxed4 $0\builder_sync_rhs_array_muxed4[0:0] + end + attribute \src "ls180.v:708.5-708.44" + process $proc$ls180.v:708$3032 + assign { } { } + assign $0\main_sdram_choose_cmd_want_reads[0:0] 1'0 + sync always + update \main_sdram_choose_cmd_want_reads $0\main_sdram_choose_cmd_want_reads[0:0] + sync init + end + attribute \src "ls180.v:709.5-709.45" + process $proc$ls180.v:709$3033 + assign { } { } + assign $0\main_sdram_choose_cmd_want_writes[0:0] 1'0 + sync always + update \main_sdram_choose_cmd_want_writes $0\main_sdram_choose_cmd_want_writes[0:0] + sync init + end + attribute \src "ls180.v:7095.1-7111.4" + process $proc$ls180.v:7095$2337 + assign { } { } + assign $0\builder_sync_rhs_array_muxed5[0:0] 1'0 + attribute \src "ls180.v:7097.2-7110.9" + switch \main_sdram_steerer_sel + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_sync_rhs_array_muxed5[0:0] 1'0 + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_sync_rhs_array_muxed5[0:0] $and$ls180.v:7102$2339_Y + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_sync_rhs_array_muxed5[0:0] $and$ls180.v:7105$2341_Y + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_sync_rhs_array_muxed5[0:0] $and$ls180.v:7108$2343_Y + end + sync always + update \builder_sync_rhs_array_muxed5 $0\builder_sync_rhs_array_muxed5[0:0] + end + attribute \src "ls180.v:710.5-710.43" + process $proc$ls180.v:710$3034 + assign { } { } + assign $0\main_sdram_choose_cmd_want_cmds[0:0] 1'0 + sync always + update \main_sdram_choose_cmd_want_cmds $0\main_sdram_choose_cmd_want_cmds[0:0] + sync init + end + attribute \src "ls180.v:711.5-711.48" + process $proc$ls180.v:711$3035 + assign { } { } + assign $0\main_sdram_choose_cmd_want_activates[0:0] 1'0 + sync always + update \main_sdram_choose_cmd_want_activates $0\main_sdram_choose_cmd_want_activates[0:0] + sync init + end + attribute \src "ls180.v:7112.1-7128.4" + process $proc$ls180.v:7112$2344 + assign { } { } + assign $0\builder_sync_rhs_array_muxed6[0:0] 1'0 + attribute \src "ls180.v:7114.2-7127.9" + switch \main_sdram_steerer_sel + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_sync_rhs_array_muxed6[0:0] 1'0 + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_sync_rhs_array_muxed6[0:0] $and$ls180.v:7119$2346_Y + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_sync_rhs_array_muxed6[0:0] $and$ls180.v:7122$2348_Y + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_sync_rhs_array_muxed6[0:0] $and$ls180.v:7125$2350_Y + end + sync always + update \builder_sync_rhs_array_muxed6 $0\builder_sync_rhs_array_muxed6[0:0] + end + attribute \src "ls180.v:7129.1-7157.4" + process $proc$ls180.v:7129$2351 + assign { } { } + assign $0\builder_sync_f_array_muxed0[0:0] 1'0 + attribute \src "ls180.v:7131.2-7156.9" + switch \main_spi_master_mosi_sel + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\builder_sync_f_array_muxed0[0:0] \main_spi_master_mosi_data [0] + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\builder_sync_f_array_muxed0[0:0] \main_spi_master_mosi_data [1] + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\builder_sync_f_array_muxed0[0:0] \main_spi_master_mosi_data [2] + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\builder_sync_f_array_muxed0[0:0] \main_spi_master_mosi_data [3] + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\builder_sync_f_array_muxed0[0:0] \main_spi_master_mosi_data [4] + attribute \src "ls180.v:0.0-0.0" + case 3'101 + assign $0\builder_sync_f_array_muxed0[0:0] \main_spi_master_mosi_data [5] + attribute \src "ls180.v:0.0-0.0" + case 3'110 + assign $0\builder_sync_f_array_muxed0[0:0] \main_spi_master_mosi_data [6] + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_sync_f_array_muxed0[0:0] \main_spi_master_mosi_data [7] + end + sync always + update \builder_sync_f_array_muxed0 $0\builder_sync_f_array_muxed0[0:0] + end + attribute \src "ls180.v:713.5-713.43" + process $proc$ls180.v:713$3036 + assign { } { } + assign $0\main_sdram_choose_cmd_cmd_ready[0:0] 1'0 + sync always + update \main_sdram_choose_cmd_cmd_ready $0\main_sdram_choose_cmd_cmd_ready[0:0] + sync init + end + attribute \src "ls180.v:7158.1-7186.4" + process $proc$ls180.v:7158$2352 + assign { } { } + assign $0\builder_sync_f_array_muxed1[0:0] 1'0 + attribute \src "ls180.v:7160.2-7185.9" + switch \libresocsim_mosi_sel + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\builder_sync_f_array_muxed1[0:0] \libresocsim_mosi_data [0] + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\builder_sync_f_array_muxed1[0:0] \libresocsim_mosi_data [1] + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\builder_sync_f_array_muxed1[0:0] \libresocsim_mosi_data [2] + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\builder_sync_f_array_muxed1[0:0] \libresocsim_mosi_data [3] + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\builder_sync_f_array_muxed1[0:0] \libresocsim_mosi_data [4] + attribute \src "ls180.v:0.0-0.0" + case 3'101 + assign $0\builder_sync_f_array_muxed1[0:0] \libresocsim_mosi_data [5] + attribute \src "ls180.v:0.0-0.0" + case 3'110 + assign $0\builder_sync_f_array_muxed1[0:0] \libresocsim_mosi_data [6] + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_sync_f_array_muxed1[0:0] \libresocsim_mosi_data [7] + end + sync always + update \builder_sync_f_array_muxed1 $0\builder_sync_f_array_muxed1[0:0] + end + attribute \src "ls180.v:716.5-716.49" + process $proc$ls180.v:716$3037 + assign { } { } + assign $1\main_sdram_choose_cmd_cmd_payload_cas[0:0] 1'0 + sync always + sync init + update \main_sdram_choose_cmd_cmd_payload_cas $1\main_sdram_choose_cmd_cmd_payload_cas[0:0] + end + attribute \src "ls180.v:717.5-717.49" + process $proc$ls180.v:717$3038 + assign { } { } + assign $1\main_sdram_choose_cmd_cmd_payload_ras[0:0] 1'0 + sync always + sync init + update \main_sdram_choose_cmd_cmd_payload_ras $1\main_sdram_choose_cmd_cmd_payload_ras[0:0] + end + attribute \src "ls180.v:718.5-718.48" + process $proc$ls180.v:718$3039 + assign { } { } + assign $1\main_sdram_choose_cmd_cmd_payload_we[0:0] 1'0 + sync always + sync init + update \main_sdram_choose_cmd_cmd_payload_we $1\main_sdram_choose_cmd_cmd_payload_we[0:0] + end + attribute \src "ls180.v:722.11-722.46" + process $proc$ls180.v:722$3040 + assign { } { } + assign $1\main_sdram_choose_cmd_valids[3:0] 4'0000 + sync always + sync init + update \main_sdram_choose_cmd_valids $1\main_sdram_choose_cmd_valids[3:0] + end + attribute \src "ls180.v:724.11-724.45" + process $proc$ls180.v:724$3041 + assign { } { } + assign $1\main_sdram_choose_cmd_grant[1:0] 2'00 + sync always + sync init + update \main_sdram_choose_cmd_grant $1\main_sdram_choose_cmd_grant[1:0] + end + attribute \src "ls180.v:7244.1-7262.4" + process $proc$ls180.v:7244$2353 + assign { } { } + assign { } { } + assign $0\main_gpio_status[15:0] [0] \builder_multiregimpl1_regs1 + assign $0\main_gpio_status[15:0] [1] \builder_multiregimpl2_regs1 + assign $0\main_gpio_status[15:0] [2] \builder_multiregimpl3_regs1 + assign $0\main_gpio_status[15:0] [3] \builder_multiregimpl4_regs1 + assign $0\main_gpio_status[15:0] [4] \builder_multiregimpl5_regs1 + assign $0\main_gpio_status[15:0] [5] \builder_multiregimpl6_regs1 + assign $0\main_gpio_status[15:0] [6] \builder_multiregimpl7_regs1 + assign $0\main_gpio_status[15:0] [7] \builder_multiregimpl8_regs1 + assign $0\main_gpio_status[15:0] [8] \builder_multiregimpl9_regs1 + assign $0\main_gpio_status[15:0] [9] \builder_multiregimpl10_regs1 + assign $0\main_gpio_status[15:0] [10] \builder_multiregimpl11_regs1 + assign $0\main_gpio_status[15:0] [11] \builder_multiregimpl12_regs1 + assign $0\main_gpio_status[15:0] [12] \builder_multiregimpl13_regs1 + assign $0\main_gpio_status[15:0] [13] \builder_multiregimpl14_regs1 + assign $0\main_gpio_status[15:0] [14] \builder_multiregimpl15_regs1 + assign $0\main_gpio_status[15:0] [15] \builder_multiregimpl16_regs1 + sync always + update \main_gpio_status $0\main_gpio_status[15:0] + end + attribute \src "ls180.v:726.5-726.44" + process $proc$ls180.v:726$3042 + assign { } { } + assign $1\main_sdram_choose_req_want_reads[0:0] 1'0 + sync always + sync init + update \main_sdram_choose_req_want_reads $1\main_sdram_choose_req_want_reads[0:0] + end + attribute \src "ls180.v:727.5-727.45" + process $proc$ls180.v:727$3043 + assign { } { } + assign $1\main_sdram_choose_req_want_writes[0:0] 1'0 + sync always + sync init + update \main_sdram_choose_req_want_writes $1\main_sdram_choose_req_want_writes[0:0] + end + attribute \src "ls180.v:7283.1-7285.4" + process $proc$ls180.v:7283$2354 + assign { } { } + assign $0\main_int_rst[0:0] \sys_rst + sync posedge \por_clk + update \main_int_rst $0\main_int_rst[0:0] + end + attribute \src "ls180.v:7287.1-7357.4" + process $proc$ls180.v:7287$2355 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\sdram_a[12:0] [0] \main_dfi_p0_address [0] + assign $0\sdram_a[12:0] [1] \main_dfi_p0_address [1] + assign $0\sdram_a[12:0] [2] \main_dfi_p0_address [2] + assign $0\sdram_a[12:0] [3] \main_dfi_p0_address [3] + assign $0\sdram_a[12:0] [4] \main_dfi_p0_address [4] + assign $0\sdram_a[12:0] [5] \main_dfi_p0_address [5] + assign $0\sdram_a[12:0] [6] \main_dfi_p0_address [6] + assign $0\sdram_a[12:0] [7] \main_dfi_p0_address [7] + assign $0\sdram_a[12:0] [8] \main_dfi_p0_address [8] + assign $0\sdram_a[12:0] [9] \main_dfi_p0_address [9] + assign $0\sdram_a[12:0] [10] \main_dfi_p0_address [10] + assign $0\sdram_a[12:0] [11] \main_dfi_p0_address [11] + assign $0\sdram_a[12:0] [12] \main_dfi_p0_address [12] + assign $0\sdram_ba[1:0] [0] \main_dfi_p0_bank [0] + assign $0\sdram_ba[1:0] [1] \main_dfi_p0_bank [1] + assign $0\sdram_cas_n[0:0] \main_dfi_p0_cas_n + assign $0\sdram_ras_n[0:0] \main_dfi_p0_ras_n + assign $0\sdram_we_n[0:0] \main_dfi_p0_we_n + assign $0\sdram_cke[0:0] \main_dfi_p0_cke + assign $0\sdram_cs_n[0:0] \main_dfi_p0_cs_n + assign $0\sdram_dq_oe[0:0] \main_dfi_p0_wrdata_en + assign $0\sdram_dq_o[15:0] [0] \main_dfi_p0_wrdata [0] + assign $0\main_dfi_p0_rddata[15:0] [0] \sdram_dq_i [0] + assign $0\sdram_dq_o[15:0] [1] \main_dfi_p0_wrdata [1] + assign $0\main_dfi_p0_rddata[15:0] [1] \sdram_dq_i [1] + assign $0\sdram_dq_o[15:0] [2] \main_dfi_p0_wrdata [2] + assign $0\main_dfi_p0_rddata[15:0] [2] \sdram_dq_i [2] + assign $0\sdram_dq_o[15:0] [3] \main_dfi_p0_wrdata [3] + assign $0\main_dfi_p0_rddata[15:0] [3] \sdram_dq_i [3] + assign $0\sdram_dq_o[15:0] [4] \main_dfi_p0_wrdata [4] + assign $0\main_dfi_p0_rddata[15:0] [4] \sdram_dq_i [4] + assign $0\sdram_dq_o[15:0] [5] \main_dfi_p0_wrdata [5] + assign $0\main_dfi_p0_rddata[15:0] [5] \sdram_dq_i [5] + assign $0\sdram_dq_o[15:0] [6] \main_dfi_p0_wrdata [6] + assign $0\main_dfi_p0_rddata[15:0] [6] \sdram_dq_i [6] + assign $0\sdram_dq_o[15:0] [7] \main_dfi_p0_wrdata [7] + assign $0\main_dfi_p0_rddata[15:0] [7] \sdram_dq_i [7] + assign $0\sdram_dq_o[15:0] [8] \main_dfi_p0_wrdata [8] + assign $0\main_dfi_p0_rddata[15:0] [8] \sdram_dq_i [8] + assign $0\sdram_dq_o[15:0] [9] \main_dfi_p0_wrdata [9] + assign $0\main_dfi_p0_rddata[15:0] [9] \sdram_dq_i [9] + assign $0\sdram_dq_o[15:0] [10] \main_dfi_p0_wrdata [10] + assign $0\main_dfi_p0_rddata[15:0] [10] \sdram_dq_i [10] + assign $0\sdram_dq_o[15:0] [11] \main_dfi_p0_wrdata [11] + assign $0\main_dfi_p0_rddata[15:0] [11] \sdram_dq_i [11] + assign $0\sdram_dq_o[15:0] [12] \main_dfi_p0_wrdata [12] + assign $0\main_dfi_p0_rddata[15:0] [12] \sdram_dq_i [12] + assign $0\sdram_dq_o[15:0] [13] \main_dfi_p0_wrdata [13] + assign $0\main_dfi_p0_rddata[15:0] [13] \sdram_dq_i [13] + assign $0\sdram_dq_o[15:0] [14] \main_dfi_p0_wrdata [14] + assign $0\main_dfi_p0_rddata[15:0] [14] \sdram_dq_i [14] + assign $0\sdram_dq_o[15:0] [15] \main_dfi_p0_wrdata [15] + assign $0\main_dfi_p0_rddata[15:0] [15] \sdram_dq_i [15] + assign $0\sdram_dm[1:0] [0] \main_dfi_p0_wrdata_mask [0] + assign $0\sdram_dm[1:0] [1] \main_dfi_p0_wrdata_mask [1] + assign $0\sdram_clock[0:0] \sys_clk_1 + assign $0\sdcard_clk[0:0] $and$ls180.v:7344$2357_Y + assign $0\sdcard_cmd_oe[0:0] \main_sdphy_sdpads_cmd_oe + assign $0\sdcard_cmd_o[0:0] \main_sdphy_sdpads_cmd_o + assign $0\main_sdphy_sdpads_cmd_i[0:0] \sdcard_cmd_i + assign $0\sdcard_data_oe[0:0] \main_sdphy_sdpads_data_oe + assign $0\sdcard_data_o[3:0] [0] \main_sdphy_sdpads_data_o [0] + assign $0\main_sdphy_sdpads_data_i[3:0] [0] \sdcard_data_i [0] + assign $0\sdcard_data_o[3:0] [1] \main_sdphy_sdpads_data_o [1] + assign $0\main_sdphy_sdpads_data_i[3:0] [1] \sdcard_data_i [1] + assign $0\sdcard_data_o[3:0] [2] \main_sdphy_sdpads_data_o [2] + assign $0\main_sdphy_sdpads_data_i[3:0] [2] \sdcard_data_i [2] + assign $0\sdcard_data_o[3:0] [3] \main_sdphy_sdpads_data_o [3] + assign $0\main_sdphy_sdpads_data_i[3:0] [3] \sdcard_data_i [3] + sync posedge \sdrio_clk + update \sdram_a $0\sdram_a[12:0] + update \sdram_dq_o $0\sdram_dq_o[15:0] + update \sdram_dq_oe $0\sdram_dq_oe[0:0] + update \sdram_we_n $0\sdram_we_n[0:0] + update \sdram_ras_n $0\sdram_ras_n[0:0] + update \sdram_cas_n $0\sdram_cas_n[0:0] + update \sdram_cs_n $0\sdram_cs_n[0:0] + update \sdram_cke $0\sdram_cke[0:0] + update \sdram_ba $0\sdram_ba[1:0] + update \sdram_dm $0\sdram_dm[1:0] + update \sdram_clock $0\sdram_clock[0:0] + update \sdcard_clk $0\sdcard_clk[0:0] + update \sdcard_cmd_o $0\sdcard_cmd_o[0:0] + update \sdcard_cmd_oe $0\sdcard_cmd_oe[0:0] + update \sdcard_data_o $0\sdcard_data_o[3:0] + update \sdcard_data_oe $0\sdcard_data_oe[0:0] + update \main_dfi_p0_rddata $0\main_dfi_p0_rddata[15:0] + update \main_sdphy_sdpads_cmd_i $0\main_sdphy_sdpads_cmd_i[0:0] + update \main_sdphy_sdpads_data_i $0\main_sdphy_sdpads_data_i[3:0] + end + attribute \src "ls180.v:729.5-729.48" + process $proc$ls180.v:729$3044 + assign { } { } + assign $1\main_sdram_choose_req_want_activates[0:0] 1'0 + sync always + sync init + update \main_sdram_choose_req_want_activates $1\main_sdram_choose_req_want_activates[0:0] + end + attribute \src "ls180.v:731.5-731.43" + process $proc$ls180.v:731$3045 + assign { } { } + assign $1\main_sdram_choose_req_cmd_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_choose_req_cmd_ready $1\main_sdram_choose_req_cmd_ready[0:0] + end + attribute \src "ls180.v:734.5-734.49" + process $proc$ls180.v:734$3046 + assign { } { } + assign $1\main_sdram_choose_req_cmd_payload_cas[0:0] 1'0 + sync always + sync init + update \main_sdram_choose_req_cmd_payload_cas $1\main_sdram_choose_req_cmd_payload_cas[0:0] + end + attribute \src "ls180.v:735.5-735.49" + process $proc$ls180.v:735$3047 + assign { } { } + assign $1\main_sdram_choose_req_cmd_payload_ras[0:0] 1'0 + sync always + sync init + update \main_sdram_choose_req_cmd_payload_ras $1\main_sdram_choose_req_cmd_payload_ras[0:0] + end + attribute \src "ls180.v:7359.1-9973.4" + process $proc$ls180.v:7359$2358 + assign $0\spi_master_clk[0:0] \spi_master_clk + assign $0\spi_master_mosi[0:0] \spi_master_mosi + assign { } { } + assign $0\pwm0[0:0] \pwm0 + assign $0\pwm1[0:0] \pwm1 + assign $0\spisdcard_clk[0:0] \spisdcard_clk + assign $0\spisdcard_mosi[0:0] \spisdcard_mosi + assign { } { } + assign $0\main_libresocsim_reset_storage[0:0] \main_libresocsim_reset_storage + assign { } { } + assign $0\main_libresocsim_scratch_storage[31:0] \main_libresocsim_scratch_storage + assign { } { } + assign $0\main_libresocsim_bus_errors[31:0] \main_libresocsim_bus_errors + assign $0\main_libresocsim_libresoc_constraintmanager0_uart0_tx[0:0] \main_libresocsim_libresoc_constraintmanager0_uart0_tx + assign $0\main_libresocsim_converter0_counter[0:0] \main_libresocsim_converter0_counter + assign $0\main_libresocsim_converter0_dat_r[63:0] \main_libresocsim_converter0_dat_r + assign $0\main_libresocsim_converter1_counter[0:0] \main_libresocsim_converter1_counter + assign $0\main_libresocsim_converter1_dat_r[63:0] \main_libresocsim_converter1_dat_r + assign $0\main_libresocsim_converter2_counter[0:0] \main_libresocsim_converter2_counter + assign $0\main_libresocsim_converter2_dat_r[63:0] \main_libresocsim_converter2_dat_r + assign { } { } + assign $0\main_libresocsim_load_storage[31:0] \main_libresocsim_load_storage + assign { } { } + assign $0\main_libresocsim_reload_storage[31:0] \main_libresocsim_reload_storage + assign { } { } + assign $0\main_libresocsim_en_storage[0:0] \main_libresocsim_en_storage + assign { } { } + assign $0\main_libresocsim_update_value_storage[0:0] \main_libresocsim_update_value_storage + assign { } { } + assign $0\main_libresocsim_value_status[31:0] \main_libresocsim_value_status + assign $0\main_libresocsim_zero_pending[0:0] \main_libresocsim_zero_pending + assign { } { } + assign $0\main_libresocsim_eventmanager_storage[0:0] \main_libresocsim_eventmanager_storage + assign { } { } + assign $0\main_libresocsim_value[31:0] \main_libresocsim_value + assign { } { } + assign { } { } + assign $0\main_sdram_storage[3:0] \main_sdram_storage + assign { } { } + assign $0\main_sdram_command_storage[5:0] \main_sdram_command_storage + assign { } { } + assign $0\main_sdram_address_storage[12:0] \main_sdram_address_storage + assign { } { } + assign $0\main_sdram_baddress_storage[1:0] \main_sdram_baddress_storage + assign { } { } + assign $0\main_sdram_wrdata_storage[15:0] \main_sdram_wrdata_storage + assign { } { } + assign $0\main_sdram_status[15:0] \main_sdram_status + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdram_timer_count1[9:0] \main_sdram_timer_count1 + assign { } { } + assign $0\main_sdram_postponer_count[0:0] \main_sdram_postponer_count + assign { } { } + assign $0\main_sdram_sequencer_counter[3:0] \main_sdram_sequencer_counter + assign $0\main_sdram_sequencer_count[0:0] \main_sdram_sequencer_count + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] \main_sdram_bankmachine0_cmd_buffer_lookahead_level + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] \main_sdram_bankmachine0_cmd_buffer_lookahead_produce + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] \main_sdram_bankmachine0_cmd_buffer_lookahead_consume + assign $0\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine0_cmd_buffer_source_valid + assign $0\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] \main_sdram_bankmachine0_cmd_buffer_source_first + assign $0\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] \main_sdram_bankmachine0_cmd_buffer_source_last + assign $0\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] \main_sdram_bankmachine0_cmd_buffer_source_payload_we + assign $0\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine0_cmd_buffer_source_payload_addr + assign $0\main_sdram_bankmachine0_row[12:0] \main_sdram_bankmachine0_row + assign $0\main_sdram_bankmachine0_row_opened[0:0] \main_sdram_bankmachine0_row_opened + assign $0\main_sdram_bankmachine0_twtpcon_ready[0:0] \main_sdram_bankmachine0_twtpcon_ready + assign $0\main_sdram_bankmachine0_twtpcon_count[2:0] \main_sdram_bankmachine0_twtpcon_count + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] \main_sdram_bankmachine1_cmd_buffer_lookahead_level + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] \main_sdram_bankmachine1_cmd_buffer_lookahead_produce + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] \main_sdram_bankmachine1_cmd_buffer_lookahead_consume + assign $0\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine1_cmd_buffer_source_valid + assign $0\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] \main_sdram_bankmachine1_cmd_buffer_source_first + assign $0\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] \main_sdram_bankmachine1_cmd_buffer_source_last + assign $0\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] \main_sdram_bankmachine1_cmd_buffer_source_payload_we + assign $0\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine1_cmd_buffer_source_payload_addr + assign $0\main_sdram_bankmachine1_row[12:0] \main_sdram_bankmachine1_row + assign $0\main_sdram_bankmachine1_row_opened[0:0] \main_sdram_bankmachine1_row_opened + assign $0\main_sdram_bankmachine1_twtpcon_ready[0:0] \main_sdram_bankmachine1_twtpcon_ready + assign $0\main_sdram_bankmachine1_twtpcon_count[2:0] \main_sdram_bankmachine1_twtpcon_count + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] \main_sdram_bankmachine2_cmd_buffer_lookahead_level + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] \main_sdram_bankmachine2_cmd_buffer_lookahead_produce + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] \main_sdram_bankmachine2_cmd_buffer_lookahead_consume + assign $0\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine2_cmd_buffer_source_valid + assign $0\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] \main_sdram_bankmachine2_cmd_buffer_source_first + assign $0\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] \main_sdram_bankmachine2_cmd_buffer_source_last + assign $0\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] \main_sdram_bankmachine2_cmd_buffer_source_payload_we + assign $0\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine2_cmd_buffer_source_payload_addr + assign $0\main_sdram_bankmachine2_row[12:0] \main_sdram_bankmachine2_row + assign $0\main_sdram_bankmachine2_row_opened[0:0] \main_sdram_bankmachine2_row_opened + assign $0\main_sdram_bankmachine2_twtpcon_ready[0:0] \main_sdram_bankmachine2_twtpcon_ready + assign $0\main_sdram_bankmachine2_twtpcon_count[2:0] \main_sdram_bankmachine2_twtpcon_count + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] \main_sdram_bankmachine3_cmd_buffer_lookahead_level + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] \main_sdram_bankmachine3_cmd_buffer_lookahead_produce + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] \main_sdram_bankmachine3_cmd_buffer_lookahead_consume + assign $0\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine3_cmd_buffer_source_valid + assign $0\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] \main_sdram_bankmachine3_cmd_buffer_source_first + assign $0\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] \main_sdram_bankmachine3_cmd_buffer_source_last + assign $0\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] \main_sdram_bankmachine3_cmd_buffer_source_payload_we + assign $0\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine3_cmd_buffer_source_payload_addr + assign $0\main_sdram_bankmachine3_row[12:0] \main_sdram_bankmachine3_row + assign $0\main_sdram_bankmachine3_row_opened[0:0] \main_sdram_bankmachine3_row_opened + assign $0\main_sdram_bankmachine3_twtpcon_ready[0:0] \main_sdram_bankmachine3_twtpcon_ready + assign $0\main_sdram_bankmachine3_twtpcon_count[2:0] \main_sdram_bankmachine3_twtpcon_count + assign $0\main_sdram_choose_cmd_grant[1:0] \main_sdram_choose_cmd_grant + assign $0\main_sdram_choose_req_grant[1:0] \main_sdram_choose_req_grant + assign $0\main_sdram_tccdcon_ready[0:0] \main_sdram_tccdcon_ready + assign $0\main_sdram_tccdcon_count[0:0] \main_sdram_tccdcon_count + assign $0\main_sdram_twtrcon_ready[0:0] \main_sdram_twtrcon_ready + assign $0\main_sdram_twtrcon_count[2:0] \main_sdram_twtrcon_count + assign $0\main_sdram_time0[4:0] \main_sdram_time0 + assign $0\main_sdram_time1[3:0] \main_sdram_time1 + assign $0\main_converter_counter[0:0] \main_converter_counter + assign $0\main_converter_dat_r[31:0] \main_converter_dat_r + assign $0\main_cmd_consumed[0:0] \main_cmd_consumed + assign $0\main_wdata_consumed[0:0] \main_wdata_consumed + assign $0\main_storage[31:0] \main_storage + assign { } { } + assign { } { } + assign $0\main_uart_clk_txen[0:0] \main_uart_clk_txen + assign $0\main_phase_accumulator_tx[31:0] \main_phase_accumulator_tx + assign $0\main_tx_reg[7:0] \main_tx_reg + assign $0\main_tx_bitcount[3:0] \main_tx_bitcount + assign $0\main_tx_busy[0:0] \main_tx_busy + assign { } { } + assign $0\main_source_payload_data[7:0] \main_source_payload_data + assign $0\main_uart_clk_rxen[0:0] \main_uart_clk_rxen + assign $0\main_phase_accumulator_rx[31:0] \main_phase_accumulator_rx + assign { } { } + assign $0\main_rx_reg[7:0] \main_rx_reg + assign $0\main_rx_bitcount[3:0] \main_rx_bitcount + assign $0\main_rx_busy[0:0] \main_rx_busy + assign $0\main_uart_tx_pending[0:0] \main_uart_tx_pending + assign { } { } + assign $0\main_uart_rx_pending[0:0] \main_uart_rx_pending + assign { } { } + assign $0\main_uart_eventmanager_storage[1:0] \main_uart_eventmanager_storage + assign { } { } + assign $0\main_uart_tx_fifo_readable[0:0] \main_uart_tx_fifo_readable + assign $0\main_uart_tx_fifo_level0[4:0] \main_uart_tx_fifo_level0 + assign $0\main_uart_tx_fifo_produce[3:0] \main_uart_tx_fifo_produce + assign $0\main_uart_tx_fifo_consume[3:0] \main_uart_tx_fifo_consume + assign $0\main_uart_rx_fifo_readable[0:0] \main_uart_rx_fifo_readable + assign $0\main_uart_rx_fifo_level0[4:0] \main_uart_rx_fifo_level0 + assign $0\main_uart_rx_fifo_produce[3:0] \main_uart_rx_fifo_produce + assign $0\main_uart_rx_fifo_consume[3:0] \main_uart_rx_fifo_consume + assign $0\main_gpio_oe_storage[15:0] \main_gpio_oe_storage + assign { } { } + assign $0\main_gpio_out_storage[15:0] \main_gpio_out_storage + assign { } { } + assign $0\main_spi_master_miso[7:0] \main_spi_master_miso + assign $0\main_spi_master_control_storage[15:0] \main_spi_master_control_storage + assign { } { } + assign $0\main_spi_master_mosi_storage[7:0] \main_spi_master_mosi_storage + assign { } { } + assign $0\main_spi_master_cs_storage[0:0] \main_spi_master_cs_storage + assign { } { } + assign $0\main_spi_master_loopback_storage[0:0] \main_spi_master_loopback_storage + assign { } { } + assign $0\main_spi_master_count[2:0] \main_spi_master_count + assign { } { } + assign $0\main_spi_master_mosi_data[7:0] \main_spi_master_mosi_data + assign $0\main_spi_master_mosi_sel[2:0] \main_spi_master_mosi_sel + assign $0\main_spi_master_miso_data[7:0] \main_spi_master_miso_data + assign { } { } + assign $0\main_pwm0_counter[31:0] \main_pwm0_counter + assign $0\main_pwm0_enable_storage[0:0] \main_pwm0_enable_storage + assign { } { } + assign $0\main_pwm0_width_storage[31:0] \main_pwm0_width_storage + assign { } { } + assign $0\main_pwm0_period_storage[31:0] \main_pwm0_period_storage + assign { } { } + assign $0\main_pwm1_counter[31:0] \main_pwm1_counter + assign $0\main_pwm1_enable_storage[0:0] \main_pwm1_enable_storage + assign { } { } + assign $0\main_pwm1_width_storage[31:0] \main_pwm1_width_storage + assign { } { } + assign $0\main_pwm1_period_storage[31:0] \main_pwm1_period_storage + assign { } { } + assign $0\main_sdphy_clocker_storage[8:0] \main_sdphy_clocker_storage + assign { } { } + assign { } { } + assign $0\main_sdphy_clocker_clks[8:0] \main_sdphy_clocker_clks + assign { } { } + assign $0\main_sdphy_init_count[7:0] \main_sdphy_init_count + assign $0\main_sdphy_cmdw_count[7:0] \main_sdphy_cmdw_count + assign $0\main_sdphy_cmdr_timeout[31:0] \main_sdphy_cmdr_timeout + assign $0\main_sdphy_cmdr_count[7:0] \main_sdphy_cmdr_count + assign $0\main_sdphy_cmdr_cmdr_run[0:0] \main_sdphy_cmdr_cmdr_run + assign $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0] \main_sdphy_cmdr_cmdr_converter_source_first + assign $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0] \main_sdphy_cmdr_cmdr_converter_source_last + assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] \main_sdphy_cmdr_cmdr_converter_source_payload_data + assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] \main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count + assign $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] \main_sdphy_cmdr_cmdr_converter_demux + assign $0\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] \main_sdphy_cmdr_cmdr_converter_strobe_all + assign $0\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] \main_sdphy_cmdr_cmdr_buf_source_valid + assign $0\main_sdphy_cmdr_cmdr_buf_source_first[0:0] \main_sdphy_cmdr_cmdr_buf_source_first + assign $0\main_sdphy_cmdr_cmdr_buf_source_last[0:0] \main_sdphy_cmdr_cmdr_buf_source_last + assign $0\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] \main_sdphy_cmdr_cmdr_buf_source_payload_data + assign $0\main_sdphy_cmdr_cmdr_reset[0:0] \main_sdphy_cmdr_cmdr_reset + assign $0\main_sdphy_dataw_count[7:0] \main_sdphy_dataw_count + assign $0\main_sdphy_dataw_crcr_run[0:0] \main_sdphy_dataw_crcr_run + assign $0\main_sdphy_dataw_crcr_converter_source_first[0:0] \main_sdphy_dataw_crcr_converter_source_first + assign $0\main_sdphy_dataw_crcr_converter_source_last[0:0] \main_sdphy_dataw_crcr_converter_source_last + assign $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] \main_sdphy_dataw_crcr_converter_source_payload_data + assign $0\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] \main_sdphy_dataw_crcr_converter_source_payload_valid_token_count + assign $0\main_sdphy_dataw_crcr_converter_demux[2:0] \main_sdphy_dataw_crcr_converter_demux + assign $0\main_sdphy_dataw_crcr_converter_strobe_all[0:0] \main_sdphy_dataw_crcr_converter_strobe_all + assign $0\main_sdphy_dataw_crcr_buf_source_valid[0:0] \main_sdphy_dataw_crcr_buf_source_valid + assign $0\main_sdphy_dataw_crcr_buf_source_first[0:0] \main_sdphy_dataw_crcr_buf_source_first + assign $0\main_sdphy_dataw_crcr_buf_source_last[0:0] \main_sdphy_dataw_crcr_buf_source_last + assign $0\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] \main_sdphy_dataw_crcr_buf_source_payload_data + assign $0\main_sdphy_dataw_crcr_reset[0:0] \main_sdphy_dataw_crcr_reset + assign $0\main_sdphy_datar_timeout[31:0] \main_sdphy_datar_timeout + assign $0\main_sdphy_datar_count[9:0] \main_sdphy_datar_count + assign $0\main_sdphy_datar_datar_run[0:0] \main_sdphy_datar_datar_run + assign $0\main_sdphy_datar_datar_converter_source_first[0:0] \main_sdphy_datar_datar_converter_source_first + assign $0\main_sdphy_datar_datar_converter_source_last[0:0] \main_sdphy_datar_datar_converter_source_last + assign $0\main_sdphy_datar_datar_converter_source_payload_data[7:0] \main_sdphy_datar_datar_converter_source_payload_data + assign $0\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] \main_sdphy_datar_datar_converter_source_payload_valid_token_count + assign $0\main_sdphy_datar_datar_converter_demux[0:0] \main_sdphy_datar_datar_converter_demux + assign $0\main_sdphy_datar_datar_converter_strobe_all[0:0] \main_sdphy_datar_datar_converter_strobe_all + assign $0\main_sdphy_datar_datar_buf_source_valid[0:0] \main_sdphy_datar_datar_buf_source_valid + assign $0\main_sdphy_datar_datar_buf_source_first[0:0] \main_sdphy_datar_datar_buf_source_first + assign $0\main_sdphy_datar_datar_buf_source_last[0:0] \main_sdphy_datar_datar_buf_source_last + assign $0\main_sdphy_datar_datar_buf_source_payload_data[7:0] \main_sdphy_datar_datar_buf_source_payload_data + assign $0\main_sdphy_datar_datar_reset[0:0] \main_sdphy_datar_datar_reset + assign $0\main_sdcore_cmd_argument_storage[31:0] \main_sdcore_cmd_argument_storage + assign { } { } + assign $0\main_sdcore_cmd_command_storage[31:0] \main_sdcore_cmd_command_storage + assign { } { } + assign $0\main_sdcore_cmd_response_status[127:0] \main_sdcore_cmd_response_status + assign $0\main_sdcore_block_length_storage[9:0] \main_sdcore_block_length_storage + assign { } { } + assign $0\main_sdcore_block_count_storage[31:0] \main_sdcore_block_count_storage + assign { } { } + assign $0\main_sdcore_crc7_inserter_crcreg0[6:0] \main_sdcore_crc7_inserter_crcreg0 + assign $0\main_sdcore_crc16_inserter_cnt[2:0] \main_sdcore_crc16_inserter_cnt + assign $0\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] \main_sdcore_crc16_inserter_crc0_crcreg0 + assign $0\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] \main_sdcore_crc16_inserter_crc1_crcreg0 + assign $0\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] \main_sdcore_crc16_inserter_crc2_crcreg0 + assign $0\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] \main_sdcore_crc16_inserter_crc3_crcreg0 + assign $0\main_sdcore_crc16_inserter_crctmp0[15:0] \main_sdcore_crc16_inserter_crctmp0 + assign $0\main_sdcore_crc16_inserter_crctmp1[15:0] \main_sdcore_crc16_inserter_crctmp1 + assign $0\main_sdcore_crc16_inserter_crctmp2[15:0] \main_sdcore_crc16_inserter_crctmp2 + assign $0\main_sdcore_crc16_inserter_crctmp3[15:0] \main_sdcore_crc16_inserter_crctmp3 + assign $0\main_sdcore_crc16_checker_val[7:0] \main_sdcore_crc16_checker_val + assign $0\main_sdcore_crc16_checker_cnt[3:0] \main_sdcore_crc16_checker_cnt + assign $0\main_sdcore_crc16_checker_crc0_crcreg0[15:0] \main_sdcore_crc16_checker_crc0_crcreg0 + assign $0\main_sdcore_crc16_checker_crc1_crcreg0[15:0] \main_sdcore_crc16_checker_crc1_crcreg0 + assign $0\main_sdcore_crc16_checker_crc2_crcreg0[15:0] \main_sdcore_crc16_checker_crc2_crcreg0 + assign $0\main_sdcore_crc16_checker_crc3_crcreg0[15:0] \main_sdcore_crc16_checker_crc3_crcreg0 + assign $0\main_sdcore_crc16_checker_crctmp0[15:0] \main_sdcore_crc16_checker_crctmp0 + assign $0\main_sdcore_crc16_checker_crctmp1[15:0] \main_sdcore_crc16_checker_crctmp1 + assign $0\main_sdcore_crc16_checker_crctmp2[15:0] \main_sdcore_crc16_checker_crctmp2 + assign $0\main_sdcore_crc16_checker_crctmp3[15:0] \main_sdcore_crc16_checker_crctmp3 + assign $0\main_sdcore_crc16_checker_fifo0[15:0] \main_sdcore_crc16_checker_fifo0 + assign $0\main_sdcore_crc16_checker_fifo1[15:0] \main_sdcore_crc16_checker_fifo1 + assign $0\main_sdcore_crc16_checker_fifo2[15:0] \main_sdcore_crc16_checker_fifo2 + assign $0\main_sdcore_crc16_checker_fifo3[15:0] \main_sdcore_crc16_checker_fifo3 + assign $0\main_sdcore_cmd_count[2:0] \main_sdcore_cmd_count + assign $0\main_sdcore_cmd_done[0:0] \main_sdcore_cmd_done + assign $0\main_sdcore_cmd_error[0:0] \main_sdcore_cmd_error + assign $0\main_sdcore_cmd_timeout[0:0] \main_sdcore_cmd_timeout + assign $0\main_sdcore_data_count[31:0] \main_sdcore_data_count + assign $0\main_sdcore_data_done[0:0] \main_sdcore_data_done + assign $0\main_sdcore_data_error[0:0] \main_sdcore_data_error + assign $0\main_sdcore_data_timeout[0:0] \main_sdcore_data_timeout + assign $0\main_sdblock2mem_fifo_level[5:0] \main_sdblock2mem_fifo_level + assign $0\main_sdblock2mem_fifo_produce[4:0] \main_sdblock2mem_fifo_produce + assign $0\main_sdblock2mem_fifo_consume[4:0] \main_sdblock2mem_fifo_consume + assign $0\main_sdblock2mem_converter_source_first[0:0] \main_sdblock2mem_converter_source_first + assign $0\main_sdblock2mem_converter_source_last[0:0] \main_sdblock2mem_converter_source_last + assign $0\main_sdblock2mem_converter_source_payload_data[31:0] \main_sdblock2mem_converter_source_payload_data + assign $0\main_sdblock2mem_converter_source_payload_valid_token_count[2:0] \main_sdblock2mem_converter_source_payload_valid_token_count + assign $0\main_sdblock2mem_converter_demux[1:0] \main_sdblock2mem_converter_demux + assign $0\main_sdblock2mem_converter_strobe_all[0:0] \main_sdblock2mem_converter_strobe_all + assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] \main_sdblock2mem_wishbonedmawriter_base_storage + assign { } { } + assign $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] \main_sdblock2mem_wishbonedmawriter_length_storage + assign { } { } + assign $0\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] \main_sdblock2mem_wishbonedmawriter_enable_storage + assign { } { } + assign $0\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] \main_sdblock2mem_wishbonedmawriter_loop_storage + assign { } { } + assign $0\main_sdblock2mem_wishbonedmawriter_offset[31:0] \main_sdblock2mem_wishbonedmawriter_offset + assign $0\main_sdmem2block_dma_data[31:0] \main_sdmem2block_dma_data + assign $0\main_sdmem2block_dma_base_storage[63:0] \main_sdmem2block_dma_base_storage + assign { } { } + assign $0\main_sdmem2block_dma_length_storage[31:0] \main_sdmem2block_dma_length_storage + assign { } { } + assign $0\main_sdmem2block_dma_enable_storage[0:0] \main_sdmem2block_dma_enable_storage + assign { } { } + assign $0\main_sdmem2block_dma_loop_storage[0:0] \main_sdmem2block_dma_loop_storage + assign { } { } + assign $0\main_sdmem2block_dma_offset[31:0] \main_sdmem2block_dma_offset + assign $0\main_sdmem2block_converter_mux[1:0] \main_sdmem2block_converter_mux + assign $0\main_sdmem2block_fifo_level[5:0] \main_sdmem2block_fifo_level + assign $0\main_sdmem2block_fifo_produce[4:0] \main_sdmem2block_fifo_produce + assign $0\main_sdmem2block_fifo_consume[4:0] \main_sdmem2block_fifo_consume + assign $0\libresocsim_miso[7:0] \libresocsim_miso + assign $0\libresocsim_control_storage[15:0] \libresocsim_control_storage + assign { } { } + assign $0\libresocsim_mosi_storage[7:0] \libresocsim_mosi_storage + assign { } { } + assign $0\libresocsim_cs_storage[0:0] \libresocsim_cs_storage + assign { } { } + assign $0\libresocsim_loopback_storage[0:0] \libresocsim_loopback_storage + assign { } { } + assign $0\libresocsim_count[2:0] \libresocsim_count + assign { } { } + assign $0\libresocsim_mosi_data[7:0] \libresocsim_mosi_data + assign $0\libresocsim_mosi_sel[2:0] \libresocsim_mosi_sel + assign $0\libresocsim_miso_data[7:0] \libresocsim_miso_data + assign $0\libresocsim_storage[15:0] \libresocsim_storage + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\builder_libresocsim_adr[13:0] \builder_libresocsim_adr + assign $0\builder_libresocsim_we[0:0] \builder_libresocsim_we + assign $0\builder_libresocsim_dat_w[7:0] \builder_libresocsim_dat_w + assign $0\builder_grant[2:0] \builder_grant + assign { } { } + assign $0\builder_count[19:0] \builder_count + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_dummy[41:0] [0] $or$ls180.v:7360$2359_Y + assign $0\main_dummy[41:0] [1] $or$ls180.v:7361$2360_Y + assign $0\main_dummy[41:0] [2] $or$ls180.v:7362$2361_Y + assign $0\main_dummy[41:0] [3] $or$ls180.v:7363$2362_Y + assign $0\main_dummy[41:0] [4] $or$ls180.v:7364$2363_Y + assign $0\main_dummy[41:0] [5] $or$ls180.v:7365$2364_Y + assign $0\main_dummy[41:0] [6] $or$ls180.v:7366$2365_Y + assign $0\main_dummy[41:0] [7] $or$ls180.v:7367$2366_Y + assign $0\main_dummy[41:0] [8] $or$ls180.v:7368$2367_Y + assign $0\main_dummy[41:0] [9] $or$ls180.v:7369$2368_Y + assign $0\main_dummy[41:0] [10] $or$ls180.v:7370$2369_Y + assign $0\main_dummy[41:0] [11] $or$ls180.v:7371$2370_Y + assign $0\main_dummy[41:0] [12] $or$ls180.v:7372$2371_Y + assign $0\main_dummy[41:0] [13] $or$ls180.v:7373$2372_Y + assign $0\main_dummy[41:0] [14] $or$ls180.v:7374$2373_Y + assign $0\main_dummy[41:0] [15] $or$ls180.v:7375$2374_Y + assign $0\main_dummy[41:0] [16] $or$ls180.v:7376$2375_Y + assign $0\main_dummy[41:0] [17] $or$ls180.v:7377$2376_Y + assign $0\main_dummy[41:0] [18] $or$ls180.v:7378$2377_Y + assign $0\main_dummy[41:0] [19] $or$ls180.v:7379$2378_Y + assign $0\main_dummy[41:0] [20] $or$ls180.v:7380$2379_Y + assign $0\main_dummy[41:0] [21] $or$ls180.v:7381$2380_Y + assign $0\main_dummy[41:0] [22] $or$ls180.v:7382$2381_Y + assign $0\main_dummy[41:0] [23] $or$ls180.v:7383$2382_Y + assign $0\main_dummy[41:0] [24] $or$ls180.v:7384$2383_Y + assign $0\main_dummy[41:0] [25] $or$ls180.v:7385$2384_Y + assign $0\main_dummy[41:0] [26] $or$ls180.v:7386$2385_Y + assign $0\main_dummy[41:0] [27] $or$ls180.v:7387$2386_Y + assign $0\main_dummy[41:0] [28] $or$ls180.v:7388$2387_Y + assign $0\main_dummy[41:0] [29] $or$ls180.v:7389$2388_Y + assign $0\main_dummy[41:0] [30] $or$ls180.v:7390$2389_Y + assign $0\main_dummy[41:0] [31] $or$ls180.v:7391$2390_Y + assign $0\main_dummy[41:0] [32] $or$ls180.v:7392$2391_Y + assign $0\main_dummy[41:0] [33] $or$ls180.v:7393$2392_Y + assign $0\main_dummy[41:0] [34] $or$ls180.v:7394$2393_Y + assign $0\main_dummy[41:0] [35] $or$ls180.v:7395$2394_Y + assign $0\main_dummy[41:0] [36] $or$ls180.v:7396$2395_Y + assign $0\main_dummy[41:0] [37] $or$ls180.v:7397$2396_Y + assign $0\main_dummy[41:0] [38] $or$ls180.v:7398$2397_Y + assign $0\main_dummy[41:0] [39] $or$ls180.v:7399$2398_Y + assign $0\main_dummy[41:0] [40] $or$ls180.v:7400$2399_Y + assign $0\main_dummy[41:0] [41] $or$ls180.v:7401$2400_Y + assign $0\builder_converter0_state[0:0] \builder_converter0_next_state + assign $0\builder_converter1_state[0:0] \builder_converter1_next_state + assign $0\builder_converter2_state[0:0] \builder_converter2_next_state + assign $0\main_libresocsim_ram_bus_ack[0:0] 1'0 + assign $0\main_libresocsim_zero_old_trigger[0:0] \main_libresocsim_zero_trigger + assign $0\main_rddata_en[2:0] { \main_rddata_en [1:0] \main_dfi_p0_rddata_en } + assign $0\main_dfi_p0_rddata_valid[0:0] \main_rddata_en [2] + assign $0\main_sdram_postponer_req_o[0:0] 1'0 + assign $0\main_sdram_cmd_payload_a[12:0] 13'0000000000000 + assign $0\main_sdram_cmd_payload_ba[1:0] 2'00 + assign $0\main_sdram_cmd_payload_cas[0:0] 1'0 + assign $0\main_sdram_cmd_payload_ras[0:0] 1'0 + assign $0\main_sdram_cmd_payload_we[0:0] 1'0 + assign $0\main_sdram_sequencer_done1[0:0] 1'0 + assign $0\builder_refresher_state[1:0] \builder_refresher_next_state + assign $0\builder_bankmachine0_state[2:0] \builder_bankmachine0_next_state + assign $0\builder_bankmachine1_state[2:0] \builder_bankmachine1_next_state + assign $0\builder_bankmachine2_state[2:0] \builder_bankmachine2_next_state + assign $0\builder_bankmachine3_state[2:0] \builder_bankmachine3_next_state + assign $0\main_sdram_dfi_p0_cs_n[0:0] 1'0 + assign $0\main_sdram_dfi_p0_bank[1:0] \builder_sync_rhs_array_muxed0 + assign $0\main_sdram_dfi_p0_address[12:0] \builder_sync_rhs_array_muxed1 + assign $0\main_sdram_dfi_p0_cas_n[0:0] $not$ls180.v:7843$2497_Y + assign $0\main_sdram_dfi_p0_ras_n[0:0] $not$ls180.v:7844$2498_Y + assign $0\main_sdram_dfi_p0_we_n[0:0] $not$ls180.v:7845$2499_Y + assign $0\main_sdram_dfi_p0_rddata_en[0:0] \builder_sync_rhs_array_muxed5 + assign $0\main_sdram_dfi_p0_wrdata_en[0:0] \builder_sync_rhs_array_muxed6 + assign $0\builder_multiplexer_state[2:0] \builder_multiplexer_next_state + assign $0\builder_new_master_wdata_ready[0:0] $or$ls180.v:7879$2517_Y + assign $0\builder_new_master_rdata_valid0[0:0] $or$ls180.v:7880$2529_Y + assign $0\builder_new_master_rdata_valid1[0:0] \builder_new_master_rdata_valid0 + assign $0\builder_new_master_rdata_valid2[0:0] \builder_new_master_rdata_valid1 + assign $0\builder_new_master_rdata_valid3[0:0] \builder_new_master_rdata_valid2 + assign $0\builder_converter_state[0:0] \builder_converter_next_state + assign $0\main_sink_ready[0:0] 1'0 + assign $0\main_source_valid[0:0] 1'0 + assign $0\main_rx_r[0:0] \main_rx + assign $0\main_uart_tx_old_trigger[0:0] \main_uart_tx_trigger + assign $0\main_uart_rx_old_trigger[0:0] \main_uart_rx_trigger + assign $0\main_spi_master_clk_divider1[15:0] $add$ls180.v:8038$2575_Y + assign $0\spi_master_cs_n[0:0] $or$ls180.v:8047$2578_Y + assign $0\builder_spimaster0_state[1:0] \builder_spimaster0_next_state + assign $0\main_sdphy_clocker_clk_d[0:0] \main_sdphy_clocker_clk1 + assign $0\main_sdphy_clocker_clk0[0:0] \main_sdphy_clocker_clk1 + assign $0\builder_sdphy_sdphyinit_state[0:0] \builder_sdphy_sdphyinit_next_state + assign $0\builder_sdphy_sdphycmdw_state[1:0] \builder_sdphy_sdphycmdw_next_state + assign $0\builder_sdphy_sdphycmdr_state[2:0] \builder_sdphy_sdphycmdr_next_state + assign $0\builder_sdphy_sdphycrcr_state[0:0] \builder_sdphy_sdphycrcr_next_state + assign $0\builder_sdphy_fsm_state[2:0] \builder_sdphy_fsm_next_state + assign $0\builder_sdphy_sdphydatar_state[2:0] \builder_sdphy_sdphydatar_next_state + assign $0\builder_sdcore_crcupstreaminserter_state[0:0] \builder_sdcore_crcupstreaminserter_next_state + assign $0\builder_sdcore_fsm_state[2:0] \builder_sdcore_fsm_next_state + assign $0\builder_sdblock2memdma_state[1:0] \builder_sdblock2memdma_next_state + assign $0\builder_sdmem2blockdma_fsm_state[0:0] \builder_sdmem2blockdma_fsm_next_state + assign $0\builder_sdmem2blockdma_resetinserter_state[1:0] \builder_sdmem2blockdma_resetinserter_next_state + assign $0\libresocsim_clk_divider1[15:0] $add$ls180.v:8586$2670_Y + assign $0\spisdcard_cs_n[0:0] $or$ls180.v:8595$2673_Y + assign $0\builder_spimaster1_state[1:0] \builder_spimaster1_next_state + assign $0\builder_state[1:0] \builder_next_state + assign $0\builder_slave_sel_r[4:0] \builder_slave_sel + assign $0\builder_interface0_bank_bus_dat_r[7:0] 8'00000000 + assign $0\main_libresocsim_reset_re[0:0] \builder_csrbank0_reset0_re + assign $0\main_libresocsim_scratch_re[0:0] \builder_csrbank0_scratch0_re + assign $0\builder_interface1_bank_bus_dat_r[7:0] 8'00000000 + assign $0\main_gpio_oe_re[0:0] \builder_csrbank1_oe0_re + assign $0\main_gpio_out_re[0:0] \builder_csrbank1_out0_re + assign $0\builder_interface2_bank_bus_dat_r[7:0] 8'00000000 + assign $0\main_pwm0_enable_re[0:0] \builder_csrbank2_enable0_re + assign $0\main_pwm0_width_re[0:0] \builder_csrbank2_width0_re + assign $0\main_pwm0_period_re[0:0] \builder_csrbank2_period0_re + assign $0\builder_interface3_bank_bus_dat_r[7:0] 8'00000000 + assign $0\main_pwm1_enable_re[0:0] \builder_csrbank3_enable0_re + assign $0\main_pwm1_width_re[0:0] \builder_csrbank3_width0_re + assign $0\main_pwm1_period_re[0:0] \builder_csrbank3_period0_re + assign $0\builder_interface4_bank_bus_dat_r[7:0] 8'00000000 + assign $0\main_sdblock2mem_wishbonedmawriter_base_re[0:0] \builder_csrbank4_dma_base0_re + assign $0\main_sdblock2mem_wishbonedmawriter_length_re[0:0] \builder_csrbank4_dma_length0_re + assign $0\main_sdblock2mem_wishbonedmawriter_enable_re[0:0] \builder_csrbank4_dma_enable0_re + assign $0\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] \builder_csrbank4_dma_loop0_re + assign $0\builder_interface5_bank_bus_dat_r[7:0] 8'00000000 + assign $0\main_sdcore_cmd_argument_re[0:0] \builder_csrbank5_cmd_argument0_re + assign $0\main_sdcore_cmd_command_re[0:0] \builder_csrbank5_cmd_command0_re + assign $0\main_sdcore_block_length_re[0:0] \builder_csrbank5_block_length0_re + assign $0\main_sdcore_block_count_re[0:0] \builder_csrbank5_block_count0_re + assign $0\builder_interface6_bank_bus_dat_r[7:0] 8'00000000 + assign $0\main_sdmem2block_dma_base_re[0:0] \builder_csrbank6_dma_base0_re + assign $0\main_sdmem2block_dma_length_re[0:0] \builder_csrbank6_dma_length0_re + assign $0\main_sdmem2block_dma_enable_re[0:0] \builder_csrbank6_dma_enable0_re + assign $0\main_sdmem2block_dma_loop_re[0:0] \builder_csrbank6_dma_loop0_re + assign $0\builder_interface7_bank_bus_dat_r[7:0] 8'00000000 + assign $0\main_sdphy_clocker_re[0:0] \builder_csrbank7_clocker_divider0_re + assign $0\builder_interface8_bank_bus_dat_r[7:0] 8'00000000 + assign $0\main_sdram_re[0:0] \builder_csrbank8_dfii_control0_re + assign $0\main_sdram_command_re[0:0] \builder_csrbank8_dfii_pi0_command0_re + assign $0\main_sdram_address_re[0:0] \builder_csrbank8_dfii_pi0_address0_re + assign $0\main_sdram_baddress_re[0:0] \builder_csrbank8_dfii_pi0_baddress0_re + assign $0\main_sdram_wrdata_re[0:0] \builder_csrbank8_dfii_pi0_wrdata0_re + assign $0\builder_interface9_bank_bus_dat_r[7:0] 8'00000000 + assign $0\main_spi_master_control_re[0:0] \builder_csrbank9_control0_re + assign $0\main_spi_master_mosi_re[0:0] \builder_csrbank9_mosi0_re + assign $0\main_spi_master_cs_re[0:0] \builder_csrbank9_cs0_re + assign $0\main_spi_master_loopback_re[0:0] \builder_csrbank9_loopback0_re + assign $0\builder_interface10_bank_bus_dat_r[7:0] 8'00000000 + assign $0\libresocsim_control_re[0:0] \builder_csrbank10_control0_re + assign $0\libresocsim_mosi_re[0:0] \builder_csrbank10_mosi0_re + assign $0\libresocsim_cs_re[0:0] \builder_csrbank10_cs0_re + assign $0\libresocsim_loopback_re[0:0] \builder_csrbank10_loopback0_re + assign $0\libresocsim_re[0:0] \builder_csrbank10_clk_divider0_re + assign $0\builder_interface11_bank_bus_dat_r[7:0] 8'00000000 + assign $0\main_libresocsim_load_re[0:0] \builder_csrbank11_load0_re + assign $0\main_libresocsim_reload_re[0:0] \builder_csrbank11_reload0_re + assign $0\main_libresocsim_en_re[0:0] \builder_csrbank11_en0_re + assign $0\main_libresocsim_update_value_re[0:0] \builder_csrbank11_update_value0_re + assign $0\main_libresocsim_eventmanager_re[0:0] \builder_csrbank11_ev_enable0_re + assign $0\builder_interface12_bank_bus_dat_r[7:0] 8'00000000 + assign $0\main_uart_eventmanager_re[0:0] \builder_csrbank12_ev_enable0_re + assign $0\builder_interface13_bank_bus_dat_r[7:0] 8'00000000 + assign $0\main_re[0:0] \builder_csrbank13_tuning_word0_re + assign $0\builder_multiregimpl0_regs0[0:0] \main_libresocsim_libresoc_constraintmanager0_uart0_rx + assign $0\builder_multiregimpl0_regs1[0:0] \builder_multiregimpl0_regs0 + assign $0\builder_multiregimpl1_regs0[0:0] \main_gpio_pads_i [0] + assign $0\builder_multiregimpl1_regs1[0:0] \builder_multiregimpl1_regs0 + assign $0\builder_multiregimpl2_regs0[0:0] \main_gpio_pads_i [1] + assign $0\builder_multiregimpl2_regs1[0:0] \builder_multiregimpl2_regs0 + assign $0\builder_multiregimpl3_regs0[0:0] \main_gpio_pads_i [2] + assign $0\builder_multiregimpl3_regs1[0:0] \builder_multiregimpl3_regs0 + assign $0\builder_multiregimpl4_regs0[0:0] \main_gpio_pads_i [3] + assign $0\builder_multiregimpl4_regs1[0:0] \builder_multiregimpl4_regs0 + assign $0\builder_multiregimpl5_regs0[0:0] \main_gpio_pads_i [4] + assign $0\builder_multiregimpl5_regs1[0:0] \builder_multiregimpl5_regs0 + assign $0\builder_multiregimpl6_regs0[0:0] \main_gpio_pads_i [5] + assign $0\builder_multiregimpl6_regs1[0:0] \builder_multiregimpl6_regs0 + assign $0\builder_multiregimpl7_regs0[0:0] \main_gpio_pads_i [6] + assign $0\builder_multiregimpl7_regs1[0:0] \builder_multiregimpl7_regs0 + assign $0\builder_multiregimpl8_regs0[0:0] \main_gpio_pads_i [7] + assign $0\builder_multiregimpl8_regs1[0:0] \builder_multiregimpl8_regs0 + assign $0\builder_multiregimpl9_regs0[0:0] \main_gpio_pads_i [8] + assign $0\builder_multiregimpl9_regs1[0:0] \builder_multiregimpl9_regs0 + assign $0\builder_multiregimpl10_regs0[0:0] \main_gpio_pads_i [9] + assign $0\builder_multiregimpl10_regs1[0:0] \builder_multiregimpl10_regs0 + assign $0\builder_multiregimpl11_regs0[0:0] \main_gpio_pads_i [10] + assign $0\builder_multiregimpl11_regs1[0:0] \builder_multiregimpl11_regs0 + assign $0\builder_multiregimpl12_regs0[0:0] \main_gpio_pads_i [11] + assign $0\builder_multiregimpl12_regs1[0:0] \builder_multiregimpl12_regs0 + assign $0\builder_multiregimpl13_regs0[0:0] \main_gpio_pads_i [12] + assign $0\builder_multiregimpl13_regs1[0:0] \builder_multiregimpl13_regs0 + assign $0\builder_multiregimpl14_regs0[0:0] \main_gpio_pads_i [13] + assign $0\builder_multiregimpl14_regs1[0:0] \builder_multiregimpl14_regs0 + assign $0\builder_multiregimpl15_regs0[0:0] \main_gpio_pads_i [14] + assign $0\builder_multiregimpl15_regs1[0:0] \builder_multiregimpl15_regs0 + assign $0\builder_multiregimpl16_regs0[0:0] \main_gpio_pads_i [15] + assign $0\builder_multiregimpl16_regs1[0:0] \builder_multiregimpl16_regs0 + attribute \src "ls180.v:7402.2-7404.5" + switch $or$ls180.v:7402$2401_Y + attribute \src "ls180.v:7402.6-7402.94" + case 1'1 + assign $0\main_libresocsim_converter0_dat_r[63:0] \main_libresocsim_libresoc_ibus_dat_r + case + end + attribute \src "ls180.v:7406.2-7408.5" + switch \main_libresocsim_converter0_counter_converter0_next_value_ce + attribute \src "ls180.v:7406.6-7406.66" + case 1'1 + assign $0\main_libresocsim_converter0_counter[0:0] \main_libresocsim_converter0_counter_converter0_next_value + case + end + attribute \src "ls180.v:7409.2-7412.5" + switch \main_libresocsim_converter0_reset + attribute \src "ls180.v:7409.6-7409.39" + case 1'1 + assign $0\main_libresocsim_converter0_counter[0:0] 1'0 + assign $0\builder_converter0_state[0:0] 1'0 + case + end + attribute \src "ls180.v:7413.2-7415.5" + switch $or$ls180.v:7413$2402_Y + attribute \src "ls180.v:7413.6-7413.94" + case 1'1 + assign $0\main_libresocsim_converter1_dat_r[63:0] \main_libresocsim_libresoc_dbus_dat_r + case + end + attribute \src "ls180.v:7417.2-7419.5" + switch \main_libresocsim_converter1_counter_converter1_next_value_ce + attribute \src "ls180.v:7417.6-7417.66" + case 1'1 + assign $0\main_libresocsim_converter1_counter[0:0] \main_libresocsim_converter1_counter_converter1_next_value + case + end + attribute \src "ls180.v:7420.2-7423.5" + switch \main_libresocsim_converter1_reset + attribute \src "ls180.v:7420.6-7420.39" + case 1'1 + assign $0\main_libresocsim_converter1_counter[0:0] 1'0 + assign $0\builder_converter1_state[0:0] 1'0 + case + end + attribute \src "ls180.v:7424.2-7426.5" + switch $or$ls180.v:7424$2403_Y + attribute \src "ls180.v:7424.6-7424.94" + case 1'1 + assign $0\main_libresocsim_converter2_dat_r[63:0] \main_libresocsim_libresoc_jtag_wb_dat_r + case + end + attribute \src "ls180.v:7428.2-7430.5" + switch \main_libresocsim_converter2_counter_converter2_next_value_ce + attribute \src "ls180.v:7428.6-7428.66" + case 1'1 + assign $0\main_libresocsim_converter2_counter[0:0] \main_libresocsim_converter2_counter_converter2_next_value + case + end + attribute \src "ls180.v:7431.2-7434.5" + switch \main_libresocsim_converter2_reset + attribute \src "ls180.v:7431.6-7431.39" + case 1'1 + assign $0\main_libresocsim_converter2_counter[0:0] 1'0 + assign $0\builder_converter2_state[0:0] 1'0 + case + end + attribute \src "ls180.v:7435.2-7439.5" + switch $ne$ls180.v:7435$2404_Y + attribute \src "ls180.v:7435.6-7435.53" + case 1'1 + attribute \src "ls180.v:7436.3-7438.6" + switch \main_libresocsim_bus_error + attribute \src "ls180.v:7436.7-7436.33" + case 1'1 + assign $0\main_libresocsim_bus_errors[31:0] $add$ls180.v:7437$2405_Y + case + end + case + end + attribute \src "ls180.v:7441.2-7443.5" + switch $and$ls180.v:7441$2408_Y + attribute \src "ls180.v:7441.6-7441.103" + case 1'1 + assign $0\main_libresocsim_ram_bus_ack[0:0] 1'1 + case + end + attribute \src "ls180.v:7444.2-7452.5" + switch \main_libresocsim_en_storage + attribute \src "ls180.v:7444.6-7444.33" + case 1'1 + attribute \src "ls180.v:7445.3-7449.6" + switch $eq$ls180.v:7445$2409_Y + attribute \src "ls180.v:7445.7-7445.39" + case 1'1 + assign $0\main_libresocsim_value[31:0] \main_libresocsim_reload_storage + attribute \src "ls180.v:7447.7-7447.11" + case + assign $0\main_libresocsim_value[31:0] $sub$ls180.v:7448$2410_Y + end + attribute \src "ls180.v:7450.6-7450.10" + case + assign $0\main_libresocsim_value[31:0] \main_libresocsim_load_storage + end + attribute \src "ls180.v:7453.2-7455.5" + switch \main_libresocsim_update_value_re + attribute \src "ls180.v:7453.6-7453.38" + case 1'1 + assign $0\main_libresocsim_value_status[31:0] \main_libresocsim_value + case + end + attribute \src "ls180.v:7456.2-7458.5" + switch \main_libresocsim_zero_clear + attribute \src "ls180.v:7456.6-7456.33" + case 1'1 + assign $0\main_libresocsim_zero_pending[0:0] 1'0 + case + end + attribute \src "ls180.v:7460.2-7462.5" + switch $and$ls180.v:7460$2412_Y + attribute \src "ls180.v:7460.6-7460.76" + case 1'1 + assign $0\main_libresocsim_zero_pending[0:0] 1'1 + case + end + attribute \src "ls180.v:7465.2-7467.5" + switch \main_sdram_inti_p0_rddata_valid + attribute \src "ls180.v:7465.6-7465.37" + case 1'1 + assign $0\main_sdram_status[15:0] \main_sdram_inti_p0_rddata + case + end + attribute \src "ls180.v:7468.2-7472.5" + switch $and$ls180.v:7468$2414_Y + attribute \src "ls180.v:7468.6-7468.57" + case 1'1 + assign $0\main_sdram_timer_count1[9:0] $sub$ls180.v:7469$2415_Y + attribute \src "ls180.v:7470.6-7470.10" + case + assign $0\main_sdram_timer_count1[9:0] 10'1100001101 + end + attribute \src "ls180.v:7474.2-7480.5" + switch \main_sdram_postponer_req_i + attribute \src "ls180.v:7474.6-7474.32" + case 1'1 + assign $0\main_sdram_postponer_count[0:0] $sub$ls180.v:7475$2416_Y + attribute \src "ls180.v:7476.3-7479.6" + switch $eq$ls180.v:7476$2417_Y + attribute \src "ls180.v:7476.7-7476.43" + case 1'1 + assign $0\main_sdram_postponer_count[0:0] 1'0 + assign $0\main_sdram_postponer_req_o[0:0] 1'1 + case + end + case + end + attribute \src "ls180.v:7481.2-7489.5" + switch \main_sdram_sequencer_start0 + attribute \src "ls180.v:7481.6-7481.33" + case 1'1 + assign $0\main_sdram_sequencer_count[0:0] 1'0 + attribute \src "ls180.v:7483.6-7483.10" + case + attribute \src "ls180.v:7484.3-7488.6" + switch \main_sdram_sequencer_done1 + attribute \src "ls180.v:7484.7-7484.33" + case 1'1 + attribute \src "ls180.v:7485.4-7487.7" + switch $ne$ls180.v:7485$2418_Y + attribute \src "ls180.v:7485.8-7485.44" + case 1'1 + assign $0\main_sdram_sequencer_count[0:0] $sub$ls180.v:7486$2419_Y + case + end + case + end + end + attribute \src "ls180.v:7496.2-7502.5" + switch $and$ls180.v:7496$2421_Y + attribute \src "ls180.v:7496.6-7496.76" + case 1'1 + assign $0\main_sdram_cmd_payload_a[12:0] 13'0010000000000 + assign $0\main_sdram_cmd_payload_ba[1:0] 2'00 + assign $0\main_sdram_cmd_payload_cas[0:0] 1'0 + assign $0\main_sdram_cmd_payload_ras[0:0] 1'1 + assign $0\main_sdram_cmd_payload_we[0:0] 1'1 + case + end + attribute \src "ls180.v:7503.2-7509.5" + switch $eq$ls180.v:7503$2422_Y + attribute \src "ls180.v:7503.6-7503.44" + case 1'1 + assign $0\main_sdram_cmd_payload_a[12:0] 13'0000000000000 + assign $0\main_sdram_cmd_payload_ba[1:0] 2'00 + assign $0\main_sdram_cmd_payload_cas[0:0] 1'1 + assign $0\main_sdram_cmd_payload_ras[0:0] 1'1 + assign $0\main_sdram_cmd_payload_we[0:0] 1'0 + case + end + attribute \src "ls180.v:7510.2-7517.5" + switch $eq$ls180.v:7510$2423_Y + attribute \src "ls180.v:7510.6-7510.44" + case 1'1 + assign $0\main_sdram_cmd_payload_a[12:0] 13'0000000000000 + assign $0\main_sdram_cmd_payload_ba[1:0] 2'00 + assign $0\main_sdram_cmd_payload_cas[0:0] 1'0 + assign $0\main_sdram_cmd_payload_ras[0:0] 1'0 + assign $0\main_sdram_cmd_payload_we[0:0] 1'0 + assign $0\main_sdram_sequencer_done1[0:0] 1'1 + case + end + attribute \src "ls180.v:7518.2-7528.5" + switch $eq$ls180.v:7518$2424_Y + attribute \src "ls180.v:7518.6-7518.44" + case 1'1 + assign $0\main_sdram_sequencer_counter[3:0] 4'0000 + attribute \src "ls180.v:7520.6-7520.10" + case + attribute \src "ls180.v:7521.3-7527.6" + switch $ne$ls180.v:7521$2425_Y + attribute \src "ls180.v:7521.7-7521.45" + case 1'1 + assign $0\main_sdram_sequencer_counter[3:0] $add$ls180.v:7522$2426_Y + attribute \src "ls180.v:7523.7-7523.11" + case + attribute \src "ls180.v:7524.4-7526.7" + switch \main_sdram_sequencer_start1 + attribute \src "ls180.v:7524.8-7524.35" + case 1'1 + assign $0\main_sdram_sequencer_counter[3:0] 4'0001 + case + end + end + end + attribute \src "ls180.v:7530.2-7537.5" + switch \main_sdram_bankmachine0_row_close + attribute \src "ls180.v:7530.6-7530.39" + case 1'1 + assign $0\main_sdram_bankmachine0_row_opened[0:0] 1'0 + attribute \src "ls180.v:7532.6-7532.10" + case + attribute \src "ls180.v:7533.3-7536.6" + switch \main_sdram_bankmachine0_row_open + attribute \src "ls180.v:7533.7-7533.39" + case 1'1 + assign $0\main_sdram_bankmachine0_row_opened[0:0] 1'1 + assign $0\main_sdram_bankmachine0_row[12:0] \main_sdram_bankmachine0_cmd_buffer_source_payload_addr [21:9] + case + end + end + attribute \src "ls180.v:7538.2-7540.5" + switch $and$ls180.v:7538$2429_Y + attribute \src "ls180.v:7538.6-7538.191" + case 1'1 + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7539$2430_Y + case + end + attribute \src "ls180.v:7541.2-7543.5" + switch \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read + attribute \src "ls180.v:7541.6-7541.58" + case 1'1 + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7542$2431_Y + case + end + attribute \src "ls180.v:7544.2-7552.5" + switch $and$ls180.v:7544$2434_Y + attribute \src "ls180.v:7544.6-7544.191" + case 1'1 + attribute \src "ls180.v:7545.3-7547.6" + switch $not$ls180.v:7545$2435_Y + attribute \src "ls180.v:7545.7-7545.62" + case 1'1 + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7546$2436_Y + case + end + attribute \src "ls180.v:7548.6-7548.10" + case + attribute \src "ls180.v:7549.3-7551.6" + switch \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read + attribute \src "ls180.v:7549.7-7549.59" + case 1'1 + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7550$2437_Y + case + end + end + attribute \src "ls180.v:7553.2-7559.5" + switch $or$ls180.v:7553$2439_Y + attribute \src "ls180.v:7553.6-7553.108" + case 1'1 + assign $0\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine0_cmd_buffer_sink_valid + assign $0\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] \main_sdram_bankmachine0_cmd_buffer_sink_first + assign $0\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] \main_sdram_bankmachine0_cmd_buffer_sink_last + assign $0\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] \main_sdram_bankmachine0_cmd_buffer_sink_payload_we + assign $0\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine0_cmd_buffer_sink_payload_addr + case + end + attribute \src "ls180.v:7560.2-7574.5" + switch \main_sdram_bankmachine0_twtpcon_valid + attribute \src "ls180.v:7560.6-7560.43" + case 1'1 + assign $0\main_sdram_bankmachine0_twtpcon_count[2:0] 3'100 + attribute \src "ls180.v:7562.3-7566.6" + switch 1'0 + attribute \src "ls180.v:7564.7-7564.11" + case + assign $0\main_sdram_bankmachine0_twtpcon_ready[0:0] 1'0 + end + attribute \src "ls180.v:7567.6-7567.10" + case + attribute \src "ls180.v:7568.3-7573.6" + switch $not$ls180.v:7568$2440_Y + attribute \src "ls180.v:7568.7-7568.47" + case 1'1 + assign $0\main_sdram_bankmachine0_twtpcon_count[2:0] $sub$ls180.v:7569$2441_Y + attribute \src "ls180.v:7570.4-7572.7" + switch $eq$ls180.v:7570$2442_Y + attribute \src "ls180.v:7570.8-7570.55" + case 1'1 + assign $0\main_sdram_bankmachine0_twtpcon_ready[0:0] 1'1 + case + end + case + end + end + attribute \src "ls180.v:7576.2-7583.5" + switch \main_sdram_bankmachine1_row_close + attribute \src "ls180.v:7576.6-7576.39" + case 1'1 + assign $0\main_sdram_bankmachine1_row_opened[0:0] 1'0 + attribute \src "ls180.v:7578.6-7578.10" + case + attribute \src "ls180.v:7579.3-7582.6" + switch \main_sdram_bankmachine1_row_open + attribute \src "ls180.v:7579.7-7579.39" + case 1'1 + assign $0\main_sdram_bankmachine1_row_opened[0:0] 1'1 + assign $0\main_sdram_bankmachine1_row[12:0] \main_sdram_bankmachine1_cmd_buffer_source_payload_addr [21:9] + case + end + end + attribute \src "ls180.v:7584.2-7586.5" + switch $and$ls180.v:7584$2445_Y + attribute \src "ls180.v:7584.6-7584.191" + case 1'1 + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7585$2446_Y + case + end + attribute \src "ls180.v:7587.2-7589.5" + switch \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read + attribute \src "ls180.v:7587.6-7587.58" + case 1'1 + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7588$2447_Y + case + end + attribute \src "ls180.v:7590.2-7598.5" + switch $and$ls180.v:7590$2450_Y + attribute \src "ls180.v:7590.6-7590.191" + case 1'1 + attribute \src "ls180.v:7591.3-7593.6" + switch $not$ls180.v:7591$2451_Y + attribute \src "ls180.v:7591.7-7591.62" + case 1'1 + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7592$2452_Y + case + end + attribute \src "ls180.v:7594.6-7594.10" + case + attribute \src "ls180.v:7595.3-7597.6" + switch \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read + attribute \src "ls180.v:7595.7-7595.59" + case 1'1 + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7596$2453_Y + case + end + end + attribute \src "ls180.v:7599.2-7605.5" + switch $or$ls180.v:7599$2455_Y + attribute \src "ls180.v:7599.6-7599.108" + case 1'1 + assign $0\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine1_cmd_buffer_sink_valid + assign $0\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] \main_sdram_bankmachine1_cmd_buffer_sink_first + assign $0\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] \main_sdram_bankmachine1_cmd_buffer_sink_last + assign $0\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] \main_sdram_bankmachine1_cmd_buffer_sink_payload_we + assign $0\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine1_cmd_buffer_sink_payload_addr + case + end + attribute \src "ls180.v:7606.2-7620.5" + switch \main_sdram_bankmachine1_twtpcon_valid + attribute \src "ls180.v:7606.6-7606.43" + case 1'1 + assign $0\main_sdram_bankmachine1_twtpcon_count[2:0] 3'100 + attribute \src "ls180.v:7608.3-7612.6" + switch 1'0 + attribute \src "ls180.v:7610.7-7610.11" + case + assign $0\main_sdram_bankmachine1_twtpcon_ready[0:0] 1'0 + end + attribute \src "ls180.v:7613.6-7613.10" + case + attribute \src "ls180.v:7614.3-7619.6" + switch $not$ls180.v:7614$2456_Y + attribute \src "ls180.v:7614.7-7614.47" + case 1'1 + assign $0\main_sdram_bankmachine1_twtpcon_count[2:0] $sub$ls180.v:7615$2457_Y + attribute \src "ls180.v:7616.4-7618.7" + switch $eq$ls180.v:7616$2458_Y + attribute \src "ls180.v:7616.8-7616.55" + case 1'1 + assign $0\main_sdram_bankmachine1_twtpcon_ready[0:0] 1'1 + case + end + case + end + end + attribute \src "ls180.v:7622.2-7629.5" + switch \main_sdram_bankmachine2_row_close + attribute \src "ls180.v:7622.6-7622.39" + case 1'1 + assign $0\main_sdram_bankmachine2_row_opened[0:0] 1'0 + attribute \src "ls180.v:7624.6-7624.10" + case + attribute \src "ls180.v:7625.3-7628.6" + switch \main_sdram_bankmachine2_row_open + attribute \src "ls180.v:7625.7-7625.39" + case 1'1 + assign $0\main_sdram_bankmachine2_row_opened[0:0] 1'1 + assign $0\main_sdram_bankmachine2_row[12:0] \main_sdram_bankmachine2_cmd_buffer_source_payload_addr [21:9] + case + end + end + attribute \src "ls180.v:7630.2-7632.5" + switch $and$ls180.v:7630$2461_Y + attribute \src "ls180.v:7630.6-7630.191" + case 1'1 + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7631$2462_Y + case + end + attribute \src "ls180.v:7633.2-7635.5" + switch \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read + attribute \src "ls180.v:7633.6-7633.58" + case 1'1 + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7634$2463_Y + case + end + attribute \src "ls180.v:7636.2-7644.5" + switch $and$ls180.v:7636$2466_Y + attribute \src "ls180.v:7636.6-7636.191" + case 1'1 + attribute \src "ls180.v:7637.3-7639.6" + switch $not$ls180.v:7637$2467_Y + attribute \src "ls180.v:7637.7-7637.62" + case 1'1 + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7638$2468_Y + case + end + attribute \src "ls180.v:7640.6-7640.10" + case + attribute \src "ls180.v:7641.3-7643.6" + switch \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read + attribute \src "ls180.v:7641.7-7641.59" + case 1'1 + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7642$2469_Y + case + end + end + attribute \src "ls180.v:7645.2-7651.5" + switch $or$ls180.v:7645$2471_Y + attribute \src "ls180.v:7645.6-7645.108" + case 1'1 + assign $0\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine2_cmd_buffer_sink_valid + assign $0\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] \main_sdram_bankmachine2_cmd_buffer_sink_first + assign $0\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] \main_sdram_bankmachine2_cmd_buffer_sink_last + assign $0\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] \main_sdram_bankmachine2_cmd_buffer_sink_payload_we + assign $0\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine2_cmd_buffer_sink_payload_addr + case + end + attribute \src "ls180.v:7652.2-7666.5" + switch \main_sdram_bankmachine2_twtpcon_valid + attribute \src "ls180.v:7652.6-7652.43" + case 1'1 + assign $0\main_sdram_bankmachine2_twtpcon_count[2:0] 3'100 + attribute \src "ls180.v:7654.3-7658.6" + switch 1'0 + attribute \src "ls180.v:7656.7-7656.11" + case + assign $0\main_sdram_bankmachine2_twtpcon_ready[0:0] 1'0 + end + attribute \src "ls180.v:7659.6-7659.10" + case + attribute \src "ls180.v:7660.3-7665.6" + switch $not$ls180.v:7660$2472_Y + attribute \src "ls180.v:7660.7-7660.47" + case 1'1 + assign $0\main_sdram_bankmachine2_twtpcon_count[2:0] $sub$ls180.v:7661$2473_Y + attribute \src "ls180.v:7662.4-7664.7" + switch $eq$ls180.v:7662$2474_Y + attribute \src "ls180.v:7662.8-7662.55" + case 1'1 + assign $0\main_sdram_bankmachine2_twtpcon_ready[0:0] 1'1 + case + end + case + end + end + attribute \src "ls180.v:7668.2-7675.5" + switch \main_sdram_bankmachine3_row_close + attribute \src "ls180.v:7668.6-7668.39" + case 1'1 + assign $0\main_sdram_bankmachine3_row_opened[0:0] 1'0 + attribute \src "ls180.v:7670.6-7670.10" + case + attribute \src "ls180.v:7671.3-7674.6" + switch \main_sdram_bankmachine3_row_open + attribute \src "ls180.v:7671.7-7671.39" + case 1'1 + assign $0\main_sdram_bankmachine3_row_opened[0:0] 1'1 + assign $0\main_sdram_bankmachine3_row[12:0] \main_sdram_bankmachine3_cmd_buffer_source_payload_addr [21:9] + case + end + end + attribute \src "ls180.v:7676.2-7678.5" + switch $and$ls180.v:7676$2477_Y + attribute \src "ls180.v:7676.6-7676.191" + case 1'1 + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7677$2478_Y + case + end + attribute \src "ls180.v:7679.2-7681.5" + switch \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read + attribute \src "ls180.v:7679.6-7679.58" + case 1'1 + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7680$2479_Y + case + end + attribute \src "ls180.v:7682.2-7690.5" + switch $and$ls180.v:7682$2482_Y + attribute \src "ls180.v:7682.6-7682.191" + case 1'1 + attribute \src "ls180.v:7683.3-7685.6" + switch $not$ls180.v:7683$2483_Y + attribute \src "ls180.v:7683.7-7683.62" + case 1'1 + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7684$2484_Y + case + end + attribute \src "ls180.v:7686.6-7686.10" + case + attribute \src "ls180.v:7687.3-7689.6" + switch \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read + attribute \src "ls180.v:7687.7-7687.59" + case 1'1 + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7688$2485_Y + case + end + end + attribute \src "ls180.v:7691.2-7697.5" + switch $or$ls180.v:7691$2487_Y + attribute \src "ls180.v:7691.6-7691.108" + case 1'1 + assign $0\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine3_cmd_buffer_sink_valid + assign $0\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] \main_sdram_bankmachine3_cmd_buffer_sink_first + assign $0\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] \main_sdram_bankmachine3_cmd_buffer_sink_last + assign $0\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] \main_sdram_bankmachine3_cmd_buffer_sink_payload_we + assign $0\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine3_cmd_buffer_sink_payload_addr + case + end + attribute \src "ls180.v:7698.2-7712.5" + switch \main_sdram_bankmachine3_twtpcon_valid + attribute \src "ls180.v:7698.6-7698.43" + case 1'1 + assign $0\main_sdram_bankmachine3_twtpcon_count[2:0] 3'100 + attribute \src "ls180.v:7700.3-7704.6" + switch 1'0 + attribute \src "ls180.v:7702.7-7702.11" + case + assign $0\main_sdram_bankmachine3_twtpcon_ready[0:0] 1'0 + end + attribute \src "ls180.v:7705.6-7705.10" + case + attribute \src "ls180.v:7706.3-7711.6" + switch $not$ls180.v:7706$2488_Y + attribute \src "ls180.v:7706.7-7706.47" + case 1'1 + assign $0\main_sdram_bankmachine3_twtpcon_count[2:0] $sub$ls180.v:7707$2489_Y + attribute \src "ls180.v:7708.4-7710.7" + switch $eq$ls180.v:7708$2490_Y + attribute \src "ls180.v:7708.8-7708.55" + case 1'1 + assign $0\main_sdram_bankmachine3_twtpcon_ready[0:0] 1'1 + case + end + case + end + end + attribute \src "ls180.v:7714.2-7720.5" + switch $not$ls180.v:7714$2491_Y + attribute \src "ls180.v:7714.6-7714.23" + case 1'1 + assign $0\main_sdram_time0[4:0] 5'11111 + attribute \src "ls180.v:7716.6-7716.10" + case + attribute \src "ls180.v:7717.3-7719.6" + switch $not$ls180.v:7717$2492_Y + attribute \src "ls180.v:7717.7-7717.30" + case 1'1 + assign $0\main_sdram_time0[4:0] $sub$ls180.v:7718$2493_Y + case + end + end + attribute \src "ls180.v:7721.2-7727.5" + switch $not$ls180.v:7721$2494_Y + attribute \src "ls180.v:7721.6-7721.23" + case 1'1 + assign $0\main_sdram_time1[3:0] 4'1111 + attribute \src "ls180.v:7723.6-7723.10" + case + attribute \src "ls180.v:7724.3-7726.6" + switch $not$ls180.v:7724$2495_Y + attribute \src "ls180.v:7724.7-7724.30" + case 1'1 + assign $0\main_sdram_time1[3:0] $sub$ls180.v:7725$2496_Y + case + end + end + attribute \src "ls180.v:7728.2-7783.5" + switch \main_sdram_choose_cmd_ce + attribute \src "ls180.v:7728.6-7728.30" + case 1'1 + attribute \src "ls180.v:7729.3-7782.10" + switch \main_sdram_choose_cmd_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + attribute \src "ls180.v:7731.5-7741.8" + switch \main_sdram_choose_cmd_request [1] + attribute \src "ls180.v:7731.9-7731.41" + case 1'1 + assign $0\main_sdram_choose_cmd_grant[1:0] 2'01 + attribute \src "ls180.v:7733.9-7733.13" + case + attribute \src "ls180.v:7734.6-7740.9" + switch \main_sdram_choose_cmd_request [2] + attribute \src "ls180.v:7734.10-7734.42" + case 1'1 + assign $0\main_sdram_choose_cmd_grant[1:0] 2'10 + attribute \src "ls180.v:7736.10-7736.14" + case + attribute \src "ls180.v:7737.7-7739.10" + switch \main_sdram_choose_cmd_request [3] + attribute \src "ls180.v:7737.11-7737.43" + case 1'1 + assign $0\main_sdram_choose_cmd_grant[1:0] 2'11 + case + end + end + end + attribute \src "ls180.v:0.0-0.0" + case 2'01 + attribute \src "ls180.v:7744.5-7754.8" + switch \main_sdram_choose_cmd_request [2] + attribute \src "ls180.v:7744.9-7744.41" + case 1'1 + assign $0\main_sdram_choose_cmd_grant[1:0] 2'10 + attribute \src "ls180.v:7746.9-7746.13" + case + attribute \src "ls180.v:7747.6-7753.9" + switch \main_sdram_choose_cmd_request [3] + attribute \src "ls180.v:7747.10-7747.42" + case 1'1 + assign $0\main_sdram_choose_cmd_grant[1:0] 2'11 + attribute \src "ls180.v:7749.10-7749.14" + case + attribute \src "ls180.v:7750.7-7752.10" + switch \main_sdram_choose_cmd_request [0] + attribute \src "ls180.v:7750.11-7750.43" + case 1'1 + assign $0\main_sdram_choose_cmd_grant[1:0] 2'00 + case + end + end + end + attribute \src "ls180.v:0.0-0.0" + case 2'10 + attribute \src "ls180.v:7757.5-7767.8" + switch \main_sdram_choose_cmd_request [3] + attribute \src "ls180.v:7757.9-7757.41" + case 1'1 + assign $0\main_sdram_choose_cmd_grant[1:0] 2'11 + attribute \src "ls180.v:7759.9-7759.13" + case + attribute \src "ls180.v:7760.6-7766.9" + switch \main_sdram_choose_cmd_request [0] + attribute \src "ls180.v:7760.10-7760.42" + case 1'1 + assign $0\main_sdram_choose_cmd_grant[1:0] 2'00 + attribute \src "ls180.v:7762.10-7762.14" + case + attribute \src "ls180.v:7763.7-7765.10" + switch \main_sdram_choose_cmd_request [1] + attribute \src "ls180.v:7763.11-7763.43" + case 1'1 + assign $0\main_sdram_choose_cmd_grant[1:0] 2'01 + case + end + end + end + attribute \src "ls180.v:0.0-0.0" + case 2'11 + attribute \src "ls180.v:7770.5-7780.8" + switch \main_sdram_choose_cmd_request [0] + attribute \src "ls180.v:7770.9-7770.41" + case 1'1 + assign $0\main_sdram_choose_cmd_grant[1:0] 2'00 + attribute \src "ls180.v:7772.9-7772.13" + case + attribute \src "ls180.v:7773.6-7779.9" + switch \main_sdram_choose_cmd_request [1] + attribute \src "ls180.v:7773.10-7773.42" + case 1'1 + assign $0\main_sdram_choose_cmd_grant[1:0] 2'01 + attribute \src "ls180.v:7775.10-7775.14" + case + attribute \src "ls180.v:7776.7-7778.10" + switch \main_sdram_choose_cmd_request [2] + attribute \src "ls180.v:7776.11-7776.43" + case 1'1 + assign $0\main_sdram_choose_cmd_grant[1:0] 2'10 + case + end + end + end + case + end + case + end + attribute \src "ls180.v:7784.2-7839.5" + switch \main_sdram_choose_req_ce + attribute \src "ls180.v:7784.6-7784.30" + case 1'1 + attribute \src "ls180.v:7785.3-7838.10" + switch \main_sdram_choose_req_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + attribute \src "ls180.v:7787.5-7797.8" + switch \main_sdram_choose_req_request [1] + attribute \src "ls180.v:7787.9-7787.41" + case 1'1 + assign $0\main_sdram_choose_req_grant[1:0] 2'01 + attribute \src "ls180.v:7789.9-7789.13" + case + attribute \src "ls180.v:7790.6-7796.9" + switch \main_sdram_choose_req_request [2] + attribute \src "ls180.v:7790.10-7790.42" + case 1'1 + assign $0\main_sdram_choose_req_grant[1:0] 2'10 + attribute \src "ls180.v:7792.10-7792.14" + case + attribute \src "ls180.v:7793.7-7795.10" + switch \main_sdram_choose_req_request [3] + attribute \src "ls180.v:7793.11-7793.43" + case 1'1 + assign $0\main_sdram_choose_req_grant[1:0] 2'11 + case + end + end + end + attribute \src "ls180.v:0.0-0.0" + case 2'01 + attribute \src "ls180.v:7800.5-7810.8" + switch \main_sdram_choose_req_request [2] + attribute \src "ls180.v:7800.9-7800.41" + case 1'1 + assign $0\main_sdram_choose_req_grant[1:0] 2'10 + attribute \src "ls180.v:7802.9-7802.13" + case + attribute \src "ls180.v:7803.6-7809.9" + switch \main_sdram_choose_req_request [3] + attribute \src "ls180.v:7803.10-7803.42" + case 1'1 + assign $0\main_sdram_choose_req_grant[1:0] 2'11 + attribute \src "ls180.v:7805.10-7805.14" + case + attribute \src "ls180.v:7806.7-7808.10" + switch \main_sdram_choose_req_request [0] + attribute \src "ls180.v:7806.11-7806.43" + case 1'1 + assign $0\main_sdram_choose_req_grant[1:0] 2'00 + case + end + end + end + attribute \src "ls180.v:0.0-0.0" + case 2'10 + attribute \src "ls180.v:7813.5-7823.8" + switch \main_sdram_choose_req_request [3] + attribute \src "ls180.v:7813.9-7813.41" + case 1'1 + assign $0\main_sdram_choose_req_grant[1:0] 2'11 + attribute \src "ls180.v:7815.9-7815.13" + case + attribute \src "ls180.v:7816.6-7822.9" + switch \main_sdram_choose_req_request [0] + attribute \src "ls180.v:7816.10-7816.42" + case 1'1 + assign $0\main_sdram_choose_req_grant[1:0] 2'00 + attribute \src "ls180.v:7818.10-7818.14" + case + attribute \src "ls180.v:7819.7-7821.10" + switch \main_sdram_choose_req_request [1] + attribute \src "ls180.v:7819.11-7819.43" + case 1'1 + assign $0\main_sdram_choose_req_grant[1:0] 2'01 + case + end + end + end + attribute \src "ls180.v:0.0-0.0" + case 2'11 + attribute \src "ls180.v:7826.5-7836.8" + switch \main_sdram_choose_req_request [0] + attribute \src "ls180.v:7826.9-7826.41" + case 1'1 + assign $0\main_sdram_choose_req_grant[1:0] 2'00 + attribute \src "ls180.v:7828.9-7828.13" + case + attribute \src "ls180.v:7829.6-7835.9" + switch \main_sdram_choose_req_request [1] + attribute \src "ls180.v:7829.10-7829.42" + case 1'1 + assign $0\main_sdram_choose_req_grant[1:0] 2'01 + attribute \src "ls180.v:7831.10-7831.14" + case + attribute \src "ls180.v:7832.7-7834.10" + switch \main_sdram_choose_req_request [2] + attribute \src "ls180.v:7832.11-7832.43" + case 1'1 + assign $0\main_sdram_choose_req_grant[1:0] 2'10 + case + end + end + end + case + end + case + end + attribute \src "ls180.v:7848.2-7862.5" + switch \main_sdram_tccdcon_valid + attribute \src "ls180.v:7848.6-7848.30" + case 1'1 + assign $0\main_sdram_tccdcon_count[0:0] 1'0 + attribute \src "ls180.v:7850.3-7854.6" + switch 1'1 + attribute \src "ls180.v:7850.7-7850.11" + case 1'1 + assign $0\main_sdram_tccdcon_ready[0:0] 1'1 + case + end + attribute \src "ls180.v:7855.6-7855.10" + case + attribute \src "ls180.v:7856.3-7861.6" + switch $not$ls180.v:7856$2500_Y + attribute \src "ls180.v:7856.7-7856.34" + case 1'1 + assign $0\main_sdram_tccdcon_count[0:0] $sub$ls180.v:7857$2501_Y + attribute \src "ls180.v:7858.4-7860.7" + switch $eq$ls180.v:7858$2502_Y + attribute \src "ls180.v:7858.8-7858.42" + case 1'1 + assign $0\main_sdram_tccdcon_ready[0:0] 1'1 + case + end + case + end + end + attribute \src "ls180.v:7863.2-7877.5" + switch \main_sdram_twtrcon_valid + attribute \src "ls180.v:7863.6-7863.30" + case 1'1 + assign $0\main_sdram_twtrcon_count[2:0] 3'100 + attribute \src "ls180.v:7865.3-7869.6" + switch 1'0 + attribute \src "ls180.v:7867.7-7867.11" + case + assign $0\main_sdram_twtrcon_ready[0:0] 1'0 + end + attribute \src "ls180.v:7870.6-7870.10" + case + attribute \src "ls180.v:7871.3-7876.6" + switch $not$ls180.v:7871$2503_Y + attribute \src "ls180.v:7871.7-7871.34" + case 1'1 + assign $0\main_sdram_twtrcon_count[2:0] $sub$ls180.v:7872$2504_Y + attribute \src "ls180.v:7873.4-7875.7" + switch $eq$ls180.v:7873$2505_Y + attribute \src "ls180.v:7873.8-7873.42" + case 1'1 + assign $0\main_sdram_twtrcon_ready[0:0] 1'1 + case + end + case + end + end + attribute \src "ls180.v:7884.2-7886.5" + switch $or$ls180.v:7884$2530_Y + attribute \src "ls180.v:7884.6-7884.50" + case 1'1 + assign $0\main_converter_dat_r[31:0] \main_wb_sdram_dat_r + case + end + attribute \src "ls180.v:7888.2-7890.5" + switch \main_converter_counter_converter_next_value_ce + attribute \src "ls180.v:7888.6-7888.52" + case 1'1 + assign $0\main_converter_counter[0:0] \main_converter_counter_converter_next_value + case + end + attribute \src "ls180.v:7891.2-7894.5" + switch \main_converter_reset + attribute \src "ls180.v:7891.6-7891.26" + case 1'1 + assign $0\main_converter_counter[0:0] 1'0 + assign $0\builder_converter_state[0:0] 1'0 + case + end + attribute \src "ls180.v:7895.2-7905.5" + switch \main_litedram_wb_ack + attribute \src "ls180.v:7895.6-7895.26" + case 1'1 + assign $0\main_cmd_consumed[0:0] 1'0 + assign $0\main_wdata_consumed[0:0] 1'0 + attribute \src "ls180.v:7898.6-7898.10" + case + attribute \src "ls180.v:7899.3-7901.6" + switch $and$ls180.v:7899$2531_Y + attribute \src "ls180.v:7899.7-7899.50" + case 1'1 + assign $0\main_cmd_consumed[0:0] 1'1 + case + end + attribute \src "ls180.v:7902.3-7904.6" + switch $and$ls180.v:7902$2532_Y + attribute \src "ls180.v:7902.7-7902.54" + case 1'1 + assign $0\main_wdata_consumed[0:0] 1'1 + case + end + end + attribute \src "ls180.v:7907.2-7928.5" + switch $and$ls180.v:7907$2536_Y + attribute \src "ls180.v:7907.6-7907.64" + case 1'1 + assign $0\main_tx_reg[7:0] \main_sink_payload_data + assign $0\main_tx_bitcount[3:0] 4'0000 + assign $0\main_tx_busy[0:0] 1'1 + assign $0\main_libresocsim_libresoc_constraintmanager0_uart0_tx[0:0] 1'0 + attribute \src "ls180.v:7912.6-7912.10" + case + attribute \src "ls180.v:7913.3-7927.6" + switch $and$ls180.v:7913$2537_Y + attribute \src "ls180.v:7913.7-7913.42" + case 1'1 + assign $0\main_tx_bitcount[3:0] $add$ls180.v:7914$2538_Y + attribute \src "ls180.v:7915.4-7926.7" + switch $eq$ls180.v:7915$2539_Y + attribute \src "ls180.v:7915.8-7915.34" + case 1'1 + assign $0\main_libresocsim_libresoc_constraintmanager0_uart0_tx[0:0] 1'1 + attribute \src "ls180.v:7917.8-7917.12" + case + attribute \src "ls180.v:7918.5-7925.8" + switch $eq$ls180.v:7918$2540_Y + attribute \src "ls180.v:7918.9-7918.35" + case 1'1 + assign $0\main_libresocsim_libresoc_constraintmanager0_uart0_tx[0:0] 1'1 + assign $0\main_tx_busy[0:0] 1'0 + assign $0\main_sink_ready[0:0] 1'1 + attribute \src "ls180.v:7922.9-7922.13" + case + assign $0\main_libresocsim_libresoc_constraintmanager0_uart0_tx[0:0] \main_tx_reg [0] + assign $0\main_tx_reg[7:0] { 1'0 \main_tx_reg [7:1] } + end + end + case + end + end + attribute \src "ls180.v:7929.2-7933.5" + switch \main_tx_busy + attribute \src "ls180.v:7929.6-7929.18" + case 1'1 + assign { $0\main_uart_clk_txen[0:0] $0\main_phase_accumulator_tx[31:0] } $add$ls180.v:7930$2541_Y + attribute \src "ls180.v:7931.6-7931.10" + case + assign { $0\main_uart_clk_txen[0:0] $0\main_phase_accumulator_tx[31:0] } { 1'0 \main_storage } + end + attribute \src "ls180.v:7936.2-7960.5" + switch $not$ls180.v:7936$2542_Y + attribute \src "ls180.v:7936.6-7936.21" + case 1'1 + attribute \src "ls180.v:7937.3-7940.6" + switch $and$ls180.v:7937$2544_Y + attribute \src "ls180.v:7937.7-7937.31" + case 1'1 + assign $0\main_rx_busy[0:0] 1'1 + assign $0\main_rx_bitcount[3:0] 4'0000 + case + end + attribute \src "ls180.v:7941.6-7941.10" + case + attribute \src "ls180.v:7942.3-7959.6" + switch \main_uart_clk_rxen + attribute \src "ls180.v:7942.7-7942.25" + case 1'1 + assign $0\main_rx_bitcount[3:0] $add$ls180.v:7943$2545_Y + attribute \src "ls180.v:7944.4-7958.7" + switch $eq$ls180.v:7944$2546_Y + attribute \src "ls180.v:7944.8-7944.34" + case 1'1 + attribute \src "ls180.v:7945.5-7947.8" + switch \main_rx + attribute \src "ls180.v:7945.9-7945.16" + case 1'1 + assign $0\main_rx_busy[0:0] 1'0 + case + end + attribute \src "ls180.v:7948.8-7948.12" + case + attribute \src "ls180.v:7949.5-7957.8" + switch $eq$ls180.v:7949$2547_Y + attribute \src "ls180.v:7949.9-7949.35" + case 1'1 + assign $0\main_rx_busy[0:0] 1'0 + attribute \src "ls180.v:7951.6-7954.9" + switch \main_rx + attribute \src "ls180.v:7951.10-7951.17" + case 1'1 + assign $0\main_source_payload_data[7:0] \main_rx_reg + assign $0\main_source_valid[0:0] 1'1 + case + end + attribute \src "ls180.v:7955.9-7955.13" + case + assign $0\main_rx_reg[7:0] { \main_rx \main_rx_reg [7:1] } + end + end + case + end + end + attribute \src "ls180.v:7961.2-7965.5" + switch \main_rx_busy + attribute \src "ls180.v:7961.6-7961.18" + case 1'1 + assign { $0\main_uart_clk_rxen[0:0] $0\main_phase_accumulator_rx[31:0] } $add$ls180.v:7962$2548_Y + attribute \src "ls180.v:7963.6-7963.10" + case + assign { $0\main_uart_clk_rxen[0:0] $0\main_phase_accumulator_rx[31:0] } 33'010000000000000000000000000000000 + end + attribute \src "ls180.v:7966.2-7968.5" + switch \main_uart_tx_clear + attribute \src "ls180.v:7966.6-7966.24" + case 1'1 + assign $0\main_uart_tx_pending[0:0] 1'0 + case + end + attribute \src "ls180.v:7970.2-7972.5" + switch $and$ls180.v:7970$2550_Y + attribute \src "ls180.v:7970.6-7970.58" + case 1'1 + assign $0\main_uart_tx_pending[0:0] 1'1 + case + end + attribute \src "ls180.v:7973.2-7975.5" + switch \main_uart_rx_clear + attribute \src "ls180.v:7973.6-7973.24" + case 1'1 + assign $0\main_uart_rx_pending[0:0] 1'0 + case + end + attribute \src "ls180.v:7977.2-7979.5" + switch $and$ls180.v:7977$2552_Y + attribute \src "ls180.v:7977.6-7977.58" + case 1'1 + assign $0\main_uart_rx_pending[0:0] 1'1 + case + end + attribute \src "ls180.v:7980.2-7986.5" + switch \main_uart_tx_fifo_syncfifo_re + attribute \src "ls180.v:7980.6-7980.35" + case 1'1 + assign $0\main_uart_tx_fifo_readable[0:0] 1'1 + attribute \src "ls180.v:7982.6-7982.10" + case + attribute \src "ls180.v:7983.3-7985.6" + switch \main_uart_tx_fifo_re + attribute \src "ls180.v:7983.7-7983.27" + case 1'1 + assign $0\main_uart_tx_fifo_readable[0:0] 1'0 + case + end + end + attribute \src "ls180.v:7987.2-7989.5" + switch $and$ls180.v:7987$2555_Y + attribute \src "ls180.v:7987.6-7987.108" + case 1'1 + assign $0\main_uart_tx_fifo_produce[3:0] $add$ls180.v:7988$2556_Y + case + end + attribute \src "ls180.v:7990.2-7992.5" + switch \main_uart_tx_fifo_do_read + attribute \src "ls180.v:7990.6-7990.31" + case 1'1 + assign $0\main_uart_tx_fifo_consume[3:0] $add$ls180.v:7991$2557_Y + case + end + attribute \src "ls180.v:7993.2-8001.5" + switch $and$ls180.v:7993$2560_Y + attribute \src "ls180.v:7993.6-7993.108" + case 1'1 + attribute \src "ls180.v:7994.3-7996.6" + switch $not$ls180.v:7994$2561_Y + attribute \src "ls180.v:7994.7-7994.35" + case 1'1 + assign $0\main_uart_tx_fifo_level0[4:0] $add$ls180.v:7995$2562_Y + case + end + attribute \src "ls180.v:7997.6-7997.10" + case + attribute \src "ls180.v:7998.3-8000.6" + switch \main_uart_tx_fifo_do_read + attribute \src "ls180.v:7998.7-7998.32" + case 1'1 + assign $0\main_uart_tx_fifo_level0[4:0] $sub$ls180.v:7999$2563_Y + case + end + end + attribute \src "ls180.v:8002.2-8008.5" + switch \main_uart_rx_fifo_syncfifo_re + attribute \src "ls180.v:8002.6-8002.35" + case 1'1 + assign $0\main_uart_rx_fifo_readable[0:0] 1'1 + attribute \src "ls180.v:8004.6-8004.10" + case + attribute \src "ls180.v:8005.3-8007.6" + switch \main_uart_rx_fifo_re + attribute \src "ls180.v:8005.7-8005.27" + case 1'1 + assign $0\main_uart_rx_fifo_readable[0:0] 1'0 + case + end + end + attribute \src "ls180.v:8009.2-8011.5" + switch $and$ls180.v:8009$2566_Y + attribute \src "ls180.v:8009.6-8009.108" + case 1'1 + assign $0\main_uart_rx_fifo_produce[3:0] $add$ls180.v:8010$2567_Y + case + end + attribute \src "ls180.v:8012.2-8014.5" + switch \main_uart_rx_fifo_do_read + attribute \src "ls180.v:8012.6-8012.31" + case 1'1 + assign $0\main_uart_rx_fifo_consume[3:0] $add$ls180.v:8013$2568_Y + case + end + attribute \src "ls180.v:8015.2-8023.5" + switch $and$ls180.v:8015$2571_Y + attribute \src "ls180.v:8015.6-8015.108" + case 1'1 + attribute \src "ls180.v:8016.3-8018.6" + switch $not$ls180.v:8016$2572_Y + attribute \src "ls180.v:8016.7-8016.35" + case 1'1 + assign $0\main_uart_rx_fifo_level0[4:0] $add$ls180.v:8017$2573_Y + case + end + attribute \src "ls180.v:8019.6-8019.10" + case + attribute \src "ls180.v:8020.3-8022.6" + switch \main_uart_rx_fifo_do_read + attribute \src "ls180.v:8020.7-8020.32" + case 1'1 + assign $0\main_uart_rx_fifo_level0[4:0] $sub$ls180.v:8021$2574_Y + case + end + end + attribute \src "ls180.v:8024.2-8037.5" + switch \main_uart_reset + attribute \src "ls180.v:8024.6-8024.21" + case 1'1 + assign $0\main_uart_tx_pending[0:0] 1'0 + assign $0\main_uart_tx_old_trigger[0:0] 1'0 + assign $0\main_uart_rx_pending[0:0] 1'0 + assign $0\main_uart_rx_old_trigger[0:0] 1'0 + assign $0\main_uart_tx_fifo_readable[0:0] 1'0 + assign $0\main_uart_tx_fifo_level0[4:0] 5'00000 + assign $0\main_uart_tx_fifo_produce[3:0] 4'0000 + assign $0\main_uart_tx_fifo_consume[3:0] 4'0000 + assign $0\main_uart_rx_fifo_readable[0:0] 1'0 + assign $0\main_uart_rx_fifo_level0[4:0] 5'00000 + assign $0\main_uart_rx_fifo_produce[3:0] 4'0000 + assign $0\main_uart_rx_fifo_consume[3:0] 4'0000 + case + end + attribute \src "ls180.v:8039.2-8046.5" + switch \main_spi_master_clk_rise + attribute \src "ls180.v:8039.6-8039.30" + case 1'1 + assign $0\spi_master_clk[0:0] \main_spi_master_clk_enable + attribute \src "ls180.v:8041.6-8041.10" + case + attribute \src "ls180.v:8042.3-8045.6" + switch \main_spi_master_clk_fall + attribute \src "ls180.v:8042.7-8042.31" + case 1'1 + assign $0\main_spi_master_clk_divider1[15:0] 16'0000000000000000 + assign $0\spi_master_clk[0:0] 1'0 + case + end + end + attribute \src "ls180.v:8048.2-8058.5" + switch \main_spi_master_mosi_latch + attribute \src "ls180.v:8048.6-8048.32" + case 1'1 + assign $0\main_spi_master_mosi_data[7:0] \main_spi_master_mosi + assign $0\main_spi_master_mosi_sel[2:0] 3'111 + attribute \src "ls180.v:8051.6-8051.10" + case + attribute \src "ls180.v:8052.3-8057.6" + switch \main_spi_master_clk_fall + attribute \src "ls180.v:8052.7-8052.31" + case 1'1 + assign $0\main_spi_master_mosi_sel[2:0] $sub$ls180.v:8056$2579_Y + attribute \src "ls180.v:8053.4-8055.7" + switch \main_spi_master_cs_enable + attribute \src "ls180.v:8053.8-8053.33" + case 1'1 + assign $0\spi_master_mosi[0:0] \builder_sync_f_array_muxed0 + case + end + case + end + end + attribute \src "ls180.v:8059.2-8065.5" + switch \main_spi_master_clk_rise + attribute \src "ls180.v:8059.6-8059.30" + case 1'1 + attribute \src "ls180.v:8060.3-8064.6" + switch \main_spi_master_loopback + attribute \src "ls180.v:8060.7-8060.31" + case 1'1 + assign $0\main_spi_master_miso_data[7:0] { \main_spi_master_miso_data [6:0] \spi_master_mosi } + attribute \src "ls180.v:8062.7-8062.11" + case + assign $0\main_spi_master_miso_data[7:0] { \main_spi_master_miso_data [6:0] \spi_master_miso } + end + case + end + attribute \src "ls180.v:8066.2-8068.5" + switch \main_spi_master_miso_latch + attribute \src "ls180.v:8066.6-8066.32" + case 1'1 + assign $0\main_spi_master_miso[7:0] \main_spi_master_miso_data + case + end + attribute \src "ls180.v:8070.2-8072.5" + switch \main_spi_master_count_spimaster0_next_value_ce + attribute \src "ls180.v:8070.6-8070.52" + case 1'1 + assign $0\main_spi_master_count[2:0] \main_spi_master_count_spimaster0_next_value + case + end + attribute \src "ls180.v:8073.2-8086.5" + switch \main_pwm0_enable + attribute \src "ls180.v:8073.6-8073.22" + case 1'1 + assign $0\main_pwm0_counter[31:0] $add$ls180.v:8074$2580_Y + attribute \src "ls180.v:8075.3-8079.6" + switch $lt$ls180.v:8075$2581_Y + attribute \src "ls180.v:8075.7-8075.44" + case 1'1 + assign $0\pwm0[0:0] 1'1 + attribute \src "ls180.v:8077.7-8077.11" + case + assign $0\pwm0[0:0] 1'0 + end + attribute \src "ls180.v:8080.3-8082.6" + switch $ge$ls180.v:8080$2583_Y + attribute \src "ls180.v:8080.7-8080.55" + case 1'1 + assign $0\main_pwm0_counter[31:0] 0 + case + end + attribute \src "ls180.v:8083.6-8083.10" + case + assign $0\main_pwm0_counter[31:0] 0 + assign $0\pwm0[0:0] 1'0 + end + attribute \src "ls180.v:8087.2-8100.5" + switch \main_pwm1_enable + attribute \src "ls180.v:8087.6-8087.22" + case 1'1 + assign $0\main_pwm1_counter[31:0] $add$ls180.v:8088$2584_Y + attribute \src "ls180.v:8089.3-8093.6" + switch $lt$ls180.v:8089$2585_Y + attribute \src "ls180.v:8089.7-8089.44" + case 1'1 + assign $0\pwm1[0:0] 1'1 + attribute \src "ls180.v:8091.7-8091.11" + case + assign $0\pwm1[0:0] 1'0 + end + attribute \src "ls180.v:8094.3-8096.6" + switch $ge$ls180.v:8094$2587_Y + attribute \src "ls180.v:8094.7-8094.55" + case 1'1 + assign $0\main_pwm1_counter[31:0] 0 + case + end + attribute \src "ls180.v:8097.6-8097.10" + case + assign $0\main_pwm1_counter[31:0] 0 + assign $0\pwm1[0:0] 1'0 + end + attribute \src "ls180.v:8101.2-8103.5" + switch $not$ls180.v:8101$2588_Y + attribute \src "ls180.v:8101.6-8101.32" + case 1'1 + assign $0\main_sdphy_clocker_clks[8:0] $add$ls180.v:8102$2589_Y + case + end + attribute \src "ls180.v:8107.2-8109.5" + switch \main_sdphy_init_count_sdphy_sdphyinit_next_value_ce + attribute \src "ls180.v:8107.6-8107.57" + case 1'1 + assign $0\main_sdphy_init_count[7:0] \main_sdphy_init_count_sdphy_sdphyinit_next_value + case + end + attribute \src "ls180.v:8111.2-8113.5" + switch \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce + attribute \src "ls180.v:8111.6-8111.57" + case 1'1 + assign $0\main_sdphy_cmdw_count[7:0] \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value + case + end + attribute \src "ls180.v:8114.2-8116.5" + switch \main_sdphy_cmdr_cmdr_pads_in_valid + attribute \src "ls180.v:8114.6-8114.40" + case 1'1 + assign $0\main_sdphy_cmdr_cmdr_run[0:0] $or$ls180.v:8115$2590_Y + case + end + attribute \src "ls180.v:8117.2-8119.5" + switch \main_sdphy_cmdr_cmdr_converter_source_ready + attribute \src "ls180.v:8117.6-8117.49" + case 1'1 + assign $0\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] 1'0 + case + end + attribute \src "ls180.v:8120.2-8127.5" + switch \main_sdphy_cmdr_cmdr_converter_load_part + attribute \src "ls180.v:8120.6-8120.46" + case 1'1 + attribute \src "ls180.v:8121.3-8126.6" + switch $or$ls180.v:8121$2592_Y + attribute \src "ls180.v:8121.7-8121.98" + case 1'1 + assign $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] 3'000 + assign $0\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] 1'1 + attribute \src "ls180.v:8124.7-8124.11" + case + assign $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] $add$ls180.v:8125$2593_Y + end + case + end + attribute \src "ls180.v:8128.2-8141.5" + switch $and$ls180.v:8128$2594_Y + attribute \src "ls180.v:8128.6-8128.97" + case 1'1 + attribute \src "ls180.v:8129.3-8135.6" + switch $and$ls180.v:8129$2595_Y + attribute \src "ls180.v:8129.7-8129.94" + case 1'1 + assign $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0] \main_sdphy_cmdr_cmdr_converter_sink_first + assign $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0] \main_sdphy_cmdr_cmdr_converter_sink_last + attribute \src "ls180.v:8132.7-8132.11" + case + assign $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0] 1'0 + assign $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0] 1'0 + end + attribute \src "ls180.v:8136.6-8136.10" + case + attribute \src "ls180.v:8137.3-8140.6" + switch $and$ls180.v:8137$2596_Y + attribute \src "ls180.v:8137.7-8137.94" + case 1'1 + assign $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0] $or$ls180.v:8138$2597_Y + assign $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0] $or$ls180.v:8139$2598_Y + case + end + end + attribute \src "ls180.v:8142.2-8169.5" + switch \main_sdphy_cmdr_cmdr_converter_load_part + attribute \src "ls180.v:8142.6-8142.46" + case 1'1 + attribute \src "ls180.v:8143.3-8168.10" + switch \main_sdphy_cmdr_cmdr_converter_demux + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] [7] \main_sdphy_cmdr_cmdr_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] [6] \main_sdphy_cmdr_cmdr_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] [5] \main_sdphy_cmdr_cmdr_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] [4] \main_sdphy_cmdr_cmdr_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] [3] \main_sdphy_cmdr_cmdr_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'101 + assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] [2] \main_sdphy_cmdr_cmdr_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'110 + assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] [1] \main_sdphy_cmdr_cmdr_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'111 + assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] [0] \main_sdphy_cmdr_cmdr_converter_sink_payload_data + case + end + case + end + attribute \src "ls180.v:8170.2-8172.5" + switch \main_sdphy_cmdr_cmdr_converter_load_part + attribute \src "ls180.v:8170.6-8170.46" + case 1'1 + assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] $add$ls180.v:8171$2599_Y + case + end + attribute \src "ls180.v:8173.2-8178.5" + switch $or$ls180.v:8173$2601_Y + attribute \src "ls180.v:8173.6-8173.88" + case 1'1 + assign $0\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] \main_sdphy_cmdr_cmdr_buf_sink_valid + assign $0\main_sdphy_cmdr_cmdr_buf_source_first[0:0] \main_sdphy_cmdr_cmdr_buf_sink_first + assign $0\main_sdphy_cmdr_cmdr_buf_source_last[0:0] \main_sdphy_cmdr_cmdr_buf_sink_last + assign $0\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] \main_sdphy_cmdr_cmdr_buf_sink_payload_data + case + end + attribute \src "ls180.v:8179.2-8184.5" + switch \main_sdphy_cmdr_cmdr_reset + attribute \src "ls180.v:8179.6-8179.32" + case 1'1 + assign $0\main_sdphy_cmdr_cmdr_run[0:0] 1'0 + assign $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] 3'000 + assign $0\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] 1'0 + assign $0\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] 1'0 + case + end + attribute \src "ls180.v:8186.2-8188.5" + switch \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0 + attribute \src "ls180.v:8186.6-8186.58" + case 1'1 + assign $0\main_sdphy_cmdr_count[7:0] \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0 + case + end + attribute \src "ls180.v:8189.2-8191.5" + switch \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1 + attribute \src "ls180.v:8189.6-8189.60" + case 1'1 + assign $0\main_sdphy_cmdr_timeout[31:0] \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1 + case + end + attribute \src "ls180.v:8192.2-8194.5" + switch \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2 + attribute \src "ls180.v:8192.6-8192.63" + case 1'1 + assign $0\main_sdphy_cmdr_cmdr_reset[0:0] \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2 + case + end + attribute \src "ls180.v:8195.2-8197.5" + switch \main_sdphy_dataw_crcr_pads_in_valid + attribute \src "ls180.v:8195.6-8195.41" + case 1'1 + assign $0\main_sdphy_dataw_crcr_run[0:0] $or$ls180.v:8196$2602_Y + case + end + attribute \src "ls180.v:8198.2-8200.5" + switch \main_sdphy_dataw_crcr_converter_source_ready + attribute \src "ls180.v:8198.6-8198.50" + case 1'1 + assign $0\main_sdphy_dataw_crcr_converter_strobe_all[0:0] 1'0 + case + end + attribute \src "ls180.v:8201.2-8208.5" + switch \main_sdphy_dataw_crcr_converter_load_part + attribute \src "ls180.v:8201.6-8201.47" + case 1'1 + attribute \src "ls180.v:8202.3-8207.6" + switch $or$ls180.v:8202$2604_Y + attribute \src "ls180.v:8202.7-8202.100" + case 1'1 + assign $0\main_sdphy_dataw_crcr_converter_demux[2:0] 3'000 + assign $0\main_sdphy_dataw_crcr_converter_strobe_all[0:0] 1'1 + attribute \src "ls180.v:8205.7-8205.11" + case + assign $0\main_sdphy_dataw_crcr_converter_demux[2:0] $add$ls180.v:8206$2605_Y + end + case + end + attribute \src "ls180.v:8209.2-8222.5" + switch $and$ls180.v:8209$2606_Y + attribute \src "ls180.v:8209.6-8209.99" + case 1'1 + attribute \src "ls180.v:8210.3-8216.6" + switch $and$ls180.v:8210$2607_Y + attribute \src "ls180.v:8210.7-8210.96" + case 1'1 + assign $0\main_sdphy_dataw_crcr_converter_source_first[0:0] \main_sdphy_dataw_crcr_converter_sink_first + assign $0\main_sdphy_dataw_crcr_converter_source_last[0:0] \main_sdphy_dataw_crcr_converter_sink_last + attribute \src "ls180.v:8213.7-8213.11" + case + assign $0\main_sdphy_dataw_crcr_converter_source_first[0:0] 1'0 + assign $0\main_sdphy_dataw_crcr_converter_source_last[0:0] 1'0 + end + attribute \src "ls180.v:8217.6-8217.10" + case + attribute \src "ls180.v:8218.3-8221.6" + switch $and$ls180.v:8218$2608_Y + attribute \src "ls180.v:8218.7-8218.96" + case 1'1 + assign $0\main_sdphy_dataw_crcr_converter_source_first[0:0] $or$ls180.v:8219$2609_Y + assign $0\main_sdphy_dataw_crcr_converter_source_last[0:0] $or$ls180.v:8220$2610_Y + case + end + end + attribute \src "ls180.v:8223.2-8250.5" + switch \main_sdphy_dataw_crcr_converter_load_part + attribute \src "ls180.v:8223.6-8223.47" + case 1'1 + attribute \src "ls180.v:8224.3-8249.10" + switch \main_sdphy_dataw_crcr_converter_demux + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] [7] \main_sdphy_dataw_crcr_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] [6] \main_sdphy_dataw_crcr_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] [5] \main_sdphy_dataw_crcr_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] [4] \main_sdphy_dataw_crcr_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] [3] \main_sdphy_dataw_crcr_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'101 + assign $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] [2] \main_sdphy_dataw_crcr_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'110 + assign $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] [1] \main_sdphy_dataw_crcr_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'111 + assign $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] [0] \main_sdphy_dataw_crcr_converter_sink_payload_data + case + end + case + end + attribute \src "ls180.v:8251.2-8253.5" + switch \main_sdphy_dataw_crcr_converter_load_part + attribute \src "ls180.v:8251.6-8251.47" + case 1'1 + assign $0\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] $add$ls180.v:8252$2611_Y + case + end + attribute \src "ls180.v:8254.2-8259.5" + switch $or$ls180.v:8254$2613_Y + attribute \src "ls180.v:8254.6-8254.90" + case 1'1 + assign $0\main_sdphy_dataw_crcr_buf_source_valid[0:0] \main_sdphy_dataw_crcr_buf_sink_valid + assign $0\main_sdphy_dataw_crcr_buf_source_first[0:0] \main_sdphy_dataw_crcr_buf_sink_first + assign $0\main_sdphy_dataw_crcr_buf_source_last[0:0] \main_sdphy_dataw_crcr_buf_sink_last + assign $0\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] \main_sdphy_dataw_crcr_buf_sink_payload_data + case + end + attribute \src "ls180.v:8260.2-8265.5" + switch \main_sdphy_dataw_crcr_reset + attribute \src "ls180.v:8260.6-8260.33" + case 1'1 + assign $0\main_sdphy_dataw_crcr_run[0:0] 1'0 + assign $0\main_sdphy_dataw_crcr_converter_demux[2:0] 3'000 + assign $0\main_sdphy_dataw_crcr_converter_strobe_all[0:0] 1'0 + assign $0\main_sdphy_dataw_crcr_buf_source_valid[0:0] 1'0 + case + end + attribute \src "ls180.v:8267.2-8269.5" + switch \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce + attribute \src "ls180.v:8267.6-8267.63" + case 1'1 + assign $0\main_sdphy_dataw_crcr_reset[0:0] \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value + case + end + attribute \src "ls180.v:8271.2-8273.5" + switch \main_sdphy_dataw_count_sdphy_fsm_next_value_ce + attribute \src "ls180.v:8271.6-8271.52" + case 1'1 + assign $0\main_sdphy_dataw_count[7:0] \main_sdphy_dataw_count_sdphy_fsm_next_value + case + end + attribute \src "ls180.v:8274.2-8276.5" + switch \main_sdphy_datar_datar_pads_in_valid + attribute \src "ls180.v:8274.6-8274.42" + case 1'1 + assign $0\main_sdphy_datar_datar_run[0:0] $or$ls180.v:8275$2614_Y + case + end + attribute \src "ls180.v:8277.2-8279.5" + switch \main_sdphy_datar_datar_converter_source_ready + attribute \src "ls180.v:8277.6-8277.51" + case 1'1 + assign $0\main_sdphy_datar_datar_converter_strobe_all[0:0] 1'0 + case + end + attribute \src "ls180.v:8280.2-8287.5" + switch \main_sdphy_datar_datar_converter_load_part + attribute \src "ls180.v:8280.6-8280.48" + case 1'1 + attribute \src "ls180.v:8281.3-8286.6" + switch $or$ls180.v:8281$2616_Y + attribute \src "ls180.v:8281.7-8281.102" + case 1'1 + assign $0\main_sdphy_datar_datar_converter_demux[0:0] 1'0 + assign $0\main_sdphy_datar_datar_converter_strobe_all[0:0] 1'1 + attribute \src "ls180.v:8284.7-8284.11" + case + assign $0\main_sdphy_datar_datar_converter_demux[0:0] $add$ls180.v:8285$2617_Y + end + case + end + attribute \src "ls180.v:8288.2-8301.5" + switch $and$ls180.v:8288$2618_Y + attribute \src "ls180.v:8288.6-8288.101" + case 1'1 + attribute \src "ls180.v:8289.3-8295.6" + switch $and$ls180.v:8289$2619_Y + attribute \src "ls180.v:8289.7-8289.98" + case 1'1 + assign $0\main_sdphy_datar_datar_converter_source_first[0:0] \main_sdphy_datar_datar_converter_sink_first + assign $0\main_sdphy_datar_datar_converter_source_last[0:0] \main_sdphy_datar_datar_converter_sink_last + attribute \src "ls180.v:8292.7-8292.11" + case + assign $0\main_sdphy_datar_datar_converter_source_first[0:0] 1'0 + assign $0\main_sdphy_datar_datar_converter_source_last[0:0] 1'0 + end + attribute \src "ls180.v:8296.6-8296.10" + case + attribute \src "ls180.v:8297.3-8300.6" + switch $and$ls180.v:8297$2620_Y + attribute \src "ls180.v:8297.7-8297.98" + case 1'1 + assign $0\main_sdphy_datar_datar_converter_source_first[0:0] $or$ls180.v:8298$2621_Y + assign $0\main_sdphy_datar_datar_converter_source_last[0:0] $or$ls180.v:8299$2622_Y + case + end + end + attribute \src "ls180.v:8302.2-8311.5" + switch \main_sdphy_datar_datar_converter_load_part + attribute \src "ls180.v:8302.6-8302.48" + case 1'1 + attribute \src "ls180.v:8303.3-8310.10" + switch \main_sdphy_datar_datar_converter_demux + attribute \src "ls180.v:0.0-0.0" + case 1'0 + assign $0\main_sdphy_datar_datar_converter_source_payload_data[7:0] [7:4] \main_sdphy_datar_datar_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\main_sdphy_datar_datar_converter_source_payload_data[7:0] [3:0] \main_sdphy_datar_datar_converter_sink_payload_data + case + end + case + end + attribute \src "ls180.v:8312.2-8314.5" + switch \main_sdphy_datar_datar_converter_load_part + attribute \src "ls180.v:8312.6-8312.48" + case 1'1 + assign $0\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] $add$ls180.v:8313$2623_Y + case + end + attribute \src "ls180.v:8315.2-8320.5" + switch $or$ls180.v:8315$2625_Y + attribute \src "ls180.v:8315.6-8315.92" + case 1'1 + assign $0\main_sdphy_datar_datar_buf_source_valid[0:0] \main_sdphy_datar_datar_buf_sink_valid + assign $0\main_sdphy_datar_datar_buf_source_first[0:0] \main_sdphy_datar_datar_buf_sink_first + assign $0\main_sdphy_datar_datar_buf_source_last[0:0] \main_sdphy_datar_datar_buf_sink_last + assign $0\main_sdphy_datar_datar_buf_source_payload_data[7:0] \main_sdphy_datar_datar_buf_sink_payload_data + case + end + attribute \src "ls180.v:8321.2-8326.5" + switch \main_sdphy_datar_datar_reset + attribute \src "ls180.v:8321.6-8321.34" + case 1'1 + assign $0\main_sdphy_datar_datar_run[0:0] 1'0 + assign $0\main_sdphy_datar_datar_converter_demux[0:0] 1'0 + assign $0\main_sdphy_datar_datar_converter_strobe_all[0:0] 1'0 + assign $0\main_sdphy_datar_datar_buf_source_valid[0:0] 1'0 + case + end + attribute \src "ls180.v:8328.2-8330.5" + switch \main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0 + attribute \src "ls180.v:8328.6-8328.60" + case 1'1 + assign $0\main_sdphy_datar_count[9:0] \main_sdphy_datar_count_sdphy_sdphydatar_next_value0 + case + end + attribute \src "ls180.v:8331.2-8333.5" + switch \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1 + attribute \src "ls180.v:8331.6-8331.62" + case 1'1 + assign $0\main_sdphy_datar_timeout[31:0] \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1 + case + end + attribute \src "ls180.v:8334.2-8336.5" + switch \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2 + attribute \src "ls180.v:8334.6-8334.66" + case 1'1 + assign $0\main_sdphy_datar_datar_reset[0:0] \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2 + case + end + attribute \src "ls180.v:8337.2-8343.5" + switch \main_sdcore_crc7_inserter_clr + attribute \src "ls180.v:8337.6-8337.35" + case 1'1 + assign $0\main_sdcore_crc7_inserter_crcreg0[6:0] 7'0000000 + attribute \src "ls180.v:8339.6-8339.10" + case + attribute \src "ls180.v:8340.3-8342.6" + switch \main_sdcore_crc7_inserter_enable + attribute \src "ls180.v:8340.7-8340.39" + case 1'1 + assign $0\main_sdcore_crc7_inserter_crcreg0[6:0] \main_sdcore_crc7_inserter_crcreg40 + case + end + end + attribute \src "ls180.v:8344.2-8350.5" + switch \main_sdcore_crc16_inserter_crc0_clr + attribute \src "ls180.v:8344.6-8344.41" + case 1'1 + assign $0\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] 16'0000000000000000 + attribute \src "ls180.v:8346.6-8346.10" + case + attribute \src "ls180.v:8347.3-8349.6" + switch \main_sdcore_crc16_inserter_crc0_enable + attribute \src "ls180.v:8347.7-8347.45" + case 1'1 + assign $0\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] \main_sdcore_crc16_inserter_crc0_crcreg2 + case + end + end + attribute \src "ls180.v:8351.2-8357.5" + switch \main_sdcore_crc16_inserter_crc1_clr + attribute \src "ls180.v:8351.6-8351.41" + case 1'1 + assign $0\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] 16'0000000000000000 + attribute \src "ls180.v:8353.6-8353.10" + case + attribute \src "ls180.v:8354.3-8356.6" + switch \main_sdcore_crc16_inserter_crc1_enable + attribute \src "ls180.v:8354.7-8354.45" + case 1'1 + assign $0\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] \main_sdcore_crc16_inserter_crc1_crcreg2 + case + end + end + attribute \src "ls180.v:8358.2-8364.5" + switch \main_sdcore_crc16_inserter_crc2_clr + attribute \src "ls180.v:8358.6-8358.41" + case 1'1 + assign $0\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] 16'0000000000000000 + attribute \src "ls180.v:8360.6-8360.10" + case + attribute \src "ls180.v:8361.3-8363.6" + switch \main_sdcore_crc16_inserter_crc2_enable + attribute \src "ls180.v:8361.7-8361.45" + case 1'1 + assign $0\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] \main_sdcore_crc16_inserter_crc2_crcreg2 + case + end + end + attribute \src "ls180.v:8365.2-8371.5" + switch \main_sdcore_crc16_inserter_crc3_clr + attribute \src "ls180.v:8365.6-8365.41" + case 1'1 + assign $0\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] 16'0000000000000000 + attribute \src "ls180.v:8367.6-8367.10" + case + attribute \src "ls180.v:8368.3-8370.6" + switch \main_sdcore_crc16_inserter_crc3_enable + attribute \src "ls180.v:8368.7-8368.45" + case 1'1 + assign $0\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] \main_sdcore_crc16_inserter_crc3_crcreg2 + case + end + end + attribute \src "ls180.v:8373.2-8375.5" + switch \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0 + attribute \src "ls180.v:8373.6-8373.82" + case 1'1 + assign $0\main_sdcore_crc16_inserter_crctmp0[15:0] \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0 + case + end + attribute \src "ls180.v:8376.2-8378.5" + switch \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1 + attribute \src "ls180.v:8376.6-8376.82" + case 1'1 + assign $0\main_sdcore_crc16_inserter_crctmp1[15:0] \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1 + case + end + attribute \src "ls180.v:8379.2-8381.5" + switch \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2 + attribute \src "ls180.v:8379.6-8379.82" + case 1'1 + assign $0\main_sdcore_crc16_inserter_crctmp2[15:0] \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2 + case + end + attribute \src "ls180.v:8382.2-8384.5" + switch \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3 + attribute \src "ls180.v:8382.6-8382.82" + case 1'1 + assign $0\main_sdcore_crc16_inserter_crctmp3[15:0] \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3 + case + end + attribute \src "ls180.v:8385.2-8387.5" + switch \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4 + attribute \src "ls180.v:8385.6-8385.78" + case 1'1 + assign $0\main_sdcore_crc16_inserter_cnt[2:0] \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4 + case + end + attribute \src "ls180.v:8388.2-8390.5" + switch $and$ls180.v:8388$2626_Y + attribute \src "ls180.v:8388.6-8388.83" + case 1'1 + assign $0\main_sdcore_crc16_checker_crctmp0[15:0] \main_sdcore_crc16_checker_crc0_crc + case + end + attribute \src "ls180.v:8391.2-8393.5" + switch $and$ls180.v:8391$2627_Y + attribute \src "ls180.v:8391.6-8391.83" + case 1'1 + assign $0\main_sdcore_crc16_checker_crctmp1[15:0] \main_sdcore_crc16_checker_crc1_crc + case + end + attribute \src "ls180.v:8394.2-8396.5" + switch $and$ls180.v:8394$2628_Y + attribute \src "ls180.v:8394.6-8394.83" + case 1'1 + assign $0\main_sdcore_crc16_checker_crctmp2[15:0] \main_sdcore_crc16_checker_crc2_crc + case + end + attribute \src "ls180.v:8397.2-8399.5" + switch $and$ls180.v:8397$2629_Y + attribute \src "ls180.v:8397.6-8397.83" + case 1'1 + assign $0\main_sdcore_crc16_checker_crctmp3[15:0] \main_sdcore_crc16_checker_crc3_crc + case + end + attribute \src "ls180.v:8400.2-8404.5" + switch $and$ls180.v:8400$2630_Y + attribute \src "ls180.v:8400.6-8400.83" + case 1'1 + assign $0\main_sdcore_crc16_checker_fifo0[15:0] { \main_sdcore_crc16_checker_fifo0 [13:0] \main_sdcore_crc16_checker_sink_payload_data [7] \main_sdcore_crc16_checker_sink_payload_data [3] } + assign $0\main_sdcore_crc16_checker_val[7:0] [7] \main_sdcore_crc16_checker_fifo0 [13] + assign $0\main_sdcore_crc16_checker_val[7:0] [3] \main_sdcore_crc16_checker_fifo0 [12] + case + end + attribute \src "ls180.v:8405.2-8409.5" + switch $and$ls180.v:8405$2631_Y + attribute \src "ls180.v:8405.6-8405.83" + case 1'1 + assign $0\main_sdcore_crc16_checker_fifo1[15:0] { \main_sdcore_crc16_checker_fifo1 [13:0] \main_sdcore_crc16_checker_sink_payload_data [6] \main_sdcore_crc16_checker_sink_payload_data [2] } + assign $0\main_sdcore_crc16_checker_val[7:0] [6] \main_sdcore_crc16_checker_fifo1 [13] + assign $0\main_sdcore_crc16_checker_val[7:0] [2] \main_sdcore_crc16_checker_fifo1 [12] + case + end + attribute \src "ls180.v:8410.2-8414.5" + switch $and$ls180.v:8410$2632_Y + attribute \src "ls180.v:8410.6-8410.83" + case 1'1 + assign $0\main_sdcore_crc16_checker_fifo2[15:0] { \main_sdcore_crc16_checker_fifo2 [13:0] \main_sdcore_crc16_checker_sink_payload_data [5] \main_sdcore_crc16_checker_sink_payload_data [1] } + assign $0\main_sdcore_crc16_checker_val[7:0] [5] \main_sdcore_crc16_checker_fifo2 [13] + assign $0\main_sdcore_crc16_checker_val[7:0] [1] \main_sdcore_crc16_checker_fifo2 [12] + case + end + attribute \src "ls180.v:8415.2-8419.5" + switch $and$ls180.v:8415$2633_Y + attribute \src "ls180.v:8415.6-8415.83" + case 1'1 + assign $0\main_sdcore_crc16_checker_fifo3[15:0] { \main_sdcore_crc16_checker_fifo3 [13:0] \main_sdcore_crc16_checker_sink_payload_data [4] \main_sdcore_crc16_checker_sink_payload_data [0] } + assign $0\main_sdcore_crc16_checker_val[7:0] [4] \main_sdcore_crc16_checker_fifo3 [13] + assign $0\main_sdcore_crc16_checker_val[7:0] [0] \main_sdcore_crc16_checker_fifo3 [12] + case + end + attribute \src "ls180.v:8420.2-8428.5" + switch $and$ls180.v:8420$2634_Y + attribute \src "ls180.v:8420.6-8420.83" + case 1'1 + attribute \src "ls180.v:8421.3-8427.6" + switch \main_sdcore_crc16_checker_sink_last + attribute \src "ls180.v:8421.7-8421.42" + case 1'1 + assign $0\main_sdcore_crc16_checker_cnt[3:0] 4'0000 + attribute \src "ls180.v:8423.7-8423.11" + case + attribute \src "ls180.v:8424.4-8426.7" + switch $ne$ls180.v:8424$2635_Y + attribute \src "ls180.v:8424.8-8424.48" + case 1'1 + assign $0\main_sdcore_crc16_checker_cnt[3:0] $add$ls180.v:8425$2636_Y + case + end + end + case + end + attribute \src "ls180.v:8429.2-8435.5" + switch \main_sdcore_crc16_checker_crc0_clr + attribute \src "ls180.v:8429.6-8429.40" + case 1'1 + assign $0\main_sdcore_crc16_checker_crc0_crcreg0[15:0] 16'0000000000000000 + attribute \src "ls180.v:8431.6-8431.10" + case + attribute \src "ls180.v:8432.3-8434.6" + switch \main_sdcore_crc16_checker_crc0_enable + attribute \src "ls180.v:8432.7-8432.44" + case 1'1 + assign $0\main_sdcore_crc16_checker_crc0_crcreg0[15:0] \main_sdcore_crc16_checker_crc0_crcreg2 + case + end + end + attribute \src "ls180.v:8436.2-8442.5" + switch \main_sdcore_crc16_checker_crc1_clr + attribute \src "ls180.v:8436.6-8436.40" + case 1'1 + assign $0\main_sdcore_crc16_checker_crc1_crcreg0[15:0] 16'0000000000000000 + attribute \src "ls180.v:8438.6-8438.10" + case + attribute \src "ls180.v:8439.3-8441.6" + switch \main_sdcore_crc16_checker_crc1_enable + attribute \src "ls180.v:8439.7-8439.44" + case 1'1 + assign $0\main_sdcore_crc16_checker_crc1_crcreg0[15:0] \main_sdcore_crc16_checker_crc1_crcreg2 + case + end + end + attribute \src "ls180.v:8443.2-8449.5" + switch \main_sdcore_crc16_checker_crc2_clr + attribute \src "ls180.v:8443.6-8443.40" + case 1'1 + assign $0\main_sdcore_crc16_checker_crc2_crcreg0[15:0] 16'0000000000000000 + attribute \src "ls180.v:8445.6-8445.10" + case + attribute \src "ls180.v:8446.3-8448.6" + switch \main_sdcore_crc16_checker_crc2_enable + attribute \src "ls180.v:8446.7-8446.44" + case 1'1 + assign $0\main_sdcore_crc16_checker_crc2_crcreg0[15:0] \main_sdcore_crc16_checker_crc2_crcreg2 + case + end + end + attribute \src "ls180.v:8450.2-8456.5" + switch \main_sdcore_crc16_checker_crc3_clr + attribute \src "ls180.v:8450.6-8450.40" + case 1'1 + assign $0\main_sdcore_crc16_checker_crc3_crcreg0[15:0] 16'0000000000000000 + attribute \src "ls180.v:8452.6-8452.10" + case + attribute \src "ls180.v:8453.3-8455.6" + switch \main_sdcore_crc16_checker_crc3_enable + attribute \src "ls180.v:8453.7-8453.44" + case 1'1 + assign $0\main_sdcore_crc16_checker_crc3_crcreg0[15:0] \main_sdcore_crc16_checker_crc3_crcreg2 + case + end + end + attribute \src "ls180.v:8458.2-8460.5" + switch \main_sdcore_cmd_done_sdcore_fsm_next_value_ce0 + attribute \src "ls180.v:8458.6-8458.52" + case 1'1 + assign $0\main_sdcore_cmd_done[0:0] \main_sdcore_cmd_done_sdcore_fsm_next_value0 + case + end + attribute \src "ls180.v:8461.2-8463.5" + switch \main_sdcore_data_done_sdcore_fsm_next_value_ce1 + attribute \src "ls180.v:8461.6-8461.53" + case 1'1 + assign $0\main_sdcore_data_done[0:0] \main_sdcore_data_done_sdcore_fsm_next_value1 + case + end + attribute \src "ls180.v:8464.2-8466.5" + switch \main_sdcore_cmd_count_sdcore_fsm_next_value_ce2 + attribute \src "ls180.v:8464.6-8464.53" + case 1'1 + assign $0\main_sdcore_cmd_count[2:0] \main_sdcore_cmd_count_sdcore_fsm_next_value2 + case + end + attribute \src "ls180.v:8467.2-8469.5" + switch \main_sdcore_data_count_sdcore_fsm_next_value_ce3 + attribute \src "ls180.v:8467.6-8467.54" + case 1'1 + assign $0\main_sdcore_data_count[31:0] \main_sdcore_data_count_sdcore_fsm_next_value3 + case + end + attribute \src "ls180.v:8470.2-8472.5" + switch \main_sdcore_cmd_error_sdcore_fsm_next_value_ce4 + attribute \src "ls180.v:8470.6-8470.53" + case 1'1 + assign $0\main_sdcore_cmd_error[0:0] \main_sdcore_cmd_error_sdcore_fsm_next_value4 + case + end + attribute \src "ls180.v:8473.2-8475.5" + switch \main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5 + attribute \src "ls180.v:8473.6-8473.55" + case 1'1 + assign $0\main_sdcore_cmd_timeout[0:0] \main_sdcore_cmd_timeout_sdcore_fsm_next_value5 + case + end + attribute \src "ls180.v:8476.2-8478.5" + switch \main_sdcore_data_error_sdcore_fsm_next_value_ce6 + attribute \src "ls180.v:8476.6-8476.54" + case 1'1 + assign $0\main_sdcore_data_error[0:0] \main_sdcore_data_error_sdcore_fsm_next_value6 + case + end + attribute \src "ls180.v:8479.2-8481.5" + switch \main_sdcore_data_timeout_sdcore_fsm_next_value_ce7 + attribute \src "ls180.v:8479.6-8479.56" + case 1'1 + assign $0\main_sdcore_data_timeout[0:0] \main_sdcore_data_timeout_sdcore_fsm_next_value7 + case + end + attribute \src "ls180.v:8482.2-8484.5" + switch \main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8 + attribute \src "ls180.v:8482.6-8482.63" + case 1'1 + assign $0\main_sdcore_cmd_response_status[127:0] \main_sdcore_cmd_response_status_sdcore_fsm_next_value8 + case + end + attribute \src "ls180.v:8485.2-8487.5" + switch $and$ls180.v:8485$2639_Y + attribute \src "ls180.v:8485.6-8485.120" + case 1'1 + assign $0\main_sdblock2mem_fifo_produce[4:0] $add$ls180.v:8486$2640_Y + case + end + attribute \src "ls180.v:8488.2-8490.5" + switch \main_sdblock2mem_fifo_do_read + attribute \src "ls180.v:8488.6-8488.35" + case 1'1 + assign $0\main_sdblock2mem_fifo_consume[4:0] $add$ls180.v:8489$2641_Y + case + end + attribute \src "ls180.v:8491.2-8499.5" + switch $and$ls180.v:8491$2644_Y + attribute \src "ls180.v:8491.6-8491.120" + case 1'1 + attribute \src "ls180.v:8492.3-8494.6" + switch $not$ls180.v:8492$2645_Y + attribute \src "ls180.v:8492.7-8492.39" + case 1'1 + assign $0\main_sdblock2mem_fifo_level[5:0] $add$ls180.v:8493$2646_Y + case + end + attribute \src "ls180.v:8495.6-8495.10" + case + attribute \src "ls180.v:8496.3-8498.6" + switch \main_sdblock2mem_fifo_do_read + attribute \src "ls180.v:8496.7-8496.36" + case 1'1 + assign $0\main_sdblock2mem_fifo_level[5:0] $sub$ls180.v:8497$2647_Y + case + end + end + attribute \src "ls180.v:8500.2-8502.5" + switch \main_sdblock2mem_converter_source_ready + attribute \src "ls180.v:8500.6-8500.45" + case 1'1 + assign $0\main_sdblock2mem_converter_strobe_all[0:0] 1'0 + case + end + attribute \src "ls180.v:8503.2-8510.5" + switch \main_sdblock2mem_converter_load_part + attribute \src "ls180.v:8503.6-8503.42" + case 1'1 + attribute \src "ls180.v:8504.3-8509.6" + switch $or$ls180.v:8504$2649_Y + attribute \src "ls180.v:8504.7-8504.90" + case 1'1 + assign $0\main_sdblock2mem_converter_demux[1:0] 2'00 + assign $0\main_sdblock2mem_converter_strobe_all[0:0] 1'1 + attribute \src "ls180.v:8507.7-8507.11" + case + assign $0\main_sdblock2mem_converter_demux[1:0] $add$ls180.v:8508$2650_Y + end + case + end + attribute \src "ls180.v:8511.2-8524.5" + switch $and$ls180.v:8511$2651_Y + attribute \src "ls180.v:8511.6-8511.89" + case 1'1 + attribute \src "ls180.v:8512.3-8518.6" + switch $and$ls180.v:8512$2652_Y + attribute \src "ls180.v:8512.7-8512.86" + case 1'1 + assign $0\main_sdblock2mem_converter_source_first[0:0] \main_sdblock2mem_converter_sink_first + assign $0\main_sdblock2mem_converter_source_last[0:0] \main_sdblock2mem_converter_sink_last + attribute \src "ls180.v:8515.7-8515.11" + case + assign $0\main_sdblock2mem_converter_source_first[0:0] 1'0 + assign $0\main_sdblock2mem_converter_source_last[0:0] 1'0 + end + attribute \src "ls180.v:8519.6-8519.10" + case + attribute \src "ls180.v:8520.3-8523.6" + switch $and$ls180.v:8520$2653_Y + attribute \src "ls180.v:8520.7-8520.86" + case 1'1 + assign $0\main_sdblock2mem_converter_source_first[0:0] $or$ls180.v:8521$2654_Y + assign $0\main_sdblock2mem_converter_source_last[0:0] $or$ls180.v:8522$2655_Y + case + end + end + attribute \src "ls180.v:8525.2-8540.5" + switch \main_sdblock2mem_converter_load_part + attribute \src "ls180.v:8525.6-8525.42" + case 1'1 + attribute \src "ls180.v:8526.3-8539.10" + switch \main_sdblock2mem_converter_demux + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\main_sdblock2mem_converter_source_payload_data[31:0] [31:24] \main_sdblock2mem_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\main_sdblock2mem_converter_source_payload_data[31:0] [23:16] \main_sdblock2mem_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\main_sdblock2mem_converter_source_payload_data[31:0] [15:8] \main_sdblock2mem_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 2'11 + assign $0\main_sdblock2mem_converter_source_payload_data[31:0] [7:0] \main_sdblock2mem_converter_sink_payload_data + case + end + case + end + attribute \src "ls180.v:8541.2-8543.5" + switch \main_sdblock2mem_converter_load_part + attribute \src "ls180.v:8541.6-8541.42" + case 1'1 + assign $0\main_sdblock2mem_converter_source_payload_valid_token_count[2:0] $add$ls180.v:8542$2656_Y + case + end + attribute \src "ls180.v:8545.2-8547.5" + switch \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce + attribute \src "ls180.v:8545.6-8545.76" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_offset[31:0] \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value + case + end + attribute \src "ls180.v:8548.2-8551.5" + switch \main_sdblock2mem_wishbonedmawriter_reset + attribute \src "ls180.v:8548.6-8548.46" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_offset[31:0] 0 + assign $0\builder_sdblock2memdma_state[1:0] 2'00 + case + end + attribute \src "ls180.v:8553.2-8555.5" + switch \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce + attribute \src "ls180.v:8553.6-8553.64" + case 1'1 + assign $0\main_sdmem2block_dma_data[31:0] \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value + case + end + attribute \src "ls180.v:8557.2-8559.5" + switch \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce + attribute \src "ls180.v:8557.6-8557.76" + case 1'1 + assign $0\main_sdmem2block_dma_offset[31:0] \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value + case + end + attribute \src "ls180.v:8560.2-8563.5" + switch \main_sdmem2block_dma_reset + attribute \src "ls180.v:8560.6-8560.32" + case 1'1 + assign $0\main_sdmem2block_dma_offset[31:0] 0 + assign $0\builder_sdmem2blockdma_resetinserter_state[1:0] 2'00 + case + end + attribute \src "ls180.v:8564.2-8570.5" + switch $and$ls180.v:8564$2657_Y + attribute \src "ls180.v:8564.6-8564.89" + case 1'1 + attribute \src "ls180.v:8565.3-8569.6" + switch \main_sdmem2block_converter_last + attribute \src "ls180.v:8565.7-8565.38" + case 1'1 + assign $0\main_sdmem2block_converter_mux[1:0] 2'00 + attribute \src "ls180.v:8567.7-8567.11" + case + assign $0\main_sdmem2block_converter_mux[1:0] $add$ls180.v:8568$2658_Y + end + case + end + attribute \src "ls180.v:8571.2-8573.5" + switch $and$ls180.v:8571$2661_Y + attribute \src "ls180.v:8571.6-8571.120" + case 1'1 + assign $0\main_sdmem2block_fifo_produce[4:0] $add$ls180.v:8572$2662_Y + case + end + attribute \src "ls180.v:8574.2-8576.5" + switch \main_sdmem2block_fifo_do_read + attribute \src "ls180.v:8574.6-8574.35" + case 1'1 + assign $0\main_sdmem2block_fifo_consume[4:0] $add$ls180.v:8575$2663_Y + case + end + attribute \src "ls180.v:8577.2-8585.5" + switch $and$ls180.v:8577$2666_Y + attribute \src "ls180.v:8577.6-8577.120" + case 1'1 + attribute \src "ls180.v:8578.3-8580.6" + switch $not$ls180.v:8578$2667_Y + attribute \src "ls180.v:8578.7-8578.39" + case 1'1 + assign $0\main_sdmem2block_fifo_level[5:0] $add$ls180.v:8579$2668_Y + case + end + attribute \src "ls180.v:8581.6-8581.10" + case + attribute \src "ls180.v:8582.3-8584.6" + switch \main_sdmem2block_fifo_do_read + attribute \src "ls180.v:8582.7-8582.36" + case 1'1 + assign $0\main_sdmem2block_fifo_level[5:0] $sub$ls180.v:8583$2669_Y + case + end + end + attribute \src "ls180.v:8587.2-8594.5" + switch \libresocsim_clk_rise + attribute \src "ls180.v:8587.6-8587.26" + case 1'1 + assign $0\spisdcard_clk[0:0] \libresocsim_clk_enable + attribute \src "ls180.v:8589.6-8589.10" + case + attribute \src "ls180.v:8590.3-8593.6" + switch \libresocsim_clk_fall + attribute \src "ls180.v:8590.7-8590.27" + case 1'1 + assign $0\libresocsim_clk_divider1[15:0] 16'0000000000000000 + assign $0\spisdcard_clk[0:0] 1'0 + case + end + end + attribute \src "ls180.v:8596.2-8606.5" + switch \libresocsim_mosi_latch + attribute \src "ls180.v:8596.6-8596.28" + case 1'1 + assign $0\libresocsim_mosi_data[7:0] \libresocsim_mosi + assign $0\libresocsim_mosi_sel[2:0] 3'111 + attribute \src "ls180.v:8599.6-8599.10" + case + attribute \src "ls180.v:8600.3-8605.6" + switch \libresocsim_clk_fall + attribute \src "ls180.v:8600.7-8600.27" + case 1'1 + assign $0\libresocsim_mosi_sel[2:0] $sub$ls180.v:8604$2674_Y + attribute \src "ls180.v:8601.4-8603.7" + switch \libresocsim_cs_enable + attribute \src "ls180.v:8601.8-8601.29" + case 1'1 + assign $0\spisdcard_mosi[0:0] \builder_sync_f_array_muxed1 + case + end + case + end + end + attribute \src "ls180.v:8607.2-8613.5" + switch \libresocsim_clk_rise + attribute \src "ls180.v:8607.6-8607.26" + case 1'1 + attribute \src "ls180.v:8608.3-8612.6" + switch \libresocsim_loopback + attribute \src "ls180.v:8608.7-8608.27" + case 1'1 + assign $0\libresocsim_miso_data[7:0] { \libresocsim_miso_data [6:0] \spisdcard_mosi } + attribute \src "ls180.v:8610.7-8610.11" + case + assign $0\libresocsim_miso_data[7:0] { \libresocsim_miso_data [6:0] \spisdcard_miso } + end + case + end + attribute \src "ls180.v:8614.2-8616.5" + switch \libresocsim_miso_latch + attribute \src "ls180.v:8614.6-8614.28" + case 1'1 + assign $0\libresocsim_miso[7:0] \libresocsim_miso_data + case + end + attribute \src "ls180.v:8618.2-8620.5" + switch \libresocsim_count_spimaster1_next_value_ce + attribute \src "ls180.v:8618.6-8618.48" + case 1'1 + assign $0\libresocsim_count[2:0] \libresocsim_count_spimaster1_next_value + case + end + attribute \src "ls180.v:8622.2-8624.5" + switch \builder_libresocsim_dat_w_next_value_ce0 + attribute \src "ls180.v:8622.6-8622.46" + case 1'1 + assign $0\builder_libresocsim_dat_w[7:0] \builder_libresocsim_dat_w_next_value0 + case + end + attribute \src "ls180.v:8625.2-8627.5" + switch \builder_libresocsim_adr_next_value_ce1 + attribute \src "ls180.v:8625.6-8625.44" + case 1'1 + assign $0\builder_libresocsim_adr[13:0] \builder_libresocsim_adr_next_value1 + case + end + attribute \src "ls180.v:8628.2-8630.5" + switch \builder_libresocsim_we_next_value_ce2 + attribute \src "ls180.v:8628.6-8628.43" + case 1'1 + assign $0\builder_libresocsim_we[0:0] \builder_libresocsim_we_next_value2 + case + end + attribute \src "ls180.v:8631.2-8727.9" + switch \builder_grant + attribute \src "ls180.v:0.0-0.0" + case 3'000 + attribute \src "ls180.v:8633.4-8649.7" + switch $not$ls180.v:8633$2675_Y + attribute \src "ls180.v:8633.8-8633.29" + case 1'1 + attribute \src "ls180.v:8634.5-8648.8" + switch \builder_request [1] + attribute \src "ls180.v:8634.9-8634.27" + case 1'1 + assign $0\builder_grant[2:0] 3'001 + attribute \src "ls180.v:8636.9-8636.13" + case + attribute \src "ls180.v:8637.6-8647.9" + switch \builder_request [2] + attribute \src "ls180.v:8637.10-8637.28" + case 1'1 + assign $0\builder_grant[2:0] 3'010 + attribute \src "ls180.v:8639.10-8639.14" + case + attribute \src "ls180.v:8640.7-8646.10" + switch \builder_request [3] + attribute \src "ls180.v:8640.11-8640.29" + case 1'1 + assign $0\builder_grant[2:0] 3'011 + attribute \src "ls180.v:8642.11-8642.15" + case + attribute \src "ls180.v:8643.8-8645.11" + switch \builder_request [4] + attribute \src "ls180.v:8643.12-8643.30" + case 1'1 + assign $0\builder_grant[2:0] 3'100 + case + end + end + end + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'001 + attribute \src "ls180.v:8652.4-8668.7" + switch $not$ls180.v:8652$2676_Y + attribute \src "ls180.v:8652.8-8652.29" + case 1'1 + attribute \src "ls180.v:8653.5-8667.8" + switch \builder_request [2] + attribute \src "ls180.v:8653.9-8653.27" + case 1'1 + assign $0\builder_grant[2:0] 3'010 + attribute \src "ls180.v:8655.9-8655.13" + case + attribute \src "ls180.v:8656.6-8666.9" + switch \builder_request [3] + attribute \src "ls180.v:8656.10-8656.28" + case 1'1 + assign $0\builder_grant[2:0] 3'011 + attribute \src "ls180.v:8658.10-8658.14" + case + attribute \src "ls180.v:8659.7-8665.10" + switch \builder_request [4] + attribute \src "ls180.v:8659.11-8659.29" + case 1'1 + assign $0\builder_grant[2:0] 3'100 + attribute \src "ls180.v:8661.11-8661.15" + case + attribute \src "ls180.v:8662.8-8664.11" + switch \builder_request [0] + attribute \src "ls180.v:8662.12-8662.30" + case 1'1 + assign $0\builder_grant[2:0] 3'000 + case + end + end + end + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'010 + attribute \src "ls180.v:8671.4-8687.7" + switch $not$ls180.v:8671$2677_Y + attribute \src "ls180.v:8671.8-8671.29" + case 1'1 + attribute \src "ls180.v:8672.5-8686.8" + switch \builder_request [3] + attribute \src "ls180.v:8672.9-8672.27" + case 1'1 + assign $0\builder_grant[2:0] 3'011 + attribute \src "ls180.v:8674.9-8674.13" + case + attribute \src "ls180.v:8675.6-8685.9" + switch \builder_request [4] + attribute \src "ls180.v:8675.10-8675.28" + case 1'1 + assign $0\builder_grant[2:0] 3'100 + attribute \src "ls180.v:8677.10-8677.14" + case + attribute \src "ls180.v:8678.7-8684.10" + switch \builder_request [0] + attribute \src "ls180.v:8678.11-8678.29" + case 1'1 + assign $0\builder_grant[2:0] 3'000 + attribute \src "ls180.v:8680.11-8680.15" + case + attribute \src "ls180.v:8681.8-8683.11" + switch \builder_request [1] + attribute \src "ls180.v:8681.12-8681.30" + case 1'1 + assign $0\builder_grant[2:0] 3'001 + case + end + end + end + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'011 + attribute \src "ls180.v:8690.4-8706.7" + switch $not$ls180.v:8690$2678_Y + attribute \src "ls180.v:8690.8-8690.29" + case 1'1 + attribute \src "ls180.v:8691.5-8705.8" + switch \builder_request [4] + attribute \src "ls180.v:8691.9-8691.27" + case 1'1 + assign $0\builder_grant[2:0] 3'100 + attribute \src "ls180.v:8693.9-8693.13" + case + attribute \src "ls180.v:8694.6-8704.9" + switch \builder_request [0] + attribute \src "ls180.v:8694.10-8694.28" + case 1'1 + assign $0\builder_grant[2:0] 3'000 + attribute \src "ls180.v:8696.10-8696.14" + case + attribute \src "ls180.v:8697.7-8703.10" + switch \builder_request [1] + attribute \src "ls180.v:8697.11-8697.29" + case 1'1 + assign $0\builder_grant[2:0] 3'001 + attribute \src "ls180.v:8699.11-8699.15" + case + attribute \src "ls180.v:8700.8-8702.11" + switch \builder_request [2] + attribute \src "ls180.v:8700.12-8700.30" + case 1'1 + assign $0\builder_grant[2:0] 3'010 + case + end + end + end + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'100 + attribute \src "ls180.v:8709.4-8725.7" + switch $not$ls180.v:8709$2679_Y + attribute \src "ls180.v:8709.8-8709.29" + case 1'1 + attribute \src "ls180.v:8710.5-8724.8" + switch \builder_request [0] + attribute \src "ls180.v:8710.9-8710.27" + case 1'1 + assign $0\builder_grant[2:0] 3'000 + attribute \src "ls180.v:8712.9-8712.13" + case + attribute \src "ls180.v:8713.6-8723.9" + switch \builder_request [1] + attribute \src "ls180.v:8713.10-8713.28" + case 1'1 + assign $0\builder_grant[2:0] 3'001 + attribute \src "ls180.v:8715.10-8715.14" + case + attribute \src "ls180.v:8716.7-8722.10" + switch \builder_request [2] + attribute \src "ls180.v:8716.11-8716.29" + case 1'1 + assign $0\builder_grant[2:0] 3'010 + attribute \src "ls180.v:8718.11-8718.15" + case + attribute \src "ls180.v:8719.8-8721.11" + switch \builder_request [3] + attribute \src "ls180.v:8719.12-8719.30" + case 1'1 + assign $0\builder_grant[2:0] 3'011 + case + end + end + end + end + case + end + case + end + attribute \src "ls180.v:8729.2-8735.5" + switch \builder_wait + attribute \src "ls180.v:8729.6-8729.18" + case 1'1 + attribute \src "ls180.v:8730.3-8732.6" + switch $not$ls180.v:8730$2680_Y + attribute \src "ls180.v:8730.7-8730.22" + case 1'1 + assign $0\builder_count[19:0] $sub$ls180.v:8731$2681_Y + case + end + attribute \src "ls180.v:8733.6-8733.10" + case + assign $0\builder_count[19:0] 20'11110100001001000000 + end + attribute \src "ls180.v:8737.2-8767.5" + switch \builder_csrbank0_sel + attribute \src "ls180.v:8737.6-8737.26" + case 1'1 + attribute \src "ls180.v:8738.3-8766.10" + switch \builder_interface0_bank_bus_adr [3:0] + attribute \src "ls180.v:0.0-0.0" + case 4'0000 + assign $0\builder_interface0_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank0_reset0_w } + attribute \src "ls180.v:0.0-0.0" + case 4'0001 + assign $0\builder_interface0_bank_bus_dat_r[7:0] \builder_csrbank0_scratch3_w + attribute \src "ls180.v:0.0-0.0" + case 4'0010 + assign $0\builder_interface0_bank_bus_dat_r[7:0] \builder_csrbank0_scratch2_w + attribute \src "ls180.v:0.0-0.0" + case 4'0011 + assign $0\builder_interface0_bank_bus_dat_r[7:0] \builder_csrbank0_scratch1_w + attribute \src "ls180.v:0.0-0.0" + case 4'0100 + assign $0\builder_interface0_bank_bus_dat_r[7:0] \builder_csrbank0_scratch0_w + attribute \src "ls180.v:0.0-0.0" + case 4'0101 + assign $0\builder_interface0_bank_bus_dat_r[7:0] \builder_csrbank0_bus_errors3_w + attribute \src "ls180.v:0.0-0.0" + case 4'0110 + assign $0\builder_interface0_bank_bus_dat_r[7:0] \builder_csrbank0_bus_errors2_w + attribute \src "ls180.v:0.0-0.0" + case 4'0111 + assign $0\builder_interface0_bank_bus_dat_r[7:0] \builder_csrbank0_bus_errors1_w + attribute \src "ls180.v:0.0-0.0" + case 4'1000 + assign $0\builder_interface0_bank_bus_dat_r[7:0] \builder_csrbank0_bus_errors0_w + case + end + case + end + attribute \src "ls180.v:8768.2-8770.5" + switch \builder_csrbank0_reset0_re + attribute \src "ls180.v:8768.6-8768.32" + case 1'1 + assign $0\main_libresocsim_reset_storage[0:0] \builder_csrbank0_reset0_r + case + end + attribute \src "ls180.v:8772.2-8774.5" + switch \builder_csrbank0_scratch3_re + attribute \src "ls180.v:8772.6-8772.34" + case 1'1 + assign $0\main_libresocsim_scratch_storage[31:0] [31:24] \builder_csrbank0_scratch3_r + case + end + attribute \src "ls180.v:8775.2-8777.5" + switch \builder_csrbank0_scratch2_re + attribute \src "ls180.v:8775.6-8775.34" + case 1'1 + assign $0\main_libresocsim_scratch_storage[31:0] [23:16] \builder_csrbank0_scratch2_r + case + end + attribute \src "ls180.v:8778.2-8780.5" + switch \builder_csrbank0_scratch1_re + attribute \src "ls180.v:8778.6-8778.34" + case 1'1 + assign $0\main_libresocsim_scratch_storage[31:0] [15:8] \builder_csrbank0_scratch1_r + case + end + attribute \src "ls180.v:8781.2-8783.5" + switch \builder_csrbank0_scratch0_re + attribute \src "ls180.v:8781.6-8781.34" + case 1'1 + assign $0\main_libresocsim_scratch_storage[31:0] [7:0] \builder_csrbank0_scratch0_r + case + end + attribute \src "ls180.v:8786.2-8807.5" + switch \builder_csrbank1_sel + attribute \src "ls180.v:8786.6-8786.26" + case 1'1 + attribute \src "ls180.v:8787.3-8806.10" + switch \builder_interface1_bank_bus_adr [2:0] + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\builder_interface1_bank_bus_dat_r[7:0] \builder_csrbank1_oe1_w + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\builder_interface1_bank_bus_dat_r[7:0] \builder_csrbank1_oe0_w + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\builder_interface1_bank_bus_dat_r[7:0] \builder_csrbank1_in1_w + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\builder_interface1_bank_bus_dat_r[7:0] \builder_csrbank1_in0_w + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\builder_interface1_bank_bus_dat_r[7:0] \builder_csrbank1_out1_w + attribute \src "ls180.v:0.0-0.0" + case 3'101 + assign $0\builder_interface1_bank_bus_dat_r[7:0] \builder_csrbank1_out0_w + case + end + case + end + attribute \src "ls180.v:8808.2-8810.5" + switch \builder_csrbank1_oe1_re + attribute \src "ls180.v:8808.6-8808.29" + case 1'1 + assign $0\main_gpio_oe_storage[15:0] [15:8] \builder_csrbank1_oe1_r + case + end + attribute \src "ls180.v:8811.2-8813.5" + switch \builder_csrbank1_oe0_re + attribute \src "ls180.v:8811.6-8811.29" + case 1'1 + assign $0\main_gpio_oe_storage[15:0] [7:0] \builder_csrbank1_oe0_r + case + end + attribute \src "ls180.v:8815.2-8817.5" + switch \builder_csrbank1_out1_re + attribute \src "ls180.v:8815.6-8815.30" + case 1'1 + assign $0\main_gpio_out_storage[15:0] [15:8] \builder_csrbank1_out1_r + case + end + attribute \src "ls180.v:8818.2-8820.5" + switch \builder_csrbank1_out0_re + attribute \src "ls180.v:8818.6-8818.30" + case 1'1 + assign $0\main_gpio_out_storage[15:0] [7:0] \builder_csrbank1_out0_r + case + end + attribute \src "ls180.v:8823.2-8853.5" + switch \builder_csrbank2_sel + attribute \src "ls180.v:8823.6-8823.26" + case 1'1 + attribute \src "ls180.v:8824.3-8852.10" + switch \builder_interface2_bank_bus_adr [3:0] + attribute \src "ls180.v:0.0-0.0" + case 4'0000 + assign $0\builder_interface2_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank2_enable0_w } + attribute \src "ls180.v:0.0-0.0" + case 4'0001 + assign $0\builder_interface2_bank_bus_dat_r[7:0] \builder_csrbank2_width3_w + attribute \src "ls180.v:0.0-0.0" + case 4'0010 + assign $0\builder_interface2_bank_bus_dat_r[7:0] \builder_csrbank2_width2_w + attribute \src "ls180.v:0.0-0.0" + case 4'0011 + assign $0\builder_interface2_bank_bus_dat_r[7:0] \builder_csrbank2_width1_w + attribute \src "ls180.v:0.0-0.0" + case 4'0100 + assign $0\builder_interface2_bank_bus_dat_r[7:0] \builder_csrbank2_width0_w + attribute \src "ls180.v:0.0-0.0" + case 4'0101 + assign $0\builder_interface2_bank_bus_dat_r[7:0] \builder_csrbank2_period3_w + attribute \src "ls180.v:0.0-0.0" + case 4'0110 + assign $0\builder_interface2_bank_bus_dat_r[7:0] \builder_csrbank2_period2_w + attribute \src "ls180.v:0.0-0.0" + case 4'0111 + assign $0\builder_interface2_bank_bus_dat_r[7:0] \builder_csrbank2_period1_w + attribute \src "ls180.v:0.0-0.0" + case 4'1000 + assign $0\builder_interface2_bank_bus_dat_r[7:0] \builder_csrbank2_period0_w + case + end + case + end + attribute \src "ls180.v:8854.2-8856.5" + switch \builder_csrbank2_enable0_re + attribute \src "ls180.v:8854.6-8854.33" + case 1'1 + assign $0\main_pwm0_enable_storage[0:0] \builder_csrbank2_enable0_r + case + end + attribute \src "ls180.v:8858.2-8860.5" + switch \builder_csrbank2_width3_re + attribute \src "ls180.v:8858.6-8858.32" + case 1'1 + assign $0\main_pwm0_width_storage[31:0] [31:24] \builder_csrbank2_width3_r + case + end + attribute \src "ls180.v:8861.2-8863.5" + switch \builder_csrbank2_width2_re + attribute \src "ls180.v:8861.6-8861.32" + case 1'1 + assign $0\main_pwm0_width_storage[31:0] [23:16] \builder_csrbank2_width2_r + case + end + attribute \src "ls180.v:8864.2-8866.5" + switch \builder_csrbank2_width1_re + attribute \src "ls180.v:8864.6-8864.32" + case 1'1 + assign $0\main_pwm0_width_storage[31:0] [15:8] \builder_csrbank2_width1_r + case + end + attribute \src "ls180.v:8867.2-8869.5" + switch \builder_csrbank2_width0_re + attribute \src "ls180.v:8867.6-8867.32" + case 1'1 + assign $0\main_pwm0_width_storage[31:0] [7:0] \builder_csrbank2_width0_r + case + end + attribute \src "ls180.v:8871.2-8873.5" + switch \builder_csrbank2_period3_re + attribute \src "ls180.v:8871.6-8871.33" + case 1'1 + assign $0\main_pwm0_period_storage[31:0] [31:24] \builder_csrbank2_period3_r + case + end + attribute \src "ls180.v:8874.2-8876.5" + switch \builder_csrbank2_period2_re + attribute \src "ls180.v:8874.6-8874.33" + case 1'1 + assign $0\main_pwm0_period_storage[31:0] [23:16] \builder_csrbank2_period2_r + case + end + attribute \src "ls180.v:8877.2-8879.5" + switch \builder_csrbank2_period1_re + attribute \src "ls180.v:8877.6-8877.33" + case 1'1 + assign $0\main_pwm0_period_storage[31:0] [15:8] \builder_csrbank2_period1_r + case + end + attribute \src "ls180.v:8880.2-8882.5" + switch \builder_csrbank2_period0_re + attribute \src "ls180.v:8880.6-8880.33" + case 1'1 + assign $0\main_pwm0_period_storage[31:0] [7:0] \builder_csrbank2_period0_r + case + end + attribute \src "ls180.v:8885.2-8915.5" + switch \builder_csrbank3_sel + attribute \src "ls180.v:8885.6-8885.26" + case 1'1 + attribute \src "ls180.v:8886.3-8914.10" + switch \builder_interface3_bank_bus_adr [3:0] + attribute \src "ls180.v:0.0-0.0" + case 4'0000 + assign $0\builder_interface3_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank3_enable0_w } + attribute \src "ls180.v:0.0-0.0" + case 4'0001 + assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_width3_w + attribute \src "ls180.v:0.0-0.0" + case 4'0010 + assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_width2_w + attribute \src "ls180.v:0.0-0.0" + case 4'0011 + assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_width1_w + attribute \src "ls180.v:0.0-0.0" + case 4'0100 + assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_width0_w + attribute \src "ls180.v:0.0-0.0" + case 4'0101 + assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_period3_w + attribute \src "ls180.v:0.0-0.0" + case 4'0110 + assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_period2_w + attribute \src "ls180.v:0.0-0.0" + case 4'0111 + assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_period1_w + attribute \src "ls180.v:0.0-0.0" + case 4'1000 + assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_period0_w + case + end + case + end + attribute \src "ls180.v:8916.2-8918.5" + switch \builder_csrbank3_enable0_re + attribute \src "ls180.v:8916.6-8916.33" + case 1'1 + assign $0\main_pwm1_enable_storage[0:0] \builder_csrbank3_enable0_r + case + end + attribute \src "ls180.v:8920.2-8922.5" + switch \builder_csrbank3_width3_re + attribute \src "ls180.v:8920.6-8920.32" + case 1'1 + assign $0\main_pwm1_width_storage[31:0] [31:24] \builder_csrbank3_width3_r + case + end + attribute \src "ls180.v:8923.2-8925.5" + switch \builder_csrbank3_width2_re + attribute \src "ls180.v:8923.6-8923.32" + case 1'1 + assign $0\main_pwm1_width_storage[31:0] [23:16] \builder_csrbank3_width2_r + case + end + attribute \src "ls180.v:8926.2-8928.5" + switch \builder_csrbank3_width1_re + attribute \src "ls180.v:8926.6-8926.32" + case 1'1 + assign $0\main_pwm1_width_storage[31:0] [15:8] \builder_csrbank3_width1_r + case + end + attribute \src "ls180.v:8929.2-8931.5" + switch \builder_csrbank3_width0_re + attribute \src "ls180.v:8929.6-8929.32" + case 1'1 + assign $0\main_pwm1_width_storage[31:0] [7:0] \builder_csrbank3_width0_r + case + end + attribute \src "ls180.v:8933.2-8935.5" + switch \builder_csrbank3_period3_re + attribute \src "ls180.v:8933.6-8933.33" + case 1'1 + assign $0\main_pwm1_period_storage[31:0] [31:24] \builder_csrbank3_period3_r + case + end + attribute \src "ls180.v:8936.2-8938.5" + switch \builder_csrbank3_period2_re + attribute \src "ls180.v:8936.6-8936.33" + case 1'1 + assign $0\main_pwm1_period_storage[31:0] [23:16] \builder_csrbank3_period2_r + case + end + attribute \src "ls180.v:8939.2-8941.5" + switch \builder_csrbank3_period1_re + attribute \src "ls180.v:8939.6-8939.33" + case 1'1 + assign $0\main_pwm1_period_storage[31:0] [15:8] \builder_csrbank3_period1_r + case + end + attribute \src "ls180.v:8942.2-8944.5" + switch \builder_csrbank3_period0_re + attribute \src "ls180.v:8942.6-8942.33" + case 1'1 + assign $0\main_pwm1_period_storage[31:0] [7:0] \builder_csrbank3_period0_r + case + end + attribute \src "ls180.v:8947.2-8995.5" + switch \builder_csrbank4_sel + attribute \src "ls180.v:8947.6-8947.26" + case 1'1 + attribute \src "ls180.v:8948.3-8994.10" + switch \builder_interface4_bank_bus_adr [3:0] + attribute \src "ls180.v:0.0-0.0" + case 4'0000 + assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_dma_base7_w + attribute \src "ls180.v:0.0-0.0" + case 4'0001 + assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_dma_base6_w + attribute \src "ls180.v:0.0-0.0" + case 4'0010 + assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_dma_base5_w + attribute \src "ls180.v:0.0-0.0" + case 4'0011 + assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_dma_base4_w + attribute \src "ls180.v:0.0-0.0" + case 4'0100 + assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_dma_base3_w + attribute \src "ls180.v:0.0-0.0" + case 4'0101 + assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_dma_base2_w + attribute \src "ls180.v:0.0-0.0" + case 4'0110 + assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_dma_base1_w + attribute \src "ls180.v:0.0-0.0" + case 4'0111 + assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_dma_base0_w + attribute \src "ls180.v:0.0-0.0" + case 4'1000 + assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_dma_length3_w + attribute \src "ls180.v:0.0-0.0" + case 4'1001 + assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_dma_length2_w + attribute \src "ls180.v:0.0-0.0" + case 4'1010 + assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_dma_length1_w + attribute \src "ls180.v:0.0-0.0" + case 4'1011 + assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_dma_length0_w + attribute \src "ls180.v:0.0-0.0" + case 4'1100 + assign $0\builder_interface4_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank4_dma_enable0_w } + attribute \src "ls180.v:0.0-0.0" + case 4'1101 + assign $0\builder_interface4_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank4_dma_done_w } + attribute \src "ls180.v:0.0-0.0" + case 4'1110 + assign $0\builder_interface4_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank4_dma_loop0_w } + case + end + case + end + attribute \src "ls180.v:8996.2-8998.5" + switch \builder_csrbank4_dma_base7_re + attribute \src "ls180.v:8996.6-8996.35" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [63:56] \builder_csrbank4_dma_base7_r + case + end + attribute \src "ls180.v:8999.2-9001.5" + switch \builder_csrbank4_dma_base6_re + attribute \src "ls180.v:8999.6-8999.35" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [55:48] \builder_csrbank4_dma_base6_r + case + end + attribute \src "ls180.v:9002.2-9004.5" + switch \builder_csrbank4_dma_base5_re + attribute \src "ls180.v:9002.6-9002.35" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [47:40] \builder_csrbank4_dma_base5_r + case + end + attribute \src "ls180.v:9005.2-9007.5" + switch \builder_csrbank4_dma_base4_re + attribute \src "ls180.v:9005.6-9005.35" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [39:32] \builder_csrbank4_dma_base4_r + case + end + attribute \src "ls180.v:9008.2-9010.5" + switch \builder_csrbank4_dma_base3_re + attribute \src "ls180.v:9008.6-9008.35" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [31:24] \builder_csrbank4_dma_base3_r + case + end + attribute \src "ls180.v:9011.2-9013.5" + switch \builder_csrbank4_dma_base2_re + attribute \src "ls180.v:9011.6-9011.35" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [23:16] \builder_csrbank4_dma_base2_r + case + end + attribute \src "ls180.v:9014.2-9016.5" + switch \builder_csrbank4_dma_base1_re + attribute \src "ls180.v:9014.6-9014.35" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [15:8] \builder_csrbank4_dma_base1_r + case + end + attribute \src "ls180.v:9017.2-9019.5" + switch \builder_csrbank4_dma_base0_re + attribute \src "ls180.v:9017.6-9017.35" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [7:0] \builder_csrbank4_dma_base0_r + case + end + attribute \src "ls180.v:9021.2-9023.5" + switch \builder_csrbank4_dma_length3_re + attribute \src "ls180.v:9021.6-9021.37" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] [31:24] \builder_csrbank4_dma_length3_r + case + end + attribute \src "ls180.v:9024.2-9026.5" + switch \builder_csrbank4_dma_length2_re + attribute \src "ls180.v:9024.6-9024.37" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] [23:16] \builder_csrbank4_dma_length2_r + case + end + attribute \src "ls180.v:9027.2-9029.5" + switch \builder_csrbank4_dma_length1_re + attribute \src "ls180.v:9027.6-9027.37" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] [15:8] \builder_csrbank4_dma_length1_r + case + end + attribute \src "ls180.v:9030.2-9032.5" + switch \builder_csrbank4_dma_length0_re + attribute \src "ls180.v:9030.6-9030.37" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] [7:0] \builder_csrbank4_dma_length0_r + case + end + attribute \src "ls180.v:9034.2-9036.5" + switch \builder_csrbank4_dma_enable0_re + attribute \src "ls180.v:9034.6-9034.37" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] \builder_csrbank4_dma_enable0_r + case + end + attribute \src "ls180.v:9038.2-9040.5" + switch \builder_csrbank4_dma_loop0_re + attribute \src "ls180.v:9038.6-9038.35" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] \builder_csrbank4_dma_loop0_r + case + end + attribute \src "ls180.v:9043.2-9145.5" + switch \builder_csrbank5_sel + attribute \src "ls180.v:9043.6-9043.26" + case 1'1 + attribute \src "ls180.v:9044.3-9144.10" + switch \builder_interface5_bank_bus_adr [5:0] + attribute \src "ls180.v:0.0-0.0" + case 6'000000 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_cmd_argument3_w + attribute \src "ls180.v:0.0-0.0" + case 6'000001 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_cmd_argument2_w + attribute \src "ls180.v:0.0-0.0" + case 6'000010 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_cmd_argument1_w + attribute \src "ls180.v:0.0-0.0" + case 6'000011 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_cmd_argument0_w + attribute \src "ls180.v:0.0-0.0" + case 6'000100 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_cmd_command3_w + attribute \src "ls180.v:0.0-0.0" + case 6'000101 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_cmd_command2_w + attribute \src "ls180.v:0.0-0.0" + case 6'000110 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_cmd_command1_w + attribute \src "ls180.v:0.0-0.0" + case 6'000111 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_cmd_command0_w + attribute \src "ls180.v:0.0-0.0" + case 6'001000 + assign $0\builder_interface5_bank_bus_dat_r[7:0] { 7'0000000 \main_sdcore_cmd_send_w } + attribute \src "ls180.v:0.0-0.0" + case 6'001001 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_cmd_response15_w + attribute \src "ls180.v:0.0-0.0" + case 6'001010 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_cmd_response14_w + attribute \src "ls180.v:0.0-0.0" + case 6'001011 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_cmd_response13_w + attribute \src "ls180.v:0.0-0.0" + case 6'001100 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_cmd_response12_w + attribute \src "ls180.v:0.0-0.0" + case 6'001101 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_cmd_response11_w + attribute \src "ls180.v:0.0-0.0" + case 6'001110 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_cmd_response10_w + attribute \src "ls180.v:0.0-0.0" + case 6'001111 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_cmd_response9_w + attribute \src "ls180.v:0.0-0.0" + case 6'010000 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_cmd_response8_w + attribute \src "ls180.v:0.0-0.0" + case 6'010001 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_cmd_response7_w + attribute \src "ls180.v:0.0-0.0" + case 6'010010 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_cmd_response6_w + attribute \src "ls180.v:0.0-0.0" + case 6'010011 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_cmd_response5_w + attribute \src "ls180.v:0.0-0.0" + case 6'010100 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_cmd_response4_w + attribute \src "ls180.v:0.0-0.0" + case 6'010101 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_cmd_response3_w + attribute \src "ls180.v:0.0-0.0" + case 6'010110 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_cmd_response2_w + attribute \src "ls180.v:0.0-0.0" + case 6'010111 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_cmd_response1_w + attribute \src "ls180.v:0.0-0.0" + case 6'011000 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_cmd_response0_w + attribute \src "ls180.v:0.0-0.0" + case 6'011001 + assign $0\builder_interface5_bank_bus_dat_r[7:0] { 4'0000 \builder_csrbank5_cmd_event_w } + attribute \src "ls180.v:0.0-0.0" + case 6'011010 + assign $0\builder_interface5_bank_bus_dat_r[7:0] { 4'0000 \builder_csrbank5_data_event_w } + attribute \src "ls180.v:0.0-0.0" + case 6'011011 + assign $0\builder_interface5_bank_bus_dat_r[7:0] { 6'000000 \builder_csrbank5_block_length1_w } + attribute \src "ls180.v:0.0-0.0" + case 6'011100 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_block_length0_w + attribute \src "ls180.v:0.0-0.0" + case 6'011101 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_block_count3_w + attribute \src "ls180.v:0.0-0.0" + case 6'011110 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_block_count2_w + attribute \src "ls180.v:0.0-0.0" + case 6'011111 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_block_count1_w + attribute \src "ls180.v:0.0-0.0" + case 6'100000 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_block_count0_w + case + end + case + end + attribute \src "ls180.v:9146.2-9148.5" + switch \builder_csrbank5_cmd_argument3_re + attribute \src "ls180.v:9146.6-9146.39" + case 1'1 + assign $0\main_sdcore_cmd_argument_storage[31:0] [31:24] \builder_csrbank5_cmd_argument3_r + case + end + attribute \src "ls180.v:9149.2-9151.5" + switch \builder_csrbank5_cmd_argument2_re + attribute \src "ls180.v:9149.6-9149.39" + case 1'1 + assign $0\main_sdcore_cmd_argument_storage[31:0] [23:16] \builder_csrbank5_cmd_argument2_r + case + end + attribute \src "ls180.v:9152.2-9154.5" + switch \builder_csrbank5_cmd_argument1_re + attribute \src "ls180.v:9152.6-9152.39" + case 1'1 + assign $0\main_sdcore_cmd_argument_storage[31:0] [15:8] \builder_csrbank5_cmd_argument1_r + case + end + attribute \src "ls180.v:9155.2-9157.5" + switch \builder_csrbank5_cmd_argument0_re + attribute \src "ls180.v:9155.6-9155.39" + case 1'1 + assign $0\main_sdcore_cmd_argument_storage[31:0] [7:0] \builder_csrbank5_cmd_argument0_r + case + end + attribute \src "ls180.v:9159.2-9161.5" + switch \builder_csrbank5_cmd_command3_re + attribute \src "ls180.v:9159.6-9159.38" + case 1'1 + assign $0\main_sdcore_cmd_command_storage[31:0] [31:24] \builder_csrbank5_cmd_command3_r + case + end + attribute \src "ls180.v:9162.2-9164.5" + switch \builder_csrbank5_cmd_command2_re + attribute \src "ls180.v:9162.6-9162.38" + case 1'1 + assign $0\main_sdcore_cmd_command_storage[31:0] [23:16] \builder_csrbank5_cmd_command2_r + case + end + attribute \src "ls180.v:9165.2-9167.5" + switch \builder_csrbank5_cmd_command1_re + attribute \src "ls180.v:9165.6-9165.38" + case 1'1 + assign $0\main_sdcore_cmd_command_storage[31:0] [15:8] \builder_csrbank5_cmd_command1_r + case + end + attribute \src "ls180.v:9168.2-9170.5" + switch \builder_csrbank5_cmd_command0_re + attribute \src "ls180.v:9168.6-9168.38" + case 1'1 + assign $0\main_sdcore_cmd_command_storage[31:0] [7:0] \builder_csrbank5_cmd_command0_r + case + end + attribute \src "ls180.v:9172.2-9174.5" + switch \builder_csrbank5_block_length1_re + attribute \src "ls180.v:9172.6-9172.39" + case 1'1 + assign $0\main_sdcore_block_length_storage[9:0] [9:8] \builder_csrbank5_block_length1_r + case + end + attribute \src "ls180.v:9175.2-9177.5" + switch \builder_csrbank5_block_length0_re + attribute \src "ls180.v:9175.6-9175.39" + case 1'1 + assign $0\main_sdcore_block_length_storage[9:0] [7:0] \builder_csrbank5_block_length0_r + case + end + attribute \src "ls180.v:9179.2-9181.5" + switch \builder_csrbank5_block_count3_re + attribute \src "ls180.v:9179.6-9179.38" + case 1'1 + assign $0\main_sdcore_block_count_storage[31:0] [31:24] \builder_csrbank5_block_count3_r + case + end + attribute \src "ls180.v:9182.2-9184.5" + switch \builder_csrbank5_block_count2_re + attribute \src "ls180.v:9182.6-9182.38" + case 1'1 + assign $0\main_sdcore_block_count_storage[31:0] [23:16] \builder_csrbank5_block_count2_r + case + end + attribute \src "ls180.v:9185.2-9187.5" + switch \builder_csrbank5_block_count1_re + attribute \src "ls180.v:9185.6-9185.38" + case 1'1 + assign $0\main_sdcore_block_count_storage[31:0] [15:8] \builder_csrbank5_block_count1_r + case + end + attribute \src "ls180.v:9188.2-9190.5" + switch \builder_csrbank5_block_count0_re + attribute \src "ls180.v:9188.6-9188.38" + case 1'1 + assign $0\main_sdcore_block_count_storage[31:0] [7:0] \builder_csrbank5_block_count0_r + case + end + attribute \src "ls180.v:9193.2-9253.5" + switch \builder_csrbank6_sel + attribute \src "ls180.v:9193.6-9193.26" + case 1'1 + attribute \src "ls180.v:9194.3-9252.10" + switch \builder_interface6_bank_bus_adr [4:0] + attribute \src "ls180.v:0.0-0.0" + case 5'00000 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_dma_base7_w + attribute \src "ls180.v:0.0-0.0" + case 5'00001 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_dma_base6_w + attribute \src "ls180.v:0.0-0.0" + case 5'00010 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_dma_base5_w + attribute \src "ls180.v:0.0-0.0" + case 5'00011 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_dma_base4_w + attribute \src "ls180.v:0.0-0.0" + case 5'00100 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_dma_base3_w + attribute \src "ls180.v:0.0-0.0" + case 5'00101 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_dma_base2_w + attribute \src "ls180.v:0.0-0.0" + case 5'00110 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_dma_base1_w + attribute \src "ls180.v:0.0-0.0" + case 5'00111 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_dma_base0_w + attribute \src "ls180.v:0.0-0.0" + case 5'01000 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_dma_length3_w + attribute \src "ls180.v:0.0-0.0" + case 5'01001 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_dma_length2_w + attribute \src "ls180.v:0.0-0.0" + case 5'01010 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_dma_length1_w + attribute \src "ls180.v:0.0-0.0" + case 5'01011 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_dma_length0_w + attribute \src "ls180.v:0.0-0.0" + case 5'01100 + assign $0\builder_interface6_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank6_dma_enable0_w } + attribute \src "ls180.v:0.0-0.0" + case 5'01101 + assign $0\builder_interface6_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank6_dma_done_w } + attribute \src "ls180.v:0.0-0.0" + case 5'01110 + assign $0\builder_interface6_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank6_dma_loop0_w } + attribute \src "ls180.v:0.0-0.0" + case 5'01111 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_dma_offset3_w + attribute \src "ls180.v:0.0-0.0" + case 5'10000 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_dma_offset2_w + attribute \src "ls180.v:0.0-0.0" + case 5'10001 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_dma_offset1_w + attribute \src "ls180.v:0.0-0.0" + case 5'10010 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_dma_offset0_w + case + end + case + end + attribute \src "ls180.v:9254.2-9256.5" + switch \builder_csrbank6_dma_base7_re + attribute \src "ls180.v:9254.6-9254.35" + case 1'1 + assign $0\main_sdmem2block_dma_base_storage[63:0] [63:56] \builder_csrbank6_dma_base7_r + case + end + attribute \src "ls180.v:9257.2-9259.5" + switch \builder_csrbank6_dma_base6_re + attribute \src "ls180.v:9257.6-9257.35" + case 1'1 + assign $0\main_sdmem2block_dma_base_storage[63:0] [55:48] \builder_csrbank6_dma_base6_r + case + end + attribute \src "ls180.v:9260.2-9262.5" + switch \builder_csrbank6_dma_base5_re + attribute \src "ls180.v:9260.6-9260.35" + case 1'1 + assign $0\main_sdmem2block_dma_base_storage[63:0] [47:40] \builder_csrbank6_dma_base5_r + case + end + attribute \src "ls180.v:9263.2-9265.5" + switch \builder_csrbank6_dma_base4_re + attribute \src "ls180.v:9263.6-9263.35" + case 1'1 + assign $0\main_sdmem2block_dma_base_storage[63:0] [39:32] \builder_csrbank6_dma_base4_r + case + end + attribute \src "ls180.v:9266.2-9268.5" + switch \builder_csrbank6_dma_base3_re + attribute \src "ls180.v:9266.6-9266.35" + case 1'1 + assign $0\main_sdmem2block_dma_base_storage[63:0] [31:24] \builder_csrbank6_dma_base3_r + case + end + attribute \src "ls180.v:9269.2-9271.5" + switch \builder_csrbank6_dma_base2_re + attribute \src "ls180.v:9269.6-9269.35" + case 1'1 + assign $0\main_sdmem2block_dma_base_storage[63:0] [23:16] \builder_csrbank6_dma_base2_r + case + end + attribute \src "ls180.v:9272.2-9274.5" + switch \builder_csrbank6_dma_base1_re + attribute \src "ls180.v:9272.6-9272.35" + case 1'1 + assign $0\main_sdmem2block_dma_base_storage[63:0] [15:8] \builder_csrbank6_dma_base1_r + case + end + attribute \src "ls180.v:9275.2-9277.5" + switch \builder_csrbank6_dma_base0_re + attribute \src "ls180.v:9275.6-9275.35" + case 1'1 + assign $0\main_sdmem2block_dma_base_storage[63:0] [7:0] \builder_csrbank6_dma_base0_r + case + end + attribute \src "ls180.v:9279.2-9281.5" + switch \builder_csrbank6_dma_length3_re + attribute \src "ls180.v:9279.6-9279.37" + case 1'1 + assign $0\main_sdmem2block_dma_length_storage[31:0] [31:24] \builder_csrbank6_dma_length3_r + case + end + attribute \src "ls180.v:9282.2-9284.5" + switch \builder_csrbank6_dma_length2_re + attribute \src "ls180.v:9282.6-9282.37" + case 1'1 + assign $0\main_sdmem2block_dma_length_storage[31:0] [23:16] \builder_csrbank6_dma_length2_r + case + end + attribute \src "ls180.v:9285.2-9287.5" + switch \builder_csrbank6_dma_length1_re + attribute \src "ls180.v:9285.6-9285.37" + case 1'1 + assign $0\main_sdmem2block_dma_length_storage[31:0] [15:8] \builder_csrbank6_dma_length1_r + case + end + attribute \src "ls180.v:9288.2-9290.5" + switch \builder_csrbank6_dma_length0_re + attribute \src "ls180.v:9288.6-9288.37" + case 1'1 + assign $0\main_sdmem2block_dma_length_storage[31:0] [7:0] \builder_csrbank6_dma_length0_r + case + end + attribute \src "ls180.v:9292.2-9294.5" + switch \builder_csrbank6_dma_enable0_re + attribute \src "ls180.v:9292.6-9292.37" + case 1'1 + assign $0\main_sdmem2block_dma_enable_storage[0:0] \builder_csrbank6_dma_enable0_r + case + end + attribute \src "ls180.v:9296.2-9298.5" + switch \builder_csrbank6_dma_loop0_re + attribute \src "ls180.v:9296.6-9296.35" + case 1'1 + assign $0\main_sdmem2block_dma_loop_storage[0:0] \builder_csrbank6_dma_loop0_r + case + end + attribute \src "ls180.v:9301.2-9316.5" + switch \builder_csrbank7_sel + attribute \src "ls180.v:9301.6-9301.26" + case 1'1 + attribute \src "ls180.v:9302.3-9315.10" + switch \builder_interface7_bank_bus_adr [1:0] + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_interface7_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank7_card_detect_w } + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_interface7_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank7_clocker_divider1_w } + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_clocker_divider0_w + attribute \src "ls180.v:0.0-0.0" + case 2'11 + assign $0\builder_interface7_bank_bus_dat_r[7:0] { 7'0000000 \main_sdphy_init_initialize_w } + case + end + case + end + attribute \src "ls180.v:9317.2-9319.5" + switch \builder_csrbank7_clocker_divider1_re + attribute \src "ls180.v:9317.6-9317.42" + case 1'1 + assign $0\main_sdphy_clocker_storage[8:0] [8] \builder_csrbank7_clocker_divider1_r + case + end + attribute \src "ls180.v:9320.2-9322.5" + switch \builder_csrbank7_clocker_divider0_re + attribute \src "ls180.v:9320.6-9320.42" + case 1'1 + assign $0\main_sdphy_clocker_storage[8:0] [7:0] \builder_csrbank7_clocker_divider0_r + case + end + attribute \src "ls180.v:9325.2-9358.5" + switch \builder_csrbank8_sel + attribute \src "ls180.v:9325.6-9325.26" + case 1'1 + attribute \src "ls180.v:9326.3-9357.10" + switch \builder_interface8_bank_bus_adr [3:0] + attribute \src "ls180.v:0.0-0.0" + case 4'0000 + assign $0\builder_interface8_bank_bus_dat_r[7:0] { 4'0000 \builder_csrbank8_dfii_control0_w } + attribute \src "ls180.v:0.0-0.0" + case 4'0001 + assign $0\builder_interface8_bank_bus_dat_r[7:0] { 2'00 \builder_csrbank8_dfii_pi0_command0_w } + attribute \src "ls180.v:0.0-0.0" + case 4'0010 + assign $0\builder_interface8_bank_bus_dat_r[7:0] { 7'0000000 \main_sdram_command_issue_w } + attribute \src "ls180.v:0.0-0.0" + case 4'0011 + assign $0\builder_interface8_bank_bus_dat_r[7:0] { 3'000 \builder_csrbank8_dfii_pi0_address1_w } + attribute \src "ls180.v:0.0-0.0" + case 4'0100 + assign $0\builder_interface8_bank_bus_dat_r[7:0] \builder_csrbank8_dfii_pi0_address0_w + attribute \src "ls180.v:0.0-0.0" + case 4'0101 + assign $0\builder_interface8_bank_bus_dat_r[7:0] { 6'000000 \builder_csrbank8_dfii_pi0_baddress0_w } + attribute \src "ls180.v:0.0-0.0" + case 4'0110 + assign $0\builder_interface8_bank_bus_dat_r[7:0] \builder_csrbank8_dfii_pi0_wrdata1_w + attribute \src "ls180.v:0.0-0.0" + case 4'0111 + assign $0\builder_interface8_bank_bus_dat_r[7:0] \builder_csrbank8_dfii_pi0_wrdata0_w + attribute \src "ls180.v:0.0-0.0" + case 4'1000 + assign $0\builder_interface8_bank_bus_dat_r[7:0] \builder_csrbank8_dfii_pi0_rddata1_w + attribute \src "ls180.v:0.0-0.0" + case 4'1001 + assign $0\builder_interface8_bank_bus_dat_r[7:0] \builder_csrbank8_dfii_pi0_rddata0_w + case + end + case + end + attribute \src "ls180.v:9359.2-9361.5" + switch \builder_csrbank8_dfii_control0_re + attribute \src "ls180.v:9359.6-9359.39" + case 1'1 + assign $0\main_sdram_storage[3:0] \builder_csrbank8_dfii_control0_r + case + end + attribute \src "ls180.v:9363.2-9365.5" + switch \builder_csrbank8_dfii_pi0_command0_re + attribute \src "ls180.v:9363.6-9363.43" + case 1'1 + assign $0\main_sdram_command_storage[5:0] \builder_csrbank8_dfii_pi0_command0_r + case + end + attribute \src "ls180.v:9367.2-9369.5" + switch \builder_csrbank8_dfii_pi0_address1_re + attribute \src "ls180.v:9367.6-9367.43" + case 1'1 + assign $0\main_sdram_address_storage[12:0] [12:8] \builder_csrbank8_dfii_pi0_address1_r + case + end + attribute \src "ls180.v:9370.2-9372.5" + switch \builder_csrbank8_dfii_pi0_address0_re + attribute \src "ls180.v:9370.6-9370.43" + case 1'1 + assign $0\main_sdram_address_storage[12:0] [7:0] \builder_csrbank8_dfii_pi0_address0_r + case + end + attribute \src "ls180.v:9374.2-9376.5" + switch \builder_csrbank8_dfii_pi0_baddress0_re + attribute \src "ls180.v:9374.6-9374.44" + case 1'1 + assign $0\main_sdram_baddress_storage[1:0] \builder_csrbank8_dfii_pi0_baddress0_r + case + end + attribute \src "ls180.v:9378.2-9380.5" + switch \builder_csrbank8_dfii_pi0_wrdata1_re + attribute \src "ls180.v:9378.6-9378.42" + case 1'1 + assign $0\main_sdram_wrdata_storage[15:0] [15:8] \builder_csrbank8_dfii_pi0_wrdata1_r + case + end + attribute \src "ls180.v:9381.2-9383.5" + switch \builder_csrbank8_dfii_pi0_wrdata0_re + attribute \src "ls180.v:9381.6-9381.42" + case 1'1 + assign $0\main_sdram_wrdata_storage[15:0] [7:0] \builder_csrbank8_dfii_pi0_wrdata0_r + case + end + attribute \src "ls180.v:9386.2-9410.5" + switch \builder_csrbank9_sel + attribute \src "ls180.v:9386.6-9386.26" + case 1'1 + attribute \src "ls180.v:9387.3-9409.10" + switch \builder_interface9_bank_bus_adr [2:0] + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\builder_interface9_bank_bus_dat_r[7:0] \builder_csrbank9_control1_w + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\builder_interface9_bank_bus_dat_r[7:0] \builder_csrbank9_control0_w + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\builder_interface9_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank9_status_w } + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\builder_interface9_bank_bus_dat_r[7:0] \builder_csrbank9_mosi0_w + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\builder_interface9_bank_bus_dat_r[7:0] \builder_csrbank9_miso_w + attribute \src "ls180.v:0.0-0.0" + case 3'101 + assign $0\builder_interface9_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank9_cs0_w } + attribute \src "ls180.v:0.0-0.0" + case 3'110 + assign $0\builder_interface9_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank9_loopback0_w } + case + end + case + end + attribute \src "ls180.v:9411.2-9413.5" + switch \builder_csrbank9_control1_re + attribute \src "ls180.v:9411.6-9411.34" + case 1'1 + assign $0\main_spi_master_control_storage[15:0] [15:8] \builder_csrbank9_control1_r + case + end + attribute \src "ls180.v:9414.2-9416.5" + switch \builder_csrbank9_control0_re + attribute \src "ls180.v:9414.6-9414.34" + case 1'1 + assign $0\main_spi_master_control_storage[15:0] [7:0] \builder_csrbank9_control0_r + case + end + attribute \src "ls180.v:9418.2-9420.5" + switch \builder_csrbank9_mosi0_re + attribute \src "ls180.v:9418.6-9418.31" + case 1'1 + assign $0\main_spi_master_mosi_storage[7:0] \builder_csrbank9_mosi0_r + case + end + attribute \src "ls180.v:9422.2-9424.5" + switch \builder_csrbank9_cs0_re + attribute \src "ls180.v:9422.6-9422.29" + case 1'1 + assign $0\main_spi_master_cs_storage[0:0] \builder_csrbank9_cs0_r + case + end + attribute \src "ls180.v:9426.2-9428.5" + switch \builder_csrbank9_loopback0_re + attribute \src "ls180.v:9426.6-9426.35" + case 1'1 + assign $0\main_spi_master_loopback_storage[0:0] \builder_csrbank9_loopback0_r + case + end + attribute \src "ls180.v:9431.2-9461.5" + switch \builder_csrbank10_sel + attribute \src "ls180.v:9431.6-9431.27" + case 1'1 + attribute \src "ls180.v:9432.3-9460.10" + switch \builder_interface10_bank_bus_adr [3:0] + attribute \src "ls180.v:0.0-0.0" + case 4'0000 + assign $0\builder_interface10_bank_bus_dat_r[7:0] \builder_csrbank10_control1_w + attribute \src "ls180.v:0.0-0.0" + case 4'0001 + assign $0\builder_interface10_bank_bus_dat_r[7:0] \builder_csrbank10_control0_w + attribute \src "ls180.v:0.0-0.0" + case 4'0010 + assign $0\builder_interface10_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank10_status_w } + attribute \src "ls180.v:0.0-0.0" + case 4'0011 + assign $0\builder_interface10_bank_bus_dat_r[7:0] \builder_csrbank10_mosi0_w + attribute \src "ls180.v:0.0-0.0" + case 4'0100 + assign $0\builder_interface10_bank_bus_dat_r[7:0] \builder_csrbank10_miso_w + attribute \src "ls180.v:0.0-0.0" + case 4'0101 + assign $0\builder_interface10_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank10_cs0_w } + attribute \src "ls180.v:0.0-0.0" + case 4'0110 + assign $0\builder_interface10_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank10_loopback0_w } + attribute \src "ls180.v:0.0-0.0" + case 4'0111 + assign $0\builder_interface10_bank_bus_dat_r[7:0] \builder_csrbank10_clk_divider1_w + attribute \src "ls180.v:0.0-0.0" + case 4'1000 + assign $0\builder_interface10_bank_bus_dat_r[7:0] \builder_csrbank10_clk_divider0_w + case + end + case + end + attribute \src "ls180.v:9462.2-9464.5" + switch \builder_csrbank10_control1_re + attribute \src "ls180.v:9462.6-9462.35" + case 1'1 + assign $0\libresocsim_control_storage[15:0] [15:8] \builder_csrbank10_control1_r + case + end + attribute \src "ls180.v:9465.2-9467.5" + switch \builder_csrbank10_control0_re + attribute \src "ls180.v:9465.6-9465.35" + case 1'1 + assign $0\libresocsim_control_storage[15:0] [7:0] \builder_csrbank10_control0_r + case + end + attribute \src "ls180.v:9469.2-9471.5" + switch \builder_csrbank10_mosi0_re + attribute \src "ls180.v:9469.6-9469.32" + case 1'1 + assign $0\libresocsim_mosi_storage[7:0] \builder_csrbank10_mosi0_r + case + end + attribute \src "ls180.v:9473.2-9475.5" + switch \builder_csrbank10_cs0_re + attribute \src "ls180.v:9473.6-9473.30" + case 1'1 + assign $0\libresocsim_cs_storage[0:0] \builder_csrbank10_cs0_r + case + end + attribute \src "ls180.v:9477.2-9479.5" + switch \builder_csrbank10_loopback0_re + attribute \src "ls180.v:9477.6-9477.36" + case 1'1 + assign $0\libresocsim_loopback_storage[0:0] \builder_csrbank10_loopback0_r + case + end + attribute \src "ls180.v:9481.2-9483.5" + switch \builder_csrbank10_clk_divider1_re + attribute \src "ls180.v:9481.6-9481.39" + case 1'1 + assign $0\libresocsim_storage[15:0] [15:8] \builder_csrbank10_clk_divider1_r + case + end + attribute \src "ls180.v:9484.2-9486.5" + switch \builder_csrbank10_clk_divider0_re + attribute \src "ls180.v:9484.6-9484.39" + case 1'1 + assign $0\libresocsim_storage[15:0] [7:0] \builder_csrbank10_clk_divider0_r + case + end + attribute \src "ls180.v:9489.2-9543.5" + switch \builder_csrbank11_sel + attribute \src "ls180.v:9489.6-9489.27" + case 1'1 + attribute \src "ls180.v:9490.3-9542.10" + switch \builder_interface11_bank_bus_adr [4:0] + attribute \src "ls180.v:0.0-0.0" + case 5'00000 + assign $0\builder_interface11_bank_bus_dat_r[7:0] \builder_csrbank11_load3_w + attribute \src "ls180.v:0.0-0.0" + case 5'00001 + assign $0\builder_interface11_bank_bus_dat_r[7:0] \builder_csrbank11_load2_w + attribute \src "ls180.v:0.0-0.0" + case 5'00010 + assign $0\builder_interface11_bank_bus_dat_r[7:0] \builder_csrbank11_load1_w + attribute \src "ls180.v:0.0-0.0" + case 5'00011 + assign $0\builder_interface11_bank_bus_dat_r[7:0] \builder_csrbank11_load0_w + attribute \src "ls180.v:0.0-0.0" + case 5'00100 + assign $0\builder_interface11_bank_bus_dat_r[7:0] \builder_csrbank11_reload3_w + attribute \src "ls180.v:0.0-0.0" + case 5'00101 + assign $0\builder_interface11_bank_bus_dat_r[7:0] \builder_csrbank11_reload2_w + attribute \src "ls180.v:0.0-0.0" + case 5'00110 + assign $0\builder_interface11_bank_bus_dat_r[7:0] \builder_csrbank11_reload1_w + attribute \src "ls180.v:0.0-0.0" + case 5'00111 + assign $0\builder_interface11_bank_bus_dat_r[7:0] \builder_csrbank11_reload0_w + attribute \src "ls180.v:0.0-0.0" + case 5'01000 + assign $0\builder_interface11_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank11_en0_w } + attribute \src "ls180.v:0.0-0.0" + case 5'01001 + assign $0\builder_interface11_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank11_update_value0_w } + attribute \src "ls180.v:0.0-0.0" + case 5'01010 + assign $0\builder_interface11_bank_bus_dat_r[7:0] \builder_csrbank11_value3_w + attribute \src "ls180.v:0.0-0.0" + case 5'01011 + assign $0\builder_interface11_bank_bus_dat_r[7:0] \builder_csrbank11_value2_w + attribute \src "ls180.v:0.0-0.0" + case 5'01100 + assign $0\builder_interface11_bank_bus_dat_r[7:0] \builder_csrbank11_value1_w + attribute \src "ls180.v:0.0-0.0" + case 5'01101 + assign $0\builder_interface11_bank_bus_dat_r[7:0] \builder_csrbank11_value0_w + attribute \src "ls180.v:0.0-0.0" + case 5'01110 + assign $0\builder_interface11_bank_bus_dat_r[7:0] { 7'0000000 \main_libresocsim_eventmanager_status_w } + attribute \src "ls180.v:0.0-0.0" + case 5'01111 + assign $0\builder_interface11_bank_bus_dat_r[7:0] { 7'0000000 \main_libresocsim_eventmanager_pending_w } + attribute \src "ls180.v:0.0-0.0" + case 5'10000 + assign $0\builder_interface11_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank11_ev_enable0_w } + case + end + case + end + attribute \src "ls180.v:9544.2-9546.5" + switch \builder_csrbank11_load3_re + attribute \src "ls180.v:9544.6-9544.32" + case 1'1 + assign $0\main_libresocsim_load_storage[31:0] [31:24] \builder_csrbank11_load3_r + case + end + attribute \src "ls180.v:9547.2-9549.5" + switch \builder_csrbank11_load2_re + attribute \src "ls180.v:9547.6-9547.32" + case 1'1 + assign $0\main_libresocsim_load_storage[31:0] [23:16] \builder_csrbank11_load2_r + case + end + attribute \src "ls180.v:9550.2-9552.5" + switch \builder_csrbank11_load1_re + attribute \src "ls180.v:9550.6-9550.32" + case 1'1 + assign $0\main_libresocsim_load_storage[31:0] [15:8] \builder_csrbank11_load1_r + case + end + attribute \src "ls180.v:9553.2-9555.5" + switch \builder_csrbank11_load0_re + attribute \src "ls180.v:9553.6-9553.32" + case 1'1 + assign $0\main_libresocsim_load_storage[31:0] [7:0] \builder_csrbank11_load0_r + case + end + attribute \src "ls180.v:9557.2-9559.5" + switch \builder_csrbank11_reload3_re + attribute \src "ls180.v:9557.6-9557.34" + case 1'1 + assign $0\main_libresocsim_reload_storage[31:0] [31:24] \builder_csrbank11_reload3_r + case + end + attribute \src "ls180.v:9560.2-9562.5" + switch \builder_csrbank11_reload2_re + attribute \src "ls180.v:9560.6-9560.34" + case 1'1 + assign $0\main_libresocsim_reload_storage[31:0] [23:16] \builder_csrbank11_reload2_r + case + end + attribute \src "ls180.v:9563.2-9565.5" + switch \builder_csrbank11_reload1_re + attribute \src "ls180.v:9563.6-9563.34" + case 1'1 + assign $0\main_libresocsim_reload_storage[31:0] [15:8] \builder_csrbank11_reload1_r + case + end + attribute \src "ls180.v:9566.2-9568.5" + switch \builder_csrbank11_reload0_re + attribute \src "ls180.v:9566.6-9566.34" + case 1'1 + assign $0\main_libresocsim_reload_storage[31:0] [7:0] \builder_csrbank11_reload0_r + case + end + attribute \src "ls180.v:9570.2-9572.5" + switch \builder_csrbank11_en0_re + attribute \src "ls180.v:9570.6-9570.30" + case 1'1 + assign $0\main_libresocsim_en_storage[0:0] \builder_csrbank11_en0_r + case + end + attribute \src "ls180.v:9574.2-9576.5" + switch \builder_csrbank11_update_value0_re + attribute \src "ls180.v:9574.6-9574.40" + case 1'1 + assign $0\main_libresocsim_update_value_storage[0:0] \builder_csrbank11_update_value0_r + case + end + attribute \src "ls180.v:9578.2-9580.5" + switch \builder_csrbank11_ev_enable0_re + attribute \src "ls180.v:9578.6-9578.37" + case 1'1 + assign $0\main_libresocsim_eventmanager_storage[0:0] \builder_csrbank11_ev_enable0_r + case + end + attribute \src "ls180.v:9583.2-9610.5" + switch \builder_csrbank12_sel + attribute \src "ls180.v:9583.6-9583.27" + case 1'1 + attribute \src "ls180.v:9584.3-9609.10" + switch \builder_interface12_bank_bus_adr [2:0] + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\builder_interface12_bank_bus_dat_r[7:0] \main_uart_rxtx_w + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\builder_interface12_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank12_txfull_w } + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\builder_interface12_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank12_rxempty_w } + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\builder_interface12_bank_bus_dat_r[7:0] { 6'000000 \main_uart_eventmanager_status_w } + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\builder_interface12_bank_bus_dat_r[7:0] { 6'000000 \main_uart_eventmanager_pending_w } + attribute \src "ls180.v:0.0-0.0" + case 3'101 + assign $0\builder_interface12_bank_bus_dat_r[7:0] { 6'000000 \builder_csrbank12_ev_enable0_w } + attribute \src "ls180.v:0.0-0.0" + case 3'110 + assign $0\builder_interface12_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank12_txempty_w } + attribute \src "ls180.v:0.0-0.0" + case 3'111 + assign $0\builder_interface12_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank12_rxfull_w } + case + end + case + end + attribute \src "ls180.v:9611.2-9613.5" + switch \builder_csrbank12_ev_enable0_re + attribute \src "ls180.v:9611.6-9611.37" + case 1'1 + assign $0\main_uart_eventmanager_storage[1:0] \builder_csrbank12_ev_enable0_r + case + end + attribute \src "ls180.v:9616.2-9631.5" + switch \builder_csrbank13_sel + attribute \src "ls180.v:9616.6-9616.27" + case 1'1 + attribute \src "ls180.v:9617.3-9630.10" + switch \builder_interface13_bank_bus_adr [1:0] + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_interface13_bank_bus_dat_r[7:0] \builder_csrbank13_tuning_word3_w + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_interface13_bank_bus_dat_r[7:0] \builder_csrbank13_tuning_word2_w + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_interface13_bank_bus_dat_r[7:0] \builder_csrbank13_tuning_word1_w + attribute \src "ls180.v:0.0-0.0" + case 2'11 + assign $0\builder_interface13_bank_bus_dat_r[7:0] \builder_csrbank13_tuning_word0_w + case + end + case + end + attribute \src "ls180.v:9632.2-9634.5" + switch \builder_csrbank13_tuning_word3_re + attribute \src "ls180.v:9632.6-9632.39" + case 1'1 + assign $0\main_storage[31:0] [31:24] \builder_csrbank13_tuning_word3_r + case + end + attribute \src "ls180.v:9635.2-9637.5" + switch \builder_csrbank13_tuning_word2_re + attribute \src "ls180.v:9635.6-9635.39" + case 1'1 + assign $0\main_storage[31:0] [23:16] \builder_csrbank13_tuning_word2_r + case + end + attribute \src "ls180.v:9638.2-9640.5" + switch \builder_csrbank13_tuning_word1_re + attribute \src "ls180.v:9638.6-9638.39" + case 1'1 + assign $0\main_storage[31:0] [15:8] \builder_csrbank13_tuning_word1_r + case + end + attribute \src "ls180.v:9641.2-9643.5" + switch \builder_csrbank13_tuning_word0_re + attribute \src "ls180.v:9641.6-9641.39" + case 1'1 + assign $0\main_storage[31:0] [7:0] \builder_csrbank13_tuning_word0_r + case + end + attribute \src "ls180.v:9645.2-9938.5" + switch \sys_rst_1 + attribute \src "ls180.v:9645.6-9645.15" + case 1'1 + assign $0\main_libresocsim_reset_storage[0:0] 1'0 + assign $0\main_libresocsim_reset_re[0:0] 1'0 + assign $0\main_libresocsim_scratch_storage[31:0] 305419896 + assign $0\main_libresocsim_scratch_re[0:0] 1'0 + assign $0\main_libresocsim_bus_errors[31:0] 0 + assign $0\main_libresocsim_libresoc_constraintmanager0_uart0_tx[0:0] 1'1 + assign $0\main_libresocsim_converter0_counter[0:0] 1'0 + assign $0\main_libresocsim_converter1_counter[0:0] 1'0 + assign $0\main_libresocsim_converter2_counter[0:0] 1'0 + assign $0\main_libresocsim_ram_bus_ack[0:0] 1'0 + assign $0\main_libresocsim_load_storage[31:0] 0 + assign $0\main_libresocsim_load_re[0:0] 1'0 + assign $0\main_libresocsim_reload_storage[31:0] 0 + assign $0\main_libresocsim_reload_re[0:0] 1'0 + assign $0\main_libresocsim_en_storage[0:0] 1'0 + assign $0\main_libresocsim_en_re[0:0] 1'0 + assign $0\main_libresocsim_update_value_storage[0:0] 1'0 + assign $0\main_libresocsim_update_value_re[0:0] 1'0 + assign $0\main_libresocsim_value_status[31:0] 0 + assign $0\main_libresocsim_zero_pending[0:0] 1'0 + assign $0\main_libresocsim_zero_old_trigger[0:0] 1'0 + assign $0\main_libresocsim_eventmanager_storage[0:0] 1'0 + assign $0\main_libresocsim_eventmanager_re[0:0] 1'0 + assign $0\main_libresocsim_value[31:0] 0 + assign $0\main_dfi_p0_rddata_valid[0:0] 1'0 + assign $0\main_rddata_en[2:0] 3'000 + assign $0\main_sdram_storage[3:0] 4'0001 + assign $0\main_sdram_re[0:0] 1'0 + assign $0\main_sdram_command_storage[5:0] 6'000000 + assign $0\main_sdram_command_re[0:0] 1'0 + assign $0\main_sdram_address_re[0:0] 1'0 + assign $0\main_sdram_baddress_re[0:0] 1'0 + assign $0\main_sdram_wrdata_re[0:0] 1'0 + assign $0\main_sdram_status[15:0] 16'0000000000000000 + assign $0\main_sdram_dfi_p0_address[12:0] 13'0000000000000 + assign $0\main_sdram_dfi_p0_bank[1:0] 2'00 + assign $0\main_sdram_dfi_p0_cas_n[0:0] 1'1 + assign $0\main_sdram_dfi_p0_cs_n[0:0] 1'1 + assign $0\main_sdram_dfi_p0_ras_n[0:0] 1'1 + assign $0\main_sdram_dfi_p0_we_n[0:0] 1'1 + assign $0\main_sdram_dfi_p0_wrdata_en[0:0] 1'0 + assign $0\main_sdram_dfi_p0_rddata_en[0:0] 1'0 + assign $0\main_sdram_timer_count1[9:0] 10'1100001101 + assign $0\main_sdram_postponer_req_o[0:0] 1'0 + assign $0\main_sdram_postponer_count[0:0] 1'0 + assign $0\main_sdram_sequencer_done1[0:0] 1'0 + assign $0\main_sdram_sequencer_counter[3:0] 4'0000 + assign $0\main_sdram_sequencer_count[0:0] 1'0 + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] 4'0000 + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] 3'000 + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] 3'000 + assign $0\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] 1'0 + assign $0\main_sdram_bankmachine0_row[12:0] 13'0000000000000 + assign $0\main_sdram_bankmachine0_row_opened[0:0] 1'0 + assign $0\main_sdram_bankmachine0_twtpcon_ready[0:0] 1'0 + assign $0\main_sdram_bankmachine0_twtpcon_count[2:0] 3'000 + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] 4'0000 + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] 3'000 + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] 3'000 + assign $0\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] 1'0 + assign $0\main_sdram_bankmachine1_row[12:0] 13'0000000000000 + assign $0\main_sdram_bankmachine1_row_opened[0:0] 1'0 + assign $0\main_sdram_bankmachine1_twtpcon_ready[0:0] 1'0 + assign $0\main_sdram_bankmachine1_twtpcon_count[2:0] 3'000 + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] 4'0000 + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] 3'000 + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] 3'000 + assign $0\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] 1'0 + assign $0\main_sdram_bankmachine2_row[12:0] 13'0000000000000 + assign $0\main_sdram_bankmachine2_row_opened[0:0] 1'0 + assign $0\main_sdram_bankmachine2_twtpcon_ready[0:0] 1'0 + assign $0\main_sdram_bankmachine2_twtpcon_count[2:0] 3'000 + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] 4'0000 + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] 3'000 + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] 3'000 + assign $0\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] 1'0 + assign $0\main_sdram_bankmachine3_row[12:0] 13'0000000000000 + assign $0\main_sdram_bankmachine3_row_opened[0:0] 1'0 + assign $0\main_sdram_bankmachine3_twtpcon_ready[0:0] 1'0 + assign $0\main_sdram_bankmachine3_twtpcon_count[2:0] 3'000 + assign $0\main_sdram_choose_cmd_grant[1:0] 2'00 + assign $0\main_sdram_choose_req_grant[1:0] 2'00 + assign $0\main_sdram_tccdcon_ready[0:0] 1'0 + assign $0\main_sdram_tccdcon_count[0:0] 1'0 + assign $0\main_sdram_twtrcon_ready[0:0] 1'0 + assign $0\main_sdram_twtrcon_count[2:0] 3'000 + assign $0\main_sdram_time0[4:0] 5'00000 + assign $0\main_sdram_time1[3:0] 4'0000 + assign $0\main_converter_counter[0:0] 1'0 + assign $0\main_cmd_consumed[0:0] 1'0 + assign $0\main_wdata_consumed[0:0] 1'0 + assign $0\main_storage[31:0] 9895604 + assign $0\main_re[0:0] 1'0 + assign $0\main_sink_ready[0:0] 1'0 + assign $0\main_uart_clk_txen[0:0] 1'0 + assign $0\main_tx_busy[0:0] 1'0 + assign $0\main_source_valid[0:0] 1'0 + assign $0\main_uart_clk_rxen[0:0] 1'0 + assign $0\main_rx_r[0:0] 1'0 + assign $0\main_rx_busy[0:0] 1'0 + assign $0\main_uart_tx_pending[0:0] 1'0 + assign $0\main_uart_tx_old_trigger[0:0] 1'0 + assign $0\main_uart_rx_pending[0:0] 1'0 + assign $0\main_uart_rx_old_trigger[0:0] 1'0 + assign $0\main_uart_eventmanager_storage[1:0] 2'00 + assign $0\main_uart_eventmanager_re[0:0] 1'0 + assign $0\main_uart_tx_fifo_readable[0:0] 1'0 + assign $0\main_uart_tx_fifo_level0[4:0] 5'00000 + assign $0\main_uart_tx_fifo_produce[3:0] 4'0000 + assign $0\main_uart_tx_fifo_consume[3:0] 4'0000 + assign $0\main_uart_rx_fifo_readable[0:0] 1'0 + assign $0\main_uart_rx_fifo_level0[4:0] 5'00000 + assign $0\main_uart_rx_fifo_produce[3:0] 4'0000 + assign $0\main_uart_rx_fifo_consume[3:0] 4'0000 + assign $0\main_gpio_oe_storage[15:0] 16'0000000000000000 + assign $0\main_gpio_oe_re[0:0] 1'0 + assign $0\main_gpio_out_storage[15:0] 16'0000000000000000 + assign $0\main_gpio_out_re[0:0] 1'0 + assign $0\spi_master_clk[0:0] 1'0 + assign $0\spi_master_mosi[0:0] 1'0 + assign $0\spi_master_cs_n[0:0] 1'0 + assign $0\main_spi_master_miso[7:0] 8'00000000 + assign $0\main_spi_master_control_storage[15:0] 16'0000000000000000 + assign $0\main_spi_master_control_re[0:0] 1'0 + assign $0\main_spi_master_mosi_re[0:0] 1'0 + assign $0\main_spi_master_cs_storage[0:0] 1'1 + assign $0\main_spi_master_cs_re[0:0] 1'0 + assign $0\main_spi_master_loopback_storage[0:0] 1'0 + assign $0\main_spi_master_loopback_re[0:0] 1'0 + assign $0\main_spi_master_count[2:0] 3'000 + assign $0\main_spi_master_clk_divider1[15:0] 16'0000000000000000 + assign $0\main_spi_master_mosi_data[7:0] 8'00000000 + assign $0\main_spi_master_mosi_sel[2:0] 3'000 + assign $0\main_spi_master_miso_data[7:0] 8'00000000 + assign $0\main_dummy[41:0] 42'000000000000000000000000000000000000000000 + assign $0\pwm0[0:0] 1'0 + assign $0\main_pwm0_enable_storage[0:0] 1'0 + assign $0\main_pwm0_enable_re[0:0] 1'0 + assign $0\main_pwm0_width_re[0:0] 1'0 + assign $0\main_pwm0_period_re[0:0] 1'0 + assign $0\pwm1[0:0] 1'0 + assign $0\main_pwm1_enable_storage[0:0] 1'0 + assign $0\main_pwm1_enable_re[0:0] 1'0 + assign $0\main_pwm1_width_re[0:0] 1'0 + assign $0\main_pwm1_period_re[0:0] 1'0 + assign $0\main_sdphy_clocker_storage[8:0] 9'100000000 + assign $0\main_sdphy_clocker_re[0:0] 1'0 + assign $0\main_sdphy_clocker_clk0[0:0] 1'0 + assign $0\main_sdphy_clocker_clks[8:0] 9'000000000 + assign $0\main_sdphy_clocker_clk_d[0:0] 1'0 + assign $0\main_sdphy_init_count[7:0] 8'00000000 + assign $0\main_sdphy_cmdw_count[7:0] 8'00000000 + assign $0\main_sdphy_cmdr_timeout[31:0] 500000 + assign $0\main_sdphy_cmdr_count[7:0] 8'00000000 + assign $0\main_sdphy_cmdr_cmdr_run[0:0] 1'0 + assign $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] 3'000 + assign $0\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] 1'0 + assign $0\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] 1'0 + assign $0\main_sdphy_cmdr_cmdr_reset[0:0] 1'0 + assign $0\main_sdphy_dataw_count[7:0] 8'00000000 + assign $0\main_sdphy_dataw_crcr_run[0:0] 1'0 + assign $0\main_sdphy_dataw_crcr_converter_demux[2:0] 3'000 + assign $0\main_sdphy_dataw_crcr_converter_strobe_all[0:0] 1'0 + assign $0\main_sdphy_dataw_crcr_buf_source_valid[0:0] 1'0 + assign $0\main_sdphy_dataw_crcr_reset[0:0] 1'0 + assign $0\main_sdphy_datar_timeout[31:0] 500000 + assign $0\main_sdphy_datar_count[9:0] 10'0000000000 + assign $0\main_sdphy_datar_datar_run[0:0] 1'0 + assign $0\main_sdphy_datar_datar_converter_demux[0:0] 1'0 + assign $0\main_sdphy_datar_datar_converter_strobe_all[0:0] 1'0 + assign $0\main_sdphy_datar_datar_buf_source_valid[0:0] 1'0 + assign $0\main_sdphy_datar_datar_reset[0:0] 1'0 + assign $0\main_sdcore_cmd_argument_storage[31:0] 0 + assign $0\main_sdcore_cmd_argument_re[0:0] 1'0 + assign $0\main_sdcore_cmd_command_storage[31:0] 0 + assign $0\main_sdcore_cmd_command_re[0:0] 1'0 + assign $0\main_sdcore_cmd_response_status[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign $0\main_sdcore_block_length_storage[9:0] 10'0000000000 + assign $0\main_sdcore_block_length_re[0:0] 1'0 + assign $0\main_sdcore_block_count_storage[31:0] 0 + assign $0\main_sdcore_block_count_re[0:0] 1'0 + assign $0\main_sdcore_crc7_inserter_crcreg0[6:0] 7'0000000 + assign $0\main_sdcore_crc16_inserter_cnt[2:0] 3'000 + assign $0\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_inserter_crctmp0[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_inserter_crctmp1[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_inserter_crctmp2[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_inserter_crctmp3[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_checker_val[7:0] 8'00000000 + assign $0\main_sdcore_crc16_checker_cnt[3:0] 4'0000 + assign $0\main_sdcore_crc16_checker_crc0_crcreg0[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_checker_crc1_crcreg0[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_checker_crc2_crcreg0[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_checker_crc3_crcreg0[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_checker_crctmp0[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_checker_crctmp1[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_checker_crctmp2[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_checker_crctmp3[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_checker_fifo0[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_checker_fifo1[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_checker_fifo2[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_checker_fifo3[15:0] 16'0000000000000000 + assign $0\main_sdcore_cmd_count[2:0] 3'000 + assign $0\main_sdcore_cmd_done[0:0] 1'0 + assign $0\main_sdcore_cmd_error[0:0] 1'0 + assign $0\main_sdcore_cmd_timeout[0:0] 1'0 + assign $0\main_sdcore_data_count[31:0] 0 + assign $0\main_sdcore_data_done[0:0] 1'0 + assign $0\main_sdcore_data_error[0:0] 1'0 + assign $0\main_sdcore_data_timeout[0:0] 1'0 + assign $0\main_sdblock2mem_fifo_level[5:0] 6'000000 + assign $0\main_sdblock2mem_fifo_produce[4:0] 5'00000 + assign $0\main_sdblock2mem_fifo_consume[4:0] 5'00000 + assign $0\main_sdblock2mem_converter_demux[1:0] 2'00 + assign $0\main_sdblock2mem_converter_strobe_all[0:0] 1'0 + assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\main_sdblock2mem_wishbonedmawriter_base_re[0:0] 1'0 + assign $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] 0 + assign $0\main_sdblock2mem_wishbonedmawriter_length_re[0:0] 1'0 + assign $0\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] 1'0 + assign $0\main_sdblock2mem_wishbonedmawriter_enable_re[0:0] 1'0 + assign $0\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] 1'0 + assign $0\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] 1'0 + assign $0\main_sdblock2mem_wishbonedmawriter_offset[31:0] 0 + assign $0\main_sdmem2block_dma_data[31:0] 0 + assign $0\main_sdmem2block_dma_base_storage[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\main_sdmem2block_dma_base_re[0:0] 1'0 + assign $0\main_sdmem2block_dma_length_storage[31:0] 0 + assign $0\main_sdmem2block_dma_length_re[0:0] 1'0 + assign $0\main_sdmem2block_dma_enable_storage[0:0] 1'0 + assign $0\main_sdmem2block_dma_enable_re[0:0] 1'0 + assign $0\main_sdmem2block_dma_loop_storage[0:0] 1'0 + assign $0\main_sdmem2block_dma_loop_re[0:0] 1'0 + assign $0\main_sdmem2block_dma_offset[31:0] 0 + assign $0\main_sdmem2block_converter_mux[1:0] 2'00 + assign $0\main_sdmem2block_fifo_level[5:0] 6'000000 + assign $0\main_sdmem2block_fifo_produce[4:0] 5'00000 + assign $0\main_sdmem2block_fifo_consume[4:0] 5'00000 + assign $0\spisdcard_clk[0:0] 1'0 + assign $0\spisdcard_mosi[0:0] 1'0 + assign $0\spisdcard_cs_n[0:0] 1'0 + assign $0\libresocsim_miso[7:0] 8'00000000 + assign $0\libresocsim_control_storage[15:0] 16'0000000000000000 + assign $0\libresocsim_control_re[0:0] 1'0 + assign $0\libresocsim_mosi_re[0:0] 1'0 + assign $0\libresocsim_cs_storage[0:0] 1'1 + assign $0\libresocsim_cs_re[0:0] 1'0 + assign $0\libresocsim_loopback_storage[0:0] 1'0 + assign $0\libresocsim_loopback_re[0:0] 1'0 + assign $0\libresocsim_count[2:0] 3'000 + assign $0\libresocsim_clk_divider1[15:0] 16'0000000000000000 + assign $0\libresocsim_mosi_data[7:0] 8'00000000 + assign $0\libresocsim_mosi_sel[2:0] 3'000 + assign $0\libresocsim_miso_data[7:0] 8'00000000 + assign $0\libresocsim_storage[15:0] 16'0000000001111101 + assign $0\libresocsim_re[0:0] 1'0 + assign $0\builder_converter0_state[0:0] 1'0 + assign $0\builder_converter1_state[0:0] 1'0 + assign $0\builder_converter2_state[0:0] 1'0 + assign $0\builder_refresher_state[1:0] 2'00 + assign $0\builder_bankmachine0_state[2:0] 3'000 + assign $0\builder_bankmachine1_state[2:0] 3'000 + assign $0\builder_bankmachine2_state[2:0] 3'000 + assign $0\builder_bankmachine3_state[2:0] 3'000 + assign $0\builder_multiplexer_state[2:0] 3'000 + assign $0\builder_new_master_wdata_ready[0:0] 1'0 + assign $0\builder_new_master_rdata_valid0[0:0] 1'0 + assign $0\builder_new_master_rdata_valid1[0:0] 1'0 + assign $0\builder_new_master_rdata_valid2[0:0] 1'0 + assign $0\builder_new_master_rdata_valid3[0:0] 1'0 + assign $0\builder_converter_state[0:0] 1'0 + assign $0\builder_spimaster0_state[1:0] 2'00 + assign $0\builder_sdphy_sdphyinit_state[0:0] 1'0 + assign $0\builder_sdphy_sdphycmdw_state[1:0] 2'00 + assign $0\builder_sdphy_sdphycmdr_state[2:0] 3'000 + assign $0\builder_sdphy_sdphycrcr_state[0:0] 1'0 + assign $0\builder_sdphy_fsm_state[2:0] 3'000 + assign $0\builder_sdphy_sdphydatar_state[2:0] 3'000 + assign $0\builder_sdcore_crcupstreaminserter_state[0:0] 1'0 + assign $0\builder_sdcore_fsm_state[2:0] 3'000 + assign $0\builder_sdblock2memdma_state[1:0] 2'00 + assign $0\builder_sdmem2blockdma_fsm_state[0:0] 1'0 + assign $0\builder_sdmem2blockdma_resetinserter_state[1:0] 2'00 + assign $0\builder_spimaster1_state[1:0] 2'00 + assign $0\builder_libresocsim_we[0:0] 1'0 + assign $0\builder_grant[2:0] 3'000 + assign $0\builder_slave_sel_r[4:0] 5'00000 + assign $0\builder_count[19:0] 20'11110100001001000000 + assign $0\builder_state[1:0] 2'00 + case + end + sync posedge \sys_clk_1 + update \spi_master_clk $0\spi_master_clk[0:0] + update \spi_master_mosi $0\spi_master_mosi[0:0] + update \spi_master_cs_n $0\spi_master_cs_n[0:0] + update \pwm0 $0\pwm0[0:0] + update \pwm1 $0\pwm1[0:0] + update \spisdcard_clk $0\spisdcard_clk[0:0] + update \spisdcard_mosi $0\spisdcard_mosi[0:0] + update \spisdcard_cs_n $0\spisdcard_cs_n[0:0] + update \main_libresocsim_reset_storage $0\main_libresocsim_reset_storage[0:0] + update \main_libresocsim_reset_re $0\main_libresocsim_reset_re[0:0] + update \main_libresocsim_scratch_storage $0\main_libresocsim_scratch_storage[31:0] + update \main_libresocsim_scratch_re $0\main_libresocsim_scratch_re[0:0] + update \main_libresocsim_bus_errors $0\main_libresocsim_bus_errors[31:0] + update \main_libresocsim_libresoc_constraintmanager0_uart0_tx $0\main_libresocsim_libresoc_constraintmanager0_uart0_tx[0:0] + update \main_libresocsim_converter0_counter $0\main_libresocsim_converter0_counter[0:0] + update \main_libresocsim_converter0_dat_r $0\main_libresocsim_converter0_dat_r[63:0] + update \main_libresocsim_converter1_counter $0\main_libresocsim_converter1_counter[0:0] + update \main_libresocsim_converter1_dat_r $0\main_libresocsim_converter1_dat_r[63:0] + update \main_libresocsim_converter2_counter $0\main_libresocsim_converter2_counter[0:0] + update \main_libresocsim_converter2_dat_r $0\main_libresocsim_converter2_dat_r[63:0] + update \main_libresocsim_ram_bus_ack $0\main_libresocsim_ram_bus_ack[0:0] + update \main_libresocsim_load_storage $0\main_libresocsim_load_storage[31:0] + update \main_libresocsim_load_re $0\main_libresocsim_load_re[0:0] + update \main_libresocsim_reload_storage $0\main_libresocsim_reload_storage[31:0] + update \main_libresocsim_reload_re $0\main_libresocsim_reload_re[0:0] + update \main_libresocsim_en_storage $0\main_libresocsim_en_storage[0:0] + update \main_libresocsim_en_re $0\main_libresocsim_en_re[0:0] + update \main_libresocsim_update_value_storage $0\main_libresocsim_update_value_storage[0:0] + update \main_libresocsim_update_value_re $0\main_libresocsim_update_value_re[0:0] + update \main_libresocsim_value_status $0\main_libresocsim_value_status[31:0] + update \main_libresocsim_zero_pending $0\main_libresocsim_zero_pending[0:0] + update \main_libresocsim_zero_old_trigger $0\main_libresocsim_zero_old_trigger[0:0] + update \main_libresocsim_eventmanager_storage $0\main_libresocsim_eventmanager_storage[0:0] + update \main_libresocsim_eventmanager_re $0\main_libresocsim_eventmanager_re[0:0] + update \main_libresocsim_value $0\main_libresocsim_value[31:0] + update \main_dfi_p0_rddata_valid $0\main_dfi_p0_rddata_valid[0:0] + update \main_rddata_en $0\main_rddata_en[2:0] + update \main_sdram_storage $0\main_sdram_storage[3:0] + update \main_sdram_re $0\main_sdram_re[0:0] + update \main_sdram_command_storage $0\main_sdram_command_storage[5:0] + update \main_sdram_command_re $0\main_sdram_command_re[0:0] + update \main_sdram_address_storage $0\main_sdram_address_storage[12:0] + update \main_sdram_address_re $0\main_sdram_address_re[0:0] + update \main_sdram_baddress_storage $0\main_sdram_baddress_storage[1:0] + update \main_sdram_baddress_re $0\main_sdram_baddress_re[0:0] + update \main_sdram_wrdata_storage $0\main_sdram_wrdata_storage[15:0] + update \main_sdram_wrdata_re $0\main_sdram_wrdata_re[0:0] + update \main_sdram_status $0\main_sdram_status[15:0] + update \main_sdram_dfi_p0_address $0\main_sdram_dfi_p0_address[12:0] + update \main_sdram_dfi_p0_bank $0\main_sdram_dfi_p0_bank[1:0] + update \main_sdram_dfi_p0_cas_n $0\main_sdram_dfi_p0_cas_n[0:0] + update \main_sdram_dfi_p0_cs_n $0\main_sdram_dfi_p0_cs_n[0:0] + update \main_sdram_dfi_p0_ras_n $0\main_sdram_dfi_p0_ras_n[0:0] + update \main_sdram_dfi_p0_we_n $0\main_sdram_dfi_p0_we_n[0:0] + update \main_sdram_dfi_p0_wrdata_en $0\main_sdram_dfi_p0_wrdata_en[0:0] + update \main_sdram_dfi_p0_rddata_en $0\main_sdram_dfi_p0_rddata_en[0:0] + update \main_sdram_cmd_payload_a $0\main_sdram_cmd_payload_a[12:0] + update \main_sdram_cmd_payload_ba $0\main_sdram_cmd_payload_ba[1:0] + update \main_sdram_cmd_payload_cas $0\main_sdram_cmd_payload_cas[0:0] + update \main_sdram_cmd_payload_ras $0\main_sdram_cmd_payload_ras[0:0] + update \main_sdram_cmd_payload_we $0\main_sdram_cmd_payload_we[0:0] + update \main_sdram_timer_count1 $0\main_sdram_timer_count1[9:0] + update \main_sdram_postponer_req_o $0\main_sdram_postponer_req_o[0:0] + update \main_sdram_postponer_count $0\main_sdram_postponer_count[0:0] + update \main_sdram_sequencer_done1 $0\main_sdram_sequencer_done1[0:0] + update \main_sdram_sequencer_counter $0\main_sdram_sequencer_counter[3:0] + update \main_sdram_sequencer_count $0\main_sdram_sequencer_count[0:0] + update \main_sdram_bankmachine0_cmd_buffer_lookahead_level $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] + update \main_sdram_bankmachine0_cmd_buffer_lookahead_produce $0\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] + update \main_sdram_bankmachine0_cmd_buffer_lookahead_consume $0\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] + update \main_sdram_bankmachine0_cmd_buffer_source_valid $0\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] + update \main_sdram_bankmachine0_cmd_buffer_source_first $0\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] + update \main_sdram_bankmachine0_cmd_buffer_source_last $0\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] + update \main_sdram_bankmachine0_cmd_buffer_source_payload_we $0\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] + update \main_sdram_bankmachine0_cmd_buffer_source_payload_addr $0\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] + update \main_sdram_bankmachine0_row $0\main_sdram_bankmachine0_row[12:0] + update \main_sdram_bankmachine0_row_opened $0\main_sdram_bankmachine0_row_opened[0:0] + update \main_sdram_bankmachine0_twtpcon_ready $0\main_sdram_bankmachine0_twtpcon_ready[0:0] + update \main_sdram_bankmachine0_twtpcon_count $0\main_sdram_bankmachine0_twtpcon_count[2:0] + update \main_sdram_bankmachine1_cmd_buffer_lookahead_level $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] + update \main_sdram_bankmachine1_cmd_buffer_lookahead_produce $0\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] + update \main_sdram_bankmachine1_cmd_buffer_lookahead_consume $0\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] + update \main_sdram_bankmachine1_cmd_buffer_source_valid $0\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] + update \main_sdram_bankmachine1_cmd_buffer_source_first $0\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] + update \main_sdram_bankmachine1_cmd_buffer_source_last $0\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] + update \main_sdram_bankmachine1_cmd_buffer_source_payload_we $0\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] + update \main_sdram_bankmachine1_cmd_buffer_source_payload_addr $0\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] + update \main_sdram_bankmachine1_row $0\main_sdram_bankmachine1_row[12:0] + update \main_sdram_bankmachine1_row_opened $0\main_sdram_bankmachine1_row_opened[0:0] + update \main_sdram_bankmachine1_twtpcon_ready $0\main_sdram_bankmachine1_twtpcon_ready[0:0] + update \main_sdram_bankmachine1_twtpcon_count $0\main_sdram_bankmachine1_twtpcon_count[2:0] + update \main_sdram_bankmachine2_cmd_buffer_lookahead_level $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] + update \main_sdram_bankmachine2_cmd_buffer_lookahead_produce $0\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] + update \main_sdram_bankmachine2_cmd_buffer_lookahead_consume $0\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] + update \main_sdram_bankmachine2_cmd_buffer_source_valid $0\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] + update \main_sdram_bankmachine2_cmd_buffer_source_first $0\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] + update \main_sdram_bankmachine2_cmd_buffer_source_last $0\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] + update \main_sdram_bankmachine2_cmd_buffer_source_payload_we $0\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] + update \main_sdram_bankmachine2_cmd_buffer_source_payload_addr $0\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] + update \main_sdram_bankmachine2_row $0\main_sdram_bankmachine2_row[12:0] + update \main_sdram_bankmachine2_row_opened $0\main_sdram_bankmachine2_row_opened[0:0] + update \main_sdram_bankmachine2_twtpcon_ready $0\main_sdram_bankmachine2_twtpcon_ready[0:0] + update \main_sdram_bankmachine2_twtpcon_count $0\main_sdram_bankmachine2_twtpcon_count[2:0] + update \main_sdram_bankmachine3_cmd_buffer_lookahead_level $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] + update \main_sdram_bankmachine3_cmd_buffer_lookahead_produce $0\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] + update \main_sdram_bankmachine3_cmd_buffer_lookahead_consume $0\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] + update \main_sdram_bankmachine3_cmd_buffer_source_valid $0\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] + update \main_sdram_bankmachine3_cmd_buffer_source_first $0\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] + update \main_sdram_bankmachine3_cmd_buffer_source_last $0\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] + update \main_sdram_bankmachine3_cmd_buffer_source_payload_we $0\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] + update \main_sdram_bankmachine3_cmd_buffer_source_payload_addr $0\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] + update \main_sdram_bankmachine3_row $0\main_sdram_bankmachine3_row[12:0] + update \main_sdram_bankmachine3_row_opened $0\main_sdram_bankmachine3_row_opened[0:0] + update \main_sdram_bankmachine3_twtpcon_ready $0\main_sdram_bankmachine3_twtpcon_ready[0:0] + update \main_sdram_bankmachine3_twtpcon_count $0\main_sdram_bankmachine3_twtpcon_count[2:0] + update \main_sdram_choose_cmd_grant $0\main_sdram_choose_cmd_grant[1:0] + update \main_sdram_choose_req_grant $0\main_sdram_choose_req_grant[1:0] + update \main_sdram_tccdcon_ready $0\main_sdram_tccdcon_ready[0:0] + update \main_sdram_tccdcon_count $0\main_sdram_tccdcon_count[0:0] + update \main_sdram_twtrcon_ready $0\main_sdram_twtrcon_ready[0:0] + update \main_sdram_twtrcon_count $0\main_sdram_twtrcon_count[2:0] + update \main_sdram_time0 $0\main_sdram_time0[4:0] + update \main_sdram_time1 $0\main_sdram_time1[3:0] + update \main_converter_counter $0\main_converter_counter[0:0] + update \main_converter_dat_r $0\main_converter_dat_r[31:0] + update \main_cmd_consumed $0\main_cmd_consumed[0:0] + update \main_wdata_consumed $0\main_wdata_consumed[0:0] + update \main_storage $0\main_storage[31:0] + update \main_re $0\main_re[0:0] + update \main_sink_ready $0\main_sink_ready[0:0] + update \main_uart_clk_txen $0\main_uart_clk_txen[0:0] + update \main_phase_accumulator_tx $0\main_phase_accumulator_tx[31:0] + update \main_tx_reg $0\main_tx_reg[7:0] + update \main_tx_bitcount $0\main_tx_bitcount[3:0] + update \main_tx_busy $0\main_tx_busy[0:0] + update \main_source_valid $0\main_source_valid[0:0] + update \main_source_payload_data $0\main_source_payload_data[7:0] + update \main_uart_clk_rxen $0\main_uart_clk_rxen[0:0] + update \main_phase_accumulator_rx $0\main_phase_accumulator_rx[31:0] + update \main_rx_r $0\main_rx_r[0:0] + update \main_rx_reg $0\main_rx_reg[7:0] + update \main_rx_bitcount $0\main_rx_bitcount[3:0] + update \main_rx_busy $0\main_rx_busy[0:0] + update \main_uart_tx_pending $0\main_uart_tx_pending[0:0] + update \main_uart_tx_old_trigger $0\main_uart_tx_old_trigger[0:0] + update \main_uart_rx_pending $0\main_uart_rx_pending[0:0] + update \main_uart_rx_old_trigger $0\main_uart_rx_old_trigger[0:0] + update \main_uart_eventmanager_storage $0\main_uart_eventmanager_storage[1:0] + update \main_uart_eventmanager_re $0\main_uart_eventmanager_re[0:0] + update \main_uart_tx_fifo_readable $0\main_uart_tx_fifo_readable[0:0] + update \main_uart_tx_fifo_level0 $0\main_uart_tx_fifo_level0[4:0] + update \main_uart_tx_fifo_produce $0\main_uart_tx_fifo_produce[3:0] + update \main_uart_tx_fifo_consume $0\main_uart_tx_fifo_consume[3:0] + update \main_uart_rx_fifo_readable $0\main_uart_rx_fifo_readable[0:0] + update \main_uart_rx_fifo_level0 $0\main_uart_rx_fifo_level0[4:0] + update \main_uart_rx_fifo_produce $0\main_uart_rx_fifo_produce[3:0] + update \main_uart_rx_fifo_consume $0\main_uart_rx_fifo_consume[3:0] + update \main_gpio_oe_storage $0\main_gpio_oe_storage[15:0] + update \main_gpio_oe_re $0\main_gpio_oe_re[0:0] + update \main_gpio_out_storage $0\main_gpio_out_storage[15:0] + update \main_gpio_out_re $0\main_gpio_out_re[0:0] + update \main_spi_master_miso $0\main_spi_master_miso[7:0] + update \main_spi_master_control_storage $0\main_spi_master_control_storage[15:0] + update \main_spi_master_control_re $0\main_spi_master_control_re[0:0] + update \main_spi_master_mosi_storage $0\main_spi_master_mosi_storage[7:0] + update \main_spi_master_mosi_re $0\main_spi_master_mosi_re[0:0] + update \main_spi_master_cs_storage $0\main_spi_master_cs_storage[0:0] + update \main_spi_master_cs_re $0\main_spi_master_cs_re[0:0] + update \main_spi_master_loopback_storage $0\main_spi_master_loopback_storage[0:0] + update \main_spi_master_loopback_re $0\main_spi_master_loopback_re[0:0] + update \main_spi_master_count $0\main_spi_master_count[2:0] + update \main_spi_master_clk_divider1 $0\main_spi_master_clk_divider1[15:0] + update \main_spi_master_mosi_data $0\main_spi_master_mosi_data[7:0] + update \main_spi_master_mosi_sel $0\main_spi_master_mosi_sel[2:0] + update \main_spi_master_miso_data $0\main_spi_master_miso_data[7:0] + update \main_dummy $0\main_dummy[41:0] + update \main_pwm0_counter $0\main_pwm0_counter[31:0] + update \main_pwm0_enable_storage $0\main_pwm0_enable_storage[0:0] + update \main_pwm0_enable_re $0\main_pwm0_enable_re[0:0] + update \main_pwm0_width_storage $0\main_pwm0_width_storage[31:0] + update \main_pwm0_width_re $0\main_pwm0_width_re[0:0] + update \main_pwm0_period_storage $0\main_pwm0_period_storage[31:0] + update \main_pwm0_period_re $0\main_pwm0_period_re[0:0] + update \main_pwm1_counter $0\main_pwm1_counter[31:0] + update \main_pwm1_enable_storage $0\main_pwm1_enable_storage[0:0] + update \main_pwm1_enable_re $0\main_pwm1_enable_re[0:0] + update \main_pwm1_width_storage $0\main_pwm1_width_storage[31:0] + update \main_pwm1_width_re $0\main_pwm1_width_re[0:0] + update \main_pwm1_period_storage $0\main_pwm1_period_storage[31:0] + update \main_pwm1_period_re $0\main_pwm1_period_re[0:0] + update \main_sdphy_clocker_storage $0\main_sdphy_clocker_storage[8:0] + update \main_sdphy_clocker_re $0\main_sdphy_clocker_re[0:0] + update \main_sdphy_clocker_clk0 $0\main_sdphy_clocker_clk0[0:0] + update \main_sdphy_clocker_clks $0\main_sdphy_clocker_clks[8:0] + update \main_sdphy_clocker_clk_d $0\main_sdphy_clocker_clk_d[0:0] + update \main_sdphy_init_count $0\main_sdphy_init_count[7:0] + update \main_sdphy_cmdw_count $0\main_sdphy_cmdw_count[7:0] + update \main_sdphy_cmdr_timeout $0\main_sdphy_cmdr_timeout[31:0] + update \main_sdphy_cmdr_count $0\main_sdphy_cmdr_count[7:0] + update \main_sdphy_cmdr_cmdr_run $0\main_sdphy_cmdr_cmdr_run[0:0] + update \main_sdphy_cmdr_cmdr_converter_source_first $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0] + update \main_sdphy_cmdr_cmdr_converter_source_last $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0] + update \main_sdphy_cmdr_cmdr_converter_source_payload_data $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] + update \main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count $0\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] + update \main_sdphy_cmdr_cmdr_converter_demux $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] + update \main_sdphy_cmdr_cmdr_converter_strobe_all $0\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] + update \main_sdphy_cmdr_cmdr_buf_source_valid $0\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] + update \main_sdphy_cmdr_cmdr_buf_source_first $0\main_sdphy_cmdr_cmdr_buf_source_first[0:0] + update \main_sdphy_cmdr_cmdr_buf_source_last $0\main_sdphy_cmdr_cmdr_buf_source_last[0:0] + update \main_sdphy_cmdr_cmdr_buf_source_payload_data $0\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] + update \main_sdphy_cmdr_cmdr_reset $0\main_sdphy_cmdr_cmdr_reset[0:0] + update \main_sdphy_dataw_count $0\main_sdphy_dataw_count[7:0] + update \main_sdphy_dataw_crcr_run $0\main_sdphy_dataw_crcr_run[0:0] + update \main_sdphy_dataw_crcr_converter_source_first $0\main_sdphy_dataw_crcr_converter_source_first[0:0] + update \main_sdphy_dataw_crcr_converter_source_last $0\main_sdphy_dataw_crcr_converter_source_last[0:0] + update \main_sdphy_dataw_crcr_converter_source_payload_data $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] + update \main_sdphy_dataw_crcr_converter_source_payload_valid_token_count $0\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] + update \main_sdphy_dataw_crcr_converter_demux $0\main_sdphy_dataw_crcr_converter_demux[2:0] + update \main_sdphy_dataw_crcr_converter_strobe_all $0\main_sdphy_dataw_crcr_converter_strobe_all[0:0] + update \main_sdphy_dataw_crcr_buf_source_valid $0\main_sdphy_dataw_crcr_buf_source_valid[0:0] + update \main_sdphy_dataw_crcr_buf_source_first $0\main_sdphy_dataw_crcr_buf_source_first[0:0] + update \main_sdphy_dataw_crcr_buf_source_last $0\main_sdphy_dataw_crcr_buf_source_last[0:0] + update \main_sdphy_dataw_crcr_buf_source_payload_data $0\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] + update \main_sdphy_dataw_crcr_reset $0\main_sdphy_dataw_crcr_reset[0:0] + update \main_sdphy_datar_timeout $0\main_sdphy_datar_timeout[31:0] + update \main_sdphy_datar_count $0\main_sdphy_datar_count[9:0] + update \main_sdphy_datar_datar_run $0\main_sdphy_datar_datar_run[0:0] + update \main_sdphy_datar_datar_converter_source_first $0\main_sdphy_datar_datar_converter_source_first[0:0] + update \main_sdphy_datar_datar_converter_source_last $0\main_sdphy_datar_datar_converter_source_last[0:0] + update \main_sdphy_datar_datar_converter_source_payload_data $0\main_sdphy_datar_datar_converter_source_payload_data[7:0] + update \main_sdphy_datar_datar_converter_source_payload_valid_token_count $0\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] + update \main_sdphy_datar_datar_converter_demux $0\main_sdphy_datar_datar_converter_demux[0:0] + update \main_sdphy_datar_datar_converter_strobe_all $0\main_sdphy_datar_datar_converter_strobe_all[0:0] + update \main_sdphy_datar_datar_buf_source_valid $0\main_sdphy_datar_datar_buf_source_valid[0:0] + update \main_sdphy_datar_datar_buf_source_first $0\main_sdphy_datar_datar_buf_source_first[0:0] + update \main_sdphy_datar_datar_buf_source_last $0\main_sdphy_datar_datar_buf_source_last[0:0] + update \main_sdphy_datar_datar_buf_source_payload_data $0\main_sdphy_datar_datar_buf_source_payload_data[7:0] + update \main_sdphy_datar_datar_reset $0\main_sdphy_datar_datar_reset[0:0] + update \main_sdcore_cmd_argument_storage $0\main_sdcore_cmd_argument_storage[31:0] + update \main_sdcore_cmd_argument_re $0\main_sdcore_cmd_argument_re[0:0] + update \main_sdcore_cmd_command_storage $0\main_sdcore_cmd_command_storage[31:0] + update \main_sdcore_cmd_command_re $0\main_sdcore_cmd_command_re[0:0] + update \main_sdcore_cmd_response_status $0\main_sdcore_cmd_response_status[127:0] + update \main_sdcore_block_length_storage $0\main_sdcore_block_length_storage[9:0] + update \main_sdcore_block_length_re $0\main_sdcore_block_length_re[0:0] + update \main_sdcore_block_count_storage $0\main_sdcore_block_count_storage[31:0] + update \main_sdcore_block_count_re $0\main_sdcore_block_count_re[0:0] + update \main_sdcore_crc7_inserter_crcreg0 $0\main_sdcore_crc7_inserter_crcreg0[6:0] + update \main_sdcore_crc16_inserter_cnt $0\main_sdcore_crc16_inserter_cnt[2:0] + update \main_sdcore_crc16_inserter_crc0_crcreg0 $0\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] + update \main_sdcore_crc16_inserter_crc1_crcreg0 $0\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] + update \main_sdcore_crc16_inserter_crc2_crcreg0 $0\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] + update \main_sdcore_crc16_inserter_crc3_crcreg0 $0\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] + update \main_sdcore_crc16_inserter_crctmp0 $0\main_sdcore_crc16_inserter_crctmp0[15:0] + update \main_sdcore_crc16_inserter_crctmp1 $0\main_sdcore_crc16_inserter_crctmp1[15:0] + update \main_sdcore_crc16_inserter_crctmp2 $0\main_sdcore_crc16_inserter_crctmp2[15:0] + update \main_sdcore_crc16_inserter_crctmp3 $0\main_sdcore_crc16_inserter_crctmp3[15:0] + update \main_sdcore_crc16_checker_val $0\main_sdcore_crc16_checker_val[7:0] + update \main_sdcore_crc16_checker_cnt $0\main_sdcore_crc16_checker_cnt[3:0] + update \main_sdcore_crc16_checker_crc0_crcreg0 $0\main_sdcore_crc16_checker_crc0_crcreg0[15:0] + update \main_sdcore_crc16_checker_crc1_crcreg0 $0\main_sdcore_crc16_checker_crc1_crcreg0[15:0] + update \main_sdcore_crc16_checker_crc2_crcreg0 $0\main_sdcore_crc16_checker_crc2_crcreg0[15:0] + update \main_sdcore_crc16_checker_crc3_crcreg0 $0\main_sdcore_crc16_checker_crc3_crcreg0[15:0] + update \main_sdcore_crc16_checker_crctmp0 $0\main_sdcore_crc16_checker_crctmp0[15:0] + update \main_sdcore_crc16_checker_crctmp1 $0\main_sdcore_crc16_checker_crctmp1[15:0] + update \main_sdcore_crc16_checker_crctmp2 $0\main_sdcore_crc16_checker_crctmp2[15:0] + update \main_sdcore_crc16_checker_crctmp3 $0\main_sdcore_crc16_checker_crctmp3[15:0] + update \main_sdcore_crc16_checker_fifo0 $0\main_sdcore_crc16_checker_fifo0[15:0] + update \main_sdcore_crc16_checker_fifo1 $0\main_sdcore_crc16_checker_fifo1[15:0] + update \main_sdcore_crc16_checker_fifo2 $0\main_sdcore_crc16_checker_fifo2[15:0] + update \main_sdcore_crc16_checker_fifo3 $0\main_sdcore_crc16_checker_fifo3[15:0] + update \main_sdcore_cmd_count $0\main_sdcore_cmd_count[2:0] + update \main_sdcore_cmd_done $0\main_sdcore_cmd_done[0:0] + update \main_sdcore_cmd_error $0\main_sdcore_cmd_error[0:0] + update \main_sdcore_cmd_timeout $0\main_sdcore_cmd_timeout[0:0] + update \main_sdcore_data_count $0\main_sdcore_data_count[31:0] + update \main_sdcore_data_done $0\main_sdcore_data_done[0:0] + update \main_sdcore_data_error $0\main_sdcore_data_error[0:0] + update \main_sdcore_data_timeout $0\main_sdcore_data_timeout[0:0] + update \main_sdblock2mem_fifo_level $0\main_sdblock2mem_fifo_level[5:0] + update \main_sdblock2mem_fifo_produce $0\main_sdblock2mem_fifo_produce[4:0] + update \main_sdblock2mem_fifo_consume $0\main_sdblock2mem_fifo_consume[4:0] + update \main_sdblock2mem_converter_source_first $0\main_sdblock2mem_converter_source_first[0:0] + update \main_sdblock2mem_converter_source_last $0\main_sdblock2mem_converter_source_last[0:0] + update \main_sdblock2mem_converter_source_payload_data $0\main_sdblock2mem_converter_source_payload_data[31:0] + update \main_sdblock2mem_converter_source_payload_valid_token_count $0\main_sdblock2mem_converter_source_payload_valid_token_count[2:0] + update \main_sdblock2mem_converter_demux $0\main_sdblock2mem_converter_demux[1:0] + update \main_sdblock2mem_converter_strobe_all $0\main_sdblock2mem_converter_strobe_all[0:0] + update \main_sdblock2mem_wishbonedmawriter_base_storage $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] + update \main_sdblock2mem_wishbonedmawriter_base_re $0\main_sdblock2mem_wishbonedmawriter_base_re[0:0] + update \main_sdblock2mem_wishbonedmawriter_length_storage $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] + update \main_sdblock2mem_wishbonedmawriter_length_re $0\main_sdblock2mem_wishbonedmawriter_length_re[0:0] + update \main_sdblock2mem_wishbonedmawriter_enable_storage $0\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] + update \main_sdblock2mem_wishbonedmawriter_enable_re $0\main_sdblock2mem_wishbonedmawriter_enable_re[0:0] + update \main_sdblock2mem_wishbonedmawriter_loop_storage $0\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] + update \main_sdblock2mem_wishbonedmawriter_loop_re $0\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] + update \main_sdblock2mem_wishbonedmawriter_offset $0\main_sdblock2mem_wishbonedmawriter_offset[31:0] + update \main_sdmem2block_dma_data $0\main_sdmem2block_dma_data[31:0] + update \main_sdmem2block_dma_base_storage $0\main_sdmem2block_dma_base_storage[63:0] + update \main_sdmem2block_dma_base_re $0\main_sdmem2block_dma_base_re[0:0] + update \main_sdmem2block_dma_length_storage $0\main_sdmem2block_dma_length_storage[31:0] + update \main_sdmem2block_dma_length_re $0\main_sdmem2block_dma_length_re[0:0] + update \main_sdmem2block_dma_enable_storage $0\main_sdmem2block_dma_enable_storage[0:0] + update \main_sdmem2block_dma_enable_re $0\main_sdmem2block_dma_enable_re[0:0] + update \main_sdmem2block_dma_loop_storage $0\main_sdmem2block_dma_loop_storage[0:0] + update \main_sdmem2block_dma_loop_re $0\main_sdmem2block_dma_loop_re[0:0] + update \main_sdmem2block_dma_offset $0\main_sdmem2block_dma_offset[31:0] + update \main_sdmem2block_converter_mux $0\main_sdmem2block_converter_mux[1:0] + update \main_sdmem2block_fifo_level $0\main_sdmem2block_fifo_level[5:0] + update \main_sdmem2block_fifo_produce $0\main_sdmem2block_fifo_produce[4:0] + update \main_sdmem2block_fifo_consume $0\main_sdmem2block_fifo_consume[4:0] + update \libresocsim_miso $0\libresocsim_miso[7:0] + update \libresocsim_control_storage $0\libresocsim_control_storage[15:0] + update \libresocsim_control_re $0\libresocsim_control_re[0:0] + update \libresocsim_mosi_storage $0\libresocsim_mosi_storage[7:0] + update \libresocsim_mosi_re $0\libresocsim_mosi_re[0:0] + update \libresocsim_cs_storage $0\libresocsim_cs_storage[0:0] + update \libresocsim_cs_re $0\libresocsim_cs_re[0:0] + update \libresocsim_loopback_storage $0\libresocsim_loopback_storage[0:0] + update \libresocsim_loopback_re $0\libresocsim_loopback_re[0:0] + update \libresocsim_count $0\libresocsim_count[2:0] + update \libresocsim_clk_divider1 $0\libresocsim_clk_divider1[15:0] + update \libresocsim_mosi_data $0\libresocsim_mosi_data[7:0] + update \libresocsim_mosi_sel $0\libresocsim_mosi_sel[2:0] + update \libresocsim_miso_data $0\libresocsim_miso_data[7:0] + update \libresocsim_storage $0\libresocsim_storage[15:0] + update \libresocsim_re $0\libresocsim_re[0:0] + update \builder_converter0_state $0\builder_converter0_state[0:0] + update \builder_converter1_state $0\builder_converter1_state[0:0] + update \builder_converter2_state $0\builder_converter2_state[0:0] + update \builder_refresher_state $0\builder_refresher_state[1:0] + update \builder_bankmachine0_state $0\builder_bankmachine0_state[2:0] + update \builder_bankmachine1_state $0\builder_bankmachine1_state[2:0] + update \builder_bankmachine2_state $0\builder_bankmachine2_state[2:0] + update \builder_bankmachine3_state $0\builder_bankmachine3_state[2:0] + update \builder_multiplexer_state $0\builder_multiplexer_state[2:0] + update \builder_new_master_wdata_ready $0\builder_new_master_wdata_ready[0:0] + update \builder_new_master_rdata_valid0 $0\builder_new_master_rdata_valid0[0:0] + update \builder_new_master_rdata_valid1 $0\builder_new_master_rdata_valid1[0:0] + update \builder_new_master_rdata_valid2 $0\builder_new_master_rdata_valid2[0:0] + update \builder_new_master_rdata_valid3 $0\builder_new_master_rdata_valid3[0:0] + update \builder_converter_state $0\builder_converter_state[0:0] + update \builder_spimaster0_state $0\builder_spimaster0_state[1:0] + update \builder_sdphy_sdphyinit_state $0\builder_sdphy_sdphyinit_state[0:0] + update \builder_sdphy_sdphycmdw_state $0\builder_sdphy_sdphycmdw_state[1:0] + update \builder_sdphy_sdphycmdr_state $0\builder_sdphy_sdphycmdr_state[2:0] + update \builder_sdphy_sdphycrcr_state $0\builder_sdphy_sdphycrcr_state[0:0] + update \builder_sdphy_fsm_state $0\builder_sdphy_fsm_state[2:0] + update \builder_sdphy_sdphydatar_state $0\builder_sdphy_sdphydatar_state[2:0] + update \builder_sdcore_crcupstreaminserter_state $0\builder_sdcore_crcupstreaminserter_state[0:0] + update \builder_sdcore_fsm_state $0\builder_sdcore_fsm_state[2:0] + update \builder_sdblock2memdma_state $0\builder_sdblock2memdma_state[1:0] + update \builder_sdmem2blockdma_fsm_state $0\builder_sdmem2blockdma_fsm_state[0:0] + update \builder_sdmem2blockdma_resetinserter_state $0\builder_sdmem2blockdma_resetinserter_state[1:0] + update \builder_spimaster1_state $0\builder_spimaster1_state[1:0] + update \builder_libresocsim_adr $0\builder_libresocsim_adr[13:0] + update \builder_libresocsim_we $0\builder_libresocsim_we[0:0] + update \builder_libresocsim_dat_w $0\builder_libresocsim_dat_w[7:0] + update \builder_grant $0\builder_grant[2:0] + update \builder_slave_sel_r $0\builder_slave_sel_r[4:0] + update \builder_count $0\builder_count[19:0] + update \builder_interface0_bank_bus_dat_r $0\builder_interface0_bank_bus_dat_r[7:0] + update \builder_interface1_bank_bus_dat_r $0\builder_interface1_bank_bus_dat_r[7:0] + update \builder_interface2_bank_bus_dat_r $0\builder_interface2_bank_bus_dat_r[7:0] + update \builder_interface3_bank_bus_dat_r $0\builder_interface3_bank_bus_dat_r[7:0] + update \builder_interface4_bank_bus_dat_r $0\builder_interface4_bank_bus_dat_r[7:0] + update \builder_interface5_bank_bus_dat_r $0\builder_interface5_bank_bus_dat_r[7:0] + update \builder_interface6_bank_bus_dat_r $0\builder_interface6_bank_bus_dat_r[7:0] + update \builder_interface7_bank_bus_dat_r $0\builder_interface7_bank_bus_dat_r[7:0] + update \builder_interface8_bank_bus_dat_r $0\builder_interface8_bank_bus_dat_r[7:0] + update \builder_interface9_bank_bus_dat_r $0\builder_interface9_bank_bus_dat_r[7:0] + update \builder_interface10_bank_bus_dat_r $0\builder_interface10_bank_bus_dat_r[7:0] + update \builder_interface11_bank_bus_dat_r $0\builder_interface11_bank_bus_dat_r[7:0] + update \builder_interface12_bank_bus_dat_r $0\builder_interface12_bank_bus_dat_r[7:0] + update \builder_interface13_bank_bus_dat_r $0\builder_interface13_bank_bus_dat_r[7:0] + update \builder_state $0\builder_state[1:0] + update \builder_multiregimpl0_regs0 $0\builder_multiregimpl0_regs0[0:0] + update \builder_multiregimpl0_regs1 $0\builder_multiregimpl0_regs1[0:0] + update \builder_multiregimpl1_regs0 $0\builder_multiregimpl1_regs0[0:0] + update \builder_multiregimpl1_regs1 $0\builder_multiregimpl1_regs1[0:0] + update \builder_multiregimpl2_regs0 $0\builder_multiregimpl2_regs0[0:0] + update \builder_multiregimpl2_regs1 $0\builder_multiregimpl2_regs1[0:0] + update \builder_multiregimpl3_regs0 $0\builder_multiregimpl3_regs0[0:0] + update \builder_multiregimpl3_regs1 $0\builder_multiregimpl3_regs1[0:0] + update \builder_multiregimpl4_regs0 $0\builder_multiregimpl4_regs0[0:0] + update \builder_multiregimpl4_regs1 $0\builder_multiregimpl4_regs1[0:0] + update \builder_multiregimpl5_regs0 $0\builder_multiregimpl5_regs0[0:0] + update \builder_multiregimpl5_regs1 $0\builder_multiregimpl5_regs1[0:0] + update \builder_multiregimpl6_regs0 $0\builder_multiregimpl6_regs0[0:0] + update \builder_multiregimpl6_regs1 $0\builder_multiregimpl6_regs1[0:0] + update \builder_multiregimpl7_regs0 $0\builder_multiregimpl7_regs0[0:0] + update \builder_multiregimpl7_regs1 $0\builder_multiregimpl7_regs1[0:0] + update \builder_multiregimpl8_regs0 $0\builder_multiregimpl8_regs0[0:0] + update \builder_multiregimpl8_regs1 $0\builder_multiregimpl8_regs1[0:0] + update \builder_multiregimpl9_regs0 $0\builder_multiregimpl9_regs0[0:0] + update \builder_multiregimpl9_regs1 $0\builder_multiregimpl9_regs1[0:0] + update \builder_multiregimpl10_regs0 $0\builder_multiregimpl10_regs0[0:0] + update \builder_multiregimpl10_regs1 $0\builder_multiregimpl10_regs1[0:0] + update \builder_multiregimpl11_regs0 $0\builder_multiregimpl11_regs0[0:0] + update \builder_multiregimpl11_regs1 $0\builder_multiregimpl11_regs1[0:0] + update \builder_multiregimpl12_regs0 $0\builder_multiregimpl12_regs0[0:0] + update \builder_multiregimpl12_regs1 $0\builder_multiregimpl12_regs1[0:0] + update \builder_multiregimpl13_regs0 $0\builder_multiregimpl13_regs0[0:0] + update \builder_multiregimpl13_regs1 $0\builder_multiregimpl13_regs1[0:0] + update \builder_multiregimpl14_regs0 $0\builder_multiregimpl14_regs0[0:0] + update \builder_multiregimpl14_regs1 $0\builder_multiregimpl14_regs1[0:0] + update \builder_multiregimpl15_regs0 $0\builder_multiregimpl15_regs0[0:0] + update \builder_multiregimpl15_regs1 $0\builder_multiregimpl15_regs1[0:0] + update \builder_multiregimpl16_regs0 $0\builder_multiregimpl16_regs0[0:0] + update \builder_multiregimpl16_regs1 $0\builder_multiregimpl16_regs1[0:0] + end + attribute \src "ls180.v:736.5-736.48" + process $proc$ls180.v:736$3048 + assign { } { } + assign $1\main_sdram_choose_req_cmd_payload_we[0:0] 1'0 + sync always + sync init + update \main_sdram_choose_req_cmd_payload_we $1\main_sdram_choose_req_cmd_payload_we[0:0] + end + attribute \src "ls180.v:740.11-740.46" + process $proc$ls180.v:740$3049 + assign { } { } + assign $1\main_sdram_choose_req_valids[3:0] 4'0000 + sync always + sync init + update \main_sdram_choose_req_valids $1\main_sdram_choose_req_valids[3:0] + end + attribute \src "ls180.v:742.11-742.45" + process $proc$ls180.v:742$3050 + assign { } { } + assign $1\main_sdram_choose_req_grant[1:0] 2'00 + sync always + sync init + update \main_sdram_choose_req_grant $1\main_sdram_choose_req_grant[1:0] + end + attribute \src "ls180.v:744.12-744.36" + process $proc$ls180.v:744$3051 + assign { } { } + assign $0\main_sdram_nop_a[12:0] 13'0000000000000 + sync always + update \main_sdram_nop_a $0\main_sdram_nop_a[12:0] + sync init + end + attribute \src "ls180.v:745.11-745.35" + process $proc$ls180.v:745$3052 + assign { } { } + assign $0\main_sdram_nop_ba[1:0] 2'00 + sync always + update \main_sdram_nop_ba $0\main_sdram_nop_ba[1:0] + sync init + end + attribute \src "ls180.v:746.11-746.40" + process $proc$ls180.v:746$3053 + assign { } { } + assign $1\main_sdram_steerer_sel[1:0] 2'00 + sync always + sync init + update \main_sdram_steerer_sel $1\main_sdram_steerer_sel[1:0] + end + attribute \src "ls180.v:747.5-747.31" + process $proc$ls180.v:747$3054 + assign { } { } + assign $0\main_sdram_steerer0[0:0] 1'1 + sync always + update \main_sdram_steerer0 $0\main_sdram_steerer0[0:0] + sync init + end + attribute \src "ls180.v:748.5-748.31" + process $proc$ls180.v:748$3055 + assign { } { } + assign $0\main_sdram_steerer1[0:0] 1'1 + sync always + update \main_sdram_steerer1 $0\main_sdram_steerer1[0:0] + sync init + end + attribute \src "ls180.v:750.32-750.63" + process $proc$ls180.v:750$3056 + assign { } { } + assign $0\main_sdram_trrdcon_ready[0:0] 1'1 + sync always + update \main_sdram_trrdcon_ready $0\main_sdram_trrdcon_ready[0:0] + sync init + end + attribute \src "ls180.v:752.32-752.63" + process $proc$ls180.v:752$3057 + assign { } { } + assign $0\main_sdram_tfawcon_ready[0:0] 1'1 + sync always + update \main_sdram_tfawcon_ready $0\main_sdram_tfawcon_ready[0:0] + sync init + end + attribute \src "ls180.v:754.32-754.63" + process $proc$ls180.v:754$3058 + assign { } { } + assign $1\main_sdram_tccdcon_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_tccdcon_ready $1\main_sdram_tccdcon_ready[0:0] + end + attribute \src "ls180.v:755.5-755.36" + process $proc$ls180.v:755$3059 + assign { } { } + assign $1\main_sdram_tccdcon_count[0:0] 1'0 + sync always + sync init + update \main_sdram_tccdcon_count $1\main_sdram_tccdcon_count[0:0] + end + attribute \src "ls180.v:757.32-757.63" + process $proc$ls180.v:757$3060 + assign { } { } + assign $1\main_sdram_twtrcon_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_twtrcon_ready $1\main_sdram_twtrcon_ready[0:0] + end + attribute \src "ls180.v:758.11-758.42" + process $proc$ls180.v:758$3061 + assign { } { } + assign $1\main_sdram_twtrcon_count[2:0] 3'000 + sync always + sync init + update \main_sdram_twtrcon_count $1\main_sdram_twtrcon_count[2:0] + end + attribute \src "ls180.v:761.5-761.26" + process $proc$ls180.v:761$3062 + assign { } { } + assign $1\main_sdram_en0[0:0] 1'0 + sync always + sync init + update \main_sdram_en0 $1\main_sdram_en0[0:0] + end + attribute \src "ls180.v:763.11-763.34" + process $proc$ls180.v:763$3063 + assign { } { } + assign $1\main_sdram_time0[4:0] 5'00000 + sync always + sync init + update \main_sdram_time0 $1\main_sdram_time0[4:0] + end + attribute \src "ls180.v:764.5-764.26" + process $proc$ls180.v:764$3064 + assign { } { } + assign $1\main_sdram_en1[0:0] 1'0 + sync always + sync init + update \main_sdram_en1 $1\main_sdram_en1[0:0] + end + attribute \src "ls180.v:766.11-766.34" + process $proc$ls180.v:766$3065 + assign { } { } + assign $1\main_sdram_time1[3:0] 4'0000 + sync always + sync init + update \main_sdram_time1 $1\main_sdram_time1[3:0] + end + attribute \src "ls180.v:77.5-77.46" + process $proc$ls180.v:77$2773 + assign { } { } + assign $1\main_libresocsim_libresoc_ibus_ack[0:0] 1'0 + sync always + sync init + update \main_libresocsim_libresoc_ibus_ack $1\main_libresocsim_libresoc_ibus_ack[0:0] + end + attribute \src "ls180.v:787.5-787.29" + process $proc$ls180.v:787$3066 + assign { } { } + assign $1\main_wb_sdram_ack[0:0] 1'0 + sync always + sync init + update \main_wb_sdram_ack $1\main_wb_sdram_ack[0:0] + end + attribute \src "ls180.v:791.5-791.29" + process $proc$ls180.v:791$3067 + assign { } { } + assign $0\main_wb_sdram_err[0:0] 1'0 + sync always + update \main_wb_sdram_err $0\main_wb_sdram_err[0:0] + sync init + end + attribute \src "ls180.v:792.12-792.40" + process $proc$ls180.v:792$3068 + assign { } { } + assign $1\main_litedram_wb_adr[29:0] 30'000000000000000000000000000000 + sync always + sync init + update \main_litedram_wb_adr $1\main_litedram_wb_adr[29:0] + end + attribute \src "ls180.v:793.12-793.42" + process $proc$ls180.v:793$3069 + assign { } { } + assign $1\main_litedram_wb_dat_w[15:0] 16'0000000000000000 + sync always + sync init + update \main_litedram_wb_dat_w $1\main_litedram_wb_dat_w[15:0] + end + attribute \src "ls180.v:795.11-795.38" + process $proc$ls180.v:795$3070 + assign { } { } + assign $1\main_litedram_wb_sel[1:0] 2'00 + sync always + sync init + update \main_litedram_wb_sel $1\main_litedram_wb_sel[1:0] + end + attribute \src "ls180.v:796.5-796.32" + process $proc$ls180.v:796$3071 + assign { } { } + assign $1\main_litedram_wb_cyc[0:0] 1'0 + sync always + sync init + update \main_litedram_wb_cyc $1\main_litedram_wb_cyc[0:0] + end + attribute \src "ls180.v:797.5-797.32" + process $proc$ls180.v:797$3072 + assign { } { } + assign $1\main_litedram_wb_stb[0:0] 1'0 + sync always + sync init + update \main_litedram_wb_stb $1\main_litedram_wb_stb[0:0] + end + attribute \src "ls180.v:799.5-799.31" + process $proc$ls180.v:799$3073 + assign { } { } + assign $1\main_litedram_wb_we[0:0] 1'0 + sync always + sync init + update \main_litedram_wb_we $1\main_litedram_wb_we[0:0] + end + attribute \src "ls180.v:800.5-800.31" + process $proc$ls180.v:800$3074 + assign { } { } + assign $1\main_converter_skip[0:0] 1'0 + sync always + sync init + update \main_converter_skip $1\main_converter_skip[0:0] + end + attribute \src "ls180.v:801.5-801.34" + process $proc$ls180.v:801$3075 + assign { } { } + assign $1\main_converter_counter[0:0] 1'0 + sync always + sync init + update \main_converter_counter $1\main_converter_counter[0:0] + end + attribute \src "ls180.v:803.12-803.40" + process $proc$ls180.v:803$3076 + assign { } { } + assign $1\main_converter_dat_r[31:0] 0 + sync always + sync init + update \main_converter_dat_r $1\main_converter_dat_r[31:0] + end + attribute \src "ls180.v:804.5-804.29" + process $proc$ls180.v:804$3077 + assign { } { } + assign $1\main_cmd_consumed[0:0] 1'0 + sync always + sync init + update \main_cmd_consumed $1\main_cmd_consumed[0:0] + end + attribute \src "ls180.v:805.5-805.31" + process $proc$ls180.v:805$3078 + assign { } { } + assign $1\main_wdata_consumed[0:0] 1'0 + sync always + sync init + update \main_wdata_consumed $1\main_wdata_consumed[0:0] + end + attribute \src "ls180.v:809.12-809.38" + process $proc$ls180.v:809$3079 + assign { } { } + assign $1\main_storage[31:0] 9895604 + sync always + sync init + update \main_storage $1\main_storage[31:0] + end + attribute \src "ls180.v:81.5-81.46" + process $proc$ls180.v:81$2774 + assign { } { } + assign $0\main_libresocsim_libresoc_ibus_err[0:0] 1'0 + sync always + update \main_libresocsim_libresoc_ibus_err $0\main_libresocsim_libresoc_ibus_err[0:0] + sync init + end + attribute \src "ls180.v:810.5-810.19" + process $proc$ls180.v:810$3080 + assign { } { } + assign $1\main_re[0:0] 1'0 + sync always + sync init + update \main_re $1\main_re[0:0] + end + attribute \src "ls180.v:812.5-812.27" + process $proc$ls180.v:812$3081 + assign { } { } + assign $1\main_sink_ready[0:0] 1'0 + sync always + sync init + update \main_sink_ready $1\main_sink_ready[0:0] + end + attribute \src "ls180.v:816.5-816.30" + process $proc$ls180.v:816$3082 + assign { } { } + assign $1\main_uart_clk_txen[0:0] 1'0 + sync always + sync init + update \main_uart_clk_txen $1\main_uart_clk_txen[0:0] + end + attribute \src "ls180.v:817.12-817.45" + process $proc$ls180.v:817$3083 + assign { } { } + assign $1\main_phase_accumulator_tx[31:0] 0 + sync always + sync init + update \main_phase_accumulator_tx $1\main_phase_accumulator_tx[31:0] + end + attribute \src "ls180.v:818.11-818.29" + process $proc$ls180.v:818$3084 + assign { } { } + assign $1\main_tx_reg[7:0] 8'00000000 + sync always + sync init + update \main_tx_reg $1\main_tx_reg[7:0] + end + attribute \src "ls180.v:819.11-819.34" + process $proc$ls180.v:819$3085 + assign { } { } + assign $1\main_tx_bitcount[3:0] 4'0000 + sync always + sync init + update \main_tx_bitcount $1\main_tx_bitcount[3:0] + end + attribute \src "ls180.v:820.5-820.24" + process $proc$ls180.v:820$3086 + assign { } { } + assign $1\main_tx_busy[0:0] 1'0 + sync always + sync init + update \main_tx_busy $1\main_tx_busy[0:0] + end + attribute \src "ls180.v:821.5-821.29" + process $proc$ls180.v:821$3087 + assign { } { } + assign $1\main_source_valid[0:0] 1'0 + sync always + sync init + update \main_source_valid $1\main_source_valid[0:0] + end + attribute \src "ls180.v:823.5-823.29" + process $proc$ls180.v:823$3088 + assign { } { } + assign $0\main_source_first[0:0] 1'0 + sync always + update \main_source_first $0\main_source_first[0:0] + sync init + end + attribute \src "ls180.v:824.5-824.28" + process $proc$ls180.v:824$3089 + assign { } { } + assign $0\main_source_last[0:0] 1'0 + sync always + update \main_source_last $0\main_source_last[0:0] + sync init + end + attribute \src "ls180.v:825.11-825.42" + process $proc$ls180.v:825$3090 + assign { } { } + assign $1\main_source_payload_data[7:0] 8'00000000 + sync always + sync init + update \main_source_payload_data $1\main_source_payload_data[7:0] + end + attribute \src "ls180.v:826.5-826.30" + process $proc$ls180.v:826$3091 + assign { } { } + assign $1\main_uart_clk_rxen[0:0] 1'0 + sync always + sync init + update \main_uart_clk_rxen $1\main_uart_clk_rxen[0:0] + end + attribute \src "ls180.v:827.12-827.45" + process $proc$ls180.v:827$3092 + assign { } { } + assign $1\main_phase_accumulator_rx[31:0] 0 + sync always + sync init + update \main_phase_accumulator_rx $1\main_phase_accumulator_rx[31:0] + end + attribute \src "ls180.v:829.5-829.21" + process $proc$ls180.v:829$3093 + assign { } { } + assign $1\main_rx_r[0:0] 1'0 + sync always + sync init + update \main_rx_r $1\main_rx_r[0:0] + end + attribute \src "ls180.v:830.11-830.29" + process $proc$ls180.v:830$3094 + assign { } { } + assign $1\main_rx_reg[7:0] 8'00000000 + sync always + sync init + update \main_rx_reg $1\main_rx_reg[7:0] + end + attribute \src "ls180.v:831.11-831.34" + process $proc$ls180.v:831$3095 + assign { } { } + assign $1\main_rx_bitcount[3:0] 4'0000 + sync always + sync init + update \main_rx_bitcount $1\main_rx_bitcount[3:0] + end + attribute \src "ls180.v:832.5-832.24" + process $proc$ls180.v:832$3096 + assign { } { } + assign $1\main_rx_busy[0:0] 1'0 + sync always + sync init + update \main_rx_busy $1\main_rx_busy[0:0] + end + attribute \src "ls180.v:843.5-843.32" + process $proc$ls180.v:843$3097 + assign { } { } + assign $1\main_uart_tx_pending[0:0] 1'0 + sync always + sync init + update \main_uart_tx_pending $1\main_uart_tx_pending[0:0] + end + attribute \src "ls180.v:845.5-845.30" + process $proc$ls180.v:845$3098 + assign { } { } + assign $1\main_uart_tx_clear[0:0] 1'0 + sync always + sync init + update \main_uart_tx_clear $1\main_uart_tx_clear[0:0] + end + attribute \src "ls180.v:846.5-846.36" + process $proc$ls180.v:846$3099 + assign { } { } + assign $1\main_uart_tx_old_trigger[0:0] 1'0 + sync always + sync init + update \main_uart_tx_old_trigger $1\main_uart_tx_old_trigger[0:0] + end + attribute \src "ls180.v:848.5-848.32" + process $proc$ls180.v:848$3100 + assign { } { } + assign $1\main_uart_rx_pending[0:0] 1'0 + sync always + sync init + update \main_uart_rx_pending $1\main_uart_rx_pending[0:0] + end + attribute \src "ls180.v:850.5-850.30" + process $proc$ls180.v:850$3101 + assign { } { } + assign $1\main_uart_rx_clear[0:0] 1'0 + sync always + sync init + update \main_uart_rx_clear $1\main_uart_rx_clear[0:0] + end + attribute \src "ls180.v:851.5-851.36" + process $proc$ls180.v:851$3102 + assign { } { } + assign $1\main_uart_rx_old_trigger[0:0] 1'0 + sync always + sync init + update \main_uart_rx_old_trigger $1\main_uart_rx_old_trigger[0:0] + end + attribute \src "ls180.v:855.11-855.49" + process $proc$ls180.v:855$3103 + assign { } { } + assign $1\main_uart_eventmanager_status_w[1:0] 2'00 + sync always + sync init + update \main_uart_eventmanager_status_w $1\main_uart_eventmanager_status_w[1:0] + end + attribute \src "ls180.v:859.11-859.50" + process $proc$ls180.v:859$3104 + assign { } { } + assign $1\main_uart_eventmanager_pending_w[1:0] 2'00 + sync always + sync init + update \main_uart_eventmanager_pending_w $1\main_uart_eventmanager_pending_w[1:0] + end + attribute \src "ls180.v:860.11-860.48" + process $proc$ls180.v:860$3105 + assign { } { } + assign $1\main_uart_eventmanager_storage[1:0] 2'00 + sync always + sync init + update \main_uart_eventmanager_storage $1\main_uart_eventmanager_storage[1:0] + end + attribute \src "ls180.v:861.5-861.37" + process $proc$ls180.v:861$3106 + assign { } { } + assign $1\main_uart_eventmanager_re[0:0] 1'0 + sync always + sync init + update \main_uart_eventmanager_re $1\main_uart_eventmanager_re[0:0] + end + attribute \src "ls180.v:878.5-878.40" + process $proc$ls180.v:878$3107 + assign { } { } + assign $0\main_uart_tx_fifo_sink_first[0:0] 1'0 + sync always + update \main_uart_tx_fifo_sink_first $0\main_uart_tx_fifo_sink_first[0:0] + sync init + end + attribute \src "ls180.v:879.5-879.39" + process $proc$ls180.v:879$3108 + assign { } { } + assign $0\main_uart_tx_fifo_sink_last[0:0] 1'0 + sync always + update \main_uart_tx_fifo_sink_last $0\main_uart_tx_fifo_sink_last[0:0] + sync init + end + attribute \src "ls180.v:887.5-887.38" + process $proc$ls180.v:887$3109 + assign { } { } + assign $1\main_uart_tx_fifo_readable[0:0] 1'0 + sync always + sync init + update \main_uart_tx_fifo_readable $1\main_uart_tx_fifo_readable[0:0] + end + attribute \src "ls180.v:894.11-894.42" + process $proc$ls180.v:894$3110 + assign { } { } + assign $1\main_uart_tx_fifo_level0[4:0] 5'00000 + sync always + sync init + update \main_uart_tx_fifo_level0 $1\main_uart_tx_fifo_level0[4:0] + end + attribute \src "ls180.v:895.5-895.37" + process $proc$ls180.v:895$3111 + assign { } { } + assign $0\main_uart_tx_fifo_replace[0:0] 1'0 + sync always + update \main_uart_tx_fifo_replace $0\main_uart_tx_fifo_replace[0:0] + sync init + end + attribute \src "ls180.v:896.11-896.43" + process $proc$ls180.v:896$3112 + assign { } { } + assign $1\main_uart_tx_fifo_produce[3:0] 4'0000 + sync always + sync init + update \main_uart_tx_fifo_produce $1\main_uart_tx_fifo_produce[3:0] + end + attribute \src "ls180.v:897.11-897.43" + process $proc$ls180.v:897$3113 + assign { } { } + assign $1\main_uart_tx_fifo_consume[3:0] 4'0000 + sync always + sync init + update \main_uart_tx_fifo_consume $1\main_uart_tx_fifo_consume[3:0] + end + attribute \src "ls180.v:898.11-898.46" + process $proc$ls180.v:898$3114 + assign { } { } + assign $1\main_uart_tx_fifo_wrport_adr[3:0] 4'0000 + sync always + sync init + update \main_uart_tx_fifo_wrport_adr $1\main_uart_tx_fifo_wrport_adr[3:0] + end + attribute \src "ls180.v:924.5-924.38" + process $proc$ls180.v:924$3115 + assign { } { } + assign $1\main_uart_rx_fifo_readable[0:0] 1'0 + sync always + sync init + update \main_uart_rx_fifo_readable $1\main_uart_rx_fifo_readable[0:0] + end + attribute \src "ls180.v:931.11-931.42" + process $proc$ls180.v:931$3116 + assign { } { } + assign $1\main_uart_rx_fifo_level0[4:0] 5'00000 + sync always + sync init + update \main_uart_rx_fifo_level0 $1\main_uart_rx_fifo_level0[4:0] + end + attribute \src "ls180.v:932.5-932.37" + process $proc$ls180.v:932$3117 + assign { } { } + assign $0\main_uart_rx_fifo_replace[0:0] 1'0 + sync always + update \main_uart_rx_fifo_replace $0\main_uart_rx_fifo_replace[0:0] + sync init + end + attribute \src "ls180.v:933.11-933.43" + process $proc$ls180.v:933$3118 + assign { } { } + assign $1\main_uart_rx_fifo_produce[3:0] 4'0000 + sync always + sync init + update \main_uart_rx_fifo_produce $1\main_uart_rx_fifo_produce[3:0] + end + attribute \src "ls180.v:934.11-934.43" + process $proc$ls180.v:934$3119 + assign { } { } + assign $1\main_uart_rx_fifo_consume[3:0] 4'0000 + sync always + sync init + update \main_uart_rx_fifo_consume $1\main_uart_rx_fifo_consume[3:0] + end + attribute \src "ls180.v:935.11-935.46" + process $proc$ls180.v:935$3120 + assign { } { } + assign $1\main_uart_rx_fifo_wrport_adr[3:0] 4'0000 + sync always + sync init + update \main_uart_rx_fifo_wrport_adr $1\main_uart_rx_fifo_wrport_adr[3:0] + end + attribute \src "ls180.v:950.5-950.27" + process $proc$ls180.v:950$3121 + assign { } { } + assign $0\main_uart_reset[0:0] 1'0 + sync always + update \main_uart_reset $0\main_uart_reset[0:0] + sync init + end + attribute \src "ls180.v:951.12-951.40" + process $proc$ls180.v:951$3122 + assign { } { } + assign $1\main_gpio_oe_storage[15:0] 16'0000000000000000 + sync always + sync init + update \main_gpio_oe_storage $1\main_gpio_oe_storage[15:0] + end + attribute \src "ls180.v:952.5-952.27" + process $proc$ls180.v:952$3123 + assign { } { } + assign $1\main_gpio_oe_re[0:0] 1'0 + sync always + sync init + update \main_gpio_oe_re $1\main_gpio_oe_re[0:0] + end + attribute \src "ls180.v:953.12-953.36" + process $proc$ls180.v:953$3124 + assign { } { } + assign $1\main_gpio_status[15:0] 16'0000000000000000 + sync always + sync init + update \main_gpio_status $1\main_gpio_status[15:0] + end + attribute \src "ls180.v:955.12-955.41" + process $proc$ls180.v:955$3125 + assign { } { } + assign $1\main_gpio_out_storage[15:0] 16'0000000000000000 + sync always + sync init + update \main_gpio_out_storage $1\main_gpio_out_storage[15:0] + end + attribute \src "ls180.v:956.5-956.28" + process $proc$ls180.v:956$3126 + assign { } { } + assign $1\main_gpio_out_re[0:0] 1'0 + sync always + sync init + update \main_gpio_out_re $1\main_gpio_out_re[0:0] + end + attribute \src "ls180.v:962.5-962.33" + process $proc$ls180.v:962$3127 + assign { } { } + assign $1\main_spi_master_done0[0:0] 1'0 + sync always + sync init + update \main_spi_master_done0 $1\main_spi_master_done0[0:0] + end + attribute \src "ls180.v:963.5-963.31" + process $proc$ls180.v:963$3128 + assign { } { } + assign $1\main_spi_master_irq[0:0] 1'0 + sync always + sync init + update \main_spi_master_irq $1\main_spi_master_irq[0:0] + end + attribute \src "ls180.v:965.11-965.38" + process $proc$ls180.v:965$3129 + assign { } { } + assign $1\main_spi_master_miso[7:0] 8'00000000 + sync always + sync init + update \main_spi_master_miso $1\main_spi_master_miso[7:0] + end + attribute \src "ls180.v:968.12-968.48" + process $proc$ls180.v:968$3130 + assign { } { } + assign $0\main_spi_master_clk_divider0[15:0] 16'0000000000000111 + sync always + update \main_spi_master_clk_divider0 $0\main_spi_master_clk_divider0[15:0] + sync init + end + attribute \src "ls180.v:969.5-969.34" + process $proc$ls180.v:969$3131 + assign { } { } + assign $1\main_spi_master_start1[0:0] 1'0 + sync always + sync init + update \main_spi_master_start1 $1\main_spi_master_start1[0:0] + end + attribute \src "ls180.v:971.12-971.51" + process $proc$ls180.v:971$3132 + assign { } { } + assign $1\main_spi_master_control_storage[15:0] 16'0000000000000000 + sync always + sync init + update \main_spi_master_control_storage $1\main_spi_master_control_storage[15:0] + end + attribute \src "ls180.v:972.5-972.38" + process $proc$ls180.v:972$3133 + assign { } { } + assign $1\main_spi_master_control_re[0:0] 1'0 + sync always + sync init + update \main_spi_master_control_re $1\main_spi_master_control_re[0:0] + end + attribute \src "ls180.v:976.11-976.46" + process $proc$ls180.v:976$3134 + assign { } { } + assign $1\main_spi_master_mosi_storage[7:0] 8'00000000 + sync always + sync init + update \main_spi_master_mosi_storage $1\main_spi_master_mosi_storage[7:0] + end + attribute \src "ls180.v:977.5-977.35" + process $proc$ls180.v:977$3135 + assign { } { } + assign $1\main_spi_master_mosi_re[0:0] 1'0 + sync always + sync init + update \main_spi_master_mosi_re $1\main_spi_master_mosi_re[0:0] + end + attribute \src "ls180.v:981.5-981.38" + process $proc$ls180.v:981$3136 + assign { } { } + assign $1\main_spi_master_cs_storage[0:0] 1'1 + sync always + sync init + update \main_spi_master_cs_storage $1\main_spi_master_cs_storage[0:0] + end + attribute \src "ls180.v:982.5-982.33" + process $proc$ls180.v:982$3137 + assign { } { } + assign $1\main_spi_master_cs_re[0:0] 1'0 + sync always + sync init + update \main_spi_master_cs_re $1\main_spi_master_cs_re[0:0] + end + attribute \src "ls180.v:983.5-983.44" + process $proc$ls180.v:983$3138 + assign { } { } + assign $1\main_spi_master_loopback_storage[0:0] 1'0 + sync always + sync init + update \main_spi_master_loopback_storage $1\main_spi_master_loopback_storage[0:0] + end + attribute \src "ls180.v:984.5-984.39" + process $proc$ls180.v:984$3139 + assign { } { } + assign $1\main_spi_master_loopback_re[0:0] 1'0 + sync always + sync init + update \main_spi_master_loopback_re $1\main_spi_master_loopback_re[0:0] + end + attribute \src "ls180.v:985.5-985.38" + process $proc$ls180.v:985$3140 + assign { } { } + assign $1\main_spi_master_clk_enable[0:0] 1'0 + sync always + sync init + update \main_spi_master_clk_enable $1\main_spi_master_clk_enable[0:0] + end + attribute \src "ls180.v:986.5-986.37" + process $proc$ls180.v:986$3141 + assign { } { } + assign $1\main_spi_master_cs_enable[0:0] 1'0 + sync always + sync init + update \main_spi_master_cs_enable $1\main_spi_master_cs_enable[0:0] + end + attribute \src "ls180.v:987.11-987.39" + process $proc$ls180.v:987$3142 + assign { } { } + assign $1\main_spi_master_count[2:0] 3'000 + sync always + sync init + update \main_spi_master_count $1\main_spi_master_count[2:0] + end + attribute \src "ls180.v:988.5-988.38" + process $proc$ls180.v:988$3143 + assign { } { } + assign $1\main_spi_master_mosi_latch[0:0] 1'0 + sync always + sync init + update \main_spi_master_mosi_latch $1\main_spi_master_mosi_latch[0:0] + end + attribute \src "ls180.v:989.5-989.38" + process $proc$ls180.v:989$3144 + assign { } { } + assign $1\main_spi_master_miso_latch[0:0] 1'0 + sync always + sync init + update \main_spi_master_miso_latch $1\main_spi_master_miso_latch[0:0] + end + attribute \src "ls180.v:990.12-990.48" + process $proc$ls180.v:990$3145 + assign { } { } + assign $1\main_spi_master_clk_divider1[15:0] 16'0000000000000000 + sync always + sync init + update \main_spi_master_clk_divider1 $1\main_spi_master_clk_divider1[15:0] + end + attribute \src "ls180.v:993.11-993.43" + process $proc$ls180.v:993$3146 + assign { } { } + assign $1\main_spi_master_mosi_data[7:0] 8'00000000 + sync always + sync init + update \main_spi_master_mosi_data $1\main_spi_master_mosi_data[7:0] + end + attribute \src "ls180.v:994.11-994.42" + process $proc$ls180.v:994$3147 + assign { } { } + assign $1\main_spi_master_mosi_sel[2:0] 3'000 + sync always + sync init + update \main_spi_master_mosi_sel $1\main_spi_master_mosi_sel[2:0] + end + attribute \src "ls180.v:995.11-995.43" + process $proc$ls180.v:995$3148 + assign { } { } + assign $1\main_spi_master_miso_data[7:0] 8'00000000 + sync always + sync init + update \main_spi_master_miso_data $1\main_spi_master_miso_data[7:0] + end + attribute \src "ls180.v:997.12-997.30" + process $proc$ls180.v:997$3149 + assign { } { } + assign $1\main_dummy[41:0] 42'000000000000000000000000000000000000000000 + sync always + sync init + update \main_dummy $1\main_dummy[41:0] + end + attribute \src "ls180.v:9977.1-9987.4" + process $proc$ls180.v:9977$2682 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\mem$ls180.v:9985$4_ADDR[6:0]$2692 7'xxxxxxx + assign $0$memwr$\mem$ls180.v:9985$4_DATA[31:0]$2693 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem$ls180.v:9985$4_EN[31:0]$2694 0 + assign $0$memwr$\mem$ls180.v:9983$3_ADDR[6:0]$2689 7'xxxxxxx + assign $0$memwr$\mem$ls180.v:9983$3_DATA[31:0]$2690 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem$ls180.v:9983$3_EN[31:0]$2691 0 + assign $0$memwr$\mem$ls180.v:9981$2_ADDR[6:0]$2686 7'xxxxxxx + assign $0$memwr$\mem$ls180.v:9981$2_DATA[31:0]$2687 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem$ls180.v:9981$2_EN[31:0]$2688 0 + assign $0$memwr$\mem$ls180.v:9979$1_ADDR[6:0]$2683 7'xxxxxxx + assign $0$memwr$\mem$ls180.v:9979$1_DATA[31:0]$2684 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem$ls180.v:9979$1_EN[31:0]$2685 0 + assign $0\memadr[6:0] \main_libresocsim_adr + attribute \src "ls180.v:9978.2-9979.65" + switch \main_libresocsim_we [0] + attribute \src "ls180.v:9978.6-9978.28" + case 1'1 + assign $0$memwr$\mem$ls180.v:9979$1_ADDR[6:0]$2683 \main_libresocsim_adr + assign $0$memwr$\mem$ls180.v:9979$1_DATA[31:0]$2684 { 24'000000000000000000000000 \main_libresocsim_dat_w [7:0] } + assign $0$memwr$\mem$ls180.v:9979$1_EN[31:0]$2685 255 + case + end + attribute \src "ls180.v:9980.2-9981.67" + switch \main_libresocsim_we [1] + attribute \src "ls180.v:9980.6-9980.28" + case 1'1 + assign $0$memwr$\mem$ls180.v:9981$2_ADDR[6:0]$2686 \main_libresocsim_adr + assign $0$memwr$\mem$ls180.v:9981$2_DATA[31:0]$2687 { 16'0000000000000000 \main_libresocsim_dat_w [15:8] 8'xxxxxxxx } + assign $0$memwr$\mem$ls180.v:9981$2_EN[31:0]$2688 65280 + case + end + attribute \src "ls180.v:9982.2-9983.69" + switch \main_libresocsim_we [2] + attribute \src "ls180.v:9982.6-9982.28" + case 1'1 + assign $0$memwr$\mem$ls180.v:9983$3_ADDR[6:0]$2689 \main_libresocsim_adr + assign $0$memwr$\mem$ls180.v:9983$3_DATA[31:0]$2690 { 8'00000000 \main_libresocsim_dat_w [23:16] 16'xxxxxxxxxxxxxxxx } + assign $0$memwr$\mem$ls180.v:9983$3_EN[31:0]$2691 16711680 + case + end + attribute \src "ls180.v:9984.2-9985.69" + switch \main_libresocsim_we [3] + attribute \src "ls180.v:9984.6-9984.28" + case 1'1 + assign $0$memwr$\mem$ls180.v:9985$4_ADDR[6:0]$2692 \main_libresocsim_adr + assign $0$memwr$\mem$ls180.v:9985$4_DATA[31:0]$2693 { \main_libresocsim_dat_w [31:24] 24'xxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem$ls180.v:9985$4_EN[31:0]$2694 32'11111111000000000000000000000000 + case + end + sync posedge \sys_clk_1 + update \memadr $0\memadr[6:0] + update $memwr$\mem$ls180.v:9979$1_ADDR $0$memwr$\mem$ls180.v:9979$1_ADDR[6:0]$2683 + update $memwr$\mem$ls180.v:9979$1_DATA $0$memwr$\mem$ls180.v:9979$1_DATA[31:0]$2684 + update $memwr$\mem$ls180.v:9979$1_EN $0$memwr$\mem$ls180.v:9979$1_EN[31:0]$2685 + update $memwr$\mem$ls180.v:9981$2_ADDR $0$memwr$\mem$ls180.v:9981$2_ADDR[6:0]$2686 + update $memwr$\mem$ls180.v:9981$2_DATA $0$memwr$\mem$ls180.v:9981$2_DATA[31:0]$2687 + update $memwr$\mem$ls180.v:9981$2_EN $0$memwr$\mem$ls180.v:9981$2_EN[31:0]$2688 + update $memwr$\mem$ls180.v:9983$3_ADDR $0$memwr$\mem$ls180.v:9983$3_ADDR[6:0]$2689 + update $memwr$\mem$ls180.v:9983$3_DATA $0$memwr$\mem$ls180.v:9983$3_DATA[31:0]$2690 + update $memwr$\mem$ls180.v:9983$3_EN $0$memwr$\mem$ls180.v:9983$3_EN[31:0]$2691 + update $memwr$\mem$ls180.v:9985$4_ADDR $0$memwr$\mem$ls180.v:9985$4_ADDR[6:0]$2692 + update $memwr$\mem$ls180.v:9985$4_DATA $0$memwr$\mem$ls180.v:9985$4_DATA[31:0]$2693 + update $memwr$\mem$ls180.v:9985$4_EN $0$memwr$\mem$ls180.v:9985$4_EN[31:0]$2694 + end + attribute \src "ls180.v:9997.1-10001.4" + process $proc$ls180.v:9997$2696 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\storage$ls180.v:9999$5_ADDR[2:0]$2697 3'xxx + assign $0$memwr$\storage$ls180.v:9999$5_DATA[24:0]$2698 25'xxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\storage$ls180.v:9999$5_EN[24:0]$2699 25'0000000000000000000000000 + assign $0\memdat[24:0] $memrd$\storage$ls180.v:10000$2700_DATA + attribute \src "ls180.v:9998.2-9999.129" + switch \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we + attribute \src "ls180.v:9998.6-9998.60" + case 1'1 + assign $0$memwr$\storage$ls180.v:9999$5_ADDR[2:0]$2697 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr + assign $0$memwr$\storage$ls180.v:9999$5_DATA[24:0]$2698 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w + assign $0$memwr$\storage$ls180.v:9999$5_EN[24:0]$2699 25'1111111111111111111111111 + case + end + sync posedge \sys_clk_1 + update \memdat $0\memdat[24:0] + update $memwr$\storage$ls180.v:9999$5_ADDR $0$memwr$\storage$ls180.v:9999$5_ADDR[2:0]$2697 + update $memwr$\storage$ls180.v:9999$5_DATA $0$memwr$\storage$ls180.v:9999$5_DATA[24:0]$2698 + update $memwr$\storage$ls180.v:9999$5_EN $0$memwr$\storage$ls180.v:9999$5_EN[24:0]$2699 + end + connect \main_libresocsim_libresoc_reset \main_libresocsim_reset + connect \uart_tx \main_libresocsim_libresoc_constraintmanager1_uart0_tx + connect \main_libresocsim_libresoc_constraintmanager1_uart0_rx \uart_rx + connect \main_libresocsim_libresoc_constraintmanager1_gpio0_i \gpio_i + connect \gpio_o \main_libresocsim_libresoc_constraintmanager1_gpio0_o + connect \gpio_oe \main_libresocsim_libresoc_constraintmanager1_gpio0_oe + connect \main_libresocsim_libresoc_jtag_tck \jtag_tck + connect \main_libresocsim_libresoc_jtag_tms \jtag_tms + connect \main_libresocsim_libresoc_jtag_tdi \jtag_tdi + connect \jtag_tdo \main_libresocsim_libresoc_jtag_tdo + connect \main_nc \nc + connect \main_sdblock2mem_sink_sink_valid0 \main_sdcore_source_source_valid + connect \main_sdcore_source_source_ready \main_sdblock2mem_sink_sink_ready0 + connect \main_sdblock2mem_sink_sink_first \main_sdcore_source_source_first + connect \main_sdblock2mem_sink_sink_last \main_sdcore_source_source_last + connect \main_sdblock2mem_sink_sink_payload_data0 \main_sdcore_source_source_payload_data + connect \main_sdcore_sink_sink_valid \main_sdmem2block_source_source_valid0 + connect \main_sdmem2block_source_source_ready0 \main_sdcore_sink_sink_ready + connect \main_sdcore_sink_sink_first \main_sdmem2block_source_source_first0 + connect \main_sdcore_sink_sink_last \main_sdmem2block_source_source_last0 + connect \main_sdcore_sink_sink_payload_data \main_sdmem2block_source_source_payload_data0 + connect \main_libresocsim_bus_error \builder_error + connect \main_libresocsim_converter0_reset $not$ls180.v:2726$14_Y + connect \main_libresocsim_libresoc_ibus_dat_r { \main_libresocsim_interface0_converted_interface_dat_r \main_libresocsim_converter0_dat_r [63:32] } + connect \main_libresocsim_converter1_reset $not$ls180.v:2786$25_Y + connect \main_libresocsim_libresoc_dbus_dat_r { \main_libresocsim_interface1_converted_interface_dat_r \main_libresocsim_converter1_dat_r [63:32] } + connect \main_libresocsim_converter2_reset $not$ls180.v:2846$36_Y + connect \main_libresocsim_libresoc_jtag_wb_dat_r { \main_libresocsim_interface2_converted_interface_dat_r \main_libresocsim_converter2_dat_r [63:32] } + connect \main_libresocsim_reset \main_libresocsim_reset_re + connect \main_libresocsim_bus_errors_status \main_libresocsim_bus_errors + connect \main_libresocsim_adr \main_libresocsim_ram_bus_adr [6:0] + connect \main_libresocsim_ram_bus_dat_r \main_libresocsim_dat_r + connect \main_libresocsim_dat_w \main_libresocsim_ram_bus_dat_w + connect \main_libresocsim_zero_trigger $ne$ls180.v:2918$60_Y + connect \main_libresocsim_eventmanager_status_w \main_libresocsim_zero_status + connect \main_libresocsim_eventmanager_pending_w \main_libresocsim_zero_pending + connect \main_libresocsim_irq $and$ls180.v:2927$63_Y + connect \main_libresocsim_zero_status \main_libresocsim_zero_trigger + connect \sys_clk_1 \sys_clk + connect \por_clk \sys_clk + connect \sys_rst_1 \main_int_rst + connect \main_dfi_p0_address \main_sdram_master_p0_address + connect \main_dfi_p0_bank \main_sdram_master_p0_bank + connect \main_dfi_p0_cas_n \main_sdram_master_p0_cas_n + connect \main_dfi_p0_cs_n \main_sdram_master_p0_cs_n + connect \main_dfi_p0_ras_n \main_sdram_master_p0_ras_n + connect \main_dfi_p0_we_n \main_sdram_master_p0_we_n + connect \main_dfi_p0_cke \main_sdram_master_p0_cke + connect \main_dfi_p0_odt \main_sdram_master_p0_odt + connect \main_dfi_p0_reset_n \main_sdram_master_p0_reset_n + connect \main_dfi_p0_act_n \main_sdram_master_p0_act_n + connect \main_dfi_p0_wrdata \main_sdram_master_p0_wrdata + connect \main_dfi_p0_wrdata_en \main_sdram_master_p0_wrdata_en + connect \main_dfi_p0_wrdata_mask \main_sdram_master_p0_wrdata_mask + connect \main_dfi_p0_rddata_en \main_sdram_master_p0_rddata_en + connect \main_sdram_master_p0_rddata \main_dfi_p0_rddata + connect \main_sdram_master_p0_rddata_valid \main_dfi_p0_rddata_valid + connect \main_sdram_slave_p0_address \main_sdram_dfi_p0_address + connect \main_sdram_slave_p0_bank \main_sdram_dfi_p0_bank + connect \main_sdram_slave_p0_cas_n \main_sdram_dfi_p0_cas_n + connect \main_sdram_slave_p0_cs_n \main_sdram_dfi_p0_cs_n + connect \main_sdram_slave_p0_ras_n \main_sdram_dfi_p0_ras_n + connect \main_sdram_slave_p0_we_n \main_sdram_dfi_p0_we_n + connect \main_sdram_slave_p0_cke \main_sdram_dfi_p0_cke + connect \main_sdram_slave_p0_odt \main_sdram_dfi_p0_odt + connect \main_sdram_slave_p0_reset_n \main_sdram_dfi_p0_reset_n + connect \main_sdram_slave_p0_act_n \main_sdram_dfi_p0_act_n + connect \main_sdram_slave_p0_wrdata \main_sdram_dfi_p0_wrdata + connect \main_sdram_slave_p0_wrdata_en \main_sdram_dfi_p0_wrdata_en + connect \main_sdram_slave_p0_wrdata_mask \main_sdram_dfi_p0_wrdata_mask + connect \main_sdram_slave_p0_rddata_en \main_sdram_dfi_p0_rddata_en + connect \main_sdram_dfi_p0_rddata \main_sdram_slave_p0_rddata + connect \main_sdram_dfi_p0_rddata_valid \main_sdram_slave_p0_rddata_valid + connect \main_sdram_inti_p0_cke \main_sdram_cke + connect \main_sdram_inti_p0_odt \main_sdram_odt + connect \main_sdram_inti_p0_reset_n \main_sdram_reset_n + connect \main_sdram_inti_p0_address \main_sdram_address_storage + connect \main_sdram_inti_p0_bank \main_sdram_baddress_storage + connect \main_sdram_inti_p0_wrdata_en $and$ls180.v:3041$70_Y + connect \main_sdram_inti_p0_rddata_en $and$ls180.v:3042$71_Y + connect \main_sdram_inti_p0_wrdata \main_sdram_wrdata_storage + connect \main_sdram_inti_p0_wrdata_mask 2'00 + connect \main_sdram_bankmachine0_req_valid \main_sdram_interface_bank0_valid + connect \main_sdram_interface_bank0_ready \main_sdram_bankmachine0_req_ready + connect \main_sdram_bankmachine0_req_we \main_sdram_interface_bank0_we + connect \main_sdram_bankmachine0_req_addr \main_sdram_interface_bank0_addr + connect \main_sdram_interface_bank0_lock \main_sdram_bankmachine0_req_lock + connect \main_sdram_interface_bank0_wdata_ready \main_sdram_bankmachine0_req_wdata_ready + connect \main_sdram_interface_bank0_rdata_valid \main_sdram_bankmachine0_req_rdata_valid + connect \main_sdram_bankmachine1_req_valid \main_sdram_interface_bank1_valid + connect \main_sdram_interface_bank1_ready \main_sdram_bankmachine1_req_ready + connect \main_sdram_bankmachine1_req_we \main_sdram_interface_bank1_we + connect \main_sdram_bankmachine1_req_addr \main_sdram_interface_bank1_addr + connect \main_sdram_interface_bank1_lock \main_sdram_bankmachine1_req_lock + connect \main_sdram_interface_bank1_wdata_ready \main_sdram_bankmachine1_req_wdata_ready + connect \main_sdram_interface_bank1_rdata_valid \main_sdram_bankmachine1_req_rdata_valid + connect \main_sdram_bankmachine2_req_valid \main_sdram_interface_bank2_valid + connect \main_sdram_interface_bank2_ready \main_sdram_bankmachine2_req_ready + connect \main_sdram_bankmachine2_req_we \main_sdram_interface_bank2_we + connect \main_sdram_bankmachine2_req_addr \main_sdram_interface_bank2_addr + connect \main_sdram_interface_bank2_lock \main_sdram_bankmachine2_req_lock + connect \main_sdram_interface_bank2_wdata_ready \main_sdram_bankmachine2_req_wdata_ready + connect \main_sdram_interface_bank2_rdata_valid \main_sdram_bankmachine2_req_rdata_valid + connect \main_sdram_bankmachine3_req_valid \main_sdram_interface_bank3_valid + connect \main_sdram_interface_bank3_ready \main_sdram_bankmachine3_req_ready + connect \main_sdram_bankmachine3_req_we \main_sdram_interface_bank3_we + connect \main_sdram_bankmachine3_req_addr \main_sdram_interface_bank3_addr + connect \main_sdram_interface_bank3_lock \main_sdram_bankmachine3_req_lock + connect \main_sdram_interface_bank3_wdata_ready \main_sdram_bankmachine3_req_wdata_ready + connect \main_sdram_interface_bank3_rdata_valid \main_sdram_bankmachine3_req_rdata_valid + connect \main_sdram_timer_wait $not$ls180.v:3073$72_Y + connect \main_sdram_postponer_req_i \main_sdram_timer_done0 + connect \main_sdram_wants_refresh \main_sdram_postponer_req_o + connect \main_sdram_timer_done1 $eq$ls180.v:3076$73_Y + connect \main_sdram_timer_done0 \main_sdram_timer_done1 + connect \main_sdram_timer_count0 \main_sdram_timer_count1 + connect \main_sdram_sequencer_start1 $or$ls180.v:3079$75_Y + connect \main_sdram_sequencer_done0 $and$ls180.v:3080$77_Y + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_valid \main_sdram_bankmachine0_req_valid + connect \main_sdram_bankmachine0_req_ready \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_ready + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we \main_sdram_bankmachine0_req_we + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr \main_sdram_bankmachine0_req_addr + connect \main_sdram_bankmachine0_cmd_buffer_sink_valid \main_sdram_bankmachine0_cmd_buffer_lookahead_source_valid + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_source_ready \main_sdram_bankmachine0_cmd_buffer_sink_ready + connect \main_sdram_bankmachine0_cmd_buffer_sink_first \main_sdram_bankmachine0_cmd_buffer_lookahead_source_first + connect \main_sdram_bankmachine0_cmd_buffer_sink_last \main_sdram_bankmachine0_cmd_buffer_lookahead_source_last + connect \main_sdram_bankmachine0_cmd_buffer_sink_payload_we \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we + connect \main_sdram_bankmachine0_cmd_buffer_sink_payload_addr \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr + connect \main_sdram_bankmachine0_cmd_buffer_source_ready $or$ls180.v:3122$79_Y + connect \main_sdram_bankmachine0_req_lock $or$ls180.v:3123$80_Y + connect \main_sdram_bankmachine0_row_hit $eq$ls180.v:3124$81_Y + connect \main_sdram_bankmachine0_cmd_payload_ba 2'00 + connect \main_sdram_bankmachine0_twtpcon_valid $and$ls180.v:3134$86_Y + connect \main_sdram_bankmachine0_trccon_valid $and$ls180.v:3135$88_Y + connect \main_sdram_bankmachine0_trascon_valid $and$ls180.v:3136$90_Y + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din { \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we } + connect { \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we } \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_ready \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_valid + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_source_valid \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_source_first \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_source_last \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re \main_sdram_bankmachine0_cmd_buffer_lookahead_source_ready + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we $and$ls180.v:3168$98_Y + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read $and$ls180.v:3169$99_Y + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr \main_sdram_bankmachine0_cmd_buffer_lookahead_consume + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable $ne$ls180.v:3172$100_Y + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable $ne$ls180.v:3173$101_Y + connect \main_sdram_bankmachine0_cmd_buffer_sink_ready $or$ls180.v:3174$103_Y + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_valid \main_sdram_bankmachine1_req_valid + connect \main_sdram_bankmachine1_req_ready \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_ready + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we \main_sdram_bankmachine1_req_we + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr \main_sdram_bankmachine1_req_addr + connect \main_sdram_bankmachine1_cmd_buffer_sink_valid \main_sdram_bankmachine1_cmd_buffer_lookahead_source_valid + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_source_ready \main_sdram_bankmachine1_cmd_buffer_sink_ready + connect \main_sdram_bankmachine1_cmd_buffer_sink_first \main_sdram_bankmachine1_cmd_buffer_lookahead_source_first + connect \main_sdram_bankmachine1_cmd_buffer_sink_last \main_sdram_bankmachine1_cmd_buffer_lookahead_source_last + connect \main_sdram_bankmachine1_cmd_buffer_sink_payload_we \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we + connect \main_sdram_bankmachine1_cmd_buffer_sink_payload_addr \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr + connect \main_sdram_bankmachine1_cmd_buffer_source_ready $or$ls180.v:3279$109_Y + connect \main_sdram_bankmachine1_req_lock $or$ls180.v:3280$110_Y + connect \main_sdram_bankmachine1_row_hit $eq$ls180.v:3281$111_Y + connect \main_sdram_bankmachine1_cmd_payload_ba 2'01 + connect \main_sdram_bankmachine1_twtpcon_valid $and$ls180.v:3291$116_Y + connect \main_sdram_bankmachine1_trccon_valid $and$ls180.v:3292$118_Y + connect \main_sdram_bankmachine1_trascon_valid $and$ls180.v:3293$120_Y + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din { \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we } + connect { \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we } \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_ready \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_valid + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_source_valid \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_source_first \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_source_last \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re \main_sdram_bankmachine1_cmd_buffer_lookahead_source_ready + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we $and$ls180.v:3325$128_Y + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read $and$ls180.v:3326$129_Y + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr \main_sdram_bankmachine1_cmd_buffer_lookahead_consume + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable $ne$ls180.v:3329$130_Y + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable $ne$ls180.v:3330$131_Y + connect \main_sdram_bankmachine1_cmd_buffer_sink_ready $or$ls180.v:3331$133_Y + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_valid \main_sdram_bankmachine2_req_valid + connect \main_sdram_bankmachine2_req_ready \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_ready + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we \main_sdram_bankmachine2_req_we + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr \main_sdram_bankmachine2_req_addr + connect \main_sdram_bankmachine2_cmd_buffer_sink_valid \main_sdram_bankmachine2_cmd_buffer_lookahead_source_valid + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_source_ready \main_sdram_bankmachine2_cmd_buffer_sink_ready + connect \main_sdram_bankmachine2_cmd_buffer_sink_first \main_sdram_bankmachine2_cmd_buffer_lookahead_source_first + connect \main_sdram_bankmachine2_cmd_buffer_sink_last \main_sdram_bankmachine2_cmd_buffer_lookahead_source_last + connect \main_sdram_bankmachine2_cmd_buffer_sink_payload_we \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we + connect \main_sdram_bankmachine2_cmd_buffer_sink_payload_addr \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr + connect \main_sdram_bankmachine2_cmd_buffer_source_ready $or$ls180.v:3436$139_Y + connect \main_sdram_bankmachine2_req_lock $or$ls180.v:3437$140_Y + connect \main_sdram_bankmachine2_row_hit $eq$ls180.v:3438$141_Y + connect \main_sdram_bankmachine2_cmd_payload_ba 2'10 + connect \main_sdram_bankmachine2_twtpcon_valid $and$ls180.v:3448$146_Y + connect \main_sdram_bankmachine2_trccon_valid $and$ls180.v:3449$148_Y + connect \main_sdram_bankmachine2_trascon_valid $and$ls180.v:3450$150_Y + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din { \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we } + connect { \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we } \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_ready \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_valid + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_source_valid \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_source_first \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_source_last \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re \main_sdram_bankmachine2_cmd_buffer_lookahead_source_ready + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_we $and$ls180.v:3482$158_Y + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read $and$ls180.v:3483$159_Y + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr \main_sdram_bankmachine2_cmd_buffer_lookahead_consume + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable $ne$ls180.v:3486$160_Y + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable $ne$ls180.v:3487$161_Y + connect \main_sdram_bankmachine2_cmd_buffer_sink_ready $or$ls180.v:3488$163_Y + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_valid \main_sdram_bankmachine3_req_valid + connect \main_sdram_bankmachine3_req_ready \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_ready + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we \main_sdram_bankmachine3_req_we + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr \main_sdram_bankmachine3_req_addr + connect \main_sdram_bankmachine3_cmd_buffer_sink_valid \main_sdram_bankmachine3_cmd_buffer_lookahead_source_valid + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_source_ready \main_sdram_bankmachine3_cmd_buffer_sink_ready + connect \main_sdram_bankmachine3_cmd_buffer_sink_first \main_sdram_bankmachine3_cmd_buffer_lookahead_source_first + connect \main_sdram_bankmachine3_cmd_buffer_sink_last \main_sdram_bankmachine3_cmd_buffer_lookahead_source_last + connect \main_sdram_bankmachine3_cmd_buffer_sink_payload_we \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we + connect \main_sdram_bankmachine3_cmd_buffer_sink_payload_addr \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr + connect \main_sdram_bankmachine3_cmd_buffer_source_ready $or$ls180.v:3593$169_Y + connect \main_sdram_bankmachine3_req_lock $or$ls180.v:3594$170_Y + connect \main_sdram_bankmachine3_row_hit $eq$ls180.v:3595$171_Y + connect \main_sdram_bankmachine3_cmd_payload_ba 2'11 + connect \main_sdram_bankmachine3_twtpcon_valid $and$ls180.v:3605$176_Y + connect \main_sdram_bankmachine3_trccon_valid $and$ls180.v:3606$178_Y + connect \main_sdram_bankmachine3_trascon_valid $and$ls180.v:3607$180_Y + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din { \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we } + connect { \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we } \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_ready \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_valid + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_source_valid \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_source_first \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_source_last \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re \main_sdram_bankmachine3_cmd_buffer_lookahead_source_ready + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_we $and$ls180.v:3639$188_Y + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read $and$ls180.v:3640$189_Y + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr \main_sdram_bankmachine3_cmd_buffer_lookahead_consume + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable $ne$ls180.v:3643$190_Y + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable $ne$ls180.v:3644$191_Y + connect \main_sdram_bankmachine3_cmd_buffer_sink_ready $or$ls180.v:3645$193_Y + connect \main_sdram_choose_req_want_cmds 1'1 + connect \main_sdram_trrdcon_valid $and$ls180.v:3741$204_Y + connect \main_sdram_tfawcon_valid $and$ls180.v:3742$210_Y + connect \main_sdram_ras_allowed $and$ls180.v:3743$211_Y + connect \main_sdram_tccdcon_valid $and$ls180.v:3744$214_Y + connect \main_sdram_cas_allowed \main_sdram_tccdcon_ready + connect \main_sdram_twtrcon_valid $and$ls180.v:3746$216_Y + connect \main_sdram_read_available $or$ls180.v:3747$223_Y + connect \main_sdram_write_available $or$ls180.v:3748$230_Y + connect \main_sdram_max_time0 $eq$ls180.v:3749$231_Y + connect \main_sdram_max_time1 $eq$ls180.v:3750$232_Y + connect \main_sdram_bankmachine0_refresh_req \main_sdram_cmd_valid + connect \main_sdram_bankmachine1_refresh_req \main_sdram_cmd_valid + connect \main_sdram_bankmachine2_refresh_req \main_sdram_cmd_valid + connect \main_sdram_bankmachine3_refresh_req \main_sdram_cmd_valid + connect \main_sdram_go_to_refresh $and$ls180.v:3755$235_Y + connect \main_sdram_interface_rdata \main_sdram_dfi_p0_rddata + connect \main_sdram_dfi_p0_wrdata \main_sdram_interface_wdata + connect \main_sdram_dfi_p0_wrdata_mask $not$ls180.v:3758$236_Y + connect \main_sdram_choose_cmd_request \main_sdram_choose_cmd_valids + connect \main_sdram_choose_cmd_cmd_valid \builder_comb_rhs_array_muxed0 + connect \main_sdram_choose_cmd_cmd_payload_a \builder_comb_rhs_array_muxed1 + connect \main_sdram_choose_cmd_cmd_payload_ba \builder_comb_rhs_array_muxed2 + connect \main_sdram_choose_cmd_cmd_payload_is_read \builder_comb_rhs_array_muxed3 + connect \main_sdram_choose_cmd_cmd_payload_is_write \builder_comb_rhs_array_muxed4 + connect \main_sdram_choose_cmd_cmd_payload_is_cmd \builder_comb_rhs_array_muxed5 + connect \main_sdram_choose_cmd_ce $or$ls180.v:3791$294_Y + connect \main_sdram_choose_req_request \main_sdram_choose_req_valids + connect \main_sdram_choose_req_cmd_valid \builder_comb_rhs_array_muxed6 + connect \main_sdram_choose_req_cmd_payload_a \builder_comb_rhs_array_muxed7 + connect \main_sdram_choose_req_cmd_payload_ba \builder_comb_rhs_array_muxed8 + connect \main_sdram_choose_req_cmd_payload_is_read \builder_comb_rhs_array_muxed9 + connect \main_sdram_choose_req_cmd_payload_is_write \builder_comb_rhs_array_muxed10 + connect \main_sdram_choose_req_cmd_payload_is_cmd \builder_comb_rhs_array_muxed11 + connect \main_sdram_choose_req_ce $or$ls180.v:3860$380_Y + connect \main_sdram_dfi_p0_reset_n 1'1 + connect \main_sdram_dfi_p0_cke \main_sdram_steerer0 + connect \main_sdram_dfi_p0_odt \main_sdram_steerer1 + connect \builder_roundrobin0_request $and$ls180.v:3937$412_Y + connect \builder_roundrobin0_ce $and$ls180.v:3938$415_Y + connect \main_sdram_interface_bank0_addr \builder_comb_rhs_array_muxed12 + connect \main_sdram_interface_bank0_we \builder_comb_rhs_array_muxed13 + connect \main_sdram_interface_bank0_valid \builder_comb_rhs_array_muxed14 + connect \builder_roundrobin1_request $and$ls180.v:3942$428_Y + connect \builder_roundrobin1_ce $and$ls180.v:3943$431_Y + connect \main_sdram_interface_bank1_addr \builder_comb_rhs_array_muxed15 + connect \main_sdram_interface_bank1_we \builder_comb_rhs_array_muxed16 + connect \main_sdram_interface_bank1_valid \builder_comb_rhs_array_muxed17 + connect \builder_roundrobin2_request $and$ls180.v:3947$444_Y + connect \builder_roundrobin2_ce $and$ls180.v:3948$447_Y + connect \main_sdram_interface_bank2_addr \builder_comb_rhs_array_muxed18 + connect \main_sdram_interface_bank2_we \builder_comb_rhs_array_muxed19 + connect \main_sdram_interface_bank2_valid \builder_comb_rhs_array_muxed20 + connect \builder_roundrobin3_request $and$ls180.v:3952$460_Y + connect \builder_roundrobin3_ce $and$ls180.v:3953$463_Y + connect \main_sdram_interface_bank3_addr \builder_comb_rhs_array_muxed21 + connect \main_sdram_interface_bank3_we \builder_comb_rhs_array_muxed22 + connect \main_sdram_interface_bank3_valid \builder_comb_rhs_array_muxed23 + connect \main_port_cmd_ready $or$ls180.v:3957$527_Y + connect \main_port_wdata_ready \builder_new_master_wdata_ready + connect \main_port_rdata_valid \builder_new_master_rdata_valid3 + connect \main_port_rdata_payload_data \main_sdram_interface_rdata + connect \builder_roundrobin0_grant 1'0 + connect \builder_roundrobin1_grant 1'0 + connect \builder_roundrobin2_grant 1'0 + connect \builder_roundrobin3_grant 1'0 + connect \main_converter_reset $not$ls180.v:3979$529_Y + connect \main_wb_sdram_dat_r { \main_litedram_wb_dat_r \main_converter_dat_r [31:16] } + connect \main_port_cmd_payload_addr $sub$ls180.v:4039$540_Y [23:0] + connect \main_port_cmd_payload_we \main_litedram_wb_we + connect \main_port_wdata_payload_data \main_litedram_wb_dat_w + connect \main_port_wdata_payload_we \main_litedram_wb_sel + connect \main_litedram_wb_dat_r \main_port_rdata_payload_data + connect \main_port_flush $not$ls180.v:4044$541_Y + connect \main_port_cmd_last $not$ls180.v:4045$542_Y + connect \main_port_cmd_valid $and$ls180.v:4046$545_Y + connect \main_port_wdata_valid $and$ls180.v:4047$549_Y + connect \main_port_rdata_ready $and$ls180.v:4048$552_Y + connect \main_litedram_wb_ack $and$ls180.v:4049$557_Y + connect \main_ack_cmd $or$ls180.v:4050$559_Y + connect \main_ack_wdata $or$ls180.v:4051$561_Y + connect \main_ack_rdata $and$ls180.v:4052$562_Y + connect \main_uart_uart_sink_valid \main_source_valid + connect \main_source_ready \main_uart_uart_sink_ready + connect \main_uart_uart_sink_first \main_source_first + connect \main_uart_uart_sink_last \main_source_last + connect \main_uart_uart_sink_payload_data \main_source_payload_data + connect \main_sink_valid \main_uart_uart_source_valid + connect \main_uart_uart_source_ready \main_sink_ready + connect \main_sink_first \main_uart_uart_source_first + connect \main_sink_last \main_uart_uart_source_last + connect \main_sink_payload_data \main_uart_uart_source_payload_data + connect \main_uart_tx_fifo_sink_valid \main_uart_rxtx_re + connect \main_uart_tx_fifo_sink_payload_data \main_uart_rxtx_r + connect \main_uart_txfull_status $not$ls180.v:4065$563_Y + connect \main_uart_txempty_status $not$ls180.v:4066$564_Y + connect \main_uart_uart_source_valid \main_uart_tx_fifo_source_valid + connect \main_uart_tx_fifo_source_ready \main_uart_uart_source_ready + connect \main_uart_uart_source_first \main_uart_tx_fifo_source_first + connect \main_uart_uart_source_last \main_uart_tx_fifo_source_last + connect \main_uart_uart_source_payload_data \main_uart_tx_fifo_source_payload_data + connect \main_uart_tx_trigger $not$ls180.v:4072$565_Y + connect \main_uart_rx_fifo_sink_valid \main_uart_uart_sink_valid + connect \main_uart_uart_sink_ready \main_uart_rx_fifo_sink_ready + connect \main_uart_rx_fifo_sink_first \main_uart_uart_sink_first + connect \main_uart_rx_fifo_sink_last \main_uart_uart_sink_last + connect \main_uart_rx_fifo_sink_payload_data \main_uart_uart_sink_payload_data + connect \main_uart_rxempty_status $not$ls180.v:4078$566_Y + connect \main_uart_rxfull_status $not$ls180.v:4079$567_Y + connect \main_uart_rxtx_w \main_uart_rx_fifo_source_payload_data + connect \main_uart_rx_fifo_source_ready $or$ls180.v:4081$569_Y + connect \main_uart_rx_trigger $not$ls180.v:4082$570_Y + connect \main_uart_irq $or$ls180.v:4105$579_Y + connect \main_uart_tx_status \main_uart_tx_trigger + connect \main_uart_rx_status \main_uart_rx_trigger + connect \main_uart_tx_fifo_syncfifo_din { \main_uart_tx_fifo_fifo_in_last \main_uart_tx_fifo_fifo_in_first \main_uart_tx_fifo_fifo_in_payload_data } + connect { \main_uart_tx_fifo_fifo_out_last \main_uart_tx_fifo_fifo_out_first \main_uart_tx_fifo_fifo_out_payload_data } \main_uart_tx_fifo_syncfifo_dout + connect \main_uart_tx_fifo_sink_ready \main_uart_tx_fifo_syncfifo_writable + connect \main_uart_tx_fifo_syncfifo_we \main_uart_tx_fifo_sink_valid + connect \main_uart_tx_fifo_fifo_in_first \main_uart_tx_fifo_sink_first + connect \main_uart_tx_fifo_fifo_in_last \main_uart_tx_fifo_sink_last + connect \main_uart_tx_fifo_fifo_in_payload_data \main_uart_tx_fifo_sink_payload_data + connect \main_uart_tx_fifo_source_valid \main_uart_tx_fifo_readable + connect \main_uart_tx_fifo_source_first \main_uart_tx_fifo_fifo_out_first + connect \main_uart_tx_fifo_source_last \main_uart_tx_fifo_fifo_out_last + connect \main_uart_tx_fifo_source_payload_data \main_uart_tx_fifo_fifo_out_payload_data + connect \main_uart_tx_fifo_re \main_uart_tx_fifo_source_ready + connect \main_uart_tx_fifo_syncfifo_re $and$ls180.v:4120$582_Y + connect \main_uart_tx_fifo_level1 $add$ls180.v:4121$583_Y + connect \main_uart_tx_fifo_wrport_dat_w \main_uart_tx_fifo_syncfifo_din + connect \main_uart_tx_fifo_wrport_we $and$ls180.v:4131$587_Y + connect \main_uart_tx_fifo_do_read $and$ls180.v:4132$588_Y + connect \main_uart_tx_fifo_rdport_adr \main_uart_tx_fifo_consume + connect \main_uart_tx_fifo_syncfifo_dout \main_uart_tx_fifo_rdport_dat_r + connect \main_uart_tx_fifo_rdport_re \main_uart_tx_fifo_do_read + connect \main_uart_tx_fifo_syncfifo_writable $ne$ls180.v:4136$589_Y + connect \main_uart_tx_fifo_syncfifo_readable $ne$ls180.v:4137$590_Y + connect \main_uart_rx_fifo_syncfifo_din { \main_uart_rx_fifo_fifo_in_last \main_uart_rx_fifo_fifo_in_first \main_uart_rx_fifo_fifo_in_payload_data } + connect { \main_uart_rx_fifo_fifo_out_last \main_uart_rx_fifo_fifo_out_first \main_uart_rx_fifo_fifo_out_payload_data } \main_uart_rx_fifo_syncfifo_dout + connect \main_uart_rx_fifo_sink_ready \main_uart_rx_fifo_syncfifo_writable + connect \main_uart_rx_fifo_syncfifo_we \main_uart_rx_fifo_sink_valid + connect \main_uart_rx_fifo_fifo_in_first \main_uart_rx_fifo_sink_first + connect \main_uart_rx_fifo_fifo_in_last \main_uart_rx_fifo_sink_last + connect \main_uart_rx_fifo_fifo_in_payload_data \main_uart_rx_fifo_sink_payload_data + connect \main_uart_rx_fifo_source_valid \main_uart_rx_fifo_readable + connect \main_uart_rx_fifo_source_first \main_uart_rx_fifo_fifo_out_first + connect \main_uart_rx_fifo_source_last \main_uart_rx_fifo_fifo_out_last + connect \main_uart_rx_fifo_source_payload_data \main_uart_rx_fifo_fifo_out_payload_data + connect \main_uart_rx_fifo_re \main_uart_rx_fifo_source_ready + connect \main_uart_rx_fifo_syncfifo_re $and$ls180.v:4150$593_Y + connect \main_uart_rx_fifo_level1 $add$ls180.v:4151$594_Y + connect \main_uart_rx_fifo_wrport_dat_w \main_uart_rx_fifo_syncfifo_din + connect \main_uart_rx_fifo_wrport_we $and$ls180.v:4161$598_Y + connect \main_uart_rx_fifo_do_read $and$ls180.v:4162$599_Y + connect \main_uart_rx_fifo_rdport_adr \main_uart_rx_fifo_consume + connect \main_uart_rx_fifo_syncfifo_dout \main_uart_rx_fifo_rdport_dat_r + connect \main_uart_rx_fifo_rdport_re \main_uart_rx_fifo_do_read + connect \main_uart_rx_fifo_syncfifo_writable $ne$ls180.v:4166$600_Y + connect \main_uart_rx_fifo_syncfifo_readable $ne$ls180.v:4167$601_Y + connect \main_gpio_pads_i \main_libresocsim_libresoc_constraintmanager0_gpio0_i + connect \main_libresocsim_libresoc_constraintmanager0_gpio0_o \main_gpio_pads_o + connect \main_libresocsim_libresoc_constraintmanager0_gpio0_oe \main_gpio_pads_oe + connect \main_gpio_pads_oe \main_gpio_oe_storage + connect \main_gpio_pads_o \main_gpio_out_storage + connect \main_spi_master_start0 \main_spi_master_start1 + connect \main_spi_master_length0 \main_spi_master_length1 + connect \main_spi_master_mosi \main_spi_master_mosi_storage + connect \main_spi_master_done1 \main_spi_master_done0 + connect \main_spi_master_miso_status \main_spi_master_miso + connect \main_spi_master_cs \main_spi_master_cs_storage + connect \main_spi_master_loopback \main_spi_master_loopback_storage + connect \main_spi_master_clk_rise $eq$ls180.v:4180$603_Y + connect \main_spi_master_clk_fall $eq$ls180.v:4181$605_Y + connect \main_sdphy_status 1'0 + connect \main_sdphy_sdpads_clk $or$ls180.v:4232$613_Y + connect \main_sdphy_sdpads_cmd_oe $or$ls180.v:4233$617_Y + connect \main_sdphy_sdpads_cmd_o $or$ls180.v:4234$621_Y + connect \main_sdphy_sdpads_data_oe $or$ls180.v:4235$625_Y + connect \main_sdphy_sdpads_data_o $or$ls180.v:4236$629_Y + connect \main_sdphy_init_pads_out_ready \main_sdphy_clocker_ce + connect \main_sdphy_cmdw_pads_out_ready \main_sdphy_clocker_ce + connect \main_sdphy_cmdr_pads_out_ready \main_sdphy_clocker_ce + connect \main_sdphy_dataw_pads_out_ready \main_sdphy_clocker_ce + connect \main_sdphy_datar_pads_out_ready \main_sdphy_clocker_ce + connect \main_sdphy_init_pads_in_valid \main_sdphy_clocker_ce + connect \main_sdphy_init_pads_in_payload_cmd_i \main_sdphy_sdpads_cmd_i + connect \main_sdphy_init_pads_in_payload_data_i \main_sdphy_sdpads_data_i + connect \main_sdphy_cmdw_pads_in_valid \main_sdphy_clocker_ce + connect \main_sdphy_cmdw_pads_in_payload_cmd_i \main_sdphy_sdpads_cmd_i + connect \main_sdphy_cmdw_pads_in_payload_data_i \main_sdphy_sdpads_data_i + connect \main_sdphy_cmdr_pads_in_pads_in_valid \main_sdphy_clocker_ce + connect \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_i \main_sdphy_sdpads_cmd_i + connect \main_sdphy_cmdr_pads_in_pads_in_payload_data_i \main_sdphy_sdpads_data_i + connect \main_sdphy_dataw_pads_in_valid \main_sdphy_clocker_ce + connect \main_sdphy_dataw_pads_in_payload_cmd_i \main_sdphy_sdpads_cmd_i + connect \main_sdphy_dataw_pads_in_payload_data_i \main_sdphy_sdpads_data_i + connect \main_sdphy_datar_pads_in_pads_in_valid \main_sdphy_clocker_ce + connect \main_sdphy_datar_pads_in_pads_in_payload_cmd_i \main_sdphy_sdpads_cmd_i + connect \main_sdphy_datar_pads_in_pads_in_payload_data_i \main_sdphy_sdpads_data_i + connect \main_sdphy_clocker_stop $or$ls180.v:4257$630_Y + connect \main_sdphy_clocker_ce $and$ls180.v:4287$633_Y + connect \main_sdphy_cmdr_cmdr_pads_in_valid \main_sdphy_cmdr_pads_in_pads_in_valid + connect \main_sdphy_cmdr_pads_in_pads_in_ready \main_sdphy_cmdr_cmdr_pads_in_ready + connect \main_sdphy_cmdr_cmdr_pads_in_first \main_sdphy_cmdr_pads_in_pads_in_first + connect \main_sdphy_cmdr_cmdr_pads_in_last \main_sdphy_cmdr_pads_in_pads_in_last + connect \main_sdphy_cmdr_cmdr_pads_in_payload_clk \main_sdphy_cmdr_pads_in_pads_in_payload_clk + connect \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_i \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_i + connect \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_o \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_o + connect \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_oe \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_oe + connect \main_sdphy_cmdr_cmdr_pads_in_payload_data_i \main_sdphy_cmdr_pads_in_pads_in_payload_data_i + connect \main_sdphy_cmdr_cmdr_pads_in_payload_data_o \main_sdphy_cmdr_pads_in_pads_in_payload_data_o + connect \main_sdphy_cmdr_cmdr_pads_in_payload_data_oe \main_sdphy_cmdr_pads_in_pads_in_payload_data_oe + connect \main_sdphy_cmdr_cmdr_start $eq$ls180.v:4410$643_Y + connect \main_sdphy_cmdr_cmdr_converter_sink_valid $and$ls180.v:4411$645_Y + connect \main_sdphy_cmdr_cmdr_converter_sink_payload_data \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_i + connect \main_sdphy_cmdr_cmdr_buf_sink_valid \main_sdphy_cmdr_cmdr_source_source_valid1 + connect \main_sdphy_cmdr_cmdr_source_source_ready1 \main_sdphy_cmdr_cmdr_buf_sink_ready + connect \main_sdphy_cmdr_cmdr_buf_sink_first \main_sdphy_cmdr_cmdr_source_source_first1 + connect \main_sdphy_cmdr_cmdr_buf_sink_last \main_sdphy_cmdr_cmdr_source_source_last1 + connect \main_sdphy_cmdr_cmdr_buf_sink_payload_data \main_sdphy_cmdr_cmdr_source_source_payload_data1 + connect \main_sdphy_cmdr_cmdr_source_source_valid0 \main_sdphy_cmdr_cmdr_buf_source_valid + connect \main_sdphy_cmdr_cmdr_buf_source_ready \main_sdphy_cmdr_cmdr_source_source_ready0 + connect \main_sdphy_cmdr_cmdr_source_source_first0 \main_sdphy_cmdr_cmdr_buf_source_first + connect \main_sdphy_cmdr_cmdr_source_source_last0 \main_sdphy_cmdr_cmdr_buf_source_last + connect \main_sdphy_cmdr_cmdr_source_source_payload_data0 \main_sdphy_cmdr_cmdr_buf_source_payload_data + connect \main_sdphy_cmdr_cmdr_source_source_valid1 \main_sdphy_cmdr_cmdr_converter_source_valid + connect \main_sdphy_cmdr_cmdr_converter_source_ready \main_sdphy_cmdr_cmdr_source_source_ready1 + connect \main_sdphy_cmdr_cmdr_source_source_first1 \main_sdphy_cmdr_cmdr_converter_source_first + connect \main_sdphy_cmdr_cmdr_source_source_last1 \main_sdphy_cmdr_cmdr_converter_source_last + connect \main_sdphy_cmdr_cmdr_source_source_payload_data1 \main_sdphy_cmdr_cmdr_converter_source_payload_data + connect \main_sdphy_cmdr_cmdr_converter_sink_ready $or$ls180.v:4428$647_Y + connect \main_sdphy_cmdr_cmdr_converter_source_valid \main_sdphy_cmdr_cmdr_converter_strobe_all + connect \main_sdphy_cmdr_cmdr_converter_load_part $and$ls180.v:4430$648_Y + connect \main_sdphy_cmdr_cmdr_buf_sink_ready $or$ls180.v:4431$650_Y + connect \main_sdphy_dataw_crcr_pads_in_valid \main_sdphy_dataw_pads_in_pads_in_valid + connect \main_sdphy_dataw_pads_in_pads_in_ready \main_sdphy_dataw_crcr_pads_in_ready + connect \main_sdphy_dataw_crcr_pads_in_first \main_sdphy_dataw_pads_in_pads_in_first + connect \main_sdphy_dataw_crcr_pads_in_last \main_sdphy_dataw_pads_in_pads_in_last + connect \main_sdphy_dataw_crcr_pads_in_payload_clk \main_sdphy_dataw_pads_in_pads_in_payload_clk + connect \main_sdphy_dataw_crcr_pads_in_payload_cmd_i \main_sdphy_dataw_pads_in_pads_in_payload_cmd_i + connect \main_sdphy_dataw_crcr_pads_in_payload_cmd_o \main_sdphy_dataw_pads_in_pads_in_payload_cmd_o + connect \main_sdphy_dataw_crcr_pads_in_payload_cmd_oe \main_sdphy_dataw_pads_in_pads_in_payload_cmd_oe + connect \main_sdphy_dataw_crcr_pads_in_payload_data_i \main_sdphy_dataw_pads_in_pads_in_payload_data_i + connect \main_sdphy_dataw_crcr_pads_in_payload_data_o \main_sdphy_dataw_pads_in_pads_in_payload_data_o + connect \main_sdphy_dataw_crcr_pads_in_payload_data_oe \main_sdphy_dataw_pads_in_pads_in_payload_data_oe + connect \main_sdphy_dataw_crcr_start $eq$ls180.v:4537$665_Y + connect \main_sdphy_dataw_crcr_converter_sink_valid $and$ls180.v:4538$666_Y + connect \main_sdphy_dataw_crcr_converter_sink_payload_data \main_sdphy_dataw_crcr_pads_in_payload_data_i [0] + connect \main_sdphy_dataw_crcr_buf_sink_valid \main_sdphy_dataw_crcr_source_source_valid1 + connect \main_sdphy_dataw_crcr_source_source_ready1 \main_sdphy_dataw_crcr_buf_sink_ready + connect \main_sdphy_dataw_crcr_buf_sink_first \main_sdphy_dataw_crcr_source_source_first1 + connect \main_sdphy_dataw_crcr_buf_sink_last \main_sdphy_dataw_crcr_source_source_last1 + connect \main_sdphy_dataw_crcr_buf_sink_payload_data \main_sdphy_dataw_crcr_source_source_payload_data1 + connect \main_sdphy_dataw_crcr_source_source_valid0 \main_sdphy_dataw_crcr_buf_source_valid + connect \main_sdphy_dataw_crcr_buf_source_ready \main_sdphy_dataw_crcr_source_source_ready0 + connect \main_sdphy_dataw_crcr_source_source_first0 \main_sdphy_dataw_crcr_buf_source_first + connect \main_sdphy_dataw_crcr_source_source_last0 \main_sdphy_dataw_crcr_buf_source_last + connect \main_sdphy_dataw_crcr_source_source_payload_data0 \main_sdphy_dataw_crcr_buf_source_payload_data + connect \main_sdphy_dataw_crcr_source_source_valid1 \main_sdphy_dataw_crcr_converter_source_valid + connect \main_sdphy_dataw_crcr_converter_source_ready \main_sdphy_dataw_crcr_source_source_ready1 + connect \main_sdphy_dataw_crcr_source_source_first1 \main_sdphy_dataw_crcr_converter_source_first + connect \main_sdphy_dataw_crcr_source_source_last1 \main_sdphy_dataw_crcr_converter_source_last + connect \main_sdphy_dataw_crcr_source_source_payload_data1 \main_sdphy_dataw_crcr_converter_source_payload_data + connect \main_sdphy_dataw_crcr_converter_sink_ready $or$ls180.v:4555$668_Y + connect \main_sdphy_dataw_crcr_converter_source_valid \main_sdphy_dataw_crcr_converter_strobe_all + connect \main_sdphy_dataw_crcr_converter_load_part $and$ls180.v:4557$669_Y + connect \main_sdphy_dataw_crcr_buf_sink_ready $or$ls180.v:4558$671_Y + connect \main_sdphy_datar_datar_pads_in_valid \main_sdphy_datar_pads_in_pads_in_valid + connect \main_sdphy_datar_pads_in_pads_in_ready \main_sdphy_datar_datar_pads_in_ready + connect \main_sdphy_datar_datar_pads_in_first \main_sdphy_datar_pads_in_pads_in_first + connect \main_sdphy_datar_datar_pads_in_last \main_sdphy_datar_pads_in_pads_in_last + connect \main_sdphy_datar_datar_pads_in_payload_clk \main_sdphy_datar_pads_in_pads_in_payload_clk + connect \main_sdphy_datar_datar_pads_in_payload_cmd_i \main_sdphy_datar_pads_in_pads_in_payload_cmd_i + connect \main_sdphy_datar_datar_pads_in_payload_cmd_o \main_sdphy_datar_pads_in_pads_in_payload_cmd_o + connect \main_sdphy_datar_datar_pads_in_payload_cmd_oe \main_sdphy_datar_pads_in_pads_in_payload_cmd_oe + connect \main_sdphy_datar_datar_pads_in_payload_data_i \main_sdphy_datar_pads_in_pads_in_payload_data_i + connect \main_sdphy_datar_datar_pads_in_payload_data_o \main_sdphy_datar_pads_in_pads_in_payload_data_o + connect \main_sdphy_datar_datar_pads_in_payload_data_oe \main_sdphy_datar_pads_in_pads_in_payload_data_oe + connect \main_sdphy_datar_datar_start $eq$ls180.v:4671$680_Y + connect \main_sdphy_datar_datar_converter_sink_valid $and$ls180.v:4672$681_Y + connect \main_sdphy_datar_datar_converter_sink_payload_data \main_sdphy_datar_datar_pads_in_payload_data_i + connect \main_sdphy_datar_datar_buf_sink_valid \main_sdphy_datar_datar_source_source_valid1 + connect \main_sdphy_datar_datar_source_source_ready1 \main_sdphy_datar_datar_buf_sink_ready + connect \main_sdphy_datar_datar_buf_sink_first \main_sdphy_datar_datar_source_source_first1 + connect \main_sdphy_datar_datar_buf_sink_last \main_sdphy_datar_datar_source_source_last1 + connect \main_sdphy_datar_datar_buf_sink_payload_data \main_sdphy_datar_datar_source_source_payload_data1 + connect \main_sdphy_datar_datar_source_source_valid0 \main_sdphy_datar_datar_buf_source_valid + connect \main_sdphy_datar_datar_buf_source_ready \main_sdphy_datar_datar_source_source_ready0 + connect \main_sdphy_datar_datar_source_source_first0 \main_sdphy_datar_datar_buf_source_first + connect \main_sdphy_datar_datar_source_source_last0 \main_sdphy_datar_datar_buf_source_last + connect \main_sdphy_datar_datar_source_source_payload_data0 \main_sdphy_datar_datar_buf_source_payload_data + connect \main_sdphy_datar_datar_source_source_valid1 \main_sdphy_datar_datar_converter_source_valid + connect \main_sdphy_datar_datar_converter_source_ready \main_sdphy_datar_datar_source_source_ready1 + connect \main_sdphy_datar_datar_source_source_first1 \main_sdphy_datar_datar_converter_source_first + connect \main_sdphy_datar_datar_source_source_last1 \main_sdphy_datar_datar_converter_source_last + connect \main_sdphy_datar_datar_source_source_payload_data1 \main_sdphy_datar_datar_converter_source_payload_data + connect \main_sdphy_datar_datar_converter_sink_ready $or$ls180.v:4689$683_Y + connect \main_sdphy_datar_datar_converter_source_valid \main_sdphy_datar_datar_converter_strobe_all + connect \main_sdphy_datar_datar_converter_load_part $and$ls180.v:4691$684_Y + connect \main_sdphy_datar_datar_buf_sink_ready $or$ls180.v:4692$686_Y + connect \main_sdcore_crc16_inserter_sink_valid \main_sdcore_sink_sink_valid + connect \main_sdcore_sink_sink_ready \main_sdcore_crc16_inserter_sink_ready + connect \main_sdcore_crc16_inserter_sink_first \main_sdcore_sink_sink_first + connect \main_sdcore_crc16_inserter_sink_last \main_sdcore_sink_sink_last + connect \main_sdcore_crc16_inserter_sink_payload_data \main_sdcore_sink_sink_payload_data + connect \main_sdcore_source_source_valid \main_sdcore_crc16_checker_source_valid + connect \main_sdcore_crc16_checker_source_ready \main_sdcore_source_source_ready + connect \main_sdcore_source_source_first \main_sdcore_crc16_checker_source_first + connect \main_sdcore_source_source_last \main_sdcore_crc16_checker_source_last + connect \main_sdcore_source_source_payload_data \main_sdcore_crc16_checker_source_payload_data + connect \main_sdcore_cmd_type \main_sdcore_cmd_command_storage [1:0] + connect \main_sdcore_data_type \main_sdcore_cmd_command_storage [6:5] + connect \main_sdcore_cmd_event_status { 1'0 \main_sdcore_cmd_timeout \main_sdcore_cmd_error \main_sdcore_cmd_done } + connect \main_sdcore_data_event_status { $not$ls180.v:4808$701_Y \main_sdcore_data_timeout \main_sdcore_data_error \main_sdcore_data_done } + connect \main_sdcore_crc7_inserter_val { 2'01 \main_sdcore_cmd_command_storage [13:8] \main_sdcore_cmd_argument_storage } + connect \main_sdcore_crc7_inserter_clr 1'1 + connect \main_sdcore_crc7_inserter_enable 1'1 + connect \main_sdcore_crc7_inserter_crcreg1 { \main_sdcore_crc7_inserter_crcreg0 [5:3] $xor$ls180.v:4812$704_Y \main_sdcore_crc7_inserter_crcreg0 [1:0] $xor$ls180.v:4812$702_Y } + connect \main_sdcore_crc7_inserter_crcreg2 { \main_sdcore_crc7_inserter_crcreg1 [5:3] $xor$ls180.v:4813$707_Y \main_sdcore_crc7_inserter_crcreg1 [1:0] $xor$ls180.v:4813$705_Y } + connect \main_sdcore_crc7_inserter_crcreg3 { \main_sdcore_crc7_inserter_crcreg2 [5:3] $xor$ls180.v:4814$710_Y \main_sdcore_crc7_inserter_crcreg2 [1:0] $xor$ls180.v:4814$708_Y } + connect \main_sdcore_crc7_inserter_crcreg4 { \main_sdcore_crc7_inserter_crcreg3 [5:3] $xor$ls180.v:4815$713_Y \main_sdcore_crc7_inserter_crcreg3 [1:0] $xor$ls180.v:4815$711_Y } + connect \main_sdcore_crc7_inserter_crcreg5 { \main_sdcore_crc7_inserter_crcreg4 [5:3] $xor$ls180.v:4816$716_Y \main_sdcore_crc7_inserter_crcreg4 [1:0] $xor$ls180.v:4816$714_Y } + connect \main_sdcore_crc7_inserter_crcreg6 { \main_sdcore_crc7_inserter_crcreg5 [5:3] $xor$ls180.v:4817$719_Y \main_sdcore_crc7_inserter_crcreg5 [1:0] $xor$ls180.v:4817$717_Y } + connect \main_sdcore_crc7_inserter_crcreg7 { \main_sdcore_crc7_inserter_crcreg6 [5:3] $xor$ls180.v:4818$722_Y \main_sdcore_crc7_inserter_crcreg6 [1:0] $xor$ls180.v:4818$720_Y } + connect \main_sdcore_crc7_inserter_crcreg8 { \main_sdcore_crc7_inserter_crcreg7 [5:3] $xor$ls180.v:4819$725_Y \main_sdcore_crc7_inserter_crcreg7 [1:0] $xor$ls180.v:4819$723_Y } + connect \main_sdcore_crc7_inserter_crcreg9 { \main_sdcore_crc7_inserter_crcreg8 [5:3] $xor$ls180.v:4820$728_Y \main_sdcore_crc7_inserter_crcreg8 [1:0] $xor$ls180.v:4820$726_Y } + connect \main_sdcore_crc7_inserter_crcreg10 { \main_sdcore_crc7_inserter_crcreg9 [5:3] $xor$ls180.v:4821$731_Y \main_sdcore_crc7_inserter_crcreg9 [1:0] $xor$ls180.v:4821$729_Y } + connect \main_sdcore_crc7_inserter_crcreg11 { \main_sdcore_crc7_inserter_crcreg10 [5:3] $xor$ls180.v:4822$734_Y \main_sdcore_crc7_inserter_crcreg10 [1:0] $xor$ls180.v:4822$732_Y } + connect \main_sdcore_crc7_inserter_crcreg12 { \main_sdcore_crc7_inserter_crcreg11 [5:3] $xor$ls180.v:4823$737_Y \main_sdcore_crc7_inserter_crcreg11 [1:0] $xor$ls180.v:4823$735_Y } + connect \main_sdcore_crc7_inserter_crcreg13 { \main_sdcore_crc7_inserter_crcreg12 [5:3] $xor$ls180.v:4824$740_Y \main_sdcore_crc7_inserter_crcreg12 [1:0] $xor$ls180.v:4824$738_Y } + connect \main_sdcore_crc7_inserter_crcreg14 { \main_sdcore_crc7_inserter_crcreg13 [5:3] $xor$ls180.v:4825$743_Y \main_sdcore_crc7_inserter_crcreg13 [1:0] $xor$ls180.v:4825$741_Y } + connect \main_sdcore_crc7_inserter_crcreg15 { \main_sdcore_crc7_inserter_crcreg14 [5:3] $xor$ls180.v:4826$746_Y \main_sdcore_crc7_inserter_crcreg14 [1:0] $xor$ls180.v:4826$744_Y } + connect \main_sdcore_crc7_inserter_crcreg16 { \main_sdcore_crc7_inserter_crcreg15 [5:3] $xor$ls180.v:4827$749_Y \main_sdcore_crc7_inserter_crcreg15 [1:0] $xor$ls180.v:4827$747_Y } + connect \main_sdcore_crc7_inserter_crcreg17 { \main_sdcore_crc7_inserter_crcreg16 [5:3] $xor$ls180.v:4828$752_Y \main_sdcore_crc7_inserter_crcreg16 [1:0] $xor$ls180.v:4828$750_Y } + connect \main_sdcore_crc7_inserter_crcreg18 { \main_sdcore_crc7_inserter_crcreg17 [5:3] $xor$ls180.v:4829$755_Y \main_sdcore_crc7_inserter_crcreg17 [1:0] $xor$ls180.v:4829$753_Y } + connect \main_sdcore_crc7_inserter_crcreg19 { \main_sdcore_crc7_inserter_crcreg18 [5:3] $xor$ls180.v:4830$758_Y \main_sdcore_crc7_inserter_crcreg18 [1:0] $xor$ls180.v:4830$756_Y } + connect \main_sdcore_crc7_inserter_crcreg20 { \main_sdcore_crc7_inserter_crcreg19 [5:3] $xor$ls180.v:4831$761_Y \main_sdcore_crc7_inserter_crcreg19 [1:0] $xor$ls180.v:4831$759_Y } + connect \main_sdcore_crc7_inserter_crcreg21 { \main_sdcore_crc7_inserter_crcreg20 [5:3] $xor$ls180.v:4832$764_Y \main_sdcore_crc7_inserter_crcreg20 [1:0] $xor$ls180.v:4832$762_Y } + connect \main_sdcore_crc7_inserter_crcreg22 { \main_sdcore_crc7_inserter_crcreg21 [5:3] $xor$ls180.v:4833$767_Y \main_sdcore_crc7_inserter_crcreg21 [1:0] $xor$ls180.v:4833$765_Y } + connect \main_sdcore_crc7_inserter_crcreg23 { \main_sdcore_crc7_inserter_crcreg22 [5:3] $xor$ls180.v:4834$770_Y \main_sdcore_crc7_inserter_crcreg22 [1:0] $xor$ls180.v:4834$768_Y } + connect \main_sdcore_crc7_inserter_crcreg24 { \main_sdcore_crc7_inserter_crcreg23 [5:3] $xor$ls180.v:4835$773_Y \main_sdcore_crc7_inserter_crcreg23 [1:0] $xor$ls180.v:4835$771_Y } + connect \main_sdcore_crc7_inserter_crcreg25 { \main_sdcore_crc7_inserter_crcreg24 [5:3] $xor$ls180.v:4836$776_Y \main_sdcore_crc7_inserter_crcreg24 [1:0] $xor$ls180.v:4836$774_Y } + connect \main_sdcore_crc7_inserter_crcreg26 { \main_sdcore_crc7_inserter_crcreg25 [5:3] $xor$ls180.v:4837$779_Y \main_sdcore_crc7_inserter_crcreg25 [1:0] $xor$ls180.v:4837$777_Y } + connect \main_sdcore_crc7_inserter_crcreg27 { \main_sdcore_crc7_inserter_crcreg26 [5:3] $xor$ls180.v:4838$782_Y \main_sdcore_crc7_inserter_crcreg26 [1:0] $xor$ls180.v:4838$780_Y } + connect \main_sdcore_crc7_inserter_crcreg28 { \main_sdcore_crc7_inserter_crcreg27 [5:3] $xor$ls180.v:4839$785_Y \main_sdcore_crc7_inserter_crcreg27 [1:0] $xor$ls180.v:4839$783_Y } + connect \main_sdcore_crc7_inserter_crcreg29 { \main_sdcore_crc7_inserter_crcreg28 [5:3] $xor$ls180.v:4840$788_Y \main_sdcore_crc7_inserter_crcreg28 [1:0] $xor$ls180.v:4840$786_Y } + connect \main_sdcore_crc7_inserter_crcreg30 { \main_sdcore_crc7_inserter_crcreg29 [5:3] $xor$ls180.v:4841$791_Y \main_sdcore_crc7_inserter_crcreg29 [1:0] $xor$ls180.v:4841$789_Y } + connect \main_sdcore_crc7_inserter_crcreg31 { \main_sdcore_crc7_inserter_crcreg30 [5:3] $xor$ls180.v:4842$794_Y \main_sdcore_crc7_inserter_crcreg30 [1:0] $xor$ls180.v:4842$792_Y } + connect \main_sdcore_crc7_inserter_crcreg32 { \main_sdcore_crc7_inserter_crcreg31 [5:3] $xor$ls180.v:4843$797_Y \main_sdcore_crc7_inserter_crcreg31 [1:0] $xor$ls180.v:4843$795_Y } + connect \main_sdcore_crc7_inserter_crcreg33 { \main_sdcore_crc7_inserter_crcreg32 [5:3] $xor$ls180.v:4844$800_Y \main_sdcore_crc7_inserter_crcreg32 [1:0] $xor$ls180.v:4844$798_Y } + connect \main_sdcore_crc7_inserter_crcreg34 { \main_sdcore_crc7_inserter_crcreg33 [5:3] $xor$ls180.v:4845$803_Y \main_sdcore_crc7_inserter_crcreg33 [1:0] $xor$ls180.v:4845$801_Y } + connect \main_sdcore_crc7_inserter_crcreg35 { \main_sdcore_crc7_inserter_crcreg34 [5:3] $xor$ls180.v:4846$806_Y \main_sdcore_crc7_inserter_crcreg34 [1:0] $xor$ls180.v:4846$804_Y } + connect \main_sdcore_crc7_inserter_crcreg36 { \main_sdcore_crc7_inserter_crcreg35 [5:3] $xor$ls180.v:4847$809_Y \main_sdcore_crc7_inserter_crcreg35 [1:0] $xor$ls180.v:4847$807_Y } + connect \main_sdcore_crc7_inserter_crcreg37 { \main_sdcore_crc7_inserter_crcreg36 [5:3] $xor$ls180.v:4848$812_Y \main_sdcore_crc7_inserter_crcreg36 [1:0] $xor$ls180.v:4848$810_Y } + connect \main_sdcore_crc7_inserter_crcreg38 { \main_sdcore_crc7_inserter_crcreg37 [5:3] $xor$ls180.v:4849$815_Y \main_sdcore_crc7_inserter_crcreg37 [1:0] $xor$ls180.v:4849$813_Y } + connect \main_sdcore_crc7_inserter_crcreg39 { \main_sdcore_crc7_inserter_crcreg38 [5:3] $xor$ls180.v:4850$818_Y \main_sdcore_crc7_inserter_crcreg38 [1:0] $xor$ls180.v:4850$816_Y } + connect \main_sdcore_crc7_inserter_crcreg40 { \main_sdcore_crc7_inserter_crcreg39 [5:3] $xor$ls180.v:4851$821_Y \main_sdcore_crc7_inserter_crcreg39 [1:0] $xor$ls180.v:4851$819_Y } + connect \main_sdcore_crc16_inserter_crc0_val { \main_sdcore_crc16_inserter_sink_payload_data [4] \main_sdcore_crc16_inserter_sink_payload_data [0] } + connect \main_sdcore_crc16_inserter_crc0_clr $and$ls180.v:4861$824_Y + connect \main_sdcore_crc16_inserter_crc0_enable $and$ls180.v:4862$825_Y + connect \main_sdcore_crc16_inserter_crc1_val { \main_sdcore_crc16_inserter_sink_payload_data [5] \main_sdcore_crc16_inserter_sink_payload_data [1] } + connect \main_sdcore_crc16_inserter_crc1_clr $and$ls180.v:4864$827_Y + connect \main_sdcore_crc16_inserter_crc1_enable $and$ls180.v:4865$828_Y + connect \main_sdcore_crc16_inserter_crc2_val { \main_sdcore_crc16_inserter_sink_payload_data [6] \main_sdcore_crc16_inserter_sink_payload_data [2] } + connect \main_sdcore_crc16_inserter_crc2_clr $and$ls180.v:4867$830_Y + connect \main_sdcore_crc16_inserter_crc2_enable $and$ls180.v:4868$831_Y + connect \main_sdcore_crc16_inserter_crc3_val { \main_sdcore_crc16_inserter_sink_payload_data [7] \main_sdcore_crc16_inserter_sink_payload_data [3] } + connect \main_sdcore_crc16_inserter_crc3_clr $and$ls180.v:4870$833_Y + connect \main_sdcore_crc16_inserter_crc3_enable $and$ls180.v:4871$834_Y + connect \main_sdcore_crc16_inserter_crc0_crcreg1 { \main_sdcore_crc16_inserter_crc0_crcreg0 [14:12] $xor$ls180.v:4872$839_Y \main_sdcore_crc16_inserter_crc0_crcreg0 [10:5] $xor$ls180.v:4872$837_Y \main_sdcore_crc16_inserter_crc0_crcreg0 [3:0] $xor$ls180.v:4872$835_Y } + connect \main_sdcore_crc16_inserter_crc0_crcreg2 { \main_sdcore_crc16_inserter_crc0_crcreg1 [14:12] $xor$ls180.v:4873$844_Y \main_sdcore_crc16_inserter_crc0_crcreg1 [10:5] $xor$ls180.v:4873$842_Y \main_sdcore_crc16_inserter_crc0_crcreg1 [3:0] $xor$ls180.v:4873$840_Y } + connect \main_sdcore_crc16_inserter_crc1_crcreg1 { \main_sdcore_crc16_inserter_crc1_crcreg0 [14:12] $xor$ls180.v:4882$850_Y \main_sdcore_crc16_inserter_crc1_crcreg0 [10:5] $xor$ls180.v:4882$848_Y \main_sdcore_crc16_inserter_crc1_crcreg0 [3:0] $xor$ls180.v:4882$846_Y } + connect \main_sdcore_crc16_inserter_crc1_crcreg2 { \main_sdcore_crc16_inserter_crc1_crcreg1 [14:12] $xor$ls180.v:4883$855_Y \main_sdcore_crc16_inserter_crc1_crcreg1 [10:5] $xor$ls180.v:4883$853_Y \main_sdcore_crc16_inserter_crc1_crcreg1 [3:0] $xor$ls180.v:4883$851_Y } + connect \main_sdcore_crc16_inserter_crc2_crcreg1 { \main_sdcore_crc16_inserter_crc2_crcreg0 [14:12] $xor$ls180.v:4892$861_Y \main_sdcore_crc16_inserter_crc2_crcreg0 [10:5] $xor$ls180.v:4892$859_Y \main_sdcore_crc16_inserter_crc2_crcreg0 [3:0] $xor$ls180.v:4892$857_Y } + connect \main_sdcore_crc16_inserter_crc2_crcreg2 { \main_sdcore_crc16_inserter_crc2_crcreg1 [14:12] $xor$ls180.v:4893$866_Y \main_sdcore_crc16_inserter_crc2_crcreg1 [10:5] $xor$ls180.v:4893$864_Y \main_sdcore_crc16_inserter_crc2_crcreg1 [3:0] $xor$ls180.v:4893$862_Y } + connect \main_sdcore_crc16_inserter_crc3_crcreg1 { \main_sdcore_crc16_inserter_crc3_crcreg0 [14:12] $xor$ls180.v:4902$872_Y \main_sdcore_crc16_inserter_crc3_crcreg0 [10:5] $xor$ls180.v:4902$870_Y \main_sdcore_crc16_inserter_crc3_crcreg0 [3:0] $xor$ls180.v:4902$868_Y } + connect \main_sdcore_crc16_inserter_crc3_crcreg2 { \main_sdcore_crc16_inserter_crc3_crcreg1 [14:12] $xor$ls180.v:4903$877_Y \main_sdcore_crc16_inserter_crc3_crcreg1 [10:5] $xor$ls180.v:4903$875_Y \main_sdcore_crc16_inserter_crc3_crcreg1 [3:0] $xor$ls180.v:4903$873_Y } + connect \main_sdcore_crc16_checker_crc0_val { \main_sdcore_crc16_checker_val [7] \main_sdcore_crc16_checker_val [3] } + connect \main_sdcore_crc16_checker_crc0_enable $and$ls180.v:4999$893_Y + connect \main_sdcore_crc16_checker_crc1_val { \main_sdcore_crc16_checker_val [6] \main_sdcore_crc16_checker_val [2] } + connect \main_sdcore_crc16_checker_crc1_enable $and$ls180.v:5009$896_Y + connect \main_sdcore_crc16_checker_crc2_val { \main_sdcore_crc16_checker_val [5] \main_sdcore_crc16_checker_val [1] } + connect \main_sdcore_crc16_checker_crc2_enable $and$ls180.v:5019$899_Y + connect \main_sdcore_crc16_checker_crc3_val { \main_sdcore_crc16_checker_val [4] \main_sdcore_crc16_checker_val [0] } + connect \main_sdcore_crc16_checker_crc3_enable $and$ls180.v:5029$902_Y + connect \main_sdcore_crc16_checker_source_payload_data \main_sdcore_crc16_checker_val + connect \main_sdcore_crc16_checker_source_last \main_sdcore_crc16_checker_sink_last + connect \main_sdcore_crc16_checker_crc0_crcreg1 { \main_sdcore_crc16_checker_crc0_crcreg0 [14:12] $xor$ls180.v:5054$914_Y \main_sdcore_crc16_checker_crc0_crcreg0 [10:5] $xor$ls180.v:5054$912_Y \main_sdcore_crc16_checker_crc0_crcreg0 [3:0] $xor$ls180.v:5054$910_Y } + connect \main_sdcore_crc16_checker_crc0_crcreg2 { \main_sdcore_crc16_checker_crc0_crcreg1 [14:12] $xor$ls180.v:5055$919_Y \main_sdcore_crc16_checker_crc0_crcreg1 [10:5] $xor$ls180.v:5055$917_Y \main_sdcore_crc16_checker_crc0_crcreg1 [3:0] $xor$ls180.v:5055$915_Y } + connect \main_sdcore_crc16_checker_crc1_crcreg1 { \main_sdcore_crc16_checker_crc1_crcreg0 [14:12] $xor$ls180.v:5064$925_Y \main_sdcore_crc16_checker_crc1_crcreg0 [10:5] $xor$ls180.v:5064$923_Y \main_sdcore_crc16_checker_crc1_crcreg0 [3:0] $xor$ls180.v:5064$921_Y } + connect \main_sdcore_crc16_checker_crc1_crcreg2 { \main_sdcore_crc16_checker_crc1_crcreg1 [14:12] $xor$ls180.v:5065$930_Y \main_sdcore_crc16_checker_crc1_crcreg1 [10:5] $xor$ls180.v:5065$928_Y \main_sdcore_crc16_checker_crc1_crcreg1 [3:0] $xor$ls180.v:5065$926_Y } + connect \main_sdcore_crc16_checker_crc2_crcreg1 { \main_sdcore_crc16_checker_crc2_crcreg0 [14:12] $xor$ls180.v:5074$936_Y \main_sdcore_crc16_checker_crc2_crcreg0 [10:5] $xor$ls180.v:5074$934_Y \main_sdcore_crc16_checker_crc2_crcreg0 [3:0] $xor$ls180.v:5074$932_Y } + connect \main_sdcore_crc16_checker_crc2_crcreg2 { \main_sdcore_crc16_checker_crc2_crcreg1 [14:12] $xor$ls180.v:5075$941_Y \main_sdcore_crc16_checker_crc2_crcreg1 [10:5] $xor$ls180.v:5075$939_Y \main_sdcore_crc16_checker_crc2_crcreg1 [3:0] $xor$ls180.v:5075$937_Y } + connect \main_sdcore_crc16_checker_crc3_crcreg1 { \main_sdcore_crc16_checker_crc3_crcreg0 [14:12] $xor$ls180.v:5084$947_Y \main_sdcore_crc16_checker_crc3_crcreg0 [10:5] $xor$ls180.v:5084$945_Y \main_sdcore_crc16_checker_crc3_crcreg0 [3:0] $xor$ls180.v:5084$943_Y } + connect \main_sdcore_crc16_checker_crc3_crcreg2 { \main_sdcore_crc16_checker_crc3_crcreg1 [14:12] $xor$ls180.v:5085$952_Y \main_sdcore_crc16_checker_crc3_crcreg1 [10:5] $xor$ls180.v:5085$950_Y \main_sdcore_crc16_checker_crc3_crcreg1 [3:0] $xor$ls180.v:5085$948_Y } + connect \main_sdblock2mem_fifo_sink_valid \main_sdblock2mem_sink_sink_valid0 + connect \main_sdblock2mem_sink_sink_ready0 \main_sdblock2mem_fifo_sink_ready + connect \main_sdblock2mem_fifo_sink_first \main_sdblock2mem_sink_sink_first + connect \main_sdblock2mem_fifo_sink_last \main_sdblock2mem_sink_sink_last + connect \main_sdblock2mem_fifo_sink_payload_data \main_sdblock2mem_sink_sink_payload_data0 + connect \main_sdblock2mem_converter_sink_valid \main_sdblock2mem_fifo_source_valid + connect \main_sdblock2mem_fifo_source_ready \main_sdblock2mem_converter_sink_ready + connect \main_sdblock2mem_converter_sink_first \main_sdblock2mem_fifo_source_first + connect \main_sdblock2mem_converter_sink_last \main_sdblock2mem_fifo_source_last + connect \main_sdblock2mem_converter_sink_payload_data \main_sdblock2mem_fifo_source_payload_data + connect \main_sdblock2mem_wishbonedmawriter_sink_valid \main_sdblock2mem_source_source_valid + connect \main_sdblock2mem_source_source_ready \main_sdblock2mem_wishbonedmawriter_sink_ready + connect \main_sdblock2mem_wishbonedmawriter_sink_first \main_sdblock2mem_source_source_first + connect \main_sdblock2mem_wishbonedmawriter_sink_last \main_sdblock2mem_source_source_last + connect \main_sdblock2mem_wishbonedmawriter_sink_payload_data \main_sdblock2mem_source_source_payload_data + connect \main_sdblock2mem_fifo_syncfifo_din { \main_sdblock2mem_fifo_fifo_in_last \main_sdblock2mem_fifo_fifo_in_first \main_sdblock2mem_fifo_fifo_in_payload_data } + connect { \main_sdblock2mem_fifo_fifo_out_last \main_sdblock2mem_fifo_fifo_out_first \main_sdblock2mem_fifo_fifo_out_payload_data } \main_sdblock2mem_fifo_syncfifo_dout + connect \main_sdblock2mem_fifo_sink_ready \main_sdblock2mem_fifo_syncfifo_writable + connect \main_sdblock2mem_fifo_syncfifo_we \main_sdblock2mem_fifo_sink_valid + connect \main_sdblock2mem_fifo_fifo_in_first \main_sdblock2mem_fifo_sink_first + connect \main_sdblock2mem_fifo_fifo_in_last \main_sdblock2mem_fifo_sink_last + connect \main_sdblock2mem_fifo_fifo_in_payload_data \main_sdblock2mem_fifo_sink_payload_data + connect \main_sdblock2mem_fifo_source_valid \main_sdblock2mem_fifo_syncfifo_readable + connect \main_sdblock2mem_fifo_source_first \main_sdblock2mem_fifo_fifo_out_first + connect \main_sdblock2mem_fifo_source_last \main_sdblock2mem_fifo_fifo_out_last + connect \main_sdblock2mem_fifo_source_payload_data \main_sdblock2mem_fifo_fifo_out_payload_data + connect \main_sdblock2mem_fifo_syncfifo_re \main_sdblock2mem_fifo_source_ready + connect \main_sdblock2mem_fifo_wrport_dat_w \main_sdblock2mem_fifo_syncfifo_din + connect \main_sdblock2mem_fifo_wrport_we $and$ls180.v:5321$982_Y + connect \main_sdblock2mem_fifo_do_read $and$ls180.v:5322$983_Y + connect \main_sdblock2mem_fifo_rdport_adr \main_sdblock2mem_fifo_consume + connect \main_sdblock2mem_fifo_syncfifo_dout \main_sdblock2mem_fifo_rdport_dat_r + connect \main_sdblock2mem_fifo_syncfifo_writable $ne$ls180.v:5325$984_Y + connect \main_sdblock2mem_fifo_syncfifo_readable $ne$ls180.v:5326$985_Y + connect \main_sdblock2mem_source_source_valid \main_sdblock2mem_converter_source_valid + connect \main_sdblock2mem_converter_source_ready \main_sdblock2mem_source_source_ready + connect \main_sdblock2mem_source_source_first \main_sdblock2mem_converter_source_first + connect \main_sdblock2mem_source_source_last \main_sdblock2mem_converter_source_last + connect \main_sdblock2mem_source_source_payload_data \main_sdblock2mem_converter_source_payload_data + connect \main_sdblock2mem_converter_sink_ready $or$ls180.v:5332$987_Y + connect \main_sdblock2mem_converter_source_valid \main_sdblock2mem_converter_strobe_all + connect \main_sdblock2mem_converter_load_part $and$ls180.v:5334$988_Y + connect \main_interface0_bus_stb \main_sdblock2mem_sink_sink_valid1 + connect \main_interface0_bus_cyc \main_sdblock2mem_sink_sink_valid1 + connect \main_interface0_bus_we 1'1 + connect \main_interface0_bus_sel 4'1111 + connect \main_interface0_bus_adr \main_sdblock2mem_sink_sink_payload_address + connect \main_interface0_bus_dat_w { \main_sdblock2mem_sink_sink_payload_data1 [7:0] \main_sdblock2mem_sink_sink_payload_data1 [15:8] \main_sdblock2mem_sink_sink_payload_data1 [23:16] \main_sdblock2mem_sink_sink_payload_data1 [31:24] } + connect \main_sdblock2mem_sink_sink_ready1 \main_interface0_bus_ack + connect \main_sdblock2mem_wishbonedmawriter_base \main_sdblock2mem_wishbonedmawriter_base_storage [33:2] + connect \main_sdblock2mem_wishbonedmawriter_length { 2'00 \main_sdblock2mem_wishbonedmawriter_length_storage [31:2] } + connect \main_sdblock2mem_wishbonedmawriter_reset $not$ls180.v:5344$989_Y + connect \main_sdmem2block_converter_sink_valid \main_sdmem2block_dma_source_valid + connect \main_sdmem2block_dma_source_ready \main_sdmem2block_converter_sink_ready + connect \main_sdmem2block_converter_sink_first \main_sdmem2block_dma_source_first + connect \main_sdmem2block_converter_sink_last \main_sdmem2block_dma_source_last + connect \main_sdmem2block_converter_sink_payload_data \main_sdmem2block_dma_source_payload_data + connect \main_sdmem2block_fifo_sink_valid \main_sdmem2block_source_source_valid1 + connect \main_sdmem2block_source_source_ready1 \main_sdmem2block_fifo_sink_ready + connect \main_sdmem2block_fifo_sink_first \main_sdmem2block_source_source_first1 + connect \main_sdmem2block_fifo_sink_last \main_sdmem2block_source_source_last1 + connect \main_sdmem2block_fifo_sink_payload_data \main_sdmem2block_source_source_payload_data1 + connect \main_sdmem2block_source_source_valid0 \main_sdmem2block_fifo_source_valid + connect \main_sdmem2block_fifo_source_ready \main_sdmem2block_source_source_ready0 + connect \main_sdmem2block_source_source_first0 \main_sdmem2block_fifo_source_first + connect \main_sdmem2block_source_source_last0 \main_sdmem2block_fifo_source_last + connect \main_sdmem2block_source_source_payload_data0 \main_sdmem2block_fifo_source_payload_data + connect \main_sdmem2block_dma_base \main_sdmem2block_dma_base_storage [33:2] + connect \main_sdmem2block_dma_length { 2'00 \main_sdmem2block_dma_length_storage [31:2] } + connect \main_sdmem2block_dma_offset_status \main_sdmem2block_dma_offset + connect \main_sdmem2block_dma_reset $not$ls180.v:5403$996_Y + connect \main_sdmem2block_source_source_valid1 \main_sdmem2block_converter_source_valid + connect \main_sdmem2block_converter_source_ready \main_sdmem2block_source_source_ready1 + connect \main_sdmem2block_source_source_first1 \main_sdmem2block_converter_source_first + connect \main_sdmem2block_source_source_last1 \main_sdmem2block_converter_source_last + connect \main_sdmem2block_source_source_payload_data1 \main_sdmem2block_converter_source_payload_data + connect \main_sdmem2block_converter_first $eq$ls180.v:5484$1004_Y + connect \main_sdmem2block_converter_last $eq$ls180.v:5485$1005_Y + connect \main_sdmem2block_converter_source_valid \main_sdmem2block_converter_sink_valid + connect \main_sdmem2block_converter_source_first $and$ls180.v:5487$1006_Y + connect \main_sdmem2block_converter_source_last $and$ls180.v:5488$1007_Y + connect \main_sdmem2block_converter_sink_ready $and$ls180.v:5489$1008_Y + connect \main_sdmem2block_converter_source_payload_valid_token_count \main_sdmem2block_converter_last + connect \main_sdmem2block_fifo_syncfifo_din { \main_sdmem2block_fifo_fifo_in_last \main_sdmem2block_fifo_fifo_in_first \main_sdmem2block_fifo_fifo_in_payload_data } + connect { \main_sdmem2block_fifo_fifo_out_last \main_sdmem2block_fifo_fifo_out_first \main_sdmem2block_fifo_fifo_out_payload_data } \main_sdmem2block_fifo_syncfifo_dout + connect \main_sdmem2block_fifo_sink_ready \main_sdmem2block_fifo_syncfifo_writable + connect \main_sdmem2block_fifo_syncfifo_we \main_sdmem2block_fifo_sink_valid + connect \main_sdmem2block_fifo_fifo_in_first \main_sdmem2block_fifo_sink_first + connect \main_sdmem2block_fifo_fifo_in_last \main_sdmem2block_fifo_sink_last + connect \main_sdmem2block_fifo_fifo_in_payload_data \main_sdmem2block_fifo_sink_payload_data + connect \main_sdmem2block_fifo_source_valid \main_sdmem2block_fifo_syncfifo_readable + connect \main_sdmem2block_fifo_source_first \main_sdmem2block_fifo_fifo_out_first + connect \main_sdmem2block_fifo_source_last \main_sdmem2block_fifo_fifo_out_last + connect \main_sdmem2block_fifo_source_payload_data \main_sdmem2block_fifo_fifo_out_payload_data + connect \main_sdmem2block_fifo_syncfifo_re \main_sdmem2block_fifo_source_ready + connect \main_sdmem2block_fifo_wrport_dat_w \main_sdmem2block_fifo_syncfifo_din + connect \main_sdmem2block_fifo_wrport_we $and$ls180.v:5529$1013_Y + connect \main_sdmem2block_fifo_do_read $and$ls180.v:5530$1014_Y + connect \main_sdmem2block_fifo_rdport_adr \main_sdmem2block_fifo_consume + connect \main_sdmem2block_fifo_syncfifo_dout \main_sdmem2block_fifo_rdport_dat_r + connect \main_sdmem2block_fifo_syncfifo_writable $ne$ls180.v:5533$1015_Y + connect \main_sdmem2block_fifo_syncfifo_readable $ne$ls180.v:5534$1016_Y + connect \libresocsim_start0 \libresocsim_start1 + connect \libresocsim_length0 \libresocsim_length1 + connect \libresocsim_mosi \libresocsim_mosi_storage + connect \libresocsim_done1 \libresocsim_done0 + connect \libresocsim_miso_status \libresocsim_miso + connect \libresocsim_cs \libresocsim_cs_storage + connect \libresocsim_loopback \libresocsim_loopback_storage + connect \libresocsim_clk_rise $eq$ls180.v:5542$1018_Y + connect \libresocsim_clk_fall $eq$ls180.v:5543$1020_Y + connect \libresocsim_clk_divider0 \libresocsim_storage + connect \builder_shared_adr \builder_comb_rhs_array_muxed24 [29:0] + connect \builder_shared_dat_w \builder_comb_rhs_array_muxed25 + connect \builder_shared_sel \builder_comb_rhs_array_muxed26 + connect \builder_shared_cyc \builder_comb_rhs_array_muxed27 + connect \builder_shared_stb \builder_comb_rhs_array_muxed28 + connect \builder_shared_we \builder_comb_rhs_array_muxed29 + connect \builder_shared_cti \builder_comb_rhs_array_muxed30 + connect \builder_shared_bte \builder_comb_rhs_array_muxed31 + connect \main_libresocsim_interface0_converted_interface_dat_r \builder_shared_dat_r + connect \main_libresocsim_interface1_converted_interface_dat_r \builder_shared_dat_r + connect \main_libresocsim_interface2_converted_interface_dat_r \builder_shared_dat_r + connect \main_interface0_bus_dat_r \builder_shared_dat_r + connect \main_interface1_bus_dat_r \builder_shared_dat_r + connect \main_libresocsim_interface0_converted_interface_ack $and$ls180.v:5644$1030_Y + connect \main_libresocsim_interface1_converted_interface_ack $and$ls180.v:5645$1032_Y + connect \main_libresocsim_interface2_converted_interface_ack $and$ls180.v:5646$1034_Y + connect \main_interface0_bus_ack $and$ls180.v:5647$1036_Y + connect \main_interface1_bus_ack $and$ls180.v:5648$1038_Y + connect \main_libresocsim_interface0_converted_interface_err $and$ls180.v:5649$1040_Y + connect \main_libresocsim_interface1_converted_interface_err $and$ls180.v:5650$1042_Y + connect \main_libresocsim_interface2_converted_interface_err $and$ls180.v:5651$1044_Y + connect \main_interface0_bus_err $and$ls180.v:5652$1046_Y + connect \main_interface1_bus_err $and$ls180.v:5653$1048_Y + connect \builder_request { \main_interface1_bus_cyc \main_interface0_bus_cyc \main_libresocsim_interface2_converted_interface_cyc \main_libresocsim_interface1_converted_interface_cyc \main_libresocsim_interface0_converted_interface_cyc } + connect \main_libresocsim_ram_bus_adr \builder_shared_adr + connect \main_libresocsim_ram_bus_dat_w \builder_shared_dat_w + connect \main_libresocsim_ram_bus_sel \builder_shared_sel + connect \main_libresocsim_ram_bus_stb \builder_shared_stb + connect \main_libresocsim_ram_bus_we \builder_shared_we + connect \main_libresocsim_ram_bus_cti \builder_shared_cti + connect \main_libresocsim_ram_bus_bte \builder_shared_bte + connect \main_libresocsim_libresoc_xics_icp_adr \builder_shared_adr + connect \main_libresocsim_libresoc_xics_icp_dat_w \builder_shared_dat_w + connect \main_libresocsim_libresoc_xics_icp_sel \builder_shared_sel + connect \main_libresocsim_libresoc_xics_icp_stb \builder_shared_stb + connect \main_libresocsim_libresoc_xics_icp_we \builder_shared_we + connect \main_libresocsim_libresoc_xics_icp_cti \builder_shared_cti + connect \main_libresocsim_libresoc_xics_icp_bte \builder_shared_bte + connect \main_libresocsim_libresoc_xics_ics_adr \builder_shared_adr + connect \main_libresocsim_libresoc_xics_ics_dat_w \builder_shared_dat_w + connect \main_libresocsim_libresoc_xics_ics_sel \builder_shared_sel + connect \main_libresocsim_libresoc_xics_ics_stb \builder_shared_stb + connect \main_libresocsim_libresoc_xics_ics_we \builder_shared_we + connect \main_libresocsim_libresoc_xics_ics_cti \builder_shared_cti + connect \main_libresocsim_libresoc_xics_ics_bte \builder_shared_bte + connect \main_wb_sdram_adr \builder_shared_adr + connect \main_wb_sdram_dat_w \builder_shared_dat_w + connect \main_wb_sdram_sel \builder_shared_sel + connect \main_wb_sdram_stb \builder_shared_stb + connect \main_wb_sdram_we \builder_shared_we + connect \main_wb_sdram_cti \builder_shared_cti + connect \main_wb_sdram_bte \builder_shared_bte + connect \builder_libresocsim_wishbone_adr \builder_shared_adr + connect \builder_libresocsim_wishbone_dat_w \builder_shared_dat_w + connect \builder_libresocsim_wishbone_sel \builder_shared_sel + connect \builder_libresocsim_wishbone_stb \builder_shared_stb + connect \builder_libresocsim_wishbone_we \builder_shared_we + connect \builder_libresocsim_wishbone_cti \builder_shared_cti + connect \builder_libresocsim_wishbone_bte \builder_shared_bte + connect \main_libresocsim_ram_bus_cyc $and$ls180.v:5698$1055_Y + connect \main_libresocsim_libresoc_xics_icp_cyc $and$ls180.v:5699$1056_Y + connect \main_libresocsim_libresoc_xics_ics_cyc $and$ls180.v:5700$1057_Y + connect \main_wb_sdram_cyc $and$ls180.v:5701$1058_Y + connect \builder_libresocsim_wishbone_cyc $and$ls180.v:5702$1059_Y + connect \builder_shared_err $or$ls180.v:5703$1063_Y + connect \builder_wait $and$ls180.v:5704$1066_Y + connect \builder_done $eq$ls180.v:5717$1081_Y + connect \builder_csrbank0_sel $eq$ls180.v:5718$1082_Y + connect \builder_csrbank0_reset0_r \builder_interface0_bank_bus_dat_w [0] + connect \builder_csrbank0_reset0_re $and$ls180.v:5720$1085_Y + connect \builder_csrbank0_reset0_we $and$ls180.v:5721$1089_Y + connect \builder_csrbank0_scratch3_r \builder_interface0_bank_bus_dat_w + connect \builder_csrbank0_scratch3_re $and$ls180.v:5723$1092_Y + connect \builder_csrbank0_scratch3_we $and$ls180.v:5724$1096_Y + connect \builder_csrbank0_scratch2_r \builder_interface0_bank_bus_dat_w + connect \builder_csrbank0_scratch2_re $and$ls180.v:5726$1099_Y + connect \builder_csrbank0_scratch2_we $and$ls180.v:5727$1103_Y + connect \builder_csrbank0_scratch1_r \builder_interface0_bank_bus_dat_w + connect \builder_csrbank0_scratch1_re $and$ls180.v:5729$1106_Y + connect \builder_csrbank0_scratch1_we $and$ls180.v:5730$1110_Y + connect \builder_csrbank0_scratch0_r \builder_interface0_bank_bus_dat_w + connect \builder_csrbank0_scratch0_re $and$ls180.v:5732$1113_Y + connect \builder_csrbank0_scratch0_we $and$ls180.v:5733$1117_Y + connect \builder_csrbank0_bus_errors3_r \builder_interface0_bank_bus_dat_w + connect \builder_csrbank0_bus_errors3_re $and$ls180.v:5735$1120_Y + connect \builder_csrbank0_bus_errors3_we $and$ls180.v:5736$1124_Y + connect \builder_csrbank0_bus_errors2_r \builder_interface0_bank_bus_dat_w + connect \builder_csrbank0_bus_errors2_re $and$ls180.v:5738$1127_Y + connect \builder_csrbank0_bus_errors2_we $and$ls180.v:5739$1131_Y + connect \builder_csrbank0_bus_errors1_r \builder_interface0_bank_bus_dat_w + connect \builder_csrbank0_bus_errors1_re $and$ls180.v:5741$1134_Y + connect \builder_csrbank0_bus_errors1_we $and$ls180.v:5742$1138_Y + connect \builder_csrbank0_bus_errors0_r \builder_interface0_bank_bus_dat_w + connect \builder_csrbank0_bus_errors0_re $and$ls180.v:5744$1141_Y + connect \builder_csrbank0_bus_errors0_we $and$ls180.v:5745$1145_Y + connect \builder_csrbank0_reset0_w \main_libresocsim_reset_storage + connect \builder_csrbank0_scratch3_w \main_libresocsim_scratch_storage [31:24] + connect \builder_csrbank0_scratch2_w \main_libresocsim_scratch_storage [23:16] + connect \builder_csrbank0_scratch1_w \main_libresocsim_scratch_storage [15:8] + connect \builder_csrbank0_scratch0_w \main_libresocsim_scratch_storage [7:0] + connect \builder_csrbank0_bus_errors3_w \main_libresocsim_bus_errors_status [31:24] + connect \builder_csrbank0_bus_errors2_w \main_libresocsim_bus_errors_status [23:16] + connect \builder_csrbank0_bus_errors1_w \main_libresocsim_bus_errors_status [15:8] + connect \builder_csrbank0_bus_errors0_w \main_libresocsim_bus_errors_status [7:0] + connect \main_libresocsim_bus_errors_we \builder_csrbank0_bus_errors0_we + connect \builder_csrbank1_sel $eq$ls180.v:5756$1146_Y + connect \builder_csrbank1_oe1_r \builder_interface1_bank_bus_dat_w + connect \builder_csrbank1_oe1_re $and$ls180.v:5758$1149_Y + connect \builder_csrbank1_oe1_we $and$ls180.v:5759$1153_Y + connect \builder_csrbank1_oe0_r \builder_interface1_bank_bus_dat_w + connect \builder_csrbank1_oe0_re $and$ls180.v:5761$1156_Y + connect \builder_csrbank1_oe0_we $and$ls180.v:5762$1160_Y + connect \builder_csrbank1_in1_r \builder_interface1_bank_bus_dat_w + connect \builder_csrbank1_in1_re $and$ls180.v:5764$1163_Y + connect \builder_csrbank1_in1_we $and$ls180.v:5765$1167_Y + connect \builder_csrbank1_in0_r \builder_interface1_bank_bus_dat_w + connect \builder_csrbank1_in0_re $and$ls180.v:5767$1170_Y + connect \builder_csrbank1_in0_we $and$ls180.v:5768$1174_Y + connect \builder_csrbank1_out1_r \builder_interface1_bank_bus_dat_w + connect \builder_csrbank1_out1_re $and$ls180.v:5770$1177_Y + connect \builder_csrbank1_out1_we $and$ls180.v:5771$1181_Y + connect \builder_csrbank1_out0_r \builder_interface1_bank_bus_dat_w + connect \builder_csrbank1_out0_re $and$ls180.v:5773$1184_Y + connect \builder_csrbank1_out0_we $and$ls180.v:5774$1188_Y + connect \builder_csrbank1_oe1_w \main_gpio_oe_storage [15:8] + connect \builder_csrbank1_oe0_w \main_gpio_oe_storage [7:0] + connect \builder_csrbank1_in1_w \main_gpio_status [15:8] + connect \builder_csrbank1_in0_w \main_gpio_status [7:0] + connect \main_gpio_we \builder_csrbank1_in0_we + connect \builder_csrbank1_out1_w \main_gpio_out_storage [15:8] + connect \builder_csrbank1_out0_w \main_gpio_out_storage [7:0] + connect \builder_csrbank2_sel $eq$ls180.v:5782$1189_Y + connect \builder_csrbank2_enable0_r \builder_interface2_bank_bus_dat_w [0] + connect \builder_csrbank2_enable0_re $and$ls180.v:5784$1192_Y + connect \builder_csrbank2_enable0_we $and$ls180.v:5785$1196_Y + connect \builder_csrbank2_width3_r \builder_interface2_bank_bus_dat_w + connect \builder_csrbank2_width3_re $and$ls180.v:5787$1199_Y + connect \builder_csrbank2_width3_we $and$ls180.v:5788$1203_Y + connect \builder_csrbank2_width2_r \builder_interface2_bank_bus_dat_w + connect \builder_csrbank2_width2_re $and$ls180.v:5790$1206_Y + connect \builder_csrbank2_width2_we $and$ls180.v:5791$1210_Y + connect \builder_csrbank2_width1_r \builder_interface2_bank_bus_dat_w + connect \builder_csrbank2_width1_re $and$ls180.v:5793$1213_Y + connect \builder_csrbank2_width1_we $and$ls180.v:5794$1217_Y + connect \builder_csrbank2_width0_r \builder_interface2_bank_bus_dat_w + connect \builder_csrbank2_width0_re $and$ls180.v:5796$1220_Y + connect \builder_csrbank2_width0_we $and$ls180.v:5797$1224_Y + connect \builder_csrbank2_period3_r \builder_interface2_bank_bus_dat_w + connect \builder_csrbank2_period3_re $and$ls180.v:5799$1227_Y + connect \builder_csrbank2_period3_we $and$ls180.v:5800$1231_Y + connect \builder_csrbank2_period2_r \builder_interface2_bank_bus_dat_w + connect \builder_csrbank2_period2_re $and$ls180.v:5802$1234_Y + connect \builder_csrbank2_period2_we $and$ls180.v:5803$1238_Y + connect \builder_csrbank2_period1_r \builder_interface2_bank_bus_dat_w + connect \builder_csrbank2_period1_re $and$ls180.v:5805$1241_Y + connect \builder_csrbank2_period1_we $and$ls180.v:5806$1245_Y + connect \builder_csrbank2_period0_r \builder_interface2_bank_bus_dat_w + connect \builder_csrbank2_period0_re $and$ls180.v:5808$1248_Y + connect \builder_csrbank2_period0_we $and$ls180.v:5809$1252_Y + connect \builder_csrbank2_enable0_w \main_pwm0_enable_storage + connect \builder_csrbank2_width3_w \main_pwm0_width_storage [31:24] + connect \builder_csrbank2_width2_w \main_pwm0_width_storage [23:16] + connect \builder_csrbank2_width1_w \main_pwm0_width_storage [15:8] + connect \builder_csrbank2_width0_w \main_pwm0_width_storage [7:0] + connect \builder_csrbank2_period3_w \main_pwm0_period_storage [31:24] + connect \builder_csrbank2_period2_w \main_pwm0_period_storage [23:16] + connect \builder_csrbank2_period1_w \main_pwm0_period_storage [15:8] + connect \builder_csrbank2_period0_w \main_pwm0_period_storage [7:0] + connect \builder_csrbank3_sel $eq$ls180.v:5819$1253_Y + connect \builder_csrbank3_enable0_r \builder_interface3_bank_bus_dat_w [0] + connect \builder_csrbank3_enable0_re $and$ls180.v:5821$1256_Y + connect \builder_csrbank3_enable0_we $and$ls180.v:5822$1260_Y + connect \builder_csrbank3_width3_r \builder_interface3_bank_bus_dat_w + connect \builder_csrbank3_width3_re $and$ls180.v:5824$1263_Y + connect \builder_csrbank3_width3_we $and$ls180.v:5825$1267_Y + connect \builder_csrbank3_width2_r \builder_interface3_bank_bus_dat_w + connect \builder_csrbank3_width2_re $and$ls180.v:5827$1270_Y + connect \builder_csrbank3_width2_we $and$ls180.v:5828$1274_Y + connect \builder_csrbank3_width1_r \builder_interface3_bank_bus_dat_w + connect \builder_csrbank3_width1_re $and$ls180.v:5830$1277_Y + connect \builder_csrbank3_width1_we $and$ls180.v:5831$1281_Y + connect \builder_csrbank3_width0_r \builder_interface3_bank_bus_dat_w + connect \builder_csrbank3_width0_re $and$ls180.v:5833$1284_Y + connect \builder_csrbank3_width0_we $and$ls180.v:5834$1288_Y + connect \builder_csrbank3_period3_r \builder_interface3_bank_bus_dat_w + connect \builder_csrbank3_period3_re $and$ls180.v:5836$1291_Y + connect \builder_csrbank3_period3_we $and$ls180.v:5837$1295_Y + connect \builder_csrbank3_period2_r \builder_interface3_bank_bus_dat_w + connect \builder_csrbank3_period2_re $and$ls180.v:5839$1298_Y + connect \builder_csrbank3_period2_we $and$ls180.v:5840$1302_Y + connect \builder_csrbank3_period1_r \builder_interface3_bank_bus_dat_w + connect \builder_csrbank3_period1_re $and$ls180.v:5842$1305_Y + connect \builder_csrbank3_period1_we $and$ls180.v:5843$1309_Y + connect \builder_csrbank3_period0_r \builder_interface3_bank_bus_dat_w + connect \builder_csrbank3_period0_re $and$ls180.v:5845$1312_Y + connect \builder_csrbank3_period0_we $and$ls180.v:5846$1316_Y + connect \builder_csrbank3_enable0_w \main_pwm1_enable_storage + connect \builder_csrbank3_width3_w \main_pwm1_width_storage [31:24] + connect \builder_csrbank3_width2_w \main_pwm1_width_storage [23:16] + connect \builder_csrbank3_width1_w \main_pwm1_width_storage [15:8] + connect \builder_csrbank3_width0_w \main_pwm1_width_storage [7:0] + connect \builder_csrbank3_period3_w \main_pwm1_period_storage [31:24] + connect \builder_csrbank3_period2_w \main_pwm1_period_storage [23:16] + connect \builder_csrbank3_period1_w \main_pwm1_period_storage [15:8] + connect \builder_csrbank3_period0_w \main_pwm1_period_storage [7:0] + connect \builder_csrbank4_sel $eq$ls180.v:5856$1317_Y + connect \builder_csrbank4_dma_base7_r \builder_interface4_bank_bus_dat_w + connect \builder_csrbank4_dma_base7_re $and$ls180.v:5858$1320_Y + connect \builder_csrbank4_dma_base7_we $and$ls180.v:5859$1324_Y + connect \builder_csrbank4_dma_base6_r \builder_interface4_bank_bus_dat_w + connect \builder_csrbank4_dma_base6_re $and$ls180.v:5861$1327_Y + connect \builder_csrbank4_dma_base6_we $and$ls180.v:5862$1331_Y + connect \builder_csrbank4_dma_base5_r \builder_interface4_bank_bus_dat_w + connect \builder_csrbank4_dma_base5_re $and$ls180.v:5864$1334_Y + connect \builder_csrbank4_dma_base5_we $and$ls180.v:5865$1338_Y + connect \builder_csrbank4_dma_base4_r \builder_interface4_bank_bus_dat_w + connect \builder_csrbank4_dma_base4_re $and$ls180.v:5867$1341_Y + connect \builder_csrbank4_dma_base4_we $and$ls180.v:5868$1345_Y + connect \builder_csrbank4_dma_base3_r \builder_interface4_bank_bus_dat_w + connect \builder_csrbank4_dma_base3_re $and$ls180.v:5870$1348_Y + connect \builder_csrbank4_dma_base3_we $and$ls180.v:5871$1352_Y + connect \builder_csrbank4_dma_base2_r \builder_interface4_bank_bus_dat_w + connect \builder_csrbank4_dma_base2_re $and$ls180.v:5873$1355_Y + connect \builder_csrbank4_dma_base2_we $and$ls180.v:5874$1359_Y + connect \builder_csrbank4_dma_base1_r \builder_interface4_bank_bus_dat_w + connect \builder_csrbank4_dma_base1_re $and$ls180.v:5876$1362_Y + connect \builder_csrbank4_dma_base1_we $and$ls180.v:5877$1366_Y + connect \builder_csrbank4_dma_base0_r \builder_interface4_bank_bus_dat_w + connect \builder_csrbank4_dma_base0_re $and$ls180.v:5879$1369_Y + connect \builder_csrbank4_dma_base0_we $and$ls180.v:5880$1373_Y + connect \builder_csrbank4_dma_length3_r \builder_interface4_bank_bus_dat_w + connect \builder_csrbank4_dma_length3_re $and$ls180.v:5882$1376_Y + connect \builder_csrbank4_dma_length3_we $and$ls180.v:5883$1380_Y + connect \builder_csrbank4_dma_length2_r \builder_interface4_bank_bus_dat_w + connect \builder_csrbank4_dma_length2_re $and$ls180.v:5885$1383_Y + connect \builder_csrbank4_dma_length2_we $and$ls180.v:5886$1387_Y + connect \builder_csrbank4_dma_length1_r \builder_interface4_bank_bus_dat_w + connect \builder_csrbank4_dma_length1_re $and$ls180.v:5888$1390_Y + connect \builder_csrbank4_dma_length1_we $and$ls180.v:5889$1394_Y + connect \builder_csrbank4_dma_length0_r \builder_interface4_bank_bus_dat_w + connect \builder_csrbank4_dma_length0_re $and$ls180.v:5891$1397_Y + connect \builder_csrbank4_dma_length0_we $and$ls180.v:5892$1401_Y + connect \builder_csrbank4_dma_enable0_r \builder_interface4_bank_bus_dat_w [0] + connect \builder_csrbank4_dma_enable0_re $and$ls180.v:5894$1404_Y + connect \builder_csrbank4_dma_enable0_we $and$ls180.v:5895$1408_Y + connect \builder_csrbank4_dma_done_r \builder_interface4_bank_bus_dat_w [0] + connect \builder_csrbank4_dma_done_re $and$ls180.v:5897$1411_Y + connect \builder_csrbank4_dma_done_we $and$ls180.v:5898$1415_Y + connect \builder_csrbank4_dma_loop0_r \builder_interface4_bank_bus_dat_w [0] + connect \builder_csrbank4_dma_loop0_re $and$ls180.v:5900$1418_Y + connect \builder_csrbank4_dma_loop0_we $and$ls180.v:5901$1422_Y + connect \builder_csrbank4_dma_base7_w \main_sdblock2mem_wishbonedmawriter_base_storage [63:56] + connect \builder_csrbank4_dma_base6_w \main_sdblock2mem_wishbonedmawriter_base_storage [55:48] + connect \builder_csrbank4_dma_base5_w \main_sdblock2mem_wishbonedmawriter_base_storage [47:40] + connect \builder_csrbank4_dma_base4_w \main_sdblock2mem_wishbonedmawriter_base_storage [39:32] + connect \builder_csrbank4_dma_base3_w \main_sdblock2mem_wishbonedmawriter_base_storage [31:24] + connect \builder_csrbank4_dma_base2_w \main_sdblock2mem_wishbonedmawriter_base_storage [23:16] + connect \builder_csrbank4_dma_base1_w \main_sdblock2mem_wishbonedmawriter_base_storage [15:8] + connect \builder_csrbank4_dma_base0_w \main_sdblock2mem_wishbonedmawriter_base_storage [7:0] + connect \builder_csrbank4_dma_length3_w \main_sdblock2mem_wishbonedmawriter_length_storage [31:24] + connect \builder_csrbank4_dma_length2_w \main_sdblock2mem_wishbonedmawriter_length_storage [23:16] + connect \builder_csrbank4_dma_length1_w \main_sdblock2mem_wishbonedmawriter_length_storage [15:8] + connect \builder_csrbank4_dma_length0_w \main_sdblock2mem_wishbonedmawriter_length_storage [7:0] + connect \builder_csrbank4_dma_enable0_w \main_sdblock2mem_wishbonedmawriter_enable_storage + connect \builder_csrbank4_dma_done_w \main_sdblock2mem_wishbonedmawriter_status + connect \main_sdblock2mem_wishbonedmawriter_we \builder_csrbank4_dma_done_we + connect \builder_csrbank4_dma_loop0_w \main_sdblock2mem_wishbonedmawriter_loop_storage + connect \builder_csrbank5_sel $eq$ls180.v:5918$1423_Y + connect \builder_csrbank5_cmd_argument3_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_cmd_argument3_re $and$ls180.v:5920$1426_Y + connect \builder_csrbank5_cmd_argument3_we $and$ls180.v:5921$1430_Y + connect \builder_csrbank5_cmd_argument2_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_cmd_argument2_re $and$ls180.v:5923$1433_Y + connect \builder_csrbank5_cmd_argument2_we $and$ls180.v:5924$1437_Y + connect \builder_csrbank5_cmd_argument1_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_cmd_argument1_re $and$ls180.v:5926$1440_Y + connect \builder_csrbank5_cmd_argument1_we $and$ls180.v:5927$1444_Y + connect \builder_csrbank5_cmd_argument0_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_cmd_argument0_re $and$ls180.v:5929$1447_Y + connect \builder_csrbank5_cmd_argument0_we $and$ls180.v:5930$1451_Y + connect \builder_csrbank5_cmd_command3_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_cmd_command3_re $and$ls180.v:5932$1454_Y + connect \builder_csrbank5_cmd_command3_we $and$ls180.v:5933$1458_Y + connect \builder_csrbank5_cmd_command2_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_cmd_command2_re $and$ls180.v:5935$1461_Y + connect \builder_csrbank5_cmd_command2_we $and$ls180.v:5936$1465_Y + connect \builder_csrbank5_cmd_command1_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_cmd_command1_re $and$ls180.v:5938$1468_Y + connect \builder_csrbank5_cmd_command1_we $and$ls180.v:5939$1472_Y + connect \builder_csrbank5_cmd_command0_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_cmd_command0_re $and$ls180.v:5941$1475_Y + connect \builder_csrbank5_cmd_command0_we $and$ls180.v:5942$1479_Y + connect \main_sdcore_cmd_send_r \builder_interface5_bank_bus_dat_w [0] + connect \main_sdcore_cmd_send_re $and$ls180.v:5944$1482_Y + connect \main_sdcore_cmd_send_we $and$ls180.v:5945$1486_Y + connect \builder_csrbank5_cmd_response15_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_cmd_response15_re $and$ls180.v:5947$1489_Y + connect \builder_csrbank5_cmd_response15_we $and$ls180.v:5948$1493_Y + connect \builder_csrbank5_cmd_response14_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_cmd_response14_re $and$ls180.v:5950$1496_Y + connect \builder_csrbank5_cmd_response14_we $and$ls180.v:5951$1500_Y + connect \builder_csrbank5_cmd_response13_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_cmd_response13_re $and$ls180.v:5953$1503_Y + connect \builder_csrbank5_cmd_response13_we $and$ls180.v:5954$1507_Y + connect \builder_csrbank5_cmd_response12_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_cmd_response12_re $and$ls180.v:5956$1510_Y + connect \builder_csrbank5_cmd_response12_we $and$ls180.v:5957$1514_Y + connect \builder_csrbank5_cmd_response11_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_cmd_response11_re $and$ls180.v:5959$1517_Y + connect \builder_csrbank5_cmd_response11_we $and$ls180.v:5960$1521_Y + connect \builder_csrbank5_cmd_response10_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_cmd_response10_re $and$ls180.v:5962$1524_Y + connect \builder_csrbank5_cmd_response10_we $and$ls180.v:5963$1528_Y + connect \builder_csrbank5_cmd_response9_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_cmd_response9_re $and$ls180.v:5965$1531_Y + connect \builder_csrbank5_cmd_response9_we $and$ls180.v:5966$1535_Y + connect \builder_csrbank5_cmd_response8_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_cmd_response8_re $and$ls180.v:5968$1538_Y + connect \builder_csrbank5_cmd_response8_we $and$ls180.v:5969$1542_Y + connect \builder_csrbank5_cmd_response7_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_cmd_response7_re $and$ls180.v:5971$1545_Y + connect \builder_csrbank5_cmd_response7_we $and$ls180.v:5972$1549_Y + connect \builder_csrbank5_cmd_response6_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_cmd_response6_re $and$ls180.v:5974$1552_Y + connect \builder_csrbank5_cmd_response6_we $and$ls180.v:5975$1556_Y + connect \builder_csrbank5_cmd_response5_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_cmd_response5_re $and$ls180.v:5977$1559_Y + connect \builder_csrbank5_cmd_response5_we $and$ls180.v:5978$1563_Y + connect \builder_csrbank5_cmd_response4_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_cmd_response4_re $and$ls180.v:5980$1566_Y + connect \builder_csrbank5_cmd_response4_we $and$ls180.v:5981$1570_Y + connect \builder_csrbank5_cmd_response3_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_cmd_response3_re $and$ls180.v:5983$1573_Y + connect \builder_csrbank5_cmd_response3_we $and$ls180.v:5984$1577_Y + connect \builder_csrbank5_cmd_response2_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_cmd_response2_re $and$ls180.v:5986$1580_Y + connect \builder_csrbank5_cmd_response2_we $and$ls180.v:5987$1584_Y + connect \builder_csrbank5_cmd_response1_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_cmd_response1_re $and$ls180.v:5989$1587_Y + connect \builder_csrbank5_cmd_response1_we $and$ls180.v:5990$1591_Y + connect \builder_csrbank5_cmd_response0_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_cmd_response0_re $and$ls180.v:5992$1594_Y + connect \builder_csrbank5_cmd_response0_we $and$ls180.v:5993$1598_Y + connect \builder_csrbank5_cmd_event_r \builder_interface5_bank_bus_dat_w [3:0] + connect \builder_csrbank5_cmd_event_re $and$ls180.v:5995$1601_Y + connect \builder_csrbank5_cmd_event_we $and$ls180.v:5996$1605_Y + connect \builder_csrbank5_data_event_r \builder_interface5_bank_bus_dat_w [3:0] + connect \builder_csrbank5_data_event_re $and$ls180.v:5998$1608_Y + connect \builder_csrbank5_data_event_we $and$ls180.v:5999$1612_Y + connect \builder_csrbank5_block_length1_r \builder_interface5_bank_bus_dat_w [1:0] + connect \builder_csrbank5_block_length1_re $and$ls180.v:6001$1615_Y + connect \builder_csrbank5_block_length1_we $and$ls180.v:6002$1619_Y + connect \builder_csrbank5_block_length0_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_block_length0_re $and$ls180.v:6004$1622_Y + connect \builder_csrbank5_block_length0_we $and$ls180.v:6005$1626_Y + connect \builder_csrbank5_block_count3_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_block_count3_re $and$ls180.v:6007$1629_Y + connect \builder_csrbank5_block_count3_we $and$ls180.v:6008$1633_Y + connect \builder_csrbank5_block_count2_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_block_count2_re $and$ls180.v:6010$1636_Y + connect \builder_csrbank5_block_count2_we $and$ls180.v:6011$1640_Y + connect \builder_csrbank5_block_count1_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_block_count1_re $and$ls180.v:6013$1643_Y + connect \builder_csrbank5_block_count1_we $and$ls180.v:6014$1647_Y + connect \builder_csrbank5_block_count0_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_block_count0_re $and$ls180.v:6016$1650_Y + connect \builder_csrbank5_block_count0_we $and$ls180.v:6017$1654_Y + connect \builder_csrbank5_cmd_argument3_w \main_sdcore_cmd_argument_storage [31:24] + connect \builder_csrbank5_cmd_argument2_w \main_sdcore_cmd_argument_storage [23:16] + connect \builder_csrbank5_cmd_argument1_w \main_sdcore_cmd_argument_storage [15:8] + connect \builder_csrbank5_cmd_argument0_w \main_sdcore_cmd_argument_storage [7:0] + connect \builder_csrbank5_cmd_command3_w \main_sdcore_cmd_command_storage [31:24] + connect \builder_csrbank5_cmd_command2_w \main_sdcore_cmd_command_storage [23:16] + connect \builder_csrbank5_cmd_command1_w \main_sdcore_cmd_command_storage [15:8] + connect \builder_csrbank5_cmd_command0_w \main_sdcore_cmd_command_storage [7:0] + connect \builder_csrbank5_cmd_response15_w \main_sdcore_cmd_response_status [127:120] + connect \builder_csrbank5_cmd_response14_w \main_sdcore_cmd_response_status [119:112] + connect \builder_csrbank5_cmd_response13_w \main_sdcore_cmd_response_status [111:104] + connect \builder_csrbank5_cmd_response12_w \main_sdcore_cmd_response_status [103:96] + connect \builder_csrbank5_cmd_response11_w \main_sdcore_cmd_response_status [95:88] + connect \builder_csrbank5_cmd_response10_w \main_sdcore_cmd_response_status [87:80] + connect \builder_csrbank5_cmd_response9_w \main_sdcore_cmd_response_status [79:72] + connect \builder_csrbank5_cmd_response8_w \main_sdcore_cmd_response_status [71:64] + connect \builder_csrbank5_cmd_response7_w \main_sdcore_cmd_response_status [63:56] + connect \builder_csrbank5_cmd_response6_w \main_sdcore_cmd_response_status [55:48] + connect \builder_csrbank5_cmd_response5_w \main_sdcore_cmd_response_status [47:40] + connect \builder_csrbank5_cmd_response4_w \main_sdcore_cmd_response_status [39:32] + connect \builder_csrbank5_cmd_response3_w \main_sdcore_cmd_response_status [31:24] + connect \builder_csrbank5_cmd_response2_w \main_sdcore_cmd_response_status [23:16] + connect \builder_csrbank5_cmd_response1_w \main_sdcore_cmd_response_status [15:8] + connect \builder_csrbank5_cmd_response0_w \main_sdcore_cmd_response_status [7:0] + connect \main_sdcore_cmd_response_we \builder_csrbank5_cmd_response0_we + connect \builder_csrbank5_cmd_event_w \main_sdcore_cmd_event_status + connect \main_sdcore_cmd_event_we \builder_csrbank5_cmd_event_we + connect \builder_csrbank5_data_event_w \main_sdcore_data_event_status + connect \main_sdcore_data_event_we \builder_csrbank5_data_event_we + connect \builder_csrbank5_block_length1_w \main_sdcore_block_length_storage [9:8] + connect \builder_csrbank5_block_length0_w \main_sdcore_block_length_storage [7:0] + connect \builder_csrbank5_block_count3_w \main_sdcore_block_count_storage [31:24] + connect \builder_csrbank5_block_count2_w \main_sdcore_block_count_storage [23:16] + connect \builder_csrbank5_block_count1_w \main_sdcore_block_count_storage [15:8] + connect \builder_csrbank5_block_count0_w \main_sdcore_block_count_storage [7:0] + connect \builder_csrbank6_sel $eq$ls180.v:6053$1655_Y + connect \builder_csrbank6_dma_base7_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_dma_base7_re $and$ls180.v:6055$1658_Y + connect \builder_csrbank6_dma_base7_we $and$ls180.v:6056$1662_Y + connect \builder_csrbank6_dma_base6_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_dma_base6_re $and$ls180.v:6058$1665_Y + connect \builder_csrbank6_dma_base6_we $and$ls180.v:6059$1669_Y + connect \builder_csrbank6_dma_base5_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_dma_base5_re $and$ls180.v:6061$1672_Y + connect \builder_csrbank6_dma_base5_we $and$ls180.v:6062$1676_Y + connect \builder_csrbank6_dma_base4_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_dma_base4_re $and$ls180.v:6064$1679_Y + connect \builder_csrbank6_dma_base4_we $and$ls180.v:6065$1683_Y + connect \builder_csrbank6_dma_base3_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_dma_base3_re $and$ls180.v:6067$1686_Y + connect \builder_csrbank6_dma_base3_we $and$ls180.v:6068$1690_Y + connect \builder_csrbank6_dma_base2_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_dma_base2_re $and$ls180.v:6070$1693_Y + connect \builder_csrbank6_dma_base2_we $and$ls180.v:6071$1697_Y + connect \builder_csrbank6_dma_base1_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_dma_base1_re $and$ls180.v:6073$1700_Y + connect \builder_csrbank6_dma_base1_we $and$ls180.v:6074$1704_Y + connect \builder_csrbank6_dma_base0_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_dma_base0_re $and$ls180.v:6076$1707_Y + connect \builder_csrbank6_dma_base0_we $and$ls180.v:6077$1711_Y + connect \builder_csrbank6_dma_length3_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_dma_length3_re $and$ls180.v:6079$1714_Y + connect \builder_csrbank6_dma_length3_we $and$ls180.v:6080$1718_Y + connect \builder_csrbank6_dma_length2_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_dma_length2_re $and$ls180.v:6082$1721_Y + connect \builder_csrbank6_dma_length2_we $and$ls180.v:6083$1725_Y + connect \builder_csrbank6_dma_length1_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_dma_length1_re $and$ls180.v:6085$1728_Y + connect \builder_csrbank6_dma_length1_we $and$ls180.v:6086$1732_Y + connect \builder_csrbank6_dma_length0_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_dma_length0_re $and$ls180.v:6088$1735_Y + connect \builder_csrbank6_dma_length0_we $and$ls180.v:6089$1739_Y + connect \builder_csrbank6_dma_enable0_r \builder_interface6_bank_bus_dat_w [0] + connect \builder_csrbank6_dma_enable0_re $and$ls180.v:6091$1742_Y + connect \builder_csrbank6_dma_enable0_we $and$ls180.v:6092$1746_Y + connect \builder_csrbank6_dma_done_r \builder_interface6_bank_bus_dat_w [0] + connect \builder_csrbank6_dma_done_re $and$ls180.v:6094$1749_Y + connect \builder_csrbank6_dma_done_we $and$ls180.v:6095$1753_Y + connect \builder_csrbank6_dma_loop0_r \builder_interface6_bank_bus_dat_w [0] + connect \builder_csrbank6_dma_loop0_re $and$ls180.v:6097$1756_Y + connect \builder_csrbank6_dma_loop0_we $and$ls180.v:6098$1760_Y + connect \builder_csrbank6_dma_offset3_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_dma_offset3_re $and$ls180.v:6100$1763_Y + connect \builder_csrbank6_dma_offset3_we $and$ls180.v:6101$1767_Y + connect \builder_csrbank6_dma_offset2_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_dma_offset2_re $and$ls180.v:6103$1770_Y + connect \builder_csrbank6_dma_offset2_we $and$ls180.v:6104$1774_Y + connect \builder_csrbank6_dma_offset1_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_dma_offset1_re $and$ls180.v:6106$1777_Y + connect \builder_csrbank6_dma_offset1_we $and$ls180.v:6107$1781_Y + connect \builder_csrbank6_dma_offset0_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_dma_offset0_re $and$ls180.v:6109$1784_Y + connect \builder_csrbank6_dma_offset0_we $and$ls180.v:6110$1788_Y + connect \builder_csrbank6_dma_base7_w \main_sdmem2block_dma_base_storage [63:56] + connect \builder_csrbank6_dma_base6_w \main_sdmem2block_dma_base_storage [55:48] + connect \builder_csrbank6_dma_base5_w \main_sdmem2block_dma_base_storage [47:40] + connect \builder_csrbank6_dma_base4_w \main_sdmem2block_dma_base_storage [39:32] + connect \builder_csrbank6_dma_base3_w \main_sdmem2block_dma_base_storage [31:24] + connect \builder_csrbank6_dma_base2_w \main_sdmem2block_dma_base_storage [23:16] + connect \builder_csrbank6_dma_base1_w \main_sdmem2block_dma_base_storage [15:8] + connect \builder_csrbank6_dma_base0_w \main_sdmem2block_dma_base_storage [7:0] + connect \builder_csrbank6_dma_length3_w \main_sdmem2block_dma_length_storage [31:24] + connect \builder_csrbank6_dma_length2_w \main_sdmem2block_dma_length_storage [23:16] + connect \builder_csrbank6_dma_length1_w \main_sdmem2block_dma_length_storage [15:8] + connect \builder_csrbank6_dma_length0_w \main_sdmem2block_dma_length_storage [7:0] + connect \builder_csrbank6_dma_enable0_w \main_sdmem2block_dma_enable_storage + connect \builder_csrbank6_dma_done_w \main_sdmem2block_dma_done_status + connect \main_sdmem2block_dma_done_we \builder_csrbank6_dma_done_we + connect \builder_csrbank6_dma_loop0_w \main_sdmem2block_dma_loop_storage + connect \builder_csrbank6_dma_offset3_w \main_sdmem2block_dma_offset_status [31:24] + connect \builder_csrbank6_dma_offset2_w \main_sdmem2block_dma_offset_status [23:16] + connect \builder_csrbank6_dma_offset1_w \main_sdmem2block_dma_offset_status [15:8] + connect \builder_csrbank6_dma_offset0_w \main_sdmem2block_dma_offset_status [7:0] + connect \main_sdmem2block_dma_offset_we \builder_csrbank6_dma_offset0_we + connect \builder_csrbank7_sel $eq$ls180.v:6132$1789_Y + connect \builder_csrbank7_card_detect_r \builder_interface7_bank_bus_dat_w [0] + connect \builder_csrbank7_card_detect_re $and$ls180.v:6134$1792_Y + connect \builder_csrbank7_card_detect_we $and$ls180.v:6135$1796_Y + connect \builder_csrbank7_clocker_divider1_r \builder_interface7_bank_bus_dat_w [0] + connect \builder_csrbank7_clocker_divider1_re $and$ls180.v:6137$1799_Y + connect \builder_csrbank7_clocker_divider1_we $and$ls180.v:6138$1803_Y + connect \builder_csrbank7_clocker_divider0_r \builder_interface7_bank_bus_dat_w + connect \builder_csrbank7_clocker_divider0_re $and$ls180.v:6140$1806_Y + connect \builder_csrbank7_clocker_divider0_we $and$ls180.v:6141$1810_Y + connect \main_sdphy_init_initialize_r \builder_interface7_bank_bus_dat_w [0] + connect \main_sdphy_init_initialize_re $and$ls180.v:6143$1813_Y + connect \main_sdphy_init_initialize_we $and$ls180.v:6144$1817_Y + connect \builder_csrbank7_card_detect_w \main_sdphy_status + connect \main_sdphy_we \builder_csrbank7_card_detect_we + connect \builder_csrbank7_clocker_divider1_w \main_sdphy_clocker_storage [8] + connect \builder_csrbank7_clocker_divider0_w \main_sdphy_clocker_storage [7:0] + connect \builder_csrbank8_sel $eq$ls180.v:6149$1818_Y + connect \builder_csrbank8_dfii_control0_r \builder_interface8_bank_bus_dat_w [3:0] + connect \builder_csrbank8_dfii_control0_re $and$ls180.v:6151$1821_Y + connect \builder_csrbank8_dfii_control0_we $and$ls180.v:6152$1825_Y + connect \builder_csrbank8_dfii_pi0_command0_r \builder_interface8_bank_bus_dat_w [5:0] + connect \builder_csrbank8_dfii_pi0_command0_re $and$ls180.v:6154$1828_Y + connect \builder_csrbank8_dfii_pi0_command0_we $and$ls180.v:6155$1832_Y + connect \main_sdram_command_issue_r \builder_interface8_bank_bus_dat_w [0] + connect \main_sdram_command_issue_re $and$ls180.v:6157$1835_Y + connect \main_sdram_command_issue_we $and$ls180.v:6158$1839_Y + connect \builder_csrbank8_dfii_pi0_address1_r \builder_interface8_bank_bus_dat_w [4:0] + connect \builder_csrbank8_dfii_pi0_address1_re $and$ls180.v:6160$1842_Y + connect \builder_csrbank8_dfii_pi0_address1_we $and$ls180.v:6161$1846_Y + connect \builder_csrbank8_dfii_pi0_address0_r \builder_interface8_bank_bus_dat_w + connect \builder_csrbank8_dfii_pi0_address0_re $and$ls180.v:6163$1849_Y + connect \builder_csrbank8_dfii_pi0_address0_we $and$ls180.v:6164$1853_Y + connect \builder_csrbank8_dfii_pi0_baddress0_r \builder_interface8_bank_bus_dat_w [1:0] + connect \builder_csrbank8_dfii_pi0_baddress0_re $and$ls180.v:6166$1856_Y + connect \builder_csrbank8_dfii_pi0_baddress0_we $and$ls180.v:6167$1860_Y + connect \builder_csrbank8_dfii_pi0_wrdata1_r \builder_interface8_bank_bus_dat_w + connect \builder_csrbank8_dfii_pi0_wrdata1_re $and$ls180.v:6169$1863_Y + connect \builder_csrbank8_dfii_pi0_wrdata1_we $and$ls180.v:6170$1867_Y + connect \builder_csrbank8_dfii_pi0_wrdata0_r \builder_interface8_bank_bus_dat_w + connect \builder_csrbank8_dfii_pi0_wrdata0_re $and$ls180.v:6172$1870_Y + connect \builder_csrbank8_dfii_pi0_wrdata0_we $and$ls180.v:6173$1874_Y + connect \builder_csrbank8_dfii_pi0_rddata1_r \builder_interface8_bank_bus_dat_w + connect \builder_csrbank8_dfii_pi0_rddata1_re $and$ls180.v:6175$1877_Y + connect \builder_csrbank8_dfii_pi0_rddata1_we $and$ls180.v:6176$1881_Y + connect \builder_csrbank8_dfii_pi0_rddata0_r \builder_interface8_bank_bus_dat_w + connect \builder_csrbank8_dfii_pi0_rddata0_re $and$ls180.v:6178$1884_Y + connect \builder_csrbank8_dfii_pi0_rddata0_we $and$ls180.v:6179$1888_Y + connect \main_sdram_sel \main_sdram_storage [0] + connect \main_sdram_cke \main_sdram_storage [1] + connect \main_sdram_odt \main_sdram_storage [2] + connect \main_sdram_reset_n \main_sdram_storage [3] + connect \builder_csrbank8_dfii_control0_w \main_sdram_storage + connect \builder_csrbank8_dfii_pi0_command0_w \main_sdram_command_storage + connect \builder_csrbank8_dfii_pi0_address1_w \main_sdram_address_storage [12:8] + connect \builder_csrbank8_dfii_pi0_address0_w \main_sdram_address_storage [7:0] + connect \builder_csrbank8_dfii_pi0_baddress0_w \main_sdram_baddress_storage + connect \builder_csrbank8_dfii_pi0_wrdata1_w \main_sdram_wrdata_storage [15:8] + connect \builder_csrbank8_dfii_pi0_wrdata0_w \main_sdram_wrdata_storage [7:0] + connect \builder_csrbank8_dfii_pi0_rddata1_w \main_sdram_status [15:8] + connect \builder_csrbank8_dfii_pi0_rddata0_w \main_sdram_status [7:0] + connect \main_sdram_we \builder_csrbank8_dfii_pi0_rddata0_we + connect \builder_csrbank9_sel $eq$ls180.v:6194$1889_Y + connect \builder_csrbank9_control1_r \builder_interface9_bank_bus_dat_w + connect \builder_csrbank9_control1_re $and$ls180.v:6196$1892_Y + connect \builder_csrbank9_control1_we $and$ls180.v:6197$1896_Y + connect \builder_csrbank9_control0_r \builder_interface9_bank_bus_dat_w + connect \builder_csrbank9_control0_re $and$ls180.v:6199$1899_Y + connect \builder_csrbank9_control0_we $and$ls180.v:6200$1903_Y + connect \builder_csrbank9_status_r \builder_interface9_bank_bus_dat_w [0] + connect \builder_csrbank9_status_re $and$ls180.v:6202$1906_Y + connect \builder_csrbank9_status_we $and$ls180.v:6203$1910_Y + connect \builder_csrbank9_mosi0_r \builder_interface9_bank_bus_dat_w + connect \builder_csrbank9_mosi0_re $and$ls180.v:6205$1913_Y + connect \builder_csrbank9_mosi0_we $and$ls180.v:6206$1917_Y + connect \builder_csrbank9_miso_r \builder_interface9_bank_bus_dat_w + connect \builder_csrbank9_miso_re $and$ls180.v:6208$1920_Y + connect \builder_csrbank9_miso_we $and$ls180.v:6209$1924_Y + connect \builder_csrbank9_cs0_r \builder_interface9_bank_bus_dat_w [0] + connect \builder_csrbank9_cs0_re $and$ls180.v:6211$1927_Y + connect \builder_csrbank9_cs0_we $and$ls180.v:6212$1931_Y + connect \builder_csrbank9_loopback0_r \builder_interface9_bank_bus_dat_w [0] + connect \builder_csrbank9_loopback0_re $and$ls180.v:6214$1934_Y + connect \builder_csrbank9_loopback0_we $and$ls180.v:6215$1938_Y + connect \main_spi_master_length1 \main_spi_master_control_storage [15:8] + connect \builder_csrbank9_control1_w \main_spi_master_control_storage [15:8] + connect \builder_csrbank9_control0_w \main_spi_master_control_storage [7:0] + connect \main_spi_master_status_status \main_spi_master_done1 + connect \builder_csrbank9_status_w \main_spi_master_status_status + connect \main_spi_master_status_we \builder_csrbank9_status_we + connect \builder_csrbank9_mosi0_w \main_spi_master_mosi_storage + connect \builder_csrbank9_miso_w \main_spi_master_miso_status + connect \main_spi_master_miso_we \builder_csrbank9_miso_we + connect \main_spi_master_sel \main_spi_master_cs_storage + connect \builder_csrbank9_cs0_w \main_spi_master_cs_storage + connect \builder_csrbank9_loopback0_w \main_spi_master_loopback_storage + connect \builder_csrbank10_sel $eq$ls180.v:6234$1940_Y + connect \builder_csrbank10_control1_r \builder_interface10_bank_bus_dat_w + connect \builder_csrbank10_control1_re $and$ls180.v:6236$1943_Y + connect \builder_csrbank10_control1_we $and$ls180.v:6237$1947_Y + connect \builder_csrbank10_control0_r \builder_interface10_bank_bus_dat_w + connect \builder_csrbank10_control0_re $and$ls180.v:6239$1950_Y + connect \builder_csrbank10_control0_we $and$ls180.v:6240$1954_Y + connect \builder_csrbank10_status_r \builder_interface10_bank_bus_dat_w [0] + connect \builder_csrbank10_status_re $and$ls180.v:6242$1957_Y + connect \builder_csrbank10_status_we $and$ls180.v:6243$1961_Y + connect \builder_csrbank10_mosi0_r \builder_interface10_bank_bus_dat_w + connect \builder_csrbank10_mosi0_re $and$ls180.v:6245$1964_Y + connect \builder_csrbank10_mosi0_we $and$ls180.v:6246$1968_Y + connect \builder_csrbank10_miso_r \builder_interface10_bank_bus_dat_w + connect \builder_csrbank10_miso_re $and$ls180.v:6248$1971_Y + connect \builder_csrbank10_miso_we $and$ls180.v:6249$1975_Y + connect \builder_csrbank10_cs0_r \builder_interface10_bank_bus_dat_w [0] + connect \builder_csrbank10_cs0_re $and$ls180.v:6251$1978_Y + connect \builder_csrbank10_cs0_we $and$ls180.v:6252$1982_Y + connect \builder_csrbank10_loopback0_r \builder_interface10_bank_bus_dat_w [0] + connect \builder_csrbank10_loopback0_re $and$ls180.v:6254$1985_Y + connect \builder_csrbank10_loopback0_we $and$ls180.v:6255$1989_Y + connect \builder_csrbank10_clk_divider1_r \builder_interface10_bank_bus_dat_w + connect \builder_csrbank10_clk_divider1_re $and$ls180.v:6257$1992_Y + connect \builder_csrbank10_clk_divider1_we $and$ls180.v:6258$1996_Y + connect \builder_csrbank10_clk_divider0_r \builder_interface10_bank_bus_dat_w + connect \builder_csrbank10_clk_divider0_re $and$ls180.v:6260$1999_Y + connect \builder_csrbank10_clk_divider0_we $and$ls180.v:6261$2003_Y + connect \libresocsim_length1 \libresocsim_control_storage [15:8] + connect \builder_csrbank10_control1_w \libresocsim_control_storage [15:8] + connect \builder_csrbank10_control0_w \libresocsim_control_storage [7:0] + connect \libresocsim_status_status \libresocsim_done1 + connect \builder_csrbank10_status_w \libresocsim_status_status + connect \libresocsim_status_we \builder_csrbank10_status_we + connect \builder_csrbank10_mosi0_w \libresocsim_mosi_storage + connect \builder_csrbank10_miso_w \libresocsim_miso_status + connect \libresocsim_miso_we \builder_csrbank10_miso_we + connect \libresocsim_sel \libresocsim_cs_storage + connect \builder_csrbank10_cs0_w \libresocsim_cs_storage + connect \builder_csrbank10_loopback0_w \libresocsim_loopback_storage + connect \builder_csrbank10_clk_divider1_w \libresocsim_storage [15:8] + connect \builder_csrbank10_clk_divider0_w \libresocsim_storage [7:0] + connect \builder_csrbank11_sel $eq$ls180.v:6282$2005_Y + connect \builder_csrbank11_load3_r \builder_interface11_bank_bus_dat_w + connect \builder_csrbank11_load3_re $and$ls180.v:6284$2008_Y + connect \builder_csrbank11_load3_we $and$ls180.v:6285$2012_Y + connect \builder_csrbank11_load2_r \builder_interface11_bank_bus_dat_w + connect \builder_csrbank11_load2_re $and$ls180.v:6287$2015_Y + connect \builder_csrbank11_load2_we $and$ls180.v:6288$2019_Y + connect \builder_csrbank11_load1_r \builder_interface11_bank_bus_dat_w + connect \builder_csrbank11_load1_re $and$ls180.v:6290$2022_Y + connect \builder_csrbank11_load1_we $and$ls180.v:6291$2026_Y + connect \builder_csrbank11_load0_r \builder_interface11_bank_bus_dat_w + connect \builder_csrbank11_load0_re $and$ls180.v:6293$2029_Y + connect \builder_csrbank11_load0_we $and$ls180.v:6294$2033_Y + connect \builder_csrbank11_reload3_r \builder_interface11_bank_bus_dat_w + connect \builder_csrbank11_reload3_re $and$ls180.v:6296$2036_Y + connect \builder_csrbank11_reload3_we $and$ls180.v:6297$2040_Y + connect \builder_csrbank11_reload2_r \builder_interface11_bank_bus_dat_w + connect \builder_csrbank11_reload2_re $and$ls180.v:6299$2043_Y + connect \builder_csrbank11_reload2_we $and$ls180.v:6300$2047_Y + connect \builder_csrbank11_reload1_r \builder_interface11_bank_bus_dat_w + connect \builder_csrbank11_reload1_re $and$ls180.v:6302$2050_Y + connect \builder_csrbank11_reload1_we $and$ls180.v:6303$2054_Y + connect \builder_csrbank11_reload0_r \builder_interface11_bank_bus_dat_w + connect \builder_csrbank11_reload0_re $and$ls180.v:6305$2057_Y + connect \builder_csrbank11_reload0_we $and$ls180.v:6306$2061_Y + connect \builder_csrbank11_en0_r \builder_interface11_bank_bus_dat_w [0] + connect \builder_csrbank11_en0_re $and$ls180.v:6308$2064_Y + connect \builder_csrbank11_en0_we $and$ls180.v:6309$2068_Y + connect \builder_csrbank11_update_value0_r \builder_interface11_bank_bus_dat_w [0] + connect \builder_csrbank11_update_value0_re $and$ls180.v:6311$2071_Y + connect \builder_csrbank11_update_value0_we $and$ls180.v:6312$2075_Y + connect \builder_csrbank11_value3_r \builder_interface11_bank_bus_dat_w + connect \builder_csrbank11_value3_re $and$ls180.v:6314$2078_Y + connect \builder_csrbank11_value3_we $and$ls180.v:6315$2082_Y + connect \builder_csrbank11_value2_r \builder_interface11_bank_bus_dat_w + connect \builder_csrbank11_value2_re $and$ls180.v:6317$2085_Y + connect \builder_csrbank11_value2_we $and$ls180.v:6318$2089_Y + connect \builder_csrbank11_value1_r \builder_interface11_bank_bus_dat_w + connect \builder_csrbank11_value1_re $and$ls180.v:6320$2092_Y + connect \builder_csrbank11_value1_we $and$ls180.v:6321$2096_Y + connect \builder_csrbank11_value0_r \builder_interface11_bank_bus_dat_w + connect \builder_csrbank11_value0_re $and$ls180.v:6323$2099_Y + connect \builder_csrbank11_value0_we $and$ls180.v:6324$2103_Y + connect \main_libresocsim_eventmanager_status_r \builder_interface11_bank_bus_dat_w [0] + connect \main_libresocsim_eventmanager_status_re $and$ls180.v:6326$2106_Y + connect \main_libresocsim_eventmanager_status_we $and$ls180.v:6327$2110_Y + connect \main_libresocsim_eventmanager_pending_r \builder_interface11_bank_bus_dat_w [0] + connect \main_libresocsim_eventmanager_pending_re $and$ls180.v:6329$2113_Y + connect \main_libresocsim_eventmanager_pending_we $and$ls180.v:6330$2117_Y + connect \builder_csrbank11_ev_enable0_r \builder_interface11_bank_bus_dat_w [0] + connect \builder_csrbank11_ev_enable0_re $and$ls180.v:6332$2120_Y + connect \builder_csrbank11_ev_enable0_we $and$ls180.v:6333$2124_Y + connect \builder_csrbank11_load3_w \main_libresocsim_load_storage [31:24] + connect \builder_csrbank11_load2_w \main_libresocsim_load_storage [23:16] + connect \builder_csrbank11_load1_w \main_libresocsim_load_storage [15:8] + connect \builder_csrbank11_load0_w \main_libresocsim_load_storage [7:0] + connect \builder_csrbank11_reload3_w \main_libresocsim_reload_storage [31:24] + connect \builder_csrbank11_reload2_w \main_libresocsim_reload_storage [23:16] + connect \builder_csrbank11_reload1_w \main_libresocsim_reload_storage [15:8] + connect \builder_csrbank11_reload0_w \main_libresocsim_reload_storage [7:0] + connect \builder_csrbank11_en0_w \main_libresocsim_en_storage + connect \builder_csrbank11_update_value0_w \main_libresocsim_update_value_storage + connect \builder_csrbank11_value3_w \main_libresocsim_value_status [31:24] + connect \builder_csrbank11_value2_w \main_libresocsim_value_status [23:16] + connect \builder_csrbank11_value1_w \main_libresocsim_value_status [15:8] + connect \builder_csrbank11_value0_w \main_libresocsim_value_status [7:0] + connect \main_libresocsim_value_we \builder_csrbank11_value0_we + connect \builder_csrbank11_ev_enable0_w \main_libresocsim_eventmanager_storage + connect \builder_csrbank12_sel $eq$ls180.v:6350$2125_Y + connect \main_uart_rxtx_r \builder_interface12_bank_bus_dat_w + connect \main_uart_rxtx_re $and$ls180.v:6352$2128_Y + connect \main_uart_rxtx_we $and$ls180.v:6353$2132_Y + connect \builder_csrbank12_txfull_r \builder_interface12_bank_bus_dat_w [0] + connect \builder_csrbank12_txfull_re $and$ls180.v:6355$2135_Y + connect \builder_csrbank12_txfull_we $and$ls180.v:6356$2139_Y + connect \builder_csrbank12_rxempty_r \builder_interface12_bank_bus_dat_w [0] + connect \builder_csrbank12_rxempty_re $and$ls180.v:6358$2142_Y + connect \builder_csrbank12_rxempty_we $and$ls180.v:6359$2146_Y + connect \main_uart_eventmanager_status_r \builder_interface12_bank_bus_dat_w [1:0] + connect \main_uart_eventmanager_status_re $and$ls180.v:6361$2149_Y + connect \main_uart_eventmanager_status_we $and$ls180.v:6362$2153_Y + connect \main_uart_eventmanager_pending_r \builder_interface12_bank_bus_dat_w [1:0] + connect \main_uart_eventmanager_pending_re $and$ls180.v:6364$2156_Y + connect \main_uart_eventmanager_pending_we $and$ls180.v:6365$2160_Y + connect \builder_csrbank12_ev_enable0_r \builder_interface12_bank_bus_dat_w [1:0] + connect \builder_csrbank12_ev_enable0_re $and$ls180.v:6367$2163_Y + connect \builder_csrbank12_ev_enable0_we $and$ls180.v:6368$2167_Y + connect \builder_csrbank12_txempty_r \builder_interface12_bank_bus_dat_w [0] + connect \builder_csrbank12_txempty_re $and$ls180.v:6370$2170_Y + connect \builder_csrbank12_txempty_we $and$ls180.v:6371$2174_Y + connect \builder_csrbank12_rxfull_r \builder_interface12_bank_bus_dat_w [0] + connect \builder_csrbank12_rxfull_re $and$ls180.v:6373$2177_Y + connect \builder_csrbank12_rxfull_we $and$ls180.v:6374$2181_Y + connect \builder_csrbank12_txfull_w \main_uart_txfull_status + connect \main_uart_txfull_we \builder_csrbank12_txfull_we + connect \builder_csrbank12_rxempty_w \main_uart_rxempty_status + connect \main_uart_rxempty_we \builder_csrbank12_rxempty_we + connect \builder_csrbank12_ev_enable0_w \main_uart_eventmanager_storage + connect \builder_csrbank12_txempty_w \main_uart_txempty_status + connect \main_uart_txempty_we \builder_csrbank12_txempty_we + connect \builder_csrbank12_rxfull_w \main_uart_rxfull_status + connect \main_uart_rxfull_we \builder_csrbank12_rxfull_we + connect \builder_csrbank13_sel $eq$ls180.v:6384$2182_Y + connect \builder_csrbank13_tuning_word3_r \builder_interface13_bank_bus_dat_w + connect \builder_csrbank13_tuning_word3_re $and$ls180.v:6386$2185_Y + connect \builder_csrbank13_tuning_word3_we $and$ls180.v:6387$2189_Y + connect \builder_csrbank13_tuning_word2_r \builder_interface13_bank_bus_dat_w + connect \builder_csrbank13_tuning_word2_re $and$ls180.v:6389$2192_Y + connect \builder_csrbank13_tuning_word2_we $and$ls180.v:6390$2196_Y + connect \builder_csrbank13_tuning_word1_r \builder_interface13_bank_bus_dat_w + connect \builder_csrbank13_tuning_word1_re $and$ls180.v:6392$2199_Y + connect \builder_csrbank13_tuning_word1_we $and$ls180.v:6393$2203_Y + connect \builder_csrbank13_tuning_word0_r \builder_interface13_bank_bus_dat_w + connect \builder_csrbank13_tuning_word0_re $and$ls180.v:6395$2206_Y + connect \builder_csrbank13_tuning_word0_we $and$ls180.v:6396$2210_Y + connect \builder_csrbank13_tuning_word3_w \main_storage [31:24] + connect \builder_csrbank13_tuning_word2_w \main_storage [23:16] + connect \builder_csrbank13_tuning_word1_w \main_storage [15:8] + connect \builder_csrbank13_tuning_word0_w \main_storage [7:0] + connect \builder_csr_interconnect_adr \builder_libresocsim_adr + connect \builder_csr_interconnect_we \builder_libresocsim_we + connect \builder_csr_interconnect_dat_w \builder_libresocsim_dat_w + connect \builder_libresocsim_dat_r \builder_csr_interconnect_dat_r + connect \builder_interface0_bank_bus_adr \builder_csr_interconnect_adr + connect \builder_interface1_bank_bus_adr \builder_csr_interconnect_adr + connect \builder_interface2_bank_bus_adr \builder_csr_interconnect_adr + connect \builder_interface3_bank_bus_adr \builder_csr_interconnect_adr + connect \builder_interface4_bank_bus_adr \builder_csr_interconnect_adr + connect \builder_interface5_bank_bus_adr \builder_csr_interconnect_adr + connect \builder_interface6_bank_bus_adr \builder_csr_interconnect_adr + connect \builder_interface7_bank_bus_adr \builder_csr_interconnect_adr + connect \builder_interface8_bank_bus_adr \builder_csr_interconnect_adr + connect \builder_interface9_bank_bus_adr \builder_csr_interconnect_adr + connect \builder_interface10_bank_bus_adr \builder_csr_interconnect_adr + connect \builder_interface11_bank_bus_adr \builder_csr_interconnect_adr + connect \builder_interface12_bank_bus_adr \builder_csr_interconnect_adr + connect \builder_interface13_bank_bus_adr \builder_csr_interconnect_adr + connect \builder_interface0_bank_bus_we \builder_csr_interconnect_we + connect \builder_interface1_bank_bus_we \builder_csr_interconnect_we + connect \builder_interface2_bank_bus_we \builder_csr_interconnect_we + connect \builder_interface3_bank_bus_we \builder_csr_interconnect_we + connect \builder_interface4_bank_bus_we \builder_csr_interconnect_we + connect \builder_interface5_bank_bus_we \builder_csr_interconnect_we + connect \builder_interface6_bank_bus_we \builder_csr_interconnect_we + connect \builder_interface7_bank_bus_we \builder_csr_interconnect_we + connect \builder_interface8_bank_bus_we \builder_csr_interconnect_we + connect \builder_interface9_bank_bus_we \builder_csr_interconnect_we + connect \builder_interface10_bank_bus_we \builder_csr_interconnect_we + connect \builder_interface11_bank_bus_we \builder_csr_interconnect_we + connect \builder_interface12_bank_bus_we \builder_csr_interconnect_we + connect \builder_interface13_bank_bus_we \builder_csr_interconnect_we + connect \builder_interface0_bank_bus_dat_w \builder_csr_interconnect_dat_w + connect \builder_interface1_bank_bus_dat_w \builder_csr_interconnect_dat_w + connect \builder_interface2_bank_bus_dat_w \builder_csr_interconnect_dat_w + connect \builder_interface3_bank_bus_dat_w \builder_csr_interconnect_dat_w + connect \builder_interface4_bank_bus_dat_w \builder_csr_interconnect_dat_w + connect \builder_interface5_bank_bus_dat_w \builder_csr_interconnect_dat_w + connect \builder_interface6_bank_bus_dat_w \builder_csr_interconnect_dat_w + connect \builder_interface7_bank_bus_dat_w \builder_csr_interconnect_dat_w + connect \builder_interface8_bank_bus_dat_w \builder_csr_interconnect_dat_w + connect \builder_interface9_bank_bus_dat_w \builder_csr_interconnect_dat_w + connect \builder_interface10_bank_bus_dat_w \builder_csr_interconnect_dat_w + connect \builder_interface11_bank_bus_dat_w \builder_csr_interconnect_dat_w + connect \builder_interface12_bank_bus_dat_w \builder_csr_interconnect_dat_w + connect \builder_interface13_bank_bus_dat_w \builder_csr_interconnect_dat_w + connect \builder_csr_interconnect_dat_r $or$ls180.v:6447$2223_Y + connect \sdrio_clk \sys_clk_1 + connect \sdrio_clk_1 \sys_clk_1 + connect \sdrio_clk_2 \sys_clk_1 + connect \sdrio_clk_3 \sys_clk_1 + connect \sdrio_clk_4 \sys_clk_1 + connect \sdrio_clk_5 \sys_clk_1 + connect \sdrio_clk_6 \sys_clk_1 + connect \sdrio_clk_7 \sys_clk_1 + connect \sdrio_clk_8 \sys_clk_1 + connect \sdrio_clk_9 \sys_clk_1 + connect \sdrio_clk_10 \sys_clk_1 + connect \sdrio_clk_11 \sys_clk_1 + connect \sdrio_clk_12 \sys_clk_1 + connect \sdrio_clk_13 \sys_clk_1 + connect \sdrio_clk_14 \sys_clk_1 + connect \sdrio_clk_15 \sys_clk_1 + connect \sdrio_clk_16 \sys_clk_1 + connect \sdrio_clk_17 \sys_clk_1 + connect \sdrio_clk_18 \sys_clk_1 + connect \sdrio_clk_19 \sys_clk_1 + connect \sdrio_clk_20 \sys_clk_1 + connect \sdrio_clk_21 \sys_clk_1 + connect \sdrio_clk_22 \sys_clk_1 + connect \sdrio_clk_23 \sys_clk_1 + connect \sdrio_clk_24 \sys_clk_1 + connect \sdrio_clk_25 \sys_clk_1 + connect \sdrio_clk_26 \sys_clk_1 + connect \sdrio_clk_27 \sys_clk_1 + connect \sdrio_clk_28 \sys_clk_1 + connect \sdrio_clk_29 \sys_clk_1 + connect \sdrio_clk_30 \sys_clk_1 + connect \sdrio_clk_31 \sys_clk_1 + connect \sdrio_clk_32 \sys_clk_1 + connect \sdrio_clk_33 \sys_clk_1 + connect \sdrio_clk_34 \sys_clk_1 + connect \sdrio_clk_35 \sys_clk_1 + connect \sdrio_clk_36 \sys_clk_1 + connect \sdrio_clk_37 \sys_clk_1 + connect \sdrio_clk_38 \sys_clk_1 + connect \sdrio_clk_39 \sys_clk_1 + connect \sdrio_clk_40 \sys_clk_1 + connect \sdrio_clk_41 \sys_clk_1 + connect \sdrio_clk_42 \sys_clk_1 + connect \sdrio_clk_43 \sys_clk_1 + connect \sdrio_clk_44 \sys_clk_1 + connect \sdrio_clk_45 \sys_clk_1 + connect \sdrio_clk_46 \sys_clk_1 + connect \sdrio_clk_47 \sys_clk_1 + connect \sdrio_clk_48 \sys_clk_1 + connect \sdrio_clk_49 \sys_clk_1 + connect \sdrio_clk_50 \sys_clk_1 + connect \sdrio_clk_51 \sys_clk_1 + connect \sdrio_clk_52 \sys_clk_1 + connect \sdrio_clk_53 \sys_clk_1 + connect \sdrio_clk_54 \sys_clk_1 + connect \sdrio_clk_55 \sys_clk_1 + connect \main_rx \builder_multiregimpl0_regs1 + connect \main_pwm0_enable \main_pwm0_enable_storage + connect \main_pwm0_width \main_pwm0_width_storage + connect \main_pwm0_period \main_pwm0_period_storage + connect \main_pwm1_enable \main_pwm1_enable_storage + connect \main_pwm1_width \main_pwm1_width_storage + connect \main_pwm1_period \main_pwm1_period_storage + connect \sdrio_clk_56 \sys_clk_1 + connect \sdrio_clk_57 \sys_clk_1 + connect \sdrio_clk_58 \sys_clk_1 + connect \sdrio_clk_59 \sys_clk_1 + connect \sdrio_clk_60 \sys_clk_1 + connect \sdrio_clk_61 \sys_clk_1 + connect \sdrio_clk_62 \sys_clk_1 + connect \sdrio_clk_63 \sys_clk_1 + connect \sdrio_clk_64 \sys_clk_1 + connect \sdrio_clk_65 \sys_clk_1 + connect \sdrio_clk_66 \sys_clk_1 + connect \sdrio_clk_67 \sys_clk_1 + connect \sdrio_clk_68 \sys_clk_1 + connect \main_libresocsim_dat_r $memrd$\mem$ls180.v:9989$2695_DATA + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_r \memdat + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage$ls180.v:10007$2702_DATA + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_r \memdat_1 + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_1$ls180.v:10021$2709_DATA + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_r \memdat_2 + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_2$ls180.v:10035$2716_DATA + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_r \memdat_3 + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_3$ls180.v:10049$2723_DATA + connect \main_uart_tx_fifo_wrport_dat_r \memdat_4 + connect \main_uart_tx_fifo_rdport_dat_r \memdat_5 + connect \main_uart_rx_fifo_wrport_dat_r \memdat_6 + connect \main_uart_rx_fifo_rdport_dat_r \memdat_7 + connect \main_sdblock2mem_fifo_wrport_dat_r \memdat_8 + connect \main_sdblock2mem_fifo_rdport_dat_r $memrd$\storage_6$ls180.v:10097$2744_DATA + connect \main_sdmem2block_fifo_wrport_dat_r \memdat_9 + connect \main_sdmem2block_fifo_rdport_dat_r $memrd$\storage_7$ls180.v:10111$2751_DATA +end +attribute \src "libresoc.v:133011.1-133069.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.lsd_l" +attribute \generator "nMigen" +module \lsd_l + attribute \src "libresoc.v:133012.7-133012.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:133057.3-133065.6" + wire $0\q_int$next[0:0]$6560 + attribute \src "libresoc.v:133055.3-133056.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:133057.3-133065.6" + wire $1\q_int$next[0:0]$6561 + attribute \src "libresoc.v:133034.7-133034.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:133047.17-133047.96" + wire $and$libresoc.v:133047$6550_Y + attribute \src "libresoc.v:133052.17-133052.96" + wire $and$libresoc.v:133052$6555_Y + attribute \src "libresoc.v:133049.18-133049.93" + wire $not$libresoc.v:133049$6552_Y + attribute \src "libresoc.v:133051.17-133051.92" + wire $not$libresoc.v:133051$6554_Y + attribute \src "libresoc.v:133054.17-133054.92" + wire $not$libresoc.v:133054$6557_Y + attribute \src "libresoc.v:133048.18-133048.98" + wire $or$libresoc.v:133048$6551_Y + attribute \src "libresoc.v:133050.18-133050.99" + wire $or$libresoc.v:133050$6553_Y + attribute \src "libresoc.v:133053.17-133053.97" + wire $or$libresoc.v:133053$6556_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 1 \coresync_rst + attribute \src "libresoc.v:133012.7-133012.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 4 \q_lsd + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_lsd + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_lsd + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_lsd + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 2 \s_lsd + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$libresoc.v:133047$6550 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:133047$6550_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:133052$6555 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:133052$6555_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:133049$6552 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_lsd + connect \Y $not$libresoc.v:133049$6552_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:133051$6554 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_lsd + connect \Y $not$libresoc.v:133051$6554_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:133054$6557 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_lsd + connect \Y $not$libresoc.v:133054$6557_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:133048$6551 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_lsd + connect \Y $or$libresoc.v:133048$6551_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:133050$6553 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_lsd + connect \B \q_int + connect \Y $or$libresoc.v:133050$6553_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:133053$6556 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_lsd + connect \Y $or$libresoc.v:133053$6556_Y + end + attribute \src "libresoc.v:133012.7-133012.20" + process $proc$libresoc.v:133012$6562 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:133034.7-133034.19" + process $proc$libresoc.v:133034$6563 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:133055.3-133056.27" + process $proc$libresoc.v:133055$6558 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:133057.3-133065.6" + process $proc$libresoc.v:133057$6559 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$6560 $1\q_int$next[0:0]$6561 + attribute \src "libresoc.v:133058.5-133058.29" + switch \initial + attribute \src "libresoc.v:133058.9-133058.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$6561 1'0 + case + assign $1\q_int$next[0:0]$6561 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$6560 + end + connect \$9 $and$libresoc.v:133047$6550_Y + connect \$11 $or$libresoc.v:133048$6551_Y + connect \$13 $not$libresoc.v:133049$6552_Y + connect \$15 $or$libresoc.v:133050$6553_Y + connect \$1 $not$libresoc.v:133051$6554_Y + connect \$3 $and$libresoc.v:133052$6555_Y + connect \$5 $or$libresoc.v:133053$6556_Y + connect \$7 $not$libresoc.v:133054$6557_Y + connect \qlq_lsd \$15 + connect \qn_lsd \$13 + connect \q_lsd \$11 +end +attribute \src "libresoc.v:133073.1-133539.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.l0.lsmem" +attribute \generator "nMigen" +module \lsmem + attribute \src "libresoc.v:133422.3-133442.6" + wire width 45 $0\dbus__adr$next[44:0]$6644 + attribute \src "libresoc.v:133308.3-133309.35" + wire width 45 $0\dbus__adr[44:0] + attribute \src "libresoc.v:133318.3-133340.6" + wire $0\dbus__cyc$next[0:0]$6623 + attribute \src "libresoc.v:133316.3-133317.35" + wire $0\dbus__cyc[0:0] + attribute \src "libresoc.v:133464.3-133484.6" + wire width 64 $0\dbus__dat_w$next[63:0]$6652 + attribute \src "libresoc.v:133304.3-133305.39" + wire width 64 $0\dbus__dat_w[63:0] + attribute \src "libresoc.v:133376.3-133401.6" + wire width 8 $0\dbus__sel$next[7:0]$6634 + attribute \src "libresoc.v:133312.3-133313.35" + wire width 8 $0\dbus__sel[7:0] + attribute \src "libresoc.v:133341.3-133363.6" + wire $0\dbus__stb$next[0:0]$6628 + attribute \src "libresoc.v:133314.3-133315.35" + wire $0\dbus__stb[0:0] + attribute \src "libresoc.v:133443.3-133463.6" + wire $0\dbus__we$next[0:0]$6648 + attribute \src "libresoc.v:133306.3-133307.33" + wire $0\dbus__we[0:0] + attribute \src "libresoc.v:133074.7-133074.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:133521.3-133535.6" + wire width 45 $0\m_badaddr_o$next[44:0]$6664 + attribute \src "libresoc.v:133298.3-133299.39" + wire width 45 $0\m_badaddr_o[44:0] + attribute \src "libresoc.v:133364.3-133375.6" + wire $0\m_busy_o[0:0] + attribute \src "libresoc.v:133402.3-133421.6" + wire width 64 $0\m_ld_data_o$next[63:0]$6639 + attribute \src "libresoc.v:133310.3-133311.39" + wire width 64 $0\m_ld_data_o[63:0] + attribute \src "libresoc.v:133485.3-133502.6" + wire $0\m_load_err_o$next[0:0]$6656 + attribute \src "libresoc.v:133302.3-133303.41" + wire $0\m_load_err_o[0:0] + attribute \src "libresoc.v:133503.3-133520.6" + wire $0\m_store_err_o$next[0:0]$6660 + attribute \src "libresoc.v:133300.3-133301.43" + wire $0\m_store_err_o[0:0] + attribute \src "libresoc.v:133422.3-133442.6" + wire width 45 $1\dbus__adr$next[44:0]$6645 + attribute \src "libresoc.v:133179.14-133179.42" + wire width 45 $1\dbus__adr[44:0] + attribute \src "libresoc.v:133318.3-133340.6" + wire $1\dbus__cyc$next[0:0]$6624 + attribute \src "libresoc.v:133184.7-133184.23" + wire $1\dbus__cyc[0:0] + attribute \src "libresoc.v:133464.3-133484.6" + wire width 64 $1\dbus__dat_w$next[63:0]$6653 + attribute \src "libresoc.v:133191.14-133191.48" + wire width 64 $1\dbus__dat_w[63:0] + attribute \src "libresoc.v:133376.3-133401.6" + wire width 8 $1\dbus__sel$next[7:0]$6635 + attribute \src "libresoc.v:133198.13-133198.30" + wire width 8 $1\dbus__sel[7:0] + attribute \src "libresoc.v:133341.3-133363.6" + wire $1\dbus__stb$next[0:0]$6629 + attribute \src "libresoc.v:133203.7-133203.23" + wire $1\dbus__stb[0:0] + attribute \src "libresoc.v:133443.3-133463.6" + wire $1\dbus__we$next[0:0]$6649 + attribute \src "libresoc.v:133208.7-133208.22" + wire $1\dbus__we[0:0] + attribute \src "libresoc.v:133521.3-133535.6" + wire width 45 $1\m_badaddr_o$next[44:0]$6665 + attribute \src "libresoc.v:133212.14-133212.44" + wire width 45 $1\m_badaddr_o[44:0] + attribute \src "libresoc.v:133364.3-133375.6" + wire $1\m_busy_o[0:0] + attribute \src "libresoc.v:133402.3-133421.6" + wire width 64 $1\m_ld_data_o$next[63:0]$6640 + attribute \src "libresoc.v:133219.14-133219.48" + wire width 64 $1\m_ld_data_o[63:0] + attribute \src "libresoc.v:133485.3-133502.6" + wire $1\m_load_err_o$next[0:0]$6657 + attribute \src "libresoc.v:133223.7-133223.26" + wire $1\m_load_err_o[0:0] + attribute \src "libresoc.v:133503.3-133520.6" + wire $1\m_store_err_o$next[0:0]$6661 + attribute \src "libresoc.v:133229.7-133229.27" + wire $1\m_store_err_o[0:0] + attribute \src "libresoc.v:133422.3-133442.6" + wire width 45 $2\dbus__adr$next[44:0]$6646 + attribute \src "libresoc.v:133318.3-133340.6" + wire $2\dbus__cyc$next[0:0]$6625 + attribute \src "libresoc.v:133464.3-133484.6" + wire width 64 $2\dbus__dat_w$next[63:0]$6654 + attribute \src "libresoc.v:133376.3-133401.6" + wire width 8 $2\dbus__sel$next[7:0]$6636 + attribute \src "libresoc.v:133341.3-133363.6" + wire $2\dbus__stb$next[0:0]$6630 + attribute \src "libresoc.v:133443.3-133463.6" + wire $2\dbus__we$next[0:0]$6650 + attribute \src "libresoc.v:133521.3-133535.6" + wire width 45 $2\m_badaddr_o$next[44:0]$6666 + attribute \src "libresoc.v:133402.3-133421.6" + wire width 64 $2\m_ld_data_o$next[63:0]$6641 + attribute \src "libresoc.v:133485.3-133502.6" + wire $2\m_load_err_o$next[0:0]$6658 + attribute \src "libresoc.v:133503.3-133520.6" + wire $2\m_store_err_o$next[0:0]$6662 + attribute \src "libresoc.v:133318.3-133340.6" + wire $3\dbus__cyc$next[0:0]$6626 + attribute \src "libresoc.v:133376.3-133401.6" + wire width 8 $3\dbus__sel$next[7:0]$6637 + attribute \src "libresoc.v:133341.3-133363.6" + wire $3\dbus__stb$next[0:0]$6631 + attribute \src "libresoc.v:133402.3-133421.6" + wire width 64 $3\m_ld_data_o$next[63:0]$6642 + attribute \src "libresoc.v:133254.18-133254.116" + wire $and$libresoc.v:133254$6568_Y + attribute \src "libresoc.v:133257.18-133257.111" + wire $and$libresoc.v:133257$6571_Y + attribute \src "libresoc.v:133262.18-133262.116" + wire $and$libresoc.v:133262$6576_Y + attribute \src "libresoc.v:133264.18-133264.111" + wire $and$libresoc.v:133264$6578_Y + attribute \src "libresoc.v:133266.17-133266.114" + wire $and$libresoc.v:133266$6580_Y + attribute \src "libresoc.v:133270.18-133270.116" + wire $and$libresoc.v:133270$6584_Y + attribute \src "libresoc.v:133272.18-133272.111" + wire $and$libresoc.v:133272$6586_Y + attribute \src "libresoc.v:133278.18-133278.116" + wire $and$libresoc.v:133278$6592_Y + attribute \src "libresoc.v:133280.18-133280.111" + wire $and$libresoc.v:133280$6594_Y + attribute \src "libresoc.v:133282.18-133282.116" + wire $and$libresoc.v:133282$6596_Y + attribute \src "libresoc.v:133284.18-133284.111" + wire $and$libresoc.v:133284$6598_Y + attribute \src "libresoc.v:133286.18-133286.116" + wire $and$libresoc.v:133286$6600_Y + attribute \src "libresoc.v:133288.17-133288.108" + wire $and$libresoc.v:133288$6602_Y + attribute \src "libresoc.v:133289.18-133289.111" + wire $and$libresoc.v:133289$6603_Y + attribute \src "libresoc.v:133290.18-133290.120" + wire $and$libresoc.v:133290$6604_Y + attribute \src "libresoc.v:133293.18-133293.120" + wire $and$libresoc.v:133293$6607_Y + attribute \src "libresoc.v:133295.18-133295.120" + wire $and$libresoc.v:133295$6609_Y + attribute \src "libresoc.v:133251.18-133251.110" + wire $not$libresoc.v:133251$6565_Y + attribute \src "libresoc.v:133256.18-133256.110" + wire $not$libresoc.v:133256$6570_Y + attribute \src "libresoc.v:133259.18-133259.110" + wire $not$libresoc.v:133259$6573_Y + attribute \src "libresoc.v:133263.18-133263.110" + wire $not$libresoc.v:133263$6577_Y + attribute \src "libresoc.v:133267.18-133267.110" + wire $not$libresoc.v:133267$6581_Y + attribute \src "libresoc.v:133271.18-133271.110" + wire $not$libresoc.v:133271$6585_Y + attribute \src "libresoc.v:133274.18-133274.110" + wire $not$libresoc.v:133274$6588_Y + attribute \src "libresoc.v:133277.17-133277.109" + wire $not$libresoc.v:133277$6591_Y + attribute \src "libresoc.v:133279.18-133279.110" + wire $not$libresoc.v:133279$6593_Y + attribute \src "libresoc.v:133283.18-133283.110" + wire $not$libresoc.v:133283$6597_Y + attribute \src "libresoc.v:133287.18-133287.110" + wire $not$libresoc.v:133287$6601_Y + attribute \src "libresoc.v:133291.18-133291.110" + wire $not$libresoc.v:133291$6605_Y + attribute \src "libresoc.v:133292.18-133292.109" + wire $not$libresoc.v:133292$6606_Y + attribute \src "libresoc.v:133294.18-133294.110" + wire $not$libresoc.v:133294$6608_Y + attribute \src "libresoc.v:133296.18-133296.110" + wire $not$libresoc.v:133296$6610_Y + attribute \src "libresoc.v:133250.17-133250.119" + wire $or$libresoc.v:133250$6564_Y + attribute \src "libresoc.v:133252.18-133252.110" + wire $or$libresoc.v:133252$6566_Y + attribute \src "libresoc.v:133253.18-133253.114" + wire $or$libresoc.v:133253$6567_Y + attribute \src "libresoc.v:133255.17-133255.113" + wire $or$libresoc.v:133255$6569_Y + attribute \src "libresoc.v:133258.18-133258.120" + wire $or$libresoc.v:133258$6572_Y + attribute \src "libresoc.v:133260.18-133260.111" + wire $or$libresoc.v:133260$6574_Y + attribute \src "libresoc.v:133261.18-133261.114" + wire $or$libresoc.v:133261$6575_Y + attribute \src "libresoc.v:133265.18-133265.120" + wire $or$libresoc.v:133265$6579_Y + attribute \src "libresoc.v:133268.18-133268.111" + wire $or$libresoc.v:133268$6582_Y + attribute \src "libresoc.v:133269.18-133269.114" + wire $or$libresoc.v:133269$6583_Y + attribute \src "libresoc.v:133273.18-133273.120" + wire $or$libresoc.v:133273$6587_Y + attribute \src "libresoc.v:133275.18-133275.111" + wire $or$libresoc.v:133275$6589_Y + attribute \src "libresoc.v:133276.18-133276.114" + wire $or$libresoc.v:133276$6590_Y + attribute \src "libresoc.v:133281.18-133281.114" + wire $or$libresoc.v:133281$6595_Y + attribute \src "libresoc.v:133285.18-133285.114" + wire $or$libresoc.v:133285$6599_Y + attribute \src "libresoc.v:133297.18-133297.127" + wire $or$libresoc.v:133297$6611_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + wire \$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + wire \$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" + wire \$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + wire \$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + wire \$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + wire \$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" + wire \$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" + wire \$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" + wire \$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + wire \$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + wire \$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + wire \$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + wire \$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" + wire \$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" + wire \$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" + wire \$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + wire \$57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + wire \$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + wire \$61 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + wire \$63 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + wire \$65 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + wire \$67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + wire \$69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + wire \$71 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + wire \$73 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + wire \$75 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + wire \$77 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + wire \$79 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:131" + wire \$81 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:137" + wire \$83 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:133" + wire \$85 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:131" + wire \$87 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:137" + wire \$89 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:131" + wire \$91 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:137" + wire \$93 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:145" + wire \$95 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 20 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire input 12 \dbus__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 45 output 17 \dbus__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 45 \dbus__adr$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire output 11 \dbus__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire \dbus__cyc$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 64 input 16 \dbus__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 64 output 19 \dbus__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 64 \dbus__dat_w$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire input 13 \dbus__err + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 8 output 15 \dbus__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 8 \dbus__sel$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire output 14 \dbus__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire \dbus__stb$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire output 18 \dbus__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire \dbus__we$next + attribute \src "libresoc.v:133074.7-133074.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:70" + wire width 45 \m_badaddr_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:70" + wire width 45 \m_badaddr_o$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:60" + wire \m_busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:62" + wire width 64 output 4 \m_ld_data_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:62" + wire width 64 \m_ld_data_o$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:67" + wire \m_load_err_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:67" + wire \m_load_err_o$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:53" + wire \m_stall_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:68" + wire \m_store_err_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:68" + wire \m_store_err_o$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:54" + wire input 9 \m_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:43" + wire width 48 input 3 \x_addr_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:59" + wire output 6 \x_busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:45" + wire input 7 \x_ld_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:44" + wire width 8 input 2 \x_mask_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:47" + wire width 64 input 5 \x_st_data_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:46" + wire input 8 \x_st_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:49" + wire \x_stall_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:50" + wire input 10 \x_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + cell $and $and$libresoc.v:133254$6568 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$15 + connect \B \x_valid_i + connect \Y $and$libresoc.v:133254$6568_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + cell $and $and$libresoc.v:133257$6571 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$17 + connect \B \$19 + connect \Y $and$libresoc.v:133257$6571_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + cell $and $and$libresoc.v:133262$6576 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$29 + connect \B \x_valid_i + connect \Y $and$libresoc.v:133262$6576_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + cell $and $and$libresoc.v:133264$6578 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$31 + connect \B \$33 + connect \Y $and$libresoc.v:133264$6578_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + cell $and $and$libresoc.v:133266$6580 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$1 + connect \B \x_valid_i + connect \Y $and$libresoc.v:133266$6580_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + cell $and $and$libresoc.v:133270$6584 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$43 + connect \B \x_valid_i + connect \Y $and$libresoc.v:133270$6584_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + cell $and $and$libresoc.v:133272$6586 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$45 + connect \B \$47 + connect \Y $and$libresoc.v:133272$6586_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + cell $and $and$libresoc.v:133278$6592 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$57 + connect \B \x_valid_i + connect \Y $and$libresoc.v:133278$6592_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + cell $and $and$libresoc.v:133280$6594 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$59 + connect \B \$61 + connect \Y $and$libresoc.v:133280$6594_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + cell $and $and$libresoc.v:133282$6596 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$65 + connect \B \x_valid_i + connect \Y $and$libresoc.v:133282$6596_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + cell $and $and$libresoc.v:133284$6598 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$67 + connect \B \$69 + connect \Y $and$libresoc.v:133284$6598_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + cell $and $and$libresoc.v:133286$6600 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$73 + connect \B \x_valid_i + connect \Y $and$libresoc.v:133286$6600_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + cell $and $and$libresoc.v:133288$6602 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \$5 + connect \Y $and$libresoc.v:133288$6602_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + cell $and $and$libresoc.v:133289$6603 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$75 + connect \B \$77 + connect \Y $and$libresoc.v:133289$6603_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:131" + cell $and $and$libresoc.v:133290$6604 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dbus__cyc + connect \B \dbus__err + connect \Y $and$libresoc.v:133290$6604_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:131" + cell $and $and$libresoc.v:133293$6607 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dbus__cyc + connect \B \dbus__err + connect \Y $and$libresoc.v:133293$6607_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:131" + cell $and $and$libresoc.v:133295$6609 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dbus__cyc + connect \B \dbus__err + connect \Y $and$libresoc.v:133295$6609_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" + cell $not $not$libresoc.v:133251$6565 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \m_valid_i + connect \Y $not$libresoc.v:133251$6565_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + cell $not $not$libresoc.v:133256$6570 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \x_stall_i + connect \Y $not$libresoc.v:133256$6570_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" + cell $not $not$libresoc.v:133259$6573 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \m_valid_i + connect \Y $not$libresoc.v:133259$6573_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + cell $not $not$libresoc.v:133263$6577 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \x_stall_i + connect \Y $not$libresoc.v:133263$6577_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" + cell $not $not$libresoc.v:133267$6581 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \m_valid_i + connect \Y $not$libresoc.v:133267$6581_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + cell $not $not$libresoc.v:133271$6585 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \x_stall_i + connect \Y $not$libresoc.v:133271$6585_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" + cell $not $not$libresoc.v:133274$6588 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \m_valid_i + connect \Y $not$libresoc.v:133274$6588_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + cell $not $not$libresoc.v:133277$6591 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \x_stall_i + connect \Y $not$libresoc.v:133277$6591_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + cell $not $not$libresoc.v:133279$6593 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \x_stall_i + connect \Y $not$libresoc.v:133279$6593_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + cell $not $not$libresoc.v:133283$6597 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \x_stall_i + connect \Y $not$libresoc.v:133283$6597_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + cell $not $not$libresoc.v:133287$6601 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \x_stall_i + connect \Y $not$libresoc.v:133287$6601_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:137" + cell $not $not$libresoc.v:133291$6605 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \m_stall_i + connect \Y $not$libresoc.v:133291$6605_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:133" + cell $not $not$libresoc.v:133292$6606 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dbus__we + connect \Y $not$libresoc.v:133292$6606_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:137" + cell $not $not$libresoc.v:133294$6608 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \m_stall_i + connect \Y $not$libresoc.v:133294$6608_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:137" + cell $not $not$libresoc.v:133296$6610 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \m_stall_i + connect \Y $not$libresoc.v:133296$6610_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" + cell $or $or$libresoc.v:133250$6564 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dbus__ack + connect \B \dbus__err + connect \Y $or$libresoc.v:133250$6564_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" + cell $or $or$libresoc.v:133252$6566 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \$11 + connect \Y $or$libresoc.v:133252$6566_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + cell $or $or$libresoc.v:133253$6567 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \x_ld_i + connect \B \x_st_i + connect \Y $or$libresoc.v:133253$6567_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + cell $or $or$libresoc.v:133255$6569 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \x_ld_i + connect \B \x_st_i + connect \Y $or$libresoc.v:133255$6569_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" + cell $or $or$libresoc.v:133258$6572 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dbus__ack + connect \B \dbus__err + connect \Y $or$libresoc.v:133258$6572_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" + cell $or $or$libresoc.v:133260$6574 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$23 + connect \B \$25 + connect \Y $or$libresoc.v:133260$6574_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + cell $or $or$libresoc.v:133261$6575 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \x_ld_i + connect \B \x_st_i + connect \Y $or$libresoc.v:133261$6575_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" + cell $or $or$libresoc.v:133265$6579 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dbus__ack + connect \B \dbus__err + connect \Y $or$libresoc.v:133265$6579_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" + cell $or $or$libresoc.v:133268$6582 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$37 + connect \B \$39 + connect \Y $or$libresoc.v:133268$6582_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + cell $or $or$libresoc.v:133269$6583 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \x_ld_i + connect \B \x_st_i + connect \Y $or$libresoc.v:133269$6583_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" + cell $or $or$libresoc.v:133273$6587 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dbus__ack + connect \B \dbus__err + connect \Y $or$libresoc.v:133273$6587_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" + cell $or $or$libresoc.v:133275$6589 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$51 + connect \B \$53 + connect \Y $or$libresoc.v:133275$6589_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + cell $or $or$libresoc.v:133276$6590 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \x_ld_i + connect \B \x_st_i + connect \Y $or$libresoc.v:133276$6590_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + cell $or $or$libresoc.v:133281$6595 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \x_ld_i + connect \B \x_st_i + connect \Y $or$libresoc.v:133281$6595_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + cell $or $or$libresoc.v:133285$6599 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \x_ld_i + connect \B \x_st_i + connect \Y $or$libresoc.v:133285$6599_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:145" + cell $or $or$libresoc.v:133297$6611 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \m_load_err_o + connect \B \m_store_err_o + connect \Y $or$libresoc.v:133297$6611_Y + end + attribute \src "libresoc.v:133074.7-133074.20" + process $proc$libresoc.v:133074$6667 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:133179.14-133179.42" + process $proc$libresoc.v:133179$6668 + assign { } { } + assign $1\dbus__adr[44:0] 45'000000000000000000000000000000000000000000000 + sync always + sync init + update \dbus__adr $1\dbus__adr[44:0] + end + attribute \src "libresoc.v:133184.7-133184.23" + process $proc$libresoc.v:133184$6669 + assign { } { } + assign $1\dbus__cyc[0:0] 1'0 + sync always + sync init + update \dbus__cyc $1\dbus__cyc[0:0] + end + attribute \src "libresoc.v:133191.14-133191.48" + process $proc$libresoc.v:133191$6670 + assign { } { } + assign $1\dbus__dat_w[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \dbus__dat_w $1\dbus__dat_w[63:0] + end + attribute \src "libresoc.v:133198.13-133198.30" + process $proc$libresoc.v:133198$6671 + assign { } { } + assign $1\dbus__sel[7:0] 8'00000000 + sync always + sync init + update \dbus__sel $1\dbus__sel[7:0] + end + attribute \src "libresoc.v:133203.7-133203.23" + process $proc$libresoc.v:133203$6672 + assign { } { } + assign $1\dbus__stb[0:0] 1'0 + sync always + sync init + update \dbus__stb $1\dbus__stb[0:0] + end + attribute \src "libresoc.v:133208.7-133208.22" + process $proc$libresoc.v:133208$6673 + assign { } { } + assign $1\dbus__we[0:0] 1'0 + sync always + sync init + update \dbus__we $1\dbus__we[0:0] + end + attribute \src "libresoc.v:133212.14-133212.44" + process $proc$libresoc.v:133212$6674 + assign { } { } + assign $1\m_badaddr_o[44:0] 45'000000000000000000000000000000000000000000000 + sync always + sync init + update \m_badaddr_o $1\m_badaddr_o[44:0] + end + attribute \src "libresoc.v:133219.14-133219.48" + process $proc$libresoc.v:133219$6675 + assign { } { } + assign $1\m_ld_data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \m_ld_data_o $1\m_ld_data_o[63:0] + end + attribute \src "libresoc.v:133223.7-133223.26" + process $proc$libresoc.v:133223$6676 + assign { } { } + assign $1\m_load_err_o[0:0] 1'0 + sync always + sync init + update \m_load_err_o $1\m_load_err_o[0:0] + end + attribute \src "libresoc.v:133229.7-133229.27" + process $proc$libresoc.v:133229$6677 + assign { } { } + assign $1\m_store_err_o[0:0] 1'0 + sync always + sync init + update \m_store_err_o $1\m_store_err_o[0:0] + end + attribute \src "libresoc.v:133298.3-133299.39" + process $proc$libresoc.v:133298$6612 + assign { } { } + assign $0\m_badaddr_o[44:0] \m_badaddr_o$next + sync posedge \coresync_clk + update \m_badaddr_o $0\m_badaddr_o[44:0] + end + attribute \src "libresoc.v:133300.3-133301.43" + process $proc$libresoc.v:133300$6613 + assign { } { } + assign $0\m_store_err_o[0:0] \m_store_err_o$next + sync posedge \coresync_clk + update \m_store_err_o $0\m_store_err_o[0:0] + end + attribute \src "libresoc.v:133302.3-133303.41" + process $proc$libresoc.v:133302$6614 + assign { } { } + assign $0\m_load_err_o[0:0] \m_load_err_o$next + sync posedge \coresync_clk + update \m_load_err_o $0\m_load_err_o[0:0] + end + attribute \src "libresoc.v:133304.3-133305.39" + process $proc$libresoc.v:133304$6615 + assign { } { } + assign $0\dbus__dat_w[63:0] \dbus__dat_w$next + sync posedge \coresync_clk + update \dbus__dat_w $0\dbus__dat_w[63:0] + end + attribute \src "libresoc.v:133306.3-133307.33" + process $proc$libresoc.v:133306$6616 + assign { } { } + assign $0\dbus__we[0:0] \dbus__we$next + sync posedge \coresync_clk + update \dbus__we $0\dbus__we[0:0] + end + attribute \src "libresoc.v:133308.3-133309.35" + process $proc$libresoc.v:133308$6617 + assign { } { } + assign $0\dbus__adr[44:0] \dbus__adr$next + sync posedge \coresync_clk + update \dbus__adr $0\dbus__adr[44:0] + end + attribute \src "libresoc.v:133310.3-133311.39" + process $proc$libresoc.v:133310$6618 + assign { } { } + assign $0\m_ld_data_o[63:0] \m_ld_data_o$next + sync posedge \coresync_clk + update \m_ld_data_o $0\m_ld_data_o[63:0] + end + attribute \src "libresoc.v:133312.3-133313.35" + process $proc$libresoc.v:133312$6619 + assign { } { } + assign $0\dbus__sel[7:0] \dbus__sel$next + sync posedge \coresync_clk + update \dbus__sel $0\dbus__sel[7:0] + end + attribute \src "libresoc.v:133314.3-133315.35" + process $proc$libresoc.v:133314$6620 + assign { } { } + assign $0\dbus__stb[0:0] \dbus__stb$next + sync posedge \coresync_clk + update \dbus__stb $0\dbus__stb[0:0] + end + attribute \src "libresoc.v:133316.3-133317.35" + process $proc$libresoc.v:133316$6621 + assign { } { } + assign $0\dbus__cyc[0:0] \dbus__cyc$next + sync posedge \coresync_clk + update \dbus__cyc $0\dbus__cyc[0:0] + end + attribute \src "libresoc.v:133318.3-133340.6" + process $proc$libresoc.v:133318$6622 + assign { } { } + assign { } { } + assign { } { } + assign $0\dbus__cyc$next[0:0]$6623 $3\dbus__cyc$next[0:0]$6626 + attribute \src "libresoc.v:133319.5-133319.29" + switch \initial + attribute \src "libresoc.v:133319.9-133319.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:104" + switch { \$7 \dbus__cyc } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\dbus__cyc$next[0:0]$6624 $2\dbus__cyc$next[0:0]$6625 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" + switch \$13 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\dbus__cyc$next[0:0]$6625 1'0 + case + assign $2\dbus__cyc$next[0:0]$6625 \dbus__cyc + end + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\dbus__cyc$next[0:0]$6624 1'1 + case + assign $1\dbus__cyc$next[0:0]$6624 \dbus__cyc + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\dbus__cyc$next[0:0]$6626 1'0 + case + assign $3\dbus__cyc$next[0:0]$6626 $1\dbus__cyc$next[0:0]$6624 + end + sync always + update \dbus__cyc$next $0\dbus__cyc$next[0:0]$6623 + end + attribute \src "libresoc.v:133341.3-133363.6" + process $proc$libresoc.v:133341$6627 + assign { } { } + assign { } { } + assign { } { } + assign $0\dbus__stb$next[0:0]$6628 $3\dbus__stb$next[0:0]$6631 + attribute \src "libresoc.v:133342.5-133342.29" + switch \initial + attribute \src "libresoc.v:133342.9-133342.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:104" + switch { \$21 \dbus__cyc } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\dbus__stb$next[0:0]$6629 $2\dbus__stb$next[0:0]$6630 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" + switch \$27 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\dbus__stb$next[0:0]$6630 1'0 + case + assign $2\dbus__stb$next[0:0]$6630 \dbus__stb + end + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\dbus__stb$next[0:0]$6629 1'1 + case + assign $1\dbus__stb$next[0:0]$6629 \dbus__stb + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\dbus__stb$next[0:0]$6631 1'0 + case + assign $3\dbus__stb$next[0:0]$6631 $1\dbus__stb$next[0:0]$6629 + end + sync always + update \dbus__stb$next $0\dbus__stb$next[0:0]$6628 + end + attribute \src "libresoc.v:133364.3-133375.6" + process $proc$libresoc.v:133364$6632 + assign { } { } + assign $0\m_busy_o[0:0] $1\m_busy_o[0:0] + attribute \src "libresoc.v:133365.5-133365.29" + switch \initial + attribute \src "libresoc.v:133365.9-133365.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:145" + switch \$95 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\m_busy_o[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\m_busy_o[0:0] \dbus__cyc + end + sync always + update \m_busy_o $0\m_busy_o[0:0] + end + attribute \src "libresoc.v:133376.3-133401.6" + process $proc$libresoc.v:133376$6633 + assign { } { } + assign { } { } + assign { } { } + assign $0\dbus__sel$next[7:0]$6634 $3\dbus__sel$next[7:0]$6637 + attribute \src "libresoc.v:133377.5-133377.29" + switch \initial + attribute \src "libresoc.v:133377.9-133377.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:104" + switch { \$35 \dbus__cyc } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\dbus__sel$next[7:0]$6635 $2\dbus__sel$next[7:0]$6636 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" + switch \$41 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\dbus__sel$next[7:0]$6636 8'00000000 + case + assign $2\dbus__sel$next[7:0]$6636 \dbus__sel + end + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\dbus__sel$next[7:0]$6635 \x_mask_i + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\dbus__sel$next[7:0]$6635 8'00000000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\dbus__sel$next[7:0]$6637 8'00000000 + case + assign $3\dbus__sel$next[7:0]$6637 $1\dbus__sel$next[7:0]$6635 + end + sync always + update \dbus__sel$next $0\dbus__sel$next[7:0]$6634 + end + attribute \src "libresoc.v:133402.3-133421.6" + process $proc$libresoc.v:133402$6638 + assign { } { } + assign { } { } + assign { } { } + assign $0\m_ld_data_o$next[63:0]$6639 $3\m_ld_data_o$next[63:0]$6642 + attribute \src "libresoc.v:133403.5-133403.29" + switch \initial + attribute \src "libresoc.v:133403.9-133403.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:104" + switch { \$49 \dbus__cyc } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\m_ld_data_o$next[63:0]$6640 $2\m_ld_data_o$next[63:0]$6641 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" + switch \$55 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\m_ld_data_o$next[63:0]$6641 \dbus__dat_r + case + assign $2\m_ld_data_o$next[63:0]$6641 \m_ld_data_o + end + case + assign $1\m_ld_data_o$next[63:0]$6640 \m_ld_data_o + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\m_ld_data_o$next[63:0]$6642 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $3\m_ld_data_o$next[63:0]$6642 $1\m_ld_data_o$next[63:0]$6640 + end + sync always + update \m_ld_data_o$next $0\m_ld_data_o$next[63:0]$6639 + end + attribute \src "libresoc.v:133422.3-133442.6" + process $proc$libresoc.v:133422$6643 + assign { } { } + assign { } { } + assign { } { } + assign $0\dbus__adr$next[44:0]$6644 $2\dbus__adr$next[44:0]$6646 + attribute \src "libresoc.v:133423.5-133423.29" + switch \initial + attribute \src "libresoc.v:133423.9-133423.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:104" + switch { \$63 \dbus__cyc } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign $1\dbus__adr$next[44:0]$6645 \dbus__adr + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\dbus__adr$next[44:0]$6645 \x_addr_i [47:3] + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\dbus__adr$next[44:0]$6645 45'000000000000000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\dbus__adr$next[44:0]$6646 45'000000000000000000000000000000000000000000000 + case + assign $2\dbus__adr$next[44:0]$6646 $1\dbus__adr$next[44:0]$6645 + end + sync always + update \dbus__adr$next $0\dbus__adr$next[44:0]$6644 + end + attribute \src "libresoc.v:133443.3-133463.6" + process $proc$libresoc.v:133443$6647 + assign { } { } + assign { } { } + assign { } { } + assign $0\dbus__we$next[0:0]$6648 $2\dbus__we$next[0:0]$6650 + attribute \src "libresoc.v:133444.5-133444.29" + switch \initial + attribute \src "libresoc.v:133444.9-133444.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:104" + switch { \$71 \dbus__cyc } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign $1\dbus__we$next[0:0]$6649 \dbus__we + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\dbus__we$next[0:0]$6649 \x_st_i + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\dbus__we$next[0:0]$6649 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\dbus__we$next[0:0]$6650 1'0 + case + assign $2\dbus__we$next[0:0]$6650 $1\dbus__we$next[0:0]$6649 + end + sync always + update \dbus__we$next $0\dbus__we$next[0:0]$6648 + end + attribute \src "libresoc.v:133464.3-133484.6" + process $proc$libresoc.v:133464$6651 + assign { } { } + assign { } { } + assign { } { } + assign $0\dbus__dat_w$next[63:0]$6652 $2\dbus__dat_w$next[63:0]$6654 + attribute \src "libresoc.v:133465.5-133465.29" + switch \initial + attribute \src "libresoc.v:133465.9-133465.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:104" + switch { \$79 \dbus__cyc } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign $1\dbus__dat_w$next[63:0]$6653 \dbus__dat_w + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\dbus__dat_w$next[63:0]$6653 \x_st_data_i + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\dbus__dat_w$next[63:0]$6653 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\dbus__dat_w$next[63:0]$6654 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $2\dbus__dat_w$next[63:0]$6654 $1\dbus__dat_w$next[63:0]$6653 + end + sync always + update \dbus__dat_w$next $0\dbus__dat_w$next[63:0]$6652 + end + attribute \src "libresoc.v:133485.3-133502.6" + process $proc$libresoc.v:133485$6655 + assign { } { } + assign { } { } + assign { } { } + assign $0\m_load_err_o$next[0:0]$6656 $2\m_load_err_o$next[0:0]$6658 + attribute \src "libresoc.v:133486.5-133486.29" + switch \initial + attribute \src "libresoc.v:133486.9-133486.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:131" + switch { \$83 \$81 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\m_load_err_o$next[0:0]$6657 \$85 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\m_load_err_o$next[0:0]$6657 1'0 + case + assign $1\m_load_err_o$next[0:0]$6657 \m_load_err_o + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\m_load_err_o$next[0:0]$6658 1'0 + case + assign $2\m_load_err_o$next[0:0]$6658 $1\m_load_err_o$next[0:0]$6657 + end + sync always + update \m_load_err_o$next $0\m_load_err_o$next[0:0]$6656 + end + attribute \src "libresoc.v:133503.3-133520.6" + process $proc$libresoc.v:133503$6659 + assign { } { } + assign { } { } + assign { } { } + assign $0\m_store_err_o$next[0:0]$6660 $2\m_store_err_o$next[0:0]$6662 + attribute \src "libresoc.v:133504.5-133504.29" + switch \initial + attribute \src "libresoc.v:133504.9-133504.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:131" + switch { \$89 \$87 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\m_store_err_o$next[0:0]$6661 \dbus__we + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\m_store_err_o$next[0:0]$6661 1'0 + case + assign $1\m_store_err_o$next[0:0]$6661 \m_store_err_o + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\m_store_err_o$next[0:0]$6662 1'0 + case + assign $2\m_store_err_o$next[0:0]$6662 $1\m_store_err_o$next[0:0]$6661 + end + sync always + update \m_store_err_o$next $0\m_store_err_o$next[0:0]$6660 + end + attribute \src "libresoc.v:133521.3-133535.6" + process $proc$libresoc.v:133521$6663 + assign { } { } + assign { } { } + assign { } { } + assign $0\m_badaddr_o$next[44:0]$6664 $2\m_badaddr_o$next[44:0]$6666 + attribute \src "libresoc.v:133522.5-133522.29" + switch \initial + attribute \src "libresoc.v:133522.9-133522.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:131" + switch { \$93 \$91 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\m_badaddr_o$next[44:0]$6665 \dbus__adr + case + assign $1\m_badaddr_o$next[44:0]$6665 \m_badaddr_o + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\m_badaddr_o$next[44:0]$6666 45'000000000000000000000000000000000000000000000 + case + assign $2\m_badaddr_o$next[44:0]$6666 $1\m_badaddr_o$next[44:0]$6665 + end + sync always + update \m_badaddr_o$next $0\m_badaddr_o$next[44:0]$6664 + end + connect \$9 $or$libresoc.v:133250$6564_Y + connect \$11 $not$libresoc.v:133251$6565_Y + connect \$13 $or$libresoc.v:133252$6566_Y + connect \$15 $or$libresoc.v:133253$6567_Y + connect \$17 $and$libresoc.v:133254$6568_Y + connect \$1 $or$libresoc.v:133255$6569_Y + connect \$19 $not$libresoc.v:133256$6570_Y + connect \$21 $and$libresoc.v:133257$6571_Y + connect \$23 $or$libresoc.v:133258$6572_Y + connect \$25 $not$libresoc.v:133259$6573_Y + connect \$27 $or$libresoc.v:133260$6574_Y + connect \$29 $or$libresoc.v:133261$6575_Y + connect \$31 $and$libresoc.v:133262$6576_Y + connect \$33 $not$libresoc.v:133263$6577_Y + connect \$35 $and$libresoc.v:133264$6578_Y + connect \$37 $or$libresoc.v:133265$6579_Y + connect \$3 $and$libresoc.v:133266$6580_Y + connect \$39 $not$libresoc.v:133267$6581_Y + connect \$41 $or$libresoc.v:133268$6582_Y + connect \$43 $or$libresoc.v:133269$6583_Y + connect \$45 $and$libresoc.v:133270$6584_Y + connect \$47 $not$libresoc.v:133271$6585_Y + connect \$49 $and$libresoc.v:133272$6586_Y + connect \$51 $or$libresoc.v:133273$6587_Y + connect \$53 $not$libresoc.v:133274$6588_Y + connect \$55 $or$libresoc.v:133275$6589_Y + connect \$57 $or$libresoc.v:133276$6590_Y + connect \$5 $not$libresoc.v:133277$6591_Y + connect \$59 $and$libresoc.v:133278$6592_Y + connect \$61 $not$libresoc.v:133279$6593_Y + connect \$63 $and$libresoc.v:133280$6594_Y + connect \$65 $or$libresoc.v:133281$6595_Y + connect \$67 $and$libresoc.v:133282$6596_Y + connect \$69 $not$libresoc.v:133283$6597_Y + connect \$71 $and$libresoc.v:133284$6598_Y + connect \$73 $or$libresoc.v:133285$6599_Y + connect \$75 $and$libresoc.v:133286$6600_Y + connect \$77 $not$libresoc.v:133287$6601_Y + connect \$7 $and$libresoc.v:133288$6602_Y + connect \$79 $and$libresoc.v:133289$6603_Y + connect \$81 $and$libresoc.v:133290$6604_Y + connect \$83 $not$libresoc.v:133291$6605_Y + connect \$85 $not$libresoc.v:133292$6606_Y + connect \$87 $and$libresoc.v:133293$6607_Y + connect \$89 $not$libresoc.v:133294$6608_Y + connect \$91 $and$libresoc.v:133295$6609_Y + connect \$93 $not$libresoc.v:133296$6610_Y + connect \$95 $or$libresoc.v:133297$6611_Y + connect \x_stall_i 1'0 + connect \m_stall_i 1'0 + connect \x_busy_o \dbus__cyc +end +attribute \src "libresoc.v:133543.1-134498.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alu_alu0.pipe1.main" +attribute \generator "nMigen" +module \main + attribute \src "libresoc.v:134070.3-134092.6" + wire width 64 $0\a_i[63:0] + attribute \src "libresoc.v:134169.3-134195.6" + wire $0\a_lt[0:0] + attribute \src "libresoc.v:134450.3-134460.6" + wire width 64 $0\a_n[63:0] + attribute \src "libresoc.v:134420.3-134429.6" + wire width 66 $0\add_a[65:0] + attribute \src "libresoc.v:134430.3-134439.6" + wire width 66 $0\add_b[65:0] + attribute \src "libresoc.v:134440.3-134449.6" + wire width 66 $0\add_o[65:0] + attribute \src "libresoc.v:134308.3-134330.6" + wire width 64 $0\b_i[63:0] + attribute \src "libresoc.v:134294.3-134307.6" + wire width 2 $0\ca[1:0] + attribute \src "libresoc.v:134461.3-134471.6" + wire $0\carry_32[0:0] + attribute \src "libresoc.v:134472.3-134482.6" + wire $0\carry_64[0:0] + attribute \src "libresoc.v:134196.3-134221.6" + wire width 4 $0\cr_a[3:0] + attribute \src "libresoc.v:134222.3-134236.6" + wire $0\cr_a_ok[0:0] + attribute \src "libresoc.v:134400.3-134419.6" + wire width 8 $0\eqs[7:0] + attribute \src "libresoc.v:133544.7-133544.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:134060.3-134069.6" + wire $0\is_32bit[0:0] + attribute \src "libresoc.v:134131.3-134149.6" + wire $0\msb_a[0:0] + attribute \src "libresoc.v:134150.3-134168.6" + wire $0\msb_b[0:0] + attribute \src "libresoc.v:134237.3-134274.6" + wire width 64 $0\o[63:0] + attribute \src "libresoc.v:134275.3-134293.6" + wire $0\o_ok[0:0] + attribute \src "libresoc.v:134353.3-134366.6" + wire width 2 $0\ov[1:0] + attribute \src "libresoc.v:134389.3-134399.6" + wire width 8 $0\src1[7:0] + attribute \src "libresoc.v:134104.3-134130.6" + wire width 5 $0\tval[4:0] + attribute \src "libresoc.v:134331.3-134341.6" + wire width 2 $0\xer_ca$20[1:0]$6753 + attribute \src "libresoc.v:134342.3-134352.6" + wire $0\xer_ca_ok[0:0] + attribute \src "libresoc.v:134367.3-134377.6" + wire width 2 $0\xer_ov[1:0] + attribute \src "libresoc.v:134378.3-134388.6" + wire $0\xer_ov_ok[0:0] + attribute \src "libresoc.v:134093.3-134103.6" + wire $0\zerohi[0:0] + attribute \src "libresoc.v:134483.3-134493.6" + wire $0\zerolo[0:0] + attribute \src "libresoc.v:134070.3-134092.6" + wire width 64 $1\a_i[63:0] + attribute \src "libresoc.v:134169.3-134195.6" + wire $1\a_lt[0:0] + attribute \src "libresoc.v:134450.3-134460.6" + wire width 64 $1\a_n[63:0] + attribute \src "libresoc.v:134420.3-134429.6" + wire width 66 $1\add_a[65:0] + attribute \src "libresoc.v:134430.3-134439.6" + wire width 66 $1\add_b[65:0] + attribute \src "libresoc.v:134440.3-134449.6" + wire width 66 $1\add_o[65:0] + attribute \src "libresoc.v:134308.3-134330.6" + wire width 64 $1\b_i[63:0] + attribute \src "libresoc.v:134294.3-134307.6" + wire width 2 $1\ca[1:0] + attribute \src "libresoc.v:134461.3-134471.6" + wire $1\carry_32[0:0] + attribute \src "libresoc.v:134472.3-134482.6" + wire $1\carry_64[0:0] + attribute \src "libresoc.v:134196.3-134221.6" + wire width 4 $1\cr_a[3:0] + attribute \src "libresoc.v:134222.3-134236.6" + wire $1\cr_a_ok[0:0] + attribute \src "libresoc.v:134400.3-134419.6" + wire width 8 $1\eqs[7:0] + attribute \src "libresoc.v:134060.3-134069.6" + wire $1\is_32bit[0:0] + attribute \src "libresoc.v:134131.3-134149.6" + wire $1\msb_a[0:0] + attribute \src "libresoc.v:134150.3-134168.6" + wire $1\msb_b[0:0] + attribute \src "libresoc.v:134237.3-134274.6" + wire width 64 $1\o[63:0] + attribute \src "libresoc.v:134275.3-134293.6" + wire $1\o_ok[0:0] + attribute \src "libresoc.v:134353.3-134366.6" + wire width 2 $1\ov[1:0] + attribute \src "libresoc.v:134389.3-134399.6" + wire width 8 $1\src1[7:0] + attribute \src "libresoc.v:134104.3-134130.6" + wire width 5 $1\tval[4:0] + attribute \src "libresoc.v:134331.3-134341.6" + wire width 2 $1\xer_ca$20[1:0]$6754 + attribute \src "libresoc.v:134342.3-134352.6" + wire $1\xer_ca_ok[0:0] + attribute \src "libresoc.v:134367.3-134377.6" + wire width 2 $1\xer_ov[1:0] + attribute \src "libresoc.v:134378.3-134388.6" + wire $1\xer_ov_ok[0:0] + attribute \src "libresoc.v:134093.3-134103.6" + wire $1\zerohi[0:0] + attribute \src "libresoc.v:134483.3-134493.6" + wire $1\zerolo[0:0] + attribute \src "libresoc.v:134070.3-134092.6" + wire width 64 $2\a_i[63:0] + attribute \src "libresoc.v:134169.3-134195.6" + wire $2\a_lt[0:0] + attribute \src "libresoc.v:134308.3-134330.6" + wire width 64 $2\b_i[63:0] + attribute \src "libresoc.v:134196.3-134221.6" + wire width 2 $2\cr_a[3:2] + attribute \src "libresoc.v:134131.3-134149.6" + wire $2\msb_a[0:0] + attribute \src "libresoc.v:134150.3-134168.6" + wire $2\msb_b[0:0] + attribute \src "libresoc.v:134237.3-134274.6" + wire width 64 $2\o[63:0] + attribute \src "libresoc.v:134104.3-134130.6" + wire width 5 $2\tval[4:0] + attribute \src "libresoc.v:134169.3-134195.6" + wire $3\a_lt[0:0] + attribute \src "libresoc.v:134237.3-134274.6" + wire width 64 $3\o[63:0] + attribute \src "libresoc.v:134104.3-134130.6" + wire width 5 $3\tval[4:0] + attribute \src "libresoc.v:134237.3-134274.6" + wire width 64 $4\o[63:0] + attribute \src "libresoc.v:134035.18-134035.105" + wire width 67 $add$libresoc.v:134035$6714_Y + attribute \src "libresoc.v:134009.19-134009.107" + wire $and$libresoc.v:134009$6688_Y + attribute \src "libresoc.v:134013.19-134013.107" + wire $and$libresoc.v:134013$6692_Y + attribute \src "libresoc.v:134046.18-134046.106" + wire $and$libresoc.v:134046$6725_Y + attribute \src "libresoc.v:134051.18-134051.106" + wire $and$libresoc.v:134051$6730_Y + attribute \src "libresoc.v:134054.18-134054.106" + wire $and$libresoc.v:134054$6733_Y + attribute \src "libresoc.v:134057.18-134057.106" + wire $and$libresoc.v:134057$6736_Y + attribute \src "libresoc.v:134000.19-134000.118" + wire $eq$libresoc.v:134000$6679_Y + attribute \src "libresoc.v:134001.19-134001.118" + wire $eq$libresoc.v:134001$6680_Y + attribute \src "libresoc.v:134002.19-134002.118" + wire $eq$libresoc.v:134002$6681_Y + attribute \src "libresoc.v:134014.19-134014.109" + wire $eq$libresoc.v:134014$6693_Y + attribute \src "libresoc.v:134015.19-134015.110" + wire $eq$libresoc.v:134015$6694_Y + attribute \src "libresoc.v:134016.19-134016.111" + wire $eq$libresoc.v:134016$6695_Y + attribute \src "libresoc.v:134017.19-134017.111" + wire $eq$libresoc.v:134017$6696_Y + attribute \src "libresoc.v:134018.19-134018.111" + wire $eq$libresoc.v:134018$6697_Y + attribute \src "libresoc.v:134019.19-134019.111" + wire $eq$libresoc.v:134019$6698_Y + attribute \src "libresoc.v:134020.19-134020.111" + wire $eq$libresoc.v:134020$6699_Y + attribute \src "libresoc.v:134021.19-134021.111" + wire $eq$libresoc.v:134021$6700_Y + attribute \src "libresoc.v:134022.18-134022.118" + wire $eq$libresoc.v:134022$6701_Y + attribute \src "libresoc.v:134024.18-134024.118" + wire $eq$libresoc.v:134024$6703_Y + attribute \src "libresoc.v:134025.18-134025.118" + wire $eq$libresoc.v:134025$6704_Y + attribute \src "libresoc.v:134026.18-134026.118" + wire $eq$libresoc.v:134026$6705_Y + attribute \src "libresoc.v:134027.18-134027.118" + wire $eq$libresoc.v:134027$6706_Y + attribute \src "libresoc.v:134029.18-134029.118" + wire $eq$libresoc.v:134029$6708_Y + attribute \src "libresoc.v:134030.18-134030.118" + wire $eq$libresoc.v:134030$6709_Y + attribute \src "libresoc.v:134032.18-134032.118" + wire $eq$libresoc.v:134032$6711_Y + attribute \src "libresoc.v:134033.18-134033.118" + wire $eq$libresoc.v:134033$6712_Y + attribute \src "libresoc.v:134047.18-134047.107" + wire $ne$libresoc.v:134047$6726_Y + attribute \src "libresoc.v:134058.18-134058.107" + wire $ne$libresoc.v:134058$6737_Y + attribute \src "libresoc.v:134008.19-134008.100" + wire $not$libresoc.v:134008$6687_Y + attribute \src "libresoc.v:134012.19-134012.100" + wire $not$libresoc.v:134012$6691_Y + attribute \src "libresoc.v:134023.18-134023.110" + wire $not$libresoc.v:134023$6702_Y + attribute \src "libresoc.v:134036.18-134036.97" + wire width 64 $not$libresoc.v:134036$6715_Y + attribute \src "libresoc.v:134041.18-134041.99" + wire $not$libresoc.v:134041$6720_Y + attribute \src "libresoc.v:134044.18-134044.99" + wire $not$libresoc.v:134044$6723_Y + attribute \src "libresoc.v:134048.18-134048.99" + wire $not$libresoc.v:134048$6727_Y + attribute \src "libresoc.v:134049.18-134049.99" + wire $not$libresoc.v:134049$6728_Y + attribute \src "libresoc.v:134028.18-134028.104" + wire $or$libresoc.v:134028$6707_Y + attribute \src "libresoc.v:134031.18-134031.104" + wire $or$libresoc.v:134031$6710_Y + attribute \src "libresoc.v:134034.18-134034.104" + wire $or$libresoc.v:134034$6713_Y + attribute \src "libresoc.v:134045.18-134045.110" + wire $or$libresoc.v:134045$6724_Y + attribute \src "libresoc.v:134050.18-134050.110" + wire $or$libresoc.v:134050$6729_Y + attribute \src "libresoc.v:134053.18-134053.110" + wire $or$libresoc.v:134053$6732_Y + attribute \src "libresoc.v:134056.18-134056.110" + wire $or$libresoc.v:134056$6735_Y + attribute \src "libresoc.v:133999.18-133999.98" + wire $reduce_or$libresoc.v:133999$6678_Y + attribute \src "libresoc.v:134003.19-134003.99" + wire $reduce_or$libresoc.v:134003$6682_Y + attribute \src "libresoc.v:134040.18-134040.99" + wire $reduce_or$libresoc.v:134040$6719_Y + attribute \src "libresoc.v:134043.18-134043.99" + wire $reduce_or$libresoc.v:134043$6722_Y + attribute \src "libresoc.v:134052.18-134052.121" + wire $ternary$libresoc.v:134052$6731_Y + attribute \src "libresoc.v:134055.18-134055.119" + wire $ternary$libresoc.v:134055$6734_Y + attribute \src "libresoc.v:134059.18-134059.123" + wire $ternary$libresoc.v:134059$6738_Y + attribute \src "libresoc.v:134004.19-134004.111" + wire $xor$libresoc.v:134004$6683_Y + attribute \src "libresoc.v:134005.19-134005.111" + wire $xor$libresoc.v:134005$6684_Y + attribute \src "libresoc.v:134006.19-134006.110" + wire $xor$libresoc.v:134006$6685_Y + attribute \src "libresoc.v:134007.19-134007.110" + wire $xor$libresoc.v:134007$6686_Y + attribute \src "libresoc.v:134010.19-134010.110" + wire $xor$libresoc.v:134010$6689_Y + attribute \src "libresoc.v:134011.19-134011.110" + wire $xor$libresoc.v:134011$6690_Y + attribute \src "libresoc.v:134037.18-134037.111" + wire $xor$libresoc.v:134037$6716_Y + attribute \src "libresoc.v:134038.18-134038.107" + wire $xor$libresoc.v:134038$6717_Y + attribute \src "libresoc.v:134039.18-134039.113" + wire width 32 $xor$libresoc.v:134039$6718_Y + attribute \src "libresoc.v:134042.18-134042.115" + wire width 32 $xor$libresoc.v:134042$6721_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:162" + wire \$101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:164" + wire \$103 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:166" + wire \$105 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:179" + wire \$107 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:148" + wire \$109 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:148" + wire \$111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:21" + wire \$113 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:21" + wire \$115 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:21" + wire \$116 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:21" + wire \$119 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:21" + wire \$121 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:21" + wire \$123 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:21" + wire \$124 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:21" + wire \$127 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:178" + wire \$129 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:178" + wire \$131 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:178" + wire \$133 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:178" + wire \$135 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:178" + wire \$137 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:178" + wire \$139 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:178" + wire \$141 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:178" + wire \$143 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:52" + wire \$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:53" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:63" + wire \$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:63" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:77" + wire \$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:78" + wire \$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:78" + wire \$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:77" + wire \$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:78" + wire \$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:78" + wire \$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:77" + wire \$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:78" + wire \$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:78" + wire \$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" + wire width 67 \$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" + wire width 67 \$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:105" + wire width 64 \$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:106" + wire \$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:106" + wire \$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:109" + wire \$57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:109" + wire \$58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:109" + wire width 32 \$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:110" + wire \$63 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:110" + wire \$64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:110" + wire width 32 \$65 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:112" + wire \$69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:112" + wire \$71 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:119" + wire \$73 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:128" + wire \$75 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:128" + wire \$77 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:112" + wire \$79 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:112" + wire \$81 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" + wire \$83 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:112" + wire \$85 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:112" + wire \$87 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:117" + wire \$89 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:112" + wire \$91 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:112" + wire \$93 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:119" + wire \$95 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:127" + wire \$97 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:181" + wire \$99 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:61" + wire width 64 \a_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:95" + wire \a_lt + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:93" + wire width 64 \a_n + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:57" + wire width 66 \add_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:58" + wire width 66 \add_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:59" + wire width 66 \add_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 17 \alu_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 40 \alu_op__data_len$18 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 2 \alu_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 output 25 \alu_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 3 \alu_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 26 \alu_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 4 \alu_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 27 \alu_op__imm_data__ok$5 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 13 \alu_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 36 \alu_op__input_carry$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 18 \alu_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 41 \alu_op__insn$19 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \alu_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 24 \alu_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \alu_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 32 \alu_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 11 \alu_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 34 \alu_op__invert_out$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 15 \alu_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 38 \alu_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 16 \alu_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 39 \alu_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 7 \alu_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 30 \alu_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \alu_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 31 \alu_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \alu_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 37 \alu_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 6 \alu_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 29 \alu_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 5 \alu_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 28 \alu_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \alu_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 35 \alu_op__write_cr0$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \alu_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 33 \alu_op__zero_a$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:62" + wire width 64 \b_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:146" + wire width 2 \ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:96" + wire \carry_32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:97" + wire \carry_64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 output 44 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 45 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:174" + wire width 8 \eqs + attribute \src "libresoc.v:133544.7-133544.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:50" + wire \is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:100" + wire \msb_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:101" + wire \msb_b + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 51 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 23 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 42 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 43 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:152" + wire width 2 \ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 19 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 20 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:175" + wire width 8 \src1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:94" + wire width 5 \tval + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 input 22 \xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 output 46 \xer_ca$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 47 \xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 output 48 \xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 49 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 21 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 50 \xer_so$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:99" + wire \zerohi + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:98" + wire \zerolo + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" + cell $add $add$libresoc.v:134035$6714 + parameter \A_SIGNED 0 + parameter \A_WIDTH 66 + parameter \B_SIGNED 0 + parameter \B_WIDTH 66 + parameter \Y_WIDTH 67 + connect \A \add_a + connect \B \add_b + connect \Y $add$libresoc.v:134035$6714_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:21" + cell $and $and$libresoc.v:134009$6688 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$113 + connect \B \$115 + connect \Y $and$libresoc.v:134009$6688_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:21" + cell $and $and$libresoc.v:134013$6692 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$121 + connect \B \$123 + connect \Y $and$libresoc.v:134013$6692_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:112" + cell $and $and$libresoc.v:134046$6725 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \zerolo + connect \B \$69 + connect \Y $and$libresoc.v:134046$6725_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:112" + cell $and $and$libresoc.v:134051$6730 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \zerolo + connect \B \$79 + connect \Y $and$libresoc.v:134051$6730_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:112" + cell $and $and$libresoc.v:134054$6733 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \zerolo + connect \B \$85 + connect \Y $and$libresoc.v:134054$6733_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:112" + cell $and $and$libresoc.v:134057$6736 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \zerolo + connect \B \$91 + connect \Y $and$libresoc.v:134057$6736_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:162" + cell $eq $eq$libresoc.v:134000$6679 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_op__data_len + connect \B 1'1 + connect \Y $eq$libresoc.v:134000$6679_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:164" + cell $eq $eq$libresoc.v:134001$6680 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \alu_op__data_len + connect \B 2'10 + connect \Y $eq$libresoc.v:134001$6680_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:166" + cell $eq $eq$libresoc.v:134002$6681 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \alu_op__data_len + connect \B 3'100 + connect \Y $eq$libresoc.v:134002$6681_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:178" + cell $eq $eq$libresoc.v:134014$6693 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \src1 + connect \B \rb [7:0] + connect \Y $eq$libresoc.v:134014$6693_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:178" + cell $eq $eq$libresoc.v:134015$6694 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \src1 + connect \B \rb [15:8] + connect \Y $eq$libresoc.v:134015$6694_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:178" + cell $eq $eq$libresoc.v:134016$6695 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \src1 + connect \B \rb [23:16] + connect \Y $eq$libresoc.v:134016$6695_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:178" + cell $eq $eq$libresoc.v:134017$6696 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \src1 + connect \B \rb [31:24] + connect \Y $eq$libresoc.v:134017$6696_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:178" + cell $eq $eq$libresoc.v:134018$6697 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \src1 + connect \B \rb [39:32] + connect \Y $eq$libresoc.v:134018$6697_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:178" + cell $eq $eq$libresoc.v:134019$6698 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \src1 + connect \B \rb [47:40] + connect \Y $eq$libresoc.v:134019$6698_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:178" + cell $eq $eq$libresoc.v:134020$6699 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \src1 + connect \B \rb [55:48] + connect \Y $eq$libresoc.v:134020$6699_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:178" + cell $eq $eq$libresoc.v:134021$6700 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \src1 + connect \B \rb [63:56] + connect \Y $eq$libresoc.v:134021$6700_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:52" + cell $eq $eq$libresoc.v:134022$6701 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \alu_op__insn_type + connect \B 7'0001010 + connect \Y $eq$libresoc.v:134022$6701_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:63" + cell $eq $eq$libresoc.v:134024$6703 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \alu_op__insn_type + connect \B 7'0001010 + connect \Y $eq$libresoc.v:134024$6703_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:63" + cell $eq $eq$libresoc.v:134025$6704 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \alu_op__insn_type + connect \B 7'0001010 + connect \Y $eq$libresoc.v:134025$6704_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:77" + cell $eq $eq$libresoc.v:134026$6705 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \alu_op__insn_type + connect \B 7'0000010 + connect \Y $eq$libresoc.v:134026$6705_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:78" + cell $eq $eq$libresoc.v:134027$6706 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \alu_op__insn_type + connect \B 7'0001010 + connect \Y $eq$libresoc.v:134027$6706_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:77" + cell $eq $eq$libresoc.v:134029$6708 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \alu_op__insn_type + connect \B 7'0000010 + connect \Y $eq$libresoc.v:134029$6708_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:78" + cell $eq $eq$libresoc.v:134030$6709 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \alu_op__insn_type + connect \B 7'0001010 + connect \Y $eq$libresoc.v:134030$6709_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:77" + cell $eq $eq$libresoc.v:134032$6711 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \alu_op__insn_type + connect \B 7'0000010 + connect \Y $eq$libresoc.v:134032$6711_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:78" + cell $eq $eq$libresoc.v:134033$6712 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \alu_op__insn_type + connect \B 7'0001010 + connect \Y $eq$libresoc.v:134033$6712_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:119" + cell $ne $ne$libresoc.v:134047$6726 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \msb_a + connect \B \msb_b + connect \Y $ne$libresoc.v:134047$6726_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:119" + cell $ne $ne$libresoc.v:134058$6737 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \msb_a + connect \B \msb_b + connect \Y $ne$libresoc.v:134058$6737_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:21" + cell $not $not$libresoc.v:134008$6687 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$116 + connect \Y $not$libresoc.v:134008$6687_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:21" + cell $not $not$libresoc.v:134012$6691 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$124 + connect \Y $not$libresoc.v:134012$6691_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:53" + cell $not $not$libresoc.v:134023$6702 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_op__insn [21] + connect \Y $not$libresoc.v:134023$6702_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:105" + cell $not $not$libresoc.v:134036$6715 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \ra + connect \Y $not$libresoc.v:134036$6715_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:109" + cell $not $not$libresoc.v:134041$6720 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$58 + connect \Y $not$libresoc.v:134041$6720_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:110" + cell $not $not$libresoc.v:134044$6723 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$64 + connect \Y $not$libresoc.v:134044$6723_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:128" + cell $not $not$libresoc.v:134048$6727 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \a_lt + connect \Y $not$libresoc.v:134048$6727_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:128" + cell $not $not$libresoc.v:134049$6728 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \a_lt + connect \Y $not$libresoc.v:134049$6728_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:78" + cell $or $or$libresoc.v:134028$6707 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$30 + connect \B \$32 + connect \Y $or$libresoc.v:134028$6707_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:78" + cell $or $or$libresoc.v:134031$6710 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$36 + connect \B \$38 + connect \Y $or$libresoc.v:134031$6710_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:78" + cell $or $or$libresoc.v:134034$6713 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$42 + connect \B \$44 + connect \Y $or$libresoc.v:134034$6713_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:112" + cell $or $or$libresoc.v:134045$6724 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_32bit + connect \B \zerohi + connect \Y $or$libresoc.v:134045$6724_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:112" + cell $or $or$libresoc.v:134050$6729 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_32bit + connect \B \zerohi + connect \Y $or$libresoc.v:134050$6729_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:112" + cell $or $or$libresoc.v:134053$6732 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_32bit + connect \B \zerohi + connect \Y $or$libresoc.v:134053$6732_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:112" + cell $or $or$libresoc.v:134056$6735 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_32bit + connect \B \zerohi + connect \Y $or$libresoc.v:134056$6735_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:181" + cell $reduce_or $reduce_or$libresoc.v:133999$6678 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \eqs + connect \Y $reduce_or$libresoc.v:133999$6678_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:179" + cell $reduce_or $reduce_or$libresoc.v:134003$6682 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \eqs + connect \Y $reduce_or$libresoc.v:134003$6682_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:109" + cell $reduce_or $reduce_or$libresoc.v:134040$6719 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \Y_WIDTH 1 + connect \A \$59 + connect \Y $reduce_or$libresoc.v:134040$6719_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:110" + cell $reduce_or $reduce_or$libresoc.v:134043$6722 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \Y_WIDTH 1 + connect \A \$65 + connect \Y $reduce_or$libresoc.v:134043$6722_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" + cell $mux $ternary$libresoc.v:134052$6731 + parameter \WIDTH 1 + connect \A \a_n [63] + connect \B \a_n [31] + connect \S \is_32bit + connect \Y $ternary$libresoc.v:134052$6731_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:117" + cell $mux $ternary$libresoc.v:134055$6734 + parameter \WIDTH 1 + connect \A \rb [63] + connect \B \rb [31] + connect \S \is_32bit + connect \Y $ternary$libresoc.v:134055$6734_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:127" + cell $mux $ternary$libresoc.v:134059$6738 + parameter \WIDTH 1 + connect \A \carry_64 + connect \B \carry_32 + connect \S \is_32bit + connect \Y $ternary$libresoc.v:134059$6738_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:148" + cell $xor $xor$libresoc.v:134004$6683 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \a_i [32] + connect \B \b_i [32] + connect \Y $xor$libresoc.v:134004$6683_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:148" + cell $xor $xor$libresoc.v:134005$6684 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \add_o [33] + connect \B \$109 + connect \Y $xor$libresoc.v:134005$6684_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:21" + cell $xor $xor$libresoc.v:134006$6685 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ca [0] + connect \B \add_o [64] + connect \Y $xor$libresoc.v:134006$6685_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:21" + cell $xor $xor$libresoc.v:134007$6686 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \a_i [63] + connect \B \b_i [63] + connect \Y $xor$libresoc.v:134007$6686_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:21" + cell $xor $xor$libresoc.v:134010$6689 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ca [1] + connect \B \add_o [32] + connect \Y $xor$libresoc.v:134010$6689_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:21" + cell $xor $xor$libresoc.v:134011$6690 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \a_i [31] + connect \B \b_i [31] + connect \Y $xor$libresoc.v:134011$6690_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:106" + cell $xor $xor$libresoc.v:134037$6716 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \add_o [33] + connect \B \ra [32] + connect \Y $xor$libresoc.v:134037$6716_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:106" + cell $xor $xor$libresoc.v:134038$6717 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$53 + connect \B \rb [32] + connect \Y $xor$libresoc.v:134038$6717_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:109" + cell $xor $xor$libresoc.v:134039$6718 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A \a_n [31:0] + connect \B \rb [31:0] + connect \Y $xor$libresoc.v:134039$6718_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:110" + cell $xor $xor$libresoc.v:134042$6721 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A \a_n [63:32] + connect \B \rb [63:32] + connect \Y $xor$libresoc.v:134042$6721_Y + end + attribute \src "libresoc.v:133544.7-133544.20" + process $proc$libresoc.v:133544$6768 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:134060.3-134069.6" + process $proc$libresoc.v:134060$6739 + assign { } { } + assign { } { } + assign $0\is_32bit[0:0] $1\is_32bit[0:0] + attribute \src "libresoc.v:134061.5-134061.29" + switch \initial + attribute \src "libresoc.v:134061.9-134061.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:52" + switch \$22 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\is_32bit[0:0] \$24 + case + assign $1\is_32bit[0:0] 1'0 + end + sync always + update \is_32bit $0\is_32bit[0:0] + end + attribute \src "libresoc.v:134070.3-134092.6" + process $proc$libresoc.v:134070$6740 + assign { } { } + assign $0\a_i[63:0] $1\a_i[63:0] + attribute \src "libresoc.v:134071.5-134071.29" + switch \initial + attribute \src "libresoc.v:134071.9-134071.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:63" + switch { \is_32bit \$26 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\a_i[63:0] \ra + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\a_i[63:0] $2\a_i[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:67" + switch \alu_op__is_signed + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\a_i[63:0] { \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31:0] } + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\a_i[63:0] { 32'00000000000000000000000000000000 \ra [31:0] } + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\a_i[63:0] \ra + end + sync always + update \a_i $0\a_i[63:0] + end + attribute \src "libresoc.v:134093.3-134103.6" + process $proc$libresoc.v:134093$6741 + assign { } { } + assign { } { } + assign $0\zerohi[0:0] $1\zerohi[0:0] + attribute \src "libresoc.v:134094.5-134094.29" + switch \initial + attribute \src "libresoc.v:134094.9-134094.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:87" + switch \alu_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0001010 + assign { } { } + assign $1\zerohi[0:0] \$63 + case + assign $1\zerohi[0:0] 1'0 + end + sync always + update \zerohi $0\zerohi[0:0] + end + attribute \src "libresoc.v:134104.3-134130.6" + process $proc$libresoc.v:134104$6742 + assign { } { } + assign { } { } + assign $0\tval[4:0] $1\tval[4:0] + attribute \src "libresoc.v:134105.5-134105.29" + switch \initial + attribute \src "libresoc.v:134105.9-134105.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:87" + switch \alu_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0001010 + assign { } { } + assign $1\tval[4:0] $2\tval[4:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:112" + switch \$71 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { $2\tval[4:0] [4:3] $2\tval[4:0] [1:0] } 4'0000 + assign $2\tval[4:0] [2] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\tval[4:0] $3\tval[4:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:119" + switch \$73 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\tval[4:0] { \msb_a \msb_b 1'0 \msb_b \msb_a } + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $3\tval[4:0] { \a_lt \$77 1'0 \a_lt \$75 } + end + end + case + assign $1\tval[4:0] 5'00000 + end + sync always + update \tval $0\tval[4:0] + end + attribute \src "libresoc.v:134131.3-134149.6" + process $proc$libresoc.v:134131$6743 + assign { } { } + assign { } { } + assign $0\msb_a[0:0] $1\msb_a[0:0] + attribute \src "libresoc.v:134132.5-134132.29" + switch \initial + attribute \src "libresoc.v:134132.9-134132.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:87" + switch \alu_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0001010 + assign { } { } + assign $1\msb_a[0:0] $2\msb_a[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:112" + switch \$81 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $2\msb_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\msb_a[0:0] \$83 + end + case + assign $1\msb_a[0:0] 1'0 + end + sync always + update \msb_a $0\msb_a[0:0] + end + attribute \src "libresoc.v:134150.3-134168.6" + process $proc$libresoc.v:134150$6744 + assign { } { } + assign { } { } + assign $0\msb_b[0:0] $1\msb_b[0:0] + attribute \src "libresoc.v:134151.5-134151.29" + switch \initial + attribute \src "libresoc.v:134151.9-134151.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:87" + switch \alu_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0001010 + assign { } { } + assign $1\msb_b[0:0] $2\msb_b[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:112" + switch \$87 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $2\msb_b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\msb_b[0:0] \$89 + end + case + assign $1\msb_b[0:0] 1'0 + end + sync always + update \msb_b $0\msb_b[0:0] + end + attribute \src "libresoc.v:134169.3-134195.6" + process $proc$libresoc.v:134169$6745 + assign { } { } + assign { } { } + assign $0\a_lt[0:0] $1\a_lt[0:0] + attribute \src "libresoc.v:134170.5-134170.29" + switch \initial + attribute \src "libresoc.v:134170.9-134170.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:87" + switch \alu_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0001010 + assign { } { } + assign $1\a_lt[0:0] $2\a_lt[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:112" + switch \$93 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $2\a_lt[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\a_lt[0:0] $3\a_lt[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:119" + switch \$95 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $3\a_lt[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $3\a_lt[0:0] \$97 + end + end + case + assign $1\a_lt[0:0] 1'0 + end + sync always + update \a_lt $0\a_lt[0:0] + end + attribute \src "libresoc.v:134196.3-134221.6" + process $proc$libresoc.v:134196$6746 + assign { } { } + assign { } { } + assign $0\cr_a[3:0] $1\cr_a[3:0] + attribute \src "libresoc.v:134197.5-134197.29" + switch \initial + attribute \src "libresoc.v:134197.9-134197.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:87" + switch \alu_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0001010 + assign { } { } + assign $1\cr_a[3:0] [1:0] { \tval [2] \xer_so } + assign $1\cr_a[3:0] [3:2] $2\cr_a[3:2] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:130" + switch \alu_op__is_signed + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_a[3:2] \tval [4:3] + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cr_a[3:2] \tval [1:0] + end + attribute \src "libresoc.v:0.0-0.0" + case 7'0001100 + assign { } { } + assign $1\cr_a[3:0] { 1'0 \$99 2'00 } + case + assign $1\cr_a[3:0] 4'0000 + end + sync always + update \cr_a $0\cr_a[3:0] + end + attribute \src "libresoc.v:134222.3-134236.6" + process $proc$libresoc.v:134222$6747 + assign { } { } + assign { } { } + assign $0\cr_a_ok[0:0] $1\cr_a_ok[0:0] + attribute \src "libresoc.v:134223.5-134223.29" + switch \initial + attribute \src "libresoc.v:134223.9-134223.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:87" + switch \alu_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0001010 + assign { } { } + assign $1\cr_a_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 7'0001100 + assign { } { } + assign $1\cr_a_ok[0:0] 1'1 + case + assign $1\cr_a_ok[0:0] 1'0 + end + sync always + update \cr_a_ok $0\cr_a_ok[0:0] + end + attribute \src "libresoc.v:134237.3-134274.6" + process $proc$libresoc.v:134237$6748 + assign { } { } + assign { } { } + assign $0\o[63:0] $1\o[63:0] + attribute \src "libresoc.v:134238.5-134238.29" + switch \initial + attribute \src "libresoc.v:134238.9-134238.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:87" + switch \alu_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000010 + assign { } { } + assign $1\o[63:0] \add_o [64:1] + attribute \src "libresoc.v:0.0-0.0" + case 7'0011111 + assign { } { } + assign { } { } + assign { } { } + assign $1\o[63:0] $4\o[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:162" + switch \$101 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\o[63:0] { \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7:0] } + case + assign $2\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:164" + switch \$103 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\o[63:0] { \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15:0] } + case + assign $3\o[63:0] $2\o[63:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:166" + switch \$105 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\o[63:0] { \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31:0] } + case + assign $4\o[63:0] $3\o[63:0] + end + attribute \src "libresoc.v:0.0-0.0" + case 7'0001100 + assign $1\o[63:0] [63:1] 63'000000000000000000000000000000000000000000000000000000000000000 + assign $1\o[63:0] [0] \$107 + case + assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \o $0\o[63:0] + end + attribute \src "libresoc.v:134275.3-134293.6" + process $proc$libresoc.v:134275$6749 + assign { } { } + assign { } { } + assign $0\o_ok[0:0] $1\o_ok[0:0] + attribute \src "libresoc.v:134276.5-134276.29" + switch \initial + attribute \src "libresoc.v:134276.9-134276.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:87" + switch \alu_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000010 + assign { } { } + assign $1\o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 7'0011111 + assign { } { } + assign $1\o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 7'0001100 + assign { } { } + assign $1\o_ok[0:0] 1'0 + case + assign $1\o_ok[0:0] 1'0 + end + sync always + update \o_ok $0\o_ok[0:0] + end + attribute \src "libresoc.v:134294.3-134307.6" + process $proc$libresoc.v:134294$6750 + assign { } { } + assign { } { } + assign $0\ca[1:0] $1\ca[1:0] + attribute \src "libresoc.v:134295.5-134295.29" + switch \initial + attribute \src "libresoc.v:134295.9-134295.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:87" + switch \alu_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000010 + assign { } { } + assign $1\ca[1:0] [0] \add_o [65] + assign $1\ca[1:0] [1] \$111 + case + assign $1\ca[1:0] 2'00 + end + sync always + update \ca $0\ca[1:0] + end + attribute \src "libresoc.v:134308.3-134330.6" + process $proc$libresoc.v:134308$6751 + assign { } { } + assign $0\b_i[63:0] $1\b_i[63:0] + attribute \src "libresoc.v:134309.5-134309.29" + switch \initial + attribute \src "libresoc.v:134309.9-134309.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:63" + switch { \is_32bit \$28 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\b_i[63:0] \rb + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\b_i[63:0] $2\b_i[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:67" + switch \alu_op__is_signed + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\b_i[63:0] { \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31:0] } + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\b_i[63:0] { 32'00000000000000000000000000000000 \rb [31:0] } + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\b_i[63:0] \rb + end + sync always + update \b_i $0\b_i[63:0] + end + attribute \src "libresoc.v:134331.3-134341.6" + process $proc$libresoc.v:134331$6752 + assign { } { } + assign { } { } + assign $0\xer_ca$20[1:0]$6753 $1\xer_ca$20[1:0]$6754 + attribute \src "libresoc.v:134332.5-134332.29" + switch \initial + attribute \src "libresoc.v:134332.9-134332.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:87" + switch \alu_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000010 + assign { } { } + assign $1\xer_ca$20[1:0]$6754 \ca + case + assign $1\xer_ca$20[1:0]$6754 2'00 + end + sync always + update \xer_ca$20 $0\xer_ca$20[1:0]$6753 + end + attribute \src "libresoc.v:134342.3-134352.6" + process $proc$libresoc.v:134342$6755 + assign { } { } + assign { } { } + assign $0\xer_ca_ok[0:0] $1\xer_ca_ok[0:0] + attribute \src "libresoc.v:134343.5-134343.29" + switch \initial + attribute \src "libresoc.v:134343.9-134343.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:87" + switch \alu_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000010 + assign { } { } + assign $1\xer_ca_ok[0:0] 1'1 + case + assign $1\xer_ca_ok[0:0] 1'0 + end + sync always + update \xer_ca_ok $0\xer_ca_ok[0:0] + end + attribute \src "libresoc.v:134353.3-134366.6" + process $proc$libresoc.v:134353$6756 + assign { } { } + assign { } { } + assign $0\ov[1:0] $1\ov[1:0] + attribute \src "libresoc.v:134354.5-134354.29" + switch \initial + attribute \src "libresoc.v:134354.9-134354.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:87" + switch \alu_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000010 + assign { } { } + assign $1\ov[1:0] [0] \$119 + assign $1\ov[1:0] [1] \$127 + case + assign $1\ov[1:0] 2'00 + end + sync always + update \ov $0\ov[1:0] + end + attribute \src "libresoc.v:134367.3-134377.6" + process $proc$libresoc.v:134367$6757 + assign { } { } + assign { } { } + assign $0\xer_ov[1:0] $1\xer_ov[1:0] + attribute \src "libresoc.v:134368.5-134368.29" + switch \initial + attribute \src "libresoc.v:134368.9-134368.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:87" + switch \alu_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000010 + assign { } { } + assign $1\xer_ov[1:0] \ov + case + assign $1\xer_ov[1:0] 2'00 + end + sync always + update \xer_ov $0\xer_ov[1:0] + end + attribute \src "libresoc.v:134378.3-134388.6" + process $proc$libresoc.v:134378$6758 + assign { } { } + assign { } { } + assign $0\xer_ov_ok[0:0] $1\xer_ov_ok[0:0] + attribute \src "libresoc.v:134379.5-134379.29" + switch \initial + attribute \src "libresoc.v:134379.9-134379.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:87" + switch \alu_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000010 + assign { } { } + assign $1\xer_ov_ok[0:0] 1'1 + case + assign $1\xer_ov_ok[0:0] 1'0 + end + sync always + update \xer_ov_ok $0\xer_ov_ok[0:0] + end + attribute \src "libresoc.v:134389.3-134399.6" + process $proc$libresoc.v:134389$6759 + assign { } { } + assign { } { } + assign $0\src1[7:0] $1\src1[7:0] + attribute \src "libresoc.v:134390.5-134390.29" + switch \initial + attribute \src "libresoc.v:134390.9-134390.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:87" + switch \alu_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0001100 + assign { } { } + assign $1\src1[7:0] \ra [7:0] + case + assign $1\src1[7:0] 8'00000000 + end + sync always + update \src1 $0\src1[7:0] + end + attribute \src "libresoc.v:134400.3-134419.6" + process $proc$libresoc.v:134400$6760 + assign { } { } + assign { } { } + assign $0\eqs[7:0] $1\eqs[7:0] + attribute \src "libresoc.v:134401.5-134401.29" + switch \initial + attribute \src "libresoc.v:134401.9-134401.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:87" + switch \alu_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0001100 + assign { } { } + assign $1\eqs[7:0] [0] \$129 + assign $1\eqs[7:0] [1] \$131 + assign $1\eqs[7:0] [2] \$133 + assign $1\eqs[7:0] [3] \$135 + assign $1\eqs[7:0] [4] \$137 + assign $1\eqs[7:0] [5] \$139 + assign $1\eqs[7:0] [6] \$141 + assign $1\eqs[7:0] [7] \$143 + case + assign $1\eqs[7:0] 8'00000000 + end + sync always + update \eqs $0\eqs[7:0] + end + attribute \src "libresoc.v:134420.3-134429.6" + process $proc$libresoc.v:134420$6761 + assign { } { } + assign { } { } + assign $0\add_a[65:0] $1\add_a[65:0] + attribute \src "libresoc.v:134421.5-134421.29" + switch \initial + attribute \src "libresoc.v:134421.9-134421.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:78" + switch \$34 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\add_a[65:0] { 1'0 \a_i \xer_ca [0] } + case + assign $1\add_a[65:0] 66'000000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \add_a $0\add_a[65:0] + end + attribute \src "libresoc.v:134430.3-134439.6" + process $proc$libresoc.v:134430$6762 + assign { } { } + assign { } { } + assign $0\add_b[65:0] $1\add_b[65:0] + attribute \src "libresoc.v:134431.5-134431.29" + switch \initial + attribute \src "libresoc.v:134431.9-134431.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:78" + switch \$40 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\add_b[65:0] { 1'0 \b_i 1'1 } + case + assign $1\add_b[65:0] 66'000000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \add_b $0\add_b[65:0] + end + attribute \src "libresoc.v:134440.3-134449.6" + process $proc$libresoc.v:134440$6763 + assign { } { } + assign { } { } + assign $0\add_o[65:0] $1\add_o[65:0] + attribute \src "libresoc.v:134441.5-134441.29" + switch \initial + attribute \src "libresoc.v:134441.9-134441.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:78" + switch \$46 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\add_o[65:0] \$48 [65:0] + case + assign $1\add_o[65:0] 66'000000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \add_o $0\add_o[65:0] + end + attribute \src "libresoc.v:134450.3-134460.6" + process $proc$libresoc.v:134450$6764 + assign { } { } + assign { } { } + assign $0\a_n[63:0] $1\a_n[63:0] + attribute \src "libresoc.v:134451.5-134451.29" + switch \initial + attribute \src "libresoc.v:134451.9-134451.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:87" + switch \alu_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0001010 + assign { } { } + assign $1\a_n[63:0] \$51 + case + assign $1\a_n[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \a_n $0\a_n[63:0] + end + attribute \src "libresoc.v:134461.3-134471.6" + process $proc$libresoc.v:134461$6765 + assign { } { } + assign { } { } + assign $0\carry_32[0:0] $1\carry_32[0:0] + attribute \src "libresoc.v:134462.5-134462.29" + switch \initial + attribute \src "libresoc.v:134462.9-134462.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:87" + switch \alu_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0001010 + assign { } { } + assign $1\carry_32[0:0] \$55 + case + assign $1\carry_32[0:0] 1'0 + end + sync always + update \carry_32 $0\carry_32[0:0] + end + attribute \src "libresoc.v:134472.3-134482.6" + process $proc$libresoc.v:134472$6766 + assign { } { } + assign { } { } + assign $0\carry_64[0:0] $1\carry_64[0:0] + attribute \src "libresoc.v:134473.5-134473.29" + switch \initial + attribute \src "libresoc.v:134473.9-134473.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:87" + switch \alu_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0001010 + assign { } { } + assign $1\carry_64[0:0] \add_o [65] + case + assign $1\carry_64[0:0] 1'0 + end + sync always + update \carry_64 $0\carry_64[0:0] + end + attribute \src "libresoc.v:134483.3-134493.6" + process $proc$libresoc.v:134483$6767 + assign { } { } + assign { } { } + assign $0\zerolo[0:0] $1\zerolo[0:0] + attribute \src "libresoc.v:134484.5-134484.29" + switch \initial + attribute \src "libresoc.v:134484.9-134484.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:87" + switch \alu_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0001010 + assign { } { } + assign $1\zerolo[0:0] \$57 + case + assign $1\zerolo[0:0] 1'0 + end + sync always + update \zerolo $0\zerolo[0:0] + end + connect \$99 $reduce_or$libresoc.v:133999$6678_Y + connect \$101 $eq$libresoc.v:134000$6679_Y + connect \$103 $eq$libresoc.v:134001$6680_Y + connect \$105 $eq$libresoc.v:134002$6681_Y + connect \$107 $reduce_or$libresoc.v:134003$6682_Y + connect \$109 $xor$libresoc.v:134004$6683_Y + connect \$111 $xor$libresoc.v:134005$6684_Y + connect \$113 $xor$libresoc.v:134006$6685_Y + connect \$116 $xor$libresoc.v:134007$6686_Y + connect \$115 $not$libresoc.v:134008$6687_Y + connect \$119 $and$libresoc.v:134009$6688_Y + connect \$121 $xor$libresoc.v:134010$6689_Y + connect \$124 $xor$libresoc.v:134011$6690_Y + connect \$123 $not$libresoc.v:134012$6691_Y + connect \$127 $and$libresoc.v:134013$6692_Y + connect \$129 $eq$libresoc.v:134014$6693_Y + connect \$131 $eq$libresoc.v:134015$6694_Y + connect \$133 $eq$libresoc.v:134016$6695_Y + connect \$135 $eq$libresoc.v:134017$6696_Y + connect \$137 $eq$libresoc.v:134018$6697_Y + connect \$139 $eq$libresoc.v:134019$6698_Y + connect \$141 $eq$libresoc.v:134020$6699_Y + connect \$143 $eq$libresoc.v:134021$6700_Y + connect \$22 $eq$libresoc.v:134022$6701_Y + connect \$24 $not$libresoc.v:134023$6702_Y + connect \$26 $eq$libresoc.v:134024$6703_Y + connect \$28 $eq$libresoc.v:134025$6704_Y + connect \$30 $eq$libresoc.v:134026$6705_Y + connect \$32 $eq$libresoc.v:134027$6706_Y + connect \$34 $or$libresoc.v:134028$6707_Y + connect \$36 $eq$libresoc.v:134029$6708_Y + connect \$38 $eq$libresoc.v:134030$6709_Y + connect \$40 $or$libresoc.v:134031$6710_Y + connect \$42 $eq$libresoc.v:134032$6711_Y + connect \$44 $eq$libresoc.v:134033$6712_Y + connect \$46 $or$libresoc.v:134034$6713_Y + connect \$49 $add$libresoc.v:134035$6714_Y + connect \$51 $not$libresoc.v:134036$6715_Y + connect \$53 $xor$libresoc.v:134037$6716_Y + connect \$55 $xor$libresoc.v:134038$6717_Y + connect \$59 $xor$libresoc.v:134039$6718_Y + connect \$58 $reduce_or$libresoc.v:134040$6719_Y + connect \$57 $not$libresoc.v:134041$6720_Y + connect \$65 $xor$libresoc.v:134042$6721_Y + connect \$64 $reduce_or$libresoc.v:134043$6722_Y + connect \$63 $not$libresoc.v:134044$6723_Y + connect \$69 $or$libresoc.v:134045$6724_Y + connect \$71 $and$libresoc.v:134046$6725_Y + connect \$73 $ne$libresoc.v:134047$6726_Y + connect \$75 $not$libresoc.v:134048$6727_Y + connect \$77 $not$libresoc.v:134049$6728_Y + connect \$79 $or$libresoc.v:134050$6729_Y + connect \$81 $and$libresoc.v:134051$6730_Y + connect \$83 $ternary$libresoc.v:134052$6731_Y + connect \$85 $or$libresoc.v:134053$6732_Y + connect \$87 $and$libresoc.v:134054$6733_Y + connect \$89 $ternary$libresoc.v:134055$6734_Y + connect \$91 $or$libresoc.v:134056$6735_Y + connect \$93 $and$libresoc.v:134057$6736_Y + connect \$95 $ne$libresoc.v:134058$6737_Y + connect \$97 $ternary$libresoc.v:134059$6738_Y + connect \$48 \$49 + connect { \alu_op__insn$19 \alu_op__data_len$18 \alu_op__is_signed$17 \alu_op__is_32bit$16 \alu_op__output_carry$15 \alu_op__input_carry$14 \alu_op__write_cr0$13 \alu_op__invert_out$12 \alu_op__zero_a$11 \alu_op__invert_in$10 \alu_op__oe__ok$9 \alu_op__oe__oe$8 \alu_op__rc__ok$7 \alu_op__rc__rc$6 \alu_op__imm_data__ok$5 \alu_op__imm_data__data$4 \alu_op__fn_unit$3 \alu_op__insn_type$2 } { \alu_op__insn \alu_op__data_len \alu_op__is_signed \alu_op__is_32bit \alu_op__output_carry \alu_op__input_carry \alu_op__write_cr0 \alu_op__invert_out \alu_op__zero_a \alu_op__invert_in \alu_op__oe__ok \alu_op__oe__oe \alu_op__rc__ok \alu_op__rc__rc \alu_op__imm_data__ok \alu_op__imm_data__data \alu_op__fn_unit \alu_op__insn_type } + connect \muxid$1 \muxid + connect \xer_so$21 \xer_so +end +attribute \src "libresoc.v:134502.1-134906.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.pipe1.main" +attribute \generator "nMigen" +module \main$111 + attribute \src "libresoc.v:134503.7-134503.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:134858.3-134888.6" + wire width 4 $0\mode[3:0] + attribute \src "libresoc.v:134823.3-134857.6" + wire $0\o_ok[0:0] + attribute \src "libresoc.v:134858.3-134888.6" + wire width 4 $1\mode[3:0] + attribute \src "libresoc.v:134823.3-134857.6" + wire $1\o_ok[0:0] + attribute \src "libresoc.v:134503.7-134503.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:46" + wire width 5 \mb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:48" + wire \mb_extra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:47" + wire width 5 \me + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:69" + wire width 4 \mode + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 42 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 21 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 38 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 39 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 17 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 18 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 19 \rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:59" + wire \rotator_arith + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:65" + wire \rotator_carry_out_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:60" + wire \rotator_clear_left + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:61" + wire \rotator_clear_right + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:57" + wire \rotator_is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:51" + wire width 5 \rotator_mb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:53" + wire \rotator_mb_extra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:50" + wire width 5 \rotator_me + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:54" + wire width 64 \rotator_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:64" + wire width 64 \rotator_result_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:58" + wire \rotator_right_shift + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:55" + wire width 64 \rotator_rs + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:56" + wire width 7 \rotator_shift + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:62" + wire \rotator_sign_ext_rs + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 2 \sr_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 output 23 \sr_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 3 \sr_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 24 \sr_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 4 \sr_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 25 \sr_op__imm_data__ok$5 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 10 \sr_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 31 \sr_op__input_carry$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \sr_op__input_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 33 \sr_op__input_cr$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 16 \sr_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 37 \sr_op__insn$17 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \sr_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 22 \sr_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \sr_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 35 \sr_op__is_32bit$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 15 \sr_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 36 \sr_op__is_signed$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 7 \sr_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 28 \sr_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \sr_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 29 \sr_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 11 \sr_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 32 \sr_op__output_carry$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \sr_op__output_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 34 \sr_op__output_cr$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 6 \sr_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 27 \sr_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 5 \sr_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 26 \sr_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \sr_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 30 \sr_op__write_cr0$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 output 41 \xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 20 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 40 \xer_so$18 + attribute \module_not_derived 1 + attribute \src "libresoc.v:134807.11-134822.4" + cell \rotator \rotator + connect \arith \rotator_arith + connect \carry_out_o \rotator_carry_out_o + connect \clear_left \rotator_clear_left + connect \clear_right \rotator_clear_right + connect \is_32bit \rotator_is_32bit + connect \mb \rotator_mb + connect \mb_extra \rotator_mb_extra + connect \me \rotator_me + connect \ra \rotator_ra + connect \result_o \rotator_result_o + connect \right_shift \rotator_right_shift + connect \rs \rotator_rs + connect \shift \rotator_shift + connect \sign_ext_rs \rotator_sign_ext_rs + end + attribute \src "libresoc.v:134503.7-134503.20" + process $proc$libresoc.v:134503$6771 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:134823.3-134857.6" + process $proc$libresoc.v:134823$6769 + assign { } { } + assign { } { } + assign $0\o_ok[0:0] $1\o_ok[0:0] + attribute \src "libresoc.v:134824.5-134824.29" + switch \initial + attribute \src "libresoc.v:134824.9-134824.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:70" + switch \sr_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0111100 + assign $1\o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 7'0111101 + assign $1\o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 7'0111000 + assign $1\o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 7'0111001 + assign $1\o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 7'0111010 + assign $1\o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 7'0100000 + assign $1\o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\o_ok[0:0] 1'0 + end + sync always + update \o_ok $0\o_ok[0:0] + end + attribute \src "libresoc.v:134858.3-134888.6" + process $proc$libresoc.v:134858$6770 + assign { } { } + assign { } { } + assign $0\mode[3:0] $1\mode[3:0] + attribute \src "libresoc.v:134859.5-134859.29" + switch \initial + attribute \src "libresoc.v:134859.9-134859.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:70" + switch \sr_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0111100 + assign { } { } + assign $1\mode[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0111101 + assign { } { } + assign $1\mode[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 7'0111000 + assign { } { } + assign $1\mode[3:0] 4'0110 + attribute \src "libresoc.v:0.0-0.0" + case 7'0111001 + assign { } { } + assign $1\mode[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 7'0111010 + assign { } { } + assign $1\mode[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 7'0100000 + assign { } { } + assign $1\mode[3:0] 4'1000 + case + assign $1\mode[3:0] 4'0000 + end + sync always + update \mode $0\mode[3:0] + end + connect { \sr_op__insn$17 \sr_op__is_signed$16 \sr_op__is_32bit$15 \sr_op__output_cr$14 \sr_op__input_cr$13 \sr_op__output_carry$12 \sr_op__input_carry$11 \sr_op__write_cr0$10 \sr_op__oe__ok$9 \sr_op__oe__oe$8 \sr_op__rc__ok$7 \sr_op__rc__rc$6 \sr_op__imm_data__ok$5 \sr_op__imm_data__data$4 \sr_op__fn_unit$3 \sr_op__insn_type$2 } { \sr_op__insn \sr_op__is_signed \sr_op__is_32bit \sr_op__output_cr \sr_op__input_cr \sr_op__output_carry \sr_op__input_carry \sr_op__write_cr0 \sr_op__oe__ok \sr_op__oe__oe \sr_op__rc__ok \sr_op__rc__rc \sr_op__imm_data__ok \sr_op__imm_data__data \sr_op__fn_unit \sr_op__insn_type } + connect \muxid$1 \muxid + connect \xer_so$18 \xer_so + connect \xer_ca { \rotator_carry_out_o \rotator_carry_out_o } + connect \o \rotator_result_o + connect { \rotator_sign_ext_rs \rotator_clear_right \rotator_clear_left \rotator_right_shift } \mode + connect \rotator_arith \sr_op__is_signed + connect \rotator_is_32bit \sr_op__is_32bit + connect \rotator_shift \rb [6:0] + connect \rotator_ra \ra + connect \rotator_rs \rc + connect \rotator_mb_extra \mb_extra + connect \rotator_mb \mb + connect \rotator_me \me + connect \mb_extra \sr_op__insn [5] + connect \me \sr_op__insn [5:1] + connect \mb \sr_op__insn [10:6] +end +attribute \src "libresoc.v:134910.1-135440.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.alu_branch0.pipe.main" +attribute \generator "nMigen" +module \main$22 + attribute \src "libresoc.v:135347.3-135370.6" + wire $0\bc_taken[0:0] + attribute \src "libresoc.v:135226.3-135237.6" + wire width 64 $0\br_addr[63:0] + attribute \src "libresoc.v:135238.3-135264.6" + wire width 64 $0\br_imm_addr[63:0] + attribute \src "libresoc.v:135265.3-135283.6" + wire $0\br_taken[0:0] + attribute \src "libresoc.v:135319.3-135333.6" + wire $0\cr_bit[0:0] + attribute \src "libresoc.v:135397.3-135417.6" + wire width 64 $0\ctr_m[63:0] + attribute \src "libresoc.v:135371.3-135383.6" + wire width 64 $0\ctr_n[63:0] + attribute \src "libresoc.v:135334.3-135346.6" + wire $0\ctr_write[0:0] + attribute \src "libresoc.v:135418.3-135430.6" + wire $0\ctr_zero_bo1[0:0] + attribute \src "libresoc.v:135384.3-135396.6" + wire width 64 $0\fast1$10[63:0]$6804 + attribute \src "libresoc.v:135284.3-135298.6" + wire $0\fast1_ok[0:0] + attribute \src "libresoc.v:135299.3-135308.6" + wire width 64 $0\fast2$11[63:0]$6796 + attribute \src "libresoc.v:135309.3-135318.6" + wire $0\fast2_ok[0:0] + attribute \src "libresoc.v:134911.7-134911.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:135347.3-135370.6" + wire $1\bc_taken[0:0] + attribute \src "libresoc.v:135226.3-135237.6" + wire width 64 $1\br_addr[63:0] + attribute \src "libresoc.v:135238.3-135264.6" + wire width 64 $1\br_imm_addr[63:0] + attribute \src "libresoc.v:135265.3-135283.6" + wire $1\br_taken[0:0] + attribute \src "libresoc.v:135319.3-135333.6" + wire $1\cr_bit[0:0] + attribute \src "libresoc.v:135397.3-135417.6" + wire width 64 $1\ctr_m[63:0] + attribute \src "libresoc.v:135371.3-135383.6" + wire width 64 $1\ctr_n[63:0] + attribute \src "libresoc.v:135334.3-135346.6" + wire $1\ctr_write[0:0] + attribute \src "libresoc.v:135418.3-135430.6" + wire $1\ctr_zero_bo1[0:0] + attribute \src "libresoc.v:135384.3-135396.6" + wire width 64 $1\fast1$10[63:0]$6805 + attribute \src "libresoc.v:135284.3-135298.6" + wire $1\fast1_ok[0:0] + attribute \src "libresoc.v:135299.3-135308.6" + wire width 64 $1\fast2$11[63:0]$6797 + attribute \src "libresoc.v:135309.3-135318.6" + wire $1\fast2_ok[0:0] + attribute \src "libresoc.v:135347.3-135370.6" + wire $2\bc_taken[0:0] + attribute \src "libresoc.v:135238.3-135264.6" + wire width 64 $2\br_imm_addr[63:0] + attribute \src "libresoc.v:135397.3-135417.6" + wire width 64 $2\ctr_m[63:0] + attribute \src "libresoc.v:135210.18-135210.119" + wire width 65 $add$libresoc.v:135210$6774_Y + attribute \src "libresoc.v:135225.18-135225.113" + wire width 65 $add$libresoc.v:135225$6790_Y + attribute \src "libresoc.v:135217.18-135217.115" + wire $and$libresoc.v:135217$6781_Y + attribute \src "libresoc.v:135218.18-135218.117" + wire $and$libresoc.v:135218$6782_Y + attribute \src "libresoc.v:135224.18-135224.118" + wire $and$libresoc.v:135224$6789_Y + attribute \src "libresoc.v:135208.18-135208.120" + wire $eq$libresoc.v:135208$6772_Y + attribute \src "libresoc.v:135211.18-135211.111" + wire $eq$libresoc.v:135211$6775_Y + attribute \src "libresoc.v:135213.18-135213.111" + wire $eq$libresoc.v:135213$6777_Y + attribute \src "libresoc.v:135214.18-135214.111" + wire $eq$libresoc.v:135214$6778_Y + attribute \src "libresoc.v:135215.18-135215.109" + wire $eq$libresoc.v:135215$6779_Y + attribute \src "libresoc.v:135220.18-135220.98" + wire width 64 $extend$libresoc.v:135220$6784_Y + attribute \src "libresoc.v:135216.18-135216.104" + wire $not$libresoc.v:135216$6780_Y + attribute \src "libresoc.v:135223.18-135223.112" + wire $not$libresoc.v:135223$6788_Y + attribute \src "libresoc.v:135209.18-135209.116" + wire $or$libresoc.v:135209$6773_Y + attribute \src "libresoc.v:135212.18-135212.109" + wire $or$libresoc.v:135212$6776_Y + attribute \src "libresoc.v:135220.18-135220.98" + wire width 64 $pos$libresoc.v:135220$6785_Y + attribute \src "libresoc.v:135221.18-135221.103" + wire $reduce_or$libresoc.v:135221$6786_Y + attribute \src "libresoc.v:135219.18-135219.108" + wire width 65 $sub$libresoc.v:135219$6783_Y + attribute \src "libresoc.v:135222.18-135222.108" + wire $xor$libresoc.v:135222$6787_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:92" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:92" + wire \$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:95" + wire width 65 \$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:95" + wire width 65 \$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:121" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:121" + wire \$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:137" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:139" + wire \$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:141" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:138" + wire \$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:138" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:140" + wire \$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:125" + wire width 65 \$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:125" + wire width 65 \$36 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" + wire width 64 \$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:136" + wire \$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:136" + wire \$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:160" + wire \$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:160" + wire \$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:175" + wire width 65 \$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:175" + wire width 65 \$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:119" + wire \bc_taken + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:109" + wire width 2 \bi + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:105" + wire width 5 \bo + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:88" + wire width 64 \br_addr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:87" + wire width 64 \br_imm_addr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 1 \br_op__cia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 13 \br_op__cia$2 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 3 \br_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 output 15 \br_op__fn_unit$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 5 \br_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 17 \br_op__imm_data__data$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 6 \br_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 18 \br_op__imm_data__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 4 \br_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 16 \br_op__insn$5 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 2 \br_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 14 \br_op__insn_type$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \br_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 20 \br_op__is_32bit$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 7 \br_op__lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 19 \br_op__lk$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:89" + wire \br_taken + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 4 input 11 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:110" + wire \cr_bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:129" + wire width 64 \ctr_m + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:124" + wire width 64 \ctr_n + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:115" + wire \ctr_write + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:135" + wire \ctr_zero_bo1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 9 \fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 21 \fast1$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 22 \fast1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 10 \fast2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 23 \fast2$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 24 \fast2_ok + attribute \src "libresoc.v:134911.7-134911.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 27 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 12 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 25 \nia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 26 \nia_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:95" + cell $add $add$libresoc.v:135210$6774 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \br_imm_addr + connect \B \br_op__cia + connect \Y $add$libresoc.v:135210$6774_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:175" + cell $add $add$libresoc.v:135225$6790 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 65 + connect \A \br_op__cia + connect \B 3'100 + connect \Y $add$libresoc.v:135225$6790_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:138" + cell $and $and$libresoc.v:135217$6781 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ctr_zero_bo1 + connect \B \$29 + connect \Y $and$libresoc.v:135217$6781_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:140" + cell $and $and$libresoc.v:135218$6782 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ctr_zero_bo1 + connect \B \cr_bit + connect \Y $and$libresoc.v:135218$6782_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:160" + cell $and $and$libresoc.v:135224$6789 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \br_op__insn [10] + connect \B \$44 + connect \Y $and$libresoc.v:135224$6789_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:92" + cell $eq $eq$libresoc.v:135208$6772 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \br_op__insn_type + connect \B 7'0001000 + connect \Y $eq$libresoc.v:135208$6772_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:121" + cell $eq $eq$libresoc.v:135211$6775 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cr_bit + connect \B \bo [3] + connect \Y $eq$libresoc.v:135211$6775_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:137" + cell $eq $eq$libresoc.v:135213$6777 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \bo [4:3] + connect \B 1'0 + connect \Y $eq$libresoc.v:135213$6777_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:139" + cell $eq $eq$libresoc.v:135214$6778 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \bo [4:3] + connect \B 1'1 + connect \Y $eq$libresoc.v:135214$6778_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:141" + cell $eq $eq$libresoc.v:135215$6779 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \bo [4] + connect \B 1'1 + connect \Y $eq$libresoc.v:135215$6779_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" + cell $pos $extend$libresoc.v:135220$6784 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \Y_WIDTH 64 + connect \A \fast1 [31:0] + connect \Y $extend$libresoc.v:135220$6784_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:138" + cell $not $not$libresoc.v:135216$6780 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cr_bit + connect \Y $not$libresoc.v:135216$6780_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:160" + cell $not $not$libresoc.v:135223$6788 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \br_op__insn [6] + connect \Y $not$libresoc.v:135223$6788_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:92" + cell $or $or$libresoc.v:135209$6773 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \br_op__insn [1] + connect \B \$12 + connect \Y $or$libresoc.v:135209$6773_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:121" + cell $or $or$libresoc.v:135212$6776 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$19 + connect \B \bo [4] + connect \Y $or$libresoc.v:135212$6776_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" + cell $pos $pos$libresoc.v:135220$6785 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:135220$6784_Y + connect \Y $pos$libresoc.v:135220$6785_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:136" + cell $reduce_or $reduce_or$libresoc.v:135221$6786 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 1 + connect \A \ctr_n + connect \Y $reduce_or$libresoc.v:135221$6786_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:125" + cell $sub $sub$libresoc.v:135219$6783 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 65 + connect \A \fast1 + connect \B 1'1 + connect \Y $sub$libresoc.v:135219$6783_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:136" + cell $xor $xor$libresoc.v:135222$6787 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \bo [1] + connect \B \$40 + connect \Y $xor$libresoc.v:135222$6787_Y + end + attribute \src "libresoc.v:134911.7-134911.20" + process $proc$libresoc.v:134911$6808 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:135226.3-135237.6" + process $proc$libresoc.v:135226$6791 + assign { } { } + assign $0\br_addr[63:0] $1\br_addr[63:0] + attribute \src "libresoc.v:135227.5-135227.29" + switch \initial + attribute \src "libresoc.v:135227.9-135227.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:92" + switch \$14 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\br_addr[63:0] \br_imm_addr + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\br_addr[63:0] \$16 [63:0] + end + sync always + update \br_addr $0\br_addr[63:0] + end + attribute \src "libresoc.v:135238.3-135264.6" + process $proc$libresoc.v:135238$6792 + assign { } { } + assign { } { } + assign $0\br_imm_addr[63:0] $1\br_imm_addr[63:0] + attribute \src "libresoc.v:135239.5-135239.29" + switch \initial + attribute \src "libresoc.v:135239.9-135239.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:145" + switch \br_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000110 + assign { } { } + assign $1\br_imm_addr[63:0] { \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25:2] 2'00 } + attribute \src "libresoc.v:0.0-0.0" + case 7'0000111 + assign { } { } + assign $1\br_imm_addr[63:0] { \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15:2] 2'00 } + attribute \src "libresoc.v:0.0-0.0" + case 7'0001000 + assign { } { } + assign $1\br_imm_addr[63:0] $2\br_imm_addr[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:160" + switch \$46 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\br_imm_addr[63:0] { \fast1 [63:2] 2'00 } + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\br_imm_addr[63:0] { \fast2 [63:2] 2'00 } + end + case + assign $1\br_imm_addr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \br_imm_addr $0\br_imm_addr[63:0] + end + attribute \src "libresoc.v:135265.3-135283.6" + process $proc$libresoc.v:135265$6793 + assign { } { } + assign { } { } + assign $0\br_taken[0:0] $1\br_taken[0:0] + attribute \src "libresoc.v:135266.5-135266.29" + switch \initial + attribute \src "libresoc.v:135266.9-135266.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:145" + switch \br_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000110 + assign { } { } + assign $1\br_taken[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000111 + assign { } { } + assign $1\br_taken[0:0] \bc_taken + attribute \src "libresoc.v:0.0-0.0" + case 7'0001000 + assign { } { } + assign $1\br_taken[0:0] \bc_taken + case + assign $1\br_taken[0:0] 1'0 + end + sync always + update \br_taken $0\br_taken[0:0] + end + attribute \src "libresoc.v:135284.3-135298.6" + process $proc$libresoc.v:135284$6794 + assign { } { } + assign { } { } + assign $0\fast1_ok[0:0] $1\fast1_ok[0:0] + attribute \src "libresoc.v:135285.5-135285.29" + switch \initial + attribute \src "libresoc.v:135285.9-135285.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:145" + switch \br_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000111 + assign { } { } + assign $1\fast1_ok[0:0] \ctr_write + attribute \src "libresoc.v:0.0-0.0" + case 7'0001000 + assign { } { } + assign $1\fast1_ok[0:0] \ctr_write + case + assign $1\fast1_ok[0:0] 1'0 + end + sync always + update \fast1_ok $0\fast1_ok[0:0] + end + attribute \src "libresoc.v:135299.3-135308.6" + process $proc$libresoc.v:135299$6795 + assign { } { } + assign { } { } + assign $0\fast2$11[63:0]$6796 $1\fast2$11[63:0]$6797 + attribute \src "libresoc.v:135300.5-135300.29" + switch \initial + attribute \src "libresoc.v:135300.9-135300.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:172" + switch \br_op__lk + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fast2$11[63:0]$6797 \$48 [63:0] + case + assign $1\fast2$11[63:0]$6797 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fast2$11 $0\fast2$11[63:0]$6796 + end + attribute \src "libresoc.v:135309.3-135318.6" + process $proc$libresoc.v:135309$6798 + assign { } { } + assign { } { } + assign $0\fast2_ok[0:0] $1\fast2_ok[0:0] + attribute \src "libresoc.v:135310.5-135310.29" + switch \initial + attribute \src "libresoc.v:135310.9-135310.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:172" + switch \br_op__lk + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fast2_ok[0:0] 1'1 + case + assign $1\fast2_ok[0:0] 1'0 + end + sync always + update \fast2_ok $0\fast2_ok[0:0] + end + attribute \src "libresoc.v:135319.3-135333.6" + process $proc$libresoc.v:135319$6799 + assign { } { } + assign { } { } + assign $0\cr_bit[0:0] $1\cr_bit[0:0] + attribute \src "libresoc.v:135320.5-135320.29" + switch \initial + attribute \src "libresoc.v:135320.9-135320.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:112" + switch \bi + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cr_bit[0:0] \cr_a [3] + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cr_bit[0:0] \cr_a [2] + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\cr_bit[0:0] \cr_a [1] + attribute \src "libresoc.v:0.0-0.0" + case 2'-- + assign { } { } + assign $1\cr_bit[0:0] \cr_a [0] + case + assign $1\cr_bit[0:0] 1'0 + end + sync always + update \cr_bit $0\cr_bit[0:0] + end + attribute \src "libresoc.v:135334.3-135346.6" + process $proc$libresoc.v:135334$6800 + assign { } { } + assign { } { } + assign $0\ctr_write[0:0] $1\ctr_write[0:0] + attribute \src "libresoc.v:135335.5-135335.29" + switch \initial + attribute \src "libresoc.v:135335.9-135335.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:120" + switch \bo [2] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $1\ctr_write[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\ctr_write[0:0] 1'1 + end + sync always + update \ctr_write $0\ctr_write[0:0] + end + attribute \src "libresoc.v:135347.3-135370.6" + process $proc$libresoc.v:135347$6801 + assign { } { } + assign { } { } + assign $0\bc_taken[0:0] $1\bc_taken[0:0] + attribute \src "libresoc.v:135348.5-135348.29" + switch \initial + attribute \src "libresoc.v:135348.9-135348.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:120" + switch \bo [2] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\bc_taken[0:0] \$21 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\bc_taken[0:0] $2\bc_taken[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:137" + switch { \$27 \$25 \$23 } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign { } { } + assign $2\bc_taken[0:0] \$31 + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- + assign { } { } + assign $2\bc_taken[0:0] \$33 + attribute \src "libresoc.v:0.0-0.0" + case 3'1-- + assign { } { } + assign $2\bc_taken[0:0] \ctr_zero_bo1 + case + assign $2\bc_taken[0:0] 1'0 + end + end + sync always + update \bc_taken $0\bc_taken[0:0] + end + attribute \src "libresoc.v:135371.3-135383.6" + process $proc$libresoc.v:135371$6802 + assign { } { } + assign { } { } + assign $0\ctr_n[63:0] $1\ctr_n[63:0] + attribute \src "libresoc.v:135372.5-135372.29" + switch \initial + attribute \src "libresoc.v:135372.9-135372.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:120" + switch \bo [2] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $1\ctr_n[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\ctr_n[63:0] \$35 [63:0] + end + sync always + update \ctr_n $0\ctr_n[63:0] + end + attribute \src "libresoc.v:135384.3-135396.6" + process $proc$libresoc.v:135384$6803 + assign { } { } + assign { } { } + assign $0\fast1$10[63:0]$6804 $1\fast1$10[63:0]$6805 + attribute \src "libresoc.v:135385.5-135385.29" + switch \initial + attribute \src "libresoc.v:135385.9-135385.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:120" + switch \bo [2] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $1\fast1$10[63:0]$6805 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\fast1$10[63:0]$6805 \ctr_n + end + sync always + update \fast1$10 $0\fast1$10[63:0]$6804 + end + attribute \src "libresoc.v:135397.3-135417.6" + process $proc$libresoc.v:135397$6806 + assign { } { } + assign { } { } + assign $0\ctr_m[63:0] $1\ctr_m[63:0] + attribute \src "libresoc.v:135398.5-135398.29" + switch \initial + attribute \src "libresoc.v:135398.9-135398.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:120" + switch \bo [2] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $1\ctr_m[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\ctr_m[63:0] $2\ctr_m[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:130" + switch \br_op__is_32bit + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ctr_m[63:0] \$38 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\ctr_m[63:0] \fast1 + end + end + sync always + update \ctr_m $0\ctr_m[63:0] + end + attribute \src "libresoc.v:135418.3-135430.6" + process $proc$libresoc.v:135418$6807 + assign { } { } + assign { } { } + assign $0\ctr_zero_bo1[0:0] $1\ctr_zero_bo1[0:0] + attribute \src "libresoc.v:135419.5-135419.29" + switch \initial + attribute \src "libresoc.v:135419.9-135419.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:120" + switch \bo [2] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $1\ctr_zero_bo1[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\ctr_zero_bo1[0:0] \$42 + end + sync always + update \ctr_zero_bo1 $0\ctr_zero_bo1[0:0] + end + connect \$12 $eq$libresoc.v:135208$6772_Y + connect \$14 $or$libresoc.v:135209$6773_Y + connect \$17 $add$libresoc.v:135210$6774_Y + connect \$19 $eq$libresoc.v:135211$6775_Y + connect \$21 $or$libresoc.v:135212$6776_Y + connect \$23 $eq$libresoc.v:135213$6777_Y + connect \$25 $eq$libresoc.v:135214$6778_Y + connect \$27 $eq$libresoc.v:135215$6779_Y + connect \$29 $not$libresoc.v:135216$6780_Y + connect \$31 $and$libresoc.v:135217$6781_Y + connect \$33 $and$libresoc.v:135218$6782_Y + connect \$36 $sub$libresoc.v:135219$6783_Y + connect \$38 $pos$libresoc.v:135220$6785_Y + connect \$40 $reduce_or$libresoc.v:135221$6786_Y + connect \$42 $xor$libresoc.v:135222$6787_Y + connect \$44 $not$libresoc.v:135223$6788_Y + connect \$46 $and$libresoc.v:135224$6789_Y + connect \$49 $add$libresoc.v:135225$6790_Y + connect \$16 \$17 + connect \$35 \$36 + connect \$48 \$49 + connect { \br_op__is_32bit$9 \br_op__lk$8 \br_op__imm_data__ok$7 \br_op__imm_data__data$6 \br_op__insn$5 \br_op__fn_unit$4 \br_op__insn_type$3 \br_op__cia$2 } { \br_op__is_32bit \br_op__lk \br_op__imm_data__ok \br_op__imm_data__data \br_op__insn \br_op__fn_unit \br_op__insn_type \br_op__cia } + connect \muxid$1 \muxid + connect \nia_ok \br_taken + connect \nia \br_addr + connect \bi \br_op__insn [17:16] + connect \bo \br_op__insn [25:21] +end +attribute \src "libresoc.v:135444.1-136317.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.alu_trap0.pipe.main" +attribute \generator "nMigen" +module \main$35 + attribute \src "libresoc.v:136282.3-136293.6" + wire width 64 $0\a[63:0] + attribute \src "libresoc.v:135819.3-135830.6" + wire width 64 $0\a_s[63:0] + attribute \src "libresoc.v:136294.3-136305.6" + wire width 64 $0\b[63:0] + attribute \src "libresoc.v:136232.3-136243.6" + wire width 64 $0\b_s[63:0] + attribute \src "libresoc.v:135895.3-135926.6" + wire width 64 $0\fast1$10[63:0]$6850 + attribute \src "libresoc.v:135927.3-135958.6" + wire $0\fast1_ok[0:0] + attribute \src "libresoc.v:135959.3-136030.6" + wire width 64 $0\fast2$11[63:0]$6855 + attribute \src "libresoc.v:136031.3-136062.6" + wire $0\fast2_ok[0:0] + attribute \src "libresoc.v:135445.7-135445.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:136063.3-136231.6" + wire width 64 $0\msr[63:0] + attribute \src "libresoc.v:136063.3-136231.6" + wire $0\msr_ok[0:0] + attribute \src "libresoc.v:135831.3-135862.6" + wire width 64 $0\nia[63:0] + attribute \src "libresoc.v:135863.3-135894.6" + wire $0\nia_ok[0:0] + attribute \src "libresoc.v:136244.3-136262.6" + wire width 64 $0\o[63:0] + attribute \src "libresoc.v:136263.3-136281.6" + wire $0\o_ok[0:0] + attribute \src "libresoc.v:136063.3-136231.6" + wire width 2 $10\msr[5:4] + attribute \src "libresoc.v:136063.3-136231.6" + wire $11\msr[15:15] + attribute \src "libresoc.v:136063.3-136231.6" + wire $12\msr[12:12] + attribute \src "libresoc.v:136063.3-136231.6" + wire $13\msr[60:60] + attribute \src "libresoc.v:136063.3-136231.6" + wire $14\msr[12:12] + attribute \src "libresoc.v:136063.3-136231.6" + wire $15\msr[12:12] + attribute \src "libresoc.v:136063.3-136231.6" + wire width 2 $16\msr[5:4] + attribute \src "libresoc.v:136063.3-136231.6" + wire $17\msr[15:15] + attribute \src "libresoc.v:136063.3-136231.6" + wire width 3 $18\msr[34:32] + attribute \src "libresoc.v:136282.3-136293.6" + wire width 64 $1\a[63:0] + attribute \src "libresoc.v:135819.3-135830.6" + wire width 64 $1\a_s[63:0] + attribute \src "libresoc.v:136294.3-136305.6" + wire width 64 $1\b[63:0] + attribute \src "libresoc.v:136232.3-136243.6" + wire width 64 $1\b_s[63:0] + attribute \src "libresoc.v:135895.3-135926.6" + wire width 64 $1\fast1$10[63:0]$6851 + attribute \src "libresoc.v:135927.3-135958.6" + wire $1\fast1_ok[0:0] + attribute \src "libresoc.v:135959.3-136030.6" + wire width 64 $1\fast2$11[63:0]$6856 + attribute \src "libresoc.v:136031.3-136062.6" + wire $1\fast2_ok[0:0] + attribute \src "libresoc.v:136063.3-136231.6" + wire width 64 $1\msr[63:0] + attribute \src "libresoc.v:136063.3-136231.6" + wire $1\msr_ok[0:0] + attribute \src "libresoc.v:135831.3-135862.6" + wire width 64 $1\nia[63:0] + attribute \src "libresoc.v:135863.3-135894.6" + wire $1\nia_ok[0:0] + attribute \src "libresoc.v:136244.3-136262.6" + wire width 64 $1\o[63:0] + attribute \src "libresoc.v:136263.3-136281.6" + wire $1\o_ok[0:0] + attribute \src "libresoc.v:135895.3-135926.6" + wire width 64 $2\fast1$10[63:0]$6852 + attribute \src "libresoc.v:135927.3-135958.6" + wire $2\fast1_ok[0:0] + attribute \src "libresoc.v:135959.3-136030.6" + wire width 64 $2\fast2$11[63:0]$6857 + attribute \src "libresoc.v:136031.3-136062.6" + wire $2\fast2_ok[0:0] + attribute \src "libresoc.v:136063.3-136231.6" + wire width 64 $2\msr[63:0] + attribute \src "libresoc.v:136063.3-136231.6" + wire $2\msr_ok[0:0] + attribute \src "libresoc.v:135831.3-135862.6" + wire width 64 $2\nia[63:0] + attribute \src "libresoc.v:135863.3-135894.6" + wire $2\nia_ok[0:0] + attribute \src "libresoc.v:135959.3-136030.6" + wire $3\fast2$11[17:17]$6858 + attribute \src "libresoc.v:136063.3-136231.6" + wire width 11 $3\msr[11:1] + attribute \src "libresoc.v:135959.3-136030.6" + wire $4\fast2$11[18:18]$6859 + attribute \src "libresoc.v:136063.3-136231.6" + wire width 47 $4\msr[59:13] + attribute \src "libresoc.v:135959.3-136030.6" + wire $5\fast2$11[20:20]$6860 + attribute \src "libresoc.v:136063.3-136231.6" + wire width 3 $5\msr[63:61] + attribute \src "libresoc.v:135959.3-136030.6" + wire $6\fast2$11[16:16]$6861 + attribute \src "libresoc.v:136063.3-136231.6" + wire width 11 $6\msr[11:1] + attribute \src "libresoc.v:135959.3-136030.6" + wire $7\fast2$11[19:19]$6862 + attribute \src "libresoc.v:136063.3-136231.6" + wire width 47 $7\msr[59:13] + attribute \src "libresoc.v:136063.3-136231.6" + wire width 3 $8\msr[63:61] + attribute \src "libresoc.v:136063.3-136231.6" + wire width 3 $9\msr[34:32] + attribute \src "libresoc.v:135799.18-135799.113" + wire width 65 $add$libresoc.v:135799$6825_Y + attribute \src "libresoc.v:135793.18-135793.108" + wire width 5 $and$libresoc.v:135793$6818_Y + attribute \src "libresoc.v:135801.18-135801.118" + wire width 7 $and$libresoc.v:135801$6827_Y + attribute \src "libresoc.v:135803.18-135803.118" + wire width 7 $and$libresoc.v:135803$6829_Y + attribute \src "libresoc.v:135805.18-135805.118" + wire width 7 $and$libresoc.v:135805$6831_Y + attribute \src "libresoc.v:135807.18-135807.119" + wire width 7 $and$libresoc.v:135807$6833_Y + attribute \src "libresoc.v:135813.18-135813.106" + wire $and$libresoc.v:135813$6840_Y + attribute \src "libresoc.v:135818.18-135818.106" + wire $and$libresoc.v:135818$6845_Y + attribute \src "libresoc.v:135792.18-135792.100" + wire $eq$libresoc.v:135792$6817_Y + attribute \src "libresoc.v:135800.18-135800.119" + wire $eq$libresoc.v:135800$6826_Y + attribute \src "libresoc.v:135810.18-135810.121" + wire $eq$libresoc.v:135810$6837_Y + attribute \src "libresoc.v:135811.18-135811.121" + wire $eq$libresoc.v:135811$6838_Y + attribute \src "libresoc.v:135812.18-135812.111" + wire $eq$libresoc.v:135812$6839_Y + attribute \src "libresoc.v:135816.18-135816.121" + wire $eq$libresoc.v:135816$6843_Y + attribute \src "libresoc.v:135817.18-135817.114" + wire $eq$libresoc.v:135817$6844_Y + attribute \src "libresoc.v:135786.18-135786.95" + wire width 64 $extend$libresoc.v:135786$6809_Y + attribute \src "libresoc.v:135787.18-135787.95" + wire width 64 $extend$libresoc.v:135787$6811_Y + attribute \src "libresoc.v:135798.18-135798.100" + wire width 64 $extend$libresoc.v:135798$6823_Y + attribute \src "libresoc.v:135809.18-135809.109" + wire width 65 $extend$libresoc.v:135809$6835_Y + attribute \src "libresoc.v:135789.18-135789.121" + wire $gt$libresoc.v:135789$6814_Y + attribute \src "libresoc.v:135791.18-135791.99" + wire $gt$libresoc.v:135791$6816_Y + attribute \src "libresoc.v:135788.18-135788.121" + wire $lt$libresoc.v:135788$6813_Y + attribute \src "libresoc.v:135790.18-135790.99" + wire $lt$libresoc.v:135790$6815_Y + attribute \src "libresoc.v:135814.18-135814.112" + wire $not$libresoc.v:135814$6841_Y + attribute \src "libresoc.v:135815.18-135815.112" + wire $not$libresoc.v:135815$6842_Y + attribute \src "libresoc.v:135796.18-135796.106" + wire $or$libresoc.v:135796$6821_Y + attribute \src "libresoc.v:135786.18-135786.95" + wire width 64 $pos$libresoc.v:135786$6810_Y + attribute \src "libresoc.v:135787.18-135787.95" + wire width 64 $pos$libresoc.v:135787$6812_Y + attribute \src "libresoc.v:135798.18-135798.100" + wire width 64 $pos$libresoc.v:135798$6824_Y + attribute \src "libresoc.v:135809.18-135809.109" + wire width 65 $pos$libresoc.v:135809$6836_Y + attribute \src "libresoc.v:135794.18-135794.100" + wire $reduce_or$libresoc.v:135794$6819_Y + attribute \src "libresoc.v:135795.18-135795.113" + wire $reduce_or$libresoc.v:135795$6820_Y + attribute \src "libresoc.v:135802.18-135802.91" + wire $reduce_or$libresoc.v:135802$6828_Y + attribute \src "libresoc.v:135804.18-135804.91" + wire $reduce_or$libresoc.v:135804$6830_Y + attribute \src "libresoc.v:135806.18-135806.91" + wire $reduce_or$libresoc.v:135806$6832_Y + attribute \src "libresoc.v:135808.18-135808.91" + wire $reduce_or$libresoc.v:135808$6834_Y + attribute \src "libresoc.v:135797.18-135797.120" + wire width 20 $sshl$libresoc.v:135797$6822_Y + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" + wire width 64 \$12 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" + wire width 64 \$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:162" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:163" + wire \$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:164" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:165" + wire \$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:166" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:176" + wire \$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:176" + wire width 5 \$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:176" + wire \$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:176" + wire \$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:188" + wire width 64 \$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:188" + wire width 20 \$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:306" + wire width 65 \$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:306" + wire width 65 \$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:189" + wire \$41 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + wire \$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:192" + wire width 7 \$44 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + wire \$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:194" + wire width 7 \$48 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + wire \$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:196" + wire width 7 \$52 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + wire \$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:204" + wire width 7 \$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 65 \$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:225" + wire \$61 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:231" + wire \$63 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:232" + wire \$65 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:232" + wire \$67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:247" + wire \$69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:273" + wire \$71 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:286" + wire \$73 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:287" + wire \$75 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:287" + wire \$77 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:140" + wire width 64 \a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:137" + wire width 64 \a_s + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:141" + wire width 64 \b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:138" + wire width 64 \b_s + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:160" + wire \equal + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 11 \fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 24 \fast1$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 25 \fast1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 12 \fast2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 26 \fast2$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 27 \fast2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:157" + wire \gt_s + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:159" + wire \gt_u + attribute \src "libresoc.v:135445.7-135445.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:156" + wire \lt_s + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:158" + wire \lt_u + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 30 \msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 31 \msr_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 32 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 13 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 28 \nia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 29 \nia_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 22 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 23 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 9 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 10 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:175" + wire \should_trap + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:133" + wire width 5 \to + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:170" + wire width 5 \trap_bits + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 5 \trap_op__cia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 18 \trap_op__cia$6 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 2 \trap_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 output 15 \trap_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 3 \trap_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 16 \trap_op__insn$4 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \trap_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 14 \trap_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 6 \trap_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 19 \trap_op__is_32bit$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 4 \trap_op__msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 17 \trap_op__msr$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 input 8 \trap_op__trapaddr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 output 21 \trap_op__trapaddr$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 7 \trap_op__traptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 20 \trap_op__traptype$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:306" + cell $add $add$libresoc.v:135799$6825 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 65 + connect \A \trap_op__cia + connect \B 3'100 + connect \Y $add$libresoc.v:135799$6825_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:176" + cell $and $and$libresoc.v:135793$6818 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \trap_bits + connect \B \to + connect \Y $and$libresoc.v:135793$6818_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:192" + cell $and $and$libresoc.v:135801$6827 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 7 + connect \A \trap_op__traptype + connect \B 2'10 + connect \Y $and$libresoc.v:135801$6827_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:194" + cell $and $and$libresoc.v:135803$6829 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 7 + connect \A \trap_op__traptype + connect \B 1'1 + connect \Y $and$libresoc.v:135803$6829_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:196" + cell $and $and$libresoc.v:135805$6831 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 7 + connect \A \trap_op__traptype + connect \B 4'1000 + connect \Y $and$libresoc.v:135805$6831_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:204" + cell $and $and$libresoc.v:135807$6833 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 7 + connect \A \trap_op__traptype + connect \B 7'1000000 + connect \Y $and$libresoc.v:135807$6833_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:232" + cell $and $and$libresoc.v:135813$6840 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$63 + connect \B \$65 + connect \Y $and$libresoc.v:135813$6840_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:287" + cell $and $and$libresoc.v:135818$6845 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$73 + connect \B \$75 + connect \Y $and$libresoc.v:135818$6845_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:166" + cell $eq $eq$libresoc.v:135792$6817 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 1 + connect \A \a + connect \B \b + connect \Y $eq$libresoc.v:135792$6817_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:189" + cell $eq $eq$libresoc.v:135800$6826 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \trap_op__traptype + connect \B 1'0 + connect \Y $eq$libresoc.v:135800$6826_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:225" + cell $eq $eq$libresoc.v:135810$6837 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \trap_op__insn_type + connect \B 7'1001000 + connect \Y $eq$libresoc.v:135810$6837_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:231" + cell $eq $eq$libresoc.v:135811$6838 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \trap_op__msr [34:32] + connect \B 3'010 + connect \Y $eq$libresoc.v:135811$6838_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:232" + cell $eq $eq$libresoc.v:135812$6839 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \ra [34:32] + connect \B 3'000 + connect \Y $eq$libresoc.v:135812$6839_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:286" + cell $eq $eq$libresoc.v:135816$6843 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \trap_op__msr [34:32] + connect \B 3'010 + connect \Y $eq$libresoc.v:135816$6843_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:287" + cell $eq $eq$libresoc.v:135817$6844 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \fast2 [34:32] + connect \B 3'000 + connect \Y $eq$libresoc.v:135817$6844_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" + cell $pos $extend$libresoc.v:135786$6809 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \Y_WIDTH 64 + connect \A \ra [31:0] + connect \Y $extend$libresoc.v:135786$6809_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" + cell $pos $extend$libresoc.v:135787$6811 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \Y_WIDTH 64 + connect \A \rb [31:0] + connect \Y $extend$libresoc.v:135787$6811_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:188" + cell $pos $extend$libresoc.v:135798$6823 + parameter \A_SIGNED 0 + parameter \A_WIDTH 20 + parameter \Y_WIDTH 64 + connect \A \$35 + connect \Y $extend$libresoc.v:135798$6823_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + cell $pos $extend$libresoc.v:135809$6835 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \trap_op__msr + connect \Y $extend$libresoc.v:135809$6835_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:163" + cell $gt $gt$libresoc.v:135789$6814 + parameter \A_SIGNED 1 + parameter \A_WIDTH 64 + parameter \B_SIGNED 1 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 1 + connect \A \a_s + connect \B \b_s + connect \Y $gt$libresoc.v:135789$6814_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:165" + cell $gt $gt$libresoc.v:135791$6816 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 1 + connect \A \a + connect \B \b + connect \Y $gt$libresoc.v:135791$6816_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:162" + cell $lt $lt$libresoc.v:135788$6813 + parameter \A_SIGNED 1 + parameter \A_WIDTH 64 + parameter \B_SIGNED 1 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 1 + connect \A \a_s + connect \B \b_s + connect \Y $lt$libresoc.v:135788$6813_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:164" + cell $lt $lt$libresoc.v:135790$6815 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 1 + connect \A \a + connect \B \b + connect \Y $lt$libresoc.v:135790$6815_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:247" + cell $not $not$libresoc.v:135814$6841 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \trap_op__msr [60] + connect \Y $not$libresoc.v:135814$6841_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:273" + cell $not $not$libresoc.v:135815$6842 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \trap_op__insn [9] + connect \Y $not$libresoc.v:135815$6842_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:176" + cell $or $or$libresoc.v:135796$6821 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$26 + connect \B \$30 + connect \Y $or$libresoc.v:135796$6821_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" + cell $pos $pos$libresoc.v:135786$6810 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:135786$6809_Y + connect \Y $pos$libresoc.v:135786$6810_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" + cell $pos $pos$libresoc.v:135787$6812 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:135787$6811_Y + connect \Y $pos$libresoc.v:135787$6812_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:188" + cell $pos $pos$libresoc.v:135798$6824 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:135798$6823_Y + connect \Y $pos$libresoc.v:135798$6824_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + cell $pos $pos$libresoc.v:135809$6836 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \Y_WIDTH 65 + connect \A $extend$libresoc.v:135809$6835_Y + connect \Y $pos$libresoc.v:135809$6836_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:176" + cell $reduce_or $reduce_or$libresoc.v:135794$6819 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \$27 + connect \Y $reduce_or$libresoc.v:135794$6819_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:176" + cell $reduce_or $reduce_or$libresoc.v:135795$6820 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \trap_op__traptype + connect \Y $reduce_or$libresoc.v:135795$6820_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + cell $reduce_or $reduce_or$libresoc.v:135802$6828 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \$44 + connect \Y $reduce_or$libresoc.v:135802$6828_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + cell $reduce_or $reduce_or$libresoc.v:135804$6830 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \$48 + connect \Y $reduce_or$libresoc.v:135804$6830_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + cell $reduce_or $reduce_or$libresoc.v:135806$6832 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \$52 + connect \Y $reduce_or$libresoc.v:135806$6832_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + cell $reduce_or $reduce_or$libresoc.v:135808$6834 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \$56 + connect \Y $reduce_or$libresoc.v:135808$6834_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:188" + cell $sshl $sshl$libresoc.v:135797$6822 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 20 + connect \A \trap_op__trapaddr + connect \B 3'100 + connect \Y $sshl$libresoc.v:135797$6822_Y + end + attribute \src "libresoc.v:135445.7-135445.20" + process $proc$libresoc.v:135445$6870 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:135819.3-135830.6" + process $proc$libresoc.v:135819$6846 + assign { } { } + assign $0\a_s[63:0] $1\a_s[63:0] + attribute \src "libresoc.v:135820.5-135820.29" + switch \initial + attribute \src "libresoc.v:135820.9-135820.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:144" + switch \trap_op__is_32bit + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\a_s[63:0] { \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31:0] } + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\a_s[63:0] \ra + end + sync always + update \a_s $0\a_s[63:0] + end + attribute \src "libresoc.v:135831.3-135862.6" + process $proc$libresoc.v:135831$6847 + assign { } { } + assign { } { } + assign $0\nia[63:0] $1\nia[63:0] + attribute \src "libresoc.v:135832.5-135832.29" + switch \initial + attribute \src "libresoc.v:135832.9-135832.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:179" + switch \trap_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0111111 + assign { } { } + assign $1\nia[63:0] $2\nia[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:186" + switch \should_trap + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\nia[63:0] \$34 + case + assign $2\nia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + case 7'1001000 , 7'1001010 + assign $1\nia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'1000111 + assign $1\nia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'1000110 + assign { } { } + assign $1\nia[63:0] { \fast1 [63:2] 2'00 } + attribute \src "libresoc.v:0.0-0.0" + case 7'1001001 + assign { } { } + assign $1\nia[63:0] 64'0000000000000000000000000000000000000000000000000000110000000000 + case + assign $1\nia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \nia $0\nia[63:0] + end + attribute \src "libresoc.v:135863.3-135894.6" + process $proc$libresoc.v:135863$6848 + assign { } { } + assign { } { } + assign $0\nia_ok[0:0] $1\nia_ok[0:0] + attribute \src "libresoc.v:135864.5-135864.29" + switch \initial + attribute \src "libresoc.v:135864.9-135864.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:179" + switch \trap_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0111111 + assign { } { } + assign $1\nia_ok[0:0] $2\nia_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:186" + switch \should_trap + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\nia_ok[0:0] 1'1 + case + assign $2\nia_ok[0:0] 1'0 + end + attribute \src "libresoc.v:0.0-0.0" + case 7'1001000 , 7'1001010 + assign $1\nia_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'1000111 + assign $1\nia_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'1000110 + assign { } { } + assign $1\nia_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 7'1001001 + assign { } { } + assign $1\nia_ok[0:0] 1'1 + case + assign $1\nia_ok[0:0] 1'0 + end + sync always + update \nia_ok $0\nia_ok[0:0] + end + attribute \src "libresoc.v:135895.3-135926.6" + process $proc$libresoc.v:135895$6849 + assign { } { } + assign { } { } + assign $0\fast1$10[63:0]$6850 $1\fast1$10[63:0]$6851 + attribute \src "libresoc.v:135896.5-135896.29" + switch \initial + attribute \src "libresoc.v:135896.9-135896.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:179" + switch \trap_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0111111 + assign { } { } + assign $1\fast1$10[63:0]$6851 $2\fast1$10[63:0]$6852 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:186" + switch \should_trap + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\fast1$10[63:0]$6852 \trap_op__cia + case + assign $2\fast1$10[63:0]$6852 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + case 7'1001000 , 7'1001010 + assign $1\fast1$10[63:0]$6851 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'1000111 + assign $1\fast1$10[63:0]$6851 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'1000110 + assign $1\fast1$10[63:0]$6851 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'1001001 + assign { } { } + assign $1\fast1$10[63:0]$6851 \$38 [63:0] + case + assign $1\fast1$10[63:0]$6851 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fast1$10 $0\fast1$10[63:0]$6850 + end + attribute \src "libresoc.v:135927.3-135958.6" + process $proc$libresoc.v:135927$6853 + assign { } { } + assign { } { } + assign $0\fast1_ok[0:0] $1\fast1_ok[0:0] + attribute \src "libresoc.v:135928.5-135928.29" + switch \initial + attribute \src "libresoc.v:135928.9-135928.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:179" + switch \trap_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0111111 + assign { } { } + assign $1\fast1_ok[0:0] $2\fast1_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:186" + switch \should_trap + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\fast1_ok[0:0] 1'1 + case + assign $2\fast1_ok[0:0] 1'0 + end + attribute \src "libresoc.v:0.0-0.0" + case 7'1001000 , 7'1001010 + assign $1\fast1_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'1000111 + assign $1\fast1_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'1000110 + assign $1\fast1_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'1001001 + assign { } { } + assign $1\fast1_ok[0:0] 1'1 + case + assign $1\fast1_ok[0:0] 1'0 + end + sync always + update \fast1_ok $0\fast1_ok[0:0] + end + attribute \src "libresoc.v:135959.3-136030.6" + process $proc$libresoc.v:135959$6854 + assign { } { } + assign { } { } + assign $0\fast2$11[63:0]$6855 $1\fast2$11[63:0]$6856 + attribute \src "libresoc.v:135960.5-135960.29" + switch \initial + attribute \src "libresoc.v:135960.9-135960.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:179" + switch \trap_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0111111 + assign { } { } + assign $1\fast2$11[63:0]$6856 $2\fast2$11[63:0]$6857 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:186" + switch \should_trap + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { $2\fast2$11[63:0]$6857 [30:27] $2\fast2$11[63:0]$6857 [21] } 5'00000 + assign $2\fast2$11[63:0]$6857 [15:0] \trap_op__msr [15:0] + assign $2\fast2$11[63:0]$6857 [26:22] \trap_op__msr [26:22] + assign $2\fast2$11[63:0]$6857 [63:31] \trap_op__msr [63:31] + assign $2\fast2$11[63:0]$6857 [17] $3\fast2$11[17:17]$6858 + assign $2\fast2$11[63:0]$6857 [18] $4\fast2$11[18:18]$6859 + assign $2\fast2$11[63:0]$6857 [20] $5\fast2$11[20:20]$6860 + assign $2\fast2$11[63:0]$6857 [16] $6\fast2$11[16:16]$6861 + assign $2\fast2$11[63:0]$6857 [19] $7\fast2$11[19:19]$6862 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:189" + switch \$41 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fast2$11[17:17]$6858 1'1 + case + assign $3\fast2$11[17:17]$6858 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:192" + switch \$43 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\fast2$11[18:18]$6859 1'1 + case + assign $4\fast2$11[18:18]$6859 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:194" + switch \$47 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\fast2$11[20:20]$6860 1'1 + case + assign $5\fast2$11[20:20]$6860 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:196" + switch \$51 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\fast2$11[16:16]$6861 1'1 + case + assign $6\fast2$11[16:16]$6861 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:204" + switch \$55 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\fast2$11[19:19]$6862 1'1 + case + assign $7\fast2$11[19:19]$6862 1'0 + end + case + assign $2\fast2$11[63:0]$6857 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + case 7'1001000 , 7'1001010 + assign $1\fast2$11[63:0]$6856 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'1000111 + assign $1\fast2$11[63:0]$6856 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'1000110 + assign $1\fast2$11[63:0]$6856 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'1001001 + assign { } { } + assign { $1\fast2$11[63:0]$6856 [30:27] $1\fast2$11[63:0]$6856 [21:16] } 10'0000000000 + assign $1\fast2$11[63:0]$6856 [15:0] \trap_op__msr [15:0] + assign $1\fast2$11[63:0]$6856 [26:22] \trap_op__msr [26:22] + assign $1\fast2$11[63:0]$6856 [63:31] \trap_op__msr [63:31] + case + assign $1\fast2$11[63:0]$6856 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fast2$11 $0\fast2$11[63:0]$6855 + end + attribute \src "libresoc.v:136031.3-136062.6" + process $proc$libresoc.v:136031$6863 + assign { } { } + assign { } { } + assign $0\fast2_ok[0:0] $1\fast2_ok[0:0] + attribute \src "libresoc.v:136032.5-136032.29" + switch \initial + attribute \src "libresoc.v:136032.9-136032.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:179" + switch \trap_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0111111 + assign { } { } + assign $1\fast2_ok[0:0] $2\fast2_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:186" + switch \should_trap + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\fast2_ok[0:0] 1'1 + case + assign $2\fast2_ok[0:0] 1'0 + end + attribute \src "libresoc.v:0.0-0.0" + case 7'1001000 , 7'1001010 + assign $1\fast2_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'1000111 + assign $1\fast2_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'1000110 + assign $1\fast2_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'1001001 + assign { } { } + assign $1\fast2_ok[0:0] 1'1 + case + assign $1\fast2_ok[0:0] 1'0 + end + sync always + update \fast2_ok $0\fast2_ok[0:0] + end + attribute \src "libresoc.v:136063.3-136231.6" + process $proc$libresoc.v:136063$6864 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\msr[63:0] $1\msr[63:0] + assign $0\msr_ok[0:0] $1\msr_ok[0:0] + attribute \src "libresoc.v:136064.5-136064.29" + switch \initial + attribute \src "libresoc.v:136064.9-136064.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:179" + switch \trap_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0111111 + assign { } { } + assign { } { } + assign $1\msr[63:0] $2\msr[63:0] + assign $1\msr_ok[0:0] $2\msr_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:186" + switch \should_trap + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\msr[63:0] [62:59] $2\msr[63:0] [57:33] $2\msr[63:0] [31:26] $2\msr[63:0] [24] $2\msr[63:0] [22:16] $2\msr[63:0] [12] $2\msr[63:0] [7:6] $2\msr[63:0] [2] } { \trap_op__msr [62:59] \trap_op__msr [57:33] \trap_op__msr [31:26] \trap_op__msr [24] \trap_op__msr [22:16] \trap_op__msr [12] \trap_op__msr [7:6] \trap_op__msr [2] } + assign $2\msr[63:0] [63] 1'1 + assign $2\msr[63:0] [15] 1'0 + assign $2\msr[63:0] [14] 1'0 + assign $2\msr[63:0] [5] 1'0 + assign $2\msr[63:0] [4] 1'0 + assign $2\msr[63:0] [1] 1'0 + assign $2\msr[63:0] [0] 1'1 + assign $2\msr[63:0] [11] 1'0 + assign $2\msr[63:0] [8] 1'0 + assign $2\msr[63:0] [23] 1'0 + assign $2\msr[63:0] [32] 1'0 + assign $2\msr[63:0] [25] 1'0 + assign $2\msr[63:0] [13] 1'0 + assign $2\msr[63:0] [3] 1'0 + assign $2\msr[63:0] [10] 1'0 + assign $2\msr[63:0] [9] 1'0 + assign $2\msr[63:0] [58] 1'0 + assign $2\msr_ok[0:0] 1'1 + case + assign $2\msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\msr_ok[0:0] 1'0 + end + attribute \src "libresoc.v:0.0-0.0" + case 7'1001000 , 7'1001010 + assign { } { } + assign { } { } + assign $1\msr[63:0] [0] \$59 [0] + assign $1\msr[63:0] [11:1] $3\msr[11:1] + assign $1\msr[63:0] [59:13] $4\msr[59:13] + assign $1\msr[63:0] [63:61] $5\msr[63:61] + assign $1\msr[63:0] [12] $12\msr[12:12] + assign $1\msr[63:0] [60] $13\msr[60:60] + assign $1\msr_ok[0:0] 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:218" + switch \trap_op__insn [21] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $3\msr[11:1] [10:1] \$59 [11:2] + assign { $4\msr[59:13] [46:3] $4\msr[59:13] [1:0] } { \$59 [59:16] \$59 [14:13] } + assign $5\msr[63:61] \$59 [63:61] + assign $3\msr[11:1] [0] \ra [1] + assign $4\msr[59:13] [2] \ra [15] + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign { } { } + assign { $3\msr[11:1] [10:5] $3\msr[11:1] [2:0] } { $6\msr[11:1] [10:5] $6\msr[11:1] [2:0] } + assign { $4\msr[59:13] [46:3] $4\msr[59:13] [1:0] } { $7\msr[59:13] [46:3] $7\msr[59:13] [1:0] } + assign $5\msr[63:61] $8\msr[63:61] + assign $3\msr[11:1] [4:3] $10\msr[5:4] + assign $4\msr[59:13] [2] $11\msr[15:15] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:225" + switch \$61 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign $6\msr[11:1] \ra [11:1] + assign { $7\msr[59:13] [46:22] $7\msr[59:13] [18:0] } { \ra [59:35] \ra [31:13] } + assign $8\msr[63:61] \ra [63:61] + assign $7\msr[59:13] [21:19] $9\msr[34:32] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:232" + switch \$67 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $9\msr[34:32] \trap_op__msr [34:32] + case + assign $9\msr[34:32] \ra [34:32] + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $7\msr[59:13] [46:19] \$59 [59:32] + assign $8\msr[63:61] \$59 [63:61] + assign $6\msr[11:1] \ra [11:1] + assign $7\msr[59:13] [18:0] \ra [31:13] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:48" + switch $7\msr[59:13] [1] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $11\msr[15:15] 1'1 + assign $10\msr[5:4] [1] 1'1 + assign $10\msr[5:4] [0] 1'1 + case + assign $10\msr[5:4] $6\msr[11:1] [4:3] + assign $11\msr[15:15] $7\msr[59:13] [2] + end + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:247" + switch \$69 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $13\msr[60:60] \trap_op__msr [60] + assign $12\msr[12:12] \trap_op__msr [12] + case + assign $12\msr[12:12] \$59 [12] + assign $13\msr[60:60] \$59 [60] + end + attribute \src "libresoc.v:0.0-0.0" + case 7'1000111 + assign $1\msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\msr_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'1000110 + assign { $1\msr[63:0] [30:27] $1\msr[63:0] [21:16] } 10'0000000000 + assign { } { } + assign { $1\msr[63:0] [14:13] $1\msr[63:0] [11:6] $1\msr[63:0] [3:0] } { \fast2 [14:13] \fast2 [11:6] \fast2 [3:0] } + assign $1\msr[63:0] [26:22] \fast2 [26:22] + assign { $1\msr[63:0] [63:35] $1\msr[63:0] [31] } { \fast2 [63:35] \fast2 [31] } + assign $1\msr[63:0] [12] $14\msr[12:12] + assign $1\msr[63:0] [5:4] $16\msr[5:4] + assign $1\msr[63:0] [15] $17\msr[15:15] + assign $1\msr[63:0] [34:32] $18\msr[34:32] + assign $1\msr_ok[0:0] 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:273" + switch \$71 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $14\msr[12:12] $15\msr[12:12] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:274" + switch \trap_op__msr [60] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $15\msr[12:12] \fast2 [12] + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $15\msr[12:12] \trap_op__msr [12] + end + case + assign $14\msr[12:12] \fast2 [12] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:48" + switch \fast2 [14] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $17\msr[15:15] 1'1 + assign $16\msr[5:4] [1] 1'1 + assign $16\msr[5:4] [0] 1'1 + case + assign $16\msr[5:4] \fast2 [5:4] + assign $17\msr[15:15] \fast2 [15] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:287" + switch \$77 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $18\msr[34:32] \trap_op__msr [34:32] + case + assign $18\msr[34:32] \fast2 [34:32] + end + attribute \src "libresoc.v:0.0-0.0" + case 7'1001001 + assign { } { } + assign { } { } + assign { $1\msr[63:0] [62:59] $1\msr[63:0] [57:33] $1\msr[63:0] [31:26] $1\msr[63:0] [24] $1\msr[63:0] [22:16] $1\msr[63:0] [12] $1\msr[63:0] [7:6] $1\msr[63:0] [2] } { \trap_op__msr [62:59] \trap_op__msr [57:33] \trap_op__msr [31:26] \trap_op__msr [24] \trap_op__msr [22:16] \trap_op__msr [12] \trap_op__msr [7:6] \trap_op__msr [2] } + assign $1\msr[63:0] [63] 1'1 + assign $1\msr[63:0] [15] 1'0 + assign $1\msr[63:0] [14] 1'0 + assign $1\msr[63:0] [5] 1'0 + assign $1\msr[63:0] [4] 1'0 + assign $1\msr[63:0] [1] 1'0 + assign $1\msr[63:0] [0] 1'1 + assign $1\msr[63:0] [11] 1'0 + assign $1\msr[63:0] [8] 1'0 + assign $1\msr[63:0] [23] 1'0 + assign $1\msr[63:0] [32] 1'0 + assign $1\msr[63:0] [25] 1'0 + assign $1\msr[63:0] [13] 1'0 + assign $1\msr[63:0] [3] 1'0 + assign $1\msr[63:0] [10] 1'0 + assign $1\msr[63:0] [9] 1'0 + assign $1\msr[63:0] [58] 1'0 + assign $1\msr_ok[0:0] 1'1 + case + assign $1\msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\msr_ok[0:0] 1'0 + end + sync always + update \msr $0\msr[63:0] + update \msr_ok $0\msr_ok[0:0] + end + attribute \src "libresoc.v:136232.3-136243.6" + process $proc$libresoc.v:136232$6865 + assign { } { } + assign $0\b_s[63:0] $1\b_s[63:0] + attribute \src "libresoc.v:136233.5-136233.29" + switch \initial + attribute \src "libresoc.v:136233.9-136233.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:144" + switch \trap_op__is_32bit + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\b_s[63:0] { \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31:0] } + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\b_s[63:0] \rb + end + sync always + update \b_s $0\b_s[63:0] + end + attribute \src "libresoc.v:136244.3-136262.6" + process $proc$libresoc.v:136244$6866 + assign { } { } + assign { } { } + assign $0\o[63:0] $1\o[63:0] + attribute \src "libresoc.v:136245.5-136245.29" + switch \initial + attribute \src "libresoc.v:136245.9-136245.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:179" + switch \trap_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0111111 + assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'1001000 , 7'1001010 + assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'1000111 + assign { } { } + assign $1\o[63:0] \trap_op__msr + case + assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \o $0\o[63:0] + end + attribute \src "libresoc.v:136263.3-136281.6" + process $proc$libresoc.v:136263$6867 + assign { } { } + assign { } { } + assign $0\o_ok[0:0] $1\o_ok[0:0] + attribute \src "libresoc.v:136264.5-136264.29" + switch \initial + attribute \src "libresoc.v:136264.9-136264.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:179" + switch \trap_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0111111 + assign $1\o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'1001000 , 7'1001010 + assign $1\o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'1000111 + assign { } { } + assign $1\o_ok[0:0] 1'1 + case + assign $1\o_ok[0:0] 1'0 + end + sync always + update \o_ok $0\o_ok[0:0] + end + attribute \src "libresoc.v:136282.3-136293.6" + process $proc$libresoc.v:136282$6868 + assign { } { } + assign $0\a[63:0] $1\a[63:0] + attribute \src "libresoc.v:136283.5-136283.29" + switch \initial + attribute \src "libresoc.v:136283.9-136283.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:144" + switch \trap_op__is_32bit + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\a[63:0] \$12 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\a[63:0] \ra + end + sync always + update \a $0\a[63:0] + end + attribute \src "libresoc.v:136294.3-136305.6" + process $proc$libresoc.v:136294$6869 + assign { } { } + assign $0\b[63:0] $1\b[63:0] + attribute \src "libresoc.v:136295.5-136295.29" + switch \initial + attribute \src "libresoc.v:136295.9-136295.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:144" + switch \trap_op__is_32bit + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\b[63:0] \$14 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\b[63:0] \rb + end + sync always + update \b $0\b[63:0] + end + connect \$12 $pos$libresoc.v:135786$6810_Y + connect \$14 $pos$libresoc.v:135787$6812_Y + connect \$16 $lt$libresoc.v:135788$6813_Y + connect \$18 $gt$libresoc.v:135789$6814_Y + connect \$20 $lt$libresoc.v:135790$6815_Y + connect \$22 $gt$libresoc.v:135791$6816_Y + connect \$24 $eq$libresoc.v:135792$6817_Y + connect \$27 $and$libresoc.v:135793$6818_Y + connect \$26 $reduce_or$libresoc.v:135794$6819_Y + connect \$30 $reduce_or$libresoc.v:135795$6820_Y + connect \$32 $or$libresoc.v:135796$6821_Y + connect \$35 $sshl$libresoc.v:135797$6822_Y + connect \$34 $pos$libresoc.v:135798$6824_Y + connect \$39 $add$libresoc.v:135799$6825_Y + connect \$41 $eq$libresoc.v:135800$6826_Y + connect \$44 $and$libresoc.v:135801$6827_Y + connect \$43 $reduce_or$libresoc.v:135802$6828_Y + connect \$48 $and$libresoc.v:135803$6829_Y + connect \$47 $reduce_or$libresoc.v:135804$6830_Y + connect \$52 $and$libresoc.v:135805$6831_Y + connect \$51 $reduce_or$libresoc.v:135806$6832_Y + connect \$56 $and$libresoc.v:135807$6833_Y + connect \$55 $reduce_or$libresoc.v:135808$6834_Y + connect \$59 $pos$libresoc.v:135809$6836_Y + connect \$61 $eq$libresoc.v:135810$6837_Y + connect \$63 $eq$libresoc.v:135811$6838_Y + connect \$65 $eq$libresoc.v:135812$6839_Y + connect \$67 $and$libresoc.v:135813$6840_Y + connect \$69 $not$libresoc.v:135814$6841_Y + connect \$71 $not$libresoc.v:135815$6842_Y + connect \$73 $eq$libresoc.v:135816$6843_Y + connect \$75 $eq$libresoc.v:135817$6844_Y + connect \$77 $and$libresoc.v:135818$6845_Y + connect \$38 \$39 + connect { \trap_op__trapaddr$9 \trap_op__traptype$8 \trap_op__is_32bit$7 \trap_op__cia$6 \trap_op__msr$5 \trap_op__insn$4 \trap_op__fn_unit$3 \trap_op__insn_type$2 } { \trap_op__trapaddr \trap_op__traptype \trap_op__is_32bit \trap_op__cia \trap_op__msr \trap_op__insn \trap_op__fn_unit \trap_op__insn_type } + connect \muxid$1 \muxid + connect \should_trap \$32 + connect \trap_bits { \lt_s \gt_s \equal \lt_u \gt_u } + connect \equal \$24 + connect \gt_u \$22 + connect \lt_u \$20 + connect \gt_s \$18 + connect \lt_s \$16 + connect \to \trap_op__insn [25:21] +end +attribute \src "libresoc.v:136321.1-137064.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_logical0.logical_pipe1.main" +attribute \generator "nMigen" +module \main$48 + attribute \src "libresoc.v:137031.3-137041.6" + wire width 32 $0\a32[31:0] + attribute \src "libresoc.v:136976.3-136986.6" + wire width 64 $0\b[63:0] + attribute \src "libresoc.v:136954.3-136964.6" + wire width 64 $0\bpermd_rb[63:0] + attribute \src "libresoc.v:136943.3-136953.6" + wire width 64 $0\bpermd_rs[63:0] + attribute \src "libresoc.v:136932.3-136942.6" + wire width 64 $0\clz_sig_in[63:0] + attribute \src "libresoc.v:137042.3-137060.6" + wire width 64 $0\cntz_i[63:0] + attribute \src "libresoc.v:137020.3-137030.6" + wire $0\count_right[0:0] + attribute \src "libresoc.v:136322.7-136322.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:136877.3-136931.6" + wire width 64 $0\o[63:0] + attribute \src "libresoc.v:136877.3-136931.6" + wire $0\o_ok[0:0] + attribute \src "libresoc.v:136998.3-137008.6" + wire $0\par0[0:0] + attribute \src "libresoc.v:137009.3-137019.6" + wire $0\par1[0:0] + attribute \src "libresoc.v:136965.3-136975.6" + wire width 64 $0\popcount_a[63:0] + attribute \src "libresoc.v:136987.3-136997.6" + wire width 64 $0\popcount_data_len[63:0] + attribute \src "libresoc.v:137031.3-137041.6" + wire width 32 $1\a32[31:0] + attribute \src "libresoc.v:136976.3-136986.6" + wire width 64 $1\b[63:0] + attribute \src "libresoc.v:136954.3-136964.6" + wire width 64 $1\bpermd_rb[63:0] + attribute \src "libresoc.v:136943.3-136953.6" + wire width 64 $1\bpermd_rs[63:0] + attribute \src "libresoc.v:136932.3-136942.6" + wire width 64 $1\clz_sig_in[63:0] + attribute \src "libresoc.v:137042.3-137060.6" + wire width 64 $1\cntz_i[63:0] + attribute \src "libresoc.v:137020.3-137030.6" + wire $1\count_right[0:0] + attribute \src "libresoc.v:136877.3-136931.6" + wire width 64 $1\o[63:0] + attribute \src "libresoc.v:136877.3-136931.6" + wire $1\o_ok[0:0] + attribute \src "libresoc.v:136998.3-137008.6" + wire $1\par0[0:0] + attribute \src "libresoc.v:137009.3-137019.6" + wire $1\par1[0:0] + attribute \src "libresoc.v:136965.3-136975.6" + wire width 64 $1\popcount_a[63:0] + attribute \src "libresoc.v:136987.3-136997.6" + wire width 64 $1\popcount_data_len[63:0] + attribute \src "libresoc.v:137042.3-137060.6" + wire width 64 $2\cntz_i[63:0] + attribute \src "libresoc.v:136877.3-136931.6" + wire width 64 $2\o[63:0] + attribute \src "libresoc.v:136824.18-136824.103" + wire width 64 $and$libresoc.v:136824$6917_Y + attribute \src "libresoc.v:136783.18-136783.118" + wire $eq$libresoc.v:136783$6871_Y + attribute \src "libresoc.v:136784.19-136784.119" + wire $eq$libresoc.v:136784$6872_Y + attribute \src "libresoc.v:136785.19-136785.119" + wire $eq$libresoc.v:136785$6873_Y + attribute \src "libresoc.v:136786.19-136786.119" + wire $eq$libresoc.v:136786$6874_Y + attribute \src "libresoc.v:136787.19-136787.119" + wire $eq$libresoc.v:136787$6875_Y + attribute \src "libresoc.v:136788.19-136788.119" + wire $eq$libresoc.v:136788$6876_Y + attribute \src "libresoc.v:136789.19-136789.119" + wire $eq$libresoc.v:136789$6877_Y + attribute \src "libresoc.v:136790.19-136790.119" + wire $eq$libresoc.v:136790$6878_Y + attribute \src "libresoc.v:136791.19-136791.119" + wire $eq$libresoc.v:136791$6879_Y + attribute \src "libresoc.v:136792.19-136792.119" + wire $eq$libresoc.v:136792$6880_Y + attribute \src "libresoc.v:136793.19-136793.119" + wire $eq$libresoc.v:136793$6881_Y + attribute \src "libresoc.v:136794.19-136794.119" + wire $eq$libresoc.v:136794$6882_Y + attribute \src "libresoc.v:136795.19-136795.119" + wire $eq$libresoc.v:136795$6883_Y + attribute \src "libresoc.v:136796.19-136796.119" + wire $eq$libresoc.v:136796$6884_Y + attribute \src "libresoc.v:136797.19-136797.119" + wire $eq$libresoc.v:136797$6885_Y + attribute \src "libresoc.v:136798.19-136798.119" + wire $eq$libresoc.v:136798$6886_Y + attribute \src "libresoc.v:136799.19-136799.119" + wire $eq$libresoc.v:136799$6887_Y + attribute \src "libresoc.v:136800.19-136800.119" + wire $eq$libresoc.v:136800$6888_Y + attribute \src "libresoc.v:136801.19-136801.119" + wire $eq$libresoc.v:136801$6889_Y + attribute \src "libresoc.v:136802.19-136802.119" + wire $eq$libresoc.v:136802$6890_Y + attribute \src "libresoc.v:136803.19-136803.119" + wire $eq$libresoc.v:136803$6891_Y + attribute \src "libresoc.v:136804.19-136804.119" + wire $eq$libresoc.v:136804$6892_Y + attribute \src "libresoc.v:136805.19-136805.119" + wire $eq$libresoc.v:136805$6893_Y + attribute \src "libresoc.v:136806.19-136806.119" + wire $eq$libresoc.v:136806$6894_Y + attribute \src "libresoc.v:136807.19-136807.119" + wire $eq$libresoc.v:136807$6895_Y + attribute \src "libresoc.v:136808.19-136808.119" + wire $eq$libresoc.v:136808$6896_Y + attribute \src "libresoc.v:136809.19-136809.119" + wire $eq$libresoc.v:136809$6897_Y + attribute \src "libresoc.v:136810.19-136810.119" + wire $eq$libresoc.v:136810$6898_Y + attribute \src "libresoc.v:136811.19-136811.128" + wire $eq$libresoc.v:136811$6899_Y + attribute \src "libresoc.v:136827.18-136827.114" + wire $eq$libresoc.v:136827$6920_Y + attribute \src "libresoc.v:136828.18-136828.114" + wire $eq$libresoc.v:136828$6921_Y + attribute \src "libresoc.v:136829.18-136829.114" + wire $eq$libresoc.v:136829$6922_Y + attribute \src "libresoc.v:136830.18-136830.114" + wire $eq$libresoc.v:136830$6923_Y + attribute \src "libresoc.v:136831.18-136831.114" + wire $eq$libresoc.v:136831$6924_Y + attribute \src "libresoc.v:136832.18-136832.114" + wire $eq$libresoc.v:136832$6925_Y + attribute \src "libresoc.v:136833.18-136833.114" + wire $eq$libresoc.v:136833$6926_Y + attribute \src "libresoc.v:136834.18-136834.114" + wire $eq$libresoc.v:136834$6927_Y + attribute \src "libresoc.v:136835.18-136835.116" + wire $eq$libresoc.v:136835$6928_Y + attribute \src "libresoc.v:136836.18-136836.116" + wire $eq$libresoc.v:136836$6929_Y + attribute \src "libresoc.v:136837.18-136837.116" + wire $eq$libresoc.v:136837$6930_Y + attribute \src "libresoc.v:136838.18-136838.116" + wire $eq$libresoc.v:136838$6931_Y + attribute \src "libresoc.v:136839.18-136839.116" + wire $eq$libresoc.v:136839$6932_Y + attribute \src "libresoc.v:136840.18-136840.116" + wire $eq$libresoc.v:136840$6933_Y + attribute \src "libresoc.v:136841.18-136841.116" + wire $eq$libresoc.v:136841$6934_Y + attribute \src "libresoc.v:136842.18-136842.116" + wire $eq$libresoc.v:136842$6935_Y + attribute \src "libresoc.v:136843.18-136843.118" + wire $eq$libresoc.v:136843$6936_Y + attribute \src "libresoc.v:136844.18-136844.118" + wire $eq$libresoc.v:136844$6937_Y + attribute \src "libresoc.v:136845.18-136845.118" + wire $eq$libresoc.v:136845$6938_Y + attribute \src "libresoc.v:136846.18-136846.118" + wire $eq$libresoc.v:136846$6939_Y + attribute \src "libresoc.v:136847.18-136847.118" + wire $eq$libresoc.v:136847$6940_Y + attribute \src "libresoc.v:136848.18-136848.118" + wire $eq$libresoc.v:136848$6941_Y + attribute \src "libresoc.v:136849.18-136849.118" + wire $eq$libresoc.v:136849$6942_Y + attribute \src "libresoc.v:136850.18-136850.118" + wire $eq$libresoc.v:136850$6943_Y + attribute \src "libresoc.v:136851.18-136851.118" + wire $eq$libresoc.v:136851$6944_Y + attribute \src "libresoc.v:136852.18-136852.118" + wire $eq$libresoc.v:136852$6945_Y + attribute \src "libresoc.v:136853.18-136853.118" + wire $eq$libresoc.v:136853$6946_Y + attribute \src "libresoc.v:136854.18-136854.118" + wire $eq$libresoc.v:136854$6947_Y + attribute \src "libresoc.v:136855.18-136855.118" + wire $eq$libresoc.v:136855$6948_Y + attribute \src "libresoc.v:136856.18-136856.118" + wire $eq$libresoc.v:136856$6949_Y + attribute \src "libresoc.v:136857.18-136857.118" + wire $eq$libresoc.v:136857$6950_Y + attribute \src "libresoc.v:136858.18-136858.118" + wire $eq$libresoc.v:136858$6951_Y + attribute \src "libresoc.v:136859.18-136859.118" + wire $eq$libresoc.v:136859$6952_Y + attribute \src "libresoc.v:136860.18-136860.118" + wire $eq$libresoc.v:136860$6953_Y + attribute \src "libresoc.v:136861.18-136861.118" + wire $eq$libresoc.v:136861$6954_Y + attribute \src "libresoc.v:136862.18-136862.118" + wire $eq$libresoc.v:136862$6955_Y + attribute \src "libresoc.v:136813.19-136813.104" + wire width 64 $extend$libresoc.v:136813$6901_Y + attribute \src "libresoc.v:136815.19-136815.93" + wire width 8 $extend$libresoc.v:136815$6904_Y + attribute \src "libresoc.v:136817.19-136817.105" + wire width 64 $extend$libresoc.v:136817$6907_Y + attribute \src "libresoc.v:136818.19-136818.118" + wire width 64 $extend$libresoc.v:136818$6909_Y + attribute \src "libresoc.v:136822.19-136822.105" + wire width 64 $extend$libresoc.v:136822$6914_Y + attribute \src "libresoc.v:136825.18-136825.103" + wire width 64 $or$libresoc.v:136825$6918_Y + attribute \src "libresoc.v:136813.19-136813.104" + wire width 64 $pos$libresoc.v:136813$6902_Y + attribute \src "libresoc.v:136815.19-136815.93" + wire width 8 $pos$libresoc.v:136815$6905_Y + attribute \src "libresoc.v:136817.19-136817.105" + wire width 64 $pos$libresoc.v:136817$6908_Y + attribute \src "libresoc.v:136818.19-136818.118" + wire width 64 $pos$libresoc.v:136818$6910_Y + attribute \src "libresoc.v:136822.19-136822.105" + wire width 64 $pos$libresoc.v:136822$6915_Y + attribute \src "libresoc.v:136819.19-136819.131" + wire $reduce_xor$libresoc.v:136819$6911_Y + attribute \src "libresoc.v:136820.19-136820.133" + wire $reduce_xor$libresoc.v:136820$6912_Y + attribute \src "libresoc.v:136814.19-136814.112" + wire width 8 $sub$libresoc.v:136814$6903_Y + attribute \src "libresoc.v:136816.19-136816.135" + wire width 8 $ternary$libresoc.v:136816$6906_Y + attribute \src "libresoc.v:136821.19-136821.398" + wire width 32 $ternary$libresoc.v:136821$6913_Y + attribute \src "libresoc.v:136823.19-136823.621" + wire width 64 $ternary$libresoc.v:136823$6916_Y + attribute \src "libresoc.v:136812.19-136812.108" + wire $xor$libresoc.v:136812$6900_Y + attribute \src "libresoc.v:136826.18-136826.103" + wire width 64 $xor$libresoc.v:136826$6919_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + wire \$101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + wire \$103 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + wire \$105 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + wire \$107 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + wire \$109 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + wire \$111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + wire \$113 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + wire \$115 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + wire \$117 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + wire \$119 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + wire \$121 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + wire \$123 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + wire \$125 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + wire \$127 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + wire \$129 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + wire \$131 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + wire \$133 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + wire \$135 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + wire \$137 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + wire \$139 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + wire \$141 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + wire \$143 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + wire \$145 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + wire \$147 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + wire \$149 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + wire \$151 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + wire \$153 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:88" + wire \$155 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:89" + wire width 64 \$157 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:89" + wire \$158 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113" + wire width 64 \$161 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113" + wire width 8 \$162 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:13" + wire width 8 \$164 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113" + wire width 8 \$166 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \$169 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:86" + wire \$171 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:87" + wire \$173 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:107" + wire width 64 \$175 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:107" + wire width 32 \$176 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:109" + wire width 64 \$179 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:54" + wire width 64 \$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:56" + wire width 64 \$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:58" + wire width 64 \$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + wire \$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + wire \$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + wire \$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + wire \$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + wire \$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + wire \$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + wire \$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + wire \$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + wire \$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + wire \$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + wire \$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + wire \$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + wire \$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + wire \$57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + wire \$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + wire \$61 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + wire \$63 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + wire \$65 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + wire \$67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + wire \$69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + wire \$71 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + wire \$73 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + wire \$75 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + wire \$77 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + wire \$79 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + wire \$81 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + wire \$83 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + wire \$85 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + wire \$87 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + wire \$89 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + wire \$91 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + wire \$93 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + wire \$95 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + wire \$97 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + wire \$99 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:103" + wire width 32 \a32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:28" + wire width 64 \b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:55" + wire width 64 \bpermd_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:56" + wire width 64 \bpermd_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:54" + wire width 64 \bpermd_rs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:13" + wire width 7 \clz_lz + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:11" + wire width 64 \clz_sig_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:102" + wire width 64 \cntz_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:99" + wire \count_right + attribute \src "libresoc.v:136322.7-136322.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 17 \logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 39 \logical_op__data_len$18 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 2 \logical_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 output 24 \logical_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 3 \logical_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 25 \logical_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 4 \logical_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 26 \logical_op__imm_data__ok$5 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 11 \logical_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 33 \logical_op__input_carry$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 18 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 40 \logical_op__insn$19 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \logical_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 23 \logical_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 31 \logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 34 \logical_op__invert_out$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 15 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 37 \logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 16 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 38 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 7 \logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 29 \logical_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 30 \logical_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 36 \logical_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 6 \logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 28 \logical_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 5 \logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 27 \logical_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 35 \logical_op__write_cr0$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 32 \logical_op__zero_a$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 44 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 22 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 41 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 42 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:84" + wire \par0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:85" + wire \par1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:27" + wire width 64 \popcount_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:29" + wire width 64 \popcount_data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:30" + wire width 64 \popcount_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 19 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 20 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 21 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 43 \xer_so$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:54" + cell $and $and$libresoc.v:136824$6917 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \ra + connect \B \rb + connect \Y $and$libresoc.v:136824$6917_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:136783$6871 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [39:32] + connect \B \rb [39:32] + connect \Y $eq$libresoc.v:136783$6871_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:136784$6872 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [39:32] + connect \B \rb [39:32] + connect \Y $eq$libresoc.v:136784$6872_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:136785$6873 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [39:32] + connect \B \rb [39:32] + connect \Y $eq$libresoc.v:136785$6873_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:136786$6874 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [39:32] + connect \B \rb [39:32] + connect \Y $eq$libresoc.v:136786$6874_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:136787$6875 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [47:40] + connect \B \rb [47:40] + connect \Y $eq$libresoc.v:136787$6875_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:136788$6876 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [47:40] + connect \B \rb [47:40] + connect \Y $eq$libresoc.v:136788$6876_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:136789$6877 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [47:40] + connect \B \rb [47:40] + connect \Y $eq$libresoc.v:136789$6877_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:136790$6878 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [47:40] + connect \B \rb [47:40] + connect \Y $eq$libresoc.v:136790$6878_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:136791$6879 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [47:40] + connect \B \rb [47:40] + connect \Y $eq$libresoc.v:136791$6879_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:136792$6880 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [47:40] + connect \B \rb [47:40] + connect \Y $eq$libresoc.v:136792$6880_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:136793$6881 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [47:40] + connect \B \rb [47:40] + connect \Y $eq$libresoc.v:136793$6881_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:136794$6882 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [47:40] + connect \B \rb [47:40] + connect \Y $eq$libresoc.v:136794$6882_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:136795$6883 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [55:48] + connect \B \rb [55:48] + connect \Y $eq$libresoc.v:136795$6883_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:136796$6884 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [55:48] + connect \B \rb [55:48] + connect \Y $eq$libresoc.v:136796$6884_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:136797$6885 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [55:48] + connect \B \rb [55:48] + connect \Y $eq$libresoc.v:136797$6885_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:136798$6886 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [55:48] + connect \B \rb [55:48] + connect \Y $eq$libresoc.v:136798$6886_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:136799$6887 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [55:48] + connect \B \rb [55:48] + connect \Y $eq$libresoc.v:136799$6887_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:136800$6888 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [55:48] + connect \B \rb [55:48] + connect \Y $eq$libresoc.v:136800$6888_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:136801$6889 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [55:48] + connect \B \rb [55:48] + connect \Y $eq$libresoc.v:136801$6889_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:136802$6890 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [55:48] + connect \B \rb [55:48] + connect \Y $eq$libresoc.v:136802$6890_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:136803$6891 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [63:56] + connect \B \rb [63:56] + connect \Y $eq$libresoc.v:136803$6891_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:136804$6892 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [63:56] + connect \B \rb [63:56] + connect \Y $eq$libresoc.v:136804$6892_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:136805$6893 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [63:56] + connect \B \rb [63:56] + connect \Y $eq$libresoc.v:136805$6893_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:136806$6894 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [63:56] + connect \B \rb [63:56] + connect \Y $eq$libresoc.v:136806$6894_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:136807$6895 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [63:56] + connect \B \rb [63:56] + connect \Y $eq$libresoc.v:136807$6895_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:136808$6896 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [63:56] + connect \B \rb [63:56] + connect \Y $eq$libresoc.v:136808$6896_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:136809$6897 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [63:56] + connect \B \rb [63:56] + connect \Y $eq$libresoc.v:136809$6897_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:136810$6898 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [63:56] + connect \B \rb [63:56] + connect \Y $eq$libresoc.v:136810$6898_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:88" + cell $eq $eq$libresoc.v:136811$6899 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \logical_op__data_len [3] + connect \B 1'1 + connect \Y $eq$libresoc.v:136811$6899_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:136827$6920 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [7:0] + connect \B \rb [7:0] + connect \Y $eq$libresoc.v:136827$6920_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:136828$6921 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [7:0] + connect \B \rb [7:0] + connect \Y $eq$libresoc.v:136828$6921_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:136829$6922 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [7:0] + connect \B \rb [7:0] + connect \Y $eq$libresoc.v:136829$6922_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:136830$6923 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [7:0] + connect \B \rb [7:0] + connect \Y $eq$libresoc.v:136830$6923_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:136831$6924 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [7:0] + connect \B \rb [7:0] + connect \Y $eq$libresoc.v:136831$6924_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:136832$6925 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [7:0] + connect \B \rb [7:0] + connect \Y $eq$libresoc.v:136832$6925_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:136833$6926 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [7:0] + connect \B \rb [7:0] + connect \Y $eq$libresoc.v:136833$6926_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:136834$6927 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [7:0] + connect \B \rb [7:0] + connect \Y $eq$libresoc.v:136834$6927_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:136835$6928 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [15:8] + connect \B \rb [15:8] + connect \Y $eq$libresoc.v:136835$6928_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:136836$6929 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [15:8] + connect \B \rb [15:8] + connect \Y $eq$libresoc.v:136836$6929_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:136837$6930 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [15:8] + connect \B \rb [15:8] + connect \Y $eq$libresoc.v:136837$6930_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:136838$6931 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [15:8] + connect \B \rb [15:8] + connect \Y $eq$libresoc.v:136838$6931_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:136839$6932 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [15:8] + connect \B \rb [15:8] + connect \Y $eq$libresoc.v:136839$6932_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:136840$6933 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [15:8] + connect \B \rb [15:8] + connect \Y $eq$libresoc.v:136840$6933_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:136841$6934 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [15:8] + connect \B \rb [15:8] + connect \Y $eq$libresoc.v:136841$6934_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:136842$6935 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [15:8] + connect \B \rb [15:8] + connect \Y $eq$libresoc.v:136842$6935_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:136843$6936 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [23:16] + connect \B \rb [23:16] + connect \Y $eq$libresoc.v:136843$6936_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:136844$6937 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [23:16] + connect \B \rb [23:16] + connect \Y $eq$libresoc.v:136844$6937_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:136845$6938 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [23:16] + connect \B \rb [23:16] + connect \Y $eq$libresoc.v:136845$6938_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:136846$6939 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [23:16] + connect \B \rb [23:16] + connect \Y $eq$libresoc.v:136846$6939_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:136847$6940 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [23:16] + connect \B \rb [23:16] + connect \Y $eq$libresoc.v:136847$6940_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:136848$6941 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [23:16] + connect \B \rb [23:16] + connect \Y $eq$libresoc.v:136848$6941_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:136849$6942 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [23:16] + connect \B \rb [23:16] + connect \Y $eq$libresoc.v:136849$6942_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:136850$6943 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [23:16] + connect \B \rb [23:16] + connect \Y $eq$libresoc.v:136850$6943_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:136851$6944 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [31:24] + connect \B \rb [31:24] + connect \Y $eq$libresoc.v:136851$6944_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:136852$6945 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [31:24] + connect \B \rb [31:24] + connect \Y $eq$libresoc.v:136852$6945_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:136853$6946 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [31:24] + connect \B \rb [31:24] + connect \Y $eq$libresoc.v:136853$6946_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:136854$6947 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [31:24] + connect \B \rb [31:24] + connect \Y $eq$libresoc.v:136854$6947_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:136855$6948 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [31:24] + connect \B \rb [31:24] + connect \Y $eq$libresoc.v:136855$6948_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:136856$6949 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [31:24] + connect \B \rb [31:24] + connect \Y $eq$libresoc.v:136856$6949_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:136857$6950 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [31:24] + connect \B \rb [31:24] + connect \Y $eq$libresoc.v:136857$6950_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:136858$6951 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [31:24] + connect \B \rb [31:24] + connect \Y $eq$libresoc.v:136858$6951_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:136859$6952 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [39:32] + connect \B \rb [39:32] + connect \Y $eq$libresoc.v:136859$6952_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:136860$6953 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [39:32] + connect \B \rb [39:32] + connect \Y $eq$libresoc.v:136860$6953_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:136861$6954 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [39:32] + connect \B \rb [39:32] + connect \Y $eq$libresoc.v:136861$6954_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:136862$6955 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [39:32] + connect \B \rb [39:32] + connect \Y $eq$libresoc.v:136862$6955_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:89" + cell $pos $extend$libresoc.v:136813$6901 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 64 + connect \A \$158 + connect \Y $extend$libresoc.v:136813$6901_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:13" + cell $pos $extend$libresoc.v:136815$6904 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 8 + connect \A \clz_lz + connect \Y $extend$libresoc.v:136815$6904_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113" + cell $pos $extend$libresoc.v:136817$6907 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 64 + connect \A \$166 + connect \Y $extend$libresoc.v:136817$6907_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + cell $pos $extend$libresoc.v:136818$6909 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 64 + connect \A \logical_op__data_len + connect \Y $extend$libresoc.v:136818$6909_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:107" + cell $pos $extend$libresoc.v:136822$6914 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \Y_WIDTH 64 + connect \A \$176 + connect \Y $extend$libresoc.v:136822$6914_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:56" + cell $or $or$libresoc.v:136825$6918 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \ra + connect \B \rb + connect \Y $or$libresoc.v:136825$6918_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:89" + cell $pos $pos$libresoc.v:136813$6902 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:136813$6901_Y + connect \Y $pos$libresoc.v:136813$6902_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:13" + cell $pos $pos$libresoc.v:136815$6905 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $extend$libresoc.v:136815$6904_Y + connect \Y $pos$libresoc.v:136815$6905_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113" + cell $pos $pos$libresoc.v:136817$6908 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:136817$6907_Y + connect \Y $pos$libresoc.v:136817$6908_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + cell $pos $pos$libresoc.v:136818$6910 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:136818$6909_Y + connect \Y $pos$libresoc.v:136818$6910_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:107" + cell $pos $pos$libresoc.v:136822$6915 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:136822$6914_Y + connect \Y $pos$libresoc.v:136822$6915_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:86" + cell $reduce_xor $reduce_xor$libresoc.v:136819$6911 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \ra [24] \ra [16] \ra [8] \ra [0] } + connect \Y $reduce_xor$libresoc.v:136819$6911_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:87" + cell $reduce_xor $reduce_xor$libresoc.v:136820$6912 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \ra [56] \ra [48] \ra [40] \ra [32] } + connect \Y $reduce_xor$libresoc.v:136820$6912_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113" + cell $sub $sub$libresoc.v:136814$6903 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 8 + connect \A \clz_lz + connect \B 6'100000 + connect \Y $sub$libresoc.v:136814$6903_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113" + cell $mux $ternary$libresoc.v:136816$6906 + parameter \WIDTH 8 + connect \A \$164 + connect \B \$162 + connect \S \logical_op__is_32bit + connect \Y $ternary$libresoc.v:136816$6906_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:107" + cell $mux $ternary$libresoc.v:136821$6913 + parameter \WIDTH 32 + connect \A \a32 + connect \B { \a32 [0] \a32 [1] \a32 [2] \a32 [3] \a32 [4] \a32 [5] \a32 [6] \a32 [7] \a32 [8] \a32 [9] \a32 [10] \a32 [11] \a32 [12] \a32 [13] \a32 [14] \a32 [15] \a32 [16] \a32 [17] \a32 [18] \a32 [19] \a32 [20] \a32 [21] \a32 [22] \a32 [23] \a32 [24] \a32 [25] \a32 [26] \a32 [27] \a32 [28] \a32 [29] \a32 [30] \a32 [31] } + connect \S \count_right + connect \Y $ternary$libresoc.v:136821$6913_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:109" + cell $mux $ternary$libresoc.v:136823$6916 + parameter \WIDTH 64 + connect \A \ra + connect \B { \ra [0] \ra [1] \ra [2] \ra [3] \ra [4] \ra [5] \ra [6] \ra [7] \ra [8] \ra [9] \ra [10] \ra [11] \ra [12] \ra [13] \ra [14] \ra [15] \ra [16] \ra [17] \ra [18] \ra [19] \ra [20] \ra [21] \ra [22] \ra [23] \ra [24] \ra [25] \ra [26] \ra [27] \ra [28] \ra [29] \ra [30] \ra [31] \ra [32] \ra [33] \ra [34] \ra [35] \ra [36] \ra [37] \ra [38] \ra [39] \ra [40] \ra [41] \ra [42] \ra [43] \ra [44] \ra [45] \ra [46] \ra [47] \ra [48] \ra [49] \ra [50] \ra [51] \ra [52] \ra [53] \ra [54] \ra [55] \ra [56] \ra [57] \ra [58] \ra [59] \ra [60] \ra [61] \ra [62] \ra [63] } + connect \S \count_right + connect \Y $ternary$libresoc.v:136823$6916_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:89" + cell $xor $xor$libresoc.v:136812$6900 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \par0 + connect \B \par1 + connect \Y $xor$libresoc.v:136812$6900_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:58" + cell $xor $xor$libresoc.v:136826$6919 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \ra + connect \B \rb + connect \Y $xor$libresoc.v:136826$6919_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:136863.10-136867.4" + cell \bpermd \bpermd + connect \ra \bpermd_ra + connect \rb \bpermd_rb + connect \rs \bpermd_rs + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:136868.7-136871.4" + cell \clz \clz + connect \lz \clz_lz + connect \sig_in \clz_sig_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:136872.12-136876.4" + cell \popcount \popcount + connect \a \popcount_a + connect \data_len \popcount_data_len + connect \o \popcount_o + end + attribute \src "libresoc.v:136322.7-136322.20" + process $proc$libresoc.v:136322$6968 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:136877.3-136931.6" + process $proc$libresoc.v:136877$6956 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\o_ok[0:0] $1\o_ok[0:0] + assign $0\o[63:0] $1\o[63:0] + attribute \src "libresoc.v:136878.5-136878.29" + switch \initial + attribute \src "libresoc.v:136878.9-136878.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" + switch \logical_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000100 + assign $1\o_ok[0:0] 1'1 + assign { } { } + assign $1\o[63:0] \$21 + attribute \src "libresoc.v:0.0-0.0" + case 7'0110101 + assign $1\o_ok[0:0] 1'1 + assign { } { } + assign $1\o[63:0] \$23 + attribute \src "libresoc.v:0.0-0.0" + case 7'1000011 + assign $1\o_ok[0:0] 1'1 + assign { } { } + assign $1\o[63:0] \$25 + attribute \src "libresoc.v:0.0-0.0" + case 7'0001011 + assign $1\o_ok[0:0] 1'1 + assign { } { } + assign $1\o[63:0] { \$139 \$141 \$143 \$145 \$147 \$149 \$151 \$153 \$123 \$125 \$127 \$129 \$131 \$133 \$135 \$137 \$107 \$109 \$111 \$113 \$115 \$117 \$119 \$121 \$91 \$93 \$95 \$97 \$99 \$101 \$103 \$105 \$75 \$77 \$79 \$81 \$83 \$85 \$87 \$89 \$59 \$61 \$63 \$65 \$67 \$69 \$71 \$73 \$43 \$45 \$47 \$49 \$51 \$53 \$55 \$57 \$27 \$29 \$31 \$33 \$35 \$37 \$39 \$41 } + attribute \src "libresoc.v:0.0-0.0" + case 7'0110110 + assign $1\o_ok[0:0] 1'1 + assign { } { } + assign $1\o[63:0] \popcount_o + attribute \src "libresoc.v:0.0-0.0" + case 7'0110111 + assign $1\o_ok[0:0] 1'1 + assign { } { } + assign $1\o[63:0] $2\o[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:88" + switch \$155 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\o[63:0] \$157 + attribute \src "libresoc.v:0.0-0.0" + case + assign { $2\o[63:0] [63:33] $2\o[63:0] [31:1] } 62'00000000000000000000000000000000000000000000000000000000000000 + assign $2\o[63:0] [0] \par0 + assign $2\o[63:0] [32] \par1 + end + attribute \src "libresoc.v:0.0-0.0" + case 7'0001110 + assign $1\o_ok[0:0] 1'1 + assign { } { } + assign $1\o[63:0] \$161 + attribute \src "libresoc.v:0.0-0.0" + case 7'0001001 + assign $1\o_ok[0:0] 1'1 + assign { } { } + assign $1\o[63:0] \bpermd_ra + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\o_ok[0:0] 1'0 + end + sync always + update \o_ok $0\o_ok[0:0] + update \o $0\o[63:0] + end + attribute \src "libresoc.v:136932.3-136942.6" + process $proc$libresoc.v:136932$6957 + assign { } { } + assign { } { } + assign $0\clz_sig_in[63:0] $1\clz_sig_in[63:0] + attribute \src "libresoc.v:136933.5-136933.29" + switch \initial + attribute \src "libresoc.v:136933.9-136933.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" + switch \logical_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0001110 + assign { } { } + assign $1\clz_sig_in[63:0] \cntz_i + case + assign $1\clz_sig_in[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \clz_sig_in $0\clz_sig_in[63:0] + end + attribute \src "libresoc.v:136943.3-136953.6" + process $proc$libresoc.v:136943$6958 + assign { } { } + assign { } { } + assign $0\bpermd_rs[63:0] $1\bpermd_rs[63:0] + attribute \src "libresoc.v:136944.5-136944.29" + switch \initial + attribute \src "libresoc.v:136944.9-136944.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" + switch \logical_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0001001 + assign { } { } + assign $1\bpermd_rs[63:0] \ra + case + assign $1\bpermd_rs[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \bpermd_rs $0\bpermd_rs[63:0] + end + attribute \src "libresoc.v:136954.3-136964.6" + process $proc$libresoc.v:136954$6959 + assign { } { } + assign { } { } + assign $0\bpermd_rb[63:0] $1\bpermd_rb[63:0] + attribute \src "libresoc.v:136955.5-136955.29" + switch \initial + attribute \src "libresoc.v:136955.9-136955.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" + switch \logical_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0001001 + assign { } { } + assign $1\bpermd_rb[63:0] \rb + case + assign $1\bpermd_rb[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \bpermd_rb $0\bpermd_rb[63:0] + end + attribute \src "libresoc.v:136965.3-136975.6" + process $proc$libresoc.v:136965$6960 + assign { } { } + assign { } { } + assign $0\popcount_a[63:0] $1\popcount_a[63:0] + attribute \src "libresoc.v:136966.5-136966.29" + switch \initial + attribute \src "libresoc.v:136966.9-136966.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" + switch \logical_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0110110 + assign { } { } + assign $1\popcount_a[63:0] \ra + case + assign $1\popcount_a[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \popcount_a $0\popcount_a[63:0] + end + attribute \src "libresoc.v:136976.3-136986.6" + process $proc$libresoc.v:136976$6961 + assign { } { } + assign { } { } + assign $0\b[63:0] $1\b[63:0] + attribute \src "libresoc.v:136977.5-136977.29" + switch \initial + attribute \src "libresoc.v:136977.9-136977.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" + switch \logical_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0110110 + assign { } { } + assign $1\b[63:0] \rb + case + assign $1\b[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \b $0\b[63:0] + end + attribute \src "libresoc.v:136987.3-136997.6" + process $proc$libresoc.v:136987$6962 + assign { } { } + assign { } { } + assign $0\popcount_data_len[63:0] $1\popcount_data_len[63:0] + attribute \src "libresoc.v:136988.5-136988.29" + switch \initial + attribute \src "libresoc.v:136988.9-136988.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" + switch \logical_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0110110 + assign { } { } + assign $1\popcount_data_len[63:0] \$169 + case + assign $1\popcount_data_len[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \popcount_data_len $0\popcount_data_len[63:0] + end + attribute \src "libresoc.v:136998.3-137008.6" + process $proc$libresoc.v:136998$6963 + assign { } { } + assign { } { } + assign $0\par0[0:0] $1\par0[0:0] + attribute \src "libresoc.v:136999.5-136999.29" + switch \initial + attribute \src "libresoc.v:136999.9-136999.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" + switch \logical_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0110111 + assign { } { } + assign $1\par0[0:0] \$171 + case + assign $1\par0[0:0] 1'0 + end + sync always + update \par0 $0\par0[0:0] + end + attribute \src "libresoc.v:137009.3-137019.6" + process $proc$libresoc.v:137009$6964 + assign { } { } + assign { } { } + assign $0\par1[0:0] $1\par1[0:0] + attribute \src "libresoc.v:137010.5-137010.29" + switch \initial + attribute \src "libresoc.v:137010.9-137010.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" + switch \logical_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0110111 + assign { } { } + assign $1\par1[0:0] \$173 + case + assign $1\par1[0:0] 1'0 + end + sync always + update \par1 $0\par1[0:0] + end + attribute \src "libresoc.v:137020.3-137030.6" + process $proc$libresoc.v:137020$6965 + assign { } { } + assign { } { } + assign $0\count_right[0:0] $1\count_right[0:0] + attribute \src "libresoc.v:137021.5-137021.29" + switch \initial + attribute \src "libresoc.v:137021.9-137021.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" + switch \logical_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0001110 + assign { } { } + assign $1\count_right[0:0] \logical_op__insn [10] + case + assign $1\count_right[0:0] 1'0 + end + sync always + update \count_right $0\count_right[0:0] + end + attribute \src "libresoc.v:137031.3-137041.6" + process $proc$libresoc.v:137031$6966 + assign { } { } + assign { } { } + assign $0\a32[31:0] $1\a32[31:0] + attribute \src "libresoc.v:137032.5-137032.29" + switch \initial + attribute \src "libresoc.v:137032.9-137032.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" + switch \logical_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0001110 + assign { } { } + assign $1\a32[31:0] \ra [31:0] + case + assign $1\a32[31:0] 0 + end + sync always + update \a32 $0\a32[31:0] + end + attribute \src "libresoc.v:137042.3-137060.6" + process $proc$libresoc.v:137042$6967 + assign { } { } + assign { } { } + assign $0\cntz_i[63:0] $1\cntz_i[63:0] + attribute \src "libresoc.v:137043.5-137043.29" + switch \initial + attribute \src "libresoc.v:137043.9-137043.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" + switch \logical_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0001110 + assign { } { } + assign $1\cntz_i[63:0] $2\cntz_i[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:106" + switch \logical_op__is_32bit + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cntz_i[63:0] \$175 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cntz_i[63:0] \$179 + end + case + assign $1\cntz_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \cntz_i $0\cntz_i[63:0] + end + connect \$99 $eq$libresoc.v:136783$6871_Y + connect \$101 $eq$libresoc.v:136784$6872_Y + connect \$103 $eq$libresoc.v:136785$6873_Y + connect \$105 $eq$libresoc.v:136786$6874_Y + connect \$107 $eq$libresoc.v:136787$6875_Y + connect \$109 $eq$libresoc.v:136788$6876_Y + connect \$111 $eq$libresoc.v:136789$6877_Y + connect \$113 $eq$libresoc.v:136790$6878_Y + connect \$115 $eq$libresoc.v:136791$6879_Y + connect \$117 $eq$libresoc.v:136792$6880_Y + connect \$119 $eq$libresoc.v:136793$6881_Y + connect \$121 $eq$libresoc.v:136794$6882_Y + connect \$123 $eq$libresoc.v:136795$6883_Y + connect \$125 $eq$libresoc.v:136796$6884_Y + connect \$127 $eq$libresoc.v:136797$6885_Y + connect \$129 $eq$libresoc.v:136798$6886_Y + connect \$131 $eq$libresoc.v:136799$6887_Y + connect \$133 $eq$libresoc.v:136800$6888_Y + connect \$135 $eq$libresoc.v:136801$6889_Y + connect \$137 $eq$libresoc.v:136802$6890_Y + connect \$139 $eq$libresoc.v:136803$6891_Y + connect \$141 $eq$libresoc.v:136804$6892_Y + connect \$143 $eq$libresoc.v:136805$6893_Y + connect \$145 $eq$libresoc.v:136806$6894_Y + connect \$147 $eq$libresoc.v:136807$6895_Y + connect \$149 $eq$libresoc.v:136808$6896_Y + connect \$151 $eq$libresoc.v:136809$6897_Y + connect \$153 $eq$libresoc.v:136810$6898_Y + connect \$155 $eq$libresoc.v:136811$6899_Y + connect \$158 $xor$libresoc.v:136812$6900_Y + connect \$157 $pos$libresoc.v:136813$6902_Y + connect \$162 $sub$libresoc.v:136814$6903_Y + connect \$164 $pos$libresoc.v:136815$6905_Y + connect \$166 $ternary$libresoc.v:136816$6906_Y + connect \$161 $pos$libresoc.v:136817$6908_Y + connect \$169 $pos$libresoc.v:136818$6910_Y + connect \$171 $reduce_xor$libresoc.v:136819$6911_Y + connect \$173 $reduce_xor$libresoc.v:136820$6912_Y + connect \$176 $ternary$libresoc.v:136821$6913_Y + connect \$175 $pos$libresoc.v:136822$6915_Y + connect \$179 $ternary$libresoc.v:136823$6916_Y + connect \$21 $and$libresoc.v:136824$6917_Y + connect \$23 $or$libresoc.v:136825$6918_Y + connect \$25 $xor$libresoc.v:136826$6919_Y + connect \$27 $eq$libresoc.v:136827$6920_Y + connect \$29 $eq$libresoc.v:136828$6921_Y + connect \$31 $eq$libresoc.v:136829$6922_Y + connect \$33 $eq$libresoc.v:136830$6923_Y + connect \$35 $eq$libresoc.v:136831$6924_Y + connect \$37 $eq$libresoc.v:136832$6925_Y + connect \$39 $eq$libresoc.v:136833$6926_Y + connect \$41 $eq$libresoc.v:136834$6927_Y + connect \$43 $eq$libresoc.v:136835$6928_Y + connect \$45 $eq$libresoc.v:136836$6929_Y + connect \$47 $eq$libresoc.v:136837$6930_Y + connect \$49 $eq$libresoc.v:136838$6931_Y + connect \$51 $eq$libresoc.v:136839$6932_Y + connect \$53 $eq$libresoc.v:136840$6933_Y + connect \$55 $eq$libresoc.v:136841$6934_Y + connect \$57 $eq$libresoc.v:136842$6935_Y + connect \$59 $eq$libresoc.v:136843$6936_Y + connect \$61 $eq$libresoc.v:136844$6937_Y + connect \$63 $eq$libresoc.v:136845$6938_Y + connect \$65 $eq$libresoc.v:136846$6939_Y + connect \$67 $eq$libresoc.v:136847$6940_Y + connect \$69 $eq$libresoc.v:136848$6941_Y + connect \$71 $eq$libresoc.v:136849$6942_Y + connect \$73 $eq$libresoc.v:136850$6943_Y + connect \$75 $eq$libresoc.v:136851$6944_Y + connect \$77 $eq$libresoc.v:136852$6945_Y + connect \$79 $eq$libresoc.v:136853$6946_Y + connect \$81 $eq$libresoc.v:136854$6947_Y + connect \$83 $eq$libresoc.v:136855$6948_Y + connect \$85 $eq$libresoc.v:136856$6949_Y + connect \$87 $eq$libresoc.v:136857$6950_Y + connect \$89 $eq$libresoc.v:136858$6951_Y + connect \$91 $eq$libresoc.v:136859$6952_Y + connect \$93 $eq$libresoc.v:136860$6953_Y + connect \$95 $eq$libresoc.v:136861$6954_Y + connect \$97 $eq$libresoc.v:136862$6955_Y + connect { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } + connect \muxid$1 \muxid + connect \xer_so$20 \xer_so +end +attribute \src "libresoc.v:137068.1-137577.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.alu_cr0.pipe.main" +attribute \generator "nMigen" +module \main$9 + attribute \src "libresoc.v:137432.3-137442.6" + wire width 2 $0\BC[1:0] + attribute \src "libresoc.v:137486.3-137496.6" + wire width 2 $0\ba[1:0] + attribute \src "libresoc.v:137497.3-137507.6" + wire width 2 $0\bb[1:0] + attribute \src "libresoc.v:137508.3-137528.6" + wire $0\bit_a[0:0] + attribute \src "libresoc.v:137529.3-137549.6" + wire $0\bit_b[0:0] + attribute \src "libresoc.v:137550.3-137560.6" + wire $0\bit_o[0:0] + attribute \src "libresoc.v:137475.3-137485.6" + wire width 2 $0\bt[1:0] + attribute \src "libresoc.v:137344.3-137378.6" + wire width 4 $0\cr_a$6[3:0]$6983 + attribute \src "libresoc.v:137344.3-137378.6" + wire $0\cr_a_ok[0:0] + attribute \src "libresoc.v:137443.3-137463.6" + wire $0\cr_bit[0:0] + attribute \src "libresoc.v:137561.3-137571.6" + wire width 32 $0\full_cr$5[31:0]$6998 + attribute \src "libresoc.v:137379.3-137389.6" + wire $0\full_cr_ok[0:0] + attribute \src "libresoc.v:137069.7-137069.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:137464.3-137474.6" + wire width 4 $0\lut[3:0] + attribute \src "libresoc.v:137390.3-137431.6" + wire width 64 $0\o[63:0] + attribute \src "libresoc.v:137390.3-137431.6" + wire $0\o_ok[0:0] + attribute \src "libresoc.v:137432.3-137442.6" + wire width 2 $1\BC[1:0] + attribute \src "libresoc.v:137486.3-137496.6" + wire width 2 $1\ba[1:0] + attribute \src "libresoc.v:137497.3-137507.6" + wire width 2 $1\bb[1:0] + attribute \src "libresoc.v:137508.3-137528.6" + wire $1\bit_a[0:0] + attribute \src "libresoc.v:137529.3-137549.6" + wire $1\bit_b[0:0] + attribute \src "libresoc.v:137550.3-137560.6" + wire $1\bit_o[0:0] + attribute \src "libresoc.v:137475.3-137485.6" + wire width 2 $1\bt[1:0] + attribute \src "libresoc.v:137344.3-137378.6" + wire width 4 $1\cr_a$6[3:0]$6984 + attribute \src "libresoc.v:137344.3-137378.6" + wire $1\cr_a_ok[0:0] + attribute \src "libresoc.v:137443.3-137463.6" + wire $1\cr_bit[0:0] + attribute \src "libresoc.v:137561.3-137571.6" + wire width 32 $1\full_cr$5[31:0]$6999 + attribute \src "libresoc.v:137379.3-137389.6" + wire $1\full_cr_ok[0:0] + attribute \src "libresoc.v:137464.3-137474.6" + wire width 4 $1\lut[3:0] + attribute \src "libresoc.v:137390.3-137431.6" + wire width 64 $1\o[63:0] + attribute \src "libresoc.v:137390.3-137431.6" + wire $1\o_ok[0:0] + attribute \src "libresoc.v:137508.3-137528.6" + wire $2\bit_a[0:0] + attribute \src "libresoc.v:137529.3-137549.6" + wire $2\bit_b[0:0] + attribute \src "libresoc.v:137344.3-137378.6" + wire width 4 $2\cr_a$6[3:0]$6985 + attribute \src "libresoc.v:137443.3-137463.6" + wire $2\cr_bit[0:0] + attribute \src "libresoc.v:137390.3-137431.6" + wire width 64 $2\o[63:0] + attribute \src "libresoc.v:137340.18-137340.96" + wire width 64 $extend$libresoc.v:137340$6975_Y + attribute \src "libresoc.v:137342.18-137342.98" + wire width 65 $extend$libresoc.v:137342$6978_Y + attribute \src "libresoc.v:137343.17-137343.92" + wire width 5 $extend$libresoc.v:137343$6980_Y + attribute \src "libresoc.v:137340.18-137340.96" + wire width 64 $pos$libresoc.v:137340$6976_Y + attribute \src "libresoc.v:137342.18-137342.98" + wire width 65 $pos$libresoc.v:137342$6979_Y + attribute \src "libresoc.v:137343.17-137343.92" + wire width 5 $pos$libresoc.v:137343$6981_Y + attribute \src "libresoc.v:137334.18-137334.116" + wire width 3 $sub$libresoc.v:137334$6969_Y + attribute \src "libresoc.v:137335.18-137335.116" + wire width 3 $sub$libresoc.v:137335$6970_Y + attribute \src "libresoc.v:137336.18-137336.116" + wire width 3 $sub$libresoc.v:137336$6971_Y + attribute \src "libresoc.v:137337.18-137337.114" + wire $ternary$libresoc.v:137337$6972_Y + attribute \src "libresoc.v:137338.18-137338.115" + wire $ternary$libresoc.v:137338$6973_Y + attribute \src "libresoc.v:137339.18-137339.112" + wire $ternary$libresoc.v:137339$6974_Y + attribute \src "libresoc.v:137341.18-137341.108" + wire width 64 $ternary$libresoc.v:137341$6977_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:86" + wire width 3 \$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:87" + wire width 3 \$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:87" + wire width 3 \$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:88" + wire width 3 \$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:88" + wire width 3 \$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:99" + wire \$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:100" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:100" + wire \$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:140" + wire width 65 \$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:140" + wire width 64 \$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 5 \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:86" + wire width 3 \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:131" + wire width 2 \BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:82" + wire width 2 \ba + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:83" + wire width 2 \bb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:91" + wire \bit_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:92" + wire \bit_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:97" + wire \bit_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:81" + wire width 2 \bt + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 4 input 7 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 output 18 \cr_a$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 19 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 4 input 8 \cr_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:136" + wire \cr_bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 4 input 9 \cr_c + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 2 \cr_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 output 12 \cr_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 3 \cr_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 13 \cr_op__insn$4 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \cr_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 11 \cr_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 32 input 6 \full_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 32 output 16 \full_cr$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 17 \full_cr_ok + attribute \src "libresoc.v:137069.7-137069.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:70" + wire width 4 \lut + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 20 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 10 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 14 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 15 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 4 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 5 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + cell $pos $extend$libresoc.v:137340$6975 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \Y_WIDTH 64 + connect \A \full_cr + connect \Y $extend$libresoc.v:137340$6975_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:140" + cell $pos $extend$libresoc.v:137342$6978 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \$27 + connect \Y $extend$libresoc.v:137342$6978_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + cell $pos $extend$libresoc.v:137343$6980 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 5 + connect \A \cr_a + connect \Y $extend$libresoc.v:137343$6980_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + cell $pos $pos$libresoc.v:137340$6976 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:137340$6975_Y + connect \Y $pos$libresoc.v:137340$6976_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:140" + cell $pos $pos$libresoc.v:137342$6979 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \Y_WIDTH 65 + connect \A $extend$libresoc.v:137342$6978_Y + connect \Y $pos$libresoc.v:137342$6979_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + cell $pos $pos$libresoc.v:137343$6981 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A $extend$libresoc.v:137343$6980_Y + connect \Y $pos$libresoc.v:137343$6981_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:86" + cell $sub $sub$libresoc.v:137334$6969 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 3 + connect \A 2'11 + connect \B \cr_op__insn [22:21] + connect \Y $sub$libresoc.v:137334$6969_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:87" + cell $sub $sub$libresoc.v:137335$6970 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 3 + connect \A 2'11 + connect \B \cr_op__insn [17:16] + connect \Y $sub$libresoc.v:137335$6970_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:88" + cell $sub $sub$libresoc.v:137336$6971 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 3 + connect \A 2'11 + connect \B \cr_op__insn [12:11] + connect \Y $sub$libresoc.v:137336$6971_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:99" + cell $mux $ternary$libresoc.v:137337$6972 + parameter \WIDTH 1 + connect \A \lut [1] + connect \B \lut [3] + connect \S \bit_a + connect \Y $ternary$libresoc.v:137337$6972_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:100" + cell $mux $ternary$libresoc.v:137338$6973 + parameter \WIDTH 1 + connect \A \lut [0] + connect \B \lut [2] + connect \S \bit_a + connect \Y $ternary$libresoc.v:137338$6973_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:100" + cell $mux $ternary$libresoc.v:137339$6974 + parameter \WIDTH 1 + connect \A \$20 + connect \B \$18 + connect \S \bit_b + connect \Y $ternary$libresoc.v:137339$6974_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:140" + cell $mux $ternary$libresoc.v:137341$6977 + parameter \WIDTH 64 + connect \A \rb + connect \B \ra + connect \S \cr_bit + connect \Y $ternary$libresoc.v:137341$6977_Y + end + attribute \src "libresoc.v:137069.7-137069.20" + process $proc$libresoc.v:137069$7000 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:137344.3-137378.6" + process $proc$libresoc.v:137344$6982 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\cr_a_ok[0:0] $1\cr_a_ok[0:0] + assign $0\cr_a$6[3:0]$6983 $1\cr_a$6[3:0]$6984 + attribute \src "libresoc.v:137345.5-137345.29" + switch \initial + attribute \src "libresoc.v:137345.9-137345.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" + switch \cr_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0101010 + assign { } { } + assign { } { } + assign $1\cr_a$6[3:0]$6984 \$7 [3:0] + assign $1\cr_a_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 7'1000101 + assign { } { } + assign { } { } + assign { } { } + assign $1\cr_a$6[3:0]$6984 $2\cr_a$6[3:0]$6985 + assign $1\cr_a_ok[0:0] 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:105" + switch \bt + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign $2\cr_a$6[3:0]$6985 [3:1] \cr_c [3:1] + assign $2\cr_a$6[3:0]$6985 [0] \bit_o + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { $2\cr_a$6[3:0]$6985 [3:2] $2\cr_a$6[3:0]$6985 [0] } { \cr_c [3:2] \cr_c [0] } + assign $2\cr_a$6[3:0]$6985 [1] \bit_o + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { $2\cr_a$6[3:0]$6985 [3] $2\cr_a$6[3:0]$6985 [1:0] } { \cr_c [3] \cr_c [1:0] } + assign $2\cr_a$6[3:0]$6985 [2] \bit_o + attribute \src "libresoc.v:0.0-0.0" + case 2'-- + assign $2\cr_a$6[3:0]$6985 [2:0] \cr_c [2:0] + assign $2\cr_a$6[3:0]$6985 [3] \bit_o + case + assign $2\cr_a$6[3:0]$6985 \cr_c + end + case + assign $1\cr_a_ok[0:0] 1'0 + assign $1\cr_a$6[3:0]$6984 4'0000 + end + sync always + update \cr_a_ok $0\cr_a_ok[0:0] + update \cr_a$6 $0\cr_a$6[3:0]$6983 + end + attribute \src "libresoc.v:137379.3-137389.6" + process $proc$libresoc.v:137379$6986 + assign { } { } + assign { } { } + assign $0\full_cr_ok[0:0] $1\full_cr_ok[0:0] + attribute \src "libresoc.v:137380.5-137380.29" + switch \initial + attribute \src "libresoc.v:137380.9-137380.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" + switch \cr_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0110000 + assign { } { } + assign $1\full_cr_ok[0:0] 1'1 + case + assign $1\full_cr_ok[0:0] 1'0 + end + sync always + update \full_cr_ok $0\full_cr_ok[0:0] + end + attribute \src "libresoc.v:137390.3-137431.6" + process $proc$libresoc.v:137390$6987 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\o_ok[0:0] $1\o_ok[0:0] + assign $0\o[63:0] $1\o[63:0] + attribute \src "libresoc.v:137391.5-137391.29" + switch \initial + attribute \src "libresoc.v:137391.9-137391.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" + switch \cr_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0101101 + assign { } { } + assign { } { } + assign $1\o[63:0] \$24 + assign $1\o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 7'0100011 + assign { } { } + assign { } { } + assign $1\o[63:0] \$26 [63:0] + assign $1\o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 7'0111011 + assign { } { } + assign { } { } + assign $1\o[63:0] $2\o[63:0] + assign $1\o_ok[0:0] 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:144" + switch { \cr_a [2] \cr_a [3] } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $2\o[63:0] 64'1111111111111111111111111111111111111111111111111111111111111111 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $2\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000001 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + case + assign $1\o_ok[0:0] 1'0 + assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \o_ok $0\o_ok[0:0] + update \o $0\o[63:0] + end + attribute \src "libresoc.v:137432.3-137442.6" + process $proc$libresoc.v:137432$6988 + assign { } { } + assign { } { } + assign $0\BC[1:0] $1\BC[1:0] + attribute \src "libresoc.v:137433.5-137433.29" + switch \initial + attribute \src "libresoc.v:137433.9-137433.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" + switch \cr_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0100011 + assign { } { } + assign $1\BC[1:0] \cr_op__insn [7:6] + case + assign $1\BC[1:0] 2'00 + end + sync always + update \BC $0\BC[1:0] + end + attribute \src "libresoc.v:137443.3-137463.6" + process $proc$libresoc.v:137443$6989 + assign { } { } + assign { } { } + assign $0\cr_bit[0:0] $1\cr_bit[0:0] + attribute \src "libresoc.v:137444.5-137444.29" + switch \initial + attribute \src "libresoc.v:137444.9-137444.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" + switch \cr_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0100011 + assign { } { } + assign $1\cr_bit[0:0] $2\cr_bit[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:137" + switch \BC + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $2\cr_bit[0:0] \cr_a [3] + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $2\cr_bit[0:0] \cr_a [2] + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $2\cr_bit[0:0] \cr_a [1] + attribute \src "libresoc.v:0.0-0.0" + case 2'-- + assign { } { } + assign $2\cr_bit[0:0] \cr_a [0] + case + assign $2\cr_bit[0:0] 1'0 + end + case + assign $1\cr_bit[0:0] 1'0 + end + sync always + update \cr_bit $0\cr_bit[0:0] + end + attribute \src "libresoc.v:137464.3-137474.6" + process $proc$libresoc.v:137464$6990 + assign { } { } + assign { } { } + assign $0\lut[3:0] $1\lut[3:0] + attribute \src "libresoc.v:137465.5-137465.29" + switch \initial + attribute \src "libresoc.v:137465.9-137465.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" + switch \cr_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'1000101 + assign { } { } + assign $1\lut[3:0] \cr_op__insn [9:6] + case + assign $1\lut[3:0] 4'0000 + end + sync always + update \lut $0\lut[3:0] + end + attribute \src "libresoc.v:137475.3-137485.6" + process $proc$libresoc.v:137475$6991 + assign { } { } + assign { } { } + assign $0\bt[1:0] $1\bt[1:0] + attribute \src "libresoc.v:137476.5-137476.29" + switch \initial + attribute \src "libresoc.v:137476.9-137476.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" + switch \cr_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'1000101 + assign { } { } + assign $1\bt[1:0] \$9 [1:0] + case + assign $1\bt[1:0] 2'00 + end + sync always + update \bt $0\bt[1:0] + end + attribute \src "libresoc.v:137486.3-137496.6" + process $proc$libresoc.v:137486$6992 + assign { } { } + assign { } { } + assign $0\ba[1:0] $1\ba[1:0] + attribute \src "libresoc.v:137487.5-137487.29" + switch \initial + attribute \src "libresoc.v:137487.9-137487.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" + switch \cr_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'1000101 + assign { } { } + assign $1\ba[1:0] \$12 [1:0] + case + assign $1\ba[1:0] 2'00 + end + sync always + update \ba $0\ba[1:0] + end + attribute \src "libresoc.v:137497.3-137507.6" + process $proc$libresoc.v:137497$6993 + assign { } { } + assign { } { } + assign $0\bb[1:0] $1\bb[1:0] + attribute \src "libresoc.v:137498.5-137498.29" + switch \initial + attribute \src "libresoc.v:137498.9-137498.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" + switch \cr_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'1000101 + assign { } { } + assign $1\bb[1:0] \$15 [1:0] + case + assign $1\bb[1:0] 2'00 + end + sync always + update \bb $0\bb[1:0] + end + attribute \src "libresoc.v:137508.3-137528.6" + process $proc$libresoc.v:137508$6994 + assign { } { } + assign { } { } + assign $0\bit_a[0:0] $1\bit_a[0:0] + attribute \src "libresoc.v:137509.5-137509.29" + switch \initial + attribute \src "libresoc.v:137509.9-137509.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" + switch \cr_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'1000101 + assign { } { } + assign $1\bit_a[0:0] $2\bit_a[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:93" + switch \ba + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $2\bit_a[0:0] \cr_a [0] + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $2\bit_a[0:0] \cr_a [1] + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $2\bit_a[0:0] \cr_a [2] + attribute \src "libresoc.v:0.0-0.0" + case 2'-- + assign { } { } + assign $2\bit_a[0:0] \cr_a [3] + case + assign $2\bit_a[0:0] 1'0 + end + case + assign $1\bit_a[0:0] 1'0 + end + sync always + update \bit_a $0\bit_a[0:0] + end + attribute \src "libresoc.v:137529.3-137549.6" + process $proc$libresoc.v:137529$6995 + assign { } { } + assign { } { } + assign $0\bit_b[0:0] $1\bit_b[0:0] + attribute \src "libresoc.v:137530.5-137530.29" + switch \initial + attribute \src "libresoc.v:137530.9-137530.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" + switch \cr_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'1000101 + assign { } { } + assign $1\bit_b[0:0] $2\bit_b[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:94" + switch \bb + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $2\bit_b[0:0] \cr_b [0] + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $2\bit_b[0:0] \cr_b [1] + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $2\bit_b[0:0] \cr_b [2] + attribute \src "libresoc.v:0.0-0.0" + case 2'-- + assign { } { } + assign $2\bit_b[0:0] \cr_b [3] + case + assign $2\bit_b[0:0] 1'0 + end + case + assign $1\bit_b[0:0] 1'0 + end + sync always + update \bit_b $0\bit_b[0:0] + end + attribute \src "libresoc.v:137550.3-137560.6" + process $proc$libresoc.v:137550$6996 + assign { } { } + assign { } { } + assign $0\bit_o[0:0] $1\bit_o[0:0] + attribute \src "libresoc.v:137551.5-137551.29" + switch \initial + attribute \src "libresoc.v:137551.9-137551.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" + switch \cr_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'1000101 + assign { } { } + assign $1\bit_o[0:0] \$22 + case + assign $1\bit_o[0:0] 1'0 + end + sync always + update \bit_o $0\bit_o[0:0] + end + attribute \src "libresoc.v:137561.3-137571.6" + process $proc$libresoc.v:137561$6997 + assign { } { } + assign { } { } + assign $0\full_cr$5[31:0]$6998 $1\full_cr$5[31:0]$6999 + attribute \src "libresoc.v:137562.5-137562.29" + switch \initial + attribute \src "libresoc.v:137562.9-137562.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" + switch \cr_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0110000 + assign { } { } + assign $1\full_cr$5[31:0]$6999 \ra [31:0] + case + assign $1\full_cr$5[31:0]$6999 0 + end + sync always + update \full_cr$5 $0\full_cr$5[31:0]$6998 + end + connect \$10 $sub$libresoc.v:137334$6969_Y + connect \$13 $sub$libresoc.v:137335$6970_Y + connect \$16 $sub$libresoc.v:137336$6971_Y + connect \$18 $ternary$libresoc.v:137337$6972_Y + connect \$20 $ternary$libresoc.v:137338$6973_Y + connect \$22 $ternary$libresoc.v:137339$6974_Y + connect \$24 $pos$libresoc.v:137340$6976_Y + connect \$27 $ternary$libresoc.v:137341$6977_Y + connect \$26 $pos$libresoc.v:137342$6979_Y + connect \$7 $pos$libresoc.v:137343$6981_Y + connect \$9 \$10 + connect \$12 \$13 + connect \$15 \$16 + connect { \cr_op__insn$4 \cr_op__fn_unit$3 \cr_op__insn_type$2 } { \cr_op__insn \cr_op__fn_unit \cr_op__insn_type } + connect \muxid$1 \muxid +end +attribute \src "libresoc.v:137581.1-138736.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.mul0" +attribute \generator "nMigen" +module \mul0 + attribute \src "libresoc.v:138307.3-138308.25" + wire $0\all_rd_dly[0:0] + attribute \src "libresoc.v:138305.3-138306.40" + wire $0\alu_done_dly[0:0] + attribute \src "libresoc.v:138648.3-138656.6" + wire $0\alu_l_r_alu$next[0:0]$7206 + attribute \src "libresoc.v:138233.3-138234.39" + wire $0\alu_l_r_alu[0:0] + attribute \src "libresoc.v:138488.3-138520.6" + wire width 12 $0\alu_mul0_mul_op__fn_unit$next[11:0]$7131 + attribute \src "libresoc.v:138261.3-138262.65" + wire width 12 $0\alu_mul0_mul_op__fn_unit[11:0] + attribute \src "libresoc.v:138488.3-138520.6" + wire width 64 $0\alu_mul0_mul_op__imm_data__data$next[63:0]$7132 + attribute \src "libresoc.v:138263.3-138264.79" + wire width 64 $0\alu_mul0_mul_op__imm_data__data[63:0] + attribute \src "libresoc.v:138488.3-138520.6" + wire $0\alu_mul0_mul_op__imm_data__ok$next[0:0]$7133 + attribute \src "libresoc.v:138265.3-138266.75" + wire $0\alu_mul0_mul_op__imm_data__ok[0:0] + attribute \src "libresoc.v:138488.3-138520.6" + wire width 32 $0\alu_mul0_mul_op__insn$next[31:0]$7134 + attribute \src "libresoc.v:138281.3-138282.59" + wire width 32 $0\alu_mul0_mul_op__insn[31:0] + attribute \src "libresoc.v:138488.3-138520.6" + wire width 7 $0\alu_mul0_mul_op__insn_type$next[6:0]$7135 + attribute \src "libresoc.v:138259.3-138260.69" + wire width 7 $0\alu_mul0_mul_op__insn_type[6:0] + attribute \src "libresoc.v:138488.3-138520.6" + wire $0\alu_mul0_mul_op__is_32bit$next[0:0]$7136 + attribute \src "libresoc.v:138277.3-138278.67" + wire $0\alu_mul0_mul_op__is_32bit[0:0] + attribute \src "libresoc.v:138488.3-138520.6" + wire $0\alu_mul0_mul_op__is_signed$next[0:0]$7137 + attribute \src "libresoc.v:138279.3-138280.69" + wire $0\alu_mul0_mul_op__is_signed[0:0] + attribute \src "libresoc.v:138488.3-138520.6" + wire $0\alu_mul0_mul_op__oe__oe$next[0:0]$7138 + attribute \src "libresoc.v:138271.3-138272.63" + wire $0\alu_mul0_mul_op__oe__oe[0:0] + attribute \src "libresoc.v:138488.3-138520.6" + wire $0\alu_mul0_mul_op__oe__ok$next[0:0]$7139 + attribute \src "libresoc.v:138273.3-138274.63" + wire $0\alu_mul0_mul_op__oe__ok[0:0] + attribute \src "libresoc.v:138488.3-138520.6" + wire $0\alu_mul0_mul_op__rc__ok$next[0:0]$7140 + attribute \src "libresoc.v:138269.3-138270.63" + wire $0\alu_mul0_mul_op__rc__ok[0:0] + attribute \src "libresoc.v:138488.3-138520.6" + wire $0\alu_mul0_mul_op__rc__rc$next[0:0]$7141 + attribute \src "libresoc.v:138267.3-138268.63" + wire $0\alu_mul0_mul_op__rc__rc[0:0] + attribute \src "libresoc.v:138488.3-138520.6" + wire $0\alu_mul0_mul_op__write_cr0$next[0:0]$7142 + attribute \src "libresoc.v:138275.3-138276.69" + wire $0\alu_mul0_mul_op__write_cr0[0:0] + attribute \src "libresoc.v:138639.3-138647.6" + wire $0\alui_l_r_alui$next[0:0]$7203 + attribute \src "libresoc.v:138235.3-138236.43" + wire $0\alui_l_r_alui[0:0] + attribute \src "libresoc.v:138521.3-138542.6" + wire width 64 $0\data_r0__o$next[63:0]$7162 + attribute \src "libresoc.v:138255.3-138256.37" + wire width 64 $0\data_r0__o[63:0] + attribute \src "libresoc.v:138521.3-138542.6" + wire $0\data_r0__o_ok$next[0:0]$7163 + attribute \src "libresoc.v:138257.3-138258.43" + wire $0\data_r0__o_ok[0:0] + attribute \src "libresoc.v:138543.3-138564.6" + wire width 4 $0\data_r1__cr_a$next[3:0]$7170 + attribute \src "libresoc.v:138251.3-138252.43" + wire width 4 $0\data_r1__cr_a[3:0] + attribute \src "libresoc.v:138543.3-138564.6" + wire $0\data_r1__cr_a_ok$next[0:0]$7171 + attribute \src "libresoc.v:138253.3-138254.49" + wire $0\data_r1__cr_a_ok[0:0] + attribute \src "libresoc.v:138565.3-138586.6" + wire width 2 $0\data_r2__xer_ov$next[1:0]$7178 + attribute \src "libresoc.v:138247.3-138248.47" + wire width 2 $0\data_r2__xer_ov[1:0] + attribute \src "libresoc.v:138565.3-138586.6" + wire $0\data_r2__xer_ov_ok$next[0:0]$7179 + attribute \src "libresoc.v:138249.3-138250.53" + wire $0\data_r2__xer_ov_ok[0:0] + attribute \src "libresoc.v:138587.3-138608.6" + wire $0\data_r3__xer_so$next[0:0]$7186 + attribute \src "libresoc.v:138243.3-138244.47" + wire $0\data_r3__xer_so[0:0] + attribute \src "libresoc.v:138587.3-138608.6" + wire $0\data_r3__xer_so_ok$next[0:0]$7187 + attribute \src "libresoc.v:138245.3-138246.53" + wire $0\data_r3__xer_so_ok[0:0] + attribute \src "libresoc.v:138657.3-138666.6" + wire width 64 $0\dest1_o[63:0] + attribute \src "libresoc.v:138667.3-138676.6" + wire width 4 $0\dest2_o[3:0] + attribute \src "libresoc.v:138677.3-138686.6" + wire width 2 $0\dest3_o[1:0] + attribute \src "libresoc.v:138687.3-138696.6" + wire $0\dest4_o[0:0] + attribute \src "libresoc.v:137582.7-137582.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:138443.3-138451.6" + wire $0\opc_l_r_opc$next[0:0]$7116 + attribute \src "libresoc.v:138291.3-138292.39" + wire $0\opc_l_r_opc[0:0] + attribute \src "libresoc.v:138434.3-138442.6" + wire $0\opc_l_s_opc$next[0:0]$7113 + attribute \src "libresoc.v:138293.3-138294.39" + wire $0\opc_l_s_opc[0:0] + attribute \src "libresoc.v:138697.3-138705.6" + wire width 4 $0\prev_wr_go$next[3:0]$7213 + attribute \src "libresoc.v:138303.3-138304.37" + wire width 4 $0\prev_wr_go[3:0] + attribute \src "libresoc.v:138388.3-138397.6" + wire $0\req_done[0:0] + attribute \src "libresoc.v:138479.3-138487.6" + wire width 4 $0\req_l_r_req$next[3:0]$7128 + attribute \src "libresoc.v:138283.3-138284.39" + wire width 4 $0\req_l_r_req[3:0] + attribute \src "libresoc.v:138470.3-138478.6" + wire width 4 $0\req_l_s_req$next[3:0]$7125 + attribute \src "libresoc.v:138285.3-138286.39" + wire width 4 $0\req_l_s_req[3:0] + attribute \src "libresoc.v:138407.3-138415.6" + wire $0\rok_l_r_rdok$next[0:0]$7104 + attribute \src "libresoc.v:138299.3-138300.41" + wire $0\rok_l_r_rdok[0:0] + attribute \src "libresoc.v:138398.3-138406.6" + wire $0\rok_l_s_rdok$next[0:0]$7101 + attribute \src "libresoc.v:138301.3-138302.41" + wire $0\rok_l_s_rdok[0:0] + attribute \src "libresoc.v:138425.3-138433.6" + wire $0\rst_l_r_rst$next[0:0]$7110 + attribute \src "libresoc.v:138295.3-138296.39" + wire $0\rst_l_r_rst[0:0] + attribute \src "libresoc.v:138416.3-138424.6" + wire $0\rst_l_s_rst$next[0:0]$7107 + attribute \src "libresoc.v:138297.3-138298.39" + wire $0\rst_l_s_rst[0:0] + attribute \src "libresoc.v:138461.3-138469.6" + wire width 3 $0\src_l_r_src$next[2:0]$7122 + attribute \src "libresoc.v:138287.3-138288.39" + wire width 3 $0\src_l_r_src[2:0] + attribute \src "libresoc.v:138452.3-138460.6" + wire width 3 $0\src_l_s_src$next[2:0]$7119 + attribute \src "libresoc.v:138289.3-138290.39" + wire width 3 $0\src_l_s_src[2:0] + attribute \src "libresoc.v:138609.3-138618.6" + wire width 64 $0\src_r0$next[63:0]$7194 + attribute \src "libresoc.v:138241.3-138242.29" + wire width 64 $0\src_r0[63:0] + attribute \src "libresoc.v:138619.3-138628.6" + wire width 64 $0\src_r1$next[63:0]$7197 + attribute \src "libresoc.v:138239.3-138240.29" + wire width 64 $0\src_r1[63:0] + attribute \src "libresoc.v:138629.3-138638.6" + wire $0\src_r2$next[0:0]$7200 + attribute \src "libresoc.v:138237.3-138238.29" + wire $0\src_r2[0:0] + attribute \src "libresoc.v:137706.7-137706.24" + wire $1\all_rd_dly[0:0] + attribute \src "libresoc.v:137716.7-137716.26" + wire $1\alu_done_dly[0:0] + attribute \src "libresoc.v:138648.3-138656.6" + wire $1\alu_l_r_alu$next[0:0]$7207 + attribute \src "libresoc.v:137724.7-137724.25" + wire $1\alu_l_r_alu[0:0] + attribute \src "libresoc.v:138488.3-138520.6" + wire width 12 $1\alu_mul0_mul_op__fn_unit$next[11:0]$7143 + attribute \src "libresoc.v:137745.14-137745.48" + wire width 12 $1\alu_mul0_mul_op__fn_unit[11:0] + attribute \src "libresoc.v:138488.3-138520.6" + wire width 64 $1\alu_mul0_mul_op__imm_data__data$next[63:0]$7144 + attribute \src "libresoc.v:137749.14-137749.68" + wire width 64 $1\alu_mul0_mul_op__imm_data__data[63:0] + attribute \src "libresoc.v:138488.3-138520.6" + wire $1\alu_mul0_mul_op__imm_data__ok$next[0:0]$7145 + attribute \src "libresoc.v:137753.7-137753.43" + wire $1\alu_mul0_mul_op__imm_data__ok[0:0] + attribute \src "libresoc.v:138488.3-138520.6" + wire width 32 $1\alu_mul0_mul_op__insn$next[31:0]$7146 + attribute \src "libresoc.v:137757.14-137757.43" + wire width 32 $1\alu_mul0_mul_op__insn[31:0] + attribute \src "libresoc.v:138488.3-138520.6" + wire width 7 $1\alu_mul0_mul_op__insn_type$next[6:0]$7147 + attribute \src "libresoc.v:137835.13-137835.47" + wire width 7 $1\alu_mul0_mul_op__insn_type[6:0] + attribute \src "libresoc.v:138488.3-138520.6" + wire $1\alu_mul0_mul_op__is_32bit$next[0:0]$7148 + attribute \src "libresoc.v:137839.7-137839.39" + wire $1\alu_mul0_mul_op__is_32bit[0:0] + attribute \src "libresoc.v:138488.3-138520.6" + wire $1\alu_mul0_mul_op__is_signed$next[0:0]$7149 + attribute \src "libresoc.v:137843.7-137843.40" + wire $1\alu_mul0_mul_op__is_signed[0:0] + attribute \src "libresoc.v:138488.3-138520.6" + wire $1\alu_mul0_mul_op__oe__oe$next[0:0]$7150 + attribute \src "libresoc.v:137847.7-137847.37" + wire $1\alu_mul0_mul_op__oe__oe[0:0] + attribute \src "libresoc.v:138488.3-138520.6" + wire $1\alu_mul0_mul_op__oe__ok$next[0:0]$7151 + attribute \src "libresoc.v:137851.7-137851.37" + wire $1\alu_mul0_mul_op__oe__ok[0:0] + attribute \src "libresoc.v:138488.3-138520.6" + wire $1\alu_mul0_mul_op__rc__ok$next[0:0]$7152 + attribute \src "libresoc.v:137855.7-137855.37" + wire $1\alu_mul0_mul_op__rc__ok[0:0] + attribute \src "libresoc.v:138488.3-138520.6" + wire $1\alu_mul0_mul_op__rc__rc$next[0:0]$7153 + attribute \src "libresoc.v:137859.7-137859.37" + wire $1\alu_mul0_mul_op__rc__rc[0:0] + attribute \src "libresoc.v:138488.3-138520.6" + wire $1\alu_mul0_mul_op__write_cr0$next[0:0]$7154 + attribute \src "libresoc.v:137863.7-137863.40" + wire $1\alu_mul0_mul_op__write_cr0[0:0] + attribute \src "libresoc.v:138639.3-138647.6" + wire $1\alui_l_r_alui$next[0:0]$7204 + attribute \src "libresoc.v:137893.7-137893.27" + wire $1\alui_l_r_alui[0:0] + attribute \src "libresoc.v:138521.3-138542.6" + wire width 64 $1\data_r0__o$next[63:0]$7164 + attribute \src "libresoc.v:137927.14-137927.47" + wire width 64 $1\data_r0__o[63:0] + attribute \src "libresoc.v:138521.3-138542.6" + wire $1\data_r0__o_ok$next[0:0]$7165 + attribute \src "libresoc.v:137931.7-137931.27" + wire $1\data_r0__o_ok[0:0] + attribute \src "libresoc.v:138543.3-138564.6" + wire width 4 $1\data_r1__cr_a$next[3:0]$7172 + attribute \src "libresoc.v:137935.13-137935.33" + wire width 4 $1\data_r1__cr_a[3:0] + attribute \src "libresoc.v:138543.3-138564.6" + wire $1\data_r1__cr_a_ok$next[0:0]$7173 + attribute \src "libresoc.v:137939.7-137939.30" + wire $1\data_r1__cr_a_ok[0:0] + attribute \src "libresoc.v:138565.3-138586.6" + wire width 2 $1\data_r2__xer_ov$next[1:0]$7180 + attribute \src "libresoc.v:137943.13-137943.35" + wire width 2 $1\data_r2__xer_ov[1:0] + attribute \src "libresoc.v:138565.3-138586.6" + wire $1\data_r2__xer_ov_ok$next[0:0]$7181 + attribute \src "libresoc.v:137947.7-137947.32" + wire $1\data_r2__xer_ov_ok[0:0] + attribute \src "libresoc.v:138587.3-138608.6" + wire $1\data_r3__xer_so$next[0:0]$7188 + attribute \src "libresoc.v:137951.7-137951.29" + wire $1\data_r3__xer_so[0:0] + attribute \src "libresoc.v:138587.3-138608.6" + wire $1\data_r3__xer_so_ok$next[0:0]$7189 + attribute \src "libresoc.v:137955.7-137955.32" + wire $1\data_r3__xer_so_ok[0:0] + attribute \src "libresoc.v:138657.3-138666.6" + wire width 64 $1\dest1_o[63:0] + attribute \src "libresoc.v:138667.3-138676.6" + wire width 4 $1\dest2_o[3:0] + attribute \src "libresoc.v:138677.3-138686.6" + wire width 2 $1\dest3_o[1:0] + attribute \src "libresoc.v:138687.3-138696.6" + wire $1\dest4_o[0:0] + attribute \src "libresoc.v:138443.3-138451.6" + wire $1\opc_l_r_opc$next[0:0]$7117 + attribute \src "libresoc.v:137975.7-137975.25" + wire $1\opc_l_r_opc[0:0] + attribute \src "libresoc.v:138434.3-138442.6" + wire $1\opc_l_s_opc$next[0:0]$7114 + attribute \src "libresoc.v:137979.7-137979.25" + wire $1\opc_l_s_opc[0:0] + attribute \src "libresoc.v:138697.3-138705.6" + wire width 4 $1\prev_wr_go$next[3:0]$7214 + attribute \src "libresoc.v:138094.13-138094.30" + wire width 4 $1\prev_wr_go[3:0] + attribute \src "libresoc.v:138388.3-138397.6" + wire $1\req_done[0:0] + attribute \src "libresoc.v:138479.3-138487.6" + wire width 4 $1\req_l_r_req$next[3:0]$7129 + attribute \src "libresoc.v:138102.13-138102.31" + wire width 4 $1\req_l_r_req[3:0] + attribute \src "libresoc.v:138470.3-138478.6" + wire width 4 $1\req_l_s_req$next[3:0]$7126 + attribute \src "libresoc.v:138106.13-138106.31" + wire width 4 $1\req_l_s_req[3:0] + attribute \src "libresoc.v:138407.3-138415.6" + wire $1\rok_l_r_rdok$next[0:0]$7105 + attribute \src "libresoc.v:138118.7-138118.26" + wire $1\rok_l_r_rdok[0:0] + attribute \src "libresoc.v:138398.3-138406.6" + wire $1\rok_l_s_rdok$next[0:0]$7102 + attribute \src "libresoc.v:138122.7-138122.26" + wire $1\rok_l_s_rdok[0:0] + attribute \src "libresoc.v:138425.3-138433.6" + wire $1\rst_l_r_rst$next[0:0]$7111 + attribute \src "libresoc.v:138126.7-138126.25" + wire $1\rst_l_r_rst[0:0] + attribute \src "libresoc.v:138416.3-138424.6" + wire $1\rst_l_s_rst$next[0:0]$7108 + attribute \src "libresoc.v:138130.7-138130.25" + wire $1\rst_l_s_rst[0:0] + attribute \src "libresoc.v:138461.3-138469.6" + wire width 3 $1\src_l_r_src$next[2:0]$7123 + attribute \src "libresoc.v:138144.13-138144.31" + wire width 3 $1\src_l_r_src[2:0] + attribute \src "libresoc.v:138452.3-138460.6" + wire width 3 $1\src_l_s_src$next[2:0]$7120 + attribute \src "libresoc.v:138148.13-138148.31" + wire width 3 $1\src_l_s_src[2:0] + attribute \src "libresoc.v:138609.3-138618.6" + wire width 64 $1\src_r0$next[63:0]$7195 + attribute \src "libresoc.v:138154.14-138154.43" + wire width 64 $1\src_r0[63:0] + attribute \src "libresoc.v:138619.3-138628.6" + wire width 64 $1\src_r1$next[63:0]$7198 + attribute \src "libresoc.v:138158.14-138158.43" + wire width 64 $1\src_r1[63:0] + attribute \src "libresoc.v:138629.3-138638.6" + wire $1\src_r2$next[0:0]$7201 + attribute \src "libresoc.v:138162.7-138162.20" + wire $1\src_r2[0:0] + attribute \src "libresoc.v:138488.3-138520.6" + wire width 64 $2\alu_mul0_mul_op__imm_data__data$next[63:0]$7155 + attribute \src "libresoc.v:138488.3-138520.6" + wire $2\alu_mul0_mul_op__imm_data__ok$next[0:0]$7156 + attribute \src "libresoc.v:138488.3-138520.6" + wire $2\alu_mul0_mul_op__oe__oe$next[0:0]$7157 + attribute \src "libresoc.v:138488.3-138520.6" + wire $2\alu_mul0_mul_op__oe__ok$next[0:0]$7158 + attribute \src "libresoc.v:138488.3-138520.6" + wire $2\alu_mul0_mul_op__rc__ok$next[0:0]$7159 + attribute \src "libresoc.v:138488.3-138520.6" + wire $2\alu_mul0_mul_op__rc__rc$next[0:0]$7160 + attribute \src "libresoc.v:138521.3-138542.6" + wire width 64 $2\data_r0__o$next[63:0]$7166 + attribute \src "libresoc.v:138521.3-138542.6" + wire $2\data_r0__o_ok$next[0:0]$7167 + attribute \src "libresoc.v:138543.3-138564.6" + wire width 4 $2\data_r1__cr_a$next[3:0]$7174 + attribute \src "libresoc.v:138543.3-138564.6" + wire $2\data_r1__cr_a_ok$next[0:0]$7175 + attribute \src "libresoc.v:138565.3-138586.6" + wire width 2 $2\data_r2__xer_ov$next[1:0]$7182 + attribute \src "libresoc.v:138565.3-138586.6" + wire $2\data_r2__xer_ov_ok$next[0:0]$7183 + attribute \src "libresoc.v:138587.3-138608.6" + wire $2\data_r3__xer_so$next[0:0]$7190 + attribute \src "libresoc.v:138587.3-138608.6" + wire $2\data_r3__xer_so_ok$next[0:0]$7191 + attribute \src "libresoc.v:138521.3-138542.6" + wire $3\data_r0__o_ok$next[0:0]$7168 + attribute \src "libresoc.v:138543.3-138564.6" + wire $3\data_r1__cr_a_ok$next[0:0]$7176 + attribute \src "libresoc.v:138565.3-138586.6" + wire $3\data_r2__xer_ov_ok$next[0:0]$7184 + attribute \src "libresoc.v:138587.3-138608.6" + wire $3\data_r3__xer_so_ok$next[0:0]$7192 + attribute \src "libresoc.v:138173.19-138173.113" + wire width 3 $and$libresoc.v:138173$7001_Y + attribute \src "libresoc.v:138174.19-138174.125" + wire $and$libresoc.v:138174$7002_Y + attribute \src "libresoc.v:138175.19-138175.125" + wire $and$libresoc.v:138175$7003_Y + attribute \src "libresoc.v:138176.19-138176.125" + wire $and$libresoc.v:138176$7004_Y + attribute \src "libresoc.v:138177.19-138177.125" + wire $and$libresoc.v:138177$7005_Y + attribute \src "libresoc.v:138178.18-138178.110" + wire $and$libresoc.v:138178$7006_Y + attribute \src "libresoc.v:138179.19-138179.149" + wire width 4 $and$libresoc.v:138179$7007_Y + attribute \src "libresoc.v:138180.19-138180.121" + wire width 4 $and$libresoc.v:138180$7008_Y + attribute \src "libresoc.v:138181.19-138181.127" + wire $and$libresoc.v:138181$7009_Y + attribute \src "libresoc.v:138182.19-138182.127" + wire $and$libresoc.v:138182$7010_Y + attribute \src "libresoc.v:138183.19-138183.127" + wire $and$libresoc.v:138183$7011_Y + attribute \src "libresoc.v:138184.19-138184.127" + wire $and$libresoc.v:138184$7012_Y + attribute \src "libresoc.v:138186.18-138186.98" + wire $and$libresoc.v:138186$7014_Y + attribute \src "libresoc.v:138188.18-138188.100" + wire $and$libresoc.v:138188$7016_Y + attribute \src "libresoc.v:138189.18-138189.160" + wire width 4 $and$libresoc.v:138189$7017_Y + attribute \src "libresoc.v:138191.18-138191.119" + wire width 4 $and$libresoc.v:138191$7019_Y + attribute \src "libresoc.v:138194.17-138194.123" + wire $and$libresoc.v:138194$7022_Y + attribute \src "libresoc.v:138195.18-138195.116" + wire $and$libresoc.v:138195$7023_Y + attribute \src "libresoc.v:138200.18-138200.113" + wire $and$libresoc.v:138200$7028_Y + attribute \src "libresoc.v:138201.18-138201.125" + wire width 4 $and$libresoc.v:138201$7029_Y + attribute \src "libresoc.v:138203.18-138203.112" + wire $and$libresoc.v:138203$7031_Y + attribute \src "libresoc.v:138205.18-138205.126" + wire $and$libresoc.v:138205$7033_Y + attribute \src "libresoc.v:138206.18-138206.126" + wire $and$libresoc.v:138206$7034_Y + attribute \src "libresoc.v:138207.18-138207.117" + wire $and$libresoc.v:138207$7035_Y + attribute \src "libresoc.v:138213.18-138213.130" + wire $and$libresoc.v:138213$7041_Y + attribute \src "libresoc.v:138214.18-138214.124" + wire width 4 $and$libresoc.v:138214$7042_Y + attribute \src "libresoc.v:138216.18-138216.116" + wire $and$libresoc.v:138216$7044_Y + attribute \src "libresoc.v:138217.18-138217.119" + wire $and$libresoc.v:138217$7045_Y + attribute \src "libresoc.v:138218.18-138218.121" + wire $and$libresoc.v:138218$7046_Y + attribute \src "libresoc.v:138219.18-138219.121" + wire $and$libresoc.v:138219$7047_Y + attribute \src "libresoc.v:138226.18-138226.134" + wire $and$libresoc.v:138226$7054_Y + attribute \src "libresoc.v:138228.18-138228.132" + wire $and$libresoc.v:138228$7056_Y + attribute \src "libresoc.v:138229.18-138229.149" + wire width 3 $and$libresoc.v:138229$7057_Y + attribute \src "libresoc.v:138231.18-138231.129" + wire width 3 $and$libresoc.v:138231$7059_Y + attribute \src "libresoc.v:138202.18-138202.113" + wire $eq$libresoc.v:138202$7030_Y + attribute \src "libresoc.v:138204.18-138204.119" + wire $eq$libresoc.v:138204$7032_Y + attribute \src "libresoc.v:138185.18-138185.97" + wire $not$libresoc.v:138185$7013_Y + attribute \src "libresoc.v:138187.18-138187.99" + wire $not$libresoc.v:138187$7015_Y + attribute \src "libresoc.v:138190.18-138190.113" + wire width 4 $not$libresoc.v:138190$7018_Y + attribute \src "libresoc.v:138193.18-138193.106" + wire $not$libresoc.v:138193$7021_Y + attribute \src "libresoc.v:138199.18-138199.120" + wire $not$libresoc.v:138199$7027_Y + attribute \src "libresoc.v:138210.17-138210.113" + wire width 3 $not$libresoc.v:138210$7038_Y + attribute \src "libresoc.v:138230.18-138230.131" + wire $not$libresoc.v:138230$7058_Y + attribute \src "libresoc.v:138232.18-138232.114" + wire width 3 $not$libresoc.v:138232$7060_Y + attribute \src "libresoc.v:138198.18-138198.112" + wire $or$libresoc.v:138198$7026_Y + attribute \src "libresoc.v:138208.18-138208.122" + wire $or$libresoc.v:138208$7036_Y + attribute \src "libresoc.v:138209.18-138209.124" + wire $or$libresoc.v:138209$7037_Y + attribute \src "libresoc.v:138211.18-138211.168" + wire width 4 $or$libresoc.v:138211$7039_Y + attribute \src "libresoc.v:138212.18-138212.155" + wire width 3 $or$libresoc.v:138212$7040_Y + attribute \src "libresoc.v:138215.18-138215.120" + wire width 4 $or$libresoc.v:138215$7043_Y + attribute \src "libresoc.v:138221.17-138221.117" + wire width 3 $or$libresoc.v:138221$7049_Y + attribute \src "libresoc.v:138227.17-138227.104" + wire $reduce_and$libresoc.v:138227$7055_Y + attribute \src "libresoc.v:138192.18-138192.106" + wire $reduce_or$libresoc.v:138192$7020_Y + attribute \src "libresoc.v:138196.18-138196.113" + wire $reduce_or$libresoc.v:138196$7024_Y + attribute \src "libresoc.v:138197.18-138197.112" + wire $reduce_or$libresoc.v:138197$7025_Y + attribute \src "libresoc.v:138220.18-138220.160" + wire $ternary$libresoc.v:138220$7048_Y + attribute \src "libresoc.v:138222.18-138222.172" + wire width 64 $ternary$libresoc.v:138222$7050_Y + attribute \src "libresoc.v:138223.18-138223.118" + wire width 64 $ternary$libresoc.v:138223$7051_Y + attribute \src "libresoc.v:138224.18-138224.115" + wire width 64 $ternary$libresoc.v:138224$7052_Y + attribute \src "libresoc.v:138225.18-138225.118" + wire $ternary$libresoc.v:138225$7053_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + wire \$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + wire width 3 \$100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + wire \$102 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + wire \$104 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + wire \$106 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + wire \$108 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" + wire width 4 \$110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" + wire width 4 \$112 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + wire \$114 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + wire \$116 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + wire \$118 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + wire \$120 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire \$14 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire \$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" + wire \$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" + wire width 4 \$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + wire \$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + wire width 4 \$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + wire width 4 \$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + wire \$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + wire \$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + wire \$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + wire \$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + wire \$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + wire \$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + wire width 4 \$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + wire \$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + wire \$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + wire \$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + wire width 3 \$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + wire \$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + wire \$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + wire \$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" + wire \$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" + wire \$58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" + wire width 4 \$60 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" + wire width 3 \$62 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" + wire \$64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" + wire width 4 \$66 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" + wire width 4 \$68 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + wire width 3 \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + wire \$70 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + wire \$72 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + wire \$74 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + wire \$76 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" + wire \$78 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" + wire width 64 \$80 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 64 \$82 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 64 \$84 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire \$86 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" + wire \$88 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" + wire \$90 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + wire width 3 \$92 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" + wire \$94 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + wire width 3 \$96 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + wire width 3 \$98 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:187" + wire \all_rd + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire \all_rd_dly + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire \all_rd_dly$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:192" + wire \all_rd_pulse + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + wire \all_rd_rise + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:196" + wire \alu_done + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire \alu_done_dly + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire \alu_done_dly$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + wire \alu_done_rise + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire \alu_l_q_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \alu_l_r_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \alu_l_r_alu$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \alu_l_s_alu + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \alu_mul0_cr_a + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \alu_mul0_mul_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \alu_mul0_mul_op__fn_unit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \alu_mul0_mul_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \alu_mul0_mul_op__imm_data__data$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_mul0_mul_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_mul0_mul_op__imm_data__ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \alu_mul0_mul_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \alu_mul0_mul_op__insn$next + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \alu_mul0_mul_op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \alu_mul0_mul_op__insn_type$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_mul0_mul_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_mul0_mul_op__is_32bit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_mul0_mul_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_mul0_mul_op__is_signed$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_mul0_mul_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_mul0_mul_op__oe__oe$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_mul0_mul_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_mul0_mul_op__oe__ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_mul0_mul_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_mul0_mul_op__rc__ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_mul0_mul_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_mul0_mul_op__rc__rc$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_mul0_mul_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_mul0_mul_op__write_cr0$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire \alu_mul0_n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire \alu_mul0_n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \alu_mul0_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire \alu_mul0_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire \alu_mul0_p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \alu_mul0_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \alu_mul0_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \alu_mul0_xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \alu_mul0_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \alu_mul0_xer_so$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:197" + wire \alu_pulse + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198" + wire width 4 \alu_pulsem + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire \alui_l_q_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \alui_l_r_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \alui_l_r_alui$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \alui_l_s_alui + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 32 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 31 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 25 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" + wire output 14 \cu_busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:108" + wire \cu_done_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:104" + wire \cu_go_die_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" + wire input 13 \cu_issue_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 input 17 \cu_rd__go_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 output 16 \cu_rd__rel_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" + wire width 3 input 15 \cu_rdmaskn_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:102" + wire \cu_shadown_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 4 input 23 \cu_wr__go_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 4 output 22 \cu_wr__rel_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:97" + wire width 4 \cu_wrmask_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 64 \data_r0__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 64 \data_r0__o$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r0__o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r0__o_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 4 \data_r1__cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 4 \data_r1__cr_a$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r1__cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r1__cr_a_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 2 \data_r2__xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 2 \data_r2__xer_ov$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r2__xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r2__xer_ov_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r3__xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r3__xer_so$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r3__xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r3__xer_so_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 24 \dest1_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 4 output 26 \dest2_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 2 output 28 \dest3_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire output 30 \dest4_o + attribute \src "libresoc.v:137582.7-137582.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 21 \o_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire \opc_l_q_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \opc_l_r_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \opc_l_r_opc$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \opc_l_s_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \opc_l_s_opc$next + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 2 \oper_i_alu_mul0__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 3 \oper_i_alu_mul0__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 4 \oper_i_alu_mul0__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 12 \oper_i_alu_mul0__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \oper_i_alu_mul0__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \oper_i_alu_mul0__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 11 \oper_i_alu_mul0__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 7 \oper_i_alu_mul0__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \oper_i_alu_mul0__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 6 \oper_i_alu_mul0__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 5 \oper_i_alu_mul0__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \oper_i_alu_mul0__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" + wire width 4 \prev_wr_go + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" + wire width 4 \prev_wr_go$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212" + wire \req_done + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 4 \req_l_q_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 4 \req_l_r_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 4 \req_l_r_req$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 4 \req_l_s_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 4 \req_l_s_req$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226" + wire \reset + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:229" + wire width 3 \reset_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:228" + wire width 4 \reset_w + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire \rok_l_q_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \rok_l_r_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \rok_l_r_rdok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \rok_l_s_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \rok_l_s_rdok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \rst_l_r_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \rst_l_r_rst$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \rst_l_s_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \rst_l_s_rst$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227" + wire \rst_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 18 \src1_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 19 \src2_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire input 20 \src3_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 3 \src_l_q_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 3 \src_l_r_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 3 \src_l_r_src$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 3 \src_l_s_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 3 \src_l_s_src$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:166" + wire width 64 \src_or_imm + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 64 \src_r0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 64 \src_r0$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 64 \src_r1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 64 \src_r1$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire \src_r2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire \src_r2$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:167" + wire \src_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" + wire \wr_any + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 27 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 29 \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + cell $and $and$libresoc.v:138173$7001 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \$96 + connect \B \$98 + connect \Y $and$libresoc.v:138173$7001_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + cell $and $and$libresoc.v:138174$7002 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_busy_o + connect \B \cu_shadown_i + connect \Y $and$libresoc.v:138174$7002_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + cell $and $and$libresoc.v:138175$7003 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_busy_o + connect \B \cu_shadown_i + connect \Y $and$libresoc.v:138175$7003_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + cell $and $and$libresoc.v:138176$7004 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_busy_o + connect \B \cu_shadown_i + connect \Y $and$libresoc.v:138176$7004_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + cell $and $and$libresoc.v:138177$7005 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_busy_o + connect \B \cu_shadown_i + connect \Y $and$libresoc.v:138177$7005_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $and $and$libresoc.v:138178$7006 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$2 + connect \B \$4 + connect \Y $and$libresoc.v:138178$7006_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" + cell $and $and$libresoc.v:138179$7007 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \req_l_q_req + connect \B { \$102 \$104 \$106 \$108 } + connect \Y $and$libresoc.v:138179$7007_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" + cell $and $and$libresoc.v:138180$7008 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \$110 + connect \B \cu_wrmask_o + connect \Y $and$libresoc.v:138180$7008_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + cell $and $and$libresoc.v:138181$7009 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_wr__go_i [0] + connect \B \cu_busy_o + connect \Y $and$libresoc.v:138181$7009_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + cell $and $and$libresoc.v:138182$7010 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_wr__go_i [1] + connect \B \cu_busy_o + connect \Y $and$libresoc.v:138182$7010_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + cell $and $and$libresoc.v:138183$7011 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_wr__go_i [2] + connect \B \cu_busy_o + connect \Y $and$libresoc.v:138183$7011_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + cell $and $and$libresoc.v:138184$7012 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_wr__go_i [3] + connect \B \cu_busy_o + connect \Y $and$libresoc.v:138184$7012_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $and$libresoc.v:138186$7014 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \all_rd + connect \B \$12 + connect \Y $and$libresoc.v:138186$7014_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $and$libresoc.v:138188$7016 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_done + connect \B \$16 + connect \Y $and$libresoc.v:138188$7016_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" + cell $and $and$libresoc.v:138189$7017 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \cu_wr__go_i + connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } + connect \Y $and$libresoc.v:138189$7017_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $and $and$libresoc.v:138191$7019 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \cu_wr__rel_o + connect \B \$24 + connect \Y $and$libresoc.v:138191$7019_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" + cell $and $and$libresoc.v:138194$7022 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_busy_o + connect \B \rok_l_q_rdok + connect \Y $and$libresoc.v:138194$7022_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $and $and$libresoc.v:138195$7023 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_busy_o + connect \B \$22 + connect \Y $and$libresoc.v:138195$7023_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + cell $and $and$libresoc.v:138200$7028 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_any + connect \B \$38 + connect \Y $and$libresoc.v:138200$7028_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + cell $and $and$libresoc.v:138201$7029 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \req_l_q_req + connect \B \cu_wrmask_o + connect \Y $and$libresoc.v:138201$7029_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + cell $and $and$libresoc.v:138203$7031 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$40 + connect \B \$44 + connect \Y $and$libresoc.v:138203$7031_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + cell $and $and$libresoc.v:138205$7033 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$48 + connect \B \alu_mul0_n_ready_i + connect \Y $and$libresoc.v:138205$7033_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + cell $and $and$libresoc.v:138206$7034 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$50 + connect \B \alu_mul0_n_valid_o + connect \Y $and$libresoc.v:138206$7034_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + cell $and $and$libresoc.v:138207$7035 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$52 + connect \B \cu_busy_o + connect \Y $and$libresoc.v:138207$7035_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" + cell $and $and$libresoc.v:138213$7041 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_mul0_n_valid_o + connect \B \cu_busy_o + connect \Y $and$libresoc.v:138213$7041_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" + cell $and $and$libresoc.v:138214$7042 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \alu_pulsem + connect \B \cu_wrmask_o + connect \Y $and$libresoc.v:138214$7042_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + cell $and $and$libresoc.v:138216$7044 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \o_ok + connect \B \cu_busy_o + connect \Y $and$libresoc.v:138216$7044_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + cell $and $and$libresoc.v:138217$7045 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cr_a_ok + connect \B \cu_busy_o + connect \Y $and$libresoc.v:138217$7045_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + cell $and $and$libresoc.v:138218$7046 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \xer_ov_ok + connect \B \cu_busy_o + connect \Y $and$libresoc.v:138218$7046_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + cell $and $and$libresoc.v:138219$7047 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \xer_so_ok + connect \B \cu_busy_o + connect \Y $and$libresoc.v:138219$7047_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" + cell $and $and$libresoc.v:138226$7054 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_mul0_p_ready_o + connect \B \alui_l_q_alui + connect \Y $and$libresoc.v:138226$7054_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" + cell $and $and$libresoc.v:138228$7056 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_mul0_n_valid_o + connect \B \alu_l_q_alu + connect \Y $and$libresoc.v:138228$7056_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + cell $and $and$libresoc.v:138229$7057 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \src_l_q_src + connect \B { \cu_busy_o \cu_busy_o \cu_busy_o } + connect \Y $and$libresoc.v:138229$7057_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + cell $and $and$libresoc.v:138231$7059 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \$92 + connect \B { 1'1 \$94 1'1 } + connect \Y $and$libresoc.v:138231$7059_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + cell $eq $eq$libresoc.v:138202$7030 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$42 + connect \B 1'0 + connect \Y $eq$libresoc.v:138202$7030_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + cell $eq $eq$libresoc.v:138204$7032 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_wrmask_o + connect \B 1'0 + connect \Y $eq$libresoc.v:138204$7032_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $not$libresoc.v:138185$7013 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \all_rd_dly + connect \Y $not$libresoc.v:138185$7013_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $not$libresoc.v:138187$7015 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_done_dly + connect \Y $not$libresoc.v:138187$7015_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $not $not$libresoc.v:138190$7018 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \cu_wrmask_o + connect \Y $not$libresoc.v:138190$7018_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $not $not$libresoc.v:138193$7021 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$23 + connect \Y $not$libresoc.v:138193$7021_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + cell $not $not$libresoc.v:138199$7027 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_mul0_n_ready_i + connect \Y $not$libresoc.v:138199$7027_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $not $not$libresoc.v:138210$7038 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \cu_rd__rel_o + connect \Y $not$libresoc.v:138210$7038_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" + cell $not $not$libresoc.v:138230$7058 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_mul0_mul_op__imm_data__ok + connect \Y $not$libresoc.v:138230$7058_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + cell $not $not$libresoc.v:138232$7060 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \cu_rdmaskn_i + connect \Y $not$libresoc.v:138232$7060_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $or $or$libresoc.v:138198$7026 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$32 + connect \B \$34 + connect \Y $or$libresoc.v:138198$7026_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" + cell $or $or$libresoc.v:138208$7036 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \req_done + connect \B \cu_go_die_i + connect \Y $or$libresoc.v:138208$7036_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" + cell $or $or$libresoc.v:138209$7037 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_issue_i + connect \B \cu_go_die_i + connect \Y $or$libresoc.v:138209$7037_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" + cell $or $or$libresoc.v:138211$7039 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \cu_wr__go_i + connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } + connect \Y $or$libresoc.v:138211$7039_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" + cell $or $or$libresoc.v:138212$7040 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \cu_rd__go_i + connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } + connect \Y $or$libresoc.v:138212$7040_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" + cell $or $or$libresoc.v:138215$7043 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \reset_w + connect \B \prev_wr_go + connect \Y $or$libresoc.v:138215$7043_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $or $or$libresoc.v:138221$7049 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \$5 + connect \B \cu_rd__go_i + connect \Y $or$libresoc.v:138221$7049_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $reduce_and $reduce_and$libresoc.v:138227$7055 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \$7 + connect \Y $reduce_and$libresoc.v:138227$7055_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $reduce_or $reduce_or$libresoc.v:138192$7020 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \$26 + connect \Y $reduce_or$libresoc.v:138192$7020_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $reduce_or $reduce_or$libresoc.v:138196$7024 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \cu_wr__go_i + connect \Y $reduce_or$libresoc.v:138196$7024_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $reduce_or $reduce_or$libresoc.v:138197$7025 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \prev_wr_go + connect \Y $reduce_or$libresoc.v:138197$7025_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" + cell $mux $ternary$libresoc.v:138220$7048 + parameter \WIDTH 1 + connect \A \src_l_q_src [1] + connect \B \opc_l_q_opc + connect \S \alu_mul0_mul_op__imm_data__ok + connect \Y $ternary$libresoc.v:138220$7048_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" + cell $mux $ternary$libresoc.v:138222$7050 + parameter \WIDTH 64 + connect \A \src2_i + connect \B \alu_mul0_mul_op__imm_data__data + connect \S \alu_mul0_mul_op__imm_data__ok + connect \Y $ternary$libresoc.v:138222$7050_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $ternary$libresoc.v:138223$7051 + parameter \WIDTH 64 + connect \A \src_r0 + connect \B \src1_i + connect \S \src_l_q_src [0] + connect \Y $ternary$libresoc.v:138223$7051_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $ternary$libresoc.v:138224$7052 + parameter \WIDTH 64 + connect \A \src_r1 + connect \B \src_or_imm + connect \S \src_sel + connect \Y $ternary$libresoc.v:138224$7052_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $ternary$libresoc.v:138225$7053 + parameter \WIDTH 1 + connect \A \src_r2 + connect \B \src3_i + connect \S \src_l_q_src [2] + connect \Y $ternary$libresoc.v:138225$7053_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:138309.15-138315.4" + cell \alu_l$104 \alu_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_alu \alu_l_q_alu + connect \r_alu \alu_l_r_alu + connect \s_alu \alu_l_s_alu + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:138316.12-138346.4" + cell \alu_mul0 \alu_mul0 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cr_a \alu_mul0_cr_a + connect \cr_a_ok \cr_a_ok + connect \mul_op__fn_unit \alu_mul0_mul_op__fn_unit + connect \mul_op__imm_data__data \alu_mul0_mul_op__imm_data__data + connect \mul_op__imm_data__ok \alu_mul0_mul_op__imm_data__ok + connect \mul_op__insn \alu_mul0_mul_op__insn + connect \mul_op__insn_type \alu_mul0_mul_op__insn_type + connect \mul_op__is_32bit \alu_mul0_mul_op__is_32bit + connect \mul_op__is_signed \alu_mul0_mul_op__is_signed + connect \mul_op__oe__oe \alu_mul0_mul_op__oe__oe + connect \mul_op__oe__ok \alu_mul0_mul_op__oe__ok + connect \mul_op__rc__ok \alu_mul0_mul_op__rc__ok + connect \mul_op__rc__rc \alu_mul0_mul_op__rc__rc + connect \mul_op__write_cr0 \alu_mul0_mul_op__write_cr0 + connect \n_ready_i \alu_mul0_n_ready_i + connect \n_valid_o \alu_mul0_n_valid_o + connect \o \alu_mul0_o + connect \o_ok \o_ok + connect \p_ready_o \alu_mul0_p_ready_o + connect \p_valid_i \alu_mul0_p_valid_i + connect \ra \alu_mul0_ra + connect \rb \alu_mul0_rb + connect \xer_ov \alu_mul0_xer_ov + connect \xer_ov_ok \xer_ov_ok + connect \xer_so \alu_mul0_xer_so + connect \xer_so$1 \alu_mul0_xer_so$1 + connect \xer_so_ok \xer_so_ok + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:138347.16-138353.4" + cell \alui_l$103 \alui_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_alui \alui_l_q_alui + connect \r_alui \alui_l_r_alui + connect \s_alui \alui_l_s_alui + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:138354.14-138360.4" + cell \opc_l$99 \opc_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_opc \opc_l_q_opc + connect \r_opc \opc_l_r_opc + connect \s_opc \opc_l_s_opc + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:138361.15-138367.4" + cell \req_l$100 \req_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_req \req_l_q_req + connect \r_req \req_l_r_req + connect \s_req \req_l_s_req + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:138368.15-138374.4" + cell \rok_l$102 \rok_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_rdok \rok_l_q_rdok + connect \r_rdok \rok_l_r_rdok + connect \s_rdok \rok_l_s_rdok + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:138375.15-138380.4" + cell \rst_l$101 \rst_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \r_rst \rst_l_r_rst + connect \s_rst \rst_l_s_rst + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:138381.14-138387.4" + cell \src_l$98 \src_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_src \src_l_q_src + connect \r_src \src_l_r_src + connect \s_src \src_l_s_src + end + attribute \src "libresoc.v:137582.7-137582.20" + process $proc$libresoc.v:137582$7215 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:137706.7-137706.24" + process $proc$libresoc.v:137706$7216 + assign { } { } + assign $1\all_rd_dly[0:0] 1'0 + sync always + sync init + update \all_rd_dly $1\all_rd_dly[0:0] + end + attribute \src "libresoc.v:137716.7-137716.26" + process $proc$libresoc.v:137716$7217 + assign { } { } + assign $1\alu_done_dly[0:0] 1'0 + sync always + sync init + update \alu_done_dly $1\alu_done_dly[0:0] + end + attribute \src "libresoc.v:137724.7-137724.25" + process $proc$libresoc.v:137724$7218 + assign { } { } + assign $1\alu_l_r_alu[0:0] 1'1 + sync always + sync init + update \alu_l_r_alu $1\alu_l_r_alu[0:0] + end + attribute \src "libresoc.v:137745.14-137745.48" + process $proc$libresoc.v:137745$7219 + assign { } { } + assign $1\alu_mul0_mul_op__fn_unit[11:0] 12'000000000000 + sync always + sync init + update \alu_mul0_mul_op__fn_unit $1\alu_mul0_mul_op__fn_unit[11:0] + end + attribute \src "libresoc.v:137749.14-137749.68" + process $proc$libresoc.v:137749$7220 + assign { } { } + assign $1\alu_mul0_mul_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \alu_mul0_mul_op__imm_data__data $1\alu_mul0_mul_op__imm_data__data[63:0] + end + attribute \src "libresoc.v:137753.7-137753.43" + process $proc$libresoc.v:137753$7221 + assign { } { } + assign $1\alu_mul0_mul_op__imm_data__ok[0:0] 1'0 + sync always + sync init + update \alu_mul0_mul_op__imm_data__ok $1\alu_mul0_mul_op__imm_data__ok[0:0] + end + attribute \src "libresoc.v:137757.14-137757.43" + process $proc$libresoc.v:137757$7222 + assign { } { } + assign $1\alu_mul0_mul_op__insn[31:0] 0 + sync always + sync init + update \alu_mul0_mul_op__insn $1\alu_mul0_mul_op__insn[31:0] + end + attribute \src "libresoc.v:137835.13-137835.47" + process $proc$libresoc.v:137835$7223 + assign { } { } + assign $1\alu_mul0_mul_op__insn_type[6:0] 7'0000000 + sync always + sync init + update \alu_mul0_mul_op__insn_type $1\alu_mul0_mul_op__insn_type[6:0] + end + attribute \src "libresoc.v:137839.7-137839.39" + process $proc$libresoc.v:137839$7224 + assign { } { } + assign $1\alu_mul0_mul_op__is_32bit[0:0] 1'0 + sync always + sync init + update \alu_mul0_mul_op__is_32bit $1\alu_mul0_mul_op__is_32bit[0:0] + end + attribute \src "libresoc.v:137843.7-137843.40" + process $proc$libresoc.v:137843$7225 + assign { } { } + assign $1\alu_mul0_mul_op__is_signed[0:0] 1'0 + sync always + sync init + update \alu_mul0_mul_op__is_signed $1\alu_mul0_mul_op__is_signed[0:0] + end + attribute \src "libresoc.v:137847.7-137847.37" + process $proc$libresoc.v:137847$7226 + assign { } { } + assign $1\alu_mul0_mul_op__oe__oe[0:0] 1'0 + sync always + sync init + update \alu_mul0_mul_op__oe__oe $1\alu_mul0_mul_op__oe__oe[0:0] + end + attribute \src "libresoc.v:137851.7-137851.37" + process $proc$libresoc.v:137851$7227 + assign { } { } + assign $1\alu_mul0_mul_op__oe__ok[0:0] 1'0 + sync always + sync init + update \alu_mul0_mul_op__oe__ok $1\alu_mul0_mul_op__oe__ok[0:0] + end + attribute \src "libresoc.v:137855.7-137855.37" + process $proc$libresoc.v:137855$7228 + assign { } { } + assign $1\alu_mul0_mul_op__rc__ok[0:0] 1'0 + sync always + sync init + update \alu_mul0_mul_op__rc__ok $1\alu_mul0_mul_op__rc__ok[0:0] + end + attribute \src "libresoc.v:137859.7-137859.37" + process $proc$libresoc.v:137859$7229 + assign { } { } + assign $1\alu_mul0_mul_op__rc__rc[0:0] 1'0 + sync always + sync init + update \alu_mul0_mul_op__rc__rc $1\alu_mul0_mul_op__rc__rc[0:0] + end + attribute \src "libresoc.v:137863.7-137863.40" + process $proc$libresoc.v:137863$7230 + assign { } { } + assign $1\alu_mul0_mul_op__write_cr0[0:0] 1'0 + sync always + sync init + update \alu_mul0_mul_op__write_cr0 $1\alu_mul0_mul_op__write_cr0[0:0] + end + attribute \src "libresoc.v:137893.7-137893.27" + process $proc$libresoc.v:137893$7231 + assign { } { } + assign $1\alui_l_r_alui[0:0] 1'1 + sync always + sync init + update \alui_l_r_alui $1\alui_l_r_alui[0:0] + end + attribute \src "libresoc.v:137927.14-137927.47" + process $proc$libresoc.v:137927$7232 + assign { } { } + assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \data_r0__o $1\data_r0__o[63:0] + end + attribute \src "libresoc.v:137931.7-137931.27" + process $proc$libresoc.v:137931$7233 + assign { } { } + assign $1\data_r0__o_ok[0:0] 1'0 + sync always + sync init + update \data_r0__o_ok $1\data_r0__o_ok[0:0] + end + attribute \src "libresoc.v:137935.13-137935.33" + process $proc$libresoc.v:137935$7234 + assign { } { } + assign $1\data_r1__cr_a[3:0] 4'0000 + sync always + sync init + update \data_r1__cr_a $1\data_r1__cr_a[3:0] + end + attribute \src "libresoc.v:137939.7-137939.30" + process $proc$libresoc.v:137939$7235 + assign { } { } + assign $1\data_r1__cr_a_ok[0:0] 1'0 + sync always + sync init + update \data_r1__cr_a_ok $1\data_r1__cr_a_ok[0:0] + end + attribute \src "libresoc.v:137943.13-137943.35" + process $proc$libresoc.v:137943$7236 + assign { } { } + assign $1\data_r2__xer_ov[1:0] 2'00 + sync always + sync init + update \data_r2__xer_ov $1\data_r2__xer_ov[1:0] + end + attribute \src "libresoc.v:137947.7-137947.32" + process $proc$libresoc.v:137947$7237 + assign { } { } + assign $1\data_r2__xer_ov_ok[0:0] 1'0 + sync always + sync init + update \data_r2__xer_ov_ok $1\data_r2__xer_ov_ok[0:0] + end + attribute \src "libresoc.v:137951.7-137951.29" + process $proc$libresoc.v:137951$7238 + assign { } { } + assign $1\data_r3__xer_so[0:0] 1'0 + sync always + sync init + update \data_r3__xer_so $1\data_r3__xer_so[0:0] + end + attribute \src "libresoc.v:137955.7-137955.32" + process $proc$libresoc.v:137955$7239 + assign { } { } + assign $1\data_r3__xer_so_ok[0:0] 1'0 + sync always + sync init + update \data_r3__xer_so_ok $1\data_r3__xer_so_ok[0:0] + end + attribute \src "libresoc.v:137975.7-137975.25" + process $proc$libresoc.v:137975$7240 + assign { } { } + assign $1\opc_l_r_opc[0:0] 1'1 + sync always + sync init + update \opc_l_r_opc $1\opc_l_r_opc[0:0] + end + attribute \src "libresoc.v:137979.7-137979.25" + process $proc$libresoc.v:137979$7241 + assign { } { } + assign $1\opc_l_s_opc[0:0] 1'0 + sync always + sync init + update \opc_l_s_opc $1\opc_l_s_opc[0:0] + end + attribute \src "libresoc.v:138094.13-138094.30" + process $proc$libresoc.v:138094$7242 + assign { } { } + assign $1\prev_wr_go[3:0] 4'0000 + sync always + sync init + update \prev_wr_go $1\prev_wr_go[3:0] + end + attribute \src "libresoc.v:138102.13-138102.31" + process $proc$libresoc.v:138102$7243 + assign { } { } + assign $1\req_l_r_req[3:0] 4'1111 + sync always + sync init + update \req_l_r_req $1\req_l_r_req[3:0] + end + attribute \src "libresoc.v:138106.13-138106.31" + process $proc$libresoc.v:138106$7244 + assign { } { } + assign $1\req_l_s_req[3:0] 4'0000 + sync always + sync init + update \req_l_s_req $1\req_l_s_req[3:0] + end + attribute \src "libresoc.v:138118.7-138118.26" + process $proc$libresoc.v:138118$7245 + assign { } { } + assign $1\rok_l_r_rdok[0:0] 1'1 + sync always + sync init + update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] + end + attribute \src "libresoc.v:138122.7-138122.26" + process $proc$libresoc.v:138122$7246 + assign { } { } + assign $1\rok_l_s_rdok[0:0] 1'0 + sync always + sync init + update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] + end + attribute \src "libresoc.v:138126.7-138126.25" + process $proc$libresoc.v:138126$7247 + assign { } { } + assign $1\rst_l_r_rst[0:0] 1'1 + sync always + sync init + update \rst_l_r_rst $1\rst_l_r_rst[0:0] + end + attribute \src "libresoc.v:138130.7-138130.25" + process $proc$libresoc.v:138130$7248 + assign { } { } + assign $1\rst_l_s_rst[0:0] 1'0 + sync always + sync init + update \rst_l_s_rst $1\rst_l_s_rst[0:0] + end + attribute \src "libresoc.v:138144.13-138144.31" + process $proc$libresoc.v:138144$7249 + assign { } { } + assign $1\src_l_r_src[2:0] 3'111 + sync always + sync init + update \src_l_r_src $1\src_l_r_src[2:0] + end + attribute \src "libresoc.v:138148.13-138148.31" + process $proc$libresoc.v:138148$7250 + assign { } { } + assign $1\src_l_s_src[2:0] 3'000 + sync always + sync init + update \src_l_s_src $1\src_l_s_src[2:0] + end + attribute \src "libresoc.v:138154.14-138154.43" + process $proc$libresoc.v:138154$7251 + assign { } { } + assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \src_r0 $1\src_r0[63:0] + end + attribute \src "libresoc.v:138158.14-138158.43" + process $proc$libresoc.v:138158$7252 + assign { } { } + assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \src_r1 $1\src_r1[63:0] + end + attribute \src "libresoc.v:138162.7-138162.20" + process $proc$libresoc.v:138162$7253 + assign { } { } + assign $1\src_r2[0:0] 1'0 + sync always + sync init + update \src_r2 $1\src_r2[0:0] + end + attribute \src "libresoc.v:138233.3-138234.39" + process $proc$libresoc.v:138233$7061 + assign { } { } + assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next + sync posedge \coresync_clk + update \alu_l_r_alu $0\alu_l_r_alu[0:0] + end + attribute \src "libresoc.v:138235.3-138236.43" + process $proc$libresoc.v:138235$7062 + assign { } { } + assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next + sync posedge \coresync_clk + update \alui_l_r_alui $0\alui_l_r_alui[0:0] + end + attribute \src "libresoc.v:138237.3-138238.29" + process $proc$libresoc.v:138237$7063 + assign { } { } + assign $0\src_r2[0:0] \src_r2$next + sync posedge \coresync_clk + update \src_r2 $0\src_r2[0:0] + end + attribute \src "libresoc.v:138239.3-138240.29" + process $proc$libresoc.v:138239$7064 + assign { } { } + assign $0\src_r1[63:0] \src_r1$next + sync posedge \coresync_clk + update \src_r1 $0\src_r1[63:0] + end + attribute \src "libresoc.v:138241.3-138242.29" + process $proc$libresoc.v:138241$7065 + assign { } { } + assign $0\src_r0[63:0] \src_r0$next + sync posedge \coresync_clk + update \src_r0 $0\src_r0[63:0] + end + attribute \src "libresoc.v:138243.3-138244.47" + process $proc$libresoc.v:138243$7066 + assign { } { } + assign $0\data_r3__xer_so[0:0] \data_r3__xer_so$next + sync posedge \coresync_clk + update \data_r3__xer_so $0\data_r3__xer_so[0:0] + end + attribute \src "libresoc.v:138245.3-138246.53" + process $proc$libresoc.v:138245$7067 + assign { } { } + assign $0\data_r3__xer_so_ok[0:0] \data_r3__xer_so_ok$next + sync posedge \coresync_clk + update \data_r3__xer_so_ok $0\data_r3__xer_so_ok[0:0] + end + attribute \src "libresoc.v:138247.3-138248.47" + process $proc$libresoc.v:138247$7068 + assign { } { } + assign $0\data_r2__xer_ov[1:0] \data_r2__xer_ov$next + sync posedge \coresync_clk + update \data_r2__xer_ov $0\data_r2__xer_ov[1:0] + end + attribute \src "libresoc.v:138249.3-138250.53" + process $proc$libresoc.v:138249$7069 + assign { } { } + assign $0\data_r2__xer_ov_ok[0:0] \data_r2__xer_ov_ok$next + sync posedge \coresync_clk + update \data_r2__xer_ov_ok $0\data_r2__xer_ov_ok[0:0] + end + attribute \src "libresoc.v:138251.3-138252.43" + process $proc$libresoc.v:138251$7070 + assign { } { } + assign $0\data_r1__cr_a[3:0] \data_r1__cr_a$next + sync posedge \coresync_clk + update \data_r1__cr_a $0\data_r1__cr_a[3:0] + end + attribute \src "libresoc.v:138253.3-138254.49" + process $proc$libresoc.v:138253$7071 + assign { } { } + assign $0\data_r1__cr_a_ok[0:0] \data_r1__cr_a_ok$next + sync posedge \coresync_clk + update \data_r1__cr_a_ok $0\data_r1__cr_a_ok[0:0] + end + attribute \src "libresoc.v:138255.3-138256.37" + process $proc$libresoc.v:138255$7072 + assign { } { } + assign $0\data_r0__o[63:0] \data_r0__o$next + sync posedge \coresync_clk + update \data_r0__o $0\data_r0__o[63:0] + end + attribute \src "libresoc.v:138257.3-138258.43" + process $proc$libresoc.v:138257$7073 + assign { } { } + assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next + sync posedge \coresync_clk + update \data_r0__o_ok $0\data_r0__o_ok[0:0] + end + attribute \src "libresoc.v:138259.3-138260.69" + process $proc$libresoc.v:138259$7074 + assign { } { } + assign $0\alu_mul0_mul_op__insn_type[6:0] \alu_mul0_mul_op__insn_type$next + sync posedge \coresync_clk + update \alu_mul0_mul_op__insn_type $0\alu_mul0_mul_op__insn_type[6:0] + end + attribute \src "libresoc.v:138261.3-138262.65" + process $proc$libresoc.v:138261$7075 + assign { } { } + assign $0\alu_mul0_mul_op__fn_unit[11:0] \alu_mul0_mul_op__fn_unit$next + sync posedge \coresync_clk + update \alu_mul0_mul_op__fn_unit $0\alu_mul0_mul_op__fn_unit[11:0] + end + attribute \src "libresoc.v:138263.3-138264.79" + process $proc$libresoc.v:138263$7076 + assign { } { } + assign $0\alu_mul0_mul_op__imm_data__data[63:0] \alu_mul0_mul_op__imm_data__data$next + sync posedge \coresync_clk + update \alu_mul0_mul_op__imm_data__data $0\alu_mul0_mul_op__imm_data__data[63:0] + end + attribute \src "libresoc.v:138265.3-138266.75" + process $proc$libresoc.v:138265$7077 + assign { } { } + assign $0\alu_mul0_mul_op__imm_data__ok[0:0] \alu_mul0_mul_op__imm_data__ok$next + sync posedge \coresync_clk + update \alu_mul0_mul_op__imm_data__ok $0\alu_mul0_mul_op__imm_data__ok[0:0] + end + attribute \src "libresoc.v:138267.3-138268.63" + process $proc$libresoc.v:138267$7078 + assign { } { } + assign $0\alu_mul0_mul_op__rc__rc[0:0] \alu_mul0_mul_op__rc__rc$next + sync posedge \coresync_clk + update \alu_mul0_mul_op__rc__rc $0\alu_mul0_mul_op__rc__rc[0:0] + end + attribute \src "libresoc.v:138269.3-138270.63" + process $proc$libresoc.v:138269$7079 + assign { } { } + assign $0\alu_mul0_mul_op__rc__ok[0:0] \alu_mul0_mul_op__rc__ok$next + sync posedge \coresync_clk + update \alu_mul0_mul_op__rc__ok $0\alu_mul0_mul_op__rc__ok[0:0] + end + attribute \src "libresoc.v:138271.3-138272.63" + process $proc$libresoc.v:138271$7080 + assign { } { } + assign $0\alu_mul0_mul_op__oe__oe[0:0] \alu_mul0_mul_op__oe__oe$next + sync posedge \coresync_clk + update \alu_mul0_mul_op__oe__oe $0\alu_mul0_mul_op__oe__oe[0:0] + end + attribute \src "libresoc.v:138273.3-138274.63" + process $proc$libresoc.v:138273$7081 + assign { } { } + assign $0\alu_mul0_mul_op__oe__ok[0:0] \alu_mul0_mul_op__oe__ok$next + sync posedge \coresync_clk + update \alu_mul0_mul_op__oe__ok $0\alu_mul0_mul_op__oe__ok[0:0] + end + attribute \src "libresoc.v:138275.3-138276.69" + process $proc$libresoc.v:138275$7082 + assign { } { } + assign $0\alu_mul0_mul_op__write_cr0[0:0] \alu_mul0_mul_op__write_cr0$next + sync posedge \coresync_clk + update \alu_mul0_mul_op__write_cr0 $0\alu_mul0_mul_op__write_cr0[0:0] + end + attribute \src "libresoc.v:138277.3-138278.67" + process $proc$libresoc.v:138277$7083 + assign { } { } + assign $0\alu_mul0_mul_op__is_32bit[0:0] \alu_mul0_mul_op__is_32bit$next + sync posedge \coresync_clk + update \alu_mul0_mul_op__is_32bit $0\alu_mul0_mul_op__is_32bit[0:0] + end + attribute \src "libresoc.v:138279.3-138280.69" + process $proc$libresoc.v:138279$7084 + assign { } { } + assign $0\alu_mul0_mul_op__is_signed[0:0] \alu_mul0_mul_op__is_signed$next + sync posedge \coresync_clk + update \alu_mul0_mul_op__is_signed $0\alu_mul0_mul_op__is_signed[0:0] + end + attribute \src "libresoc.v:138281.3-138282.59" + process $proc$libresoc.v:138281$7085 + assign { } { } + assign $0\alu_mul0_mul_op__insn[31:0] \alu_mul0_mul_op__insn$next + sync posedge \coresync_clk + update \alu_mul0_mul_op__insn $0\alu_mul0_mul_op__insn[31:0] + end + attribute \src "libresoc.v:138283.3-138284.39" + process $proc$libresoc.v:138283$7086 + assign { } { } + assign $0\req_l_r_req[3:0] \req_l_r_req$next + sync posedge \coresync_clk + update \req_l_r_req $0\req_l_r_req[3:0] + end + attribute \src "libresoc.v:138285.3-138286.39" + process $proc$libresoc.v:138285$7087 + assign { } { } + assign $0\req_l_s_req[3:0] \req_l_s_req$next + sync posedge \coresync_clk + update \req_l_s_req $0\req_l_s_req[3:0] + end + attribute \src "libresoc.v:138287.3-138288.39" + process $proc$libresoc.v:138287$7088 + assign { } { } + assign $0\src_l_r_src[2:0] \src_l_r_src$next + sync posedge \coresync_clk + update \src_l_r_src $0\src_l_r_src[2:0] + end + attribute \src "libresoc.v:138289.3-138290.39" + process $proc$libresoc.v:138289$7089 + assign { } { } + assign $0\src_l_s_src[2:0] \src_l_s_src$next + sync posedge \coresync_clk + update \src_l_s_src $0\src_l_s_src[2:0] + end + attribute \src "libresoc.v:138291.3-138292.39" + process $proc$libresoc.v:138291$7090 + assign { } { } + assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next + sync posedge \coresync_clk + update \opc_l_r_opc $0\opc_l_r_opc[0:0] + end + attribute \src "libresoc.v:138293.3-138294.39" + process $proc$libresoc.v:138293$7091 + assign { } { } + assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next + sync posedge \coresync_clk + update \opc_l_s_opc $0\opc_l_s_opc[0:0] + end + attribute \src "libresoc.v:138295.3-138296.39" + process $proc$libresoc.v:138295$7092 + assign { } { } + assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next + sync posedge \coresync_clk + update \rst_l_r_rst $0\rst_l_r_rst[0:0] + end + attribute \src "libresoc.v:138297.3-138298.39" + process $proc$libresoc.v:138297$7093 + assign { } { } + assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next + sync posedge \coresync_clk + update \rst_l_s_rst $0\rst_l_s_rst[0:0] + end + attribute \src "libresoc.v:138299.3-138300.41" + process $proc$libresoc.v:138299$7094 + assign { } { } + assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next + sync posedge \coresync_clk + update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] + end + attribute \src "libresoc.v:138301.3-138302.41" + process $proc$libresoc.v:138301$7095 + assign { } { } + assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next + sync posedge \coresync_clk + update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] + end + attribute \src "libresoc.v:138303.3-138304.37" + process $proc$libresoc.v:138303$7096 + assign { } { } + assign $0\prev_wr_go[3:0] \prev_wr_go$next + sync posedge \coresync_clk + update \prev_wr_go $0\prev_wr_go[3:0] + end + attribute \src "libresoc.v:138305.3-138306.40" + process $proc$libresoc.v:138305$7097 + assign { } { } + assign $0\alu_done_dly[0:0] \alu_mul0_n_valid_o + sync posedge \coresync_clk + update \alu_done_dly $0\alu_done_dly[0:0] + end + attribute \src "libresoc.v:138307.3-138308.25" + process $proc$libresoc.v:138307$7098 + assign { } { } + assign $0\all_rd_dly[0:0] \$10 + sync posedge \coresync_clk + update \all_rd_dly $0\all_rd_dly[0:0] + end + attribute \src "libresoc.v:138388.3-138397.6" + process $proc$libresoc.v:138388$7099 + assign { } { } + assign { } { } + assign $0\req_done[0:0] $1\req_done[0:0] + attribute \src "libresoc.v:138389.5-138389.29" + switch \initial + attribute \src "libresoc.v:138389.9-138389.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + switch \$54 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\req_done[0:0] 1'1 + case + assign $1\req_done[0:0] \$46 + end + sync always + update \req_done $0\req_done[0:0] + end + attribute \src "libresoc.v:138398.3-138406.6" + process $proc$libresoc.v:138398$7100 + assign { } { } + assign { } { } + assign $0\rok_l_s_rdok$next[0:0]$7101 $1\rok_l_s_rdok$next[0:0]$7102 + attribute \src "libresoc.v:138399.5-138399.29" + switch \initial + attribute \src "libresoc.v:138399.9-138399.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rok_l_s_rdok$next[0:0]$7102 1'0 + case + assign $1\rok_l_s_rdok$next[0:0]$7102 \cu_issue_i + end + sync always + update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$7101 + end + attribute \src "libresoc.v:138407.3-138415.6" + process $proc$libresoc.v:138407$7103 + assign { } { } + assign { } { } + assign $0\rok_l_r_rdok$next[0:0]$7104 $1\rok_l_r_rdok$next[0:0]$7105 + attribute \src "libresoc.v:138408.5-138408.29" + switch \initial + attribute \src "libresoc.v:138408.9-138408.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rok_l_r_rdok$next[0:0]$7105 1'1 + case + assign $1\rok_l_r_rdok$next[0:0]$7105 \$64 + end + sync always + update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$7104 + end + attribute \src "libresoc.v:138416.3-138424.6" + process $proc$libresoc.v:138416$7106 + assign { } { } + assign { } { } + assign $0\rst_l_s_rst$next[0:0]$7107 $1\rst_l_s_rst$next[0:0]$7108 + attribute \src "libresoc.v:138417.5-138417.29" + switch \initial + attribute \src "libresoc.v:138417.9-138417.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rst_l_s_rst$next[0:0]$7108 1'0 + case + assign $1\rst_l_s_rst$next[0:0]$7108 \all_rd + end + sync always + update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$7107 + end + attribute \src "libresoc.v:138425.3-138433.6" + process $proc$libresoc.v:138425$7109 + assign { } { } + assign { } { } + assign $0\rst_l_r_rst$next[0:0]$7110 $1\rst_l_r_rst$next[0:0]$7111 + attribute \src "libresoc.v:138426.5-138426.29" + switch \initial + attribute \src "libresoc.v:138426.9-138426.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rst_l_r_rst$next[0:0]$7111 1'1 + case + assign $1\rst_l_r_rst$next[0:0]$7111 \rst_r + end + sync always + update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$7110 + end + attribute \src "libresoc.v:138434.3-138442.6" + process $proc$libresoc.v:138434$7112 + assign { } { } + assign { } { } + assign $0\opc_l_s_opc$next[0:0]$7113 $1\opc_l_s_opc$next[0:0]$7114 + attribute \src "libresoc.v:138435.5-138435.29" + switch \initial + attribute \src "libresoc.v:138435.9-138435.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\opc_l_s_opc$next[0:0]$7114 1'0 + case + assign $1\opc_l_s_opc$next[0:0]$7114 \cu_issue_i + end + sync always + update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$7113 + end + attribute \src "libresoc.v:138443.3-138451.6" + process $proc$libresoc.v:138443$7115 + assign { } { } + assign { } { } + assign $0\opc_l_r_opc$next[0:0]$7116 $1\opc_l_r_opc$next[0:0]$7117 + attribute \src "libresoc.v:138444.5-138444.29" + switch \initial + attribute \src "libresoc.v:138444.9-138444.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\opc_l_r_opc$next[0:0]$7117 1'1 + case + assign $1\opc_l_r_opc$next[0:0]$7117 \req_done + end + sync always + update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$7116 + end + attribute \src "libresoc.v:138452.3-138460.6" + process $proc$libresoc.v:138452$7118 + assign { } { } + assign { } { } + assign $0\src_l_s_src$next[2:0]$7119 $1\src_l_s_src$next[2:0]$7120 + attribute \src "libresoc.v:138453.5-138453.29" + switch \initial + attribute \src "libresoc.v:138453.9-138453.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_l_s_src$next[2:0]$7120 3'000 + case + assign $1\src_l_s_src$next[2:0]$7120 { \cu_issue_i \cu_issue_i \cu_issue_i } + end + sync always + update \src_l_s_src$next $0\src_l_s_src$next[2:0]$7119 + end + attribute \src "libresoc.v:138461.3-138469.6" + process $proc$libresoc.v:138461$7121 + assign { } { } + assign { } { } + assign $0\src_l_r_src$next[2:0]$7122 $1\src_l_r_src$next[2:0]$7123 + attribute \src "libresoc.v:138462.5-138462.29" + switch \initial + attribute \src "libresoc.v:138462.9-138462.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_l_r_src$next[2:0]$7123 3'111 + case + assign $1\src_l_r_src$next[2:0]$7123 \reset_r + end + sync always + update \src_l_r_src$next $0\src_l_r_src$next[2:0]$7122 + end + attribute \src "libresoc.v:138470.3-138478.6" + process $proc$libresoc.v:138470$7124 + assign { } { } + assign { } { } + assign $0\req_l_s_req$next[3:0]$7125 $1\req_l_s_req$next[3:0]$7126 + attribute \src "libresoc.v:138471.5-138471.29" + switch \initial + attribute \src "libresoc.v:138471.9-138471.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\req_l_s_req$next[3:0]$7126 4'0000 + case + assign $1\req_l_s_req$next[3:0]$7126 \$66 + end + sync always + update \req_l_s_req$next $0\req_l_s_req$next[3:0]$7125 + end + attribute \src "libresoc.v:138479.3-138487.6" + process $proc$libresoc.v:138479$7127 + assign { } { } + assign { } { } + assign $0\req_l_r_req$next[3:0]$7128 $1\req_l_r_req$next[3:0]$7129 + attribute \src "libresoc.v:138480.5-138480.29" + switch \initial + attribute \src "libresoc.v:138480.9-138480.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\req_l_r_req$next[3:0]$7129 4'1111 + case + assign $1\req_l_r_req$next[3:0]$7129 \$68 + end + sync always + update \req_l_r_req$next $0\req_l_r_req$next[3:0]$7128 + end + attribute \src "libresoc.v:138488.3-138520.6" + process $proc$libresoc.v:138488$7130 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\alu_mul0_mul_op__fn_unit$next[11:0]$7131 $1\alu_mul0_mul_op__fn_unit$next[11:0]$7143 + assign { } { } + assign { } { } + assign $0\alu_mul0_mul_op__insn$next[31:0]$7134 $1\alu_mul0_mul_op__insn$next[31:0]$7146 + assign $0\alu_mul0_mul_op__insn_type$next[6:0]$7135 $1\alu_mul0_mul_op__insn_type$next[6:0]$7147 + assign $0\alu_mul0_mul_op__is_32bit$next[0:0]$7136 $1\alu_mul0_mul_op__is_32bit$next[0:0]$7148 + assign $0\alu_mul0_mul_op__is_signed$next[0:0]$7137 $1\alu_mul0_mul_op__is_signed$next[0:0]$7149 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\alu_mul0_mul_op__write_cr0$next[0:0]$7142 $1\alu_mul0_mul_op__write_cr0$next[0:0]$7154 + assign $0\alu_mul0_mul_op__imm_data__data$next[63:0]$7132 $2\alu_mul0_mul_op__imm_data__data$next[63:0]$7155 + assign $0\alu_mul0_mul_op__imm_data__ok$next[0:0]$7133 $2\alu_mul0_mul_op__imm_data__ok$next[0:0]$7156 + assign $0\alu_mul0_mul_op__oe__oe$next[0:0]$7138 $2\alu_mul0_mul_op__oe__oe$next[0:0]$7157 + assign $0\alu_mul0_mul_op__oe__ok$next[0:0]$7139 $2\alu_mul0_mul_op__oe__ok$next[0:0]$7158 + assign $0\alu_mul0_mul_op__rc__ok$next[0:0]$7140 $2\alu_mul0_mul_op__rc__ok$next[0:0]$7159 + assign $0\alu_mul0_mul_op__rc__rc$next[0:0]$7141 $2\alu_mul0_mul_op__rc__rc$next[0:0]$7160 + attribute \src "libresoc.v:138489.5-138489.29" + switch \initial + attribute \src "libresoc.v:138489.9-138489.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\alu_mul0_mul_op__insn$next[31:0]$7146 $1\alu_mul0_mul_op__is_signed$next[0:0]$7149 $1\alu_mul0_mul_op__is_32bit$next[0:0]$7148 $1\alu_mul0_mul_op__write_cr0$next[0:0]$7154 $1\alu_mul0_mul_op__oe__ok$next[0:0]$7151 $1\alu_mul0_mul_op__oe__oe$next[0:0]$7150 $1\alu_mul0_mul_op__rc__ok$next[0:0]$7152 $1\alu_mul0_mul_op__rc__rc$next[0:0]$7153 $1\alu_mul0_mul_op__imm_data__ok$next[0:0]$7145 $1\alu_mul0_mul_op__imm_data__data$next[63:0]$7144 $1\alu_mul0_mul_op__fn_unit$next[11:0]$7143 $1\alu_mul0_mul_op__insn_type$next[6:0]$7147 } { \oper_i_alu_mul0__insn \oper_i_alu_mul0__is_signed \oper_i_alu_mul0__is_32bit \oper_i_alu_mul0__write_cr0 \oper_i_alu_mul0__oe__ok \oper_i_alu_mul0__oe__oe \oper_i_alu_mul0__rc__ok \oper_i_alu_mul0__rc__rc \oper_i_alu_mul0__imm_data__ok \oper_i_alu_mul0__imm_data__data \oper_i_alu_mul0__fn_unit \oper_i_alu_mul0__insn_type } + case + assign $1\alu_mul0_mul_op__fn_unit$next[11:0]$7143 \alu_mul0_mul_op__fn_unit + assign $1\alu_mul0_mul_op__imm_data__data$next[63:0]$7144 \alu_mul0_mul_op__imm_data__data + assign $1\alu_mul0_mul_op__imm_data__ok$next[0:0]$7145 \alu_mul0_mul_op__imm_data__ok + assign $1\alu_mul0_mul_op__insn$next[31:0]$7146 \alu_mul0_mul_op__insn + assign $1\alu_mul0_mul_op__insn_type$next[6:0]$7147 \alu_mul0_mul_op__insn_type + assign $1\alu_mul0_mul_op__is_32bit$next[0:0]$7148 \alu_mul0_mul_op__is_32bit + assign $1\alu_mul0_mul_op__is_signed$next[0:0]$7149 \alu_mul0_mul_op__is_signed + assign $1\alu_mul0_mul_op__oe__oe$next[0:0]$7150 \alu_mul0_mul_op__oe__oe + assign $1\alu_mul0_mul_op__oe__ok$next[0:0]$7151 \alu_mul0_mul_op__oe__ok + assign $1\alu_mul0_mul_op__rc__ok$next[0:0]$7152 \alu_mul0_mul_op__rc__ok + assign $1\alu_mul0_mul_op__rc__rc$next[0:0]$7153 \alu_mul0_mul_op__rc__rc + assign $1\alu_mul0_mul_op__write_cr0$next[0:0]$7154 \alu_mul0_mul_op__write_cr0 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $2\alu_mul0_mul_op__imm_data__data$next[63:0]$7155 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\alu_mul0_mul_op__imm_data__ok$next[0:0]$7156 1'0 + assign $2\alu_mul0_mul_op__rc__rc$next[0:0]$7160 1'0 + assign $2\alu_mul0_mul_op__rc__ok$next[0:0]$7159 1'0 + assign $2\alu_mul0_mul_op__oe__oe$next[0:0]$7157 1'0 + assign $2\alu_mul0_mul_op__oe__ok$next[0:0]$7158 1'0 + case + assign $2\alu_mul0_mul_op__imm_data__data$next[63:0]$7155 $1\alu_mul0_mul_op__imm_data__data$next[63:0]$7144 + assign $2\alu_mul0_mul_op__imm_data__ok$next[0:0]$7156 $1\alu_mul0_mul_op__imm_data__ok$next[0:0]$7145 + assign $2\alu_mul0_mul_op__oe__oe$next[0:0]$7157 $1\alu_mul0_mul_op__oe__oe$next[0:0]$7150 + assign $2\alu_mul0_mul_op__oe__ok$next[0:0]$7158 $1\alu_mul0_mul_op__oe__ok$next[0:0]$7151 + assign $2\alu_mul0_mul_op__rc__ok$next[0:0]$7159 $1\alu_mul0_mul_op__rc__ok$next[0:0]$7152 + assign $2\alu_mul0_mul_op__rc__rc$next[0:0]$7160 $1\alu_mul0_mul_op__rc__rc$next[0:0]$7153 + end + sync always + update \alu_mul0_mul_op__fn_unit$next $0\alu_mul0_mul_op__fn_unit$next[11:0]$7131 + update \alu_mul0_mul_op__imm_data__data$next $0\alu_mul0_mul_op__imm_data__data$next[63:0]$7132 + update \alu_mul0_mul_op__imm_data__ok$next $0\alu_mul0_mul_op__imm_data__ok$next[0:0]$7133 + update \alu_mul0_mul_op__insn$next $0\alu_mul0_mul_op__insn$next[31:0]$7134 + update \alu_mul0_mul_op__insn_type$next $0\alu_mul0_mul_op__insn_type$next[6:0]$7135 + update \alu_mul0_mul_op__is_32bit$next $0\alu_mul0_mul_op__is_32bit$next[0:0]$7136 + update \alu_mul0_mul_op__is_signed$next $0\alu_mul0_mul_op__is_signed$next[0:0]$7137 + update \alu_mul0_mul_op__oe__oe$next $0\alu_mul0_mul_op__oe__oe$next[0:0]$7138 + update \alu_mul0_mul_op__oe__ok$next $0\alu_mul0_mul_op__oe__ok$next[0:0]$7139 + update \alu_mul0_mul_op__rc__ok$next $0\alu_mul0_mul_op__rc__ok$next[0:0]$7140 + update \alu_mul0_mul_op__rc__rc$next $0\alu_mul0_mul_op__rc__rc$next[0:0]$7141 + update \alu_mul0_mul_op__write_cr0$next $0\alu_mul0_mul_op__write_cr0$next[0:0]$7142 + end + attribute \src "libresoc.v:138521.3-138542.6" + process $proc$libresoc.v:138521$7161 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r0__o$next[63:0]$7162 $2\data_r0__o$next[63:0]$7166 + assign { } { } + assign $0\data_r0__o_ok$next[0:0]$7163 $3\data_r0__o_ok$next[0:0]$7168 + attribute \src "libresoc.v:138522.5-138522.29" + switch \initial + attribute \src "libresoc.v:138522.9-138522.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r0__o_ok$next[0:0]$7165 $1\data_r0__o$next[63:0]$7164 } { \o_ok \alu_mul0_o } + case + assign $1\data_r0__o$next[63:0]$7164 \data_r0__o + assign $1\data_r0__o_ok$next[0:0]$7165 \data_r0__o_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r0__o_ok$next[0:0]$7167 $2\data_r0__o$next[63:0]$7166 } 65'00000000000000000000000000000000000000000000000000000000000000000 + case + assign $2\data_r0__o$next[63:0]$7166 $1\data_r0__o$next[63:0]$7164 + assign $2\data_r0__o_ok$next[0:0]$7167 $1\data_r0__o_ok$next[0:0]$7165 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r0__o_ok$next[0:0]$7168 1'0 + case + assign $3\data_r0__o_ok$next[0:0]$7168 $2\data_r0__o_ok$next[0:0]$7167 + end + sync always + update \data_r0__o$next $0\data_r0__o$next[63:0]$7162 + update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$7163 + end + attribute \src "libresoc.v:138543.3-138564.6" + process $proc$libresoc.v:138543$7169 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r1__cr_a$next[3:0]$7170 $2\data_r1__cr_a$next[3:0]$7174 + assign { } { } + assign $0\data_r1__cr_a_ok$next[0:0]$7171 $3\data_r1__cr_a_ok$next[0:0]$7176 + attribute \src "libresoc.v:138544.5-138544.29" + switch \initial + attribute \src "libresoc.v:138544.9-138544.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r1__cr_a_ok$next[0:0]$7173 $1\data_r1__cr_a$next[3:0]$7172 } { \cr_a_ok \alu_mul0_cr_a } + case + assign $1\data_r1__cr_a$next[3:0]$7172 \data_r1__cr_a + assign $1\data_r1__cr_a_ok$next[0:0]$7173 \data_r1__cr_a_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r1__cr_a_ok$next[0:0]$7175 $2\data_r1__cr_a$next[3:0]$7174 } 5'00000 + case + assign $2\data_r1__cr_a$next[3:0]$7174 $1\data_r1__cr_a$next[3:0]$7172 + assign $2\data_r1__cr_a_ok$next[0:0]$7175 $1\data_r1__cr_a_ok$next[0:0]$7173 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r1__cr_a_ok$next[0:0]$7176 1'0 + case + assign $3\data_r1__cr_a_ok$next[0:0]$7176 $2\data_r1__cr_a_ok$next[0:0]$7175 + end + sync always + update \data_r1__cr_a$next $0\data_r1__cr_a$next[3:0]$7170 + update \data_r1__cr_a_ok$next $0\data_r1__cr_a_ok$next[0:0]$7171 + end + attribute \src "libresoc.v:138565.3-138586.6" + process $proc$libresoc.v:138565$7177 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r2__xer_ov$next[1:0]$7178 $2\data_r2__xer_ov$next[1:0]$7182 + assign { } { } + assign $0\data_r2__xer_ov_ok$next[0:0]$7179 $3\data_r2__xer_ov_ok$next[0:0]$7184 + attribute \src "libresoc.v:138566.5-138566.29" + switch \initial + attribute \src "libresoc.v:138566.9-138566.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r2__xer_ov_ok$next[0:0]$7181 $1\data_r2__xer_ov$next[1:0]$7180 } { \xer_ov_ok \alu_mul0_xer_ov } + case + assign $1\data_r2__xer_ov$next[1:0]$7180 \data_r2__xer_ov + assign $1\data_r2__xer_ov_ok$next[0:0]$7181 \data_r2__xer_ov_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r2__xer_ov_ok$next[0:0]$7183 $2\data_r2__xer_ov$next[1:0]$7182 } 3'000 + case + assign $2\data_r2__xer_ov$next[1:0]$7182 $1\data_r2__xer_ov$next[1:0]$7180 + assign $2\data_r2__xer_ov_ok$next[0:0]$7183 $1\data_r2__xer_ov_ok$next[0:0]$7181 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r2__xer_ov_ok$next[0:0]$7184 1'0 + case + assign $3\data_r2__xer_ov_ok$next[0:0]$7184 $2\data_r2__xer_ov_ok$next[0:0]$7183 + end + sync always + update \data_r2__xer_ov$next $0\data_r2__xer_ov$next[1:0]$7178 + update \data_r2__xer_ov_ok$next $0\data_r2__xer_ov_ok$next[0:0]$7179 + end + attribute \src "libresoc.v:138587.3-138608.6" + process $proc$libresoc.v:138587$7185 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r3__xer_so$next[0:0]$7186 $2\data_r3__xer_so$next[0:0]$7190 + assign { } { } + assign $0\data_r3__xer_so_ok$next[0:0]$7187 $3\data_r3__xer_so_ok$next[0:0]$7192 + attribute \src "libresoc.v:138588.5-138588.29" + switch \initial + attribute \src "libresoc.v:138588.9-138588.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r3__xer_so_ok$next[0:0]$7189 $1\data_r3__xer_so$next[0:0]$7188 } { \xer_so_ok \alu_mul0_xer_so } + case + assign $1\data_r3__xer_so$next[0:0]$7188 \data_r3__xer_so + assign $1\data_r3__xer_so_ok$next[0:0]$7189 \data_r3__xer_so_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r3__xer_so_ok$next[0:0]$7191 $2\data_r3__xer_so$next[0:0]$7190 } 2'00 + case + assign $2\data_r3__xer_so$next[0:0]$7190 $1\data_r3__xer_so$next[0:0]$7188 + assign $2\data_r3__xer_so_ok$next[0:0]$7191 $1\data_r3__xer_so_ok$next[0:0]$7189 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r3__xer_so_ok$next[0:0]$7192 1'0 + case + assign $3\data_r3__xer_so_ok$next[0:0]$7192 $2\data_r3__xer_so_ok$next[0:0]$7191 + end + sync always + update \data_r3__xer_so$next $0\data_r3__xer_so$next[0:0]$7186 + update \data_r3__xer_so_ok$next $0\data_r3__xer_so_ok$next[0:0]$7187 + end + attribute \src "libresoc.v:138609.3-138618.6" + process $proc$libresoc.v:138609$7193 + assign { } { } + assign { } { } + assign $0\src_r0$next[63:0]$7194 $1\src_r0$next[63:0]$7195 + attribute \src "libresoc.v:138610.5-138610.29" + switch \initial + attribute \src "libresoc.v:138610.9-138610.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch \src_l_q_src [0] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r0$next[63:0]$7195 \src1_i + case + assign $1\src_r0$next[63:0]$7195 \src_r0 + end + sync always + update \src_r0$next $0\src_r0$next[63:0]$7194 + end + attribute \src "libresoc.v:138619.3-138628.6" + process $proc$libresoc.v:138619$7196 + assign { } { } + assign { } { } + assign $0\src_r1$next[63:0]$7197 $1\src_r1$next[63:0]$7198 + attribute \src "libresoc.v:138620.5-138620.29" + switch \initial + attribute \src "libresoc.v:138620.9-138620.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch \src_sel + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r1$next[63:0]$7198 \src_or_imm + case + assign $1\src_r1$next[63:0]$7198 \src_r1 + end + sync always + update \src_r1$next $0\src_r1$next[63:0]$7197 + end + attribute \src "libresoc.v:138629.3-138638.6" + process $proc$libresoc.v:138629$7199 + assign { } { } + assign { } { } + assign $0\src_r2$next[0:0]$7200 $1\src_r2$next[0:0]$7201 + attribute \src "libresoc.v:138630.5-138630.29" + switch \initial + attribute \src "libresoc.v:138630.9-138630.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch \src_l_q_src [2] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r2$next[0:0]$7201 \src3_i + case + assign $1\src_r2$next[0:0]$7201 \src_r2 + end + sync always + update \src_r2$next $0\src_r2$next[0:0]$7200 + end + attribute \src "libresoc.v:138639.3-138647.6" + process $proc$libresoc.v:138639$7202 + assign { } { } + assign { } { } + assign $0\alui_l_r_alui$next[0:0]$7203 $1\alui_l_r_alui$next[0:0]$7204 + attribute \src "libresoc.v:138640.5-138640.29" + switch \initial + attribute \src "libresoc.v:138640.9-138640.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\alui_l_r_alui$next[0:0]$7204 1'1 + case + assign $1\alui_l_r_alui$next[0:0]$7204 \$88 + end + sync always + update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$7203 + end + attribute \src "libresoc.v:138648.3-138656.6" + process $proc$libresoc.v:138648$7205 + assign { } { } + assign { } { } + assign $0\alu_l_r_alu$next[0:0]$7206 $1\alu_l_r_alu$next[0:0]$7207 + attribute \src "libresoc.v:138649.5-138649.29" + switch \initial + attribute \src "libresoc.v:138649.9-138649.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\alu_l_r_alu$next[0:0]$7207 1'1 + case + assign $1\alu_l_r_alu$next[0:0]$7207 \$90 + end + sync always + update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$7206 + end + attribute \src "libresoc.v:138657.3-138666.6" + process $proc$libresoc.v:138657$7208 + assign { } { } + assign { } { } + assign $0\dest1_o[63:0] $1\dest1_o[63:0] + attribute \src "libresoc.v:138658.5-138658.29" + switch \initial + attribute \src "libresoc.v:138658.9-138658.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$114 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest1_o[63:0] \data_r0__o + case + assign $1\dest1_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \dest1_o $0\dest1_o[63:0] + end + attribute \src "libresoc.v:138667.3-138676.6" + process $proc$libresoc.v:138667$7209 + assign { } { } + assign { } { } + assign $0\dest2_o[3:0] $1\dest2_o[3:0] + attribute \src "libresoc.v:138668.5-138668.29" + switch \initial + attribute \src "libresoc.v:138668.9-138668.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$116 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest2_o[3:0] \data_r1__cr_a + case + assign $1\dest2_o[3:0] 4'0000 + end + sync always + update \dest2_o $0\dest2_o[3:0] + end + attribute \src "libresoc.v:138677.3-138686.6" + process $proc$libresoc.v:138677$7210 + assign { } { } + assign { } { } + assign $0\dest3_o[1:0] $1\dest3_o[1:0] + attribute \src "libresoc.v:138678.5-138678.29" + switch \initial + attribute \src "libresoc.v:138678.9-138678.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$118 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest3_o[1:0] \data_r2__xer_ov + case + assign $1\dest3_o[1:0] 2'00 + end + sync always + update \dest3_o $0\dest3_o[1:0] + end + attribute \src "libresoc.v:138687.3-138696.6" + process $proc$libresoc.v:138687$7211 + assign { } { } + assign { } { } + assign $0\dest4_o[0:0] $1\dest4_o[0:0] + attribute \src "libresoc.v:138688.5-138688.29" + switch \initial + attribute \src "libresoc.v:138688.9-138688.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$120 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest4_o[0:0] \data_r3__xer_so + case + assign $1\dest4_o[0:0] 1'0 + end + sync always + update \dest4_o $0\dest4_o[0:0] + end + attribute \src "libresoc.v:138697.3-138705.6" + process $proc$libresoc.v:138697$7212 + assign { } { } + assign { } { } + assign $0\prev_wr_go$next[3:0]$7213 $1\prev_wr_go$next[3:0]$7214 + attribute \src "libresoc.v:138698.5-138698.29" + switch \initial + attribute \src "libresoc.v:138698.9-138698.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\prev_wr_go$next[3:0]$7214 4'0000 + case + assign $1\prev_wr_go$next[3:0]$7214 \$20 + end + sync always + update \prev_wr_go$next $0\prev_wr_go$next[3:0]$7213 + end + connect \$100 $and$libresoc.v:138173$7001_Y + connect \$102 $and$libresoc.v:138174$7002_Y + connect \$104 $and$libresoc.v:138175$7003_Y + connect \$106 $and$libresoc.v:138176$7004_Y + connect \$108 $and$libresoc.v:138177$7005_Y + connect \$10 $and$libresoc.v:138178$7006_Y + connect \$110 $and$libresoc.v:138179$7007_Y + connect \$112 $and$libresoc.v:138180$7008_Y + connect \$114 $and$libresoc.v:138181$7009_Y + connect \$116 $and$libresoc.v:138182$7010_Y + connect \$118 $and$libresoc.v:138183$7011_Y + connect \$120 $and$libresoc.v:138184$7012_Y + connect \$12 $not$libresoc.v:138185$7013_Y + connect \$14 $and$libresoc.v:138186$7014_Y + connect \$16 $not$libresoc.v:138187$7015_Y + connect \$18 $and$libresoc.v:138188$7016_Y + connect \$20 $and$libresoc.v:138189$7017_Y + connect \$24 $not$libresoc.v:138190$7018_Y + connect \$26 $and$libresoc.v:138191$7019_Y + connect \$23 $reduce_or$libresoc.v:138192$7020_Y + connect \$22 $not$libresoc.v:138193$7021_Y + connect \$2 $and$libresoc.v:138194$7022_Y + connect \$30 $and$libresoc.v:138195$7023_Y + connect \$32 $reduce_or$libresoc.v:138196$7024_Y + connect \$34 $reduce_or$libresoc.v:138197$7025_Y + connect \$36 $or$libresoc.v:138198$7026_Y + connect \$38 $not$libresoc.v:138199$7027_Y + connect \$40 $and$libresoc.v:138200$7028_Y + connect \$42 $and$libresoc.v:138201$7029_Y + connect \$44 $eq$libresoc.v:138202$7030_Y + connect \$46 $and$libresoc.v:138203$7031_Y + connect \$48 $eq$libresoc.v:138204$7032_Y + connect \$50 $and$libresoc.v:138205$7033_Y + connect \$52 $and$libresoc.v:138206$7034_Y + connect \$54 $and$libresoc.v:138207$7035_Y + connect \$56 $or$libresoc.v:138208$7036_Y + connect \$58 $or$libresoc.v:138209$7037_Y + connect \$5 $not$libresoc.v:138210$7038_Y + connect \$60 $or$libresoc.v:138211$7039_Y + connect \$62 $or$libresoc.v:138212$7040_Y + connect \$64 $and$libresoc.v:138213$7041_Y + connect \$66 $and$libresoc.v:138214$7042_Y + connect \$68 $or$libresoc.v:138215$7043_Y + connect \$70 $and$libresoc.v:138216$7044_Y + connect \$72 $and$libresoc.v:138217$7045_Y + connect \$74 $and$libresoc.v:138218$7046_Y + connect \$76 $and$libresoc.v:138219$7047_Y + connect \$78 $ternary$libresoc.v:138220$7048_Y + connect \$7 $or$libresoc.v:138221$7049_Y + connect \$80 $ternary$libresoc.v:138222$7050_Y + connect \$82 $ternary$libresoc.v:138223$7051_Y + connect \$84 $ternary$libresoc.v:138224$7052_Y + connect \$86 $ternary$libresoc.v:138225$7053_Y + connect \$88 $and$libresoc.v:138226$7054_Y + connect \$4 $reduce_and$libresoc.v:138227$7055_Y + connect \$90 $and$libresoc.v:138228$7056_Y + connect \$92 $and$libresoc.v:138229$7057_Y + connect \$94 $not$libresoc.v:138230$7058_Y + connect \$96 $and$libresoc.v:138231$7059_Y + connect \$98 $not$libresoc.v:138232$7060_Y + connect \cu_go_die_i 1'0 + connect \cu_shadown_i 1'1 + connect \cu_wr__rel_o \$112 + connect \cu_rd__rel_o \$100 + connect \cu_busy_o \opc_l_q_opc + connect \alu_l_s_alu \all_rd_pulse + connect \alu_mul0_n_ready_i \alu_l_q_alu + connect \alui_l_s_alui \all_rd_pulse + connect \alu_mul0_p_valid_i \alui_l_q_alui + connect \alu_mul0_xer_so$1 \$86 + connect \alu_mul0_rb \$84 + connect \alu_mul0_ra \$82 + connect \src_or_imm \$80 + connect \src_sel \$78 + connect \cu_wrmask_o { \$76 \$74 \$72 \$70 } + connect \reset_r \$62 + connect \reset_w \$60 + connect \rst_r \$58 + connect \reset \$56 + connect \wr_any \$36 + connect \cu_done_o \$30 + connect \alu_pulsem { \alu_pulse \alu_pulse \alu_pulse \alu_pulse } + connect \alu_pulse \alu_done_rise + connect \alu_done_rise \$18 + connect \alu_done_dly$next \alu_done + connect \alu_done \alu_mul0_n_valid_o + connect \all_rd_pulse \all_rd_rise + connect \all_rd_rise \$14 + connect \all_rd_dly$next \all_rd + connect \all_rd \$10 +end +attribute \src "libresoc.v:138740.1-139067.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe1.mul1" +attribute \generator "nMigen" +module \mul1 + attribute \src "libresoc.v:139034.18-139034.116" + wire $and$libresoc.v:139034$7255_Y + attribute \src "libresoc.v:139036.18-139036.116" + wire $and$libresoc.v:139036$7257_Y + attribute \src "libresoc.v:139037.18-139037.117" + wire $and$libresoc.v:139037$7258_Y + attribute \src "libresoc.v:139038.18-139038.117" + wire $and$libresoc.v:139038$7259_Y + attribute \src "libresoc.v:139041.18-139041.95" + wire width 65 $extend$libresoc.v:139041$7262_Y + attribute \src "libresoc.v:139042.18-139042.91" + wire width 65 $extend$libresoc.v:139042$7264_Y + attribute \src "libresoc.v:139044.18-139044.95" + wire width 65 $extend$libresoc.v:139044$7267_Y + attribute \src "libresoc.v:139045.18-139045.91" + wire width 65 $extend$libresoc.v:139045$7269_Y + attribute \src "libresoc.v:139041.18-139041.95" + wire width 65 $neg$libresoc.v:139041$7263_Y + attribute \src "libresoc.v:139044.18-139044.95" + wire width 65 $neg$libresoc.v:139044$7268_Y + attribute \src "libresoc.v:139042.18-139042.91" + wire width 65 $pos$libresoc.v:139042$7265_Y + attribute \src "libresoc.v:139045.18-139045.91" + wire width 65 $pos$libresoc.v:139045$7270_Y + attribute \src "libresoc.v:139033.18-139033.125" + wire $ternary$libresoc.v:139033$7254_Y + attribute \src "libresoc.v:139035.18-139035.125" + wire $ternary$libresoc.v:139035$7256_Y + attribute \src "libresoc.v:139043.18-139043.112" + wire width 65 $ternary$libresoc.v:139043$7266_Y + attribute \src "libresoc.v:139046.18-139046.112" + wire width 65 $ternary$libresoc.v:139046$7271_Y + attribute \src "libresoc.v:139047.18-139047.116" + wire width 32 $ternary$libresoc.v:139047$7272_Y + attribute \src "libresoc.v:139048.18-139048.116" + wire width 32 $ternary$libresoc.v:139048$7273_Y + attribute \src "libresoc.v:139039.18-139039.106" + wire $xor$libresoc.v:139039$7260_Y + attribute \src "libresoc.v:139040.18-139040.110" + wire $xor$libresoc.v:139040$7261_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:38" + wire \$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:38" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:39" + wire \$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:39" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:40" + wire \$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:41" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:44" + wire \$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:45" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:52" + wire width 65 \$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:52" + wire width 65 \$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 65 \$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:52" + wire width 65 \$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:53" + wire width 65 \$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:53" + wire width 65 \$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 65 \$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:53" + wire width 65 \$45 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:34" + wire width 32 \$47 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:34" + wire width 32 \$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:50" + wire width 64 \abs_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:51" + wire width 64 \abs_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:30" + wire \is_32bit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 2 \mul_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 output 18 \mul_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 3 \mul_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 19 \mul_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 4 \mul_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 20 \mul_op__imm_data__ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 12 \mul_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 28 \mul_op__insn$13 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \mul_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 17 \mul_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \mul_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 26 \mul_op__is_32bit$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 11 \mul_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 27 \mul_op__is_signed$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 7 \mul_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 23 \mul_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \mul_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 24 \mul_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 6 \mul_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 22 \mul_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 5 \mul_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 21 \mul_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \mul_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 25 \mul_op__write_cr0$10 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 34 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 16 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" + wire output 32 \neg_res + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" + wire output 33 \neg_res32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 13 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 29 \ra$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 14 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 30 \rb$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:33" + wire \sign32_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:34" + wire \sign32_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:31" + wire \sign_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:32" + wire \sign_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 15 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire output 31 \xer_so$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:38" + cell $and $and$libresoc.v:139034$7255 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$17 + connect \B \mul_op__is_signed + connect \Y $and$libresoc.v:139034$7255_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:39" + cell $and $and$libresoc.v:139036$7257 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$21 + connect \B \mul_op__is_signed + connect \Y $and$libresoc.v:139036$7257_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:40" + cell $and $and$libresoc.v:139037$7258 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ra [31] + connect \B \mul_op__is_signed + connect \Y $and$libresoc.v:139037$7258_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:41" + cell $and $and$libresoc.v:139038$7259 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \rb [31] + connect \B \mul_op__is_signed + connect \Y $and$libresoc.v:139038$7259_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:52" + cell $pos $extend$libresoc.v:139041$7262 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \ra + connect \Y $extend$libresoc.v:139041$7262_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + cell $pos $extend$libresoc.v:139042$7264 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \ra + connect \Y $extend$libresoc.v:139042$7264_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:53" + cell $pos $extend$libresoc.v:139044$7267 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \rb + connect \Y $extend$libresoc.v:139044$7267_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + cell $pos $extend$libresoc.v:139045$7269 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \rb + connect \Y $extend$libresoc.v:139045$7269_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:52" + cell $neg $neg$libresoc.v:139041$7263 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \Y_WIDTH 65 + connect \A $extend$libresoc.v:139041$7262_Y + connect \Y $neg$libresoc.v:139041$7263_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:53" + cell $neg $neg$libresoc.v:139044$7268 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \Y_WIDTH 65 + connect \A $extend$libresoc.v:139044$7267_Y + connect \Y $neg$libresoc.v:139044$7268_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + cell $pos $pos$libresoc.v:139042$7265 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \Y_WIDTH 65 + connect \A $extend$libresoc.v:139042$7264_Y + connect \Y $pos$libresoc.v:139042$7265_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + cell $pos $pos$libresoc.v:139045$7270 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \Y_WIDTH 65 + connect \A $extend$libresoc.v:139045$7269_Y + connect \Y $pos$libresoc.v:139045$7270_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:38" + cell $mux $ternary$libresoc.v:139033$7254 + parameter \WIDTH 1 + connect \A \ra [63] + connect \B \ra [31] + connect \S \mul_op__is_32bit + connect \Y $ternary$libresoc.v:139033$7254_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:39" + cell $mux $ternary$libresoc.v:139035$7256 + parameter \WIDTH 1 + connect \A \rb [63] + connect \B \rb [31] + connect \S \mul_op__is_32bit + connect \Y $ternary$libresoc.v:139035$7256_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:52" + cell $mux $ternary$libresoc.v:139043$7266 + parameter \WIDTH 65 + connect \A \$36 + connect \B \$34 + connect \S \sign_a + connect \Y $ternary$libresoc.v:139043$7266_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:53" + cell $mux $ternary$libresoc.v:139046$7271 + parameter \WIDTH 65 + connect \A \$43 + connect \B \$41 + connect \S \sign_b + connect \Y $ternary$libresoc.v:139046$7271_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:34" + cell $mux $ternary$libresoc.v:139047$7272 + parameter \WIDTH 32 + connect \A \abs_a [63:32] + connect \B 0 + connect \S \is_32bit + connect \Y $ternary$libresoc.v:139047$7272_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:34" + cell $mux $ternary$libresoc.v:139048$7273 + parameter \WIDTH 32 + connect \A \abs_b [63:32] + connect \B 0 + connect \S \is_32bit + connect \Y $ternary$libresoc.v:139048$7273_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:44" + cell $xor $xor$libresoc.v:139039$7260 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \sign_a + connect \B \sign_b + connect \Y $xor$libresoc.v:139039$7260_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:45" + cell $xor $xor$libresoc.v:139040$7261 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \sign32_a + connect \B \sign32_b + connect \Y $xor$libresoc.v:139040$7261_Y + end + connect \$17 $ternary$libresoc.v:139033$7254_Y + connect \$19 $and$libresoc.v:139034$7255_Y + connect \$21 $ternary$libresoc.v:139035$7256_Y + connect \$23 $and$libresoc.v:139036$7257_Y + connect \$25 $and$libresoc.v:139037$7258_Y + connect \$27 $and$libresoc.v:139038$7259_Y + connect \$29 $xor$libresoc.v:139039$7260_Y + connect \$31 $xor$libresoc.v:139040$7261_Y + connect \$34 $neg$libresoc.v:139041$7263_Y + connect \$36 $pos$libresoc.v:139042$7265_Y + connect \$38 $ternary$libresoc.v:139043$7266_Y + connect \$41 $neg$libresoc.v:139044$7268_Y + connect \$43 $pos$libresoc.v:139045$7270_Y + connect \$45 $ternary$libresoc.v:139046$7271_Y + connect \$47 $ternary$libresoc.v:139047$7272_Y + connect \$49 $ternary$libresoc.v:139048$7273_Y + connect \$33 \$38 + connect \$40 \$45 + connect { \mul_op__insn$13 \mul_op__is_signed$12 \mul_op__is_32bit$11 \mul_op__write_cr0$10 \mul_op__oe__ok$9 \mul_op__oe__oe$8 \mul_op__rc__ok$7 \mul_op__rc__rc$6 \mul_op__imm_data__ok$5 \mul_op__imm_data__data$4 \mul_op__fn_unit$3 \mul_op__insn_type$2 } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__oe__ok \mul_op__oe__oe \mul_op__rc__ok \mul_op__rc__rc \mul_op__imm_data__ok \mul_op__imm_data__data \mul_op__fn_unit \mul_op__insn_type } + connect \muxid$1 \muxid + connect \xer_so$16 \xer_so + connect \rb$15 [63:32] \$49 + connect \rb$15 [31:0] \abs_b [31:0] + connect \ra$14 [63:32] \$47 + connect \ra$14 [31:0] \abs_a [31:0] + connect \abs_b \$45 [63:0] + connect \abs_a \$38 [63:0] + connect \neg_res32 \$31 + connect \neg_res \$29 + connect \sign32_b \$27 + connect \sign32_a \$25 + connect \sign_b \$23 + connect \sign_a \$19 + connect \is_32bit \mul_op__is_32bit +end +attribute \src "libresoc.v:139071.1-139328.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe2.mul2" +attribute \generator "nMigen" +module \mul2 + attribute \src "libresoc.v:139321.18-139321.98" + wire width 129 $extend$libresoc.v:139321$7275_Y + attribute \src "libresoc.v:139320.18-139320.99" + wire width 128 $mul$libresoc.v:139320$7274_Y + attribute \src "libresoc.v:139321.18-139321.98" + wire width 129 $pos$libresoc.v:139321$7276_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/main_stage.py:28" + wire width 129 \$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/main_stage.py:28" + wire width 128 \$18 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 2 \mul_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 output 20 \mul_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 3 \mul_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 21 \mul_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 4 \mul_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 22 \mul_op__imm_data__ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 12 \mul_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 30 \mul_op__insn$13 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \mul_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 19 \mul_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \mul_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 28 \mul_op__is_32bit$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 11 \mul_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 29 \mul_op__is_signed$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 7 \mul_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 25 \mul_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \mul_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 26 \mul_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 6 \mul_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 24 \mul_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 5 \mul_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 23 \mul_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \mul_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 27 \mul_op__write_cr0$10 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 35 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 18 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" + wire input 16 \neg_res + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" + wire output 33 \neg_res$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" + wire input 17 \neg_res32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" + wire output 34 \neg_res32$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 129 output 31 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 13 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 14 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 15 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire output 32 \xer_so$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/main_stage.py:28" + cell $pos $extend$libresoc.v:139321$7275 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \Y_WIDTH 129 + connect \A \$18 + connect \Y $extend$libresoc.v:139321$7275_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/main_stage.py:28" + cell $mul $mul$libresoc.v:139320$7274 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 128 + connect \A \ra + connect \B \rb + connect \Y $mul$libresoc.v:139320$7274_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/main_stage.py:28" + cell $pos $pos$libresoc.v:139321$7276 + parameter \A_SIGNED 0 + parameter \A_WIDTH 129 + parameter \Y_WIDTH 129 + connect \A $extend$libresoc.v:139321$7275_Y + connect \Y $pos$libresoc.v:139321$7276_Y + end + connect \$18 $mul$libresoc.v:139320$7274_Y + connect \$17 $pos$libresoc.v:139321$7276_Y + connect { \mul_op__insn$13 \mul_op__is_signed$12 \mul_op__is_32bit$11 \mul_op__write_cr0$10 \mul_op__oe__ok$9 \mul_op__oe__oe$8 \mul_op__rc__ok$7 \mul_op__rc__rc$6 \mul_op__imm_data__ok$5 \mul_op__imm_data__data$4 \mul_op__fn_unit$3 \mul_op__insn_type$2 } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__oe__ok \mul_op__oe__oe \mul_op__rc__ok \mul_op__rc__rc \mul_op__imm_data__ok \mul_op__imm_data__data \mul_op__fn_unit \mul_op__insn_type } + connect \muxid$1 \muxid + connect \xer_so$14 \xer_so + connect \neg_res32$16 \neg_res32 + connect \neg_res$15 \neg_res + connect \o \$17 +end +attribute \src "libresoc.v:139332.1-139711.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe3.mul3" +attribute \generator "nMigen" +module \mul3 + attribute \src "libresoc.v:139333.7-139333.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:139664.3-139682.6" + wire $0\mul_ov[0:0] + attribute \src "libresoc.v:139626.3-139644.6" + wire width 64 $0\o$14[63:0]$7293 + attribute \src "libresoc.v:139645.3-139663.6" + wire $0\o_ok[0:0] + attribute \src "libresoc.v:139683.3-139693.6" + wire width 2 $0\xer_ov[1:0] + attribute \src "libresoc.v:139694.3-139704.6" + wire $0\xer_ov_ok[0:0] + attribute \src "libresoc.v:139664.3-139682.6" + wire $1\mul_ov[0:0] + attribute \src "libresoc.v:139626.3-139644.6" + wire width 64 $1\o$14[63:0]$7294 + attribute \src "libresoc.v:139645.3-139663.6" + wire $1\o_ok[0:0] + attribute \src "libresoc.v:139683.3-139693.6" + wire width 2 $1\xer_ov[1:0] + attribute \src "libresoc.v:139694.3-139704.6" + wire $1\xer_ov_ok[0:0] + attribute \src "libresoc.v:139664.3-139682.6" + wire $2\mul_ov[0:0] + attribute \src "libresoc.v:139620.18-139620.104" + wire $and$libresoc.v:139620$7285_Y + attribute \src "libresoc.v:139624.18-139624.104" + wire $and$libresoc.v:139624$7289_Y + attribute \src "libresoc.v:139614.18-139614.95" + wire width 130 $extend$libresoc.v:139614$7277_Y + attribute \src "libresoc.v:139615.18-139615.90" + wire width 130 $extend$libresoc.v:139615$7279_Y + attribute \src "libresoc.v:139625.18-139625.95" + wire width 2 $extend$libresoc.v:139625$7290_Y + attribute \src "libresoc.v:139614.18-139614.95" + wire width 130 $neg$libresoc.v:139614$7278_Y + attribute \src "libresoc.v:139619.18-139619.98" + wire $not$libresoc.v:139619$7284_Y + attribute \src "libresoc.v:139623.18-139623.98" + wire $not$libresoc.v:139623$7288_Y + attribute \src "libresoc.v:139615.18-139615.90" + wire width 130 $pos$libresoc.v:139615$7280_Y + attribute \src "libresoc.v:139625.18-139625.95" + wire width 2 $pos$libresoc.v:139625$7291_Y + attribute \src "libresoc.v:139618.18-139618.106" + wire $reduce_and$libresoc.v:139618$7283_Y + attribute \src "libresoc.v:139622.18-139622.107" + wire $reduce_and$libresoc.v:139622$7287_Y + attribute \src "libresoc.v:139617.18-139617.106" + wire $reduce_or$libresoc.v:139617$7282_Y + attribute \src "libresoc.v:139621.18-139621.107" + wire $reduce_or$libresoc.v:139621$7286_Y + attribute \src "libresoc.v:139616.18-139616.114" + wire width 130 $ternary$libresoc.v:139616$7281_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" + wire width 130 \$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" + wire width 130 \$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 130 \$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" + wire width 130 \$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" + wire \$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" + wire \$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" + wire \$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" + wire \$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" + wire \$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" + wire \$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 \$39 + attribute \src "libresoc.v:139333.7-139333.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:36" + wire \is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:40" + wire width 129 \mul_o + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 2 \mul_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 output 18 \mul_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 3 \mul_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 19 \mul_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 4 \mul_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 20 \mul_op__imm_data__ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 12 \mul_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 28 \mul_op__insn$13 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \mul_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 17 \mul_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \mul_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 26 \mul_op__is_32bit$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 11 \mul_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 27 \mul_op__is_signed$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 7 \mul_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 23 \mul_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \mul_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 24 \mul_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 6 \mul_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 22 \mul_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 5 \mul_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 21 \mul_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \mul_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 25 \mul_op__write_cr0$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:60" + wire \mul_ov + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 35 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 16 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" + wire input 15 \neg_res + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 129 input 13 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 29 \o$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 30 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 output 31 \xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 32 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 14 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 33 \xer_so$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 34 \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" + cell $and $and$libresoc.v:139620$7285 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$23 + connect \B \$25 + connect \Y $and$libresoc.v:139620$7285_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" + cell $and $and$libresoc.v:139624$7289 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$31 + connect \B \$33 + connect \Y $and$libresoc.v:139624$7289_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" + cell $pos $extend$libresoc.v:139614$7277 + parameter \A_SIGNED 0 + parameter \A_WIDTH 129 + parameter \Y_WIDTH 130 + connect \A \o + connect \Y $extend$libresoc.v:139614$7277_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + cell $pos $extend$libresoc.v:139615$7279 + parameter \A_SIGNED 0 + parameter \A_WIDTH 129 + parameter \Y_WIDTH 130 + connect \A \o + connect \Y $extend$libresoc.v:139615$7279_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + cell $pos $extend$libresoc.v:139625$7290 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 2 + connect \A \xer_so + connect \Y $extend$libresoc.v:139625$7290_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" + cell $neg $neg$libresoc.v:139614$7278 + parameter \A_SIGNED 0 + parameter \A_WIDTH 130 + parameter \Y_WIDTH 130 + connect \A $extend$libresoc.v:139614$7277_Y + connect \Y $neg$libresoc.v:139614$7278_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" + cell $not $not$libresoc.v:139619$7284 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$26 + connect \Y $not$libresoc.v:139619$7284_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" + cell $not $not$libresoc.v:139623$7288 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$34 + connect \Y $not$libresoc.v:139623$7288_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + cell $pos $pos$libresoc.v:139615$7280 + parameter \A_SIGNED 0 + parameter \A_WIDTH 130 + parameter \Y_WIDTH 130 + connect \A $extend$libresoc.v:139615$7279_Y + connect \Y $pos$libresoc.v:139615$7280_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + cell $pos $pos$libresoc.v:139625$7291 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A $extend$libresoc.v:139625$7290_Y + connect \Y $pos$libresoc.v:139625$7291_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" + cell $reduce_and $reduce_and$libresoc.v:139618$7283 + parameter \A_SIGNED 0 + parameter \A_WIDTH 33 + parameter \Y_WIDTH 1 + connect \A \mul_o [63:31] + connect \Y $reduce_and$libresoc.v:139618$7283_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" + cell $reduce_and $reduce_and$libresoc.v:139622$7287 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \Y_WIDTH 1 + connect \A \mul_o [127:63] + connect \Y $reduce_and$libresoc.v:139622$7287_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" + cell $reduce_or $reduce_or$libresoc.v:139617$7282 + parameter \A_SIGNED 0 + parameter \A_WIDTH 33 + parameter \Y_WIDTH 1 + connect \A \mul_o [63:31] + connect \Y $reduce_or$libresoc.v:139617$7282_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" + cell $reduce_or $reduce_or$libresoc.v:139621$7286 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \Y_WIDTH 1 + connect \A \mul_o [127:63] + connect \Y $reduce_or$libresoc.v:139621$7286_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" + cell $mux $ternary$libresoc.v:139616$7281 + parameter \WIDTH 130 + connect \A \$19 + connect \B \$17 + connect \S \neg_res + connect \Y $ternary$libresoc.v:139616$7281_Y + end + attribute \src "libresoc.v:139333.7-139333.20" + process $proc$libresoc.v:139333$7299 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:139626.3-139644.6" + process $proc$libresoc.v:139626$7292 + assign { } { } + assign { } { } + assign $0\o$14[63:0]$7293 $1\o$14[63:0]$7294 + attribute \src "libresoc.v:139627.5-139627.29" + switch \initial + attribute \src "libresoc.v:139627.9-139627.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:44" + switch \mul_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0110100 + assign { } { } + assign $1\o$14[63:0]$7294 { \mul_o [63:32] \mul_o [63:32] } + attribute \src "libresoc.v:0.0-0.0" + case 7'0110011 + assign { } { } + assign $1\o$14[63:0]$7294 \mul_o [127:64] + attribute \src "libresoc.v:0.0-0.0" + case 7'0110010 + assign { } { } + assign $1\o$14[63:0]$7294 \mul_o [63:0] + case + assign $1\o$14[63:0]$7294 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \o$14 $0\o$14[63:0]$7293 + end + attribute \src "libresoc.v:139645.3-139663.6" + process $proc$libresoc.v:139645$7295 + assign { } { } + assign { } { } + assign $0\o_ok[0:0] $1\o_ok[0:0] + attribute \src "libresoc.v:139646.5-139646.29" + switch \initial + attribute \src "libresoc.v:139646.9-139646.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:44" + switch \mul_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0110100 + assign { } { } + assign $1\o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 7'0110011 + assign { } { } + assign $1\o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 7'0110010 + assign { } { } + assign $1\o_ok[0:0] 1'1 + case + assign $1\o_ok[0:0] 1'0 + end + sync always + update \o_ok $0\o_ok[0:0] + end + attribute \src "libresoc.v:139664.3-139682.6" + process $proc$libresoc.v:139664$7296 + assign { } { } + assign { } { } + assign $0\mul_ov[0:0] $1\mul_ov[0:0] + attribute \src "libresoc.v:139665.5-139665.29" + switch \initial + attribute \src "libresoc.v:139665.9-139665.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:44" + switch \mul_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0110010 + assign { } { } + assign $1\mul_ov[0:0] $2\mul_ov[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:61" + switch \is_32bit + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\mul_ov[0:0] \$29 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\mul_ov[0:0] \$37 + end + case + assign $1\mul_ov[0:0] 1'0 + end + sync always + update \mul_ov $0\mul_ov[0:0] + end + attribute \src "libresoc.v:139683.3-139693.6" + process $proc$libresoc.v:139683$7297 + assign { } { } + assign { } { } + assign $0\xer_ov[1:0] $1\xer_ov[1:0] + attribute \src "libresoc.v:139684.5-139684.29" + switch \initial + attribute \src "libresoc.v:139684.9-139684.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:44" + switch \mul_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0110010 + assign { } { } + assign $1\xer_ov[1:0] { \mul_ov \mul_ov } + case + assign $1\xer_ov[1:0] 2'00 + end + sync always + update \xer_ov $0\xer_ov[1:0] + end + attribute \src "libresoc.v:139694.3-139704.6" + process $proc$libresoc.v:139694$7298 + assign { } { } + assign { } { } + assign $0\xer_ov_ok[0:0] $1\xer_ov_ok[0:0] + attribute \src "libresoc.v:139695.5-139695.29" + switch \initial + attribute \src "libresoc.v:139695.9-139695.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:44" + switch \mul_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0110010 + assign { } { } + assign $1\xer_ov_ok[0:0] 1'1 + case + assign $1\xer_ov_ok[0:0] 1'0 + end + sync always + update \xer_ov_ok $0\xer_ov_ok[0:0] + end + connect \$17 $neg$libresoc.v:139614$7278_Y + connect \$19 $pos$libresoc.v:139615$7280_Y + connect \$21 $ternary$libresoc.v:139616$7281_Y + connect \$23 $reduce_or$libresoc.v:139617$7282_Y + connect \$26 $reduce_and$libresoc.v:139618$7283_Y + connect \$25 $not$libresoc.v:139619$7284_Y + connect \$29 $and$libresoc.v:139620$7285_Y + connect \$31 $reduce_or$libresoc.v:139621$7286_Y + connect \$34 $reduce_and$libresoc.v:139622$7287_Y + connect \$33 $not$libresoc.v:139623$7288_Y + connect \$37 $and$libresoc.v:139624$7289_Y + connect \$39 $pos$libresoc.v:139625$7291_Y + connect \$16 \$21 + connect { \mul_op__insn$13 \mul_op__is_signed$12 \mul_op__is_32bit$11 \mul_op__write_cr0$10 \mul_op__oe__ok$9 \mul_op__oe__oe$8 \mul_op__rc__ok$7 \mul_op__rc__rc$6 \mul_op__imm_data__ok$5 \mul_op__imm_data__data$4 \mul_op__fn_unit$3 \mul_op__insn_type$2 } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__oe__ok \mul_op__oe__oe \mul_op__rc__ok \mul_op__rc__rc \mul_op__imm_data__ok \mul_op__imm_data__data \mul_op__fn_unit \mul_op__insn_type } + connect \muxid$1 \muxid + connect { \xer_so_ok \xer_so$15 } \$39 + connect \mul_o \$21 [128:0] + connect \is_32bit \mul_op__is_32bit +end +attribute \src "libresoc.v:139715.1-140911.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe1" +attribute \generator "nMigen" +module \mul_pipe1 + attribute \src "libresoc.v:139716.7-139716.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:140788.3-140823.6" + wire width 12 $0\mul_op__fn_unit$next[11:0]$7328 + attribute \src "libresoc.v:140653.3-140654.47" + wire width 12 $0\mul_op__fn_unit[11:0] + attribute \src "libresoc.v:140788.3-140823.6" + wire width 64 $0\mul_op__imm_data__data$next[63:0]$7329 + attribute \src "libresoc.v:140655.3-140656.61" + wire width 64 $0\mul_op__imm_data__data[63:0] + attribute \src "libresoc.v:140788.3-140823.6" + wire $0\mul_op__imm_data__ok$next[0:0]$7330 + attribute \src "libresoc.v:140657.3-140658.57" + wire $0\mul_op__imm_data__ok[0:0] + attribute \src "libresoc.v:140788.3-140823.6" + wire width 32 $0\mul_op__insn$next[31:0]$7331 + attribute \src "libresoc.v:140673.3-140674.41" + wire width 32 $0\mul_op__insn[31:0] + attribute \src "libresoc.v:140788.3-140823.6" + wire width 7 $0\mul_op__insn_type$next[6:0]$7332 + attribute \src "libresoc.v:140651.3-140652.51" + wire width 7 $0\mul_op__insn_type[6:0] + attribute \src "libresoc.v:140788.3-140823.6" + wire $0\mul_op__is_32bit$next[0:0]$7333 + attribute \src "libresoc.v:140669.3-140670.49" + wire $0\mul_op__is_32bit[0:0] + attribute \src "libresoc.v:140788.3-140823.6" + wire $0\mul_op__is_signed$next[0:0]$7334 + attribute \src "libresoc.v:140671.3-140672.51" + wire $0\mul_op__is_signed[0:0] + attribute \src "libresoc.v:140788.3-140823.6" + wire $0\mul_op__oe__oe$next[0:0]$7335 + attribute \src "libresoc.v:140663.3-140664.45" + wire $0\mul_op__oe__oe[0:0] + attribute \src "libresoc.v:140788.3-140823.6" + wire $0\mul_op__oe__ok$next[0:0]$7336 + attribute \src "libresoc.v:140665.3-140666.45" + wire $0\mul_op__oe__ok[0:0] + attribute \src "libresoc.v:140788.3-140823.6" + wire $0\mul_op__rc__ok$next[0:0]$7337 + attribute \src "libresoc.v:140661.3-140662.45" + wire $0\mul_op__rc__ok[0:0] + attribute \src "libresoc.v:140788.3-140823.6" + wire $0\mul_op__rc__rc$next[0:0]$7338 + attribute \src "libresoc.v:140659.3-140660.45" + wire $0\mul_op__rc__rc[0:0] + attribute \src "libresoc.v:140788.3-140823.6" + wire $0\mul_op__write_cr0$next[0:0]$7339 + attribute \src "libresoc.v:140667.3-140668.51" + wire $0\mul_op__write_cr0[0:0] + attribute \src "libresoc.v:140775.3-140787.6" + wire width 2 $0\muxid$next[1:0]$7325 + attribute \src "libresoc.v:140675.3-140676.27" + wire width 2 $0\muxid[1:0] + attribute \src "libresoc.v:140863.3-140875.6" + wire $0\neg_res$next[0:0]$7368 + attribute \src "libresoc.v:140876.3-140888.6" + wire $0\neg_res32$next[0:0]$7371 + attribute \src "libresoc.v:140641.3-140642.35" + wire $0\neg_res32[0:0] + attribute \src "libresoc.v:140643.3-140644.31" + wire $0\neg_res[0:0] + attribute \src "libresoc.v:140757.3-140774.6" + wire $0\r_busy$next[0:0]$7321 + attribute \src "libresoc.v:140677.3-140678.29" + wire $0\r_busy[0:0] + attribute \src "libresoc.v:140824.3-140836.6" + wire width 64 $0\ra$next[63:0]$7359 + attribute \src "libresoc.v:140649.3-140650.21" + wire width 64 $0\ra[63:0] + attribute \src "libresoc.v:140837.3-140849.6" + wire width 64 $0\rb$next[63:0]$7362 + attribute \src "libresoc.v:140647.3-140648.21" + wire width 64 $0\rb[63:0] + attribute \src "libresoc.v:140850.3-140862.6" + wire $0\xer_so$next[0:0]$7365 + attribute \src "libresoc.v:140645.3-140646.29" + wire $0\xer_so[0:0] + attribute \src "libresoc.v:140788.3-140823.6" + wire width 12 $1\mul_op__fn_unit$next[11:0]$7340 + attribute \src "libresoc.v:140218.14-140218.39" + wire width 12 $1\mul_op__fn_unit[11:0] + attribute \src "libresoc.v:140788.3-140823.6" + wire width 64 $1\mul_op__imm_data__data$next[63:0]$7341 + attribute \src "libresoc.v:140253.14-140253.59" + wire width 64 $1\mul_op__imm_data__data[63:0] + attribute \src "libresoc.v:140788.3-140823.6" + wire $1\mul_op__imm_data__ok$next[0:0]$7342 + attribute \src "libresoc.v:140262.7-140262.34" + wire $1\mul_op__imm_data__ok[0:0] + attribute \src "libresoc.v:140788.3-140823.6" + wire width 32 $1\mul_op__insn$next[31:0]$7343 + attribute \src "libresoc.v:140271.14-140271.34" + wire width 32 $1\mul_op__insn[31:0] + attribute \src "libresoc.v:140788.3-140823.6" + wire width 7 $1\mul_op__insn_type$next[6:0]$7344 + attribute \src "libresoc.v:140354.13-140354.38" + wire width 7 $1\mul_op__insn_type[6:0] + attribute \src "libresoc.v:140788.3-140823.6" + wire $1\mul_op__is_32bit$next[0:0]$7345 + attribute \src "libresoc.v:140511.7-140511.30" + wire $1\mul_op__is_32bit[0:0] + attribute \src "libresoc.v:140788.3-140823.6" + wire $1\mul_op__is_signed$next[0:0]$7346 + attribute \src "libresoc.v:140520.7-140520.31" + wire $1\mul_op__is_signed[0:0] + attribute \src "libresoc.v:140788.3-140823.6" + wire $1\mul_op__oe__oe$next[0:0]$7347 + attribute \src "libresoc.v:140529.7-140529.28" + wire $1\mul_op__oe__oe[0:0] + attribute \src "libresoc.v:140788.3-140823.6" + wire $1\mul_op__oe__ok$next[0:0]$7348 + attribute \src "libresoc.v:140538.7-140538.28" + wire $1\mul_op__oe__ok[0:0] + attribute \src "libresoc.v:140788.3-140823.6" + wire $1\mul_op__rc__ok$next[0:0]$7349 + attribute \src "libresoc.v:140547.7-140547.28" + wire $1\mul_op__rc__ok[0:0] + attribute \src "libresoc.v:140788.3-140823.6" + wire $1\mul_op__rc__rc$next[0:0]$7350 + attribute \src "libresoc.v:140556.7-140556.28" + wire $1\mul_op__rc__rc[0:0] + attribute \src "libresoc.v:140788.3-140823.6" + wire $1\mul_op__write_cr0$next[0:0]$7351 + attribute \src "libresoc.v:140565.7-140565.31" + wire $1\mul_op__write_cr0[0:0] + attribute \src "libresoc.v:140775.3-140787.6" + wire width 2 $1\muxid$next[1:0]$7326 + attribute \src "libresoc.v:140574.13-140574.25" + wire width 2 $1\muxid[1:0] + attribute \src "libresoc.v:140863.3-140875.6" + wire $1\neg_res$next[0:0]$7369 + attribute \src "libresoc.v:140876.3-140888.6" + wire $1\neg_res32$next[0:0]$7372 + attribute \src "libresoc.v:140596.7-140596.23" + wire $1\neg_res32[0:0] + attribute \src "libresoc.v:140589.7-140589.21" + wire $1\neg_res[0:0] + attribute \src "libresoc.v:140757.3-140774.6" + wire $1\r_busy$next[0:0]$7322 + attribute \src "libresoc.v:140610.7-140610.20" + wire $1\r_busy[0:0] + attribute \src "libresoc.v:140824.3-140836.6" + wire width 64 $1\ra$next[63:0]$7360 + attribute \src "libresoc.v:140615.14-140615.39" + wire width 64 $1\ra[63:0] + attribute \src "libresoc.v:140837.3-140849.6" + wire width 64 $1\rb$next[63:0]$7363 + attribute \src "libresoc.v:140624.14-140624.39" + wire width 64 $1\rb[63:0] + attribute \src "libresoc.v:140850.3-140862.6" + wire $1\xer_so$next[0:0]$7366 + attribute \src "libresoc.v:140633.7-140633.20" + wire $1\xer_so[0:0] + attribute \src "libresoc.v:140788.3-140823.6" + wire width 64 $2\mul_op__imm_data__data$next[63:0]$7352 + attribute \src "libresoc.v:140788.3-140823.6" + wire $2\mul_op__imm_data__ok$next[0:0]$7353 + attribute \src "libresoc.v:140788.3-140823.6" + wire $2\mul_op__oe__oe$next[0:0]$7354 + attribute \src "libresoc.v:140788.3-140823.6" + wire $2\mul_op__oe__ok$next[0:0]$7355 + attribute \src "libresoc.v:140788.3-140823.6" + wire $2\mul_op__rc__ok$next[0:0]$7356 + attribute \src "libresoc.v:140788.3-140823.6" + wire $2\mul_op__rc__rc$next[0:0]$7357 + attribute \src "libresoc.v:140757.3-140774.6" + wire $2\r_busy$next[0:0]$7323 + attribute \src "libresoc.v:140640.18-140640.118" + wire $and$libresoc.v:140640$7300_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + wire \$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 40 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 1 \coresync_rst + attribute \src "libresoc.v:139716.7-139716.15" + wire \initial + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \input_mul_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \input_mul_op__fn_unit$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \input_mul_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \input_mul_op__imm_data__data$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_mul_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_mul_op__imm_data__ok$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \input_mul_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \input_mul_op__insn$29 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \input_mul_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \input_mul_op__insn_type$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_mul_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_mul_op__is_32bit$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_mul_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_mul_op__is_signed$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_mul_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_mul_op__oe__oe$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_mul_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_mul_op__oe__ok$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_mul_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_mul_op__rc__ok$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_mul_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_mul_op__rc__rc$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_mul_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_mul_op__write_cr0$26 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \input_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \input_muxid$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_ra$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_rb$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \input_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \input_xer_so$32 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \mul1_mul_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \mul1_mul_op__fn_unit$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \mul1_mul_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \mul1_mul_op__imm_data__data$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul1_mul_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul1_mul_op__imm_data__ok$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \mul1_mul_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \mul1_mul_op__insn$45 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \mul1_mul_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \mul1_mul_op__insn_type$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul1_mul_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul1_mul_op__is_32bit$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul1_mul_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul1_mul_op__is_signed$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul1_mul_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul1_mul_op__oe__oe$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul1_mul_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul1_mul_op__oe__ok$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul1_mul_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul1_mul_op__rc__ok$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul1_mul_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul1_mul_op__rc__rc$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul1_mul_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul1_mul_op__write_cr0$42 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \mul1_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \mul1_muxid$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" + wire \mul1_neg_res + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" + wire \mul1_neg_res32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \mul1_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \mul1_ra$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \mul1_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \mul1_rb$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \mul1_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \mul1_xer_so$48 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 output 6 \mul_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 26 \mul_op__fn_unit$3 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \mul_op__fn_unit$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \mul_op__fn_unit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 7 \mul_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 27 \mul_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \mul_op__imm_data__data$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \mul_op__imm_data__data$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 8 \mul_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 28 \mul_op__imm_data__ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__imm_data__ok$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__imm_data__ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 16 \mul_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 36 \mul_op__insn$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \mul_op__insn$64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \mul_op__insn$next + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 5 \mul_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 25 \mul_op__insn_type$2 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \mul_op__insn_type$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \mul_op__insn_type$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 14 \mul_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 34 \mul_op__is_32bit$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__is_32bit$62 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__is_32bit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 15 \mul_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 35 \mul_op__is_signed$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__is_signed$63 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__is_signed$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 11 \mul_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__oe__oe$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 31 \mul_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__oe__oe$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 12 \mul_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__oe__ok$60 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 32 \mul_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__oe__ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 10 \mul_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__rc__ok$58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 30 \mul_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__rc__ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 9 \mul_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__rc__rc$57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 29 \mul_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__rc__rc$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 13 \mul_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 33 \mul_op__write_cr0$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__write_cr0$61 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__write_cr0$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 4 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 24 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$52 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" + wire \n_i_rdy_data + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire input 3 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire output 2 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" + wire output 20 \neg_res + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" + wire \neg_res$68 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" + wire \neg_res$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" + wire output 21 \neg_res32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" + wire \neg_res32$69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" + wire \neg_res32$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire output 23 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire input 22 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" + wire \p_valid_i$49 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire \r_busy$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 17 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 37 \ra$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \ra$65 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \ra$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 18 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 38 \rb$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \rb$66 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \rb$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire output 19 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 39 \xer_so$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \xer_so$67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \xer_so$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + cell $and $and$libresoc.v:140640$7300 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i$49 + connect \B \p_ready_o + connect \Y $and$libresoc.v:140640$7300_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:140679.14-140712.4" + cell \input$92 \input + connect \mul_op__fn_unit \input_mul_op__fn_unit + connect \mul_op__fn_unit$3 \input_mul_op__fn_unit$19 + connect \mul_op__imm_data__data \input_mul_op__imm_data__data + connect \mul_op__imm_data__data$4 \input_mul_op__imm_data__data$20 + connect \mul_op__imm_data__ok \input_mul_op__imm_data__ok + connect \mul_op__imm_data__ok$5 \input_mul_op__imm_data__ok$21 + connect \mul_op__insn \input_mul_op__insn + connect \mul_op__insn$13 \input_mul_op__insn$29 + connect \mul_op__insn_type \input_mul_op__insn_type + connect \mul_op__insn_type$2 \input_mul_op__insn_type$18 + connect \mul_op__is_32bit \input_mul_op__is_32bit + connect \mul_op__is_32bit$11 \input_mul_op__is_32bit$27 + connect \mul_op__is_signed \input_mul_op__is_signed + connect \mul_op__is_signed$12 \input_mul_op__is_signed$28 + connect \mul_op__oe__oe \input_mul_op__oe__oe + connect \mul_op__oe__oe$8 \input_mul_op__oe__oe$24 + connect \mul_op__oe__ok \input_mul_op__oe__ok + connect \mul_op__oe__ok$9 \input_mul_op__oe__ok$25 + connect \mul_op__rc__ok \input_mul_op__rc__ok + connect \mul_op__rc__ok$7 \input_mul_op__rc__ok$23 + connect \mul_op__rc__rc \input_mul_op__rc__rc + connect \mul_op__rc__rc$6 \input_mul_op__rc__rc$22 + connect \mul_op__write_cr0 \input_mul_op__write_cr0 + connect \mul_op__write_cr0$10 \input_mul_op__write_cr0$26 + connect \muxid \input_muxid + connect \muxid$1 \input_muxid$17 + connect \ra \input_ra + connect \ra$14 \input_ra$30 + connect \rb \input_rb + connect \rb$15 \input_rb$31 + connect \xer_so \input_xer_so + connect \xer_so$16 \input_xer_so$32 + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:140713.8-140748.4" + cell \mul1 \mul1 + connect \mul_op__fn_unit \mul1_mul_op__fn_unit + connect \mul_op__fn_unit$3 \mul1_mul_op__fn_unit$35 + connect \mul_op__imm_data__data \mul1_mul_op__imm_data__data + connect \mul_op__imm_data__data$4 \mul1_mul_op__imm_data__data$36 + connect \mul_op__imm_data__ok \mul1_mul_op__imm_data__ok + connect \mul_op__imm_data__ok$5 \mul1_mul_op__imm_data__ok$37 + connect \mul_op__insn \mul1_mul_op__insn + connect \mul_op__insn$13 \mul1_mul_op__insn$45 + connect \mul_op__insn_type \mul1_mul_op__insn_type + connect \mul_op__insn_type$2 \mul1_mul_op__insn_type$34 + connect \mul_op__is_32bit \mul1_mul_op__is_32bit + connect \mul_op__is_32bit$11 \mul1_mul_op__is_32bit$43 + connect \mul_op__is_signed \mul1_mul_op__is_signed + connect \mul_op__is_signed$12 \mul1_mul_op__is_signed$44 + connect \mul_op__oe__oe \mul1_mul_op__oe__oe + connect \mul_op__oe__oe$8 \mul1_mul_op__oe__oe$40 + connect \mul_op__oe__ok \mul1_mul_op__oe__ok + connect \mul_op__oe__ok$9 \mul1_mul_op__oe__ok$41 + connect \mul_op__rc__ok \mul1_mul_op__rc__ok + connect \mul_op__rc__ok$7 \mul1_mul_op__rc__ok$39 + connect \mul_op__rc__rc \mul1_mul_op__rc__rc + connect \mul_op__rc__rc$6 \mul1_mul_op__rc__rc$38 + connect \mul_op__write_cr0 \mul1_mul_op__write_cr0 + connect \mul_op__write_cr0$10 \mul1_mul_op__write_cr0$42 + connect \muxid \mul1_muxid + connect \muxid$1 \mul1_muxid$33 + connect \neg_res \mul1_neg_res + connect \neg_res32 \mul1_neg_res32 + connect \ra \mul1_ra + connect \ra$14 \mul1_ra$46 + connect \rb \mul1_rb + connect \rb$15 \mul1_rb$47 + connect \xer_so \mul1_xer_so + connect \xer_so$16 \mul1_xer_so$48 + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:140749.10-140752.4" + cell \n$91 \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:140753.10-140756.4" + cell \p$90 \p + connect \p_ready_o \p_ready_o + connect \p_valid_i \p_valid_i + end + attribute \src "libresoc.v:139716.7-139716.20" + process $proc$libresoc.v:139716$7373 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:140218.14-140218.39" + process $proc$libresoc.v:140218$7374 + assign { } { } + assign $1\mul_op__fn_unit[11:0] 12'000000000000 + sync always + sync init + update \mul_op__fn_unit $1\mul_op__fn_unit[11:0] + end + attribute \src "libresoc.v:140253.14-140253.59" + process $proc$libresoc.v:140253$7375 + assign { } { } + assign $1\mul_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \mul_op__imm_data__data $1\mul_op__imm_data__data[63:0] + end + attribute \src "libresoc.v:140262.7-140262.34" + process $proc$libresoc.v:140262$7376 + assign { } { } + assign $1\mul_op__imm_data__ok[0:0] 1'0 + sync always + sync init + update \mul_op__imm_data__ok $1\mul_op__imm_data__ok[0:0] + end + attribute \src "libresoc.v:140271.14-140271.34" + process $proc$libresoc.v:140271$7377 + assign { } { } + assign $1\mul_op__insn[31:0] 0 + sync always + sync init + update \mul_op__insn $1\mul_op__insn[31:0] + end + attribute \src "libresoc.v:140354.13-140354.38" + process $proc$libresoc.v:140354$7378 + assign { } { } + assign $1\mul_op__insn_type[6:0] 7'0000000 + sync always + sync init + update \mul_op__insn_type $1\mul_op__insn_type[6:0] + end + attribute \src "libresoc.v:140511.7-140511.30" + process $proc$libresoc.v:140511$7379 + assign { } { } + assign $1\mul_op__is_32bit[0:0] 1'0 + sync always + sync init + update \mul_op__is_32bit $1\mul_op__is_32bit[0:0] + end + attribute \src "libresoc.v:140520.7-140520.31" + process $proc$libresoc.v:140520$7380 + assign { } { } + assign $1\mul_op__is_signed[0:0] 1'0 + sync always + sync init + update \mul_op__is_signed $1\mul_op__is_signed[0:0] + end + attribute \src "libresoc.v:140529.7-140529.28" + process $proc$libresoc.v:140529$7381 + assign { } { } + assign $1\mul_op__oe__oe[0:0] 1'0 + sync always + sync init + update \mul_op__oe__oe $1\mul_op__oe__oe[0:0] + end + attribute \src "libresoc.v:140538.7-140538.28" + process $proc$libresoc.v:140538$7382 + assign { } { } + assign $1\mul_op__oe__ok[0:0] 1'0 + sync always + sync init + update \mul_op__oe__ok $1\mul_op__oe__ok[0:0] + end + attribute \src "libresoc.v:140547.7-140547.28" + process $proc$libresoc.v:140547$7383 + assign { } { } + assign $1\mul_op__rc__ok[0:0] 1'0 + sync always + sync init + update \mul_op__rc__ok $1\mul_op__rc__ok[0:0] + end + attribute \src "libresoc.v:140556.7-140556.28" + process $proc$libresoc.v:140556$7384 + assign { } { } + assign $1\mul_op__rc__rc[0:0] 1'0 + sync always + sync init + update \mul_op__rc__rc $1\mul_op__rc__rc[0:0] + end + attribute \src "libresoc.v:140565.7-140565.31" + process $proc$libresoc.v:140565$7385 + assign { } { } + assign $1\mul_op__write_cr0[0:0] 1'0 + sync always + sync init + update \mul_op__write_cr0 $1\mul_op__write_cr0[0:0] + end + attribute \src "libresoc.v:140574.13-140574.25" + process $proc$libresoc.v:140574$7386 + assign { } { } + assign $1\muxid[1:0] 2'00 + sync always + sync init + update \muxid $1\muxid[1:0] + end + attribute \src "libresoc.v:140589.7-140589.21" + process $proc$libresoc.v:140589$7387 + assign { } { } + assign $1\neg_res[0:0] 1'0 + sync always + sync init + update \neg_res $1\neg_res[0:0] + end + attribute \src "libresoc.v:140596.7-140596.23" + process $proc$libresoc.v:140596$7388 + assign { } { } + assign $1\neg_res32[0:0] 1'0 + sync always + sync init + update \neg_res32 $1\neg_res32[0:0] + end + attribute \src "libresoc.v:140610.7-140610.20" + process $proc$libresoc.v:140610$7389 + assign { } { } + assign $1\r_busy[0:0] 1'0 + sync always + sync init + update \r_busy $1\r_busy[0:0] + end + attribute \src "libresoc.v:140615.14-140615.39" + process $proc$libresoc.v:140615$7390 + assign { } { } + assign $1\ra[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \ra $1\ra[63:0] + end + attribute \src "libresoc.v:140624.14-140624.39" + process $proc$libresoc.v:140624$7391 + assign { } { } + assign $1\rb[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \rb $1\rb[63:0] + end + attribute \src "libresoc.v:140633.7-140633.20" + process $proc$libresoc.v:140633$7392 + assign { } { } + assign $1\xer_so[0:0] 1'0 + sync always + sync init + update \xer_so $1\xer_so[0:0] + end + attribute \src "libresoc.v:140641.3-140642.35" + process $proc$libresoc.v:140641$7301 + assign { } { } + assign $0\neg_res32[0:0] \neg_res32$next + sync posedge \coresync_clk + update \neg_res32 $0\neg_res32[0:0] + end + attribute \src "libresoc.v:140643.3-140644.31" + process $proc$libresoc.v:140643$7302 + assign { } { } + assign $0\neg_res[0:0] \neg_res$next + sync posedge \coresync_clk + update \neg_res $0\neg_res[0:0] + end + attribute \src "libresoc.v:140645.3-140646.29" + process $proc$libresoc.v:140645$7303 + assign { } { } + assign $0\xer_so[0:0] \xer_so$next + sync posedge \coresync_clk + update \xer_so $0\xer_so[0:0] + end + attribute \src "libresoc.v:140647.3-140648.21" + process $proc$libresoc.v:140647$7304 + assign { } { } + assign $0\rb[63:0] \rb$next + sync posedge \coresync_clk + update \rb $0\rb[63:0] + end + attribute \src "libresoc.v:140649.3-140650.21" + process $proc$libresoc.v:140649$7305 + assign { } { } + assign $0\ra[63:0] \ra$next + sync posedge \coresync_clk + update \ra $0\ra[63:0] + end + attribute \src "libresoc.v:140651.3-140652.51" + process $proc$libresoc.v:140651$7306 + assign { } { } + assign $0\mul_op__insn_type[6:0] \mul_op__insn_type$next + sync posedge \coresync_clk + update \mul_op__insn_type $0\mul_op__insn_type[6:0] + end + attribute \src "libresoc.v:140653.3-140654.47" + process $proc$libresoc.v:140653$7307 + assign { } { } + assign $0\mul_op__fn_unit[11:0] \mul_op__fn_unit$next + sync posedge \coresync_clk + update \mul_op__fn_unit $0\mul_op__fn_unit[11:0] + end + attribute \src "libresoc.v:140655.3-140656.61" + process $proc$libresoc.v:140655$7308 + assign { } { } + assign $0\mul_op__imm_data__data[63:0] \mul_op__imm_data__data$next + sync posedge \coresync_clk + update \mul_op__imm_data__data $0\mul_op__imm_data__data[63:0] + end + attribute \src "libresoc.v:140657.3-140658.57" + process $proc$libresoc.v:140657$7309 + assign { } { } + assign $0\mul_op__imm_data__ok[0:0] \mul_op__imm_data__ok$next + sync posedge \coresync_clk + update \mul_op__imm_data__ok $0\mul_op__imm_data__ok[0:0] + end + attribute \src "libresoc.v:140659.3-140660.45" + process $proc$libresoc.v:140659$7310 + assign { } { } + assign $0\mul_op__rc__rc[0:0] \mul_op__rc__rc$next + sync posedge \coresync_clk + update \mul_op__rc__rc $0\mul_op__rc__rc[0:0] + end + attribute \src "libresoc.v:140661.3-140662.45" + process $proc$libresoc.v:140661$7311 + assign { } { } + assign $0\mul_op__rc__ok[0:0] \mul_op__rc__ok$next + sync posedge \coresync_clk + update \mul_op__rc__ok $0\mul_op__rc__ok[0:0] + end + attribute \src "libresoc.v:140663.3-140664.45" + process $proc$libresoc.v:140663$7312 + assign { } { } + assign $0\mul_op__oe__oe[0:0] \mul_op__oe__oe$next + sync posedge \coresync_clk + update \mul_op__oe__oe $0\mul_op__oe__oe[0:0] + end + attribute \src "libresoc.v:140665.3-140666.45" + process $proc$libresoc.v:140665$7313 + assign { } { } + assign $0\mul_op__oe__ok[0:0] \mul_op__oe__ok$next + sync posedge \coresync_clk + update \mul_op__oe__ok $0\mul_op__oe__ok[0:0] + end + attribute \src "libresoc.v:140667.3-140668.51" + process $proc$libresoc.v:140667$7314 + assign { } { } + assign $0\mul_op__write_cr0[0:0] \mul_op__write_cr0$next + sync posedge \coresync_clk + update \mul_op__write_cr0 $0\mul_op__write_cr0[0:0] + end + attribute \src "libresoc.v:140669.3-140670.49" + process $proc$libresoc.v:140669$7315 + assign { } { } + assign $0\mul_op__is_32bit[0:0] \mul_op__is_32bit$next + sync posedge \coresync_clk + update \mul_op__is_32bit $0\mul_op__is_32bit[0:0] + end + attribute \src "libresoc.v:140671.3-140672.51" + process $proc$libresoc.v:140671$7316 + assign { } { } + assign $0\mul_op__is_signed[0:0] \mul_op__is_signed$next + sync posedge \coresync_clk + update \mul_op__is_signed $0\mul_op__is_signed[0:0] + end + attribute \src "libresoc.v:140673.3-140674.41" + process $proc$libresoc.v:140673$7317 + assign { } { } + assign $0\mul_op__insn[31:0] \mul_op__insn$next + sync posedge \coresync_clk + update \mul_op__insn $0\mul_op__insn[31:0] + end + attribute \src "libresoc.v:140675.3-140676.27" + process $proc$libresoc.v:140675$7318 + assign { } { } + assign $0\muxid[1:0] \muxid$next + sync posedge \coresync_clk + update \muxid $0\muxid[1:0] + end + attribute \src "libresoc.v:140677.3-140678.29" + process $proc$libresoc.v:140677$7319 + assign { } { } + assign $0\r_busy[0:0] \r_busy$next + sync posedge \coresync_clk + update \r_busy $0\r_busy[0:0] + end + attribute \src "libresoc.v:140757.3-140774.6" + process $proc$libresoc.v:140757$7320 + assign { } { } + assign { } { } + assign { } { } + assign $0\r_busy$next[0:0]$7321 $2\r_busy$next[0:0]$7323 + attribute \src "libresoc.v:140758.5-140758.29" + switch \initial + attribute \src "libresoc.v:140758.9-140758.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\r_busy$next[0:0]$7322 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\r_busy$next[0:0]$7322 1'0 + case + assign $1\r_busy$next[0:0]$7322 \r_busy + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r_busy$next[0:0]$7323 1'0 + case + assign $2\r_busy$next[0:0]$7323 $1\r_busy$next[0:0]$7322 + end + sync always + update \r_busy$next $0\r_busy$next[0:0]$7321 + end + attribute \src "libresoc.v:140775.3-140787.6" + process $proc$libresoc.v:140775$7324 + assign { } { } + assign { } { } + assign $0\muxid$next[1:0]$7325 $1\muxid$next[1:0]$7326 + attribute \src "libresoc.v:140776.5-140776.29" + switch \initial + attribute \src "libresoc.v:140776.9-140776.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\muxid$next[1:0]$7326 \muxid$52 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\muxid$next[1:0]$7326 \muxid$52 + case + assign $1\muxid$next[1:0]$7326 \muxid + end + sync always + update \muxid$next $0\muxid$next[1:0]$7325 + end + attribute \src "libresoc.v:140788.3-140823.6" + process $proc$libresoc.v:140788$7327 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\mul_op__fn_unit$next[11:0]$7328 $1\mul_op__fn_unit$next[11:0]$7340 + assign { } { } + assign { } { } + assign $0\mul_op__insn$next[31:0]$7331 $1\mul_op__insn$next[31:0]$7343 + assign $0\mul_op__insn_type$next[6:0]$7332 $1\mul_op__insn_type$next[6:0]$7344 + assign $0\mul_op__is_32bit$next[0:0]$7333 $1\mul_op__is_32bit$next[0:0]$7345 + assign $0\mul_op__is_signed$next[0:0]$7334 $1\mul_op__is_signed$next[0:0]$7346 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\mul_op__write_cr0$next[0:0]$7339 $1\mul_op__write_cr0$next[0:0]$7351 + assign $0\mul_op__imm_data__data$next[63:0]$7329 $2\mul_op__imm_data__data$next[63:0]$7352 + assign $0\mul_op__imm_data__ok$next[0:0]$7330 $2\mul_op__imm_data__ok$next[0:0]$7353 + assign $0\mul_op__oe__oe$next[0:0]$7335 $2\mul_op__oe__oe$next[0:0]$7354 + assign $0\mul_op__oe__ok$next[0:0]$7336 $2\mul_op__oe__ok$next[0:0]$7355 + assign $0\mul_op__rc__ok$next[0:0]$7337 $2\mul_op__rc__ok$next[0:0]$7356 + assign $0\mul_op__rc__rc$next[0:0]$7338 $2\mul_op__rc__rc$next[0:0]$7357 + attribute \src "libresoc.v:140789.5-140789.29" + switch \initial + attribute \src "libresoc.v:140789.9-140789.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\mul_op__insn$next[31:0]$7343 $1\mul_op__is_signed$next[0:0]$7346 $1\mul_op__is_32bit$next[0:0]$7345 $1\mul_op__write_cr0$next[0:0]$7351 $1\mul_op__oe__ok$next[0:0]$7348 $1\mul_op__oe__oe$next[0:0]$7347 $1\mul_op__rc__ok$next[0:0]$7349 $1\mul_op__rc__rc$next[0:0]$7350 $1\mul_op__imm_data__ok$next[0:0]$7342 $1\mul_op__imm_data__data$next[63:0]$7341 $1\mul_op__fn_unit$next[11:0]$7340 $1\mul_op__insn_type$next[6:0]$7344 } { \mul_op__insn$64 \mul_op__is_signed$63 \mul_op__is_32bit$62 \mul_op__write_cr0$61 \mul_op__oe__ok$60 \mul_op__oe__oe$59 \mul_op__rc__ok$58 \mul_op__rc__rc$57 \mul_op__imm_data__ok$56 \mul_op__imm_data__data$55 \mul_op__fn_unit$54 \mul_op__insn_type$53 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\mul_op__insn$next[31:0]$7343 $1\mul_op__is_signed$next[0:0]$7346 $1\mul_op__is_32bit$next[0:0]$7345 $1\mul_op__write_cr0$next[0:0]$7351 $1\mul_op__oe__ok$next[0:0]$7348 $1\mul_op__oe__oe$next[0:0]$7347 $1\mul_op__rc__ok$next[0:0]$7349 $1\mul_op__rc__rc$next[0:0]$7350 $1\mul_op__imm_data__ok$next[0:0]$7342 $1\mul_op__imm_data__data$next[63:0]$7341 $1\mul_op__fn_unit$next[11:0]$7340 $1\mul_op__insn_type$next[6:0]$7344 } { \mul_op__insn$64 \mul_op__is_signed$63 \mul_op__is_32bit$62 \mul_op__write_cr0$61 \mul_op__oe__ok$60 \mul_op__oe__oe$59 \mul_op__rc__ok$58 \mul_op__rc__rc$57 \mul_op__imm_data__ok$56 \mul_op__imm_data__data$55 \mul_op__fn_unit$54 \mul_op__insn_type$53 } + case + assign $1\mul_op__fn_unit$next[11:0]$7340 \mul_op__fn_unit + assign $1\mul_op__imm_data__data$next[63:0]$7341 \mul_op__imm_data__data + assign $1\mul_op__imm_data__ok$next[0:0]$7342 \mul_op__imm_data__ok + assign $1\mul_op__insn$next[31:0]$7343 \mul_op__insn + assign $1\mul_op__insn_type$next[6:0]$7344 \mul_op__insn_type + assign $1\mul_op__is_32bit$next[0:0]$7345 \mul_op__is_32bit + assign $1\mul_op__is_signed$next[0:0]$7346 \mul_op__is_signed + assign $1\mul_op__oe__oe$next[0:0]$7347 \mul_op__oe__oe + assign $1\mul_op__oe__ok$next[0:0]$7348 \mul_op__oe__ok + assign $1\mul_op__rc__ok$next[0:0]$7349 \mul_op__rc__ok + assign $1\mul_op__rc__rc$next[0:0]$7350 \mul_op__rc__rc + assign $1\mul_op__write_cr0$next[0:0]$7351 \mul_op__write_cr0 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $2\mul_op__imm_data__data$next[63:0]$7352 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\mul_op__imm_data__ok$next[0:0]$7353 1'0 + assign $2\mul_op__rc__rc$next[0:0]$7357 1'0 + assign $2\mul_op__rc__ok$next[0:0]$7356 1'0 + assign $2\mul_op__oe__oe$next[0:0]$7354 1'0 + assign $2\mul_op__oe__ok$next[0:0]$7355 1'0 + case + assign $2\mul_op__imm_data__data$next[63:0]$7352 $1\mul_op__imm_data__data$next[63:0]$7341 + assign $2\mul_op__imm_data__ok$next[0:0]$7353 $1\mul_op__imm_data__ok$next[0:0]$7342 + assign $2\mul_op__oe__oe$next[0:0]$7354 $1\mul_op__oe__oe$next[0:0]$7347 + assign $2\mul_op__oe__ok$next[0:0]$7355 $1\mul_op__oe__ok$next[0:0]$7348 + assign $2\mul_op__rc__ok$next[0:0]$7356 $1\mul_op__rc__ok$next[0:0]$7349 + assign $2\mul_op__rc__rc$next[0:0]$7357 $1\mul_op__rc__rc$next[0:0]$7350 + end + sync always + update \mul_op__fn_unit$next $0\mul_op__fn_unit$next[11:0]$7328 + update \mul_op__imm_data__data$next $0\mul_op__imm_data__data$next[63:0]$7329 + update \mul_op__imm_data__ok$next $0\mul_op__imm_data__ok$next[0:0]$7330 + update \mul_op__insn$next $0\mul_op__insn$next[31:0]$7331 + update \mul_op__insn_type$next $0\mul_op__insn_type$next[6:0]$7332 + update \mul_op__is_32bit$next $0\mul_op__is_32bit$next[0:0]$7333 + update \mul_op__is_signed$next $0\mul_op__is_signed$next[0:0]$7334 + update \mul_op__oe__oe$next $0\mul_op__oe__oe$next[0:0]$7335 + update \mul_op__oe__ok$next $0\mul_op__oe__ok$next[0:0]$7336 + update \mul_op__rc__ok$next $0\mul_op__rc__ok$next[0:0]$7337 + update \mul_op__rc__rc$next $0\mul_op__rc__rc$next[0:0]$7338 + update \mul_op__write_cr0$next $0\mul_op__write_cr0$next[0:0]$7339 + end + attribute \src "libresoc.v:140824.3-140836.6" + process $proc$libresoc.v:140824$7358 + assign { } { } + assign { } { } + assign $0\ra$next[63:0]$7359 $1\ra$next[63:0]$7360 + attribute \src "libresoc.v:140825.5-140825.29" + switch \initial + attribute \src "libresoc.v:140825.9-140825.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\ra$next[63:0]$7360 \ra$65 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\ra$next[63:0]$7360 \ra$65 + case + assign $1\ra$next[63:0]$7360 \ra + end + sync always + update \ra$next $0\ra$next[63:0]$7359 + end + attribute \src "libresoc.v:140837.3-140849.6" + process $proc$libresoc.v:140837$7361 + assign { } { } + assign { } { } + assign $0\rb$next[63:0]$7362 $1\rb$next[63:0]$7363 + attribute \src "libresoc.v:140838.5-140838.29" + switch \initial + attribute \src "libresoc.v:140838.9-140838.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\rb$next[63:0]$7363 \rb$66 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\rb$next[63:0]$7363 \rb$66 + case + assign $1\rb$next[63:0]$7363 \rb + end + sync always + update \rb$next $0\rb$next[63:0]$7362 + end + attribute \src "libresoc.v:140850.3-140862.6" + process $proc$libresoc.v:140850$7364 + assign { } { } + assign { } { } + assign $0\xer_so$next[0:0]$7365 $1\xer_so$next[0:0]$7366 + attribute \src "libresoc.v:140851.5-140851.29" + switch \initial + attribute \src "libresoc.v:140851.9-140851.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\xer_so$next[0:0]$7366 \xer_so$67 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\xer_so$next[0:0]$7366 \xer_so$67 + case + assign $1\xer_so$next[0:0]$7366 \xer_so + end + sync always + update \xer_so$next $0\xer_so$next[0:0]$7365 + end + attribute \src "libresoc.v:140863.3-140875.6" + process $proc$libresoc.v:140863$7367 + assign { } { } + assign { } { } + assign $0\neg_res$next[0:0]$7368 $1\neg_res$next[0:0]$7369 + attribute \src "libresoc.v:140864.5-140864.29" + switch \initial + attribute \src "libresoc.v:140864.9-140864.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\neg_res$next[0:0]$7369 \neg_res$68 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\neg_res$next[0:0]$7369 \neg_res$68 + case + assign $1\neg_res$next[0:0]$7369 \neg_res + end + sync always + update \neg_res$next $0\neg_res$next[0:0]$7368 + end + attribute \src "libresoc.v:140876.3-140888.6" + process $proc$libresoc.v:140876$7370 + assign { } { } + assign { } { } + assign $0\neg_res32$next[0:0]$7371 $1\neg_res32$next[0:0]$7372 + attribute \src "libresoc.v:140877.5-140877.29" + switch \initial + attribute \src "libresoc.v:140877.9-140877.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\neg_res32$next[0:0]$7372 \neg_res32$69 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\neg_res32$next[0:0]$7372 \neg_res32$69 + case + assign $1\neg_res32$next[0:0]$7372 \neg_res32 + end + sync always + update \neg_res32$next $0\neg_res32$next[0:0]$7371 + end + connect \$50 $and$libresoc.v:140640$7300_Y + connect \p_ready_o \n_i_rdy_data + connect \n_valid_o \r_busy + connect \neg_res32$69 \mul1_neg_res32 + connect \neg_res$68 \mul1_neg_res + connect \xer_so$67 \mul1_xer_so$48 + connect \rb$66 \mul1_rb$47 + connect \ra$65 \mul1_ra$46 + connect { \mul_op__insn$64 \mul_op__is_signed$63 \mul_op__is_32bit$62 \mul_op__write_cr0$61 \mul_op__oe__ok$60 \mul_op__oe__oe$59 \mul_op__rc__ok$58 \mul_op__rc__rc$57 \mul_op__imm_data__ok$56 \mul_op__imm_data__data$55 \mul_op__fn_unit$54 \mul_op__insn_type$53 } { \mul1_mul_op__insn$45 \mul1_mul_op__is_signed$44 \mul1_mul_op__is_32bit$43 \mul1_mul_op__write_cr0$42 \mul1_mul_op__oe__ok$41 \mul1_mul_op__oe__oe$40 \mul1_mul_op__rc__ok$39 \mul1_mul_op__rc__rc$38 \mul1_mul_op__imm_data__ok$37 \mul1_mul_op__imm_data__data$36 \mul1_mul_op__fn_unit$35 \mul1_mul_op__insn_type$34 } + connect \muxid$52 \mul1_muxid$33 + connect \p_valid_i_p_ready_o \$50 + connect \n_i_rdy_data \n_ready_i + connect \p_valid_i$49 \p_valid_i + connect \mul1_xer_so \input_xer_so$32 + connect \mul1_rb \input_rb$31 + connect \mul1_ra \input_ra$30 + connect { \mul1_mul_op__insn \mul1_mul_op__is_signed \mul1_mul_op__is_32bit \mul1_mul_op__write_cr0 \mul1_mul_op__oe__ok \mul1_mul_op__oe__oe \mul1_mul_op__rc__ok \mul1_mul_op__rc__rc \mul1_mul_op__imm_data__ok \mul1_mul_op__imm_data__data \mul1_mul_op__fn_unit \mul1_mul_op__insn_type } { \input_mul_op__insn$29 \input_mul_op__is_signed$28 \input_mul_op__is_32bit$27 \input_mul_op__write_cr0$26 \input_mul_op__oe__ok$25 \input_mul_op__oe__oe$24 \input_mul_op__rc__ok$23 \input_mul_op__rc__rc$22 \input_mul_op__imm_data__ok$21 \input_mul_op__imm_data__data$20 \input_mul_op__fn_unit$19 \input_mul_op__insn_type$18 } + connect \mul1_muxid \input_muxid$17 + connect \input_xer_so \xer_so$16 + connect \input_rb \rb$15 + connect \input_ra \ra$14 + connect { \input_mul_op__insn \input_mul_op__is_signed \input_mul_op__is_32bit \input_mul_op__write_cr0 \input_mul_op__oe__ok \input_mul_op__oe__oe \input_mul_op__rc__ok \input_mul_op__rc__rc \input_mul_op__imm_data__ok \input_mul_op__imm_data__data \input_mul_op__fn_unit \input_mul_op__insn_type } { \mul_op__insn$13 \mul_op__is_signed$12 \mul_op__is_32bit$11 \mul_op__write_cr0$10 \mul_op__oe__ok$9 \mul_op__oe__oe$8 \mul_op__rc__ok$7 \mul_op__rc__rc$6 \mul_op__imm_data__ok$5 \mul_op__imm_data__data$4 \mul_op__fn_unit$3 \mul_op__insn_type$2 } + connect \input_muxid \muxid$1 +end +attribute \src "libresoc.v:140915.1-141820.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe2" +attribute \generator "nMigen" +module \mul_pipe2 + attribute \src "libresoc.v:140916.7-140916.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:141714.3-141749.6" + wire width 12 $0\mul_op__fn_unit$3$next[11:0]$7436 + attribute \src "libresoc.v:141612.3-141613.53" + wire width 12 $0\mul_op__fn_unit$3[11:0]$7404 + attribute \src "libresoc.v:141197.14-141197.43" + wire width 12 $0\mul_op__fn_unit$3[11:0]$7480 + attribute \src "libresoc.v:141714.3-141749.6" + wire width 64 $0\mul_op__imm_data__data$4$next[63:0]$7437 + attribute \src "libresoc.v:141614.3-141615.67" + wire width 64 $0\mul_op__imm_data__data$4[63:0]$7406 + attribute \src "libresoc.v:141221.14-141221.63" + wire width 64 $0\mul_op__imm_data__data$4[63:0]$7482 + attribute \src "libresoc.v:141714.3-141749.6" + wire $0\mul_op__imm_data__ok$5$next[0:0]$7438 + attribute \src "libresoc.v:141616.3-141617.63" + wire $0\mul_op__imm_data__ok$5[0:0]$7408 + attribute \src "libresoc.v:141230.7-141230.38" + wire $0\mul_op__imm_data__ok$5[0:0]$7484 + attribute \src "libresoc.v:141714.3-141749.6" + wire width 32 $0\mul_op__insn$13$next[31:0]$7439 + attribute \src "libresoc.v:141632.3-141633.49" + wire width 32 $0\mul_op__insn$13[31:0]$7424 + attribute \src "libresoc.v:141237.14-141237.39" + wire width 32 $0\mul_op__insn$13[31:0]$7486 + attribute \src "libresoc.v:141714.3-141749.6" + wire width 7 $0\mul_op__insn_type$2$next[6:0]$7440 + attribute \src "libresoc.v:141610.3-141611.57" + wire width 7 $0\mul_op__insn_type$2[6:0]$7402 + attribute \src "libresoc.v:141394.13-141394.42" + wire width 7 $0\mul_op__insn_type$2[6:0]$7488 + attribute \src "libresoc.v:141714.3-141749.6" + wire $0\mul_op__is_32bit$11$next[0:0]$7441 + attribute \src "libresoc.v:141628.3-141629.57" + wire $0\mul_op__is_32bit$11[0:0]$7420 + attribute \src "libresoc.v:141477.7-141477.35" + wire $0\mul_op__is_32bit$11[0:0]$7490 + attribute \src "libresoc.v:141714.3-141749.6" + wire $0\mul_op__is_signed$12$next[0:0]$7442 + attribute \src "libresoc.v:141630.3-141631.59" + wire $0\mul_op__is_signed$12[0:0]$7422 + attribute \src "libresoc.v:141486.7-141486.36" + wire $0\mul_op__is_signed$12[0:0]$7492 + attribute \src "libresoc.v:141714.3-141749.6" + wire $0\mul_op__oe__oe$8$next[0:0]$7443 + attribute \src "libresoc.v:141622.3-141623.51" + wire $0\mul_op__oe__oe$8[0:0]$7414 + attribute \src "libresoc.v:141497.7-141497.32" + wire $0\mul_op__oe__oe$8[0:0]$7494 + attribute \src "libresoc.v:141714.3-141749.6" + wire $0\mul_op__oe__ok$9$next[0:0]$7444 + attribute \src "libresoc.v:141624.3-141625.51" + wire $0\mul_op__oe__ok$9[0:0]$7416 + attribute \src "libresoc.v:141506.7-141506.32" + wire $0\mul_op__oe__ok$9[0:0]$7496 + attribute \src "libresoc.v:141714.3-141749.6" + wire $0\mul_op__rc__ok$7$next[0:0]$7445 + attribute \src "libresoc.v:141620.3-141621.51" + wire $0\mul_op__rc__ok$7[0:0]$7412 + attribute \src "libresoc.v:141515.7-141515.32" + wire $0\mul_op__rc__ok$7[0:0]$7498 + attribute \src "libresoc.v:141714.3-141749.6" + wire $0\mul_op__rc__rc$6$next[0:0]$7446 + attribute \src "libresoc.v:141618.3-141619.51" + wire $0\mul_op__rc__rc$6[0:0]$7410 + attribute \src "libresoc.v:141524.7-141524.32" + wire $0\mul_op__rc__rc$6[0:0]$7500 + attribute \src "libresoc.v:141714.3-141749.6" + wire $0\mul_op__write_cr0$10$next[0:0]$7447 + attribute \src "libresoc.v:141626.3-141627.59" + wire $0\mul_op__write_cr0$10[0:0]$7418 + attribute \src "libresoc.v:141531.7-141531.36" + wire $0\mul_op__write_cr0$10[0:0]$7502 + attribute \src "libresoc.v:141701.3-141713.6" + wire width 2 $0\muxid$1$next[1:0]$7433 + attribute \src "libresoc.v:141634.3-141635.33" + wire width 2 $0\muxid$1[1:0]$7426 + attribute \src "libresoc.v:141540.13-141540.29" + wire width 2 $0\muxid$1[1:0]$7504 + attribute \src "libresoc.v:141776.3-141788.6" + wire $0\neg_res$15$next[0:0]$7473 + attribute \src "libresoc.v:141604.3-141605.39" + wire $0\neg_res$15[0:0]$7397 + attribute \src "libresoc.v:141555.7-141555.26" + wire $0\neg_res$15[0:0]$7506 + attribute \src "libresoc.v:141789.3-141801.6" + wire $0\neg_res32$16$next[0:0]$7476 + attribute \src "libresoc.v:141602.3-141603.43" + wire $0\neg_res32$16[0:0]$7395 + attribute \src "libresoc.v:141564.7-141564.28" + wire $0\neg_res32$16[0:0]$7508 + attribute \src "libresoc.v:141750.3-141762.6" + wire width 129 $0\o$next[128:0]$7467 + attribute \src "libresoc.v:141608.3-141609.19" + wire width 129 $0\o[128:0] + attribute \src "libresoc.v:141683.3-141700.6" + wire $0\r_busy$next[0:0]$7429 + attribute \src "libresoc.v:141636.3-141637.29" + wire $0\r_busy[0:0] + attribute \src "libresoc.v:141763.3-141775.6" + wire $0\xer_so$14$next[0:0]$7470 + attribute \src "libresoc.v:141606.3-141607.37" + wire $0\xer_so$14[0:0]$7399 + attribute \src "libresoc.v:141596.7-141596.25" + wire $0\xer_so$14[0:0]$7512 + attribute \src "libresoc.v:141714.3-141749.6" + wire width 12 $1\mul_op__fn_unit$3$next[11:0]$7448 + attribute \src "libresoc.v:141714.3-141749.6" + wire width 64 $1\mul_op__imm_data__data$4$next[63:0]$7449 + attribute \src "libresoc.v:141714.3-141749.6" + wire $1\mul_op__imm_data__ok$5$next[0:0]$7450 + attribute \src "libresoc.v:141714.3-141749.6" + wire width 32 $1\mul_op__insn$13$next[31:0]$7451 + attribute \src "libresoc.v:141714.3-141749.6" + wire width 7 $1\mul_op__insn_type$2$next[6:0]$7452 + attribute \src "libresoc.v:141714.3-141749.6" + wire $1\mul_op__is_32bit$11$next[0:0]$7453 + attribute \src "libresoc.v:141714.3-141749.6" + wire $1\mul_op__is_signed$12$next[0:0]$7454 + attribute \src "libresoc.v:141714.3-141749.6" + wire $1\mul_op__oe__oe$8$next[0:0]$7455 + attribute \src "libresoc.v:141714.3-141749.6" + wire $1\mul_op__oe__ok$9$next[0:0]$7456 + attribute \src "libresoc.v:141714.3-141749.6" + wire $1\mul_op__rc__ok$7$next[0:0]$7457 + attribute \src "libresoc.v:141714.3-141749.6" + wire $1\mul_op__rc__rc$6$next[0:0]$7458 + attribute \src "libresoc.v:141714.3-141749.6" + wire $1\mul_op__write_cr0$10$next[0:0]$7459 + attribute \src "libresoc.v:141701.3-141713.6" + wire width 2 $1\muxid$1$next[1:0]$7434 + attribute \src "libresoc.v:141776.3-141788.6" + wire $1\neg_res$15$next[0:0]$7474 + attribute \src "libresoc.v:141789.3-141801.6" + wire $1\neg_res32$16$next[0:0]$7477 + attribute \src "libresoc.v:141750.3-141762.6" + wire width 129 $1\o$next[128:0]$7468 + attribute \src "libresoc.v:141571.15-141571.57" + wire width 129 $1\o[128:0] + attribute \src "libresoc.v:141683.3-141700.6" + wire $1\r_busy$next[0:0]$7430 + attribute \src "libresoc.v:141585.7-141585.20" + wire $1\r_busy[0:0] + attribute \src "libresoc.v:141763.3-141775.6" + wire $1\xer_so$14$next[0:0]$7471 + attribute \src "libresoc.v:141714.3-141749.6" + wire width 64 $2\mul_op__imm_data__data$4$next[63:0]$7460 + attribute \src "libresoc.v:141714.3-141749.6" + wire $2\mul_op__imm_data__ok$5$next[0:0]$7461 + attribute \src "libresoc.v:141714.3-141749.6" + wire $2\mul_op__oe__oe$8$next[0:0]$7462 + attribute \src "libresoc.v:141714.3-141749.6" + wire $2\mul_op__oe__ok$9$next[0:0]$7463 + attribute \src "libresoc.v:141714.3-141749.6" + wire $2\mul_op__rc__ok$7$next[0:0]$7464 + attribute \src "libresoc.v:141714.3-141749.6" + wire $2\mul_op__rc__rc$6$next[0:0]$7465 + attribute \src "libresoc.v:141683.3-141700.6" + wire $2\r_busy$next[0:0]$7431 + attribute \src "libresoc.v:141601.18-141601.118" + wire $and$libresoc.v:141601$7393_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + wire \$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 41 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 1 \coresync_rst + attribute \src "libresoc.v:140916.7-140916.15" + wire \initial + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \mul2_mul_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \mul2_mul_op__fn_unit$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \mul2_mul_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \mul2_mul_op__imm_data__data$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul2_mul_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul2_mul_op__imm_data__ok$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \mul2_mul_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \mul2_mul_op__insn$29 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \mul2_mul_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \mul2_mul_op__insn_type$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul2_mul_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul2_mul_op__is_32bit$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul2_mul_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul2_mul_op__is_signed$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul2_mul_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul2_mul_op__oe__oe$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul2_mul_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul2_mul_op__oe__ok$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul2_mul_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul2_mul_op__rc__ok$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul2_mul_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul2_mul_op__rc__rc$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul2_mul_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul2_mul_op__write_cr0$26 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \mul2_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \mul2_muxid$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" + wire \mul2_neg_res + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" + wire \mul2_neg_res$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" + wire \mul2_neg_res32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" + wire \mul2_neg_res32$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 129 \mul2_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \mul2_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \mul2_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \mul2_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \mul2_xer_so$30 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 6 \mul_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 output 26 \mul_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \mul_op__fn_unit$3$next + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \mul_op__fn_unit$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 7 \mul_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \mul_op__imm_data__data$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 27 \mul_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \mul_op__imm_data__data$4$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \mul_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__imm_data__ok$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 28 \mul_op__imm_data__ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__imm_data__ok$5$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 16 \mul_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 36 \mul_op__insn$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \mul_op__insn$13$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \mul_op__insn$48 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 5 \mul_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 25 \mul_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \mul_op__insn_type$2$next + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \mul_op__insn_type$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \mul_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 34 \mul_op__is_32bit$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__is_32bit$11$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__is_32bit$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 15 \mul_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 35 \mul_op__is_signed$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__is_signed$12$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__is_signed$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 11 \mul_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__oe__oe$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 31 \mul_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__oe__oe$8$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \mul_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__oe__ok$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 32 \mul_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__oe__ok$9$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \mul_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__rc__ok$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 30 \mul_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__rc__ok$7$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \mul_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__rc__rc$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 29 \mul_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__rc__rc$6$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \mul_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 33 \mul_op__write_cr0$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__write_cr0$10$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__write_cr0$45 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 4 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 24 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$1$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$36 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" + wire \n_i_rdy_data + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire input 23 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire output 22 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" + wire input 20 \neg_res + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" + wire output 39 \neg_res$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" + wire \neg_res$15$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" + wire \neg_res$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" + wire input 21 \neg_res32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" + wire output 40 \neg_res32$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" + wire \neg_res32$16$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" + wire \neg_res32$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 129 output 37 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 129 \o$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 129 \o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire output 3 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" + wire \p_valid_i$33 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire \r_busy$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 17 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 18 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 19 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire output 38 \xer_so$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \xer_so$14$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \xer_so$50 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + cell $and $and$libresoc.v:141601$7393 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i$33 + connect \B \p_ready_o + connect \Y $and$libresoc.v:141601$7393_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:141638.8-141674.4" + cell \mul2 \mul2 + connect \mul_op__fn_unit \mul2_mul_op__fn_unit + connect \mul_op__fn_unit$3 \mul2_mul_op__fn_unit$19 + connect \mul_op__imm_data__data \mul2_mul_op__imm_data__data + connect \mul_op__imm_data__data$4 \mul2_mul_op__imm_data__data$20 + connect \mul_op__imm_data__ok \mul2_mul_op__imm_data__ok + connect \mul_op__imm_data__ok$5 \mul2_mul_op__imm_data__ok$21 + connect \mul_op__insn \mul2_mul_op__insn + connect \mul_op__insn$13 \mul2_mul_op__insn$29 + connect \mul_op__insn_type \mul2_mul_op__insn_type + connect \mul_op__insn_type$2 \mul2_mul_op__insn_type$18 + connect \mul_op__is_32bit \mul2_mul_op__is_32bit + connect \mul_op__is_32bit$11 \mul2_mul_op__is_32bit$27 + connect \mul_op__is_signed \mul2_mul_op__is_signed + connect \mul_op__is_signed$12 \mul2_mul_op__is_signed$28 + connect \mul_op__oe__oe \mul2_mul_op__oe__oe + connect \mul_op__oe__oe$8 \mul2_mul_op__oe__oe$24 + connect \mul_op__oe__ok \mul2_mul_op__oe__ok + connect \mul_op__oe__ok$9 \mul2_mul_op__oe__ok$25 + connect \mul_op__rc__ok \mul2_mul_op__rc__ok + connect \mul_op__rc__ok$7 \mul2_mul_op__rc__ok$23 + connect \mul_op__rc__rc \mul2_mul_op__rc__rc + connect \mul_op__rc__rc$6 \mul2_mul_op__rc__rc$22 + connect \mul_op__write_cr0 \mul2_mul_op__write_cr0 + connect \mul_op__write_cr0$10 \mul2_mul_op__write_cr0$26 + connect \muxid \mul2_muxid + connect \muxid$1 \mul2_muxid$17 + connect \neg_res \mul2_neg_res + connect \neg_res$15 \mul2_neg_res$31 + connect \neg_res32 \mul2_neg_res32 + connect \neg_res32$16 \mul2_neg_res32$32 + connect \o \mul2_o + connect \ra \mul2_ra + connect \rb \mul2_rb + connect \xer_so \mul2_xer_so + connect \xer_so$14 \mul2_xer_so$30 + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:141675.10-141678.4" + cell \n$94 \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:141679.10-141682.4" + cell \p$93 \p + connect \p_ready_o \p_ready_o + connect \p_valid_i \p_valid_i + end + attribute \src "libresoc.v:140916.7-140916.20" + process $proc$libresoc.v:140916$7478 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:141197.14-141197.43" + process $proc$libresoc.v:141197$7479 + assign { } { } + assign $0\mul_op__fn_unit$3[11:0]$7480 12'000000000000 + sync always + sync init + update \mul_op__fn_unit$3 $0\mul_op__fn_unit$3[11:0]$7480 + end + attribute \src "libresoc.v:141221.14-141221.63" + process $proc$libresoc.v:141221$7481 + assign { } { } + assign $0\mul_op__imm_data__data$4[63:0]$7482 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \mul_op__imm_data__data$4 $0\mul_op__imm_data__data$4[63:0]$7482 + end + attribute \src "libresoc.v:141230.7-141230.38" + process $proc$libresoc.v:141230$7483 + assign { } { } + assign $0\mul_op__imm_data__ok$5[0:0]$7484 1'0 + sync always + sync init + update \mul_op__imm_data__ok$5 $0\mul_op__imm_data__ok$5[0:0]$7484 + end + attribute \src "libresoc.v:141237.14-141237.39" + process $proc$libresoc.v:141237$7485 + assign { } { } + assign $0\mul_op__insn$13[31:0]$7486 0 + sync always + sync init + update \mul_op__insn$13 $0\mul_op__insn$13[31:0]$7486 + end + attribute \src "libresoc.v:141394.13-141394.42" + process $proc$libresoc.v:141394$7487 + assign { } { } + assign $0\mul_op__insn_type$2[6:0]$7488 7'0000000 + sync always + sync init + update \mul_op__insn_type$2 $0\mul_op__insn_type$2[6:0]$7488 + end + attribute \src "libresoc.v:141477.7-141477.35" + process $proc$libresoc.v:141477$7489 + assign { } { } + assign $0\mul_op__is_32bit$11[0:0]$7490 1'0 + sync always + sync init + update \mul_op__is_32bit$11 $0\mul_op__is_32bit$11[0:0]$7490 + end + attribute \src "libresoc.v:141486.7-141486.36" + process $proc$libresoc.v:141486$7491 + assign { } { } + assign $0\mul_op__is_signed$12[0:0]$7492 1'0 + sync always + sync init + update \mul_op__is_signed$12 $0\mul_op__is_signed$12[0:0]$7492 + end + attribute \src "libresoc.v:141497.7-141497.32" + process $proc$libresoc.v:141497$7493 + assign { } { } + assign $0\mul_op__oe__oe$8[0:0]$7494 1'0 + sync always + sync init + update \mul_op__oe__oe$8 $0\mul_op__oe__oe$8[0:0]$7494 + end + attribute \src "libresoc.v:141506.7-141506.32" + process $proc$libresoc.v:141506$7495 + assign { } { } + assign $0\mul_op__oe__ok$9[0:0]$7496 1'0 + sync always + sync init + update \mul_op__oe__ok$9 $0\mul_op__oe__ok$9[0:0]$7496 + end + attribute \src "libresoc.v:141515.7-141515.32" + process $proc$libresoc.v:141515$7497 + assign { } { } + assign $0\mul_op__rc__ok$7[0:0]$7498 1'0 + sync always + sync init + update \mul_op__rc__ok$7 $0\mul_op__rc__ok$7[0:0]$7498 + end + attribute \src "libresoc.v:141524.7-141524.32" + process $proc$libresoc.v:141524$7499 + assign { } { } + assign $0\mul_op__rc__rc$6[0:0]$7500 1'0 + sync always + sync init + update \mul_op__rc__rc$6 $0\mul_op__rc__rc$6[0:0]$7500 + end + attribute \src "libresoc.v:141531.7-141531.36" + process $proc$libresoc.v:141531$7501 + assign { } { } + assign $0\mul_op__write_cr0$10[0:0]$7502 1'0 + sync always + sync init + update \mul_op__write_cr0$10 $0\mul_op__write_cr0$10[0:0]$7502 + end + attribute \src "libresoc.v:141540.13-141540.29" + process $proc$libresoc.v:141540$7503 + assign { } { } + assign $0\muxid$1[1:0]$7504 2'00 + sync always + sync init + update \muxid$1 $0\muxid$1[1:0]$7504 + end + attribute \src "libresoc.v:141555.7-141555.26" + process $proc$libresoc.v:141555$7505 + assign { } { } + assign $0\neg_res$15[0:0]$7506 1'0 + sync always + sync init + update \neg_res$15 $0\neg_res$15[0:0]$7506 + end + attribute \src "libresoc.v:141564.7-141564.28" + process $proc$libresoc.v:141564$7507 + assign { } { } + assign $0\neg_res32$16[0:0]$7508 1'0 + sync always + sync init + update \neg_res32$16 $0\neg_res32$16[0:0]$7508 + end + attribute \src "libresoc.v:141571.15-141571.57" + process $proc$libresoc.v:141571$7509 + assign { } { } + assign $1\o[128:0] 129'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \o $1\o[128:0] + end + attribute \src "libresoc.v:141585.7-141585.20" + process $proc$libresoc.v:141585$7510 + assign { } { } + assign $1\r_busy[0:0] 1'0 + sync always + sync init + update \r_busy $1\r_busy[0:0] + end + attribute \src "libresoc.v:141596.7-141596.25" + process $proc$libresoc.v:141596$7511 + assign { } { } + assign $0\xer_so$14[0:0]$7512 1'0 + sync always + sync init + update \xer_so$14 $0\xer_so$14[0:0]$7512 + end + attribute \src "libresoc.v:141602.3-141603.43" + process $proc$libresoc.v:141602$7394 + assign { } { } + assign $0\neg_res32$16[0:0]$7395 \neg_res32$16$next + sync posedge \coresync_clk + update \neg_res32$16 $0\neg_res32$16[0:0]$7395 + end + attribute \src "libresoc.v:141604.3-141605.39" + process $proc$libresoc.v:141604$7396 + assign { } { } + assign $0\neg_res$15[0:0]$7397 \neg_res$15$next + sync posedge \coresync_clk + update \neg_res$15 $0\neg_res$15[0:0]$7397 + end + attribute \src "libresoc.v:141606.3-141607.37" + process $proc$libresoc.v:141606$7398 + assign { } { } + assign $0\xer_so$14[0:0]$7399 \xer_so$14$next + sync posedge \coresync_clk + update \xer_so$14 $0\xer_so$14[0:0]$7399 + end + attribute \src "libresoc.v:141608.3-141609.19" + process $proc$libresoc.v:141608$7400 + assign { } { } + assign $0\o[128:0] \o$next + sync posedge \coresync_clk + update \o $0\o[128:0] + end + attribute \src "libresoc.v:141610.3-141611.57" + process $proc$libresoc.v:141610$7401 + assign { } { } + assign $0\mul_op__insn_type$2[6:0]$7402 \mul_op__insn_type$2$next + sync posedge \coresync_clk + update \mul_op__insn_type$2 $0\mul_op__insn_type$2[6:0]$7402 + end + attribute \src "libresoc.v:141612.3-141613.53" + process $proc$libresoc.v:141612$7403 + assign { } { } + assign $0\mul_op__fn_unit$3[11:0]$7404 \mul_op__fn_unit$3$next + sync posedge \coresync_clk + update \mul_op__fn_unit$3 $0\mul_op__fn_unit$3[11:0]$7404 + end + attribute \src "libresoc.v:141614.3-141615.67" + process $proc$libresoc.v:141614$7405 + assign { } { } + assign $0\mul_op__imm_data__data$4[63:0]$7406 \mul_op__imm_data__data$4$next + sync posedge \coresync_clk + update \mul_op__imm_data__data$4 $0\mul_op__imm_data__data$4[63:0]$7406 + end + attribute \src "libresoc.v:141616.3-141617.63" + process $proc$libresoc.v:141616$7407 + assign { } { } + assign $0\mul_op__imm_data__ok$5[0:0]$7408 \mul_op__imm_data__ok$5$next + sync posedge \coresync_clk + update \mul_op__imm_data__ok$5 $0\mul_op__imm_data__ok$5[0:0]$7408 + end + attribute \src "libresoc.v:141618.3-141619.51" + process $proc$libresoc.v:141618$7409 + assign { } { } + assign $0\mul_op__rc__rc$6[0:0]$7410 \mul_op__rc__rc$6$next + sync posedge \coresync_clk + update \mul_op__rc__rc$6 $0\mul_op__rc__rc$6[0:0]$7410 + end + attribute \src "libresoc.v:141620.3-141621.51" + process $proc$libresoc.v:141620$7411 + assign { } { } + assign $0\mul_op__rc__ok$7[0:0]$7412 \mul_op__rc__ok$7$next + sync posedge \coresync_clk + update \mul_op__rc__ok$7 $0\mul_op__rc__ok$7[0:0]$7412 + end + attribute \src "libresoc.v:141622.3-141623.51" + process $proc$libresoc.v:141622$7413 + assign { } { } + assign $0\mul_op__oe__oe$8[0:0]$7414 \mul_op__oe__oe$8$next + sync posedge \coresync_clk + update \mul_op__oe__oe$8 $0\mul_op__oe__oe$8[0:0]$7414 + end + attribute \src "libresoc.v:141624.3-141625.51" + process $proc$libresoc.v:141624$7415 + assign { } { } + assign $0\mul_op__oe__ok$9[0:0]$7416 \mul_op__oe__ok$9$next + sync posedge \coresync_clk + update \mul_op__oe__ok$9 $0\mul_op__oe__ok$9[0:0]$7416 + end + attribute \src "libresoc.v:141626.3-141627.59" + process $proc$libresoc.v:141626$7417 + assign { } { } + assign $0\mul_op__write_cr0$10[0:0]$7418 \mul_op__write_cr0$10$next + sync posedge \coresync_clk + update \mul_op__write_cr0$10 $0\mul_op__write_cr0$10[0:0]$7418 + end + attribute \src "libresoc.v:141628.3-141629.57" + process $proc$libresoc.v:141628$7419 + assign { } { } + assign $0\mul_op__is_32bit$11[0:0]$7420 \mul_op__is_32bit$11$next + sync posedge \coresync_clk + update \mul_op__is_32bit$11 $0\mul_op__is_32bit$11[0:0]$7420 + end + attribute \src "libresoc.v:141630.3-141631.59" + process $proc$libresoc.v:141630$7421 + assign { } { } + assign $0\mul_op__is_signed$12[0:0]$7422 \mul_op__is_signed$12$next + sync posedge \coresync_clk + update \mul_op__is_signed$12 $0\mul_op__is_signed$12[0:0]$7422 + end + attribute \src "libresoc.v:141632.3-141633.49" + process $proc$libresoc.v:141632$7423 + assign { } { } + assign $0\mul_op__insn$13[31:0]$7424 \mul_op__insn$13$next + sync posedge \coresync_clk + update \mul_op__insn$13 $0\mul_op__insn$13[31:0]$7424 + end + attribute \src "libresoc.v:141634.3-141635.33" + process $proc$libresoc.v:141634$7425 + assign { } { } + assign $0\muxid$1[1:0]$7426 \muxid$1$next + sync posedge \coresync_clk + update \muxid$1 $0\muxid$1[1:0]$7426 + end + attribute \src "libresoc.v:141636.3-141637.29" + process $proc$libresoc.v:141636$7427 + assign { } { } + assign $0\r_busy[0:0] \r_busy$next + sync posedge \coresync_clk + update \r_busy $0\r_busy[0:0] + end + attribute \src "libresoc.v:141683.3-141700.6" + process $proc$libresoc.v:141683$7428 + assign { } { } + assign { } { } + assign { } { } + assign $0\r_busy$next[0:0]$7429 $2\r_busy$next[0:0]$7431 + attribute \src "libresoc.v:141684.5-141684.29" + switch \initial + attribute \src "libresoc.v:141684.9-141684.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\r_busy$next[0:0]$7430 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\r_busy$next[0:0]$7430 1'0 + case + assign $1\r_busy$next[0:0]$7430 \r_busy + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r_busy$next[0:0]$7431 1'0 + case + assign $2\r_busy$next[0:0]$7431 $1\r_busy$next[0:0]$7430 + end + sync always + update \r_busy$next $0\r_busy$next[0:0]$7429 + end + attribute \src "libresoc.v:141701.3-141713.6" + process $proc$libresoc.v:141701$7432 + assign { } { } + assign { } { } + assign $0\muxid$1$next[1:0]$7433 $1\muxid$1$next[1:0]$7434 + attribute \src "libresoc.v:141702.5-141702.29" + switch \initial + attribute \src "libresoc.v:141702.9-141702.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\muxid$1$next[1:0]$7434 \muxid$36 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\muxid$1$next[1:0]$7434 \muxid$36 + case + assign $1\muxid$1$next[1:0]$7434 \muxid$1 + end + sync always + update \muxid$1$next $0\muxid$1$next[1:0]$7433 + end + attribute \src "libresoc.v:141714.3-141749.6" + process $proc$libresoc.v:141714$7435 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\mul_op__fn_unit$3$next[11:0]$7436 $1\mul_op__fn_unit$3$next[11:0]$7448 + assign { } { } + assign { } { } + assign $0\mul_op__insn$13$next[31:0]$7439 $1\mul_op__insn$13$next[31:0]$7451 + assign $0\mul_op__insn_type$2$next[6:0]$7440 $1\mul_op__insn_type$2$next[6:0]$7452 + assign $0\mul_op__is_32bit$11$next[0:0]$7441 $1\mul_op__is_32bit$11$next[0:0]$7453 + assign $0\mul_op__is_signed$12$next[0:0]$7442 $1\mul_op__is_signed$12$next[0:0]$7454 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\mul_op__write_cr0$10$next[0:0]$7447 $1\mul_op__write_cr0$10$next[0:0]$7459 + assign $0\mul_op__imm_data__data$4$next[63:0]$7437 $2\mul_op__imm_data__data$4$next[63:0]$7460 + assign $0\mul_op__imm_data__ok$5$next[0:0]$7438 $2\mul_op__imm_data__ok$5$next[0:0]$7461 + assign $0\mul_op__oe__oe$8$next[0:0]$7443 $2\mul_op__oe__oe$8$next[0:0]$7462 + assign $0\mul_op__oe__ok$9$next[0:0]$7444 $2\mul_op__oe__ok$9$next[0:0]$7463 + assign $0\mul_op__rc__ok$7$next[0:0]$7445 $2\mul_op__rc__ok$7$next[0:0]$7464 + assign $0\mul_op__rc__rc$6$next[0:0]$7446 $2\mul_op__rc__rc$6$next[0:0]$7465 + attribute \src "libresoc.v:141715.5-141715.29" + switch \initial + attribute \src "libresoc.v:141715.9-141715.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\mul_op__insn$13$next[31:0]$7451 $1\mul_op__is_signed$12$next[0:0]$7454 $1\mul_op__is_32bit$11$next[0:0]$7453 $1\mul_op__write_cr0$10$next[0:0]$7459 $1\mul_op__oe__ok$9$next[0:0]$7456 $1\mul_op__oe__oe$8$next[0:0]$7455 $1\mul_op__rc__ok$7$next[0:0]$7457 $1\mul_op__rc__rc$6$next[0:0]$7458 $1\mul_op__imm_data__ok$5$next[0:0]$7450 $1\mul_op__imm_data__data$4$next[63:0]$7449 $1\mul_op__fn_unit$3$next[11:0]$7448 $1\mul_op__insn_type$2$next[6:0]$7452 } { \mul_op__insn$48 \mul_op__is_signed$47 \mul_op__is_32bit$46 \mul_op__write_cr0$45 \mul_op__oe__ok$44 \mul_op__oe__oe$43 \mul_op__rc__ok$42 \mul_op__rc__rc$41 \mul_op__imm_data__ok$40 \mul_op__imm_data__data$39 \mul_op__fn_unit$38 \mul_op__insn_type$37 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\mul_op__insn$13$next[31:0]$7451 $1\mul_op__is_signed$12$next[0:0]$7454 $1\mul_op__is_32bit$11$next[0:0]$7453 $1\mul_op__write_cr0$10$next[0:0]$7459 $1\mul_op__oe__ok$9$next[0:0]$7456 $1\mul_op__oe__oe$8$next[0:0]$7455 $1\mul_op__rc__ok$7$next[0:0]$7457 $1\mul_op__rc__rc$6$next[0:0]$7458 $1\mul_op__imm_data__ok$5$next[0:0]$7450 $1\mul_op__imm_data__data$4$next[63:0]$7449 $1\mul_op__fn_unit$3$next[11:0]$7448 $1\mul_op__insn_type$2$next[6:0]$7452 } { \mul_op__insn$48 \mul_op__is_signed$47 \mul_op__is_32bit$46 \mul_op__write_cr0$45 \mul_op__oe__ok$44 \mul_op__oe__oe$43 \mul_op__rc__ok$42 \mul_op__rc__rc$41 \mul_op__imm_data__ok$40 \mul_op__imm_data__data$39 \mul_op__fn_unit$38 \mul_op__insn_type$37 } + case + assign $1\mul_op__fn_unit$3$next[11:0]$7448 \mul_op__fn_unit$3 + assign $1\mul_op__imm_data__data$4$next[63:0]$7449 \mul_op__imm_data__data$4 + assign $1\mul_op__imm_data__ok$5$next[0:0]$7450 \mul_op__imm_data__ok$5 + assign $1\mul_op__insn$13$next[31:0]$7451 \mul_op__insn$13 + assign $1\mul_op__insn_type$2$next[6:0]$7452 \mul_op__insn_type$2 + assign $1\mul_op__is_32bit$11$next[0:0]$7453 \mul_op__is_32bit$11 + assign $1\mul_op__is_signed$12$next[0:0]$7454 \mul_op__is_signed$12 + assign $1\mul_op__oe__oe$8$next[0:0]$7455 \mul_op__oe__oe$8 + assign $1\mul_op__oe__ok$9$next[0:0]$7456 \mul_op__oe__ok$9 + assign $1\mul_op__rc__ok$7$next[0:0]$7457 \mul_op__rc__ok$7 + assign $1\mul_op__rc__rc$6$next[0:0]$7458 \mul_op__rc__rc$6 + assign $1\mul_op__write_cr0$10$next[0:0]$7459 \mul_op__write_cr0$10 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $2\mul_op__imm_data__data$4$next[63:0]$7460 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\mul_op__imm_data__ok$5$next[0:0]$7461 1'0 + assign $2\mul_op__rc__rc$6$next[0:0]$7465 1'0 + assign $2\mul_op__rc__ok$7$next[0:0]$7464 1'0 + assign $2\mul_op__oe__oe$8$next[0:0]$7462 1'0 + assign $2\mul_op__oe__ok$9$next[0:0]$7463 1'0 + case + assign $2\mul_op__imm_data__data$4$next[63:0]$7460 $1\mul_op__imm_data__data$4$next[63:0]$7449 + assign $2\mul_op__imm_data__ok$5$next[0:0]$7461 $1\mul_op__imm_data__ok$5$next[0:0]$7450 + assign $2\mul_op__oe__oe$8$next[0:0]$7462 $1\mul_op__oe__oe$8$next[0:0]$7455 + assign $2\mul_op__oe__ok$9$next[0:0]$7463 $1\mul_op__oe__ok$9$next[0:0]$7456 + assign $2\mul_op__rc__ok$7$next[0:0]$7464 $1\mul_op__rc__ok$7$next[0:0]$7457 + assign $2\mul_op__rc__rc$6$next[0:0]$7465 $1\mul_op__rc__rc$6$next[0:0]$7458 + end + sync always + update \mul_op__fn_unit$3$next $0\mul_op__fn_unit$3$next[11:0]$7436 + update \mul_op__imm_data__data$4$next $0\mul_op__imm_data__data$4$next[63:0]$7437 + update \mul_op__imm_data__ok$5$next $0\mul_op__imm_data__ok$5$next[0:0]$7438 + update \mul_op__insn$13$next $0\mul_op__insn$13$next[31:0]$7439 + update \mul_op__insn_type$2$next $0\mul_op__insn_type$2$next[6:0]$7440 + update \mul_op__is_32bit$11$next $0\mul_op__is_32bit$11$next[0:0]$7441 + update \mul_op__is_signed$12$next $0\mul_op__is_signed$12$next[0:0]$7442 + update \mul_op__oe__oe$8$next $0\mul_op__oe__oe$8$next[0:0]$7443 + update \mul_op__oe__ok$9$next $0\mul_op__oe__ok$9$next[0:0]$7444 + update \mul_op__rc__ok$7$next $0\mul_op__rc__ok$7$next[0:0]$7445 + update \mul_op__rc__rc$6$next $0\mul_op__rc__rc$6$next[0:0]$7446 + update \mul_op__write_cr0$10$next $0\mul_op__write_cr0$10$next[0:0]$7447 + end + attribute \src "libresoc.v:141750.3-141762.6" + process $proc$libresoc.v:141750$7466 + assign { } { } + assign { } { } + assign $0\o$next[128:0]$7467 $1\o$next[128:0]$7468 + attribute \src "libresoc.v:141751.5-141751.29" + switch \initial + attribute \src "libresoc.v:141751.9-141751.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\o$next[128:0]$7468 \o$49 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\o$next[128:0]$7468 \o$49 + case + assign $1\o$next[128:0]$7468 \o + end + sync always + update \o$next $0\o$next[128:0]$7467 + end + attribute \src "libresoc.v:141763.3-141775.6" + process $proc$libresoc.v:141763$7469 + assign { } { } + assign { } { } + assign $0\xer_so$14$next[0:0]$7470 $1\xer_so$14$next[0:0]$7471 + attribute \src "libresoc.v:141764.5-141764.29" + switch \initial + attribute \src "libresoc.v:141764.9-141764.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\xer_so$14$next[0:0]$7471 \xer_so$50 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\xer_so$14$next[0:0]$7471 \xer_so$50 + case + assign $1\xer_so$14$next[0:0]$7471 \xer_so$14 + end + sync always + update \xer_so$14$next $0\xer_so$14$next[0:0]$7470 + end + attribute \src "libresoc.v:141776.3-141788.6" + process $proc$libresoc.v:141776$7472 + assign { } { } + assign { } { } + assign $0\neg_res$15$next[0:0]$7473 $1\neg_res$15$next[0:0]$7474 + attribute \src "libresoc.v:141777.5-141777.29" + switch \initial + attribute \src "libresoc.v:141777.9-141777.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\neg_res$15$next[0:0]$7474 \neg_res$51 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\neg_res$15$next[0:0]$7474 \neg_res$51 + case + assign $1\neg_res$15$next[0:0]$7474 \neg_res$15 + end + sync always + update \neg_res$15$next $0\neg_res$15$next[0:0]$7473 + end + attribute \src "libresoc.v:141789.3-141801.6" + process $proc$libresoc.v:141789$7475 + assign { } { } + assign { } { } + assign $0\neg_res32$16$next[0:0]$7476 $1\neg_res32$16$next[0:0]$7477 + attribute \src "libresoc.v:141790.5-141790.29" + switch \initial + attribute \src "libresoc.v:141790.9-141790.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\neg_res32$16$next[0:0]$7477 \neg_res32$52 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\neg_res32$16$next[0:0]$7477 \neg_res32$52 + case + assign $1\neg_res32$16$next[0:0]$7477 \neg_res32$16 + end + sync always + update \neg_res32$16$next $0\neg_res32$16$next[0:0]$7476 + end + connect \$34 $and$libresoc.v:141601$7393_Y + connect \p_ready_o \n_i_rdy_data + connect \n_valid_o \r_busy + connect \neg_res32$52 \mul2_neg_res32$32 + connect \neg_res$51 \mul2_neg_res$31 + connect \xer_so$50 \mul2_xer_so$30 + connect \o$49 \mul2_o + connect { \mul_op__insn$48 \mul_op__is_signed$47 \mul_op__is_32bit$46 \mul_op__write_cr0$45 \mul_op__oe__ok$44 \mul_op__oe__oe$43 \mul_op__rc__ok$42 \mul_op__rc__rc$41 \mul_op__imm_data__ok$40 \mul_op__imm_data__data$39 \mul_op__fn_unit$38 \mul_op__insn_type$37 } { \mul2_mul_op__insn$29 \mul2_mul_op__is_signed$28 \mul2_mul_op__is_32bit$27 \mul2_mul_op__write_cr0$26 \mul2_mul_op__oe__ok$25 \mul2_mul_op__oe__oe$24 \mul2_mul_op__rc__ok$23 \mul2_mul_op__rc__rc$22 \mul2_mul_op__imm_data__ok$21 \mul2_mul_op__imm_data__data$20 \mul2_mul_op__fn_unit$19 \mul2_mul_op__insn_type$18 } + connect \muxid$36 \mul2_muxid$17 + connect \p_valid_i_p_ready_o \$34 + connect \n_i_rdy_data \n_ready_i + connect \p_valid_i$33 \p_valid_i + connect \mul2_neg_res32 \neg_res32 + connect \mul2_neg_res \neg_res + connect \mul2_xer_so \xer_so + connect \mul2_rb \rb + connect \mul2_ra \ra + connect { \mul2_mul_op__insn \mul2_mul_op__is_signed \mul2_mul_op__is_32bit \mul2_mul_op__write_cr0 \mul2_mul_op__oe__ok \mul2_mul_op__oe__oe \mul2_mul_op__rc__ok \mul2_mul_op__rc__rc \mul2_mul_op__imm_data__ok \mul2_mul_op__imm_data__data \mul2_mul_op__fn_unit \mul2_mul_op__insn_type } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__oe__ok \mul_op__oe__oe \mul_op__rc__ok \mul_op__rc__rc \mul_op__imm_data__ok \mul_op__imm_data__data \mul_op__fn_unit \mul_op__insn_type } + connect \mul2_muxid \muxid +end +attribute \src "libresoc.v:141824.1-143099.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe3" +attribute \generator "nMigen" +module \mul_pipe3 + attribute \src "libresoc.v:143017.3-143035.6" + wire width 4 $0\cr_a$next[3:0]$7596 + attribute \src "libresoc.v:142809.3-142810.25" + wire width 4 $0\cr_a[3:0] + attribute \src "libresoc.v:143017.3-143035.6" + wire $0\cr_a_ok$next[0:0]$7597 + attribute \src "libresoc.v:142811.3-142812.31" + wire $0\cr_a_ok[0:0] + attribute \src "libresoc.v:141825.7-141825.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:142962.3-142997.6" + wire width 12 $0\mul_op__fn_unit$3$next[11:0]$7559 + attribute \src "libresoc.v:142819.3-142820.53" + wire width 12 $0\mul_op__fn_unit$3[11:0]$7527 + attribute \src "libresoc.v:142126.14-142126.43" + wire width 12 $0\mul_op__fn_unit$3[11:0]$7617 + attribute \src "libresoc.v:142962.3-142997.6" + wire width 64 $0\mul_op__imm_data__data$4$next[63:0]$7560 + attribute \src "libresoc.v:142821.3-142822.67" + wire width 64 $0\mul_op__imm_data__data$4[63:0]$7529 + attribute \src "libresoc.v:142148.14-142148.63" + wire width 64 $0\mul_op__imm_data__data$4[63:0]$7619 + attribute \src "libresoc.v:142962.3-142997.6" + wire $0\mul_op__imm_data__ok$5$next[0:0]$7561 + attribute \src "libresoc.v:142823.3-142824.63" + wire $0\mul_op__imm_data__ok$5[0:0]$7531 + attribute \src "libresoc.v:142157.7-142157.38" + wire $0\mul_op__imm_data__ok$5[0:0]$7621 + attribute \src "libresoc.v:142962.3-142997.6" + wire width 32 $0\mul_op__insn$13$next[31:0]$7562 + attribute \src "libresoc.v:142839.3-142840.49" + wire width 32 $0\mul_op__insn$13[31:0]$7547 + attribute \src "libresoc.v:142166.14-142166.39" + wire width 32 $0\mul_op__insn$13[31:0]$7623 + attribute \src "libresoc.v:142962.3-142997.6" + wire width 7 $0\mul_op__insn_type$2$next[6:0]$7563 + attribute \src "libresoc.v:142817.3-142818.57" + wire width 7 $0\mul_op__insn_type$2[6:0]$7525 + attribute \src "libresoc.v:142323.13-142323.42" + wire width 7 $0\mul_op__insn_type$2[6:0]$7625 + attribute \src "libresoc.v:142962.3-142997.6" + wire $0\mul_op__is_32bit$11$next[0:0]$7564 + attribute \src "libresoc.v:142835.3-142836.57" + wire $0\mul_op__is_32bit$11[0:0]$7543 + attribute \src "libresoc.v:142406.7-142406.35" + wire $0\mul_op__is_32bit$11[0:0]$7627 + attribute \src "libresoc.v:142962.3-142997.6" + wire $0\mul_op__is_signed$12$next[0:0]$7565 + attribute \src "libresoc.v:142837.3-142838.59" + wire $0\mul_op__is_signed$12[0:0]$7545 + attribute \src "libresoc.v:142415.7-142415.36" + wire $0\mul_op__is_signed$12[0:0]$7629 + attribute \src "libresoc.v:142962.3-142997.6" + wire $0\mul_op__oe__oe$8$next[0:0]$7566 + attribute \src "libresoc.v:142829.3-142830.51" + wire $0\mul_op__oe__oe$8[0:0]$7537 + attribute \src "libresoc.v:142426.7-142426.32" + wire $0\mul_op__oe__oe$8[0:0]$7631 + attribute \src "libresoc.v:142962.3-142997.6" + wire $0\mul_op__oe__ok$9$next[0:0]$7567 + attribute \src "libresoc.v:142831.3-142832.51" + wire $0\mul_op__oe__ok$9[0:0]$7539 + attribute \src "libresoc.v:142435.7-142435.32" + wire $0\mul_op__oe__ok$9[0:0]$7633 + attribute \src "libresoc.v:142962.3-142997.6" + wire $0\mul_op__rc__ok$7$next[0:0]$7568 + attribute \src "libresoc.v:142827.3-142828.51" + wire $0\mul_op__rc__ok$7[0:0]$7535 + attribute \src "libresoc.v:142444.7-142444.32" + wire $0\mul_op__rc__ok$7[0:0]$7635 + attribute \src "libresoc.v:142962.3-142997.6" + wire $0\mul_op__rc__rc$6$next[0:0]$7569 + attribute \src "libresoc.v:142825.3-142826.51" + wire $0\mul_op__rc__rc$6[0:0]$7533 + attribute \src "libresoc.v:142451.7-142451.32" + wire $0\mul_op__rc__rc$6[0:0]$7637 + attribute \src "libresoc.v:142962.3-142997.6" + wire $0\mul_op__write_cr0$10$next[0:0]$7570 + attribute \src "libresoc.v:142833.3-142834.59" + wire $0\mul_op__write_cr0$10[0:0]$7541 + attribute \src "libresoc.v:142460.7-142460.36" + wire $0\mul_op__write_cr0$10[0:0]$7639 + attribute \src "libresoc.v:142949.3-142961.6" + wire width 2 $0\muxid$1$next[1:0]$7556 + attribute \src "libresoc.v:142841.3-142842.33" + wire width 2 $0\muxid$1[1:0]$7549 + attribute \src "libresoc.v:142469.13-142469.29" + wire width 2 $0\muxid$1[1:0]$7641 + attribute \src "libresoc.v:142998.3-143016.6" + wire width 64 $0\o$14$next[63:0]$7591 + attribute \src "libresoc.v:142813.3-142814.27" + wire width 64 $0\o$14[63:0]$7522 + attribute \src "libresoc.v:142490.14-142490.43" + wire width 64 $0\o$14[63:0]$7643 + attribute \src "libresoc.v:142998.3-143016.6" + wire $0\o_ok$next[0:0]$7590 + attribute \src "libresoc.v:142815.3-142816.25" + wire $0\o_ok[0:0] + attribute \src "libresoc.v:142931.3-142948.6" + wire $0\r_busy$next[0:0]$7552 + attribute \src "libresoc.v:142843.3-142844.29" + wire $0\r_busy[0:0] + attribute \src "libresoc.v:143036.3-143054.6" + wire width 2 $0\xer_ov$next[1:0]$7602 + attribute \src "libresoc.v:142805.3-142806.29" + wire width 2 $0\xer_ov[1:0] + attribute \src "libresoc.v:143036.3-143054.6" + wire $0\xer_ov_ok$next[0:0]$7603 + attribute \src "libresoc.v:142807.3-142808.35" + wire $0\xer_ov_ok[0:0] + attribute \src "libresoc.v:143055.3-143073.6" + wire $0\xer_so$15$next[0:0]$7609 + attribute \src "libresoc.v:142801.3-142802.37" + wire $0\xer_so$15[0:0]$7515 + attribute \src "libresoc.v:142786.7-142786.25" + wire $0\xer_so$15[0:0]$7649 + attribute \src "libresoc.v:143055.3-143073.6" + wire $0\xer_so_ok$next[0:0]$7608 + attribute \src "libresoc.v:142803.3-142804.35" + wire $0\xer_so_ok[0:0] + attribute \src "libresoc.v:143017.3-143035.6" + wire width 4 $1\cr_a$next[3:0]$7598 + attribute \src "libresoc.v:141834.13-141834.24" + wire width 4 $1\cr_a[3:0] + attribute \src "libresoc.v:143017.3-143035.6" + wire $1\cr_a_ok$next[0:0]$7599 + attribute \src "libresoc.v:141843.7-141843.21" + wire $1\cr_a_ok[0:0] + attribute \src "libresoc.v:142962.3-142997.6" + wire width 12 $1\mul_op__fn_unit$3$next[11:0]$7571 + attribute \src "libresoc.v:142962.3-142997.6" + wire width 64 $1\mul_op__imm_data__data$4$next[63:0]$7572 + attribute \src "libresoc.v:142962.3-142997.6" + wire $1\mul_op__imm_data__ok$5$next[0:0]$7573 + attribute \src "libresoc.v:142962.3-142997.6" + wire width 32 $1\mul_op__insn$13$next[31:0]$7574 + attribute \src "libresoc.v:142962.3-142997.6" + wire width 7 $1\mul_op__insn_type$2$next[6:0]$7575 + attribute \src "libresoc.v:142962.3-142997.6" + wire $1\mul_op__is_32bit$11$next[0:0]$7576 + attribute \src "libresoc.v:142962.3-142997.6" + wire $1\mul_op__is_signed$12$next[0:0]$7577 + attribute \src "libresoc.v:142962.3-142997.6" + wire $1\mul_op__oe__oe$8$next[0:0]$7578 + attribute \src "libresoc.v:142962.3-142997.6" + wire $1\mul_op__oe__ok$9$next[0:0]$7579 + attribute \src "libresoc.v:142962.3-142997.6" + wire $1\mul_op__rc__ok$7$next[0:0]$7580 + attribute \src "libresoc.v:142962.3-142997.6" + wire $1\mul_op__rc__rc$6$next[0:0]$7581 + attribute \src "libresoc.v:142962.3-142997.6" + wire $1\mul_op__write_cr0$10$next[0:0]$7582 + attribute \src "libresoc.v:142949.3-142961.6" + wire width 2 $1\muxid$1$next[1:0]$7557 + attribute \src "libresoc.v:142998.3-143016.6" + wire width 64 $1\o$14$next[63:0]$7593 + attribute \src "libresoc.v:142998.3-143016.6" + wire $1\o_ok$next[0:0]$7592 + attribute \src "libresoc.v:142497.7-142497.18" + wire $1\o_ok[0:0] + attribute \src "libresoc.v:142931.3-142948.6" + wire $1\r_busy$next[0:0]$7553 + attribute \src "libresoc.v:142763.7-142763.20" + wire $1\r_busy[0:0] + attribute \src "libresoc.v:143036.3-143054.6" + wire width 2 $1\xer_ov$next[1:0]$7604 + attribute \src "libresoc.v:142768.13-142768.26" + wire width 2 $1\xer_ov[1:0] + attribute \src "libresoc.v:143036.3-143054.6" + wire $1\xer_ov_ok$next[0:0]$7605 + attribute \src "libresoc.v:142775.7-142775.23" + wire $1\xer_ov_ok[0:0] + attribute \src "libresoc.v:143055.3-143073.6" + wire $1\xer_so$15$next[0:0]$7611 + attribute \src "libresoc.v:143055.3-143073.6" + wire $1\xer_so_ok$next[0:0]$7610 + attribute \src "libresoc.v:142793.7-142793.23" + wire $1\xer_so_ok[0:0] + attribute \src "libresoc.v:143017.3-143035.6" + wire $2\cr_a_ok$next[0:0]$7600 + attribute \src "libresoc.v:142962.3-142997.6" + wire width 64 $2\mul_op__imm_data__data$4$next[63:0]$7583 + attribute \src "libresoc.v:142962.3-142997.6" + wire $2\mul_op__imm_data__ok$5$next[0:0]$7584 + attribute \src "libresoc.v:142962.3-142997.6" + wire $2\mul_op__oe__oe$8$next[0:0]$7585 + attribute \src "libresoc.v:142962.3-142997.6" + wire $2\mul_op__oe__ok$9$next[0:0]$7586 + attribute \src "libresoc.v:142962.3-142997.6" + wire $2\mul_op__rc__ok$7$next[0:0]$7587 + attribute \src "libresoc.v:142962.3-142997.6" + wire $2\mul_op__rc__rc$6$next[0:0]$7588 + attribute \src "libresoc.v:142998.3-143016.6" + wire $2\o_ok$next[0:0]$7594 + attribute \src "libresoc.v:142931.3-142948.6" + wire $2\r_busy$next[0:0]$7554 + attribute \src "libresoc.v:143036.3-143054.6" + wire $2\xer_ov_ok$next[0:0]$7606 + attribute \src "libresoc.v:143055.3-143073.6" + wire $2\xer_so_ok$next[0:0]$7612 + attribute \src "libresoc.v:142800.18-142800.118" + wire $and$libresoc.v:142800$7513_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + wire \$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 44 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 output 38 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \cr_a$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \cr_a$73 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \cr_a$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 39 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_a_ok$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_a_ok$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_a_ok$74 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_a_ok$next + attribute \src "libresoc.v:141825.7-141825.15" + wire \initial + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \mul3_mul_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \mul3_mul_op__fn_unit$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \mul3_mul_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \mul3_mul_op__imm_data__data$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul3_mul_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul3_mul_op__imm_data__ok$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \mul3_mul_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \mul3_mul_op__insn$28 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \mul3_mul_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \mul3_mul_op__insn_type$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul3_mul_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul3_mul_op__is_32bit$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul3_mul_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul3_mul_op__is_signed$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul3_mul_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul3_mul_op__oe__oe$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul3_mul_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul3_mul_op__oe__ok$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul3_mul_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul3_mul_op__rc__ok$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul3_mul_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul3_mul_op__rc__rc$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul3_mul_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul3_mul_op__write_cr0$25 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \mul3_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \mul3_muxid$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" + wire \mul3_neg_res + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 129 \mul3_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \mul3_o$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \mul3_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \mul3_xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \mul3_xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \mul3_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \mul3_xer_so$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \mul3_xer_so_ok + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 6 \mul_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 output 25 \mul_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \mul_op__fn_unit$3$next + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \mul_op__fn_unit$60 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 7 \mul_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 26 \mul_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \mul_op__imm_data__data$4$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \mul_op__imm_data__data$61 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \mul_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 27 \mul_op__imm_data__ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__imm_data__ok$5$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__imm_data__ok$62 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 16 \mul_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 35 \mul_op__insn$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \mul_op__insn$13$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \mul_op__insn$70 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 5 \mul_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 24 \mul_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \mul_op__insn_type$2$next + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \mul_op__insn_type$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \mul_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 33 \mul_op__is_32bit$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__is_32bit$11$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__is_32bit$68 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 15 \mul_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 34 \mul_op__is_signed$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__is_signed$12$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__is_signed$69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 11 \mul_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__oe__oe$65 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 30 \mul_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__oe__oe$8$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \mul_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__oe__ok$66 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 31 \mul_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__oe__ok$9$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \mul_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__rc__ok$64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 29 \mul_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__rc__ok$7$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \mul_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 28 \mul_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__rc__rc$6$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__rc__rc$63 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \mul_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 32 \mul_op__write_cr0$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__write_cr0$10$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__write_cr0$67 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 4 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 23 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$1$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$58 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" + wire \n_i_rdy_data + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire input 22 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire output 21 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" + wire input 19 \neg_res + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" + wire input 20 \neg_res32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" + wire \neg_res32$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 129 input 17 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 36 \o$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \o$14$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \o$71 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 37 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \o_ok$72 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \o_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \output_cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \output_cr_a$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \output_cr_a_ok + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \output_mul_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \output_mul_op__fn_unit$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \output_mul_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \output_mul_op__imm_data__data$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_mul_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_mul_op__imm_data__ok$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \output_mul_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \output_mul_op__insn$43 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \output_mul_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \output_mul_op__insn_type$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_mul_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_mul_op__is_32bit$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_mul_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_mul_op__is_signed$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_mul_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_mul_op__oe__oe$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_mul_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_mul_op__oe__ok$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_mul_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_mul_op__rc__ok$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_mul_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_mul_op__rc__rc$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_mul_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_mul_op__write_cr0$40 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \output_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \output_muxid$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \output_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \output_o$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \output_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \output_o_ok$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \output_xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \output_xer_ov$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \output_xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \output_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \output_xer_so$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \output_xer_so_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire output 3 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" + wire \p_valid_i$55 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire \r_busy$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 output 40 \xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \xer_ov$75 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \xer_ov$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 41 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \xer_ov_ok$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \xer_ov_ok$76 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \xer_ov_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 18 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 42 \xer_so$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \xer_so$15$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \xer_so$77 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 43 \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \xer_so_ok$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \xer_so_ok$78 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \xer_so_ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + cell $and $and$libresoc.v:142800$7513 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i$55 + connect \B \p_ready_o + connect \Y $and$libresoc.v:142800$7513_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:142845.8-142881.4" + cell \mul3 \mul3 + connect \mul_op__fn_unit \mul3_mul_op__fn_unit + connect \mul_op__fn_unit$3 \mul3_mul_op__fn_unit$18 + connect \mul_op__imm_data__data \mul3_mul_op__imm_data__data + connect \mul_op__imm_data__data$4 \mul3_mul_op__imm_data__data$19 + connect \mul_op__imm_data__ok \mul3_mul_op__imm_data__ok + connect \mul_op__imm_data__ok$5 \mul3_mul_op__imm_data__ok$20 + connect \mul_op__insn \mul3_mul_op__insn + connect \mul_op__insn$13 \mul3_mul_op__insn$28 + connect \mul_op__insn_type \mul3_mul_op__insn_type + connect \mul_op__insn_type$2 \mul3_mul_op__insn_type$17 + connect \mul_op__is_32bit \mul3_mul_op__is_32bit + connect \mul_op__is_32bit$11 \mul3_mul_op__is_32bit$26 + connect \mul_op__is_signed \mul3_mul_op__is_signed + connect \mul_op__is_signed$12 \mul3_mul_op__is_signed$27 + connect \mul_op__oe__oe \mul3_mul_op__oe__oe + connect \mul_op__oe__oe$8 \mul3_mul_op__oe__oe$23 + connect \mul_op__oe__ok \mul3_mul_op__oe__ok + connect \mul_op__oe__ok$9 \mul3_mul_op__oe__ok$24 + connect \mul_op__rc__ok \mul3_mul_op__rc__ok + connect \mul_op__rc__ok$7 \mul3_mul_op__rc__ok$22 + connect \mul_op__rc__rc \mul3_mul_op__rc__rc + connect \mul_op__rc__rc$6 \mul3_mul_op__rc__rc$21 + connect \mul_op__write_cr0 \mul3_mul_op__write_cr0 + connect \mul_op__write_cr0$10 \mul3_mul_op__write_cr0$25 + connect \muxid \mul3_muxid + connect \muxid$1 \mul3_muxid$16 + connect \neg_res \mul3_neg_res + connect \o \mul3_o + connect \o$14 \mul3_o$29 + connect \o_ok \mul3_o_ok + connect \xer_ov \mul3_xer_ov + connect \xer_ov_ok \mul3_xer_ov_ok + connect \xer_so \mul3_xer_so + connect \xer_so$15 \mul3_xer_so$30 + connect \xer_so_ok \mul3_xer_so_ok + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:142882.10-142885.4" + cell \n$96 \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:142886.15-142926.4" + cell \output$97 \output + connect \cr_a \output_cr_a + connect \cr_a$16 \output_cr_a$46 + connect \cr_a_ok \output_cr_a_ok + connect \mul_op__fn_unit \output_mul_op__fn_unit + connect \mul_op__fn_unit$3 \output_mul_op__fn_unit$33 + connect \mul_op__imm_data__data \output_mul_op__imm_data__data + connect \mul_op__imm_data__data$4 \output_mul_op__imm_data__data$34 + connect \mul_op__imm_data__ok \output_mul_op__imm_data__ok + connect \mul_op__imm_data__ok$5 \output_mul_op__imm_data__ok$35 + connect \mul_op__insn \output_mul_op__insn + connect \mul_op__insn$13 \output_mul_op__insn$43 + connect \mul_op__insn_type \output_mul_op__insn_type + connect \mul_op__insn_type$2 \output_mul_op__insn_type$32 + connect \mul_op__is_32bit \output_mul_op__is_32bit + connect \mul_op__is_32bit$11 \output_mul_op__is_32bit$41 + connect \mul_op__is_signed \output_mul_op__is_signed + connect \mul_op__is_signed$12 \output_mul_op__is_signed$42 + connect \mul_op__oe__oe \output_mul_op__oe__oe + connect \mul_op__oe__oe$8 \output_mul_op__oe__oe$38 + connect \mul_op__oe__ok \output_mul_op__oe__ok + connect \mul_op__oe__ok$9 \output_mul_op__oe__ok$39 + connect \mul_op__rc__ok \output_mul_op__rc__ok + connect \mul_op__rc__ok$7 \output_mul_op__rc__ok$37 + connect \mul_op__rc__rc \output_mul_op__rc__rc + connect \mul_op__rc__rc$6 \output_mul_op__rc__rc$36 + connect \mul_op__write_cr0 \output_mul_op__write_cr0 + connect \mul_op__write_cr0$10 \output_mul_op__write_cr0$40 + connect \muxid \output_muxid + connect \muxid$1 \output_muxid$31 + connect \o \output_o + connect \o$14 \output_o$44 + connect \o_ok \output_o_ok + connect \o_ok$15 \output_o_ok$45 + connect \xer_ov \output_xer_ov + connect \xer_ov$17 \output_xer_ov$47 + connect \xer_ov_ok \output_xer_ov_ok + connect \xer_so \output_xer_so + connect \xer_so$18 \output_xer_so$48 + connect \xer_so_ok \output_xer_so_ok + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:142927.10-142930.4" + cell \p$95 \p + connect \p_ready_o \p_ready_o + connect \p_valid_i \p_valid_i + end + attribute \src "libresoc.v:141825.7-141825.20" + process $proc$libresoc.v:141825$7613 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:141834.13-141834.24" + process $proc$libresoc.v:141834$7614 + assign { } { } + assign $1\cr_a[3:0] 4'0000 + sync always + sync init + update \cr_a $1\cr_a[3:0] + end + attribute \src "libresoc.v:141843.7-141843.21" + process $proc$libresoc.v:141843$7615 + assign { } { } + assign $1\cr_a_ok[0:0] 1'0 + sync always + sync init + update \cr_a_ok $1\cr_a_ok[0:0] + end + attribute \src "libresoc.v:142126.14-142126.43" + process $proc$libresoc.v:142126$7616 + assign { } { } + assign $0\mul_op__fn_unit$3[11:0]$7617 12'000000000000 + sync always + sync init + update \mul_op__fn_unit$3 $0\mul_op__fn_unit$3[11:0]$7617 + end + attribute \src "libresoc.v:142148.14-142148.63" + process $proc$libresoc.v:142148$7618 + assign { } { } + assign $0\mul_op__imm_data__data$4[63:0]$7619 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \mul_op__imm_data__data$4 $0\mul_op__imm_data__data$4[63:0]$7619 + end + attribute \src "libresoc.v:142157.7-142157.38" + process $proc$libresoc.v:142157$7620 + assign { } { } + assign $0\mul_op__imm_data__ok$5[0:0]$7621 1'0 + sync always + sync init + update \mul_op__imm_data__ok$5 $0\mul_op__imm_data__ok$5[0:0]$7621 + end + attribute \src "libresoc.v:142166.14-142166.39" + process $proc$libresoc.v:142166$7622 + assign { } { } + assign $0\mul_op__insn$13[31:0]$7623 0 + sync always + sync init + update \mul_op__insn$13 $0\mul_op__insn$13[31:0]$7623 + end + attribute \src "libresoc.v:142323.13-142323.42" + process $proc$libresoc.v:142323$7624 + assign { } { } + assign $0\mul_op__insn_type$2[6:0]$7625 7'0000000 + sync always + sync init + update \mul_op__insn_type$2 $0\mul_op__insn_type$2[6:0]$7625 + end + attribute \src "libresoc.v:142406.7-142406.35" + process $proc$libresoc.v:142406$7626 + assign { } { } + assign $0\mul_op__is_32bit$11[0:0]$7627 1'0 + sync always + sync init + update \mul_op__is_32bit$11 $0\mul_op__is_32bit$11[0:0]$7627 + end + attribute \src "libresoc.v:142415.7-142415.36" + process $proc$libresoc.v:142415$7628 + assign { } { } + assign $0\mul_op__is_signed$12[0:0]$7629 1'0 + sync always + sync init + update \mul_op__is_signed$12 $0\mul_op__is_signed$12[0:0]$7629 + end + attribute \src "libresoc.v:142426.7-142426.32" + process $proc$libresoc.v:142426$7630 + assign { } { } + assign $0\mul_op__oe__oe$8[0:0]$7631 1'0 + sync always + sync init + update \mul_op__oe__oe$8 $0\mul_op__oe__oe$8[0:0]$7631 + end + attribute \src "libresoc.v:142435.7-142435.32" + process $proc$libresoc.v:142435$7632 + assign { } { } + assign $0\mul_op__oe__ok$9[0:0]$7633 1'0 + sync always + sync init + update \mul_op__oe__ok$9 $0\mul_op__oe__ok$9[0:0]$7633 + end + attribute \src "libresoc.v:142444.7-142444.32" + process $proc$libresoc.v:142444$7634 + assign { } { } + assign $0\mul_op__rc__ok$7[0:0]$7635 1'0 + sync always + sync init + update \mul_op__rc__ok$7 $0\mul_op__rc__ok$7[0:0]$7635 + end + attribute \src "libresoc.v:142451.7-142451.32" + process $proc$libresoc.v:142451$7636 + assign { } { } + assign $0\mul_op__rc__rc$6[0:0]$7637 1'0 + sync always + sync init + update \mul_op__rc__rc$6 $0\mul_op__rc__rc$6[0:0]$7637 + end + attribute \src "libresoc.v:142460.7-142460.36" + process $proc$libresoc.v:142460$7638 + assign { } { } + assign $0\mul_op__write_cr0$10[0:0]$7639 1'0 + sync always + sync init + update \mul_op__write_cr0$10 $0\mul_op__write_cr0$10[0:0]$7639 + end + attribute \src "libresoc.v:142469.13-142469.29" + process $proc$libresoc.v:142469$7640 + assign { } { } + assign $0\muxid$1[1:0]$7641 2'00 + sync always + sync init + update \muxid$1 $0\muxid$1[1:0]$7641 + end + attribute \src "libresoc.v:142490.14-142490.43" + process $proc$libresoc.v:142490$7642 + assign { } { } + assign $0\o$14[63:0]$7643 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \o$14 $0\o$14[63:0]$7643 + end + attribute \src "libresoc.v:142497.7-142497.18" + process $proc$libresoc.v:142497$7644 + assign { } { } + assign $1\o_ok[0:0] 1'0 + sync always + sync init + update \o_ok $1\o_ok[0:0] + end + attribute \src "libresoc.v:142763.7-142763.20" + process $proc$libresoc.v:142763$7645 + assign { } { } + assign $1\r_busy[0:0] 1'0 + sync always + sync init + update \r_busy $1\r_busy[0:0] + end + attribute \src "libresoc.v:142768.13-142768.26" + process $proc$libresoc.v:142768$7646 + assign { } { } + assign $1\xer_ov[1:0] 2'00 + sync always + sync init + update \xer_ov $1\xer_ov[1:0] + end + attribute \src "libresoc.v:142775.7-142775.23" + process $proc$libresoc.v:142775$7647 + assign { } { } + assign $1\xer_ov_ok[0:0] 1'0 + sync always + sync init + update \xer_ov_ok $1\xer_ov_ok[0:0] + end + attribute \src "libresoc.v:142786.7-142786.25" + process $proc$libresoc.v:142786$7648 + assign { } { } + assign $0\xer_so$15[0:0]$7649 1'0 + sync always + sync init + update \xer_so$15 $0\xer_so$15[0:0]$7649 + end + attribute \src "libresoc.v:142793.7-142793.23" + process $proc$libresoc.v:142793$7650 + assign { } { } + assign $1\xer_so_ok[0:0] 1'0 + sync always + sync init + update \xer_so_ok $1\xer_so_ok[0:0] + end + attribute \src "libresoc.v:142801.3-142802.37" + process $proc$libresoc.v:142801$7514 + assign { } { } + assign $0\xer_so$15[0:0]$7515 \xer_so$15$next + sync posedge \coresync_clk + update \xer_so$15 $0\xer_so$15[0:0]$7515 + end + attribute \src "libresoc.v:142803.3-142804.35" + process $proc$libresoc.v:142803$7516 + assign { } { } + assign $0\xer_so_ok[0:0] \xer_so_ok$next + sync posedge \coresync_clk + update \xer_so_ok $0\xer_so_ok[0:0] + end + attribute \src "libresoc.v:142805.3-142806.29" + process $proc$libresoc.v:142805$7517 + assign { } { } + assign $0\xer_ov[1:0] \xer_ov$next + sync posedge \coresync_clk + update \xer_ov $0\xer_ov[1:0] + end + attribute \src "libresoc.v:142807.3-142808.35" + process $proc$libresoc.v:142807$7518 + assign { } { } + assign $0\xer_ov_ok[0:0] \xer_ov_ok$next + sync posedge \coresync_clk + update \xer_ov_ok $0\xer_ov_ok[0:0] + end + attribute \src "libresoc.v:142809.3-142810.25" + process $proc$libresoc.v:142809$7519 + assign { } { } + assign $0\cr_a[3:0] \cr_a$next + sync posedge \coresync_clk + update \cr_a $0\cr_a[3:0] + end + attribute \src "libresoc.v:142811.3-142812.31" + process $proc$libresoc.v:142811$7520 + assign { } { } + assign $0\cr_a_ok[0:0] \cr_a_ok$next + sync posedge \coresync_clk + update \cr_a_ok $0\cr_a_ok[0:0] + end + attribute \src "libresoc.v:142813.3-142814.27" + process $proc$libresoc.v:142813$7521 + assign { } { } + assign $0\o$14[63:0]$7522 \o$14$next + sync posedge \coresync_clk + update \o$14 $0\o$14[63:0]$7522 + end + attribute \src "libresoc.v:142815.3-142816.25" + process $proc$libresoc.v:142815$7523 + assign { } { } + assign $0\o_ok[0:0] \o_ok$next + sync posedge \coresync_clk + update \o_ok $0\o_ok[0:0] + end + attribute \src "libresoc.v:142817.3-142818.57" + process $proc$libresoc.v:142817$7524 + assign { } { } + assign $0\mul_op__insn_type$2[6:0]$7525 \mul_op__insn_type$2$next + sync posedge \coresync_clk + update \mul_op__insn_type$2 $0\mul_op__insn_type$2[6:0]$7525 + end + attribute \src "libresoc.v:142819.3-142820.53" + process $proc$libresoc.v:142819$7526 + assign { } { } + assign $0\mul_op__fn_unit$3[11:0]$7527 \mul_op__fn_unit$3$next + sync posedge \coresync_clk + update \mul_op__fn_unit$3 $0\mul_op__fn_unit$3[11:0]$7527 + end + attribute \src "libresoc.v:142821.3-142822.67" + process $proc$libresoc.v:142821$7528 + assign { } { } + assign $0\mul_op__imm_data__data$4[63:0]$7529 \mul_op__imm_data__data$4$next + sync posedge \coresync_clk + update \mul_op__imm_data__data$4 $0\mul_op__imm_data__data$4[63:0]$7529 + end + attribute \src "libresoc.v:142823.3-142824.63" + process $proc$libresoc.v:142823$7530 + assign { } { } + assign $0\mul_op__imm_data__ok$5[0:0]$7531 \mul_op__imm_data__ok$5$next + sync posedge \coresync_clk + update \mul_op__imm_data__ok$5 $0\mul_op__imm_data__ok$5[0:0]$7531 + end + attribute \src "libresoc.v:142825.3-142826.51" + process $proc$libresoc.v:142825$7532 + assign { } { } + assign $0\mul_op__rc__rc$6[0:0]$7533 \mul_op__rc__rc$6$next + sync posedge \coresync_clk + update \mul_op__rc__rc$6 $0\mul_op__rc__rc$6[0:0]$7533 + end + attribute \src "libresoc.v:142827.3-142828.51" + process $proc$libresoc.v:142827$7534 + assign { } { } + assign $0\mul_op__rc__ok$7[0:0]$7535 \mul_op__rc__ok$7$next + sync posedge \coresync_clk + update \mul_op__rc__ok$7 $0\mul_op__rc__ok$7[0:0]$7535 + end + attribute \src "libresoc.v:142829.3-142830.51" + process $proc$libresoc.v:142829$7536 + assign { } { } + assign $0\mul_op__oe__oe$8[0:0]$7537 \mul_op__oe__oe$8$next + sync posedge \coresync_clk + update \mul_op__oe__oe$8 $0\mul_op__oe__oe$8[0:0]$7537 + end + attribute \src "libresoc.v:142831.3-142832.51" + process $proc$libresoc.v:142831$7538 + assign { } { } + assign $0\mul_op__oe__ok$9[0:0]$7539 \mul_op__oe__ok$9$next + sync posedge \coresync_clk + update \mul_op__oe__ok$9 $0\mul_op__oe__ok$9[0:0]$7539 + end + attribute \src "libresoc.v:142833.3-142834.59" + process $proc$libresoc.v:142833$7540 + assign { } { } + assign $0\mul_op__write_cr0$10[0:0]$7541 \mul_op__write_cr0$10$next + sync posedge \coresync_clk + update \mul_op__write_cr0$10 $0\mul_op__write_cr0$10[0:0]$7541 + end + attribute \src "libresoc.v:142835.3-142836.57" + process $proc$libresoc.v:142835$7542 + assign { } { } + assign $0\mul_op__is_32bit$11[0:0]$7543 \mul_op__is_32bit$11$next + sync posedge \coresync_clk + update \mul_op__is_32bit$11 $0\mul_op__is_32bit$11[0:0]$7543 + end + attribute \src "libresoc.v:142837.3-142838.59" + process $proc$libresoc.v:142837$7544 + assign { } { } + assign $0\mul_op__is_signed$12[0:0]$7545 \mul_op__is_signed$12$next + sync posedge \coresync_clk + update \mul_op__is_signed$12 $0\mul_op__is_signed$12[0:0]$7545 + end + attribute \src "libresoc.v:142839.3-142840.49" + process $proc$libresoc.v:142839$7546 + assign { } { } + assign $0\mul_op__insn$13[31:0]$7547 \mul_op__insn$13$next + sync posedge \coresync_clk + update \mul_op__insn$13 $0\mul_op__insn$13[31:0]$7547 + end + attribute \src "libresoc.v:142841.3-142842.33" + process $proc$libresoc.v:142841$7548 + assign { } { } + assign $0\muxid$1[1:0]$7549 \muxid$1$next + sync posedge \coresync_clk + update \muxid$1 $0\muxid$1[1:0]$7549 + end + attribute \src "libresoc.v:142843.3-142844.29" + process $proc$libresoc.v:142843$7550 + assign { } { } + assign $0\r_busy[0:0] \r_busy$next + sync posedge \coresync_clk + update \r_busy $0\r_busy[0:0] + end + attribute \src "libresoc.v:142931.3-142948.6" + process $proc$libresoc.v:142931$7551 + assign { } { } + assign { } { } + assign { } { } + assign $0\r_busy$next[0:0]$7552 $2\r_busy$next[0:0]$7554 + attribute \src "libresoc.v:142932.5-142932.29" + switch \initial + attribute \src "libresoc.v:142932.9-142932.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\r_busy$next[0:0]$7553 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\r_busy$next[0:0]$7553 1'0 + case + assign $1\r_busy$next[0:0]$7553 \r_busy + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r_busy$next[0:0]$7554 1'0 + case + assign $2\r_busy$next[0:0]$7554 $1\r_busy$next[0:0]$7553 + end + sync always + update \r_busy$next $0\r_busy$next[0:0]$7552 + end + attribute \src "libresoc.v:142949.3-142961.6" + process $proc$libresoc.v:142949$7555 + assign { } { } + assign { } { } + assign $0\muxid$1$next[1:0]$7556 $1\muxid$1$next[1:0]$7557 + attribute \src "libresoc.v:142950.5-142950.29" + switch \initial + attribute \src "libresoc.v:142950.9-142950.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\muxid$1$next[1:0]$7557 \muxid$58 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\muxid$1$next[1:0]$7557 \muxid$58 + case + assign $1\muxid$1$next[1:0]$7557 \muxid$1 + end + sync always + update \muxid$1$next $0\muxid$1$next[1:0]$7556 + end + attribute \src "libresoc.v:142962.3-142997.6" + process $proc$libresoc.v:142962$7558 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\mul_op__fn_unit$3$next[11:0]$7559 $1\mul_op__fn_unit$3$next[11:0]$7571 + assign { } { } + assign { } { } + assign $0\mul_op__insn$13$next[31:0]$7562 $1\mul_op__insn$13$next[31:0]$7574 + assign $0\mul_op__insn_type$2$next[6:0]$7563 $1\mul_op__insn_type$2$next[6:0]$7575 + assign $0\mul_op__is_32bit$11$next[0:0]$7564 $1\mul_op__is_32bit$11$next[0:0]$7576 + assign $0\mul_op__is_signed$12$next[0:0]$7565 $1\mul_op__is_signed$12$next[0:0]$7577 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\mul_op__write_cr0$10$next[0:0]$7570 $1\mul_op__write_cr0$10$next[0:0]$7582 + assign $0\mul_op__imm_data__data$4$next[63:0]$7560 $2\mul_op__imm_data__data$4$next[63:0]$7583 + assign $0\mul_op__imm_data__ok$5$next[0:0]$7561 $2\mul_op__imm_data__ok$5$next[0:0]$7584 + assign $0\mul_op__oe__oe$8$next[0:0]$7566 $2\mul_op__oe__oe$8$next[0:0]$7585 + assign $0\mul_op__oe__ok$9$next[0:0]$7567 $2\mul_op__oe__ok$9$next[0:0]$7586 + assign $0\mul_op__rc__ok$7$next[0:0]$7568 $2\mul_op__rc__ok$7$next[0:0]$7587 + assign $0\mul_op__rc__rc$6$next[0:0]$7569 $2\mul_op__rc__rc$6$next[0:0]$7588 + attribute \src "libresoc.v:142963.5-142963.29" + switch \initial + attribute \src "libresoc.v:142963.9-142963.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\mul_op__insn$13$next[31:0]$7574 $1\mul_op__is_signed$12$next[0:0]$7577 $1\mul_op__is_32bit$11$next[0:0]$7576 $1\mul_op__write_cr0$10$next[0:0]$7582 $1\mul_op__oe__ok$9$next[0:0]$7579 $1\mul_op__oe__oe$8$next[0:0]$7578 $1\mul_op__rc__ok$7$next[0:0]$7580 $1\mul_op__rc__rc$6$next[0:0]$7581 $1\mul_op__imm_data__ok$5$next[0:0]$7573 $1\mul_op__imm_data__data$4$next[63:0]$7572 $1\mul_op__fn_unit$3$next[11:0]$7571 $1\mul_op__insn_type$2$next[6:0]$7575 } { \mul_op__insn$70 \mul_op__is_signed$69 \mul_op__is_32bit$68 \mul_op__write_cr0$67 \mul_op__oe__ok$66 \mul_op__oe__oe$65 \mul_op__rc__ok$64 \mul_op__rc__rc$63 \mul_op__imm_data__ok$62 \mul_op__imm_data__data$61 \mul_op__fn_unit$60 \mul_op__insn_type$59 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\mul_op__insn$13$next[31:0]$7574 $1\mul_op__is_signed$12$next[0:0]$7577 $1\mul_op__is_32bit$11$next[0:0]$7576 $1\mul_op__write_cr0$10$next[0:0]$7582 $1\mul_op__oe__ok$9$next[0:0]$7579 $1\mul_op__oe__oe$8$next[0:0]$7578 $1\mul_op__rc__ok$7$next[0:0]$7580 $1\mul_op__rc__rc$6$next[0:0]$7581 $1\mul_op__imm_data__ok$5$next[0:0]$7573 $1\mul_op__imm_data__data$4$next[63:0]$7572 $1\mul_op__fn_unit$3$next[11:0]$7571 $1\mul_op__insn_type$2$next[6:0]$7575 } { \mul_op__insn$70 \mul_op__is_signed$69 \mul_op__is_32bit$68 \mul_op__write_cr0$67 \mul_op__oe__ok$66 \mul_op__oe__oe$65 \mul_op__rc__ok$64 \mul_op__rc__rc$63 \mul_op__imm_data__ok$62 \mul_op__imm_data__data$61 \mul_op__fn_unit$60 \mul_op__insn_type$59 } + case + assign $1\mul_op__fn_unit$3$next[11:0]$7571 \mul_op__fn_unit$3 + assign $1\mul_op__imm_data__data$4$next[63:0]$7572 \mul_op__imm_data__data$4 + assign $1\mul_op__imm_data__ok$5$next[0:0]$7573 \mul_op__imm_data__ok$5 + assign $1\mul_op__insn$13$next[31:0]$7574 \mul_op__insn$13 + assign $1\mul_op__insn_type$2$next[6:0]$7575 \mul_op__insn_type$2 + assign $1\mul_op__is_32bit$11$next[0:0]$7576 \mul_op__is_32bit$11 + assign $1\mul_op__is_signed$12$next[0:0]$7577 \mul_op__is_signed$12 + assign $1\mul_op__oe__oe$8$next[0:0]$7578 \mul_op__oe__oe$8 + assign $1\mul_op__oe__ok$9$next[0:0]$7579 \mul_op__oe__ok$9 + assign $1\mul_op__rc__ok$7$next[0:0]$7580 \mul_op__rc__ok$7 + assign $1\mul_op__rc__rc$6$next[0:0]$7581 \mul_op__rc__rc$6 + assign $1\mul_op__write_cr0$10$next[0:0]$7582 \mul_op__write_cr0$10 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $2\mul_op__imm_data__data$4$next[63:0]$7583 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\mul_op__imm_data__ok$5$next[0:0]$7584 1'0 + assign $2\mul_op__rc__rc$6$next[0:0]$7588 1'0 + assign $2\mul_op__rc__ok$7$next[0:0]$7587 1'0 + assign $2\mul_op__oe__oe$8$next[0:0]$7585 1'0 + assign $2\mul_op__oe__ok$9$next[0:0]$7586 1'0 + case + assign $2\mul_op__imm_data__data$4$next[63:0]$7583 $1\mul_op__imm_data__data$4$next[63:0]$7572 + assign $2\mul_op__imm_data__ok$5$next[0:0]$7584 $1\mul_op__imm_data__ok$5$next[0:0]$7573 + assign $2\mul_op__oe__oe$8$next[0:0]$7585 $1\mul_op__oe__oe$8$next[0:0]$7578 + assign $2\mul_op__oe__ok$9$next[0:0]$7586 $1\mul_op__oe__ok$9$next[0:0]$7579 + assign $2\mul_op__rc__ok$7$next[0:0]$7587 $1\mul_op__rc__ok$7$next[0:0]$7580 + assign $2\mul_op__rc__rc$6$next[0:0]$7588 $1\mul_op__rc__rc$6$next[0:0]$7581 + end + sync always + update \mul_op__fn_unit$3$next $0\mul_op__fn_unit$3$next[11:0]$7559 + update \mul_op__imm_data__data$4$next $0\mul_op__imm_data__data$4$next[63:0]$7560 + update \mul_op__imm_data__ok$5$next $0\mul_op__imm_data__ok$5$next[0:0]$7561 + update \mul_op__insn$13$next $0\mul_op__insn$13$next[31:0]$7562 + update \mul_op__insn_type$2$next $0\mul_op__insn_type$2$next[6:0]$7563 + update \mul_op__is_32bit$11$next $0\mul_op__is_32bit$11$next[0:0]$7564 + update \mul_op__is_signed$12$next $0\mul_op__is_signed$12$next[0:0]$7565 + update \mul_op__oe__oe$8$next $0\mul_op__oe__oe$8$next[0:0]$7566 + update \mul_op__oe__ok$9$next $0\mul_op__oe__ok$9$next[0:0]$7567 + update \mul_op__rc__ok$7$next $0\mul_op__rc__ok$7$next[0:0]$7568 + update \mul_op__rc__rc$6$next $0\mul_op__rc__rc$6$next[0:0]$7569 + update \mul_op__write_cr0$10$next $0\mul_op__write_cr0$10$next[0:0]$7570 + end + attribute \src "libresoc.v:142998.3-143016.6" + process $proc$libresoc.v:142998$7589 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\o$14$next[63:0]$7591 $1\o$14$next[63:0]$7593 + assign $0\o_ok$next[0:0]$7590 $2\o_ok$next[0:0]$7594 + attribute \src "libresoc.v:142999.5-142999.29" + switch \initial + attribute \src "libresoc.v:142999.9-142999.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\o_ok$next[0:0]$7592 $1\o$14$next[63:0]$7593 } { \o_ok$72 \o$71 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\o_ok$next[0:0]$7592 $1\o$14$next[63:0]$7593 } { \o_ok$72 \o$71 } + case + assign $1\o_ok$next[0:0]$7592 \o_ok + assign $1\o$14$next[63:0]$7593 \o$14 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\o_ok$next[0:0]$7594 1'0 + case + assign $2\o_ok$next[0:0]$7594 $1\o_ok$next[0:0]$7592 + end + sync always + update \o_ok$next $0\o_ok$next[0:0]$7590 + update \o$14$next $0\o$14$next[63:0]$7591 + end + attribute \src "libresoc.v:143017.3-143035.6" + process $proc$libresoc.v:143017$7595 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\cr_a$next[3:0]$7596 $1\cr_a$next[3:0]$7598 + assign { } { } + assign $0\cr_a_ok$next[0:0]$7597 $2\cr_a_ok$next[0:0]$7600 + attribute \src "libresoc.v:143018.5-143018.29" + switch \initial + attribute \src "libresoc.v:143018.9-143018.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\cr_a_ok$next[0:0]$7599 $1\cr_a$next[3:0]$7598 } { \cr_a_ok$74 \cr_a$73 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\cr_a_ok$next[0:0]$7599 $1\cr_a$next[3:0]$7598 } { \cr_a_ok$74 \cr_a$73 } + case + assign $1\cr_a$next[3:0]$7598 \cr_a + assign $1\cr_a_ok$next[0:0]$7599 \cr_a_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_a_ok$next[0:0]$7600 1'0 + case + assign $2\cr_a_ok$next[0:0]$7600 $1\cr_a_ok$next[0:0]$7599 + end + sync always + update \cr_a$next $0\cr_a$next[3:0]$7596 + update \cr_a_ok$next $0\cr_a_ok$next[0:0]$7597 + end + attribute \src "libresoc.v:143036.3-143054.6" + process $proc$libresoc.v:143036$7601 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\xer_ov$next[1:0]$7602 $1\xer_ov$next[1:0]$7604 + assign { } { } + assign $0\xer_ov_ok$next[0:0]$7603 $2\xer_ov_ok$next[0:0]$7606 + attribute \src "libresoc.v:143037.5-143037.29" + switch \initial + attribute \src "libresoc.v:143037.9-143037.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\xer_ov_ok$next[0:0]$7605 $1\xer_ov$next[1:0]$7604 } { \xer_ov_ok$76 \xer_ov$75 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\xer_ov_ok$next[0:0]$7605 $1\xer_ov$next[1:0]$7604 } { \xer_ov_ok$76 \xer_ov$75 } + case + assign $1\xer_ov$next[1:0]$7604 \xer_ov + assign $1\xer_ov_ok$next[0:0]$7605 \xer_ov_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\xer_ov_ok$next[0:0]$7606 1'0 + case + assign $2\xer_ov_ok$next[0:0]$7606 $1\xer_ov_ok$next[0:0]$7605 + end + sync always + update \xer_ov$next $0\xer_ov$next[1:0]$7602 + update \xer_ov_ok$next $0\xer_ov_ok$next[0:0]$7603 + end + attribute \src "libresoc.v:143055.3-143073.6" + process $proc$libresoc.v:143055$7607 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\xer_so$15$next[0:0]$7609 $1\xer_so$15$next[0:0]$7611 + assign $0\xer_so_ok$next[0:0]$7608 $2\xer_so_ok$next[0:0]$7612 + attribute \src "libresoc.v:143056.5-143056.29" + switch \initial + attribute \src "libresoc.v:143056.9-143056.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\xer_so_ok$next[0:0]$7610 $1\xer_so$15$next[0:0]$7611 } { \xer_so_ok$78 \xer_so$77 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\xer_so_ok$next[0:0]$7610 $1\xer_so$15$next[0:0]$7611 } { \xer_so_ok$78 \xer_so$77 } + case + assign $1\xer_so_ok$next[0:0]$7610 \xer_so_ok + assign $1\xer_so$15$next[0:0]$7611 \xer_so$15 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\xer_so_ok$next[0:0]$7612 1'0 + case + assign $2\xer_so_ok$next[0:0]$7612 $1\xer_so_ok$next[0:0]$7610 + end + sync always + update \xer_so_ok$next $0\xer_so_ok$next[0:0]$7608 + update \xer_so$15$next $0\xer_so$15$next[0:0]$7609 + end + connect \$56 $and$libresoc.v:142800$7513_Y + connect \cr_a$51 4'0000 + connect \cr_a_ok$52 1'0 + connect \p_ready_o \n_i_rdy_data + connect \n_valid_o \r_busy + connect { \xer_so_ok$78 \xer_so$77 } { \output_xer_so_ok \output_xer_so$48 } + connect { \xer_ov_ok$76 \xer_ov$75 } { \output_xer_ov_ok \output_xer_ov$47 } + connect { \cr_a_ok$74 \cr_a$73 } { \output_cr_a_ok \output_cr_a$46 } + connect { \o_ok$72 \o$71 } { \output_o_ok$45 \output_o$44 } + connect { \mul_op__insn$70 \mul_op__is_signed$69 \mul_op__is_32bit$68 \mul_op__write_cr0$67 \mul_op__oe__ok$66 \mul_op__oe__oe$65 \mul_op__rc__ok$64 \mul_op__rc__rc$63 \mul_op__imm_data__ok$62 \mul_op__imm_data__data$61 \mul_op__fn_unit$60 \mul_op__insn_type$59 } { \output_mul_op__insn$43 \output_mul_op__is_signed$42 \output_mul_op__is_32bit$41 \output_mul_op__write_cr0$40 \output_mul_op__oe__ok$39 \output_mul_op__oe__oe$38 \output_mul_op__rc__ok$37 \output_mul_op__rc__rc$36 \output_mul_op__imm_data__ok$35 \output_mul_op__imm_data__data$34 \output_mul_op__fn_unit$33 \output_mul_op__insn_type$32 } + connect \muxid$58 \output_muxid$31 + connect \p_valid_i_p_ready_o \$56 + connect \n_i_rdy_data \n_ready_i + connect \p_valid_i$55 \p_valid_i + connect { \xer_so_ok$54 \output_xer_so } { \mul3_xer_so_ok \mul3_xer_so$30 } + connect { \xer_ov_ok$53 \output_xer_ov } { \mul3_xer_ov_ok \mul3_xer_ov } + connect { \cr_a_ok$50 \output_cr_a } 5'00000 + connect { \output_o_ok \output_o } { \mul3_o_ok \mul3_o$29 } + connect { \output_mul_op__insn \output_mul_op__is_signed \output_mul_op__is_32bit \output_mul_op__write_cr0 \output_mul_op__oe__ok \output_mul_op__oe__oe \output_mul_op__rc__ok \output_mul_op__rc__rc \output_mul_op__imm_data__ok \output_mul_op__imm_data__data \output_mul_op__fn_unit \output_mul_op__insn_type } { \mul3_mul_op__insn$28 \mul3_mul_op__is_signed$27 \mul3_mul_op__is_32bit$26 \mul3_mul_op__write_cr0$25 \mul3_mul_op__oe__ok$24 \mul3_mul_op__oe__oe$23 \mul3_mul_op__rc__ok$22 \mul3_mul_op__rc__rc$21 \mul3_mul_op__imm_data__ok$20 \mul3_mul_op__imm_data__data$19 \mul3_mul_op__fn_unit$18 \mul3_mul_op__insn_type$17 } + connect \output_muxid \mul3_muxid$16 + connect \neg_res32$49 \neg_res32 + connect \mul3_neg_res \neg_res + connect \mul3_xer_so \xer_so + connect \mul3_o \o + connect { \mul3_mul_op__insn \mul3_mul_op__is_signed \mul3_mul_op__is_32bit \mul3_mul_op__write_cr0 \mul3_mul_op__oe__ok \mul3_mul_op__oe__oe \mul3_mul_op__rc__ok \mul3_mul_op__rc__rc \mul3_mul_op__imm_data__ok \mul3_mul_op__imm_data__data \mul3_mul_op__fn_unit \mul3_mul_op__insn_type } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__oe__ok \mul_op__oe__oe \mul_op__rc__ok \mul_op__rc__rc \mul_op__imm_data__ok \mul_op__imm_data__data \mul_op__fn_unit \mul_op__insn_type } + connect \mul3_muxid \muxid +end +attribute \src "libresoc.v:143103.1-143114.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alu_alu0.n" +attribute \generator "nMigen" +module \n + attribute \src "libresoc.v:143112.17-143112.111" + wire $and$libresoc.v:143112$7651_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire input 1 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire input 2 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" + wire \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + cell $and $and$libresoc.v:143112$7651 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $and$libresoc.v:143112$7651_Y + end + connect \$1 $and$libresoc.v:143112$7651_Y + connect \trigger \$1 +end +attribute \src "libresoc.v:143118.1-143129.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.n" +attribute \generator "nMigen" +module \n$106 + attribute \src "libresoc.v:143127.17-143127.111" + wire $and$libresoc.v:143127$7652_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire input 1 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire input 2 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" + wire \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + cell $and $and$libresoc.v:143127$7652 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $and$libresoc.v:143127$7652_Y + end + connect \$1 $and$libresoc.v:143127$7652_Y + connect \trigger \$1 +end +attribute \src "libresoc.v:143133.1-143144.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.pipe1.n" +attribute \generator "nMigen" +module \n$109 + attribute \src "libresoc.v:143142.17-143142.111" + wire $and$libresoc.v:143142$7653_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire input 1 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire input 2 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" + wire \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + cell $and $and$libresoc.v:143142$7653 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $and$libresoc.v:143142$7653_Y + end + connect \$1 $and$libresoc.v:143142$7653_Y + connect \trigger \$1 +end +attribute \src "libresoc.v:143148.1-143159.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.pipe2.n" +attribute \generator "nMigen" +module \n$114 + attribute \src "libresoc.v:143157.17-143157.111" + wire $and$libresoc.v:143157$7654_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire input 1 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire input 2 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" + wire \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + cell $and $and$libresoc.v:143157$7654 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $and$libresoc.v:143157$7654_Y + end + connect \$1 $and$libresoc.v:143157$7654_Y + connect \trigger \$1 +end +attribute \src "libresoc.v:143163.1-143174.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.alu_branch0.n" +attribute \generator "nMigen" +module \n$18 + attribute \src "libresoc.v:143172.17-143172.111" + wire $and$libresoc.v:143172$7655_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire input 1 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire input 2 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" + wire \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + cell $and $and$libresoc.v:143172$7655 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $and$libresoc.v:143172$7655_Y + end + connect \$1 $and$libresoc.v:143172$7655_Y + connect \trigger \$1 +end +attribute \src "libresoc.v:143178.1-143189.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alu_alu0.pipe1.n" +attribute \generator "nMigen" +module \n$2 + attribute \src "libresoc.v:143187.17-143187.111" + wire $and$libresoc.v:143187$7656_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire input 1 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire input 2 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" + wire \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + cell $and $and$libresoc.v:143187$7656 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $and$libresoc.v:143187$7656_Y + end + connect \$1 $and$libresoc.v:143187$7656_Y + connect \trigger \$1 +end +attribute \src "libresoc.v:143193.1-143204.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.alu_branch0.pipe.n" +attribute \generator "nMigen" +module \n$21 + attribute \src "libresoc.v:143202.17-143202.111" + wire $and$libresoc.v:143202$7657_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire input 1 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire input 2 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" + wire \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + cell $and $and$libresoc.v:143202$7657 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $and$libresoc.v:143202$7657_Y + end + connect \$1 $and$libresoc.v:143202$7657_Y + connect \trigger \$1 +end +attribute \src "libresoc.v:143208.1-143219.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.alu_trap0.n" +attribute \generator "nMigen" +module \n$31 + attribute \src "libresoc.v:143217.17-143217.111" + wire $and$libresoc.v:143217$7658_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire input 1 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire input 2 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" + wire \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + cell $and $and$libresoc.v:143217$7658 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $and$libresoc.v:143217$7658_Y + end + connect \$1 $and$libresoc.v:143217$7658_Y + connect \trigger \$1 +end +attribute \src "libresoc.v:143223.1-143234.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.alu_trap0.pipe.n" +attribute \generator "nMigen" +module \n$34 + attribute \src "libresoc.v:143232.17-143232.111" + wire $and$libresoc.v:143232$7659_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire input 1 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire input 2 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" + wire \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + cell $and $and$libresoc.v:143232$7659 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $and$libresoc.v:143232$7659_Y + end + connect \$1 $and$libresoc.v:143232$7659_Y + connect \trigger \$1 +end +attribute \src "libresoc.v:143238.1-143249.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alu_alu0.pipe2.n" +attribute \generator "nMigen" +module \n$4 + attribute \src "libresoc.v:143247.17-143247.111" + wire $and$libresoc.v:143247$7660_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire input 1 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire input 2 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" + wire \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + cell $and $and$libresoc.v:143247$7660 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $and$libresoc.v:143247$7660_Y + end + connect \$1 $and$libresoc.v:143247$7660_Y + connect \trigger \$1 +end +attribute \src "libresoc.v:143253.1-143264.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_logical0.n" +attribute \generator "nMigen" +module \n$44 + attribute \src "libresoc.v:143262.17-143262.111" + wire $and$libresoc.v:143262$7661_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire input 1 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire input 2 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" + wire \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + cell $and $and$libresoc.v:143262$7661 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $and$libresoc.v:143262$7661_Y + end + connect \$1 $and$libresoc.v:143262$7661_Y + connect \trigger \$1 +end +attribute \src "libresoc.v:143268.1-143279.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_logical0.logical_pipe1.n" +attribute \generator "nMigen" +module \n$46 + attribute \src "libresoc.v:143277.17-143277.111" + wire $and$libresoc.v:143277$7662_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire input 1 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire input 2 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" + wire \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + cell $and $and$libresoc.v:143277$7662 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $and$libresoc.v:143277$7662_Y + end + connect \$1 $and$libresoc.v:143277$7662_Y + connect \trigger \$1 +end +attribute \src "libresoc.v:143283.1-143294.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_logical0.logical_pipe2.n" +attribute \generator "nMigen" +module \n$50 + attribute \src "libresoc.v:143292.17-143292.111" + wire $and$libresoc.v:143292$7663_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire input 1 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire input 2 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" + wire \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + cell $and $and$libresoc.v:143292$7663 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $and$libresoc.v:143292$7663_Y + end + connect \$1 $and$libresoc.v:143292$7663_Y + connect \trigger \$1 +end +attribute \src "libresoc.v:143298.1-143309.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.alu_cr0.n" +attribute \generator "nMigen" +module \n$6 + attribute \src "libresoc.v:143307.17-143307.111" + wire $and$libresoc.v:143307$7664_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire input 1 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire input 2 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" + wire \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + cell $and $and$libresoc.v:143307$7664 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $and$libresoc.v:143307$7664_Y + end + connect \$1 $and$libresoc.v:143307$7664_Y + connect \trigger \$1 +end +attribute \src "libresoc.v:143313.1-143324.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.alu_spr0.n" +attribute \generator "nMigen" +module \n$60 + attribute \src "libresoc.v:143322.17-143322.111" + wire $and$libresoc.v:143322$7665_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire input 1 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire input 2 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" + wire \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + cell $and $and$libresoc.v:143322$7665 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $and$libresoc.v:143322$7665_Y + end + connect \$1 $and$libresoc.v:143322$7665_Y + connect \trigger \$1 +end +attribute \src "libresoc.v:143328.1-143339.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.alu_spr0.pipe.n" +attribute \generator "nMigen" +module \n$63 + attribute \src "libresoc.v:143337.17-143337.111" + wire $and$libresoc.v:143337$7666_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire input 1 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire input 2 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" + wire \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + cell $and $and$libresoc.v:143337$7666 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $and$libresoc.v:143337$7666_Y + end + connect \$1 $and$libresoc.v:143337$7666_Y + connect \trigger \$1 +end +attribute \src "libresoc.v:143343.1-143354.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.n" +attribute \generator "nMigen" +module \n$72 + attribute \src "libresoc.v:143352.17-143352.111" + wire $and$libresoc.v:143352$7667_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire input 1 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire input 2 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" + wire \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + cell $and $and$libresoc.v:143352$7667 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $and$libresoc.v:143352$7667_Y + end + connect \$1 $and$libresoc.v:143352$7667_Y + connect \trigger \$1 +end +attribute \src "libresoc.v:143358.1-143369.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_start.n" +attribute \generator "nMigen" +module \n$74 + attribute \src "libresoc.v:143367.17-143367.111" + wire $and$libresoc.v:143367$7668_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire input 1 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire input 2 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" + wire \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + cell $and $and$libresoc.v:143367$7668 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $and$libresoc.v:143367$7668_Y + end + connect \$1 $and$libresoc.v:143367$7668_Y + connect \trigger \$1 +end +attribute \src "libresoc.v:143373.1-143384.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_0.n" +attribute \generator "nMigen" +module \n$77 + attribute \src "libresoc.v:143382.17-143382.111" + wire $and$libresoc.v:143382$7669_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire input 1 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire input 2 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" + wire \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + cell $and $and$libresoc.v:143382$7669 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $and$libresoc.v:143382$7669_Y + end + connect \$1 $and$libresoc.v:143382$7669_Y + connect \trigger \$1 +end +attribute \src "libresoc.v:143388.1-143399.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_end.n" +attribute \generator "nMigen" +module \n$79 + attribute \src "libresoc.v:143397.17-143397.111" + wire $and$libresoc.v:143397$7670_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire input 1 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire input 2 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" + wire \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + cell $and $and$libresoc.v:143397$7670 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $and$libresoc.v:143397$7670_Y + end + connect \$1 $and$libresoc.v:143397$7670_Y + connect \trigger \$1 +end +attribute \src "libresoc.v:143403.1-143414.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.alu_cr0.pipe.n" +attribute \generator "nMigen" +module \n$8 + attribute \src "libresoc.v:143412.17-143412.111" + wire $and$libresoc.v:143412$7671_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire input 1 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire input 2 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" + wire \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + cell $and $and$libresoc.v:143412$7671 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $and$libresoc.v:143412$7671_Y + end + connect \$1 $and$libresoc.v:143412$7671_Y + connect \trigger \$1 +end +attribute \src "libresoc.v:143418.1-143429.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.n" +attribute \generator "nMigen" +module \n$89 + attribute \src "libresoc.v:143427.17-143427.111" + wire $and$libresoc.v:143427$7672_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire input 1 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire input 2 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" + wire \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + cell $and $and$libresoc.v:143427$7672 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $and$libresoc.v:143427$7672_Y + end + connect \$1 $and$libresoc.v:143427$7672_Y + connect \trigger \$1 +end +attribute \src "libresoc.v:143433.1-143444.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe1.n" +attribute \generator "nMigen" +module \n$91 + attribute \src "libresoc.v:143442.17-143442.111" + wire $and$libresoc.v:143442$7673_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire input 1 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire input 2 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" + wire \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + cell $and $and$libresoc.v:143442$7673 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $and$libresoc.v:143442$7673_Y + end + connect \$1 $and$libresoc.v:143442$7673_Y + connect \trigger \$1 +end +attribute \src "libresoc.v:143448.1-143459.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe2.n" +attribute \generator "nMigen" +module \n$94 + attribute \src "libresoc.v:143457.17-143457.111" + wire $and$libresoc.v:143457$7674_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire input 1 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire input 2 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" + wire \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + cell $and $and$libresoc.v:143457$7674 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $and$libresoc.v:143457$7674_Y + end + connect \$1 $and$libresoc.v:143457$7674_Y + connect \trigger \$1 +end +attribute \src "libresoc.v:143463.1-143474.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe3.n" +attribute \generator "nMigen" +module \n$96 + attribute \src "libresoc.v:143472.17-143472.111" + wire $and$libresoc.v:143472$7675_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire input 1 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire input 2 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" + wire \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + cell $and $and$libresoc.v:143472$7675 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $and$libresoc.v:143472$7675_Y + end + connect \$1 $and$libresoc.v:143472$7675_Y + connect \trigger \$1 +end +attribute \src "libresoc.v:143478.1-143536.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.opc_l" +attribute \generator "nMigen" +module \opc_l + attribute \src "libresoc.v:143479.7-143479.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:143524.3-143532.6" + wire $0\q_int$next[0:0]$7686 + attribute \src "libresoc.v:143522.3-143523.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:143524.3-143532.6" + wire $1\q_int$next[0:0]$7687 + attribute \src "libresoc.v:143501.7-143501.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:143514.17-143514.96" + wire $and$libresoc.v:143514$7676_Y + attribute \src "libresoc.v:143519.17-143519.96" + wire $and$libresoc.v:143519$7681_Y + attribute \src "libresoc.v:143516.18-143516.93" + wire $not$libresoc.v:143516$7678_Y + attribute \src "libresoc.v:143518.17-143518.92" + wire $not$libresoc.v:143518$7680_Y + attribute \src "libresoc.v:143521.17-143521.92" + wire $not$libresoc.v:143521$7683_Y + attribute \src "libresoc.v:143515.18-143515.98" + wire $or$libresoc.v:143515$7677_Y + attribute \src "libresoc.v:143517.18-143517.99" + wire $or$libresoc.v:143517$7679_Y + attribute \src "libresoc.v:143520.17-143520.97" + wire $or$libresoc.v:143520$7682_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 1 \coresync_rst + attribute \src "libresoc.v:143479.7-143479.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 4 \q_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 2 \s_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$libresoc.v:143514$7676 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:143514$7676_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:143519$7681 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:143519$7681_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:143516$7678 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_opc + connect \Y $not$libresoc.v:143516$7678_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:143518$7680 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_opc + connect \Y $not$libresoc.v:143518$7680_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:143521$7683 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_opc + connect \Y $not$libresoc.v:143521$7683_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:143515$7677 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_opc + connect \Y $or$libresoc.v:143515$7677_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:143517$7679 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_opc + connect \B \q_int + connect \Y $or$libresoc.v:143517$7679_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:143520$7682 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_opc + connect \Y $or$libresoc.v:143520$7682_Y + end + attribute \src "libresoc.v:143479.7-143479.20" + process $proc$libresoc.v:143479$7688 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:143501.7-143501.19" + process $proc$libresoc.v:143501$7689 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:143522.3-143523.27" + process $proc$libresoc.v:143522$7684 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:143524.3-143532.6" + process $proc$libresoc.v:143524$7685 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$7686 $1\q_int$next[0:0]$7687 + attribute \src "libresoc.v:143525.5-143525.29" + switch \initial + attribute \src "libresoc.v:143525.9-143525.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$7687 1'0 + case + assign $1\q_int$next[0:0]$7687 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$7686 + end + connect \$9 $and$libresoc.v:143514$7676_Y + connect \$11 $or$libresoc.v:143515$7677_Y + connect \$13 $not$libresoc.v:143516$7678_Y + connect \$15 $or$libresoc.v:143517$7679_Y + connect \$1 $not$libresoc.v:143518$7680_Y + connect \$3 $and$libresoc.v:143519$7681_Y + connect \$5 $or$libresoc.v:143520$7682_Y + connect \$7 $not$libresoc.v:143521$7683_Y + connect \qlq_opc \$15 + connect \qn_opc \$13 + connect \q_opc \$11 +end +attribute \src "libresoc.v:143540.1-143598.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.opc_l" +attribute \generator "nMigen" +module \opc_l$11 + attribute \src "libresoc.v:143541.7-143541.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:143586.3-143594.6" + wire $0\q_int$next[0:0]$7700 + attribute \src "libresoc.v:143584.3-143585.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:143586.3-143594.6" + wire $1\q_int$next[0:0]$7701 + attribute \src "libresoc.v:143563.7-143563.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:143576.17-143576.96" + wire $and$libresoc.v:143576$7690_Y + attribute \src "libresoc.v:143581.17-143581.96" + wire $and$libresoc.v:143581$7695_Y + attribute \src "libresoc.v:143578.18-143578.93" + wire $not$libresoc.v:143578$7692_Y + attribute \src "libresoc.v:143580.17-143580.92" + wire $not$libresoc.v:143580$7694_Y + attribute \src "libresoc.v:143583.17-143583.92" + wire $not$libresoc.v:143583$7697_Y + attribute \src "libresoc.v:143577.18-143577.98" + wire $or$libresoc.v:143577$7691_Y + attribute \src "libresoc.v:143579.18-143579.99" + wire $or$libresoc.v:143579$7693_Y + attribute \src "libresoc.v:143582.17-143582.97" + wire $or$libresoc.v:143582$7696_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 1 \coresync_rst + attribute \src "libresoc.v:143541.7-143541.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 4 \q_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 2 \s_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$libresoc.v:143576$7690 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:143576$7690_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:143581$7695 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:143581$7695_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:143578$7692 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_opc + connect \Y $not$libresoc.v:143578$7692_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:143580$7694 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_opc + connect \Y $not$libresoc.v:143580$7694_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:143583$7697 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_opc + connect \Y $not$libresoc.v:143583$7697_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:143577$7691 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_opc + connect \Y $or$libresoc.v:143577$7691_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:143579$7693 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_opc + connect \B \q_int + connect \Y $or$libresoc.v:143579$7693_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:143582$7696 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_opc + connect \Y $or$libresoc.v:143582$7696_Y + end + attribute \src "libresoc.v:143541.7-143541.20" + process $proc$libresoc.v:143541$7702 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:143563.7-143563.19" + process $proc$libresoc.v:143563$7703 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:143584.3-143585.27" + process $proc$libresoc.v:143584$7698 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:143586.3-143594.6" + process $proc$libresoc.v:143586$7699 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$7700 $1\q_int$next[0:0]$7701 + attribute \src "libresoc.v:143587.5-143587.29" + switch \initial + attribute \src "libresoc.v:143587.9-143587.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$7701 1'0 + case + assign $1\q_int$next[0:0]$7701 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$7700 + end + connect \$9 $and$libresoc.v:143576$7690_Y + connect \$11 $or$libresoc.v:143577$7691_Y + connect \$13 $not$libresoc.v:143578$7692_Y + connect \$15 $or$libresoc.v:143579$7693_Y + connect \$1 $not$libresoc.v:143580$7694_Y + connect \$3 $and$libresoc.v:143581$7695_Y + connect \$5 $or$libresoc.v:143582$7696_Y + connect \$7 $not$libresoc.v:143583$7697_Y + connect \qlq_opc \$15 + connect \qn_opc \$13 + connect \q_opc \$11 +end +attribute \src "libresoc.v:143602.1-143660.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.opc_l" +attribute \generator "nMigen" +module \opc_l$117 + attribute \src "libresoc.v:143603.7-143603.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:143648.3-143656.6" + wire $0\q_int$next[0:0]$7714 + attribute \src "libresoc.v:143646.3-143647.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:143648.3-143656.6" + wire $1\q_int$next[0:0]$7715 + attribute \src "libresoc.v:143625.7-143625.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:143638.17-143638.96" + wire $and$libresoc.v:143638$7704_Y + attribute \src "libresoc.v:143643.17-143643.96" + wire $and$libresoc.v:143643$7709_Y + attribute \src "libresoc.v:143640.18-143640.93" + wire $not$libresoc.v:143640$7706_Y + attribute \src "libresoc.v:143642.17-143642.92" + wire $not$libresoc.v:143642$7708_Y + attribute \src "libresoc.v:143645.17-143645.92" + wire $not$libresoc.v:143645$7711_Y + attribute \src "libresoc.v:143639.18-143639.98" + wire $or$libresoc.v:143639$7705_Y + attribute \src "libresoc.v:143641.18-143641.99" + wire $or$libresoc.v:143641$7707_Y + attribute \src "libresoc.v:143644.17-143644.97" + wire $or$libresoc.v:143644$7710_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 1 \coresync_rst + attribute \src "libresoc.v:143603.7-143603.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 4 \q_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 2 \s_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$libresoc.v:143638$7704 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:143638$7704_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:143643$7709 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:143643$7709_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:143640$7706 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_opc + connect \Y $not$libresoc.v:143640$7706_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:143642$7708 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_opc + connect \Y $not$libresoc.v:143642$7708_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:143645$7711 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_opc + connect \Y $not$libresoc.v:143645$7711_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:143639$7705 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_opc + connect \Y $or$libresoc.v:143639$7705_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:143641$7707 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_opc + connect \B \q_int + connect \Y $or$libresoc.v:143641$7707_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:143644$7710 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_opc + connect \Y $or$libresoc.v:143644$7710_Y + end + attribute \src "libresoc.v:143603.7-143603.20" + process $proc$libresoc.v:143603$7716 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:143625.7-143625.19" + process $proc$libresoc.v:143625$7717 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:143646.3-143647.27" + process $proc$libresoc.v:143646$7712 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:143648.3-143656.6" + process $proc$libresoc.v:143648$7713 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$7714 $1\q_int$next[0:0]$7715 + attribute \src "libresoc.v:143649.5-143649.29" + switch \initial + attribute \src "libresoc.v:143649.9-143649.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$7715 1'0 + case + assign $1\q_int$next[0:0]$7715 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$7714 + end + connect \$9 $and$libresoc.v:143638$7704_Y + connect \$11 $or$libresoc.v:143639$7705_Y + connect \$13 $not$libresoc.v:143640$7706_Y + connect \$15 $or$libresoc.v:143641$7707_Y + connect \$1 $not$libresoc.v:143642$7708_Y + connect \$3 $and$libresoc.v:143643$7709_Y + connect \$5 $or$libresoc.v:143644$7710_Y + connect \$7 $not$libresoc.v:143645$7711_Y + connect \qlq_opc \$15 + connect \qn_opc \$13 + connect \q_opc \$11 +end +attribute \src "libresoc.v:143664.1-143722.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.opc_l" +attribute \generator "nMigen" +module \opc_l$123 + attribute \src "libresoc.v:143665.7-143665.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:143710.3-143718.6" + wire $0\q_int$next[0:0]$7728 + attribute \src "libresoc.v:143708.3-143709.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:143710.3-143718.6" + wire $1\q_int$next[0:0]$7729 + attribute \src "libresoc.v:143687.7-143687.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:143700.17-143700.96" + wire $and$libresoc.v:143700$7718_Y + attribute \src "libresoc.v:143705.17-143705.96" + wire $and$libresoc.v:143705$7723_Y + attribute \src "libresoc.v:143702.18-143702.93" + wire $not$libresoc.v:143702$7720_Y + attribute \src "libresoc.v:143704.17-143704.92" + wire $not$libresoc.v:143704$7722_Y + attribute \src "libresoc.v:143707.17-143707.92" + wire $not$libresoc.v:143707$7725_Y + attribute \src "libresoc.v:143701.18-143701.98" + wire $or$libresoc.v:143701$7719_Y + attribute \src "libresoc.v:143703.18-143703.99" + wire $or$libresoc.v:143703$7721_Y + attribute \src "libresoc.v:143706.17-143706.97" + wire $or$libresoc.v:143706$7724_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 1 \coresync_rst + attribute \src "libresoc.v:143665.7-143665.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 4 \q_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 2 \s_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$libresoc.v:143700$7718 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:143700$7718_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:143705$7723 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:143705$7723_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:143702$7720 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_opc + connect \Y $not$libresoc.v:143702$7720_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:143704$7722 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_opc + connect \Y $not$libresoc.v:143704$7722_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:143707$7725 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_opc + connect \Y $not$libresoc.v:143707$7725_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:143701$7719 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_opc + connect \Y $or$libresoc.v:143701$7719_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:143703$7721 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_opc + connect \B \q_int + connect \Y $or$libresoc.v:143703$7721_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:143706$7724 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_opc + connect \Y $or$libresoc.v:143706$7724_Y + end + attribute \src "libresoc.v:143665.7-143665.20" + process $proc$libresoc.v:143665$7730 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:143687.7-143687.19" + process $proc$libresoc.v:143687$7731 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:143708.3-143709.27" + process $proc$libresoc.v:143708$7726 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:143710.3-143718.6" + process $proc$libresoc.v:143710$7727 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$7728 $1\q_int$next[0:0]$7729 + attribute \src "libresoc.v:143711.5-143711.29" + switch \initial + attribute \src "libresoc.v:143711.9-143711.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$7729 1'0 + case + assign $1\q_int$next[0:0]$7729 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$7728 + end + connect \$9 $and$libresoc.v:143700$7718_Y + connect \$11 $or$libresoc.v:143701$7719_Y + connect \$13 $not$libresoc.v:143702$7720_Y + connect \$15 $or$libresoc.v:143703$7721_Y + connect \$1 $not$libresoc.v:143704$7722_Y + connect \$3 $and$libresoc.v:143705$7723_Y + connect \$5 $or$libresoc.v:143706$7724_Y + connect \$7 $not$libresoc.v:143707$7725_Y + connect \qlq_opc \$15 + connect \qn_opc \$13 + connect \q_opc \$11 +end +attribute \src "libresoc.v:143726.1-143784.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.opc_l" +attribute \generator "nMigen" +module \opc_l$24 + attribute \src "libresoc.v:143727.7-143727.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:143772.3-143780.6" + wire $0\q_int$next[0:0]$7742 + attribute \src "libresoc.v:143770.3-143771.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:143772.3-143780.6" + wire $1\q_int$next[0:0]$7743 + attribute \src "libresoc.v:143749.7-143749.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:143762.17-143762.96" + wire $and$libresoc.v:143762$7732_Y + attribute \src "libresoc.v:143767.17-143767.96" + wire $and$libresoc.v:143767$7737_Y + attribute \src "libresoc.v:143764.18-143764.93" + wire $not$libresoc.v:143764$7734_Y + attribute \src "libresoc.v:143766.17-143766.92" + wire $not$libresoc.v:143766$7736_Y + attribute \src "libresoc.v:143769.17-143769.92" + wire $not$libresoc.v:143769$7739_Y + attribute \src "libresoc.v:143763.18-143763.98" + wire $or$libresoc.v:143763$7733_Y + attribute \src "libresoc.v:143765.18-143765.99" + wire $or$libresoc.v:143765$7735_Y + attribute \src "libresoc.v:143768.17-143768.97" + wire $or$libresoc.v:143768$7738_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 1 \coresync_rst + attribute \src "libresoc.v:143727.7-143727.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 4 \q_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 2 \s_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$libresoc.v:143762$7732 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:143762$7732_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:143767$7737 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:143767$7737_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:143764$7734 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_opc + connect \Y $not$libresoc.v:143764$7734_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:143766$7736 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_opc + connect \Y $not$libresoc.v:143766$7736_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:143769$7739 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_opc + connect \Y $not$libresoc.v:143769$7739_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:143763$7733 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_opc + connect \Y $or$libresoc.v:143763$7733_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:143765$7735 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_opc + connect \B \q_int + connect \Y $or$libresoc.v:143765$7735_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:143768$7738 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_opc + connect \Y $or$libresoc.v:143768$7738_Y + end + attribute \src "libresoc.v:143727.7-143727.20" + process $proc$libresoc.v:143727$7744 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:143749.7-143749.19" + process $proc$libresoc.v:143749$7745 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:143770.3-143771.27" + process $proc$libresoc.v:143770$7740 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:143772.3-143780.6" + process $proc$libresoc.v:143772$7741 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$7742 $1\q_int$next[0:0]$7743 + attribute \src "libresoc.v:143773.5-143773.29" + switch \initial + attribute \src "libresoc.v:143773.9-143773.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$7743 1'0 + case + assign $1\q_int$next[0:0]$7743 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$7742 + end + connect \$9 $and$libresoc.v:143762$7732_Y + connect \$11 $or$libresoc.v:143763$7733_Y + connect \$13 $not$libresoc.v:143764$7734_Y + connect \$15 $or$libresoc.v:143765$7735_Y + connect \$1 $not$libresoc.v:143766$7736_Y + connect \$3 $and$libresoc.v:143767$7737_Y + connect \$5 $or$libresoc.v:143768$7738_Y + connect \$7 $not$libresoc.v:143769$7739_Y + connect \qlq_opc \$15 + connect \qn_opc \$13 + connect \q_opc \$11 +end +attribute \src "libresoc.v:143788.1-143846.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.opc_l" +attribute \generator "nMigen" +module \opc_l$37 + attribute \src "libresoc.v:143789.7-143789.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:143834.3-143842.6" + wire $0\q_int$next[0:0]$7756 + attribute \src "libresoc.v:143832.3-143833.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:143834.3-143842.6" + wire $1\q_int$next[0:0]$7757 + attribute \src "libresoc.v:143811.7-143811.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:143824.17-143824.96" + wire $and$libresoc.v:143824$7746_Y + attribute \src "libresoc.v:143829.17-143829.96" + wire $and$libresoc.v:143829$7751_Y + attribute \src "libresoc.v:143826.18-143826.93" + wire $not$libresoc.v:143826$7748_Y + attribute \src "libresoc.v:143828.17-143828.92" + wire $not$libresoc.v:143828$7750_Y + attribute \src "libresoc.v:143831.17-143831.92" + wire $not$libresoc.v:143831$7753_Y + attribute \src "libresoc.v:143825.18-143825.98" + wire $or$libresoc.v:143825$7747_Y + attribute \src "libresoc.v:143827.18-143827.99" + wire $or$libresoc.v:143827$7749_Y + attribute \src "libresoc.v:143830.17-143830.97" + wire $or$libresoc.v:143830$7752_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 1 \coresync_rst + attribute \src "libresoc.v:143789.7-143789.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 4 \q_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 2 \s_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$libresoc.v:143824$7746 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:143824$7746_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:143829$7751 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:143829$7751_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:143826$7748 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_opc + connect \Y $not$libresoc.v:143826$7748_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:143828$7750 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_opc + connect \Y $not$libresoc.v:143828$7750_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:143831$7753 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_opc + connect \Y $not$libresoc.v:143831$7753_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:143825$7747 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_opc + connect \Y $or$libresoc.v:143825$7747_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:143827$7749 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_opc + connect \B \q_int + connect \Y $or$libresoc.v:143827$7749_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:143830$7752 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_opc + connect \Y $or$libresoc.v:143830$7752_Y + end + attribute \src "libresoc.v:143789.7-143789.20" + process $proc$libresoc.v:143789$7758 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:143811.7-143811.19" + process $proc$libresoc.v:143811$7759 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:143832.3-143833.27" + process $proc$libresoc.v:143832$7754 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:143834.3-143842.6" + process $proc$libresoc.v:143834$7755 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$7756 $1\q_int$next[0:0]$7757 + attribute \src "libresoc.v:143835.5-143835.29" + switch \initial + attribute \src "libresoc.v:143835.9-143835.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$7757 1'0 + case + assign $1\q_int$next[0:0]$7757 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$7756 + end + connect \$9 $and$libresoc.v:143824$7746_Y + connect \$11 $or$libresoc.v:143825$7747_Y + connect \$13 $not$libresoc.v:143826$7748_Y + connect \$15 $or$libresoc.v:143827$7749_Y + connect \$1 $not$libresoc.v:143828$7750_Y + connect \$3 $and$libresoc.v:143829$7751_Y + connect \$5 $or$libresoc.v:143830$7752_Y + connect \$7 $not$libresoc.v:143831$7753_Y + connect \qlq_opc \$15 + connect \qn_opc \$13 + connect \q_opc \$11 +end +attribute \src "libresoc.v:143850.1-143908.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.opc_l" +attribute \generator "nMigen" +module \opc_l$53 + attribute \src "libresoc.v:143851.7-143851.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:143896.3-143904.6" + wire $0\q_int$next[0:0]$7770 + attribute \src "libresoc.v:143894.3-143895.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:143896.3-143904.6" + wire $1\q_int$next[0:0]$7771 + attribute \src "libresoc.v:143873.7-143873.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:143886.17-143886.96" + wire $and$libresoc.v:143886$7760_Y + attribute \src "libresoc.v:143891.17-143891.96" + wire $and$libresoc.v:143891$7765_Y + attribute \src "libresoc.v:143888.18-143888.93" + wire $not$libresoc.v:143888$7762_Y + attribute \src "libresoc.v:143890.17-143890.92" + wire $not$libresoc.v:143890$7764_Y + attribute \src "libresoc.v:143893.17-143893.92" + wire $not$libresoc.v:143893$7767_Y + attribute \src "libresoc.v:143887.18-143887.98" + wire $or$libresoc.v:143887$7761_Y + attribute \src "libresoc.v:143889.18-143889.99" + wire $or$libresoc.v:143889$7763_Y + attribute \src "libresoc.v:143892.17-143892.97" + wire $or$libresoc.v:143892$7766_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 1 \coresync_rst + attribute \src "libresoc.v:143851.7-143851.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 4 \q_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 2 \s_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$libresoc.v:143886$7760 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:143886$7760_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:143891$7765 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:143891$7765_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:143888$7762 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_opc + connect \Y $not$libresoc.v:143888$7762_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:143890$7764 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_opc + connect \Y $not$libresoc.v:143890$7764_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:143893$7767 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_opc + connect \Y $not$libresoc.v:143893$7767_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:143887$7761 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_opc + connect \Y $or$libresoc.v:143887$7761_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:143889$7763 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_opc + connect \B \q_int + connect \Y $or$libresoc.v:143889$7763_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:143892$7766 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_opc + connect \Y $or$libresoc.v:143892$7766_Y + end + attribute \src "libresoc.v:143851.7-143851.20" + process $proc$libresoc.v:143851$7772 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:143873.7-143873.19" + process $proc$libresoc.v:143873$7773 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:143894.3-143895.27" + process $proc$libresoc.v:143894$7768 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:143896.3-143904.6" + process $proc$libresoc.v:143896$7769 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$7770 $1\q_int$next[0:0]$7771 + attribute \src "libresoc.v:143897.5-143897.29" + switch \initial + attribute \src "libresoc.v:143897.9-143897.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$7771 1'0 + case + assign $1\q_int$next[0:0]$7771 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$7770 + end + connect \$9 $and$libresoc.v:143886$7760_Y + connect \$11 $or$libresoc.v:143887$7761_Y + connect \$13 $not$libresoc.v:143888$7762_Y + connect \$15 $or$libresoc.v:143889$7763_Y + connect \$1 $not$libresoc.v:143890$7764_Y + connect \$3 $and$libresoc.v:143891$7765_Y + connect \$5 $or$libresoc.v:143892$7766_Y + connect \$7 $not$libresoc.v:143893$7767_Y + connect \qlq_opc \$15 + connect \qn_opc \$13 + connect \q_opc \$11 +end +attribute \src "libresoc.v:143912.1-143970.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.opc_l" +attribute \generator "nMigen" +module \opc_l$65 + attribute \src "libresoc.v:143913.7-143913.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:143958.3-143966.6" + wire $0\q_int$next[0:0]$7784 + attribute \src "libresoc.v:143956.3-143957.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:143958.3-143966.6" + wire $1\q_int$next[0:0]$7785 + attribute \src "libresoc.v:143935.7-143935.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:143948.17-143948.96" + wire $and$libresoc.v:143948$7774_Y + attribute \src "libresoc.v:143953.17-143953.96" + wire $and$libresoc.v:143953$7779_Y + attribute \src "libresoc.v:143950.18-143950.93" + wire $not$libresoc.v:143950$7776_Y + attribute \src "libresoc.v:143952.17-143952.92" + wire $not$libresoc.v:143952$7778_Y + attribute \src "libresoc.v:143955.17-143955.92" + wire $not$libresoc.v:143955$7781_Y + attribute \src "libresoc.v:143949.18-143949.98" + wire $or$libresoc.v:143949$7775_Y + attribute \src "libresoc.v:143951.18-143951.99" + wire $or$libresoc.v:143951$7777_Y + attribute \src "libresoc.v:143954.17-143954.97" + wire $or$libresoc.v:143954$7780_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 1 \coresync_rst + attribute \src "libresoc.v:143913.7-143913.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 4 \q_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 2 \s_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$libresoc.v:143948$7774 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:143948$7774_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:143953$7779 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:143953$7779_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:143950$7776 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_opc + connect \Y $not$libresoc.v:143950$7776_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:143952$7778 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_opc + connect \Y $not$libresoc.v:143952$7778_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:143955$7781 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_opc + connect \Y $not$libresoc.v:143955$7781_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:143949$7775 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_opc + connect \Y $or$libresoc.v:143949$7775_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:143951$7777 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_opc + connect \B \q_int + connect \Y $or$libresoc.v:143951$7777_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:143954$7780 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_opc + connect \Y $or$libresoc.v:143954$7780_Y + end + attribute \src "libresoc.v:143913.7-143913.20" + process $proc$libresoc.v:143913$7786 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:143935.7-143935.19" + process $proc$libresoc.v:143935$7787 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:143956.3-143957.27" + process $proc$libresoc.v:143956$7782 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:143958.3-143966.6" + process $proc$libresoc.v:143958$7783 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$7784 $1\q_int$next[0:0]$7785 + attribute \src "libresoc.v:143959.5-143959.29" + switch \initial + attribute \src "libresoc.v:143959.9-143959.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$7785 1'0 + case + assign $1\q_int$next[0:0]$7785 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$7784 + end + connect \$9 $and$libresoc.v:143948$7774_Y + connect \$11 $or$libresoc.v:143949$7775_Y + connect \$13 $not$libresoc.v:143950$7776_Y + connect \$15 $or$libresoc.v:143951$7777_Y + connect \$1 $not$libresoc.v:143952$7778_Y + connect \$3 $and$libresoc.v:143953$7779_Y + connect \$5 $or$libresoc.v:143954$7780_Y + connect \$7 $not$libresoc.v:143955$7781_Y + connect \qlq_opc \$15 + connect \qn_opc \$13 + connect \q_opc \$11 +end +attribute \src "libresoc.v:143974.1-144032.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.opc_l" +attribute \generator "nMigen" +module \opc_l$82 + attribute \src "libresoc.v:143975.7-143975.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:144020.3-144028.6" + wire $0\q_int$next[0:0]$7798 + attribute \src "libresoc.v:144018.3-144019.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:144020.3-144028.6" + wire $1\q_int$next[0:0]$7799 + attribute \src "libresoc.v:143997.7-143997.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:144010.17-144010.96" + wire $and$libresoc.v:144010$7788_Y + attribute \src "libresoc.v:144015.17-144015.96" + wire $and$libresoc.v:144015$7793_Y + attribute \src "libresoc.v:144012.18-144012.93" + wire $not$libresoc.v:144012$7790_Y + attribute \src "libresoc.v:144014.17-144014.92" + wire $not$libresoc.v:144014$7792_Y + attribute \src "libresoc.v:144017.17-144017.92" + wire $not$libresoc.v:144017$7795_Y + attribute \src "libresoc.v:144011.18-144011.98" + wire $or$libresoc.v:144011$7789_Y + attribute \src "libresoc.v:144013.18-144013.99" + wire $or$libresoc.v:144013$7791_Y + attribute \src "libresoc.v:144016.17-144016.97" + wire $or$libresoc.v:144016$7794_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 1 \coresync_rst + attribute \src "libresoc.v:143975.7-143975.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 4 \q_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 2 \s_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$libresoc.v:144010$7788 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:144010$7788_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:144015$7793 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:144015$7793_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:144012$7790 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_opc + connect \Y $not$libresoc.v:144012$7790_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:144014$7792 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_opc + connect \Y $not$libresoc.v:144014$7792_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:144017$7795 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_opc + connect \Y $not$libresoc.v:144017$7795_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:144011$7789 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_opc + connect \Y $or$libresoc.v:144011$7789_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:144013$7791 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_opc + connect \B \q_int + connect \Y $or$libresoc.v:144013$7791_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:144016$7794 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_opc + connect \Y $or$libresoc.v:144016$7794_Y + end + attribute \src "libresoc.v:143975.7-143975.20" + process $proc$libresoc.v:143975$7800 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:143997.7-143997.19" + process $proc$libresoc.v:143997$7801 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:144018.3-144019.27" + process $proc$libresoc.v:144018$7796 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:144020.3-144028.6" + process $proc$libresoc.v:144020$7797 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$7798 $1\q_int$next[0:0]$7799 + attribute \src "libresoc.v:144021.5-144021.29" + switch \initial + attribute \src "libresoc.v:144021.9-144021.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$7799 1'0 + case + assign $1\q_int$next[0:0]$7799 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$7798 + end + connect \$9 $and$libresoc.v:144010$7788_Y + connect \$11 $or$libresoc.v:144011$7789_Y + connect \$13 $not$libresoc.v:144012$7790_Y + connect \$15 $or$libresoc.v:144013$7791_Y + connect \$1 $not$libresoc.v:144014$7792_Y + connect \$3 $and$libresoc.v:144015$7793_Y + connect \$5 $or$libresoc.v:144016$7794_Y + connect \$7 $not$libresoc.v:144017$7795_Y + connect \qlq_opc \$15 + connect \qn_opc \$13 + connect \q_opc \$11 +end +attribute \src "libresoc.v:144036.1-144094.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.opc_l" +attribute \generator "nMigen" +module \opc_l$99 + attribute \src "libresoc.v:144037.7-144037.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:144082.3-144090.6" + wire $0\q_int$next[0:0]$7812 + attribute \src "libresoc.v:144080.3-144081.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:144082.3-144090.6" + wire $1\q_int$next[0:0]$7813 + attribute \src "libresoc.v:144059.7-144059.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:144072.17-144072.96" + wire $and$libresoc.v:144072$7802_Y + attribute \src "libresoc.v:144077.17-144077.96" + wire $and$libresoc.v:144077$7807_Y + attribute \src "libresoc.v:144074.18-144074.93" + wire $not$libresoc.v:144074$7804_Y + attribute \src "libresoc.v:144076.17-144076.92" + wire $not$libresoc.v:144076$7806_Y + attribute \src "libresoc.v:144079.17-144079.92" + wire $not$libresoc.v:144079$7809_Y + attribute \src "libresoc.v:144073.18-144073.98" + wire $or$libresoc.v:144073$7803_Y + attribute \src "libresoc.v:144075.18-144075.99" + wire $or$libresoc.v:144075$7805_Y + attribute \src "libresoc.v:144078.17-144078.97" + wire $or$libresoc.v:144078$7808_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 1 \coresync_rst + attribute \src "libresoc.v:144037.7-144037.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 4 \q_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 2 \s_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$libresoc.v:144072$7802 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:144072$7802_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:144077$7807 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:144077$7807_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:144074$7804 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_opc + connect \Y $not$libresoc.v:144074$7804_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:144076$7806 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_opc + connect \Y $not$libresoc.v:144076$7806_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:144079$7809 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_opc + connect \Y $not$libresoc.v:144079$7809_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:144073$7803 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_opc + connect \Y $or$libresoc.v:144073$7803_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:144075$7805 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_opc + connect \B \q_int + connect \Y $or$libresoc.v:144075$7805_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:144078$7808 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_opc + connect \Y $or$libresoc.v:144078$7808_Y + end + attribute \src "libresoc.v:144037.7-144037.20" + process $proc$libresoc.v:144037$7814 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:144059.7-144059.19" + process $proc$libresoc.v:144059$7815 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:144080.3-144081.27" + process $proc$libresoc.v:144080$7810 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:144082.3-144090.6" + process $proc$libresoc.v:144082$7811 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$7812 $1\q_int$next[0:0]$7813 + attribute \src "libresoc.v:144083.5-144083.29" + switch \initial + attribute \src "libresoc.v:144083.9-144083.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$7813 1'0 + case + assign $1\q_int$next[0:0]$7813 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$7812 + end + connect \$9 $and$libresoc.v:144072$7802_Y + connect \$11 $or$libresoc.v:144073$7803_Y + connect \$13 $not$libresoc.v:144074$7804_Y + connect \$15 $or$libresoc.v:144075$7805_Y + connect \$1 $not$libresoc.v:144076$7806_Y + connect \$3 $and$libresoc.v:144077$7807_Y + connect \$5 $or$libresoc.v:144078$7808_Y + connect \$7 $not$libresoc.v:144079$7809_Y + connect \qlq_opc \$15 + connect \qn_opc \$13 + connect \q_opc \$11 +end +attribute \src "libresoc.v:144098.1-144550.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alu_alu0.pipe2.output" +attribute \generator "nMigen" +module \output + attribute \src "libresoc.v:144469.3-144480.6" + wire width 4 $0\cr0[3:0] + attribute \src "libresoc.v:144099.7-144099.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:144481.3-144492.6" + wire width 65 $0\o$28[64:0]$7834 + attribute \src "libresoc.v:144457.3-144468.6" + wire $0\so[0:0] + attribute \src "libresoc.v:144513.3-144522.6" + wire width 2 $0\xer_ov$24[1:0]$7841 + attribute \src "libresoc.v:144523.3-144532.6" + wire $0\xer_ov_ok[0:0] + attribute \src "libresoc.v:144493.3-144502.6" + wire $0\xer_so$25[0:0]$7837 + attribute \src "libresoc.v:144503.3-144512.6" + wire $0\xer_so_ok[0:0] + attribute \src "libresoc.v:144469.3-144480.6" + wire width 4 $1\cr0[3:0] + attribute \src "libresoc.v:144481.3-144492.6" + wire width 65 $1\o$28[64:0]$7835 + attribute \src "libresoc.v:144457.3-144468.6" + wire $1\so[0:0] + attribute \src "libresoc.v:144513.3-144522.6" + wire width 2 $1\xer_ov$24[1:0]$7842 + attribute \src "libresoc.v:144523.3-144532.6" + wire $1\xer_ov_ok[0:0] + attribute \src "libresoc.v:144493.3-144502.6" + wire $1\xer_so$25[0:0]$7838 + attribute \src "libresoc.v:144503.3-144512.6" + wire $1\xer_so_ok[0:0] + attribute \src "libresoc.v:144444.18-144444.128" + wire $and$libresoc.v:144444$7816_Y + attribute \src "libresoc.v:144452.18-144452.112" + wire $and$libresoc.v:144452$7826_Y + attribute \src "libresoc.v:144455.18-144455.125" + wire $and$libresoc.v:144455$7829_Y + attribute \src "libresoc.v:144448.18-144448.123" + wire $eq$libresoc.v:144448$7822_Y + attribute \src "libresoc.v:144449.18-144449.123" + wire $eq$libresoc.v:144449$7823_Y + attribute \src "libresoc.v:144446.18-144446.103" + wire width 65 $extend$libresoc.v:144446$7818_Y + attribute \src "libresoc.v:144447.18-144447.101" + wire width 65 $extend$libresoc.v:144447$7820_Y + attribute \src "libresoc.v:144445.18-144445.100" + wire width 64 $not$libresoc.v:144445$7817_Y + attribute \src "libresoc.v:144451.18-144451.107" + wire $not$libresoc.v:144451$7825_Y + attribute \src "libresoc.v:144454.18-144454.107" + wire $not$libresoc.v:144454$7828_Y + attribute \src "libresoc.v:144453.18-144453.115" + wire $or$libresoc.v:144453$7827_Y + attribute \src "libresoc.v:144456.18-144456.112" + wire $or$libresoc.v:144456$7830_Y + attribute \src "libresoc.v:144446.18-144446.103" + wire width 65 $pos$libresoc.v:144446$7819_Y + attribute \src "libresoc.v:144447.18-144447.101" + wire width 65 $pos$libresoc.v:144447$7821_Y + attribute \src "libresoc.v:144450.18-144450.105" + wire $reduce_or$libresoc.v:144450$7824_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29" + wire \$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" + wire width 65 \$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" + wire width 64 \$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 65 \$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" + wire \$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" + wire \$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" + wire \$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" + wire \$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" + wire \$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" + wire \$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" + wire \$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" + wire \$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:33" + wire \$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 17 \alu_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 42 \alu_op__data_len$18 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 2 \alu_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 output 27 \alu_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 3 \alu_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 28 \alu_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 4 \alu_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 29 \alu_op__imm_data__ok$5 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 13 \alu_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 38 \alu_op__input_carry$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 18 \alu_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 43 \alu_op__insn$19 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \alu_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 26 \alu_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \alu_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 34 \alu_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 11 \alu_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 36 \alu_op__invert_out$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 15 \alu_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 40 \alu_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 16 \alu_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 41 \alu_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 7 \alu_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 32 \alu_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \alu_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 33 \alu_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \alu_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 39 \alu_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 6 \alu_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 31 \alu_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 5 \alu_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 30 \alu_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \alu_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 37 \alu_op__write_cr0$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \alu_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 35 \alu_op__zero_a$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:71" + wire width 4 \cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 input 21 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 output 46 \cr_a$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 47 \cr_a_ok + attribute \src "libresoc.v:144099.7-144099.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:69" + wire \is_cmp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:70" + wire \is_cmpeqb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:67" + wire \is_negative + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:65" + wire \is_nzero + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:66" + wire \is_positive + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:68" + wire \msb_test + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 54 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 25 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 input 19 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 44 \o$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:38" + wire width 65 \o$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire input 20 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 45 \o_ok$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:28" + wire \oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:29" + wire \oe$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:27" + wire \so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:50" + wire width 64 \target + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 input 22 \xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 output 48 \xer_ca$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 49 \xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 input 23 \xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 output 50 \xer_ov$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 51 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire input 24 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 52 \xer_so$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 53 \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29" + cell $and $and$libresoc.v:144444$7816 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_op__oe__oe + connect \B \alu_op__oe__ok + connect \Y $and$libresoc.v:144444$7816_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" + cell $and $and$libresoc.v:144452$7826 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_nzero + connect \B \$41 + connect \Y $and$libresoc.v:144452$7826_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" + cell $and $and$libresoc.v:144455$7829 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_op__oe__oe + connect \B \alu_op__oe__ok + connect \Y $and$libresoc.v:144455$7829_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" + cell $eq $eq$libresoc.v:144448$7822 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \alu_op__insn_type + connect \B 7'0001010 + connect \Y $eq$libresoc.v:144448$7822_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" + cell $eq $eq$libresoc.v:144449$7823 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \alu_op__insn_type + connect \B 7'0001100 + connect \Y $eq$libresoc.v:144449$7823_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" + cell $pos $extend$libresoc.v:144446$7818 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \$30 + connect \Y $extend$libresoc.v:144446$7818_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + cell $pos $extend$libresoc.v:144447$7820 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \o + connect \Y $extend$libresoc.v:144447$7820_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" + cell $not $not$libresoc.v:144445$7817 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \o + connect \Y $not$libresoc.v:144445$7817_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" + cell $not $not$libresoc.v:144451$7825 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \msb_test + connect \Y $not$libresoc.v:144451$7825_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" + cell $not $not$libresoc.v:144454$7828 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_nzero + connect \Y $not$libresoc.v:144454$7828_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" + cell $or $or$libresoc.v:144453$7827 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_cmpeqb + connect \B \is_cmp + connect \Y $or$libresoc.v:144453$7827_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:33" + cell $or $or$libresoc.v:144456$7830 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \xer_so + connect \B \xer_ov [0] + connect \Y $or$libresoc.v:144456$7830_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" + cell $pos $pos$libresoc.v:144446$7819 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \Y_WIDTH 65 + connect \A $extend$libresoc.v:144446$7818_Y + connect \Y $pos$libresoc.v:144446$7819_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + cell $pos $pos$libresoc.v:144447$7821 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \Y_WIDTH 65 + connect \A $extend$libresoc.v:144447$7820_Y + connect \Y $pos$libresoc.v:144447$7821_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" + cell $reduce_or $reduce_or$libresoc.v:144450$7824 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 1 + connect \A \target + connect \Y $reduce_or$libresoc.v:144450$7824_Y + end + attribute \src "libresoc.v:144099.7-144099.20" + process $proc$libresoc.v:144099$7844 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:144457.3-144468.6" + process $proc$libresoc.v:144457$7831 + assign { } { } + assign $0\so[0:0] $1\so[0:0] + attribute \src "libresoc.v:144458.5-144458.29" + switch \initial + attribute \src "libresoc.v:144458.9-144458.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:30" + switch \oe + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\so[0:0] \xer_so$25 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\so[0:0] \xer_so + end + sync always + update \so $0\so[0:0] + end + attribute \src "libresoc.v:144469.3-144480.6" + process $proc$libresoc.v:144469$7832 + assign { } { } + assign $0\cr0[3:0] $1\cr0[3:0] + attribute \src "libresoc.v:144470.5-144470.29" + switch \initial + attribute \src "libresoc.v:144470.9-144470.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" + switch \$45 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cr0[3:0] \cr_a + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cr0[3:0] { \is_negative \is_positive \$47 \so } + end + sync always + update \cr0 $0\cr0[3:0] + end + attribute \src "libresoc.v:144481.3-144492.6" + process $proc$libresoc.v:144481$7833 + assign { } { } + assign $0\o$28[64:0]$7834 $1\o$28[64:0]$7835 + attribute \src "libresoc.v:144482.5-144482.29" + switch \initial + attribute \src "libresoc.v:144482.9-144482.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:40" + switch \alu_op__invert_out + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\o$28[64:0]$7835 \$29 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\o$28[64:0]$7835 \$33 + end + sync always + update \o$28 $0\o$28[64:0]$7834 + end + attribute \src "libresoc.v:144493.3-144502.6" + process $proc$libresoc.v:144493$7836 + assign { } { } + assign { } { } + assign $0\xer_so$25[0:0]$7837 $1\xer_so$25[0:0]$7838 + attribute \src "libresoc.v:144494.5-144494.29" + switch \initial + attribute \src "libresoc.v:144494.9-144494.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" + switch \oe$49 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\xer_so$25[0:0]$7838 \$52 + case + assign $1\xer_so$25[0:0]$7838 1'0 + end + sync always + update \xer_so$25 $0\xer_so$25[0:0]$7837 + end + attribute \src "libresoc.v:144503.3-144512.6" + process $proc$libresoc.v:144503$7839 + assign { } { } + assign { } { } + assign $0\xer_so_ok[0:0] $1\xer_so_ok[0:0] + attribute \src "libresoc.v:144504.5-144504.29" + switch \initial + attribute \src "libresoc.v:144504.9-144504.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" + switch \oe$49 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\xer_so_ok[0:0] 1'1 + case + assign $1\xer_so_ok[0:0] 1'0 + end + sync always + update \xer_so_ok $0\xer_so_ok[0:0] + end + attribute \src "libresoc.v:144513.3-144522.6" + process $proc$libresoc.v:144513$7840 + assign { } { } + assign { } { } + assign $0\xer_ov$24[1:0]$7841 $1\xer_ov$24[1:0]$7842 + attribute \src "libresoc.v:144514.5-144514.29" + switch \initial + attribute \src "libresoc.v:144514.9-144514.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" + switch \oe$49 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\xer_ov$24[1:0]$7842 \xer_ov + case + assign $1\xer_ov$24[1:0]$7842 2'00 + end + sync always + update \xer_ov$24 $0\xer_ov$24[1:0]$7841 + end + attribute \src "libresoc.v:144523.3-144532.6" + process $proc$libresoc.v:144523$7843 + assign { } { } + assign { } { } + assign $0\xer_ov_ok[0:0] $1\xer_ov_ok[0:0] + attribute \src "libresoc.v:144524.5-144524.29" + switch \initial + attribute \src "libresoc.v:144524.9-144524.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" + switch \oe$49 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\xer_ov_ok[0:0] 1'1 + case + assign $1\xer_ov_ok[0:0] 1'0 + end + sync always + update \xer_ov_ok $0\xer_ov_ok[0:0] + end + connect \$26 $and$libresoc.v:144444$7816_Y + connect \$30 $not$libresoc.v:144445$7817_Y + connect \$29 $pos$libresoc.v:144446$7819_Y + connect \$33 $pos$libresoc.v:144447$7821_Y + connect \$35 $eq$libresoc.v:144448$7822_Y + connect \$37 $eq$libresoc.v:144449$7823_Y + connect \$39 $reduce_or$libresoc.v:144450$7824_Y + connect \$41 $not$libresoc.v:144451$7825_Y + connect \$43 $and$libresoc.v:144452$7826_Y + connect \$45 $or$libresoc.v:144453$7827_Y + connect \$47 $not$libresoc.v:144454$7828_Y + connect \$50 $and$libresoc.v:144455$7829_Y + connect \$52 $or$libresoc.v:144456$7830_Y + connect \oe$49 \$50 + connect { \alu_op__insn$19 \alu_op__data_len$18 \alu_op__is_signed$17 \alu_op__is_32bit$16 \alu_op__output_carry$15 \alu_op__input_carry$14 \alu_op__write_cr0$13 \alu_op__invert_out$12 \alu_op__zero_a$11 \alu_op__invert_in$10 \alu_op__oe__ok$9 \alu_op__oe__oe$8 \alu_op__rc__ok$7 \alu_op__rc__rc$6 \alu_op__imm_data__ok$5 \alu_op__imm_data__data$4 \alu_op__fn_unit$3 \alu_op__insn_type$2 } { \alu_op__insn \alu_op__data_len \alu_op__is_signed \alu_op__is_32bit \alu_op__output_carry \alu_op__input_carry \alu_op__write_cr0 \alu_op__invert_out \alu_op__zero_a \alu_op__invert_in \alu_op__oe__ok \alu_op__oe__oe \alu_op__rc__ok \alu_op__rc__rc \alu_op__imm_data__ok \alu_op__imm_data__data \alu_op__fn_unit \alu_op__insn_type } + connect \muxid$1 \muxid + connect \cr_a_ok \alu_op__write_cr0 + connect \cr_a$22 \cr0 + connect \o_ok$21 \o_ok + connect \o$20 \o$28 [63:0] + connect \is_positive \$43 + connect \is_negative \msb_test + connect \is_nzero \$39 + connect \msb_test \target [63] + connect \is_cmpeqb \$37 + connect \is_cmp \$35 + connect \xer_ca_ok \alu_op__output_carry + connect \xer_ca$23 \xer_ca + connect \target \o$28 [63:0] + connect \oe \$26 +end +attribute \src "libresoc.v:144554.1-144898.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.pipe2.output" +attribute \generator "nMigen" +module \output$115 + attribute \src "libresoc.v:144870.3-144881.6" + wire width 4 $0\cr0[3:0] + attribute \src "libresoc.v:144555.7-144555.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:144870.3-144881.6" + wire width 4 $1\cr0[3:0] + attribute \src "libresoc.v:144867.18-144867.112" + wire $and$libresoc.v:144867$7851_Y + attribute \src "libresoc.v:144863.18-144863.122" + wire $eq$libresoc.v:144863$7847_Y + attribute \src "libresoc.v:144864.18-144864.122" + wire $eq$libresoc.v:144864$7848_Y + attribute \src "libresoc.v:144862.18-144862.101" + wire width 65 $extend$libresoc.v:144862$7845_Y + attribute \src "libresoc.v:144866.18-144866.107" + wire $not$libresoc.v:144866$7850_Y + attribute \src "libresoc.v:144869.18-144869.107" + wire $not$libresoc.v:144869$7853_Y + attribute \src "libresoc.v:144868.18-144868.115" + wire $or$libresoc.v:144868$7852_Y + attribute \src "libresoc.v:144862.18-144862.101" + wire width 65 $pos$libresoc.v:144862$7846_Y + attribute \src "libresoc.v:144865.18-144865.105" + wire $reduce_or$libresoc.v:144865$7849_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 65 \$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" + wire \$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" + wire \$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" + wire \$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" + wire \$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" + wire \$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:71" + wire width 4 \cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 input 19 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 output 41 \cr_a$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 42 \cr_a_ok + attribute \src "libresoc.v:144555.7-144555.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:69" + wire \is_cmp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:70" + wire \is_cmpeqb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:67" + wire \is_negative + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:65" + wire \is_nzero + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:66" + wire \is_positive + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:68" + wire \msb_test + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 45 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 22 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 input 17 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 39 \o$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:38" + wire width 65 \o$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire input 18 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 40 \o_ok$19 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 2 \sr_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 output 24 \sr_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 3 \sr_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 25 \sr_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 4 \sr_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 26 \sr_op__imm_data__ok$5 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 10 \sr_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 32 \sr_op__input_carry$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \sr_op__input_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 34 \sr_op__input_cr$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 16 \sr_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 38 \sr_op__insn$17 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \sr_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 23 \sr_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \sr_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 36 \sr_op__is_32bit$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 15 \sr_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 37 \sr_op__is_signed$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 7 \sr_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 29 \sr_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \sr_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 30 \sr_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 11 \sr_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 33 \sr_op__output_carry$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \sr_op__output_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 35 \sr_op__output_cr$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 6 \sr_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 28 \sr_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 5 \sr_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 27 \sr_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \sr_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 31 \sr_op__write_cr0$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:50" + wire width 64 \target + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 input 21 \xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 output 43 \xer_ca$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 44 \xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire input 20 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" + cell $and $and$libresoc.v:144867$7851 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_nzero + connect \B \$31 + connect \Y $and$libresoc.v:144867$7851_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" + cell $eq $eq$libresoc.v:144863$7847 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \sr_op__insn_type + connect \B 7'0001010 + connect \Y $eq$libresoc.v:144863$7847_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" + cell $eq $eq$libresoc.v:144864$7848 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \sr_op__insn_type + connect \B 7'0001100 + connect \Y $eq$libresoc.v:144864$7848_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + cell $pos $extend$libresoc.v:144862$7845 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \o + connect \Y $extend$libresoc.v:144862$7845_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" + cell $not $not$libresoc.v:144866$7850 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \msb_test + connect \Y $not$libresoc.v:144866$7850_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" + cell $not $not$libresoc.v:144869$7853 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_nzero + connect \Y $not$libresoc.v:144869$7853_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" + cell $or $or$libresoc.v:144868$7852 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_cmpeqb + connect \B \is_cmp + connect \Y $or$libresoc.v:144868$7852_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + cell $pos $pos$libresoc.v:144862$7846 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \Y_WIDTH 65 + connect \A $extend$libresoc.v:144862$7845_Y + connect \Y $pos$libresoc.v:144862$7846_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" + cell $reduce_or $reduce_or$libresoc.v:144865$7849 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 1 + connect \A \target + connect \Y $reduce_or$libresoc.v:144865$7849_Y + end + attribute \src "libresoc.v:144555.7-144555.20" + process $proc$libresoc.v:144555$7855 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:144870.3-144881.6" + process $proc$libresoc.v:144870$7854 + assign { } { } + assign $0\cr0[3:0] $1\cr0[3:0] + attribute \src "libresoc.v:144871.5-144871.29" + switch \initial + attribute \src "libresoc.v:144871.9-144871.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" + switch \$35 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cr0[3:0] \cr_a + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cr0[3:0] { \is_negative \is_positive \$37 \xer_so } + end + sync always + update \cr0 $0\cr0[3:0] + end + connect \$23 $pos$libresoc.v:144862$7846_Y + connect \$25 $eq$libresoc.v:144863$7847_Y + connect \$27 $eq$libresoc.v:144864$7848_Y + connect \$29 $reduce_or$libresoc.v:144865$7849_Y + connect \$31 $not$libresoc.v:144866$7850_Y + connect \$33 $and$libresoc.v:144867$7851_Y + connect \$35 $or$libresoc.v:144868$7852_Y + connect \$37 $not$libresoc.v:144869$7853_Y + connect { \sr_op__insn$17 \sr_op__is_signed$16 \sr_op__is_32bit$15 \sr_op__output_cr$14 \sr_op__input_cr$13 \sr_op__output_carry$12 \sr_op__input_carry$11 \sr_op__write_cr0$10 \sr_op__oe__ok$9 \sr_op__oe__oe$8 \sr_op__rc__ok$7 \sr_op__rc__rc$6 \sr_op__imm_data__ok$5 \sr_op__imm_data__data$4 \sr_op__fn_unit$3 \sr_op__insn_type$2 } { \sr_op__insn \sr_op__is_signed \sr_op__is_32bit \sr_op__output_cr \sr_op__input_cr \sr_op__output_carry \sr_op__input_carry \sr_op__write_cr0 \sr_op__oe__ok \sr_op__oe__oe \sr_op__rc__ok \sr_op__rc__rc \sr_op__imm_data__ok \sr_op__imm_data__data \sr_op__fn_unit \sr_op__insn_type } + connect \muxid$1 \muxid + connect \cr_a_ok \sr_op__write_cr0 + connect \cr_a$20 \cr0 + connect \o_ok$19 \o_ok + connect \o$18 \o$22 [63:0] + connect \is_positive \$33 + connect \is_negative \msb_test + connect \is_nzero \$29 + connect \msb_test \target [63] + connect \is_cmpeqb \$27 + connect \is_cmp \$25 + connect \xer_ca_ok \sr_op__output_carry + connect \xer_ca$21 \xer_ca + connect \target \o$22 [63:0] + connect \o$22 \$23 +end +attribute \src "libresoc.v:144902.1-145263.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_logical0.logical_pipe2.output" +attribute \generator "nMigen" +module \output$51 + attribute \src "libresoc.v:145238.3-145249.6" + wire width 4 $0\cr0[3:0] + attribute \src "libresoc.v:144903.7-144903.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:145226.3-145237.6" + wire width 65 $0\o$23[64:0]$7869 + attribute \src "libresoc.v:145238.3-145249.6" + wire width 4 $1\cr0[3:0] + attribute \src "libresoc.v:145226.3-145237.6" + wire width 65 $1\o$23[64:0]$7870 + attribute \src "libresoc.v:145223.18-145223.112" + wire $and$libresoc.v:145223$7865_Y + attribute \src "libresoc.v:145219.18-145219.127" + wire $eq$libresoc.v:145219$7861_Y + attribute \src "libresoc.v:145220.18-145220.127" + wire $eq$libresoc.v:145220$7862_Y + attribute \src "libresoc.v:145217.18-145217.103" + wire width 65 $extend$libresoc.v:145217$7857_Y + attribute \src "libresoc.v:145218.18-145218.101" + wire width 65 $extend$libresoc.v:145218$7859_Y + attribute \src "libresoc.v:145216.18-145216.100" + wire width 64 $not$libresoc.v:145216$7856_Y + attribute \src "libresoc.v:145222.18-145222.107" + wire $not$libresoc.v:145222$7864_Y + attribute \src "libresoc.v:145225.18-145225.107" + wire $not$libresoc.v:145225$7867_Y + attribute \src "libresoc.v:145224.18-145224.115" + wire $or$libresoc.v:145224$7866_Y + attribute \src "libresoc.v:145217.18-145217.103" + wire width 65 $pos$libresoc.v:145217$7858_Y + attribute \src "libresoc.v:145218.18-145218.101" + wire width 65 $pos$libresoc.v:145218$7860_Y + attribute \src "libresoc.v:145221.18-145221.105" + wire $reduce_or$libresoc.v:145221$7863_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" + wire width 65 \$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" + wire width 64 \$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 65 \$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" + wire \$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" + wire \$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" + wire \$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" + wire \$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" + wire \$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" + wire \$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" + wire \$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:71" + wire width 4 \cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 input 21 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 output 44 \cr_a$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 45 \cr_a_ok + attribute \src "libresoc.v:144903.7-144903.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:69" + wire \is_cmp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:70" + wire \is_cmpeqb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:67" + wire \is_negative + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:65" + wire \is_nzero + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:66" + wire \is_positive + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 17 \logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 40 \logical_op__data_len$18 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 2 \logical_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 output 25 \logical_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 3 \logical_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 26 \logical_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 4 \logical_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 27 \logical_op__imm_data__ok$5 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 11 \logical_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 34 \logical_op__input_carry$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 18 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 41 \logical_op__insn$19 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \logical_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 24 \logical_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 32 \logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 35 \logical_op__invert_out$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 15 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 38 \logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 16 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 39 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 7 \logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 30 \logical_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 31 \logical_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 37 \logical_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 6 \logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 29 \logical_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 5 \logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 28 \logical_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 36 \logical_op__write_cr0$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 33 \logical_op__zero_a$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:68" + wire \msb_test + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 46 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 23 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 input 19 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 42 \o$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:38" + wire width 65 \o$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire input 20 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 43 \o_ok$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:50" + wire width 64 \target + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire input 22 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" + cell $and $and$libresoc.v:145223$7865 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_nzero + connect \B \$36 + connect \Y $and$libresoc.v:145223$7865_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" + cell $eq $eq$libresoc.v:145219$7861 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \logical_op__insn_type + connect \B 7'0001010 + connect \Y $eq$libresoc.v:145219$7861_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" + cell $eq $eq$libresoc.v:145220$7862 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \logical_op__insn_type + connect \B 7'0001100 + connect \Y $eq$libresoc.v:145220$7862_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" + cell $pos $extend$libresoc.v:145217$7857 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \$25 + connect \Y $extend$libresoc.v:145217$7857_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + cell $pos $extend$libresoc.v:145218$7859 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \o + connect \Y $extend$libresoc.v:145218$7859_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" + cell $not $not$libresoc.v:145216$7856 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \o + connect \Y $not$libresoc.v:145216$7856_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" + cell $not $not$libresoc.v:145222$7864 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \msb_test + connect \Y $not$libresoc.v:145222$7864_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" + cell $not $not$libresoc.v:145225$7867 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_nzero + connect \Y $not$libresoc.v:145225$7867_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" + cell $or $or$libresoc.v:145224$7866 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_cmpeqb + connect \B \is_cmp + connect \Y $or$libresoc.v:145224$7866_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" + cell $pos $pos$libresoc.v:145217$7858 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \Y_WIDTH 65 + connect \A $extend$libresoc.v:145217$7857_Y + connect \Y $pos$libresoc.v:145217$7858_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + cell $pos $pos$libresoc.v:145218$7860 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \Y_WIDTH 65 + connect \A $extend$libresoc.v:145218$7859_Y + connect \Y $pos$libresoc.v:145218$7860_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" + cell $reduce_or $reduce_or$libresoc.v:145221$7863 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 1 + connect \A \target + connect \Y $reduce_or$libresoc.v:145221$7863_Y + end + attribute \src "libresoc.v:144903.7-144903.20" + process $proc$libresoc.v:144903$7872 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:145226.3-145237.6" + process $proc$libresoc.v:145226$7868 + assign { } { } + assign $0\o$23[64:0]$7869 $1\o$23[64:0]$7870 + attribute \src "libresoc.v:145227.5-145227.29" + switch \initial + attribute \src "libresoc.v:145227.9-145227.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:40" + switch \logical_op__invert_out + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\o$23[64:0]$7870 \$24 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\o$23[64:0]$7870 \$28 + end + sync always + update \o$23 $0\o$23[64:0]$7869 + end + attribute \src "libresoc.v:145238.3-145249.6" + process $proc$libresoc.v:145238$7871 + assign { } { } + assign $0\cr0[3:0] $1\cr0[3:0] + attribute \src "libresoc.v:145239.5-145239.29" + switch \initial + attribute \src "libresoc.v:145239.9-145239.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" + switch \$40 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cr0[3:0] \cr_a + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cr0[3:0] { \is_negative \is_positive \$42 \xer_so } + end + sync always + update \cr0 $0\cr0[3:0] + end + connect \$25 $not$libresoc.v:145216$7856_Y + connect \$24 $pos$libresoc.v:145217$7858_Y + connect \$28 $pos$libresoc.v:145218$7860_Y + connect \$30 $eq$libresoc.v:145219$7861_Y + connect \$32 $eq$libresoc.v:145220$7862_Y + connect \$34 $reduce_or$libresoc.v:145221$7863_Y + connect \$36 $not$libresoc.v:145222$7864_Y + connect \$38 $and$libresoc.v:145223$7865_Y + connect \$40 $or$libresoc.v:145224$7866_Y + connect \$42 $not$libresoc.v:145225$7867_Y + connect { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } + connect \muxid$1 \muxid + connect \cr_a_ok \logical_op__write_cr0 + connect \cr_a$22 \cr0 + connect \o_ok$21 \o_ok + connect \o$20 \o$23 [63:0] + connect \is_positive \$38 + connect \is_negative \msb_test + connect \is_nzero \$34 + connect \msb_test \target [63] + connect \is_cmpeqb \$32 + connect \is_cmp \$30 + connect \target \o$23 [63:0] +end +attribute \src "libresoc.v:145267.1-145711.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_end.output" +attribute \generator "nMigen" +module \output$80 + attribute \src "libresoc.v:145632.3-145643.6" + wire width 4 $0\cr0[3:0] + attribute \src "libresoc.v:145268.7-145268.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:145644.3-145655.6" + wire width 65 $0\o$27[64:0]$7891 + attribute \src "libresoc.v:145620.3-145631.6" + wire $0\so[0:0] + attribute \src "libresoc.v:145676.3-145685.6" + wire width 2 $0\xer_ov$23[1:0]$7898 + attribute \src "libresoc.v:145686.3-145695.6" + wire $0\xer_ov_ok[0:0] + attribute \src "libresoc.v:145656.3-145665.6" + wire $0\xer_so$24[0:0]$7894 + attribute \src "libresoc.v:145666.3-145675.6" + wire $0\xer_so_ok[0:0] + attribute \src "libresoc.v:145632.3-145643.6" + wire width 4 $1\cr0[3:0] + attribute \src "libresoc.v:145644.3-145655.6" + wire width 65 $1\o$27[64:0]$7892 + attribute \src "libresoc.v:145620.3-145631.6" + wire $1\so[0:0] + attribute \src "libresoc.v:145676.3-145685.6" + wire width 2 $1\xer_ov$23[1:0]$7899 + attribute \src "libresoc.v:145686.3-145695.6" + wire $1\xer_ov_ok[0:0] + attribute \src "libresoc.v:145656.3-145665.6" + wire $1\xer_so$24[0:0]$7895 + attribute \src "libresoc.v:145666.3-145675.6" + wire $1\xer_so_ok[0:0] + attribute \src "libresoc.v:145607.18-145607.136" + wire $and$libresoc.v:145607$7873_Y + attribute \src "libresoc.v:145615.18-145615.112" + wire $and$libresoc.v:145615$7883_Y + attribute \src "libresoc.v:145618.18-145618.133" + wire $and$libresoc.v:145618$7886_Y + attribute \src "libresoc.v:145611.18-145611.127" + wire $eq$libresoc.v:145611$7879_Y + attribute \src "libresoc.v:145612.18-145612.127" + wire $eq$libresoc.v:145612$7880_Y + attribute \src "libresoc.v:145609.18-145609.103" + wire width 65 $extend$libresoc.v:145609$7875_Y + attribute \src "libresoc.v:145610.18-145610.101" + wire width 65 $extend$libresoc.v:145610$7877_Y + attribute \src "libresoc.v:145608.18-145608.100" + wire width 64 $not$libresoc.v:145608$7874_Y + attribute \src "libresoc.v:145614.18-145614.107" + wire $not$libresoc.v:145614$7882_Y + attribute \src "libresoc.v:145617.18-145617.107" + wire $not$libresoc.v:145617$7885_Y + attribute \src "libresoc.v:145616.18-145616.115" + wire $or$libresoc.v:145616$7884_Y + attribute \src "libresoc.v:145619.18-145619.112" + wire $or$libresoc.v:145619$7887_Y + attribute \src "libresoc.v:145609.18-145609.103" + wire width 65 $pos$libresoc.v:145609$7876_Y + attribute \src "libresoc.v:145610.18-145610.101" + wire width 65 $pos$libresoc.v:145610$7878_Y + attribute \src "libresoc.v:145613.18-145613.105" + wire $reduce_or$libresoc.v:145613$7881_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29" + wire \$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" + wire width 65 \$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" + wire width 64 \$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 65 \$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" + wire \$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" + wire \$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" + wire \$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" + wire \$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" + wire \$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" + wire \$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" + wire \$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" + wire \$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:33" + wire \$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:71" + wire width 4 \cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 input 21 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 output 45 \cr_a$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 46 \cr_a_ok + attribute \src "libresoc.v:145268.7-145268.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:69" + wire \is_cmp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:70" + wire \is_cmpeqb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:67" + wire \is_negative + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:65" + wire \is_nzero + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:66" + wire \is_positive + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 17 \logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 41 \logical_op__data_len$18 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 2 \logical_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 output 26 \logical_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 3 \logical_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 27 \logical_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 4 \logical_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 28 \logical_op__imm_data__ok$5 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 11 \logical_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 35 \logical_op__input_carry$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 18 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 42 \logical_op__insn$19 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \logical_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 25 \logical_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 33 \logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 36 \logical_op__invert_out$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 15 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 39 \logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 16 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 40 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 7 \logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 31 \logical_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 32 \logical_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 38 \logical_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 6 \logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 30 \logical_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 5 \logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 29 \logical_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 37 \logical_op__write_cr0$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 34 \logical_op__zero_a$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:68" + wire \msb_test + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 51 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 24 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 input 19 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 43 \o$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:38" + wire width 65 \o$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire input 20 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 44 \o_ok$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:28" + wire \oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:29" + wire \oe$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:27" + wire \so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:50" + wire width 64 \target + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 input 22 \xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 output 47 \xer_ov$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 48 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire input 23 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 49 \xer_so$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 50 \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29" + cell $and $and$libresoc.v:145607$7873 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \logical_op__oe__oe + connect \B \logical_op__oe__ok + connect \Y $and$libresoc.v:145607$7873_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" + cell $and $and$libresoc.v:145615$7883 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_nzero + connect \B \$40 + connect \Y $and$libresoc.v:145615$7883_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" + cell $and $and$libresoc.v:145618$7886 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \logical_op__oe__oe + connect \B \logical_op__oe__ok + connect \Y $and$libresoc.v:145618$7886_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" + cell $eq $eq$libresoc.v:145611$7879 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \logical_op__insn_type + connect \B 7'0001010 + connect \Y $eq$libresoc.v:145611$7879_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" + cell $eq $eq$libresoc.v:145612$7880 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \logical_op__insn_type + connect \B 7'0001100 + connect \Y $eq$libresoc.v:145612$7880_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" + cell $pos $extend$libresoc.v:145609$7875 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \$29 + connect \Y $extend$libresoc.v:145609$7875_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + cell $pos $extend$libresoc.v:145610$7877 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \o + connect \Y $extend$libresoc.v:145610$7877_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" + cell $not $not$libresoc.v:145608$7874 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \o + connect \Y $not$libresoc.v:145608$7874_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" + cell $not $not$libresoc.v:145614$7882 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \msb_test + connect \Y $not$libresoc.v:145614$7882_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" + cell $not $not$libresoc.v:145617$7885 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_nzero + connect \Y $not$libresoc.v:145617$7885_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" + cell $or $or$libresoc.v:145616$7884 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_cmpeqb + connect \B \is_cmp + connect \Y $or$libresoc.v:145616$7884_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:33" + cell $or $or$libresoc.v:145619$7887 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \xer_so + connect \B \xer_ov [0] + connect \Y $or$libresoc.v:145619$7887_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" + cell $pos $pos$libresoc.v:145609$7876 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \Y_WIDTH 65 + connect \A $extend$libresoc.v:145609$7875_Y + connect \Y $pos$libresoc.v:145609$7876_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + cell $pos $pos$libresoc.v:145610$7878 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \Y_WIDTH 65 + connect \A $extend$libresoc.v:145610$7877_Y + connect \Y $pos$libresoc.v:145610$7878_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" + cell $reduce_or $reduce_or$libresoc.v:145613$7881 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 1 + connect \A \target + connect \Y $reduce_or$libresoc.v:145613$7881_Y + end + attribute \src "libresoc.v:145268.7-145268.20" + process $proc$libresoc.v:145268$7901 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:145620.3-145631.6" + process $proc$libresoc.v:145620$7888 + assign { } { } + assign $0\so[0:0] $1\so[0:0] + attribute \src "libresoc.v:145621.5-145621.29" + switch \initial + attribute \src "libresoc.v:145621.9-145621.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:30" + switch \oe + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\so[0:0] \xer_so$24 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\so[0:0] \xer_so + end + sync always + update \so $0\so[0:0] + end + attribute \src "libresoc.v:145632.3-145643.6" + process $proc$libresoc.v:145632$7889 + assign { } { } + assign $0\cr0[3:0] $1\cr0[3:0] + attribute \src "libresoc.v:145633.5-145633.29" + switch \initial + attribute \src "libresoc.v:145633.9-145633.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" + switch \$44 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cr0[3:0] \cr_a + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cr0[3:0] { \is_negative \is_positive \$46 \so } + end + sync always + update \cr0 $0\cr0[3:0] + end + attribute \src "libresoc.v:145644.3-145655.6" + process $proc$libresoc.v:145644$7890 + assign { } { } + assign $0\o$27[64:0]$7891 $1\o$27[64:0]$7892 + attribute \src "libresoc.v:145645.5-145645.29" + switch \initial + attribute \src "libresoc.v:145645.9-145645.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:40" + switch \logical_op__invert_out + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\o$27[64:0]$7892 \$28 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\o$27[64:0]$7892 \$32 + end + sync always + update \o$27 $0\o$27[64:0]$7891 + end + attribute \src "libresoc.v:145656.3-145665.6" + process $proc$libresoc.v:145656$7893 + assign { } { } + assign { } { } + assign $0\xer_so$24[0:0]$7894 $1\xer_so$24[0:0]$7895 + attribute \src "libresoc.v:145657.5-145657.29" + switch \initial + attribute \src "libresoc.v:145657.9-145657.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" + switch \oe$48 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\xer_so$24[0:0]$7895 \$51 + case + assign $1\xer_so$24[0:0]$7895 1'0 + end + sync always + update \xer_so$24 $0\xer_so$24[0:0]$7894 + end + attribute \src "libresoc.v:145666.3-145675.6" + process $proc$libresoc.v:145666$7896 + assign { } { } + assign { } { } + assign $0\xer_so_ok[0:0] $1\xer_so_ok[0:0] + attribute \src "libresoc.v:145667.5-145667.29" + switch \initial + attribute \src "libresoc.v:145667.9-145667.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" + switch \oe$48 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\xer_so_ok[0:0] 1'1 + case + assign $1\xer_so_ok[0:0] 1'0 + end + sync always + update \xer_so_ok $0\xer_so_ok[0:0] + end + attribute \src "libresoc.v:145676.3-145685.6" + process $proc$libresoc.v:145676$7897 + assign { } { } + assign { } { } + assign $0\xer_ov$23[1:0]$7898 $1\xer_ov$23[1:0]$7899 + attribute \src "libresoc.v:145677.5-145677.29" + switch \initial + attribute \src "libresoc.v:145677.9-145677.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" + switch \oe$48 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\xer_ov$23[1:0]$7899 \xer_ov + case + assign $1\xer_ov$23[1:0]$7899 2'00 + end + sync always + update \xer_ov$23 $0\xer_ov$23[1:0]$7898 + end + attribute \src "libresoc.v:145686.3-145695.6" + process $proc$libresoc.v:145686$7900 + assign { } { } + assign { } { } + assign $0\xer_ov_ok[0:0] $1\xer_ov_ok[0:0] + attribute \src "libresoc.v:145687.5-145687.29" + switch \initial + attribute \src "libresoc.v:145687.9-145687.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" + switch \oe$48 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\xer_ov_ok[0:0] 1'1 + case + assign $1\xer_ov_ok[0:0] 1'0 + end + sync always + update \xer_ov_ok $0\xer_ov_ok[0:0] + end + connect \$25 $and$libresoc.v:145607$7873_Y + connect \$29 $not$libresoc.v:145608$7874_Y + connect \$28 $pos$libresoc.v:145609$7876_Y + connect \$32 $pos$libresoc.v:145610$7878_Y + connect \$34 $eq$libresoc.v:145611$7879_Y + connect \$36 $eq$libresoc.v:145612$7880_Y + connect \$38 $reduce_or$libresoc.v:145613$7881_Y + connect \$40 $not$libresoc.v:145614$7882_Y + connect \$42 $and$libresoc.v:145615$7883_Y + connect \$44 $or$libresoc.v:145616$7884_Y + connect \$46 $not$libresoc.v:145617$7885_Y + connect \$49 $and$libresoc.v:145618$7886_Y + connect \$51 $or$libresoc.v:145619$7887_Y + connect \oe$48 \$49 + connect { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } + connect \muxid$1 \muxid + connect \cr_a_ok \logical_op__write_cr0 + connect \cr_a$22 \cr0 + connect \o_ok$21 \o_ok + connect \o$20 \o$27 [63:0] + connect \is_positive \$42 + connect \is_negative \msb_test + connect \is_nzero \$38 + connect \msb_test \target [63] + connect \is_cmpeqb \$36 + connect \is_cmp \$34 + connect \target \o$27 [63:0] + connect \oe \$25 +end +attribute \src "libresoc.v:145715.1-146110.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe3.output" +attribute \generator "nMigen" +module \output$97 + attribute \src "libresoc.v:146042.3-146053.6" + wire width 4 $0\cr0[3:0] + attribute \src "libresoc.v:145716.7-145716.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:146030.3-146041.6" + wire $0\so[0:0] + attribute \src "libresoc.v:146074.3-146083.6" + wire width 2 $0\xer_ov$17[1:0]$7921 + attribute \src "libresoc.v:146084.3-146093.6" + wire $0\xer_ov_ok[0:0] + attribute \src "libresoc.v:146054.3-146063.6" + wire $0\xer_so$18[0:0]$7917 + attribute \src "libresoc.v:146064.3-146073.6" + wire $0\xer_so_ok[0:0] + attribute \src "libresoc.v:146042.3-146053.6" + wire width 4 $1\cr0[3:0] + attribute \src "libresoc.v:146030.3-146041.6" + wire $1\so[0:0] + attribute \src "libresoc.v:146074.3-146083.6" + wire width 2 $1\xer_ov$17[1:0]$7922 + attribute \src "libresoc.v:146084.3-146093.6" + wire $1\xer_ov_ok[0:0] + attribute \src "libresoc.v:146054.3-146063.6" + wire $1\xer_so$18[0:0]$7918 + attribute \src "libresoc.v:146064.3-146073.6" + wire $1\xer_so_ok[0:0] + attribute \src "libresoc.v:146019.18-146019.128" + wire $and$libresoc.v:146019$7902_Y + attribute \src "libresoc.v:146025.18-146025.112" + wire $and$libresoc.v:146025$7909_Y + attribute \src "libresoc.v:146028.18-146028.125" + wire $and$libresoc.v:146028$7912_Y + attribute \src "libresoc.v:146021.18-146021.123" + wire $eq$libresoc.v:146021$7905_Y + attribute \src "libresoc.v:146022.18-146022.123" + wire $eq$libresoc.v:146022$7906_Y + attribute \src "libresoc.v:146020.18-146020.101" + wire width 65 $extend$libresoc.v:146020$7903_Y + attribute \src "libresoc.v:146024.18-146024.107" + wire $not$libresoc.v:146024$7908_Y + attribute \src "libresoc.v:146027.18-146027.107" + wire $not$libresoc.v:146027$7911_Y + attribute \src "libresoc.v:146026.18-146026.115" + wire $or$libresoc.v:146026$7910_Y + attribute \src "libresoc.v:146029.18-146029.112" + wire $or$libresoc.v:146029$7913_Y + attribute \src "libresoc.v:146020.18-146020.101" + wire width 65 $pos$libresoc.v:146020$7904_Y + attribute \src "libresoc.v:146023.18-146023.105" + wire $reduce_or$libresoc.v:146023$7907_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 65 \$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" + wire \$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" + wire \$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" + wire \$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" + wire \$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" + wire \$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" + wire \$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:33" + wire \$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:71" + wire width 4 \cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 input 15 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 output 33 \cr_a$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 34 \cr_a_ok + attribute \src "libresoc.v:145716.7-145716.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:69" + wire \is_cmp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:70" + wire \is_cmpeqb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:67" + wire \is_negative + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:65" + wire \is_nzero + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:66" + wire \is_positive + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:68" + wire \msb_test + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 2 \mul_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 output 20 \mul_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 3 \mul_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 21 \mul_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 4 \mul_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 22 \mul_op__imm_data__ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 12 \mul_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 30 \mul_op__insn$13 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \mul_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 19 \mul_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \mul_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 28 \mul_op__is_32bit$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 11 \mul_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 29 \mul_op__is_signed$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 7 \mul_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 25 \mul_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \mul_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 26 \mul_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 6 \mul_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 24 \mul_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 5 \mul_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 23 \mul_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \mul_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 27 \mul_op__write_cr0$10 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 39 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 18 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 input 13 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 31 \o$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:38" + wire width 65 \o$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire input 14 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 32 \o_ok$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:28" + wire \oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:29" + wire \oe$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:27" + wire \so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:50" + wire width 64 \target + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 input 16 \xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 output 35 \xer_ov$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 36 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire input 17 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 37 \xer_so$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 38 \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29" + cell $and $and$libresoc.v:146019$7902 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \mul_op__oe__oe + connect \B \mul_op__oe__ok + connect \Y $and$libresoc.v:146019$7902_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" + cell $and $and$libresoc.v:146025$7909 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_nzero + connect \B \$30 + connect \Y $and$libresoc.v:146025$7909_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" + cell $and $and$libresoc.v:146028$7912 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \mul_op__oe__oe + connect \B \mul_op__oe__ok + connect \Y $and$libresoc.v:146028$7912_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" + cell $eq $eq$libresoc.v:146021$7905 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \mul_op__insn_type + connect \B 7'0001010 + connect \Y $eq$libresoc.v:146021$7905_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" + cell $eq $eq$libresoc.v:146022$7906 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \mul_op__insn_type + connect \B 7'0001100 + connect \Y $eq$libresoc.v:146022$7906_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + cell $pos $extend$libresoc.v:146020$7903 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \o + connect \Y $extend$libresoc.v:146020$7903_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" + cell $not $not$libresoc.v:146024$7908 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \msb_test + connect \Y $not$libresoc.v:146024$7908_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" + cell $not $not$libresoc.v:146027$7911 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_nzero + connect \Y $not$libresoc.v:146027$7911_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" + cell $or $or$libresoc.v:146026$7910 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_cmpeqb + connect \B \is_cmp + connect \Y $or$libresoc.v:146026$7910_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:33" + cell $or $or$libresoc.v:146029$7913 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \xer_so + connect \B \xer_ov [0] + connect \Y $or$libresoc.v:146029$7913_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + cell $pos $pos$libresoc.v:146020$7904 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \Y_WIDTH 65 + connect \A $extend$libresoc.v:146020$7903_Y + connect \Y $pos$libresoc.v:146020$7904_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" + cell $reduce_or $reduce_or$libresoc.v:146023$7907 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 1 + connect \A \target + connect \Y $reduce_or$libresoc.v:146023$7907_Y + end + attribute \src "libresoc.v:145716.7-145716.20" + process $proc$libresoc.v:145716$7924 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:146030.3-146041.6" + process $proc$libresoc.v:146030$7914 + assign { } { } + assign $0\so[0:0] $1\so[0:0] + attribute \src "libresoc.v:146031.5-146031.29" + switch \initial + attribute \src "libresoc.v:146031.9-146031.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:30" + switch \oe + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\so[0:0] \xer_so$18 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\so[0:0] \xer_so + end + sync always + update \so $0\so[0:0] + end + attribute \src "libresoc.v:146042.3-146053.6" + process $proc$libresoc.v:146042$7915 + assign { } { } + assign $0\cr0[3:0] $1\cr0[3:0] + attribute \src "libresoc.v:146043.5-146043.29" + switch \initial + attribute \src "libresoc.v:146043.9-146043.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" + switch \$34 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cr0[3:0] \cr_a + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cr0[3:0] { \is_negative \is_positive \$36 \so } + end + sync always + update \cr0 $0\cr0[3:0] + end + attribute \src "libresoc.v:146054.3-146063.6" + process $proc$libresoc.v:146054$7916 + assign { } { } + assign { } { } + assign $0\xer_so$18[0:0]$7917 $1\xer_so$18[0:0]$7918 + attribute \src "libresoc.v:146055.5-146055.29" + switch \initial + attribute \src "libresoc.v:146055.9-146055.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" + switch \oe$38 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\xer_so$18[0:0]$7918 \$41 + case + assign $1\xer_so$18[0:0]$7918 1'0 + end + sync always + update \xer_so$18 $0\xer_so$18[0:0]$7917 + end + attribute \src "libresoc.v:146064.3-146073.6" + process $proc$libresoc.v:146064$7919 + assign { } { } + assign { } { } + assign $0\xer_so_ok[0:0] $1\xer_so_ok[0:0] + attribute \src "libresoc.v:146065.5-146065.29" + switch \initial + attribute \src "libresoc.v:146065.9-146065.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" + switch \oe$38 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\xer_so_ok[0:0] 1'1 + case + assign $1\xer_so_ok[0:0] 1'0 + end + sync always + update \xer_so_ok $0\xer_so_ok[0:0] + end + attribute \src "libresoc.v:146074.3-146083.6" + process $proc$libresoc.v:146074$7920 + assign { } { } + assign { } { } + assign $0\xer_ov$17[1:0]$7921 $1\xer_ov$17[1:0]$7922 + attribute \src "libresoc.v:146075.5-146075.29" + switch \initial + attribute \src "libresoc.v:146075.9-146075.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" + switch \oe$38 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\xer_ov$17[1:0]$7922 \xer_ov + case + assign $1\xer_ov$17[1:0]$7922 2'00 + end + sync always + update \xer_ov$17 $0\xer_ov$17[1:0]$7921 + end + attribute \src "libresoc.v:146084.3-146093.6" + process $proc$libresoc.v:146084$7923 + assign { } { } + assign { } { } + assign $0\xer_ov_ok[0:0] $1\xer_ov_ok[0:0] + attribute \src "libresoc.v:146085.5-146085.29" + switch \initial + attribute \src "libresoc.v:146085.9-146085.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" + switch \oe$38 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\xer_ov_ok[0:0] 1'1 + case + assign $1\xer_ov_ok[0:0] 1'0 + end + sync always + update \xer_ov_ok $0\xer_ov_ok[0:0] + end + connect \$19 $and$libresoc.v:146019$7902_Y + connect \$22 $pos$libresoc.v:146020$7904_Y + connect \$24 $eq$libresoc.v:146021$7905_Y + connect \$26 $eq$libresoc.v:146022$7906_Y + connect \$28 $reduce_or$libresoc.v:146023$7907_Y + connect \$30 $not$libresoc.v:146024$7908_Y + connect \$32 $and$libresoc.v:146025$7909_Y + connect \$34 $or$libresoc.v:146026$7910_Y + connect \$36 $not$libresoc.v:146027$7911_Y + connect \$39 $and$libresoc.v:146028$7912_Y + connect \$41 $or$libresoc.v:146029$7913_Y + connect \oe$38 \$39 + connect { \mul_op__insn$13 \mul_op__is_signed$12 \mul_op__is_32bit$11 \mul_op__write_cr0$10 \mul_op__oe__ok$9 \mul_op__oe__oe$8 \mul_op__rc__ok$7 \mul_op__rc__rc$6 \mul_op__imm_data__ok$5 \mul_op__imm_data__data$4 \mul_op__fn_unit$3 \mul_op__insn_type$2 } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__oe__ok \mul_op__oe__oe \mul_op__rc__ok \mul_op__rc__rc \mul_op__imm_data__ok \mul_op__imm_data__data \mul_op__fn_unit \mul_op__insn_type } + connect \muxid$1 \muxid + connect \cr_a_ok \mul_op__write_cr0 + connect \cr_a$16 \cr0 + connect \o_ok$15 \o_ok + connect \o$14 \o$21 [63:0] + connect \is_positive \$32 + connect \is_negative \msb_test + connect \is_nzero \$28 + connect \msb_test \target [63] + connect \is_cmpeqb \$26 + connect \is_cmp \$24 + connect \target \o$21 [63:0] + connect \o$21 \$22 + connect \oe \$19 +end +attribute \src "libresoc.v:146114.1-146584.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_end.output_stage" +attribute \generator "nMigen" +module \output_stage + attribute \src "libresoc.v:146115.7-146115.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:146501.3-146572.6" + wire width 64 $0\o[63:0] + attribute \src "libresoc.v:146467.3-146500.6" + wire $0\ov[0:0] + attribute \src "libresoc.v:146501.3-146572.6" + wire width 64 $1\o[63:0] + attribute \src "libresoc.v:146467.3-146500.6" + wire $1\ov[0:0] + attribute \src "libresoc.v:146501.3-146572.6" + wire width 64 $2\o[63:0] + attribute \src "libresoc.v:146467.3-146500.6" + wire $2\ov[0:0] + attribute \src "libresoc.v:146501.3-146572.6" + wire width 64 $3\o[63:0] + attribute \src "libresoc.v:146467.3-146500.6" + wire $3\ov[0:0] + attribute \src "libresoc.v:146501.3-146572.6" + wire width 64 $4\o[63:0] + attribute \src "libresoc.v:146501.3-146572.6" + wire width 64 $5\o[63:0] + attribute \src "libresoc.v:146501.3-146572.6" + wire width 64 $6\o[63:0] + attribute \src "libresoc.v:146501.3-146572.6" + wire width 64 $7\o[63:0] + attribute \src "libresoc.v:146501.3-146572.6" + wire width 64 $8\o[63:0] + attribute \src "libresoc.v:146458.18-146458.122" + wire $and$libresoc.v:146458$7938_Y + attribute \src "libresoc.v:146450.18-146450.109" + wire width 65 $extend$libresoc.v:146450$7926_Y + attribute \src "libresoc.v:146451.18-146451.100" + wire width 65 $extend$libresoc.v:146451$7928_Y + attribute \src "libresoc.v:146453.18-146453.113" + wire width 65 $extend$libresoc.v:146453$7931_Y + attribute \src "libresoc.v:146454.18-146454.104" + wire width 65 $extend$libresoc.v:146454$7933_Y + attribute \src "libresoc.v:146461.18-146461.114" + wire width 64 $extend$libresoc.v:146461$7941_Y + attribute \src "libresoc.v:146462.18-146462.114" + wire width 64 $extend$libresoc.v:146462$7943_Y + attribute \src "libresoc.v:146463.18-146463.114" + wire width 64 $extend$libresoc.v:146463$7945_Y + attribute \src "libresoc.v:146464.18-146464.114" + wire width 64 $extend$libresoc.v:146464$7947_Y + attribute \src "libresoc.v:146466.18-146466.115" + wire width 64 $extend$libresoc.v:146466$7950_Y + attribute \src "libresoc.v:146459.18-146459.128" + wire $ne$libresoc.v:146459$7939_Y + attribute \src "libresoc.v:146450.18-146450.109" + wire width 65 $neg$libresoc.v:146450$7927_Y + attribute \src "libresoc.v:146453.18-146453.113" + wire width 65 $neg$libresoc.v:146453$7932_Y + attribute \src "libresoc.v:146456.18-146456.116" + wire $not$libresoc.v:146456$7936_Y + attribute \src "libresoc.v:146460.18-146460.98" + wire $not$libresoc.v:146460$7940_Y + attribute \src "libresoc.v:146451.18-146451.100" + wire width 65 $pos$libresoc.v:146451$7929_Y + attribute \src "libresoc.v:146454.18-146454.104" + wire width 65 $pos$libresoc.v:146454$7934_Y + attribute \src "libresoc.v:146461.18-146461.114" + wire width 64 $pos$libresoc.v:146461$7942_Y + attribute \src "libresoc.v:146462.18-146462.114" + wire width 64 $pos$libresoc.v:146462$7944_Y + attribute \src "libresoc.v:146463.18-146463.114" + wire width 64 $pos$libresoc.v:146463$7946_Y + attribute \src "libresoc.v:146464.18-146464.114" + wire width 64 $pos$libresoc.v:146464$7948_Y + attribute \src "libresoc.v:146465.18-146465.124" + wire width 64 $pos$libresoc.v:146465$7949_Y + attribute \src "libresoc.v:146466.18-146466.115" + wire width 64 $pos$libresoc.v:146466$7951_Y + attribute \src "libresoc.v:146452.18-146452.121" + wire width 65 $ternary$libresoc.v:146452$7930_Y + attribute \src "libresoc.v:146455.18-146455.122" + wire width 65 $ternary$libresoc.v:146455$7935_Y + attribute \src "libresoc.v:146449.18-146449.120" + wire $xor$libresoc.v:146449$7925_Y + attribute \src "libresoc.v:146457.18-146457.127" + wire $xor$libresoc.v:146457$7937_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:55" + wire \$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:65" + wire width 65 \$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" + wire width 65 \$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:65" + wire width 65 \$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67" + wire width 65 \$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67" + wire width 65 \$30 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" + wire width 65 \$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67" + wire width 65 \$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:78" + wire \$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:80" + wire \$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:80" + wire \$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:84" + wire \$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:96" + wire \$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:102" + wire width 64 \$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:104" + wire width 64 \$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:111" + wire width 64 \$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:113" + wire width 64 \$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:120" + wire width 64 \$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:122" + wire width 64 \$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire input 24 \div_by_zero + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire input 22 \dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire input 23 \dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire input 21 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire input 20 \divisor_neg + attribute \src "libresoc.v:146115.7-146115.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 17 \logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 44 \logical_op__data_len$18 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 2 \logical_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 output 29 \logical_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 3 \logical_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 30 \logical_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 4 \logical_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 31 \logical_op__imm_data__ok$5 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 11 \logical_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 38 \logical_op__input_carry$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 18 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 45 \logical_op__insn$19 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \logical_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 28 \logical_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 36 \logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 39 \logical_op__invert_out$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 15 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 42 \logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 16 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 43 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 7 \logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 34 \logical_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 35 \logical_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 41 \logical_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 6 \logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 33 \logical_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 5 \logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 32 \logical_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 40 \logical_op__write_cr0$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 37 \logical_op__zero_a$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 51 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 27 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 46 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 47 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:75" + wire \ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:26" + wire width 65 \quotient_65 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:24" + wire \quotient_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" + wire width 64 input 25 \quotient_root + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:41" + wire width 192 input 26 \remainder + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:27" + wire width 64 \remainder_64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:25" + wire \remainder_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 output 48 \xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 49 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 19 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 50 \xer_so$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:80" + cell $and $and$libresoc.v:146458$7938 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \logical_op__is_signed + connect \B \$38 + connect \Y $and$libresoc.v:146458$7938_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:65" + cell $pos $extend$libresoc.v:146450$7926 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \quotient_root + connect \Y $extend$libresoc.v:146450$7926_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" + cell $pos $extend$libresoc.v:146451$7928 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \quotient_root + connect \Y $extend$libresoc.v:146451$7928_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67" + cell $pos $extend$libresoc.v:146453$7931 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \remainder [127:64] + connect \Y $extend$libresoc.v:146453$7931_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" + cell $pos $extend$libresoc.v:146454$7933 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \remainder [127:64] + connect \Y $extend$libresoc.v:146454$7933_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:102" + cell $pos $extend$libresoc.v:146461$7941 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \Y_WIDTH 64 + connect \A \quotient_65 [31:0] + connect \Y $extend$libresoc.v:146461$7941_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:104" + cell $pos $extend$libresoc.v:146462$7943 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \Y_WIDTH 64 + connect \A \quotient_65 [31:0] + connect \Y $extend$libresoc.v:146462$7943_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:111" + cell $pos $extend$libresoc.v:146463$7945 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \Y_WIDTH 64 + connect \A \quotient_65 [31:0] + connect \Y $extend$libresoc.v:146463$7945_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:113" + cell $pos $extend$libresoc.v:146464$7947 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \Y_WIDTH 64 + connect \A \quotient_65 [31:0] + connect \Y $extend$libresoc.v:146464$7947_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:122" + cell $pos $extend$libresoc.v:146466$7950 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \Y_WIDTH 64 + connect \A \remainder_64 [31:0] + connect \Y $extend$libresoc.v:146466$7950_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:84" + cell $ne $ne$libresoc.v:146459$7939 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \quotient_65 [32] + connect \B \quotient_65 [31] + connect \Y $ne$libresoc.v:146459$7939_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:65" + cell $neg $neg$libresoc.v:146450$7927 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \Y_WIDTH 65 + connect \A $extend$libresoc.v:146450$7926_Y + connect \Y $neg$libresoc.v:146450$7927_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67" + cell $neg $neg$libresoc.v:146453$7932 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \Y_WIDTH 65 + connect \A $extend$libresoc.v:146453$7931_Y + connect \Y $neg$libresoc.v:146453$7932_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:78" + cell $not $not$libresoc.v:146456$7936 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \logical_op__is_32bit + connect \Y $not$libresoc.v:146456$7936_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:96" + cell $not $not$libresoc.v:146460$7940 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ov + connect \Y $not$libresoc.v:146460$7940_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" + cell $pos $pos$libresoc.v:146451$7929 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \Y_WIDTH 65 + connect \A $extend$libresoc.v:146451$7928_Y + connect \Y $pos$libresoc.v:146451$7929_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" + cell $pos $pos$libresoc.v:146454$7934 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \Y_WIDTH 65 + connect \A $extend$libresoc.v:146454$7933_Y + connect \Y $pos$libresoc.v:146454$7934_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:102" + cell $pos $pos$libresoc.v:146461$7942 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:146461$7941_Y + connect \Y $pos$libresoc.v:146461$7942_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:104" + cell $pos $pos$libresoc.v:146462$7944 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:146462$7943_Y + connect \Y $pos$libresoc.v:146462$7944_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:111" + cell $pos $pos$libresoc.v:146463$7946 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:146463$7945_Y + connect \Y $pos$libresoc.v:146463$7946_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:113" + cell $pos $pos$libresoc.v:146464$7948 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:146464$7947_Y + connect \Y $pos$libresoc.v:146464$7948_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:120" + cell $pos $pos$libresoc.v:146465$7949 + parameter \A_SIGNED 1 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A { \remainder_64 [31] \remainder_64 [31] \remainder_64 [31] \remainder_64 [31] \remainder_64 [31] \remainder_64 [31] \remainder_64 [31] \remainder_64 [31] \remainder_64 [31] \remainder_64 [31] \remainder_64 [31] \remainder_64 [31] \remainder_64 [31] \remainder_64 [31] \remainder_64 [31] \remainder_64 [31] \remainder_64 [31] \remainder_64 [31] \remainder_64 [31] \remainder_64 [31] \remainder_64 [31] \remainder_64 [31] \remainder_64 [31] \remainder_64 [31] \remainder_64 [31] \remainder_64 [31] \remainder_64 [31] \remainder_64 [31] \remainder_64 [31] \remainder_64 [31] \remainder_64 [31] \remainder_64 [31] \remainder_64 [31:0] } + connect \Y $pos$libresoc.v:146465$7949_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:122" + cell $pos $pos$libresoc.v:146466$7951 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:146466$7950_Y + connect \Y $pos$libresoc.v:146466$7951_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:65" + cell $mux $ternary$libresoc.v:146452$7930 + parameter \WIDTH 65 + connect \A \$25 + connect \B \$23 + connect \S \quotient_neg + connect \Y $ternary$libresoc.v:146452$7930_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67" + cell $mux $ternary$libresoc.v:146455$7935 + parameter \WIDTH 65 + connect \A \$32 + connect \B \$30 + connect \S \remainder_neg + connect \Y $ternary$libresoc.v:146455$7935_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:55" + cell $xor $xor$libresoc.v:146449$7925 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dividend_neg + connect \B \divisor_neg + connect \Y $xor$libresoc.v:146449$7925_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:80" + cell $xor $xor$libresoc.v:146457$7937 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \quotient_65 [64] + connect \B \quotient_65 [63] + connect \Y $xor$libresoc.v:146457$7937_Y + end + attribute \src "libresoc.v:146115.7-146115.20" + process $proc$libresoc.v:146115$7954 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:146467.3-146500.6" + process $proc$libresoc.v:146467$7952 + assign { } { } + assign $0\ov[0:0] $1\ov[0:0] + attribute \src "libresoc.v:146468.5-146468.29" + switch \initial + attribute \src "libresoc.v:146468.9-146468.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:76" + switch { \logical_op__is_signed \$36 \div_by_zero } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign { } { } + assign $1\ov[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- + assign { } { } + assign { } { } + assign $1\ov[0:0] $2\ov[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:80" + switch \$40 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ov[0:0] 1'1 + case + assign $2\ov[0:0] \dive_abs_ov64 + end + attribute \src "libresoc.v:0.0-0.0" + case 3'1-- + assign { } { } + assign { } { } + assign $1\ov[0:0] $3\ov[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:84" + switch \$42 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\ov[0:0] 1'1 + case + assign $3\ov[0:0] \dive_abs_ov32 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\ov[0:0] \dive_abs_ov32 + end + sync always + update \ov $0\ov[0:0] + end + attribute \src "libresoc.v:146501.3-146572.6" + process $proc$libresoc.v:146501$7953 + assign { } { } + assign { } { } + assign $0\o[63:0] $1\o[63:0] + attribute \src "libresoc.v:146502.5-146502.29" + switch \initial + attribute \src "libresoc.v:146502.9-146502.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:96" + switch \$44 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\o[63:0] $2\o[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:97" + switch \logical_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0011110 + assign { } { } + assign $2\o[63:0] $3\o[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:99" + switch \logical_op__is_32bit + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\o[63:0] $4\o[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:100" + switch \logical_op__is_signed + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\o[63:0] \$46 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $4\o[63:0] \$48 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $3\o[63:0] \quotient_65 [63:0] + end + attribute \src "libresoc.v:0.0-0.0" + case 7'0011101 + assign { } { } + assign $2\o[63:0] $5\o[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:108" + switch \logical_op__is_32bit + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\o[63:0] $6\o[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:109" + switch \logical_op__is_signed + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\o[63:0] \$50 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $6\o[63:0] \$52 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $5\o[63:0] \quotient_65 [63:0] + end + attribute \src "libresoc.v:0.0-0.0" + case 7'0101111 + assign { } { } + assign $2\o[63:0] $7\o[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:117" + switch \logical_op__is_32bit + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\o[63:0] $8\o[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:118" + switch \logical_op__is_signed + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $8\o[63:0] \$54 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $8\o[63:0] \$56 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $7\o[63:0] \remainder_64 + end + case + assign $2\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + case + assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \o $0\o[63:0] + end + connect \$21 $xor$libresoc.v:146449$7925_Y + connect \$23 $neg$libresoc.v:146450$7927_Y + connect \$25 $pos$libresoc.v:146451$7929_Y + connect \$27 $ternary$libresoc.v:146452$7930_Y + connect \$30 $neg$libresoc.v:146453$7932_Y + connect \$32 $pos$libresoc.v:146454$7934_Y + connect \$34 $ternary$libresoc.v:146455$7935_Y + connect \$36 $not$libresoc.v:146456$7936_Y + connect \$38 $xor$libresoc.v:146457$7937_Y + connect \$40 $and$libresoc.v:146458$7938_Y + connect \$42 $ne$libresoc.v:146459$7939_Y + connect \$44 $not$libresoc.v:146460$7940_Y + connect \$46 $pos$libresoc.v:146461$7942_Y + connect \$48 $pos$libresoc.v:146462$7944_Y + connect \$50 $pos$libresoc.v:146463$7946_Y + connect \$52 $pos$libresoc.v:146464$7948_Y + connect \$54 $pos$libresoc.v:146465$7949_Y + connect \$56 $pos$libresoc.v:146466$7951_Y + connect \$29 \$34 + connect { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } + connect \muxid$1 \muxid + connect \xer_so$20 \xer_so + connect \o_ok 1'1 + connect \xer_ov { \ov \ov } + connect \xer_ov_ok 1'1 + connect \remainder_64 \$34 [63:0] + connect \quotient_65 \$27 + connect \remainder_neg \dividend_neg + connect \quotient_neg \$21 +end +attribute \src "libresoc.v:146588.1-146599.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alu_alu0.p" +attribute \generator "nMigen" +module \p + attribute \src "libresoc.v:146597.17-146597.111" + wire $and$libresoc.v:146597$7955_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire input 1 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" + wire \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + cell $and $and$libresoc.v:146597$7955 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i + connect \B \p_ready_o + connect \Y $and$libresoc.v:146597$7955_Y + end + connect \$1 $and$libresoc.v:146597$7955_Y + connect \trigger \$1 +end +attribute \src "libresoc.v:146603.1-146614.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alu_alu0.pipe1.p" +attribute \generator "nMigen" +module \p$1 + attribute \src "libresoc.v:146612.17-146612.111" + wire $and$libresoc.v:146612$7956_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire input 1 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" + wire \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + cell $and $and$libresoc.v:146612$7956 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i + connect \B \p_ready_o + connect \Y $and$libresoc.v:146612$7956_Y + end + connect \$1 $and$libresoc.v:146612$7956_Y + connect \trigger \$1 +end +attribute \src "libresoc.v:146618.1-146629.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.p" +attribute \generator "nMigen" +module \p$105 + attribute \src "libresoc.v:146627.17-146627.111" + wire $and$libresoc.v:146627$7957_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire input 1 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" + wire \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + cell $and $and$libresoc.v:146627$7957 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i + connect \B \p_ready_o + connect \Y $and$libresoc.v:146627$7957_Y + end + connect \$1 $and$libresoc.v:146627$7957_Y + connect \trigger \$1 +end +attribute \src "libresoc.v:146633.1-146644.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.pipe1.p" +attribute \generator "nMigen" +module \p$108 + attribute \src "libresoc.v:146642.17-146642.111" + wire $and$libresoc.v:146642$7958_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire input 1 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" + wire \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + cell $and $and$libresoc.v:146642$7958 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i + connect \B \p_ready_o + connect \Y $and$libresoc.v:146642$7958_Y + end + connect \$1 $and$libresoc.v:146642$7958_Y + connect \trigger \$1 +end +attribute \src "libresoc.v:146648.1-146659.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.pipe2.p" +attribute \generator "nMigen" +module \p$113 + attribute \src "libresoc.v:146657.17-146657.111" + wire $and$libresoc.v:146657$7959_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire input 1 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" + wire \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + cell $and $and$libresoc.v:146657$7959 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i + connect \B \p_ready_o + connect \Y $and$libresoc.v:146657$7959_Y + end + connect \$1 $and$libresoc.v:146657$7959_Y + connect \trigger \$1 +end +attribute \src "libresoc.v:146663.1-146674.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.alu_branch0.p" +attribute \generator "nMigen" +module \p$17 + attribute \src "libresoc.v:146672.17-146672.111" + wire $and$libresoc.v:146672$7960_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire input 1 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" + wire \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + cell $and $and$libresoc.v:146672$7960 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i + connect \B \p_ready_o + connect \Y $and$libresoc.v:146672$7960_Y + end + connect \$1 $and$libresoc.v:146672$7960_Y + connect \trigger \$1 +end +attribute \src "libresoc.v:146678.1-146689.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.alu_branch0.pipe.p" +attribute \generator "nMigen" +module \p$20 + attribute \src "libresoc.v:146687.17-146687.111" + wire $and$libresoc.v:146687$7961_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire input 1 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" + wire \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + cell $and $and$libresoc.v:146687$7961 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i + connect \B \p_ready_o + connect \Y $and$libresoc.v:146687$7961_Y + end + connect \$1 $and$libresoc.v:146687$7961_Y + connect \trigger \$1 +end +attribute \src "libresoc.v:146693.1-146704.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alu_alu0.pipe2.p" +attribute \generator "nMigen" +module \p$3 + attribute \src "libresoc.v:146702.17-146702.111" + wire $and$libresoc.v:146702$7962_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire input 1 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" + wire \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + cell $and $and$libresoc.v:146702$7962 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i + connect \B \p_ready_o + connect \Y $and$libresoc.v:146702$7962_Y + end + connect \$1 $and$libresoc.v:146702$7962_Y + connect \trigger \$1 +end +attribute \src "libresoc.v:146708.1-146719.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.alu_trap0.p" +attribute \generator "nMigen" +module \p$30 + attribute \src "libresoc.v:146717.17-146717.111" + wire $and$libresoc.v:146717$7963_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire input 1 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" + wire \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + cell $and $and$libresoc.v:146717$7963 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i + connect \B \p_ready_o + connect \Y $and$libresoc.v:146717$7963_Y + end + connect \$1 $and$libresoc.v:146717$7963_Y + connect \trigger \$1 +end +attribute \src "libresoc.v:146723.1-146734.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.alu_trap0.pipe.p" +attribute \generator "nMigen" +module \p$33 + attribute \src "libresoc.v:146732.17-146732.111" + wire $and$libresoc.v:146732$7964_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire input 1 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" + wire \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + cell $and $and$libresoc.v:146732$7964 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i + connect \B \p_ready_o + connect \Y $and$libresoc.v:146732$7964_Y + end + connect \$1 $and$libresoc.v:146732$7964_Y + connect \trigger \$1 +end +attribute \src "libresoc.v:146738.1-146749.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_logical0.p" +attribute \generator "nMigen" +module \p$43 + attribute \src "libresoc.v:146747.17-146747.111" + wire $and$libresoc.v:146747$7965_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire input 1 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" + wire \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + cell $and $and$libresoc.v:146747$7965 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i + connect \B \p_ready_o + connect \Y $and$libresoc.v:146747$7965_Y + end + connect \$1 $and$libresoc.v:146747$7965_Y + connect \trigger \$1 +end +attribute \src "libresoc.v:146753.1-146764.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_logical0.logical_pipe1.p" +attribute \generator "nMigen" +module \p$45 + attribute \src "libresoc.v:146762.17-146762.111" + wire $and$libresoc.v:146762$7966_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire input 1 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" + wire \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + cell $and $and$libresoc.v:146762$7966 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i + connect \B \p_ready_o + connect \Y $and$libresoc.v:146762$7966_Y + end + connect \$1 $and$libresoc.v:146762$7966_Y + connect \trigger \$1 +end +attribute \src "libresoc.v:146768.1-146779.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_logical0.logical_pipe2.p" +attribute \generator "nMigen" +module \p$49 + attribute \src "libresoc.v:146777.17-146777.111" + wire $and$libresoc.v:146777$7967_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire input 1 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" + wire \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + cell $and $and$libresoc.v:146777$7967 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i + connect \B \p_ready_o + connect \Y $and$libresoc.v:146777$7967_Y + end + connect \$1 $and$libresoc.v:146777$7967_Y + connect \trigger \$1 +end +attribute \src "libresoc.v:146783.1-146794.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.alu_cr0.p" +attribute \generator "nMigen" +module \p$5 + attribute \src "libresoc.v:146792.17-146792.111" + wire $and$libresoc.v:146792$7968_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire input 1 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" + wire \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + cell $and $and$libresoc.v:146792$7968 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i + connect \B \p_ready_o + connect \Y $and$libresoc.v:146792$7968_Y + end + connect \$1 $and$libresoc.v:146792$7968_Y + connect \trigger \$1 +end +attribute \src "libresoc.v:146798.1-146809.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.alu_spr0.p" +attribute \generator "nMigen" +module \p$59 + attribute \src "libresoc.v:146807.17-146807.111" + wire $and$libresoc.v:146807$7969_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire input 1 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" + wire \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + cell $and $and$libresoc.v:146807$7969 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i + connect \B \p_ready_o + connect \Y $and$libresoc.v:146807$7969_Y + end + connect \$1 $and$libresoc.v:146807$7969_Y + connect \trigger \$1 +end +attribute \src "libresoc.v:146813.1-146824.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.alu_spr0.pipe.p" +attribute \generator "nMigen" +module \p$62 + attribute \src "libresoc.v:146822.17-146822.111" + wire $and$libresoc.v:146822$7970_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire input 1 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" + wire \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + cell $and $and$libresoc.v:146822$7970 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i + connect \B \p_ready_o + connect \Y $and$libresoc.v:146822$7970_Y + end + connect \$1 $and$libresoc.v:146822$7970_Y + connect \trigger \$1 +end +attribute \src "libresoc.v:146828.1-146839.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.alu_cr0.pipe.p" +attribute \generator "nMigen" +module \p$7 + attribute \src "libresoc.v:146837.17-146837.111" + wire $and$libresoc.v:146837$7971_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire input 1 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" + wire \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + cell $and $and$libresoc.v:146837$7971 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i + connect \B \p_ready_o + connect \Y $and$libresoc.v:146837$7971_Y + end + connect \$1 $and$libresoc.v:146837$7971_Y + connect \trigger \$1 +end +attribute \src "libresoc.v:146843.1-146854.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.p" +attribute \generator "nMigen" +module \p$71 + attribute \src "libresoc.v:146852.17-146852.111" + wire $and$libresoc.v:146852$7972_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire input 1 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" + wire \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + cell $and $and$libresoc.v:146852$7972 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i + connect \B \p_ready_o + connect \Y $and$libresoc.v:146852$7972_Y + end + connect \$1 $and$libresoc.v:146852$7972_Y + connect \trigger \$1 +end +attribute \src "libresoc.v:146858.1-146869.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_start.p" +attribute \generator "nMigen" +module \p$73 + attribute \src "libresoc.v:146867.17-146867.111" + wire $and$libresoc.v:146867$7973_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire input 1 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" + wire \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + cell $and $and$libresoc.v:146867$7973 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i + connect \B \p_ready_o + connect \Y $and$libresoc.v:146867$7973_Y + end + connect \$1 $and$libresoc.v:146867$7973_Y + connect \trigger \$1 +end +attribute \src "libresoc.v:146873.1-146884.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_0.p" +attribute \generator "nMigen" +module \p$76 + attribute \src "libresoc.v:146882.17-146882.111" + wire $and$libresoc.v:146882$7974_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire input 1 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" + wire \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + cell $and $and$libresoc.v:146882$7974 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i + connect \B \p_ready_o + connect \Y $and$libresoc.v:146882$7974_Y + end + connect \$1 $and$libresoc.v:146882$7974_Y + connect \trigger \$1 +end +attribute \src "libresoc.v:146888.1-146899.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_end.p" +attribute \generator "nMigen" +module \p$78 + attribute \src "libresoc.v:146897.17-146897.111" + wire $and$libresoc.v:146897$7975_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire input 1 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" + wire \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + cell $and $and$libresoc.v:146897$7975 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i + connect \B \p_ready_o + connect \Y $and$libresoc.v:146897$7975_Y + end + connect \$1 $and$libresoc.v:146897$7975_Y + connect \trigger \$1 +end +attribute \src "libresoc.v:146903.1-146914.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.p" +attribute \generator "nMigen" +module \p$88 + attribute \src "libresoc.v:146912.17-146912.111" + wire $and$libresoc.v:146912$7976_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire input 1 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" + wire \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + cell $and $and$libresoc.v:146912$7976 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i + connect \B \p_ready_o + connect \Y $and$libresoc.v:146912$7976_Y + end + connect \$1 $and$libresoc.v:146912$7976_Y + connect \trigger \$1 +end +attribute \src "libresoc.v:146918.1-146929.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe1.p" +attribute \generator "nMigen" +module \p$90 + attribute \src "libresoc.v:146927.17-146927.111" + wire $and$libresoc.v:146927$7977_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire input 1 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" + wire \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + cell $and $and$libresoc.v:146927$7977 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i + connect \B \p_ready_o + connect \Y $and$libresoc.v:146927$7977_Y + end + connect \$1 $and$libresoc.v:146927$7977_Y + connect \trigger \$1 +end +attribute \src "libresoc.v:146933.1-146944.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe2.p" +attribute \generator "nMigen" +module \p$93 + attribute \src "libresoc.v:146942.17-146942.111" + wire $and$libresoc.v:146942$7978_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire input 1 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" + wire \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + cell $and $and$libresoc.v:146942$7978 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i + connect \B \p_ready_o + connect \Y $and$libresoc.v:146942$7978_Y + end + connect \$1 $and$libresoc.v:146942$7978_Y + connect \trigger \$1 +end +attribute \src "libresoc.v:146948.1-146959.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe3.p" +attribute \generator "nMigen" +module \p$95 + attribute \src "libresoc.v:146957.17-146957.111" + wire $and$libresoc.v:146957$7979_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire input 1 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" + wire \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + cell $and $and$libresoc.v:146957$7979 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i + connect \B \p_ready_o + connect \Y $and$libresoc.v:146957$7979_Y + end + connect \$1 $and$libresoc.v:146957$7979_Y + connect \trigger \$1 +end +attribute \src "libresoc.v:146963.1-146986.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.l0.l0.pick" +attribute \generator "nMigen" +module \pick + attribute \src "libresoc.v:146964.7-146964.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:146975.3-146984.6" + wire $0\o[0:0] + attribute \src "libresoc.v:146975.3-146984.6" + wire $1\o[0:0] + attribute \src "libresoc.v:146974.17-146974.95" + wire $eq$libresoc.v:146974$7980_Y + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire input 3 \i + attribute \src "libresoc.v:146964.7-146964.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire output 2 \n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + cell $eq $eq$libresoc.v:146974$7980 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \i + connect \B 1'0 + connect \Y $eq$libresoc.v:146974$7980_Y + end + attribute \src "libresoc.v:146964.7-146964.20" + process $proc$libresoc.v:146964$7982 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:146975.3-146984.6" + process $proc$libresoc.v:146975$7981 + assign { } { } + assign { } { } + assign $0\o[0:0] $1\o[0:0] + attribute \src "libresoc.v:146976.5-146976.29" + switch \initial + attribute \src "libresoc.v:146976.9-146976.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch \i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\o[0:0] 1'0 + case + assign $1\o[0:0] 1'0 + end + sync always + update \o $0\o[0:0] + end + connect \$1 $eq$libresoc.v:146974$7980_Y + connect \n \$1 +end +attribute \src "libresoc.v:146990.1-147804.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.l0.pimem" +attribute \generator "nMigen" +module \pimem + attribute \src "libresoc.v:147767.3-147782.6" + wire $0\adrok_l_r_addr_acked[0:0] + attribute \src "libresoc.v:147731.3-147766.6" + wire $0\adrok_l_s_addr_acked$next[0:0]$8072 + attribute \src "libresoc.v:147289.3-147290.57" + wire $0\adrok_l_s_addr_acked[0:0] + attribute \src "libresoc.v:147381.3-147389.6" + wire $0\busy_delay$next[0:0]$8040 + attribute \src "libresoc.v:147287.3-147288.37" + wire $0\busy_delay[0:0] + attribute \src "libresoc.v:147715.3-147730.6" + wire $0\busy_l_r_busy[0:0] + attribute \src "libresoc.v:147705.3-147714.6" + wire $0\busy_l_s_busy[0:0] + attribute \src "libresoc.v:147695.3-147704.6" + wire $0\cyc_l_r_cyc[0:0] + attribute \src "libresoc.v:147676.3-147685.6" + wire $0\cyc_l_s_cyc[0:0] + attribute \src "libresoc.v:147637.3-147675.6" + wire width 2 $0\fsm_state$next[1:0]$8058 + attribute \src "libresoc.v:147279.3-147280.35" + wire width 2 $0\fsm_state[1:0] + attribute \src "libresoc.v:146991.7-146991.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:147577.3-147586.6" + wire $0\ld_active_r_ld_active[0:0] + attribute \src "libresoc.v:147285.3-147286.35" + wire $0\lds_dly[0:0] + attribute \src "libresoc.v:147510.3-147540.6" + wire $0\ldst_port0_addr_ok_o[0:0] + attribute \src "libresoc.v:147567.3-147576.6" + wire width 64 $0\ldst_port0_ld_data_o[63:0] + attribute \src "libresoc.v:147587.3-147596.6" + wire $0\ldst_port0_ld_data_o_ok[0:0] + attribute \src "libresoc.v:147416.3-147431.6" + wire width 4 $0\lenexp_addr_i[3:0] + attribute \src "libresoc.v:147400.3-147415.6" + wire width 4 $0\lenexp_len_i[3:0] + attribute \src "libresoc.v:147686.3-147694.6" + wire $0\lsui_active_dly$next[0:0]$8066 + attribute \src "libresoc.v:147277.3-147278.47" + wire $0\lsui_active_dly[0:0] + attribute \src "libresoc.v:147617.3-147636.6" + wire $0\lsui_busy[0:0] + attribute \src "libresoc.v:147281.3-147282.36" + wire $0\reset_delay[0:0] + attribute \src "libresoc.v:147557.3-147566.6" + wire $0\reset_l_r_reset[0:0] + attribute \src "libresoc.v:147541.3-147556.6" + wire $0\reset_l_s_reset[0:0] + attribute \src "libresoc.v:147390.3-147399.6" + wire $0\st_active_r_st_active[0:0] + attribute \src "libresoc.v:147371.3-147380.6" + wire $0\st_done_r_st_done[0:0] + attribute \src "libresoc.v:147356.3-147370.6" + wire $0\st_done_s_st_done$next[0:0]$8035 + attribute \src "libresoc.v:147291.3-147292.51" + wire $0\st_done_s_st_done[0:0] + attribute \src "libresoc.v:147597.3-147606.6" + wire width 64 $0\stdata[63:0] + attribute \src "libresoc.v:147283.3-147284.35" + wire $0\sts_dly[0:0] + attribute \src "libresoc.v:147432.3-147457.6" + wire $0\valid_l_s_valid[0:0] + attribute \src "libresoc.v:147484.3-147509.6" + wire width 48 $0\x_addr_i[47:0] + attribute \src "libresoc.v:147458.3-147483.6" + wire width 8 $0\x_mask_i[7:0] + attribute \src "libresoc.v:147607.3-147616.6" + wire width 64 $0\x_st_data_i[63:0] + attribute \src "libresoc.v:147767.3-147782.6" + wire $1\adrok_l_r_addr_acked[0:0] + attribute \src "libresoc.v:147731.3-147766.6" + wire $1\adrok_l_s_addr_acked$next[0:0]$8073 + attribute \src "libresoc.v:147085.7-147085.34" + wire $1\adrok_l_s_addr_acked[0:0] + attribute \src "libresoc.v:147381.3-147389.6" + wire $1\busy_delay$next[0:0]$8041 + attribute \src "libresoc.v:147089.7-147089.24" + wire $1\busy_delay[0:0] + attribute \src "libresoc.v:147715.3-147730.6" + wire $1\busy_l_r_busy[0:0] + attribute \src "libresoc.v:147705.3-147714.6" + wire $1\busy_l_s_busy[0:0] + attribute \src "libresoc.v:147695.3-147704.6" + wire $1\cyc_l_r_cyc[0:0] + attribute \src "libresoc.v:147676.3-147685.6" + wire $1\cyc_l_s_cyc[0:0] + attribute \src "libresoc.v:147637.3-147675.6" + wire width 2 $1\fsm_state$next[1:0]$8059 + attribute \src "libresoc.v:147111.13-147111.29" + wire width 2 $1\fsm_state[1:0] + attribute \src "libresoc.v:147577.3-147586.6" + wire $1\ld_active_r_ld_active[0:0] + attribute \src "libresoc.v:147125.7-147125.21" + wire $1\lds_dly[0:0] + attribute \src "libresoc.v:147510.3-147540.6" + wire $1\ldst_port0_addr_ok_o[0:0] + attribute \src "libresoc.v:147567.3-147576.6" + wire width 64 $1\ldst_port0_ld_data_o[63:0] + attribute \src "libresoc.v:147587.3-147596.6" + wire $1\ldst_port0_ld_data_o_ok[0:0] + attribute \src "libresoc.v:147416.3-147431.6" + wire width 4 $1\lenexp_addr_i[3:0] + attribute \src "libresoc.v:147400.3-147415.6" + wire width 4 $1\lenexp_len_i[3:0] + attribute \src "libresoc.v:147686.3-147694.6" + wire $1\lsui_active_dly$next[0:0]$8067 + attribute \src "libresoc.v:147168.7-147168.29" + wire $1\lsui_active_dly[0:0] + attribute \src "libresoc.v:147617.3-147636.6" + wire $1\lsui_busy[0:0] + attribute \src "libresoc.v:147180.7-147180.25" + wire $1\reset_delay[0:0] + attribute \src "libresoc.v:147557.3-147566.6" + wire $1\reset_l_r_reset[0:0] + attribute \src "libresoc.v:147541.3-147556.6" + wire $1\reset_l_s_reset[0:0] + attribute \src "libresoc.v:147390.3-147399.6" + wire $1\st_active_r_st_active[0:0] + attribute \src "libresoc.v:147371.3-147380.6" + wire $1\st_done_r_st_done[0:0] + attribute \src "libresoc.v:147356.3-147370.6" + wire $1\st_done_s_st_done$next[0:0]$8036 + attribute \src "libresoc.v:147200.7-147200.31" + wire $1\st_done_s_st_done[0:0] + attribute \src "libresoc.v:147597.3-147606.6" + wire width 64 $1\stdata[63:0] + attribute \src "libresoc.v:147208.7-147208.21" + wire $1\sts_dly[0:0] + attribute \src "libresoc.v:147432.3-147457.6" + wire $1\valid_l_s_valid[0:0] + attribute \src "libresoc.v:147484.3-147509.6" + wire width 48 $1\x_addr_i[47:0] + attribute \src "libresoc.v:147458.3-147483.6" + wire width 8 $1\x_mask_i[7:0] + attribute \src "libresoc.v:147607.3-147616.6" + wire width 64 $1\x_st_data_i[63:0] + attribute \src "libresoc.v:147767.3-147782.6" + wire $2\adrok_l_r_addr_acked[0:0] + attribute \src "libresoc.v:147731.3-147766.6" + wire $2\adrok_l_s_addr_acked$next[0:0]$8074 + attribute \src "libresoc.v:147715.3-147730.6" + wire $2\busy_l_r_busy[0:0] + attribute \src "libresoc.v:147637.3-147675.6" + wire width 2 $2\fsm_state$next[1:0]$8060 + attribute \src "libresoc.v:147510.3-147540.6" + wire $2\ldst_port0_addr_ok_o[0:0] + attribute \src "libresoc.v:147416.3-147431.6" + wire width 4 $2\lenexp_addr_i[3:0] + attribute \src "libresoc.v:147400.3-147415.6" + wire width 4 $2\lenexp_len_i[3:0] + attribute \src "libresoc.v:147617.3-147636.6" + wire $2\lsui_busy[0:0] + attribute \src "libresoc.v:147541.3-147556.6" + wire $2\reset_l_s_reset[0:0] + attribute \src "libresoc.v:147356.3-147370.6" + wire $2\st_done_s_st_done$next[0:0]$8037 + attribute \src "libresoc.v:147432.3-147457.6" + wire $2\valid_l_s_valid[0:0] + attribute \src "libresoc.v:147484.3-147509.6" + wire width 48 $2\x_addr_i[47:0] + attribute \src "libresoc.v:147458.3-147483.6" + wire width 8 $2\x_mask_i[7:0] + attribute \src "libresoc.v:147731.3-147766.6" + wire $3\adrok_l_s_addr_acked$next[0:0]$8075 + attribute \src "libresoc.v:147637.3-147675.6" + wire width 2 $3\fsm_state$next[1:0]$8061 + attribute \src "libresoc.v:147510.3-147540.6" + wire $3\ldst_port0_addr_ok_o[0:0] + attribute \src "libresoc.v:147432.3-147457.6" + wire $3\valid_l_s_valid[0:0] + attribute \src "libresoc.v:147484.3-147509.6" + wire width 48 $3\x_addr_i[47:0] + attribute \src "libresoc.v:147458.3-147483.6" + wire width 8 $3\x_mask_i[7:0] + attribute \src "libresoc.v:147731.3-147766.6" + wire $4\adrok_l_s_addr_acked$next[0:0]$8076 + attribute \src "libresoc.v:147637.3-147675.6" + wire width 2 $4\fsm_state$next[1:0]$8062 + attribute \src "libresoc.v:147510.3-147540.6" + wire $4\ldst_port0_addr_ok_o[0:0] + attribute \src "libresoc.v:147432.3-147457.6" + wire $4\valid_l_s_valid[0:0] + attribute \src "libresoc.v:147484.3-147509.6" + wire width 48 $4\x_addr_i[47:0] + attribute \src "libresoc.v:147458.3-147483.6" + wire width 8 $4\x_mask_i[7:0] + attribute \src "libresoc.v:147731.3-147766.6" + wire $5\adrok_l_s_addr_acked$next[0:0]$8077 + attribute \src "libresoc.v:147637.3-147675.6" + wire width 2 $5\fsm_state$next[1:0]$8063 + attribute \src "libresoc.v:147510.3-147540.6" + wire $5\ldst_port0_addr_ok_o[0:0] + attribute \src "libresoc.v:147731.3-147766.6" + wire $6\adrok_l_s_addr_acked$next[0:0]$8078 + attribute \src "libresoc.v:147237.18-147237.115" + wire $and$libresoc.v:147237$7984_Y + attribute \src "libresoc.v:147239.18-147239.95" + wire $and$libresoc.v:147239$7986_Y + attribute \src "libresoc.v:147241.17-147241.138" + wire $and$libresoc.v:147241$7988_Y + attribute \src "libresoc.v:147242.18-147242.95" + wire $and$libresoc.v:147242$7989_Y + attribute \src "libresoc.v:147245.18-147245.136" + wire $and$libresoc.v:147245$7994_Y + attribute \src "libresoc.v:147246.18-147246.136" + wire $and$libresoc.v:147246$7995_Y + attribute \src "libresoc.v:147247.18-147247.136" + wire $and$libresoc.v:147247$7996_Y + attribute \src "libresoc.v:147248.18-147248.136" + wire $and$libresoc.v:147248$7997_Y + attribute \src "libresoc.v:147249.18-147249.136" + wire $and$libresoc.v:147249$7998_Y + attribute \src "libresoc.v:147254.18-147254.119" + wire width 176 $and$libresoc.v:147254$8003_Y + attribute \src "libresoc.v:147257.18-147257.136" + wire $and$libresoc.v:147257$8006_Y + attribute \src "libresoc.v:147258.18-147258.136" + wire $and$libresoc.v:147258$8007_Y + attribute \src "libresoc.v:147260.18-147260.139" + wire $and$libresoc.v:147260$8009_Y + attribute \src "libresoc.v:147264.18-147264.139" + wire $and$libresoc.v:147264$8013_Y + attribute \src "libresoc.v:147266.18-147266.114" + wire $and$libresoc.v:147266$8015_Y + attribute \src "libresoc.v:147268.18-147268.114" + wire $and$libresoc.v:147268$8017_Y + attribute \src "libresoc.v:147272.18-147272.103" + wire $and$libresoc.v:147272$8021_Y + attribute \src "libresoc.v:147273.17-147273.135" + wire $and$libresoc.v:147273$8022_Y + attribute \src "libresoc.v:147276.18-147276.103" + wire $and$libresoc.v:147276$8025_Y + attribute \src "libresoc.v:147243.18-147243.109" + wire width 4 $extend$libresoc.v:147243$7990_Y + attribute \src "libresoc.v:147244.18-147244.109" + wire width 4 $extend$libresoc.v:147244$7992_Y + attribute \src "libresoc.v:147255.18-147255.112" + wire width 8 $mul$libresoc.v:147255$8004_Y + attribute \src "libresoc.v:147261.18-147261.112" + wire width 8 $mul$libresoc.v:147261$8010_Y + attribute \src "libresoc.v:147236.17-147236.103" + wire $not$libresoc.v:147236$7983_Y + attribute \src "libresoc.v:147238.18-147238.94" + wire $not$libresoc.v:147238$7985_Y + attribute \src "libresoc.v:147240.18-147240.94" + wire $not$libresoc.v:147240$7987_Y + attribute \src "libresoc.v:147250.18-147250.102" + wire $not$libresoc.v:147250$7999_Y + attribute \src "libresoc.v:147253.18-147253.97" + wire $not$libresoc.v:147253$8002_Y + attribute \src "libresoc.v:147259.18-147259.102" + wire $not$libresoc.v:147259$8008_Y + attribute \src "libresoc.v:147262.17-147262.103" + wire $not$libresoc.v:147262$8011_Y + attribute \src "libresoc.v:147269.18-147269.101" + wire $not$libresoc.v:147269$8018_Y + attribute \src "libresoc.v:147270.18-147270.111" + wire $not$libresoc.v:147270$8019_Y + attribute \src "libresoc.v:147271.18-147271.110" + wire $not$libresoc.v:147271$8020_Y + attribute \src "libresoc.v:147274.18-147274.102" + wire $not$libresoc.v:147274$8023_Y + attribute \src "libresoc.v:147275.18-147275.102" + wire $not$libresoc.v:147275$8024_Y + attribute \src "libresoc.v:147251.18-147251.111" + wire $or$libresoc.v:147251$8000_Y + attribute \src "libresoc.v:147252.17-147252.130" + wire $or$libresoc.v:147252$8001_Y + attribute \src "libresoc.v:147265.18-147265.130" + wire $or$libresoc.v:147265$8014_Y + attribute \src "libresoc.v:147267.18-147267.130" + wire $or$libresoc.v:147267$8016_Y + attribute \src "libresoc.v:147243.18-147243.109" + wire width 4 $pos$libresoc.v:147243$7991_Y + attribute \src "libresoc.v:147244.18-147244.109" + wire width 4 $pos$libresoc.v:147244$7993_Y + attribute \src "libresoc.v:147263.18-147263.121" + wire width 319 $sshl$libresoc.v:147263$8012_Y + attribute \src "libresoc.v:147256.18-147256.106" + wire width 176 $sshr$libresoc.v:147256$8005_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:256" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:205" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire \$17 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" + wire width 4 \$21 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" + wire width 4 \$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:222" + wire \$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:222" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:222" + wire \$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:212" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:222" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:248" + wire \$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:64" + wire \$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:61" + wire \$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:61" + wire \$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:247" + wire width 176 \$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:246" + wire width 176 \$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:247" + wire width 8 \$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:247" + wire width 176 \$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:248" + wire \$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:213" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:248" + wire \$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:64" + wire \$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:256" + wire \$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:260" + wire width 319 \$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:260" + wire width 8 \$57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:260" + wire width 319 \$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:256" + wire \$61 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" + wire \$63 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" + wire \$65 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" + wire \$67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" + wire \$69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:222" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:95" + wire \$71 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:99" + wire \$73 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:99" + wire \$75 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:99" + wire \$77 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:108" + wire \$79 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire \$81 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire \$83 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:205" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire \adrok_l_q_addr_acked + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \adrok_l_qn_addr_acked + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \adrok_l_r_addr_acked + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \adrok_l_s_addr_acked + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \adrok_l_s_addr_acked$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:202" + wire \busy_delay + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:202" + wire \busy_delay$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:203" + wire \busy_edge + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire \busy_l_q_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \busy_l_r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \busy_l_s_busy + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 23 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire \cyc_l_q_cyc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \cyc_l_r_cyc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \cyc_l_s_cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:85" + wire width 2 \fsm_state + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:85" + wire width 2 \fsm_state$next + attribute \src "libresoc.v:146991.7-146991.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire \ld_active_q_ld_active + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \ld_active_r_ld_active + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \ld_active_s_ld_active + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:244" + wire width 64 \lddata + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:195" + wire \lds + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire \lds_dly + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire \lds_dly$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + wire \lds_rise + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:110" + wire input 18 \ldst_port0_addr_exc_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 48 input 6 \ldst_port0_addr_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire input 7 \ldst_port0_addr_i_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:109" + wire output 10 \ldst_port0_addr_ok_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:105" + wire output 4 \ldst_port0_busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102" + wire width 4 input 5 \ldst_port0_data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:98" + wire input 2 \ldst_port0_is_ld_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" + wire input 3 \ldst_port0_is_st_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 12 \ldst_port0_ld_data_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 13 \ldst_port0_ld_data_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 input 15 \ldst_port0_st_data_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire input 14 \ldst_port0_st_data_i_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:131" + wire width 4 \lenexp_addr_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:130" + wire width 4 \lenexp_len_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:132" + wire width 64 \lenexp_lexp_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:134" + wire width 176 \lenexp_rexp_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:107" + wire \lsui_active + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire \lsui_active_dly + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire \lsui_active_dly$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + wire \lsui_active_rise + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:46" + wire \lsui_busy + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:62" + wire width 64 input 11 \m_ld_data_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:54" + wire output 21 \m_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:269" + wire \reset_delay + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:269" + wire \reset_delay$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire \reset_l_q_reset + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \reset_l_r_reset + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \reset_l_s_reset + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire \st_active_q_st_active + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \st_active_r_st_active + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \st_active_s_st_active + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire \st_done_q_st_done + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \st_done_r_st_done + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \st_done_s_st_done + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \st_done_s_st_done$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:259" + wire width 64 \stdata + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:196" + wire \sts + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire \sts_dly + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire \sts_dly$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + wire \sts_rise + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire \valid_l_q_valid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \valid_l_r_valid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \valid_l_s_valid + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:43" + wire width 48 output 9 \x_addr_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:59" + wire input 17 \x_busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:45" + wire output 19 \x_ld_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:44" + wire width 8 output 8 \x_mask_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:47" + wire width 64 output 16 \x_st_data_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:46" + wire output 20 \x_st_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:50" + wire output 22 \x_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:205" + cell $and $and$libresoc.v:147237$7984 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ldst_port0_busy_o + connect \B \$9 + connect \Y $and$libresoc.v:147237$7984_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $and$libresoc.v:147239$7986 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \lds + connect \B \$13 + connect \Y $and$libresoc.v:147239$7986_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:256" + cell $and $and$libresoc.v:147241$7988 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \st_active_q_st_active + connect \B \ldst_port0_st_data_i_ok + connect \Y $and$libresoc.v:147241$7988_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $and$libresoc.v:147242$7989 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \sts + connect \B \$17 + connect \Y $and$libresoc.v:147242$7989_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:222" + cell $and $and$libresoc.v:147245$7994 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ldst_port0_addr_i_ok + connect \B \adrok_l_qn_addr_acked + connect \Y $and$libresoc.v:147245$7994_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:222" + cell $and $and$libresoc.v:147246$7995 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ldst_port0_addr_i_ok + connect \B \adrok_l_qn_addr_acked + connect \Y $and$libresoc.v:147246$7995_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:222" + cell $and $and$libresoc.v:147247$7996 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ldst_port0_addr_i_ok + connect \B \adrok_l_qn_addr_acked + connect \Y $and$libresoc.v:147247$7996_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:222" + cell $and $and$libresoc.v:147248$7997 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ldst_port0_addr_i_ok + connect \B \adrok_l_qn_addr_acked + connect \Y $and$libresoc.v:147248$7997_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:248" + cell $and $and$libresoc.v:147249$7998 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ld_active_q_ld_active + connect \B \adrok_l_q_addr_acked + connect \Y $and$libresoc.v:147249$7998_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:246" + cell $and $and$libresoc.v:147254$8003 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 176 + parameter \Y_WIDTH 176 + connect \A \m_ld_data_o + connect \B \lenexp_rexp_o + connect \Y $and$libresoc.v:147254$8003_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:248" + cell $and $and$libresoc.v:147257$8006 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ld_active_q_ld_active + connect \B \adrok_l_q_addr_acked + connect \Y $and$libresoc.v:147257$8006_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:248" + cell $and $and$libresoc.v:147258$8007 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ld_active_q_ld_active + connect \B \adrok_l_q_addr_acked + connect \Y $and$libresoc.v:147258$8007_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:256" + cell $and $and$libresoc.v:147260$8009 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \st_active_q_st_active + connect \B \ldst_port0_st_data_i_ok + connect \Y $and$libresoc.v:147260$8009_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:256" + cell $and $and$libresoc.v:147264$8013 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \st_active_q_st_active + connect \B \ldst_port0_st_data_i_ok + connect \Y $and$libresoc.v:147264$8013_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" + cell $and $and$libresoc.v:147266$8015 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$63 + connect \B \valid_l_q_valid + connect \Y $and$libresoc.v:147266$8015_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" + cell $and $and$libresoc.v:147268$8017 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$67 + connect \B \valid_l_q_valid + connect \Y $and$libresoc.v:147268$8017_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:99" + cell $and $and$libresoc.v:147272$8021 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$73 + connect \B \$75 + connect \Y $and$libresoc.v:147272$8021_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:222" + cell $and $and$libresoc.v:147273$8022 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ldst_port0_addr_i_ok + connect \B \adrok_l_qn_addr_acked + connect \Y $and$libresoc.v:147273$8022_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $and$libresoc.v:147276$8025 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \lsui_active + connect \B \$81 + connect \Y $and$libresoc.v:147276$8025_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" + cell $pos $extend$libresoc.v:147243$7990 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 4 + connect \A \ldst_port0_addr_i [2:0] + connect \Y $extend$libresoc.v:147243$7990_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" + cell $pos $extend$libresoc.v:147244$7992 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 4 + connect \A \ldst_port0_addr_i [2:0] + connect \Y $extend$libresoc.v:147244$7992_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:247" + cell $mul $mul$libresoc.v:147255$8004 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 8 + connect \A \lenexp_addr_i + connect \B 4'1000 + connect \Y $mul$libresoc.v:147255$8004_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:260" + cell $mul $mul$libresoc.v:147261$8010 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 8 + connect \A \lenexp_addr_i + connect \B 4'1000 + connect \Y $mul$libresoc.v:147261$8010_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:205" + cell $not $not$libresoc.v:147236$7983 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \busy_delay + connect \Y $not$libresoc.v:147236$7983_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $not$libresoc.v:147238$7985 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \lds_dly + connect \Y $not$libresoc.v:147238$7985_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $not$libresoc.v:147240$7987 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \sts_dly + connect \Y $not$libresoc.v:147240$7987_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:64" + cell $not $not$libresoc.v:147250$7999 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \lsui_busy + connect \Y $not$libresoc.v:147250$7999_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:61" + cell $not $not$libresoc.v:147253$8002 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$38 + connect \Y $not$libresoc.v:147253$8002_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:64" + cell $not $not$libresoc.v:147259$8008 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \lsui_busy + connect \Y $not$libresoc.v:147259$8008_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:213" + cell $not $not$libresoc.v:147262$8011 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \busy_delay + connect \Y $not$libresoc.v:147262$8011_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:95" + cell $not $not$libresoc.v:147269$8018 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \x_busy_o + connect \Y $not$libresoc.v:147269$8018_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:99" + cell $not $not$libresoc.v:147270$8019 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ldst_port0_is_st_i + connect \Y $not$libresoc.v:147270$8019_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:99" + cell $not $not$libresoc.v:147271$8020 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ldst_port0_busy_o + connect \Y $not$libresoc.v:147271$8020_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:108" + cell $not $not$libresoc.v:147274$8023 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \x_busy_o + connect \Y $not$libresoc.v:147274$8023_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $not$libresoc.v:147275$8024 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \lsui_active_dly + connect \Y $not$libresoc.v:147275$8024_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:61" + cell $or $or$libresoc.v:147251$8000 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \x_busy_o + connect \B \lsui_busy + connect \Y $or$libresoc.v:147251$8000_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:212" + cell $or $or$libresoc.v:147252$8001 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ldst_port0_is_ld_i + connect \B \ldst_port0_is_st_i + connect \Y $or$libresoc.v:147252$8001_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" + cell $or $or$libresoc.v:147265$8014 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ldst_port0_is_ld_i + connect \B \ldst_port0_is_st_i + connect \Y $or$libresoc.v:147265$8014_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" + cell $or $or$libresoc.v:147267$8016 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ldst_port0_is_ld_i + connect \B \ldst_port0_is_st_i + connect \Y $or$libresoc.v:147267$8016_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" + cell $pos $pos$libresoc.v:147243$7991 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A $extend$libresoc.v:147243$7990_Y + connect \Y $pos$libresoc.v:147243$7991_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" + cell $pos $pos$libresoc.v:147244$7993 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A $extend$libresoc.v:147244$7992_Y + connect \Y $pos$libresoc.v:147244$7993_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:260" + cell $sshl $sshl$libresoc.v:147263$8012 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 319 + connect \A \ldst_port0_st_data_i + connect \B \$57 + connect \Y $sshl$libresoc.v:147263$8012_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:247" + cell $sshr $sshr$libresoc.v:147256$8005 + parameter \A_SIGNED 0 + parameter \A_WIDTH 176 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 176 + connect \A \$42 + connect \B \$44 + connect \Y $sshr$libresoc.v:147256$8005_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:147293.11-147300.4" + cell \adrok_l \adrok_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_addr_acked \adrok_l_q_addr_acked + connect \qn_addr_acked \adrok_l_qn_addr_acked + connect \r_addr_acked \adrok_l_r_addr_acked + connect \s_addr_acked \adrok_l_s_addr_acked + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:147301.10-147307.4" + cell \busy_l \busy_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_busy \busy_l_q_busy + connect \r_busy \busy_l_r_busy + connect \s_busy \busy_l_s_busy + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:147308.9-147314.4" + cell \cyc_l \cyc_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_cyc \cyc_l_q_cyc + connect \r_cyc \cyc_l_r_cyc + connect \s_cyc \cyc_l_s_cyc + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:147315.13-147321.4" + cell \ld_active \ld_active + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_ld_active \ld_active_q_ld_active + connect \r_ld_active \ld_active_r_ld_active + connect \s_ld_active \ld_active_s_ld_active + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:147322.10-147327.4" + cell \lenexp \lenexp + connect \addr_i \lenexp_addr_i + connect \len_i \lenexp_len_i + connect \lexp_o \lenexp_lexp_o + connect \rexp_o \lenexp_rexp_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:147328.11-147334.4" + cell \reset_l \reset_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_reset \reset_l_q_reset + connect \r_reset \reset_l_r_reset + connect \s_reset \reset_l_s_reset + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:147335.13-147341.4" + cell \st_active \st_active + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_st_active \st_active_q_st_active + connect \r_st_active \st_active_r_st_active + connect \s_st_active \st_active_s_st_active + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:147342.11-147348.4" + cell \st_done \st_done + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_st_done \st_done_q_st_done + connect \r_st_done \st_done_r_st_done + connect \s_st_done \st_done_s_st_done + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:147349.11-147355.4" + cell \valid_l \valid_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_valid \valid_l_q_valid + connect \r_valid \valid_l_r_valid + connect \s_valid \valid_l_s_valid + end + attribute \src "libresoc.v:146991.7-146991.20" + process $proc$libresoc.v:146991$8080 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:147085.7-147085.34" + process $proc$libresoc.v:147085$8081 + assign { } { } + assign $1\adrok_l_s_addr_acked[0:0] 1'0 + sync always + sync init + update \adrok_l_s_addr_acked $1\adrok_l_s_addr_acked[0:0] + end + attribute \src "libresoc.v:147089.7-147089.24" + process $proc$libresoc.v:147089$8082 + assign { } { } + assign $1\busy_delay[0:0] 1'0 + sync always + sync init + update \busy_delay $1\busy_delay[0:0] + end + attribute \src "libresoc.v:147111.13-147111.29" + process $proc$libresoc.v:147111$8083 + assign { } { } + assign $1\fsm_state[1:0] 2'00 + sync always + sync init + update \fsm_state $1\fsm_state[1:0] + end + attribute \src "libresoc.v:147125.7-147125.21" + process $proc$libresoc.v:147125$8084 + assign { } { } + assign $1\lds_dly[0:0] 1'0 + sync always + sync init + update \lds_dly $1\lds_dly[0:0] + end + attribute \src "libresoc.v:147168.7-147168.29" + process $proc$libresoc.v:147168$8085 + assign { } { } + assign $1\lsui_active_dly[0:0] 1'0 + sync always + sync init + update \lsui_active_dly $1\lsui_active_dly[0:0] + end + attribute \src "libresoc.v:147180.7-147180.25" + process $proc$libresoc.v:147180$8086 + assign { } { } + assign $1\reset_delay[0:0] 1'0 + sync always + sync init + update \reset_delay $1\reset_delay[0:0] + end + attribute \src "libresoc.v:147200.7-147200.31" + process $proc$libresoc.v:147200$8087 + assign { } { } + assign $1\st_done_s_st_done[0:0] 1'0 + sync always + sync init + update \st_done_s_st_done $1\st_done_s_st_done[0:0] + end + attribute \src "libresoc.v:147208.7-147208.21" + process $proc$libresoc.v:147208$8088 + assign { } { } + assign $1\sts_dly[0:0] 1'0 + sync always + sync init + update \sts_dly $1\sts_dly[0:0] + end + attribute \src "libresoc.v:147277.3-147278.47" + process $proc$libresoc.v:147277$8026 + assign { } { } + assign $0\lsui_active_dly[0:0] \lsui_active_dly$next + sync posedge \coresync_clk + update \lsui_active_dly $0\lsui_active_dly[0:0] + end + attribute \src "libresoc.v:147279.3-147280.35" + process $proc$libresoc.v:147279$8027 + assign { } { } + assign $0\fsm_state[1:0] \fsm_state$next + sync posedge \coresync_clk + update \fsm_state $0\fsm_state[1:0] + end + attribute \src "libresoc.v:147281.3-147282.36" + process $proc$libresoc.v:147281$8028 + assign { } { } + assign $0\reset_delay[0:0] \reset_l_q_reset + sync posedge \coresync_clk + update \reset_delay $0\reset_delay[0:0] + end + attribute \src "libresoc.v:147283.3-147284.35" + process $proc$libresoc.v:147283$8029 + assign { } { } + assign $0\sts_dly[0:0] \ldst_port0_is_st_i + sync posedge \coresync_clk + update \sts_dly $0\sts_dly[0:0] + end + attribute \src "libresoc.v:147285.3-147286.35" + process $proc$libresoc.v:147285$8030 + assign { } { } + assign $0\lds_dly[0:0] \ldst_port0_is_ld_i + sync posedge \coresync_clk + update \lds_dly $0\lds_dly[0:0] + end + attribute \src "libresoc.v:147287.3-147288.37" + process $proc$libresoc.v:147287$8031 + assign { } { } + assign $0\busy_delay[0:0] \busy_delay$next + sync posedge \coresync_clk + update \busy_delay $0\busy_delay[0:0] + end + attribute \src "libresoc.v:147289.3-147290.57" + process $proc$libresoc.v:147289$8032 + assign { } { } + assign $0\adrok_l_s_addr_acked[0:0] \adrok_l_s_addr_acked$next + sync posedge \coresync_clk + update \adrok_l_s_addr_acked $0\adrok_l_s_addr_acked[0:0] + end + attribute \src "libresoc.v:147291.3-147292.51" + process $proc$libresoc.v:147291$8033 + assign { } { } + assign $0\st_done_s_st_done[0:0] \st_done_s_st_done$next + sync posedge \coresync_clk + update \st_done_s_st_done $0\st_done_s_st_done[0:0] + end + attribute \src "libresoc.v:147356.3-147370.6" + process $proc$libresoc.v:147356$8034 + assign { } { } + assign { } { } + assign { } { } + assign $0\st_done_s_st_done$next[0:0]$8035 $2\st_done_s_st_done$next[0:0]$8037 + attribute \src "libresoc.v:147357.5-147357.29" + switch \initial + attribute \src "libresoc.v:147357.9-147357.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:256" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\st_done_s_st_done$next[0:0]$8036 1'1 + case + assign $1\st_done_s_st_done$next[0:0]$8036 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\st_done_s_st_done$next[0:0]$8037 1'0 + case + assign $2\st_done_s_st_done$next[0:0]$8037 $1\st_done_s_st_done$next[0:0]$8036 + end + sync always + update \st_done_s_st_done$next $0\st_done_s_st_done$next[0:0]$8035 + end + attribute \src "libresoc.v:147371.3-147380.6" + process $proc$libresoc.v:147371$8038 + assign { } { } + assign { } { } + assign $0\st_done_r_st_done[0:0] $1\st_done_r_st_done[0:0] + attribute \src "libresoc.v:147372.5-147372.29" + switch \initial + attribute \src "libresoc.v:147372.9-147372.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:275" + switch \reset_l_q_reset + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\st_done_r_st_done[0:0] 1'1 + case + assign $1\st_done_r_st_done[0:0] 1'0 + end + sync always + update \st_done_r_st_done $0\st_done_r_st_done[0:0] + end + attribute \src "libresoc.v:147381.3-147389.6" + process $proc$libresoc.v:147381$8039 + assign { } { } + assign { } { } + assign $0\busy_delay$next[0:0]$8040 $1\busy_delay$next[0:0]$8041 + attribute \src "libresoc.v:147382.5-147382.29" + switch \initial + attribute \src "libresoc.v:147382.9-147382.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\busy_delay$next[0:0]$8041 1'0 + case + assign $1\busy_delay$next[0:0]$8041 \ldst_port0_busy_o + end + sync always + update \busy_delay$next $0\busy_delay$next[0:0]$8040 + end + attribute \src "libresoc.v:147390.3-147399.6" + process $proc$libresoc.v:147390$8042 + assign { } { } + assign { } { } + assign $0\st_active_r_st_active[0:0] $1\st_active_r_st_active[0:0] + attribute \src "libresoc.v:147391.5-147391.29" + switch \initial + attribute \src "libresoc.v:147391.9-147391.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:275" + switch \reset_l_q_reset + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\st_active_r_st_active[0:0] 1'1 + case + assign $1\st_active_r_st_active[0:0] 1'0 + end + sync always + update \st_active_r_st_active $0\st_active_r_st_active[0:0] + end + attribute \src "libresoc.v:147400.3-147415.6" + process $proc$libresoc.v:147400$8043 + assign { } { } + assign { } { } + assign { } { } + assign $0\lenexp_len_i[3:0] $2\lenexp_len_i[3:0] + attribute \src "libresoc.v:147401.5-147401.29" + switch \initial + attribute \src "libresoc.v:147401.9-147401.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:217" + switch \ld_active_q_ld_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\lenexp_len_i[3:0] \ldst_port0_data_len + case + assign $1\lenexp_len_i[3:0] 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:229" + switch \st_active_q_st_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\lenexp_len_i[3:0] \ldst_port0_data_len + case + assign $2\lenexp_len_i[3:0] $1\lenexp_len_i[3:0] + end + sync always + update \lenexp_len_i $0\lenexp_len_i[3:0] + end + attribute \src "libresoc.v:147416.3-147431.6" + process $proc$libresoc.v:147416$8044 + assign { } { } + assign { } { } + assign { } { } + assign $0\lenexp_addr_i[3:0] $2\lenexp_addr_i[3:0] + attribute \src "libresoc.v:147417.5-147417.29" + switch \initial + attribute \src "libresoc.v:147417.9-147417.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:217" + switch \ld_active_q_ld_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\lenexp_addr_i[3:0] \$21 + case + assign $1\lenexp_addr_i[3:0] 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:229" + switch \st_active_q_st_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\lenexp_addr_i[3:0] \$23 + case + assign $2\lenexp_addr_i[3:0] $1\lenexp_addr_i[3:0] + end + sync always + update \lenexp_addr_i $0\lenexp_addr_i[3:0] + end + attribute \src "libresoc.v:147432.3-147457.6" + process $proc$libresoc.v:147432$8045 + assign { } { } + assign { } { } + assign { } { } + assign $0\valid_l_s_valid[0:0] $3\valid_l_s_valid[0:0] + attribute \src "libresoc.v:147433.5-147433.29" + switch \initial + attribute \src "libresoc.v:147433.9-147433.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:217" + switch \ld_active_q_ld_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\valid_l_s_valid[0:0] $2\valid_l_s_valid[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:222" + switch \$25 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\valid_l_s_valid[0:0] 1'1 + case + assign $2\valid_l_s_valid[0:0] 1'0 + end + case + assign $1\valid_l_s_valid[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:229" + switch \st_active_q_st_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\valid_l_s_valid[0:0] $4\valid_l_s_valid[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:234" + switch \ldst_port0_addr_i_ok + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\valid_l_s_valid[0:0] 1'1 + case + assign $4\valid_l_s_valid[0:0] $1\valid_l_s_valid[0:0] + end + case + assign $3\valid_l_s_valid[0:0] $1\valid_l_s_valid[0:0] + end + sync always + update \valid_l_s_valid $0\valid_l_s_valid[0:0] + end + attribute \src "libresoc.v:147458.3-147483.6" + process $proc$libresoc.v:147458$8046 + assign { } { } + assign { } { } + assign { } { } + assign $0\x_mask_i[7:0] $3\x_mask_i[7:0] + attribute \src "libresoc.v:147459.5-147459.29" + switch \initial + attribute \src "libresoc.v:147459.9-147459.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:217" + switch \ld_active_q_ld_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\x_mask_i[7:0] $2\x_mask_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:222" + switch \$27 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\x_mask_i[7:0] \lenexp_lexp_o [7:0] + case + assign $2\x_mask_i[7:0] 8'00000000 + end + case + assign $1\x_mask_i[7:0] 8'00000000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:229" + switch \st_active_q_st_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\x_mask_i[7:0] $4\x_mask_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:234" + switch \ldst_port0_addr_i_ok + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\x_mask_i[7:0] \lenexp_lexp_o [7:0] + case + assign $4\x_mask_i[7:0] $1\x_mask_i[7:0] + end + case + assign $3\x_mask_i[7:0] $1\x_mask_i[7:0] + end + sync always + update \x_mask_i $0\x_mask_i[7:0] + end + attribute \src "libresoc.v:147484.3-147509.6" + process $proc$libresoc.v:147484$8047 + assign { } { } + assign { } { } + assign { } { } + assign $0\x_addr_i[47:0] $3\x_addr_i[47:0] + attribute \src "libresoc.v:147485.5-147485.29" + switch \initial + attribute \src "libresoc.v:147485.9-147485.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:217" + switch \ld_active_q_ld_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\x_addr_i[47:0] $2\x_addr_i[47:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:222" + switch \$29 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\x_addr_i[47:0] \ldst_port0_addr_i + case + assign $2\x_addr_i[47:0] 48'000000000000000000000000000000000000000000000000 + end + case + assign $1\x_addr_i[47:0] 48'000000000000000000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:229" + switch \st_active_q_st_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\x_addr_i[47:0] $4\x_addr_i[47:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:234" + switch \ldst_port0_addr_i_ok + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\x_addr_i[47:0] \ldst_port0_addr_i + case + assign $4\x_addr_i[47:0] $1\x_addr_i[47:0] + end + case + assign $3\x_addr_i[47:0] $1\x_addr_i[47:0] + end + sync always + update \x_addr_i $0\x_addr_i[47:0] + end + attribute \src "libresoc.v:147510.3-147540.6" + process $proc$libresoc.v:147510$8048 + assign { } { } + assign { } { } + assign { } { } + assign $0\ldst_port0_addr_ok_o[0:0] $3\ldst_port0_addr_ok_o[0:0] + attribute \src "libresoc.v:147511.5-147511.29" + switch \initial + attribute \src "libresoc.v:147511.9-147511.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:217" + switch \ld_active_q_ld_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ldst_port0_addr_ok_o[0:0] $2\ldst_port0_addr_ok_o[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:222" + switch \$31 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ldst_port0_addr_ok_o[0:0] 1'1 + case + assign $2\ldst_port0_addr_ok_o[0:0] 1'0 + end + case + assign $1\ldst_port0_addr_ok_o[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:229" + switch \st_active_q_st_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\ldst_port0_addr_ok_o[0:0] $4\ldst_port0_addr_ok_o[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:234" + switch \ldst_port0_addr_i_ok + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\ldst_port0_addr_ok_o[0:0] $5\ldst_port0_addr_ok_o[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:236" + switch \adrok_l_qn_addr_acked + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\ldst_port0_addr_ok_o[0:0] 1'1 + case + assign $5\ldst_port0_addr_ok_o[0:0] $1\ldst_port0_addr_ok_o[0:0] + end + case + assign $4\ldst_port0_addr_ok_o[0:0] $1\ldst_port0_addr_ok_o[0:0] + end + case + assign $3\ldst_port0_addr_ok_o[0:0] $1\ldst_port0_addr_ok_o[0:0] + end + sync always + update \ldst_port0_addr_ok_o $0\ldst_port0_addr_ok_o[0:0] + end + attribute \src "libresoc.v:147541.3-147556.6" + process $proc$libresoc.v:147541$8049 + assign { } { } + assign { } { } + assign { } { } + assign $0\reset_l_s_reset[0:0] $2\reset_l_s_reset[0:0] + attribute \src "libresoc.v:147542.5-147542.29" + switch \initial + attribute \src "libresoc.v:147542.9-147542.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:248" + switch \$33 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\reset_l_s_reset[0:0] \$35 + case + assign $1\reset_l_s_reset[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:265" + switch \st_done_q_st_done + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\reset_l_s_reset[0:0] \$37 + case + assign $2\reset_l_s_reset[0:0] $1\reset_l_s_reset[0:0] + end + sync always + update \reset_l_s_reset $0\reset_l_s_reset[0:0] + end + attribute \src "libresoc.v:147557.3-147566.6" + process $proc$libresoc.v:147557$8050 + assign { } { } + assign { } { } + assign $0\reset_l_r_reset[0:0] $1\reset_l_r_reset[0:0] + attribute \src "libresoc.v:147558.5-147558.29" + switch \initial + attribute \src "libresoc.v:147558.9-147558.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:275" + switch \reset_l_q_reset + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\reset_l_r_reset[0:0] 1'1 + case + assign $1\reset_l_r_reset[0:0] 1'0 + end + sync always + update \reset_l_r_reset $0\reset_l_r_reset[0:0] + end + attribute \src "libresoc.v:147567.3-147576.6" + process $proc$libresoc.v:147567$8051 + assign { } { } + assign { } { } + assign $0\ldst_port0_ld_data_o[63:0] $1\ldst_port0_ld_data_o[63:0] + attribute \src "libresoc.v:147568.5-147568.29" + switch \initial + attribute \src "libresoc.v:147568.9-147568.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:248" + switch \$48 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ldst_port0_ld_data_o[63:0] \lddata + case + assign $1\ldst_port0_ld_data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \ldst_port0_ld_data_o $0\ldst_port0_ld_data_o[63:0] + end + attribute \src "libresoc.v:147577.3-147586.6" + process $proc$libresoc.v:147577$8052 + assign { } { } + assign { } { } + assign $0\ld_active_r_ld_active[0:0] $1\ld_active_r_ld_active[0:0] + attribute \src "libresoc.v:147578.5-147578.29" + switch \initial + attribute \src "libresoc.v:147578.9-147578.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:275" + switch \reset_l_q_reset + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ld_active_r_ld_active[0:0] 1'1 + case + assign $1\ld_active_r_ld_active[0:0] 1'0 + end + sync always + update \ld_active_r_ld_active $0\ld_active_r_ld_active[0:0] + end + attribute \src "libresoc.v:147587.3-147596.6" + process $proc$libresoc.v:147587$8053 + assign { } { } + assign { } { } + assign $0\ldst_port0_ld_data_o_ok[0:0] $1\ldst_port0_ld_data_o_ok[0:0] + attribute \src "libresoc.v:147588.5-147588.29" + switch \initial + attribute \src "libresoc.v:147588.9-147588.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:248" + switch \$50 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ldst_port0_ld_data_o_ok[0:0] \$52 + case + assign $1\ldst_port0_ld_data_o_ok[0:0] 1'0 + end + sync always + update \ldst_port0_ld_data_o_ok $0\ldst_port0_ld_data_o_ok[0:0] + end + attribute \src "libresoc.v:147597.3-147606.6" + process $proc$libresoc.v:147597$8054 + assign { } { } + assign { } { } + assign $0\stdata[63:0] $1\stdata[63:0] + attribute \src "libresoc.v:147598.5-147598.29" + switch \initial + attribute \src "libresoc.v:147598.9-147598.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:256" + switch \$54 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\stdata[63:0] \$56 [63:0] + case + assign $1\stdata[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \stdata $0\stdata[63:0] + end + attribute \src "libresoc.v:147607.3-147616.6" + process $proc$libresoc.v:147607$8055 + assign { } { } + assign { } { } + assign $0\x_st_data_i[63:0] $1\x_st_data_i[63:0] + attribute \src "libresoc.v:147608.5-147608.29" + switch \initial + attribute \src "libresoc.v:147608.9-147608.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:256" + switch \$61 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\x_st_data_i[63:0] \stdata + case + assign $1\x_st_data_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \x_st_data_i $0\x_st_data_i[63:0] + end + attribute \src "libresoc.v:147617.3-147636.6" + process $proc$libresoc.v:147617$8056 + assign { } { } + assign { } { } + assign $0\lsui_busy[0:0] $1\lsui_busy[0:0] + attribute \src "libresoc.v:147618.5-147618.29" + switch \initial + attribute \src "libresoc.v:147618.9-147618.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:85" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\lsui_busy[0:0] $2\lsui_busy[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" + switch \$65 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\lsui_busy[0:0] 1'1 + case + assign $2\lsui_busy[0:0] 1'0 + end + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\lsui_busy[0:0] 1'1 + case + assign $1\lsui_busy[0:0] 1'0 + end + sync always + update \lsui_busy $0\lsui_busy[0:0] + end + attribute \src "libresoc.v:147637.3-147675.6" + process $proc$libresoc.v:147637$8057 + assign { } { } + assign { } { } + assign { } { } + assign $0\fsm_state$next[1:0]$8058 $5\fsm_state$next[1:0]$8063 + attribute \src "libresoc.v:147638.5-147638.29" + switch \initial + attribute \src "libresoc.v:147638.9-147638.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:85" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\fsm_state$next[1:0]$8059 $2\fsm_state$next[1:0]$8060 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" + switch \$69 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\fsm_state$next[1:0]$8060 2'01 + case + assign $2\fsm_state$next[1:0]$8060 \fsm_state + end + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\fsm_state$next[1:0]$8059 $3\fsm_state$next[1:0]$8061 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:95" + switch \$71 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fsm_state$next[1:0]$8061 2'10 + case + assign $3\fsm_state$next[1:0]$8061 \fsm_state + end + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\fsm_state$next[1:0]$8059 $4\fsm_state$next[1:0]$8062 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:99" + switch \$77 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\fsm_state$next[1:0]$8062 2'00 + case + assign $4\fsm_state$next[1:0]$8062 \fsm_state + end + case + assign $1\fsm_state$next[1:0]$8059 \fsm_state + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\fsm_state$next[1:0]$8063 2'00 + case + assign $5\fsm_state$next[1:0]$8063 $1\fsm_state$next[1:0]$8059 + end + sync always + update \fsm_state$next $0\fsm_state$next[1:0]$8058 + end + attribute \src "libresoc.v:147676.3-147685.6" + process $proc$libresoc.v:147676$8064 + assign { } { } + assign { } { } + assign $0\cyc_l_s_cyc[0:0] $1\cyc_l_s_cyc[0:0] + attribute \src "libresoc.v:147677.5-147677.29" + switch \initial + attribute \src "libresoc.v:147677.9-147677.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:288" + switch \reset_l_s_reset + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cyc_l_s_cyc[0:0] 1'1 + case + assign $1\cyc_l_s_cyc[0:0] 1'0 + end + sync always + update \cyc_l_s_cyc $0\cyc_l_s_cyc[0:0] + end + attribute \src "libresoc.v:147686.3-147694.6" + process $proc$libresoc.v:147686$8065 + assign { } { } + assign { } { } + assign $0\lsui_active_dly$next[0:0]$8066 $1\lsui_active_dly$next[0:0]$8067 + attribute \src "libresoc.v:147687.5-147687.29" + switch \initial + attribute \src "libresoc.v:147687.9-147687.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\lsui_active_dly$next[0:0]$8067 1'0 + case + assign $1\lsui_active_dly$next[0:0]$8067 \lsui_active + end + sync always + update \lsui_active_dly$next $0\lsui_active_dly$next[0:0]$8066 + end + attribute \src "libresoc.v:147695.3-147704.6" + process $proc$libresoc.v:147695$8068 + assign { } { } + assign { } { } + assign $0\cyc_l_r_cyc[0:0] $1\cyc_l_r_cyc[0:0] + attribute \src "libresoc.v:147696.5-147696.29" + switch \initial + attribute \src "libresoc.v:147696.9-147696.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:291" + switch \cyc_l_q_cyc + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cyc_l_r_cyc[0:0] 1'1 + case + assign $1\cyc_l_r_cyc[0:0] 1'0 + end + sync always + update \cyc_l_r_cyc $0\cyc_l_r_cyc[0:0] + end + attribute \src "libresoc.v:147705.3-147714.6" + process $proc$libresoc.v:147705$8069 + assign { } { } + assign { } { } + assign $0\busy_l_s_busy[0:0] $1\busy_l_s_busy[0:0] + attribute \src "libresoc.v:147706.5-147706.29" + switch \initial + attribute \src "libresoc.v:147706.9-147706.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:212" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\busy_l_s_busy[0:0] \$5 + case + assign $1\busy_l_s_busy[0:0] 1'0 + end + sync always + update \busy_l_s_busy $0\busy_l_s_busy[0:0] + end + attribute \src "libresoc.v:147715.3-147730.6" + process $proc$libresoc.v:147715$8070 + assign { } { } + assign { } { } + assign { } { } + assign $0\busy_l_r_busy[0:0] $2\busy_l_r_busy[0:0] + attribute \src "libresoc.v:147716.5-147716.29" + switch \initial + attribute \src "libresoc.v:147716.9-147716.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:283" + switch \ldst_port0_addr_exc_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\busy_l_r_busy[0:0] 1'1 + case + assign $1\busy_l_r_busy[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:291" + switch \cyc_l_q_cyc + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\busy_l_r_busy[0:0] 1'1 + case + assign $2\busy_l_r_busy[0:0] $1\busy_l_r_busy[0:0] + end + sync always + update \busy_l_r_busy $0\busy_l_r_busy[0:0] + end + attribute \src "libresoc.v:147731.3-147766.6" + process $proc$libresoc.v:147731$8071 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\adrok_l_s_addr_acked$next[0:0]$8072 $6\adrok_l_s_addr_acked$next[0:0]$8078 + attribute \src "libresoc.v:147732.5-147732.29" + switch \initial + attribute \src "libresoc.v:147732.9-147732.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:217" + switch \ld_active_q_ld_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\adrok_l_s_addr_acked$next[0:0]$8073 $2\adrok_l_s_addr_acked$next[0:0]$8074 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:222" + switch \$7 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\adrok_l_s_addr_acked$next[0:0]$8074 1'1 + case + assign $2\adrok_l_s_addr_acked$next[0:0]$8074 1'0 + end + case + assign $1\adrok_l_s_addr_acked$next[0:0]$8073 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:229" + switch \st_active_q_st_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\adrok_l_s_addr_acked$next[0:0]$8075 $4\adrok_l_s_addr_acked$next[0:0]$8076 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:234" + switch \ldst_port0_addr_i_ok + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\adrok_l_s_addr_acked$next[0:0]$8076 $5\adrok_l_s_addr_acked$next[0:0]$8077 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:236" + switch \adrok_l_qn_addr_acked + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\adrok_l_s_addr_acked$next[0:0]$8077 1'1 + case + assign $5\adrok_l_s_addr_acked$next[0:0]$8077 $1\adrok_l_s_addr_acked$next[0:0]$8073 + end + case + assign $4\adrok_l_s_addr_acked$next[0:0]$8076 $1\adrok_l_s_addr_acked$next[0:0]$8073 + end + case + assign $3\adrok_l_s_addr_acked$next[0:0]$8075 $1\adrok_l_s_addr_acked$next[0:0]$8073 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\adrok_l_s_addr_acked$next[0:0]$8078 1'0 + case + assign $6\adrok_l_s_addr_acked$next[0:0]$8078 $3\adrok_l_s_addr_acked$next[0:0]$8075 + end + sync always + update \adrok_l_s_addr_acked$next $0\adrok_l_s_addr_acked$next[0:0]$8072 + end + attribute \src "libresoc.v:147767.3-147782.6" + process $proc$libresoc.v:147767$8079 + assign { } { } + assign { } { } + assign { } { } + assign $0\adrok_l_r_addr_acked[0:0] $2\adrok_l_r_addr_acked[0:0] + attribute \src "libresoc.v:147768.5-147768.29" + switch \initial + attribute \src "libresoc.v:147768.9-147768.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:271" + switch \reset_delay + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\adrok_l_r_addr_acked[0:0] 1'1 + case + assign $1\adrok_l_r_addr_acked[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:275" + switch \reset_l_q_reset + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\adrok_l_r_addr_acked[0:0] 1'1 + case + assign $2\adrok_l_r_addr_acked[0:0] $1\adrok_l_r_addr_acked[0:0] + end + sync always + update \adrok_l_r_addr_acked $0\adrok_l_r_addr_acked[0:0] + end + connect \$9 $not$libresoc.v:147236$7983_Y + connect \$11 $and$libresoc.v:147237$7984_Y + connect \$13 $not$libresoc.v:147238$7985_Y + connect \$15 $and$libresoc.v:147239$7986_Y + connect \$17 $not$libresoc.v:147240$7987_Y + connect \$1 $and$libresoc.v:147241$7988_Y + connect \$19 $and$libresoc.v:147242$7989_Y + connect \$21 $pos$libresoc.v:147243$7991_Y + connect \$23 $pos$libresoc.v:147244$7993_Y + connect \$25 $and$libresoc.v:147245$7994_Y + connect \$27 $and$libresoc.v:147246$7995_Y + connect \$29 $and$libresoc.v:147247$7996_Y + connect \$31 $and$libresoc.v:147248$7997_Y + connect \$33 $and$libresoc.v:147249$7998_Y + connect \$35 $not$libresoc.v:147250$7999_Y + connect \$38 $or$libresoc.v:147251$8000_Y + connect \$3 $or$libresoc.v:147252$8001_Y + connect \$37 $not$libresoc.v:147253$8002_Y + connect \$42 $and$libresoc.v:147254$8003_Y + connect \$44 $mul$libresoc.v:147255$8004_Y + connect \$46 $sshr$libresoc.v:147256$8005_Y + connect \$48 $and$libresoc.v:147257$8006_Y + connect \$50 $and$libresoc.v:147258$8007_Y + connect \$52 $not$libresoc.v:147259$8008_Y + connect \$54 $and$libresoc.v:147260$8009_Y + connect \$57 $mul$libresoc.v:147261$8010_Y + connect \$5 $not$libresoc.v:147262$8011_Y + connect \$59 $sshl$libresoc.v:147263$8012_Y + connect \$61 $and$libresoc.v:147264$8013_Y + connect \$63 $or$libresoc.v:147265$8014_Y + connect \$65 $and$libresoc.v:147266$8015_Y + connect \$67 $or$libresoc.v:147267$8016_Y + connect \$69 $and$libresoc.v:147268$8017_Y + connect \$71 $not$libresoc.v:147269$8018_Y + connect \$73 $not$libresoc.v:147270$8019_Y + connect \$75 $not$libresoc.v:147271$8020_Y + connect \$77 $and$libresoc.v:147272$8021_Y + connect \$7 $and$libresoc.v:147273$8022_Y + connect \$79 $not$libresoc.v:147274$8023_Y + connect \$81 $not$libresoc.v:147275$8024_Y + connect \$83 $and$libresoc.v:147276$8025_Y + connect \$41 \$46 + connect \$56 \$59 + connect \valid_l_r_valid \lsui_active_rise + connect \lsui_active_rise \$83 + connect \lsui_active \$79 + connect \x_valid_i \valid_l_q_valid + connect \m_valid_i \valid_l_q_valid + connect \x_st_i \ldst_port0_is_st_i + connect \x_ld_i \ldst_port0_is_ld_i + connect \ldst_port0_busy_o \busy_l_q_busy + connect \reset_delay$next \reset_l_q_reset + connect \lddata \$46 [63:0] + connect \st_active_s_st_active \sts_rise + connect \sts_rise \$19 + connect \sts_dly$next \sts + connect \ld_active_s_ld_active \lds_rise + connect \lds_rise \$15 + connect \lds_dly$next \lds + connect \busy_edge \$11 + connect \sts \ldst_port0_is_st_i + connect \lds \ldst_port0_is_ld_i +end +attribute \src "libresoc.v:147808.1-148573.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.alu_cr0.pipe" +attribute \generator "nMigen" +module \pipe + attribute \src "libresoc.v:148536.3-148554.6" + wire width 4 $0\cr_a$6$next[3:0]$8135 + attribute \src "libresoc.v:148400.3-148401.31" + wire width 4 $0\cr_a$6[3:0]$8091 + attribute \src "libresoc.v:147822.13-147822.28" + wire width 4 $0\cr_a$6[3:0]$8141 + attribute \src "libresoc.v:148536.3-148554.6" + wire $0\cr_a_ok$next[0:0]$8134 + attribute \src "libresoc.v:148402.3-148403.31" + wire $0\cr_a_ok[0:0] + attribute \src "libresoc.v:148483.3-148497.6" + wire width 12 $0\cr_op__fn_unit$3$next[11:0]$8115 + attribute \src "libresoc.v:148414.3-148415.51" + wire width 12 $0\cr_op__fn_unit$3[11:0]$8101 + attribute \src "libresoc.v:147881.14-147881.42" + wire width 12 $0\cr_op__fn_unit$3[11:0]$8144 + attribute \src "libresoc.v:148483.3-148497.6" + wire width 32 $0\cr_op__insn$4$next[31:0]$8116 + attribute \src "libresoc.v:148416.3-148417.45" + wire width 32 $0\cr_op__insn$4[31:0]$8103 + attribute \src "libresoc.v:147890.14-147890.37" + wire width 32 $0\cr_op__insn$4[31:0]$8146 + attribute \src "libresoc.v:148483.3-148497.6" + wire width 7 $0\cr_op__insn_type$2$next[6:0]$8117 + attribute \src "libresoc.v:148412.3-148413.55" + wire width 7 $0\cr_op__insn_type$2[6:0]$8099 + attribute \src "libresoc.v:148121.13-148121.41" + wire width 7 $0\cr_op__insn_type$2[6:0]$8148 + attribute \src "libresoc.v:148517.3-148535.6" + wire width 32 $0\full_cr$5$next[31:0]$8128 + attribute \src "libresoc.v:148404.3-148405.37" + wire width 32 $0\full_cr$5[31:0]$8094 + attribute \src "libresoc.v:148130.14-148130.33" + wire width 32 $0\full_cr$5[31:0]$8150 + attribute \src "libresoc.v:148517.3-148535.6" + wire $0\full_cr_ok$next[0:0]$8129 + attribute \src "libresoc.v:148406.3-148407.37" + wire $0\full_cr_ok[0:0] + attribute \src "libresoc.v:147809.7-147809.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:148470.3-148482.6" + wire width 2 $0\muxid$1$next[1:0]$8112 + attribute \src "libresoc.v:148418.3-148419.33" + wire width 2 $0\muxid$1[1:0]$8105 + attribute \src "libresoc.v:148358.13-148358.29" + wire width 2 $0\muxid$1[1:0]$8153 + attribute \src "libresoc.v:148498.3-148516.6" + wire width 64 $0\o$next[63:0]$8122 + attribute \src "libresoc.v:148408.3-148409.19" + wire width 64 $0\o[63:0] + attribute \src "libresoc.v:148498.3-148516.6" + wire $0\o_ok$next[0:0]$8123 + attribute \src "libresoc.v:148410.3-148411.25" + wire $0\o_ok[0:0] + attribute \src "libresoc.v:148452.3-148469.6" + wire $0\r_busy$next[0:0]$8108 + attribute \src "libresoc.v:148420.3-148421.29" + wire $0\r_busy[0:0] + attribute \src "libresoc.v:148536.3-148554.6" + wire width 4 $1\cr_a$6$next[3:0]$8137 + attribute \src "libresoc.v:148536.3-148554.6" + wire $1\cr_a_ok$next[0:0]$8136 + attribute \src "libresoc.v:147827.7-147827.21" + wire $1\cr_a_ok[0:0] + attribute \src "libresoc.v:148483.3-148497.6" + wire width 12 $1\cr_op__fn_unit$3$next[11:0]$8118 + attribute \src "libresoc.v:148483.3-148497.6" + wire width 32 $1\cr_op__insn$4$next[31:0]$8119 + attribute \src "libresoc.v:148483.3-148497.6" + wire width 7 $1\cr_op__insn_type$2$next[6:0]$8120 + attribute \src "libresoc.v:148517.3-148535.6" + wire width 32 $1\full_cr$5$next[31:0]$8130 + attribute \src "libresoc.v:148517.3-148535.6" + wire $1\full_cr_ok$next[0:0]$8131 + attribute \src "libresoc.v:148135.7-148135.24" + wire $1\full_cr_ok[0:0] + attribute \src "libresoc.v:148470.3-148482.6" + wire width 2 $1\muxid$1$next[1:0]$8113 + attribute \src "libresoc.v:148498.3-148516.6" + wire width 64 $1\o$next[63:0]$8124 + attribute \src "libresoc.v:148371.14-148371.38" + wire width 64 $1\o[63:0] + attribute \src "libresoc.v:148498.3-148516.6" + wire $1\o_ok$next[0:0]$8125 + attribute \src "libresoc.v:148378.7-148378.18" + wire $1\o_ok[0:0] + attribute \src "libresoc.v:148452.3-148469.6" + wire $1\r_busy$next[0:0]$8109 + attribute \src "libresoc.v:148392.7-148392.20" + wire $1\r_busy[0:0] + attribute \src "libresoc.v:148536.3-148554.6" + wire $2\cr_a_ok$next[0:0]$8138 + attribute \src "libresoc.v:148517.3-148535.6" + wire $2\full_cr_ok$next[0:0]$8132 + attribute \src "libresoc.v:148498.3-148516.6" + wire $2\o_ok$next[0:0]$8126 + attribute \src "libresoc.v:148452.3-148469.6" + wire $2\r_busy$next[0:0]$8110 + attribute \src "libresoc.v:148399.18-148399.118" + wire $and$libresoc.v:148399$8089_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + wire \$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 26 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 4 input 11 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \cr_a$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 output 24 \cr_a$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \cr_a$6$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 25 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_a_ok$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_a_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 4 input 12 \cr_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 4 input 13 \cr_c + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 6 \cr_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \cr_op__fn_unit$18 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 output 18 \cr_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \cr_op__fn_unit$3$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 7 \cr_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \cr_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 19 \cr_op__insn$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \cr_op__insn$4$next + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 5 \cr_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \cr_op__insn_type$17 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 17 \cr_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \cr_op__insn_type$2$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 32 input 10 \full_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 32 \full_cr$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 32 output 22 \full_cr$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 32 \full_cr$5$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 23 \full_cr_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \full_cr_ok$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \full_cr_ok$next + attribute \src "libresoc.v:147809.7-147809.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 4 \main_cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \main_cr_a$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \main_cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 4 \main_cr_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 4 \main_cr_c + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \main_cr_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \main_cr_op__fn_unit$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \main_cr_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \main_cr_op__insn$10 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \main_cr_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \main_cr_op__insn_type$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 32 \main_full_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 32 \main_full_cr$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \main_full_cr_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \main_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \main_muxid$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \main_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \main_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \main_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \main_rb + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 4 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 16 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$1$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" + wire \n_i_rdy_data + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire input 15 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire output 14 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 20 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \o$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \o$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 21 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \o_ok$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \o_ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire output 3 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" + wire \p_valid_i$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire \r_busy$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 8 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 9 \rb + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + cell $and $and$libresoc.v:148399$8089 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i$13 + connect \B \p_ready_o + connect \Y $and$libresoc.v:148399$8089_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:148422.12-148443.4" + cell \main$9 \main + connect \cr_a \main_cr_a + connect \cr_a$6 \main_cr_a$12 + connect \cr_a_ok \main_cr_a_ok + connect \cr_b \main_cr_b + connect \cr_c \main_cr_c + connect \cr_op__fn_unit \main_cr_op__fn_unit + connect \cr_op__fn_unit$3 \main_cr_op__fn_unit$9 + connect \cr_op__insn \main_cr_op__insn + connect \cr_op__insn$4 \main_cr_op__insn$10 + connect \cr_op__insn_type \main_cr_op__insn_type + connect \cr_op__insn_type$2 \main_cr_op__insn_type$8 + connect \full_cr \main_full_cr + connect \full_cr$5 \main_full_cr$11 + connect \full_cr_ok \main_full_cr_ok + connect \muxid \main_muxid + connect \muxid$1 \main_muxid$7 + connect \o \main_o + connect \o_ok \main_o_ok + connect \ra \main_ra + connect \rb \main_rb + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:148444.9-148447.4" + cell \n$8 \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:148448.9-148451.4" + cell \p$7 \p + connect \p_ready_o \p_ready_o + connect \p_valid_i \p_valid_i + end + attribute \src "libresoc.v:147809.7-147809.20" + process $proc$libresoc.v:147809$8139 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:147822.13-147822.28" + process $proc$libresoc.v:147822$8140 + assign { } { } + assign $0\cr_a$6[3:0]$8141 4'0000 + sync always + sync init + update \cr_a$6 $0\cr_a$6[3:0]$8141 + end + attribute \src "libresoc.v:147827.7-147827.21" + process $proc$libresoc.v:147827$8142 + assign { } { } + assign $1\cr_a_ok[0:0] 1'0 + sync always + sync init + update \cr_a_ok $1\cr_a_ok[0:0] + end + attribute \src "libresoc.v:147881.14-147881.42" + process $proc$libresoc.v:147881$8143 + assign { } { } + assign $0\cr_op__fn_unit$3[11:0]$8144 12'000000000000 + sync always + sync init + update \cr_op__fn_unit$3 $0\cr_op__fn_unit$3[11:0]$8144 + end + attribute \src "libresoc.v:147890.14-147890.37" + process $proc$libresoc.v:147890$8145 + assign { } { } + assign $0\cr_op__insn$4[31:0]$8146 0 + sync always + sync init + update \cr_op__insn$4 $0\cr_op__insn$4[31:0]$8146 + end + attribute \src "libresoc.v:148121.13-148121.41" + process $proc$libresoc.v:148121$8147 + assign { } { } + assign $0\cr_op__insn_type$2[6:0]$8148 7'0000000 + sync always + sync init + update \cr_op__insn_type$2 $0\cr_op__insn_type$2[6:0]$8148 + end + attribute \src "libresoc.v:148130.14-148130.33" + process $proc$libresoc.v:148130$8149 + assign { } { } + assign $0\full_cr$5[31:0]$8150 0 + sync always + sync init + update \full_cr$5 $0\full_cr$5[31:0]$8150 + end + attribute \src "libresoc.v:148135.7-148135.24" + process $proc$libresoc.v:148135$8151 + assign { } { } + assign $1\full_cr_ok[0:0] 1'0 + sync always + sync init + update \full_cr_ok $1\full_cr_ok[0:0] + end + attribute \src "libresoc.v:148358.13-148358.29" + process $proc$libresoc.v:148358$8152 + assign { } { } + assign $0\muxid$1[1:0]$8153 2'00 + sync always + sync init + update \muxid$1 $0\muxid$1[1:0]$8153 + end + attribute \src "libresoc.v:148371.14-148371.38" + process $proc$libresoc.v:148371$8154 + assign { } { } + assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \o $1\o[63:0] + end + attribute \src "libresoc.v:148378.7-148378.18" + process $proc$libresoc.v:148378$8155 + assign { } { } + assign $1\o_ok[0:0] 1'0 + sync always + sync init + update \o_ok $1\o_ok[0:0] + end + attribute \src "libresoc.v:148392.7-148392.20" + process $proc$libresoc.v:148392$8156 + assign { } { } + assign $1\r_busy[0:0] 1'0 + sync always + sync init + update \r_busy $1\r_busy[0:0] + end + attribute \src "libresoc.v:148400.3-148401.31" + process $proc$libresoc.v:148400$8090 + assign { } { } + assign $0\cr_a$6[3:0]$8091 \cr_a$6$next + sync posedge \coresync_clk + update \cr_a$6 $0\cr_a$6[3:0]$8091 + end + attribute \src "libresoc.v:148402.3-148403.31" + process $proc$libresoc.v:148402$8092 + assign { } { } + assign $0\cr_a_ok[0:0] \cr_a_ok$next + sync posedge \coresync_clk + update \cr_a_ok $0\cr_a_ok[0:0] + end + attribute \src "libresoc.v:148404.3-148405.37" + process $proc$libresoc.v:148404$8093 + assign { } { } + assign $0\full_cr$5[31:0]$8094 \full_cr$5$next + sync posedge \coresync_clk + update \full_cr$5 $0\full_cr$5[31:0]$8094 + end + attribute \src "libresoc.v:148406.3-148407.37" + process $proc$libresoc.v:148406$8095 + assign { } { } + assign $0\full_cr_ok[0:0] \full_cr_ok$next + sync posedge \coresync_clk + update \full_cr_ok $0\full_cr_ok[0:0] + end + attribute \src "libresoc.v:148408.3-148409.19" + process $proc$libresoc.v:148408$8096 + assign { } { } + assign $0\o[63:0] \o$next + sync posedge \coresync_clk + update \o $0\o[63:0] + end + attribute \src "libresoc.v:148410.3-148411.25" + process $proc$libresoc.v:148410$8097 + assign { } { } + assign $0\o_ok[0:0] \o_ok$next + sync posedge \coresync_clk + update \o_ok $0\o_ok[0:0] + end + attribute \src "libresoc.v:148412.3-148413.55" + process $proc$libresoc.v:148412$8098 + assign { } { } + assign $0\cr_op__insn_type$2[6:0]$8099 \cr_op__insn_type$2$next + sync posedge \coresync_clk + update \cr_op__insn_type$2 $0\cr_op__insn_type$2[6:0]$8099 + end + attribute \src "libresoc.v:148414.3-148415.51" + process $proc$libresoc.v:148414$8100 + assign { } { } + assign $0\cr_op__fn_unit$3[11:0]$8101 \cr_op__fn_unit$3$next + sync posedge \coresync_clk + update \cr_op__fn_unit$3 $0\cr_op__fn_unit$3[11:0]$8101 + end + attribute \src "libresoc.v:148416.3-148417.45" + process $proc$libresoc.v:148416$8102 + assign { } { } + assign $0\cr_op__insn$4[31:0]$8103 \cr_op__insn$4$next + sync posedge \coresync_clk + update \cr_op__insn$4 $0\cr_op__insn$4[31:0]$8103 + end + attribute \src "libresoc.v:148418.3-148419.33" + process $proc$libresoc.v:148418$8104 + assign { } { } + assign $0\muxid$1[1:0]$8105 \muxid$1$next + sync posedge \coresync_clk + update \muxid$1 $0\muxid$1[1:0]$8105 + end + attribute \src "libresoc.v:148420.3-148421.29" + process $proc$libresoc.v:148420$8106 + assign { } { } + assign $0\r_busy[0:0] \r_busy$next + sync posedge \coresync_clk + update \r_busy $0\r_busy[0:0] + end + attribute \src "libresoc.v:148452.3-148469.6" + process $proc$libresoc.v:148452$8107 + assign { } { } + assign { } { } + assign { } { } + assign $0\r_busy$next[0:0]$8108 $2\r_busy$next[0:0]$8110 + attribute \src "libresoc.v:148453.5-148453.29" + switch \initial + attribute \src "libresoc.v:148453.9-148453.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\r_busy$next[0:0]$8109 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\r_busy$next[0:0]$8109 1'0 + case + assign $1\r_busy$next[0:0]$8109 \r_busy + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r_busy$next[0:0]$8110 1'0 + case + assign $2\r_busy$next[0:0]$8110 $1\r_busy$next[0:0]$8109 + end + sync always + update \r_busy$next $0\r_busy$next[0:0]$8108 + end + attribute \src "libresoc.v:148470.3-148482.6" + process $proc$libresoc.v:148470$8111 + assign { } { } + assign { } { } + assign $0\muxid$1$next[1:0]$8112 $1\muxid$1$next[1:0]$8113 + attribute \src "libresoc.v:148471.5-148471.29" + switch \initial + attribute \src "libresoc.v:148471.9-148471.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\muxid$1$next[1:0]$8113 \muxid$16 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\muxid$1$next[1:0]$8113 \muxid$16 + case + assign $1\muxid$1$next[1:0]$8113 \muxid$1 + end + sync always + update \muxid$1$next $0\muxid$1$next[1:0]$8112 + end + attribute \src "libresoc.v:148483.3-148497.6" + process $proc$libresoc.v:148483$8114 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\cr_op__fn_unit$3$next[11:0]$8115 $1\cr_op__fn_unit$3$next[11:0]$8118 + assign $0\cr_op__insn$4$next[31:0]$8116 $1\cr_op__insn$4$next[31:0]$8119 + assign $0\cr_op__insn_type$2$next[6:0]$8117 $1\cr_op__insn_type$2$next[6:0]$8120 + attribute \src "libresoc.v:148484.5-148484.29" + switch \initial + attribute \src "libresoc.v:148484.9-148484.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { } { } + assign { $1\cr_op__insn$4$next[31:0]$8119 $1\cr_op__fn_unit$3$next[11:0]$8118 $1\cr_op__insn_type$2$next[6:0]$8120 } { \cr_op__insn$19 \cr_op__fn_unit$18 \cr_op__insn_type$17 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { } { } + assign { $1\cr_op__insn$4$next[31:0]$8119 $1\cr_op__fn_unit$3$next[11:0]$8118 $1\cr_op__insn_type$2$next[6:0]$8120 } { \cr_op__insn$19 \cr_op__fn_unit$18 \cr_op__insn_type$17 } + case + assign $1\cr_op__fn_unit$3$next[11:0]$8118 \cr_op__fn_unit$3 + assign $1\cr_op__insn$4$next[31:0]$8119 \cr_op__insn$4 + assign $1\cr_op__insn_type$2$next[6:0]$8120 \cr_op__insn_type$2 + end + sync always + update \cr_op__fn_unit$3$next $0\cr_op__fn_unit$3$next[11:0]$8115 + update \cr_op__insn$4$next $0\cr_op__insn$4$next[31:0]$8116 + update \cr_op__insn_type$2$next $0\cr_op__insn_type$2$next[6:0]$8117 + end + attribute \src "libresoc.v:148498.3-148516.6" + process $proc$libresoc.v:148498$8121 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\o$next[63:0]$8122 $1\o$next[63:0]$8124 + assign { } { } + assign $0\o_ok$next[0:0]$8123 $2\o_ok$next[0:0]$8126 + attribute \src "libresoc.v:148499.5-148499.29" + switch \initial + attribute \src "libresoc.v:148499.9-148499.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\o_ok$next[0:0]$8125 $1\o$next[63:0]$8124 } { \o_ok$21 \o$20 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\o_ok$next[0:0]$8125 $1\o$next[63:0]$8124 } { \o_ok$21 \o$20 } + case + assign $1\o$next[63:0]$8124 \o + assign $1\o_ok$next[0:0]$8125 \o_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\o_ok$next[0:0]$8126 1'0 + case + assign $2\o_ok$next[0:0]$8126 $1\o_ok$next[0:0]$8125 + end + sync always + update \o$next $0\o$next[63:0]$8122 + update \o_ok$next $0\o_ok$next[0:0]$8123 + end + attribute \src "libresoc.v:148517.3-148535.6" + process $proc$libresoc.v:148517$8127 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\full_cr$5$next[31:0]$8128 $1\full_cr$5$next[31:0]$8130 + assign { } { } + assign $0\full_cr_ok$next[0:0]$8129 $2\full_cr_ok$next[0:0]$8132 + attribute \src "libresoc.v:148518.5-148518.29" + switch \initial + attribute \src "libresoc.v:148518.9-148518.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\full_cr_ok$next[0:0]$8131 $1\full_cr$5$next[31:0]$8130 } { \full_cr_ok$23 \full_cr$22 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\full_cr_ok$next[0:0]$8131 $1\full_cr$5$next[31:0]$8130 } { \full_cr_ok$23 \full_cr$22 } + case + assign $1\full_cr$5$next[31:0]$8130 \full_cr$5 + assign $1\full_cr_ok$next[0:0]$8131 \full_cr_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\full_cr_ok$next[0:0]$8132 1'0 + case + assign $2\full_cr_ok$next[0:0]$8132 $1\full_cr_ok$next[0:0]$8131 + end + sync always + update \full_cr$5$next $0\full_cr$5$next[31:0]$8128 + update \full_cr_ok$next $0\full_cr_ok$next[0:0]$8129 + end + attribute \src "libresoc.v:148536.3-148554.6" + process $proc$libresoc.v:148536$8133 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\cr_a$6$next[3:0]$8135 $1\cr_a$6$next[3:0]$8137 + assign $0\cr_a_ok$next[0:0]$8134 $2\cr_a_ok$next[0:0]$8138 + attribute \src "libresoc.v:148537.5-148537.29" + switch \initial + attribute \src "libresoc.v:148537.9-148537.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\cr_a_ok$next[0:0]$8136 $1\cr_a$6$next[3:0]$8137 } { \cr_a_ok$25 \cr_a$24 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\cr_a_ok$next[0:0]$8136 $1\cr_a$6$next[3:0]$8137 } { \cr_a_ok$25 \cr_a$24 } + case + assign $1\cr_a_ok$next[0:0]$8136 \cr_a_ok + assign $1\cr_a$6$next[3:0]$8137 \cr_a$6 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_a_ok$next[0:0]$8138 1'0 + case + assign $2\cr_a_ok$next[0:0]$8138 $1\cr_a_ok$next[0:0]$8136 + end + sync always + update \cr_a_ok$next $0\cr_a_ok$next[0:0]$8134 + update \cr_a$6$next $0\cr_a$6$next[3:0]$8135 + end + connect \$14 $and$libresoc.v:148399$8089_Y + connect \p_ready_o \n_i_rdy_data + connect \n_valid_o \r_busy + connect { \cr_a_ok$25 \cr_a$24 } { \main_cr_a_ok \main_cr_a$12 } + connect { \full_cr_ok$23 \full_cr$22 } { \main_full_cr_ok \main_full_cr$11 } + connect { \o_ok$21 \o$20 } { \main_o_ok \main_o } + connect { \cr_op__insn$19 \cr_op__fn_unit$18 \cr_op__insn_type$17 } { \main_cr_op__insn$10 \main_cr_op__fn_unit$9 \main_cr_op__insn_type$8 } + connect \muxid$16 \main_muxid$7 + connect \p_valid_i_p_ready_o \$14 + connect \n_i_rdy_data \n_ready_i + connect \p_valid_i$13 \p_valid_i + connect \main_cr_c \cr_c + connect \main_cr_b \cr_b + connect \main_cr_a \cr_a + connect \main_full_cr \full_cr + connect \main_rb \rb + connect \main_ra \ra + connect { \main_cr_op__insn \main_cr_op__fn_unit \main_cr_op__insn_type } { \cr_op__insn \cr_op__fn_unit \cr_op__insn_type } + connect \main_muxid \muxid +end +attribute \src "libresoc.v:148577.1-149422.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.alu_branch0.pipe" +attribute \generator "nMigen" +module \pipe$19 + attribute \src "libresoc.v:149322.3-149349.6" + wire width 64 $0\br_op__cia$2$next[63:0]$8193 + attribute \src "libresoc.v:149234.3-149235.43" + wire width 64 $0\br_op__cia$2[63:0]$8167 + attribute \src "libresoc.v:148585.14-148585.51" + wire width 64 $0\br_op__cia$2[63:0]$8231 + attribute \src "libresoc.v:149322.3-149349.6" + wire width 12 $0\br_op__fn_unit$4$next[11:0]$8194 + attribute \src "libresoc.v:149238.3-149239.51" + wire width 12 $0\br_op__fn_unit$4[11:0]$8171 + attribute \src "libresoc.v:148635.14-148635.42" + wire width 12 $0\br_op__fn_unit$4[11:0]$8233 + attribute \src "libresoc.v:149322.3-149349.6" + wire width 64 $0\br_op__imm_data__data$6$next[63:0]$8195 + attribute \src "libresoc.v:149242.3-149243.65" + wire width 64 $0\br_op__imm_data__data$6[63:0]$8175 + attribute \src "libresoc.v:148644.14-148644.62" + wire width 64 $0\br_op__imm_data__data$6[63:0]$8235 + attribute \src "libresoc.v:149322.3-149349.6" + wire $0\br_op__imm_data__ok$7$next[0:0]$8196 + attribute \src "libresoc.v:149244.3-149245.61" + wire $0\br_op__imm_data__ok$7[0:0]$8177 + attribute \src "libresoc.v:148653.7-148653.37" + wire $0\br_op__imm_data__ok$7[0:0]$8237 + attribute \src "libresoc.v:149322.3-149349.6" + wire width 32 $0\br_op__insn$5$next[31:0]$8197 + attribute \src "libresoc.v:149240.3-149241.45" + wire width 32 $0\br_op__insn$5[31:0]$8173 + attribute \src "libresoc.v:148662.14-148662.37" + wire width 32 $0\br_op__insn$5[31:0]$8239 + attribute \src "libresoc.v:149322.3-149349.6" + wire width 7 $0\br_op__insn_type$3$next[6:0]$8198 + attribute \src "libresoc.v:149236.3-149237.55" + wire width 7 $0\br_op__insn_type$3[6:0]$8169 + attribute \src "libresoc.v:148893.13-148893.41" + wire width 7 $0\br_op__insn_type$3[6:0]$8241 + attribute \src "libresoc.v:149322.3-149349.6" + wire $0\br_op__is_32bit$9$next[0:0]$8199 + attribute \src "libresoc.v:149248.3-149249.53" + wire $0\br_op__is_32bit$9[0:0]$8181 + attribute \src "libresoc.v:148902.7-148902.33" + wire $0\br_op__is_32bit$9[0:0]$8243 + attribute \src "libresoc.v:149322.3-149349.6" + wire $0\br_op__lk$8$next[0:0]$8200 + attribute \src "libresoc.v:149246.3-149247.41" + wire $0\br_op__lk$8[0:0]$8179 + attribute \src "libresoc.v:148911.7-148911.27" + wire $0\br_op__lk$8[0:0]$8245 + attribute \src "libresoc.v:149350.3-149368.6" + wire width 64 $0\fast1$10$next[63:0]$8212 + attribute \src "libresoc.v:149230.3-149231.35" + wire width 64 $0\fast1$10[63:0]$8164 + attribute \src "libresoc.v:148924.14-148924.47" + wire width 64 $0\fast1$10[63:0]$8247 + attribute \src "libresoc.v:149350.3-149368.6" + wire $0\fast1_ok$next[0:0]$8213 + attribute \src "libresoc.v:149232.3-149233.33" + wire $0\fast1_ok[0:0] + attribute \src "libresoc.v:149369.3-149387.6" + wire width 64 $0\fast2$11$next[63:0]$8218 + attribute \src "libresoc.v:149226.3-149227.35" + wire width 64 $0\fast2$11[63:0]$8161 + attribute \src "libresoc.v:148940.14-148940.47" + wire width 64 $0\fast2$11[63:0]$8250 + attribute \src "libresoc.v:149369.3-149387.6" + wire $0\fast2_ok$next[0:0]$8219 + attribute \src "libresoc.v:149228.3-149229.33" + wire $0\fast2_ok[0:0] + attribute \src "libresoc.v:148578.7-148578.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:149309.3-149321.6" + wire width 2 $0\muxid$1$next[1:0]$8190 + attribute \src "libresoc.v:149250.3-149251.33" + wire width 2 $0\muxid$1[1:0]$8183 + attribute \src "libresoc.v:149184.13-149184.29" + wire width 2 $0\muxid$1[1:0]$8253 + attribute \src "libresoc.v:149388.3-149406.6" + wire width 64 $0\nia$next[63:0]$8224 + attribute \src "libresoc.v:149222.3-149223.23" + wire width 64 $0\nia[63:0] + attribute \src "libresoc.v:149388.3-149406.6" + wire $0\nia_ok$next[0:0]$8225 + attribute \src "libresoc.v:149224.3-149225.29" + wire $0\nia_ok[0:0] + attribute \src "libresoc.v:149291.3-149308.6" + wire $0\r_busy$next[0:0]$8186 + attribute \src "libresoc.v:149252.3-149253.29" + wire $0\r_busy[0:0] + attribute \src "libresoc.v:149322.3-149349.6" + wire width 64 $1\br_op__cia$2$next[63:0]$8201 + attribute \src "libresoc.v:149322.3-149349.6" + wire width 12 $1\br_op__fn_unit$4$next[11:0]$8202 + attribute \src "libresoc.v:149322.3-149349.6" + wire width 64 $1\br_op__imm_data__data$6$next[63:0]$8203 + attribute \src "libresoc.v:149322.3-149349.6" + wire $1\br_op__imm_data__ok$7$next[0:0]$8204 + attribute \src "libresoc.v:149322.3-149349.6" + wire width 32 $1\br_op__insn$5$next[31:0]$8205 + attribute \src "libresoc.v:149322.3-149349.6" + wire width 7 $1\br_op__insn_type$3$next[6:0]$8206 + attribute \src "libresoc.v:149322.3-149349.6" + wire $1\br_op__is_32bit$9$next[0:0]$8207 + attribute \src "libresoc.v:149322.3-149349.6" + wire $1\br_op__lk$8$next[0:0]$8208 + attribute \src "libresoc.v:149350.3-149368.6" + wire width 64 $1\fast1$10$next[63:0]$8214 + attribute \src "libresoc.v:149350.3-149368.6" + wire $1\fast1_ok$next[0:0]$8215 + attribute \src "libresoc.v:148931.7-148931.22" + wire $1\fast1_ok[0:0] + attribute \src "libresoc.v:149369.3-149387.6" + wire width 64 $1\fast2$11$next[63:0]$8220 + attribute \src "libresoc.v:149369.3-149387.6" + wire $1\fast2_ok$next[0:0]$8221 + attribute \src "libresoc.v:148947.7-148947.22" + wire $1\fast2_ok[0:0] + attribute \src "libresoc.v:149309.3-149321.6" + wire width 2 $1\muxid$1$next[1:0]$8191 + attribute \src "libresoc.v:149388.3-149406.6" + wire width 64 $1\nia$next[63:0]$8226 + attribute \src "libresoc.v:149197.14-149197.40" + wire width 64 $1\nia[63:0] + attribute \src "libresoc.v:149388.3-149406.6" + wire $1\nia_ok$next[0:0]$8227 + attribute \src "libresoc.v:149204.7-149204.20" + wire $1\nia_ok[0:0] + attribute \src "libresoc.v:149291.3-149308.6" + wire $1\r_busy$next[0:0]$8187 + attribute \src "libresoc.v:149218.7-149218.20" + wire $1\r_busy[0:0] + attribute \src "libresoc.v:149322.3-149349.6" + wire width 64 $2\br_op__imm_data__data$6$next[63:0]$8209 + attribute \src "libresoc.v:149322.3-149349.6" + wire $2\br_op__imm_data__ok$7$next[0:0]$8210 + attribute \src "libresoc.v:149350.3-149368.6" + wire $2\fast1_ok$next[0:0]$8216 + attribute \src "libresoc.v:149369.3-149387.6" + wire $2\fast2_ok$next[0:0]$8222 + attribute \src "libresoc.v:149388.3-149406.6" + wire $2\nia_ok$next[0:0]$8228 + attribute \src "libresoc.v:149291.3-149308.6" + wire $2\r_busy$next[0:0]$8188 + attribute \src "libresoc.v:149221.18-149221.118" + wire $and$libresoc.v:149221$8157_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 5 \br_op__cia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 19 \br_op__cia$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \br_op__cia$2$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \br_op__cia$27 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 7 \br_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \br_op__fn_unit$29 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 output 21 \br_op__fn_unit$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \br_op__fn_unit$4$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 9 \br_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \br_op__imm_data__data$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 23 \br_op__imm_data__data$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \br_op__imm_data__data$6$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \br_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \br_op__imm_data__ok$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 24 \br_op__imm_data__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \br_op__imm_data__ok$7$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 8 \br_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \br_op__insn$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 22 \br_op__insn$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \br_op__insn$5$next + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 6 \br_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \br_op__insn_type$28 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 20 \br_op__insn_type$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \br_op__insn_type$3$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \br_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \br_op__is_32bit$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 26 \br_op__is_32bit$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \br_op__is_32bit$9$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 11 \br_op__lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \br_op__lk$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 25 \br_op__lk$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \br_op__lk$8$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 33 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 4 input 15 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 13 \fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 27 \fast1$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \fast1$10$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \fast1$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 28 \fast1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \fast1_ok$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \fast1_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 14 \fast2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 29 \fast2$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \fast2$11$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \fast2$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 30 \fast2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \fast2_ok$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \fast2_ok$next + attribute \src "libresoc.v:148578.7-148578.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \main_br_op__cia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \main_br_op__cia$13 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \main_br_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \main_br_op__fn_unit$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \main_br_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \main_br_op__imm_data__data$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_br_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_br_op__imm_data__ok$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \main_br_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \main_br_op__insn$16 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \main_br_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \main_br_op__insn_type$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_br_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_br_op__is_32bit$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_br_op__lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_br_op__lk$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 4 \main_cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \main_fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \main_fast1$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \main_fast1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \main_fast2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \main_fast2$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \main_fast2_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \main_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \main_muxid$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \main_nia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \main_nia_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 4 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 18 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$1$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$26 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" + wire \n_i_rdy_data + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire input 17 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire output 16 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 31 \nia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \nia$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \nia$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 32 \nia_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \nia_ok$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \nia_ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire output 3 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" + wire \p_valid_i$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire \r_busy$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + cell $and $and$libresoc.v:149221$8157 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i$23 + connect \B \p_ready_o + connect \Y $and$libresoc.v:149221$8157_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:149254.13-149282.4" + cell \main$22 \main + connect \br_op__cia \main_br_op__cia + connect \br_op__cia$2 \main_br_op__cia$13 + connect \br_op__fn_unit \main_br_op__fn_unit + connect \br_op__fn_unit$4 \main_br_op__fn_unit$15 + connect \br_op__imm_data__data \main_br_op__imm_data__data + connect \br_op__imm_data__data$6 \main_br_op__imm_data__data$17 + connect \br_op__imm_data__ok \main_br_op__imm_data__ok + connect \br_op__imm_data__ok$7 \main_br_op__imm_data__ok$18 + connect \br_op__insn \main_br_op__insn + connect \br_op__insn$5 \main_br_op__insn$16 + connect \br_op__insn_type \main_br_op__insn_type + connect \br_op__insn_type$3 \main_br_op__insn_type$14 + connect \br_op__is_32bit \main_br_op__is_32bit + connect \br_op__is_32bit$9 \main_br_op__is_32bit$20 + connect \br_op__lk \main_br_op__lk + connect \br_op__lk$8 \main_br_op__lk$19 + connect \cr_a \main_cr_a + connect \fast1 \main_fast1 + connect \fast1$10 \main_fast1$21 + connect \fast1_ok \main_fast1_ok + connect \fast2 \main_fast2 + connect \fast2$11 \main_fast2$22 + connect \fast2_ok \main_fast2_ok + connect \muxid \main_muxid + connect \muxid$1 \main_muxid$12 + connect \nia \main_nia + connect \nia_ok \main_nia_ok + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:149283.10-149286.4" + cell \n$21 \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:149287.10-149290.4" + cell \p$20 \p + connect \p_ready_o \p_ready_o + connect \p_valid_i \p_valid_i + end + attribute \src "libresoc.v:148578.7-148578.20" + process $proc$libresoc.v:148578$8229 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:148585.14-148585.51" + process $proc$libresoc.v:148585$8230 + assign { } { } + assign $0\br_op__cia$2[63:0]$8231 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \br_op__cia$2 $0\br_op__cia$2[63:0]$8231 + end + attribute \src "libresoc.v:148635.14-148635.42" + process $proc$libresoc.v:148635$8232 + assign { } { } + assign $0\br_op__fn_unit$4[11:0]$8233 12'000000000000 + sync always + sync init + update \br_op__fn_unit$4 $0\br_op__fn_unit$4[11:0]$8233 + end + attribute \src "libresoc.v:148644.14-148644.62" + process $proc$libresoc.v:148644$8234 + assign { } { } + assign $0\br_op__imm_data__data$6[63:0]$8235 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \br_op__imm_data__data$6 $0\br_op__imm_data__data$6[63:0]$8235 + end + attribute \src "libresoc.v:148653.7-148653.37" + process $proc$libresoc.v:148653$8236 + assign { } { } + assign $0\br_op__imm_data__ok$7[0:0]$8237 1'0 + sync always + sync init + update \br_op__imm_data__ok$7 $0\br_op__imm_data__ok$7[0:0]$8237 + end + attribute \src "libresoc.v:148662.14-148662.37" + process $proc$libresoc.v:148662$8238 + assign { } { } + assign $0\br_op__insn$5[31:0]$8239 0 + sync always + sync init + update \br_op__insn$5 $0\br_op__insn$5[31:0]$8239 + end + attribute \src "libresoc.v:148893.13-148893.41" + process $proc$libresoc.v:148893$8240 + assign { } { } + assign $0\br_op__insn_type$3[6:0]$8241 7'0000000 + sync always + sync init + update \br_op__insn_type$3 $0\br_op__insn_type$3[6:0]$8241 + end + attribute \src "libresoc.v:148902.7-148902.33" + process $proc$libresoc.v:148902$8242 + assign { } { } + assign $0\br_op__is_32bit$9[0:0]$8243 1'0 + sync always + sync init + update \br_op__is_32bit$9 $0\br_op__is_32bit$9[0:0]$8243 + end + attribute \src "libresoc.v:148911.7-148911.27" + process $proc$libresoc.v:148911$8244 + assign { } { } + assign $0\br_op__lk$8[0:0]$8245 1'0 + sync always + sync init + update \br_op__lk$8 $0\br_op__lk$8[0:0]$8245 + end + attribute \src "libresoc.v:148924.14-148924.47" + process $proc$libresoc.v:148924$8246 + assign { } { } + assign $0\fast1$10[63:0]$8247 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \fast1$10 $0\fast1$10[63:0]$8247 + end + attribute \src "libresoc.v:148931.7-148931.22" + process $proc$libresoc.v:148931$8248 + assign { } { } + assign $1\fast1_ok[0:0] 1'0 + sync always + sync init + update \fast1_ok $1\fast1_ok[0:0] + end + attribute \src "libresoc.v:148940.14-148940.47" + process $proc$libresoc.v:148940$8249 + assign { } { } + assign $0\fast2$11[63:0]$8250 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \fast2$11 $0\fast2$11[63:0]$8250 + end + attribute \src "libresoc.v:148947.7-148947.22" + process $proc$libresoc.v:148947$8251 + assign { } { } + assign $1\fast2_ok[0:0] 1'0 + sync always + sync init + update \fast2_ok $1\fast2_ok[0:0] + end + attribute \src "libresoc.v:149184.13-149184.29" + process $proc$libresoc.v:149184$8252 + assign { } { } + assign $0\muxid$1[1:0]$8253 2'00 + sync always + sync init + update \muxid$1 $0\muxid$1[1:0]$8253 + end + attribute \src "libresoc.v:149197.14-149197.40" + process $proc$libresoc.v:149197$8254 + assign { } { } + assign $1\nia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \nia $1\nia[63:0] + end + attribute \src "libresoc.v:149204.7-149204.20" + process $proc$libresoc.v:149204$8255 + assign { } { } + assign $1\nia_ok[0:0] 1'0 + sync always + sync init + update \nia_ok $1\nia_ok[0:0] + end + attribute \src "libresoc.v:149218.7-149218.20" + process $proc$libresoc.v:149218$8256 + assign { } { } + assign $1\r_busy[0:0] 1'0 + sync always + sync init + update \r_busy $1\r_busy[0:0] + end + attribute \src "libresoc.v:149222.3-149223.23" + process $proc$libresoc.v:149222$8158 + assign { } { } + assign $0\nia[63:0] \nia$next + sync posedge \coresync_clk + update \nia $0\nia[63:0] + end + attribute \src "libresoc.v:149224.3-149225.29" + process $proc$libresoc.v:149224$8159 + assign { } { } + assign $0\nia_ok[0:0] \nia_ok$next + sync posedge \coresync_clk + update \nia_ok $0\nia_ok[0:0] + end + attribute \src "libresoc.v:149226.3-149227.35" + process $proc$libresoc.v:149226$8160 + assign { } { } + assign $0\fast2$11[63:0]$8161 \fast2$11$next + sync posedge \coresync_clk + update \fast2$11 $0\fast2$11[63:0]$8161 + end + attribute \src "libresoc.v:149228.3-149229.33" + process $proc$libresoc.v:149228$8162 + assign { } { } + assign $0\fast2_ok[0:0] \fast2_ok$next + sync posedge \coresync_clk + update \fast2_ok $0\fast2_ok[0:0] + end + attribute \src "libresoc.v:149230.3-149231.35" + process $proc$libresoc.v:149230$8163 + assign { } { } + assign $0\fast1$10[63:0]$8164 \fast1$10$next + sync posedge \coresync_clk + update \fast1$10 $0\fast1$10[63:0]$8164 + end + attribute \src "libresoc.v:149232.3-149233.33" + process $proc$libresoc.v:149232$8165 + assign { } { } + assign $0\fast1_ok[0:0] \fast1_ok$next + sync posedge \coresync_clk + update \fast1_ok $0\fast1_ok[0:0] + end + attribute \src "libresoc.v:149234.3-149235.43" + process $proc$libresoc.v:149234$8166 + assign { } { } + assign $0\br_op__cia$2[63:0]$8167 \br_op__cia$2$next + sync posedge \coresync_clk + update \br_op__cia$2 $0\br_op__cia$2[63:0]$8167 + end + attribute \src "libresoc.v:149236.3-149237.55" + process $proc$libresoc.v:149236$8168 + assign { } { } + assign $0\br_op__insn_type$3[6:0]$8169 \br_op__insn_type$3$next + sync posedge \coresync_clk + update \br_op__insn_type$3 $0\br_op__insn_type$3[6:0]$8169 + end + attribute \src "libresoc.v:149238.3-149239.51" + process $proc$libresoc.v:149238$8170 + assign { } { } + assign $0\br_op__fn_unit$4[11:0]$8171 \br_op__fn_unit$4$next + sync posedge \coresync_clk + update \br_op__fn_unit$4 $0\br_op__fn_unit$4[11:0]$8171 + end + attribute \src "libresoc.v:149240.3-149241.45" + process $proc$libresoc.v:149240$8172 + assign { } { } + assign $0\br_op__insn$5[31:0]$8173 \br_op__insn$5$next + sync posedge \coresync_clk + update \br_op__insn$5 $0\br_op__insn$5[31:0]$8173 + end + attribute \src "libresoc.v:149242.3-149243.65" + process $proc$libresoc.v:149242$8174 + assign { } { } + assign $0\br_op__imm_data__data$6[63:0]$8175 \br_op__imm_data__data$6$next + sync posedge \coresync_clk + update \br_op__imm_data__data$6 $0\br_op__imm_data__data$6[63:0]$8175 + end + attribute \src "libresoc.v:149244.3-149245.61" + process $proc$libresoc.v:149244$8176 + assign { } { } + assign $0\br_op__imm_data__ok$7[0:0]$8177 \br_op__imm_data__ok$7$next + sync posedge \coresync_clk + update \br_op__imm_data__ok$7 $0\br_op__imm_data__ok$7[0:0]$8177 + end + attribute \src "libresoc.v:149246.3-149247.41" + process $proc$libresoc.v:149246$8178 + assign { } { } + assign $0\br_op__lk$8[0:0]$8179 \br_op__lk$8$next + sync posedge \coresync_clk + update \br_op__lk$8 $0\br_op__lk$8[0:0]$8179 + end + attribute \src "libresoc.v:149248.3-149249.53" + process $proc$libresoc.v:149248$8180 + assign { } { } + assign $0\br_op__is_32bit$9[0:0]$8181 \br_op__is_32bit$9$next + sync posedge \coresync_clk + update \br_op__is_32bit$9 $0\br_op__is_32bit$9[0:0]$8181 + end + attribute \src "libresoc.v:149250.3-149251.33" + process $proc$libresoc.v:149250$8182 + assign { } { } + assign $0\muxid$1[1:0]$8183 \muxid$1$next + sync posedge \coresync_clk + update \muxid$1 $0\muxid$1[1:0]$8183 + end + attribute \src "libresoc.v:149252.3-149253.29" + process $proc$libresoc.v:149252$8184 + assign { } { } + assign $0\r_busy[0:0] \r_busy$next + sync posedge \coresync_clk + update \r_busy $0\r_busy[0:0] + end + attribute \src "libresoc.v:149291.3-149308.6" + process $proc$libresoc.v:149291$8185 + assign { } { } + assign { } { } + assign { } { } + assign $0\r_busy$next[0:0]$8186 $2\r_busy$next[0:0]$8188 + attribute \src "libresoc.v:149292.5-149292.29" + switch \initial + attribute \src "libresoc.v:149292.9-149292.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\r_busy$next[0:0]$8187 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\r_busy$next[0:0]$8187 1'0 + case + assign $1\r_busy$next[0:0]$8187 \r_busy + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r_busy$next[0:0]$8188 1'0 + case + assign $2\r_busy$next[0:0]$8188 $1\r_busy$next[0:0]$8187 + end + sync always + update \r_busy$next $0\r_busy$next[0:0]$8186 + end + attribute \src "libresoc.v:149309.3-149321.6" + process $proc$libresoc.v:149309$8189 + assign { } { } + assign { } { } + assign $0\muxid$1$next[1:0]$8190 $1\muxid$1$next[1:0]$8191 + attribute \src "libresoc.v:149310.5-149310.29" + switch \initial + attribute \src "libresoc.v:149310.9-149310.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\muxid$1$next[1:0]$8191 \muxid$26 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\muxid$1$next[1:0]$8191 \muxid$26 + case + assign $1\muxid$1$next[1:0]$8191 \muxid$1 + end + sync always + update \muxid$1$next $0\muxid$1$next[1:0]$8190 + end + attribute \src "libresoc.v:149322.3-149349.6" + process $proc$libresoc.v:149322$8192 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\br_op__cia$2$next[63:0]$8193 $1\br_op__cia$2$next[63:0]$8201 + assign $0\br_op__fn_unit$4$next[11:0]$8194 $1\br_op__fn_unit$4$next[11:0]$8202 + assign { } { } + assign { } { } + assign $0\br_op__insn$5$next[31:0]$8197 $1\br_op__insn$5$next[31:0]$8205 + assign $0\br_op__insn_type$3$next[6:0]$8198 $1\br_op__insn_type$3$next[6:0]$8206 + assign $0\br_op__is_32bit$9$next[0:0]$8199 $1\br_op__is_32bit$9$next[0:0]$8207 + assign $0\br_op__lk$8$next[0:0]$8200 $1\br_op__lk$8$next[0:0]$8208 + assign $0\br_op__imm_data__data$6$next[63:0]$8195 $2\br_op__imm_data__data$6$next[63:0]$8209 + assign $0\br_op__imm_data__ok$7$next[0:0]$8196 $2\br_op__imm_data__ok$7$next[0:0]$8210 + attribute \src "libresoc.v:149323.5-149323.29" + switch \initial + attribute \src "libresoc.v:149323.9-149323.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\br_op__is_32bit$9$next[0:0]$8207 $1\br_op__lk$8$next[0:0]$8208 $1\br_op__imm_data__ok$7$next[0:0]$8204 $1\br_op__imm_data__data$6$next[63:0]$8203 $1\br_op__insn$5$next[31:0]$8205 $1\br_op__fn_unit$4$next[11:0]$8202 $1\br_op__insn_type$3$next[6:0]$8206 $1\br_op__cia$2$next[63:0]$8201 } { \br_op__is_32bit$34 \br_op__lk$33 \br_op__imm_data__ok$32 \br_op__imm_data__data$31 \br_op__insn$30 \br_op__fn_unit$29 \br_op__insn_type$28 \br_op__cia$27 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\br_op__is_32bit$9$next[0:0]$8207 $1\br_op__lk$8$next[0:0]$8208 $1\br_op__imm_data__ok$7$next[0:0]$8204 $1\br_op__imm_data__data$6$next[63:0]$8203 $1\br_op__insn$5$next[31:0]$8205 $1\br_op__fn_unit$4$next[11:0]$8202 $1\br_op__insn_type$3$next[6:0]$8206 $1\br_op__cia$2$next[63:0]$8201 } { \br_op__is_32bit$34 \br_op__lk$33 \br_op__imm_data__ok$32 \br_op__imm_data__data$31 \br_op__insn$30 \br_op__fn_unit$29 \br_op__insn_type$28 \br_op__cia$27 } + case + assign $1\br_op__cia$2$next[63:0]$8201 \br_op__cia$2 + assign $1\br_op__fn_unit$4$next[11:0]$8202 \br_op__fn_unit$4 + assign $1\br_op__imm_data__data$6$next[63:0]$8203 \br_op__imm_data__data$6 + assign $1\br_op__imm_data__ok$7$next[0:0]$8204 \br_op__imm_data__ok$7 + assign $1\br_op__insn$5$next[31:0]$8205 \br_op__insn$5 + assign $1\br_op__insn_type$3$next[6:0]$8206 \br_op__insn_type$3 + assign $1\br_op__is_32bit$9$next[0:0]$8207 \br_op__is_32bit$9 + assign $1\br_op__lk$8$next[0:0]$8208 \br_op__lk$8 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $2\br_op__imm_data__data$6$next[63:0]$8209 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\br_op__imm_data__ok$7$next[0:0]$8210 1'0 + case + assign $2\br_op__imm_data__data$6$next[63:0]$8209 $1\br_op__imm_data__data$6$next[63:0]$8203 + assign $2\br_op__imm_data__ok$7$next[0:0]$8210 $1\br_op__imm_data__ok$7$next[0:0]$8204 + end + sync always + update \br_op__cia$2$next $0\br_op__cia$2$next[63:0]$8193 + update \br_op__fn_unit$4$next $0\br_op__fn_unit$4$next[11:0]$8194 + update \br_op__imm_data__data$6$next $0\br_op__imm_data__data$6$next[63:0]$8195 + update \br_op__imm_data__ok$7$next $0\br_op__imm_data__ok$7$next[0:0]$8196 + update \br_op__insn$5$next $0\br_op__insn$5$next[31:0]$8197 + update \br_op__insn_type$3$next $0\br_op__insn_type$3$next[6:0]$8198 + update \br_op__is_32bit$9$next $0\br_op__is_32bit$9$next[0:0]$8199 + update \br_op__lk$8$next $0\br_op__lk$8$next[0:0]$8200 + end + attribute \src "libresoc.v:149350.3-149368.6" + process $proc$libresoc.v:149350$8211 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fast1$10$next[63:0]$8212 $1\fast1$10$next[63:0]$8214 + assign { } { } + assign $0\fast1_ok$next[0:0]$8213 $2\fast1_ok$next[0:0]$8216 + attribute \src "libresoc.v:149351.5-149351.29" + switch \initial + attribute \src "libresoc.v:149351.9-149351.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\fast1_ok$next[0:0]$8215 $1\fast1$10$next[63:0]$8214 } { \fast1_ok$36 \fast1$35 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\fast1_ok$next[0:0]$8215 $1\fast1$10$next[63:0]$8214 } { \fast1_ok$36 \fast1$35 } + case + assign $1\fast1$10$next[63:0]$8214 \fast1$10 + assign $1\fast1_ok$next[0:0]$8215 \fast1_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\fast1_ok$next[0:0]$8216 1'0 + case + assign $2\fast1_ok$next[0:0]$8216 $1\fast1_ok$next[0:0]$8215 + end + sync always + update \fast1$10$next $0\fast1$10$next[63:0]$8212 + update \fast1_ok$next $0\fast1_ok$next[0:0]$8213 + end + attribute \src "libresoc.v:149369.3-149387.6" + process $proc$libresoc.v:149369$8217 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fast2$11$next[63:0]$8218 $1\fast2$11$next[63:0]$8220 + assign { } { } + assign $0\fast2_ok$next[0:0]$8219 $2\fast2_ok$next[0:0]$8222 + attribute \src "libresoc.v:149370.5-149370.29" + switch \initial + attribute \src "libresoc.v:149370.9-149370.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\fast2_ok$next[0:0]$8221 $1\fast2$11$next[63:0]$8220 } { \fast2_ok$38 \fast2$37 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\fast2_ok$next[0:0]$8221 $1\fast2$11$next[63:0]$8220 } { \fast2_ok$38 \fast2$37 } + case + assign $1\fast2$11$next[63:0]$8220 \fast2$11 + assign $1\fast2_ok$next[0:0]$8221 \fast2_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\fast2_ok$next[0:0]$8222 1'0 + case + assign $2\fast2_ok$next[0:0]$8222 $1\fast2_ok$next[0:0]$8221 + end + sync always + update \fast2$11$next $0\fast2$11$next[63:0]$8218 + update \fast2_ok$next $0\fast2_ok$next[0:0]$8219 + end + attribute \src "libresoc.v:149388.3-149406.6" + process $proc$libresoc.v:149388$8223 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\nia$next[63:0]$8224 $1\nia$next[63:0]$8226 + assign { } { } + assign $0\nia_ok$next[0:0]$8225 $2\nia_ok$next[0:0]$8228 + attribute \src "libresoc.v:149389.5-149389.29" + switch \initial + attribute \src "libresoc.v:149389.9-149389.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\nia_ok$next[0:0]$8227 $1\nia$next[63:0]$8226 } { \nia_ok$40 \nia$39 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\nia_ok$next[0:0]$8227 $1\nia$next[63:0]$8226 } { \nia_ok$40 \nia$39 } + case + assign $1\nia$next[63:0]$8226 \nia + assign $1\nia_ok$next[0:0]$8227 \nia_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\nia_ok$next[0:0]$8228 1'0 + case + assign $2\nia_ok$next[0:0]$8228 $1\nia_ok$next[0:0]$8227 + end + sync always + update \nia$next $0\nia$next[63:0]$8224 + update \nia_ok$next $0\nia_ok$next[0:0]$8225 + end + connect \$24 $and$libresoc.v:149221$8157_Y + connect \p_ready_o \n_i_rdy_data + connect \n_valid_o \r_busy + connect { \nia_ok$40 \nia$39 } { \main_nia_ok \main_nia } + connect { \fast2_ok$38 \fast2$37 } { \main_fast2_ok \main_fast2$22 } + connect { \fast1_ok$36 \fast1$35 } { \main_fast1_ok \main_fast1$21 } + connect { \br_op__is_32bit$34 \br_op__lk$33 \br_op__imm_data__ok$32 \br_op__imm_data__data$31 \br_op__insn$30 \br_op__fn_unit$29 \br_op__insn_type$28 \br_op__cia$27 } { \main_br_op__is_32bit$20 \main_br_op__lk$19 \main_br_op__imm_data__ok$18 \main_br_op__imm_data__data$17 \main_br_op__insn$16 \main_br_op__fn_unit$15 \main_br_op__insn_type$14 \main_br_op__cia$13 } + connect \muxid$26 \main_muxid$12 + connect \p_valid_i_p_ready_o \$24 + connect \n_i_rdy_data \n_ready_i + connect \p_valid_i$23 \p_valid_i + connect \main_cr_a \cr_a + connect \main_fast2 \fast2 + connect \main_fast1 \fast1 + connect { \main_br_op__is_32bit \main_br_op__lk \main_br_op__imm_data__ok \main_br_op__imm_data__data \main_br_op__insn \main_br_op__fn_unit \main_br_op__insn_type \main_br_op__cia } { \br_op__is_32bit \br_op__lk \br_op__imm_data__ok \br_op__imm_data__data \br_op__insn \br_op__fn_unit \br_op__insn_type \br_op__cia } + connect \main_muxid \muxid +end +attribute \src "libresoc.v:149426.1-150357.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.alu_trap0.pipe" +attribute \generator "nMigen" +module \pipe$32 + attribute \src "libresoc.v:150263.3-150281.6" + wire width 64 $0\fast1$10$next[63:0]$8320 + attribute \src "libresoc.v:150123.3-150124.35" + wire width 64 $0\fast1$10[63:0]$8266 + attribute \src "libresoc.v:149438.14-149438.47" + wire width 64 $0\fast1$10[63:0]$8345 + attribute \src "libresoc.v:150263.3-150281.6" + wire $0\fast1_ok$next[0:0]$8321 + attribute \src "libresoc.v:150125.3-150126.33" + wire $0\fast1_ok[0:0] + attribute \src "libresoc.v:150282.3-150300.6" + wire width 64 $0\fast2$11$next[63:0]$8326 + attribute \src "libresoc.v:150119.3-150120.35" + wire width 64 $0\fast2$11[63:0]$8263 + attribute \src "libresoc.v:149454.14-149454.47" + wire width 64 $0\fast2$11[63:0]$8348 + attribute \src "libresoc.v:150282.3-150300.6" + wire $0\fast2_ok$next[0:0]$8327 + attribute \src "libresoc.v:150121.3-150122.33" + wire $0\fast2_ok[0:0] + attribute \src "libresoc.v:149427.7-149427.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:150320.3-150338.6" + wire width 64 $0\msr$next[63:0]$8338 + attribute \src "libresoc.v:150111.3-150112.23" + wire width 64 $0\msr[63:0] + attribute \src "libresoc.v:150320.3-150338.6" + wire $0\msr_ok$next[0:0]$8339 + attribute \src "libresoc.v:150113.3-150114.29" + wire $0\msr_ok[0:0] + attribute \src "libresoc.v:150211.3-150223.6" + wire width 2 $0\muxid$1$next[1:0]$8294 + attribute \src "libresoc.v:150147.3-150148.33" + wire width 2 $0\muxid$1[1:0]$8287 + attribute \src "libresoc.v:149722.13-149722.29" + wire width 2 $0\muxid$1[1:0]$8353 + attribute \src "libresoc.v:150301.3-150319.6" + wire width 64 $0\nia$next[63:0]$8332 + attribute \src "libresoc.v:150115.3-150116.23" + wire width 64 $0\nia[63:0] + attribute \src "libresoc.v:150301.3-150319.6" + wire $0\nia_ok$next[0:0]$8333 + attribute \src "libresoc.v:150117.3-150118.29" + wire $0\nia_ok[0:0] + attribute \src "libresoc.v:150244.3-150262.6" + wire width 64 $0\o$next[63:0]$8314 + attribute \src "libresoc.v:150127.3-150128.19" + wire width 64 $0\o[63:0] + attribute \src "libresoc.v:150244.3-150262.6" + wire $0\o_ok$next[0:0]$8315 + attribute \src "libresoc.v:150129.3-150130.25" + wire $0\o_ok[0:0] + attribute \src "libresoc.v:150193.3-150210.6" + wire $0\r_busy$next[0:0]$8290 + attribute \src "libresoc.v:150149.3-150150.29" + wire $0\r_busy[0:0] + attribute \src "libresoc.v:150224.3-150243.6" + wire width 64 $0\trap_op__cia$6$next[63:0]$8297 + attribute \src "libresoc.v:150139.3-150140.47" + wire width 64 $0\trap_op__cia$6[63:0]$8279 + attribute \src "libresoc.v:149783.14-149783.53" + wire width 64 $0\trap_op__cia$6[63:0]$8360 + attribute \src "libresoc.v:150224.3-150243.6" + wire width 12 $0\trap_op__fn_unit$3$next[11:0]$8298 + attribute \src "libresoc.v:150133.3-150134.55" + wire width 12 $0\trap_op__fn_unit$3[11:0]$8273 + attribute \src "libresoc.v:149831.14-149831.44" + wire width 12 $0\trap_op__fn_unit$3[11:0]$8362 + attribute \src "libresoc.v:150224.3-150243.6" + wire width 32 $0\trap_op__insn$4$next[31:0]$8299 + attribute \src "libresoc.v:150135.3-150136.49" + wire width 32 $0\trap_op__insn$4[31:0]$8275 + attribute \src "libresoc.v:149840.14-149840.39" + wire width 32 $0\trap_op__insn$4[31:0]$8364 + attribute \src "libresoc.v:150224.3-150243.6" + wire width 7 $0\trap_op__insn_type$2$next[6:0]$8300 + attribute \src "libresoc.v:150131.3-150132.59" + wire width 7 $0\trap_op__insn_type$2[6:0]$8271 + attribute \src "libresoc.v:149995.13-149995.43" + wire width 7 $0\trap_op__insn_type$2[6:0]$8366 + attribute \src "libresoc.v:150224.3-150243.6" + wire $0\trap_op__is_32bit$7$next[0:0]$8301 + attribute \src "libresoc.v:150141.3-150142.57" + wire $0\trap_op__is_32bit$7[0:0]$8281 + attribute \src "libresoc.v:150080.7-150080.35" + wire $0\trap_op__is_32bit$7[0:0]$8368 + attribute \src "libresoc.v:150224.3-150243.6" + wire width 64 $0\trap_op__msr$5$next[63:0]$8302 + attribute \src "libresoc.v:150137.3-150138.47" + wire width 64 $0\trap_op__msr$5[63:0]$8277 + attribute \src "libresoc.v:150089.14-150089.53" + wire width 64 $0\trap_op__msr$5[63:0]$8370 + attribute \src "libresoc.v:150224.3-150243.6" + wire width 13 $0\trap_op__trapaddr$9$next[12:0]$8303 + attribute \src "libresoc.v:150145.3-150146.57" + wire width 13 $0\trap_op__trapaddr$9[12:0]$8285 + attribute \src "libresoc.v:150098.14-150098.46" + wire width 13 $0\trap_op__trapaddr$9[12:0]$8372 + attribute \src "libresoc.v:150224.3-150243.6" + wire width 7 $0\trap_op__traptype$8$next[6:0]$8304 + attribute \src "libresoc.v:150143.3-150144.57" + wire width 7 $0\trap_op__traptype$8[6:0]$8283 + attribute \src "libresoc.v:150107.13-150107.42" + wire width 7 $0\trap_op__traptype$8[6:0]$8374 + attribute \src "libresoc.v:150263.3-150281.6" + wire width 64 $1\fast1$10$next[63:0]$8322 + attribute \src "libresoc.v:150263.3-150281.6" + wire $1\fast1_ok$next[0:0]$8323 + attribute \src "libresoc.v:149445.7-149445.22" + wire $1\fast1_ok[0:0] + attribute \src "libresoc.v:150282.3-150300.6" + wire width 64 $1\fast2$11$next[63:0]$8328 + attribute \src "libresoc.v:150282.3-150300.6" + wire $1\fast2_ok$next[0:0]$8329 + attribute \src "libresoc.v:149461.7-149461.22" + wire $1\fast2_ok[0:0] + attribute \src "libresoc.v:150320.3-150338.6" + wire width 64 $1\msr$next[63:0]$8340 + attribute \src "libresoc.v:149706.14-149706.40" + wire width 64 $1\msr[63:0] + attribute \src "libresoc.v:150320.3-150338.6" + wire $1\msr_ok$next[0:0]$8341 + attribute \src "libresoc.v:149713.7-149713.20" + wire $1\msr_ok[0:0] + attribute \src "libresoc.v:150211.3-150223.6" + wire width 2 $1\muxid$1$next[1:0]$8295 + attribute \src "libresoc.v:150301.3-150319.6" + wire width 64 $1\nia$next[63:0]$8334 + attribute \src "libresoc.v:149735.14-149735.40" + wire width 64 $1\nia[63:0] + attribute \src "libresoc.v:150301.3-150319.6" + wire $1\nia_ok$next[0:0]$8335 + attribute \src "libresoc.v:149742.7-149742.20" + wire $1\nia_ok[0:0] + attribute \src "libresoc.v:150244.3-150262.6" + wire width 64 $1\o$next[63:0]$8316 + attribute \src "libresoc.v:149749.14-149749.38" + wire width 64 $1\o[63:0] + attribute \src "libresoc.v:150244.3-150262.6" + wire $1\o_ok$next[0:0]$8317 + attribute \src "libresoc.v:149756.7-149756.18" + wire $1\o_ok[0:0] + attribute \src "libresoc.v:150193.3-150210.6" + wire $1\r_busy$next[0:0]$8291 + attribute \src "libresoc.v:149770.7-149770.20" + wire $1\r_busy[0:0] + attribute \src "libresoc.v:150224.3-150243.6" + wire width 64 $1\trap_op__cia$6$next[63:0]$8305 + attribute \src "libresoc.v:150224.3-150243.6" + wire width 12 $1\trap_op__fn_unit$3$next[11:0]$8306 + attribute \src "libresoc.v:150224.3-150243.6" + wire width 32 $1\trap_op__insn$4$next[31:0]$8307 + attribute \src "libresoc.v:150224.3-150243.6" + wire width 7 $1\trap_op__insn_type$2$next[6:0]$8308 + attribute \src "libresoc.v:150224.3-150243.6" + wire $1\trap_op__is_32bit$7$next[0:0]$8309 + attribute \src "libresoc.v:150224.3-150243.6" + wire width 64 $1\trap_op__msr$5$next[63:0]$8310 + attribute \src "libresoc.v:150224.3-150243.6" + wire width 13 $1\trap_op__trapaddr$9$next[12:0]$8311 + attribute \src "libresoc.v:150224.3-150243.6" + wire width 7 $1\trap_op__traptype$8$next[6:0]$8312 + attribute \src "libresoc.v:150263.3-150281.6" + wire $2\fast1_ok$next[0:0]$8324 + attribute \src "libresoc.v:150282.3-150300.6" + wire $2\fast2_ok$next[0:0]$8330 + attribute \src "libresoc.v:150320.3-150338.6" + wire $2\msr_ok$next[0:0]$8342 + attribute \src "libresoc.v:150301.3-150319.6" + wire $2\nia_ok$next[0:0]$8336 + attribute \src "libresoc.v:150244.3-150262.6" + wire $2\o_ok$next[0:0]$8318 + attribute \src "libresoc.v:150193.3-150210.6" + wire $2\r_busy$next[0:0]$8292 + attribute \src "libresoc.v:150110.18-150110.118" + wire $and$libresoc.v:150110$8257_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 38 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 15 \fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 30 \fast1$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \fast1$10$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \fast1$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 31 \fast1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \fast1_ok$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \fast1_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 16 \fast2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 32 \fast2$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \fast2$11$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \fast2$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 33 \fast2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \fast2_ok$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \fast2_ok$next + attribute \src "libresoc.v:149427.7-149427.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \main_fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \main_fast1$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \main_fast1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \main_fast2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \main_fast2$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \main_fast2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \main_msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \main_msr_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \main_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \main_muxid$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \main_nia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \main_nia_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \main_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \main_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \main_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \main_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \main_trap_op__cia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \main_trap_op__cia$17 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \main_trap_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \main_trap_op__fn_unit$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \main_trap_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \main_trap_op__insn$15 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \main_trap_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \main_trap_op__insn_type$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_trap_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_trap_op__is_32bit$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \main_trap_op__msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \main_trap_op__msr$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \main_trap_op__trapaddr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \main_trap_op__trapaddr$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \main_trap_op__traptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \main_trap_op__traptype$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 36 \msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \msr$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \msr$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 37 \msr_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \msr_ok$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \msr_ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 4 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 19 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$1$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$26 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" + wire \n_i_rdy_data + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire input 18 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire output 17 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 34 \nia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \nia$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \nia$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 35 \nia_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \nia_ok$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \nia_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 28 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \o$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \o$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 29 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \o_ok$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \o_ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire output 3 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" + wire \p_valid_i$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire \r_busy$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 13 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 14 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 9 \trap_op__cia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \trap_op__cia$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 24 \trap_op__cia$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \trap_op__cia$6$next + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 6 \trap_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \trap_op__fn_unit$28 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 output 21 \trap_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \trap_op__fn_unit$3$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 7 \trap_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \trap_op__insn$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 22 \trap_op__insn$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \trap_op__insn$4$next + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 5 \trap_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 20 \trap_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \trap_op__insn_type$2$next + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \trap_op__insn_type$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \trap_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \trap_op__is_32bit$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 25 \trap_op__is_32bit$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \trap_op__is_32bit$7$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 8 \trap_op__msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \trap_op__msr$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 23 \trap_op__msr$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \trap_op__msr$5$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 input 12 \trap_op__trapaddr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \trap_op__trapaddr$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 output 27 \trap_op__trapaddr$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \trap_op__trapaddr$9$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 11 \trap_op__traptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \trap_op__traptype$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 26 \trap_op__traptype$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \trap_op__traptype$8$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + cell $and $and$libresoc.v:150110$8257 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i$23 + connect \B \p_ready_o + connect \Y $and$libresoc.v:150110$8257_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:150151.13-150184.4" + cell \main$35 \main + connect \fast1 \main_fast1 + connect \fast1$10 \main_fast1$21 + connect \fast1_ok \main_fast1_ok + connect \fast2 \main_fast2 + connect \fast2$11 \main_fast2$22 + connect \fast2_ok \main_fast2_ok + connect \msr \main_msr + connect \msr_ok \main_msr_ok + connect \muxid \main_muxid + connect \muxid$1 \main_muxid$12 + connect \nia \main_nia + connect \nia_ok \main_nia_ok + connect \o \main_o + connect \o_ok \main_o_ok + connect \ra \main_ra + connect \rb \main_rb + connect \trap_op__cia \main_trap_op__cia + connect \trap_op__cia$6 \main_trap_op__cia$17 + connect \trap_op__fn_unit \main_trap_op__fn_unit + connect \trap_op__fn_unit$3 \main_trap_op__fn_unit$14 + connect \trap_op__insn \main_trap_op__insn + connect \trap_op__insn$4 \main_trap_op__insn$15 + connect \trap_op__insn_type \main_trap_op__insn_type + connect \trap_op__insn_type$2 \main_trap_op__insn_type$13 + connect \trap_op__is_32bit \main_trap_op__is_32bit + connect \trap_op__is_32bit$7 \main_trap_op__is_32bit$18 + connect \trap_op__msr \main_trap_op__msr + connect \trap_op__msr$5 \main_trap_op__msr$16 + connect \trap_op__trapaddr \main_trap_op__trapaddr + connect \trap_op__trapaddr$9 \main_trap_op__trapaddr$20 + connect \trap_op__traptype \main_trap_op__traptype + connect \trap_op__traptype$8 \main_trap_op__traptype$19 + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:150185.10-150188.4" + cell \n$34 \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:150189.10-150192.4" + cell \p$33 \p + connect \p_ready_o \p_ready_o + connect \p_valid_i \p_valid_i + end + attribute \src "libresoc.v:149427.7-149427.20" + process $proc$libresoc.v:149427$8343 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:149438.14-149438.47" + process $proc$libresoc.v:149438$8344 + assign { } { } + assign $0\fast1$10[63:0]$8345 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \fast1$10 $0\fast1$10[63:0]$8345 + end + attribute \src "libresoc.v:149445.7-149445.22" + process $proc$libresoc.v:149445$8346 + assign { } { } + assign $1\fast1_ok[0:0] 1'0 + sync always + sync init + update \fast1_ok $1\fast1_ok[0:0] + end + attribute \src "libresoc.v:149454.14-149454.47" + process $proc$libresoc.v:149454$8347 + assign { } { } + assign $0\fast2$11[63:0]$8348 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \fast2$11 $0\fast2$11[63:0]$8348 + end + attribute \src "libresoc.v:149461.7-149461.22" + process $proc$libresoc.v:149461$8349 + assign { } { } + assign $1\fast2_ok[0:0] 1'0 + sync always + sync init + update \fast2_ok $1\fast2_ok[0:0] + end + attribute \src "libresoc.v:149706.14-149706.40" + process $proc$libresoc.v:149706$8350 + assign { } { } + assign $1\msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \msr $1\msr[63:0] + end + attribute \src "libresoc.v:149713.7-149713.20" + process $proc$libresoc.v:149713$8351 + assign { } { } + assign $1\msr_ok[0:0] 1'0 + sync always + sync init + update \msr_ok $1\msr_ok[0:0] + end + attribute \src "libresoc.v:149722.13-149722.29" + process $proc$libresoc.v:149722$8352 + assign { } { } + assign $0\muxid$1[1:0]$8353 2'00 + sync always + sync init + update \muxid$1 $0\muxid$1[1:0]$8353 + end + attribute \src "libresoc.v:149735.14-149735.40" + process $proc$libresoc.v:149735$8354 + assign { } { } + assign $1\nia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \nia $1\nia[63:0] + end + attribute \src "libresoc.v:149742.7-149742.20" + process $proc$libresoc.v:149742$8355 + assign { } { } + assign $1\nia_ok[0:0] 1'0 + sync always + sync init + update \nia_ok $1\nia_ok[0:0] + end + attribute \src "libresoc.v:149749.14-149749.38" + process $proc$libresoc.v:149749$8356 + assign { } { } + assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \o $1\o[63:0] + end + attribute \src "libresoc.v:149756.7-149756.18" + process $proc$libresoc.v:149756$8357 + assign { } { } + assign $1\o_ok[0:0] 1'0 + sync always + sync init + update \o_ok $1\o_ok[0:0] + end + attribute \src "libresoc.v:149770.7-149770.20" + process $proc$libresoc.v:149770$8358 + assign { } { } + assign $1\r_busy[0:0] 1'0 + sync always + sync init + update \r_busy $1\r_busy[0:0] + end + attribute \src "libresoc.v:149783.14-149783.53" + process $proc$libresoc.v:149783$8359 + assign { } { } + assign $0\trap_op__cia$6[63:0]$8360 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \trap_op__cia$6 $0\trap_op__cia$6[63:0]$8360 + end + attribute \src "libresoc.v:149831.14-149831.44" + process $proc$libresoc.v:149831$8361 + assign { } { } + assign $0\trap_op__fn_unit$3[11:0]$8362 12'000000000000 + sync always + sync init + update \trap_op__fn_unit$3 $0\trap_op__fn_unit$3[11:0]$8362 + end + attribute \src "libresoc.v:149840.14-149840.39" + process $proc$libresoc.v:149840$8363 + assign { } { } + assign $0\trap_op__insn$4[31:0]$8364 0 + sync always + sync init + update \trap_op__insn$4 $0\trap_op__insn$4[31:0]$8364 + end + attribute \src "libresoc.v:149995.13-149995.43" + process $proc$libresoc.v:149995$8365 + assign { } { } + assign $0\trap_op__insn_type$2[6:0]$8366 7'0000000 + sync always + sync init + update \trap_op__insn_type$2 $0\trap_op__insn_type$2[6:0]$8366 + end + attribute \src "libresoc.v:150080.7-150080.35" + process $proc$libresoc.v:150080$8367 + assign { } { } + assign $0\trap_op__is_32bit$7[0:0]$8368 1'0 + sync always + sync init + update \trap_op__is_32bit$7 $0\trap_op__is_32bit$7[0:0]$8368 + end + attribute \src "libresoc.v:150089.14-150089.53" + process $proc$libresoc.v:150089$8369 + assign { } { } + assign $0\trap_op__msr$5[63:0]$8370 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \trap_op__msr$5 $0\trap_op__msr$5[63:0]$8370 + end + attribute \src "libresoc.v:150098.14-150098.46" + process $proc$libresoc.v:150098$8371 + assign { } { } + assign $0\trap_op__trapaddr$9[12:0]$8372 13'0000000000000 + sync always + sync init + update \trap_op__trapaddr$9 $0\trap_op__trapaddr$9[12:0]$8372 + end + attribute \src "libresoc.v:150107.13-150107.42" + process $proc$libresoc.v:150107$8373 + assign { } { } + assign $0\trap_op__traptype$8[6:0]$8374 7'0000000 + sync always + sync init + update \trap_op__traptype$8 $0\trap_op__traptype$8[6:0]$8374 + end + attribute \src "libresoc.v:150111.3-150112.23" + process $proc$libresoc.v:150111$8258 + assign { } { } + assign $0\msr[63:0] \msr$next + sync posedge \coresync_clk + update \msr $0\msr[63:0] + end + attribute \src "libresoc.v:150113.3-150114.29" + process $proc$libresoc.v:150113$8259 + assign { } { } + assign $0\msr_ok[0:0] \msr_ok$next + sync posedge \coresync_clk + update \msr_ok $0\msr_ok[0:0] + end + attribute \src "libresoc.v:150115.3-150116.23" + process $proc$libresoc.v:150115$8260 + assign { } { } + assign $0\nia[63:0] \nia$next + sync posedge \coresync_clk + update \nia $0\nia[63:0] + end + attribute \src "libresoc.v:150117.3-150118.29" + process $proc$libresoc.v:150117$8261 + assign { } { } + assign $0\nia_ok[0:0] \nia_ok$next + sync posedge \coresync_clk + update \nia_ok $0\nia_ok[0:0] + end + attribute \src "libresoc.v:150119.3-150120.35" + process $proc$libresoc.v:150119$8262 + assign { } { } + assign $0\fast2$11[63:0]$8263 \fast2$11$next + sync posedge \coresync_clk + update \fast2$11 $0\fast2$11[63:0]$8263 + end + attribute \src "libresoc.v:150121.3-150122.33" + process $proc$libresoc.v:150121$8264 + assign { } { } + assign $0\fast2_ok[0:0] \fast2_ok$next + sync posedge \coresync_clk + update \fast2_ok $0\fast2_ok[0:0] + end + attribute \src "libresoc.v:150123.3-150124.35" + process $proc$libresoc.v:150123$8265 + assign { } { } + assign $0\fast1$10[63:0]$8266 \fast1$10$next + sync posedge \coresync_clk + update \fast1$10 $0\fast1$10[63:0]$8266 + end + attribute \src "libresoc.v:150125.3-150126.33" + process $proc$libresoc.v:150125$8267 + assign { } { } + assign $0\fast1_ok[0:0] \fast1_ok$next + sync posedge \coresync_clk + update \fast1_ok $0\fast1_ok[0:0] + end + attribute \src "libresoc.v:150127.3-150128.19" + process $proc$libresoc.v:150127$8268 + assign { } { } + assign $0\o[63:0] \o$next + sync posedge \coresync_clk + update \o $0\o[63:0] + end + attribute \src "libresoc.v:150129.3-150130.25" + process $proc$libresoc.v:150129$8269 + assign { } { } + assign $0\o_ok[0:0] \o_ok$next + sync posedge \coresync_clk + update \o_ok $0\o_ok[0:0] + end + attribute \src "libresoc.v:150131.3-150132.59" + process $proc$libresoc.v:150131$8270 + assign { } { } + assign $0\trap_op__insn_type$2[6:0]$8271 \trap_op__insn_type$2$next + sync posedge \coresync_clk + update \trap_op__insn_type$2 $0\trap_op__insn_type$2[6:0]$8271 + end + attribute \src "libresoc.v:150133.3-150134.55" + process $proc$libresoc.v:150133$8272 + assign { } { } + assign $0\trap_op__fn_unit$3[11:0]$8273 \trap_op__fn_unit$3$next + sync posedge \coresync_clk + update \trap_op__fn_unit$3 $0\trap_op__fn_unit$3[11:0]$8273 + end + attribute \src "libresoc.v:150135.3-150136.49" + process $proc$libresoc.v:150135$8274 + assign { } { } + assign $0\trap_op__insn$4[31:0]$8275 \trap_op__insn$4$next + sync posedge \coresync_clk + update \trap_op__insn$4 $0\trap_op__insn$4[31:0]$8275 + end + attribute \src "libresoc.v:150137.3-150138.47" + process $proc$libresoc.v:150137$8276 + assign { } { } + assign $0\trap_op__msr$5[63:0]$8277 \trap_op__msr$5$next + sync posedge \coresync_clk + update \trap_op__msr$5 $0\trap_op__msr$5[63:0]$8277 + end + attribute \src "libresoc.v:150139.3-150140.47" + process $proc$libresoc.v:150139$8278 + assign { } { } + assign $0\trap_op__cia$6[63:0]$8279 \trap_op__cia$6$next + sync posedge \coresync_clk + update \trap_op__cia$6 $0\trap_op__cia$6[63:0]$8279 + end + attribute \src "libresoc.v:150141.3-150142.57" + process $proc$libresoc.v:150141$8280 + assign { } { } + assign $0\trap_op__is_32bit$7[0:0]$8281 \trap_op__is_32bit$7$next + sync posedge \coresync_clk + update \trap_op__is_32bit$7 $0\trap_op__is_32bit$7[0:0]$8281 + end + attribute \src "libresoc.v:150143.3-150144.57" + process $proc$libresoc.v:150143$8282 + assign { } { } + assign $0\trap_op__traptype$8[6:0]$8283 \trap_op__traptype$8$next + sync posedge \coresync_clk + update \trap_op__traptype$8 $0\trap_op__traptype$8[6:0]$8283 + end + attribute \src "libresoc.v:150145.3-150146.57" + process $proc$libresoc.v:150145$8284 + assign { } { } + assign $0\trap_op__trapaddr$9[12:0]$8285 \trap_op__trapaddr$9$next + sync posedge \coresync_clk + update \trap_op__trapaddr$9 $0\trap_op__trapaddr$9[12:0]$8285 + end + attribute \src "libresoc.v:150147.3-150148.33" + process $proc$libresoc.v:150147$8286 + assign { } { } + assign $0\muxid$1[1:0]$8287 \muxid$1$next + sync posedge \coresync_clk + update \muxid$1 $0\muxid$1[1:0]$8287 + end + attribute \src "libresoc.v:150149.3-150150.29" + process $proc$libresoc.v:150149$8288 + assign { } { } + assign $0\r_busy[0:0] \r_busy$next + sync posedge \coresync_clk + update \r_busy $0\r_busy[0:0] + end + attribute \src "libresoc.v:150193.3-150210.6" + process $proc$libresoc.v:150193$8289 + assign { } { } + assign { } { } + assign { } { } + assign $0\r_busy$next[0:0]$8290 $2\r_busy$next[0:0]$8292 + attribute \src "libresoc.v:150194.5-150194.29" + switch \initial + attribute \src "libresoc.v:150194.9-150194.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\r_busy$next[0:0]$8291 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\r_busy$next[0:0]$8291 1'0 + case + assign $1\r_busy$next[0:0]$8291 \r_busy + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r_busy$next[0:0]$8292 1'0 + case + assign $2\r_busy$next[0:0]$8292 $1\r_busy$next[0:0]$8291 + end + sync always + update \r_busy$next $0\r_busy$next[0:0]$8290 + end + attribute \src "libresoc.v:150211.3-150223.6" + process $proc$libresoc.v:150211$8293 + assign { } { } + assign { } { } + assign $0\muxid$1$next[1:0]$8294 $1\muxid$1$next[1:0]$8295 + attribute \src "libresoc.v:150212.5-150212.29" + switch \initial + attribute \src "libresoc.v:150212.9-150212.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\muxid$1$next[1:0]$8295 \muxid$26 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\muxid$1$next[1:0]$8295 \muxid$26 + case + assign $1\muxid$1$next[1:0]$8295 \muxid$1 + end + sync always + update \muxid$1$next $0\muxid$1$next[1:0]$8294 + end + attribute \src "libresoc.v:150224.3-150243.6" + process $proc$libresoc.v:150224$8296 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\trap_op__cia$6$next[63:0]$8297 $1\trap_op__cia$6$next[63:0]$8305 + assign $0\trap_op__fn_unit$3$next[11:0]$8298 $1\trap_op__fn_unit$3$next[11:0]$8306 + assign $0\trap_op__insn$4$next[31:0]$8299 $1\trap_op__insn$4$next[31:0]$8307 + assign $0\trap_op__insn_type$2$next[6:0]$8300 $1\trap_op__insn_type$2$next[6:0]$8308 + assign $0\trap_op__is_32bit$7$next[0:0]$8301 $1\trap_op__is_32bit$7$next[0:0]$8309 + assign $0\trap_op__msr$5$next[63:0]$8302 $1\trap_op__msr$5$next[63:0]$8310 + assign $0\trap_op__trapaddr$9$next[12:0]$8303 $1\trap_op__trapaddr$9$next[12:0]$8311 + assign $0\trap_op__traptype$8$next[6:0]$8304 $1\trap_op__traptype$8$next[6:0]$8312 + attribute \src "libresoc.v:150225.5-150225.29" + switch \initial + attribute \src "libresoc.v:150225.9-150225.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\trap_op__trapaddr$9$next[12:0]$8311 $1\trap_op__traptype$8$next[6:0]$8312 $1\trap_op__is_32bit$7$next[0:0]$8309 $1\trap_op__cia$6$next[63:0]$8305 $1\trap_op__msr$5$next[63:0]$8310 $1\trap_op__insn$4$next[31:0]$8307 $1\trap_op__fn_unit$3$next[11:0]$8306 $1\trap_op__insn_type$2$next[6:0]$8308 } { \trap_op__trapaddr$34 \trap_op__traptype$33 \trap_op__is_32bit$32 \trap_op__cia$31 \trap_op__msr$30 \trap_op__insn$29 \trap_op__fn_unit$28 \trap_op__insn_type$27 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\trap_op__trapaddr$9$next[12:0]$8311 $1\trap_op__traptype$8$next[6:0]$8312 $1\trap_op__is_32bit$7$next[0:0]$8309 $1\trap_op__cia$6$next[63:0]$8305 $1\trap_op__msr$5$next[63:0]$8310 $1\trap_op__insn$4$next[31:0]$8307 $1\trap_op__fn_unit$3$next[11:0]$8306 $1\trap_op__insn_type$2$next[6:0]$8308 } { \trap_op__trapaddr$34 \trap_op__traptype$33 \trap_op__is_32bit$32 \trap_op__cia$31 \trap_op__msr$30 \trap_op__insn$29 \trap_op__fn_unit$28 \trap_op__insn_type$27 } + case + assign $1\trap_op__cia$6$next[63:0]$8305 \trap_op__cia$6 + assign $1\trap_op__fn_unit$3$next[11:0]$8306 \trap_op__fn_unit$3 + assign $1\trap_op__insn$4$next[31:0]$8307 \trap_op__insn$4 + assign $1\trap_op__insn_type$2$next[6:0]$8308 \trap_op__insn_type$2 + assign $1\trap_op__is_32bit$7$next[0:0]$8309 \trap_op__is_32bit$7 + assign $1\trap_op__msr$5$next[63:0]$8310 \trap_op__msr$5 + assign $1\trap_op__trapaddr$9$next[12:0]$8311 \trap_op__trapaddr$9 + assign $1\trap_op__traptype$8$next[6:0]$8312 \trap_op__traptype$8 + end + sync always + update \trap_op__cia$6$next $0\trap_op__cia$6$next[63:0]$8297 + update \trap_op__fn_unit$3$next $0\trap_op__fn_unit$3$next[11:0]$8298 + update \trap_op__insn$4$next $0\trap_op__insn$4$next[31:0]$8299 + update \trap_op__insn_type$2$next $0\trap_op__insn_type$2$next[6:0]$8300 + update \trap_op__is_32bit$7$next $0\trap_op__is_32bit$7$next[0:0]$8301 + update \trap_op__msr$5$next $0\trap_op__msr$5$next[63:0]$8302 + update \trap_op__trapaddr$9$next $0\trap_op__trapaddr$9$next[12:0]$8303 + update \trap_op__traptype$8$next $0\trap_op__traptype$8$next[6:0]$8304 + end + attribute \src "libresoc.v:150244.3-150262.6" + process $proc$libresoc.v:150244$8313 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\o$next[63:0]$8314 $1\o$next[63:0]$8316 + assign { } { } + assign $0\o_ok$next[0:0]$8315 $2\o_ok$next[0:0]$8318 + attribute \src "libresoc.v:150245.5-150245.29" + switch \initial + attribute \src "libresoc.v:150245.9-150245.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\o_ok$next[0:0]$8317 $1\o$next[63:0]$8316 } { \o_ok$36 \o$35 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\o_ok$next[0:0]$8317 $1\o$next[63:0]$8316 } { \o_ok$36 \o$35 } + case + assign $1\o$next[63:0]$8316 \o + assign $1\o_ok$next[0:0]$8317 \o_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\o_ok$next[0:0]$8318 1'0 + case + assign $2\o_ok$next[0:0]$8318 $1\o_ok$next[0:0]$8317 + end + sync always + update \o$next $0\o$next[63:0]$8314 + update \o_ok$next $0\o_ok$next[0:0]$8315 + end + attribute \src "libresoc.v:150263.3-150281.6" + process $proc$libresoc.v:150263$8319 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fast1$10$next[63:0]$8320 $1\fast1$10$next[63:0]$8322 + assign { } { } + assign $0\fast1_ok$next[0:0]$8321 $2\fast1_ok$next[0:0]$8324 + attribute \src "libresoc.v:150264.5-150264.29" + switch \initial + attribute \src "libresoc.v:150264.9-150264.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\fast1_ok$next[0:0]$8323 $1\fast1$10$next[63:0]$8322 } { \fast1_ok$38 \fast1$37 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\fast1_ok$next[0:0]$8323 $1\fast1$10$next[63:0]$8322 } { \fast1_ok$38 \fast1$37 } + case + assign $1\fast1$10$next[63:0]$8322 \fast1$10 + assign $1\fast1_ok$next[0:0]$8323 \fast1_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\fast1_ok$next[0:0]$8324 1'0 + case + assign $2\fast1_ok$next[0:0]$8324 $1\fast1_ok$next[0:0]$8323 + end + sync always + update \fast1$10$next $0\fast1$10$next[63:0]$8320 + update \fast1_ok$next $0\fast1_ok$next[0:0]$8321 + end + attribute \src "libresoc.v:150282.3-150300.6" + process $proc$libresoc.v:150282$8325 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fast2$11$next[63:0]$8326 $1\fast2$11$next[63:0]$8328 + assign { } { } + assign $0\fast2_ok$next[0:0]$8327 $2\fast2_ok$next[0:0]$8330 + attribute \src "libresoc.v:150283.5-150283.29" + switch \initial + attribute \src "libresoc.v:150283.9-150283.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\fast2_ok$next[0:0]$8329 $1\fast2$11$next[63:0]$8328 } { \fast2_ok$40 \fast2$39 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\fast2_ok$next[0:0]$8329 $1\fast2$11$next[63:0]$8328 } { \fast2_ok$40 \fast2$39 } + case + assign $1\fast2$11$next[63:0]$8328 \fast2$11 + assign $1\fast2_ok$next[0:0]$8329 \fast2_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\fast2_ok$next[0:0]$8330 1'0 + case + assign $2\fast2_ok$next[0:0]$8330 $1\fast2_ok$next[0:0]$8329 + end + sync always + update \fast2$11$next $0\fast2$11$next[63:0]$8326 + update \fast2_ok$next $0\fast2_ok$next[0:0]$8327 + end + attribute \src "libresoc.v:150301.3-150319.6" + process $proc$libresoc.v:150301$8331 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\nia$next[63:0]$8332 $1\nia$next[63:0]$8334 + assign { } { } + assign $0\nia_ok$next[0:0]$8333 $2\nia_ok$next[0:0]$8336 + attribute \src "libresoc.v:150302.5-150302.29" + switch \initial + attribute \src "libresoc.v:150302.9-150302.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\nia_ok$next[0:0]$8335 $1\nia$next[63:0]$8334 } { \nia_ok$42 \nia$41 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\nia_ok$next[0:0]$8335 $1\nia$next[63:0]$8334 } { \nia_ok$42 \nia$41 } + case + assign $1\nia$next[63:0]$8334 \nia + assign $1\nia_ok$next[0:0]$8335 \nia_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\nia_ok$next[0:0]$8336 1'0 + case + assign $2\nia_ok$next[0:0]$8336 $1\nia_ok$next[0:0]$8335 + end + sync always + update \nia$next $0\nia$next[63:0]$8332 + update \nia_ok$next $0\nia_ok$next[0:0]$8333 + end + attribute \src "libresoc.v:150320.3-150338.6" + process $proc$libresoc.v:150320$8337 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\msr$next[63:0]$8338 $1\msr$next[63:0]$8340 + assign { } { } + assign $0\msr_ok$next[0:0]$8339 $2\msr_ok$next[0:0]$8342 + attribute \src "libresoc.v:150321.5-150321.29" + switch \initial + attribute \src "libresoc.v:150321.9-150321.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\msr_ok$next[0:0]$8341 $1\msr$next[63:0]$8340 } { \msr_ok$44 \msr$43 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\msr_ok$next[0:0]$8341 $1\msr$next[63:0]$8340 } { \msr_ok$44 \msr$43 } + case + assign $1\msr$next[63:0]$8340 \msr + assign $1\msr_ok$next[0:0]$8341 \msr_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\msr_ok$next[0:0]$8342 1'0 + case + assign $2\msr_ok$next[0:0]$8342 $1\msr_ok$next[0:0]$8341 + end + sync always + update \msr$next $0\msr$next[63:0]$8338 + update \msr_ok$next $0\msr_ok$next[0:0]$8339 + end + connect \$24 $and$libresoc.v:150110$8257_Y + connect \p_ready_o \n_i_rdy_data + connect \n_valid_o \r_busy + connect { \msr_ok$44 \msr$43 } { \main_msr_ok \main_msr } + connect { \nia_ok$42 \nia$41 } { \main_nia_ok \main_nia } + connect { \fast2_ok$40 \fast2$39 } { \main_fast2_ok \main_fast2$22 } + connect { \fast1_ok$38 \fast1$37 } { \main_fast1_ok \main_fast1$21 } + connect { \o_ok$36 \o$35 } { \main_o_ok \main_o } + connect { \trap_op__trapaddr$34 \trap_op__traptype$33 \trap_op__is_32bit$32 \trap_op__cia$31 \trap_op__msr$30 \trap_op__insn$29 \trap_op__fn_unit$28 \trap_op__insn_type$27 } { \main_trap_op__trapaddr$20 \main_trap_op__traptype$19 \main_trap_op__is_32bit$18 \main_trap_op__cia$17 \main_trap_op__msr$16 \main_trap_op__insn$15 \main_trap_op__fn_unit$14 \main_trap_op__insn_type$13 } + connect \muxid$26 \main_muxid$12 + connect \p_valid_i_p_ready_o \$24 + connect \n_i_rdy_data \n_ready_i + connect \p_valid_i$23 \p_valid_i + connect \main_fast2 \fast2 + connect \main_fast1 \fast1 + connect \main_rb \rb + connect \main_ra \ra + connect { \main_trap_op__trapaddr \main_trap_op__traptype \main_trap_op__is_32bit \main_trap_op__cia \main_trap_op__msr \main_trap_op__insn \main_trap_op__fn_unit \main_trap_op__insn_type } { \trap_op__trapaddr \trap_op__traptype \trap_op__is_32bit \trap_op__cia \trap_op__msr \trap_op__insn \trap_op__fn_unit \trap_op__insn_type } + connect \main_muxid \muxid +end +attribute \src "libresoc.v:150361.1-151276.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.alu_spr0.pipe" +attribute \generator "nMigen" +module \pipe$61 + attribute \src "libresoc.v:151179.3-151197.6" + wire width 64 $0\fast1$7$next[63:0]$8434 + attribute \src "libresoc.v:151032.3-151033.33" + wire width 64 $0\fast1$7[63:0]$8386 + attribute \src "libresoc.v:150375.14-150375.46" + wire width 64 $0\fast1$7[63:0]$8458 + attribute \src "libresoc.v:151179.3-151197.6" + wire $0\fast1_ok$next[0:0]$8433 + attribute \src "libresoc.v:151034.3-151035.33" + wire $0\fast1_ok[0:0] + attribute \src "libresoc.v:150362.7-150362.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:151112.3-151124.6" + wire width 2 $0\muxid$1$next[1:0]$8409 + attribute \src "libresoc.v:151052.3-151053.33" + wire width 2 $0\muxid$1[1:0]$8402 + attribute \src "libresoc.v:150389.13-150389.29" + wire width 2 $0\muxid$1[1:0]$8461 + attribute \src "libresoc.v:151141.3-151159.6" + wire width 64 $0\o$next[63:0]$8421 + attribute \src "libresoc.v:151040.3-151041.19" + wire width 64 $0\o[63:0] + attribute \src "libresoc.v:151141.3-151159.6" + wire $0\o_ok$next[0:0]$8422 + attribute \src "libresoc.v:151042.3-151043.25" + wire $0\o_ok[0:0] + attribute \src "libresoc.v:151094.3-151111.6" + wire $0\r_busy$next[0:0]$8405 + attribute \src "libresoc.v:151054.3-151055.29" + wire $0\r_busy[0:0] + attribute \src "libresoc.v:151160.3-151178.6" + wire width 64 $0\spr1$6$next[63:0]$8427 + attribute \src "libresoc.v:151036.3-151037.31" + wire width 64 $0\spr1$6[63:0]$8389 + attribute \src "libresoc.v:150434.14-150434.45" + wire width 64 $0\spr1$6[63:0]$8466 + attribute \src "libresoc.v:151160.3-151178.6" + wire $0\spr1_ok$next[0:0]$8428 + attribute \src "libresoc.v:151038.3-151039.31" + wire $0\spr1_ok[0:0] + attribute \src "libresoc.v:151125.3-151140.6" + wire width 12 $0\spr_op__fn_unit$3$next[11:0]$8412 + attribute \src "libresoc.v:151046.3-151047.53" + wire width 12 $0\spr_op__fn_unit$3[11:0]$8396 + attribute \src "libresoc.v:150719.14-150719.43" + wire width 12 $0\spr_op__fn_unit$3[11:0]$8469 + attribute \src "libresoc.v:151125.3-151140.6" + wire width 32 $0\spr_op__insn$4$next[31:0]$8413 + attribute \src "libresoc.v:151048.3-151049.47" + wire width 32 $0\spr_op__insn$4[31:0]$8398 + attribute \src "libresoc.v:150728.14-150728.38" + wire width 32 $0\spr_op__insn$4[31:0]$8471 + attribute \src "libresoc.v:151125.3-151140.6" + wire width 7 $0\spr_op__insn_type$2$next[6:0]$8414 + attribute \src "libresoc.v:151044.3-151045.57" + wire width 7 $0\spr_op__insn_type$2[6:0]$8394 + attribute \src "libresoc.v:150883.13-150883.42" + wire width 7 $0\spr_op__insn_type$2[6:0]$8473 + attribute \src "libresoc.v:151125.3-151140.6" + wire $0\spr_op__is_32bit$5$next[0:0]$8415 + attribute \src "libresoc.v:151050.3-151051.55" + wire $0\spr_op__is_32bit$5[0:0]$8400 + attribute \src "libresoc.v:150968.7-150968.34" + wire $0\spr_op__is_32bit$5[0:0]$8475 + attribute \src "libresoc.v:151236.3-151254.6" + wire width 2 $0\xer_ca$10$next[1:0]$8451 + attribute \src "libresoc.v:151020.3-151021.37" + wire width 2 $0\xer_ca$10[1:0]$8377 + attribute \src "libresoc.v:150975.13-150975.31" + wire width 2 $0\xer_ca$10[1:0]$8477 + attribute \src "libresoc.v:151236.3-151254.6" + wire $0\xer_ca_ok$next[0:0]$8452 + attribute \src "libresoc.v:151022.3-151023.35" + wire $0\xer_ca_ok[0:0] + attribute \src "libresoc.v:151217.3-151235.6" + wire width 2 $0\xer_ov$9$next[1:0]$8446 + attribute \src "libresoc.v:151024.3-151025.35" + wire width 2 $0\xer_ov$9[1:0]$8380 + attribute \src "libresoc.v:150993.13-150993.30" + wire width 2 $0\xer_ov$9[1:0]$8480 + attribute \src "libresoc.v:151217.3-151235.6" + wire $0\xer_ov_ok$next[0:0]$8445 + attribute \src "libresoc.v:151026.3-151027.35" + wire $0\xer_ov_ok[0:0] + attribute \src "libresoc.v:151198.3-151216.6" + wire $0\xer_so$8$next[0:0]$8440 + attribute \src "libresoc.v:151028.3-151029.35" + wire $0\xer_so$8[0:0]$8383 + attribute \src "libresoc.v:151009.7-151009.24" + wire $0\xer_so$8[0:0]$8483 + attribute \src "libresoc.v:151198.3-151216.6" + wire $0\xer_so_ok$next[0:0]$8439 + attribute \src "libresoc.v:151030.3-151031.35" + wire $0\xer_so_ok[0:0] + attribute \src "libresoc.v:151179.3-151197.6" + wire width 64 $1\fast1$7$next[63:0]$8436 + attribute \src "libresoc.v:151179.3-151197.6" + wire $1\fast1_ok$next[0:0]$8435 + attribute \src "libresoc.v:150380.7-150380.22" + wire $1\fast1_ok[0:0] + attribute \src "libresoc.v:151112.3-151124.6" + wire width 2 $1\muxid$1$next[1:0]$8410 + attribute \src "libresoc.v:151141.3-151159.6" + wire width 64 $1\o$next[63:0]$8423 + attribute \src "libresoc.v:150402.14-150402.38" + wire width 64 $1\o[63:0] + attribute \src "libresoc.v:151141.3-151159.6" + wire $1\o_ok$next[0:0]$8424 + attribute \src "libresoc.v:150409.7-150409.18" + wire $1\o_ok[0:0] + attribute \src "libresoc.v:151094.3-151111.6" + wire $1\r_busy$next[0:0]$8406 + attribute \src "libresoc.v:150423.7-150423.20" + wire $1\r_busy[0:0] + attribute \src "libresoc.v:151160.3-151178.6" + wire width 64 $1\spr1$6$next[63:0]$8429 + attribute \src "libresoc.v:151160.3-151178.6" + wire $1\spr1_ok$next[0:0]$8430 + attribute \src "libresoc.v:150439.7-150439.21" + wire $1\spr1_ok[0:0] + attribute \src "libresoc.v:151125.3-151140.6" + wire width 12 $1\spr_op__fn_unit$3$next[11:0]$8416 + attribute \src "libresoc.v:151125.3-151140.6" + wire width 32 $1\spr_op__insn$4$next[31:0]$8417 + attribute \src "libresoc.v:151125.3-151140.6" + wire width 7 $1\spr_op__insn_type$2$next[6:0]$8418 + attribute \src "libresoc.v:151125.3-151140.6" + wire $1\spr_op__is_32bit$5$next[0:0]$8419 + attribute \src "libresoc.v:151236.3-151254.6" + wire width 2 $1\xer_ca$10$next[1:0]$8453 + attribute \src "libresoc.v:151236.3-151254.6" + wire $1\xer_ca_ok$next[0:0]$8454 + attribute \src "libresoc.v:150982.7-150982.23" + wire $1\xer_ca_ok[0:0] + attribute \src "libresoc.v:151217.3-151235.6" + wire width 2 $1\xer_ov$9$next[1:0]$8448 + attribute \src "libresoc.v:151217.3-151235.6" + wire $1\xer_ov_ok$next[0:0]$8447 + attribute \src "libresoc.v:150998.7-150998.23" + wire $1\xer_ov_ok[0:0] + attribute \src "libresoc.v:151198.3-151216.6" + wire $1\xer_so$8$next[0:0]$8442 + attribute \src "libresoc.v:151198.3-151216.6" + wire $1\xer_so_ok$next[0:0]$8441 + attribute \src "libresoc.v:151014.7-151014.23" + wire $1\xer_so_ok[0:0] + attribute \src "libresoc.v:151179.3-151197.6" + wire $2\fast1_ok$next[0:0]$8437 + attribute \src "libresoc.v:151141.3-151159.6" + wire $2\o_ok$next[0:0]$8425 + attribute \src "libresoc.v:151094.3-151111.6" + wire $2\r_busy$next[0:0]$8407 + attribute \src "libresoc.v:151160.3-151178.6" + wire $2\spr1_ok$next[0:0]$8431 + attribute \src "libresoc.v:151236.3-151254.6" + wire $2\xer_ca_ok$next[0:0]$8455 + attribute \src "libresoc.v:151217.3-151235.6" + wire $2\xer_ov_ok$next[0:0]$8449 + attribute \src "libresoc.v:151198.3-151216.6" + wire $2\xer_so_ok$next[0:0]$8443 + attribute \src "libresoc.v:151019.18-151019.118" + wire $and$libresoc.v:151019$8375_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + wire \$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 34 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 11 \fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \fast1$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 26 \fast1$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \fast1$7$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 27 \fast1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \fast1_ok$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \fast1_ok$next + attribute \src "libresoc.v:150362.7-150362.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 4 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 17 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$1$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" + wire \n_i_rdy_data + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire input 16 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire output 15 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 22 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \o$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \o$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 23 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \o_ok$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \o_ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire output 3 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" + wire \p_valid_i$21 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire \r_busy$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 9 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 10 \spr1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \spr1$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 24 \spr1$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \spr1$6$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 25 \spr1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \spr1_ok$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \spr1_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \spr_main_fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \spr_main_fast1$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \spr_main_fast1_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \spr_main_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \spr_main_muxid$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \spr_main_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \spr_main_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \spr_main_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \spr_main_spr1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \spr_main_spr1$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \spr_main_spr1_ok + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \spr_main_spr_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \spr_main_spr_op__fn_unit$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \spr_main_spr_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \spr_main_spr_op__insn$14 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \spr_main_spr_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \spr_main_spr_op__insn_type$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \spr_main_spr_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \spr_main_spr_op__is_32bit$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 \spr_main_xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \spr_main_xer_ca$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \spr_main_xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 \spr_main_xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \spr_main_xer_ov$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \spr_main_xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \spr_main_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \spr_main_xer_so$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \spr_main_xer_so_ok + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 6 \spr_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \spr_op__fn_unit$26 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 output 19 \spr_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \spr_op__fn_unit$3$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 7 \spr_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \spr_op__insn$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 20 \spr_op__insn$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \spr_op__insn$4$next + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 5 \spr_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 18 \spr_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \spr_op__insn_type$2$next + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \spr_op__insn_type$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \spr_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \spr_op__is_32bit$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 21 \spr_op__is_32bit$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \spr_op__is_32bit$5$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 input 14 \xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 output 32 \xer_ca$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \xer_ca$10$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \xer_ca$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 33 \xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \xer_ca_ok$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \xer_ca_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 input 13 \xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \xer_ov$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 output 30 \xer_ov$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \xer_ov$9$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 31 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \xer_ov_ok$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \xer_ov_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 12 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \xer_so$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 28 \xer_so$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \xer_so$8$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 29 \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \xer_so_ok$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \xer_so_ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + cell $and $and$libresoc.v:151019$8375 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i$21 + connect \B \p_ready_o + connect \Y $and$libresoc.v:151019$8375_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:151056.10-151059.4" + cell \n$63 \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:151060.10-151063.4" + cell \p$62 \p + connect \p_ready_o \p_ready_o + connect \p_valid_i \p_valid_i + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:151064.12-151093.4" + cell \spr_main \spr_main + connect \fast1 \spr_main_fast1 + connect \fast1$7 \spr_main_fast1$17 + connect \fast1_ok \spr_main_fast1_ok + connect \muxid \spr_main_muxid + connect \muxid$1 \spr_main_muxid$11 + connect \o \spr_main_o + connect \o_ok \spr_main_o_ok + connect \ra \spr_main_ra + connect \spr1 \spr_main_spr1 + connect \spr1$6 \spr_main_spr1$16 + connect \spr1_ok \spr_main_spr1_ok + connect \spr_op__fn_unit \spr_main_spr_op__fn_unit + connect \spr_op__fn_unit$3 \spr_main_spr_op__fn_unit$13 + connect \spr_op__insn \spr_main_spr_op__insn + connect \spr_op__insn$4 \spr_main_spr_op__insn$14 + connect \spr_op__insn_type \spr_main_spr_op__insn_type + connect \spr_op__insn_type$2 \spr_main_spr_op__insn_type$12 + connect \spr_op__is_32bit \spr_main_spr_op__is_32bit + connect \spr_op__is_32bit$5 \spr_main_spr_op__is_32bit$15 + connect \xer_ca \spr_main_xer_ca + connect \xer_ca$10 \spr_main_xer_ca$20 + connect \xer_ca_ok \spr_main_xer_ca_ok + connect \xer_ov \spr_main_xer_ov + connect \xer_ov$9 \spr_main_xer_ov$19 + connect \xer_ov_ok \spr_main_xer_ov_ok + connect \xer_so \spr_main_xer_so + connect \xer_so$8 \spr_main_xer_so$18 + connect \xer_so_ok \spr_main_xer_so_ok + end + attribute \src "libresoc.v:150362.7-150362.20" + process $proc$libresoc.v:150362$8456 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:150375.14-150375.46" + process $proc$libresoc.v:150375$8457 + assign { } { } + assign $0\fast1$7[63:0]$8458 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \fast1$7 $0\fast1$7[63:0]$8458 + end + attribute \src "libresoc.v:150380.7-150380.22" + process $proc$libresoc.v:150380$8459 + assign { } { } + assign $1\fast1_ok[0:0] 1'0 + sync always + sync init + update \fast1_ok $1\fast1_ok[0:0] + end + attribute \src "libresoc.v:150389.13-150389.29" + process $proc$libresoc.v:150389$8460 + assign { } { } + assign $0\muxid$1[1:0]$8461 2'00 + sync always + sync init + update \muxid$1 $0\muxid$1[1:0]$8461 + end + attribute \src "libresoc.v:150402.14-150402.38" + process $proc$libresoc.v:150402$8462 + assign { } { } + assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \o $1\o[63:0] + end + attribute \src "libresoc.v:150409.7-150409.18" + process $proc$libresoc.v:150409$8463 + assign { } { } + assign $1\o_ok[0:0] 1'0 + sync always + sync init + update \o_ok $1\o_ok[0:0] + end + attribute \src "libresoc.v:150423.7-150423.20" + process $proc$libresoc.v:150423$8464 + assign { } { } + assign $1\r_busy[0:0] 1'0 + sync always + sync init + update \r_busy $1\r_busy[0:0] + end + attribute \src "libresoc.v:150434.14-150434.45" + process $proc$libresoc.v:150434$8465 + assign { } { } + assign $0\spr1$6[63:0]$8466 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \spr1$6 $0\spr1$6[63:0]$8466 + end + attribute \src "libresoc.v:150439.7-150439.21" + process $proc$libresoc.v:150439$8467 + assign { } { } + assign $1\spr1_ok[0:0] 1'0 + sync always + sync init + update \spr1_ok $1\spr1_ok[0:0] + end + attribute \src "libresoc.v:150719.14-150719.43" + process $proc$libresoc.v:150719$8468 + assign { } { } + assign $0\spr_op__fn_unit$3[11:0]$8469 12'000000000000 + sync always + sync init + update \spr_op__fn_unit$3 $0\spr_op__fn_unit$3[11:0]$8469 + end + attribute \src "libresoc.v:150728.14-150728.38" + process $proc$libresoc.v:150728$8470 + assign { } { } + assign $0\spr_op__insn$4[31:0]$8471 0 + sync always + sync init + update \spr_op__insn$4 $0\spr_op__insn$4[31:0]$8471 + end + attribute \src "libresoc.v:150883.13-150883.42" + process $proc$libresoc.v:150883$8472 + assign { } { } + assign $0\spr_op__insn_type$2[6:0]$8473 7'0000000 + sync always + sync init + update \spr_op__insn_type$2 $0\spr_op__insn_type$2[6:0]$8473 + end + attribute \src "libresoc.v:150968.7-150968.34" + process $proc$libresoc.v:150968$8474 + assign { } { } + assign $0\spr_op__is_32bit$5[0:0]$8475 1'0 + sync always + sync init + update \spr_op__is_32bit$5 $0\spr_op__is_32bit$5[0:0]$8475 + end + attribute \src "libresoc.v:150975.13-150975.31" + process $proc$libresoc.v:150975$8476 + assign { } { } + assign $0\xer_ca$10[1:0]$8477 2'00 + sync always + sync init + update \xer_ca$10 $0\xer_ca$10[1:0]$8477 + end + attribute \src "libresoc.v:150982.7-150982.23" + process $proc$libresoc.v:150982$8478 + assign { } { } + assign $1\xer_ca_ok[0:0] 1'0 + sync always + sync init + update \xer_ca_ok $1\xer_ca_ok[0:0] + end + attribute \src "libresoc.v:150993.13-150993.30" + process $proc$libresoc.v:150993$8479 + assign { } { } + assign $0\xer_ov$9[1:0]$8480 2'00 + sync always + sync init + update \xer_ov$9 $0\xer_ov$9[1:0]$8480 + end + attribute \src "libresoc.v:150998.7-150998.23" + process $proc$libresoc.v:150998$8481 + assign { } { } + assign $1\xer_ov_ok[0:0] 1'0 + sync always + sync init + update \xer_ov_ok $1\xer_ov_ok[0:0] + end + attribute \src "libresoc.v:151009.7-151009.24" + process $proc$libresoc.v:151009$8482 + assign { } { } + assign $0\xer_so$8[0:0]$8483 1'0 + sync always + sync init + update \xer_so$8 $0\xer_so$8[0:0]$8483 + end + attribute \src "libresoc.v:151014.7-151014.23" + process $proc$libresoc.v:151014$8484 + assign { } { } + assign $1\xer_so_ok[0:0] 1'0 + sync always + sync init + update \xer_so_ok $1\xer_so_ok[0:0] + end + attribute \src "libresoc.v:151020.3-151021.37" + process $proc$libresoc.v:151020$8376 + assign { } { } + assign $0\xer_ca$10[1:0]$8377 \xer_ca$10$next + sync posedge \coresync_clk + update \xer_ca$10 $0\xer_ca$10[1:0]$8377 + end + attribute \src "libresoc.v:151022.3-151023.35" + process $proc$libresoc.v:151022$8378 + assign { } { } + assign $0\xer_ca_ok[0:0] \xer_ca_ok$next + sync posedge \coresync_clk + update \xer_ca_ok $0\xer_ca_ok[0:0] + end + attribute \src "libresoc.v:151024.3-151025.35" + process $proc$libresoc.v:151024$8379 + assign { } { } + assign $0\xer_ov$9[1:0]$8380 \xer_ov$9$next + sync posedge \coresync_clk + update \xer_ov$9 $0\xer_ov$9[1:0]$8380 + end + attribute \src "libresoc.v:151026.3-151027.35" + process $proc$libresoc.v:151026$8381 + assign { } { } + assign $0\xer_ov_ok[0:0] \xer_ov_ok$next + sync posedge \coresync_clk + update \xer_ov_ok $0\xer_ov_ok[0:0] + end + attribute \src "libresoc.v:151028.3-151029.35" + process $proc$libresoc.v:151028$8382 + assign { } { } + assign $0\xer_so$8[0:0]$8383 \xer_so$8$next + sync posedge \coresync_clk + update \xer_so$8 $0\xer_so$8[0:0]$8383 + end + attribute \src "libresoc.v:151030.3-151031.35" + process $proc$libresoc.v:151030$8384 + assign { } { } + assign $0\xer_so_ok[0:0] \xer_so_ok$next + sync posedge \coresync_clk + update \xer_so_ok $0\xer_so_ok[0:0] + end + attribute \src "libresoc.v:151032.3-151033.33" + process $proc$libresoc.v:151032$8385 + assign { } { } + assign $0\fast1$7[63:0]$8386 \fast1$7$next + sync posedge \coresync_clk + update \fast1$7 $0\fast1$7[63:0]$8386 + end + attribute \src "libresoc.v:151034.3-151035.33" + process $proc$libresoc.v:151034$8387 + assign { } { } + assign $0\fast1_ok[0:0] \fast1_ok$next + sync posedge \coresync_clk + update \fast1_ok $0\fast1_ok[0:0] + end + attribute \src "libresoc.v:151036.3-151037.31" + process $proc$libresoc.v:151036$8388 + assign { } { } + assign $0\spr1$6[63:0]$8389 \spr1$6$next + sync posedge \coresync_clk + update \spr1$6 $0\spr1$6[63:0]$8389 + end + attribute \src "libresoc.v:151038.3-151039.31" + process $proc$libresoc.v:151038$8390 + assign { } { } + assign $0\spr1_ok[0:0] \spr1_ok$next + sync posedge \coresync_clk + update \spr1_ok $0\spr1_ok[0:0] + end + attribute \src "libresoc.v:151040.3-151041.19" + process $proc$libresoc.v:151040$8391 + assign { } { } + assign $0\o[63:0] \o$next + sync posedge \coresync_clk + update \o $0\o[63:0] + end + attribute \src "libresoc.v:151042.3-151043.25" + process $proc$libresoc.v:151042$8392 + assign { } { } + assign $0\o_ok[0:0] \o_ok$next + sync posedge \coresync_clk + update \o_ok $0\o_ok[0:0] + end + attribute \src "libresoc.v:151044.3-151045.57" + process $proc$libresoc.v:151044$8393 + assign { } { } + assign $0\spr_op__insn_type$2[6:0]$8394 \spr_op__insn_type$2$next + sync posedge \coresync_clk + update \spr_op__insn_type$2 $0\spr_op__insn_type$2[6:0]$8394 + end + attribute \src "libresoc.v:151046.3-151047.53" + process $proc$libresoc.v:151046$8395 + assign { } { } + assign $0\spr_op__fn_unit$3[11:0]$8396 \spr_op__fn_unit$3$next + sync posedge \coresync_clk + update \spr_op__fn_unit$3 $0\spr_op__fn_unit$3[11:0]$8396 + end + attribute \src "libresoc.v:151048.3-151049.47" + process $proc$libresoc.v:151048$8397 + assign { } { } + assign $0\spr_op__insn$4[31:0]$8398 \spr_op__insn$4$next + sync posedge \coresync_clk + update \spr_op__insn$4 $0\spr_op__insn$4[31:0]$8398 + end + attribute \src "libresoc.v:151050.3-151051.55" + process $proc$libresoc.v:151050$8399 + assign { } { } + assign $0\spr_op__is_32bit$5[0:0]$8400 \spr_op__is_32bit$5$next + sync posedge \coresync_clk + update \spr_op__is_32bit$5 $0\spr_op__is_32bit$5[0:0]$8400 + end + attribute \src "libresoc.v:151052.3-151053.33" + process $proc$libresoc.v:151052$8401 + assign { } { } + assign $0\muxid$1[1:0]$8402 \muxid$1$next + sync posedge \coresync_clk + update \muxid$1 $0\muxid$1[1:0]$8402 + end + attribute \src "libresoc.v:151054.3-151055.29" + process $proc$libresoc.v:151054$8403 + assign { } { } + assign $0\r_busy[0:0] \r_busy$next + sync posedge \coresync_clk + update \r_busy $0\r_busy[0:0] + end + attribute \src "libresoc.v:151094.3-151111.6" + process $proc$libresoc.v:151094$8404 + assign { } { } + assign { } { } + assign { } { } + assign $0\r_busy$next[0:0]$8405 $2\r_busy$next[0:0]$8407 + attribute \src "libresoc.v:151095.5-151095.29" + switch \initial + attribute \src "libresoc.v:151095.9-151095.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\r_busy$next[0:0]$8406 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\r_busy$next[0:0]$8406 1'0 + case + assign $1\r_busy$next[0:0]$8406 \r_busy + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r_busy$next[0:0]$8407 1'0 + case + assign $2\r_busy$next[0:0]$8407 $1\r_busy$next[0:0]$8406 + end + sync always + update \r_busy$next $0\r_busy$next[0:0]$8405 + end + attribute \src "libresoc.v:151112.3-151124.6" + process $proc$libresoc.v:151112$8408 + assign { } { } + assign { } { } + assign $0\muxid$1$next[1:0]$8409 $1\muxid$1$next[1:0]$8410 + attribute \src "libresoc.v:151113.5-151113.29" + switch \initial + attribute \src "libresoc.v:151113.9-151113.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\muxid$1$next[1:0]$8410 \muxid$24 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\muxid$1$next[1:0]$8410 \muxid$24 + case + assign $1\muxid$1$next[1:0]$8410 \muxid$1 + end + sync always + update \muxid$1$next $0\muxid$1$next[1:0]$8409 + end + attribute \src "libresoc.v:151125.3-151140.6" + process $proc$libresoc.v:151125$8411 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\spr_op__fn_unit$3$next[11:0]$8412 $1\spr_op__fn_unit$3$next[11:0]$8416 + assign $0\spr_op__insn$4$next[31:0]$8413 $1\spr_op__insn$4$next[31:0]$8417 + assign $0\spr_op__insn_type$2$next[6:0]$8414 $1\spr_op__insn_type$2$next[6:0]$8418 + assign $0\spr_op__is_32bit$5$next[0:0]$8415 $1\spr_op__is_32bit$5$next[0:0]$8419 + attribute \src "libresoc.v:151126.5-151126.29" + switch \initial + attribute \src "libresoc.v:151126.9-151126.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\spr_op__is_32bit$5$next[0:0]$8419 $1\spr_op__insn$4$next[31:0]$8417 $1\spr_op__fn_unit$3$next[11:0]$8416 $1\spr_op__insn_type$2$next[6:0]$8418 } { \spr_op__is_32bit$28 \spr_op__insn$27 \spr_op__fn_unit$26 \spr_op__insn_type$25 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\spr_op__is_32bit$5$next[0:0]$8419 $1\spr_op__insn$4$next[31:0]$8417 $1\spr_op__fn_unit$3$next[11:0]$8416 $1\spr_op__insn_type$2$next[6:0]$8418 } { \spr_op__is_32bit$28 \spr_op__insn$27 \spr_op__fn_unit$26 \spr_op__insn_type$25 } + case + assign $1\spr_op__fn_unit$3$next[11:0]$8416 \spr_op__fn_unit$3 + assign $1\spr_op__insn$4$next[31:0]$8417 \spr_op__insn$4 + assign $1\spr_op__insn_type$2$next[6:0]$8418 \spr_op__insn_type$2 + assign $1\spr_op__is_32bit$5$next[0:0]$8419 \spr_op__is_32bit$5 + end + sync always + update \spr_op__fn_unit$3$next $0\spr_op__fn_unit$3$next[11:0]$8412 + update \spr_op__insn$4$next $0\spr_op__insn$4$next[31:0]$8413 + update \spr_op__insn_type$2$next $0\spr_op__insn_type$2$next[6:0]$8414 + update \spr_op__is_32bit$5$next $0\spr_op__is_32bit$5$next[0:0]$8415 + end + attribute \src "libresoc.v:151141.3-151159.6" + process $proc$libresoc.v:151141$8420 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\o$next[63:0]$8421 $1\o$next[63:0]$8423 + assign { } { } + assign $0\o_ok$next[0:0]$8422 $2\o_ok$next[0:0]$8425 + attribute \src "libresoc.v:151142.5-151142.29" + switch \initial + attribute \src "libresoc.v:151142.9-151142.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\o_ok$next[0:0]$8424 $1\o$next[63:0]$8423 } { \o_ok$30 \o$29 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\o_ok$next[0:0]$8424 $1\o$next[63:0]$8423 } { \o_ok$30 \o$29 } + case + assign $1\o$next[63:0]$8423 \o + assign $1\o_ok$next[0:0]$8424 \o_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\o_ok$next[0:0]$8425 1'0 + case + assign $2\o_ok$next[0:0]$8425 $1\o_ok$next[0:0]$8424 + end + sync always + update \o$next $0\o$next[63:0]$8421 + update \o_ok$next $0\o_ok$next[0:0]$8422 + end + attribute \src "libresoc.v:151160.3-151178.6" + process $proc$libresoc.v:151160$8426 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\spr1$6$next[63:0]$8427 $1\spr1$6$next[63:0]$8429 + assign { } { } + assign $0\spr1_ok$next[0:0]$8428 $2\spr1_ok$next[0:0]$8431 + attribute \src "libresoc.v:151161.5-151161.29" + switch \initial + attribute \src "libresoc.v:151161.9-151161.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\spr1_ok$next[0:0]$8430 $1\spr1$6$next[63:0]$8429 } { \spr1_ok$32 \spr1$31 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\spr1_ok$next[0:0]$8430 $1\spr1$6$next[63:0]$8429 } { \spr1_ok$32 \spr1$31 } + case + assign $1\spr1$6$next[63:0]$8429 \spr1$6 + assign $1\spr1_ok$next[0:0]$8430 \spr1_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\spr1_ok$next[0:0]$8431 1'0 + case + assign $2\spr1_ok$next[0:0]$8431 $1\spr1_ok$next[0:0]$8430 + end + sync always + update \spr1$6$next $0\spr1$6$next[63:0]$8427 + update \spr1_ok$next $0\spr1_ok$next[0:0]$8428 + end + attribute \src "libresoc.v:151179.3-151197.6" + process $proc$libresoc.v:151179$8432 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fast1$7$next[63:0]$8434 $1\fast1$7$next[63:0]$8436 + assign $0\fast1_ok$next[0:0]$8433 $2\fast1_ok$next[0:0]$8437 + attribute \src "libresoc.v:151180.5-151180.29" + switch \initial + attribute \src "libresoc.v:151180.9-151180.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\fast1_ok$next[0:0]$8435 $1\fast1$7$next[63:0]$8436 } { \fast1_ok$34 \fast1$33 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\fast1_ok$next[0:0]$8435 $1\fast1$7$next[63:0]$8436 } { \fast1_ok$34 \fast1$33 } + case + assign $1\fast1_ok$next[0:0]$8435 \fast1_ok + assign $1\fast1$7$next[63:0]$8436 \fast1$7 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\fast1_ok$next[0:0]$8437 1'0 + case + assign $2\fast1_ok$next[0:0]$8437 $1\fast1_ok$next[0:0]$8435 + end + sync always + update \fast1_ok$next $0\fast1_ok$next[0:0]$8433 + update \fast1$7$next $0\fast1$7$next[63:0]$8434 + end + attribute \src "libresoc.v:151198.3-151216.6" + process $proc$libresoc.v:151198$8438 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\xer_so$8$next[0:0]$8440 $1\xer_so$8$next[0:0]$8442 + assign $0\xer_so_ok$next[0:0]$8439 $2\xer_so_ok$next[0:0]$8443 + attribute \src "libresoc.v:151199.5-151199.29" + switch \initial + attribute \src "libresoc.v:151199.9-151199.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\xer_so_ok$next[0:0]$8441 $1\xer_so$8$next[0:0]$8442 } { \xer_so_ok$36 \xer_so$35 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\xer_so_ok$next[0:0]$8441 $1\xer_so$8$next[0:0]$8442 } { \xer_so_ok$36 \xer_so$35 } + case + assign $1\xer_so_ok$next[0:0]$8441 \xer_so_ok + assign $1\xer_so$8$next[0:0]$8442 \xer_so$8 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\xer_so_ok$next[0:0]$8443 1'0 + case + assign $2\xer_so_ok$next[0:0]$8443 $1\xer_so_ok$next[0:0]$8441 + end + sync always + update \xer_so_ok$next $0\xer_so_ok$next[0:0]$8439 + update \xer_so$8$next $0\xer_so$8$next[0:0]$8440 + end + attribute \src "libresoc.v:151217.3-151235.6" + process $proc$libresoc.v:151217$8444 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\xer_ov$9$next[1:0]$8446 $1\xer_ov$9$next[1:0]$8448 + assign $0\xer_ov_ok$next[0:0]$8445 $2\xer_ov_ok$next[0:0]$8449 + attribute \src "libresoc.v:151218.5-151218.29" + switch \initial + attribute \src "libresoc.v:151218.9-151218.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\xer_ov_ok$next[0:0]$8447 $1\xer_ov$9$next[1:0]$8448 } { \xer_ov_ok$38 \xer_ov$37 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\xer_ov_ok$next[0:0]$8447 $1\xer_ov$9$next[1:0]$8448 } { \xer_ov_ok$38 \xer_ov$37 } + case + assign $1\xer_ov_ok$next[0:0]$8447 \xer_ov_ok + assign $1\xer_ov$9$next[1:0]$8448 \xer_ov$9 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\xer_ov_ok$next[0:0]$8449 1'0 + case + assign $2\xer_ov_ok$next[0:0]$8449 $1\xer_ov_ok$next[0:0]$8447 + end + sync always + update \xer_ov_ok$next $0\xer_ov_ok$next[0:0]$8445 + update \xer_ov$9$next $0\xer_ov$9$next[1:0]$8446 + end + attribute \src "libresoc.v:151236.3-151254.6" + process $proc$libresoc.v:151236$8450 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\xer_ca$10$next[1:0]$8451 $1\xer_ca$10$next[1:0]$8453 + assign { } { } + assign $0\xer_ca_ok$next[0:0]$8452 $2\xer_ca_ok$next[0:0]$8455 + attribute \src "libresoc.v:151237.5-151237.29" + switch \initial + attribute \src "libresoc.v:151237.9-151237.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\xer_ca_ok$next[0:0]$8454 $1\xer_ca$10$next[1:0]$8453 } { \xer_ca_ok$40 \xer_ca$39 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\xer_ca_ok$next[0:0]$8454 $1\xer_ca$10$next[1:0]$8453 } { \xer_ca_ok$40 \xer_ca$39 } + case + assign $1\xer_ca$10$next[1:0]$8453 \xer_ca$10 + assign $1\xer_ca_ok$next[0:0]$8454 \xer_ca_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\xer_ca_ok$next[0:0]$8455 1'0 + case + assign $2\xer_ca_ok$next[0:0]$8455 $1\xer_ca_ok$next[0:0]$8454 + end + sync always + update \xer_ca$10$next $0\xer_ca$10$next[1:0]$8451 + update \xer_ca_ok$next $0\xer_ca_ok$next[0:0]$8452 + end + connect \$22 $and$libresoc.v:151019$8375_Y + connect \p_ready_o \n_i_rdy_data + connect \n_valid_o \r_busy + connect { \xer_ca_ok$40 \xer_ca$39 } { \spr_main_xer_ca_ok \spr_main_xer_ca$20 } + connect { \xer_ov_ok$38 \xer_ov$37 } { \spr_main_xer_ov_ok \spr_main_xer_ov$19 } + connect { \xer_so_ok$36 \xer_so$35 } { \spr_main_xer_so_ok \spr_main_xer_so$18 } + connect { \fast1_ok$34 \fast1$33 } { \spr_main_fast1_ok \spr_main_fast1$17 } + connect { \spr1_ok$32 \spr1$31 } { \spr_main_spr1_ok \spr_main_spr1$16 } + connect { \o_ok$30 \o$29 } { \spr_main_o_ok \spr_main_o } + connect { \spr_op__is_32bit$28 \spr_op__insn$27 \spr_op__fn_unit$26 \spr_op__insn_type$25 } { \spr_main_spr_op__is_32bit$15 \spr_main_spr_op__insn$14 \spr_main_spr_op__fn_unit$13 \spr_main_spr_op__insn_type$12 } + connect \muxid$24 \spr_main_muxid$11 + connect \p_valid_i_p_ready_o \$22 + connect \n_i_rdy_data \n_ready_i + connect \p_valid_i$21 \p_valid_i + connect \spr_main_xer_ca \xer_ca + connect \spr_main_xer_ov \xer_ov + connect \spr_main_xer_so \xer_so + connect \spr_main_fast1 \fast1 + connect \spr_main_spr1 \spr1 + connect \spr_main_ra \ra + connect { \spr_main_spr_op__is_32bit \spr_main_spr_op__insn \spr_main_spr_op__fn_unit \spr_main_spr_op__insn_type } { \spr_op__is_32bit \spr_op__insn \spr_op__fn_unit \spr_op__insn_type } + connect \spr_main_muxid \muxid +end +attribute \src "libresoc.v:151280.1-152751.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alu_alu0.pipe1" +attribute \generator "nMigen" +module \pipe1 + attribute \src "libresoc.v:152665.3-152706.6" + wire width 4 $0\alu_op__data_len$next[3:0]$8548 + attribute \src "libresoc.v:152441.3-152442.49" + wire width 4 $0\alu_op__data_len[3:0] + attribute \src "libresoc.v:152665.3-152706.6" + wire width 12 $0\alu_op__fn_unit$next[11:0]$8549 + attribute \src "libresoc.v:152411.3-152412.47" + wire width 12 $0\alu_op__fn_unit[11:0] + attribute \src "libresoc.v:152665.3-152706.6" + wire width 64 $0\alu_op__imm_data__data$next[63:0]$8550 + attribute \src "libresoc.v:152413.3-152414.61" + wire width 64 $0\alu_op__imm_data__data[63:0] + attribute \src "libresoc.v:152665.3-152706.6" + wire $0\alu_op__imm_data__ok$next[0:0]$8551 + attribute \src "libresoc.v:152415.3-152416.57" + wire $0\alu_op__imm_data__ok[0:0] + attribute \src "libresoc.v:152665.3-152706.6" + wire width 2 $0\alu_op__input_carry$next[1:0]$8552 + attribute \src "libresoc.v:152433.3-152434.55" + wire width 2 $0\alu_op__input_carry[1:0] + attribute \src "libresoc.v:152665.3-152706.6" + wire width 32 $0\alu_op__insn$next[31:0]$8553 + attribute \src "libresoc.v:152443.3-152444.41" + wire width 32 $0\alu_op__insn[31:0] + attribute \src "libresoc.v:152665.3-152706.6" + wire width 7 $0\alu_op__insn_type$next[6:0]$8554 + attribute \src "libresoc.v:152409.3-152410.51" + wire width 7 $0\alu_op__insn_type[6:0] + attribute \src "libresoc.v:152665.3-152706.6" + wire $0\alu_op__invert_in$next[0:0]$8555 + attribute \src "libresoc.v:152425.3-152426.51" + wire $0\alu_op__invert_in[0:0] + attribute \src "libresoc.v:152665.3-152706.6" + wire $0\alu_op__invert_out$next[0:0]$8556 + attribute \src "libresoc.v:152429.3-152430.53" + wire $0\alu_op__invert_out[0:0] + attribute \src "libresoc.v:152665.3-152706.6" + wire $0\alu_op__is_32bit$next[0:0]$8557 + attribute \src "libresoc.v:152437.3-152438.49" + wire $0\alu_op__is_32bit[0:0] + attribute \src "libresoc.v:152665.3-152706.6" + wire $0\alu_op__is_signed$next[0:0]$8558 + attribute \src "libresoc.v:152439.3-152440.51" + wire $0\alu_op__is_signed[0:0] + attribute \src "libresoc.v:152665.3-152706.6" + wire $0\alu_op__oe__oe$next[0:0]$8559 + attribute \src "libresoc.v:152421.3-152422.45" + wire $0\alu_op__oe__oe[0:0] + attribute \src "libresoc.v:152665.3-152706.6" + wire $0\alu_op__oe__ok$next[0:0]$8560 + attribute \src "libresoc.v:152423.3-152424.45" + wire $0\alu_op__oe__ok[0:0] + attribute \src "libresoc.v:152665.3-152706.6" + wire $0\alu_op__output_carry$next[0:0]$8561 + attribute \src "libresoc.v:152435.3-152436.57" + wire $0\alu_op__output_carry[0:0] + attribute \src "libresoc.v:152665.3-152706.6" + wire $0\alu_op__rc__ok$next[0:0]$8562 + attribute \src "libresoc.v:152419.3-152420.45" + wire $0\alu_op__rc__ok[0:0] + attribute \src "libresoc.v:152665.3-152706.6" + wire $0\alu_op__rc__rc$next[0:0]$8563 + attribute \src "libresoc.v:152417.3-152418.45" + wire $0\alu_op__rc__rc[0:0] + attribute \src "libresoc.v:152665.3-152706.6" + wire $0\alu_op__write_cr0$next[0:0]$8564 + attribute \src "libresoc.v:152431.3-152432.51" + wire $0\alu_op__write_cr0[0:0] + attribute \src "libresoc.v:152665.3-152706.6" + wire $0\alu_op__zero_a$next[0:0]$8565 + attribute \src "libresoc.v:152427.3-152428.45" + wire $0\alu_op__zero_a[0:0] + attribute \src "libresoc.v:152558.3-152576.6" + wire width 4 $0\cr_a$next[3:0]$8517 + attribute \src "libresoc.v:152401.3-152402.25" + wire width 4 $0\cr_a[3:0] + attribute \src "libresoc.v:152558.3-152576.6" + wire $0\cr_a_ok$next[0:0]$8518 + attribute \src "libresoc.v:152403.3-152404.31" + wire $0\cr_a_ok[0:0] + attribute \src "libresoc.v:151281.7-151281.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:152652.3-152664.6" + wire width 2 $0\muxid$next[1:0]$8545 + attribute \src "libresoc.v:152445.3-152446.27" + wire width 2 $0\muxid[1:0] + attribute \src "libresoc.v:152707.3-152725.6" + wire width 64 $0\o$next[63:0]$8591 + attribute \src "libresoc.v:152405.3-152406.19" + wire width 64 $0\o[63:0] + attribute \src "libresoc.v:152707.3-152725.6" + wire $0\o_ok$next[0:0]$8592 + attribute \src "libresoc.v:152407.3-152408.25" + wire $0\o_ok[0:0] + attribute \src "libresoc.v:152634.3-152651.6" + wire $0\r_busy$next[0:0]$8541 + attribute \src "libresoc.v:152447.3-152448.29" + wire $0\r_busy[0:0] + attribute \src "libresoc.v:152577.3-152595.6" + wire width 2 $0\xer_ca$next[1:0]$8524 + attribute \src "libresoc.v:152397.3-152398.29" + wire width 2 $0\xer_ca[1:0] + attribute \src "libresoc.v:152577.3-152595.6" + wire $0\xer_ca_ok$next[0:0]$8523 + attribute \src "libresoc.v:152399.3-152400.35" + wire $0\xer_ca_ok[0:0] + attribute \src "libresoc.v:152596.3-152614.6" + wire width 2 $0\xer_ov$next[1:0]$8529 + attribute \src "libresoc.v:152393.3-152394.29" + wire width 2 $0\xer_ov[1:0] + attribute \src "libresoc.v:152596.3-152614.6" + wire $0\xer_ov_ok$next[0:0]$8530 + attribute \src "libresoc.v:152395.3-152396.35" + wire $0\xer_ov_ok[0:0] + attribute \src "libresoc.v:152615.3-152633.6" + wire $0\xer_so$next[0:0]$8535 + attribute \src "libresoc.v:152389.3-152390.29" + wire $0\xer_so[0:0] + attribute \src "libresoc.v:152615.3-152633.6" + wire $0\xer_so_ok$next[0:0]$8536 + attribute \src "libresoc.v:152391.3-152392.35" + wire $0\xer_so_ok[0:0] + attribute \src "libresoc.v:152665.3-152706.6" + wire width 4 $1\alu_op__data_len$next[3:0]$8566 + attribute \src "libresoc.v:151286.13-151286.36" + wire width 4 $1\alu_op__data_len[3:0] + attribute \src "libresoc.v:152665.3-152706.6" + wire width 12 $1\alu_op__fn_unit$next[11:0]$8567 + attribute \src "libresoc.v:151308.14-151308.39" + wire width 12 $1\alu_op__fn_unit[11:0] + attribute \src "libresoc.v:152665.3-152706.6" + wire width 64 $1\alu_op__imm_data__data$next[63:0]$8568 + attribute \src "libresoc.v:151343.14-151343.59" + wire width 64 $1\alu_op__imm_data__data[63:0] + attribute \src "libresoc.v:152665.3-152706.6" + wire $1\alu_op__imm_data__ok$next[0:0]$8569 + attribute \src "libresoc.v:151352.7-151352.34" + wire $1\alu_op__imm_data__ok[0:0] + attribute \src "libresoc.v:152665.3-152706.6" + wire width 2 $1\alu_op__input_carry$next[1:0]$8570 + attribute \src "libresoc.v:151365.13-151365.39" + wire width 2 $1\alu_op__input_carry[1:0] + attribute \src "libresoc.v:152665.3-152706.6" + wire width 32 $1\alu_op__insn$next[31:0]$8571 + attribute \src "libresoc.v:151382.14-151382.34" + wire width 32 $1\alu_op__insn[31:0] + attribute \src "libresoc.v:152665.3-152706.6" + wire width 7 $1\alu_op__insn_type$next[6:0]$8572 + attribute \src "libresoc.v:151465.13-151465.38" + wire width 7 $1\alu_op__insn_type[6:0] + attribute \src "libresoc.v:152665.3-152706.6" + wire $1\alu_op__invert_in$next[0:0]$8573 + attribute \src "libresoc.v:151622.7-151622.31" + wire $1\alu_op__invert_in[0:0] + attribute \src "libresoc.v:152665.3-152706.6" + wire $1\alu_op__invert_out$next[0:0]$8574 + attribute \src "libresoc.v:151631.7-151631.32" + wire $1\alu_op__invert_out[0:0] + attribute \src "libresoc.v:152665.3-152706.6" + wire $1\alu_op__is_32bit$next[0:0]$8575 + attribute \src "libresoc.v:151640.7-151640.30" + wire $1\alu_op__is_32bit[0:0] + attribute \src "libresoc.v:152665.3-152706.6" + wire $1\alu_op__is_signed$next[0:0]$8576 + attribute \src "libresoc.v:151649.7-151649.31" + wire $1\alu_op__is_signed[0:0] + attribute \src "libresoc.v:152665.3-152706.6" + wire $1\alu_op__oe__oe$next[0:0]$8577 + attribute \src "libresoc.v:151658.7-151658.28" + wire $1\alu_op__oe__oe[0:0] + attribute \src "libresoc.v:152665.3-152706.6" + wire $1\alu_op__oe__ok$next[0:0]$8578 + attribute \src "libresoc.v:151667.7-151667.28" + wire $1\alu_op__oe__ok[0:0] + attribute \src "libresoc.v:152665.3-152706.6" + wire $1\alu_op__output_carry$next[0:0]$8579 + attribute \src "libresoc.v:151676.7-151676.34" + wire $1\alu_op__output_carry[0:0] + attribute \src "libresoc.v:152665.3-152706.6" + wire $1\alu_op__rc__ok$next[0:0]$8580 + attribute \src "libresoc.v:151685.7-151685.28" + wire $1\alu_op__rc__ok[0:0] + attribute \src "libresoc.v:152665.3-152706.6" + wire $1\alu_op__rc__rc$next[0:0]$8581 + attribute \src "libresoc.v:151694.7-151694.28" + wire $1\alu_op__rc__rc[0:0] + attribute \src "libresoc.v:152665.3-152706.6" + wire $1\alu_op__write_cr0$next[0:0]$8582 + attribute \src "libresoc.v:151703.7-151703.31" + wire $1\alu_op__write_cr0[0:0] + attribute \src "libresoc.v:152665.3-152706.6" + wire $1\alu_op__zero_a$next[0:0]$8583 + attribute \src "libresoc.v:151712.7-151712.28" + wire $1\alu_op__zero_a[0:0] + attribute \src "libresoc.v:152558.3-152576.6" + wire width 4 $1\cr_a$next[3:0]$8519 + attribute \src "libresoc.v:151725.13-151725.24" + wire width 4 $1\cr_a[3:0] + attribute \src "libresoc.v:152558.3-152576.6" + wire $1\cr_a_ok$next[0:0]$8520 + attribute \src "libresoc.v:151732.7-151732.21" + wire $1\cr_a_ok[0:0] + attribute \src "libresoc.v:152652.3-152664.6" + wire width 2 $1\muxid$next[1:0]$8546 + attribute \src "libresoc.v:152297.13-152297.25" + wire width 2 $1\muxid[1:0] + attribute \src "libresoc.v:152707.3-152725.6" + wire width 64 $1\o$next[63:0]$8593 + attribute \src "libresoc.v:152312.14-152312.38" + wire width 64 $1\o[63:0] + attribute \src "libresoc.v:152707.3-152725.6" + wire $1\o_ok$next[0:0]$8594 + attribute \src "libresoc.v:152319.7-152319.18" + wire $1\o_ok[0:0] + attribute \src "libresoc.v:152634.3-152651.6" + wire $1\r_busy$next[0:0]$8542 + attribute \src "libresoc.v:152333.7-152333.20" + wire $1\r_busy[0:0] + attribute \src "libresoc.v:152577.3-152595.6" + wire width 2 $1\xer_ca$next[1:0]$8526 + attribute \src "libresoc.v:152342.13-152342.26" + wire width 2 $1\xer_ca[1:0] + attribute \src "libresoc.v:152577.3-152595.6" + wire $1\xer_ca_ok$next[0:0]$8525 + attribute \src "libresoc.v:152351.7-152351.23" + wire $1\xer_ca_ok[0:0] + attribute \src "libresoc.v:152596.3-152614.6" + wire width 2 $1\xer_ov$next[1:0]$8531 + attribute \src "libresoc.v:152358.13-152358.26" + wire width 2 $1\xer_ov[1:0] + attribute \src "libresoc.v:152596.3-152614.6" + wire $1\xer_ov_ok$next[0:0]$8532 + attribute \src "libresoc.v:152365.7-152365.23" + wire $1\xer_ov_ok[0:0] + attribute \src "libresoc.v:152615.3-152633.6" + wire $1\xer_so$next[0:0]$8537 + attribute \src "libresoc.v:152372.7-152372.20" + wire $1\xer_so[0:0] + attribute \src "libresoc.v:152615.3-152633.6" + wire $1\xer_so_ok$next[0:0]$8538 + attribute \src "libresoc.v:152381.7-152381.23" + wire $1\xer_so_ok[0:0] + attribute \src "libresoc.v:152665.3-152706.6" + wire width 64 $2\alu_op__imm_data__data$next[63:0]$8584 + attribute \src "libresoc.v:152665.3-152706.6" + wire $2\alu_op__imm_data__ok$next[0:0]$8585 + attribute \src "libresoc.v:152665.3-152706.6" + wire $2\alu_op__oe__oe$next[0:0]$8586 + attribute \src "libresoc.v:152665.3-152706.6" + wire $2\alu_op__oe__ok$next[0:0]$8587 + attribute \src "libresoc.v:152665.3-152706.6" + wire $2\alu_op__rc__ok$next[0:0]$8588 + attribute \src "libresoc.v:152665.3-152706.6" + wire $2\alu_op__rc__rc$next[0:0]$8589 + attribute \src "libresoc.v:152558.3-152576.6" + wire $2\cr_a_ok$next[0:0]$8521 + attribute \src "libresoc.v:152707.3-152725.6" + wire $2\o_ok$next[0:0]$8595 + attribute \src "libresoc.v:152634.3-152651.6" + wire $2\r_busy$next[0:0]$8543 + attribute \src "libresoc.v:152577.3-152595.6" + wire $2\xer_ca_ok$next[0:0]$8527 + attribute \src "libresoc.v:152596.3-152614.6" + wire $2\xer_ov_ok$next[0:0]$8533 + attribute \src "libresoc.v:152615.3-152633.6" + wire $2\xer_so_ok$next[0:0]$8539 + attribute \src "libresoc.v:152388.18-152388.118" + wire $and$libresoc.v:152388$8485_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + wire \$67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 21 \alu_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 52 \alu_op__data_len$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \alu_op__data_len$86 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \alu_op__data_len$next + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 output 6 \alu_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 37 \alu_op__fn_unit$3 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \alu_op__fn_unit$71 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \alu_op__fn_unit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 7 \alu_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 38 \alu_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \alu_op__imm_data__data$72 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \alu_op__imm_data__data$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 8 \alu_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 39 \alu_op__imm_data__ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__imm_data__ok$73 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__imm_data__ok$next + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 17 \alu_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 48 \alu_op__input_carry$14 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \alu_op__input_carry$82 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \alu_op__input_carry$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 22 \alu_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 53 \alu_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \alu_op__insn$87 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \alu_op__insn$next + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 5 \alu_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 36 \alu_op__insn_type$2 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \alu_op__insn_type$70 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \alu_op__insn_type$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 13 \alu_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 44 \alu_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__invert_in$78 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__invert_in$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 15 \alu_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 46 \alu_op__invert_out$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__invert_out$80 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__invert_out$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 19 \alu_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 50 \alu_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__is_32bit$84 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__is_32bit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 20 \alu_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 51 \alu_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__is_signed$85 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__is_signed$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 11 \alu_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__oe__oe$76 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 42 \alu_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__oe__oe$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 12 \alu_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__oe__ok$77 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 43 \alu_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__oe__ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 18 \alu_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 49 \alu_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__output_carry$83 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__output_carry$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 10 \alu_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 41 \alu_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__rc__ok$75 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__rc__ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 9 \alu_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 40 \alu_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__rc__rc$74 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__rc__rc$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 16 \alu_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 47 \alu_op__write_cr0$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__write_cr0$81 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__write_cr0$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 14 \alu_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 45 \alu_op__zero_a$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__zero_a$79 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__zero_a$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 58 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 output 25 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \cr_a$90 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \cr_a$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 26 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_a_ok$91 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_a_ok$next + attribute \src "libresoc.v:151281.7-151281.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \input_alu_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \input_alu_op__data_len$39 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \input_alu_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \input_alu_op__fn_unit$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \input_alu_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \input_alu_op__imm_data__data$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__imm_data__ok$26 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \input_alu_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \input_alu_op__input_carry$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \input_alu_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \input_alu_op__insn$40 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \input_alu_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \input_alu_op__insn_type$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__invert_in$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__invert_out$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__is_32bit$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__is_signed$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__oe__oe$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__oe__ok$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__output_carry$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__rc__ok$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__rc__rc$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__write_cr0$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__zero_a$32 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \input_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \input_muxid$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_ra$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_rb$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 \input_xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 \input_xer_ca$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \input_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \input_xer_so$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \main_alu_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \main_alu_op__data_len$62 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \main_alu_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \main_alu_op__fn_unit$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \main_alu_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \main_alu_op__imm_data__data$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__imm_data__ok$49 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \main_alu_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \main_alu_op__input_carry$58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \main_alu_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \main_alu_op__insn$63 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \main_alu_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \main_alu_op__insn_type$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__invert_in$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__invert_out$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__is_32bit$60 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__is_signed$61 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__oe__oe$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__oe__ok$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__output_carry$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__rc__ok$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__rc__rc$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__write_cr0$57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__zero_a$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \main_cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \main_cr_a_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \main_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \main_muxid$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \main_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \main_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \main_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \main_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 \main_xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \main_xer_ca$64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \main_xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \main_xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \main_xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \main_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \main_xer_so$65 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 4 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 35 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$69 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" + wire \n_i_rdy_data + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire input 3 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire output 2 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 23 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \o$88 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \o$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 24 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \o_ok$89 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \o_ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire output 34 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire input 33 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" + wire \p_valid_i$66 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire \r_busy$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 54 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 55 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 output 27 \xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 input 57 \xer_ca$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \xer_ca$92 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \xer_ca$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 28 \xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \xer_ca_ok$93 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \xer_ca_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 output 29 \xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \xer_ov$94 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \xer_ov$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 30 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \xer_ov_ok$95 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \xer_ov_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 31 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 56 \xer_so$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \xer_so$96 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \xer_so$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 32 \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \xer_so_ok$97 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \xer_so_ok$98 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \xer_so_ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + cell $and $and$libresoc.v:152388$8485 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i$66 + connect \B \p_ready_o + connect \Y $and$libresoc.v:152388$8485_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:152449.11-152496.4" + cell \input \input + connect \alu_op__data_len \input_alu_op__data_len + connect \alu_op__data_len$18 \input_alu_op__data_len$39 + connect \alu_op__fn_unit \input_alu_op__fn_unit + connect \alu_op__fn_unit$3 \input_alu_op__fn_unit$24 + connect \alu_op__imm_data__data \input_alu_op__imm_data__data + connect \alu_op__imm_data__data$4 \input_alu_op__imm_data__data$25 + connect \alu_op__imm_data__ok \input_alu_op__imm_data__ok + connect \alu_op__imm_data__ok$5 \input_alu_op__imm_data__ok$26 + connect \alu_op__input_carry \input_alu_op__input_carry + connect \alu_op__input_carry$14 \input_alu_op__input_carry$35 + connect \alu_op__insn \input_alu_op__insn + connect \alu_op__insn$19 \input_alu_op__insn$40 + connect \alu_op__insn_type \input_alu_op__insn_type + connect \alu_op__insn_type$2 \input_alu_op__insn_type$23 + connect \alu_op__invert_in \input_alu_op__invert_in + connect \alu_op__invert_in$10 \input_alu_op__invert_in$31 + connect \alu_op__invert_out \input_alu_op__invert_out + connect \alu_op__invert_out$12 \input_alu_op__invert_out$33 + connect \alu_op__is_32bit \input_alu_op__is_32bit + connect \alu_op__is_32bit$16 \input_alu_op__is_32bit$37 + connect \alu_op__is_signed \input_alu_op__is_signed + connect \alu_op__is_signed$17 \input_alu_op__is_signed$38 + connect \alu_op__oe__oe \input_alu_op__oe__oe + connect \alu_op__oe__oe$8 \input_alu_op__oe__oe$29 + connect \alu_op__oe__ok \input_alu_op__oe__ok + connect \alu_op__oe__ok$9 \input_alu_op__oe__ok$30 + connect \alu_op__output_carry \input_alu_op__output_carry + connect \alu_op__output_carry$15 \input_alu_op__output_carry$36 + connect \alu_op__rc__ok \input_alu_op__rc__ok + connect \alu_op__rc__ok$7 \input_alu_op__rc__ok$28 + connect \alu_op__rc__rc \input_alu_op__rc__rc + connect \alu_op__rc__rc$6 \input_alu_op__rc__rc$27 + connect \alu_op__write_cr0 \input_alu_op__write_cr0 + connect \alu_op__write_cr0$13 \input_alu_op__write_cr0$34 + connect \alu_op__zero_a \input_alu_op__zero_a + connect \alu_op__zero_a$11 \input_alu_op__zero_a$32 + connect \muxid \input_muxid + connect \muxid$1 \input_muxid$22 + connect \ra \input_ra + connect \ra$20 \input_ra$41 + connect \rb \input_rb + connect \rb$21 \input_rb$42 + connect \xer_ca \input_xer_ca + connect \xer_ca$23 \input_xer_ca$44 + connect \xer_so \input_xer_so + connect \xer_so$22 \input_xer_so$43 + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:152497.8-152549.4" + cell \main \main + connect \alu_op__data_len \main_alu_op__data_len + connect \alu_op__data_len$18 \main_alu_op__data_len$62 + connect \alu_op__fn_unit \main_alu_op__fn_unit + connect \alu_op__fn_unit$3 \main_alu_op__fn_unit$47 + connect \alu_op__imm_data__data \main_alu_op__imm_data__data + connect \alu_op__imm_data__data$4 \main_alu_op__imm_data__data$48 + connect \alu_op__imm_data__ok \main_alu_op__imm_data__ok + connect \alu_op__imm_data__ok$5 \main_alu_op__imm_data__ok$49 + connect \alu_op__input_carry \main_alu_op__input_carry + connect \alu_op__input_carry$14 \main_alu_op__input_carry$58 + connect \alu_op__insn \main_alu_op__insn + connect \alu_op__insn$19 \main_alu_op__insn$63 + connect \alu_op__insn_type \main_alu_op__insn_type + connect \alu_op__insn_type$2 \main_alu_op__insn_type$46 + connect \alu_op__invert_in \main_alu_op__invert_in + connect \alu_op__invert_in$10 \main_alu_op__invert_in$54 + connect \alu_op__invert_out \main_alu_op__invert_out + connect \alu_op__invert_out$12 \main_alu_op__invert_out$56 + connect \alu_op__is_32bit \main_alu_op__is_32bit + connect \alu_op__is_32bit$16 \main_alu_op__is_32bit$60 + connect \alu_op__is_signed \main_alu_op__is_signed + connect \alu_op__is_signed$17 \main_alu_op__is_signed$61 + connect \alu_op__oe__oe \main_alu_op__oe__oe + connect \alu_op__oe__oe$8 \main_alu_op__oe__oe$52 + connect \alu_op__oe__ok \main_alu_op__oe__ok + connect \alu_op__oe__ok$9 \main_alu_op__oe__ok$53 + connect \alu_op__output_carry \main_alu_op__output_carry + connect \alu_op__output_carry$15 \main_alu_op__output_carry$59 + connect \alu_op__rc__ok \main_alu_op__rc__ok + connect \alu_op__rc__ok$7 \main_alu_op__rc__ok$51 + connect \alu_op__rc__rc \main_alu_op__rc__rc + connect \alu_op__rc__rc$6 \main_alu_op__rc__rc$50 + connect \alu_op__write_cr0 \main_alu_op__write_cr0 + connect \alu_op__write_cr0$13 \main_alu_op__write_cr0$57 + connect \alu_op__zero_a \main_alu_op__zero_a + connect \alu_op__zero_a$11 \main_alu_op__zero_a$55 + connect \cr_a \main_cr_a + connect \cr_a_ok \main_cr_a_ok + connect \muxid \main_muxid + connect \muxid$1 \main_muxid$45 + connect \o \main_o + connect \o_ok \main_o_ok + connect \ra \main_ra + connect \rb \main_rb + connect \xer_ca \main_xer_ca + connect \xer_ca$20 \main_xer_ca$64 + connect \xer_ca_ok \main_xer_ca_ok + connect \xer_ov \main_xer_ov + connect \xer_ov_ok \main_xer_ov_ok + connect \xer_so \main_xer_so + connect \xer_so$21 \main_xer_so$65 + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:152550.9-152553.4" + cell \n$2 \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:152554.9-152557.4" + cell \p$1 \p + connect \p_ready_o \p_ready_o + connect \p_valid_i \p_valid_i + end + attribute \src "libresoc.v:151281.7-151281.20" + process $proc$libresoc.v:151281$8596 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:151286.13-151286.36" + process $proc$libresoc.v:151286$8597 + assign { } { } + assign $1\alu_op__data_len[3:0] 4'0000 + sync always + sync init + update \alu_op__data_len $1\alu_op__data_len[3:0] + end + attribute \src "libresoc.v:151308.14-151308.39" + process $proc$libresoc.v:151308$8598 + assign { } { } + assign $1\alu_op__fn_unit[11:0] 12'000000000000 + sync always + sync init + update \alu_op__fn_unit $1\alu_op__fn_unit[11:0] + end + attribute \src "libresoc.v:151343.14-151343.59" + process $proc$libresoc.v:151343$8599 + assign { } { } + assign $1\alu_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \alu_op__imm_data__data $1\alu_op__imm_data__data[63:0] + end + attribute \src "libresoc.v:151352.7-151352.34" + process $proc$libresoc.v:151352$8600 + assign { } { } + assign $1\alu_op__imm_data__ok[0:0] 1'0 + sync always + sync init + update \alu_op__imm_data__ok $1\alu_op__imm_data__ok[0:0] + end + attribute \src "libresoc.v:151365.13-151365.39" + process $proc$libresoc.v:151365$8601 + assign { } { } + assign $1\alu_op__input_carry[1:0] 2'00 + sync always + sync init + update \alu_op__input_carry $1\alu_op__input_carry[1:0] + end + attribute \src "libresoc.v:151382.14-151382.34" + process $proc$libresoc.v:151382$8602 + assign { } { } + assign $1\alu_op__insn[31:0] 0 + sync always + sync init + update \alu_op__insn $1\alu_op__insn[31:0] + end + attribute \src "libresoc.v:151465.13-151465.38" + process $proc$libresoc.v:151465$8603 + assign { } { } + assign $1\alu_op__insn_type[6:0] 7'0000000 + sync always + sync init + update \alu_op__insn_type $1\alu_op__insn_type[6:0] + end + attribute \src "libresoc.v:151622.7-151622.31" + process $proc$libresoc.v:151622$8604 + assign { } { } + assign $1\alu_op__invert_in[0:0] 1'0 + sync always + sync init + update \alu_op__invert_in $1\alu_op__invert_in[0:0] + end + attribute \src "libresoc.v:151631.7-151631.32" + process $proc$libresoc.v:151631$8605 + assign { } { } + assign $1\alu_op__invert_out[0:0] 1'0 + sync always + sync init + update \alu_op__invert_out $1\alu_op__invert_out[0:0] + end + attribute \src "libresoc.v:151640.7-151640.30" + process $proc$libresoc.v:151640$8606 + assign { } { } + assign $1\alu_op__is_32bit[0:0] 1'0 + sync always + sync init + update \alu_op__is_32bit $1\alu_op__is_32bit[0:0] + end + attribute \src "libresoc.v:151649.7-151649.31" + process $proc$libresoc.v:151649$8607 + assign { } { } + assign $1\alu_op__is_signed[0:0] 1'0 + sync always + sync init + update \alu_op__is_signed $1\alu_op__is_signed[0:0] + end + attribute \src "libresoc.v:151658.7-151658.28" + process $proc$libresoc.v:151658$8608 + assign { } { } + assign $1\alu_op__oe__oe[0:0] 1'0 + sync always + sync init + update \alu_op__oe__oe $1\alu_op__oe__oe[0:0] + end + attribute \src "libresoc.v:151667.7-151667.28" + process $proc$libresoc.v:151667$8609 + assign { } { } + assign $1\alu_op__oe__ok[0:0] 1'0 + sync always + sync init + update \alu_op__oe__ok $1\alu_op__oe__ok[0:0] + end + attribute \src "libresoc.v:151676.7-151676.34" + process $proc$libresoc.v:151676$8610 + assign { } { } + assign $1\alu_op__output_carry[0:0] 1'0 + sync always + sync init + update \alu_op__output_carry $1\alu_op__output_carry[0:0] + end + attribute \src "libresoc.v:151685.7-151685.28" + process $proc$libresoc.v:151685$8611 + assign { } { } + assign $1\alu_op__rc__ok[0:0] 1'0 + sync always + sync init + update \alu_op__rc__ok $1\alu_op__rc__ok[0:0] + end + attribute \src "libresoc.v:151694.7-151694.28" + process $proc$libresoc.v:151694$8612 + assign { } { } + assign $1\alu_op__rc__rc[0:0] 1'0 + sync always + sync init + update \alu_op__rc__rc $1\alu_op__rc__rc[0:0] + end + attribute \src "libresoc.v:151703.7-151703.31" + process $proc$libresoc.v:151703$8613 + assign { } { } + assign $1\alu_op__write_cr0[0:0] 1'0 + sync always + sync init + update \alu_op__write_cr0 $1\alu_op__write_cr0[0:0] + end + attribute \src "libresoc.v:151712.7-151712.28" + process $proc$libresoc.v:151712$8614 + assign { } { } + assign $1\alu_op__zero_a[0:0] 1'0 + sync always + sync init + update \alu_op__zero_a $1\alu_op__zero_a[0:0] + end + attribute \src "libresoc.v:151725.13-151725.24" + process $proc$libresoc.v:151725$8615 + assign { } { } + assign $1\cr_a[3:0] 4'0000 + sync always + sync init + update \cr_a $1\cr_a[3:0] + end + attribute \src "libresoc.v:151732.7-151732.21" + process $proc$libresoc.v:151732$8616 + assign { } { } + assign $1\cr_a_ok[0:0] 1'0 + sync always + sync init + update \cr_a_ok $1\cr_a_ok[0:0] + end + attribute \src "libresoc.v:152297.13-152297.25" + process $proc$libresoc.v:152297$8617 + assign { } { } + assign $1\muxid[1:0] 2'00 + sync always + sync init + update \muxid $1\muxid[1:0] + end + attribute \src "libresoc.v:152312.14-152312.38" + process $proc$libresoc.v:152312$8618 + assign { } { } + assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \o $1\o[63:0] + end + attribute \src "libresoc.v:152319.7-152319.18" + process $proc$libresoc.v:152319$8619 + assign { } { } + assign $1\o_ok[0:0] 1'0 + sync always + sync init + update \o_ok $1\o_ok[0:0] + end + attribute \src "libresoc.v:152333.7-152333.20" + process $proc$libresoc.v:152333$8620 + assign { } { } + assign $1\r_busy[0:0] 1'0 + sync always + sync init + update \r_busy $1\r_busy[0:0] + end + attribute \src "libresoc.v:152342.13-152342.26" + process $proc$libresoc.v:152342$8621 + assign { } { } + assign $1\xer_ca[1:0] 2'00 + sync always + sync init + update \xer_ca $1\xer_ca[1:0] + end + attribute \src "libresoc.v:152351.7-152351.23" + process $proc$libresoc.v:152351$8622 + assign { } { } + assign $1\xer_ca_ok[0:0] 1'0 + sync always + sync init + update \xer_ca_ok $1\xer_ca_ok[0:0] + end + attribute \src "libresoc.v:152358.13-152358.26" + process $proc$libresoc.v:152358$8623 + assign { } { } + assign $1\xer_ov[1:0] 2'00 + sync always + sync init + update \xer_ov $1\xer_ov[1:0] + end + attribute \src "libresoc.v:152365.7-152365.23" + process $proc$libresoc.v:152365$8624 + assign { } { } + assign $1\xer_ov_ok[0:0] 1'0 + sync always + sync init + update \xer_ov_ok $1\xer_ov_ok[0:0] + end + attribute \src "libresoc.v:152372.7-152372.20" + process $proc$libresoc.v:152372$8625 + assign { } { } + assign $1\xer_so[0:0] 1'0 + sync always + sync init + update \xer_so $1\xer_so[0:0] + end + attribute \src "libresoc.v:152381.7-152381.23" + process $proc$libresoc.v:152381$8626 + assign { } { } + assign $1\xer_so_ok[0:0] 1'0 + sync always + sync init + update \xer_so_ok $1\xer_so_ok[0:0] + end + attribute \src "libresoc.v:152389.3-152390.29" + process $proc$libresoc.v:152389$8486 + assign { } { } + assign $0\xer_so[0:0] \xer_so$next + sync posedge \coresync_clk + update \xer_so $0\xer_so[0:0] + end + attribute \src "libresoc.v:152391.3-152392.35" + process $proc$libresoc.v:152391$8487 + assign { } { } + assign $0\xer_so_ok[0:0] \xer_so_ok$next + sync posedge \coresync_clk + update \xer_so_ok $0\xer_so_ok[0:0] + end + attribute \src "libresoc.v:152393.3-152394.29" + process $proc$libresoc.v:152393$8488 + assign { } { } + assign $0\xer_ov[1:0] \xer_ov$next + sync posedge \coresync_clk + update \xer_ov $0\xer_ov[1:0] + end + attribute \src "libresoc.v:152395.3-152396.35" + process $proc$libresoc.v:152395$8489 + assign { } { } + assign $0\xer_ov_ok[0:0] \xer_ov_ok$next + sync posedge \coresync_clk + update \xer_ov_ok $0\xer_ov_ok[0:0] + end + attribute \src "libresoc.v:152397.3-152398.29" + process $proc$libresoc.v:152397$8490 + assign { } { } + assign $0\xer_ca[1:0] \xer_ca$next + sync posedge \coresync_clk + update \xer_ca $0\xer_ca[1:0] + end + attribute \src "libresoc.v:152399.3-152400.35" + process $proc$libresoc.v:152399$8491 + assign { } { } + assign $0\xer_ca_ok[0:0] \xer_ca_ok$next + sync posedge \coresync_clk + update \xer_ca_ok $0\xer_ca_ok[0:0] + end + attribute \src "libresoc.v:152401.3-152402.25" + process $proc$libresoc.v:152401$8492 + assign { } { } + assign $0\cr_a[3:0] \cr_a$next + sync posedge \coresync_clk + update \cr_a $0\cr_a[3:0] + end + attribute \src "libresoc.v:152403.3-152404.31" + process $proc$libresoc.v:152403$8493 + assign { } { } + assign $0\cr_a_ok[0:0] \cr_a_ok$next + sync posedge \coresync_clk + update \cr_a_ok $0\cr_a_ok[0:0] + end + attribute \src "libresoc.v:152405.3-152406.19" + process $proc$libresoc.v:152405$8494 + assign { } { } + assign $0\o[63:0] \o$next + sync posedge \coresync_clk + update \o $0\o[63:0] + end + attribute \src "libresoc.v:152407.3-152408.25" + process $proc$libresoc.v:152407$8495 + assign { } { } + assign $0\o_ok[0:0] \o_ok$next + sync posedge \coresync_clk + update \o_ok $0\o_ok[0:0] + end + attribute \src "libresoc.v:152409.3-152410.51" + process $proc$libresoc.v:152409$8496 + assign { } { } + assign $0\alu_op__insn_type[6:0] \alu_op__insn_type$next + sync posedge \coresync_clk + update \alu_op__insn_type $0\alu_op__insn_type[6:0] + end + attribute \src "libresoc.v:152411.3-152412.47" + process $proc$libresoc.v:152411$8497 + assign { } { } + assign $0\alu_op__fn_unit[11:0] \alu_op__fn_unit$next + sync posedge \coresync_clk + update \alu_op__fn_unit $0\alu_op__fn_unit[11:0] + end + attribute \src "libresoc.v:152413.3-152414.61" + process $proc$libresoc.v:152413$8498 + assign { } { } + assign $0\alu_op__imm_data__data[63:0] \alu_op__imm_data__data$next + sync posedge \coresync_clk + update \alu_op__imm_data__data $0\alu_op__imm_data__data[63:0] + end + attribute \src "libresoc.v:152415.3-152416.57" + process $proc$libresoc.v:152415$8499 + assign { } { } + assign $0\alu_op__imm_data__ok[0:0] \alu_op__imm_data__ok$next + sync posedge \coresync_clk + update \alu_op__imm_data__ok $0\alu_op__imm_data__ok[0:0] + end + attribute \src "libresoc.v:152417.3-152418.45" + process $proc$libresoc.v:152417$8500 + assign { } { } + assign $0\alu_op__rc__rc[0:0] \alu_op__rc__rc$next + sync posedge \coresync_clk + update \alu_op__rc__rc $0\alu_op__rc__rc[0:0] + end + attribute \src "libresoc.v:152419.3-152420.45" + process $proc$libresoc.v:152419$8501 + assign { } { } + assign $0\alu_op__rc__ok[0:0] \alu_op__rc__ok$next + sync posedge \coresync_clk + update \alu_op__rc__ok $0\alu_op__rc__ok[0:0] + end + attribute \src "libresoc.v:152421.3-152422.45" + process $proc$libresoc.v:152421$8502 + assign { } { } + assign $0\alu_op__oe__oe[0:0] \alu_op__oe__oe$next + sync posedge \coresync_clk + update \alu_op__oe__oe $0\alu_op__oe__oe[0:0] + end + attribute \src "libresoc.v:152423.3-152424.45" + process $proc$libresoc.v:152423$8503 + assign { } { } + assign $0\alu_op__oe__ok[0:0] \alu_op__oe__ok$next + sync posedge \coresync_clk + update \alu_op__oe__ok $0\alu_op__oe__ok[0:0] + end + attribute \src "libresoc.v:152425.3-152426.51" + process $proc$libresoc.v:152425$8504 + assign { } { } + assign $0\alu_op__invert_in[0:0] \alu_op__invert_in$next + sync posedge \coresync_clk + update \alu_op__invert_in $0\alu_op__invert_in[0:0] + end + attribute \src "libresoc.v:152427.3-152428.45" + process $proc$libresoc.v:152427$8505 + assign { } { } + assign $0\alu_op__zero_a[0:0] \alu_op__zero_a$next + sync posedge \coresync_clk + update \alu_op__zero_a $0\alu_op__zero_a[0:0] + end + attribute \src "libresoc.v:152429.3-152430.53" + process $proc$libresoc.v:152429$8506 + assign { } { } + assign $0\alu_op__invert_out[0:0] \alu_op__invert_out$next + sync posedge \coresync_clk + update \alu_op__invert_out $0\alu_op__invert_out[0:0] + end + attribute \src "libresoc.v:152431.3-152432.51" + process $proc$libresoc.v:152431$8507 + assign { } { } + assign $0\alu_op__write_cr0[0:0] \alu_op__write_cr0$next + sync posedge \coresync_clk + update \alu_op__write_cr0 $0\alu_op__write_cr0[0:0] + end + attribute \src "libresoc.v:152433.3-152434.55" + process $proc$libresoc.v:152433$8508 + assign { } { } + assign $0\alu_op__input_carry[1:0] \alu_op__input_carry$next + sync posedge \coresync_clk + update \alu_op__input_carry $0\alu_op__input_carry[1:0] + end + attribute \src "libresoc.v:152435.3-152436.57" + process $proc$libresoc.v:152435$8509 + assign { } { } + assign $0\alu_op__output_carry[0:0] \alu_op__output_carry$next + sync posedge \coresync_clk + update \alu_op__output_carry $0\alu_op__output_carry[0:0] + end + attribute \src "libresoc.v:152437.3-152438.49" + process $proc$libresoc.v:152437$8510 + assign { } { } + assign $0\alu_op__is_32bit[0:0] \alu_op__is_32bit$next + sync posedge \coresync_clk + update \alu_op__is_32bit $0\alu_op__is_32bit[0:0] + end + attribute \src "libresoc.v:152439.3-152440.51" + process $proc$libresoc.v:152439$8511 + assign { } { } + assign $0\alu_op__is_signed[0:0] \alu_op__is_signed$next + sync posedge \coresync_clk + update \alu_op__is_signed $0\alu_op__is_signed[0:0] + end + attribute \src "libresoc.v:152441.3-152442.49" + process $proc$libresoc.v:152441$8512 + assign { } { } + assign $0\alu_op__data_len[3:0] \alu_op__data_len$next + sync posedge \coresync_clk + update \alu_op__data_len $0\alu_op__data_len[3:0] + end + attribute \src "libresoc.v:152443.3-152444.41" + process $proc$libresoc.v:152443$8513 + assign { } { } + assign $0\alu_op__insn[31:0] \alu_op__insn$next + sync posedge \coresync_clk + update \alu_op__insn $0\alu_op__insn[31:0] + end + attribute \src "libresoc.v:152445.3-152446.27" + process $proc$libresoc.v:152445$8514 + assign { } { } + assign $0\muxid[1:0] \muxid$next + sync posedge \coresync_clk + update \muxid $0\muxid[1:0] + end + attribute \src "libresoc.v:152447.3-152448.29" + process $proc$libresoc.v:152447$8515 + assign { } { } + assign $0\r_busy[0:0] \r_busy$next + sync posedge \coresync_clk + update \r_busy $0\r_busy[0:0] + end + attribute \src "libresoc.v:152558.3-152576.6" + process $proc$libresoc.v:152558$8516 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\cr_a$next[3:0]$8517 $1\cr_a$next[3:0]$8519 + assign { } { } + assign $0\cr_a_ok$next[0:0]$8518 $2\cr_a_ok$next[0:0]$8521 + attribute \src "libresoc.v:152559.5-152559.29" + switch \initial + attribute \src "libresoc.v:152559.9-152559.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\cr_a_ok$next[0:0]$8520 $1\cr_a$next[3:0]$8519 } { \cr_a_ok$91 \cr_a$90 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\cr_a_ok$next[0:0]$8520 $1\cr_a$next[3:0]$8519 } { \cr_a_ok$91 \cr_a$90 } + case + assign $1\cr_a$next[3:0]$8519 \cr_a + assign $1\cr_a_ok$next[0:0]$8520 \cr_a_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_a_ok$next[0:0]$8521 1'0 + case + assign $2\cr_a_ok$next[0:0]$8521 $1\cr_a_ok$next[0:0]$8520 + end + sync always + update \cr_a$next $0\cr_a$next[3:0]$8517 + update \cr_a_ok$next $0\cr_a_ok$next[0:0]$8518 + end + attribute \src "libresoc.v:152577.3-152595.6" + process $proc$libresoc.v:152577$8522 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\xer_ca$next[1:0]$8524 $1\xer_ca$next[1:0]$8526 + assign $0\xer_ca_ok$next[0:0]$8523 $2\xer_ca_ok$next[0:0]$8527 + attribute \src "libresoc.v:152578.5-152578.29" + switch \initial + attribute \src "libresoc.v:152578.9-152578.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\xer_ca_ok$next[0:0]$8525 $1\xer_ca$next[1:0]$8526 } { \xer_ca_ok$93 \xer_ca$92 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\xer_ca_ok$next[0:0]$8525 $1\xer_ca$next[1:0]$8526 } { \xer_ca_ok$93 \xer_ca$92 } + case + assign $1\xer_ca_ok$next[0:0]$8525 \xer_ca_ok + assign $1\xer_ca$next[1:0]$8526 \xer_ca + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\xer_ca_ok$next[0:0]$8527 1'0 + case + assign $2\xer_ca_ok$next[0:0]$8527 $1\xer_ca_ok$next[0:0]$8525 + end + sync always + update \xer_ca_ok$next $0\xer_ca_ok$next[0:0]$8523 + update \xer_ca$next $0\xer_ca$next[1:0]$8524 + end + attribute \src "libresoc.v:152596.3-152614.6" + process $proc$libresoc.v:152596$8528 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\xer_ov$next[1:0]$8529 $1\xer_ov$next[1:0]$8531 + assign { } { } + assign $0\xer_ov_ok$next[0:0]$8530 $2\xer_ov_ok$next[0:0]$8533 + attribute \src "libresoc.v:152597.5-152597.29" + switch \initial + attribute \src "libresoc.v:152597.9-152597.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\xer_ov_ok$next[0:0]$8532 $1\xer_ov$next[1:0]$8531 } { \xer_ov_ok$95 \xer_ov$94 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\xer_ov_ok$next[0:0]$8532 $1\xer_ov$next[1:0]$8531 } { \xer_ov_ok$95 \xer_ov$94 } + case + assign $1\xer_ov$next[1:0]$8531 \xer_ov + assign $1\xer_ov_ok$next[0:0]$8532 \xer_ov_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\xer_ov_ok$next[0:0]$8533 1'0 + case + assign $2\xer_ov_ok$next[0:0]$8533 $1\xer_ov_ok$next[0:0]$8532 + end + sync always + update \xer_ov$next $0\xer_ov$next[1:0]$8529 + update \xer_ov_ok$next $0\xer_ov_ok$next[0:0]$8530 + end + attribute \src "libresoc.v:152615.3-152633.6" + process $proc$libresoc.v:152615$8534 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\xer_so$next[0:0]$8535 $1\xer_so$next[0:0]$8537 + assign { } { } + assign $0\xer_so_ok$next[0:0]$8536 $2\xer_so_ok$next[0:0]$8539 + attribute \src "libresoc.v:152616.5-152616.29" + switch \initial + attribute \src "libresoc.v:152616.9-152616.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\xer_so_ok$next[0:0]$8538 $1\xer_so$next[0:0]$8537 } { \xer_so_ok$97 \xer_so$96 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\xer_so_ok$next[0:0]$8538 $1\xer_so$next[0:0]$8537 } { \xer_so_ok$97 \xer_so$96 } + case + assign $1\xer_so$next[0:0]$8537 \xer_so + assign $1\xer_so_ok$next[0:0]$8538 \xer_so_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\xer_so_ok$next[0:0]$8539 1'0 + case + assign $2\xer_so_ok$next[0:0]$8539 $1\xer_so_ok$next[0:0]$8538 + end + sync always + update \xer_so$next $0\xer_so$next[0:0]$8535 + update \xer_so_ok$next $0\xer_so_ok$next[0:0]$8536 + end + attribute \src "libresoc.v:152634.3-152651.6" + process $proc$libresoc.v:152634$8540 + assign { } { } + assign { } { } + assign { } { } + assign $0\r_busy$next[0:0]$8541 $2\r_busy$next[0:0]$8543 + attribute \src "libresoc.v:152635.5-152635.29" + switch \initial + attribute \src "libresoc.v:152635.9-152635.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\r_busy$next[0:0]$8542 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\r_busy$next[0:0]$8542 1'0 + case + assign $1\r_busy$next[0:0]$8542 \r_busy + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r_busy$next[0:0]$8543 1'0 + case + assign $2\r_busy$next[0:0]$8543 $1\r_busy$next[0:0]$8542 + end + sync always + update \r_busy$next $0\r_busy$next[0:0]$8541 + end + attribute \src "libresoc.v:152652.3-152664.6" + process $proc$libresoc.v:152652$8544 + assign { } { } + assign { } { } + assign $0\muxid$next[1:0]$8545 $1\muxid$next[1:0]$8546 + attribute \src "libresoc.v:152653.5-152653.29" + switch \initial + attribute \src "libresoc.v:152653.9-152653.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\muxid$next[1:0]$8546 \muxid$69 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\muxid$next[1:0]$8546 \muxid$69 + case + assign $1\muxid$next[1:0]$8546 \muxid + end + sync always + update \muxid$next $0\muxid$next[1:0]$8545 + end + attribute \src "libresoc.v:152665.3-152706.6" + process $proc$libresoc.v:152665$8547 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\alu_op__data_len$next[3:0]$8548 $1\alu_op__data_len$next[3:0]$8566 + assign $0\alu_op__fn_unit$next[11:0]$8549 $1\alu_op__fn_unit$next[11:0]$8567 + assign { } { } + assign { } { } + assign $0\alu_op__input_carry$next[1:0]$8552 $1\alu_op__input_carry$next[1:0]$8570 + assign $0\alu_op__insn$next[31:0]$8553 $1\alu_op__insn$next[31:0]$8571 + assign $0\alu_op__insn_type$next[6:0]$8554 $1\alu_op__insn_type$next[6:0]$8572 + assign $0\alu_op__invert_in$next[0:0]$8555 $1\alu_op__invert_in$next[0:0]$8573 + assign $0\alu_op__invert_out$next[0:0]$8556 $1\alu_op__invert_out$next[0:0]$8574 + assign $0\alu_op__is_32bit$next[0:0]$8557 $1\alu_op__is_32bit$next[0:0]$8575 + assign $0\alu_op__is_signed$next[0:0]$8558 $1\alu_op__is_signed$next[0:0]$8576 + assign { } { } + assign { } { } + assign $0\alu_op__output_carry$next[0:0]$8561 $1\alu_op__output_carry$next[0:0]$8579 + assign { } { } + assign { } { } + assign $0\alu_op__write_cr0$next[0:0]$8564 $1\alu_op__write_cr0$next[0:0]$8582 + assign $0\alu_op__zero_a$next[0:0]$8565 $1\alu_op__zero_a$next[0:0]$8583 + assign $0\alu_op__imm_data__data$next[63:0]$8550 $2\alu_op__imm_data__data$next[63:0]$8584 + assign $0\alu_op__imm_data__ok$next[0:0]$8551 $2\alu_op__imm_data__ok$next[0:0]$8585 + assign $0\alu_op__oe__oe$next[0:0]$8559 $2\alu_op__oe__oe$next[0:0]$8586 + assign $0\alu_op__oe__ok$next[0:0]$8560 $2\alu_op__oe__ok$next[0:0]$8587 + assign $0\alu_op__rc__ok$next[0:0]$8562 $2\alu_op__rc__ok$next[0:0]$8588 + assign $0\alu_op__rc__rc$next[0:0]$8563 $2\alu_op__rc__rc$next[0:0]$8589 + attribute \src "libresoc.v:152666.5-152666.29" + switch \initial + attribute \src "libresoc.v:152666.9-152666.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\alu_op__insn$next[31:0]$8571 $1\alu_op__data_len$next[3:0]$8566 $1\alu_op__is_signed$next[0:0]$8576 $1\alu_op__is_32bit$next[0:0]$8575 $1\alu_op__output_carry$next[0:0]$8579 $1\alu_op__input_carry$next[1:0]$8570 $1\alu_op__write_cr0$next[0:0]$8582 $1\alu_op__invert_out$next[0:0]$8574 $1\alu_op__zero_a$next[0:0]$8583 $1\alu_op__invert_in$next[0:0]$8573 $1\alu_op__oe__ok$next[0:0]$8578 $1\alu_op__oe__oe$next[0:0]$8577 $1\alu_op__rc__ok$next[0:0]$8580 $1\alu_op__rc__rc$next[0:0]$8581 $1\alu_op__imm_data__ok$next[0:0]$8569 $1\alu_op__imm_data__data$next[63:0]$8568 $1\alu_op__fn_unit$next[11:0]$8567 $1\alu_op__insn_type$next[6:0]$8572 } { \alu_op__insn$87 \alu_op__data_len$86 \alu_op__is_signed$85 \alu_op__is_32bit$84 \alu_op__output_carry$83 \alu_op__input_carry$82 \alu_op__write_cr0$81 \alu_op__invert_out$80 \alu_op__zero_a$79 \alu_op__invert_in$78 \alu_op__oe__ok$77 \alu_op__oe__oe$76 \alu_op__rc__ok$75 \alu_op__rc__rc$74 \alu_op__imm_data__ok$73 \alu_op__imm_data__data$72 \alu_op__fn_unit$71 \alu_op__insn_type$70 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\alu_op__insn$next[31:0]$8571 $1\alu_op__data_len$next[3:0]$8566 $1\alu_op__is_signed$next[0:0]$8576 $1\alu_op__is_32bit$next[0:0]$8575 $1\alu_op__output_carry$next[0:0]$8579 $1\alu_op__input_carry$next[1:0]$8570 $1\alu_op__write_cr0$next[0:0]$8582 $1\alu_op__invert_out$next[0:0]$8574 $1\alu_op__zero_a$next[0:0]$8583 $1\alu_op__invert_in$next[0:0]$8573 $1\alu_op__oe__ok$next[0:0]$8578 $1\alu_op__oe__oe$next[0:0]$8577 $1\alu_op__rc__ok$next[0:0]$8580 $1\alu_op__rc__rc$next[0:0]$8581 $1\alu_op__imm_data__ok$next[0:0]$8569 $1\alu_op__imm_data__data$next[63:0]$8568 $1\alu_op__fn_unit$next[11:0]$8567 $1\alu_op__insn_type$next[6:0]$8572 } { \alu_op__insn$87 \alu_op__data_len$86 \alu_op__is_signed$85 \alu_op__is_32bit$84 \alu_op__output_carry$83 \alu_op__input_carry$82 \alu_op__write_cr0$81 \alu_op__invert_out$80 \alu_op__zero_a$79 \alu_op__invert_in$78 \alu_op__oe__ok$77 \alu_op__oe__oe$76 \alu_op__rc__ok$75 \alu_op__rc__rc$74 \alu_op__imm_data__ok$73 \alu_op__imm_data__data$72 \alu_op__fn_unit$71 \alu_op__insn_type$70 } + case + assign $1\alu_op__data_len$next[3:0]$8566 \alu_op__data_len + assign $1\alu_op__fn_unit$next[11:0]$8567 \alu_op__fn_unit + assign $1\alu_op__imm_data__data$next[63:0]$8568 \alu_op__imm_data__data + assign $1\alu_op__imm_data__ok$next[0:0]$8569 \alu_op__imm_data__ok + assign $1\alu_op__input_carry$next[1:0]$8570 \alu_op__input_carry + assign $1\alu_op__insn$next[31:0]$8571 \alu_op__insn + assign $1\alu_op__insn_type$next[6:0]$8572 \alu_op__insn_type + assign $1\alu_op__invert_in$next[0:0]$8573 \alu_op__invert_in + assign $1\alu_op__invert_out$next[0:0]$8574 \alu_op__invert_out + assign $1\alu_op__is_32bit$next[0:0]$8575 \alu_op__is_32bit + assign $1\alu_op__is_signed$next[0:0]$8576 \alu_op__is_signed + assign $1\alu_op__oe__oe$next[0:0]$8577 \alu_op__oe__oe + assign $1\alu_op__oe__ok$next[0:0]$8578 \alu_op__oe__ok + assign $1\alu_op__output_carry$next[0:0]$8579 \alu_op__output_carry + assign $1\alu_op__rc__ok$next[0:0]$8580 \alu_op__rc__ok + assign $1\alu_op__rc__rc$next[0:0]$8581 \alu_op__rc__rc + assign $1\alu_op__write_cr0$next[0:0]$8582 \alu_op__write_cr0 + assign $1\alu_op__zero_a$next[0:0]$8583 \alu_op__zero_a + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $2\alu_op__imm_data__data$next[63:0]$8584 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\alu_op__imm_data__ok$next[0:0]$8585 1'0 + assign $2\alu_op__rc__rc$next[0:0]$8589 1'0 + assign $2\alu_op__rc__ok$next[0:0]$8588 1'0 + assign $2\alu_op__oe__oe$next[0:0]$8586 1'0 + assign $2\alu_op__oe__ok$next[0:0]$8587 1'0 + case + assign $2\alu_op__imm_data__data$next[63:0]$8584 $1\alu_op__imm_data__data$next[63:0]$8568 + assign $2\alu_op__imm_data__ok$next[0:0]$8585 $1\alu_op__imm_data__ok$next[0:0]$8569 + assign $2\alu_op__oe__oe$next[0:0]$8586 $1\alu_op__oe__oe$next[0:0]$8577 + assign $2\alu_op__oe__ok$next[0:0]$8587 $1\alu_op__oe__ok$next[0:0]$8578 + assign $2\alu_op__rc__ok$next[0:0]$8588 $1\alu_op__rc__ok$next[0:0]$8580 + assign $2\alu_op__rc__rc$next[0:0]$8589 $1\alu_op__rc__rc$next[0:0]$8581 + end + sync always + update \alu_op__data_len$next $0\alu_op__data_len$next[3:0]$8548 + update \alu_op__fn_unit$next $0\alu_op__fn_unit$next[11:0]$8549 + update \alu_op__imm_data__data$next $0\alu_op__imm_data__data$next[63:0]$8550 + update \alu_op__imm_data__ok$next $0\alu_op__imm_data__ok$next[0:0]$8551 + update \alu_op__input_carry$next $0\alu_op__input_carry$next[1:0]$8552 + update \alu_op__insn$next $0\alu_op__insn$next[31:0]$8553 + update \alu_op__insn_type$next $0\alu_op__insn_type$next[6:0]$8554 + update \alu_op__invert_in$next $0\alu_op__invert_in$next[0:0]$8555 + update \alu_op__invert_out$next $0\alu_op__invert_out$next[0:0]$8556 + update \alu_op__is_32bit$next $0\alu_op__is_32bit$next[0:0]$8557 + update \alu_op__is_signed$next $0\alu_op__is_signed$next[0:0]$8558 + update \alu_op__oe__oe$next $0\alu_op__oe__oe$next[0:0]$8559 + update \alu_op__oe__ok$next $0\alu_op__oe__ok$next[0:0]$8560 + update \alu_op__output_carry$next $0\alu_op__output_carry$next[0:0]$8561 + update \alu_op__rc__ok$next $0\alu_op__rc__ok$next[0:0]$8562 + update \alu_op__rc__rc$next $0\alu_op__rc__rc$next[0:0]$8563 + update \alu_op__write_cr0$next $0\alu_op__write_cr0$next[0:0]$8564 + update \alu_op__zero_a$next $0\alu_op__zero_a$next[0:0]$8565 + end + attribute \src "libresoc.v:152707.3-152725.6" + process $proc$libresoc.v:152707$8590 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\o$next[63:0]$8591 $1\o$next[63:0]$8593 + assign { } { } + assign $0\o_ok$next[0:0]$8592 $2\o_ok$next[0:0]$8595 + attribute \src "libresoc.v:152708.5-152708.29" + switch \initial + attribute \src "libresoc.v:152708.9-152708.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\o_ok$next[0:0]$8594 $1\o$next[63:0]$8593 } { \o_ok$89 \o$88 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\o_ok$next[0:0]$8594 $1\o$next[63:0]$8593 } { \o_ok$89 \o$88 } + case + assign $1\o$next[63:0]$8593 \o + assign $1\o_ok$next[0:0]$8594 \o_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\o_ok$next[0:0]$8595 1'0 + case + assign $2\o_ok$next[0:0]$8595 $1\o_ok$next[0:0]$8594 + end + sync always + update \o$next $0\o$next[63:0]$8591 + update \o_ok$next $0\o_ok$next[0:0]$8592 + end + connect \$67 $and$libresoc.v:152388$8485_Y + connect \xer_so_ok$98 1'0 + connect \p_ready_o \n_i_rdy_data + connect \n_valid_o \r_busy + connect { \xer_so_ok$97 \xer_so$96 } { 1'0 \main_xer_so$65 } + connect { \xer_ov_ok$95 \xer_ov$94 } { \main_xer_ov_ok \main_xer_ov } + connect { \xer_ca_ok$93 \xer_ca$92 } { \main_xer_ca_ok \main_xer_ca$64 } + connect { \cr_a_ok$91 \cr_a$90 } { \main_cr_a_ok \main_cr_a } + connect { \o_ok$89 \o$88 } { \main_o_ok \main_o } + connect { \alu_op__insn$87 \alu_op__data_len$86 \alu_op__is_signed$85 \alu_op__is_32bit$84 \alu_op__output_carry$83 \alu_op__input_carry$82 \alu_op__write_cr0$81 \alu_op__invert_out$80 \alu_op__zero_a$79 \alu_op__invert_in$78 \alu_op__oe__ok$77 \alu_op__oe__oe$76 \alu_op__rc__ok$75 \alu_op__rc__rc$74 \alu_op__imm_data__ok$73 \alu_op__imm_data__data$72 \alu_op__fn_unit$71 \alu_op__insn_type$70 } { \main_alu_op__insn$63 \main_alu_op__data_len$62 \main_alu_op__is_signed$61 \main_alu_op__is_32bit$60 \main_alu_op__output_carry$59 \main_alu_op__input_carry$58 \main_alu_op__write_cr0$57 \main_alu_op__invert_out$56 \main_alu_op__zero_a$55 \main_alu_op__invert_in$54 \main_alu_op__oe__ok$53 \main_alu_op__oe__oe$52 \main_alu_op__rc__ok$51 \main_alu_op__rc__rc$50 \main_alu_op__imm_data__ok$49 \main_alu_op__imm_data__data$48 \main_alu_op__fn_unit$47 \main_alu_op__insn_type$46 } + connect \muxid$69 \main_muxid$45 + connect \p_valid_i_p_ready_o \$67 + connect \n_i_rdy_data \n_ready_i + connect \p_valid_i$66 \p_valid_i + connect \main_xer_ca \input_xer_ca$44 + connect \main_xer_so \input_xer_so$43 + connect \main_rb \input_rb$42 + connect \main_ra \input_ra$41 + connect { \main_alu_op__insn \main_alu_op__data_len \main_alu_op__is_signed \main_alu_op__is_32bit \main_alu_op__output_carry \main_alu_op__input_carry \main_alu_op__write_cr0 \main_alu_op__invert_out \main_alu_op__zero_a \main_alu_op__invert_in \main_alu_op__oe__ok \main_alu_op__oe__oe \main_alu_op__rc__ok \main_alu_op__rc__rc \main_alu_op__imm_data__ok \main_alu_op__imm_data__data \main_alu_op__fn_unit \main_alu_op__insn_type } { \input_alu_op__insn$40 \input_alu_op__data_len$39 \input_alu_op__is_signed$38 \input_alu_op__is_32bit$37 \input_alu_op__output_carry$36 \input_alu_op__input_carry$35 \input_alu_op__write_cr0$34 \input_alu_op__invert_out$33 \input_alu_op__zero_a$32 \input_alu_op__invert_in$31 \input_alu_op__oe__ok$30 \input_alu_op__oe__oe$29 \input_alu_op__rc__ok$28 \input_alu_op__rc__rc$27 \input_alu_op__imm_data__ok$26 \input_alu_op__imm_data__data$25 \input_alu_op__fn_unit$24 \input_alu_op__insn_type$23 } + connect \main_muxid \input_muxid$22 + connect \input_xer_ca \xer_ca$21 + connect \input_xer_so \xer_so$20 + connect \input_rb \rb + connect \input_ra \ra + connect { \input_alu_op__insn \input_alu_op__data_len \input_alu_op__is_signed \input_alu_op__is_32bit \input_alu_op__output_carry \input_alu_op__input_carry \input_alu_op__write_cr0 \input_alu_op__invert_out \input_alu_op__zero_a \input_alu_op__invert_in \input_alu_op__oe__ok \input_alu_op__oe__oe \input_alu_op__rc__ok \input_alu_op__rc__rc \input_alu_op__imm_data__ok \input_alu_op__imm_data__data \input_alu_op__fn_unit \input_alu_op__insn_type } { \alu_op__insn$19 \alu_op__data_len$18 \alu_op__is_signed$17 \alu_op__is_32bit$16 \alu_op__output_carry$15 \alu_op__input_carry$14 \alu_op__write_cr0$13 \alu_op__invert_out$12 \alu_op__zero_a$11 \alu_op__invert_in$10 \alu_op__oe__ok$9 \alu_op__oe__oe$8 \alu_op__rc__ok$7 \alu_op__rc__rc$6 \alu_op__imm_data__ok$5 \alu_op__imm_data__data$4 \alu_op__fn_unit$3 \alu_op__insn_type$2 } + connect \input_muxid \muxid$1 +end +attribute \src "libresoc.v:152755.1-154146.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.pipe1" +attribute \generator "nMigen" +module \pipe1$107 + attribute \src "libresoc.v:154060.3-154078.6" + wire width 4 $0\cr_a$next[3:0]$8707 + attribute \src "libresoc.v:153828.3-153829.25" + wire width 4 $0\cr_a[3:0] + attribute \src "libresoc.v:154060.3-154078.6" + wire $0\cr_a_ok$next[0:0]$8708 + attribute \src "libresoc.v:153830.3-153831.31" + wire $0\cr_a_ok[0:0] + attribute \src "libresoc.v:152756.7-152756.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:153988.3-154000.6" + wire width 2 $0\muxid$next[1:0]$8659 + attribute \src "libresoc.v:153868.3-153869.27" + wire width 2 $0\muxid[1:0] + attribute \src "libresoc.v:154041.3-154059.6" + wire width 64 $0\o$next[63:0]$8701 + attribute \src "libresoc.v:153832.3-153833.19" + wire width 64 $0\o[63:0] + attribute \src "libresoc.v:154041.3-154059.6" + wire $0\o_ok$next[0:0]$8702 + attribute \src "libresoc.v:153834.3-153835.25" + wire $0\o_ok[0:0] + attribute \src "libresoc.v:153970.3-153987.6" + wire $0\r_busy$next[0:0]$8655 + attribute \src "libresoc.v:153870.3-153871.29" + wire $0\r_busy[0:0] + attribute \src "libresoc.v:154001.3-154040.6" + wire width 12 $0\sr_op__fn_unit$next[11:0]$8662 + attribute \src "libresoc.v:153838.3-153839.45" + wire width 12 $0\sr_op__fn_unit[11:0] + attribute \src "libresoc.v:154001.3-154040.6" + wire width 64 $0\sr_op__imm_data__data$next[63:0]$8663 + attribute \src "libresoc.v:153840.3-153841.59" + wire width 64 $0\sr_op__imm_data__data[63:0] + attribute \src "libresoc.v:154001.3-154040.6" + wire $0\sr_op__imm_data__ok$next[0:0]$8664 + attribute \src "libresoc.v:153842.3-153843.55" + wire $0\sr_op__imm_data__ok[0:0] + attribute \src "libresoc.v:154001.3-154040.6" + wire width 2 $0\sr_op__input_carry$next[1:0]$8665 + attribute \src "libresoc.v:153854.3-153855.53" + wire width 2 $0\sr_op__input_carry[1:0] + attribute \src "libresoc.v:154001.3-154040.6" + wire $0\sr_op__input_cr$next[0:0]$8666 + attribute \src "libresoc.v:153858.3-153859.47" + wire $0\sr_op__input_cr[0:0] + attribute \src "libresoc.v:154001.3-154040.6" + wire width 32 $0\sr_op__insn$next[31:0]$8667 + attribute \src "libresoc.v:153866.3-153867.39" + wire width 32 $0\sr_op__insn[31:0] + attribute \src "libresoc.v:154001.3-154040.6" + wire width 7 $0\sr_op__insn_type$next[6:0]$8668 + attribute \src "libresoc.v:153836.3-153837.49" + wire width 7 $0\sr_op__insn_type[6:0] + attribute \src "libresoc.v:154001.3-154040.6" + wire $0\sr_op__is_32bit$next[0:0]$8669 + attribute \src "libresoc.v:153862.3-153863.47" + wire $0\sr_op__is_32bit[0:0] + attribute \src "libresoc.v:154001.3-154040.6" + wire $0\sr_op__is_signed$next[0:0]$8670 + attribute \src "libresoc.v:153864.3-153865.49" + wire $0\sr_op__is_signed[0:0] + attribute \src "libresoc.v:154001.3-154040.6" + wire $0\sr_op__oe__oe$next[0:0]$8671 + attribute \src "libresoc.v:153848.3-153849.43" + wire $0\sr_op__oe__oe[0:0] + attribute \src "libresoc.v:154001.3-154040.6" + wire $0\sr_op__oe__ok$next[0:0]$8672 + attribute \src "libresoc.v:153850.3-153851.43" + wire $0\sr_op__oe__ok[0:0] + attribute \src "libresoc.v:154001.3-154040.6" + wire $0\sr_op__output_carry$next[0:0]$8673 + attribute \src "libresoc.v:153856.3-153857.55" + wire $0\sr_op__output_carry[0:0] + attribute \src "libresoc.v:154001.3-154040.6" + wire $0\sr_op__output_cr$next[0:0]$8674 + attribute \src "libresoc.v:153860.3-153861.49" + wire $0\sr_op__output_cr[0:0] + attribute \src "libresoc.v:154001.3-154040.6" + wire $0\sr_op__rc__ok$next[0:0]$8675 + attribute \src "libresoc.v:153846.3-153847.43" + wire $0\sr_op__rc__ok[0:0] + attribute \src "libresoc.v:154001.3-154040.6" + wire $0\sr_op__rc__rc$next[0:0]$8676 + attribute \src "libresoc.v:153844.3-153845.43" + wire $0\sr_op__rc__rc[0:0] + attribute \src "libresoc.v:154001.3-154040.6" + wire $0\sr_op__write_cr0$next[0:0]$8677 + attribute \src "libresoc.v:153852.3-153853.49" + wire $0\sr_op__write_cr0[0:0] + attribute \src "libresoc.v:154098.3-154116.6" + wire width 2 $0\xer_ca$next[1:0]$8720 + attribute \src "libresoc.v:153820.3-153821.29" + wire width 2 $0\xer_ca[1:0] + attribute \src "libresoc.v:154098.3-154116.6" + wire $0\xer_ca_ok$next[0:0]$8719 + attribute \src "libresoc.v:153822.3-153823.35" + wire $0\xer_ca_ok[0:0] + attribute \src "libresoc.v:154079.3-154097.6" + wire $0\xer_so$next[0:0]$8713 + attribute \src "libresoc.v:153824.3-153825.29" + wire $0\xer_so[0:0] + attribute \src "libresoc.v:154079.3-154097.6" + wire $0\xer_so_ok$next[0:0]$8714 + attribute \src "libresoc.v:153826.3-153827.35" + wire $0\xer_so_ok[0:0] + attribute \src "libresoc.v:154060.3-154078.6" + wire width 4 $1\cr_a$next[3:0]$8709 + attribute \src "libresoc.v:152765.13-152765.24" + wire width 4 $1\cr_a[3:0] + attribute \src "libresoc.v:154060.3-154078.6" + wire $1\cr_a_ok$next[0:0]$8710 + attribute \src "libresoc.v:152774.7-152774.21" + wire $1\cr_a_ok[0:0] + attribute \src "libresoc.v:153988.3-154000.6" + wire width 2 $1\muxid$next[1:0]$8660 + attribute \src "libresoc.v:153319.13-153319.25" + wire width 2 $1\muxid[1:0] + attribute \src "libresoc.v:154041.3-154059.6" + wire width 64 $1\o$next[63:0]$8703 + attribute \src "libresoc.v:153334.14-153334.38" + wire width 64 $1\o[63:0] + attribute \src "libresoc.v:154041.3-154059.6" + wire $1\o_ok$next[0:0]$8704 + attribute \src "libresoc.v:153341.7-153341.18" + wire $1\o_ok[0:0] + attribute \src "libresoc.v:153970.3-153987.6" + wire $1\r_busy$next[0:0]$8656 + attribute \src "libresoc.v:153355.7-153355.20" + wire $1\r_busy[0:0] + attribute \src "libresoc.v:154001.3-154040.6" + wire width 12 $1\sr_op__fn_unit$next[11:0]$8678 + attribute \src "libresoc.v:153379.14-153379.38" + wire width 12 $1\sr_op__fn_unit[11:0] + attribute \src "libresoc.v:154001.3-154040.6" + wire width 64 $1\sr_op__imm_data__data$next[63:0]$8679 + attribute \src "libresoc.v:153414.14-153414.58" + wire width 64 $1\sr_op__imm_data__data[63:0] + attribute \src "libresoc.v:154001.3-154040.6" + wire $1\sr_op__imm_data__ok$next[0:0]$8680 + attribute \src "libresoc.v:153423.7-153423.33" + wire $1\sr_op__imm_data__ok[0:0] + attribute \src "libresoc.v:154001.3-154040.6" + wire width 2 $1\sr_op__input_carry$next[1:0]$8681 + attribute \src "libresoc.v:153436.13-153436.38" + wire width 2 $1\sr_op__input_carry[1:0] + attribute \src "libresoc.v:154001.3-154040.6" + wire $1\sr_op__input_cr$next[0:0]$8682 + attribute \src "libresoc.v:153453.7-153453.29" + wire $1\sr_op__input_cr[0:0] + attribute \src "libresoc.v:154001.3-154040.6" + wire width 32 $1\sr_op__insn$next[31:0]$8683 + attribute \src "libresoc.v:153462.14-153462.33" + wire width 32 $1\sr_op__insn[31:0] + attribute \src "libresoc.v:154001.3-154040.6" + wire width 7 $1\sr_op__insn_type$next[6:0]$8684 + attribute \src "libresoc.v:153545.13-153545.37" + wire width 7 $1\sr_op__insn_type[6:0] + attribute \src "libresoc.v:154001.3-154040.6" + wire $1\sr_op__is_32bit$next[0:0]$8685 + attribute \src "libresoc.v:153702.7-153702.29" + wire $1\sr_op__is_32bit[0:0] + attribute \src "libresoc.v:154001.3-154040.6" + wire $1\sr_op__is_signed$next[0:0]$8686 + attribute \src "libresoc.v:153711.7-153711.30" + wire $1\sr_op__is_signed[0:0] + attribute \src "libresoc.v:154001.3-154040.6" + wire $1\sr_op__oe__oe$next[0:0]$8687 + attribute \src "libresoc.v:153720.7-153720.27" + wire $1\sr_op__oe__oe[0:0] + attribute \src "libresoc.v:154001.3-154040.6" + wire $1\sr_op__oe__ok$next[0:0]$8688 + attribute \src "libresoc.v:153729.7-153729.27" + wire $1\sr_op__oe__ok[0:0] + attribute \src "libresoc.v:154001.3-154040.6" + wire $1\sr_op__output_carry$next[0:0]$8689 + attribute \src "libresoc.v:153738.7-153738.33" + wire $1\sr_op__output_carry[0:0] + attribute \src "libresoc.v:154001.3-154040.6" + wire $1\sr_op__output_cr$next[0:0]$8690 + attribute \src "libresoc.v:153747.7-153747.30" + wire $1\sr_op__output_cr[0:0] + attribute \src "libresoc.v:154001.3-154040.6" + wire $1\sr_op__rc__ok$next[0:0]$8691 + attribute \src "libresoc.v:153756.7-153756.27" + wire $1\sr_op__rc__ok[0:0] + attribute \src "libresoc.v:154001.3-154040.6" + wire $1\sr_op__rc__rc$next[0:0]$8692 + attribute \src "libresoc.v:153765.7-153765.27" + wire $1\sr_op__rc__rc[0:0] + attribute \src "libresoc.v:154001.3-154040.6" + wire $1\sr_op__write_cr0$next[0:0]$8693 + attribute \src "libresoc.v:153774.7-153774.30" + wire $1\sr_op__write_cr0[0:0] + attribute \src "libresoc.v:154098.3-154116.6" + wire width 2 $1\xer_ca$next[1:0]$8722 + attribute \src "libresoc.v:153783.13-153783.26" + wire width 2 $1\xer_ca[1:0] + attribute \src "libresoc.v:154098.3-154116.6" + wire $1\xer_ca_ok$next[0:0]$8721 + attribute \src "libresoc.v:153794.7-153794.23" + wire $1\xer_ca_ok[0:0] + attribute \src "libresoc.v:154079.3-154097.6" + wire $1\xer_so$next[0:0]$8715 + attribute \src "libresoc.v:153803.7-153803.20" + wire $1\xer_so[0:0] + attribute \src "libresoc.v:154079.3-154097.6" + wire $1\xer_so_ok$next[0:0]$8716 + attribute \src "libresoc.v:153812.7-153812.23" + wire $1\xer_so_ok[0:0] + attribute \src "libresoc.v:154060.3-154078.6" + wire $2\cr_a_ok$next[0:0]$8711 + attribute \src "libresoc.v:154041.3-154059.6" + wire $2\o_ok$next[0:0]$8705 + attribute \src "libresoc.v:153970.3-153987.6" + wire $2\r_busy$next[0:0]$8657 + attribute \src "libresoc.v:154001.3-154040.6" + wire width 64 $2\sr_op__imm_data__data$next[63:0]$8694 + attribute \src "libresoc.v:154001.3-154040.6" + wire $2\sr_op__imm_data__ok$next[0:0]$8695 + attribute \src "libresoc.v:154001.3-154040.6" + wire $2\sr_op__oe__oe$next[0:0]$8696 + attribute \src "libresoc.v:154001.3-154040.6" + wire $2\sr_op__oe__ok$next[0:0]$8697 + attribute \src "libresoc.v:154001.3-154040.6" + wire $2\sr_op__rc__ok$next[0:0]$8698 + attribute \src "libresoc.v:154001.3-154040.6" + wire $2\sr_op__rc__rc$next[0:0]$8699 + attribute \src "libresoc.v:154098.3-154116.6" + wire $2\xer_ca_ok$next[0:0]$8723 + attribute \src "libresoc.v:154079.3-154097.6" + wire $2\xer_so_ok$next[0:0]$8717 + attribute \src "libresoc.v:153819.18-153819.118" + wire $and$libresoc.v:153819$8627_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + wire \$62 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 53 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 output 23 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \cr_a$83 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \cr_a$85 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \cr_a$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 24 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_a_ok$84 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_a_ok$86 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_a_ok$next + attribute \src "libresoc.v:152756.7-152756.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \input_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \input_muxid$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_ra$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_rb$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_rc$39 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \input_sr_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \input_sr_op__fn_unit$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \input_sr_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \input_sr_op__imm_data__data$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__imm_data__ok$24 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \input_sr_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \input_sr_op__input_carry$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__input_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__input_cr$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \input_sr_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \input_sr_op__insn$36 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \input_sr_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \input_sr_op__insn_type$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__is_32bit$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__is_signed$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__oe__oe$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__oe__ok$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__output_carry$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__output_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__output_cr$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__rc__ok$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__rc__rc$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__write_cr0$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 \input_xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 \input_xer_ca$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \input_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \input_xer_so$40 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \main_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \main_muxid$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \main_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \main_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \main_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \main_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \main_rc + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \main_sr_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \main_sr_op__fn_unit$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \main_sr_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \main_sr_op__imm_data__data$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__imm_data__ok$46 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \main_sr_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \main_sr_op__input_carry$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__input_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__input_cr$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \main_sr_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \main_sr_op__insn$58 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \main_sr_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \main_sr_op__insn_type$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__is_32bit$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__is_signed$57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__oe__oe$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__oe__ok$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__output_carry$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__output_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__output_cr$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__rc__ok$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__rc__rc$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__write_cr0$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \main_xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \main_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \main_xer_so$59 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 4 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 31 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$64 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" + wire \n_i_rdy_data + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire input 3 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire output 2 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 21 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \o$81 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \o$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 22 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \o_ok$82 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \o_ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire output 30 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire input 29 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" + wire \p_valid_i$61 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire \r_busy$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 48 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 49 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 50 \rc + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 output 6 \sr_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 33 \sr_op__fn_unit$3 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \sr_op__fn_unit$66 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \sr_op__fn_unit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 7 \sr_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 34 \sr_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \sr_op__imm_data__data$67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \sr_op__imm_data__data$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 8 \sr_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 35 \sr_op__imm_data__ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__imm_data__ok$68 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__imm_data__ok$next + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 14 \sr_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 41 \sr_op__input_carry$11 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \sr_op__input_carry$74 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \sr_op__input_carry$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 16 \sr_op__input_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 43 \sr_op__input_cr$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__input_cr$76 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__input_cr$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 20 \sr_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 47 \sr_op__insn$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \sr_op__insn$80 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \sr_op__insn$next + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 5 \sr_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 32 \sr_op__insn_type$2 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \sr_op__insn_type$65 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \sr_op__insn_type$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 18 \sr_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 45 \sr_op__is_32bit$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__is_32bit$78 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__is_32bit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 19 \sr_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 46 \sr_op__is_signed$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__is_signed$79 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__is_signed$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 11 \sr_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__oe__oe$71 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 38 \sr_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__oe__oe$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 12 \sr_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__oe__ok$72 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 39 \sr_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__oe__ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 15 \sr_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 42 \sr_op__output_carry$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__output_carry$75 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__output_carry$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 17 \sr_op__output_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 44 \sr_op__output_cr$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__output_cr$77 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__output_cr$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 10 \sr_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 37 \sr_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__rc__ok$70 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__rc__ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 9 \sr_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 36 \sr_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__rc__rc$69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__rc__rc$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 13 \sr_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 40 \sr_op__write_cr0$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__write_cr0$73 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__write_cr0$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 output 27 \xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 input 52 \xer_ca$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 \xer_ca$60 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \xer_ca$90 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \xer_ca$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 28 \xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \xer_ca_ok$91 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \xer_ca_ok$92 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \xer_ca_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 25 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 51 \xer_so$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \xer_so$87 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \xer_so$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 26 \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \xer_so_ok$88 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \xer_so_ok$89 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \xer_so_ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + cell $and $and$libresoc.v:153819$8627 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i$61 + connect \B \p_ready_o + connect \Y $and$libresoc.v:153819$8627_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:153872.15-153917.4" + cell \input$110 \input + connect \muxid \input_muxid + connect \muxid$1 \input_muxid$20 + connect \ra \input_ra + connect \ra$18 \input_ra$37 + connect \rb \input_rb + connect \rb$19 \input_rb$38 + connect \rc \input_rc + connect \rc$20 \input_rc$39 + connect \sr_op__fn_unit \input_sr_op__fn_unit + connect \sr_op__fn_unit$3 \input_sr_op__fn_unit$22 + connect \sr_op__imm_data__data \input_sr_op__imm_data__data + connect \sr_op__imm_data__data$4 \input_sr_op__imm_data__data$23 + connect \sr_op__imm_data__ok \input_sr_op__imm_data__ok + connect \sr_op__imm_data__ok$5 \input_sr_op__imm_data__ok$24 + connect \sr_op__input_carry \input_sr_op__input_carry + connect \sr_op__input_carry$11 \input_sr_op__input_carry$30 + connect \sr_op__input_cr \input_sr_op__input_cr + connect \sr_op__input_cr$13 \input_sr_op__input_cr$32 + connect \sr_op__insn \input_sr_op__insn + connect \sr_op__insn$17 \input_sr_op__insn$36 + connect \sr_op__insn_type \input_sr_op__insn_type + connect \sr_op__insn_type$2 \input_sr_op__insn_type$21 + connect \sr_op__is_32bit \input_sr_op__is_32bit + connect \sr_op__is_32bit$15 \input_sr_op__is_32bit$34 + connect \sr_op__is_signed \input_sr_op__is_signed + connect \sr_op__is_signed$16 \input_sr_op__is_signed$35 + connect \sr_op__oe__oe \input_sr_op__oe__oe + connect \sr_op__oe__oe$8 \input_sr_op__oe__oe$27 + connect \sr_op__oe__ok \input_sr_op__oe__ok + connect \sr_op__oe__ok$9 \input_sr_op__oe__ok$28 + connect \sr_op__output_carry \input_sr_op__output_carry + connect \sr_op__output_carry$12 \input_sr_op__output_carry$31 + connect \sr_op__output_cr \input_sr_op__output_cr + connect \sr_op__output_cr$14 \input_sr_op__output_cr$33 + connect \sr_op__rc__ok \input_sr_op__rc__ok + connect \sr_op__rc__ok$7 \input_sr_op__rc__ok$26 + connect \sr_op__rc__rc \input_sr_op__rc__rc + connect \sr_op__rc__rc$6 \input_sr_op__rc__rc$25 + connect \sr_op__write_cr0 \input_sr_op__write_cr0 + connect \sr_op__write_cr0$10 \input_sr_op__write_cr0$29 + connect \xer_ca \input_xer_ca + connect \xer_ca$22 \input_xer_ca$41 + connect \xer_so \input_xer_so + connect \xer_so$21 \input_xer_so$40 + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:153918.14-153961.4" + cell \main$111 \main + connect \muxid \main_muxid + connect \muxid$1 \main_muxid$42 + connect \o \main_o + connect \o_ok \main_o_ok + connect \ra \main_ra + connect \rb \main_rb + connect \rc \main_rc + connect \sr_op__fn_unit \main_sr_op__fn_unit + connect \sr_op__fn_unit$3 \main_sr_op__fn_unit$44 + connect \sr_op__imm_data__data \main_sr_op__imm_data__data + connect \sr_op__imm_data__data$4 \main_sr_op__imm_data__data$45 + connect \sr_op__imm_data__ok \main_sr_op__imm_data__ok + connect \sr_op__imm_data__ok$5 \main_sr_op__imm_data__ok$46 + connect \sr_op__input_carry \main_sr_op__input_carry + connect \sr_op__input_carry$11 \main_sr_op__input_carry$52 + connect \sr_op__input_cr \main_sr_op__input_cr + connect \sr_op__input_cr$13 \main_sr_op__input_cr$54 + connect \sr_op__insn \main_sr_op__insn + connect \sr_op__insn$17 \main_sr_op__insn$58 + connect \sr_op__insn_type \main_sr_op__insn_type + connect \sr_op__insn_type$2 \main_sr_op__insn_type$43 + connect \sr_op__is_32bit \main_sr_op__is_32bit + connect \sr_op__is_32bit$15 \main_sr_op__is_32bit$56 + connect \sr_op__is_signed \main_sr_op__is_signed + connect \sr_op__is_signed$16 \main_sr_op__is_signed$57 + connect \sr_op__oe__oe \main_sr_op__oe__oe + connect \sr_op__oe__oe$8 \main_sr_op__oe__oe$49 + connect \sr_op__oe__ok \main_sr_op__oe__ok + connect \sr_op__oe__ok$9 \main_sr_op__oe__ok$50 + connect \sr_op__output_carry \main_sr_op__output_carry + connect \sr_op__output_carry$12 \main_sr_op__output_carry$53 + connect \sr_op__output_cr \main_sr_op__output_cr + connect \sr_op__output_cr$14 \main_sr_op__output_cr$55 + connect \sr_op__rc__ok \main_sr_op__rc__ok + connect \sr_op__rc__ok$7 \main_sr_op__rc__ok$48 + connect \sr_op__rc__rc \main_sr_op__rc__rc + connect \sr_op__rc__rc$6 \main_sr_op__rc__rc$47 + connect \sr_op__write_cr0 \main_sr_op__write_cr0 + connect \sr_op__write_cr0$10 \main_sr_op__write_cr0$51 + connect \xer_ca \main_xer_ca + connect \xer_so \main_xer_so + connect \xer_so$18 \main_xer_so$59 + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:153962.11-153965.4" + cell \n$109 \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:153966.11-153969.4" + cell \p$108 \p + connect \p_ready_o \p_ready_o + connect \p_valid_i \p_valid_i + end + attribute \src "libresoc.v:152756.7-152756.20" + process $proc$libresoc.v:152756$8724 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:152765.13-152765.24" + process $proc$libresoc.v:152765$8725 + assign { } { } + assign $1\cr_a[3:0] 4'0000 + sync always + sync init + update \cr_a $1\cr_a[3:0] + end + attribute \src "libresoc.v:152774.7-152774.21" + process $proc$libresoc.v:152774$8726 + assign { } { } + assign $1\cr_a_ok[0:0] 1'0 + sync always + sync init + update \cr_a_ok $1\cr_a_ok[0:0] + end + attribute \src "libresoc.v:153319.13-153319.25" + process $proc$libresoc.v:153319$8727 + assign { } { } + assign $1\muxid[1:0] 2'00 + sync always + sync init + update \muxid $1\muxid[1:0] + end + attribute \src "libresoc.v:153334.14-153334.38" + process $proc$libresoc.v:153334$8728 + assign { } { } + assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \o $1\o[63:0] + end + attribute \src "libresoc.v:153341.7-153341.18" + process $proc$libresoc.v:153341$8729 + assign { } { } + assign $1\o_ok[0:0] 1'0 + sync always + sync init + update \o_ok $1\o_ok[0:0] + end + attribute \src "libresoc.v:153355.7-153355.20" + process $proc$libresoc.v:153355$8730 + assign { } { } + assign $1\r_busy[0:0] 1'0 + sync always + sync init + update \r_busy $1\r_busy[0:0] + end + attribute \src "libresoc.v:153379.14-153379.38" + process $proc$libresoc.v:153379$8731 + assign { } { } + assign $1\sr_op__fn_unit[11:0] 12'000000000000 + sync always + sync init + update \sr_op__fn_unit $1\sr_op__fn_unit[11:0] + end + attribute \src "libresoc.v:153414.14-153414.58" + process $proc$libresoc.v:153414$8732 + assign { } { } + assign $1\sr_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \sr_op__imm_data__data $1\sr_op__imm_data__data[63:0] + end + attribute \src "libresoc.v:153423.7-153423.33" + process $proc$libresoc.v:153423$8733 + assign { } { } + assign $1\sr_op__imm_data__ok[0:0] 1'0 + sync always + sync init + update \sr_op__imm_data__ok $1\sr_op__imm_data__ok[0:0] + end + attribute \src "libresoc.v:153436.13-153436.38" + process $proc$libresoc.v:153436$8734 + assign { } { } + assign $1\sr_op__input_carry[1:0] 2'00 + sync always + sync init + update \sr_op__input_carry $1\sr_op__input_carry[1:0] + end + attribute \src "libresoc.v:153453.7-153453.29" + process $proc$libresoc.v:153453$8735 + assign { } { } + assign $1\sr_op__input_cr[0:0] 1'0 + sync always + sync init + update \sr_op__input_cr $1\sr_op__input_cr[0:0] + end + attribute \src "libresoc.v:153462.14-153462.33" + process $proc$libresoc.v:153462$8736 + assign { } { } + assign $1\sr_op__insn[31:0] 0 + sync always + sync init + update \sr_op__insn $1\sr_op__insn[31:0] + end + attribute \src "libresoc.v:153545.13-153545.37" + process $proc$libresoc.v:153545$8737 + assign { } { } + assign $1\sr_op__insn_type[6:0] 7'0000000 + sync always + sync init + update \sr_op__insn_type $1\sr_op__insn_type[6:0] + end + attribute \src "libresoc.v:153702.7-153702.29" + process $proc$libresoc.v:153702$8738 + assign { } { } + assign $1\sr_op__is_32bit[0:0] 1'0 + sync always + sync init + update \sr_op__is_32bit $1\sr_op__is_32bit[0:0] + end + attribute \src "libresoc.v:153711.7-153711.30" + process $proc$libresoc.v:153711$8739 + assign { } { } + assign $1\sr_op__is_signed[0:0] 1'0 + sync always + sync init + update \sr_op__is_signed $1\sr_op__is_signed[0:0] + end + attribute \src "libresoc.v:153720.7-153720.27" + process $proc$libresoc.v:153720$8740 + assign { } { } + assign $1\sr_op__oe__oe[0:0] 1'0 + sync always + sync init + update \sr_op__oe__oe $1\sr_op__oe__oe[0:0] + end + attribute \src "libresoc.v:153729.7-153729.27" + process $proc$libresoc.v:153729$8741 + assign { } { } + assign $1\sr_op__oe__ok[0:0] 1'0 + sync always + sync init + update \sr_op__oe__ok $1\sr_op__oe__ok[0:0] + end + attribute \src "libresoc.v:153738.7-153738.33" + process $proc$libresoc.v:153738$8742 + assign { } { } + assign $1\sr_op__output_carry[0:0] 1'0 + sync always + sync init + update \sr_op__output_carry $1\sr_op__output_carry[0:0] + end + attribute \src "libresoc.v:153747.7-153747.30" + process $proc$libresoc.v:153747$8743 + assign { } { } + assign $1\sr_op__output_cr[0:0] 1'0 + sync always + sync init + update \sr_op__output_cr $1\sr_op__output_cr[0:0] + end + attribute \src "libresoc.v:153756.7-153756.27" + process $proc$libresoc.v:153756$8744 + assign { } { } + assign $1\sr_op__rc__ok[0:0] 1'0 + sync always + sync init + update \sr_op__rc__ok $1\sr_op__rc__ok[0:0] + end + attribute \src "libresoc.v:153765.7-153765.27" + process $proc$libresoc.v:153765$8745 + assign { } { } + assign $1\sr_op__rc__rc[0:0] 1'0 + sync always + sync init + update \sr_op__rc__rc $1\sr_op__rc__rc[0:0] + end + attribute \src "libresoc.v:153774.7-153774.30" + process $proc$libresoc.v:153774$8746 + assign { } { } + assign $1\sr_op__write_cr0[0:0] 1'0 + sync always + sync init + update \sr_op__write_cr0 $1\sr_op__write_cr0[0:0] + end + attribute \src "libresoc.v:153783.13-153783.26" + process $proc$libresoc.v:153783$8747 + assign { } { } + assign $1\xer_ca[1:0] 2'00 + sync always + sync init + update \xer_ca $1\xer_ca[1:0] + end + attribute \src "libresoc.v:153794.7-153794.23" + process $proc$libresoc.v:153794$8748 + assign { } { } + assign $1\xer_ca_ok[0:0] 1'0 + sync always + sync init + update \xer_ca_ok $1\xer_ca_ok[0:0] + end + attribute \src "libresoc.v:153803.7-153803.20" + process $proc$libresoc.v:153803$8749 + assign { } { } + assign $1\xer_so[0:0] 1'0 + sync always + sync init + update \xer_so $1\xer_so[0:0] + end + attribute \src "libresoc.v:153812.7-153812.23" + process $proc$libresoc.v:153812$8750 + assign { } { } + assign $1\xer_so_ok[0:0] 1'0 + sync always + sync init + update \xer_so_ok $1\xer_so_ok[0:0] + end + attribute \src "libresoc.v:153820.3-153821.29" + process $proc$libresoc.v:153820$8628 + assign { } { } + assign $0\xer_ca[1:0] \xer_ca$next + sync posedge \coresync_clk + update \xer_ca $0\xer_ca[1:0] + end + attribute \src "libresoc.v:153822.3-153823.35" + process $proc$libresoc.v:153822$8629 + assign { } { } + assign $0\xer_ca_ok[0:0] \xer_ca_ok$next + sync posedge \coresync_clk + update \xer_ca_ok $0\xer_ca_ok[0:0] + end + attribute \src "libresoc.v:153824.3-153825.29" + process $proc$libresoc.v:153824$8630 + assign { } { } + assign $0\xer_so[0:0] \xer_so$next + sync posedge \coresync_clk + update \xer_so $0\xer_so[0:0] + end + attribute \src "libresoc.v:153826.3-153827.35" + process $proc$libresoc.v:153826$8631 + assign { } { } + assign $0\xer_so_ok[0:0] \xer_so_ok$next + sync posedge \coresync_clk + update \xer_so_ok $0\xer_so_ok[0:0] + end + attribute \src "libresoc.v:153828.3-153829.25" + process $proc$libresoc.v:153828$8632 + assign { } { } + assign $0\cr_a[3:0] \cr_a$next + sync posedge \coresync_clk + update \cr_a $0\cr_a[3:0] + end + attribute \src "libresoc.v:153830.3-153831.31" + process $proc$libresoc.v:153830$8633 + assign { } { } + assign $0\cr_a_ok[0:0] \cr_a_ok$next + sync posedge \coresync_clk + update \cr_a_ok $0\cr_a_ok[0:0] + end + attribute \src "libresoc.v:153832.3-153833.19" + process $proc$libresoc.v:153832$8634 + assign { } { } + assign $0\o[63:0] \o$next + sync posedge \coresync_clk + update \o $0\o[63:0] + end + attribute \src "libresoc.v:153834.3-153835.25" + process $proc$libresoc.v:153834$8635 + assign { } { } + assign $0\o_ok[0:0] \o_ok$next + sync posedge \coresync_clk + update \o_ok $0\o_ok[0:0] + end + attribute \src "libresoc.v:153836.3-153837.49" + process $proc$libresoc.v:153836$8636 + assign { } { } + assign $0\sr_op__insn_type[6:0] \sr_op__insn_type$next + sync posedge \coresync_clk + update \sr_op__insn_type $0\sr_op__insn_type[6:0] + end + attribute \src "libresoc.v:153838.3-153839.45" + process $proc$libresoc.v:153838$8637 + assign { } { } + assign $0\sr_op__fn_unit[11:0] \sr_op__fn_unit$next + sync posedge \coresync_clk + update \sr_op__fn_unit $0\sr_op__fn_unit[11:0] + end + attribute \src "libresoc.v:153840.3-153841.59" + process $proc$libresoc.v:153840$8638 + assign { } { } + assign $0\sr_op__imm_data__data[63:0] \sr_op__imm_data__data$next + sync posedge \coresync_clk + update \sr_op__imm_data__data $0\sr_op__imm_data__data[63:0] + end + attribute \src "libresoc.v:153842.3-153843.55" + process $proc$libresoc.v:153842$8639 + assign { } { } + assign $0\sr_op__imm_data__ok[0:0] \sr_op__imm_data__ok$next + sync posedge \coresync_clk + update \sr_op__imm_data__ok $0\sr_op__imm_data__ok[0:0] + end + attribute \src "libresoc.v:153844.3-153845.43" + process $proc$libresoc.v:153844$8640 + assign { } { } + assign $0\sr_op__rc__rc[0:0] \sr_op__rc__rc$next + sync posedge \coresync_clk + update \sr_op__rc__rc $0\sr_op__rc__rc[0:0] + end + attribute \src "libresoc.v:153846.3-153847.43" + process $proc$libresoc.v:153846$8641 + assign { } { } + assign $0\sr_op__rc__ok[0:0] \sr_op__rc__ok$next + sync posedge \coresync_clk + update \sr_op__rc__ok $0\sr_op__rc__ok[0:0] + end + attribute \src "libresoc.v:153848.3-153849.43" + process $proc$libresoc.v:153848$8642 + assign { } { } + assign $0\sr_op__oe__oe[0:0] \sr_op__oe__oe$next + sync posedge \coresync_clk + update \sr_op__oe__oe $0\sr_op__oe__oe[0:0] + end + attribute \src "libresoc.v:153850.3-153851.43" + process $proc$libresoc.v:153850$8643 + assign { } { } + assign $0\sr_op__oe__ok[0:0] \sr_op__oe__ok$next + sync posedge \coresync_clk + update \sr_op__oe__ok $0\sr_op__oe__ok[0:0] + end + attribute \src "libresoc.v:153852.3-153853.49" + process $proc$libresoc.v:153852$8644 + assign { } { } + assign $0\sr_op__write_cr0[0:0] \sr_op__write_cr0$next + sync posedge \coresync_clk + update \sr_op__write_cr0 $0\sr_op__write_cr0[0:0] + end + attribute \src "libresoc.v:153854.3-153855.53" + process $proc$libresoc.v:153854$8645 + assign { } { } + assign $0\sr_op__input_carry[1:0] \sr_op__input_carry$next + sync posedge \coresync_clk + update \sr_op__input_carry $0\sr_op__input_carry[1:0] + end + attribute \src "libresoc.v:153856.3-153857.55" + process $proc$libresoc.v:153856$8646 + assign { } { } + assign $0\sr_op__output_carry[0:0] \sr_op__output_carry$next + sync posedge \coresync_clk + update \sr_op__output_carry $0\sr_op__output_carry[0:0] + end + attribute \src "libresoc.v:153858.3-153859.47" + process $proc$libresoc.v:153858$8647 + assign { } { } + assign $0\sr_op__input_cr[0:0] \sr_op__input_cr$next + sync posedge \coresync_clk + update \sr_op__input_cr $0\sr_op__input_cr[0:0] + end + attribute \src "libresoc.v:153860.3-153861.49" + process $proc$libresoc.v:153860$8648 + assign { } { } + assign $0\sr_op__output_cr[0:0] \sr_op__output_cr$next + sync posedge \coresync_clk + update \sr_op__output_cr $0\sr_op__output_cr[0:0] + end + attribute \src "libresoc.v:153862.3-153863.47" + process $proc$libresoc.v:153862$8649 + assign { } { } + assign $0\sr_op__is_32bit[0:0] \sr_op__is_32bit$next + sync posedge \coresync_clk + update \sr_op__is_32bit $0\sr_op__is_32bit[0:0] + end + attribute \src "libresoc.v:153864.3-153865.49" + process $proc$libresoc.v:153864$8650 + assign { } { } + assign $0\sr_op__is_signed[0:0] \sr_op__is_signed$next + sync posedge \coresync_clk + update \sr_op__is_signed $0\sr_op__is_signed[0:0] + end + attribute \src "libresoc.v:153866.3-153867.39" + process $proc$libresoc.v:153866$8651 + assign { } { } + assign $0\sr_op__insn[31:0] \sr_op__insn$next + sync posedge \coresync_clk + update \sr_op__insn $0\sr_op__insn[31:0] + end + attribute \src "libresoc.v:153868.3-153869.27" + process $proc$libresoc.v:153868$8652 + assign { } { } + assign $0\muxid[1:0] \muxid$next + sync posedge \coresync_clk + update \muxid $0\muxid[1:0] + end + attribute \src "libresoc.v:153870.3-153871.29" + process $proc$libresoc.v:153870$8653 + assign { } { } + assign $0\r_busy[0:0] \r_busy$next + sync posedge \coresync_clk + update \r_busy $0\r_busy[0:0] + end + attribute \src "libresoc.v:153970.3-153987.6" + process $proc$libresoc.v:153970$8654 + assign { } { } + assign { } { } + assign { } { } + assign $0\r_busy$next[0:0]$8655 $2\r_busy$next[0:0]$8657 + attribute \src "libresoc.v:153971.5-153971.29" + switch \initial + attribute \src "libresoc.v:153971.9-153971.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\r_busy$next[0:0]$8656 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\r_busy$next[0:0]$8656 1'0 + case + assign $1\r_busy$next[0:0]$8656 \r_busy + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r_busy$next[0:0]$8657 1'0 + case + assign $2\r_busy$next[0:0]$8657 $1\r_busy$next[0:0]$8656 + end + sync always + update \r_busy$next $0\r_busy$next[0:0]$8655 + end + attribute \src "libresoc.v:153988.3-154000.6" + process $proc$libresoc.v:153988$8658 + assign { } { } + assign { } { } + assign $0\muxid$next[1:0]$8659 $1\muxid$next[1:0]$8660 + attribute \src "libresoc.v:153989.5-153989.29" + switch \initial + attribute \src "libresoc.v:153989.9-153989.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\muxid$next[1:0]$8660 \muxid$64 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\muxid$next[1:0]$8660 \muxid$64 + case + assign $1\muxid$next[1:0]$8660 \muxid + end + sync always + update \muxid$next $0\muxid$next[1:0]$8659 + end + attribute \src "libresoc.v:154001.3-154040.6" + process $proc$libresoc.v:154001$8661 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\sr_op__fn_unit$next[11:0]$8662 $1\sr_op__fn_unit$next[11:0]$8678 + assign { } { } + assign { } { } + assign $0\sr_op__input_carry$next[1:0]$8665 $1\sr_op__input_carry$next[1:0]$8681 + assign $0\sr_op__input_cr$next[0:0]$8666 $1\sr_op__input_cr$next[0:0]$8682 + assign $0\sr_op__insn$next[31:0]$8667 $1\sr_op__insn$next[31:0]$8683 + assign $0\sr_op__insn_type$next[6:0]$8668 $1\sr_op__insn_type$next[6:0]$8684 + assign $0\sr_op__is_32bit$next[0:0]$8669 $1\sr_op__is_32bit$next[0:0]$8685 + assign $0\sr_op__is_signed$next[0:0]$8670 $1\sr_op__is_signed$next[0:0]$8686 + assign { } { } + assign { } { } + assign $0\sr_op__output_carry$next[0:0]$8673 $1\sr_op__output_carry$next[0:0]$8689 + assign $0\sr_op__output_cr$next[0:0]$8674 $1\sr_op__output_cr$next[0:0]$8690 + assign { } { } + assign { } { } + assign $0\sr_op__write_cr0$next[0:0]$8677 $1\sr_op__write_cr0$next[0:0]$8693 + assign $0\sr_op__imm_data__data$next[63:0]$8663 $2\sr_op__imm_data__data$next[63:0]$8694 + assign $0\sr_op__imm_data__ok$next[0:0]$8664 $2\sr_op__imm_data__ok$next[0:0]$8695 + assign $0\sr_op__oe__oe$next[0:0]$8671 $2\sr_op__oe__oe$next[0:0]$8696 + assign $0\sr_op__oe__ok$next[0:0]$8672 $2\sr_op__oe__ok$next[0:0]$8697 + assign $0\sr_op__rc__ok$next[0:0]$8675 $2\sr_op__rc__ok$next[0:0]$8698 + assign $0\sr_op__rc__rc$next[0:0]$8676 $2\sr_op__rc__rc$next[0:0]$8699 + attribute \src "libresoc.v:154002.5-154002.29" + switch \initial + attribute \src "libresoc.v:154002.9-154002.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\sr_op__insn$next[31:0]$8683 $1\sr_op__is_signed$next[0:0]$8686 $1\sr_op__is_32bit$next[0:0]$8685 $1\sr_op__output_cr$next[0:0]$8690 $1\sr_op__input_cr$next[0:0]$8682 $1\sr_op__output_carry$next[0:0]$8689 $1\sr_op__input_carry$next[1:0]$8681 $1\sr_op__write_cr0$next[0:0]$8693 $1\sr_op__oe__ok$next[0:0]$8688 $1\sr_op__oe__oe$next[0:0]$8687 $1\sr_op__rc__ok$next[0:0]$8691 $1\sr_op__rc__rc$next[0:0]$8692 $1\sr_op__imm_data__ok$next[0:0]$8680 $1\sr_op__imm_data__data$next[63:0]$8679 $1\sr_op__fn_unit$next[11:0]$8678 $1\sr_op__insn_type$next[6:0]$8684 } { \sr_op__insn$80 \sr_op__is_signed$79 \sr_op__is_32bit$78 \sr_op__output_cr$77 \sr_op__input_cr$76 \sr_op__output_carry$75 \sr_op__input_carry$74 \sr_op__write_cr0$73 \sr_op__oe__ok$72 \sr_op__oe__oe$71 \sr_op__rc__ok$70 \sr_op__rc__rc$69 \sr_op__imm_data__ok$68 \sr_op__imm_data__data$67 \sr_op__fn_unit$66 \sr_op__insn_type$65 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\sr_op__insn$next[31:0]$8683 $1\sr_op__is_signed$next[0:0]$8686 $1\sr_op__is_32bit$next[0:0]$8685 $1\sr_op__output_cr$next[0:0]$8690 $1\sr_op__input_cr$next[0:0]$8682 $1\sr_op__output_carry$next[0:0]$8689 $1\sr_op__input_carry$next[1:0]$8681 $1\sr_op__write_cr0$next[0:0]$8693 $1\sr_op__oe__ok$next[0:0]$8688 $1\sr_op__oe__oe$next[0:0]$8687 $1\sr_op__rc__ok$next[0:0]$8691 $1\sr_op__rc__rc$next[0:0]$8692 $1\sr_op__imm_data__ok$next[0:0]$8680 $1\sr_op__imm_data__data$next[63:0]$8679 $1\sr_op__fn_unit$next[11:0]$8678 $1\sr_op__insn_type$next[6:0]$8684 } { \sr_op__insn$80 \sr_op__is_signed$79 \sr_op__is_32bit$78 \sr_op__output_cr$77 \sr_op__input_cr$76 \sr_op__output_carry$75 \sr_op__input_carry$74 \sr_op__write_cr0$73 \sr_op__oe__ok$72 \sr_op__oe__oe$71 \sr_op__rc__ok$70 \sr_op__rc__rc$69 \sr_op__imm_data__ok$68 \sr_op__imm_data__data$67 \sr_op__fn_unit$66 \sr_op__insn_type$65 } + case + assign $1\sr_op__fn_unit$next[11:0]$8678 \sr_op__fn_unit + assign $1\sr_op__imm_data__data$next[63:0]$8679 \sr_op__imm_data__data + assign $1\sr_op__imm_data__ok$next[0:0]$8680 \sr_op__imm_data__ok + assign $1\sr_op__input_carry$next[1:0]$8681 \sr_op__input_carry + assign $1\sr_op__input_cr$next[0:0]$8682 \sr_op__input_cr + assign $1\sr_op__insn$next[31:0]$8683 \sr_op__insn + assign $1\sr_op__insn_type$next[6:0]$8684 \sr_op__insn_type + assign $1\sr_op__is_32bit$next[0:0]$8685 \sr_op__is_32bit + assign $1\sr_op__is_signed$next[0:0]$8686 \sr_op__is_signed + assign $1\sr_op__oe__oe$next[0:0]$8687 \sr_op__oe__oe + assign $1\sr_op__oe__ok$next[0:0]$8688 \sr_op__oe__ok + assign $1\sr_op__output_carry$next[0:0]$8689 \sr_op__output_carry + assign $1\sr_op__output_cr$next[0:0]$8690 \sr_op__output_cr + assign $1\sr_op__rc__ok$next[0:0]$8691 \sr_op__rc__ok + assign $1\sr_op__rc__rc$next[0:0]$8692 \sr_op__rc__rc + assign $1\sr_op__write_cr0$next[0:0]$8693 \sr_op__write_cr0 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $2\sr_op__imm_data__data$next[63:0]$8694 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\sr_op__imm_data__ok$next[0:0]$8695 1'0 + assign $2\sr_op__rc__rc$next[0:0]$8699 1'0 + assign $2\sr_op__rc__ok$next[0:0]$8698 1'0 + assign $2\sr_op__oe__oe$next[0:0]$8696 1'0 + assign $2\sr_op__oe__ok$next[0:0]$8697 1'0 + case + assign $2\sr_op__imm_data__data$next[63:0]$8694 $1\sr_op__imm_data__data$next[63:0]$8679 + assign $2\sr_op__imm_data__ok$next[0:0]$8695 $1\sr_op__imm_data__ok$next[0:0]$8680 + assign $2\sr_op__oe__oe$next[0:0]$8696 $1\sr_op__oe__oe$next[0:0]$8687 + assign $2\sr_op__oe__ok$next[0:0]$8697 $1\sr_op__oe__ok$next[0:0]$8688 + assign $2\sr_op__rc__ok$next[0:0]$8698 $1\sr_op__rc__ok$next[0:0]$8691 + assign $2\sr_op__rc__rc$next[0:0]$8699 $1\sr_op__rc__rc$next[0:0]$8692 + end + sync always + update \sr_op__fn_unit$next $0\sr_op__fn_unit$next[11:0]$8662 + update \sr_op__imm_data__data$next $0\sr_op__imm_data__data$next[63:0]$8663 + update \sr_op__imm_data__ok$next $0\sr_op__imm_data__ok$next[0:0]$8664 + update \sr_op__input_carry$next $0\sr_op__input_carry$next[1:0]$8665 + update \sr_op__input_cr$next $0\sr_op__input_cr$next[0:0]$8666 + update \sr_op__insn$next $0\sr_op__insn$next[31:0]$8667 + update \sr_op__insn_type$next $0\sr_op__insn_type$next[6:0]$8668 + update \sr_op__is_32bit$next $0\sr_op__is_32bit$next[0:0]$8669 + update \sr_op__is_signed$next $0\sr_op__is_signed$next[0:0]$8670 + update \sr_op__oe__oe$next $0\sr_op__oe__oe$next[0:0]$8671 + update \sr_op__oe__ok$next $0\sr_op__oe__ok$next[0:0]$8672 + update \sr_op__output_carry$next $0\sr_op__output_carry$next[0:0]$8673 + update \sr_op__output_cr$next $0\sr_op__output_cr$next[0:0]$8674 + update \sr_op__rc__ok$next $0\sr_op__rc__ok$next[0:0]$8675 + update \sr_op__rc__rc$next $0\sr_op__rc__rc$next[0:0]$8676 + update \sr_op__write_cr0$next $0\sr_op__write_cr0$next[0:0]$8677 + end + attribute \src "libresoc.v:154041.3-154059.6" + process $proc$libresoc.v:154041$8700 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\o$next[63:0]$8701 $1\o$next[63:0]$8703 + assign { } { } + assign $0\o_ok$next[0:0]$8702 $2\o_ok$next[0:0]$8705 + attribute \src "libresoc.v:154042.5-154042.29" + switch \initial + attribute \src "libresoc.v:154042.9-154042.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\o_ok$next[0:0]$8704 $1\o$next[63:0]$8703 } { \o_ok$82 \o$81 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\o_ok$next[0:0]$8704 $1\o$next[63:0]$8703 } { \o_ok$82 \o$81 } + case + assign $1\o$next[63:0]$8703 \o + assign $1\o_ok$next[0:0]$8704 \o_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\o_ok$next[0:0]$8705 1'0 + case + assign $2\o_ok$next[0:0]$8705 $1\o_ok$next[0:0]$8704 + end + sync always + update \o$next $0\o$next[63:0]$8701 + update \o_ok$next $0\o_ok$next[0:0]$8702 + end + attribute \src "libresoc.v:154060.3-154078.6" + process $proc$libresoc.v:154060$8706 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\cr_a$next[3:0]$8707 $1\cr_a$next[3:0]$8709 + assign { } { } + assign $0\cr_a_ok$next[0:0]$8708 $2\cr_a_ok$next[0:0]$8711 + attribute \src "libresoc.v:154061.5-154061.29" + switch \initial + attribute \src "libresoc.v:154061.9-154061.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\cr_a_ok$next[0:0]$8710 $1\cr_a$next[3:0]$8709 } { \cr_a_ok$84 \cr_a$83 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\cr_a_ok$next[0:0]$8710 $1\cr_a$next[3:0]$8709 } { \cr_a_ok$84 \cr_a$83 } + case + assign $1\cr_a$next[3:0]$8709 \cr_a + assign $1\cr_a_ok$next[0:0]$8710 \cr_a_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_a_ok$next[0:0]$8711 1'0 + case + assign $2\cr_a_ok$next[0:0]$8711 $1\cr_a_ok$next[0:0]$8710 + end + sync always + update \cr_a$next $0\cr_a$next[3:0]$8707 + update \cr_a_ok$next $0\cr_a_ok$next[0:0]$8708 + end + attribute \src "libresoc.v:154079.3-154097.6" + process $proc$libresoc.v:154079$8712 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\xer_so$next[0:0]$8713 $1\xer_so$next[0:0]$8715 + assign { } { } + assign $0\xer_so_ok$next[0:0]$8714 $2\xer_so_ok$next[0:0]$8717 + attribute \src "libresoc.v:154080.5-154080.29" + switch \initial + attribute \src "libresoc.v:154080.9-154080.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\xer_so_ok$next[0:0]$8716 $1\xer_so$next[0:0]$8715 } { \xer_so_ok$88 \xer_so$87 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\xer_so_ok$next[0:0]$8716 $1\xer_so$next[0:0]$8715 } { \xer_so_ok$88 \xer_so$87 } + case + assign $1\xer_so$next[0:0]$8715 \xer_so + assign $1\xer_so_ok$next[0:0]$8716 \xer_so_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\xer_so_ok$next[0:0]$8717 1'0 + case + assign $2\xer_so_ok$next[0:0]$8717 $1\xer_so_ok$next[0:0]$8716 + end + sync always + update \xer_so$next $0\xer_so$next[0:0]$8713 + update \xer_so_ok$next $0\xer_so_ok$next[0:0]$8714 + end + attribute \src "libresoc.v:154098.3-154116.6" + process $proc$libresoc.v:154098$8718 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\xer_ca$next[1:0]$8720 $1\xer_ca$next[1:0]$8722 + assign $0\xer_ca_ok$next[0:0]$8719 $2\xer_ca_ok$next[0:0]$8723 + attribute \src "libresoc.v:154099.5-154099.29" + switch \initial + attribute \src "libresoc.v:154099.9-154099.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\xer_ca_ok$next[0:0]$8721 $1\xer_ca$next[1:0]$8722 } { \xer_ca_ok$91 \xer_ca$90 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\xer_ca_ok$next[0:0]$8721 $1\xer_ca$next[1:0]$8722 } { \xer_ca_ok$91 \xer_ca$90 } + case + assign $1\xer_ca_ok$next[0:0]$8721 \xer_ca_ok + assign $1\xer_ca$next[1:0]$8722 \xer_ca + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\xer_ca_ok$next[0:0]$8723 1'0 + case + assign $2\xer_ca_ok$next[0:0]$8723 $1\xer_ca_ok$next[0:0]$8721 + end + sync always + update \xer_ca_ok$next $0\xer_ca_ok$next[0:0]$8719 + update \xer_ca$next $0\xer_ca$next[1:0]$8720 + end + connect \$62 $and$libresoc.v:153819$8627_Y + connect \cr_a$85 4'0000 + connect \cr_a_ok$86 1'0 + connect \xer_so_ok$89 1'0 + connect \xer_ca_ok$92 1'0 + connect \p_ready_o \n_i_rdy_data + connect \n_valid_o \r_busy + connect { \xer_ca_ok$91 \xer_ca$90 } { 1'0 \main_xer_ca } + connect { \xer_so_ok$88 \xer_so$87 } { 1'0 \main_xer_so$59 } + connect { \cr_a_ok$84 \cr_a$83 } 5'00000 + connect { \o_ok$82 \o$81 } { \main_o_ok \main_o } + connect { \sr_op__insn$80 \sr_op__is_signed$79 \sr_op__is_32bit$78 \sr_op__output_cr$77 \sr_op__input_cr$76 \sr_op__output_carry$75 \sr_op__input_carry$74 \sr_op__write_cr0$73 \sr_op__oe__ok$72 \sr_op__oe__oe$71 \sr_op__rc__ok$70 \sr_op__rc__rc$69 \sr_op__imm_data__ok$68 \sr_op__imm_data__data$67 \sr_op__fn_unit$66 \sr_op__insn_type$65 } { \main_sr_op__insn$58 \main_sr_op__is_signed$57 \main_sr_op__is_32bit$56 \main_sr_op__output_cr$55 \main_sr_op__input_cr$54 \main_sr_op__output_carry$53 \main_sr_op__input_carry$52 \main_sr_op__write_cr0$51 \main_sr_op__oe__ok$50 \main_sr_op__oe__oe$49 \main_sr_op__rc__ok$48 \main_sr_op__rc__rc$47 \main_sr_op__imm_data__ok$46 \main_sr_op__imm_data__data$45 \main_sr_op__fn_unit$44 \main_sr_op__insn_type$43 } + connect \muxid$64 \main_muxid$42 + connect \p_valid_i_p_ready_o \$62 + connect \n_i_rdy_data \n_ready_i + connect \p_valid_i$61 \p_valid_i + connect \xer_ca$60 \input_xer_ca$41 + connect \main_xer_so \input_xer_so$40 + connect \main_rc \input_rc$39 + connect \main_rb \input_rb$38 + connect \main_ra \input_ra$37 + connect { \main_sr_op__insn \main_sr_op__is_signed \main_sr_op__is_32bit \main_sr_op__output_cr \main_sr_op__input_cr \main_sr_op__output_carry \main_sr_op__input_carry \main_sr_op__write_cr0 \main_sr_op__oe__ok \main_sr_op__oe__oe \main_sr_op__rc__ok \main_sr_op__rc__rc \main_sr_op__imm_data__ok \main_sr_op__imm_data__data \main_sr_op__fn_unit \main_sr_op__insn_type } { \input_sr_op__insn$36 \input_sr_op__is_signed$35 \input_sr_op__is_32bit$34 \input_sr_op__output_cr$33 \input_sr_op__input_cr$32 \input_sr_op__output_carry$31 \input_sr_op__input_carry$30 \input_sr_op__write_cr0$29 \input_sr_op__oe__ok$28 \input_sr_op__oe__oe$27 \input_sr_op__rc__ok$26 \input_sr_op__rc__rc$25 \input_sr_op__imm_data__ok$24 \input_sr_op__imm_data__data$23 \input_sr_op__fn_unit$22 \input_sr_op__insn_type$21 } + connect \main_muxid \input_muxid$20 + connect \input_xer_ca \xer_ca$19 + connect \input_xer_so \xer_so$18 + connect \input_rc \rc + connect \input_rb \rb + connect \input_ra \ra + connect { \input_sr_op__insn \input_sr_op__is_signed \input_sr_op__is_32bit \input_sr_op__output_cr \input_sr_op__input_cr \input_sr_op__output_carry \input_sr_op__input_carry \input_sr_op__write_cr0 \input_sr_op__oe__ok \input_sr_op__oe__oe \input_sr_op__rc__ok \input_sr_op__rc__rc \input_sr_op__imm_data__ok \input_sr_op__imm_data__data \input_sr_op__fn_unit \input_sr_op__insn_type } { \sr_op__insn$17 \sr_op__is_signed$16 \sr_op__is_32bit$15 \sr_op__output_cr$14 \sr_op__input_cr$13 \sr_op__output_carry$12 \sr_op__input_carry$11 \sr_op__write_cr0$10 \sr_op__oe__ok$9 \sr_op__oe__oe$8 \sr_op__rc__ok$7 \sr_op__rc__rc$6 \sr_op__imm_data__ok$5 \sr_op__imm_data__data$4 \sr_op__fn_unit$3 \sr_op__insn_type$2 } + connect \input_muxid \muxid$1 +end +attribute \src "libresoc.v:154150.1-155320.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alu_alu0.pipe2" +attribute \generator "nMigen" +module \pipe2 + attribute \src "libresoc.v:155164.3-155205.6" + wire width 4 $0\alu_op__data_len$18$next[3:0]$8819 + attribute \src "libresoc.v:155061.3-155062.57" + wire width 4 $0\alu_op__data_len$18[3:0]$8805 + attribute \src "libresoc.v:154158.13-154158.41" + wire width 4 $0\alu_op__data_len$18[3:0]$8893 + attribute \src "libresoc.v:155164.3-155205.6" + wire width 12 $0\alu_op__fn_unit$3$next[11:0]$8820 + attribute \src "libresoc.v:155031.3-155032.53" + wire width 12 $0\alu_op__fn_unit$3[11:0]$8775 + attribute \src "libresoc.v:154193.14-154193.43" + wire width 12 $0\alu_op__fn_unit$3[11:0]$8895 + attribute \src "libresoc.v:155164.3-155205.6" + wire width 64 $0\alu_op__imm_data__data$4$next[63:0]$8821 + attribute \src "libresoc.v:155033.3-155034.67" + wire width 64 $0\alu_op__imm_data__data$4[63:0]$8777 + attribute \src "libresoc.v:154215.14-154215.63" + wire width 64 $0\alu_op__imm_data__data$4[63:0]$8897 + attribute \src "libresoc.v:155164.3-155205.6" + wire $0\alu_op__imm_data__ok$5$next[0:0]$8822 + attribute \src "libresoc.v:155035.3-155036.63" + wire $0\alu_op__imm_data__ok$5[0:0]$8779 + attribute \src "libresoc.v:154224.7-154224.38" + wire $0\alu_op__imm_data__ok$5[0:0]$8899 + attribute \src "libresoc.v:155164.3-155205.6" + wire width 2 $0\alu_op__input_carry$14$next[1:0]$8823 + attribute \src "libresoc.v:155053.3-155054.63" + wire width 2 $0\alu_op__input_carry$14[1:0]$8797 + attribute \src "libresoc.v:154241.13-154241.44" + wire width 2 $0\alu_op__input_carry$14[1:0]$8901 + attribute \src "libresoc.v:155164.3-155205.6" + wire width 32 $0\alu_op__insn$19$next[31:0]$8824 + attribute \src "libresoc.v:155063.3-155064.49" + wire width 32 $0\alu_op__insn$19[31:0]$8807 + attribute \src "libresoc.v:154254.14-154254.39" + wire width 32 $0\alu_op__insn$19[31:0]$8903 + attribute \src "libresoc.v:155164.3-155205.6" + wire width 7 $0\alu_op__insn_type$2$next[6:0]$8825 + attribute \src "libresoc.v:155029.3-155030.57" + wire width 7 $0\alu_op__insn_type$2[6:0]$8773 + attribute \src "libresoc.v:154411.13-154411.42" + wire width 7 $0\alu_op__insn_type$2[6:0]$8905 + attribute \src "libresoc.v:155164.3-155205.6" + wire $0\alu_op__invert_in$10$next[0:0]$8826 + attribute \src "libresoc.v:155045.3-155046.59" + wire $0\alu_op__invert_in$10[0:0]$8789 + attribute \src "libresoc.v:154494.7-154494.36" + wire $0\alu_op__invert_in$10[0:0]$8907 + attribute \src "libresoc.v:155164.3-155205.6" + wire $0\alu_op__invert_out$12$next[0:0]$8827 + attribute \src "libresoc.v:155049.3-155050.61" + wire $0\alu_op__invert_out$12[0:0]$8793 + attribute \src "libresoc.v:154503.7-154503.37" + wire $0\alu_op__invert_out$12[0:0]$8909 + attribute \src "libresoc.v:155164.3-155205.6" + wire $0\alu_op__is_32bit$16$next[0:0]$8828 + attribute \src "libresoc.v:155057.3-155058.57" + wire $0\alu_op__is_32bit$16[0:0]$8801 + attribute \src "libresoc.v:154512.7-154512.35" + wire $0\alu_op__is_32bit$16[0:0]$8911 + attribute \src "libresoc.v:155164.3-155205.6" + wire $0\alu_op__is_signed$17$next[0:0]$8829 + attribute \src "libresoc.v:155059.3-155060.59" + wire $0\alu_op__is_signed$17[0:0]$8803 + attribute \src "libresoc.v:154521.7-154521.36" + wire $0\alu_op__is_signed$17[0:0]$8913 + attribute \src "libresoc.v:155164.3-155205.6" + wire $0\alu_op__oe__oe$8$next[0:0]$8830 + attribute \src "libresoc.v:155041.3-155042.51" + wire $0\alu_op__oe__oe$8[0:0]$8785 + attribute \src "libresoc.v:154532.7-154532.32" + wire $0\alu_op__oe__oe$8[0:0]$8915 + attribute \src "libresoc.v:155164.3-155205.6" + wire $0\alu_op__oe__ok$9$next[0:0]$8831 + attribute \src "libresoc.v:155043.3-155044.51" + wire $0\alu_op__oe__ok$9[0:0]$8787 + attribute \src "libresoc.v:154541.7-154541.32" + wire $0\alu_op__oe__ok$9[0:0]$8917 + attribute \src "libresoc.v:155164.3-155205.6" + wire $0\alu_op__output_carry$15$next[0:0]$8832 + attribute \src "libresoc.v:155055.3-155056.65" + wire $0\alu_op__output_carry$15[0:0]$8799 + attribute \src "libresoc.v:154548.7-154548.39" + wire $0\alu_op__output_carry$15[0:0]$8919 + attribute \src "libresoc.v:155164.3-155205.6" + wire $0\alu_op__rc__ok$7$next[0:0]$8833 + attribute \src "libresoc.v:155039.3-155040.51" + wire $0\alu_op__rc__ok$7[0:0]$8783 + attribute \src "libresoc.v:154559.7-154559.32" + wire $0\alu_op__rc__ok$7[0:0]$8921 + attribute \src "libresoc.v:155164.3-155205.6" + wire $0\alu_op__rc__rc$6$next[0:0]$8834 + attribute \src "libresoc.v:155037.3-155038.51" + wire $0\alu_op__rc__rc$6[0:0]$8781 + attribute \src "libresoc.v:154566.7-154566.32" + wire $0\alu_op__rc__rc$6[0:0]$8923 + attribute \src "libresoc.v:155164.3-155205.6" + wire $0\alu_op__write_cr0$13$next[0:0]$8835 + attribute \src "libresoc.v:155051.3-155052.59" + wire $0\alu_op__write_cr0$13[0:0]$8795 + attribute \src "libresoc.v:154575.7-154575.36" + wire $0\alu_op__write_cr0$13[0:0]$8925 + attribute \src "libresoc.v:155164.3-155205.6" + wire $0\alu_op__zero_a$11$next[0:0]$8836 + attribute \src "libresoc.v:155047.3-155048.53" + wire $0\alu_op__zero_a$11[0:0]$8791 + attribute \src "libresoc.v:154584.7-154584.33" + wire $0\alu_op__zero_a$11[0:0]$8927 + attribute \src "libresoc.v:155225.3-155243.6" + wire width 4 $0\cr_a$22$next[3:0]$8868 + attribute \src "libresoc.v:155021.3-155022.33" + wire width 4 $0\cr_a$22[3:0]$8765 + attribute \src "libresoc.v:154597.13-154597.29" + wire width 4 $0\cr_a$22[3:0]$8929 + attribute \src "libresoc.v:155225.3-155243.6" + wire $0\cr_a_ok$23$next[0:0]$8869 + attribute \src "libresoc.v:155023.3-155024.39" + wire $0\cr_a_ok$23[0:0]$8767 + attribute \src "libresoc.v:154606.7-154606.26" + wire $0\cr_a_ok$23[0:0]$8931 + attribute \src "libresoc.v:154151.7-154151.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:155151.3-155163.6" + wire width 2 $0\muxid$1$next[1:0]$8816 + attribute \src "libresoc.v:155065.3-155066.33" + wire width 2 $0\muxid$1[1:0]$8809 + attribute \src "libresoc.v:154617.13-154617.29" + wire width 2 $0\muxid$1[1:0]$8933 + attribute \src "libresoc.v:155206.3-155224.6" + wire width 64 $0\o$20$next[63:0]$8862 + attribute \src "libresoc.v:155025.3-155026.27" + wire width 64 $0\o$20[63:0]$8769 + attribute \src "libresoc.v:154632.14-154632.43" + wire width 64 $0\o$20[63:0]$8935 + attribute \src "libresoc.v:155206.3-155224.6" + wire $0\o_ok$21$next[0:0]$8863 + attribute \src "libresoc.v:155027.3-155028.33" + wire $0\o_ok$21[0:0]$8771 + attribute \src "libresoc.v:154641.7-154641.23" + wire $0\o_ok$21[0:0]$8937 + attribute \src "libresoc.v:155133.3-155150.6" + wire $0\r_busy$next[0:0]$8812 + attribute \src "libresoc.v:155067.3-155068.29" + wire $0\r_busy[0:0] + attribute \src "libresoc.v:155244.3-155262.6" + wire width 2 $0\xer_ca$24$next[1:0]$8874 + attribute \src "libresoc.v:155017.3-155018.37" + wire width 2 $0\xer_ca$24[1:0]$8761 + attribute \src "libresoc.v:154952.13-154952.31" + wire width 2 $0\xer_ca$24[1:0]$8940 + attribute \src "libresoc.v:155244.3-155262.6" + wire $0\xer_ca_ok$25$next[0:0]$8875 + attribute \src "libresoc.v:155019.3-155020.43" + wire $0\xer_ca_ok$25[0:0]$8763 + attribute \src "libresoc.v:154961.7-154961.28" + wire $0\xer_ca_ok$25[0:0]$8942 + attribute \src "libresoc.v:155263.3-155281.6" + wire width 2 $0\xer_ov$26$next[1:0]$8880 + attribute \src "libresoc.v:155013.3-155014.37" + wire width 2 $0\xer_ov$26[1:0]$8757 + attribute \src "libresoc.v:154972.13-154972.31" + wire width 2 $0\xer_ov$26[1:0]$8944 + attribute \src "libresoc.v:155263.3-155281.6" + wire $0\xer_ov_ok$27$next[0:0]$8881 + attribute \src "libresoc.v:155015.3-155016.43" + wire $0\xer_ov_ok$27[0:0]$8759 + attribute \src "libresoc.v:154981.7-154981.28" + wire $0\xer_ov_ok$27[0:0]$8946 + attribute \src "libresoc.v:155282.3-155300.6" + wire $0\xer_so$28$next[0:0]$8886 + attribute \src "libresoc.v:155009.3-155010.37" + wire $0\xer_so$28[0:0]$8753 + attribute \src "libresoc.v:154992.7-154992.25" + wire $0\xer_so$28[0:0]$8948 + attribute \src "libresoc.v:155282.3-155300.6" + wire $0\xer_so_ok$29$next[0:0]$8887 + attribute \src "libresoc.v:155011.3-155012.43" + wire $0\xer_so_ok$29[0:0]$8755 + attribute \src "libresoc.v:155001.7-155001.28" + wire $0\xer_so_ok$29[0:0]$8950 + attribute \src "libresoc.v:155164.3-155205.6" + wire width 4 $1\alu_op__data_len$18$next[3:0]$8837 + attribute \src "libresoc.v:155164.3-155205.6" + wire width 12 $1\alu_op__fn_unit$3$next[11:0]$8838 + attribute \src "libresoc.v:155164.3-155205.6" + wire width 64 $1\alu_op__imm_data__data$4$next[63:0]$8839 + attribute \src "libresoc.v:155164.3-155205.6" + wire $1\alu_op__imm_data__ok$5$next[0:0]$8840 + attribute \src "libresoc.v:155164.3-155205.6" + wire width 2 $1\alu_op__input_carry$14$next[1:0]$8841 + attribute \src "libresoc.v:155164.3-155205.6" + wire width 32 $1\alu_op__insn$19$next[31:0]$8842 + attribute \src "libresoc.v:155164.3-155205.6" + wire width 7 $1\alu_op__insn_type$2$next[6:0]$8843 + attribute \src "libresoc.v:155164.3-155205.6" + wire $1\alu_op__invert_in$10$next[0:0]$8844 + attribute \src "libresoc.v:155164.3-155205.6" + wire $1\alu_op__invert_out$12$next[0:0]$8845 + attribute \src "libresoc.v:155164.3-155205.6" + wire $1\alu_op__is_32bit$16$next[0:0]$8846 + attribute \src "libresoc.v:155164.3-155205.6" + wire $1\alu_op__is_signed$17$next[0:0]$8847 + attribute \src "libresoc.v:155164.3-155205.6" + wire $1\alu_op__oe__oe$8$next[0:0]$8848 + attribute \src "libresoc.v:155164.3-155205.6" + wire $1\alu_op__oe__ok$9$next[0:0]$8849 + attribute \src "libresoc.v:155164.3-155205.6" + wire $1\alu_op__output_carry$15$next[0:0]$8850 + attribute \src "libresoc.v:155164.3-155205.6" + wire $1\alu_op__rc__ok$7$next[0:0]$8851 + attribute \src "libresoc.v:155164.3-155205.6" + wire $1\alu_op__rc__rc$6$next[0:0]$8852 + attribute \src "libresoc.v:155164.3-155205.6" + wire $1\alu_op__write_cr0$13$next[0:0]$8853 + attribute \src "libresoc.v:155164.3-155205.6" + wire $1\alu_op__zero_a$11$next[0:0]$8854 + attribute \src "libresoc.v:155225.3-155243.6" + wire width 4 $1\cr_a$22$next[3:0]$8870 + attribute \src "libresoc.v:155225.3-155243.6" + wire $1\cr_a_ok$23$next[0:0]$8871 + attribute \src "libresoc.v:155151.3-155163.6" + wire width 2 $1\muxid$1$next[1:0]$8817 + attribute \src "libresoc.v:155206.3-155224.6" + wire width 64 $1\o$20$next[63:0]$8864 + attribute \src "libresoc.v:155206.3-155224.6" + wire $1\o_ok$21$next[0:0]$8865 + attribute \src "libresoc.v:155133.3-155150.6" + wire $1\r_busy$next[0:0]$8813 + attribute \src "libresoc.v:154945.7-154945.20" + wire $1\r_busy[0:0] + attribute \src "libresoc.v:155244.3-155262.6" + wire width 2 $1\xer_ca$24$next[1:0]$8876 + attribute \src "libresoc.v:155244.3-155262.6" + wire $1\xer_ca_ok$25$next[0:0]$8877 + attribute \src "libresoc.v:155263.3-155281.6" + wire width 2 $1\xer_ov$26$next[1:0]$8882 + attribute \src "libresoc.v:155263.3-155281.6" + wire $1\xer_ov_ok$27$next[0:0]$8883 + attribute \src "libresoc.v:155282.3-155300.6" + wire $1\xer_so$28$next[0:0]$8888 + attribute \src "libresoc.v:155282.3-155300.6" + wire $1\xer_so_ok$29$next[0:0]$8889 + attribute \src "libresoc.v:155164.3-155205.6" + wire width 64 $2\alu_op__imm_data__data$4$next[63:0]$8855 + attribute \src "libresoc.v:155164.3-155205.6" + wire $2\alu_op__imm_data__ok$5$next[0:0]$8856 + attribute \src "libresoc.v:155164.3-155205.6" + wire $2\alu_op__oe__oe$8$next[0:0]$8857 + attribute \src "libresoc.v:155164.3-155205.6" + wire $2\alu_op__oe__ok$9$next[0:0]$8858 + attribute \src "libresoc.v:155164.3-155205.6" + wire $2\alu_op__rc__ok$7$next[0:0]$8859 + attribute \src "libresoc.v:155164.3-155205.6" + wire $2\alu_op__rc__rc$6$next[0:0]$8860 + attribute \src "libresoc.v:155225.3-155243.6" + wire $2\cr_a_ok$23$next[0:0]$8872 + attribute \src "libresoc.v:155206.3-155224.6" + wire $2\o_ok$21$next[0:0]$8866 + attribute \src "libresoc.v:155133.3-155150.6" + wire $2\r_busy$next[0:0]$8814 + attribute \src "libresoc.v:155244.3-155262.6" + wire $2\xer_ca_ok$25$next[0:0]$8878 + attribute \src "libresoc.v:155263.3-155281.6" + wire $2\xer_ov_ok$27$next[0:0]$8884 + attribute \src "libresoc.v:155282.3-155300.6" + wire $2\xer_so_ok$29$next[0:0]$8890 + attribute \src "libresoc.v:155008.18-155008.118" + wire $and$libresoc.v:155008$8751_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + wire \$60 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 21 \alu_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 52 \alu_op__data_len$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \alu_op__data_len$18$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \alu_op__data_len$79 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 6 \alu_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 output 37 \alu_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \alu_op__fn_unit$3$next + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \alu_op__fn_unit$64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 7 \alu_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 38 \alu_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \alu_op__imm_data__data$4$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \alu_op__imm_data__data$65 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \alu_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 39 \alu_op__imm_data__ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__imm_data__ok$5$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__imm_data__ok$66 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 17 \alu_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 48 \alu_op__input_carry$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \alu_op__input_carry$14$next + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \alu_op__input_carry$75 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 22 \alu_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 53 \alu_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \alu_op__insn$19$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \alu_op__insn$80 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 5 \alu_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 36 \alu_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \alu_op__insn_type$2$next + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \alu_op__insn_type$63 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \alu_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 44 \alu_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__invert_in$10$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__invert_in$71 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 15 \alu_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 46 \alu_op__invert_out$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__invert_out$12$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__invert_out$73 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 19 \alu_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 50 \alu_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__is_32bit$16$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__is_32bit$77 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 20 \alu_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 51 \alu_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__is_signed$17$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__is_signed$78 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 11 \alu_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__oe__oe$69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 42 \alu_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__oe__oe$8$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \alu_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__oe__ok$70 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 43 \alu_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__oe__ok$9$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 18 \alu_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 49 \alu_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__output_carry$15$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__output_carry$76 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \alu_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__rc__ok$68 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 41 \alu_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__rc__ok$7$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \alu_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 40 \alu_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__rc__rc$6$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__rc__rc$67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 16 \alu_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 47 \alu_op__write_cr0$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__write_cr0$13$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__write_cr0$74 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \alu_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 45 \alu_op__zero_a$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__zero_a$11$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__zero_a$72 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 64 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 input 25 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 output 56 \cr_a$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \cr_a$22$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \cr_a$83 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire input 26 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 57 \cr_a_ok$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_a_ok$23$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_a_ok$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_a_ok$84 + attribute \src "libresoc.v:154151.7-154151.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 4 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 35 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$1$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$62 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" + wire \n_i_rdy_data + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire input 34 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire output 33 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 input 23 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 54 \o$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \o$20$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \o$81 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire input 24 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 55 \o_ok$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \o_ok$21$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \o_ok$82 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \output_alu_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \output_alu_op__data_len$47 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \output_alu_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \output_alu_op__fn_unit$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \output_alu_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \output_alu_op__imm_data__data$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_alu_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_alu_op__imm_data__ok$34 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \output_alu_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \output_alu_op__input_carry$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \output_alu_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \output_alu_op__insn$48 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \output_alu_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \output_alu_op__insn_type$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_alu_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_alu_op__invert_in$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_alu_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_alu_op__invert_out$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_alu_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_alu_op__is_32bit$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_alu_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_alu_op__is_signed$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_alu_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_alu_op__oe__oe$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_alu_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_alu_op__oe__ok$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_alu_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_alu_op__output_carry$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_alu_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_alu_op__rc__ok$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_alu_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_alu_op__rc__rc$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_alu_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_alu_op__write_cr0$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_alu_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_alu_op__zero_a$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \output_cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \output_cr_a$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \output_cr_a_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \output_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \output_muxid$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \output_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \output_o$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \output_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \output_o_ok$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \output_xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \output_xer_ca$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \output_xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \output_xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \output_xer_ov$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \output_xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \output_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \output_xer_so$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \output_xer_so_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire output 3 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" + wire \p_valid_i$59 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire \r_busy$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 input 27 \xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 output 58 \xer_ca$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \xer_ca$24$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \xer_ca$85 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire input 28 \xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 59 \xer_ca_ok$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \xer_ca_ok$25$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \xer_ca_ok$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \xer_ca_ok$86 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 input 29 \xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 output 60 \xer_ov$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \xer_ov$26$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \xer_ov$87 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire input 30 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 61 \xer_ov_ok$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \xer_ov_ok$27$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \xer_ov_ok$57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \xer_ov_ok$88 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire input 31 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 62 \xer_so$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \xer_so$28$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \xer_so$89 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire input 32 \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 63 \xer_so_ok$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \xer_so_ok$29$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \xer_so_ok$58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \xer_so_ok$90 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + cell $and $and$libresoc.v:155008$8751 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i$59 + connect \B \p_ready_o + connect \Y $and$libresoc.v:155008$8751_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:155069.9-155072.4" + cell \n$4 \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:155073.12-155128.4" + cell \output \output + connect \alu_op__data_len \output_alu_op__data_len + connect \alu_op__data_len$18 \output_alu_op__data_len$47 + connect \alu_op__fn_unit \output_alu_op__fn_unit + connect \alu_op__fn_unit$3 \output_alu_op__fn_unit$32 + connect \alu_op__imm_data__data \output_alu_op__imm_data__data + connect \alu_op__imm_data__data$4 \output_alu_op__imm_data__data$33 + connect \alu_op__imm_data__ok \output_alu_op__imm_data__ok + connect \alu_op__imm_data__ok$5 \output_alu_op__imm_data__ok$34 + connect \alu_op__input_carry \output_alu_op__input_carry + connect \alu_op__input_carry$14 \output_alu_op__input_carry$43 + connect \alu_op__insn \output_alu_op__insn + connect \alu_op__insn$19 \output_alu_op__insn$48 + connect \alu_op__insn_type \output_alu_op__insn_type + connect \alu_op__insn_type$2 \output_alu_op__insn_type$31 + connect \alu_op__invert_in \output_alu_op__invert_in + connect \alu_op__invert_in$10 \output_alu_op__invert_in$39 + connect \alu_op__invert_out \output_alu_op__invert_out + connect \alu_op__invert_out$12 \output_alu_op__invert_out$41 + connect \alu_op__is_32bit \output_alu_op__is_32bit + connect \alu_op__is_32bit$16 \output_alu_op__is_32bit$45 + connect \alu_op__is_signed \output_alu_op__is_signed + connect \alu_op__is_signed$17 \output_alu_op__is_signed$46 + connect \alu_op__oe__oe \output_alu_op__oe__oe + connect \alu_op__oe__oe$8 \output_alu_op__oe__oe$37 + connect \alu_op__oe__ok \output_alu_op__oe__ok + connect \alu_op__oe__ok$9 \output_alu_op__oe__ok$38 + connect \alu_op__output_carry \output_alu_op__output_carry + connect \alu_op__output_carry$15 \output_alu_op__output_carry$44 + connect \alu_op__rc__ok \output_alu_op__rc__ok + connect \alu_op__rc__ok$7 \output_alu_op__rc__ok$36 + connect \alu_op__rc__rc \output_alu_op__rc__rc + connect \alu_op__rc__rc$6 \output_alu_op__rc__rc$35 + connect \alu_op__write_cr0 \output_alu_op__write_cr0 + connect \alu_op__write_cr0$13 \output_alu_op__write_cr0$42 + connect \alu_op__zero_a \output_alu_op__zero_a + connect \alu_op__zero_a$11 \output_alu_op__zero_a$40 + connect \cr_a \output_cr_a + connect \cr_a$22 \output_cr_a$51 + connect \cr_a_ok \output_cr_a_ok + connect \muxid \output_muxid + connect \muxid$1 \output_muxid$30 + connect \o \output_o + connect \o$20 \output_o$49 + connect \o_ok \output_o_ok + connect \o_ok$21 \output_o_ok$50 + connect \xer_ca \output_xer_ca + connect \xer_ca$23 \output_xer_ca$52 + connect \xer_ca_ok \output_xer_ca_ok + connect \xer_ov \output_xer_ov + connect \xer_ov$24 \output_xer_ov$53 + connect \xer_ov_ok \output_xer_ov_ok + connect \xer_so \output_xer_so + connect \xer_so$25 \output_xer_so$54 + connect \xer_so_ok \output_xer_so_ok + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:155129.9-155132.4" + cell \p$3 \p + connect \p_ready_o \p_ready_o + connect \p_valid_i \p_valid_i + end + attribute \src "libresoc.v:154151.7-154151.20" + process $proc$libresoc.v:154151$8891 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:154158.13-154158.41" + process $proc$libresoc.v:154158$8892 + assign { } { } + assign $0\alu_op__data_len$18[3:0]$8893 4'0000 + sync always + sync init + update \alu_op__data_len$18 $0\alu_op__data_len$18[3:0]$8893 + end + attribute \src "libresoc.v:154193.14-154193.43" + process $proc$libresoc.v:154193$8894 + assign { } { } + assign $0\alu_op__fn_unit$3[11:0]$8895 12'000000000000 + sync always + sync init + update \alu_op__fn_unit$3 $0\alu_op__fn_unit$3[11:0]$8895 + end + attribute \src "libresoc.v:154215.14-154215.63" + process $proc$libresoc.v:154215$8896 + assign { } { } + assign $0\alu_op__imm_data__data$4[63:0]$8897 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \alu_op__imm_data__data$4 $0\alu_op__imm_data__data$4[63:0]$8897 + end + attribute \src "libresoc.v:154224.7-154224.38" + process $proc$libresoc.v:154224$8898 + assign { } { } + assign $0\alu_op__imm_data__ok$5[0:0]$8899 1'0 + sync always + sync init + update \alu_op__imm_data__ok$5 $0\alu_op__imm_data__ok$5[0:0]$8899 + end + attribute \src "libresoc.v:154241.13-154241.44" + process $proc$libresoc.v:154241$8900 + assign { } { } + assign $0\alu_op__input_carry$14[1:0]$8901 2'00 + sync always + sync init + update \alu_op__input_carry$14 $0\alu_op__input_carry$14[1:0]$8901 + end + attribute \src "libresoc.v:154254.14-154254.39" + process $proc$libresoc.v:154254$8902 + assign { } { } + assign $0\alu_op__insn$19[31:0]$8903 0 + sync always + sync init + update \alu_op__insn$19 $0\alu_op__insn$19[31:0]$8903 + end + attribute \src "libresoc.v:154411.13-154411.42" + process $proc$libresoc.v:154411$8904 + assign { } { } + assign $0\alu_op__insn_type$2[6:0]$8905 7'0000000 + sync always + sync init + update \alu_op__insn_type$2 $0\alu_op__insn_type$2[6:0]$8905 + end + attribute \src "libresoc.v:154494.7-154494.36" + process $proc$libresoc.v:154494$8906 + assign { } { } + assign $0\alu_op__invert_in$10[0:0]$8907 1'0 + sync always + sync init + update \alu_op__invert_in$10 $0\alu_op__invert_in$10[0:0]$8907 + end + attribute \src "libresoc.v:154503.7-154503.37" + process $proc$libresoc.v:154503$8908 + assign { } { } + assign $0\alu_op__invert_out$12[0:0]$8909 1'0 + sync always + sync init + update \alu_op__invert_out$12 $0\alu_op__invert_out$12[0:0]$8909 + end + attribute \src "libresoc.v:154512.7-154512.35" + process $proc$libresoc.v:154512$8910 + assign { } { } + assign $0\alu_op__is_32bit$16[0:0]$8911 1'0 + sync always + sync init + update \alu_op__is_32bit$16 $0\alu_op__is_32bit$16[0:0]$8911 + end + attribute \src "libresoc.v:154521.7-154521.36" + process $proc$libresoc.v:154521$8912 + assign { } { } + assign $0\alu_op__is_signed$17[0:0]$8913 1'0 + sync always + sync init + update \alu_op__is_signed$17 $0\alu_op__is_signed$17[0:0]$8913 + end + attribute \src "libresoc.v:154532.7-154532.32" + process $proc$libresoc.v:154532$8914 + assign { } { } + assign $0\alu_op__oe__oe$8[0:0]$8915 1'0 + sync always + sync init + update \alu_op__oe__oe$8 $0\alu_op__oe__oe$8[0:0]$8915 + end + attribute \src "libresoc.v:154541.7-154541.32" + process $proc$libresoc.v:154541$8916 + assign { } { } + assign $0\alu_op__oe__ok$9[0:0]$8917 1'0 + sync always + sync init + update \alu_op__oe__ok$9 $0\alu_op__oe__ok$9[0:0]$8917 + end + attribute \src "libresoc.v:154548.7-154548.39" + process $proc$libresoc.v:154548$8918 + assign { } { } + assign $0\alu_op__output_carry$15[0:0]$8919 1'0 + sync always + sync init + update \alu_op__output_carry$15 $0\alu_op__output_carry$15[0:0]$8919 + end + attribute \src "libresoc.v:154559.7-154559.32" + process $proc$libresoc.v:154559$8920 + assign { } { } + assign $0\alu_op__rc__ok$7[0:0]$8921 1'0 + sync always + sync init + update \alu_op__rc__ok$7 $0\alu_op__rc__ok$7[0:0]$8921 + end + attribute \src "libresoc.v:154566.7-154566.32" + process $proc$libresoc.v:154566$8922 + assign { } { } + assign $0\alu_op__rc__rc$6[0:0]$8923 1'0 + sync always + sync init + update \alu_op__rc__rc$6 $0\alu_op__rc__rc$6[0:0]$8923 + end + attribute \src "libresoc.v:154575.7-154575.36" + process $proc$libresoc.v:154575$8924 + assign { } { } + assign $0\alu_op__write_cr0$13[0:0]$8925 1'0 + sync always + sync init + update \alu_op__write_cr0$13 $0\alu_op__write_cr0$13[0:0]$8925 + end + attribute \src "libresoc.v:154584.7-154584.33" + process $proc$libresoc.v:154584$8926 + assign { } { } + assign $0\alu_op__zero_a$11[0:0]$8927 1'0 + sync always + sync init + update \alu_op__zero_a$11 $0\alu_op__zero_a$11[0:0]$8927 + end + attribute \src "libresoc.v:154597.13-154597.29" + process $proc$libresoc.v:154597$8928 + assign { } { } + assign $0\cr_a$22[3:0]$8929 4'0000 + sync always + sync init + update \cr_a$22 $0\cr_a$22[3:0]$8929 + end + attribute \src "libresoc.v:154606.7-154606.26" + process $proc$libresoc.v:154606$8930 + assign { } { } + assign $0\cr_a_ok$23[0:0]$8931 1'0 + sync always + sync init + update \cr_a_ok$23 $0\cr_a_ok$23[0:0]$8931 + end + attribute \src "libresoc.v:154617.13-154617.29" + process $proc$libresoc.v:154617$8932 + assign { } { } + assign $0\muxid$1[1:0]$8933 2'00 + sync always + sync init + update \muxid$1 $0\muxid$1[1:0]$8933 + end + attribute \src "libresoc.v:154632.14-154632.43" + process $proc$libresoc.v:154632$8934 + assign { } { } + assign $0\o$20[63:0]$8935 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \o$20 $0\o$20[63:0]$8935 + end + attribute \src "libresoc.v:154641.7-154641.23" + process $proc$libresoc.v:154641$8936 + assign { } { } + assign $0\o_ok$21[0:0]$8937 1'0 + sync always + sync init + update \o_ok$21 $0\o_ok$21[0:0]$8937 + end + attribute \src "libresoc.v:154945.7-154945.20" + process $proc$libresoc.v:154945$8938 + assign { } { } + assign $1\r_busy[0:0] 1'0 + sync always + sync init + update \r_busy $1\r_busy[0:0] + end + attribute \src "libresoc.v:154952.13-154952.31" + process $proc$libresoc.v:154952$8939 + assign { } { } + assign $0\xer_ca$24[1:0]$8940 2'00 + sync always + sync init + update \xer_ca$24 $0\xer_ca$24[1:0]$8940 + end + attribute \src "libresoc.v:154961.7-154961.28" + process $proc$libresoc.v:154961$8941 + assign { } { } + assign $0\xer_ca_ok$25[0:0]$8942 1'0 + sync always + sync init + update \xer_ca_ok$25 $0\xer_ca_ok$25[0:0]$8942 + end + attribute \src "libresoc.v:154972.13-154972.31" + process $proc$libresoc.v:154972$8943 + assign { } { } + assign $0\xer_ov$26[1:0]$8944 2'00 + sync always + sync init + update \xer_ov$26 $0\xer_ov$26[1:0]$8944 + end + attribute \src "libresoc.v:154981.7-154981.28" + process $proc$libresoc.v:154981$8945 + assign { } { } + assign $0\xer_ov_ok$27[0:0]$8946 1'0 + sync always + sync init + update \xer_ov_ok$27 $0\xer_ov_ok$27[0:0]$8946 + end + attribute \src "libresoc.v:154992.7-154992.25" + process $proc$libresoc.v:154992$8947 + assign { } { } + assign $0\xer_so$28[0:0]$8948 1'0 + sync always + sync init + update \xer_so$28 $0\xer_so$28[0:0]$8948 + end + attribute \src "libresoc.v:155001.7-155001.28" + process $proc$libresoc.v:155001$8949 + assign { } { } + assign $0\xer_so_ok$29[0:0]$8950 1'0 + sync always + sync init + update \xer_so_ok$29 $0\xer_so_ok$29[0:0]$8950 + end + attribute \src "libresoc.v:155009.3-155010.37" + process $proc$libresoc.v:155009$8752 + assign { } { } + assign $0\xer_so$28[0:0]$8753 \xer_so$28$next + sync posedge \coresync_clk + update \xer_so$28 $0\xer_so$28[0:0]$8753 + end + attribute \src "libresoc.v:155011.3-155012.43" + process $proc$libresoc.v:155011$8754 + assign { } { } + assign $0\xer_so_ok$29[0:0]$8755 \xer_so_ok$29$next + sync posedge \coresync_clk + update \xer_so_ok$29 $0\xer_so_ok$29[0:0]$8755 + end + attribute \src "libresoc.v:155013.3-155014.37" + process $proc$libresoc.v:155013$8756 + assign { } { } + assign $0\xer_ov$26[1:0]$8757 \xer_ov$26$next + sync posedge \coresync_clk + update \xer_ov$26 $0\xer_ov$26[1:0]$8757 + end + attribute \src "libresoc.v:155015.3-155016.43" + process $proc$libresoc.v:155015$8758 + assign { } { } + assign $0\xer_ov_ok$27[0:0]$8759 \xer_ov_ok$27$next + sync posedge \coresync_clk + update \xer_ov_ok$27 $0\xer_ov_ok$27[0:0]$8759 + end + attribute \src "libresoc.v:155017.3-155018.37" + process $proc$libresoc.v:155017$8760 + assign { } { } + assign $0\xer_ca$24[1:0]$8761 \xer_ca$24$next + sync posedge \coresync_clk + update \xer_ca$24 $0\xer_ca$24[1:0]$8761 + end + attribute \src "libresoc.v:155019.3-155020.43" + process $proc$libresoc.v:155019$8762 + assign { } { } + assign $0\xer_ca_ok$25[0:0]$8763 \xer_ca_ok$25$next + sync posedge \coresync_clk + update \xer_ca_ok$25 $0\xer_ca_ok$25[0:0]$8763 + end + attribute \src "libresoc.v:155021.3-155022.33" + process $proc$libresoc.v:155021$8764 + assign { } { } + assign $0\cr_a$22[3:0]$8765 \cr_a$22$next + sync posedge \coresync_clk + update \cr_a$22 $0\cr_a$22[3:0]$8765 + end + attribute \src "libresoc.v:155023.3-155024.39" + process $proc$libresoc.v:155023$8766 + assign { } { } + assign $0\cr_a_ok$23[0:0]$8767 \cr_a_ok$23$next + sync posedge \coresync_clk + update \cr_a_ok$23 $0\cr_a_ok$23[0:0]$8767 + end + attribute \src "libresoc.v:155025.3-155026.27" + process $proc$libresoc.v:155025$8768 + assign { } { } + assign $0\o$20[63:0]$8769 \o$20$next + sync posedge \coresync_clk + update \o$20 $0\o$20[63:0]$8769 + end + attribute \src "libresoc.v:155027.3-155028.33" + process $proc$libresoc.v:155027$8770 + assign { } { } + assign $0\o_ok$21[0:0]$8771 \o_ok$21$next + sync posedge \coresync_clk + update \o_ok$21 $0\o_ok$21[0:0]$8771 + end + attribute \src "libresoc.v:155029.3-155030.57" + process $proc$libresoc.v:155029$8772 + assign { } { } + assign $0\alu_op__insn_type$2[6:0]$8773 \alu_op__insn_type$2$next + sync posedge \coresync_clk + update \alu_op__insn_type$2 $0\alu_op__insn_type$2[6:0]$8773 + end + attribute \src "libresoc.v:155031.3-155032.53" + process $proc$libresoc.v:155031$8774 + assign { } { } + assign $0\alu_op__fn_unit$3[11:0]$8775 \alu_op__fn_unit$3$next + sync posedge \coresync_clk + update \alu_op__fn_unit$3 $0\alu_op__fn_unit$3[11:0]$8775 + end + attribute \src "libresoc.v:155033.3-155034.67" + process $proc$libresoc.v:155033$8776 + assign { } { } + assign $0\alu_op__imm_data__data$4[63:0]$8777 \alu_op__imm_data__data$4$next + sync posedge \coresync_clk + update \alu_op__imm_data__data$4 $0\alu_op__imm_data__data$4[63:0]$8777 + end + attribute \src "libresoc.v:155035.3-155036.63" + process $proc$libresoc.v:155035$8778 + assign { } { } + assign $0\alu_op__imm_data__ok$5[0:0]$8779 \alu_op__imm_data__ok$5$next + sync posedge \coresync_clk + update \alu_op__imm_data__ok$5 $0\alu_op__imm_data__ok$5[0:0]$8779 + end + attribute \src "libresoc.v:155037.3-155038.51" + process $proc$libresoc.v:155037$8780 + assign { } { } + assign $0\alu_op__rc__rc$6[0:0]$8781 \alu_op__rc__rc$6$next + sync posedge \coresync_clk + update \alu_op__rc__rc$6 $0\alu_op__rc__rc$6[0:0]$8781 + end + attribute \src "libresoc.v:155039.3-155040.51" + process $proc$libresoc.v:155039$8782 + assign { } { } + assign $0\alu_op__rc__ok$7[0:0]$8783 \alu_op__rc__ok$7$next + sync posedge \coresync_clk + update \alu_op__rc__ok$7 $0\alu_op__rc__ok$7[0:0]$8783 + end + attribute \src "libresoc.v:155041.3-155042.51" + process $proc$libresoc.v:155041$8784 + assign { } { } + assign $0\alu_op__oe__oe$8[0:0]$8785 \alu_op__oe__oe$8$next + sync posedge \coresync_clk + update \alu_op__oe__oe$8 $0\alu_op__oe__oe$8[0:0]$8785 + end + attribute \src "libresoc.v:155043.3-155044.51" + process $proc$libresoc.v:155043$8786 + assign { } { } + assign $0\alu_op__oe__ok$9[0:0]$8787 \alu_op__oe__ok$9$next + sync posedge \coresync_clk + update \alu_op__oe__ok$9 $0\alu_op__oe__ok$9[0:0]$8787 + end + attribute \src "libresoc.v:155045.3-155046.59" + process $proc$libresoc.v:155045$8788 + assign { } { } + assign $0\alu_op__invert_in$10[0:0]$8789 \alu_op__invert_in$10$next + sync posedge \coresync_clk + update \alu_op__invert_in$10 $0\alu_op__invert_in$10[0:0]$8789 + end + attribute \src "libresoc.v:155047.3-155048.53" + process $proc$libresoc.v:155047$8790 + assign { } { } + assign $0\alu_op__zero_a$11[0:0]$8791 \alu_op__zero_a$11$next + sync posedge \coresync_clk + update \alu_op__zero_a$11 $0\alu_op__zero_a$11[0:0]$8791 + end + attribute \src "libresoc.v:155049.3-155050.61" + process $proc$libresoc.v:155049$8792 + assign { } { } + assign $0\alu_op__invert_out$12[0:0]$8793 \alu_op__invert_out$12$next + sync posedge \coresync_clk + update \alu_op__invert_out$12 $0\alu_op__invert_out$12[0:0]$8793 + end + attribute \src "libresoc.v:155051.3-155052.59" + process $proc$libresoc.v:155051$8794 + assign { } { } + assign $0\alu_op__write_cr0$13[0:0]$8795 \alu_op__write_cr0$13$next + sync posedge \coresync_clk + update \alu_op__write_cr0$13 $0\alu_op__write_cr0$13[0:0]$8795 + end + attribute \src "libresoc.v:155053.3-155054.63" + process $proc$libresoc.v:155053$8796 + assign { } { } + assign $0\alu_op__input_carry$14[1:0]$8797 \alu_op__input_carry$14$next + sync posedge \coresync_clk + update \alu_op__input_carry$14 $0\alu_op__input_carry$14[1:0]$8797 + end + attribute \src "libresoc.v:155055.3-155056.65" + process $proc$libresoc.v:155055$8798 + assign { } { } + assign $0\alu_op__output_carry$15[0:0]$8799 \alu_op__output_carry$15$next + sync posedge \coresync_clk + update \alu_op__output_carry$15 $0\alu_op__output_carry$15[0:0]$8799 + end + attribute \src "libresoc.v:155057.3-155058.57" + process $proc$libresoc.v:155057$8800 + assign { } { } + assign $0\alu_op__is_32bit$16[0:0]$8801 \alu_op__is_32bit$16$next + sync posedge \coresync_clk + update \alu_op__is_32bit$16 $0\alu_op__is_32bit$16[0:0]$8801 + end + attribute \src "libresoc.v:155059.3-155060.59" + process $proc$libresoc.v:155059$8802 + assign { } { } + assign $0\alu_op__is_signed$17[0:0]$8803 \alu_op__is_signed$17$next + sync posedge \coresync_clk + update \alu_op__is_signed$17 $0\alu_op__is_signed$17[0:0]$8803 + end + attribute \src "libresoc.v:155061.3-155062.57" + process $proc$libresoc.v:155061$8804 + assign { } { } + assign $0\alu_op__data_len$18[3:0]$8805 \alu_op__data_len$18$next + sync posedge \coresync_clk + update \alu_op__data_len$18 $0\alu_op__data_len$18[3:0]$8805 + end + attribute \src "libresoc.v:155063.3-155064.49" + process $proc$libresoc.v:155063$8806 + assign { } { } + assign $0\alu_op__insn$19[31:0]$8807 \alu_op__insn$19$next + sync posedge \coresync_clk + update \alu_op__insn$19 $0\alu_op__insn$19[31:0]$8807 + end + attribute \src "libresoc.v:155065.3-155066.33" + process $proc$libresoc.v:155065$8808 + assign { } { } + assign $0\muxid$1[1:0]$8809 \muxid$1$next + sync posedge \coresync_clk + update \muxid$1 $0\muxid$1[1:0]$8809 + end + attribute \src "libresoc.v:155067.3-155068.29" + process $proc$libresoc.v:155067$8810 + assign { } { } + assign $0\r_busy[0:0] \r_busy$next + sync posedge \coresync_clk + update \r_busy $0\r_busy[0:0] + end + attribute \src "libresoc.v:155133.3-155150.6" + process $proc$libresoc.v:155133$8811 + assign { } { } + assign { } { } + assign { } { } + assign $0\r_busy$next[0:0]$8812 $2\r_busy$next[0:0]$8814 + attribute \src "libresoc.v:155134.5-155134.29" + switch \initial + attribute \src "libresoc.v:155134.9-155134.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\r_busy$next[0:0]$8813 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\r_busy$next[0:0]$8813 1'0 + case + assign $1\r_busy$next[0:0]$8813 \r_busy + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r_busy$next[0:0]$8814 1'0 + case + assign $2\r_busy$next[0:0]$8814 $1\r_busy$next[0:0]$8813 + end + sync always + update \r_busy$next $0\r_busy$next[0:0]$8812 + end + attribute \src "libresoc.v:155151.3-155163.6" + process $proc$libresoc.v:155151$8815 + assign { } { } + assign { } { } + assign $0\muxid$1$next[1:0]$8816 $1\muxid$1$next[1:0]$8817 + attribute \src "libresoc.v:155152.5-155152.29" + switch \initial + attribute \src "libresoc.v:155152.9-155152.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\muxid$1$next[1:0]$8817 \muxid$62 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\muxid$1$next[1:0]$8817 \muxid$62 + case + assign $1\muxid$1$next[1:0]$8817 \muxid$1 + end + sync always + update \muxid$1$next $0\muxid$1$next[1:0]$8816 + end + attribute \src "libresoc.v:155164.3-155205.6" + process $proc$libresoc.v:155164$8818 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\alu_op__data_len$18$next[3:0]$8819 $1\alu_op__data_len$18$next[3:0]$8837 + assign $0\alu_op__fn_unit$3$next[11:0]$8820 $1\alu_op__fn_unit$3$next[11:0]$8838 + assign { } { } + assign { } { } + assign $0\alu_op__input_carry$14$next[1:0]$8823 $1\alu_op__input_carry$14$next[1:0]$8841 + assign $0\alu_op__insn$19$next[31:0]$8824 $1\alu_op__insn$19$next[31:0]$8842 + assign $0\alu_op__insn_type$2$next[6:0]$8825 $1\alu_op__insn_type$2$next[6:0]$8843 + assign $0\alu_op__invert_in$10$next[0:0]$8826 $1\alu_op__invert_in$10$next[0:0]$8844 + assign $0\alu_op__invert_out$12$next[0:0]$8827 $1\alu_op__invert_out$12$next[0:0]$8845 + assign $0\alu_op__is_32bit$16$next[0:0]$8828 $1\alu_op__is_32bit$16$next[0:0]$8846 + assign $0\alu_op__is_signed$17$next[0:0]$8829 $1\alu_op__is_signed$17$next[0:0]$8847 + assign { } { } + assign { } { } + assign $0\alu_op__output_carry$15$next[0:0]$8832 $1\alu_op__output_carry$15$next[0:0]$8850 + assign { } { } + assign { } { } + assign $0\alu_op__write_cr0$13$next[0:0]$8835 $1\alu_op__write_cr0$13$next[0:0]$8853 + assign $0\alu_op__zero_a$11$next[0:0]$8836 $1\alu_op__zero_a$11$next[0:0]$8854 + assign $0\alu_op__imm_data__data$4$next[63:0]$8821 $2\alu_op__imm_data__data$4$next[63:0]$8855 + assign $0\alu_op__imm_data__ok$5$next[0:0]$8822 $2\alu_op__imm_data__ok$5$next[0:0]$8856 + assign $0\alu_op__oe__oe$8$next[0:0]$8830 $2\alu_op__oe__oe$8$next[0:0]$8857 + assign $0\alu_op__oe__ok$9$next[0:0]$8831 $2\alu_op__oe__ok$9$next[0:0]$8858 + assign $0\alu_op__rc__ok$7$next[0:0]$8833 $2\alu_op__rc__ok$7$next[0:0]$8859 + assign $0\alu_op__rc__rc$6$next[0:0]$8834 $2\alu_op__rc__rc$6$next[0:0]$8860 + attribute \src "libresoc.v:155165.5-155165.29" + switch \initial + attribute \src "libresoc.v:155165.9-155165.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\alu_op__insn$19$next[31:0]$8842 $1\alu_op__data_len$18$next[3:0]$8837 $1\alu_op__is_signed$17$next[0:0]$8847 $1\alu_op__is_32bit$16$next[0:0]$8846 $1\alu_op__output_carry$15$next[0:0]$8850 $1\alu_op__input_carry$14$next[1:0]$8841 $1\alu_op__write_cr0$13$next[0:0]$8853 $1\alu_op__invert_out$12$next[0:0]$8845 $1\alu_op__zero_a$11$next[0:0]$8854 $1\alu_op__invert_in$10$next[0:0]$8844 $1\alu_op__oe__ok$9$next[0:0]$8849 $1\alu_op__oe__oe$8$next[0:0]$8848 $1\alu_op__rc__ok$7$next[0:0]$8851 $1\alu_op__rc__rc$6$next[0:0]$8852 $1\alu_op__imm_data__ok$5$next[0:0]$8840 $1\alu_op__imm_data__data$4$next[63:0]$8839 $1\alu_op__fn_unit$3$next[11:0]$8838 $1\alu_op__insn_type$2$next[6:0]$8843 } { \alu_op__insn$80 \alu_op__data_len$79 \alu_op__is_signed$78 \alu_op__is_32bit$77 \alu_op__output_carry$76 \alu_op__input_carry$75 \alu_op__write_cr0$74 \alu_op__invert_out$73 \alu_op__zero_a$72 \alu_op__invert_in$71 \alu_op__oe__ok$70 \alu_op__oe__oe$69 \alu_op__rc__ok$68 \alu_op__rc__rc$67 \alu_op__imm_data__ok$66 \alu_op__imm_data__data$65 \alu_op__fn_unit$64 \alu_op__insn_type$63 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\alu_op__insn$19$next[31:0]$8842 $1\alu_op__data_len$18$next[3:0]$8837 $1\alu_op__is_signed$17$next[0:0]$8847 $1\alu_op__is_32bit$16$next[0:0]$8846 $1\alu_op__output_carry$15$next[0:0]$8850 $1\alu_op__input_carry$14$next[1:0]$8841 $1\alu_op__write_cr0$13$next[0:0]$8853 $1\alu_op__invert_out$12$next[0:0]$8845 $1\alu_op__zero_a$11$next[0:0]$8854 $1\alu_op__invert_in$10$next[0:0]$8844 $1\alu_op__oe__ok$9$next[0:0]$8849 $1\alu_op__oe__oe$8$next[0:0]$8848 $1\alu_op__rc__ok$7$next[0:0]$8851 $1\alu_op__rc__rc$6$next[0:0]$8852 $1\alu_op__imm_data__ok$5$next[0:0]$8840 $1\alu_op__imm_data__data$4$next[63:0]$8839 $1\alu_op__fn_unit$3$next[11:0]$8838 $1\alu_op__insn_type$2$next[6:0]$8843 } { \alu_op__insn$80 \alu_op__data_len$79 \alu_op__is_signed$78 \alu_op__is_32bit$77 \alu_op__output_carry$76 \alu_op__input_carry$75 \alu_op__write_cr0$74 \alu_op__invert_out$73 \alu_op__zero_a$72 \alu_op__invert_in$71 \alu_op__oe__ok$70 \alu_op__oe__oe$69 \alu_op__rc__ok$68 \alu_op__rc__rc$67 \alu_op__imm_data__ok$66 \alu_op__imm_data__data$65 \alu_op__fn_unit$64 \alu_op__insn_type$63 } + case + assign $1\alu_op__data_len$18$next[3:0]$8837 \alu_op__data_len$18 + assign $1\alu_op__fn_unit$3$next[11:0]$8838 \alu_op__fn_unit$3 + assign $1\alu_op__imm_data__data$4$next[63:0]$8839 \alu_op__imm_data__data$4 + assign $1\alu_op__imm_data__ok$5$next[0:0]$8840 \alu_op__imm_data__ok$5 + assign $1\alu_op__input_carry$14$next[1:0]$8841 \alu_op__input_carry$14 + assign $1\alu_op__insn$19$next[31:0]$8842 \alu_op__insn$19 + assign $1\alu_op__insn_type$2$next[6:0]$8843 \alu_op__insn_type$2 + assign $1\alu_op__invert_in$10$next[0:0]$8844 \alu_op__invert_in$10 + assign $1\alu_op__invert_out$12$next[0:0]$8845 \alu_op__invert_out$12 + assign $1\alu_op__is_32bit$16$next[0:0]$8846 \alu_op__is_32bit$16 + assign $1\alu_op__is_signed$17$next[0:0]$8847 \alu_op__is_signed$17 + assign $1\alu_op__oe__oe$8$next[0:0]$8848 \alu_op__oe__oe$8 + assign $1\alu_op__oe__ok$9$next[0:0]$8849 \alu_op__oe__ok$9 + assign $1\alu_op__output_carry$15$next[0:0]$8850 \alu_op__output_carry$15 + assign $1\alu_op__rc__ok$7$next[0:0]$8851 \alu_op__rc__ok$7 + assign $1\alu_op__rc__rc$6$next[0:0]$8852 \alu_op__rc__rc$6 + assign $1\alu_op__write_cr0$13$next[0:0]$8853 \alu_op__write_cr0$13 + assign $1\alu_op__zero_a$11$next[0:0]$8854 \alu_op__zero_a$11 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $2\alu_op__imm_data__data$4$next[63:0]$8855 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\alu_op__imm_data__ok$5$next[0:0]$8856 1'0 + assign $2\alu_op__rc__rc$6$next[0:0]$8860 1'0 + assign $2\alu_op__rc__ok$7$next[0:0]$8859 1'0 + assign $2\alu_op__oe__oe$8$next[0:0]$8857 1'0 + assign $2\alu_op__oe__ok$9$next[0:0]$8858 1'0 + case + assign $2\alu_op__imm_data__data$4$next[63:0]$8855 $1\alu_op__imm_data__data$4$next[63:0]$8839 + assign $2\alu_op__imm_data__ok$5$next[0:0]$8856 $1\alu_op__imm_data__ok$5$next[0:0]$8840 + assign $2\alu_op__oe__oe$8$next[0:0]$8857 $1\alu_op__oe__oe$8$next[0:0]$8848 + assign $2\alu_op__oe__ok$9$next[0:0]$8858 $1\alu_op__oe__ok$9$next[0:0]$8849 + assign $2\alu_op__rc__ok$7$next[0:0]$8859 $1\alu_op__rc__ok$7$next[0:0]$8851 + assign $2\alu_op__rc__rc$6$next[0:0]$8860 $1\alu_op__rc__rc$6$next[0:0]$8852 + end + sync always + update \alu_op__data_len$18$next $0\alu_op__data_len$18$next[3:0]$8819 + update \alu_op__fn_unit$3$next $0\alu_op__fn_unit$3$next[11:0]$8820 + update \alu_op__imm_data__data$4$next $0\alu_op__imm_data__data$4$next[63:0]$8821 + update \alu_op__imm_data__ok$5$next $0\alu_op__imm_data__ok$5$next[0:0]$8822 + update \alu_op__input_carry$14$next $0\alu_op__input_carry$14$next[1:0]$8823 + update \alu_op__insn$19$next $0\alu_op__insn$19$next[31:0]$8824 + update \alu_op__insn_type$2$next $0\alu_op__insn_type$2$next[6:0]$8825 + update \alu_op__invert_in$10$next $0\alu_op__invert_in$10$next[0:0]$8826 + update \alu_op__invert_out$12$next $0\alu_op__invert_out$12$next[0:0]$8827 + update \alu_op__is_32bit$16$next $0\alu_op__is_32bit$16$next[0:0]$8828 + update \alu_op__is_signed$17$next $0\alu_op__is_signed$17$next[0:0]$8829 + update \alu_op__oe__oe$8$next $0\alu_op__oe__oe$8$next[0:0]$8830 + update \alu_op__oe__ok$9$next $0\alu_op__oe__ok$9$next[0:0]$8831 + update \alu_op__output_carry$15$next $0\alu_op__output_carry$15$next[0:0]$8832 + update \alu_op__rc__ok$7$next $0\alu_op__rc__ok$7$next[0:0]$8833 + update \alu_op__rc__rc$6$next $0\alu_op__rc__rc$6$next[0:0]$8834 + update \alu_op__write_cr0$13$next $0\alu_op__write_cr0$13$next[0:0]$8835 + update \alu_op__zero_a$11$next $0\alu_op__zero_a$11$next[0:0]$8836 + end + attribute \src "libresoc.v:155206.3-155224.6" + process $proc$libresoc.v:155206$8861 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\o$20$next[63:0]$8862 $1\o$20$next[63:0]$8864 + assign { } { } + assign $0\o_ok$21$next[0:0]$8863 $2\o_ok$21$next[0:0]$8866 + attribute \src "libresoc.v:155207.5-155207.29" + switch \initial + attribute \src "libresoc.v:155207.9-155207.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\o_ok$21$next[0:0]$8865 $1\o$20$next[63:0]$8864 } { \o_ok$82 \o$81 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\o_ok$21$next[0:0]$8865 $1\o$20$next[63:0]$8864 } { \o_ok$82 \o$81 } + case + assign $1\o$20$next[63:0]$8864 \o$20 + assign $1\o_ok$21$next[0:0]$8865 \o_ok$21 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\o_ok$21$next[0:0]$8866 1'0 + case + assign $2\o_ok$21$next[0:0]$8866 $1\o_ok$21$next[0:0]$8865 + end + sync always + update \o$20$next $0\o$20$next[63:0]$8862 + update \o_ok$21$next $0\o_ok$21$next[0:0]$8863 + end + attribute \src "libresoc.v:155225.3-155243.6" + process $proc$libresoc.v:155225$8867 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\cr_a$22$next[3:0]$8868 $1\cr_a$22$next[3:0]$8870 + assign { } { } + assign $0\cr_a_ok$23$next[0:0]$8869 $2\cr_a_ok$23$next[0:0]$8872 + attribute \src "libresoc.v:155226.5-155226.29" + switch \initial + attribute \src "libresoc.v:155226.9-155226.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\cr_a_ok$23$next[0:0]$8871 $1\cr_a$22$next[3:0]$8870 } { \cr_a_ok$84 \cr_a$83 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\cr_a_ok$23$next[0:0]$8871 $1\cr_a$22$next[3:0]$8870 } { \cr_a_ok$84 \cr_a$83 } + case + assign $1\cr_a$22$next[3:0]$8870 \cr_a$22 + assign $1\cr_a_ok$23$next[0:0]$8871 \cr_a_ok$23 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_a_ok$23$next[0:0]$8872 1'0 + case + assign $2\cr_a_ok$23$next[0:0]$8872 $1\cr_a_ok$23$next[0:0]$8871 + end + sync always + update \cr_a$22$next $0\cr_a$22$next[3:0]$8868 + update \cr_a_ok$23$next $0\cr_a_ok$23$next[0:0]$8869 + end + attribute \src "libresoc.v:155244.3-155262.6" + process $proc$libresoc.v:155244$8873 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\xer_ca$24$next[1:0]$8874 $1\xer_ca$24$next[1:0]$8876 + assign { } { } + assign $0\xer_ca_ok$25$next[0:0]$8875 $2\xer_ca_ok$25$next[0:0]$8878 + attribute \src "libresoc.v:155245.5-155245.29" + switch \initial + attribute \src "libresoc.v:155245.9-155245.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\xer_ca_ok$25$next[0:0]$8877 $1\xer_ca$24$next[1:0]$8876 } { \xer_ca_ok$86 \xer_ca$85 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\xer_ca_ok$25$next[0:0]$8877 $1\xer_ca$24$next[1:0]$8876 } { \xer_ca_ok$86 \xer_ca$85 } + case + assign $1\xer_ca$24$next[1:0]$8876 \xer_ca$24 + assign $1\xer_ca_ok$25$next[0:0]$8877 \xer_ca_ok$25 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\xer_ca_ok$25$next[0:0]$8878 1'0 + case + assign $2\xer_ca_ok$25$next[0:0]$8878 $1\xer_ca_ok$25$next[0:0]$8877 + end + sync always + update \xer_ca$24$next $0\xer_ca$24$next[1:0]$8874 + update \xer_ca_ok$25$next $0\xer_ca_ok$25$next[0:0]$8875 + end + attribute \src "libresoc.v:155263.3-155281.6" + process $proc$libresoc.v:155263$8879 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\xer_ov$26$next[1:0]$8880 $1\xer_ov$26$next[1:0]$8882 + assign { } { } + assign $0\xer_ov_ok$27$next[0:0]$8881 $2\xer_ov_ok$27$next[0:0]$8884 + attribute \src "libresoc.v:155264.5-155264.29" + switch \initial + attribute \src "libresoc.v:155264.9-155264.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\xer_ov_ok$27$next[0:0]$8883 $1\xer_ov$26$next[1:0]$8882 } { \xer_ov_ok$88 \xer_ov$87 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\xer_ov_ok$27$next[0:0]$8883 $1\xer_ov$26$next[1:0]$8882 } { \xer_ov_ok$88 \xer_ov$87 } + case + assign $1\xer_ov$26$next[1:0]$8882 \xer_ov$26 + assign $1\xer_ov_ok$27$next[0:0]$8883 \xer_ov_ok$27 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\xer_ov_ok$27$next[0:0]$8884 1'0 + case + assign $2\xer_ov_ok$27$next[0:0]$8884 $1\xer_ov_ok$27$next[0:0]$8883 + end + sync always + update \xer_ov$26$next $0\xer_ov$26$next[1:0]$8880 + update \xer_ov_ok$27$next $0\xer_ov_ok$27$next[0:0]$8881 + end + attribute \src "libresoc.v:155282.3-155300.6" + process $proc$libresoc.v:155282$8885 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\xer_so$28$next[0:0]$8886 $1\xer_so$28$next[0:0]$8888 + assign { } { } + assign $0\xer_so_ok$29$next[0:0]$8887 $2\xer_so_ok$29$next[0:0]$8890 + attribute \src "libresoc.v:155283.5-155283.29" + switch \initial + attribute \src "libresoc.v:155283.9-155283.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\xer_so_ok$29$next[0:0]$8889 $1\xer_so$28$next[0:0]$8888 } { \xer_so_ok$90 \xer_so$89 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\xer_so_ok$29$next[0:0]$8889 $1\xer_so$28$next[0:0]$8888 } { \xer_so_ok$90 \xer_so$89 } + case + assign $1\xer_so$28$next[0:0]$8888 \xer_so$28 + assign $1\xer_so_ok$29$next[0:0]$8889 \xer_so_ok$29 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\xer_so_ok$29$next[0:0]$8890 1'0 + case + assign $2\xer_so_ok$29$next[0:0]$8890 $1\xer_so_ok$29$next[0:0]$8889 + end + sync always + update \xer_so$28$next $0\xer_so$28$next[0:0]$8886 + update \xer_so_ok$29$next $0\xer_so_ok$29$next[0:0]$8887 + end + connect \$60 $and$libresoc.v:155008$8751_Y + connect \p_ready_o \n_i_rdy_data + connect \n_valid_o \r_busy + connect { \xer_so_ok$90 \xer_so$89 } { \output_xer_so_ok \output_xer_so$54 } + connect { \xer_ov_ok$88 \xer_ov$87 } { \output_xer_ov_ok \output_xer_ov$53 } + connect { \xer_ca_ok$86 \xer_ca$85 } { \output_xer_ca_ok \output_xer_ca$52 } + connect { \cr_a_ok$84 \cr_a$83 } { \output_cr_a_ok \output_cr_a$51 } + connect { \o_ok$82 \o$81 } { \output_o_ok$50 \output_o$49 } + connect { \alu_op__insn$80 \alu_op__data_len$79 \alu_op__is_signed$78 \alu_op__is_32bit$77 \alu_op__output_carry$76 \alu_op__input_carry$75 \alu_op__write_cr0$74 \alu_op__invert_out$73 \alu_op__zero_a$72 \alu_op__invert_in$71 \alu_op__oe__ok$70 \alu_op__oe__oe$69 \alu_op__rc__ok$68 \alu_op__rc__rc$67 \alu_op__imm_data__ok$66 \alu_op__imm_data__data$65 \alu_op__fn_unit$64 \alu_op__insn_type$63 } { \output_alu_op__insn$48 \output_alu_op__data_len$47 \output_alu_op__is_signed$46 \output_alu_op__is_32bit$45 \output_alu_op__output_carry$44 \output_alu_op__input_carry$43 \output_alu_op__write_cr0$42 \output_alu_op__invert_out$41 \output_alu_op__zero_a$40 \output_alu_op__invert_in$39 \output_alu_op__oe__ok$38 \output_alu_op__oe__oe$37 \output_alu_op__rc__ok$36 \output_alu_op__rc__rc$35 \output_alu_op__imm_data__ok$34 \output_alu_op__imm_data__data$33 \output_alu_op__fn_unit$32 \output_alu_op__insn_type$31 } + connect \muxid$62 \output_muxid$30 + connect \p_valid_i_p_ready_o \$60 + connect \n_i_rdy_data \n_ready_i + connect \p_valid_i$59 \p_valid_i + connect { \xer_so_ok$58 \output_xer_so } { \xer_so_ok \xer_so } + connect { \xer_ov_ok$57 \output_xer_ov } { \xer_ov_ok \xer_ov } + connect { \xer_ca_ok$56 \output_xer_ca } { \xer_ca_ok \xer_ca } + connect { \cr_a_ok$55 \output_cr_a } { \cr_a_ok \cr_a } + connect { \output_o_ok \output_o } { \o_ok \o } + connect { \output_alu_op__insn \output_alu_op__data_len \output_alu_op__is_signed \output_alu_op__is_32bit \output_alu_op__output_carry \output_alu_op__input_carry \output_alu_op__write_cr0 \output_alu_op__invert_out \output_alu_op__zero_a \output_alu_op__invert_in \output_alu_op__oe__ok \output_alu_op__oe__oe \output_alu_op__rc__ok \output_alu_op__rc__rc \output_alu_op__imm_data__ok \output_alu_op__imm_data__data \output_alu_op__fn_unit \output_alu_op__insn_type } { \alu_op__insn \alu_op__data_len \alu_op__is_signed \alu_op__is_32bit \alu_op__output_carry \alu_op__input_carry \alu_op__write_cr0 \alu_op__invert_out \alu_op__zero_a \alu_op__invert_in \alu_op__oe__ok \alu_op__oe__oe \alu_op__rc__ok \alu_op__rc__rc \alu_op__imm_data__ok \alu_op__imm_data__data \alu_op__fn_unit \alu_op__insn_type } + connect \output_muxid \muxid +end +attribute \src "libresoc.v:155324.1-156360.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.pipe2" +attribute \generator "nMigen" +module \pipe2$112 + attribute \src "libresoc.v:156306.3-156324.6" + wire width 4 $0\cr_a$20$next[3:0]$9052 + attribute \src "libresoc.v:156117.3-156118.33" + wire width 4 $0\cr_a$20[3:0]$8957 + attribute \src "libresoc.v:155336.13-155336.29" + wire width 4 $0\cr_a$20[3:0]$9065 + attribute \src "libresoc.v:156306.3-156324.6" + wire $0\cr_a_ok$21$next[0:0]$9053 + attribute \src "libresoc.v:156119.3-156120.39" + wire $0\cr_a_ok$21[0:0]$8959 + attribute \src "libresoc.v:155345.7-155345.26" + wire $0\cr_a_ok$21[0:0]$9067 + attribute \src "libresoc.v:155325.7-155325.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:156234.3-156246.6" + wire width 2 $0\muxid$1$next[1:0]$9004 + attribute \src "libresoc.v:156157.3-156158.33" + wire width 2 $0\muxid$1[1:0]$8997 + attribute \src "libresoc.v:155356.13-155356.29" + wire width 2 $0\muxid$1[1:0]$9069 + attribute \src "libresoc.v:156287.3-156305.6" + wire width 64 $0\o$18$next[63:0]$9046 + attribute \src "libresoc.v:156121.3-156122.27" + wire width 64 $0\o$18[63:0]$8961 + attribute \src "libresoc.v:155371.14-155371.43" + wire width 64 $0\o$18[63:0]$9071 + attribute \src "libresoc.v:156287.3-156305.6" + wire $0\o_ok$19$next[0:0]$9047 + attribute \src "libresoc.v:156123.3-156124.33" + wire $0\o_ok$19[0:0]$8963 + attribute \src "libresoc.v:155380.7-155380.23" + wire $0\o_ok$19[0:0]$9073 + attribute \src "libresoc.v:156216.3-156233.6" + wire $0\r_busy$next[0:0]$9000 + attribute \src "libresoc.v:156159.3-156160.29" + wire $0\r_busy[0:0] + attribute \src "libresoc.v:156247.3-156286.6" + wire width 12 $0\sr_op__fn_unit$3$next[11:0]$9007 + attribute \src "libresoc.v:156127.3-156128.51" + wire width 12 $0\sr_op__fn_unit$3[11:0]$8967 + attribute \src "libresoc.v:155699.14-155699.42" + wire width 12 $0\sr_op__fn_unit$3[11:0]$9076 + attribute \src "libresoc.v:156247.3-156286.6" + wire width 64 $0\sr_op__imm_data__data$4$next[63:0]$9008 + attribute \src "libresoc.v:156129.3-156130.65" + wire width 64 $0\sr_op__imm_data__data$4[63:0]$8969 + attribute \src "libresoc.v:155721.14-155721.62" + wire width 64 $0\sr_op__imm_data__data$4[63:0]$9078 + attribute \src "libresoc.v:156247.3-156286.6" + wire $0\sr_op__imm_data__ok$5$next[0:0]$9009 + attribute \src "libresoc.v:156131.3-156132.61" + wire $0\sr_op__imm_data__ok$5[0:0]$8971 + attribute \src "libresoc.v:155730.7-155730.37" + wire $0\sr_op__imm_data__ok$5[0:0]$9080 + attribute \src "libresoc.v:156247.3-156286.6" + wire width 2 $0\sr_op__input_carry$11$next[1:0]$9010 + attribute \src "libresoc.v:156143.3-156144.61" + wire width 2 $0\sr_op__input_carry$11[1:0]$8983 + attribute \src "libresoc.v:155747.13-155747.43" + wire width 2 $0\sr_op__input_carry$11[1:0]$9082 + attribute \src "libresoc.v:156247.3-156286.6" + wire $0\sr_op__input_cr$13$next[0:0]$9011 + attribute \src "libresoc.v:156147.3-156148.55" + wire $0\sr_op__input_cr$13[0:0]$8987 + attribute \src "libresoc.v:155760.7-155760.34" + wire $0\sr_op__input_cr$13[0:0]$9084 + attribute \src "libresoc.v:156247.3-156286.6" + wire width 32 $0\sr_op__insn$17$next[31:0]$9012 + attribute \src "libresoc.v:156155.3-156156.47" + wire width 32 $0\sr_op__insn$17[31:0]$8995 + attribute \src "libresoc.v:155769.14-155769.38" + wire width 32 $0\sr_op__insn$17[31:0]$9086 + attribute \src "libresoc.v:156247.3-156286.6" + wire width 7 $0\sr_op__insn_type$2$next[6:0]$9013 + attribute \src "libresoc.v:156125.3-156126.55" + wire width 7 $0\sr_op__insn_type$2[6:0]$8965 + attribute \src "libresoc.v:155926.13-155926.41" + wire width 7 $0\sr_op__insn_type$2[6:0]$9088 + attribute \src "libresoc.v:156247.3-156286.6" + wire $0\sr_op__is_32bit$15$next[0:0]$9014 + attribute \src "libresoc.v:156151.3-156152.55" + wire $0\sr_op__is_32bit$15[0:0]$8991 + attribute \src "libresoc.v:156009.7-156009.34" + wire $0\sr_op__is_32bit$15[0:0]$9090 + attribute \src "libresoc.v:156247.3-156286.6" + wire $0\sr_op__is_signed$16$next[0:0]$9015 + attribute \src "libresoc.v:156153.3-156154.57" + wire $0\sr_op__is_signed$16[0:0]$8993 + attribute \src "libresoc.v:156018.7-156018.35" + wire $0\sr_op__is_signed$16[0:0]$9092 + attribute \src "libresoc.v:156247.3-156286.6" + wire $0\sr_op__oe__oe$8$next[0:0]$9016 + attribute \src "libresoc.v:156137.3-156138.49" + wire $0\sr_op__oe__oe$8[0:0]$8977 + attribute \src "libresoc.v:156029.7-156029.31" + wire $0\sr_op__oe__oe$8[0:0]$9094 + attribute \src "libresoc.v:156247.3-156286.6" + wire $0\sr_op__oe__ok$9$next[0:0]$9017 + attribute \src "libresoc.v:156139.3-156140.49" + wire $0\sr_op__oe__ok$9[0:0]$8979 + attribute \src "libresoc.v:156038.7-156038.31" + wire $0\sr_op__oe__ok$9[0:0]$9096 + attribute \src "libresoc.v:156247.3-156286.6" + wire $0\sr_op__output_carry$12$next[0:0]$9018 + attribute \src "libresoc.v:156145.3-156146.63" + wire $0\sr_op__output_carry$12[0:0]$8985 + attribute \src "libresoc.v:156045.7-156045.38" + wire $0\sr_op__output_carry$12[0:0]$9098 + attribute \src "libresoc.v:156247.3-156286.6" + wire $0\sr_op__output_cr$14$next[0:0]$9019 + attribute \src "libresoc.v:156149.3-156150.57" + wire $0\sr_op__output_cr$14[0:0]$8989 + attribute \src "libresoc.v:156054.7-156054.35" + wire $0\sr_op__output_cr$14[0:0]$9100 + attribute \src "libresoc.v:156247.3-156286.6" + wire $0\sr_op__rc__ok$7$next[0:0]$9020 + attribute \src "libresoc.v:156135.3-156136.49" + wire $0\sr_op__rc__ok$7[0:0]$8975 + attribute \src "libresoc.v:156065.7-156065.31" + wire $0\sr_op__rc__ok$7[0:0]$9102 + attribute \src "libresoc.v:156247.3-156286.6" + wire $0\sr_op__rc__rc$6$next[0:0]$9021 + attribute \src "libresoc.v:156133.3-156134.49" + wire $0\sr_op__rc__rc$6[0:0]$8973 + attribute \src "libresoc.v:156074.7-156074.31" + wire $0\sr_op__rc__rc$6[0:0]$9104 + attribute \src "libresoc.v:156247.3-156286.6" + wire $0\sr_op__write_cr0$10$next[0:0]$9022 + attribute \src "libresoc.v:156141.3-156142.57" + wire $0\sr_op__write_cr0$10[0:0]$8981 + attribute \src "libresoc.v:156081.7-156081.35" + wire $0\sr_op__write_cr0$10[0:0]$9106 + attribute \src "libresoc.v:156325.3-156343.6" + wire width 2 $0\xer_ca$22$next[1:0]$9058 + attribute \src "libresoc.v:156113.3-156114.37" + wire width 2 $0\xer_ca$22[1:0]$8953 + attribute \src "libresoc.v:156090.13-156090.31" + wire width 2 $0\xer_ca$22[1:0]$9108 + attribute \src "libresoc.v:156325.3-156343.6" + wire $0\xer_ca_ok$23$next[0:0]$9059 + attribute \src "libresoc.v:156115.3-156116.43" + wire $0\xer_ca_ok$23[0:0]$8955 + attribute \src "libresoc.v:156099.7-156099.28" + wire $0\xer_ca_ok$23[0:0]$9110 + attribute \src "libresoc.v:156306.3-156324.6" + wire width 4 $1\cr_a$20$next[3:0]$9054 + attribute \src "libresoc.v:156306.3-156324.6" + wire $1\cr_a_ok$21$next[0:0]$9055 + attribute \src "libresoc.v:156234.3-156246.6" + wire width 2 $1\muxid$1$next[1:0]$9005 + attribute \src "libresoc.v:156287.3-156305.6" + wire width 64 $1\o$18$next[63:0]$9048 + attribute \src "libresoc.v:156287.3-156305.6" + wire $1\o_ok$19$next[0:0]$9049 + attribute \src "libresoc.v:156216.3-156233.6" + wire $1\r_busy$next[0:0]$9001 + attribute \src "libresoc.v:155666.7-155666.20" + wire $1\r_busy[0:0] + attribute \src "libresoc.v:156247.3-156286.6" + wire width 12 $1\sr_op__fn_unit$3$next[11:0]$9023 + attribute \src "libresoc.v:156247.3-156286.6" + wire width 64 $1\sr_op__imm_data__data$4$next[63:0]$9024 + attribute \src "libresoc.v:156247.3-156286.6" + wire $1\sr_op__imm_data__ok$5$next[0:0]$9025 + attribute \src "libresoc.v:156247.3-156286.6" + wire width 2 $1\sr_op__input_carry$11$next[1:0]$9026 + attribute \src "libresoc.v:156247.3-156286.6" + wire $1\sr_op__input_cr$13$next[0:0]$9027 + attribute \src "libresoc.v:156247.3-156286.6" + wire width 32 $1\sr_op__insn$17$next[31:0]$9028 + attribute \src "libresoc.v:156247.3-156286.6" + wire width 7 $1\sr_op__insn_type$2$next[6:0]$9029 + attribute \src "libresoc.v:156247.3-156286.6" + wire $1\sr_op__is_32bit$15$next[0:0]$9030 + attribute \src "libresoc.v:156247.3-156286.6" + wire $1\sr_op__is_signed$16$next[0:0]$9031 + attribute \src "libresoc.v:156247.3-156286.6" + wire $1\sr_op__oe__oe$8$next[0:0]$9032 + attribute \src "libresoc.v:156247.3-156286.6" + wire $1\sr_op__oe__ok$9$next[0:0]$9033 + attribute \src "libresoc.v:156247.3-156286.6" + wire $1\sr_op__output_carry$12$next[0:0]$9034 + attribute \src "libresoc.v:156247.3-156286.6" + wire $1\sr_op__output_cr$14$next[0:0]$9035 + attribute \src "libresoc.v:156247.3-156286.6" + wire $1\sr_op__rc__ok$7$next[0:0]$9036 + attribute \src "libresoc.v:156247.3-156286.6" + wire $1\sr_op__rc__rc$6$next[0:0]$9037 + attribute \src "libresoc.v:156247.3-156286.6" + wire $1\sr_op__write_cr0$10$next[0:0]$9038 + attribute \src "libresoc.v:156325.3-156343.6" + wire width 2 $1\xer_ca$22$next[1:0]$9060 + attribute \src "libresoc.v:156325.3-156343.6" + wire $1\xer_ca_ok$23$next[0:0]$9061 + attribute \src "libresoc.v:156306.3-156324.6" + wire $2\cr_a_ok$21$next[0:0]$9056 + attribute \src "libresoc.v:156287.3-156305.6" + wire $2\o_ok$19$next[0:0]$9050 + attribute \src "libresoc.v:156216.3-156233.6" + wire $2\r_busy$next[0:0]$9002 + attribute \src "libresoc.v:156247.3-156286.6" + wire width 64 $2\sr_op__imm_data__data$4$next[63:0]$9039 + attribute \src "libresoc.v:156247.3-156286.6" + wire $2\sr_op__imm_data__ok$5$next[0:0]$9040 + attribute \src "libresoc.v:156247.3-156286.6" + wire $2\sr_op__oe__oe$8$next[0:0]$9041 + attribute \src "libresoc.v:156247.3-156286.6" + wire $2\sr_op__oe__ok$9$next[0:0]$9042 + attribute \src "libresoc.v:156247.3-156286.6" + wire $2\sr_op__rc__ok$7$next[0:0]$9043 + attribute \src "libresoc.v:156247.3-156286.6" + wire $2\sr_op__rc__rc$6$next[0:0]$9044 + attribute \src "libresoc.v:156325.3-156343.6" + wire $2\xer_ca_ok$23$next[0:0]$9062 + attribute \src "libresoc.v:156112.18-156112.118" + wire $and$libresoc.v:156112$8951_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + wire \$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 54 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 input 23 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 output 50 \cr_a$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \cr_a$20$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \cr_a$70 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire input 24 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 51 \cr_a_ok$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_a_ok$21$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_a_ok$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_a_ok$71 + attribute \src "libresoc.v:155325.7-155325.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 4 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 31 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$1$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$51 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" + wire \n_i_rdy_data + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire input 30 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire output 29 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 input 21 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 48 \o$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \o$18$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \o$68 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire input 22 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 49 \o_ok$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \o_ok$19$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \o_ok$69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \output_cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \output_cr_a$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \output_cr_a_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \output_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \output_muxid$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \output_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \output_o$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \output_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \output_o_ok$42 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \output_sr_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \output_sr_op__fn_unit$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \output_sr_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \output_sr_op__imm_data__data$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_sr_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_sr_op__imm_data__ok$28 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \output_sr_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \output_sr_op__input_carry$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_sr_op__input_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_sr_op__input_cr$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \output_sr_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \output_sr_op__insn$40 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \output_sr_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \output_sr_op__insn_type$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_sr_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_sr_op__is_32bit$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_sr_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_sr_op__is_signed$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_sr_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_sr_op__oe__oe$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_sr_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_sr_op__oe__ok$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_sr_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_sr_op__output_carry$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_sr_op__output_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_sr_op__output_cr$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_sr_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_sr_op__rc__ok$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_sr_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_sr_op__rc__rc$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_sr_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_sr_op__write_cr0$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \output_xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \output_xer_ca$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \output_xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \output_xer_so + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire output 3 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" + wire \p_valid_i$48 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire \r_busy$next + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 6 \sr_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 output 33 \sr_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \sr_op__fn_unit$3$next + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \sr_op__fn_unit$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 7 \sr_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 34 \sr_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \sr_op__imm_data__data$4$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \sr_op__imm_data__data$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \sr_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 35 \sr_op__imm_data__ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__imm_data__ok$5$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__imm_data__ok$55 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 14 \sr_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 41 \sr_op__input_carry$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \sr_op__input_carry$11$next + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \sr_op__input_carry$61 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 16 \sr_op__input_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 43 \sr_op__input_cr$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__input_cr$13$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__input_cr$63 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 20 \sr_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 47 \sr_op__insn$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \sr_op__insn$17$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \sr_op__insn$67 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 5 \sr_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 32 \sr_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \sr_op__insn_type$2$next + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \sr_op__insn_type$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 18 \sr_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 45 \sr_op__is_32bit$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__is_32bit$15$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__is_32bit$65 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 19 \sr_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 46 \sr_op__is_signed$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__is_signed$16$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__is_signed$66 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 11 \sr_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__oe__oe$58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 38 \sr_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__oe__oe$8$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \sr_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__oe__ok$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 39 \sr_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__oe__ok$9$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 15 \sr_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 42 \sr_op__output_carry$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__output_carry$12$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__output_carry$62 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 17 \sr_op__output_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 44 \sr_op__output_cr$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__output_cr$14$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__output_cr$64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \sr_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__rc__ok$57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 37 \sr_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__rc__ok$7$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \sr_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__rc__rc$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 36 \sr_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__rc__rc$6$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \sr_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 40 \sr_op__write_cr0$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__write_cr0$10$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__write_cr0$60 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 input 27 \xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 output 52 \xer_ca$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \xer_ca$22$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \xer_ca$72 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire input 28 \xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 53 \xer_ca_ok$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \xer_ca_ok$23$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \xer_ca_ok$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \xer_ca_ok$73 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire input 25 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire input 26 \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \xer_so_ok$46 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + cell $and $and$libresoc.v:156112$8951 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i$48 + connect \B \p_ready_o + connect \Y $and$libresoc.v:156112$8951_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:156161.11-156164.4" + cell \n$114 \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:156165.16-156211.4" + cell \output$115 \output + connect \cr_a \output_cr_a + connect \cr_a$20 \output_cr_a$43 + connect \cr_a_ok \output_cr_a_ok + connect \muxid \output_muxid + connect \muxid$1 \output_muxid$24 + connect \o \output_o + connect \o$18 \output_o$41 + connect \o_ok \output_o_ok + connect \o_ok$19 \output_o_ok$42 + connect \sr_op__fn_unit \output_sr_op__fn_unit + connect \sr_op__fn_unit$3 \output_sr_op__fn_unit$26 + connect \sr_op__imm_data__data \output_sr_op__imm_data__data + connect \sr_op__imm_data__data$4 \output_sr_op__imm_data__data$27 + connect \sr_op__imm_data__ok \output_sr_op__imm_data__ok + connect \sr_op__imm_data__ok$5 \output_sr_op__imm_data__ok$28 + connect \sr_op__input_carry \output_sr_op__input_carry + connect \sr_op__input_carry$11 \output_sr_op__input_carry$34 + connect \sr_op__input_cr \output_sr_op__input_cr + connect \sr_op__input_cr$13 \output_sr_op__input_cr$36 + connect \sr_op__insn \output_sr_op__insn + connect \sr_op__insn$17 \output_sr_op__insn$40 + connect \sr_op__insn_type \output_sr_op__insn_type + connect \sr_op__insn_type$2 \output_sr_op__insn_type$25 + connect \sr_op__is_32bit \output_sr_op__is_32bit + connect \sr_op__is_32bit$15 \output_sr_op__is_32bit$38 + connect \sr_op__is_signed \output_sr_op__is_signed + connect \sr_op__is_signed$16 \output_sr_op__is_signed$39 + connect \sr_op__oe__oe \output_sr_op__oe__oe + connect \sr_op__oe__oe$8 \output_sr_op__oe__oe$31 + connect \sr_op__oe__ok \output_sr_op__oe__ok + connect \sr_op__oe__ok$9 \output_sr_op__oe__ok$32 + connect \sr_op__output_carry \output_sr_op__output_carry + connect \sr_op__output_carry$12 \output_sr_op__output_carry$35 + connect \sr_op__output_cr \output_sr_op__output_cr + connect \sr_op__output_cr$14 \output_sr_op__output_cr$37 + connect \sr_op__rc__ok \output_sr_op__rc__ok + connect \sr_op__rc__ok$7 \output_sr_op__rc__ok$30 + connect \sr_op__rc__rc \output_sr_op__rc__rc + connect \sr_op__rc__rc$6 \output_sr_op__rc__rc$29 + connect \sr_op__write_cr0 \output_sr_op__write_cr0 + connect \sr_op__write_cr0$10 \output_sr_op__write_cr0$33 + connect \xer_ca \output_xer_ca + connect \xer_ca$21 \output_xer_ca$44 + connect \xer_ca_ok \output_xer_ca_ok + connect \xer_so \output_xer_so + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:156212.11-156215.4" + cell \p$113 \p + connect \p_ready_o \p_ready_o + connect \p_valid_i \p_valid_i + end + attribute \src "libresoc.v:155325.7-155325.20" + process $proc$libresoc.v:155325$9063 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:155336.13-155336.29" + process $proc$libresoc.v:155336$9064 + assign { } { } + assign $0\cr_a$20[3:0]$9065 4'0000 + sync always + sync init + update \cr_a$20 $0\cr_a$20[3:0]$9065 + end + attribute \src "libresoc.v:155345.7-155345.26" + process $proc$libresoc.v:155345$9066 + assign { } { } + assign $0\cr_a_ok$21[0:0]$9067 1'0 + sync always + sync init + update \cr_a_ok$21 $0\cr_a_ok$21[0:0]$9067 + end + attribute \src "libresoc.v:155356.13-155356.29" + process $proc$libresoc.v:155356$9068 + assign { } { } + assign $0\muxid$1[1:0]$9069 2'00 + sync always + sync init + update \muxid$1 $0\muxid$1[1:0]$9069 + end + attribute \src "libresoc.v:155371.14-155371.43" + process $proc$libresoc.v:155371$9070 + assign { } { } + assign $0\o$18[63:0]$9071 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \o$18 $0\o$18[63:0]$9071 + end + attribute \src "libresoc.v:155380.7-155380.23" + process $proc$libresoc.v:155380$9072 + assign { } { } + assign $0\o_ok$19[0:0]$9073 1'0 + sync always + sync init + update \o_ok$19 $0\o_ok$19[0:0]$9073 + end + attribute \src "libresoc.v:155666.7-155666.20" + process $proc$libresoc.v:155666$9074 + assign { } { } + assign $1\r_busy[0:0] 1'0 + sync always + sync init + update \r_busy $1\r_busy[0:0] + end + attribute \src "libresoc.v:155699.14-155699.42" + process $proc$libresoc.v:155699$9075 + assign { } { } + assign $0\sr_op__fn_unit$3[11:0]$9076 12'000000000000 + sync always + sync init + update \sr_op__fn_unit$3 $0\sr_op__fn_unit$3[11:0]$9076 + end + attribute \src "libresoc.v:155721.14-155721.62" + process $proc$libresoc.v:155721$9077 + assign { } { } + assign $0\sr_op__imm_data__data$4[63:0]$9078 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \sr_op__imm_data__data$4 $0\sr_op__imm_data__data$4[63:0]$9078 + end + attribute \src "libresoc.v:155730.7-155730.37" + process $proc$libresoc.v:155730$9079 + assign { } { } + assign $0\sr_op__imm_data__ok$5[0:0]$9080 1'0 + sync always + sync init + update \sr_op__imm_data__ok$5 $0\sr_op__imm_data__ok$5[0:0]$9080 + end + attribute \src "libresoc.v:155747.13-155747.43" + process $proc$libresoc.v:155747$9081 + assign { } { } + assign $0\sr_op__input_carry$11[1:0]$9082 2'00 + sync always + sync init + update \sr_op__input_carry$11 $0\sr_op__input_carry$11[1:0]$9082 + end + attribute \src "libresoc.v:155760.7-155760.34" + process $proc$libresoc.v:155760$9083 + assign { } { } + assign $0\sr_op__input_cr$13[0:0]$9084 1'0 + sync always + sync init + update \sr_op__input_cr$13 $0\sr_op__input_cr$13[0:0]$9084 + end + attribute \src "libresoc.v:155769.14-155769.38" + process $proc$libresoc.v:155769$9085 + assign { } { } + assign $0\sr_op__insn$17[31:0]$9086 0 + sync always + sync init + update \sr_op__insn$17 $0\sr_op__insn$17[31:0]$9086 + end + attribute \src "libresoc.v:155926.13-155926.41" + process $proc$libresoc.v:155926$9087 + assign { } { } + assign $0\sr_op__insn_type$2[6:0]$9088 7'0000000 + sync always + sync init + update \sr_op__insn_type$2 $0\sr_op__insn_type$2[6:0]$9088 + end + attribute \src "libresoc.v:156009.7-156009.34" + process $proc$libresoc.v:156009$9089 + assign { } { } + assign $0\sr_op__is_32bit$15[0:0]$9090 1'0 + sync always + sync init + update \sr_op__is_32bit$15 $0\sr_op__is_32bit$15[0:0]$9090 + end + attribute \src "libresoc.v:156018.7-156018.35" + process $proc$libresoc.v:156018$9091 + assign { } { } + assign $0\sr_op__is_signed$16[0:0]$9092 1'0 + sync always + sync init + update \sr_op__is_signed$16 $0\sr_op__is_signed$16[0:0]$9092 + end + attribute \src "libresoc.v:156029.7-156029.31" + process $proc$libresoc.v:156029$9093 + assign { } { } + assign $0\sr_op__oe__oe$8[0:0]$9094 1'0 + sync always + sync init + update \sr_op__oe__oe$8 $0\sr_op__oe__oe$8[0:0]$9094 + end + attribute \src "libresoc.v:156038.7-156038.31" + process $proc$libresoc.v:156038$9095 + assign { } { } + assign $0\sr_op__oe__ok$9[0:0]$9096 1'0 + sync always + sync init + update \sr_op__oe__ok$9 $0\sr_op__oe__ok$9[0:0]$9096 + end + attribute \src "libresoc.v:156045.7-156045.38" + process $proc$libresoc.v:156045$9097 + assign { } { } + assign $0\sr_op__output_carry$12[0:0]$9098 1'0 + sync always + sync init + update \sr_op__output_carry$12 $0\sr_op__output_carry$12[0:0]$9098 + end + attribute \src "libresoc.v:156054.7-156054.35" + process $proc$libresoc.v:156054$9099 + assign { } { } + assign $0\sr_op__output_cr$14[0:0]$9100 1'0 + sync always + sync init + update \sr_op__output_cr$14 $0\sr_op__output_cr$14[0:0]$9100 + end + attribute \src "libresoc.v:156065.7-156065.31" + process $proc$libresoc.v:156065$9101 + assign { } { } + assign $0\sr_op__rc__ok$7[0:0]$9102 1'0 + sync always + sync init + update \sr_op__rc__ok$7 $0\sr_op__rc__ok$7[0:0]$9102 + end + attribute \src "libresoc.v:156074.7-156074.31" + process $proc$libresoc.v:156074$9103 + assign { } { } + assign $0\sr_op__rc__rc$6[0:0]$9104 1'0 + sync always + sync init + update \sr_op__rc__rc$6 $0\sr_op__rc__rc$6[0:0]$9104 + end + attribute \src "libresoc.v:156081.7-156081.35" + process $proc$libresoc.v:156081$9105 + assign { } { } + assign $0\sr_op__write_cr0$10[0:0]$9106 1'0 + sync always + sync init + update \sr_op__write_cr0$10 $0\sr_op__write_cr0$10[0:0]$9106 + end + attribute \src "libresoc.v:156090.13-156090.31" + process $proc$libresoc.v:156090$9107 + assign { } { } + assign $0\xer_ca$22[1:0]$9108 2'00 + sync always + sync init + update \xer_ca$22 $0\xer_ca$22[1:0]$9108 + end + attribute \src "libresoc.v:156099.7-156099.28" + process $proc$libresoc.v:156099$9109 + assign { } { } + assign $0\xer_ca_ok$23[0:0]$9110 1'0 + sync always + sync init + update \xer_ca_ok$23 $0\xer_ca_ok$23[0:0]$9110 + end + attribute \src "libresoc.v:156113.3-156114.37" + process $proc$libresoc.v:156113$8952 + assign { } { } + assign $0\xer_ca$22[1:0]$8953 \xer_ca$22$next + sync posedge \coresync_clk + update \xer_ca$22 $0\xer_ca$22[1:0]$8953 + end + attribute \src "libresoc.v:156115.3-156116.43" + process $proc$libresoc.v:156115$8954 + assign { } { } + assign $0\xer_ca_ok$23[0:0]$8955 \xer_ca_ok$23$next + sync posedge \coresync_clk + update \xer_ca_ok$23 $0\xer_ca_ok$23[0:0]$8955 + end + attribute \src "libresoc.v:156117.3-156118.33" + process $proc$libresoc.v:156117$8956 + assign { } { } + assign $0\cr_a$20[3:0]$8957 \cr_a$20$next + sync posedge \coresync_clk + update \cr_a$20 $0\cr_a$20[3:0]$8957 + end + attribute \src "libresoc.v:156119.3-156120.39" + process $proc$libresoc.v:156119$8958 + assign { } { } + assign $0\cr_a_ok$21[0:0]$8959 \cr_a_ok$21$next + sync posedge \coresync_clk + update \cr_a_ok$21 $0\cr_a_ok$21[0:0]$8959 + end + attribute \src "libresoc.v:156121.3-156122.27" + process $proc$libresoc.v:156121$8960 + assign { } { } + assign $0\o$18[63:0]$8961 \o$18$next + sync posedge \coresync_clk + update \o$18 $0\o$18[63:0]$8961 + end + attribute \src "libresoc.v:156123.3-156124.33" + process $proc$libresoc.v:156123$8962 + assign { } { } + assign $0\o_ok$19[0:0]$8963 \o_ok$19$next + sync posedge \coresync_clk + update \o_ok$19 $0\o_ok$19[0:0]$8963 + end + attribute \src "libresoc.v:156125.3-156126.55" + process $proc$libresoc.v:156125$8964 + assign { } { } + assign $0\sr_op__insn_type$2[6:0]$8965 \sr_op__insn_type$2$next + sync posedge \coresync_clk + update \sr_op__insn_type$2 $0\sr_op__insn_type$2[6:0]$8965 + end + attribute \src "libresoc.v:156127.3-156128.51" + process $proc$libresoc.v:156127$8966 + assign { } { } + assign $0\sr_op__fn_unit$3[11:0]$8967 \sr_op__fn_unit$3$next + sync posedge \coresync_clk + update \sr_op__fn_unit$3 $0\sr_op__fn_unit$3[11:0]$8967 + end + attribute \src "libresoc.v:156129.3-156130.65" + process $proc$libresoc.v:156129$8968 + assign { } { } + assign $0\sr_op__imm_data__data$4[63:0]$8969 \sr_op__imm_data__data$4$next + sync posedge \coresync_clk + update \sr_op__imm_data__data$4 $0\sr_op__imm_data__data$4[63:0]$8969 + end + attribute \src "libresoc.v:156131.3-156132.61" + process $proc$libresoc.v:156131$8970 + assign { } { } + assign $0\sr_op__imm_data__ok$5[0:0]$8971 \sr_op__imm_data__ok$5$next + sync posedge \coresync_clk + update \sr_op__imm_data__ok$5 $0\sr_op__imm_data__ok$5[0:0]$8971 + end + attribute \src "libresoc.v:156133.3-156134.49" + process $proc$libresoc.v:156133$8972 + assign { } { } + assign $0\sr_op__rc__rc$6[0:0]$8973 \sr_op__rc__rc$6$next + sync posedge \coresync_clk + update \sr_op__rc__rc$6 $0\sr_op__rc__rc$6[0:0]$8973 + end + attribute \src "libresoc.v:156135.3-156136.49" + process $proc$libresoc.v:156135$8974 + assign { } { } + assign $0\sr_op__rc__ok$7[0:0]$8975 \sr_op__rc__ok$7$next + sync posedge \coresync_clk + update \sr_op__rc__ok$7 $0\sr_op__rc__ok$7[0:0]$8975 + end + attribute \src "libresoc.v:156137.3-156138.49" + process $proc$libresoc.v:156137$8976 + assign { } { } + assign $0\sr_op__oe__oe$8[0:0]$8977 \sr_op__oe__oe$8$next + sync posedge \coresync_clk + update \sr_op__oe__oe$8 $0\sr_op__oe__oe$8[0:0]$8977 + end + attribute \src "libresoc.v:156139.3-156140.49" + process $proc$libresoc.v:156139$8978 + assign { } { } + assign $0\sr_op__oe__ok$9[0:0]$8979 \sr_op__oe__ok$9$next + sync posedge \coresync_clk + update \sr_op__oe__ok$9 $0\sr_op__oe__ok$9[0:0]$8979 + end + attribute \src "libresoc.v:156141.3-156142.57" + process $proc$libresoc.v:156141$8980 + assign { } { } + assign $0\sr_op__write_cr0$10[0:0]$8981 \sr_op__write_cr0$10$next + sync posedge \coresync_clk + update \sr_op__write_cr0$10 $0\sr_op__write_cr0$10[0:0]$8981 + end + attribute \src "libresoc.v:156143.3-156144.61" + process $proc$libresoc.v:156143$8982 + assign { } { } + assign $0\sr_op__input_carry$11[1:0]$8983 \sr_op__input_carry$11$next + sync posedge \coresync_clk + update \sr_op__input_carry$11 $0\sr_op__input_carry$11[1:0]$8983 + end + attribute \src "libresoc.v:156145.3-156146.63" + process $proc$libresoc.v:156145$8984 + assign { } { } + assign $0\sr_op__output_carry$12[0:0]$8985 \sr_op__output_carry$12$next + sync posedge \coresync_clk + update \sr_op__output_carry$12 $0\sr_op__output_carry$12[0:0]$8985 + end + attribute \src "libresoc.v:156147.3-156148.55" + process $proc$libresoc.v:156147$8986 + assign { } { } + assign $0\sr_op__input_cr$13[0:0]$8987 \sr_op__input_cr$13$next + sync posedge \coresync_clk + update \sr_op__input_cr$13 $0\sr_op__input_cr$13[0:0]$8987 + end + attribute \src "libresoc.v:156149.3-156150.57" + process $proc$libresoc.v:156149$8988 + assign { } { } + assign $0\sr_op__output_cr$14[0:0]$8989 \sr_op__output_cr$14$next + sync posedge \coresync_clk + update \sr_op__output_cr$14 $0\sr_op__output_cr$14[0:0]$8989 + end + attribute \src "libresoc.v:156151.3-156152.55" + process $proc$libresoc.v:156151$8990 + assign { } { } + assign $0\sr_op__is_32bit$15[0:0]$8991 \sr_op__is_32bit$15$next + sync posedge \coresync_clk + update \sr_op__is_32bit$15 $0\sr_op__is_32bit$15[0:0]$8991 + end + attribute \src "libresoc.v:156153.3-156154.57" + process $proc$libresoc.v:156153$8992 + assign { } { } + assign $0\sr_op__is_signed$16[0:0]$8993 \sr_op__is_signed$16$next + sync posedge \coresync_clk + update \sr_op__is_signed$16 $0\sr_op__is_signed$16[0:0]$8993 + end + attribute \src "libresoc.v:156155.3-156156.47" + process $proc$libresoc.v:156155$8994 + assign { } { } + assign $0\sr_op__insn$17[31:0]$8995 \sr_op__insn$17$next + sync posedge \coresync_clk + update \sr_op__insn$17 $0\sr_op__insn$17[31:0]$8995 + end + attribute \src "libresoc.v:156157.3-156158.33" + process $proc$libresoc.v:156157$8996 + assign { } { } + assign $0\muxid$1[1:0]$8997 \muxid$1$next + sync posedge \coresync_clk + update \muxid$1 $0\muxid$1[1:0]$8997 + end + attribute \src "libresoc.v:156159.3-156160.29" + process $proc$libresoc.v:156159$8998 + assign { } { } + assign $0\r_busy[0:0] \r_busy$next + sync posedge \coresync_clk + update \r_busy $0\r_busy[0:0] + end + attribute \src "libresoc.v:156216.3-156233.6" + process $proc$libresoc.v:156216$8999 + assign { } { } + assign { } { } + assign { } { } + assign $0\r_busy$next[0:0]$9000 $2\r_busy$next[0:0]$9002 + attribute \src "libresoc.v:156217.5-156217.29" + switch \initial + attribute \src "libresoc.v:156217.9-156217.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\r_busy$next[0:0]$9001 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\r_busy$next[0:0]$9001 1'0 + case + assign $1\r_busy$next[0:0]$9001 \r_busy + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r_busy$next[0:0]$9002 1'0 + case + assign $2\r_busy$next[0:0]$9002 $1\r_busy$next[0:0]$9001 + end + sync always + update \r_busy$next $0\r_busy$next[0:0]$9000 + end + attribute \src "libresoc.v:156234.3-156246.6" + process $proc$libresoc.v:156234$9003 + assign { } { } + assign { } { } + assign $0\muxid$1$next[1:0]$9004 $1\muxid$1$next[1:0]$9005 + attribute \src "libresoc.v:156235.5-156235.29" + switch \initial + attribute \src "libresoc.v:156235.9-156235.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\muxid$1$next[1:0]$9005 \muxid$51 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\muxid$1$next[1:0]$9005 \muxid$51 + case + assign $1\muxid$1$next[1:0]$9005 \muxid$1 + end + sync always + update \muxid$1$next $0\muxid$1$next[1:0]$9004 + end + attribute \src "libresoc.v:156247.3-156286.6" + process $proc$libresoc.v:156247$9006 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\sr_op__fn_unit$3$next[11:0]$9007 $1\sr_op__fn_unit$3$next[11:0]$9023 + assign { } { } + assign { } { } + assign $0\sr_op__input_carry$11$next[1:0]$9010 $1\sr_op__input_carry$11$next[1:0]$9026 + assign $0\sr_op__input_cr$13$next[0:0]$9011 $1\sr_op__input_cr$13$next[0:0]$9027 + assign $0\sr_op__insn$17$next[31:0]$9012 $1\sr_op__insn$17$next[31:0]$9028 + assign $0\sr_op__insn_type$2$next[6:0]$9013 $1\sr_op__insn_type$2$next[6:0]$9029 + assign $0\sr_op__is_32bit$15$next[0:0]$9014 $1\sr_op__is_32bit$15$next[0:0]$9030 + assign $0\sr_op__is_signed$16$next[0:0]$9015 $1\sr_op__is_signed$16$next[0:0]$9031 + assign { } { } + assign { } { } + assign $0\sr_op__output_carry$12$next[0:0]$9018 $1\sr_op__output_carry$12$next[0:0]$9034 + assign $0\sr_op__output_cr$14$next[0:0]$9019 $1\sr_op__output_cr$14$next[0:0]$9035 + assign { } { } + assign { } { } + assign $0\sr_op__write_cr0$10$next[0:0]$9022 $1\sr_op__write_cr0$10$next[0:0]$9038 + assign $0\sr_op__imm_data__data$4$next[63:0]$9008 $2\sr_op__imm_data__data$4$next[63:0]$9039 + assign $0\sr_op__imm_data__ok$5$next[0:0]$9009 $2\sr_op__imm_data__ok$5$next[0:0]$9040 + assign $0\sr_op__oe__oe$8$next[0:0]$9016 $2\sr_op__oe__oe$8$next[0:0]$9041 + assign $0\sr_op__oe__ok$9$next[0:0]$9017 $2\sr_op__oe__ok$9$next[0:0]$9042 + assign $0\sr_op__rc__ok$7$next[0:0]$9020 $2\sr_op__rc__ok$7$next[0:0]$9043 + assign $0\sr_op__rc__rc$6$next[0:0]$9021 $2\sr_op__rc__rc$6$next[0:0]$9044 + attribute \src "libresoc.v:156248.5-156248.29" + switch \initial + attribute \src "libresoc.v:156248.9-156248.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\sr_op__insn$17$next[31:0]$9028 $1\sr_op__is_signed$16$next[0:0]$9031 $1\sr_op__is_32bit$15$next[0:0]$9030 $1\sr_op__output_cr$14$next[0:0]$9035 $1\sr_op__input_cr$13$next[0:0]$9027 $1\sr_op__output_carry$12$next[0:0]$9034 $1\sr_op__input_carry$11$next[1:0]$9026 $1\sr_op__write_cr0$10$next[0:0]$9038 $1\sr_op__oe__ok$9$next[0:0]$9033 $1\sr_op__oe__oe$8$next[0:0]$9032 $1\sr_op__rc__ok$7$next[0:0]$9036 $1\sr_op__rc__rc$6$next[0:0]$9037 $1\sr_op__imm_data__ok$5$next[0:0]$9025 $1\sr_op__imm_data__data$4$next[63:0]$9024 $1\sr_op__fn_unit$3$next[11:0]$9023 $1\sr_op__insn_type$2$next[6:0]$9029 } { \sr_op__insn$67 \sr_op__is_signed$66 \sr_op__is_32bit$65 \sr_op__output_cr$64 \sr_op__input_cr$63 \sr_op__output_carry$62 \sr_op__input_carry$61 \sr_op__write_cr0$60 \sr_op__oe__ok$59 \sr_op__oe__oe$58 \sr_op__rc__ok$57 \sr_op__rc__rc$56 \sr_op__imm_data__ok$55 \sr_op__imm_data__data$54 \sr_op__fn_unit$53 \sr_op__insn_type$52 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\sr_op__insn$17$next[31:0]$9028 $1\sr_op__is_signed$16$next[0:0]$9031 $1\sr_op__is_32bit$15$next[0:0]$9030 $1\sr_op__output_cr$14$next[0:0]$9035 $1\sr_op__input_cr$13$next[0:0]$9027 $1\sr_op__output_carry$12$next[0:0]$9034 $1\sr_op__input_carry$11$next[1:0]$9026 $1\sr_op__write_cr0$10$next[0:0]$9038 $1\sr_op__oe__ok$9$next[0:0]$9033 $1\sr_op__oe__oe$8$next[0:0]$9032 $1\sr_op__rc__ok$7$next[0:0]$9036 $1\sr_op__rc__rc$6$next[0:0]$9037 $1\sr_op__imm_data__ok$5$next[0:0]$9025 $1\sr_op__imm_data__data$4$next[63:0]$9024 $1\sr_op__fn_unit$3$next[11:0]$9023 $1\sr_op__insn_type$2$next[6:0]$9029 } { \sr_op__insn$67 \sr_op__is_signed$66 \sr_op__is_32bit$65 \sr_op__output_cr$64 \sr_op__input_cr$63 \sr_op__output_carry$62 \sr_op__input_carry$61 \sr_op__write_cr0$60 \sr_op__oe__ok$59 \sr_op__oe__oe$58 \sr_op__rc__ok$57 \sr_op__rc__rc$56 \sr_op__imm_data__ok$55 \sr_op__imm_data__data$54 \sr_op__fn_unit$53 \sr_op__insn_type$52 } + case + assign $1\sr_op__fn_unit$3$next[11:0]$9023 \sr_op__fn_unit$3 + assign $1\sr_op__imm_data__data$4$next[63:0]$9024 \sr_op__imm_data__data$4 + assign $1\sr_op__imm_data__ok$5$next[0:0]$9025 \sr_op__imm_data__ok$5 + assign $1\sr_op__input_carry$11$next[1:0]$9026 \sr_op__input_carry$11 + assign $1\sr_op__input_cr$13$next[0:0]$9027 \sr_op__input_cr$13 + assign $1\sr_op__insn$17$next[31:0]$9028 \sr_op__insn$17 + assign $1\sr_op__insn_type$2$next[6:0]$9029 \sr_op__insn_type$2 + assign $1\sr_op__is_32bit$15$next[0:0]$9030 \sr_op__is_32bit$15 + assign $1\sr_op__is_signed$16$next[0:0]$9031 \sr_op__is_signed$16 + assign $1\sr_op__oe__oe$8$next[0:0]$9032 \sr_op__oe__oe$8 + assign $1\sr_op__oe__ok$9$next[0:0]$9033 \sr_op__oe__ok$9 + assign $1\sr_op__output_carry$12$next[0:0]$9034 \sr_op__output_carry$12 + assign $1\sr_op__output_cr$14$next[0:0]$9035 \sr_op__output_cr$14 + assign $1\sr_op__rc__ok$7$next[0:0]$9036 \sr_op__rc__ok$7 + assign $1\sr_op__rc__rc$6$next[0:0]$9037 \sr_op__rc__rc$6 + assign $1\sr_op__write_cr0$10$next[0:0]$9038 \sr_op__write_cr0$10 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $2\sr_op__imm_data__data$4$next[63:0]$9039 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\sr_op__imm_data__ok$5$next[0:0]$9040 1'0 + assign $2\sr_op__rc__rc$6$next[0:0]$9044 1'0 + assign $2\sr_op__rc__ok$7$next[0:0]$9043 1'0 + assign $2\sr_op__oe__oe$8$next[0:0]$9041 1'0 + assign $2\sr_op__oe__ok$9$next[0:0]$9042 1'0 + case + assign $2\sr_op__imm_data__data$4$next[63:0]$9039 $1\sr_op__imm_data__data$4$next[63:0]$9024 + assign $2\sr_op__imm_data__ok$5$next[0:0]$9040 $1\sr_op__imm_data__ok$5$next[0:0]$9025 + assign $2\sr_op__oe__oe$8$next[0:0]$9041 $1\sr_op__oe__oe$8$next[0:0]$9032 + assign $2\sr_op__oe__ok$9$next[0:0]$9042 $1\sr_op__oe__ok$9$next[0:0]$9033 + assign $2\sr_op__rc__ok$7$next[0:0]$9043 $1\sr_op__rc__ok$7$next[0:0]$9036 + assign $2\sr_op__rc__rc$6$next[0:0]$9044 $1\sr_op__rc__rc$6$next[0:0]$9037 + end + sync always + update \sr_op__fn_unit$3$next $0\sr_op__fn_unit$3$next[11:0]$9007 + update \sr_op__imm_data__data$4$next $0\sr_op__imm_data__data$4$next[63:0]$9008 + update \sr_op__imm_data__ok$5$next $0\sr_op__imm_data__ok$5$next[0:0]$9009 + update \sr_op__input_carry$11$next $0\sr_op__input_carry$11$next[1:0]$9010 + update \sr_op__input_cr$13$next $0\sr_op__input_cr$13$next[0:0]$9011 + update \sr_op__insn$17$next $0\sr_op__insn$17$next[31:0]$9012 + update \sr_op__insn_type$2$next $0\sr_op__insn_type$2$next[6:0]$9013 + update \sr_op__is_32bit$15$next $0\sr_op__is_32bit$15$next[0:0]$9014 + update \sr_op__is_signed$16$next $0\sr_op__is_signed$16$next[0:0]$9015 + update \sr_op__oe__oe$8$next $0\sr_op__oe__oe$8$next[0:0]$9016 + update \sr_op__oe__ok$9$next $0\sr_op__oe__ok$9$next[0:0]$9017 + update \sr_op__output_carry$12$next $0\sr_op__output_carry$12$next[0:0]$9018 + update \sr_op__output_cr$14$next $0\sr_op__output_cr$14$next[0:0]$9019 + update \sr_op__rc__ok$7$next $0\sr_op__rc__ok$7$next[0:0]$9020 + update \sr_op__rc__rc$6$next $0\sr_op__rc__rc$6$next[0:0]$9021 + update \sr_op__write_cr0$10$next $0\sr_op__write_cr0$10$next[0:0]$9022 + end + attribute \src "libresoc.v:156287.3-156305.6" + process $proc$libresoc.v:156287$9045 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\o$18$next[63:0]$9046 $1\o$18$next[63:0]$9048 + assign { } { } + assign $0\o_ok$19$next[0:0]$9047 $2\o_ok$19$next[0:0]$9050 + attribute \src "libresoc.v:156288.5-156288.29" + switch \initial + attribute \src "libresoc.v:156288.9-156288.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\o_ok$19$next[0:0]$9049 $1\o$18$next[63:0]$9048 } { \o_ok$69 \o$68 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\o_ok$19$next[0:0]$9049 $1\o$18$next[63:0]$9048 } { \o_ok$69 \o$68 } + case + assign $1\o$18$next[63:0]$9048 \o$18 + assign $1\o_ok$19$next[0:0]$9049 \o_ok$19 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\o_ok$19$next[0:0]$9050 1'0 + case + assign $2\o_ok$19$next[0:0]$9050 $1\o_ok$19$next[0:0]$9049 + end + sync always + update \o$18$next $0\o$18$next[63:0]$9046 + update \o_ok$19$next $0\o_ok$19$next[0:0]$9047 + end + attribute \src "libresoc.v:156306.3-156324.6" + process $proc$libresoc.v:156306$9051 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\cr_a$20$next[3:0]$9052 $1\cr_a$20$next[3:0]$9054 + assign { } { } + assign $0\cr_a_ok$21$next[0:0]$9053 $2\cr_a_ok$21$next[0:0]$9056 + attribute \src "libresoc.v:156307.5-156307.29" + switch \initial + attribute \src "libresoc.v:156307.9-156307.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\cr_a_ok$21$next[0:0]$9055 $1\cr_a$20$next[3:0]$9054 } { \cr_a_ok$71 \cr_a$70 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\cr_a_ok$21$next[0:0]$9055 $1\cr_a$20$next[3:0]$9054 } { \cr_a_ok$71 \cr_a$70 } + case + assign $1\cr_a$20$next[3:0]$9054 \cr_a$20 + assign $1\cr_a_ok$21$next[0:0]$9055 \cr_a_ok$21 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_a_ok$21$next[0:0]$9056 1'0 + case + assign $2\cr_a_ok$21$next[0:0]$9056 $1\cr_a_ok$21$next[0:0]$9055 + end + sync always + update \cr_a$20$next $0\cr_a$20$next[3:0]$9052 + update \cr_a_ok$21$next $0\cr_a_ok$21$next[0:0]$9053 + end + attribute \src "libresoc.v:156325.3-156343.6" + process $proc$libresoc.v:156325$9057 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\xer_ca$22$next[1:0]$9058 $1\xer_ca$22$next[1:0]$9060 + assign { } { } + assign $0\xer_ca_ok$23$next[0:0]$9059 $2\xer_ca_ok$23$next[0:0]$9062 + attribute \src "libresoc.v:156326.5-156326.29" + switch \initial + attribute \src "libresoc.v:156326.9-156326.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\xer_ca_ok$23$next[0:0]$9061 $1\xer_ca$22$next[1:0]$9060 } { \xer_ca_ok$73 \xer_ca$72 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\xer_ca_ok$23$next[0:0]$9061 $1\xer_ca$22$next[1:0]$9060 } { \xer_ca_ok$73 \xer_ca$72 } + case + assign $1\xer_ca$22$next[1:0]$9060 \xer_ca$22 + assign $1\xer_ca_ok$23$next[0:0]$9061 \xer_ca_ok$23 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\xer_ca_ok$23$next[0:0]$9062 1'0 + case + assign $2\xer_ca_ok$23$next[0:0]$9062 $1\xer_ca_ok$23$next[0:0]$9061 + end + sync always + update \xer_ca$22$next $0\xer_ca$22$next[1:0]$9058 + update \xer_ca_ok$23$next $0\xer_ca_ok$23$next[0:0]$9059 + end + connect \$49 $and$libresoc.v:156112$8951_Y + connect \p_ready_o \n_i_rdy_data + connect \n_valid_o \r_busy + connect { \xer_ca_ok$73 \xer_ca$72 } { \output_xer_ca_ok \output_xer_ca$44 } + connect { \cr_a_ok$71 \cr_a$70 } { \output_cr_a_ok \output_cr_a$43 } + connect { \o_ok$69 \o$68 } { \output_o_ok$42 \output_o$41 } + connect { \sr_op__insn$67 \sr_op__is_signed$66 \sr_op__is_32bit$65 \sr_op__output_cr$64 \sr_op__input_cr$63 \sr_op__output_carry$62 \sr_op__input_carry$61 \sr_op__write_cr0$60 \sr_op__oe__ok$59 \sr_op__oe__oe$58 \sr_op__rc__ok$57 \sr_op__rc__rc$56 \sr_op__imm_data__ok$55 \sr_op__imm_data__data$54 \sr_op__fn_unit$53 \sr_op__insn_type$52 } { \output_sr_op__insn$40 \output_sr_op__is_signed$39 \output_sr_op__is_32bit$38 \output_sr_op__output_cr$37 \output_sr_op__input_cr$36 \output_sr_op__output_carry$35 \output_sr_op__input_carry$34 \output_sr_op__write_cr0$33 \output_sr_op__oe__ok$32 \output_sr_op__oe__oe$31 \output_sr_op__rc__ok$30 \output_sr_op__rc__rc$29 \output_sr_op__imm_data__ok$28 \output_sr_op__imm_data__data$27 \output_sr_op__fn_unit$26 \output_sr_op__insn_type$25 } + connect \muxid$51 \output_muxid$24 + connect \p_valid_i_p_ready_o \$49 + connect \n_i_rdy_data \n_ready_i + connect \p_valid_i$48 \p_valid_i + connect { \xer_ca_ok$47 \output_xer_ca } { \xer_ca_ok \xer_ca } + connect { \xer_so_ok$46 \output_xer_so } { \xer_so_ok \xer_so } + connect { \cr_a_ok$45 \output_cr_a } { \cr_a_ok \cr_a } + connect { \output_o_ok \output_o } { \o_ok \o } + connect { \output_sr_op__insn \output_sr_op__is_signed \output_sr_op__is_32bit \output_sr_op__output_cr \output_sr_op__input_cr \output_sr_op__output_carry \output_sr_op__input_carry \output_sr_op__write_cr0 \output_sr_op__oe__ok \output_sr_op__oe__oe \output_sr_op__rc__ok \output_sr_op__rc__rc \output_sr_op__imm_data__ok \output_sr_op__imm_data__data \output_sr_op__fn_unit \output_sr_op__insn_type } { \sr_op__insn \sr_op__is_signed \sr_op__is_32bit \sr_op__output_cr \sr_op__input_cr \sr_op__output_carry \sr_op__input_carry \sr_op__write_cr0 \sr_op__oe__ok \sr_op__oe__oe \sr_op__rc__ok \sr_op__rc__rc \sr_op__imm_data__ok \sr_op__imm_data__data \sr_op__fn_unit \sr_op__insn_type } + connect \output_muxid \muxid +end +attribute \src "libresoc.v:156364.1-157846.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_end" +attribute \generator "nMigen" +module \pipe_end + attribute \src "libresoc.v:157684.3-157702.6" + wire width 4 $0\cr_a$next[3:0]$9167 + attribute \src "libresoc.v:157503.3-157504.25" + wire width 4 $0\cr_a[3:0] + attribute \src "libresoc.v:157684.3-157702.6" + wire $0\cr_a_ok$next[0:0]$9168 + attribute \src "libresoc.v:157505.3-157506.31" + wire $0\cr_a_ok[0:0] + attribute \src "libresoc.v:156365.7-156365.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:157772.3-157813.6" + wire width 4 $0\logical_op__data_len$18$next[3:0]$9192 + attribute \src "libresoc.v:157543.3-157544.65" + wire width 4 $0\logical_op__data_len$18[3:0]$9154 + attribute \src "libresoc.v:156406.13-156406.45" + wire width 4 $0\logical_op__data_len$18[3:0]$9238 + attribute \src "libresoc.v:157772.3-157813.6" + wire width 12 $0\logical_op__fn_unit$3$next[11:0]$9193 + attribute \src "libresoc.v:157513.3-157514.61" + wire width 12 $0\logical_op__fn_unit$3[11:0]$9124 + attribute \src "libresoc.v:156441.14-156441.47" + wire width 12 $0\logical_op__fn_unit$3[11:0]$9240 + attribute \src "libresoc.v:157772.3-157813.6" + wire width 64 $0\logical_op__imm_data__data$4$next[63:0]$9194 + attribute \src "libresoc.v:157515.3-157516.75" + wire width 64 $0\logical_op__imm_data__data$4[63:0]$9126 + attribute \src "libresoc.v:156463.14-156463.67" + wire width 64 $0\logical_op__imm_data__data$4[63:0]$9242 + attribute \src "libresoc.v:157772.3-157813.6" + wire $0\logical_op__imm_data__ok$5$next[0:0]$9195 + attribute \src "libresoc.v:157517.3-157518.71" + wire $0\logical_op__imm_data__ok$5[0:0]$9128 + attribute \src "libresoc.v:156472.7-156472.42" + wire $0\logical_op__imm_data__ok$5[0:0]$9244 + attribute \src "libresoc.v:157772.3-157813.6" + wire width 2 $0\logical_op__input_carry$12$next[1:0]$9196 + attribute \src "libresoc.v:157531.3-157532.71" + wire width 2 $0\logical_op__input_carry$12[1:0]$9142 + attribute \src "libresoc.v:156489.13-156489.48" + wire width 2 $0\logical_op__input_carry$12[1:0]$9246 + attribute \src "libresoc.v:157772.3-157813.6" + wire width 32 $0\logical_op__insn$19$next[31:0]$9197 + attribute \src "libresoc.v:157545.3-157546.57" + wire width 32 $0\logical_op__insn$19[31:0]$9156 + attribute \src "libresoc.v:156502.14-156502.43" + wire width 32 $0\logical_op__insn$19[31:0]$9248 + attribute \src "libresoc.v:157772.3-157813.6" + wire width 7 $0\logical_op__insn_type$2$next[6:0]$9198 + attribute \src "libresoc.v:157511.3-157512.65" + wire width 7 $0\logical_op__insn_type$2[6:0]$9122 + attribute \src "libresoc.v:156659.13-156659.46" + wire width 7 $0\logical_op__insn_type$2[6:0]$9250 + attribute \src "libresoc.v:157772.3-157813.6" + wire $0\logical_op__invert_in$10$next[0:0]$9199 + attribute \src "libresoc.v:157527.3-157528.67" + wire $0\logical_op__invert_in$10[0:0]$9138 + attribute \src "libresoc.v:156742.7-156742.40" + wire $0\logical_op__invert_in$10[0:0]$9252 + attribute \src "libresoc.v:157772.3-157813.6" + wire $0\logical_op__invert_out$13$next[0:0]$9200 + attribute \src "libresoc.v:157533.3-157534.69" + wire $0\logical_op__invert_out$13[0:0]$9144 + attribute \src "libresoc.v:156751.7-156751.41" + wire $0\logical_op__invert_out$13[0:0]$9254 + attribute \src "libresoc.v:157772.3-157813.6" + wire $0\logical_op__is_32bit$16$next[0:0]$9201 + attribute \src "libresoc.v:157539.3-157540.65" + wire $0\logical_op__is_32bit$16[0:0]$9150 + attribute \src "libresoc.v:156760.7-156760.39" + wire $0\logical_op__is_32bit$16[0:0]$9256 + attribute \src "libresoc.v:157772.3-157813.6" + wire $0\logical_op__is_signed$17$next[0:0]$9202 + attribute \src "libresoc.v:157541.3-157542.67" + wire $0\logical_op__is_signed$17[0:0]$9152 + attribute \src "libresoc.v:156769.7-156769.40" + wire $0\logical_op__is_signed$17[0:0]$9258 + attribute \src "libresoc.v:157772.3-157813.6" + wire $0\logical_op__oe__oe$8$next[0:0]$9203 + attribute \src "libresoc.v:157523.3-157524.59" + wire $0\logical_op__oe__oe$8[0:0]$9134 + attribute \src "libresoc.v:156778.7-156778.36" + wire $0\logical_op__oe__oe$8[0:0]$9260 + attribute \src "libresoc.v:157772.3-157813.6" + wire $0\logical_op__oe__ok$9$next[0:0]$9204 + attribute \src "libresoc.v:157525.3-157526.59" + wire $0\logical_op__oe__ok$9[0:0]$9136 + attribute \src "libresoc.v:156789.7-156789.36" + wire $0\logical_op__oe__ok$9[0:0]$9262 + attribute \src "libresoc.v:157772.3-157813.6" + wire $0\logical_op__output_carry$15$next[0:0]$9205 + attribute \src "libresoc.v:157537.3-157538.73" + wire $0\logical_op__output_carry$15[0:0]$9148 + attribute \src "libresoc.v:156796.7-156796.43" + wire $0\logical_op__output_carry$15[0:0]$9264 + attribute \src "libresoc.v:157772.3-157813.6" + wire $0\logical_op__rc__ok$7$next[0:0]$9206 + attribute \src "libresoc.v:157521.3-157522.59" + wire $0\logical_op__rc__ok$7[0:0]$9132 + attribute \src "libresoc.v:156805.7-156805.36" + wire $0\logical_op__rc__ok$7[0:0]$9266 + attribute \src "libresoc.v:157772.3-157813.6" + wire $0\logical_op__rc__rc$6$next[0:0]$9207 + attribute \src "libresoc.v:157519.3-157520.59" + wire $0\logical_op__rc__rc$6[0:0]$9130 + attribute \src "libresoc.v:156814.7-156814.36" + wire $0\logical_op__rc__rc$6[0:0]$9268 + attribute \src "libresoc.v:157772.3-157813.6" + wire $0\logical_op__write_cr0$14$next[0:0]$9208 + attribute \src "libresoc.v:157535.3-157536.67" + wire $0\logical_op__write_cr0$14[0:0]$9146 + attribute \src "libresoc.v:156823.7-156823.40" + wire $0\logical_op__write_cr0$14[0:0]$9270 + attribute \src "libresoc.v:157772.3-157813.6" + wire $0\logical_op__zero_a$11$next[0:0]$9209 + attribute \src "libresoc.v:157529.3-157530.61" + wire $0\logical_op__zero_a$11[0:0]$9140 + attribute \src "libresoc.v:156832.7-156832.37" + wire $0\logical_op__zero_a$11[0:0]$9272 + attribute \src "libresoc.v:157759.3-157771.6" + wire width 2 $0\muxid$1$next[1:0]$9189 + attribute \src "libresoc.v:157547.3-157548.33" + wire width 2 $0\muxid$1[1:0]$9158 + attribute \src "libresoc.v:156841.13-156841.29" + wire width 2 $0\muxid$1[1:0]$9274 + attribute \src "libresoc.v:157665.3-157683.6" + wire width 64 $0\o$next[63:0]$9161 + attribute \src "libresoc.v:157507.3-157508.19" + wire width 64 $0\o[63:0] + attribute \src "libresoc.v:157665.3-157683.6" + wire $0\o_ok$next[0:0]$9162 + attribute \src "libresoc.v:157509.3-157510.25" + wire $0\o_ok[0:0] + attribute \src "libresoc.v:157741.3-157758.6" + wire $0\r_busy$next[0:0]$9185 + attribute \src "libresoc.v:157549.3-157550.29" + wire $0\r_busy[0:0] + attribute \src "libresoc.v:157703.3-157721.6" + wire width 2 $0\xer_ov$next[1:0]$9173 + attribute \src "libresoc.v:157499.3-157500.29" + wire width 2 $0\xer_ov[1:0] + attribute \src "libresoc.v:157703.3-157721.6" + wire $0\xer_ov_ok$next[0:0]$9174 + attribute \src "libresoc.v:157501.3-157502.35" + wire $0\xer_ov_ok[0:0] + attribute \src "libresoc.v:157722.3-157740.6" + wire $0\xer_so$20$next[0:0]$9180 + attribute \src "libresoc.v:157495.3-157496.37" + wire $0\xer_so$20[0:0]$9113 + attribute \src "libresoc.v:157480.7-157480.25" + wire $0\xer_so$20[0:0]$9281 + attribute \src "libresoc.v:157722.3-157740.6" + wire $0\xer_so_ok$next[0:0]$9179 + attribute \src "libresoc.v:157497.3-157498.35" + wire $0\xer_so_ok[0:0] + attribute \src "libresoc.v:157684.3-157702.6" + wire width 4 $1\cr_a$next[3:0]$9169 + attribute \src "libresoc.v:156374.13-156374.24" + wire width 4 $1\cr_a[3:0] + attribute \src "libresoc.v:157684.3-157702.6" + wire $1\cr_a_ok$next[0:0]$9170 + attribute \src "libresoc.v:156383.7-156383.21" + wire $1\cr_a_ok[0:0] + attribute \src "libresoc.v:157772.3-157813.6" + wire width 4 $1\logical_op__data_len$18$next[3:0]$9210 + attribute \src "libresoc.v:157772.3-157813.6" + wire width 12 $1\logical_op__fn_unit$3$next[11:0]$9211 + attribute \src "libresoc.v:157772.3-157813.6" + wire width 64 $1\logical_op__imm_data__data$4$next[63:0]$9212 + attribute \src "libresoc.v:157772.3-157813.6" + wire $1\logical_op__imm_data__ok$5$next[0:0]$9213 + attribute \src "libresoc.v:157772.3-157813.6" + wire width 2 $1\logical_op__input_carry$12$next[1:0]$9214 + attribute \src "libresoc.v:157772.3-157813.6" + wire width 32 $1\logical_op__insn$19$next[31:0]$9215 + attribute \src "libresoc.v:157772.3-157813.6" + wire width 7 $1\logical_op__insn_type$2$next[6:0]$9216 + attribute \src "libresoc.v:157772.3-157813.6" + wire $1\logical_op__invert_in$10$next[0:0]$9217 + attribute \src "libresoc.v:157772.3-157813.6" + wire $1\logical_op__invert_out$13$next[0:0]$9218 + attribute \src "libresoc.v:157772.3-157813.6" + wire $1\logical_op__is_32bit$16$next[0:0]$9219 + attribute \src "libresoc.v:157772.3-157813.6" + wire $1\logical_op__is_signed$17$next[0:0]$9220 + attribute \src "libresoc.v:157772.3-157813.6" + wire $1\logical_op__oe__oe$8$next[0:0]$9221 + attribute \src "libresoc.v:157772.3-157813.6" + wire $1\logical_op__oe__ok$9$next[0:0]$9222 + attribute \src "libresoc.v:157772.3-157813.6" + wire $1\logical_op__output_carry$15$next[0:0]$9223 + attribute \src "libresoc.v:157772.3-157813.6" + wire $1\logical_op__rc__ok$7$next[0:0]$9224 + attribute \src "libresoc.v:157772.3-157813.6" + wire $1\logical_op__rc__rc$6$next[0:0]$9225 + attribute \src "libresoc.v:157772.3-157813.6" + wire $1\logical_op__write_cr0$14$next[0:0]$9226 + attribute \src "libresoc.v:157772.3-157813.6" + wire $1\logical_op__zero_a$11$next[0:0]$9227 + attribute \src "libresoc.v:157759.3-157771.6" + wire width 2 $1\muxid$1$next[1:0]$9190 + attribute \src "libresoc.v:157665.3-157683.6" + wire width 64 $1\o$next[63:0]$9163 + attribute \src "libresoc.v:156854.14-156854.38" + wire width 64 $1\o[63:0] + attribute \src "libresoc.v:157665.3-157683.6" + wire $1\o_ok$next[0:0]$9164 + attribute \src "libresoc.v:156861.7-156861.18" + wire $1\o_ok[0:0] + attribute \src "libresoc.v:157741.3-157758.6" + wire $1\r_busy$next[0:0]$9186 + attribute \src "libresoc.v:157445.7-157445.20" + wire $1\r_busy[0:0] + attribute \src "libresoc.v:157703.3-157721.6" + wire width 2 $1\xer_ov$next[1:0]$9175 + attribute \src "libresoc.v:157460.13-157460.26" + wire width 2 $1\xer_ov[1:0] + attribute \src "libresoc.v:157703.3-157721.6" + wire $1\xer_ov_ok$next[0:0]$9176 + attribute \src "libresoc.v:157467.7-157467.23" + wire $1\xer_ov_ok[0:0] + attribute \src "libresoc.v:157722.3-157740.6" + wire $1\xer_so$20$next[0:0]$9182 + attribute \src "libresoc.v:157722.3-157740.6" + wire $1\xer_so_ok$next[0:0]$9181 + attribute \src "libresoc.v:157485.7-157485.23" + wire $1\xer_so_ok[0:0] + attribute \src "libresoc.v:157684.3-157702.6" + wire $2\cr_a_ok$next[0:0]$9171 + attribute \src "libresoc.v:157772.3-157813.6" + wire width 64 $2\logical_op__imm_data__data$4$next[63:0]$9228 + attribute \src "libresoc.v:157772.3-157813.6" + wire $2\logical_op__imm_data__ok$5$next[0:0]$9229 + attribute \src "libresoc.v:157772.3-157813.6" + wire $2\logical_op__oe__oe$8$next[0:0]$9230 + attribute \src "libresoc.v:157772.3-157813.6" + wire $2\logical_op__oe__ok$9$next[0:0]$9231 + attribute \src "libresoc.v:157772.3-157813.6" + wire $2\logical_op__rc__ok$7$next[0:0]$9232 + attribute \src "libresoc.v:157772.3-157813.6" + wire $2\logical_op__rc__rc$6$next[0:0]$9233 + attribute \src "libresoc.v:157665.3-157683.6" + wire $2\o_ok$next[0:0]$9165 + attribute \src "libresoc.v:157741.3-157758.6" + wire $2\r_busy$next[0:0]$9187 + attribute \src "libresoc.v:157703.3-157721.6" + wire $2\xer_ov_ok$next[0:0]$9177 + attribute \src "libresoc.v:157722.3-157740.6" + wire $2\xer_so_ok$next[0:0]$9183 + attribute \src "libresoc.v:157494.18-157494.118" + wire $and$libresoc.v:157494$9111_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + wire \$74 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 62 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 output 56 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \cr_a$68 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \cr_a$97 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \cr_a$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 57 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_a_ok$67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_a_ok$69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_a_ok$98 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_a_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire input 30 \div_by_zero + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire input 28 \dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire input 29 \dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire input 27 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire input 26 \divisor_neg + attribute \src "libresoc.v:156365.7-156365.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 21 \logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 52 \logical_op__data_len$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \logical_op__data_len$18$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \logical_op__data_len$93 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 6 \logical_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 output 37 \logical_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \logical_op__fn_unit$3$next + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \logical_op__fn_unit$78 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 7 \logical_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 38 \logical_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \logical_op__imm_data__data$4$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \logical_op__imm_data__data$79 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \logical_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 39 \logical_op__imm_data__ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__imm_data__ok$5$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__imm_data__ok$80 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 15 \logical_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 46 \logical_op__input_carry$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \logical_op__input_carry$12$next + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \logical_op__input_carry$87 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 22 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 53 \logical_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \logical_op__insn$19$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \logical_op__insn$94 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 5 \logical_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 36 \logical_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \logical_op__insn_type$2$next + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \logical_op__insn_type$77 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 44 \logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_in$10$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_in$85 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 16 \logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 47 \logical_op__invert_out$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_out$13$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_out$88 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 19 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 50 \logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_32bit$16$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_32bit$91 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 20 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 51 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_signed$17$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_signed$92 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 11 \logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 42 \logical_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__oe$8$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__oe$83 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__ok$84 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 43 \logical_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__ok$9$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 18 \logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 49 \logical_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__output_carry$15$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__output_carry$90 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 41 \logical_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__ok$7$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__ok$82 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 40 \logical_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__rc$6$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__rc$81 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 17 \logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 48 \logical_op__write_cr0$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__write_cr0$14$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__write_cr0$89 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 45 \logical_op__zero_a$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__zero_a$11$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__zero_a$86 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 4 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 35 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$1$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$76 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" + wire \n_i_rdy_data + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire input 34 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire output 33 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 54 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \o$95 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \o$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 55 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \o_ok$96 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \o_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \output_cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \output_cr_a$62 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \output_cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \output_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \output_logical_op__data_len$58 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \output_logical_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \output_logical_op__fn_unit$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \output_logical_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \output_logical_op__imm_data__data$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__imm_data__ok$45 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \output_logical_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \output_logical_op__input_carry$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \output_logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \output_logical_op__insn$59 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \output_logical_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \output_logical_op__insn_type$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__invert_in$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__invert_out$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__is_32bit$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__is_signed$57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__oe__oe$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__oe__ok$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__output_carry$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__rc__ok$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__rc__rc$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__write_cr0$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__zero_a$51 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \output_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \output_muxid$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \output_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \output_o$60 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \output_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \output_o_ok$61 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire \output_stage_div_by_zero + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire \output_stage_dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire \output_stage_dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire \output_stage_dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire \output_stage_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \output_stage_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \output_stage_logical_op__data_len$38 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \output_stage_logical_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \output_stage_logical_op__fn_unit$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \output_stage_logical_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \output_stage_logical_op__imm_data__data$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_stage_logical_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_stage_logical_op__imm_data__ok$25 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \output_stage_logical_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \output_stage_logical_op__input_carry$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \output_stage_logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \output_stage_logical_op__insn$39 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \output_stage_logical_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \output_stage_logical_op__insn_type$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_stage_logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_stage_logical_op__invert_in$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_stage_logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_stage_logical_op__invert_out$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_stage_logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_stage_logical_op__is_32bit$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_stage_logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_stage_logical_op__is_signed$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_stage_logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_stage_logical_op__oe__oe$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_stage_logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_stage_logical_op__oe__ok$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_stage_logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_stage_logical_op__output_carry$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_stage_logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_stage_logical_op__rc__ok$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_stage_logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_stage_logical_op__rc__rc$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_stage_logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_stage_logical_op__write_cr0$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_stage_logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_stage_logical_op__zero_a$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \output_stage_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \output_stage_muxid$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \output_stage_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \output_stage_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" + wire width 64 \output_stage_quotient_root + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:41" + wire width 192 \output_stage_remainder + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \output_stage_xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \output_stage_xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \output_stage_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \output_stage_xer_so$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \output_xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \output_xer_ov$63 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \output_xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \output_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \output_xer_so$64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \output_xer_so_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire output 3 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" + wire \p_valid_i$73 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" + wire width 64 input 31 \quotient_root + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire \r_busy$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 23 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \ra$65 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 24 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \rb$66 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:41" + wire width 192 input 32 \remainder + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 output 58 \xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \xer_ov$99 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \xer_ov$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 59 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \xer_ov_ok$100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \xer_ov_ok$70 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \xer_ov_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 25 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \xer_so$101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 60 \xer_so$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \xer_so$20$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 61 \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \xer_so_ok$102 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \xer_so_ok$71 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \xer_so_ok$72 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \xer_so_ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + cell $and $and$libresoc.v:157494$9111 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i$73 + connect \B \p_ready_o + connect \Y $and$libresoc.v:157494$9111_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:157551.10-157554.4" + cell \n$79 \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:157555.15-157607.4" + cell \output$80 \output + connect \cr_a \output_cr_a + connect \cr_a$22 \output_cr_a$62 + connect \cr_a_ok \output_cr_a_ok + connect \logical_op__data_len \output_logical_op__data_len + connect \logical_op__data_len$18 \output_logical_op__data_len$58 + connect \logical_op__fn_unit \output_logical_op__fn_unit + connect \logical_op__fn_unit$3 \output_logical_op__fn_unit$43 + connect \logical_op__imm_data__data \output_logical_op__imm_data__data + connect \logical_op__imm_data__data$4 \output_logical_op__imm_data__data$44 + connect \logical_op__imm_data__ok \output_logical_op__imm_data__ok + connect \logical_op__imm_data__ok$5 \output_logical_op__imm_data__ok$45 + connect \logical_op__input_carry \output_logical_op__input_carry + connect \logical_op__input_carry$12 \output_logical_op__input_carry$52 + connect \logical_op__insn \output_logical_op__insn + connect \logical_op__insn$19 \output_logical_op__insn$59 + connect \logical_op__insn_type \output_logical_op__insn_type + connect \logical_op__insn_type$2 \output_logical_op__insn_type$42 + connect \logical_op__invert_in \output_logical_op__invert_in + connect \logical_op__invert_in$10 \output_logical_op__invert_in$50 + connect \logical_op__invert_out \output_logical_op__invert_out + connect \logical_op__invert_out$13 \output_logical_op__invert_out$53 + connect \logical_op__is_32bit \output_logical_op__is_32bit + connect \logical_op__is_32bit$16 \output_logical_op__is_32bit$56 + connect \logical_op__is_signed \output_logical_op__is_signed + connect \logical_op__is_signed$17 \output_logical_op__is_signed$57 + connect \logical_op__oe__oe \output_logical_op__oe__oe + connect \logical_op__oe__oe$8 \output_logical_op__oe__oe$48 + connect \logical_op__oe__ok \output_logical_op__oe__ok + connect \logical_op__oe__ok$9 \output_logical_op__oe__ok$49 + connect \logical_op__output_carry \output_logical_op__output_carry + connect \logical_op__output_carry$15 \output_logical_op__output_carry$55 + connect \logical_op__rc__ok \output_logical_op__rc__ok + connect \logical_op__rc__ok$7 \output_logical_op__rc__ok$47 + connect \logical_op__rc__rc \output_logical_op__rc__rc + connect \logical_op__rc__rc$6 \output_logical_op__rc__rc$46 + connect \logical_op__write_cr0 \output_logical_op__write_cr0 + connect \logical_op__write_cr0$14 \output_logical_op__write_cr0$54 + connect \logical_op__zero_a \output_logical_op__zero_a + connect \logical_op__zero_a$11 \output_logical_op__zero_a$51 + connect \muxid \output_muxid + connect \muxid$1 \output_muxid$41 + connect \o \output_o + connect \o$20 \output_o$60 + connect \o_ok \output_o_ok + connect \o_ok$21 \output_o_ok$61 + connect \xer_ov \output_xer_ov + connect \xer_ov$23 \output_xer_ov$63 + connect \xer_ov_ok \output_xer_ov_ok + connect \xer_so \output_xer_so + connect \xer_so$24 \output_xer_so$64 + connect \xer_so_ok \output_xer_so_ok + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:157608.16-157660.4" + cell \output_stage \output_stage + connect \div_by_zero \output_stage_div_by_zero + connect \dive_abs_ov32 \output_stage_dive_abs_ov32 + connect \dive_abs_ov64 \output_stage_dive_abs_ov64 + connect \dividend_neg \output_stage_dividend_neg + connect \divisor_neg \output_stage_divisor_neg + connect \logical_op__data_len \output_stage_logical_op__data_len + connect \logical_op__data_len$18 \output_stage_logical_op__data_len$38 + connect \logical_op__fn_unit \output_stage_logical_op__fn_unit + connect \logical_op__fn_unit$3 \output_stage_logical_op__fn_unit$23 + connect \logical_op__imm_data__data \output_stage_logical_op__imm_data__data + connect \logical_op__imm_data__data$4 \output_stage_logical_op__imm_data__data$24 + connect \logical_op__imm_data__ok \output_stage_logical_op__imm_data__ok + connect \logical_op__imm_data__ok$5 \output_stage_logical_op__imm_data__ok$25 + connect \logical_op__input_carry \output_stage_logical_op__input_carry + connect \logical_op__input_carry$12 \output_stage_logical_op__input_carry$32 + connect \logical_op__insn \output_stage_logical_op__insn + connect \logical_op__insn$19 \output_stage_logical_op__insn$39 + connect \logical_op__insn_type \output_stage_logical_op__insn_type + connect \logical_op__insn_type$2 \output_stage_logical_op__insn_type$22 + connect \logical_op__invert_in \output_stage_logical_op__invert_in + connect \logical_op__invert_in$10 \output_stage_logical_op__invert_in$30 + connect \logical_op__invert_out \output_stage_logical_op__invert_out + connect \logical_op__invert_out$13 \output_stage_logical_op__invert_out$33 + connect \logical_op__is_32bit \output_stage_logical_op__is_32bit + connect \logical_op__is_32bit$16 \output_stage_logical_op__is_32bit$36 + connect \logical_op__is_signed \output_stage_logical_op__is_signed + connect \logical_op__is_signed$17 \output_stage_logical_op__is_signed$37 + connect \logical_op__oe__oe \output_stage_logical_op__oe__oe + connect \logical_op__oe__oe$8 \output_stage_logical_op__oe__oe$28 + connect \logical_op__oe__ok \output_stage_logical_op__oe__ok + connect \logical_op__oe__ok$9 \output_stage_logical_op__oe__ok$29 + connect \logical_op__output_carry \output_stage_logical_op__output_carry + connect \logical_op__output_carry$15 \output_stage_logical_op__output_carry$35 + connect \logical_op__rc__ok \output_stage_logical_op__rc__ok + connect \logical_op__rc__ok$7 \output_stage_logical_op__rc__ok$27 + connect \logical_op__rc__rc \output_stage_logical_op__rc__rc + connect \logical_op__rc__rc$6 \output_stage_logical_op__rc__rc$26 + connect \logical_op__write_cr0 \output_stage_logical_op__write_cr0 + connect \logical_op__write_cr0$14 \output_stage_logical_op__write_cr0$34 + connect \logical_op__zero_a \output_stage_logical_op__zero_a + connect \logical_op__zero_a$11 \output_stage_logical_op__zero_a$31 + connect \muxid \output_stage_muxid + connect \muxid$1 \output_stage_muxid$21 + connect \o \output_stage_o + connect \o_ok \output_stage_o_ok + connect \quotient_root \output_stage_quotient_root + connect \remainder \output_stage_remainder + connect \xer_ov \output_stage_xer_ov + connect \xer_ov_ok \output_stage_xer_ov_ok + connect \xer_so \output_stage_xer_so + connect \xer_so$20 \output_stage_xer_so$40 + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:157661.10-157664.4" + cell \p$78 \p + connect \p_ready_o \p_ready_o + connect \p_valid_i \p_valid_i + end + attribute \src "libresoc.v:156365.7-156365.20" + process $proc$libresoc.v:156365$9234 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:156374.13-156374.24" + process $proc$libresoc.v:156374$9235 + assign { } { } + assign $1\cr_a[3:0] 4'0000 + sync always + sync init + update \cr_a $1\cr_a[3:0] + end + attribute \src "libresoc.v:156383.7-156383.21" + process $proc$libresoc.v:156383$9236 + assign { } { } + assign $1\cr_a_ok[0:0] 1'0 + sync always + sync init + update \cr_a_ok $1\cr_a_ok[0:0] + end + attribute \src "libresoc.v:156406.13-156406.45" + process $proc$libresoc.v:156406$9237 + assign { } { } + assign $0\logical_op__data_len$18[3:0]$9238 4'0000 + sync always + sync init + update \logical_op__data_len$18 $0\logical_op__data_len$18[3:0]$9238 + end + attribute \src "libresoc.v:156441.14-156441.47" + process $proc$libresoc.v:156441$9239 + assign { } { } + assign $0\logical_op__fn_unit$3[11:0]$9240 12'000000000000 + sync always + sync init + update \logical_op__fn_unit$3 $0\logical_op__fn_unit$3[11:0]$9240 + end + attribute \src "libresoc.v:156463.14-156463.67" + process $proc$libresoc.v:156463$9241 + assign { } { } + assign $0\logical_op__imm_data__data$4[63:0]$9242 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \logical_op__imm_data__data$4 $0\logical_op__imm_data__data$4[63:0]$9242 + end + attribute \src "libresoc.v:156472.7-156472.42" + process $proc$libresoc.v:156472$9243 + assign { } { } + assign $0\logical_op__imm_data__ok$5[0:0]$9244 1'0 + sync always + sync init + update \logical_op__imm_data__ok$5 $0\logical_op__imm_data__ok$5[0:0]$9244 + end + attribute \src "libresoc.v:156489.13-156489.48" + process $proc$libresoc.v:156489$9245 + assign { } { } + assign $0\logical_op__input_carry$12[1:0]$9246 2'00 + sync always + sync init + update \logical_op__input_carry$12 $0\logical_op__input_carry$12[1:0]$9246 + end + attribute \src "libresoc.v:156502.14-156502.43" + process $proc$libresoc.v:156502$9247 + assign { } { } + assign $0\logical_op__insn$19[31:0]$9248 0 + sync always + sync init + update \logical_op__insn$19 $0\logical_op__insn$19[31:0]$9248 + end + attribute \src "libresoc.v:156659.13-156659.46" + process $proc$libresoc.v:156659$9249 + assign { } { } + assign $0\logical_op__insn_type$2[6:0]$9250 7'0000000 + sync always + sync init + update \logical_op__insn_type$2 $0\logical_op__insn_type$2[6:0]$9250 + end + attribute \src "libresoc.v:156742.7-156742.40" + process $proc$libresoc.v:156742$9251 + assign { } { } + assign $0\logical_op__invert_in$10[0:0]$9252 1'0 + sync always + sync init + update \logical_op__invert_in$10 $0\logical_op__invert_in$10[0:0]$9252 + end + attribute \src "libresoc.v:156751.7-156751.41" + process $proc$libresoc.v:156751$9253 + assign { } { } + assign $0\logical_op__invert_out$13[0:0]$9254 1'0 + sync always + sync init + update \logical_op__invert_out$13 $0\logical_op__invert_out$13[0:0]$9254 + end + attribute \src "libresoc.v:156760.7-156760.39" + process $proc$libresoc.v:156760$9255 + assign { } { } + assign $0\logical_op__is_32bit$16[0:0]$9256 1'0 + sync always + sync init + update \logical_op__is_32bit$16 $0\logical_op__is_32bit$16[0:0]$9256 + end + attribute \src "libresoc.v:156769.7-156769.40" + process $proc$libresoc.v:156769$9257 + assign { } { } + assign $0\logical_op__is_signed$17[0:0]$9258 1'0 + sync always + sync init + update \logical_op__is_signed$17 $0\logical_op__is_signed$17[0:0]$9258 + end + attribute \src "libresoc.v:156778.7-156778.36" + process $proc$libresoc.v:156778$9259 + assign { } { } + assign $0\logical_op__oe__oe$8[0:0]$9260 1'0 + sync always + sync init + update \logical_op__oe__oe$8 $0\logical_op__oe__oe$8[0:0]$9260 + end + attribute \src "libresoc.v:156789.7-156789.36" + process $proc$libresoc.v:156789$9261 + assign { } { } + assign $0\logical_op__oe__ok$9[0:0]$9262 1'0 + sync always + sync init + update \logical_op__oe__ok$9 $0\logical_op__oe__ok$9[0:0]$9262 + end + attribute \src "libresoc.v:156796.7-156796.43" + process $proc$libresoc.v:156796$9263 + assign { } { } + assign $0\logical_op__output_carry$15[0:0]$9264 1'0 + sync always + sync init + update \logical_op__output_carry$15 $0\logical_op__output_carry$15[0:0]$9264 + end + attribute \src "libresoc.v:156805.7-156805.36" + process $proc$libresoc.v:156805$9265 + assign { } { } + assign $0\logical_op__rc__ok$7[0:0]$9266 1'0 + sync always + sync init + update \logical_op__rc__ok$7 $0\logical_op__rc__ok$7[0:0]$9266 + end + attribute \src "libresoc.v:156814.7-156814.36" + process $proc$libresoc.v:156814$9267 + assign { } { } + assign $0\logical_op__rc__rc$6[0:0]$9268 1'0 + sync always + sync init + update \logical_op__rc__rc$6 $0\logical_op__rc__rc$6[0:0]$9268 + end + attribute \src "libresoc.v:156823.7-156823.40" + process $proc$libresoc.v:156823$9269 + assign { } { } + assign $0\logical_op__write_cr0$14[0:0]$9270 1'0 + sync always + sync init + update \logical_op__write_cr0$14 $0\logical_op__write_cr0$14[0:0]$9270 + end + attribute \src "libresoc.v:156832.7-156832.37" + process $proc$libresoc.v:156832$9271 + assign { } { } + assign $0\logical_op__zero_a$11[0:0]$9272 1'0 + sync always + sync init + update \logical_op__zero_a$11 $0\logical_op__zero_a$11[0:0]$9272 + end + attribute \src "libresoc.v:156841.13-156841.29" + process $proc$libresoc.v:156841$9273 + assign { } { } + assign $0\muxid$1[1:0]$9274 2'00 + sync always + sync init + update \muxid$1 $0\muxid$1[1:0]$9274 + end + attribute \src "libresoc.v:156854.14-156854.38" + process $proc$libresoc.v:156854$9275 + assign { } { } + assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \o $1\o[63:0] + end + attribute \src "libresoc.v:156861.7-156861.18" + process $proc$libresoc.v:156861$9276 + assign { } { } + assign $1\o_ok[0:0] 1'0 + sync always + sync init + update \o_ok $1\o_ok[0:0] + end + attribute \src "libresoc.v:157445.7-157445.20" + process $proc$libresoc.v:157445$9277 + assign { } { } + assign $1\r_busy[0:0] 1'0 + sync always + sync init + update \r_busy $1\r_busy[0:0] + end + attribute \src "libresoc.v:157460.13-157460.26" + process $proc$libresoc.v:157460$9278 + assign { } { } + assign $1\xer_ov[1:0] 2'00 + sync always + sync init + update \xer_ov $1\xer_ov[1:0] + end + attribute \src "libresoc.v:157467.7-157467.23" + process $proc$libresoc.v:157467$9279 + assign { } { } + assign $1\xer_ov_ok[0:0] 1'0 + sync always + sync init + update \xer_ov_ok $1\xer_ov_ok[0:0] + end + attribute \src "libresoc.v:157480.7-157480.25" + process $proc$libresoc.v:157480$9280 + assign { } { } + assign $0\xer_so$20[0:0]$9281 1'0 + sync always + sync init + update \xer_so$20 $0\xer_so$20[0:0]$9281 + end + attribute \src "libresoc.v:157485.7-157485.23" + process $proc$libresoc.v:157485$9282 + assign { } { } + assign $1\xer_so_ok[0:0] 1'0 + sync always + sync init + update \xer_so_ok $1\xer_so_ok[0:0] + end + attribute \src "libresoc.v:157495.3-157496.37" + process $proc$libresoc.v:157495$9112 + assign { } { } + assign $0\xer_so$20[0:0]$9113 \xer_so$20$next + sync posedge \coresync_clk + update \xer_so$20 $0\xer_so$20[0:0]$9113 + end + attribute \src "libresoc.v:157497.3-157498.35" + process $proc$libresoc.v:157497$9114 + assign { } { } + assign $0\xer_so_ok[0:0] \xer_so_ok$next + sync posedge \coresync_clk + update \xer_so_ok $0\xer_so_ok[0:0] + end + attribute \src "libresoc.v:157499.3-157500.29" + process $proc$libresoc.v:157499$9115 + assign { } { } + assign $0\xer_ov[1:0] \xer_ov$next + sync posedge \coresync_clk + update \xer_ov $0\xer_ov[1:0] + end + attribute \src "libresoc.v:157501.3-157502.35" + process $proc$libresoc.v:157501$9116 + assign { } { } + assign $0\xer_ov_ok[0:0] \xer_ov_ok$next + sync posedge \coresync_clk + update \xer_ov_ok $0\xer_ov_ok[0:0] + end + attribute \src "libresoc.v:157503.3-157504.25" + process $proc$libresoc.v:157503$9117 + assign { } { } + assign $0\cr_a[3:0] \cr_a$next + sync posedge \coresync_clk + update \cr_a $0\cr_a[3:0] + end + attribute \src "libresoc.v:157505.3-157506.31" + process $proc$libresoc.v:157505$9118 + assign { } { } + assign $0\cr_a_ok[0:0] \cr_a_ok$next + sync posedge \coresync_clk + update \cr_a_ok $0\cr_a_ok[0:0] + end + attribute \src "libresoc.v:157507.3-157508.19" + process $proc$libresoc.v:157507$9119 + assign { } { } + assign $0\o[63:0] \o$next + sync posedge \coresync_clk + update \o $0\o[63:0] + end + attribute \src "libresoc.v:157509.3-157510.25" + process $proc$libresoc.v:157509$9120 + assign { } { } + assign $0\o_ok[0:0] \o_ok$next + sync posedge \coresync_clk + update \o_ok $0\o_ok[0:0] + end + attribute \src "libresoc.v:157511.3-157512.65" + process $proc$libresoc.v:157511$9121 + assign { } { } + assign $0\logical_op__insn_type$2[6:0]$9122 \logical_op__insn_type$2$next + sync posedge \coresync_clk + update \logical_op__insn_type$2 $0\logical_op__insn_type$2[6:0]$9122 + end + attribute \src "libresoc.v:157513.3-157514.61" + process $proc$libresoc.v:157513$9123 + assign { } { } + assign $0\logical_op__fn_unit$3[11:0]$9124 \logical_op__fn_unit$3$next + sync posedge \coresync_clk + update \logical_op__fn_unit$3 $0\logical_op__fn_unit$3[11:0]$9124 + end + attribute \src "libresoc.v:157515.3-157516.75" + process $proc$libresoc.v:157515$9125 + assign { } { } + assign $0\logical_op__imm_data__data$4[63:0]$9126 \logical_op__imm_data__data$4$next + sync posedge \coresync_clk + update \logical_op__imm_data__data$4 $0\logical_op__imm_data__data$4[63:0]$9126 + end + attribute \src "libresoc.v:157517.3-157518.71" + process $proc$libresoc.v:157517$9127 + assign { } { } + assign $0\logical_op__imm_data__ok$5[0:0]$9128 \logical_op__imm_data__ok$5$next + sync posedge \coresync_clk + update \logical_op__imm_data__ok$5 $0\logical_op__imm_data__ok$5[0:0]$9128 + end + attribute \src "libresoc.v:157519.3-157520.59" + process $proc$libresoc.v:157519$9129 + assign { } { } + assign $0\logical_op__rc__rc$6[0:0]$9130 \logical_op__rc__rc$6$next + sync posedge \coresync_clk + update \logical_op__rc__rc$6 $0\logical_op__rc__rc$6[0:0]$9130 + end + attribute \src "libresoc.v:157521.3-157522.59" + process $proc$libresoc.v:157521$9131 + assign { } { } + assign $0\logical_op__rc__ok$7[0:0]$9132 \logical_op__rc__ok$7$next + sync posedge \coresync_clk + update \logical_op__rc__ok$7 $0\logical_op__rc__ok$7[0:0]$9132 + end + attribute \src "libresoc.v:157523.3-157524.59" + process $proc$libresoc.v:157523$9133 + assign { } { } + assign $0\logical_op__oe__oe$8[0:0]$9134 \logical_op__oe__oe$8$next + sync posedge \coresync_clk + update \logical_op__oe__oe$8 $0\logical_op__oe__oe$8[0:0]$9134 + end + attribute \src "libresoc.v:157525.3-157526.59" + process $proc$libresoc.v:157525$9135 + assign { } { } + assign $0\logical_op__oe__ok$9[0:0]$9136 \logical_op__oe__ok$9$next + sync posedge \coresync_clk + update \logical_op__oe__ok$9 $0\logical_op__oe__ok$9[0:0]$9136 + end + attribute \src "libresoc.v:157527.3-157528.67" + process $proc$libresoc.v:157527$9137 + assign { } { } + assign $0\logical_op__invert_in$10[0:0]$9138 \logical_op__invert_in$10$next + sync posedge \coresync_clk + update \logical_op__invert_in$10 $0\logical_op__invert_in$10[0:0]$9138 + end + attribute \src "libresoc.v:157529.3-157530.61" + process $proc$libresoc.v:157529$9139 + assign { } { } + assign $0\logical_op__zero_a$11[0:0]$9140 \logical_op__zero_a$11$next + sync posedge \coresync_clk + update \logical_op__zero_a$11 $0\logical_op__zero_a$11[0:0]$9140 + end + attribute \src "libresoc.v:157531.3-157532.71" + process $proc$libresoc.v:157531$9141 + assign { } { } + assign $0\logical_op__input_carry$12[1:0]$9142 \logical_op__input_carry$12$next + sync posedge \coresync_clk + update \logical_op__input_carry$12 $0\logical_op__input_carry$12[1:0]$9142 + end + attribute \src "libresoc.v:157533.3-157534.69" + process $proc$libresoc.v:157533$9143 + assign { } { } + assign $0\logical_op__invert_out$13[0:0]$9144 \logical_op__invert_out$13$next + sync posedge \coresync_clk + update \logical_op__invert_out$13 $0\logical_op__invert_out$13[0:0]$9144 + end + attribute \src "libresoc.v:157535.3-157536.67" + process $proc$libresoc.v:157535$9145 + assign { } { } + assign $0\logical_op__write_cr0$14[0:0]$9146 \logical_op__write_cr0$14$next + sync posedge \coresync_clk + update \logical_op__write_cr0$14 $0\logical_op__write_cr0$14[0:0]$9146 + end + attribute \src "libresoc.v:157537.3-157538.73" + process $proc$libresoc.v:157537$9147 + assign { } { } + assign $0\logical_op__output_carry$15[0:0]$9148 \logical_op__output_carry$15$next + sync posedge \coresync_clk + update \logical_op__output_carry$15 $0\logical_op__output_carry$15[0:0]$9148 + end + attribute \src "libresoc.v:157539.3-157540.65" + process $proc$libresoc.v:157539$9149 + assign { } { } + assign $0\logical_op__is_32bit$16[0:0]$9150 \logical_op__is_32bit$16$next + sync posedge \coresync_clk + update \logical_op__is_32bit$16 $0\logical_op__is_32bit$16[0:0]$9150 + end + attribute \src "libresoc.v:157541.3-157542.67" + process $proc$libresoc.v:157541$9151 + assign { } { } + assign $0\logical_op__is_signed$17[0:0]$9152 \logical_op__is_signed$17$next + sync posedge \coresync_clk + update \logical_op__is_signed$17 $0\logical_op__is_signed$17[0:0]$9152 + end + attribute \src "libresoc.v:157543.3-157544.65" + process $proc$libresoc.v:157543$9153 + assign { } { } + assign $0\logical_op__data_len$18[3:0]$9154 \logical_op__data_len$18$next + sync posedge \coresync_clk + update \logical_op__data_len$18 $0\logical_op__data_len$18[3:0]$9154 + end + attribute \src "libresoc.v:157545.3-157546.57" + process $proc$libresoc.v:157545$9155 + assign { } { } + assign $0\logical_op__insn$19[31:0]$9156 \logical_op__insn$19$next + sync posedge \coresync_clk + update \logical_op__insn$19 $0\logical_op__insn$19[31:0]$9156 + end + attribute \src "libresoc.v:157547.3-157548.33" + process $proc$libresoc.v:157547$9157 + assign { } { } + assign $0\muxid$1[1:0]$9158 \muxid$1$next + sync posedge \coresync_clk + update \muxid$1 $0\muxid$1[1:0]$9158 + end + attribute \src "libresoc.v:157549.3-157550.29" + process $proc$libresoc.v:157549$9159 + assign { } { } + assign $0\r_busy[0:0] \r_busy$next + sync posedge \coresync_clk + update \r_busy $0\r_busy[0:0] + end + attribute \src "libresoc.v:157665.3-157683.6" + process $proc$libresoc.v:157665$9160 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\o$next[63:0]$9161 $1\o$next[63:0]$9163 + assign { } { } + assign $0\o_ok$next[0:0]$9162 $2\o_ok$next[0:0]$9165 + attribute \src "libresoc.v:157666.5-157666.29" + switch \initial + attribute \src "libresoc.v:157666.9-157666.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\o_ok$next[0:0]$9164 $1\o$next[63:0]$9163 } { \o_ok$96 \o$95 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\o_ok$next[0:0]$9164 $1\o$next[63:0]$9163 } { \o_ok$96 \o$95 } + case + assign $1\o$next[63:0]$9163 \o + assign $1\o_ok$next[0:0]$9164 \o_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\o_ok$next[0:0]$9165 1'0 + case + assign $2\o_ok$next[0:0]$9165 $1\o_ok$next[0:0]$9164 + end + sync always + update \o$next $0\o$next[63:0]$9161 + update \o_ok$next $0\o_ok$next[0:0]$9162 + end + attribute \src "libresoc.v:157684.3-157702.6" + process $proc$libresoc.v:157684$9166 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\cr_a$next[3:0]$9167 $1\cr_a$next[3:0]$9169 + assign { } { } + assign $0\cr_a_ok$next[0:0]$9168 $2\cr_a_ok$next[0:0]$9171 + attribute \src "libresoc.v:157685.5-157685.29" + switch \initial + attribute \src "libresoc.v:157685.9-157685.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\cr_a_ok$next[0:0]$9170 $1\cr_a$next[3:0]$9169 } { \cr_a_ok$98 \cr_a$97 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\cr_a_ok$next[0:0]$9170 $1\cr_a$next[3:0]$9169 } { \cr_a_ok$98 \cr_a$97 } + case + assign $1\cr_a$next[3:0]$9169 \cr_a + assign $1\cr_a_ok$next[0:0]$9170 \cr_a_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_a_ok$next[0:0]$9171 1'0 + case + assign $2\cr_a_ok$next[0:0]$9171 $1\cr_a_ok$next[0:0]$9170 + end + sync always + update \cr_a$next $0\cr_a$next[3:0]$9167 + update \cr_a_ok$next $0\cr_a_ok$next[0:0]$9168 + end + attribute \src "libresoc.v:157703.3-157721.6" + process $proc$libresoc.v:157703$9172 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\xer_ov$next[1:0]$9173 $1\xer_ov$next[1:0]$9175 + assign { } { } + assign $0\xer_ov_ok$next[0:0]$9174 $2\xer_ov_ok$next[0:0]$9177 + attribute \src "libresoc.v:157704.5-157704.29" + switch \initial + attribute \src "libresoc.v:157704.9-157704.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\xer_ov_ok$next[0:0]$9176 $1\xer_ov$next[1:0]$9175 } { \xer_ov_ok$100 \xer_ov$99 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\xer_ov_ok$next[0:0]$9176 $1\xer_ov$next[1:0]$9175 } { \xer_ov_ok$100 \xer_ov$99 } + case + assign $1\xer_ov$next[1:0]$9175 \xer_ov + assign $1\xer_ov_ok$next[0:0]$9176 \xer_ov_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\xer_ov_ok$next[0:0]$9177 1'0 + case + assign $2\xer_ov_ok$next[0:0]$9177 $1\xer_ov_ok$next[0:0]$9176 + end + sync always + update \xer_ov$next $0\xer_ov$next[1:0]$9173 + update \xer_ov_ok$next $0\xer_ov_ok$next[0:0]$9174 + end + attribute \src "libresoc.v:157722.3-157740.6" + process $proc$libresoc.v:157722$9178 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\xer_so$20$next[0:0]$9180 $1\xer_so$20$next[0:0]$9182 + assign $0\xer_so_ok$next[0:0]$9179 $2\xer_so_ok$next[0:0]$9183 + attribute \src "libresoc.v:157723.5-157723.29" + switch \initial + attribute \src "libresoc.v:157723.9-157723.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\xer_so_ok$next[0:0]$9181 $1\xer_so$20$next[0:0]$9182 } { \xer_so_ok$102 \xer_so$101 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\xer_so_ok$next[0:0]$9181 $1\xer_so$20$next[0:0]$9182 } { \xer_so_ok$102 \xer_so$101 } + case + assign $1\xer_so_ok$next[0:0]$9181 \xer_so_ok + assign $1\xer_so$20$next[0:0]$9182 \xer_so$20 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\xer_so_ok$next[0:0]$9183 1'0 + case + assign $2\xer_so_ok$next[0:0]$9183 $1\xer_so_ok$next[0:0]$9181 + end + sync always + update \xer_so_ok$next $0\xer_so_ok$next[0:0]$9179 + update \xer_so$20$next $0\xer_so$20$next[0:0]$9180 + end + attribute \src "libresoc.v:157741.3-157758.6" + process $proc$libresoc.v:157741$9184 + assign { } { } + assign { } { } + assign { } { } + assign $0\r_busy$next[0:0]$9185 $2\r_busy$next[0:0]$9187 + attribute \src "libresoc.v:157742.5-157742.29" + switch \initial + attribute \src "libresoc.v:157742.9-157742.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\r_busy$next[0:0]$9186 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\r_busy$next[0:0]$9186 1'0 + case + assign $1\r_busy$next[0:0]$9186 \r_busy + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r_busy$next[0:0]$9187 1'0 + case + assign $2\r_busy$next[0:0]$9187 $1\r_busy$next[0:0]$9186 + end + sync always + update \r_busy$next $0\r_busy$next[0:0]$9185 + end + attribute \src "libresoc.v:157759.3-157771.6" + process $proc$libresoc.v:157759$9188 + assign { } { } + assign { } { } + assign $0\muxid$1$next[1:0]$9189 $1\muxid$1$next[1:0]$9190 + attribute \src "libresoc.v:157760.5-157760.29" + switch \initial + attribute \src "libresoc.v:157760.9-157760.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\muxid$1$next[1:0]$9190 \muxid$76 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\muxid$1$next[1:0]$9190 \muxid$76 + case + assign $1\muxid$1$next[1:0]$9190 \muxid$1 + end + sync always + update \muxid$1$next $0\muxid$1$next[1:0]$9189 + end + attribute \src "libresoc.v:157772.3-157813.6" + process $proc$libresoc.v:157772$9191 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\logical_op__data_len$18$next[3:0]$9192 $1\logical_op__data_len$18$next[3:0]$9210 + assign $0\logical_op__fn_unit$3$next[11:0]$9193 $1\logical_op__fn_unit$3$next[11:0]$9211 + assign { } { } + assign { } { } + assign $0\logical_op__input_carry$12$next[1:0]$9196 $1\logical_op__input_carry$12$next[1:0]$9214 + assign $0\logical_op__insn$19$next[31:0]$9197 $1\logical_op__insn$19$next[31:0]$9215 + assign $0\logical_op__insn_type$2$next[6:0]$9198 $1\logical_op__insn_type$2$next[6:0]$9216 + assign $0\logical_op__invert_in$10$next[0:0]$9199 $1\logical_op__invert_in$10$next[0:0]$9217 + assign $0\logical_op__invert_out$13$next[0:0]$9200 $1\logical_op__invert_out$13$next[0:0]$9218 + assign $0\logical_op__is_32bit$16$next[0:0]$9201 $1\logical_op__is_32bit$16$next[0:0]$9219 + assign $0\logical_op__is_signed$17$next[0:0]$9202 $1\logical_op__is_signed$17$next[0:0]$9220 + assign { } { } + assign { } { } + assign $0\logical_op__output_carry$15$next[0:0]$9205 $1\logical_op__output_carry$15$next[0:0]$9223 + assign { } { } + assign { } { } + assign $0\logical_op__write_cr0$14$next[0:0]$9208 $1\logical_op__write_cr0$14$next[0:0]$9226 + assign $0\logical_op__zero_a$11$next[0:0]$9209 $1\logical_op__zero_a$11$next[0:0]$9227 + assign $0\logical_op__imm_data__data$4$next[63:0]$9194 $2\logical_op__imm_data__data$4$next[63:0]$9228 + assign $0\logical_op__imm_data__ok$5$next[0:0]$9195 $2\logical_op__imm_data__ok$5$next[0:0]$9229 + assign $0\logical_op__oe__oe$8$next[0:0]$9203 $2\logical_op__oe__oe$8$next[0:0]$9230 + assign $0\logical_op__oe__ok$9$next[0:0]$9204 $2\logical_op__oe__ok$9$next[0:0]$9231 + assign $0\logical_op__rc__ok$7$next[0:0]$9206 $2\logical_op__rc__ok$7$next[0:0]$9232 + assign $0\logical_op__rc__rc$6$next[0:0]$9207 $2\logical_op__rc__rc$6$next[0:0]$9233 + attribute \src "libresoc.v:157773.5-157773.29" + switch \initial + attribute \src "libresoc.v:157773.9-157773.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\logical_op__insn$19$next[31:0]$9215 $1\logical_op__data_len$18$next[3:0]$9210 $1\logical_op__is_signed$17$next[0:0]$9220 $1\logical_op__is_32bit$16$next[0:0]$9219 $1\logical_op__output_carry$15$next[0:0]$9223 $1\logical_op__write_cr0$14$next[0:0]$9226 $1\logical_op__invert_out$13$next[0:0]$9218 $1\logical_op__input_carry$12$next[1:0]$9214 $1\logical_op__zero_a$11$next[0:0]$9227 $1\logical_op__invert_in$10$next[0:0]$9217 $1\logical_op__oe__ok$9$next[0:0]$9222 $1\logical_op__oe__oe$8$next[0:0]$9221 $1\logical_op__rc__ok$7$next[0:0]$9224 $1\logical_op__rc__rc$6$next[0:0]$9225 $1\logical_op__imm_data__ok$5$next[0:0]$9213 $1\logical_op__imm_data__data$4$next[63:0]$9212 $1\logical_op__fn_unit$3$next[11:0]$9211 $1\logical_op__insn_type$2$next[6:0]$9216 } { \logical_op__insn$94 \logical_op__data_len$93 \logical_op__is_signed$92 \logical_op__is_32bit$91 \logical_op__output_carry$90 \logical_op__write_cr0$89 \logical_op__invert_out$88 \logical_op__input_carry$87 \logical_op__zero_a$86 \logical_op__invert_in$85 \logical_op__oe__ok$84 \logical_op__oe__oe$83 \logical_op__rc__ok$82 \logical_op__rc__rc$81 \logical_op__imm_data__ok$80 \logical_op__imm_data__data$79 \logical_op__fn_unit$78 \logical_op__insn_type$77 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\logical_op__insn$19$next[31:0]$9215 $1\logical_op__data_len$18$next[3:0]$9210 $1\logical_op__is_signed$17$next[0:0]$9220 $1\logical_op__is_32bit$16$next[0:0]$9219 $1\logical_op__output_carry$15$next[0:0]$9223 $1\logical_op__write_cr0$14$next[0:0]$9226 $1\logical_op__invert_out$13$next[0:0]$9218 $1\logical_op__input_carry$12$next[1:0]$9214 $1\logical_op__zero_a$11$next[0:0]$9227 $1\logical_op__invert_in$10$next[0:0]$9217 $1\logical_op__oe__ok$9$next[0:0]$9222 $1\logical_op__oe__oe$8$next[0:0]$9221 $1\logical_op__rc__ok$7$next[0:0]$9224 $1\logical_op__rc__rc$6$next[0:0]$9225 $1\logical_op__imm_data__ok$5$next[0:0]$9213 $1\logical_op__imm_data__data$4$next[63:0]$9212 $1\logical_op__fn_unit$3$next[11:0]$9211 $1\logical_op__insn_type$2$next[6:0]$9216 } { \logical_op__insn$94 \logical_op__data_len$93 \logical_op__is_signed$92 \logical_op__is_32bit$91 \logical_op__output_carry$90 \logical_op__write_cr0$89 \logical_op__invert_out$88 \logical_op__input_carry$87 \logical_op__zero_a$86 \logical_op__invert_in$85 \logical_op__oe__ok$84 \logical_op__oe__oe$83 \logical_op__rc__ok$82 \logical_op__rc__rc$81 \logical_op__imm_data__ok$80 \logical_op__imm_data__data$79 \logical_op__fn_unit$78 \logical_op__insn_type$77 } + case + assign $1\logical_op__data_len$18$next[3:0]$9210 \logical_op__data_len$18 + assign $1\logical_op__fn_unit$3$next[11:0]$9211 \logical_op__fn_unit$3 + assign $1\logical_op__imm_data__data$4$next[63:0]$9212 \logical_op__imm_data__data$4 + assign $1\logical_op__imm_data__ok$5$next[0:0]$9213 \logical_op__imm_data__ok$5 + assign $1\logical_op__input_carry$12$next[1:0]$9214 \logical_op__input_carry$12 + assign $1\logical_op__insn$19$next[31:0]$9215 \logical_op__insn$19 + assign $1\logical_op__insn_type$2$next[6:0]$9216 \logical_op__insn_type$2 + assign $1\logical_op__invert_in$10$next[0:0]$9217 \logical_op__invert_in$10 + assign $1\logical_op__invert_out$13$next[0:0]$9218 \logical_op__invert_out$13 + assign $1\logical_op__is_32bit$16$next[0:0]$9219 \logical_op__is_32bit$16 + assign $1\logical_op__is_signed$17$next[0:0]$9220 \logical_op__is_signed$17 + assign $1\logical_op__oe__oe$8$next[0:0]$9221 \logical_op__oe__oe$8 + assign $1\logical_op__oe__ok$9$next[0:0]$9222 \logical_op__oe__ok$9 + assign $1\logical_op__output_carry$15$next[0:0]$9223 \logical_op__output_carry$15 + assign $1\logical_op__rc__ok$7$next[0:0]$9224 \logical_op__rc__ok$7 + assign $1\logical_op__rc__rc$6$next[0:0]$9225 \logical_op__rc__rc$6 + assign $1\logical_op__write_cr0$14$next[0:0]$9226 \logical_op__write_cr0$14 + assign $1\logical_op__zero_a$11$next[0:0]$9227 \logical_op__zero_a$11 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $2\logical_op__imm_data__data$4$next[63:0]$9228 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\logical_op__imm_data__ok$5$next[0:0]$9229 1'0 + assign $2\logical_op__rc__rc$6$next[0:0]$9233 1'0 + assign $2\logical_op__rc__ok$7$next[0:0]$9232 1'0 + assign $2\logical_op__oe__oe$8$next[0:0]$9230 1'0 + assign $2\logical_op__oe__ok$9$next[0:0]$9231 1'0 + case + assign $2\logical_op__imm_data__data$4$next[63:0]$9228 $1\logical_op__imm_data__data$4$next[63:0]$9212 + assign $2\logical_op__imm_data__ok$5$next[0:0]$9229 $1\logical_op__imm_data__ok$5$next[0:0]$9213 + assign $2\logical_op__oe__oe$8$next[0:0]$9230 $1\logical_op__oe__oe$8$next[0:0]$9221 + assign $2\logical_op__oe__ok$9$next[0:0]$9231 $1\logical_op__oe__ok$9$next[0:0]$9222 + assign $2\logical_op__rc__ok$7$next[0:0]$9232 $1\logical_op__rc__ok$7$next[0:0]$9224 + assign $2\logical_op__rc__rc$6$next[0:0]$9233 $1\logical_op__rc__rc$6$next[0:0]$9225 + end + sync always + update \logical_op__data_len$18$next $0\logical_op__data_len$18$next[3:0]$9192 + update \logical_op__fn_unit$3$next $0\logical_op__fn_unit$3$next[11:0]$9193 + update \logical_op__imm_data__data$4$next $0\logical_op__imm_data__data$4$next[63:0]$9194 + update \logical_op__imm_data__ok$5$next $0\logical_op__imm_data__ok$5$next[0:0]$9195 + update \logical_op__input_carry$12$next $0\logical_op__input_carry$12$next[1:0]$9196 + update \logical_op__insn$19$next $0\logical_op__insn$19$next[31:0]$9197 + update \logical_op__insn_type$2$next $0\logical_op__insn_type$2$next[6:0]$9198 + update \logical_op__invert_in$10$next $0\logical_op__invert_in$10$next[0:0]$9199 + update \logical_op__invert_out$13$next $0\logical_op__invert_out$13$next[0:0]$9200 + update \logical_op__is_32bit$16$next $0\logical_op__is_32bit$16$next[0:0]$9201 + update \logical_op__is_signed$17$next $0\logical_op__is_signed$17$next[0:0]$9202 + update \logical_op__oe__oe$8$next $0\logical_op__oe__oe$8$next[0:0]$9203 + update \logical_op__oe__ok$9$next $0\logical_op__oe__ok$9$next[0:0]$9204 + update \logical_op__output_carry$15$next $0\logical_op__output_carry$15$next[0:0]$9205 + update \logical_op__rc__ok$7$next $0\logical_op__rc__ok$7$next[0:0]$9206 + update \logical_op__rc__rc$6$next $0\logical_op__rc__rc$6$next[0:0]$9207 + update \logical_op__write_cr0$14$next $0\logical_op__write_cr0$14$next[0:0]$9208 + update \logical_op__zero_a$11$next $0\logical_op__zero_a$11$next[0:0]$9209 + end + connect \$74 $and$libresoc.v:157494$9111_Y + connect \cr_a$68 4'0000 + connect \cr_a_ok$69 1'0 + connect \xer_so_ok$72 1'0 + connect \p_ready_o \n_i_rdy_data + connect \n_valid_o \r_busy + connect { \xer_so_ok$102 \xer_so$101 } { \output_xer_so_ok \output_xer_so$64 } + connect { \xer_ov_ok$100 \xer_ov$99 } { \output_xer_ov_ok \output_xer_ov$63 } + connect { \cr_a_ok$98 \cr_a$97 } { \output_cr_a_ok \output_cr_a$62 } + connect { \o_ok$96 \o$95 } { \output_o_ok$61 \output_o$60 } + connect { \logical_op__insn$94 \logical_op__data_len$93 \logical_op__is_signed$92 \logical_op__is_32bit$91 \logical_op__output_carry$90 \logical_op__write_cr0$89 \logical_op__invert_out$88 \logical_op__input_carry$87 \logical_op__zero_a$86 \logical_op__invert_in$85 \logical_op__oe__ok$84 \logical_op__oe__oe$83 \logical_op__rc__ok$82 \logical_op__rc__rc$81 \logical_op__imm_data__ok$80 \logical_op__imm_data__data$79 \logical_op__fn_unit$78 \logical_op__insn_type$77 } { \output_logical_op__insn$59 \output_logical_op__data_len$58 \output_logical_op__is_signed$57 \output_logical_op__is_32bit$56 \output_logical_op__output_carry$55 \output_logical_op__write_cr0$54 \output_logical_op__invert_out$53 \output_logical_op__input_carry$52 \output_logical_op__zero_a$51 \output_logical_op__invert_in$50 \output_logical_op__oe__ok$49 \output_logical_op__oe__oe$48 \output_logical_op__rc__ok$47 \output_logical_op__rc__rc$46 \output_logical_op__imm_data__ok$45 \output_logical_op__imm_data__data$44 \output_logical_op__fn_unit$43 \output_logical_op__insn_type$42 } + connect \muxid$76 \output_muxid$41 + connect \p_valid_i_p_ready_o \$74 + connect \n_i_rdy_data \n_ready_i + connect \p_valid_i$73 \p_valid_i + connect { \xer_so_ok$71 \output_xer_so } { 1'0 \output_stage_xer_so$40 } + connect { \xer_ov_ok$70 \output_xer_ov } { \output_stage_xer_ov_ok \output_stage_xer_ov } + connect { \cr_a_ok$67 \output_cr_a } 5'00000 + connect { \output_o_ok \output_o } { \output_stage_o_ok \output_stage_o } + connect { \output_logical_op__insn \output_logical_op__data_len \output_logical_op__is_signed \output_logical_op__is_32bit \output_logical_op__output_carry \output_logical_op__write_cr0 \output_logical_op__invert_out \output_logical_op__input_carry \output_logical_op__zero_a \output_logical_op__invert_in \output_logical_op__oe__ok \output_logical_op__oe__oe \output_logical_op__rc__ok \output_logical_op__rc__rc \output_logical_op__imm_data__ok \output_logical_op__imm_data__data \output_logical_op__fn_unit \output_logical_op__insn_type } { \output_stage_logical_op__insn$39 \output_stage_logical_op__data_len$38 \output_stage_logical_op__is_signed$37 \output_stage_logical_op__is_32bit$36 \output_stage_logical_op__output_carry$35 \output_stage_logical_op__write_cr0$34 \output_stage_logical_op__invert_out$33 \output_stage_logical_op__input_carry$32 \output_stage_logical_op__zero_a$31 \output_stage_logical_op__invert_in$30 \output_stage_logical_op__oe__ok$29 \output_stage_logical_op__oe__oe$28 \output_stage_logical_op__rc__ok$27 \output_stage_logical_op__rc__rc$26 \output_stage_logical_op__imm_data__ok$25 \output_stage_logical_op__imm_data__data$24 \output_stage_logical_op__fn_unit$23 \output_stage_logical_op__insn_type$22 } + connect \output_muxid \output_stage_muxid$21 + connect \output_stage_remainder \remainder + connect \output_stage_quotient_root \quotient_root + connect \output_stage_div_by_zero \div_by_zero + connect \output_stage_dive_abs_ov64 \dive_abs_ov64 + connect \output_stage_dive_abs_ov32 \dive_abs_ov32 + connect \output_stage_dividend_neg \dividend_neg + connect \output_stage_divisor_neg \divisor_neg + connect \output_stage_xer_so \xer_so + connect \rb$66 \rb + connect \ra$65 \ra + connect { \output_stage_logical_op__insn \output_stage_logical_op__data_len \output_stage_logical_op__is_signed \output_stage_logical_op__is_32bit \output_stage_logical_op__output_carry \output_stage_logical_op__write_cr0 \output_stage_logical_op__invert_out \output_stage_logical_op__input_carry \output_stage_logical_op__zero_a \output_stage_logical_op__invert_in \output_stage_logical_op__oe__ok \output_stage_logical_op__oe__oe \output_stage_logical_op__rc__ok \output_stage_logical_op__rc__rc \output_stage_logical_op__imm_data__ok \output_stage_logical_op__imm_data__data \output_stage_logical_op__fn_unit \output_stage_logical_op__insn_type } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } + connect \output_stage_muxid \muxid +end +attribute \src "libresoc.v:157850.1-158828.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_0" +attribute \generator "nMigen" +module \pipe_middle_0 + attribute \src "libresoc.v:158753.3-158767.6" + wire $0\div_by_zero$54$next[0:0]$9462 + attribute \src "libresoc.v:158427.3-158428.47" + wire $0\div_by_zero$54[0:0]$9297 + attribute \src "libresoc.v:157873.7-157873.30" + wire $0\div_by_zero$54[0:0]$9479 + attribute \src "libresoc.v:158549.3-158560.6" + wire width 64 $0\div_state_next_divisor[63:0] + attribute \src "libresoc.v:158537.3-158548.6" + wire width 128 $0\div_state_next_i_dividend_quotient[127:0] + attribute \src "libresoc.v:158525.3-158536.6" + wire width 7 $0\div_state_next_i_q_bits_known[6:0] + attribute \src "libresoc.v:158723.3-158737.6" + wire $0\dive_abs_ov32$52$next[0:0]$9454 + attribute \src "libresoc.v:158431.3-158432.51" + wire $0\dive_abs_ov32$52[0:0]$9301 + attribute \src "libresoc.v:157897.7-157897.32" + wire $0\dive_abs_ov32$52[0:0]$9481 + attribute \src "libresoc.v:158738.3-158752.6" + wire $0\dive_abs_ov64$53$next[0:0]$9458 + attribute \src "libresoc.v:158429.3-158430.51" + wire $0\dive_abs_ov64$53[0:0]$9299 + attribute \src "libresoc.v:157905.7-157905.32" + wire $0\dive_abs_ov64$53[0:0]$9483 + attribute \src "libresoc.v:158768.3-158782.6" + wire width 128 $0\dividend$68$next[127:0]$9466 + attribute \src "libresoc.v:158425.3-158426.41" + wire width 128 $0\dividend$68[127:0]$9295 + attribute \src "libresoc.v:157911.15-157911.68" + wire width 128 $0\dividend$68[127:0]$9485 + attribute \src "libresoc.v:158708.3-158722.6" + wire $0\dividend_neg$51$next[0:0]$9450 + attribute \src "libresoc.v:158433.3-158434.49" + wire $0\dividend_neg$51[0:0]$9303 + attribute \src "libresoc.v:157919.7-157919.31" + wire $0\dividend_neg$51[0:0]$9487 + attribute \src "libresoc.v:158693.3-158707.6" + wire $0\divisor_neg$50$next[0:0]$9446 + attribute \src "libresoc.v:158435.3-158436.47" + wire $0\divisor_neg$50[0:0]$9305 + attribute \src "libresoc.v:157927.7-157927.30" + wire $0\divisor_neg$50[0:0]$9489 + attribute \src "libresoc.v:158783.3-158797.6" + wire width 64 $0\divisor_radicand$65$next[63:0]$9470 + attribute \src "libresoc.v:158423.3-158424.57" + wire width 64 $0\divisor_radicand$65[63:0]$9293 + attribute \src "libresoc.v:157933.14-157933.58" + wire width 64 $0\divisor_radicand$65[63:0]$9491 + attribute \src "libresoc.v:158561.3-158588.6" + wire $0\empty$next[0:0]$9363 + attribute \src "libresoc.v:158481.3-158482.27" + wire $0\empty[0:0] + attribute \src "libresoc.v:157851.7-157851.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:158604.3-158647.6" + wire width 4 $0\logical_op__data_len$45$next[3:0]$9373 + attribute \src "libresoc.v:158475.3-158476.65" + wire width 4 $0\logical_op__data_len$45[3:0]$9345 + attribute \src "libresoc.v:157945.13-157945.45" + wire width 4 $0\logical_op__data_len$45[3:0]$9494 + attribute \src "libresoc.v:158604.3-158647.6" + wire width 12 $0\logical_op__fn_unit$30$next[11:0]$9374 + attribute \src "libresoc.v:158445.3-158446.63" + wire width 12 $0\logical_op__fn_unit$30[11:0]$9315 + attribute \src "libresoc.v:157992.14-157992.48" + wire width 12 $0\logical_op__fn_unit$30[11:0]$9496 + attribute \src "libresoc.v:158604.3-158647.6" + wire width 64 $0\logical_op__imm_data__data$31$next[63:0]$9375 + attribute \src "libresoc.v:158447.3-158448.77" + wire width 64 $0\logical_op__imm_data__data$31[63:0]$9317 + attribute \src "libresoc.v:157998.14-157998.68" + wire width 64 $0\logical_op__imm_data__data$31[63:0]$9498 + attribute \src "libresoc.v:158604.3-158647.6" + wire $0\logical_op__imm_data__ok$32$next[0:0]$9376 + attribute \src "libresoc.v:158449.3-158450.73" + wire $0\logical_op__imm_data__ok$32[0:0]$9319 + attribute \src "libresoc.v:158006.7-158006.43" + wire $0\logical_op__imm_data__ok$32[0:0]$9500 + attribute \src "libresoc.v:158604.3-158647.6" + wire width 2 $0\logical_op__input_carry$39$next[1:0]$9377 + attribute \src "libresoc.v:158463.3-158464.71" + wire width 2 $0\logical_op__input_carry$39[1:0]$9333 + attribute \src "libresoc.v:158028.13-158028.48" + wire width 2 $0\logical_op__input_carry$39[1:0]$9502 + attribute \src "libresoc.v:158604.3-158647.6" + wire width 32 $0\logical_op__insn$46$next[31:0]$9378 + attribute \src "libresoc.v:158477.3-158478.57" + wire width 32 $0\logical_op__insn$46[31:0]$9347 + attribute \src "libresoc.v:158036.14-158036.43" + wire width 32 $0\logical_op__insn$46[31:0]$9504 + attribute \src "libresoc.v:158604.3-158647.6" + wire width 7 $0\logical_op__insn_type$29$next[6:0]$9379 + attribute \src "libresoc.v:158443.3-158444.67" + wire width 7 $0\logical_op__insn_type$29[6:0]$9313 + attribute \src "libresoc.v:158266.13-158266.47" + wire width 7 $0\logical_op__insn_type$29[6:0]$9506 + attribute \src "libresoc.v:158604.3-158647.6" + wire $0\logical_op__invert_in$37$next[0:0]$9380 + attribute \src "libresoc.v:158459.3-158460.67" + wire $0\logical_op__invert_in$37[0:0]$9329 + attribute \src "libresoc.v:158274.7-158274.40" + wire $0\logical_op__invert_in$37[0:0]$9508 + attribute \src "libresoc.v:158604.3-158647.6" + wire $0\logical_op__invert_out$40$next[0:0]$9381 + attribute \src "libresoc.v:158465.3-158466.69" + wire $0\logical_op__invert_out$40[0:0]$9335 + attribute \src "libresoc.v:158282.7-158282.41" + wire $0\logical_op__invert_out$40[0:0]$9510 + attribute \src "libresoc.v:158604.3-158647.6" + wire $0\logical_op__is_32bit$43$next[0:0]$9382 + attribute \src "libresoc.v:158471.3-158472.65" + wire $0\logical_op__is_32bit$43[0:0]$9341 + attribute \src "libresoc.v:158290.7-158290.39" + wire $0\logical_op__is_32bit$43[0:0]$9512 + attribute \src "libresoc.v:158604.3-158647.6" + wire $0\logical_op__is_signed$44$next[0:0]$9383 + attribute \src "libresoc.v:158473.3-158474.67" + wire $0\logical_op__is_signed$44[0:0]$9343 + attribute \src "libresoc.v:158298.7-158298.40" + wire $0\logical_op__is_signed$44[0:0]$9514 + attribute \src "libresoc.v:158604.3-158647.6" + wire $0\logical_op__oe__oe$35$next[0:0]$9384 + attribute \src "libresoc.v:158455.3-158456.61" + wire $0\logical_op__oe__oe$35[0:0]$9325 + attribute \src "libresoc.v:158304.7-158304.37" + wire $0\logical_op__oe__oe$35[0:0]$9516 + attribute \src "libresoc.v:158604.3-158647.6" + wire $0\logical_op__oe__ok$36$next[0:0]$9385 + attribute \src "libresoc.v:158457.3-158458.61" + wire $0\logical_op__oe__ok$36[0:0]$9327 + attribute \src "libresoc.v:158312.7-158312.37" + wire $0\logical_op__oe__ok$36[0:0]$9518 + attribute \src "libresoc.v:158604.3-158647.6" + wire $0\logical_op__output_carry$42$next[0:0]$9386 + attribute \src "libresoc.v:158469.3-158470.73" + wire $0\logical_op__output_carry$42[0:0]$9339 + attribute \src "libresoc.v:158322.7-158322.43" + wire $0\logical_op__output_carry$42[0:0]$9520 + attribute \src "libresoc.v:158604.3-158647.6" + wire $0\logical_op__rc__ok$34$next[0:0]$9387 + attribute \src "libresoc.v:158453.3-158454.61" + wire $0\logical_op__rc__ok$34[0:0]$9323 + attribute \src "libresoc.v:158328.7-158328.37" + wire $0\logical_op__rc__ok$34[0:0]$9522 + attribute \src "libresoc.v:158604.3-158647.6" + wire $0\logical_op__rc__rc$33$next[0:0]$9388 + attribute \src "libresoc.v:158451.3-158452.61" + wire $0\logical_op__rc__rc$33[0:0]$9321 + attribute \src "libresoc.v:158336.7-158336.37" + wire $0\logical_op__rc__rc$33[0:0]$9524 + attribute \src "libresoc.v:158604.3-158647.6" + wire $0\logical_op__write_cr0$41$next[0:0]$9389 + attribute \src "libresoc.v:158467.3-158468.67" + wire $0\logical_op__write_cr0$41[0:0]$9337 + attribute \src "libresoc.v:158346.7-158346.40" + wire $0\logical_op__write_cr0$41[0:0]$9526 + attribute \src "libresoc.v:158604.3-158647.6" + wire $0\logical_op__zero_a$38$next[0:0]$9390 + attribute \src "libresoc.v:158461.3-158462.61" + wire $0\logical_op__zero_a$38[0:0]$9331 + attribute \src "libresoc.v:158354.7-158354.37" + wire $0\logical_op__zero_a$38[0:0]$9528 + attribute \src "libresoc.v:158589.3-158603.6" + wire width 2 $0\muxid$28$next[1:0]$9369 + attribute \src "libresoc.v:158479.3-158480.35" + wire width 2 $0\muxid$28[1:0]$9349 + attribute \src "libresoc.v:158362.13-158362.30" + wire width 2 $0\muxid$28[1:0]$9530 + attribute \src "libresoc.v:158798.3-158812.6" + wire width 2 $0\operation$69$next[1:0]$9474 + attribute \src "libresoc.v:158421.3-158422.43" + wire width 2 $0\operation$69[1:0]$9291 + attribute \src "libresoc.v:158372.13-158372.34" + wire width 2 $0\operation$69[1:0]$9532 + attribute \src "libresoc.v:158648.3-158662.6" + wire width 64 $0\ra$47$next[63:0]$9434 + attribute \src "libresoc.v:158441.3-158442.29" + wire width 64 $0\ra$47[63:0]$9311 + attribute \src "libresoc.v:158386.14-158386.44" + wire width 64 $0\ra$47[63:0]$9534 + attribute \src "libresoc.v:158663.3-158677.6" + wire width 64 $0\rb$48$next[63:0]$9438 + attribute \src "libresoc.v:158439.3-158440.29" + wire width 64 $0\rb$48[63:0]$9309 + attribute \src "libresoc.v:158394.14-158394.44" + wire width 64 $0\rb$48[63:0]$9536 + attribute \src "libresoc.v:158516.3-158524.6" + wire width 128 $0\saved_state_dividend_quotient$next[127:0]$9357 + attribute \src "libresoc.v:158483.3-158484.75" + wire width 128 $0\saved_state_dividend_quotient[127:0] + attribute \src "libresoc.v:158507.3-158515.6" + wire width 7 $0\saved_state_q_bits_known$next[6:0]$9354 + attribute \src "libresoc.v:158485.3-158486.65" + wire width 7 $0\saved_state_q_bits_known[6:0] + attribute \src "libresoc.v:158678.3-158692.6" + wire $0\xer_so$49$next[0:0]$9442 + attribute \src "libresoc.v:158437.3-158438.37" + wire $0\xer_so$49[0:0]$9307 + attribute \src "libresoc.v:158412.7-158412.25" + wire $0\xer_so$49[0:0]$9540 + attribute \src "libresoc.v:158753.3-158767.6" + wire $1\div_by_zero$54$next[0:0]$9463 + attribute \src "libresoc.v:158549.3-158560.6" + wire width 64 $1\div_state_next_divisor[63:0] + attribute \src "libresoc.v:158537.3-158548.6" + wire width 128 $1\div_state_next_i_dividend_quotient[127:0] + attribute \src "libresoc.v:158525.3-158536.6" + wire width 7 $1\div_state_next_i_q_bits_known[6:0] + attribute \src "libresoc.v:158723.3-158737.6" + wire $1\dive_abs_ov32$52$next[0:0]$9455 + attribute \src "libresoc.v:158738.3-158752.6" + wire $1\dive_abs_ov64$53$next[0:0]$9459 + attribute \src "libresoc.v:158768.3-158782.6" + wire width 128 $1\dividend$68$next[127:0]$9467 + attribute \src "libresoc.v:158708.3-158722.6" + wire $1\dividend_neg$51$next[0:0]$9451 + attribute \src "libresoc.v:158693.3-158707.6" + wire $1\divisor_neg$50$next[0:0]$9447 + attribute \src "libresoc.v:158783.3-158797.6" + wire width 64 $1\divisor_radicand$65$next[63:0]$9471 + attribute \src "libresoc.v:158561.3-158588.6" + wire $1\empty$next[0:0]$9364 + attribute \src "libresoc.v:157937.7-157937.19" + wire $1\empty[0:0] + attribute \src "libresoc.v:158604.3-158647.6" + wire width 4 $1\logical_op__data_len$45$next[3:0]$9391 + attribute \src "libresoc.v:158604.3-158647.6" + wire width 12 $1\logical_op__fn_unit$30$next[11:0]$9392 + attribute \src "libresoc.v:158604.3-158647.6" + wire width 64 $1\logical_op__imm_data__data$31$next[63:0]$9393 + attribute \src "libresoc.v:158604.3-158647.6" + wire $1\logical_op__imm_data__ok$32$next[0:0]$9394 + attribute \src "libresoc.v:158604.3-158647.6" + wire width 2 $1\logical_op__input_carry$39$next[1:0]$9395 + attribute \src "libresoc.v:158604.3-158647.6" + wire width 32 $1\logical_op__insn$46$next[31:0]$9396 + attribute \src "libresoc.v:158604.3-158647.6" + wire width 7 $1\logical_op__insn_type$29$next[6:0]$9397 + attribute \src "libresoc.v:158604.3-158647.6" + wire $1\logical_op__invert_in$37$next[0:0]$9398 + attribute \src "libresoc.v:158604.3-158647.6" + wire $1\logical_op__invert_out$40$next[0:0]$9399 + attribute \src "libresoc.v:158604.3-158647.6" + wire $1\logical_op__is_32bit$43$next[0:0]$9400 + attribute \src "libresoc.v:158604.3-158647.6" + wire $1\logical_op__is_signed$44$next[0:0]$9401 + attribute \src "libresoc.v:158604.3-158647.6" + wire $1\logical_op__oe__oe$35$next[0:0]$9402 + attribute \src "libresoc.v:158604.3-158647.6" + wire $1\logical_op__oe__ok$36$next[0:0]$9403 + attribute \src "libresoc.v:158604.3-158647.6" + wire $1\logical_op__output_carry$42$next[0:0]$9404 + attribute \src "libresoc.v:158604.3-158647.6" + wire $1\logical_op__rc__ok$34$next[0:0]$9405 + attribute \src "libresoc.v:158604.3-158647.6" + wire $1\logical_op__rc__rc$33$next[0:0]$9406 + attribute \src "libresoc.v:158604.3-158647.6" + wire $1\logical_op__write_cr0$41$next[0:0]$9407 + attribute \src "libresoc.v:158604.3-158647.6" + wire $1\logical_op__zero_a$38$next[0:0]$9408 + attribute \src "libresoc.v:158589.3-158603.6" + wire width 2 $1\muxid$28$next[1:0]$9370 + attribute \src "libresoc.v:158798.3-158812.6" + wire width 2 $1\operation$69$next[1:0]$9475 + attribute \src "libresoc.v:158648.3-158662.6" + wire width 64 $1\ra$47$next[63:0]$9435 + attribute \src "libresoc.v:158663.3-158677.6" + wire width 64 $1\rb$48$next[63:0]$9439 + attribute \src "libresoc.v:158516.3-158524.6" + wire width 128 $1\saved_state_dividend_quotient$next[127:0]$9358 + attribute \src "libresoc.v:158400.15-158400.84" + wire width 128 $1\saved_state_dividend_quotient[127:0] + attribute \src "libresoc.v:158507.3-158515.6" + wire width 7 $1\saved_state_q_bits_known$next[6:0]$9355 + attribute \src "libresoc.v:158404.13-158404.45" + wire width 7 $1\saved_state_q_bits_known[6:0] + attribute \src "libresoc.v:158678.3-158692.6" + wire $1\xer_so$49$next[0:0]$9443 + attribute \src "libresoc.v:158753.3-158767.6" + wire $2\div_by_zero$54$next[0:0]$9464 + attribute \src "libresoc.v:158723.3-158737.6" + wire $2\dive_abs_ov32$52$next[0:0]$9456 + attribute \src "libresoc.v:158738.3-158752.6" + wire $2\dive_abs_ov64$53$next[0:0]$9460 + attribute \src "libresoc.v:158768.3-158782.6" + wire width 128 $2\dividend$68$next[127:0]$9468 + attribute \src "libresoc.v:158708.3-158722.6" + wire $2\dividend_neg$51$next[0:0]$9452 + attribute \src "libresoc.v:158693.3-158707.6" + wire $2\divisor_neg$50$next[0:0]$9448 + attribute \src "libresoc.v:158783.3-158797.6" + wire width 64 $2\divisor_radicand$65$next[63:0]$9472 + attribute \src "libresoc.v:158561.3-158588.6" + wire $2\empty$next[0:0]$9365 + attribute \src "libresoc.v:158604.3-158647.6" + wire width 4 $2\logical_op__data_len$45$next[3:0]$9409 + attribute \src "libresoc.v:158604.3-158647.6" + wire width 12 $2\logical_op__fn_unit$30$next[11:0]$9410 + attribute \src "libresoc.v:158604.3-158647.6" + wire width 64 $2\logical_op__imm_data__data$31$next[63:0]$9411 + attribute \src "libresoc.v:158604.3-158647.6" + wire $2\logical_op__imm_data__ok$32$next[0:0]$9412 + attribute \src "libresoc.v:158604.3-158647.6" + wire width 2 $2\logical_op__input_carry$39$next[1:0]$9413 + attribute \src "libresoc.v:158604.3-158647.6" + wire width 32 $2\logical_op__insn$46$next[31:0]$9414 + attribute \src "libresoc.v:158604.3-158647.6" + wire width 7 $2\logical_op__insn_type$29$next[6:0]$9415 + attribute \src "libresoc.v:158604.3-158647.6" + wire $2\logical_op__invert_in$37$next[0:0]$9416 + attribute \src "libresoc.v:158604.3-158647.6" + wire $2\logical_op__invert_out$40$next[0:0]$9417 + attribute \src "libresoc.v:158604.3-158647.6" + wire $2\logical_op__is_32bit$43$next[0:0]$9418 + attribute \src "libresoc.v:158604.3-158647.6" + wire $2\logical_op__is_signed$44$next[0:0]$9419 + attribute \src "libresoc.v:158604.3-158647.6" + wire $2\logical_op__oe__oe$35$next[0:0]$9420 + attribute \src "libresoc.v:158604.3-158647.6" + wire $2\logical_op__oe__ok$36$next[0:0]$9421 + attribute \src "libresoc.v:158604.3-158647.6" + wire $2\logical_op__output_carry$42$next[0:0]$9422 + attribute \src "libresoc.v:158604.3-158647.6" + wire $2\logical_op__rc__ok$34$next[0:0]$9423 + attribute \src "libresoc.v:158604.3-158647.6" + wire $2\logical_op__rc__rc$33$next[0:0]$9424 + attribute \src "libresoc.v:158604.3-158647.6" + wire $2\logical_op__write_cr0$41$next[0:0]$9425 + attribute \src "libresoc.v:158604.3-158647.6" + wire $2\logical_op__zero_a$38$next[0:0]$9426 + attribute \src "libresoc.v:158589.3-158603.6" + wire width 2 $2\muxid$28$next[1:0]$9371 + attribute \src "libresoc.v:158798.3-158812.6" + wire width 2 $2\operation$69$next[1:0]$9476 + attribute \src "libresoc.v:158648.3-158662.6" + wire width 64 $2\ra$47$next[63:0]$9436 + attribute \src "libresoc.v:158663.3-158677.6" + wire width 64 $2\rb$48$next[63:0]$9440 + attribute \src "libresoc.v:158678.3-158692.6" + wire $2\xer_so$49$next[0:0]$9444 + attribute \src "libresoc.v:158561.3-158588.6" + wire $3\empty$next[0:0]$9366 + attribute \src "libresoc.v:158604.3-158647.6" + wire width 64 $3\logical_op__imm_data__data$31$next[63:0]$9427 + attribute \src "libresoc.v:158604.3-158647.6" + wire $3\logical_op__imm_data__ok$32$next[0:0]$9428 + attribute \src "libresoc.v:158604.3-158647.6" + wire $3\logical_op__oe__oe$35$next[0:0]$9429 + attribute \src "libresoc.v:158604.3-158647.6" + wire $3\logical_op__oe__ok$36$next[0:0]$9430 + attribute \src "libresoc.v:158604.3-158647.6" + wire $3\logical_op__rc__ok$34$next[0:0]$9431 + attribute \src "libresoc.v:158604.3-158647.6" + wire $3\logical_op__rc__rc$33$next[0:0]$9432 + attribute \src "libresoc.v:158561.3-158588.6" + wire $4\empty$next[0:0]$9367 + attribute \src "libresoc.v:158419.18-158419.98" + wire $and$libresoc.v:158419$9288_Y + attribute \src "libresoc.v:158420.18-158420.107" + wire $and$libresoc.v:158420$9289_Y + attribute \src "libresoc.v:158418.18-158418.124" + wire $eq$libresoc.v:158418$9287_Y + attribute \src "libresoc.v:158416.18-158416.92" + wire width 192 $extend$libresoc.v:158416$9284_Y + attribute \src "libresoc.v:158417.18-158417.93" + wire $not$libresoc.v:158417$9286_Y + attribute \src "libresoc.v:158416.18-158416.92" + wire width 192 $pos$libresoc.v:158416$9285_Y + attribute \src "libresoc.v:158415.18-158415.138" + wire width 191 $sshl$libresoc.v:158415$9283_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:162" + wire width 192 \$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:162" + wire width 191 \$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:163" + wire \$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:109" + wire \$61 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:163" + wire \$63 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:177" + wire \$66 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 65 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire input 30 \div_by_zero + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire output 62 \div_by_zero$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire \div_by_zero$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire \div_by_zero$54$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:89" + wire width 128 \div_state_init_dividend + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:105" + wire width 128 \div_state_init_o_dividend_quotient + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:103" + wire width 7 \div_state_init_o_q_bits_known + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:59" + wire width 64 \div_state_next_divisor + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:105" + wire width 128 \div_state_next_i_dividend_quotient + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:103" + wire width 7 \div_state_next_i_q_bits_known + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:105" + wire width 128 \div_state_next_o_dividend_quotient + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:103" + wire width 7 \div_state_next_o_q_bits_known + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire input 28 \dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire output 60 \dive_abs_ov32$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire \dive_abs_ov32$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire \dive_abs_ov32$52$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire input 29 \dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire output 61 \dive_abs_ov64$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire \dive_abs_ov64$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire \dive_abs_ov64$53$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" + wire width 128 input 31 \dividend + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" + wire width 128 \dividend$68 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" + wire width 128 \dividend$68$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire input 27 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire output 59 \dividend_neg$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire \dividend_neg$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire \dividend_neg$51$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire input 26 \divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire output 58 \divisor_neg$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire \divisor_neg$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire \divisor_neg$50$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" + wire width 64 input 32 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" + wire width 64 \divisor_radicand$65 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" + wire width 64 \divisor_radicand$65$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:133" + wire \empty + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:133" + wire \empty$next + attribute \src "libresoc.v:157851.7-157851.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 21 \logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 53 \logical_op__data_len$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \logical_op__data_len$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \logical_op__data_len$45$next + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 6 \logical_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 output 38 \logical_op__fn_unit$3 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \logical_op__fn_unit$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \logical_op__fn_unit$30$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 7 \logical_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \logical_op__imm_data__data$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \logical_op__imm_data__data$31$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 39 \logical_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \logical_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__imm_data__ok$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__imm_data__ok$32$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 40 \logical_op__imm_data__ok$5 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 15 \logical_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 47 \logical_op__input_carry$12 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \logical_op__input_carry$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \logical_op__input_carry$39$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 22 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 54 \logical_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \logical_op__insn$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \logical_op__insn$46$next + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 5 \logical_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 37 \logical_op__insn_type$2 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \logical_op__insn_type$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \logical_op__insn_type$29$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 45 \logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_in$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_in$37$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 16 \logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 48 \logical_op__invert_out$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_out$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_out$40$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 19 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 51 \logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_32bit$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_32bit$43$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 20 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 52 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_signed$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_signed$44$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 11 \logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__oe$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__oe$35$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 43 \logical_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__ok$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__ok$36$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 44 \logical_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 18 \logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 50 \logical_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__output_carry$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__output_carry$42$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__ok$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__ok$34$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 42 \logical_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__rc$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__rc$33$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 41 \logical_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 17 \logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 49 \logical_op__write_cr0$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__write_cr0$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__write_cr0$41$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 46 \logical_op__zero_a$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__zero_a$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__zero_a$38$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 4 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 36 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$28$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire input 35 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire output 34 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" + wire width 2 input 33 \operation + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" + wire width 2 \operation$69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" + wire width 2 \operation$69$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire output 3 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" + wire width 64 output 63 \quotient_root + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 23 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 55 \ra$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \ra$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \ra$47$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 24 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 56 \rb$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \rb$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \rb$48$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:41" + wire width 192 output 64 \remainder + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:105" + wire width 128 \saved_state_dividend_quotient + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:105" + wire width 128 \saved_state_dividend_quotient$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:103" + wire width 7 \saved_state_q_bits_known + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:103" + wire width 7 \saved_state_q_bits_known$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 25 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire output 57 \xer_so$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \xer_so$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \xer_so$49$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:163" + cell $and $and$libresoc.v:158419$9288 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$59 + connect \B \$61 + connect \Y $and$libresoc.v:158419$9288_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:177" + cell $and $and$libresoc.v:158420$9289 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $and$libresoc.v:158420$9289_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:109" + cell $eq $eq$libresoc.v:158418$9287 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \div_state_next_o_q_bits_known + connect \B 7'1000000 + connect \Y $eq$libresoc.v:158418$9287_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:162" + cell $pos $extend$libresoc.v:158416$9284 + parameter \A_SIGNED 0 + parameter \A_WIDTH 191 + parameter \Y_WIDTH 192 + connect \A \$56 + connect \Y $extend$libresoc.v:158416$9284_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:163" + cell $not $not$libresoc.v:158417$9286 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \empty + connect \Y $not$libresoc.v:158417$9286_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:162" + cell $pos $pos$libresoc.v:158416$9285 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A $extend$libresoc.v:158416$9284_Y + connect \Y $pos$libresoc.v:158416$9285_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:162" + cell $sshl $sshl$libresoc.v:158415$9283 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 191 + connect \A \div_state_next_o_dividend_quotient [127:64] + connect \B 7'1000000 + connect \Y $sshl$libresoc.v:158415$9283_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:158487.18-158491.4" + cell \div_state_init \div_state_init + connect \dividend \div_state_init_dividend + connect \o_dividend_quotient \div_state_init_o_dividend_quotient + connect \o_q_bits_known \div_state_init_o_q_bits_known + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:158492.18-158498.4" + cell \div_state_next \div_state_next + connect \divisor \div_state_next_divisor + connect \i_dividend_quotient \div_state_next_i_dividend_quotient + connect \i_q_bits_known \div_state_next_i_q_bits_known + connect \o_dividend_quotient \div_state_next_o_dividend_quotient + connect \o_q_bits_known \div_state_next_o_q_bits_known + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:158499.10-158502.4" + cell \n$77 \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:158503.10-158506.4" + cell \p$76 \p + connect \p_ready_o \p_ready_o + connect \p_valid_i \p_valid_i + end + attribute \src "libresoc.v:157851.7-157851.20" + process $proc$libresoc.v:157851$9477 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:157873.7-157873.30" + process $proc$libresoc.v:157873$9478 + assign { } { } + assign $0\div_by_zero$54[0:0]$9479 1'0 + sync always + sync init + update \div_by_zero$54 $0\div_by_zero$54[0:0]$9479 + end + attribute \src "libresoc.v:157897.7-157897.32" + process $proc$libresoc.v:157897$9480 + assign { } { } + assign $0\dive_abs_ov32$52[0:0]$9481 1'0 + sync always + sync init + update \dive_abs_ov32$52 $0\dive_abs_ov32$52[0:0]$9481 + end + attribute \src "libresoc.v:157905.7-157905.32" + process $proc$libresoc.v:157905$9482 + assign { } { } + assign $0\dive_abs_ov64$53[0:0]$9483 1'0 + sync always + sync init + update \dive_abs_ov64$53 $0\dive_abs_ov64$53[0:0]$9483 + end + attribute \src "libresoc.v:157911.15-157911.68" + process $proc$libresoc.v:157911$9484 + assign { } { } + assign $0\dividend$68[127:0]$9485 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \dividend$68 $0\dividend$68[127:0]$9485 + end + attribute \src "libresoc.v:157919.7-157919.31" + process $proc$libresoc.v:157919$9486 + assign { } { } + assign $0\dividend_neg$51[0:0]$9487 1'0 + sync always + sync init + update \dividend_neg$51 $0\dividend_neg$51[0:0]$9487 + end + attribute \src "libresoc.v:157927.7-157927.30" + process $proc$libresoc.v:157927$9488 + assign { } { } + assign $0\divisor_neg$50[0:0]$9489 1'0 + sync always + sync init + update \divisor_neg$50 $0\divisor_neg$50[0:0]$9489 + end + attribute \src "libresoc.v:157933.14-157933.58" + process $proc$libresoc.v:157933$9490 + assign { } { } + assign $0\divisor_radicand$65[63:0]$9491 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \divisor_radicand$65 $0\divisor_radicand$65[63:0]$9491 + end + attribute \src "libresoc.v:157937.7-157937.19" + process $proc$libresoc.v:157937$9492 + assign { } { } + assign $1\empty[0:0] 1'1 + sync always + sync init + update \empty $1\empty[0:0] + end + attribute \src "libresoc.v:157945.13-157945.45" + process $proc$libresoc.v:157945$9493 + assign { } { } + assign $0\logical_op__data_len$45[3:0]$9494 4'0000 + sync always + sync init + update \logical_op__data_len$45 $0\logical_op__data_len$45[3:0]$9494 + end + attribute \src "libresoc.v:157992.14-157992.48" + process $proc$libresoc.v:157992$9495 + assign { } { } + assign $0\logical_op__fn_unit$30[11:0]$9496 12'000000000000 + sync always + sync init + update \logical_op__fn_unit$30 $0\logical_op__fn_unit$30[11:0]$9496 + end + attribute \src "libresoc.v:157998.14-157998.68" + process $proc$libresoc.v:157998$9497 + assign { } { } + assign $0\logical_op__imm_data__data$31[63:0]$9498 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \logical_op__imm_data__data$31 $0\logical_op__imm_data__data$31[63:0]$9498 + end + attribute \src "libresoc.v:158006.7-158006.43" + process $proc$libresoc.v:158006$9499 + assign { } { } + assign $0\logical_op__imm_data__ok$32[0:0]$9500 1'0 + sync always + sync init + update \logical_op__imm_data__ok$32 $0\logical_op__imm_data__ok$32[0:0]$9500 + end + attribute \src "libresoc.v:158028.13-158028.48" + process $proc$libresoc.v:158028$9501 + assign { } { } + assign $0\logical_op__input_carry$39[1:0]$9502 2'00 + sync always + sync init + update \logical_op__input_carry$39 $0\logical_op__input_carry$39[1:0]$9502 + end + attribute \src "libresoc.v:158036.14-158036.43" + process $proc$libresoc.v:158036$9503 + assign { } { } + assign $0\logical_op__insn$46[31:0]$9504 0 + sync always + sync init + update \logical_op__insn$46 $0\logical_op__insn$46[31:0]$9504 + end + attribute \src "libresoc.v:158266.13-158266.47" + process $proc$libresoc.v:158266$9505 + assign { } { } + assign $0\logical_op__insn_type$29[6:0]$9506 7'0000000 + sync always + sync init + update \logical_op__insn_type$29 $0\logical_op__insn_type$29[6:0]$9506 + end + attribute \src "libresoc.v:158274.7-158274.40" + process $proc$libresoc.v:158274$9507 + assign { } { } + assign $0\logical_op__invert_in$37[0:0]$9508 1'0 + sync always + sync init + update \logical_op__invert_in$37 $0\logical_op__invert_in$37[0:0]$9508 + end + attribute \src "libresoc.v:158282.7-158282.41" + process $proc$libresoc.v:158282$9509 + assign { } { } + assign $0\logical_op__invert_out$40[0:0]$9510 1'0 + sync always + sync init + update \logical_op__invert_out$40 $0\logical_op__invert_out$40[0:0]$9510 + end + attribute \src "libresoc.v:158290.7-158290.39" + process $proc$libresoc.v:158290$9511 + assign { } { } + assign $0\logical_op__is_32bit$43[0:0]$9512 1'0 + sync always + sync init + update \logical_op__is_32bit$43 $0\logical_op__is_32bit$43[0:0]$9512 + end + attribute \src "libresoc.v:158298.7-158298.40" + process $proc$libresoc.v:158298$9513 + assign { } { } + assign $0\logical_op__is_signed$44[0:0]$9514 1'0 + sync always + sync init + update \logical_op__is_signed$44 $0\logical_op__is_signed$44[0:0]$9514 + end + attribute \src "libresoc.v:158304.7-158304.37" + process $proc$libresoc.v:158304$9515 + assign { } { } + assign $0\logical_op__oe__oe$35[0:0]$9516 1'0 + sync always + sync init + update \logical_op__oe__oe$35 $0\logical_op__oe__oe$35[0:0]$9516 + end + attribute \src "libresoc.v:158312.7-158312.37" + process $proc$libresoc.v:158312$9517 + assign { } { } + assign $0\logical_op__oe__ok$36[0:0]$9518 1'0 + sync always + sync init + update \logical_op__oe__ok$36 $0\logical_op__oe__ok$36[0:0]$9518 + end + attribute \src "libresoc.v:158322.7-158322.43" + process $proc$libresoc.v:158322$9519 + assign { } { } + assign $0\logical_op__output_carry$42[0:0]$9520 1'0 + sync always + sync init + update \logical_op__output_carry$42 $0\logical_op__output_carry$42[0:0]$9520 + end + attribute \src "libresoc.v:158328.7-158328.37" + process $proc$libresoc.v:158328$9521 + assign { } { } + assign $0\logical_op__rc__ok$34[0:0]$9522 1'0 + sync always + sync init + update \logical_op__rc__ok$34 $0\logical_op__rc__ok$34[0:0]$9522 + end + attribute \src "libresoc.v:158336.7-158336.37" + process $proc$libresoc.v:158336$9523 + assign { } { } + assign $0\logical_op__rc__rc$33[0:0]$9524 1'0 + sync always + sync init + update \logical_op__rc__rc$33 $0\logical_op__rc__rc$33[0:0]$9524 + end + attribute \src "libresoc.v:158346.7-158346.40" + process $proc$libresoc.v:158346$9525 + assign { } { } + assign $0\logical_op__write_cr0$41[0:0]$9526 1'0 + sync always + sync init + update \logical_op__write_cr0$41 $0\logical_op__write_cr0$41[0:0]$9526 + end + attribute \src "libresoc.v:158354.7-158354.37" + process $proc$libresoc.v:158354$9527 + assign { } { } + assign $0\logical_op__zero_a$38[0:0]$9528 1'0 + sync always + sync init + update \logical_op__zero_a$38 $0\logical_op__zero_a$38[0:0]$9528 + end + attribute \src "libresoc.v:158362.13-158362.30" + process $proc$libresoc.v:158362$9529 + assign { } { } + assign $0\muxid$28[1:0]$9530 2'00 + sync always + sync init + update \muxid$28 $0\muxid$28[1:0]$9530 + end + attribute \src "libresoc.v:158372.13-158372.34" + process $proc$libresoc.v:158372$9531 + assign { } { } + assign $0\operation$69[1:0]$9532 2'00 + sync always + sync init + update \operation$69 $0\operation$69[1:0]$9532 + end + attribute \src "libresoc.v:158386.14-158386.44" + process $proc$libresoc.v:158386$9533 + assign { } { } + assign $0\ra$47[63:0]$9534 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \ra$47 $0\ra$47[63:0]$9534 + end + attribute \src "libresoc.v:158394.14-158394.44" + process $proc$libresoc.v:158394$9535 + assign { } { } + assign $0\rb$48[63:0]$9536 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \rb$48 $0\rb$48[63:0]$9536 + end + attribute \src "libresoc.v:158400.15-158400.84" + process $proc$libresoc.v:158400$9537 + assign { } { } + assign $1\saved_state_dividend_quotient[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \saved_state_dividend_quotient $1\saved_state_dividend_quotient[127:0] + end + attribute \src "libresoc.v:158404.13-158404.45" + process $proc$libresoc.v:158404$9538 + assign { } { } + assign $1\saved_state_q_bits_known[6:0] 7'0000000 + sync always + sync init + update \saved_state_q_bits_known $1\saved_state_q_bits_known[6:0] + end + attribute \src "libresoc.v:158412.7-158412.25" + process $proc$libresoc.v:158412$9539 + assign { } { } + assign $0\xer_so$49[0:0]$9540 1'0 + sync always + sync init + update \xer_so$49 $0\xer_so$49[0:0]$9540 + end + attribute \src "libresoc.v:158421.3-158422.43" + process $proc$libresoc.v:158421$9290 + assign { } { } + assign $0\operation$69[1:0]$9291 \operation$69$next + sync posedge \coresync_clk + update \operation$69 $0\operation$69[1:0]$9291 + end + attribute \src "libresoc.v:158423.3-158424.57" + process $proc$libresoc.v:158423$9292 + assign { } { } + assign $0\divisor_radicand$65[63:0]$9293 \divisor_radicand$65$next + sync posedge \coresync_clk + update \divisor_radicand$65 $0\divisor_radicand$65[63:0]$9293 + end + attribute \src "libresoc.v:158425.3-158426.41" + process $proc$libresoc.v:158425$9294 + assign { } { } + assign $0\dividend$68[127:0]$9295 \dividend$68$next + sync posedge \coresync_clk + update \dividend$68 $0\dividend$68[127:0]$9295 + end + attribute \src "libresoc.v:158427.3-158428.47" + process $proc$libresoc.v:158427$9296 + assign { } { } + assign $0\div_by_zero$54[0:0]$9297 \div_by_zero$54$next + sync posedge \coresync_clk + update \div_by_zero$54 $0\div_by_zero$54[0:0]$9297 + end + attribute \src "libresoc.v:158429.3-158430.51" + process $proc$libresoc.v:158429$9298 + assign { } { } + assign $0\dive_abs_ov64$53[0:0]$9299 \dive_abs_ov64$53$next + sync posedge \coresync_clk + update \dive_abs_ov64$53 $0\dive_abs_ov64$53[0:0]$9299 + end + attribute \src "libresoc.v:158431.3-158432.51" + process $proc$libresoc.v:158431$9300 + assign { } { } + assign $0\dive_abs_ov32$52[0:0]$9301 \dive_abs_ov32$52$next + sync posedge \coresync_clk + update \dive_abs_ov32$52 $0\dive_abs_ov32$52[0:0]$9301 + end + attribute \src "libresoc.v:158433.3-158434.49" + process $proc$libresoc.v:158433$9302 + assign { } { } + assign $0\dividend_neg$51[0:0]$9303 \dividend_neg$51$next + sync posedge \coresync_clk + update \dividend_neg$51 $0\dividend_neg$51[0:0]$9303 + end + attribute \src "libresoc.v:158435.3-158436.47" + process $proc$libresoc.v:158435$9304 + assign { } { } + assign $0\divisor_neg$50[0:0]$9305 \divisor_neg$50$next + sync posedge \coresync_clk + update \divisor_neg$50 $0\divisor_neg$50[0:0]$9305 + end + attribute \src "libresoc.v:158437.3-158438.37" + process $proc$libresoc.v:158437$9306 + assign { } { } + assign $0\xer_so$49[0:0]$9307 \xer_so$49$next + sync posedge \coresync_clk + update \xer_so$49 $0\xer_so$49[0:0]$9307 + end + attribute \src "libresoc.v:158439.3-158440.29" + process $proc$libresoc.v:158439$9308 + assign { } { } + assign $0\rb$48[63:0]$9309 \rb$48$next + sync posedge \coresync_clk + update \rb$48 $0\rb$48[63:0]$9309 + end + attribute \src "libresoc.v:158441.3-158442.29" + process $proc$libresoc.v:158441$9310 + assign { } { } + assign $0\ra$47[63:0]$9311 \ra$47$next + sync posedge \coresync_clk + update \ra$47 $0\ra$47[63:0]$9311 + end + attribute \src "libresoc.v:158443.3-158444.67" + process $proc$libresoc.v:158443$9312 + assign { } { } + assign $0\logical_op__insn_type$29[6:0]$9313 \logical_op__insn_type$29$next + sync posedge \coresync_clk + update \logical_op__insn_type$29 $0\logical_op__insn_type$29[6:0]$9313 + end + attribute \src "libresoc.v:158445.3-158446.63" + process $proc$libresoc.v:158445$9314 + assign { } { } + assign $0\logical_op__fn_unit$30[11:0]$9315 \logical_op__fn_unit$30$next + sync posedge \coresync_clk + update \logical_op__fn_unit$30 $0\logical_op__fn_unit$30[11:0]$9315 + end + attribute \src "libresoc.v:158447.3-158448.77" + process $proc$libresoc.v:158447$9316 + assign { } { } + assign $0\logical_op__imm_data__data$31[63:0]$9317 \logical_op__imm_data__data$31$next + sync posedge \coresync_clk + update \logical_op__imm_data__data$31 $0\logical_op__imm_data__data$31[63:0]$9317 + end + attribute \src "libresoc.v:158449.3-158450.73" + process $proc$libresoc.v:158449$9318 + assign { } { } + assign $0\logical_op__imm_data__ok$32[0:0]$9319 \logical_op__imm_data__ok$32$next + sync posedge \coresync_clk + update \logical_op__imm_data__ok$32 $0\logical_op__imm_data__ok$32[0:0]$9319 + end + attribute \src "libresoc.v:158451.3-158452.61" + process $proc$libresoc.v:158451$9320 + assign { } { } + assign $0\logical_op__rc__rc$33[0:0]$9321 \logical_op__rc__rc$33$next + sync posedge \coresync_clk + update \logical_op__rc__rc$33 $0\logical_op__rc__rc$33[0:0]$9321 + end + attribute \src "libresoc.v:158453.3-158454.61" + process $proc$libresoc.v:158453$9322 + assign { } { } + assign $0\logical_op__rc__ok$34[0:0]$9323 \logical_op__rc__ok$34$next + sync posedge \coresync_clk + update \logical_op__rc__ok$34 $0\logical_op__rc__ok$34[0:0]$9323 + end + attribute \src "libresoc.v:158455.3-158456.61" + process $proc$libresoc.v:158455$9324 + assign { } { } + assign $0\logical_op__oe__oe$35[0:0]$9325 \logical_op__oe__oe$35$next + sync posedge \coresync_clk + update \logical_op__oe__oe$35 $0\logical_op__oe__oe$35[0:0]$9325 + end + attribute \src "libresoc.v:158457.3-158458.61" + process $proc$libresoc.v:158457$9326 + assign { } { } + assign $0\logical_op__oe__ok$36[0:0]$9327 \logical_op__oe__ok$36$next + sync posedge \coresync_clk + update \logical_op__oe__ok$36 $0\logical_op__oe__ok$36[0:0]$9327 + end + attribute \src "libresoc.v:158459.3-158460.67" + process $proc$libresoc.v:158459$9328 + assign { } { } + assign $0\logical_op__invert_in$37[0:0]$9329 \logical_op__invert_in$37$next + sync posedge \coresync_clk + update \logical_op__invert_in$37 $0\logical_op__invert_in$37[0:0]$9329 + end + attribute \src "libresoc.v:158461.3-158462.61" + process $proc$libresoc.v:158461$9330 + assign { } { } + assign $0\logical_op__zero_a$38[0:0]$9331 \logical_op__zero_a$38$next + sync posedge \coresync_clk + update \logical_op__zero_a$38 $0\logical_op__zero_a$38[0:0]$9331 + end + attribute \src "libresoc.v:158463.3-158464.71" + process $proc$libresoc.v:158463$9332 + assign { } { } + assign $0\logical_op__input_carry$39[1:0]$9333 \logical_op__input_carry$39$next + sync posedge \coresync_clk + update \logical_op__input_carry$39 $0\logical_op__input_carry$39[1:0]$9333 + end + attribute \src "libresoc.v:158465.3-158466.69" + process $proc$libresoc.v:158465$9334 + assign { } { } + assign $0\logical_op__invert_out$40[0:0]$9335 \logical_op__invert_out$40$next + sync posedge \coresync_clk + update \logical_op__invert_out$40 $0\logical_op__invert_out$40[0:0]$9335 + end + attribute \src "libresoc.v:158467.3-158468.67" + process $proc$libresoc.v:158467$9336 + assign { } { } + assign $0\logical_op__write_cr0$41[0:0]$9337 \logical_op__write_cr0$41$next + sync posedge \coresync_clk + update \logical_op__write_cr0$41 $0\logical_op__write_cr0$41[0:0]$9337 + end + attribute \src "libresoc.v:158469.3-158470.73" + process $proc$libresoc.v:158469$9338 + assign { } { } + assign $0\logical_op__output_carry$42[0:0]$9339 \logical_op__output_carry$42$next + sync posedge \coresync_clk + update \logical_op__output_carry$42 $0\logical_op__output_carry$42[0:0]$9339 + end + attribute \src "libresoc.v:158471.3-158472.65" + process $proc$libresoc.v:158471$9340 + assign { } { } + assign $0\logical_op__is_32bit$43[0:0]$9341 \logical_op__is_32bit$43$next + sync posedge \coresync_clk + update \logical_op__is_32bit$43 $0\logical_op__is_32bit$43[0:0]$9341 + end + attribute \src "libresoc.v:158473.3-158474.67" + process $proc$libresoc.v:158473$9342 + assign { } { } + assign $0\logical_op__is_signed$44[0:0]$9343 \logical_op__is_signed$44$next + sync posedge \coresync_clk + update \logical_op__is_signed$44 $0\logical_op__is_signed$44[0:0]$9343 + end + attribute \src "libresoc.v:158475.3-158476.65" + process $proc$libresoc.v:158475$9344 + assign { } { } + assign $0\logical_op__data_len$45[3:0]$9345 \logical_op__data_len$45$next + sync posedge \coresync_clk + update \logical_op__data_len$45 $0\logical_op__data_len$45[3:0]$9345 + end + attribute \src "libresoc.v:158477.3-158478.57" + process $proc$libresoc.v:158477$9346 + assign { } { } + assign $0\logical_op__insn$46[31:0]$9347 \logical_op__insn$46$next + sync posedge \coresync_clk + update \logical_op__insn$46 $0\logical_op__insn$46[31:0]$9347 + end + attribute \src "libresoc.v:158479.3-158480.35" + process $proc$libresoc.v:158479$9348 + assign { } { } + assign $0\muxid$28[1:0]$9349 \muxid$28$next + sync posedge \coresync_clk + update \muxid$28 $0\muxid$28[1:0]$9349 + end + attribute \src "libresoc.v:158481.3-158482.27" + process $proc$libresoc.v:158481$9350 + assign { } { } + assign $0\empty[0:0] \empty$next + sync posedge \coresync_clk + update \empty $0\empty[0:0] + end + attribute \src "libresoc.v:158483.3-158484.75" + process $proc$libresoc.v:158483$9351 + assign { } { } + assign $0\saved_state_dividend_quotient[127:0] \saved_state_dividend_quotient$next + sync posedge \coresync_clk + update \saved_state_dividend_quotient $0\saved_state_dividend_quotient[127:0] + end + attribute \src "libresoc.v:158485.3-158486.65" + process $proc$libresoc.v:158485$9352 + assign { } { } + assign $0\saved_state_q_bits_known[6:0] \saved_state_q_bits_known$next + sync posedge \coresync_clk + update \saved_state_q_bits_known $0\saved_state_q_bits_known[6:0] + end + attribute \src "libresoc.v:158507.3-158515.6" + process $proc$libresoc.v:158507$9353 + assign { } { } + assign { } { } + assign $0\saved_state_q_bits_known$next[6:0]$9354 $1\saved_state_q_bits_known$next[6:0]$9355 + attribute \src "libresoc.v:158508.5-158508.29" + switch \initial + attribute \src "libresoc.v:158508.9-158508.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\saved_state_q_bits_known$next[6:0]$9355 7'0000000 + case + assign $1\saved_state_q_bits_known$next[6:0]$9355 \div_state_next_o_q_bits_known + end + sync always + update \saved_state_q_bits_known$next $0\saved_state_q_bits_known$next[6:0]$9354 + end + attribute \src "libresoc.v:158516.3-158524.6" + process $proc$libresoc.v:158516$9356 + assign { } { } + assign { } { } + assign $0\saved_state_dividend_quotient$next[127:0]$9357 $1\saved_state_dividend_quotient$next[127:0]$9358 + attribute \src "libresoc.v:158517.5-158517.29" + switch \initial + attribute \src "libresoc.v:158517.9-158517.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\saved_state_dividend_quotient$next[127:0]$9358 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + case + assign $1\saved_state_dividend_quotient$next[127:0]$9358 \div_state_next_o_dividend_quotient + end + sync always + update \saved_state_dividend_quotient$next $0\saved_state_dividend_quotient$next[127:0]$9357 + end + attribute \src "libresoc.v:158525.3-158536.6" + process $proc$libresoc.v:158525$9359 + assign { } { } + assign $0\div_state_next_i_q_bits_known[6:0] $1\div_state_next_i_q_bits_known[6:0] + attribute \src "libresoc.v:158526.5-158526.29" + switch \initial + attribute \src "libresoc.v:158526.9-158526.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:167" + switch \empty + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\div_state_next_i_q_bits_known[6:0] \div_state_init_o_q_bits_known + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\div_state_next_i_q_bits_known[6:0] \saved_state_q_bits_known + end + sync always + update \div_state_next_i_q_bits_known $0\div_state_next_i_q_bits_known[6:0] + end + attribute \src "libresoc.v:158537.3-158548.6" + process $proc$libresoc.v:158537$9360 + assign { } { } + assign $0\div_state_next_i_dividend_quotient[127:0] $1\div_state_next_i_dividend_quotient[127:0] + attribute \src "libresoc.v:158538.5-158538.29" + switch \initial + attribute \src "libresoc.v:158538.9-158538.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:167" + switch \empty + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\div_state_next_i_dividend_quotient[127:0] \div_state_init_o_dividend_quotient + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\div_state_next_i_dividend_quotient[127:0] \saved_state_dividend_quotient + end + sync always + update \div_state_next_i_dividend_quotient $0\div_state_next_i_dividend_quotient[127:0] + end + attribute \src "libresoc.v:158549.3-158560.6" + process $proc$libresoc.v:158549$9361 + assign { } { } + assign $0\div_state_next_divisor[63:0] $1\div_state_next_divisor[63:0] + attribute \src "libresoc.v:158550.5-158550.29" + switch \initial + attribute \src "libresoc.v:158550.9-158550.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:167" + switch \empty + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\div_state_next_divisor[63:0] \divisor_radicand + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\div_state_next_divisor[63:0] \divisor_radicand$65 + end + sync always + update \div_state_next_divisor $0\div_state_next_divisor[63:0] + end + attribute \src "libresoc.v:158561.3-158588.6" + process $proc$libresoc.v:158561$9362 + assign { } { } + assign { } { } + assign { } { } + assign $0\empty$next[0:0]$9363 $4\empty$next[0:0]$9367 + attribute \src "libresoc.v:158562.5-158562.29" + switch \initial + attribute \src "libresoc.v:158562.9-158562.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:167" + switch \empty + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\empty$next[0:0]$9364 $2\empty$next[0:0]$9365 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:170" + switch \p_valid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\empty$next[0:0]$9365 1'0 + case + assign $2\empty$next[0:0]$9365 \empty + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\empty$next[0:0]$9364 $3\empty$next[0:0]$9366 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:177" + switch \$66 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\empty$next[0:0]$9366 1'1 + case + assign $3\empty$next[0:0]$9366 \empty + end + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\empty$next[0:0]$9367 1'1 + case + assign $4\empty$next[0:0]$9367 $1\empty$next[0:0]$9364 + end + sync always + update \empty$next $0\empty$next[0:0]$9363 + end + attribute \src "libresoc.v:158589.3-158603.6" + process $proc$libresoc.v:158589$9368 + assign { } { } + assign { } { } + assign $0\muxid$28$next[1:0]$9369 $1\muxid$28$next[1:0]$9370 + attribute \src "libresoc.v:158590.5-158590.29" + switch \initial + attribute \src "libresoc.v:158590.9-158590.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:167" + switch \empty + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\muxid$28$next[1:0]$9370 $2\muxid$28$next[1:0]$9371 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:170" + switch \p_valid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\muxid$28$next[1:0]$9371 \muxid + case + assign $2\muxid$28$next[1:0]$9371 \muxid$28 + end + case + assign $1\muxid$28$next[1:0]$9370 \muxid$28 + end + sync always + update \muxid$28$next $0\muxid$28$next[1:0]$9369 + end + attribute \src "libresoc.v:158604.3-158647.6" + process $proc$libresoc.v:158604$9372 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\logical_op__data_len$45$next[3:0]$9373 $1\logical_op__data_len$45$next[3:0]$9391 + assign $0\logical_op__fn_unit$30$next[11:0]$9374 $1\logical_op__fn_unit$30$next[11:0]$9392 + assign { } { } + assign { } { } + assign $0\logical_op__input_carry$39$next[1:0]$9377 $1\logical_op__input_carry$39$next[1:0]$9395 + assign $0\logical_op__insn$46$next[31:0]$9378 $1\logical_op__insn$46$next[31:0]$9396 + assign $0\logical_op__insn_type$29$next[6:0]$9379 $1\logical_op__insn_type$29$next[6:0]$9397 + assign $0\logical_op__invert_in$37$next[0:0]$9380 $1\logical_op__invert_in$37$next[0:0]$9398 + assign $0\logical_op__invert_out$40$next[0:0]$9381 $1\logical_op__invert_out$40$next[0:0]$9399 + assign $0\logical_op__is_32bit$43$next[0:0]$9382 $1\logical_op__is_32bit$43$next[0:0]$9400 + assign $0\logical_op__is_signed$44$next[0:0]$9383 $1\logical_op__is_signed$44$next[0:0]$9401 + assign { } { } + assign { } { } + assign $0\logical_op__output_carry$42$next[0:0]$9386 $1\logical_op__output_carry$42$next[0:0]$9404 + assign { } { } + assign { } { } + assign $0\logical_op__write_cr0$41$next[0:0]$9389 $1\logical_op__write_cr0$41$next[0:0]$9407 + assign $0\logical_op__zero_a$38$next[0:0]$9390 $1\logical_op__zero_a$38$next[0:0]$9408 + assign $0\logical_op__imm_data__data$31$next[63:0]$9375 $3\logical_op__imm_data__data$31$next[63:0]$9427 + assign $0\logical_op__imm_data__ok$32$next[0:0]$9376 $3\logical_op__imm_data__ok$32$next[0:0]$9428 + assign $0\logical_op__oe__oe$35$next[0:0]$9384 $3\logical_op__oe__oe$35$next[0:0]$9429 + assign $0\logical_op__oe__ok$36$next[0:0]$9385 $3\logical_op__oe__ok$36$next[0:0]$9430 + assign $0\logical_op__rc__ok$34$next[0:0]$9387 $3\logical_op__rc__ok$34$next[0:0]$9431 + assign $0\logical_op__rc__rc$33$next[0:0]$9388 $3\logical_op__rc__rc$33$next[0:0]$9432 + attribute \src "libresoc.v:158605.5-158605.29" + switch \initial + attribute \src "libresoc.v:158605.9-158605.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:167" + switch \empty + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\logical_op__data_len$45$next[3:0]$9391 $2\logical_op__data_len$45$next[3:0]$9409 + assign $1\logical_op__fn_unit$30$next[11:0]$9392 $2\logical_op__fn_unit$30$next[11:0]$9410 + assign $1\logical_op__imm_data__data$31$next[63:0]$9393 $2\logical_op__imm_data__data$31$next[63:0]$9411 + assign $1\logical_op__imm_data__ok$32$next[0:0]$9394 $2\logical_op__imm_data__ok$32$next[0:0]$9412 + assign $1\logical_op__input_carry$39$next[1:0]$9395 $2\logical_op__input_carry$39$next[1:0]$9413 + assign $1\logical_op__insn$46$next[31:0]$9396 $2\logical_op__insn$46$next[31:0]$9414 + assign $1\logical_op__insn_type$29$next[6:0]$9397 $2\logical_op__insn_type$29$next[6:0]$9415 + assign $1\logical_op__invert_in$37$next[0:0]$9398 $2\logical_op__invert_in$37$next[0:0]$9416 + assign $1\logical_op__invert_out$40$next[0:0]$9399 $2\logical_op__invert_out$40$next[0:0]$9417 + assign $1\logical_op__is_32bit$43$next[0:0]$9400 $2\logical_op__is_32bit$43$next[0:0]$9418 + assign $1\logical_op__is_signed$44$next[0:0]$9401 $2\logical_op__is_signed$44$next[0:0]$9419 + assign $1\logical_op__oe__oe$35$next[0:0]$9402 $2\logical_op__oe__oe$35$next[0:0]$9420 + assign $1\logical_op__oe__ok$36$next[0:0]$9403 $2\logical_op__oe__ok$36$next[0:0]$9421 + assign $1\logical_op__output_carry$42$next[0:0]$9404 $2\logical_op__output_carry$42$next[0:0]$9422 + assign $1\logical_op__rc__ok$34$next[0:0]$9405 $2\logical_op__rc__ok$34$next[0:0]$9423 + assign $1\logical_op__rc__rc$33$next[0:0]$9406 $2\logical_op__rc__rc$33$next[0:0]$9424 + assign $1\logical_op__write_cr0$41$next[0:0]$9407 $2\logical_op__write_cr0$41$next[0:0]$9425 + assign $1\logical_op__zero_a$38$next[0:0]$9408 $2\logical_op__zero_a$38$next[0:0]$9426 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:170" + switch \p_valid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $2\logical_op__insn$46$next[31:0]$9414 $2\logical_op__data_len$45$next[3:0]$9409 $2\logical_op__is_signed$44$next[0:0]$9419 $2\logical_op__is_32bit$43$next[0:0]$9418 $2\logical_op__output_carry$42$next[0:0]$9422 $2\logical_op__write_cr0$41$next[0:0]$9425 $2\logical_op__invert_out$40$next[0:0]$9417 $2\logical_op__input_carry$39$next[1:0]$9413 $2\logical_op__zero_a$38$next[0:0]$9426 $2\logical_op__invert_in$37$next[0:0]$9416 $2\logical_op__oe__ok$36$next[0:0]$9421 $2\logical_op__oe__oe$35$next[0:0]$9420 $2\logical_op__rc__ok$34$next[0:0]$9423 $2\logical_op__rc__rc$33$next[0:0]$9424 $2\logical_op__imm_data__ok$32$next[0:0]$9412 $2\logical_op__imm_data__data$31$next[63:0]$9411 $2\logical_op__fn_unit$30$next[11:0]$9410 $2\logical_op__insn_type$29$next[6:0]$9415 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } + case + assign $2\logical_op__data_len$45$next[3:0]$9409 \logical_op__data_len$45 + assign $2\logical_op__fn_unit$30$next[11:0]$9410 \logical_op__fn_unit$30 + assign $2\logical_op__imm_data__data$31$next[63:0]$9411 \logical_op__imm_data__data$31 + assign $2\logical_op__imm_data__ok$32$next[0:0]$9412 \logical_op__imm_data__ok$32 + assign $2\logical_op__input_carry$39$next[1:0]$9413 \logical_op__input_carry$39 + assign $2\logical_op__insn$46$next[31:0]$9414 \logical_op__insn$46 + assign $2\logical_op__insn_type$29$next[6:0]$9415 \logical_op__insn_type$29 + assign $2\logical_op__invert_in$37$next[0:0]$9416 \logical_op__invert_in$37 + assign $2\logical_op__invert_out$40$next[0:0]$9417 \logical_op__invert_out$40 + assign $2\logical_op__is_32bit$43$next[0:0]$9418 \logical_op__is_32bit$43 + assign $2\logical_op__is_signed$44$next[0:0]$9419 \logical_op__is_signed$44 + assign $2\logical_op__oe__oe$35$next[0:0]$9420 \logical_op__oe__oe$35 + assign $2\logical_op__oe__ok$36$next[0:0]$9421 \logical_op__oe__ok$36 + assign $2\logical_op__output_carry$42$next[0:0]$9422 \logical_op__output_carry$42 + assign $2\logical_op__rc__ok$34$next[0:0]$9423 \logical_op__rc__ok$34 + assign $2\logical_op__rc__rc$33$next[0:0]$9424 \logical_op__rc__rc$33 + assign $2\logical_op__write_cr0$41$next[0:0]$9425 \logical_op__write_cr0$41 + assign $2\logical_op__zero_a$38$next[0:0]$9426 \logical_op__zero_a$38 + end + case + assign $1\logical_op__data_len$45$next[3:0]$9391 \logical_op__data_len$45 + assign $1\logical_op__fn_unit$30$next[11:0]$9392 \logical_op__fn_unit$30 + assign $1\logical_op__imm_data__data$31$next[63:0]$9393 \logical_op__imm_data__data$31 + assign $1\logical_op__imm_data__ok$32$next[0:0]$9394 \logical_op__imm_data__ok$32 + assign $1\logical_op__input_carry$39$next[1:0]$9395 \logical_op__input_carry$39 + assign $1\logical_op__insn$46$next[31:0]$9396 \logical_op__insn$46 + assign $1\logical_op__insn_type$29$next[6:0]$9397 \logical_op__insn_type$29 + assign $1\logical_op__invert_in$37$next[0:0]$9398 \logical_op__invert_in$37 + assign $1\logical_op__invert_out$40$next[0:0]$9399 \logical_op__invert_out$40 + assign $1\logical_op__is_32bit$43$next[0:0]$9400 \logical_op__is_32bit$43 + assign $1\logical_op__is_signed$44$next[0:0]$9401 \logical_op__is_signed$44 + assign $1\logical_op__oe__oe$35$next[0:0]$9402 \logical_op__oe__oe$35 + assign $1\logical_op__oe__ok$36$next[0:0]$9403 \logical_op__oe__ok$36 + assign $1\logical_op__output_carry$42$next[0:0]$9404 \logical_op__output_carry$42 + assign $1\logical_op__rc__ok$34$next[0:0]$9405 \logical_op__rc__ok$34 + assign $1\logical_op__rc__rc$33$next[0:0]$9406 \logical_op__rc__rc$33 + assign $1\logical_op__write_cr0$41$next[0:0]$9407 \logical_op__write_cr0$41 + assign $1\logical_op__zero_a$38$next[0:0]$9408 \logical_op__zero_a$38 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $3\logical_op__imm_data__data$31$next[63:0]$9427 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\logical_op__imm_data__ok$32$next[0:0]$9428 1'0 + assign $3\logical_op__rc__rc$33$next[0:0]$9432 1'0 + assign $3\logical_op__rc__ok$34$next[0:0]$9431 1'0 + assign $3\logical_op__oe__oe$35$next[0:0]$9429 1'0 + assign $3\logical_op__oe__ok$36$next[0:0]$9430 1'0 + case + assign $3\logical_op__imm_data__data$31$next[63:0]$9427 $1\logical_op__imm_data__data$31$next[63:0]$9393 + assign $3\logical_op__imm_data__ok$32$next[0:0]$9428 $1\logical_op__imm_data__ok$32$next[0:0]$9394 + assign $3\logical_op__oe__oe$35$next[0:0]$9429 $1\logical_op__oe__oe$35$next[0:0]$9402 + assign $3\logical_op__oe__ok$36$next[0:0]$9430 $1\logical_op__oe__ok$36$next[0:0]$9403 + assign $3\logical_op__rc__ok$34$next[0:0]$9431 $1\logical_op__rc__ok$34$next[0:0]$9405 + assign $3\logical_op__rc__rc$33$next[0:0]$9432 $1\logical_op__rc__rc$33$next[0:0]$9406 + end + sync always + update \logical_op__data_len$45$next $0\logical_op__data_len$45$next[3:0]$9373 + update \logical_op__fn_unit$30$next $0\logical_op__fn_unit$30$next[11:0]$9374 + update \logical_op__imm_data__data$31$next $0\logical_op__imm_data__data$31$next[63:0]$9375 + update \logical_op__imm_data__ok$32$next $0\logical_op__imm_data__ok$32$next[0:0]$9376 + update \logical_op__input_carry$39$next $0\logical_op__input_carry$39$next[1:0]$9377 + update \logical_op__insn$46$next $0\logical_op__insn$46$next[31:0]$9378 + update \logical_op__insn_type$29$next $0\logical_op__insn_type$29$next[6:0]$9379 + update \logical_op__invert_in$37$next $0\logical_op__invert_in$37$next[0:0]$9380 + update \logical_op__invert_out$40$next $0\logical_op__invert_out$40$next[0:0]$9381 + update \logical_op__is_32bit$43$next $0\logical_op__is_32bit$43$next[0:0]$9382 + update \logical_op__is_signed$44$next $0\logical_op__is_signed$44$next[0:0]$9383 + update \logical_op__oe__oe$35$next $0\logical_op__oe__oe$35$next[0:0]$9384 + update \logical_op__oe__ok$36$next $0\logical_op__oe__ok$36$next[0:0]$9385 + update \logical_op__output_carry$42$next $0\logical_op__output_carry$42$next[0:0]$9386 + update \logical_op__rc__ok$34$next $0\logical_op__rc__ok$34$next[0:0]$9387 + update \logical_op__rc__rc$33$next $0\logical_op__rc__rc$33$next[0:0]$9388 + update \logical_op__write_cr0$41$next $0\logical_op__write_cr0$41$next[0:0]$9389 + update \logical_op__zero_a$38$next $0\logical_op__zero_a$38$next[0:0]$9390 + end + attribute \src "libresoc.v:158648.3-158662.6" + process $proc$libresoc.v:158648$9433 + assign { } { } + assign { } { } + assign $0\ra$47$next[63:0]$9434 $1\ra$47$next[63:0]$9435 + attribute \src "libresoc.v:158649.5-158649.29" + switch \initial + attribute \src "libresoc.v:158649.9-158649.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:167" + switch \empty + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ra$47$next[63:0]$9435 $2\ra$47$next[63:0]$9436 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:170" + switch \p_valid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ra$47$next[63:0]$9436 \ra + case + assign $2\ra$47$next[63:0]$9436 \ra$47 + end + case + assign $1\ra$47$next[63:0]$9435 \ra$47 + end + sync always + update \ra$47$next $0\ra$47$next[63:0]$9434 + end + attribute \src "libresoc.v:158663.3-158677.6" + process $proc$libresoc.v:158663$9437 + assign { } { } + assign { } { } + assign $0\rb$48$next[63:0]$9438 $1\rb$48$next[63:0]$9439 + attribute \src "libresoc.v:158664.5-158664.29" + switch \initial + attribute \src "libresoc.v:158664.9-158664.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:167" + switch \empty + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rb$48$next[63:0]$9439 $2\rb$48$next[63:0]$9440 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:170" + switch \p_valid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\rb$48$next[63:0]$9440 \rb + case + assign $2\rb$48$next[63:0]$9440 \rb$48 + end + case + assign $1\rb$48$next[63:0]$9439 \rb$48 + end + sync always + update \rb$48$next $0\rb$48$next[63:0]$9438 + end + attribute \src "libresoc.v:158678.3-158692.6" + process $proc$libresoc.v:158678$9441 + assign { } { } + assign { } { } + assign $0\xer_so$49$next[0:0]$9442 $1\xer_so$49$next[0:0]$9443 + attribute \src "libresoc.v:158679.5-158679.29" + switch \initial + attribute \src "libresoc.v:158679.9-158679.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:167" + switch \empty + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\xer_so$49$next[0:0]$9443 $2\xer_so$49$next[0:0]$9444 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:170" + switch \p_valid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\xer_so$49$next[0:0]$9444 \xer_so + case + assign $2\xer_so$49$next[0:0]$9444 \xer_so$49 + end + case + assign $1\xer_so$49$next[0:0]$9443 \xer_so$49 + end + sync always + update \xer_so$49$next $0\xer_so$49$next[0:0]$9442 + end + attribute \src "libresoc.v:158693.3-158707.6" + process $proc$libresoc.v:158693$9445 + assign { } { } + assign { } { } + assign $0\divisor_neg$50$next[0:0]$9446 $1\divisor_neg$50$next[0:0]$9447 + attribute \src "libresoc.v:158694.5-158694.29" + switch \initial + attribute \src "libresoc.v:158694.9-158694.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:167" + switch \empty + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\divisor_neg$50$next[0:0]$9447 $2\divisor_neg$50$next[0:0]$9448 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:170" + switch \p_valid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\divisor_neg$50$next[0:0]$9448 \divisor_neg + case + assign $2\divisor_neg$50$next[0:0]$9448 \divisor_neg$50 + end + case + assign $1\divisor_neg$50$next[0:0]$9447 \divisor_neg$50 + end + sync always + update \divisor_neg$50$next $0\divisor_neg$50$next[0:0]$9446 + end + attribute \src "libresoc.v:158708.3-158722.6" + process $proc$libresoc.v:158708$9449 + assign { } { } + assign { } { } + assign $0\dividend_neg$51$next[0:0]$9450 $1\dividend_neg$51$next[0:0]$9451 + attribute \src "libresoc.v:158709.5-158709.29" + switch \initial + attribute \src "libresoc.v:158709.9-158709.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:167" + switch \empty + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dividend_neg$51$next[0:0]$9451 $2\dividend_neg$51$next[0:0]$9452 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:170" + switch \p_valid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\dividend_neg$51$next[0:0]$9452 \dividend_neg + case + assign $2\dividend_neg$51$next[0:0]$9452 \dividend_neg$51 + end + case + assign $1\dividend_neg$51$next[0:0]$9451 \dividend_neg$51 + end + sync always + update \dividend_neg$51$next $0\dividend_neg$51$next[0:0]$9450 + end + attribute \src "libresoc.v:158723.3-158737.6" + process $proc$libresoc.v:158723$9453 + assign { } { } + assign { } { } + assign $0\dive_abs_ov32$52$next[0:0]$9454 $1\dive_abs_ov32$52$next[0:0]$9455 + attribute \src "libresoc.v:158724.5-158724.29" + switch \initial + attribute \src "libresoc.v:158724.9-158724.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:167" + switch \empty + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dive_abs_ov32$52$next[0:0]$9455 $2\dive_abs_ov32$52$next[0:0]$9456 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:170" + switch \p_valid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\dive_abs_ov32$52$next[0:0]$9456 \dive_abs_ov32 + case + assign $2\dive_abs_ov32$52$next[0:0]$9456 \dive_abs_ov32$52 + end + case + assign $1\dive_abs_ov32$52$next[0:0]$9455 \dive_abs_ov32$52 + end + sync always + update \dive_abs_ov32$52$next $0\dive_abs_ov32$52$next[0:0]$9454 + end + attribute \src "libresoc.v:158738.3-158752.6" + process $proc$libresoc.v:158738$9457 + assign { } { } + assign { } { } + assign $0\dive_abs_ov64$53$next[0:0]$9458 $1\dive_abs_ov64$53$next[0:0]$9459 + attribute \src "libresoc.v:158739.5-158739.29" + switch \initial + attribute \src "libresoc.v:158739.9-158739.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:167" + switch \empty + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dive_abs_ov64$53$next[0:0]$9459 $2\dive_abs_ov64$53$next[0:0]$9460 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:170" + switch \p_valid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\dive_abs_ov64$53$next[0:0]$9460 \dive_abs_ov64 + case + assign $2\dive_abs_ov64$53$next[0:0]$9460 \dive_abs_ov64$53 + end + case + assign $1\dive_abs_ov64$53$next[0:0]$9459 \dive_abs_ov64$53 + end + sync always + update \dive_abs_ov64$53$next $0\dive_abs_ov64$53$next[0:0]$9458 + end + attribute \src "libresoc.v:158753.3-158767.6" + process $proc$libresoc.v:158753$9461 + assign { } { } + assign { } { } + assign $0\div_by_zero$54$next[0:0]$9462 $1\div_by_zero$54$next[0:0]$9463 + attribute \src "libresoc.v:158754.5-158754.29" + switch \initial + attribute \src "libresoc.v:158754.9-158754.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:167" + switch \empty + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\div_by_zero$54$next[0:0]$9463 $2\div_by_zero$54$next[0:0]$9464 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:170" + switch \p_valid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\div_by_zero$54$next[0:0]$9464 \div_by_zero + case + assign $2\div_by_zero$54$next[0:0]$9464 \div_by_zero$54 + end + case + assign $1\div_by_zero$54$next[0:0]$9463 \div_by_zero$54 + end + sync always + update \div_by_zero$54$next $0\div_by_zero$54$next[0:0]$9462 + end + attribute \src "libresoc.v:158768.3-158782.6" + process $proc$libresoc.v:158768$9465 + assign { } { } + assign { } { } + assign $0\dividend$68$next[127:0]$9466 $1\dividend$68$next[127:0]$9467 + attribute \src "libresoc.v:158769.5-158769.29" + switch \initial + attribute \src "libresoc.v:158769.9-158769.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:167" + switch \empty + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dividend$68$next[127:0]$9467 $2\dividend$68$next[127:0]$9468 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:170" + switch \p_valid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\dividend$68$next[127:0]$9468 \dividend + case + assign $2\dividend$68$next[127:0]$9468 \dividend$68 + end + case + assign $1\dividend$68$next[127:0]$9467 \dividend$68 + end + sync always + update \dividend$68$next $0\dividend$68$next[127:0]$9466 + end + attribute \src "libresoc.v:158783.3-158797.6" + process $proc$libresoc.v:158783$9469 + assign { } { } + assign { } { } + assign $0\divisor_radicand$65$next[63:0]$9470 $1\divisor_radicand$65$next[63:0]$9471 + attribute \src "libresoc.v:158784.5-158784.29" + switch \initial + attribute \src "libresoc.v:158784.9-158784.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:167" + switch \empty + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\divisor_radicand$65$next[63:0]$9471 $2\divisor_radicand$65$next[63:0]$9472 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:170" + switch \p_valid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\divisor_radicand$65$next[63:0]$9472 \divisor_radicand + case + assign $2\divisor_radicand$65$next[63:0]$9472 \divisor_radicand$65 + end + case + assign $1\divisor_radicand$65$next[63:0]$9471 \divisor_radicand$65 + end + sync always + update \divisor_radicand$65$next $0\divisor_radicand$65$next[63:0]$9470 + end + attribute \src "libresoc.v:158798.3-158812.6" + process $proc$libresoc.v:158798$9473 + assign { } { } + assign { } { } + assign $0\operation$69$next[1:0]$9474 $1\operation$69$next[1:0]$9475 + attribute \src "libresoc.v:158799.5-158799.29" + switch \initial + attribute \src "libresoc.v:158799.9-158799.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:167" + switch \empty + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\operation$69$next[1:0]$9475 $2\operation$69$next[1:0]$9476 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:170" + switch \p_valid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\operation$69$next[1:0]$9476 \operation + case + assign $2\operation$69$next[1:0]$9476 \operation$69 + end + case + assign $1\operation$69$next[1:0]$9475 \operation$69 + end + sync always + update \operation$69$next $0\operation$69$next[1:0]$9474 + end + connect \$56 $sshl$libresoc.v:158415$9283_Y + connect \$55 $pos$libresoc.v:158416$9285_Y + connect \$59 $not$libresoc.v:158417$9286_Y + connect \$61 $eq$libresoc.v:158418$9287_Y + connect \$63 $and$libresoc.v:158419$9288_Y + connect \$66 $and$libresoc.v:158420$9289_Y + connect \p_ready_o \empty + connect \n_valid_o \$63 + connect \remainder \$55 + connect \quotient_root \div_state_next_o_dividend_quotient [63:0] + connect \div_by_zero$27 \div_by_zero$54 + connect \dive_abs_ov64$26 \dive_abs_ov64$53 + connect \dive_abs_ov32$25 \dive_abs_ov32$52 + connect \dividend_neg$24 \dividend_neg$51 + connect \divisor_neg$23 \divisor_neg$50 + connect \xer_so$22 \xer_so$49 + connect \rb$21 \rb$48 + connect \ra$20 \ra$47 + connect { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn$46 \logical_op__data_len$45 \logical_op__is_signed$44 \logical_op__is_32bit$43 \logical_op__output_carry$42 \logical_op__write_cr0$41 \logical_op__invert_out$40 \logical_op__input_carry$39 \logical_op__zero_a$38 \logical_op__invert_in$37 \logical_op__oe__ok$36 \logical_op__oe__oe$35 \logical_op__rc__ok$34 \logical_op__rc__rc$33 \logical_op__imm_data__ok$32 \logical_op__imm_data__data$31 \logical_op__fn_unit$30 \logical_op__insn_type$29 } + connect \muxid$1 \muxid$28 + connect \div_state_init_dividend \dividend +end +attribute \src "libresoc.v:158832.1-160356.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_start" +attribute \generator "nMigen" +module \pipe_start + attribute \src "libresoc.v:160162.3-160174.6" + wire $0\div_by_zero$next[0:0]$9586 + attribute \src "libresoc.v:159948.3-159949.39" + wire $0\div_by_zero[0:0] + attribute \src "libresoc.v:160136.3-160148.6" + wire $0\dive_abs_ov32$next[0:0]$9580 + attribute \src "libresoc.v:159952.3-159953.43" + wire $0\dive_abs_ov32[0:0] + attribute \src "libresoc.v:160149.3-160161.6" + wire $0\dive_abs_ov64$next[0:0]$9583 + attribute \src "libresoc.v:159950.3-159951.43" + wire $0\dive_abs_ov64[0:0] + attribute \src "libresoc.v:160175.3-160187.6" + wire width 128 $0\dividend$next[127:0]$9589 + attribute \src "libresoc.v:159946.3-159947.33" + wire width 128 $0\dividend[127:0] + attribute \src "libresoc.v:160123.3-160135.6" + wire $0\dividend_neg$next[0:0]$9577 + attribute \src "libresoc.v:159954.3-159955.41" + wire $0\dividend_neg[0:0] + attribute \src "libresoc.v:160110.3-160122.6" + wire $0\divisor_neg$next[0:0]$9574 + attribute \src "libresoc.v:159956.3-159957.39" + wire $0\divisor_neg[0:0] + attribute \src "libresoc.v:160188.3-160200.6" + wire width 64 $0\divisor_radicand$next[63:0]$9592 + attribute \src "libresoc.v:159944.3-159945.49" + wire width 64 $0\divisor_radicand[63:0] + attribute \src "libresoc.v:158833.7-158833.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:160245.3-160286.6" + wire width 4 $0\logical_op__data_len$next[3:0]$9605 + attribute \src "libresoc.v:159996.3-159997.57" + wire width 4 $0\logical_op__data_len[3:0] + attribute \src "libresoc.v:160245.3-160286.6" + wire width 12 $0\logical_op__fn_unit$next[11:0]$9606 + attribute \src "libresoc.v:159966.3-159967.55" + wire width 12 $0\logical_op__fn_unit[11:0] + attribute \src "libresoc.v:160245.3-160286.6" + wire width 64 $0\logical_op__imm_data__data$next[63:0]$9607 + attribute \src "libresoc.v:159968.3-159969.69" + wire width 64 $0\logical_op__imm_data__data[63:0] + attribute \src "libresoc.v:160245.3-160286.6" + wire $0\logical_op__imm_data__ok$next[0:0]$9608 + attribute \src "libresoc.v:159970.3-159971.65" + wire $0\logical_op__imm_data__ok[0:0] + attribute \src "libresoc.v:160245.3-160286.6" + wire width 2 $0\logical_op__input_carry$next[1:0]$9609 + attribute \src "libresoc.v:159984.3-159985.63" + wire width 2 $0\logical_op__input_carry[1:0] + attribute \src "libresoc.v:160245.3-160286.6" + wire width 32 $0\logical_op__insn$next[31:0]$9610 + attribute \src "libresoc.v:159998.3-159999.49" + wire width 32 $0\logical_op__insn[31:0] + attribute \src "libresoc.v:160245.3-160286.6" + wire width 7 $0\logical_op__insn_type$next[6:0]$9611 + attribute \src "libresoc.v:159964.3-159965.59" + wire width 7 $0\logical_op__insn_type[6:0] + attribute \src "libresoc.v:160245.3-160286.6" + wire $0\logical_op__invert_in$next[0:0]$9612 + attribute \src "libresoc.v:159980.3-159981.59" + wire $0\logical_op__invert_in[0:0] + attribute \src "libresoc.v:160245.3-160286.6" + wire $0\logical_op__invert_out$next[0:0]$9613 + attribute \src "libresoc.v:159986.3-159987.61" + wire $0\logical_op__invert_out[0:0] + attribute \src "libresoc.v:160245.3-160286.6" + wire $0\logical_op__is_32bit$next[0:0]$9614 + attribute \src "libresoc.v:159992.3-159993.57" + wire $0\logical_op__is_32bit[0:0] + attribute \src "libresoc.v:160245.3-160286.6" + wire $0\logical_op__is_signed$next[0:0]$9615 + attribute \src "libresoc.v:159994.3-159995.59" + wire $0\logical_op__is_signed[0:0] + attribute \src "libresoc.v:160245.3-160286.6" + wire $0\logical_op__oe__oe$next[0:0]$9616 + attribute \src "libresoc.v:159976.3-159977.53" + wire $0\logical_op__oe__oe[0:0] + attribute \src "libresoc.v:160245.3-160286.6" + wire $0\logical_op__oe__ok$next[0:0]$9617 + attribute \src "libresoc.v:159978.3-159979.53" + wire $0\logical_op__oe__ok[0:0] + attribute \src "libresoc.v:160245.3-160286.6" + wire $0\logical_op__output_carry$next[0:0]$9618 + attribute \src "libresoc.v:159990.3-159991.65" + wire $0\logical_op__output_carry[0:0] + attribute \src "libresoc.v:160245.3-160286.6" + wire $0\logical_op__rc__ok$next[0:0]$9619 + attribute \src "libresoc.v:159974.3-159975.53" + wire $0\logical_op__rc__ok[0:0] + attribute \src "libresoc.v:160245.3-160286.6" + wire $0\logical_op__rc__rc$next[0:0]$9620 + attribute \src "libresoc.v:159972.3-159973.53" + wire $0\logical_op__rc__rc[0:0] + attribute \src "libresoc.v:160245.3-160286.6" + wire $0\logical_op__write_cr0$next[0:0]$9621 + attribute \src "libresoc.v:159988.3-159989.59" + wire $0\logical_op__write_cr0[0:0] + attribute \src "libresoc.v:160245.3-160286.6" + wire $0\logical_op__zero_a$next[0:0]$9622 + attribute \src "libresoc.v:159982.3-159983.53" + wire $0\logical_op__zero_a[0:0] + attribute \src "libresoc.v:160232.3-160244.6" + wire width 2 $0\muxid$next[1:0]$9602 + attribute \src "libresoc.v:160000.3-160001.27" + wire width 2 $0\muxid[1:0] + attribute \src "libresoc.v:160201.3-160213.6" + wire width 2 $0\operation$next[1:0]$9595 + attribute \src "libresoc.v:159942.3-159943.35" + wire width 2 $0\operation[1:0] + attribute \src "libresoc.v:160214.3-160231.6" + wire $0\r_busy$next[0:0]$9598 + attribute \src "libresoc.v:160002.3-160003.29" + wire $0\r_busy[0:0] + attribute \src "libresoc.v:160287.3-160299.6" + wire width 64 $0\ra$next[63:0]$9648 + attribute \src "libresoc.v:159962.3-159963.21" + wire width 64 $0\ra[63:0] + attribute \src "libresoc.v:160300.3-160312.6" + wire width 64 $0\rb$next[63:0]$9651 + attribute \src "libresoc.v:159960.3-159961.21" + wire width 64 $0\rb[63:0] + attribute \src "libresoc.v:160313.3-160325.6" + wire $0\xer_so$next[0:0]$9654 + attribute \src "libresoc.v:159958.3-159959.29" + wire $0\xer_so[0:0] + attribute \src "libresoc.v:160162.3-160174.6" + wire $1\div_by_zero$next[0:0]$9587 + attribute \src "libresoc.v:158842.7-158842.25" + wire $1\div_by_zero[0:0] + attribute \src "libresoc.v:160136.3-160148.6" + wire $1\dive_abs_ov32$next[0:0]$9581 + attribute \src "libresoc.v:158849.7-158849.27" + wire $1\dive_abs_ov32[0:0] + attribute \src "libresoc.v:160149.3-160161.6" + wire $1\dive_abs_ov64$next[0:0]$9584 + attribute \src "libresoc.v:158856.7-158856.27" + wire $1\dive_abs_ov64[0:0] + attribute \src "libresoc.v:160175.3-160187.6" + wire width 128 $1\dividend$next[127:0]$9590 + attribute \src "libresoc.v:158863.15-158863.63" + wire width 128 $1\dividend[127:0] + attribute \src "libresoc.v:160123.3-160135.6" + wire $1\dividend_neg$next[0:0]$9578 + attribute \src "libresoc.v:158870.7-158870.26" + wire $1\dividend_neg[0:0] + attribute \src "libresoc.v:160110.3-160122.6" + wire $1\divisor_neg$next[0:0]$9575 + attribute \src "libresoc.v:158877.7-158877.25" + wire $1\divisor_neg[0:0] + attribute \src "libresoc.v:160188.3-160200.6" + wire width 64 $1\divisor_radicand$next[63:0]$9593 + attribute \src "libresoc.v:158884.14-158884.53" + wire width 64 $1\divisor_radicand[63:0] + attribute \src "libresoc.v:160245.3-160286.6" + wire width 4 $1\logical_op__data_len$next[3:0]$9623 + attribute \src "libresoc.v:159161.13-159161.40" + wire width 4 $1\logical_op__data_len[3:0] + attribute \src "libresoc.v:160245.3-160286.6" + wire width 12 $1\logical_op__fn_unit$next[11:0]$9624 + attribute \src "libresoc.v:159183.14-159183.43" + wire width 12 $1\logical_op__fn_unit[11:0] + attribute \src "libresoc.v:160245.3-160286.6" + wire width 64 $1\logical_op__imm_data__data$next[63:0]$9625 + attribute \src "libresoc.v:159218.14-159218.63" + wire width 64 $1\logical_op__imm_data__data[63:0] + attribute \src "libresoc.v:160245.3-160286.6" + wire $1\logical_op__imm_data__ok$next[0:0]$9626 + attribute \src "libresoc.v:159227.7-159227.38" + wire $1\logical_op__imm_data__ok[0:0] + attribute \src "libresoc.v:160245.3-160286.6" + wire width 2 $1\logical_op__input_carry$next[1:0]$9627 + attribute \src "libresoc.v:159240.13-159240.43" + wire width 2 $1\logical_op__input_carry[1:0] + attribute \src "libresoc.v:160245.3-160286.6" + wire width 32 $1\logical_op__insn$next[31:0]$9628 + attribute \src "libresoc.v:159257.14-159257.38" + wire width 32 $1\logical_op__insn[31:0] + attribute \src "libresoc.v:160245.3-160286.6" + wire width 7 $1\logical_op__insn_type$next[6:0]$9629 + attribute \src "libresoc.v:159340.13-159340.42" + wire width 7 $1\logical_op__insn_type[6:0] + attribute \src "libresoc.v:160245.3-160286.6" + wire $1\logical_op__invert_in$next[0:0]$9630 + attribute \src "libresoc.v:159497.7-159497.35" + wire $1\logical_op__invert_in[0:0] + attribute \src "libresoc.v:160245.3-160286.6" + wire $1\logical_op__invert_out$next[0:0]$9631 + attribute \src "libresoc.v:159506.7-159506.36" + wire $1\logical_op__invert_out[0:0] + attribute \src "libresoc.v:160245.3-160286.6" + wire $1\logical_op__is_32bit$next[0:0]$9632 + attribute \src "libresoc.v:159515.7-159515.34" + wire $1\logical_op__is_32bit[0:0] + attribute \src "libresoc.v:160245.3-160286.6" + wire $1\logical_op__is_signed$next[0:0]$9633 + attribute \src "libresoc.v:159524.7-159524.35" + wire $1\logical_op__is_signed[0:0] + attribute \src "libresoc.v:160245.3-160286.6" + wire $1\logical_op__oe__oe$next[0:0]$9634 + attribute \src "libresoc.v:159533.7-159533.32" + wire $1\logical_op__oe__oe[0:0] + attribute \src "libresoc.v:160245.3-160286.6" + wire $1\logical_op__oe__ok$next[0:0]$9635 + attribute \src "libresoc.v:159542.7-159542.32" + wire $1\logical_op__oe__ok[0:0] + attribute \src "libresoc.v:160245.3-160286.6" + wire $1\logical_op__output_carry$next[0:0]$9636 + attribute \src "libresoc.v:159551.7-159551.38" + wire $1\logical_op__output_carry[0:0] + attribute \src "libresoc.v:160245.3-160286.6" + wire $1\logical_op__rc__ok$next[0:0]$9637 + attribute \src "libresoc.v:159560.7-159560.32" + wire $1\logical_op__rc__ok[0:0] + attribute \src "libresoc.v:160245.3-160286.6" + wire $1\logical_op__rc__rc$next[0:0]$9638 + attribute \src "libresoc.v:159569.7-159569.32" + wire $1\logical_op__rc__rc[0:0] + attribute \src "libresoc.v:160245.3-160286.6" + wire $1\logical_op__write_cr0$next[0:0]$9639 + attribute \src "libresoc.v:159578.7-159578.35" + wire $1\logical_op__write_cr0[0:0] + attribute \src "libresoc.v:160245.3-160286.6" + wire $1\logical_op__zero_a$next[0:0]$9640 + attribute \src "libresoc.v:159587.7-159587.32" + wire $1\logical_op__zero_a[0:0] + attribute \src "libresoc.v:160232.3-160244.6" + wire width 2 $1\muxid$next[1:0]$9603 + attribute \src "libresoc.v:159596.13-159596.25" + wire width 2 $1\muxid[1:0] + attribute \src "libresoc.v:160201.3-160213.6" + wire width 2 $1\operation$next[1:0]$9596 + attribute \src "libresoc.v:159611.13-159611.29" + wire width 2 $1\operation[1:0] + attribute \src "libresoc.v:160214.3-160231.6" + wire $1\r_busy$next[0:0]$9599 + attribute \src "libresoc.v:159625.7-159625.20" + wire $1\r_busy[0:0] + attribute \src "libresoc.v:160287.3-160299.6" + wire width 64 $1\ra$next[63:0]$9649 + attribute \src "libresoc.v:159630.14-159630.39" + wire width 64 $1\ra[63:0] + attribute \src "libresoc.v:160300.3-160312.6" + wire width 64 $1\rb$next[63:0]$9652 + attribute \src "libresoc.v:159641.14-159641.39" + wire width 64 $1\rb[63:0] + attribute \src "libresoc.v:160313.3-160325.6" + wire $1\xer_so$next[0:0]$9655 + attribute \src "libresoc.v:159934.7-159934.20" + wire $1\xer_so[0:0] + attribute \src "libresoc.v:160245.3-160286.6" + wire width 64 $2\logical_op__imm_data__data$next[63:0]$9641 + attribute \src "libresoc.v:160245.3-160286.6" + wire $2\logical_op__imm_data__ok$next[0:0]$9642 + attribute \src "libresoc.v:160245.3-160286.6" + wire $2\logical_op__oe__oe$next[0:0]$9643 + attribute \src "libresoc.v:160245.3-160286.6" + wire $2\logical_op__oe__ok$next[0:0]$9644 + attribute \src "libresoc.v:160245.3-160286.6" + wire $2\logical_op__rc__ok$next[0:0]$9645 + attribute \src "libresoc.v:160245.3-160286.6" + wire $2\logical_op__rc__rc$next[0:0]$9646 + attribute \src "libresoc.v:160214.3-160231.6" + wire $2\r_busy$next[0:0]$9600 + attribute \src "libresoc.v:159941.18-159941.118" + wire $and$libresoc.v:159941$9541_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + wire \$66 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 58 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire output 30 \div_by_zero + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire \div_by_zero$96 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire \div_by_zero$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire output 28 \dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire \dive_abs_ov32$94 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire \dive_abs_ov32$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire output 29 \dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire \dive_abs_ov64$95 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire \dive_abs_ov64$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" + wire width 128 output 31 \dividend + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" + wire width 128 \dividend$97 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" + wire width 128 \dividend$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire output 27 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire \dividend_neg$93 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire \dividend_neg$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire output 26 \divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire \divisor_neg$92 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire \divisor_neg$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" + wire width 64 output 32 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" + wire width 64 \divisor_radicand$98 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" + wire width 64 \divisor_radicand$next + attribute \src "libresoc.v:158833.7-158833.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \input_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \input_logical_op__data_len$40 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \input_logical_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \input_logical_op__fn_unit$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \input_logical_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \input_logical_op__imm_data__data$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__imm_data__ok$27 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \input_logical_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \input_logical_op__input_carry$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \input_logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \input_logical_op__insn$41 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \input_logical_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \input_logical_op__insn_type$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__invert_in$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__invert_out$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__is_32bit$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__is_signed$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__oe__oe$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__oe__ok$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__output_carry$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__rc__ok$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__rc__rc$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__write_cr0$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__zero_a$33 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \input_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \input_muxid$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_ra$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_rb$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \input_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \input_xer_so$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 21 \logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 53 \logical_op__data_len$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \logical_op__data_len$85 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \logical_op__data_len$next + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 output 6 \logical_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 38 \logical_op__fn_unit$3 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \logical_op__fn_unit$70 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \logical_op__fn_unit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 7 \logical_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 39 \logical_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \logical_op__imm_data__data$71 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \logical_op__imm_data__data$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 8 \logical_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 40 \logical_op__imm_data__ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__imm_data__ok$72 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__imm_data__ok$next + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 15 \logical_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 47 \logical_op__input_carry$12 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \logical_op__input_carry$79 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \logical_op__input_carry$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 22 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 54 \logical_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \logical_op__insn$86 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \logical_op__insn$next + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 5 \logical_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 37 \logical_op__insn_type$2 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \logical_op__insn_type$69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \logical_op__insn_type$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 13 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 45 \logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_in$77 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_in$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 16 \logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 48 \logical_op__invert_out$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_out$80 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_out$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 19 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 51 \logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_32bit$83 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_32bit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 20 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 52 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_signed$84 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_signed$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 11 \logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__oe$75 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 43 \logical_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__oe$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 12 \logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__ok$76 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 44 \logical_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 18 \logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 50 \logical_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__output_carry$82 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__output_carry$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 10 \logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 42 \logical_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__ok$74 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 9 \logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 41 \logical_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__rc$73 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__rc$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 17 \logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 49 \logical_op__write_cr0$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__write_cr0$81 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__write_cr0$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 14 \logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 46 \logical_op__zero_a$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__zero_a$78 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__zero_a$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 4 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 36 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$68 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" + wire \n_i_rdy_data + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire input 3 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire output 2 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" + wire width 2 output 33 \operation + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" + wire width 2 \operation$99 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" + wire width 2 \operation$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire output 35 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire input 34 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" + wire \p_valid_i$65 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire \r_busy$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 23 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 55 \ra$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \ra$87 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \ra$88 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \ra$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 24 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 56 \rb$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \rb$89 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \rb$90 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \rb$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire \setup_stage_div_by_zero + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire \setup_stage_dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire \setup_stage_dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" + wire width 128 \setup_stage_dividend + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire \setup_stage_dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire \setup_stage_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" + wire width 64 \setup_stage_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \setup_stage_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \setup_stage_logical_op__data_len$62 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \setup_stage_logical_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \setup_stage_logical_op__fn_unit$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \setup_stage_logical_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \setup_stage_logical_op__imm_data__data$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \setup_stage_logical_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \setup_stage_logical_op__imm_data__ok$49 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \setup_stage_logical_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \setup_stage_logical_op__input_carry$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \setup_stage_logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \setup_stage_logical_op__insn$63 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \setup_stage_logical_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \setup_stage_logical_op__insn_type$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \setup_stage_logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \setup_stage_logical_op__invert_in$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \setup_stage_logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \setup_stage_logical_op__invert_out$57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \setup_stage_logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \setup_stage_logical_op__is_32bit$60 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \setup_stage_logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \setup_stage_logical_op__is_signed$61 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \setup_stage_logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \setup_stage_logical_op__oe__oe$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \setup_stage_logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \setup_stage_logical_op__oe__ok$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \setup_stage_logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \setup_stage_logical_op__output_carry$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \setup_stage_logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \setup_stage_logical_op__rc__ok$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \setup_stage_logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \setup_stage_logical_op__rc__rc$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \setup_stage_logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \setup_stage_logical_op__write_cr0$58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \setup_stage_logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \setup_stage_logical_op__zero_a$55 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \setup_stage_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \setup_stage_muxid$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" + wire width 2 \setup_stage_operation + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \setup_stage_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \setup_stage_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \setup_stage_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \setup_stage_xer_so$64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire output 25 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 57 \xer_so$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \xer_so$91 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \xer_so$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + cell $and $and$libresoc.v:159941$9541 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i$65 + connect \B \p_ready_o + connect \Y $and$libresoc.v:159941$9541_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:160004.14-160049.4" + cell \input$75 \input + connect \logical_op__data_len \input_logical_op__data_len + connect \logical_op__data_len$18 \input_logical_op__data_len$40 + connect \logical_op__fn_unit \input_logical_op__fn_unit + connect \logical_op__fn_unit$3 \input_logical_op__fn_unit$25 + connect \logical_op__imm_data__data \input_logical_op__imm_data__data + connect \logical_op__imm_data__data$4 \input_logical_op__imm_data__data$26 + connect \logical_op__imm_data__ok \input_logical_op__imm_data__ok + connect \logical_op__imm_data__ok$5 \input_logical_op__imm_data__ok$27 + connect \logical_op__input_carry \input_logical_op__input_carry + connect \logical_op__input_carry$12 \input_logical_op__input_carry$34 + connect \logical_op__insn \input_logical_op__insn + connect \logical_op__insn$19 \input_logical_op__insn$41 + connect \logical_op__insn_type \input_logical_op__insn_type + connect \logical_op__insn_type$2 \input_logical_op__insn_type$24 + connect \logical_op__invert_in \input_logical_op__invert_in + connect \logical_op__invert_in$10 \input_logical_op__invert_in$32 + connect \logical_op__invert_out \input_logical_op__invert_out + connect \logical_op__invert_out$13 \input_logical_op__invert_out$35 + connect \logical_op__is_32bit \input_logical_op__is_32bit + connect \logical_op__is_32bit$16 \input_logical_op__is_32bit$38 + connect \logical_op__is_signed \input_logical_op__is_signed + connect \logical_op__is_signed$17 \input_logical_op__is_signed$39 + connect \logical_op__oe__oe \input_logical_op__oe__oe + connect \logical_op__oe__oe$8 \input_logical_op__oe__oe$30 + connect \logical_op__oe__ok \input_logical_op__oe__ok + connect \logical_op__oe__ok$9 \input_logical_op__oe__ok$31 + connect \logical_op__output_carry \input_logical_op__output_carry + connect \logical_op__output_carry$15 \input_logical_op__output_carry$37 + connect \logical_op__rc__ok \input_logical_op__rc__ok + connect \logical_op__rc__ok$7 \input_logical_op__rc__ok$29 + connect \logical_op__rc__rc \input_logical_op__rc__rc + connect \logical_op__rc__rc$6 \input_logical_op__rc__rc$28 + connect \logical_op__write_cr0 \input_logical_op__write_cr0 + connect \logical_op__write_cr0$14 \input_logical_op__write_cr0$36 + connect \logical_op__zero_a \input_logical_op__zero_a + connect \logical_op__zero_a$11 \input_logical_op__zero_a$33 + connect \muxid \input_muxid + connect \muxid$1 \input_muxid$23 + connect \ra \input_ra + connect \ra$20 \input_ra$42 + connect \rb \input_rb + connect \rb$21 \input_rb$43 + connect \xer_so \input_xer_so + connect \xer_so$22 \input_xer_so$44 + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:160050.10-160053.4" + cell \n$74 \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:160054.10-160057.4" + cell \p$73 \p + connect \p_ready_o \p_ready_o + connect \p_valid_i \p_valid_i + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:160058.15-160109.4" + cell \setup_stage \setup_stage + connect \div_by_zero \setup_stage_div_by_zero + connect \dive_abs_ov32 \setup_stage_dive_abs_ov32 + connect \dive_abs_ov64 \setup_stage_dive_abs_ov64 + connect \dividend \setup_stage_dividend + connect \dividend_neg \setup_stage_dividend_neg + connect \divisor_neg \setup_stage_divisor_neg + connect \divisor_radicand \setup_stage_divisor_radicand + connect \logical_op__data_len \setup_stage_logical_op__data_len + connect \logical_op__data_len$18 \setup_stage_logical_op__data_len$62 + connect \logical_op__fn_unit \setup_stage_logical_op__fn_unit + connect \logical_op__fn_unit$3 \setup_stage_logical_op__fn_unit$47 + connect \logical_op__imm_data__data \setup_stage_logical_op__imm_data__data + connect \logical_op__imm_data__data$4 \setup_stage_logical_op__imm_data__data$48 + connect \logical_op__imm_data__ok \setup_stage_logical_op__imm_data__ok + connect \logical_op__imm_data__ok$5 \setup_stage_logical_op__imm_data__ok$49 + connect \logical_op__input_carry \setup_stage_logical_op__input_carry + connect \logical_op__input_carry$12 \setup_stage_logical_op__input_carry$56 + connect \logical_op__insn \setup_stage_logical_op__insn + connect \logical_op__insn$19 \setup_stage_logical_op__insn$63 + connect \logical_op__insn_type \setup_stage_logical_op__insn_type + connect \logical_op__insn_type$2 \setup_stage_logical_op__insn_type$46 + connect \logical_op__invert_in \setup_stage_logical_op__invert_in + connect \logical_op__invert_in$10 \setup_stage_logical_op__invert_in$54 + connect \logical_op__invert_out \setup_stage_logical_op__invert_out + connect \logical_op__invert_out$13 \setup_stage_logical_op__invert_out$57 + connect \logical_op__is_32bit \setup_stage_logical_op__is_32bit + connect \logical_op__is_32bit$16 \setup_stage_logical_op__is_32bit$60 + connect \logical_op__is_signed \setup_stage_logical_op__is_signed + connect \logical_op__is_signed$17 \setup_stage_logical_op__is_signed$61 + connect \logical_op__oe__oe \setup_stage_logical_op__oe__oe + connect \logical_op__oe__oe$8 \setup_stage_logical_op__oe__oe$52 + connect \logical_op__oe__ok \setup_stage_logical_op__oe__ok + connect \logical_op__oe__ok$9 \setup_stage_logical_op__oe__ok$53 + connect \logical_op__output_carry \setup_stage_logical_op__output_carry + connect \logical_op__output_carry$15 \setup_stage_logical_op__output_carry$59 + connect \logical_op__rc__ok \setup_stage_logical_op__rc__ok + connect \logical_op__rc__ok$7 \setup_stage_logical_op__rc__ok$51 + connect \logical_op__rc__rc \setup_stage_logical_op__rc__rc + connect \logical_op__rc__rc$6 \setup_stage_logical_op__rc__rc$50 + connect \logical_op__write_cr0 \setup_stage_logical_op__write_cr0 + connect \logical_op__write_cr0$14 \setup_stage_logical_op__write_cr0$58 + connect \logical_op__zero_a \setup_stage_logical_op__zero_a + connect \logical_op__zero_a$11 \setup_stage_logical_op__zero_a$55 + connect \muxid \setup_stage_muxid + connect \muxid$1 \setup_stage_muxid$45 + connect \operation \setup_stage_operation + connect \ra \setup_stage_ra + connect \rb \setup_stage_rb + connect \xer_so \setup_stage_xer_so + connect \xer_so$20 \setup_stage_xer_so$64 + end + attribute \src "libresoc.v:158833.7-158833.20" + process $proc$libresoc.v:158833$9656 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:158842.7-158842.25" + process $proc$libresoc.v:158842$9657 + assign { } { } + assign $1\div_by_zero[0:0] 1'0 + sync always + sync init + update \div_by_zero $1\div_by_zero[0:0] + end + attribute \src "libresoc.v:158849.7-158849.27" + process $proc$libresoc.v:158849$9658 + assign { } { } + assign $1\dive_abs_ov32[0:0] 1'0 + sync always + sync init + update \dive_abs_ov32 $1\dive_abs_ov32[0:0] + end + attribute \src "libresoc.v:158856.7-158856.27" + process $proc$libresoc.v:158856$9659 + assign { } { } + assign $1\dive_abs_ov64[0:0] 1'0 + sync always + sync init + update \dive_abs_ov64 $1\dive_abs_ov64[0:0] + end + attribute \src "libresoc.v:158863.15-158863.63" + process $proc$libresoc.v:158863$9660 + assign { } { } + assign $1\dividend[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \dividend $1\dividend[127:0] + end + attribute \src "libresoc.v:158870.7-158870.26" + process $proc$libresoc.v:158870$9661 + assign { } { } + assign $1\dividend_neg[0:0] 1'0 + sync always + sync init + update \dividend_neg $1\dividend_neg[0:0] + end + attribute \src "libresoc.v:158877.7-158877.25" + process $proc$libresoc.v:158877$9662 + assign { } { } + assign $1\divisor_neg[0:0] 1'0 + sync always + sync init + update \divisor_neg $1\divisor_neg[0:0] + end + attribute \src "libresoc.v:158884.14-158884.53" + process $proc$libresoc.v:158884$9663 + assign { } { } + assign $1\divisor_radicand[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \divisor_radicand $1\divisor_radicand[63:0] + end + attribute \src "libresoc.v:159161.13-159161.40" + process $proc$libresoc.v:159161$9664 + assign { } { } + assign $1\logical_op__data_len[3:0] 4'0000 + sync always + sync init + update \logical_op__data_len $1\logical_op__data_len[3:0] + end + attribute \src "libresoc.v:159183.14-159183.43" + process $proc$libresoc.v:159183$9665 + assign { } { } + assign $1\logical_op__fn_unit[11:0] 12'000000000000 + sync always + sync init + update \logical_op__fn_unit $1\logical_op__fn_unit[11:0] + end + attribute \src "libresoc.v:159218.14-159218.63" + process $proc$libresoc.v:159218$9666 + assign { } { } + assign $1\logical_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \logical_op__imm_data__data $1\logical_op__imm_data__data[63:0] + end + attribute \src "libresoc.v:159227.7-159227.38" + process $proc$libresoc.v:159227$9667 + assign { } { } + assign $1\logical_op__imm_data__ok[0:0] 1'0 + sync always + sync init + update \logical_op__imm_data__ok $1\logical_op__imm_data__ok[0:0] + end + attribute \src "libresoc.v:159240.13-159240.43" + process $proc$libresoc.v:159240$9668 + assign { } { } + assign $1\logical_op__input_carry[1:0] 2'00 + sync always + sync init + update \logical_op__input_carry $1\logical_op__input_carry[1:0] + end + attribute \src "libresoc.v:159257.14-159257.38" + process $proc$libresoc.v:159257$9669 + assign { } { } + assign $1\logical_op__insn[31:0] 0 + sync always + sync init + update \logical_op__insn $1\logical_op__insn[31:0] + end + attribute \src "libresoc.v:159340.13-159340.42" + process $proc$libresoc.v:159340$9670 + assign { } { } + assign $1\logical_op__insn_type[6:0] 7'0000000 + sync always + sync init + update \logical_op__insn_type $1\logical_op__insn_type[6:0] + end + attribute \src "libresoc.v:159497.7-159497.35" + process $proc$libresoc.v:159497$9671 + assign { } { } + assign $1\logical_op__invert_in[0:0] 1'0 + sync always + sync init + update \logical_op__invert_in $1\logical_op__invert_in[0:0] + end + attribute \src "libresoc.v:159506.7-159506.36" + process $proc$libresoc.v:159506$9672 + assign { } { } + assign $1\logical_op__invert_out[0:0] 1'0 + sync always + sync init + update \logical_op__invert_out $1\logical_op__invert_out[0:0] + end + attribute \src "libresoc.v:159515.7-159515.34" + process $proc$libresoc.v:159515$9673 + assign { } { } + assign $1\logical_op__is_32bit[0:0] 1'0 + sync always + sync init + update \logical_op__is_32bit $1\logical_op__is_32bit[0:0] + end + attribute \src "libresoc.v:159524.7-159524.35" + process $proc$libresoc.v:159524$9674 + assign { } { } + assign $1\logical_op__is_signed[0:0] 1'0 + sync always + sync init + update \logical_op__is_signed $1\logical_op__is_signed[0:0] + end + attribute \src "libresoc.v:159533.7-159533.32" + process $proc$libresoc.v:159533$9675 + assign { } { } + assign $1\logical_op__oe__oe[0:0] 1'0 + sync always + sync init + update \logical_op__oe__oe $1\logical_op__oe__oe[0:0] + end + attribute \src "libresoc.v:159542.7-159542.32" + process $proc$libresoc.v:159542$9676 + assign { } { } + assign $1\logical_op__oe__ok[0:0] 1'0 + sync always + sync init + update \logical_op__oe__ok $1\logical_op__oe__ok[0:0] + end + attribute \src "libresoc.v:159551.7-159551.38" + process $proc$libresoc.v:159551$9677 + assign { } { } + assign $1\logical_op__output_carry[0:0] 1'0 + sync always + sync init + update \logical_op__output_carry $1\logical_op__output_carry[0:0] + end + attribute \src "libresoc.v:159560.7-159560.32" + process $proc$libresoc.v:159560$9678 + assign { } { } + assign $1\logical_op__rc__ok[0:0] 1'0 + sync always + sync init + update \logical_op__rc__ok $1\logical_op__rc__ok[0:0] + end + attribute \src "libresoc.v:159569.7-159569.32" + process $proc$libresoc.v:159569$9679 + assign { } { } + assign $1\logical_op__rc__rc[0:0] 1'0 + sync always + sync init + update \logical_op__rc__rc $1\logical_op__rc__rc[0:0] + end + attribute \src "libresoc.v:159578.7-159578.35" + process $proc$libresoc.v:159578$9680 + assign { } { } + assign $1\logical_op__write_cr0[0:0] 1'0 + sync always + sync init + update \logical_op__write_cr0 $1\logical_op__write_cr0[0:0] + end + attribute \src "libresoc.v:159587.7-159587.32" + process $proc$libresoc.v:159587$9681 + assign { } { } + assign $1\logical_op__zero_a[0:0] 1'0 + sync always + sync init + update \logical_op__zero_a $1\logical_op__zero_a[0:0] + end + attribute \src "libresoc.v:159596.13-159596.25" + process $proc$libresoc.v:159596$9682 + assign { } { } + assign $1\muxid[1:0] 2'00 + sync always + sync init + update \muxid $1\muxid[1:0] + end + attribute \src "libresoc.v:159611.13-159611.29" + process $proc$libresoc.v:159611$9683 + assign { } { } + assign $1\operation[1:0] 2'00 + sync always + sync init + update \operation $1\operation[1:0] + end + attribute \src "libresoc.v:159625.7-159625.20" + process $proc$libresoc.v:159625$9684 + assign { } { } + assign $1\r_busy[0:0] 1'0 + sync always + sync init + update \r_busy $1\r_busy[0:0] + end + attribute \src "libresoc.v:159630.14-159630.39" + process $proc$libresoc.v:159630$9685 + assign { } { } + assign $1\ra[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \ra $1\ra[63:0] + end + attribute \src "libresoc.v:159641.14-159641.39" + process $proc$libresoc.v:159641$9686 + assign { } { } + assign $1\rb[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \rb $1\rb[63:0] + end + attribute \src "libresoc.v:159934.7-159934.20" + process $proc$libresoc.v:159934$9687 + assign { } { } + assign $1\xer_so[0:0] 1'0 + sync always + sync init + update \xer_so $1\xer_so[0:0] + end + attribute \src "libresoc.v:159942.3-159943.35" + process $proc$libresoc.v:159942$9542 + assign { } { } + assign $0\operation[1:0] \operation$next + sync posedge \coresync_clk + update \operation $0\operation[1:0] + end + attribute \src "libresoc.v:159944.3-159945.49" + process $proc$libresoc.v:159944$9543 + assign { } { } + assign $0\divisor_radicand[63:0] \divisor_radicand$next + sync posedge \coresync_clk + update \divisor_radicand $0\divisor_radicand[63:0] + end + attribute \src "libresoc.v:159946.3-159947.33" + process $proc$libresoc.v:159946$9544 + assign { } { } + assign $0\dividend[127:0] \dividend$next + sync posedge \coresync_clk + update \dividend $0\dividend[127:0] + end + attribute \src "libresoc.v:159948.3-159949.39" + process $proc$libresoc.v:159948$9545 + assign { } { } + assign $0\div_by_zero[0:0] \div_by_zero$next + sync posedge \coresync_clk + update \div_by_zero $0\div_by_zero[0:0] + end + attribute \src "libresoc.v:159950.3-159951.43" + process $proc$libresoc.v:159950$9546 + assign { } { } + assign $0\dive_abs_ov64[0:0] \dive_abs_ov64$next + sync posedge \coresync_clk + update \dive_abs_ov64 $0\dive_abs_ov64[0:0] + end + attribute \src "libresoc.v:159952.3-159953.43" + process $proc$libresoc.v:159952$9547 + assign { } { } + assign $0\dive_abs_ov32[0:0] \dive_abs_ov32$next + sync posedge \coresync_clk + update \dive_abs_ov32 $0\dive_abs_ov32[0:0] + end + attribute \src "libresoc.v:159954.3-159955.41" + process $proc$libresoc.v:159954$9548 + assign { } { } + assign $0\dividend_neg[0:0] \dividend_neg$next + sync posedge \coresync_clk + update \dividend_neg $0\dividend_neg[0:0] + end + attribute \src "libresoc.v:159956.3-159957.39" + process $proc$libresoc.v:159956$9549 + assign { } { } + assign $0\divisor_neg[0:0] \divisor_neg$next + sync posedge \coresync_clk + update \divisor_neg $0\divisor_neg[0:0] + end + attribute \src "libresoc.v:159958.3-159959.29" + process $proc$libresoc.v:159958$9550 + assign { } { } + assign $0\xer_so[0:0] \xer_so$next + sync posedge \coresync_clk + update \xer_so $0\xer_so[0:0] + end + attribute \src "libresoc.v:159960.3-159961.21" + process $proc$libresoc.v:159960$9551 + assign { } { } + assign $0\rb[63:0] \rb$next + sync posedge \coresync_clk + update \rb $0\rb[63:0] + end + attribute \src "libresoc.v:159962.3-159963.21" + process $proc$libresoc.v:159962$9552 + assign { } { } + assign $0\ra[63:0] \ra$next + sync posedge \coresync_clk + update \ra $0\ra[63:0] + end + attribute \src "libresoc.v:159964.3-159965.59" + process $proc$libresoc.v:159964$9553 + assign { } { } + assign $0\logical_op__insn_type[6:0] \logical_op__insn_type$next + sync posedge \coresync_clk + update \logical_op__insn_type $0\logical_op__insn_type[6:0] + end + attribute \src "libresoc.v:159966.3-159967.55" + process $proc$libresoc.v:159966$9554 + assign { } { } + assign $0\logical_op__fn_unit[11:0] \logical_op__fn_unit$next + sync posedge \coresync_clk + update \logical_op__fn_unit $0\logical_op__fn_unit[11:0] + end + attribute \src "libresoc.v:159968.3-159969.69" + process $proc$libresoc.v:159968$9555 + assign { } { } + assign $0\logical_op__imm_data__data[63:0] \logical_op__imm_data__data$next + sync posedge \coresync_clk + update \logical_op__imm_data__data $0\logical_op__imm_data__data[63:0] + end + attribute \src "libresoc.v:159970.3-159971.65" + process $proc$libresoc.v:159970$9556 + assign { } { } + assign $0\logical_op__imm_data__ok[0:0] \logical_op__imm_data__ok$next + sync posedge \coresync_clk + update \logical_op__imm_data__ok $0\logical_op__imm_data__ok[0:0] + end + attribute \src "libresoc.v:159972.3-159973.53" + process $proc$libresoc.v:159972$9557 + assign { } { } + assign $0\logical_op__rc__rc[0:0] \logical_op__rc__rc$next + sync posedge \coresync_clk + update \logical_op__rc__rc $0\logical_op__rc__rc[0:0] + end + attribute \src "libresoc.v:159974.3-159975.53" + process $proc$libresoc.v:159974$9558 + assign { } { } + assign $0\logical_op__rc__ok[0:0] \logical_op__rc__ok$next + sync posedge \coresync_clk + update \logical_op__rc__ok $0\logical_op__rc__ok[0:0] + end + attribute \src "libresoc.v:159976.3-159977.53" + process $proc$libresoc.v:159976$9559 + assign { } { } + assign $0\logical_op__oe__oe[0:0] \logical_op__oe__oe$next + sync posedge \coresync_clk + update \logical_op__oe__oe $0\logical_op__oe__oe[0:0] + end + attribute \src "libresoc.v:159978.3-159979.53" + process $proc$libresoc.v:159978$9560 + assign { } { } + assign $0\logical_op__oe__ok[0:0] \logical_op__oe__ok$next + sync posedge \coresync_clk + update \logical_op__oe__ok $0\logical_op__oe__ok[0:0] + end + attribute \src "libresoc.v:159980.3-159981.59" + process $proc$libresoc.v:159980$9561 + assign { } { } + assign $0\logical_op__invert_in[0:0] \logical_op__invert_in$next + sync posedge \coresync_clk + update \logical_op__invert_in $0\logical_op__invert_in[0:0] + end + attribute \src "libresoc.v:159982.3-159983.53" + process $proc$libresoc.v:159982$9562 + assign { } { } + assign $0\logical_op__zero_a[0:0] \logical_op__zero_a$next + sync posedge \coresync_clk + update \logical_op__zero_a $0\logical_op__zero_a[0:0] + end + attribute \src "libresoc.v:159984.3-159985.63" + process $proc$libresoc.v:159984$9563 + assign { } { } + assign $0\logical_op__input_carry[1:0] \logical_op__input_carry$next + sync posedge \coresync_clk + update \logical_op__input_carry $0\logical_op__input_carry[1:0] + end + attribute \src "libresoc.v:159986.3-159987.61" + process $proc$libresoc.v:159986$9564 + assign { } { } + assign $0\logical_op__invert_out[0:0] \logical_op__invert_out$next + sync posedge \coresync_clk + update \logical_op__invert_out $0\logical_op__invert_out[0:0] + end + attribute \src "libresoc.v:159988.3-159989.59" + process $proc$libresoc.v:159988$9565 + assign { } { } + assign $0\logical_op__write_cr0[0:0] \logical_op__write_cr0$next + sync posedge \coresync_clk + update \logical_op__write_cr0 $0\logical_op__write_cr0[0:0] + end + attribute \src "libresoc.v:159990.3-159991.65" + process $proc$libresoc.v:159990$9566 + assign { } { } + assign $0\logical_op__output_carry[0:0] \logical_op__output_carry$next + sync posedge \coresync_clk + update \logical_op__output_carry $0\logical_op__output_carry[0:0] + end + attribute \src "libresoc.v:159992.3-159993.57" + process $proc$libresoc.v:159992$9567 + assign { } { } + assign $0\logical_op__is_32bit[0:0] \logical_op__is_32bit$next + sync posedge \coresync_clk + update \logical_op__is_32bit $0\logical_op__is_32bit[0:0] + end + attribute \src "libresoc.v:159994.3-159995.59" + process $proc$libresoc.v:159994$9568 + assign { } { } + assign $0\logical_op__is_signed[0:0] \logical_op__is_signed$next + sync posedge \coresync_clk + update \logical_op__is_signed $0\logical_op__is_signed[0:0] + end + attribute \src "libresoc.v:159996.3-159997.57" + process $proc$libresoc.v:159996$9569 + assign { } { } + assign $0\logical_op__data_len[3:0] \logical_op__data_len$next + sync posedge \coresync_clk + update \logical_op__data_len $0\logical_op__data_len[3:0] + end + attribute \src "libresoc.v:159998.3-159999.49" + process $proc$libresoc.v:159998$9570 + assign { } { } + assign $0\logical_op__insn[31:0] \logical_op__insn$next + sync posedge \coresync_clk + update \logical_op__insn $0\logical_op__insn[31:0] + end + attribute \src "libresoc.v:160000.3-160001.27" + process $proc$libresoc.v:160000$9571 + assign { } { } + assign $0\muxid[1:0] \muxid$next + sync posedge \coresync_clk + update \muxid $0\muxid[1:0] + end + attribute \src "libresoc.v:160002.3-160003.29" + process $proc$libresoc.v:160002$9572 + assign { } { } + assign $0\r_busy[0:0] \r_busy$next + sync posedge \coresync_clk + update \r_busy $0\r_busy[0:0] + end + attribute \src "libresoc.v:160110.3-160122.6" + process $proc$libresoc.v:160110$9573 + assign { } { } + assign { } { } + assign $0\divisor_neg$next[0:0]$9574 $1\divisor_neg$next[0:0]$9575 + attribute \src "libresoc.v:160111.5-160111.29" + switch \initial + attribute \src "libresoc.v:160111.9-160111.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\divisor_neg$next[0:0]$9575 \divisor_neg$92 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\divisor_neg$next[0:0]$9575 \divisor_neg$92 + case + assign $1\divisor_neg$next[0:0]$9575 \divisor_neg + end + sync always + update \divisor_neg$next $0\divisor_neg$next[0:0]$9574 + end + attribute \src "libresoc.v:160123.3-160135.6" + process $proc$libresoc.v:160123$9576 + assign { } { } + assign { } { } + assign $0\dividend_neg$next[0:0]$9577 $1\dividend_neg$next[0:0]$9578 + attribute \src "libresoc.v:160124.5-160124.29" + switch \initial + attribute \src "libresoc.v:160124.9-160124.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\dividend_neg$next[0:0]$9578 \dividend_neg$93 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\dividend_neg$next[0:0]$9578 \dividend_neg$93 + case + assign $1\dividend_neg$next[0:0]$9578 \dividend_neg + end + sync always + update \dividend_neg$next $0\dividend_neg$next[0:0]$9577 + end + attribute \src "libresoc.v:160136.3-160148.6" + process $proc$libresoc.v:160136$9579 + assign { } { } + assign { } { } + assign $0\dive_abs_ov32$next[0:0]$9580 $1\dive_abs_ov32$next[0:0]$9581 + attribute \src "libresoc.v:160137.5-160137.29" + switch \initial + attribute \src "libresoc.v:160137.9-160137.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\dive_abs_ov32$next[0:0]$9581 \dive_abs_ov32$94 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\dive_abs_ov32$next[0:0]$9581 \dive_abs_ov32$94 + case + assign $1\dive_abs_ov32$next[0:0]$9581 \dive_abs_ov32 + end + sync always + update \dive_abs_ov32$next $0\dive_abs_ov32$next[0:0]$9580 + end + attribute \src "libresoc.v:160149.3-160161.6" + process $proc$libresoc.v:160149$9582 + assign { } { } + assign { } { } + assign $0\dive_abs_ov64$next[0:0]$9583 $1\dive_abs_ov64$next[0:0]$9584 + attribute \src "libresoc.v:160150.5-160150.29" + switch \initial + attribute \src "libresoc.v:160150.9-160150.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\dive_abs_ov64$next[0:0]$9584 \dive_abs_ov64$95 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\dive_abs_ov64$next[0:0]$9584 \dive_abs_ov64$95 + case + assign $1\dive_abs_ov64$next[0:0]$9584 \dive_abs_ov64 + end + sync always + update \dive_abs_ov64$next $0\dive_abs_ov64$next[0:0]$9583 + end + attribute \src "libresoc.v:160162.3-160174.6" + process $proc$libresoc.v:160162$9585 + assign { } { } + assign { } { } + assign $0\div_by_zero$next[0:0]$9586 $1\div_by_zero$next[0:0]$9587 + attribute \src "libresoc.v:160163.5-160163.29" + switch \initial + attribute \src "libresoc.v:160163.9-160163.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\div_by_zero$next[0:0]$9587 \div_by_zero$96 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\div_by_zero$next[0:0]$9587 \div_by_zero$96 + case + assign $1\div_by_zero$next[0:0]$9587 \div_by_zero + end + sync always + update \div_by_zero$next $0\div_by_zero$next[0:0]$9586 + end + attribute \src "libresoc.v:160175.3-160187.6" + process $proc$libresoc.v:160175$9588 + assign { } { } + assign { } { } + assign $0\dividend$next[127:0]$9589 $1\dividend$next[127:0]$9590 + attribute \src "libresoc.v:160176.5-160176.29" + switch \initial + attribute \src "libresoc.v:160176.9-160176.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\dividend$next[127:0]$9590 \dividend$97 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\dividend$next[127:0]$9590 \dividend$97 + case + assign $1\dividend$next[127:0]$9590 \dividend + end + sync always + update \dividend$next $0\dividend$next[127:0]$9589 + end + attribute \src "libresoc.v:160188.3-160200.6" + process $proc$libresoc.v:160188$9591 + assign { } { } + assign { } { } + assign $0\divisor_radicand$next[63:0]$9592 $1\divisor_radicand$next[63:0]$9593 + attribute \src "libresoc.v:160189.5-160189.29" + switch \initial + attribute \src "libresoc.v:160189.9-160189.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\divisor_radicand$next[63:0]$9593 \divisor_radicand$98 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\divisor_radicand$next[63:0]$9593 \divisor_radicand$98 + case + assign $1\divisor_radicand$next[63:0]$9593 \divisor_radicand + end + sync always + update \divisor_radicand$next $0\divisor_radicand$next[63:0]$9592 + end + attribute \src "libresoc.v:160201.3-160213.6" + process $proc$libresoc.v:160201$9594 + assign { } { } + assign { } { } + assign $0\operation$next[1:0]$9595 $1\operation$next[1:0]$9596 + attribute \src "libresoc.v:160202.5-160202.29" + switch \initial + attribute \src "libresoc.v:160202.9-160202.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\operation$next[1:0]$9596 \operation$99 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\operation$next[1:0]$9596 \operation$99 + case + assign $1\operation$next[1:0]$9596 \operation + end + sync always + update \operation$next $0\operation$next[1:0]$9595 + end + attribute \src "libresoc.v:160214.3-160231.6" + process $proc$libresoc.v:160214$9597 + assign { } { } + assign { } { } + assign { } { } + assign $0\r_busy$next[0:0]$9598 $2\r_busy$next[0:0]$9600 + attribute \src "libresoc.v:160215.5-160215.29" + switch \initial + attribute \src "libresoc.v:160215.9-160215.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\r_busy$next[0:0]$9599 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\r_busy$next[0:0]$9599 1'0 + case + assign $1\r_busy$next[0:0]$9599 \r_busy + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r_busy$next[0:0]$9600 1'0 + case + assign $2\r_busy$next[0:0]$9600 $1\r_busy$next[0:0]$9599 + end + sync always + update \r_busy$next $0\r_busy$next[0:0]$9598 + end + attribute \src "libresoc.v:160232.3-160244.6" + process $proc$libresoc.v:160232$9601 + assign { } { } + assign { } { } + assign $0\muxid$next[1:0]$9602 $1\muxid$next[1:0]$9603 + attribute \src "libresoc.v:160233.5-160233.29" + switch \initial + attribute \src "libresoc.v:160233.9-160233.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\muxid$next[1:0]$9603 \muxid$68 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\muxid$next[1:0]$9603 \muxid$68 + case + assign $1\muxid$next[1:0]$9603 \muxid + end + sync always + update \muxid$next $0\muxid$next[1:0]$9602 + end + attribute \src "libresoc.v:160245.3-160286.6" + process $proc$libresoc.v:160245$9604 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\logical_op__data_len$next[3:0]$9605 $1\logical_op__data_len$next[3:0]$9623 + assign $0\logical_op__fn_unit$next[11:0]$9606 $1\logical_op__fn_unit$next[11:0]$9624 + assign { } { } + assign { } { } + assign $0\logical_op__input_carry$next[1:0]$9609 $1\logical_op__input_carry$next[1:0]$9627 + assign $0\logical_op__insn$next[31:0]$9610 $1\logical_op__insn$next[31:0]$9628 + assign $0\logical_op__insn_type$next[6:0]$9611 $1\logical_op__insn_type$next[6:0]$9629 + assign $0\logical_op__invert_in$next[0:0]$9612 $1\logical_op__invert_in$next[0:0]$9630 + assign $0\logical_op__invert_out$next[0:0]$9613 $1\logical_op__invert_out$next[0:0]$9631 + assign $0\logical_op__is_32bit$next[0:0]$9614 $1\logical_op__is_32bit$next[0:0]$9632 + assign $0\logical_op__is_signed$next[0:0]$9615 $1\logical_op__is_signed$next[0:0]$9633 + assign { } { } + assign { } { } + assign $0\logical_op__output_carry$next[0:0]$9618 $1\logical_op__output_carry$next[0:0]$9636 + assign { } { } + assign { } { } + assign $0\logical_op__write_cr0$next[0:0]$9621 $1\logical_op__write_cr0$next[0:0]$9639 + assign $0\logical_op__zero_a$next[0:0]$9622 $1\logical_op__zero_a$next[0:0]$9640 + assign $0\logical_op__imm_data__data$next[63:0]$9607 $2\logical_op__imm_data__data$next[63:0]$9641 + assign $0\logical_op__imm_data__ok$next[0:0]$9608 $2\logical_op__imm_data__ok$next[0:0]$9642 + assign $0\logical_op__oe__oe$next[0:0]$9616 $2\logical_op__oe__oe$next[0:0]$9643 + assign $0\logical_op__oe__ok$next[0:0]$9617 $2\logical_op__oe__ok$next[0:0]$9644 + assign $0\logical_op__rc__ok$next[0:0]$9619 $2\logical_op__rc__ok$next[0:0]$9645 + assign $0\logical_op__rc__rc$next[0:0]$9620 $2\logical_op__rc__rc$next[0:0]$9646 + attribute \src "libresoc.v:160246.5-160246.29" + switch \initial + attribute \src "libresoc.v:160246.9-160246.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\logical_op__insn$next[31:0]$9628 $1\logical_op__data_len$next[3:0]$9623 $1\logical_op__is_signed$next[0:0]$9633 $1\logical_op__is_32bit$next[0:0]$9632 $1\logical_op__output_carry$next[0:0]$9636 $1\logical_op__write_cr0$next[0:0]$9639 $1\logical_op__invert_out$next[0:0]$9631 $1\logical_op__input_carry$next[1:0]$9627 $1\logical_op__zero_a$next[0:0]$9640 $1\logical_op__invert_in$next[0:0]$9630 $1\logical_op__oe__ok$next[0:0]$9635 $1\logical_op__oe__oe$next[0:0]$9634 $1\logical_op__rc__ok$next[0:0]$9637 $1\logical_op__rc__rc$next[0:0]$9638 $1\logical_op__imm_data__ok$next[0:0]$9626 $1\logical_op__imm_data__data$next[63:0]$9625 $1\logical_op__fn_unit$next[11:0]$9624 $1\logical_op__insn_type$next[6:0]$9629 } { \logical_op__insn$86 \logical_op__data_len$85 \logical_op__is_signed$84 \logical_op__is_32bit$83 \logical_op__output_carry$82 \logical_op__write_cr0$81 \logical_op__invert_out$80 \logical_op__input_carry$79 \logical_op__zero_a$78 \logical_op__invert_in$77 \logical_op__oe__ok$76 \logical_op__oe__oe$75 \logical_op__rc__ok$74 \logical_op__rc__rc$73 \logical_op__imm_data__ok$72 \logical_op__imm_data__data$71 \logical_op__fn_unit$70 \logical_op__insn_type$69 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\logical_op__insn$next[31:0]$9628 $1\logical_op__data_len$next[3:0]$9623 $1\logical_op__is_signed$next[0:0]$9633 $1\logical_op__is_32bit$next[0:0]$9632 $1\logical_op__output_carry$next[0:0]$9636 $1\logical_op__write_cr0$next[0:0]$9639 $1\logical_op__invert_out$next[0:0]$9631 $1\logical_op__input_carry$next[1:0]$9627 $1\logical_op__zero_a$next[0:0]$9640 $1\logical_op__invert_in$next[0:0]$9630 $1\logical_op__oe__ok$next[0:0]$9635 $1\logical_op__oe__oe$next[0:0]$9634 $1\logical_op__rc__ok$next[0:0]$9637 $1\logical_op__rc__rc$next[0:0]$9638 $1\logical_op__imm_data__ok$next[0:0]$9626 $1\logical_op__imm_data__data$next[63:0]$9625 $1\logical_op__fn_unit$next[11:0]$9624 $1\logical_op__insn_type$next[6:0]$9629 } { \logical_op__insn$86 \logical_op__data_len$85 \logical_op__is_signed$84 \logical_op__is_32bit$83 \logical_op__output_carry$82 \logical_op__write_cr0$81 \logical_op__invert_out$80 \logical_op__input_carry$79 \logical_op__zero_a$78 \logical_op__invert_in$77 \logical_op__oe__ok$76 \logical_op__oe__oe$75 \logical_op__rc__ok$74 \logical_op__rc__rc$73 \logical_op__imm_data__ok$72 \logical_op__imm_data__data$71 \logical_op__fn_unit$70 \logical_op__insn_type$69 } + case + assign $1\logical_op__data_len$next[3:0]$9623 \logical_op__data_len + assign $1\logical_op__fn_unit$next[11:0]$9624 \logical_op__fn_unit + assign $1\logical_op__imm_data__data$next[63:0]$9625 \logical_op__imm_data__data + assign $1\logical_op__imm_data__ok$next[0:0]$9626 \logical_op__imm_data__ok + assign $1\logical_op__input_carry$next[1:0]$9627 \logical_op__input_carry + assign $1\logical_op__insn$next[31:0]$9628 \logical_op__insn + assign $1\logical_op__insn_type$next[6:0]$9629 \logical_op__insn_type + assign $1\logical_op__invert_in$next[0:0]$9630 \logical_op__invert_in + assign $1\logical_op__invert_out$next[0:0]$9631 \logical_op__invert_out + assign $1\logical_op__is_32bit$next[0:0]$9632 \logical_op__is_32bit + assign $1\logical_op__is_signed$next[0:0]$9633 \logical_op__is_signed + assign $1\logical_op__oe__oe$next[0:0]$9634 \logical_op__oe__oe + assign $1\logical_op__oe__ok$next[0:0]$9635 \logical_op__oe__ok + assign $1\logical_op__output_carry$next[0:0]$9636 \logical_op__output_carry + assign $1\logical_op__rc__ok$next[0:0]$9637 \logical_op__rc__ok + assign $1\logical_op__rc__rc$next[0:0]$9638 \logical_op__rc__rc + assign $1\logical_op__write_cr0$next[0:0]$9639 \logical_op__write_cr0 + assign $1\logical_op__zero_a$next[0:0]$9640 \logical_op__zero_a + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $2\logical_op__imm_data__data$next[63:0]$9641 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\logical_op__imm_data__ok$next[0:0]$9642 1'0 + assign $2\logical_op__rc__rc$next[0:0]$9646 1'0 + assign $2\logical_op__rc__ok$next[0:0]$9645 1'0 + assign $2\logical_op__oe__oe$next[0:0]$9643 1'0 + assign $2\logical_op__oe__ok$next[0:0]$9644 1'0 + case + assign $2\logical_op__imm_data__data$next[63:0]$9641 $1\logical_op__imm_data__data$next[63:0]$9625 + assign $2\logical_op__imm_data__ok$next[0:0]$9642 $1\logical_op__imm_data__ok$next[0:0]$9626 + assign $2\logical_op__oe__oe$next[0:0]$9643 $1\logical_op__oe__oe$next[0:0]$9634 + assign $2\logical_op__oe__ok$next[0:0]$9644 $1\logical_op__oe__ok$next[0:0]$9635 + assign $2\logical_op__rc__ok$next[0:0]$9645 $1\logical_op__rc__ok$next[0:0]$9637 + assign $2\logical_op__rc__rc$next[0:0]$9646 $1\logical_op__rc__rc$next[0:0]$9638 + end + sync always + update \logical_op__data_len$next $0\logical_op__data_len$next[3:0]$9605 + update \logical_op__fn_unit$next $0\logical_op__fn_unit$next[11:0]$9606 + update \logical_op__imm_data__data$next $0\logical_op__imm_data__data$next[63:0]$9607 + update \logical_op__imm_data__ok$next $0\logical_op__imm_data__ok$next[0:0]$9608 + update \logical_op__input_carry$next $0\logical_op__input_carry$next[1:0]$9609 + update \logical_op__insn$next $0\logical_op__insn$next[31:0]$9610 + update \logical_op__insn_type$next $0\logical_op__insn_type$next[6:0]$9611 + update \logical_op__invert_in$next $0\logical_op__invert_in$next[0:0]$9612 + update \logical_op__invert_out$next $0\logical_op__invert_out$next[0:0]$9613 + update \logical_op__is_32bit$next $0\logical_op__is_32bit$next[0:0]$9614 + update \logical_op__is_signed$next $0\logical_op__is_signed$next[0:0]$9615 + update \logical_op__oe__oe$next $0\logical_op__oe__oe$next[0:0]$9616 + update \logical_op__oe__ok$next $0\logical_op__oe__ok$next[0:0]$9617 + update \logical_op__output_carry$next $0\logical_op__output_carry$next[0:0]$9618 + update \logical_op__rc__ok$next $0\logical_op__rc__ok$next[0:0]$9619 + update \logical_op__rc__rc$next $0\logical_op__rc__rc$next[0:0]$9620 + update \logical_op__write_cr0$next $0\logical_op__write_cr0$next[0:0]$9621 + update \logical_op__zero_a$next $0\logical_op__zero_a$next[0:0]$9622 + end + attribute \src "libresoc.v:160287.3-160299.6" + process $proc$libresoc.v:160287$9647 + assign { } { } + assign { } { } + assign $0\ra$next[63:0]$9648 $1\ra$next[63:0]$9649 + attribute \src "libresoc.v:160288.5-160288.29" + switch \initial + attribute \src "libresoc.v:160288.9-160288.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\ra$next[63:0]$9649 \ra$87 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\ra$next[63:0]$9649 \ra$87 + case + assign $1\ra$next[63:0]$9649 \ra + end + sync always + update \ra$next $0\ra$next[63:0]$9648 + end + attribute \src "libresoc.v:160300.3-160312.6" + process $proc$libresoc.v:160300$9650 + assign { } { } + assign { } { } + assign $0\rb$next[63:0]$9651 $1\rb$next[63:0]$9652 + attribute \src "libresoc.v:160301.5-160301.29" + switch \initial + attribute \src "libresoc.v:160301.9-160301.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\rb$next[63:0]$9652 \rb$89 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\rb$next[63:0]$9652 \rb$89 + case + assign $1\rb$next[63:0]$9652 \rb + end + sync always + update \rb$next $0\rb$next[63:0]$9651 + end + attribute \src "libresoc.v:160313.3-160325.6" + process $proc$libresoc.v:160313$9653 + assign { } { } + assign { } { } + assign $0\xer_so$next[0:0]$9654 $1\xer_so$next[0:0]$9655 + attribute \src "libresoc.v:160314.5-160314.29" + switch \initial + attribute \src "libresoc.v:160314.9-160314.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\xer_so$next[0:0]$9655 \xer_so$91 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\xer_so$next[0:0]$9655 \xer_so$91 + case + assign $1\xer_so$next[0:0]$9655 \xer_so + end + sync always + update \xer_so$next $0\xer_so$next[0:0]$9654 + end + connect \$66 $and$libresoc.v:159941$9541_Y + connect \ra$88 64'0000000000000000000000000000000000000000000000000000000000000000 + connect \rb$90 64'0000000000000000000000000000000000000000000000000000000000000000 + connect \p_ready_o \n_i_rdy_data + connect \n_valid_o \r_busy + connect \operation$99 \setup_stage_operation + connect \divisor_radicand$98 \setup_stage_divisor_radicand + connect \dividend$97 \setup_stage_dividend + connect \div_by_zero$96 \setup_stage_div_by_zero + connect \dive_abs_ov64$95 \setup_stage_dive_abs_ov64 + connect \dive_abs_ov32$94 \setup_stage_dive_abs_ov32 + connect \dividend_neg$93 \setup_stage_dividend_neg + connect \divisor_neg$92 \setup_stage_divisor_neg + connect \xer_so$91 \setup_stage_xer_so$64 + connect \rb$89 64'0000000000000000000000000000000000000000000000000000000000000000 + connect \ra$87 64'0000000000000000000000000000000000000000000000000000000000000000 + connect { \logical_op__insn$86 \logical_op__data_len$85 \logical_op__is_signed$84 \logical_op__is_32bit$83 \logical_op__output_carry$82 \logical_op__write_cr0$81 \logical_op__invert_out$80 \logical_op__input_carry$79 \logical_op__zero_a$78 \logical_op__invert_in$77 \logical_op__oe__ok$76 \logical_op__oe__oe$75 \logical_op__rc__ok$74 \logical_op__rc__rc$73 \logical_op__imm_data__ok$72 \logical_op__imm_data__data$71 \logical_op__fn_unit$70 \logical_op__insn_type$69 } { \setup_stage_logical_op__insn$63 \setup_stage_logical_op__data_len$62 \setup_stage_logical_op__is_signed$61 \setup_stage_logical_op__is_32bit$60 \setup_stage_logical_op__output_carry$59 \setup_stage_logical_op__write_cr0$58 \setup_stage_logical_op__invert_out$57 \setup_stage_logical_op__input_carry$56 \setup_stage_logical_op__zero_a$55 \setup_stage_logical_op__invert_in$54 \setup_stage_logical_op__oe__ok$53 \setup_stage_logical_op__oe__oe$52 \setup_stage_logical_op__rc__ok$51 \setup_stage_logical_op__rc__rc$50 \setup_stage_logical_op__imm_data__ok$49 \setup_stage_logical_op__imm_data__data$48 \setup_stage_logical_op__fn_unit$47 \setup_stage_logical_op__insn_type$46 } + connect \muxid$68 \setup_stage_muxid$45 + connect \p_valid_i_p_ready_o \$66 + connect \n_i_rdy_data \n_ready_i + connect \p_valid_i$65 \p_valid_i + connect \setup_stage_xer_so \input_xer_so$44 + connect \setup_stage_rb \input_rb$43 + connect \setup_stage_ra \input_ra$42 + connect { \setup_stage_logical_op__insn \setup_stage_logical_op__data_len \setup_stage_logical_op__is_signed \setup_stage_logical_op__is_32bit \setup_stage_logical_op__output_carry \setup_stage_logical_op__write_cr0 \setup_stage_logical_op__invert_out \setup_stage_logical_op__input_carry \setup_stage_logical_op__zero_a \setup_stage_logical_op__invert_in \setup_stage_logical_op__oe__ok \setup_stage_logical_op__oe__oe \setup_stage_logical_op__rc__ok \setup_stage_logical_op__rc__rc \setup_stage_logical_op__imm_data__ok \setup_stage_logical_op__imm_data__data \setup_stage_logical_op__fn_unit \setup_stage_logical_op__insn_type } { \input_logical_op__insn$41 \input_logical_op__data_len$40 \input_logical_op__is_signed$39 \input_logical_op__is_32bit$38 \input_logical_op__output_carry$37 \input_logical_op__write_cr0$36 \input_logical_op__invert_out$35 \input_logical_op__input_carry$34 \input_logical_op__zero_a$33 \input_logical_op__invert_in$32 \input_logical_op__oe__ok$31 \input_logical_op__oe__oe$30 \input_logical_op__rc__ok$29 \input_logical_op__rc__rc$28 \input_logical_op__imm_data__ok$27 \input_logical_op__imm_data__data$26 \input_logical_op__fn_unit$25 \input_logical_op__insn_type$24 } + connect \setup_stage_muxid \input_muxid$23 + connect \input_xer_so \xer_so$22 + connect \input_rb \rb$21 + connect \input_ra \ra$20 + connect { \input_logical_op__insn \input_logical_op__data_len \input_logical_op__is_signed \input_logical_op__is_32bit \input_logical_op__output_carry \input_logical_op__write_cr0 \input_logical_op__invert_out \input_logical_op__input_carry \input_logical_op__zero_a \input_logical_op__invert_in \input_logical_op__oe__ok \input_logical_op__oe__oe \input_logical_op__rc__ok \input_logical_op__rc__rc \input_logical_op__imm_data__ok \input_logical_op__imm_data__data \input_logical_op__fn_unit \input_logical_op__insn_type } { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } + connect \input_muxid \muxid$1 +end +attribute \src "libresoc.v:160360.1-161002.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_logical0.logical_pipe1.main.popcount" +attribute \generator "nMigen" +module \popcount + attribute \src "libresoc.v:160361.7-160361.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:160849.3-160875.6" + wire width 64 $0\o[63:0] + attribute \src "libresoc.v:160849.3-160875.6" + wire width 64 $1\o[63:0] + attribute \src "libresoc.v:160773.19-160773.132" + wire width 4 $add$libresoc.v:160773$9688_Y + attribute \src "libresoc.v:160774.19-160774.132" + wire width 4 $add$libresoc.v:160774$9689_Y + attribute \src "libresoc.v:160775.19-160775.132" + wire width 4 $add$libresoc.v:160775$9690_Y + attribute \src "libresoc.v:160776.19-160776.132" + wire width 4 $add$libresoc.v:160776$9691_Y + attribute \src "libresoc.v:160777.19-160777.134" + wire width 4 $add$libresoc.v:160777$9692_Y + attribute \src "libresoc.v:160778.19-160778.134" + wire width 4 $add$libresoc.v:160778$9693_Y + attribute \src "libresoc.v:160779.18-160779.125" + wire width 3 $add$libresoc.v:160779$9694_Y + attribute \src "libresoc.v:160780.19-160780.134" + wire width 4 $add$libresoc.v:160780$9695_Y + attribute \src "libresoc.v:160781.19-160781.134" + wire width 4 $add$libresoc.v:160781$9696_Y + attribute \src "libresoc.v:160782.19-160782.134" + wire width 4 $add$libresoc.v:160782$9697_Y + attribute \src "libresoc.v:160783.19-160783.134" + wire width 4 $add$libresoc.v:160783$9698_Y + attribute \src "libresoc.v:160784.19-160784.134" + wire width 4 $add$libresoc.v:160784$9699_Y + attribute \src "libresoc.v:160785.19-160785.134" + wire width 4 $add$libresoc.v:160785$9700_Y + attribute \src "libresoc.v:160786.19-160786.134" + wire width 4 $add$libresoc.v:160786$9701_Y + attribute \src "libresoc.v:160787.19-160787.134" + wire width 4 $add$libresoc.v:160787$9702_Y + attribute \src "libresoc.v:160788.19-160788.134" + wire width 4 $add$libresoc.v:160788$9703_Y + attribute \src "libresoc.v:160789.19-160789.132" + wire width 5 $add$libresoc.v:160789$9704_Y + attribute \src "libresoc.v:160790.18-160790.125" + wire width 3 $add$libresoc.v:160790$9705_Y + attribute \src "libresoc.v:160791.19-160791.132" + wire width 5 $add$libresoc.v:160791$9706_Y + attribute \src "libresoc.v:160792.19-160792.132" + wire width 5 $add$libresoc.v:160792$9707_Y + attribute \src "libresoc.v:160793.19-160793.132" + wire width 5 $add$libresoc.v:160793$9708_Y + attribute \src "libresoc.v:160794.19-160794.132" + wire width 5 $add$libresoc.v:160794$9709_Y + attribute \src "libresoc.v:160795.19-160795.134" + wire width 5 $add$libresoc.v:160795$9710_Y + attribute \src "libresoc.v:160796.19-160796.134" + wire width 5 $add$libresoc.v:160796$9711_Y + attribute \src "libresoc.v:160797.19-160797.134" + wire width 5 $add$libresoc.v:160797$9712_Y + attribute \src "libresoc.v:160798.19-160798.132" + wire width 6 $add$libresoc.v:160798$9713_Y + attribute \src "libresoc.v:160799.19-160799.132" + wire width 6 $add$libresoc.v:160799$9714_Y + attribute \src "libresoc.v:160800.19-160800.132" + wire width 6 $add$libresoc.v:160800$9715_Y + attribute \src "libresoc.v:160801.18-160801.127" + wire width 3 $add$libresoc.v:160801$9716_Y + attribute \src "libresoc.v:160802.19-160802.132" + wire width 6 $add$libresoc.v:160802$9717_Y + attribute \src "libresoc.v:160803.19-160803.132" + wire width 7 $add$libresoc.v:160803$9718_Y + attribute \src "libresoc.v:160804.19-160804.132" + wire width 7 $add$libresoc.v:160804$9719_Y + attribute \src "libresoc.v:160805.19-160805.132" + wire width 8 $add$libresoc.v:160805$9720_Y + attribute \src "libresoc.v:160816.18-160816.127" + wire width 3 $add$libresoc.v:160816$9739_Y + attribute \src "libresoc.v:160820.18-160820.127" + wire width 3 $add$libresoc.v:160820$9746_Y + attribute \src "libresoc.v:160821.18-160821.127" + wire width 3 $add$libresoc.v:160821$9747_Y + attribute \src "libresoc.v:160822.17-160822.124" + wire width 3 $add$libresoc.v:160822$9748_Y + attribute \src "libresoc.v:160823.18-160823.127" + wire width 3 $add$libresoc.v:160823$9749_Y + attribute \src "libresoc.v:160824.18-160824.127" + wire width 3 $add$libresoc.v:160824$9750_Y + attribute \src "libresoc.v:160825.18-160825.127" + wire width 3 $add$libresoc.v:160825$9751_Y + attribute \src "libresoc.v:160826.18-160826.127" + wire width 3 $add$libresoc.v:160826$9752_Y + attribute \src "libresoc.v:160827.18-160827.127" + wire width 3 $add$libresoc.v:160827$9753_Y + attribute \src "libresoc.v:160828.18-160828.127" + wire width 3 $add$libresoc.v:160828$9754_Y + attribute \src "libresoc.v:160829.18-160829.127" + wire width 3 $add$libresoc.v:160829$9755_Y + attribute \src "libresoc.v:160830.18-160830.127" + wire width 3 $add$libresoc.v:160830$9756_Y + attribute \src "libresoc.v:160831.18-160831.127" + wire width 3 $add$libresoc.v:160831$9757_Y + attribute \src "libresoc.v:160832.18-160832.127" + wire width 3 $add$libresoc.v:160832$9758_Y + attribute \src "libresoc.v:160833.17-160833.124" + wire width 3 $add$libresoc.v:160833$9759_Y + attribute \src "libresoc.v:160834.18-160834.127" + wire width 3 $add$libresoc.v:160834$9760_Y + attribute \src "libresoc.v:160835.18-160835.127" + wire width 3 $add$libresoc.v:160835$9761_Y + attribute \src "libresoc.v:160836.18-160836.127" + wire width 3 $add$libresoc.v:160836$9762_Y + attribute \src "libresoc.v:160837.18-160837.127" + wire width 3 $add$libresoc.v:160837$9763_Y + attribute \src "libresoc.v:160838.18-160838.127" + wire width 3 $add$libresoc.v:160838$9764_Y + attribute \src "libresoc.v:160839.18-160839.127" + wire width 3 $add$libresoc.v:160839$9765_Y + attribute \src "libresoc.v:160840.18-160840.127" + wire width 3 $add$libresoc.v:160840$9766_Y + attribute \src "libresoc.v:160841.18-160841.127" + wire width 3 $add$libresoc.v:160841$9767_Y + attribute \src "libresoc.v:160842.18-160842.127" + wire width 3 $add$libresoc.v:160842$9768_Y + attribute \src "libresoc.v:160843.18-160843.127" + wire width 3 $add$libresoc.v:160843$9769_Y + attribute \src "libresoc.v:160844.17-160844.124" + wire width 3 $add$libresoc.v:160844$9770_Y + attribute \src "libresoc.v:160845.18-160845.127" + wire width 3 $add$libresoc.v:160845$9771_Y + attribute \src "libresoc.v:160846.18-160846.127" + wire width 3 $add$libresoc.v:160846$9772_Y + attribute \src "libresoc.v:160847.18-160847.127" + wire width 3 $add$libresoc.v:160847$9773_Y + attribute \src "libresoc.v:160848.18-160848.131" + wire width 4 $add$libresoc.v:160848$9774_Y + attribute \src "libresoc.v:160806.19-160806.111" + wire $eq$libresoc.v:160806$9721_Y + attribute \src "libresoc.v:160807.19-160807.111" + wire $eq$libresoc.v:160807$9722_Y + attribute \src "libresoc.v:160808.19-160808.104" + wire width 8 $extend$libresoc.v:160808$9723_Y + attribute \src "libresoc.v:160809.19-160809.104" + wire width 8 $extend$libresoc.v:160809$9725_Y + attribute \src "libresoc.v:160810.19-160810.104" + wire width 8 $extend$libresoc.v:160810$9727_Y + attribute \src "libresoc.v:160811.19-160811.104" + wire width 8 $extend$libresoc.v:160811$9729_Y + attribute \src "libresoc.v:160812.19-160812.104" + wire width 8 $extend$libresoc.v:160812$9731_Y + attribute \src "libresoc.v:160813.19-160813.104" + wire width 8 $extend$libresoc.v:160813$9733_Y + attribute \src "libresoc.v:160814.19-160814.104" + wire width 8 $extend$libresoc.v:160814$9735_Y + attribute \src "libresoc.v:160815.19-160815.104" + wire width 8 $extend$libresoc.v:160815$9737_Y + attribute \src "libresoc.v:160817.19-160817.104" + wire width 32 $extend$libresoc.v:160817$9740_Y + attribute \src "libresoc.v:160818.19-160818.104" + wire width 32 $extend$libresoc.v:160818$9742_Y + attribute \src "libresoc.v:160819.19-160819.104" + wire width 64 $extend$libresoc.v:160819$9744_Y + attribute \src "libresoc.v:160808.19-160808.104" + wire width 8 $pos$libresoc.v:160808$9724_Y + attribute \src "libresoc.v:160809.19-160809.104" + wire width 8 $pos$libresoc.v:160809$9726_Y + attribute \src "libresoc.v:160810.19-160810.104" + wire width 8 $pos$libresoc.v:160810$9728_Y + attribute \src "libresoc.v:160811.19-160811.104" + wire width 8 $pos$libresoc.v:160811$9730_Y + attribute \src "libresoc.v:160812.19-160812.104" + wire width 8 $pos$libresoc.v:160812$9732_Y + attribute \src "libresoc.v:160813.19-160813.104" + wire width 8 $pos$libresoc.v:160813$9734_Y + attribute \src "libresoc.v:160814.19-160814.104" + wire width 8 $pos$libresoc.v:160814$9736_Y + attribute \src "libresoc.v:160815.19-160815.104" + wire width 8 $pos$libresoc.v:160815$9738_Y + attribute \src "libresoc.v:160817.19-160817.104" + wire width 32 $pos$libresoc.v:160817$9741_Y + attribute \src "libresoc.v:160818.19-160818.104" + wire width 32 $pos$libresoc.v:160818$9743_Y + attribute \src "libresoc.v:160819.19-160819.104" + wire width 64 $pos$libresoc.v:160819$9745_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 3 \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 3 \$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 4 \$100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 4 \$101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 4 \$103 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 4 \$104 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 4 \$106 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 4 \$107 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 4 \$109 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 3 \$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 4 \$110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 4 \$112 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 4 \$113 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 4 \$115 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 4 \$116 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 4 \$118 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 4 \$119 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 4 \$121 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 4 \$122 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 4 \$124 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 4 \$125 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 4 \$127 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 4 \$128 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 3 \$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 4 \$130 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 4 \$131 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 4 \$133 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 4 \$134 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 4 \$136 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 4 \$137 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 4 \$139 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 3 \$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 4 \$140 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 4 \$142 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 4 \$143 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 5 \$145 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 5 \$146 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 5 \$148 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 5 \$149 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 5 \$151 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 5 \$152 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 5 \$154 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 5 \$155 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 5 \$157 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 5 \$158 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 3 \$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 5 \$160 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 5 \$161 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 5 \$163 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 5 \$164 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 5 \$166 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 5 \$167 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 6 \$169 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 3 \$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 6 \$170 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 6 \$172 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 6 \$173 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 6 \$175 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 6 \$176 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 6 \$178 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 6 \$179 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 7 \$181 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 7 \$182 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 7 \$184 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 7 \$185 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 8 \$187 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 8 \$188 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 3 \$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:55" + wire \$190 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:59" + wire \$192 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 8 \$194 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 8 \$196 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 8 \$198 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 3 \$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 3 \$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 8 \$200 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 8 \$202 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 8 \$204 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 8 \$206 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 8 \$208 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 32 \$210 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 32 \$212 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 64 \$214 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 3 \$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 3 \$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 3 \$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 3 \$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 3 \$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 3 \$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 3 \$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 3 \$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 3 \$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 3 \$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 3 \$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 3 \$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 3 \$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 3 \$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 3 \$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 3 \$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 3 \$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 3 \$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 3 \$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 3 \$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 3 \$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 3 \$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 3 \$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 3 \$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 3 \$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 3 \$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 3 \$58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 3 \$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 3 \$61 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 3 \$62 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 3 \$64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 3 \$65 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 3 \$67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 3 \$68 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 3 \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 3 \$70 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 3 \$71 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 3 \$73 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 3 \$74 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 3 \$76 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 3 \$77 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 3 \$79 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 3 \$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 3 \$80 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 3 \$82 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 3 \$83 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 3 \$85 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 3 \$86 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 3 \$88 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 3 \$89 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 3 \$91 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 3 \$92 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 3 \$94 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 3 \$95 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 4 \$97 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 4 \$98 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:27" + wire width 64 input 3 \a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:29" + wire width 64 input 1 \data_len + attribute \src "libresoc.v:160361.7-160361.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:30" + wire width 64 output 2 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 2 \pop_2_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 2 \pop_2_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 2 \pop_2_10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 2 \pop_2_11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 2 \pop_2_12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 2 \pop_2_13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 2 \pop_2_14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 2 \pop_2_15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 2 \pop_2_16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 2 \pop_2_17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 2 \pop_2_18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 2 \pop_2_19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 2 \pop_2_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 2 \pop_2_20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 2 \pop_2_21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 2 \pop_2_22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 2 \pop_2_23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 2 \pop_2_24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 2 \pop_2_25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 2 \pop_2_26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 2 \pop_2_27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 2 \pop_2_28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 2 \pop_2_29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 2 \pop_2_3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 2 \pop_2_30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 2 \pop_2_31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 2 \pop_2_4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 2 \pop_2_5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 2 \pop_2_6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 2 \pop_2_7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 2 \pop_2_8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 2 \pop_2_9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 3 \pop_3_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 3 \pop_3_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 3 \pop_3_10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 3 \pop_3_11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 3 \pop_3_12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 3 \pop_3_13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 3 \pop_3_14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 3 \pop_3_15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 3 \pop_3_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 3 \pop_3_3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 3 \pop_3_4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 3 \pop_3_5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 3 \pop_3_6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 3 \pop_3_7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 3 \pop_3_8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 3 \pop_3_9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 4 \pop_4_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 4 \pop_4_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 4 \pop_4_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 4 \pop_4_3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 4 \pop_4_4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 4 \pop_4_5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 4 \pop_4_6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 4 \pop_4_7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 5 \pop_5_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 5 \pop_5_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 5 \pop_5_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 5 \pop_5_3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 6 \pop_6_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 6 \pop_6_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 7 \pop_7_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:160773$9688 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A { 2'00 \pop_2_2 } + connect \B { 2'00 \pop_2_3 } + connect \Y $add$libresoc.v:160773$9688_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:160774$9689 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A { 2'00 \pop_2_4 } + connect \B { 2'00 \pop_2_5 } + connect \Y $add$libresoc.v:160774$9689_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:160775$9690 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A { 2'00 \pop_2_6 } + connect \B { 2'00 \pop_2_7 } + connect \Y $add$libresoc.v:160775$9690_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:160776$9691 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A { 2'00 \pop_2_8 } + connect \B { 2'00 \pop_2_9 } + connect \Y $add$libresoc.v:160776$9691_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:160777$9692 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A { 2'00 \pop_2_10 } + connect \B { 2'00 \pop_2_11 } + connect \Y $add$libresoc.v:160777$9692_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:160778$9693 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A { 2'00 \pop_2_12 } + connect \B { 2'00 \pop_2_13 } + connect \Y $add$libresoc.v:160778$9693_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:160779$9694 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [6] } + connect \B { 2'00 \a [7] } + connect \Y $add$libresoc.v:160779$9694_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:160780$9695 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A { 2'00 \pop_2_14 } + connect \B { 2'00 \pop_2_15 } + connect \Y $add$libresoc.v:160780$9695_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:160781$9696 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A { 2'00 \pop_2_16 } + connect \B { 2'00 \pop_2_17 } + connect \Y $add$libresoc.v:160781$9696_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:160782$9697 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A { 2'00 \pop_2_18 } + connect \B { 2'00 \pop_2_19 } + connect \Y $add$libresoc.v:160782$9697_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:160783$9698 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A { 2'00 \pop_2_20 } + connect \B { 2'00 \pop_2_21 } + connect \Y $add$libresoc.v:160783$9698_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:160784$9699 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A { 2'00 \pop_2_22 } + connect \B { 2'00 \pop_2_23 } + connect \Y $add$libresoc.v:160784$9699_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:160785$9700 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A { 2'00 \pop_2_24 } + connect \B { 2'00 \pop_2_25 } + connect \Y $add$libresoc.v:160785$9700_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:160786$9701 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A { 2'00 \pop_2_26 } + connect \B { 2'00 \pop_2_27 } + connect \Y $add$libresoc.v:160786$9701_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:160787$9702 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A { 2'00 \pop_2_28 } + connect \B { 2'00 \pop_2_29 } + connect \Y $add$libresoc.v:160787$9702_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:160788$9703 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A { 2'00 \pop_2_30 } + connect \B { 2'00 \pop_2_31 } + connect \Y $add$libresoc.v:160788$9703_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:160789$9704 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A { 2'00 \pop_3_0 } + connect \B { 2'00 \pop_3_1 } + connect \Y $add$libresoc.v:160789$9704_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:160790$9705 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [8] } + connect \B { 2'00 \a [9] } + connect \Y $add$libresoc.v:160790$9705_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:160791$9706 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A { 2'00 \pop_3_2 } + connect \B { 2'00 \pop_3_3 } + connect \Y $add$libresoc.v:160791$9706_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:160792$9707 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A { 2'00 \pop_3_4 } + connect \B { 2'00 \pop_3_5 } + connect \Y $add$libresoc.v:160792$9707_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:160793$9708 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A { 2'00 \pop_3_6 } + connect \B { 2'00 \pop_3_7 } + connect \Y $add$libresoc.v:160793$9708_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:160794$9709 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A { 2'00 \pop_3_8 } + connect \B { 2'00 \pop_3_9 } + connect \Y $add$libresoc.v:160794$9709_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:160795$9710 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A { 2'00 \pop_3_10 } + connect \B { 2'00 \pop_3_11 } + connect \Y $add$libresoc.v:160795$9710_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:160796$9711 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A { 2'00 \pop_3_12 } + connect \B { 2'00 \pop_3_13 } + connect \Y $add$libresoc.v:160796$9711_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:160797$9712 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A { 2'00 \pop_3_14 } + connect \B { 2'00 \pop_3_15 } + connect \Y $add$libresoc.v:160797$9712_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:160798$9713 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A { 2'00 \pop_4_0 } + connect \B { 2'00 \pop_4_1 } + connect \Y $add$libresoc.v:160798$9713_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:160799$9714 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A { 2'00 \pop_4_2 } + connect \B { 2'00 \pop_4_3 } + connect \Y $add$libresoc.v:160799$9714_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:160800$9715 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A { 2'00 \pop_4_4 } + connect \B { 2'00 \pop_4_5 } + connect \Y $add$libresoc.v:160800$9715_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:160801$9716 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [10] } + connect \B { 2'00 \a [11] } + connect \Y $add$libresoc.v:160801$9716_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:160802$9717 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A { 2'00 \pop_4_6 } + connect \B { 2'00 \pop_4_7 } + connect \Y $add$libresoc.v:160802$9717_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:160803$9718 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 7 + connect \A { 2'00 \pop_5_0 } + connect \B { 2'00 \pop_5_1 } + connect \Y $add$libresoc.v:160803$9718_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:160804$9719 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 7 + connect \A { 2'00 \pop_5_2 } + connect \B { 2'00 \pop_5_3 } + connect \Y $add$libresoc.v:160804$9719_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:160805$9720 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A { 2'00 \pop_6_0 } + connect \B { 2'00 \pop_6_1 } + connect \Y $add$libresoc.v:160805$9720_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:160816$9739 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [12] } + connect \B { 2'00 \a [13] } + connect \Y $add$libresoc.v:160816$9739_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:160820$9746 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [14] } + connect \B { 2'00 \a [15] } + connect \Y $add$libresoc.v:160820$9746_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:160821$9747 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [16] } + connect \B { 2'00 \a [17] } + connect \Y $add$libresoc.v:160821$9747_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:160822$9748 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [0] } + connect \B { 2'00 \a [1] } + connect \Y $add$libresoc.v:160822$9748_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:160823$9749 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [18] } + connect \B { 2'00 \a [19] } + connect \Y $add$libresoc.v:160823$9749_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:160824$9750 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [20] } + connect \B { 2'00 \a [21] } + connect \Y $add$libresoc.v:160824$9750_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:160825$9751 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [22] } + connect \B { 2'00 \a [23] } + connect \Y $add$libresoc.v:160825$9751_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:160826$9752 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [24] } + connect \B { 2'00 \a [25] } + connect \Y $add$libresoc.v:160826$9752_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:160827$9753 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [26] } + connect \B { 2'00 \a [27] } + connect \Y $add$libresoc.v:160827$9753_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:160828$9754 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [28] } + connect \B { 2'00 \a [29] } + connect \Y $add$libresoc.v:160828$9754_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:160829$9755 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [30] } + connect \B { 2'00 \a [31] } + connect \Y $add$libresoc.v:160829$9755_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:160830$9756 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [32] } + connect \B { 2'00 \a [33] } + connect \Y $add$libresoc.v:160830$9756_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:160831$9757 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [34] } + connect \B { 2'00 \a [35] } + connect \Y $add$libresoc.v:160831$9757_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:160832$9758 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [36] } + connect \B { 2'00 \a [37] } + connect \Y $add$libresoc.v:160832$9758_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:160833$9759 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [2] } + connect \B { 2'00 \a [3] } + connect \Y $add$libresoc.v:160833$9759_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:160834$9760 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [38] } + connect \B { 2'00 \a [39] } + connect \Y $add$libresoc.v:160834$9760_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:160835$9761 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [40] } + connect \B { 2'00 \a [41] } + connect \Y $add$libresoc.v:160835$9761_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:160836$9762 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [42] } + connect \B { 2'00 \a [43] } + connect \Y $add$libresoc.v:160836$9762_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:160837$9763 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [44] } + connect \B { 2'00 \a [45] } + connect \Y $add$libresoc.v:160837$9763_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:160838$9764 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [46] } + connect \B { 2'00 \a [47] } + connect \Y $add$libresoc.v:160838$9764_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:160839$9765 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [48] } + connect \B { 2'00 \a [49] } + connect \Y $add$libresoc.v:160839$9765_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:160840$9766 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [50] } + connect \B { 2'00 \a [51] } + connect \Y $add$libresoc.v:160840$9766_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:160841$9767 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [52] } + connect \B { 2'00 \a [53] } + connect \Y $add$libresoc.v:160841$9767_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:160842$9768 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [54] } + connect \B { 2'00 \a [55] } + connect \Y $add$libresoc.v:160842$9768_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:160843$9769 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [56] } + connect \B { 2'00 \a [57] } + connect \Y $add$libresoc.v:160843$9769_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:160844$9770 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [4] } + connect \B { 2'00 \a [5] } + connect \Y $add$libresoc.v:160844$9770_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:160845$9771 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [58] } + connect \B { 2'00 \a [59] } + connect \Y $add$libresoc.v:160845$9771_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:160846$9772 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [60] } + connect \B { 2'00 \a [61] } + connect \Y $add$libresoc.v:160846$9772_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:160847$9773 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [62] } + connect \B { 2'00 \a [63] } + connect \Y $add$libresoc.v:160847$9773_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:160848$9774 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A { 2'00 \pop_2_0 } + connect \B { 2'00 \pop_2_1 } + connect \Y $add$libresoc.v:160848$9774_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:55" + cell $eq $eq$libresoc.v:160806$9721 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \data_len + connect \B 1'1 + connect \Y $eq$libresoc.v:160806$9721_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:59" + cell $eq $eq$libresoc.v:160807$9722 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \data_len + connect \B 3'100 + connect \Y $eq$libresoc.v:160807$9722_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $extend$libresoc.v:160808$9723 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 8 + connect \A \pop_4_0 + connect \Y $extend$libresoc.v:160808$9723_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $extend$libresoc.v:160809$9725 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 8 + connect \A \pop_4_1 + connect \Y $extend$libresoc.v:160809$9725_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $extend$libresoc.v:160810$9727 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 8 + connect \A \pop_4_2 + connect \Y $extend$libresoc.v:160810$9727_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $extend$libresoc.v:160811$9729 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 8 + connect \A \pop_4_3 + connect \Y $extend$libresoc.v:160811$9729_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $extend$libresoc.v:160812$9731 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 8 + connect \A \pop_4_4 + connect \Y $extend$libresoc.v:160812$9731_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $extend$libresoc.v:160813$9733 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 8 + connect \A \pop_4_5 + connect \Y $extend$libresoc.v:160813$9733_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $extend$libresoc.v:160814$9735 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 8 + connect \A \pop_4_6 + connect \Y $extend$libresoc.v:160814$9735_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $extend$libresoc.v:160815$9737 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 8 + connect \A \pop_4_7 + connect \Y $extend$libresoc.v:160815$9737_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $extend$libresoc.v:160817$9740 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 32 + connect \A \pop_6_0 + connect \Y $extend$libresoc.v:160817$9740_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $extend$libresoc.v:160818$9742 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 32 + connect \A \pop_6_1 + connect \Y $extend$libresoc.v:160818$9742_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $extend$libresoc.v:160819$9744 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 64 + connect \A \pop_7_0 + connect \Y $extend$libresoc.v:160819$9744_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $pos$libresoc.v:160808$9724 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $extend$libresoc.v:160808$9723_Y + connect \Y $pos$libresoc.v:160808$9724_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $pos$libresoc.v:160809$9726 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $extend$libresoc.v:160809$9725_Y + connect \Y $pos$libresoc.v:160809$9726_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $pos$libresoc.v:160810$9728 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $extend$libresoc.v:160810$9727_Y + connect \Y $pos$libresoc.v:160810$9728_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $pos$libresoc.v:160811$9730 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $extend$libresoc.v:160811$9729_Y + connect \Y $pos$libresoc.v:160811$9730_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $pos$libresoc.v:160812$9732 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $extend$libresoc.v:160812$9731_Y + connect \Y $pos$libresoc.v:160812$9732_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $pos$libresoc.v:160813$9734 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $extend$libresoc.v:160813$9733_Y + connect \Y $pos$libresoc.v:160813$9734_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $pos$libresoc.v:160814$9736 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $extend$libresoc.v:160814$9735_Y + connect \Y $pos$libresoc.v:160814$9736_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $pos$libresoc.v:160815$9738 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $extend$libresoc.v:160815$9737_Y + connect \Y $pos$libresoc.v:160815$9738_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $pos$libresoc.v:160817$9741 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A $extend$libresoc.v:160817$9740_Y + connect \Y $pos$libresoc.v:160817$9741_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $pos$libresoc.v:160818$9743 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A $extend$libresoc.v:160818$9742_Y + connect \Y $pos$libresoc.v:160818$9743_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $pos$libresoc.v:160819$9745 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:160819$9744_Y + connect \Y $pos$libresoc.v:160819$9745_Y + end + attribute \src "libresoc.v:160361.7-160361.20" + process $proc$libresoc.v:160361$9776 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:160849.3-160875.6" + process $proc$libresoc.v:160849$9775 + assign { } { } + assign $0\o[63:0] $1\o[63:0] + attribute \src "libresoc.v:160850.5-160850.29" + switch \initial + attribute \src "libresoc.v:160850.9-160850.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:55" + switch { \$192 \$190 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\o[63:0] [7:0] \$194 + assign $1\o[63:0] [15:8] \$196 + assign $1\o[63:0] [23:16] \$198 + assign $1\o[63:0] [31:24] \$200 + assign $1\o[63:0] [39:32] \$202 + assign $1\o[63:0] [47:40] \$204 + assign $1\o[63:0] [55:48] \$206 + assign $1\o[63:0] [63:56] \$208 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\o[63:0] [31:0] \$210 + assign $1\o[63:0] [63:32] \$212 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\o[63:0] \$214 + end + sync always + update \o $0\o[63:0] + end + connect \$101 $add$libresoc.v:160773$9688_Y + connect \$104 $add$libresoc.v:160774$9689_Y + connect \$107 $add$libresoc.v:160775$9690_Y + connect \$110 $add$libresoc.v:160776$9691_Y + connect \$113 $add$libresoc.v:160777$9692_Y + connect \$116 $add$libresoc.v:160778$9693_Y + connect \$11 $add$libresoc.v:160779$9694_Y + connect \$119 $add$libresoc.v:160780$9695_Y + connect \$122 $add$libresoc.v:160781$9696_Y + connect \$125 $add$libresoc.v:160782$9697_Y + connect \$128 $add$libresoc.v:160783$9698_Y + connect \$131 $add$libresoc.v:160784$9699_Y + connect \$134 $add$libresoc.v:160785$9700_Y + connect \$137 $add$libresoc.v:160786$9701_Y + connect \$140 $add$libresoc.v:160787$9702_Y + connect \$143 $add$libresoc.v:160788$9703_Y + connect \$146 $add$libresoc.v:160789$9704_Y + connect \$14 $add$libresoc.v:160790$9705_Y + connect \$149 $add$libresoc.v:160791$9706_Y + connect \$152 $add$libresoc.v:160792$9707_Y + connect \$155 $add$libresoc.v:160793$9708_Y + connect \$158 $add$libresoc.v:160794$9709_Y + connect \$161 $add$libresoc.v:160795$9710_Y + connect \$164 $add$libresoc.v:160796$9711_Y + connect \$167 $add$libresoc.v:160797$9712_Y + connect \$170 $add$libresoc.v:160798$9713_Y + connect \$173 $add$libresoc.v:160799$9714_Y + connect \$176 $add$libresoc.v:160800$9715_Y + connect \$17 $add$libresoc.v:160801$9716_Y + connect \$179 $add$libresoc.v:160802$9717_Y + connect \$182 $add$libresoc.v:160803$9718_Y + connect \$185 $add$libresoc.v:160804$9719_Y + connect \$188 $add$libresoc.v:160805$9720_Y + connect \$190 $eq$libresoc.v:160806$9721_Y + connect \$192 $eq$libresoc.v:160807$9722_Y + connect \$194 $pos$libresoc.v:160808$9724_Y + connect \$196 $pos$libresoc.v:160809$9726_Y + connect \$198 $pos$libresoc.v:160810$9728_Y + connect \$200 $pos$libresoc.v:160811$9730_Y + connect \$202 $pos$libresoc.v:160812$9732_Y + connect \$204 $pos$libresoc.v:160813$9734_Y + connect \$206 $pos$libresoc.v:160814$9736_Y + connect \$208 $pos$libresoc.v:160815$9738_Y + connect \$20 $add$libresoc.v:160816$9739_Y + connect \$210 $pos$libresoc.v:160817$9741_Y + connect \$212 $pos$libresoc.v:160818$9743_Y + connect \$214 $pos$libresoc.v:160819$9745_Y + connect \$23 $add$libresoc.v:160820$9746_Y + connect \$26 $add$libresoc.v:160821$9747_Y + connect \$2 $add$libresoc.v:160822$9748_Y + connect \$29 $add$libresoc.v:160823$9749_Y + connect \$32 $add$libresoc.v:160824$9750_Y + connect \$35 $add$libresoc.v:160825$9751_Y + connect \$38 $add$libresoc.v:160826$9752_Y + connect \$41 $add$libresoc.v:160827$9753_Y + connect \$44 $add$libresoc.v:160828$9754_Y + connect \$47 $add$libresoc.v:160829$9755_Y + connect \$50 $add$libresoc.v:160830$9756_Y + connect \$53 $add$libresoc.v:160831$9757_Y + connect \$56 $add$libresoc.v:160832$9758_Y + connect \$5 $add$libresoc.v:160833$9759_Y + connect \$59 $add$libresoc.v:160834$9760_Y + connect \$62 $add$libresoc.v:160835$9761_Y + connect \$65 $add$libresoc.v:160836$9762_Y + connect \$68 $add$libresoc.v:160837$9763_Y + connect \$71 $add$libresoc.v:160838$9764_Y + connect \$74 $add$libresoc.v:160839$9765_Y + connect \$77 $add$libresoc.v:160840$9766_Y + connect \$80 $add$libresoc.v:160841$9767_Y + connect \$83 $add$libresoc.v:160842$9768_Y + connect \$86 $add$libresoc.v:160843$9769_Y + connect \$8 $add$libresoc.v:160844$9770_Y + connect \$89 $add$libresoc.v:160845$9771_Y + connect \$92 $add$libresoc.v:160846$9772_Y + connect \$95 $add$libresoc.v:160847$9773_Y + connect \$98 $add$libresoc.v:160848$9774_Y + connect \$1 \$2 + connect \$4 \$5 + connect \$7 \$8 + connect \$10 \$11 + connect \$13 \$14 + connect \$16 \$17 + connect \$19 \$20 + connect \$22 \$23 + connect \$25 \$26 + connect \$28 \$29 + connect \$31 \$32 + connect \$34 \$35 + connect \$37 \$38 + connect \$40 \$41 + connect \$43 \$44 + connect \$46 \$47 + connect \$49 \$50 + connect \$52 \$53 + connect \$55 \$56 + connect \$58 \$59 + connect \$61 \$62 + connect \$64 \$65 + connect \$67 \$68 + connect \$70 \$71 + connect \$73 \$74 + connect \$76 \$77 + connect \$79 \$80 + connect \$82 \$83 + connect \$85 \$86 + connect \$88 \$89 + connect \$91 \$92 + connect \$94 \$95 + connect \$97 \$98 + connect \$100 \$101 + connect \$103 \$104 + connect \$106 \$107 + connect \$109 \$110 + connect \$112 \$113 + connect \$115 \$116 + connect \$118 \$119 + connect \$121 \$122 + connect \$124 \$125 + connect \$127 \$128 + connect \$130 \$131 + connect \$133 \$134 + connect \$136 \$137 + connect \$139 \$140 + connect \$142 \$143 + connect \$145 \$146 + connect \$148 \$149 + connect \$151 \$152 + connect \$154 \$155 + connect \$157 \$158 + connect \$160 \$161 + connect \$163 \$164 + connect \$166 \$167 + connect \$169 \$170 + connect \$172 \$173 + connect \$175 \$176 + connect \$178 \$179 + connect \$181 \$182 + connect \$184 \$185 + connect \$187 \$188 + connect \pop_7_0 \$188 [6:0] + connect \pop_6_1 \$185 [5:0] + connect \pop_6_0 \$182 [5:0] + connect \pop_5_3 \$179 [4:0] + connect \pop_5_2 \$176 [4:0] + connect \pop_5_1 \$173 [4:0] + connect \pop_5_0 \$170 [4:0] + connect \pop_4_7 \$167 [3:0] + connect \pop_4_6 \$164 [3:0] + connect \pop_4_5 \$161 [3:0] + connect \pop_4_4 \$158 [3:0] + connect \pop_4_3 \$155 [3:0] + connect \pop_4_2 \$152 [3:0] + connect \pop_4_1 \$149 [3:0] + connect \pop_4_0 \$146 [3:0] + connect \pop_3_15 \$143 [2:0] + connect \pop_3_14 \$140 [2:0] + connect \pop_3_13 \$137 [2:0] + connect \pop_3_12 \$134 [2:0] + connect \pop_3_11 \$131 [2:0] + connect \pop_3_10 \$128 [2:0] + connect \pop_3_9 \$125 [2:0] + connect \pop_3_8 \$122 [2:0] + connect \pop_3_7 \$119 [2:0] + connect \pop_3_6 \$116 [2:0] + connect \pop_3_5 \$113 [2:0] + connect \pop_3_4 \$110 [2:0] + connect \pop_3_3 \$107 [2:0] + connect \pop_3_2 \$104 [2:0] + connect \pop_3_1 \$101 [2:0] + connect \pop_3_0 \$98 [2:0] + connect \pop_2_31 \$95 [1:0] + connect \pop_2_30 \$92 [1:0] + connect \pop_2_29 \$89 [1:0] + connect \pop_2_28 \$86 [1:0] + connect \pop_2_27 \$83 [1:0] + connect \pop_2_26 \$80 [1:0] + connect \pop_2_25 \$77 [1:0] + connect \pop_2_24 \$74 [1:0] + connect \pop_2_23 \$71 [1:0] + connect \pop_2_22 \$68 [1:0] + connect \pop_2_21 \$65 [1:0] + connect \pop_2_20 \$62 [1:0] + connect \pop_2_19 \$59 [1:0] + connect \pop_2_18 \$56 [1:0] + connect \pop_2_17 \$53 [1:0] + connect \pop_2_16 \$50 [1:0] + connect \pop_2_15 \$47 [1:0] + connect \pop_2_14 \$44 [1:0] + connect \pop_2_13 \$41 [1:0] + connect \pop_2_12 \$38 [1:0] + connect \pop_2_11 \$35 [1:0] + connect \pop_2_10 \$32 [1:0] + connect \pop_2_9 \$29 [1:0] + connect \pop_2_8 \$26 [1:0] + connect \pop_2_7 \$23 [1:0] + connect \pop_2_6 \$20 [1:0] + connect \pop_2_5 \$17 [1:0] + connect \pop_2_4 \$14 [1:0] + connect \pop_2_3 \$11 [1:0] + connect \pop_2_2 \$8 [1:0] + connect \pop_2_1 \$5 [1:0] + connect \pop_2_0 \$2 [1:0] +end +attribute \src "libresoc.v:161006.1-161090.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_ALU.dec_cr_in.ppick" +attribute \generator "nMigen" +module \ppick + attribute \src "libresoc.v:161063.17-161063.91" + wire $not$libresoc.v:161063$9777_Y + attribute \src "libresoc.v:161065.18-161065.93" + wire $not$libresoc.v:161065$9779_Y + attribute \src "libresoc.v:161067.18-161067.93" + wire $not$libresoc.v:161067$9781_Y + attribute \src "libresoc.v:161068.17-161068.138" + wire width 8 $not$libresoc.v:161068$9782_Y + attribute \src "libresoc.v:161070.18-161070.93" + wire $not$libresoc.v:161070$9784_Y + attribute \src "libresoc.v:161072.18-161072.93" + wire $not$libresoc.v:161072$9786_Y + attribute \src "libresoc.v:161074.18-161074.93" + wire $not$libresoc.v:161074$9788_Y + attribute \src "libresoc.v:161077.17-161077.91" + wire $not$libresoc.v:161077$9791_Y + attribute \src "libresoc.v:161064.18-161064.116" + wire $reduce_or$libresoc.v:161064$9778_Y + attribute \src "libresoc.v:161066.18-161066.122" + wire $reduce_or$libresoc.v:161066$9780_Y + attribute \src "libresoc.v:161069.18-161069.128" + wire $reduce_or$libresoc.v:161069$9783_Y + attribute \src "libresoc.v:161071.18-161071.134" + wire $reduce_or$libresoc.v:161071$9785_Y + attribute \src "libresoc.v:161073.18-161073.140" + wire $reduce_or$libresoc.v:161073$9787_Y + attribute \src "libresoc.v:161075.18-161075.90" + wire $reduce_or$libresoc.v:161075$9789_Y + attribute \src "libresoc.v:161076.17-161076.103" + wire $reduce_or$libresoc.v:161076$9790_Y + attribute \src "libresoc.v:161078.17-161078.109" + wire $reduce_or$libresoc.v:161078$9792_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire width 8 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 input 2 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire width 8 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:161063$9777 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $not$libresoc.v:161063$9777_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:161065$9779 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$12 + connect \Y $not$libresoc.v:161065$9779_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:161067$9781 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \Y $not$libresoc.v:161067$9781_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $not$libresoc.v:161068$9782 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } + connect \Y $not$libresoc.v:161068$9782_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:161070$9784 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$20 + connect \Y $not$libresoc.v:161070$9784_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:161072$9786 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$24 + connect \Y $not$libresoc.v:161072$9786_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:161074$9788 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$28 + connect \Y $not$libresoc.v:161074$9788_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:161077$9791 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$libresoc.v:161077$9791_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:161064$9778 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [5] \i [6] \i [7] \ni [3] } + connect \Y $reduce_or$libresoc.v:161064$9778_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:161066$9780 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } + connect \Y $reduce_or$libresoc.v:161066$9780_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:161069$9783 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } + connect \Y $reduce_or$libresoc.v:161069$9783_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:161071$9785 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } + connect \Y $reduce_or$libresoc.v:161071$9785_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:161073$9787 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } + connect \Y $reduce_or$libresoc.v:161073$9787_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_or $reduce_or$libresoc.v:161075$9789 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:161075$9789_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:161076$9790 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [7] \ni [1] } + connect \Y $reduce_or$libresoc.v:161076$9790_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:161078$9792 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [6] \i [7] \ni [2] } + connect \Y $reduce_or$libresoc.v:161078$9792_Y + end + connect \$7 $not$libresoc.v:161063$9777_Y + connect \$12 $reduce_or$libresoc.v:161064$9778_Y + connect \$11 $not$libresoc.v:161065$9779_Y + connect \$16 $reduce_or$libresoc.v:161066$9780_Y + connect \$15 $not$libresoc.v:161067$9781_Y + connect \$1 $not$libresoc.v:161068$9782_Y + connect \$20 $reduce_or$libresoc.v:161069$9783_Y + connect \$19 $not$libresoc.v:161070$9784_Y + connect \$24 $reduce_or$libresoc.v:161071$9785_Y + connect \$23 $not$libresoc.v:161072$9786_Y + connect \$28 $reduce_or$libresoc.v:161073$9787_Y + connect \$27 $not$libresoc.v:161074$9788_Y + connect \$31 $reduce_or$libresoc.v:161075$9789_Y + connect \$4 $reduce_or$libresoc.v:161076$9790_Y + connect \$3 $not$libresoc.v:161077$9791_Y + connect \$8 $reduce_or$libresoc.v:161078$9792_Y + connect \en_o \$31 + connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } + connect \t7 \$27 + connect \t6 \$23 + connect \t5 \$19 + connect \t4 \$15 + connect \t3 \$11 + connect \t2 \$7 + connect \t1 \$3 + connect \t0 \i [7] + connect \ni \$1 +end +attribute \src "libresoc.v:161094.1-161178.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_ALU.dec_cr_out.ppick" +attribute \generator "nMigen" +module \ppick$136 + attribute \src "libresoc.v:161151.17-161151.91" + wire $not$libresoc.v:161151$9793_Y + attribute \src "libresoc.v:161153.18-161153.93" + wire $not$libresoc.v:161153$9795_Y + attribute \src "libresoc.v:161155.18-161155.93" + wire $not$libresoc.v:161155$9797_Y + attribute \src "libresoc.v:161156.17-161156.138" + wire width 8 $not$libresoc.v:161156$9798_Y + attribute \src "libresoc.v:161158.18-161158.93" + wire $not$libresoc.v:161158$9800_Y + attribute \src "libresoc.v:161160.18-161160.93" + wire $not$libresoc.v:161160$9802_Y + attribute \src "libresoc.v:161162.18-161162.93" + wire $not$libresoc.v:161162$9804_Y + attribute \src "libresoc.v:161165.17-161165.91" + wire $not$libresoc.v:161165$9807_Y + attribute \src "libresoc.v:161152.18-161152.116" + wire $reduce_or$libresoc.v:161152$9794_Y + attribute \src "libresoc.v:161154.18-161154.122" + wire $reduce_or$libresoc.v:161154$9796_Y + attribute \src "libresoc.v:161157.18-161157.128" + wire $reduce_or$libresoc.v:161157$9799_Y + attribute \src "libresoc.v:161159.18-161159.134" + wire $reduce_or$libresoc.v:161159$9801_Y + attribute \src "libresoc.v:161161.18-161161.140" + wire $reduce_or$libresoc.v:161161$9803_Y + attribute \src "libresoc.v:161163.18-161163.90" + wire $reduce_or$libresoc.v:161163$9805_Y + attribute \src "libresoc.v:161164.17-161164.103" + wire $reduce_or$libresoc.v:161164$9806_Y + attribute \src "libresoc.v:161166.17-161166.109" + wire $reduce_or$libresoc.v:161166$9808_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire width 8 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire output 1 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire width 8 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 output 2 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:161151$9793 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $not$libresoc.v:161151$9793_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:161153$9795 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$12 + connect \Y $not$libresoc.v:161153$9795_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:161155$9797 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \Y $not$libresoc.v:161155$9797_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $not$libresoc.v:161156$9798 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } + connect \Y $not$libresoc.v:161156$9798_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:161158$9800 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$20 + connect \Y $not$libresoc.v:161158$9800_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:161160$9802 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$24 + connect \Y $not$libresoc.v:161160$9802_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:161162$9804 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$28 + connect \Y $not$libresoc.v:161162$9804_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:161165$9807 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$libresoc.v:161165$9807_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:161152$9794 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [5] \i [6] \i [7] \ni [3] } + connect \Y $reduce_or$libresoc.v:161152$9794_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:161154$9796 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } + connect \Y $reduce_or$libresoc.v:161154$9796_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:161157$9799 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } + connect \Y $reduce_or$libresoc.v:161157$9799_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:161159$9801 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } + connect \Y $reduce_or$libresoc.v:161159$9801_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:161161$9803 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } + connect \Y $reduce_or$libresoc.v:161161$9803_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_or $reduce_or$libresoc.v:161163$9805 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:161163$9805_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:161164$9806 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [7] \ni [1] } + connect \Y $reduce_or$libresoc.v:161164$9806_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:161166$9808 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [6] \i [7] \ni [2] } + connect \Y $reduce_or$libresoc.v:161166$9808_Y + end + connect \$7 $not$libresoc.v:161151$9793_Y + connect \$12 $reduce_or$libresoc.v:161152$9794_Y + connect \$11 $not$libresoc.v:161153$9795_Y + connect \$16 $reduce_or$libresoc.v:161154$9796_Y + connect \$15 $not$libresoc.v:161155$9797_Y + connect \$1 $not$libresoc.v:161156$9798_Y + connect \$20 $reduce_or$libresoc.v:161157$9799_Y + connect \$19 $not$libresoc.v:161158$9800_Y + connect \$24 $reduce_or$libresoc.v:161159$9801_Y + connect \$23 $not$libresoc.v:161160$9802_Y + connect \$28 $reduce_or$libresoc.v:161161$9803_Y + connect \$27 $not$libresoc.v:161162$9804_Y + connect \$31 $reduce_or$libresoc.v:161163$9805_Y + connect \$4 $reduce_or$libresoc.v:161164$9806_Y + connect \$3 $not$libresoc.v:161165$9807_Y + connect \$8 $reduce_or$libresoc.v:161166$9808_Y + connect \en_o \$31 + connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } + connect \t7 \$27 + connect \t6 \$23 + connect \t5 \$19 + connect \t4 \$15 + connect \t3 \$11 + connect \t2 \$7 + connect \t1 \$3 + connect \t0 \i [7] + connect \ni \$1 +end +attribute \src "libresoc.v:161182.1-161266.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_CR.dec_cr_in.ppick" +attribute \generator "nMigen" +module \ppick$141 + attribute \src "libresoc.v:161239.17-161239.91" + wire $not$libresoc.v:161239$9809_Y + attribute \src "libresoc.v:161241.18-161241.93" + wire $not$libresoc.v:161241$9811_Y + attribute \src "libresoc.v:161243.18-161243.93" + wire $not$libresoc.v:161243$9813_Y + attribute \src "libresoc.v:161244.17-161244.138" + wire width 8 $not$libresoc.v:161244$9814_Y + attribute \src "libresoc.v:161246.18-161246.93" + wire $not$libresoc.v:161246$9816_Y + attribute \src "libresoc.v:161248.18-161248.93" + wire $not$libresoc.v:161248$9818_Y + attribute \src "libresoc.v:161250.18-161250.93" + wire $not$libresoc.v:161250$9820_Y + attribute \src "libresoc.v:161253.17-161253.91" + wire $not$libresoc.v:161253$9823_Y + attribute \src "libresoc.v:161240.18-161240.116" + wire $reduce_or$libresoc.v:161240$9810_Y + attribute \src "libresoc.v:161242.18-161242.122" + wire $reduce_or$libresoc.v:161242$9812_Y + attribute \src "libresoc.v:161245.18-161245.128" + wire $reduce_or$libresoc.v:161245$9815_Y + attribute \src "libresoc.v:161247.18-161247.134" + wire $reduce_or$libresoc.v:161247$9817_Y + attribute \src "libresoc.v:161249.18-161249.140" + wire $reduce_or$libresoc.v:161249$9819_Y + attribute \src "libresoc.v:161251.18-161251.90" + wire $reduce_or$libresoc.v:161251$9821_Y + attribute \src "libresoc.v:161252.17-161252.103" + wire $reduce_or$libresoc.v:161252$9822_Y + attribute \src "libresoc.v:161254.17-161254.109" + wire $reduce_or$libresoc.v:161254$9824_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire width 8 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 input 2 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire width 8 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:161239$9809 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $not$libresoc.v:161239$9809_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:161241$9811 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$12 + connect \Y $not$libresoc.v:161241$9811_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:161243$9813 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \Y $not$libresoc.v:161243$9813_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $not$libresoc.v:161244$9814 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } + connect \Y $not$libresoc.v:161244$9814_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:161246$9816 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$20 + connect \Y $not$libresoc.v:161246$9816_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:161248$9818 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$24 + connect \Y $not$libresoc.v:161248$9818_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:161250$9820 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$28 + connect \Y $not$libresoc.v:161250$9820_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:161253$9823 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$libresoc.v:161253$9823_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:161240$9810 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [5] \i [6] \i [7] \ni [3] } + connect \Y $reduce_or$libresoc.v:161240$9810_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:161242$9812 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } + connect \Y $reduce_or$libresoc.v:161242$9812_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:161245$9815 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } + connect \Y $reduce_or$libresoc.v:161245$9815_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:161247$9817 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } + connect \Y $reduce_or$libresoc.v:161247$9817_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:161249$9819 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } + connect \Y $reduce_or$libresoc.v:161249$9819_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_or $reduce_or$libresoc.v:161251$9821 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:161251$9821_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:161252$9822 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [7] \ni [1] } + connect \Y $reduce_or$libresoc.v:161252$9822_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:161254$9824 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [6] \i [7] \ni [2] } + connect \Y $reduce_or$libresoc.v:161254$9824_Y + end + connect \$7 $not$libresoc.v:161239$9809_Y + connect \$12 $reduce_or$libresoc.v:161240$9810_Y + connect \$11 $not$libresoc.v:161241$9811_Y + connect \$16 $reduce_or$libresoc.v:161242$9812_Y + connect \$15 $not$libresoc.v:161243$9813_Y + connect \$1 $not$libresoc.v:161244$9814_Y + connect \$20 $reduce_or$libresoc.v:161245$9815_Y + connect \$19 $not$libresoc.v:161246$9816_Y + connect \$24 $reduce_or$libresoc.v:161247$9817_Y + connect \$23 $not$libresoc.v:161248$9818_Y + connect \$28 $reduce_or$libresoc.v:161249$9819_Y + connect \$27 $not$libresoc.v:161250$9820_Y + connect \$31 $reduce_or$libresoc.v:161251$9821_Y + connect \$4 $reduce_or$libresoc.v:161252$9822_Y + connect \$3 $not$libresoc.v:161253$9823_Y + connect \$8 $reduce_or$libresoc.v:161254$9824_Y + connect \en_o \$31 + connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } + connect \t7 \$27 + connect \t6 \$23 + connect \t5 \$19 + connect \t4 \$15 + connect \t3 \$11 + connect \t2 \$7 + connect \t1 \$3 + connect \t0 \i [7] + connect \ni \$1 +end +attribute \src "libresoc.v:161270.1-161354.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_CR.dec_cr_out.ppick" +attribute \generator "nMigen" +module \ppick$143 + attribute \src "libresoc.v:161327.17-161327.91" + wire $not$libresoc.v:161327$9825_Y + attribute \src "libresoc.v:161329.18-161329.93" + wire $not$libresoc.v:161329$9827_Y + attribute \src "libresoc.v:161331.18-161331.93" + wire $not$libresoc.v:161331$9829_Y + attribute \src "libresoc.v:161332.17-161332.138" + wire width 8 $not$libresoc.v:161332$9830_Y + attribute \src "libresoc.v:161334.18-161334.93" + wire $not$libresoc.v:161334$9832_Y + attribute \src "libresoc.v:161336.18-161336.93" + wire $not$libresoc.v:161336$9834_Y + attribute \src "libresoc.v:161338.18-161338.93" + wire $not$libresoc.v:161338$9836_Y + attribute \src "libresoc.v:161341.17-161341.91" + wire $not$libresoc.v:161341$9839_Y + attribute \src "libresoc.v:161328.18-161328.116" + wire $reduce_or$libresoc.v:161328$9826_Y + attribute \src "libresoc.v:161330.18-161330.122" + wire $reduce_or$libresoc.v:161330$9828_Y + attribute \src "libresoc.v:161333.18-161333.128" + wire $reduce_or$libresoc.v:161333$9831_Y + attribute \src "libresoc.v:161335.18-161335.134" + wire $reduce_or$libresoc.v:161335$9833_Y + attribute \src "libresoc.v:161337.18-161337.140" + wire $reduce_or$libresoc.v:161337$9835_Y + attribute \src "libresoc.v:161339.18-161339.90" + wire $reduce_or$libresoc.v:161339$9837_Y + attribute \src "libresoc.v:161340.17-161340.103" + wire $reduce_or$libresoc.v:161340$9838_Y + attribute \src "libresoc.v:161342.17-161342.109" + wire $reduce_or$libresoc.v:161342$9840_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire width 8 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire output 1 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire width 8 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 output 2 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:161327$9825 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $not$libresoc.v:161327$9825_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:161329$9827 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$12 + connect \Y $not$libresoc.v:161329$9827_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:161331$9829 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \Y $not$libresoc.v:161331$9829_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $not$libresoc.v:161332$9830 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } + connect \Y $not$libresoc.v:161332$9830_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:161334$9832 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$20 + connect \Y $not$libresoc.v:161334$9832_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:161336$9834 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$24 + connect \Y $not$libresoc.v:161336$9834_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:161338$9836 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$28 + connect \Y $not$libresoc.v:161338$9836_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:161341$9839 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$libresoc.v:161341$9839_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:161328$9826 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [5] \i [6] \i [7] \ni [3] } + connect \Y $reduce_or$libresoc.v:161328$9826_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:161330$9828 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } + connect \Y $reduce_or$libresoc.v:161330$9828_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:161333$9831 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } + connect \Y $reduce_or$libresoc.v:161333$9831_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:161335$9833 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } + connect \Y $reduce_or$libresoc.v:161335$9833_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:161337$9835 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } + connect \Y $reduce_or$libresoc.v:161337$9835_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_or $reduce_or$libresoc.v:161339$9837 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:161339$9837_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:161340$9838 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [7] \ni [1] } + connect \Y $reduce_or$libresoc.v:161340$9838_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:161342$9840 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [6] \i [7] \ni [2] } + connect \Y $reduce_or$libresoc.v:161342$9840_Y + end + connect \$7 $not$libresoc.v:161327$9825_Y + connect \$12 $reduce_or$libresoc.v:161328$9826_Y + connect \$11 $not$libresoc.v:161329$9827_Y + connect \$16 $reduce_or$libresoc.v:161330$9828_Y + connect \$15 $not$libresoc.v:161331$9829_Y + connect \$1 $not$libresoc.v:161332$9830_Y + connect \$20 $reduce_or$libresoc.v:161333$9831_Y + connect \$19 $not$libresoc.v:161334$9832_Y + connect \$24 $reduce_or$libresoc.v:161335$9833_Y + connect \$23 $not$libresoc.v:161336$9834_Y + connect \$28 $reduce_or$libresoc.v:161337$9835_Y + connect \$27 $not$libresoc.v:161338$9836_Y + connect \$31 $reduce_or$libresoc.v:161339$9837_Y + connect \$4 $reduce_or$libresoc.v:161340$9838_Y + connect \$3 $not$libresoc.v:161341$9839_Y + connect \$8 $reduce_or$libresoc.v:161342$9840_Y + connect \en_o \$31 + connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } + connect \t7 \$27 + connect \t6 \$23 + connect \t5 \$19 + connect \t4 \$15 + connect \t3 \$11 + connect \t2 \$7 + connect \t1 \$3 + connect \t0 \i [7] + connect \ni \$1 +end +attribute \src "libresoc.v:161358.1-161442.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_BRANCH.dec_cr_in.ppick" +attribute \generator "nMigen" +module \ppick$148 + attribute \src "libresoc.v:161415.17-161415.91" + wire $not$libresoc.v:161415$9841_Y + attribute \src "libresoc.v:161417.18-161417.93" + wire $not$libresoc.v:161417$9843_Y + attribute \src "libresoc.v:161419.18-161419.93" + wire $not$libresoc.v:161419$9845_Y + attribute \src "libresoc.v:161420.17-161420.138" + wire width 8 $not$libresoc.v:161420$9846_Y + attribute \src "libresoc.v:161422.18-161422.93" + wire $not$libresoc.v:161422$9848_Y + attribute \src "libresoc.v:161424.18-161424.93" + wire $not$libresoc.v:161424$9850_Y + attribute \src "libresoc.v:161426.18-161426.93" + wire $not$libresoc.v:161426$9852_Y + attribute \src "libresoc.v:161429.17-161429.91" + wire $not$libresoc.v:161429$9855_Y + attribute \src "libresoc.v:161416.18-161416.116" + wire $reduce_or$libresoc.v:161416$9842_Y + attribute \src "libresoc.v:161418.18-161418.122" + wire $reduce_or$libresoc.v:161418$9844_Y + attribute \src "libresoc.v:161421.18-161421.128" + wire $reduce_or$libresoc.v:161421$9847_Y + attribute \src "libresoc.v:161423.18-161423.134" + wire $reduce_or$libresoc.v:161423$9849_Y + attribute \src "libresoc.v:161425.18-161425.140" + wire $reduce_or$libresoc.v:161425$9851_Y + attribute \src "libresoc.v:161427.18-161427.90" + wire $reduce_or$libresoc.v:161427$9853_Y + attribute \src "libresoc.v:161428.17-161428.103" + wire $reduce_or$libresoc.v:161428$9854_Y + attribute \src "libresoc.v:161430.17-161430.109" + wire $reduce_or$libresoc.v:161430$9856_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire width 8 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 input 2 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire width 8 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:161415$9841 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $not$libresoc.v:161415$9841_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:161417$9843 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$12 + connect \Y $not$libresoc.v:161417$9843_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:161419$9845 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \Y $not$libresoc.v:161419$9845_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $not$libresoc.v:161420$9846 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } + connect \Y $not$libresoc.v:161420$9846_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:161422$9848 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$20 + connect \Y $not$libresoc.v:161422$9848_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:161424$9850 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$24 + connect \Y $not$libresoc.v:161424$9850_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:161426$9852 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$28 + connect \Y $not$libresoc.v:161426$9852_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:161429$9855 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$libresoc.v:161429$9855_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:161416$9842 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [5] \i [6] \i [7] \ni [3] } + connect \Y $reduce_or$libresoc.v:161416$9842_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:161418$9844 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } + connect \Y $reduce_or$libresoc.v:161418$9844_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:161421$9847 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } + connect \Y $reduce_or$libresoc.v:161421$9847_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:161423$9849 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } + connect \Y $reduce_or$libresoc.v:161423$9849_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:161425$9851 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } + connect \Y $reduce_or$libresoc.v:161425$9851_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_or $reduce_or$libresoc.v:161427$9853 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:161427$9853_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:161428$9854 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [7] \ni [1] } + connect \Y $reduce_or$libresoc.v:161428$9854_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:161430$9856 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [6] \i [7] \ni [2] } + connect \Y $reduce_or$libresoc.v:161430$9856_Y + end + connect \$7 $not$libresoc.v:161415$9841_Y + connect \$12 $reduce_or$libresoc.v:161416$9842_Y + connect \$11 $not$libresoc.v:161417$9843_Y + connect \$16 $reduce_or$libresoc.v:161418$9844_Y + connect \$15 $not$libresoc.v:161419$9845_Y + connect \$1 $not$libresoc.v:161420$9846_Y + connect \$20 $reduce_or$libresoc.v:161421$9847_Y + connect \$19 $not$libresoc.v:161422$9848_Y + connect \$24 $reduce_or$libresoc.v:161423$9849_Y + connect \$23 $not$libresoc.v:161424$9850_Y + connect \$28 $reduce_or$libresoc.v:161425$9851_Y + connect \$27 $not$libresoc.v:161426$9852_Y + connect \$31 $reduce_or$libresoc.v:161427$9853_Y + connect \$4 $reduce_or$libresoc.v:161428$9854_Y + connect \$3 $not$libresoc.v:161429$9855_Y + connect \$8 $reduce_or$libresoc.v:161430$9856_Y + connect \en_o \$31 + connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } + connect \t7 \$27 + connect \t6 \$23 + connect \t5 \$19 + connect \t4 \$15 + connect \t3 \$11 + connect \t2 \$7 + connect \t1 \$3 + connect \t0 \i [7] + connect \ni \$1 +end +attribute \src "libresoc.v:161446.1-161530.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_BRANCH.dec_cr_out.ppick" +attribute \generator "nMigen" +module \ppick$150 + attribute \src "libresoc.v:161503.17-161503.91" + wire $not$libresoc.v:161503$9857_Y + attribute \src "libresoc.v:161505.18-161505.93" + wire $not$libresoc.v:161505$9859_Y + attribute \src "libresoc.v:161507.18-161507.93" + wire $not$libresoc.v:161507$9861_Y + attribute \src "libresoc.v:161508.17-161508.138" + wire width 8 $not$libresoc.v:161508$9862_Y + attribute \src "libresoc.v:161510.18-161510.93" + wire $not$libresoc.v:161510$9864_Y + attribute \src "libresoc.v:161512.18-161512.93" + wire $not$libresoc.v:161512$9866_Y + attribute \src "libresoc.v:161514.18-161514.93" + wire $not$libresoc.v:161514$9868_Y + attribute \src "libresoc.v:161517.17-161517.91" + wire $not$libresoc.v:161517$9871_Y + attribute \src "libresoc.v:161504.18-161504.116" + wire $reduce_or$libresoc.v:161504$9858_Y + attribute \src "libresoc.v:161506.18-161506.122" + wire $reduce_or$libresoc.v:161506$9860_Y + attribute \src "libresoc.v:161509.18-161509.128" + wire $reduce_or$libresoc.v:161509$9863_Y + attribute \src "libresoc.v:161511.18-161511.134" + wire $reduce_or$libresoc.v:161511$9865_Y + attribute \src "libresoc.v:161513.18-161513.140" + wire $reduce_or$libresoc.v:161513$9867_Y + attribute \src "libresoc.v:161515.18-161515.90" + wire $reduce_or$libresoc.v:161515$9869_Y + attribute \src "libresoc.v:161516.17-161516.103" + wire $reduce_or$libresoc.v:161516$9870_Y + attribute \src "libresoc.v:161518.17-161518.109" + wire $reduce_or$libresoc.v:161518$9872_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire width 8 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire output 1 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire width 8 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 output 2 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:161503$9857 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $not$libresoc.v:161503$9857_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:161505$9859 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$12 + connect \Y $not$libresoc.v:161505$9859_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:161507$9861 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \Y $not$libresoc.v:161507$9861_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $not$libresoc.v:161508$9862 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } + connect \Y $not$libresoc.v:161508$9862_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:161510$9864 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$20 + connect \Y $not$libresoc.v:161510$9864_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:161512$9866 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$24 + connect \Y $not$libresoc.v:161512$9866_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:161514$9868 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$28 + connect \Y $not$libresoc.v:161514$9868_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:161517$9871 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$libresoc.v:161517$9871_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:161504$9858 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [5] \i [6] \i [7] \ni [3] } + connect \Y $reduce_or$libresoc.v:161504$9858_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:161506$9860 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } + connect \Y $reduce_or$libresoc.v:161506$9860_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:161509$9863 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } + connect \Y $reduce_or$libresoc.v:161509$9863_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:161511$9865 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } + connect \Y $reduce_or$libresoc.v:161511$9865_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:161513$9867 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } + connect \Y $reduce_or$libresoc.v:161513$9867_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_or $reduce_or$libresoc.v:161515$9869 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:161515$9869_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:161516$9870 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [7] \ni [1] } + connect \Y $reduce_or$libresoc.v:161516$9870_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:161518$9872 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [6] \i [7] \ni [2] } + connect \Y $reduce_or$libresoc.v:161518$9872_Y + end + connect \$7 $not$libresoc.v:161503$9857_Y + connect \$12 $reduce_or$libresoc.v:161504$9858_Y + connect \$11 $not$libresoc.v:161505$9859_Y + connect \$16 $reduce_or$libresoc.v:161506$9860_Y + connect \$15 $not$libresoc.v:161507$9861_Y + connect \$1 $not$libresoc.v:161508$9862_Y + connect \$20 $reduce_or$libresoc.v:161509$9863_Y + connect \$19 $not$libresoc.v:161510$9864_Y + connect \$24 $reduce_or$libresoc.v:161511$9865_Y + connect \$23 $not$libresoc.v:161512$9866_Y + connect \$28 $reduce_or$libresoc.v:161513$9867_Y + connect \$27 $not$libresoc.v:161514$9868_Y + connect \$31 $reduce_or$libresoc.v:161515$9869_Y + connect \$4 $reduce_or$libresoc.v:161516$9870_Y + connect \$3 $not$libresoc.v:161517$9871_Y + connect \$8 $reduce_or$libresoc.v:161518$9872_Y + connect \en_o \$31 + connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } + connect \t7 \$27 + connect \t6 \$23 + connect \t5 \$19 + connect \t4 \$15 + connect \t3 \$11 + connect \t2 \$7 + connect \t1 \$3 + connect \t0 \i [7] + connect \ni \$1 +end +attribute \src "libresoc.v:161534.1-161618.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_LOGICAL.dec_cr_in.ppick" +attribute \generator "nMigen" +module \ppick$156 + attribute \src "libresoc.v:161591.17-161591.91" + wire $not$libresoc.v:161591$9873_Y + attribute \src "libresoc.v:161593.18-161593.93" + wire $not$libresoc.v:161593$9875_Y + attribute \src "libresoc.v:161595.18-161595.93" + wire $not$libresoc.v:161595$9877_Y + attribute \src "libresoc.v:161596.17-161596.138" + wire width 8 $not$libresoc.v:161596$9878_Y + attribute \src "libresoc.v:161598.18-161598.93" + wire $not$libresoc.v:161598$9880_Y + attribute \src "libresoc.v:161600.18-161600.93" + wire $not$libresoc.v:161600$9882_Y + attribute \src "libresoc.v:161602.18-161602.93" + wire $not$libresoc.v:161602$9884_Y + attribute \src "libresoc.v:161605.17-161605.91" + wire $not$libresoc.v:161605$9887_Y + attribute \src "libresoc.v:161592.18-161592.116" + wire $reduce_or$libresoc.v:161592$9874_Y + attribute \src "libresoc.v:161594.18-161594.122" + wire $reduce_or$libresoc.v:161594$9876_Y + attribute \src "libresoc.v:161597.18-161597.128" + wire $reduce_or$libresoc.v:161597$9879_Y + attribute \src "libresoc.v:161599.18-161599.134" + wire $reduce_or$libresoc.v:161599$9881_Y + attribute \src "libresoc.v:161601.18-161601.140" + wire $reduce_or$libresoc.v:161601$9883_Y + attribute \src "libresoc.v:161603.18-161603.90" + wire $reduce_or$libresoc.v:161603$9885_Y + attribute \src "libresoc.v:161604.17-161604.103" + wire $reduce_or$libresoc.v:161604$9886_Y + attribute \src "libresoc.v:161606.17-161606.109" + wire $reduce_or$libresoc.v:161606$9888_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire width 8 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 input 2 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire width 8 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:161591$9873 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $not$libresoc.v:161591$9873_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:161593$9875 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$12 + connect \Y $not$libresoc.v:161593$9875_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:161595$9877 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \Y $not$libresoc.v:161595$9877_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $not$libresoc.v:161596$9878 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } + connect \Y $not$libresoc.v:161596$9878_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:161598$9880 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$20 + connect \Y $not$libresoc.v:161598$9880_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:161600$9882 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$24 + connect \Y $not$libresoc.v:161600$9882_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:161602$9884 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$28 + connect \Y $not$libresoc.v:161602$9884_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:161605$9887 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$libresoc.v:161605$9887_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:161592$9874 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [5] \i [6] \i [7] \ni [3] } + connect \Y $reduce_or$libresoc.v:161592$9874_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:161594$9876 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } + connect \Y $reduce_or$libresoc.v:161594$9876_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:161597$9879 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } + connect \Y $reduce_or$libresoc.v:161597$9879_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:161599$9881 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } + connect \Y $reduce_or$libresoc.v:161599$9881_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:161601$9883 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } + connect \Y $reduce_or$libresoc.v:161601$9883_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_or $reduce_or$libresoc.v:161603$9885 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:161603$9885_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:161604$9886 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [7] \ni [1] } + connect \Y $reduce_or$libresoc.v:161604$9886_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:161606$9888 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [6] \i [7] \ni [2] } + connect \Y $reduce_or$libresoc.v:161606$9888_Y + end + connect \$7 $not$libresoc.v:161591$9873_Y + connect \$12 $reduce_or$libresoc.v:161592$9874_Y + connect \$11 $not$libresoc.v:161593$9875_Y + connect \$16 $reduce_or$libresoc.v:161594$9876_Y + connect \$15 $not$libresoc.v:161595$9877_Y + connect \$1 $not$libresoc.v:161596$9878_Y + connect \$20 $reduce_or$libresoc.v:161597$9879_Y + connect \$19 $not$libresoc.v:161598$9880_Y + connect \$24 $reduce_or$libresoc.v:161599$9881_Y + connect \$23 $not$libresoc.v:161600$9882_Y + connect \$28 $reduce_or$libresoc.v:161601$9883_Y + connect \$27 $not$libresoc.v:161602$9884_Y + connect \$31 $reduce_or$libresoc.v:161603$9885_Y + connect \$4 $reduce_or$libresoc.v:161604$9886_Y + connect \$3 $not$libresoc.v:161605$9887_Y + connect \$8 $reduce_or$libresoc.v:161606$9888_Y + connect \en_o \$31 + connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } + connect \t7 \$27 + connect \t6 \$23 + connect \t5 \$19 + connect \t4 \$15 + connect \t3 \$11 + connect \t2 \$7 + connect \t1 \$3 + connect \t0 \i [7] + connect \ni \$1 +end +attribute \src "libresoc.v:161622.1-161706.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_LOGICAL.dec_cr_out.ppick" +attribute \generator "nMigen" +module \ppick$158 + attribute \src "libresoc.v:161679.17-161679.91" + wire $not$libresoc.v:161679$9889_Y + attribute \src "libresoc.v:161681.18-161681.93" + wire $not$libresoc.v:161681$9891_Y + attribute \src "libresoc.v:161683.18-161683.93" + wire $not$libresoc.v:161683$9893_Y + attribute \src "libresoc.v:161684.17-161684.138" + wire width 8 $not$libresoc.v:161684$9894_Y + attribute \src "libresoc.v:161686.18-161686.93" + wire $not$libresoc.v:161686$9896_Y + attribute \src "libresoc.v:161688.18-161688.93" + wire $not$libresoc.v:161688$9898_Y + attribute \src "libresoc.v:161690.18-161690.93" + wire $not$libresoc.v:161690$9900_Y + attribute \src "libresoc.v:161693.17-161693.91" + wire $not$libresoc.v:161693$9903_Y + attribute \src "libresoc.v:161680.18-161680.116" + wire $reduce_or$libresoc.v:161680$9890_Y + attribute \src "libresoc.v:161682.18-161682.122" + wire $reduce_or$libresoc.v:161682$9892_Y + attribute \src "libresoc.v:161685.18-161685.128" + wire $reduce_or$libresoc.v:161685$9895_Y + attribute \src "libresoc.v:161687.18-161687.134" + wire $reduce_or$libresoc.v:161687$9897_Y + attribute \src "libresoc.v:161689.18-161689.140" + wire $reduce_or$libresoc.v:161689$9899_Y + attribute \src "libresoc.v:161691.18-161691.90" + wire $reduce_or$libresoc.v:161691$9901_Y + attribute \src "libresoc.v:161692.17-161692.103" + wire $reduce_or$libresoc.v:161692$9902_Y + attribute \src "libresoc.v:161694.17-161694.109" + wire $reduce_or$libresoc.v:161694$9904_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire width 8 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire output 1 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire width 8 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 output 2 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:161679$9889 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $not$libresoc.v:161679$9889_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:161681$9891 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$12 + connect \Y $not$libresoc.v:161681$9891_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:161683$9893 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \Y $not$libresoc.v:161683$9893_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $not$libresoc.v:161684$9894 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } + connect \Y $not$libresoc.v:161684$9894_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:161686$9896 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$20 + connect \Y $not$libresoc.v:161686$9896_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:161688$9898 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$24 + connect \Y $not$libresoc.v:161688$9898_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:161690$9900 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$28 + connect \Y $not$libresoc.v:161690$9900_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:161693$9903 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$libresoc.v:161693$9903_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:161680$9890 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [5] \i [6] \i [7] \ni [3] } + connect \Y $reduce_or$libresoc.v:161680$9890_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:161682$9892 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } + connect \Y $reduce_or$libresoc.v:161682$9892_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:161685$9895 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } + connect \Y $reduce_or$libresoc.v:161685$9895_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:161687$9897 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } + connect \Y $reduce_or$libresoc.v:161687$9897_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:161689$9899 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } + connect \Y $reduce_or$libresoc.v:161689$9899_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_or $reduce_or$libresoc.v:161691$9901 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:161691$9901_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:161692$9902 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [7] \ni [1] } + connect \Y $reduce_or$libresoc.v:161692$9902_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:161694$9904 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [6] \i [7] \ni [2] } + connect \Y $reduce_or$libresoc.v:161694$9904_Y + end + connect \$7 $not$libresoc.v:161679$9889_Y + connect \$12 $reduce_or$libresoc.v:161680$9890_Y + connect \$11 $not$libresoc.v:161681$9891_Y + connect \$16 $reduce_or$libresoc.v:161682$9892_Y + connect \$15 $not$libresoc.v:161683$9893_Y + connect \$1 $not$libresoc.v:161684$9894_Y + connect \$20 $reduce_or$libresoc.v:161685$9895_Y + connect \$19 $not$libresoc.v:161686$9896_Y + connect \$24 $reduce_or$libresoc.v:161687$9897_Y + connect \$23 $not$libresoc.v:161688$9898_Y + connect \$28 $reduce_or$libresoc.v:161689$9899_Y + connect \$27 $not$libresoc.v:161690$9900_Y + connect \$31 $reduce_or$libresoc.v:161691$9901_Y + connect \$4 $reduce_or$libresoc.v:161692$9902_Y + connect \$3 $not$libresoc.v:161693$9903_Y + connect \$8 $reduce_or$libresoc.v:161694$9904_Y + connect \en_o \$31 + connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } + connect \t7 \$27 + connect \t6 \$23 + connect \t5 \$19 + connect \t4 \$15 + connect \t3 \$11 + connect \t2 \$7 + connect \t1 \$3 + connect \t0 \i [7] + connect \ni \$1 +end +attribute \src "libresoc.v:161710.1-161794.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_SPR.dec_cr_in.ppick" +attribute \generator "nMigen" +module \ppick$165 + attribute \src "libresoc.v:161767.17-161767.91" + wire $not$libresoc.v:161767$9905_Y + attribute \src "libresoc.v:161769.18-161769.93" + wire $not$libresoc.v:161769$9907_Y + attribute \src "libresoc.v:161771.18-161771.93" + wire $not$libresoc.v:161771$9909_Y + attribute \src "libresoc.v:161772.17-161772.138" + wire width 8 $not$libresoc.v:161772$9910_Y + attribute \src "libresoc.v:161774.18-161774.93" + wire $not$libresoc.v:161774$9912_Y + attribute \src "libresoc.v:161776.18-161776.93" + wire $not$libresoc.v:161776$9914_Y + attribute \src "libresoc.v:161778.18-161778.93" + wire $not$libresoc.v:161778$9916_Y + attribute \src "libresoc.v:161781.17-161781.91" + wire $not$libresoc.v:161781$9919_Y + attribute \src "libresoc.v:161768.18-161768.116" + wire $reduce_or$libresoc.v:161768$9906_Y + attribute \src "libresoc.v:161770.18-161770.122" + wire $reduce_or$libresoc.v:161770$9908_Y + attribute \src "libresoc.v:161773.18-161773.128" + wire $reduce_or$libresoc.v:161773$9911_Y + attribute \src "libresoc.v:161775.18-161775.134" + wire $reduce_or$libresoc.v:161775$9913_Y + attribute \src "libresoc.v:161777.18-161777.140" + wire $reduce_or$libresoc.v:161777$9915_Y + attribute \src "libresoc.v:161779.18-161779.90" + wire $reduce_or$libresoc.v:161779$9917_Y + attribute \src "libresoc.v:161780.17-161780.103" + wire $reduce_or$libresoc.v:161780$9918_Y + attribute \src "libresoc.v:161782.17-161782.109" + wire $reduce_or$libresoc.v:161782$9920_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire width 8 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 input 2 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire width 8 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:161767$9905 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $not$libresoc.v:161767$9905_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:161769$9907 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$12 + connect \Y $not$libresoc.v:161769$9907_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:161771$9909 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \Y $not$libresoc.v:161771$9909_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $not$libresoc.v:161772$9910 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } + connect \Y $not$libresoc.v:161772$9910_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:161774$9912 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$20 + connect \Y $not$libresoc.v:161774$9912_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:161776$9914 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$24 + connect \Y $not$libresoc.v:161776$9914_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:161778$9916 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$28 + connect \Y $not$libresoc.v:161778$9916_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:161781$9919 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$libresoc.v:161781$9919_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:161768$9906 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [5] \i [6] \i [7] \ni [3] } + connect \Y $reduce_or$libresoc.v:161768$9906_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:161770$9908 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } + connect \Y $reduce_or$libresoc.v:161770$9908_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:161773$9911 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } + connect \Y $reduce_or$libresoc.v:161773$9911_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:161775$9913 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } + connect \Y $reduce_or$libresoc.v:161775$9913_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:161777$9915 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } + connect \Y $reduce_or$libresoc.v:161777$9915_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_or $reduce_or$libresoc.v:161779$9917 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:161779$9917_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:161780$9918 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [7] \ni [1] } + connect \Y $reduce_or$libresoc.v:161780$9918_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:161782$9920 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [6] \i [7] \ni [2] } + connect \Y $reduce_or$libresoc.v:161782$9920_Y + end + connect \$7 $not$libresoc.v:161767$9905_Y + connect \$12 $reduce_or$libresoc.v:161768$9906_Y + connect \$11 $not$libresoc.v:161769$9907_Y + connect \$16 $reduce_or$libresoc.v:161770$9908_Y + connect \$15 $not$libresoc.v:161771$9909_Y + connect \$1 $not$libresoc.v:161772$9910_Y + connect \$20 $reduce_or$libresoc.v:161773$9911_Y + connect \$19 $not$libresoc.v:161774$9912_Y + connect \$24 $reduce_or$libresoc.v:161775$9913_Y + connect \$23 $not$libresoc.v:161776$9914_Y + connect \$28 $reduce_or$libresoc.v:161777$9915_Y + connect \$27 $not$libresoc.v:161778$9916_Y + connect \$31 $reduce_or$libresoc.v:161779$9917_Y + connect \$4 $reduce_or$libresoc.v:161780$9918_Y + connect \$3 $not$libresoc.v:161781$9919_Y + connect \$8 $reduce_or$libresoc.v:161782$9920_Y + connect \en_o \$31 + connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } + connect \t7 \$27 + connect \t6 \$23 + connect \t5 \$19 + connect \t4 \$15 + connect \t3 \$11 + connect \t2 \$7 + connect \t1 \$3 + connect \t0 \i [7] + connect \ni \$1 +end +attribute \src "libresoc.v:161798.1-161882.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_SPR.dec_cr_out.ppick" +attribute \generator "nMigen" +module \ppick$167 + attribute \src "libresoc.v:161855.17-161855.91" + wire $not$libresoc.v:161855$9921_Y + attribute \src "libresoc.v:161857.18-161857.93" + wire $not$libresoc.v:161857$9923_Y + attribute \src "libresoc.v:161859.18-161859.93" + wire $not$libresoc.v:161859$9925_Y + attribute \src "libresoc.v:161860.17-161860.138" + wire width 8 $not$libresoc.v:161860$9926_Y + attribute \src "libresoc.v:161862.18-161862.93" + wire $not$libresoc.v:161862$9928_Y + attribute \src "libresoc.v:161864.18-161864.93" + wire $not$libresoc.v:161864$9930_Y + attribute \src "libresoc.v:161866.18-161866.93" + wire $not$libresoc.v:161866$9932_Y + attribute \src "libresoc.v:161869.17-161869.91" + wire $not$libresoc.v:161869$9935_Y + attribute \src "libresoc.v:161856.18-161856.116" + wire $reduce_or$libresoc.v:161856$9922_Y + attribute \src "libresoc.v:161858.18-161858.122" + wire $reduce_or$libresoc.v:161858$9924_Y + attribute \src "libresoc.v:161861.18-161861.128" + wire $reduce_or$libresoc.v:161861$9927_Y + attribute \src "libresoc.v:161863.18-161863.134" + wire $reduce_or$libresoc.v:161863$9929_Y + attribute \src "libresoc.v:161865.18-161865.140" + wire $reduce_or$libresoc.v:161865$9931_Y + attribute \src "libresoc.v:161867.18-161867.90" + wire $reduce_or$libresoc.v:161867$9933_Y + attribute \src "libresoc.v:161868.17-161868.103" + wire $reduce_or$libresoc.v:161868$9934_Y + attribute \src "libresoc.v:161870.17-161870.109" + wire $reduce_or$libresoc.v:161870$9936_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire width 8 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire output 1 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire width 8 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 output 2 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:161855$9921 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $not$libresoc.v:161855$9921_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:161857$9923 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$12 + connect \Y $not$libresoc.v:161857$9923_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:161859$9925 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \Y $not$libresoc.v:161859$9925_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $not$libresoc.v:161860$9926 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } + connect \Y $not$libresoc.v:161860$9926_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:161862$9928 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$20 + connect \Y $not$libresoc.v:161862$9928_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:161864$9930 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$24 + connect \Y $not$libresoc.v:161864$9930_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:161866$9932 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$28 + connect \Y $not$libresoc.v:161866$9932_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:161869$9935 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$libresoc.v:161869$9935_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:161856$9922 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [5] \i [6] \i [7] \ni [3] } + connect \Y $reduce_or$libresoc.v:161856$9922_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:161858$9924 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } + connect \Y $reduce_or$libresoc.v:161858$9924_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:161861$9927 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } + connect \Y $reduce_or$libresoc.v:161861$9927_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:161863$9929 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } + connect \Y $reduce_or$libresoc.v:161863$9929_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:161865$9931 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } + connect \Y $reduce_or$libresoc.v:161865$9931_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_or $reduce_or$libresoc.v:161867$9933 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:161867$9933_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:161868$9934 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [7] \ni [1] } + connect \Y $reduce_or$libresoc.v:161868$9934_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:161870$9936 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [6] \i [7] \ni [2] } + connect \Y $reduce_or$libresoc.v:161870$9936_Y + end + connect \$7 $not$libresoc.v:161855$9921_Y + connect \$12 $reduce_or$libresoc.v:161856$9922_Y + connect \$11 $not$libresoc.v:161857$9923_Y + connect \$16 $reduce_or$libresoc.v:161858$9924_Y + connect \$15 $not$libresoc.v:161859$9925_Y + connect \$1 $not$libresoc.v:161860$9926_Y + connect \$20 $reduce_or$libresoc.v:161861$9927_Y + connect \$19 $not$libresoc.v:161862$9928_Y + connect \$24 $reduce_or$libresoc.v:161863$9929_Y + connect \$23 $not$libresoc.v:161864$9930_Y + connect \$28 $reduce_or$libresoc.v:161865$9931_Y + connect \$27 $not$libresoc.v:161866$9932_Y + connect \$31 $reduce_or$libresoc.v:161867$9933_Y + connect \$4 $reduce_or$libresoc.v:161868$9934_Y + connect \$3 $not$libresoc.v:161869$9935_Y + connect \$8 $reduce_or$libresoc.v:161870$9936_Y + connect \en_o \$31 + connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } + connect \t7 \$27 + connect \t6 \$23 + connect \t5 \$19 + connect \t4 \$15 + connect \t3 \$11 + connect \t2 \$7 + connect \t1 \$3 + connect \t0 \i [7] + connect \ni \$1 +end +attribute \src "libresoc.v:161886.1-161970.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_DIV.dec_cr_in.ppick" +attribute \generator "nMigen" +module \ppick$172 + attribute \src "libresoc.v:161943.17-161943.91" + wire $not$libresoc.v:161943$9937_Y + attribute \src "libresoc.v:161945.18-161945.93" + wire $not$libresoc.v:161945$9939_Y + attribute \src "libresoc.v:161947.18-161947.93" + wire $not$libresoc.v:161947$9941_Y + attribute \src "libresoc.v:161948.17-161948.138" + wire width 8 $not$libresoc.v:161948$9942_Y + attribute \src "libresoc.v:161950.18-161950.93" + wire $not$libresoc.v:161950$9944_Y + attribute \src "libresoc.v:161952.18-161952.93" + wire $not$libresoc.v:161952$9946_Y + attribute \src "libresoc.v:161954.18-161954.93" + wire $not$libresoc.v:161954$9948_Y + attribute \src "libresoc.v:161957.17-161957.91" + wire $not$libresoc.v:161957$9951_Y + attribute \src "libresoc.v:161944.18-161944.116" + wire $reduce_or$libresoc.v:161944$9938_Y + attribute \src "libresoc.v:161946.18-161946.122" + wire $reduce_or$libresoc.v:161946$9940_Y + attribute \src "libresoc.v:161949.18-161949.128" + wire $reduce_or$libresoc.v:161949$9943_Y + attribute \src "libresoc.v:161951.18-161951.134" + wire $reduce_or$libresoc.v:161951$9945_Y + attribute \src "libresoc.v:161953.18-161953.140" + wire $reduce_or$libresoc.v:161953$9947_Y + attribute \src "libresoc.v:161955.18-161955.90" + wire $reduce_or$libresoc.v:161955$9949_Y + attribute \src "libresoc.v:161956.17-161956.103" + wire $reduce_or$libresoc.v:161956$9950_Y + attribute \src "libresoc.v:161958.17-161958.109" + wire $reduce_or$libresoc.v:161958$9952_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire width 8 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 input 2 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire width 8 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:161943$9937 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $not$libresoc.v:161943$9937_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:161945$9939 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$12 + connect \Y $not$libresoc.v:161945$9939_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:161947$9941 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \Y $not$libresoc.v:161947$9941_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $not$libresoc.v:161948$9942 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } + connect \Y $not$libresoc.v:161948$9942_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:161950$9944 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$20 + connect \Y $not$libresoc.v:161950$9944_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:161952$9946 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$24 + connect \Y $not$libresoc.v:161952$9946_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:161954$9948 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$28 + connect \Y $not$libresoc.v:161954$9948_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:161957$9951 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$libresoc.v:161957$9951_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:161944$9938 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [5] \i [6] \i [7] \ni [3] } + connect \Y $reduce_or$libresoc.v:161944$9938_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:161946$9940 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } + connect \Y $reduce_or$libresoc.v:161946$9940_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:161949$9943 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } + connect \Y $reduce_or$libresoc.v:161949$9943_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:161951$9945 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } + connect \Y $reduce_or$libresoc.v:161951$9945_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:161953$9947 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } + connect \Y $reduce_or$libresoc.v:161953$9947_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_or $reduce_or$libresoc.v:161955$9949 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:161955$9949_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:161956$9950 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [7] \ni [1] } + connect \Y $reduce_or$libresoc.v:161956$9950_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:161958$9952 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [6] \i [7] \ni [2] } + connect \Y $reduce_or$libresoc.v:161958$9952_Y + end + connect \$7 $not$libresoc.v:161943$9937_Y + connect \$12 $reduce_or$libresoc.v:161944$9938_Y + connect \$11 $not$libresoc.v:161945$9939_Y + connect \$16 $reduce_or$libresoc.v:161946$9940_Y + connect \$15 $not$libresoc.v:161947$9941_Y + connect \$1 $not$libresoc.v:161948$9942_Y + connect \$20 $reduce_or$libresoc.v:161949$9943_Y + connect \$19 $not$libresoc.v:161950$9944_Y + connect \$24 $reduce_or$libresoc.v:161951$9945_Y + connect \$23 $not$libresoc.v:161952$9946_Y + connect \$28 $reduce_or$libresoc.v:161953$9947_Y + connect \$27 $not$libresoc.v:161954$9948_Y + connect \$31 $reduce_or$libresoc.v:161955$9949_Y + connect \$4 $reduce_or$libresoc.v:161956$9950_Y + connect \$3 $not$libresoc.v:161957$9951_Y + connect \$8 $reduce_or$libresoc.v:161958$9952_Y + connect \en_o \$31 + connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } + connect \t7 \$27 + connect \t6 \$23 + connect \t5 \$19 + connect \t4 \$15 + connect \t3 \$11 + connect \t2 \$7 + connect \t1 \$3 + connect \t0 \i [7] + connect \ni \$1 +end +attribute \src "libresoc.v:161974.1-162058.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_DIV.dec_cr_out.ppick" +attribute \generator "nMigen" +module \ppick$174 + attribute \src "libresoc.v:162031.17-162031.91" + wire $not$libresoc.v:162031$9953_Y + attribute \src "libresoc.v:162033.18-162033.93" + wire $not$libresoc.v:162033$9955_Y + attribute \src "libresoc.v:162035.18-162035.93" + wire $not$libresoc.v:162035$9957_Y + attribute \src "libresoc.v:162036.17-162036.138" + wire width 8 $not$libresoc.v:162036$9958_Y + attribute \src "libresoc.v:162038.18-162038.93" + wire $not$libresoc.v:162038$9960_Y + attribute \src "libresoc.v:162040.18-162040.93" + wire $not$libresoc.v:162040$9962_Y + attribute \src "libresoc.v:162042.18-162042.93" + wire $not$libresoc.v:162042$9964_Y + attribute \src "libresoc.v:162045.17-162045.91" + wire $not$libresoc.v:162045$9967_Y + attribute \src "libresoc.v:162032.18-162032.116" + wire $reduce_or$libresoc.v:162032$9954_Y + attribute \src "libresoc.v:162034.18-162034.122" + wire $reduce_or$libresoc.v:162034$9956_Y + attribute \src "libresoc.v:162037.18-162037.128" + wire $reduce_or$libresoc.v:162037$9959_Y + attribute \src "libresoc.v:162039.18-162039.134" + wire $reduce_or$libresoc.v:162039$9961_Y + attribute \src "libresoc.v:162041.18-162041.140" + wire $reduce_or$libresoc.v:162041$9963_Y + attribute \src "libresoc.v:162043.18-162043.90" + wire $reduce_or$libresoc.v:162043$9965_Y + attribute \src "libresoc.v:162044.17-162044.103" + wire $reduce_or$libresoc.v:162044$9966_Y + attribute \src "libresoc.v:162046.17-162046.109" + wire $reduce_or$libresoc.v:162046$9968_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire width 8 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire output 1 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire width 8 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 output 2 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:162031$9953 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $not$libresoc.v:162031$9953_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:162033$9955 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$12 + connect \Y $not$libresoc.v:162033$9955_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:162035$9957 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \Y $not$libresoc.v:162035$9957_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $not$libresoc.v:162036$9958 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } + connect \Y $not$libresoc.v:162036$9958_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:162038$9960 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$20 + connect \Y $not$libresoc.v:162038$9960_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:162040$9962 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$24 + connect \Y $not$libresoc.v:162040$9962_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:162042$9964 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$28 + connect \Y $not$libresoc.v:162042$9964_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:162045$9967 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$libresoc.v:162045$9967_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:162032$9954 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [5] \i [6] \i [7] \ni [3] } + connect \Y $reduce_or$libresoc.v:162032$9954_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:162034$9956 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } + connect \Y $reduce_or$libresoc.v:162034$9956_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:162037$9959 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } + connect \Y $reduce_or$libresoc.v:162037$9959_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:162039$9961 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } + connect \Y $reduce_or$libresoc.v:162039$9961_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:162041$9963 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } + connect \Y $reduce_or$libresoc.v:162041$9963_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_or $reduce_or$libresoc.v:162043$9965 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:162043$9965_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:162044$9966 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [7] \ni [1] } + connect \Y $reduce_or$libresoc.v:162044$9966_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:162046$9968 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [6] \i [7] \ni [2] } + connect \Y $reduce_or$libresoc.v:162046$9968_Y + end + connect \$7 $not$libresoc.v:162031$9953_Y + connect \$12 $reduce_or$libresoc.v:162032$9954_Y + connect \$11 $not$libresoc.v:162033$9955_Y + connect \$16 $reduce_or$libresoc.v:162034$9956_Y + connect \$15 $not$libresoc.v:162035$9957_Y + connect \$1 $not$libresoc.v:162036$9958_Y + connect \$20 $reduce_or$libresoc.v:162037$9959_Y + connect \$19 $not$libresoc.v:162038$9960_Y + connect \$24 $reduce_or$libresoc.v:162039$9961_Y + connect \$23 $not$libresoc.v:162040$9962_Y + connect \$28 $reduce_or$libresoc.v:162041$9963_Y + connect \$27 $not$libresoc.v:162042$9964_Y + connect \$31 $reduce_or$libresoc.v:162043$9965_Y + connect \$4 $reduce_or$libresoc.v:162044$9966_Y + connect \$3 $not$libresoc.v:162045$9967_Y + connect \$8 $reduce_or$libresoc.v:162046$9968_Y + connect \en_o \$31 + connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } + connect \t7 \$27 + connect \t6 \$23 + connect \t5 \$19 + connect \t4 \$15 + connect \t3 \$11 + connect \t2 \$7 + connect \t1 \$3 + connect \t0 \i [7] + connect \ni \$1 +end +attribute \src "libresoc.v:162062.1-162146.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_MUL.dec_cr_in.ppick" +attribute \generator "nMigen" +module \ppick$181 + attribute \src "libresoc.v:162119.17-162119.91" + wire $not$libresoc.v:162119$9969_Y + attribute \src "libresoc.v:162121.18-162121.93" + wire $not$libresoc.v:162121$9971_Y + attribute \src "libresoc.v:162123.18-162123.93" + wire $not$libresoc.v:162123$9973_Y + attribute \src "libresoc.v:162124.17-162124.138" + wire width 8 $not$libresoc.v:162124$9974_Y + attribute \src "libresoc.v:162126.18-162126.93" + wire $not$libresoc.v:162126$9976_Y + attribute \src "libresoc.v:162128.18-162128.93" + wire $not$libresoc.v:162128$9978_Y + attribute \src "libresoc.v:162130.18-162130.93" + wire $not$libresoc.v:162130$9980_Y + attribute \src "libresoc.v:162133.17-162133.91" + wire $not$libresoc.v:162133$9983_Y + attribute \src "libresoc.v:162120.18-162120.116" + wire $reduce_or$libresoc.v:162120$9970_Y + attribute \src "libresoc.v:162122.18-162122.122" + wire $reduce_or$libresoc.v:162122$9972_Y + attribute \src "libresoc.v:162125.18-162125.128" + wire $reduce_or$libresoc.v:162125$9975_Y + attribute \src "libresoc.v:162127.18-162127.134" + wire $reduce_or$libresoc.v:162127$9977_Y + attribute \src "libresoc.v:162129.18-162129.140" + wire $reduce_or$libresoc.v:162129$9979_Y + attribute \src "libresoc.v:162131.18-162131.90" + wire $reduce_or$libresoc.v:162131$9981_Y + attribute \src "libresoc.v:162132.17-162132.103" + wire $reduce_or$libresoc.v:162132$9982_Y + attribute \src "libresoc.v:162134.17-162134.109" + wire $reduce_or$libresoc.v:162134$9984_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire width 8 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 input 2 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire width 8 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:162119$9969 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $not$libresoc.v:162119$9969_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:162121$9971 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$12 + connect \Y $not$libresoc.v:162121$9971_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:162123$9973 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \Y $not$libresoc.v:162123$9973_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $not$libresoc.v:162124$9974 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } + connect \Y $not$libresoc.v:162124$9974_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:162126$9976 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$20 + connect \Y $not$libresoc.v:162126$9976_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:162128$9978 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$24 + connect \Y $not$libresoc.v:162128$9978_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:162130$9980 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$28 + connect \Y $not$libresoc.v:162130$9980_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:162133$9983 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$libresoc.v:162133$9983_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:162120$9970 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [5] \i [6] \i [7] \ni [3] } + connect \Y $reduce_or$libresoc.v:162120$9970_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:162122$9972 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } + connect \Y $reduce_or$libresoc.v:162122$9972_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:162125$9975 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } + connect \Y $reduce_or$libresoc.v:162125$9975_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:162127$9977 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } + connect \Y $reduce_or$libresoc.v:162127$9977_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:162129$9979 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } + connect \Y $reduce_or$libresoc.v:162129$9979_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_or $reduce_or$libresoc.v:162131$9981 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:162131$9981_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:162132$9982 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [7] \ni [1] } + connect \Y $reduce_or$libresoc.v:162132$9982_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:162134$9984 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [6] \i [7] \ni [2] } + connect \Y $reduce_or$libresoc.v:162134$9984_Y + end + connect \$7 $not$libresoc.v:162119$9969_Y + connect \$12 $reduce_or$libresoc.v:162120$9970_Y + connect \$11 $not$libresoc.v:162121$9971_Y + connect \$16 $reduce_or$libresoc.v:162122$9972_Y + connect \$15 $not$libresoc.v:162123$9973_Y + connect \$1 $not$libresoc.v:162124$9974_Y + connect \$20 $reduce_or$libresoc.v:162125$9975_Y + connect \$19 $not$libresoc.v:162126$9976_Y + connect \$24 $reduce_or$libresoc.v:162127$9977_Y + connect \$23 $not$libresoc.v:162128$9978_Y + connect \$28 $reduce_or$libresoc.v:162129$9979_Y + connect \$27 $not$libresoc.v:162130$9980_Y + connect \$31 $reduce_or$libresoc.v:162131$9981_Y + connect \$4 $reduce_or$libresoc.v:162132$9982_Y + connect \$3 $not$libresoc.v:162133$9983_Y + connect \$8 $reduce_or$libresoc.v:162134$9984_Y + connect \en_o \$31 + connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } + connect \t7 \$27 + connect \t6 \$23 + connect \t5 \$19 + connect \t4 \$15 + connect \t3 \$11 + connect \t2 \$7 + connect \t1 \$3 + connect \t0 \i [7] + connect \ni \$1 +end +attribute \src "libresoc.v:162150.1-162234.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_MUL.dec_cr_out.ppick" +attribute \generator "nMigen" +module \ppick$183 + attribute \src "libresoc.v:162207.17-162207.91" + wire $not$libresoc.v:162207$9985_Y + attribute \src "libresoc.v:162209.18-162209.93" + wire $not$libresoc.v:162209$9987_Y + attribute \src "libresoc.v:162211.18-162211.93" + wire $not$libresoc.v:162211$9989_Y + attribute \src "libresoc.v:162212.17-162212.138" + wire width 8 $not$libresoc.v:162212$9990_Y + attribute \src "libresoc.v:162214.18-162214.93" + wire $not$libresoc.v:162214$9992_Y + attribute \src "libresoc.v:162216.18-162216.93" + wire $not$libresoc.v:162216$9994_Y + attribute \src "libresoc.v:162218.18-162218.93" + wire $not$libresoc.v:162218$9996_Y + attribute \src "libresoc.v:162221.17-162221.91" + wire $not$libresoc.v:162221$9999_Y + attribute \src "libresoc.v:162208.18-162208.116" + wire $reduce_or$libresoc.v:162208$9986_Y + attribute \src "libresoc.v:162210.18-162210.122" + wire $reduce_or$libresoc.v:162210$9988_Y + attribute \src "libresoc.v:162213.18-162213.128" + wire $reduce_or$libresoc.v:162213$9991_Y + attribute \src "libresoc.v:162215.18-162215.134" + wire $reduce_or$libresoc.v:162215$9993_Y + attribute \src "libresoc.v:162217.18-162217.140" + wire $reduce_or$libresoc.v:162217$9995_Y + attribute \src "libresoc.v:162219.18-162219.90" + wire $reduce_or$libresoc.v:162219$9997_Y + attribute \src "libresoc.v:162220.17-162220.103" + wire $reduce_or$libresoc.v:162220$9998_Y + attribute \src "libresoc.v:162222.17-162222.109" + wire $reduce_or$libresoc.v:162222$10000_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire width 8 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire output 1 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire width 8 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 output 2 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:162207$9985 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $not$libresoc.v:162207$9985_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:162209$9987 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$12 + connect \Y $not$libresoc.v:162209$9987_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:162211$9989 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \Y $not$libresoc.v:162211$9989_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $not$libresoc.v:162212$9990 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } + connect \Y $not$libresoc.v:162212$9990_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:162214$9992 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$20 + connect \Y $not$libresoc.v:162214$9992_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:162216$9994 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$24 + connect \Y $not$libresoc.v:162216$9994_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:162218$9996 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$28 + connect \Y $not$libresoc.v:162218$9996_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:162221$9999 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$libresoc.v:162221$9999_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:162208$9986 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [5] \i [6] \i [7] \ni [3] } + connect \Y $reduce_or$libresoc.v:162208$9986_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:162210$9988 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } + connect \Y $reduce_or$libresoc.v:162210$9988_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:162213$9991 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } + connect \Y $reduce_or$libresoc.v:162213$9991_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:162215$9993 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } + connect \Y $reduce_or$libresoc.v:162215$9993_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:162217$9995 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } + connect \Y $reduce_or$libresoc.v:162217$9995_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_or $reduce_or$libresoc.v:162219$9997 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:162219$9997_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:162220$9998 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [7] \ni [1] } + connect \Y $reduce_or$libresoc.v:162220$9998_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:162222$10000 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [6] \i [7] \ni [2] } + connect \Y $reduce_or$libresoc.v:162222$10000_Y + end + connect \$7 $not$libresoc.v:162207$9985_Y + connect \$12 $reduce_or$libresoc.v:162208$9986_Y + connect \$11 $not$libresoc.v:162209$9987_Y + connect \$16 $reduce_or$libresoc.v:162210$9988_Y + connect \$15 $not$libresoc.v:162211$9989_Y + connect \$1 $not$libresoc.v:162212$9990_Y + connect \$20 $reduce_or$libresoc.v:162213$9991_Y + connect \$19 $not$libresoc.v:162214$9992_Y + connect \$24 $reduce_or$libresoc.v:162215$9993_Y + connect \$23 $not$libresoc.v:162216$9994_Y + connect \$28 $reduce_or$libresoc.v:162217$9995_Y + connect \$27 $not$libresoc.v:162218$9996_Y + connect \$31 $reduce_or$libresoc.v:162219$9997_Y + connect \$4 $reduce_or$libresoc.v:162220$9998_Y + connect \$3 $not$libresoc.v:162221$9999_Y + connect \$8 $reduce_or$libresoc.v:162222$10000_Y + connect \en_o \$31 + connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } + connect \t7 \$27 + connect \t6 \$23 + connect \t5 \$19 + connect \t4 \$15 + connect \t3 \$11 + connect \t2 \$7 + connect \t1 \$3 + connect \t0 \i [7] + connect \ni \$1 +end +attribute \src "libresoc.v:162238.1-162322.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_SHIFT_ROT.dec_cr_in.ppick" +attribute \generator "nMigen" +module \ppick$189 + attribute \src "libresoc.v:162295.17-162295.91" + wire $not$libresoc.v:162295$10001_Y + attribute \src "libresoc.v:162297.18-162297.93" + wire $not$libresoc.v:162297$10003_Y + attribute \src "libresoc.v:162299.18-162299.93" + wire $not$libresoc.v:162299$10005_Y + attribute \src "libresoc.v:162300.17-162300.138" + wire width 8 $not$libresoc.v:162300$10006_Y + attribute \src "libresoc.v:162302.18-162302.93" + wire $not$libresoc.v:162302$10008_Y + attribute \src "libresoc.v:162304.18-162304.93" + wire $not$libresoc.v:162304$10010_Y + attribute \src "libresoc.v:162306.18-162306.93" + wire $not$libresoc.v:162306$10012_Y + attribute \src "libresoc.v:162309.17-162309.91" + wire $not$libresoc.v:162309$10015_Y + attribute \src "libresoc.v:162296.18-162296.116" + wire $reduce_or$libresoc.v:162296$10002_Y + attribute \src "libresoc.v:162298.18-162298.122" + wire $reduce_or$libresoc.v:162298$10004_Y + attribute \src "libresoc.v:162301.18-162301.128" + wire $reduce_or$libresoc.v:162301$10007_Y + attribute \src "libresoc.v:162303.18-162303.134" + wire $reduce_or$libresoc.v:162303$10009_Y + attribute \src "libresoc.v:162305.18-162305.140" + wire $reduce_or$libresoc.v:162305$10011_Y + attribute \src "libresoc.v:162307.18-162307.90" + wire $reduce_or$libresoc.v:162307$10013_Y + attribute \src "libresoc.v:162308.17-162308.103" + wire $reduce_or$libresoc.v:162308$10014_Y + attribute \src "libresoc.v:162310.17-162310.109" + wire $reduce_or$libresoc.v:162310$10016_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire width 8 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 input 2 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire width 8 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:162295$10001 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $not$libresoc.v:162295$10001_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:162297$10003 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$12 + connect \Y $not$libresoc.v:162297$10003_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:162299$10005 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \Y $not$libresoc.v:162299$10005_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $not$libresoc.v:162300$10006 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } + connect \Y $not$libresoc.v:162300$10006_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:162302$10008 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$20 + connect \Y $not$libresoc.v:162302$10008_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:162304$10010 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$24 + connect \Y $not$libresoc.v:162304$10010_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:162306$10012 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$28 + connect \Y $not$libresoc.v:162306$10012_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:162309$10015 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$libresoc.v:162309$10015_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:162296$10002 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [5] \i [6] \i [7] \ni [3] } + connect \Y $reduce_or$libresoc.v:162296$10002_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:162298$10004 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } + connect \Y $reduce_or$libresoc.v:162298$10004_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:162301$10007 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } + connect \Y $reduce_or$libresoc.v:162301$10007_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:162303$10009 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } + connect \Y $reduce_or$libresoc.v:162303$10009_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:162305$10011 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } + connect \Y $reduce_or$libresoc.v:162305$10011_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_or $reduce_or$libresoc.v:162307$10013 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:162307$10013_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:162308$10014 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [7] \ni [1] } + connect \Y $reduce_or$libresoc.v:162308$10014_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:162310$10016 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [6] \i [7] \ni [2] } + connect \Y $reduce_or$libresoc.v:162310$10016_Y + end + connect \$7 $not$libresoc.v:162295$10001_Y + connect \$12 $reduce_or$libresoc.v:162296$10002_Y + connect \$11 $not$libresoc.v:162297$10003_Y + connect \$16 $reduce_or$libresoc.v:162298$10004_Y + connect \$15 $not$libresoc.v:162299$10005_Y + connect \$1 $not$libresoc.v:162300$10006_Y + connect \$20 $reduce_or$libresoc.v:162301$10007_Y + connect \$19 $not$libresoc.v:162302$10008_Y + connect \$24 $reduce_or$libresoc.v:162303$10009_Y + connect \$23 $not$libresoc.v:162304$10010_Y + connect \$28 $reduce_or$libresoc.v:162305$10011_Y + connect \$27 $not$libresoc.v:162306$10012_Y + connect \$31 $reduce_or$libresoc.v:162307$10013_Y + connect \$4 $reduce_or$libresoc.v:162308$10014_Y + connect \$3 $not$libresoc.v:162309$10015_Y + connect \$8 $reduce_or$libresoc.v:162310$10016_Y + connect \en_o \$31 + connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } + connect \t7 \$27 + connect \t6 \$23 + connect \t5 \$19 + connect \t4 \$15 + connect \t3 \$11 + connect \t2 \$7 + connect \t1 \$3 + connect \t0 \i [7] + connect \ni \$1 +end +attribute \src "libresoc.v:162326.1-162410.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_SHIFT_ROT.dec_cr_out.ppick" +attribute \generator "nMigen" +module \ppick$191 + attribute \src "libresoc.v:162383.17-162383.91" + wire $not$libresoc.v:162383$10017_Y + attribute \src "libresoc.v:162385.18-162385.93" + wire $not$libresoc.v:162385$10019_Y + attribute \src "libresoc.v:162387.18-162387.93" + wire $not$libresoc.v:162387$10021_Y + attribute \src "libresoc.v:162388.17-162388.138" + wire width 8 $not$libresoc.v:162388$10022_Y + attribute \src "libresoc.v:162390.18-162390.93" + wire $not$libresoc.v:162390$10024_Y + attribute \src "libresoc.v:162392.18-162392.93" + wire $not$libresoc.v:162392$10026_Y + attribute \src "libresoc.v:162394.18-162394.93" + wire $not$libresoc.v:162394$10028_Y + attribute \src "libresoc.v:162397.17-162397.91" + wire $not$libresoc.v:162397$10031_Y + attribute \src "libresoc.v:162384.18-162384.116" + wire $reduce_or$libresoc.v:162384$10018_Y + attribute \src "libresoc.v:162386.18-162386.122" + wire $reduce_or$libresoc.v:162386$10020_Y + attribute \src "libresoc.v:162389.18-162389.128" + wire $reduce_or$libresoc.v:162389$10023_Y + attribute \src "libresoc.v:162391.18-162391.134" + wire $reduce_or$libresoc.v:162391$10025_Y + attribute \src "libresoc.v:162393.18-162393.140" + wire $reduce_or$libresoc.v:162393$10027_Y + attribute \src "libresoc.v:162395.18-162395.90" + wire $reduce_or$libresoc.v:162395$10029_Y + attribute \src "libresoc.v:162396.17-162396.103" + wire $reduce_or$libresoc.v:162396$10030_Y + attribute \src "libresoc.v:162398.17-162398.109" + wire $reduce_or$libresoc.v:162398$10032_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire width 8 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire output 1 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire width 8 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 output 2 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:162383$10017 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $not$libresoc.v:162383$10017_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:162385$10019 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$12 + connect \Y $not$libresoc.v:162385$10019_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:162387$10021 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \Y $not$libresoc.v:162387$10021_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $not$libresoc.v:162388$10022 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } + connect \Y $not$libresoc.v:162388$10022_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:162390$10024 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$20 + connect \Y $not$libresoc.v:162390$10024_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:162392$10026 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$24 + connect \Y $not$libresoc.v:162392$10026_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:162394$10028 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$28 + connect \Y $not$libresoc.v:162394$10028_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:162397$10031 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$libresoc.v:162397$10031_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:162384$10018 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [5] \i [6] \i [7] \ni [3] } + connect \Y $reduce_or$libresoc.v:162384$10018_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:162386$10020 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } + connect \Y $reduce_or$libresoc.v:162386$10020_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:162389$10023 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } + connect \Y $reduce_or$libresoc.v:162389$10023_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:162391$10025 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } + connect \Y $reduce_or$libresoc.v:162391$10025_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:162393$10027 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } + connect \Y $reduce_or$libresoc.v:162393$10027_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_or $reduce_or$libresoc.v:162395$10029 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:162395$10029_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:162396$10030 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [7] \ni [1] } + connect \Y $reduce_or$libresoc.v:162396$10030_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:162398$10032 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [6] \i [7] \ni [2] } + connect \Y $reduce_or$libresoc.v:162398$10032_Y + end + connect \$7 $not$libresoc.v:162383$10017_Y + connect \$12 $reduce_or$libresoc.v:162384$10018_Y + connect \$11 $not$libresoc.v:162385$10019_Y + connect \$16 $reduce_or$libresoc.v:162386$10020_Y + connect \$15 $not$libresoc.v:162387$10021_Y + connect \$1 $not$libresoc.v:162388$10022_Y + connect \$20 $reduce_or$libresoc.v:162389$10023_Y + connect \$19 $not$libresoc.v:162390$10024_Y + connect \$24 $reduce_or$libresoc.v:162391$10025_Y + connect \$23 $not$libresoc.v:162392$10026_Y + connect \$28 $reduce_or$libresoc.v:162393$10027_Y + connect \$27 $not$libresoc.v:162394$10028_Y + connect \$31 $reduce_or$libresoc.v:162395$10029_Y + connect \$4 $reduce_or$libresoc.v:162396$10030_Y + connect \$3 $not$libresoc.v:162397$10031_Y + connect \$8 $reduce_or$libresoc.v:162398$10032_Y + connect \en_o \$31 + connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } + connect \t7 \$27 + connect \t6 \$23 + connect \t5 \$19 + connect \t4 \$15 + connect \t3 \$11 + connect \t2 \$7 + connect \t1 \$3 + connect \t0 \i [7] + connect \ni \$1 +end +attribute \src "libresoc.v:162414.1-162498.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_LDST.dec_cr_in.ppick" +attribute \generator "nMigen" +module \ppick$197 + attribute \src "libresoc.v:162471.17-162471.91" + wire $not$libresoc.v:162471$10033_Y + attribute \src "libresoc.v:162473.18-162473.93" + wire $not$libresoc.v:162473$10035_Y + attribute \src "libresoc.v:162475.18-162475.93" + wire $not$libresoc.v:162475$10037_Y + attribute \src "libresoc.v:162476.17-162476.138" + wire width 8 $not$libresoc.v:162476$10038_Y + attribute \src "libresoc.v:162478.18-162478.93" + wire $not$libresoc.v:162478$10040_Y + attribute \src "libresoc.v:162480.18-162480.93" + wire $not$libresoc.v:162480$10042_Y + attribute \src "libresoc.v:162482.18-162482.93" + wire $not$libresoc.v:162482$10044_Y + attribute \src "libresoc.v:162485.17-162485.91" + wire $not$libresoc.v:162485$10047_Y + attribute \src "libresoc.v:162472.18-162472.116" + wire $reduce_or$libresoc.v:162472$10034_Y + attribute \src "libresoc.v:162474.18-162474.122" + wire $reduce_or$libresoc.v:162474$10036_Y + attribute \src "libresoc.v:162477.18-162477.128" + wire $reduce_or$libresoc.v:162477$10039_Y + attribute \src "libresoc.v:162479.18-162479.134" + wire $reduce_or$libresoc.v:162479$10041_Y + attribute \src "libresoc.v:162481.18-162481.140" + wire $reduce_or$libresoc.v:162481$10043_Y + attribute \src "libresoc.v:162483.18-162483.90" + wire $reduce_or$libresoc.v:162483$10045_Y + attribute \src "libresoc.v:162484.17-162484.103" + wire $reduce_or$libresoc.v:162484$10046_Y + attribute \src "libresoc.v:162486.17-162486.109" + wire $reduce_or$libresoc.v:162486$10048_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire width 8 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 input 2 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire width 8 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:162471$10033 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $not$libresoc.v:162471$10033_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:162473$10035 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$12 + connect \Y $not$libresoc.v:162473$10035_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:162475$10037 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \Y $not$libresoc.v:162475$10037_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $not$libresoc.v:162476$10038 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } + connect \Y $not$libresoc.v:162476$10038_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:162478$10040 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$20 + connect \Y $not$libresoc.v:162478$10040_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:162480$10042 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$24 + connect \Y $not$libresoc.v:162480$10042_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:162482$10044 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$28 + connect \Y $not$libresoc.v:162482$10044_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:162485$10047 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$libresoc.v:162485$10047_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:162472$10034 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [5] \i [6] \i [7] \ni [3] } + connect \Y $reduce_or$libresoc.v:162472$10034_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:162474$10036 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } + connect \Y $reduce_or$libresoc.v:162474$10036_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:162477$10039 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } + connect \Y $reduce_or$libresoc.v:162477$10039_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:162479$10041 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } + connect \Y $reduce_or$libresoc.v:162479$10041_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:162481$10043 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } + connect \Y $reduce_or$libresoc.v:162481$10043_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_or $reduce_or$libresoc.v:162483$10045 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:162483$10045_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:162484$10046 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [7] \ni [1] } + connect \Y $reduce_or$libresoc.v:162484$10046_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:162486$10048 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [6] \i [7] \ni [2] } + connect \Y $reduce_or$libresoc.v:162486$10048_Y + end + connect \$7 $not$libresoc.v:162471$10033_Y + connect \$12 $reduce_or$libresoc.v:162472$10034_Y + connect \$11 $not$libresoc.v:162473$10035_Y + connect \$16 $reduce_or$libresoc.v:162474$10036_Y + connect \$15 $not$libresoc.v:162475$10037_Y + connect \$1 $not$libresoc.v:162476$10038_Y + connect \$20 $reduce_or$libresoc.v:162477$10039_Y + connect \$19 $not$libresoc.v:162478$10040_Y + connect \$24 $reduce_or$libresoc.v:162479$10041_Y + connect \$23 $not$libresoc.v:162480$10042_Y + connect \$28 $reduce_or$libresoc.v:162481$10043_Y + connect \$27 $not$libresoc.v:162482$10044_Y + connect \$31 $reduce_or$libresoc.v:162483$10045_Y + connect \$4 $reduce_or$libresoc.v:162484$10046_Y + connect \$3 $not$libresoc.v:162485$10047_Y + connect \$8 $reduce_or$libresoc.v:162486$10048_Y + connect \en_o \$31 + connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } + connect \t7 \$27 + connect \t6 \$23 + connect \t5 \$19 + connect \t4 \$15 + connect \t3 \$11 + connect \t2 \$7 + connect \t1 \$3 + connect \t0 \i [7] + connect \ni \$1 +end +attribute \src "libresoc.v:162502.1-162586.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_LDST.dec_cr_out.ppick" +attribute \generator "nMigen" +module \ppick$199 + attribute \src "libresoc.v:162559.17-162559.91" + wire $not$libresoc.v:162559$10049_Y + attribute \src "libresoc.v:162561.18-162561.93" + wire $not$libresoc.v:162561$10051_Y + attribute \src "libresoc.v:162563.18-162563.93" + wire $not$libresoc.v:162563$10053_Y + attribute \src "libresoc.v:162564.17-162564.138" + wire width 8 $not$libresoc.v:162564$10054_Y + attribute \src "libresoc.v:162566.18-162566.93" + wire $not$libresoc.v:162566$10056_Y + attribute \src "libresoc.v:162568.18-162568.93" + wire $not$libresoc.v:162568$10058_Y + attribute \src "libresoc.v:162570.18-162570.93" + wire $not$libresoc.v:162570$10060_Y + attribute \src "libresoc.v:162573.17-162573.91" + wire $not$libresoc.v:162573$10063_Y + attribute \src "libresoc.v:162560.18-162560.116" + wire $reduce_or$libresoc.v:162560$10050_Y + attribute \src "libresoc.v:162562.18-162562.122" + wire $reduce_or$libresoc.v:162562$10052_Y + attribute \src "libresoc.v:162565.18-162565.128" + wire $reduce_or$libresoc.v:162565$10055_Y + attribute \src "libresoc.v:162567.18-162567.134" + wire $reduce_or$libresoc.v:162567$10057_Y + attribute \src "libresoc.v:162569.18-162569.140" + wire $reduce_or$libresoc.v:162569$10059_Y + attribute \src "libresoc.v:162571.18-162571.90" + wire $reduce_or$libresoc.v:162571$10061_Y + attribute \src "libresoc.v:162572.17-162572.103" + wire $reduce_or$libresoc.v:162572$10062_Y + attribute \src "libresoc.v:162574.17-162574.109" + wire $reduce_or$libresoc.v:162574$10064_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire width 8 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire output 1 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire width 8 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 output 2 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:162559$10049 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $not$libresoc.v:162559$10049_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:162561$10051 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$12 + connect \Y $not$libresoc.v:162561$10051_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:162563$10053 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \Y $not$libresoc.v:162563$10053_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $not$libresoc.v:162564$10054 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } + connect \Y $not$libresoc.v:162564$10054_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:162566$10056 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$20 + connect \Y $not$libresoc.v:162566$10056_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:162568$10058 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$24 + connect \Y $not$libresoc.v:162568$10058_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:162570$10060 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$28 + connect \Y $not$libresoc.v:162570$10060_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:162573$10063 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$libresoc.v:162573$10063_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:162560$10050 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [5] \i [6] \i [7] \ni [3] } + connect \Y $reduce_or$libresoc.v:162560$10050_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:162562$10052 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } + connect \Y $reduce_or$libresoc.v:162562$10052_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:162565$10055 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } + connect \Y $reduce_or$libresoc.v:162565$10055_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:162567$10057 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } + connect \Y $reduce_or$libresoc.v:162567$10057_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:162569$10059 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } + connect \Y $reduce_or$libresoc.v:162569$10059_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_or $reduce_or$libresoc.v:162571$10061 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:162571$10061_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:162572$10062 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [7] \ni [1] } + connect \Y $reduce_or$libresoc.v:162572$10062_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:162574$10064 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [6] \i [7] \ni [2] } + connect \Y $reduce_or$libresoc.v:162574$10064_Y + end + connect \$7 $not$libresoc.v:162559$10049_Y + connect \$12 $reduce_or$libresoc.v:162560$10050_Y + connect \$11 $not$libresoc.v:162561$10051_Y + connect \$16 $reduce_or$libresoc.v:162562$10052_Y + connect \$15 $not$libresoc.v:162563$10053_Y + connect \$1 $not$libresoc.v:162564$10054_Y + connect \$20 $reduce_or$libresoc.v:162565$10055_Y + connect \$19 $not$libresoc.v:162566$10056_Y + connect \$24 $reduce_or$libresoc.v:162567$10057_Y + connect \$23 $not$libresoc.v:162568$10058_Y + connect \$28 $reduce_or$libresoc.v:162569$10059_Y + connect \$27 $not$libresoc.v:162570$10060_Y + connect \$31 $reduce_or$libresoc.v:162571$10061_Y + connect \$4 $reduce_or$libresoc.v:162572$10062_Y + connect \$3 $not$libresoc.v:162573$10063_Y + connect \$8 $reduce_or$libresoc.v:162574$10064_Y + connect \en_o \$31 + connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } + connect \t7 \$27 + connect \t6 \$23 + connect \t5 \$19 + connect \t4 \$15 + connect \t3 \$11 + connect \t2 \$7 + connect \t1 \$3 + connect \t0 \i [7] + connect \ni \$1 +end +attribute \src "libresoc.v:162590.1-162674.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.dec2.dec_cr_in.ppick" +attribute \generator "nMigen" +module \ppick$206 + attribute \src "libresoc.v:162647.17-162647.91" + wire $not$libresoc.v:162647$10065_Y + attribute \src "libresoc.v:162649.18-162649.93" + wire $not$libresoc.v:162649$10067_Y + attribute \src "libresoc.v:162651.18-162651.93" + wire $not$libresoc.v:162651$10069_Y + attribute \src "libresoc.v:162652.17-162652.138" + wire width 8 $not$libresoc.v:162652$10070_Y + attribute \src "libresoc.v:162654.18-162654.93" + wire $not$libresoc.v:162654$10072_Y + attribute \src "libresoc.v:162656.18-162656.93" + wire $not$libresoc.v:162656$10074_Y + attribute \src "libresoc.v:162658.18-162658.93" + wire $not$libresoc.v:162658$10076_Y + attribute \src "libresoc.v:162661.17-162661.91" + wire $not$libresoc.v:162661$10079_Y + attribute \src "libresoc.v:162648.18-162648.116" + wire $reduce_or$libresoc.v:162648$10066_Y + attribute \src "libresoc.v:162650.18-162650.122" + wire $reduce_or$libresoc.v:162650$10068_Y + attribute \src "libresoc.v:162653.18-162653.128" + wire $reduce_or$libresoc.v:162653$10071_Y + attribute \src "libresoc.v:162655.18-162655.134" + wire $reduce_or$libresoc.v:162655$10073_Y + attribute \src "libresoc.v:162657.18-162657.140" + wire $reduce_or$libresoc.v:162657$10075_Y + attribute \src "libresoc.v:162659.18-162659.90" + wire $reduce_or$libresoc.v:162659$10077_Y + attribute \src "libresoc.v:162660.17-162660.103" + wire $reduce_or$libresoc.v:162660$10078_Y + attribute \src "libresoc.v:162662.17-162662.109" + wire $reduce_or$libresoc.v:162662$10080_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire width 8 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 input 2 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire width 8 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:162647$10065 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $not$libresoc.v:162647$10065_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:162649$10067 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$12 + connect \Y $not$libresoc.v:162649$10067_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:162651$10069 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \Y $not$libresoc.v:162651$10069_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $not$libresoc.v:162652$10070 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } + connect \Y $not$libresoc.v:162652$10070_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:162654$10072 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$20 + connect \Y $not$libresoc.v:162654$10072_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:162656$10074 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$24 + connect \Y $not$libresoc.v:162656$10074_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:162658$10076 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$28 + connect \Y $not$libresoc.v:162658$10076_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:162661$10079 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$libresoc.v:162661$10079_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:162648$10066 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [5] \i [6] \i [7] \ni [3] } + connect \Y $reduce_or$libresoc.v:162648$10066_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:162650$10068 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } + connect \Y $reduce_or$libresoc.v:162650$10068_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:162653$10071 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } + connect \Y $reduce_or$libresoc.v:162653$10071_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:162655$10073 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } + connect \Y $reduce_or$libresoc.v:162655$10073_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:162657$10075 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } + connect \Y $reduce_or$libresoc.v:162657$10075_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_or $reduce_or$libresoc.v:162659$10077 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:162659$10077_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:162660$10078 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [7] \ni [1] } + connect \Y $reduce_or$libresoc.v:162660$10078_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:162662$10080 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [6] \i [7] \ni [2] } + connect \Y $reduce_or$libresoc.v:162662$10080_Y + end + connect \$7 $not$libresoc.v:162647$10065_Y + connect \$12 $reduce_or$libresoc.v:162648$10066_Y + connect \$11 $not$libresoc.v:162649$10067_Y + connect \$16 $reduce_or$libresoc.v:162650$10068_Y + connect \$15 $not$libresoc.v:162651$10069_Y + connect \$1 $not$libresoc.v:162652$10070_Y + connect \$20 $reduce_or$libresoc.v:162653$10071_Y + connect \$19 $not$libresoc.v:162654$10072_Y + connect \$24 $reduce_or$libresoc.v:162655$10073_Y + connect \$23 $not$libresoc.v:162656$10074_Y + connect \$28 $reduce_or$libresoc.v:162657$10075_Y + connect \$27 $not$libresoc.v:162658$10076_Y + connect \$31 $reduce_or$libresoc.v:162659$10077_Y + connect \$4 $reduce_or$libresoc.v:162660$10078_Y + connect \$3 $not$libresoc.v:162661$10079_Y + connect \$8 $reduce_or$libresoc.v:162662$10080_Y + connect \en_o \$31 + connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } + connect \t7 \$27 + connect \t6 \$23 + connect \t5 \$19 + connect \t4 \$15 + connect \t3 \$11 + connect \t2 \$7 + connect \t1 \$3 + connect \t0 \i [7] + connect \ni \$1 +end +attribute \src "libresoc.v:162678.1-162762.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.dec2.dec_cr_out.ppick" +attribute \generator "nMigen" +module \ppick$208 + attribute \src "libresoc.v:162735.17-162735.91" + wire $not$libresoc.v:162735$10081_Y + attribute \src "libresoc.v:162737.18-162737.93" + wire $not$libresoc.v:162737$10083_Y + attribute \src "libresoc.v:162739.18-162739.93" + wire $not$libresoc.v:162739$10085_Y + attribute \src "libresoc.v:162740.17-162740.138" + wire width 8 $not$libresoc.v:162740$10086_Y + attribute \src "libresoc.v:162742.18-162742.93" + wire $not$libresoc.v:162742$10088_Y + attribute \src "libresoc.v:162744.18-162744.93" + wire $not$libresoc.v:162744$10090_Y + attribute \src "libresoc.v:162746.18-162746.93" + wire $not$libresoc.v:162746$10092_Y + attribute \src "libresoc.v:162749.17-162749.91" + wire $not$libresoc.v:162749$10095_Y + attribute \src "libresoc.v:162736.18-162736.116" + wire $reduce_or$libresoc.v:162736$10082_Y + attribute \src "libresoc.v:162738.18-162738.122" + wire $reduce_or$libresoc.v:162738$10084_Y + attribute \src "libresoc.v:162741.18-162741.128" + wire $reduce_or$libresoc.v:162741$10087_Y + attribute \src "libresoc.v:162743.18-162743.134" + wire $reduce_or$libresoc.v:162743$10089_Y + attribute \src "libresoc.v:162745.18-162745.140" + wire $reduce_or$libresoc.v:162745$10091_Y + attribute \src "libresoc.v:162747.18-162747.90" + wire $reduce_or$libresoc.v:162747$10093_Y + attribute \src "libresoc.v:162748.17-162748.103" + wire $reduce_or$libresoc.v:162748$10094_Y + attribute \src "libresoc.v:162750.17-162750.109" + wire $reduce_or$libresoc.v:162750$10096_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire width 8 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire output 1 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire width 8 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 output 2 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:162735$10081 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $not$libresoc.v:162735$10081_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:162737$10083 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$12 + connect \Y $not$libresoc.v:162737$10083_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:162739$10085 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \Y $not$libresoc.v:162739$10085_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $not$libresoc.v:162740$10086 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } + connect \Y $not$libresoc.v:162740$10086_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:162742$10088 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$20 + connect \Y $not$libresoc.v:162742$10088_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:162744$10090 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$24 + connect \Y $not$libresoc.v:162744$10090_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:162746$10092 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$28 + connect \Y $not$libresoc.v:162746$10092_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:162749$10095 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$libresoc.v:162749$10095_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:162736$10082 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [5] \i [6] \i [7] \ni [3] } + connect \Y $reduce_or$libresoc.v:162736$10082_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:162738$10084 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } + connect \Y $reduce_or$libresoc.v:162738$10084_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:162741$10087 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } + connect \Y $reduce_or$libresoc.v:162741$10087_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:162743$10089 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } + connect \Y $reduce_or$libresoc.v:162743$10089_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:162745$10091 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } + connect \Y $reduce_or$libresoc.v:162745$10091_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_or $reduce_or$libresoc.v:162747$10093 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:162747$10093_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:162748$10094 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [7] \ni [1] } + connect \Y $reduce_or$libresoc.v:162748$10094_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:162750$10096 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [6] \i [7] \ni [2] } + connect \Y $reduce_or$libresoc.v:162750$10096_Y + end + connect \$7 $not$libresoc.v:162735$10081_Y + connect \$12 $reduce_or$libresoc.v:162736$10082_Y + connect \$11 $not$libresoc.v:162737$10083_Y + connect \$16 $reduce_or$libresoc.v:162738$10084_Y + connect \$15 $not$libresoc.v:162739$10085_Y + connect \$1 $not$libresoc.v:162740$10086_Y + connect \$20 $reduce_or$libresoc.v:162741$10087_Y + connect \$19 $not$libresoc.v:162742$10088_Y + connect \$24 $reduce_or$libresoc.v:162743$10089_Y + connect \$23 $not$libresoc.v:162744$10090_Y + connect \$28 $reduce_or$libresoc.v:162745$10091_Y + connect \$27 $not$libresoc.v:162746$10092_Y + connect \$31 $reduce_or$libresoc.v:162747$10093_Y + connect \$4 $reduce_or$libresoc.v:162748$10094_Y + connect \$3 $not$libresoc.v:162749$10095_Y + connect \$8 $reduce_or$libresoc.v:162750$10096_Y + connect \en_o \$31 + connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } + connect \t7 \$27 + connect \t6 \$23 + connect \t5 \$19 + connect \t4 \$15 + connect \t3 \$11 + connect \t2 \$7 + connect \t1 \$3 + connect \t0 \i [7] + connect \ni \$1 +end +attribute \src "libresoc.v:162766.1-162796.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.rdpick_CR_cr_a" +attribute \generator "nMigen" +module \rdpick_CR_cr_a + attribute \src "libresoc.v:162787.17-162787.89" + wire width 2 $not$libresoc.v:162787$10097_Y + attribute \src "libresoc.v:162789.17-162789.91" + wire $not$libresoc.v:162789$10099_Y + attribute \src "libresoc.v:162788.17-162788.103" + wire $reduce_or$libresoc.v:162788$10098_Y + attribute \src "libresoc.v:162790.17-162790.89" + wire $reduce_or$libresoc.v:162790$10100_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire width 2 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 2 input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire width 2 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 2 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $not$libresoc.v:162787$10097 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \i + connect \Y $not$libresoc.v:162787$10097_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:162789$10099 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$libresoc.v:162789$10099_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:162788$10098 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [0] \ni [1] } + connect \Y $reduce_or$libresoc.v:162788$10098_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_or $reduce_or$libresoc.v:162790$10100 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:162790$10100_Y + end + connect \$1 $not$libresoc.v:162787$10097_Y + connect \$4 $reduce_or$libresoc.v:162788$10098_Y + connect \$3 $not$libresoc.v:162789$10099_Y + connect \$7 $reduce_or$libresoc.v:162790$10100_Y + connect \en_o \$7 + connect \o { \t1 \t0 } + connect \t1 \$3 + connect \t0 \i [0] + connect \ni \$1 +end +attribute \src "libresoc.v:162800.1-162821.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.rdpick_CR_cr_b" +attribute \generator "nMigen" +module \rdpick_CR_cr_b + attribute \src "libresoc.v:162815.17-162815.89" + wire $not$libresoc.v:162815$10101_Y + attribute \src "libresoc.v:162816.17-162816.89" + wire $reduce_or$libresoc.v:162816$10102_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $not$libresoc.v:162815$10101 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \i + connect \Y $not$libresoc.v:162815$10101_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_or $reduce_or$libresoc.v:162816$10102 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:162816$10102_Y + end + connect \$1 $not$libresoc.v:162815$10101_Y + connect \$3 $reduce_or$libresoc.v:162816$10102_Y + connect \en_o \$3 + connect \o \t0 + connect \t0 \i + connect \ni \$1 +end +attribute \src "libresoc.v:162825.1-162846.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.rdpick_CR_cr_c" +attribute \generator "nMigen" +module \rdpick_CR_cr_c + attribute \src "libresoc.v:162840.17-162840.89" + wire $not$libresoc.v:162840$10103_Y + attribute \src "libresoc.v:162841.17-162841.89" + wire $reduce_or$libresoc.v:162841$10104_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $not$libresoc.v:162840$10103 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \i + connect \Y $not$libresoc.v:162840$10103_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_or $reduce_or$libresoc.v:162841$10104 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:162841$10104_Y + end + connect \$1 $not$libresoc.v:162840$10103_Y + connect \$3 $reduce_or$libresoc.v:162841$10104_Y + connect \en_o \$3 + connect \o \t0 + connect \t0 \i + connect \ni \$1 +end +attribute \src "libresoc.v:162850.1-162871.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.rdpick_CR_full_cr" +attribute \generator "nMigen" +module \rdpick_CR_full_cr + attribute \src "libresoc.v:162865.17-162865.89" + wire $not$libresoc.v:162865$10105_Y + attribute \src "libresoc.v:162866.17-162866.89" + wire $reduce_or$libresoc.v:162866$10106_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $not$libresoc.v:162865$10105 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \i + connect \Y $not$libresoc.v:162865$10105_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_or $reduce_or$libresoc.v:162866$10106 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:162866$10106_Y + end + connect \$1 $not$libresoc.v:162865$10105_Y + connect \$3 $reduce_or$libresoc.v:162866$10106_Y + connect \en_o \$3 + connect \o \t0 + connect \t0 \i + connect \ni \$1 +end +attribute \src "libresoc.v:162875.1-162914.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.rdpick_FAST_fast1" +attribute \generator "nMigen" +module \rdpick_FAST_fast1 + attribute \src "libresoc.v:162902.17-162902.91" + wire $not$libresoc.v:162902$10107_Y + attribute \src "libresoc.v:162904.17-162904.89" + wire width 3 $not$libresoc.v:162904$10109_Y + attribute \src "libresoc.v:162906.17-162906.91" + wire $not$libresoc.v:162906$10111_Y + attribute \src "libresoc.v:162903.18-162903.90" + wire $reduce_or$libresoc.v:162903$10108_Y + attribute \src "libresoc.v:162905.17-162905.103" + wire $reduce_or$libresoc.v:162905$10110_Y + attribute \src "libresoc.v:162907.17-162907.105" + wire $reduce_or$libresoc.v:162907$10112_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire width 3 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 3 input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire width 3 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 3 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:162902$10107 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $not$libresoc.v:162902$10107_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $not$libresoc.v:162904$10109 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \i + connect \Y $not$libresoc.v:162904$10109_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:162906$10111 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$libresoc.v:162906$10111_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_or $reduce_or$libresoc.v:162903$10108 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:162903$10108_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:162905$10110 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [0] \ni [1] } + connect \Y $reduce_or$libresoc.v:162905$10110_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:162907$10112 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [1:0] \ni [2] } + connect \Y $reduce_or$libresoc.v:162907$10112_Y + end + connect \$7 $not$libresoc.v:162902$10107_Y + connect \$11 $reduce_or$libresoc.v:162903$10108_Y + connect \$1 $not$libresoc.v:162904$10109_Y + connect \$4 $reduce_or$libresoc.v:162905$10110_Y + connect \$3 $not$libresoc.v:162906$10111_Y + connect \$8 $reduce_or$libresoc.v:162907$10112_Y + connect \en_o \$11 + connect \o { \t2 \t1 \t0 } + connect \t2 \$7 + connect \t1 \$3 + connect \t0 \i [0] + connect \ni \$1 +end +attribute \src "libresoc.v:162918.1-162948.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.rdpick_FAST_fast2" +attribute \generator "nMigen" +module \rdpick_FAST_fast2 + attribute \src "libresoc.v:162939.17-162939.89" + wire width 2 $not$libresoc.v:162939$10113_Y + attribute \src "libresoc.v:162941.17-162941.91" + wire $not$libresoc.v:162941$10115_Y + attribute \src "libresoc.v:162940.17-162940.103" + wire $reduce_or$libresoc.v:162940$10114_Y + attribute \src "libresoc.v:162942.17-162942.89" + wire $reduce_or$libresoc.v:162942$10116_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire width 2 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 2 input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire width 2 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 2 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $not$libresoc.v:162939$10113 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \i + connect \Y $not$libresoc.v:162939$10113_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:162941$10115 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$libresoc.v:162941$10115_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:162940$10114 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [0] \ni [1] } + connect \Y $reduce_or$libresoc.v:162940$10114_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_or $reduce_or$libresoc.v:162942$10116 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:162942$10116_Y + end + connect \$1 $not$libresoc.v:162939$10113_Y + connect \$4 $reduce_or$libresoc.v:162940$10114_Y + connect \$3 $not$libresoc.v:162941$10115_Y + connect \$7 $reduce_or$libresoc.v:162942$10116_Y + connect \en_o \$7 + connect \o { \t1 \t0 } + connect \t1 \$3 + connect \t0 \i [0] + connect \ni \$1 +end +attribute \src "libresoc.v:162952.1-163045.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.rdpick_INT_ra" +attribute \generator "nMigen" +module \rdpick_INT_ra + attribute \src "libresoc.v:163015.17-163015.91" + wire $not$libresoc.v:163015$10117_Y + attribute \src "libresoc.v:163017.18-163017.93" + wire $not$libresoc.v:163017$10119_Y + attribute \src "libresoc.v:163019.18-163019.93" + wire $not$libresoc.v:163019$10121_Y + attribute \src "libresoc.v:163020.17-163020.89" + wire width 9 $not$libresoc.v:163020$10122_Y + attribute \src "libresoc.v:163022.18-163022.93" + wire $not$libresoc.v:163022$10124_Y + attribute \src "libresoc.v:163024.18-163024.93" + wire $not$libresoc.v:163024$10126_Y + attribute \src "libresoc.v:163026.18-163026.93" + wire $not$libresoc.v:163026$10128_Y + attribute \src "libresoc.v:163028.18-163028.93" + wire $not$libresoc.v:163028$10130_Y + attribute \src "libresoc.v:163031.17-163031.91" + wire $not$libresoc.v:163031$10133_Y + attribute \src "libresoc.v:163016.18-163016.106" + wire $reduce_or$libresoc.v:163016$10118_Y + attribute \src "libresoc.v:163018.18-163018.106" + wire $reduce_or$libresoc.v:163018$10120_Y + attribute \src "libresoc.v:163021.18-163021.106" + wire $reduce_or$libresoc.v:163021$10123_Y + attribute \src "libresoc.v:163023.18-163023.106" + wire $reduce_or$libresoc.v:163023$10125_Y + attribute \src "libresoc.v:163025.18-163025.106" + wire $reduce_or$libresoc.v:163025$10127_Y + attribute \src "libresoc.v:163027.18-163027.106" + wire $reduce_or$libresoc.v:163027$10129_Y + attribute \src "libresoc.v:163029.18-163029.90" + wire $reduce_or$libresoc.v:163029$10131_Y + attribute \src "libresoc.v:163030.17-163030.103" + wire $reduce_or$libresoc.v:163030$10132_Y + attribute \src "libresoc.v:163032.17-163032.105" + wire $reduce_or$libresoc.v:163032$10134_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire width 9 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$32 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire \$35 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 9 input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire width 9 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 9 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:163015$10117 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $not$libresoc.v:163015$10117_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:163017$10119 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$12 + connect \Y $not$libresoc.v:163017$10119_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:163019$10121 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \Y $not$libresoc.v:163019$10121_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $not$libresoc.v:163020$10122 + parameter \A_SIGNED 0 + parameter \A_WIDTH 9 + parameter \Y_WIDTH 9 + connect \A \i + connect \Y $not$libresoc.v:163020$10122_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:163022$10124 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$20 + connect \Y $not$libresoc.v:163022$10124_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:163024$10126 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$24 + connect \Y $not$libresoc.v:163024$10126_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:163026$10128 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$28 + connect \Y $not$libresoc.v:163026$10128_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:163028$10130 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$32 + connect \Y $not$libresoc.v:163028$10130_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:163031$10133 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$libresoc.v:163031$10133_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:163016$10118 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [2:0] \ni [3] } + connect \Y $reduce_or$libresoc.v:163016$10118_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:163018$10120 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [3:0] \ni [4] } + connect \Y $reduce_or$libresoc.v:163018$10120_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:163021$10123 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [4:0] \ni [5] } + connect \Y $reduce_or$libresoc.v:163021$10123_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:163023$10125 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A { \i [5:0] \ni [6] } + connect \Y $reduce_or$libresoc.v:163023$10125_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:163025$10127 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A { \i [6:0] \ni [7] } + connect \Y $reduce_or$libresoc.v:163025$10127_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:163027$10129 + parameter \A_SIGNED 0 + parameter \A_WIDTH 9 + parameter \Y_WIDTH 1 + connect \A { \i [7:0] \ni [8] } + connect \Y $reduce_or$libresoc.v:163027$10129_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_or $reduce_or$libresoc.v:163029$10131 + parameter \A_SIGNED 0 + parameter \A_WIDTH 9 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:163029$10131_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:163030$10132 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [0] \ni [1] } + connect \Y $reduce_or$libresoc.v:163030$10132_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:163032$10134 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [1:0] \ni [2] } + connect \Y $reduce_or$libresoc.v:163032$10134_Y + end + connect \$7 $not$libresoc.v:163015$10117_Y + connect \$12 $reduce_or$libresoc.v:163016$10118_Y + connect \$11 $not$libresoc.v:163017$10119_Y + connect \$16 $reduce_or$libresoc.v:163018$10120_Y + connect \$15 $not$libresoc.v:163019$10121_Y + connect \$1 $not$libresoc.v:163020$10122_Y + connect \$20 $reduce_or$libresoc.v:163021$10123_Y + connect \$19 $not$libresoc.v:163022$10124_Y + connect \$24 $reduce_or$libresoc.v:163023$10125_Y + connect \$23 $not$libresoc.v:163024$10126_Y + connect \$28 $reduce_or$libresoc.v:163025$10127_Y + connect \$27 $not$libresoc.v:163026$10128_Y + connect \$32 $reduce_or$libresoc.v:163027$10129_Y + connect \$31 $not$libresoc.v:163028$10130_Y + connect \$35 $reduce_or$libresoc.v:163029$10131_Y + connect \$4 $reduce_or$libresoc.v:163030$10132_Y + connect \$3 $not$libresoc.v:163031$10133_Y + connect \$8 $reduce_or$libresoc.v:163032$10134_Y + connect \en_o \$35 + connect \o { \t8 \t7 \t6 \t5 \t4 \t3 \t2 \t1 \t0 } + connect \t8 \$31 + connect \t7 \$27 + connect \t6 \$23 + connect \t5 \$19 + connect \t4 \$15 + connect \t3 \$11 + connect \t2 \$7 + connect \t1 \$3 + connect \t0 \i [0] + connect \ni \$1 +end +attribute \src "libresoc.v:163049.1-163133.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.rdpick_INT_rb" +attribute \generator "nMigen" +module \rdpick_INT_rb + attribute \src "libresoc.v:163106.17-163106.91" + wire $not$libresoc.v:163106$10135_Y + attribute \src "libresoc.v:163108.18-163108.93" + wire $not$libresoc.v:163108$10137_Y + attribute \src "libresoc.v:163110.18-163110.93" + wire $not$libresoc.v:163110$10139_Y + attribute \src "libresoc.v:163111.17-163111.89" + wire width 8 $not$libresoc.v:163111$10140_Y + attribute \src "libresoc.v:163113.18-163113.93" + wire $not$libresoc.v:163113$10142_Y + attribute \src "libresoc.v:163115.18-163115.93" + wire $not$libresoc.v:163115$10144_Y + attribute \src "libresoc.v:163117.18-163117.93" + wire $not$libresoc.v:163117$10146_Y + attribute \src "libresoc.v:163120.17-163120.91" + wire $not$libresoc.v:163120$10149_Y + attribute \src "libresoc.v:163107.18-163107.106" + wire $reduce_or$libresoc.v:163107$10136_Y + attribute \src "libresoc.v:163109.18-163109.106" + wire $reduce_or$libresoc.v:163109$10138_Y + attribute \src "libresoc.v:163112.18-163112.106" + wire $reduce_or$libresoc.v:163112$10141_Y + attribute \src "libresoc.v:163114.18-163114.106" + wire $reduce_or$libresoc.v:163114$10143_Y + attribute \src "libresoc.v:163116.18-163116.106" + wire $reduce_or$libresoc.v:163116$10145_Y + attribute \src "libresoc.v:163118.18-163118.90" + wire $reduce_or$libresoc.v:163118$10147_Y + attribute \src "libresoc.v:163119.17-163119.103" + wire $reduce_or$libresoc.v:163119$10148_Y + attribute \src "libresoc.v:163121.17-163121.105" + wire $reduce_or$libresoc.v:163121$10150_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire width 8 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire width 8 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:163106$10135 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $not$libresoc.v:163106$10135_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:163108$10137 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$12 + connect \Y $not$libresoc.v:163108$10137_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:163110$10139 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \Y $not$libresoc.v:163110$10139_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $not$libresoc.v:163111$10140 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A \i + connect \Y $not$libresoc.v:163111$10140_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:163113$10142 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$20 + connect \Y $not$libresoc.v:163113$10142_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:163115$10144 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$24 + connect \Y $not$libresoc.v:163115$10144_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:163117$10146 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$28 + connect \Y $not$libresoc.v:163117$10146_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:163120$10149 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$libresoc.v:163120$10149_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:163107$10136 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [2:0] \ni [3] } + connect \Y $reduce_or$libresoc.v:163107$10136_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:163109$10138 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [3:0] \ni [4] } + connect \Y $reduce_or$libresoc.v:163109$10138_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:163112$10141 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [4:0] \ni [5] } + connect \Y $reduce_or$libresoc.v:163112$10141_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:163114$10143 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A { \i [5:0] \ni [6] } + connect \Y $reduce_or$libresoc.v:163114$10143_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:163116$10145 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A { \i [6:0] \ni [7] } + connect \Y $reduce_or$libresoc.v:163116$10145_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_or $reduce_or$libresoc.v:163118$10147 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:163118$10147_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:163119$10148 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [0] \ni [1] } + connect \Y $reduce_or$libresoc.v:163119$10148_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:163121$10150 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [1:0] \ni [2] } + connect \Y $reduce_or$libresoc.v:163121$10150_Y + end + connect \$7 $not$libresoc.v:163106$10135_Y + connect \$12 $reduce_or$libresoc.v:163107$10136_Y + connect \$11 $not$libresoc.v:163108$10137_Y + connect \$16 $reduce_or$libresoc.v:163109$10138_Y + connect \$15 $not$libresoc.v:163110$10139_Y + connect \$1 $not$libresoc.v:163111$10140_Y + connect \$20 $reduce_or$libresoc.v:163112$10141_Y + connect \$19 $not$libresoc.v:163113$10142_Y + connect \$24 $reduce_or$libresoc.v:163114$10143_Y + connect \$23 $not$libresoc.v:163115$10144_Y + connect \$28 $reduce_or$libresoc.v:163116$10145_Y + connect \$27 $not$libresoc.v:163117$10146_Y + connect \$31 $reduce_or$libresoc.v:163118$10147_Y + connect \$4 $reduce_or$libresoc.v:163119$10148_Y + connect \$3 $not$libresoc.v:163120$10149_Y + connect \$8 $reduce_or$libresoc.v:163121$10150_Y + connect \en_o \$31 + connect \o { \t7 \t6 \t5 \t4 \t3 \t2 \t1 \t0 } + connect \t7 \$27 + connect \t6 \$23 + connect \t5 \$19 + connect \t4 \$15 + connect \t3 \$11 + connect \t2 \$7 + connect \t1 \$3 + connect \t0 \i [0] + connect \ni \$1 +end +attribute \src "libresoc.v:163137.1-163167.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.rdpick_INT_rc" +attribute \generator "nMigen" +module \rdpick_INT_rc + attribute \src "libresoc.v:163158.17-163158.89" + wire width 2 $not$libresoc.v:163158$10151_Y + attribute \src "libresoc.v:163160.17-163160.91" + wire $not$libresoc.v:163160$10153_Y + attribute \src "libresoc.v:163159.17-163159.103" + wire $reduce_or$libresoc.v:163159$10152_Y + attribute \src "libresoc.v:163161.17-163161.89" + wire $reduce_or$libresoc.v:163161$10154_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire width 2 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 2 input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire width 2 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 2 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $not$libresoc.v:163158$10151 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \i + connect \Y $not$libresoc.v:163158$10151_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:163160$10153 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$libresoc.v:163160$10153_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:163159$10152 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [0] \ni [1] } + connect \Y $reduce_or$libresoc.v:163159$10152_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_or $reduce_or$libresoc.v:163161$10154 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:163161$10154_Y + end + connect \$1 $not$libresoc.v:163158$10151_Y + connect \$4 $reduce_or$libresoc.v:163159$10152_Y + connect \$3 $not$libresoc.v:163160$10153_Y + connect \$7 $reduce_or$libresoc.v:163161$10154_Y + connect \en_o \$7 + connect \o { \t1 \t0 } + connect \t1 \$3 + connect \t0 \i [0] + connect \ni \$1 +end +attribute \src "libresoc.v:163171.1-163192.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.rdpick_SPR_spr1" +attribute \generator "nMigen" +module \rdpick_SPR_spr1 + attribute \src "libresoc.v:163186.17-163186.89" + wire $not$libresoc.v:163186$10155_Y + attribute \src "libresoc.v:163187.17-163187.89" + wire $reduce_or$libresoc.v:163187$10156_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $not$libresoc.v:163186$10155 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \i + connect \Y $not$libresoc.v:163186$10155_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_or $reduce_or$libresoc.v:163187$10156 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:163187$10156_Y + end + connect \$1 $not$libresoc.v:163186$10155_Y + connect \$3 $reduce_or$libresoc.v:163187$10156_Y + connect \en_o \$3 + connect \o \t0 + connect \t0 \i + connect \ni \$1 +end +attribute \src "libresoc.v:163196.1-163235.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.rdpick_XER_xer_ca" +attribute \generator "nMigen" +module \rdpick_XER_xer_ca + attribute \src "libresoc.v:163223.17-163223.91" + wire $not$libresoc.v:163223$10157_Y + attribute \src "libresoc.v:163225.17-163225.89" + wire width 3 $not$libresoc.v:163225$10159_Y + attribute \src "libresoc.v:163227.17-163227.91" + wire $not$libresoc.v:163227$10161_Y + attribute \src "libresoc.v:163224.18-163224.90" + wire $reduce_or$libresoc.v:163224$10158_Y + attribute \src "libresoc.v:163226.17-163226.103" + wire $reduce_or$libresoc.v:163226$10160_Y + attribute \src "libresoc.v:163228.17-163228.105" + wire $reduce_or$libresoc.v:163228$10162_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire width 3 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 3 input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire width 3 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 3 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:163223$10157 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $not$libresoc.v:163223$10157_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $not$libresoc.v:163225$10159 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \i + connect \Y $not$libresoc.v:163225$10159_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:163227$10161 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$libresoc.v:163227$10161_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_or $reduce_or$libresoc.v:163224$10158 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:163224$10158_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:163226$10160 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [0] \ni [1] } + connect \Y $reduce_or$libresoc.v:163226$10160_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:163228$10162 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [1:0] \ni [2] } + connect \Y $reduce_or$libresoc.v:163228$10162_Y + end + connect \$7 $not$libresoc.v:163223$10157_Y + connect \$11 $reduce_or$libresoc.v:163224$10158_Y + connect \$1 $not$libresoc.v:163225$10159_Y + connect \$4 $reduce_or$libresoc.v:163226$10160_Y + connect \$3 $not$libresoc.v:163227$10161_Y + connect \$8 $reduce_or$libresoc.v:163228$10162_Y + connect \en_o \$11 + connect \o { \t2 \t1 \t0 } + connect \t2 \$7 + connect \t1 \$3 + connect \t0 \i [0] + connect \ni \$1 +end +attribute \src "libresoc.v:163239.1-163260.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.rdpick_XER_xer_ov" +attribute \generator "nMigen" +module \rdpick_XER_xer_ov + attribute \src "libresoc.v:163254.17-163254.89" + wire $not$libresoc.v:163254$10163_Y + attribute \src "libresoc.v:163255.17-163255.89" + wire $reduce_or$libresoc.v:163255$10164_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $not$libresoc.v:163254$10163 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \i + connect \Y $not$libresoc.v:163254$10163_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_or $reduce_or$libresoc.v:163255$10164 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:163255$10164_Y + end + connect \$1 $not$libresoc.v:163254$10163_Y + connect \$3 $reduce_or$libresoc.v:163255$10164_Y + connect \en_o \$3 + connect \o \t0 + connect \t0 \i + connect \ni \$1 +end +attribute \src "libresoc.v:163264.1-163330.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.rdpick_XER_xer_so" +attribute \generator "nMigen" +module \rdpick_XER_xer_so + attribute \src "libresoc.v:163309.17-163309.91" + wire $not$libresoc.v:163309$10165_Y + attribute \src "libresoc.v:163311.18-163311.93" + wire $not$libresoc.v:163311$10167_Y + attribute \src "libresoc.v:163313.18-163313.93" + wire $not$libresoc.v:163313$10169_Y + attribute \src "libresoc.v:163314.17-163314.89" + wire width 6 $not$libresoc.v:163314$10170_Y + attribute \src "libresoc.v:163316.18-163316.93" + wire $not$libresoc.v:163316$10172_Y + attribute \src "libresoc.v:163319.17-163319.91" + wire $not$libresoc.v:163319$10175_Y + attribute \src "libresoc.v:163310.18-163310.106" + wire $reduce_or$libresoc.v:163310$10166_Y + attribute \src "libresoc.v:163312.18-163312.106" + wire $reduce_or$libresoc.v:163312$10168_Y + attribute \src "libresoc.v:163315.18-163315.106" + wire $reduce_or$libresoc.v:163315$10171_Y + attribute \src "libresoc.v:163317.18-163317.90" + wire $reduce_or$libresoc.v:163317$10173_Y + attribute \src "libresoc.v:163318.17-163318.103" + wire $reduce_or$libresoc.v:163318$10174_Y + attribute \src "libresoc.v:163320.17-163320.105" + wire $reduce_or$libresoc.v:163320$10176_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire width 6 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 6 input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire width 6 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 6 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:163309$10165 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $not$libresoc.v:163309$10165_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:163311$10167 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$12 + connect \Y $not$libresoc.v:163311$10167_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:163313$10169 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \Y $not$libresoc.v:163313$10169_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $not$libresoc.v:163314$10170 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \i + connect \Y $not$libresoc.v:163314$10170_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:163316$10172 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$20 + connect \Y $not$libresoc.v:163316$10172_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:163319$10175 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$libresoc.v:163319$10175_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:163310$10166 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [2:0] \ni [3] } + connect \Y $reduce_or$libresoc.v:163310$10166_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:163312$10168 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [3:0] \ni [4] } + connect \Y $reduce_or$libresoc.v:163312$10168_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:163315$10171 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [4:0] \ni [5] } + connect \Y $reduce_or$libresoc.v:163315$10171_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_or $reduce_or$libresoc.v:163317$10173 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:163317$10173_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:163318$10174 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [0] \ni [1] } + connect \Y $reduce_or$libresoc.v:163318$10174_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:163320$10176 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [1:0] \ni [2] } + connect \Y $reduce_or$libresoc.v:163320$10176_Y + end + connect \$7 $not$libresoc.v:163309$10165_Y + connect \$12 $reduce_or$libresoc.v:163310$10166_Y + connect \$11 $not$libresoc.v:163311$10167_Y + connect \$16 $reduce_or$libresoc.v:163312$10168_Y + connect \$15 $not$libresoc.v:163313$10169_Y + connect \$1 $not$libresoc.v:163314$10170_Y + connect \$20 $reduce_or$libresoc.v:163315$10171_Y + connect \$19 $not$libresoc.v:163316$10172_Y + connect \$23 $reduce_or$libresoc.v:163317$10173_Y + connect \$4 $reduce_or$libresoc.v:163318$10174_Y + connect \$3 $not$libresoc.v:163319$10175_Y + connect \$8 $reduce_or$libresoc.v:163320$10176_Y + connect \en_o \$23 + connect \o { \t5 \t4 \t3 \t2 \t1 \t0 } + connect \t5 \$19 + connect \t4 \$15 + connect \t3 \$11 + connect \t2 \$7 + connect \t1 \$3 + connect \t0 \i [0] + connect \ni \$1 +end +attribute \src "libresoc.v:163334.1-163805.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.cr.reg_0" +attribute \generator "nMigen" +module \reg_0 + attribute \src "libresoc.v:163335.7-163335.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:163665.3-163704.6" + wire width 4 $0\r0__data_o$next[3:0]$10232 + attribute \src "libresoc.v:163420.3-163421.37" + wire width 4 $0\r0__data_o[3:0] + attribute \src "libresoc.v:163735.3-163774.6" + wire width 4 $0\r20__data_o$next[3:0]$10246 + attribute \src "libresoc.v:163418.3-163419.39" + wire width 4 $0\r20__data_o[3:0] + attribute \src "libresoc.v:163498.3-163524.6" + wire width 4 $0\reg$next[3:0]$10198 + attribute \src "libresoc.v:163416.3-163417.25" + wire width 4 $0\reg[3:0] + attribute \src "libresoc.v:163428.3-163467.6" + wire width 4 $0\src10__data_o$next[3:0]$10189 + attribute \src "libresoc.v:163426.3-163427.43" + wire width 4 $0\src10__data_o[3:0] + attribute \src "libresoc.v:163525.3-163564.6" + wire width 4 $0\src20__data_o$next[3:0]$10204 + attribute \src "libresoc.v:163424.3-163425.43" + wire width 4 $0\src20__data_o[3:0] + attribute \src "libresoc.v:163595.3-163634.6" + wire width 4 $0\src30__data_o$next[3:0]$10218 + attribute \src "libresoc.v:163422.3-163423.43" + wire width 4 $0\src30__data_o[3:0] + attribute \src "libresoc.v:163705.3-163734.6" + wire $0\wr_detect$10[0:0]$10240 + attribute \src "libresoc.v:163775.3-163804.6" + wire $0\wr_detect$13[0:0]$10254 + attribute \src "libresoc.v:163565.3-163594.6" + wire $0\wr_detect$4[0:0]$10212 + attribute \src "libresoc.v:163635.3-163664.6" + wire $0\wr_detect$7[0:0]$10226 + attribute \src "libresoc.v:163468.3-163497.6" + wire $0\wr_detect[0:0] + attribute \src "libresoc.v:163665.3-163704.6" + wire width 4 $1\r0__data_o$next[3:0]$10233 + attribute \src "libresoc.v:163360.13-163360.30" + wire width 4 $1\r0__data_o[3:0] + attribute \src "libresoc.v:163735.3-163774.6" + wire width 4 $1\r20__data_o$next[3:0]$10247 + attribute \src "libresoc.v:163367.13-163367.31" + wire width 4 $1\r20__data_o[3:0] + attribute \src "libresoc.v:163498.3-163524.6" + wire width 4 $1\reg$next[3:0]$10199 + attribute \src "libresoc.v:163373.13-163373.25" + wire width 4 $1\reg[3:0] + attribute \src "libresoc.v:163428.3-163467.6" + wire width 4 $1\src10__data_o$next[3:0]$10190 + attribute \src "libresoc.v:163378.13-163378.33" + wire width 4 $1\src10__data_o[3:0] + attribute \src "libresoc.v:163525.3-163564.6" + wire width 4 $1\src20__data_o$next[3:0]$10205 + attribute \src "libresoc.v:163385.13-163385.33" + wire width 4 $1\src20__data_o[3:0] + attribute \src "libresoc.v:163595.3-163634.6" + wire width 4 $1\src30__data_o$next[3:0]$10219 + attribute \src "libresoc.v:163392.13-163392.33" + wire width 4 $1\src30__data_o[3:0] + attribute \src "libresoc.v:163705.3-163734.6" + wire $1\wr_detect$10[0:0]$10241 + attribute \src "libresoc.v:163775.3-163804.6" + wire $1\wr_detect$13[0:0]$10255 + attribute \src "libresoc.v:163565.3-163594.6" + wire $1\wr_detect$4[0:0]$10213 + attribute \src "libresoc.v:163635.3-163664.6" + wire $1\wr_detect$7[0:0]$10227 + attribute \src "libresoc.v:163468.3-163497.6" + wire $1\wr_detect[0:0] + attribute \src "libresoc.v:163665.3-163704.6" + wire width 4 $2\r0__data_o$next[3:0]$10234 + attribute \src "libresoc.v:163735.3-163774.6" + wire width 4 $2\r20__data_o$next[3:0]$10248 + attribute \src "libresoc.v:163498.3-163524.6" + wire width 4 $2\reg$next[3:0]$10200 + attribute \src "libresoc.v:163428.3-163467.6" + wire width 4 $2\src10__data_o$next[3:0]$10191 + attribute \src "libresoc.v:163525.3-163564.6" + wire width 4 $2\src20__data_o$next[3:0]$10206 + attribute \src "libresoc.v:163595.3-163634.6" + wire width 4 $2\src30__data_o$next[3:0]$10220 + attribute \src "libresoc.v:163705.3-163734.6" + wire $2\wr_detect$10[0:0]$10242 + attribute \src "libresoc.v:163775.3-163804.6" + wire $2\wr_detect$13[0:0]$10256 + attribute \src "libresoc.v:163565.3-163594.6" + wire $2\wr_detect$4[0:0]$10214 + attribute \src "libresoc.v:163635.3-163664.6" + wire $2\wr_detect$7[0:0]$10228 + attribute \src "libresoc.v:163468.3-163497.6" + wire $2\wr_detect[0:0] + attribute \src "libresoc.v:163665.3-163704.6" + wire width 4 $3\r0__data_o$next[3:0]$10235 + attribute \src "libresoc.v:163735.3-163774.6" + wire width 4 $3\r20__data_o$next[3:0]$10249 + attribute \src "libresoc.v:163498.3-163524.6" + wire width 4 $3\reg$next[3:0]$10201 + attribute \src "libresoc.v:163428.3-163467.6" + wire width 4 $3\src10__data_o$next[3:0]$10192 + attribute \src "libresoc.v:163525.3-163564.6" + wire width 4 $3\src20__data_o$next[3:0]$10207 + attribute \src "libresoc.v:163595.3-163634.6" + wire width 4 $3\src30__data_o$next[3:0]$10221 + attribute \src "libresoc.v:163705.3-163734.6" + wire $3\wr_detect$10[0:0]$10243 + attribute \src "libresoc.v:163775.3-163804.6" + wire $3\wr_detect$13[0:0]$10257 + attribute \src "libresoc.v:163565.3-163594.6" + wire $3\wr_detect$4[0:0]$10215 + attribute \src "libresoc.v:163635.3-163664.6" + wire $3\wr_detect$7[0:0]$10229 + attribute \src "libresoc.v:163468.3-163497.6" + wire $3\wr_detect[0:0] + attribute \src "libresoc.v:163665.3-163704.6" + wire width 4 $4\r0__data_o$next[3:0]$10236 + attribute \src "libresoc.v:163735.3-163774.6" + wire width 4 $4\r20__data_o$next[3:0]$10250 + attribute \src "libresoc.v:163498.3-163524.6" + wire width 4 $4\reg$next[3:0]$10202 + attribute \src "libresoc.v:163428.3-163467.6" + wire width 4 $4\src10__data_o$next[3:0]$10193 + attribute \src "libresoc.v:163525.3-163564.6" + wire width 4 $4\src20__data_o$next[3:0]$10208 + attribute \src "libresoc.v:163595.3-163634.6" + wire width 4 $4\src30__data_o$next[3:0]$10222 + attribute \src "libresoc.v:163705.3-163734.6" + wire $4\wr_detect$10[0:0]$10244 + attribute \src "libresoc.v:163775.3-163804.6" + wire $4\wr_detect$13[0:0]$10258 + attribute \src "libresoc.v:163565.3-163594.6" + wire $4\wr_detect$4[0:0]$10216 + attribute \src "libresoc.v:163635.3-163664.6" + wire $4\wr_detect$7[0:0]$10230 + attribute \src "libresoc.v:163468.3-163497.6" + wire $4\wr_detect[0:0] + attribute \src "libresoc.v:163665.3-163704.6" + wire width 4 $5\r0__data_o$next[3:0]$10237 + attribute \src "libresoc.v:163735.3-163774.6" + wire width 4 $5\r20__data_o$next[3:0]$10251 + attribute \src "libresoc.v:163428.3-163467.6" + wire width 4 $5\src10__data_o$next[3:0]$10194 + attribute \src "libresoc.v:163525.3-163564.6" + wire width 4 $5\src20__data_o$next[3:0]$10209 + attribute \src "libresoc.v:163595.3-163634.6" + wire width 4 $5\src30__data_o$next[3:0]$10223 + attribute \src "libresoc.v:163665.3-163704.6" + wire width 4 $6\r0__data_o$next[3:0]$10238 + attribute \src "libresoc.v:163735.3-163774.6" + wire width 4 $6\r20__data_o$next[3:0]$10252 + attribute \src "libresoc.v:163428.3-163467.6" + wire width 4 $6\src10__data_o$next[3:0]$10195 + attribute \src "libresoc.v:163525.3-163564.6" + wire width 4 $6\src20__data_o$next[3:0]$10210 + attribute \src "libresoc.v:163595.3-163634.6" + wire width 4 $6\src30__data_o$next[3:0]$10224 + attribute \src "libresoc.v:163411.17-163411.104" + wire $not$libresoc.v:163411$10177_Y + attribute \src "libresoc.v:163412.18-163412.105" + wire $not$libresoc.v:163412$10178_Y + attribute \src "libresoc.v:163413.17-163413.100" + wire $not$libresoc.v:163413$10179_Y + attribute \src "libresoc.v:163414.17-163414.103" + wire $not$libresoc.v:163414$10180_Y + attribute \src "libresoc.v:163415.17-163415.103" + wire $not$libresoc.v:163415$10181_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 18 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 input 9 \dest10__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 8 \dest10__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 input 11 \dest20__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 10 \dest20__wen + attribute \src "libresoc.v:163335.7-163335.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 12 \r0__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \r0__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 13 \r0__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 14 \r20__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \r20__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 15 \r20__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 4 \reg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 4 \reg$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 3 \src10__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \src10__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 2 \src10__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 5 \src20__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \src20__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 4 \src20__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 7 \src30__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \src30__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 6 \src30__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 input 16 \w0__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 17 \w0__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:163411$10177 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$10 + connect \Y $not$libresoc.v:163411$10177_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:163412$10178 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$13 + connect \Y $not$libresoc.v:163412$10178_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:163413$10179 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect + connect \Y $not$libresoc.v:163413$10179_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:163414$10180 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$4 + connect \Y $not$libresoc.v:163414$10180_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:163415$10181 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$7 + connect \Y $not$libresoc.v:163415$10181_Y + end + attribute \src "libresoc.v:163335.7-163335.20" + process $proc$libresoc.v:163335$10259 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:163360.13-163360.30" + process $proc$libresoc.v:163360$10260 + assign { } { } + assign $1\r0__data_o[3:0] 4'0000 + sync always + sync init + update \r0__data_o $1\r0__data_o[3:0] + end + attribute \src "libresoc.v:163367.13-163367.31" + process $proc$libresoc.v:163367$10261 + assign { } { } + assign $1\r20__data_o[3:0] 4'0000 + sync always + sync init + update \r20__data_o $1\r20__data_o[3:0] + end + attribute \src "libresoc.v:163373.13-163373.25" + process $proc$libresoc.v:163373$10262 + assign { } { } + assign $1\reg[3:0] 4'0000 + sync always + sync init + update \reg $1\reg[3:0] + end + attribute \src "libresoc.v:163378.13-163378.33" + process $proc$libresoc.v:163378$10263 + assign { } { } + assign $1\src10__data_o[3:0] 4'0000 + sync always + sync init + update \src10__data_o $1\src10__data_o[3:0] + end + attribute \src "libresoc.v:163385.13-163385.33" + process $proc$libresoc.v:163385$10264 + assign { } { } + assign $1\src20__data_o[3:0] 4'0000 + sync always + sync init + update \src20__data_o $1\src20__data_o[3:0] + end + attribute \src "libresoc.v:163392.13-163392.33" + process $proc$libresoc.v:163392$10265 + assign { } { } + assign $1\src30__data_o[3:0] 4'0000 + sync always + sync init + update \src30__data_o $1\src30__data_o[3:0] + end + attribute \src "libresoc.v:163416.3-163417.25" + process $proc$libresoc.v:163416$10182 + assign { } { } + assign $0\reg[3:0] \reg$next + sync posedge \coresync_clk + update \reg $0\reg[3:0] + end + attribute \src "libresoc.v:163418.3-163419.39" + process $proc$libresoc.v:163418$10183 + assign { } { } + assign $0\r20__data_o[3:0] \r20__data_o$next + sync posedge \coresync_clk + update \r20__data_o $0\r20__data_o[3:0] + end + attribute \src "libresoc.v:163420.3-163421.37" + process $proc$libresoc.v:163420$10184 + assign { } { } + assign $0\r0__data_o[3:0] \r0__data_o$next + sync posedge \coresync_clk + update \r0__data_o $0\r0__data_o[3:0] + end + attribute \src "libresoc.v:163422.3-163423.43" + process $proc$libresoc.v:163422$10185 + assign { } { } + assign $0\src30__data_o[3:0] \src30__data_o$next + sync posedge \coresync_clk + update \src30__data_o $0\src30__data_o[3:0] + end + attribute \src "libresoc.v:163424.3-163425.43" + process $proc$libresoc.v:163424$10186 + assign { } { } + assign $0\src20__data_o[3:0] \src20__data_o$next + sync posedge \coresync_clk + update \src20__data_o $0\src20__data_o[3:0] + end + attribute \src "libresoc.v:163426.3-163427.43" + process $proc$libresoc.v:163426$10187 + assign { } { } + assign $0\src10__data_o[3:0] \src10__data_o$next + sync posedge \coresync_clk + update \src10__data_o $0\src10__data_o[3:0] + end + attribute \src "libresoc.v:163428.3-163467.6" + process $proc$libresoc.v:163428$10188 + assign { } { } + assign { } { } + assign { } { } + assign $0\src10__data_o$next[3:0]$10189 $6\src10__data_o$next[3:0]$10195 + attribute \src "libresoc.v:163429.5-163429.29" + switch \initial + attribute \src "libresoc.v:163429.9-163429.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src10__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src10__data_o$next[3:0]$10190 $5\src10__data_o$next[3:0]$10194 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest10__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src10__data_o$next[3:0]$10191 \dest10__data_i + case + assign $2\src10__data_o$next[3:0]$10191 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest20__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src10__data_o$next[3:0]$10192 \dest20__data_i + case + assign $3\src10__data_o$next[3:0]$10192 $2\src10__data_o$next[3:0]$10191 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src10__data_o$next[3:0]$10193 \w0__data_i + case + assign $4\src10__data_o$next[3:0]$10193 $3\src10__data_o$next[3:0]$10192 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src10__data_o$next[3:0]$10194 \reg + case + assign $5\src10__data_o$next[3:0]$10194 $4\src10__data_o$next[3:0]$10193 + end + case + assign $1\src10__data_o$next[3:0]$10190 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src10__data_o$next[3:0]$10195 4'0000 + case + assign $6\src10__data_o$next[3:0]$10195 $1\src10__data_o$next[3:0]$10190 + end + sync always + update \src10__data_o$next $0\src10__data_o$next[3:0]$10189 + end + attribute \src "libresoc.v:163468.3-163497.6" + process $proc$libresoc.v:163468$10196 + assign { } { } + assign { } { } + assign $0\wr_detect[0:0] $1\wr_detect[0:0] + attribute \src "libresoc.v:163469.5-163469.29" + switch \initial + attribute \src "libresoc.v:163469.9-163469.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src10__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect[0:0] $4\wr_detect[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest10__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect[0:0] 1'1 + case + assign $2\wr_detect[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest20__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect[0:0] 1'1 + case + assign $3\wr_detect[0:0] $2\wr_detect[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect[0:0] 1'1 + case + assign $4\wr_detect[0:0] $3\wr_detect[0:0] + end + case + assign $1\wr_detect[0:0] 1'0 + end + sync always + update \wr_detect $0\wr_detect[0:0] + end + attribute \src "libresoc.v:163498.3-163524.6" + process $proc$libresoc.v:163498$10197 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\reg$next[3:0]$10198 $4\reg$next[3:0]$10202 + attribute \src "libresoc.v:163499.5-163499.29" + switch \initial + attribute \src "libresoc.v:163499.9-163499.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest10__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\reg$next[3:0]$10199 \dest10__data_i + case + assign $1\reg$next[3:0]$10199 \reg + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest20__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\reg$next[3:0]$10200 \dest20__data_i + case + assign $2\reg$next[3:0]$10200 $1\reg$next[3:0]$10199 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \w0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\reg$next[3:0]$10201 \w0__data_i + case + assign $3\reg$next[3:0]$10201 $2\reg$next[3:0]$10200 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\reg$next[3:0]$10202 4'0000 + case + assign $4\reg$next[3:0]$10202 $3\reg$next[3:0]$10201 + end + sync always + update \reg$next $0\reg$next[3:0]$10198 + end + attribute \src "libresoc.v:163525.3-163564.6" + process $proc$libresoc.v:163525$10203 + assign { } { } + assign { } { } + assign { } { } + assign $0\src20__data_o$next[3:0]$10204 $6\src20__data_o$next[3:0]$10210 + attribute \src "libresoc.v:163526.5-163526.29" + switch \initial + attribute \src "libresoc.v:163526.9-163526.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src20__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src20__data_o$next[3:0]$10205 $5\src20__data_o$next[3:0]$10209 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest10__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src20__data_o$next[3:0]$10206 \dest10__data_i + case + assign $2\src20__data_o$next[3:0]$10206 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest20__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src20__data_o$next[3:0]$10207 \dest20__data_i + case + assign $3\src20__data_o$next[3:0]$10207 $2\src20__data_o$next[3:0]$10206 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src20__data_o$next[3:0]$10208 \w0__data_i + case + assign $4\src20__data_o$next[3:0]$10208 $3\src20__data_o$next[3:0]$10207 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src20__data_o$next[3:0]$10209 \reg + case + assign $5\src20__data_o$next[3:0]$10209 $4\src20__data_o$next[3:0]$10208 + end + case + assign $1\src20__data_o$next[3:0]$10205 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src20__data_o$next[3:0]$10210 4'0000 + case + assign $6\src20__data_o$next[3:0]$10210 $1\src20__data_o$next[3:0]$10205 + end + sync always + update \src20__data_o$next $0\src20__data_o$next[3:0]$10204 + end + attribute \src "libresoc.v:163565.3-163594.6" + process $proc$libresoc.v:163565$10211 + assign { } { } + assign { } { } + assign $0\wr_detect$4[0:0]$10212 $1\wr_detect$4[0:0]$10213 + attribute \src "libresoc.v:163566.5-163566.29" + switch \initial + attribute \src "libresoc.v:163566.9-163566.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src20__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$4[0:0]$10213 $4\wr_detect$4[0:0]$10216 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest10__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$4[0:0]$10214 1'1 + case + assign $2\wr_detect$4[0:0]$10214 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest20__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$4[0:0]$10215 1'1 + case + assign $3\wr_detect$4[0:0]$10215 $2\wr_detect$4[0:0]$10214 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$4[0:0]$10216 1'1 + case + assign $4\wr_detect$4[0:0]$10216 $3\wr_detect$4[0:0]$10215 + end + case + assign $1\wr_detect$4[0:0]$10213 1'0 + end + sync always + update \wr_detect$4 $0\wr_detect$4[0:0]$10212 + end + attribute \src "libresoc.v:163595.3-163634.6" + process $proc$libresoc.v:163595$10217 + assign { } { } + assign { } { } + assign { } { } + assign $0\src30__data_o$next[3:0]$10218 $6\src30__data_o$next[3:0]$10224 + attribute \src "libresoc.v:163596.5-163596.29" + switch \initial + attribute \src "libresoc.v:163596.9-163596.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src30__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src30__data_o$next[3:0]$10219 $5\src30__data_o$next[3:0]$10223 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest10__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src30__data_o$next[3:0]$10220 \dest10__data_i + case + assign $2\src30__data_o$next[3:0]$10220 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest20__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src30__data_o$next[3:0]$10221 \dest20__data_i + case + assign $3\src30__data_o$next[3:0]$10221 $2\src30__data_o$next[3:0]$10220 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src30__data_o$next[3:0]$10222 \w0__data_i + case + assign $4\src30__data_o$next[3:0]$10222 $3\src30__data_o$next[3:0]$10221 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$6 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src30__data_o$next[3:0]$10223 \reg + case + assign $5\src30__data_o$next[3:0]$10223 $4\src30__data_o$next[3:0]$10222 + end + case + assign $1\src30__data_o$next[3:0]$10219 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src30__data_o$next[3:0]$10224 4'0000 + case + assign $6\src30__data_o$next[3:0]$10224 $1\src30__data_o$next[3:0]$10219 + end + sync always + update \src30__data_o$next $0\src30__data_o$next[3:0]$10218 + end + attribute \src "libresoc.v:163635.3-163664.6" + process $proc$libresoc.v:163635$10225 + assign { } { } + assign { } { } + assign $0\wr_detect$7[0:0]$10226 $1\wr_detect$7[0:0]$10227 + attribute \src "libresoc.v:163636.5-163636.29" + switch \initial + attribute \src "libresoc.v:163636.9-163636.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src30__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$7[0:0]$10227 $4\wr_detect$7[0:0]$10230 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest10__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$7[0:0]$10228 1'1 + case + assign $2\wr_detect$7[0:0]$10228 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest20__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$7[0:0]$10229 1'1 + case + assign $3\wr_detect$7[0:0]$10229 $2\wr_detect$7[0:0]$10228 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$7[0:0]$10230 1'1 + case + assign $4\wr_detect$7[0:0]$10230 $3\wr_detect$7[0:0]$10229 + end + case + assign $1\wr_detect$7[0:0]$10227 1'0 + end + sync always + update \wr_detect$7 $0\wr_detect$7[0:0]$10226 + end + attribute \src "libresoc.v:163665.3-163704.6" + process $proc$libresoc.v:163665$10231 + assign { } { } + assign { } { } + assign { } { } + assign $0\r0__data_o$next[3:0]$10232 $6\r0__data_o$next[3:0]$10238 + attribute \src "libresoc.v:163666.5-163666.29" + switch \initial + attribute \src "libresoc.v:163666.9-163666.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r0__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\r0__data_o$next[3:0]$10233 $5\r0__data_o$next[3:0]$10237 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest10__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r0__data_o$next[3:0]$10234 \dest10__data_i + case + assign $2\r0__data_o$next[3:0]$10234 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest20__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\r0__data_o$next[3:0]$10235 \dest20__data_i + case + assign $3\r0__data_o$next[3:0]$10235 $2\r0__data_o$next[3:0]$10234 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\r0__data_o$next[3:0]$10236 \w0__data_i + case + assign $4\r0__data_o$next[3:0]$10236 $3\r0__data_o$next[3:0]$10235 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$9 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\r0__data_o$next[3:0]$10237 \reg + case + assign $5\r0__data_o$next[3:0]$10237 $4\r0__data_o$next[3:0]$10236 + end + case + assign $1\r0__data_o$next[3:0]$10233 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\r0__data_o$next[3:0]$10238 4'0000 + case + assign $6\r0__data_o$next[3:0]$10238 $1\r0__data_o$next[3:0]$10233 + end + sync always + update \r0__data_o$next $0\r0__data_o$next[3:0]$10232 + end + attribute \src "libresoc.v:163705.3-163734.6" + process $proc$libresoc.v:163705$10239 + assign { } { } + assign { } { } + assign $0\wr_detect$10[0:0]$10240 $1\wr_detect$10[0:0]$10241 + attribute \src "libresoc.v:163706.5-163706.29" + switch \initial + attribute \src "libresoc.v:163706.9-163706.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r0__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$10[0:0]$10241 $4\wr_detect$10[0:0]$10244 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest10__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$10[0:0]$10242 1'1 + case + assign $2\wr_detect$10[0:0]$10242 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest20__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$10[0:0]$10243 1'1 + case + assign $3\wr_detect$10[0:0]$10243 $2\wr_detect$10[0:0]$10242 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$10[0:0]$10244 1'1 + case + assign $4\wr_detect$10[0:0]$10244 $3\wr_detect$10[0:0]$10243 + end + case + assign $1\wr_detect$10[0:0]$10241 1'0 + end + sync always + update \wr_detect$10 $0\wr_detect$10[0:0]$10240 + end + attribute \src "libresoc.v:163735.3-163774.6" + process $proc$libresoc.v:163735$10245 + assign { } { } + assign { } { } + assign { } { } + assign $0\r20__data_o$next[3:0]$10246 $6\r20__data_o$next[3:0]$10252 + attribute \src "libresoc.v:163736.5-163736.29" + switch \initial + attribute \src "libresoc.v:163736.9-163736.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r20__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\r20__data_o$next[3:0]$10247 $5\r20__data_o$next[3:0]$10251 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest10__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r20__data_o$next[3:0]$10248 \dest10__data_i + case + assign $2\r20__data_o$next[3:0]$10248 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest20__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\r20__data_o$next[3:0]$10249 \dest20__data_i + case + assign $3\r20__data_o$next[3:0]$10249 $2\r20__data_o$next[3:0]$10248 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\r20__data_o$next[3:0]$10250 \w0__data_i + case + assign $4\r20__data_o$next[3:0]$10250 $3\r20__data_o$next[3:0]$10249 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$12 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\r20__data_o$next[3:0]$10251 \reg + case + assign $5\r20__data_o$next[3:0]$10251 $4\r20__data_o$next[3:0]$10250 + end + case + assign $1\r20__data_o$next[3:0]$10247 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\r20__data_o$next[3:0]$10252 4'0000 + case + assign $6\r20__data_o$next[3:0]$10252 $1\r20__data_o$next[3:0]$10247 + end + sync always + update \r20__data_o$next $0\r20__data_o$next[3:0]$10246 + end + attribute \src "libresoc.v:163775.3-163804.6" + process $proc$libresoc.v:163775$10253 + assign { } { } + assign { } { } + assign $0\wr_detect$13[0:0]$10254 $1\wr_detect$13[0:0]$10255 + attribute \src "libresoc.v:163776.5-163776.29" + switch \initial + attribute \src "libresoc.v:163776.9-163776.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r20__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$13[0:0]$10255 $4\wr_detect$13[0:0]$10258 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest10__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$13[0:0]$10256 1'1 + case + assign $2\wr_detect$13[0:0]$10256 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest20__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$13[0:0]$10257 1'1 + case + assign $3\wr_detect$13[0:0]$10257 $2\wr_detect$13[0:0]$10256 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$13[0:0]$10258 1'1 + case + assign $4\wr_detect$13[0:0]$10258 $3\wr_detect$13[0:0]$10257 + end + case + assign $1\wr_detect$13[0:0]$10255 1'0 + end + sync always + update \wr_detect$13 $0\wr_detect$13[0:0]$10254 + end + connect \$9 $not$libresoc.v:163411$10177_Y + connect \$12 $not$libresoc.v:163412$10178_Y + connect \$1 $not$libresoc.v:163413$10179_Y + connect \$3 $not$libresoc.v:163414$10180_Y + connect \$6 $not$libresoc.v:163415$10181_Y +end +attribute \src "libresoc.v:163809.1-164254.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.xer.reg_0" +attribute \generator "nMigen" +module \reg_0$129 + attribute \src "libresoc.v:163810.7-163810.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:164139.3-164184.6" + wire width 2 $0\r0__data_o$next[1:0]$10318 + attribute \src "libresoc.v:163885.3-163886.37" + wire width 2 $0\r0__data_o[1:0] + attribute \src "libresoc.v:164221.3-164253.6" + wire width 2 $0\reg$next[1:0]$10334 + attribute \src "libresoc.v:163883.3-163884.25" + wire width 2 $0\reg[1:0] + attribute \src "libresoc.v:163893.3-163938.6" + wire width 2 $0\src10__data_o$next[1:0]$10276 + attribute \src "libresoc.v:163891.3-163892.43" + wire width 2 $0\src10__data_o[1:0] + attribute \src "libresoc.v:163975.3-164020.6" + wire width 2 $0\src20__data_o$next[1:0]$10286 + attribute \src "libresoc.v:163889.3-163890.43" + wire width 2 $0\src20__data_o[1:0] + attribute \src "libresoc.v:164057.3-164102.6" + wire width 2 $0\src30__data_o$next[1:0]$10302 + attribute \src "libresoc.v:163887.3-163888.43" + wire width 2 $0\src30__data_o[1:0] + attribute \src "libresoc.v:164185.3-164220.6" + wire $0\wr_detect$10[0:0]$10327 + attribute \src "libresoc.v:164021.3-164056.6" + wire $0\wr_detect$4[0:0]$10295 + attribute \src "libresoc.v:164103.3-164138.6" + wire $0\wr_detect$7[0:0]$10311 + attribute \src "libresoc.v:163939.3-163974.6" + wire $0\wr_detect[0:0] + attribute \src "libresoc.v:164139.3-164184.6" + wire width 2 $1\r0__data_o$next[1:0]$10319 + attribute \src "libresoc.v:163837.13-163837.30" + wire width 2 $1\r0__data_o[1:0] + attribute \src "libresoc.v:164221.3-164253.6" + wire width 2 $1\reg$next[1:0]$10335 + attribute \src "libresoc.v:163843.13-163843.25" + wire width 2 $1\reg[1:0] + attribute \src "libresoc.v:163893.3-163938.6" + wire width 2 $1\src10__data_o$next[1:0]$10277 + attribute \src "libresoc.v:163848.13-163848.33" + wire width 2 $1\src10__data_o[1:0] + attribute \src "libresoc.v:163975.3-164020.6" + wire width 2 $1\src20__data_o$next[1:0]$10287 + attribute \src "libresoc.v:163855.13-163855.33" + wire width 2 $1\src20__data_o[1:0] + attribute \src "libresoc.v:164057.3-164102.6" + wire width 2 $1\src30__data_o$next[1:0]$10303 + attribute \src "libresoc.v:163862.13-163862.33" + wire width 2 $1\src30__data_o[1:0] + attribute \src "libresoc.v:164185.3-164220.6" + wire $1\wr_detect$10[0:0]$10328 + attribute \src "libresoc.v:164021.3-164056.6" + wire $1\wr_detect$4[0:0]$10296 + attribute \src "libresoc.v:164103.3-164138.6" + wire $1\wr_detect$7[0:0]$10312 + attribute \src "libresoc.v:163939.3-163974.6" + wire $1\wr_detect[0:0] + attribute \src "libresoc.v:164139.3-164184.6" + wire width 2 $2\r0__data_o$next[1:0]$10320 + attribute \src "libresoc.v:164221.3-164253.6" + wire width 2 $2\reg$next[1:0]$10336 + attribute \src "libresoc.v:163893.3-163938.6" + wire width 2 $2\src10__data_o$next[1:0]$10278 + attribute \src "libresoc.v:163975.3-164020.6" + wire width 2 $2\src20__data_o$next[1:0]$10288 + attribute \src "libresoc.v:164057.3-164102.6" + wire width 2 $2\src30__data_o$next[1:0]$10304 + attribute \src "libresoc.v:164185.3-164220.6" + wire $2\wr_detect$10[0:0]$10329 + attribute \src "libresoc.v:164021.3-164056.6" + wire $2\wr_detect$4[0:0]$10297 + attribute \src "libresoc.v:164103.3-164138.6" + wire $2\wr_detect$7[0:0]$10313 + attribute \src "libresoc.v:163939.3-163974.6" + wire $2\wr_detect[0:0] + attribute \src "libresoc.v:164139.3-164184.6" + wire width 2 $3\r0__data_o$next[1:0]$10321 + attribute \src "libresoc.v:164221.3-164253.6" + wire width 2 $3\reg$next[1:0]$10337 + attribute \src "libresoc.v:163893.3-163938.6" + wire width 2 $3\src10__data_o$next[1:0]$10279 + attribute \src "libresoc.v:163975.3-164020.6" + wire width 2 $3\src20__data_o$next[1:0]$10289 + attribute \src "libresoc.v:164057.3-164102.6" + wire width 2 $3\src30__data_o$next[1:0]$10305 + attribute \src "libresoc.v:164185.3-164220.6" + wire $3\wr_detect$10[0:0]$10330 + attribute \src "libresoc.v:164021.3-164056.6" + wire $3\wr_detect$4[0:0]$10298 + attribute \src "libresoc.v:164103.3-164138.6" + wire $3\wr_detect$7[0:0]$10314 + attribute \src "libresoc.v:163939.3-163974.6" + wire $3\wr_detect[0:0] + attribute \src "libresoc.v:164139.3-164184.6" + wire width 2 $4\r0__data_o$next[1:0]$10322 + attribute \src "libresoc.v:164221.3-164253.6" + wire width 2 $4\reg$next[1:0]$10338 + attribute \src "libresoc.v:163893.3-163938.6" + wire width 2 $4\src10__data_o$next[1:0]$10280 + attribute \src "libresoc.v:163975.3-164020.6" + wire width 2 $4\src20__data_o$next[1:0]$10290 + attribute \src "libresoc.v:164057.3-164102.6" + wire width 2 $4\src30__data_o$next[1:0]$10306 + attribute \src "libresoc.v:164185.3-164220.6" + wire $4\wr_detect$10[0:0]$10331 + attribute \src "libresoc.v:164021.3-164056.6" + wire $4\wr_detect$4[0:0]$10299 + attribute \src "libresoc.v:164103.3-164138.6" + wire $4\wr_detect$7[0:0]$10315 + attribute \src "libresoc.v:163939.3-163974.6" + wire $4\wr_detect[0:0] + attribute \src "libresoc.v:164139.3-164184.6" + wire width 2 $5\r0__data_o$next[1:0]$10323 + attribute \src "libresoc.v:164221.3-164253.6" + wire width 2 $5\reg$next[1:0]$10339 + attribute \src "libresoc.v:163893.3-163938.6" + wire width 2 $5\src10__data_o$next[1:0]$10281 + attribute \src "libresoc.v:163975.3-164020.6" + wire width 2 $5\src20__data_o$next[1:0]$10291 + attribute \src "libresoc.v:164057.3-164102.6" + wire width 2 $5\src30__data_o$next[1:0]$10307 + attribute \src "libresoc.v:164185.3-164220.6" + wire $5\wr_detect$10[0:0]$10332 + attribute \src "libresoc.v:164021.3-164056.6" + wire $5\wr_detect$4[0:0]$10300 + attribute \src "libresoc.v:164103.3-164138.6" + wire $5\wr_detect$7[0:0]$10316 + attribute \src "libresoc.v:163939.3-163974.6" + wire $5\wr_detect[0:0] + attribute \src "libresoc.v:164139.3-164184.6" + wire width 2 $6\r0__data_o$next[1:0]$10324 + attribute \src "libresoc.v:163893.3-163938.6" + wire width 2 $6\src10__data_o$next[1:0]$10282 + attribute \src "libresoc.v:163975.3-164020.6" + wire width 2 $6\src20__data_o$next[1:0]$10292 + attribute \src "libresoc.v:164057.3-164102.6" + wire width 2 $6\src30__data_o$next[1:0]$10308 + attribute \src "libresoc.v:164139.3-164184.6" + wire width 2 $7\r0__data_o$next[1:0]$10325 + attribute \src "libresoc.v:163893.3-163938.6" + wire width 2 $7\src10__data_o$next[1:0]$10283 + attribute \src "libresoc.v:163975.3-164020.6" + wire width 2 $7\src20__data_o$next[1:0]$10293 + attribute \src "libresoc.v:164057.3-164102.6" + wire width 2 $7\src30__data_o$next[1:0]$10309 + attribute \src "libresoc.v:163879.17-163879.104" + wire $not$libresoc.v:163879$10266_Y + attribute \src "libresoc.v:163880.17-163880.100" + wire $not$libresoc.v:163880$10267_Y + attribute \src "libresoc.v:163881.17-163881.103" + wire $not$libresoc.v:163881$10268_Y + attribute \src "libresoc.v:163882.17-163882.103" + wire $not$libresoc.v:163882$10269_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 18 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 input 9 \dest10__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 8 \dest10__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 input 11 \dest20__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 10 \dest20__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 input 13 \dest30__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 12 \dest30__wen + attribute \src "libresoc.v:163810.7-163810.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 output 14 \r0__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 \r0__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 15 \r0__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 2 \reg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 2 \reg$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 output 3 \src10__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 \src10__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 2 \src10__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 output 5 \src20__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 \src20__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 4 \src20__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 output 7 \src30__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 \src30__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 6 \src30__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 input 16 \w0__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 17 \w0__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:163879$10266 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$10 + connect \Y $not$libresoc.v:163879$10266_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:163880$10267 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect + connect \Y $not$libresoc.v:163880$10267_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:163881$10268 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$4 + connect \Y $not$libresoc.v:163881$10268_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:163882$10269 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$7 + connect \Y $not$libresoc.v:163882$10269_Y + end + attribute \src "libresoc.v:163810.7-163810.20" + process $proc$libresoc.v:163810$10340 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:163837.13-163837.30" + process $proc$libresoc.v:163837$10341 + assign { } { } + assign $1\r0__data_o[1:0] 2'00 + sync always + sync init + update \r0__data_o $1\r0__data_o[1:0] + end + attribute \src "libresoc.v:163843.13-163843.25" + process $proc$libresoc.v:163843$10342 + assign { } { } + assign $1\reg[1:0] 2'00 + sync always + sync init + update \reg $1\reg[1:0] + end + attribute \src "libresoc.v:163848.13-163848.33" + process $proc$libresoc.v:163848$10343 + assign { } { } + assign $1\src10__data_o[1:0] 2'00 + sync always + sync init + update \src10__data_o $1\src10__data_o[1:0] + end + attribute \src "libresoc.v:163855.13-163855.33" + process $proc$libresoc.v:163855$10344 + assign { } { } + assign $1\src20__data_o[1:0] 2'00 + sync always + sync init + update \src20__data_o $1\src20__data_o[1:0] + end + attribute \src "libresoc.v:163862.13-163862.33" + process $proc$libresoc.v:163862$10345 + assign { } { } + assign $1\src30__data_o[1:0] 2'00 + sync always + sync init + update \src30__data_o $1\src30__data_o[1:0] + end + attribute \src "libresoc.v:163883.3-163884.25" + process $proc$libresoc.v:163883$10270 + assign { } { } + assign $0\reg[1:0] \reg$next + sync posedge \coresync_clk + update \reg $0\reg[1:0] + end + attribute \src "libresoc.v:163885.3-163886.37" + process $proc$libresoc.v:163885$10271 + assign { } { } + assign $0\r0__data_o[1:0] \r0__data_o$next + sync posedge \coresync_clk + update \r0__data_o $0\r0__data_o[1:0] + end + attribute \src "libresoc.v:163887.3-163888.43" + process $proc$libresoc.v:163887$10272 + assign { } { } + assign $0\src30__data_o[1:0] \src30__data_o$next + sync posedge \coresync_clk + update \src30__data_o $0\src30__data_o[1:0] + end + attribute \src "libresoc.v:163889.3-163890.43" + process $proc$libresoc.v:163889$10273 + assign { } { } + assign $0\src20__data_o[1:0] \src20__data_o$next + sync posedge \coresync_clk + update \src20__data_o $0\src20__data_o[1:0] + end + attribute \src "libresoc.v:163891.3-163892.43" + process $proc$libresoc.v:163891$10274 + assign { } { } + assign $0\src10__data_o[1:0] \src10__data_o$next + sync posedge \coresync_clk + update \src10__data_o $0\src10__data_o[1:0] + end + attribute \src "libresoc.v:163893.3-163938.6" + process $proc$libresoc.v:163893$10275 + assign { } { } + assign { } { } + assign { } { } + assign $0\src10__data_o$next[1:0]$10276 $7\src10__data_o$next[1:0]$10283 + attribute \src "libresoc.v:163894.5-163894.29" + switch \initial + attribute \src "libresoc.v:163894.9-163894.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src10__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src10__data_o$next[1:0]$10277 $6\src10__data_o$next[1:0]$10282 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest10__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src10__data_o$next[1:0]$10278 \dest10__data_i + case + assign $2\src10__data_o$next[1:0]$10278 2'00 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest20__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src10__data_o$next[1:0]$10279 \dest20__data_i + case + assign $3\src10__data_o$next[1:0]$10279 $2\src10__data_o$next[1:0]$10278 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest30__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src10__data_o$next[1:0]$10280 \dest30__data_i + case + assign $4\src10__data_o$next[1:0]$10280 $3\src10__data_o$next[1:0]$10279 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src10__data_o$next[1:0]$10281 \w0__data_i + case + assign $5\src10__data_o$next[1:0]$10281 $4\src10__data_o$next[1:0]$10280 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src10__data_o$next[1:0]$10282 \reg + case + assign $6\src10__data_o$next[1:0]$10282 $5\src10__data_o$next[1:0]$10281 + end + case + assign $1\src10__data_o$next[1:0]$10277 2'00 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\src10__data_o$next[1:0]$10283 2'00 + case + assign $7\src10__data_o$next[1:0]$10283 $1\src10__data_o$next[1:0]$10277 + end + sync always + update \src10__data_o$next $0\src10__data_o$next[1:0]$10276 + end + attribute \src "libresoc.v:163939.3-163974.6" + process $proc$libresoc.v:163939$10284 + assign { } { } + assign { } { } + assign $0\wr_detect[0:0] $1\wr_detect[0:0] + attribute \src "libresoc.v:163940.5-163940.29" + switch \initial + attribute \src "libresoc.v:163940.9-163940.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src10__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect[0:0] $5\wr_detect[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest10__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect[0:0] 1'1 + case + assign $2\wr_detect[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest20__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect[0:0] 1'1 + case + assign $3\wr_detect[0:0] $2\wr_detect[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest30__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect[0:0] 1'1 + case + assign $4\wr_detect[0:0] $3\wr_detect[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\wr_detect[0:0] 1'1 + case + assign $5\wr_detect[0:0] $4\wr_detect[0:0] + end + case + assign $1\wr_detect[0:0] 1'0 + end + sync always + update \wr_detect $0\wr_detect[0:0] + end + attribute \src "libresoc.v:163975.3-164020.6" + process $proc$libresoc.v:163975$10285 + assign { } { } + assign { } { } + assign { } { } + assign $0\src20__data_o$next[1:0]$10286 $7\src20__data_o$next[1:0]$10293 + attribute \src "libresoc.v:163976.5-163976.29" + switch \initial + attribute \src "libresoc.v:163976.9-163976.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src20__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src20__data_o$next[1:0]$10287 $6\src20__data_o$next[1:0]$10292 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest10__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src20__data_o$next[1:0]$10288 \dest10__data_i + case + assign $2\src20__data_o$next[1:0]$10288 2'00 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest20__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src20__data_o$next[1:0]$10289 \dest20__data_i + case + assign $3\src20__data_o$next[1:0]$10289 $2\src20__data_o$next[1:0]$10288 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest30__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src20__data_o$next[1:0]$10290 \dest30__data_i + case + assign $4\src20__data_o$next[1:0]$10290 $3\src20__data_o$next[1:0]$10289 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src20__data_o$next[1:0]$10291 \w0__data_i + case + assign $5\src20__data_o$next[1:0]$10291 $4\src20__data_o$next[1:0]$10290 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src20__data_o$next[1:0]$10292 \reg + case + assign $6\src20__data_o$next[1:0]$10292 $5\src20__data_o$next[1:0]$10291 + end + case + assign $1\src20__data_o$next[1:0]$10287 2'00 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\src20__data_o$next[1:0]$10293 2'00 + case + assign $7\src20__data_o$next[1:0]$10293 $1\src20__data_o$next[1:0]$10287 + end + sync always + update \src20__data_o$next $0\src20__data_o$next[1:0]$10286 + end + attribute \src "libresoc.v:164021.3-164056.6" + process $proc$libresoc.v:164021$10294 + assign { } { } + assign { } { } + assign $0\wr_detect$4[0:0]$10295 $1\wr_detect$4[0:0]$10296 + attribute \src "libresoc.v:164022.5-164022.29" + switch \initial + attribute \src "libresoc.v:164022.9-164022.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src20__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$4[0:0]$10296 $5\wr_detect$4[0:0]$10300 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest10__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$4[0:0]$10297 1'1 + case + assign $2\wr_detect$4[0:0]$10297 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest20__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$4[0:0]$10298 1'1 + case + assign $3\wr_detect$4[0:0]$10298 $2\wr_detect$4[0:0]$10297 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest30__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$4[0:0]$10299 1'1 + case + assign $4\wr_detect$4[0:0]$10299 $3\wr_detect$4[0:0]$10298 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\wr_detect$4[0:0]$10300 1'1 + case + assign $5\wr_detect$4[0:0]$10300 $4\wr_detect$4[0:0]$10299 + end + case + assign $1\wr_detect$4[0:0]$10296 1'0 + end + sync always + update \wr_detect$4 $0\wr_detect$4[0:0]$10295 + end + attribute \src "libresoc.v:164057.3-164102.6" + process $proc$libresoc.v:164057$10301 + assign { } { } + assign { } { } + assign { } { } + assign $0\src30__data_o$next[1:0]$10302 $7\src30__data_o$next[1:0]$10309 + attribute \src "libresoc.v:164058.5-164058.29" + switch \initial + attribute \src "libresoc.v:164058.9-164058.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src30__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src30__data_o$next[1:0]$10303 $6\src30__data_o$next[1:0]$10308 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest10__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src30__data_o$next[1:0]$10304 \dest10__data_i + case + assign $2\src30__data_o$next[1:0]$10304 2'00 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest20__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src30__data_o$next[1:0]$10305 \dest20__data_i + case + assign $3\src30__data_o$next[1:0]$10305 $2\src30__data_o$next[1:0]$10304 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest30__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src30__data_o$next[1:0]$10306 \dest30__data_i + case + assign $4\src30__data_o$next[1:0]$10306 $3\src30__data_o$next[1:0]$10305 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src30__data_o$next[1:0]$10307 \w0__data_i + case + assign $5\src30__data_o$next[1:0]$10307 $4\src30__data_o$next[1:0]$10306 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$6 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src30__data_o$next[1:0]$10308 \reg + case + assign $6\src30__data_o$next[1:0]$10308 $5\src30__data_o$next[1:0]$10307 + end + case + assign $1\src30__data_o$next[1:0]$10303 2'00 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\src30__data_o$next[1:0]$10309 2'00 + case + assign $7\src30__data_o$next[1:0]$10309 $1\src30__data_o$next[1:0]$10303 + end + sync always + update \src30__data_o$next $0\src30__data_o$next[1:0]$10302 + end + attribute \src "libresoc.v:164103.3-164138.6" + process $proc$libresoc.v:164103$10310 + assign { } { } + assign { } { } + assign $0\wr_detect$7[0:0]$10311 $1\wr_detect$7[0:0]$10312 + attribute \src "libresoc.v:164104.5-164104.29" + switch \initial + attribute \src "libresoc.v:164104.9-164104.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src30__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$7[0:0]$10312 $5\wr_detect$7[0:0]$10316 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest10__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$7[0:0]$10313 1'1 + case + assign $2\wr_detect$7[0:0]$10313 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest20__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$7[0:0]$10314 1'1 + case + assign $3\wr_detect$7[0:0]$10314 $2\wr_detect$7[0:0]$10313 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest30__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$7[0:0]$10315 1'1 + case + assign $4\wr_detect$7[0:0]$10315 $3\wr_detect$7[0:0]$10314 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\wr_detect$7[0:0]$10316 1'1 + case + assign $5\wr_detect$7[0:0]$10316 $4\wr_detect$7[0:0]$10315 + end + case + assign $1\wr_detect$7[0:0]$10312 1'0 + end + sync always + update \wr_detect$7 $0\wr_detect$7[0:0]$10311 + end + attribute \src "libresoc.v:164139.3-164184.6" + process $proc$libresoc.v:164139$10317 + assign { } { } + assign { } { } + assign { } { } + assign $0\r0__data_o$next[1:0]$10318 $7\r0__data_o$next[1:0]$10325 + attribute \src "libresoc.v:164140.5-164140.29" + switch \initial + attribute \src "libresoc.v:164140.9-164140.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r0__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\r0__data_o$next[1:0]$10319 $6\r0__data_o$next[1:0]$10324 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest10__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r0__data_o$next[1:0]$10320 \dest10__data_i + case + assign $2\r0__data_o$next[1:0]$10320 2'00 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest20__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\r0__data_o$next[1:0]$10321 \dest20__data_i + case + assign $3\r0__data_o$next[1:0]$10321 $2\r0__data_o$next[1:0]$10320 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest30__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\r0__data_o$next[1:0]$10322 \dest30__data_i + case + assign $4\r0__data_o$next[1:0]$10322 $3\r0__data_o$next[1:0]$10321 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\r0__data_o$next[1:0]$10323 \w0__data_i + case + assign $5\r0__data_o$next[1:0]$10323 $4\r0__data_o$next[1:0]$10322 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$9 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\r0__data_o$next[1:0]$10324 \reg + case + assign $6\r0__data_o$next[1:0]$10324 $5\r0__data_o$next[1:0]$10323 + end + case + assign $1\r0__data_o$next[1:0]$10319 2'00 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\r0__data_o$next[1:0]$10325 2'00 + case + assign $7\r0__data_o$next[1:0]$10325 $1\r0__data_o$next[1:0]$10319 + end + sync always + update \r0__data_o$next $0\r0__data_o$next[1:0]$10318 + end + attribute \src "libresoc.v:164185.3-164220.6" + process $proc$libresoc.v:164185$10326 + assign { } { } + assign { } { } + assign $0\wr_detect$10[0:0]$10327 $1\wr_detect$10[0:0]$10328 + attribute \src "libresoc.v:164186.5-164186.29" + switch \initial + attribute \src "libresoc.v:164186.9-164186.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r0__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$10[0:0]$10328 $5\wr_detect$10[0:0]$10332 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest10__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$10[0:0]$10329 1'1 + case + assign $2\wr_detect$10[0:0]$10329 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest20__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$10[0:0]$10330 1'1 + case + assign $3\wr_detect$10[0:0]$10330 $2\wr_detect$10[0:0]$10329 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest30__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$10[0:0]$10331 1'1 + case + assign $4\wr_detect$10[0:0]$10331 $3\wr_detect$10[0:0]$10330 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\wr_detect$10[0:0]$10332 1'1 + case + assign $5\wr_detect$10[0:0]$10332 $4\wr_detect$10[0:0]$10331 + end + case + assign $1\wr_detect$10[0:0]$10328 1'0 + end + sync always + update \wr_detect$10 $0\wr_detect$10[0:0]$10327 + end + attribute \src "libresoc.v:164221.3-164253.6" + process $proc$libresoc.v:164221$10333 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\reg$next[1:0]$10334 $5\reg$next[1:0]$10339 + attribute \src "libresoc.v:164222.5-164222.29" + switch \initial + attribute \src "libresoc.v:164222.9-164222.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest10__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\reg$next[1:0]$10335 \dest10__data_i + case + assign $1\reg$next[1:0]$10335 \reg + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest20__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\reg$next[1:0]$10336 \dest20__data_i + case + assign $2\reg$next[1:0]$10336 $1\reg$next[1:0]$10335 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest30__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\reg$next[1:0]$10337 \dest30__data_i + case + assign $3\reg$next[1:0]$10337 $2\reg$next[1:0]$10336 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \w0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\reg$next[1:0]$10338 \w0__data_i + case + assign $4\reg$next[1:0]$10338 $3\reg$next[1:0]$10337 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\reg$next[1:0]$10339 2'00 + case + assign $5\reg$next[1:0]$10339 $4\reg$next[1:0]$10338 + end + sync always + update \reg$next $0\reg$next[1:0]$10334 + end + connect \$9 $not$libresoc.v:163879$10266_Y + connect \$1 $not$libresoc.v:163880$10267_Y + connect \$3 $not$libresoc.v:163881$10268_Y + connect \$6 $not$libresoc.v:163882$10269_Y +end +attribute \src "libresoc.v:164258.1-164477.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.state.reg_0" +attribute \generator "nMigen" +module \reg_0$132 + attribute \src "libresoc.v:164310.3-164349.6" + wire width 64 $0\cia0__data_o$next[63:0]$10352 + attribute \src "libresoc.v:164308.3-164309.41" + wire width 64 $0\cia0__data_o[63:0] + attribute \src "libresoc.v:164259.7-164259.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:164380.3-164419.6" + wire width 64 $0\msr0__data_o$next[63:0]$10361 + attribute \src "libresoc.v:164306.3-164307.41" + wire width 64 $0\msr0__data_o[63:0] + attribute \src "libresoc.v:164450.3-164476.6" + wire width 64 $0\reg$next[63:0]$10375 + attribute \src "libresoc.v:164304.3-164305.25" + wire width 64 $0\reg[63:0] + attribute \src "libresoc.v:164420.3-164449.6" + wire $0\wr_detect$4[0:0]$10369 + attribute \src "libresoc.v:164350.3-164379.6" + wire $0\wr_detect[0:0] + attribute \src "libresoc.v:164310.3-164349.6" + wire width 64 $1\cia0__data_o$next[63:0]$10353 + attribute \src "libresoc.v:164266.14-164266.49" + wire width 64 $1\cia0__data_o[63:0] + attribute \src "libresoc.v:164380.3-164419.6" + wire width 64 $1\msr0__data_o$next[63:0]$10362 + attribute \src "libresoc.v:164283.14-164283.49" + wire width 64 $1\msr0__data_o[63:0] + attribute \src "libresoc.v:164450.3-164476.6" + wire width 64 $1\reg$next[63:0]$10376 + attribute \src "libresoc.v:164295.14-164295.42" + wire width 64 $1\reg[63:0] + attribute \src "libresoc.v:164420.3-164449.6" + wire $1\wr_detect$4[0:0]$10370 + attribute \src "libresoc.v:164350.3-164379.6" + wire $1\wr_detect[0:0] + attribute \src "libresoc.v:164310.3-164349.6" + wire width 64 $2\cia0__data_o$next[63:0]$10354 + attribute \src "libresoc.v:164380.3-164419.6" + wire width 64 $2\msr0__data_o$next[63:0]$10363 + attribute \src "libresoc.v:164450.3-164476.6" + wire width 64 $2\reg$next[63:0]$10377 + attribute \src "libresoc.v:164420.3-164449.6" + wire $2\wr_detect$4[0:0]$10371 + attribute \src "libresoc.v:164350.3-164379.6" + wire $2\wr_detect[0:0] + attribute \src "libresoc.v:164310.3-164349.6" + wire width 64 $3\cia0__data_o$next[63:0]$10355 + attribute \src "libresoc.v:164380.3-164419.6" + wire width 64 $3\msr0__data_o$next[63:0]$10364 + attribute \src "libresoc.v:164450.3-164476.6" + wire width 64 $3\reg$next[63:0]$10378 + attribute \src "libresoc.v:164420.3-164449.6" + wire $3\wr_detect$4[0:0]$10372 + attribute \src "libresoc.v:164350.3-164379.6" + wire $3\wr_detect[0:0] + attribute \src "libresoc.v:164310.3-164349.6" + wire width 64 $4\cia0__data_o$next[63:0]$10356 + attribute \src "libresoc.v:164380.3-164419.6" + wire width 64 $4\msr0__data_o$next[63:0]$10365 + attribute \src "libresoc.v:164450.3-164476.6" + wire width 64 $4\reg$next[63:0]$10379 + attribute \src "libresoc.v:164420.3-164449.6" + wire $4\wr_detect$4[0:0]$10373 + attribute \src "libresoc.v:164350.3-164379.6" + wire $4\wr_detect[0:0] + attribute \src "libresoc.v:164310.3-164349.6" + wire width 64 $5\cia0__data_o$next[63:0]$10357 + attribute \src "libresoc.v:164380.3-164419.6" + wire width 64 $5\msr0__data_o$next[63:0]$10366 + attribute \src "libresoc.v:164310.3-164349.6" + wire width 64 $6\cia0__data_o$next[63:0]$10358 + attribute \src "libresoc.v:164380.3-164419.6" + wire width 64 $6\msr0__data_o$next[63:0]$10367 + attribute \src "libresoc.v:164302.17-164302.100" + wire $not$libresoc.v:164302$10346_Y + attribute \src "libresoc.v:164303.17-164303.103" + wire $not$libresoc.v:164303$10347_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 output 3 \cia0__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \cia0__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 2 \cia0__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 12 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 input 11 \d_wr10__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 10 \d_wr10__wen + attribute \src "libresoc.v:164259.7-164259.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 input 9 \msr0__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 output 5 \msr0__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \msr0__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 4 \msr0__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 8 \msr0__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 input 7 \nia0__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 6 \nia0__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 64 \reg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 64 \reg$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:164302$10346 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect + connect \Y $not$libresoc.v:164302$10346_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:164303$10347 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$4 + connect \Y $not$libresoc.v:164303$10347_Y + end + attribute \src "libresoc.v:164259.7-164259.20" + process $proc$libresoc.v:164259$10380 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:164266.14-164266.49" + process $proc$libresoc.v:164266$10381 + assign { } { } + assign $1\cia0__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \cia0__data_o $1\cia0__data_o[63:0] + end + attribute \src "libresoc.v:164283.14-164283.49" + process $proc$libresoc.v:164283$10382 + assign { } { } + assign $1\msr0__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \msr0__data_o $1\msr0__data_o[63:0] + end + attribute \src "libresoc.v:164295.14-164295.42" + process $proc$libresoc.v:164295$10383 + assign { } { } + assign $1\reg[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \reg $1\reg[63:0] + end + attribute \src "libresoc.v:164304.3-164305.25" + process $proc$libresoc.v:164304$10348 + assign { } { } + assign $0\reg[63:0] \reg$next + sync posedge \coresync_clk + update \reg $0\reg[63:0] + end + attribute \src "libresoc.v:164306.3-164307.41" + process $proc$libresoc.v:164306$10349 + assign { } { } + assign $0\msr0__data_o[63:0] \msr0__data_o$next + sync posedge \coresync_clk + update \msr0__data_o $0\msr0__data_o[63:0] + end + attribute \src "libresoc.v:164308.3-164309.41" + process $proc$libresoc.v:164308$10350 + assign { } { } + assign $0\cia0__data_o[63:0] \cia0__data_o$next + sync posedge \coresync_clk + update \cia0__data_o $0\cia0__data_o[63:0] + end + attribute \src "libresoc.v:164310.3-164349.6" + process $proc$libresoc.v:164310$10351 + assign { } { } + assign { } { } + assign { } { } + assign $0\cia0__data_o$next[63:0]$10352 $6\cia0__data_o$next[63:0]$10358 + attribute \src "libresoc.v:164311.5-164311.29" + switch \initial + attribute \src "libresoc.v:164311.9-164311.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \cia0__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\cia0__data_o$next[63:0]$10353 $5\cia0__data_o$next[63:0]$10357 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \nia0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cia0__data_o$next[63:0]$10354 \nia0__data_i + case + assign $2\cia0__data_o$next[63:0]$10354 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \msr0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\cia0__data_o$next[63:0]$10355 \msr0__data_i + case + assign $3\cia0__data_o$next[63:0]$10355 $2\cia0__data_o$next[63:0]$10354 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \d_wr10__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\cia0__data_o$next[63:0]$10356 \d_wr10__data_i + case + assign $4\cia0__data_o$next[63:0]$10356 $3\cia0__data_o$next[63:0]$10355 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\cia0__data_o$next[63:0]$10357 \reg + case + assign $5\cia0__data_o$next[63:0]$10357 $4\cia0__data_o$next[63:0]$10356 + end + case + assign $1\cia0__data_o$next[63:0]$10353 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\cia0__data_o$next[63:0]$10358 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $6\cia0__data_o$next[63:0]$10358 $1\cia0__data_o$next[63:0]$10353 + end + sync always + update \cia0__data_o$next $0\cia0__data_o$next[63:0]$10352 + end + attribute \src "libresoc.v:164350.3-164379.6" + process $proc$libresoc.v:164350$10359 + assign { } { } + assign { } { } + assign $0\wr_detect[0:0] $1\wr_detect[0:0] + attribute \src "libresoc.v:164351.5-164351.29" + switch \initial + attribute \src "libresoc.v:164351.9-164351.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \cia0__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect[0:0] $4\wr_detect[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \nia0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect[0:0] 1'1 + case + assign $2\wr_detect[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \msr0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect[0:0] 1'1 + case + assign $3\wr_detect[0:0] $2\wr_detect[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \d_wr10__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect[0:0] 1'1 + case + assign $4\wr_detect[0:0] $3\wr_detect[0:0] + end + case + assign $1\wr_detect[0:0] 1'0 + end + sync always + update \wr_detect $0\wr_detect[0:0] + end + attribute \src "libresoc.v:164380.3-164419.6" + process $proc$libresoc.v:164380$10360 + assign { } { } + assign { } { } + assign { } { } + assign $0\msr0__data_o$next[63:0]$10361 $6\msr0__data_o$next[63:0]$10367 + attribute \src "libresoc.v:164381.5-164381.29" + switch \initial + attribute \src "libresoc.v:164381.9-164381.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \msr0__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\msr0__data_o$next[63:0]$10362 $5\msr0__data_o$next[63:0]$10366 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \nia0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\msr0__data_o$next[63:0]$10363 \nia0__data_i + case + assign $2\msr0__data_o$next[63:0]$10363 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \msr0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\msr0__data_o$next[63:0]$10364 \msr0__data_i + case + assign $3\msr0__data_o$next[63:0]$10364 $2\msr0__data_o$next[63:0]$10363 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \d_wr10__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\msr0__data_o$next[63:0]$10365 \d_wr10__data_i + case + assign $4\msr0__data_o$next[63:0]$10365 $3\msr0__data_o$next[63:0]$10364 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\msr0__data_o$next[63:0]$10366 \reg + case + assign $5\msr0__data_o$next[63:0]$10366 $4\msr0__data_o$next[63:0]$10365 + end + case + assign $1\msr0__data_o$next[63:0]$10362 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\msr0__data_o$next[63:0]$10367 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $6\msr0__data_o$next[63:0]$10367 $1\msr0__data_o$next[63:0]$10362 + end + sync always + update \msr0__data_o$next $0\msr0__data_o$next[63:0]$10361 + end + attribute \src "libresoc.v:164420.3-164449.6" + process $proc$libresoc.v:164420$10368 + assign { } { } + assign { } { } + assign $0\wr_detect$4[0:0]$10369 $1\wr_detect$4[0:0]$10370 + attribute \src "libresoc.v:164421.5-164421.29" + switch \initial + attribute \src "libresoc.v:164421.9-164421.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \msr0__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$4[0:0]$10370 $4\wr_detect$4[0:0]$10373 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \nia0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$4[0:0]$10371 1'1 + case + assign $2\wr_detect$4[0:0]$10371 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \msr0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$4[0:0]$10372 1'1 + case + assign $3\wr_detect$4[0:0]$10372 $2\wr_detect$4[0:0]$10371 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \d_wr10__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$4[0:0]$10373 1'1 + case + assign $4\wr_detect$4[0:0]$10373 $3\wr_detect$4[0:0]$10372 + end + case + assign $1\wr_detect$4[0:0]$10370 1'0 + end + sync always + update \wr_detect$4 $0\wr_detect$4[0:0]$10369 + end + attribute \src "libresoc.v:164450.3-164476.6" + process $proc$libresoc.v:164450$10374 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\reg$next[63:0]$10375 $4\reg$next[63:0]$10379 + attribute \src "libresoc.v:164451.5-164451.29" + switch \initial + attribute \src "libresoc.v:164451.9-164451.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \nia0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\reg$next[63:0]$10376 \nia0__data_i + case + assign $1\reg$next[63:0]$10376 \reg + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \msr0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\reg$next[63:0]$10377 \msr0__data_i + case + assign $2\reg$next[63:0]$10377 $1\reg$next[63:0]$10376 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \d_wr10__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\reg$next[63:0]$10378 \d_wr10__data_i + case + assign $3\reg$next[63:0]$10378 $2\reg$next[63:0]$10377 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\reg$next[63:0]$10379 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $4\reg$next[63:0]$10379 $3\reg$next[63:0]$10378 + end + sync always + update \reg$next $0\reg$next[63:0]$10375 + end + connect \$1 $not$libresoc.v:164302$10346_Y + connect \$3 $not$libresoc.v:164303$10347_Y +end +attribute \src "libresoc.v:164481.1-164952.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.cr.reg_1" +attribute \generator "nMigen" +module \reg_1 + attribute \src "libresoc.v:164482.7-164482.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:164812.3-164851.6" + wire width 4 $0\r1__data_o$next[3:0]$10439 + attribute \src "libresoc.v:164567.3-164568.37" + wire width 4 $0\r1__data_o[3:0] + attribute \src "libresoc.v:164882.3-164921.6" + wire width 4 $0\r21__data_o$next[3:0]$10453 + attribute \src "libresoc.v:164565.3-164566.39" + wire width 4 $0\r21__data_o[3:0] + attribute \src "libresoc.v:164645.3-164671.6" + wire width 4 $0\reg$next[3:0]$10405 + attribute \src "libresoc.v:164563.3-164564.25" + wire width 4 $0\reg[3:0] + attribute \src "libresoc.v:164575.3-164614.6" + wire width 4 $0\src11__data_o$next[3:0]$10396 + attribute \src "libresoc.v:164573.3-164574.43" + wire width 4 $0\src11__data_o[3:0] + attribute \src "libresoc.v:164672.3-164711.6" + wire width 4 $0\src21__data_o$next[3:0]$10411 + attribute \src "libresoc.v:164571.3-164572.43" + wire width 4 $0\src21__data_o[3:0] + attribute \src "libresoc.v:164742.3-164781.6" + wire width 4 $0\src31__data_o$next[3:0]$10425 + attribute \src "libresoc.v:164569.3-164570.43" + wire width 4 $0\src31__data_o[3:0] + attribute \src "libresoc.v:164852.3-164881.6" + wire $0\wr_detect$10[0:0]$10447 + attribute \src "libresoc.v:164922.3-164951.6" + wire $0\wr_detect$13[0:0]$10461 + attribute \src "libresoc.v:164712.3-164741.6" + wire $0\wr_detect$4[0:0]$10419 + attribute \src "libresoc.v:164782.3-164811.6" + wire $0\wr_detect$7[0:0]$10433 + attribute \src "libresoc.v:164615.3-164644.6" + wire $0\wr_detect[0:0] + attribute \src "libresoc.v:164812.3-164851.6" + wire width 4 $1\r1__data_o$next[3:0]$10440 + attribute \src "libresoc.v:164507.13-164507.30" + wire width 4 $1\r1__data_o[3:0] + attribute \src "libresoc.v:164882.3-164921.6" + wire width 4 $1\r21__data_o$next[3:0]$10454 + attribute \src "libresoc.v:164514.13-164514.31" + wire width 4 $1\r21__data_o[3:0] + attribute \src "libresoc.v:164645.3-164671.6" + wire width 4 $1\reg$next[3:0]$10406 + attribute \src "libresoc.v:164520.13-164520.25" + wire width 4 $1\reg[3:0] + attribute \src "libresoc.v:164575.3-164614.6" + wire width 4 $1\src11__data_o$next[3:0]$10397 + attribute \src "libresoc.v:164525.13-164525.33" + wire width 4 $1\src11__data_o[3:0] + attribute \src "libresoc.v:164672.3-164711.6" + wire width 4 $1\src21__data_o$next[3:0]$10412 + attribute \src "libresoc.v:164532.13-164532.33" + wire width 4 $1\src21__data_o[3:0] + attribute \src "libresoc.v:164742.3-164781.6" + wire width 4 $1\src31__data_o$next[3:0]$10426 + attribute \src "libresoc.v:164539.13-164539.33" + wire width 4 $1\src31__data_o[3:0] + attribute \src "libresoc.v:164852.3-164881.6" + wire $1\wr_detect$10[0:0]$10448 + attribute \src "libresoc.v:164922.3-164951.6" + wire $1\wr_detect$13[0:0]$10462 + attribute \src "libresoc.v:164712.3-164741.6" + wire $1\wr_detect$4[0:0]$10420 + attribute \src "libresoc.v:164782.3-164811.6" + wire $1\wr_detect$7[0:0]$10434 + attribute \src "libresoc.v:164615.3-164644.6" + wire $1\wr_detect[0:0] + attribute \src "libresoc.v:164812.3-164851.6" + wire width 4 $2\r1__data_o$next[3:0]$10441 + attribute \src "libresoc.v:164882.3-164921.6" + wire width 4 $2\r21__data_o$next[3:0]$10455 + attribute \src "libresoc.v:164645.3-164671.6" + wire width 4 $2\reg$next[3:0]$10407 + attribute \src "libresoc.v:164575.3-164614.6" + wire width 4 $2\src11__data_o$next[3:0]$10398 + attribute \src "libresoc.v:164672.3-164711.6" + wire width 4 $2\src21__data_o$next[3:0]$10413 + attribute \src "libresoc.v:164742.3-164781.6" + wire width 4 $2\src31__data_o$next[3:0]$10427 + attribute \src "libresoc.v:164852.3-164881.6" + wire $2\wr_detect$10[0:0]$10449 + attribute \src "libresoc.v:164922.3-164951.6" + wire $2\wr_detect$13[0:0]$10463 + attribute \src "libresoc.v:164712.3-164741.6" + wire $2\wr_detect$4[0:0]$10421 + attribute \src "libresoc.v:164782.3-164811.6" + wire $2\wr_detect$7[0:0]$10435 + attribute \src "libresoc.v:164615.3-164644.6" + wire $2\wr_detect[0:0] + attribute \src "libresoc.v:164812.3-164851.6" + wire width 4 $3\r1__data_o$next[3:0]$10442 + attribute \src "libresoc.v:164882.3-164921.6" + wire width 4 $3\r21__data_o$next[3:0]$10456 + attribute \src "libresoc.v:164645.3-164671.6" + wire width 4 $3\reg$next[3:0]$10408 + attribute \src "libresoc.v:164575.3-164614.6" + wire width 4 $3\src11__data_o$next[3:0]$10399 + attribute \src "libresoc.v:164672.3-164711.6" + wire width 4 $3\src21__data_o$next[3:0]$10414 + attribute \src "libresoc.v:164742.3-164781.6" + wire width 4 $3\src31__data_o$next[3:0]$10428 + attribute \src "libresoc.v:164852.3-164881.6" + wire $3\wr_detect$10[0:0]$10450 + attribute \src "libresoc.v:164922.3-164951.6" + wire $3\wr_detect$13[0:0]$10464 + attribute \src "libresoc.v:164712.3-164741.6" + wire $3\wr_detect$4[0:0]$10422 + attribute \src "libresoc.v:164782.3-164811.6" + wire $3\wr_detect$7[0:0]$10436 + attribute \src "libresoc.v:164615.3-164644.6" + wire $3\wr_detect[0:0] + attribute \src "libresoc.v:164812.3-164851.6" + wire width 4 $4\r1__data_o$next[3:0]$10443 + attribute \src "libresoc.v:164882.3-164921.6" + wire width 4 $4\r21__data_o$next[3:0]$10457 + attribute \src "libresoc.v:164645.3-164671.6" + wire width 4 $4\reg$next[3:0]$10409 + attribute \src "libresoc.v:164575.3-164614.6" + wire width 4 $4\src11__data_o$next[3:0]$10400 + attribute \src "libresoc.v:164672.3-164711.6" + wire width 4 $4\src21__data_o$next[3:0]$10415 + attribute \src "libresoc.v:164742.3-164781.6" + wire width 4 $4\src31__data_o$next[3:0]$10429 + attribute \src "libresoc.v:164852.3-164881.6" + wire $4\wr_detect$10[0:0]$10451 + attribute \src "libresoc.v:164922.3-164951.6" + wire $4\wr_detect$13[0:0]$10465 + attribute \src "libresoc.v:164712.3-164741.6" + wire $4\wr_detect$4[0:0]$10423 + attribute \src "libresoc.v:164782.3-164811.6" + wire $4\wr_detect$7[0:0]$10437 + attribute \src "libresoc.v:164615.3-164644.6" + wire $4\wr_detect[0:0] + attribute \src "libresoc.v:164812.3-164851.6" + wire width 4 $5\r1__data_o$next[3:0]$10444 + attribute \src "libresoc.v:164882.3-164921.6" + wire width 4 $5\r21__data_o$next[3:0]$10458 + attribute \src "libresoc.v:164575.3-164614.6" + wire width 4 $5\src11__data_o$next[3:0]$10401 + attribute \src "libresoc.v:164672.3-164711.6" + wire width 4 $5\src21__data_o$next[3:0]$10416 + attribute \src "libresoc.v:164742.3-164781.6" + wire width 4 $5\src31__data_o$next[3:0]$10430 + attribute \src "libresoc.v:164812.3-164851.6" + wire width 4 $6\r1__data_o$next[3:0]$10445 + attribute \src "libresoc.v:164882.3-164921.6" + wire width 4 $6\r21__data_o$next[3:0]$10459 + attribute \src "libresoc.v:164575.3-164614.6" + wire width 4 $6\src11__data_o$next[3:0]$10402 + attribute \src "libresoc.v:164672.3-164711.6" + wire width 4 $6\src21__data_o$next[3:0]$10417 + attribute \src "libresoc.v:164742.3-164781.6" + wire width 4 $6\src31__data_o$next[3:0]$10431 + attribute \src "libresoc.v:164558.17-164558.104" + wire $not$libresoc.v:164558$10384_Y + attribute \src "libresoc.v:164559.18-164559.105" + wire $not$libresoc.v:164559$10385_Y + attribute \src "libresoc.v:164560.17-164560.100" + wire $not$libresoc.v:164560$10386_Y + attribute \src "libresoc.v:164561.17-164561.103" + wire $not$libresoc.v:164561$10387_Y + attribute \src "libresoc.v:164562.17-164562.103" + wire $not$libresoc.v:164562$10388_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 18 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 input 9 \dest11__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 8 \dest11__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 input 11 \dest21__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 10 \dest21__wen + attribute \src "libresoc.v:164482.7-164482.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 12 \r1__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \r1__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 13 \r1__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 14 \r21__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \r21__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 15 \r21__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 4 \reg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 4 \reg$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 3 \src11__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \src11__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 2 \src11__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 5 \src21__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \src21__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 4 \src21__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 7 \src31__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \src31__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 6 \src31__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 input 16 \w1__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 17 \w1__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:164558$10384 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$10 + connect \Y $not$libresoc.v:164558$10384_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:164559$10385 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$13 + connect \Y $not$libresoc.v:164559$10385_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:164560$10386 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect + connect \Y $not$libresoc.v:164560$10386_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:164561$10387 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$4 + connect \Y $not$libresoc.v:164561$10387_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:164562$10388 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$7 + connect \Y $not$libresoc.v:164562$10388_Y + end + attribute \src "libresoc.v:164482.7-164482.20" + process $proc$libresoc.v:164482$10466 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:164507.13-164507.30" + process $proc$libresoc.v:164507$10467 + assign { } { } + assign $1\r1__data_o[3:0] 4'0000 + sync always + sync init + update \r1__data_o $1\r1__data_o[3:0] + end + attribute \src "libresoc.v:164514.13-164514.31" + process $proc$libresoc.v:164514$10468 + assign { } { } + assign $1\r21__data_o[3:0] 4'0000 + sync always + sync init + update \r21__data_o $1\r21__data_o[3:0] + end + attribute \src "libresoc.v:164520.13-164520.25" + process $proc$libresoc.v:164520$10469 + assign { } { } + assign $1\reg[3:0] 4'0000 + sync always + sync init + update \reg $1\reg[3:0] + end + attribute \src "libresoc.v:164525.13-164525.33" + process $proc$libresoc.v:164525$10470 + assign { } { } + assign $1\src11__data_o[3:0] 4'0000 + sync always + sync init + update \src11__data_o $1\src11__data_o[3:0] + end + attribute \src "libresoc.v:164532.13-164532.33" + process $proc$libresoc.v:164532$10471 + assign { } { } + assign $1\src21__data_o[3:0] 4'0000 + sync always + sync init + update \src21__data_o $1\src21__data_o[3:0] + end + attribute \src "libresoc.v:164539.13-164539.33" + process $proc$libresoc.v:164539$10472 + assign { } { } + assign $1\src31__data_o[3:0] 4'0000 + sync always + sync init + update \src31__data_o $1\src31__data_o[3:0] + end + attribute \src "libresoc.v:164563.3-164564.25" + process $proc$libresoc.v:164563$10389 + assign { } { } + assign $0\reg[3:0] \reg$next + sync posedge \coresync_clk + update \reg $0\reg[3:0] + end + attribute \src "libresoc.v:164565.3-164566.39" + process $proc$libresoc.v:164565$10390 + assign { } { } + assign $0\r21__data_o[3:0] \r21__data_o$next + sync posedge \coresync_clk + update \r21__data_o $0\r21__data_o[3:0] + end + attribute \src "libresoc.v:164567.3-164568.37" + process $proc$libresoc.v:164567$10391 + assign { } { } + assign $0\r1__data_o[3:0] \r1__data_o$next + sync posedge \coresync_clk + update \r1__data_o $0\r1__data_o[3:0] + end + attribute \src "libresoc.v:164569.3-164570.43" + process $proc$libresoc.v:164569$10392 + assign { } { } + assign $0\src31__data_o[3:0] \src31__data_o$next + sync posedge \coresync_clk + update \src31__data_o $0\src31__data_o[3:0] + end + attribute \src "libresoc.v:164571.3-164572.43" + process $proc$libresoc.v:164571$10393 + assign { } { } + assign $0\src21__data_o[3:0] \src21__data_o$next + sync posedge \coresync_clk + update \src21__data_o $0\src21__data_o[3:0] + end + attribute \src "libresoc.v:164573.3-164574.43" + process $proc$libresoc.v:164573$10394 + assign { } { } + assign $0\src11__data_o[3:0] \src11__data_o$next + sync posedge \coresync_clk + update \src11__data_o $0\src11__data_o[3:0] + end + attribute \src "libresoc.v:164575.3-164614.6" + process $proc$libresoc.v:164575$10395 + assign { } { } + assign { } { } + assign { } { } + assign $0\src11__data_o$next[3:0]$10396 $6\src11__data_o$next[3:0]$10402 + attribute \src "libresoc.v:164576.5-164576.29" + switch \initial + attribute \src "libresoc.v:164576.9-164576.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src11__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src11__data_o$next[3:0]$10397 $5\src11__data_o$next[3:0]$10401 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest11__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src11__data_o$next[3:0]$10398 \dest11__data_i + case + assign $2\src11__data_o$next[3:0]$10398 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest21__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src11__data_o$next[3:0]$10399 \dest21__data_i + case + assign $3\src11__data_o$next[3:0]$10399 $2\src11__data_o$next[3:0]$10398 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src11__data_o$next[3:0]$10400 \w1__data_i + case + assign $4\src11__data_o$next[3:0]$10400 $3\src11__data_o$next[3:0]$10399 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src11__data_o$next[3:0]$10401 \reg + case + assign $5\src11__data_o$next[3:0]$10401 $4\src11__data_o$next[3:0]$10400 + end + case + assign $1\src11__data_o$next[3:0]$10397 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src11__data_o$next[3:0]$10402 4'0000 + case + assign $6\src11__data_o$next[3:0]$10402 $1\src11__data_o$next[3:0]$10397 + end + sync always + update \src11__data_o$next $0\src11__data_o$next[3:0]$10396 + end + attribute \src "libresoc.v:164615.3-164644.6" + process $proc$libresoc.v:164615$10403 + assign { } { } + assign { } { } + assign $0\wr_detect[0:0] $1\wr_detect[0:0] + attribute \src "libresoc.v:164616.5-164616.29" + switch \initial + attribute \src "libresoc.v:164616.9-164616.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src11__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect[0:0] $4\wr_detect[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest11__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect[0:0] 1'1 + case + assign $2\wr_detect[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest21__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect[0:0] 1'1 + case + assign $3\wr_detect[0:0] $2\wr_detect[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect[0:0] 1'1 + case + assign $4\wr_detect[0:0] $3\wr_detect[0:0] + end + case + assign $1\wr_detect[0:0] 1'0 + end + sync always + update \wr_detect $0\wr_detect[0:0] + end + attribute \src "libresoc.v:164645.3-164671.6" + process $proc$libresoc.v:164645$10404 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\reg$next[3:0]$10405 $4\reg$next[3:0]$10409 + attribute \src "libresoc.v:164646.5-164646.29" + switch \initial + attribute \src "libresoc.v:164646.9-164646.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest11__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\reg$next[3:0]$10406 \dest11__data_i + case + assign $1\reg$next[3:0]$10406 \reg + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest21__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\reg$next[3:0]$10407 \dest21__data_i + case + assign $2\reg$next[3:0]$10407 $1\reg$next[3:0]$10406 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \w1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\reg$next[3:0]$10408 \w1__data_i + case + assign $3\reg$next[3:0]$10408 $2\reg$next[3:0]$10407 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\reg$next[3:0]$10409 4'0000 + case + assign $4\reg$next[3:0]$10409 $3\reg$next[3:0]$10408 + end + sync always + update \reg$next $0\reg$next[3:0]$10405 + end + attribute \src "libresoc.v:164672.3-164711.6" + process $proc$libresoc.v:164672$10410 + assign { } { } + assign { } { } + assign { } { } + assign $0\src21__data_o$next[3:0]$10411 $6\src21__data_o$next[3:0]$10417 + attribute \src "libresoc.v:164673.5-164673.29" + switch \initial + attribute \src "libresoc.v:164673.9-164673.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src21__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src21__data_o$next[3:0]$10412 $5\src21__data_o$next[3:0]$10416 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest11__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src21__data_o$next[3:0]$10413 \dest11__data_i + case + assign $2\src21__data_o$next[3:0]$10413 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest21__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src21__data_o$next[3:0]$10414 \dest21__data_i + case + assign $3\src21__data_o$next[3:0]$10414 $2\src21__data_o$next[3:0]$10413 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src21__data_o$next[3:0]$10415 \w1__data_i + case + assign $4\src21__data_o$next[3:0]$10415 $3\src21__data_o$next[3:0]$10414 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src21__data_o$next[3:0]$10416 \reg + case + assign $5\src21__data_o$next[3:0]$10416 $4\src21__data_o$next[3:0]$10415 + end + case + assign $1\src21__data_o$next[3:0]$10412 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src21__data_o$next[3:0]$10417 4'0000 + case + assign $6\src21__data_o$next[3:0]$10417 $1\src21__data_o$next[3:0]$10412 + end + sync always + update \src21__data_o$next $0\src21__data_o$next[3:0]$10411 + end + attribute \src "libresoc.v:164712.3-164741.6" + process $proc$libresoc.v:164712$10418 + assign { } { } + assign { } { } + assign $0\wr_detect$4[0:0]$10419 $1\wr_detect$4[0:0]$10420 + attribute \src "libresoc.v:164713.5-164713.29" + switch \initial + attribute \src "libresoc.v:164713.9-164713.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src21__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$4[0:0]$10420 $4\wr_detect$4[0:0]$10423 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest11__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$4[0:0]$10421 1'1 + case + assign $2\wr_detect$4[0:0]$10421 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest21__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$4[0:0]$10422 1'1 + case + assign $3\wr_detect$4[0:0]$10422 $2\wr_detect$4[0:0]$10421 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$4[0:0]$10423 1'1 + case + assign $4\wr_detect$4[0:0]$10423 $3\wr_detect$4[0:0]$10422 + end + case + assign $1\wr_detect$4[0:0]$10420 1'0 + end + sync always + update \wr_detect$4 $0\wr_detect$4[0:0]$10419 + end + attribute \src "libresoc.v:164742.3-164781.6" + process $proc$libresoc.v:164742$10424 + assign { } { } + assign { } { } + assign { } { } + assign $0\src31__data_o$next[3:0]$10425 $6\src31__data_o$next[3:0]$10431 + attribute \src "libresoc.v:164743.5-164743.29" + switch \initial + attribute \src "libresoc.v:164743.9-164743.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src31__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src31__data_o$next[3:0]$10426 $5\src31__data_o$next[3:0]$10430 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest11__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src31__data_o$next[3:0]$10427 \dest11__data_i + case + assign $2\src31__data_o$next[3:0]$10427 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest21__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src31__data_o$next[3:0]$10428 \dest21__data_i + case + assign $3\src31__data_o$next[3:0]$10428 $2\src31__data_o$next[3:0]$10427 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src31__data_o$next[3:0]$10429 \w1__data_i + case + assign $4\src31__data_o$next[3:0]$10429 $3\src31__data_o$next[3:0]$10428 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$6 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src31__data_o$next[3:0]$10430 \reg + case + assign $5\src31__data_o$next[3:0]$10430 $4\src31__data_o$next[3:0]$10429 + end + case + assign $1\src31__data_o$next[3:0]$10426 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src31__data_o$next[3:0]$10431 4'0000 + case + assign $6\src31__data_o$next[3:0]$10431 $1\src31__data_o$next[3:0]$10426 + end + sync always + update \src31__data_o$next $0\src31__data_o$next[3:0]$10425 + end + attribute \src "libresoc.v:164782.3-164811.6" + process $proc$libresoc.v:164782$10432 + assign { } { } + assign { } { } + assign $0\wr_detect$7[0:0]$10433 $1\wr_detect$7[0:0]$10434 + attribute \src "libresoc.v:164783.5-164783.29" + switch \initial + attribute \src "libresoc.v:164783.9-164783.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src31__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$7[0:0]$10434 $4\wr_detect$7[0:0]$10437 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest11__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$7[0:0]$10435 1'1 + case + assign $2\wr_detect$7[0:0]$10435 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest21__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$7[0:0]$10436 1'1 + case + assign $3\wr_detect$7[0:0]$10436 $2\wr_detect$7[0:0]$10435 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$7[0:0]$10437 1'1 + case + assign $4\wr_detect$7[0:0]$10437 $3\wr_detect$7[0:0]$10436 + end + case + assign $1\wr_detect$7[0:0]$10434 1'0 + end + sync always + update \wr_detect$7 $0\wr_detect$7[0:0]$10433 + end + attribute \src "libresoc.v:164812.3-164851.6" + process $proc$libresoc.v:164812$10438 + assign { } { } + assign { } { } + assign { } { } + assign $0\r1__data_o$next[3:0]$10439 $6\r1__data_o$next[3:0]$10445 + attribute \src "libresoc.v:164813.5-164813.29" + switch \initial + attribute \src "libresoc.v:164813.9-164813.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r1__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\r1__data_o$next[3:0]$10440 $5\r1__data_o$next[3:0]$10444 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest11__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r1__data_o$next[3:0]$10441 \dest11__data_i + case + assign $2\r1__data_o$next[3:0]$10441 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest21__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\r1__data_o$next[3:0]$10442 \dest21__data_i + case + assign $3\r1__data_o$next[3:0]$10442 $2\r1__data_o$next[3:0]$10441 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\r1__data_o$next[3:0]$10443 \w1__data_i + case + assign $4\r1__data_o$next[3:0]$10443 $3\r1__data_o$next[3:0]$10442 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$9 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\r1__data_o$next[3:0]$10444 \reg + case + assign $5\r1__data_o$next[3:0]$10444 $4\r1__data_o$next[3:0]$10443 + end + case + assign $1\r1__data_o$next[3:0]$10440 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\r1__data_o$next[3:0]$10445 4'0000 + case + assign $6\r1__data_o$next[3:0]$10445 $1\r1__data_o$next[3:0]$10440 + end + sync always + update \r1__data_o$next $0\r1__data_o$next[3:0]$10439 + end + attribute \src "libresoc.v:164852.3-164881.6" + process $proc$libresoc.v:164852$10446 + assign { } { } + assign { } { } + assign $0\wr_detect$10[0:0]$10447 $1\wr_detect$10[0:0]$10448 + attribute \src "libresoc.v:164853.5-164853.29" + switch \initial + attribute \src "libresoc.v:164853.9-164853.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r1__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$10[0:0]$10448 $4\wr_detect$10[0:0]$10451 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest11__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$10[0:0]$10449 1'1 + case + assign $2\wr_detect$10[0:0]$10449 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest21__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$10[0:0]$10450 1'1 + case + assign $3\wr_detect$10[0:0]$10450 $2\wr_detect$10[0:0]$10449 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$10[0:0]$10451 1'1 + case + assign $4\wr_detect$10[0:0]$10451 $3\wr_detect$10[0:0]$10450 + end + case + assign $1\wr_detect$10[0:0]$10448 1'0 + end + sync always + update \wr_detect$10 $0\wr_detect$10[0:0]$10447 + end + attribute \src "libresoc.v:164882.3-164921.6" + process $proc$libresoc.v:164882$10452 + assign { } { } + assign { } { } + assign { } { } + assign $0\r21__data_o$next[3:0]$10453 $6\r21__data_o$next[3:0]$10459 + attribute \src "libresoc.v:164883.5-164883.29" + switch \initial + attribute \src "libresoc.v:164883.9-164883.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r21__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\r21__data_o$next[3:0]$10454 $5\r21__data_o$next[3:0]$10458 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest11__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r21__data_o$next[3:0]$10455 \dest11__data_i + case + assign $2\r21__data_o$next[3:0]$10455 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest21__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\r21__data_o$next[3:0]$10456 \dest21__data_i + case + assign $3\r21__data_o$next[3:0]$10456 $2\r21__data_o$next[3:0]$10455 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\r21__data_o$next[3:0]$10457 \w1__data_i + case + assign $4\r21__data_o$next[3:0]$10457 $3\r21__data_o$next[3:0]$10456 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$12 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\r21__data_o$next[3:0]$10458 \reg + case + assign $5\r21__data_o$next[3:0]$10458 $4\r21__data_o$next[3:0]$10457 + end + case + assign $1\r21__data_o$next[3:0]$10454 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\r21__data_o$next[3:0]$10459 4'0000 + case + assign $6\r21__data_o$next[3:0]$10459 $1\r21__data_o$next[3:0]$10454 + end + sync always + update \r21__data_o$next $0\r21__data_o$next[3:0]$10453 + end + attribute \src "libresoc.v:164922.3-164951.6" + process $proc$libresoc.v:164922$10460 + assign { } { } + assign { } { } + assign $0\wr_detect$13[0:0]$10461 $1\wr_detect$13[0:0]$10462 + attribute \src "libresoc.v:164923.5-164923.29" + switch \initial + attribute \src "libresoc.v:164923.9-164923.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r21__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$13[0:0]$10462 $4\wr_detect$13[0:0]$10465 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest11__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$13[0:0]$10463 1'1 + case + assign $2\wr_detect$13[0:0]$10463 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest21__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$13[0:0]$10464 1'1 + case + assign $3\wr_detect$13[0:0]$10464 $2\wr_detect$13[0:0]$10463 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$13[0:0]$10465 1'1 + case + assign $4\wr_detect$13[0:0]$10465 $3\wr_detect$13[0:0]$10464 + end + case + assign $1\wr_detect$13[0:0]$10462 1'0 + end + sync always + update \wr_detect$13 $0\wr_detect$13[0:0]$10461 + end + connect \$9 $not$libresoc.v:164558$10384_Y + connect \$12 $not$libresoc.v:164559$10385_Y + connect \$1 $not$libresoc.v:164560$10386_Y + connect \$3 $not$libresoc.v:164561$10387_Y + connect \$6 $not$libresoc.v:164562$10388_Y +end +attribute \src "libresoc.v:164956.1-165401.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.xer.reg_1" +attribute \generator "nMigen" +module \reg_1$130 + attribute \src "libresoc.v:164957.7-164957.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:165286.3-165331.6" + wire width 2 $0\r1__data_o$next[1:0]$10525 + attribute \src "libresoc.v:165032.3-165033.37" + wire width 2 $0\r1__data_o[1:0] + attribute \src "libresoc.v:165368.3-165400.6" + wire width 2 $0\reg$next[1:0]$10541 + attribute \src "libresoc.v:165030.3-165031.25" + wire width 2 $0\reg[1:0] + attribute \src "libresoc.v:165040.3-165085.6" + wire width 2 $0\src11__data_o$next[1:0]$10483 + attribute \src "libresoc.v:165038.3-165039.43" + wire width 2 $0\src11__data_o[1:0] + attribute \src "libresoc.v:165122.3-165167.6" + wire width 2 $0\src21__data_o$next[1:0]$10493 + attribute \src "libresoc.v:165036.3-165037.43" + wire width 2 $0\src21__data_o[1:0] + attribute \src "libresoc.v:165204.3-165249.6" + wire width 2 $0\src31__data_o$next[1:0]$10509 + attribute \src "libresoc.v:165034.3-165035.43" + wire width 2 $0\src31__data_o[1:0] + attribute \src "libresoc.v:165332.3-165367.6" + wire $0\wr_detect$10[0:0]$10534 + attribute \src "libresoc.v:165168.3-165203.6" + wire $0\wr_detect$4[0:0]$10502 + attribute \src "libresoc.v:165250.3-165285.6" + wire $0\wr_detect$7[0:0]$10518 + attribute \src "libresoc.v:165086.3-165121.6" + wire $0\wr_detect[0:0] + attribute \src "libresoc.v:165286.3-165331.6" + wire width 2 $1\r1__data_o$next[1:0]$10526 + attribute \src "libresoc.v:164984.13-164984.30" + wire width 2 $1\r1__data_o[1:0] + attribute \src "libresoc.v:165368.3-165400.6" + wire width 2 $1\reg$next[1:0]$10542 + attribute \src "libresoc.v:164990.13-164990.25" + wire width 2 $1\reg[1:0] + attribute \src "libresoc.v:165040.3-165085.6" + wire width 2 $1\src11__data_o$next[1:0]$10484 + attribute \src "libresoc.v:164995.13-164995.33" + wire width 2 $1\src11__data_o[1:0] + attribute \src "libresoc.v:165122.3-165167.6" + wire width 2 $1\src21__data_o$next[1:0]$10494 + attribute \src "libresoc.v:165002.13-165002.33" + wire width 2 $1\src21__data_o[1:0] + attribute \src "libresoc.v:165204.3-165249.6" + wire width 2 $1\src31__data_o$next[1:0]$10510 + attribute \src "libresoc.v:165009.13-165009.33" + wire width 2 $1\src31__data_o[1:0] + attribute \src "libresoc.v:165332.3-165367.6" + wire $1\wr_detect$10[0:0]$10535 + attribute \src "libresoc.v:165168.3-165203.6" + wire $1\wr_detect$4[0:0]$10503 + attribute \src "libresoc.v:165250.3-165285.6" + wire $1\wr_detect$7[0:0]$10519 + attribute \src "libresoc.v:165086.3-165121.6" + wire $1\wr_detect[0:0] + attribute \src "libresoc.v:165286.3-165331.6" + wire width 2 $2\r1__data_o$next[1:0]$10527 + attribute \src "libresoc.v:165368.3-165400.6" + wire width 2 $2\reg$next[1:0]$10543 + attribute \src "libresoc.v:165040.3-165085.6" + wire width 2 $2\src11__data_o$next[1:0]$10485 + attribute \src "libresoc.v:165122.3-165167.6" + wire width 2 $2\src21__data_o$next[1:0]$10495 + attribute \src "libresoc.v:165204.3-165249.6" + wire width 2 $2\src31__data_o$next[1:0]$10511 + attribute \src "libresoc.v:165332.3-165367.6" + wire $2\wr_detect$10[0:0]$10536 + attribute \src "libresoc.v:165168.3-165203.6" + wire $2\wr_detect$4[0:0]$10504 + attribute \src "libresoc.v:165250.3-165285.6" + wire $2\wr_detect$7[0:0]$10520 + attribute \src "libresoc.v:165086.3-165121.6" + wire $2\wr_detect[0:0] + attribute \src "libresoc.v:165286.3-165331.6" + wire width 2 $3\r1__data_o$next[1:0]$10528 + attribute \src "libresoc.v:165368.3-165400.6" + wire width 2 $3\reg$next[1:0]$10544 + attribute \src "libresoc.v:165040.3-165085.6" + wire width 2 $3\src11__data_o$next[1:0]$10486 + attribute \src "libresoc.v:165122.3-165167.6" + wire width 2 $3\src21__data_o$next[1:0]$10496 + attribute \src "libresoc.v:165204.3-165249.6" + wire width 2 $3\src31__data_o$next[1:0]$10512 + attribute \src "libresoc.v:165332.3-165367.6" + wire $3\wr_detect$10[0:0]$10537 + attribute \src "libresoc.v:165168.3-165203.6" + wire $3\wr_detect$4[0:0]$10505 + attribute \src "libresoc.v:165250.3-165285.6" + wire $3\wr_detect$7[0:0]$10521 + attribute \src "libresoc.v:165086.3-165121.6" + wire $3\wr_detect[0:0] + attribute \src "libresoc.v:165286.3-165331.6" + wire width 2 $4\r1__data_o$next[1:0]$10529 + attribute \src "libresoc.v:165368.3-165400.6" + wire width 2 $4\reg$next[1:0]$10545 + attribute \src "libresoc.v:165040.3-165085.6" + wire width 2 $4\src11__data_o$next[1:0]$10487 + attribute \src "libresoc.v:165122.3-165167.6" + wire width 2 $4\src21__data_o$next[1:0]$10497 + attribute \src "libresoc.v:165204.3-165249.6" + wire width 2 $4\src31__data_o$next[1:0]$10513 + attribute \src "libresoc.v:165332.3-165367.6" + wire $4\wr_detect$10[0:0]$10538 + attribute \src "libresoc.v:165168.3-165203.6" + wire $4\wr_detect$4[0:0]$10506 + attribute \src "libresoc.v:165250.3-165285.6" + wire $4\wr_detect$7[0:0]$10522 + attribute \src "libresoc.v:165086.3-165121.6" + wire $4\wr_detect[0:0] + attribute \src "libresoc.v:165286.3-165331.6" + wire width 2 $5\r1__data_o$next[1:0]$10530 + attribute \src "libresoc.v:165368.3-165400.6" + wire width 2 $5\reg$next[1:0]$10546 + attribute \src "libresoc.v:165040.3-165085.6" + wire width 2 $5\src11__data_o$next[1:0]$10488 + attribute \src "libresoc.v:165122.3-165167.6" + wire width 2 $5\src21__data_o$next[1:0]$10498 + attribute \src "libresoc.v:165204.3-165249.6" + wire width 2 $5\src31__data_o$next[1:0]$10514 + attribute \src "libresoc.v:165332.3-165367.6" + wire $5\wr_detect$10[0:0]$10539 + attribute \src "libresoc.v:165168.3-165203.6" + wire $5\wr_detect$4[0:0]$10507 + attribute \src "libresoc.v:165250.3-165285.6" + wire $5\wr_detect$7[0:0]$10523 + attribute \src "libresoc.v:165086.3-165121.6" + wire $5\wr_detect[0:0] + attribute \src "libresoc.v:165286.3-165331.6" + wire width 2 $6\r1__data_o$next[1:0]$10531 + attribute \src "libresoc.v:165040.3-165085.6" + wire width 2 $6\src11__data_o$next[1:0]$10489 + attribute \src "libresoc.v:165122.3-165167.6" + wire width 2 $6\src21__data_o$next[1:0]$10499 + attribute \src "libresoc.v:165204.3-165249.6" + wire width 2 $6\src31__data_o$next[1:0]$10515 + attribute \src "libresoc.v:165286.3-165331.6" + wire width 2 $7\r1__data_o$next[1:0]$10532 + attribute \src "libresoc.v:165040.3-165085.6" + wire width 2 $7\src11__data_o$next[1:0]$10490 + attribute \src "libresoc.v:165122.3-165167.6" + wire width 2 $7\src21__data_o$next[1:0]$10500 + attribute \src "libresoc.v:165204.3-165249.6" + wire width 2 $7\src31__data_o$next[1:0]$10516 + attribute \src "libresoc.v:165026.17-165026.104" + wire $not$libresoc.v:165026$10473_Y + attribute \src "libresoc.v:165027.17-165027.100" + wire $not$libresoc.v:165027$10474_Y + attribute \src "libresoc.v:165028.17-165028.103" + wire $not$libresoc.v:165028$10475_Y + attribute \src "libresoc.v:165029.17-165029.103" + wire $not$libresoc.v:165029$10476_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 18 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 input 9 \dest11__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 8 \dest11__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 input 11 \dest21__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 10 \dest21__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 input 13 \dest31__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 12 \dest31__wen + attribute \src "libresoc.v:164957.7-164957.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 output 14 \r1__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 \r1__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 15 \r1__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 2 \reg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 2 \reg$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 output 3 \src11__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 \src11__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 2 \src11__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 output 5 \src21__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 \src21__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 4 \src21__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 output 7 \src31__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 \src31__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 6 \src31__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 input 16 \w1__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 17 \w1__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:165026$10473 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$10 + connect \Y $not$libresoc.v:165026$10473_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:165027$10474 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect + connect \Y $not$libresoc.v:165027$10474_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:165028$10475 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$4 + connect \Y $not$libresoc.v:165028$10475_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:165029$10476 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$7 + connect \Y $not$libresoc.v:165029$10476_Y + end + attribute \src "libresoc.v:164957.7-164957.20" + process $proc$libresoc.v:164957$10547 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:164984.13-164984.30" + process $proc$libresoc.v:164984$10548 + assign { } { } + assign $1\r1__data_o[1:0] 2'00 + sync always + sync init + update \r1__data_o $1\r1__data_o[1:0] + end + attribute \src "libresoc.v:164990.13-164990.25" + process $proc$libresoc.v:164990$10549 + assign { } { } + assign $1\reg[1:0] 2'00 + sync always + sync init + update \reg $1\reg[1:0] + end + attribute \src "libresoc.v:164995.13-164995.33" + process $proc$libresoc.v:164995$10550 + assign { } { } + assign $1\src11__data_o[1:0] 2'00 + sync always + sync init + update \src11__data_o $1\src11__data_o[1:0] + end + attribute \src "libresoc.v:165002.13-165002.33" + process $proc$libresoc.v:165002$10551 + assign { } { } + assign $1\src21__data_o[1:0] 2'00 + sync always + sync init + update \src21__data_o $1\src21__data_o[1:0] + end + attribute \src "libresoc.v:165009.13-165009.33" + process $proc$libresoc.v:165009$10552 + assign { } { } + assign $1\src31__data_o[1:0] 2'00 + sync always + sync init + update \src31__data_o $1\src31__data_o[1:0] + end + attribute \src "libresoc.v:165030.3-165031.25" + process $proc$libresoc.v:165030$10477 + assign { } { } + assign $0\reg[1:0] \reg$next + sync posedge \coresync_clk + update \reg $0\reg[1:0] + end + attribute \src "libresoc.v:165032.3-165033.37" + process $proc$libresoc.v:165032$10478 + assign { } { } + assign $0\r1__data_o[1:0] \r1__data_o$next + sync posedge \coresync_clk + update \r1__data_o $0\r1__data_o[1:0] + end + attribute \src "libresoc.v:165034.3-165035.43" + process $proc$libresoc.v:165034$10479 + assign { } { } + assign $0\src31__data_o[1:0] \src31__data_o$next + sync posedge \coresync_clk + update \src31__data_o $0\src31__data_o[1:0] + end + attribute \src "libresoc.v:165036.3-165037.43" + process $proc$libresoc.v:165036$10480 + assign { } { } + assign $0\src21__data_o[1:0] \src21__data_o$next + sync posedge \coresync_clk + update \src21__data_o $0\src21__data_o[1:0] + end + attribute \src "libresoc.v:165038.3-165039.43" + process $proc$libresoc.v:165038$10481 + assign { } { } + assign $0\src11__data_o[1:0] \src11__data_o$next + sync posedge \coresync_clk + update \src11__data_o $0\src11__data_o[1:0] + end + attribute \src "libresoc.v:165040.3-165085.6" + process $proc$libresoc.v:165040$10482 + assign { } { } + assign { } { } + assign { } { } + assign $0\src11__data_o$next[1:0]$10483 $7\src11__data_o$next[1:0]$10490 + attribute \src "libresoc.v:165041.5-165041.29" + switch \initial + attribute \src "libresoc.v:165041.9-165041.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src11__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src11__data_o$next[1:0]$10484 $6\src11__data_o$next[1:0]$10489 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest11__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src11__data_o$next[1:0]$10485 \dest11__data_i + case + assign $2\src11__data_o$next[1:0]$10485 2'00 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest21__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src11__data_o$next[1:0]$10486 \dest21__data_i + case + assign $3\src11__data_o$next[1:0]$10486 $2\src11__data_o$next[1:0]$10485 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest31__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src11__data_o$next[1:0]$10487 \dest31__data_i + case + assign $4\src11__data_o$next[1:0]$10487 $3\src11__data_o$next[1:0]$10486 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src11__data_o$next[1:0]$10488 \w1__data_i + case + assign $5\src11__data_o$next[1:0]$10488 $4\src11__data_o$next[1:0]$10487 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src11__data_o$next[1:0]$10489 \reg + case + assign $6\src11__data_o$next[1:0]$10489 $5\src11__data_o$next[1:0]$10488 + end + case + assign $1\src11__data_o$next[1:0]$10484 2'00 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\src11__data_o$next[1:0]$10490 2'00 + case + assign $7\src11__data_o$next[1:0]$10490 $1\src11__data_o$next[1:0]$10484 + end + sync always + update \src11__data_o$next $0\src11__data_o$next[1:0]$10483 + end + attribute \src "libresoc.v:165086.3-165121.6" + process $proc$libresoc.v:165086$10491 + assign { } { } + assign { } { } + assign $0\wr_detect[0:0] $1\wr_detect[0:0] + attribute \src "libresoc.v:165087.5-165087.29" + switch \initial + attribute \src "libresoc.v:165087.9-165087.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src11__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect[0:0] $5\wr_detect[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest11__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect[0:0] 1'1 + case + assign $2\wr_detect[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest21__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect[0:0] 1'1 + case + assign $3\wr_detect[0:0] $2\wr_detect[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest31__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect[0:0] 1'1 + case + assign $4\wr_detect[0:0] $3\wr_detect[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\wr_detect[0:0] 1'1 + case + assign $5\wr_detect[0:0] $4\wr_detect[0:0] + end + case + assign $1\wr_detect[0:0] 1'0 + end + sync always + update \wr_detect $0\wr_detect[0:0] + end + attribute \src "libresoc.v:165122.3-165167.6" + process $proc$libresoc.v:165122$10492 + assign { } { } + assign { } { } + assign { } { } + assign $0\src21__data_o$next[1:0]$10493 $7\src21__data_o$next[1:0]$10500 + attribute \src "libresoc.v:165123.5-165123.29" + switch \initial + attribute \src "libresoc.v:165123.9-165123.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src21__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src21__data_o$next[1:0]$10494 $6\src21__data_o$next[1:0]$10499 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest11__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src21__data_o$next[1:0]$10495 \dest11__data_i + case + assign $2\src21__data_o$next[1:0]$10495 2'00 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest21__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src21__data_o$next[1:0]$10496 \dest21__data_i + case + assign $3\src21__data_o$next[1:0]$10496 $2\src21__data_o$next[1:0]$10495 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest31__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src21__data_o$next[1:0]$10497 \dest31__data_i + case + assign $4\src21__data_o$next[1:0]$10497 $3\src21__data_o$next[1:0]$10496 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src21__data_o$next[1:0]$10498 \w1__data_i + case + assign $5\src21__data_o$next[1:0]$10498 $4\src21__data_o$next[1:0]$10497 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src21__data_o$next[1:0]$10499 \reg + case + assign $6\src21__data_o$next[1:0]$10499 $5\src21__data_o$next[1:0]$10498 + end + case + assign $1\src21__data_o$next[1:0]$10494 2'00 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\src21__data_o$next[1:0]$10500 2'00 + case + assign $7\src21__data_o$next[1:0]$10500 $1\src21__data_o$next[1:0]$10494 + end + sync always + update \src21__data_o$next $0\src21__data_o$next[1:0]$10493 + end + attribute \src "libresoc.v:165168.3-165203.6" + process $proc$libresoc.v:165168$10501 + assign { } { } + assign { } { } + assign $0\wr_detect$4[0:0]$10502 $1\wr_detect$4[0:0]$10503 + attribute \src "libresoc.v:165169.5-165169.29" + switch \initial + attribute \src "libresoc.v:165169.9-165169.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src21__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$4[0:0]$10503 $5\wr_detect$4[0:0]$10507 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest11__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$4[0:0]$10504 1'1 + case + assign $2\wr_detect$4[0:0]$10504 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest21__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$4[0:0]$10505 1'1 + case + assign $3\wr_detect$4[0:0]$10505 $2\wr_detect$4[0:0]$10504 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest31__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$4[0:0]$10506 1'1 + case + assign $4\wr_detect$4[0:0]$10506 $3\wr_detect$4[0:0]$10505 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\wr_detect$4[0:0]$10507 1'1 + case + assign $5\wr_detect$4[0:0]$10507 $4\wr_detect$4[0:0]$10506 + end + case + assign $1\wr_detect$4[0:0]$10503 1'0 + end + sync always + update \wr_detect$4 $0\wr_detect$4[0:0]$10502 + end + attribute \src "libresoc.v:165204.3-165249.6" + process $proc$libresoc.v:165204$10508 + assign { } { } + assign { } { } + assign { } { } + assign $0\src31__data_o$next[1:0]$10509 $7\src31__data_o$next[1:0]$10516 + attribute \src "libresoc.v:165205.5-165205.29" + switch \initial + attribute \src "libresoc.v:165205.9-165205.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src31__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src31__data_o$next[1:0]$10510 $6\src31__data_o$next[1:0]$10515 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest11__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src31__data_o$next[1:0]$10511 \dest11__data_i + case + assign $2\src31__data_o$next[1:0]$10511 2'00 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest21__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src31__data_o$next[1:0]$10512 \dest21__data_i + case + assign $3\src31__data_o$next[1:0]$10512 $2\src31__data_o$next[1:0]$10511 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest31__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src31__data_o$next[1:0]$10513 \dest31__data_i + case + assign $4\src31__data_o$next[1:0]$10513 $3\src31__data_o$next[1:0]$10512 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src31__data_o$next[1:0]$10514 \w1__data_i + case + assign $5\src31__data_o$next[1:0]$10514 $4\src31__data_o$next[1:0]$10513 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$6 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src31__data_o$next[1:0]$10515 \reg + case + assign $6\src31__data_o$next[1:0]$10515 $5\src31__data_o$next[1:0]$10514 + end + case + assign $1\src31__data_o$next[1:0]$10510 2'00 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\src31__data_o$next[1:0]$10516 2'00 + case + assign $7\src31__data_o$next[1:0]$10516 $1\src31__data_o$next[1:0]$10510 + end + sync always + update \src31__data_o$next $0\src31__data_o$next[1:0]$10509 + end + attribute \src "libresoc.v:165250.3-165285.6" + process $proc$libresoc.v:165250$10517 + assign { } { } + assign { } { } + assign $0\wr_detect$7[0:0]$10518 $1\wr_detect$7[0:0]$10519 + attribute \src "libresoc.v:165251.5-165251.29" + switch \initial + attribute \src "libresoc.v:165251.9-165251.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src31__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$7[0:0]$10519 $5\wr_detect$7[0:0]$10523 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest11__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$7[0:0]$10520 1'1 + case + assign $2\wr_detect$7[0:0]$10520 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest21__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$7[0:0]$10521 1'1 + case + assign $3\wr_detect$7[0:0]$10521 $2\wr_detect$7[0:0]$10520 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest31__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$7[0:0]$10522 1'1 + case + assign $4\wr_detect$7[0:0]$10522 $3\wr_detect$7[0:0]$10521 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\wr_detect$7[0:0]$10523 1'1 + case + assign $5\wr_detect$7[0:0]$10523 $4\wr_detect$7[0:0]$10522 + end + case + assign $1\wr_detect$7[0:0]$10519 1'0 + end + sync always + update \wr_detect$7 $0\wr_detect$7[0:0]$10518 + end + attribute \src "libresoc.v:165286.3-165331.6" + process $proc$libresoc.v:165286$10524 + assign { } { } + assign { } { } + assign { } { } + assign $0\r1__data_o$next[1:0]$10525 $7\r1__data_o$next[1:0]$10532 + attribute \src "libresoc.v:165287.5-165287.29" + switch \initial + attribute \src "libresoc.v:165287.9-165287.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r1__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\r1__data_o$next[1:0]$10526 $6\r1__data_o$next[1:0]$10531 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest11__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r1__data_o$next[1:0]$10527 \dest11__data_i + case + assign $2\r1__data_o$next[1:0]$10527 2'00 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest21__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\r1__data_o$next[1:0]$10528 \dest21__data_i + case + assign $3\r1__data_o$next[1:0]$10528 $2\r1__data_o$next[1:0]$10527 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest31__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\r1__data_o$next[1:0]$10529 \dest31__data_i + case + assign $4\r1__data_o$next[1:0]$10529 $3\r1__data_o$next[1:0]$10528 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\r1__data_o$next[1:0]$10530 \w1__data_i + case + assign $5\r1__data_o$next[1:0]$10530 $4\r1__data_o$next[1:0]$10529 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$9 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\r1__data_o$next[1:0]$10531 \reg + case + assign $6\r1__data_o$next[1:0]$10531 $5\r1__data_o$next[1:0]$10530 + end + case + assign $1\r1__data_o$next[1:0]$10526 2'00 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\r1__data_o$next[1:0]$10532 2'00 + case + assign $7\r1__data_o$next[1:0]$10532 $1\r1__data_o$next[1:0]$10526 + end + sync always + update \r1__data_o$next $0\r1__data_o$next[1:0]$10525 + end + attribute \src "libresoc.v:165332.3-165367.6" + process $proc$libresoc.v:165332$10533 + assign { } { } + assign { } { } + assign $0\wr_detect$10[0:0]$10534 $1\wr_detect$10[0:0]$10535 + attribute \src "libresoc.v:165333.5-165333.29" + switch \initial + attribute \src "libresoc.v:165333.9-165333.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r1__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$10[0:0]$10535 $5\wr_detect$10[0:0]$10539 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest11__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$10[0:0]$10536 1'1 + case + assign $2\wr_detect$10[0:0]$10536 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest21__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$10[0:0]$10537 1'1 + case + assign $3\wr_detect$10[0:0]$10537 $2\wr_detect$10[0:0]$10536 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest31__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$10[0:0]$10538 1'1 + case + assign $4\wr_detect$10[0:0]$10538 $3\wr_detect$10[0:0]$10537 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\wr_detect$10[0:0]$10539 1'1 + case + assign $5\wr_detect$10[0:0]$10539 $4\wr_detect$10[0:0]$10538 + end + case + assign $1\wr_detect$10[0:0]$10535 1'0 + end + sync always + update \wr_detect$10 $0\wr_detect$10[0:0]$10534 + end + attribute \src "libresoc.v:165368.3-165400.6" + process $proc$libresoc.v:165368$10540 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\reg$next[1:0]$10541 $5\reg$next[1:0]$10546 + attribute \src "libresoc.v:165369.5-165369.29" + switch \initial + attribute \src "libresoc.v:165369.9-165369.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest11__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\reg$next[1:0]$10542 \dest11__data_i + case + assign $1\reg$next[1:0]$10542 \reg + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest21__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\reg$next[1:0]$10543 \dest21__data_i + case + assign $2\reg$next[1:0]$10543 $1\reg$next[1:0]$10542 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest31__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\reg$next[1:0]$10544 \dest31__data_i + case + assign $3\reg$next[1:0]$10544 $2\reg$next[1:0]$10543 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \w1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\reg$next[1:0]$10545 \w1__data_i + case + assign $4\reg$next[1:0]$10545 $3\reg$next[1:0]$10544 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\reg$next[1:0]$10546 2'00 + case + assign $5\reg$next[1:0]$10546 $4\reg$next[1:0]$10545 + end + sync always + update \reg$next $0\reg$next[1:0]$10541 + end + connect \$9 $not$libresoc.v:165026$10473_Y + connect \$1 $not$libresoc.v:165027$10474_Y + connect \$3 $not$libresoc.v:165028$10475_Y + connect \$6 $not$libresoc.v:165029$10476_Y +end +attribute \src "libresoc.v:165405.1-165624.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.state.reg_1" +attribute \generator "nMigen" +module \reg_1$133 + attribute \src "libresoc.v:165457.3-165496.6" + wire width 64 $0\cia1__data_o$next[63:0]$10559 + attribute \src "libresoc.v:165455.3-165456.41" + wire width 64 $0\cia1__data_o[63:0] + attribute \src "libresoc.v:165406.7-165406.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:165527.3-165566.6" + wire width 64 $0\msr1__data_o$next[63:0]$10568 + attribute \src "libresoc.v:165453.3-165454.41" + wire width 64 $0\msr1__data_o[63:0] + attribute \src "libresoc.v:165597.3-165623.6" + wire width 64 $0\reg$next[63:0]$10582 + attribute \src "libresoc.v:165451.3-165452.25" + wire width 64 $0\reg[63:0] + attribute \src "libresoc.v:165567.3-165596.6" + wire $0\wr_detect$4[0:0]$10576 + attribute \src "libresoc.v:165497.3-165526.6" + wire $0\wr_detect[0:0] + attribute \src "libresoc.v:165457.3-165496.6" + wire width 64 $1\cia1__data_o$next[63:0]$10560 + attribute \src "libresoc.v:165413.14-165413.49" + wire width 64 $1\cia1__data_o[63:0] + attribute \src "libresoc.v:165527.3-165566.6" + wire width 64 $1\msr1__data_o$next[63:0]$10569 + attribute \src "libresoc.v:165430.14-165430.49" + wire width 64 $1\msr1__data_o[63:0] + attribute \src "libresoc.v:165597.3-165623.6" + wire width 64 $1\reg$next[63:0]$10583 + attribute \src "libresoc.v:165442.14-165442.42" + wire width 64 $1\reg[63:0] + attribute \src "libresoc.v:165567.3-165596.6" + wire $1\wr_detect$4[0:0]$10577 + attribute \src "libresoc.v:165497.3-165526.6" + wire $1\wr_detect[0:0] + attribute \src "libresoc.v:165457.3-165496.6" + wire width 64 $2\cia1__data_o$next[63:0]$10561 + attribute \src "libresoc.v:165527.3-165566.6" + wire width 64 $2\msr1__data_o$next[63:0]$10570 + attribute \src "libresoc.v:165597.3-165623.6" + wire width 64 $2\reg$next[63:0]$10584 + attribute \src "libresoc.v:165567.3-165596.6" + wire $2\wr_detect$4[0:0]$10578 + attribute \src "libresoc.v:165497.3-165526.6" + wire $2\wr_detect[0:0] + attribute \src "libresoc.v:165457.3-165496.6" + wire width 64 $3\cia1__data_o$next[63:0]$10562 + attribute \src "libresoc.v:165527.3-165566.6" + wire width 64 $3\msr1__data_o$next[63:0]$10571 + attribute \src "libresoc.v:165597.3-165623.6" + wire width 64 $3\reg$next[63:0]$10585 + attribute \src "libresoc.v:165567.3-165596.6" + wire $3\wr_detect$4[0:0]$10579 + attribute \src "libresoc.v:165497.3-165526.6" + wire $3\wr_detect[0:0] + attribute \src "libresoc.v:165457.3-165496.6" + wire width 64 $4\cia1__data_o$next[63:0]$10563 + attribute \src "libresoc.v:165527.3-165566.6" + wire width 64 $4\msr1__data_o$next[63:0]$10572 + attribute \src "libresoc.v:165597.3-165623.6" + wire width 64 $4\reg$next[63:0]$10586 + attribute \src "libresoc.v:165567.3-165596.6" + wire $4\wr_detect$4[0:0]$10580 + attribute \src "libresoc.v:165497.3-165526.6" + wire $4\wr_detect[0:0] + attribute \src "libresoc.v:165457.3-165496.6" + wire width 64 $5\cia1__data_o$next[63:0]$10564 + attribute \src "libresoc.v:165527.3-165566.6" + wire width 64 $5\msr1__data_o$next[63:0]$10573 + attribute \src "libresoc.v:165457.3-165496.6" + wire width 64 $6\cia1__data_o$next[63:0]$10565 + attribute \src "libresoc.v:165527.3-165566.6" + wire width 64 $6\msr1__data_o$next[63:0]$10574 + attribute \src "libresoc.v:165449.17-165449.100" + wire $not$libresoc.v:165449$10553_Y + attribute \src "libresoc.v:165450.17-165450.103" + wire $not$libresoc.v:165450$10554_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 output 3 \cia1__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \cia1__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 2 \cia1__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 12 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 input 11 \d_wr11__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 10 \d_wr11__wen + attribute \src "libresoc.v:165406.7-165406.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 input 9 \msr1__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 output 5 \msr1__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \msr1__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 4 \msr1__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 8 \msr1__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 input 7 \nia1__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 6 \nia1__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 64 \reg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 64 \reg$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:165449$10553 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect + connect \Y $not$libresoc.v:165449$10553_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:165450$10554 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$4 + connect \Y $not$libresoc.v:165450$10554_Y + end + attribute \src "libresoc.v:165406.7-165406.20" + process $proc$libresoc.v:165406$10587 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:165413.14-165413.49" + process $proc$libresoc.v:165413$10588 + assign { } { } + assign $1\cia1__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \cia1__data_o $1\cia1__data_o[63:0] + end + attribute \src "libresoc.v:165430.14-165430.49" + process $proc$libresoc.v:165430$10589 + assign { } { } + assign $1\msr1__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \msr1__data_o $1\msr1__data_o[63:0] + end + attribute \src "libresoc.v:165442.14-165442.42" + process $proc$libresoc.v:165442$10590 + assign { } { } + assign $1\reg[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \reg $1\reg[63:0] + end + attribute \src "libresoc.v:165451.3-165452.25" + process $proc$libresoc.v:165451$10555 + assign { } { } + assign $0\reg[63:0] \reg$next + sync posedge \coresync_clk + update \reg $0\reg[63:0] + end + attribute \src "libresoc.v:165453.3-165454.41" + process $proc$libresoc.v:165453$10556 + assign { } { } + assign $0\msr1__data_o[63:0] \msr1__data_o$next + sync posedge \coresync_clk + update \msr1__data_o $0\msr1__data_o[63:0] + end + attribute \src "libresoc.v:165455.3-165456.41" + process $proc$libresoc.v:165455$10557 + assign { } { } + assign $0\cia1__data_o[63:0] \cia1__data_o$next + sync posedge \coresync_clk + update \cia1__data_o $0\cia1__data_o[63:0] + end + attribute \src "libresoc.v:165457.3-165496.6" + process $proc$libresoc.v:165457$10558 + assign { } { } + assign { } { } + assign { } { } + assign $0\cia1__data_o$next[63:0]$10559 $6\cia1__data_o$next[63:0]$10565 + attribute \src "libresoc.v:165458.5-165458.29" + switch \initial + attribute \src "libresoc.v:165458.9-165458.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \cia1__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\cia1__data_o$next[63:0]$10560 $5\cia1__data_o$next[63:0]$10564 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \nia1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cia1__data_o$next[63:0]$10561 \nia1__data_i + case + assign $2\cia1__data_o$next[63:0]$10561 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \msr1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\cia1__data_o$next[63:0]$10562 \msr1__data_i + case + assign $3\cia1__data_o$next[63:0]$10562 $2\cia1__data_o$next[63:0]$10561 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \d_wr11__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\cia1__data_o$next[63:0]$10563 \d_wr11__data_i + case + assign $4\cia1__data_o$next[63:0]$10563 $3\cia1__data_o$next[63:0]$10562 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\cia1__data_o$next[63:0]$10564 \reg + case + assign $5\cia1__data_o$next[63:0]$10564 $4\cia1__data_o$next[63:0]$10563 + end + case + assign $1\cia1__data_o$next[63:0]$10560 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\cia1__data_o$next[63:0]$10565 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $6\cia1__data_o$next[63:0]$10565 $1\cia1__data_o$next[63:0]$10560 + end + sync always + update \cia1__data_o$next $0\cia1__data_o$next[63:0]$10559 + end + attribute \src "libresoc.v:165497.3-165526.6" + process $proc$libresoc.v:165497$10566 + assign { } { } + assign { } { } + assign $0\wr_detect[0:0] $1\wr_detect[0:0] + attribute \src "libresoc.v:165498.5-165498.29" + switch \initial + attribute \src "libresoc.v:165498.9-165498.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \cia1__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect[0:0] $4\wr_detect[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \nia1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect[0:0] 1'1 + case + assign $2\wr_detect[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \msr1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect[0:0] 1'1 + case + assign $3\wr_detect[0:0] $2\wr_detect[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \d_wr11__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect[0:0] 1'1 + case + assign $4\wr_detect[0:0] $3\wr_detect[0:0] + end + case + assign $1\wr_detect[0:0] 1'0 + end + sync always + update \wr_detect $0\wr_detect[0:0] + end + attribute \src "libresoc.v:165527.3-165566.6" + process $proc$libresoc.v:165527$10567 + assign { } { } + assign { } { } + assign { } { } + assign $0\msr1__data_o$next[63:0]$10568 $6\msr1__data_o$next[63:0]$10574 + attribute \src "libresoc.v:165528.5-165528.29" + switch \initial + attribute \src "libresoc.v:165528.9-165528.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \msr1__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\msr1__data_o$next[63:0]$10569 $5\msr1__data_o$next[63:0]$10573 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \nia1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\msr1__data_o$next[63:0]$10570 \nia1__data_i + case + assign $2\msr1__data_o$next[63:0]$10570 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \msr1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\msr1__data_o$next[63:0]$10571 \msr1__data_i + case + assign $3\msr1__data_o$next[63:0]$10571 $2\msr1__data_o$next[63:0]$10570 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \d_wr11__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\msr1__data_o$next[63:0]$10572 \d_wr11__data_i + case + assign $4\msr1__data_o$next[63:0]$10572 $3\msr1__data_o$next[63:0]$10571 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\msr1__data_o$next[63:0]$10573 \reg + case + assign $5\msr1__data_o$next[63:0]$10573 $4\msr1__data_o$next[63:0]$10572 + end + case + assign $1\msr1__data_o$next[63:0]$10569 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\msr1__data_o$next[63:0]$10574 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $6\msr1__data_o$next[63:0]$10574 $1\msr1__data_o$next[63:0]$10569 + end + sync always + update \msr1__data_o$next $0\msr1__data_o$next[63:0]$10568 + end + attribute \src "libresoc.v:165567.3-165596.6" + process $proc$libresoc.v:165567$10575 + assign { } { } + assign { } { } + assign $0\wr_detect$4[0:0]$10576 $1\wr_detect$4[0:0]$10577 + attribute \src "libresoc.v:165568.5-165568.29" + switch \initial + attribute \src "libresoc.v:165568.9-165568.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \msr1__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$4[0:0]$10577 $4\wr_detect$4[0:0]$10580 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \nia1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$4[0:0]$10578 1'1 + case + assign $2\wr_detect$4[0:0]$10578 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \msr1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$4[0:0]$10579 1'1 + case + assign $3\wr_detect$4[0:0]$10579 $2\wr_detect$4[0:0]$10578 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \d_wr11__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$4[0:0]$10580 1'1 + case + assign $4\wr_detect$4[0:0]$10580 $3\wr_detect$4[0:0]$10579 + end + case + assign $1\wr_detect$4[0:0]$10577 1'0 + end + sync always + update \wr_detect$4 $0\wr_detect$4[0:0]$10576 + end + attribute \src "libresoc.v:165597.3-165623.6" + process $proc$libresoc.v:165597$10581 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\reg$next[63:0]$10582 $4\reg$next[63:0]$10586 + attribute \src "libresoc.v:165598.5-165598.29" + switch \initial + attribute \src "libresoc.v:165598.9-165598.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \nia1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\reg$next[63:0]$10583 \nia1__data_i + case + assign $1\reg$next[63:0]$10583 \reg + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \msr1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\reg$next[63:0]$10584 \msr1__data_i + case + assign $2\reg$next[63:0]$10584 $1\reg$next[63:0]$10583 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \d_wr11__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\reg$next[63:0]$10585 \d_wr11__data_i + case + assign $3\reg$next[63:0]$10585 $2\reg$next[63:0]$10584 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\reg$next[63:0]$10586 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $4\reg$next[63:0]$10586 $3\reg$next[63:0]$10585 + end + sync always + update \reg$next $0\reg$next[63:0]$10582 + end + connect \$1 $not$libresoc.v:165449$10553_Y + connect \$3 $not$libresoc.v:165450$10554_Y +end +attribute \src "libresoc.v:165628.1-166099.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.cr.reg_2" +attribute \generator "nMigen" +module \reg_2 + attribute \src "libresoc.v:165629.7-165629.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:166029.3-166068.6" + wire width 4 $0\r22__data_o$next[3:0]$10660 + attribute \src "libresoc.v:165712.3-165713.39" + wire width 4 $0\r22__data_o[3:0] + attribute \src "libresoc.v:165959.3-165998.6" + wire width 4 $0\r2__data_o$next[3:0]$10646 + attribute \src "libresoc.v:165714.3-165715.37" + wire width 4 $0\r2__data_o[3:0] + attribute \src "libresoc.v:165792.3-165818.6" + wire width 4 $0\reg$next[3:0]$10612 + attribute \src "libresoc.v:165710.3-165711.25" + wire width 4 $0\reg[3:0] + attribute \src "libresoc.v:165722.3-165761.6" + wire width 4 $0\src12__data_o$next[3:0]$10603 + attribute \src "libresoc.v:165720.3-165721.43" + wire width 4 $0\src12__data_o[3:0] + attribute \src "libresoc.v:165819.3-165858.6" + wire width 4 $0\src22__data_o$next[3:0]$10618 + attribute \src "libresoc.v:165718.3-165719.43" + wire width 4 $0\src22__data_o[3:0] + attribute \src "libresoc.v:165889.3-165928.6" + wire width 4 $0\src32__data_o$next[3:0]$10632 + attribute \src "libresoc.v:165716.3-165717.43" + wire width 4 $0\src32__data_o[3:0] + attribute \src "libresoc.v:165999.3-166028.6" + wire $0\wr_detect$10[0:0]$10654 + attribute \src "libresoc.v:166069.3-166098.6" + wire $0\wr_detect$13[0:0]$10668 + attribute \src "libresoc.v:165859.3-165888.6" + wire $0\wr_detect$4[0:0]$10626 + attribute \src "libresoc.v:165929.3-165958.6" + wire $0\wr_detect$7[0:0]$10640 + attribute \src "libresoc.v:165762.3-165791.6" + wire $0\wr_detect[0:0] + attribute \src "libresoc.v:166029.3-166068.6" + wire width 4 $1\r22__data_o$next[3:0]$10661 + attribute \src "libresoc.v:165654.13-165654.31" + wire width 4 $1\r22__data_o[3:0] + attribute \src "libresoc.v:165959.3-165998.6" + wire width 4 $1\r2__data_o$next[3:0]$10647 + attribute \src "libresoc.v:165661.13-165661.30" + wire width 4 $1\r2__data_o[3:0] + attribute \src "libresoc.v:165792.3-165818.6" + wire width 4 $1\reg$next[3:0]$10613 + attribute \src "libresoc.v:165667.13-165667.25" + wire width 4 $1\reg[3:0] + attribute \src "libresoc.v:165722.3-165761.6" + wire width 4 $1\src12__data_o$next[3:0]$10604 + attribute \src "libresoc.v:165672.13-165672.33" + wire width 4 $1\src12__data_o[3:0] + attribute \src "libresoc.v:165819.3-165858.6" + wire width 4 $1\src22__data_o$next[3:0]$10619 + attribute \src "libresoc.v:165679.13-165679.33" + wire width 4 $1\src22__data_o[3:0] + attribute \src "libresoc.v:165889.3-165928.6" + wire width 4 $1\src32__data_o$next[3:0]$10633 + attribute \src "libresoc.v:165686.13-165686.33" + wire width 4 $1\src32__data_o[3:0] + attribute \src "libresoc.v:165999.3-166028.6" + wire $1\wr_detect$10[0:0]$10655 + attribute \src "libresoc.v:166069.3-166098.6" + wire $1\wr_detect$13[0:0]$10669 + attribute \src "libresoc.v:165859.3-165888.6" + wire $1\wr_detect$4[0:0]$10627 + attribute \src "libresoc.v:165929.3-165958.6" + wire $1\wr_detect$7[0:0]$10641 + attribute \src "libresoc.v:165762.3-165791.6" + wire $1\wr_detect[0:0] + attribute \src "libresoc.v:166029.3-166068.6" + wire width 4 $2\r22__data_o$next[3:0]$10662 + attribute \src "libresoc.v:165959.3-165998.6" + wire width 4 $2\r2__data_o$next[3:0]$10648 + attribute \src "libresoc.v:165792.3-165818.6" + wire width 4 $2\reg$next[3:0]$10614 + attribute \src "libresoc.v:165722.3-165761.6" + wire width 4 $2\src12__data_o$next[3:0]$10605 + attribute \src "libresoc.v:165819.3-165858.6" + wire width 4 $2\src22__data_o$next[3:0]$10620 + attribute \src "libresoc.v:165889.3-165928.6" + wire width 4 $2\src32__data_o$next[3:0]$10634 + attribute \src "libresoc.v:165999.3-166028.6" + wire $2\wr_detect$10[0:0]$10656 + attribute \src "libresoc.v:166069.3-166098.6" + wire $2\wr_detect$13[0:0]$10670 + attribute \src "libresoc.v:165859.3-165888.6" + wire $2\wr_detect$4[0:0]$10628 + attribute \src "libresoc.v:165929.3-165958.6" + wire $2\wr_detect$7[0:0]$10642 + attribute \src "libresoc.v:165762.3-165791.6" + wire $2\wr_detect[0:0] + attribute \src "libresoc.v:166029.3-166068.6" + wire width 4 $3\r22__data_o$next[3:0]$10663 + attribute \src "libresoc.v:165959.3-165998.6" + wire width 4 $3\r2__data_o$next[3:0]$10649 + attribute \src "libresoc.v:165792.3-165818.6" + wire width 4 $3\reg$next[3:0]$10615 + attribute \src "libresoc.v:165722.3-165761.6" + wire width 4 $3\src12__data_o$next[3:0]$10606 + attribute \src "libresoc.v:165819.3-165858.6" + wire width 4 $3\src22__data_o$next[3:0]$10621 + attribute \src "libresoc.v:165889.3-165928.6" + wire width 4 $3\src32__data_o$next[3:0]$10635 + attribute \src "libresoc.v:165999.3-166028.6" + wire $3\wr_detect$10[0:0]$10657 + attribute \src "libresoc.v:166069.3-166098.6" + wire $3\wr_detect$13[0:0]$10671 + attribute \src "libresoc.v:165859.3-165888.6" + wire $3\wr_detect$4[0:0]$10629 + attribute \src "libresoc.v:165929.3-165958.6" + wire $3\wr_detect$7[0:0]$10643 + attribute \src "libresoc.v:165762.3-165791.6" + wire $3\wr_detect[0:0] + attribute \src "libresoc.v:166029.3-166068.6" + wire width 4 $4\r22__data_o$next[3:0]$10664 + attribute \src "libresoc.v:165959.3-165998.6" + wire width 4 $4\r2__data_o$next[3:0]$10650 + attribute \src "libresoc.v:165792.3-165818.6" + wire width 4 $4\reg$next[3:0]$10616 + attribute \src "libresoc.v:165722.3-165761.6" + wire width 4 $4\src12__data_o$next[3:0]$10607 + attribute \src "libresoc.v:165819.3-165858.6" + wire width 4 $4\src22__data_o$next[3:0]$10622 + attribute \src "libresoc.v:165889.3-165928.6" + wire width 4 $4\src32__data_o$next[3:0]$10636 + attribute \src "libresoc.v:165999.3-166028.6" + wire $4\wr_detect$10[0:0]$10658 + attribute \src "libresoc.v:166069.3-166098.6" + wire $4\wr_detect$13[0:0]$10672 + attribute \src "libresoc.v:165859.3-165888.6" + wire $4\wr_detect$4[0:0]$10630 + attribute \src "libresoc.v:165929.3-165958.6" + wire $4\wr_detect$7[0:0]$10644 + attribute \src "libresoc.v:165762.3-165791.6" + wire $4\wr_detect[0:0] + attribute \src "libresoc.v:166029.3-166068.6" + wire width 4 $5\r22__data_o$next[3:0]$10665 + attribute \src "libresoc.v:165959.3-165998.6" + wire width 4 $5\r2__data_o$next[3:0]$10651 + attribute \src "libresoc.v:165722.3-165761.6" + wire width 4 $5\src12__data_o$next[3:0]$10608 + attribute \src "libresoc.v:165819.3-165858.6" + wire width 4 $5\src22__data_o$next[3:0]$10623 + attribute \src "libresoc.v:165889.3-165928.6" + wire width 4 $5\src32__data_o$next[3:0]$10637 + attribute \src "libresoc.v:166029.3-166068.6" + wire width 4 $6\r22__data_o$next[3:0]$10666 + attribute \src "libresoc.v:165959.3-165998.6" + wire width 4 $6\r2__data_o$next[3:0]$10652 + attribute \src "libresoc.v:165722.3-165761.6" + wire width 4 $6\src12__data_o$next[3:0]$10609 + attribute \src "libresoc.v:165819.3-165858.6" + wire width 4 $6\src22__data_o$next[3:0]$10624 + attribute \src "libresoc.v:165889.3-165928.6" + wire width 4 $6\src32__data_o$next[3:0]$10638 + attribute \src "libresoc.v:165705.17-165705.104" + wire $not$libresoc.v:165705$10591_Y + attribute \src "libresoc.v:165706.18-165706.105" + wire $not$libresoc.v:165706$10592_Y + attribute \src "libresoc.v:165707.17-165707.100" + wire $not$libresoc.v:165707$10593_Y + attribute \src "libresoc.v:165708.17-165708.103" + wire $not$libresoc.v:165708$10594_Y + attribute \src "libresoc.v:165709.17-165709.103" + wire $not$libresoc.v:165709$10595_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 18 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 input 9 \dest12__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 8 \dest12__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 input 11 \dest22__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 10 \dest22__wen + attribute \src "libresoc.v:165629.7-165629.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 14 \r22__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \r22__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 15 \r22__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 12 \r2__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \r2__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 13 \r2__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 4 \reg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 4 \reg$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 3 \src12__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \src12__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 2 \src12__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 5 \src22__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \src22__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 4 \src22__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 7 \src32__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \src32__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 6 \src32__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 input 16 \w2__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 17 \w2__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:165705$10591 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$10 + connect \Y $not$libresoc.v:165705$10591_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:165706$10592 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$13 + connect \Y $not$libresoc.v:165706$10592_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:165707$10593 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect + connect \Y $not$libresoc.v:165707$10593_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:165708$10594 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$4 + connect \Y $not$libresoc.v:165708$10594_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:165709$10595 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$7 + connect \Y $not$libresoc.v:165709$10595_Y + end + attribute \src "libresoc.v:165629.7-165629.20" + process $proc$libresoc.v:165629$10673 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:165654.13-165654.31" + process $proc$libresoc.v:165654$10674 + assign { } { } + assign $1\r22__data_o[3:0] 4'0000 + sync always + sync init + update \r22__data_o $1\r22__data_o[3:0] + end + attribute \src "libresoc.v:165661.13-165661.30" + process $proc$libresoc.v:165661$10675 + assign { } { } + assign $1\r2__data_o[3:0] 4'0000 + sync always + sync init + update \r2__data_o $1\r2__data_o[3:0] + end + attribute \src "libresoc.v:165667.13-165667.25" + process $proc$libresoc.v:165667$10676 + assign { } { } + assign $1\reg[3:0] 4'0000 + sync always + sync init + update \reg $1\reg[3:0] + end + attribute \src "libresoc.v:165672.13-165672.33" + process $proc$libresoc.v:165672$10677 + assign { } { } + assign $1\src12__data_o[3:0] 4'0000 + sync always + sync init + update \src12__data_o $1\src12__data_o[3:0] + end + attribute \src "libresoc.v:165679.13-165679.33" + process $proc$libresoc.v:165679$10678 + assign { } { } + assign $1\src22__data_o[3:0] 4'0000 + sync always + sync init + update \src22__data_o $1\src22__data_o[3:0] + end + attribute \src "libresoc.v:165686.13-165686.33" + process $proc$libresoc.v:165686$10679 + assign { } { } + assign $1\src32__data_o[3:0] 4'0000 + sync always + sync init + update \src32__data_o $1\src32__data_o[3:0] + end + attribute \src "libresoc.v:165710.3-165711.25" + process $proc$libresoc.v:165710$10596 + assign { } { } + assign $0\reg[3:0] \reg$next + sync posedge \coresync_clk + update \reg $0\reg[3:0] + end + attribute \src "libresoc.v:165712.3-165713.39" + process $proc$libresoc.v:165712$10597 + assign { } { } + assign $0\r22__data_o[3:0] \r22__data_o$next + sync posedge \coresync_clk + update \r22__data_o $0\r22__data_o[3:0] + end + attribute \src "libresoc.v:165714.3-165715.37" + process $proc$libresoc.v:165714$10598 + assign { } { } + assign $0\r2__data_o[3:0] \r2__data_o$next + sync posedge \coresync_clk + update \r2__data_o $0\r2__data_o[3:0] + end + attribute \src "libresoc.v:165716.3-165717.43" + process $proc$libresoc.v:165716$10599 + assign { } { } + assign $0\src32__data_o[3:0] \src32__data_o$next + sync posedge \coresync_clk + update \src32__data_o $0\src32__data_o[3:0] + end + attribute \src "libresoc.v:165718.3-165719.43" + process $proc$libresoc.v:165718$10600 + assign { } { } + assign $0\src22__data_o[3:0] \src22__data_o$next + sync posedge \coresync_clk + update \src22__data_o $0\src22__data_o[3:0] + end + attribute \src "libresoc.v:165720.3-165721.43" + process $proc$libresoc.v:165720$10601 + assign { } { } + assign $0\src12__data_o[3:0] \src12__data_o$next + sync posedge \coresync_clk + update \src12__data_o $0\src12__data_o[3:0] + end + attribute \src "libresoc.v:165722.3-165761.6" + process $proc$libresoc.v:165722$10602 + assign { } { } + assign { } { } + assign { } { } + assign $0\src12__data_o$next[3:0]$10603 $6\src12__data_o$next[3:0]$10609 + attribute \src "libresoc.v:165723.5-165723.29" + switch \initial + attribute \src "libresoc.v:165723.9-165723.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src12__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src12__data_o$next[3:0]$10604 $5\src12__data_o$next[3:0]$10608 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest12__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src12__data_o$next[3:0]$10605 \dest12__data_i + case + assign $2\src12__data_o$next[3:0]$10605 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest22__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src12__data_o$next[3:0]$10606 \dest22__data_i + case + assign $3\src12__data_o$next[3:0]$10606 $2\src12__data_o$next[3:0]$10605 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src12__data_o$next[3:0]$10607 \w2__data_i + case + assign $4\src12__data_o$next[3:0]$10607 $3\src12__data_o$next[3:0]$10606 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src12__data_o$next[3:0]$10608 \reg + case + assign $5\src12__data_o$next[3:0]$10608 $4\src12__data_o$next[3:0]$10607 + end + case + assign $1\src12__data_o$next[3:0]$10604 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src12__data_o$next[3:0]$10609 4'0000 + case + assign $6\src12__data_o$next[3:0]$10609 $1\src12__data_o$next[3:0]$10604 + end + sync always + update \src12__data_o$next $0\src12__data_o$next[3:0]$10603 + end + attribute \src "libresoc.v:165762.3-165791.6" + process $proc$libresoc.v:165762$10610 + assign { } { } + assign { } { } + assign $0\wr_detect[0:0] $1\wr_detect[0:0] + attribute \src "libresoc.v:165763.5-165763.29" + switch \initial + attribute \src "libresoc.v:165763.9-165763.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src12__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect[0:0] $4\wr_detect[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest12__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect[0:0] 1'1 + case + assign $2\wr_detect[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest22__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect[0:0] 1'1 + case + assign $3\wr_detect[0:0] $2\wr_detect[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect[0:0] 1'1 + case + assign $4\wr_detect[0:0] $3\wr_detect[0:0] + end + case + assign $1\wr_detect[0:0] 1'0 + end + sync always + update \wr_detect $0\wr_detect[0:0] + end + attribute \src "libresoc.v:165792.3-165818.6" + process $proc$libresoc.v:165792$10611 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\reg$next[3:0]$10612 $4\reg$next[3:0]$10616 + attribute \src "libresoc.v:165793.5-165793.29" + switch \initial + attribute \src "libresoc.v:165793.9-165793.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest12__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\reg$next[3:0]$10613 \dest12__data_i + case + assign $1\reg$next[3:0]$10613 \reg + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest22__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\reg$next[3:0]$10614 \dest22__data_i + case + assign $2\reg$next[3:0]$10614 $1\reg$next[3:0]$10613 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \w2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\reg$next[3:0]$10615 \w2__data_i + case + assign $3\reg$next[3:0]$10615 $2\reg$next[3:0]$10614 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\reg$next[3:0]$10616 4'0000 + case + assign $4\reg$next[3:0]$10616 $3\reg$next[3:0]$10615 + end + sync always + update \reg$next $0\reg$next[3:0]$10612 + end + attribute \src "libresoc.v:165819.3-165858.6" + process $proc$libresoc.v:165819$10617 + assign { } { } + assign { } { } + assign { } { } + assign $0\src22__data_o$next[3:0]$10618 $6\src22__data_o$next[3:0]$10624 + attribute \src "libresoc.v:165820.5-165820.29" + switch \initial + attribute \src "libresoc.v:165820.9-165820.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src22__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src22__data_o$next[3:0]$10619 $5\src22__data_o$next[3:0]$10623 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest12__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src22__data_o$next[3:0]$10620 \dest12__data_i + case + assign $2\src22__data_o$next[3:0]$10620 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest22__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src22__data_o$next[3:0]$10621 \dest22__data_i + case + assign $3\src22__data_o$next[3:0]$10621 $2\src22__data_o$next[3:0]$10620 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src22__data_o$next[3:0]$10622 \w2__data_i + case + assign $4\src22__data_o$next[3:0]$10622 $3\src22__data_o$next[3:0]$10621 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src22__data_o$next[3:0]$10623 \reg + case + assign $5\src22__data_o$next[3:0]$10623 $4\src22__data_o$next[3:0]$10622 + end + case + assign $1\src22__data_o$next[3:0]$10619 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src22__data_o$next[3:0]$10624 4'0000 + case + assign $6\src22__data_o$next[3:0]$10624 $1\src22__data_o$next[3:0]$10619 + end + sync always + update \src22__data_o$next $0\src22__data_o$next[3:0]$10618 + end + attribute \src "libresoc.v:165859.3-165888.6" + process $proc$libresoc.v:165859$10625 + assign { } { } + assign { } { } + assign $0\wr_detect$4[0:0]$10626 $1\wr_detect$4[0:0]$10627 + attribute \src "libresoc.v:165860.5-165860.29" + switch \initial + attribute \src "libresoc.v:165860.9-165860.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src22__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$4[0:0]$10627 $4\wr_detect$4[0:0]$10630 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest12__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$4[0:0]$10628 1'1 + case + assign $2\wr_detect$4[0:0]$10628 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest22__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$4[0:0]$10629 1'1 + case + assign $3\wr_detect$4[0:0]$10629 $2\wr_detect$4[0:0]$10628 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$4[0:0]$10630 1'1 + case + assign $4\wr_detect$4[0:0]$10630 $3\wr_detect$4[0:0]$10629 + end + case + assign $1\wr_detect$4[0:0]$10627 1'0 + end + sync always + update \wr_detect$4 $0\wr_detect$4[0:0]$10626 + end + attribute \src "libresoc.v:165889.3-165928.6" + process $proc$libresoc.v:165889$10631 + assign { } { } + assign { } { } + assign { } { } + assign $0\src32__data_o$next[3:0]$10632 $6\src32__data_o$next[3:0]$10638 + attribute \src "libresoc.v:165890.5-165890.29" + switch \initial + attribute \src "libresoc.v:165890.9-165890.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src32__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src32__data_o$next[3:0]$10633 $5\src32__data_o$next[3:0]$10637 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest12__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src32__data_o$next[3:0]$10634 \dest12__data_i + case + assign $2\src32__data_o$next[3:0]$10634 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest22__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src32__data_o$next[3:0]$10635 \dest22__data_i + case + assign $3\src32__data_o$next[3:0]$10635 $2\src32__data_o$next[3:0]$10634 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src32__data_o$next[3:0]$10636 \w2__data_i + case + assign $4\src32__data_o$next[3:0]$10636 $3\src32__data_o$next[3:0]$10635 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$6 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src32__data_o$next[3:0]$10637 \reg + case + assign $5\src32__data_o$next[3:0]$10637 $4\src32__data_o$next[3:0]$10636 + end + case + assign $1\src32__data_o$next[3:0]$10633 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src32__data_o$next[3:0]$10638 4'0000 + case + assign $6\src32__data_o$next[3:0]$10638 $1\src32__data_o$next[3:0]$10633 + end + sync always + update \src32__data_o$next $0\src32__data_o$next[3:0]$10632 + end + attribute \src "libresoc.v:165929.3-165958.6" + process $proc$libresoc.v:165929$10639 + assign { } { } + assign { } { } + assign $0\wr_detect$7[0:0]$10640 $1\wr_detect$7[0:0]$10641 + attribute \src "libresoc.v:165930.5-165930.29" + switch \initial + attribute \src "libresoc.v:165930.9-165930.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src32__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$7[0:0]$10641 $4\wr_detect$7[0:0]$10644 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest12__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$7[0:0]$10642 1'1 + case + assign $2\wr_detect$7[0:0]$10642 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest22__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$7[0:0]$10643 1'1 + case + assign $3\wr_detect$7[0:0]$10643 $2\wr_detect$7[0:0]$10642 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$7[0:0]$10644 1'1 + case + assign $4\wr_detect$7[0:0]$10644 $3\wr_detect$7[0:0]$10643 + end + case + assign $1\wr_detect$7[0:0]$10641 1'0 + end + sync always + update \wr_detect$7 $0\wr_detect$7[0:0]$10640 + end + attribute \src "libresoc.v:165959.3-165998.6" + process $proc$libresoc.v:165959$10645 + assign { } { } + assign { } { } + assign { } { } + assign $0\r2__data_o$next[3:0]$10646 $6\r2__data_o$next[3:0]$10652 + attribute \src "libresoc.v:165960.5-165960.29" + switch \initial + attribute \src "libresoc.v:165960.9-165960.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r2__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\r2__data_o$next[3:0]$10647 $5\r2__data_o$next[3:0]$10651 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest12__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r2__data_o$next[3:0]$10648 \dest12__data_i + case + assign $2\r2__data_o$next[3:0]$10648 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest22__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\r2__data_o$next[3:0]$10649 \dest22__data_i + case + assign $3\r2__data_o$next[3:0]$10649 $2\r2__data_o$next[3:0]$10648 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\r2__data_o$next[3:0]$10650 \w2__data_i + case + assign $4\r2__data_o$next[3:0]$10650 $3\r2__data_o$next[3:0]$10649 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$9 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\r2__data_o$next[3:0]$10651 \reg + case + assign $5\r2__data_o$next[3:0]$10651 $4\r2__data_o$next[3:0]$10650 + end + case + assign $1\r2__data_o$next[3:0]$10647 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\r2__data_o$next[3:0]$10652 4'0000 + case + assign $6\r2__data_o$next[3:0]$10652 $1\r2__data_o$next[3:0]$10647 + end + sync always + update \r2__data_o$next $0\r2__data_o$next[3:0]$10646 + end + attribute \src "libresoc.v:165999.3-166028.6" + process $proc$libresoc.v:165999$10653 + assign { } { } + assign { } { } + assign $0\wr_detect$10[0:0]$10654 $1\wr_detect$10[0:0]$10655 + attribute \src "libresoc.v:166000.5-166000.29" + switch \initial + attribute \src "libresoc.v:166000.9-166000.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r2__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$10[0:0]$10655 $4\wr_detect$10[0:0]$10658 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest12__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$10[0:0]$10656 1'1 + case + assign $2\wr_detect$10[0:0]$10656 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest22__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$10[0:0]$10657 1'1 + case + assign $3\wr_detect$10[0:0]$10657 $2\wr_detect$10[0:0]$10656 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$10[0:0]$10658 1'1 + case + assign $4\wr_detect$10[0:0]$10658 $3\wr_detect$10[0:0]$10657 + end + case + assign $1\wr_detect$10[0:0]$10655 1'0 + end + sync always + update \wr_detect$10 $0\wr_detect$10[0:0]$10654 + end + attribute \src "libresoc.v:166029.3-166068.6" + process $proc$libresoc.v:166029$10659 + assign { } { } + assign { } { } + assign { } { } + assign $0\r22__data_o$next[3:0]$10660 $6\r22__data_o$next[3:0]$10666 + attribute \src "libresoc.v:166030.5-166030.29" + switch \initial + attribute \src "libresoc.v:166030.9-166030.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r22__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\r22__data_o$next[3:0]$10661 $5\r22__data_o$next[3:0]$10665 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest12__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r22__data_o$next[3:0]$10662 \dest12__data_i + case + assign $2\r22__data_o$next[3:0]$10662 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest22__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\r22__data_o$next[3:0]$10663 \dest22__data_i + case + assign $3\r22__data_o$next[3:0]$10663 $2\r22__data_o$next[3:0]$10662 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\r22__data_o$next[3:0]$10664 \w2__data_i + case + assign $4\r22__data_o$next[3:0]$10664 $3\r22__data_o$next[3:0]$10663 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$12 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\r22__data_o$next[3:0]$10665 \reg + case + assign $5\r22__data_o$next[3:0]$10665 $4\r22__data_o$next[3:0]$10664 + end + case + assign $1\r22__data_o$next[3:0]$10661 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\r22__data_o$next[3:0]$10666 4'0000 + case + assign $6\r22__data_o$next[3:0]$10666 $1\r22__data_o$next[3:0]$10661 + end + sync always + update \r22__data_o$next $0\r22__data_o$next[3:0]$10660 + end + attribute \src "libresoc.v:166069.3-166098.6" + process $proc$libresoc.v:166069$10667 + assign { } { } + assign { } { } + assign $0\wr_detect$13[0:0]$10668 $1\wr_detect$13[0:0]$10669 + attribute \src "libresoc.v:166070.5-166070.29" + switch \initial + attribute \src "libresoc.v:166070.9-166070.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r22__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$13[0:0]$10669 $4\wr_detect$13[0:0]$10672 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest12__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$13[0:0]$10670 1'1 + case + assign $2\wr_detect$13[0:0]$10670 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest22__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$13[0:0]$10671 1'1 + case + assign $3\wr_detect$13[0:0]$10671 $2\wr_detect$13[0:0]$10670 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$13[0:0]$10672 1'1 + case + assign $4\wr_detect$13[0:0]$10672 $3\wr_detect$13[0:0]$10671 + end + case + assign $1\wr_detect$13[0:0]$10669 1'0 + end + sync always + update \wr_detect$13 $0\wr_detect$13[0:0]$10668 + end + connect \$9 $not$libresoc.v:165705$10591_Y + connect \$12 $not$libresoc.v:165706$10592_Y + connect \$1 $not$libresoc.v:165707$10593_Y + connect \$3 $not$libresoc.v:165708$10594_Y + connect \$6 $not$libresoc.v:165709$10595_Y +end +attribute \src "libresoc.v:166103.1-166548.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.xer.reg_2" +attribute \generator "nMigen" +module \reg_2$131 + attribute \src "libresoc.v:166104.7-166104.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:166433.3-166478.6" + wire width 2 $0\r2__data_o$next[1:0]$10732 + attribute \src "libresoc.v:166179.3-166180.37" + wire width 2 $0\r2__data_o[1:0] + attribute \src "libresoc.v:166515.3-166547.6" + wire width 2 $0\reg$next[1:0]$10748 + attribute \src "libresoc.v:166177.3-166178.25" + wire width 2 $0\reg[1:0] + attribute \src "libresoc.v:166187.3-166232.6" + wire width 2 $0\src12__data_o$next[1:0]$10690 + attribute \src "libresoc.v:166185.3-166186.43" + wire width 2 $0\src12__data_o[1:0] + attribute \src "libresoc.v:166269.3-166314.6" + wire width 2 $0\src22__data_o$next[1:0]$10700 + attribute \src "libresoc.v:166183.3-166184.43" + wire width 2 $0\src22__data_o[1:0] + attribute \src "libresoc.v:166351.3-166396.6" + wire width 2 $0\src32__data_o$next[1:0]$10716 + attribute \src "libresoc.v:166181.3-166182.43" + wire width 2 $0\src32__data_o[1:0] + attribute \src "libresoc.v:166479.3-166514.6" + wire $0\wr_detect$10[0:0]$10741 + attribute \src "libresoc.v:166315.3-166350.6" + wire $0\wr_detect$4[0:0]$10709 + attribute \src "libresoc.v:166397.3-166432.6" + wire $0\wr_detect$7[0:0]$10725 + attribute \src "libresoc.v:166233.3-166268.6" + wire $0\wr_detect[0:0] + attribute \src "libresoc.v:166433.3-166478.6" + wire width 2 $1\r2__data_o$next[1:0]$10733 + attribute \src "libresoc.v:166131.13-166131.30" + wire width 2 $1\r2__data_o[1:0] + attribute \src "libresoc.v:166515.3-166547.6" + wire width 2 $1\reg$next[1:0]$10749 + attribute \src "libresoc.v:166137.13-166137.25" + wire width 2 $1\reg[1:0] + attribute \src "libresoc.v:166187.3-166232.6" + wire width 2 $1\src12__data_o$next[1:0]$10691 + attribute \src "libresoc.v:166142.13-166142.33" + wire width 2 $1\src12__data_o[1:0] + attribute \src "libresoc.v:166269.3-166314.6" + wire width 2 $1\src22__data_o$next[1:0]$10701 + attribute \src "libresoc.v:166149.13-166149.33" + wire width 2 $1\src22__data_o[1:0] + attribute \src "libresoc.v:166351.3-166396.6" + wire width 2 $1\src32__data_o$next[1:0]$10717 + attribute \src "libresoc.v:166156.13-166156.33" + wire width 2 $1\src32__data_o[1:0] + attribute \src "libresoc.v:166479.3-166514.6" + wire $1\wr_detect$10[0:0]$10742 + attribute \src "libresoc.v:166315.3-166350.6" + wire $1\wr_detect$4[0:0]$10710 + attribute \src "libresoc.v:166397.3-166432.6" + wire $1\wr_detect$7[0:0]$10726 + attribute \src "libresoc.v:166233.3-166268.6" + wire $1\wr_detect[0:0] + attribute \src "libresoc.v:166433.3-166478.6" + wire width 2 $2\r2__data_o$next[1:0]$10734 + attribute \src "libresoc.v:166515.3-166547.6" + wire width 2 $2\reg$next[1:0]$10750 + attribute \src "libresoc.v:166187.3-166232.6" + wire width 2 $2\src12__data_o$next[1:0]$10692 + attribute \src "libresoc.v:166269.3-166314.6" + wire width 2 $2\src22__data_o$next[1:0]$10702 + attribute \src "libresoc.v:166351.3-166396.6" + wire width 2 $2\src32__data_o$next[1:0]$10718 + attribute \src "libresoc.v:166479.3-166514.6" + wire $2\wr_detect$10[0:0]$10743 + attribute \src "libresoc.v:166315.3-166350.6" + wire $2\wr_detect$4[0:0]$10711 + attribute \src "libresoc.v:166397.3-166432.6" + wire $2\wr_detect$7[0:0]$10727 + attribute \src "libresoc.v:166233.3-166268.6" + wire $2\wr_detect[0:0] + attribute \src "libresoc.v:166433.3-166478.6" + wire width 2 $3\r2__data_o$next[1:0]$10735 + attribute \src "libresoc.v:166515.3-166547.6" + wire width 2 $3\reg$next[1:0]$10751 + attribute \src "libresoc.v:166187.3-166232.6" + wire width 2 $3\src12__data_o$next[1:0]$10693 + attribute \src "libresoc.v:166269.3-166314.6" + wire width 2 $3\src22__data_o$next[1:0]$10703 + attribute \src "libresoc.v:166351.3-166396.6" + wire width 2 $3\src32__data_o$next[1:0]$10719 + attribute \src "libresoc.v:166479.3-166514.6" + wire $3\wr_detect$10[0:0]$10744 + attribute \src "libresoc.v:166315.3-166350.6" + wire $3\wr_detect$4[0:0]$10712 + attribute \src "libresoc.v:166397.3-166432.6" + wire $3\wr_detect$7[0:0]$10728 + attribute \src "libresoc.v:166233.3-166268.6" + wire $3\wr_detect[0:0] + attribute \src "libresoc.v:166433.3-166478.6" + wire width 2 $4\r2__data_o$next[1:0]$10736 + attribute \src "libresoc.v:166515.3-166547.6" + wire width 2 $4\reg$next[1:0]$10752 + attribute \src "libresoc.v:166187.3-166232.6" + wire width 2 $4\src12__data_o$next[1:0]$10694 + attribute \src "libresoc.v:166269.3-166314.6" + wire width 2 $4\src22__data_o$next[1:0]$10704 + attribute \src "libresoc.v:166351.3-166396.6" + wire width 2 $4\src32__data_o$next[1:0]$10720 + attribute \src "libresoc.v:166479.3-166514.6" + wire $4\wr_detect$10[0:0]$10745 + attribute \src "libresoc.v:166315.3-166350.6" + wire $4\wr_detect$4[0:0]$10713 + attribute \src "libresoc.v:166397.3-166432.6" + wire $4\wr_detect$7[0:0]$10729 + attribute \src "libresoc.v:166233.3-166268.6" + wire $4\wr_detect[0:0] + attribute \src "libresoc.v:166433.3-166478.6" + wire width 2 $5\r2__data_o$next[1:0]$10737 + attribute \src "libresoc.v:166515.3-166547.6" + wire width 2 $5\reg$next[1:0]$10753 + attribute \src "libresoc.v:166187.3-166232.6" + wire width 2 $5\src12__data_o$next[1:0]$10695 + attribute \src "libresoc.v:166269.3-166314.6" + wire width 2 $5\src22__data_o$next[1:0]$10705 + attribute \src "libresoc.v:166351.3-166396.6" + wire width 2 $5\src32__data_o$next[1:0]$10721 + attribute \src "libresoc.v:166479.3-166514.6" + wire $5\wr_detect$10[0:0]$10746 + attribute \src "libresoc.v:166315.3-166350.6" + wire $5\wr_detect$4[0:0]$10714 + attribute \src "libresoc.v:166397.3-166432.6" + wire $5\wr_detect$7[0:0]$10730 + attribute \src "libresoc.v:166233.3-166268.6" + wire $5\wr_detect[0:0] + attribute \src "libresoc.v:166433.3-166478.6" + wire width 2 $6\r2__data_o$next[1:0]$10738 + attribute \src "libresoc.v:166187.3-166232.6" + wire width 2 $6\src12__data_o$next[1:0]$10696 + attribute \src "libresoc.v:166269.3-166314.6" + wire width 2 $6\src22__data_o$next[1:0]$10706 + attribute \src "libresoc.v:166351.3-166396.6" + wire width 2 $6\src32__data_o$next[1:0]$10722 + attribute \src "libresoc.v:166433.3-166478.6" + wire width 2 $7\r2__data_o$next[1:0]$10739 + attribute \src "libresoc.v:166187.3-166232.6" + wire width 2 $7\src12__data_o$next[1:0]$10697 + attribute \src "libresoc.v:166269.3-166314.6" + wire width 2 $7\src22__data_o$next[1:0]$10707 + attribute \src "libresoc.v:166351.3-166396.6" + wire width 2 $7\src32__data_o$next[1:0]$10723 + attribute \src "libresoc.v:166173.17-166173.104" + wire $not$libresoc.v:166173$10680_Y + attribute \src "libresoc.v:166174.17-166174.100" + wire $not$libresoc.v:166174$10681_Y + attribute \src "libresoc.v:166175.17-166175.103" + wire $not$libresoc.v:166175$10682_Y + attribute \src "libresoc.v:166176.17-166176.103" + wire $not$libresoc.v:166176$10683_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 18 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 input 9 \dest12__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 8 \dest12__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 input 11 \dest22__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 10 \dest22__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 input 13 \dest32__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 12 \dest32__wen + attribute \src "libresoc.v:166104.7-166104.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 output 14 \r2__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 \r2__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 15 \r2__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 2 \reg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 2 \reg$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 output 3 \src12__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 \src12__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 2 \src12__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 output 5 \src22__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 \src22__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 4 \src22__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 output 7 \src32__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 \src32__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 6 \src32__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 input 16 \w2__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 17 \w2__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:166173$10680 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$10 + connect \Y $not$libresoc.v:166173$10680_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:166174$10681 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect + connect \Y $not$libresoc.v:166174$10681_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:166175$10682 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$4 + connect \Y $not$libresoc.v:166175$10682_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:166176$10683 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$7 + connect \Y $not$libresoc.v:166176$10683_Y + end + attribute \src "libresoc.v:166104.7-166104.20" + process $proc$libresoc.v:166104$10754 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:166131.13-166131.30" + process $proc$libresoc.v:166131$10755 + assign { } { } + assign $1\r2__data_o[1:0] 2'00 + sync always + sync init + update \r2__data_o $1\r2__data_o[1:0] + end + attribute \src "libresoc.v:166137.13-166137.25" + process $proc$libresoc.v:166137$10756 + assign { } { } + assign $1\reg[1:0] 2'00 + sync always + sync init + update \reg $1\reg[1:0] + end + attribute \src "libresoc.v:166142.13-166142.33" + process $proc$libresoc.v:166142$10757 + assign { } { } + assign $1\src12__data_o[1:0] 2'00 + sync always + sync init + update \src12__data_o $1\src12__data_o[1:0] + end + attribute \src "libresoc.v:166149.13-166149.33" + process $proc$libresoc.v:166149$10758 + assign { } { } + assign $1\src22__data_o[1:0] 2'00 + sync always + sync init + update \src22__data_o $1\src22__data_o[1:0] + end + attribute \src "libresoc.v:166156.13-166156.33" + process $proc$libresoc.v:166156$10759 + assign { } { } + assign $1\src32__data_o[1:0] 2'00 + sync always + sync init + update \src32__data_o $1\src32__data_o[1:0] + end + attribute \src "libresoc.v:166177.3-166178.25" + process $proc$libresoc.v:166177$10684 + assign { } { } + assign $0\reg[1:0] \reg$next + sync posedge \coresync_clk + update \reg $0\reg[1:0] + end + attribute \src "libresoc.v:166179.3-166180.37" + process $proc$libresoc.v:166179$10685 + assign { } { } + assign $0\r2__data_o[1:0] \r2__data_o$next + sync posedge \coresync_clk + update \r2__data_o $0\r2__data_o[1:0] + end + attribute \src "libresoc.v:166181.3-166182.43" + process $proc$libresoc.v:166181$10686 + assign { } { } + assign $0\src32__data_o[1:0] \src32__data_o$next + sync posedge \coresync_clk + update \src32__data_o $0\src32__data_o[1:0] + end + attribute \src "libresoc.v:166183.3-166184.43" + process $proc$libresoc.v:166183$10687 + assign { } { } + assign $0\src22__data_o[1:0] \src22__data_o$next + sync posedge \coresync_clk + update \src22__data_o $0\src22__data_o[1:0] + end + attribute \src "libresoc.v:166185.3-166186.43" + process $proc$libresoc.v:166185$10688 + assign { } { } + assign $0\src12__data_o[1:0] \src12__data_o$next + sync posedge \coresync_clk + update \src12__data_o $0\src12__data_o[1:0] + end + attribute \src "libresoc.v:166187.3-166232.6" + process $proc$libresoc.v:166187$10689 + assign { } { } + assign { } { } + assign { } { } + assign $0\src12__data_o$next[1:0]$10690 $7\src12__data_o$next[1:0]$10697 + attribute \src "libresoc.v:166188.5-166188.29" + switch \initial + attribute \src "libresoc.v:166188.9-166188.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src12__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src12__data_o$next[1:0]$10691 $6\src12__data_o$next[1:0]$10696 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest12__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src12__data_o$next[1:0]$10692 \dest12__data_i + case + assign $2\src12__data_o$next[1:0]$10692 2'00 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest22__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src12__data_o$next[1:0]$10693 \dest22__data_i + case + assign $3\src12__data_o$next[1:0]$10693 $2\src12__data_o$next[1:0]$10692 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest32__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src12__data_o$next[1:0]$10694 \dest32__data_i + case + assign $4\src12__data_o$next[1:0]$10694 $3\src12__data_o$next[1:0]$10693 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src12__data_o$next[1:0]$10695 \w2__data_i + case + assign $5\src12__data_o$next[1:0]$10695 $4\src12__data_o$next[1:0]$10694 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src12__data_o$next[1:0]$10696 \reg + case + assign $6\src12__data_o$next[1:0]$10696 $5\src12__data_o$next[1:0]$10695 + end + case + assign $1\src12__data_o$next[1:0]$10691 2'00 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\src12__data_o$next[1:0]$10697 2'00 + case + assign $7\src12__data_o$next[1:0]$10697 $1\src12__data_o$next[1:0]$10691 + end + sync always + update \src12__data_o$next $0\src12__data_o$next[1:0]$10690 + end + attribute \src "libresoc.v:166233.3-166268.6" + process $proc$libresoc.v:166233$10698 + assign { } { } + assign { } { } + assign $0\wr_detect[0:0] $1\wr_detect[0:0] + attribute \src "libresoc.v:166234.5-166234.29" + switch \initial + attribute \src "libresoc.v:166234.9-166234.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src12__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect[0:0] $5\wr_detect[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest12__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect[0:0] 1'1 + case + assign $2\wr_detect[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest22__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect[0:0] 1'1 + case + assign $3\wr_detect[0:0] $2\wr_detect[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest32__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect[0:0] 1'1 + case + assign $4\wr_detect[0:0] $3\wr_detect[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\wr_detect[0:0] 1'1 + case + assign $5\wr_detect[0:0] $4\wr_detect[0:0] + end + case + assign $1\wr_detect[0:0] 1'0 + end + sync always + update \wr_detect $0\wr_detect[0:0] + end + attribute \src "libresoc.v:166269.3-166314.6" + process $proc$libresoc.v:166269$10699 + assign { } { } + assign { } { } + assign { } { } + assign $0\src22__data_o$next[1:0]$10700 $7\src22__data_o$next[1:0]$10707 + attribute \src "libresoc.v:166270.5-166270.29" + switch \initial + attribute \src "libresoc.v:166270.9-166270.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src22__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src22__data_o$next[1:0]$10701 $6\src22__data_o$next[1:0]$10706 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest12__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src22__data_o$next[1:0]$10702 \dest12__data_i + case + assign $2\src22__data_o$next[1:0]$10702 2'00 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest22__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src22__data_o$next[1:0]$10703 \dest22__data_i + case + assign $3\src22__data_o$next[1:0]$10703 $2\src22__data_o$next[1:0]$10702 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest32__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src22__data_o$next[1:0]$10704 \dest32__data_i + case + assign $4\src22__data_o$next[1:0]$10704 $3\src22__data_o$next[1:0]$10703 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src22__data_o$next[1:0]$10705 \w2__data_i + case + assign $5\src22__data_o$next[1:0]$10705 $4\src22__data_o$next[1:0]$10704 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src22__data_o$next[1:0]$10706 \reg + case + assign $6\src22__data_o$next[1:0]$10706 $5\src22__data_o$next[1:0]$10705 + end + case + assign $1\src22__data_o$next[1:0]$10701 2'00 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\src22__data_o$next[1:0]$10707 2'00 + case + assign $7\src22__data_o$next[1:0]$10707 $1\src22__data_o$next[1:0]$10701 + end + sync always + update \src22__data_o$next $0\src22__data_o$next[1:0]$10700 + end + attribute \src "libresoc.v:166315.3-166350.6" + process $proc$libresoc.v:166315$10708 + assign { } { } + assign { } { } + assign $0\wr_detect$4[0:0]$10709 $1\wr_detect$4[0:0]$10710 + attribute \src "libresoc.v:166316.5-166316.29" + switch \initial + attribute \src "libresoc.v:166316.9-166316.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src22__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$4[0:0]$10710 $5\wr_detect$4[0:0]$10714 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest12__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$4[0:0]$10711 1'1 + case + assign $2\wr_detect$4[0:0]$10711 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest22__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$4[0:0]$10712 1'1 + case + assign $3\wr_detect$4[0:0]$10712 $2\wr_detect$4[0:0]$10711 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest32__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$4[0:0]$10713 1'1 + case + assign $4\wr_detect$4[0:0]$10713 $3\wr_detect$4[0:0]$10712 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\wr_detect$4[0:0]$10714 1'1 + case + assign $5\wr_detect$4[0:0]$10714 $4\wr_detect$4[0:0]$10713 + end + case + assign $1\wr_detect$4[0:0]$10710 1'0 + end + sync always + update \wr_detect$4 $0\wr_detect$4[0:0]$10709 + end + attribute \src "libresoc.v:166351.3-166396.6" + process $proc$libresoc.v:166351$10715 + assign { } { } + assign { } { } + assign { } { } + assign $0\src32__data_o$next[1:0]$10716 $7\src32__data_o$next[1:0]$10723 + attribute \src "libresoc.v:166352.5-166352.29" + switch \initial + attribute \src "libresoc.v:166352.9-166352.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src32__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src32__data_o$next[1:0]$10717 $6\src32__data_o$next[1:0]$10722 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest12__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src32__data_o$next[1:0]$10718 \dest12__data_i + case + assign $2\src32__data_o$next[1:0]$10718 2'00 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest22__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src32__data_o$next[1:0]$10719 \dest22__data_i + case + assign $3\src32__data_o$next[1:0]$10719 $2\src32__data_o$next[1:0]$10718 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest32__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src32__data_o$next[1:0]$10720 \dest32__data_i + case + assign $4\src32__data_o$next[1:0]$10720 $3\src32__data_o$next[1:0]$10719 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src32__data_o$next[1:0]$10721 \w2__data_i + case + assign $5\src32__data_o$next[1:0]$10721 $4\src32__data_o$next[1:0]$10720 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$6 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src32__data_o$next[1:0]$10722 \reg + case + assign $6\src32__data_o$next[1:0]$10722 $5\src32__data_o$next[1:0]$10721 + end + case + assign $1\src32__data_o$next[1:0]$10717 2'00 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\src32__data_o$next[1:0]$10723 2'00 + case + assign $7\src32__data_o$next[1:0]$10723 $1\src32__data_o$next[1:0]$10717 + end + sync always + update \src32__data_o$next $0\src32__data_o$next[1:0]$10716 + end + attribute \src "libresoc.v:166397.3-166432.6" + process $proc$libresoc.v:166397$10724 + assign { } { } + assign { } { } + assign $0\wr_detect$7[0:0]$10725 $1\wr_detect$7[0:0]$10726 + attribute \src "libresoc.v:166398.5-166398.29" + switch \initial + attribute \src "libresoc.v:166398.9-166398.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src32__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$7[0:0]$10726 $5\wr_detect$7[0:0]$10730 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest12__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$7[0:0]$10727 1'1 + case + assign $2\wr_detect$7[0:0]$10727 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest22__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$7[0:0]$10728 1'1 + case + assign $3\wr_detect$7[0:0]$10728 $2\wr_detect$7[0:0]$10727 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest32__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$7[0:0]$10729 1'1 + case + assign $4\wr_detect$7[0:0]$10729 $3\wr_detect$7[0:0]$10728 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\wr_detect$7[0:0]$10730 1'1 + case + assign $5\wr_detect$7[0:0]$10730 $4\wr_detect$7[0:0]$10729 + end + case + assign $1\wr_detect$7[0:0]$10726 1'0 + end + sync always + update \wr_detect$7 $0\wr_detect$7[0:0]$10725 + end + attribute \src "libresoc.v:166433.3-166478.6" + process $proc$libresoc.v:166433$10731 + assign { } { } + assign { } { } + assign { } { } + assign $0\r2__data_o$next[1:0]$10732 $7\r2__data_o$next[1:0]$10739 + attribute \src "libresoc.v:166434.5-166434.29" + switch \initial + attribute \src "libresoc.v:166434.9-166434.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r2__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\r2__data_o$next[1:0]$10733 $6\r2__data_o$next[1:0]$10738 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest12__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r2__data_o$next[1:0]$10734 \dest12__data_i + case + assign $2\r2__data_o$next[1:0]$10734 2'00 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest22__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\r2__data_o$next[1:0]$10735 \dest22__data_i + case + assign $3\r2__data_o$next[1:0]$10735 $2\r2__data_o$next[1:0]$10734 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest32__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\r2__data_o$next[1:0]$10736 \dest32__data_i + case + assign $4\r2__data_o$next[1:0]$10736 $3\r2__data_o$next[1:0]$10735 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\r2__data_o$next[1:0]$10737 \w2__data_i + case + assign $5\r2__data_o$next[1:0]$10737 $4\r2__data_o$next[1:0]$10736 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$9 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\r2__data_o$next[1:0]$10738 \reg + case + assign $6\r2__data_o$next[1:0]$10738 $5\r2__data_o$next[1:0]$10737 + end + case + assign $1\r2__data_o$next[1:0]$10733 2'00 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\r2__data_o$next[1:0]$10739 2'00 + case + assign $7\r2__data_o$next[1:0]$10739 $1\r2__data_o$next[1:0]$10733 + end + sync always + update \r2__data_o$next $0\r2__data_o$next[1:0]$10732 + end + attribute \src "libresoc.v:166479.3-166514.6" + process $proc$libresoc.v:166479$10740 + assign { } { } + assign { } { } + assign $0\wr_detect$10[0:0]$10741 $1\wr_detect$10[0:0]$10742 + attribute \src "libresoc.v:166480.5-166480.29" + switch \initial + attribute \src "libresoc.v:166480.9-166480.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r2__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$10[0:0]$10742 $5\wr_detect$10[0:0]$10746 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest12__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$10[0:0]$10743 1'1 + case + assign $2\wr_detect$10[0:0]$10743 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest22__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$10[0:0]$10744 1'1 + case + assign $3\wr_detect$10[0:0]$10744 $2\wr_detect$10[0:0]$10743 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest32__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$10[0:0]$10745 1'1 + case + assign $4\wr_detect$10[0:0]$10745 $3\wr_detect$10[0:0]$10744 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\wr_detect$10[0:0]$10746 1'1 + case + assign $5\wr_detect$10[0:0]$10746 $4\wr_detect$10[0:0]$10745 + end + case + assign $1\wr_detect$10[0:0]$10742 1'0 + end + sync always + update \wr_detect$10 $0\wr_detect$10[0:0]$10741 + end + attribute \src "libresoc.v:166515.3-166547.6" + process $proc$libresoc.v:166515$10747 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\reg$next[1:0]$10748 $5\reg$next[1:0]$10753 + attribute \src "libresoc.v:166516.5-166516.29" + switch \initial + attribute \src "libresoc.v:166516.9-166516.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest12__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\reg$next[1:0]$10749 \dest12__data_i + case + assign $1\reg$next[1:0]$10749 \reg + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest22__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\reg$next[1:0]$10750 \dest22__data_i + case + assign $2\reg$next[1:0]$10750 $1\reg$next[1:0]$10749 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest32__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\reg$next[1:0]$10751 \dest32__data_i + case + assign $3\reg$next[1:0]$10751 $2\reg$next[1:0]$10750 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \w2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\reg$next[1:0]$10752 \w2__data_i + case + assign $4\reg$next[1:0]$10752 $3\reg$next[1:0]$10751 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\reg$next[1:0]$10753 2'00 + case + assign $5\reg$next[1:0]$10753 $4\reg$next[1:0]$10752 + end + sync always + update \reg$next $0\reg$next[1:0]$10748 + end + connect \$9 $not$libresoc.v:166173$10680_Y + connect \$1 $not$libresoc.v:166174$10681_Y + connect \$3 $not$libresoc.v:166175$10682_Y + connect \$6 $not$libresoc.v:166176$10683_Y +end +attribute \src "libresoc.v:166552.1-166771.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.state.reg_2" +attribute \generator "nMigen" +module \reg_2$134 + attribute \src "libresoc.v:166604.3-166643.6" + wire width 64 $0\cia2__data_o$next[63:0]$10766 + attribute \src "libresoc.v:166602.3-166603.41" + wire width 64 $0\cia2__data_o[63:0] + attribute \src "libresoc.v:166553.7-166553.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:166674.3-166713.6" + wire width 64 $0\msr2__data_o$next[63:0]$10775 + attribute \src "libresoc.v:166600.3-166601.41" + wire width 64 $0\msr2__data_o[63:0] + attribute \src "libresoc.v:166744.3-166770.6" + wire width 64 $0\reg$next[63:0]$10789 + attribute \src "libresoc.v:166598.3-166599.25" + wire width 64 $0\reg[63:0] + attribute \src "libresoc.v:166714.3-166743.6" + wire $0\wr_detect$4[0:0]$10783 + attribute \src "libresoc.v:166644.3-166673.6" + wire $0\wr_detect[0:0] + attribute \src "libresoc.v:166604.3-166643.6" + wire width 64 $1\cia2__data_o$next[63:0]$10767 + attribute \src "libresoc.v:166560.14-166560.49" + wire width 64 $1\cia2__data_o[63:0] + attribute \src "libresoc.v:166674.3-166713.6" + wire width 64 $1\msr2__data_o$next[63:0]$10776 + attribute \src "libresoc.v:166577.14-166577.49" + wire width 64 $1\msr2__data_o[63:0] + attribute \src "libresoc.v:166744.3-166770.6" + wire width 64 $1\reg$next[63:0]$10790 + attribute \src "libresoc.v:166589.14-166589.42" + wire width 64 $1\reg[63:0] + attribute \src "libresoc.v:166714.3-166743.6" + wire $1\wr_detect$4[0:0]$10784 + attribute \src "libresoc.v:166644.3-166673.6" + wire $1\wr_detect[0:0] + attribute \src "libresoc.v:166604.3-166643.6" + wire width 64 $2\cia2__data_o$next[63:0]$10768 + attribute \src "libresoc.v:166674.3-166713.6" + wire width 64 $2\msr2__data_o$next[63:0]$10777 + attribute \src "libresoc.v:166744.3-166770.6" + wire width 64 $2\reg$next[63:0]$10791 + attribute \src "libresoc.v:166714.3-166743.6" + wire $2\wr_detect$4[0:0]$10785 + attribute \src "libresoc.v:166644.3-166673.6" + wire $2\wr_detect[0:0] + attribute \src "libresoc.v:166604.3-166643.6" + wire width 64 $3\cia2__data_o$next[63:0]$10769 + attribute \src "libresoc.v:166674.3-166713.6" + wire width 64 $3\msr2__data_o$next[63:0]$10778 + attribute \src "libresoc.v:166744.3-166770.6" + wire width 64 $3\reg$next[63:0]$10792 + attribute \src "libresoc.v:166714.3-166743.6" + wire $3\wr_detect$4[0:0]$10786 + attribute \src "libresoc.v:166644.3-166673.6" + wire $3\wr_detect[0:0] + attribute \src "libresoc.v:166604.3-166643.6" + wire width 64 $4\cia2__data_o$next[63:0]$10770 + attribute \src "libresoc.v:166674.3-166713.6" + wire width 64 $4\msr2__data_o$next[63:0]$10779 + attribute \src "libresoc.v:166744.3-166770.6" + wire width 64 $4\reg$next[63:0]$10793 + attribute \src "libresoc.v:166714.3-166743.6" + wire $4\wr_detect$4[0:0]$10787 + attribute \src "libresoc.v:166644.3-166673.6" + wire $4\wr_detect[0:0] + attribute \src "libresoc.v:166604.3-166643.6" + wire width 64 $5\cia2__data_o$next[63:0]$10771 + attribute \src "libresoc.v:166674.3-166713.6" + wire width 64 $5\msr2__data_o$next[63:0]$10780 + attribute \src "libresoc.v:166604.3-166643.6" + wire width 64 $6\cia2__data_o$next[63:0]$10772 + attribute \src "libresoc.v:166674.3-166713.6" + wire width 64 $6\msr2__data_o$next[63:0]$10781 + attribute \src "libresoc.v:166596.17-166596.100" + wire $not$libresoc.v:166596$10760_Y + attribute \src "libresoc.v:166597.17-166597.103" + wire $not$libresoc.v:166597$10761_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 output 3 \cia2__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \cia2__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 2 \cia2__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 12 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 input 11 \d_wr12__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 10 \d_wr12__wen + attribute \src "libresoc.v:166553.7-166553.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 input 9 \msr2__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 output 5 \msr2__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \msr2__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 4 \msr2__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 8 \msr2__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 input 7 \nia2__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 6 \nia2__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 64 \reg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 64 \reg$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:166596$10760 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect + connect \Y $not$libresoc.v:166596$10760_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:166597$10761 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$4 + connect \Y $not$libresoc.v:166597$10761_Y + end + attribute \src "libresoc.v:166553.7-166553.20" + process $proc$libresoc.v:166553$10794 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:166560.14-166560.49" + process $proc$libresoc.v:166560$10795 + assign { } { } + assign $1\cia2__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \cia2__data_o $1\cia2__data_o[63:0] + end + attribute \src "libresoc.v:166577.14-166577.49" + process $proc$libresoc.v:166577$10796 + assign { } { } + assign $1\msr2__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \msr2__data_o $1\msr2__data_o[63:0] + end + attribute \src "libresoc.v:166589.14-166589.42" + process $proc$libresoc.v:166589$10797 + assign { } { } + assign $1\reg[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \reg $1\reg[63:0] + end + attribute \src "libresoc.v:166598.3-166599.25" + process $proc$libresoc.v:166598$10762 + assign { } { } + assign $0\reg[63:0] \reg$next + sync posedge \coresync_clk + update \reg $0\reg[63:0] + end + attribute \src "libresoc.v:166600.3-166601.41" + process $proc$libresoc.v:166600$10763 + assign { } { } + assign $0\msr2__data_o[63:0] \msr2__data_o$next + sync posedge \coresync_clk + update \msr2__data_o $0\msr2__data_o[63:0] + end + attribute \src "libresoc.v:166602.3-166603.41" + process $proc$libresoc.v:166602$10764 + assign { } { } + assign $0\cia2__data_o[63:0] \cia2__data_o$next + sync posedge \coresync_clk + update \cia2__data_o $0\cia2__data_o[63:0] + end + attribute \src "libresoc.v:166604.3-166643.6" + process $proc$libresoc.v:166604$10765 + assign { } { } + assign { } { } + assign { } { } + assign $0\cia2__data_o$next[63:0]$10766 $6\cia2__data_o$next[63:0]$10772 + attribute \src "libresoc.v:166605.5-166605.29" + switch \initial + attribute \src "libresoc.v:166605.9-166605.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \cia2__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\cia2__data_o$next[63:0]$10767 $5\cia2__data_o$next[63:0]$10771 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \nia2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cia2__data_o$next[63:0]$10768 \nia2__data_i + case + assign $2\cia2__data_o$next[63:0]$10768 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \msr2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\cia2__data_o$next[63:0]$10769 \msr2__data_i + case + assign $3\cia2__data_o$next[63:0]$10769 $2\cia2__data_o$next[63:0]$10768 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \d_wr12__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\cia2__data_o$next[63:0]$10770 \d_wr12__data_i + case + assign $4\cia2__data_o$next[63:0]$10770 $3\cia2__data_o$next[63:0]$10769 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\cia2__data_o$next[63:0]$10771 \reg + case + assign $5\cia2__data_o$next[63:0]$10771 $4\cia2__data_o$next[63:0]$10770 + end + case + assign $1\cia2__data_o$next[63:0]$10767 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\cia2__data_o$next[63:0]$10772 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $6\cia2__data_o$next[63:0]$10772 $1\cia2__data_o$next[63:0]$10767 + end + sync always + update \cia2__data_o$next $0\cia2__data_o$next[63:0]$10766 + end + attribute \src "libresoc.v:166644.3-166673.6" + process $proc$libresoc.v:166644$10773 + assign { } { } + assign { } { } + assign $0\wr_detect[0:0] $1\wr_detect[0:0] + attribute \src "libresoc.v:166645.5-166645.29" + switch \initial + attribute \src "libresoc.v:166645.9-166645.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \cia2__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect[0:0] $4\wr_detect[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \nia2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect[0:0] 1'1 + case + assign $2\wr_detect[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \msr2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect[0:0] 1'1 + case + assign $3\wr_detect[0:0] $2\wr_detect[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \d_wr12__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect[0:0] 1'1 + case + assign $4\wr_detect[0:0] $3\wr_detect[0:0] + end + case + assign $1\wr_detect[0:0] 1'0 + end + sync always + update \wr_detect $0\wr_detect[0:0] + end + attribute \src "libresoc.v:166674.3-166713.6" + process $proc$libresoc.v:166674$10774 + assign { } { } + assign { } { } + assign { } { } + assign $0\msr2__data_o$next[63:0]$10775 $6\msr2__data_o$next[63:0]$10781 + attribute \src "libresoc.v:166675.5-166675.29" + switch \initial + attribute \src "libresoc.v:166675.9-166675.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \msr2__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\msr2__data_o$next[63:0]$10776 $5\msr2__data_o$next[63:0]$10780 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \nia2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\msr2__data_o$next[63:0]$10777 \nia2__data_i + case + assign $2\msr2__data_o$next[63:0]$10777 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \msr2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\msr2__data_o$next[63:0]$10778 \msr2__data_i + case + assign $3\msr2__data_o$next[63:0]$10778 $2\msr2__data_o$next[63:0]$10777 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \d_wr12__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\msr2__data_o$next[63:0]$10779 \d_wr12__data_i + case + assign $4\msr2__data_o$next[63:0]$10779 $3\msr2__data_o$next[63:0]$10778 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\msr2__data_o$next[63:0]$10780 \reg + case + assign $5\msr2__data_o$next[63:0]$10780 $4\msr2__data_o$next[63:0]$10779 + end + case + assign $1\msr2__data_o$next[63:0]$10776 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\msr2__data_o$next[63:0]$10781 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $6\msr2__data_o$next[63:0]$10781 $1\msr2__data_o$next[63:0]$10776 + end + sync always + update \msr2__data_o$next $0\msr2__data_o$next[63:0]$10775 + end + attribute \src "libresoc.v:166714.3-166743.6" + process $proc$libresoc.v:166714$10782 + assign { } { } + assign { } { } + assign $0\wr_detect$4[0:0]$10783 $1\wr_detect$4[0:0]$10784 + attribute \src "libresoc.v:166715.5-166715.29" + switch \initial + attribute \src "libresoc.v:166715.9-166715.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \msr2__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$4[0:0]$10784 $4\wr_detect$4[0:0]$10787 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \nia2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$4[0:0]$10785 1'1 + case + assign $2\wr_detect$4[0:0]$10785 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \msr2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$4[0:0]$10786 1'1 + case + assign $3\wr_detect$4[0:0]$10786 $2\wr_detect$4[0:0]$10785 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \d_wr12__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$4[0:0]$10787 1'1 + case + assign $4\wr_detect$4[0:0]$10787 $3\wr_detect$4[0:0]$10786 + end + case + assign $1\wr_detect$4[0:0]$10784 1'0 + end + sync always + update \wr_detect$4 $0\wr_detect$4[0:0]$10783 + end + attribute \src "libresoc.v:166744.3-166770.6" + process $proc$libresoc.v:166744$10788 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\reg$next[63:0]$10789 $4\reg$next[63:0]$10793 + attribute \src "libresoc.v:166745.5-166745.29" + switch \initial + attribute \src "libresoc.v:166745.9-166745.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \nia2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\reg$next[63:0]$10790 \nia2__data_i + case + assign $1\reg$next[63:0]$10790 \reg + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \msr2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\reg$next[63:0]$10791 \msr2__data_i + case + assign $2\reg$next[63:0]$10791 $1\reg$next[63:0]$10790 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \d_wr12__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\reg$next[63:0]$10792 \d_wr12__data_i + case + assign $3\reg$next[63:0]$10792 $2\reg$next[63:0]$10791 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\reg$next[63:0]$10793 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $4\reg$next[63:0]$10793 $3\reg$next[63:0]$10792 + end + sync always + update \reg$next $0\reg$next[63:0]$10789 + end + connect \$1 $not$libresoc.v:166596$10760_Y + connect \$3 $not$libresoc.v:166597$10761_Y +end +attribute \src "libresoc.v:166775.1-167246.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.cr.reg_3" +attribute \generator "nMigen" +module \reg_3 + attribute \src "libresoc.v:166776.7-166776.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:167176.3-167215.6" + wire width 4 $0\r23__data_o$next[3:0]$10867 + attribute \src "libresoc.v:166859.3-166860.39" + wire width 4 $0\r23__data_o[3:0] + attribute \src "libresoc.v:167106.3-167145.6" + wire width 4 $0\r3__data_o$next[3:0]$10853 + attribute \src "libresoc.v:166861.3-166862.37" + wire width 4 $0\r3__data_o[3:0] + attribute \src "libresoc.v:166939.3-166965.6" + wire width 4 $0\reg$next[3:0]$10819 + attribute \src "libresoc.v:166857.3-166858.25" + wire width 4 $0\reg[3:0] + attribute \src "libresoc.v:166869.3-166908.6" + wire width 4 $0\src13__data_o$next[3:0]$10810 + attribute \src "libresoc.v:166867.3-166868.43" + wire width 4 $0\src13__data_o[3:0] + attribute \src "libresoc.v:166966.3-167005.6" + wire width 4 $0\src23__data_o$next[3:0]$10825 + attribute \src "libresoc.v:166865.3-166866.43" + wire width 4 $0\src23__data_o[3:0] + attribute \src "libresoc.v:167036.3-167075.6" + wire width 4 $0\src33__data_o$next[3:0]$10839 + attribute \src "libresoc.v:166863.3-166864.43" + wire width 4 $0\src33__data_o[3:0] + attribute \src "libresoc.v:167146.3-167175.6" + wire $0\wr_detect$10[0:0]$10861 + attribute \src "libresoc.v:167216.3-167245.6" + wire $0\wr_detect$13[0:0]$10875 + attribute \src "libresoc.v:167006.3-167035.6" + wire $0\wr_detect$4[0:0]$10833 + attribute \src "libresoc.v:167076.3-167105.6" + wire $0\wr_detect$7[0:0]$10847 + attribute \src "libresoc.v:166909.3-166938.6" + wire $0\wr_detect[0:0] + attribute \src "libresoc.v:167176.3-167215.6" + wire width 4 $1\r23__data_o$next[3:0]$10868 + attribute \src "libresoc.v:166801.13-166801.31" + wire width 4 $1\r23__data_o[3:0] + attribute \src "libresoc.v:167106.3-167145.6" + wire width 4 $1\r3__data_o$next[3:0]$10854 + attribute \src "libresoc.v:166808.13-166808.30" + wire width 4 $1\r3__data_o[3:0] + attribute \src "libresoc.v:166939.3-166965.6" + wire width 4 $1\reg$next[3:0]$10820 + attribute \src "libresoc.v:166814.13-166814.25" + wire width 4 $1\reg[3:0] + attribute \src "libresoc.v:166869.3-166908.6" + wire width 4 $1\src13__data_o$next[3:0]$10811 + attribute \src "libresoc.v:166819.13-166819.33" + wire width 4 $1\src13__data_o[3:0] + attribute \src "libresoc.v:166966.3-167005.6" + wire width 4 $1\src23__data_o$next[3:0]$10826 + attribute \src "libresoc.v:166826.13-166826.33" + wire width 4 $1\src23__data_o[3:0] + attribute \src "libresoc.v:167036.3-167075.6" + wire width 4 $1\src33__data_o$next[3:0]$10840 + attribute \src "libresoc.v:166833.13-166833.33" + wire width 4 $1\src33__data_o[3:0] + attribute \src "libresoc.v:167146.3-167175.6" + wire $1\wr_detect$10[0:0]$10862 + attribute \src "libresoc.v:167216.3-167245.6" + wire $1\wr_detect$13[0:0]$10876 + attribute \src "libresoc.v:167006.3-167035.6" + wire $1\wr_detect$4[0:0]$10834 + attribute \src "libresoc.v:167076.3-167105.6" + wire $1\wr_detect$7[0:0]$10848 + attribute \src "libresoc.v:166909.3-166938.6" + wire $1\wr_detect[0:0] + attribute \src "libresoc.v:167176.3-167215.6" + wire width 4 $2\r23__data_o$next[3:0]$10869 + attribute \src "libresoc.v:167106.3-167145.6" + wire width 4 $2\r3__data_o$next[3:0]$10855 + attribute \src "libresoc.v:166939.3-166965.6" + wire width 4 $2\reg$next[3:0]$10821 + attribute \src "libresoc.v:166869.3-166908.6" + wire width 4 $2\src13__data_o$next[3:0]$10812 + attribute \src "libresoc.v:166966.3-167005.6" + wire width 4 $2\src23__data_o$next[3:0]$10827 + attribute \src "libresoc.v:167036.3-167075.6" + wire width 4 $2\src33__data_o$next[3:0]$10841 + attribute \src "libresoc.v:167146.3-167175.6" + wire $2\wr_detect$10[0:0]$10863 + attribute \src "libresoc.v:167216.3-167245.6" + wire $2\wr_detect$13[0:0]$10877 + attribute \src "libresoc.v:167006.3-167035.6" + wire $2\wr_detect$4[0:0]$10835 + attribute \src "libresoc.v:167076.3-167105.6" + wire $2\wr_detect$7[0:0]$10849 + attribute \src "libresoc.v:166909.3-166938.6" + wire $2\wr_detect[0:0] + attribute \src "libresoc.v:167176.3-167215.6" + wire width 4 $3\r23__data_o$next[3:0]$10870 + attribute \src "libresoc.v:167106.3-167145.6" + wire width 4 $3\r3__data_o$next[3:0]$10856 + attribute \src "libresoc.v:166939.3-166965.6" + wire width 4 $3\reg$next[3:0]$10822 + attribute \src "libresoc.v:166869.3-166908.6" + wire width 4 $3\src13__data_o$next[3:0]$10813 + attribute \src "libresoc.v:166966.3-167005.6" + wire width 4 $3\src23__data_o$next[3:0]$10828 + attribute \src "libresoc.v:167036.3-167075.6" + wire width 4 $3\src33__data_o$next[3:0]$10842 + attribute \src "libresoc.v:167146.3-167175.6" + wire $3\wr_detect$10[0:0]$10864 + attribute \src "libresoc.v:167216.3-167245.6" + wire $3\wr_detect$13[0:0]$10878 + attribute \src "libresoc.v:167006.3-167035.6" + wire $3\wr_detect$4[0:0]$10836 + attribute \src "libresoc.v:167076.3-167105.6" + wire $3\wr_detect$7[0:0]$10850 + attribute \src "libresoc.v:166909.3-166938.6" + wire $3\wr_detect[0:0] + attribute \src "libresoc.v:167176.3-167215.6" + wire width 4 $4\r23__data_o$next[3:0]$10871 + attribute \src "libresoc.v:167106.3-167145.6" + wire width 4 $4\r3__data_o$next[3:0]$10857 + attribute \src "libresoc.v:166939.3-166965.6" + wire width 4 $4\reg$next[3:0]$10823 + attribute \src "libresoc.v:166869.3-166908.6" + wire width 4 $4\src13__data_o$next[3:0]$10814 + attribute \src "libresoc.v:166966.3-167005.6" + wire width 4 $4\src23__data_o$next[3:0]$10829 + attribute \src "libresoc.v:167036.3-167075.6" + wire width 4 $4\src33__data_o$next[3:0]$10843 + attribute \src "libresoc.v:167146.3-167175.6" + wire $4\wr_detect$10[0:0]$10865 + attribute \src "libresoc.v:167216.3-167245.6" + wire $4\wr_detect$13[0:0]$10879 + attribute \src "libresoc.v:167006.3-167035.6" + wire $4\wr_detect$4[0:0]$10837 + attribute \src "libresoc.v:167076.3-167105.6" + wire $4\wr_detect$7[0:0]$10851 + attribute \src "libresoc.v:166909.3-166938.6" + wire $4\wr_detect[0:0] + attribute \src "libresoc.v:167176.3-167215.6" + wire width 4 $5\r23__data_o$next[3:0]$10872 + attribute \src "libresoc.v:167106.3-167145.6" + wire width 4 $5\r3__data_o$next[3:0]$10858 + attribute \src "libresoc.v:166869.3-166908.6" + wire width 4 $5\src13__data_o$next[3:0]$10815 + attribute \src "libresoc.v:166966.3-167005.6" + wire width 4 $5\src23__data_o$next[3:0]$10830 + attribute \src "libresoc.v:167036.3-167075.6" + wire width 4 $5\src33__data_o$next[3:0]$10844 + attribute \src "libresoc.v:167176.3-167215.6" + wire width 4 $6\r23__data_o$next[3:0]$10873 + attribute \src "libresoc.v:167106.3-167145.6" + wire width 4 $6\r3__data_o$next[3:0]$10859 + attribute \src "libresoc.v:166869.3-166908.6" + wire width 4 $6\src13__data_o$next[3:0]$10816 + attribute \src "libresoc.v:166966.3-167005.6" + wire width 4 $6\src23__data_o$next[3:0]$10831 + attribute \src "libresoc.v:167036.3-167075.6" + wire width 4 $6\src33__data_o$next[3:0]$10845 + attribute \src "libresoc.v:166852.17-166852.104" + wire $not$libresoc.v:166852$10798_Y + attribute \src "libresoc.v:166853.18-166853.105" + wire $not$libresoc.v:166853$10799_Y + attribute \src "libresoc.v:166854.17-166854.100" + wire $not$libresoc.v:166854$10800_Y + attribute \src "libresoc.v:166855.17-166855.103" + wire $not$libresoc.v:166855$10801_Y + attribute \src "libresoc.v:166856.17-166856.103" + wire $not$libresoc.v:166856$10802_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 18 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 input 9 \dest13__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 8 \dest13__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 input 11 \dest23__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 10 \dest23__wen + attribute \src "libresoc.v:166776.7-166776.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 14 \r23__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \r23__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 15 \r23__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 12 \r3__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \r3__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 13 \r3__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 4 \reg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 4 \reg$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 3 \src13__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \src13__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 2 \src13__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 5 \src23__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \src23__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 4 \src23__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 7 \src33__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \src33__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 6 \src33__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 input 16 \w3__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 17 \w3__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:166852$10798 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$10 + connect \Y $not$libresoc.v:166852$10798_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:166853$10799 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$13 + connect \Y $not$libresoc.v:166853$10799_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:166854$10800 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect + connect \Y $not$libresoc.v:166854$10800_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:166855$10801 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$4 + connect \Y $not$libresoc.v:166855$10801_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:166856$10802 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$7 + connect \Y $not$libresoc.v:166856$10802_Y + end + attribute \src "libresoc.v:166776.7-166776.20" + process $proc$libresoc.v:166776$10880 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:166801.13-166801.31" + process $proc$libresoc.v:166801$10881 + assign { } { } + assign $1\r23__data_o[3:0] 4'0000 + sync always + sync init + update \r23__data_o $1\r23__data_o[3:0] + end + attribute \src "libresoc.v:166808.13-166808.30" + process $proc$libresoc.v:166808$10882 + assign { } { } + assign $1\r3__data_o[3:0] 4'0000 + sync always + sync init + update \r3__data_o $1\r3__data_o[3:0] + end + attribute \src "libresoc.v:166814.13-166814.25" + process $proc$libresoc.v:166814$10883 + assign { } { } + assign $1\reg[3:0] 4'0000 + sync always + sync init + update \reg $1\reg[3:0] + end + attribute \src "libresoc.v:166819.13-166819.33" + process $proc$libresoc.v:166819$10884 + assign { } { } + assign $1\src13__data_o[3:0] 4'0000 + sync always + sync init + update \src13__data_o $1\src13__data_o[3:0] + end + attribute \src "libresoc.v:166826.13-166826.33" + process $proc$libresoc.v:166826$10885 + assign { } { } + assign $1\src23__data_o[3:0] 4'0000 + sync always + sync init + update \src23__data_o $1\src23__data_o[3:0] + end + attribute \src "libresoc.v:166833.13-166833.33" + process $proc$libresoc.v:166833$10886 + assign { } { } + assign $1\src33__data_o[3:0] 4'0000 + sync always + sync init + update \src33__data_o $1\src33__data_o[3:0] + end + attribute \src "libresoc.v:166857.3-166858.25" + process $proc$libresoc.v:166857$10803 + assign { } { } + assign $0\reg[3:0] \reg$next + sync posedge \coresync_clk + update \reg $0\reg[3:0] + end + attribute \src "libresoc.v:166859.3-166860.39" + process $proc$libresoc.v:166859$10804 + assign { } { } + assign $0\r23__data_o[3:0] \r23__data_o$next + sync posedge \coresync_clk + update \r23__data_o $0\r23__data_o[3:0] + end + attribute \src "libresoc.v:166861.3-166862.37" + process $proc$libresoc.v:166861$10805 + assign { } { } + assign $0\r3__data_o[3:0] \r3__data_o$next + sync posedge \coresync_clk + update \r3__data_o $0\r3__data_o[3:0] + end + attribute \src "libresoc.v:166863.3-166864.43" + process $proc$libresoc.v:166863$10806 + assign { } { } + assign $0\src33__data_o[3:0] \src33__data_o$next + sync posedge \coresync_clk + update \src33__data_o $0\src33__data_o[3:0] + end + attribute \src "libresoc.v:166865.3-166866.43" + process $proc$libresoc.v:166865$10807 + assign { } { } + assign $0\src23__data_o[3:0] \src23__data_o$next + sync posedge \coresync_clk + update \src23__data_o $0\src23__data_o[3:0] + end + attribute \src "libresoc.v:166867.3-166868.43" + process $proc$libresoc.v:166867$10808 + assign { } { } + assign $0\src13__data_o[3:0] \src13__data_o$next + sync posedge \coresync_clk + update \src13__data_o $0\src13__data_o[3:0] + end + attribute \src "libresoc.v:166869.3-166908.6" + process $proc$libresoc.v:166869$10809 + assign { } { } + assign { } { } + assign { } { } + assign $0\src13__data_o$next[3:0]$10810 $6\src13__data_o$next[3:0]$10816 + attribute \src "libresoc.v:166870.5-166870.29" + switch \initial + attribute \src "libresoc.v:166870.9-166870.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src13__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src13__data_o$next[3:0]$10811 $5\src13__data_o$next[3:0]$10815 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest13__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src13__data_o$next[3:0]$10812 \dest13__data_i + case + assign $2\src13__data_o$next[3:0]$10812 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest23__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src13__data_o$next[3:0]$10813 \dest23__data_i + case + assign $3\src13__data_o$next[3:0]$10813 $2\src13__data_o$next[3:0]$10812 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w3__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src13__data_o$next[3:0]$10814 \w3__data_i + case + assign $4\src13__data_o$next[3:0]$10814 $3\src13__data_o$next[3:0]$10813 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src13__data_o$next[3:0]$10815 \reg + case + assign $5\src13__data_o$next[3:0]$10815 $4\src13__data_o$next[3:0]$10814 + end + case + assign $1\src13__data_o$next[3:0]$10811 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src13__data_o$next[3:0]$10816 4'0000 + case + assign $6\src13__data_o$next[3:0]$10816 $1\src13__data_o$next[3:0]$10811 + end + sync always + update \src13__data_o$next $0\src13__data_o$next[3:0]$10810 + end + attribute \src "libresoc.v:166909.3-166938.6" + process $proc$libresoc.v:166909$10817 + assign { } { } + assign { } { } + assign $0\wr_detect[0:0] $1\wr_detect[0:0] + attribute \src "libresoc.v:166910.5-166910.29" + switch \initial + attribute \src "libresoc.v:166910.9-166910.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src13__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect[0:0] $4\wr_detect[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest13__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect[0:0] 1'1 + case + assign $2\wr_detect[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest23__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect[0:0] 1'1 + case + assign $3\wr_detect[0:0] $2\wr_detect[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w3__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect[0:0] 1'1 + case + assign $4\wr_detect[0:0] $3\wr_detect[0:0] + end + case + assign $1\wr_detect[0:0] 1'0 + end + sync always + update \wr_detect $0\wr_detect[0:0] + end + attribute \src "libresoc.v:166939.3-166965.6" + process $proc$libresoc.v:166939$10818 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\reg$next[3:0]$10819 $4\reg$next[3:0]$10823 + attribute \src "libresoc.v:166940.5-166940.29" + switch \initial + attribute \src "libresoc.v:166940.9-166940.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest13__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\reg$next[3:0]$10820 \dest13__data_i + case + assign $1\reg$next[3:0]$10820 \reg + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest23__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\reg$next[3:0]$10821 \dest23__data_i + case + assign $2\reg$next[3:0]$10821 $1\reg$next[3:0]$10820 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \w3__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\reg$next[3:0]$10822 \w3__data_i + case + assign $3\reg$next[3:0]$10822 $2\reg$next[3:0]$10821 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\reg$next[3:0]$10823 4'0000 + case + assign $4\reg$next[3:0]$10823 $3\reg$next[3:0]$10822 + end + sync always + update \reg$next $0\reg$next[3:0]$10819 + end + attribute \src "libresoc.v:166966.3-167005.6" + process $proc$libresoc.v:166966$10824 + assign { } { } + assign { } { } + assign { } { } + assign $0\src23__data_o$next[3:0]$10825 $6\src23__data_o$next[3:0]$10831 + attribute \src "libresoc.v:166967.5-166967.29" + switch \initial + attribute \src "libresoc.v:166967.9-166967.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src23__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src23__data_o$next[3:0]$10826 $5\src23__data_o$next[3:0]$10830 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest13__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src23__data_o$next[3:0]$10827 \dest13__data_i + case + assign $2\src23__data_o$next[3:0]$10827 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest23__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src23__data_o$next[3:0]$10828 \dest23__data_i + case + assign $3\src23__data_o$next[3:0]$10828 $2\src23__data_o$next[3:0]$10827 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w3__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src23__data_o$next[3:0]$10829 \w3__data_i + case + assign $4\src23__data_o$next[3:0]$10829 $3\src23__data_o$next[3:0]$10828 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src23__data_o$next[3:0]$10830 \reg + case + assign $5\src23__data_o$next[3:0]$10830 $4\src23__data_o$next[3:0]$10829 + end + case + assign $1\src23__data_o$next[3:0]$10826 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src23__data_o$next[3:0]$10831 4'0000 + case + assign $6\src23__data_o$next[3:0]$10831 $1\src23__data_o$next[3:0]$10826 + end + sync always + update \src23__data_o$next $0\src23__data_o$next[3:0]$10825 + end + attribute \src "libresoc.v:167006.3-167035.6" + process $proc$libresoc.v:167006$10832 + assign { } { } + assign { } { } + assign $0\wr_detect$4[0:0]$10833 $1\wr_detect$4[0:0]$10834 + attribute \src "libresoc.v:167007.5-167007.29" + switch \initial + attribute \src "libresoc.v:167007.9-167007.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src23__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$4[0:0]$10834 $4\wr_detect$4[0:0]$10837 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest13__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$4[0:0]$10835 1'1 + case + assign $2\wr_detect$4[0:0]$10835 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest23__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$4[0:0]$10836 1'1 + case + assign $3\wr_detect$4[0:0]$10836 $2\wr_detect$4[0:0]$10835 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w3__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$4[0:0]$10837 1'1 + case + assign $4\wr_detect$4[0:0]$10837 $3\wr_detect$4[0:0]$10836 + end + case + assign $1\wr_detect$4[0:0]$10834 1'0 + end + sync always + update \wr_detect$4 $0\wr_detect$4[0:0]$10833 + end + attribute \src "libresoc.v:167036.3-167075.6" + process $proc$libresoc.v:167036$10838 + assign { } { } + assign { } { } + assign { } { } + assign $0\src33__data_o$next[3:0]$10839 $6\src33__data_o$next[3:0]$10845 + attribute \src "libresoc.v:167037.5-167037.29" + switch \initial + attribute \src "libresoc.v:167037.9-167037.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src33__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src33__data_o$next[3:0]$10840 $5\src33__data_o$next[3:0]$10844 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest13__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src33__data_o$next[3:0]$10841 \dest13__data_i + case + assign $2\src33__data_o$next[3:0]$10841 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest23__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src33__data_o$next[3:0]$10842 \dest23__data_i + case + assign $3\src33__data_o$next[3:0]$10842 $2\src33__data_o$next[3:0]$10841 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w3__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src33__data_o$next[3:0]$10843 \w3__data_i + case + assign $4\src33__data_o$next[3:0]$10843 $3\src33__data_o$next[3:0]$10842 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$6 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src33__data_o$next[3:0]$10844 \reg + case + assign $5\src33__data_o$next[3:0]$10844 $4\src33__data_o$next[3:0]$10843 + end + case + assign $1\src33__data_o$next[3:0]$10840 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src33__data_o$next[3:0]$10845 4'0000 + case + assign $6\src33__data_o$next[3:0]$10845 $1\src33__data_o$next[3:0]$10840 + end + sync always + update \src33__data_o$next $0\src33__data_o$next[3:0]$10839 + end + attribute \src "libresoc.v:167076.3-167105.6" + process $proc$libresoc.v:167076$10846 + assign { } { } + assign { } { } + assign $0\wr_detect$7[0:0]$10847 $1\wr_detect$7[0:0]$10848 + attribute \src "libresoc.v:167077.5-167077.29" + switch \initial + attribute \src "libresoc.v:167077.9-167077.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src33__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$7[0:0]$10848 $4\wr_detect$7[0:0]$10851 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest13__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$7[0:0]$10849 1'1 + case + assign $2\wr_detect$7[0:0]$10849 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest23__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$7[0:0]$10850 1'1 + case + assign $3\wr_detect$7[0:0]$10850 $2\wr_detect$7[0:0]$10849 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w3__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$7[0:0]$10851 1'1 + case + assign $4\wr_detect$7[0:0]$10851 $3\wr_detect$7[0:0]$10850 + end + case + assign $1\wr_detect$7[0:0]$10848 1'0 + end + sync always + update \wr_detect$7 $0\wr_detect$7[0:0]$10847 + end + attribute \src "libresoc.v:167106.3-167145.6" + process $proc$libresoc.v:167106$10852 + assign { } { } + assign { } { } + assign { } { } + assign $0\r3__data_o$next[3:0]$10853 $6\r3__data_o$next[3:0]$10859 + attribute \src "libresoc.v:167107.5-167107.29" + switch \initial + attribute \src "libresoc.v:167107.9-167107.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r3__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\r3__data_o$next[3:0]$10854 $5\r3__data_o$next[3:0]$10858 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest13__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r3__data_o$next[3:0]$10855 \dest13__data_i + case + assign $2\r3__data_o$next[3:0]$10855 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest23__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\r3__data_o$next[3:0]$10856 \dest23__data_i + case + assign $3\r3__data_o$next[3:0]$10856 $2\r3__data_o$next[3:0]$10855 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w3__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\r3__data_o$next[3:0]$10857 \w3__data_i + case + assign $4\r3__data_o$next[3:0]$10857 $3\r3__data_o$next[3:0]$10856 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$9 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\r3__data_o$next[3:0]$10858 \reg + case + assign $5\r3__data_o$next[3:0]$10858 $4\r3__data_o$next[3:0]$10857 + end + case + assign $1\r3__data_o$next[3:0]$10854 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\r3__data_o$next[3:0]$10859 4'0000 + case + assign $6\r3__data_o$next[3:0]$10859 $1\r3__data_o$next[3:0]$10854 + end + sync always + update \r3__data_o$next $0\r3__data_o$next[3:0]$10853 + end + attribute \src "libresoc.v:167146.3-167175.6" + process $proc$libresoc.v:167146$10860 + assign { } { } + assign { } { } + assign $0\wr_detect$10[0:0]$10861 $1\wr_detect$10[0:0]$10862 + attribute \src "libresoc.v:167147.5-167147.29" + switch \initial + attribute \src "libresoc.v:167147.9-167147.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r3__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$10[0:0]$10862 $4\wr_detect$10[0:0]$10865 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest13__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$10[0:0]$10863 1'1 + case + assign $2\wr_detect$10[0:0]$10863 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest23__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$10[0:0]$10864 1'1 + case + assign $3\wr_detect$10[0:0]$10864 $2\wr_detect$10[0:0]$10863 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w3__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$10[0:0]$10865 1'1 + case + assign $4\wr_detect$10[0:0]$10865 $3\wr_detect$10[0:0]$10864 + end + case + assign $1\wr_detect$10[0:0]$10862 1'0 + end + sync always + update \wr_detect$10 $0\wr_detect$10[0:0]$10861 + end + attribute \src "libresoc.v:167176.3-167215.6" + process $proc$libresoc.v:167176$10866 + assign { } { } + assign { } { } + assign { } { } + assign $0\r23__data_o$next[3:0]$10867 $6\r23__data_o$next[3:0]$10873 + attribute \src "libresoc.v:167177.5-167177.29" + switch \initial + attribute \src "libresoc.v:167177.9-167177.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r23__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\r23__data_o$next[3:0]$10868 $5\r23__data_o$next[3:0]$10872 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest13__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r23__data_o$next[3:0]$10869 \dest13__data_i + case + assign $2\r23__data_o$next[3:0]$10869 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest23__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\r23__data_o$next[3:0]$10870 \dest23__data_i + case + assign $3\r23__data_o$next[3:0]$10870 $2\r23__data_o$next[3:0]$10869 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w3__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\r23__data_o$next[3:0]$10871 \w3__data_i + case + assign $4\r23__data_o$next[3:0]$10871 $3\r23__data_o$next[3:0]$10870 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$12 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\r23__data_o$next[3:0]$10872 \reg + case + assign $5\r23__data_o$next[3:0]$10872 $4\r23__data_o$next[3:0]$10871 + end + case + assign $1\r23__data_o$next[3:0]$10868 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\r23__data_o$next[3:0]$10873 4'0000 + case + assign $6\r23__data_o$next[3:0]$10873 $1\r23__data_o$next[3:0]$10868 + end + sync always + update \r23__data_o$next $0\r23__data_o$next[3:0]$10867 + end + attribute \src "libresoc.v:167216.3-167245.6" + process $proc$libresoc.v:167216$10874 + assign { } { } + assign { } { } + assign $0\wr_detect$13[0:0]$10875 $1\wr_detect$13[0:0]$10876 + attribute \src "libresoc.v:167217.5-167217.29" + switch \initial + attribute \src "libresoc.v:167217.9-167217.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r23__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$13[0:0]$10876 $4\wr_detect$13[0:0]$10879 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest13__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$13[0:0]$10877 1'1 + case + assign $2\wr_detect$13[0:0]$10877 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest23__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$13[0:0]$10878 1'1 + case + assign $3\wr_detect$13[0:0]$10878 $2\wr_detect$13[0:0]$10877 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w3__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$13[0:0]$10879 1'1 + case + assign $4\wr_detect$13[0:0]$10879 $3\wr_detect$13[0:0]$10878 + end + case + assign $1\wr_detect$13[0:0]$10876 1'0 + end + sync always + update \wr_detect$13 $0\wr_detect$13[0:0]$10875 + end + connect \$9 $not$libresoc.v:166852$10798_Y + connect \$12 $not$libresoc.v:166853$10799_Y + connect \$1 $not$libresoc.v:166854$10800_Y + connect \$3 $not$libresoc.v:166855$10801_Y + connect \$6 $not$libresoc.v:166856$10802_Y +end +attribute \src "libresoc.v:167250.1-167469.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.state.reg_3" +attribute \generator "nMigen" +module \reg_3$135 + attribute \src "libresoc.v:167302.3-167341.6" + wire width 64 $0\cia3__data_o$next[63:0]$10893 + attribute \src "libresoc.v:167300.3-167301.41" + wire width 64 $0\cia3__data_o[63:0] + attribute \src "libresoc.v:167251.7-167251.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:167372.3-167411.6" + wire width 64 $0\msr3__data_o$next[63:0]$10902 + attribute \src "libresoc.v:167298.3-167299.41" + wire width 64 $0\msr3__data_o[63:0] + attribute \src "libresoc.v:167442.3-167468.6" + wire width 64 $0\reg$next[63:0]$10916 + attribute \src "libresoc.v:167296.3-167297.25" + wire width 64 $0\reg[63:0] + attribute \src "libresoc.v:167412.3-167441.6" + wire $0\wr_detect$4[0:0]$10910 + attribute \src "libresoc.v:167342.3-167371.6" + wire $0\wr_detect[0:0] + attribute \src "libresoc.v:167302.3-167341.6" + wire width 64 $1\cia3__data_o$next[63:0]$10894 + attribute \src "libresoc.v:167258.14-167258.49" + wire width 64 $1\cia3__data_o[63:0] + attribute \src "libresoc.v:167372.3-167411.6" + wire width 64 $1\msr3__data_o$next[63:0]$10903 + attribute \src "libresoc.v:167275.14-167275.49" + wire width 64 $1\msr3__data_o[63:0] + attribute \src "libresoc.v:167442.3-167468.6" + wire width 64 $1\reg$next[63:0]$10917 + attribute \src "libresoc.v:167287.14-167287.42" + wire width 64 $1\reg[63:0] + attribute \src "libresoc.v:167412.3-167441.6" + wire $1\wr_detect$4[0:0]$10911 + attribute \src "libresoc.v:167342.3-167371.6" + wire $1\wr_detect[0:0] + attribute \src "libresoc.v:167302.3-167341.6" + wire width 64 $2\cia3__data_o$next[63:0]$10895 + attribute \src "libresoc.v:167372.3-167411.6" + wire width 64 $2\msr3__data_o$next[63:0]$10904 + attribute \src "libresoc.v:167442.3-167468.6" + wire width 64 $2\reg$next[63:0]$10918 + attribute \src "libresoc.v:167412.3-167441.6" + wire $2\wr_detect$4[0:0]$10912 + attribute \src "libresoc.v:167342.3-167371.6" + wire $2\wr_detect[0:0] + attribute \src "libresoc.v:167302.3-167341.6" + wire width 64 $3\cia3__data_o$next[63:0]$10896 + attribute \src "libresoc.v:167372.3-167411.6" + wire width 64 $3\msr3__data_o$next[63:0]$10905 + attribute \src "libresoc.v:167442.3-167468.6" + wire width 64 $3\reg$next[63:0]$10919 + attribute \src "libresoc.v:167412.3-167441.6" + wire $3\wr_detect$4[0:0]$10913 + attribute \src "libresoc.v:167342.3-167371.6" + wire $3\wr_detect[0:0] + attribute \src "libresoc.v:167302.3-167341.6" + wire width 64 $4\cia3__data_o$next[63:0]$10897 + attribute \src "libresoc.v:167372.3-167411.6" + wire width 64 $4\msr3__data_o$next[63:0]$10906 + attribute \src "libresoc.v:167442.3-167468.6" + wire width 64 $4\reg$next[63:0]$10920 + attribute \src "libresoc.v:167412.3-167441.6" + wire $4\wr_detect$4[0:0]$10914 + attribute \src "libresoc.v:167342.3-167371.6" + wire $4\wr_detect[0:0] + attribute \src "libresoc.v:167302.3-167341.6" + wire width 64 $5\cia3__data_o$next[63:0]$10898 + attribute \src "libresoc.v:167372.3-167411.6" + wire width 64 $5\msr3__data_o$next[63:0]$10907 + attribute \src "libresoc.v:167302.3-167341.6" + wire width 64 $6\cia3__data_o$next[63:0]$10899 + attribute \src "libresoc.v:167372.3-167411.6" + wire width 64 $6\msr3__data_o$next[63:0]$10908 + attribute \src "libresoc.v:167294.17-167294.100" + wire $not$libresoc.v:167294$10887_Y + attribute \src "libresoc.v:167295.17-167295.103" + wire $not$libresoc.v:167295$10888_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 output 3 \cia3__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \cia3__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 2 \cia3__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 12 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 input 11 \d_wr13__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 10 \d_wr13__wen + attribute \src "libresoc.v:167251.7-167251.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 input 9 \msr3__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 output 5 \msr3__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \msr3__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 4 \msr3__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 8 \msr3__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 input 7 \nia3__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 6 \nia3__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 64 \reg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 64 \reg$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:167294$10887 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect + connect \Y $not$libresoc.v:167294$10887_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:167295$10888 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$4 + connect \Y $not$libresoc.v:167295$10888_Y + end + attribute \src "libresoc.v:167251.7-167251.20" + process $proc$libresoc.v:167251$10921 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:167258.14-167258.49" + process $proc$libresoc.v:167258$10922 + assign { } { } + assign $1\cia3__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \cia3__data_o $1\cia3__data_o[63:0] + end + attribute \src "libresoc.v:167275.14-167275.49" + process $proc$libresoc.v:167275$10923 + assign { } { } + assign $1\msr3__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \msr3__data_o $1\msr3__data_o[63:0] + end + attribute \src "libresoc.v:167287.14-167287.42" + process $proc$libresoc.v:167287$10924 + assign { } { } + assign $1\reg[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \reg $1\reg[63:0] + end + attribute \src "libresoc.v:167296.3-167297.25" + process $proc$libresoc.v:167296$10889 + assign { } { } + assign $0\reg[63:0] \reg$next + sync posedge \coresync_clk + update \reg $0\reg[63:0] + end + attribute \src "libresoc.v:167298.3-167299.41" + process $proc$libresoc.v:167298$10890 + assign { } { } + assign $0\msr3__data_o[63:0] \msr3__data_o$next + sync posedge \coresync_clk + update \msr3__data_o $0\msr3__data_o[63:0] + end + attribute \src "libresoc.v:167300.3-167301.41" + process $proc$libresoc.v:167300$10891 + assign { } { } + assign $0\cia3__data_o[63:0] \cia3__data_o$next + sync posedge \coresync_clk + update \cia3__data_o $0\cia3__data_o[63:0] + end + attribute \src "libresoc.v:167302.3-167341.6" + process $proc$libresoc.v:167302$10892 + assign { } { } + assign { } { } + assign { } { } + assign $0\cia3__data_o$next[63:0]$10893 $6\cia3__data_o$next[63:0]$10899 + attribute \src "libresoc.v:167303.5-167303.29" + switch \initial + attribute \src "libresoc.v:167303.9-167303.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \cia3__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\cia3__data_o$next[63:0]$10894 $5\cia3__data_o$next[63:0]$10898 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \nia3__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cia3__data_o$next[63:0]$10895 \nia3__data_i + case + assign $2\cia3__data_o$next[63:0]$10895 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \msr3__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\cia3__data_o$next[63:0]$10896 \msr3__data_i + case + assign $3\cia3__data_o$next[63:0]$10896 $2\cia3__data_o$next[63:0]$10895 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \d_wr13__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\cia3__data_o$next[63:0]$10897 \d_wr13__data_i + case + assign $4\cia3__data_o$next[63:0]$10897 $3\cia3__data_o$next[63:0]$10896 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\cia3__data_o$next[63:0]$10898 \reg + case + assign $5\cia3__data_o$next[63:0]$10898 $4\cia3__data_o$next[63:0]$10897 + end + case + assign $1\cia3__data_o$next[63:0]$10894 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\cia3__data_o$next[63:0]$10899 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $6\cia3__data_o$next[63:0]$10899 $1\cia3__data_o$next[63:0]$10894 + end + sync always + update \cia3__data_o$next $0\cia3__data_o$next[63:0]$10893 + end + attribute \src "libresoc.v:167342.3-167371.6" + process $proc$libresoc.v:167342$10900 + assign { } { } + assign { } { } + assign $0\wr_detect[0:0] $1\wr_detect[0:0] + attribute \src "libresoc.v:167343.5-167343.29" + switch \initial + attribute \src "libresoc.v:167343.9-167343.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \cia3__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect[0:0] $4\wr_detect[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \nia3__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect[0:0] 1'1 + case + assign $2\wr_detect[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \msr3__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect[0:0] 1'1 + case + assign $3\wr_detect[0:0] $2\wr_detect[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \d_wr13__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect[0:0] 1'1 + case + assign $4\wr_detect[0:0] $3\wr_detect[0:0] + end + case + assign $1\wr_detect[0:0] 1'0 + end + sync always + update \wr_detect $0\wr_detect[0:0] + end + attribute \src "libresoc.v:167372.3-167411.6" + process $proc$libresoc.v:167372$10901 + assign { } { } + assign { } { } + assign { } { } + assign $0\msr3__data_o$next[63:0]$10902 $6\msr3__data_o$next[63:0]$10908 + attribute \src "libresoc.v:167373.5-167373.29" + switch \initial + attribute \src "libresoc.v:167373.9-167373.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \msr3__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\msr3__data_o$next[63:0]$10903 $5\msr3__data_o$next[63:0]$10907 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \nia3__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\msr3__data_o$next[63:0]$10904 \nia3__data_i + case + assign $2\msr3__data_o$next[63:0]$10904 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \msr3__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\msr3__data_o$next[63:0]$10905 \msr3__data_i + case + assign $3\msr3__data_o$next[63:0]$10905 $2\msr3__data_o$next[63:0]$10904 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \d_wr13__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\msr3__data_o$next[63:0]$10906 \d_wr13__data_i + case + assign $4\msr3__data_o$next[63:0]$10906 $3\msr3__data_o$next[63:0]$10905 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\msr3__data_o$next[63:0]$10907 \reg + case + assign $5\msr3__data_o$next[63:0]$10907 $4\msr3__data_o$next[63:0]$10906 + end + case + assign $1\msr3__data_o$next[63:0]$10903 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\msr3__data_o$next[63:0]$10908 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $6\msr3__data_o$next[63:0]$10908 $1\msr3__data_o$next[63:0]$10903 + end + sync always + update \msr3__data_o$next $0\msr3__data_o$next[63:0]$10902 + end + attribute \src "libresoc.v:167412.3-167441.6" + process $proc$libresoc.v:167412$10909 + assign { } { } + assign { } { } + assign $0\wr_detect$4[0:0]$10910 $1\wr_detect$4[0:0]$10911 + attribute \src "libresoc.v:167413.5-167413.29" + switch \initial + attribute \src "libresoc.v:167413.9-167413.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \msr3__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$4[0:0]$10911 $4\wr_detect$4[0:0]$10914 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \nia3__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$4[0:0]$10912 1'1 + case + assign $2\wr_detect$4[0:0]$10912 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \msr3__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$4[0:0]$10913 1'1 + case + assign $3\wr_detect$4[0:0]$10913 $2\wr_detect$4[0:0]$10912 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \d_wr13__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$4[0:0]$10914 1'1 + case + assign $4\wr_detect$4[0:0]$10914 $3\wr_detect$4[0:0]$10913 + end + case + assign $1\wr_detect$4[0:0]$10911 1'0 + end + sync always + update \wr_detect$4 $0\wr_detect$4[0:0]$10910 + end + attribute \src "libresoc.v:167442.3-167468.6" + process $proc$libresoc.v:167442$10915 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\reg$next[63:0]$10916 $4\reg$next[63:0]$10920 + attribute \src "libresoc.v:167443.5-167443.29" + switch \initial + attribute \src "libresoc.v:167443.9-167443.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \nia3__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\reg$next[63:0]$10917 \nia3__data_i + case + assign $1\reg$next[63:0]$10917 \reg + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \msr3__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\reg$next[63:0]$10918 \msr3__data_i + case + assign $2\reg$next[63:0]$10918 $1\reg$next[63:0]$10917 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \d_wr13__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\reg$next[63:0]$10919 \d_wr13__data_i + case + assign $3\reg$next[63:0]$10919 $2\reg$next[63:0]$10918 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\reg$next[63:0]$10920 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $4\reg$next[63:0]$10920 $3\reg$next[63:0]$10919 + end + sync always + update \reg$next $0\reg$next[63:0]$10916 + end + connect \$1 $not$libresoc.v:167294$10887_Y + connect \$3 $not$libresoc.v:167295$10888_Y +end +attribute \src "libresoc.v:167473.1-167944.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.cr.reg_4" +attribute \generator "nMigen" +module \reg_4 + attribute \src "libresoc.v:167474.7-167474.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:167874.3-167913.6" + wire width 4 $0\r24__data_o$next[3:0]$10994 + attribute \src "libresoc.v:167557.3-167558.39" + wire width 4 $0\r24__data_o[3:0] + attribute \src "libresoc.v:167804.3-167843.6" + wire width 4 $0\r4__data_o$next[3:0]$10980 + attribute \src "libresoc.v:167559.3-167560.37" + wire width 4 $0\r4__data_o[3:0] + attribute \src "libresoc.v:167637.3-167663.6" + wire width 4 $0\reg$next[3:0]$10946 + attribute \src "libresoc.v:167555.3-167556.25" + wire width 4 $0\reg[3:0] + attribute \src "libresoc.v:167567.3-167606.6" + wire width 4 $0\src14__data_o$next[3:0]$10937 + attribute \src "libresoc.v:167565.3-167566.43" + wire width 4 $0\src14__data_o[3:0] + attribute \src "libresoc.v:167664.3-167703.6" + wire width 4 $0\src24__data_o$next[3:0]$10952 + attribute \src "libresoc.v:167563.3-167564.43" + wire width 4 $0\src24__data_o[3:0] + attribute \src "libresoc.v:167734.3-167773.6" + wire width 4 $0\src34__data_o$next[3:0]$10966 + attribute \src "libresoc.v:167561.3-167562.43" + wire width 4 $0\src34__data_o[3:0] + attribute \src "libresoc.v:167844.3-167873.6" + wire $0\wr_detect$10[0:0]$10988 + attribute \src "libresoc.v:167914.3-167943.6" + wire $0\wr_detect$13[0:0]$11002 + attribute \src "libresoc.v:167704.3-167733.6" + wire $0\wr_detect$4[0:0]$10960 + attribute \src "libresoc.v:167774.3-167803.6" + wire $0\wr_detect$7[0:0]$10974 + attribute \src "libresoc.v:167607.3-167636.6" + wire $0\wr_detect[0:0] + attribute \src "libresoc.v:167874.3-167913.6" + wire width 4 $1\r24__data_o$next[3:0]$10995 + attribute \src "libresoc.v:167499.13-167499.31" + wire width 4 $1\r24__data_o[3:0] + attribute \src "libresoc.v:167804.3-167843.6" + wire width 4 $1\r4__data_o$next[3:0]$10981 + attribute \src "libresoc.v:167506.13-167506.30" + wire width 4 $1\r4__data_o[3:0] + attribute \src "libresoc.v:167637.3-167663.6" + wire width 4 $1\reg$next[3:0]$10947 + attribute \src "libresoc.v:167512.13-167512.25" + wire width 4 $1\reg[3:0] + attribute \src "libresoc.v:167567.3-167606.6" + wire width 4 $1\src14__data_o$next[3:0]$10938 + attribute \src "libresoc.v:167517.13-167517.33" + wire width 4 $1\src14__data_o[3:0] + attribute \src "libresoc.v:167664.3-167703.6" + wire width 4 $1\src24__data_o$next[3:0]$10953 + attribute \src "libresoc.v:167524.13-167524.33" + wire width 4 $1\src24__data_o[3:0] + attribute \src "libresoc.v:167734.3-167773.6" + wire width 4 $1\src34__data_o$next[3:0]$10967 + attribute \src "libresoc.v:167531.13-167531.33" + wire width 4 $1\src34__data_o[3:0] + attribute \src "libresoc.v:167844.3-167873.6" + wire $1\wr_detect$10[0:0]$10989 + attribute \src "libresoc.v:167914.3-167943.6" + wire $1\wr_detect$13[0:0]$11003 + attribute \src "libresoc.v:167704.3-167733.6" + wire $1\wr_detect$4[0:0]$10961 + attribute \src "libresoc.v:167774.3-167803.6" + wire $1\wr_detect$7[0:0]$10975 + attribute \src "libresoc.v:167607.3-167636.6" + wire $1\wr_detect[0:0] + attribute \src "libresoc.v:167874.3-167913.6" + wire width 4 $2\r24__data_o$next[3:0]$10996 + attribute \src "libresoc.v:167804.3-167843.6" + wire width 4 $2\r4__data_o$next[3:0]$10982 + attribute \src "libresoc.v:167637.3-167663.6" + wire width 4 $2\reg$next[3:0]$10948 + attribute \src "libresoc.v:167567.3-167606.6" + wire width 4 $2\src14__data_o$next[3:0]$10939 + attribute \src "libresoc.v:167664.3-167703.6" + wire width 4 $2\src24__data_o$next[3:0]$10954 + attribute \src "libresoc.v:167734.3-167773.6" + wire width 4 $2\src34__data_o$next[3:0]$10968 + attribute \src "libresoc.v:167844.3-167873.6" + wire $2\wr_detect$10[0:0]$10990 + attribute \src "libresoc.v:167914.3-167943.6" + wire $2\wr_detect$13[0:0]$11004 + attribute \src "libresoc.v:167704.3-167733.6" + wire $2\wr_detect$4[0:0]$10962 + attribute \src "libresoc.v:167774.3-167803.6" + wire $2\wr_detect$7[0:0]$10976 + attribute \src "libresoc.v:167607.3-167636.6" + wire $2\wr_detect[0:0] + attribute \src "libresoc.v:167874.3-167913.6" + wire width 4 $3\r24__data_o$next[3:0]$10997 + attribute \src "libresoc.v:167804.3-167843.6" + wire width 4 $3\r4__data_o$next[3:0]$10983 + attribute \src "libresoc.v:167637.3-167663.6" + wire width 4 $3\reg$next[3:0]$10949 + attribute \src "libresoc.v:167567.3-167606.6" + wire width 4 $3\src14__data_o$next[3:0]$10940 + attribute \src "libresoc.v:167664.3-167703.6" + wire width 4 $3\src24__data_o$next[3:0]$10955 + attribute \src "libresoc.v:167734.3-167773.6" + wire width 4 $3\src34__data_o$next[3:0]$10969 + attribute \src "libresoc.v:167844.3-167873.6" + wire $3\wr_detect$10[0:0]$10991 + attribute \src "libresoc.v:167914.3-167943.6" + wire $3\wr_detect$13[0:0]$11005 + attribute \src "libresoc.v:167704.3-167733.6" + wire $3\wr_detect$4[0:0]$10963 + attribute \src "libresoc.v:167774.3-167803.6" + wire $3\wr_detect$7[0:0]$10977 + attribute \src "libresoc.v:167607.3-167636.6" + wire $3\wr_detect[0:0] + attribute \src "libresoc.v:167874.3-167913.6" + wire width 4 $4\r24__data_o$next[3:0]$10998 + attribute \src "libresoc.v:167804.3-167843.6" + wire width 4 $4\r4__data_o$next[3:0]$10984 + attribute \src "libresoc.v:167637.3-167663.6" + wire width 4 $4\reg$next[3:0]$10950 + attribute \src "libresoc.v:167567.3-167606.6" + wire width 4 $4\src14__data_o$next[3:0]$10941 + attribute \src "libresoc.v:167664.3-167703.6" + wire width 4 $4\src24__data_o$next[3:0]$10956 + attribute \src "libresoc.v:167734.3-167773.6" + wire width 4 $4\src34__data_o$next[3:0]$10970 + attribute \src "libresoc.v:167844.3-167873.6" + wire $4\wr_detect$10[0:0]$10992 + attribute \src "libresoc.v:167914.3-167943.6" + wire $4\wr_detect$13[0:0]$11006 + attribute \src "libresoc.v:167704.3-167733.6" + wire $4\wr_detect$4[0:0]$10964 + attribute \src "libresoc.v:167774.3-167803.6" + wire $4\wr_detect$7[0:0]$10978 + attribute \src "libresoc.v:167607.3-167636.6" + wire $4\wr_detect[0:0] + attribute \src "libresoc.v:167874.3-167913.6" + wire width 4 $5\r24__data_o$next[3:0]$10999 + attribute \src "libresoc.v:167804.3-167843.6" + wire width 4 $5\r4__data_o$next[3:0]$10985 + attribute \src "libresoc.v:167567.3-167606.6" + wire width 4 $5\src14__data_o$next[3:0]$10942 + attribute \src "libresoc.v:167664.3-167703.6" + wire width 4 $5\src24__data_o$next[3:0]$10957 + attribute \src "libresoc.v:167734.3-167773.6" + wire width 4 $5\src34__data_o$next[3:0]$10971 + attribute \src "libresoc.v:167874.3-167913.6" + wire width 4 $6\r24__data_o$next[3:0]$11000 + attribute \src "libresoc.v:167804.3-167843.6" + wire width 4 $6\r4__data_o$next[3:0]$10986 + attribute \src "libresoc.v:167567.3-167606.6" + wire width 4 $6\src14__data_o$next[3:0]$10943 + attribute \src "libresoc.v:167664.3-167703.6" + wire width 4 $6\src24__data_o$next[3:0]$10958 + attribute \src "libresoc.v:167734.3-167773.6" + wire width 4 $6\src34__data_o$next[3:0]$10972 + attribute \src "libresoc.v:167550.17-167550.104" + wire $not$libresoc.v:167550$10925_Y + attribute \src "libresoc.v:167551.18-167551.105" + wire $not$libresoc.v:167551$10926_Y + attribute \src "libresoc.v:167552.17-167552.100" + wire $not$libresoc.v:167552$10927_Y + attribute \src "libresoc.v:167553.17-167553.103" + wire $not$libresoc.v:167553$10928_Y + attribute \src "libresoc.v:167554.17-167554.103" + wire $not$libresoc.v:167554$10929_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 18 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 input 9 \dest14__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 8 \dest14__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 input 11 \dest24__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 10 \dest24__wen + attribute \src "libresoc.v:167474.7-167474.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 14 \r24__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \r24__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 15 \r24__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 12 \r4__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \r4__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 13 \r4__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 4 \reg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 4 \reg$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 3 \src14__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \src14__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 2 \src14__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 5 \src24__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \src24__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 4 \src24__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 7 \src34__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \src34__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 6 \src34__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 input 16 \w4__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 17 \w4__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:167550$10925 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$10 + connect \Y $not$libresoc.v:167550$10925_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:167551$10926 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$13 + connect \Y $not$libresoc.v:167551$10926_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:167552$10927 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect + connect \Y $not$libresoc.v:167552$10927_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:167553$10928 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$4 + connect \Y $not$libresoc.v:167553$10928_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:167554$10929 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$7 + connect \Y $not$libresoc.v:167554$10929_Y + end + attribute \src "libresoc.v:167474.7-167474.20" + process $proc$libresoc.v:167474$11007 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:167499.13-167499.31" + process $proc$libresoc.v:167499$11008 + assign { } { } + assign $1\r24__data_o[3:0] 4'0000 + sync always + sync init + update \r24__data_o $1\r24__data_o[3:0] + end + attribute \src "libresoc.v:167506.13-167506.30" + process $proc$libresoc.v:167506$11009 + assign { } { } + assign $1\r4__data_o[3:0] 4'0000 + sync always + sync init + update \r4__data_o $1\r4__data_o[3:0] + end + attribute \src "libresoc.v:167512.13-167512.25" + process $proc$libresoc.v:167512$11010 + assign { } { } + assign $1\reg[3:0] 4'0000 + sync always + sync init + update \reg $1\reg[3:0] + end + attribute \src "libresoc.v:167517.13-167517.33" + process $proc$libresoc.v:167517$11011 + assign { } { } + assign $1\src14__data_o[3:0] 4'0000 + sync always + sync init + update \src14__data_o $1\src14__data_o[3:0] + end + attribute \src "libresoc.v:167524.13-167524.33" + process $proc$libresoc.v:167524$11012 + assign { } { } + assign $1\src24__data_o[3:0] 4'0000 + sync always + sync init + update \src24__data_o $1\src24__data_o[3:0] + end + attribute \src "libresoc.v:167531.13-167531.33" + process $proc$libresoc.v:167531$11013 + assign { } { } + assign $1\src34__data_o[3:0] 4'0000 + sync always + sync init + update \src34__data_o $1\src34__data_o[3:0] + end + attribute \src "libresoc.v:167555.3-167556.25" + process $proc$libresoc.v:167555$10930 + assign { } { } + assign $0\reg[3:0] \reg$next + sync posedge \coresync_clk + update \reg $0\reg[3:0] + end + attribute \src "libresoc.v:167557.3-167558.39" + process $proc$libresoc.v:167557$10931 + assign { } { } + assign $0\r24__data_o[3:0] \r24__data_o$next + sync posedge \coresync_clk + update \r24__data_o $0\r24__data_o[3:0] + end + attribute \src "libresoc.v:167559.3-167560.37" + process $proc$libresoc.v:167559$10932 + assign { } { } + assign $0\r4__data_o[3:0] \r4__data_o$next + sync posedge \coresync_clk + update \r4__data_o $0\r4__data_o[3:0] + end + attribute \src "libresoc.v:167561.3-167562.43" + process $proc$libresoc.v:167561$10933 + assign { } { } + assign $0\src34__data_o[3:0] \src34__data_o$next + sync posedge \coresync_clk + update \src34__data_o $0\src34__data_o[3:0] + end + attribute \src "libresoc.v:167563.3-167564.43" + process $proc$libresoc.v:167563$10934 + assign { } { } + assign $0\src24__data_o[3:0] \src24__data_o$next + sync posedge \coresync_clk + update \src24__data_o $0\src24__data_o[3:0] + end + attribute \src "libresoc.v:167565.3-167566.43" + process $proc$libresoc.v:167565$10935 + assign { } { } + assign $0\src14__data_o[3:0] \src14__data_o$next + sync posedge \coresync_clk + update \src14__data_o $0\src14__data_o[3:0] + end + attribute \src "libresoc.v:167567.3-167606.6" + process $proc$libresoc.v:167567$10936 + assign { } { } + assign { } { } + assign { } { } + assign $0\src14__data_o$next[3:0]$10937 $6\src14__data_o$next[3:0]$10943 + attribute \src "libresoc.v:167568.5-167568.29" + switch \initial + attribute \src "libresoc.v:167568.9-167568.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src14__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src14__data_o$next[3:0]$10938 $5\src14__data_o$next[3:0]$10942 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest14__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src14__data_o$next[3:0]$10939 \dest14__data_i + case + assign $2\src14__data_o$next[3:0]$10939 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest24__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src14__data_o$next[3:0]$10940 \dest24__data_i + case + assign $3\src14__data_o$next[3:0]$10940 $2\src14__data_o$next[3:0]$10939 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w4__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src14__data_o$next[3:0]$10941 \w4__data_i + case + assign $4\src14__data_o$next[3:0]$10941 $3\src14__data_o$next[3:0]$10940 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src14__data_o$next[3:0]$10942 \reg + case + assign $5\src14__data_o$next[3:0]$10942 $4\src14__data_o$next[3:0]$10941 + end + case + assign $1\src14__data_o$next[3:0]$10938 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src14__data_o$next[3:0]$10943 4'0000 + case + assign $6\src14__data_o$next[3:0]$10943 $1\src14__data_o$next[3:0]$10938 + end + sync always + update \src14__data_o$next $0\src14__data_o$next[3:0]$10937 + end + attribute \src "libresoc.v:167607.3-167636.6" + process $proc$libresoc.v:167607$10944 + assign { } { } + assign { } { } + assign $0\wr_detect[0:0] $1\wr_detect[0:0] + attribute \src "libresoc.v:167608.5-167608.29" + switch \initial + attribute \src "libresoc.v:167608.9-167608.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src14__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect[0:0] $4\wr_detect[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest14__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect[0:0] 1'1 + case + assign $2\wr_detect[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest24__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect[0:0] 1'1 + case + assign $3\wr_detect[0:0] $2\wr_detect[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w4__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect[0:0] 1'1 + case + assign $4\wr_detect[0:0] $3\wr_detect[0:0] + end + case + assign $1\wr_detect[0:0] 1'0 + end + sync always + update \wr_detect $0\wr_detect[0:0] + end + attribute \src "libresoc.v:167637.3-167663.6" + process $proc$libresoc.v:167637$10945 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\reg$next[3:0]$10946 $4\reg$next[3:0]$10950 + attribute \src "libresoc.v:167638.5-167638.29" + switch \initial + attribute \src "libresoc.v:167638.9-167638.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest14__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\reg$next[3:0]$10947 \dest14__data_i + case + assign $1\reg$next[3:0]$10947 \reg + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest24__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\reg$next[3:0]$10948 \dest24__data_i + case + assign $2\reg$next[3:0]$10948 $1\reg$next[3:0]$10947 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \w4__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\reg$next[3:0]$10949 \w4__data_i + case + assign $3\reg$next[3:0]$10949 $2\reg$next[3:0]$10948 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\reg$next[3:0]$10950 4'0000 + case + assign $4\reg$next[3:0]$10950 $3\reg$next[3:0]$10949 + end + sync always + update \reg$next $0\reg$next[3:0]$10946 + end + attribute \src "libresoc.v:167664.3-167703.6" + process $proc$libresoc.v:167664$10951 + assign { } { } + assign { } { } + assign { } { } + assign $0\src24__data_o$next[3:0]$10952 $6\src24__data_o$next[3:0]$10958 + attribute \src "libresoc.v:167665.5-167665.29" + switch \initial + attribute \src "libresoc.v:167665.9-167665.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src24__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src24__data_o$next[3:0]$10953 $5\src24__data_o$next[3:0]$10957 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest14__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src24__data_o$next[3:0]$10954 \dest14__data_i + case + assign $2\src24__data_o$next[3:0]$10954 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest24__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src24__data_o$next[3:0]$10955 \dest24__data_i + case + assign $3\src24__data_o$next[3:0]$10955 $2\src24__data_o$next[3:0]$10954 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w4__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src24__data_o$next[3:0]$10956 \w4__data_i + case + assign $4\src24__data_o$next[3:0]$10956 $3\src24__data_o$next[3:0]$10955 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src24__data_o$next[3:0]$10957 \reg + case + assign $5\src24__data_o$next[3:0]$10957 $4\src24__data_o$next[3:0]$10956 + end + case + assign $1\src24__data_o$next[3:0]$10953 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src24__data_o$next[3:0]$10958 4'0000 + case + assign $6\src24__data_o$next[3:0]$10958 $1\src24__data_o$next[3:0]$10953 + end + sync always + update \src24__data_o$next $0\src24__data_o$next[3:0]$10952 + end + attribute \src "libresoc.v:167704.3-167733.6" + process $proc$libresoc.v:167704$10959 + assign { } { } + assign { } { } + assign $0\wr_detect$4[0:0]$10960 $1\wr_detect$4[0:0]$10961 + attribute \src "libresoc.v:167705.5-167705.29" + switch \initial + attribute \src "libresoc.v:167705.9-167705.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src24__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$4[0:0]$10961 $4\wr_detect$4[0:0]$10964 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest14__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$4[0:0]$10962 1'1 + case + assign $2\wr_detect$4[0:0]$10962 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest24__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$4[0:0]$10963 1'1 + case + assign $3\wr_detect$4[0:0]$10963 $2\wr_detect$4[0:0]$10962 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w4__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$4[0:0]$10964 1'1 + case + assign $4\wr_detect$4[0:0]$10964 $3\wr_detect$4[0:0]$10963 + end + case + assign $1\wr_detect$4[0:0]$10961 1'0 + end + sync always + update \wr_detect$4 $0\wr_detect$4[0:0]$10960 + end + attribute \src "libresoc.v:167734.3-167773.6" + process $proc$libresoc.v:167734$10965 + assign { } { } + assign { } { } + assign { } { } + assign $0\src34__data_o$next[3:0]$10966 $6\src34__data_o$next[3:0]$10972 + attribute \src "libresoc.v:167735.5-167735.29" + switch \initial + attribute \src "libresoc.v:167735.9-167735.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src34__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src34__data_o$next[3:0]$10967 $5\src34__data_o$next[3:0]$10971 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest14__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src34__data_o$next[3:0]$10968 \dest14__data_i + case + assign $2\src34__data_o$next[3:0]$10968 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest24__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src34__data_o$next[3:0]$10969 \dest24__data_i + case + assign $3\src34__data_o$next[3:0]$10969 $2\src34__data_o$next[3:0]$10968 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w4__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src34__data_o$next[3:0]$10970 \w4__data_i + case + assign $4\src34__data_o$next[3:0]$10970 $3\src34__data_o$next[3:0]$10969 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$6 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src34__data_o$next[3:0]$10971 \reg + case + assign $5\src34__data_o$next[3:0]$10971 $4\src34__data_o$next[3:0]$10970 + end + case + assign $1\src34__data_o$next[3:0]$10967 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src34__data_o$next[3:0]$10972 4'0000 + case + assign $6\src34__data_o$next[3:0]$10972 $1\src34__data_o$next[3:0]$10967 + end + sync always + update \src34__data_o$next $0\src34__data_o$next[3:0]$10966 + end + attribute \src "libresoc.v:167774.3-167803.6" + process $proc$libresoc.v:167774$10973 + assign { } { } + assign { } { } + assign $0\wr_detect$7[0:0]$10974 $1\wr_detect$7[0:0]$10975 + attribute \src "libresoc.v:167775.5-167775.29" + switch \initial + attribute \src "libresoc.v:167775.9-167775.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src34__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$7[0:0]$10975 $4\wr_detect$7[0:0]$10978 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest14__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$7[0:0]$10976 1'1 + case + assign $2\wr_detect$7[0:0]$10976 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest24__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$7[0:0]$10977 1'1 + case + assign $3\wr_detect$7[0:0]$10977 $2\wr_detect$7[0:0]$10976 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w4__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$7[0:0]$10978 1'1 + case + assign $4\wr_detect$7[0:0]$10978 $3\wr_detect$7[0:0]$10977 + end + case + assign $1\wr_detect$7[0:0]$10975 1'0 + end + sync always + update \wr_detect$7 $0\wr_detect$7[0:0]$10974 + end + attribute \src "libresoc.v:167804.3-167843.6" + process $proc$libresoc.v:167804$10979 + assign { } { } + assign { } { } + assign { } { } + assign $0\r4__data_o$next[3:0]$10980 $6\r4__data_o$next[3:0]$10986 + attribute \src "libresoc.v:167805.5-167805.29" + switch \initial + attribute \src "libresoc.v:167805.9-167805.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r4__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\r4__data_o$next[3:0]$10981 $5\r4__data_o$next[3:0]$10985 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest14__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r4__data_o$next[3:0]$10982 \dest14__data_i + case + assign $2\r4__data_o$next[3:0]$10982 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest24__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\r4__data_o$next[3:0]$10983 \dest24__data_i + case + assign $3\r4__data_o$next[3:0]$10983 $2\r4__data_o$next[3:0]$10982 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w4__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\r4__data_o$next[3:0]$10984 \w4__data_i + case + assign $4\r4__data_o$next[3:0]$10984 $3\r4__data_o$next[3:0]$10983 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$9 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\r4__data_o$next[3:0]$10985 \reg + case + assign $5\r4__data_o$next[3:0]$10985 $4\r4__data_o$next[3:0]$10984 + end + case + assign $1\r4__data_o$next[3:0]$10981 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\r4__data_o$next[3:0]$10986 4'0000 + case + assign $6\r4__data_o$next[3:0]$10986 $1\r4__data_o$next[3:0]$10981 + end + sync always + update \r4__data_o$next $0\r4__data_o$next[3:0]$10980 + end + attribute \src "libresoc.v:167844.3-167873.6" + process $proc$libresoc.v:167844$10987 + assign { } { } + assign { } { } + assign $0\wr_detect$10[0:0]$10988 $1\wr_detect$10[0:0]$10989 + attribute \src "libresoc.v:167845.5-167845.29" + switch \initial + attribute \src "libresoc.v:167845.9-167845.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r4__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$10[0:0]$10989 $4\wr_detect$10[0:0]$10992 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest14__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$10[0:0]$10990 1'1 + case + assign $2\wr_detect$10[0:0]$10990 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest24__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$10[0:0]$10991 1'1 + case + assign $3\wr_detect$10[0:0]$10991 $2\wr_detect$10[0:0]$10990 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w4__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$10[0:0]$10992 1'1 + case + assign $4\wr_detect$10[0:0]$10992 $3\wr_detect$10[0:0]$10991 + end + case + assign $1\wr_detect$10[0:0]$10989 1'0 + end + sync always + update \wr_detect$10 $0\wr_detect$10[0:0]$10988 + end + attribute \src "libresoc.v:167874.3-167913.6" + process $proc$libresoc.v:167874$10993 + assign { } { } + assign { } { } + assign { } { } + assign $0\r24__data_o$next[3:0]$10994 $6\r24__data_o$next[3:0]$11000 + attribute \src "libresoc.v:167875.5-167875.29" + switch \initial + attribute \src "libresoc.v:167875.9-167875.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r24__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\r24__data_o$next[3:0]$10995 $5\r24__data_o$next[3:0]$10999 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest14__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r24__data_o$next[3:0]$10996 \dest14__data_i + case + assign $2\r24__data_o$next[3:0]$10996 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest24__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\r24__data_o$next[3:0]$10997 \dest24__data_i + case + assign $3\r24__data_o$next[3:0]$10997 $2\r24__data_o$next[3:0]$10996 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w4__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\r24__data_o$next[3:0]$10998 \w4__data_i + case + assign $4\r24__data_o$next[3:0]$10998 $3\r24__data_o$next[3:0]$10997 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$12 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\r24__data_o$next[3:0]$10999 \reg + case + assign $5\r24__data_o$next[3:0]$10999 $4\r24__data_o$next[3:0]$10998 + end + case + assign $1\r24__data_o$next[3:0]$10995 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\r24__data_o$next[3:0]$11000 4'0000 + case + assign $6\r24__data_o$next[3:0]$11000 $1\r24__data_o$next[3:0]$10995 + end + sync always + update \r24__data_o$next $0\r24__data_o$next[3:0]$10994 + end + attribute \src "libresoc.v:167914.3-167943.6" + process $proc$libresoc.v:167914$11001 + assign { } { } + assign { } { } + assign $0\wr_detect$13[0:0]$11002 $1\wr_detect$13[0:0]$11003 + attribute \src "libresoc.v:167915.5-167915.29" + switch \initial + attribute \src "libresoc.v:167915.9-167915.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r24__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$13[0:0]$11003 $4\wr_detect$13[0:0]$11006 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest14__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$13[0:0]$11004 1'1 + case + assign $2\wr_detect$13[0:0]$11004 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest24__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$13[0:0]$11005 1'1 + case + assign $3\wr_detect$13[0:0]$11005 $2\wr_detect$13[0:0]$11004 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w4__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$13[0:0]$11006 1'1 + case + assign $4\wr_detect$13[0:0]$11006 $3\wr_detect$13[0:0]$11005 + end + case + assign $1\wr_detect$13[0:0]$11003 1'0 + end + sync always + update \wr_detect$13 $0\wr_detect$13[0:0]$11002 + end + connect \$9 $not$libresoc.v:167550$10925_Y + connect \$12 $not$libresoc.v:167551$10926_Y + connect \$1 $not$libresoc.v:167552$10927_Y + connect \$3 $not$libresoc.v:167553$10928_Y + connect \$6 $not$libresoc.v:167554$10929_Y +end +attribute \src "libresoc.v:167948.1-168419.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.cr.reg_5" +attribute \generator "nMigen" +module \reg_5 + attribute \src "libresoc.v:167949.7-167949.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:168349.3-168388.6" + wire width 4 $0\r25__data_o$next[3:0]$11083 + attribute \src "libresoc.v:168032.3-168033.39" + wire width 4 $0\r25__data_o[3:0] + attribute \src "libresoc.v:168279.3-168318.6" + wire width 4 $0\r5__data_o$next[3:0]$11069 + attribute \src "libresoc.v:168034.3-168035.37" + wire width 4 $0\r5__data_o[3:0] + attribute \src "libresoc.v:168112.3-168138.6" + wire width 4 $0\reg$next[3:0]$11035 + attribute \src "libresoc.v:168030.3-168031.25" + wire width 4 $0\reg[3:0] + attribute \src "libresoc.v:168042.3-168081.6" + wire width 4 $0\src15__data_o$next[3:0]$11026 + attribute \src "libresoc.v:168040.3-168041.43" + wire width 4 $0\src15__data_o[3:0] + attribute \src "libresoc.v:168139.3-168178.6" + wire width 4 $0\src25__data_o$next[3:0]$11041 + attribute \src "libresoc.v:168038.3-168039.43" + wire width 4 $0\src25__data_o[3:0] + attribute \src "libresoc.v:168209.3-168248.6" + wire width 4 $0\src35__data_o$next[3:0]$11055 + attribute \src "libresoc.v:168036.3-168037.43" + wire width 4 $0\src35__data_o[3:0] + attribute \src "libresoc.v:168319.3-168348.6" + wire $0\wr_detect$10[0:0]$11077 + attribute \src "libresoc.v:168389.3-168418.6" + wire $0\wr_detect$13[0:0]$11091 + attribute \src "libresoc.v:168179.3-168208.6" + wire $0\wr_detect$4[0:0]$11049 + attribute \src "libresoc.v:168249.3-168278.6" + wire $0\wr_detect$7[0:0]$11063 + attribute \src "libresoc.v:168082.3-168111.6" + wire $0\wr_detect[0:0] + attribute \src "libresoc.v:168349.3-168388.6" + wire width 4 $1\r25__data_o$next[3:0]$11084 + attribute \src "libresoc.v:167974.13-167974.31" + wire width 4 $1\r25__data_o[3:0] + attribute \src "libresoc.v:168279.3-168318.6" + wire width 4 $1\r5__data_o$next[3:0]$11070 + attribute \src "libresoc.v:167981.13-167981.30" + wire width 4 $1\r5__data_o[3:0] + attribute \src "libresoc.v:168112.3-168138.6" + wire width 4 $1\reg$next[3:0]$11036 + attribute \src "libresoc.v:167987.13-167987.25" + wire width 4 $1\reg[3:0] + attribute \src "libresoc.v:168042.3-168081.6" + wire width 4 $1\src15__data_o$next[3:0]$11027 + attribute \src "libresoc.v:167992.13-167992.33" + wire width 4 $1\src15__data_o[3:0] + attribute \src "libresoc.v:168139.3-168178.6" + wire width 4 $1\src25__data_o$next[3:0]$11042 + attribute \src "libresoc.v:167999.13-167999.33" + wire width 4 $1\src25__data_o[3:0] + attribute \src "libresoc.v:168209.3-168248.6" + wire width 4 $1\src35__data_o$next[3:0]$11056 + attribute \src "libresoc.v:168006.13-168006.33" + wire width 4 $1\src35__data_o[3:0] + attribute \src "libresoc.v:168319.3-168348.6" + wire $1\wr_detect$10[0:0]$11078 + attribute \src "libresoc.v:168389.3-168418.6" + wire $1\wr_detect$13[0:0]$11092 + attribute \src "libresoc.v:168179.3-168208.6" + wire $1\wr_detect$4[0:0]$11050 + attribute \src "libresoc.v:168249.3-168278.6" + wire $1\wr_detect$7[0:0]$11064 + attribute \src "libresoc.v:168082.3-168111.6" + wire $1\wr_detect[0:0] + attribute \src "libresoc.v:168349.3-168388.6" + wire width 4 $2\r25__data_o$next[3:0]$11085 + attribute \src "libresoc.v:168279.3-168318.6" + wire width 4 $2\r5__data_o$next[3:0]$11071 + attribute \src "libresoc.v:168112.3-168138.6" + wire width 4 $2\reg$next[3:0]$11037 + attribute \src "libresoc.v:168042.3-168081.6" + wire width 4 $2\src15__data_o$next[3:0]$11028 + attribute \src "libresoc.v:168139.3-168178.6" + wire width 4 $2\src25__data_o$next[3:0]$11043 + attribute \src "libresoc.v:168209.3-168248.6" + wire width 4 $2\src35__data_o$next[3:0]$11057 + attribute \src "libresoc.v:168319.3-168348.6" + wire $2\wr_detect$10[0:0]$11079 + attribute \src "libresoc.v:168389.3-168418.6" + wire $2\wr_detect$13[0:0]$11093 + attribute \src "libresoc.v:168179.3-168208.6" + wire $2\wr_detect$4[0:0]$11051 + attribute \src "libresoc.v:168249.3-168278.6" + wire $2\wr_detect$7[0:0]$11065 + attribute \src "libresoc.v:168082.3-168111.6" + wire $2\wr_detect[0:0] + attribute \src "libresoc.v:168349.3-168388.6" + wire width 4 $3\r25__data_o$next[3:0]$11086 + attribute \src "libresoc.v:168279.3-168318.6" + wire width 4 $3\r5__data_o$next[3:0]$11072 + attribute \src "libresoc.v:168112.3-168138.6" + wire width 4 $3\reg$next[3:0]$11038 + attribute \src "libresoc.v:168042.3-168081.6" + wire width 4 $3\src15__data_o$next[3:0]$11029 + attribute \src "libresoc.v:168139.3-168178.6" + wire width 4 $3\src25__data_o$next[3:0]$11044 + attribute \src "libresoc.v:168209.3-168248.6" + wire width 4 $3\src35__data_o$next[3:0]$11058 + attribute \src "libresoc.v:168319.3-168348.6" + wire $3\wr_detect$10[0:0]$11080 + attribute \src "libresoc.v:168389.3-168418.6" + wire $3\wr_detect$13[0:0]$11094 + attribute \src "libresoc.v:168179.3-168208.6" + wire $3\wr_detect$4[0:0]$11052 + attribute \src "libresoc.v:168249.3-168278.6" + wire $3\wr_detect$7[0:0]$11066 + attribute \src "libresoc.v:168082.3-168111.6" + wire $3\wr_detect[0:0] + attribute \src "libresoc.v:168349.3-168388.6" + wire width 4 $4\r25__data_o$next[3:0]$11087 + attribute \src "libresoc.v:168279.3-168318.6" + wire width 4 $4\r5__data_o$next[3:0]$11073 + attribute \src "libresoc.v:168112.3-168138.6" + wire width 4 $4\reg$next[3:0]$11039 + attribute \src "libresoc.v:168042.3-168081.6" + wire width 4 $4\src15__data_o$next[3:0]$11030 + attribute \src "libresoc.v:168139.3-168178.6" + wire width 4 $4\src25__data_o$next[3:0]$11045 + attribute \src "libresoc.v:168209.3-168248.6" + wire width 4 $4\src35__data_o$next[3:0]$11059 + attribute \src "libresoc.v:168319.3-168348.6" + wire $4\wr_detect$10[0:0]$11081 + attribute \src "libresoc.v:168389.3-168418.6" + wire $4\wr_detect$13[0:0]$11095 + attribute \src "libresoc.v:168179.3-168208.6" + wire $4\wr_detect$4[0:0]$11053 + attribute \src "libresoc.v:168249.3-168278.6" + wire $4\wr_detect$7[0:0]$11067 + attribute \src "libresoc.v:168082.3-168111.6" + wire $4\wr_detect[0:0] + attribute \src "libresoc.v:168349.3-168388.6" + wire width 4 $5\r25__data_o$next[3:0]$11088 + attribute \src "libresoc.v:168279.3-168318.6" + wire width 4 $5\r5__data_o$next[3:0]$11074 + attribute \src "libresoc.v:168042.3-168081.6" + wire width 4 $5\src15__data_o$next[3:0]$11031 + attribute \src "libresoc.v:168139.3-168178.6" + wire width 4 $5\src25__data_o$next[3:0]$11046 + attribute \src "libresoc.v:168209.3-168248.6" + wire width 4 $5\src35__data_o$next[3:0]$11060 + attribute \src "libresoc.v:168349.3-168388.6" + wire width 4 $6\r25__data_o$next[3:0]$11089 + attribute \src "libresoc.v:168279.3-168318.6" + wire width 4 $6\r5__data_o$next[3:0]$11075 + attribute \src "libresoc.v:168042.3-168081.6" + wire width 4 $6\src15__data_o$next[3:0]$11032 + attribute \src "libresoc.v:168139.3-168178.6" + wire width 4 $6\src25__data_o$next[3:0]$11047 + attribute \src "libresoc.v:168209.3-168248.6" + wire width 4 $6\src35__data_o$next[3:0]$11061 + attribute \src "libresoc.v:168025.17-168025.104" + wire $not$libresoc.v:168025$11014_Y + attribute \src "libresoc.v:168026.18-168026.105" + wire $not$libresoc.v:168026$11015_Y + attribute \src "libresoc.v:168027.17-168027.100" + wire $not$libresoc.v:168027$11016_Y + attribute \src "libresoc.v:168028.17-168028.103" + wire $not$libresoc.v:168028$11017_Y + attribute \src "libresoc.v:168029.17-168029.103" + wire $not$libresoc.v:168029$11018_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 18 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 input 9 \dest15__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 8 \dest15__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 input 11 \dest25__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 10 \dest25__wen + attribute \src "libresoc.v:167949.7-167949.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 14 \r25__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \r25__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 15 \r25__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 12 \r5__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \r5__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 13 \r5__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 4 \reg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 4 \reg$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 3 \src15__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \src15__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 2 \src15__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 5 \src25__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \src25__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 4 \src25__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 7 \src35__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \src35__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 6 \src35__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 input 16 \w5__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 17 \w5__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:168025$11014 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$10 + connect \Y $not$libresoc.v:168025$11014_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:168026$11015 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$13 + connect \Y $not$libresoc.v:168026$11015_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:168027$11016 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect + connect \Y $not$libresoc.v:168027$11016_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:168028$11017 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$4 + connect \Y $not$libresoc.v:168028$11017_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:168029$11018 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$7 + connect \Y $not$libresoc.v:168029$11018_Y + end + attribute \src "libresoc.v:167949.7-167949.20" + process $proc$libresoc.v:167949$11096 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:167974.13-167974.31" + process $proc$libresoc.v:167974$11097 + assign { } { } + assign $1\r25__data_o[3:0] 4'0000 + sync always + sync init + update \r25__data_o $1\r25__data_o[3:0] + end + attribute \src "libresoc.v:167981.13-167981.30" + process $proc$libresoc.v:167981$11098 + assign { } { } + assign $1\r5__data_o[3:0] 4'0000 + sync always + sync init + update \r5__data_o $1\r5__data_o[3:0] + end + attribute \src "libresoc.v:167987.13-167987.25" + process $proc$libresoc.v:167987$11099 + assign { } { } + assign $1\reg[3:0] 4'0000 + sync always + sync init + update \reg $1\reg[3:0] + end + attribute \src "libresoc.v:167992.13-167992.33" + process $proc$libresoc.v:167992$11100 + assign { } { } + assign $1\src15__data_o[3:0] 4'0000 + sync always + sync init + update \src15__data_o $1\src15__data_o[3:0] + end + attribute \src "libresoc.v:167999.13-167999.33" + process $proc$libresoc.v:167999$11101 + assign { } { } + assign $1\src25__data_o[3:0] 4'0000 + sync always + sync init + update \src25__data_o $1\src25__data_o[3:0] + end + attribute \src "libresoc.v:168006.13-168006.33" + process $proc$libresoc.v:168006$11102 + assign { } { } + assign $1\src35__data_o[3:0] 4'0000 + sync always + sync init + update \src35__data_o $1\src35__data_o[3:0] + end + attribute \src "libresoc.v:168030.3-168031.25" + process $proc$libresoc.v:168030$11019 + assign { } { } + assign $0\reg[3:0] \reg$next + sync posedge \coresync_clk + update \reg $0\reg[3:0] + end + attribute \src "libresoc.v:168032.3-168033.39" + process $proc$libresoc.v:168032$11020 + assign { } { } + assign $0\r25__data_o[3:0] \r25__data_o$next + sync posedge \coresync_clk + update \r25__data_o $0\r25__data_o[3:0] + end + attribute \src "libresoc.v:168034.3-168035.37" + process $proc$libresoc.v:168034$11021 + assign { } { } + assign $0\r5__data_o[3:0] \r5__data_o$next + sync posedge \coresync_clk + update \r5__data_o $0\r5__data_o[3:0] + end + attribute \src "libresoc.v:168036.3-168037.43" + process $proc$libresoc.v:168036$11022 + assign { } { } + assign $0\src35__data_o[3:0] \src35__data_o$next + sync posedge \coresync_clk + update \src35__data_o $0\src35__data_o[3:0] + end + attribute \src "libresoc.v:168038.3-168039.43" + process $proc$libresoc.v:168038$11023 + assign { } { } + assign $0\src25__data_o[3:0] \src25__data_o$next + sync posedge \coresync_clk + update \src25__data_o $0\src25__data_o[3:0] + end + attribute \src "libresoc.v:168040.3-168041.43" + process $proc$libresoc.v:168040$11024 + assign { } { } + assign $0\src15__data_o[3:0] \src15__data_o$next + sync posedge \coresync_clk + update \src15__data_o $0\src15__data_o[3:0] + end + attribute \src "libresoc.v:168042.3-168081.6" + process $proc$libresoc.v:168042$11025 + assign { } { } + assign { } { } + assign { } { } + assign $0\src15__data_o$next[3:0]$11026 $6\src15__data_o$next[3:0]$11032 + attribute \src "libresoc.v:168043.5-168043.29" + switch \initial + attribute \src "libresoc.v:168043.9-168043.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src15__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src15__data_o$next[3:0]$11027 $5\src15__data_o$next[3:0]$11031 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest15__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src15__data_o$next[3:0]$11028 \dest15__data_i + case + assign $2\src15__data_o$next[3:0]$11028 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest25__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src15__data_o$next[3:0]$11029 \dest25__data_i + case + assign $3\src15__data_o$next[3:0]$11029 $2\src15__data_o$next[3:0]$11028 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w5__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src15__data_o$next[3:0]$11030 \w5__data_i + case + assign $4\src15__data_o$next[3:0]$11030 $3\src15__data_o$next[3:0]$11029 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src15__data_o$next[3:0]$11031 \reg + case + assign $5\src15__data_o$next[3:0]$11031 $4\src15__data_o$next[3:0]$11030 + end + case + assign $1\src15__data_o$next[3:0]$11027 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src15__data_o$next[3:0]$11032 4'0000 + case + assign $6\src15__data_o$next[3:0]$11032 $1\src15__data_o$next[3:0]$11027 + end + sync always + update \src15__data_o$next $0\src15__data_o$next[3:0]$11026 + end + attribute \src "libresoc.v:168082.3-168111.6" + process $proc$libresoc.v:168082$11033 + assign { } { } + assign { } { } + assign $0\wr_detect[0:0] $1\wr_detect[0:0] + attribute \src "libresoc.v:168083.5-168083.29" + switch \initial + attribute \src "libresoc.v:168083.9-168083.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src15__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect[0:0] $4\wr_detect[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest15__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect[0:0] 1'1 + case + assign $2\wr_detect[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest25__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect[0:0] 1'1 + case + assign $3\wr_detect[0:0] $2\wr_detect[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w5__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect[0:0] 1'1 + case + assign $4\wr_detect[0:0] $3\wr_detect[0:0] + end + case + assign $1\wr_detect[0:0] 1'0 + end + sync always + update \wr_detect $0\wr_detect[0:0] + end + attribute \src "libresoc.v:168112.3-168138.6" + process $proc$libresoc.v:168112$11034 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\reg$next[3:0]$11035 $4\reg$next[3:0]$11039 + attribute \src "libresoc.v:168113.5-168113.29" + switch \initial + attribute \src "libresoc.v:168113.9-168113.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest15__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\reg$next[3:0]$11036 \dest15__data_i + case + assign $1\reg$next[3:0]$11036 \reg + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest25__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\reg$next[3:0]$11037 \dest25__data_i + case + assign $2\reg$next[3:0]$11037 $1\reg$next[3:0]$11036 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \w5__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\reg$next[3:0]$11038 \w5__data_i + case + assign $3\reg$next[3:0]$11038 $2\reg$next[3:0]$11037 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\reg$next[3:0]$11039 4'0000 + case + assign $4\reg$next[3:0]$11039 $3\reg$next[3:0]$11038 + end + sync always + update \reg$next $0\reg$next[3:0]$11035 + end + attribute \src "libresoc.v:168139.3-168178.6" + process $proc$libresoc.v:168139$11040 + assign { } { } + assign { } { } + assign { } { } + assign $0\src25__data_o$next[3:0]$11041 $6\src25__data_o$next[3:0]$11047 + attribute \src "libresoc.v:168140.5-168140.29" + switch \initial + attribute \src "libresoc.v:168140.9-168140.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src25__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src25__data_o$next[3:0]$11042 $5\src25__data_o$next[3:0]$11046 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest15__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src25__data_o$next[3:0]$11043 \dest15__data_i + case + assign $2\src25__data_o$next[3:0]$11043 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest25__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src25__data_o$next[3:0]$11044 \dest25__data_i + case + assign $3\src25__data_o$next[3:0]$11044 $2\src25__data_o$next[3:0]$11043 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w5__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src25__data_o$next[3:0]$11045 \w5__data_i + case + assign $4\src25__data_o$next[3:0]$11045 $3\src25__data_o$next[3:0]$11044 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src25__data_o$next[3:0]$11046 \reg + case + assign $5\src25__data_o$next[3:0]$11046 $4\src25__data_o$next[3:0]$11045 + end + case + assign $1\src25__data_o$next[3:0]$11042 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src25__data_o$next[3:0]$11047 4'0000 + case + assign $6\src25__data_o$next[3:0]$11047 $1\src25__data_o$next[3:0]$11042 + end + sync always + update \src25__data_o$next $0\src25__data_o$next[3:0]$11041 + end + attribute \src "libresoc.v:168179.3-168208.6" + process $proc$libresoc.v:168179$11048 + assign { } { } + assign { } { } + assign $0\wr_detect$4[0:0]$11049 $1\wr_detect$4[0:0]$11050 + attribute \src "libresoc.v:168180.5-168180.29" + switch \initial + attribute \src "libresoc.v:168180.9-168180.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src25__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$4[0:0]$11050 $4\wr_detect$4[0:0]$11053 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest15__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$4[0:0]$11051 1'1 + case + assign $2\wr_detect$4[0:0]$11051 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest25__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$4[0:0]$11052 1'1 + case + assign $3\wr_detect$4[0:0]$11052 $2\wr_detect$4[0:0]$11051 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w5__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$4[0:0]$11053 1'1 + case + assign $4\wr_detect$4[0:0]$11053 $3\wr_detect$4[0:0]$11052 + end + case + assign $1\wr_detect$4[0:0]$11050 1'0 + end + sync always + update \wr_detect$4 $0\wr_detect$4[0:0]$11049 + end + attribute \src "libresoc.v:168209.3-168248.6" + process $proc$libresoc.v:168209$11054 + assign { } { } + assign { } { } + assign { } { } + assign $0\src35__data_o$next[3:0]$11055 $6\src35__data_o$next[3:0]$11061 + attribute \src "libresoc.v:168210.5-168210.29" + switch \initial + attribute \src "libresoc.v:168210.9-168210.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src35__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src35__data_o$next[3:0]$11056 $5\src35__data_o$next[3:0]$11060 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest15__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src35__data_o$next[3:0]$11057 \dest15__data_i + case + assign $2\src35__data_o$next[3:0]$11057 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest25__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src35__data_o$next[3:0]$11058 \dest25__data_i + case + assign $3\src35__data_o$next[3:0]$11058 $2\src35__data_o$next[3:0]$11057 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w5__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src35__data_o$next[3:0]$11059 \w5__data_i + case + assign $4\src35__data_o$next[3:0]$11059 $3\src35__data_o$next[3:0]$11058 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$6 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src35__data_o$next[3:0]$11060 \reg + case + assign $5\src35__data_o$next[3:0]$11060 $4\src35__data_o$next[3:0]$11059 + end + case + assign $1\src35__data_o$next[3:0]$11056 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src35__data_o$next[3:0]$11061 4'0000 + case + assign $6\src35__data_o$next[3:0]$11061 $1\src35__data_o$next[3:0]$11056 + end + sync always + update \src35__data_o$next $0\src35__data_o$next[3:0]$11055 + end + attribute \src "libresoc.v:168249.3-168278.6" + process $proc$libresoc.v:168249$11062 + assign { } { } + assign { } { } + assign $0\wr_detect$7[0:0]$11063 $1\wr_detect$7[0:0]$11064 + attribute \src "libresoc.v:168250.5-168250.29" + switch \initial + attribute \src "libresoc.v:168250.9-168250.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src35__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$7[0:0]$11064 $4\wr_detect$7[0:0]$11067 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest15__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$7[0:0]$11065 1'1 + case + assign $2\wr_detect$7[0:0]$11065 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest25__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$7[0:0]$11066 1'1 + case + assign $3\wr_detect$7[0:0]$11066 $2\wr_detect$7[0:0]$11065 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w5__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$7[0:0]$11067 1'1 + case + assign $4\wr_detect$7[0:0]$11067 $3\wr_detect$7[0:0]$11066 + end + case + assign $1\wr_detect$7[0:0]$11064 1'0 + end + sync always + update \wr_detect$7 $0\wr_detect$7[0:0]$11063 + end + attribute \src "libresoc.v:168279.3-168318.6" + process $proc$libresoc.v:168279$11068 + assign { } { } + assign { } { } + assign { } { } + assign $0\r5__data_o$next[3:0]$11069 $6\r5__data_o$next[3:0]$11075 + attribute \src "libresoc.v:168280.5-168280.29" + switch \initial + attribute \src "libresoc.v:168280.9-168280.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r5__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\r5__data_o$next[3:0]$11070 $5\r5__data_o$next[3:0]$11074 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest15__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r5__data_o$next[3:0]$11071 \dest15__data_i + case + assign $2\r5__data_o$next[3:0]$11071 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest25__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\r5__data_o$next[3:0]$11072 \dest25__data_i + case + assign $3\r5__data_o$next[3:0]$11072 $2\r5__data_o$next[3:0]$11071 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w5__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\r5__data_o$next[3:0]$11073 \w5__data_i + case + assign $4\r5__data_o$next[3:0]$11073 $3\r5__data_o$next[3:0]$11072 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$9 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\r5__data_o$next[3:0]$11074 \reg + case + assign $5\r5__data_o$next[3:0]$11074 $4\r5__data_o$next[3:0]$11073 + end + case + assign $1\r5__data_o$next[3:0]$11070 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\r5__data_o$next[3:0]$11075 4'0000 + case + assign $6\r5__data_o$next[3:0]$11075 $1\r5__data_o$next[3:0]$11070 + end + sync always + update \r5__data_o$next $0\r5__data_o$next[3:0]$11069 + end + attribute \src "libresoc.v:168319.3-168348.6" + process $proc$libresoc.v:168319$11076 + assign { } { } + assign { } { } + assign $0\wr_detect$10[0:0]$11077 $1\wr_detect$10[0:0]$11078 + attribute \src "libresoc.v:168320.5-168320.29" + switch \initial + attribute \src "libresoc.v:168320.9-168320.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r5__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$10[0:0]$11078 $4\wr_detect$10[0:0]$11081 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest15__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$10[0:0]$11079 1'1 + case + assign $2\wr_detect$10[0:0]$11079 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest25__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$10[0:0]$11080 1'1 + case + assign $3\wr_detect$10[0:0]$11080 $2\wr_detect$10[0:0]$11079 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w5__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$10[0:0]$11081 1'1 + case + assign $4\wr_detect$10[0:0]$11081 $3\wr_detect$10[0:0]$11080 + end + case + assign $1\wr_detect$10[0:0]$11078 1'0 + end + sync always + update \wr_detect$10 $0\wr_detect$10[0:0]$11077 + end + attribute \src "libresoc.v:168349.3-168388.6" + process $proc$libresoc.v:168349$11082 + assign { } { } + assign { } { } + assign { } { } + assign $0\r25__data_o$next[3:0]$11083 $6\r25__data_o$next[3:0]$11089 + attribute \src "libresoc.v:168350.5-168350.29" + switch \initial + attribute \src "libresoc.v:168350.9-168350.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r25__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\r25__data_o$next[3:0]$11084 $5\r25__data_o$next[3:0]$11088 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest15__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r25__data_o$next[3:0]$11085 \dest15__data_i + case + assign $2\r25__data_o$next[3:0]$11085 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest25__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\r25__data_o$next[3:0]$11086 \dest25__data_i + case + assign $3\r25__data_o$next[3:0]$11086 $2\r25__data_o$next[3:0]$11085 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w5__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\r25__data_o$next[3:0]$11087 \w5__data_i + case + assign $4\r25__data_o$next[3:0]$11087 $3\r25__data_o$next[3:0]$11086 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$12 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\r25__data_o$next[3:0]$11088 \reg + case + assign $5\r25__data_o$next[3:0]$11088 $4\r25__data_o$next[3:0]$11087 + end + case + assign $1\r25__data_o$next[3:0]$11084 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\r25__data_o$next[3:0]$11089 4'0000 + case + assign $6\r25__data_o$next[3:0]$11089 $1\r25__data_o$next[3:0]$11084 + end + sync always + update \r25__data_o$next $0\r25__data_o$next[3:0]$11083 + end + attribute \src "libresoc.v:168389.3-168418.6" + process $proc$libresoc.v:168389$11090 + assign { } { } + assign { } { } + assign $0\wr_detect$13[0:0]$11091 $1\wr_detect$13[0:0]$11092 + attribute \src "libresoc.v:168390.5-168390.29" + switch \initial + attribute \src "libresoc.v:168390.9-168390.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r25__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$13[0:0]$11092 $4\wr_detect$13[0:0]$11095 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest15__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$13[0:0]$11093 1'1 + case + assign $2\wr_detect$13[0:0]$11093 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest25__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$13[0:0]$11094 1'1 + case + assign $3\wr_detect$13[0:0]$11094 $2\wr_detect$13[0:0]$11093 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w5__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$13[0:0]$11095 1'1 + case + assign $4\wr_detect$13[0:0]$11095 $3\wr_detect$13[0:0]$11094 + end + case + assign $1\wr_detect$13[0:0]$11092 1'0 + end + sync always + update \wr_detect$13 $0\wr_detect$13[0:0]$11091 + end + connect \$9 $not$libresoc.v:168025$11014_Y + connect \$12 $not$libresoc.v:168026$11015_Y + connect \$1 $not$libresoc.v:168027$11016_Y + connect \$3 $not$libresoc.v:168028$11017_Y + connect \$6 $not$libresoc.v:168029$11018_Y +end +attribute \src "libresoc.v:168423.1-168894.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.cr.reg_6" +attribute \generator "nMigen" +module \reg_6 + attribute \src "libresoc.v:168424.7-168424.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:168824.3-168863.6" + wire width 4 $0\r26__data_o$next[3:0]$11172 + attribute \src "libresoc.v:168507.3-168508.39" + wire width 4 $0\r26__data_o[3:0] + attribute \src "libresoc.v:168754.3-168793.6" + wire width 4 $0\r6__data_o$next[3:0]$11158 + attribute \src "libresoc.v:168509.3-168510.37" + wire width 4 $0\r6__data_o[3:0] + attribute \src "libresoc.v:168587.3-168613.6" + wire width 4 $0\reg$next[3:0]$11124 + attribute \src "libresoc.v:168505.3-168506.25" + wire width 4 $0\reg[3:0] + attribute \src "libresoc.v:168517.3-168556.6" + wire width 4 $0\src16__data_o$next[3:0]$11115 + attribute \src "libresoc.v:168515.3-168516.43" + wire width 4 $0\src16__data_o[3:0] + attribute \src "libresoc.v:168614.3-168653.6" + wire width 4 $0\src26__data_o$next[3:0]$11130 + attribute \src "libresoc.v:168513.3-168514.43" + wire width 4 $0\src26__data_o[3:0] + attribute \src "libresoc.v:168684.3-168723.6" + wire width 4 $0\src36__data_o$next[3:0]$11144 + attribute \src "libresoc.v:168511.3-168512.43" + wire width 4 $0\src36__data_o[3:0] + attribute \src "libresoc.v:168794.3-168823.6" + wire $0\wr_detect$10[0:0]$11166 + attribute \src "libresoc.v:168864.3-168893.6" + wire $0\wr_detect$13[0:0]$11180 + attribute \src "libresoc.v:168654.3-168683.6" + wire $0\wr_detect$4[0:0]$11138 + attribute \src "libresoc.v:168724.3-168753.6" + wire $0\wr_detect$7[0:0]$11152 + attribute \src "libresoc.v:168557.3-168586.6" + wire $0\wr_detect[0:0] + attribute \src "libresoc.v:168824.3-168863.6" + wire width 4 $1\r26__data_o$next[3:0]$11173 + attribute \src "libresoc.v:168449.13-168449.31" + wire width 4 $1\r26__data_o[3:0] + attribute \src "libresoc.v:168754.3-168793.6" + wire width 4 $1\r6__data_o$next[3:0]$11159 + attribute \src "libresoc.v:168456.13-168456.30" + wire width 4 $1\r6__data_o[3:0] + attribute \src "libresoc.v:168587.3-168613.6" + wire width 4 $1\reg$next[3:0]$11125 + attribute \src "libresoc.v:168462.13-168462.25" + wire width 4 $1\reg[3:0] + attribute \src "libresoc.v:168517.3-168556.6" + wire width 4 $1\src16__data_o$next[3:0]$11116 + attribute \src "libresoc.v:168467.13-168467.33" + wire width 4 $1\src16__data_o[3:0] + attribute \src "libresoc.v:168614.3-168653.6" + wire width 4 $1\src26__data_o$next[3:0]$11131 + attribute \src "libresoc.v:168474.13-168474.33" + wire width 4 $1\src26__data_o[3:0] + attribute \src "libresoc.v:168684.3-168723.6" + wire width 4 $1\src36__data_o$next[3:0]$11145 + attribute \src "libresoc.v:168481.13-168481.33" + wire width 4 $1\src36__data_o[3:0] + attribute \src "libresoc.v:168794.3-168823.6" + wire $1\wr_detect$10[0:0]$11167 + attribute \src "libresoc.v:168864.3-168893.6" + wire $1\wr_detect$13[0:0]$11181 + attribute \src "libresoc.v:168654.3-168683.6" + wire $1\wr_detect$4[0:0]$11139 + attribute \src "libresoc.v:168724.3-168753.6" + wire $1\wr_detect$7[0:0]$11153 + attribute \src "libresoc.v:168557.3-168586.6" + wire $1\wr_detect[0:0] + attribute \src "libresoc.v:168824.3-168863.6" + wire width 4 $2\r26__data_o$next[3:0]$11174 + attribute \src "libresoc.v:168754.3-168793.6" + wire width 4 $2\r6__data_o$next[3:0]$11160 + attribute \src "libresoc.v:168587.3-168613.6" + wire width 4 $2\reg$next[3:0]$11126 + attribute \src "libresoc.v:168517.3-168556.6" + wire width 4 $2\src16__data_o$next[3:0]$11117 + attribute \src "libresoc.v:168614.3-168653.6" + wire width 4 $2\src26__data_o$next[3:0]$11132 + attribute \src "libresoc.v:168684.3-168723.6" + wire width 4 $2\src36__data_o$next[3:0]$11146 + attribute \src "libresoc.v:168794.3-168823.6" + wire $2\wr_detect$10[0:0]$11168 + attribute \src "libresoc.v:168864.3-168893.6" + wire $2\wr_detect$13[0:0]$11182 + attribute \src "libresoc.v:168654.3-168683.6" + wire $2\wr_detect$4[0:0]$11140 + attribute \src "libresoc.v:168724.3-168753.6" + wire $2\wr_detect$7[0:0]$11154 + attribute \src "libresoc.v:168557.3-168586.6" + wire $2\wr_detect[0:0] + attribute \src "libresoc.v:168824.3-168863.6" + wire width 4 $3\r26__data_o$next[3:0]$11175 + attribute \src "libresoc.v:168754.3-168793.6" + wire width 4 $3\r6__data_o$next[3:0]$11161 + attribute \src "libresoc.v:168587.3-168613.6" + wire width 4 $3\reg$next[3:0]$11127 + attribute \src "libresoc.v:168517.3-168556.6" + wire width 4 $3\src16__data_o$next[3:0]$11118 + attribute \src "libresoc.v:168614.3-168653.6" + wire width 4 $3\src26__data_o$next[3:0]$11133 + attribute \src "libresoc.v:168684.3-168723.6" + wire width 4 $3\src36__data_o$next[3:0]$11147 + attribute \src "libresoc.v:168794.3-168823.6" + wire $3\wr_detect$10[0:0]$11169 + attribute \src "libresoc.v:168864.3-168893.6" + wire $3\wr_detect$13[0:0]$11183 + attribute \src "libresoc.v:168654.3-168683.6" + wire $3\wr_detect$4[0:0]$11141 + attribute \src "libresoc.v:168724.3-168753.6" + wire $3\wr_detect$7[0:0]$11155 + attribute \src "libresoc.v:168557.3-168586.6" + wire $3\wr_detect[0:0] + attribute \src "libresoc.v:168824.3-168863.6" + wire width 4 $4\r26__data_o$next[3:0]$11176 + attribute \src "libresoc.v:168754.3-168793.6" + wire width 4 $4\r6__data_o$next[3:0]$11162 + attribute \src "libresoc.v:168587.3-168613.6" + wire width 4 $4\reg$next[3:0]$11128 + attribute \src "libresoc.v:168517.3-168556.6" + wire width 4 $4\src16__data_o$next[3:0]$11119 + attribute \src "libresoc.v:168614.3-168653.6" + wire width 4 $4\src26__data_o$next[3:0]$11134 + attribute \src "libresoc.v:168684.3-168723.6" + wire width 4 $4\src36__data_o$next[3:0]$11148 + attribute \src "libresoc.v:168794.3-168823.6" + wire $4\wr_detect$10[0:0]$11170 + attribute \src "libresoc.v:168864.3-168893.6" + wire $4\wr_detect$13[0:0]$11184 + attribute \src "libresoc.v:168654.3-168683.6" + wire $4\wr_detect$4[0:0]$11142 + attribute \src "libresoc.v:168724.3-168753.6" + wire $4\wr_detect$7[0:0]$11156 + attribute \src "libresoc.v:168557.3-168586.6" + wire $4\wr_detect[0:0] + attribute \src "libresoc.v:168824.3-168863.6" + wire width 4 $5\r26__data_o$next[3:0]$11177 + attribute \src "libresoc.v:168754.3-168793.6" + wire width 4 $5\r6__data_o$next[3:0]$11163 + attribute \src "libresoc.v:168517.3-168556.6" + wire width 4 $5\src16__data_o$next[3:0]$11120 + attribute \src "libresoc.v:168614.3-168653.6" + wire width 4 $5\src26__data_o$next[3:0]$11135 + attribute \src "libresoc.v:168684.3-168723.6" + wire width 4 $5\src36__data_o$next[3:0]$11149 + attribute \src "libresoc.v:168824.3-168863.6" + wire width 4 $6\r26__data_o$next[3:0]$11178 + attribute \src "libresoc.v:168754.3-168793.6" + wire width 4 $6\r6__data_o$next[3:0]$11164 + attribute \src "libresoc.v:168517.3-168556.6" + wire width 4 $6\src16__data_o$next[3:0]$11121 + attribute \src "libresoc.v:168614.3-168653.6" + wire width 4 $6\src26__data_o$next[3:0]$11136 + attribute \src "libresoc.v:168684.3-168723.6" + wire width 4 $6\src36__data_o$next[3:0]$11150 + attribute \src "libresoc.v:168500.17-168500.104" + wire $not$libresoc.v:168500$11103_Y + attribute \src "libresoc.v:168501.18-168501.105" + wire $not$libresoc.v:168501$11104_Y + attribute \src "libresoc.v:168502.17-168502.100" + wire $not$libresoc.v:168502$11105_Y + attribute \src "libresoc.v:168503.17-168503.103" + wire $not$libresoc.v:168503$11106_Y + attribute \src "libresoc.v:168504.17-168504.103" + wire $not$libresoc.v:168504$11107_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 18 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 input 9 \dest16__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 8 \dest16__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 input 11 \dest26__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 10 \dest26__wen + attribute \src "libresoc.v:168424.7-168424.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 14 \r26__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \r26__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 15 \r26__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 12 \r6__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \r6__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 13 \r6__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 4 \reg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 4 \reg$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 3 \src16__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \src16__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 2 \src16__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 5 \src26__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \src26__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 4 \src26__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 7 \src36__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \src36__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 6 \src36__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 input 16 \w6__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 17 \w6__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:168500$11103 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$10 + connect \Y $not$libresoc.v:168500$11103_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:168501$11104 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$13 + connect \Y $not$libresoc.v:168501$11104_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:168502$11105 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect + connect \Y $not$libresoc.v:168502$11105_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:168503$11106 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$4 + connect \Y $not$libresoc.v:168503$11106_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:168504$11107 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$7 + connect \Y $not$libresoc.v:168504$11107_Y + end + attribute \src "libresoc.v:168424.7-168424.20" + process $proc$libresoc.v:168424$11185 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:168449.13-168449.31" + process $proc$libresoc.v:168449$11186 + assign { } { } + assign $1\r26__data_o[3:0] 4'0000 + sync always + sync init + update \r26__data_o $1\r26__data_o[3:0] + end + attribute \src "libresoc.v:168456.13-168456.30" + process $proc$libresoc.v:168456$11187 + assign { } { } + assign $1\r6__data_o[3:0] 4'0000 + sync always + sync init + update \r6__data_o $1\r6__data_o[3:0] + end + attribute \src "libresoc.v:168462.13-168462.25" + process $proc$libresoc.v:168462$11188 + assign { } { } + assign $1\reg[3:0] 4'0000 + sync always + sync init + update \reg $1\reg[3:0] + end + attribute \src "libresoc.v:168467.13-168467.33" + process $proc$libresoc.v:168467$11189 + assign { } { } + assign $1\src16__data_o[3:0] 4'0000 + sync always + sync init + update \src16__data_o $1\src16__data_o[3:0] + end + attribute \src "libresoc.v:168474.13-168474.33" + process $proc$libresoc.v:168474$11190 + assign { } { } + assign $1\src26__data_o[3:0] 4'0000 + sync always + sync init + update \src26__data_o $1\src26__data_o[3:0] + end + attribute \src "libresoc.v:168481.13-168481.33" + process $proc$libresoc.v:168481$11191 + assign { } { } + assign $1\src36__data_o[3:0] 4'0000 + sync always + sync init + update \src36__data_o $1\src36__data_o[3:0] + end + attribute \src "libresoc.v:168505.3-168506.25" + process $proc$libresoc.v:168505$11108 + assign { } { } + assign $0\reg[3:0] \reg$next + sync posedge \coresync_clk + update \reg $0\reg[3:0] + end + attribute \src "libresoc.v:168507.3-168508.39" + process $proc$libresoc.v:168507$11109 + assign { } { } + assign $0\r26__data_o[3:0] \r26__data_o$next + sync posedge \coresync_clk + update \r26__data_o $0\r26__data_o[3:0] + end + attribute \src "libresoc.v:168509.3-168510.37" + process $proc$libresoc.v:168509$11110 + assign { } { } + assign $0\r6__data_o[3:0] \r6__data_o$next + sync posedge \coresync_clk + update \r6__data_o $0\r6__data_o[3:0] + end + attribute \src "libresoc.v:168511.3-168512.43" + process $proc$libresoc.v:168511$11111 + assign { } { } + assign $0\src36__data_o[3:0] \src36__data_o$next + sync posedge \coresync_clk + update \src36__data_o $0\src36__data_o[3:0] + end + attribute \src "libresoc.v:168513.3-168514.43" + process $proc$libresoc.v:168513$11112 + assign { } { } + assign $0\src26__data_o[3:0] \src26__data_o$next + sync posedge \coresync_clk + update \src26__data_o $0\src26__data_o[3:0] + end + attribute \src "libresoc.v:168515.3-168516.43" + process $proc$libresoc.v:168515$11113 + assign { } { } + assign $0\src16__data_o[3:0] \src16__data_o$next + sync posedge \coresync_clk + update \src16__data_o $0\src16__data_o[3:0] + end + attribute \src "libresoc.v:168517.3-168556.6" + process $proc$libresoc.v:168517$11114 + assign { } { } + assign { } { } + assign { } { } + assign $0\src16__data_o$next[3:0]$11115 $6\src16__data_o$next[3:0]$11121 + attribute \src "libresoc.v:168518.5-168518.29" + switch \initial + attribute \src "libresoc.v:168518.9-168518.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src16__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src16__data_o$next[3:0]$11116 $5\src16__data_o$next[3:0]$11120 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest16__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src16__data_o$next[3:0]$11117 \dest16__data_i + case + assign $2\src16__data_o$next[3:0]$11117 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest26__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src16__data_o$next[3:0]$11118 \dest26__data_i + case + assign $3\src16__data_o$next[3:0]$11118 $2\src16__data_o$next[3:0]$11117 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w6__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src16__data_o$next[3:0]$11119 \w6__data_i + case + assign $4\src16__data_o$next[3:0]$11119 $3\src16__data_o$next[3:0]$11118 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src16__data_o$next[3:0]$11120 \reg + case + assign $5\src16__data_o$next[3:0]$11120 $4\src16__data_o$next[3:0]$11119 + end + case + assign $1\src16__data_o$next[3:0]$11116 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src16__data_o$next[3:0]$11121 4'0000 + case + assign $6\src16__data_o$next[3:0]$11121 $1\src16__data_o$next[3:0]$11116 + end + sync always + update \src16__data_o$next $0\src16__data_o$next[3:0]$11115 + end + attribute \src "libresoc.v:168557.3-168586.6" + process $proc$libresoc.v:168557$11122 + assign { } { } + assign { } { } + assign $0\wr_detect[0:0] $1\wr_detect[0:0] + attribute \src "libresoc.v:168558.5-168558.29" + switch \initial + attribute \src "libresoc.v:168558.9-168558.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src16__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect[0:0] $4\wr_detect[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest16__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect[0:0] 1'1 + case + assign $2\wr_detect[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest26__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect[0:0] 1'1 + case + assign $3\wr_detect[0:0] $2\wr_detect[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w6__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect[0:0] 1'1 + case + assign $4\wr_detect[0:0] $3\wr_detect[0:0] + end + case + assign $1\wr_detect[0:0] 1'0 + end + sync always + update \wr_detect $0\wr_detect[0:0] + end + attribute \src "libresoc.v:168587.3-168613.6" + process $proc$libresoc.v:168587$11123 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\reg$next[3:0]$11124 $4\reg$next[3:0]$11128 + attribute \src "libresoc.v:168588.5-168588.29" + switch \initial + attribute \src "libresoc.v:168588.9-168588.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest16__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\reg$next[3:0]$11125 \dest16__data_i + case + assign $1\reg$next[3:0]$11125 \reg + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest26__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\reg$next[3:0]$11126 \dest26__data_i + case + assign $2\reg$next[3:0]$11126 $1\reg$next[3:0]$11125 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \w6__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\reg$next[3:0]$11127 \w6__data_i + case + assign $3\reg$next[3:0]$11127 $2\reg$next[3:0]$11126 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\reg$next[3:0]$11128 4'0000 + case + assign $4\reg$next[3:0]$11128 $3\reg$next[3:0]$11127 + end + sync always + update \reg$next $0\reg$next[3:0]$11124 + end + attribute \src "libresoc.v:168614.3-168653.6" + process $proc$libresoc.v:168614$11129 + assign { } { } + assign { } { } + assign { } { } + assign $0\src26__data_o$next[3:0]$11130 $6\src26__data_o$next[3:0]$11136 + attribute \src "libresoc.v:168615.5-168615.29" + switch \initial + attribute \src "libresoc.v:168615.9-168615.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src26__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src26__data_o$next[3:0]$11131 $5\src26__data_o$next[3:0]$11135 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest16__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src26__data_o$next[3:0]$11132 \dest16__data_i + case + assign $2\src26__data_o$next[3:0]$11132 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest26__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src26__data_o$next[3:0]$11133 \dest26__data_i + case + assign $3\src26__data_o$next[3:0]$11133 $2\src26__data_o$next[3:0]$11132 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w6__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src26__data_o$next[3:0]$11134 \w6__data_i + case + assign $4\src26__data_o$next[3:0]$11134 $3\src26__data_o$next[3:0]$11133 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src26__data_o$next[3:0]$11135 \reg + case + assign $5\src26__data_o$next[3:0]$11135 $4\src26__data_o$next[3:0]$11134 + end + case + assign $1\src26__data_o$next[3:0]$11131 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src26__data_o$next[3:0]$11136 4'0000 + case + assign $6\src26__data_o$next[3:0]$11136 $1\src26__data_o$next[3:0]$11131 + end + sync always + update \src26__data_o$next $0\src26__data_o$next[3:0]$11130 + end + attribute \src "libresoc.v:168654.3-168683.6" + process $proc$libresoc.v:168654$11137 + assign { } { } + assign { } { } + assign $0\wr_detect$4[0:0]$11138 $1\wr_detect$4[0:0]$11139 + attribute \src "libresoc.v:168655.5-168655.29" + switch \initial + attribute \src "libresoc.v:168655.9-168655.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src26__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$4[0:0]$11139 $4\wr_detect$4[0:0]$11142 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest16__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$4[0:0]$11140 1'1 + case + assign $2\wr_detect$4[0:0]$11140 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest26__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$4[0:0]$11141 1'1 + case + assign $3\wr_detect$4[0:0]$11141 $2\wr_detect$4[0:0]$11140 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w6__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$4[0:0]$11142 1'1 + case + assign $4\wr_detect$4[0:0]$11142 $3\wr_detect$4[0:0]$11141 + end + case + assign $1\wr_detect$4[0:0]$11139 1'0 + end + sync always + update \wr_detect$4 $0\wr_detect$4[0:0]$11138 + end + attribute \src "libresoc.v:168684.3-168723.6" + process $proc$libresoc.v:168684$11143 + assign { } { } + assign { } { } + assign { } { } + assign $0\src36__data_o$next[3:0]$11144 $6\src36__data_o$next[3:0]$11150 + attribute \src "libresoc.v:168685.5-168685.29" + switch \initial + attribute \src "libresoc.v:168685.9-168685.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src36__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src36__data_o$next[3:0]$11145 $5\src36__data_o$next[3:0]$11149 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest16__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src36__data_o$next[3:0]$11146 \dest16__data_i + case + assign $2\src36__data_o$next[3:0]$11146 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest26__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src36__data_o$next[3:0]$11147 \dest26__data_i + case + assign $3\src36__data_o$next[3:0]$11147 $2\src36__data_o$next[3:0]$11146 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w6__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src36__data_o$next[3:0]$11148 \w6__data_i + case + assign $4\src36__data_o$next[3:0]$11148 $3\src36__data_o$next[3:0]$11147 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$6 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src36__data_o$next[3:0]$11149 \reg + case + assign $5\src36__data_o$next[3:0]$11149 $4\src36__data_o$next[3:0]$11148 + end + case + assign $1\src36__data_o$next[3:0]$11145 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src36__data_o$next[3:0]$11150 4'0000 + case + assign $6\src36__data_o$next[3:0]$11150 $1\src36__data_o$next[3:0]$11145 + end + sync always + update \src36__data_o$next $0\src36__data_o$next[3:0]$11144 + end + attribute \src "libresoc.v:168724.3-168753.6" + process $proc$libresoc.v:168724$11151 + assign { } { } + assign { } { } + assign $0\wr_detect$7[0:0]$11152 $1\wr_detect$7[0:0]$11153 + attribute \src "libresoc.v:168725.5-168725.29" + switch \initial + attribute \src "libresoc.v:168725.9-168725.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src36__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$7[0:0]$11153 $4\wr_detect$7[0:0]$11156 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest16__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$7[0:0]$11154 1'1 + case + assign $2\wr_detect$7[0:0]$11154 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest26__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$7[0:0]$11155 1'1 + case + assign $3\wr_detect$7[0:0]$11155 $2\wr_detect$7[0:0]$11154 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w6__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$7[0:0]$11156 1'1 + case + assign $4\wr_detect$7[0:0]$11156 $3\wr_detect$7[0:0]$11155 + end + case + assign $1\wr_detect$7[0:0]$11153 1'0 + end + sync always + update \wr_detect$7 $0\wr_detect$7[0:0]$11152 + end + attribute \src "libresoc.v:168754.3-168793.6" + process $proc$libresoc.v:168754$11157 + assign { } { } + assign { } { } + assign { } { } + assign $0\r6__data_o$next[3:0]$11158 $6\r6__data_o$next[3:0]$11164 + attribute \src "libresoc.v:168755.5-168755.29" + switch \initial + attribute \src "libresoc.v:168755.9-168755.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r6__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\r6__data_o$next[3:0]$11159 $5\r6__data_o$next[3:0]$11163 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest16__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r6__data_o$next[3:0]$11160 \dest16__data_i + case + assign $2\r6__data_o$next[3:0]$11160 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest26__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\r6__data_o$next[3:0]$11161 \dest26__data_i + case + assign $3\r6__data_o$next[3:0]$11161 $2\r6__data_o$next[3:0]$11160 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w6__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\r6__data_o$next[3:0]$11162 \w6__data_i + case + assign $4\r6__data_o$next[3:0]$11162 $3\r6__data_o$next[3:0]$11161 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$9 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\r6__data_o$next[3:0]$11163 \reg + case + assign $5\r6__data_o$next[3:0]$11163 $4\r6__data_o$next[3:0]$11162 + end + case + assign $1\r6__data_o$next[3:0]$11159 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\r6__data_o$next[3:0]$11164 4'0000 + case + assign $6\r6__data_o$next[3:0]$11164 $1\r6__data_o$next[3:0]$11159 + end + sync always + update \r6__data_o$next $0\r6__data_o$next[3:0]$11158 + end + attribute \src "libresoc.v:168794.3-168823.6" + process $proc$libresoc.v:168794$11165 + assign { } { } + assign { } { } + assign $0\wr_detect$10[0:0]$11166 $1\wr_detect$10[0:0]$11167 + attribute \src "libresoc.v:168795.5-168795.29" + switch \initial + attribute \src "libresoc.v:168795.9-168795.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r6__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$10[0:0]$11167 $4\wr_detect$10[0:0]$11170 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest16__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$10[0:0]$11168 1'1 + case + assign $2\wr_detect$10[0:0]$11168 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest26__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$10[0:0]$11169 1'1 + case + assign $3\wr_detect$10[0:0]$11169 $2\wr_detect$10[0:0]$11168 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w6__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$10[0:0]$11170 1'1 + case + assign $4\wr_detect$10[0:0]$11170 $3\wr_detect$10[0:0]$11169 + end + case + assign $1\wr_detect$10[0:0]$11167 1'0 + end + sync always + update \wr_detect$10 $0\wr_detect$10[0:0]$11166 + end + attribute \src "libresoc.v:168824.3-168863.6" + process $proc$libresoc.v:168824$11171 + assign { } { } + assign { } { } + assign { } { } + assign $0\r26__data_o$next[3:0]$11172 $6\r26__data_o$next[3:0]$11178 + attribute \src "libresoc.v:168825.5-168825.29" + switch \initial + attribute \src "libresoc.v:168825.9-168825.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r26__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\r26__data_o$next[3:0]$11173 $5\r26__data_o$next[3:0]$11177 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest16__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r26__data_o$next[3:0]$11174 \dest16__data_i + case + assign $2\r26__data_o$next[3:0]$11174 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest26__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\r26__data_o$next[3:0]$11175 \dest26__data_i + case + assign $3\r26__data_o$next[3:0]$11175 $2\r26__data_o$next[3:0]$11174 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w6__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\r26__data_o$next[3:0]$11176 \w6__data_i + case + assign $4\r26__data_o$next[3:0]$11176 $3\r26__data_o$next[3:0]$11175 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$12 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\r26__data_o$next[3:0]$11177 \reg + case + assign $5\r26__data_o$next[3:0]$11177 $4\r26__data_o$next[3:0]$11176 + end + case + assign $1\r26__data_o$next[3:0]$11173 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\r26__data_o$next[3:0]$11178 4'0000 + case + assign $6\r26__data_o$next[3:0]$11178 $1\r26__data_o$next[3:0]$11173 + end + sync always + update \r26__data_o$next $0\r26__data_o$next[3:0]$11172 + end + attribute \src "libresoc.v:168864.3-168893.6" + process $proc$libresoc.v:168864$11179 + assign { } { } + assign { } { } + assign $0\wr_detect$13[0:0]$11180 $1\wr_detect$13[0:0]$11181 + attribute \src "libresoc.v:168865.5-168865.29" + switch \initial + attribute \src "libresoc.v:168865.9-168865.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r26__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$13[0:0]$11181 $4\wr_detect$13[0:0]$11184 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest16__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$13[0:0]$11182 1'1 + case + assign $2\wr_detect$13[0:0]$11182 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest26__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$13[0:0]$11183 1'1 + case + assign $3\wr_detect$13[0:0]$11183 $2\wr_detect$13[0:0]$11182 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w6__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$13[0:0]$11184 1'1 + case + assign $4\wr_detect$13[0:0]$11184 $3\wr_detect$13[0:0]$11183 + end + case + assign $1\wr_detect$13[0:0]$11181 1'0 + end + sync always + update \wr_detect$13 $0\wr_detect$13[0:0]$11180 + end + connect \$9 $not$libresoc.v:168500$11103_Y + connect \$12 $not$libresoc.v:168501$11104_Y + connect \$1 $not$libresoc.v:168502$11105_Y + connect \$3 $not$libresoc.v:168503$11106_Y + connect \$6 $not$libresoc.v:168504$11107_Y +end +attribute \src "libresoc.v:168898.1-169369.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.cr.reg_7" +attribute \generator "nMigen" +module \reg_7 + attribute \src "libresoc.v:168899.7-168899.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:169299.3-169338.6" + wire width 4 $0\r27__data_o$next[3:0]$11261 + attribute \src "libresoc.v:168982.3-168983.39" + wire width 4 $0\r27__data_o[3:0] + attribute \src "libresoc.v:169229.3-169268.6" + wire width 4 $0\r7__data_o$next[3:0]$11247 + attribute \src "libresoc.v:168984.3-168985.37" + wire width 4 $0\r7__data_o[3:0] + attribute \src "libresoc.v:169062.3-169088.6" + wire width 4 $0\reg$next[3:0]$11213 + attribute \src "libresoc.v:168980.3-168981.25" + wire width 4 $0\reg[3:0] + attribute \src "libresoc.v:168992.3-169031.6" + wire width 4 $0\src17__data_o$next[3:0]$11204 + attribute \src "libresoc.v:168990.3-168991.43" + wire width 4 $0\src17__data_o[3:0] + attribute \src "libresoc.v:169089.3-169128.6" + wire width 4 $0\src27__data_o$next[3:0]$11219 + attribute \src "libresoc.v:168988.3-168989.43" + wire width 4 $0\src27__data_o[3:0] + attribute \src "libresoc.v:169159.3-169198.6" + wire width 4 $0\src37__data_o$next[3:0]$11233 + attribute \src "libresoc.v:168986.3-168987.43" + wire width 4 $0\src37__data_o[3:0] + attribute \src "libresoc.v:169269.3-169298.6" + wire $0\wr_detect$10[0:0]$11255 + attribute \src "libresoc.v:169339.3-169368.6" + wire $0\wr_detect$13[0:0]$11269 + attribute \src "libresoc.v:169129.3-169158.6" + wire $0\wr_detect$4[0:0]$11227 + attribute \src "libresoc.v:169199.3-169228.6" + wire $0\wr_detect$7[0:0]$11241 + attribute \src "libresoc.v:169032.3-169061.6" + wire $0\wr_detect[0:0] + attribute \src "libresoc.v:169299.3-169338.6" + wire width 4 $1\r27__data_o$next[3:0]$11262 + attribute \src "libresoc.v:168924.13-168924.31" + wire width 4 $1\r27__data_o[3:0] + attribute \src "libresoc.v:169229.3-169268.6" + wire width 4 $1\r7__data_o$next[3:0]$11248 + attribute \src "libresoc.v:168931.13-168931.30" + wire width 4 $1\r7__data_o[3:0] + attribute \src "libresoc.v:169062.3-169088.6" + wire width 4 $1\reg$next[3:0]$11214 + attribute \src "libresoc.v:168937.13-168937.25" + wire width 4 $1\reg[3:0] + attribute \src "libresoc.v:168992.3-169031.6" + wire width 4 $1\src17__data_o$next[3:0]$11205 + attribute \src "libresoc.v:168942.13-168942.33" + wire width 4 $1\src17__data_o[3:0] + attribute \src "libresoc.v:169089.3-169128.6" + wire width 4 $1\src27__data_o$next[3:0]$11220 + attribute \src "libresoc.v:168949.13-168949.33" + wire width 4 $1\src27__data_o[3:0] + attribute \src "libresoc.v:169159.3-169198.6" + wire width 4 $1\src37__data_o$next[3:0]$11234 + attribute \src "libresoc.v:168956.13-168956.33" + wire width 4 $1\src37__data_o[3:0] + attribute \src "libresoc.v:169269.3-169298.6" + wire $1\wr_detect$10[0:0]$11256 + attribute \src "libresoc.v:169339.3-169368.6" + wire $1\wr_detect$13[0:0]$11270 + attribute \src "libresoc.v:169129.3-169158.6" + wire $1\wr_detect$4[0:0]$11228 + attribute \src "libresoc.v:169199.3-169228.6" + wire $1\wr_detect$7[0:0]$11242 + attribute \src "libresoc.v:169032.3-169061.6" + wire $1\wr_detect[0:0] + attribute \src "libresoc.v:169299.3-169338.6" + wire width 4 $2\r27__data_o$next[3:0]$11263 + attribute \src "libresoc.v:169229.3-169268.6" + wire width 4 $2\r7__data_o$next[3:0]$11249 + attribute \src "libresoc.v:169062.3-169088.6" + wire width 4 $2\reg$next[3:0]$11215 + attribute \src "libresoc.v:168992.3-169031.6" + wire width 4 $2\src17__data_o$next[3:0]$11206 + attribute \src "libresoc.v:169089.3-169128.6" + wire width 4 $2\src27__data_o$next[3:0]$11221 + attribute \src "libresoc.v:169159.3-169198.6" + wire width 4 $2\src37__data_o$next[3:0]$11235 + attribute \src "libresoc.v:169269.3-169298.6" + wire $2\wr_detect$10[0:0]$11257 + attribute \src "libresoc.v:169339.3-169368.6" + wire $2\wr_detect$13[0:0]$11271 + attribute \src "libresoc.v:169129.3-169158.6" + wire $2\wr_detect$4[0:0]$11229 + attribute \src "libresoc.v:169199.3-169228.6" + wire $2\wr_detect$7[0:0]$11243 + attribute \src "libresoc.v:169032.3-169061.6" + wire $2\wr_detect[0:0] + attribute \src "libresoc.v:169299.3-169338.6" + wire width 4 $3\r27__data_o$next[3:0]$11264 + attribute \src "libresoc.v:169229.3-169268.6" + wire width 4 $3\r7__data_o$next[3:0]$11250 + attribute \src "libresoc.v:169062.3-169088.6" + wire width 4 $3\reg$next[3:0]$11216 + attribute \src "libresoc.v:168992.3-169031.6" + wire width 4 $3\src17__data_o$next[3:0]$11207 + attribute \src "libresoc.v:169089.3-169128.6" + wire width 4 $3\src27__data_o$next[3:0]$11222 + attribute \src "libresoc.v:169159.3-169198.6" + wire width 4 $3\src37__data_o$next[3:0]$11236 + attribute \src "libresoc.v:169269.3-169298.6" + wire $3\wr_detect$10[0:0]$11258 + attribute \src "libresoc.v:169339.3-169368.6" + wire $3\wr_detect$13[0:0]$11272 + attribute \src "libresoc.v:169129.3-169158.6" + wire $3\wr_detect$4[0:0]$11230 + attribute \src "libresoc.v:169199.3-169228.6" + wire $3\wr_detect$7[0:0]$11244 + attribute \src "libresoc.v:169032.3-169061.6" + wire $3\wr_detect[0:0] + attribute \src "libresoc.v:169299.3-169338.6" + wire width 4 $4\r27__data_o$next[3:0]$11265 + attribute \src "libresoc.v:169229.3-169268.6" + wire width 4 $4\r7__data_o$next[3:0]$11251 + attribute \src "libresoc.v:169062.3-169088.6" + wire width 4 $4\reg$next[3:0]$11217 + attribute \src "libresoc.v:168992.3-169031.6" + wire width 4 $4\src17__data_o$next[3:0]$11208 + attribute \src "libresoc.v:169089.3-169128.6" + wire width 4 $4\src27__data_o$next[3:0]$11223 + attribute \src "libresoc.v:169159.3-169198.6" + wire width 4 $4\src37__data_o$next[3:0]$11237 + attribute \src "libresoc.v:169269.3-169298.6" + wire $4\wr_detect$10[0:0]$11259 + attribute \src "libresoc.v:169339.3-169368.6" + wire $4\wr_detect$13[0:0]$11273 + attribute \src "libresoc.v:169129.3-169158.6" + wire $4\wr_detect$4[0:0]$11231 + attribute \src "libresoc.v:169199.3-169228.6" + wire $4\wr_detect$7[0:0]$11245 + attribute \src "libresoc.v:169032.3-169061.6" + wire $4\wr_detect[0:0] + attribute \src "libresoc.v:169299.3-169338.6" + wire width 4 $5\r27__data_o$next[3:0]$11266 + attribute \src "libresoc.v:169229.3-169268.6" + wire width 4 $5\r7__data_o$next[3:0]$11252 + attribute \src "libresoc.v:168992.3-169031.6" + wire width 4 $5\src17__data_o$next[3:0]$11209 + attribute \src "libresoc.v:169089.3-169128.6" + wire width 4 $5\src27__data_o$next[3:0]$11224 + attribute \src "libresoc.v:169159.3-169198.6" + wire width 4 $5\src37__data_o$next[3:0]$11238 + attribute \src "libresoc.v:169299.3-169338.6" + wire width 4 $6\r27__data_o$next[3:0]$11267 + attribute \src "libresoc.v:169229.3-169268.6" + wire width 4 $6\r7__data_o$next[3:0]$11253 + attribute \src "libresoc.v:168992.3-169031.6" + wire width 4 $6\src17__data_o$next[3:0]$11210 + attribute \src "libresoc.v:169089.3-169128.6" + wire width 4 $6\src27__data_o$next[3:0]$11225 + attribute \src "libresoc.v:169159.3-169198.6" + wire width 4 $6\src37__data_o$next[3:0]$11239 + attribute \src "libresoc.v:168975.17-168975.104" + wire $not$libresoc.v:168975$11192_Y + attribute \src "libresoc.v:168976.18-168976.105" + wire $not$libresoc.v:168976$11193_Y + attribute \src "libresoc.v:168977.17-168977.100" + wire $not$libresoc.v:168977$11194_Y + attribute \src "libresoc.v:168978.17-168978.103" + wire $not$libresoc.v:168978$11195_Y + attribute \src "libresoc.v:168979.17-168979.103" + wire $not$libresoc.v:168979$11196_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 18 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 input 9 \dest17__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 8 \dest17__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 input 11 \dest27__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 10 \dest27__wen + attribute \src "libresoc.v:168899.7-168899.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 14 \r27__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \r27__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 15 \r27__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 12 \r7__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \r7__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 13 \r7__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 4 \reg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 4 \reg$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 3 \src17__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \src17__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 2 \src17__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 5 \src27__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \src27__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 4 \src27__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 7 \src37__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \src37__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 6 \src37__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 input 16 \w7__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 17 \w7__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:168975$11192 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$10 + connect \Y $not$libresoc.v:168975$11192_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:168976$11193 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$13 + connect \Y $not$libresoc.v:168976$11193_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:168977$11194 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect + connect \Y $not$libresoc.v:168977$11194_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:168978$11195 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$4 + connect \Y $not$libresoc.v:168978$11195_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:168979$11196 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$7 + connect \Y $not$libresoc.v:168979$11196_Y + end + attribute \src "libresoc.v:168899.7-168899.20" + process $proc$libresoc.v:168899$11274 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:168924.13-168924.31" + process $proc$libresoc.v:168924$11275 + assign { } { } + assign $1\r27__data_o[3:0] 4'0000 + sync always + sync init + update \r27__data_o $1\r27__data_o[3:0] + end + attribute \src "libresoc.v:168931.13-168931.30" + process $proc$libresoc.v:168931$11276 + assign { } { } + assign $1\r7__data_o[3:0] 4'0000 + sync always + sync init + update \r7__data_o $1\r7__data_o[3:0] + end + attribute \src "libresoc.v:168937.13-168937.25" + process $proc$libresoc.v:168937$11277 + assign { } { } + assign $1\reg[3:0] 4'0000 + sync always + sync init + update \reg $1\reg[3:0] + end + attribute \src "libresoc.v:168942.13-168942.33" + process $proc$libresoc.v:168942$11278 + assign { } { } + assign $1\src17__data_o[3:0] 4'0000 + sync always + sync init + update \src17__data_o $1\src17__data_o[3:0] + end + attribute \src "libresoc.v:168949.13-168949.33" + process $proc$libresoc.v:168949$11279 + assign { } { } + assign $1\src27__data_o[3:0] 4'0000 + sync always + sync init + update \src27__data_o $1\src27__data_o[3:0] + end + attribute \src "libresoc.v:168956.13-168956.33" + process $proc$libresoc.v:168956$11280 + assign { } { } + assign $1\src37__data_o[3:0] 4'0000 + sync always + sync init + update \src37__data_o $1\src37__data_o[3:0] + end + attribute \src "libresoc.v:168980.3-168981.25" + process $proc$libresoc.v:168980$11197 + assign { } { } + assign $0\reg[3:0] \reg$next + sync posedge \coresync_clk + update \reg $0\reg[3:0] + end + attribute \src "libresoc.v:168982.3-168983.39" + process $proc$libresoc.v:168982$11198 + assign { } { } + assign $0\r27__data_o[3:0] \r27__data_o$next + sync posedge \coresync_clk + update \r27__data_o $0\r27__data_o[3:0] + end + attribute \src "libresoc.v:168984.3-168985.37" + process $proc$libresoc.v:168984$11199 + assign { } { } + assign $0\r7__data_o[3:0] \r7__data_o$next + sync posedge \coresync_clk + update \r7__data_o $0\r7__data_o[3:0] + end + attribute \src "libresoc.v:168986.3-168987.43" + process $proc$libresoc.v:168986$11200 + assign { } { } + assign $0\src37__data_o[3:0] \src37__data_o$next + sync posedge \coresync_clk + update \src37__data_o $0\src37__data_o[3:0] + end + attribute \src "libresoc.v:168988.3-168989.43" + process $proc$libresoc.v:168988$11201 + assign { } { } + assign $0\src27__data_o[3:0] \src27__data_o$next + sync posedge \coresync_clk + update \src27__data_o $0\src27__data_o[3:0] + end + attribute \src "libresoc.v:168990.3-168991.43" + process $proc$libresoc.v:168990$11202 + assign { } { } + assign $0\src17__data_o[3:0] \src17__data_o$next + sync posedge \coresync_clk + update \src17__data_o $0\src17__data_o[3:0] + end + attribute \src "libresoc.v:168992.3-169031.6" + process $proc$libresoc.v:168992$11203 + assign { } { } + assign { } { } + assign { } { } + assign $0\src17__data_o$next[3:0]$11204 $6\src17__data_o$next[3:0]$11210 + attribute \src "libresoc.v:168993.5-168993.29" + switch \initial + attribute \src "libresoc.v:168993.9-168993.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src17__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src17__data_o$next[3:0]$11205 $5\src17__data_o$next[3:0]$11209 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest17__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src17__data_o$next[3:0]$11206 \dest17__data_i + case + assign $2\src17__data_o$next[3:0]$11206 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest27__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src17__data_o$next[3:0]$11207 \dest27__data_i + case + assign $3\src17__data_o$next[3:0]$11207 $2\src17__data_o$next[3:0]$11206 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w7__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src17__data_o$next[3:0]$11208 \w7__data_i + case + assign $4\src17__data_o$next[3:0]$11208 $3\src17__data_o$next[3:0]$11207 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src17__data_o$next[3:0]$11209 \reg + case + assign $5\src17__data_o$next[3:0]$11209 $4\src17__data_o$next[3:0]$11208 + end + case + assign $1\src17__data_o$next[3:0]$11205 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src17__data_o$next[3:0]$11210 4'0000 + case + assign $6\src17__data_o$next[3:0]$11210 $1\src17__data_o$next[3:0]$11205 + end + sync always + update \src17__data_o$next $0\src17__data_o$next[3:0]$11204 + end + attribute \src "libresoc.v:169032.3-169061.6" + process $proc$libresoc.v:169032$11211 + assign { } { } + assign { } { } + assign $0\wr_detect[0:0] $1\wr_detect[0:0] + attribute \src "libresoc.v:169033.5-169033.29" + switch \initial + attribute \src "libresoc.v:169033.9-169033.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src17__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect[0:0] $4\wr_detect[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest17__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect[0:0] 1'1 + case + assign $2\wr_detect[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest27__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect[0:0] 1'1 + case + assign $3\wr_detect[0:0] $2\wr_detect[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w7__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect[0:0] 1'1 + case + assign $4\wr_detect[0:0] $3\wr_detect[0:0] + end + case + assign $1\wr_detect[0:0] 1'0 + end + sync always + update \wr_detect $0\wr_detect[0:0] + end + attribute \src "libresoc.v:169062.3-169088.6" + process $proc$libresoc.v:169062$11212 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\reg$next[3:0]$11213 $4\reg$next[3:0]$11217 + attribute \src "libresoc.v:169063.5-169063.29" + switch \initial + attribute \src "libresoc.v:169063.9-169063.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest17__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\reg$next[3:0]$11214 \dest17__data_i + case + assign $1\reg$next[3:0]$11214 \reg + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest27__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\reg$next[3:0]$11215 \dest27__data_i + case + assign $2\reg$next[3:0]$11215 $1\reg$next[3:0]$11214 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \w7__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\reg$next[3:0]$11216 \w7__data_i + case + assign $3\reg$next[3:0]$11216 $2\reg$next[3:0]$11215 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\reg$next[3:0]$11217 4'0000 + case + assign $4\reg$next[3:0]$11217 $3\reg$next[3:0]$11216 + end + sync always + update \reg$next $0\reg$next[3:0]$11213 + end + attribute \src "libresoc.v:169089.3-169128.6" + process $proc$libresoc.v:169089$11218 + assign { } { } + assign { } { } + assign { } { } + assign $0\src27__data_o$next[3:0]$11219 $6\src27__data_o$next[3:0]$11225 + attribute \src "libresoc.v:169090.5-169090.29" + switch \initial + attribute \src "libresoc.v:169090.9-169090.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src27__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src27__data_o$next[3:0]$11220 $5\src27__data_o$next[3:0]$11224 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest17__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src27__data_o$next[3:0]$11221 \dest17__data_i + case + assign $2\src27__data_o$next[3:0]$11221 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest27__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src27__data_o$next[3:0]$11222 \dest27__data_i + case + assign $3\src27__data_o$next[3:0]$11222 $2\src27__data_o$next[3:0]$11221 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w7__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src27__data_o$next[3:0]$11223 \w7__data_i + case + assign $4\src27__data_o$next[3:0]$11223 $3\src27__data_o$next[3:0]$11222 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src27__data_o$next[3:0]$11224 \reg + case + assign $5\src27__data_o$next[3:0]$11224 $4\src27__data_o$next[3:0]$11223 + end + case + assign $1\src27__data_o$next[3:0]$11220 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src27__data_o$next[3:0]$11225 4'0000 + case + assign $6\src27__data_o$next[3:0]$11225 $1\src27__data_o$next[3:0]$11220 + end + sync always + update \src27__data_o$next $0\src27__data_o$next[3:0]$11219 + end + attribute \src "libresoc.v:169129.3-169158.6" + process $proc$libresoc.v:169129$11226 + assign { } { } + assign { } { } + assign $0\wr_detect$4[0:0]$11227 $1\wr_detect$4[0:0]$11228 + attribute \src "libresoc.v:169130.5-169130.29" + switch \initial + attribute \src "libresoc.v:169130.9-169130.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src27__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$4[0:0]$11228 $4\wr_detect$4[0:0]$11231 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest17__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$4[0:0]$11229 1'1 + case + assign $2\wr_detect$4[0:0]$11229 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest27__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$4[0:0]$11230 1'1 + case + assign $3\wr_detect$4[0:0]$11230 $2\wr_detect$4[0:0]$11229 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w7__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$4[0:0]$11231 1'1 + case + assign $4\wr_detect$4[0:0]$11231 $3\wr_detect$4[0:0]$11230 + end + case + assign $1\wr_detect$4[0:0]$11228 1'0 + end + sync always + update \wr_detect$4 $0\wr_detect$4[0:0]$11227 + end + attribute \src "libresoc.v:169159.3-169198.6" + process $proc$libresoc.v:169159$11232 + assign { } { } + assign { } { } + assign { } { } + assign $0\src37__data_o$next[3:0]$11233 $6\src37__data_o$next[3:0]$11239 + attribute \src "libresoc.v:169160.5-169160.29" + switch \initial + attribute \src "libresoc.v:169160.9-169160.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src37__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src37__data_o$next[3:0]$11234 $5\src37__data_o$next[3:0]$11238 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest17__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src37__data_o$next[3:0]$11235 \dest17__data_i + case + assign $2\src37__data_o$next[3:0]$11235 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest27__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src37__data_o$next[3:0]$11236 \dest27__data_i + case + assign $3\src37__data_o$next[3:0]$11236 $2\src37__data_o$next[3:0]$11235 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w7__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src37__data_o$next[3:0]$11237 \w7__data_i + case + assign $4\src37__data_o$next[3:0]$11237 $3\src37__data_o$next[3:0]$11236 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$6 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src37__data_o$next[3:0]$11238 \reg + case + assign $5\src37__data_o$next[3:0]$11238 $4\src37__data_o$next[3:0]$11237 + end + case + assign $1\src37__data_o$next[3:0]$11234 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src37__data_o$next[3:0]$11239 4'0000 + case + assign $6\src37__data_o$next[3:0]$11239 $1\src37__data_o$next[3:0]$11234 + end + sync always + update \src37__data_o$next $0\src37__data_o$next[3:0]$11233 + end + attribute \src "libresoc.v:169199.3-169228.6" + process $proc$libresoc.v:169199$11240 + assign { } { } + assign { } { } + assign $0\wr_detect$7[0:0]$11241 $1\wr_detect$7[0:0]$11242 + attribute \src "libresoc.v:169200.5-169200.29" + switch \initial + attribute \src "libresoc.v:169200.9-169200.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src37__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$7[0:0]$11242 $4\wr_detect$7[0:0]$11245 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest17__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$7[0:0]$11243 1'1 + case + assign $2\wr_detect$7[0:0]$11243 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest27__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$7[0:0]$11244 1'1 + case + assign $3\wr_detect$7[0:0]$11244 $2\wr_detect$7[0:0]$11243 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w7__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$7[0:0]$11245 1'1 + case + assign $4\wr_detect$7[0:0]$11245 $3\wr_detect$7[0:0]$11244 + end + case + assign $1\wr_detect$7[0:0]$11242 1'0 + end + sync always + update \wr_detect$7 $0\wr_detect$7[0:0]$11241 + end + attribute \src "libresoc.v:169229.3-169268.6" + process $proc$libresoc.v:169229$11246 + assign { } { } + assign { } { } + assign { } { } + assign $0\r7__data_o$next[3:0]$11247 $6\r7__data_o$next[3:0]$11253 + attribute \src "libresoc.v:169230.5-169230.29" + switch \initial + attribute \src "libresoc.v:169230.9-169230.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r7__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\r7__data_o$next[3:0]$11248 $5\r7__data_o$next[3:0]$11252 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest17__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r7__data_o$next[3:0]$11249 \dest17__data_i + case + assign $2\r7__data_o$next[3:0]$11249 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest27__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\r7__data_o$next[3:0]$11250 \dest27__data_i + case + assign $3\r7__data_o$next[3:0]$11250 $2\r7__data_o$next[3:0]$11249 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w7__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\r7__data_o$next[3:0]$11251 \w7__data_i + case + assign $4\r7__data_o$next[3:0]$11251 $3\r7__data_o$next[3:0]$11250 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$9 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\r7__data_o$next[3:0]$11252 \reg + case + assign $5\r7__data_o$next[3:0]$11252 $4\r7__data_o$next[3:0]$11251 + end + case + assign $1\r7__data_o$next[3:0]$11248 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\r7__data_o$next[3:0]$11253 4'0000 + case + assign $6\r7__data_o$next[3:0]$11253 $1\r7__data_o$next[3:0]$11248 + end + sync always + update \r7__data_o$next $0\r7__data_o$next[3:0]$11247 + end + attribute \src "libresoc.v:169269.3-169298.6" + process $proc$libresoc.v:169269$11254 + assign { } { } + assign { } { } + assign $0\wr_detect$10[0:0]$11255 $1\wr_detect$10[0:0]$11256 + attribute \src "libresoc.v:169270.5-169270.29" + switch \initial + attribute \src "libresoc.v:169270.9-169270.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r7__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$10[0:0]$11256 $4\wr_detect$10[0:0]$11259 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest17__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$10[0:0]$11257 1'1 + case + assign $2\wr_detect$10[0:0]$11257 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest27__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$10[0:0]$11258 1'1 + case + assign $3\wr_detect$10[0:0]$11258 $2\wr_detect$10[0:0]$11257 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w7__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$10[0:0]$11259 1'1 + case + assign $4\wr_detect$10[0:0]$11259 $3\wr_detect$10[0:0]$11258 + end + case + assign $1\wr_detect$10[0:0]$11256 1'0 + end + sync always + update \wr_detect$10 $0\wr_detect$10[0:0]$11255 + end + attribute \src "libresoc.v:169299.3-169338.6" + process $proc$libresoc.v:169299$11260 + assign { } { } + assign { } { } + assign { } { } + assign $0\r27__data_o$next[3:0]$11261 $6\r27__data_o$next[3:0]$11267 + attribute \src "libresoc.v:169300.5-169300.29" + switch \initial + attribute \src "libresoc.v:169300.9-169300.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r27__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\r27__data_o$next[3:0]$11262 $5\r27__data_o$next[3:0]$11266 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest17__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r27__data_o$next[3:0]$11263 \dest17__data_i + case + assign $2\r27__data_o$next[3:0]$11263 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest27__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\r27__data_o$next[3:0]$11264 \dest27__data_i + case + assign $3\r27__data_o$next[3:0]$11264 $2\r27__data_o$next[3:0]$11263 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w7__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\r27__data_o$next[3:0]$11265 \w7__data_i + case + assign $4\r27__data_o$next[3:0]$11265 $3\r27__data_o$next[3:0]$11264 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$12 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\r27__data_o$next[3:0]$11266 \reg + case + assign $5\r27__data_o$next[3:0]$11266 $4\r27__data_o$next[3:0]$11265 + end + case + assign $1\r27__data_o$next[3:0]$11262 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\r27__data_o$next[3:0]$11267 4'0000 + case + assign $6\r27__data_o$next[3:0]$11267 $1\r27__data_o$next[3:0]$11262 + end + sync always + update \r27__data_o$next $0\r27__data_o$next[3:0]$11261 + end + attribute \src "libresoc.v:169339.3-169368.6" + process $proc$libresoc.v:169339$11268 + assign { } { } + assign { } { } + assign $0\wr_detect$13[0:0]$11269 $1\wr_detect$13[0:0]$11270 + attribute \src "libresoc.v:169340.5-169340.29" + switch \initial + attribute \src "libresoc.v:169340.9-169340.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r27__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$13[0:0]$11270 $4\wr_detect$13[0:0]$11273 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest17__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$13[0:0]$11271 1'1 + case + assign $2\wr_detect$13[0:0]$11271 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest27__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$13[0:0]$11272 1'1 + case + assign $3\wr_detect$13[0:0]$11272 $2\wr_detect$13[0:0]$11271 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w7__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$13[0:0]$11273 1'1 + case + assign $4\wr_detect$13[0:0]$11273 $3\wr_detect$13[0:0]$11272 + end + case + assign $1\wr_detect$13[0:0]$11270 1'0 + end + sync always + update \wr_detect$13 $0\wr_detect$13[0:0]$11269 + end + connect \$9 $not$libresoc.v:168975$11192_Y + connect \$12 $not$libresoc.v:168976$11193_Y + connect \$1 $not$libresoc.v:168977$11194_Y + connect \$3 $not$libresoc.v:168978$11195_Y + connect \$6 $not$libresoc.v:168979$11196_Y +end +attribute \src "libresoc.v:169373.1-169431.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.req_l" +attribute \generator "nMigen" +module \req_l + attribute \src "libresoc.v:169374.7-169374.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:169419.3-169427.6" + wire width 5 $0\q_int$next[4:0]$11291 + attribute \src "libresoc.v:169417.3-169418.27" + wire width 5 $0\q_int[4:0] + attribute \src "libresoc.v:169419.3-169427.6" + wire width 5 $1\q_int$next[4:0]$11292 + attribute \src "libresoc.v:169396.13-169396.26" + wire width 5 $1\q_int[4:0] + attribute \src "libresoc.v:169409.17-169409.96" + wire width 5 $and$libresoc.v:169409$11281_Y + attribute \src "libresoc.v:169414.17-169414.96" + wire width 5 $and$libresoc.v:169414$11286_Y + attribute \src "libresoc.v:169411.18-169411.93" + wire width 5 $not$libresoc.v:169411$11283_Y + attribute \src "libresoc.v:169413.17-169413.92" + wire width 5 $not$libresoc.v:169413$11285_Y + attribute \src "libresoc.v:169416.17-169416.92" + wire width 5 $not$libresoc.v:169416$11288_Y + attribute \src "libresoc.v:169410.18-169410.98" + wire width 5 $or$libresoc.v:169410$11282_Y + attribute \src "libresoc.v:169412.18-169412.99" + wire width 5 $or$libresoc.v:169412$11284_Y + attribute \src "libresoc.v:169415.17-169415.97" + wire width 5 $or$libresoc.v:169415$11287_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 5 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 5 \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 5 \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire width 5 \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 5 \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 5 \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 5 \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 5 \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 1 \coresync_rst + attribute \src "libresoc.v:169374.7-169374.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 5 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 5 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 5 output 2 \q_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire width 5 \qlq_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 5 \qn_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 5 input 4 \r_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 5 input 3 \s_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$libresoc.v:169409$11281 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:169409$11281_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:169414$11286 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:169414$11286_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:169411$11283 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \q_req + connect \Y $not$libresoc.v:169411$11283_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:169413$11285 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \r_req + connect \Y $not$libresoc.v:169413$11285_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:169416$11288 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \r_req + connect \Y $not$libresoc.v:169416$11288_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:169410$11282 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \$9 + connect \B \s_req + connect \Y $or$libresoc.v:169410$11282_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:169412$11284 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \q_req + connect \B \q_int + connect \Y $or$libresoc.v:169412$11284_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:169415$11287 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \$3 + connect \B \s_req + connect \Y $or$libresoc.v:169415$11287_Y + end + attribute \src "libresoc.v:169374.7-169374.20" + process $proc$libresoc.v:169374$11293 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:169396.13-169396.26" + process $proc$libresoc.v:169396$11294 + assign { } { } + assign $1\q_int[4:0] 5'00000 + sync always + sync init + update \q_int $1\q_int[4:0] + end + attribute \src "libresoc.v:169417.3-169418.27" + process $proc$libresoc.v:169417$11289 + assign { } { } + assign $0\q_int[4:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[4:0] + end + attribute \src "libresoc.v:169419.3-169427.6" + process $proc$libresoc.v:169419$11290 + assign { } { } + assign { } { } + assign $0\q_int$next[4:0]$11291 $1\q_int$next[4:0]$11292 + attribute \src "libresoc.v:169420.5-169420.29" + switch \initial + attribute \src "libresoc.v:169420.9-169420.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[4:0]$11292 5'00000 + case + assign $1\q_int$next[4:0]$11292 \$5 + end + sync always + update \q_int$next $0\q_int$next[4:0]$11291 + end + connect \$9 $and$libresoc.v:169409$11281_Y + connect \$11 $or$libresoc.v:169410$11282_Y + connect \$13 $not$libresoc.v:169411$11283_Y + connect \$15 $or$libresoc.v:169412$11284_Y + connect \$1 $not$libresoc.v:169413$11285_Y + connect \$3 $and$libresoc.v:169414$11286_Y + connect \$5 $or$libresoc.v:169415$11287_Y + connect \$7 $not$libresoc.v:169416$11288_Y + connect \qlq_req \$15 + connect \qn_req \$13 + connect \q_req \$11 +end +attribute \src "libresoc.v:169435.1-169493.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.req_l" +attribute \generator "nMigen" +module \req_l$100 + attribute \src "libresoc.v:169436.7-169436.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:169481.3-169489.6" + wire width 4 $0\q_int$next[3:0]$11305 + attribute \src "libresoc.v:169479.3-169480.27" + wire width 4 $0\q_int[3:0] + attribute \src "libresoc.v:169481.3-169489.6" + wire width 4 $1\q_int$next[3:0]$11306 + attribute \src "libresoc.v:169458.13-169458.25" + wire width 4 $1\q_int[3:0] + attribute \src "libresoc.v:169471.17-169471.96" + wire width 4 $and$libresoc.v:169471$11295_Y + attribute \src "libresoc.v:169476.17-169476.96" + wire width 4 $and$libresoc.v:169476$11300_Y + attribute \src "libresoc.v:169473.18-169473.93" + wire width 4 $not$libresoc.v:169473$11297_Y + attribute \src "libresoc.v:169475.17-169475.92" + wire width 4 $not$libresoc.v:169475$11299_Y + attribute \src "libresoc.v:169478.17-169478.92" + wire width 4 $not$libresoc.v:169478$11302_Y + attribute \src "libresoc.v:169472.18-169472.98" + wire width 4 $or$libresoc.v:169472$11296_Y + attribute \src "libresoc.v:169474.18-169474.99" + wire width 4 $or$libresoc.v:169474$11298_Y + attribute \src "libresoc.v:169477.17-169477.97" + wire width 4 $or$libresoc.v:169477$11301_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 4 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 4 \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 4 \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire width 4 \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 4 \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 4 \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 4 \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 4 \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 1 \coresync_rst + attribute \src "libresoc.v:169436.7-169436.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 4 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 4 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 4 output 2 \q_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire width 4 \qlq_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 4 \qn_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 4 input 4 \r_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 4 input 3 \s_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$libresoc.v:169471$11295 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:169471$11295_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:169476$11300 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:169476$11300_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:169473$11297 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \q_req + connect \Y $not$libresoc.v:169473$11297_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:169475$11299 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \r_req + connect \Y $not$libresoc.v:169475$11299_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:169478$11302 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \r_req + connect \Y $not$libresoc.v:169478$11302_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:169472$11296 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \$9 + connect \B \s_req + connect \Y $or$libresoc.v:169472$11296_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:169474$11298 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \q_req + connect \B \q_int + connect \Y $or$libresoc.v:169474$11298_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:169477$11301 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \$3 + connect \B \s_req + connect \Y $or$libresoc.v:169477$11301_Y + end + attribute \src "libresoc.v:169436.7-169436.20" + process $proc$libresoc.v:169436$11307 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:169458.13-169458.25" + process $proc$libresoc.v:169458$11308 + assign { } { } + assign $1\q_int[3:0] 4'0000 + sync always + sync init + update \q_int $1\q_int[3:0] + end + attribute \src "libresoc.v:169479.3-169480.27" + process $proc$libresoc.v:169479$11303 + assign { } { } + assign $0\q_int[3:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[3:0] + end + attribute \src "libresoc.v:169481.3-169489.6" + process $proc$libresoc.v:169481$11304 + assign { } { } + assign { } { } + assign $0\q_int$next[3:0]$11305 $1\q_int$next[3:0]$11306 + attribute \src "libresoc.v:169482.5-169482.29" + switch \initial + attribute \src "libresoc.v:169482.9-169482.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[3:0]$11306 4'0000 + case + assign $1\q_int$next[3:0]$11306 \$5 + end + sync always + update \q_int$next $0\q_int$next[3:0]$11305 + end + connect \$9 $and$libresoc.v:169471$11295_Y + connect \$11 $or$libresoc.v:169472$11296_Y + connect \$13 $not$libresoc.v:169473$11297_Y + connect \$15 $or$libresoc.v:169474$11298_Y + connect \$1 $not$libresoc.v:169475$11299_Y + connect \$3 $and$libresoc.v:169476$11300_Y + connect \$5 $or$libresoc.v:169477$11301_Y + connect \$7 $not$libresoc.v:169478$11302_Y + connect \qlq_req \$15 + connect \qn_req \$13 + connect \q_req \$11 +end +attribute \src "libresoc.v:169497.1-169555.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.req_l" +attribute \generator "nMigen" +module \req_l$118 + attribute \src "libresoc.v:169498.7-169498.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:169543.3-169551.6" + wire width 3 $0\q_int$next[2:0]$11319 + attribute \src "libresoc.v:169541.3-169542.27" + wire width 3 $0\q_int[2:0] + attribute \src "libresoc.v:169543.3-169551.6" + wire width 3 $1\q_int$next[2:0]$11320 + attribute \src "libresoc.v:169520.13-169520.25" + wire width 3 $1\q_int[2:0] + attribute \src "libresoc.v:169533.17-169533.96" + wire width 3 $and$libresoc.v:169533$11309_Y + attribute \src "libresoc.v:169538.17-169538.96" + wire width 3 $and$libresoc.v:169538$11314_Y + attribute \src "libresoc.v:169535.18-169535.93" + wire width 3 $not$libresoc.v:169535$11311_Y + attribute \src "libresoc.v:169537.17-169537.92" + wire width 3 $not$libresoc.v:169537$11313_Y + attribute \src "libresoc.v:169540.17-169540.92" + wire width 3 $not$libresoc.v:169540$11316_Y + attribute \src "libresoc.v:169534.18-169534.98" + wire width 3 $or$libresoc.v:169534$11310_Y + attribute \src "libresoc.v:169536.18-169536.99" + wire width 3 $or$libresoc.v:169536$11312_Y + attribute \src "libresoc.v:169539.17-169539.97" + wire width 3 $or$libresoc.v:169539$11315_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 3 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 3 \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 3 \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire width 3 \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 3 \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 3 \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 3 \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 3 \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 1 \coresync_rst + attribute \src "libresoc.v:169498.7-169498.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 3 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 3 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 3 output 2 \q_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire width 3 \qlq_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 3 \qn_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 3 input 4 \r_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 3 input 3 \s_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$libresoc.v:169533$11309 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:169533$11309_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:169538$11314 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:169538$11314_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:169535$11311 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_req + connect \Y $not$libresoc.v:169535$11311_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:169537$11313 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \r_req + connect \Y $not$libresoc.v:169537$11313_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:169540$11316 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \r_req + connect \Y $not$libresoc.v:169540$11316_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:169534$11310 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \$9 + connect \B \s_req + connect \Y $or$libresoc.v:169534$11310_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:169536$11312 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_req + connect \B \q_int + connect \Y $or$libresoc.v:169536$11312_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:169539$11315 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \$3 + connect \B \s_req + connect \Y $or$libresoc.v:169539$11315_Y + end + attribute \src "libresoc.v:169498.7-169498.20" + process $proc$libresoc.v:169498$11321 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:169520.13-169520.25" + process $proc$libresoc.v:169520$11322 + assign { } { } + assign $1\q_int[2:0] 3'000 + sync always + sync init + update \q_int $1\q_int[2:0] + end + attribute \src "libresoc.v:169541.3-169542.27" + process $proc$libresoc.v:169541$11317 + assign { } { } + assign $0\q_int[2:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[2:0] + end + attribute \src "libresoc.v:169543.3-169551.6" + process $proc$libresoc.v:169543$11318 + assign { } { } + assign { } { } + assign $0\q_int$next[2:0]$11319 $1\q_int$next[2:0]$11320 + attribute \src "libresoc.v:169544.5-169544.29" + switch \initial + attribute \src "libresoc.v:169544.9-169544.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[2:0]$11320 3'000 + case + assign $1\q_int$next[2:0]$11320 \$5 + end + sync always + update \q_int$next $0\q_int$next[2:0]$11319 + end + connect \$9 $and$libresoc.v:169533$11309_Y + connect \$11 $or$libresoc.v:169534$11310_Y + connect \$13 $not$libresoc.v:169535$11311_Y + connect \$15 $or$libresoc.v:169536$11312_Y + connect \$1 $not$libresoc.v:169537$11313_Y + connect \$3 $and$libresoc.v:169538$11314_Y + connect \$5 $or$libresoc.v:169539$11315_Y + connect \$7 $not$libresoc.v:169540$11316_Y + connect \qlq_req \$15 + connect \qn_req \$13 + connect \q_req \$11 +end +attribute \src "libresoc.v:169559.1-169617.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.req_l" +attribute \generator "nMigen" +module \req_l$12 + attribute \src "libresoc.v:169560.7-169560.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:169605.3-169613.6" + wire width 3 $0\q_int$next[2:0]$11333 + attribute \src "libresoc.v:169603.3-169604.27" + wire width 3 $0\q_int[2:0] + attribute \src "libresoc.v:169605.3-169613.6" + wire width 3 $1\q_int$next[2:0]$11334 + attribute \src "libresoc.v:169582.13-169582.25" + wire width 3 $1\q_int[2:0] + attribute \src "libresoc.v:169595.17-169595.96" + wire width 3 $and$libresoc.v:169595$11323_Y + attribute \src "libresoc.v:169600.17-169600.96" + wire width 3 $and$libresoc.v:169600$11328_Y + attribute \src "libresoc.v:169597.18-169597.93" + wire width 3 $not$libresoc.v:169597$11325_Y + attribute \src "libresoc.v:169599.17-169599.92" + wire width 3 $not$libresoc.v:169599$11327_Y + attribute \src "libresoc.v:169602.17-169602.92" + wire width 3 $not$libresoc.v:169602$11330_Y + attribute \src "libresoc.v:169596.18-169596.98" + wire width 3 $or$libresoc.v:169596$11324_Y + attribute \src "libresoc.v:169598.18-169598.99" + wire width 3 $or$libresoc.v:169598$11326_Y + attribute \src "libresoc.v:169601.17-169601.97" + wire width 3 $or$libresoc.v:169601$11329_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 3 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 3 \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 3 \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire width 3 \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 3 \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 3 \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 3 \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 3 \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 1 \coresync_rst + attribute \src "libresoc.v:169560.7-169560.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 3 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 3 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 3 output 2 \q_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire width 3 \qlq_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 3 \qn_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 3 input 4 \r_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 3 input 3 \s_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$libresoc.v:169595$11323 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:169595$11323_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:169600$11328 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:169600$11328_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:169597$11325 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_req + connect \Y $not$libresoc.v:169597$11325_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:169599$11327 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \r_req + connect \Y $not$libresoc.v:169599$11327_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:169602$11330 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \r_req + connect \Y $not$libresoc.v:169602$11330_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:169596$11324 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \$9 + connect \B \s_req + connect \Y $or$libresoc.v:169596$11324_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:169598$11326 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_req + connect \B \q_int + connect \Y $or$libresoc.v:169598$11326_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:169601$11329 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \$3 + connect \B \s_req + connect \Y $or$libresoc.v:169601$11329_Y + end + attribute \src "libresoc.v:169560.7-169560.20" + process $proc$libresoc.v:169560$11335 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:169582.13-169582.25" + process $proc$libresoc.v:169582$11336 + assign { } { } + assign $1\q_int[2:0] 3'000 + sync always + sync init + update \q_int $1\q_int[2:0] + end + attribute \src "libresoc.v:169603.3-169604.27" + process $proc$libresoc.v:169603$11331 + assign { } { } + assign $0\q_int[2:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[2:0] + end + attribute \src "libresoc.v:169605.3-169613.6" + process $proc$libresoc.v:169605$11332 + assign { } { } + assign { } { } + assign $0\q_int$next[2:0]$11333 $1\q_int$next[2:0]$11334 + attribute \src "libresoc.v:169606.5-169606.29" + switch \initial + attribute \src "libresoc.v:169606.9-169606.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[2:0]$11334 3'000 + case + assign $1\q_int$next[2:0]$11334 \$5 + end + sync always + update \q_int$next $0\q_int$next[2:0]$11333 + end + connect \$9 $and$libresoc.v:169595$11323_Y + connect \$11 $or$libresoc.v:169596$11324_Y + connect \$13 $not$libresoc.v:169597$11325_Y + connect \$15 $or$libresoc.v:169598$11326_Y + connect \$1 $not$libresoc.v:169599$11327_Y + connect \$3 $and$libresoc.v:169600$11328_Y + connect \$5 $or$libresoc.v:169601$11329_Y + connect \$7 $not$libresoc.v:169602$11330_Y + connect \qlq_req \$15 + connect \qn_req \$13 + connect \q_req \$11 +end +attribute \src "libresoc.v:169621.1-169679.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.req_l" +attribute \generator "nMigen" +module \req_l$25 + attribute \src "libresoc.v:169622.7-169622.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:169667.3-169675.6" + wire width 3 $0\q_int$next[2:0]$11347 + attribute \src "libresoc.v:169665.3-169666.27" + wire width 3 $0\q_int[2:0] + attribute \src "libresoc.v:169667.3-169675.6" + wire width 3 $1\q_int$next[2:0]$11348 + attribute \src "libresoc.v:169644.13-169644.25" + wire width 3 $1\q_int[2:0] + attribute \src "libresoc.v:169657.17-169657.96" + wire width 3 $and$libresoc.v:169657$11337_Y + attribute \src "libresoc.v:169662.17-169662.96" + wire width 3 $and$libresoc.v:169662$11342_Y + attribute \src "libresoc.v:169659.18-169659.93" + wire width 3 $not$libresoc.v:169659$11339_Y + attribute \src "libresoc.v:169661.17-169661.92" + wire width 3 $not$libresoc.v:169661$11341_Y + attribute \src "libresoc.v:169664.17-169664.92" + wire width 3 $not$libresoc.v:169664$11344_Y + attribute \src "libresoc.v:169658.18-169658.98" + wire width 3 $or$libresoc.v:169658$11338_Y + attribute \src "libresoc.v:169660.18-169660.99" + wire width 3 $or$libresoc.v:169660$11340_Y + attribute \src "libresoc.v:169663.17-169663.97" + wire width 3 $or$libresoc.v:169663$11343_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 3 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 3 \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 3 \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire width 3 \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 3 \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 3 \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 3 \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 3 \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 1 \coresync_rst + attribute \src "libresoc.v:169622.7-169622.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 3 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 3 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 3 output 2 \q_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire width 3 \qlq_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 3 \qn_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 3 input 4 \r_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 3 input 3 \s_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$libresoc.v:169657$11337 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:169657$11337_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:169662$11342 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:169662$11342_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:169659$11339 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_req + connect \Y $not$libresoc.v:169659$11339_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:169661$11341 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \r_req + connect \Y $not$libresoc.v:169661$11341_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:169664$11344 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \r_req + connect \Y $not$libresoc.v:169664$11344_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:169658$11338 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \$9 + connect \B \s_req + connect \Y $or$libresoc.v:169658$11338_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:169660$11340 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_req + connect \B \q_int + connect \Y $or$libresoc.v:169660$11340_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:169663$11343 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \$3 + connect \B \s_req + connect \Y $or$libresoc.v:169663$11343_Y + end + attribute \src "libresoc.v:169622.7-169622.20" + process $proc$libresoc.v:169622$11349 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:169644.13-169644.25" + process $proc$libresoc.v:169644$11350 + assign { } { } + assign $1\q_int[2:0] 3'000 + sync always + sync init + update \q_int $1\q_int[2:0] + end + attribute \src "libresoc.v:169665.3-169666.27" + process $proc$libresoc.v:169665$11345 + assign { } { } + assign $0\q_int[2:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[2:0] + end + attribute \src "libresoc.v:169667.3-169675.6" + process $proc$libresoc.v:169667$11346 + assign { } { } + assign { } { } + assign $0\q_int$next[2:0]$11347 $1\q_int$next[2:0]$11348 + attribute \src "libresoc.v:169668.5-169668.29" + switch \initial + attribute \src "libresoc.v:169668.9-169668.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[2:0]$11348 3'000 + case + assign $1\q_int$next[2:0]$11348 \$5 + end + sync always + update \q_int$next $0\q_int$next[2:0]$11347 + end + connect \$9 $and$libresoc.v:169657$11337_Y + connect \$11 $or$libresoc.v:169658$11338_Y + connect \$13 $not$libresoc.v:169659$11339_Y + connect \$15 $or$libresoc.v:169660$11340_Y + connect \$1 $not$libresoc.v:169661$11341_Y + connect \$3 $and$libresoc.v:169662$11342_Y + connect \$5 $or$libresoc.v:169663$11343_Y + connect \$7 $not$libresoc.v:169664$11344_Y + connect \qlq_req \$15 + connect \qn_req \$13 + connect \q_req \$11 +end +attribute \src "libresoc.v:169683.1-169741.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.req_l" +attribute \generator "nMigen" +module \req_l$38 + attribute \src "libresoc.v:169684.7-169684.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:169729.3-169737.6" + wire width 5 $0\q_int$next[4:0]$11361 + attribute \src "libresoc.v:169727.3-169728.27" + wire width 5 $0\q_int[4:0] + attribute \src "libresoc.v:169729.3-169737.6" + wire width 5 $1\q_int$next[4:0]$11362 + attribute \src "libresoc.v:169706.13-169706.26" + wire width 5 $1\q_int[4:0] + attribute \src "libresoc.v:169719.17-169719.96" + wire width 5 $and$libresoc.v:169719$11351_Y + attribute \src "libresoc.v:169724.17-169724.96" + wire width 5 $and$libresoc.v:169724$11356_Y + attribute \src "libresoc.v:169721.18-169721.93" + wire width 5 $not$libresoc.v:169721$11353_Y + attribute \src "libresoc.v:169723.17-169723.92" + wire width 5 $not$libresoc.v:169723$11355_Y + attribute \src "libresoc.v:169726.17-169726.92" + wire width 5 $not$libresoc.v:169726$11358_Y + attribute \src "libresoc.v:169720.18-169720.98" + wire width 5 $or$libresoc.v:169720$11352_Y + attribute \src "libresoc.v:169722.18-169722.99" + wire width 5 $or$libresoc.v:169722$11354_Y + attribute \src "libresoc.v:169725.17-169725.97" + wire width 5 $or$libresoc.v:169725$11357_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 5 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 5 \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 5 \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire width 5 \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 5 \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 5 \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 5 \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 5 \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 1 \coresync_rst + attribute \src "libresoc.v:169684.7-169684.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 5 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 5 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 5 output 2 \q_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire width 5 \qlq_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 5 \qn_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 5 input 4 \r_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 5 input 3 \s_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$libresoc.v:169719$11351 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:169719$11351_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:169724$11356 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:169724$11356_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:169721$11353 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \q_req + connect \Y $not$libresoc.v:169721$11353_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:169723$11355 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \r_req + connect \Y $not$libresoc.v:169723$11355_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:169726$11358 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \r_req + connect \Y $not$libresoc.v:169726$11358_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:169720$11352 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \$9 + connect \B \s_req + connect \Y $or$libresoc.v:169720$11352_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:169722$11354 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \q_req + connect \B \q_int + connect \Y $or$libresoc.v:169722$11354_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:169725$11357 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \$3 + connect \B \s_req + connect \Y $or$libresoc.v:169725$11357_Y + end + attribute \src "libresoc.v:169684.7-169684.20" + process $proc$libresoc.v:169684$11363 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:169706.13-169706.26" + process $proc$libresoc.v:169706$11364 + assign { } { } + assign $1\q_int[4:0] 5'00000 + sync always + sync init + update \q_int $1\q_int[4:0] + end + attribute \src "libresoc.v:169727.3-169728.27" + process $proc$libresoc.v:169727$11359 + assign { } { } + assign $0\q_int[4:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[4:0] + end + attribute \src "libresoc.v:169729.3-169737.6" + process $proc$libresoc.v:169729$11360 + assign { } { } + assign { } { } + assign $0\q_int$next[4:0]$11361 $1\q_int$next[4:0]$11362 + attribute \src "libresoc.v:169730.5-169730.29" + switch \initial + attribute \src "libresoc.v:169730.9-169730.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[4:0]$11362 5'00000 + case + assign $1\q_int$next[4:0]$11362 \$5 + end + sync always + update \q_int$next $0\q_int$next[4:0]$11361 + end + connect \$9 $and$libresoc.v:169719$11351_Y + connect \$11 $or$libresoc.v:169720$11352_Y + connect \$13 $not$libresoc.v:169721$11353_Y + connect \$15 $or$libresoc.v:169722$11354_Y + connect \$1 $not$libresoc.v:169723$11355_Y + connect \$3 $and$libresoc.v:169724$11356_Y + connect \$5 $or$libresoc.v:169725$11357_Y + connect \$7 $not$libresoc.v:169726$11358_Y + connect \qlq_req \$15 + connect \qn_req \$13 + connect \q_req \$11 +end +attribute \src "libresoc.v:169745.1-169803.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.req_l" +attribute \generator "nMigen" +module \req_l$54 + attribute \src "libresoc.v:169746.7-169746.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:169791.3-169799.6" + wire width 2 $0\q_int$next[1:0]$11375 + attribute \src "libresoc.v:169789.3-169790.27" + wire width 2 $0\q_int[1:0] + attribute \src "libresoc.v:169791.3-169799.6" + wire width 2 $1\q_int$next[1:0]$11376 + attribute \src "libresoc.v:169768.13-169768.25" + wire width 2 $1\q_int[1:0] + attribute \src "libresoc.v:169781.17-169781.96" + wire width 2 $and$libresoc.v:169781$11365_Y + attribute \src "libresoc.v:169786.17-169786.96" + wire width 2 $and$libresoc.v:169786$11370_Y + attribute \src "libresoc.v:169783.18-169783.93" + wire width 2 $not$libresoc.v:169783$11367_Y + attribute \src "libresoc.v:169785.17-169785.92" + wire width 2 $not$libresoc.v:169785$11369_Y + attribute \src "libresoc.v:169788.17-169788.92" + wire width 2 $not$libresoc.v:169788$11372_Y + attribute \src "libresoc.v:169782.18-169782.98" + wire width 2 $or$libresoc.v:169782$11366_Y + attribute \src "libresoc.v:169784.18-169784.99" + wire width 2 $or$libresoc.v:169784$11368_Y + attribute \src "libresoc.v:169787.17-169787.97" + wire width 2 $or$libresoc.v:169787$11371_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 2 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 2 \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 2 \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire width 2 \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 2 \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 2 \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 2 \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 2 \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 1 \coresync_rst + attribute \src "libresoc.v:169746.7-169746.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 2 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 2 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 2 output 2 \q_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire width 2 \qlq_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 2 \qn_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 2 input 4 \r_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 2 input 3 \s_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$libresoc.v:169781$11365 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:169781$11365_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:169786$11370 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:169786$11370_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:169783$11367 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \q_req + connect \Y $not$libresoc.v:169783$11367_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:169785$11369 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \r_req + connect \Y $not$libresoc.v:169785$11369_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:169788$11372 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \r_req + connect \Y $not$libresoc.v:169788$11372_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:169782$11366 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \$9 + connect \B \s_req + connect \Y $or$libresoc.v:169782$11366_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:169784$11368 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \q_req + connect \B \q_int + connect \Y $or$libresoc.v:169784$11368_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:169787$11371 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \$3 + connect \B \s_req + connect \Y $or$libresoc.v:169787$11371_Y + end + attribute \src "libresoc.v:169746.7-169746.20" + process $proc$libresoc.v:169746$11377 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:169768.13-169768.25" + process $proc$libresoc.v:169768$11378 + assign { } { } + assign $1\q_int[1:0] 2'00 + sync always + sync init + update \q_int $1\q_int[1:0] + end + attribute \src "libresoc.v:169789.3-169790.27" + process $proc$libresoc.v:169789$11373 + assign { } { } + assign $0\q_int[1:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[1:0] + end + attribute \src "libresoc.v:169791.3-169799.6" + process $proc$libresoc.v:169791$11374 + assign { } { } + assign { } { } + assign $0\q_int$next[1:0]$11375 $1\q_int$next[1:0]$11376 + attribute \src "libresoc.v:169792.5-169792.29" + switch \initial + attribute \src "libresoc.v:169792.9-169792.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[1:0]$11376 2'00 + case + assign $1\q_int$next[1:0]$11376 \$5 + end + sync always + update \q_int$next $0\q_int$next[1:0]$11375 + end + connect \$9 $and$libresoc.v:169781$11365_Y + connect \$11 $or$libresoc.v:169782$11366_Y + connect \$13 $not$libresoc.v:169783$11367_Y + connect \$15 $or$libresoc.v:169784$11368_Y + connect \$1 $not$libresoc.v:169785$11369_Y + connect \$3 $and$libresoc.v:169786$11370_Y + connect \$5 $or$libresoc.v:169787$11371_Y + connect \$7 $not$libresoc.v:169788$11372_Y + connect \qlq_req \$15 + connect \qn_req \$13 + connect \q_req \$11 +end +attribute \src "libresoc.v:169807.1-169865.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.req_l" +attribute \generator "nMigen" +module \req_l$66 + attribute \src "libresoc.v:169808.7-169808.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:169853.3-169861.6" + wire width 6 $0\q_int$next[5:0]$11389 + attribute \src "libresoc.v:169851.3-169852.27" + wire width 6 $0\q_int[5:0] + attribute \src "libresoc.v:169853.3-169861.6" + wire width 6 $1\q_int$next[5:0]$11390 + attribute \src "libresoc.v:169830.13-169830.26" + wire width 6 $1\q_int[5:0] + attribute \src "libresoc.v:169843.17-169843.96" + wire width 6 $and$libresoc.v:169843$11379_Y + attribute \src "libresoc.v:169848.17-169848.96" + wire width 6 $and$libresoc.v:169848$11384_Y + attribute \src "libresoc.v:169845.18-169845.93" + wire width 6 $not$libresoc.v:169845$11381_Y + attribute \src "libresoc.v:169847.17-169847.92" + wire width 6 $not$libresoc.v:169847$11383_Y + attribute \src "libresoc.v:169850.17-169850.92" + wire width 6 $not$libresoc.v:169850$11386_Y + attribute \src "libresoc.v:169844.18-169844.98" + wire width 6 $or$libresoc.v:169844$11380_Y + attribute \src "libresoc.v:169846.18-169846.99" + wire width 6 $or$libresoc.v:169846$11382_Y + attribute \src "libresoc.v:169849.17-169849.97" + wire width 6 $or$libresoc.v:169849$11385_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 6 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 6 \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 6 \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire width 6 \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 6 \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 6 \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 6 \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 6 \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 1 \coresync_rst + attribute \src "libresoc.v:169808.7-169808.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 6 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 6 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 6 output 2 \q_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire width 6 \qlq_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 6 \qn_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 6 input 4 \r_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 6 input 3 \s_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$libresoc.v:169843$11379 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:169843$11379_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:169848$11384 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:169848$11384_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:169845$11381 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \q_req + connect \Y $not$libresoc.v:169845$11381_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:169847$11383 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \r_req + connect \Y $not$libresoc.v:169847$11383_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:169850$11386 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \r_req + connect \Y $not$libresoc.v:169850$11386_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:169844$11380 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \$9 + connect \B \s_req + connect \Y $or$libresoc.v:169844$11380_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:169846$11382 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \q_req + connect \B \q_int + connect \Y $or$libresoc.v:169846$11382_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:169849$11385 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \$3 + connect \B \s_req + connect \Y $or$libresoc.v:169849$11385_Y + end + attribute \src "libresoc.v:169808.7-169808.20" + process $proc$libresoc.v:169808$11391 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:169830.13-169830.26" + process $proc$libresoc.v:169830$11392 + assign { } { } + assign $1\q_int[5:0] 6'000000 + sync always + sync init + update \q_int $1\q_int[5:0] + end + attribute \src "libresoc.v:169851.3-169852.27" + process $proc$libresoc.v:169851$11387 + assign { } { } + assign $0\q_int[5:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[5:0] + end + attribute \src "libresoc.v:169853.3-169861.6" + process $proc$libresoc.v:169853$11388 + assign { } { } + assign { } { } + assign $0\q_int$next[5:0]$11389 $1\q_int$next[5:0]$11390 + attribute \src "libresoc.v:169854.5-169854.29" + switch \initial + attribute \src "libresoc.v:169854.9-169854.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[5:0]$11390 6'000000 + case + assign $1\q_int$next[5:0]$11390 \$5 + end + sync always + update \q_int$next $0\q_int$next[5:0]$11389 + end + connect \$9 $and$libresoc.v:169843$11379_Y + connect \$11 $or$libresoc.v:169844$11380_Y + connect \$13 $not$libresoc.v:169845$11381_Y + connect \$15 $or$libresoc.v:169846$11382_Y + connect \$1 $not$libresoc.v:169847$11383_Y + connect \$3 $and$libresoc.v:169848$11384_Y + connect \$5 $or$libresoc.v:169849$11385_Y + connect \$7 $not$libresoc.v:169850$11386_Y + connect \qlq_req \$15 + connect \qn_req \$13 + connect \q_req \$11 +end +attribute \src "libresoc.v:169869.1-169927.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.req_l" +attribute \generator "nMigen" +module \req_l$83 + attribute \src "libresoc.v:169870.7-169870.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:169915.3-169923.6" + wire width 4 $0\q_int$next[3:0]$11403 + attribute \src "libresoc.v:169913.3-169914.27" + wire width 4 $0\q_int[3:0] + attribute \src "libresoc.v:169915.3-169923.6" + wire width 4 $1\q_int$next[3:0]$11404 + attribute \src "libresoc.v:169892.13-169892.25" + wire width 4 $1\q_int[3:0] + attribute \src "libresoc.v:169905.17-169905.96" + wire width 4 $and$libresoc.v:169905$11393_Y + attribute \src "libresoc.v:169910.17-169910.96" + wire width 4 $and$libresoc.v:169910$11398_Y + attribute \src "libresoc.v:169907.18-169907.93" + wire width 4 $not$libresoc.v:169907$11395_Y + attribute \src "libresoc.v:169909.17-169909.92" + wire width 4 $not$libresoc.v:169909$11397_Y + attribute \src "libresoc.v:169912.17-169912.92" + wire width 4 $not$libresoc.v:169912$11400_Y + attribute \src "libresoc.v:169906.18-169906.98" + wire width 4 $or$libresoc.v:169906$11394_Y + attribute \src "libresoc.v:169908.18-169908.99" + wire width 4 $or$libresoc.v:169908$11396_Y + attribute \src "libresoc.v:169911.17-169911.97" + wire width 4 $or$libresoc.v:169911$11399_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 4 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 4 \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 4 \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire width 4 \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 4 \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 4 \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 4 \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 4 \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 1 \coresync_rst + attribute \src "libresoc.v:169870.7-169870.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 4 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 4 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 4 output 2 \q_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire width 4 \qlq_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 4 \qn_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 4 input 4 \r_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 4 input 3 \s_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$libresoc.v:169905$11393 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:169905$11393_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:169910$11398 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:169910$11398_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:169907$11395 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \q_req + connect \Y $not$libresoc.v:169907$11395_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:169909$11397 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \r_req + connect \Y $not$libresoc.v:169909$11397_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:169912$11400 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \r_req + connect \Y $not$libresoc.v:169912$11400_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:169906$11394 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \$9 + connect \B \s_req + connect \Y $or$libresoc.v:169906$11394_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:169908$11396 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \q_req + connect \B \q_int + connect \Y $or$libresoc.v:169908$11396_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:169911$11399 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \$3 + connect \B \s_req + connect \Y $or$libresoc.v:169911$11399_Y + end + attribute \src "libresoc.v:169870.7-169870.20" + process $proc$libresoc.v:169870$11405 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:169892.13-169892.25" + process $proc$libresoc.v:169892$11406 + assign { } { } + assign $1\q_int[3:0] 4'0000 + sync always + sync init + update \q_int $1\q_int[3:0] + end + attribute \src "libresoc.v:169913.3-169914.27" + process $proc$libresoc.v:169913$11401 + assign { } { } + assign $0\q_int[3:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[3:0] + end + attribute \src "libresoc.v:169915.3-169923.6" + process $proc$libresoc.v:169915$11402 + assign { } { } + assign { } { } + assign $0\q_int$next[3:0]$11403 $1\q_int$next[3:0]$11404 + attribute \src "libresoc.v:169916.5-169916.29" + switch \initial + attribute \src "libresoc.v:169916.9-169916.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[3:0]$11404 4'0000 + case + assign $1\q_int$next[3:0]$11404 \$5 + end + sync always + update \q_int$next $0\q_int$next[3:0]$11403 + end + connect \$9 $and$libresoc.v:169905$11393_Y + connect \$11 $or$libresoc.v:169906$11394_Y + connect \$13 $not$libresoc.v:169907$11395_Y + connect \$15 $or$libresoc.v:169908$11396_Y + connect \$1 $not$libresoc.v:169909$11397_Y + connect \$3 $and$libresoc.v:169910$11398_Y + connect \$5 $or$libresoc.v:169911$11399_Y + connect \$7 $not$libresoc.v:169912$11400_Y + connect \qlq_req \$15 + connect \qn_req \$13 + connect \q_req \$11 +end +attribute \src "libresoc.v:169931.1-169980.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.l0.pimem.reset_l" +attribute \generator "nMigen" +module \reset_l + attribute \src "libresoc.v:169932.7-169932.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:169968.3-169976.6" + wire $0\q_int$next[0:0]$11414 + attribute \src "libresoc.v:169966.3-169967.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:169968.3-169976.6" + wire $1\q_int$next[0:0]$11415 + attribute \src "libresoc.v:169948.7-169948.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:169963.17-169963.96" + wire $and$libresoc.v:169963$11409_Y + attribute \src "libresoc.v:169962.17-169962.94" + wire $not$libresoc.v:169962$11408_Y + attribute \src "libresoc.v:169965.17-169965.94" + wire $not$libresoc.v:169965$11411_Y + attribute \src "libresoc.v:169961.17-169961.100" + wire $or$libresoc.v:169961$11407_Y + attribute \src "libresoc.v:169964.17-169964.99" + wire $or$libresoc.v:169964$11410_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 1 \coresync_rst + attribute \src "libresoc.v:169932.7-169932.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 4 \q_reset + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_reset + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_reset + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_reset + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 2 \s_reset + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:169963$11409 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:169963$11409_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:169962$11408 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_reset + connect \Y $not$libresoc.v:169962$11408_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:169965$11411 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_reset + connect \Y $not$libresoc.v:169965$11411_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:169961$11407 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_reset + connect \B \q_int + connect \Y $or$libresoc.v:169961$11407_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:169964$11410 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_reset + connect \Y $or$libresoc.v:169964$11410_Y + end + attribute \src "libresoc.v:169932.7-169932.20" + process $proc$libresoc.v:169932$11416 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:169948.7-169948.19" + process $proc$libresoc.v:169948$11417 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:169966.3-169967.27" + process $proc$libresoc.v:169966$11412 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:169968.3-169976.6" + process $proc$libresoc.v:169968$11413 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$11414 $1\q_int$next[0:0]$11415 + attribute \src "libresoc.v:169969.5-169969.29" + switch \initial + attribute \src "libresoc.v:169969.9-169969.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$11415 1'0 + case + assign $1\q_int$next[0:0]$11415 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$11414 + end + connect \$9 $or$libresoc.v:169961$11407_Y + connect \$1 $not$libresoc.v:169962$11408_Y + connect \$3 $and$libresoc.v:169963$11409_Y + connect \$5 $or$libresoc.v:169964$11410_Y + connect \$7 $not$libresoc.v:169965$11411_Y + connect \qlq_reset \$9 + connect \qn_reset \$7 + connect \q_reset \q_int +end +attribute \src "libresoc.v:169984.1-170033.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.l0.l0.reset_l" +attribute \generator "nMigen" +module \reset_l$128 + attribute \src "libresoc.v:169985.7-169985.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:170021.3-170029.6" + wire $0\q_int$next[0:0]$11425 + attribute \src "libresoc.v:170019.3-170020.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:170021.3-170029.6" + wire $1\q_int$next[0:0]$11426 + attribute \src "libresoc.v:170001.7-170001.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:170016.17-170016.96" + wire $and$libresoc.v:170016$11420_Y + attribute \src "libresoc.v:170015.17-170015.94" + wire $not$libresoc.v:170015$11419_Y + attribute \src "libresoc.v:170018.17-170018.94" + wire $not$libresoc.v:170018$11422_Y + attribute \src "libresoc.v:170014.17-170014.100" + wire $or$libresoc.v:170014$11418_Y + attribute \src "libresoc.v:170017.17-170017.99" + wire $or$libresoc.v:170017$11421_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 1 \coresync_rst + attribute \src "libresoc.v:169985.7-169985.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 4 \q_reset + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_reset + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_reset + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_reset + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 2 \s_reset + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:170016$11420 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:170016$11420_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:170015$11419 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_reset + connect \Y $not$libresoc.v:170015$11419_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:170018$11422 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_reset + connect \Y $not$libresoc.v:170018$11422_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:170014$11418 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_reset + connect \B \q_int + connect \Y $or$libresoc.v:170014$11418_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:170017$11421 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_reset + connect \Y $or$libresoc.v:170017$11421_Y + end + attribute \src "libresoc.v:169985.7-169985.20" + process $proc$libresoc.v:169985$11427 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:170001.7-170001.19" + process $proc$libresoc.v:170001$11428 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:170019.3-170020.27" + process $proc$libresoc.v:170019$11423 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:170021.3-170029.6" + process $proc$libresoc.v:170021$11424 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$11425 $1\q_int$next[0:0]$11426 + attribute \src "libresoc.v:170022.5-170022.29" + switch \initial + attribute \src "libresoc.v:170022.9-170022.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$11426 1'0 + case + assign $1\q_int$next[0:0]$11426 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$11425 + end + connect \$9 $or$libresoc.v:170014$11418_Y + connect \$1 $not$libresoc.v:170015$11419_Y + connect \$3 $and$libresoc.v:170016$11420_Y + connect \$5 $or$libresoc.v:170017$11421_Y + connect \$7 $not$libresoc.v:170018$11422_Y + connect \qlq_reset \$9 + connect \qn_reset \$7 + connect \q_reset \q_int +end +attribute \src "libresoc.v:170037.1-170624.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.pipe1.main.rotator.right_mask" +attribute \generator "nMigen" +module \right_mask + attribute \src "libresoc.v:170038.7-170038.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:170236.3-170623.6" + wire width 64 $0\mask[63:0] + attribute \src "libresoc.v:170236.3-170623.6" + wire $10\mask[9:9] + attribute \src "libresoc.v:170236.3-170623.6" + wire $11\mask[10:10] + attribute \src "libresoc.v:170236.3-170623.6" + wire $12\mask[11:11] + attribute \src "libresoc.v:170236.3-170623.6" + wire $13\mask[12:12] + attribute \src "libresoc.v:170236.3-170623.6" + wire $14\mask[13:13] + attribute \src "libresoc.v:170236.3-170623.6" + wire $15\mask[14:14] + attribute \src "libresoc.v:170236.3-170623.6" + wire $16\mask[15:15] + attribute \src "libresoc.v:170236.3-170623.6" + wire $17\mask[16:16] + attribute \src "libresoc.v:170236.3-170623.6" + wire $18\mask[17:17] + attribute \src "libresoc.v:170236.3-170623.6" + wire $19\mask[18:18] + attribute \src "libresoc.v:170236.3-170623.6" + wire $1\mask[0:0] + attribute \src "libresoc.v:170236.3-170623.6" + wire $20\mask[19:19] + attribute \src "libresoc.v:170236.3-170623.6" + wire $21\mask[20:20] + attribute \src "libresoc.v:170236.3-170623.6" + wire $22\mask[21:21] + attribute \src "libresoc.v:170236.3-170623.6" + wire $23\mask[22:22] + attribute \src "libresoc.v:170236.3-170623.6" + wire $24\mask[23:23] + attribute \src "libresoc.v:170236.3-170623.6" + wire $25\mask[24:24] + attribute \src "libresoc.v:170236.3-170623.6" + wire $26\mask[25:25] + attribute \src "libresoc.v:170236.3-170623.6" + wire $27\mask[26:26] + attribute \src "libresoc.v:170236.3-170623.6" + wire $28\mask[27:27] + attribute \src "libresoc.v:170236.3-170623.6" + wire $29\mask[28:28] + attribute \src "libresoc.v:170236.3-170623.6" + wire $2\mask[1:1] + attribute \src "libresoc.v:170236.3-170623.6" + wire $30\mask[29:29] + attribute \src "libresoc.v:170236.3-170623.6" + wire $31\mask[30:30] + attribute \src "libresoc.v:170236.3-170623.6" + wire $32\mask[31:31] + attribute \src "libresoc.v:170236.3-170623.6" + wire $33\mask[32:32] + attribute \src "libresoc.v:170236.3-170623.6" + wire $34\mask[33:33] + attribute \src "libresoc.v:170236.3-170623.6" + wire $35\mask[34:34] + attribute \src "libresoc.v:170236.3-170623.6" + wire $36\mask[35:35] + attribute \src "libresoc.v:170236.3-170623.6" + wire $37\mask[36:36] + attribute \src "libresoc.v:170236.3-170623.6" + wire $38\mask[37:37] + attribute \src "libresoc.v:170236.3-170623.6" + wire $39\mask[38:38] + attribute \src "libresoc.v:170236.3-170623.6" + wire $3\mask[2:2] + attribute \src "libresoc.v:170236.3-170623.6" + wire $40\mask[39:39] + attribute \src "libresoc.v:170236.3-170623.6" + wire $41\mask[40:40] + attribute \src "libresoc.v:170236.3-170623.6" + wire $42\mask[41:41] + attribute \src "libresoc.v:170236.3-170623.6" + wire $43\mask[42:42] + attribute \src "libresoc.v:170236.3-170623.6" + wire $44\mask[43:43] + attribute \src "libresoc.v:170236.3-170623.6" + wire $45\mask[44:44] + attribute \src "libresoc.v:170236.3-170623.6" + wire $46\mask[45:45] + attribute \src "libresoc.v:170236.3-170623.6" + wire $47\mask[46:46] + attribute \src "libresoc.v:170236.3-170623.6" + wire $48\mask[47:47] + attribute \src "libresoc.v:170236.3-170623.6" + wire $49\mask[48:48] + attribute \src "libresoc.v:170236.3-170623.6" + wire $4\mask[3:3] + attribute \src "libresoc.v:170236.3-170623.6" + wire $50\mask[49:49] + attribute \src "libresoc.v:170236.3-170623.6" + wire $51\mask[50:50] + attribute \src "libresoc.v:170236.3-170623.6" + wire $52\mask[51:51] + attribute \src "libresoc.v:170236.3-170623.6" + wire $53\mask[52:52] + attribute \src "libresoc.v:170236.3-170623.6" + wire $54\mask[53:53] + attribute \src "libresoc.v:170236.3-170623.6" + wire $55\mask[54:54] + attribute \src "libresoc.v:170236.3-170623.6" + wire $56\mask[55:55] + attribute \src "libresoc.v:170236.3-170623.6" + wire $57\mask[56:56] + attribute \src "libresoc.v:170236.3-170623.6" + wire $58\mask[57:57] + attribute \src "libresoc.v:170236.3-170623.6" + wire $59\mask[58:58] + attribute \src "libresoc.v:170236.3-170623.6" + wire $5\mask[4:4] + attribute \src "libresoc.v:170236.3-170623.6" + wire $60\mask[59:59] + attribute \src "libresoc.v:170236.3-170623.6" + wire $61\mask[60:60] + attribute \src "libresoc.v:170236.3-170623.6" + wire $62\mask[61:61] + attribute \src "libresoc.v:170236.3-170623.6" + wire $63\mask[62:62] + attribute \src "libresoc.v:170236.3-170623.6" + wire $64\mask[63:63] + attribute \src "libresoc.v:170236.3-170623.6" + wire $6\mask[5:5] + attribute \src "libresoc.v:170236.3-170623.6" + wire $7\mask[6:6] + attribute \src "libresoc.v:170236.3-170623.6" + wire $8\mask[7:7] + attribute \src "libresoc.v:170236.3-170623.6" + wire $9\mask[8:8] + attribute \src "libresoc.v:170172.17-170172.96" + wire $gt$libresoc.v:170172$11429_Y + attribute \src "libresoc.v:170173.18-170173.98" + wire $gt$libresoc.v:170173$11430_Y + attribute \src "libresoc.v:170174.19-170174.99" + wire $gt$libresoc.v:170174$11431_Y + attribute \src "libresoc.v:170175.19-170175.99" + wire $gt$libresoc.v:170175$11432_Y + attribute \src "libresoc.v:170176.19-170176.99" + wire $gt$libresoc.v:170176$11433_Y + attribute \src "libresoc.v:170177.19-170177.99" + wire $gt$libresoc.v:170177$11434_Y + attribute \src "libresoc.v:170178.19-170178.99" + wire $gt$libresoc.v:170178$11435_Y + attribute \src "libresoc.v:170179.19-170179.99" + wire $gt$libresoc.v:170179$11436_Y + attribute \src "libresoc.v:170180.19-170180.99" + wire $gt$libresoc.v:170180$11437_Y + attribute \src "libresoc.v:170181.19-170181.99" + wire $gt$libresoc.v:170181$11438_Y + attribute \src "libresoc.v:170182.19-170182.99" + wire $gt$libresoc.v:170182$11439_Y + attribute \src "libresoc.v:170183.18-170183.97" + wire $gt$libresoc.v:170183$11440_Y + attribute \src "libresoc.v:170184.19-170184.99" + wire $gt$libresoc.v:170184$11441_Y + attribute \src "libresoc.v:170185.19-170185.99" + wire $gt$libresoc.v:170185$11442_Y + attribute \src "libresoc.v:170186.19-170186.99" + wire $gt$libresoc.v:170186$11443_Y + attribute \src "libresoc.v:170187.19-170187.99" + wire $gt$libresoc.v:170187$11444_Y + attribute \src "libresoc.v:170188.19-170188.99" + wire $gt$libresoc.v:170188$11445_Y + attribute \src "libresoc.v:170189.18-170189.97" + wire $gt$libresoc.v:170189$11446_Y + attribute \src "libresoc.v:170190.18-170190.97" + wire $gt$libresoc.v:170190$11447_Y + attribute \src "libresoc.v:170191.18-170191.97" + wire $gt$libresoc.v:170191$11448_Y + attribute \src "libresoc.v:170192.17-170192.96" + wire $gt$libresoc.v:170192$11449_Y + attribute \src "libresoc.v:170193.18-170193.97" + wire $gt$libresoc.v:170193$11450_Y + attribute \src "libresoc.v:170194.18-170194.97" + wire $gt$libresoc.v:170194$11451_Y + attribute \src "libresoc.v:170195.18-170195.97" + wire $gt$libresoc.v:170195$11452_Y + attribute \src "libresoc.v:170196.18-170196.97" + wire $gt$libresoc.v:170196$11453_Y + attribute \src "libresoc.v:170197.18-170197.97" + wire $gt$libresoc.v:170197$11454_Y + attribute \src "libresoc.v:170198.18-170198.97" + wire $gt$libresoc.v:170198$11455_Y + attribute \src "libresoc.v:170199.18-170199.97" + wire $gt$libresoc.v:170199$11456_Y + attribute \src "libresoc.v:170200.18-170200.98" + wire $gt$libresoc.v:170200$11457_Y + attribute \src "libresoc.v:170201.18-170201.98" + wire $gt$libresoc.v:170201$11458_Y + attribute \src "libresoc.v:170202.18-170202.98" + wire $gt$libresoc.v:170202$11459_Y + attribute \src "libresoc.v:170203.17-170203.96" + wire $gt$libresoc.v:170203$11460_Y + attribute \src "libresoc.v:170204.18-170204.98" + wire $gt$libresoc.v:170204$11461_Y + attribute \src "libresoc.v:170205.18-170205.98" + wire $gt$libresoc.v:170205$11462_Y + attribute \src "libresoc.v:170206.18-170206.98" + wire $gt$libresoc.v:170206$11463_Y + attribute \src "libresoc.v:170207.18-170207.98" + wire $gt$libresoc.v:170207$11464_Y + attribute \src "libresoc.v:170208.18-170208.98" + wire $gt$libresoc.v:170208$11465_Y + attribute \src "libresoc.v:170209.18-170209.98" + wire $gt$libresoc.v:170209$11466_Y + attribute \src "libresoc.v:170210.18-170210.98" + wire $gt$libresoc.v:170210$11467_Y + attribute \src "libresoc.v:170211.18-170211.98" + wire $gt$libresoc.v:170211$11468_Y + attribute \src "libresoc.v:170212.18-170212.98" + wire $gt$libresoc.v:170212$11469_Y + attribute \src "libresoc.v:170213.18-170213.98" + wire $gt$libresoc.v:170213$11470_Y + attribute \src "libresoc.v:170214.17-170214.96" + wire $gt$libresoc.v:170214$11471_Y + attribute \src "libresoc.v:170215.18-170215.98" + wire $gt$libresoc.v:170215$11472_Y + attribute \src "libresoc.v:170216.18-170216.98" + wire $gt$libresoc.v:170216$11473_Y + attribute \src "libresoc.v:170217.18-170217.98" + wire $gt$libresoc.v:170217$11474_Y + attribute \src "libresoc.v:170218.18-170218.98" + wire $gt$libresoc.v:170218$11475_Y + attribute \src "libresoc.v:170219.18-170219.98" + wire $gt$libresoc.v:170219$11476_Y + attribute \src "libresoc.v:170220.18-170220.98" + wire $gt$libresoc.v:170220$11477_Y + attribute \src "libresoc.v:170221.18-170221.98" + wire $gt$libresoc.v:170221$11478_Y + attribute \src "libresoc.v:170222.18-170222.98" + wire $gt$libresoc.v:170222$11479_Y + attribute \src "libresoc.v:170223.18-170223.98" + wire $gt$libresoc.v:170223$11480_Y + attribute \src "libresoc.v:170224.18-170224.98" + wire $gt$libresoc.v:170224$11481_Y + attribute \src "libresoc.v:170225.17-170225.96" + wire $gt$libresoc.v:170225$11482_Y + attribute \src "libresoc.v:170226.18-170226.98" + wire $gt$libresoc.v:170226$11483_Y + attribute \src "libresoc.v:170227.18-170227.98" + wire $gt$libresoc.v:170227$11484_Y + attribute \src "libresoc.v:170228.18-170228.98" + wire $gt$libresoc.v:170228$11485_Y + attribute \src "libresoc.v:170229.18-170229.98" + wire $gt$libresoc.v:170229$11486_Y + attribute \src "libresoc.v:170230.18-170230.98" + wire $gt$libresoc.v:170230$11487_Y + attribute \src "libresoc.v:170231.18-170231.98" + wire $gt$libresoc.v:170231$11488_Y + attribute \src "libresoc.v:170232.18-170232.98" + wire $gt$libresoc.v:170232$11489_Y + attribute \src "libresoc.v:170233.18-170233.98" + wire $gt$libresoc.v:170233$11490_Y + attribute \src "libresoc.v:170234.18-170234.98" + wire $gt$libresoc.v:170234$11491_Y + attribute \src "libresoc.v:170235.18-170235.98" + wire $gt$libresoc.v:170235$11492_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$101 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$103 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$105 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$107 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$109 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$111 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$113 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$115 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$117 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$119 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$121 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$123 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$125 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$127 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$17 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$21 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$25 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$29 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$33 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$35 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$37 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$39 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$41 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$43 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$45 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$47 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$49 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$51 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$53 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$55 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$57 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$59 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$61 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$63 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$65 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$67 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$69 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$71 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$73 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$75 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$77 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$79 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$81 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$83 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$85 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$87 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$89 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$91 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$93 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$95 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$97 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$99 + attribute \src "libresoc.v:170038.7-170038.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:12" + wire width 64 output 1 \mask + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:11" + wire width 7 input 2 \shift + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:170172$11429 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 3'100 + connect \Y $gt$libresoc.v:170172$11429_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:170173$11430 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'110001 + connect \Y $gt$libresoc.v:170173$11430_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:170174$11431 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'110010 + connect \Y $gt$libresoc.v:170174$11431_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:170175$11432 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'110011 + connect \Y $gt$libresoc.v:170175$11432_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:170176$11433 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'110100 + connect \Y $gt$libresoc.v:170176$11433_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:170177$11434 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'110101 + connect \Y $gt$libresoc.v:170177$11434_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:170178$11435 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'110110 + connect \Y $gt$libresoc.v:170178$11435_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:170179$11436 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'110111 + connect \Y $gt$libresoc.v:170179$11436_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:170180$11437 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'111000 + connect \Y $gt$libresoc.v:170180$11437_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:170181$11438 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'111001 + connect \Y $gt$libresoc.v:170181$11438_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:170182$11439 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'111010 + connect \Y $gt$libresoc.v:170182$11439_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:170183$11440 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 3'101 + connect \Y $gt$libresoc.v:170183$11440_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:170184$11441 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'111011 + connect \Y $gt$libresoc.v:170184$11441_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:170185$11442 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'111100 + connect \Y $gt$libresoc.v:170185$11442_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:170186$11443 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'111101 + connect \Y $gt$libresoc.v:170186$11443_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:170187$11444 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'111110 + connect \Y $gt$libresoc.v:170187$11444_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:170188$11445 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'111111 + connect \Y $gt$libresoc.v:170188$11445_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:170189$11446 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 3'110 + connect \Y $gt$libresoc.v:170189$11446_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:170190$11447 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 3'111 + connect \Y $gt$libresoc.v:170190$11447_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:170191$11448 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 4'1000 + connect \Y $gt$libresoc.v:170191$11448_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:170192$11449 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 1'0 + connect \Y $gt$libresoc.v:170192$11449_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:170193$11450 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 4'1001 + connect \Y $gt$libresoc.v:170193$11450_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:170194$11451 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 4'1010 + connect \Y $gt$libresoc.v:170194$11451_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:170195$11452 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 4'1011 + connect \Y $gt$libresoc.v:170195$11452_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:170196$11453 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 4'1100 + connect \Y $gt$libresoc.v:170196$11453_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:170197$11454 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 4'1101 + connect \Y $gt$libresoc.v:170197$11454_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:170198$11455 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 4'1110 + connect \Y $gt$libresoc.v:170198$11455_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:170199$11456 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 4'1111 + connect \Y $gt$libresoc.v:170199$11456_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:170200$11457 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'10000 + connect \Y $gt$libresoc.v:170200$11457_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:170201$11458 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'10001 + connect \Y $gt$libresoc.v:170201$11458_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:170202$11459 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'10010 + connect \Y $gt$libresoc.v:170202$11459_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:170203$11460 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 1'1 + connect \Y $gt$libresoc.v:170203$11460_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:170204$11461 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'10011 + connect \Y $gt$libresoc.v:170204$11461_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:170205$11462 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'10100 + connect \Y $gt$libresoc.v:170205$11462_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:170206$11463 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'10101 + connect \Y $gt$libresoc.v:170206$11463_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:170207$11464 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'10110 + connect \Y $gt$libresoc.v:170207$11464_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:170208$11465 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'10111 + connect \Y $gt$libresoc.v:170208$11465_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:170209$11466 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'11000 + connect \Y $gt$libresoc.v:170209$11466_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:170210$11467 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'11001 + connect \Y $gt$libresoc.v:170210$11467_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:170211$11468 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'11010 + connect \Y $gt$libresoc.v:170211$11468_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:170212$11469 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'11011 + connect \Y $gt$libresoc.v:170212$11469_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:170213$11470 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'11100 + connect \Y $gt$libresoc.v:170213$11470_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:170214$11471 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 2'10 + connect \Y $gt$libresoc.v:170214$11471_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:170215$11472 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'11101 + connect \Y $gt$libresoc.v:170215$11472_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:170216$11473 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'11110 + connect \Y $gt$libresoc.v:170216$11473_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:170217$11474 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'11111 + connect \Y $gt$libresoc.v:170217$11474_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:170218$11475 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'100000 + connect \Y $gt$libresoc.v:170218$11475_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:170219$11476 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'100001 + connect \Y $gt$libresoc.v:170219$11476_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:170220$11477 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'100010 + connect \Y $gt$libresoc.v:170220$11477_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:170221$11478 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'100011 + connect \Y $gt$libresoc.v:170221$11478_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:170222$11479 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'100100 + connect \Y $gt$libresoc.v:170222$11479_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:170223$11480 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'100101 + connect \Y $gt$libresoc.v:170223$11480_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:170224$11481 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'100110 + connect \Y $gt$libresoc.v:170224$11481_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:170225$11482 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 2'11 + connect \Y $gt$libresoc.v:170225$11482_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:170226$11483 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'100111 + connect \Y $gt$libresoc.v:170226$11483_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:170227$11484 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'101000 + connect \Y $gt$libresoc.v:170227$11484_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:170228$11485 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'101001 + connect \Y $gt$libresoc.v:170228$11485_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:170229$11486 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'101010 + connect \Y $gt$libresoc.v:170229$11486_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:170230$11487 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'101011 + connect \Y $gt$libresoc.v:170230$11487_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:170231$11488 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'101100 + connect \Y $gt$libresoc.v:170231$11488_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:170232$11489 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'101101 + connect \Y $gt$libresoc.v:170232$11489_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:170233$11490 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'101110 + connect \Y $gt$libresoc.v:170233$11490_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:170234$11491 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'101111 + connect \Y $gt$libresoc.v:170234$11491_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$libresoc.v:170235$11492 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'110000 + connect \Y $gt$libresoc.v:170235$11492_Y + end + attribute \src "libresoc.v:170038.7-170038.20" + process $proc$libresoc.v:170038$11494 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:170236.3-170623.6" + process $proc$libresoc.v:170236$11493 + assign { } { } + assign { } { } + assign $0\mask[63:0] [0] $1\mask[0:0] + assign $0\mask[63:0] [1] $2\mask[1:1] + assign $0\mask[63:0] [2] $3\mask[2:2] + assign $0\mask[63:0] [3] $4\mask[3:3] + assign $0\mask[63:0] [4] $5\mask[4:4] + assign $0\mask[63:0] [5] $6\mask[5:5] + assign $0\mask[63:0] [6] $7\mask[6:6] + assign $0\mask[63:0] [7] $8\mask[7:7] + assign $0\mask[63:0] [8] $9\mask[8:8] + assign $0\mask[63:0] [9] $10\mask[9:9] + assign $0\mask[63:0] [10] $11\mask[10:10] + assign $0\mask[63:0] [11] $12\mask[11:11] + assign $0\mask[63:0] [12] $13\mask[12:12] + assign $0\mask[63:0] [13] $14\mask[13:13] + assign $0\mask[63:0] [14] $15\mask[14:14] + assign $0\mask[63:0] [15] $16\mask[15:15] + assign $0\mask[63:0] [16] $17\mask[16:16] + assign $0\mask[63:0] [17] $18\mask[17:17] + assign $0\mask[63:0] [18] $19\mask[18:18] + assign $0\mask[63:0] [19] $20\mask[19:19] + assign $0\mask[63:0] [20] $21\mask[20:20] + assign $0\mask[63:0] [21] $22\mask[21:21] + assign $0\mask[63:0] [22] $23\mask[22:22] + assign $0\mask[63:0] [23] $24\mask[23:23] + assign $0\mask[63:0] [24] $25\mask[24:24] + assign $0\mask[63:0] [25] $26\mask[25:25] + assign $0\mask[63:0] [26] $27\mask[26:26] + assign $0\mask[63:0] [27] $28\mask[27:27] + assign $0\mask[63:0] [28] $29\mask[28:28] + assign $0\mask[63:0] [29] $30\mask[29:29] + assign $0\mask[63:0] [30] $31\mask[30:30] + assign $0\mask[63:0] [31] $32\mask[31:31] + assign $0\mask[63:0] [32] $33\mask[32:32] + assign $0\mask[63:0] [33] $34\mask[33:33] + assign $0\mask[63:0] [34] $35\mask[34:34] + assign $0\mask[63:0] [35] $36\mask[35:35] + assign $0\mask[63:0] [36] $37\mask[36:36] + assign $0\mask[63:0] [37] $38\mask[37:37] + assign $0\mask[63:0] [38] $39\mask[38:38] + assign $0\mask[63:0] [39] $40\mask[39:39] + assign $0\mask[63:0] [40] $41\mask[40:40] + assign $0\mask[63:0] [41] $42\mask[41:41] + assign $0\mask[63:0] [42] $43\mask[42:42] + assign $0\mask[63:0] [43] $44\mask[43:43] + assign $0\mask[63:0] [44] $45\mask[44:44] + assign $0\mask[63:0] [45] $46\mask[45:45] + assign $0\mask[63:0] [46] $47\mask[46:46] + assign $0\mask[63:0] [47] $48\mask[47:47] + assign $0\mask[63:0] [48] $49\mask[48:48] + assign $0\mask[63:0] [49] $50\mask[49:49] + assign $0\mask[63:0] [50] $51\mask[50:50] + assign $0\mask[63:0] [51] $52\mask[51:51] + assign $0\mask[63:0] [52] $53\mask[52:52] + assign $0\mask[63:0] [53] $54\mask[53:53] + assign $0\mask[63:0] [54] $55\mask[54:54] + assign $0\mask[63:0] [55] $56\mask[55:55] + assign $0\mask[63:0] [56] $57\mask[56:56] + assign $0\mask[63:0] [57] $58\mask[57:57] + assign $0\mask[63:0] [58] $59\mask[58:58] + assign $0\mask[63:0] [59] $60\mask[59:59] + assign $0\mask[63:0] [60] $61\mask[60:60] + assign $0\mask[63:0] [61] $62\mask[61:61] + assign $0\mask[63:0] [62] $63\mask[62:62] + assign $0\mask[63:0] [63] $64\mask[63:63] + attribute \src "libresoc.v:170237.5-170237.29" + switch \initial + attribute \src "libresoc.v:170237.9-170237.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\mask[0:0] 1'1 + case + assign $1\mask[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\mask[1:1] 1'1 + case + assign $2\mask[1:1] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$5 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\mask[2:2] 1'1 + case + assign $3\mask[2:2] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$7 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\mask[3:3] 1'1 + case + assign $4\mask[3:3] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$9 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\mask[4:4] 1'1 + case + assign $5\mask[4:4] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$11 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\mask[5:5] 1'1 + case + assign $6\mask[5:5] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$13 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\mask[6:6] 1'1 + case + assign $7\mask[6:6] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$15 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $8\mask[7:7] 1'1 + case + assign $8\mask[7:7] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$17 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $9\mask[8:8] 1'1 + case + assign $9\mask[8:8] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$19 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $10\mask[9:9] 1'1 + case + assign $10\mask[9:9] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$21 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $11\mask[10:10] 1'1 + case + assign $11\mask[10:10] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$23 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $12\mask[11:11] 1'1 + case + assign $12\mask[11:11] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$25 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $13\mask[12:12] 1'1 + case + assign $13\mask[12:12] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$27 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $14\mask[13:13] 1'1 + case + assign $14\mask[13:13] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$29 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $15\mask[14:14] 1'1 + case + assign $15\mask[14:14] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$31 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $16\mask[15:15] 1'1 + case + assign $16\mask[15:15] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$33 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $17\mask[16:16] 1'1 + case + assign $17\mask[16:16] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$35 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $18\mask[17:17] 1'1 + case + assign $18\mask[17:17] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$37 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $19\mask[18:18] 1'1 + case + assign $19\mask[18:18] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$39 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $20\mask[19:19] 1'1 + case + assign $20\mask[19:19] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$41 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $21\mask[20:20] 1'1 + case + assign $21\mask[20:20] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$43 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $22\mask[21:21] 1'1 + case + assign $22\mask[21:21] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$45 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $23\mask[22:22] 1'1 + case + assign $23\mask[22:22] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$47 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $24\mask[23:23] 1'1 + case + assign $24\mask[23:23] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$49 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $25\mask[24:24] 1'1 + case + assign $25\mask[24:24] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$51 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $26\mask[25:25] 1'1 + case + assign $26\mask[25:25] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$53 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $27\mask[26:26] 1'1 + case + assign $27\mask[26:26] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$55 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $28\mask[27:27] 1'1 + case + assign $28\mask[27:27] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$57 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $29\mask[28:28] 1'1 + case + assign $29\mask[28:28] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$59 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $30\mask[29:29] 1'1 + case + assign $30\mask[29:29] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$61 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $31\mask[30:30] 1'1 + case + assign $31\mask[30:30] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$63 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $32\mask[31:31] 1'1 + case + assign $32\mask[31:31] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$65 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $33\mask[32:32] 1'1 + case + assign $33\mask[32:32] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$67 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $34\mask[33:33] 1'1 + case + assign $34\mask[33:33] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$69 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $35\mask[34:34] 1'1 + case + assign $35\mask[34:34] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$71 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $36\mask[35:35] 1'1 + case + assign $36\mask[35:35] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$73 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $37\mask[36:36] 1'1 + case + assign $37\mask[36:36] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$75 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $38\mask[37:37] 1'1 + case + assign $38\mask[37:37] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$77 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $39\mask[38:38] 1'1 + case + assign $39\mask[38:38] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$79 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $40\mask[39:39] 1'1 + case + assign $40\mask[39:39] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$81 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $41\mask[40:40] 1'1 + case + assign $41\mask[40:40] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$83 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $42\mask[41:41] 1'1 + case + assign $42\mask[41:41] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$85 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $43\mask[42:42] 1'1 + case + assign $43\mask[42:42] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$87 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $44\mask[43:43] 1'1 + case + assign $44\mask[43:43] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$89 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $45\mask[44:44] 1'1 + case + assign $45\mask[44:44] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$91 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $46\mask[45:45] 1'1 + case + assign $46\mask[45:45] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$93 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $47\mask[46:46] 1'1 + case + assign $47\mask[46:46] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$95 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $48\mask[47:47] 1'1 + case + assign $48\mask[47:47] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$97 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $49\mask[48:48] 1'1 + case + assign $49\mask[48:48] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$99 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $50\mask[49:49] 1'1 + case + assign $50\mask[49:49] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$101 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $51\mask[50:50] 1'1 + case + assign $51\mask[50:50] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$103 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $52\mask[51:51] 1'1 + case + assign $52\mask[51:51] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$105 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $53\mask[52:52] 1'1 + case + assign $53\mask[52:52] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$107 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $54\mask[53:53] 1'1 + case + assign $54\mask[53:53] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$109 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $55\mask[54:54] 1'1 + case + assign $55\mask[54:54] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$111 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $56\mask[55:55] 1'1 + case + assign $56\mask[55:55] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$113 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $57\mask[56:56] 1'1 + case + assign $57\mask[56:56] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$115 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $58\mask[57:57] 1'1 + case + assign $58\mask[57:57] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$117 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $59\mask[58:58] 1'1 + case + assign $59\mask[58:58] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$119 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $60\mask[59:59] 1'1 + case + assign $60\mask[59:59] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$121 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $61\mask[60:60] 1'1 + case + assign $61\mask[60:60] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$123 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $62\mask[61:61] 1'1 + case + assign $62\mask[61:61] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$125 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $63\mask[62:62] 1'1 + case + assign $63\mask[62:62] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$127 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $64\mask[63:63] 1'1 + case + assign $64\mask[63:63] 1'0 + end + sync always + update \mask $0\mask[63:0] + end + connect \$9 $gt$libresoc.v:170172$11429_Y + connect \$99 $gt$libresoc.v:170173$11430_Y + connect \$101 $gt$libresoc.v:170174$11431_Y + connect \$103 $gt$libresoc.v:170175$11432_Y + connect \$105 $gt$libresoc.v:170176$11433_Y + connect \$107 $gt$libresoc.v:170177$11434_Y + connect \$109 $gt$libresoc.v:170178$11435_Y + connect \$111 $gt$libresoc.v:170179$11436_Y + connect \$113 $gt$libresoc.v:170180$11437_Y + connect \$115 $gt$libresoc.v:170181$11438_Y + connect \$117 $gt$libresoc.v:170182$11439_Y + connect \$11 $gt$libresoc.v:170183$11440_Y + connect \$119 $gt$libresoc.v:170184$11441_Y + connect \$121 $gt$libresoc.v:170185$11442_Y + connect \$123 $gt$libresoc.v:170186$11443_Y + connect \$125 $gt$libresoc.v:170187$11444_Y + connect \$127 $gt$libresoc.v:170188$11445_Y + connect \$13 $gt$libresoc.v:170189$11446_Y + connect \$15 $gt$libresoc.v:170190$11447_Y + connect \$17 $gt$libresoc.v:170191$11448_Y + connect \$1 $gt$libresoc.v:170192$11449_Y + connect \$19 $gt$libresoc.v:170193$11450_Y + connect \$21 $gt$libresoc.v:170194$11451_Y + connect \$23 $gt$libresoc.v:170195$11452_Y + connect \$25 $gt$libresoc.v:170196$11453_Y + connect \$27 $gt$libresoc.v:170197$11454_Y + connect \$29 $gt$libresoc.v:170198$11455_Y + connect \$31 $gt$libresoc.v:170199$11456_Y + connect \$33 $gt$libresoc.v:170200$11457_Y + connect \$35 $gt$libresoc.v:170201$11458_Y + connect \$37 $gt$libresoc.v:170202$11459_Y + connect \$3 $gt$libresoc.v:170203$11460_Y + connect \$39 $gt$libresoc.v:170204$11461_Y + connect \$41 $gt$libresoc.v:170205$11462_Y + connect \$43 $gt$libresoc.v:170206$11463_Y + connect \$45 $gt$libresoc.v:170207$11464_Y + connect \$47 $gt$libresoc.v:170208$11465_Y + connect \$49 $gt$libresoc.v:170209$11466_Y + connect \$51 $gt$libresoc.v:170210$11467_Y + connect \$53 $gt$libresoc.v:170211$11468_Y + connect \$55 $gt$libresoc.v:170212$11469_Y + connect \$57 $gt$libresoc.v:170213$11470_Y + connect \$5 $gt$libresoc.v:170214$11471_Y + connect \$59 $gt$libresoc.v:170215$11472_Y + connect \$61 $gt$libresoc.v:170216$11473_Y + connect \$63 $gt$libresoc.v:170217$11474_Y + connect \$65 $gt$libresoc.v:170218$11475_Y + connect \$67 $gt$libresoc.v:170219$11476_Y + connect \$69 $gt$libresoc.v:170220$11477_Y + connect \$71 $gt$libresoc.v:170221$11478_Y + connect \$73 $gt$libresoc.v:170222$11479_Y + connect \$75 $gt$libresoc.v:170223$11480_Y + connect \$77 $gt$libresoc.v:170224$11481_Y + connect \$7 $gt$libresoc.v:170225$11482_Y + connect \$79 $gt$libresoc.v:170226$11483_Y + connect \$81 $gt$libresoc.v:170227$11484_Y + connect \$83 $gt$libresoc.v:170228$11485_Y + connect \$85 $gt$libresoc.v:170229$11486_Y + connect \$87 $gt$libresoc.v:170230$11487_Y + connect \$89 $gt$libresoc.v:170231$11488_Y + connect \$91 $gt$libresoc.v:170232$11489_Y + connect \$93 $gt$libresoc.v:170233$11490_Y + connect \$95 $gt$libresoc.v:170234$11491_Y + connect \$97 $gt$libresoc.v:170235$11492_Y +end +attribute \src "libresoc.v:170628.1-170686.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.rok_l" +attribute \generator "nMigen" +module \rok_l + attribute \src "libresoc.v:170629.7-170629.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:170674.3-170682.6" + wire $0\q_int$next[0:0]$11505 + attribute \src "libresoc.v:170672.3-170673.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:170674.3-170682.6" + wire $1\q_int$next[0:0]$11506 + attribute \src "libresoc.v:170651.7-170651.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:170664.17-170664.96" + wire $and$libresoc.v:170664$11495_Y + attribute \src "libresoc.v:170669.17-170669.96" + wire $and$libresoc.v:170669$11500_Y + attribute \src "libresoc.v:170666.18-170666.94" + wire $not$libresoc.v:170666$11497_Y + attribute \src "libresoc.v:170668.17-170668.93" + wire $not$libresoc.v:170668$11499_Y + attribute \src "libresoc.v:170671.17-170671.93" + wire $not$libresoc.v:170671$11502_Y + attribute \src "libresoc.v:170665.18-170665.99" + wire $or$libresoc.v:170665$11496_Y + attribute \src "libresoc.v:170667.18-170667.100" + wire $or$libresoc.v:170667$11498_Y + attribute \src "libresoc.v:170670.17-170670.98" + wire $or$libresoc.v:170670$11501_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 1 \coresync_rst + attribute \src "libresoc.v:170629.7-170629.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 2 \q_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 4 \r_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 3 \s_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$libresoc.v:170664$11495 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:170664$11495_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:170669$11500 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:170669$11500_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:170666$11497 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rdok + connect \Y $not$libresoc.v:170666$11497_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:170668$11499 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rdok + connect \Y $not$libresoc.v:170668$11499_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:170671$11502 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rdok + connect \Y $not$libresoc.v:170671$11502_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:170665$11496 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_rdok + connect \Y $or$libresoc.v:170665$11496_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:170667$11498 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rdok + connect \B \q_int + connect \Y $or$libresoc.v:170667$11498_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:170670$11501 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_rdok + connect \Y $or$libresoc.v:170670$11501_Y + end + attribute \src "libresoc.v:170629.7-170629.20" + process $proc$libresoc.v:170629$11507 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:170651.7-170651.19" + process $proc$libresoc.v:170651$11508 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:170672.3-170673.27" + process $proc$libresoc.v:170672$11503 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:170674.3-170682.6" + process $proc$libresoc.v:170674$11504 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$11505 $1\q_int$next[0:0]$11506 + attribute \src "libresoc.v:170675.5-170675.29" + switch \initial + attribute \src "libresoc.v:170675.9-170675.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$11506 1'0 + case + assign $1\q_int$next[0:0]$11506 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$11505 + end + connect \$9 $and$libresoc.v:170664$11495_Y + connect \$11 $or$libresoc.v:170665$11496_Y + connect \$13 $not$libresoc.v:170666$11497_Y + connect \$15 $or$libresoc.v:170667$11498_Y + connect \$1 $not$libresoc.v:170668$11499_Y + connect \$3 $and$libresoc.v:170669$11500_Y + connect \$5 $or$libresoc.v:170670$11501_Y + connect \$7 $not$libresoc.v:170671$11502_Y + connect \qlq_rdok \$15 + connect \qn_rdok \$13 + connect \q_rdok \$11 +end +attribute \src "libresoc.v:170690.1-170748.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.rok_l" +attribute \generator "nMigen" +module \rok_l$102 + attribute \src "libresoc.v:170691.7-170691.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:170736.3-170744.6" + wire $0\q_int$next[0:0]$11519 + attribute \src "libresoc.v:170734.3-170735.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:170736.3-170744.6" + wire $1\q_int$next[0:0]$11520 + attribute \src "libresoc.v:170713.7-170713.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:170726.17-170726.96" + wire $and$libresoc.v:170726$11509_Y + attribute \src "libresoc.v:170731.17-170731.96" + wire $and$libresoc.v:170731$11514_Y + attribute \src "libresoc.v:170728.18-170728.94" + wire $not$libresoc.v:170728$11511_Y + attribute \src "libresoc.v:170730.17-170730.93" + wire $not$libresoc.v:170730$11513_Y + attribute \src "libresoc.v:170733.17-170733.93" + wire $not$libresoc.v:170733$11516_Y + attribute \src "libresoc.v:170727.18-170727.99" + wire $or$libresoc.v:170727$11510_Y + attribute \src "libresoc.v:170729.18-170729.100" + wire $or$libresoc.v:170729$11512_Y + attribute \src "libresoc.v:170732.17-170732.98" + wire $or$libresoc.v:170732$11515_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 1 \coresync_rst + attribute \src "libresoc.v:170691.7-170691.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 2 \q_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 4 \r_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 3 \s_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$libresoc.v:170726$11509 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:170726$11509_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:170731$11514 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:170731$11514_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:170728$11511 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rdok + connect \Y $not$libresoc.v:170728$11511_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:170730$11513 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rdok + connect \Y $not$libresoc.v:170730$11513_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:170733$11516 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rdok + connect \Y $not$libresoc.v:170733$11516_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:170727$11510 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_rdok + connect \Y $or$libresoc.v:170727$11510_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:170729$11512 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rdok + connect \B \q_int + connect \Y $or$libresoc.v:170729$11512_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:170732$11515 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_rdok + connect \Y $or$libresoc.v:170732$11515_Y + end + attribute \src "libresoc.v:170691.7-170691.20" + process $proc$libresoc.v:170691$11521 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:170713.7-170713.19" + process $proc$libresoc.v:170713$11522 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:170734.3-170735.27" + process $proc$libresoc.v:170734$11517 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:170736.3-170744.6" + process $proc$libresoc.v:170736$11518 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$11519 $1\q_int$next[0:0]$11520 + attribute \src "libresoc.v:170737.5-170737.29" + switch \initial + attribute \src "libresoc.v:170737.9-170737.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$11520 1'0 + case + assign $1\q_int$next[0:0]$11520 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$11519 + end + connect \$9 $and$libresoc.v:170726$11509_Y + connect \$11 $or$libresoc.v:170727$11510_Y + connect \$13 $not$libresoc.v:170728$11511_Y + connect \$15 $or$libresoc.v:170729$11512_Y + connect \$1 $not$libresoc.v:170730$11513_Y + connect \$3 $and$libresoc.v:170731$11514_Y + connect \$5 $or$libresoc.v:170732$11515_Y + connect \$7 $not$libresoc.v:170733$11516_Y + connect \qlq_rdok \$15 + connect \qn_rdok \$13 + connect \q_rdok \$11 +end +attribute \src "libresoc.v:170752.1-170810.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.rok_l" +attribute \generator "nMigen" +module \rok_l$120 + attribute \src "libresoc.v:170753.7-170753.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:170798.3-170806.6" + wire $0\q_int$next[0:0]$11533 + attribute \src "libresoc.v:170796.3-170797.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:170798.3-170806.6" + wire $1\q_int$next[0:0]$11534 + attribute \src "libresoc.v:170775.7-170775.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:170788.17-170788.96" + wire $and$libresoc.v:170788$11523_Y + attribute \src "libresoc.v:170793.17-170793.96" + wire $and$libresoc.v:170793$11528_Y + attribute \src "libresoc.v:170790.18-170790.94" + wire $not$libresoc.v:170790$11525_Y + attribute \src "libresoc.v:170792.17-170792.93" + wire $not$libresoc.v:170792$11527_Y + attribute \src "libresoc.v:170795.17-170795.93" + wire $not$libresoc.v:170795$11530_Y + attribute \src "libresoc.v:170789.18-170789.99" + wire $or$libresoc.v:170789$11524_Y + attribute \src "libresoc.v:170791.18-170791.100" + wire $or$libresoc.v:170791$11526_Y + attribute \src "libresoc.v:170794.17-170794.98" + wire $or$libresoc.v:170794$11529_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 1 \coresync_rst + attribute \src "libresoc.v:170753.7-170753.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 2 \q_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 4 \r_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 3 \s_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$libresoc.v:170788$11523 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:170788$11523_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:170793$11528 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:170793$11528_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:170790$11525 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rdok + connect \Y $not$libresoc.v:170790$11525_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:170792$11527 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rdok + connect \Y $not$libresoc.v:170792$11527_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:170795$11530 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rdok + connect \Y $not$libresoc.v:170795$11530_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:170789$11524 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_rdok + connect \Y $or$libresoc.v:170789$11524_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:170791$11526 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rdok + connect \B \q_int + connect \Y $or$libresoc.v:170791$11526_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:170794$11529 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_rdok + connect \Y $or$libresoc.v:170794$11529_Y + end + attribute \src "libresoc.v:170753.7-170753.20" + process $proc$libresoc.v:170753$11535 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:170775.7-170775.19" + process $proc$libresoc.v:170775$11536 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:170796.3-170797.27" + process $proc$libresoc.v:170796$11531 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:170798.3-170806.6" + process $proc$libresoc.v:170798$11532 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$11533 $1\q_int$next[0:0]$11534 + attribute \src "libresoc.v:170799.5-170799.29" + switch \initial + attribute \src "libresoc.v:170799.9-170799.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$11534 1'0 + case + assign $1\q_int$next[0:0]$11534 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$11533 + end + connect \$9 $and$libresoc.v:170788$11523_Y + connect \$11 $or$libresoc.v:170789$11524_Y + connect \$13 $not$libresoc.v:170790$11525_Y + connect \$15 $or$libresoc.v:170791$11526_Y + connect \$1 $not$libresoc.v:170792$11527_Y + connect \$3 $and$libresoc.v:170793$11528_Y + connect \$5 $or$libresoc.v:170794$11529_Y + connect \$7 $not$libresoc.v:170795$11530_Y + connect \qlq_rdok \$15 + connect \qn_rdok \$13 + connect \q_rdok \$11 +end +attribute \src "libresoc.v:170814.1-170872.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.rok_l" +attribute \generator "nMigen" +module \rok_l$14 + attribute \src "libresoc.v:170815.7-170815.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:170860.3-170868.6" + wire $0\q_int$next[0:0]$11547 + attribute \src "libresoc.v:170858.3-170859.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:170860.3-170868.6" + wire $1\q_int$next[0:0]$11548 + attribute \src "libresoc.v:170837.7-170837.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:170850.17-170850.96" + wire $and$libresoc.v:170850$11537_Y + attribute \src "libresoc.v:170855.17-170855.96" + wire $and$libresoc.v:170855$11542_Y + attribute \src "libresoc.v:170852.18-170852.94" + wire $not$libresoc.v:170852$11539_Y + attribute \src "libresoc.v:170854.17-170854.93" + wire $not$libresoc.v:170854$11541_Y + attribute \src "libresoc.v:170857.17-170857.93" + wire $not$libresoc.v:170857$11544_Y + attribute \src "libresoc.v:170851.18-170851.99" + wire $or$libresoc.v:170851$11538_Y + attribute \src "libresoc.v:170853.18-170853.100" + wire $or$libresoc.v:170853$11540_Y + attribute \src "libresoc.v:170856.17-170856.98" + wire $or$libresoc.v:170856$11543_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 1 \coresync_rst + attribute \src "libresoc.v:170815.7-170815.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 2 \q_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 4 \r_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 3 \s_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$libresoc.v:170850$11537 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:170850$11537_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:170855$11542 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:170855$11542_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:170852$11539 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rdok + connect \Y $not$libresoc.v:170852$11539_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:170854$11541 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rdok + connect \Y $not$libresoc.v:170854$11541_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:170857$11544 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rdok + connect \Y $not$libresoc.v:170857$11544_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:170851$11538 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_rdok + connect \Y $or$libresoc.v:170851$11538_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:170853$11540 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rdok + connect \B \q_int + connect \Y $or$libresoc.v:170853$11540_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:170856$11543 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_rdok + connect \Y $or$libresoc.v:170856$11543_Y + end + attribute \src "libresoc.v:170815.7-170815.20" + process $proc$libresoc.v:170815$11549 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:170837.7-170837.19" + process $proc$libresoc.v:170837$11550 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:170858.3-170859.27" + process $proc$libresoc.v:170858$11545 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:170860.3-170868.6" + process $proc$libresoc.v:170860$11546 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$11547 $1\q_int$next[0:0]$11548 + attribute \src "libresoc.v:170861.5-170861.29" + switch \initial + attribute \src "libresoc.v:170861.9-170861.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$11548 1'0 + case + assign $1\q_int$next[0:0]$11548 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$11547 + end + connect \$9 $and$libresoc.v:170850$11537_Y + connect \$11 $or$libresoc.v:170851$11538_Y + connect \$13 $not$libresoc.v:170852$11539_Y + connect \$15 $or$libresoc.v:170853$11540_Y + connect \$1 $not$libresoc.v:170854$11541_Y + connect \$3 $and$libresoc.v:170855$11542_Y + connect \$5 $or$libresoc.v:170856$11543_Y + connect \$7 $not$libresoc.v:170857$11544_Y + connect \qlq_rdok \$15 + connect \qn_rdok \$13 + connect \q_rdok \$11 +end +attribute \src "libresoc.v:170876.1-170934.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.rok_l" +attribute \generator "nMigen" +module \rok_l$27 + attribute \src "libresoc.v:170877.7-170877.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:170922.3-170930.6" + wire $0\q_int$next[0:0]$11561 + attribute \src "libresoc.v:170920.3-170921.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:170922.3-170930.6" + wire $1\q_int$next[0:0]$11562 + attribute \src "libresoc.v:170899.7-170899.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:170912.17-170912.96" + wire $and$libresoc.v:170912$11551_Y + attribute \src "libresoc.v:170917.17-170917.96" + wire $and$libresoc.v:170917$11556_Y + attribute \src "libresoc.v:170914.18-170914.94" + wire $not$libresoc.v:170914$11553_Y + attribute \src "libresoc.v:170916.17-170916.93" + wire $not$libresoc.v:170916$11555_Y + attribute \src "libresoc.v:170919.17-170919.93" + wire $not$libresoc.v:170919$11558_Y + attribute \src "libresoc.v:170913.18-170913.99" + wire $or$libresoc.v:170913$11552_Y + attribute \src "libresoc.v:170915.18-170915.100" + wire $or$libresoc.v:170915$11554_Y + attribute \src "libresoc.v:170918.17-170918.98" + wire $or$libresoc.v:170918$11557_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 1 \coresync_rst + attribute \src "libresoc.v:170877.7-170877.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 2 \q_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 4 \r_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 3 \s_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$libresoc.v:170912$11551 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:170912$11551_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:170917$11556 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:170917$11556_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:170914$11553 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rdok + connect \Y $not$libresoc.v:170914$11553_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:170916$11555 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rdok + connect \Y $not$libresoc.v:170916$11555_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:170919$11558 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rdok + connect \Y $not$libresoc.v:170919$11558_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:170913$11552 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_rdok + connect \Y $or$libresoc.v:170913$11552_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:170915$11554 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rdok + connect \B \q_int + connect \Y $or$libresoc.v:170915$11554_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:170918$11557 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_rdok + connect \Y $or$libresoc.v:170918$11557_Y + end + attribute \src "libresoc.v:170877.7-170877.20" + process $proc$libresoc.v:170877$11563 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:170899.7-170899.19" + process $proc$libresoc.v:170899$11564 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:170920.3-170921.27" + process $proc$libresoc.v:170920$11559 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:170922.3-170930.6" + process $proc$libresoc.v:170922$11560 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$11561 $1\q_int$next[0:0]$11562 + attribute \src "libresoc.v:170923.5-170923.29" + switch \initial + attribute \src "libresoc.v:170923.9-170923.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$11562 1'0 + case + assign $1\q_int$next[0:0]$11562 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$11561 + end + connect \$9 $and$libresoc.v:170912$11551_Y + connect \$11 $or$libresoc.v:170913$11552_Y + connect \$13 $not$libresoc.v:170914$11553_Y + connect \$15 $or$libresoc.v:170915$11554_Y + connect \$1 $not$libresoc.v:170916$11555_Y + connect \$3 $and$libresoc.v:170917$11556_Y + connect \$5 $or$libresoc.v:170918$11557_Y + connect \$7 $not$libresoc.v:170919$11558_Y + connect \qlq_rdok \$15 + connect \qn_rdok \$13 + connect \q_rdok \$11 +end +attribute \src "libresoc.v:170938.1-170996.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.rok_l" +attribute \generator "nMigen" +module \rok_l$40 + attribute \src "libresoc.v:170939.7-170939.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:170984.3-170992.6" + wire $0\q_int$next[0:0]$11575 + attribute \src "libresoc.v:170982.3-170983.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:170984.3-170992.6" + wire $1\q_int$next[0:0]$11576 + attribute \src "libresoc.v:170961.7-170961.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:170974.17-170974.96" + wire $and$libresoc.v:170974$11565_Y + attribute \src "libresoc.v:170979.17-170979.96" + wire $and$libresoc.v:170979$11570_Y + attribute \src "libresoc.v:170976.18-170976.94" + wire $not$libresoc.v:170976$11567_Y + attribute \src "libresoc.v:170978.17-170978.93" + wire $not$libresoc.v:170978$11569_Y + attribute \src "libresoc.v:170981.17-170981.93" + wire $not$libresoc.v:170981$11572_Y + attribute \src "libresoc.v:170975.18-170975.99" + wire $or$libresoc.v:170975$11566_Y + attribute \src "libresoc.v:170977.18-170977.100" + wire $or$libresoc.v:170977$11568_Y + attribute \src "libresoc.v:170980.17-170980.98" + wire $or$libresoc.v:170980$11571_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 1 \coresync_rst + attribute \src "libresoc.v:170939.7-170939.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 2 \q_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 4 \r_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 3 \s_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$libresoc.v:170974$11565 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:170974$11565_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:170979$11570 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:170979$11570_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:170976$11567 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rdok + connect \Y $not$libresoc.v:170976$11567_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:170978$11569 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rdok + connect \Y $not$libresoc.v:170978$11569_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:170981$11572 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rdok + connect \Y $not$libresoc.v:170981$11572_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:170975$11566 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_rdok + connect \Y $or$libresoc.v:170975$11566_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:170977$11568 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rdok + connect \B \q_int + connect \Y $or$libresoc.v:170977$11568_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:170980$11571 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_rdok + connect \Y $or$libresoc.v:170980$11571_Y + end + attribute \src "libresoc.v:170939.7-170939.20" + process $proc$libresoc.v:170939$11577 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:170961.7-170961.19" + process $proc$libresoc.v:170961$11578 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:170982.3-170983.27" + process $proc$libresoc.v:170982$11573 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:170984.3-170992.6" + process $proc$libresoc.v:170984$11574 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$11575 $1\q_int$next[0:0]$11576 + attribute \src "libresoc.v:170985.5-170985.29" + switch \initial + attribute \src "libresoc.v:170985.9-170985.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$11576 1'0 + case + assign $1\q_int$next[0:0]$11576 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$11575 + end + connect \$9 $and$libresoc.v:170974$11565_Y + connect \$11 $or$libresoc.v:170975$11566_Y + connect \$13 $not$libresoc.v:170976$11567_Y + connect \$15 $or$libresoc.v:170977$11568_Y + connect \$1 $not$libresoc.v:170978$11569_Y + connect \$3 $and$libresoc.v:170979$11570_Y + connect \$5 $or$libresoc.v:170980$11571_Y + connect \$7 $not$libresoc.v:170981$11572_Y + connect \qlq_rdok \$15 + connect \qn_rdok \$13 + connect \q_rdok \$11 +end +attribute \src "libresoc.v:171000.1-171058.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.rok_l" +attribute \generator "nMigen" +module \rok_l$56 + attribute \src "libresoc.v:171001.7-171001.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:171046.3-171054.6" + wire $0\q_int$next[0:0]$11589 + attribute \src "libresoc.v:171044.3-171045.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:171046.3-171054.6" + wire $1\q_int$next[0:0]$11590 + attribute \src "libresoc.v:171023.7-171023.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:171036.17-171036.96" + wire $and$libresoc.v:171036$11579_Y + attribute \src "libresoc.v:171041.17-171041.96" + wire $and$libresoc.v:171041$11584_Y + attribute \src "libresoc.v:171038.18-171038.94" + wire $not$libresoc.v:171038$11581_Y + attribute \src "libresoc.v:171040.17-171040.93" + wire $not$libresoc.v:171040$11583_Y + attribute \src "libresoc.v:171043.17-171043.93" + wire $not$libresoc.v:171043$11586_Y + attribute \src "libresoc.v:171037.18-171037.99" + wire $or$libresoc.v:171037$11580_Y + attribute \src "libresoc.v:171039.18-171039.100" + wire $or$libresoc.v:171039$11582_Y + attribute \src "libresoc.v:171042.17-171042.98" + wire $or$libresoc.v:171042$11585_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 1 \coresync_rst + attribute \src "libresoc.v:171001.7-171001.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 2 \q_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 4 \r_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 3 \s_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$libresoc.v:171036$11579 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:171036$11579_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:171041$11584 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:171041$11584_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:171038$11581 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rdok + connect \Y $not$libresoc.v:171038$11581_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:171040$11583 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rdok + connect \Y $not$libresoc.v:171040$11583_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:171043$11586 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rdok + connect \Y $not$libresoc.v:171043$11586_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:171037$11580 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_rdok + connect \Y $or$libresoc.v:171037$11580_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:171039$11582 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rdok + connect \B \q_int + connect \Y $or$libresoc.v:171039$11582_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:171042$11585 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_rdok + connect \Y $or$libresoc.v:171042$11585_Y + end + attribute \src "libresoc.v:171001.7-171001.20" + process $proc$libresoc.v:171001$11591 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:171023.7-171023.19" + process $proc$libresoc.v:171023$11592 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:171044.3-171045.27" + process $proc$libresoc.v:171044$11587 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:171046.3-171054.6" + process $proc$libresoc.v:171046$11588 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$11589 $1\q_int$next[0:0]$11590 + attribute \src "libresoc.v:171047.5-171047.29" + switch \initial + attribute \src "libresoc.v:171047.9-171047.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$11590 1'0 + case + assign $1\q_int$next[0:0]$11590 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$11589 + end + connect \$9 $and$libresoc.v:171036$11579_Y + connect \$11 $or$libresoc.v:171037$11580_Y + connect \$13 $not$libresoc.v:171038$11581_Y + connect \$15 $or$libresoc.v:171039$11582_Y + connect \$1 $not$libresoc.v:171040$11583_Y + connect \$3 $and$libresoc.v:171041$11584_Y + connect \$5 $or$libresoc.v:171042$11585_Y + connect \$7 $not$libresoc.v:171043$11586_Y + connect \qlq_rdok \$15 + connect \qn_rdok \$13 + connect \q_rdok \$11 +end +attribute \src "libresoc.v:171062.1-171120.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.rok_l" +attribute \generator "nMigen" +module \rok_l$68 + attribute \src "libresoc.v:171063.7-171063.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:171108.3-171116.6" + wire $0\q_int$next[0:0]$11603 + attribute \src "libresoc.v:171106.3-171107.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:171108.3-171116.6" + wire $1\q_int$next[0:0]$11604 + attribute \src "libresoc.v:171085.7-171085.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:171098.17-171098.96" + wire $and$libresoc.v:171098$11593_Y + attribute \src "libresoc.v:171103.17-171103.96" + wire $and$libresoc.v:171103$11598_Y + attribute \src "libresoc.v:171100.18-171100.94" + wire $not$libresoc.v:171100$11595_Y + attribute \src "libresoc.v:171102.17-171102.93" + wire $not$libresoc.v:171102$11597_Y + attribute \src "libresoc.v:171105.17-171105.93" + wire $not$libresoc.v:171105$11600_Y + attribute \src "libresoc.v:171099.18-171099.99" + wire $or$libresoc.v:171099$11594_Y + attribute \src "libresoc.v:171101.18-171101.100" + wire $or$libresoc.v:171101$11596_Y + attribute \src "libresoc.v:171104.17-171104.98" + wire $or$libresoc.v:171104$11599_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 1 \coresync_rst + attribute \src "libresoc.v:171063.7-171063.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 2 \q_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 4 \r_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 3 \s_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$libresoc.v:171098$11593 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:171098$11593_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:171103$11598 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:171103$11598_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:171100$11595 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rdok + connect \Y $not$libresoc.v:171100$11595_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:171102$11597 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rdok + connect \Y $not$libresoc.v:171102$11597_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:171105$11600 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rdok + connect \Y $not$libresoc.v:171105$11600_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:171099$11594 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_rdok + connect \Y $or$libresoc.v:171099$11594_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:171101$11596 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rdok + connect \B \q_int + connect \Y $or$libresoc.v:171101$11596_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:171104$11599 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_rdok + connect \Y $or$libresoc.v:171104$11599_Y + end + attribute \src "libresoc.v:171063.7-171063.20" + process $proc$libresoc.v:171063$11605 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:171085.7-171085.19" + process $proc$libresoc.v:171085$11606 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:171106.3-171107.27" + process $proc$libresoc.v:171106$11601 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:171108.3-171116.6" + process $proc$libresoc.v:171108$11602 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$11603 $1\q_int$next[0:0]$11604 + attribute \src "libresoc.v:171109.5-171109.29" + switch \initial + attribute \src "libresoc.v:171109.9-171109.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$11604 1'0 + case + assign $1\q_int$next[0:0]$11604 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$11603 + end + connect \$9 $and$libresoc.v:171098$11593_Y + connect \$11 $or$libresoc.v:171099$11594_Y + connect \$13 $not$libresoc.v:171100$11595_Y + connect \$15 $or$libresoc.v:171101$11596_Y + connect \$1 $not$libresoc.v:171102$11597_Y + connect \$3 $and$libresoc.v:171103$11598_Y + connect \$5 $or$libresoc.v:171104$11599_Y + connect \$7 $not$libresoc.v:171105$11600_Y + connect \qlq_rdok \$15 + connect \qn_rdok \$13 + connect \q_rdok \$11 +end +attribute \src "libresoc.v:171124.1-171182.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.rok_l" +attribute \generator "nMigen" +module \rok_l$85 + attribute \src "libresoc.v:171125.7-171125.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:171170.3-171178.6" + wire $0\q_int$next[0:0]$11617 + attribute \src "libresoc.v:171168.3-171169.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:171170.3-171178.6" + wire $1\q_int$next[0:0]$11618 + attribute \src "libresoc.v:171147.7-171147.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:171160.17-171160.96" + wire $and$libresoc.v:171160$11607_Y + attribute \src "libresoc.v:171165.17-171165.96" + wire $and$libresoc.v:171165$11612_Y + attribute \src "libresoc.v:171162.18-171162.94" + wire $not$libresoc.v:171162$11609_Y + attribute \src "libresoc.v:171164.17-171164.93" + wire $not$libresoc.v:171164$11611_Y + attribute \src "libresoc.v:171167.17-171167.93" + wire $not$libresoc.v:171167$11614_Y + attribute \src "libresoc.v:171161.18-171161.99" + wire $or$libresoc.v:171161$11608_Y + attribute \src "libresoc.v:171163.18-171163.100" + wire $or$libresoc.v:171163$11610_Y + attribute \src "libresoc.v:171166.17-171166.98" + wire $or$libresoc.v:171166$11613_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 1 \coresync_rst + attribute \src "libresoc.v:171125.7-171125.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 2 \q_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 4 \r_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 3 \s_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$libresoc.v:171160$11607 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:171160$11607_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:171165$11612 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:171165$11612_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:171162$11609 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rdok + connect \Y $not$libresoc.v:171162$11609_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:171164$11611 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rdok + connect \Y $not$libresoc.v:171164$11611_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:171167$11614 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rdok + connect \Y $not$libresoc.v:171167$11614_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:171161$11608 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_rdok + connect \Y $or$libresoc.v:171161$11608_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:171163$11610 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rdok + connect \B \q_int + connect \Y $or$libresoc.v:171163$11610_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:171166$11613 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_rdok + connect \Y $or$libresoc.v:171166$11613_Y + end + attribute \src "libresoc.v:171125.7-171125.20" + process $proc$libresoc.v:171125$11619 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:171147.7-171147.19" + process $proc$libresoc.v:171147$11620 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:171168.3-171169.27" + process $proc$libresoc.v:171168$11615 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:171170.3-171178.6" + process $proc$libresoc.v:171170$11616 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$11617 $1\q_int$next[0:0]$11618 + attribute \src "libresoc.v:171171.5-171171.29" + switch \initial + attribute \src "libresoc.v:171171.9-171171.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$11618 1'0 + case + assign $1\q_int$next[0:0]$11618 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$11617 + end + connect \$9 $and$libresoc.v:171160$11607_Y + connect \$11 $or$libresoc.v:171161$11608_Y + connect \$13 $not$libresoc.v:171162$11609_Y + connect \$15 $or$libresoc.v:171163$11610_Y + connect \$1 $not$libresoc.v:171164$11611_Y + connect \$3 $and$libresoc.v:171165$11612_Y + connect \$5 $or$libresoc.v:171166$11613_Y + connect \$7 $not$libresoc.v:171167$11614_Y + connect \qlq_rdok \$15 + connect \qn_rdok \$13 + connect \q_rdok \$11 +end +attribute \src "libresoc.v:171186.1-171537.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.pipe1.main.rotator" +attribute \generator "nMigen" +module \rotator + attribute \src "libresoc.v:171455.3-171464.6" + wire $0\carry_out_o[0:0] + attribute \src "libresoc.v:171387.3-171401.6" + wire width 32 $0\hi32[31:0] + attribute \src "libresoc.v:171187.7-171187.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:171477.3-171510.6" + wire width 7 $0\mb$8[6:0]$11668 + attribute \src "libresoc.v:171511.3-171525.6" + wire width 7 $0\me$13[6:0]$11673 + attribute \src "libresoc.v:171412.3-171423.6" + wire width 64 $0\mr[63:0] + attribute \src "libresoc.v:171424.3-171435.6" + wire width 2 $0\output_mode[1:0] + attribute \src "libresoc.v:171436.3-171454.6" + wire width 64 $0\result_o[63:0] + attribute \src "libresoc.v:171402.3-171411.6" + wire width 7 $0\right_mask_shift[6:0] + attribute \src "libresoc.v:171465.3-171476.6" + wire width 6 $0\rot_count[5:0] + attribute \src "libresoc.v:171455.3-171464.6" + wire $1\carry_out_o[0:0] + attribute \src "libresoc.v:171387.3-171401.6" + wire width 32 $1\hi32[31:0] + attribute \src "libresoc.v:171477.3-171510.6" + wire width 7 $1\mb$8[6:0]$11669 + attribute \src "libresoc.v:171511.3-171525.6" + wire width 7 $1\me$13[6:0]$11674 + attribute \src "libresoc.v:171412.3-171423.6" + wire width 64 $1\mr[63:0] + attribute \src "libresoc.v:171424.3-171435.6" + wire width 2 $1\output_mode[1:0] + attribute \src "libresoc.v:171436.3-171454.6" + wire width 64 $1\result_o[63:0] + attribute \src "libresoc.v:171402.3-171411.6" + wire width 7 $1\right_mask_shift[6:0] + attribute \src "libresoc.v:171465.3-171476.6" + wire width 6 $1\rot_count[5:0] + attribute \src "libresoc.v:171477.3-171510.6" + wire width 2 $2\mb$8[6:5]$11670 + attribute \src "libresoc.v:171477.3-171510.6" + wire width 2 $3\mb$8[6:5]$11671 + attribute \src "libresoc.v:171338.18-171338.118" + wire $and$libresoc.v:171338$11624_Y + attribute \src "libresoc.v:171340.18-171340.114" + wire $and$libresoc.v:171340$11626_Y + attribute \src "libresoc.v:171349.18-171349.113" + wire $and$libresoc.v:171349$11635_Y + attribute \src "libresoc.v:171351.18-171351.114" + wire $and$libresoc.v:171351$11637_Y + attribute \src "libresoc.v:171353.18-171353.114" + wire $and$libresoc.v:171353$11639_Y + attribute \src "libresoc.v:171354.18-171354.103" + wire width 64 $and$libresoc.v:171354$11640_Y + attribute \src "libresoc.v:171355.18-171355.106" + wire width 64 $and$libresoc.v:171355$11641_Y + attribute \src "libresoc.v:171357.18-171357.103" + wire width 64 $and$libresoc.v:171357$11643_Y + attribute \src "libresoc.v:171359.18-171359.105" + wire width 64 $and$libresoc.v:171359$11645_Y + attribute \src "libresoc.v:171362.18-171362.106" + wire width 64 $and$libresoc.v:171362$11648_Y + attribute \src "libresoc.v:171365.18-171365.105" + wire width 64 $and$libresoc.v:171365$11651_Y + attribute \src "libresoc.v:171367.17-171367.109" + wire $and$libresoc.v:171367$11653_Y + attribute \src "libresoc.v:171368.18-171368.104" + wire width 64 $and$libresoc.v:171368$11654_Y + attribute \src "libresoc.v:171372.18-171372.105" + wire width 64 $and$libresoc.v:171372$11658_Y + attribute \src "libresoc.v:171336.17-171336.98" + wire width 7 $extend$libresoc.v:171336$11621_Y + attribute \src "libresoc.v:171352.18-171352.122" + wire $gt$libresoc.v:171352$11638_Y + attribute \src "libresoc.v:171342.18-171342.111" + wire $le$libresoc.v:171342$11628_Y + attribute \src "libresoc.v:171344.18-171344.111" + wire $le$libresoc.v:171344$11630_Y + attribute \src "libresoc.v:171345.17-171345.117" + wire width 7 $neg$libresoc.v:171345$11631_Y + attribute \src "libresoc.v:171337.18-171337.103" + wire $not$libresoc.v:171337$11623_Y + attribute \src "libresoc.v:171339.18-171339.108" + wire $not$libresoc.v:171339$11625_Y + attribute \src "libresoc.v:171341.18-171341.105" + wire width 6 $not$libresoc.v:171341$11627_Y + attribute \src "libresoc.v:171347.18-171347.112" + wire width 64 $not$libresoc.v:171347$11633_Y + attribute \src "libresoc.v:171348.18-171348.109" + wire $not$libresoc.v:171348$11634_Y + attribute \src "libresoc.v:171356.17-171356.105" + wire $not$libresoc.v:171356$11642_Y + attribute \src "libresoc.v:171358.18-171358.102" + wire width 64 $not$libresoc.v:171358$11644_Y + attribute \src "libresoc.v:171364.18-171364.102" + wire width 64 $not$libresoc.v:171364$11650_Y + attribute \src "libresoc.v:171369.18-171369.100" + wire width 64 $not$libresoc.v:171369$11655_Y + attribute \src "libresoc.v:171371.18-171371.100" + wire width 64 $not$libresoc.v:171371$11657_Y + attribute \src "libresoc.v:171350.18-171350.115" + wire $or$libresoc.v:171350$11636_Y + attribute \src "libresoc.v:171360.18-171360.108" + wire width 64 $or$libresoc.v:171360$11646_Y + attribute \src "libresoc.v:171361.18-171361.103" + wire width 64 $or$libresoc.v:171361$11647_Y + attribute \src "libresoc.v:171363.18-171363.103" + wire width 64 $or$libresoc.v:171363$11649_Y + attribute \src "libresoc.v:171366.18-171366.108" + wire width 64 $or$libresoc.v:171366$11652_Y + attribute \src "libresoc.v:171370.18-171370.106" + wire width 64 $or$libresoc.v:171370$11656_Y + attribute \src "libresoc.v:171336.17-171336.98" + wire width 7 $pos$libresoc.v:171336$11622_Y + attribute \src "libresoc.v:171373.18-171373.102" + wire $reduce_or$libresoc.v:171373$11659_Y + attribute \src "libresoc.v:171343.18-171343.109" + wire width 8 $sub$libresoc.v:171343$11629_Y + attribute \src "libresoc.v:171346.18-171346.110" + wire width 8 $sub$libresoc.v:171346$11632_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:99" + wire width 7 \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:126" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:131" + wire \$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:134" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:134" + wire \$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:99" + wire width 7 \$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:139" + wire width 6 \$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:143" + wire \$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:144" + wire width 8 \$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:144" + wire width 8 \$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:143" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:151" + wire width 8 \$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:151" + wire width 8 \$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:152" + wire width 64 \$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:161" + wire \$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:161" + wire \$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:161" + wire \$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:110" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:162" + wire \$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:164" + wire \$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:164" + wire \$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170" + wire width 64 \$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170" + wire width 64 \$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170" + wire width 64 \$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170" + wire width 64 \$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170" + wire width 64 \$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170" + wire width 64 \$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172" + wire width 64 \$58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:110" + wire \$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172" + wire width 64 \$60 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172" + wire width 64 \$62 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172" + wire width 64 \$63 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172" + wire width 64 \$66 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172" + wire width 64 \$68 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:174" + wire width 64 \$70 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:176" + wire width 64 \$72 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:176" + wire width 64 \$74 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:178" + wire \$76 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:178" + wire width 64 \$77 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:178" + wire width 64 \$79 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:51" + wire width 7 \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:59" + wire input 7 \arith + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:65" + wire output 13 \carry_out_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:60" + wire input 9 \clear_left + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:61" + wire input 10 \clear_right + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:81" + wire width 32 \hi32 + attribute \src "libresoc.v:171187.7-171187.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:57" + wire input 6 \is_32bit + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:12" + wire width 64 \left_mask_mask + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:11" + wire width 7 \left_mask_shift + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:51" + wire width 5 input 1 \mb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:76" + wire width 7 \mb$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:53" + wire input 2 \mb_extra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:50" + wire width 5 input 14 \me + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:77" + wire width 7 \me$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:79" + wire width 64 \ml + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:78" + wire width 64 \mr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:80" + wire width 2 \output_mode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:54" + wire width 64 input 4 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:82" + wire width 64 \repl32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:64" + wire width 64 output 12 \result_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:12" + wire width 64 \right_mask_mask + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:11" + wire width 7 \right_mask_shift + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:58" + wire input 8 \right_shift + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:74" + wire width 64 \rot + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:73" + wire width 6 \rot_count + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:8" + wire width 64 \rotl_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:9" + wire width 6 \rotl_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:11" + wire width 64 \rotl_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:55" + wire width 64 input 3 \rs + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:75" + wire width 7 \sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:56" + wire width 7 input 5 \shift + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:94" + wire width 6 \shift_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:62" + wire input 11 \sign_ext_rs + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:131" + cell $and $and$libresoc.v:171338$11624 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \clear_right + connect \B \is_32bit + connect \Y $and$libresoc.v:171338$11624_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:134" + cell $and $and$libresoc.v:171340$11626 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \clear_right + connect \B \$16 + connect \Y $and$libresoc.v:171340$11626_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:161" + cell $and $and$libresoc.v:171349$11635 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \clear_left + connect \B \$34 + connect \Y $and$libresoc.v:171349$11635_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:162" + cell $and $and$libresoc.v:171351$11637 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \arith + connect \B \repl32 [63] + connect \Y $and$libresoc.v:171351$11637_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:164" + cell $and $and$libresoc.v:171353$11639 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \clear_right + connect \B \$42 + connect \Y $and$libresoc.v:171353$11639_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170" + cell $and $and$libresoc.v:171354$11640 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \mr + connect \B \ml + connect \Y $and$libresoc.v:171354$11640_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170" + cell $and $and$libresoc.v:171355$11641 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \rot + connect \B \$46 + connect \Y $and$libresoc.v:171355$11641_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170" + cell $and $and$libresoc.v:171357$11643 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \mr + connect \B \ml + connect \Y $and$libresoc.v:171357$11643_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170" + cell $and $and$libresoc.v:171359$11645 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \ra + connect \B \$50 + connect \Y $and$libresoc.v:171359$11645_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172" + cell $and $and$libresoc.v:171362$11648 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \rot + connect \B \$58 + connect \Y $and$libresoc.v:171362$11648_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172" + cell $and $and$libresoc.v:171365$11651 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \ra + connect \B \$62 + connect \Y $and$libresoc.v:171365$11651_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:110" + cell $and $and$libresoc.v:171367$11653 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \shift [6] + connect \B \$4 + connect \Y $and$libresoc.v:171367$11653_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:174" + cell $and $and$libresoc.v:171368$11654 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \rot + connect \B \mr + connect \Y $and$libresoc.v:171368$11654_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:178" + cell $and $and$libresoc.v:171372$11658 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \rs + connect \B \$77 + connect \Y $and$libresoc.v:171372$11658_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:51" + cell $pos $extend$libresoc.v:171336$11621 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 7 + connect \A \mb + connect \Y $extend$libresoc.v:171336$11621_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:164" + cell $gt $gt$libresoc.v:171352$11638 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \mb$8 [5:0] + connect \B \me$13 [5:0] + connect \Y $gt$libresoc.v:171352$11638_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:143" + cell $le $le$libresoc.v:171342$11628 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \mb$8 + connect \B 7'1000000 + connect \Y $le$libresoc.v:171342$11628_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:143" + cell $le $le$libresoc.v:171344$11630 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \mb$8 + connect \B 7'1000000 + connect \Y $le$libresoc.v:171344$11630_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:99" + cell $neg $neg$libresoc.v:171345$11631 + parameter \A_SIGNED 1 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 7 + connect \A { \shift_signed [5] \shift_signed } + connect \Y $neg$libresoc.v:171345$11631_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:126" + cell $not $not$libresoc.v:171337$11623 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \sh [5] + connect \Y $not$libresoc.v:171337$11623_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:134" + cell $not $not$libresoc.v:171339$11625 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \clear_left + connect \Y $not$libresoc.v:171339$11625_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:139" + cell $not $not$libresoc.v:171341$11627 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \sh [5:0] + connect \Y $not$libresoc.v:171341$11627_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:152" + cell $not $not$libresoc.v:171347$11633 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \left_mask_mask + connect \Y $not$libresoc.v:171347$11633_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:161" + cell $not $not$libresoc.v:171348$11634 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \clear_right + connect \Y $not$libresoc.v:171348$11634_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:110" + cell $not $not$libresoc.v:171356$11642 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_32bit + connect \Y $not$libresoc.v:171356$11642_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170" + cell $not $not$libresoc.v:171358$11644 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \$51 + connect \Y $not$libresoc.v:171358$11644_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172" + cell $not $not$libresoc.v:171364$11650 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \$63 + connect \Y $not$libresoc.v:171364$11650_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:176" + cell $not $not$libresoc.v:171369$11655 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \mr + connect \Y $not$libresoc.v:171369$11655_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:178" + cell $not $not$libresoc.v:171371$11657 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \ml + connect \Y $not$libresoc.v:171371$11657_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:161" + cell $or $or$libresoc.v:171350$11636 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$36 + connect \B \right_shift + connect \Y $or$libresoc.v:171350$11636_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170" + cell $or $or$libresoc.v:171360$11646 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \$48 + connect \B \$54 + connect \Y $or$libresoc.v:171360$11646_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172" + cell $or $or$libresoc.v:171361$11647 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \mr + connect \B \ml + connect \Y $or$libresoc.v:171361$11647_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172" + cell $or $or$libresoc.v:171363$11649 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \mr + connect \B \ml + connect \Y $or$libresoc.v:171363$11649_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172" + cell $or $or$libresoc.v:171366$11652 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \$60 + connect \B \$66 + connect \Y $or$libresoc.v:171366$11652_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:176" + cell $or $or$libresoc.v:171370$11656 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \rot + connect \B \$72 + connect \Y $or$libresoc.v:171370$11656_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:51" + cell $pos $pos$libresoc.v:171336$11622 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 7 + connect \A $extend$libresoc.v:171336$11621_Y + connect \Y $pos$libresoc.v:171336$11622_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:178" + cell $reduce_or $reduce_or$libresoc.v:171373$11659 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 1 + connect \A \$79 + connect \Y $reduce_or$libresoc.v:171373$11659_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:144" + cell $sub $sub$libresoc.v:171343$11629 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 8 + connect \A 7'1000000 + connect \B \mb$8 + connect \Y $sub$libresoc.v:171343$11629_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:151" + cell $sub $sub$libresoc.v:171346$11632 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 8 + connect \A 6'111111 + connect \B \me$13 + connect \Y $sub$libresoc.v:171346$11632_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:171374.13-171377.4" + cell \left_mask \left_mask + connect \mask \left_mask_mask + connect \shift \left_mask_shift + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:171378.14-171381.4" + cell \right_mask \right_mask + connect \mask \right_mask_mask + connect \shift \right_mask_shift + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:171382.8-171386.4" + cell \rotl \rotl + connect \a \rotl_a + connect \b \rotl_b + connect \o \rotl_o + end + attribute \src "libresoc.v:171187.7-171187.20" + process $proc$libresoc.v:171187$11675 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:171387.3-171401.6" + process $proc$libresoc.v:171387$11660 + assign { } { } + assign $0\hi32[31:0] $1\hi32[31:0] + attribute \src "libresoc.v:171388.5-171388.29" + switch \initial + attribute \src "libresoc.v:171388.9-171388.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:85" + switch { \sign_ext_rs \is_32bit } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\hi32[31:0] \rs [31:0] + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\hi32[31:0] { \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] } + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\hi32[31:0] \rs [63:32] + end + sync always + update \hi32 $0\hi32[31:0] + end + attribute \src "libresoc.v:171402.3-171411.6" + process $proc$libresoc.v:171402$11661 + assign { } { } + assign { } { } + assign $0\right_mask_shift[6:0] $1\right_mask_shift[6:0] + attribute \src "libresoc.v:171403.5-171403.29" + switch \initial + attribute \src "libresoc.v:171403.9-171403.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:143" + switch \$22 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\right_mask_shift[6:0] \$24 [6:0] + case + assign $1\right_mask_shift[6:0] 7'0000000 + end + sync always + update \right_mask_shift $0\right_mask_shift[6:0] + end + attribute \src "libresoc.v:171412.3-171423.6" + process $proc$libresoc.v:171412$11662 + assign { } { } + assign $0\mr[63:0] $1\mr[63:0] + attribute \src "libresoc.v:171413.5-171413.29" + switch \initial + attribute \src "libresoc.v:171413.9-171413.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:143" + switch \$27 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\mr[63:0] \right_mask_mask + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\mr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \mr $0\mr[63:0] + end + attribute \src "libresoc.v:171424.3-171435.6" + process $proc$libresoc.v:171424$11663 + assign { } { } + assign $0\output_mode[1:0] $1\output_mode[1:0] + attribute \src "libresoc.v:171425.5-171425.29" + switch \initial + attribute \src "libresoc.v:171425.9-171425.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:161" + switch \$38 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\output_mode[1:0] { 1'1 \$40 } + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\output_mode[1:0] { 1'0 \$44 } + end + sync always + update \output_mode $0\output_mode[1:0] + end + attribute \src "libresoc.v:171436.3-171454.6" + process $proc$libresoc.v:171436$11664 + assign { } { } + assign { } { } + assign $0\result_o[63:0] $1\result_o[63:0] + attribute \src "libresoc.v:171437.5-171437.29" + switch \initial + attribute \src "libresoc.v:171437.9-171437.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:168" + switch \output_mode + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\result_o[63:0] \$56 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\result_o[63:0] \$68 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\result_o[63:0] \$70 + attribute \src "libresoc.v:0.0-0.0" + case 2'11 + assign { } { } + assign $1\result_o[63:0] \$74 + case + assign $1\result_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \result_o $0\result_o[63:0] + end + attribute \src "libresoc.v:171455.3-171464.6" + process $proc$libresoc.v:171455$11665 + assign { } { } + assign { } { } + assign $0\carry_out_o[0:0] $1\carry_out_o[0:0] + attribute \src "libresoc.v:171456.5-171456.29" + switch \initial + attribute \src "libresoc.v:171456.9-171456.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:168" + switch \output_mode + attribute \src "libresoc.v:0.0-0.0" + case 2'11 + assign { } { } + assign $1\carry_out_o[0:0] \$76 + case + assign $1\carry_out_o[0:0] 1'0 + end + sync always + update \carry_out_o $0\carry_out_o[0:0] + end + attribute \src "libresoc.v:171465.3-171476.6" + process $proc$libresoc.v:171465$11666 + assign { } { } + assign $0\rot_count[5:0] $1\rot_count[5:0] + attribute \src "libresoc.v:171466.5-171466.29" + switch \initial + attribute \src "libresoc.v:171466.9-171466.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:98" + switch \right_shift + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rot_count[5:0] \$1 [5:0] + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\rot_count[5:0] \shift [5:0] + end + sync always + update \rot_count $0\rot_count[5:0] + end + attribute \src "libresoc.v:171477.3-171510.6" + process $proc$libresoc.v:171477$11667 + assign { } { } + assign $0\mb$8[6:0]$11668 $1\mb$8[6:0]$11669 + attribute \src "libresoc.v:171478.5-171478.29" + switch \initial + attribute \src "libresoc.v:171478.9-171478.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:116" + switch { \right_shift \clear_left } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\mb$8[6:0]$11669 [4:0] \$9 [4:0] + assign $1\mb$8[6:0]$11669 [6:5] $2\mb$8[6:5]$11670 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:118" + switch \is_32bit + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\mb$8[6:5]$11670 2'01 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\mb$8[6:5]$11670 { 1'0 \mb_extra } + end + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\mb$8[6:0]$11669 [4:0] \sh [4:0] + assign $1\mb$8[6:0]$11669 [6:5] $3\mb$8[6:5]$11671 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:125" + switch \is_32bit + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\mb$8[6:5]$11671 { \sh [5] \$11 } + case + assign $3\mb$8[6:5]$11671 \sh [6:5] + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\mb$8[6:0]$11669 { 1'0 \is_32bit 5'00000 } + end + sync always + update \mb$8 $0\mb$8[6:0]$11668 + end + attribute \src "libresoc.v:171511.3-171525.6" + process $proc$libresoc.v:171511$11672 + assign { } { } + assign $0\me$13[6:0]$11673 $1\me$13[6:0]$11674 + attribute \src "libresoc.v:171512.5-171512.29" + switch \initial + attribute \src "libresoc.v:171512.9-171512.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:131" + switch { \$18 \$14 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\me$13[6:0]$11674 { 2'01 \me } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\me$13[6:0]$11674 { 1'0 \mb_extra \mb } + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\me$13[6:0]$11674 { \sh [6] \$20 } + end + sync always + update \me$13 $0\me$13[6:0]$11673 + end + connect \$9 $pos$libresoc.v:171336$11622_Y + connect \$11 $not$libresoc.v:171337$11623_Y + connect \$14 $and$libresoc.v:171338$11624_Y + connect \$16 $not$libresoc.v:171339$11625_Y + connect \$18 $and$libresoc.v:171340$11626_Y + connect \$20 $not$libresoc.v:171341$11627_Y + connect \$22 $le$libresoc.v:171342$11628_Y + connect \$25 $sub$libresoc.v:171343$11629_Y + connect \$27 $le$libresoc.v:171344$11630_Y + connect \$2 $neg$libresoc.v:171345$11631_Y + connect \$30 $sub$libresoc.v:171346$11632_Y + connect \$32 $not$libresoc.v:171347$11633_Y + connect \$34 $not$libresoc.v:171348$11634_Y + connect \$36 $and$libresoc.v:171349$11635_Y + connect \$38 $or$libresoc.v:171350$11636_Y + connect \$40 $and$libresoc.v:171351$11637_Y + connect \$42 $gt$libresoc.v:171352$11638_Y + connect \$44 $and$libresoc.v:171353$11639_Y + connect \$46 $and$libresoc.v:171354$11640_Y + connect \$48 $and$libresoc.v:171355$11641_Y + connect \$4 $not$libresoc.v:171356$11642_Y + connect \$51 $and$libresoc.v:171357$11643_Y + connect \$50 $not$libresoc.v:171358$11644_Y + connect \$54 $and$libresoc.v:171359$11645_Y + connect \$56 $or$libresoc.v:171360$11646_Y + connect \$58 $or$libresoc.v:171361$11647_Y + connect \$60 $and$libresoc.v:171362$11648_Y + connect \$63 $or$libresoc.v:171363$11649_Y + connect \$62 $not$libresoc.v:171364$11650_Y + connect \$66 $and$libresoc.v:171365$11651_Y + connect \$68 $or$libresoc.v:171366$11652_Y + connect \$6 $and$libresoc.v:171367$11653_Y + connect \$70 $and$libresoc.v:171368$11654_Y + connect \$72 $not$libresoc.v:171369$11655_Y + connect \$74 $or$libresoc.v:171370$11656_Y + connect \$77 $not$libresoc.v:171371$11657_Y + connect \$79 $and$libresoc.v:171372$11658_Y + connect \$76 $reduce_or$libresoc.v:171373$11659_Y + connect \$1 \$2 + connect \$24 \$25 + connect \$29 \$30 + connect \ml \$32 + connect \left_mask_shift \$30 [6:0] + connect \sh { \$6 \shift [5:0] } + connect \rot \rotl_o + connect \rotl_b \rot_count + connect \rotl_a \repl32 + connect \shift_signed \shift [5:0] + connect \repl32 { \hi32 \rs [31:0] } +end +attribute \src "libresoc.v:171541.1-171555.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.pipe1.main.rotator.rotl" +attribute \generator "nMigen" +module \rotl + attribute \src "libresoc.v:171553.17-171553.32" + wire width 128 $shr$libresoc.v:171553$11677_Y + attribute \src "libresoc.v:171552.17-171552.100" + wire width 8 $sub$libresoc.v:171552$11676_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:19" + wire width 64 \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:18" + wire width 8 \$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:8" + wire width 64 input 3 \a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:9" + wire width 6 input 1 \b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:11" + wire width 64 output 2 \o + attribute \src "libresoc.v:171553.17-171553.32" + cell $shr $shr$libresoc.v:171553$11677 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 128 + connect \A { \a \a } + connect \B \$2 + connect \Y $shr$libresoc.v:171553$11677_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:18" + cell $sub $sub$libresoc.v:171552$11676 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 8 + connect \A 7'1000000 + connect \B \b + connect \Y $sub$libresoc.v:171552$11676_Y + end + connect \$2 $sub$libresoc.v:171552$11676_Y + connect \$1 $shr$libresoc.v:171553$11677_Y [63:0] + connect \o \$1 +end +attribute \src "libresoc.v:171559.1-171617.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.rst_l" +attribute \generator "nMigen" +module \rst_l + attribute \src "libresoc.v:171560.7-171560.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:171605.3-171613.6" + wire $0\q_int$next[0:0]$11688 + attribute \src "libresoc.v:171603.3-171604.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:171605.3-171613.6" + wire $1\q_int$next[0:0]$11689 + attribute \src "libresoc.v:171582.7-171582.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:171595.17-171595.96" + wire $and$libresoc.v:171595$11678_Y + attribute \src "libresoc.v:171600.17-171600.96" + wire $and$libresoc.v:171600$11683_Y + attribute \src "libresoc.v:171597.18-171597.93" + wire $not$libresoc.v:171597$11680_Y + attribute \src "libresoc.v:171599.17-171599.92" + wire $not$libresoc.v:171599$11682_Y + attribute \src "libresoc.v:171602.17-171602.92" + wire $not$libresoc.v:171602$11685_Y + attribute \src "libresoc.v:171596.18-171596.98" + wire $or$libresoc.v:171596$11679_Y + attribute \src "libresoc.v:171598.18-171598.99" + wire $or$libresoc.v:171598$11681_Y + attribute \src "libresoc.v:171601.17-171601.97" + wire $or$libresoc.v:171601$11684_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 4 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 1 \coresync_rst + attribute \src "libresoc.v:171560.7-171560.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire \q_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 2 \s_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$libresoc.v:171595$11678 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:171595$11678_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:171600$11683 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:171600$11683_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:171597$11680 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rst + connect \Y $not$libresoc.v:171597$11680_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:171599$11682 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rst + connect \Y $not$libresoc.v:171599$11682_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:171602$11685 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rst + connect \Y $not$libresoc.v:171602$11685_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:171596$11679 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_rst + connect \Y $or$libresoc.v:171596$11679_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:171598$11681 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rst + connect \B \q_int + connect \Y $or$libresoc.v:171598$11681_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:171601$11684 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_rst + connect \Y $or$libresoc.v:171601$11684_Y + end + attribute \src "libresoc.v:171560.7-171560.20" + process $proc$libresoc.v:171560$11690 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:171582.7-171582.19" + process $proc$libresoc.v:171582$11691 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:171603.3-171604.27" + process $proc$libresoc.v:171603$11686 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:171605.3-171613.6" + process $proc$libresoc.v:171605$11687 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$11688 $1\q_int$next[0:0]$11689 + attribute \src "libresoc.v:171606.5-171606.29" + switch \initial + attribute \src "libresoc.v:171606.9-171606.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$11689 1'0 + case + assign $1\q_int$next[0:0]$11689 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$11688 + end + connect \$9 $and$libresoc.v:171595$11678_Y + connect \$11 $or$libresoc.v:171596$11679_Y + connect \$13 $not$libresoc.v:171597$11680_Y + connect \$15 $or$libresoc.v:171598$11681_Y + connect \$1 $not$libresoc.v:171599$11682_Y + connect \$3 $and$libresoc.v:171600$11683_Y + connect \$5 $or$libresoc.v:171601$11684_Y + connect \$7 $not$libresoc.v:171602$11685_Y + connect \qlq_rst \$15 + connect \qn_rst \$13 + connect \q_rst \$11 +end +attribute \src "libresoc.v:171621.1-171679.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.rst_l" +attribute \generator "nMigen" +module \rst_l$101 + attribute \src "libresoc.v:171622.7-171622.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:171667.3-171675.6" + wire $0\q_int$next[0:0]$11702 + attribute \src "libresoc.v:171665.3-171666.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:171667.3-171675.6" + wire $1\q_int$next[0:0]$11703 + attribute \src "libresoc.v:171644.7-171644.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:171657.17-171657.96" + wire $and$libresoc.v:171657$11692_Y + attribute \src "libresoc.v:171662.17-171662.96" + wire $and$libresoc.v:171662$11697_Y + attribute \src "libresoc.v:171659.18-171659.93" + wire $not$libresoc.v:171659$11694_Y + attribute \src "libresoc.v:171661.17-171661.92" + wire $not$libresoc.v:171661$11696_Y + attribute \src "libresoc.v:171664.17-171664.92" + wire $not$libresoc.v:171664$11699_Y + attribute \src "libresoc.v:171658.18-171658.98" + wire $or$libresoc.v:171658$11693_Y + attribute \src "libresoc.v:171660.18-171660.99" + wire $or$libresoc.v:171660$11695_Y + attribute \src "libresoc.v:171663.17-171663.97" + wire $or$libresoc.v:171663$11698_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 4 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 1 \coresync_rst + attribute \src "libresoc.v:171622.7-171622.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire \q_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 2 \s_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$libresoc.v:171657$11692 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:171657$11692_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:171662$11697 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:171662$11697_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:171659$11694 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rst + connect \Y $not$libresoc.v:171659$11694_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:171661$11696 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rst + connect \Y $not$libresoc.v:171661$11696_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:171664$11699 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rst + connect \Y $not$libresoc.v:171664$11699_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:171658$11693 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_rst + connect \Y $or$libresoc.v:171658$11693_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:171660$11695 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rst + connect \B \q_int + connect \Y $or$libresoc.v:171660$11695_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:171663$11698 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_rst + connect \Y $or$libresoc.v:171663$11698_Y + end + attribute \src "libresoc.v:171622.7-171622.20" + process $proc$libresoc.v:171622$11704 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:171644.7-171644.19" + process $proc$libresoc.v:171644$11705 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:171665.3-171666.27" + process $proc$libresoc.v:171665$11700 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:171667.3-171675.6" + process $proc$libresoc.v:171667$11701 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$11702 $1\q_int$next[0:0]$11703 + attribute \src "libresoc.v:171668.5-171668.29" + switch \initial + attribute \src "libresoc.v:171668.9-171668.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$11703 1'0 + case + assign $1\q_int$next[0:0]$11703 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$11702 + end + connect \$9 $and$libresoc.v:171657$11692_Y + connect \$11 $or$libresoc.v:171658$11693_Y + connect \$13 $not$libresoc.v:171659$11694_Y + connect \$15 $or$libresoc.v:171660$11695_Y + connect \$1 $not$libresoc.v:171661$11696_Y + connect \$3 $and$libresoc.v:171662$11697_Y + connect \$5 $or$libresoc.v:171663$11698_Y + connect \$7 $not$libresoc.v:171664$11699_Y + connect \qlq_rst \$15 + connect \qn_rst \$13 + connect \q_rst \$11 +end +attribute \src "libresoc.v:171683.1-171741.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.rst_l" +attribute \generator "nMigen" +module \rst_l$119 + attribute \src "libresoc.v:171684.7-171684.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:171729.3-171737.6" + wire $0\q_int$next[0:0]$11716 + attribute \src "libresoc.v:171727.3-171728.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:171729.3-171737.6" + wire $1\q_int$next[0:0]$11717 + attribute \src "libresoc.v:171706.7-171706.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:171719.17-171719.96" + wire $and$libresoc.v:171719$11706_Y + attribute \src "libresoc.v:171724.17-171724.96" + wire $and$libresoc.v:171724$11711_Y + attribute \src "libresoc.v:171721.18-171721.93" + wire $not$libresoc.v:171721$11708_Y + attribute \src "libresoc.v:171723.17-171723.92" + wire $not$libresoc.v:171723$11710_Y + attribute \src "libresoc.v:171726.17-171726.92" + wire $not$libresoc.v:171726$11713_Y + attribute \src "libresoc.v:171720.18-171720.98" + wire $or$libresoc.v:171720$11707_Y + attribute \src "libresoc.v:171722.18-171722.99" + wire $or$libresoc.v:171722$11709_Y + attribute \src "libresoc.v:171725.17-171725.97" + wire $or$libresoc.v:171725$11712_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 4 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 1 \coresync_rst + attribute \src "libresoc.v:171684.7-171684.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire \q_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 2 \s_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$libresoc.v:171719$11706 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:171719$11706_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:171724$11711 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:171724$11711_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:171721$11708 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rst + connect \Y $not$libresoc.v:171721$11708_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:171723$11710 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rst + connect \Y $not$libresoc.v:171723$11710_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:171726$11713 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rst + connect \Y $not$libresoc.v:171726$11713_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:171720$11707 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_rst + connect \Y $or$libresoc.v:171720$11707_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:171722$11709 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rst + connect \B \q_int + connect \Y $or$libresoc.v:171722$11709_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:171725$11712 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_rst + connect \Y $or$libresoc.v:171725$11712_Y + end + attribute \src "libresoc.v:171684.7-171684.20" + process $proc$libresoc.v:171684$11718 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:171706.7-171706.19" + process $proc$libresoc.v:171706$11719 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:171727.3-171728.27" + process $proc$libresoc.v:171727$11714 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:171729.3-171737.6" + process $proc$libresoc.v:171729$11715 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$11716 $1\q_int$next[0:0]$11717 + attribute \src "libresoc.v:171730.5-171730.29" + switch \initial + attribute \src "libresoc.v:171730.9-171730.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$11717 1'0 + case + assign $1\q_int$next[0:0]$11717 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$11716 + end + connect \$9 $and$libresoc.v:171719$11706_Y + connect \$11 $or$libresoc.v:171720$11707_Y + connect \$13 $not$libresoc.v:171721$11708_Y + connect \$15 $or$libresoc.v:171722$11709_Y + connect \$1 $not$libresoc.v:171723$11710_Y + connect \$3 $and$libresoc.v:171724$11711_Y + connect \$5 $or$libresoc.v:171725$11712_Y + connect \$7 $not$libresoc.v:171726$11713_Y + connect \qlq_rst \$15 + connect \qn_rst \$13 + connect \q_rst \$11 +end +attribute \src "libresoc.v:171745.1-171803.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.rst_l" +attribute \generator "nMigen" +module \rst_l$126 + attribute \src "libresoc.v:171746.7-171746.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:171791.3-171799.6" + wire $0\q_int$next[0:0]$11730 + attribute \src "libresoc.v:171789.3-171790.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:171791.3-171799.6" + wire $1\q_int$next[0:0]$11731 + attribute \src "libresoc.v:171768.7-171768.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:171781.17-171781.96" + wire $and$libresoc.v:171781$11720_Y + attribute \src "libresoc.v:171786.17-171786.96" + wire $and$libresoc.v:171786$11725_Y + attribute \src "libresoc.v:171783.18-171783.93" + wire $not$libresoc.v:171783$11722_Y + attribute \src "libresoc.v:171785.17-171785.92" + wire $not$libresoc.v:171785$11724_Y + attribute \src "libresoc.v:171788.17-171788.92" + wire $not$libresoc.v:171788$11727_Y + attribute \src "libresoc.v:171782.18-171782.98" + wire $or$libresoc.v:171782$11721_Y + attribute \src "libresoc.v:171784.18-171784.99" + wire $or$libresoc.v:171784$11723_Y + attribute \src "libresoc.v:171787.17-171787.97" + wire $or$libresoc.v:171787$11726_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 1 \coresync_rst + attribute \src "libresoc.v:171746.7-171746.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 4 \q_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 2 \s_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$libresoc.v:171781$11720 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:171781$11720_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:171786$11725 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:171786$11725_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:171783$11722 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rst + connect \Y $not$libresoc.v:171783$11722_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:171785$11724 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rst + connect \Y $not$libresoc.v:171785$11724_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:171788$11727 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rst + connect \Y $not$libresoc.v:171788$11727_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:171782$11721 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_rst + connect \Y $or$libresoc.v:171782$11721_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:171784$11723 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rst + connect \B \q_int + connect \Y $or$libresoc.v:171784$11723_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:171787$11726 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_rst + connect \Y $or$libresoc.v:171787$11726_Y + end + attribute \src "libresoc.v:171746.7-171746.20" + process $proc$libresoc.v:171746$11732 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:171768.7-171768.19" + process $proc$libresoc.v:171768$11733 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:171789.3-171790.27" + process $proc$libresoc.v:171789$11728 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:171791.3-171799.6" + process $proc$libresoc.v:171791$11729 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$11730 $1\q_int$next[0:0]$11731 + attribute \src "libresoc.v:171792.5-171792.29" + switch \initial + attribute \src "libresoc.v:171792.9-171792.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$11731 1'0 + case + assign $1\q_int$next[0:0]$11731 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$11730 + end + connect \$9 $and$libresoc.v:171781$11720_Y + connect \$11 $or$libresoc.v:171782$11721_Y + connect \$13 $not$libresoc.v:171783$11722_Y + connect \$15 $or$libresoc.v:171784$11723_Y + connect \$1 $not$libresoc.v:171785$11724_Y + connect \$3 $and$libresoc.v:171786$11725_Y + connect \$5 $or$libresoc.v:171787$11726_Y + connect \$7 $not$libresoc.v:171788$11727_Y + connect \qlq_rst \$15 + connect \qn_rst \$13 + connect \q_rst \$11 +end +attribute \src "libresoc.v:171807.1-171865.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.rst_l" +attribute \generator "nMigen" +module \rst_l$13 + attribute \src "libresoc.v:171808.7-171808.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:171853.3-171861.6" + wire $0\q_int$next[0:0]$11744 + attribute \src "libresoc.v:171851.3-171852.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:171853.3-171861.6" + wire $1\q_int$next[0:0]$11745 + attribute \src "libresoc.v:171830.7-171830.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:171843.17-171843.96" + wire $and$libresoc.v:171843$11734_Y + attribute \src "libresoc.v:171848.17-171848.96" + wire $and$libresoc.v:171848$11739_Y + attribute \src "libresoc.v:171845.18-171845.93" + wire $not$libresoc.v:171845$11736_Y + attribute \src "libresoc.v:171847.17-171847.92" + wire $not$libresoc.v:171847$11738_Y + attribute \src "libresoc.v:171850.17-171850.92" + wire $not$libresoc.v:171850$11741_Y + attribute \src "libresoc.v:171844.18-171844.98" + wire $or$libresoc.v:171844$11735_Y + attribute \src "libresoc.v:171846.18-171846.99" + wire $or$libresoc.v:171846$11737_Y + attribute \src "libresoc.v:171849.17-171849.97" + wire $or$libresoc.v:171849$11740_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 4 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 1 \coresync_rst + attribute \src "libresoc.v:171808.7-171808.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire \q_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 2 \s_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$libresoc.v:171843$11734 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:171843$11734_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:171848$11739 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:171848$11739_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:171845$11736 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rst + connect \Y $not$libresoc.v:171845$11736_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:171847$11738 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rst + connect \Y $not$libresoc.v:171847$11738_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:171850$11741 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rst + connect \Y $not$libresoc.v:171850$11741_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:171844$11735 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_rst + connect \Y $or$libresoc.v:171844$11735_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:171846$11737 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rst + connect \B \q_int + connect \Y $or$libresoc.v:171846$11737_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:171849$11740 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_rst + connect \Y $or$libresoc.v:171849$11740_Y + end + attribute \src "libresoc.v:171808.7-171808.20" + process $proc$libresoc.v:171808$11746 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:171830.7-171830.19" + process $proc$libresoc.v:171830$11747 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:171851.3-171852.27" + process $proc$libresoc.v:171851$11742 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:171853.3-171861.6" + process $proc$libresoc.v:171853$11743 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$11744 $1\q_int$next[0:0]$11745 + attribute \src "libresoc.v:171854.5-171854.29" + switch \initial + attribute \src "libresoc.v:171854.9-171854.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$11745 1'0 + case + assign $1\q_int$next[0:0]$11745 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$11744 + end + connect \$9 $and$libresoc.v:171843$11734_Y + connect \$11 $or$libresoc.v:171844$11735_Y + connect \$13 $not$libresoc.v:171845$11736_Y + connect \$15 $or$libresoc.v:171846$11737_Y + connect \$1 $not$libresoc.v:171847$11738_Y + connect \$3 $and$libresoc.v:171848$11739_Y + connect \$5 $or$libresoc.v:171849$11740_Y + connect \$7 $not$libresoc.v:171850$11741_Y + connect \qlq_rst \$15 + connect \qn_rst \$13 + connect \q_rst \$11 +end +attribute \src "libresoc.v:171869.1-171927.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.rst_l" +attribute \generator "nMigen" +module \rst_l$26 + attribute \src "libresoc.v:171870.7-171870.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:171915.3-171923.6" + wire $0\q_int$next[0:0]$11758 + attribute \src "libresoc.v:171913.3-171914.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:171915.3-171923.6" + wire $1\q_int$next[0:0]$11759 + attribute \src "libresoc.v:171892.7-171892.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:171905.17-171905.96" + wire $and$libresoc.v:171905$11748_Y + attribute \src "libresoc.v:171910.17-171910.96" + wire $and$libresoc.v:171910$11753_Y + attribute \src "libresoc.v:171907.18-171907.93" + wire $not$libresoc.v:171907$11750_Y + attribute \src "libresoc.v:171909.17-171909.92" + wire $not$libresoc.v:171909$11752_Y + attribute \src "libresoc.v:171912.17-171912.92" + wire $not$libresoc.v:171912$11755_Y + attribute \src "libresoc.v:171906.18-171906.98" + wire $or$libresoc.v:171906$11749_Y + attribute \src "libresoc.v:171908.18-171908.99" + wire $or$libresoc.v:171908$11751_Y + attribute \src "libresoc.v:171911.17-171911.97" + wire $or$libresoc.v:171911$11754_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 4 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 1 \coresync_rst + attribute \src "libresoc.v:171870.7-171870.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire \q_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 2 \s_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$libresoc.v:171905$11748 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:171905$11748_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:171910$11753 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:171910$11753_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:171907$11750 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rst + connect \Y $not$libresoc.v:171907$11750_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:171909$11752 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rst + connect \Y $not$libresoc.v:171909$11752_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:171912$11755 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rst + connect \Y $not$libresoc.v:171912$11755_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:171906$11749 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_rst + connect \Y $or$libresoc.v:171906$11749_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:171908$11751 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rst + connect \B \q_int + connect \Y $or$libresoc.v:171908$11751_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:171911$11754 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_rst + connect \Y $or$libresoc.v:171911$11754_Y + end + attribute \src "libresoc.v:171870.7-171870.20" + process $proc$libresoc.v:171870$11760 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:171892.7-171892.19" + process $proc$libresoc.v:171892$11761 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:171913.3-171914.27" + process $proc$libresoc.v:171913$11756 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:171915.3-171923.6" + process $proc$libresoc.v:171915$11757 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$11758 $1\q_int$next[0:0]$11759 + attribute \src "libresoc.v:171916.5-171916.29" + switch \initial + attribute \src "libresoc.v:171916.9-171916.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$11759 1'0 + case + assign $1\q_int$next[0:0]$11759 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$11758 + end + connect \$9 $and$libresoc.v:171905$11748_Y + connect \$11 $or$libresoc.v:171906$11749_Y + connect \$13 $not$libresoc.v:171907$11750_Y + connect \$15 $or$libresoc.v:171908$11751_Y + connect \$1 $not$libresoc.v:171909$11752_Y + connect \$3 $and$libresoc.v:171910$11753_Y + connect \$5 $or$libresoc.v:171911$11754_Y + connect \$7 $not$libresoc.v:171912$11755_Y + connect \qlq_rst \$15 + connect \qn_rst \$13 + connect \q_rst \$11 +end +attribute \src "libresoc.v:171931.1-171989.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.rst_l" +attribute \generator "nMigen" +module \rst_l$39 + attribute \src "libresoc.v:171932.7-171932.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:171977.3-171985.6" + wire $0\q_int$next[0:0]$11772 + attribute \src "libresoc.v:171975.3-171976.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:171977.3-171985.6" + wire $1\q_int$next[0:0]$11773 + attribute \src "libresoc.v:171954.7-171954.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:171967.17-171967.96" + wire $and$libresoc.v:171967$11762_Y + attribute \src "libresoc.v:171972.17-171972.96" + wire $and$libresoc.v:171972$11767_Y + attribute \src "libresoc.v:171969.18-171969.93" + wire $not$libresoc.v:171969$11764_Y + attribute \src "libresoc.v:171971.17-171971.92" + wire $not$libresoc.v:171971$11766_Y + attribute \src "libresoc.v:171974.17-171974.92" + wire $not$libresoc.v:171974$11769_Y + attribute \src "libresoc.v:171968.18-171968.98" + wire $or$libresoc.v:171968$11763_Y + attribute \src "libresoc.v:171970.18-171970.99" + wire $or$libresoc.v:171970$11765_Y + attribute \src "libresoc.v:171973.17-171973.97" + wire $or$libresoc.v:171973$11768_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 4 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 1 \coresync_rst + attribute \src "libresoc.v:171932.7-171932.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire \q_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 2 \s_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$libresoc.v:171967$11762 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:171967$11762_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:171972$11767 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:171972$11767_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:171969$11764 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rst + connect \Y $not$libresoc.v:171969$11764_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:171971$11766 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rst + connect \Y $not$libresoc.v:171971$11766_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:171974$11769 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rst + connect \Y $not$libresoc.v:171974$11769_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:171968$11763 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_rst + connect \Y $or$libresoc.v:171968$11763_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:171970$11765 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rst + connect \B \q_int + connect \Y $or$libresoc.v:171970$11765_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:171973$11768 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_rst + connect \Y $or$libresoc.v:171973$11768_Y + end + attribute \src "libresoc.v:171932.7-171932.20" + process $proc$libresoc.v:171932$11774 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:171954.7-171954.19" + process $proc$libresoc.v:171954$11775 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:171975.3-171976.27" + process $proc$libresoc.v:171975$11770 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:171977.3-171985.6" + process $proc$libresoc.v:171977$11771 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$11772 $1\q_int$next[0:0]$11773 + attribute \src "libresoc.v:171978.5-171978.29" + switch \initial + attribute \src "libresoc.v:171978.9-171978.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$11773 1'0 + case + assign $1\q_int$next[0:0]$11773 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$11772 + end + connect \$9 $and$libresoc.v:171967$11762_Y + connect \$11 $or$libresoc.v:171968$11763_Y + connect \$13 $not$libresoc.v:171969$11764_Y + connect \$15 $or$libresoc.v:171970$11765_Y + connect \$1 $not$libresoc.v:171971$11766_Y + connect \$3 $and$libresoc.v:171972$11767_Y + connect \$5 $or$libresoc.v:171973$11768_Y + connect \$7 $not$libresoc.v:171974$11769_Y + connect \qlq_rst \$15 + connect \qn_rst \$13 + connect \q_rst \$11 +end +attribute \src "libresoc.v:171993.1-172051.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.rst_l" +attribute \generator "nMigen" +module \rst_l$55 + attribute \src "libresoc.v:171994.7-171994.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:172039.3-172047.6" + wire $0\q_int$next[0:0]$11786 + attribute \src "libresoc.v:172037.3-172038.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:172039.3-172047.6" + wire $1\q_int$next[0:0]$11787 + attribute \src "libresoc.v:172016.7-172016.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:172029.17-172029.96" + wire $and$libresoc.v:172029$11776_Y + attribute \src "libresoc.v:172034.17-172034.96" + wire $and$libresoc.v:172034$11781_Y + attribute \src "libresoc.v:172031.18-172031.93" + wire $not$libresoc.v:172031$11778_Y + attribute \src "libresoc.v:172033.17-172033.92" + wire $not$libresoc.v:172033$11780_Y + attribute \src "libresoc.v:172036.17-172036.92" + wire $not$libresoc.v:172036$11783_Y + attribute \src "libresoc.v:172030.18-172030.98" + wire $or$libresoc.v:172030$11777_Y + attribute \src "libresoc.v:172032.18-172032.99" + wire $or$libresoc.v:172032$11779_Y + attribute \src "libresoc.v:172035.17-172035.97" + wire $or$libresoc.v:172035$11782_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 4 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 1 \coresync_rst + attribute \src "libresoc.v:171994.7-171994.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire \q_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 2 \s_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$libresoc.v:172029$11776 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:172029$11776_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:172034$11781 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:172034$11781_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:172031$11778 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rst + connect \Y $not$libresoc.v:172031$11778_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:172033$11780 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rst + connect \Y $not$libresoc.v:172033$11780_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:172036$11783 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rst + connect \Y $not$libresoc.v:172036$11783_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:172030$11777 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_rst + connect \Y $or$libresoc.v:172030$11777_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:172032$11779 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rst + connect \B \q_int + connect \Y $or$libresoc.v:172032$11779_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:172035$11782 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_rst + connect \Y $or$libresoc.v:172035$11782_Y + end + attribute \src "libresoc.v:171994.7-171994.20" + process $proc$libresoc.v:171994$11788 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:172016.7-172016.19" + process $proc$libresoc.v:172016$11789 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:172037.3-172038.27" + process $proc$libresoc.v:172037$11784 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:172039.3-172047.6" + process $proc$libresoc.v:172039$11785 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$11786 $1\q_int$next[0:0]$11787 + attribute \src "libresoc.v:172040.5-172040.29" + switch \initial + attribute \src "libresoc.v:172040.9-172040.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$11787 1'0 + case + assign $1\q_int$next[0:0]$11787 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$11786 + end + connect \$9 $and$libresoc.v:172029$11776_Y + connect \$11 $or$libresoc.v:172030$11777_Y + connect \$13 $not$libresoc.v:172031$11778_Y + connect \$15 $or$libresoc.v:172032$11779_Y + connect \$1 $not$libresoc.v:172033$11780_Y + connect \$3 $and$libresoc.v:172034$11781_Y + connect \$5 $or$libresoc.v:172035$11782_Y + connect \$7 $not$libresoc.v:172036$11783_Y + connect \qlq_rst \$15 + connect \qn_rst \$13 + connect \q_rst \$11 +end +attribute \src "libresoc.v:172055.1-172113.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.rst_l" +attribute \generator "nMigen" +module \rst_l$67 + attribute \src "libresoc.v:172056.7-172056.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:172101.3-172109.6" + wire $0\q_int$next[0:0]$11800 + attribute \src "libresoc.v:172099.3-172100.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:172101.3-172109.6" + wire $1\q_int$next[0:0]$11801 + attribute \src "libresoc.v:172078.7-172078.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:172091.17-172091.96" + wire $and$libresoc.v:172091$11790_Y + attribute \src "libresoc.v:172096.17-172096.96" + wire $and$libresoc.v:172096$11795_Y + attribute \src "libresoc.v:172093.18-172093.93" + wire $not$libresoc.v:172093$11792_Y + attribute \src "libresoc.v:172095.17-172095.92" + wire $not$libresoc.v:172095$11794_Y + attribute \src "libresoc.v:172098.17-172098.92" + wire $not$libresoc.v:172098$11797_Y + attribute \src "libresoc.v:172092.18-172092.98" + wire $or$libresoc.v:172092$11791_Y + attribute \src "libresoc.v:172094.18-172094.99" + wire $or$libresoc.v:172094$11793_Y + attribute \src "libresoc.v:172097.17-172097.97" + wire $or$libresoc.v:172097$11796_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 4 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 1 \coresync_rst + attribute \src "libresoc.v:172056.7-172056.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire \q_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 2 \s_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$libresoc.v:172091$11790 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:172091$11790_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:172096$11795 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:172096$11795_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:172093$11792 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rst + connect \Y $not$libresoc.v:172093$11792_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:172095$11794 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rst + connect \Y $not$libresoc.v:172095$11794_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:172098$11797 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rst + connect \Y $not$libresoc.v:172098$11797_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:172092$11791 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_rst + connect \Y $or$libresoc.v:172092$11791_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:172094$11793 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rst + connect \B \q_int + connect \Y $or$libresoc.v:172094$11793_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:172097$11796 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_rst + connect \Y $or$libresoc.v:172097$11796_Y + end + attribute \src "libresoc.v:172056.7-172056.20" + process $proc$libresoc.v:172056$11802 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:172078.7-172078.19" + process $proc$libresoc.v:172078$11803 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:172099.3-172100.27" + process $proc$libresoc.v:172099$11798 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:172101.3-172109.6" + process $proc$libresoc.v:172101$11799 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$11800 $1\q_int$next[0:0]$11801 + attribute \src "libresoc.v:172102.5-172102.29" + switch \initial + attribute \src "libresoc.v:172102.9-172102.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$11801 1'0 + case + assign $1\q_int$next[0:0]$11801 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$11800 + end + connect \$9 $and$libresoc.v:172091$11790_Y + connect \$11 $or$libresoc.v:172092$11791_Y + connect \$13 $not$libresoc.v:172093$11792_Y + connect \$15 $or$libresoc.v:172094$11793_Y + connect \$1 $not$libresoc.v:172095$11794_Y + connect \$3 $and$libresoc.v:172096$11795_Y + connect \$5 $or$libresoc.v:172097$11796_Y + connect \$7 $not$libresoc.v:172098$11797_Y + connect \qlq_rst \$15 + connect \qn_rst \$13 + connect \q_rst \$11 +end +attribute \src "libresoc.v:172117.1-172175.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.rst_l" +attribute \generator "nMigen" +module \rst_l$84 + attribute \src "libresoc.v:172118.7-172118.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:172163.3-172171.6" + wire $0\q_int$next[0:0]$11814 + attribute \src "libresoc.v:172161.3-172162.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:172163.3-172171.6" + wire $1\q_int$next[0:0]$11815 + attribute \src "libresoc.v:172140.7-172140.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:172153.17-172153.96" + wire $and$libresoc.v:172153$11804_Y + attribute \src "libresoc.v:172158.17-172158.96" + wire $and$libresoc.v:172158$11809_Y + attribute \src "libresoc.v:172155.18-172155.93" + wire $not$libresoc.v:172155$11806_Y + attribute \src "libresoc.v:172157.17-172157.92" + wire $not$libresoc.v:172157$11808_Y + attribute \src "libresoc.v:172160.17-172160.92" + wire $not$libresoc.v:172160$11811_Y + attribute \src "libresoc.v:172154.18-172154.98" + wire $or$libresoc.v:172154$11805_Y + attribute \src "libresoc.v:172156.18-172156.99" + wire $or$libresoc.v:172156$11807_Y + attribute \src "libresoc.v:172159.17-172159.97" + wire $or$libresoc.v:172159$11810_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 4 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 1 \coresync_rst + attribute \src "libresoc.v:172118.7-172118.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire \q_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 2 \s_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$libresoc.v:172153$11804 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:172153$11804_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:172158$11809 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:172158$11809_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:172155$11806 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rst + connect \Y $not$libresoc.v:172155$11806_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:172157$11808 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rst + connect \Y $not$libresoc.v:172157$11808_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:172160$11811 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rst + connect \Y $not$libresoc.v:172160$11811_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:172154$11805 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_rst + connect \Y $or$libresoc.v:172154$11805_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:172156$11807 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rst + connect \B \q_int + connect \Y $or$libresoc.v:172156$11807_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:172159$11810 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_rst + connect \Y $or$libresoc.v:172159$11810_Y + end + attribute \src "libresoc.v:172118.7-172118.20" + process $proc$libresoc.v:172118$11816 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:172140.7-172140.19" + process $proc$libresoc.v:172140$11817 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:172161.3-172162.27" + process $proc$libresoc.v:172161$11812 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:172163.3-172171.6" + process $proc$libresoc.v:172163$11813 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$11814 $1\q_int$next[0:0]$11815 + attribute \src "libresoc.v:172164.5-172164.29" + switch \initial + attribute \src "libresoc.v:172164.9-172164.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$11815 1'0 + case + assign $1\q_int$next[0:0]$11815 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$11814 + end + connect \$9 $and$libresoc.v:172153$11804_Y + connect \$11 $or$libresoc.v:172154$11805_Y + connect \$13 $not$libresoc.v:172155$11806_Y + connect \$15 $or$libresoc.v:172156$11807_Y + connect \$1 $not$libresoc.v:172157$11808_Y + connect \$3 $and$libresoc.v:172158$11809_Y + connect \$5 $or$libresoc.v:172159$11810_Y + connect \$7 $not$libresoc.v:172160$11811_Y + connect \qlq_rst \$15 + connect \qn_rst \$13 + connect \q_rst \$11 +end +attribute \src "libresoc.v:172179.1-172582.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_start.setup_stage" +attribute \generator "nMigen" +module \setup_stage + attribute \src "libresoc.v:172540.3-172565.6" + wire width 128 $0\dividend[127:0] + attribute \src "libresoc.v:172180.7-172180.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:172540.3-172565.6" + wire width 128 $1\dividend[127:0] + attribute \src "libresoc.v:172540.3-172565.6" + wire width 128 $2\dividend[127:0] + attribute \src "libresoc.v:172519.18-172519.122" + wire $and$libresoc.v:172519$11819_Y + attribute \src "libresoc.v:172521.18-172521.122" + wire $and$libresoc.v:172521$11821_Y + attribute \src "libresoc.v:172530.18-172530.105" + wire $and$libresoc.v:172530$11834_Y + attribute \src "libresoc.v:172533.18-172533.105" + wire $and$libresoc.v:172533$11837_Y + attribute \src "libresoc.v:172529.18-172529.123" + wire $eq$libresoc.v:172529$11833_Y + attribute \src "libresoc.v:172532.18-172532.123" + wire $eq$libresoc.v:172532$11836_Y + attribute \src "libresoc.v:172535.18-172535.117" + wire $eq$libresoc.v:172535$11839_Y + attribute \src "libresoc.v:172522.18-172522.97" + wire width 65 $extend$libresoc.v:172522$11822_Y + attribute \src "libresoc.v:172523.18-172523.91" + wire width 65 $extend$libresoc.v:172523$11824_Y + attribute \src "libresoc.v:172525.18-172525.97" + wire width 65 $extend$libresoc.v:172525$11827_Y + attribute \src "libresoc.v:172526.18-172526.91" + wire width 65 $extend$libresoc.v:172526$11829_Y + attribute \src "libresoc.v:172538.18-172538.99" + wire width 128 $extend$libresoc.v:172538$11842_Y + attribute \src "libresoc.v:172528.18-172528.112" + wire $ge$libresoc.v:172528$11832_Y + attribute \src "libresoc.v:172531.18-172531.124" + wire $ge$libresoc.v:172531$11835_Y + attribute \src "libresoc.v:172522.18-172522.97" + wire width 65 $neg$libresoc.v:172522$11823_Y + attribute \src "libresoc.v:172525.18-172525.97" + wire width 65 $neg$libresoc.v:172525$11828_Y + attribute \src "libresoc.v:172523.18-172523.91" + wire width 65 $pos$libresoc.v:172523$11825_Y + attribute \src "libresoc.v:172526.18-172526.91" + wire width 65 $pos$libresoc.v:172526$11830_Y + attribute \src "libresoc.v:172538.18-172538.99" + wire width 128 $pos$libresoc.v:172538$11843_Y + attribute \src "libresoc.v:172537.18-172537.117" + wire width 95 $sshl$libresoc.v:172537$11841_Y + attribute \src "libresoc.v:172539.18-172539.111" + wire width 191 $sshl$libresoc.v:172539$11844_Y + attribute \src "libresoc.v:172518.18-172518.131" + wire $ternary$libresoc.v:172518$11818_Y + attribute \src "libresoc.v:172520.18-172520.131" + wire $ternary$libresoc.v:172520$11820_Y + attribute \src "libresoc.v:172524.18-172524.119" + wire width 65 $ternary$libresoc.v:172524$11826_Y + attribute \src "libresoc.v:172527.18-172527.120" + wire width 65 $ternary$libresoc.v:172527$11831_Y + attribute \src "libresoc.v:172534.18-172534.130" + wire width 32 $ternary$libresoc.v:172534$11838_Y + attribute \src "libresoc.v:172536.18-172536.131" + wire width 32 $ternary$libresoc.v:172536$11840_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:45" + wire \$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:45" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:46" + wire \$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:46" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:53" + wire width 65 \$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:53" + wire width 65 \$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 65 \$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:53" + wire width 65 \$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:54" + wire width 65 \$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:54" + wire width 65 \$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 65 \$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:54" + wire width 65 \$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:57" + wire \$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:58" + wire \$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:58" + wire \$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:60" + wire \$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:61" + wire \$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:61" + wire \$53 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:34" + wire width 32 \$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:67" + wire \$57 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:34" + wire width 32 \$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:79" + wire width 128 \$61 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:79" + wire width 95 \$62 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:81" + wire width 191 \$65 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:81" + wire width 191 \$66 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:52" + wire width 64 \abs_dend + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:51" + wire width 64 \abs_dor + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire output 46 \div_by_zero + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire output 44 \dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire output 45 \dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" + wire width 128 output 47 \dividend + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire output 43 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire output 42 \divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" + wire width 64 output 48 \divisor_radicand + attribute \src "libresoc.v:172180.7-172180.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 17 \logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 39 \logical_op__data_len$18 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 2 \logical_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 output 24 \logical_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 3 \logical_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 25 \logical_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 4 \logical_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 26 \logical_op__imm_data__ok$5 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 11 \logical_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 33 \logical_op__input_carry$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 18 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 40 \logical_op__insn$19 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \logical_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 23 \logical_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 31 \logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 34 \logical_op__invert_out$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 15 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 37 \logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 16 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 38 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 7 \logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 29 \logical_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 30 \logical_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 36 \logical_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 6 \logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 28 \logical_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 5 \logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 27 \logical_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 35 \logical_op__write_cr0$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 32 \logical_op__zero_a$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 50 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 22 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" + wire width 2 output 49 \operation + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 19 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 20 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 21 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire output 41 \xer_so$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:45" + cell $and $and$libresoc.v:172519$11819 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$21 + connect \B \logical_op__is_signed + connect \Y $and$libresoc.v:172519$11819_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:46" + cell $and $and$libresoc.v:172521$11821 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$25 + connect \B \logical_op__is_signed + connect \Y $and$libresoc.v:172521$11821_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:58" + cell $and $and$libresoc.v:172530$11834 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$43 + connect \B \$45 + connect \Y $and$libresoc.v:172530$11834_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:61" + cell $and $and$libresoc.v:172533$11837 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$49 + connect \B \$51 + connect \Y $and$libresoc.v:172533$11837_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:58" + cell $eq $eq$libresoc.v:172529$11833 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \logical_op__insn_type + connect \B 7'0011110 + connect \Y $eq$libresoc.v:172529$11833_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:61" + cell $eq $eq$libresoc.v:172532$11836 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \logical_op__insn_type + connect \B 7'0011110 + connect \Y $eq$libresoc.v:172532$11836_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:67" + cell $eq $eq$libresoc.v:172535$11839 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \divisor_radicand + connect \B 1'0 + connect \Y $eq$libresoc.v:172535$11839_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:53" + cell $pos $extend$libresoc.v:172522$11822 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \rb + connect \Y $extend$libresoc.v:172522$11822_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + cell $pos $extend$libresoc.v:172523$11824 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \rb + connect \Y $extend$libresoc.v:172523$11824_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:54" + cell $pos $extend$libresoc.v:172525$11827 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \ra + connect \Y $extend$libresoc.v:172525$11827_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + cell $pos $extend$libresoc.v:172526$11829 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \ra + connect \Y $extend$libresoc.v:172526$11829_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:79" + cell $pos $extend$libresoc.v:172538$11842 + parameter \A_SIGNED 0 + parameter \A_WIDTH 95 + parameter \Y_WIDTH 128 + connect \A \$62 + connect \Y $extend$libresoc.v:172538$11842_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:57" + cell $ge $ge$libresoc.v:172528$11832 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 1 + connect \A \abs_dend + connect \B \abs_dor + connect \Y $ge$libresoc.v:172528$11832_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:60" + cell $ge $ge$libresoc.v:172531$11835 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 1 + connect \A \abs_dend [31:0] + connect \B \abs_dor [31:0] + connect \Y $ge$libresoc.v:172531$11835_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:53" + cell $neg $neg$libresoc.v:172522$11823 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \Y_WIDTH 65 + connect \A $extend$libresoc.v:172522$11822_Y + connect \Y $neg$libresoc.v:172522$11823_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:54" + cell $neg $neg$libresoc.v:172525$11828 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \Y_WIDTH 65 + connect \A $extend$libresoc.v:172525$11827_Y + connect \Y $neg$libresoc.v:172525$11828_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + cell $pos $pos$libresoc.v:172523$11825 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \Y_WIDTH 65 + connect \A $extend$libresoc.v:172523$11824_Y + connect \Y $pos$libresoc.v:172523$11825_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + cell $pos $pos$libresoc.v:172526$11830 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \Y_WIDTH 65 + connect \A $extend$libresoc.v:172526$11829_Y + connect \Y $pos$libresoc.v:172526$11830_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:79" + cell $pos $pos$libresoc.v:172538$11843 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \Y_WIDTH 128 + connect \A $extend$libresoc.v:172538$11842_Y + connect \Y $pos$libresoc.v:172538$11843_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:79" + cell $sshl $sshl$libresoc.v:172537$11841 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 95 + connect \A \abs_dend [31:0] + connect \B 6'100000 + connect \Y $sshl$libresoc.v:172537$11841_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:81" + cell $sshl $sshl$libresoc.v:172539$11844 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 191 + connect \A \abs_dend + connect \B 7'1000000 + connect \Y $sshl$libresoc.v:172539$11844_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:45" + cell $mux $ternary$libresoc.v:172518$11818 + parameter \WIDTH 1 + connect \A \ra [63] + connect \B \ra [31] + connect \S \logical_op__is_32bit + connect \Y $ternary$libresoc.v:172518$11818_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:46" + cell $mux $ternary$libresoc.v:172520$11820 + parameter \WIDTH 1 + connect \A \rb [63] + connect \B \rb [31] + connect \S \logical_op__is_32bit + connect \Y $ternary$libresoc.v:172520$11820_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:53" + cell $mux $ternary$libresoc.v:172524$11826 + parameter \WIDTH 65 + connect \A \$32 + connect \B \$30 + connect \S \divisor_neg + connect \Y $ternary$libresoc.v:172524$11826_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:54" + cell $mux $ternary$libresoc.v:172527$11831 + parameter \WIDTH 65 + connect \A \$39 + connect \B \$37 + connect \S \dividend_neg + connect \Y $ternary$libresoc.v:172527$11831_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:34" + cell $mux $ternary$libresoc.v:172534$11838 + parameter \WIDTH 32 + connect \A \abs_dor [63:32] + connect \B 0 + connect \S \logical_op__is_32bit + connect \Y $ternary$libresoc.v:172534$11838_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:34" + cell $mux $ternary$libresoc.v:172536$11840 + parameter \WIDTH 32 + connect \A \abs_dend [63:32] + connect \B 0 + connect \S \logical_op__is_32bit + connect \Y $ternary$libresoc.v:172536$11840_Y + end + attribute \src "libresoc.v:172180.7-172180.20" + process $proc$libresoc.v:172180$11846 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:172540.3-172565.6" + process $proc$libresoc.v:172540$11845 + assign { } { } + assign { } { } + assign $0\dividend[127:0] $1\dividend[127:0] + attribute \src "libresoc.v:172541.5-172541.29" + switch \initial + attribute \src "libresoc.v:172541.9-172541.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:72" + switch \logical_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0011101 , 7'0101111 + assign $1\dividend[127:0] [127:64] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\dividend[127:0] [31:0] \abs_dend [31:0] + assign $1\dividend[127:0] [63:32] \$59 + attribute \src "libresoc.v:0.0-0.0" + case 7'0011110 + assign { } { } + assign $1\dividend[127:0] $2\dividend[127:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:78" + switch \logical_op__is_32bit + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\dividend[127:0] \$61 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\dividend[127:0] \$65 [127:0] + end + case + assign $1\dividend[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \dividend $0\dividend[127:0] + end + connect \$21 $ternary$libresoc.v:172518$11818_Y + connect \$23 $and$libresoc.v:172519$11819_Y + connect \$25 $ternary$libresoc.v:172520$11820_Y + connect \$27 $and$libresoc.v:172521$11821_Y + connect \$30 $neg$libresoc.v:172522$11823_Y + connect \$32 $pos$libresoc.v:172523$11825_Y + connect \$34 $ternary$libresoc.v:172524$11826_Y + connect \$37 $neg$libresoc.v:172525$11828_Y + connect \$39 $pos$libresoc.v:172526$11830_Y + connect \$41 $ternary$libresoc.v:172527$11831_Y + connect \$43 $ge$libresoc.v:172528$11832_Y + connect \$45 $eq$libresoc.v:172529$11833_Y + connect \$47 $and$libresoc.v:172530$11834_Y + connect \$49 $ge$libresoc.v:172531$11835_Y + connect \$51 $eq$libresoc.v:172532$11836_Y + connect \$53 $and$libresoc.v:172533$11837_Y + connect \$55 $ternary$libresoc.v:172534$11838_Y + connect \$57 $eq$libresoc.v:172535$11839_Y + connect \$59 $ternary$libresoc.v:172536$11840_Y + connect \$62 $sshl$libresoc.v:172537$11841_Y + connect \$61 $pos$libresoc.v:172538$11843_Y + connect \$66 $sshl$libresoc.v:172539$11844_Y + connect \$29 \$34 + connect \$36 \$41 + connect \$65 \$66 + connect { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } + connect \muxid$1 \muxid + connect \xer_so$20 \xer_so + connect \div_by_zero \$57 + connect \divisor_radicand [63:32] \$55 + connect \divisor_radicand [31:0] \abs_dor [31:0] + connect \dive_abs_ov32 \$53 + connect \dive_abs_ov64 \$47 + connect \abs_dend \$41 [63:0] + connect \abs_dor \$34 [63:0] + connect \divisor_neg \$27 + connect \dividend_neg \$23 + connect \operation 2'01 +end +attribute \src "libresoc.v:172586.1-173777.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0" +attribute \generator "nMigen" +module \shiftrot0 + attribute \src "libresoc.v:173350.3-173351.25" + wire $0\all_rd_dly[0:0] + attribute \src "libresoc.v:173348.3-173349.46" + wire $0\alu_done_dly[0:0] + attribute \src "libresoc.v:173697.3-173705.6" + wire $0\alu_l_r_alu$next[0:0]$12061 + attribute \src "libresoc.v:173268.3-173269.39" + wire $0\alu_l_r_alu[0:0] + attribute \src "libresoc.v:173535.3-173571.6" + wire width 12 $0\alu_shift_rot0_sr_op__fn_unit$next[11:0]$11980 + attribute \src "libresoc.v:173296.3-173297.75" + wire width 12 $0\alu_shift_rot0_sr_op__fn_unit[11:0] + attribute \src "libresoc.v:173535.3-173571.6" + wire width 64 $0\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$11981 + attribute \src "libresoc.v:173298.3-173299.89" + wire width 64 $0\alu_shift_rot0_sr_op__imm_data__data[63:0] + attribute \src "libresoc.v:173535.3-173571.6" + wire $0\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$11982 + attribute \src "libresoc.v:173300.3-173301.85" + wire $0\alu_shift_rot0_sr_op__imm_data__ok[0:0] + attribute \src "libresoc.v:173535.3-173571.6" + wire width 2 $0\alu_shift_rot0_sr_op__input_carry$next[1:0]$11983 + attribute \src "libresoc.v:173312.3-173313.83" + wire width 2 $0\alu_shift_rot0_sr_op__input_carry[1:0] + attribute \src "libresoc.v:173535.3-173571.6" + wire $0\alu_shift_rot0_sr_op__input_cr$next[0:0]$11984 + attribute \src "libresoc.v:173316.3-173317.77" + wire $0\alu_shift_rot0_sr_op__input_cr[0:0] + attribute \src "libresoc.v:173535.3-173571.6" + wire width 32 $0\alu_shift_rot0_sr_op__insn$next[31:0]$11985 + attribute \src "libresoc.v:173324.3-173325.69" + wire width 32 $0\alu_shift_rot0_sr_op__insn[31:0] + attribute \src "libresoc.v:173535.3-173571.6" + wire width 7 $0\alu_shift_rot0_sr_op__insn_type$next[6:0]$11986 + attribute \src "libresoc.v:173294.3-173295.79" + wire width 7 $0\alu_shift_rot0_sr_op__insn_type[6:0] + attribute \src "libresoc.v:173535.3-173571.6" + wire $0\alu_shift_rot0_sr_op__is_32bit$next[0:0]$11987 + attribute \src "libresoc.v:173320.3-173321.77" + wire $0\alu_shift_rot0_sr_op__is_32bit[0:0] + attribute \src "libresoc.v:173535.3-173571.6" + wire $0\alu_shift_rot0_sr_op__is_signed$next[0:0]$11988 + attribute \src "libresoc.v:173322.3-173323.79" + wire $0\alu_shift_rot0_sr_op__is_signed[0:0] + attribute \src "libresoc.v:173535.3-173571.6" + wire $0\alu_shift_rot0_sr_op__oe__oe$next[0:0]$11989 + attribute \src "libresoc.v:173306.3-173307.73" + wire $0\alu_shift_rot0_sr_op__oe__oe[0:0] + attribute \src "libresoc.v:173535.3-173571.6" + wire $0\alu_shift_rot0_sr_op__oe__ok$next[0:0]$11990 + attribute \src "libresoc.v:173308.3-173309.73" + wire $0\alu_shift_rot0_sr_op__oe__ok[0:0] + attribute \src "libresoc.v:173535.3-173571.6" + wire $0\alu_shift_rot0_sr_op__output_carry$next[0:0]$11991 + attribute \src "libresoc.v:173314.3-173315.85" + wire $0\alu_shift_rot0_sr_op__output_carry[0:0] + attribute \src "libresoc.v:173535.3-173571.6" + wire $0\alu_shift_rot0_sr_op__output_cr$next[0:0]$11992 + attribute \src "libresoc.v:173318.3-173319.79" + wire $0\alu_shift_rot0_sr_op__output_cr[0:0] + attribute \src "libresoc.v:173535.3-173571.6" + wire $0\alu_shift_rot0_sr_op__rc__ok$next[0:0]$11993 + attribute \src "libresoc.v:173304.3-173305.73" + wire $0\alu_shift_rot0_sr_op__rc__ok[0:0] + attribute \src "libresoc.v:173535.3-173571.6" + wire $0\alu_shift_rot0_sr_op__rc__rc$next[0:0]$11994 + attribute \src "libresoc.v:173302.3-173303.73" + wire $0\alu_shift_rot0_sr_op__rc__rc[0:0] + attribute \src "libresoc.v:173535.3-173571.6" + wire $0\alu_shift_rot0_sr_op__write_cr0$next[0:0]$11995 + attribute \src "libresoc.v:173310.3-173311.79" + wire $0\alu_shift_rot0_sr_op__write_cr0[0:0] + attribute \src "libresoc.v:173688.3-173696.6" + wire $0\alui_l_r_alui$next[0:0]$12058 + attribute \src "libresoc.v:173270.3-173271.43" + wire $0\alui_l_r_alui[0:0] + attribute \src "libresoc.v:173572.3-173593.6" + wire width 64 $0\data_r0__o$next[63:0]$12019 + attribute \src "libresoc.v:173290.3-173291.37" + wire width 64 $0\data_r0__o[63:0] + attribute \src "libresoc.v:173572.3-173593.6" + wire $0\data_r0__o_ok$next[0:0]$12020 + attribute \src "libresoc.v:173292.3-173293.43" + wire $0\data_r0__o_ok[0:0] + attribute \src "libresoc.v:173594.3-173615.6" + wire width 4 $0\data_r1__cr_a$next[3:0]$12027 + attribute \src "libresoc.v:173286.3-173287.43" + wire width 4 $0\data_r1__cr_a[3:0] + attribute \src "libresoc.v:173594.3-173615.6" + wire $0\data_r1__cr_a_ok$next[0:0]$12028 + attribute \src "libresoc.v:173288.3-173289.49" + wire $0\data_r1__cr_a_ok[0:0] + attribute \src "libresoc.v:173616.3-173637.6" + wire width 2 $0\data_r2__xer_ca$next[1:0]$12035 + attribute \src "libresoc.v:173282.3-173283.47" + wire width 2 $0\data_r2__xer_ca[1:0] + attribute \src "libresoc.v:173616.3-173637.6" + wire $0\data_r2__xer_ca_ok$next[0:0]$12036 + attribute \src "libresoc.v:173284.3-173285.53" + wire $0\data_r2__xer_ca_ok[0:0] + attribute \src "libresoc.v:173706.3-173715.6" + wire width 64 $0\dest1_o[63:0] + attribute \src "libresoc.v:173716.3-173725.6" + wire width 4 $0\dest2_o[3:0] + attribute \src "libresoc.v:173726.3-173735.6" + wire width 2 $0\dest3_o[1:0] + attribute \src "libresoc.v:172587.7-172587.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:173490.3-173498.6" + wire $0\opc_l_r_opc$next[0:0]$11965 + attribute \src "libresoc.v:173334.3-173335.39" + wire $0\opc_l_r_opc[0:0] + attribute \src "libresoc.v:173481.3-173489.6" + wire $0\opc_l_s_opc$next[0:0]$11962 + attribute \src "libresoc.v:173336.3-173337.39" + wire $0\opc_l_s_opc[0:0] + attribute \src "libresoc.v:173736.3-173744.6" + wire width 3 $0\prev_wr_go$next[2:0]$12067 + attribute \src "libresoc.v:173346.3-173347.37" + wire width 3 $0\prev_wr_go[2:0] + attribute \src "libresoc.v:173435.3-173444.6" + wire $0\req_done[0:0] + attribute \src "libresoc.v:173526.3-173534.6" + wire width 3 $0\req_l_r_req$next[2:0]$11977 + attribute \src "libresoc.v:173326.3-173327.39" + wire width 3 $0\req_l_r_req[2:0] + attribute \src "libresoc.v:173517.3-173525.6" + wire width 3 $0\req_l_s_req$next[2:0]$11974 + attribute \src "libresoc.v:173328.3-173329.39" + wire width 3 $0\req_l_s_req[2:0] + attribute \src "libresoc.v:173454.3-173462.6" + wire $0\rok_l_r_rdok$next[0:0]$11953 + attribute \src "libresoc.v:173342.3-173343.41" + wire $0\rok_l_r_rdok[0:0] + attribute \src "libresoc.v:173445.3-173453.6" + wire $0\rok_l_s_rdok$next[0:0]$11950 + attribute \src "libresoc.v:173344.3-173345.41" + wire $0\rok_l_s_rdok[0:0] + attribute \src "libresoc.v:173472.3-173480.6" + wire $0\rst_l_r_rst$next[0:0]$11959 + attribute \src "libresoc.v:173338.3-173339.39" + wire $0\rst_l_r_rst[0:0] + attribute \src "libresoc.v:173463.3-173471.6" + wire $0\rst_l_s_rst$next[0:0]$11956 + attribute \src "libresoc.v:173340.3-173341.39" + wire $0\rst_l_s_rst[0:0] + attribute \src "libresoc.v:173508.3-173516.6" + wire width 5 $0\src_l_r_src$next[4:0]$11971 + attribute \src "libresoc.v:173330.3-173331.39" + wire width 5 $0\src_l_r_src[4:0] + attribute \src "libresoc.v:173499.3-173507.6" + wire width 5 $0\src_l_s_src$next[4:0]$11968 + attribute \src "libresoc.v:173332.3-173333.39" + wire width 5 $0\src_l_s_src[4:0] + attribute \src "libresoc.v:173638.3-173647.6" + wire width 64 $0\src_r0$next[63:0]$12043 + attribute \src "libresoc.v:173280.3-173281.29" + wire width 64 $0\src_r0[63:0] + attribute \src "libresoc.v:173648.3-173657.6" + wire width 64 $0\src_r1$next[63:0]$12046 + attribute \src "libresoc.v:173278.3-173279.29" + wire width 64 $0\src_r1[63:0] + attribute \src "libresoc.v:173658.3-173667.6" + wire width 64 $0\src_r2$next[63:0]$12049 + attribute \src "libresoc.v:173276.3-173277.29" + wire width 64 $0\src_r2[63:0] + attribute \src "libresoc.v:173668.3-173677.6" + wire $0\src_r3$next[0:0]$12052 + attribute \src "libresoc.v:173274.3-173275.29" + wire $0\src_r3[0:0] + attribute \src "libresoc.v:173678.3-173687.6" + wire width 2 $0\src_r4$next[1:0]$12055 + attribute \src "libresoc.v:173272.3-173273.29" + wire width 2 $0\src_r4[1:0] + attribute \src "libresoc.v:172709.7-172709.24" + wire $1\all_rd_dly[0:0] + attribute \src "libresoc.v:172719.7-172719.26" + wire $1\alu_done_dly[0:0] + attribute \src "libresoc.v:173697.3-173705.6" + wire $1\alu_l_r_alu$next[0:0]$12062 + attribute \src "libresoc.v:172727.7-172727.25" + wire $1\alu_l_r_alu[0:0] + attribute \src "libresoc.v:173535.3-173571.6" + wire width 12 $1\alu_shift_rot0_sr_op__fn_unit$next[11:0]$11996 + attribute \src "libresoc.v:172768.14-172768.53" + wire width 12 $1\alu_shift_rot0_sr_op__fn_unit[11:0] + attribute \src "libresoc.v:173535.3-173571.6" + wire width 64 $1\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$11997 + attribute \src "libresoc.v:172772.14-172772.73" + wire width 64 $1\alu_shift_rot0_sr_op__imm_data__data[63:0] + attribute \src "libresoc.v:173535.3-173571.6" + wire $1\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$11998 + attribute \src "libresoc.v:172776.7-172776.48" + wire $1\alu_shift_rot0_sr_op__imm_data__ok[0:0] + attribute \src "libresoc.v:173535.3-173571.6" + wire width 2 $1\alu_shift_rot0_sr_op__input_carry$next[1:0]$11999 + attribute \src "libresoc.v:172784.13-172784.53" + wire width 2 $1\alu_shift_rot0_sr_op__input_carry[1:0] + attribute \src "libresoc.v:173535.3-173571.6" + wire $1\alu_shift_rot0_sr_op__input_cr$next[0:0]$12000 + attribute \src "libresoc.v:172788.7-172788.44" + wire $1\alu_shift_rot0_sr_op__input_cr[0:0] + attribute \src "libresoc.v:173535.3-173571.6" + wire width 32 $1\alu_shift_rot0_sr_op__insn$next[31:0]$12001 + attribute \src "libresoc.v:172792.14-172792.48" + wire width 32 $1\alu_shift_rot0_sr_op__insn[31:0] + attribute \src "libresoc.v:173535.3-173571.6" + wire width 7 $1\alu_shift_rot0_sr_op__insn_type$next[6:0]$12002 + attribute \src "libresoc.v:172870.13-172870.52" + wire width 7 $1\alu_shift_rot0_sr_op__insn_type[6:0] + attribute \src "libresoc.v:173535.3-173571.6" + wire $1\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12003 + attribute \src "libresoc.v:172874.7-172874.44" + wire $1\alu_shift_rot0_sr_op__is_32bit[0:0] + attribute \src "libresoc.v:173535.3-173571.6" + wire $1\alu_shift_rot0_sr_op__is_signed$next[0:0]$12004 + attribute \src "libresoc.v:172878.7-172878.45" + wire $1\alu_shift_rot0_sr_op__is_signed[0:0] + attribute \src "libresoc.v:173535.3-173571.6" + wire $1\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12005 + attribute \src "libresoc.v:172882.7-172882.42" + wire $1\alu_shift_rot0_sr_op__oe__oe[0:0] + attribute \src "libresoc.v:173535.3-173571.6" + wire $1\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12006 + attribute \src "libresoc.v:172886.7-172886.42" + wire $1\alu_shift_rot0_sr_op__oe__ok[0:0] + attribute \src "libresoc.v:173535.3-173571.6" + wire $1\alu_shift_rot0_sr_op__output_carry$next[0:0]$12007 + attribute \src "libresoc.v:172890.7-172890.48" + wire $1\alu_shift_rot0_sr_op__output_carry[0:0] + attribute \src "libresoc.v:173535.3-173571.6" + wire $1\alu_shift_rot0_sr_op__output_cr$next[0:0]$12008 + attribute \src "libresoc.v:172894.7-172894.45" + wire $1\alu_shift_rot0_sr_op__output_cr[0:0] + attribute \src "libresoc.v:173535.3-173571.6" + wire $1\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12009 + attribute \src "libresoc.v:172898.7-172898.42" + wire $1\alu_shift_rot0_sr_op__rc__ok[0:0] + attribute \src "libresoc.v:173535.3-173571.6" + wire $1\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12010 + attribute \src "libresoc.v:172902.7-172902.42" + wire $1\alu_shift_rot0_sr_op__rc__rc[0:0] + attribute \src "libresoc.v:173535.3-173571.6" + wire $1\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12011 + attribute \src "libresoc.v:172906.7-172906.45" + wire $1\alu_shift_rot0_sr_op__write_cr0[0:0] + attribute \src "libresoc.v:173688.3-173696.6" + wire $1\alui_l_r_alui$next[0:0]$12059 + attribute \src "libresoc.v:172918.7-172918.27" + wire $1\alui_l_r_alui[0:0] + attribute \src "libresoc.v:173572.3-173593.6" + wire width 64 $1\data_r0__o$next[63:0]$12021 + attribute \src "libresoc.v:172952.14-172952.47" + wire width 64 $1\data_r0__o[63:0] + attribute \src "libresoc.v:173572.3-173593.6" + wire $1\data_r0__o_ok$next[0:0]$12022 + attribute \src "libresoc.v:172956.7-172956.27" + wire $1\data_r0__o_ok[0:0] + attribute \src "libresoc.v:173594.3-173615.6" + wire width 4 $1\data_r1__cr_a$next[3:0]$12029 + attribute \src "libresoc.v:172960.13-172960.33" + wire width 4 $1\data_r1__cr_a[3:0] + attribute \src "libresoc.v:173594.3-173615.6" + wire $1\data_r1__cr_a_ok$next[0:0]$12030 + attribute \src "libresoc.v:172964.7-172964.30" + wire $1\data_r1__cr_a_ok[0:0] + attribute \src "libresoc.v:173616.3-173637.6" + wire width 2 $1\data_r2__xer_ca$next[1:0]$12037 + attribute \src "libresoc.v:172968.13-172968.35" + wire width 2 $1\data_r2__xer_ca[1:0] + attribute \src "libresoc.v:173616.3-173637.6" + wire $1\data_r2__xer_ca_ok$next[0:0]$12038 + attribute \src "libresoc.v:172972.7-172972.32" + wire $1\data_r2__xer_ca_ok[0:0] + attribute \src "libresoc.v:173706.3-173715.6" + wire width 64 $1\dest1_o[63:0] + attribute \src "libresoc.v:173716.3-173725.6" + wire width 4 $1\dest2_o[3:0] + attribute \src "libresoc.v:173726.3-173735.6" + wire width 2 $1\dest3_o[1:0] + attribute \src "libresoc.v:173490.3-173498.6" + wire $1\opc_l_r_opc$next[0:0]$11966 + attribute \src "libresoc.v:172989.7-172989.25" + wire $1\opc_l_r_opc[0:0] + attribute \src "libresoc.v:173481.3-173489.6" + wire $1\opc_l_s_opc$next[0:0]$11963 + attribute \src "libresoc.v:172993.7-172993.25" + wire $1\opc_l_s_opc[0:0] + attribute \src "libresoc.v:173736.3-173744.6" + wire width 3 $1\prev_wr_go$next[2:0]$12068 + attribute \src "libresoc.v:173120.13-173120.30" + wire width 3 $1\prev_wr_go[2:0] + attribute \src "libresoc.v:173435.3-173444.6" + wire $1\req_done[0:0] + attribute \src "libresoc.v:173526.3-173534.6" + wire width 3 $1\req_l_r_req$next[2:0]$11978 + attribute \src "libresoc.v:173128.13-173128.31" + wire width 3 $1\req_l_r_req[2:0] + attribute \src "libresoc.v:173517.3-173525.6" + wire width 3 $1\req_l_s_req$next[2:0]$11975 + attribute \src "libresoc.v:173132.13-173132.31" + wire width 3 $1\req_l_s_req[2:0] + attribute \src "libresoc.v:173454.3-173462.6" + wire $1\rok_l_r_rdok$next[0:0]$11954 + attribute \src "libresoc.v:173144.7-173144.26" + wire $1\rok_l_r_rdok[0:0] + attribute \src "libresoc.v:173445.3-173453.6" + wire $1\rok_l_s_rdok$next[0:0]$11951 + attribute \src "libresoc.v:173148.7-173148.26" + wire $1\rok_l_s_rdok[0:0] + attribute \src "libresoc.v:173472.3-173480.6" + wire $1\rst_l_r_rst$next[0:0]$11960 + attribute \src "libresoc.v:173152.7-173152.25" + wire $1\rst_l_r_rst[0:0] + attribute \src "libresoc.v:173463.3-173471.6" + wire $1\rst_l_s_rst$next[0:0]$11957 + attribute \src "libresoc.v:173156.7-173156.25" + wire $1\rst_l_s_rst[0:0] + attribute \src "libresoc.v:173508.3-173516.6" + wire width 5 $1\src_l_r_src$next[4:0]$11972 + attribute \src "libresoc.v:173174.13-173174.32" + wire width 5 $1\src_l_r_src[4:0] + attribute \src "libresoc.v:173499.3-173507.6" + wire width 5 $1\src_l_s_src$next[4:0]$11969 + attribute \src "libresoc.v:173178.13-173178.32" + wire width 5 $1\src_l_s_src[4:0] + attribute \src "libresoc.v:173638.3-173647.6" + wire width 64 $1\src_r0$next[63:0]$12044 + attribute \src "libresoc.v:173184.14-173184.43" + wire width 64 $1\src_r0[63:0] + attribute \src "libresoc.v:173648.3-173657.6" + wire width 64 $1\src_r1$next[63:0]$12047 + attribute \src "libresoc.v:173188.14-173188.43" + wire width 64 $1\src_r1[63:0] + attribute \src "libresoc.v:173658.3-173667.6" + wire width 64 $1\src_r2$next[63:0]$12050 + attribute \src "libresoc.v:173192.14-173192.43" + wire width 64 $1\src_r2[63:0] + attribute \src "libresoc.v:173668.3-173677.6" + wire $1\src_r3$next[0:0]$12053 + attribute \src "libresoc.v:173196.7-173196.20" + wire $1\src_r3[0:0] + attribute \src "libresoc.v:173678.3-173687.6" + wire width 2 $1\src_r4$next[1:0]$12056 + attribute \src "libresoc.v:173200.13-173200.26" + wire width 2 $1\src_r4[1:0] + attribute \src "libresoc.v:173535.3-173571.6" + wire width 64 $2\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12012 + attribute \src "libresoc.v:173535.3-173571.6" + wire $2\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12013 + attribute \src "libresoc.v:173535.3-173571.6" + wire $2\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12014 + attribute \src "libresoc.v:173535.3-173571.6" + wire $2\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12015 + attribute \src "libresoc.v:173535.3-173571.6" + wire $2\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12016 + attribute \src "libresoc.v:173535.3-173571.6" + wire $2\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12017 + attribute \src "libresoc.v:173572.3-173593.6" + wire width 64 $2\data_r0__o$next[63:0]$12023 + attribute \src "libresoc.v:173572.3-173593.6" + wire $2\data_r0__o_ok$next[0:0]$12024 + attribute \src "libresoc.v:173594.3-173615.6" + wire width 4 $2\data_r1__cr_a$next[3:0]$12031 + attribute \src "libresoc.v:173594.3-173615.6" + wire $2\data_r1__cr_a_ok$next[0:0]$12032 + attribute \src "libresoc.v:173616.3-173637.6" + wire width 2 $2\data_r2__xer_ca$next[1:0]$12039 + attribute \src "libresoc.v:173616.3-173637.6" + wire $2\data_r2__xer_ca_ok$next[0:0]$12040 + attribute \src "libresoc.v:173572.3-173593.6" + wire $3\data_r0__o_ok$next[0:0]$12025 + attribute \src "libresoc.v:173594.3-173615.6" + wire $3\data_r1__cr_a_ok$next[0:0]$12033 + attribute \src "libresoc.v:173616.3-173637.6" + wire $3\data_r2__xer_ca_ok$next[0:0]$12041 + attribute \src "libresoc.v:173210.19-173210.114" + wire width 5 $and$libresoc.v:173210$11848_Y + attribute \src "libresoc.v:173211.19-173211.125" + wire $and$libresoc.v:173211$11849_Y + attribute \src "libresoc.v:173212.19-173212.125" + wire $and$libresoc.v:173212$11850_Y + attribute \src "libresoc.v:173213.19-173213.125" + wire $and$libresoc.v:173213$11851_Y + attribute \src "libresoc.v:173214.18-173214.110" + wire $and$libresoc.v:173214$11852_Y + attribute \src "libresoc.v:173215.19-173215.141" + wire width 3 $and$libresoc.v:173215$11853_Y + attribute \src "libresoc.v:173216.19-173216.121" + wire width 3 $and$libresoc.v:173216$11854_Y + attribute \src "libresoc.v:173217.19-173217.127" + wire $and$libresoc.v:173217$11855_Y + attribute \src "libresoc.v:173218.19-173218.127" + wire $and$libresoc.v:173218$11856_Y + attribute \src "libresoc.v:173219.19-173219.127" + wire $and$libresoc.v:173219$11857_Y + attribute \src "libresoc.v:173221.18-173221.98" + wire $and$libresoc.v:173221$11859_Y + attribute \src "libresoc.v:173223.18-173223.100" + wire $and$libresoc.v:173223$11861_Y + attribute \src "libresoc.v:173224.18-173224.149" + wire width 3 $and$libresoc.v:173224$11862_Y + attribute \src "libresoc.v:173226.18-173226.119" + wire width 3 $and$libresoc.v:173226$11864_Y + attribute \src "libresoc.v:173229.17-173229.123" + wire $and$libresoc.v:173229$11867_Y + attribute \src "libresoc.v:173230.18-173230.116" + wire $and$libresoc.v:173230$11868_Y + attribute \src "libresoc.v:173235.18-173235.113" + wire $and$libresoc.v:173235$11873_Y + attribute \src "libresoc.v:173236.18-173236.125" + wire width 3 $and$libresoc.v:173236$11874_Y + attribute \src "libresoc.v:173238.18-173238.112" + wire $and$libresoc.v:173238$11876_Y + attribute \src "libresoc.v:173240.18-173240.132" + wire $and$libresoc.v:173240$11878_Y + attribute \src "libresoc.v:173241.18-173241.132" + wire $and$libresoc.v:173241$11879_Y + attribute \src "libresoc.v:173242.18-173242.117" + wire $and$libresoc.v:173242$11880_Y + attribute \src "libresoc.v:173248.18-173248.136" + wire $and$libresoc.v:173248$11886_Y + attribute \src "libresoc.v:173249.18-173249.124" + wire width 3 $and$libresoc.v:173249$11887_Y + attribute \src "libresoc.v:173251.18-173251.116" + wire $and$libresoc.v:173251$11889_Y + attribute \src "libresoc.v:173252.18-173252.119" + wire $and$libresoc.v:173252$11890_Y + attribute \src "libresoc.v:173253.18-173253.121" + wire $and$libresoc.v:173253$11891_Y + attribute \src "libresoc.v:173263.18-173263.140" + wire $and$libresoc.v:173263$11901_Y + attribute \src "libresoc.v:173264.18-173264.138" + wire $and$libresoc.v:173264$11902_Y + attribute \src "libresoc.v:173265.18-173265.171" + wire width 5 $and$libresoc.v:173265$11903_Y + attribute \src "libresoc.v:173267.18-173267.129" + wire width 5 $and$libresoc.v:173267$11905_Y + attribute \src "libresoc.v:173237.18-173237.113" + wire $eq$libresoc.v:173237$11875_Y + attribute \src "libresoc.v:173239.18-173239.119" + wire $eq$libresoc.v:173239$11877_Y + attribute \src "libresoc.v:173209.19-173209.115" + wire width 5 $not$libresoc.v:173209$11847_Y + attribute \src "libresoc.v:173220.18-173220.97" + wire $not$libresoc.v:173220$11858_Y + attribute \src "libresoc.v:173222.18-173222.99" + wire $not$libresoc.v:173222$11860_Y + attribute \src "libresoc.v:173225.18-173225.113" + wire width 3 $not$libresoc.v:173225$11863_Y + attribute \src "libresoc.v:173228.18-173228.106" + wire $not$libresoc.v:173228$11866_Y + attribute \src "libresoc.v:173234.18-173234.126" + wire $not$libresoc.v:173234$11872_Y + attribute \src "libresoc.v:173245.17-173245.113" + wire width 5 $not$libresoc.v:173245$11883_Y + attribute \src "libresoc.v:173266.18-173266.136" + wire $not$libresoc.v:173266$11904_Y + attribute \src "libresoc.v:173233.18-173233.112" + wire $or$libresoc.v:173233$11871_Y + attribute \src "libresoc.v:173243.18-173243.122" + wire $or$libresoc.v:173243$11881_Y + attribute \src "libresoc.v:173244.18-173244.124" + wire $or$libresoc.v:173244$11882_Y + attribute \src "libresoc.v:173246.18-173246.155" + wire width 3 $or$libresoc.v:173246$11884_Y + attribute \src "libresoc.v:173247.18-173247.181" + wire width 5 $or$libresoc.v:173247$11885_Y + attribute \src "libresoc.v:173250.18-173250.120" + wire width 3 $or$libresoc.v:173250$11888_Y + attribute \src "libresoc.v:173256.17-173256.117" + wire width 5 $or$libresoc.v:173256$11894_Y + attribute \src "libresoc.v:173262.17-173262.104" + wire $reduce_and$libresoc.v:173262$11900_Y + attribute \src "libresoc.v:173227.18-173227.106" + wire $reduce_or$libresoc.v:173227$11865_Y + attribute \src "libresoc.v:173231.18-173231.113" + wire $reduce_or$libresoc.v:173231$11869_Y + attribute \src "libresoc.v:173232.18-173232.112" + wire $reduce_or$libresoc.v:173232$11870_Y + attribute \src "libresoc.v:173254.18-173254.165" + wire $ternary$libresoc.v:173254$11892_Y + attribute \src "libresoc.v:173255.18-173255.182" + wire width 64 $ternary$libresoc.v:173255$11893_Y + attribute \src "libresoc.v:173257.18-173257.118" + wire width 64 $ternary$libresoc.v:173257$11895_Y + attribute \src "libresoc.v:173258.18-173258.115" + wire width 64 $ternary$libresoc.v:173258$11896_Y + attribute \src "libresoc.v:173259.18-173259.118" + wire width 64 $ternary$libresoc.v:173259$11897_Y + attribute \src "libresoc.v:173260.18-173260.118" + wire $ternary$libresoc.v:173260$11898_Y + attribute \src "libresoc.v:173261.18-173261.118" + wire width 2 $ternary$libresoc.v:173261$11899_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + wire \$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + wire width 5 \$100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + wire width 5 \$102 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + wire \$104 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + wire \$106 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + wire \$108 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" + wire width 3 \$110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" + wire width 3 \$112 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + wire \$114 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + wire \$116 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + wire \$118 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire \$14 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire \$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" + wire \$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" + wire width 3 \$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + wire \$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + wire width 3 \$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + wire width 3 \$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + wire \$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + wire \$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + wire \$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + wire \$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + wire \$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + wire \$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + wire width 3 \$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + wire \$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + wire \$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + wire \$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + wire width 5 \$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + wire \$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + wire \$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + wire \$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" + wire \$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" + wire \$58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" + wire width 3 \$60 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" + wire width 5 \$62 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" + wire \$64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" + wire width 3 \$66 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" + wire width 3 \$68 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + wire width 5 \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + wire \$70 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + wire \$72 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + wire \$74 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" + wire \$76 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" + wire width 64 \$78 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 64 \$80 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 64 \$82 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 64 \$84 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire \$86 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 2 \$88 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" + wire \$90 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" + wire \$92 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + wire width 5 \$94 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" + wire \$96 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + wire width 5 \$98 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:187" + wire \all_rd + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire \all_rd_dly + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire \all_rd_dly$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:192" + wire \all_rd_pulse + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + wire \all_rd_rise + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:196" + wire \alu_done + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire \alu_done_dly + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire \alu_done_dly$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + wire \alu_done_rise + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire \alu_l_q_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \alu_l_r_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \alu_l_r_alu$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \alu_l_s_alu + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:197" + wire \alu_pulse + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198" + wire width 3 \alu_pulsem + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \alu_shift_rot0_cr_a + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire \alu_shift_rot0_n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire \alu_shift_rot0_n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \alu_shift_rot0_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire \alu_shift_rot0_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire \alu_shift_rot0_p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \alu_shift_rot0_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \alu_shift_rot0_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \alu_shift_rot0_rc + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \alu_shift_rot0_sr_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \alu_shift_rot0_sr_op__fn_unit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \alu_shift_rot0_sr_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \alu_shift_rot0_sr_op__imm_data__data$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_shift_rot0_sr_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_shift_rot0_sr_op__imm_data__ok$next + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \alu_shift_rot0_sr_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \alu_shift_rot0_sr_op__input_carry$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_shift_rot0_sr_op__input_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_shift_rot0_sr_op__input_cr$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \alu_shift_rot0_sr_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \alu_shift_rot0_sr_op__insn$next + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \alu_shift_rot0_sr_op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \alu_shift_rot0_sr_op__insn_type$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_shift_rot0_sr_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_shift_rot0_sr_op__is_32bit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_shift_rot0_sr_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_shift_rot0_sr_op__is_signed$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_shift_rot0_sr_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_shift_rot0_sr_op__oe__oe$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_shift_rot0_sr_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_shift_rot0_sr_op__oe__ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_shift_rot0_sr_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_shift_rot0_sr_op__output_carry$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_shift_rot0_sr_op__output_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_shift_rot0_sr_op__output_cr$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_shift_rot0_sr_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_shift_rot0_sr_op__rc__ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_shift_rot0_sr_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_shift_rot0_sr_op__rc__rc$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_shift_rot0_sr_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_shift_rot0_sr_op__write_cr0$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \alu_shift_rot0_xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 \alu_shift_rot0_xer_ca$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \alu_shift_rot0_xer_so + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire \alui_l_q_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \alui_l_r_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \alui_l_r_alui$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \alui_l_s_alui + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 36 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 35 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 31 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" + wire output 18 \cu_busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:108" + wire \cu_done_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:104" + wire \cu_go_die_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" + wire input 17 \cu_issue_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 5 input 21 \cu_rd__go_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 5 output 20 \cu_rd__rel_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" + wire width 5 input 19 \cu_rdmaskn_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:102" + wire \cu_shadown_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 input 29 \cu_wr__go_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 output 28 \cu_wr__rel_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:97" + wire width 3 \cu_wrmask_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 64 \data_r0__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 64 \data_r0__o$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r0__o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r0__o_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 4 \data_r1__cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 4 \data_r1__cr_a$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r1__cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r1__cr_a_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 2 \data_r2__xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 2 \data_r2__xer_ca$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r2__xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r2__xer_ca_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 30 \dest1_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 4 output 32 \dest2_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 2 output 34 \dest3_o + attribute \src "libresoc.v:172587.7-172587.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 27 \o_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire \opc_l_q_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \opc_l_r_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \opc_l_r_opc$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \opc_l_s_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \opc_l_s_opc$next + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 2 \oper_i_alu_shift_rot0__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 3 \oper_i_alu_shift_rot0__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 4 \oper_i_alu_shift_rot0__imm_data__ok + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 10 \oper_i_alu_shift_rot0__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \oper_i_alu_shift_rot0__input_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 16 \oper_i_alu_shift_rot0__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \oper_i_alu_shift_rot0__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \oper_i_alu_shift_rot0__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 15 \oper_i_alu_shift_rot0__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 7 \oper_i_alu_shift_rot0__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \oper_i_alu_shift_rot0__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 11 \oper_i_alu_shift_rot0__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \oper_i_alu_shift_rot0__output_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 6 \oper_i_alu_shift_rot0__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 5 \oper_i_alu_shift_rot0__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \oper_i_alu_shift_rot0__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" + wire width 3 \prev_wr_go + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" + wire width 3 \prev_wr_go$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212" + wire \req_done + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 3 \req_l_q_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 3 \req_l_r_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 3 \req_l_r_req$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 3 \req_l_s_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 3 \req_l_s_req$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226" + wire \reset + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:229" + wire width 5 \reset_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:228" + wire width 3 \reset_w + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire \rok_l_q_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \rok_l_r_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \rok_l_r_rdok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \rok_l_s_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \rok_l_s_rdok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \rst_l_r_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \rst_l_r_rst$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \rst_l_s_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \rst_l_s_rst$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227" + wire \rst_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 22 \src1_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 23 \src2_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 24 \src3_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire input 25 \src4_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 2 input 26 \src5_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 5 \src_l_q_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 5 \src_l_r_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 5 \src_l_r_src$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 5 \src_l_s_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 5 \src_l_s_src$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:166" + wire width 64 \src_or_imm + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 64 \src_r0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 64 \src_r0$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 64 \src_r1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 64 \src_r1$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 64 \src_r2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 64 \src_r2$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire \src_r3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire \src_r3$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 2 \src_r4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 2 \src_r4$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:167" + wire \src_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" + wire \wr_any + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 33 \xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + cell $and $and$libresoc.v:173210$11848 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \$98 + connect \B \$100 + connect \Y $and$libresoc.v:173210$11848_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + cell $and $and$libresoc.v:173211$11849 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_busy_o + connect \B \cu_shadown_i + connect \Y $and$libresoc.v:173211$11849_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + cell $and $and$libresoc.v:173212$11850 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_busy_o + connect \B \cu_shadown_i + connect \Y $and$libresoc.v:173212$11850_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + cell $and $and$libresoc.v:173213$11851 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_busy_o + connect \B \cu_shadown_i + connect \Y $and$libresoc.v:173213$11851_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $and $and$libresoc.v:173214$11852 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$2 + connect \B \$4 + connect \Y $and$libresoc.v:173214$11852_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" + cell $and $and$libresoc.v:173215$11853 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \req_l_q_req + connect \B { \$104 \$106 \$108 } + connect \Y $and$libresoc.v:173215$11853_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" + cell $and $and$libresoc.v:173216$11854 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \$110 + connect \B \cu_wrmask_o + connect \Y $and$libresoc.v:173216$11854_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + cell $and $and$libresoc.v:173217$11855 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_wr__go_i [0] + connect \B \cu_busy_o + connect \Y $and$libresoc.v:173217$11855_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + cell $and $and$libresoc.v:173218$11856 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_wr__go_i [1] + connect \B \cu_busy_o + connect \Y $and$libresoc.v:173218$11856_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + cell $and $and$libresoc.v:173219$11857 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_wr__go_i [2] + connect \B \cu_busy_o + connect \Y $and$libresoc.v:173219$11857_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $and$libresoc.v:173221$11859 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \all_rd + connect \B \$12 + connect \Y $and$libresoc.v:173221$11859_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $and$libresoc.v:173223$11861 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_done + connect \B \$16 + connect \Y $and$libresoc.v:173223$11861_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" + cell $and $and$libresoc.v:173224$11862 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \cu_wr__go_i + connect \B { \cu_busy_o \cu_busy_o \cu_busy_o } + connect \Y $and$libresoc.v:173224$11862_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $and $and$libresoc.v:173226$11864 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \cu_wr__rel_o + connect \B \$24 + connect \Y $and$libresoc.v:173226$11864_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" + cell $and $and$libresoc.v:173229$11867 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_busy_o + connect \B \rok_l_q_rdok + connect \Y $and$libresoc.v:173229$11867_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $and $and$libresoc.v:173230$11868 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_busy_o + connect \B \$22 + connect \Y $and$libresoc.v:173230$11868_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + cell $and $and$libresoc.v:173235$11873 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_any + connect \B \$38 + connect \Y $and$libresoc.v:173235$11873_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + cell $and $and$libresoc.v:173236$11874 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \req_l_q_req + connect \B \cu_wrmask_o + connect \Y $and$libresoc.v:173236$11874_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + cell $and $and$libresoc.v:173238$11876 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$40 + connect \B \$44 + connect \Y $and$libresoc.v:173238$11876_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + cell $and $and$libresoc.v:173240$11878 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$48 + connect \B \alu_shift_rot0_n_ready_i + connect \Y $and$libresoc.v:173240$11878_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + cell $and $and$libresoc.v:173241$11879 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$50 + connect \B \alu_shift_rot0_n_valid_o + connect \Y $and$libresoc.v:173241$11879_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + cell $and $and$libresoc.v:173242$11880 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$52 + connect \B \cu_busy_o + connect \Y $and$libresoc.v:173242$11880_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" + cell $and $and$libresoc.v:173248$11886 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_shift_rot0_n_valid_o + connect \B \cu_busy_o + connect \Y $and$libresoc.v:173248$11886_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" + cell $and $and$libresoc.v:173249$11887 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \alu_pulsem + connect \B \cu_wrmask_o + connect \Y $and$libresoc.v:173249$11887_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + cell $and $and$libresoc.v:173251$11889 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \o_ok + connect \B \cu_busy_o + connect \Y $and$libresoc.v:173251$11889_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + cell $and $and$libresoc.v:173252$11890 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cr_a_ok + connect \B \cu_busy_o + connect \Y $and$libresoc.v:173252$11890_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + cell $and $and$libresoc.v:173253$11891 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \xer_ca_ok + connect \B \cu_busy_o + connect \Y $and$libresoc.v:173253$11891_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" + cell $and $and$libresoc.v:173263$11901 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_shift_rot0_p_ready_o + connect \B \alui_l_q_alui + connect \Y $and$libresoc.v:173263$11901_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" + cell $and $and$libresoc.v:173264$11902 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_shift_rot0_n_valid_o + connect \B \alu_l_q_alu + connect \Y $and$libresoc.v:173264$11902_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + cell $and $and$libresoc.v:173265$11903 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \src_l_q_src + connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } + connect \Y $and$libresoc.v:173265$11903_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + cell $and $and$libresoc.v:173267$11905 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \$94 + connect \B { 3'111 \$96 1'1 } + connect \Y $and$libresoc.v:173267$11905_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + cell $eq $eq$libresoc.v:173237$11875 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$42 + connect \B 1'0 + connect \Y $eq$libresoc.v:173237$11875_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + cell $eq $eq$libresoc.v:173239$11877 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_wrmask_o + connect \B 1'0 + connect \Y $eq$libresoc.v:173239$11877_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + cell $not $not$libresoc.v:173209$11847 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \cu_rdmaskn_i + connect \Y $not$libresoc.v:173209$11847_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $not$libresoc.v:173220$11858 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \all_rd_dly + connect \Y $not$libresoc.v:173220$11858_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $not$libresoc.v:173222$11860 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_done_dly + connect \Y $not$libresoc.v:173222$11860_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $not $not$libresoc.v:173225$11863 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \cu_wrmask_o + connect \Y $not$libresoc.v:173225$11863_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $not $not$libresoc.v:173228$11866 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$23 + connect \Y $not$libresoc.v:173228$11866_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + cell $not $not$libresoc.v:173234$11872 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_shift_rot0_n_ready_i + connect \Y $not$libresoc.v:173234$11872_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $not $not$libresoc.v:173245$11883 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \cu_rd__rel_o + connect \Y $not$libresoc.v:173245$11883_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" + cell $not $not$libresoc.v:173266$11904 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_shift_rot0_sr_op__imm_data__ok + connect \Y $not$libresoc.v:173266$11904_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $or $or$libresoc.v:173233$11871 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$32 + connect \B \$34 + connect \Y $or$libresoc.v:173233$11871_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" + cell $or $or$libresoc.v:173243$11881 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \req_done + connect \B \cu_go_die_i + connect \Y $or$libresoc.v:173243$11881_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" + cell $or $or$libresoc.v:173244$11882 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_issue_i + connect \B \cu_go_die_i + connect \Y $or$libresoc.v:173244$11882_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" + cell $or $or$libresoc.v:173246$11884 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \cu_wr__go_i + connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } + connect \Y $or$libresoc.v:173246$11884_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" + cell $or $or$libresoc.v:173247$11885 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \cu_rd__go_i + connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } + connect \Y $or$libresoc.v:173247$11885_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" + cell $or $or$libresoc.v:173250$11888 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \reset_w + connect \B \prev_wr_go + connect \Y $or$libresoc.v:173250$11888_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $or $or$libresoc.v:173256$11894 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \$5 + connect \B \cu_rd__go_i + connect \Y $or$libresoc.v:173256$11894_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $reduce_and $reduce_and$libresoc.v:173262$11900 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \$7 + connect \Y $reduce_and$libresoc.v:173262$11900_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $reduce_or $reduce_or$libresoc.v:173227$11865 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \$26 + connect \Y $reduce_or$libresoc.v:173227$11865_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $reduce_or $reduce_or$libresoc.v:173231$11869 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \cu_wr__go_i + connect \Y $reduce_or$libresoc.v:173231$11869_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $reduce_or $reduce_or$libresoc.v:173232$11870 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \prev_wr_go + connect \Y $reduce_or$libresoc.v:173232$11870_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" + cell $mux $ternary$libresoc.v:173254$11892 + parameter \WIDTH 1 + connect \A \src_l_q_src [1] + connect \B \opc_l_q_opc + connect \S \alu_shift_rot0_sr_op__imm_data__ok + connect \Y $ternary$libresoc.v:173254$11892_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" + cell $mux $ternary$libresoc.v:173255$11893 + parameter \WIDTH 64 + connect \A \src2_i + connect \B \alu_shift_rot0_sr_op__imm_data__data + connect \S \alu_shift_rot0_sr_op__imm_data__ok + connect \Y $ternary$libresoc.v:173255$11893_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $ternary$libresoc.v:173257$11895 + parameter \WIDTH 64 + connect \A \src_r0 + connect \B \src1_i + connect \S \src_l_q_src [0] + connect \Y $ternary$libresoc.v:173257$11895_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $ternary$libresoc.v:173258$11896 + parameter \WIDTH 64 + connect \A \src_r1 + connect \B \src_or_imm + connect \S \src_sel + connect \Y $ternary$libresoc.v:173258$11896_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $ternary$libresoc.v:173259$11897 + parameter \WIDTH 64 + connect \A \src_r2 + connect \B \src3_i + connect \S \src_l_q_src [2] + connect \Y $ternary$libresoc.v:173259$11897_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $ternary$libresoc.v:173260$11898 + parameter \WIDTH 1 + connect \A \src_r3 + connect \B \src4_i + connect \S \src_l_q_src [3] + connect \Y $ternary$libresoc.v:173260$11898_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $ternary$libresoc.v:173261$11899 + parameter \WIDTH 2 + connect \A \src_r4 + connect \B \src5_i + connect \S \src_l_q_src [4] + connect \Y $ternary$libresoc.v:173261$11899_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:173352.15-173358.4" + cell \alu_l$122 \alu_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_alu \alu_l_q_alu + connect \r_alu \alu_l_r_alu + connect \s_alu \alu_l_s_alu + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:173359.18-173393.4" + cell \alu_shift_rot0 \alu_shift_rot0 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cr_a \alu_shift_rot0_cr_a + connect \cr_a_ok \cr_a_ok + connect \n_ready_i \alu_shift_rot0_n_ready_i + connect \n_valid_o \alu_shift_rot0_n_valid_o + connect \o \alu_shift_rot0_o + connect \o_ok \o_ok + connect \p_ready_o \alu_shift_rot0_p_ready_o + connect \p_valid_i \alu_shift_rot0_p_valid_i + connect \ra \alu_shift_rot0_ra + connect \rb \alu_shift_rot0_rb + connect \rc \alu_shift_rot0_rc + connect \sr_op__fn_unit \alu_shift_rot0_sr_op__fn_unit + connect \sr_op__imm_data__data \alu_shift_rot0_sr_op__imm_data__data + connect \sr_op__imm_data__ok \alu_shift_rot0_sr_op__imm_data__ok + connect \sr_op__input_carry \alu_shift_rot0_sr_op__input_carry + connect \sr_op__input_cr \alu_shift_rot0_sr_op__input_cr + connect \sr_op__insn \alu_shift_rot0_sr_op__insn + connect \sr_op__insn_type \alu_shift_rot0_sr_op__insn_type + connect \sr_op__is_32bit \alu_shift_rot0_sr_op__is_32bit + connect \sr_op__is_signed \alu_shift_rot0_sr_op__is_signed + connect \sr_op__oe__oe \alu_shift_rot0_sr_op__oe__oe + connect \sr_op__oe__ok \alu_shift_rot0_sr_op__oe__ok + connect \sr_op__output_carry \alu_shift_rot0_sr_op__output_carry + connect \sr_op__output_cr \alu_shift_rot0_sr_op__output_cr + connect \sr_op__rc__ok \alu_shift_rot0_sr_op__rc__ok + connect \sr_op__rc__rc \alu_shift_rot0_sr_op__rc__rc + connect \sr_op__write_cr0 \alu_shift_rot0_sr_op__write_cr0 + connect \xer_ca \alu_shift_rot0_xer_ca + connect \xer_ca$1 \alu_shift_rot0_xer_ca$1 + connect \xer_ca_ok \xer_ca_ok + connect \xer_so \alu_shift_rot0_xer_so + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:173394.16-173400.4" + cell \alui_l$121 \alui_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_alui \alui_l_q_alui + connect \r_alui \alui_l_r_alui + connect \s_alui \alui_l_s_alui + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:173401.15-173407.4" + cell \opc_l$117 \opc_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_opc \opc_l_q_opc + connect \r_opc \opc_l_r_opc + connect \s_opc \opc_l_s_opc + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:173408.15-173414.4" + cell \req_l$118 \req_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_req \req_l_q_req + connect \r_req \req_l_r_req + connect \s_req \req_l_s_req + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:173415.15-173421.4" + cell \rok_l$120 \rok_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_rdok \rok_l_q_rdok + connect \r_rdok \rok_l_r_rdok + connect \s_rdok \rok_l_s_rdok + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:173422.15-173427.4" + cell \rst_l$119 \rst_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \r_rst \rst_l_r_rst + connect \s_rst \rst_l_s_rst + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:173428.15-173434.4" + cell \src_l$116 \src_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_src \src_l_q_src + connect \r_src \src_l_r_src + connect \s_src \src_l_s_src + end + attribute \src "libresoc.v:172587.7-172587.20" + process $proc$libresoc.v:172587$12069 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:172709.7-172709.24" + process $proc$libresoc.v:172709$12070 + assign { } { } + assign $1\all_rd_dly[0:0] 1'0 + sync always + sync init + update \all_rd_dly $1\all_rd_dly[0:0] + end + attribute \src "libresoc.v:172719.7-172719.26" + process $proc$libresoc.v:172719$12071 + assign { } { } + assign $1\alu_done_dly[0:0] 1'0 + sync always + sync init + update \alu_done_dly $1\alu_done_dly[0:0] + end + attribute \src "libresoc.v:172727.7-172727.25" + process $proc$libresoc.v:172727$12072 + assign { } { } + assign $1\alu_l_r_alu[0:0] 1'1 + sync always + sync init + update \alu_l_r_alu $1\alu_l_r_alu[0:0] + end + attribute \src "libresoc.v:172768.14-172768.53" + process $proc$libresoc.v:172768$12073 + assign { } { } + assign $1\alu_shift_rot0_sr_op__fn_unit[11:0] 12'000000000000 + sync always + sync init + update \alu_shift_rot0_sr_op__fn_unit $1\alu_shift_rot0_sr_op__fn_unit[11:0] + end + attribute \src "libresoc.v:172772.14-172772.73" + process $proc$libresoc.v:172772$12074 + assign { } { } + assign $1\alu_shift_rot0_sr_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \alu_shift_rot0_sr_op__imm_data__data $1\alu_shift_rot0_sr_op__imm_data__data[63:0] + end + attribute \src "libresoc.v:172776.7-172776.48" + process $proc$libresoc.v:172776$12075 + assign { } { } + assign $1\alu_shift_rot0_sr_op__imm_data__ok[0:0] 1'0 + sync always + sync init + update \alu_shift_rot0_sr_op__imm_data__ok $1\alu_shift_rot0_sr_op__imm_data__ok[0:0] + end + attribute \src "libresoc.v:172784.13-172784.53" + process $proc$libresoc.v:172784$12076 + assign { } { } + assign $1\alu_shift_rot0_sr_op__input_carry[1:0] 2'00 + sync always + sync init + update \alu_shift_rot0_sr_op__input_carry $1\alu_shift_rot0_sr_op__input_carry[1:0] + end + attribute \src "libresoc.v:172788.7-172788.44" + process $proc$libresoc.v:172788$12077 + assign { } { } + assign $1\alu_shift_rot0_sr_op__input_cr[0:0] 1'0 + sync always + sync init + update \alu_shift_rot0_sr_op__input_cr $1\alu_shift_rot0_sr_op__input_cr[0:0] + end + attribute \src "libresoc.v:172792.14-172792.48" + process $proc$libresoc.v:172792$12078 + assign { } { } + assign $1\alu_shift_rot0_sr_op__insn[31:0] 0 + sync always + sync init + update \alu_shift_rot0_sr_op__insn $1\alu_shift_rot0_sr_op__insn[31:0] + end + attribute \src "libresoc.v:172870.13-172870.52" + process $proc$libresoc.v:172870$12079 + assign { } { } + assign $1\alu_shift_rot0_sr_op__insn_type[6:0] 7'0000000 + sync always + sync init + update \alu_shift_rot0_sr_op__insn_type $1\alu_shift_rot0_sr_op__insn_type[6:0] + end + attribute \src "libresoc.v:172874.7-172874.44" + process $proc$libresoc.v:172874$12080 + assign { } { } + assign $1\alu_shift_rot0_sr_op__is_32bit[0:0] 1'0 + sync always + sync init + update \alu_shift_rot0_sr_op__is_32bit $1\alu_shift_rot0_sr_op__is_32bit[0:0] + end + attribute \src "libresoc.v:172878.7-172878.45" + process $proc$libresoc.v:172878$12081 + assign { } { } + assign $1\alu_shift_rot0_sr_op__is_signed[0:0] 1'0 + sync always + sync init + update \alu_shift_rot0_sr_op__is_signed $1\alu_shift_rot0_sr_op__is_signed[0:0] + end + attribute \src "libresoc.v:172882.7-172882.42" + process $proc$libresoc.v:172882$12082 + assign { } { } + assign $1\alu_shift_rot0_sr_op__oe__oe[0:0] 1'0 + sync always + sync init + update \alu_shift_rot0_sr_op__oe__oe $1\alu_shift_rot0_sr_op__oe__oe[0:0] + end + attribute \src "libresoc.v:172886.7-172886.42" + process $proc$libresoc.v:172886$12083 + assign { } { } + assign $1\alu_shift_rot0_sr_op__oe__ok[0:0] 1'0 + sync always + sync init + update \alu_shift_rot0_sr_op__oe__ok $1\alu_shift_rot0_sr_op__oe__ok[0:0] + end + attribute \src "libresoc.v:172890.7-172890.48" + process $proc$libresoc.v:172890$12084 + assign { } { } + assign $1\alu_shift_rot0_sr_op__output_carry[0:0] 1'0 + sync always + sync init + update \alu_shift_rot0_sr_op__output_carry $1\alu_shift_rot0_sr_op__output_carry[0:0] + end + attribute \src "libresoc.v:172894.7-172894.45" + process $proc$libresoc.v:172894$12085 + assign { } { } + assign $1\alu_shift_rot0_sr_op__output_cr[0:0] 1'0 + sync always + sync init + update \alu_shift_rot0_sr_op__output_cr $1\alu_shift_rot0_sr_op__output_cr[0:0] + end + attribute \src "libresoc.v:172898.7-172898.42" + process $proc$libresoc.v:172898$12086 + assign { } { } + assign $1\alu_shift_rot0_sr_op__rc__ok[0:0] 1'0 + sync always + sync init + update \alu_shift_rot0_sr_op__rc__ok $1\alu_shift_rot0_sr_op__rc__ok[0:0] + end + attribute \src "libresoc.v:172902.7-172902.42" + process $proc$libresoc.v:172902$12087 + assign { } { } + assign $1\alu_shift_rot0_sr_op__rc__rc[0:0] 1'0 + sync always + sync init + update \alu_shift_rot0_sr_op__rc__rc $1\alu_shift_rot0_sr_op__rc__rc[0:0] + end + attribute \src "libresoc.v:172906.7-172906.45" + process $proc$libresoc.v:172906$12088 + assign { } { } + assign $1\alu_shift_rot0_sr_op__write_cr0[0:0] 1'0 + sync always + sync init + update \alu_shift_rot0_sr_op__write_cr0 $1\alu_shift_rot0_sr_op__write_cr0[0:0] + end + attribute \src "libresoc.v:172918.7-172918.27" + process $proc$libresoc.v:172918$12089 + assign { } { } + assign $1\alui_l_r_alui[0:0] 1'1 + sync always + sync init + update \alui_l_r_alui $1\alui_l_r_alui[0:0] + end + attribute \src "libresoc.v:172952.14-172952.47" + process $proc$libresoc.v:172952$12090 + assign { } { } + assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \data_r0__o $1\data_r0__o[63:0] + end + attribute \src "libresoc.v:172956.7-172956.27" + process $proc$libresoc.v:172956$12091 + assign { } { } + assign $1\data_r0__o_ok[0:0] 1'0 + sync always + sync init + update \data_r0__o_ok $1\data_r0__o_ok[0:0] + end + attribute \src "libresoc.v:172960.13-172960.33" + process $proc$libresoc.v:172960$12092 + assign { } { } + assign $1\data_r1__cr_a[3:0] 4'0000 + sync always + sync init + update \data_r1__cr_a $1\data_r1__cr_a[3:0] + end + attribute \src "libresoc.v:172964.7-172964.30" + process $proc$libresoc.v:172964$12093 + assign { } { } + assign $1\data_r1__cr_a_ok[0:0] 1'0 + sync always + sync init + update \data_r1__cr_a_ok $1\data_r1__cr_a_ok[0:0] + end + attribute \src "libresoc.v:172968.13-172968.35" + process $proc$libresoc.v:172968$12094 + assign { } { } + assign $1\data_r2__xer_ca[1:0] 2'00 + sync always + sync init + update \data_r2__xer_ca $1\data_r2__xer_ca[1:0] + end + attribute \src "libresoc.v:172972.7-172972.32" + process $proc$libresoc.v:172972$12095 + assign { } { } + assign $1\data_r2__xer_ca_ok[0:0] 1'0 + sync always + sync init + update \data_r2__xer_ca_ok $1\data_r2__xer_ca_ok[0:0] + end + attribute \src "libresoc.v:172989.7-172989.25" + process $proc$libresoc.v:172989$12096 + assign { } { } + assign $1\opc_l_r_opc[0:0] 1'1 + sync always + sync init + update \opc_l_r_opc $1\opc_l_r_opc[0:0] + end + attribute \src "libresoc.v:172993.7-172993.25" + process $proc$libresoc.v:172993$12097 + assign { } { } + assign $1\opc_l_s_opc[0:0] 1'0 + sync always + sync init + update \opc_l_s_opc $1\opc_l_s_opc[0:0] + end + attribute \src "libresoc.v:173120.13-173120.30" + process $proc$libresoc.v:173120$12098 + assign { } { } + assign $1\prev_wr_go[2:0] 3'000 + sync always + sync init + update \prev_wr_go $1\prev_wr_go[2:0] + end + attribute \src "libresoc.v:173128.13-173128.31" + process $proc$libresoc.v:173128$12099 + assign { } { } + assign $1\req_l_r_req[2:0] 3'111 + sync always + sync init + update \req_l_r_req $1\req_l_r_req[2:0] + end + attribute \src "libresoc.v:173132.13-173132.31" + process $proc$libresoc.v:173132$12100 + assign { } { } + assign $1\req_l_s_req[2:0] 3'000 + sync always + sync init + update \req_l_s_req $1\req_l_s_req[2:0] + end + attribute \src "libresoc.v:173144.7-173144.26" + process $proc$libresoc.v:173144$12101 + assign { } { } + assign $1\rok_l_r_rdok[0:0] 1'1 + sync always + sync init + update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] + end + attribute \src "libresoc.v:173148.7-173148.26" + process $proc$libresoc.v:173148$12102 + assign { } { } + assign $1\rok_l_s_rdok[0:0] 1'0 + sync always + sync init + update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] + end + attribute \src "libresoc.v:173152.7-173152.25" + process $proc$libresoc.v:173152$12103 + assign { } { } + assign $1\rst_l_r_rst[0:0] 1'1 + sync always + sync init + update \rst_l_r_rst $1\rst_l_r_rst[0:0] + end + attribute \src "libresoc.v:173156.7-173156.25" + process $proc$libresoc.v:173156$12104 + assign { } { } + assign $1\rst_l_s_rst[0:0] 1'0 + sync always + sync init + update \rst_l_s_rst $1\rst_l_s_rst[0:0] + end + attribute \src "libresoc.v:173174.13-173174.32" + process $proc$libresoc.v:173174$12105 + assign { } { } + assign $1\src_l_r_src[4:0] 5'11111 + sync always + sync init + update \src_l_r_src $1\src_l_r_src[4:0] + end + attribute \src "libresoc.v:173178.13-173178.32" + process $proc$libresoc.v:173178$12106 + assign { } { } + assign $1\src_l_s_src[4:0] 5'00000 + sync always + sync init + update \src_l_s_src $1\src_l_s_src[4:0] + end + attribute \src "libresoc.v:173184.14-173184.43" + process $proc$libresoc.v:173184$12107 + assign { } { } + assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \src_r0 $1\src_r0[63:0] + end + attribute \src "libresoc.v:173188.14-173188.43" + process $proc$libresoc.v:173188$12108 + assign { } { } + assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \src_r1 $1\src_r1[63:0] + end + attribute \src "libresoc.v:173192.14-173192.43" + process $proc$libresoc.v:173192$12109 + assign { } { } + assign $1\src_r2[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \src_r2 $1\src_r2[63:0] + end + attribute \src "libresoc.v:173196.7-173196.20" + process $proc$libresoc.v:173196$12110 + assign { } { } + assign $1\src_r3[0:0] 1'0 + sync always + sync init + update \src_r3 $1\src_r3[0:0] + end + attribute \src "libresoc.v:173200.13-173200.26" + process $proc$libresoc.v:173200$12111 + assign { } { } + assign $1\src_r4[1:0] 2'00 + sync always + sync init + update \src_r4 $1\src_r4[1:0] + end + attribute \src "libresoc.v:173268.3-173269.39" + process $proc$libresoc.v:173268$11906 + assign { } { } + assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next + sync posedge \coresync_clk + update \alu_l_r_alu $0\alu_l_r_alu[0:0] + end + attribute \src "libresoc.v:173270.3-173271.43" + process $proc$libresoc.v:173270$11907 + assign { } { } + assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next + sync posedge \coresync_clk + update \alui_l_r_alui $0\alui_l_r_alui[0:0] + end + attribute \src "libresoc.v:173272.3-173273.29" + process $proc$libresoc.v:173272$11908 + assign { } { } + assign $0\src_r4[1:0] \src_r4$next + sync posedge \coresync_clk + update \src_r4 $0\src_r4[1:0] + end + attribute \src "libresoc.v:173274.3-173275.29" + process $proc$libresoc.v:173274$11909 + assign { } { } + assign $0\src_r3[0:0] \src_r3$next + sync posedge \coresync_clk + update \src_r3 $0\src_r3[0:0] + end + attribute \src "libresoc.v:173276.3-173277.29" + process $proc$libresoc.v:173276$11910 + assign { } { } + assign $0\src_r2[63:0] \src_r2$next + sync posedge \coresync_clk + update \src_r2 $0\src_r2[63:0] + end + attribute \src "libresoc.v:173278.3-173279.29" + process $proc$libresoc.v:173278$11911 + assign { } { } + assign $0\src_r1[63:0] \src_r1$next + sync posedge \coresync_clk + update \src_r1 $0\src_r1[63:0] + end + attribute \src "libresoc.v:173280.3-173281.29" + process $proc$libresoc.v:173280$11912 + assign { } { } + assign $0\src_r0[63:0] \src_r0$next + sync posedge \coresync_clk + update \src_r0 $0\src_r0[63:0] + end + attribute \src "libresoc.v:173282.3-173283.47" + process $proc$libresoc.v:173282$11913 + assign { } { } + assign $0\data_r2__xer_ca[1:0] \data_r2__xer_ca$next + sync posedge \coresync_clk + update \data_r2__xer_ca $0\data_r2__xer_ca[1:0] + end + attribute \src "libresoc.v:173284.3-173285.53" + process $proc$libresoc.v:173284$11914 + assign { } { } + assign $0\data_r2__xer_ca_ok[0:0] \data_r2__xer_ca_ok$next + sync posedge \coresync_clk + update \data_r2__xer_ca_ok $0\data_r2__xer_ca_ok[0:0] + end + attribute \src "libresoc.v:173286.3-173287.43" + process $proc$libresoc.v:173286$11915 + assign { } { } + assign $0\data_r1__cr_a[3:0] \data_r1__cr_a$next + sync posedge \coresync_clk + update \data_r1__cr_a $0\data_r1__cr_a[3:0] + end + attribute \src "libresoc.v:173288.3-173289.49" + process $proc$libresoc.v:173288$11916 + assign { } { } + assign $0\data_r1__cr_a_ok[0:0] \data_r1__cr_a_ok$next + sync posedge \coresync_clk + update \data_r1__cr_a_ok $0\data_r1__cr_a_ok[0:0] + end + attribute \src "libresoc.v:173290.3-173291.37" + process $proc$libresoc.v:173290$11917 + assign { } { } + assign $0\data_r0__o[63:0] \data_r0__o$next + sync posedge \coresync_clk + update \data_r0__o $0\data_r0__o[63:0] + end + attribute \src "libresoc.v:173292.3-173293.43" + process $proc$libresoc.v:173292$11918 + assign { } { } + assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next + sync posedge \coresync_clk + update \data_r0__o_ok $0\data_r0__o_ok[0:0] + end + attribute \src "libresoc.v:173294.3-173295.79" + process $proc$libresoc.v:173294$11919 + assign { } { } + assign $0\alu_shift_rot0_sr_op__insn_type[6:0] \alu_shift_rot0_sr_op__insn_type$next + sync posedge \coresync_clk + update \alu_shift_rot0_sr_op__insn_type $0\alu_shift_rot0_sr_op__insn_type[6:0] + end + attribute \src "libresoc.v:173296.3-173297.75" + process $proc$libresoc.v:173296$11920 + assign { } { } + assign $0\alu_shift_rot0_sr_op__fn_unit[11:0] \alu_shift_rot0_sr_op__fn_unit$next + sync posedge \coresync_clk + update \alu_shift_rot0_sr_op__fn_unit $0\alu_shift_rot0_sr_op__fn_unit[11:0] + end + attribute \src "libresoc.v:173298.3-173299.89" + process $proc$libresoc.v:173298$11921 + assign { } { } + assign $0\alu_shift_rot0_sr_op__imm_data__data[63:0] \alu_shift_rot0_sr_op__imm_data__data$next + sync posedge \coresync_clk + update \alu_shift_rot0_sr_op__imm_data__data $0\alu_shift_rot0_sr_op__imm_data__data[63:0] + end + attribute \src "libresoc.v:173300.3-173301.85" + process $proc$libresoc.v:173300$11922 + assign { } { } + assign $0\alu_shift_rot0_sr_op__imm_data__ok[0:0] \alu_shift_rot0_sr_op__imm_data__ok$next + sync posedge \coresync_clk + update \alu_shift_rot0_sr_op__imm_data__ok $0\alu_shift_rot0_sr_op__imm_data__ok[0:0] + end + attribute \src "libresoc.v:173302.3-173303.73" + process $proc$libresoc.v:173302$11923 + assign { } { } + assign $0\alu_shift_rot0_sr_op__rc__rc[0:0] \alu_shift_rot0_sr_op__rc__rc$next + sync posedge \coresync_clk + update \alu_shift_rot0_sr_op__rc__rc $0\alu_shift_rot0_sr_op__rc__rc[0:0] + end + attribute \src "libresoc.v:173304.3-173305.73" + process $proc$libresoc.v:173304$11924 + assign { } { } + assign $0\alu_shift_rot0_sr_op__rc__ok[0:0] \alu_shift_rot0_sr_op__rc__ok$next + sync posedge \coresync_clk + update \alu_shift_rot0_sr_op__rc__ok $0\alu_shift_rot0_sr_op__rc__ok[0:0] + end + attribute \src "libresoc.v:173306.3-173307.73" + process $proc$libresoc.v:173306$11925 + assign { } { } + assign $0\alu_shift_rot0_sr_op__oe__oe[0:0] \alu_shift_rot0_sr_op__oe__oe$next + sync posedge \coresync_clk + update \alu_shift_rot0_sr_op__oe__oe $0\alu_shift_rot0_sr_op__oe__oe[0:0] + end + attribute \src "libresoc.v:173308.3-173309.73" + process $proc$libresoc.v:173308$11926 + assign { } { } + assign $0\alu_shift_rot0_sr_op__oe__ok[0:0] \alu_shift_rot0_sr_op__oe__ok$next + sync posedge \coresync_clk + update \alu_shift_rot0_sr_op__oe__ok $0\alu_shift_rot0_sr_op__oe__ok[0:0] + end + attribute \src "libresoc.v:173310.3-173311.79" + process $proc$libresoc.v:173310$11927 + assign { } { } + assign $0\alu_shift_rot0_sr_op__write_cr0[0:0] \alu_shift_rot0_sr_op__write_cr0$next + sync posedge \coresync_clk + update \alu_shift_rot0_sr_op__write_cr0 $0\alu_shift_rot0_sr_op__write_cr0[0:0] + end + attribute \src "libresoc.v:173312.3-173313.83" + process $proc$libresoc.v:173312$11928 + assign { } { } + assign $0\alu_shift_rot0_sr_op__input_carry[1:0] \alu_shift_rot0_sr_op__input_carry$next + sync posedge \coresync_clk + update \alu_shift_rot0_sr_op__input_carry $0\alu_shift_rot0_sr_op__input_carry[1:0] + end + attribute \src "libresoc.v:173314.3-173315.85" + process $proc$libresoc.v:173314$11929 + assign { } { } + assign $0\alu_shift_rot0_sr_op__output_carry[0:0] \alu_shift_rot0_sr_op__output_carry$next + sync posedge \coresync_clk + update \alu_shift_rot0_sr_op__output_carry $0\alu_shift_rot0_sr_op__output_carry[0:0] + end + attribute \src "libresoc.v:173316.3-173317.77" + process $proc$libresoc.v:173316$11930 + assign { } { } + assign $0\alu_shift_rot0_sr_op__input_cr[0:0] \alu_shift_rot0_sr_op__input_cr$next + sync posedge \coresync_clk + update \alu_shift_rot0_sr_op__input_cr $0\alu_shift_rot0_sr_op__input_cr[0:0] + end + attribute \src "libresoc.v:173318.3-173319.79" + process $proc$libresoc.v:173318$11931 + assign { } { } + assign $0\alu_shift_rot0_sr_op__output_cr[0:0] \alu_shift_rot0_sr_op__output_cr$next + sync posedge \coresync_clk + update \alu_shift_rot0_sr_op__output_cr $0\alu_shift_rot0_sr_op__output_cr[0:0] + end + attribute \src "libresoc.v:173320.3-173321.77" + process $proc$libresoc.v:173320$11932 + assign { } { } + assign $0\alu_shift_rot0_sr_op__is_32bit[0:0] \alu_shift_rot0_sr_op__is_32bit$next + sync posedge \coresync_clk + update \alu_shift_rot0_sr_op__is_32bit $0\alu_shift_rot0_sr_op__is_32bit[0:0] + end + attribute \src "libresoc.v:173322.3-173323.79" + process $proc$libresoc.v:173322$11933 + assign { } { } + assign $0\alu_shift_rot0_sr_op__is_signed[0:0] \alu_shift_rot0_sr_op__is_signed$next + sync posedge \coresync_clk + update \alu_shift_rot0_sr_op__is_signed $0\alu_shift_rot0_sr_op__is_signed[0:0] + end + attribute \src "libresoc.v:173324.3-173325.69" + process $proc$libresoc.v:173324$11934 + assign { } { } + assign $0\alu_shift_rot0_sr_op__insn[31:0] \alu_shift_rot0_sr_op__insn$next + sync posedge \coresync_clk + update \alu_shift_rot0_sr_op__insn $0\alu_shift_rot0_sr_op__insn[31:0] + end + attribute \src "libresoc.v:173326.3-173327.39" + process $proc$libresoc.v:173326$11935 + assign { } { } + assign $0\req_l_r_req[2:0] \req_l_r_req$next + sync posedge \coresync_clk + update \req_l_r_req $0\req_l_r_req[2:0] + end + attribute \src "libresoc.v:173328.3-173329.39" + process $proc$libresoc.v:173328$11936 + assign { } { } + assign $0\req_l_s_req[2:0] \req_l_s_req$next + sync posedge \coresync_clk + update \req_l_s_req $0\req_l_s_req[2:0] + end + attribute \src "libresoc.v:173330.3-173331.39" + process $proc$libresoc.v:173330$11937 + assign { } { } + assign $0\src_l_r_src[4:0] \src_l_r_src$next + sync posedge \coresync_clk + update \src_l_r_src $0\src_l_r_src[4:0] + end + attribute \src "libresoc.v:173332.3-173333.39" + process $proc$libresoc.v:173332$11938 + assign { } { } + assign $0\src_l_s_src[4:0] \src_l_s_src$next + sync posedge \coresync_clk + update \src_l_s_src $0\src_l_s_src[4:0] + end + attribute \src "libresoc.v:173334.3-173335.39" + process $proc$libresoc.v:173334$11939 + assign { } { } + assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next + sync posedge \coresync_clk + update \opc_l_r_opc $0\opc_l_r_opc[0:0] + end + attribute \src "libresoc.v:173336.3-173337.39" + process $proc$libresoc.v:173336$11940 + assign { } { } + assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next + sync posedge \coresync_clk + update \opc_l_s_opc $0\opc_l_s_opc[0:0] + end + attribute \src "libresoc.v:173338.3-173339.39" + process $proc$libresoc.v:173338$11941 + assign { } { } + assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next + sync posedge \coresync_clk + update \rst_l_r_rst $0\rst_l_r_rst[0:0] + end + attribute \src "libresoc.v:173340.3-173341.39" + process $proc$libresoc.v:173340$11942 + assign { } { } + assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next + sync posedge \coresync_clk + update \rst_l_s_rst $0\rst_l_s_rst[0:0] + end + attribute \src "libresoc.v:173342.3-173343.41" + process $proc$libresoc.v:173342$11943 + assign { } { } + assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next + sync posedge \coresync_clk + update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] + end + attribute \src "libresoc.v:173344.3-173345.41" + process $proc$libresoc.v:173344$11944 + assign { } { } + assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next + sync posedge \coresync_clk + update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] + end + attribute \src "libresoc.v:173346.3-173347.37" + process $proc$libresoc.v:173346$11945 + assign { } { } + assign $0\prev_wr_go[2:0] \prev_wr_go$next + sync posedge \coresync_clk + update \prev_wr_go $0\prev_wr_go[2:0] + end + attribute \src "libresoc.v:173348.3-173349.46" + process $proc$libresoc.v:173348$11946 + assign { } { } + assign $0\alu_done_dly[0:0] \alu_shift_rot0_n_valid_o + sync posedge \coresync_clk + update \alu_done_dly $0\alu_done_dly[0:0] + end + attribute \src "libresoc.v:173350.3-173351.25" + process $proc$libresoc.v:173350$11947 + assign { } { } + assign $0\all_rd_dly[0:0] \$10 + sync posedge \coresync_clk + update \all_rd_dly $0\all_rd_dly[0:0] + end + attribute \src "libresoc.v:173435.3-173444.6" + process $proc$libresoc.v:173435$11948 + assign { } { } + assign { } { } + assign $0\req_done[0:0] $1\req_done[0:0] + attribute \src "libresoc.v:173436.5-173436.29" + switch \initial + attribute \src "libresoc.v:173436.9-173436.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + switch \$54 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\req_done[0:0] 1'1 + case + assign $1\req_done[0:0] \$46 + end + sync always + update \req_done $0\req_done[0:0] + end + attribute \src "libresoc.v:173445.3-173453.6" + process $proc$libresoc.v:173445$11949 + assign { } { } + assign { } { } + assign $0\rok_l_s_rdok$next[0:0]$11950 $1\rok_l_s_rdok$next[0:0]$11951 + attribute \src "libresoc.v:173446.5-173446.29" + switch \initial + attribute \src "libresoc.v:173446.9-173446.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rok_l_s_rdok$next[0:0]$11951 1'0 + case + assign $1\rok_l_s_rdok$next[0:0]$11951 \cu_issue_i + end + sync always + update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$11950 + end + attribute \src "libresoc.v:173454.3-173462.6" + process $proc$libresoc.v:173454$11952 + assign { } { } + assign { } { } + assign $0\rok_l_r_rdok$next[0:0]$11953 $1\rok_l_r_rdok$next[0:0]$11954 + attribute \src "libresoc.v:173455.5-173455.29" + switch \initial + attribute \src "libresoc.v:173455.9-173455.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rok_l_r_rdok$next[0:0]$11954 1'1 + case + assign $1\rok_l_r_rdok$next[0:0]$11954 \$64 + end + sync always + update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$11953 + end + attribute \src "libresoc.v:173463.3-173471.6" + process $proc$libresoc.v:173463$11955 + assign { } { } + assign { } { } + assign $0\rst_l_s_rst$next[0:0]$11956 $1\rst_l_s_rst$next[0:0]$11957 + attribute \src "libresoc.v:173464.5-173464.29" + switch \initial + attribute \src "libresoc.v:173464.9-173464.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rst_l_s_rst$next[0:0]$11957 1'0 + case + assign $1\rst_l_s_rst$next[0:0]$11957 \all_rd + end + sync always + update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$11956 + end + attribute \src "libresoc.v:173472.3-173480.6" + process $proc$libresoc.v:173472$11958 + assign { } { } + assign { } { } + assign $0\rst_l_r_rst$next[0:0]$11959 $1\rst_l_r_rst$next[0:0]$11960 + attribute \src "libresoc.v:173473.5-173473.29" + switch \initial + attribute \src "libresoc.v:173473.9-173473.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rst_l_r_rst$next[0:0]$11960 1'1 + case + assign $1\rst_l_r_rst$next[0:0]$11960 \rst_r + end + sync always + update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$11959 + end + attribute \src "libresoc.v:173481.3-173489.6" + process $proc$libresoc.v:173481$11961 + assign { } { } + assign { } { } + assign $0\opc_l_s_opc$next[0:0]$11962 $1\opc_l_s_opc$next[0:0]$11963 + attribute \src "libresoc.v:173482.5-173482.29" + switch \initial + attribute \src "libresoc.v:173482.9-173482.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\opc_l_s_opc$next[0:0]$11963 1'0 + case + assign $1\opc_l_s_opc$next[0:0]$11963 \cu_issue_i + end + sync always + update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$11962 + end + attribute \src "libresoc.v:173490.3-173498.6" + process $proc$libresoc.v:173490$11964 + assign { } { } + assign { } { } + assign $0\opc_l_r_opc$next[0:0]$11965 $1\opc_l_r_opc$next[0:0]$11966 + attribute \src "libresoc.v:173491.5-173491.29" + switch \initial + attribute \src "libresoc.v:173491.9-173491.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\opc_l_r_opc$next[0:0]$11966 1'1 + case + assign $1\opc_l_r_opc$next[0:0]$11966 \req_done + end + sync always + update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$11965 + end + attribute \src "libresoc.v:173499.3-173507.6" + process $proc$libresoc.v:173499$11967 + assign { } { } + assign { } { } + assign $0\src_l_s_src$next[4:0]$11968 $1\src_l_s_src$next[4:0]$11969 + attribute \src "libresoc.v:173500.5-173500.29" + switch \initial + attribute \src "libresoc.v:173500.9-173500.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_l_s_src$next[4:0]$11969 5'00000 + case + assign $1\src_l_s_src$next[4:0]$11969 { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i } + end + sync always + update \src_l_s_src$next $0\src_l_s_src$next[4:0]$11968 + end + attribute \src "libresoc.v:173508.3-173516.6" + process $proc$libresoc.v:173508$11970 + assign { } { } + assign { } { } + assign $0\src_l_r_src$next[4:0]$11971 $1\src_l_r_src$next[4:0]$11972 + attribute \src "libresoc.v:173509.5-173509.29" + switch \initial + attribute \src "libresoc.v:173509.9-173509.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_l_r_src$next[4:0]$11972 5'11111 + case + assign $1\src_l_r_src$next[4:0]$11972 \reset_r + end + sync always + update \src_l_r_src$next $0\src_l_r_src$next[4:0]$11971 + end + attribute \src "libresoc.v:173517.3-173525.6" + process $proc$libresoc.v:173517$11973 + assign { } { } + assign { } { } + assign $0\req_l_s_req$next[2:0]$11974 $1\req_l_s_req$next[2:0]$11975 + attribute \src "libresoc.v:173518.5-173518.29" + switch \initial + attribute \src "libresoc.v:173518.9-173518.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\req_l_s_req$next[2:0]$11975 3'000 + case + assign $1\req_l_s_req$next[2:0]$11975 \$66 + end + sync always + update \req_l_s_req$next $0\req_l_s_req$next[2:0]$11974 + end + attribute \src "libresoc.v:173526.3-173534.6" + process $proc$libresoc.v:173526$11976 + assign { } { } + assign { } { } + assign $0\req_l_r_req$next[2:0]$11977 $1\req_l_r_req$next[2:0]$11978 + attribute \src "libresoc.v:173527.5-173527.29" + switch \initial + attribute \src "libresoc.v:173527.9-173527.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\req_l_r_req$next[2:0]$11978 3'111 + case + assign $1\req_l_r_req$next[2:0]$11978 \$68 + end + sync always + update \req_l_r_req$next $0\req_l_r_req$next[2:0]$11977 + end + attribute \src "libresoc.v:173535.3-173571.6" + process $proc$libresoc.v:173535$11979 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\alu_shift_rot0_sr_op__fn_unit$next[11:0]$11980 $1\alu_shift_rot0_sr_op__fn_unit$next[11:0]$11996 + assign { } { } + assign { } { } + assign $0\alu_shift_rot0_sr_op__input_carry$next[1:0]$11983 $1\alu_shift_rot0_sr_op__input_carry$next[1:0]$11999 + assign $0\alu_shift_rot0_sr_op__input_cr$next[0:0]$11984 $1\alu_shift_rot0_sr_op__input_cr$next[0:0]$12000 + assign $0\alu_shift_rot0_sr_op__insn$next[31:0]$11985 $1\alu_shift_rot0_sr_op__insn$next[31:0]$12001 + assign $0\alu_shift_rot0_sr_op__insn_type$next[6:0]$11986 $1\alu_shift_rot0_sr_op__insn_type$next[6:0]$12002 + assign $0\alu_shift_rot0_sr_op__is_32bit$next[0:0]$11987 $1\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12003 + assign $0\alu_shift_rot0_sr_op__is_signed$next[0:0]$11988 $1\alu_shift_rot0_sr_op__is_signed$next[0:0]$12004 + assign { } { } + assign { } { } + assign $0\alu_shift_rot0_sr_op__output_carry$next[0:0]$11991 $1\alu_shift_rot0_sr_op__output_carry$next[0:0]$12007 + assign $0\alu_shift_rot0_sr_op__output_cr$next[0:0]$11992 $1\alu_shift_rot0_sr_op__output_cr$next[0:0]$12008 + assign { } { } + assign { } { } + assign $0\alu_shift_rot0_sr_op__write_cr0$next[0:0]$11995 $1\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12011 + assign $0\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$11981 $2\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12012 + assign $0\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$11982 $2\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12013 + assign $0\alu_shift_rot0_sr_op__oe__oe$next[0:0]$11989 $2\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12014 + assign $0\alu_shift_rot0_sr_op__oe__ok$next[0:0]$11990 $2\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12015 + assign $0\alu_shift_rot0_sr_op__rc__ok$next[0:0]$11993 $2\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12016 + assign $0\alu_shift_rot0_sr_op__rc__rc$next[0:0]$11994 $2\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12017 + attribute \src "libresoc.v:173536.5-173536.29" + switch \initial + attribute \src "libresoc.v:173536.9-173536.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\alu_shift_rot0_sr_op__insn$next[31:0]$12001 $1\alu_shift_rot0_sr_op__is_signed$next[0:0]$12004 $1\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12003 $1\alu_shift_rot0_sr_op__output_cr$next[0:0]$12008 $1\alu_shift_rot0_sr_op__input_cr$next[0:0]$12000 $1\alu_shift_rot0_sr_op__output_carry$next[0:0]$12007 $1\alu_shift_rot0_sr_op__input_carry$next[1:0]$11999 $1\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12011 $1\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12006 $1\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12005 $1\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12009 $1\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12010 $1\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$11998 $1\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$11997 $1\alu_shift_rot0_sr_op__fn_unit$next[11:0]$11996 $1\alu_shift_rot0_sr_op__insn_type$next[6:0]$12002 } { \oper_i_alu_shift_rot0__insn \oper_i_alu_shift_rot0__is_signed \oper_i_alu_shift_rot0__is_32bit \oper_i_alu_shift_rot0__output_cr \oper_i_alu_shift_rot0__input_cr \oper_i_alu_shift_rot0__output_carry \oper_i_alu_shift_rot0__input_carry \oper_i_alu_shift_rot0__write_cr0 \oper_i_alu_shift_rot0__oe__ok \oper_i_alu_shift_rot0__oe__oe \oper_i_alu_shift_rot0__rc__ok \oper_i_alu_shift_rot0__rc__rc \oper_i_alu_shift_rot0__imm_data__ok \oper_i_alu_shift_rot0__imm_data__data \oper_i_alu_shift_rot0__fn_unit \oper_i_alu_shift_rot0__insn_type } + case + assign $1\alu_shift_rot0_sr_op__fn_unit$next[11:0]$11996 \alu_shift_rot0_sr_op__fn_unit + assign $1\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$11997 \alu_shift_rot0_sr_op__imm_data__data + assign $1\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$11998 \alu_shift_rot0_sr_op__imm_data__ok + assign $1\alu_shift_rot0_sr_op__input_carry$next[1:0]$11999 \alu_shift_rot0_sr_op__input_carry + assign $1\alu_shift_rot0_sr_op__input_cr$next[0:0]$12000 \alu_shift_rot0_sr_op__input_cr + assign $1\alu_shift_rot0_sr_op__insn$next[31:0]$12001 \alu_shift_rot0_sr_op__insn + assign $1\alu_shift_rot0_sr_op__insn_type$next[6:0]$12002 \alu_shift_rot0_sr_op__insn_type + assign $1\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12003 \alu_shift_rot0_sr_op__is_32bit + assign $1\alu_shift_rot0_sr_op__is_signed$next[0:0]$12004 \alu_shift_rot0_sr_op__is_signed + assign $1\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12005 \alu_shift_rot0_sr_op__oe__oe + assign $1\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12006 \alu_shift_rot0_sr_op__oe__ok + assign $1\alu_shift_rot0_sr_op__output_carry$next[0:0]$12007 \alu_shift_rot0_sr_op__output_carry + assign $1\alu_shift_rot0_sr_op__output_cr$next[0:0]$12008 \alu_shift_rot0_sr_op__output_cr + assign $1\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12009 \alu_shift_rot0_sr_op__rc__ok + assign $1\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12010 \alu_shift_rot0_sr_op__rc__rc + assign $1\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12011 \alu_shift_rot0_sr_op__write_cr0 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $2\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12012 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12013 1'0 + assign $2\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12017 1'0 + assign $2\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12016 1'0 + assign $2\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12014 1'0 + assign $2\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12015 1'0 + case + assign $2\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12012 $1\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$11997 + assign $2\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12013 $1\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$11998 + assign $2\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12014 $1\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12005 + assign $2\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12015 $1\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12006 + assign $2\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12016 $1\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12009 + assign $2\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12017 $1\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12010 + end + sync always + update \alu_shift_rot0_sr_op__fn_unit$next $0\alu_shift_rot0_sr_op__fn_unit$next[11:0]$11980 + update \alu_shift_rot0_sr_op__imm_data__data$next $0\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$11981 + update \alu_shift_rot0_sr_op__imm_data__ok$next $0\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$11982 + update \alu_shift_rot0_sr_op__input_carry$next $0\alu_shift_rot0_sr_op__input_carry$next[1:0]$11983 + update \alu_shift_rot0_sr_op__input_cr$next $0\alu_shift_rot0_sr_op__input_cr$next[0:0]$11984 + update \alu_shift_rot0_sr_op__insn$next $0\alu_shift_rot0_sr_op__insn$next[31:0]$11985 + update \alu_shift_rot0_sr_op__insn_type$next $0\alu_shift_rot0_sr_op__insn_type$next[6:0]$11986 + update \alu_shift_rot0_sr_op__is_32bit$next $0\alu_shift_rot0_sr_op__is_32bit$next[0:0]$11987 + update \alu_shift_rot0_sr_op__is_signed$next $0\alu_shift_rot0_sr_op__is_signed$next[0:0]$11988 + update \alu_shift_rot0_sr_op__oe__oe$next $0\alu_shift_rot0_sr_op__oe__oe$next[0:0]$11989 + update \alu_shift_rot0_sr_op__oe__ok$next $0\alu_shift_rot0_sr_op__oe__ok$next[0:0]$11990 + update \alu_shift_rot0_sr_op__output_carry$next $0\alu_shift_rot0_sr_op__output_carry$next[0:0]$11991 + update \alu_shift_rot0_sr_op__output_cr$next $0\alu_shift_rot0_sr_op__output_cr$next[0:0]$11992 + update \alu_shift_rot0_sr_op__rc__ok$next $0\alu_shift_rot0_sr_op__rc__ok$next[0:0]$11993 + update \alu_shift_rot0_sr_op__rc__rc$next $0\alu_shift_rot0_sr_op__rc__rc$next[0:0]$11994 + update \alu_shift_rot0_sr_op__write_cr0$next $0\alu_shift_rot0_sr_op__write_cr0$next[0:0]$11995 + end + attribute \src "libresoc.v:173572.3-173593.6" + process $proc$libresoc.v:173572$12018 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r0__o$next[63:0]$12019 $2\data_r0__o$next[63:0]$12023 + assign { } { } + assign $0\data_r0__o_ok$next[0:0]$12020 $3\data_r0__o_ok$next[0:0]$12025 + attribute \src "libresoc.v:173573.5-173573.29" + switch \initial + attribute \src "libresoc.v:173573.9-173573.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r0__o_ok$next[0:0]$12022 $1\data_r0__o$next[63:0]$12021 } { \o_ok \alu_shift_rot0_o } + case + assign $1\data_r0__o$next[63:0]$12021 \data_r0__o + assign $1\data_r0__o_ok$next[0:0]$12022 \data_r0__o_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r0__o_ok$next[0:0]$12024 $2\data_r0__o$next[63:0]$12023 } 65'00000000000000000000000000000000000000000000000000000000000000000 + case + assign $2\data_r0__o$next[63:0]$12023 $1\data_r0__o$next[63:0]$12021 + assign $2\data_r0__o_ok$next[0:0]$12024 $1\data_r0__o_ok$next[0:0]$12022 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r0__o_ok$next[0:0]$12025 1'0 + case + assign $3\data_r0__o_ok$next[0:0]$12025 $2\data_r0__o_ok$next[0:0]$12024 + end + sync always + update \data_r0__o$next $0\data_r0__o$next[63:0]$12019 + update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$12020 + end + attribute \src "libresoc.v:173594.3-173615.6" + process $proc$libresoc.v:173594$12026 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r1__cr_a$next[3:0]$12027 $2\data_r1__cr_a$next[3:0]$12031 + assign { } { } + assign $0\data_r1__cr_a_ok$next[0:0]$12028 $3\data_r1__cr_a_ok$next[0:0]$12033 + attribute \src "libresoc.v:173595.5-173595.29" + switch \initial + attribute \src "libresoc.v:173595.9-173595.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r1__cr_a_ok$next[0:0]$12030 $1\data_r1__cr_a$next[3:0]$12029 } { \cr_a_ok \alu_shift_rot0_cr_a } + case + assign $1\data_r1__cr_a$next[3:0]$12029 \data_r1__cr_a + assign $1\data_r1__cr_a_ok$next[0:0]$12030 \data_r1__cr_a_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r1__cr_a_ok$next[0:0]$12032 $2\data_r1__cr_a$next[3:0]$12031 } 5'00000 + case + assign $2\data_r1__cr_a$next[3:0]$12031 $1\data_r1__cr_a$next[3:0]$12029 + assign $2\data_r1__cr_a_ok$next[0:0]$12032 $1\data_r1__cr_a_ok$next[0:0]$12030 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r1__cr_a_ok$next[0:0]$12033 1'0 + case + assign $3\data_r1__cr_a_ok$next[0:0]$12033 $2\data_r1__cr_a_ok$next[0:0]$12032 + end + sync always + update \data_r1__cr_a$next $0\data_r1__cr_a$next[3:0]$12027 + update \data_r1__cr_a_ok$next $0\data_r1__cr_a_ok$next[0:0]$12028 + end + attribute \src "libresoc.v:173616.3-173637.6" + process $proc$libresoc.v:173616$12034 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r2__xer_ca$next[1:0]$12035 $2\data_r2__xer_ca$next[1:0]$12039 + assign { } { } + assign $0\data_r2__xer_ca_ok$next[0:0]$12036 $3\data_r2__xer_ca_ok$next[0:0]$12041 + attribute \src "libresoc.v:173617.5-173617.29" + switch \initial + attribute \src "libresoc.v:173617.9-173617.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r2__xer_ca_ok$next[0:0]$12038 $1\data_r2__xer_ca$next[1:0]$12037 } { \xer_ca_ok \alu_shift_rot0_xer_ca } + case + assign $1\data_r2__xer_ca$next[1:0]$12037 \data_r2__xer_ca + assign $1\data_r2__xer_ca_ok$next[0:0]$12038 \data_r2__xer_ca_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r2__xer_ca_ok$next[0:0]$12040 $2\data_r2__xer_ca$next[1:0]$12039 } 3'000 + case + assign $2\data_r2__xer_ca$next[1:0]$12039 $1\data_r2__xer_ca$next[1:0]$12037 + assign $2\data_r2__xer_ca_ok$next[0:0]$12040 $1\data_r2__xer_ca_ok$next[0:0]$12038 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r2__xer_ca_ok$next[0:0]$12041 1'0 + case + assign $3\data_r2__xer_ca_ok$next[0:0]$12041 $2\data_r2__xer_ca_ok$next[0:0]$12040 + end + sync always + update \data_r2__xer_ca$next $0\data_r2__xer_ca$next[1:0]$12035 + update \data_r2__xer_ca_ok$next $0\data_r2__xer_ca_ok$next[0:0]$12036 + end + attribute \src "libresoc.v:173638.3-173647.6" + process $proc$libresoc.v:173638$12042 + assign { } { } + assign { } { } + assign $0\src_r0$next[63:0]$12043 $1\src_r0$next[63:0]$12044 + attribute \src "libresoc.v:173639.5-173639.29" + switch \initial + attribute \src "libresoc.v:173639.9-173639.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch \src_l_q_src [0] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r0$next[63:0]$12044 \src1_i + case + assign $1\src_r0$next[63:0]$12044 \src_r0 + end + sync always + update \src_r0$next $0\src_r0$next[63:0]$12043 + end + attribute \src "libresoc.v:173648.3-173657.6" + process $proc$libresoc.v:173648$12045 + assign { } { } + assign { } { } + assign $0\src_r1$next[63:0]$12046 $1\src_r1$next[63:0]$12047 + attribute \src "libresoc.v:173649.5-173649.29" + switch \initial + attribute \src "libresoc.v:173649.9-173649.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch \src_sel + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r1$next[63:0]$12047 \src_or_imm + case + assign $1\src_r1$next[63:0]$12047 \src_r1 + end + sync always + update \src_r1$next $0\src_r1$next[63:0]$12046 + end + attribute \src "libresoc.v:173658.3-173667.6" + process $proc$libresoc.v:173658$12048 + assign { } { } + assign { } { } + assign $0\src_r2$next[63:0]$12049 $1\src_r2$next[63:0]$12050 + attribute \src "libresoc.v:173659.5-173659.29" + switch \initial + attribute \src "libresoc.v:173659.9-173659.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch \src_l_q_src [2] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r2$next[63:0]$12050 \src3_i + case + assign $1\src_r2$next[63:0]$12050 \src_r2 + end + sync always + update \src_r2$next $0\src_r2$next[63:0]$12049 + end + attribute \src "libresoc.v:173668.3-173677.6" + process $proc$libresoc.v:173668$12051 + assign { } { } + assign { } { } + assign $0\src_r3$next[0:0]$12052 $1\src_r3$next[0:0]$12053 + attribute \src "libresoc.v:173669.5-173669.29" + switch \initial + attribute \src "libresoc.v:173669.9-173669.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch \src_l_q_src [3] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r3$next[0:0]$12053 \src4_i + case + assign $1\src_r3$next[0:0]$12053 \src_r3 + end + sync always + update \src_r3$next $0\src_r3$next[0:0]$12052 + end + attribute \src "libresoc.v:173678.3-173687.6" + process $proc$libresoc.v:173678$12054 + assign { } { } + assign { } { } + assign $0\src_r4$next[1:0]$12055 $1\src_r4$next[1:0]$12056 + attribute \src "libresoc.v:173679.5-173679.29" + switch \initial + attribute \src "libresoc.v:173679.9-173679.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch \src_l_q_src [4] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r4$next[1:0]$12056 \src5_i + case + assign $1\src_r4$next[1:0]$12056 \src_r4 + end + sync always + update \src_r4$next $0\src_r4$next[1:0]$12055 + end + attribute \src "libresoc.v:173688.3-173696.6" + process $proc$libresoc.v:173688$12057 + assign { } { } + assign { } { } + assign $0\alui_l_r_alui$next[0:0]$12058 $1\alui_l_r_alui$next[0:0]$12059 + attribute \src "libresoc.v:173689.5-173689.29" + switch \initial + attribute \src "libresoc.v:173689.9-173689.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\alui_l_r_alui$next[0:0]$12059 1'1 + case + assign $1\alui_l_r_alui$next[0:0]$12059 \$90 + end + sync always + update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$12058 + end + attribute \src "libresoc.v:173697.3-173705.6" + process $proc$libresoc.v:173697$12060 + assign { } { } + assign { } { } + assign $0\alu_l_r_alu$next[0:0]$12061 $1\alu_l_r_alu$next[0:0]$12062 + attribute \src "libresoc.v:173698.5-173698.29" + switch \initial + attribute \src "libresoc.v:173698.9-173698.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\alu_l_r_alu$next[0:0]$12062 1'1 + case + assign $1\alu_l_r_alu$next[0:0]$12062 \$92 + end + sync always + update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$12061 + end + attribute \src "libresoc.v:173706.3-173715.6" + process $proc$libresoc.v:173706$12063 + assign { } { } + assign { } { } + assign $0\dest1_o[63:0] $1\dest1_o[63:0] + attribute \src "libresoc.v:173707.5-173707.29" + switch \initial + attribute \src "libresoc.v:173707.9-173707.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$114 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest1_o[63:0] \data_r0__o + case + assign $1\dest1_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \dest1_o $0\dest1_o[63:0] + end + attribute \src "libresoc.v:173716.3-173725.6" + process $proc$libresoc.v:173716$12064 + assign { } { } + assign { } { } + assign $0\dest2_o[3:0] $1\dest2_o[3:0] + attribute \src "libresoc.v:173717.5-173717.29" + switch \initial + attribute \src "libresoc.v:173717.9-173717.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$116 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest2_o[3:0] \data_r1__cr_a + case + assign $1\dest2_o[3:0] 4'0000 + end + sync always + update \dest2_o $0\dest2_o[3:0] + end + attribute \src "libresoc.v:173726.3-173735.6" + process $proc$libresoc.v:173726$12065 + assign { } { } + assign { } { } + assign $0\dest3_o[1:0] $1\dest3_o[1:0] + attribute \src "libresoc.v:173727.5-173727.29" + switch \initial + attribute \src "libresoc.v:173727.9-173727.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$118 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest3_o[1:0] \data_r2__xer_ca + case + assign $1\dest3_o[1:0] 2'00 + end + sync always + update \dest3_o $0\dest3_o[1:0] + end + attribute \src "libresoc.v:173736.3-173744.6" + process $proc$libresoc.v:173736$12066 + assign { } { } + assign { } { } + assign $0\prev_wr_go$next[2:0]$12067 $1\prev_wr_go$next[2:0]$12068 + attribute \src "libresoc.v:173737.5-173737.29" + switch \initial + attribute \src "libresoc.v:173737.9-173737.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\prev_wr_go$next[2:0]$12068 3'000 + case + assign $1\prev_wr_go$next[2:0]$12068 \$20 + end + sync always + update \prev_wr_go$next $0\prev_wr_go$next[2:0]$12067 + end + connect \$100 $not$libresoc.v:173209$11847_Y + connect \$102 $and$libresoc.v:173210$11848_Y + connect \$104 $and$libresoc.v:173211$11849_Y + connect \$106 $and$libresoc.v:173212$11850_Y + connect \$108 $and$libresoc.v:173213$11851_Y + connect \$10 $and$libresoc.v:173214$11852_Y + connect \$110 $and$libresoc.v:173215$11853_Y + connect \$112 $and$libresoc.v:173216$11854_Y + connect \$114 $and$libresoc.v:173217$11855_Y + connect \$116 $and$libresoc.v:173218$11856_Y + connect \$118 $and$libresoc.v:173219$11857_Y + connect \$12 $not$libresoc.v:173220$11858_Y + connect \$14 $and$libresoc.v:173221$11859_Y + connect \$16 $not$libresoc.v:173222$11860_Y + connect \$18 $and$libresoc.v:173223$11861_Y + connect \$20 $and$libresoc.v:173224$11862_Y + connect \$24 $not$libresoc.v:173225$11863_Y + connect \$26 $and$libresoc.v:173226$11864_Y + connect \$23 $reduce_or$libresoc.v:173227$11865_Y + connect \$22 $not$libresoc.v:173228$11866_Y + connect \$2 $and$libresoc.v:173229$11867_Y + connect \$30 $and$libresoc.v:173230$11868_Y + connect \$32 $reduce_or$libresoc.v:173231$11869_Y + connect \$34 $reduce_or$libresoc.v:173232$11870_Y + connect \$36 $or$libresoc.v:173233$11871_Y + connect \$38 $not$libresoc.v:173234$11872_Y + connect \$40 $and$libresoc.v:173235$11873_Y + connect \$42 $and$libresoc.v:173236$11874_Y + connect \$44 $eq$libresoc.v:173237$11875_Y + connect \$46 $and$libresoc.v:173238$11876_Y + connect \$48 $eq$libresoc.v:173239$11877_Y + connect \$50 $and$libresoc.v:173240$11878_Y + connect \$52 $and$libresoc.v:173241$11879_Y + connect \$54 $and$libresoc.v:173242$11880_Y + connect \$56 $or$libresoc.v:173243$11881_Y + connect \$58 $or$libresoc.v:173244$11882_Y + connect \$5 $not$libresoc.v:173245$11883_Y + connect \$60 $or$libresoc.v:173246$11884_Y + connect \$62 $or$libresoc.v:173247$11885_Y + connect \$64 $and$libresoc.v:173248$11886_Y + connect \$66 $and$libresoc.v:173249$11887_Y + connect \$68 $or$libresoc.v:173250$11888_Y + connect \$70 $and$libresoc.v:173251$11889_Y + connect \$72 $and$libresoc.v:173252$11890_Y + connect \$74 $and$libresoc.v:173253$11891_Y + connect \$76 $ternary$libresoc.v:173254$11892_Y + connect \$78 $ternary$libresoc.v:173255$11893_Y + connect \$7 $or$libresoc.v:173256$11894_Y + connect \$80 $ternary$libresoc.v:173257$11895_Y + connect \$82 $ternary$libresoc.v:173258$11896_Y + connect \$84 $ternary$libresoc.v:173259$11897_Y + connect \$86 $ternary$libresoc.v:173260$11898_Y + connect \$88 $ternary$libresoc.v:173261$11899_Y + connect \$4 $reduce_and$libresoc.v:173262$11900_Y + connect \$90 $and$libresoc.v:173263$11901_Y + connect \$92 $and$libresoc.v:173264$11902_Y + connect \$94 $and$libresoc.v:173265$11903_Y + connect \$96 $not$libresoc.v:173266$11904_Y + connect \$98 $and$libresoc.v:173267$11905_Y + connect \cu_go_die_i 1'0 + connect \cu_shadown_i 1'1 + connect \cu_wr__rel_o \$112 + connect \cu_rd__rel_o \$102 + connect \cu_busy_o \opc_l_q_opc + connect \alu_l_s_alu \all_rd_pulse + connect \alu_shift_rot0_n_ready_i \alu_l_q_alu + connect \alui_l_s_alui \all_rd_pulse + connect \alu_shift_rot0_p_valid_i \alui_l_q_alui + connect \alu_shift_rot0_xer_ca$1 \$88 + connect \alu_shift_rot0_xer_so \$86 + connect \alu_shift_rot0_rc \$84 + connect \alu_shift_rot0_rb \$82 + connect \alu_shift_rot0_ra \$80 + connect \src_or_imm \$78 + connect \src_sel \$76 + connect \cu_wrmask_o { \$74 \$72 \$70 } + connect \reset_r \$62 + connect \reset_w \$60 + connect \rst_r \$58 + connect \reset \$56 + connect \wr_any \$36 + connect \cu_done_o \$30 + connect \alu_pulsem { \alu_pulse \alu_pulse \alu_pulse } + connect \alu_pulse \alu_done_rise + connect \alu_done_rise \$18 + connect \alu_done_dly$next \alu_done + connect \alu_done \alu_shift_rot0_n_valid_o + connect \all_rd_pulse \all_rd_rise + connect \all_rd_rise \$14 + connect \all_rd_dly$next \all_rd + connect \all_rd \$10 +end +attribute \src "libresoc.v:173781.1-173958.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.spr" +attribute \generator "nMigen" +module \spr + attribute \src "libresoc.v:173930.3-173933.6" + wire width 7 $0$memwr$\memory$libresoc.v:173932$12222_ADDR[6:0]$12225 + attribute \src "libresoc.v:173930.3-173933.6" + wire width 64 $0$memwr$\memory$libresoc.v:173932$12222_DATA[63:0]$12226 + attribute \src "libresoc.v:173930.3-173933.6" + wire width 64 $0$memwr$\memory$libresoc.v:173932$12222_EN[63:0]$12227 + attribute \src "libresoc.v:173930.3-173933.6" + wire width 7 $0\_0_[6:0] + attribute \src "libresoc.v:173782.7-173782.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:173935.3-173943.6" + wire $0\ren_delay$next[0:0]$12230 + attribute \src "libresoc.v:173814.3-173815.35" + wire $0\ren_delay[0:0] + attribute \src "libresoc.v:173944.3-173953.6" + wire width 64 $0\spr1__data_o[63:0] + attribute \src "libresoc.v:173935.3-173943.6" + wire $1\ren_delay$next[0:0]$12231 + attribute \src "libresoc.v:173798.7-173798.23" + wire $1\ren_delay[0:0] + attribute \src "libresoc.v:173944.3-173953.6" + wire width 64 $1\spr1__data_o[63:0] + attribute \src "libresoc.v:173934.26-173934.32" + wire width 64 $memrd$\memory$libresoc.v:173934$12228_DATA + attribute \src "libresoc.v:0.0-0.0" + wire width 7 $memwr$\memory$libresoc.v:173932$12222_ADDR + attribute \src "libresoc.v:0.0-0.0" + wire width 64 $memwr$\memory$libresoc.v:173932$12222_DATA + attribute \src "libresoc.v:0.0-0.0" + wire width 64 $memwr$\memory$libresoc.v:173932$12222_EN + attribute \src "libresoc.v:173929.13-173929.16" + wire width 7 \_0_ + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 8 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 7 \coresync_rst + attribute \src "libresoc.v:173782.7-173782.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" + wire width 7 \memory_r_addr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" + wire width 64 \memory_r_data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" + wire width 7 \memory_w_addr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" + wire width 64 \memory_w_data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" + wire \memory_w_en + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" + wire \ren_delay + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" + wire \ren_delay$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 7 input 2 \spr1__addr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 7 input 5 \spr1__addr$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 input 4 \spr1__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 output 1 \spr1__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 3 \spr1__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 6 \spr1__wen + attribute \src "libresoc.v:173816.14-173816.20" + memory width 64 size 110 \memory + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12233 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12233 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 0 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12234 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12234 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 1 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12235 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12235 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 2 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12236 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12236 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 3 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12237 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12237 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 4 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12238 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12238 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 5 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12239 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12239 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 6 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12240 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12240 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 7 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12241 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12241 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 8 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12242 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12242 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 9 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12243 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12243 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 10 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12244 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12244 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 11 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12245 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12245 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 12 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12246 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12246 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 13 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12247 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12247 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 14 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12248 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12248 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 15 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12249 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12249 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 16 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12250 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12250 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 17 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12251 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12251 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 18 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12252 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12252 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 19 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12253 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12253 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 20 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12254 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12254 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 21 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12255 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12255 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 22 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12256 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12256 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 23 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12257 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12257 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 24 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12258 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12258 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 25 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12259 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12259 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 26 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12260 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12260 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 27 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12261 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12261 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 28 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12262 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12262 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 29 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12263 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12263 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 30 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12264 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12264 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 31 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12265 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12265 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 32 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12266 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12266 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 33 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12267 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12267 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 34 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12268 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12268 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 35 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12269 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12269 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 36 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12270 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12270 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 37 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12271 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12271 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 38 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12272 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12272 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 39 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12273 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12273 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 40 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12274 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12274 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 41 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12275 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12275 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 42 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12276 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12276 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 43 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12277 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12277 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 44 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12278 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12278 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 45 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12279 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12279 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 46 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12280 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12280 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 47 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12281 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12281 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 48 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12282 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12282 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 49 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12283 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12283 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 50 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12284 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12284 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 51 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12285 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12285 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 52 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12286 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12286 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 53 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12287 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12287 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 54 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12288 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12288 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 55 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12289 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12289 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 56 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12290 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12290 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 57 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12291 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12291 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 58 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12292 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12292 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 59 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12293 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12293 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 60 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12294 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12294 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 61 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12295 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12295 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 62 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12296 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12296 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 63 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12297 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12297 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 64 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12298 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12298 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 65 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12299 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12299 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 66 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12300 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12300 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 67 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12301 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12301 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 68 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12302 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12302 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 69 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12303 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12303 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 70 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12304 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12304 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 71 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12305 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12305 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 72 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12306 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12306 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 73 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12307 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12307 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 74 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12308 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12308 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 75 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12309 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12309 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 76 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12310 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12310 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 77 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12311 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12311 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 78 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12312 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12312 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 79 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12313 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12313 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 80 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12314 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12314 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 81 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12315 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12315 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 82 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12316 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12316 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 83 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12317 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12317 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 84 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12318 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12318 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 85 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12319 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12319 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 86 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12320 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12320 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 87 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12321 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12321 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 88 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12322 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12322 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 89 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12323 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12323 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 90 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12324 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12324 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 91 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12325 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12325 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 92 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12326 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12326 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 93 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12327 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12327 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 94 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12328 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12328 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 95 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12329 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12329 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 96 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12330 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12330 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 97 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12331 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12331 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 98 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12332 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12332 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 99 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12333 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12333 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 100 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12334 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12334 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 101 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12335 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12335 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 102 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12336 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12336 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 103 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12337 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12337 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 104 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12338 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12338 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 105 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12339 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12339 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 106 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12340 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12340 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 107 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12341 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12341 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 108 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12342 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12342 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 109 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:173934.26-173934.32" + cell $memrd $memrd$\memory$libresoc.v:173934$12228 + parameter \ABITS 7 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\memory" + parameter \TRANSPARENT 0 + parameter \WIDTH 64 + connect \ADDR \_0_ + connect \CLK 1'x + connect \DATA $memrd$\memory$libresoc.v:173934$12228_DATA + connect \EN 1'x + end + attribute \src "libresoc.v:0.0-0.0" + cell $memwr $memwr$\memory$libresoc.v:0$12343 + parameter \ABITS 7 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\memory" + parameter \PRIORITY 12343 + parameter \WIDTH 64 + connect \ADDR $memwr$\memory$libresoc.v:173932$12222_ADDR + connect \CLK 1'x + connect \DATA $memwr$\memory$libresoc.v:173932$12222_DATA + connect \EN $memwr$\memory$libresoc.v:173932$12222_EN + end + attribute \src "libresoc.v:0.0-0.0" + process $proc$libresoc.v:0$12346 + sync always + sync init + end + attribute \src "libresoc.v:173782.7-173782.20" + process $proc$libresoc.v:173782$12344 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:173798.7-173798.23" + process $proc$libresoc.v:173798$12345 + assign { } { } + assign $1\ren_delay[0:0] 1'0 + sync always + sync init + update \ren_delay $1\ren_delay[0:0] + end + attribute \src "libresoc.v:173814.3-173815.35" + process $proc$libresoc.v:173814$12223 + assign { } { } + assign $0\ren_delay[0:0] \ren_delay$next + sync posedge \coresync_clk + update \ren_delay $0\ren_delay[0:0] + end + attribute \src "libresoc.v:173930.3-173933.6" + process $proc$libresoc.v:173930$12224 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\memory$libresoc.v:173932$12222_ADDR[6:0]$12225 7'xxxxxxx + assign $0$memwr$\memory$libresoc.v:173932$12222_DATA[63:0]$12226 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\memory$libresoc.v:173932$12222_EN[63:0]$12227 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\_0_[6:0] \spr1__addr + attribute \src "libresoc.v:173932.5-173932.59" + switch \spr1__wen + attribute \src "libresoc.v:173932.9-173932.18" + case 1'1 + assign $0$memwr$\memory$libresoc.v:173932$12222_ADDR[6:0]$12225 \spr1__addr$1 + assign $0$memwr$\memory$libresoc.v:173932$12222_DATA[63:0]$12226 \spr1__data_i + assign $0$memwr$\memory$libresoc.v:173932$12222_EN[63:0]$12227 64'1111111111111111111111111111111111111111111111111111111111111111 + case + end + sync posedge \coresync_clk + update \_0_ $0\_0_[6:0] + update $memwr$\memory$libresoc.v:173932$12222_ADDR $0$memwr$\memory$libresoc.v:173932$12222_ADDR[6:0]$12225 + update $memwr$\memory$libresoc.v:173932$12222_DATA $0$memwr$\memory$libresoc.v:173932$12222_DATA[63:0]$12226 + update $memwr$\memory$libresoc.v:173932$12222_EN $0$memwr$\memory$libresoc.v:173932$12222_EN[63:0]$12227 + end + attribute \src "libresoc.v:173935.3-173943.6" + process $proc$libresoc.v:173935$12229 + assign { } { } + assign { } { } + assign $0\ren_delay$next[0:0]$12230 $1\ren_delay$next[0:0]$12231 + attribute \src "libresoc.v:173936.5-173936.29" + switch \initial + attribute \src "libresoc.v:173936.9-173936.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ren_delay$next[0:0]$12231 1'0 + case + assign $1\ren_delay$next[0:0]$12231 \spr1__ren + end + sync always + update \ren_delay$next $0\ren_delay$next[0:0]$12230 + end + attribute \src "libresoc.v:173944.3-173953.6" + process $proc$libresoc.v:173944$12232 + assign { } { } + assign { } { } + assign $0\spr1__data_o[63:0] $1\spr1__data_o[63:0] + attribute \src "libresoc.v:173945.5-173945.29" + switch \initial + attribute \src "libresoc.v:173945.9-173945.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" + switch \ren_delay + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\spr1__data_o[63:0] \memory_r_data + case + assign $1\spr1__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \spr1__data_o $0\spr1__data_o[63:0] + end + connect \memory_r_data $memrd$\memory$libresoc.v:173934$12228_DATA + connect \memory_w_data \spr1__data_i + connect \memory_w_en \spr1__wen + connect \memory_w_addr \spr1__addr$1 + connect \memory_r_addr \spr1__addr +end +attribute \src "libresoc.v:173962.1-175209.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.spr0" +attribute \generator "nMigen" +module \spr0 + attribute \src "libresoc.v:174706.3-174707.25" + wire $0\all_rd_dly[0:0] + attribute \src "libresoc.v:174704.3-174705.40" + wire $0\alu_done_dly[0:0] + attribute \src "libresoc.v:175100.3-175108.6" + wire $0\alu_l_r_alu$next[0:0]$12560 + attribute \src "libresoc.v:174634.3-174635.39" + wire $0\alu_l_r_alu[0:0] + attribute \src "libresoc.v:174886.3-174898.6" + wire width 12 $0\alu_spr0_spr_op__fn_unit$next[11:0]$12482 + attribute \src "libresoc.v:174676.3-174677.65" + wire width 12 $0\alu_spr0_spr_op__fn_unit[11:0] + attribute \src "libresoc.v:174886.3-174898.6" + wire width 32 $0\alu_spr0_spr_op__insn$next[31:0]$12483 + attribute \src "libresoc.v:174678.3-174679.59" + wire width 32 $0\alu_spr0_spr_op__insn[31:0] + attribute \src "libresoc.v:174886.3-174898.6" + wire width 7 $0\alu_spr0_spr_op__insn_type$next[6:0]$12484 + attribute \src "libresoc.v:174674.3-174675.69" + wire width 7 $0\alu_spr0_spr_op__insn_type[6:0] + attribute \src "libresoc.v:174886.3-174898.6" + wire $0\alu_spr0_spr_op__is_32bit$next[0:0]$12485 + attribute \src "libresoc.v:174680.3-174681.67" + wire $0\alu_spr0_spr_op__is_32bit[0:0] + attribute \src "libresoc.v:175091.3-175099.6" + wire $0\alui_l_r_alui$next[0:0]$12557 + attribute \src "libresoc.v:174636.3-174637.43" + wire $0\alui_l_r_alui[0:0] + attribute \src "libresoc.v:174899.3-174920.6" + wire width 64 $0\data_r0__o$next[63:0]$12491 + attribute \src "libresoc.v:174670.3-174671.37" + wire width 64 $0\data_r0__o[63:0] + attribute \src "libresoc.v:174899.3-174920.6" + wire $0\data_r0__o_ok$next[0:0]$12492 + attribute \src "libresoc.v:174672.3-174673.43" + wire $0\data_r0__o_ok[0:0] + attribute \src "libresoc.v:174921.3-174942.6" + wire width 64 $0\data_r1__spr1$next[63:0]$12499 + attribute \src "libresoc.v:174666.3-174667.43" + wire width 64 $0\data_r1__spr1[63:0] + attribute \src "libresoc.v:174921.3-174942.6" + wire $0\data_r1__spr1_ok$next[0:0]$12500 + attribute \src "libresoc.v:174668.3-174669.49" + wire $0\data_r1__spr1_ok[0:0] + attribute \src "libresoc.v:174943.3-174964.6" + wire width 64 $0\data_r2__fast1$next[63:0]$12507 + attribute \src "libresoc.v:174662.3-174663.45" + wire width 64 $0\data_r2__fast1[63:0] + attribute \src "libresoc.v:174943.3-174964.6" + wire $0\data_r2__fast1_ok$next[0:0]$12508 + attribute \src "libresoc.v:174664.3-174665.51" + wire $0\data_r2__fast1_ok[0:0] + attribute \src "libresoc.v:174965.3-174986.6" + wire $0\data_r3__xer_so$next[0:0]$12515 + attribute \src "libresoc.v:174658.3-174659.47" + wire $0\data_r3__xer_so[0:0] + attribute \src "libresoc.v:174965.3-174986.6" + wire $0\data_r3__xer_so_ok$next[0:0]$12516 + attribute \src "libresoc.v:174660.3-174661.53" + wire $0\data_r3__xer_so_ok[0:0] + attribute \src "libresoc.v:174987.3-175008.6" + wire width 2 $0\data_r4__xer_ov$next[1:0]$12523 + attribute \src "libresoc.v:174654.3-174655.47" + wire width 2 $0\data_r4__xer_ov[1:0] + attribute \src "libresoc.v:174987.3-175008.6" + wire $0\data_r4__xer_ov_ok$next[0:0]$12524 + attribute \src "libresoc.v:174656.3-174657.53" + wire $0\data_r4__xer_ov_ok[0:0] + attribute \src "libresoc.v:175009.3-175030.6" + wire width 2 $0\data_r5__xer_ca$next[1:0]$12531 + attribute \src "libresoc.v:174650.3-174651.47" + wire width 2 $0\data_r5__xer_ca[1:0] + attribute \src "libresoc.v:175009.3-175030.6" + wire $0\data_r5__xer_ca_ok$next[0:0]$12532 + attribute \src "libresoc.v:174652.3-174653.53" + wire $0\data_r5__xer_ca_ok[0:0] + attribute \src "libresoc.v:175109.3-175118.6" + wire width 64 $0\dest1_o[63:0] + attribute \src "libresoc.v:175119.3-175128.6" + wire width 64 $0\dest2_o[63:0] + attribute \src "libresoc.v:175129.3-175138.6" + wire width 64 $0\dest3_o[63:0] + attribute \src "libresoc.v:175139.3-175148.6" + wire $0\dest4_o[0:0] + attribute \src "libresoc.v:175149.3-175158.6" + wire width 2 $0\dest5_o[1:0] + attribute \src "libresoc.v:175159.3-175168.6" + wire width 2 $0\dest6_o[1:0] + attribute \src "libresoc.v:173963.7-173963.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:174841.3-174849.6" + wire $0\opc_l_r_opc$next[0:0]$12467 + attribute \src "libresoc.v:174690.3-174691.39" + wire $0\opc_l_r_opc[0:0] + attribute \src "libresoc.v:174832.3-174840.6" + wire $0\opc_l_s_opc$next[0:0]$12464 + attribute \src "libresoc.v:174692.3-174693.39" + wire $0\opc_l_s_opc[0:0] + attribute \src "libresoc.v:175169.3-175177.6" + wire width 6 $0\prev_wr_go$next[5:0]$12569 + attribute \src "libresoc.v:174702.3-174703.37" + wire width 6 $0\prev_wr_go[5:0] + attribute \src "libresoc.v:174786.3-174795.6" + wire $0\req_done[0:0] + attribute \src "libresoc.v:174877.3-174885.6" + wire width 6 $0\req_l_r_req$next[5:0]$12479 + attribute \src "libresoc.v:174682.3-174683.39" + wire width 6 $0\req_l_r_req[5:0] + attribute \src "libresoc.v:174868.3-174876.6" + wire width 6 $0\req_l_s_req$next[5:0]$12476 + attribute \src "libresoc.v:174684.3-174685.39" + wire width 6 $0\req_l_s_req[5:0] + attribute \src "libresoc.v:174805.3-174813.6" + wire $0\rok_l_r_rdok$next[0:0]$12455 + attribute \src "libresoc.v:174698.3-174699.41" + wire $0\rok_l_r_rdok[0:0] + attribute \src "libresoc.v:174796.3-174804.6" + wire $0\rok_l_s_rdok$next[0:0]$12452 + attribute \src "libresoc.v:174700.3-174701.41" + wire $0\rok_l_s_rdok[0:0] + attribute \src "libresoc.v:174823.3-174831.6" + wire $0\rst_l_r_rst$next[0:0]$12461 + attribute \src "libresoc.v:174694.3-174695.39" + wire $0\rst_l_r_rst[0:0] + attribute \src "libresoc.v:174814.3-174822.6" + wire $0\rst_l_s_rst$next[0:0]$12458 + attribute \src "libresoc.v:174696.3-174697.39" + wire $0\rst_l_s_rst[0:0] + attribute \src "libresoc.v:174859.3-174867.6" + wire width 6 $0\src_l_r_src$next[5:0]$12473 + attribute \src "libresoc.v:174686.3-174687.39" + wire width 6 $0\src_l_r_src[5:0] + attribute \src "libresoc.v:174850.3-174858.6" + wire width 6 $0\src_l_s_src$next[5:0]$12470 + attribute \src "libresoc.v:174688.3-174689.39" + wire width 6 $0\src_l_s_src[5:0] + attribute \src "libresoc.v:175031.3-175040.6" + wire width 64 $0\src_r0$next[63:0]$12539 + attribute \src "libresoc.v:174648.3-174649.29" + wire width 64 $0\src_r0[63:0] + attribute \src "libresoc.v:175041.3-175050.6" + wire width 64 $0\src_r1$next[63:0]$12542 + attribute \src "libresoc.v:174646.3-174647.29" + wire width 64 $0\src_r1[63:0] + attribute \src "libresoc.v:175051.3-175060.6" + wire width 64 $0\src_r2$next[63:0]$12545 + attribute \src "libresoc.v:174644.3-174645.29" + wire width 64 $0\src_r2[63:0] + attribute \src "libresoc.v:175061.3-175070.6" + wire $0\src_r3$next[0:0]$12548 + attribute \src "libresoc.v:174642.3-174643.29" + wire $0\src_r3[0:0] + attribute \src "libresoc.v:175071.3-175080.6" + wire width 2 $0\src_r4$next[1:0]$12551 + attribute \src "libresoc.v:174640.3-174641.29" + wire width 2 $0\src_r4[1:0] + attribute \src "libresoc.v:175081.3-175090.6" + wire width 2 $0\src_r5$next[1:0]$12554 + attribute \src "libresoc.v:174638.3-174639.29" + wire width 2 $0\src_r5[1:0] + attribute \src "libresoc.v:174099.7-174099.24" + wire $1\all_rd_dly[0:0] + attribute \src "libresoc.v:174109.7-174109.26" + wire $1\alu_done_dly[0:0] + attribute \src "libresoc.v:175100.3-175108.6" + wire $1\alu_l_r_alu$next[0:0]$12561 + attribute \src "libresoc.v:174117.7-174117.25" + wire $1\alu_l_r_alu[0:0] + attribute \src "libresoc.v:174886.3-174898.6" + wire width 12 $1\alu_spr0_spr_op__fn_unit$next[11:0]$12486 + attribute \src "libresoc.v:174160.14-174160.48" + wire width 12 $1\alu_spr0_spr_op__fn_unit[11:0] + attribute \src "libresoc.v:174886.3-174898.6" + wire width 32 $1\alu_spr0_spr_op__insn$next[31:0]$12487 + attribute \src "libresoc.v:174164.14-174164.43" + wire width 32 $1\alu_spr0_spr_op__insn[31:0] + attribute \src "libresoc.v:174886.3-174898.6" + wire width 7 $1\alu_spr0_spr_op__insn_type$next[6:0]$12488 + attribute \src "libresoc.v:174242.13-174242.47" + wire width 7 $1\alu_spr0_spr_op__insn_type[6:0] + attribute \src "libresoc.v:174886.3-174898.6" + wire $1\alu_spr0_spr_op__is_32bit$next[0:0]$12489 + attribute \src "libresoc.v:174246.7-174246.39" + wire $1\alu_spr0_spr_op__is_32bit[0:0] + attribute \src "libresoc.v:175091.3-175099.6" + wire $1\alui_l_r_alui$next[0:0]$12558 + attribute \src "libresoc.v:174264.7-174264.27" + wire $1\alui_l_r_alui[0:0] + attribute \src "libresoc.v:174899.3-174920.6" + wire width 64 $1\data_r0__o$next[63:0]$12493 + attribute \src "libresoc.v:174296.14-174296.47" + wire width 64 $1\data_r0__o[63:0] + attribute \src "libresoc.v:174899.3-174920.6" + wire $1\data_r0__o_ok$next[0:0]$12494 + attribute \src "libresoc.v:174300.7-174300.27" + wire $1\data_r0__o_ok[0:0] + attribute \src "libresoc.v:174921.3-174942.6" + wire width 64 $1\data_r1__spr1$next[63:0]$12501 + attribute \src "libresoc.v:174304.14-174304.50" + wire width 64 $1\data_r1__spr1[63:0] + attribute \src "libresoc.v:174921.3-174942.6" + wire $1\data_r1__spr1_ok$next[0:0]$12502 + attribute \src "libresoc.v:174308.7-174308.30" + wire $1\data_r1__spr1_ok[0:0] + attribute \src "libresoc.v:174943.3-174964.6" + wire width 64 $1\data_r2__fast1$next[63:0]$12509 + attribute \src "libresoc.v:174312.14-174312.51" + wire width 64 $1\data_r2__fast1[63:0] + attribute \src "libresoc.v:174943.3-174964.6" + wire $1\data_r2__fast1_ok$next[0:0]$12510 + attribute \src "libresoc.v:174316.7-174316.31" + wire $1\data_r2__fast1_ok[0:0] + attribute \src "libresoc.v:174965.3-174986.6" + wire $1\data_r3__xer_so$next[0:0]$12517 + attribute \src "libresoc.v:174320.7-174320.29" + wire $1\data_r3__xer_so[0:0] + attribute \src "libresoc.v:174965.3-174986.6" + wire $1\data_r3__xer_so_ok$next[0:0]$12518 + attribute \src "libresoc.v:174324.7-174324.32" + wire $1\data_r3__xer_so_ok[0:0] + attribute \src "libresoc.v:174987.3-175008.6" + wire width 2 $1\data_r4__xer_ov$next[1:0]$12525 + attribute \src "libresoc.v:174328.13-174328.35" + wire width 2 $1\data_r4__xer_ov[1:0] + attribute \src "libresoc.v:174987.3-175008.6" + wire $1\data_r4__xer_ov_ok$next[0:0]$12526 + attribute \src "libresoc.v:174332.7-174332.32" + wire $1\data_r4__xer_ov_ok[0:0] + attribute \src "libresoc.v:175009.3-175030.6" + wire width 2 $1\data_r5__xer_ca$next[1:0]$12533 + attribute \src "libresoc.v:174336.13-174336.35" + wire width 2 $1\data_r5__xer_ca[1:0] + attribute \src "libresoc.v:175009.3-175030.6" + wire $1\data_r5__xer_ca_ok$next[0:0]$12534 + attribute \src "libresoc.v:174340.7-174340.32" + wire $1\data_r5__xer_ca_ok[0:0] + attribute \src "libresoc.v:175109.3-175118.6" + wire width 64 $1\dest1_o[63:0] + attribute \src "libresoc.v:175119.3-175128.6" + wire width 64 $1\dest2_o[63:0] + attribute \src "libresoc.v:175129.3-175138.6" + wire width 64 $1\dest3_o[63:0] + attribute \src "libresoc.v:175139.3-175148.6" + wire $1\dest4_o[0:0] + attribute \src "libresoc.v:175149.3-175158.6" + wire width 2 $1\dest5_o[1:0] + attribute \src "libresoc.v:175159.3-175168.6" + wire width 2 $1\dest6_o[1:0] + attribute \src "libresoc.v:174841.3-174849.6" + wire $1\opc_l_r_opc$next[0:0]$12468 + attribute \src "libresoc.v:174368.7-174368.25" + wire $1\opc_l_r_opc[0:0] + attribute \src "libresoc.v:174832.3-174840.6" + wire $1\opc_l_s_opc$next[0:0]$12465 + attribute \src "libresoc.v:174372.7-174372.25" + wire $1\opc_l_s_opc[0:0] + attribute \src "libresoc.v:175169.3-175177.6" + wire width 6 $1\prev_wr_go$next[5:0]$12570 + attribute \src "libresoc.v:174471.13-174471.31" + wire width 6 $1\prev_wr_go[5:0] + attribute \src "libresoc.v:174786.3-174795.6" + wire $1\req_done[0:0] + attribute \src "libresoc.v:174877.3-174885.6" + wire width 6 $1\req_l_r_req$next[5:0]$12480 + attribute \src "libresoc.v:174479.13-174479.32" + wire width 6 $1\req_l_r_req[5:0] + attribute \src "libresoc.v:174868.3-174876.6" + wire width 6 $1\req_l_s_req$next[5:0]$12477 + attribute \src "libresoc.v:174483.13-174483.32" + wire width 6 $1\req_l_s_req[5:0] + attribute \src "libresoc.v:174805.3-174813.6" + wire $1\rok_l_r_rdok$next[0:0]$12456 + attribute \src "libresoc.v:174495.7-174495.26" + wire $1\rok_l_r_rdok[0:0] + attribute \src "libresoc.v:174796.3-174804.6" + wire $1\rok_l_s_rdok$next[0:0]$12453 + attribute \src "libresoc.v:174499.7-174499.26" + wire $1\rok_l_s_rdok[0:0] + attribute \src "libresoc.v:174823.3-174831.6" + wire $1\rst_l_r_rst$next[0:0]$12462 + attribute \src "libresoc.v:174503.7-174503.25" + wire $1\rst_l_r_rst[0:0] + attribute \src "libresoc.v:174814.3-174822.6" + wire $1\rst_l_s_rst$next[0:0]$12459 + attribute \src "libresoc.v:174507.7-174507.25" + wire $1\rst_l_s_rst[0:0] + attribute \src "libresoc.v:174859.3-174867.6" + wire width 6 $1\src_l_r_src$next[5:0]$12474 + attribute \src "libresoc.v:174529.13-174529.32" + wire width 6 $1\src_l_r_src[5:0] + attribute \src "libresoc.v:174850.3-174858.6" + wire width 6 $1\src_l_s_src$next[5:0]$12471 + attribute \src "libresoc.v:174533.13-174533.32" + wire width 6 $1\src_l_s_src[5:0] + attribute \src "libresoc.v:175031.3-175040.6" + wire width 64 $1\src_r0$next[63:0]$12540 + attribute \src "libresoc.v:174537.14-174537.43" + wire width 64 $1\src_r0[63:0] + attribute \src "libresoc.v:175041.3-175050.6" + wire width 64 $1\src_r1$next[63:0]$12543 + attribute \src "libresoc.v:174541.14-174541.43" + wire width 64 $1\src_r1[63:0] + attribute \src "libresoc.v:175051.3-175060.6" + wire width 64 $1\src_r2$next[63:0]$12546 + attribute \src "libresoc.v:174545.14-174545.43" + wire width 64 $1\src_r2[63:0] + attribute \src "libresoc.v:175061.3-175070.6" + wire $1\src_r3$next[0:0]$12549 + attribute \src "libresoc.v:174549.7-174549.20" + wire $1\src_r3[0:0] + attribute \src "libresoc.v:175071.3-175080.6" + wire width 2 $1\src_r4$next[1:0]$12552 + attribute \src "libresoc.v:174553.13-174553.26" + wire width 2 $1\src_r4[1:0] + attribute \src "libresoc.v:175081.3-175090.6" + wire width 2 $1\src_r5$next[1:0]$12555 + attribute \src "libresoc.v:174557.13-174557.26" + wire width 2 $1\src_r5[1:0] + attribute \src "libresoc.v:174899.3-174920.6" + wire width 64 $2\data_r0__o$next[63:0]$12495 + attribute \src "libresoc.v:174899.3-174920.6" + wire $2\data_r0__o_ok$next[0:0]$12496 + attribute \src "libresoc.v:174921.3-174942.6" + wire width 64 $2\data_r1__spr1$next[63:0]$12503 + attribute \src "libresoc.v:174921.3-174942.6" + wire $2\data_r1__spr1_ok$next[0:0]$12504 + attribute \src "libresoc.v:174943.3-174964.6" + wire width 64 $2\data_r2__fast1$next[63:0]$12511 + attribute \src "libresoc.v:174943.3-174964.6" + wire $2\data_r2__fast1_ok$next[0:0]$12512 + attribute \src "libresoc.v:174965.3-174986.6" + wire $2\data_r3__xer_so$next[0:0]$12519 + attribute \src "libresoc.v:174965.3-174986.6" + wire $2\data_r3__xer_so_ok$next[0:0]$12520 + attribute \src "libresoc.v:174987.3-175008.6" + wire width 2 $2\data_r4__xer_ov$next[1:0]$12527 + attribute \src "libresoc.v:174987.3-175008.6" + wire $2\data_r4__xer_ov_ok$next[0:0]$12528 + attribute \src "libresoc.v:175009.3-175030.6" + wire width 2 $2\data_r5__xer_ca$next[1:0]$12535 + attribute \src "libresoc.v:175009.3-175030.6" + wire $2\data_r5__xer_ca_ok$next[0:0]$12536 + attribute \src "libresoc.v:174899.3-174920.6" + wire $3\data_r0__o_ok$next[0:0]$12497 + attribute \src "libresoc.v:174921.3-174942.6" + wire $3\data_r1__spr1_ok$next[0:0]$12505 + attribute \src "libresoc.v:174943.3-174964.6" + wire $3\data_r2__fast1_ok$next[0:0]$12513 + attribute \src "libresoc.v:174965.3-174986.6" + wire $3\data_r3__xer_so_ok$next[0:0]$12521 + attribute \src "libresoc.v:174987.3-175008.6" + wire $3\data_r4__xer_ov_ok$next[0:0]$12529 + attribute \src "libresoc.v:175009.3-175030.6" + wire $3\data_r5__xer_ca_ok$next[0:0]$12537 + attribute \src "libresoc.v:174569.19-174569.133" + wire $and$libresoc.v:174569$12348_Y + attribute \src "libresoc.v:174570.19-174570.183" + wire width 6 $and$libresoc.v:174570$12349_Y + attribute \src "libresoc.v:174571.19-174571.115" + wire width 6 $and$libresoc.v:174571$12350_Y + attribute \src "libresoc.v:174573.19-174573.115" + wire width 6 $and$libresoc.v:174573$12352_Y + attribute \src "libresoc.v:174574.19-174574.125" + wire $and$libresoc.v:174574$12353_Y + attribute \src "libresoc.v:174575.19-174575.125" + wire $and$libresoc.v:174575$12354_Y + attribute \src "libresoc.v:174576.19-174576.125" + wire $and$libresoc.v:174576$12355_Y + attribute \src "libresoc.v:174577.19-174577.125" + wire $and$libresoc.v:174577$12356_Y + attribute \src "libresoc.v:174578.19-174578.125" + wire $and$libresoc.v:174578$12357_Y + attribute \src "libresoc.v:174580.19-174580.125" + wire $and$libresoc.v:174580$12359_Y + attribute \src "libresoc.v:174581.19-174581.165" + wire width 6 $and$libresoc.v:174581$12360_Y + attribute \src "libresoc.v:174582.19-174582.121" + wire width 6 $and$libresoc.v:174582$12361_Y + attribute \src "libresoc.v:174583.19-174583.127" + wire $and$libresoc.v:174583$12362_Y + attribute \src "libresoc.v:174584.19-174584.127" + wire $and$libresoc.v:174584$12363_Y + attribute \src "libresoc.v:174586.19-174586.127" + wire $and$libresoc.v:174586$12365_Y + attribute \src "libresoc.v:174587.19-174587.127" + wire $and$libresoc.v:174587$12366_Y + attribute \src "libresoc.v:174588.19-174588.127" + wire $and$libresoc.v:174588$12367_Y + attribute \src "libresoc.v:174589.19-174589.127" + wire $and$libresoc.v:174589$12368_Y + attribute \src "libresoc.v:174590.18-174590.110" + wire $and$libresoc.v:174590$12369_Y + attribute \src "libresoc.v:174592.18-174592.98" + wire $and$libresoc.v:174592$12371_Y + attribute \src "libresoc.v:174594.18-174594.100" + wire $and$libresoc.v:174594$12373_Y + attribute \src "libresoc.v:174595.18-174595.182" + wire width 6 $and$libresoc.v:174595$12374_Y + attribute \src "libresoc.v:174597.18-174597.119" + wire width 6 $and$libresoc.v:174597$12376_Y + attribute \src "libresoc.v:174600.18-174600.116" + wire $and$libresoc.v:174600$12379_Y + attribute \src "libresoc.v:174605.18-174605.113" + wire $and$libresoc.v:174605$12384_Y + attribute \src "libresoc.v:174606.18-174606.125" + wire width 6 $and$libresoc.v:174606$12385_Y + attribute \src "libresoc.v:174608.18-174608.112" + wire $and$libresoc.v:174608$12387_Y + attribute \src "libresoc.v:174610.18-174610.126" + wire $and$libresoc.v:174610$12389_Y + attribute \src "libresoc.v:174611.18-174611.126" + wire $and$libresoc.v:174611$12390_Y + attribute \src "libresoc.v:174612.18-174612.117" + wire $and$libresoc.v:174612$12391_Y + attribute \src "libresoc.v:174617.18-174617.130" + wire $and$libresoc.v:174617$12396_Y + attribute \src "libresoc.v:174618.17-174618.123" + wire $and$libresoc.v:174618$12397_Y + attribute \src "libresoc.v:174619.18-174619.124" + wire width 6 $and$libresoc.v:174619$12398_Y + attribute \src "libresoc.v:174621.18-174621.116" + wire $and$libresoc.v:174621$12400_Y + attribute \src "libresoc.v:174622.18-174622.119" + wire $and$libresoc.v:174622$12401_Y + attribute \src "libresoc.v:174623.18-174623.120" + wire $and$libresoc.v:174623$12402_Y + attribute \src "libresoc.v:174624.18-174624.121" + wire $and$libresoc.v:174624$12403_Y + attribute \src "libresoc.v:174625.18-174625.121" + wire $and$libresoc.v:174625$12404_Y + attribute \src "libresoc.v:174626.18-174626.121" + wire $and$libresoc.v:174626$12405_Y + attribute \src "libresoc.v:174633.18-174633.134" + wire $and$libresoc.v:174633$12412_Y + attribute \src "libresoc.v:174607.18-174607.113" + wire $eq$libresoc.v:174607$12386_Y + attribute \src "libresoc.v:174609.18-174609.119" + wire $eq$libresoc.v:174609$12388_Y + attribute \src "libresoc.v:174568.17-174568.113" + wire width 6 $not$libresoc.v:174568$12347_Y + attribute \src "libresoc.v:174572.19-174572.115" + wire width 6 $not$libresoc.v:174572$12351_Y + attribute \src "libresoc.v:174591.18-174591.97" + wire $not$libresoc.v:174591$12370_Y + attribute \src "libresoc.v:174593.18-174593.99" + wire $not$libresoc.v:174593$12372_Y + attribute \src "libresoc.v:174596.18-174596.113" + wire width 6 $not$libresoc.v:174596$12375_Y + attribute \src "libresoc.v:174599.18-174599.106" + wire $not$libresoc.v:174599$12378_Y + attribute \src "libresoc.v:174604.18-174604.120" + wire $not$libresoc.v:174604$12383_Y + attribute \src "libresoc.v:174579.18-174579.118" + wire width 6 $or$libresoc.v:174579$12358_Y + attribute \src "libresoc.v:174603.18-174603.112" + wire $or$libresoc.v:174603$12382_Y + attribute \src "libresoc.v:174613.18-174613.122" + wire $or$libresoc.v:174613$12392_Y + attribute \src "libresoc.v:174614.18-174614.124" + wire $or$libresoc.v:174614$12393_Y + attribute \src "libresoc.v:174615.18-174615.194" + wire width 6 $or$libresoc.v:174615$12394_Y + attribute \src "libresoc.v:174616.18-174616.194" + wire width 6 $or$libresoc.v:174616$12395_Y + attribute \src "libresoc.v:174620.18-174620.120" + wire width 6 $or$libresoc.v:174620$12399_Y + attribute \src "libresoc.v:174585.17-174585.105" + wire $reduce_and$libresoc.v:174585$12364_Y + attribute \src "libresoc.v:174598.18-174598.106" + wire $reduce_or$libresoc.v:174598$12377_Y + attribute \src "libresoc.v:174601.18-174601.113" + wire $reduce_or$libresoc.v:174601$12380_Y + attribute \src "libresoc.v:174602.18-174602.112" + wire $reduce_or$libresoc.v:174602$12381_Y + attribute \src "libresoc.v:174627.18-174627.118" + wire width 64 $ternary$libresoc.v:174627$12406_Y + attribute \src "libresoc.v:174628.18-174628.118" + wire width 64 $ternary$libresoc.v:174628$12407_Y + attribute \src "libresoc.v:174629.18-174629.118" + wire width 64 $ternary$libresoc.v:174629$12408_Y + attribute \src "libresoc.v:174630.18-174630.118" + wire $ternary$libresoc.v:174630$12409_Y + attribute \src "libresoc.v:174631.18-174631.118" + wire width 2 $ternary$libresoc.v:174631$12410_Y + attribute \src "libresoc.v:174632.18-174632.118" + wire width 2 $ternary$libresoc.v:174632$12411_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" + wire \$100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + wire width 6 \$102 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + wire width 6 \$104 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + wire width 6 \$106 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + wire width 6 \$108 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + wire width 6 \$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + wire \$110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + wire \$112 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + wire \$114 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + wire \$116 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + wire \$118 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + wire \$120 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" + wire width 6 \$122 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" + wire width 6 \$124 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + wire \$126 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + wire \$128 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + wire \$130 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + wire \$132 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + wire \$134 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + wire \$136 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + wire \$14 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire \$18 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire \$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" + wire width 6 \$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + wire \$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + wire width 6 \$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + wire width 6 \$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + wire \$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + wire \$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + wire \$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + wire \$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + wire \$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + wire \$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + wire width 6 \$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + wire \$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + wire \$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + wire \$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + wire \$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + wire \$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + wire \$58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" + wire \$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" + wire \$60 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" + wire \$62 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" + wire width 6 \$64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" + wire width 6 \$66 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" + wire \$68 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" + wire width 6 \$70 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" + wire width 6 \$72 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + wire \$74 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + wire \$76 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + wire \$78 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + wire \$80 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + wire \$82 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + wire \$84 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 64 \$86 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 64 \$88 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + wire width 6 \$9 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 64 \$90 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire \$92 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 2 \$94 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 2 \$96 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" + wire \$98 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:187" + wire \all_rd + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire \all_rd_dly + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire \all_rd_dly$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:192" + wire \all_rd_pulse + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + wire \all_rd_rise + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:196" + wire \alu_done + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire \alu_done_dly + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire \alu_done_dly$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + wire \alu_done_rise + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire \alu_l_q_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \alu_l_r_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \alu_l_r_alu$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \alu_l_s_alu + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:197" + wire \alu_pulse + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198" + wire width 6 \alu_pulsem + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \alu_spr0_fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \alu_spr0_fast1$2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire \alu_spr0_n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire \alu_spr0_n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \alu_spr0_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire \alu_spr0_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire \alu_spr0_p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \alu_spr0_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \alu_spr0_spr1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \alu_spr0_spr1$1 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \alu_spr0_spr_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \alu_spr0_spr_op__fn_unit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \alu_spr0_spr_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \alu_spr0_spr_op__insn$next + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \alu_spr0_spr_op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \alu_spr0_spr_op__insn_type$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_spr0_spr_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_spr0_spr_op__is_32bit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \alu_spr0_xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 \alu_spr0_xer_ca$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \alu_spr0_xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 \alu_spr0_xer_ov$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \alu_spr0_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \alu_spr0_xer_so$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire \alui_l_q_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \alui_l_r_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \alui_l_r_alui$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \alui_l_s_alui + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 31 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 30 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" + wire output 6 \cu_busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:108" + wire \cu_done_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:104" + wire \cu_go_die_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" + wire input 5 \cu_issue_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 6 input 9 \cu_rd__go_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 6 output 8 \cu_rd__rel_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" + wire width 6 input 7 \cu_rdmaskn_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:102" + wire \cu_shadown_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 6 input 18 \cu_wr__go_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 6 output 17 \cu_wr__rel_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:97" + wire width 6 \cu_wrmask_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 64 \data_r0__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 64 \data_r0__o$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r0__o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r0__o_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 64 \data_r1__spr1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 64 \data_r1__spr1$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r1__spr1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r1__spr1_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 64 \data_r2__fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 64 \data_r2__fast1$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r2__fast1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r2__fast1_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r3__xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r3__xer_so$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r3__xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r3__xer_so_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 2 \data_r4__xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 2 \data_r4__xer_ov$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r4__xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r4__xer_ov_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 2 \data_r5__xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 2 \data_r5__xer_ca$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r5__xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r5__xer_ca_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 19 \dest1_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 29 \dest2_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 27 \dest3_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire output 25 \dest4_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 2 output 23 \dest5_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 2 output 21 \dest6_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 26 \fast1_ok + attribute \src "libresoc.v:173963.7-173963.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 16 \o_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire \opc_l_q_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \opc_l_r_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \opc_l_r_opc$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \opc_l_s_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \opc_l_s_opc$next + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 2 \oper_i_alu_spr0__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 3 \oper_i_alu_spr0__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \oper_i_alu_spr0__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 4 \oper_i_alu_spr0__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" + wire width 6 \prev_wr_go + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" + wire width 6 \prev_wr_go$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212" + wire \req_done + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 6 \req_l_q_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 6 \req_l_r_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 6 \req_l_r_req$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 6 \req_l_s_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 6 \req_l_s_req$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226" + wire \reset + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:229" + wire width 6 \reset_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:228" + wire width 6 \reset_w + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire \rok_l_q_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \rok_l_r_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \rok_l_r_rdok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \rok_l_s_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \rok_l_s_rdok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \rst_l_r_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \rst_l_r_rst$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \rst_l_s_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \rst_l_s_rst$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227" + wire \rst_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 28 \spr1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 10 \src1_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 15 \src2_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 14 \src3_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire input 11 \src4_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 2 input 13 \src5_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 2 input 12 \src6_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 6 \src_l_q_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 6 \src_l_r_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 6 \src_l_r_src$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 6 \src_l_s_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 6 \src_l_s_src$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 64 \src_r0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 64 \src_r0$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 64 \src_r1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 64 \src_r1$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 64 \src_r2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 64 \src_r2$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire \src_r3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire \src_r3$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 2 \src_r4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 2 \src_r4$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 2 \src_r5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 2 \src_r5$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" + wire \wr_any + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 20 \xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 22 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 24 \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" + cell $and $and$libresoc.v:174569$12348 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_spr0_n_valid_o + connect \B \alu_l_q_alu + connect \Y $and$libresoc.v:174569$12348_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + cell $and $and$libresoc.v:174570$12349 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \src_l_q_src + connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } + connect \Y $and$libresoc.v:174570$12349_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + cell $and $and$libresoc.v:174571$12350 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \$102 + connect \B 6'111111 + connect \Y $and$libresoc.v:174571$12350_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + cell $and $and$libresoc.v:174573$12352 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \$104 + connect \B \$106 + connect \Y $and$libresoc.v:174573$12352_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + cell $and $and$libresoc.v:174574$12353 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_busy_o + connect \B \cu_shadown_i + connect \Y $and$libresoc.v:174574$12353_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + cell $and $and$libresoc.v:174575$12354 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_busy_o + connect \B \cu_shadown_i + connect \Y $and$libresoc.v:174575$12354_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + cell $and $and$libresoc.v:174576$12355 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_busy_o + connect \B \cu_shadown_i + connect \Y $and$libresoc.v:174576$12355_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + cell $and $and$libresoc.v:174577$12356 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_busy_o + connect \B \cu_shadown_i + connect \Y $and$libresoc.v:174577$12356_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + cell $and $and$libresoc.v:174578$12357 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_busy_o + connect \B \cu_shadown_i + connect \Y $and$libresoc.v:174578$12357_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + cell $and $and$libresoc.v:174580$12359 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_busy_o + connect \B \cu_shadown_i + connect \Y $and$libresoc.v:174580$12359_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" + cell $and $and$libresoc.v:174581$12360 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \req_l_q_req + connect \B { \$110 \$112 \$114 \$116 \$118 \$120 } + connect \Y $and$libresoc.v:174581$12360_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" + cell $and $and$libresoc.v:174582$12361 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \$122 + connect \B \cu_wrmask_o + connect \Y $and$libresoc.v:174582$12361_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + cell $and $and$libresoc.v:174583$12362 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_wr__go_i [0] + connect \B \cu_busy_o + connect \Y $and$libresoc.v:174583$12362_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + cell $and $and$libresoc.v:174584$12363 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_wr__go_i [1] + connect \B \cu_busy_o + connect \Y $and$libresoc.v:174584$12363_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + cell $and $and$libresoc.v:174586$12365 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_wr__go_i [2] + connect \B \cu_busy_o + connect \Y $and$libresoc.v:174586$12365_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + cell $and $and$libresoc.v:174587$12366 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_wr__go_i [3] + connect \B \cu_busy_o + connect \Y $and$libresoc.v:174587$12366_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + cell $and $and$libresoc.v:174588$12367 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_wr__go_i [4] + connect \B \cu_busy_o + connect \Y $and$libresoc.v:174588$12367_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + cell $and $and$libresoc.v:174589$12368 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_wr__go_i [5] + connect \B \cu_busy_o + connect \Y $and$libresoc.v:174589$12368_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $and $and$libresoc.v:174590$12369 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$6 + connect \B \$8 + connect \Y $and$libresoc.v:174590$12369_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $and$libresoc.v:174592$12371 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \all_rd + connect \B \$16 + connect \Y $and$libresoc.v:174592$12371_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $and$libresoc.v:174594$12373 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_done + connect \B \$20 + connect \Y $and$libresoc.v:174594$12373_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" + cell $and $and$libresoc.v:174595$12374 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \cu_wr__go_i + connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } + connect \Y $and$libresoc.v:174595$12374_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $and $and$libresoc.v:174597$12376 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \cu_wr__rel_o + connect \B \$28 + connect \Y $and$libresoc.v:174597$12376_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $and $and$libresoc.v:174600$12379 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_busy_o + connect \B \$26 + connect \Y $and$libresoc.v:174600$12379_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + cell $and $and$libresoc.v:174605$12384 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_any + connect \B \$42 + connect \Y $and$libresoc.v:174605$12384_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + cell $and $and$libresoc.v:174606$12385 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \req_l_q_req + connect \B \cu_wrmask_o + connect \Y $and$libresoc.v:174606$12385_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + cell $and $and$libresoc.v:174608$12387 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$44 + connect \B \$48 + connect \Y $and$libresoc.v:174608$12387_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + cell $and $and$libresoc.v:174610$12389 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$52 + connect \B \alu_spr0_n_ready_i + connect \Y $and$libresoc.v:174610$12389_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + cell $and $and$libresoc.v:174611$12390 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$54 + connect \B \alu_spr0_n_valid_o + connect \Y $and$libresoc.v:174611$12390_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + cell $and $and$libresoc.v:174612$12391 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$56 + connect \B \cu_busy_o + connect \Y $and$libresoc.v:174612$12391_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" + cell $and $and$libresoc.v:174617$12396 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_spr0_n_valid_o + connect \B \cu_busy_o + connect \Y $and$libresoc.v:174617$12396_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" + cell $and $and$libresoc.v:174618$12397 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_busy_o + connect \B \rok_l_q_rdok + connect \Y $and$libresoc.v:174618$12397_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" + cell $and $and$libresoc.v:174619$12398 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \alu_pulsem + connect \B \cu_wrmask_o + connect \Y $and$libresoc.v:174619$12398_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + cell $and $and$libresoc.v:174621$12400 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \o_ok + connect \B \cu_busy_o + connect \Y $and$libresoc.v:174621$12400_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + cell $and $and$libresoc.v:174622$12401 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \spr1_ok + connect \B \cu_busy_o + connect \Y $and$libresoc.v:174622$12401_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + cell $and $and$libresoc.v:174623$12402 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fast1_ok + connect \B \cu_busy_o + connect \Y $and$libresoc.v:174623$12402_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + cell $and $and$libresoc.v:174624$12403 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \xer_so_ok + connect \B \cu_busy_o + connect \Y $and$libresoc.v:174624$12403_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + cell $and $and$libresoc.v:174625$12404 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \xer_ov_ok + connect \B \cu_busy_o + connect \Y $and$libresoc.v:174625$12404_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + cell $and $and$libresoc.v:174626$12405 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \xer_ca_ok + connect \B \cu_busy_o + connect \Y $and$libresoc.v:174626$12405_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" + cell $and $and$libresoc.v:174633$12412 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_spr0_p_ready_o + connect \B \alui_l_q_alui + connect \Y $and$libresoc.v:174633$12412_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + cell $eq $eq$libresoc.v:174607$12386 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$46 + connect \B 1'0 + connect \Y $eq$libresoc.v:174607$12386_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + cell $eq $eq$libresoc.v:174609$12388 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_wrmask_o + connect \B 1'0 + connect \Y $eq$libresoc.v:174609$12388_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $not $not$libresoc.v:174568$12347 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \cu_rd__rel_o + connect \Y $not$libresoc.v:174568$12347_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + cell $not $not$libresoc.v:174572$12351 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \cu_rdmaskn_i + connect \Y $not$libresoc.v:174572$12351_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $not$libresoc.v:174591$12370 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \all_rd_dly + connect \Y $not$libresoc.v:174591$12370_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $not$libresoc.v:174593$12372 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_done_dly + connect \Y $not$libresoc.v:174593$12372_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $not $not$libresoc.v:174596$12375 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \cu_wrmask_o + connect \Y $not$libresoc.v:174596$12375_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $not $not$libresoc.v:174599$12378 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$27 + connect \Y $not$libresoc.v:174599$12378_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + cell $not $not$libresoc.v:174604$12383 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_spr0_n_ready_i + connect \Y $not$libresoc.v:174604$12383_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $or $or$libresoc.v:174579$12358 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \$9 + connect \B \cu_rd__go_i + connect \Y $or$libresoc.v:174579$12358_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $or $or$libresoc.v:174603$12382 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$36 + connect \B \$38 + connect \Y $or$libresoc.v:174603$12382_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" + cell $or $or$libresoc.v:174613$12392 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \req_done + connect \B \cu_go_die_i + connect \Y $or$libresoc.v:174613$12392_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" + cell $or $or$libresoc.v:174614$12393 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_issue_i + connect \B \cu_go_die_i + connect \Y $or$libresoc.v:174614$12393_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" + cell $or $or$libresoc.v:174615$12394 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \cu_wr__go_i + connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } + connect \Y $or$libresoc.v:174615$12394_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" + cell $or $or$libresoc.v:174616$12395 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \cu_rd__go_i + connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } + connect \Y $or$libresoc.v:174616$12395_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" + cell $or $or$libresoc.v:174620$12399 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \reset_w + connect \B \prev_wr_go + connect \Y $or$libresoc.v:174620$12399_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $reduce_and $reduce_and$libresoc.v:174585$12364 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \$11 + connect \Y $reduce_and$libresoc.v:174585$12364_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $reduce_or $reduce_or$libresoc.v:174598$12377 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \$30 + connect \Y $reduce_or$libresoc.v:174598$12377_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $reduce_or $reduce_or$libresoc.v:174601$12380 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \cu_wr__go_i + connect \Y $reduce_or$libresoc.v:174601$12380_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $reduce_or $reduce_or$libresoc.v:174602$12381 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \prev_wr_go + connect \Y $reduce_or$libresoc.v:174602$12381_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $ternary$libresoc.v:174627$12406 + parameter \WIDTH 64 + connect \A \src_r0 + connect \B \src1_i + connect \S \src_l_q_src [0] + connect \Y $ternary$libresoc.v:174627$12406_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $ternary$libresoc.v:174628$12407 + parameter \WIDTH 64 + connect \A \src_r1 + connect \B \src2_i + connect \S \src_l_q_src [1] + connect \Y $ternary$libresoc.v:174628$12407_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $ternary$libresoc.v:174629$12408 + parameter \WIDTH 64 + connect \A \src_r2 + connect \B \src3_i + connect \S \src_l_q_src [2] + connect \Y $ternary$libresoc.v:174629$12408_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $ternary$libresoc.v:174630$12409 + parameter \WIDTH 1 + connect \A \src_r3 + connect \B \src4_i + connect \S \src_l_q_src [3] + connect \Y $ternary$libresoc.v:174630$12409_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $ternary$libresoc.v:174631$12410 + parameter \WIDTH 2 + connect \A \src_r4 + connect \B \src5_i + connect \S \src_l_q_src [4] + connect \Y $ternary$libresoc.v:174631$12410_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $ternary$libresoc.v:174632$12411 + parameter \WIDTH 2 + connect \A \src_r5 + connect \B \src6_i + connect \S \src_l_q_src [5] + connect \Y $ternary$libresoc.v:174632$12411_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:174708.14-174714.4" + cell \alu_l$70 \alu_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_alu \alu_l_q_alu + connect \r_alu \alu_l_r_alu + connect \s_alu \alu_l_s_alu + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:174715.12-174744.4" + cell \alu_spr0 \alu_spr0 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \fast1 \alu_spr0_fast1 + connect \fast1$2 \alu_spr0_fast1$2 + connect \fast1_ok \fast1_ok + connect \n_ready_i \alu_spr0_n_ready_i + connect \n_valid_o \alu_spr0_n_valid_o + connect \o \alu_spr0_o + connect \o_ok \o_ok + connect \p_ready_o \alu_spr0_p_ready_o + connect \p_valid_i \alu_spr0_p_valid_i + connect \ra \alu_spr0_ra + connect \spr1 \alu_spr0_spr1 + connect \spr1$1 \alu_spr0_spr1$1 + connect \spr1_ok \spr1_ok + connect \spr_op__fn_unit \alu_spr0_spr_op__fn_unit + connect \spr_op__insn \alu_spr0_spr_op__insn + connect \spr_op__insn_type \alu_spr0_spr_op__insn_type + connect \spr_op__is_32bit \alu_spr0_spr_op__is_32bit + connect \xer_ca \alu_spr0_xer_ca + connect \xer_ca$5 \alu_spr0_xer_ca$5 + connect \xer_ca_ok \xer_ca_ok + connect \xer_ov \alu_spr0_xer_ov + connect \xer_ov$4 \alu_spr0_xer_ov$4 + connect \xer_ov_ok \xer_ov_ok + connect \xer_so \alu_spr0_xer_so + connect \xer_so$3 \alu_spr0_xer_so$3 + connect \xer_so_ok \xer_so_ok + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:174745.15-174751.4" + cell \alui_l$69 \alui_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_alui \alui_l_q_alui + connect \r_alui \alui_l_r_alui + connect \s_alui \alui_l_s_alui + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:174752.14-174758.4" + cell \opc_l$65 \opc_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_opc \opc_l_q_opc + connect \r_opc \opc_l_r_opc + connect \s_opc \opc_l_s_opc + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:174759.14-174765.4" + cell \req_l$66 \req_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_req \req_l_q_req + connect \r_req \req_l_r_req + connect \s_req \req_l_s_req + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:174766.14-174772.4" + cell \rok_l$68 \rok_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_rdok \rok_l_q_rdok + connect \r_rdok \rok_l_r_rdok + connect \s_rdok \rok_l_s_rdok + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:174773.14-174778.4" + cell \rst_l$67 \rst_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \r_rst \rst_l_r_rst + connect \s_rst \rst_l_s_rst + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:174779.14-174785.4" + cell \src_l$64 \src_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_src \src_l_q_src + connect \r_src \src_l_r_src + connect \s_src \src_l_s_src + end + attribute \src "libresoc.v:173963.7-173963.20" + process $proc$libresoc.v:173963$12571 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:174099.7-174099.24" + process $proc$libresoc.v:174099$12572 + assign { } { } + assign $1\all_rd_dly[0:0] 1'0 + sync always + sync init + update \all_rd_dly $1\all_rd_dly[0:0] + end + attribute \src "libresoc.v:174109.7-174109.26" + process $proc$libresoc.v:174109$12573 + assign { } { } + assign $1\alu_done_dly[0:0] 1'0 + sync always + sync init + update \alu_done_dly $1\alu_done_dly[0:0] + end + attribute \src "libresoc.v:174117.7-174117.25" + process $proc$libresoc.v:174117$12574 + assign { } { } + assign $1\alu_l_r_alu[0:0] 1'1 + sync always + sync init + update \alu_l_r_alu $1\alu_l_r_alu[0:0] + end + attribute \src "libresoc.v:174160.14-174160.48" + process $proc$libresoc.v:174160$12575 + assign { } { } + assign $1\alu_spr0_spr_op__fn_unit[11:0] 12'000000000000 + sync always + sync init + update \alu_spr0_spr_op__fn_unit $1\alu_spr0_spr_op__fn_unit[11:0] + end + attribute \src "libresoc.v:174164.14-174164.43" + process $proc$libresoc.v:174164$12576 + assign { } { } + assign $1\alu_spr0_spr_op__insn[31:0] 0 + sync always + sync init + update \alu_spr0_spr_op__insn $1\alu_spr0_spr_op__insn[31:0] + end + attribute \src "libresoc.v:174242.13-174242.47" + process $proc$libresoc.v:174242$12577 + assign { } { } + assign $1\alu_spr0_spr_op__insn_type[6:0] 7'0000000 + sync always + sync init + update \alu_spr0_spr_op__insn_type $1\alu_spr0_spr_op__insn_type[6:0] + end + attribute \src "libresoc.v:174246.7-174246.39" + process $proc$libresoc.v:174246$12578 + assign { } { } + assign $1\alu_spr0_spr_op__is_32bit[0:0] 1'0 + sync always + sync init + update \alu_spr0_spr_op__is_32bit $1\alu_spr0_spr_op__is_32bit[0:0] + end + attribute \src "libresoc.v:174264.7-174264.27" + process $proc$libresoc.v:174264$12579 + assign { } { } + assign $1\alui_l_r_alui[0:0] 1'1 + sync always + sync init + update \alui_l_r_alui $1\alui_l_r_alui[0:0] + end + attribute \src "libresoc.v:174296.14-174296.47" + process $proc$libresoc.v:174296$12580 + assign { } { } + assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \data_r0__o $1\data_r0__o[63:0] + end + attribute \src "libresoc.v:174300.7-174300.27" + process $proc$libresoc.v:174300$12581 + assign { } { } + assign $1\data_r0__o_ok[0:0] 1'0 + sync always + sync init + update \data_r0__o_ok $1\data_r0__o_ok[0:0] + end + attribute \src "libresoc.v:174304.14-174304.50" + process $proc$libresoc.v:174304$12582 + assign { } { } + assign $1\data_r1__spr1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \data_r1__spr1 $1\data_r1__spr1[63:0] + end + attribute \src "libresoc.v:174308.7-174308.30" + process $proc$libresoc.v:174308$12583 + assign { } { } + assign $1\data_r1__spr1_ok[0:0] 1'0 + sync always + sync init + update \data_r1__spr1_ok $1\data_r1__spr1_ok[0:0] + end + attribute \src "libresoc.v:174312.14-174312.51" + process $proc$libresoc.v:174312$12584 + assign { } { } + assign $1\data_r2__fast1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \data_r2__fast1 $1\data_r2__fast1[63:0] + end + attribute \src "libresoc.v:174316.7-174316.31" + process $proc$libresoc.v:174316$12585 + assign { } { } + assign $1\data_r2__fast1_ok[0:0] 1'0 + sync always + sync init + update \data_r2__fast1_ok $1\data_r2__fast1_ok[0:0] + end + attribute \src "libresoc.v:174320.7-174320.29" + process $proc$libresoc.v:174320$12586 + assign { } { } + assign $1\data_r3__xer_so[0:0] 1'0 + sync always + sync init + update \data_r3__xer_so $1\data_r3__xer_so[0:0] + end + attribute \src "libresoc.v:174324.7-174324.32" + process $proc$libresoc.v:174324$12587 + assign { } { } + assign $1\data_r3__xer_so_ok[0:0] 1'0 + sync always + sync init + update \data_r3__xer_so_ok $1\data_r3__xer_so_ok[0:0] + end + attribute \src "libresoc.v:174328.13-174328.35" + process $proc$libresoc.v:174328$12588 + assign { } { } + assign $1\data_r4__xer_ov[1:0] 2'00 + sync always + sync init + update \data_r4__xer_ov $1\data_r4__xer_ov[1:0] + end + attribute \src "libresoc.v:174332.7-174332.32" + process $proc$libresoc.v:174332$12589 + assign { } { } + assign $1\data_r4__xer_ov_ok[0:0] 1'0 + sync always + sync init + update \data_r4__xer_ov_ok $1\data_r4__xer_ov_ok[0:0] + end + attribute \src "libresoc.v:174336.13-174336.35" + process $proc$libresoc.v:174336$12590 + assign { } { } + assign $1\data_r5__xer_ca[1:0] 2'00 + sync always + sync init + update \data_r5__xer_ca $1\data_r5__xer_ca[1:0] + end + attribute \src "libresoc.v:174340.7-174340.32" + process $proc$libresoc.v:174340$12591 + assign { } { } + assign $1\data_r5__xer_ca_ok[0:0] 1'0 + sync always + sync init + update \data_r5__xer_ca_ok $1\data_r5__xer_ca_ok[0:0] + end + attribute \src "libresoc.v:174368.7-174368.25" + process $proc$libresoc.v:174368$12592 + assign { } { } + assign $1\opc_l_r_opc[0:0] 1'1 + sync always + sync init + update \opc_l_r_opc $1\opc_l_r_opc[0:0] + end + attribute \src "libresoc.v:174372.7-174372.25" + process $proc$libresoc.v:174372$12593 + assign { } { } + assign $1\opc_l_s_opc[0:0] 1'0 + sync always + sync init + update \opc_l_s_opc $1\opc_l_s_opc[0:0] + end + attribute \src "libresoc.v:174471.13-174471.31" + process $proc$libresoc.v:174471$12594 + assign { } { } + assign $1\prev_wr_go[5:0] 6'000000 + sync always + sync init + update \prev_wr_go $1\prev_wr_go[5:0] + end + attribute \src "libresoc.v:174479.13-174479.32" + process $proc$libresoc.v:174479$12595 + assign { } { } + assign $1\req_l_r_req[5:0] 6'111111 + sync always + sync init + update \req_l_r_req $1\req_l_r_req[5:0] + end + attribute \src "libresoc.v:174483.13-174483.32" + process $proc$libresoc.v:174483$12596 + assign { } { } + assign $1\req_l_s_req[5:0] 6'000000 + sync always + sync init + update \req_l_s_req $1\req_l_s_req[5:0] + end + attribute \src "libresoc.v:174495.7-174495.26" + process $proc$libresoc.v:174495$12597 + assign { } { } + assign $1\rok_l_r_rdok[0:0] 1'1 + sync always + sync init + update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] + end + attribute \src "libresoc.v:174499.7-174499.26" + process $proc$libresoc.v:174499$12598 + assign { } { } + assign $1\rok_l_s_rdok[0:0] 1'0 + sync always + sync init + update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] + end + attribute \src "libresoc.v:174503.7-174503.25" + process $proc$libresoc.v:174503$12599 + assign { } { } + assign $1\rst_l_r_rst[0:0] 1'1 + sync always + sync init + update \rst_l_r_rst $1\rst_l_r_rst[0:0] + end + attribute \src "libresoc.v:174507.7-174507.25" + process $proc$libresoc.v:174507$12600 + assign { } { } + assign $1\rst_l_s_rst[0:0] 1'0 + sync always + sync init + update \rst_l_s_rst $1\rst_l_s_rst[0:0] + end + attribute \src "libresoc.v:174529.13-174529.32" + process $proc$libresoc.v:174529$12601 + assign { } { } + assign $1\src_l_r_src[5:0] 6'111111 + sync always + sync init + update \src_l_r_src $1\src_l_r_src[5:0] + end + attribute \src "libresoc.v:174533.13-174533.32" + process $proc$libresoc.v:174533$12602 + assign { } { } + assign $1\src_l_s_src[5:0] 6'000000 + sync always + sync init + update \src_l_s_src $1\src_l_s_src[5:0] + end + attribute \src "libresoc.v:174537.14-174537.43" + process $proc$libresoc.v:174537$12603 + assign { } { } + assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \src_r0 $1\src_r0[63:0] + end + attribute \src "libresoc.v:174541.14-174541.43" + process $proc$libresoc.v:174541$12604 + assign { } { } + assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \src_r1 $1\src_r1[63:0] + end + attribute \src "libresoc.v:174545.14-174545.43" + process $proc$libresoc.v:174545$12605 + assign { } { } + assign $1\src_r2[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \src_r2 $1\src_r2[63:0] + end + attribute \src "libresoc.v:174549.7-174549.20" + process $proc$libresoc.v:174549$12606 + assign { } { } + assign $1\src_r3[0:0] 1'0 + sync always + sync init + update \src_r3 $1\src_r3[0:0] + end + attribute \src "libresoc.v:174553.13-174553.26" + process $proc$libresoc.v:174553$12607 + assign { } { } + assign $1\src_r4[1:0] 2'00 + sync always + sync init + update \src_r4 $1\src_r4[1:0] + end + attribute \src "libresoc.v:174557.13-174557.26" + process $proc$libresoc.v:174557$12608 + assign { } { } + assign $1\src_r5[1:0] 2'00 + sync always + sync init + update \src_r5 $1\src_r5[1:0] + end + attribute \src "libresoc.v:174634.3-174635.39" + process $proc$libresoc.v:174634$12413 + assign { } { } + assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next + sync posedge \coresync_clk + update \alu_l_r_alu $0\alu_l_r_alu[0:0] + end + attribute \src "libresoc.v:174636.3-174637.43" + process $proc$libresoc.v:174636$12414 + assign { } { } + assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next + sync posedge \coresync_clk + update \alui_l_r_alui $0\alui_l_r_alui[0:0] + end + attribute \src "libresoc.v:174638.3-174639.29" + process $proc$libresoc.v:174638$12415 + assign { } { } + assign $0\src_r5[1:0] \src_r5$next + sync posedge \coresync_clk + update \src_r5 $0\src_r5[1:0] + end + attribute \src "libresoc.v:174640.3-174641.29" + process $proc$libresoc.v:174640$12416 + assign { } { } + assign $0\src_r4[1:0] \src_r4$next + sync posedge \coresync_clk + update \src_r4 $0\src_r4[1:0] + end + attribute \src "libresoc.v:174642.3-174643.29" + process $proc$libresoc.v:174642$12417 + assign { } { } + assign $0\src_r3[0:0] \src_r3$next + sync posedge \coresync_clk + update \src_r3 $0\src_r3[0:0] + end + attribute \src "libresoc.v:174644.3-174645.29" + process $proc$libresoc.v:174644$12418 + assign { } { } + assign $0\src_r2[63:0] \src_r2$next + sync posedge \coresync_clk + update \src_r2 $0\src_r2[63:0] + end + attribute \src "libresoc.v:174646.3-174647.29" + process $proc$libresoc.v:174646$12419 + assign { } { } + assign $0\src_r1[63:0] \src_r1$next + sync posedge \coresync_clk + update \src_r1 $0\src_r1[63:0] + end + attribute \src "libresoc.v:174648.3-174649.29" + process $proc$libresoc.v:174648$12420 + assign { } { } + assign $0\src_r0[63:0] \src_r0$next + sync posedge \coresync_clk + update \src_r0 $0\src_r0[63:0] + end + attribute \src "libresoc.v:174650.3-174651.47" + process $proc$libresoc.v:174650$12421 + assign { } { } + assign $0\data_r5__xer_ca[1:0] \data_r5__xer_ca$next + sync posedge \coresync_clk + update \data_r5__xer_ca $0\data_r5__xer_ca[1:0] + end + attribute \src "libresoc.v:174652.3-174653.53" + process $proc$libresoc.v:174652$12422 + assign { } { } + assign $0\data_r5__xer_ca_ok[0:0] \data_r5__xer_ca_ok$next + sync posedge \coresync_clk + update \data_r5__xer_ca_ok $0\data_r5__xer_ca_ok[0:0] + end + attribute \src "libresoc.v:174654.3-174655.47" + process $proc$libresoc.v:174654$12423 + assign { } { } + assign $0\data_r4__xer_ov[1:0] \data_r4__xer_ov$next + sync posedge \coresync_clk + update \data_r4__xer_ov $0\data_r4__xer_ov[1:0] + end + attribute \src "libresoc.v:174656.3-174657.53" + process $proc$libresoc.v:174656$12424 + assign { } { } + assign $0\data_r4__xer_ov_ok[0:0] \data_r4__xer_ov_ok$next + sync posedge \coresync_clk + update \data_r4__xer_ov_ok $0\data_r4__xer_ov_ok[0:0] + end + attribute \src "libresoc.v:174658.3-174659.47" + process $proc$libresoc.v:174658$12425 + assign { } { } + assign $0\data_r3__xer_so[0:0] \data_r3__xer_so$next + sync posedge \coresync_clk + update \data_r3__xer_so $0\data_r3__xer_so[0:0] + end + attribute \src "libresoc.v:174660.3-174661.53" + process $proc$libresoc.v:174660$12426 + assign { } { } + assign $0\data_r3__xer_so_ok[0:0] \data_r3__xer_so_ok$next + sync posedge \coresync_clk + update \data_r3__xer_so_ok $0\data_r3__xer_so_ok[0:0] + end + attribute \src "libresoc.v:174662.3-174663.45" + process $proc$libresoc.v:174662$12427 + assign { } { } + assign $0\data_r2__fast1[63:0] \data_r2__fast1$next + sync posedge \coresync_clk + update \data_r2__fast1 $0\data_r2__fast1[63:0] + end + attribute \src "libresoc.v:174664.3-174665.51" + process $proc$libresoc.v:174664$12428 + assign { } { } + assign $0\data_r2__fast1_ok[0:0] \data_r2__fast1_ok$next + sync posedge \coresync_clk + update \data_r2__fast1_ok $0\data_r2__fast1_ok[0:0] + end + attribute \src "libresoc.v:174666.3-174667.43" + process $proc$libresoc.v:174666$12429 + assign { } { } + assign $0\data_r1__spr1[63:0] \data_r1__spr1$next + sync posedge \coresync_clk + update \data_r1__spr1 $0\data_r1__spr1[63:0] + end + attribute \src "libresoc.v:174668.3-174669.49" + process $proc$libresoc.v:174668$12430 + assign { } { } + assign $0\data_r1__spr1_ok[0:0] \data_r1__spr1_ok$next + sync posedge \coresync_clk + update \data_r1__spr1_ok $0\data_r1__spr1_ok[0:0] + end + attribute \src "libresoc.v:174670.3-174671.37" + process $proc$libresoc.v:174670$12431 + assign { } { } + assign $0\data_r0__o[63:0] \data_r0__o$next + sync posedge \coresync_clk + update \data_r0__o $0\data_r0__o[63:0] + end + attribute \src "libresoc.v:174672.3-174673.43" + process $proc$libresoc.v:174672$12432 + assign { } { } + assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next + sync posedge \coresync_clk + update \data_r0__o_ok $0\data_r0__o_ok[0:0] + end + attribute \src "libresoc.v:174674.3-174675.69" + process $proc$libresoc.v:174674$12433 + assign { } { } + assign $0\alu_spr0_spr_op__insn_type[6:0] \alu_spr0_spr_op__insn_type$next + sync posedge \coresync_clk + update \alu_spr0_spr_op__insn_type $0\alu_spr0_spr_op__insn_type[6:0] + end + attribute \src "libresoc.v:174676.3-174677.65" + process $proc$libresoc.v:174676$12434 + assign { } { } + assign $0\alu_spr0_spr_op__fn_unit[11:0] \alu_spr0_spr_op__fn_unit$next + sync posedge \coresync_clk + update \alu_spr0_spr_op__fn_unit $0\alu_spr0_spr_op__fn_unit[11:0] + end + attribute \src "libresoc.v:174678.3-174679.59" + process $proc$libresoc.v:174678$12435 + assign { } { } + assign $0\alu_spr0_spr_op__insn[31:0] \alu_spr0_spr_op__insn$next + sync posedge \coresync_clk + update \alu_spr0_spr_op__insn $0\alu_spr0_spr_op__insn[31:0] + end + attribute \src "libresoc.v:174680.3-174681.67" + process $proc$libresoc.v:174680$12436 + assign { } { } + assign $0\alu_spr0_spr_op__is_32bit[0:0] \alu_spr0_spr_op__is_32bit$next + sync posedge \coresync_clk + update \alu_spr0_spr_op__is_32bit $0\alu_spr0_spr_op__is_32bit[0:0] + end + attribute \src "libresoc.v:174682.3-174683.39" + process $proc$libresoc.v:174682$12437 + assign { } { } + assign $0\req_l_r_req[5:0] \req_l_r_req$next + sync posedge \coresync_clk + update \req_l_r_req $0\req_l_r_req[5:0] + end + attribute \src "libresoc.v:174684.3-174685.39" + process $proc$libresoc.v:174684$12438 + assign { } { } + assign $0\req_l_s_req[5:0] \req_l_s_req$next + sync posedge \coresync_clk + update \req_l_s_req $0\req_l_s_req[5:0] + end + attribute \src "libresoc.v:174686.3-174687.39" + process $proc$libresoc.v:174686$12439 + assign { } { } + assign $0\src_l_r_src[5:0] \src_l_r_src$next + sync posedge \coresync_clk + update \src_l_r_src $0\src_l_r_src[5:0] + end + attribute \src "libresoc.v:174688.3-174689.39" + process $proc$libresoc.v:174688$12440 + assign { } { } + assign $0\src_l_s_src[5:0] \src_l_s_src$next + sync posedge \coresync_clk + update \src_l_s_src $0\src_l_s_src[5:0] + end + attribute \src "libresoc.v:174690.3-174691.39" + process $proc$libresoc.v:174690$12441 + assign { } { } + assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next + sync posedge \coresync_clk + update \opc_l_r_opc $0\opc_l_r_opc[0:0] + end + attribute \src "libresoc.v:174692.3-174693.39" + process $proc$libresoc.v:174692$12442 + assign { } { } + assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next + sync posedge \coresync_clk + update \opc_l_s_opc $0\opc_l_s_opc[0:0] + end + attribute \src "libresoc.v:174694.3-174695.39" + process $proc$libresoc.v:174694$12443 + assign { } { } + assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next + sync posedge \coresync_clk + update \rst_l_r_rst $0\rst_l_r_rst[0:0] + end + attribute \src "libresoc.v:174696.3-174697.39" + process $proc$libresoc.v:174696$12444 + assign { } { } + assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next + sync posedge \coresync_clk + update \rst_l_s_rst $0\rst_l_s_rst[0:0] + end + attribute \src "libresoc.v:174698.3-174699.41" + process $proc$libresoc.v:174698$12445 + assign { } { } + assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next + sync posedge \coresync_clk + update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] + end + attribute \src "libresoc.v:174700.3-174701.41" + process $proc$libresoc.v:174700$12446 + assign { } { } + assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next + sync posedge \coresync_clk + update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] + end + attribute \src "libresoc.v:174702.3-174703.37" + process $proc$libresoc.v:174702$12447 + assign { } { } + assign $0\prev_wr_go[5:0] \prev_wr_go$next + sync posedge \coresync_clk + update \prev_wr_go $0\prev_wr_go[5:0] + end + attribute \src "libresoc.v:174704.3-174705.40" + process $proc$libresoc.v:174704$12448 + assign { } { } + assign $0\alu_done_dly[0:0] \alu_spr0_n_valid_o + sync posedge \coresync_clk + update \alu_done_dly $0\alu_done_dly[0:0] + end + attribute \src "libresoc.v:174706.3-174707.25" + process $proc$libresoc.v:174706$12449 + assign { } { } + assign $0\all_rd_dly[0:0] \$14 + sync posedge \coresync_clk + update \all_rd_dly $0\all_rd_dly[0:0] + end + attribute \src "libresoc.v:174786.3-174795.6" + process $proc$libresoc.v:174786$12450 + assign { } { } + assign { } { } + assign $0\req_done[0:0] $1\req_done[0:0] + attribute \src "libresoc.v:174787.5-174787.29" + switch \initial + attribute \src "libresoc.v:174787.9-174787.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + switch \$58 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\req_done[0:0] 1'1 + case + assign $1\req_done[0:0] \$50 + end + sync always + update \req_done $0\req_done[0:0] + end + attribute \src "libresoc.v:174796.3-174804.6" + process $proc$libresoc.v:174796$12451 + assign { } { } + assign { } { } + assign $0\rok_l_s_rdok$next[0:0]$12452 $1\rok_l_s_rdok$next[0:0]$12453 + attribute \src "libresoc.v:174797.5-174797.29" + switch \initial + attribute \src "libresoc.v:174797.9-174797.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rok_l_s_rdok$next[0:0]$12453 1'0 + case + assign $1\rok_l_s_rdok$next[0:0]$12453 \cu_issue_i + end + sync always + update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$12452 + end + attribute \src "libresoc.v:174805.3-174813.6" + process $proc$libresoc.v:174805$12454 + assign { } { } + assign { } { } + assign $0\rok_l_r_rdok$next[0:0]$12455 $1\rok_l_r_rdok$next[0:0]$12456 + attribute \src "libresoc.v:174806.5-174806.29" + switch \initial + attribute \src "libresoc.v:174806.9-174806.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rok_l_r_rdok$next[0:0]$12456 1'1 + case + assign $1\rok_l_r_rdok$next[0:0]$12456 \$68 + end + sync always + update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$12455 + end + attribute \src "libresoc.v:174814.3-174822.6" + process $proc$libresoc.v:174814$12457 + assign { } { } + assign { } { } + assign $0\rst_l_s_rst$next[0:0]$12458 $1\rst_l_s_rst$next[0:0]$12459 + attribute \src "libresoc.v:174815.5-174815.29" + switch \initial + attribute \src "libresoc.v:174815.9-174815.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rst_l_s_rst$next[0:0]$12459 1'0 + case + assign $1\rst_l_s_rst$next[0:0]$12459 \all_rd + end + sync always + update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$12458 + end + attribute \src "libresoc.v:174823.3-174831.6" + process $proc$libresoc.v:174823$12460 + assign { } { } + assign { } { } + assign $0\rst_l_r_rst$next[0:0]$12461 $1\rst_l_r_rst$next[0:0]$12462 + attribute \src "libresoc.v:174824.5-174824.29" + switch \initial + attribute \src "libresoc.v:174824.9-174824.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rst_l_r_rst$next[0:0]$12462 1'1 + case + assign $1\rst_l_r_rst$next[0:0]$12462 \rst_r + end + sync always + update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$12461 + end + attribute \src "libresoc.v:174832.3-174840.6" + process $proc$libresoc.v:174832$12463 + assign { } { } + assign { } { } + assign $0\opc_l_s_opc$next[0:0]$12464 $1\opc_l_s_opc$next[0:0]$12465 + attribute \src "libresoc.v:174833.5-174833.29" + switch \initial + attribute \src "libresoc.v:174833.9-174833.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\opc_l_s_opc$next[0:0]$12465 1'0 + case + assign $1\opc_l_s_opc$next[0:0]$12465 \cu_issue_i + end + sync always + update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$12464 + end + attribute \src "libresoc.v:174841.3-174849.6" + process $proc$libresoc.v:174841$12466 + assign { } { } + assign { } { } + assign $0\opc_l_r_opc$next[0:0]$12467 $1\opc_l_r_opc$next[0:0]$12468 + attribute \src "libresoc.v:174842.5-174842.29" + switch \initial + attribute \src "libresoc.v:174842.9-174842.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\opc_l_r_opc$next[0:0]$12468 1'1 + case + assign $1\opc_l_r_opc$next[0:0]$12468 \req_done + end + sync always + update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$12467 + end + attribute \src "libresoc.v:174850.3-174858.6" + process $proc$libresoc.v:174850$12469 + assign { } { } + assign { } { } + assign $0\src_l_s_src$next[5:0]$12470 $1\src_l_s_src$next[5:0]$12471 + attribute \src "libresoc.v:174851.5-174851.29" + switch \initial + attribute \src "libresoc.v:174851.9-174851.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_l_s_src$next[5:0]$12471 6'000000 + case + assign $1\src_l_s_src$next[5:0]$12471 { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i } + end + sync always + update \src_l_s_src$next $0\src_l_s_src$next[5:0]$12470 + end + attribute \src "libresoc.v:174859.3-174867.6" + process $proc$libresoc.v:174859$12472 + assign { } { } + assign { } { } + assign $0\src_l_r_src$next[5:0]$12473 $1\src_l_r_src$next[5:0]$12474 + attribute \src "libresoc.v:174860.5-174860.29" + switch \initial + attribute \src "libresoc.v:174860.9-174860.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_l_r_src$next[5:0]$12474 6'111111 + case + assign $1\src_l_r_src$next[5:0]$12474 \reset_r + end + sync always + update \src_l_r_src$next $0\src_l_r_src$next[5:0]$12473 + end + attribute \src "libresoc.v:174868.3-174876.6" + process $proc$libresoc.v:174868$12475 + assign { } { } + assign { } { } + assign $0\req_l_s_req$next[5:0]$12476 $1\req_l_s_req$next[5:0]$12477 + attribute \src "libresoc.v:174869.5-174869.29" + switch \initial + attribute \src "libresoc.v:174869.9-174869.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\req_l_s_req$next[5:0]$12477 6'000000 + case + assign $1\req_l_s_req$next[5:0]$12477 \$70 + end + sync always + update \req_l_s_req$next $0\req_l_s_req$next[5:0]$12476 + end + attribute \src "libresoc.v:174877.3-174885.6" + process $proc$libresoc.v:174877$12478 + assign { } { } + assign { } { } + assign $0\req_l_r_req$next[5:0]$12479 $1\req_l_r_req$next[5:0]$12480 + attribute \src "libresoc.v:174878.5-174878.29" + switch \initial + attribute \src "libresoc.v:174878.9-174878.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\req_l_r_req$next[5:0]$12480 6'111111 + case + assign $1\req_l_r_req$next[5:0]$12480 \$72 + end + sync always + update \req_l_r_req$next $0\req_l_r_req$next[5:0]$12479 + end + attribute \src "libresoc.v:174886.3-174898.6" + process $proc$libresoc.v:174886$12481 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\alu_spr0_spr_op__fn_unit$next[11:0]$12482 $1\alu_spr0_spr_op__fn_unit$next[11:0]$12486 + assign $0\alu_spr0_spr_op__insn$next[31:0]$12483 $1\alu_spr0_spr_op__insn$next[31:0]$12487 + assign $0\alu_spr0_spr_op__insn_type$next[6:0]$12484 $1\alu_spr0_spr_op__insn_type$next[6:0]$12488 + assign $0\alu_spr0_spr_op__is_32bit$next[0:0]$12485 $1\alu_spr0_spr_op__is_32bit$next[0:0]$12489 + attribute \src "libresoc.v:174887.5-174887.29" + switch \initial + attribute \src "libresoc.v:174887.9-174887.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\alu_spr0_spr_op__is_32bit$next[0:0]$12489 $1\alu_spr0_spr_op__insn$next[31:0]$12487 $1\alu_spr0_spr_op__fn_unit$next[11:0]$12486 $1\alu_spr0_spr_op__insn_type$next[6:0]$12488 } { \oper_i_alu_spr0__is_32bit \oper_i_alu_spr0__insn \oper_i_alu_spr0__fn_unit \oper_i_alu_spr0__insn_type } + case + assign $1\alu_spr0_spr_op__fn_unit$next[11:0]$12486 \alu_spr0_spr_op__fn_unit + assign $1\alu_spr0_spr_op__insn$next[31:0]$12487 \alu_spr0_spr_op__insn + assign $1\alu_spr0_spr_op__insn_type$next[6:0]$12488 \alu_spr0_spr_op__insn_type + assign $1\alu_spr0_spr_op__is_32bit$next[0:0]$12489 \alu_spr0_spr_op__is_32bit + end + sync always + update \alu_spr0_spr_op__fn_unit$next $0\alu_spr0_spr_op__fn_unit$next[11:0]$12482 + update \alu_spr0_spr_op__insn$next $0\alu_spr0_spr_op__insn$next[31:0]$12483 + update \alu_spr0_spr_op__insn_type$next $0\alu_spr0_spr_op__insn_type$next[6:0]$12484 + update \alu_spr0_spr_op__is_32bit$next $0\alu_spr0_spr_op__is_32bit$next[0:0]$12485 + end + attribute \src "libresoc.v:174899.3-174920.6" + process $proc$libresoc.v:174899$12490 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r0__o$next[63:0]$12491 $2\data_r0__o$next[63:0]$12495 + assign { } { } + assign $0\data_r0__o_ok$next[0:0]$12492 $3\data_r0__o_ok$next[0:0]$12497 + attribute \src "libresoc.v:174900.5-174900.29" + switch \initial + attribute \src "libresoc.v:174900.9-174900.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r0__o_ok$next[0:0]$12494 $1\data_r0__o$next[63:0]$12493 } { \o_ok \alu_spr0_o } + case + assign $1\data_r0__o$next[63:0]$12493 \data_r0__o + assign $1\data_r0__o_ok$next[0:0]$12494 \data_r0__o_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r0__o_ok$next[0:0]$12496 $2\data_r0__o$next[63:0]$12495 } 65'00000000000000000000000000000000000000000000000000000000000000000 + case + assign $2\data_r0__o$next[63:0]$12495 $1\data_r0__o$next[63:0]$12493 + assign $2\data_r0__o_ok$next[0:0]$12496 $1\data_r0__o_ok$next[0:0]$12494 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r0__o_ok$next[0:0]$12497 1'0 + case + assign $3\data_r0__o_ok$next[0:0]$12497 $2\data_r0__o_ok$next[0:0]$12496 + end + sync always + update \data_r0__o$next $0\data_r0__o$next[63:0]$12491 + update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$12492 + end + attribute \src "libresoc.v:174921.3-174942.6" + process $proc$libresoc.v:174921$12498 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r1__spr1$next[63:0]$12499 $2\data_r1__spr1$next[63:0]$12503 + assign { } { } + assign $0\data_r1__spr1_ok$next[0:0]$12500 $3\data_r1__spr1_ok$next[0:0]$12505 + attribute \src "libresoc.v:174922.5-174922.29" + switch \initial + attribute \src "libresoc.v:174922.9-174922.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r1__spr1_ok$next[0:0]$12502 $1\data_r1__spr1$next[63:0]$12501 } { \spr1_ok \alu_spr0_spr1 } + case + assign $1\data_r1__spr1$next[63:0]$12501 \data_r1__spr1 + assign $1\data_r1__spr1_ok$next[0:0]$12502 \data_r1__spr1_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r1__spr1_ok$next[0:0]$12504 $2\data_r1__spr1$next[63:0]$12503 } 65'00000000000000000000000000000000000000000000000000000000000000000 + case + assign $2\data_r1__spr1$next[63:0]$12503 $1\data_r1__spr1$next[63:0]$12501 + assign $2\data_r1__spr1_ok$next[0:0]$12504 $1\data_r1__spr1_ok$next[0:0]$12502 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r1__spr1_ok$next[0:0]$12505 1'0 + case + assign $3\data_r1__spr1_ok$next[0:0]$12505 $2\data_r1__spr1_ok$next[0:0]$12504 + end + sync always + update \data_r1__spr1$next $0\data_r1__spr1$next[63:0]$12499 + update \data_r1__spr1_ok$next $0\data_r1__spr1_ok$next[0:0]$12500 + end + attribute \src "libresoc.v:174943.3-174964.6" + process $proc$libresoc.v:174943$12506 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r2__fast1$next[63:0]$12507 $2\data_r2__fast1$next[63:0]$12511 + assign { } { } + assign $0\data_r2__fast1_ok$next[0:0]$12508 $3\data_r2__fast1_ok$next[0:0]$12513 + attribute \src "libresoc.v:174944.5-174944.29" + switch \initial + attribute \src "libresoc.v:174944.9-174944.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r2__fast1_ok$next[0:0]$12510 $1\data_r2__fast1$next[63:0]$12509 } { \fast1_ok \alu_spr0_fast1 } + case + assign $1\data_r2__fast1$next[63:0]$12509 \data_r2__fast1 + assign $1\data_r2__fast1_ok$next[0:0]$12510 \data_r2__fast1_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r2__fast1_ok$next[0:0]$12512 $2\data_r2__fast1$next[63:0]$12511 } 65'00000000000000000000000000000000000000000000000000000000000000000 + case + assign $2\data_r2__fast1$next[63:0]$12511 $1\data_r2__fast1$next[63:0]$12509 + assign $2\data_r2__fast1_ok$next[0:0]$12512 $1\data_r2__fast1_ok$next[0:0]$12510 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r2__fast1_ok$next[0:0]$12513 1'0 + case + assign $3\data_r2__fast1_ok$next[0:0]$12513 $2\data_r2__fast1_ok$next[0:0]$12512 + end + sync always + update \data_r2__fast1$next $0\data_r2__fast1$next[63:0]$12507 + update \data_r2__fast1_ok$next $0\data_r2__fast1_ok$next[0:0]$12508 + end + attribute \src "libresoc.v:174965.3-174986.6" + process $proc$libresoc.v:174965$12514 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r3__xer_so$next[0:0]$12515 $2\data_r3__xer_so$next[0:0]$12519 + assign { } { } + assign $0\data_r3__xer_so_ok$next[0:0]$12516 $3\data_r3__xer_so_ok$next[0:0]$12521 + attribute \src "libresoc.v:174966.5-174966.29" + switch \initial + attribute \src "libresoc.v:174966.9-174966.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r3__xer_so_ok$next[0:0]$12518 $1\data_r3__xer_so$next[0:0]$12517 } { \xer_so_ok \alu_spr0_xer_so } + case + assign $1\data_r3__xer_so$next[0:0]$12517 \data_r3__xer_so + assign $1\data_r3__xer_so_ok$next[0:0]$12518 \data_r3__xer_so_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r3__xer_so_ok$next[0:0]$12520 $2\data_r3__xer_so$next[0:0]$12519 } 2'00 + case + assign $2\data_r3__xer_so$next[0:0]$12519 $1\data_r3__xer_so$next[0:0]$12517 + assign $2\data_r3__xer_so_ok$next[0:0]$12520 $1\data_r3__xer_so_ok$next[0:0]$12518 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r3__xer_so_ok$next[0:0]$12521 1'0 + case + assign $3\data_r3__xer_so_ok$next[0:0]$12521 $2\data_r3__xer_so_ok$next[0:0]$12520 + end + sync always + update \data_r3__xer_so$next $0\data_r3__xer_so$next[0:0]$12515 + update \data_r3__xer_so_ok$next $0\data_r3__xer_so_ok$next[0:0]$12516 + end + attribute \src "libresoc.v:174987.3-175008.6" + process $proc$libresoc.v:174987$12522 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r4__xer_ov$next[1:0]$12523 $2\data_r4__xer_ov$next[1:0]$12527 + assign { } { } + assign $0\data_r4__xer_ov_ok$next[0:0]$12524 $3\data_r4__xer_ov_ok$next[0:0]$12529 + attribute \src "libresoc.v:174988.5-174988.29" + switch \initial + attribute \src "libresoc.v:174988.9-174988.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r4__xer_ov_ok$next[0:0]$12526 $1\data_r4__xer_ov$next[1:0]$12525 } { \xer_ov_ok \alu_spr0_xer_ov } + case + assign $1\data_r4__xer_ov$next[1:0]$12525 \data_r4__xer_ov + assign $1\data_r4__xer_ov_ok$next[0:0]$12526 \data_r4__xer_ov_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r4__xer_ov_ok$next[0:0]$12528 $2\data_r4__xer_ov$next[1:0]$12527 } 3'000 + case + assign $2\data_r4__xer_ov$next[1:0]$12527 $1\data_r4__xer_ov$next[1:0]$12525 + assign $2\data_r4__xer_ov_ok$next[0:0]$12528 $1\data_r4__xer_ov_ok$next[0:0]$12526 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r4__xer_ov_ok$next[0:0]$12529 1'0 + case + assign $3\data_r4__xer_ov_ok$next[0:0]$12529 $2\data_r4__xer_ov_ok$next[0:0]$12528 + end + sync always + update \data_r4__xer_ov$next $0\data_r4__xer_ov$next[1:0]$12523 + update \data_r4__xer_ov_ok$next $0\data_r4__xer_ov_ok$next[0:0]$12524 + end + attribute \src "libresoc.v:175009.3-175030.6" + process $proc$libresoc.v:175009$12530 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r5__xer_ca$next[1:0]$12531 $2\data_r5__xer_ca$next[1:0]$12535 + assign { } { } + assign $0\data_r5__xer_ca_ok$next[0:0]$12532 $3\data_r5__xer_ca_ok$next[0:0]$12537 + attribute \src "libresoc.v:175010.5-175010.29" + switch \initial + attribute \src "libresoc.v:175010.9-175010.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r5__xer_ca_ok$next[0:0]$12534 $1\data_r5__xer_ca$next[1:0]$12533 } { \xer_ca_ok \alu_spr0_xer_ca } + case + assign $1\data_r5__xer_ca$next[1:0]$12533 \data_r5__xer_ca + assign $1\data_r5__xer_ca_ok$next[0:0]$12534 \data_r5__xer_ca_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r5__xer_ca_ok$next[0:0]$12536 $2\data_r5__xer_ca$next[1:0]$12535 } 3'000 + case + assign $2\data_r5__xer_ca$next[1:0]$12535 $1\data_r5__xer_ca$next[1:0]$12533 + assign $2\data_r5__xer_ca_ok$next[0:0]$12536 $1\data_r5__xer_ca_ok$next[0:0]$12534 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r5__xer_ca_ok$next[0:0]$12537 1'0 + case + assign $3\data_r5__xer_ca_ok$next[0:0]$12537 $2\data_r5__xer_ca_ok$next[0:0]$12536 + end + sync always + update \data_r5__xer_ca$next $0\data_r5__xer_ca$next[1:0]$12531 + update \data_r5__xer_ca_ok$next $0\data_r5__xer_ca_ok$next[0:0]$12532 + end + attribute \src "libresoc.v:175031.3-175040.6" + process $proc$libresoc.v:175031$12538 + assign { } { } + assign { } { } + assign $0\src_r0$next[63:0]$12539 $1\src_r0$next[63:0]$12540 + attribute \src "libresoc.v:175032.5-175032.29" + switch \initial + attribute \src "libresoc.v:175032.9-175032.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch \src_l_q_src [0] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r0$next[63:0]$12540 \src1_i + case + assign $1\src_r0$next[63:0]$12540 \src_r0 + end + sync always + update \src_r0$next $0\src_r0$next[63:0]$12539 + end + attribute \src "libresoc.v:175041.3-175050.6" + process $proc$libresoc.v:175041$12541 + assign { } { } + assign { } { } + assign $0\src_r1$next[63:0]$12542 $1\src_r1$next[63:0]$12543 + attribute \src "libresoc.v:175042.5-175042.29" + switch \initial + attribute \src "libresoc.v:175042.9-175042.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch \src_l_q_src [1] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r1$next[63:0]$12543 \src2_i + case + assign $1\src_r1$next[63:0]$12543 \src_r1 + end + sync always + update \src_r1$next $0\src_r1$next[63:0]$12542 + end + attribute \src "libresoc.v:175051.3-175060.6" + process $proc$libresoc.v:175051$12544 + assign { } { } + assign { } { } + assign $0\src_r2$next[63:0]$12545 $1\src_r2$next[63:0]$12546 + attribute \src "libresoc.v:175052.5-175052.29" + switch \initial + attribute \src "libresoc.v:175052.9-175052.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch \src_l_q_src [2] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r2$next[63:0]$12546 \src3_i + case + assign $1\src_r2$next[63:0]$12546 \src_r2 + end + sync always + update \src_r2$next $0\src_r2$next[63:0]$12545 + end + attribute \src "libresoc.v:175061.3-175070.6" + process $proc$libresoc.v:175061$12547 + assign { } { } + assign { } { } + assign $0\src_r3$next[0:0]$12548 $1\src_r3$next[0:0]$12549 + attribute \src "libresoc.v:175062.5-175062.29" + switch \initial + attribute \src "libresoc.v:175062.9-175062.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch \src_l_q_src [3] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r3$next[0:0]$12549 \src4_i + case + assign $1\src_r3$next[0:0]$12549 \src_r3 + end + sync always + update \src_r3$next $0\src_r3$next[0:0]$12548 + end + attribute \src "libresoc.v:175071.3-175080.6" + process $proc$libresoc.v:175071$12550 + assign { } { } + assign { } { } + assign $0\src_r4$next[1:0]$12551 $1\src_r4$next[1:0]$12552 + attribute \src "libresoc.v:175072.5-175072.29" + switch \initial + attribute \src "libresoc.v:175072.9-175072.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch \src_l_q_src [4] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r4$next[1:0]$12552 \src5_i + case + assign $1\src_r4$next[1:0]$12552 \src_r4 + end + sync always + update \src_r4$next $0\src_r4$next[1:0]$12551 + end + attribute \src "libresoc.v:175081.3-175090.6" + process $proc$libresoc.v:175081$12553 + assign { } { } + assign { } { } + assign $0\src_r5$next[1:0]$12554 $1\src_r5$next[1:0]$12555 + attribute \src "libresoc.v:175082.5-175082.29" + switch \initial + attribute \src "libresoc.v:175082.9-175082.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch \src_l_q_src [5] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r5$next[1:0]$12555 \src6_i + case + assign $1\src_r5$next[1:0]$12555 \src_r5 + end + sync always + update \src_r5$next $0\src_r5$next[1:0]$12554 + end + attribute \src "libresoc.v:175091.3-175099.6" + process $proc$libresoc.v:175091$12556 + assign { } { } + assign { } { } + assign $0\alui_l_r_alui$next[0:0]$12557 $1\alui_l_r_alui$next[0:0]$12558 + attribute \src "libresoc.v:175092.5-175092.29" + switch \initial + attribute \src "libresoc.v:175092.9-175092.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\alui_l_r_alui$next[0:0]$12558 1'1 + case + assign $1\alui_l_r_alui$next[0:0]$12558 \$98 + end + sync always + update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$12557 + end + attribute \src "libresoc.v:175100.3-175108.6" + process $proc$libresoc.v:175100$12559 + assign { } { } + assign { } { } + assign $0\alu_l_r_alu$next[0:0]$12560 $1\alu_l_r_alu$next[0:0]$12561 + attribute \src "libresoc.v:175101.5-175101.29" + switch \initial + attribute \src "libresoc.v:175101.9-175101.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\alu_l_r_alu$next[0:0]$12561 1'1 + case + assign $1\alu_l_r_alu$next[0:0]$12561 \$100 + end + sync always + update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$12560 + end + attribute \src "libresoc.v:175109.3-175118.6" + process $proc$libresoc.v:175109$12562 + assign { } { } + assign { } { } + assign $0\dest1_o[63:0] $1\dest1_o[63:0] + attribute \src "libresoc.v:175110.5-175110.29" + switch \initial + attribute \src "libresoc.v:175110.9-175110.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$126 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest1_o[63:0] \data_r0__o + case + assign $1\dest1_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \dest1_o $0\dest1_o[63:0] + end + attribute \src "libresoc.v:175119.3-175128.6" + process $proc$libresoc.v:175119$12563 + assign { } { } + assign { } { } + assign $0\dest2_o[63:0] $1\dest2_o[63:0] + attribute \src "libresoc.v:175120.5-175120.29" + switch \initial + attribute \src "libresoc.v:175120.9-175120.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$128 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest2_o[63:0] \data_r1__spr1 + case + assign $1\dest2_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \dest2_o $0\dest2_o[63:0] + end + attribute \src "libresoc.v:175129.3-175138.6" + process $proc$libresoc.v:175129$12564 + assign { } { } + assign { } { } + assign $0\dest3_o[63:0] $1\dest3_o[63:0] + attribute \src "libresoc.v:175130.5-175130.29" + switch \initial + attribute \src "libresoc.v:175130.9-175130.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$130 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest3_o[63:0] \data_r2__fast1 + case + assign $1\dest3_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \dest3_o $0\dest3_o[63:0] + end + attribute \src "libresoc.v:175139.3-175148.6" + process $proc$libresoc.v:175139$12565 + assign { } { } + assign { } { } + assign $0\dest4_o[0:0] $1\dest4_o[0:0] + attribute \src "libresoc.v:175140.5-175140.29" + switch \initial + attribute \src "libresoc.v:175140.9-175140.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$132 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest4_o[0:0] \data_r3__xer_so + case + assign $1\dest4_o[0:0] 1'0 + end + sync always + update \dest4_o $0\dest4_o[0:0] + end + attribute \src "libresoc.v:175149.3-175158.6" + process $proc$libresoc.v:175149$12566 + assign { } { } + assign { } { } + assign $0\dest5_o[1:0] $1\dest5_o[1:0] + attribute \src "libresoc.v:175150.5-175150.29" + switch \initial + attribute \src "libresoc.v:175150.9-175150.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$134 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest5_o[1:0] \data_r4__xer_ov + case + assign $1\dest5_o[1:0] 2'00 + end + sync always + update \dest5_o $0\dest5_o[1:0] + end + attribute \src "libresoc.v:175159.3-175168.6" + process $proc$libresoc.v:175159$12567 + assign { } { } + assign { } { } + assign $0\dest6_o[1:0] $1\dest6_o[1:0] + attribute \src "libresoc.v:175160.5-175160.29" + switch \initial + attribute \src "libresoc.v:175160.9-175160.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$136 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest6_o[1:0] \data_r5__xer_ca + case + assign $1\dest6_o[1:0] 2'00 + end + sync always + update \dest6_o $0\dest6_o[1:0] + end + attribute \src "libresoc.v:175169.3-175177.6" + process $proc$libresoc.v:175169$12568 + assign { } { } + assign { } { } + assign $0\prev_wr_go$next[5:0]$12569 $1\prev_wr_go$next[5:0]$12570 + attribute \src "libresoc.v:175170.5-175170.29" + switch \initial + attribute \src "libresoc.v:175170.9-175170.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\prev_wr_go$next[5:0]$12570 6'000000 + case + assign $1\prev_wr_go$next[5:0]$12570 \$24 + end + sync always + update \prev_wr_go$next $0\prev_wr_go$next[5:0]$12569 + end + connect \$9 $not$libresoc.v:174568$12347_Y + connect \$100 $and$libresoc.v:174569$12348_Y + connect \$102 $and$libresoc.v:174570$12349_Y + connect \$104 $and$libresoc.v:174571$12350_Y + connect \$106 $not$libresoc.v:174572$12351_Y + connect \$108 $and$libresoc.v:174573$12352_Y + connect \$110 $and$libresoc.v:174574$12353_Y + connect \$112 $and$libresoc.v:174575$12354_Y + connect \$114 $and$libresoc.v:174576$12355_Y + connect \$116 $and$libresoc.v:174577$12356_Y + connect \$118 $and$libresoc.v:174578$12357_Y + connect \$11 $or$libresoc.v:174579$12358_Y + connect \$120 $and$libresoc.v:174580$12359_Y + connect \$122 $and$libresoc.v:174581$12360_Y + connect \$124 $and$libresoc.v:174582$12361_Y + connect \$126 $and$libresoc.v:174583$12362_Y + connect \$128 $and$libresoc.v:174584$12363_Y + connect \$8 $reduce_and$libresoc.v:174585$12364_Y + connect \$130 $and$libresoc.v:174586$12365_Y + connect \$132 $and$libresoc.v:174587$12366_Y + connect \$134 $and$libresoc.v:174588$12367_Y + connect \$136 $and$libresoc.v:174589$12368_Y + connect \$14 $and$libresoc.v:174590$12369_Y + connect \$16 $not$libresoc.v:174591$12370_Y + connect \$18 $and$libresoc.v:174592$12371_Y + connect \$20 $not$libresoc.v:174593$12372_Y + connect \$22 $and$libresoc.v:174594$12373_Y + connect \$24 $and$libresoc.v:174595$12374_Y + connect \$28 $not$libresoc.v:174596$12375_Y + connect \$30 $and$libresoc.v:174597$12376_Y + connect \$27 $reduce_or$libresoc.v:174598$12377_Y + connect \$26 $not$libresoc.v:174599$12378_Y + connect \$34 $and$libresoc.v:174600$12379_Y + connect \$36 $reduce_or$libresoc.v:174601$12380_Y + connect \$38 $reduce_or$libresoc.v:174602$12381_Y + connect \$40 $or$libresoc.v:174603$12382_Y + connect \$42 $not$libresoc.v:174604$12383_Y + connect \$44 $and$libresoc.v:174605$12384_Y + connect \$46 $and$libresoc.v:174606$12385_Y + connect \$48 $eq$libresoc.v:174607$12386_Y + connect \$50 $and$libresoc.v:174608$12387_Y + connect \$52 $eq$libresoc.v:174609$12388_Y + connect \$54 $and$libresoc.v:174610$12389_Y + connect \$56 $and$libresoc.v:174611$12390_Y + connect \$58 $and$libresoc.v:174612$12391_Y + connect \$60 $or$libresoc.v:174613$12392_Y + connect \$62 $or$libresoc.v:174614$12393_Y + connect \$64 $or$libresoc.v:174615$12394_Y + connect \$66 $or$libresoc.v:174616$12395_Y + connect \$68 $and$libresoc.v:174617$12396_Y + connect \$6 $and$libresoc.v:174618$12397_Y + connect \$70 $and$libresoc.v:174619$12398_Y + connect \$72 $or$libresoc.v:174620$12399_Y + connect \$74 $and$libresoc.v:174621$12400_Y + connect \$76 $and$libresoc.v:174622$12401_Y + connect \$78 $and$libresoc.v:174623$12402_Y + connect \$80 $and$libresoc.v:174624$12403_Y + connect \$82 $and$libresoc.v:174625$12404_Y + connect \$84 $and$libresoc.v:174626$12405_Y + connect \$86 $ternary$libresoc.v:174627$12406_Y + connect \$88 $ternary$libresoc.v:174628$12407_Y + connect \$90 $ternary$libresoc.v:174629$12408_Y + connect \$92 $ternary$libresoc.v:174630$12409_Y + connect \$94 $ternary$libresoc.v:174631$12410_Y + connect \$96 $ternary$libresoc.v:174632$12411_Y + connect \$98 $and$libresoc.v:174633$12412_Y + connect \cu_go_die_i 1'0 + connect \cu_shadown_i 1'1 + connect \cu_wr__rel_o \$124 + connect \cu_rd__rel_o \$108 + connect \cu_busy_o \opc_l_q_opc + connect \alu_l_s_alu \all_rd_pulse + connect \alu_spr0_n_ready_i \alu_l_q_alu + connect \alui_l_s_alui \all_rd_pulse + connect \alu_spr0_p_valid_i \alui_l_q_alui + connect \alu_spr0_xer_ca$5 \$96 + connect \alu_spr0_xer_ov$4 \$94 + connect \alu_spr0_xer_so$3 \$92 + connect \alu_spr0_fast1$2 \$90 + connect \alu_spr0_spr1$1 \$88 + connect \alu_spr0_ra \$86 + connect \cu_wrmask_o { \$84 \$82 \$80 \$78 \$76 \$74 } + connect \reset_r \$66 + connect \reset_w \$64 + connect \rst_r \$62 + connect \reset \$60 + connect \wr_any \$40 + connect \cu_done_o \$34 + connect \alu_pulsem { \alu_pulse \alu_pulse \alu_pulse \alu_pulse \alu_pulse \alu_pulse } + connect \alu_pulse \alu_done_rise + connect \alu_done_rise \$22 + connect \alu_done_dly$next \alu_done + connect \alu_done \alu_spr0_n_valid_o + connect \all_rd_pulse \all_rd_rise + connect \all_rd_rise \$18 + connect \all_rd_dly$next \all_rd + connect \all_rd \$14 +end +attribute \src "libresoc.v:175213.1-175727.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.alu_spr0.pipe.spr_main" +attribute \generator "nMigen" +module \spr_main + attribute \src "libresoc.v:175480.3-175495.6" + wire width 64 $0\fast1$7[63:0]$12617 + attribute \src "libresoc.v:175557.3-175572.6" + wire $0\fast1_ok[0:0] + attribute \src "libresoc.v:175214.7-175214.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:175515.3-175556.6" + wire width 64 $0\o[63:0] + attribute \src "libresoc.v:175515.3-175556.6" + wire $0\o_ok[0:0] + attribute \src "libresoc.v:175705.3-175723.6" + wire width 64 $0\spr1$6[63:0]$12642 + attribute \src "libresoc.v:175496.3-175514.6" + wire $0\spr1_ok[0:0] + attribute \src "libresoc.v:175660.3-175683.6" + wire width 2 $0\xer_ca$10[1:0]$12636 + attribute \src "libresoc.v:175684.3-175704.6" + wire $0\xer_ca_ok[0:0] + attribute \src "libresoc.v:175615.3-175638.6" + wire width 2 $0\xer_ov$9[1:0]$12630 + attribute \src "libresoc.v:175639.3-175659.6" + wire $0\xer_ov_ok[0:0] + attribute \src "libresoc.v:175573.3-175593.6" + wire $0\xer_so$8[0:0]$12624 + attribute \src "libresoc.v:175594.3-175614.6" + wire $0\xer_so_ok[0:0] + attribute \src "libresoc.v:175480.3-175495.6" + wire width 64 $1\fast1$7[63:0]$12618 + attribute \src "libresoc.v:175557.3-175572.6" + wire $1\fast1_ok[0:0] + attribute \src "libresoc.v:175515.3-175556.6" + wire width 64 $1\o[63:0] + attribute \src "libresoc.v:175515.3-175556.6" + wire $1\o_ok[0:0] + attribute \src "libresoc.v:175705.3-175723.6" + wire width 64 $1\spr1$6[63:0]$12643 + attribute \src "libresoc.v:175496.3-175514.6" + wire $1\spr1_ok[0:0] + attribute \src "libresoc.v:175660.3-175683.6" + wire width 2 $1\xer_ca$10[1:0]$12637 + attribute \src "libresoc.v:175684.3-175704.6" + wire $1\xer_ca_ok[0:0] + attribute \src "libresoc.v:175615.3-175638.6" + wire width 2 $1\xer_ov$9[1:0]$12631 + attribute \src "libresoc.v:175639.3-175659.6" + wire $1\xer_ov_ok[0:0] + attribute \src "libresoc.v:175573.3-175593.6" + wire $1\xer_so$8[0:0]$12625 + attribute \src "libresoc.v:175594.3-175614.6" + wire $1\xer_so_ok[0:0] + attribute \src "libresoc.v:175480.3-175495.6" + wire width 64 $2\fast1$7[63:0]$12619 + attribute \src "libresoc.v:175557.3-175572.6" + wire $2\fast1_ok[0:0] + attribute \src "libresoc.v:175515.3-175556.6" + wire width 64 $2\o[63:0] + attribute \src "libresoc.v:175705.3-175723.6" + wire width 64 $2\spr1$6[63:0]$12644 + attribute \src "libresoc.v:175496.3-175514.6" + wire $2\spr1_ok[0:0] + attribute \src "libresoc.v:175660.3-175683.6" + wire width 2 $2\xer_ca$10[1:0]$12638 + attribute \src "libresoc.v:175684.3-175704.6" + wire $2\xer_ca_ok[0:0] + attribute \src "libresoc.v:175615.3-175638.6" + wire width 2 $2\xer_ov$9[1:0]$12632 + attribute \src "libresoc.v:175639.3-175659.6" + wire $2\xer_ov_ok[0:0] + attribute \src "libresoc.v:175573.3-175593.6" + wire $2\xer_so$8[0:0]$12626 + attribute \src "libresoc.v:175594.3-175614.6" + wire $2\xer_so_ok[0:0] + attribute \src "libresoc.v:175515.3-175556.6" + wire width 46 $3\o[63:18] + attribute \src "libresoc.v:175660.3-175683.6" + wire width 2 $3\xer_ca$10[1:0]$12639 + attribute \src "libresoc.v:175684.3-175704.6" + wire $3\xer_ca_ok[0:0] + attribute \src "libresoc.v:175615.3-175638.6" + wire width 2 $3\xer_ov$9[1:0]$12633 + attribute \src "libresoc.v:175639.3-175659.6" + wire $3\xer_ov_ok[0:0] + attribute \src "libresoc.v:175573.3-175593.6" + wire $3\xer_so$8[0:0]$12627 + attribute \src "libresoc.v:175594.3-175614.6" + wire $3\xer_so_ok[0:0] + attribute \src "libresoc.v:175473.18-175473.106" + wire $eq$libresoc.v:175473$12609_Y + attribute \src "libresoc.v:175474.18-175474.106" + wire $eq$libresoc.v:175474$12610_Y + attribute \src "libresoc.v:175475.18-175475.106" + wire $eq$libresoc.v:175475$12611_Y + attribute \src "libresoc.v:175476.18-175476.106" + wire $eq$libresoc.v:175476$12612_Y + attribute \src "libresoc.v:175477.18-175477.106" + wire $eq$libresoc.v:175477$12613_Y + attribute \src "libresoc.v:175478.18-175478.106" + wire $eq$libresoc.v:175478$12614_Y + attribute \src "libresoc.v:175479.18-175479.106" + wire $eq$libresoc.v:175479$12615_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" + wire \$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" + wire \$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:82" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 7 \fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 20 \fast1$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 21 \fast1_ok + attribute \src "libresoc.v:175214.7-175214.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 28 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 11 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 16 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 17 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 5 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:42" + wire width 10 \spr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 6 \spr1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 18 \spr1$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 19 \spr1_ok + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 2 \spr_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 output 13 \spr_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 3 \spr_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 14 \spr_op__insn$4 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \spr_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 12 \spr_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 4 \spr_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 15 \spr_op__is_32bit$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 input 10 \xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 output 26 \xer_ca$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 27 \xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 input 9 \xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 output 24 \xer_ov$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 25 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 8 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 22 \xer_so$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 23 \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" + cell $eq $eq$libresoc.v:175473$12609 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 10 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 10'0000000001 + connect \Y $eq$libresoc.v:175473$12609_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" + cell $eq $eq$libresoc.v:175474$12610 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 10 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 10'0000000001 + connect \Y $eq$libresoc.v:175474$12610_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" + cell $eq $eq$libresoc.v:175475$12611 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 10 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 10'0000000001 + connect \Y $eq$libresoc.v:175475$12611_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" + cell $eq $eq$libresoc.v:175476$12612 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 10 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 10'0000000001 + connect \Y $eq$libresoc.v:175476$12612_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" + cell $eq $eq$libresoc.v:175477$12613 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 10 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 10'0000000001 + connect \Y $eq$libresoc.v:175477$12613_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" + cell $eq $eq$libresoc.v:175478$12614 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 10 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 10'0000000001 + connect \Y $eq$libresoc.v:175478$12614_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:82" + cell $eq $eq$libresoc.v:175479$12615 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 10 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 10'0000000001 + connect \Y $eq$libresoc.v:175479$12615_Y + end + attribute \src "libresoc.v:175214.7-175214.20" + process $proc$libresoc.v:175214$12645 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:175480.3-175495.6" + process $proc$libresoc.v:175480$12616 + assign { } { } + assign { } { } + assign $0\fast1$7[63:0]$12617 $1\fast1$7[63:0]$12618 + attribute \src "libresoc.v:175481.5-175481.29" + switch \initial + attribute \src "libresoc.v:175481.9-175481.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46" + switch \spr_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0110001 + assign { } { } + assign $1\fast1$7[63:0]$12618 $2\fast1$7[63:0]$12619 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" + switch \spr + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 + assign { } { } + assign $2\fast1$7[63:0]$12619 \ra + case + assign $2\fast1$7[63:0]$12619 64'0000000000000000000000000000000000000000000000000000000000000000 + end + case + assign $1\fast1$7[63:0]$12618 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fast1$7 $0\fast1$7[63:0]$12617 + end + attribute \src "libresoc.v:175496.3-175514.6" + process $proc$libresoc.v:175496$12620 + assign { } { } + assign { } { } + assign $0\spr1_ok[0:0] $1\spr1_ok[0:0] + attribute \src "libresoc.v:175497.5-175497.29" + switch \initial + attribute \src "libresoc.v:175497.9-175497.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46" + switch \spr_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0110001 + assign { } { } + assign $1\spr1_ok[0:0] $2\spr1_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" + switch \spr + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 + assign $2\spr1_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\spr1_ok[0:0] 1'1 + end + case + assign $1\spr1_ok[0:0] 1'0 + end + sync always + update \spr1_ok $0\spr1_ok[0:0] + end + attribute \src "libresoc.v:175515.3-175556.6" + process $proc$libresoc.v:175515$12621 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\o_ok[0:0] $1\o_ok[0:0] + assign $0\o[63:0] $1\o[63:0] + attribute \src "libresoc.v:175516.5-175516.29" + switch \initial + attribute \src "libresoc.v:175516.9-175516.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46" + switch \spr_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0101110 + assign { } { } + assign { } { } + assign $1\o_ok[0:0] 1'1 + assign $1\o[63:0] $2\o[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:77" + switch \spr + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 , 10'0100001100 + assign { } { } + assign $2\o[63:0] [17:0] \fast1 [17:0] + assign $2\o[63:0] [63:18] $3\o[63:18] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:82" + switch \$23 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\o[63:18] [45:14] 0 + assign $3\o[63:18] [10:2] 9'000000000 + assign $3\o[63:18] [13] \xer_so + assign $3\o[63:18] [12] \xer_ov [0] + assign $3\o[63:18] [1] \xer_ov [1] + assign $3\o[63:18] [11] \xer_ca [0] + assign $3\o[63:18] [0] \xer_ca [1] + case + assign $3\o[63:18] \fast1 [63:18] + end + attribute \src "libresoc.v:0.0-0.0" + case 10'0100001101 + assign $2\o[63:0] [63:32] 0 + assign $2\o[63:0] [31:0] \fast1 [63:32] + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\o[63:0] \spr1 + end + case + assign $1\o_ok[0:0] 1'0 + assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \o_ok $0\o_ok[0:0] + update \o $0\o[63:0] + end + attribute \src "libresoc.v:175557.3-175572.6" + process $proc$libresoc.v:175557$12622 + assign { } { } + assign { } { } + assign $0\fast1_ok[0:0] $1\fast1_ok[0:0] + attribute \src "libresoc.v:175558.5-175558.29" + switch \initial + attribute \src "libresoc.v:175558.9-175558.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46" + switch \spr_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0110001 + assign { } { } + assign $1\fast1_ok[0:0] $2\fast1_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" + switch \spr + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 + assign { } { } + assign $2\fast1_ok[0:0] 1'1 + case + assign $2\fast1_ok[0:0] 1'0 + end + case + assign $1\fast1_ok[0:0] 1'0 + end + sync always + update \fast1_ok $0\fast1_ok[0:0] + end + attribute \src "libresoc.v:175573.3-175593.6" + process $proc$libresoc.v:175573$12623 + assign { } { } + assign { } { } + assign $0\xer_so$8[0:0]$12624 $1\xer_so$8[0:0]$12625 + attribute \src "libresoc.v:175574.5-175574.29" + switch \initial + attribute \src "libresoc.v:175574.9-175574.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46" + switch \spr_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0110001 + assign { } { } + assign $1\xer_so$8[0:0]$12625 $2\xer_so$8[0:0]$12626 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" + switch \spr + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 + assign { } { } + assign $2\xer_so$8[0:0]$12626 $3\xer_so$8[0:0]$12627 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" + switch \$11 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\xer_so$8[0:0]$12627 \ra [31] + case + assign $3\xer_so$8[0:0]$12627 1'0 + end + case + assign $2\xer_so$8[0:0]$12626 1'0 + end + case + assign $1\xer_so$8[0:0]$12625 1'0 + end + sync always + update \xer_so$8 $0\xer_so$8[0:0]$12624 + end + attribute \src "libresoc.v:175594.3-175614.6" + process $proc$libresoc.v:175594$12628 + assign { } { } + assign { } { } + assign $0\xer_so_ok[0:0] $1\xer_so_ok[0:0] + attribute \src "libresoc.v:175595.5-175595.29" + switch \initial + attribute \src "libresoc.v:175595.9-175595.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46" + switch \spr_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0110001 + assign { } { } + assign $1\xer_so_ok[0:0] $2\xer_so_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" + switch \spr + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 + assign { } { } + assign $2\xer_so_ok[0:0] $3\xer_so_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" + switch \$13 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\xer_so_ok[0:0] 1'1 + case + assign $3\xer_so_ok[0:0] 1'0 + end + case + assign $2\xer_so_ok[0:0] 1'0 + end + case + assign $1\xer_so_ok[0:0] 1'0 + end + sync always + update \xer_so_ok $0\xer_so_ok[0:0] + end + attribute \src "libresoc.v:175615.3-175638.6" + process $proc$libresoc.v:175615$12629 + assign { } { } + assign { } { } + assign $0\xer_ov$9[1:0]$12630 $1\xer_ov$9[1:0]$12631 + attribute \src "libresoc.v:175616.5-175616.29" + switch \initial + attribute \src "libresoc.v:175616.9-175616.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46" + switch \spr_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0110001 + assign { } { } + assign $1\xer_ov$9[1:0]$12631 $2\xer_ov$9[1:0]$12632 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" + switch \spr + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 + assign { } { } + assign $2\xer_ov$9[1:0]$12632 $3\xer_ov$9[1:0]$12633 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" + switch \$15 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\xer_ov$9[1:0]$12633 [0] \ra [30] + assign $3\xer_ov$9[1:0]$12633 [1] \ra [19] + case + assign $3\xer_ov$9[1:0]$12633 2'00 + end + case + assign $2\xer_ov$9[1:0]$12632 2'00 + end + case + assign $1\xer_ov$9[1:0]$12631 2'00 + end + sync always + update \xer_ov$9 $0\xer_ov$9[1:0]$12630 + end + attribute \src "libresoc.v:175639.3-175659.6" + process $proc$libresoc.v:175639$12634 + assign { } { } + assign { } { } + assign $0\xer_ov_ok[0:0] $1\xer_ov_ok[0:0] + attribute \src "libresoc.v:175640.5-175640.29" + switch \initial + attribute \src "libresoc.v:175640.9-175640.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46" + switch \spr_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0110001 + assign { } { } + assign $1\xer_ov_ok[0:0] $2\xer_ov_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" + switch \spr + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 + assign { } { } + assign $2\xer_ov_ok[0:0] $3\xer_ov_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" + switch \$17 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\xer_ov_ok[0:0] 1'1 + case + assign $3\xer_ov_ok[0:0] 1'0 + end + case + assign $2\xer_ov_ok[0:0] 1'0 + end + case + assign $1\xer_ov_ok[0:0] 1'0 + end + sync always + update \xer_ov_ok $0\xer_ov_ok[0:0] + end + attribute \src "libresoc.v:175660.3-175683.6" + process $proc$libresoc.v:175660$12635 + assign { } { } + assign { } { } + assign $0\xer_ca$10[1:0]$12636 $1\xer_ca$10[1:0]$12637 + attribute \src "libresoc.v:175661.5-175661.29" + switch \initial + attribute \src "libresoc.v:175661.9-175661.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46" + switch \spr_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0110001 + assign { } { } + assign $1\xer_ca$10[1:0]$12637 $2\xer_ca$10[1:0]$12638 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" + switch \spr + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 + assign { } { } + assign $2\xer_ca$10[1:0]$12638 $3\xer_ca$10[1:0]$12639 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" + switch \$19 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\xer_ca$10[1:0]$12639 [0] \ra [29] + assign $3\xer_ca$10[1:0]$12639 [1] \ra [18] + case + assign $3\xer_ca$10[1:0]$12639 2'00 + end + case + assign $2\xer_ca$10[1:0]$12638 2'00 + end + case + assign $1\xer_ca$10[1:0]$12637 2'00 + end + sync always + update \xer_ca$10 $0\xer_ca$10[1:0]$12636 + end + attribute \src "libresoc.v:175684.3-175704.6" + process $proc$libresoc.v:175684$12640 + assign { } { } + assign { } { } + assign $0\xer_ca_ok[0:0] $1\xer_ca_ok[0:0] + attribute \src "libresoc.v:175685.5-175685.29" + switch \initial + attribute \src "libresoc.v:175685.9-175685.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46" + switch \spr_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0110001 + assign { } { } + assign $1\xer_ca_ok[0:0] $2\xer_ca_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" + switch \spr + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 + assign { } { } + assign $2\xer_ca_ok[0:0] $3\xer_ca_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" + switch \$21 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\xer_ca_ok[0:0] 1'1 + case + assign $3\xer_ca_ok[0:0] 1'0 + end + case + assign $2\xer_ca_ok[0:0] 1'0 + end + case + assign $1\xer_ca_ok[0:0] 1'0 + end + sync always + update \xer_ca_ok $0\xer_ca_ok[0:0] + end + attribute \src "libresoc.v:175705.3-175723.6" + process $proc$libresoc.v:175705$12641 + assign { } { } + assign { } { } + assign $0\spr1$6[63:0]$12642 $1\spr1$6[63:0]$12643 + attribute \src "libresoc.v:175706.5-175706.29" + switch \initial + attribute \src "libresoc.v:175706.9-175706.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46" + switch \spr_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0110001 + assign { } { } + assign $1\spr1$6[63:0]$12643 $2\spr1$6[63:0]$12644 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" + switch \spr + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 + assign $2\spr1$6[63:0]$12644 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\spr1$6[63:0]$12644 \ra + end + case + assign $1\spr1$6[63:0]$12643 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \spr1$6 $0\spr1$6[63:0]$12642 + end + connect \$11 $eq$libresoc.v:175473$12609_Y + connect \$13 $eq$libresoc.v:175474$12610_Y + connect \$15 $eq$libresoc.v:175475$12611_Y + connect \$17 $eq$libresoc.v:175476$12612_Y + connect \$19 $eq$libresoc.v:175477$12613_Y + connect \$21 $eq$libresoc.v:175478$12614_Y + connect \$23 $eq$libresoc.v:175479$12615_Y + connect { \spr_op__is_32bit$5 \spr_op__insn$4 \spr_op__fn_unit$3 \spr_op__insn_type$2 } { \spr_op__is_32bit \spr_op__insn \spr_op__fn_unit \spr_op__insn_type } + connect \muxid$1 \muxid + connect \spr { \spr_op__insn [15:11] \spr_op__insn [20:16] } +end +attribute \src "libresoc.v:175731.1-176546.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.dec2.dec_a.sprmap" +attribute \generator "nMigen" +module \sprmap + attribute \src "libresoc.v:175858.3-175888.6" + wire width 3 $0\fast_o[2:0] + attribute \src "libresoc.v:175889.3-175919.6" + wire $0\fast_o_ok[0:0] + attribute \src "libresoc.v:175732.7-175732.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:175920.3-176232.6" + wire width 10 $0\spr_o[9:0] + attribute \src "libresoc.v:176233.3-176545.6" + wire $0\spr_o_ok[0:0] + attribute \src "libresoc.v:175858.3-175888.6" + wire width 3 $1\fast_o[2:0] + attribute \src "libresoc.v:175889.3-175919.6" + wire $1\fast_o_ok[0:0] + attribute \src "libresoc.v:175920.3-176232.6" + wire width 10 $1\spr_o[9:0] + attribute \src "libresoc.v:176233.3-176545.6" + wire $1\spr_o_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 output 3 \fast_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 4 \fast_o_ok + attribute \src "libresoc.v:175732.7-175732.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:59" + wire width 10 input 5 \spr_i + attribute \enum_base_type "SPR" + attribute \enum_value_0000000001 "XER" + attribute \enum_value_0000000011 "DSCR" + attribute \enum_value_0000001000 "LR" + attribute \enum_value_0000001001 "CTR" + attribute \enum_value_0000001101 "AMR" + attribute \enum_value_0000010001 "DSCR_priv" + attribute \enum_value_0000010010 "DSISR" + attribute \enum_value_0000010011 "DAR" + attribute \enum_value_0000010110 "DEC" + attribute \enum_value_0000011010 "SRR0" + attribute \enum_value_0000011011 "SRR1" + attribute \enum_value_0000011100 "CFAR" + attribute \enum_value_0000011101 "AMR_priv" + attribute \enum_value_0000110000 "PIDR" + attribute \enum_value_0000111101 "IAMR" + attribute \enum_value_0010000000 "TFHAR" + attribute \enum_value_0010000001 "TFIAR" + attribute \enum_value_0010000010 "TEXASR" + attribute \enum_value_0010000011 "TEXASRU" + attribute \enum_value_0010001000 "CTRL" + attribute \enum_value_0010010000 "TIDR" + attribute \enum_value_0010011000 "CTRL_priv" + attribute \enum_value_0010011001 "FSCR" + attribute \enum_value_0010011101 "UAMOR" + attribute \enum_value_0010011110 "GSR" + attribute \enum_value_0010011111 "PSPB" + attribute \enum_value_0010110000 "DPDES" + attribute \enum_value_0010110100 "DAWR0" + attribute \enum_value_0010111010 "RPR" + attribute \enum_value_0010111011 "CIABR" + attribute \enum_value_0010111100 "DAWRX0" + attribute \enum_value_0010111110 "HFSCR" + attribute \enum_value_0100000000 "VRSAVE" + attribute \enum_value_0100000011 "SPRG3" + attribute \enum_value_0100001100 "TB" + attribute \enum_value_0100001101 "TBU" + attribute \enum_value_0100010000 "SPRG0_priv" + attribute \enum_value_0100010001 "SPRG1_priv" + attribute \enum_value_0100010010 "SPRG2_priv" + attribute \enum_value_0100010011 "SPRG3_priv" + attribute \enum_value_0100011011 "CIR" + attribute \enum_value_0100011100 "TBL" + attribute \enum_value_0100011101 "TBU_hypv" + attribute \enum_value_0100011110 "TBU40" + attribute \enum_value_0100011111 "PVR" + attribute \enum_value_0100110000 "HSPRG0" + attribute \enum_value_0100110001 "HSPRG1" + attribute \enum_value_0100110010 "HDSISR" + attribute \enum_value_0100110011 "HDAR" + attribute \enum_value_0100110100 "SPURR" + attribute \enum_value_0100110101 "PURR" + attribute \enum_value_0100110110 "HDEC" + attribute \enum_value_0100111001 "HRMOR" + attribute \enum_value_0100111010 "HSRR0" + attribute \enum_value_0100111011 "HSRR1" + attribute \enum_value_0100111110 "LPCR" + attribute \enum_value_0100111111 "LPIDR" + attribute \enum_value_0101010000 "HMER" + attribute \enum_value_0101010001 "HMEER" + attribute \enum_value_0101010010 "PCR" + attribute \enum_value_0101010011 "HEIR" + attribute \enum_value_0101011101 "AMOR" + attribute \enum_value_0110111110 "TIR" + attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1100000000 "SIER" + attribute \enum_value_1100000001 "MMCR2" + attribute \enum_value_1100000010 "MMCRA" + attribute \enum_value_1100000011 "PMC1" + attribute \enum_value_1100000100 "PMC2" + attribute \enum_value_1100000101 "PMC3" + attribute \enum_value_1100000110 "PMC4" + attribute \enum_value_1100000111 "PMC5" + attribute \enum_value_1100001000 "PMC6" + attribute \enum_value_1100001011 "MMCR0" + attribute \enum_value_1100001100 "SIAR" + attribute \enum_value_1100001101 "SDAR" + attribute \enum_value_1100001110 "MMCR1" + attribute \enum_value_1100010000 "SIER_priv" + attribute \enum_value_1100010001 "MMCR2_priv" + attribute \enum_value_1100010010 "MMCRA_priv" + attribute \enum_value_1100010011 "PMC1_priv" + attribute \enum_value_1100010100 "PMC2_priv" + attribute \enum_value_1100010101 "PMC3_priv" + attribute \enum_value_1100010110 "PMC4_priv" + attribute \enum_value_1100010111 "PMC5_priv" + attribute \enum_value_1100011000 "PMC6_priv" + attribute \enum_value_1100011011 "MMCR0_priv" + attribute \enum_value_1100011100 "SIAR_priv" + attribute \enum_value_1100011101 "SDAR_priv" + attribute \enum_value_1100011110 "MMCR1_priv" + attribute \enum_value_1100100000 "BESCRS" + attribute \enum_value_1100100001 "BESCRSU" + attribute \enum_value_1100100010 "BESCRR" + attribute \enum_value_1100100011 "BESCRRU" + attribute \enum_value_1100100100 "EBBHR" + attribute \enum_value_1100100101 "EBBRR" + attribute \enum_value_1100100110 "BESCR" + attribute \enum_value_1100101000 "reserved808" + attribute \enum_value_1100101001 "reserved809" + attribute \enum_value_1100101010 "reserved810" + attribute \enum_value_1100101011 "reserved811" + attribute \enum_value_1100101111 "TAR" + attribute \enum_value_1100110000 "ASDR" + attribute \enum_value_1100110111 "PSSCR" + attribute \enum_value_1101010000 "IC" + attribute \enum_value_1101010001 "VTB" + attribute \enum_value_1101010111 "PSSCR_hypv" + attribute \enum_value_1110000000 "PPR" + attribute \enum_value_1110000010 "PPR32" + attribute \enum_value_1111111111 "PIR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 10 output 1 \spr_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 2 \spr_o_ok + attribute \src "libresoc.v:175732.7-175732.20" + process $proc$libresoc.v:175732$12650 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:175858.3-175888.6" + process $proc$libresoc.v:175858$12646 + assign { } { } + assign { } { } + assign $0\fast_o[2:0] $1\fast_o[2:0] + attribute \src "libresoc.v:175859.5-175859.29" + switch \initial + attribute \src "libresoc.v:175859.9-175859.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:65" + switch \spr_i + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000001 + assign { } { } + assign $1\fast_o[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001000 + assign { } { } + assign $1\fast_o[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001001 + assign { } { } + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010110 + assign { } { } + assign $1\fast_o[2:0] 3'110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011010 + assign { } { } + assign $1\fast_o[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011011 + assign { } { } + assign $1\fast_o[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100001100 + assign { } { } + assign $1\fast_o[2:0] 3'111 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101111 + assign { } { } + assign $1\fast_o[2:0] 3'010 + case + assign $1\fast_o[2:0] 3'000 + end + sync always + update \fast_o $0\fast_o[2:0] + end + attribute \src "libresoc.v:175889.3-175919.6" + process $proc$libresoc.v:175889$12647 + assign { } { } + assign { } { } + assign $0\fast_o_ok[0:0] $1\fast_o_ok[0:0] + attribute \src "libresoc.v:175890.5-175890.29" + switch \initial + attribute \src "libresoc.v:175890.9-175890.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:65" + switch \spr_i + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000001 + assign { } { } + assign $1\fast_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001000 + assign { } { } + assign $1\fast_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001001 + assign { } { } + assign $1\fast_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010110 + assign { } { } + assign $1\fast_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011010 + assign { } { } + assign $1\fast_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011011 + assign { } { } + assign $1\fast_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100001100 + assign { } { } + assign $1\fast_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101111 + assign { } { } + assign $1\fast_o_ok[0:0] 1'1 + case + assign $1\fast_o_ok[0:0] 1'0 + end + sync always + update \fast_o_ok $0\fast_o_ok[0:0] + end + attribute \src "libresoc.v:175920.3-176232.6" + process $proc$libresoc.v:175920$12648 + assign { } { } + assign { } { } + assign $0\spr_o[9:0] $1\spr_o[9:0] + attribute \src "libresoc.v:175921.5-175921.29" + switch \initial + attribute \src "libresoc.v:175921.9-175921.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:65" + switch \spr_i + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000011 + assign { } { } + assign $1\spr_o[9:0] 10'0000000001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001101 + assign { } { } + assign $1\spr_o[9:0] 10'0000000100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010001 + assign { } { } + assign $1\spr_o[9:0] 10'0000000101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\spr_o[9:0] 10'0000000110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010011 + assign { } { } + assign $1\spr_o[9:0] 10'0000000111 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011100 + assign { } { } + assign $1\spr_o[9:0] 10'0000001011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011101 + assign { } { } + assign $1\spr_o[9:0] 10'0000001100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000110000 + assign { } { } + assign $1\spr_o[9:0] 10'0000001101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000111101 + assign { } { } + assign $1\spr_o[9:0] 10'0000001110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000000 + assign { } { } + assign $1\spr_o[9:0] 10'0000001111 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\spr_o[9:0] 10'0000010000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000010 + assign { } { } + assign $1\spr_o[9:0] 10'0000010001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000011 + assign { } { } + assign $1\spr_o[9:0] 10'0000010010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010001000 + assign { } { } + assign $1\spr_o[9:0] 10'0000010011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010000 + assign { } { } + assign $1\spr_o[9:0] 10'0000010100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011000 + assign { } { } + assign $1\spr_o[9:0] 10'0000010101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011001 + assign { } { } + assign $1\spr_o[9:0] 10'0000010110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011101 + assign { } { } + assign $1\spr_o[9:0] 10'0000010111 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011110 + assign { } { } + assign $1\spr_o[9:0] 10'0000011000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011111 + assign { } { } + assign $1\spr_o[9:0] 10'0000011001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010110000 + assign { } { } + assign $1\spr_o[9:0] 10'0000011010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010110100 + assign { } { } + assign $1\spr_o[9:0] 10'0000011011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111010 + assign { } { } + assign $1\spr_o[9:0] 10'0000011100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111011 + assign { } { } + assign $1\spr_o[9:0] 10'0000011101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111100 + assign { } { } + assign $1\spr_o[9:0] 10'0000011110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111110 + assign { } { } + assign $1\spr_o[9:0] 10'0000011111 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000000 + assign { } { } + assign $1\spr_o[9:0] 10'0000100000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000011 + assign { } { } + assign $1\spr_o[9:0] 10'0000100001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100001101 + assign { } { } + assign $1\spr_o[9:0] 10'0000100011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010000 + assign { } { } + assign $1\spr_o[9:0] 10'0000100100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010001 + assign { } { } + assign $1\spr_o[9:0] 10'0000100101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\spr_o[9:0] 10'0000100110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010011 + assign { } { } + assign $1\spr_o[9:0] 10'0000100111 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011011 + assign { } { } + assign $1\spr_o[9:0] 10'0000101000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011100 + assign { } { } + assign $1\spr_o[9:0] 10'0000101001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011101 + assign { } { } + assign $1\spr_o[9:0] 10'0000101010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011110 + assign { } { } + assign $1\spr_o[9:0] 10'0000101011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011111 + assign { } { } + assign $1\spr_o[9:0] 10'0000101100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110000 + assign { } { } + assign $1\spr_o[9:0] 10'0000101101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110001 + assign { } { } + assign $1\spr_o[9:0] 10'0000101110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110010 + assign { } { } + assign $1\spr_o[9:0] 10'0000101111 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110011 + assign { } { } + assign $1\spr_o[9:0] 10'0000110000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110100 + assign { } { } + assign $1\spr_o[9:0] 10'0000110001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110101 + assign { } { } + assign $1\spr_o[9:0] 10'0000110010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110110 + assign { } { } + assign $1\spr_o[9:0] 10'0000110011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111001 + assign { } { } + assign $1\spr_o[9:0] 10'0000110100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111010 + assign { } { } + assign $1\spr_o[9:0] 10'0000110101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111011 + assign { } { } + assign $1\spr_o[9:0] 10'0000110110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111110 + assign { } { } + assign $1\spr_o[9:0] 10'0000110111 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111111 + assign { } { } + assign $1\spr_o[9:0] 10'0000111000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010000 + assign { } { } + assign $1\spr_o[9:0] 10'0000111001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010001 + assign { } { } + assign $1\spr_o[9:0] 10'0000111010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010010 + assign { } { } + assign $1\spr_o[9:0] 10'0000111011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010011 + assign { } { } + assign $1\spr_o[9:0] 10'0000111100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101011101 + assign { } { } + assign $1\spr_o[9:0] 10'0000111101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110111110 + assign { } { } + assign $1\spr_o[9:0] 10'0000111110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111010000 + assign { } { } + assign $1\spr_o[9:0] 10'0000111111 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000000 + assign { } { } + assign $1\spr_o[9:0] 10'0001000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000001 + assign { } { } + assign $1\spr_o[9:0] 10'0001000001 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000010 + assign { } { } + assign $1\spr_o[9:0] 10'0001000010 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000011 + assign { } { } + assign $1\spr_o[9:0] 10'0001000011 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000100 + assign { } { } + assign $1\spr_o[9:0] 10'0001000100 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000101 + assign { } { } + assign $1\spr_o[9:0] 10'0001000101 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000110 + assign { } { } + assign $1\spr_o[9:0] 10'0001000110 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000111 + assign { } { } + assign $1\spr_o[9:0] 10'0001000111 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001000 + assign { } { } + assign $1\spr_o[9:0] 10'0001001000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001011 + assign { } { } + assign $1\spr_o[9:0] 10'0001001001 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001100 + assign { } { } + assign $1\spr_o[9:0] 10'0001001010 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001101 + assign { } { } + assign $1\spr_o[9:0] 10'0001001011 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001110 + assign { } { } + assign $1\spr_o[9:0] 10'0001001100 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010000 + assign { } { } + assign $1\spr_o[9:0] 10'0001001101 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010001 + assign { } { } + assign $1\spr_o[9:0] 10'0001001110 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010010 + assign { } { } + assign $1\spr_o[9:0] 10'0001001111 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010011 + assign { } { } + assign $1\spr_o[9:0] 10'0001010000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010100 + assign { } { } + assign $1\spr_o[9:0] 10'0001010001 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010101 + assign { } { } + assign $1\spr_o[9:0] 10'0001010010 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010110 + assign { } { } + assign $1\spr_o[9:0] 10'0001010011 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010111 + assign { } { } + assign $1\spr_o[9:0] 10'0001010100 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011000 + assign { } { } + assign $1\spr_o[9:0] 10'0001010101 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011011 + assign { } { } + assign $1\spr_o[9:0] 10'0001010110 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011100 + assign { } { } + assign $1\spr_o[9:0] 10'0001010111 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011101 + assign { } { } + assign $1\spr_o[9:0] 10'0001011000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011110 + assign { } { } + assign $1\spr_o[9:0] 10'0001011001 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100000 + assign { } { } + assign $1\spr_o[9:0] 10'0001011010 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100001 + assign { } { } + assign $1\spr_o[9:0] 10'0001011011 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100010 + assign { } { } + assign $1\spr_o[9:0] 10'0001011100 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100011 + assign { } { } + assign $1\spr_o[9:0] 10'0001011101 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100100 + assign { } { } + assign $1\spr_o[9:0] 10'0001011110 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100101 + assign { } { } + assign $1\spr_o[9:0] 10'0001011111 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100110 + assign { } { } + assign $1\spr_o[9:0] 10'0001100000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101000 + assign { } { } + assign $1\spr_o[9:0] 10'0001100001 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101001 + assign { } { } + assign $1\spr_o[9:0] 10'0001100010 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101010 + assign { } { } + assign $1\spr_o[9:0] 10'0001100011 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101011 + assign { } { } + assign $1\spr_o[9:0] 10'0001100100 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100110000 + assign { } { } + assign $1\spr_o[9:0] 10'0001100110 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100110111 + assign { } { } + assign $1\spr_o[9:0] 10'0001100111 + attribute \src "libresoc.v:0.0-0.0" + case 10'1101010000 + assign { } { } + assign $1\spr_o[9:0] 10'0001101000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1101010001 + assign { } { } + assign $1\spr_o[9:0] 10'0001101001 + attribute \src "libresoc.v:0.0-0.0" + case 10'1101010111 + assign { } { } + assign $1\spr_o[9:0] 10'0001101010 + attribute \src "libresoc.v:0.0-0.0" + case 10'1110000000 + assign { } { } + assign $1\spr_o[9:0] 10'0001101011 + attribute \src "libresoc.v:0.0-0.0" + case 10'1110000010 + assign { } { } + assign $1\spr_o[9:0] 10'0001101100 + attribute \src "libresoc.v:0.0-0.0" + case 10'1111111111 + assign { } { } + assign $1\spr_o[9:0] 10'0001101101 + case + assign $1\spr_o[9:0] 10'0000000000 + end + sync always + update \spr_o $0\spr_o[9:0] + end + attribute \src "libresoc.v:176233.3-176545.6" + process $proc$libresoc.v:176233$12649 + assign { } { } + assign { } { } + assign $0\spr_o_ok[0:0] $1\spr_o_ok[0:0] + attribute \src "libresoc.v:176234.5-176234.29" + switch \initial + attribute \src "libresoc.v:176234.9-176234.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:65" + switch \spr_i + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000110000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000111101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010001000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011111 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010110000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010110100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100001101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011111 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111111 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101011101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110111110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111010000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000111 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010111 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100110000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100110111 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1101010000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1101010001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1101010111 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1110000000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1110000010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1111111111 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + case + assign $1\spr_o_ok[0:0] 1'0 + end + sync always + update \spr_o_ok $0\spr_o_ok[0:0] + end +end +attribute \src "libresoc.v:176550.1-177365.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.dec2.dec_o.sprmap" +attribute \generator "nMigen" +module \sprmap$209 + attribute \src "libresoc.v:176677.3-176707.6" + wire width 3 $0\fast_o[2:0] + attribute \src "libresoc.v:176708.3-176738.6" + wire $0\fast_o_ok[0:0] + attribute \src "libresoc.v:176551.7-176551.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:176739.3-177051.6" + wire width 10 $0\spr_o[9:0] + attribute \src "libresoc.v:177052.3-177364.6" + wire $0\spr_o_ok[0:0] + attribute \src "libresoc.v:176677.3-176707.6" + wire width 3 $1\fast_o[2:0] + attribute \src "libresoc.v:176708.3-176738.6" + wire $1\fast_o_ok[0:0] + attribute \src "libresoc.v:176739.3-177051.6" + wire width 10 $1\spr_o[9:0] + attribute \src "libresoc.v:177052.3-177364.6" + wire $1\spr_o_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 output 3 \fast_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 4 \fast_o_ok + attribute \src "libresoc.v:176551.7-176551.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:59" + wire width 10 input 5 \spr_i + attribute \enum_base_type "SPR" + attribute \enum_value_0000000001 "XER" + attribute \enum_value_0000000011 "DSCR" + attribute \enum_value_0000001000 "LR" + attribute \enum_value_0000001001 "CTR" + attribute \enum_value_0000001101 "AMR" + attribute \enum_value_0000010001 "DSCR_priv" + attribute \enum_value_0000010010 "DSISR" + attribute \enum_value_0000010011 "DAR" + attribute \enum_value_0000010110 "DEC" + attribute \enum_value_0000011010 "SRR0" + attribute \enum_value_0000011011 "SRR1" + attribute \enum_value_0000011100 "CFAR" + attribute \enum_value_0000011101 "AMR_priv" + attribute \enum_value_0000110000 "PIDR" + attribute \enum_value_0000111101 "IAMR" + attribute \enum_value_0010000000 "TFHAR" + attribute \enum_value_0010000001 "TFIAR" + attribute \enum_value_0010000010 "TEXASR" + attribute \enum_value_0010000011 "TEXASRU" + attribute \enum_value_0010001000 "CTRL" + attribute \enum_value_0010010000 "TIDR" + attribute \enum_value_0010011000 "CTRL_priv" + attribute \enum_value_0010011001 "FSCR" + attribute \enum_value_0010011101 "UAMOR" + attribute \enum_value_0010011110 "GSR" + attribute \enum_value_0010011111 "PSPB" + attribute \enum_value_0010110000 "DPDES" + attribute \enum_value_0010110100 "DAWR0" + attribute \enum_value_0010111010 "RPR" + attribute \enum_value_0010111011 "CIABR" + attribute \enum_value_0010111100 "DAWRX0" + attribute \enum_value_0010111110 "HFSCR" + attribute \enum_value_0100000000 "VRSAVE" + attribute \enum_value_0100000011 "SPRG3" + attribute \enum_value_0100001100 "TB" + attribute \enum_value_0100001101 "TBU" + attribute \enum_value_0100010000 "SPRG0_priv" + attribute \enum_value_0100010001 "SPRG1_priv" + attribute \enum_value_0100010010 "SPRG2_priv" + attribute \enum_value_0100010011 "SPRG3_priv" + attribute \enum_value_0100011011 "CIR" + attribute \enum_value_0100011100 "TBL" + attribute \enum_value_0100011101 "TBU_hypv" + attribute \enum_value_0100011110 "TBU40" + attribute \enum_value_0100011111 "PVR" + attribute \enum_value_0100110000 "HSPRG0" + attribute \enum_value_0100110001 "HSPRG1" + attribute \enum_value_0100110010 "HDSISR" + attribute \enum_value_0100110011 "HDAR" + attribute \enum_value_0100110100 "SPURR" + attribute \enum_value_0100110101 "PURR" + attribute \enum_value_0100110110 "HDEC" + attribute \enum_value_0100111001 "HRMOR" + attribute \enum_value_0100111010 "HSRR0" + attribute \enum_value_0100111011 "HSRR1" + attribute \enum_value_0100111110 "LPCR" + attribute \enum_value_0100111111 "LPIDR" + attribute \enum_value_0101010000 "HMER" + attribute \enum_value_0101010001 "HMEER" + attribute \enum_value_0101010010 "PCR" + attribute \enum_value_0101010011 "HEIR" + attribute \enum_value_0101011101 "AMOR" + attribute \enum_value_0110111110 "TIR" + attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1100000000 "SIER" + attribute \enum_value_1100000001 "MMCR2" + attribute \enum_value_1100000010 "MMCRA" + attribute \enum_value_1100000011 "PMC1" + attribute \enum_value_1100000100 "PMC2" + attribute \enum_value_1100000101 "PMC3" + attribute \enum_value_1100000110 "PMC4" + attribute \enum_value_1100000111 "PMC5" + attribute \enum_value_1100001000 "PMC6" + attribute \enum_value_1100001011 "MMCR0" + attribute \enum_value_1100001100 "SIAR" + attribute \enum_value_1100001101 "SDAR" + attribute \enum_value_1100001110 "MMCR1" + attribute \enum_value_1100010000 "SIER_priv" + attribute \enum_value_1100010001 "MMCR2_priv" + attribute \enum_value_1100010010 "MMCRA_priv" + attribute \enum_value_1100010011 "PMC1_priv" + attribute \enum_value_1100010100 "PMC2_priv" + attribute \enum_value_1100010101 "PMC3_priv" + attribute \enum_value_1100010110 "PMC4_priv" + attribute \enum_value_1100010111 "PMC5_priv" + attribute \enum_value_1100011000 "PMC6_priv" + attribute \enum_value_1100011011 "MMCR0_priv" + attribute \enum_value_1100011100 "SIAR_priv" + attribute \enum_value_1100011101 "SDAR_priv" + attribute \enum_value_1100011110 "MMCR1_priv" + attribute \enum_value_1100100000 "BESCRS" + attribute \enum_value_1100100001 "BESCRSU" + attribute \enum_value_1100100010 "BESCRR" + attribute \enum_value_1100100011 "BESCRRU" + attribute \enum_value_1100100100 "EBBHR" + attribute \enum_value_1100100101 "EBBRR" + attribute \enum_value_1100100110 "BESCR" + attribute \enum_value_1100101000 "reserved808" + attribute \enum_value_1100101001 "reserved809" + attribute \enum_value_1100101010 "reserved810" + attribute \enum_value_1100101011 "reserved811" + attribute \enum_value_1100101111 "TAR" + attribute \enum_value_1100110000 "ASDR" + attribute \enum_value_1100110111 "PSSCR" + attribute \enum_value_1101010000 "IC" + attribute \enum_value_1101010001 "VTB" + attribute \enum_value_1101010111 "PSSCR_hypv" + attribute \enum_value_1110000000 "PPR" + attribute \enum_value_1110000010 "PPR32" + attribute \enum_value_1111111111 "PIR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 10 output 1 \spr_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 2 \spr_o_ok + attribute \src "libresoc.v:176551.7-176551.20" + process $proc$libresoc.v:176551$12655 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:176677.3-176707.6" + process $proc$libresoc.v:176677$12651 + assign { } { } + assign { } { } + assign $0\fast_o[2:0] $1\fast_o[2:0] + attribute \src "libresoc.v:176678.5-176678.29" + switch \initial + attribute \src "libresoc.v:176678.9-176678.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:65" + switch \spr_i + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000001 + assign { } { } + assign $1\fast_o[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001000 + assign { } { } + assign $1\fast_o[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001001 + assign { } { } + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010110 + assign { } { } + assign $1\fast_o[2:0] 3'110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011010 + assign { } { } + assign $1\fast_o[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011011 + assign { } { } + assign $1\fast_o[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100001100 + assign { } { } + assign $1\fast_o[2:0] 3'111 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101111 + assign { } { } + assign $1\fast_o[2:0] 3'010 + case + assign $1\fast_o[2:0] 3'000 + end + sync always + update \fast_o $0\fast_o[2:0] + end + attribute \src "libresoc.v:176708.3-176738.6" + process $proc$libresoc.v:176708$12652 + assign { } { } + assign { } { } + assign $0\fast_o_ok[0:0] $1\fast_o_ok[0:0] + attribute \src "libresoc.v:176709.5-176709.29" + switch \initial + attribute \src "libresoc.v:176709.9-176709.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:65" + switch \spr_i + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000001 + assign { } { } + assign $1\fast_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001000 + assign { } { } + assign $1\fast_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001001 + assign { } { } + assign $1\fast_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010110 + assign { } { } + assign $1\fast_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011010 + assign { } { } + assign $1\fast_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011011 + assign { } { } + assign $1\fast_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100001100 + assign { } { } + assign $1\fast_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101111 + assign { } { } + assign $1\fast_o_ok[0:0] 1'1 + case + assign $1\fast_o_ok[0:0] 1'0 + end + sync always + update \fast_o_ok $0\fast_o_ok[0:0] + end + attribute \src "libresoc.v:176739.3-177051.6" + process $proc$libresoc.v:176739$12653 + assign { } { } + assign { } { } + assign $0\spr_o[9:0] $1\spr_o[9:0] + attribute \src "libresoc.v:176740.5-176740.29" + switch \initial + attribute \src "libresoc.v:176740.9-176740.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:65" + switch \spr_i + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000011 + assign { } { } + assign $1\spr_o[9:0] 10'0000000001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001101 + assign { } { } + assign $1\spr_o[9:0] 10'0000000100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010001 + assign { } { } + assign $1\spr_o[9:0] 10'0000000101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\spr_o[9:0] 10'0000000110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010011 + assign { } { } + assign $1\spr_o[9:0] 10'0000000111 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011100 + assign { } { } + assign $1\spr_o[9:0] 10'0000001011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011101 + assign { } { } + assign $1\spr_o[9:0] 10'0000001100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000110000 + assign { } { } + assign $1\spr_o[9:0] 10'0000001101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000111101 + assign { } { } + assign $1\spr_o[9:0] 10'0000001110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000000 + assign { } { } + assign $1\spr_o[9:0] 10'0000001111 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\spr_o[9:0] 10'0000010000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000010 + assign { } { } + assign $1\spr_o[9:0] 10'0000010001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000011 + assign { } { } + assign $1\spr_o[9:0] 10'0000010010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010001000 + assign { } { } + assign $1\spr_o[9:0] 10'0000010011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010000 + assign { } { } + assign $1\spr_o[9:0] 10'0000010100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011000 + assign { } { } + assign $1\spr_o[9:0] 10'0000010101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011001 + assign { } { } + assign $1\spr_o[9:0] 10'0000010110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011101 + assign { } { } + assign $1\spr_o[9:0] 10'0000010111 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011110 + assign { } { } + assign $1\spr_o[9:0] 10'0000011000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011111 + assign { } { } + assign $1\spr_o[9:0] 10'0000011001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010110000 + assign { } { } + assign $1\spr_o[9:0] 10'0000011010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010110100 + assign { } { } + assign $1\spr_o[9:0] 10'0000011011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111010 + assign { } { } + assign $1\spr_o[9:0] 10'0000011100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111011 + assign { } { } + assign $1\spr_o[9:0] 10'0000011101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111100 + assign { } { } + assign $1\spr_o[9:0] 10'0000011110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111110 + assign { } { } + assign $1\spr_o[9:0] 10'0000011111 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000000 + assign { } { } + assign $1\spr_o[9:0] 10'0000100000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000011 + assign { } { } + assign $1\spr_o[9:0] 10'0000100001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100001101 + assign { } { } + assign $1\spr_o[9:0] 10'0000100011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010000 + assign { } { } + assign $1\spr_o[9:0] 10'0000100100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010001 + assign { } { } + assign $1\spr_o[9:0] 10'0000100101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\spr_o[9:0] 10'0000100110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010011 + assign { } { } + assign $1\spr_o[9:0] 10'0000100111 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011011 + assign { } { } + assign $1\spr_o[9:0] 10'0000101000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011100 + assign { } { } + assign $1\spr_o[9:0] 10'0000101001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011101 + assign { } { } + assign $1\spr_o[9:0] 10'0000101010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011110 + assign { } { } + assign $1\spr_o[9:0] 10'0000101011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011111 + assign { } { } + assign $1\spr_o[9:0] 10'0000101100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110000 + assign { } { } + assign $1\spr_o[9:0] 10'0000101101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110001 + assign { } { } + assign $1\spr_o[9:0] 10'0000101110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110010 + assign { } { } + assign $1\spr_o[9:0] 10'0000101111 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110011 + assign { } { } + assign $1\spr_o[9:0] 10'0000110000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110100 + assign { } { } + assign $1\spr_o[9:0] 10'0000110001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110101 + assign { } { } + assign $1\spr_o[9:0] 10'0000110010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110110 + assign { } { } + assign $1\spr_o[9:0] 10'0000110011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111001 + assign { } { } + assign $1\spr_o[9:0] 10'0000110100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111010 + assign { } { } + assign $1\spr_o[9:0] 10'0000110101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111011 + assign { } { } + assign $1\spr_o[9:0] 10'0000110110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111110 + assign { } { } + assign $1\spr_o[9:0] 10'0000110111 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111111 + assign { } { } + assign $1\spr_o[9:0] 10'0000111000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010000 + assign { } { } + assign $1\spr_o[9:0] 10'0000111001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010001 + assign { } { } + assign $1\spr_o[9:0] 10'0000111010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010010 + assign { } { } + assign $1\spr_o[9:0] 10'0000111011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010011 + assign { } { } + assign $1\spr_o[9:0] 10'0000111100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101011101 + assign { } { } + assign $1\spr_o[9:0] 10'0000111101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110111110 + assign { } { } + assign $1\spr_o[9:0] 10'0000111110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111010000 + assign { } { } + assign $1\spr_o[9:0] 10'0000111111 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000000 + assign { } { } + assign $1\spr_o[9:0] 10'0001000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000001 + assign { } { } + assign $1\spr_o[9:0] 10'0001000001 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000010 + assign { } { } + assign $1\spr_o[9:0] 10'0001000010 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000011 + assign { } { } + assign $1\spr_o[9:0] 10'0001000011 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000100 + assign { } { } + assign $1\spr_o[9:0] 10'0001000100 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000101 + assign { } { } + assign $1\spr_o[9:0] 10'0001000101 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000110 + assign { } { } + assign $1\spr_o[9:0] 10'0001000110 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000111 + assign { } { } + assign $1\spr_o[9:0] 10'0001000111 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001000 + assign { } { } + assign $1\spr_o[9:0] 10'0001001000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001011 + assign { } { } + assign $1\spr_o[9:0] 10'0001001001 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001100 + assign { } { } + assign $1\spr_o[9:0] 10'0001001010 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001101 + assign { } { } + assign $1\spr_o[9:0] 10'0001001011 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001110 + assign { } { } + assign $1\spr_o[9:0] 10'0001001100 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010000 + assign { } { } + assign $1\spr_o[9:0] 10'0001001101 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010001 + assign { } { } + assign $1\spr_o[9:0] 10'0001001110 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010010 + assign { } { } + assign $1\spr_o[9:0] 10'0001001111 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010011 + assign { } { } + assign $1\spr_o[9:0] 10'0001010000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010100 + assign { } { } + assign $1\spr_o[9:0] 10'0001010001 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010101 + assign { } { } + assign $1\spr_o[9:0] 10'0001010010 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010110 + assign { } { } + assign $1\spr_o[9:0] 10'0001010011 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010111 + assign { } { } + assign $1\spr_o[9:0] 10'0001010100 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011000 + assign { } { } + assign $1\spr_o[9:0] 10'0001010101 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011011 + assign { } { } + assign $1\spr_o[9:0] 10'0001010110 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011100 + assign { } { } + assign $1\spr_o[9:0] 10'0001010111 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011101 + assign { } { } + assign $1\spr_o[9:0] 10'0001011000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011110 + assign { } { } + assign $1\spr_o[9:0] 10'0001011001 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100000 + assign { } { } + assign $1\spr_o[9:0] 10'0001011010 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100001 + assign { } { } + assign $1\spr_o[9:0] 10'0001011011 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100010 + assign { } { } + assign $1\spr_o[9:0] 10'0001011100 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100011 + assign { } { } + assign $1\spr_o[9:0] 10'0001011101 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100100 + assign { } { } + assign $1\spr_o[9:0] 10'0001011110 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100101 + assign { } { } + assign $1\spr_o[9:0] 10'0001011111 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100110 + assign { } { } + assign $1\spr_o[9:0] 10'0001100000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101000 + assign { } { } + assign $1\spr_o[9:0] 10'0001100001 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101001 + assign { } { } + assign $1\spr_o[9:0] 10'0001100010 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101010 + assign { } { } + assign $1\spr_o[9:0] 10'0001100011 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101011 + assign { } { } + assign $1\spr_o[9:0] 10'0001100100 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100110000 + assign { } { } + assign $1\spr_o[9:0] 10'0001100110 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100110111 + assign { } { } + assign $1\spr_o[9:0] 10'0001100111 + attribute \src "libresoc.v:0.0-0.0" + case 10'1101010000 + assign { } { } + assign $1\spr_o[9:0] 10'0001101000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1101010001 + assign { } { } + assign $1\spr_o[9:0] 10'0001101001 + attribute \src "libresoc.v:0.0-0.0" + case 10'1101010111 + assign { } { } + assign $1\spr_o[9:0] 10'0001101010 + attribute \src "libresoc.v:0.0-0.0" + case 10'1110000000 + assign { } { } + assign $1\spr_o[9:0] 10'0001101011 + attribute \src "libresoc.v:0.0-0.0" + case 10'1110000010 + assign { } { } + assign $1\spr_o[9:0] 10'0001101100 + attribute \src "libresoc.v:0.0-0.0" + case 10'1111111111 + assign { } { } + assign $1\spr_o[9:0] 10'0001101101 + case + assign $1\spr_o[9:0] 10'0000000000 + end + sync always + update \spr_o $0\spr_o[9:0] + end + attribute \src "libresoc.v:177052.3-177364.6" + process $proc$libresoc.v:177052$12654 + assign { } { } + assign { } { } + assign $0\spr_o_ok[0:0] $1\spr_o_ok[0:0] + attribute \src "libresoc.v:177053.5-177053.29" + switch \initial + attribute \src "libresoc.v:177053.9-177053.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:65" + switch \spr_i + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000110000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000111101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010001000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011111 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010110000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010110100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100001101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011111 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111111 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101011101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110111110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111010000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000111 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010111 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100110000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100110111 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1101010000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1101010001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1101010111 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1110000000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1110000010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1111111111 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + case + assign $1\spr_o_ok[0:0] 1'0 + end + sync always + update \spr_o_ok $0\spr_o_ok[0:0] + end +end +attribute \src "libresoc.v:177369.1-177427.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.src_l" +attribute \generator "nMigen" +module \src_l + attribute \src "libresoc.v:177370.7-177370.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:177415.3-177423.6" + wire width 4 $0\q_int$next[3:0]$12666 + attribute \src "libresoc.v:177413.3-177414.27" + wire width 4 $0\q_int[3:0] + attribute \src "libresoc.v:177415.3-177423.6" + wire width 4 $1\q_int$next[3:0]$12667 + attribute \src "libresoc.v:177392.13-177392.25" + wire width 4 $1\q_int[3:0] + attribute \src "libresoc.v:177405.17-177405.96" + wire width 4 $and$libresoc.v:177405$12656_Y + attribute \src "libresoc.v:177410.17-177410.96" + wire width 4 $and$libresoc.v:177410$12661_Y + attribute \src "libresoc.v:177407.18-177407.93" + wire width 4 $not$libresoc.v:177407$12658_Y + attribute \src "libresoc.v:177409.17-177409.92" + wire width 4 $not$libresoc.v:177409$12660_Y + attribute \src "libresoc.v:177412.17-177412.92" + wire width 4 $not$libresoc.v:177412$12663_Y + attribute \src "libresoc.v:177406.18-177406.98" + wire width 4 $or$libresoc.v:177406$12657_Y + attribute \src "libresoc.v:177408.18-177408.99" + wire width 4 $or$libresoc.v:177408$12659_Y + attribute \src "libresoc.v:177411.17-177411.97" + wire width 4 $or$libresoc.v:177411$12662_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 4 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 4 \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 4 \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire width 4 \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 4 \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 4 \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 4 \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 4 \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 1 \coresync_rst + attribute \src "libresoc.v:177370.7-177370.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 4 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 4 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 4 output 4 \q_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire width 4 \qlq_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 4 \qn_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 4 input 3 \r_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 4 input 2 \s_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$libresoc.v:177405$12656 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:177405$12656_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:177410$12661 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:177410$12661_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:177407$12658 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \q_src + connect \Y $not$libresoc.v:177407$12658_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:177409$12660 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \r_src + connect \Y $not$libresoc.v:177409$12660_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:177412$12663 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \r_src + connect \Y $not$libresoc.v:177412$12663_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:177406$12657 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \$9 + connect \B \s_src + connect \Y $or$libresoc.v:177406$12657_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:177408$12659 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \q_src + connect \B \q_int + connect \Y $or$libresoc.v:177408$12659_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:177411$12662 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \$3 + connect \B \s_src + connect \Y $or$libresoc.v:177411$12662_Y + end + attribute \src "libresoc.v:177370.7-177370.20" + process $proc$libresoc.v:177370$12668 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:177392.13-177392.25" + process $proc$libresoc.v:177392$12669 + assign { } { } + assign $1\q_int[3:0] 4'0000 + sync always + sync init + update \q_int $1\q_int[3:0] + end + attribute \src "libresoc.v:177413.3-177414.27" + process $proc$libresoc.v:177413$12664 + assign { } { } + assign $0\q_int[3:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[3:0] + end + attribute \src "libresoc.v:177415.3-177423.6" + process $proc$libresoc.v:177415$12665 + assign { } { } + assign { } { } + assign $0\q_int$next[3:0]$12666 $1\q_int$next[3:0]$12667 + attribute \src "libresoc.v:177416.5-177416.29" + switch \initial + attribute \src "libresoc.v:177416.9-177416.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[3:0]$12667 4'0000 + case + assign $1\q_int$next[3:0]$12667 \$5 + end + sync always + update \q_int$next $0\q_int$next[3:0]$12666 + end + connect \$9 $and$libresoc.v:177405$12656_Y + connect \$11 $or$libresoc.v:177406$12657_Y + connect \$13 $not$libresoc.v:177407$12658_Y + connect \$15 $or$libresoc.v:177408$12659_Y + connect \$1 $not$libresoc.v:177409$12660_Y + connect \$3 $and$libresoc.v:177410$12661_Y + connect \$5 $or$libresoc.v:177411$12662_Y + connect \$7 $not$libresoc.v:177412$12663_Y + connect \qlq_src \$15 + connect \qn_src \$13 + connect \q_src \$11 +end +attribute \src "libresoc.v:177431.1-177489.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.src_l" +attribute \generator "nMigen" +module \src_l$10 + attribute \src "libresoc.v:177432.7-177432.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:177477.3-177485.6" + wire width 6 $0\q_int$next[5:0]$12680 + attribute \src "libresoc.v:177475.3-177476.27" + wire width 6 $0\q_int[5:0] + attribute \src "libresoc.v:177477.3-177485.6" + wire width 6 $1\q_int$next[5:0]$12681 + attribute \src "libresoc.v:177454.13-177454.26" + wire width 6 $1\q_int[5:0] + attribute \src "libresoc.v:177467.17-177467.96" + wire width 6 $and$libresoc.v:177467$12670_Y + attribute \src "libresoc.v:177472.17-177472.96" + wire width 6 $and$libresoc.v:177472$12675_Y + attribute \src "libresoc.v:177469.18-177469.93" + wire width 6 $not$libresoc.v:177469$12672_Y + attribute \src "libresoc.v:177471.17-177471.92" + wire width 6 $not$libresoc.v:177471$12674_Y + attribute \src "libresoc.v:177474.17-177474.92" + wire width 6 $not$libresoc.v:177474$12677_Y + attribute \src "libresoc.v:177468.18-177468.98" + wire width 6 $or$libresoc.v:177468$12671_Y + attribute \src "libresoc.v:177470.18-177470.99" + wire width 6 $or$libresoc.v:177470$12673_Y + attribute \src "libresoc.v:177473.17-177473.97" + wire width 6 $or$libresoc.v:177473$12676_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 6 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 6 \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 6 \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire width 6 \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 6 \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 6 \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 6 \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 6 \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 1 \coresync_rst + attribute \src "libresoc.v:177432.7-177432.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 6 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 6 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 6 output 4 \q_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire width 6 \qlq_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 6 \qn_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 6 input 3 \r_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 6 input 2 \s_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$libresoc.v:177467$12670 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:177467$12670_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:177472$12675 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:177472$12675_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:177469$12672 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \q_src + connect \Y $not$libresoc.v:177469$12672_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:177471$12674 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \r_src + connect \Y $not$libresoc.v:177471$12674_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:177474$12677 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \r_src + connect \Y $not$libresoc.v:177474$12677_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:177468$12671 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \$9 + connect \B \s_src + connect \Y $or$libresoc.v:177468$12671_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:177470$12673 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \q_src + connect \B \q_int + connect \Y $or$libresoc.v:177470$12673_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:177473$12676 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \$3 + connect \B \s_src + connect \Y $or$libresoc.v:177473$12676_Y + end + attribute \src "libresoc.v:177432.7-177432.20" + process $proc$libresoc.v:177432$12682 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:177454.13-177454.26" + process $proc$libresoc.v:177454$12683 + assign { } { } + assign $1\q_int[5:0] 6'000000 + sync always + sync init + update \q_int $1\q_int[5:0] + end + attribute \src "libresoc.v:177475.3-177476.27" + process $proc$libresoc.v:177475$12678 + assign { } { } + assign $0\q_int[5:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[5:0] + end + attribute \src "libresoc.v:177477.3-177485.6" + process $proc$libresoc.v:177477$12679 + assign { } { } + assign { } { } + assign $0\q_int$next[5:0]$12680 $1\q_int$next[5:0]$12681 + attribute \src "libresoc.v:177478.5-177478.29" + switch \initial + attribute \src "libresoc.v:177478.9-177478.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[5:0]$12681 6'000000 + case + assign $1\q_int$next[5:0]$12681 \$5 + end + sync always + update \q_int$next $0\q_int$next[5:0]$12680 + end + connect \$9 $and$libresoc.v:177467$12670_Y + connect \$11 $or$libresoc.v:177468$12671_Y + connect \$13 $not$libresoc.v:177469$12672_Y + connect \$15 $or$libresoc.v:177470$12673_Y + connect \$1 $not$libresoc.v:177471$12674_Y + connect \$3 $and$libresoc.v:177472$12675_Y + connect \$5 $or$libresoc.v:177473$12676_Y + connect \$7 $not$libresoc.v:177474$12677_Y + connect \qlq_src \$15 + connect \qn_src \$13 + connect \q_src \$11 +end +attribute \src "libresoc.v:177493.1-177551.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.src_l" +attribute \generator "nMigen" +module \src_l$116 + attribute \src "libresoc.v:177494.7-177494.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:177539.3-177547.6" + wire width 5 $0\q_int$next[4:0]$12694 + attribute \src "libresoc.v:177537.3-177538.27" + wire width 5 $0\q_int[4:0] + attribute \src "libresoc.v:177539.3-177547.6" + wire width 5 $1\q_int$next[4:0]$12695 + attribute \src "libresoc.v:177516.13-177516.26" + wire width 5 $1\q_int[4:0] + attribute \src "libresoc.v:177529.17-177529.96" + wire width 5 $and$libresoc.v:177529$12684_Y + attribute \src "libresoc.v:177534.17-177534.96" + wire width 5 $and$libresoc.v:177534$12689_Y + attribute \src "libresoc.v:177531.18-177531.93" + wire width 5 $not$libresoc.v:177531$12686_Y + attribute \src "libresoc.v:177533.17-177533.92" + wire width 5 $not$libresoc.v:177533$12688_Y + attribute \src "libresoc.v:177536.17-177536.92" + wire width 5 $not$libresoc.v:177536$12691_Y + attribute \src "libresoc.v:177530.18-177530.98" + wire width 5 $or$libresoc.v:177530$12685_Y + attribute \src "libresoc.v:177532.18-177532.99" + wire width 5 $or$libresoc.v:177532$12687_Y + attribute \src "libresoc.v:177535.17-177535.97" + wire width 5 $or$libresoc.v:177535$12690_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 5 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 5 \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 5 \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire width 5 \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 5 \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 5 \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 5 \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 5 \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 1 \coresync_rst + attribute \src "libresoc.v:177494.7-177494.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 5 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 5 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 5 output 4 \q_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire width 5 \qlq_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 5 \qn_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 5 input 3 \r_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 5 input 2 \s_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$libresoc.v:177529$12684 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:177529$12684_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:177534$12689 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:177534$12689_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:177531$12686 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \q_src + connect \Y $not$libresoc.v:177531$12686_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:177533$12688 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \r_src + connect \Y $not$libresoc.v:177533$12688_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:177536$12691 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \r_src + connect \Y $not$libresoc.v:177536$12691_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:177530$12685 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \$9 + connect \B \s_src + connect \Y $or$libresoc.v:177530$12685_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:177532$12687 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \q_src + connect \B \q_int + connect \Y $or$libresoc.v:177532$12687_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:177535$12690 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \$3 + connect \B \s_src + connect \Y $or$libresoc.v:177535$12690_Y + end + attribute \src "libresoc.v:177494.7-177494.20" + process $proc$libresoc.v:177494$12696 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:177516.13-177516.26" + process $proc$libresoc.v:177516$12697 + assign { } { } + assign $1\q_int[4:0] 5'00000 + sync always + sync init + update \q_int $1\q_int[4:0] + end + attribute \src "libresoc.v:177537.3-177538.27" + process $proc$libresoc.v:177537$12692 + assign { } { } + assign $0\q_int[4:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[4:0] + end + attribute \src "libresoc.v:177539.3-177547.6" + process $proc$libresoc.v:177539$12693 + assign { } { } + assign { } { } + assign $0\q_int$next[4:0]$12694 $1\q_int$next[4:0]$12695 + attribute \src "libresoc.v:177540.5-177540.29" + switch \initial + attribute \src "libresoc.v:177540.9-177540.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[4:0]$12695 5'00000 + case + assign $1\q_int$next[4:0]$12695 \$5 + end + sync always + update \q_int$next $0\q_int$next[4:0]$12694 + end + connect \$9 $and$libresoc.v:177529$12684_Y + connect \$11 $or$libresoc.v:177530$12685_Y + connect \$13 $not$libresoc.v:177531$12686_Y + connect \$15 $or$libresoc.v:177532$12687_Y + connect \$1 $not$libresoc.v:177533$12688_Y + connect \$3 $and$libresoc.v:177534$12689_Y + connect \$5 $or$libresoc.v:177535$12690_Y + connect \$7 $not$libresoc.v:177536$12691_Y + connect \qlq_src \$15 + connect \qn_src \$13 + connect \q_src \$11 +end +attribute \src "libresoc.v:177555.1-177613.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.src_l" +attribute \generator "nMigen" +module \src_l$124 + attribute \src "libresoc.v:177556.7-177556.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:177601.3-177609.6" + wire width 3 $0\q_int$next[2:0]$12708 + attribute \src "libresoc.v:177599.3-177600.27" + wire width 3 $0\q_int[2:0] + attribute \src "libresoc.v:177601.3-177609.6" + wire width 3 $1\q_int$next[2:0]$12709 + attribute \src "libresoc.v:177578.13-177578.25" + wire width 3 $1\q_int[2:0] + attribute \src "libresoc.v:177591.17-177591.96" + wire width 3 $and$libresoc.v:177591$12698_Y + attribute \src "libresoc.v:177596.17-177596.96" + wire width 3 $and$libresoc.v:177596$12703_Y + attribute \src "libresoc.v:177593.18-177593.93" + wire width 3 $not$libresoc.v:177593$12700_Y + attribute \src "libresoc.v:177595.17-177595.92" + wire width 3 $not$libresoc.v:177595$12702_Y + attribute \src "libresoc.v:177598.17-177598.92" + wire width 3 $not$libresoc.v:177598$12705_Y + attribute \src "libresoc.v:177592.18-177592.98" + wire width 3 $or$libresoc.v:177592$12699_Y + attribute \src "libresoc.v:177594.18-177594.99" + wire width 3 $or$libresoc.v:177594$12701_Y + attribute \src "libresoc.v:177597.17-177597.97" + wire width 3 $or$libresoc.v:177597$12704_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 3 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 3 \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 3 \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire width 3 \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 3 \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 3 \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 3 \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 3 \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 1 \coresync_rst + attribute \src "libresoc.v:177556.7-177556.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 3 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 3 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 3 output 4 \q_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire width 3 \qlq_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 3 \qn_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 3 input 3 \r_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 3 input 2 \s_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$libresoc.v:177591$12698 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:177591$12698_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:177596$12703 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:177596$12703_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:177593$12700 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_src + connect \Y $not$libresoc.v:177593$12700_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:177595$12702 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \r_src + connect \Y $not$libresoc.v:177595$12702_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:177598$12705 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \r_src + connect \Y $not$libresoc.v:177598$12705_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:177592$12699 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \$9 + connect \B \s_src + connect \Y $or$libresoc.v:177592$12699_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:177594$12701 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_src + connect \B \q_int + connect \Y $or$libresoc.v:177594$12701_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:177597$12704 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \$3 + connect \B \s_src + connect \Y $or$libresoc.v:177597$12704_Y + end + attribute \src "libresoc.v:177556.7-177556.20" + process $proc$libresoc.v:177556$12710 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:177578.13-177578.25" + process $proc$libresoc.v:177578$12711 + assign { } { } + assign $1\q_int[2:0] 3'000 + sync always + sync init + update \q_int $1\q_int[2:0] + end + attribute \src "libresoc.v:177599.3-177600.27" + process $proc$libresoc.v:177599$12706 + assign { } { } + assign $0\q_int[2:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[2:0] + end + attribute \src "libresoc.v:177601.3-177609.6" + process $proc$libresoc.v:177601$12707 + assign { } { } + assign { } { } + assign $0\q_int$next[2:0]$12708 $1\q_int$next[2:0]$12709 + attribute \src "libresoc.v:177602.5-177602.29" + switch \initial + attribute \src "libresoc.v:177602.9-177602.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[2:0]$12709 3'000 + case + assign $1\q_int$next[2:0]$12709 \$5 + end + sync always + update \q_int$next $0\q_int$next[2:0]$12708 + end + connect \$9 $and$libresoc.v:177591$12698_Y + connect \$11 $or$libresoc.v:177592$12699_Y + connect \$13 $not$libresoc.v:177593$12700_Y + connect \$15 $or$libresoc.v:177594$12701_Y + connect \$1 $not$libresoc.v:177595$12702_Y + connect \$3 $and$libresoc.v:177596$12703_Y + connect \$5 $or$libresoc.v:177597$12704_Y + connect \$7 $not$libresoc.v:177598$12705_Y + connect \qlq_src \$15 + connect \qn_src \$13 + connect \q_src \$11 +end +attribute \src "libresoc.v:177617.1-177675.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.src_l" +attribute \generator "nMigen" +module \src_l$23 + attribute \src "libresoc.v:177618.7-177618.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:177663.3-177671.6" + wire width 3 $0\q_int$next[2:0]$12722 + attribute \src "libresoc.v:177661.3-177662.27" + wire width 3 $0\q_int[2:0] + attribute \src "libresoc.v:177663.3-177671.6" + wire width 3 $1\q_int$next[2:0]$12723 + attribute \src "libresoc.v:177640.13-177640.25" + wire width 3 $1\q_int[2:0] + attribute \src "libresoc.v:177653.17-177653.96" + wire width 3 $and$libresoc.v:177653$12712_Y + attribute \src "libresoc.v:177658.17-177658.96" + wire width 3 $and$libresoc.v:177658$12717_Y + attribute \src "libresoc.v:177655.18-177655.93" + wire width 3 $not$libresoc.v:177655$12714_Y + attribute \src "libresoc.v:177657.17-177657.92" + wire width 3 $not$libresoc.v:177657$12716_Y + attribute \src "libresoc.v:177660.17-177660.92" + wire width 3 $not$libresoc.v:177660$12719_Y + attribute \src "libresoc.v:177654.18-177654.98" + wire width 3 $or$libresoc.v:177654$12713_Y + attribute \src "libresoc.v:177656.18-177656.99" + wire width 3 $or$libresoc.v:177656$12715_Y + attribute \src "libresoc.v:177659.17-177659.97" + wire width 3 $or$libresoc.v:177659$12718_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 3 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 3 \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 3 \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire width 3 \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 3 \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 3 \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 3 \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 3 \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 1 \coresync_rst + attribute \src "libresoc.v:177618.7-177618.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 3 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 3 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 3 output 4 \q_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire width 3 \qlq_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 3 \qn_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 3 input 3 \r_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 3 input 2 \s_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$libresoc.v:177653$12712 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:177653$12712_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:177658$12717 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:177658$12717_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:177655$12714 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_src + connect \Y $not$libresoc.v:177655$12714_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:177657$12716 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \r_src + connect \Y $not$libresoc.v:177657$12716_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:177660$12719 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \r_src + connect \Y $not$libresoc.v:177660$12719_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:177654$12713 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \$9 + connect \B \s_src + connect \Y $or$libresoc.v:177654$12713_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:177656$12715 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_src + connect \B \q_int + connect \Y $or$libresoc.v:177656$12715_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:177659$12718 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \$3 + connect \B \s_src + connect \Y $or$libresoc.v:177659$12718_Y + end + attribute \src "libresoc.v:177618.7-177618.20" + process $proc$libresoc.v:177618$12724 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:177640.13-177640.25" + process $proc$libresoc.v:177640$12725 + assign { } { } + assign $1\q_int[2:0] 3'000 + sync always + sync init + update \q_int $1\q_int[2:0] + end + attribute \src "libresoc.v:177661.3-177662.27" + process $proc$libresoc.v:177661$12720 + assign { } { } + assign $0\q_int[2:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[2:0] + end + attribute \src "libresoc.v:177663.3-177671.6" + process $proc$libresoc.v:177663$12721 + assign { } { } + assign { } { } + assign $0\q_int$next[2:0]$12722 $1\q_int$next[2:0]$12723 + attribute \src "libresoc.v:177664.5-177664.29" + switch \initial + attribute \src "libresoc.v:177664.9-177664.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[2:0]$12723 3'000 + case + assign $1\q_int$next[2:0]$12723 \$5 + end + sync always + update \q_int$next $0\q_int$next[2:0]$12722 + end + connect \$9 $and$libresoc.v:177653$12712_Y + connect \$11 $or$libresoc.v:177654$12713_Y + connect \$13 $not$libresoc.v:177655$12714_Y + connect \$15 $or$libresoc.v:177656$12715_Y + connect \$1 $not$libresoc.v:177657$12716_Y + connect \$3 $and$libresoc.v:177658$12717_Y + connect \$5 $or$libresoc.v:177659$12718_Y + connect \$7 $not$libresoc.v:177660$12719_Y + connect \qlq_src \$15 + connect \qn_src \$13 + connect \q_src \$11 +end +attribute \src "libresoc.v:177679.1-177737.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.src_l" +attribute \generator "nMigen" +module \src_l$36 + attribute \src "libresoc.v:177680.7-177680.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:177725.3-177733.6" + wire width 4 $0\q_int$next[3:0]$12736 + attribute \src "libresoc.v:177723.3-177724.27" + wire width 4 $0\q_int[3:0] + attribute \src "libresoc.v:177725.3-177733.6" + wire width 4 $1\q_int$next[3:0]$12737 + attribute \src "libresoc.v:177702.13-177702.25" + wire width 4 $1\q_int[3:0] + attribute \src "libresoc.v:177715.17-177715.96" + wire width 4 $and$libresoc.v:177715$12726_Y + attribute \src "libresoc.v:177720.17-177720.96" + wire width 4 $and$libresoc.v:177720$12731_Y + attribute \src "libresoc.v:177717.18-177717.93" + wire width 4 $not$libresoc.v:177717$12728_Y + attribute \src "libresoc.v:177719.17-177719.92" + wire width 4 $not$libresoc.v:177719$12730_Y + attribute \src "libresoc.v:177722.17-177722.92" + wire width 4 $not$libresoc.v:177722$12733_Y + attribute \src "libresoc.v:177716.18-177716.98" + wire width 4 $or$libresoc.v:177716$12727_Y + attribute \src "libresoc.v:177718.18-177718.99" + wire width 4 $or$libresoc.v:177718$12729_Y + attribute \src "libresoc.v:177721.17-177721.97" + wire width 4 $or$libresoc.v:177721$12732_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 4 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 4 \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 4 \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire width 4 \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 4 \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 4 \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 4 \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 4 \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 1 \coresync_rst + attribute \src "libresoc.v:177680.7-177680.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 4 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 4 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 4 output 4 \q_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire width 4 \qlq_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 4 \qn_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 4 input 3 \r_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 4 input 2 \s_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$libresoc.v:177715$12726 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:177715$12726_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:177720$12731 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:177720$12731_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:177717$12728 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \q_src + connect \Y $not$libresoc.v:177717$12728_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:177719$12730 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \r_src + connect \Y $not$libresoc.v:177719$12730_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:177722$12733 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \r_src + connect \Y $not$libresoc.v:177722$12733_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:177716$12727 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \$9 + connect \B \s_src + connect \Y $or$libresoc.v:177716$12727_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:177718$12729 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \q_src + connect \B \q_int + connect \Y $or$libresoc.v:177718$12729_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:177721$12732 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \$3 + connect \B \s_src + connect \Y $or$libresoc.v:177721$12732_Y + end + attribute \src "libresoc.v:177680.7-177680.20" + process $proc$libresoc.v:177680$12738 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:177702.13-177702.25" + process $proc$libresoc.v:177702$12739 + assign { } { } + assign $1\q_int[3:0] 4'0000 + sync always + sync init + update \q_int $1\q_int[3:0] + end + attribute \src "libresoc.v:177723.3-177724.27" + process $proc$libresoc.v:177723$12734 + assign { } { } + assign $0\q_int[3:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[3:0] + end + attribute \src "libresoc.v:177725.3-177733.6" + process $proc$libresoc.v:177725$12735 + assign { } { } + assign { } { } + assign $0\q_int$next[3:0]$12736 $1\q_int$next[3:0]$12737 + attribute \src "libresoc.v:177726.5-177726.29" + switch \initial + attribute \src "libresoc.v:177726.9-177726.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[3:0]$12737 4'0000 + case + assign $1\q_int$next[3:0]$12737 \$5 + end + sync always + update \q_int$next $0\q_int$next[3:0]$12736 + end + connect \$9 $and$libresoc.v:177715$12726_Y + connect \$11 $or$libresoc.v:177716$12727_Y + connect \$13 $not$libresoc.v:177717$12728_Y + connect \$15 $or$libresoc.v:177718$12729_Y + connect \$1 $not$libresoc.v:177719$12730_Y + connect \$3 $and$libresoc.v:177720$12731_Y + connect \$5 $or$libresoc.v:177721$12732_Y + connect \$7 $not$libresoc.v:177722$12733_Y + connect \qlq_src \$15 + connect \qn_src \$13 + connect \q_src \$11 +end +attribute \src "libresoc.v:177741.1-177799.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.src_l" +attribute \generator "nMigen" +module \src_l$52 + attribute \src "libresoc.v:177742.7-177742.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:177787.3-177795.6" + wire width 3 $0\q_int$next[2:0]$12750 + attribute \src "libresoc.v:177785.3-177786.27" + wire width 3 $0\q_int[2:0] + attribute \src "libresoc.v:177787.3-177795.6" + wire width 3 $1\q_int$next[2:0]$12751 + attribute \src "libresoc.v:177764.13-177764.25" + wire width 3 $1\q_int[2:0] + attribute \src "libresoc.v:177777.17-177777.96" + wire width 3 $and$libresoc.v:177777$12740_Y + attribute \src "libresoc.v:177782.17-177782.96" + wire width 3 $and$libresoc.v:177782$12745_Y + attribute \src "libresoc.v:177779.18-177779.93" + wire width 3 $not$libresoc.v:177779$12742_Y + attribute \src "libresoc.v:177781.17-177781.92" + wire width 3 $not$libresoc.v:177781$12744_Y + attribute \src "libresoc.v:177784.17-177784.92" + wire width 3 $not$libresoc.v:177784$12747_Y + attribute \src "libresoc.v:177778.18-177778.98" + wire width 3 $or$libresoc.v:177778$12741_Y + attribute \src "libresoc.v:177780.18-177780.99" + wire width 3 $or$libresoc.v:177780$12743_Y + attribute \src "libresoc.v:177783.17-177783.97" + wire width 3 $or$libresoc.v:177783$12746_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 3 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 3 \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 3 \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire width 3 \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 3 \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 3 \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 3 \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 3 \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 1 \coresync_rst + attribute \src "libresoc.v:177742.7-177742.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 3 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 3 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 3 output 4 \q_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire width 3 \qlq_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 3 \qn_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 3 input 3 \r_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 3 input 2 \s_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$libresoc.v:177777$12740 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:177777$12740_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:177782$12745 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:177782$12745_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:177779$12742 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_src + connect \Y $not$libresoc.v:177779$12742_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:177781$12744 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \r_src + connect \Y $not$libresoc.v:177781$12744_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:177784$12747 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \r_src + connect \Y $not$libresoc.v:177784$12747_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:177778$12741 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \$9 + connect \B \s_src + connect \Y $or$libresoc.v:177778$12741_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:177780$12743 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_src + connect \B \q_int + connect \Y $or$libresoc.v:177780$12743_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:177783$12746 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \$3 + connect \B \s_src + connect \Y $or$libresoc.v:177783$12746_Y + end + attribute \src "libresoc.v:177742.7-177742.20" + process $proc$libresoc.v:177742$12752 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:177764.13-177764.25" + process $proc$libresoc.v:177764$12753 + assign { } { } + assign $1\q_int[2:0] 3'000 + sync always + sync init + update \q_int $1\q_int[2:0] + end + attribute \src "libresoc.v:177785.3-177786.27" + process $proc$libresoc.v:177785$12748 + assign { } { } + assign $0\q_int[2:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[2:0] + end + attribute \src "libresoc.v:177787.3-177795.6" + process $proc$libresoc.v:177787$12749 + assign { } { } + assign { } { } + assign $0\q_int$next[2:0]$12750 $1\q_int$next[2:0]$12751 + attribute \src "libresoc.v:177788.5-177788.29" + switch \initial + attribute \src "libresoc.v:177788.9-177788.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[2:0]$12751 3'000 + case + assign $1\q_int$next[2:0]$12751 \$5 + end + sync always + update \q_int$next $0\q_int$next[2:0]$12750 + end + connect \$9 $and$libresoc.v:177777$12740_Y + connect \$11 $or$libresoc.v:177778$12741_Y + connect \$13 $not$libresoc.v:177779$12742_Y + connect \$15 $or$libresoc.v:177780$12743_Y + connect \$1 $not$libresoc.v:177781$12744_Y + connect \$3 $and$libresoc.v:177782$12745_Y + connect \$5 $or$libresoc.v:177783$12746_Y + connect \$7 $not$libresoc.v:177784$12747_Y + connect \qlq_src \$15 + connect \qn_src \$13 + connect \q_src \$11 +end +attribute \src "libresoc.v:177803.1-177861.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.src_l" +attribute \generator "nMigen" +module \src_l$64 + attribute \src "libresoc.v:177804.7-177804.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:177849.3-177857.6" + wire width 6 $0\q_int$next[5:0]$12764 + attribute \src "libresoc.v:177847.3-177848.27" + wire width 6 $0\q_int[5:0] + attribute \src "libresoc.v:177849.3-177857.6" + wire width 6 $1\q_int$next[5:0]$12765 + attribute \src "libresoc.v:177826.13-177826.26" + wire width 6 $1\q_int[5:0] + attribute \src "libresoc.v:177839.17-177839.96" + wire width 6 $and$libresoc.v:177839$12754_Y + attribute \src "libresoc.v:177844.17-177844.96" + wire width 6 $and$libresoc.v:177844$12759_Y + attribute \src "libresoc.v:177841.18-177841.93" + wire width 6 $not$libresoc.v:177841$12756_Y + attribute \src "libresoc.v:177843.17-177843.92" + wire width 6 $not$libresoc.v:177843$12758_Y + attribute \src "libresoc.v:177846.17-177846.92" + wire width 6 $not$libresoc.v:177846$12761_Y + attribute \src "libresoc.v:177840.18-177840.98" + wire width 6 $or$libresoc.v:177840$12755_Y + attribute \src "libresoc.v:177842.18-177842.99" + wire width 6 $or$libresoc.v:177842$12757_Y + attribute \src "libresoc.v:177845.17-177845.97" + wire width 6 $or$libresoc.v:177845$12760_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 6 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 6 \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 6 \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire width 6 \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 6 \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 6 \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 6 \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 6 \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 1 \coresync_rst + attribute \src "libresoc.v:177804.7-177804.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 6 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 6 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 6 output 4 \q_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire width 6 \qlq_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 6 \qn_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 6 input 3 \r_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 6 input 2 \s_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$libresoc.v:177839$12754 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:177839$12754_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:177844$12759 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:177844$12759_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:177841$12756 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \q_src + connect \Y $not$libresoc.v:177841$12756_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:177843$12758 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \r_src + connect \Y $not$libresoc.v:177843$12758_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:177846$12761 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \r_src + connect \Y $not$libresoc.v:177846$12761_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:177840$12755 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \$9 + connect \B \s_src + connect \Y $or$libresoc.v:177840$12755_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:177842$12757 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \q_src + connect \B \q_int + connect \Y $or$libresoc.v:177842$12757_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:177845$12760 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \$3 + connect \B \s_src + connect \Y $or$libresoc.v:177845$12760_Y + end + attribute \src "libresoc.v:177804.7-177804.20" + process $proc$libresoc.v:177804$12766 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:177826.13-177826.26" + process $proc$libresoc.v:177826$12767 + assign { } { } + assign $1\q_int[5:0] 6'000000 + sync always + sync init + update \q_int $1\q_int[5:0] + end + attribute \src "libresoc.v:177847.3-177848.27" + process $proc$libresoc.v:177847$12762 + assign { } { } + assign $0\q_int[5:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[5:0] + end + attribute \src "libresoc.v:177849.3-177857.6" + process $proc$libresoc.v:177849$12763 + assign { } { } + assign { } { } + assign $0\q_int$next[5:0]$12764 $1\q_int$next[5:0]$12765 + attribute \src "libresoc.v:177850.5-177850.29" + switch \initial + attribute \src "libresoc.v:177850.9-177850.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[5:0]$12765 6'000000 + case + assign $1\q_int$next[5:0]$12765 \$5 + end + sync always + update \q_int$next $0\q_int$next[5:0]$12764 + end + connect \$9 $and$libresoc.v:177839$12754_Y + connect \$11 $or$libresoc.v:177840$12755_Y + connect \$13 $not$libresoc.v:177841$12756_Y + connect \$15 $or$libresoc.v:177842$12757_Y + connect \$1 $not$libresoc.v:177843$12758_Y + connect \$3 $and$libresoc.v:177844$12759_Y + connect \$5 $or$libresoc.v:177845$12760_Y + connect \$7 $not$libresoc.v:177846$12761_Y + connect \qlq_src \$15 + connect \qn_src \$13 + connect \q_src \$11 +end +attribute \src "libresoc.v:177865.1-177923.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.src_l" +attribute \generator "nMigen" +module \src_l$81 + attribute \src "libresoc.v:177866.7-177866.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:177911.3-177919.6" + wire width 3 $0\q_int$next[2:0]$12778 + attribute \src "libresoc.v:177909.3-177910.27" + wire width 3 $0\q_int[2:0] + attribute \src "libresoc.v:177911.3-177919.6" + wire width 3 $1\q_int$next[2:0]$12779 + attribute \src "libresoc.v:177888.13-177888.25" + wire width 3 $1\q_int[2:0] + attribute \src "libresoc.v:177901.17-177901.96" + wire width 3 $and$libresoc.v:177901$12768_Y + attribute \src "libresoc.v:177906.17-177906.96" + wire width 3 $and$libresoc.v:177906$12773_Y + attribute \src "libresoc.v:177903.18-177903.93" + wire width 3 $not$libresoc.v:177903$12770_Y + attribute \src "libresoc.v:177905.17-177905.92" + wire width 3 $not$libresoc.v:177905$12772_Y + attribute \src "libresoc.v:177908.17-177908.92" + wire width 3 $not$libresoc.v:177908$12775_Y + attribute \src "libresoc.v:177902.18-177902.98" + wire width 3 $or$libresoc.v:177902$12769_Y + attribute \src "libresoc.v:177904.18-177904.99" + wire width 3 $or$libresoc.v:177904$12771_Y + attribute \src "libresoc.v:177907.17-177907.97" + wire width 3 $or$libresoc.v:177907$12774_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 3 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 3 \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 3 \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire width 3 \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 3 \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 3 \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 3 \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 3 \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 1 \coresync_rst + attribute \src "libresoc.v:177866.7-177866.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 3 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 3 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 3 output 4 \q_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire width 3 \qlq_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 3 \qn_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 3 input 3 \r_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 3 input 2 \s_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$libresoc.v:177901$12768 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:177901$12768_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:177906$12773 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:177906$12773_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:177903$12770 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_src + connect \Y $not$libresoc.v:177903$12770_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:177905$12772 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \r_src + connect \Y $not$libresoc.v:177905$12772_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:177908$12775 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \r_src + connect \Y $not$libresoc.v:177908$12775_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:177902$12769 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \$9 + connect \B \s_src + connect \Y $or$libresoc.v:177902$12769_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:177904$12771 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_src + connect \B \q_int + connect \Y $or$libresoc.v:177904$12771_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:177907$12774 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \$3 + connect \B \s_src + connect \Y $or$libresoc.v:177907$12774_Y + end + attribute \src "libresoc.v:177866.7-177866.20" + process $proc$libresoc.v:177866$12780 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:177888.13-177888.25" + process $proc$libresoc.v:177888$12781 + assign { } { } + assign $1\q_int[2:0] 3'000 + sync always + sync init + update \q_int $1\q_int[2:0] + end + attribute \src "libresoc.v:177909.3-177910.27" + process $proc$libresoc.v:177909$12776 + assign { } { } + assign $0\q_int[2:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[2:0] + end + attribute \src "libresoc.v:177911.3-177919.6" + process $proc$libresoc.v:177911$12777 + assign { } { } + assign { } { } + assign $0\q_int$next[2:0]$12778 $1\q_int$next[2:0]$12779 + attribute \src "libresoc.v:177912.5-177912.29" + switch \initial + attribute \src "libresoc.v:177912.9-177912.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[2:0]$12779 3'000 + case + assign $1\q_int$next[2:0]$12779 \$5 + end + sync always + update \q_int$next $0\q_int$next[2:0]$12778 + end + connect \$9 $and$libresoc.v:177901$12768_Y + connect \$11 $or$libresoc.v:177902$12769_Y + connect \$13 $not$libresoc.v:177903$12770_Y + connect \$15 $or$libresoc.v:177904$12771_Y + connect \$1 $not$libresoc.v:177905$12772_Y + connect \$3 $and$libresoc.v:177906$12773_Y + connect \$5 $or$libresoc.v:177907$12774_Y + connect \$7 $not$libresoc.v:177908$12775_Y + connect \qlq_src \$15 + connect \qn_src \$13 + connect \q_src \$11 +end +attribute \src "libresoc.v:177927.1-177985.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.src_l" +attribute \generator "nMigen" +module \src_l$98 + attribute \src "libresoc.v:177928.7-177928.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:177973.3-177981.6" + wire width 3 $0\q_int$next[2:0]$12792 + attribute \src "libresoc.v:177971.3-177972.27" + wire width 3 $0\q_int[2:0] + attribute \src "libresoc.v:177973.3-177981.6" + wire width 3 $1\q_int$next[2:0]$12793 + attribute \src "libresoc.v:177950.13-177950.25" + wire width 3 $1\q_int[2:0] + attribute \src "libresoc.v:177963.17-177963.96" + wire width 3 $and$libresoc.v:177963$12782_Y + attribute \src "libresoc.v:177968.17-177968.96" + wire width 3 $and$libresoc.v:177968$12787_Y + attribute \src "libresoc.v:177965.18-177965.93" + wire width 3 $not$libresoc.v:177965$12784_Y + attribute \src "libresoc.v:177967.17-177967.92" + wire width 3 $not$libresoc.v:177967$12786_Y + attribute \src "libresoc.v:177970.17-177970.92" + wire width 3 $not$libresoc.v:177970$12789_Y + attribute \src "libresoc.v:177964.18-177964.98" + wire width 3 $or$libresoc.v:177964$12783_Y + attribute \src "libresoc.v:177966.18-177966.99" + wire width 3 $or$libresoc.v:177966$12785_Y + attribute \src "libresoc.v:177969.17-177969.97" + wire width 3 $or$libresoc.v:177969$12788_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 3 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 3 \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 3 \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire width 3 \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 3 \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 3 \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 3 \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 3 \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 1 \coresync_rst + attribute \src "libresoc.v:177928.7-177928.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 3 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 3 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 3 output 4 \q_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire width 3 \qlq_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 3 \qn_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 3 input 3 \r_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 3 input 2 \s_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$libresoc.v:177963$12782 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:177963$12782_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:177968$12787 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:177968$12787_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:177965$12784 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_src + connect \Y $not$libresoc.v:177965$12784_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:177967$12786 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \r_src + connect \Y $not$libresoc.v:177967$12786_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:177970$12789 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \r_src + connect \Y $not$libresoc.v:177970$12789_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:177964$12783 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \$9 + connect \B \s_src + connect \Y $or$libresoc.v:177964$12783_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:177966$12785 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_src + connect \B \q_int + connect \Y $or$libresoc.v:177966$12785_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:177969$12788 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \$3 + connect \B \s_src + connect \Y $or$libresoc.v:177969$12788_Y + end + attribute \src "libresoc.v:177928.7-177928.20" + process $proc$libresoc.v:177928$12794 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:177950.13-177950.25" + process $proc$libresoc.v:177950$12795 + assign { } { } + assign $1\q_int[2:0] 3'000 + sync always + sync init + update \q_int $1\q_int[2:0] + end + attribute \src "libresoc.v:177971.3-177972.27" + process $proc$libresoc.v:177971$12790 + assign { } { } + assign $0\q_int[2:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[2:0] + end + attribute \src "libresoc.v:177973.3-177981.6" + process $proc$libresoc.v:177973$12791 + assign { } { } + assign { } { } + assign $0\q_int$next[2:0]$12792 $1\q_int$next[2:0]$12793 + attribute \src "libresoc.v:177974.5-177974.29" + switch \initial + attribute \src "libresoc.v:177974.9-177974.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[2:0]$12793 3'000 + case + assign $1\q_int$next[2:0]$12793 \$5 + end + sync always + update \q_int$next $0\q_int$next[2:0]$12792 + end + connect \$9 $and$libresoc.v:177963$12782_Y + connect \$11 $or$libresoc.v:177964$12783_Y + connect \$13 $not$libresoc.v:177965$12784_Y + connect \$15 $or$libresoc.v:177966$12785_Y + connect \$1 $not$libresoc.v:177967$12786_Y + connect \$3 $and$libresoc.v:177968$12787_Y + connect \$5 $or$libresoc.v:177969$12788_Y + connect \$7 $not$libresoc.v:177970$12789_Y + connect \qlq_src \$15 + connect \qn_src \$13 + connect \q_src \$11 +end +attribute \src "libresoc.v:177989.1-178047.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.l0.pimem.st_active" +attribute \generator "nMigen" +module \st_active + attribute \src "libresoc.v:177990.7-177990.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:178035.3-178043.6" + wire $0\q_int$next[0:0]$12806 + attribute \src "libresoc.v:178033.3-178034.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:178035.3-178043.6" + wire $1\q_int$next[0:0]$12807 + attribute \src "libresoc.v:178012.7-178012.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:178025.17-178025.96" + wire $and$libresoc.v:178025$12796_Y + attribute \src "libresoc.v:178030.17-178030.96" + wire $and$libresoc.v:178030$12801_Y + attribute \src "libresoc.v:178027.18-178027.99" + wire $not$libresoc.v:178027$12798_Y + attribute \src "libresoc.v:178029.17-178029.98" + wire $not$libresoc.v:178029$12800_Y + attribute \src "libresoc.v:178032.17-178032.98" + wire $not$libresoc.v:178032$12803_Y + attribute \src "libresoc.v:178026.18-178026.104" + wire $or$libresoc.v:178026$12797_Y + attribute \src "libresoc.v:178028.18-178028.105" + wire $or$libresoc.v:178028$12799_Y + attribute \src "libresoc.v:178031.17-178031.103" + wire $or$libresoc.v:178031$12802_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 1 \coresync_rst + attribute \src "libresoc.v:177990.7-177990.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 4 \q_st_active + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_st_active + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_st_active + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 2 \r_st_active + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 3 \s_st_active + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$libresoc.v:178025$12796 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:178025$12796_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:178030$12801 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:178030$12801_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:178027$12798 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_st_active + connect \Y $not$libresoc.v:178027$12798_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:178029$12800 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_st_active + connect \Y $not$libresoc.v:178029$12800_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:178032$12803 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_st_active + connect \Y $not$libresoc.v:178032$12803_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:178026$12797 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_st_active + connect \Y $or$libresoc.v:178026$12797_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:178028$12799 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_st_active + connect \B \q_int + connect \Y $or$libresoc.v:178028$12799_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:178031$12802 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_st_active + connect \Y $or$libresoc.v:178031$12802_Y + end + attribute \src "libresoc.v:177990.7-177990.20" + process $proc$libresoc.v:177990$12808 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:178012.7-178012.19" + process $proc$libresoc.v:178012$12809 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:178033.3-178034.27" + process $proc$libresoc.v:178033$12804 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:178035.3-178043.6" + process $proc$libresoc.v:178035$12805 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$12806 $1\q_int$next[0:0]$12807 + attribute \src "libresoc.v:178036.5-178036.29" + switch \initial + attribute \src "libresoc.v:178036.9-178036.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$12807 1'0 + case + assign $1\q_int$next[0:0]$12807 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$12806 + end + connect \$9 $and$libresoc.v:178025$12796_Y + connect \$11 $or$libresoc.v:178026$12797_Y + connect \$13 $not$libresoc.v:178027$12798_Y + connect \$15 $or$libresoc.v:178028$12799_Y + connect \$1 $not$libresoc.v:178029$12800_Y + connect \$3 $and$libresoc.v:178030$12801_Y + connect \$5 $or$libresoc.v:178031$12802_Y + connect \$7 $not$libresoc.v:178032$12803_Y + connect \qlq_st_active \$15 + connect \qn_st_active \$13 + connect \q_st_active \$11 +end +attribute \src "libresoc.v:178051.1-178109.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.l0.pimem.st_done" +attribute \generator "nMigen" +module \st_done + attribute \src "libresoc.v:178052.7-178052.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:178097.3-178105.6" + wire $0\q_int$next[0:0]$12820 + attribute \src "libresoc.v:178095.3-178096.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:178097.3-178105.6" + wire $1\q_int$next[0:0]$12821 + attribute \src "libresoc.v:178074.7-178074.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:178087.17-178087.96" + wire $and$libresoc.v:178087$12810_Y + attribute \src "libresoc.v:178092.17-178092.96" + wire $and$libresoc.v:178092$12815_Y + attribute \src "libresoc.v:178089.18-178089.97" + wire $not$libresoc.v:178089$12812_Y + attribute \src "libresoc.v:178091.17-178091.96" + wire $not$libresoc.v:178091$12814_Y + attribute \src "libresoc.v:178094.17-178094.96" + wire $not$libresoc.v:178094$12817_Y + attribute \src "libresoc.v:178088.18-178088.102" + wire $or$libresoc.v:178088$12811_Y + attribute \src "libresoc.v:178090.18-178090.103" + wire $or$libresoc.v:178090$12813_Y + attribute \src "libresoc.v:178093.17-178093.101" + wire $or$libresoc.v:178093$12816_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 1 \coresync_rst + attribute \src "libresoc.v:178052.7-178052.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 4 \q_st_done + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_st_done + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_st_done + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_st_done + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 2 \s_st_done + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$libresoc.v:178087$12810 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:178087$12810_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:178092$12815 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:178092$12815_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:178089$12812 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_st_done + connect \Y $not$libresoc.v:178089$12812_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:178091$12814 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_st_done + connect \Y $not$libresoc.v:178091$12814_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:178094$12817 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_st_done + connect \Y $not$libresoc.v:178094$12817_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:178088$12811 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_st_done + connect \Y $or$libresoc.v:178088$12811_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:178090$12813 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_st_done + connect \B \q_int + connect \Y $or$libresoc.v:178090$12813_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:178093$12816 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_st_done + connect \Y $or$libresoc.v:178093$12816_Y + end + attribute \src "libresoc.v:178052.7-178052.20" + process $proc$libresoc.v:178052$12822 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:178074.7-178074.19" + process $proc$libresoc.v:178074$12823 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:178095.3-178096.27" + process $proc$libresoc.v:178095$12818 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:178097.3-178105.6" + process $proc$libresoc.v:178097$12819 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$12820 $1\q_int$next[0:0]$12821 + attribute \src "libresoc.v:178098.5-178098.29" + switch \initial + attribute \src "libresoc.v:178098.9-178098.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$12821 1'0 + case + assign $1\q_int$next[0:0]$12821 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$12820 + end + connect \$9 $and$libresoc.v:178087$12810_Y + connect \$11 $or$libresoc.v:178088$12811_Y + connect \$13 $not$libresoc.v:178089$12812_Y + connect \$15 $or$libresoc.v:178090$12813_Y + connect \$1 $not$libresoc.v:178091$12814_Y + connect \$3 $and$libresoc.v:178092$12815_Y + connect \$5 $or$libresoc.v:178093$12816_Y + connect \$7 $not$libresoc.v:178094$12817_Y + connect \qlq_st_done \$15 + connect \qn_st_done \$13 + connect \q_st_done \$11 +end +attribute \src "libresoc.v:178113.1-178368.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.state" +attribute \generator "nMigen" +module \state + attribute \src "libresoc.v:178341.3-178350.6" + wire width 64 $0\cia__data_o[63:0] + attribute \src "libresoc.v:178114.7-178114.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:178322.3-178331.6" + wire width 64 $0\msr__data_o[63:0] + attribute \src "libresoc.v:178313.3-178321.6" + wire width 4 $0\ren_delay$12$next[3:0]$12836 + attribute \src "libresoc.v:178253.3-178254.43" + wire width 4 $0\ren_delay$12[3:0]$12833 + attribute \src "libresoc.v:178234.13-178234.34" + wire width 4 $0\ren_delay$12[3:0]$12846 + attribute \src "libresoc.v:178332.3-178340.6" + wire width 4 $0\ren_delay$next[3:0]$12840 + attribute \src "libresoc.v:178255.3-178256.35" + wire width 4 $0\ren_delay[3:0] + attribute \src "libresoc.v:178341.3-178350.6" + wire width 64 $1\cia__data_o[63:0] + attribute \src "libresoc.v:178322.3-178331.6" + wire width 64 $1\msr__data_o[63:0] + attribute \src "libresoc.v:178313.3-178321.6" + wire width 4 $1\ren_delay$12$next[3:0]$12837 + attribute \src "libresoc.v:178332.3-178340.6" + wire width 4 $1\ren_delay$next[3:0]$12841 + attribute \src "libresoc.v:178232.13-178232.29" + wire width 4 $1\ren_delay[3:0] + attribute \src "libresoc.v:178245.18-178245.95" + wire width 64 $or$libresoc.v:178245$12824_Y + attribute \src "libresoc.v:178247.18-178247.124" + wire width 64 $or$libresoc.v:178247$12826_Y + attribute \src "libresoc.v:178248.18-178248.124" + wire width 64 $or$libresoc.v:178248$12827_Y + attribute \src "libresoc.v:178249.18-178249.97" + wire width 64 $or$libresoc.v:178249$12828_Y + attribute \src "libresoc.v:178251.17-178251.123" + wire width 64 $or$libresoc.v:178251$12830_Y + attribute \src "libresoc.v:178252.17-178252.123" + wire width 64 $or$libresoc.v:178252$12831_Y + attribute \src "libresoc.v:178246.18-178246.100" + wire $reduce_or$libresoc.v:178246$12825_Y + attribute \src "libresoc.v:178250.17-178250.95" + wire $reduce_or$libresoc.v:178250$12829_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 64 \$10 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 64 \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 64 \$17 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 64 \$19 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 64 \$6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 64 \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 output 2 \cia__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 input 1 \cia__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 12 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 11 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 input 4 \data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 input 8 \data_i$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 input 9 \data_i$2 + attribute \src "libresoc.v:178114.7-178114.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 output 6 \msr__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 input 5 \msr__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \reg_0_cia0__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_0_cia0__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \reg_0_d_wr10__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_0_d_wr10__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \reg_0_msr0__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \reg_0_msr0__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_0_msr0__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_0_msr0__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \reg_0_nia0__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_0_nia0__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \reg_1_cia1__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_1_cia1__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \reg_1_d_wr11__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_1_d_wr11__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \reg_1_msr1__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \reg_1_msr1__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_1_msr1__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_1_msr1__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \reg_1_nia1__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_1_nia1__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \reg_2_cia2__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_2_cia2__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \reg_2_d_wr12__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_2_d_wr12__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \reg_2_msr2__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \reg_2_msr2__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_2_msr2__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_2_msr2__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \reg_2_nia2__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_2_nia2__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \reg_3_cia3__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_3_cia3__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \reg_3_d_wr13__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_3_d_wr13__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \reg_3_msr3__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \reg_3_msr3__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_3_msr3__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_3_msr3__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \reg_3_nia3__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_3_nia3__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" + wire width 4 \ren_delay + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" + wire width 4 \ren_delay$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" + wire width 4 \ren_delay$12$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" + wire width 4 \ren_delay$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 input 7 \state_nia_wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 input 3 \wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 input 10 \wen$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $or$libresoc.v:178245$12824 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \$6 + connect \B \$8 + connect \Y $or$libresoc.v:178245$12824_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $or$libresoc.v:178247$12826 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \reg_0_msr0__data_o + connect \B \reg_1_msr1__data_o + connect \Y $or$libresoc.v:178247$12826_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $or$libresoc.v:178248$12827 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \reg_2_msr2__data_o + connect \B \reg_3_msr3__data_o + connect \Y $or$libresoc.v:178248$12827_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $or$libresoc.v:178249$12828 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \$15 + connect \B \$17 + connect \Y $or$libresoc.v:178249$12828_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $or$libresoc.v:178251$12830 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \reg_0_cia0__data_o + connect \B \reg_1_cia1__data_o + connect \Y $or$libresoc.v:178251$12830_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $or$libresoc.v:178252$12831 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \reg_2_cia2__data_o + connect \B \reg_3_cia3__data_o + connect \Y $or$libresoc.v:178252$12831_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + cell $reduce_or $reduce_or$libresoc.v:178246$12825 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \ren_delay$12 + connect \Y $reduce_or$libresoc.v:178246$12825_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + cell $reduce_or $reduce_or$libresoc.v:178250$12829 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \ren_delay + connect \Y $reduce_or$libresoc.v:178250$12829_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:178257.15-178270.4" + cell \reg_0$132 \reg_0 + connect \cia0__data_o \reg_0_cia0__data_o + connect \cia0__ren \reg_0_cia0__ren + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \d_wr10__data_i \reg_0_d_wr10__data_i + connect \d_wr10__wen \reg_0_d_wr10__wen + connect \msr0__data_i \reg_0_msr0__data_i + connect \msr0__data_o \reg_0_msr0__data_o + connect \msr0__ren \reg_0_msr0__ren + connect \msr0__wen \reg_0_msr0__wen + connect \nia0__data_i \reg_0_nia0__data_i + connect \nia0__wen \reg_0_nia0__wen + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:178271.15-178284.4" + cell \reg_1$133 \reg_1 + connect \cia1__data_o \reg_1_cia1__data_o + connect \cia1__ren \reg_1_cia1__ren + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \d_wr11__data_i \reg_1_d_wr11__data_i + connect \d_wr11__wen \reg_1_d_wr11__wen + connect \msr1__data_i \reg_1_msr1__data_i + connect \msr1__data_o \reg_1_msr1__data_o + connect \msr1__ren \reg_1_msr1__ren + connect \msr1__wen \reg_1_msr1__wen + connect \nia1__data_i \reg_1_nia1__data_i + connect \nia1__wen \reg_1_nia1__wen + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:178285.15-178298.4" + cell \reg_2$134 \reg_2 + connect \cia2__data_o \reg_2_cia2__data_o + connect \cia2__ren \reg_2_cia2__ren + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \d_wr12__data_i \reg_2_d_wr12__data_i + connect \d_wr12__wen \reg_2_d_wr12__wen + connect \msr2__data_i \reg_2_msr2__data_i + connect \msr2__data_o \reg_2_msr2__data_o + connect \msr2__ren \reg_2_msr2__ren + connect \msr2__wen \reg_2_msr2__wen + connect \nia2__data_i \reg_2_nia2__data_i + connect \nia2__wen \reg_2_nia2__wen + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:178299.15-178312.4" + cell \reg_3$135 \reg_3 + connect \cia3__data_o \reg_3_cia3__data_o + connect \cia3__ren \reg_3_cia3__ren + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \d_wr13__data_i \reg_3_d_wr13__data_i + connect \d_wr13__wen \reg_3_d_wr13__wen + connect \msr3__data_i \reg_3_msr3__data_i + connect \msr3__data_o \reg_3_msr3__data_o + connect \msr3__ren \reg_3_msr3__ren + connect \msr3__wen \reg_3_msr3__wen + connect \nia3__data_i \reg_3_nia3__data_i + connect \nia3__wen \reg_3_nia3__wen + end + attribute \src "libresoc.v:178114.7-178114.20" + process $proc$libresoc.v:178114$12843 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:178232.13-178232.29" + process $proc$libresoc.v:178232$12844 + assign { } { } + assign $1\ren_delay[3:0] 4'0000 + sync always + sync init + update \ren_delay $1\ren_delay[3:0] + end + attribute \src "libresoc.v:178234.13-178234.34" + process $proc$libresoc.v:178234$12845 + assign { } { } + assign $0\ren_delay$12[3:0]$12846 4'0000 + sync always + sync init + update \ren_delay$12 $0\ren_delay$12[3:0]$12846 + end + attribute \src "libresoc.v:178253.3-178254.43" + process $proc$libresoc.v:178253$12832 + assign { } { } + assign $0\ren_delay$12[3:0]$12833 \ren_delay$12$next + sync posedge \coresync_clk + update \ren_delay$12 $0\ren_delay$12[3:0]$12833 + end + attribute \src "libresoc.v:178255.3-178256.35" + process $proc$libresoc.v:178255$12834 + assign { } { } + assign $0\ren_delay[3:0] \ren_delay$next + sync posedge \coresync_clk + update \ren_delay $0\ren_delay[3:0] + end + attribute \src "libresoc.v:178313.3-178321.6" + process $proc$libresoc.v:178313$12835 + assign { } { } + assign { } { } + assign $0\ren_delay$12$next[3:0]$12836 $1\ren_delay$12$next[3:0]$12837 + attribute \src "libresoc.v:178314.5-178314.29" + switch \initial + attribute \src "libresoc.v:178314.9-178314.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ren_delay$12$next[3:0]$12837 4'0000 + case + assign $1\ren_delay$12$next[3:0]$12837 \msr__ren + end + sync always + update \ren_delay$12$next $0\ren_delay$12$next[3:0]$12836 + end + attribute \src "libresoc.v:178322.3-178331.6" + process $proc$libresoc.v:178322$12838 + assign { } { } + assign { } { } + assign $0\msr__data_o[63:0] $1\msr__data_o[63:0] + attribute \src "libresoc.v:178323.5-178323.29" + switch \initial + attribute \src "libresoc.v:178323.9-178323.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" + switch \$13 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\msr__data_o[63:0] \$19 + case + assign $1\msr__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \msr__data_o $0\msr__data_o[63:0] + end + attribute \src "libresoc.v:178332.3-178340.6" + process $proc$libresoc.v:178332$12839 + assign { } { } + assign { } { } + assign $0\ren_delay$next[3:0]$12840 $1\ren_delay$next[3:0]$12841 + attribute \src "libresoc.v:178333.5-178333.29" + switch \initial + attribute \src "libresoc.v:178333.9-178333.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ren_delay$next[3:0]$12841 4'0000 + case + assign $1\ren_delay$next[3:0]$12841 \cia__ren + end + sync always + update \ren_delay$next $0\ren_delay$next[3:0]$12840 + end + attribute \src "libresoc.v:178341.3-178350.6" + process $proc$libresoc.v:178341$12842 + assign { } { } + assign { } { } + assign $0\cia__data_o[63:0] $1\cia__data_o[63:0] + attribute \src "libresoc.v:178342.5-178342.29" + switch \initial + attribute \src "libresoc.v:178342.9-178342.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" + switch \$4 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cia__data_o[63:0] \$10 + case + assign $1\cia__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \cia__data_o $0\cia__data_o[63:0] + end + connect \$10 $or$libresoc.v:178245$12824_Y + connect \$13 $reduce_or$libresoc.v:178246$12825_Y + connect \$15 $or$libresoc.v:178247$12826_Y + connect \$17 $or$libresoc.v:178248$12827_Y + connect \$19 $or$libresoc.v:178249$12828_Y + connect \$4 $reduce_or$libresoc.v:178250$12829_Y + connect \$6 $or$libresoc.v:178251$12830_Y + connect \$8 $or$libresoc.v:178252$12831_Y + connect \reg_3_d_wr13__data_i \data_i + connect \reg_2_d_wr12__data_i \data_i + connect \reg_1_d_wr11__data_i \data_i + connect \reg_0_d_wr10__data_i \data_i + connect { \reg_3_d_wr13__wen \reg_2_d_wr12__wen \reg_1_d_wr11__wen \reg_0_d_wr10__wen } \wen + connect \reg_3_msr3__data_i \data_i$2 + connect \reg_2_msr2__data_i \data_i$2 + connect \reg_1_msr1__data_i \data_i$2 + connect \reg_0_msr0__data_i \data_i$2 + connect { \reg_3_msr3__wen \reg_2_msr2__wen \reg_1_msr1__wen \reg_0_msr0__wen } \wen$3 + connect \reg_3_nia3__data_i \data_i$1 + connect \reg_2_nia2__data_i \data_i$1 + connect \reg_1_nia1__data_i \data_i$1 + connect \reg_0_nia0__data_i \data_i$1 + connect { \reg_3_nia3__wen \reg_2_nia2__wen \reg_1_nia1__wen \reg_0_nia0__wen } \state_nia_wen + connect { \reg_3_msr3__ren \reg_2_msr2__ren \reg_1_msr1__ren \reg_0_msr0__ren } \msr__ren + connect { \reg_3_cia3__ren \reg_2_cia2__ren \reg_1_cia1__ren \reg_0_cia0__ren } \cia__ren +end +attribute \src "libresoc.v:178372.1-178430.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.sto_l" +attribute \generator "nMigen" +module \sto_l + attribute \src "libresoc.v:178373.7-178373.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:178418.3-178426.6" + wire $0\q_int$next[0:0]$12857 + attribute \src "libresoc.v:178416.3-178417.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:178418.3-178426.6" + wire $1\q_int$next[0:0]$12858 + attribute \src "libresoc.v:178395.7-178395.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:178408.17-178408.96" + wire $and$libresoc.v:178408$12847_Y + attribute \src "libresoc.v:178413.17-178413.96" + wire $and$libresoc.v:178413$12852_Y + attribute \src "libresoc.v:178410.18-178410.93" + wire $not$libresoc.v:178410$12849_Y + attribute \src "libresoc.v:178412.17-178412.92" + wire $not$libresoc.v:178412$12851_Y + attribute \src "libresoc.v:178415.17-178415.92" + wire $not$libresoc.v:178415$12854_Y + attribute \src "libresoc.v:178409.18-178409.98" + wire $or$libresoc.v:178409$12848_Y + attribute \src "libresoc.v:178411.18-178411.99" + wire $or$libresoc.v:178411$12850_Y + attribute \src "libresoc.v:178414.17-178414.97" + wire $or$libresoc.v:178414$12853_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 1 \coresync_rst + attribute \src "libresoc.v:178373.7-178373.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 4 \q_sto + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_sto + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_sto + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_sto + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 2 \s_sto + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$libresoc.v:178408$12847 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:178408$12847_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:178413$12852 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:178413$12852_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:178410$12849 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_sto + connect \Y $not$libresoc.v:178410$12849_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:178412$12851 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_sto + connect \Y $not$libresoc.v:178412$12851_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:178415$12854 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_sto + connect \Y $not$libresoc.v:178415$12854_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:178409$12848 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_sto + connect \Y $or$libresoc.v:178409$12848_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:178411$12850 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_sto + connect \B \q_int + connect \Y $or$libresoc.v:178411$12850_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:178414$12853 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_sto + connect \Y $or$libresoc.v:178414$12853_Y + end + attribute \src "libresoc.v:178373.7-178373.20" + process $proc$libresoc.v:178373$12859 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:178395.7-178395.19" + process $proc$libresoc.v:178395$12860 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:178416.3-178417.27" + process $proc$libresoc.v:178416$12855 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:178418.3-178426.6" + process $proc$libresoc.v:178418$12856 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$12857 $1\q_int$next[0:0]$12858 + attribute \src "libresoc.v:178419.5-178419.29" + switch \initial + attribute \src "libresoc.v:178419.9-178419.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$12858 1'0 + case + assign $1\q_int$next[0:0]$12858 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$12857 + end + connect \$9 $and$libresoc.v:178408$12847_Y + connect \$11 $or$libresoc.v:178409$12848_Y + connect \$13 $not$libresoc.v:178410$12849_Y + connect \$15 $or$libresoc.v:178411$12850_Y + connect \$1 $not$libresoc.v:178412$12851_Y + connect \$3 $and$libresoc.v:178413$12852_Y + connect \$5 $or$libresoc.v:178414$12853_Y + connect \$7 $not$libresoc.v:178415$12854_Y + connect \qlq_sto \$15 + connect \qn_sto \$13 + connect \q_sto \$11 +end +attribute \src "libresoc.v:178435.1-181610.10" +attribute \cells_not_processed 1 +attribute \top 1 +attribute \nmigen.hierarchy "test_issuer" +attribute \generator "nMigen" +module \test_issuer + attribute \src "libresoc.v:181056.3-181162.6" + wire width 8 $0\core_asmcode$next[7:0]$13064 + attribute \src "libresoc.v:180143.3-180144.41" + wire width 8 $0\core_asmcode[7:0] + attribute \src "libresoc.v:181227.3-181263.6" + wire $0\core_bigendian_i$3$next[0:0]$13303 + attribute \src "libresoc.v:180139.3-180140.55" + wire $0\core_bigendian_i$3[0:0]$12926 + attribute \src "libresoc.v:178576.7-178576.34" + wire $0\core_bigendian_i$3[0:0]$13366 + attribute \src "libresoc.v:180951.3-180963.6" + wire width 4 $0\core_cia__ren[3:0] + attribute \src "libresoc.v:181056.3-181162.6" + wire width 64 $0\core_core_core_cia$next[63:0]$13065 + attribute \src "libresoc.v:180219.3-180220.53" + wire width 64 $0\core_core_core_cia[63:0] + attribute \src "libresoc.v:181056.3-181162.6" + wire width 8 $0\core_core_core_cr_rd$next[7:0]$13066 + attribute \src "libresoc.v:180245.3-180246.57" + wire width 8 $0\core_core_core_cr_rd[7:0] + attribute \src "libresoc.v:181056.3-181162.6" + wire $0\core_core_core_cr_rd_ok$next[0:0]$13067 + attribute \src "libresoc.v:180247.3-180248.63" + wire $0\core_core_core_cr_rd_ok[0:0] + attribute \src "libresoc.v:181056.3-181162.6" + wire width 8 $0\core_core_core_cr_wr$next[7:0]$13068 + attribute \src "libresoc.v:180249.3-180250.57" + wire width 8 $0\core_core_core_cr_wr[7:0] + attribute \src "libresoc.v:181056.3-181162.6" + wire width 12 $0\core_core_core_fn_unit$next[11:0]$13069 + attribute \src "libresoc.v:180225.3-180226.61" + wire width 12 $0\core_core_core_fn_unit[11:0] + attribute \src "libresoc.v:181056.3-181162.6" + wire width 2 $0\core_core_core_input_carry$next[1:0]$13070 + attribute \src "libresoc.v:180239.3-180240.69" + wire width 2 $0\core_core_core_input_carry[1:0] + attribute \src "libresoc.v:181056.3-181162.6" + wire width 32 $0\core_core_core_insn$next[31:0]$13071 + attribute \src "libresoc.v:180221.3-180222.55" + wire width 32 $0\core_core_core_insn[31:0] + attribute \src "libresoc.v:181056.3-181162.6" + wire width 7 $0\core_core_core_insn_type$next[6:0]$13072 + attribute \src "libresoc.v:180223.3-180224.65" + wire width 7 $0\core_core_core_insn_type[6:0] + attribute \src "libresoc.v:181056.3-181162.6" + wire $0\core_core_core_is_32bit$next[0:0]$13073 + attribute \src "libresoc.v:180253.3-180254.63" + wire $0\core_core_core_is_32bit[0:0] + attribute \src "libresoc.v:181056.3-181162.6" + wire width 64 $0\core_core_core_msr$next[63:0]$13074 + attribute \src "libresoc.v:180217.3-180218.53" + wire width 64 $0\core_core_core_msr[63:0] + attribute \src "libresoc.v:181056.3-181162.6" + wire $0\core_core_core_oe$next[0:0]$13075 + attribute \src "libresoc.v:180233.3-180234.51" + wire $0\core_core_core_oe[0:0] + attribute \src "libresoc.v:181056.3-181162.6" + wire $0\core_core_core_oe_ok$next[0:0]$13076 + attribute \src "libresoc.v:180235.3-180236.57" + wire $0\core_core_core_oe_ok[0:0] + attribute \src "libresoc.v:181056.3-181162.6" + wire $0\core_core_core_rc$next[0:0]$13077 + attribute \src "libresoc.v:180229.3-180230.51" + wire $0\core_core_core_rc[0:0] + attribute \src "libresoc.v:181056.3-181162.6" + wire $0\core_core_core_rc_ok$next[0:0]$13078 + attribute \src "libresoc.v:180231.3-180232.57" + wire $0\core_core_core_rc_ok[0:0] + attribute \src "libresoc.v:181056.3-181162.6" + wire width 13 $0\core_core_core_trapaddr$next[12:0]$13079 + attribute \src "libresoc.v:180243.3-180244.63" + wire width 13 $0\core_core_core_trapaddr[12:0] + attribute \src "libresoc.v:181056.3-181162.6" + wire width 7 $0\core_core_core_traptype$next[6:0]$13080 + attribute \src "libresoc.v:180241.3-180242.63" + wire width 7 $0\core_core_core_traptype[6:0] + attribute \src "libresoc.v:181056.3-181162.6" + wire width 3 $0\core_core_cr_in1$next[2:0]$13081 + attribute \src "libresoc.v:180199.3-180200.49" + wire width 3 $0\core_core_cr_in1[2:0] + attribute \src "libresoc.v:181056.3-181162.6" + wire $0\core_core_cr_in1_ok$next[0:0]$13082 + attribute \src "libresoc.v:180201.3-180202.55" + wire $0\core_core_cr_in1_ok[0:0] + attribute \src "libresoc.v:181056.3-181162.6" + wire width 3 $0\core_core_cr_in2$1$next[2:0]$13083 + attribute \src "libresoc.v:180207.3-180208.55" + wire width 3 $0\core_core_cr_in2$1[2:0]$12962 + attribute \src "libresoc.v:178749.13-178749.40" + wire width 3 $0\core_core_cr_in2$1[2:0]$13387 + attribute \src "libresoc.v:181056.3-181162.6" + wire width 3 $0\core_core_cr_in2$next[2:0]$13084 + attribute \src "libresoc.v:180203.3-180204.49" + wire width 3 $0\core_core_cr_in2[2:0] + attribute \src "libresoc.v:181056.3-181162.6" + wire $0\core_core_cr_in2_ok$2$next[0:0]$13085 + attribute \src "libresoc.v:180209.3-180210.61" + wire $0\core_core_cr_in2_ok$2[0:0]$12964 + attribute \src "libresoc.v:178757.7-178757.37" + wire $0\core_core_cr_in2_ok$2[0:0]$13390 + attribute \src "libresoc.v:181056.3-181162.6" + wire $0\core_core_cr_in2_ok$next[0:0]$13086 + attribute \src "libresoc.v:180205.3-180206.55" + wire $0\core_core_cr_in2_ok[0:0] + attribute \src "libresoc.v:181056.3-181162.6" + wire width 3 $0\core_core_cr_out$next[2:0]$13087 + attribute \src "libresoc.v:180211.3-180212.49" + wire width 3 $0\core_core_cr_out[2:0] + attribute \src "libresoc.v:181056.3-181162.6" + wire $0\core_core_cr_wr_ok$next[0:0]$13088 + attribute \src "libresoc.v:180251.3-180252.53" + wire $0\core_core_cr_wr_ok[0:0] + attribute \src "libresoc.v:181056.3-181162.6" + wire width 5 $0\core_core_ea$next[4:0]$13089 + attribute \src "libresoc.v:180151.3-180152.41" + wire width 5 $0\core_core_ea[4:0] + attribute \src "libresoc.v:181056.3-181162.6" + wire width 3 $0\core_core_fast1$next[2:0]$13090 + attribute \src "libresoc.v:180181.3-180182.47" + wire width 3 $0\core_core_fast1[2:0] + attribute \src "libresoc.v:181056.3-181162.6" + wire $0\core_core_fast1_ok$next[0:0]$13091 + attribute \src "libresoc.v:180183.3-180184.53" + wire $0\core_core_fast1_ok[0:0] + attribute \src "libresoc.v:181056.3-181162.6" + wire width 3 $0\core_core_fast2$next[2:0]$13092 + attribute \src "libresoc.v:180185.3-180186.47" + wire width 3 $0\core_core_fast2[2:0] + attribute \src "libresoc.v:181056.3-181162.6" + wire $0\core_core_fast2_ok$next[0:0]$13093 + attribute \src "libresoc.v:180187.3-180188.53" + wire $0\core_core_fast2_ok[0:0] + attribute \src "libresoc.v:181056.3-181162.6" + wire width 3 $0\core_core_fasto1$next[2:0]$13094 + attribute \src "libresoc.v:180189.3-180190.49" + wire width 3 $0\core_core_fasto1[2:0] + attribute \src "libresoc.v:181056.3-181162.6" + wire width 3 $0\core_core_fasto2$next[2:0]$13095 + attribute \src "libresoc.v:180195.3-180196.49" + wire width 3 $0\core_core_fasto2[2:0] + attribute \src "libresoc.v:181056.3-181162.6" + wire $0\core_core_lk$next[0:0]$13096 + attribute \src "libresoc.v:180227.3-180228.41" + wire $0\core_core_lk[0:0] + attribute \src "libresoc.v:181515.3-181546.6" + wire width 64 $0\core_core_pc$next[63:0]$13341 + attribute \src "libresoc.v:180259.3-180260.41" + wire width 64 $0\core_core_pc[63:0] + attribute \src "libresoc.v:181056.3-181162.6" + wire width 5 $0\core_core_reg1$next[4:0]$13097 + attribute \src "libresoc.v:180155.3-180156.45" + wire width 5 $0\core_core_reg1[4:0] + attribute \src "libresoc.v:181056.3-181162.6" + wire $0\core_core_reg1_ok$next[0:0]$13098 + attribute \src "libresoc.v:180157.3-180158.51" + wire $0\core_core_reg1_ok[0:0] + attribute \src "libresoc.v:181056.3-181162.6" + wire width 5 $0\core_core_reg2$next[4:0]$13099 + attribute \src "libresoc.v:180159.3-180160.45" + wire width 5 $0\core_core_reg2[4:0] + attribute \src "libresoc.v:181056.3-181162.6" + wire $0\core_core_reg2_ok$next[0:0]$13100 + attribute \src "libresoc.v:180161.3-180162.51" + wire $0\core_core_reg2_ok[0:0] + attribute \src "libresoc.v:181056.3-181162.6" + wire width 5 $0\core_core_reg3$next[4:0]$13101 + attribute \src "libresoc.v:180163.3-180164.45" + wire width 5 $0\core_core_reg3[4:0] + attribute \src "libresoc.v:181056.3-181162.6" + wire $0\core_core_reg3_ok$next[0:0]$13102 + attribute \src "libresoc.v:180165.3-180166.51" + wire $0\core_core_reg3_ok[0:0] + attribute \src "libresoc.v:181056.3-181162.6" + wire width 5 $0\core_core_rego$next[4:0]$13103 + attribute \src "libresoc.v:180145.3-180146.45" + wire width 5 $0\core_core_rego[4:0] + attribute \src "libresoc.v:181056.3-181162.6" + wire width 10 $0\core_core_spr1$next[9:0]$13104 + attribute \src "libresoc.v:180173.3-180174.45" + wire width 10 $0\core_core_spr1[9:0] + attribute \src "libresoc.v:181056.3-181162.6" + wire $0\core_core_spr1_ok$next[0:0]$13105 + attribute \src "libresoc.v:180175.3-180176.51" + wire $0\core_core_spr1_ok[0:0] + attribute \src "libresoc.v:181056.3-181162.6" + wire width 10 $0\core_core_spro$next[9:0]$13106 + attribute \src "libresoc.v:180167.3-180168.45" + wire width 10 $0\core_core_spro[9:0] + attribute \src "libresoc.v:181056.3-181162.6" + wire width 3 $0\core_core_xer_in$next[2:0]$13107 + attribute \src "libresoc.v:180177.3-180178.49" + wire width 3 $0\core_core_xer_in[2:0] + attribute \src "libresoc.v:181056.3-181162.6" + wire $0\core_cr_out_ok$next[0:0]$13108 + attribute \src "libresoc.v:180213.3-180214.45" + wire $0\core_cr_out_ok[0:0] + attribute \src "libresoc.v:180985.3-181005.6" + wire width 64 $0\core_data_i[63:0] + attribute \src "libresoc.v:181515.3-181546.6" + wire width 64 $0\core_dec$next[63:0]$13342 + attribute \src "libresoc.v:180129.3-180130.33" + wire width 64 $0\core_dec[63:0] + attribute \src "libresoc.v:180649.3-180658.6" + wire width 5 $0\core_dmi__addr[4:0] + attribute \src "libresoc.v:180659.3-180668.6" + wire $0\core_dmi__ren[0:0] + attribute \src "libresoc.v:181056.3-181162.6" + wire $0\core_ea_ok$next[0:0]$13109 + attribute \src "libresoc.v:180153.3-180154.37" + wire $0\core_ea_ok[0:0] + attribute \src "libresoc.v:181515.3-181546.6" + wire $0\core_eint$next[0:0]$13343 + attribute \src "libresoc.v:180281.3-180282.35" + wire $0\core_eint[0:0] + attribute \src "libresoc.v:181056.3-181162.6" + wire $0\core_fasto1_ok$next[0:0]$13110 + attribute \src "libresoc.v:180191.3-180192.45" + wire $0\core_fasto1_ok[0:0] + attribute \src "libresoc.v:181056.3-181162.6" + wire $0\core_fasto2_ok$next[0:0]$13111 + attribute \src "libresoc.v:180197.3-180198.45" + wire $0\core_fasto2_ok[0:0] + attribute \src "libresoc.v:180698.3-180707.6" + wire width 8 $0\core_full_rd2__ren[7:0] + attribute \src "libresoc.v:180737.3-180746.6" + wire width 3 $0\core_full_rd__ren[2:0] + attribute \src "libresoc.v:180845.3-180859.6" + wire width 3 $0\core_issue__addr$4[2:0]$13035 + attribute \src "libresoc.v:180776.3-180790.6" + wire width 3 $0\core_issue__addr[2:0] + attribute \src "libresoc.v:180875.3-180889.6" + wire width 64 $0\core_issue__data_i[63:0] + attribute \src "libresoc.v:180791.3-180805.6" + wire $0\core_issue__ren[0:0] + attribute \src "libresoc.v:180860.3-180874.6" + wire $0\core_issue__wen[0:0] + attribute \src "libresoc.v:180638.3-180648.6" + wire $0\core_issue_i[0:0] + attribute \src "libresoc.v:181571.3-181590.6" + wire $0\core_ivalid_i[0:0] + attribute \src "libresoc.v:181515.3-181546.6" + wire width 64 $0\core_msr$next[63:0]$13344 + attribute \src "libresoc.v:180279.3-180280.33" + wire width 64 $0\core_msr[63:0] + attribute \src "libresoc.v:181006.3-181021.6" + wire width 4 $0\core_msr__ren[3:0] + attribute \src "libresoc.v:181190.3-181226.6" + wire width 32 $0\core_raw_insn_i$next[31:0]$13297 + attribute \src "libresoc.v:180141.3-180142.47" + wire width 32 $0\core_raw_insn_i[31:0] + attribute \src "libresoc.v:181056.3-181162.6" + wire $0\core_rego_ok$next[0:0]$13112 + attribute \src "libresoc.v:180147.3-180148.41" + wire $0\core_rego_ok[0:0] + attribute \src "libresoc.v:181056.3-181162.6" + wire $0\core_spro_ok$next[0:0]$13113 + attribute \src "libresoc.v:180169.3-180170.41" + wire $0\core_spro_ok[0:0] + attribute \src "libresoc.v:181437.3-181455.6" + wire $0\core_stopped_i[0:0] + attribute \src "libresoc.v:180964.3-180984.6" + wire width 4 $0\core_wen[3:0] + attribute \src "libresoc.v:181056.3-181162.6" + wire $0\core_xer_out$next[0:0]$13114 + attribute \src "libresoc.v:180179.3-180180.41" + wire $0\core_xer_out[0:0] + attribute \src "libresoc.v:180261.3-180262.43" + wire $0\cu_st__rel_o_dly[0:0] + attribute \src "libresoc.v:180708.3-180716.6" + wire $0\d_cr_delay$next[0:0]$13017 + attribute \src "libresoc.v:180193.3-180194.37" + wire $0\d_cr_delay[0:0] + attribute \src "libresoc.v:180669.3-180677.6" + wire $0\d_reg_delay$next[0:0]$13011 + attribute \src "libresoc.v:180215.3-180216.39" + wire $0\d_reg_delay[0:0] + attribute \src "libresoc.v:180747.3-180755.6" + wire $0\d_xer_delay$next[0:0]$13023 + attribute \src "libresoc.v:180171.3-180172.39" + wire $0\d_xer_delay[0:0] + attribute \src "libresoc.v:181456.3-181474.6" + wire $0\dbg_core_stopped_i[0:0] + attribute \src "libresoc.v:180727.3-180736.6" + wire $0\dbg_d_cr_ack[0:0] + attribute \src "libresoc.v:180717.3-180726.6" + wire width 64 $0\dbg_d_cr_data[63:0] + attribute \src "libresoc.v:180688.3-180697.6" + wire $0\dbg_d_gpr_ack[0:0] + attribute \src "libresoc.v:180678.3-180687.6" + wire width 64 $0\dbg_d_gpr_data[63:0] + attribute \src "libresoc.v:180766.3-180775.6" + wire $0\dbg_d_xer_ack[0:0] + attribute \src "libresoc.v:180756.3-180765.6" + wire width 64 $0\dbg_d_xer_data[63:0] + attribute \src "libresoc.v:180620.3-180628.6" + wire width 4 $0\dbg_dmi_addr_i$next[3:0]$13002 + attribute \src "libresoc.v:180277.3-180278.45" + wire width 4 $0\dbg_dmi_addr_i[3:0] + attribute \src "libresoc.v:181022.3-181030.6" + wire width 64 $0\dbg_dmi_din$next[63:0]$13056 + attribute \src "libresoc.v:180271.3-180272.39" + wire width 64 $0\dbg_dmi_din[63:0] + attribute \src "libresoc.v:180629.3-180637.6" + wire $0\dbg_dmi_req_i$next[0:0]$13005 + attribute \src "libresoc.v:180275.3-180276.43" + wire $0\dbg_dmi_req_i[0:0] + attribute \src "libresoc.v:180917.3-180925.6" + wire $0\dbg_dmi_we_i$next[0:0]$13045 + attribute \src "libresoc.v:180273.3-180274.41" + wire $0\dbg_dmi_we_i[0:0] + attribute \src "libresoc.v:180890.3-180905.6" + wire width 64 $0\dec2_cur_dec$next[63:0]$13040 + attribute \src "libresoc.v:180127.3-180128.41" + wire width 64 $0\dec2_cur_dec[63:0] + attribute \src "libresoc.v:181181.3-181189.6" + wire $0\dec2_cur_eint$next[0:0]$13294 + attribute \src "libresoc.v:180265.3-180266.43" + wire $0\dec2_cur_eint[0:0] + attribute \src "libresoc.v:181475.3-181495.6" + wire width 64 $0\dec2_cur_msr$next[63:0]$13335 + attribute \src "libresoc.v:180131.3-180132.41" + wire width 64 $0\dec2_cur_msr[63:0] + attribute \src "libresoc.v:181330.3-181350.6" + wire width 64 $0\dec2_cur_pc$next[63:0]$13312 + attribute \src "libresoc.v:180137.3-180138.39" + wire width 64 $0\dec2_cur_pc[63:0] + attribute \src "libresoc.v:181496.3-181514.6" + wire width 32 $0\dec2_raw_opcode_in[31:0] + attribute \src "libresoc.v:181427.3-181436.6" + wire width 2 $0\delay$next[1:0]$13330 + attribute \src "libresoc.v:180263.3-180264.27" + wire width 2 $0\delay[1:0] + attribute \src "libresoc.v:180806.3-180833.6" + wire width 2 $0\fsm_state$117$next[1:0]$13030 + attribute \src "libresoc.v:180149.3-180150.45" + wire width 2 $0\fsm_state$117[1:0]$12932 + attribute \src "libresoc.v:179708.13-179708.35" + wire width 2 $0\fsm_state$117[1:0]$13439 + attribute \src "libresoc.v:181381.3-181426.6" + wire width 2 $0\fsm_state$next[1:0]$13323 + attribute \src "libresoc.v:180133.3-180134.35" + wire width 2 $0\fsm_state[1:0] + attribute \src "libresoc.v:181547.3-181570.6" + wire width 32 $0\ilatch$next[31:0]$13358 + attribute \src "libresoc.v:180237.3-180238.29" + wire width 32 $0\ilatch[31:0] + attribute \src "libresoc.v:181264.3-181279.6" + wire width 48 $0\imem_a_pc_i[47:0] + attribute \src "libresoc.v:181280.3-181304.6" + wire $0\imem_a_valid_i[0:0] + attribute \src "libresoc.v:181305.3-181329.6" + wire $0\imem_f_valid_i[0:0] + attribute \src "libresoc.v:178436.7-178436.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:181163.3-181171.6" + wire $0\jtag_dmi0_ack_o$next[0:0]$13288 + attribute \src "libresoc.v:180269.3-180270.47" + wire $0\jtag_dmi0_ack_o[0:0] + attribute \src "libresoc.v:181172.3-181180.6" + wire width 64 $0\jtag_dmi0_dout$next[63:0]$13291 + attribute \src "libresoc.v:180267.3-180268.45" + wire width 64 $0\jtag_dmi0_dout[63:0] + attribute \src "libresoc.v:181351.3-181380.6" + wire $0\msr_read$next[0:0]$13317 + attribute \src "libresoc.v:180135.3-180136.33" + wire $0\msr_read[0:0] + attribute \src "libresoc.v:180834.3-180844.6" + wire width 64 $0\new_dec[63:0] + attribute \src "libresoc.v:180906.3-180916.6" + wire width 64 $0\new_tb[63:0] + attribute \src "libresoc.v:180935.3-180950.6" + wire width 64 $0\pc[63:0] + attribute \src "libresoc.v:181031.3-181055.6" + wire $0\pc_changed$next[0:0]$13059 + attribute \src "libresoc.v:180255.3-180256.37" + wire $0\pc_changed[0:0] + attribute \src "libresoc.v:180926.3-180934.6" + wire $0\pc_ok_delay$next[0:0]$13048 + attribute \src "libresoc.v:180257.3-180258.39" + wire $0\pc_ok_delay[0:0] + attribute \src "libresoc.v:181056.3-181162.6" + wire width 8 $1\core_asmcode$next[7:0]$13115 + attribute \src "libresoc.v:178570.13-178570.33" + wire width 8 $1\core_asmcode[7:0] + attribute \src "libresoc.v:181227.3-181263.6" + wire $1\core_bigendian_i$3$next[0:0]$13304 + attribute \src "libresoc.v:180951.3-180963.6" + wire width 4 $1\core_cia__ren[3:0] + attribute \src "libresoc.v:181056.3-181162.6" + wire width 64 $1\core_core_core_cia$next[63:0]$13116 + attribute \src "libresoc.v:178584.14-178584.55" + wire width 64 $1\core_core_core_cia[63:0] + attribute \src "libresoc.v:181056.3-181162.6" + wire width 8 $1\core_core_core_cr_rd$next[7:0]$13117 + attribute \src "libresoc.v:178588.13-178588.41" + wire width 8 $1\core_core_core_cr_rd[7:0] + attribute \src "libresoc.v:181056.3-181162.6" + wire $1\core_core_core_cr_rd_ok$next[0:0]$13118 + attribute \src "libresoc.v:178592.7-178592.37" + wire $1\core_core_core_cr_rd_ok[0:0] + attribute \src "libresoc.v:181056.3-181162.6" + wire width 8 $1\core_core_core_cr_wr$next[7:0]$13119 + attribute \src "libresoc.v:178596.13-178596.41" + wire width 8 $1\core_core_core_cr_wr[7:0] + attribute \src "libresoc.v:181056.3-181162.6" + wire width 12 $1\core_core_core_fn_unit$next[11:0]$13120 + attribute \src "libresoc.v:178613.14-178613.46" + wire width 12 $1\core_core_core_fn_unit[11:0] + attribute \src "libresoc.v:181056.3-181162.6" + wire width 2 $1\core_core_core_input_carry$next[1:0]$13121 + attribute \src "libresoc.v:178621.13-178621.46" + wire width 2 $1\core_core_core_input_carry[1:0] + attribute \src "libresoc.v:181056.3-181162.6" + wire width 32 $1\core_core_core_insn$next[31:0]$13122 + attribute \src "libresoc.v:178625.14-178625.41" + wire width 32 $1\core_core_core_insn[31:0] + attribute \src "libresoc.v:181056.3-181162.6" + wire width 7 $1\core_core_core_insn_type$next[6:0]$13123 + attribute \src "libresoc.v:178703.13-178703.45" + wire width 7 $1\core_core_core_insn_type[6:0] + attribute \src "libresoc.v:181056.3-181162.6" + wire $1\core_core_core_is_32bit$next[0:0]$13124 + attribute \src "libresoc.v:178707.7-178707.37" + wire $1\core_core_core_is_32bit[0:0] + attribute \src "libresoc.v:181056.3-181162.6" + wire width 64 $1\core_core_core_msr$next[63:0]$13125 + attribute \src "libresoc.v:178711.14-178711.55" + wire width 64 $1\core_core_core_msr[63:0] + attribute \src "libresoc.v:181056.3-181162.6" + wire $1\core_core_core_oe$next[0:0]$13126 + attribute \src "libresoc.v:178715.7-178715.31" + wire $1\core_core_core_oe[0:0] + attribute \src "libresoc.v:181056.3-181162.6" + wire $1\core_core_core_oe_ok$next[0:0]$13127 + attribute \src "libresoc.v:178719.7-178719.34" + wire $1\core_core_core_oe_ok[0:0] + attribute \src "libresoc.v:181056.3-181162.6" + wire $1\core_core_core_rc$next[0:0]$13128 + attribute \src "libresoc.v:178723.7-178723.31" + wire $1\core_core_core_rc[0:0] + attribute \src "libresoc.v:181056.3-181162.6" + wire $1\core_core_core_rc_ok$next[0:0]$13129 + attribute \src "libresoc.v:178727.7-178727.34" + wire $1\core_core_core_rc_ok[0:0] + attribute \src "libresoc.v:181056.3-181162.6" + wire width 13 $1\core_core_core_trapaddr$next[12:0]$13130 + attribute \src "libresoc.v:178731.14-178731.48" + wire width 13 $1\core_core_core_trapaddr[12:0] + attribute \src "libresoc.v:181056.3-181162.6" + wire width 7 $1\core_core_core_traptype$next[6:0]$13131 + attribute \src "libresoc.v:178735.13-178735.44" + wire width 7 $1\core_core_core_traptype[6:0] + attribute \src "libresoc.v:181056.3-181162.6" + wire width 3 $1\core_core_cr_in1$next[2:0]$13132 + attribute \src "libresoc.v:178739.13-178739.36" + wire width 3 $1\core_core_cr_in1[2:0] + attribute \src "libresoc.v:181056.3-181162.6" + wire $1\core_core_cr_in1_ok$next[0:0]$13133 + attribute \src "libresoc.v:178743.7-178743.33" + wire $1\core_core_cr_in1_ok[0:0] + attribute \src "libresoc.v:181056.3-181162.6" + wire width 3 $1\core_core_cr_in2$1$next[2:0]$13134 + attribute \src "libresoc.v:181056.3-181162.6" + wire width 3 $1\core_core_cr_in2$next[2:0]$13135 + attribute \src "libresoc.v:178747.13-178747.36" + wire width 3 $1\core_core_cr_in2[2:0] + attribute \src "libresoc.v:181056.3-181162.6" + wire $1\core_core_cr_in2_ok$2$next[0:0]$13136 + attribute \src "libresoc.v:181056.3-181162.6" + wire $1\core_core_cr_in2_ok$next[0:0]$13137 + attribute \src "libresoc.v:178755.7-178755.33" + wire $1\core_core_cr_in2_ok[0:0] + attribute \src "libresoc.v:181056.3-181162.6" + wire width 3 $1\core_core_cr_out$next[2:0]$13138 + attribute \src "libresoc.v:178763.13-178763.36" + wire width 3 $1\core_core_cr_out[2:0] + attribute \src "libresoc.v:181056.3-181162.6" + wire $1\core_core_cr_wr_ok$next[0:0]$13139 + attribute \src "libresoc.v:178767.7-178767.32" + wire $1\core_core_cr_wr_ok[0:0] + attribute \src "libresoc.v:181056.3-181162.6" + wire width 5 $1\core_core_ea$next[4:0]$13140 + attribute \src "libresoc.v:178771.13-178771.33" + wire width 5 $1\core_core_ea[4:0] + attribute \src "libresoc.v:181056.3-181162.6" + wire width 3 $1\core_core_fast1$next[2:0]$13141 + attribute \src "libresoc.v:178775.13-178775.35" + wire width 3 $1\core_core_fast1[2:0] + attribute \src "libresoc.v:181056.3-181162.6" + wire $1\core_core_fast1_ok$next[0:0]$13142 + attribute \src "libresoc.v:178779.7-178779.32" + wire $1\core_core_fast1_ok[0:0] + attribute \src "libresoc.v:181056.3-181162.6" + wire width 3 $1\core_core_fast2$next[2:0]$13143 + attribute \src "libresoc.v:178783.13-178783.35" + wire width 3 $1\core_core_fast2[2:0] + attribute \src "libresoc.v:181056.3-181162.6" + wire $1\core_core_fast2_ok$next[0:0]$13144 + attribute \src "libresoc.v:178787.7-178787.32" + wire $1\core_core_fast2_ok[0:0] + attribute \src "libresoc.v:181056.3-181162.6" + wire width 3 $1\core_core_fasto1$next[2:0]$13145 + attribute \src "libresoc.v:178791.13-178791.36" + wire width 3 $1\core_core_fasto1[2:0] + attribute \src "libresoc.v:181056.3-181162.6" + wire width 3 $1\core_core_fasto2$next[2:0]$13146 + attribute \src "libresoc.v:178795.13-178795.36" + wire width 3 $1\core_core_fasto2[2:0] + attribute \src "libresoc.v:181056.3-181162.6" + wire $1\core_core_lk$next[0:0]$13147 + attribute \src "libresoc.v:178799.7-178799.26" + wire $1\core_core_lk[0:0] + attribute \src "libresoc.v:181515.3-181546.6" + wire width 64 $1\core_core_pc$next[63:0]$13345 + attribute \src "libresoc.v:178803.14-178803.49" + wire width 64 $1\core_core_pc[63:0] + attribute \src "libresoc.v:181056.3-181162.6" + wire width 5 $1\core_core_reg1$next[4:0]$13148 + attribute \src "libresoc.v:178807.13-178807.35" + wire width 5 $1\core_core_reg1[4:0] + attribute \src "libresoc.v:181056.3-181162.6" + wire $1\core_core_reg1_ok$next[0:0]$13149 + attribute \src "libresoc.v:178811.7-178811.31" + wire $1\core_core_reg1_ok[0:0] + attribute \src "libresoc.v:181056.3-181162.6" + wire width 5 $1\core_core_reg2$next[4:0]$13150 + attribute \src "libresoc.v:178815.13-178815.35" + wire width 5 $1\core_core_reg2[4:0] + attribute \src "libresoc.v:181056.3-181162.6" + wire $1\core_core_reg2_ok$next[0:0]$13151 + attribute \src "libresoc.v:178819.7-178819.31" + wire $1\core_core_reg2_ok[0:0] + attribute \src "libresoc.v:181056.3-181162.6" + wire width 5 $1\core_core_reg3$next[4:0]$13152 + attribute \src "libresoc.v:178823.13-178823.35" + wire width 5 $1\core_core_reg3[4:0] + attribute \src "libresoc.v:181056.3-181162.6" + wire $1\core_core_reg3_ok$next[0:0]$13153 + attribute \src "libresoc.v:178827.7-178827.31" + wire $1\core_core_reg3_ok[0:0] + attribute \src "libresoc.v:181056.3-181162.6" + wire width 5 $1\core_core_rego$next[4:0]$13154 + attribute \src "libresoc.v:178831.13-178831.35" + wire width 5 $1\core_core_rego[4:0] + attribute \src "libresoc.v:181056.3-181162.6" + wire width 10 $1\core_core_spr1$next[9:0]$13155 + attribute \src "libresoc.v:178948.13-178948.37" + wire width 10 $1\core_core_spr1[9:0] + attribute \src "libresoc.v:181056.3-181162.6" + wire $1\core_core_spr1_ok$next[0:0]$13156 + attribute \src "libresoc.v:178952.7-178952.31" + wire $1\core_core_spr1_ok[0:0] + attribute \src "libresoc.v:181056.3-181162.6" + wire width 10 $1\core_core_spro$next[9:0]$13157 + attribute \src "libresoc.v:179067.13-179067.37" + wire width 10 $1\core_core_spro[9:0] + attribute \src "libresoc.v:181056.3-181162.6" + wire width 3 $1\core_core_xer_in$next[2:0]$13158 + attribute \src "libresoc.v:179073.13-179073.36" + wire width 3 $1\core_core_xer_in[2:0] + attribute \src "libresoc.v:181056.3-181162.6" + wire $1\core_cr_out_ok$next[0:0]$13159 + attribute \src "libresoc.v:179081.7-179081.28" + wire $1\core_cr_out_ok[0:0] + attribute \src "libresoc.v:180985.3-181005.6" + wire width 64 $1\core_data_i[63:0] + attribute \src "libresoc.v:181515.3-181546.6" + wire width 64 $1\core_dec$next[63:0]$13346 + attribute \src "libresoc.v:179095.14-179095.45" + wire width 64 $1\core_dec[63:0] + attribute \src "libresoc.v:180649.3-180658.6" + wire width 5 $1\core_dmi__addr[4:0] + attribute \src "libresoc.v:180659.3-180668.6" + wire $1\core_dmi__ren[0:0] + attribute \src "libresoc.v:181056.3-181162.6" + wire $1\core_ea_ok$next[0:0]$13160 + attribute \src "libresoc.v:179105.7-179105.24" + wire $1\core_ea_ok[0:0] + attribute \src "libresoc.v:181515.3-181546.6" + wire $1\core_eint$next[0:0]$13347 + attribute \src "libresoc.v:179109.7-179109.23" + wire $1\core_eint[0:0] + attribute \src "libresoc.v:181056.3-181162.6" + wire $1\core_fasto1_ok$next[0:0]$13161 + attribute \src "libresoc.v:179113.7-179113.28" + wire $1\core_fasto1_ok[0:0] + attribute \src "libresoc.v:181056.3-181162.6" + wire $1\core_fasto2_ok$next[0:0]$13162 + attribute \src "libresoc.v:179117.7-179117.28" + wire $1\core_fasto2_ok[0:0] + attribute \src "libresoc.v:180698.3-180707.6" + wire width 8 $1\core_full_rd2__ren[7:0] + attribute \src "libresoc.v:180737.3-180746.6" + wire width 3 $1\core_full_rd__ren[2:0] + attribute \src "libresoc.v:180845.3-180859.6" + wire width 3 $1\core_issue__addr$4[2:0]$13036 + attribute \src "libresoc.v:180776.3-180790.6" + wire width 3 $1\core_issue__addr[2:0] + attribute \src "libresoc.v:180875.3-180889.6" + wire width 64 $1\core_issue__data_i[63:0] + attribute \src "libresoc.v:180791.3-180805.6" + wire $1\core_issue__ren[0:0] + attribute \src "libresoc.v:180860.3-180874.6" + wire $1\core_issue__wen[0:0] + attribute \src "libresoc.v:180638.3-180648.6" + wire $1\core_issue_i[0:0] + attribute \src "libresoc.v:181571.3-181590.6" + wire $1\core_ivalid_i[0:0] + attribute \src "libresoc.v:181515.3-181546.6" + wire width 64 $1\core_msr$next[63:0]$13348 + attribute \src "libresoc.v:179145.14-179145.45" + wire width 64 $1\core_msr[63:0] + attribute \src "libresoc.v:181006.3-181021.6" + wire width 4 $1\core_msr__ren[3:0] + attribute \src "libresoc.v:181190.3-181226.6" + wire width 32 $1\core_raw_insn_i$next[31:0]$13298 + attribute \src "libresoc.v:179153.14-179153.37" + wire width 32 $1\core_raw_insn_i[31:0] + attribute \src "libresoc.v:181056.3-181162.6" + wire $1\core_rego_ok$next[0:0]$13163 + attribute \src "libresoc.v:179157.7-179157.26" + wire $1\core_rego_ok[0:0] + attribute \src "libresoc.v:181056.3-181162.6" + wire $1\core_spro_ok$next[0:0]$13164 + attribute \src "libresoc.v:179161.7-179161.26" + wire $1\core_spro_ok[0:0] + attribute \src "libresoc.v:181437.3-181455.6" + wire $1\core_stopped_i[0:0] + attribute \src "libresoc.v:180964.3-180984.6" + wire width 4 $1\core_wen[3:0] + attribute \src "libresoc.v:181056.3-181162.6" + wire $1\core_xer_out$next[0:0]$13165 + attribute \src "libresoc.v:179171.7-179171.26" + wire $1\core_xer_out[0:0] + attribute \src "libresoc.v:179175.7-179175.30" + wire $1\cu_st__rel_o_dly[0:0] + attribute \src "libresoc.v:180708.3-180716.6" + wire $1\d_cr_delay$next[0:0]$13018 + attribute \src "libresoc.v:179181.7-179181.24" + wire $1\d_cr_delay[0:0] + attribute \src "libresoc.v:180669.3-180677.6" + wire $1\d_reg_delay$next[0:0]$13012 + attribute \src "libresoc.v:179185.7-179185.25" + wire $1\d_reg_delay[0:0] + attribute \src "libresoc.v:180747.3-180755.6" + wire $1\d_xer_delay$next[0:0]$13024 + attribute \src "libresoc.v:179189.7-179189.25" + wire $1\d_xer_delay[0:0] + attribute \src "libresoc.v:181456.3-181474.6" + wire $1\dbg_core_stopped_i[0:0] + attribute \src "libresoc.v:180727.3-180736.6" + wire $1\dbg_d_cr_ack[0:0] + attribute \src "libresoc.v:180717.3-180726.6" + wire width 64 $1\dbg_d_cr_data[63:0] + attribute \src "libresoc.v:180688.3-180697.6" + wire $1\dbg_d_gpr_ack[0:0] + attribute \src "libresoc.v:180678.3-180687.6" + wire width 64 $1\dbg_d_gpr_data[63:0] + attribute \src "libresoc.v:180766.3-180775.6" + wire $1\dbg_d_xer_ack[0:0] + attribute \src "libresoc.v:180756.3-180765.6" + wire width 64 $1\dbg_d_xer_data[63:0] + attribute \src "libresoc.v:180620.3-180628.6" + wire width 4 $1\dbg_dmi_addr_i$next[3:0]$13003 + attribute \src "libresoc.v:179225.13-179225.34" + wire width 4 $1\dbg_dmi_addr_i[3:0] + attribute \src "libresoc.v:181022.3-181030.6" + wire width 64 $1\dbg_dmi_din$next[63:0]$13057 + attribute \src "libresoc.v:179229.14-179229.48" + wire width 64 $1\dbg_dmi_din[63:0] + attribute \src "libresoc.v:180629.3-180637.6" + wire $1\dbg_dmi_req_i$next[0:0]$13006 + attribute \src "libresoc.v:179235.7-179235.27" + wire $1\dbg_dmi_req_i[0:0] + attribute \src "libresoc.v:180917.3-180925.6" + wire $1\dbg_dmi_we_i$next[0:0]$13046 + attribute \src "libresoc.v:179239.7-179239.26" + wire $1\dbg_dmi_we_i[0:0] + attribute \src "libresoc.v:180890.3-180905.6" + wire width 64 $1\dec2_cur_dec$next[63:0]$13041 + attribute \src "libresoc.v:179297.14-179297.49" + wire width 64 $1\dec2_cur_dec[63:0] + attribute \src "libresoc.v:181181.3-181189.6" + wire $1\dec2_cur_eint$next[0:0]$13295 + attribute \src "libresoc.v:179301.7-179301.27" + wire $1\dec2_cur_eint[0:0] + attribute \src "libresoc.v:181475.3-181495.6" + wire width 64 $1\dec2_cur_msr$next[63:0]$13336 + attribute \src "libresoc.v:179305.14-179305.49" + wire width 64 $1\dec2_cur_msr[63:0] + attribute \src "libresoc.v:181330.3-181350.6" + wire width 64 $1\dec2_cur_pc$next[63:0]$13313 + attribute \src "libresoc.v:179309.14-179309.48" + wire width 64 $1\dec2_cur_pc[63:0] + attribute \src "libresoc.v:181496.3-181514.6" + wire width 32 $1\dec2_raw_opcode_in[31:0] + attribute \src "libresoc.v:181427.3-181436.6" + wire width 2 $1\delay$next[1:0]$13331 + attribute \src "libresoc.v:179702.13-179702.25" + wire width 2 $1\delay[1:0] + attribute \src "libresoc.v:180806.3-180833.6" + wire width 2 $1\fsm_state$117$next[1:0]$13031 + attribute \src "libresoc.v:181381.3-181426.6" + wire width 2 $1\fsm_state$next[1:0]$13324 + attribute \src "libresoc.v:179706.13-179706.29" + wire width 2 $1\fsm_state[1:0] + attribute \src "libresoc.v:181547.3-181570.6" + wire width 32 $1\ilatch$next[31:0]$13359 + attribute \src "libresoc.v:179972.14-179972.28" + wire width 32 $1\ilatch[31:0] + attribute \src "libresoc.v:181264.3-181279.6" + wire width 48 $1\imem_a_pc_i[47:0] + attribute \src "libresoc.v:181280.3-181304.6" + wire $1\imem_a_valid_i[0:0] + attribute \src "libresoc.v:181305.3-181329.6" + wire $1\imem_f_valid_i[0:0] + attribute \src "libresoc.v:181163.3-181171.6" + wire $1\jtag_dmi0_ack_o$next[0:0]$13289 + attribute \src "libresoc.v:179988.7-179988.29" + wire $1\jtag_dmi0_ack_o[0:0] + attribute \src "libresoc.v:181172.3-181180.6" + wire width 64 $1\jtag_dmi0_dout$next[63:0]$13292 + attribute \src "libresoc.v:179996.14-179996.51" + wire width 64 $1\jtag_dmi0_dout[63:0] + attribute \src "libresoc.v:181351.3-181380.6" + wire $1\msr_read$next[0:0]$13318 + attribute \src "libresoc.v:180024.7-180024.22" + wire $1\msr_read[0:0] + attribute \src "libresoc.v:180834.3-180844.6" + wire width 64 $1\new_dec[63:0] + attribute \src "libresoc.v:180906.3-180916.6" + wire width 64 $1\new_tb[63:0] + attribute \src "libresoc.v:180935.3-180950.6" + wire width 64 $1\pc[63:0] + attribute \src "libresoc.v:181031.3-181055.6" + wire $1\pc_changed$next[0:0]$13060 + attribute \src "libresoc.v:180036.7-180036.24" + wire $1\pc_changed[0:0] + attribute \src "libresoc.v:180926.3-180934.6" + wire $1\pc_ok_delay$next[0:0]$13049 + attribute \src "libresoc.v:180046.7-180046.25" + wire $1\pc_ok_delay[0:0] + attribute \src "libresoc.v:181056.3-181162.6" + wire width 8 $2\core_asmcode$next[7:0]$13166 + attribute \src "libresoc.v:181227.3-181263.6" + wire $2\core_bigendian_i$3$next[0:0]$13305 + attribute \src "libresoc.v:181056.3-181162.6" + wire width 64 $2\core_core_core_cia$next[63:0]$13167 + attribute \src "libresoc.v:181056.3-181162.6" + wire width 8 $2\core_core_core_cr_rd$next[7:0]$13168 + attribute \src "libresoc.v:181056.3-181162.6" + wire $2\core_core_core_cr_rd_ok$next[0:0]$13169 + attribute \src "libresoc.v:181056.3-181162.6" + wire width 8 $2\core_core_core_cr_wr$next[7:0]$13170 + attribute \src "libresoc.v:181056.3-181162.6" + wire width 12 $2\core_core_core_fn_unit$next[11:0]$13171 + attribute \src "libresoc.v:181056.3-181162.6" + wire width 2 $2\core_core_core_input_carry$next[1:0]$13172 + attribute \src "libresoc.v:181056.3-181162.6" + wire width 32 $2\core_core_core_insn$next[31:0]$13173 + attribute \src "libresoc.v:181056.3-181162.6" + wire width 7 $2\core_core_core_insn_type$next[6:0]$13174 + attribute \src "libresoc.v:181056.3-181162.6" + wire $2\core_core_core_is_32bit$next[0:0]$13175 + attribute \src "libresoc.v:181056.3-181162.6" + wire width 64 $2\core_core_core_msr$next[63:0]$13176 + attribute \src "libresoc.v:181056.3-181162.6" + wire $2\core_core_core_oe$next[0:0]$13177 + attribute \src "libresoc.v:181056.3-181162.6" + wire $2\core_core_core_oe_ok$next[0:0]$13178 + attribute \src "libresoc.v:181056.3-181162.6" + wire $2\core_core_core_rc$next[0:0]$13179 + attribute \src "libresoc.v:181056.3-181162.6" + wire $2\core_core_core_rc_ok$next[0:0]$13180 + attribute \src "libresoc.v:181056.3-181162.6" + wire width 13 $2\core_core_core_trapaddr$next[12:0]$13181 + attribute \src "libresoc.v:181056.3-181162.6" + wire width 7 $2\core_core_core_traptype$next[6:0]$13182 + attribute \src "libresoc.v:181056.3-181162.6" + wire width 3 $2\core_core_cr_in1$next[2:0]$13183 + attribute \src "libresoc.v:181056.3-181162.6" + wire $2\core_core_cr_in1_ok$next[0:0]$13184 + attribute \src "libresoc.v:181056.3-181162.6" + wire width 3 $2\core_core_cr_in2$1$next[2:0]$13185 + attribute \src "libresoc.v:181056.3-181162.6" + wire width 3 $2\core_core_cr_in2$next[2:0]$13186 + attribute \src "libresoc.v:181056.3-181162.6" + wire $2\core_core_cr_in2_ok$2$next[0:0]$13187 + attribute \src "libresoc.v:181056.3-181162.6" + wire $2\core_core_cr_in2_ok$next[0:0]$13188 + attribute \src "libresoc.v:181056.3-181162.6" + wire width 3 $2\core_core_cr_out$next[2:0]$13189 + attribute \src "libresoc.v:181056.3-181162.6" + wire $2\core_core_cr_wr_ok$next[0:0]$13190 + attribute \src "libresoc.v:181056.3-181162.6" + wire width 5 $2\core_core_ea$next[4:0]$13191 + attribute \src "libresoc.v:181056.3-181162.6" + wire width 3 $2\core_core_fast1$next[2:0]$13192 + attribute \src "libresoc.v:181056.3-181162.6" + wire $2\core_core_fast1_ok$next[0:0]$13193 + attribute \src "libresoc.v:181056.3-181162.6" + wire width 3 $2\core_core_fast2$next[2:0]$13194 + attribute \src "libresoc.v:181056.3-181162.6" + wire $2\core_core_fast2_ok$next[0:0]$13195 + attribute \src "libresoc.v:181056.3-181162.6" + wire width 3 $2\core_core_fasto1$next[2:0]$13196 + attribute \src "libresoc.v:181056.3-181162.6" + wire width 3 $2\core_core_fasto2$next[2:0]$13197 + attribute \src "libresoc.v:181056.3-181162.6" + wire $2\core_core_lk$next[0:0]$13198 + attribute \src "libresoc.v:181515.3-181546.6" + wire width 64 $2\core_core_pc$next[63:0]$13349 + attribute \src "libresoc.v:181056.3-181162.6" + wire width 5 $2\core_core_reg1$next[4:0]$13199 + attribute \src "libresoc.v:181056.3-181162.6" + wire $2\core_core_reg1_ok$next[0:0]$13200 + attribute \src "libresoc.v:181056.3-181162.6" + wire width 5 $2\core_core_reg2$next[4:0]$13201 + attribute \src "libresoc.v:181056.3-181162.6" + wire $2\core_core_reg2_ok$next[0:0]$13202 + attribute \src "libresoc.v:181056.3-181162.6" + wire width 5 $2\core_core_reg3$next[4:0]$13203 + attribute \src "libresoc.v:181056.3-181162.6" + wire $2\core_core_reg3_ok$next[0:0]$13204 + attribute \src "libresoc.v:181056.3-181162.6" + wire width 5 $2\core_core_rego$next[4:0]$13205 + attribute \src "libresoc.v:181056.3-181162.6" + wire width 10 $2\core_core_spr1$next[9:0]$13206 + attribute \src "libresoc.v:181056.3-181162.6" + wire $2\core_core_spr1_ok$next[0:0]$13207 + attribute \src "libresoc.v:181056.3-181162.6" + wire width 10 $2\core_core_spro$next[9:0]$13208 + attribute \src "libresoc.v:181056.3-181162.6" + wire width 3 $2\core_core_xer_in$next[2:0]$13209 + attribute \src "libresoc.v:181056.3-181162.6" + wire $2\core_cr_out_ok$next[0:0]$13210 + attribute \src "libresoc.v:180985.3-181005.6" + wire width 64 $2\core_data_i[63:0] + attribute \src "libresoc.v:181515.3-181546.6" + wire width 64 $2\core_dec$next[63:0]$13350 + attribute \src "libresoc.v:181056.3-181162.6" + wire $2\core_ea_ok$next[0:0]$13211 + attribute \src "libresoc.v:181515.3-181546.6" + wire $2\core_eint$next[0:0]$13351 + attribute \src "libresoc.v:181056.3-181162.6" + wire $2\core_fasto1_ok$next[0:0]$13212 + attribute \src "libresoc.v:181056.3-181162.6" + wire $2\core_fasto2_ok$next[0:0]$13213 + attribute \src "libresoc.v:181571.3-181590.6" + wire $2\core_ivalid_i[0:0] + attribute \src "libresoc.v:181515.3-181546.6" + wire width 64 $2\core_msr$next[63:0]$13352 + attribute \src "libresoc.v:181006.3-181021.6" + wire width 4 $2\core_msr__ren[3:0] + attribute \src "libresoc.v:181190.3-181226.6" + wire width 32 $2\core_raw_insn_i$next[31:0]$13299 + attribute \src "libresoc.v:181056.3-181162.6" + wire $2\core_rego_ok$next[0:0]$13214 + attribute \src "libresoc.v:181056.3-181162.6" + wire $2\core_spro_ok$next[0:0]$13215 + attribute \src "libresoc.v:181437.3-181455.6" + wire $2\core_stopped_i[0:0] + attribute \src "libresoc.v:180964.3-180984.6" + wire width 4 $2\core_wen[3:0] + attribute \src "libresoc.v:181056.3-181162.6" + wire $2\core_xer_out$next[0:0]$13216 + attribute \src "libresoc.v:181456.3-181474.6" + wire $2\dbg_core_stopped_i[0:0] + attribute \src "libresoc.v:180890.3-180905.6" + wire width 64 $2\dec2_cur_dec$next[63:0]$13042 + attribute \src "libresoc.v:181475.3-181495.6" + wire width 64 $2\dec2_cur_msr$next[63:0]$13337 + attribute \src "libresoc.v:181330.3-181350.6" + wire width 64 $2\dec2_cur_pc$next[63:0]$13314 + attribute \src "libresoc.v:181496.3-181514.6" + wire width 32 $2\dec2_raw_opcode_in[31:0] + attribute \src "libresoc.v:180806.3-180833.6" + wire width 2 $2\fsm_state$117$next[1:0]$13032 + attribute \src "libresoc.v:181381.3-181426.6" + wire width 2 $2\fsm_state$next[1:0]$13325 + attribute \src "libresoc.v:181547.3-181570.6" + wire width 32 $2\ilatch$next[31:0]$13360 + attribute \src "libresoc.v:181264.3-181279.6" + wire width 48 $2\imem_a_pc_i[47:0] + attribute \src "libresoc.v:181280.3-181304.6" + wire $2\imem_a_valid_i[0:0] + attribute \src "libresoc.v:181305.3-181329.6" + wire $2\imem_f_valid_i[0:0] + attribute \src "libresoc.v:181351.3-181380.6" + wire $2\msr_read$next[0:0]$13319 + attribute \src "libresoc.v:180935.3-180950.6" + wire width 64 $2\pc[63:0] + attribute \src "libresoc.v:181031.3-181055.6" + wire $2\pc_changed$next[0:0]$13061 + attribute \src "libresoc.v:181056.3-181162.6" + wire width 8 $3\core_asmcode$next[7:0]$13217 + attribute \src "libresoc.v:181227.3-181263.6" + wire $3\core_bigendian_i$3$next[0:0]$13306 + attribute \src "libresoc.v:181056.3-181162.6" + wire width 64 $3\core_core_core_cia$next[63:0]$13218 + attribute \src "libresoc.v:181056.3-181162.6" + wire width 8 $3\core_core_core_cr_rd$next[7:0]$13219 + attribute \src "libresoc.v:181056.3-181162.6" + wire $3\core_core_core_cr_rd_ok$next[0:0]$13220 + attribute \src "libresoc.v:181056.3-181162.6" + wire width 8 $3\core_core_core_cr_wr$next[7:0]$13221 + attribute \src "libresoc.v:181056.3-181162.6" + wire width 12 $3\core_core_core_fn_unit$next[11:0]$13222 + attribute \src "libresoc.v:181056.3-181162.6" + wire width 2 $3\core_core_core_input_carry$next[1:0]$13223 + attribute \src "libresoc.v:181056.3-181162.6" + wire width 32 $3\core_core_core_insn$next[31:0]$13224 + attribute \src "libresoc.v:181056.3-181162.6" + wire width 7 $3\core_core_core_insn_type$next[6:0]$13225 + attribute \src "libresoc.v:181056.3-181162.6" + wire $3\core_core_core_is_32bit$next[0:0]$13226 + attribute \src "libresoc.v:181056.3-181162.6" + wire width 64 $3\core_core_core_msr$next[63:0]$13227 + attribute \src "libresoc.v:181056.3-181162.6" + wire $3\core_core_core_oe$next[0:0]$13228 + attribute \src "libresoc.v:181056.3-181162.6" + wire $3\core_core_core_oe_ok$next[0:0]$13229 + attribute \src "libresoc.v:181056.3-181162.6" + wire $3\core_core_core_rc$next[0:0]$13230 + attribute \src "libresoc.v:181056.3-181162.6" + wire $3\core_core_core_rc_ok$next[0:0]$13231 + attribute \src "libresoc.v:181056.3-181162.6" + wire width 13 $3\core_core_core_trapaddr$next[12:0]$13232 + attribute \src "libresoc.v:181056.3-181162.6" + wire width 7 $3\core_core_core_traptype$next[6:0]$13233 + attribute \src "libresoc.v:181056.3-181162.6" + wire width 3 $3\core_core_cr_in1$next[2:0]$13234 + attribute \src "libresoc.v:181056.3-181162.6" + wire $3\core_core_cr_in1_ok$next[0:0]$13235 + attribute \src "libresoc.v:181056.3-181162.6" + wire width 3 $3\core_core_cr_in2$1$next[2:0]$13236 + attribute \src "libresoc.v:181056.3-181162.6" + wire width 3 $3\core_core_cr_in2$next[2:0]$13237 + attribute \src "libresoc.v:181056.3-181162.6" + wire $3\core_core_cr_in2_ok$2$next[0:0]$13238 + attribute \src "libresoc.v:181056.3-181162.6" + wire $3\core_core_cr_in2_ok$next[0:0]$13239 + attribute \src "libresoc.v:181056.3-181162.6" + wire width 3 $3\core_core_cr_out$next[2:0]$13240 + attribute \src "libresoc.v:181056.3-181162.6" + wire $3\core_core_cr_wr_ok$next[0:0]$13241 + attribute \src "libresoc.v:181056.3-181162.6" + wire width 5 $3\core_core_ea$next[4:0]$13242 + attribute \src "libresoc.v:181056.3-181162.6" + wire width 3 $3\core_core_fast1$next[2:0]$13243 + attribute \src "libresoc.v:181056.3-181162.6" + wire $3\core_core_fast1_ok$next[0:0]$13244 + attribute \src "libresoc.v:181056.3-181162.6" + wire width 3 $3\core_core_fast2$next[2:0]$13245 + attribute \src "libresoc.v:181056.3-181162.6" + wire $3\core_core_fast2_ok$next[0:0]$13246 + attribute \src "libresoc.v:181056.3-181162.6" + wire width 3 $3\core_core_fasto1$next[2:0]$13247 + attribute \src "libresoc.v:181056.3-181162.6" + wire width 3 $3\core_core_fasto2$next[2:0]$13248 + attribute \src "libresoc.v:181056.3-181162.6" + wire $3\core_core_lk$next[0:0]$13249 + attribute \src "libresoc.v:181515.3-181546.6" + wire width 64 $3\core_core_pc$next[63:0]$13353 + attribute \src "libresoc.v:181056.3-181162.6" + wire width 5 $3\core_core_reg1$next[4:0]$13250 + attribute \src "libresoc.v:181056.3-181162.6" + wire $3\core_core_reg1_ok$next[0:0]$13251 + attribute \src "libresoc.v:181056.3-181162.6" + wire width 5 $3\core_core_reg2$next[4:0]$13252 + attribute \src "libresoc.v:181056.3-181162.6" + wire $3\core_core_reg2_ok$next[0:0]$13253 + attribute \src "libresoc.v:181056.3-181162.6" + wire width 5 $3\core_core_reg3$next[4:0]$13254 + attribute \src "libresoc.v:181056.3-181162.6" + wire $3\core_core_reg3_ok$next[0:0]$13255 + attribute \src "libresoc.v:181056.3-181162.6" + wire width 5 $3\core_core_rego$next[4:0]$13256 + attribute \src "libresoc.v:181056.3-181162.6" + wire width 10 $3\core_core_spr1$next[9:0]$13257 + attribute \src "libresoc.v:181056.3-181162.6" + wire $3\core_core_spr1_ok$next[0:0]$13258 + attribute \src "libresoc.v:181056.3-181162.6" + wire width 10 $3\core_core_spro$next[9:0]$13259 + attribute \src "libresoc.v:181056.3-181162.6" + wire width 3 $3\core_core_xer_in$next[2:0]$13260 + attribute \src "libresoc.v:181056.3-181162.6" + wire $3\core_cr_out_ok$next[0:0]$13261 + attribute \src "libresoc.v:180985.3-181005.6" + wire width 64 $3\core_data_i[63:0] + attribute \src "libresoc.v:181515.3-181546.6" + wire width 64 $3\core_dec$next[63:0]$13354 + attribute \src "libresoc.v:181056.3-181162.6" + wire $3\core_ea_ok$next[0:0]$13262 + attribute \src "libresoc.v:181515.3-181546.6" + wire $3\core_eint$next[0:0]$13355 + attribute \src "libresoc.v:181056.3-181162.6" + wire $3\core_fasto1_ok$next[0:0]$13263 + attribute \src "libresoc.v:181056.3-181162.6" + wire $3\core_fasto2_ok$next[0:0]$13264 + attribute \src "libresoc.v:181515.3-181546.6" + wire width 64 $3\core_msr$next[63:0]$13356 + attribute \src "libresoc.v:181190.3-181226.6" + wire width 32 $3\core_raw_insn_i$next[31:0]$13300 + attribute \src "libresoc.v:181056.3-181162.6" + wire $3\core_rego_ok$next[0:0]$13265 + attribute \src "libresoc.v:181056.3-181162.6" + wire $3\core_spro_ok$next[0:0]$13266 + attribute \src "libresoc.v:180964.3-180984.6" + wire width 4 $3\core_wen[3:0] + attribute \src "libresoc.v:181056.3-181162.6" + wire $3\core_xer_out$next[0:0]$13267 + attribute \src "libresoc.v:181475.3-181495.6" + wire width 64 $3\dec2_cur_msr$next[63:0]$13338 + attribute \src "libresoc.v:181330.3-181350.6" + wire width 64 $3\dec2_cur_pc$next[63:0]$13315 + attribute \src "libresoc.v:181381.3-181426.6" + wire width 2 $3\fsm_state$next[1:0]$13326 + attribute \src "libresoc.v:181547.3-181570.6" + wire width 32 $3\ilatch$next[31:0]$13361 + attribute \src "libresoc.v:181280.3-181304.6" + wire $3\imem_a_valid_i[0:0] + attribute \src "libresoc.v:181305.3-181329.6" + wire $3\imem_f_valid_i[0:0] + attribute \src "libresoc.v:181351.3-181380.6" + wire $3\msr_read$next[0:0]$13320 + attribute \src "libresoc.v:181031.3-181055.6" + wire $3\pc_changed$next[0:0]$13062 + attribute \src "libresoc.v:181227.3-181263.6" + wire $4\core_bigendian_i$3$next[0:0]$13307 + attribute \src "libresoc.v:181056.3-181162.6" + wire $4\core_core_core_cr_rd_ok$next[0:0]$13268 + attribute \src "libresoc.v:181056.3-181162.6" + wire $4\core_core_core_oe_ok$next[0:0]$13269 + attribute \src "libresoc.v:181056.3-181162.6" + wire $4\core_core_core_rc_ok$next[0:0]$13270 + attribute \src "libresoc.v:181056.3-181162.6" + wire $4\core_core_cr_in1_ok$next[0:0]$13271 + attribute \src "libresoc.v:181056.3-181162.6" + wire $4\core_core_cr_in2_ok$2$next[0:0]$13272 + attribute \src "libresoc.v:181056.3-181162.6" + wire $4\core_core_cr_in2_ok$next[0:0]$13273 + attribute \src "libresoc.v:181056.3-181162.6" + wire $4\core_core_cr_wr_ok$next[0:0]$13274 + attribute \src "libresoc.v:181056.3-181162.6" + wire $4\core_core_fast1_ok$next[0:0]$13275 + attribute \src "libresoc.v:181056.3-181162.6" + wire $4\core_core_fast2_ok$next[0:0]$13276 + attribute \src "libresoc.v:181056.3-181162.6" + wire $4\core_core_reg1_ok$next[0:0]$13277 + attribute \src "libresoc.v:181056.3-181162.6" + wire $4\core_core_reg2_ok$next[0:0]$13278 + attribute \src "libresoc.v:181056.3-181162.6" + wire $4\core_core_reg3_ok$next[0:0]$13279 + attribute \src "libresoc.v:181056.3-181162.6" + wire $4\core_core_spr1_ok$next[0:0]$13280 + attribute \src "libresoc.v:181056.3-181162.6" + wire $4\core_cr_out_ok$next[0:0]$13281 + attribute \src "libresoc.v:181056.3-181162.6" + wire $4\core_ea_ok$next[0:0]$13282 + attribute \src "libresoc.v:181056.3-181162.6" + wire $4\core_fasto1_ok$next[0:0]$13283 + attribute \src "libresoc.v:181056.3-181162.6" + wire $4\core_fasto2_ok$next[0:0]$13284 + attribute \src "libresoc.v:181190.3-181226.6" + wire width 32 $4\core_raw_insn_i$next[31:0]$13301 + attribute \src "libresoc.v:181056.3-181162.6" + wire $4\core_rego_ok$next[0:0]$13285 + attribute \src "libresoc.v:181056.3-181162.6" + wire $4\core_spro_ok$next[0:0]$13286 + attribute \src "libresoc.v:181381.3-181426.6" + wire width 2 $4\fsm_state$next[1:0]$13327 + attribute \src "libresoc.v:181351.3-181380.6" + wire $4\msr_read$next[0:0]$13321 + attribute \src "libresoc.v:181381.3-181426.6" + wire width 2 $5\fsm_state$next[1:0]$13328 + attribute \src "libresoc.v:180082.19-180082.115" + wire width 65 $add$libresoc.v:180082$12874_Y + attribute \src "libresoc.v:180087.18-180087.107" + wire width 65 $add$libresoc.v:180087$12879_Y + attribute \src "libresoc.v:180071.18-180071.101" + wire $and$libresoc.v:180071$12861_Y + attribute \src "libresoc.v:180086.18-180086.109" + wire $and$libresoc.v:180086$12878_Y + attribute \src "libresoc.v:180095.18-180095.101" + wire $and$libresoc.v:180095$12887_Y + attribute \src "libresoc.v:180096.18-180096.114" + wire width 4 $and$libresoc.v:180096$12888_Y + attribute \src "libresoc.v:180103.18-180103.101" + wire $and$libresoc.v:180103$12895_Y + attribute \src "libresoc.v:180106.18-180106.101" + wire $and$libresoc.v:180106$12898_Y + attribute \src "libresoc.v:180109.18-180109.101" + wire $and$libresoc.v:180109$12901_Y + attribute \src "libresoc.v:180112.18-180112.101" + wire $and$libresoc.v:180112$12904_Y + attribute \src "libresoc.v:180115.18-180115.101" + wire $and$libresoc.v:180115$12907_Y + attribute \src "libresoc.v:180120.18-180120.101" + wire $and$libresoc.v:180120$12912_Y + attribute \src "libresoc.v:180124.18-180124.101" + wire $and$libresoc.v:180124$12916_Y + attribute \src "libresoc.v:180079.19-180079.114" + wire width 64 $extend$libresoc.v:180079$12869_Y + attribute \src "libresoc.v:180080.19-180080.113" + wire width 64 $extend$libresoc.v:180080$12871_Y + attribute \src "libresoc.v:180073.19-180073.111" + wire width 7 $mul$libresoc.v:180073$12863_Y + attribute \src "libresoc.v:180075.19-180075.111" + wire width 7 $mul$libresoc.v:180075$12865_Y + attribute \src "libresoc.v:180078.19-180078.123" + wire $ne$libresoc.v:180078$12868_Y + attribute \src "libresoc.v:180084.18-180084.102" + wire $ne$libresoc.v:180084$12876_Y + attribute \src "libresoc.v:180116.17-180116.101" + wire $ne$libresoc.v:180116$12908_Y + attribute \src "libresoc.v:180072.19-180072.100" + wire $not$libresoc.v:180072$12862_Y + attribute \src "libresoc.v:180085.18-180085.103" + wire $not$libresoc.v:180085$12877_Y + attribute \src "libresoc.v:180088.18-180088.98" + wire $not$libresoc.v:180088$12880_Y + attribute \src "libresoc.v:180089.18-180089.106" + wire $not$libresoc.v:180089$12881_Y + attribute \src "libresoc.v:180090.18-180090.101" + wire $not$libresoc.v:180090$12882_Y + attribute \src "libresoc.v:180091.18-180091.106" + wire $not$libresoc.v:180091$12883_Y + attribute \src "libresoc.v:180092.18-180092.101" + wire $not$libresoc.v:180092$12884_Y + attribute \src "libresoc.v:180093.18-180093.106" + wire $not$libresoc.v:180093$12885_Y + attribute \src "libresoc.v:180094.18-180094.108" + wire $not$libresoc.v:180094$12886_Y + attribute \src "libresoc.v:180098.18-180098.106" + wire $not$libresoc.v:180098$12890_Y + attribute \src "libresoc.v:180099.18-180099.106" + wire $not$libresoc.v:180099$12891_Y + attribute \src "libresoc.v:180100.18-180100.106" + wire $not$libresoc.v:180100$12892_Y + attribute \src "libresoc.v:180101.18-180101.106" + wire $not$libresoc.v:180101$12893_Y + attribute \src "libresoc.v:180102.18-180102.108" + wire $not$libresoc.v:180102$12894_Y + attribute \src "libresoc.v:180104.18-180104.106" + wire $not$libresoc.v:180104$12896_Y + attribute \src "libresoc.v:180105.18-180105.108" + wire $not$libresoc.v:180105$12897_Y + attribute \src "libresoc.v:180107.18-180107.106" + wire $not$libresoc.v:180107$12899_Y + attribute \src "libresoc.v:180108.18-180108.108" + wire $not$libresoc.v:180108$12900_Y + attribute \src "libresoc.v:180110.18-180110.106" + wire $not$libresoc.v:180110$12902_Y + attribute \src "libresoc.v:180111.18-180111.108" + wire $not$libresoc.v:180111$12903_Y + attribute \src "libresoc.v:180113.18-180113.106" + wire $not$libresoc.v:180113$12905_Y + attribute \src "libresoc.v:180114.18-180114.108" + wire $not$libresoc.v:180114$12906_Y + attribute \src "libresoc.v:180117.18-180117.99" + wire $not$libresoc.v:180117$12909_Y + attribute \src "libresoc.v:180118.18-180118.106" + wire $not$libresoc.v:180118$12910_Y + attribute \src "libresoc.v:180119.18-180119.108" + wire $not$libresoc.v:180119$12911_Y + attribute \src "libresoc.v:180121.18-180121.106" + wire $not$libresoc.v:180121$12913_Y + attribute \src "libresoc.v:180122.18-180122.106" + wire $not$libresoc.v:180122$12914_Y + attribute \src "libresoc.v:180123.18-180123.108" + wire $not$libresoc.v:180123$12915_Y + attribute \src "libresoc.v:180125.18-180125.106" + wire $not$libresoc.v:180125$12917_Y + attribute \src "libresoc.v:180126.18-180126.108" + wire $not$libresoc.v:180126$12918_Y + attribute \src "libresoc.v:180083.18-180083.110" + wire $or$libresoc.v:180083$12875_Y + attribute \src "libresoc.v:180079.19-180079.114" + wire width 64 $pos$libresoc.v:180079$12870_Y + attribute \src "libresoc.v:180080.19-180080.113" + wire width 64 $pos$libresoc.v:180080$12872_Y + attribute \src "libresoc.v:180097.18-180097.91" + wire $reduce_or$libresoc.v:180097$12889_Y + attribute \src "libresoc.v:180074.19-180074.42" + wire width 64 $shr$libresoc.v:180074$12864_Y + attribute \src "libresoc.v:180077.19-180077.42" + wire width 64 $shr$libresoc.v:180077$12867_Y + attribute \src "libresoc.v:180076.18-180076.101" + wire width 3 $sub$libresoc.v:180076$12866_Y + attribute \src "libresoc.v:180081.19-180081.115" + wire width 65 $sub$libresoc.v:180081$12873_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:157" + wire width 3 \$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:255" + wire \$101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:268" + wire width 32 \$103 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609" + wire width 7 \$104 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:268" + wire width 32 \$107 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609" + wire width 7 \$108 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:287" + wire \$111 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \$113 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \$115 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:373" + wire width 65 \$118 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:373" + wire width 65 \$119 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:161" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:389" + wire width 65 \$121 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:389" + wire width 65 \$122 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:161" + wire \$14 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire \$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:181" + wire width 65 \$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:181" + wire width 65 \$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:186" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:291" + wire \$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:291" + wire \$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" + wire \$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" + wire \$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" + wire \$37 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + wire \$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289" + wire width 4 \$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:291" + wire \$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:291" + wire \$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:291" + wire \$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" + wire \$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" + wire \$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" + wire \$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" + wire \$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" + wire \$57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" + wire \$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" + wire \$61 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" + wire \$63 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" + wire \$65 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" + wire \$67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" + wire \$69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:156" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" + wire \$71 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" + wire \$73 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" + wire \$75 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" + wire \$77 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:255" + wire \$79 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" + wire \$81 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" + wire \$83 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" + wire \$85 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:291" + wire \$87 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" + wire \$89 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:157" + wire width 3 \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" + wire \$91 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" + wire \$93 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" + wire \$95 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" + wire \$97 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" + wire \$99 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:39" + wire input 11 \TAP_bus__tck + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:39" + wire input 9 \TAP_bus__tdi + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:39" + wire output 8 \TAP_bus__tdo + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:39" + wire input 10 \TAP_bus__tms + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:90" + wire output 5 \busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:151" + wire input 6 \clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:92" + wire width 8 \core_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:92" + wire width 8 \core_asmcode$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:89" + wire input 4 \core_bigendian_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:94" + wire \core_bigendian_i$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:94" + wire \core_bigendian_i$3$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \core_cia__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \core_cia__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:42" + wire width 64 \core_core_core_cia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:42" + wire width 64 \core_core_core_cia$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 8 \core_core_core_cr_rd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 8 \core_core_core_cr_rd$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \core_core_core_cr_rd_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \core_core_core_cr_rd_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 8 \core_core_core_cr_wr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 8 \core_core_core_cr_wr$next + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47" + wire width 12 \core_core_core_fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47" + wire width 12 \core_core_core_fn_unit$next + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:51" + wire width 2 \core_core_core_input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:51" + wire width 2 \core_core_core_input_carry$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:45" + wire width 32 \core_core_core_insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:45" + wire width 32 \core_core_core_insn$next + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:46" + wire width 7 \core_core_core_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:46" + wire width 7 \core_core_core_insn_type$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:56" + wire \core_core_core_is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:56" + wire \core_core_core_is_32bit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:41" + wire width 64 \core_core_core_msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:41" + wire width 64 \core_core_core_msr$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \core_core_core_oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \core_core_core_oe$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \core_core_core_oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \core_core_core_oe_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \core_core_core_rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \core_core_core_rc$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \core_core_core_rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \core_core_core_rc_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53" + wire width 13 \core_core_core_trapaddr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53" + wire width 13 \core_core_core_trapaddr$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:52" + wire width 7 \core_core_core_traptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:52" + wire width 7 \core_core_core_traptype$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \core_core_cr_in1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \core_core_cr_in1$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \core_core_cr_in1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \core_core_cr_in1_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \core_core_cr_in2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \core_core_cr_in2$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \core_core_cr_in2$1$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \core_core_cr_in2$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \core_core_cr_in2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \core_core_cr_in2_ok$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \core_core_cr_in2_ok$2$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \core_core_cr_in2_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \core_core_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \core_core_cr_out$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \core_core_cr_wr_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \core_core_cr_wr_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 \core_core_ea + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 \core_core_ea$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \core_core_fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \core_core_fast1$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \core_core_fast1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \core_core_fast1_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \core_core_fast2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \core_core_fast2$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \core_core_fast2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \core_core_fast2_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \core_core_fasto1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \core_core_fasto1$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \core_core_fasto2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \core_core_fasto2$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48" + wire \core_core_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48" + wire \core_core_lk$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:8" + wire width 64 \core_core_pc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:8" + wire width 64 \core_core_pc$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 \core_core_reg1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 \core_core_reg1$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \core_core_reg1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \core_core_reg1_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 \core_core_reg2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 \core_core_reg2$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \core_core_reg2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \core_core_reg2_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 \core_core_reg3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 \core_core_reg3$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \core_core_reg3_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \core_core_reg3_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 \core_core_rego + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 \core_core_rego$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:103" + wire \core_core_reset_i + attribute \enum_base_type "SPR" + attribute \enum_value_0000000001 "XER" + attribute \enum_value_0000000011 "DSCR" + attribute \enum_value_0000001000 "LR" + attribute \enum_value_0000001001 "CTR" + attribute \enum_value_0000001101 "AMR" + attribute \enum_value_0000010001 "DSCR_priv" + attribute \enum_value_0000010010 "DSISR" + attribute \enum_value_0000010011 "DAR" + attribute \enum_value_0000010110 "DEC" + attribute \enum_value_0000011010 "SRR0" + attribute \enum_value_0000011011 "SRR1" + attribute \enum_value_0000011100 "CFAR" + attribute \enum_value_0000011101 "AMR_priv" + attribute \enum_value_0000110000 "PIDR" + attribute \enum_value_0000111101 "IAMR" + attribute \enum_value_0010000000 "TFHAR" + attribute \enum_value_0010000001 "TFIAR" + attribute \enum_value_0010000010 "TEXASR" + attribute \enum_value_0010000011 "TEXASRU" + attribute \enum_value_0010001000 "CTRL" + attribute \enum_value_0010010000 "TIDR" + attribute \enum_value_0010011000 "CTRL_priv" + attribute \enum_value_0010011001 "FSCR" + attribute \enum_value_0010011101 "UAMOR" + attribute \enum_value_0010011110 "GSR" + attribute \enum_value_0010011111 "PSPB" + attribute \enum_value_0010110000 "DPDES" + attribute \enum_value_0010110100 "DAWR0" + attribute \enum_value_0010111010 "RPR" + attribute \enum_value_0010111011 "CIABR" + attribute \enum_value_0010111100 "DAWRX0" + attribute \enum_value_0010111110 "HFSCR" + attribute \enum_value_0100000000 "VRSAVE" + attribute \enum_value_0100000011 "SPRG3" + attribute \enum_value_0100001100 "TB" + attribute \enum_value_0100001101 "TBU" + attribute \enum_value_0100010000 "SPRG0_priv" + attribute \enum_value_0100010001 "SPRG1_priv" + attribute \enum_value_0100010010 "SPRG2_priv" + attribute \enum_value_0100010011 "SPRG3_priv" + attribute \enum_value_0100011011 "CIR" + attribute \enum_value_0100011100 "TBL" + attribute \enum_value_0100011101 "TBU_hypv" + attribute \enum_value_0100011110 "TBU40" + attribute \enum_value_0100011111 "PVR" + attribute \enum_value_0100110000 "HSPRG0" + attribute \enum_value_0100110001 "HSPRG1" + attribute \enum_value_0100110010 "HDSISR" + attribute \enum_value_0100110011 "HDAR" + attribute \enum_value_0100110100 "SPURR" + attribute \enum_value_0100110101 "PURR" + attribute \enum_value_0100110110 "HDEC" + attribute \enum_value_0100111001 "HRMOR" + attribute \enum_value_0100111010 "HSRR0" + attribute \enum_value_0100111011 "HSRR1" + attribute \enum_value_0100111110 "LPCR" + attribute \enum_value_0100111111 "LPIDR" + attribute \enum_value_0101010000 "HMER" + attribute \enum_value_0101010001 "HMEER" + attribute \enum_value_0101010010 "PCR" + attribute \enum_value_0101010011 "HEIR" + attribute \enum_value_0101011101 "AMOR" + attribute \enum_value_0110111110 "TIR" + attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1100000000 "SIER" + attribute \enum_value_1100000001 "MMCR2" + attribute \enum_value_1100000010 "MMCRA" + attribute \enum_value_1100000011 "PMC1" + attribute \enum_value_1100000100 "PMC2" + attribute \enum_value_1100000101 "PMC3" + attribute \enum_value_1100000110 "PMC4" + attribute \enum_value_1100000111 "PMC5" + attribute \enum_value_1100001000 "PMC6" + attribute \enum_value_1100001011 "MMCR0" + attribute \enum_value_1100001100 "SIAR" + attribute \enum_value_1100001101 "SDAR" + attribute \enum_value_1100001110 "MMCR1" + attribute \enum_value_1100010000 "SIER_priv" + attribute \enum_value_1100010001 "MMCR2_priv" + attribute \enum_value_1100010010 "MMCRA_priv" + attribute \enum_value_1100010011 "PMC1_priv" + attribute \enum_value_1100010100 "PMC2_priv" + attribute \enum_value_1100010101 "PMC3_priv" + attribute \enum_value_1100010110 "PMC4_priv" + attribute \enum_value_1100010111 "PMC5_priv" + attribute \enum_value_1100011000 "PMC6_priv" + attribute \enum_value_1100011011 "MMCR0_priv" + attribute \enum_value_1100011100 "SIAR_priv" + attribute \enum_value_1100011101 "SDAR_priv" + attribute \enum_value_1100011110 "MMCR1_priv" + attribute \enum_value_1100100000 "BESCRS" + attribute \enum_value_1100100001 "BESCRSU" + attribute \enum_value_1100100010 "BESCRR" + attribute \enum_value_1100100011 "BESCRRU" + attribute \enum_value_1100100100 "EBBHR" + attribute \enum_value_1100100101 "EBBRR" + attribute \enum_value_1100100110 "BESCR" + attribute \enum_value_1100101000 "reserved808" + attribute \enum_value_1100101001 "reserved809" + attribute \enum_value_1100101010 "reserved810" + attribute \enum_value_1100101011 "reserved811" + attribute \enum_value_1100101111 "TAR" + attribute \enum_value_1100110000 "ASDR" + attribute \enum_value_1100110111 "PSSCR" + attribute \enum_value_1101010000 "IC" + attribute \enum_value_1101010001 "VTB" + attribute \enum_value_1101010111 "PSSCR_hypv" + attribute \enum_value_1110000000 "PPR" + attribute \enum_value_1110000010 "PPR32" + attribute \enum_value_1111111111 "PIR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 10 \core_core_spr1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 10 \core_core_spr1$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \core_core_spr1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \core_core_spr1_ok$next + attribute \enum_base_type "SPR" + attribute \enum_value_0000000001 "XER" + attribute \enum_value_0000000011 "DSCR" + attribute \enum_value_0000001000 "LR" + attribute \enum_value_0000001001 "CTR" + attribute \enum_value_0000001101 "AMR" + attribute \enum_value_0000010001 "DSCR_priv" + attribute \enum_value_0000010010 "DSISR" + attribute \enum_value_0000010011 "DAR" + attribute \enum_value_0000010110 "DEC" + attribute \enum_value_0000011010 "SRR0" + attribute \enum_value_0000011011 "SRR1" + attribute \enum_value_0000011100 "CFAR" + attribute \enum_value_0000011101 "AMR_priv" + attribute \enum_value_0000110000 "PIDR" + attribute \enum_value_0000111101 "IAMR" + attribute \enum_value_0010000000 "TFHAR" + attribute \enum_value_0010000001 "TFIAR" + attribute \enum_value_0010000010 "TEXASR" + attribute \enum_value_0010000011 "TEXASRU" + attribute \enum_value_0010001000 "CTRL" + attribute \enum_value_0010010000 "TIDR" + attribute \enum_value_0010011000 "CTRL_priv" + attribute \enum_value_0010011001 "FSCR" + attribute \enum_value_0010011101 "UAMOR" + attribute \enum_value_0010011110 "GSR" + attribute \enum_value_0010011111 "PSPB" + attribute \enum_value_0010110000 "DPDES" + attribute \enum_value_0010110100 "DAWR0" + attribute \enum_value_0010111010 "RPR" + attribute \enum_value_0010111011 "CIABR" + attribute \enum_value_0010111100 "DAWRX0" + attribute \enum_value_0010111110 "HFSCR" + attribute \enum_value_0100000000 "VRSAVE" + attribute \enum_value_0100000011 "SPRG3" + attribute \enum_value_0100001100 "TB" + attribute \enum_value_0100001101 "TBU" + attribute \enum_value_0100010000 "SPRG0_priv" + attribute \enum_value_0100010001 "SPRG1_priv" + attribute \enum_value_0100010010 "SPRG2_priv" + attribute \enum_value_0100010011 "SPRG3_priv" + attribute \enum_value_0100011011 "CIR" + attribute \enum_value_0100011100 "TBL" + attribute \enum_value_0100011101 "TBU_hypv" + attribute \enum_value_0100011110 "TBU40" + attribute \enum_value_0100011111 "PVR" + attribute \enum_value_0100110000 "HSPRG0" + attribute \enum_value_0100110001 "HSPRG1" + attribute \enum_value_0100110010 "HDSISR" + attribute \enum_value_0100110011 "HDAR" + attribute \enum_value_0100110100 "SPURR" + attribute \enum_value_0100110101 "PURR" + attribute \enum_value_0100110110 "HDEC" + attribute \enum_value_0100111001 "HRMOR" + attribute \enum_value_0100111010 "HSRR0" + attribute \enum_value_0100111011 "HSRR1" + attribute \enum_value_0100111110 "LPCR" + attribute \enum_value_0100111111 "LPIDR" + attribute \enum_value_0101010000 "HMER" + attribute \enum_value_0101010001 "HMEER" + attribute \enum_value_0101010010 "PCR" + attribute \enum_value_0101010011 "HEIR" + attribute \enum_value_0101011101 "AMOR" + attribute \enum_value_0110111110 "TIR" + attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1100000000 "SIER" + attribute \enum_value_1100000001 "MMCR2" + attribute \enum_value_1100000010 "MMCRA" + attribute \enum_value_1100000011 "PMC1" + attribute \enum_value_1100000100 "PMC2" + attribute \enum_value_1100000101 "PMC3" + attribute \enum_value_1100000110 "PMC4" + attribute \enum_value_1100000111 "PMC5" + attribute \enum_value_1100001000 "PMC6" + attribute \enum_value_1100001011 "MMCR0" + attribute \enum_value_1100001100 "SIAR" + attribute \enum_value_1100001101 "SDAR" + attribute \enum_value_1100001110 "MMCR1" + attribute \enum_value_1100010000 "SIER_priv" + attribute \enum_value_1100010001 "MMCR2_priv" + attribute \enum_value_1100010010 "MMCRA_priv" + attribute \enum_value_1100010011 "PMC1_priv" + attribute \enum_value_1100010100 "PMC2_priv" + attribute \enum_value_1100010101 "PMC3_priv" + attribute \enum_value_1100010110 "PMC4_priv" + attribute \enum_value_1100010111 "PMC5_priv" + attribute \enum_value_1100011000 "PMC6_priv" + attribute \enum_value_1100011011 "MMCR0_priv" + attribute \enum_value_1100011100 "SIAR_priv" + attribute \enum_value_1100011101 "SDAR_priv" + attribute \enum_value_1100011110 "MMCR1_priv" + attribute \enum_value_1100100000 "BESCRS" + attribute \enum_value_1100100001 "BESCRSU" + attribute \enum_value_1100100010 "BESCRR" + attribute \enum_value_1100100011 "BESCRRU" + attribute \enum_value_1100100100 "EBBHR" + attribute \enum_value_1100100101 "EBBRR" + attribute \enum_value_1100100110 "BESCR" + attribute \enum_value_1100101000 "reserved808" + attribute \enum_value_1100101001 "reserved809" + attribute \enum_value_1100101010 "reserved810" + attribute \enum_value_1100101011 "reserved811" + attribute \enum_value_1100101111 "TAR" + attribute \enum_value_1100110000 "ASDR" + attribute \enum_value_1100110111 "PSSCR" + attribute \enum_value_1101010000 "IC" + attribute \enum_value_1101010001 "VTB" + attribute \enum_value_1101010111 "PSSCR_hypv" + attribute \enum_value_1110000000 "PPR" + attribute \enum_value_1110000010 "PPR32" + attribute \enum_value_1111111111 "PIR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 10 \core_core_spro + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 10 \core_core_spro$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:104" + wire \core_core_terminate_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:102" + wire width 3 \core_core_xer_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:102" + wire width 3 \core_core_xer_in$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:99" + wire \core_corebusy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire \core_coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \core_cr_out_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \core_cr_out_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire \core_cu_ad__go_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire \core_cu_ad__rel_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire \core_cu_st__go_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire \core_cu_st__rel_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \core_data_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:11" + wire width 64 \core_dec + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:11" + wire width 64 \core_dec$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 5 \core_dmi__addr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \core_dmi__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \core_dmi__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \core_ea_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \core_ea_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:10" + wire \core_eint + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:10" + wire \core_eint$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \core_fasto1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \core_fasto1_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \core_fasto2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \core_fasto2_ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 32 \core_full_rd2__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 8 \core_full_rd2__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 6 \core_full_rd__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 3 \core_full_rd__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 3 \core_issue__addr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 3 \core_issue__addr$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \core_issue__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \core_issue__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \core_issue__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \core_issue__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:98" + wire \core_issue_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:97" + wire \core_ivalid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:9" + wire width 64 \core_msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:9" + wire width 64 \core_msr$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \core_msr__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \core_msr__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:93" + wire width 32 \core_raw_insn_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:93" + wire width 32 \core_raw_insn_i$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \core_rego_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \core_rego_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \core_spro_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \core_spro_ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \core_state_nia_wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:102" + wire \core_stopped_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \core_wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:103" + wire \core_xer_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:103" + wire \core_xer_out$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire \cu_st__rel_o_dly + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire \cu_st__rel_o_dly$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + wire \cu_st__rel_o_rise + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:323" + wire \d_cr_delay + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:323" + wire \d_cr_delay$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:313" + wire \d_reg_delay + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:313" + wire \d_reg_delay$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:333" + wire \d_xer_delay + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:333" + wire \d_xer_delay$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:9" + wire width 64 \dbg_core_dbg_msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:8" + wire width 64 \dbg_core_dbg_pc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:98" + wire \dbg_core_rst_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:97" + wire \dbg_core_stop_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:103" + wire \dbg_core_stopped_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:77" + wire \dbg_d_cr_ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:79" + wire width 64 \dbg_d_cr_data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:76" + wire \dbg_d_cr_req + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:77" + wire \dbg_d_gpr_ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:78" + wire width 7 \dbg_d_gpr_addr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:79" + wire width 64 \dbg_d_gpr_data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:76" + wire \dbg_d_gpr_req + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:77" + wire \dbg_d_xer_ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:79" + wire width 64 \dbg_d_xer_data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:76" + wire \dbg_d_xer_req + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:62" + wire \dbg_dmi_ack_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:57" + wire width 4 \dbg_dmi_addr_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:57" + wire width 4 \dbg_dmi_addr_i$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:58" + wire width 64 \dbg_dmi_din + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:58" + wire width 64 \dbg_dmi_din$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:59" + wire width 64 \dbg_dmi_dout + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:60" + wire \dbg_dmi_req_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:60" + wire \dbg_dmi_req_i$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:61" + wire \dbg_dmi_we_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:61" + wire \dbg_dmi_we_i$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:102" + wire \dbg_terminate_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire input 138 \dbus__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 45 output 132 \dbus__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 2 input 141 \dbus__bte + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 3 input 140 \dbus__cti + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire output 136 \dbus__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 64 input 134 \dbus__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 64 output 133 \dbus__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire input 142 \dbus__err + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 8 output 135 \dbus__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire output 137 \dbus__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire output 139 \dbus__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:92" + wire width 8 \dec2_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + wire \dec2_bigendian + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:42" + wire width 64 \dec2_cia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \dec2_cr_in1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec2_cr_in1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \dec2_cr_in2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \dec2_cr_in2$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec2_cr_in2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec2_cr_in2_ok$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \dec2_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec2_cr_out_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 8 \dec2_cr_rd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec2_cr_rd_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 8 \dec2_cr_wr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec2_cr_wr_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:11" + wire width 64 \dec2_cur_dec + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:11" + wire width 64 \dec2_cur_dec$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:10" + wire \dec2_cur_eint + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:10" + wire \dec2_cur_eint$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:9" + wire width 64 \dec2_cur_msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:9" + wire width 64 \dec2_cur_msr$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:8" + wire width 64 \dec2_cur_pc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:8" + wire width 64 \dec2_cur_pc$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 \dec2_ea + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec2_ea_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \dec2_fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec2_fast1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \dec2_fast2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec2_fast2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \dec2_fasto1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec2_fasto1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \dec2_fasto2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec2_fasto2_ok + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47" + wire width 12 \dec2_fn_unit + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:51" + wire width 2 \dec2_input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:45" + wire width 32 \dec2_insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:46" + wire width 7 \dec2_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:56" + wire \dec2_is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48" + wire \dec2_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:41" + wire width 64 \dec2_msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec2_oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec2_oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:442" + wire width 32 \dec2_raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec2_rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec2_rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 \dec2_reg1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec2_reg1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 \dec2_reg2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec2_reg2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 \dec2_reg3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec2_reg3_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 \dec2_rego + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec2_rego_ok + attribute \enum_base_type "SPR" + attribute \enum_value_0000000001 "XER" + attribute \enum_value_0000000011 "DSCR" + attribute \enum_value_0000001000 "LR" + attribute \enum_value_0000001001 "CTR" + attribute \enum_value_0000001101 "AMR" + attribute \enum_value_0000010001 "DSCR_priv" + attribute \enum_value_0000010010 "DSISR" + attribute \enum_value_0000010011 "DAR" + attribute \enum_value_0000010110 "DEC" + attribute \enum_value_0000011010 "SRR0" + attribute \enum_value_0000011011 "SRR1" + attribute \enum_value_0000011100 "CFAR" + attribute \enum_value_0000011101 "AMR_priv" + attribute \enum_value_0000110000 "PIDR" + attribute \enum_value_0000111101 "IAMR" + attribute \enum_value_0010000000 "TFHAR" + attribute \enum_value_0010000001 "TFIAR" + attribute \enum_value_0010000010 "TEXASR" + attribute \enum_value_0010000011 "TEXASRU" + attribute \enum_value_0010001000 "CTRL" + attribute \enum_value_0010010000 "TIDR" + attribute \enum_value_0010011000 "CTRL_priv" + attribute \enum_value_0010011001 "FSCR" + attribute \enum_value_0010011101 "UAMOR" + attribute \enum_value_0010011110 "GSR" + attribute \enum_value_0010011111 "PSPB" + attribute \enum_value_0010110000 "DPDES" + attribute \enum_value_0010110100 "DAWR0" + attribute \enum_value_0010111010 "RPR" + attribute \enum_value_0010111011 "CIABR" + attribute \enum_value_0010111100 "DAWRX0" + attribute \enum_value_0010111110 "HFSCR" + attribute \enum_value_0100000000 "VRSAVE" + attribute \enum_value_0100000011 "SPRG3" + attribute \enum_value_0100001100 "TB" + attribute \enum_value_0100001101 "TBU" + attribute \enum_value_0100010000 "SPRG0_priv" + attribute \enum_value_0100010001 "SPRG1_priv" + attribute \enum_value_0100010010 "SPRG2_priv" + attribute \enum_value_0100010011 "SPRG3_priv" + attribute \enum_value_0100011011 "CIR" + attribute \enum_value_0100011100 "TBL" + attribute \enum_value_0100011101 "TBU_hypv" + attribute \enum_value_0100011110 "TBU40" + attribute \enum_value_0100011111 "PVR" + attribute \enum_value_0100110000 "HSPRG0" + attribute \enum_value_0100110001 "HSPRG1" + attribute \enum_value_0100110010 "HDSISR" + attribute \enum_value_0100110011 "HDAR" + attribute \enum_value_0100110100 "SPURR" + attribute \enum_value_0100110101 "PURR" + attribute \enum_value_0100110110 "HDEC" + attribute \enum_value_0100111001 "HRMOR" + attribute \enum_value_0100111010 "HSRR0" + attribute \enum_value_0100111011 "HSRR1" + attribute \enum_value_0100111110 "LPCR" + attribute \enum_value_0100111111 "LPIDR" + attribute \enum_value_0101010000 "HMER" + attribute \enum_value_0101010001 "HMEER" + attribute \enum_value_0101010010 "PCR" + attribute \enum_value_0101010011 "HEIR" + attribute \enum_value_0101011101 "AMOR" + attribute \enum_value_0110111110 "TIR" + attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1100000000 "SIER" + attribute \enum_value_1100000001 "MMCR2" + attribute \enum_value_1100000010 "MMCRA" + attribute \enum_value_1100000011 "PMC1" + attribute \enum_value_1100000100 "PMC2" + attribute \enum_value_1100000101 "PMC3" + attribute \enum_value_1100000110 "PMC4" + attribute \enum_value_1100000111 "PMC5" + attribute \enum_value_1100001000 "PMC6" + attribute \enum_value_1100001011 "MMCR0" + attribute \enum_value_1100001100 "SIAR" + attribute \enum_value_1100001101 "SDAR" + attribute \enum_value_1100001110 "MMCR1" + attribute \enum_value_1100010000 "SIER_priv" + attribute \enum_value_1100010001 "MMCR2_priv" + attribute \enum_value_1100010010 "MMCRA_priv" + attribute \enum_value_1100010011 "PMC1_priv" + attribute \enum_value_1100010100 "PMC2_priv" + attribute \enum_value_1100010101 "PMC3_priv" + attribute \enum_value_1100010110 "PMC4_priv" + attribute \enum_value_1100010111 "PMC5_priv" + attribute \enum_value_1100011000 "PMC6_priv" + attribute \enum_value_1100011011 "MMCR0_priv" + attribute \enum_value_1100011100 "SIAR_priv" + attribute \enum_value_1100011101 "SDAR_priv" + attribute \enum_value_1100011110 "MMCR1_priv" + attribute \enum_value_1100100000 "BESCRS" + attribute \enum_value_1100100001 "BESCRSU" + attribute \enum_value_1100100010 "BESCRR" + attribute \enum_value_1100100011 "BESCRRU" + attribute \enum_value_1100100100 "EBBHR" + attribute \enum_value_1100100101 "EBBRR" + attribute \enum_value_1100100110 "BESCR" + attribute \enum_value_1100101000 "reserved808" + attribute \enum_value_1100101001 "reserved809" + attribute \enum_value_1100101010 "reserved810" + attribute \enum_value_1100101011 "reserved811" + attribute \enum_value_1100101111 "TAR" + attribute \enum_value_1100110000 "ASDR" + attribute \enum_value_1100110111 "PSSCR" + attribute \enum_value_1101010000 "IC" + attribute \enum_value_1101010001 "VTB" + attribute \enum_value_1101010111 "PSSCR_hypv" + attribute \enum_value_1110000000 "PPR" + attribute \enum_value_1110000010 "PPR32" + attribute \enum_value_1111111111 "PIR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 10 \dec2_spr1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec2_spr1_ok + attribute \enum_base_type "SPR" + attribute \enum_value_0000000001 "XER" + attribute \enum_value_0000000011 "DSCR" + attribute \enum_value_0000001000 "LR" + attribute \enum_value_0000001001 "CTR" + attribute \enum_value_0000001101 "AMR" + attribute \enum_value_0000010001 "DSCR_priv" + attribute \enum_value_0000010010 "DSISR" + attribute \enum_value_0000010011 "DAR" + attribute \enum_value_0000010110 "DEC" + attribute \enum_value_0000011010 "SRR0" + attribute \enum_value_0000011011 "SRR1" + attribute \enum_value_0000011100 "CFAR" + attribute \enum_value_0000011101 "AMR_priv" + attribute \enum_value_0000110000 "PIDR" + attribute \enum_value_0000111101 "IAMR" + attribute \enum_value_0010000000 "TFHAR" + attribute \enum_value_0010000001 "TFIAR" + attribute \enum_value_0010000010 "TEXASR" + attribute \enum_value_0010000011 "TEXASRU" + attribute \enum_value_0010001000 "CTRL" + attribute \enum_value_0010010000 "TIDR" + attribute \enum_value_0010011000 "CTRL_priv" + attribute \enum_value_0010011001 "FSCR" + attribute \enum_value_0010011101 "UAMOR" + attribute \enum_value_0010011110 "GSR" + attribute \enum_value_0010011111 "PSPB" + attribute \enum_value_0010110000 "DPDES" + attribute \enum_value_0010110100 "DAWR0" + attribute \enum_value_0010111010 "RPR" + attribute \enum_value_0010111011 "CIABR" + attribute \enum_value_0010111100 "DAWRX0" + attribute \enum_value_0010111110 "HFSCR" + attribute \enum_value_0100000000 "VRSAVE" + attribute \enum_value_0100000011 "SPRG3" + attribute \enum_value_0100001100 "TB" + attribute \enum_value_0100001101 "TBU" + attribute \enum_value_0100010000 "SPRG0_priv" + attribute \enum_value_0100010001 "SPRG1_priv" + attribute \enum_value_0100010010 "SPRG2_priv" + attribute \enum_value_0100010011 "SPRG3_priv" + attribute \enum_value_0100011011 "CIR" + attribute \enum_value_0100011100 "TBL" + attribute \enum_value_0100011101 "TBU_hypv" + attribute \enum_value_0100011110 "TBU40" + attribute \enum_value_0100011111 "PVR" + attribute \enum_value_0100110000 "HSPRG0" + attribute \enum_value_0100110001 "HSPRG1" + attribute \enum_value_0100110010 "HDSISR" + attribute \enum_value_0100110011 "HDAR" + attribute \enum_value_0100110100 "SPURR" + attribute \enum_value_0100110101 "PURR" + attribute \enum_value_0100110110 "HDEC" + attribute \enum_value_0100111001 "HRMOR" + attribute \enum_value_0100111010 "HSRR0" + attribute \enum_value_0100111011 "HSRR1" + attribute \enum_value_0100111110 "LPCR" + attribute \enum_value_0100111111 "LPIDR" + attribute \enum_value_0101010000 "HMER" + attribute \enum_value_0101010001 "HMEER" + attribute \enum_value_0101010010 "PCR" + attribute \enum_value_0101010011 "HEIR" + attribute \enum_value_0101011101 "AMOR" + attribute \enum_value_0110111110 "TIR" + attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1100000000 "SIER" + attribute \enum_value_1100000001 "MMCR2" + attribute \enum_value_1100000010 "MMCRA" + attribute \enum_value_1100000011 "PMC1" + attribute \enum_value_1100000100 "PMC2" + attribute \enum_value_1100000101 "PMC3" + attribute \enum_value_1100000110 "PMC4" + attribute \enum_value_1100000111 "PMC5" + attribute \enum_value_1100001000 "PMC6" + attribute \enum_value_1100001011 "MMCR0" + attribute \enum_value_1100001100 "SIAR" + attribute \enum_value_1100001101 "SDAR" + attribute \enum_value_1100001110 "MMCR1" + attribute \enum_value_1100010000 "SIER_priv" + attribute \enum_value_1100010001 "MMCR2_priv" + attribute \enum_value_1100010010 "MMCRA_priv" + attribute \enum_value_1100010011 "PMC1_priv" + attribute \enum_value_1100010100 "PMC2_priv" + attribute \enum_value_1100010101 "PMC3_priv" + attribute \enum_value_1100010110 "PMC4_priv" + attribute \enum_value_1100010111 "PMC5_priv" + attribute \enum_value_1100011000 "PMC6_priv" + attribute \enum_value_1100011011 "MMCR0_priv" + attribute \enum_value_1100011100 "SIAR_priv" + attribute \enum_value_1100011101 "SDAR_priv" + attribute \enum_value_1100011110 "MMCR1_priv" + attribute \enum_value_1100100000 "BESCRS" + attribute \enum_value_1100100001 "BESCRSU" + attribute \enum_value_1100100010 "BESCRR" + attribute \enum_value_1100100011 "BESCRRU" + attribute \enum_value_1100100100 "EBBHR" + attribute \enum_value_1100100101 "EBBRR" + attribute \enum_value_1100100110 "BESCR" + attribute \enum_value_1100101000 "reserved808" + attribute \enum_value_1100101001 "reserved809" + attribute \enum_value_1100101010 "reserved810" + attribute \enum_value_1100101011 "reserved811" + attribute \enum_value_1100101111 "TAR" + attribute \enum_value_1100110000 "ASDR" + attribute \enum_value_1100110111 "PSSCR" + attribute \enum_value_1101010000 "IC" + attribute \enum_value_1101010001 "VTB" + attribute \enum_value_1101010111 "PSSCR_hypv" + attribute \enum_value_1110000000 "PPR" + attribute \enum_value_1110000010 "PPR32" + attribute \enum_value_1111111111 "PIR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 10 \dec2_spro + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec2_spro_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53" + wire width 13 \dec2_trapaddr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:52" + wire width 7 \dec2_traptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:102" + wire width 3 \dec2_xer_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:103" + wire \dec2_xer_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:155" + wire width 2 \delay + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:155" + wire width 2 \delay$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:225" + wire width 2 \fsm_state + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:361" + wire width 2 \fsm_state$117 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:361" + wire width 2 \fsm_state$117$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:225" + wire width 2 \fsm_state$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 25 \gpio_gpio0__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 26 \gpio_gpio0__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 27 \gpio_gpio0__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 28 \gpio_gpio0__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 29 \gpio_gpio0__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 30 \gpio_gpio0__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 85 \gpio_gpio10__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 86 \gpio_gpio10__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 87 \gpio_gpio10__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 88 \gpio_gpio10__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 89 \gpio_gpio10__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 90 \gpio_gpio10__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 91 \gpio_gpio11__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 92 \gpio_gpio11__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 93 \gpio_gpio11__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 94 \gpio_gpio11__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 95 \gpio_gpio11__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 96 \gpio_gpio11__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 97 \gpio_gpio12__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 98 \gpio_gpio12__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 99 \gpio_gpio12__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 100 \gpio_gpio12__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 101 \gpio_gpio12__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 102 \gpio_gpio12__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 103 \gpio_gpio13__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 104 \gpio_gpio13__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 105 \gpio_gpio13__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 106 \gpio_gpio13__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 107 \gpio_gpio13__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 108 \gpio_gpio13__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 109 \gpio_gpio14__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 110 \gpio_gpio14__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 111 \gpio_gpio14__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 112 \gpio_gpio14__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 113 \gpio_gpio14__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 114 \gpio_gpio14__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 115 \gpio_gpio15__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 116 \gpio_gpio15__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 117 \gpio_gpio15__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 118 \gpio_gpio15__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 119 \gpio_gpio15__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 120 \gpio_gpio15__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 31 \gpio_gpio1__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 32 \gpio_gpio1__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 33 \gpio_gpio1__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 34 \gpio_gpio1__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 35 \gpio_gpio1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 36 \gpio_gpio1__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 37 \gpio_gpio2__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 38 \gpio_gpio2__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 39 \gpio_gpio2__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 40 \gpio_gpio2__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 41 \gpio_gpio2__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 42 \gpio_gpio2__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 43 \gpio_gpio3__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 44 \gpio_gpio3__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 45 \gpio_gpio3__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 46 \gpio_gpio3__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 47 \gpio_gpio3__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 48 \gpio_gpio3__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 49 \gpio_gpio4__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 50 \gpio_gpio4__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 51 \gpio_gpio4__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 52 \gpio_gpio4__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 53 \gpio_gpio4__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 54 \gpio_gpio4__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 55 \gpio_gpio5__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 56 \gpio_gpio5__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 57 \gpio_gpio5__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 58 \gpio_gpio5__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 59 \gpio_gpio5__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 60 \gpio_gpio5__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 61 \gpio_gpio6__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 62 \gpio_gpio6__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 63 \gpio_gpio6__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 64 \gpio_gpio6__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 65 \gpio_gpio6__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 66 \gpio_gpio6__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 67 \gpio_gpio7__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 68 \gpio_gpio7__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 69 \gpio_gpio7__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 70 \gpio_gpio7__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 71 \gpio_gpio7__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 72 \gpio_gpio7__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 73 \gpio_gpio8__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 74 \gpio_gpio8__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 75 \gpio_gpio8__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 76 \gpio_gpio8__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 77 \gpio_gpio8__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 78 \gpio_gpio8__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 79 \gpio_gpio9__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 80 \gpio_gpio9__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 81 \gpio_gpio9__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 82 \gpio_gpio9__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 83 \gpio_gpio9__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 84 \gpio_gpio9__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire input 127 \ibus__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire width 45 output 121 \ibus__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire width 2 input 130 \ibus__bte + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire width 3 input 129 \ibus__cti + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire output 125 \ibus__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire width 64 input 123 \ibus__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire width 64 input 122 \ibus__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire input 131 \ibus__err + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire width 8 output 124 \ibus__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire output 126 \ibus__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire input 128 \ibus__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire output 149 \icp_wb__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire width 28 input 143 \icp_wb__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire width 2 input 152 \icp_wb__bte + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire width 3 input 151 \icp_wb__cti + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire input 147 \icp_wb__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire width 32 output 145 \icp_wb__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire width 32 input 144 \icp_wb__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire input 153 \icp_wb__err + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire width 4 input 146 \icp_wb__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire input 148 \icp_wb__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire input 150 \icp_wb__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire output 160 \ics_wb__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire width 28 input 154 \ics_wb__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire width 2 input 163 \ics_wb__bte + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire width 3 input 162 \ics_wb__cti + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire input 158 \ics_wb__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire width 32 output 156 \ics_wb__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire width 32 input 155 \ics_wb__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire input 164 \ics_wb__err + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire width 4 input 157 \ics_wb__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire input 159 \ics_wb__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire input 161 \ics_wb__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:177" + wire width 32 \ilatch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:177" + wire width 32 \ilatch$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:24" + wire width 48 \imem_a_pc_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:26" + wire \imem_a_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:32" + wire \imem_f_busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:33" + wire width 64 \imem_f_instr_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:28" + wire \imem_f_valid_i + attribute \src "libresoc.v:178436.7-178436.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:237" + wire width 16 input 165 \int_level_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:62" + wire \jtag_dmi0_ack_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:62" + wire \jtag_dmi0_ack_o$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:57" + wire width 4 \jtag_dmi0_addr_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:58" + wire width 64 \jtag_dmi0_din + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:59" + wire width 64 \jtag_dmi0_dout + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:59" + wire width 64 \jtag_dmi0_dout$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:60" + wire \jtag_dmi0_req_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:61" + wire \jtag_dmi0_we_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:89" + wire input 19 \jtag_wb__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:89" + wire width 29 output 12 \jtag_wb__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:89" + wire output 16 \jtag_wb__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:89" + wire width 64 input 14 \jtag_wb__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:89" + wire width 64 output 13 \jtag_wb__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:89" + wire input 20 \jtag_wb__err + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:89" + wire output 15 \jtag_wb__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:89" + wire output 17 \jtag_wb__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:89" + wire output 18 \jtag_wb__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:91" + wire input 3 \memerr_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:203" + wire \msr_read + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:203" + wire \msr_read$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:371" + wire width 64 \new_dec + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:388" + wire width 64 \new_tb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:180" + wire width 64 \nia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:184" + wire width 64 \pc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:175" + wire \pc_changed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:175" + wire \pc_changed$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 input 166 \pc_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire input 1 \pc_i_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:87" + wire width 64 output 2 \pc_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:185" + wire \pc_ok_delay + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:185" + wire \pc_ok_delay$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:150" + wire \por_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:151" + wire input 7 \rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 23 \uart_rx__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 24 \uart_rx__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire input 21 \uart_tx__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" + wire output 22 \uart_tx__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:83" + wire \xics_icp_core_irq_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:46" + wire width 8 \xics_icp_ics_i_pri + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:45" + wire width 4 \xics_icp_ics_i_src + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:46" + wire width 8 \xics_ics_icp_o_pri + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:45" + wire width 4 \xics_ics_icp_o_src + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:389" + cell $add $add$libresoc.v:180082$12874 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 65 + connect \A \core_issue__data_o + connect \B 1'1 + connect \Y $add$libresoc.v:180082$12874_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:181" + cell $add $add$libresoc.v:180087$12879 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 65 + connect \A \dec2_cur_pc + connect \B 3'100 + connect \Y $add$libresoc.v:180087$12879_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" + cell $and $and$libresoc.v:180071$12861 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$95 + connect \B \$97 + connect \Y $and$libresoc.v:180071$12861_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $and$libresoc.v:180086$12878 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \core_cu_st__rel_o + connect \B \$16 + connect \Y $and$libresoc.v:180086$12878_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" + cell $and $and$libresoc.v:180095$12887 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$33 + connect \B \$35 + connect \Y $and$libresoc.v:180095$12887_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289" + cell $and $and$libresoc.v:180096$12888 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \core_state_nia_wen + connect \B 1'1 + connect \Y $and$libresoc.v:180096$12888_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" + cell $and $and$libresoc.v:180103$12895 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$49 + connect \B \$51 + connect \Y $and$libresoc.v:180103$12895_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" + cell $and $and$libresoc.v:180106$12898 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$55 + connect \B \$57 + connect \Y $and$libresoc.v:180106$12898_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" + cell $and $and$libresoc.v:180109$12901 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$61 + connect \B \$63 + connect \Y $and$libresoc.v:180109$12901_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" + cell $and $and$libresoc.v:180112$12904 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$67 + connect \B \$69 + connect \Y $and$libresoc.v:180112$12904_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" + cell $and $and$libresoc.v:180115$12907 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$73 + connect \B \$75 + connect \Y $and$libresoc.v:180115$12907_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" + cell $and $and$libresoc.v:180120$12912 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$81 + connect \B \$83 + connect \Y $and$libresoc.v:180120$12912_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" + cell $and $and$libresoc.v:180124$12916 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$89 + connect \B \$91 + connect \Y $and$libresoc.v:180124$12916_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + cell $pos $extend$libresoc.v:180079$12869 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \Y_WIDTH 64 + connect \A \core_full_rd2__data_o + connect \Y $extend$libresoc.v:180079$12869_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + cell $pos $extend$libresoc.v:180080$12871 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 64 + connect \A \core_full_rd__data_o + connect \Y $extend$libresoc.v:180080$12871_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609" + cell $mul $mul$libresoc.v:180073$12863 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 7 + connect \A \dec2_cur_pc [2] + connect \B 6'100000 + connect \Y $mul$libresoc.v:180073$12863_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609" + cell $mul $mul$libresoc.v:180075$12865 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 7 + connect \A \dec2_cur_pc [2] + connect \B 6'100000 + connect \Y $mul$libresoc.v:180075$12865_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:287" + cell $ne $ne$libresoc.v:180078$12868 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \core_core_core_insn_type + connect \B 7'0000001 + connect \Y $ne$libresoc.v:180078$12868_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:161" + cell $ne $ne$libresoc.v:180084$12876 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \delay + connect \B \$12 + connect \Y $ne$libresoc.v:180084$12876_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:156" + cell $ne $ne$libresoc.v:180116$12908 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \delay + connect \B 1'0 + connect \Y $ne$libresoc.v:180116$12908_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:255" + cell $not $not$libresoc.v:180072$12862 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \msr_read + connect \Y $not$libresoc.v:180072$12862_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $not$libresoc.v:180085$12877 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_st__rel_o_dly + connect \Y $not$libresoc.v:180085$12877_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:186" + cell $not $not$libresoc.v:180088$12880 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \pc_i_ok + connect \Y $not$libresoc.v:180088$12880_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:291" + cell $not $not$libresoc.v:180089$12881 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \core_corebusy_o + connect \Y $not$libresoc.v:180089$12881_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + cell $not $not$libresoc.v:180090$12882 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \pc_changed + connect \Y $not$libresoc.v:180090$12882_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:291" + cell $not $not$libresoc.v:180091$12883 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \core_corebusy_o + connect \Y $not$libresoc.v:180091$12883_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + cell $not $not$libresoc.v:180092$12884 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \pc_changed + connect \Y $not$libresoc.v:180092$12884_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" + cell $not $not$libresoc.v:180093$12885 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dbg_core_stop_o + connect \Y $not$libresoc.v:180093$12885_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" + cell $not $not$libresoc.v:180094$12886 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \core_core_reset_i + connect \Y $not$libresoc.v:180094$12886_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:291" + cell $not $not$libresoc.v:180098$12890 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \core_corebusy_o + connect \Y $not$libresoc.v:180098$12890_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:291" + cell $not $not$libresoc.v:180099$12891 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \core_corebusy_o + connect \Y $not$libresoc.v:180099$12891_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:291" + cell $not $not$libresoc.v:180100$12892 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \core_corebusy_o + connect \Y $not$libresoc.v:180100$12892_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" + cell $not $not$libresoc.v:180101$12893 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dbg_core_stop_o + connect \Y $not$libresoc.v:180101$12893_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" + cell $not $not$libresoc.v:180102$12894 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \core_core_reset_i + connect \Y $not$libresoc.v:180102$12894_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" + cell $not $not$libresoc.v:180104$12896 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dbg_core_stop_o + connect \Y $not$libresoc.v:180104$12896_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" + cell $not $not$libresoc.v:180105$12897 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \core_core_reset_i + connect \Y $not$libresoc.v:180105$12897_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" + cell $not $not$libresoc.v:180107$12899 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dbg_core_stop_o + connect \Y $not$libresoc.v:180107$12899_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" + cell $not $not$libresoc.v:180108$12900 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \core_core_reset_i + connect \Y $not$libresoc.v:180108$12900_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" + cell $not $not$libresoc.v:180110$12902 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dbg_core_stop_o + connect \Y $not$libresoc.v:180110$12902_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" + cell $not $not$libresoc.v:180111$12903 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \core_core_reset_i + connect \Y $not$libresoc.v:180111$12903_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" + cell $not $not$libresoc.v:180113$12905 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dbg_core_stop_o + connect \Y $not$libresoc.v:180113$12905_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" + cell $not $not$libresoc.v:180114$12906 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \core_core_reset_i + connect \Y $not$libresoc.v:180114$12906_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:255" + cell $not $not$libresoc.v:180117$12909 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \msr_read + connect \Y $not$libresoc.v:180117$12909_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" + cell $not $not$libresoc.v:180118$12910 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dbg_core_stop_o + connect \Y $not$libresoc.v:180118$12910_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" + cell $not $not$libresoc.v:180119$12911 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \core_core_reset_i + connect \Y $not$libresoc.v:180119$12911_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:291" + cell $not $not$libresoc.v:180121$12913 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \core_corebusy_o + connect \Y $not$libresoc.v:180121$12913_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" + cell $not $not$libresoc.v:180122$12914 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dbg_core_stop_o + connect \Y $not$libresoc.v:180122$12914_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" + cell $not $not$libresoc.v:180123$12915 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \core_core_reset_i + connect \Y $not$libresoc.v:180123$12915_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" + cell $not $not$libresoc.v:180125$12917 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dbg_core_stop_o + connect \Y $not$libresoc.v:180125$12917_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" + cell $not $not$libresoc.v:180126$12918 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \core_core_reset_i + connect \Y $not$libresoc.v:180126$12918_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:161" + cell $or $or$libresoc.v:180083$12875 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A 1'0 + connect \B \dbg_core_rst_o + connect \Y $or$libresoc.v:180083$12875_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + cell $pos $pos$libresoc.v:180079$12870 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:180079$12869_Y + connect \Y $pos$libresoc.v:180079$12870_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + cell $pos $pos$libresoc.v:180080$12872 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:180080$12871_Y + connect \Y $pos$libresoc.v:180080$12872_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + cell $reduce_or $reduce_or$libresoc.v:180097$12889 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \$40 + connect \Y $reduce_or$libresoc.v:180097$12889_Y + end + attribute \src "libresoc.v:180074.19-180074.42" + cell $shr $shr$libresoc.v:180074$12864 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 64 + connect \A \imem_f_instr_o + connect \B \$104 + connect \Y $shr$libresoc.v:180074$12864_Y + end + attribute \src "libresoc.v:180077.19-180077.42" + cell $shr $shr$libresoc.v:180077$12867 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 64 + connect \A \imem_f_instr_o + connect \B \$108 + connect \Y $shr$libresoc.v:180077$12867_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:157" + cell $sub $sub$libresoc.v:180076$12866 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \delay + connect \B 1'1 + connect \Y $sub$libresoc.v:180076$12866_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:373" + cell $sub $sub$libresoc.v:180081$12873 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 65 + connect \A \core_issue__data_o + connect \B 1'1 + connect \Y $sub$libresoc.v:180081$12873_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:180283.8-180367.4" + cell \core \core + connect \bigendian_i \core_bigendian_i$3 + connect \cia__data_o \core_cia__data_o + connect \cia__ren \core_cia__ren + connect \core_core_cia \core_core_core_cia + connect \core_core_cr_rd \core_core_core_cr_rd + connect \core_core_cr_rd_ok \core_core_core_cr_rd_ok + connect \core_core_cr_wr \core_core_core_cr_wr + connect \core_core_fn_unit \core_core_core_fn_unit + connect \core_core_input_carry \core_core_core_input_carry + connect \core_core_insn \core_core_core_insn + connect \core_core_insn_type \core_core_core_insn_type + connect \core_core_is_32bit \core_core_core_is_32bit + connect \core_core_msr \core_core_core_msr + connect \core_core_oe \core_core_core_oe + connect \core_core_oe_ok \core_core_core_oe_ok + connect \core_core_rc \core_core_core_rc + connect \core_core_rc_ok \core_core_core_rc_ok + connect \core_core_trapaddr \core_core_core_trapaddr + connect \core_core_traptype \core_core_core_traptype + connect \core_cr_in1 \core_core_cr_in1 + connect \core_cr_in1_ok \core_core_cr_in1_ok + connect \core_cr_in2 \core_core_cr_in2 + connect \core_cr_in2$1 \core_core_cr_in2$1 + connect \core_cr_in2_ok \core_core_cr_in2_ok + connect \core_cr_in2_ok$2 \core_core_cr_in2_ok$2 + connect \core_cr_out \core_core_cr_out + connect \core_ea \core_core_ea + connect \core_fast1 \core_core_fast1 + connect \core_fast1_ok \core_core_fast1_ok + connect \core_fast2 \core_core_fast2 + connect \core_fast2_ok \core_core_fast2_ok + connect \core_fasto1 \core_core_fasto1 + connect \core_fasto2 \core_core_fasto2 + connect \core_pc \core_core_pc + connect \core_reg1 \core_core_reg1 + connect \core_reg1_ok \core_core_reg1_ok + connect \core_reg2 \core_core_reg2 + connect \core_reg2_ok \core_core_reg2_ok + connect \core_reg3 \core_core_reg3 + connect \core_reg3_ok \core_core_reg3_ok + connect \core_rego \core_core_rego + connect \core_reset_i \core_core_reset_i + connect \core_spr1 \core_core_spr1 + connect \core_spr1_ok \core_core_spr1_ok + connect \core_spro \core_core_spro + connect \core_terminate_o \core_core_terminate_o + connect \core_xer_in \core_core_xer_in + connect \corebusy_o \core_corebusy_o + connect \coresync_clk \core_coresync_clk + connect \cu_ad__go_i \core_cu_ad__go_i + connect \cu_ad__rel_o \core_cu_ad__rel_o + connect \cu_st__go_i \core_cu_st__go_i + connect \cu_st__rel_o \core_cu_st__rel_o + connect \data_i \core_data_i + connect \dbus__ack \dbus__ack + connect \dbus__adr \dbus__adr + connect \dbus__cyc \dbus__cyc + connect \dbus__dat_r \dbus__dat_r + connect \dbus__dat_w \dbus__dat_w + connect \dbus__err \dbus__err + connect \dbus__sel \dbus__sel + connect \dbus__stb \dbus__stb + connect \dbus__we \dbus__we + connect \dmi__addr \core_dmi__addr + connect \dmi__data_o \core_dmi__data_o + connect \dmi__ren \core_dmi__ren + connect \full_rd2__data_o \core_full_rd2__data_o + connect \full_rd2__ren \core_full_rd2__ren + connect \full_rd__data_o \core_full_rd__data_o + connect \full_rd__ren \core_full_rd__ren + connect \issue__addr \core_issue__addr + connect \issue__addr$3 \core_issue__addr$4 + connect \issue__data_i \core_issue__data_i + connect \issue__data_o \core_issue__data_o + connect \issue__ren \core_issue__ren + connect \issue__wen \core_issue__wen + connect \issue_i \core_issue_i + connect \ivalid_i \core_ivalid_i + connect \msr__data_o \core_msr__data_o + connect \msr__ren \core_msr__ren + connect \raw_insn_i \core_raw_insn_i + connect \state_nia_wen \core_state_nia_wen + connect \wen \core_wen + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:180368.7-180393.4" + cell \dbg \dbg + connect \clk \clk + connect \core_dbg_msr \dbg_core_dbg_msr + connect \core_dbg_pc \dbg_core_dbg_pc + connect \core_rst_o \dbg_core_rst_o + connect \core_stop_o \dbg_core_stop_o + connect \core_stopped_i \dbg_core_stopped_i + connect \d_cr_ack \dbg_d_cr_ack + connect \d_cr_data \dbg_d_cr_data + connect \d_cr_req \dbg_d_cr_req + connect \d_gpr_ack \dbg_d_gpr_ack + connect \d_gpr_addr \dbg_d_gpr_addr + connect \d_gpr_data \dbg_d_gpr_data + connect \d_gpr_req \dbg_d_gpr_req + connect \d_xer_ack \dbg_d_xer_ack + connect \d_xer_data \dbg_d_xer_data + connect \d_xer_req \dbg_d_xer_req + connect \dmi_ack_o \dbg_dmi_ack_o + connect \dmi_addr_i \dbg_dmi_addr_i + connect \dmi_din \dbg_dmi_din + connect \dmi_dout \dbg_dmi_dout + connect \dmi_req_i \dbg_dmi_req_i + connect \dmi_we_i \dbg_dmi_we_i + connect \rst \rst + connect \terminate_i \dbg_terminate_i + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:180394.8-180452.4" + cell \dec2 \dec2 + connect \asmcode \dec2_asmcode + connect \bigendian \dec2_bigendian + connect \cia \dec2_cia + connect \cr_in1 \dec2_cr_in1 + connect \cr_in1_ok \dec2_cr_in1_ok + connect \cr_in2 \dec2_cr_in2 + connect \cr_in2$1 \dec2_cr_in2$5 + connect \cr_in2_ok \dec2_cr_in2_ok + connect \cr_in2_ok$2 \dec2_cr_in2_ok$6 + connect \cr_out \dec2_cr_out + connect \cr_out_ok \dec2_cr_out_ok + connect \cr_rd \dec2_cr_rd + connect \cr_rd_ok \dec2_cr_rd_ok + connect \cr_wr \dec2_cr_wr + connect \cr_wr_ok \dec2_cr_wr_ok + connect \cur_dec \dec2_cur_dec + connect \cur_eint \dec2_cur_eint + connect \cur_msr \dec2_cur_msr + connect \cur_pc \dec2_cur_pc + connect \ea \dec2_ea + connect \ea_ok \dec2_ea_ok + connect \fast1 \dec2_fast1 + connect \fast1_ok \dec2_fast1_ok + connect \fast2 \dec2_fast2 + connect \fast2_ok \dec2_fast2_ok + connect \fasto1 \dec2_fasto1 + connect \fasto1_ok \dec2_fasto1_ok + connect \fasto2 \dec2_fasto2 + connect \fasto2_ok \dec2_fasto2_ok + connect \fn_unit \dec2_fn_unit + connect \input_carry \dec2_input_carry + connect \insn \dec2_insn + connect \insn_type \dec2_insn_type + connect \is_32bit \dec2_is_32bit + connect \lk \dec2_lk + connect \msr \dec2_msr + connect \oe \dec2_oe + connect \oe_ok \dec2_oe_ok + connect \raw_opcode_in \dec2_raw_opcode_in + connect \rc \dec2_rc + connect \rc_ok \dec2_rc_ok + connect \reg1 \dec2_reg1 + connect \reg1_ok \dec2_reg1_ok + connect \reg2 \dec2_reg2 + connect \reg2_ok \dec2_reg2_ok + connect \reg3 \dec2_reg3 + connect \reg3_ok \dec2_reg3_ok + connect \rego \dec2_rego + connect \rego_ok \dec2_rego_ok + connect \spr1 \dec2_spr1 + connect \spr1_ok \dec2_spr1_ok + connect \spro \dec2_spro + connect \spro_ok \dec2_spro_ok + connect \trapaddr \dec2_trapaddr + connect \traptype \dec2_traptype + connect \xer_in \dec2_xer_in + connect \xer_out \dec2_xer_out + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:180453.8-180468.4" + cell \imem \imem + connect \a_pc_i \imem_a_pc_i + connect \a_valid_i \imem_a_valid_i + connect \clk \clk + connect \f_busy_o \imem_f_busy_o + connect \f_instr_o \imem_f_instr_o + connect \f_valid_i \imem_f_valid_i + connect \ibus__ack \ibus__ack + connect \ibus__adr \ibus__adr + connect \ibus__cyc \ibus__cyc + connect \ibus__dat_r \ibus__dat_r + connect \ibus__err \ibus__err + connect \ibus__sel \ibus__sel + connect \ibus__stb \ibus__stb + connect \rst \rst + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:180469.8-180590.4" + cell \jtag \jtag + connect \TAP_bus__tck \TAP_bus__tck + connect \TAP_bus__tdi \TAP_bus__tdi + connect \TAP_bus__tdo \TAP_bus__tdo + connect \TAP_bus__tms \TAP_bus__tms + connect \clk \clk + connect \dmi0_ack_o \jtag_dmi0_ack_o + connect \dmi0_addr_i \jtag_dmi0_addr_i + connect \dmi0_din \jtag_dmi0_din + connect \dmi0_dout \jtag_dmi0_dout + connect \dmi0_req_i \jtag_dmi0_req_i + connect \dmi0_we_i \jtag_dmi0_we_i + connect \gpio_gpio0__core__i \gpio_gpio0__core__i + connect \gpio_gpio0__core__o \gpio_gpio0__core__o + connect \gpio_gpio0__core__oe \gpio_gpio0__core__oe + connect \gpio_gpio0__pad__i \gpio_gpio0__pad__i + connect \gpio_gpio0__pad__o \gpio_gpio0__pad__o + connect \gpio_gpio0__pad__oe \gpio_gpio0__pad__oe + connect \gpio_gpio10__core__i \gpio_gpio10__core__i + connect \gpio_gpio10__core__o \gpio_gpio10__core__o + connect \gpio_gpio10__core__oe \gpio_gpio10__core__oe + connect \gpio_gpio10__pad__i \gpio_gpio10__pad__i + connect \gpio_gpio10__pad__o \gpio_gpio10__pad__o + connect \gpio_gpio10__pad__oe \gpio_gpio10__pad__oe + connect \gpio_gpio11__core__i \gpio_gpio11__core__i + connect \gpio_gpio11__core__o \gpio_gpio11__core__o + connect \gpio_gpio11__core__oe \gpio_gpio11__core__oe + connect \gpio_gpio11__pad__i \gpio_gpio11__pad__i + connect \gpio_gpio11__pad__o \gpio_gpio11__pad__o + connect \gpio_gpio11__pad__oe \gpio_gpio11__pad__oe + connect \gpio_gpio12__core__i \gpio_gpio12__core__i + connect \gpio_gpio12__core__o \gpio_gpio12__core__o + connect \gpio_gpio12__core__oe \gpio_gpio12__core__oe + connect \gpio_gpio12__pad__i \gpio_gpio12__pad__i + connect \gpio_gpio12__pad__o \gpio_gpio12__pad__o + connect \gpio_gpio12__pad__oe \gpio_gpio12__pad__oe + connect \gpio_gpio13__core__i \gpio_gpio13__core__i + connect \gpio_gpio13__core__o \gpio_gpio13__core__o + connect \gpio_gpio13__core__oe \gpio_gpio13__core__oe + connect \gpio_gpio13__pad__i \gpio_gpio13__pad__i + connect \gpio_gpio13__pad__o \gpio_gpio13__pad__o + connect \gpio_gpio13__pad__oe \gpio_gpio13__pad__oe + connect \gpio_gpio14__core__i \gpio_gpio14__core__i + connect \gpio_gpio14__core__o \gpio_gpio14__core__o + connect \gpio_gpio14__core__oe \gpio_gpio14__core__oe + connect \gpio_gpio14__pad__i \gpio_gpio14__pad__i + connect \gpio_gpio14__pad__o \gpio_gpio14__pad__o + connect \gpio_gpio14__pad__oe \gpio_gpio14__pad__oe + connect \gpio_gpio15__core__i \gpio_gpio15__core__i + connect \gpio_gpio15__core__o \gpio_gpio15__core__o + connect \gpio_gpio15__core__oe \gpio_gpio15__core__oe + connect \gpio_gpio15__pad__i \gpio_gpio15__pad__i + connect \gpio_gpio15__pad__o \gpio_gpio15__pad__o + connect \gpio_gpio15__pad__oe \gpio_gpio15__pad__oe + connect \gpio_gpio1__core__i \gpio_gpio1__core__i + connect \gpio_gpio1__core__o \gpio_gpio1__core__o + connect \gpio_gpio1__core__oe \gpio_gpio1__core__oe + connect \gpio_gpio1__pad__i \gpio_gpio1__pad__i + connect \gpio_gpio1__pad__o \gpio_gpio1__pad__o + connect \gpio_gpio1__pad__oe \gpio_gpio1__pad__oe + connect \gpio_gpio2__core__i \gpio_gpio2__core__i + connect \gpio_gpio2__core__o \gpio_gpio2__core__o + connect \gpio_gpio2__core__oe \gpio_gpio2__core__oe + connect \gpio_gpio2__pad__i \gpio_gpio2__pad__i + connect \gpio_gpio2__pad__o \gpio_gpio2__pad__o + connect \gpio_gpio2__pad__oe \gpio_gpio2__pad__oe + connect \gpio_gpio3__core__i \gpio_gpio3__core__i + connect \gpio_gpio3__core__o \gpio_gpio3__core__o + connect \gpio_gpio3__core__oe \gpio_gpio3__core__oe + connect \gpio_gpio3__pad__i \gpio_gpio3__pad__i + connect \gpio_gpio3__pad__o \gpio_gpio3__pad__o + connect \gpio_gpio3__pad__oe \gpio_gpio3__pad__oe + connect \gpio_gpio4__core__i \gpio_gpio4__core__i + connect \gpio_gpio4__core__o \gpio_gpio4__core__o + connect \gpio_gpio4__core__oe \gpio_gpio4__core__oe + connect \gpio_gpio4__pad__i \gpio_gpio4__pad__i + connect \gpio_gpio4__pad__o \gpio_gpio4__pad__o + connect \gpio_gpio4__pad__oe \gpio_gpio4__pad__oe + connect \gpio_gpio5__core__i \gpio_gpio5__core__i + connect \gpio_gpio5__core__o \gpio_gpio5__core__o + connect \gpio_gpio5__core__oe \gpio_gpio5__core__oe + connect \gpio_gpio5__pad__i \gpio_gpio5__pad__i + connect \gpio_gpio5__pad__o \gpio_gpio5__pad__o + connect \gpio_gpio5__pad__oe \gpio_gpio5__pad__oe + connect \gpio_gpio6__core__i \gpio_gpio6__core__i + connect \gpio_gpio6__core__o \gpio_gpio6__core__o + connect \gpio_gpio6__core__oe \gpio_gpio6__core__oe + connect \gpio_gpio6__pad__i \gpio_gpio6__pad__i + connect \gpio_gpio6__pad__o \gpio_gpio6__pad__o + connect \gpio_gpio6__pad__oe \gpio_gpio6__pad__oe + connect \gpio_gpio7__core__i \gpio_gpio7__core__i + connect \gpio_gpio7__core__o \gpio_gpio7__core__o + connect \gpio_gpio7__core__oe \gpio_gpio7__core__oe + connect \gpio_gpio7__pad__i \gpio_gpio7__pad__i + connect \gpio_gpio7__pad__o \gpio_gpio7__pad__o + connect \gpio_gpio7__pad__oe \gpio_gpio7__pad__oe + connect \gpio_gpio8__core__i \gpio_gpio8__core__i + connect \gpio_gpio8__core__o \gpio_gpio8__core__o + connect \gpio_gpio8__core__oe \gpio_gpio8__core__oe + connect \gpio_gpio8__pad__i \gpio_gpio8__pad__i + connect \gpio_gpio8__pad__o \gpio_gpio8__pad__o + connect \gpio_gpio8__pad__oe \gpio_gpio8__pad__oe + connect \gpio_gpio9__core__i \gpio_gpio9__core__i + connect \gpio_gpio9__core__o \gpio_gpio9__core__o + connect \gpio_gpio9__core__oe \gpio_gpio9__core__oe + connect \gpio_gpio9__pad__i \gpio_gpio9__pad__i + connect \gpio_gpio9__pad__o \gpio_gpio9__pad__o + connect \gpio_gpio9__pad__oe \gpio_gpio9__pad__oe + connect \jtag_wb__ack \jtag_wb__ack + connect \jtag_wb__adr \jtag_wb__adr + connect \jtag_wb__cyc \jtag_wb__cyc + connect \jtag_wb__dat_r \jtag_wb__dat_r + connect \jtag_wb__dat_w \jtag_wb__dat_w + connect \jtag_wb__sel \jtag_wb__sel + connect \jtag_wb__stb \jtag_wb__stb + connect \jtag_wb__we \jtag_wb__we + connect \rst \rst + connect \uart_rx__core__i \uart_rx__core__i + connect \uart_rx__pad__i \uart_rx__pad__i + connect \uart_tx__core__o \uart_tx__core__o + connect \uart_tx__pad__o \uart_tx__pad__o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:180591.12-180605.4" + cell \xics_icp \xics_icp + connect \clk \clk + connect \core_irq_o \xics_icp_core_irq_o + connect \icp_wb__ack \icp_wb__ack + connect \icp_wb__adr \icp_wb__adr + connect \icp_wb__cyc \icp_wb__cyc + connect \icp_wb__dat_r \icp_wb__dat_r + connect \icp_wb__dat_w \icp_wb__dat_w + connect \icp_wb__sel \icp_wb__sel + connect \icp_wb__stb \icp_wb__stb + connect \icp_wb__we \icp_wb__we + connect \ics_i_pri \xics_icp_ics_i_pri + connect \ics_i_src \xics_icp_ics_i_src + connect \rst \rst + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:180606.12-180619.4" + cell \xics_ics \xics_ics + connect \clk \clk + connect \icp_o_pri \xics_ics_icp_o_pri + connect \icp_o_src \xics_ics_icp_o_src + connect \ics_wb__ack \ics_wb__ack + connect \ics_wb__adr \ics_wb__adr + connect \ics_wb__cyc \ics_wb__cyc + connect \ics_wb__dat_r \ics_wb__dat_r + connect \ics_wb__dat_w \ics_wb__dat_w + connect \ics_wb__stb \ics_wb__stb + connect \ics_wb__we \ics_wb__we + connect \int_level_i \int_level_i + connect \rst \rst + end + attribute \src "libresoc.v:178436.7-178436.20" + process $proc$libresoc.v:178436$13363 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:178570.13-178570.33" + process $proc$libresoc.v:178570$13364 + assign { } { } + assign $1\core_asmcode[7:0] 8'00000000 + sync always + sync init + update \core_asmcode $1\core_asmcode[7:0] + end + attribute \src "libresoc.v:178576.7-178576.34" + process $proc$libresoc.v:178576$13365 + assign { } { } + assign $0\core_bigendian_i$3[0:0]$13366 1'0 + sync always + sync init + update \core_bigendian_i$3 $0\core_bigendian_i$3[0:0]$13366 + end + attribute \src "libresoc.v:178584.14-178584.55" + process $proc$libresoc.v:178584$13367 + assign { } { } + assign $1\core_core_core_cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \core_core_core_cia $1\core_core_core_cia[63:0] + end + attribute \src "libresoc.v:178588.13-178588.41" + process $proc$libresoc.v:178588$13368 + assign { } { } + assign $1\core_core_core_cr_rd[7:0] 8'00000000 + sync always + sync init + update \core_core_core_cr_rd $1\core_core_core_cr_rd[7:0] + end + attribute \src "libresoc.v:178592.7-178592.37" + process $proc$libresoc.v:178592$13369 + assign { } { } + assign $1\core_core_core_cr_rd_ok[0:0] 1'0 + sync always + sync init + update \core_core_core_cr_rd_ok $1\core_core_core_cr_rd_ok[0:0] + end + attribute \src "libresoc.v:178596.13-178596.41" + process $proc$libresoc.v:178596$13370 + assign { } { } + assign $1\core_core_core_cr_wr[7:0] 8'00000000 + sync always + sync init + update \core_core_core_cr_wr $1\core_core_core_cr_wr[7:0] + end + attribute \src "libresoc.v:178613.14-178613.46" + process $proc$libresoc.v:178613$13371 + assign { } { } + assign $1\core_core_core_fn_unit[11:0] 12'000000000000 + sync always + sync init + update \core_core_core_fn_unit $1\core_core_core_fn_unit[11:0] + end + attribute \src "libresoc.v:178621.13-178621.46" + process $proc$libresoc.v:178621$13372 + assign { } { } + assign $1\core_core_core_input_carry[1:0] 2'00 + sync always + sync init + update \core_core_core_input_carry $1\core_core_core_input_carry[1:0] + end + attribute \src "libresoc.v:178625.14-178625.41" + process $proc$libresoc.v:178625$13373 + assign { } { } + assign $1\core_core_core_insn[31:0] 0 + sync always + sync init + update \core_core_core_insn $1\core_core_core_insn[31:0] + end + attribute \src "libresoc.v:178703.13-178703.45" + process $proc$libresoc.v:178703$13374 + assign { } { } + assign $1\core_core_core_insn_type[6:0] 7'0000000 + sync always + sync init + update \core_core_core_insn_type $1\core_core_core_insn_type[6:0] + end + attribute \src "libresoc.v:178707.7-178707.37" + process $proc$libresoc.v:178707$13375 + assign { } { } + assign $1\core_core_core_is_32bit[0:0] 1'0 + sync always + sync init + update \core_core_core_is_32bit $1\core_core_core_is_32bit[0:0] + end + attribute \src "libresoc.v:178711.14-178711.55" + process $proc$libresoc.v:178711$13376 + assign { } { } + assign $1\core_core_core_msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \core_core_core_msr $1\core_core_core_msr[63:0] + end + attribute \src "libresoc.v:178715.7-178715.31" + process $proc$libresoc.v:178715$13377 + assign { } { } + assign $1\core_core_core_oe[0:0] 1'0 + sync always + sync init + update \core_core_core_oe $1\core_core_core_oe[0:0] + end + attribute \src "libresoc.v:178719.7-178719.34" + process $proc$libresoc.v:178719$13378 + assign { } { } + assign $1\core_core_core_oe_ok[0:0] 1'0 + sync always + sync init + update \core_core_core_oe_ok $1\core_core_core_oe_ok[0:0] + end + attribute \src "libresoc.v:178723.7-178723.31" + process $proc$libresoc.v:178723$13379 + assign { } { } + assign $1\core_core_core_rc[0:0] 1'0 + sync always + sync init + update \core_core_core_rc $1\core_core_core_rc[0:0] + end + attribute \src "libresoc.v:178727.7-178727.34" + process $proc$libresoc.v:178727$13380 + assign { } { } + assign $1\core_core_core_rc_ok[0:0] 1'0 + sync always + sync init + update \core_core_core_rc_ok $1\core_core_core_rc_ok[0:0] + end + attribute \src "libresoc.v:178731.14-178731.48" + process $proc$libresoc.v:178731$13381 + assign { } { } + assign $1\core_core_core_trapaddr[12:0] 13'0000000000000 + sync always + sync init + update \core_core_core_trapaddr $1\core_core_core_trapaddr[12:0] + end + attribute \src "libresoc.v:178735.13-178735.44" + process $proc$libresoc.v:178735$13382 + assign { } { } + assign $1\core_core_core_traptype[6:0] 7'0000000 + sync always + sync init + update \core_core_core_traptype $1\core_core_core_traptype[6:0] + end + attribute \src "libresoc.v:178739.13-178739.36" + process $proc$libresoc.v:178739$13383 + assign { } { } + assign $1\core_core_cr_in1[2:0] 3'000 + sync always + sync init + update \core_core_cr_in1 $1\core_core_cr_in1[2:0] + end + attribute \src "libresoc.v:178743.7-178743.33" + process $proc$libresoc.v:178743$13384 + assign { } { } + assign $1\core_core_cr_in1_ok[0:0] 1'0 + sync always + sync init + update \core_core_cr_in1_ok $1\core_core_cr_in1_ok[0:0] + end + attribute \src "libresoc.v:178747.13-178747.36" + process $proc$libresoc.v:178747$13385 + assign { } { } + assign $1\core_core_cr_in2[2:0] 3'000 + sync always + sync init + update \core_core_cr_in2 $1\core_core_cr_in2[2:0] + end + attribute \src "libresoc.v:178749.13-178749.40" + process $proc$libresoc.v:178749$13386 + assign { } { } + assign $0\core_core_cr_in2$1[2:0]$13387 3'000 + sync always + sync init + update \core_core_cr_in2$1 $0\core_core_cr_in2$1[2:0]$13387 + end + attribute \src "libresoc.v:178755.7-178755.33" + process $proc$libresoc.v:178755$13388 + assign { } { } + assign $1\core_core_cr_in2_ok[0:0] 1'0 + sync always + sync init + update \core_core_cr_in2_ok $1\core_core_cr_in2_ok[0:0] + end + attribute \src "libresoc.v:178757.7-178757.37" + process $proc$libresoc.v:178757$13389 + assign { } { } + assign $0\core_core_cr_in2_ok$2[0:0]$13390 1'0 + sync always + sync init + update \core_core_cr_in2_ok$2 $0\core_core_cr_in2_ok$2[0:0]$13390 + end + attribute \src "libresoc.v:178763.13-178763.36" + process $proc$libresoc.v:178763$13391 + assign { } { } + assign $1\core_core_cr_out[2:0] 3'000 + sync always + sync init + update \core_core_cr_out $1\core_core_cr_out[2:0] + end + attribute \src "libresoc.v:178767.7-178767.32" + process $proc$libresoc.v:178767$13392 + assign { } { } + assign $1\core_core_cr_wr_ok[0:0] 1'0 + sync always + sync init + update \core_core_cr_wr_ok $1\core_core_cr_wr_ok[0:0] + end + attribute \src "libresoc.v:178771.13-178771.33" + process $proc$libresoc.v:178771$13393 + assign { } { } + assign $1\core_core_ea[4:0] 5'00000 + sync always + sync init + update \core_core_ea $1\core_core_ea[4:0] + end + attribute \src "libresoc.v:178775.13-178775.35" + process $proc$libresoc.v:178775$13394 + assign { } { } + assign $1\core_core_fast1[2:0] 3'000 + sync always + sync init + update \core_core_fast1 $1\core_core_fast1[2:0] + end + attribute \src "libresoc.v:178779.7-178779.32" + process $proc$libresoc.v:178779$13395 + assign { } { } + assign $1\core_core_fast1_ok[0:0] 1'0 + sync always + sync init + update \core_core_fast1_ok $1\core_core_fast1_ok[0:0] + end + attribute \src "libresoc.v:178783.13-178783.35" + process $proc$libresoc.v:178783$13396 + assign { } { } + assign $1\core_core_fast2[2:0] 3'000 + sync always + sync init + update \core_core_fast2 $1\core_core_fast2[2:0] + end + attribute \src "libresoc.v:178787.7-178787.32" + process $proc$libresoc.v:178787$13397 + assign { } { } + assign $1\core_core_fast2_ok[0:0] 1'0 + sync always + sync init + update \core_core_fast2_ok $1\core_core_fast2_ok[0:0] + end + attribute \src "libresoc.v:178791.13-178791.36" + process $proc$libresoc.v:178791$13398 + assign { } { } + assign $1\core_core_fasto1[2:0] 3'000 + sync always + sync init + update \core_core_fasto1 $1\core_core_fasto1[2:0] + end + attribute \src "libresoc.v:178795.13-178795.36" + process $proc$libresoc.v:178795$13399 + assign { } { } + assign $1\core_core_fasto2[2:0] 3'000 + sync always + sync init + update \core_core_fasto2 $1\core_core_fasto2[2:0] + end + attribute \src "libresoc.v:178799.7-178799.26" + process $proc$libresoc.v:178799$13400 + assign { } { } + assign $1\core_core_lk[0:0] 1'0 + sync always + sync init + update \core_core_lk $1\core_core_lk[0:0] + end + attribute \src "libresoc.v:178803.14-178803.49" + process $proc$libresoc.v:178803$13401 + assign { } { } + assign $1\core_core_pc[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \core_core_pc $1\core_core_pc[63:0] + end + attribute \src "libresoc.v:178807.13-178807.35" + process $proc$libresoc.v:178807$13402 + assign { } { } + assign $1\core_core_reg1[4:0] 5'00000 + sync always + sync init + update \core_core_reg1 $1\core_core_reg1[4:0] + end + attribute \src "libresoc.v:178811.7-178811.31" + process $proc$libresoc.v:178811$13403 + assign { } { } + assign $1\core_core_reg1_ok[0:0] 1'0 + sync always + sync init + update \core_core_reg1_ok $1\core_core_reg1_ok[0:0] + end + attribute \src "libresoc.v:178815.13-178815.35" + process $proc$libresoc.v:178815$13404 + assign { } { } + assign $1\core_core_reg2[4:0] 5'00000 + sync always + sync init + update \core_core_reg2 $1\core_core_reg2[4:0] + end + attribute \src "libresoc.v:178819.7-178819.31" + process $proc$libresoc.v:178819$13405 + assign { } { } + assign $1\core_core_reg2_ok[0:0] 1'0 + sync always + sync init + update \core_core_reg2_ok $1\core_core_reg2_ok[0:0] + end + attribute \src "libresoc.v:178823.13-178823.35" + process $proc$libresoc.v:178823$13406 + assign { } { } + assign $1\core_core_reg3[4:0] 5'00000 + sync always + sync init + update \core_core_reg3 $1\core_core_reg3[4:0] + end + attribute \src "libresoc.v:178827.7-178827.31" + process $proc$libresoc.v:178827$13407 + assign { } { } + assign $1\core_core_reg3_ok[0:0] 1'0 + sync always + sync init + update \core_core_reg3_ok $1\core_core_reg3_ok[0:0] + end + attribute \src "libresoc.v:178831.13-178831.35" + process $proc$libresoc.v:178831$13408 + assign { } { } + assign $1\core_core_rego[4:0] 5'00000 + sync always + sync init + update \core_core_rego $1\core_core_rego[4:0] + end + attribute \src "libresoc.v:178948.13-178948.37" + process $proc$libresoc.v:178948$13409 + assign { } { } + assign $1\core_core_spr1[9:0] 10'0000000000 + sync always + sync init + update \core_core_spr1 $1\core_core_spr1[9:0] + end + attribute \src "libresoc.v:178952.7-178952.31" + process $proc$libresoc.v:178952$13410 + assign { } { } + assign $1\core_core_spr1_ok[0:0] 1'0 + sync always + sync init + update \core_core_spr1_ok $1\core_core_spr1_ok[0:0] + end + attribute \src "libresoc.v:179067.13-179067.37" + process $proc$libresoc.v:179067$13411 + assign { } { } + assign $1\core_core_spro[9:0] 10'0000000000 + sync always + sync init + update \core_core_spro $1\core_core_spro[9:0] + end + attribute \src "libresoc.v:179073.13-179073.36" + process $proc$libresoc.v:179073$13412 + assign { } { } + assign $1\core_core_xer_in[2:0] 3'000 + sync always + sync init + update \core_core_xer_in $1\core_core_xer_in[2:0] + end + attribute \src "libresoc.v:179081.7-179081.28" + process $proc$libresoc.v:179081$13413 + assign { } { } + assign $1\core_cr_out_ok[0:0] 1'0 + sync always + sync init + update \core_cr_out_ok $1\core_cr_out_ok[0:0] + end + attribute \src "libresoc.v:179095.14-179095.45" + process $proc$libresoc.v:179095$13414 + assign { } { } + assign $1\core_dec[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \core_dec $1\core_dec[63:0] + end + attribute \src "libresoc.v:179105.7-179105.24" + process $proc$libresoc.v:179105$13415 + assign { } { } + assign $1\core_ea_ok[0:0] 1'0 + sync always + sync init + update \core_ea_ok $1\core_ea_ok[0:0] + end + attribute \src "libresoc.v:179109.7-179109.23" + process $proc$libresoc.v:179109$13416 + assign { } { } + assign $1\core_eint[0:0] 1'0 + sync always + sync init + update \core_eint $1\core_eint[0:0] + end + attribute \src "libresoc.v:179113.7-179113.28" + process $proc$libresoc.v:179113$13417 + assign { } { } + assign $1\core_fasto1_ok[0:0] 1'0 + sync always + sync init + update \core_fasto1_ok $1\core_fasto1_ok[0:0] + end + attribute \src "libresoc.v:179117.7-179117.28" + process $proc$libresoc.v:179117$13418 + assign { } { } + assign $1\core_fasto2_ok[0:0] 1'0 + sync always + sync init + update \core_fasto2_ok $1\core_fasto2_ok[0:0] + end + attribute \src "libresoc.v:179145.14-179145.45" + process $proc$libresoc.v:179145$13419 + assign { } { } + assign $1\core_msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \core_msr $1\core_msr[63:0] + end + attribute \src "libresoc.v:179153.14-179153.37" + process $proc$libresoc.v:179153$13420 + assign { } { } + assign $1\core_raw_insn_i[31:0] 0 + sync always + sync init + update \core_raw_insn_i $1\core_raw_insn_i[31:0] + end + attribute \src "libresoc.v:179157.7-179157.26" + process $proc$libresoc.v:179157$13421 + assign { } { } + assign $1\core_rego_ok[0:0] 1'0 + sync always + sync init + update \core_rego_ok $1\core_rego_ok[0:0] + end + attribute \src "libresoc.v:179161.7-179161.26" + process $proc$libresoc.v:179161$13422 + assign { } { } + assign $1\core_spro_ok[0:0] 1'0 + sync always + sync init + update \core_spro_ok $1\core_spro_ok[0:0] + end + attribute \src "libresoc.v:179171.7-179171.26" + process $proc$libresoc.v:179171$13423 + assign { } { } + assign $1\core_xer_out[0:0] 1'0 + sync always + sync init + update \core_xer_out $1\core_xer_out[0:0] + end + attribute \src "libresoc.v:179175.7-179175.30" + process $proc$libresoc.v:179175$13424 + assign { } { } + assign $1\cu_st__rel_o_dly[0:0] 1'0 + sync always + sync init + update \cu_st__rel_o_dly $1\cu_st__rel_o_dly[0:0] + end + attribute \src "libresoc.v:179181.7-179181.24" + process $proc$libresoc.v:179181$13425 + assign { } { } + assign $1\d_cr_delay[0:0] 1'0 + sync always + sync init + update \d_cr_delay $1\d_cr_delay[0:0] + end + attribute \src "libresoc.v:179185.7-179185.25" + process $proc$libresoc.v:179185$13426 + assign { } { } + assign $1\d_reg_delay[0:0] 1'0 + sync always + sync init + update \d_reg_delay $1\d_reg_delay[0:0] + end + attribute \src "libresoc.v:179189.7-179189.25" + process $proc$libresoc.v:179189$13427 + assign { } { } + assign $1\d_xer_delay[0:0] 1'0 + sync always + sync init + update \d_xer_delay $1\d_xer_delay[0:0] + end + attribute \src "libresoc.v:179225.13-179225.34" + process $proc$libresoc.v:179225$13428 + assign { } { } + assign $1\dbg_dmi_addr_i[3:0] 4'0000 + sync always + sync init + update \dbg_dmi_addr_i $1\dbg_dmi_addr_i[3:0] + end + attribute \src "libresoc.v:179229.14-179229.48" + process $proc$libresoc.v:179229$13429 + assign { } { } + assign $1\dbg_dmi_din[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \dbg_dmi_din $1\dbg_dmi_din[63:0] + end + attribute \src "libresoc.v:179235.7-179235.27" + process $proc$libresoc.v:179235$13430 + assign { } { } + assign $1\dbg_dmi_req_i[0:0] 1'0 + sync always + sync init + update \dbg_dmi_req_i $1\dbg_dmi_req_i[0:0] + end + attribute \src "libresoc.v:179239.7-179239.26" + process $proc$libresoc.v:179239$13431 + assign { } { } + assign $1\dbg_dmi_we_i[0:0] 1'0 + sync always + sync init + update \dbg_dmi_we_i $1\dbg_dmi_we_i[0:0] + end + attribute \src "libresoc.v:179297.14-179297.49" + process $proc$libresoc.v:179297$13432 + assign { } { } + assign $1\dec2_cur_dec[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \dec2_cur_dec $1\dec2_cur_dec[63:0] + end + attribute \src "libresoc.v:179301.7-179301.27" + process $proc$libresoc.v:179301$13433 + assign { } { } + assign $1\dec2_cur_eint[0:0] 1'0 + sync always + sync init + update \dec2_cur_eint $1\dec2_cur_eint[0:0] + end + attribute \src "libresoc.v:179305.14-179305.49" + process $proc$libresoc.v:179305$13434 + assign { } { } + assign $1\dec2_cur_msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \dec2_cur_msr $1\dec2_cur_msr[63:0] + end + attribute \src "libresoc.v:179309.14-179309.48" + process $proc$libresoc.v:179309$13435 + assign { } { } + assign $1\dec2_cur_pc[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \dec2_cur_pc $1\dec2_cur_pc[63:0] + end + attribute \src "libresoc.v:179702.13-179702.25" + process $proc$libresoc.v:179702$13436 + assign { } { } + assign $1\delay[1:0] 2'11 + sync always + sync init + update \delay $1\delay[1:0] + end + attribute \src "libresoc.v:179706.13-179706.29" + process $proc$libresoc.v:179706$13437 + assign { } { } + assign $1\fsm_state[1:0] 2'00 + sync always + sync init + update \fsm_state $1\fsm_state[1:0] + end + attribute \src "libresoc.v:179708.13-179708.35" + process $proc$libresoc.v:179708$13438 + assign { } { } + assign $0\fsm_state$117[1:0]$13439 2'00 + sync always + sync init + update \fsm_state$117 $0\fsm_state$117[1:0]$13439 + end + attribute \src "libresoc.v:179972.14-179972.28" + process $proc$libresoc.v:179972$13440 + assign { } { } + assign $1\ilatch[31:0] 0 + sync always + sync init + update \ilatch $1\ilatch[31:0] + end + attribute \src "libresoc.v:179988.7-179988.29" + process $proc$libresoc.v:179988$13441 + assign { } { } + assign $1\jtag_dmi0_ack_o[0:0] 1'0 + sync always + sync init + update \jtag_dmi0_ack_o $1\jtag_dmi0_ack_o[0:0] + end + attribute \src "libresoc.v:179996.14-179996.51" + process $proc$libresoc.v:179996$13442 + assign { } { } + assign $1\jtag_dmi0_dout[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \jtag_dmi0_dout $1\jtag_dmi0_dout[63:0] + end + attribute \src "libresoc.v:180024.7-180024.22" + process $proc$libresoc.v:180024$13443 + assign { } { } + assign $1\msr_read[0:0] 1'1 + sync always + sync init + update \msr_read $1\msr_read[0:0] + end + attribute \src "libresoc.v:180036.7-180036.24" + process $proc$libresoc.v:180036$13444 + assign { } { } + assign $1\pc_changed[0:0] 1'0 + sync always + sync init + update \pc_changed $1\pc_changed[0:0] + end + attribute \src "libresoc.v:180046.7-180046.25" + process $proc$libresoc.v:180046$13445 + assign { } { } + assign $1\pc_ok_delay[0:0] 1'0 + sync always + sync init + update \pc_ok_delay $1\pc_ok_delay[0:0] + end + attribute \src "libresoc.v:180127.3-180128.41" + process $proc$libresoc.v:180127$12919 + assign { } { } + assign $0\dec2_cur_dec[63:0] \dec2_cur_dec$next + sync posedge \clk + update \dec2_cur_dec $0\dec2_cur_dec[63:0] + end + attribute \src "libresoc.v:180129.3-180130.33" + process $proc$libresoc.v:180129$12920 + assign { } { } + assign $0\core_dec[63:0] \core_dec$next + sync posedge \clk + update \core_dec $0\core_dec[63:0] + end + attribute \src "libresoc.v:180131.3-180132.41" + process $proc$libresoc.v:180131$12921 + assign { } { } + assign $0\dec2_cur_msr[63:0] \dec2_cur_msr$next + sync posedge \clk + update \dec2_cur_msr $0\dec2_cur_msr[63:0] + end + attribute \src "libresoc.v:180133.3-180134.35" + process $proc$libresoc.v:180133$12922 + assign { } { } + assign $0\fsm_state[1:0] \fsm_state$next + sync posedge \clk + update \fsm_state $0\fsm_state[1:0] + end + attribute \src "libresoc.v:180135.3-180136.33" + process $proc$libresoc.v:180135$12923 + assign { } { } + assign $0\msr_read[0:0] \msr_read$next + sync posedge \clk + update \msr_read $0\msr_read[0:0] + end + attribute \src "libresoc.v:180137.3-180138.39" + process $proc$libresoc.v:180137$12924 + assign { } { } + assign $0\dec2_cur_pc[63:0] \dec2_cur_pc$next + sync posedge \clk + update \dec2_cur_pc $0\dec2_cur_pc[63:0] + end + attribute \src "libresoc.v:180139.3-180140.55" + process $proc$libresoc.v:180139$12925 + assign { } { } + assign $0\core_bigendian_i$3[0:0]$12926 \core_bigendian_i$3$next + sync posedge \clk + update \core_bigendian_i$3 $0\core_bigendian_i$3[0:0]$12926 + end + attribute \src "libresoc.v:180141.3-180142.47" + process $proc$libresoc.v:180141$12927 + assign { } { } + assign $0\core_raw_insn_i[31:0] \core_raw_insn_i$next + sync posedge \clk + update \core_raw_insn_i $0\core_raw_insn_i[31:0] + end + attribute \src "libresoc.v:180143.3-180144.41" + process $proc$libresoc.v:180143$12928 + assign { } { } + assign $0\core_asmcode[7:0] \core_asmcode$next + sync posedge \clk + update \core_asmcode $0\core_asmcode[7:0] + end + attribute \src "libresoc.v:180145.3-180146.45" + process $proc$libresoc.v:180145$12929 + assign { } { } + assign $0\core_core_rego[4:0] \core_core_rego$next + sync posedge \clk + update \core_core_rego $0\core_core_rego[4:0] + end + attribute \src "libresoc.v:180147.3-180148.41" + process $proc$libresoc.v:180147$12930 + assign { } { } + assign $0\core_rego_ok[0:0] \core_rego_ok$next + sync posedge \clk + update \core_rego_ok $0\core_rego_ok[0:0] + end + attribute \src "libresoc.v:180149.3-180150.45" + process $proc$libresoc.v:180149$12931 + assign { } { } + assign $0\fsm_state$117[1:0]$12932 \fsm_state$117$next + sync posedge \clk + update \fsm_state$117 $0\fsm_state$117[1:0]$12932 + end + attribute \src "libresoc.v:180151.3-180152.41" + process $proc$libresoc.v:180151$12933 + assign { } { } + assign $0\core_core_ea[4:0] \core_core_ea$next + sync posedge \clk + update \core_core_ea $0\core_core_ea[4:0] + end + attribute \src "libresoc.v:180153.3-180154.37" + process $proc$libresoc.v:180153$12934 + assign { } { } + assign $0\core_ea_ok[0:0] \core_ea_ok$next + sync posedge \clk + update \core_ea_ok $0\core_ea_ok[0:0] + end + attribute \src "libresoc.v:180155.3-180156.45" + process $proc$libresoc.v:180155$12935 + assign { } { } + assign $0\core_core_reg1[4:0] \core_core_reg1$next + sync posedge \clk + update \core_core_reg1 $0\core_core_reg1[4:0] + end + attribute \src "libresoc.v:180157.3-180158.51" + process $proc$libresoc.v:180157$12936 + assign { } { } + assign $0\core_core_reg1_ok[0:0] \core_core_reg1_ok$next + sync posedge \clk + update \core_core_reg1_ok $0\core_core_reg1_ok[0:0] + end + attribute \src "libresoc.v:180159.3-180160.45" + process $proc$libresoc.v:180159$12937 + assign { } { } + assign $0\core_core_reg2[4:0] \core_core_reg2$next + sync posedge \clk + update \core_core_reg2 $0\core_core_reg2[4:0] + end + attribute \src "libresoc.v:180161.3-180162.51" + process $proc$libresoc.v:180161$12938 + assign { } { } + assign $0\core_core_reg2_ok[0:0] \core_core_reg2_ok$next + sync posedge \clk + update \core_core_reg2_ok $0\core_core_reg2_ok[0:0] + end + attribute \src "libresoc.v:180163.3-180164.45" + process $proc$libresoc.v:180163$12939 + assign { } { } + assign $0\core_core_reg3[4:0] \core_core_reg3$next + sync posedge \clk + update \core_core_reg3 $0\core_core_reg3[4:0] + end + attribute \src "libresoc.v:180165.3-180166.51" + process $proc$libresoc.v:180165$12940 + assign { } { } + assign $0\core_core_reg3_ok[0:0] \core_core_reg3_ok$next + sync posedge \clk + update \core_core_reg3_ok $0\core_core_reg3_ok[0:0] + end + attribute \src "libresoc.v:180167.3-180168.45" + process $proc$libresoc.v:180167$12941 + assign { } { } + assign $0\core_core_spro[9:0] \core_core_spro$next + sync posedge \clk + update \core_core_spro $0\core_core_spro[9:0] + end + attribute \src "libresoc.v:180169.3-180170.41" + process $proc$libresoc.v:180169$12942 + assign { } { } + assign $0\core_spro_ok[0:0] \core_spro_ok$next + sync posedge \clk + update \core_spro_ok $0\core_spro_ok[0:0] + end + attribute \src "libresoc.v:180171.3-180172.39" + process $proc$libresoc.v:180171$12943 + assign { } { } + assign $0\d_xer_delay[0:0] \d_xer_delay$next + sync posedge \clk + update \d_xer_delay $0\d_xer_delay[0:0] + end + attribute \src "libresoc.v:180173.3-180174.45" + process $proc$libresoc.v:180173$12944 + assign { } { } + assign $0\core_core_spr1[9:0] \core_core_spr1$next + sync posedge \clk + update \core_core_spr1 $0\core_core_spr1[9:0] + end + attribute \src "libresoc.v:180175.3-180176.51" + process $proc$libresoc.v:180175$12945 + assign { } { } + assign $0\core_core_spr1_ok[0:0] \core_core_spr1_ok$next + sync posedge \clk + update \core_core_spr1_ok $0\core_core_spr1_ok[0:0] + end + attribute \src "libresoc.v:180177.3-180178.49" + process $proc$libresoc.v:180177$12946 + assign { } { } + assign $0\core_core_xer_in[2:0] \core_core_xer_in$next + sync posedge \clk + update \core_core_xer_in $0\core_core_xer_in[2:0] + end + attribute \src "libresoc.v:180179.3-180180.41" + process $proc$libresoc.v:180179$12947 + assign { } { } + assign $0\core_xer_out[0:0] \core_xer_out$next + sync posedge \clk + update \core_xer_out $0\core_xer_out[0:0] + end + attribute \src "libresoc.v:180181.3-180182.47" + process $proc$libresoc.v:180181$12948 + assign { } { } + assign $0\core_core_fast1[2:0] \core_core_fast1$next + sync posedge \clk + update \core_core_fast1 $0\core_core_fast1[2:0] + end + attribute \src "libresoc.v:180183.3-180184.53" + process $proc$libresoc.v:180183$12949 + assign { } { } + assign $0\core_core_fast1_ok[0:0] \core_core_fast1_ok$next + sync posedge \clk + update \core_core_fast1_ok $0\core_core_fast1_ok[0:0] + end + attribute \src "libresoc.v:180185.3-180186.47" + process $proc$libresoc.v:180185$12950 + assign { } { } + assign $0\core_core_fast2[2:0] \core_core_fast2$next + sync posedge \clk + update \core_core_fast2 $0\core_core_fast2[2:0] + end + attribute \src "libresoc.v:180187.3-180188.53" + process $proc$libresoc.v:180187$12951 + assign { } { } + assign $0\core_core_fast2_ok[0:0] \core_core_fast2_ok$next + sync posedge \clk + update \core_core_fast2_ok $0\core_core_fast2_ok[0:0] + end + attribute \src "libresoc.v:180189.3-180190.49" + process $proc$libresoc.v:180189$12952 + assign { } { } + assign $0\core_core_fasto1[2:0] \core_core_fasto1$next + sync posedge \clk + update \core_core_fasto1 $0\core_core_fasto1[2:0] + end + attribute \src "libresoc.v:180191.3-180192.45" + process $proc$libresoc.v:180191$12953 + assign { } { } + assign $0\core_fasto1_ok[0:0] \core_fasto1_ok$next + sync posedge \clk + update \core_fasto1_ok $0\core_fasto1_ok[0:0] + end + attribute \src "libresoc.v:180193.3-180194.37" + process $proc$libresoc.v:180193$12954 + assign { } { } + assign $0\d_cr_delay[0:0] \d_cr_delay$next + sync posedge \clk + update \d_cr_delay $0\d_cr_delay[0:0] + end + attribute \src "libresoc.v:180195.3-180196.49" + process $proc$libresoc.v:180195$12955 + assign { } { } + assign $0\core_core_fasto2[2:0] \core_core_fasto2$next + sync posedge \clk + update \core_core_fasto2 $0\core_core_fasto2[2:0] + end + attribute \src "libresoc.v:180197.3-180198.45" + process $proc$libresoc.v:180197$12956 + assign { } { } + assign $0\core_fasto2_ok[0:0] \core_fasto2_ok$next + sync posedge \clk + update \core_fasto2_ok $0\core_fasto2_ok[0:0] + end + attribute \src "libresoc.v:180199.3-180200.49" + process $proc$libresoc.v:180199$12957 + assign { } { } + assign $0\core_core_cr_in1[2:0] \core_core_cr_in1$next + sync posedge \clk + update \core_core_cr_in1 $0\core_core_cr_in1[2:0] + end + attribute \src "libresoc.v:180201.3-180202.55" + process $proc$libresoc.v:180201$12958 + assign { } { } + assign $0\core_core_cr_in1_ok[0:0] \core_core_cr_in1_ok$next + sync posedge \clk + update \core_core_cr_in1_ok $0\core_core_cr_in1_ok[0:0] + end + attribute \src "libresoc.v:180203.3-180204.49" + process $proc$libresoc.v:180203$12959 + assign { } { } + assign $0\core_core_cr_in2[2:0] \core_core_cr_in2$next + sync posedge \clk + update \core_core_cr_in2 $0\core_core_cr_in2[2:0] + end + attribute \src "libresoc.v:180205.3-180206.55" + process $proc$libresoc.v:180205$12960 + assign { } { } + assign $0\core_core_cr_in2_ok[0:0] \core_core_cr_in2_ok$next + sync posedge \clk + update \core_core_cr_in2_ok $0\core_core_cr_in2_ok[0:0] + end + attribute \src "libresoc.v:180207.3-180208.55" + process $proc$libresoc.v:180207$12961 + assign { } { } + assign $0\core_core_cr_in2$1[2:0]$12962 \core_core_cr_in2$1$next + sync posedge \clk + update \core_core_cr_in2$1 $0\core_core_cr_in2$1[2:0]$12962 + end + attribute \src "libresoc.v:180209.3-180210.61" + process $proc$libresoc.v:180209$12963 + assign { } { } + assign $0\core_core_cr_in2_ok$2[0:0]$12964 \core_core_cr_in2_ok$2$next + sync posedge \clk + update \core_core_cr_in2_ok$2 $0\core_core_cr_in2_ok$2[0:0]$12964 + end + attribute \src "libresoc.v:180211.3-180212.49" + process $proc$libresoc.v:180211$12965 + assign { } { } + assign $0\core_core_cr_out[2:0] \core_core_cr_out$next + sync posedge \clk + update \core_core_cr_out $0\core_core_cr_out[2:0] + end + attribute \src "libresoc.v:180213.3-180214.45" + process $proc$libresoc.v:180213$12966 + assign { } { } + assign $0\core_cr_out_ok[0:0] \core_cr_out_ok$next + sync posedge \clk + update \core_cr_out_ok $0\core_cr_out_ok[0:0] + end + attribute \src "libresoc.v:180215.3-180216.39" + process $proc$libresoc.v:180215$12967 + assign { } { } + assign $0\d_reg_delay[0:0] \d_reg_delay$next + sync posedge \clk + update \d_reg_delay $0\d_reg_delay[0:0] + end + attribute \src "libresoc.v:180217.3-180218.53" + process $proc$libresoc.v:180217$12968 + assign { } { } + assign $0\core_core_core_msr[63:0] \core_core_core_msr$next + sync posedge \clk + update \core_core_core_msr $0\core_core_core_msr[63:0] + end + attribute \src "libresoc.v:180219.3-180220.53" + process $proc$libresoc.v:180219$12969 + assign { } { } + assign $0\core_core_core_cia[63:0] \core_core_core_cia$next + sync posedge \clk + update \core_core_core_cia $0\core_core_core_cia[63:0] + end + attribute \src "libresoc.v:180221.3-180222.55" + process $proc$libresoc.v:180221$12970 + assign { } { } + assign $0\core_core_core_insn[31:0] \core_core_core_insn$next + sync posedge \clk + update \core_core_core_insn $0\core_core_core_insn[31:0] + end + attribute \src "libresoc.v:180223.3-180224.65" + process $proc$libresoc.v:180223$12971 + assign { } { } + assign $0\core_core_core_insn_type[6:0] \core_core_core_insn_type$next + sync posedge \clk + update \core_core_core_insn_type $0\core_core_core_insn_type[6:0] + end + attribute \src "libresoc.v:180225.3-180226.61" + process $proc$libresoc.v:180225$12972 + assign { } { } + assign $0\core_core_core_fn_unit[11:0] \core_core_core_fn_unit$next + sync posedge \clk + update \core_core_core_fn_unit $0\core_core_core_fn_unit[11:0] + end + attribute \src "libresoc.v:180227.3-180228.41" + process $proc$libresoc.v:180227$12973 + assign { } { } + assign $0\core_core_lk[0:0] \core_core_lk$next + sync posedge \clk + update \core_core_lk $0\core_core_lk[0:0] + end + attribute \src "libresoc.v:180229.3-180230.51" + process $proc$libresoc.v:180229$12974 + assign { } { } + assign $0\core_core_core_rc[0:0] \core_core_core_rc$next + sync posedge \clk + update \core_core_core_rc $0\core_core_core_rc[0:0] + end + attribute \src "libresoc.v:180231.3-180232.57" + process $proc$libresoc.v:180231$12975 + assign { } { } + assign $0\core_core_core_rc_ok[0:0] \core_core_core_rc_ok$next + sync posedge \clk + update \core_core_core_rc_ok $0\core_core_core_rc_ok[0:0] + end + attribute \src "libresoc.v:180233.3-180234.51" + process $proc$libresoc.v:180233$12976 + assign { } { } + assign $0\core_core_core_oe[0:0] \core_core_core_oe$next + sync posedge \clk + update \core_core_core_oe $0\core_core_core_oe[0:0] + end + attribute \src "libresoc.v:180235.3-180236.57" + process $proc$libresoc.v:180235$12977 + assign { } { } + assign $0\core_core_core_oe_ok[0:0] \core_core_core_oe_ok$next + sync posedge \clk + update \core_core_core_oe_ok $0\core_core_core_oe_ok[0:0] + end + attribute \src "libresoc.v:180237.3-180238.29" + process $proc$libresoc.v:180237$12978 + assign { } { } + assign $0\ilatch[31:0] \ilatch$next + sync posedge \clk + update \ilatch $0\ilatch[31:0] + end + attribute \src "libresoc.v:180239.3-180240.69" + process $proc$libresoc.v:180239$12979 + assign { } { } + assign $0\core_core_core_input_carry[1:0] \core_core_core_input_carry$next + sync posedge \clk + update \core_core_core_input_carry $0\core_core_core_input_carry[1:0] + end + attribute \src "libresoc.v:180241.3-180242.63" + process $proc$libresoc.v:180241$12980 + assign { } { } + assign $0\core_core_core_traptype[6:0] \core_core_core_traptype$next + sync posedge \clk + update \core_core_core_traptype $0\core_core_core_traptype[6:0] + end + attribute \src "libresoc.v:180243.3-180244.63" + process $proc$libresoc.v:180243$12981 + assign { } { } + assign $0\core_core_core_trapaddr[12:0] \core_core_core_trapaddr$next + sync posedge \clk + update \core_core_core_trapaddr $0\core_core_core_trapaddr[12:0] + end + attribute \src "libresoc.v:180245.3-180246.57" + process $proc$libresoc.v:180245$12982 + assign { } { } + assign $0\core_core_core_cr_rd[7:0] \core_core_core_cr_rd$next + sync posedge \clk + update \core_core_core_cr_rd $0\core_core_core_cr_rd[7:0] + end + attribute \src "libresoc.v:180247.3-180248.63" + process $proc$libresoc.v:180247$12983 + assign { } { } + assign $0\core_core_core_cr_rd_ok[0:0] \core_core_core_cr_rd_ok$next + sync posedge \clk + update \core_core_core_cr_rd_ok $0\core_core_core_cr_rd_ok[0:0] + end + attribute \src "libresoc.v:180249.3-180250.57" + process $proc$libresoc.v:180249$12984 + assign { } { } + assign $0\core_core_core_cr_wr[7:0] \core_core_core_cr_wr$next + sync posedge \clk + update \core_core_core_cr_wr $0\core_core_core_cr_wr[7:0] + end + attribute \src "libresoc.v:180251.3-180252.53" + process $proc$libresoc.v:180251$12985 + assign { } { } + assign $0\core_core_cr_wr_ok[0:0] \core_core_cr_wr_ok$next + sync posedge \clk + update \core_core_cr_wr_ok $0\core_core_cr_wr_ok[0:0] + end + attribute \src "libresoc.v:180253.3-180254.63" + process $proc$libresoc.v:180253$12986 + assign { } { } + assign $0\core_core_core_is_32bit[0:0] \core_core_core_is_32bit$next + sync posedge \clk + update \core_core_core_is_32bit $0\core_core_core_is_32bit[0:0] + end + attribute \src "libresoc.v:180255.3-180256.37" + process $proc$libresoc.v:180255$12987 + assign { } { } + assign $0\pc_changed[0:0] \pc_changed$next + sync posedge \clk + update \pc_changed $0\pc_changed[0:0] + end + attribute \src "libresoc.v:180257.3-180258.39" + process $proc$libresoc.v:180257$12988 + assign { } { } + assign $0\pc_ok_delay[0:0] \pc_ok_delay$next + sync posedge \clk + update \pc_ok_delay $0\pc_ok_delay[0:0] + end + attribute \src "libresoc.v:180259.3-180260.41" + process $proc$libresoc.v:180259$12989 + assign { } { } + assign $0\core_core_pc[63:0] \core_core_pc$next + sync posedge \clk + update \core_core_pc $0\core_core_pc[63:0] + end + attribute \src "libresoc.v:180261.3-180262.43" + process $proc$libresoc.v:180261$12990 + assign { } { } + assign $0\cu_st__rel_o_dly[0:0] \core_cu_st__rel_o + sync posedge \clk + update \cu_st__rel_o_dly $0\cu_st__rel_o_dly[0:0] + end + attribute \src "libresoc.v:180263.3-180264.27" + process $proc$libresoc.v:180263$12991 + assign { } { } + assign $0\delay[1:0] \delay$next + sync posedge \por_clk + update \delay $0\delay[1:0] + end + attribute \src "libresoc.v:180265.3-180266.43" + process $proc$libresoc.v:180265$12992 + assign { } { } + assign $0\dec2_cur_eint[0:0] \dec2_cur_eint$next + sync posedge \clk + update \dec2_cur_eint $0\dec2_cur_eint[0:0] + end + attribute \src "libresoc.v:180267.3-180268.45" + process $proc$libresoc.v:180267$12993 + assign { } { } + assign $0\jtag_dmi0_dout[63:0] \jtag_dmi0_dout$next + sync posedge \clk + update \jtag_dmi0_dout $0\jtag_dmi0_dout[63:0] + end + attribute \src "libresoc.v:180269.3-180270.47" + process $proc$libresoc.v:180269$12994 + assign { } { } + assign $0\jtag_dmi0_ack_o[0:0] \jtag_dmi0_ack_o$next + sync posedge \clk + update \jtag_dmi0_ack_o $0\jtag_dmi0_ack_o[0:0] + end + attribute \src "libresoc.v:180271.3-180272.39" + process $proc$libresoc.v:180271$12995 + assign { } { } + assign $0\dbg_dmi_din[63:0] \dbg_dmi_din$next + sync posedge \clk + update \dbg_dmi_din $0\dbg_dmi_din[63:0] + end + attribute \src "libresoc.v:180273.3-180274.41" + process $proc$libresoc.v:180273$12996 + assign { } { } + assign $0\dbg_dmi_we_i[0:0] \dbg_dmi_we_i$next + sync posedge \clk + update \dbg_dmi_we_i $0\dbg_dmi_we_i[0:0] + end + attribute \src "libresoc.v:180275.3-180276.43" + process $proc$libresoc.v:180275$12997 + assign { } { } + assign $0\dbg_dmi_req_i[0:0] \dbg_dmi_req_i$next + sync posedge \clk + update \dbg_dmi_req_i $0\dbg_dmi_req_i[0:0] + end + attribute \src "libresoc.v:180277.3-180278.45" + process $proc$libresoc.v:180277$12998 + assign { } { } + assign $0\dbg_dmi_addr_i[3:0] \dbg_dmi_addr_i$next + sync posedge \clk + update \dbg_dmi_addr_i $0\dbg_dmi_addr_i[3:0] + end + attribute \src "libresoc.v:180279.3-180280.33" + process $proc$libresoc.v:180279$12999 + assign { } { } + assign $0\core_msr[63:0] \core_msr$next + sync posedge \clk + update \core_msr $0\core_msr[63:0] + end + attribute \src "libresoc.v:180281.3-180282.35" + process $proc$libresoc.v:180281$13000 + assign { } { } + assign $0\core_eint[0:0] \core_eint$next + sync posedge \clk + update \core_eint $0\core_eint[0:0] + end + attribute \src "libresoc.v:180620.3-180628.6" + process $proc$libresoc.v:180620$13001 + assign { } { } + assign { } { } + assign $0\dbg_dmi_addr_i$next[3:0]$13002 $1\dbg_dmi_addr_i$next[3:0]$13003 + attribute \src "libresoc.v:180621.5-180621.29" + switch \initial + attribute \src "libresoc.v:180621.9-180621.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dbg_dmi_addr_i$next[3:0]$13003 4'0000 + case + assign $1\dbg_dmi_addr_i$next[3:0]$13003 \jtag_dmi0_addr_i + end + sync always + update \dbg_dmi_addr_i$next $0\dbg_dmi_addr_i$next[3:0]$13002 + end + attribute \src "libresoc.v:180629.3-180637.6" + process $proc$libresoc.v:180629$13004 + assign { } { } + assign { } { } + assign $0\dbg_dmi_req_i$next[0:0]$13005 $1\dbg_dmi_req_i$next[0:0]$13006 + attribute \src "libresoc.v:180630.5-180630.29" + switch \initial + attribute \src "libresoc.v:180630.9-180630.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dbg_dmi_req_i$next[0:0]$13006 1'0 + case + assign $1\dbg_dmi_req_i$next[0:0]$13006 \jtag_dmi0_req_i + end + sync always + update \dbg_dmi_req_i$next $0\dbg_dmi_req_i$next[0:0]$13005 + end + attribute \src "libresoc.v:180638.3-180648.6" + process $proc$libresoc.v:180638$13007 + assign { } { } + assign { } { } + assign $0\core_issue_i[0:0] $1\core_issue_i[0:0] + attribute \src "libresoc.v:180639.5-180639.29" + switch \initial + attribute \src "libresoc.v:180639.9-180639.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:225" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\core_issue_i[0:0] 1'1 + case + assign $1\core_issue_i[0:0] 1'0 + end + sync always + update \core_issue_i $0\core_issue_i[0:0] + end + attribute \src "libresoc.v:180649.3-180658.6" + process $proc$libresoc.v:180649$13008 + assign { } { } + assign { } { } + assign $0\core_dmi__addr[4:0] $1\core_dmi__addr[4:0] + attribute \src "libresoc.v:180650.5-180650.29" + switch \initial + attribute \src "libresoc.v:180650.9-180650.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:305" + switch \dbg_d_gpr_req + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\core_dmi__addr[4:0] \dbg_d_gpr_addr [4:0] + case + assign $1\core_dmi__addr[4:0] 5'00000 + end + sync always + update \core_dmi__addr $0\core_dmi__addr[4:0] + end + attribute \src "libresoc.v:180659.3-180668.6" + process $proc$libresoc.v:180659$13009 + assign { } { } + assign { } { } + assign $0\core_dmi__ren[0:0] $1\core_dmi__ren[0:0] + attribute \src "libresoc.v:180660.5-180660.29" + switch \initial + attribute \src "libresoc.v:180660.9-180660.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:305" + switch \dbg_d_gpr_req + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\core_dmi__ren[0:0] 1'1 + case + assign $1\core_dmi__ren[0:0] 1'0 + end + sync always + update \core_dmi__ren $0\core_dmi__ren[0:0] + end + attribute \src "libresoc.v:180669.3-180677.6" + process $proc$libresoc.v:180669$13010 + assign { } { } + assign { } { } + assign $0\d_reg_delay$next[0:0]$13011 $1\d_reg_delay$next[0:0]$13012 + attribute \src "libresoc.v:180670.5-180670.29" + switch \initial + attribute \src "libresoc.v:180670.9-180670.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\d_reg_delay$next[0:0]$13012 1'0 + case + assign $1\d_reg_delay$next[0:0]$13012 \dbg_d_gpr_req + end + sync always + update \d_reg_delay$next $0\d_reg_delay$next[0:0]$13011 + end + attribute \src "libresoc.v:180678.3-180687.6" + process $proc$libresoc.v:180678$13013 + assign { } { } + assign { } { } + assign $0\dbg_d_gpr_data[63:0] $1\dbg_d_gpr_data[63:0] + attribute \src "libresoc.v:180679.5-180679.29" + switch \initial + attribute \src "libresoc.v:180679.9-180679.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:315" + switch \d_reg_delay + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dbg_d_gpr_data[63:0] \core_dmi__data_o + case + assign $1\dbg_d_gpr_data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \dbg_d_gpr_data $0\dbg_d_gpr_data[63:0] + end + attribute \src "libresoc.v:180688.3-180697.6" + process $proc$libresoc.v:180688$13014 + assign { } { } + assign { } { } + assign $0\dbg_d_gpr_ack[0:0] $1\dbg_d_gpr_ack[0:0] + attribute \src "libresoc.v:180689.5-180689.29" + switch \initial + attribute \src "libresoc.v:180689.9-180689.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:315" + switch \d_reg_delay + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dbg_d_gpr_ack[0:0] 1'1 + case + assign $1\dbg_d_gpr_ack[0:0] 1'0 + end + sync always + update \dbg_d_gpr_ack $0\dbg_d_gpr_ack[0:0] + end + attribute \src "libresoc.v:180698.3-180707.6" + process $proc$libresoc.v:180698$13015 + assign { } { } + assign { } { } + assign $0\core_full_rd2__ren[7:0] $1\core_full_rd2__ren[7:0] + attribute \src "libresoc.v:180699.5-180699.29" + switch \initial + attribute \src "libresoc.v:180699.9-180699.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:321" + switch \dbg_d_cr_req + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\core_full_rd2__ren[7:0] 8'11111111 + case + assign $1\core_full_rd2__ren[7:0] 8'00000000 + end + sync always + update \core_full_rd2__ren $0\core_full_rd2__ren[7:0] + end + attribute \src "libresoc.v:180708.3-180716.6" + process $proc$libresoc.v:180708$13016 + assign { } { } + assign { } { } + assign $0\d_cr_delay$next[0:0]$13017 $1\d_cr_delay$next[0:0]$13018 + attribute \src "libresoc.v:180709.5-180709.29" + switch \initial + attribute \src "libresoc.v:180709.9-180709.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\d_cr_delay$next[0:0]$13018 1'0 + case + assign $1\d_cr_delay$next[0:0]$13018 \dbg_d_cr_req + end + sync always + update \d_cr_delay$next $0\d_cr_delay$next[0:0]$13017 + end + attribute \src "libresoc.v:180717.3-180726.6" + process $proc$libresoc.v:180717$13019 + assign { } { } + assign { } { } + assign $0\dbg_d_cr_data[63:0] $1\dbg_d_cr_data[63:0] + attribute \src "libresoc.v:180718.5-180718.29" + switch \initial + attribute \src "libresoc.v:180718.9-180718.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:325" + switch \d_cr_delay + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dbg_d_cr_data[63:0] \$113 + case + assign $1\dbg_d_cr_data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \dbg_d_cr_data $0\dbg_d_cr_data[63:0] + end + attribute \src "libresoc.v:180727.3-180736.6" + process $proc$libresoc.v:180727$13020 + assign { } { } + assign { } { } + assign $0\dbg_d_cr_ack[0:0] $1\dbg_d_cr_ack[0:0] + attribute \src "libresoc.v:180728.5-180728.29" + switch \initial + attribute \src "libresoc.v:180728.9-180728.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:325" + switch \d_cr_delay + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dbg_d_cr_ack[0:0] 1'1 + case + assign $1\dbg_d_cr_ack[0:0] 1'0 + end + sync always + update \dbg_d_cr_ack $0\dbg_d_cr_ack[0:0] + end + attribute \src "libresoc.v:180737.3-180746.6" + process $proc$libresoc.v:180737$13021 + assign { } { } + assign { } { } + assign $0\core_full_rd__ren[2:0] $1\core_full_rd__ren[2:0] + attribute \src "libresoc.v:180738.5-180738.29" + switch \initial + attribute \src "libresoc.v:180738.9-180738.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:331" + switch \dbg_d_xer_req + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\core_full_rd__ren[2:0] 3'111 + case + assign $1\core_full_rd__ren[2:0] 3'000 + end + sync always + update \core_full_rd__ren $0\core_full_rd__ren[2:0] + end + attribute \src "libresoc.v:180747.3-180755.6" + process $proc$libresoc.v:180747$13022 + assign { } { } + assign { } { } + assign $0\d_xer_delay$next[0:0]$13023 $1\d_xer_delay$next[0:0]$13024 + attribute \src "libresoc.v:180748.5-180748.29" + switch \initial + attribute \src "libresoc.v:180748.9-180748.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\d_xer_delay$next[0:0]$13024 1'0 + case + assign $1\d_xer_delay$next[0:0]$13024 \dbg_d_xer_req + end + sync always + update \d_xer_delay$next $0\d_xer_delay$next[0:0]$13023 + end + attribute \src "libresoc.v:180756.3-180765.6" + process $proc$libresoc.v:180756$13025 + assign { } { } + assign { } { } + assign $0\dbg_d_xer_data[63:0] $1\dbg_d_xer_data[63:0] + attribute \src "libresoc.v:180757.5-180757.29" + switch \initial + attribute \src "libresoc.v:180757.9-180757.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:335" + switch \d_xer_delay + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dbg_d_xer_data[63:0] \$115 + case + assign $1\dbg_d_xer_data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \dbg_d_xer_data $0\dbg_d_xer_data[63:0] + end + attribute \src "libresoc.v:180766.3-180775.6" + process $proc$libresoc.v:180766$13026 + assign { } { } + assign { } { } + assign $0\dbg_d_xer_ack[0:0] $1\dbg_d_xer_ack[0:0] + attribute \src "libresoc.v:180767.5-180767.29" + switch \initial + attribute \src "libresoc.v:180767.9-180767.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:335" + switch \d_xer_delay + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dbg_d_xer_ack[0:0] 1'1 + case + assign $1\dbg_d_xer_ack[0:0] 1'0 + end + sync always + update \dbg_d_xer_ack $0\dbg_d_xer_ack[0:0] + end + attribute \src "libresoc.v:180776.3-180790.6" + process $proc$libresoc.v:180776$13027 + assign { } { } + assign { } { } + assign $0\core_issue__addr[2:0] $1\core_issue__addr[2:0] + attribute \src "libresoc.v:180777.5-180777.29" + switch \initial + attribute \src "libresoc.v:180777.9-180777.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:361" + switch \fsm_state$117 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\core_issue__addr[2:0] 3'110 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\core_issue__addr[2:0] 3'111 + case + assign $1\core_issue__addr[2:0] 3'000 + end + sync always + update \core_issue__addr $0\core_issue__addr[2:0] + end + attribute \src "libresoc.v:180791.3-180805.6" + process $proc$libresoc.v:180791$13028 + assign { } { } + assign { } { } + assign $0\core_issue__ren[0:0] $1\core_issue__ren[0:0] + attribute \src "libresoc.v:180792.5-180792.29" + switch \initial + attribute \src "libresoc.v:180792.9-180792.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:361" + switch \fsm_state$117 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\core_issue__ren[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\core_issue__ren[0:0] 1'1 + case + assign $1\core_issue__ren[0:0] 1'0 + end + sync always + update \core_issue__ren $0\core_issue__ren[0:0] + end + attribute \src "libresoc.v:180806.3-180833.6" + process $proc$libresoc.v:180806$13029 + assign { } { } + assign { } { } + assign { } { } + assign $0\fsm_state$117$next[1:0]$13030 $2\fsm_state$117$next[1:0]$13032 + attribute \src "libresoc.v:180807.5-180807.29" + switch \initial + attribute \src "libresoc.v:180807.9-180807.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:361" + switch \fsm_state$117 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\fsm_state$117$next[1:0]$13031 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\fsm_state$117$next[1:0]$13031 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\fsm_state$117$next[1:0]$13031 2'11 + attribute \src "libresoc.v:0.0-0.0" + case 2'11 + assign { } { } + assign $1\fsm_state$117$next[1:0]$13031 2'00 + case + assign $1\fsm_state$117$next[1:0]$13031 \fsm_state$117 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\fsm_state$117$next[1:0]$13032 2'00 + case + assign $2\fsm_state$117$next[1:0]$13032 $1\fsm_state$117$next[1:0]$13031 + end + sync always + update \fsm_state$117$next $0\fsm_state$117$next[1:0]$13030 + end + attribute \src "libresoc.v:180834.3-180844.6" + process $proc$libresoc.v:180834$13033 + assign { } { } + assign { } { } + assign $0\new_dec[63:0] $1\new_dec[63:0] + attribute \src "libresoc.v:180835.5-180835.29" + switch \initial + attribute \src "libresoc.v:180835.9-180835.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:361" + switch \fsm_state$117 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\new_dec[63:0] \$118 [63:0] + case + assign $1\new_dec[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \new_dec $0\new_dec[63:0] + end + attribute \src "libresoc.v:180845.3-180859.6" + process $proc$libresoc.v:180845$13034 + assign { } { } + assign { } { } + assign $0\core_issue__addr$4[2:0]$13035 $1\core_issue__addr$4[2:0]$13036 + attribute \src "libresoc.v:180846.5-180846.29" + switch \initial + attribute \src "libresoc.v:180846.9-180846.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:361" + switch \fsm_state$117 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\core_issue__addr$4[2:0]$13036 3'110 + attribute \src "libresoc.v:0.0-0.0" + case 2'11 + assign { } { } + assign $1\core_issue__addr$4[2:0]$13036 3'111 + case + assign $1\core_issue__addr$4[2:0]$13036 3'000 + end + sync always + update \core_issue__addr$4 $0\core_issue__addr$4[2:0]$13035 + end + attribute \src "libresoc.v:180860.3-180874.6" + process $proc$libresoc.v:180860$13037 + assign { } { } + assign { } { } + assign $0\core_issue__wen[0:0] $1\core_issue__wen[0:0] + attribute \src "libresoc.v:180861.5-180861.29" + switch \initial + attribute \src "libresoc.v:180861.9-180861.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:361" + switch \fsm_state$117 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\core_issue__wen[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'11 + assign { } { } + assign $1\core_issue__wen[0:0] 1'1 + case + assign $1\core_issue__wen[0:0] 1'0 + end + sync always + update \core_issue__wen $0\core_issue__wen[0:0] + end + attribute \src "libresoc.v:180875.3-180889.6" + process $proc$libresoc.v:180875$13038 + assign { } { } + assign { } { } + assign $0\core_issue__data_i[63:0] $1\core_issue__data_i[63:0] + attribute \src "libresoc.v:180876.5-180876.29" + switch \initial + attribute \src "libresoc.v:180876.9-180876.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:361" + switch \fsm_state$117 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\core_issue__data_i[63:0] \new_dec + attribute \src "libresoc.v:0.0-0.0" + case 2'11 + assign { } { } + assign $1\core_issue__data_i[63:0] \new_tb + case + assign $1\core_issue__data_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \core_issue__data_i $0\core_issue__data_i[63:0] + end + attribute \src "libresoc.v:180890.3-180905.6" + process $proc$libresoc.v:180890$13039 + assign { } { } + assign { } { } + assign { } { } + assign $0\dec2_cur_dec$next[63:0]$13040 $2\dec2_cur_dec$next[63:0]$13042 + attribute \src "libresoc.v:180891.5-180891.29" + switch \initial + attribute \src "libresoc.v:180891.9-180891.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:361" + switch \fsm_state$117 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec2_cur_dec$next[63:0]$13041 \new_dec + case + assign $1\dec2_cur_dec$next[63:0]$13041 \dec2_cur_dec + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\dec2_cur_dec$next[63:0]$13042 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $2\dec2_cur_dec$next[63:0]$13042 $1\dec2_cur_dec$next[63:0]$13041 + end + sync always + update \dec2_cur_dec$next $0\dec2_cur_dec$next[63:0]$13040 + end + attribute \src "libresoc.v:180906.3-180916.6" + process $proc$libresoc.v:180906$13043 + assign { } { } + assign { } { } + assign $0\new_tb[63:0] $1\new_tb[63:0] + attribute \src "libresoc.v:180907.5-180907.29" + switch \initial + attribute \src "libresoc.v:180907.9-180907.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:361" + switch \fsm_state$117 + attribute \src "libresoc.v:0.0-0.0" + case 2'11 + assign { } { } + assign $1\new_tb[63:0] \$121 [63:0] + case + assign $1\new_tb[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \new_tb $0\new_tb[63:0] + end + attribute \src "libresoc.v:180917.3-180925.6" + process $proc$libresoc.v:180917$13044 + assign { } { } + assign { } { } + assign $0\dbg_dmi_we_i$next[0:0]$13045 $1\dbg_dmi_we_i$next[0:0]$13046 + attribute \src "libresoc.v:180918.5-180918.29" + switch \initial + attribute \src "libresoc.v:180918.9-180918.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dbg_dmi_we_i$next[0:0]$13046 1'0 + case + assign $1\dbg_dmi_we_i$next[0:0]$13046 \jtag_dmi0_we_i + end + sync always + update \dbg_dmi_we_i$next $0\dbg_dmi_we_i$next[0:0]$13045 + end + attribute \src "libresoc.v:180926.3-180934.6" + process $proc$libresoc.v:180926$13047 + assign { } { } + assign { } { } + assign $0\pc_ok_delay$next[0:0]$13048 $1\pc_ok_delay$next[0:0]$13049 + attribute \src "libresoc.v:180927.5-180927.29" + switch \initial + attribute \src "libresoc.v:180927.9-180927.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\pc_ok_delay$next[0:0]$13049 1'0 + case + assign $1\pc_ok_delay$next[0:0]$13049 \$23 + end + sync always + update \pc_ok_delay$next $0\pc_ok_delay$next[0:0]$13048 + end + attribute \src "libresoc.v:180935.3-180950.6" + process $proc$libresoc.v:180935$13050 + assign { } { } + assign { } { } + assign { } { } + assign $0\pc[63:0] $2\pc[63:0] + attribute \src "libresoc.v:180936.5-180936.29" + switch \initial + attribute \src "libresoc.v:180936.9-180936.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:187" + switch \pc_i_ok + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\pc[63:0] \pc_i + case + assign $1\pc[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:194" + switch \pc_ok_delay + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\pc[63:0] \core_cia__data_o + case + assign $2\pc[63:0] $1\pc[63:0] + end + sync always + update \pc $0\pc[63:0] + end + attribute \src "libresoc.v:180951.3-180963.6" + process $proc$libresoc.v:180951$13051 + assign { } { } + assign { } { } + assign $0\core_cia__ren[3:0] $1\core_cia__ren[3:0] + attribute \src "libresoc.v:180952.5-180952.29" + switch \initial + attribute \src "libresoc.v:180952.9-180952.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:187" + switch \pc_i_ok + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $1\core_cia__ren[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\core_cia__ren[3:0] 4'0001 + end + sync always + update \core_cia__ren $0\core_cia__ren[3:0] + end + attribute \src "libresoc.v:180964.3-180984.6" + process $proc$libresoc.v:180964$13052 + assign { } { } + assign { } { } + assign $0\core_wen[3:0] $1\core_wen[3:0] + attribute \src "libresoc.v:180965.5-180965.29" + switch \initial + attribute \src "libresoc.v:180965.9-180965.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:225" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'11 + assign { } { } + assign $1\core_wen[3:0] $2\core_wen[3:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:291" + switch \$25 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\core_wen[3:0] $3\core_wen[3:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + switch \$27 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\core_wen[3:0] 4'0001 + case + assign $3\core_wen[3:0] 4'0000 + end + case + assign $2\core_wen[3:0] 4'0000 + end + case + assign $1\core_wen[3:0] 4'0000 + end + sync always + update \core_wen $0\core_wen[3:0] + end + attribute \src "libresoc.v:180985.3-181005.6" + process $proc$libresoc.v:180985$13053 + assign { } { } + assign { } { } + assign $0\core_data_i[63:0] $1\core_data_i[63:0] + attribute \src "libresoc.v:180986.5-180986.29" + switch \initial + attribute \src "libresoc.v:180986.9-180986.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:225" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'11 + assign { } { } + assign $1\core_data_i[63:0] $2\core_data_i[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:291" + switch \$29 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\core_data_i[63:0] $3\core_data_i[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" + switch \$31 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\core_data_i[63:0] \nia + case + assign $3\core_data_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + case + assign $2\core_data_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + case + assign $1\core_data_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \core_data_i $0\core_data_i[63:0] + end + attribute \src "libresoc.v:181006.3-181021.6" + process $proc$libresoc.v:181006$13054 + assign { } { } + assign { } { } + assign $0\core_msr__ren[3:0] $1\core_msr__ren[3:0] + attribute \src "libresoc.v:181007.5-181007.29" + switch \initial + attribute \src "libresoc.v:181007.9-181007.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:225" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\core_msr__ren[3:0] $2\core_msr__ren[3:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" + switch \$37 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\core_msr__ren[3:0] 4'0010 + case + assign $2\core_msr__ren[3:0] 4'0000 + end + case + assign $1\core_msr__ren[3:0] 4'0000 + end + sync always + update \core_msr__ren $0\core_msr__ren[3:0] + end + attribute \src "libresoc.v:181022.3-181030.6" + process $proc$libresoc.v:181022$13055 + assign { } { } + assign { } { } + assign $0\dbg_dmi_din$next[63:0]$13056 $1\dbg_dmi_din$next[63:0]$13057 + attribute \src "libresoc.v:181023.5-181023.29" + switch \initial + attribute \src "libresoc.v:181023.9-181023.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dbg_dmi_din$next[63:0]$13057 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $1\dbg_dmi_din$next[63:0]$13057 \jtag_dmi0_din + end + sync always + update \dbg_dmi_din$next $0\dbg_dmi_din$next[63:0]$13056 + end + attribute \src "libresoc.v:181031.3-181055.6" + process $proc$libresoc.v:181031$13058 + assign { } { } + assign { } { } + assign { } { } + assign $0\pc_changed$next[0:0]$13059 $3\pc_changed$next[0:0]$13062 + attribute \src "libresoc.v:181032.5-181032.29" + switch \initial + attribute \src "libresoc.v:181032.9-181032.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:225" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\pc_changed$next[0:0]$13060 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'11 + assign { } { } + assign $1\pc_changed$next[0:0]$13060 $2\pc_changed$next[0:0]$13061 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289" + switch \$39 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\pc_changed$next[0:0]$13061 1'1 + case + assign $2\pc_changed$next[0:0]$13061 \pc_changed + end + case + assign $1\pc_changed$next[0:0]$13060 \pc_changed + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\pc_changed$next[0:0]$13062 1'0 + case + assign $3\pc_changed$next[0:0]$13062 $1\pc_changed$next[0:0]$13060 + end + sync always + update \pc_changed$next $0\pc_changed$next[0:0]$13059 + end + attribute \src "libresoc.v:181056.3-181162.6" + process $proc$libresoc.v:181056$13063 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\core_asmcode$next[7:0]$13064 $1\core_asmcode$next[7:0]$13115 + assign $0\core_core_core_cia$next[63:0]$13065 $1\core_core_core_cia$next[63:0]$13116 + assign $0\core_core_core_cr_rd$next[7:0]$13066 $1\core_core_core_cr_rd$next[7:0]$13117 + assign { } { } + assign $0\core_core_core_cr_wr$next[7:0]$13068 $1\core_core_core_cr_wr$next[7:0]$13119 + assign $0\core_core_core_fn_unit$next[11:0]$13069 $1\core_core_core_fn_unit$next[11:0]$13120 + assign $0\core_core_core_input_carry$next[1:0]$13070 $1\core_core_core_input_carry$next[1:0]$13121 + assign $0\core_core_core_insn$next[31:0]$13071 $1\core_core_core_insn$next[31:0]$13122 + assign $0\core_core_core_insn_type$next[6:0]$13072 $1\core_core_core_insn_type$next[6:0]$13123 + assign $0\core_core_core_is_32bit$next[0:0]$13073 $1\core_core_core_is_32bit$next[0:0]$13124 + assign $0\core_core_core_msr$next[63:0]$13074 $1\core_core_core_msr$next[63:0]$13125 + assign $0\core_core_core_oe$next[0:0]$13075 $1\core_core_core_oe$next[0:0]$13126 + assign { } { } + assign $0\core_core_core_rc$next[0:0]$13077 $1\core_core_core_rc$next[0:0]$13128 + assign { } { } + assign $0\core_core_core_trapaddr$next[12:0]$13079 $1\core_core_core_trapaddr$next[12:0]$13130 + assign $0\core_core_core_traptype$next[6:0]$13080 $1\core_core_core_traptype$next[6:0]$13131 + assign $0\core_core_cr_in1$next[2:0]$13081 $1\core_core_cr_in1$next[2:0]$13132 + assign { } { } + assign $0\core_core_cr_in2$1$next[2:0]$13083 $1\core_core_cr_in2$1$next[2:0]$13134 + assign $0\core_core_cr_in2$next[2:0]$13084 $1\core_core_cr_in2$next[2:0]$13135 + assign { } { } + assign { } { } + assign $0\core_core_cr_out$next[2:0]$13087 $1\core_core_cr_out$next[2:0]$13138 + assign { } { } + assign $0\core_core_ea$next[4:0]$13089 $1\core_core_ea$next[4:0]$13140 + assign $0\core_core_fast1$next[2:0]$13090 $1\core_core_fast1$next[2:0]$13141 + assign { } { } + assign $0\core_core_fast2$next[2:0]$13092 $1\core_core_fast2$next[2:0]$13143 + assign { } { } + assign $0\core_core_fasto1$next[2:0]$13094 $1\core_core_fasto1$next[2:0]$13145 + assign $0\core_core_fasto2$next[2:0]$13095 $1\core_core_fasto2$next[2:0]$13146 + assign $0\core_core_lk$next[0:0]$13096 $1\core_core_lk$next[0:0]$13147 + assign $0\core_core_reg1$next[4:0]$13097 $1\core_core_reg1$next[4:0]$13148 + assign { } { } + assign $0\core_core_reg2$next[4:0]$13099 $1\core_core_reg2$next[4:0]$13150 + assign { } { } + assign $0\core_core_reg3$next[4:0]$13101 $1\core_core_reg3$next[4:0]$13152 + assign { } { } + assign $0\core_core_rego$next[4:0]$13103 $1\core_core_rego$next[4:0]$13154 + assign $0\core_core_spr1$next[9:0]$13104 $1\core_core_spr1$next[9:0]$13155 + assign { } { } + assign $0\core_core_spro$next[9:0]$13106 $1\core_core_spro$next[9:0]$13157 + assign $0\core_core_xer_in$next[2:0]$13107 $1\core_core_xer_in$next[2:0]$13158 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\core_xer_out$next[0:0]$13114 $1\core_xer_out$next[0:0]$13165 + assign $0\core_core_core_cr_rd_ok$next[0:0]$13067 $4\core_core_core_cr_rd_ok$next[0:0]$13268 + assign $0\core_core_core_oe_ok$next[0:0]$13076 $4\core_core_core_oe_ok$next[0:0]$13269 + assign $0\core_core_core_rc_ok$next[0:0]$13078 $4\core_core_core_rc_ok$next[0:0]$13270 + assign $0\core_core_cr_in1_ok$next[0:0]$13082 $4\core_core_cr_in1_ok$next[0:0]$13271 + assign $0\core_core_cr_in2_ok$2$next[0:0]$13085 $4\core_core_cr_in2_ok$2$next[0:0]$13272 + assign $0\core_core_cr_in2_ok$next[0:0]$13086 $4\core_core_cr_in2_ok$next[0:0]$13273 + assign $0\core_core_cr_wr_ok$next[0:0]$13088 $4\core_core_cr_wr_ok$next[0:0]$13274 + assign $0\core_core_fast1_ok$next[0:0]$13091 $4\core_core_fast1_ok$next[0:0]$13275 + assign $0\core_core_fast2_ok$next[0:0]$13093 $4\core_core_fast2_ok$next[0:0]$13276 + assign $0\core_core_reg1_ok$next[0:0]$13098 $4\core_core_reg1_ok$next[0:0]$13277 + assign $0\core_core_reg2_ok$next[0:0]$13100 $4\core_core_reg2_ok$next[0:0]$13278 + assign $0\core_core_reg3_ok$next[0:0]$13102 $4\core_core_reg3_ok$next[0:0]$13279 + assign $0\core_core_spr1_ok$next[0:0]$13105 $4\core_core_spr1_ok$next[0:0]$13280 + assign $0\core_cr_out_ok$next[0:0]$13108 $4\core_cr_out_ok$next[0:0]$13281 + assign $0\core_ea_ok$next[0:0]$13109 $4\core_ea_ok$next[0:0]$13282 + assign $0\core_fasto1_ok$next[0:0]$13110 $4\core_fasto1_ok$next[0:0]$13283 + assign $0\core_fasto2_ok$next[0:0]$13111 $4\core_fasto2_ok$next[0:0]$13284 + assign $0\core_rego_ok$next[0:0]$13112 $4\core_rego_ok$next[0:0]$13285 + assign $0\core_spro_ok$next[0:0]$13113 $4\core_spro_ok$next[0:0]$13286 + attribute \src "libresoc.v:181057.5-181057.29" + switch \initial + attribute \src "libresoc.v:181057.9-181057.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:225" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\core_core_core_is_32bit$next[0:0]$13124 $1\core_core_cr_wr_ok$next[0:0]$13139 $1\core_core_core_cr_wr$next[7:0]$13119 $1\core_core_core_cr_rd_ok$next[0:0]$13118 $1\core_core_core_cr_rd$next[7:0]$13117 $1\core_core_core_trapaddr$next[12:0]$13130 $1\core_core_core_traptype$next[6:0]$13131 $1\core_core_core_input_carry$next[1:0]$13121 $1\core_core_core_oe_ok$next[0:0]$13127 $1\core_core_core_oe$next[0:0]$13126 $1\core_core_core_rc_ok$next[0:0]$13129 $1\core_core_core_rc$next[0:0]$13128 $1\core_core_lk$next[0:0]$13147 $1\core_core_core_fn_unit$next[11:0]$13120 $1\core_core_core_insn_type$next[6:0]$13123 $1\core_core_core_insn$next[31:0]$13122 $1\core_core_core_cia$next[63:0]$13116 $1\core_core_core_msr$next[63:0]$13125 $1\core_cr_out_ok$next[0:0]$13159 $1\core_core_cr_out$next[2:0]$13138 $1\core_core_cr_in2_ok$2$next[0:0]$13136 $1\core_core_cr_in2$1$next[2:0]$13134 $1\core_core_cr_in2_ok$next[0:0]$13137 $1\core_core_cr_in2$next[2:0]$13135 $1\core_core_cr_in1_ok$next[0:0]$13133 $1\core_core_cr_in1$next[2:0]$13132 $1\core_fasto2_ok$next[0:0]$13162 $1\core_core_fasto2$next[2:0]$13146 $1\core_fasto1_ok$next[0:0]$13161 $1\core_core_fasto1$next[2:0]$13145 $1\core_core_fast2_ok$next[0:0]$13144 $1\core_core_fast2$next[2:0]$13143 $1\core_core_fast1_ok$next[0:0]$13142 $1\core_core_fast1$next[2:0]$13141 $1\core_xer_out$next[0:0]$13165 $1\core_core_xer_in$next[2:0]$13158 $1\core_core_spr1_ok$next[0:0]$13156 $1\core_core_spr1$next[9:0]$13155 $1\core_spro_ok$next[0:0]$13164 $1\core_core_spro$next[9:0]$13157 $1\core_core_reg3_ok$next[0:0]$13153 $1\core_core_reg3$next[4:0]$13152 $1\core_core_reg2_ok$next[0:0]$13151 $1\core_core_reg2$next[4:0]$13150 $1\core_core_reg1_ok$next[0:0]$13149 $1\core_core_reg1$next[4:0]$13148 $1\core_ea_ok$next[0:0]$13160 $1\core_core_ea$next[4:0]$13140 $1\core_rego_ok$next[0:0]$13163 $1\core_core_rego$next[4:0]$13154 $1\core_asmcode$next[7:0]$13115 } 321'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\core_asmcode$next[7:0]$13115 $2\core_asmcode$next[7:0]$13166 + assign $1\core_core_core_cia$next[63:0]$13116 $2\core_core_core_cia$next[63:0]$13167 + assign $1\core_core_core_cr_rd$next[7:0]$13117 $2\core_core_core_cr_rd$next[7:0]$13168 + assign $1\core_core_core_cr_rd_ok$next[0:0]$13118 $2\core_core_core_cr_rd_ok$next[0:0]$13169 + assign $1\core_core_core_cr_wr$next[7:0]$13119 $2\core_core_core_cr_wr$next[7:0]$13170 + assign $1\core_core_core_fn_unit$next[11:0]$13120 $2\core_core_core_fn_unit$next[11:0]$13171 + assign $1\core_core_core_input_carry$next[1:0]$13121 $2\core_core_core_input_carry$next[1:0]$13172 + assign $1\core_core_core_insn$next[31:0]$13122 $2\core_core_core_insn$next[31:0]$13173 + assign $1\core_core_core_insn_type$next[6:0]$13123 $2\core_core_core_insn_type$next[6:0]$13174 + assign $1\core_core_core_is_32bit$next[0:0]$13124 $2\core_core_core_is_32bit$next[0:0]$13175 + assign $1\core_core_core_msr$next[63:0]$13125 $2\core_core_core_msr$next[63:0]$13176 + assign $1\core_core_core_oe$next[0:0]$13126 $2\core_core_core_oe$next[0:0]$13177 + assign $1\core_core_core_oe_ok$next[0:0]$13127 $2\core_core_core_oe_ok$next[0:0]$13178 + assign $1\core_core_core_rc$next[0:0]$13128 $2\core_core_core_rc$next[0:0]$13179 + assign $1\core_core_core_rc_ok$next[0:0]$13129 $2\core_core_core_rc_ok$next[0:0]$13180 + assign $1\core_core_core_trapaddr$next[12:0]$13130 $2\core_core_core_trapaddr$next[12:0]$13181 + assign $1\core_core_core_traptype$next[6:0]$13131 $2\core_core_core_traptype$next[6:0]$13182 + assign $1\core_core_cr_in1$next[2:0]$13132 $2\core_core_cr_in1$next[2:0]$13183 + assign $1\core_core_cr_in1_ok$next[0:0]$13133 $2\core_core_cr_in1_ok$next[0:0]$13184 + assign $1\core_core_cr_in2$1$next[2:0]$13134 $2\core_core_cr_in2$1$next[2:0]$13185 + assign $1\core_core_cr_in2$next[2:0]$13135 $2\core_core_cr_in2$next[2:0]$13186 + assign $1\core_core_cr_in2_ok$2$next[0:0]$13136 $2\core_core_cr_in2_ok$2$next[0:0]$13187 + assign $1\core_core_cr_in2_ok$next[0:0]$13137 $2\core_core_cr_in2_ok$next[0:0]$13188 + assign $1\core_core_cr_out$next[2:0]$13138 $2\core_core_cr_out$next[2:0]$13189 + assign $1\core_core_cr_wr_ok$next[0:0]$13139 $2\core_core_cr_wr_ok$next[0:0]$13190 + assign $1\core_core_ea$next[4:0]$13140 $2\core_core_ea$next[4:0]$13191 + assign $1\core_core_fast1$next[2:0]$13141 $2\core_core_fast1$next[2:0]$13192 + assign $1\core_core_fast1_ok$next[0:0]$13142 $2\core_core_fast1_ok$next[0:0]$13193 + assign $1\core_core_fast2$next[2:0]$13143 $2\core_core_fast2$next[2:0]$13194 + assign $1\core_core_fast2_ok$next[0:0]$13144 $2\core_core_fast2_ok$next[0:0]$13195 + assign $1\core_core_fasto1$next[2:0]$13145 $2\core_core_fasto1$next[2:0]$13196 + assign $1\core_core_fasto2$next[2:0]$13146 $2\core_core_fasto2$next[2:0]$13197 + assign $1\core_core_lk$next[0:0]$13147 $2\core_core_lk$next[0:0]$13198 + assign $1\core_core_reg1$next[4:0]$13148 $2\core_core_reg1$next[4:0]$13199 + assign $1\core_core_reg1_ok$next[0:0]$13149 $2\core_core_reg1_ok$next[0:0]$13200 + assign $1\core_core_reg2$next[4:0]$13150 $2\core_core_reg2$next[4:0]$13201 + assign $1\core_core_reg2_ok$next[0:0]$13151 $2\core_core_reg2_ok$next[0:0]$13202 + assign $1\core_core_reg3$next[4:0]$13152 $2\core_core_reg3$next[4:0]$13203 + assign $1\core_core_reg3_ok$next[0:0]$13153 $2\core_core_reg3_ok$next[0:0]$13204 + assign $1\core_core_rego$next[4:0]$13154 $2\core_core_rego$next[4:0]$13205 + assign $1\core_core_spr1$next[9:0]$13155 $2\core_core_spr1$next[9:0]$13206 + assign $1\core_core_spr1_ok$next[0:0]$13156 $2\core_core_spr1_ok$next[0:0]$13207 + assign $1\core_core_spro$next[9:0]$13157 $2\core_core_spro$next[9:0]$13208 + assign $1\core_core_xer_in$next[2:0]$13158 $2\core_core_xer_in$next[2:0]$13209 + assign $1\core_cr_out_ok$next[0:0]$13159 $2\core_cr_out_ok$next[0:0]$13210 + assign $1\core_ea_ok$next[0:0]$13160 $2\core_ea_ok$next[0:0]$13211 + assign $1\core_fasto1_ok$next[0:0]$13161 $2\core_fasto1_ok$next[0:0]$13212 + assign $1\core_fasto2_ok$next[0:0]$13162 $2\core_fasto2_ok$next[0:0]$13213 + assign $1\core_rego_ok$next[0:0]$13163 $2\core_rego_ok$next[0:0]$13214 + assign $1\core_spro_ok$next[0:0]$13164 $2\core_spro_ok$next[0:0]$13215 + assign $1\core_xer_out$next[0:0]$13165 $2\core_xer_out$next[0:0]$13216 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:258" + switch \imem_f_busy_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $2\core_asmcode$next[7:0]$13166 \core_asmcode + assign $2\core_core_core_cia$next[63:0]$13167 \core_core_core_cia + assign $2\core_core_core_cr_rd$next[7:0]$13168 \core_core_core_cr_rd + assign $2\core_core_core_cr_rd_ok$next[0:0]$13169 \core_core_core_cr_rd_ok + assign $2\core_core_core_cr_wr$next[7:0]$13170 \core_core_core_cr_wr + assign $2\core_core_core_fn_unit$next[11:0]$13171 \core_core_core_fn_unit + assign $2\core_core_core_input_carry$next[1:0]$13172 \core_core_core_input_carry + assign $2\core_core_core_insn$next[31:0]$13173 \core_core_core_insn + assign $2\core_core_core_insn_type$next[6:0]$13174 \core_core_core_insn_type + assign $2\core_core_core_is_32bit$next[0:0]$13175 \core_core_core_is_32bit + assign $2\core_core_core_msr$next[63:0]$13176 \core_core_core_msr + assign $2\core_core_core_oe$next[0:0]$13177 \core_core_core_oe + assign $2\core_core_core_oe_ok$next[0:0]$13178 \core_core_core_oe_ok + assign $2\core_core_core_rc$next[0:0]$13179 \core_core_core_rc + assign $2\core_core_core_rc_ok$next[0:0]$13180 \core_core_core_rc_ok + assign $2\core_core_core_trapaddr$next[12:0]$13181 \core_core_core_trapaddr + assign $2\core_core_core_traptype$next[6:0]$13182 \core_core_core_traptype + assign $2\core_core_cr_in1$next[2:0]$13183 \core_core_cr_in1 + assign $2\core_core_cr_in1_ok$next[0:0]$13184 \core_core_cr_in1_ok + assign $2\core_core_cr_in2$1$next[2:0]$13185 \core_core_cr_in2$1 + assign $2\core_core_cr_in2$next[2:0]$13186 \core_core_cr_in2 + assign $2\core_core_cr_in2_ok$2$next[0:0]$13187 \core_core_cr_in2_ok$2 + assign $2\core_core_cr_in2_ok$next[0:0]$13188 \core_core_cr_in2_ok + assign $2\core_core_cr_out$next[2:0]$13189 \core_core_cr_out + assign $2\core_core_cr_wr_ok$next[0:0]$13190 \core_core_cr_wr_ok + assign $2\core_core_ea$next[4:0]$13191 \core_core_ea + assign $2\core_core_fast1$next[2:0]$13192 \core_core_fast1 + assign $2\core_core_fast1_ok$next[0:0]$13193 \core_core_fast1_ok + assign $2\core_core_fast2$next[2:0]$13194 \core_core_fast2 + assign $2\core_core_fast2_ok$next[0:0]$13195 \core_core_fast2_ok + assign $2\core_core_fasto1$next[2:0]$13196 \core_core_fasto1 + assign $2\core_core_fasto2$next[2:0]$13197 \core_core_fasto2 + assign $2\core_core_lk$next[0:0]$13198 \core_core_lk + assign $2\core_core_reg1$next[4:0]$13199 \core_core_reg1 + assign $2\core_core_reg1_ok$next[0:0]$13200 \core_core_reg1_ok + assign $2\core_core_reg2$next[4:0]$13201 \core_core_reg2 + assign $2\core_core_reg2_ok$next[0:0]$13202 \core_core_reg2_ok + assign $2\core_core_reg3$next[4:0]$13203 \core_core_reg3 + assign $2\core_core_reg3_ok$next[0:0]$13204 \core_core_reg3_ok + assign $2\core_core_rego$next[4:0]$13205 \core_core_rego + assign $2\core_core_spr1$next[9:0]$13206 \core_core_spr1 + assign $2\core_core_spr1_ok$next[0:0]$13207 \core_core_spr1_ok + assign $2\core_core_spro$next[9:0]$13208 \core_core_spro + assign $2\core_core_xer_in$next[2:0]$13209 \core_core_xer_in + assign $2\core_cr_out_ok$next[0:0]$13210 \core_cr_out_ok + assign $2\core_ea_ok$next[0:0]$13211 \core_ea_ok + assign $2\core_fasto1_ok$next[0:0]$13212 \core_fasto1_ok + assign $2\core_fasto2_ok$next[0:0]$13213 \core_fasto2_ok + assign $2\core_rego_ok$next[0:0]$13214 \core_rego_ok + assign $2\core_spro_ok$next[0:0]$13215 \core_spro_ok + assign $2\core_xer_out$next[0:0]$13216 \core_xer_out + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $2\core_core_core_is_32bit$next[0:0]$13175 $2\core_core_cr_wr_ok$next[0:0]$13190 $2\core_core_core_cr_wr$next[7:0]$13170 $2\core_core_core_cr_rd_ok$next[0:0]$13169 $2\core_core_core_cr_rd$next[7:0]$13168 $2\core_core_core_trapaddr$next[12:0]$13181 $2\core_core_core_traptype$next[6:0]$13182 $2\core_core_core_input_carry$next[1:0]$13172 $2\core_core_core_oe_ok$next[0:0]$13178 $2\core_core_core_oe$next[0:0]$13177 $2\core_core_core_rc_ok$next[0:0]$13180 $2\core_core_core_rc$next[0:0]$13179 $2\core_core_lk$next[0:0]$13198 $2\core_core_core_fn_unit$next[11:0]$13171 $2\core_core_core_insn_type$next[6:0]$13174 $2\core_core_core_insn$next[31:0]$13173 $2\core_core_core_cia$next[63:0]$13167 $2\core_core_core_msr$next[63:0]$13176 $2\core_cr_out_ok$next[0:0]$13210 $2\core_core_cr_out$next[2:0]$13189 $2\core_core_cr_in2_ok$2$next[0:0]$13187 $2\core_core_cr_in2$1$next[2:0]$13185 $2\core_core_cr_in2_ok$next[0:0]$13188 $2\core_core_cr_in2$next[2:0]$13186 $2\core_core_cr_in1_ok$next[0:0]$13184 $2\core_core_cr_in1$next[2:0]$13183 $2\core_fasto2_ok$next[0:0]$13213 $2\core_core_fasto2$next[2:0]$13197 $2\core_fasto1_ok$next[0:0]$13212 $2\core_core_fasto1$next[2:0]$13196 $2\core_core_fast2_ok$next[0:0]$13195 $2\core_core_fast2$next[2:0]$13194 $2\core_core_fast1_ok$next[0:0]$13193 $2\core_core_fast1$next[2:0]$13192 $2\core_xer_out$next[0:0]$13216 $2\core_core_xer_in$next[2:0]$13209 $2\core_core_spr1_ok$next[0:0]$13207 $2\core_core_spr1$next[9:0]$13206 $2\core_spro_ok$next[0:0]$13215 $2\core_core_spro$next[9:0]$13208 $2\core_core_reg3_ok$next[0:0]$13204 $2\core_core_reg3$next[4:0]$13203 $2\core_core_reg2_ok$next[0:0]$13202 $2\core_core_reg2$next[4:0]$13201 $2\core_core_reg1_ok$next[0:0]$13200 $2\core_core_reg1$next[4:0]$13199 $2\core_ea_ok$next[0:0]$13211 $2\core_core_ea$next[4:0]$13191 $2\core_rego_ok$next[0:0]$13214 $2\core_core_rego$next[4:0]$13205 $2\core_asmcode$next[7:0]$13166 } { \dec2_is_32bit \dec2_cr_wr_ok \dec2_cr_wr \dec2_cr_rd_ok \dec2_cr_rd \dec2_trapaddr \dec2_traptype \dec2_input_carry \dec2_oe_ok \dec2_oe \dec2_rc_ok \dec2_rc \dec2_lk \dec2_fn_unit \dec2_insn_type \dec2_insn \dec2_cia \dec2_msr \dec2_cr_out_ok \dec2_cr_out \dec2_cr_in2_ok$6 \dec2_cr_in2$5 \dec2_cr_in2_ok \dec2_cr_in2 \dec2_cr_in1_ok \dec2_cr_in1 \dec2_fasto2_ok \dec2_fasto2 \dec2_fasto1_ok \dec2_fasto1 \dec2_fast2_ok \dec2_fast2 \dec2_fast1_ok \dec2_fast1 \dec2_xer_out \dec2_xer_in \dec2_spr1_ok \dec2_spr1 \dec2_spro_ok \dec2_spro \dec2_reg3_ok \dec2_reg3 \dec2_reg2_ok \dec2_reg2 \dec2_reg1_ok \dec2_reg1 \dec2_ea_ok \dec2_ea \dec2_rego_ok \dec2_rego \dec2_asmcode } + end + attribute \src "libresoc.v:0.0-0.0" + case 2'11 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\core_asmcode$next[7:0]$13115 $3\core_asmcode$next[7:0]$13217 + assign $1\core_core_core_cia$next[63:0]$13116 $3\core_core_core_cia$next[63:0]$13218 + assign $1\core_core_core_cr_rd$next[7:0]$13117 $3\core_core_core_cr_rd$next[7:0]$13219 + assign $1\core_core_core_cr_rd_ok$next[0:0]$13118 $3\core_core_core_cr_rd_ok$next[0:0]$13220 + assign $1\core_core_core_cr_wr$next[7:0]$13119 $3\core_core_core_cr_wr$next[7:0]$13221 + assign $1\core_core_core_fn_unit$next[11:0]$13120 $3\core_core_core_fn_unit$next[11:0]$13222 + assign $1\core_core_core_input_carry$next[1:0]$13121 $3\core_core_core_input_carry$next[1:0]$13223 + assign $1\core_core_core_insn$next[31:0]$13122 $3\core_core_core_insn$next[31:0]$13224 + assign $1\core_core_core_insn_type$next[6:0]$13123 $3\core_core_core_insn_type$next[6:0]$13225 + assign $1\core_core_core_is_32bit$next[0:0]$13124 $3\core_core_core_is_32bit$next[0:0]$13226 + assign $1\core_core_core_msr$next[63:0]$13125 $3\core_core_core_msr$next[63:0]$13227 + assign $1\core_core_core_oe$next[0:0]$13126 $3\core_core_core_oe$next[0:0]$13228 + assign $1\core_core_core_oe_ok$next[0:0]$13127 $3\core_core_core_oe_ok$next[0:0]$13229 + assign $1\core_core_core_rc$next[0:0]$13128 $3\core_core_core_rc$next[0:0]$13230 + assign $1\core_core_core_rc_ok$next[0:0]$13129 $3\core_core_core_rc_ok$next[0:0]$13231 + assign $1\core_core_core_trapaddr$next[12:0]$13130 $3\core_core_core_trapaddr$next[12:0]$13232 + assign $1\core_core_core_traptype$next[6:0]$13131 $3\core_core_core_traptype$next[6:0]$13233 + assign $1\core_core_cr_in1$next[2:0]$13132 $3\core_core_cr_in1$next[2:0]$13234 + assign $1\core_core_cr_in1_ok$next[0:0]$13133 $3\core_core_cr_in1_ok$next[0:0]$13235 + assign $1\core_core_cr_in2$1$next[2:0]$13134 $3\core_core_cr_in2$1$next[2:0]$13236 + assign $1\core_core_cr_in2$next[2:0]$13135 $3\core_core_cr_in2$next[2:0]$13237 + assign $1\core_core_cr_in2_ok$2$next[0:0]$13136 $3\core_core_cr_in2_ok$2$next[0:0]$13238 + assign $1\core_core_cr_in2_ok$next[0:0]$13137 $3\core_core_cr_in2_ok$next[0:0]$13239 + assign $1\core_core_cr_out$next[2:0]$13138 $3\core_core_cr_out$next[2:0]$13240 + assign $1\core_core_cr_wr_ok$next[0:0]$13139 $3\core_core_cr_wr_ok$next[0:0]$13241 + assign $1\core_core_ea$next[4:0]$13140 $3\core_core_ea$next[4:0]$13242 + assign $1\core_core_fast1$next[2:0]$13141 $3\core_core_fast1$next[2:0]$13243 + assign $1\core_core_fast1_ok$next[0:0]$13142 $3\core_core_fast1_ok$next[0:0]$13244 + assign $1\core_core_fast2$next[2:0]$13143 $3\core_core_fast2$next[2:0]$13245 + assign $1\core_core_fast2_ok$next[0:0]$13144 $3\core_core_fast2_ok$next[0:0]$13246 + assign $1\core_core_fasto1$next[2:0]$13145 $3\core_core_fasto1$next[2:0]$13247 + assign $1\core_core_fasto2$next[2:0]$13146 $3\core_core_fasto2$next[2:0]$13248 + assign $1\core_core_lk$next[0:0]$13147 $3\core_core_lk$next[0:0]$13249 + assign $1\core_core_reg1$next[4:0]$13148 $3\core_core_reg1$next[4:0]$13250 + assign $1\core_core_reg1_ok$next[0:0]$13149 $3\core_core_reg1_ok$next[0:0]$13251 + assign $1\core_core_reg2$next[4:0]$13150 $3\core_core_reg2$next[4:0]$13252 + assign $1\core_core_reg2_ok$next[0:0]$13151 $3\core_core_reg2_ok$next[0:0]$13253 + assign $1\core_core_reg3$next[4:0]$13152 $3\core_core_reg3$next[4:0]$13254 + assign $1\core_core_reg3_ok$next[0:0]$13153 $3\core_core_reg3_ok$next[0:0]$13255 + assign $1\core_core_rego$next[4:0]$13154 $3\core_core_rego$next[4:0]$13256 + assign $1\core_core_spr1$next[9:0]$13155 $3\core_core_spr1$next[9:0]$13257 + assign $1\core_core_spr1_ok$next[0:0]$13156 $3\core_core_spr1_ok$next[0:0]$13258 + assign $1\core_core_spro$next[9:0]$13157 $3\core_core_spro$next[9:0]$13259 + assign $1\core_core_xer_in$next[2:0]$13158 $3\core_core_xer_in$next[2:0]$13260 + assign $1\core_cr_out_ok$next[0:0]$13159 $3\core_cr_out_ok$next[0:0]$13261 + assign $1\core_ea_ok$next[0:0]$13160 $3\core_ea_ok$next[0:0]$13262 + assign $1\core_fasto1_ok$next[0:0]$13161 $3\core_fasto1_ok$next[0:0]$13263 + assign $1\core_fasto2_ok$next[0:0]$13162 $3\core_fasto2_ok$next[0:0]$13264 + assign $1\core_rego_ok$next[0:0]$13163 $3\core_rego_ok$next[0:0]$13265 + assign $1\core_spro_ok$next[0:0]$13164 $3\core_spro_ok$next[0:0]$13266 + assign $1\core_xer_out$next[0:0]$13165 $3\core_xer_out$next[0:0]$13267 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:291" + switch \$43 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $3\core_core_core_is_32bit$next[0:0]$13226 $3\core_core_cr_wr_ok$next[0:0]$13241 $3\core_core_core_cr_wr$next[7:0]$13221 $3\core_core_core_cr_rd_ok$next[0:0]$13220 $3\core_core_core_cr_rd$next[7:0]$13219 $3\core_core_core_trapaddr$next[12:0]$13232 $3\core_core_core_traptype$next[6:0]$13233 $3\core_core_core_input_carry$next[1:0]$13223 $3\core_core_core_oe_ok$next[0:0]$13229 $3\core_core_core_oe$next[0:0]$13228 $3\core_core_core_rc_ok$next[0:0]$13231 $3\core_core_core_rc$next[0:0]$13230 $3\core_core_lk$next[0:0]$13249 $3\core_core_core_fn_unit$next[11:0]$13222 $3\core_core_core_insn_type$next[6:0]$13225 $3\core_core_core_insn$next[31:0]$13224 $3\core_core_core_cia$next[63:0]$13218 $3\core_core_core_msr$next[63:0]$13227 $3\core_cr_out_ok$next[0:0]$13261 $3\core_core_cr_out$next[2:0]$13240 $3\core_core_cr_in2_ok$2$next[0:0]$13238 $3\core_core_cr_in2$1$next[2:0]$13236 $3\core_core_cr_in2_ok$next[0:0]$13239 $3\core_core_cr_in2$next[2:0]$13237 $3\core_core_cr_in1_ok$next[0:0]$13235 $3\core_core_cr_in1$next[2:0]$13234 $3\core_fasto2_ok$next[0:0]$13264 $3\core_core_fasto2$next[2:0]$13248 $3\core_fasto1_ok$next[0:0]$13263 $3\core_core_fasto1$next[2:0]$13247 $3\core_core_fast2_ok$next[0:0]$13246 $3\core_core_fast2$next[2:0]$13245 $3\core_core_fast1_ok$next[0:0]$13244 $3\core_core_fast1$next[2:0]$13243 $3\core_xer_out$next[0:0]$13267 $3\core_core_xer_in$next[2:0]$13260 $3\core_core_spr1_ok$next[0:0]$13258 $3\core_core_spr1$next[9:0]$13257 $3\core_spro_ok$next[0:0]$13266 $3\core_core_spro$next[9:0]$13259 $3\core_core_reg3_ok$next[0:0]$13255 $3\core_core_reg3$next[4:0]$13254 $3\core_core_reg2_ok$next[0:0]$13253 $3\core_core_reg2$next[4:0]$13252 $3\core_core_reg1_ok$next[0:0]$13251 $3\core_core_reg1$next[4:0]$13250 $3\core_ea_ok$next[0:0]$13262 $3\core_core_ea$next[4:0]$13242 $3\core_rego_ok$next[0:0]$13265 $3\core_core_rego$next[4:0]$13256 $3\core_asmcode$next[7:0]$13217 } 321'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + case + assign $3\core_asmcode$next[7:0]$13217 \core_asmcode + assign $3\core_core_core_cia$next[63:0]$13218 \core_core_core_cia + assign $3\core_core_core_cr_rd$next[7:0]$13219 \core_core_core_cr_rd + assign $3\core_core_core_cr_rd_ok$next[0:0]$13220 \core_core_core_cr_rd_ok + assign $3\core_core_core_cr_wr$next[7:0]$13221 \core_core_core_cr_wr + assign $3\core_core_core_fn_unit$next[11:0]$13222 \core_core_core_fn_unit + assign $3\core_core_core_input_carry$next[1:0]$13223 \core_core_core_input_carry + assign $3\core_core_core_insn$next[31:0]$13224 \core_core_core_insn + assign $3\core_core_core_insn_type$next[6:0]$13225 \core_core_core_insn_type + assign $3\core_core_core_is_32bit$next[0:0]$13226 \core_core_core_is_32bit + assign $3\core_core_core_msr$next[63:0]$13227 \core_core_core_msr + assign $3\core_core_core_oe$next[0:0]$13228 \core_core_core_oe + assign $3\core_core_core_oe_ok$next[0:0]$13229 \core_core_core_oe_ok + assign $3\core_core_core_rc$next[0:0]$13230 \core_core_core_rc + assign $3\core_core_core_rc_ok$next[0:0]$13231 \core_core_core_rc_ok + assign $3\core_core_core_trapaddr$next[12:0]$13232 \core_core_core_trapaddr + assign $3\core_core_core_traptype$next[6:0]$13233 \core_core_core_traptype + assign $3\core_core_cr_in1$next[2:0]$13234 \core_core_cr_in1 + assign $3\core_core_cr_in1_ok$next[0:0]$13235 \core_core_cr_in1_ok + assign $3\core_core_cr_in2$1$next[2:0]$13236 \core_core_cr_in2$1 + assign $3\core_core_cr_in2$next[2:0]$13237 \core_core_cr_in2 + assign $3\core_core_cr_in2_ok$2$next[0:0]$13238 \core_core_cr_in2_ok$2 + assign $3\core_core_cr_in2_ok$next[0:0]$13239 \core_core_cr_in2_ok + assign $3\core_core_cr_out$next[2:0]$13240 \core_core_cr_out + assign $3\core_core_cr_wr_ok$next[0:0]$13241 \core_core_cr_wr_ok + assign $3\core_core_ea$next[4:0]$13242 \core_core_ea + assign $3\core_core_fast1$next[2:0]$13243 \core_core_fast1 + assign $3\core_core_fast1_ok$next[0:0]$13244 \core_core_fast1_ok + assign $3\core_core_fast2$next[2:0]$13245 \core_core_fast2 + assign $3\core_core_fast2_ok$next[0:0]$13246 \core_core_fast2_ok + assign $3\core_core_fasto1$next[2:0]$13247 \core_core_fasto1 + assign $3\core_core_fasto2$next[2:0]$13248 \core_core_fasto2 + assign $3\core_core_lk$next[0:0]$13249 \core_core_lk + assign $3\core_core_reg1$next[4:0]$13250 \core_core_reg1 + assign $3\core_core_reg1_ok$next[0:0]$13251 \core_core_reg1_ok + assign $3\core_core_reg2$next[4:0]$13252 \core_core_reg2 + assign $3\core_core_reg2_ok$next[0:0]$13253 \core_core_reg2_ok + assign $3\core_core_reg3$next[4:0]$13254 \core_core_reg3 + assign $3\core_core_reg3_ok$next[0:0]$13255 \core_core_reg3_ok + assign $3\core_core_rego$next[4:0]$13256 \core_core_rego + assign $3\core_core_spr1$next[9:0]$13257 \core_core_spr1 + assign $3\core_core_spr1_ok$next[0:0]$13258 \core_core_spr1_ok + assign $3\core_core_spro$next[9:0]$13259 \core_core_spro + assign $3\core_core_xer_in$next[2:0]$13260 \core_core_xer_in + assign $3\core_cr_out_ok$next[0:0]$13261 \core_cr_out_ok + assign $3\core_ea_ok$next[0:0]$13262 \core_ea_ok + assign $3\core_fasto1_ok$next[0:0]$13263 \core_fasto1_ok + assign $3\core_fasto2_ok$next[0:0]$13264 \core_fasto2_ok + assign $3\core_rego_ok$next[0:0]$13265 \core_rego_ok + assign $3\core_spro_ok$next[0:0]$13266 \core_spro_ok + assign $3\core_xer_out$next[0:0]$13267 \core_xer_out + end + case + assign $1\core_asmcode$next[7:0]$13115 \core_asmcode + assign $1\core_core_core_cia$next[63:0]$13116 \core_core_core_cia + assign $1\core_core_core_cr_rd$next[7:0]$13117 \core_core_core_cr_rd + assign $1\core_core_core_cr_rd_ok$next[0:0]$13118 \core_core_core_cr_rd_ok + assign $1\core_core_core_cr_wr$next[7:0]$13119 \core_core_core_cr_wr + assign $1\core_core_core_fn_unit$next[11:0]$13120 \core_core_core_fn_unit + assign $1\core_core_core_input_carry$next[1:0]$13121 \core_core_core_input_carry + assign $1\core_core_core_insn$next[31:0]$13122 \core_core_core_insn + assign $1\core_core_core_insn_type$next[6:0]$13123 \core_core_core_insn_type + assign $1\core_core_core_is_32bit$next[0:0]$13124 \core_core_core_is_32bit + assign $1\core_core_core_msr$next[63:0]$13125 \core_core_core_msr + assign $1\core_core_core_oe$next[0:0]$13126 \core_core_core_oe + assign $1\core_core_core_oe_ok$next[0:0]$13127 \core_core_core_oe_ok + assign $1\core_core_core_rc$next[0:0]$13128 \core_core_core_rc + assign $1\core_core_core_rc_ok$next[0:0]$13129 \core_core_core_rc_ok + assign $1\core_core_core_trapaddr$next[12:0]$13130 \core_core_core_trapaddr + assign $1\core_core_core_traptype$next[6:0]$13131 \core_core_core_traptype + assign $1\core_core_cr_in1$next[2:0]$13132 \core_core_cr_in1 + assign $1\core_core_cr_in1_ok$next[0:0]$13133 \core_core_cr_in1_ok + assign $1\core_core_cr_in2$1$next[2:0]$13134 \core_core_cr_in2$1 + assign $1\core_core_cr_in2$next[2:0]$13135 \core_core_cr_in2 + assign $1\core_core_cr_in2_ok$2$next[0:0]$13136 \core_core_cr_in2_ok$2 + assign $1\core_core_cr_in2_ok$next[0:0]$13137 \core_core_cr_in2_ok + assign $1\core_core_cr_out$next[2:0]$13138 \core_core_cr_out + assign $1\core_core_cr_wr_ok$next[0:0]$13139 \core_core_cr_wr_ok + assign $1\core_core_ea$next[4:0]$13140 \core_core_ea + assign $1\core_core_fast1$next[2:0]$13141 \core_core_fast1 + assign $1\core_core_fast1_ok$next[0:0]$13142 \core_core_fast1_ok + assign $1\core_core_fast2$next[2:0]$13143 \core_core_fast2 + assign $1\core_core_fast2_ok$next[0:0]$13144 \core_core_fast2_ok + assign $1\core_core_fasto1$next[2:0]$13145 \core_core_fasto1 + assign $1\core_core_fasto2$next[2:0]$13146 \core_core_fasto2 + assign $1\core_core_lk$next[0:0]$13147 \core_core_lk + assign $1\core_core_reg1$next[4:0]$13148 \core_core_reg1 + assign $1\core_core_reg1_ok$next[0:0]$13149 \core_core_reg1_ok + assign $1\core_core_reg2$next[4:0]$13150 \core_core_reg2 + assign $1\core_core_reg2_ok$next[0:0]$13151 \core_core_reg2_ok + assign $1\core_core_reg3$next[4:0]$13152 \core_core_reg3 + assign $1\core_core_reg3_ok$next[0:0]$13153 \core_core_reg3_ok + assign $1\core_core_rego$next[4:0]$13154 \core_core_rego + assign $1\core_core_spr1$next[9:0]$13155 \core_core_spr1 + assign $1\core_core_spr1_ok$next[0:0]$13156 \core_core_spr1_ok + assign $1\core_core_spro$next[9:0]$13157 \core_core_spro + assign $1\core_core_xer_in$next[2:0]$13158 \core_core_xer_in + assign $1\core_cr_out_ok$next[0:0]$13159 \core_cr_out_ok + assign $1\core_ea_ok$next[0:0]$13160 \core_ea_ok + assign $1\core_fasto1_ok$next[0:0]$13161 \core_fasto1_ok + assign $1\core_fasto2_ok$next[0:0]$13162 \core_fasto2_ok + assign $1\core_rego_ok$next[0:0]$13163 \core_rego_ok + assign $1\core_spro_ok$next[0:0]$13164 \core_spro_ok + assign $1\core_xer_out$next[0:0]$13165 \core_xer_out + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $4\core_rego_ok$next[0:0]$13285 1'0 + assign $4\core_ea_ok$next[0:0]$13282 1'0 + assign $4\core_core_reg1_ok$next[0:0]$13277 1'0 + assign $4\core_core_reg2_ok$next[0:0]$13278 1'0 + assign $4\core_core_reg3_ok$next[0:0]$13279 1'0 + assign $4\core_spro_ok$next[0:0]$13286 1'0 + assign $4\core_core_spr1_ok$next[0:0]$13280 1'0 + assign $4\core_core_fast1_ok$next[0:0]$13275 1'0 + assign $4\core_core_fast2_ok$next[0:0]$13276 1'0 + assign $4\core_fasto1_ok$next[0:0]$13283 1'0 + assign $4\core_fasto2_ok$next[0:0]$13284 1'0 + assign $4\core_core_cr_in1_ok$next[0:0]$13271 1'0 + assign $4\core_core_cr_in2_ok$next[0:0]$13273 1'0 + assign $4\core_core_cr_in2_ok$2$next[0:0]$13272 1'0 + assign $4\core_cr_out_ok$next[0:0]$13281 1'0 + assign $4\core_core_core_rc_ok$next[0:0]$13270 1'0 + assign $4\core_core_core_oe_ok$next[0:0]$13269 1'0 + assign $4\core_core_core_cr_rd_ok$next[0:0]$13268 1'0 + assign $4\core_core_cr_wr_ok$next[0:0]$13274 1'0 + case + assign $4\core_core_core_cr_rd_ok$next[0:0]$13268 $1\core_core_core_cr_rd_ok$next[0:0]$13118 + assign $4\core_core_core_oe_ok$next[0:0]$13269 $1\core_core_core_oe_ok$next[0:0]$13127 + assign $4\core_core_core_rc_ok$next[0:0]$13270 $1\core_core_core_rc_ok$next[0:0]$13129 + assign $4\core_core_cr_in1_ok$next[0:0]$13271 $1\core_core_cr_in1_ok$next[0:0]$13133 + assign $4\core_core_cr_in2_ok$2$next[0:0]$13272 $1\core_core_cr_in2_ok$2$next[0:0]$13136 + assign $4\core_core_cr_in2_ok$next[0:0]$13273 $1\core_core_cr_in2_ok$next[0:0]$13137 + assign $4\core_core_cr_wr_ok$next[0:0]$13274 $1\core_core_cr_wr_ok$next[0:0]$13139 + assign $4\core_core_fast1_ok$next[0:0]$13275 $1\core_core_fast1_ok$next[0:0]$13142 + assign $4\core_core_fast2_ok$next[0:0]$13276 $1\core_core_fast2_ok$next[0:0]$13144 + assign $4\core_core_reg1_ok$next[0:0]$13277 $1\core_core_reg1_ok$next[0:0]$13149 + assign $4\core_core_reg2_ok$next[0:0]$13278 $1\core_core_reg2_ok$next[0:0]$13151 + assign $4\core_core_reg3_ok$next[0:0]$13279 $1\core_core_reg3_ok$next[0:0]$13153 + assign $4\core_core_spr1_ok$next[0:0]$13280 $1\core_core_spr1_ok$next[0:0]$13156 + assign $4\core_cr_out_ok$next[0:0]$13281 $1\core_cr_out_ok$next[0:0]$13159 + assign $4\core_ea_ok$next[0:0]$13282 $1\core_ea_ok$next[0:0]$13160 + assign $4\core_fasto1_ok$next[0:0]$13283 $1\core_fasto1_ok$next[0:0]$13161 + assign $4\core_fasto2_ok$next[0:0]$13284 $1\core_fasto2_ok$next[0:0]$13162 + assign $4\core_rego_ok$next[0:0]$13285 $1\core_rego_ok$next[0:0]$13163 + assign $4\core_spro_ok$next[0:0]$13286 $1\core_spro_ok$next[0:0]$13164 + end + sync always + update \core_asmcode$next $0\core_asmcode$next[7:0]$13064 + update \core_core_core_cia$next $0\core_core_core_cia$next[63:0]$13065 + update \core_core_core_cr_rd$next $0\core_core_core_cr_rd$next[7:0]$13066 + update \core_core_core_cr_rd_ok$next $0\core_core_core_cr_rd_ok$next[0:0]$13067 + update \core_core_core_cr_wr$next $0\core_core_core_cr_wr$next[7:0]$13068 + update \core_core_core_fn_unit$next $0\core_core_core_fn_unit$next[11:0]$13069 + update \core_core_core_input_carry$next $0\core_core_core_input_carry$next[1:0]$13070 + update \core_core_core_insn$next $0\core_core_core_insn$next[31:0]$13071 + update \core_core_core_insn_type$next $0\core_core_core_insn_type$next[6:0]$13072 + update \core_core_core_is_32bit$next $0\core_core_core_is_32bit$next[0:0]$13073 + update \core_core_core_msr$next $0\core_core_core_msr$next[63:0]$13074 + update \core_core_core_oe$next $0\core_core_core_oe$next[0:0]$13075 + update \core_core_core_oe_ok$next $0\core_core_core_oe_ok$next[0:0]$13076 + update \core_core_core_rc$next $0\core_core_core_rc$next[0:0]$13077 + update \core_core_core_rc_ok$next $0\core_core_core_rc_ok$next[0:0]$13078 + update \core_core_core_trapaddr$next $0\core_core_core_trapaddr$next[12:0]$13079 + update \core_core_core_traptype$next $0\core_core_core_traptype$next[6:0]$13080 + update \core_core_cr_in1$next $0\core_core_cr_in1$next[2:0]$13081 + update \core_core_cr_in1_ok$next $0\core_core_cr_in1_ok$next[0:0]$13082 + update \core_core_cr_in2$1$next $0\core_core_cr_in2$1$next[2:0]$13083 + update \core_core_cr_in2$next $0\core_core_cr_in2$next[2:0]$13084 + update \core_core_cr_in2_ok$2$next $0\core_core_cr_in2_ok$2$next[0:0]$13085 + update \core_core_cr_in2_ok$next $0\core_core_cr_in2_ok$next[0:0]$13086 + update \core_core_cr_out$next $0\core_core_cr_out$next[2:0]$13087 + update \core_core_cr_wr_ok$next $0\core_core_cr_wr_ok$next[0:0]$13088 + update \core_core_ea$next $0\core_core_ea$next[4:0]$13089 + update \core_core_fast1$next $0\core_core_fast1$next[2:0]$13090 + update \core_core_fast1_ok$next $0\core_core_fast1_ok$next[0:0]$13091 + update \core_core_fast2$next $0\core_core_fast2$next[2:0]$13092 + update \core_core_fast2_ok$next $0\core_core_fast2_ok$next[0:0]$13093 + update \core_core_fasto1$next $0\core_core_fasto1$next[2:0]$13094 + update \core_core_fasto2$next $0\core_core_fasto2$next[2:0]$13095 + update \core_core_lk$next $0\core_core_lk$next[0:0]$13096 + update \core_core_reg1$next $0\core_core_reg1$next[4:0]$13097 + update \core_core_reg1_ok$next $0\core_core_reg1_ok$next[0:0]$13098 + update \core_core_reg2$next $0\core_core_reg2$next[4:0]$13099 + update \core_core_reg2_ok$next $0\core_core_reg2_ok$next[0:0]$13100 + update \core_core_reg3$next $0\core_core_reg3$next[4:0]$13101 + update \core_core_reg3_ok$next $0\core_core_reg3_ok$next[0:0]$13102 + update \core_core_rego$next $0\core_core_rego$next[4:0]$13103 + update \core_core_spr1$next $0\core_core_spr1$next[9:0]$13104 + update \core_core_spr1_ok$next $0\core_core_spr1_ok$next[0:0]$13105 + update \core_core_spro$next $0\core_core_spro$next[9:0]$13106 + update \core_core_xer_in$next $0\core_core_xer_in$next[2:0]$13107 + update \core_cr_out_ok$next $0\core_cr_out_ok$next[0:0]$13108 + update \core_ea_ok$next $0\core_ea_ok$next[0:0]$13109 + update \core_fasto1_ok$next $0\core_fasto1_ok$next[0:0]$13110 + update \core_fasto2_ok$next $0\core_fasto2_ok$next[0:0]$13111 + update \core_rego_ok$next $0\core_rego_ok$next[0:0]$13112 + update \core_spro_ok$next $0\core_spro_ok$next[0:0]$13113 + update \core_xer_out$next $0\core_xer_out$next[0:0]$13114 + end + attribute \src "libresoc.v:181163.3-181171.6" + process $proc$libresoc.v:181163$13287 + assign { } { } + assign { } { } + assign $0\jtag_dmi0_ack_o$next[0:0]$13288 $1\jtag_dmi0_ack_o$next[0:0]$13289 + attribute \src "libresoc.v:181164.5-181164.29" + switch \initial + attribute \src "libresoc.v:181164.9-181164.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\jtag_dmi0_ack_o$next[0:0]$13289 1'0 + case + assign $1\jtag_dmi0_ack_o$next[0:0]$13289 \dbg_dmi_ack_o + end + sync always + update \jtag_dmi0_ack_o$next $0\jtag_dmi0_ack_o$next[0:0]$13288 + end + attribute \src "libresoc.v:181172.3-181180.6" + process $proc$libresoc.v:181172$13290 + assign { } { } + assign { } { } + assign $0\jtag_dmi0_dout$next[63:0]$13291 $1\jtag_dmi0_dout$next[63:0]$13292 + attribute \src "libresoc.v:181173.5-181173.29" + switch \initial + attribute \src "libresoc.v:181173.9-181173.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\jtag_dmi0_dout$next[63:0]$13292 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $1\jtag_dmi0_dout$next[63:0]$13292 \dbg_dmi_dout + end + sync always + update \jtag_dmi0_dout$next $0\jtag_dmi0_dout$next[63:0]$13291 + end + attribute \src "libresoc.v:181181.3-181189.6" + process $proc$libresoc.v:181181$13293 + assign { } { } + assign { } { } + assign $0\dec2_cur_eint$next[0:0]$13294 $1\dec2_cur_eint$next[0:0]$13295 + attribute \src "libresoc.v:181182.5-181182.29" + switch \initial + attribute \src "libresoc.v:181182.9-181182.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dec2_cur_eint$next[0:0]$13295 1'0 + case + assign $1\dec2_cur_eint$next[0:0]$13295 \xics_icp_core_irq_o + end + sync always + update \dec2_cur_eint$next $0\dec2_cur_eint$next[0:0]$13294 + end + attribute \src "libresoc.v:181190.3-181226.6" + process $proc$libresoc.v:181190$13296 + assign { } { } + assign { } { } + assign { } { } + assign $0\core_raw_insn_i$next[31:0]$13297 $4\core_raw_insn_i$next[31:0]$13301 + attribute \src "libresoc.v:181191.5-181191.29" + switch \initial + attribute \src "libresoc.v:181191.9-181191.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:225" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\core_raw_insn_i$next[31:0]$13298 0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\core_raw_insn_i$next[31:0]$13298 $2\core_raw_insn_i$next[31:0]$13299 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:258" + switch \imem_f_busy_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $2\core_raw_insn_i$next[31:0]$13299 \core_raw_insn_i + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\core_raw_insn_i$next[31:0]$13299 \dec2_raw_opcode_in + end + attribute \src "libresoc.v:0.0-0.0" + case 2'11 + assign { } { } + assign $1\core_raw_insn_i$next[31:0]$13298 $3\core_raw_insn_i$next[31:0]$13300 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:291" + switch \$45 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\core_raw_insn_i$next[31:0]$13300 0 + case + assign $3\core_raw_insn_i$next[31:0]$13300 \core_raw_insn_i + end + case + assign $1\core_raw_insn_i$next[31:0]$13298 \core_raw_insn_i + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\core_raw_insn_i$next[31:0]$13301 0 + case + assign $4\core_raw_insn_i$next[31:0]$13301 $1\core_raw_insn_i$next[31:0]$13298 + end + sync always + update \core_raw_insn_i$next $0\core_raw_insn_i$next[31:0]$13297 + end + attribute \src "libresoc.v:181227.3-181263.6" + process $proc$libresoc.v:181227$13302 + assign { } { } + assign { } { } + assign { } { } + assign $0\core_bigendian_i$3$next[0:0]$13303 $4\core_bigendian_i$3$next[0:0]$13307 + attribute \src "libresoc.v:181228.5-181228.29" + switch \initial + attribute \src "libresoc.v:181228.9-181228.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:225" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\core_bigendian_i$3$next[0:0]$13304 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\core_bigendian_i$3$next[0:0]$13304 $2\core_bigendian_i$3$next[0:0]$13305 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:258" + switch \imem_f_busy_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $2\core_bigendian_i$3$next[0:0]$13305 \core_bigendian_i$3 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\core_bigendian_i$3$next[0:0]$13305 \core_bigendian_i + end + attribute \src "libresoc.v:0.0-0.0" + case 2'11 + assign { } { } + assign $1\core_bigendian_i$3$next[0:0]$13304 $3\core_bigendian_i$3$next[0:0]$13306 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:291" + switch \$47 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\core_bigendian_i$3$next[0:0]$13306 1'0 + case + assign $3\core_bigendian_i$3$next[0:0]$13306 \core_bigendian_i$3 + end + case + assign $1\core_bigendian_i$3$next[0:0]$13304 \core_bigendian_i$3 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\core_bigendian_i$3$next[0:0]$13307 1'0 + case + assign $4\core_bigendian_i$3$next[0:0]$13307 $1\core_bigendian_i$3$next[0:0]$13304 + end + sync always + update \core_bigendian_i$3$next $0\core_bigendian_i$3$next[0:0]$13303 + end + attribute \src "libresoc.v:181264.3-181279.6" + process $proc$libresoc.v:181264$13308 + assign { } { } + assign { } { } + assign $0\imem_a_pc_i[47:0] $1\imem_a_pc_i[47:0] + attribute \src "libresoc.v:181265.5-181265.29" + switch \initial + attribute \src "libresoc.v:181265.9-181265.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:225" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\imem_a_pc_i[47:0] $2\imem_a_pc_i[47:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" + switch \$53 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\imem_a_pc_i[47:0] \pc [47:0] + case + assign $2\imem_a_pc_i[47:0] 48'000000000000000000000000000000000000000000000000 + end + case + assign $1\imem_a_pc_i[47:0] 48'000000000000000000000000000000000000000000000000 + end + sync always + update \imem_a_pc_i $0\imem_a_pc_i[47:0] + end + attribute \src "libresoc.v:181280.3-181304.6" + process $proc$libresoc.v:181280$13309 + assign { } { } + assign { } { } + assign $0\imem_a_valid_i[0:0] $1\imem_a_valid_i[0:0] + attribute \src "libresoc.v:181281.5-181281.29" + switch \initial + attribute \src "libresoc.v:181281.9-181281.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:225" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\imem_a_valid_i[0:0] $2\imem_a_valid_i[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" + switch \$59 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\imem_a_valid_i[0:0] 1'1 + case + assign $2\imem_a_valid_i[0:0] 1'0 + end + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\imem_a_valid_i[0:0] $3\imem_a_valid_i[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:258" + switch \imem_f_busy_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\imem_a_valid_i[0:0] 1'1 + case + assign $3\imem_a_valid_i[0:0] 1'0 + end + case + assign $1\imem_a_valid_i[0:0] 1'0 + end + sync always + update \imem_a_valid_i $0\imem_a_valid_i[0:0] + end + attribute \src "libresoc.v:181305.3-181329.6" + process $proc$libresoc.v:181305$13310 + assign { } { } + assign { } { } + assign $0\imem_f_valid_i[0:0] $1\imem_f_valid_i[0:0] + attribute \src "libresoc.v:181306.5-181306.29" + switch \initial + attribute \src "libresoc.v:181306.9-181306.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:225" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\imem_f_valid_i[0:0] $2\imem_f_valid_i[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" + switch \$65 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\imem_f_valid_i[0:0] 1'1 + case + assign $2\imem_f_valid_i[0:0] 1'0 + end + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\imem_f_valid_i[0:0] $3\imem_f_valid_i[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:258" + switch \imem_f_busy_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\imem_f_valid_i[0:0] 1'1 + case + assign $3\imem_f_valid_i[0:0] 1'0 + end + case + assign $1\imem_f_valid_i[0:0] 1'0 + end + sync always + update \imem_f_valid_i $0\imem_f_valid_i[0:0] + end + attribute \src "libresoc.v:181330.3-181350.6" + process $proc$libresoc.v:181330$13311 + assign { } { } + assign { } { } + assign { } { } + assign $0\dec2_cur_pc$next[63:0]$13312 $3\dec2_cur_pc$next[63:0]$13315 + attribute \src "libresoc.v:181331.5-181331.29" + switch \initial + attribute \src "libresoc.v:181331.9-181331.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:225" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec2_cur_pc$next[63:0]$13313 $2\dec2_cur_pc$next[63:0]$13314 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" + switch \$71 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\dec2_cur_pc$next[63:0]$13314 \pc + case + assign $2\dec2_cur_pc$next[63:0]$13314 \dec2_cur_pc + end + case + assign $1\dec2_cur_pc$next[63:0]$13313 \dec2_cur_pc + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\dec2_cur_pc$next[63:0]$13315 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $3\dec2_cur_pc$next[63:0]$13315 $1\dec2_cur_pc$next[63:0]$13313 + end + sync always + update \dec2_cur_pc$next $0\dec2_cur_pc$next[63:0]$13312 + end + attribute \src "libresoc.v:181351.3-181380.6" + process $proc$libresoc.v:181351$13316 + assign { } { } + assign { } { } + assign { } { } + assign $0\msr_read$next[0:0]$13317 $4\msr_read$next[0:0]$13321 + attribute \src "libresoc.v:181352.5-181352.29" + switch \initial + attribute \src "libresoc.v:181352.9-181352.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:225" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\msr_read$next[0:0]$13318 $2\msr_read$next[0:0]$13319 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" + switch \$77 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\msr_read$next[0:0]$13319 1'0 + case + assign $2\msr_read$next[0:0]$13319 \msr_read + end + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\msr_read$next[0:0]$13318 $3\msr_read$next[0:0]$13320 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:255" + switch \$79 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\msr_read$next[0:0]$13320 1'1 + case + assign $3\msr_read$next[0:0]$13320 \msr_read + end + case + assign $1\msr_read$next[0:0]$13318 \msr_read + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\msr_read$next[0:0]$13321 1'1 + case + assign $4\msr_read$next[0:0]$13321 $1\msr_read$next[0:0]$13318 + end + sync always + update \msr_read$next $0\msr_read$next[0:0]$13317 + end + attribute \src "libresoc.v:181381.3-181426.6" + process $proc$libresoc.v:181381$13322 + assign { } { } + assign { } { } + assign { } { } + assign $0\fsm_state$next[1:0]$13323 $5\fsm_state$next[1:0]$13328 + attribute \src "libresoc.v:181382.5-181382.29" + switch \initial + attribute \src "libresoc.v:181382.9-181382.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:225" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\fsm_state$next[1:0]$13324 $2\fsm_state$next[1:0]$13325 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" + switch \$85 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\fsm_state$next[1:0]$13325 2'01 + case + assign $2\fsm_state$next[1:0]$13325 \fsm_state + end + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\fsm_state$next[1:0]$13324 $3\fsm_state$next[1:0]$13326 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:258" + switch \imem_f_busy_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $3\fsm_state$next[1:0]$13326 \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $3\fsm_state$next[1:0]$13326 2'10 + end + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\fsm_state$next[1:0]$13324 2'11 + attribute \src "libresoc.v:0.0-0.0" + case 2'11 + assign { } { } + assign $1\fsm_state$next[1:0]$13324 $4\fsm_state$next[1:0]$13327 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:291" + switch \$87 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\fsm_state$next[1:0]$13327 2'00 + case + assign $4\fsm_state$next[1:0]$13327 \fsm_state + end + case + assign $1\fsm_state$next[1:0]$13324 \fsm_state + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\fsm_state$next[1:0]$13328 2'00 + case + assign $5\fsm_state$next[1:0]$13328 $1\fsm_state$next[1:0]$13324 + end + sync always + update \fsm_state$next $0\fsm_state$next[1:0]$13323 + end + attribute \src "libresoc.v:181427.3-181436.6" + process $proc$libresoc.v:181427$13329 + assign { } { } + assign { } { } + assign $0\delay$next[1:0]$13330 $1\delay$next[1:0]$13331 + attribute \src "libresoc.v:181428.5-181428.29" + switch \initial + attribute \src "libresoc.v:181428.9-181428.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:156" + switch \$7 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\delay$next[1:0]$13331 \$9 [1:0] + case + assign $1\delay$next[1:0]$13331 \delay + end + sync always + update \delay$next $0\delay$next[1:0]$13330 + end + attribute \src "libresoc.v:181437.3-181455.6" + process $proc$libresoc.v:181437$13332 + assign { } { } + assign { } { } + assign $0\core_stopped_i[0:0] $1\core_stopped_i[0:0] + attribute \src "libresoc.v:181438.5-181438.29" + switch \initial + attribute \src "libresoc.v:181438.9-181438.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:225" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\core_stopped_i[0:0] $2\core_stopped_i[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" + switch \$93 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $2\core_stopped_i[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\core_stopped_i[0:0] 1'1 + end + case + assign $1\core_stopped_i[0:0] 1'0 + end + sync always + update \core_stopped_i $0\core_stopped_i[0:0] + end + attribute \src "libresoc.v:181456.3-181474.6" + process $proc$libresoc.v:181456$13333 + assign { } { } + assign { } { } + assign $0\dbg_core_stopped_i[0:0] $1\dbg_core_stopped_i[0:0] + attribute \src "libresoc.v:181457.5-181457.29" + switch \initial + attribute \src "libresoc.v:181457.9-181457.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:225" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dbg_core_stopped_i[0:0] $2\dbg_core_stopped_i[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" + switch \$99 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $2\dbg_core_stopped_i[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\dbg_core_stopped_i[0:0] 1'1 + end + case + assign $1\dbg_core_stopped_i[0:0] 1'0 + end + sync always + update \dbg_core_stopped_i $0\dbg_core_stopped_i[0:0] + end + attribute \src "libresoc.v:181475.3-181495.6" + process $proc$libresoc.v:181475$13334 + assign { } { } + assign { } { } + assign { } { } + assign $0\dec2_cur_msr$next[63:0]$13335 $3\dec2_cur_msr$next[63:0]$13338 + attribute \src "libresoc.v:181476.5-181476.29" + switch \initial + attribute \src "libresoc.v:181476.9-181476.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:225" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec2_cur_msr$next[63:0]$13336 $2\dec2_cur_msr$next[63:0]$13337 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:255" + switch \$101 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\dec2_cur_msr$next[63:0]$13337 \core_msr__data_o + case + assign $2\dec2_cur_msr$next[63:0]$13337 \dec2_cur_msr + end + case + assign $1\dec2_cur_msr$next[63:0]$13336 \dec2_cur_msr + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\dec2_cur_msr$next[63:0]$13338 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $3\dec2_cur_msr$next[63:0]$13338 $1\dec2_cur_msr$next[63:0]$13336 + end + sync always + update \dec2_cur_msr$next $0\dec2_cur_msr$next[63:0]$13335 + end + attribute \src "libresoc.v:181496.3-181514.6" + process $proc$libresoc.v:181496$13339 + assign { } { } + assign { } { } + assign $0\dec2_raw_opcode_in[31:0] $1\dec2_raw_opcode_in[31:0] + attribute \src "libresoc.v:181497.5-181497.29" + switch \initial + attribute \src "libresoc.v:181497.9-181497.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:225" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec2_raw_opcode_in[31:0] $2\dec2_raw_opcode_in[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:258" + switch \imem_f_busy_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $2\dec2_raw_opcode_in[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\dec2_raw_opcode_in[31:0] \$103 + end + case + assign $1\dec2_raw_opcode_in[31:0] 0 + end + sync always + update \dec2_raw_opcode_in $0\dec2_raw_opcode_in[31:0] + end + attribute \src "libresoc.v:181515.3-181546.6" + process $proc$libresoc.v:181515$13340 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\core_core_pc$next[63:0]$13341 $3\core_core_pc$next[63:0]$13353 + assign $0\core_dec$next[63:0]$13342 $3\core_dec$next[63:0]$13354 + assign $0\core_eint$next[0:0]$13343 $3\core_eint$next[0:0]$13355 + assign $0\core_msr$next[63:0]$13344 $3\core_msr$next[63:0]$13356 + attribute \src "libresoc.v:181516.5-181516.29" + switch \initial + attribute \src "libresoc.v:181516.9-181516.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:225" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\core_core_pc$next[63:0]$13345 $2\core_core_pc$next[63:0]$13349 + assign $1\core_dec$next[63:0]$13346 $2\core_dec$next[63:0]$13350 + assign $1\core_eint$next[0:0]$13347 $2\core_eint$next[0:0]$13351 + assign $1\core_msr$next[63:0]$13348 $2\core_msr$next[63:0]$13352 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:258" + switch \imem_f_busy_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $2\core_core_pc$next[63:0]$13349 \core_core_pc + assign $2\core_dec$next[63:0]$13350 \core_dec + assign $2\core_eint$next[0:0]$13351 \core_eint + assign $2\core_msr$next[63:0]$13352 \core_msr + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $2\core_dec$next[63:0]$13350 $2\core_eint$next[0:0]$13351 $2\core_msr$next[63:0]$13352 $2\core_core_pc$next[63:0]$13349 } { \dec2_cur_dec \dec2_cur_eint \dec2_cur_msr \dec2_cur_pc } + end + case + assign $1\core_core_pc$next[63:0]$13345 \core_core_pc + assign $1\core_dec$next[63:0]$13346 \core_dec + assign $1\core_eint$next[0:0]$13347 \core_eint + assign $1\core_msr$next[63:0]$13348 \core_msr + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $3\core_core_pc$next[63:0]$13353 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\core_msr$next[63:0]$13356 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\core_eint$next[0:0]$13355 1'0 + assign $3\core_dec$next[63:0]$13354 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $3\core_core_pc$next[63:0]$13353 $1\core_core_pc$next[63:0]$13345 + assign $3\core_dec$next[63:0]$13354 $1\core_dec$next[63:0]$13346 + assign $3\core_eint$next[0:0]$13355 $1\core_eint$next[0:0]$13347 + assign $3\core_msr$next[63:0]$13356 $1\core_msr$next[63:0]$13348 + end + sync always + update \core_core_pc$next $0\core_core_pc$next[63:0]$13341 + update \core_dec$next $0\core_dec$next[63:0]$13342 + update \core_eint$next $0\core_eint$next[0:0]$13343 + update \core_msr$next $0\core_msr$next[63:0]$13344 + end + attribute \src "libresoc.v:181547.3-181570.6" + process $proc$libresoc.v:181547$13357 + assign { } { } + assign { } { } + assign { } { } + assign $0\ilatch$next[31:0]$13358 $3\ilatch$next[31:0]$13361 + attribute \src "libresoc.v:181548.5-181548.29" + switch \initial + attribute \src "libresoc.v:181548.9-181548.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:225" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\ilatch$next[31:0]$13359 $2\ilatch$next[31:0]$13360 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:258" + switch \imem_f_busy_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $2\ilatch$next[31:0]$13360 \ilatch + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\ilatch$next[31:0]$13360 \$107 + end + case + assign $1\ilatch$next[31:0]$13359 \ilatch + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\ilatch$next[31:0]$13361 0 + case + assign $3\ilatch$next[31:0]$13361 $1\ilatch$next[31:0]$13359 + end + sync always + update \ilatch$next $0\ilatch$next[31:0]$13358 + end + attribute \src "libresoc.v:181571.3-181590.6" + process $proc$libresoc.v:181571$13362 + assign { } { } + assign { } { } + assign $0\core_ivalid_i[0:0] $1\core_ivalid_i[0:0] + attribute \src "libresoc.v:181572.5-181572.29" + switch \initial + attribute \src "libresoc.v:181572.9-181572.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:225" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\core_ivalid_i[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'11 + assign { } { } + assign $1\core_ivalid_i[0:0] $2\core_ivalid_i[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:287" + switch \$111 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\core_ivalid_i[0:0] 1'1 + case + assign $2\core_ivalid_i[0:0] 1'0 + end + case + assign $1\core_ivalid_i[0:0] 1'0 + end + sync always + update \core_ivalid_i $0\core_ivalid_i[0:0] + end + connect \$99 $and$libresoc.v:180071$12861_Y + connect \$101 $not$libresoc.v:180072$12862_Y + connect \$104 $mul$libresoc.v:180073$12863_Y + connect \$103 $shr$libresoc.v:180074$12864_Y [31:0] + connect \$108 $mul$libresoc.v:180075$12865_Y + connect \$10 $sub$libresoc.v:180076$12866_Y + connect \$107 $shr$libresoc.v:180077$12867_Y [31:0] + connect \$111 $ne$libresoc.v:180078$12868_Y + connect \$113 $pos$libresoc.v:180079$12870_Y + connect \$115 $pos$libresoc.v:180080$12872_Y + connect \$119 $sub$libresoc.v:180081$12873_Y + connect \$122 $add$libresoc.v:180082$12874_Y + connect \$12 $or$libresoc.v:180083$12875_Y + connect \$14 $ne$libresoc.v:180084$12876_Y + connect \$16 $not$libresoc.v:180085$12877_Y + connect \$18 $and$libresoc.v:180086$12878_Y + connect \$21 $add$libresoc.v:180087$12879_Y + connect \$23 $not$libresoc.v:180088$12880_Y + connect \$25 $not$libresoc.v:180089$12881_Y + connect \$27 $not$libresoc.v:180090$12882_Y + connect \$29 $not$libresoc.v:180091$12883_Y + connect \$31 $not$libresoc.v:180092$12884_Y + connect \$33 $not$libresoc.v:180093$12885_Y + connect \$35 $not$libresoc.v:180094$12886_Y + connect \$37 $and$libresoc.v:180095$12887_Y + connect \$40 $and$libresoc.v:180096$12888_Y + connect \$39 $reduce_or$libresoc.v:180097$12889_Y + connect \$43 $not$libresoc.v:180098$12890_Y + connect \$45 $not$libresoc.v:180099$12891_Y + connect \$47 $not$libresoc.v:180100$12892_Y + connect \$49 $not$libresoc.v:180101$12893_Y + connect \$51 $not$libresoc.v:180102$12894_Y + connect \$53 $and$libresoc.v:180103$12895_Y + connect \$55 $not$libresoc.v:180104$12896_Y + connect \$57 $not$libresoc.v:180105$12897_Y + connect \$59 $and$libresoc.v:180106$12898_Y + connect \$61 $not$libresoc.v:180107$12899_Y + connect \$63 $not$libresoc.v:180108$12900_Y + connect \$65 $and$libresoc.v:180109$12901_Y + connect \$67 $not$libresoc.v:180110$12902_Y + connect \$69 $not$libresoc.v:180111$12903_Y + connect \$71 $and$libresoc.v:180112$12904_Y + connect \$73 $not$libresoc.v:180113$12905_Y + connect \$75 $not$libresoc.v:180114$12906_Y + connect \$77 $and$libresoc.v:180115$12907_Y + connect \$7 $ne$libresoc.v:180116$12908_Y + connect \$79 $not$libresoc.v:180117$12909_Y + connect \$81 $not$libresoc.v:180118$12910_Y + connect \$83 $not$libresoc.v:180119$12911_Y + connect \$85 $and$libresoc.v:180120$12912_Y + connect \$87 $not$libresoc.v:180121$12913_Y + connect \$89 $not$libresoc.v:180122$12914_Y + connect \$91 $not$libresoc.v:180123$12915_Y + connect \$93 $and$libresoc.v:180124$12916_Y + connect \$95 $not$libresoc.v:180125$12917_Y + connect \$97 $not$libresoc.v:180126$12918_Y + connect \$9 \$10 + connect \$20 \$21 + connect \$118 \$119 + connect \$121 \$122 + connect \dbg_core_dbg_msr \dec2_cur_msr + connect \dbg_core_dbg_pc \pc + connect \dbg_terminate_i \core_core_terminate_o + connect \nia \$21 [63:0] + connect \pc_o \dec2_cur_pc + connect \core_cu_st__go_i \cu_st__rel_o_rise + connect \core_cu_ad__go_i \core_cu_ad__rel_o + connect \cu_st__rel_o_rise \$18 + connect \cu_st__rel_o_dly$next \core_cu_st__rel_o + connect \dec2_bigendian \core_bigendian_i + connect \busy_o \core_corebusy_o + connect \core_core_reset_i \$14 + connect \core_coresync_clk \clk + connect \por_clk \clk + connect { \xics_icp_ics_i_pri \xics_icp_ics_i_src } { \xics_ics_icp_o_pri \xics_ics_icp_o_src } +end +attribute \src "libresoc.v:181614.1-182789.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.trap0" +attribute \generator "nMigen" +module \trap0 + attribute \src "libresoc.v:182336.3-182337.25" + wire $0\all_rd_dly[0:0] + attribute \src "libresoc.v:182334.3-182335.41" + wire $0\alu_done_dly[0:0] + attribute \src "libresoc.v:182692.3-182700.6" + wire $0\alu_l_r_alu$next[0:0]$13648 + attribute \src "libresoc.v:182264.3-182265.39" + wire $0\alu_l_r_alu[0:0] + attribute \src "libresoc.v:182516.3-182532.6" + wire width 64 $0\alu_trap0_trap_op__cia$next[63:0]$13576 + attribute \src "libresoc.v:182304.3-182305.61" + wire width 64 $0\alu_trap0_trap_op__cia[63:0] + attribute \src "libresoc.v:182516.3-182532.6" + wire width 12 $0\alu_trap0_trap_op__fn_unit$next[11:0]$13577 + attribute \src "libresoc.v:182298.3-182299.69" + wire width 12 $0\alu_trap0_trap_op__fn_unit[11:0] + attribute \src "libresoc.v:182516.3-182532.6" + wire width 32 $0\alu_trap0_trap_op__insn$next[31:0]$13578 + attribute \src "libresoc.v:182300.3-182301.63" + wire width 32 $0\alu_trap0_trap_op__insn[31:0] + attribute \src "libresoc.v:182516.3-182532.6" + wire width 7 $0\alu_trap0_trap_op__insn_type$next[6:0]$13579 + attribute \src "libresoc.v:182296.3-182297.73" + wire width 7 $0\alu_trap0_trap_op__insn_type[6:0] + attribute \src "libresoc.v:182516.3-182532.6" + wire $0\alu_trap0_trap_op__is_32bit$next[0:0]$13580 + attribute \src "libresoc.v:182306.3-182307.71" + wire $0\alu_trap0_trap_op__is_32bit[0:0] + attribute \src "libresoc.v:182516.3-182532.6" + wire width 64 $0\alu_trap0_trap_op__msr$next[63:0]$13581 + attribute \src "libresoc.v:182302.3-182303.61" + wire width 64 $0\alu_trap0_trap_op__msr[63:0] + attribute \src "libresoc.v:182516.3-182532.6" + wire width 13 $0\alu_trap0_trap_op__trapaddr$next[12:0]$13582 + attribute \src "libresoc.v:182310.3-182311.71" + wire width 13 $0\alu_trap0_trap_op__trapaddr[12:0] + attribute \src "libresoc.v:182516.3-182532.6" + wire width 7 $0\alu_trap0_trap_op__traptype$next[6:0]$13583 + attribute \src "libresoc.v:182308.3-182309.71" + wire width 7 $0\alu_trap0_trap_op__traptype[6:0] + attribute \src "libresoc.v:182683.3-182691.6" + wire $0\alui_l_r_alui$next[0:0]$13645 + attribute \src "libresoc.v:182266.3-182267.43" + wire $0\alui_l_r_alui[0:0] + attribute \src "libresoc.v:182533.3-182554.6" + wire width 64 $0\data_r0__o$next[63:0]$13593 + attribute \src "libresoc.v:182292.3-182293.37" + wire width 64 $0\data_r0__o[63:0] + attribute \src "libresoc.v:182533.3-182554.6" + wire $0\data_r0__o_ok$next[0:0]$13594 + attribute \src "libresoc.v:182294.3-182295.43" + wire $0\data_r0__o_ok[0:0] + attribute \src "libresoc.v:182555.3-182576.6" + wire width 64 $0\data_r1__fast1$next[63:0]$13601 + attribute \src "libresoc.v:182288.3-182289.45" + wire width 64 $0\data_r1__fast1[63:0] + attribute \src "libresoc.v:182555.3-182576.6" + wire $0\data_r1__fast1_ok$next[0:0]$13602 + attribute \src "libresoc.v:182290.3-182291.51" + wire $0\data_r1__fast1_ok[0:0] + attribute \src "libresoc.v:182577.3-182598.6" + wire width 64 $0\data_r2__fast2$next[63:0]$13609 + attribute \src "libresoc.v:182284.3-182285.45" + wire width 64 $0\data_r2__fast2[63:0] + attribute \src "libresoc.v:182577.3-182598.6" + wire $0\data_r2__fast2_ok$next[0:0]$13610 + attribute \src "libresoc.v:182286.3-182287.51" + wire $0\data_r2__fast2_ok[0:0] + attribute \src "libresoc.v:182599.3-182620.6" + wire width 64 $0\data_r3__nia$next[63:0]$13617 + attribute \src "libresoc.v:182280.3-182281.41" + wire width 64 $0\data_r3__nia[63:0] + attribute \src "libresoc.v:182599.3-182620.6" + wire $0\data_r3__nia_ok$next[0:0]$13618 + attribute \src "libresoc.v:182282.3-182283.47" + wire $0\data_r3__nia_ok[0:0] + attribute \src "libresoc.v:182621.3-182642.6" + wire width 64 $0\data_r4__msr$next[63:0]$13625 + attribute \src "libresoc.v:182276.3-182277.41" + wire width 64 $0\data_r4__msr[63:0] + attribute \src "libresoc.v:182621.3-182642.6" + wire $0\data_r4__msr_ok$next[0:0]$13626 + attribute \src "libresoc.v:182278.3-182279.47" + wire $0\data_r4__msr_ok[0:0] + attribute \src "libresoc.v:182701.3-182710.6" + wire width 64 $0\dest1_o[63:0] + attribute \src "libresoc.v:182711.3-182720.6" + wire width 64 $0\dest2_o[63:0] + attribute \src "libresoc.v:182721.3-182730.6" + wire width 64 $0\dest3_o[63:0] + attribute \src "libresoc.v:182731.3-182740.6" + wire width 64 $0\dest4_o[63:0] + attribute \src "libresoc.v:182741.3-182750.6" + wire width 64 $0\dest5_o[63:0] + attribute \src "libresoc.v:181615.7-181615.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:182471.3-182479.6" + wire $0\opc_l_r_opc$next[0:0]$13561 + attribute \src "libresoc.v:182320.3-182321.39" + wire $0\opc_l_r_opc[0:0] + attribute \src "libresoc.v:182462.3-182470.6" + wire $0\opc_l_s_opc$next[0:0]$13558 + attribute \src "libresoc.v:182322.3-182323.39" + wire $0\opc_l_s_opc[0:0] + attribute \src "libresoc.v:182751.3-182759.6" + wire width 5 $0\prev_wr_go$next[4:0]$13656 + attribute \src "libresoc.v:182332.3-182333.37" + wire width 5 $0\prev_wr_go[4:0] + attribute \src "libresoc.v:182416.3-182425.6" + wire $0\req_done[0:0] + attribute \src "libresoc.v:182507.3-182515.6" + wire width 5 $0\req_l_r_req$next[4:0]$13573 + attribute \src "libresoc.v:182312.3-182313.39" + wire width 5 $0\req_l_r_req[4:0] + attribute \src "libresoc.v:182498.3-182506.6" + wire width 5 $0\req_l_s_req$next[4:0]$13570 + attribute \src "libresoc.v:182314.3-182315.39" + wire width 5 $0\req_l_s_req[4:0] + attribute \src "libresoc.v:182435.3-182443.6" + wire $0\rok_l_r_rdok$next[0:0]$13549 + attribute \src "libresoc.v:182328.3-182329.41" + wire $0\rok_l_r_rdok[0:0] + attribute \src "libresoc.v:182426.3-182434.6" + wire $0\rok_l_s_rdok$next[0:0]$13546 + attribute \src "libresoc.v:182330.3-182331.41" + wire $0\rok_l_s_rdok[0:0] + attribute \src "libresoc.v:182453.3-182461.6" + wire $0\rst_l_r_rst$next[0:0]$13555 + attribute \src "libresoc.v:182324.3-182325.39" + wire $0\rst_l_r_rst[0:0] + attribute \src "libresoc.v:182444.3-182452.6" + wire $0\rst_l_s_rst$next[0:0]$13552 + attribute \src "libresoc.v:182326.3-182327.39" + wire $0\rst_l_s_rst[0:0] + attribute \src "libresoc.v:182489.3-182497.6" + wire width 4 $0\src_l_r_src$next[3:0]$13567 + attribute \src "libresoc.v:182316.3-182317.39" + wire width 4 $0\src_l_r_src[3:0] + attribute \src "libresoc.v:182480.3-182488.6" + wire width 4 $0\src_l_s_src$next[3:0]$13564 + attribute \src "libresoc.v:182318.3-182319.39" + wire width 4 $0\src_l_s_src[3:0] + attribute \src "libresoc.v:182643.3-182652.6" + wire width 64 $0\src_r0$next[63:0]$13633 + attribute \src "libresoc.v:182274.3-182275.29" + wire width 64 $0\src_r0[63:0] + attribute \src "libresoc.v:182653.3-182662.6" + wire width 64 $0\src_r1$next[63:0]$13636 + attribute \src "libresoc.v:182272.3-182273.29" + wire width 64 $0\src_r1[63:0] + attribute \src "libresoc.v:182663.3-182672.6" + wire width 64 $0\src_r2$next[63:0]$13639 + attribute \src "libresoc.v:182270.3-182271.29" + wire width 64 $0\src_r2[63:0] + attribute \src "libresoc.v:182673.3-182682.6" + wire width 64 $0\src_r3$next[63:0]$13642 + attribute \src "libresoc.v:182268.3-182269.29" + wire width 64 $0\src_r3[63:0] + attribute \src "libresoc.v:181741.7-181741.24" + wire $1\all_rd_dly[0:0] + attribute \src "libresoc.v:181751.7-181751.26" + wire $1\alu_done_dly[0:0] + attribute \src "libresoc.v:182692.3-182700.6" + wire $1\alu_l_r_alu$next[0:0]$13649 + attribute \src "libresoc.v:181759.7-181759.25" + wire $1\alu_l_r_alu[0:0] + attribute \src "libresoc.v:182516.3-182532.6" + wire width 64 $1\alu_trap0_trap_op__cia$next[63:0]$13584 + attribute \src "libresoc.v:181795.14-181795.59" + wire width 64 $1\alu_trap0_trap_op__cia[63:0] + attribute \src "libresoc.v:182516.3-182532.6" + wire width 12 $1\alu_trap0_trap_op__fn_unit$next[11:0]$13585 + attribute \src "libresoc.v:181812.14-181812.50" + wire width 12 $1\alu_trap0_trap_op__fn_unit[11:0] + attribute \src "libresoc.v:182516.3-182532.6" + wire width 32 $1\alu_trap0_trap_op__insn$next[31:0]$13586 + attribute \src "libresoc.v:181816.14-181816.45" + wire width 32 $1\alu_trap0_trap_op__insn[31:0] + attribute \src "libresoc.v:182516.3-182532.6" + wire width 7 $1\alu_trap0_trap_op__insn_type$next[6:0]$13587 + attribute \src "libresoc.v:181894.13-181894.49" + wire width 7 $1\alu_trap0_trap_op__insn_type[6:0] + attribute \src "libresoc.v:182516.3-182532.6" + wire $1\alu_trap0_trap_op__is_32bit$next[0:0]$13588 + attribute \src "libresoc.v:181898.7-181898.41" + wire $1\alu_trap0_trap_op__is_32bit[0:0] + attribute \src "libresoc.v:182516.3-182532.6" + wire width 64 $1\alu_trap0_trap_op__msr$next[63:0]$13589 + attribute \src "libresoc.v:181902.14-181902.59" + wire width 64 $1\alu_trap0_trap_op__msr[63:0] + attribute \src "libresoc.v:182516.3-182532.6" + wire width 13 $1\alu_trap0_trap_op__trapaddr$next[12:0]$13590 + attribute \src "libresoc.v:181906.14-181906.52" + wire width 13 $1\alu_trap0_trap_op__trapaddr[12:0] + attribute \src "libresoc.v:182516.3-182532.6" + wire width 7 $1\alu_trap0_trap_op__traptype$next[6:0]$13591 + attribute \src "libresoc.v:181910.13-181910.48" + wire width 7 $1\alu_trap0_trap_op__traptype[6:0] + attribute \src "libresoc.v:182683.3-182691.6" + wire $1\alui_l_r_alui$next[0:0]$13646 + attribute \src "libresoc.v:181916.7-181916.27" + wire $1\alui_l_r_alui[0:0] + attribute \src "libresoc.v:182533.3-182554.6" + wire width 64 $1\data_r0__o$next[63:0]$13595 + attribute \src "libresoc.v:181948.14-181948.47" + wire width 64 $1\data_r0__o[63:0] + attribute \src "libresoc.v:182533.3-182554.6" + wire $1\data_r0__o_ok$next[0:0]$13596 + attribute \src "libresoc.v:181952.7-181952.27" + wire $1\data_r0__o_ok[0:0] + attribute \src "libresoc.v:182555.3-182576.6" + wire width 64 $1\data_r1__fast1$next[63:0]$13603 + attribute \src "libresoc.v:181956.14-181956.51" + wire width 64 $1\data_r1__fast1[63:0] + attribute \src "libresoc.v:182555.3-182576.6" + wire $1\data_r1__fast1_ok$next[0:0]$13604 + attribute \src "libresoc.v:181960.7-181960.31" + wire $1\data_r1__fast1_ok[0:0] + attribute \src "libresoc.v:182577.3-182598.6" + wire width 64 $1\data_r2__fast2$next[63:0]$13611 + attribute \src "libresoc.v:181964.14-181964.51" + wire width 64 $1\data_r2__fast2[63:0] + attribute \src "libresoc.v:182577.3-182598.6" + wire $1\data_r2__fast2_ok$next[0:0]$13612 + attribute \src "libresoc.v:181968.7-181968.31" + wire $1\data_r2__fast2_ok[0:0] + attribute \src "libresoc.v:182599.3-182620.6" + wire width 64 $1\data_r3__nia$next[63:0]$13619 + attribute \src "libresoc.v:181972.14-181972.49" + wire width 64 $1\data_r3__nia[63:0] + attribute \src "libresoc.v:182599.3-182620.6" + wire $1\data_r3__nia_ok$next[0:0]$13620 + attribute \src "libresoc.v:181976.7-181976.29" + wire $1\data_r3__nia_ok[0:0] + attribute \src "libresoc.v:182621.3-182642.6" + wire width 64 $1\data_r4__msr$next[63:0]$13627 + attribute \src "libresoc.v:181980.14-181980.49" + wire width 64 $1\data_r4__msr[63:0] + attribute \src "libresoc.v:182621.3-182642.6" + wire $1\data_r4__msr_ok$next[0:0]$13628 + attribute \src "libresoc.v:181984.7-181984.29" + wire $1\data_r4__msr_ok[0:0] + attribute \src "libresoc.v:182701.3-182710.6" + wire width 64 $1\dest1_o[63:0] + attribute \src "libresoc.v:182711.3-182720.6" + wire width 64 $1\dest2_o[63:0] + attribute \src "libresoc.v:182721.3-182730.6" + wire width 64 $1\dest3_o[63:0] + attribute \src "libresoc.v:182731.3-182740.6" + wire width 64 $1\dest4_o[63:0] + attribute \src "libresoc.v:182741.3-182750.6" + wire width 64 $1\dest5_o[63:0] + attribute \src "libresoc.v:182471.3-182479.6" + wire $1\opc_l_r_opc$next[0:0]$13562 + attribute \src "libresoc.v:182015.7-182015.25" + wire $1\opc_l_r_opc[0:0] + attribute \src "libresoc.v:182462.3-182470.6" + wire $1\opc_l_s_opc$next[0:0]$13559 + attribute \src "libresoc.v:182019.7-182019.25" + wire $1\opc_l_s_opc[0:0] + attribute \src "libresoc.v:182751.3-182759.6" + wire width 5 $1\prev_wr_go$next[4:0]$13657 + attribute \src "libresoc.v:182126.13-182126.31" + wire width 5 $1\prev_wr_go[4:0] + attribute \src "libresoc.v:182416.3-182425.6" + wire $1\req_done[0:0] + attribute \src "libresoc.v:182507.3-182515.6" + wire width 5 $1\req_l_r_req$next[4:0]$13574 + attribute \src "libresoc.v:182134.13-182134.32" + wire width 5 $1\req_l_r_req[4:0] + attribute \src "libresoc.v:182498.3-182506.6" + wire width 5 $1\req_l_s_req$next[4:0]$13571 + attribute \src "libresoc.v:182138.13-182138.32" + wire width 5 $1\req_l_s_req[4:0] + attribute \src "libresoc.v:182435.3-182443.6" + wire $1\rok_l_r_rdok$next[0:0]$13550 + attribute \src "libresoc.v:182150.7-182150.26" + wire $1\rok_l_r_rdok[0:0] + attribute \src "libresoc.v:182426.3-182434.6" + wire $1\rok_l_s_rdok$next[0:0]$13547 + attribute \src "libresoc.v:182154.7-182154.26" + wire $1\rok_l_s_rdok[0:0] + attribute \src "libresoc.v:182453.3-182461.6" + wire $1\rst_l_r_rst$next[0:0]$13556 + attribute \src "libresoc.v:182158.7-182158.25" + wire $1\rst_l_r_rst[0:0] + attribute \src "libresoc.v:182444.3-182452.6" + wire $1\rst_l_s_rst$next[0:0]$13553 + attribute \src "libresoc.v:182162.7-182162.25" + wire $1\rst_l_s_rst[0:0] + attribute \src "libresoc.v:182489.3-182497.6" + wire width 4 $1\src_l_r_src$next[3:0]$13568 + attribute \src "libresoc.v:182178.13-182178.31" + wire width 4 $1\src_l_r_src[3:0] + attribute \src "libresoc.v:182480.3-182488.6" + wire width 4 $1\src_l_s_src$next[3:0]$13565 + attribute \src "libresoc.v:182182.13-182182.31" + wire width 4 $1\src_l_s_src[3:0] + attribute \src "libresoc.v:182643.3-182652.6" + wire width 64 $1\src_r0$next[63:0]$13634 + attribute \src "libresoc.v:182186.14-182186.43" + wire width 64 $1\src_r0[63:0] + attribute \src "libresoc.v:182653.3-182662.6" + wire width 64 $1\src_r1$next[63:0]$13637 + attribute \src "libresoc.v:182190.14-182190.43" + wire width 64 $1\src_r1[63:0] + attribute \src "libresoc.v:182663.3-182672.6" + wire width 64 $1\src_r2$next[63:0]$13640 + attribute \src "libresoc.v:182194.14-182194.43" + wire width 64 $1\src_r2[63:0] + attribute \src "libresoc.v:182673.3-182682.6" + wire width 64 $1\src_r3$next[63:0]$13643 + attribute \src "libresoc.v:182198.14-182198.43" + wire width 64 $1\src_r3[63:0] + attribute \src "libresoc.v:182533.3-182554.6" + wire width 64 $2\data_r0__o$next[63:0]$13597 + attribute \src "libresoc.v:182533.3-182554.6" + wire $2\data_r0__o_ok$next[0:0]$13598 + attribute \src "libresoc.v:182555.3-182576.6" + wire width 64 $2\data_r1__fast1$next[63:0]$13605 + attribute \src "libresoc.v:182555.3-182576.6" + wire $2\data_r1__fast1_ok$next[0:0]$13606 + attribute \src "libresoc.v:182577.3-182598.6" + wire width 64 $2\data_r2__fast2$next[63:0]$13613 + attribute \src "libresoc.v:182577.3-182598.6" + wire $2\data_r2__fast2_ok$next[0:0]$13614 + attribute \src "libresoc.v:182599.3-182620.6" + wire width 64 $2\data_r3__nia$next[63:0]$13621 + attribute \src "libresoc.v:182599.3-182620.6" + wire $2\data_r3__nia_ok$next[0:0]$13622 + attribute \src "libresoc.v:182621.3-182642.6" + wire width 64 $2\data_r4__msr$next[63:0]$13629 + attribute \src "libresoc.v:182621.3-182642.6" + wire $2\data_r4__msr_ok$next[0:0]$13630 + attribute \src "libresoc.v:182533.3-182554.6" + wire $3\data_r0__o_ok$next[0:0]$13599 + attribute \src "libresoc.v:182555.3-182576.6" + wire $3\data_r1__fast1_ok$next[0:0]$13607 + attribute \src "libresoc.v:182577.3-182598.6" + wire $3\data_r2__fast2_ok$next[0:0]$13615 + attribute \src "libresoc.v:182599.3-182620.6" + wire $3\data_r3__nia_ok$next[0:0]$13623 + attribute \src "libresoc.v:182621.3-182642.6" + wire $3\data_r4__msr_ok$next[0:0]$13631 + attribute \src "libresoc.v:182204.18-182204.112" + wire width 4 $and$libresoc.v:182204$13447_Y + attribute \src "libresoc.v:182205.19-182205.125" + wire $and$libresoc.v:182205$13448_Y + attribute \src "libresoc.v:182206.19-182206.125" + wire $and$libresoc.v:182206$13449_Y + attribute \src "libresoc.v:182207.19-182207.125" + wire $and$libresoc.v:182207$13450_Y + attribute \src "libresoc.v:182208.19-182208.125" + wire $and$libresoc.v:182208$13451_Y + attribute \src "libresoc.v:182209.19-182209.125" + wire $and$libresoc.v:182209$13452_Y + attribute \src "libresoc.v:182210.19-182210.157" + wire width 5 $and$libresoc.v:182210$13453_Y + attribute \src "libresoc.v:182211.19-182211.121" + wire width 5 $and$libresoc.v:182211$13454_Y + attribute \src "libresoc.v:182212.19-182212.127" + wire $and$libresoc.v:182212$13455_Y + attribute \src "libresoc.v:182213.19-182213.127" + wire $and$libresoc.v:182213$13456_Y + attribute \src "libresoc.v:182214.18-182214.110" + wire $and$libresoc.v:182214$13457_Y + attribute \src "libresoc.v:182215.19-182215.127" + wire $and$libresoc.v:182215$13458_Y + attribute \src "libresoc.v:182216.19-182216.127" + wire $and$libresoc.v:182216$13459_Y + attribute \src "libresoc.v:182217.19-182217.127" + wire $and$libresoc.v:182217$13460_Y + attribute \src "libresoc.v:182219.18-182219.98" + wire $and$libresoc.v:182219$13462_Y + attribute \src "libresoc.v:182221.18-182221.100" + wire $and$libresoc.v:182221$13464_Y + attribute \src "libresoc.v:182222.18-182222.171" + wire width 5 $and$libresoc.v:182222$13465_Y + attribute \src "libresoc.v:182224.18-182224.119" + wire width 5 $and$libresoc.v:182224$13467_Y + attribute \src "libresoc.v:182227.18-182227.116" + wire $and$libresoc.v:182227$13470_Y + attribute \src "libresoc.v:182231.17-182231.123" + wire $and$libresoc.v:182231$13474_Y + attribute \src "libresoc.v:182233.18-182233.113" + wire $and$libresoc.v:182233$13476_Y + attribute \src "libresoc.v:182234.18-182234.125" + wire width 5 $and$libresoc.v:182234$13477_Y + attribute \src "libresoc.v:182236.18-182236.112" + wire $and$libresoc.v:182236$13479_Y + attribute \src "libresoc.v:182238.18-182238.127" + wire $and$libresoc.v:182238$13481_Y + attribute \src "libresoc.v:182239.18-182239.127" + wire $and$libresoc.v:182239$13482_Y + attribute \src "libresoc.v:182240.18-182240.117" + wire $and$libresoc.v:182240$13483_Y + attribute \src "libresoc.v:182245.18-182245.131" + wire $and$libresoc.v:182245$13488_Y + attribute \src "libresoc.v:182246.18-182246.124" + wire width 5 $and$libresoc.v:182246$13489_Y + attribute \src "libresoc.v:182249.18-182249.116" + wire $and$libresoc.v:182249$13492_Y + attribute \src "libresoc.v:182250.18-182250.120" + wire $and$libresoc.v:182250$13493_Y + attribute \src "libresoc.v:182251.18-182251.120" + wire $and$libresoc.v:182251$13494_Y + attribute \src "libresoc.v:182252.18-182252.118" + wire $and$libresoc.v:182252$13495_Y + attribute \src "libresoc.v:182253.18-182253.118" + wire $and$libresoc.v:182253$13496_Y + attribute \src "libresoc.v:182259.18-182259.135" + wire $and$libresoc.v:182259$13502_Y + attribute \src "libresoc.v:182260.18-182260.133" + wire $and$libresoc.v:182260$13503_Y + attribute \src "libresoc.v:182261.18-182261.160" + wire width 4 $and$libresoc.v:182261$13504_Y + attribute \src "libresoc.v:182262.18-182262.112" + wire width 4 $and$libresoc.v:182262$13505_Y + attribute \src "libresoc.v:182235.18-182235.113" + wire $eq$libresoc.v:182235$13478_Y + attribute \src "libresoc.v:182237.18-182237.119" + wire $eq$libresoc.v:182237$13480_Y + attribute \src "libresoc.v:182218.18-182218.97" + wire $not$libresoc.v:182218$13461_Y + attribute \src "libresoc.v:182220.18-182220.99" + wire $not$libresoc.v:182220$13463_Y + attribute \src "libresoc.v:182223.18-182223.113" + wire width 5 $not$libresoc.v:182223$13466_Y + attribute \src "libresoc.v:182226.18-182226.106" + wire $not$libresoc.v:182226$13469_Y + attribute \src "libresoc.v:182232.18-182232.121" + wire $not$libresoc.v:182232$13475_Y + attribute \src "libresoc.v:182247.17-182247.113" + wire width 4 $not$libresoc.v:182247$13490_Y + attribute \src "libresoc.v:182263.18-182263.114" + wire width 4 $not$libresoc.v:182263$13506_Y + attribute \src "libresoc.v:182230.18-182230.112" + wire $or$libresoc.v:182230$13473_Y + attribute \src "libresoc.v:182241.18-182241.122" + wire $or$libresoc.v:182241$13484_Y + attribute \src "libresoc.v:182242.18-182242.124" + wire $or$libresoc.v:182242$13485_Y + attribute \src "libresoc.v:182243.18-182243.181" + wire width 5 $or$libresoc.v:182243$13486_Y + attribute \src "libresoc.v:182244.18-182244.168" + wire width 4 $or$libresoc.v:182244$13487_Y + attribute \src "libresoc.v:182248.18-182248.120" + wire width 5 $or$libresoc.v:182248$13491_Y + attribute \src "libresoc.v:182258.17-182258.117" + wire width 4 $or$libresoc.v:182258$13501_Y + attribute \src "libresoc.v:182203.17-182203.104" + wire $reduce_and$libresoc.v:182203$13446_Y + attribute \src "libresoc.v:182225.18-182225.106" + wire $reduce_or$libresoc.v:182225$13468_Y + attribute \src "libresoc.v:182228.18-182228.113" + wire $reduce_or$libresoc.v:182228$13471_Y + attribute \src "libresoc.v:182229.18-182229.112" + wire $reduce_or$libresoc.v:182229$13472_Y + attribute \src "libresoc.v:182254.18-182254.118" + wire width 64 $ternary$libresoc.v:182254$13497_Y + attribute \src "libresoc.v:182255.18-182255.118" + wire width 64 $ternary$libresoc.v:182255$13498_Y + attribute \src "libresoc.v:182256.18-182256.118" + wire width 64 $ternary$libresoc.v:182256$13499_Y + attribute \src "libresoc.v:182257.18-182257.118" + wire width 64 $ternary$libresoc.v:182257$13500_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + wire \$101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + wire \$103 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + wire \$105 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + wire \$107 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + wire \$109 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" + wire width 5 \$111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" + wire width 5 \$113 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + wire \$115 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + wire \$117 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + wire \$119 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + wire \$121 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + wire \$123 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire \$17 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" + wire width 5 \$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + wire width 5 \$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + wire width 5 \$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + wire \$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + wire \$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + wire \$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + wire \$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + wire \$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + wire width 5 \$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + wire \$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + wire \$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + wire \$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + wire \$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + wire \$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + wire \$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" + wire \$57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" + wire \$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + wire width 4 \$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" + wire width 5 \$61 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" + wire width 4 \$63 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" + wire \$65 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" + wire width 5 \$67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" + wire width 5 \$69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + wire \$71 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + wire \$73 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + wire \$75 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + wire \$77 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + wire \$79 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + wire width 4 \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 64 \$81 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 64 \$83 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 64 \$85 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 64 \$87 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" + wire \$89 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" + wire \$91 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + wire width 4 \$93 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + wire width 4 \$95 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + wire width 4 \$97 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + wire width 4 \$99 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:187" + wire \all_rd + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire \all_rd_dly + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire \all_rd_dly$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:192" + wire \all_rd_pulse + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + wire \all_rd_rise + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:196" + wire \alu_done + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire \alu_done_dly + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire \alu_done_dly$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + wire \alu_done_rise + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire \alu_l_q_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \alu_l_r_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \alu_l_r_alu$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \alu_l_s_alu + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:197" + wire \alu_pulse + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198" + wire width 5 \alu_pulsem + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \alu_trap0_fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \alu_trap0_fast1$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \alu_trap0_fast2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \alu_trap0_fast2$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \alu_trap0_msr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire \alu_trap0_n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire \alu_trap0_n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \alu_trap0_nia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \alu_trap0_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire \alu_trap0_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire \alu_trap0_p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \alu_trap0_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \alu_trap0_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \alu_trap0_trap_op__cia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \alu_trap0_trap_op__cia$next + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \alu_trap0_trap_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \alu_trap0_trap_op__fn_unit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \alu_trap0_trap_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \alu_trap0_trap_op__insn$next + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \alu_trap0_trap_op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \alu_trap0_trap_op__insn_type$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_trap0_trap_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_trap0_trap_op__is_32bit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \alu_trap0_trap_op__msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \alu_trap0_trap_op__msr$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \alu_trap0_trap_op__trapaddr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \alu_trap0_trap_op__trapaddr$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \alu_trap0_trap_op__traptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \alu_trap0_trap_op__traptype$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire \alui_l_q_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \alui_l_r_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \alui_l_r_alui$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \alui_l_s_alui + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 31 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 30 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" + wire output 10 \cu_busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:108" + wire \cu_done_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:104" + wire \cu_go_die_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" + wire input 9 \cu_issue_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 4 input 13 \cu_rd__go_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 4 output 12 \cu_rd__rel_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" + wire width 4 input 11 \cu_rdmaskn_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:102" + wire \cu_shadown_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 5 input 20 \cu_wr__go_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 5 output 19 \cu_wr__rel_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:97" + wire width 5 \cu_wrmask_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 64 \data_r0__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 64 \data_r0__o$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r0__o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r0__o_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 64 \data_r1__fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 64 \data_r1__fast1$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r1__fast1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r1__fast1_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 64 \data_r2__fast2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 64 \data_r2__fast2$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r2__fast2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r2__fast2_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 64 \data_r3__nia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 64 \data_r3__nia$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r3__nia_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r3__nia_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 64 \data_r4__msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 64 \data_r4__msr$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r4__msr_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r4__msr_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 21 \dest1_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 24 \dest2_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 25 \dest3_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 27 \dest4_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 29 \dest5_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 22 \fast1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 23 \fast2_ok + attribute \src "libresoc.v:181615.7-181615.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 28 \msr_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 26 \nia_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 18 \o_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire \opc_l_q_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \opc_l_r_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \opc_l_r_opc$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \opc_l_s_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \opc_l_s_opc$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 5 \oper_i_alu_trap0__cia + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 2 \oper_i_alu_trap0__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 3 \oper_i_alu_trap0__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \oper_i_alu_trap0__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 6 \oper_i_alu_trap0__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 4 \oper_i_alu_trap0__msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 input 8 \oper_i_alu_trap0__trapaddr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 7 \oper_i_alu_trap0__traptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" + wire width 5 \prev_wr_go + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" + wire width 5 \prev_wr_go$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212" + wire \req_done + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 5 \req_l_q_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 5 \req_l_r_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 5 \req_l_r_req$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 5 \req_l_s_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 5 \req_l_s_req$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226" + wire \reset + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:229" + wire width 4 \reset_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:228" + wire width 5 \reset_w + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire \rok_l_q_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \rok_l_r_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \rok_l_r_rdok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \rok_l_s_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \rok_l_s_rdok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \rst_l_r_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \rst_l_r_rst$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \rst_l_s_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \rst_l_s_rst$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227" + wire \rst_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 14 \src1_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 15 \src2_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 16 \src3_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 17 \src4_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 4 \src_l_q_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 4 \src_l_r_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 4 \src_l_r_src$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 4 \src_l_s_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 4 \src_l_s_src$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 64 \src_r0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 64 \src_r0$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 64 \src_r1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 64 \src_r1$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 64 \src_r2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 64 \src_r2$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 64 \src_r3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 64 \src_r3$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" + wire \wr_any + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + cell $and $and$libresoc.v:182204$13447 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \$95 + connect \B \$97 + connect \Y $and$libresoc.v:182204$13447_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + cell $and $and$libresoc.v:182205$13448 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_busy_o + connect \B \cu_shadown_i + connect \Y $and$libresoc.v:182205$13448_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + cell $and $and$libresoc.v:182206$13449 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_busy_o + connect \B \cu_shadown_i + connect \Y $and$libresoc.v:182206$13449_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + cell $and $and$libresoc.v:182207$13450 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_busy_o + connect \B \cu_shadown_i + connect \Y $and$libresoc.v:182207$13450_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + cell $and $and$libresoc.v:182208$13451 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_busy_o + connect \B \cu_shadown_i + connect \Y $and$libresoc.v:182208$13451_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + cell $and $and$libresoc.v:182209$13452 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_busy_o + connect \B \cu_shadown_i + connect \Y $and$libresoc.v:182209$13452_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" + cell $and $and$libresoc.v:182210$13453 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \req_l_q_req + connect \B { \$101 \$103 \$105 \$107 \$109 } + connect \Y $and$libresoc.v:182210$13453_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" + cell $and $and$libresoc.v:182211$13454 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \$111 + connect \B \cu_wrmask_o + connect \Y $and$libresoc.v:182211$13454_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + cell $and $and$libresoc.v:182212$13455 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_wr__go_i [0] + connect \B \cu_busy_o + connect \Y $and$libresoc.v:182212$13455_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + cell $and $and$libresoc.v:182213$13456 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_wr__go_i [1] + connect \B \cu_busy_o + connect \Y $and$libresoc.v:182213$13456_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $and $and$libresoc.v:182214$13457 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \$5 + connect \Y $and$libresoc.v:182214$13457_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + cell $and $and$libresoc.v:182215$13458 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_wr__go_i [2] + connect \B \cu_busy_o + connect \Y $and$libresoc.v:182215$13458_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + cell $and $and$libresoc.v:182216$13459 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_wr__go_i [3] + connect \B \cu_busy_o + connect \Y $and$libresoc.v:182216$13459_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + cell $and $and$libresoc.v:182217$13460 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_wr__go_i [4] + connect \B \cu_busy_o + connect \Y $and$libresoc.v:182217$13460_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $and$libresoc.v:182219$13462 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \all_rd + connect \B \$13 + connect \Y $and$libresoc.v:182219$13462_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $and$libresoc.v:182221$13464 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_done + connect \B \$17 + connect \Y $and$libresoc.v:182221$13464_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" + cell $and $and$libresoc.v:182222$13465 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \cu_wr__go_i + connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } + connect \Y $and$libresoc.v:182222$13465_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $and $and$libresoc.v:182224$13467 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \cu_wr__rel_o + connect \B \$25 + connect \Y $and$libresoc.v:182224$13467_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $and $and$libresoc.v:182227$13470 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_busy_o + connect \B \$23 + connect \Y $and$libresoc.v:182227$13470_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" + cell $and $and$libresoc.v:182231$13474 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_busy_o + connect \B \rok_l_q_rdok + connect \Y $and$libresoc.v:182231$13474_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + cell $and $and$libresoc.v:182233$13476 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_any + connect \B \$39 + connect \Y $and$libresoc.v:182233$13476_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + cell $and $and$libresoc.v:182234$13477 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \req_l_q_req + connect \B \cu_wrmask_o + connect \Y $and$libresoc.v:182234$13477_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + cell $and $and$libresoc.v:182236$13479 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$41 + connect \B \$45 + connect \Y $and$libresoc.v:182236$13479_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + cell $and $and$libresoc.v:182238$13481 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$49 + connect \B \alu_trap0_n_ready_i + connect \Y $and$libresoc.v:182238$13481_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + cell $and $and$libresoc.v:182239$13482 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$51 + connect \B \alu_trap0_n_valid_o + connect \Y $and$libresoc.v:182239$13482_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + cell $and $and$libresoc.v:182240$13483 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$53 + connect \B \cu_busy_o + connect \Y $and$libresoc.v:182240$13483_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" + cell $and $and$libresoc.v:182245$13488 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_trap0_n_valid_o + connect \B \cu_busy_o + connect \Y $and$libresoc.v:182245$13488_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" + cell $and $and$libresoc.v:182246$13489 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \alu_pulsem + connect \B \cu_wrmask_o + connect \Y $and$libresoc.v:182246$13489_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + cell $and $and$libresoc.v:182249$13492 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \o_ok + connect \B \cu_busy_o + connect \Y $and$libresoc.v:182249$13492_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + cell $and $and$libresoc.v:182250$13493 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fast1_ok + connect \B \cu_busy_o + connect \Y $and$libresoc.v:182250$13493_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + cell $and $and$libresoc.v:182251$13494 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fast2_ok + connect \B \cu_busy_o + connect \Y $and$libresoc.v:182251$13494_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + cell $and $and$libresoc.v:182252$13495 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \nia_ok + connect \B \cu_busy_o + connect \Y $and$libresoc.v:182252$13495_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + cell $and $and$libresoc.v:182253$13496 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \msr_ok + connect \B \cu_busy_o + connect \Y $and$libresoc.v:182253$13496_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" + cell $and $and$libresoc.v:182259$13502 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_trap0_p_ready_o + connect \B \alui_l_q_alui + connect \Y $and$libresoc.v:182259$13502_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" + cell $and $and$libresoc.v:182260$13503 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_trap0_n_valid_o + connect \B \alu_l_q_alu + connect \Y $and$libresoc.v:182260$13503_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + cell $and $and$libresoc.v:182261$13504 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \src_l_q_src + connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } + connect \Y $and$libresoc.v:182261$13504_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + cell $and $and$libresoc.v:182262$13505 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \$93 + connect \B 4'1111 + connect \Y $and$libresoc.v:182262$13505_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + cell $eq $eq$libresoc.v:182235$13478 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$43 + connect \B 1'0 + connect \Y $eq$libresoc.v:182235$13478_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + cell $eq $eq$libresoc.v:182237$13480 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_wrmask_o + connect \B 1'0 + connect \Y $eq$libresoc.v:182237$13480_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $not$libresoc.v:182218$13461 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \all_rd_dly + connect \Y $not$libresoc.v:182218$13461_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $not$libresoc.v:182220$13463 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_done_dly + connect \Y $not$libresoc.v:182220$13463_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $not $not$libresoc.v:182223$13466 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \cu_wrmask_o + connect \Y $not$libresoc.v:182223$13466_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $not $not$libresoc.v:182226$13469 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$24 + connect \Y $not$libresoc.v:182226$13469_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + cell $not $not$libresoc.v:182232$13475 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_trap0_n_ready_i + connect \Y $not$libresoc.v:182232$13475_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $not $not$libresoc.v:182247$13490 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \cu_rd__rel_o + connect \Y $not$libresoc.v:182247$13490_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + cell $not $not$libresoc.v:182263$13506 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \cu_rdmaskn_i + connect \Y $not$libresoc.v:182263$13506_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $or $or$libresoc.v:182230$13473 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$33 + connect \B \$35 + connect \Y $or$libresoc.v:182230$13473_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" + cell $or $or$libresoc.v:182241$13484 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \req_done + connect \B \cu_go_die_i + connect \Y $or$libresoc.v:182241$13484_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" + cell $or $or$libresoc.v:182242$13485 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_issue_i + connect \B \cu_go_die_i + connect \Y $or$libresoc.v:182242$13485_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" + cell $or $or$libresoc.v:182243$13486 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \cu_wr__go_i + connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } + connect \Y $or$libresoc.v:182243$13486_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" + cell $or $or$libresoc.v:182244$13487 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \cu_rd__go_i + connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } + connect \Y $or$libresoc.v:182244$13487_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" + cell $or $or$libresoc.v:182248$13491 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \reset_w + connect \B \prev_wr_go + connect \Y $or$libresoc.v:182248$13491_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $or $or$libresoc.v:182258$13501 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \$6 + connect \B \cu_rd__go_i + connect \Y $or$libresoc.v:182258$13501_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $reduce_and $reduce_and$libresoc.v:182203$13446 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $reduce_and$libresoc.v:182203$13446_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $reduce_or $reduce_or$libresoc.v:182225$13468 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \$27 + connect \Y $reduce_or$libresoc.v:182225$13468_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $reduce_or $reduce_or$libresoc.v:182228$13471 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \cu_wr__go_i + connect \Y $reduce_or$libresoc.v:182228$13471_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $reduce_or $reduce_or$libresoc.v:182229$13472 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \prev_wr_go + connect \Y $reduce_or$libresoc.v:182229$13472_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $ternary$libresoc.v:182254$13497 + parameter \WIDTH 64 + connect \A \src_r0 + connect \B \src1_i + connect \S \src_l_q_src [0] + connect \Y $ternary$libresoc.v:182254$13497_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $ternary$libresoc.v:182255$13498 + parameter \WIDTH 64 + connect \A \src_r1 + connect \B \src2_i + connect \S \src_l_q_src [1] + connect \Y $ternary$libresoc.v:182255$13498_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $ternary$libresoc.v:182256$13499 + parameter \WIDTH 64 + connect \A \src_r2 + connect \B \src3_i + connect \S \src_l_q_src [2] + connect \Y $ternary$libresoc.v:182256$13499_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $ternary$libresoc.v:182257$13500 + parameter \WIDTH 64 + connect \A \src_r3 + connect \B \src4_i + connect \S \src_l_q_src [3] + connect \Y $ternary$libresoc.v:182257$13500_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:182338.14-182344.4" + cell \alu_l$42 \alu_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_alu \alu_l_q_alu + connect \r_alu \alu_l_r_alu + connect \s_alu \alu_l_s_alu + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:182345.13-182374.4" + cell \alu_trap0 \alu_trap0 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \fast1 \alu_trap0_fast1 + connect \fast1$1 \alu_trap0_fast1$1 + connect \fast1_ok \fast1_ok + connect \fast2 \alu_trap0_fast2 + connect \fast2$2 \alu_trap0_fast2$2 + connect \fast2_ok \fast2_ok + connect \msr \alu_trap0_msr + connect \msr_ok \msr_ok + connect \n_ready_i \alu_trap0_n_ready_i + connect \n_valid_o \alu_trap0_n_valid_o + connect \nia \alu_trap0_nia + connect \nia_ok \nia_ok + connect \o \alu_trap0_o + connect \o_ok \o_ok + connect \p_ready_o \alu_trap0_p_ready_o + connect \p_valid_i \alu_trap0_p_valid_i + connect \ra \alu_trap0_ra + connect \rb \alu_trap0_rb + connect \trap_op__cia \alu_trap0_trap_op__cia + connect \trap_op__fn_unit \alu_trap0_trap_op__fn_unit + connect \trap_op__insn \alu_trap0_trap_op__insn + connect \trap_op__insn_type \alu_trap0_trap_op__insn_type + connect \trap_op__is_32bit \alu_trap0_trap_op__is_32bit + connect \trap_op__msr \alu_trap0_trap_op__msr + connect \trap_op__trapaddr \alu_trap0_trap_op__trapaddr + connect \trap_op__traptype \alu_trap0_trap_op__traptype + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:182375.15-182381.4" + cell \alui_l$41 \alui_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_alui \alui_l_q_alui + connect \r_alui \alui_l_r_alui + connect \s_alui \alui_l_s_alui + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:182382.14-182388.4" + cell \opc_l$37 \opc_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_opc \opc_l_q_opc + connect \r_opc \opc_l_r_opc + connect \s_opc \opc_l_s_opc + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:182389.14-182395.4" + cell \req_l$38 \req_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_req \req_l_q_req + connect \r_req \req_l_r_req + connect \s_req \req_l_s_req + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:182396.14-182402.4" + cell \rok_l$40 \rok_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_rdok \rok_l_q_rdok + connect \r_rdok \rok_l_r_rdok + connect \s_rdok \rok_l_s_rdok + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:182403.14-182408.4" + cell \rst_l$39 \rst_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \r_rst \rst_l_r_rst + connect \s_rst \rst_l_s_rst + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:182409.14-182415.4" + cell \src_l$36 \src_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_src \src_l_q_src + connect \r_src \src_l_r_src + connect \s_src \src_l_s_src + end + attribute \src "libresoc.v:181615.7-181615.20" + process $proc$libresoc.v:181615$13658 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:181741.7-181741.24" + process $proc$libresoc.v:181741$13659 + assign { } { } + assign $1\all_rd_dly[0:0] 1'0 + sync always + sync init + update \all_rd_dly $1\all_rd_dly[0:0] + end + attribute \src "libresoc.v:181751.7-181751.26" + process $proc$libresoc.v:181751$13660 + assign { } { } + assign $1\alu_done_dly[0:0] 1'0 + sync always + sync init + update \alu_done_dly $1\alu_done_dly[0:0] + end + attribute \src "libresoc.v:181759.7-181759.25" + process $proc$libresoc.v:181759$13661 + assign { } { } + assign $1\alu_l_r_alu[0:0] 1'1 + sync always + sync init + update \alu_l_r_alu $1\alu_l_r_alu[0:0] + end + attribute \src "libresoc.v:181795.14-181795.59" + process $proc$libresoc.v:181795$13662 + assign { } { } + assign $1\alu_trap0_trap_op__cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \alu_trap0_trap_op__cia $1\alu_trap0_trap_op__cia[63:0] + end + attribute \src "libresoc.v:181812.14-181812.50" + process $proc$libresoc.v:181812$13663 + assign { } { } + assign $1\alu_trap0_trap_op__fn_unit[11:0] 12'000000000000 + sync always + sync init + update \alu_trap0_trap_op__fn_unit $1\alu_trap0_trap_op__fn_unit[11:0] + end + attribute \src "libresoc.v:181816.14-181816.45" + process $proc$libresoc.v:181816$13664 + assign { } { } + assign $1\alu_trap0_trap_op__insn[31:0] 0 + sync always + sync init + update \alu_trap0_trap_op__insn $1\alu_trap0_trap_op__insn[31:0] + end + attribute \src "libresoc.v:181894.13-181894.49" + process $proc$libresoc.v:181894$13665 + assign { } { } + assign $1\alu_trap0_trap_op__insn_type[6:0] 7'0000000 + sync always + sync init + update \alu_trap0_trap_op__insn_type $1\alu_trap0_trap_op__insn_type[6:0] + end + attribute \src "libresoc.v:181898.7-181898.41" + process $proc$libresoc.v:181898$13666 + assign { } { } + assign $1\alu_trap0_trap_op__is_32bit[0:0] 1'0 + sync always + sync init + update \alu_trap0_trap_op__is_32bit $1\alu_trap0_trap_op__is_32bit[0:0] + end + attribute \src "libresoc.v:181902.14-181902.59" + process $proc$libresoc.v:181902$13667 + assign { } { } + assign $1\alu_trap0_trap_op__msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \alu_trap0_trap_op__msr $1\alu_trap0_trap_op__msr[63:0] + end + attribute \src "libresoc.v:181906.14-181906.52" + process $proc$libresoc.v:181906$13668 + assign { } { } + assign $1\alu_trap0_trap_op__trapaddr[12:0] 13'0000000000000 + sync always + sync init + update \alu_trap0_trap_op__trapaddr $1\alu_trap0_trap_op__trapaddr[12:0] + end + attribute \src "libresoc.v:181910.13-181910.48" + process $proc$libresoc.v:181910$13669 + assign { } { } + assign $1\alu_trap0_trap_op__traptype[6:0] 7'0000000 + sync always + sync init + update \alu_trap0_trap_op__traptype $1\alu_trap0_trap_op__traptype[6:0] + end + attribute \src "libresoc.v:181916.7-181916.27" + process $proc$libresoc.v:181916$13670 + assign { } { } + assign $1\alui_l_r_alui[0:0] 1'1 + sync always + sync init + update \alui_l_r_alui $1\alui_l_r_alui[0:0] + end + attribute \src "libresoc.v:181948.14-181948.47" + process $proc$libresoc.v:181948$13671 + assign { } { } + assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \data_r0__o $1\data_r0__o[63:0] + end + attribute \src "libresoc.v:181952.7-181952.27" + process $proc$libresoc.v:181952$13672 + assign { } { } + assign $1\data_r0__o_ok[0:0] 1'0 + sync always + sync init + update \data_r0__o_ok $1\data_r0__o_ok[0:0] + end + attribute \src "libresoc.v:181956.14-181956.51" + process $proc$libresoc.v:181956$13673 + assign { } { } + assign $1\data_r1__fast1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \data_r1__fast1 $1\data_r1__fast1[63:0] + end + attribute \src "libresoc.v:181960.7-181960.31" + process $proc$libresoc.v:181960$13674 + assign { } { } + assign $1\data_r1__fast1_ok[0:0] 1'0 + sync always + sync init + update \data_r1__fast1_ok $1\data_r1__fast1_ok[0:0] + end + attribute \src "libresoc.v:181964.14-181964.51" + process $proc$libresoc.v:181964$13675 + assign { } { } + assign $1\data_r2__fast2[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \data_r2__fast2 $1\data_r2__fast2[63:0] + end + attribute \src "libresoc.v:181968.7-181968.31" + process $proc$libresoc.v:181968$13676 + assign { } { } + assign $1\data_r2__fast2_ok[0:0] 1'0 + sync always + sync init + update \data_r2__fast2_ok $1\data_r2__fast2_ok[0:0] + end + attribute \src "libresoc.v:181972.14-181972.49" + process $proc$libresoc.v:181972$13677 + assign { } { } + assign $1\data_r3__nia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \data_r3__nia $1\data_r3__nia[63:0] + end + attribute \src "libresoc.v:181976.7-181976.29" + process $proc$libresoc.v:181976$13678 + assign { } { } + assign $1\data_r3__nia_ok[0:0] 1'0 + sync always + sync init + update \data_r3__nia_ok $1\data_r3__nia_ok[0:0] + end + attribute \src "libresoc.v:181980.14-181980.49" + process $proc$libresoc.v:181980$13679 + assign { } { } + assign $1\data_r4__msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \data_r4__msr $1\data_r4__msr[63:0] + end + attribute \src "libresoc.v:181984.7-181984.29" + process $proc$libresoc.v:181984$13680 + assign { } { } + assign $1\data_r4__msr_ok[0:0] 1'0 + sync always + sync init + update \data_r4__msr_ok $1\data_r4__msr_ok[0:0] + end + attribute \src "libresoc.v:182015.7-182015.25" + process $proc$libresoc.v:182015$13681 + assign { } { } + assign $1\opc_l_r_opc[0:0] 1'1 + sync always + sync init + update \opc_l_r_opc $1\opc_l_r_opc[0:0] + end + attribute \src "libresoc.v:182019.7-182019.25" + process $proc$libresoc.v:182019$13682 + assign { } { } + assign $1\opc_l_s_opc[0:0] 1'0 + sync always + sync init + update \opc_l_s_opc $1\opc_l_s_opc[0:0] + end + attribute \src "libresoc.v:182126.13-182126.31" + process $proc$libresoc.v:182126$13683 + assign { } { } + assign $1\prev_wr_go[4:0] 5'00000 + sync always + sync init + update \prev_wr_go $1\prev_wr_go[4:0] + end + attribute \src "libresoc.v:182134.13-182134.32" + process $proc$libresoc.v:182134$13684 + assign { } { } + assign $1\req_l_r_req[4:0] 5'11111 + sync always + sync init + update \req_l_r_req $1\req_l_r_req[4:0] + end + attribute \src "libresoc.v:182138.13-182138.32" + process $proc$libresoc.v:182138$13685 + assign { } { } + assign $1\req_l_s_req[4:0] 5'00000 + sync always + sync init + update \req_l_s_req $1\req_l_s_req[4:0] + end + attribute \src "libresoc.v:182150.7-182150.26" + process $proc$libresoc.v:182150$13686 + assign { } { } + assign $1\rok_l_r_rdok[0:0] 1'1 + sync always + sync init + update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] + end + attribute \src "libresoc.v:182154.7-182154.26" + process $proc$libresoc.v:182154$13687 + assign { } { } + assign $1\rok_l_s_rdok[0:0] 1'0 + sync always + sync init + update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] + end + attribute \src "libresoc.v:182158.7-182158.25" + process $proc$libresoc.v:182158$13688 + assign { } { } + assign $1\rst_l_r_rst[0:0] 1'1 + sync always + sync init + update \rst_l_r_rst $1\rst_l_r_rst[0:0] + end + attribute \src "libresoc.v:182162.7-182162.25" + process $proc$libresoc.v:182162$13689 + assign { } { } + assign $1\rst_l_s_rst[0:0] 1'0 + sync always + sync init + update \rst_l_s_rst $1\rst_l_s_rst[0:0] + end + attribute \src "libresoc.v:182178.13-182178.31" + process $proc$libresoc.v:182178$13690 + assign { } { } + assign $1\src_l_r_src[3:0] 4'1111 + sync always + sync init + update \src_l_r_src $1\src_l_r_src[3:0] + end + attribute \src "libresoc.v:182182.13-182182.31" + process $proc$libresoc.v:182182$13691 + assign { } { } + assign $1\src_l_s_src[3:0] 4'0000 + sync always + sync init + update \src_l_s_src $1\src_l_s_src[3:0] + end + attribute \src "libresoc.v:182186.14-182186.43" + process $proc$libresoc.v:182186$13692 + assign { } { } + assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \src_r0 $1\src_r0[63:0] + end + attribute \src "libresoc.v:182190.14-182190.43" + process $proc$libresoc.v:182190$13693 + assign { } { } + assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \src_r1 $1\src_r1[63:0] + end + attribute \src "libresoc.v:182194.14-182194.43" + process $proc$libresoc.v:182194$13694 + assign { } { } + assign $1\src_r2[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \src_r2 $1\src_r2[63:0] + end + attribute \src "libresoc.v:182198.14-182198.43" + process $proc$libresoc.v:182198$13695 + assign { } { } + assign $1\src_r3[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \src_r3 $1\src_r3[63:0] + end + attribute \src "libresoc.v:182264.3-182265.39" + process $proc$libresoc.v:182264$13507 + assign { } { } + assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next + sync posedge \coresync_clk + update \alu_l_r_alu $0\alu_l_r_alu[0:0] + end + attribute \src "libresoc.v:182266.3-182267.43" + process $proc$libresoc.v:182266$13508 + assign { } { } + assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next + sync posedge \coresync_clk + update \alui_l_r_alui $0\alui_l_r_alui[0:0] + end + attribute \src "libresoc.v:182268.3-182269.29" + process $proc$libresoc.v:182268$13509 + assign { } { } + assign $0\src_r3[63:0] \src_r3$next + sync posedge \coresync_clk + update \src_r3 $0\src_r3[63:0] + end + attribute \src "libresoc.v:182270.3-182271.29" + process $proc$libresoc.v:182270$13510 + assign { } { } + assign $0\src_r2[63:0] \src_r2$next + sync posedge \coresync_clk + update \src_r2 $0\src_r2[63:0] + end + attribute \src "libresoc.v:182272.3-182273.29" + process $proc$libresoc.v:182272$13511 + assign { } { } + assign $0\src_r1[63:0] \src_r1$next + sync posedge \coresync_clk + update \src_r1 $0\src_r1[63:0] + end + attribute \src "libresoc.v:182274.3-182275.29" + process $proc$libresoc.v:182274$13512 + assign { } { } + assign $0\src_r0[63:0] \src_r0$next + sync posedge \coresync_clk + update \src_r0 $0\src_r0[63:0] + end + attribute \src "libresoc.v:182276.3-182277.41" + process $proc$libresoc.v:182276$13513 + assign { } { } + assign $0\data_r4__msr[63:0] \data_r4__msr$next + sync posedge \coresync_clk + update \data_r4__msr $0\data_r4__msr[63:0] + end + attribute \src "libresoc.v:182278.3-182279.47" + process $proc$libresoc.v:182278$13514 + assign { } { } + assign $0\data_r4__msr_ok[0:0] \data_r4__msr_ok$next + sync posedge \coresync_clk + update \data_r4__msr_ok $0\data_r4__msr_ok[0:0] + end + attribute \src "libresoc.v:182280.3-182281.41" + process $proc$libresoc.v:182280$13515 + assign { } { } + assign $0\data_r3__nia[63:0] \data_r3__nia$next + sync posedge \coresync_clk + update \data_r3__nia $0\data_r3__nia[63:0] + end + attribute \src "libresoc.v:182282.3-182283.47" + process $proc$libresoc.v:182282$13516 + assign { } { } + assign $0\data_r3__nia_ok[0:0] \data_r3__nia_ok$next + sync posedge \coresync_clk + update \data_r3__nia_ok $0\data_r3__nia_ok[0:0] + end + attribute \src "libresoc.v:182284.3-182285.45" + process $proc$libresoc.v:182284$13517 + assign { } { } + assign $0\data_r2__fast2[63:0] \data_r2__fast2$next + sync posedge \coresync_clk + update \data_r2__fast2 $0\data_r2__fast2[63:0] + end + attribute \src "libresoc.v:182286.3-182287.51" + process $proc$libresoc.v:182286$13518 + assign { } { } + assign $0\data_r2__fast2_ok[0:0] \data_r2__fast2_ok$next + sync posedge \coresync_clk + update \data_r2__fast2_ok $0\data_r2__fast2_ok[0:0] + end + attribute \src "libresoc.v:182288.3-182289.45" + process $proc$libresoc.v:182288$13519 + assign { } { } + assign $0\data_r1__fast1[63:0] \data_r1__fast1$next + sync posedge \coresync_clk + update \data_r1__fast1 $0\data_r1__fast1[63:0] + end + attribute \src "libresoc.v:182290.3-182291.51" + process $proc$libresoc.v:182290$13520 + assign { } { } + assign $0\data_r1__fast1_ok[0:0] \data_r1__fast1_ok$next + sync posedge \coresync_clk + update \data_r1__fast1_ok $0\data_r1__fast1_ok[0:0] + end + attribute \src "libresoc.v:182292.3-182293.37" + process $proc$libresoc.v:182292$13521 + assign { } { } + assign $0\data_r0__o[63:0] \data_r0__o$next + sync posedge \coresync_clk + update \data_r0__o $0\data_r0__o[63:0] + end + attribute \src "libresoc.v:182294.3-182295.43" + process $proc$libresoc.v:182294$13522 + assign { } { } + assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next + sync posedge \coresync_clk + update \data_r0__o_ok $0\data_r0__o_ok[0:0] + end + attribute \src "libresoc.v:182296.3-182297.73" + process $proc$libresoc.v:182296$13523 + assign { } { } + assign $0\alu_trap0_trap_op__insn_type[6:0] \alu_trap0_trap_op__insn_type$next + sync posedge \coresync_clk + update \alu_trap0_trap_op__insn_type $0\alu_trap0_trap_op__insn_type[6:0] + end + attribute \src "libresoc.v:182298.3-182299.69" + process $proc$libresoc.v:182298$13524 + assign { } { } + assign $0\alu_trap0_trap_op__fn_unit[11:0] \alu_trap0_trap_op__fn_unit$next + sync posedge \coresync_clk + update \alu_trap0_trap_op__fn_unit $0\alu_trap0_trap_op__fn_unit[11:0] + end + attribute \src "libresoc.v:182300.3-182301.63" + process $proc$libresoc.v:182300$13525 + assign { } { } + assign $0\alu_trap0_trap_op__insn[31:0] \alu_trap0_trap_op__insn$next + sync posedge \coresync_clk + update \alu_trap0_trap_op__insn $0\alu_trap0_trap_op__insn[31:0] + end + attribute \src "libresoc.v:182302.3-182303.61" + process $proc$libresoc.v:182302$13526 + assign { } { } + assign $0\alu_trap0_trap_op__msr[63:0] \alu_trap0_trap_op__msr$next + sync posedge \coresync_clk + update \alu_trap0_trap_op__msr $0\alu_trap0_trap_op__msr[63:0] + end + attribute \src "libresoc.v:182304.3-182305.61" + process $proc$libresoc.v:182304$13527 + assign { } { } + assign $0\alu_trap0_trap_op__cia[63:0] \alu_trap0_trap_op__cia$next + sync posedge \coresync_clk + update \alu_trap0_trap_op__cia $0\alu_trap0_trap_op__cia[63:0] + end + attribute \src "libresoc.v:182306.3-182307.71" + process $proc$libresoc.v:182306$13528 + assign { } { } + assign $0\alu_trap0_trap_op__is_32bit[0:0] \alu_trap0_trap_op__is_32bit$next + sync posedge \coresync_clk + update \alu_trap0_trap_op__is_32bit $0\alu_trap0_trap_op__is_32bit[0:0] + end + attribute \src "libresoc.v:182308.3-182309.71" + process $proc$libresoc.v:182308$13529 + assign { } { } + assign $0\alu_trap0_trap_op__traptype[6:0] \alu_trap0_trap_op__traptype$next + sync posedge \coresync_clk + update \alu_trap0_trap_op__traptype $0\alu_trap0_trap_op__traptype[6:0] + end + attribute \src "libresoc.v:182310.3-182311.71" + process $proc$libresoc.v:182310$13530 + assign { } { } + assign $0\alu_trap0_trap_op__trapaddr[12:0] \alu_trap0_trap_op__trapaddr$next + sync posedge \coresync_clk + update \alu_trap0_trap_op__trapaddr $0\alu_trap0_trap_op__trapaddr[12:0] + end + attribute \src "libresoc.v:182312.3-182313.39" + process $proc$libresoc.v:182312$13531 + assign { } { } + assign $0\req_l_r_req[4:0] \req_l_r_req$next + sync posedge \coresync_clk + update \req_l_r_req $0\req_l_r_req[4:0] + end + attribute \src "libresoc.v:182314.3-182315.39" + process $proc$libresoc.v:182314$13532 + assign { } { } + assign $0\req_l_s_req[4:0] \req_l_s_req$next + sync posedge \coresync_clk + update \req_l_s_req $0\req_l_s_req[4:0] + end + attribute \src "libresoc.v:182316.3-182317.39" + process $proc$libresoc.v:182316$13533 + assign { } { } + assign $0\src_l_r_src[3:0] \src_l_r_src$next + sync posedge \coresync_clk + update \src_l_r_src $0\src_l_r_src[3:0] + end + attribute \src "libresoc.v:182318.3-182319.39" + process $proc$libresoc.v:182318$13534 + assign { } { } + assign $0\src_l_s_src[3:0] \src_l_s_src$next + sync posedge \coresync_clk + update \src_l_s_src $0\src_l_s_src[3:0] + end + attribute \src "libresoc.v:182320.3-182321.39" + process $proc$libresoc.v:182320$13535 + assign { } { } + assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next + sync posedge \coresync_clk + update \opc_l_r_opc $0\opc_l_r_opc[0:0] + end + attribute \src "libresoc.v:182322.3-182323.39" + process $proc$libresoc.v:182322$13536 + assign { } { } + assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next + sync posedge \coresync_clk + update \opc_l_s_opc $0\opc_l_s_opc[0:0] + end + attribute \src "libresoc.v:182324.3-182325.39" + process $proc$libresoc.v:182324$13537 + assign { } { } + assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next + sync posedge \coresync_clk + update \rst_l_r_rst $0\rst_l_r_rst[0:0] + end + attribute \src "libresoc.v:182326.3-182327.39" + process $proc$libresoc.v:182326$13538 + assign { } { } + assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next + sync posedge \coresync_clk + update \rst_l_s_rst $0\rst_l_s_rst[0:0] + end + attribute \src "libresoc.v:182328.3-182329.41" + process $proc$libresoc.v:182328$13539 + assign { } { } + assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next + sync posedge \coresync_clk + update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] + end + attribute \src "libresoc.v:182330.3-182331.41" + process $proc$libresoc.v:182330$13540 + assign { } { } + assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next + sync posedge \coresync_clk + update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] + end + attribute \src "libresoc.v:182332.3-182333.37" + process $proc$libresoc.v:182332$13541 + assign { } { } + assign $0\prev_wr_go[4:0] \prev_wr_go$next + sync posedge \coresync_clk + update \prev_wr_go $0\prev_wr_go[4:0] + end + attribute \src "libresoc.v:182334.3-182335.41" + process $proc$libresoc.v:182334$13542 + assign { } { } + assign $0\alu_done_dly[0:0] \alu_trap0_n_valid_o + sync posedge \coresync_clk + update \alu_done_dly $0\alu_done_dly[0:0] + end + attribute \src "libresoc.v:182336.3-182337.25" + process $proc$libresoc.v:182336$13543 + assign { } { } + assign $0\all_rd_dly[0:0] \$11 + sync posedge \coresync_clk + update \all_rd_dly $0\all_rd_dly[0:0] + end + attribute \src "libresoc.v:182416.3-182425.6" + process $proc$libresoc.v:182416$13544 + assign { } { } + assign { } { } + assign $0\req_done[0:0] $1\req_done[0:0] + attribute \src "libresoc.v:182417.5-182417.29" + switch \initial + attribute \src "libresoc.v:182417.9-182417.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + switch \$55 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\req_done[0:0] 1'1 + case + assign $1\req_done[0:0] \$47 + end + sync always + update \req_done $0\req_done[0:0] + end + attribute \src "libresoc.v:182426.3-182434.6" + process $proc$libresoc.v:182426$13545 + assign { } { } + assign { } { } + assign $0\rok_l_s_rdok$next[0:0]$13546 $1\rok_l_s_rdok$next[0:0]$13547 + attribute \src "libresoc.v:182427.5-182427.29" + switch \initial + attribute \src "libresoc.v:182427.9-182427.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rok_l_s_rdok$next[0:0]$13547 1'0 + case + assign $1\rok_l_s_rdok$next[0:0]$13547 \cu_issue_i + end + sync always + update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$13546 + end + attribute \src "libresoc.v:182435.3-182443.6" + process $proc$libresoc.v:182435$13548 + assign { } { } + assign { } { } + assign $0\rok_l_r_rdok$next[0:0]$13549 $1\rok_l_r_rdok$next[0:0]$13550 + attribute \src "libresoc.v:182436.5-182436.29" + switch \initial + attribute \src "libresoc.v:182436.9-182436.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rok_l_r_rdok$next[0:0]$13550 1'1 + case + assign $1\rok_l_r_rdok$next[0:0]$13550 \$65 + end + sync always + update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$13549 + end + attribute \src "libresoc.v:182444.3-182452.6" + process $proc$libresoc.v:182444$13551 + assign { } { } + assign { } { } + assign $0\rst_l_s_rst$next[0:0]$13552 $1\rst_l_s_rst$next[0:0]$13553 + attribute \src "libresoc.v:182445.5-182445.29" + switch \initial + attribute \src "libresoc.v:182445.9-182445.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rst_l_s_rst$next[0:0]$13553 1'0 + case + assign $1\rst_l_s_rst$next[0:0]$13553 \all_rd + end + sync always + update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$13552 + end + attribute \src "libresoc.v:182453.3-182461.6" + process $proc$libresoc.v:182453$13554 + assign { } { } + assign { } { } + assign $0\rst_l_r_rst$next[0:0]$13555 $1\rst_l_r_rst$next[0:0]$13556 + attribute \src "libresoc.v:182454.5-182454.29" + switch \initial + attribute \src "libresoc.v:182454.9-182454.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rst_l_r_rst$next[0:0]$13556 1'1 + case + assign $1\rst_l_r_rst$next[0:0]$13556 \rst_r + end + sync always + update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$13555 + end + attribute \src "libresoc.v:182462.3-182470.6" + process $proc$libresoc.v:182462$13557 + assign { } { } + assign { } { } + assign $0\opc_l_s_opc$next[0:0]$13558 $1\opc_l_s_opc$next[0:0]$13559 + attribute \src "libresoc.v:182463.5-182463.29" + switch \initial + attribute \src "libresoc.v:182463.9-182463.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\opc_l_s_opc$next[0:0]$13559 1'0 + case + assign $1\opc_l_s_opc$next[0:0]$13559 \cu_issue_i + end + sync always + update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$13558 + end + attribute \src "libresoc.v:182471.3-182479.6" + process $proc$libresoc.v:182471$13560 + assign { } { } + assign { } { } + assign $0\opc_l_r_opc$next[0:0]$13561 $1\opc_l_r_opc$next[0:0]$13562 + attribute \src "libresoc.v:182472.5-182472.29" + switch \initial + attribute \src "libresoc.v:182472.9-182472.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\opc_l_r_opc$next[0:0]$13562 1'1 + case + assign $1\opc_l_r_opc$next[0:0]$13562 \req_done + end + sync always + update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$13561 + end + attribute \src "libresoc.v:182480.3-182488.6" + process $proc$libresoc.v:182480$13563 + assign { } { } + assign { } { } + assign $0\src_l_s_src$next[3:0]$13564 $1\src_l_s_src$next[3:0]$13565 + attribute \src "libresoc.v:182481.5-182481.29" + switch \initial + attribute \src "libresoc.v:182481.9-182481.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_l_s_src$next[3:0]$13565 4'0000 + case + assign $1\src_l_s_src$next[3:0]$13565 { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i } + end + sync always + update \src_l_s_src$next $0\src_l_s_src$next[3:0]$13564 + end + attribute \src "libresoc.v:182489.3-182497.6" + process $proc$libresoc.v:182489$13566 + assign { } { } + assign { } { } + assign $0\src_l_r_src$next[3:0]$13567 $1\src_l_r_src$next[3:0]$13568 + attribute \src "libresoc.v:182490.5-182490.29" + switch \initial + attribute \src "libresoc.v:182490.9-182490.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_l_r_src$next[3:0]$13568 4'1111 + case + assign $1\src_l_r_src$next[3:0]$13568 \reset_r + end + sync always + update \src_l_r_src$next $0\src_l_r_src$next[3:0]$13567 + end + attribute \src "libresoc.v:182498.3-182506.6" + process $proc$libresoc.v:182498$13569 + assign { } { } + assign { } { } + assign $0\req_l_s_req$next[4:0]$13570 $1\req_l_s_req$next[4:0]$13571 + attribute \src "libresoc.v:182499.5-182499.29" + switch \initial + attribute \src "libresoc.v:182499.9-182499.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\req_l_s_req$next[4:0]$13571 5'00000 + case + assign $1\req_l_s_req$next[4:0]$13571 \$67 + end + sync always + update \req_l_s_req$next $0\req_l_s_req$next[4:0]$13570 + end + attribute \src "libresoc.v:182507.3-182515.6" + process $proc$libresoc.v:182507$13572 + assign { } { } + assign { } { } + assign $0\req_l_r_req$next[4:0]$13573 $1\req_l_r_req$next[4:0]$13574 + attribute \src "libresoc.v:182508.5-182508.29" + switch \initial + attribute \src "libresoc.v:182508.9-182508.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\req_l_r_req$next[4:0]$13574 5'11111 + case + assign $1\req_l_r_req$next[4:0]$13574 \$69 + end + sync always + update \req_l_r_req$next $0\req_l_r_req$next[4:0]$13573 + end + attribute \src "libresoc.v:182516.3-182532.6" + process $proc$libresoc.v:182516$13575 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\alu_trap0_trap_op__cia$next[63:0]$13576 $1\alu_trap0_trap_op__cia$next[63:0]$13584 + assign $0\alu_trap0_trap_op__fn_unit$next[11:0]$13577 $1\alu_trap0_trap_op__fn_unit$next[11:0]$13585 + assign $0\alu_trap0_trap_op__insn$next[31:0]$13578 $1\alu_trap0_trap_op__insn$next[31:0]$13586 + assign $0\alu_trap0_trap_op__insn_type$next[6:0]$13579 $1\alu_trap0_trap_op__insn_type$next[6:0]$13587 + assign $0\alu_trap0_trap_op__is_32bit$next[0:0]$13580 $1\alu_trap0_trap_op__is_32bit$next[0:0]$13588 + assign $0\alu_trap0_trap_op__msr$next[63:0]$13581 $1\alu_trap0_trap_op__msr$next[63:0]$13589 + assign $0\alu_trap0_trap_op__trapaddr$next[12:0]$13582 $1\alu_trap0_trap_op__trapaddr$next[12:0]$13590 + assign $0\alu_trap0_trap_op__traptype$next[6:0]$13583 $1\alu_trap0_trap_op__traptype$next[6:0]$13591 + attribute \src "libresoc.v:182517.5-182517.29" + switch \initial + attribute \src "libresoc.v:182517.9-182517.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\alu_trap0_trap_op__trapaddr$next[12:0]$13590 $1\alu_trap0_trap_op__traptype$next[6:0]$13591 $1\alu_trap0_trap_op__is_32bit$next[0:0]$13588 $1\alu_trap0_trap_op__cia$next[63:0]$13584 $1\alu_trap0_trap_op__msr$next[63:0]$13589 $1\alu_trap0_trap_op__insn$next[31:0]$13586 $1\alu_trap0_trap_op__fn_unit$next[11:0]$13585 $1\alu_trap0_trap_op__insn_type$next[6:0]$13587 } { \oper_i_alu_trap0__trapaddr \oper_i_alu_trap0__traptype \oper_i_alu_trap0__is_32bit \oper_i_alu_trap0__cia \oper_i_alu_trap0__msr \oper_i_alu_trap0__insn \oper_i_alu_trap0__fn_unit \oper_i_alu_trap0__insn_type } + case + assign $1\alu_trap0_trap_op__cia$next[63:0]$13584 \alu_trap0_trap_op__cia + assign $1\alu_trap0_trap_op__fn_unit$next[11:0]$13585 \alu_trap0_trap_op__fn_unit + assign $1\alu_trap0_trap_op__insn$next[31:0]$13586 \alu_trap0_trap_op__insn + assign $1\alu_trap0_trap_op__insn_type$next[6:0]$13587 \alu_trap0_trap_op__insn_type + assign $1\alu_trap0_trap_op__is_32bit$next[0:0]$13588 \alu_trap0_trap_op__is_32bit + assign $1\alu_trap0_trap_op__msr$next[63:0]$13589 \alu_trap0_trap_op__msr + assign $1\alu_trap0_trap_op__trapaddr$next[12:0]$13590 \alu_trap0_trap_op__trapaddr + assign $1\alu_trap0_trap_op__traptype$next[6:0]$13591 \alu_trap0_trap_op__traptype + end + sync always + update \alu_trap0_trap_op__cia$next $0\alu_trap0_trap_op__cia$next[63:0]$13576 + update \alu_trap0_trap_op__fn_unit$next $0\alu_trap0_trap_op__fn_unit$next[11:0]$13577 + update \alu_trap0_trap_op__insn$next $0\alu_trap0_trap_op__insn$next[31:0]$13578 + update \alu_trap0_trap_op__insn_type$next $0\alu_trap0_trap_op__insn_type$next[6:0]$13579 + update \alu_trap0_trap_op__is_32bit$next $0\alu_trap0_trap_op__is_32bit$next[0:0]$13580 + update \alu_trap0_trap_op__msr$next $0\alu_trap0_trap_op__msr$next[63:0]$13581 + update \alu_trap0_trap_op__trapaddr$next $0\alu_trap0_trap_op__trapaddr$next[12:0]$13582 + update \alu_trap0_trap_op__traptype$next $0\alu_trap0_trap_op__traptype$next[6:0]$13583 + end + attribute \src "libresoc.v:182533.3-182554.6" + process $proc$libresoc.v:182533$13592 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r0__o$next[63:0]$13593 $2\data_r0__o$next[63:0]$13597 + assign { } { } + assign $0\data_r0__o_ok$next[0:0]$13594 $3\data_r0__o_ok$next[0:0]$13599 + attribute \src "libresoc.v:182534.5-182534.29" + switch \initial + attribute \src "libresoc.v:182534.9-182534.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r0__o_ok$next[0:0]$13596 $1\data_r0__o$next[63:0]$13595 } { \o_ok \alu_trap0_o } + case + assign $1\data_r0__o$next[63:0]$13595 \data_r0__o + assign $1\data_r0__o_ok$next[0:0]$13596 \data_r0__o_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r0__o_ok$next[0:0]$13598 $2\data_r0__o$next[63:0]$13597 } 65'00000000000000000000000000000000000000000000000000000000000000000 + case + assign $2\data_r0__o$next[63:0]$13597 $1\data_r0__o$next[63:0]$13595 + assign $2\data_r0__o_ok$next[0:0]$13598 $1\data_r0__o_ok$next[0:0]$13596 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r0__o_ok$next[0:0]$13599 1'0 + case + assign $3\data_r0__o_ok$next[0:0]$13599 $2\data_r0__o_ok$next[0:0]$13598 + end + sync always + update \data_r0__o$next $0\data_r0__o$next[63:0]$13593 + update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$13594 + end + attribute \src "libresoc.v:182555.3-182576.6" + process $proc$libresoc.v:182555$13600 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r1__fast1$next[63:0]$13601 $2\data_r1__fast1$next[63:0]$13605 + assign { } { } + assign $0\data_r1__fast1_ok$next[0:0]$13602 $3\data_r1__fast1_ok$next[0:0]$13607 + attribute \src "libresoc.v:182556.5-182556.29" + switch \initial + attribute \src "libresoc.v:182556.9-182556.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r1__fast1_ok$next[0:0]$13604 $1\data_r1__fast1$next[63:0]$13603 } { \fast1_ok \alu_trap0_fast1 } + case + assign $1\data_r1__fast1$next[63:0]$13603 \data_r1__fast1 + assign $1\data_r1__fast1_ok$next[0:0]$13604 \data_r1__fast1_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r1__fast1_ok$next[0:0]$13606 $2\data_r1__fast1$next[63:0]$13605 } 65'00000000000000000000000000000000000000000000000000000000000000000 + case + assign $2\data_r1__fast1$next[63:0]$13605 $1\data_r1__fast1$next[63:0]$13603 + assign $2\data_r1__fast1_ok$next[0:0]$13606 $1\data_r1__fast1_ok$next[0:0]$13604 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r1__fast1_ok$next[0:0]$13607 1'0 + case + assign $3\data_r1__fast1_ok$next[0:0]$13607 $2\data_r1__fast1_ok$next[0:0]$13606 + end + sync always + update \data_r1__fast1$next $0\data_r1__fast1$next[63:0]$13601 + update \data_r1__fast1_ok$next $0\data_r1__fast1_ok$next[0:0]$13602 + end + attribute \src "libresoc.v:182577.3-182598.6" + process $proc$libresoc.v:182577$13608 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r2__fast2$next[63:0]$13609 $2\data_r2__fast2$next[63:0]$13613 + assign { } { } + assign $0\data_r2__fast2_ok$next[0:0]$13610 $3\data_r2__fast2_ok$next[0:0]$13615 + attribute \src "libresoc.v:182578.5-182578.29" + switch \initial + attribute \src "libresoc.v:182578.9-182578.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r2__fast2_ok$next[0:0]$13612 $1\data_r2__fast2$next[63:0]$13611 } { \fast2_ok \alu_trap0_fast2 } + case + assign $1\data_r2__fast2$next[63:0]$13611 \data_r2__fast2 + assign $1\data_r2__fast2_ok$next[0:0]$13612 \data_r2__fast2_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r2__fast2_ok$next[0:0]$13614 $2\data_r2__fast2$next[63:0]$13613 } 65'00000000000000000000000000000000000000000000000000000000000000000 + case + assign $2\data_r2__fast2$next[63:0]$13613 $1\data_r2__fast2$next[63:0]$13611 + assign $2\data_r2__fast2_ok$next[0:0]$13614 $1\data_r2__fast2_ok$next[0:0]$13612 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r2__fast2_ok$next[0:0]$13615 1'0 + case + assign $3\data_r2__fast2_ok$next[0:0]$13615 $2\data_r2__fast2_ok$next[0:0]$13614 + end + sync always + update \data_r2__fast2$next $0\data_r2__fast2$next[63:0]$13609 + update \data_r2__fast2_ok$next $0\data_r2__fast2_ok$next[0:0]$13610 + end + attribute \src "libresoc.v:182599.3-182620.6" + process $proc$libresoc.v:182599$13616 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r3__nia$next[63:0]$13617 $2\data_r3__nia$next[63:0]$13621 + assign { } { } + assign $0\data_r3__nia_ok$next[0:0]$13618 $3\data_r3__nia_ok$next[0:0]$13623 + attribute \src "libresoc.v:182600.5-182600.29" + switch \initial + attribute \src "libresoc.v:182600.9-182600.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r3__nia_ok$next[0:0]$13620 $1\data_r3__nia$next[63:0]$13619 } { \nia_ok \alu_trap0_nia } + case + assign $1\data_r3__nia$next[63:0]$13619 \data_r3__nia + assign $1\data_r3__nia_ok$next[0:0]$13620 \data_r3__nia_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r3__nia_ok$next[0:0]$13622 $2\data_r3__nia$next[63:0]$13621 } 65'00000000000000000000000000000000000000000000000000000000000000000 + case + assign $2\data_r3__nia$next[63:0]$13621 $1\data_r3__nia$next[63:0]$13619 + assign $2\data_r3__nia_ok$next[0:0]$13622 $1\data_r3__nia_ok$next[0:0]$13620 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r3__nia_ok$next[0:0]$13623 1'0 + case + assign $3\data_r3__nia_ok$next[0:0]$13623 $2\data_r3__nia_ok$next[0:0]$13622 + end + sync always + update \data_r3__nia$next $0\data_r3__nia$next[63:0]$13617 + update \data_r3__nia_ok$next $0\data_r3__nia_ok$next[0:0]$13618 + end + attribute \src "libresoc.v:182621.3-182642.6" + process $proc$libresoc.v:182621$13624 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r4__msr$next[63:0]$13625 $2\data_r4__msr$next[63:0]$13629 + assign { } { } + assign $0\data_r4__msr_ok$next[0:0]$13626 $3\data_r4__msr_ok$next[0:0]$13631 + attribute \src "libresoc.v:182622.5-182622.29" + switch \initial + attribute \src "libresoc.v:182622.9-182622.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r4__msr_ok$next[0:0]$13628 $1\data_r4__msr$next[63:0]$13627 } { \msr_ok \alu_trap0_msr } + case + assign $1\data_r4__msr$next[63:0]$13627 \data_r4__msr + assign $1\data_r4__msr_ok$next[0:0]$13628 \data_r4__msr_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r4__msr_ok$next[0:0]$13630 $2\data_r4__msr$next[63:0]$13629 } 65'00000000000000000000000000000000000000000000000000000000000000000 + case + assign $2\data_r4__msr$next[63:0]$13629 $1\data_r4__msr$next[63:0]$13627 + assign $2\data_r4__msr_ok$next[0:0]$13630 $1\data_r4__msr_ok$next[0:0]$13628 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r4__msr_ok$next[0:0]$13631 1'0 + case + assign $3\data_r4__msr_ok$next[0:0]$13631 $2\data_r4__msr_ok$next[0:0]$13630 + end + sync always + update \data_r4__msr$next $0\data_r4__msr$next[63:0]$13625 + update \data_r4__msr_ok$next $0\data_r4__msr_ok$next[0:0]$13626 + end + attribute \src "libresoc.v:182643.3-182652.6" + process $proc$libresoc.v:182643$13632 + assign { } { } + assign { } { } + assign $0\src_r0$next[63:0]$13633 $1\src_r0$next[63:0]$13634 + attribute \src "libresoc.v:182644.5-182644.29" + switch \initial + attribute \src "libresoc.v:182644.9-182644.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch \src_l_q_src [0] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r0$next[63:0]$13634 \src1_i + case + assign $1\src_r0$next[63:0]$13634 \src_r0 + end + sync always + update \src_r0$next $0\src_r0$next[63:0]$13633 + end + attribute \src "libresoc.v:182653.3-182662.6" + process $proc$libresoc.v:182653$13635 + assign { } { } + assign { } { } + assign $0\src_r1$next[63:0]$13636 $1\src_r1$next[63:0]$13637 + attribute \src "libresoc.v:182654.5-182654.29" + switch \initial + attribute \src "libresoc.v:182654.9-182654.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch \src_l_q_src [1] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r1$next[63:0]$13637 \src2_i + case + assign $1\src_r1$next[63:0]$13637 \src_r1 + end + sync always + update \src_r1$next $0\src_r1$next[63:0]$13636 + end + attribute \src "libresoc.v:182663.3-182672.6" + process $proc$libresoc.v:182663$13638 + assign { } { } + assign { } { } + assign $0\src_r2$next[63:0]$13639 $1\src_r2$next[63:0]$13640 + attribute \src "libresoc.v:182664.5-182664.29" + switch \initial + attribute \src "libresoc.v:182664.9-182664.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch \src_l_q_src [2] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r2$next[63:0]$13640 \src3_i + case + assign $1\src_r2$next[63:0]$13640 \src_r2 + end + sync always + update \src_r2$next $0\src_r2$next[63:0]$13639 + end + attribute \src "libresoc.v:182673.3-182682.6" + process $proc$libresoc.v:182673$13641 + assign { } { } + assign { } { } + assign $0\src_r3$next[63:0]$13642 $1\src_r3$next[63:0]$13643 + attribute \src "libresoc.v:182674.5-182674.29" + switch \initial + attribute \src "libresoc.v:182674.9-182674.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch \src_l_q_src [3] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r3$next[63:0]$13643 \src4_i + case + assign $1\src_r3$next[63:0]$13643 \src_r3 + end + sync always + update \src_r3$next $0\src_r3$next[63:0]$13642 + end + attribute \src "libresoc.v:182683.3-182691.6" + process $proc$libresoc.v:182683$13644 + assign { } { } + assign { } { } + assign $0\alui_l_r_alui$next[0:0]$13645 $1\alui_l_r_alui$next[0:0]$13646 + attribute \src "libresoc.v:182684.5-182684.29" + switch \initial + attribute \src "libresoc.v:182684.9-182684.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\alui_l_r_alui$next[0:0]$13646 1'1 + case + assign $1\alui_l_r_alui$next[0:0]$13646 \$89 + end + sync always + update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$13645 + end + attribute \src "libresoc.v:182692.3-182700.6" + process $proc$libresoc.v:182692$13647 + assign { } { } + assign { } { } + assign $0\alu_l_r_alu$next[0:0]$13648 $1\alu_l_r_alu$next[0:0]$13649 + attribute \src "libresoc.v:182693.5-182693.29" + switch \initial + attribute \src "libresoc.v:182693.9-182693.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\alu_l_r_alu$next[0:0]$13649 1'1 + case + assign $1\alu_l_r_alu$next[0:0]$13649 \$91 + end + sync always + update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$13648 + end + attribute \src "libresoc.v:182701.3-182710.6" + process $proc$libresoc.v:182701$13650 + assign { } { } + assign { } { } + assign $0\dest1_o[63:0] $1\dest1_o[63:0] + attribute \src "libresoc.v:182702.5-182702.29" + switch \initial + attribute \src "libresoc.v:182702.9-182702.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$115 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest1_o[63:0] \data_r0__o + case + assign $1\dest1_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \dest1_o $0\dest1_o[63:0] + end + attribute \src "libresoc.v:182711.3-182720.6" + process $proc$libresoc.v:182711$13651 + assign { } { } + assign { } { } + assign $0\dest2_o[63:0] $1\dest2_o[63:0] + attribute \src "libresoc.v:182712.5-182712.29" + switch \initial + attribute \src "libresoc.v:182712.9-182712.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$117 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest2_o[63:0] \data_r1__fast1 + case + assign $1\dest2_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \dest2_o $0\dest2_o[63:0] + end + attribute \src "libresoc.v:182721.3-182730.6" + process $proc$libresoc.v:182721$13652 + assign { } { } + assign { } { } + assign $0\dest3_o[63:0] $1\dest3_o[63:0] + attribute \src "libresoc.v:182722.5-182722.29" + switch \initial + attribute \src "libresoc.v:182722.9-182722.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$119 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest3_o[63:0] \data_r2__fast2 + case + assign $1\dest3_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \dest3_o $0\dest3_o[63:0] + end + attribute \src "libresoc.v:182731.3-182740.6" + process $proc$libresoc.v:182731$13653 + assign { } { } + assign { } { } + assign $0\dest4_o[63:0] $1\dest4_o[63:0] + attribute \src "libresoc.v:182732.5-182732.29" + switch \initial + attribute \src "libresoc.v:182732.9-182732.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$121 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest4_o[63:0] \data_r3__nia + case + assign $1\dest4_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \dest4_o $0\dest4_o[63:0] + end + attribute \src "libresoc.v:182741.3-182750.6" + process $proc$libresoc.v:182741$13654 + assign { } { } + assign { } { } + assign $0\dest5_o[63:0] $1\dest5_o[63:0] + attribute \src "libresoc.v:182742.5-182742.29" + switch \initial + attribute \src "libresoc.v:182742.9-182742.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$123 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest5_o[63:0] \data_r4__msr + case + assign $1\dest5_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \dest5_o $0\dest5_o[63:0] + end + attribute \src "libresoc.v:182751.3-182759.6" + process $proc$libresoc.v:182751$13655 + assign { } { } + assign { } { } + assign $0\prev_wr_go$next[4:0]$13656 $1\prev_wr_go$next[4:0]$13657 + attribute \src "libresoc.v:182752.5-182752.29" + switch \initial + attribute \src "libresoc.v:182752.9-182752.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\prev_wr_go$next[4:0]$13657 5'00000 + case + assign $1\prev_wr_go$next[4:0]$13657 \$21 + end + sync always + update \prev_wr_go$next $0\prev_wr_go$next[4:0]$13656 + end + connect \$5 $reduce_and$libresoc.v:182203$13446_Y + connect \$99 $and$libresoc.v:182204$13447_Y + connect \$101 $and$libresoc.v:182205$13448_Y + connect \$103 $and$libresoc.v:182206$13449_Y + connect \$105 $and$libresoc.v:182207$13450_Y + connect \$107 $and$libresoc.v:182208$13451_Y + connect \$109 $and$libresoc.v:182209$13452_Y + connect \$111 $and$libresoc.v:182210$13453_Y + connect \$113 $and$libresoc.v:182211$13454_Y + connect \$115 $and$libresoc.v:182212$13455_Y + connect \$117 $and$libresoc.v:182213$13456_Y + connect \$11 $and$libresoc.v:182214$13457_Y + connect \$119 $and$libresoc.v:182215$13458_Y + connect \$121 $and$libresoc.v:182216$13459_Y + connect \$123 $and$libresoc.v:182217$13460_Y + connect \$13 $not$libresoc.v:182218$13461_Y + connect \$15 $and$libresoc.v:182219$13462_Y + connect \$17 $not$libresoc.v:182220$13463_Y + connect \$19 $and$libresoc.v:182221$13464_Y + connect \$21 $and$libresoc.v:182222$13465_Y + connect \$25 $not$libresoc.v:182223$13466_Y + connect \$27 $and$libresoc.v:182224$13467_Y + connect \$24 $reduce_or$libresoc.v:182225$13468_Y + connect \$23 $not$libresoc.v:182226$13469_Y + connect \$31 $and$libresoc.v:182227$13470_Y + connect \$33 $reduce_or$libresoc.v:182228$13471_Y + connect \$35 $reduce_or$libresoc.v:182229$13472_Y + connect \$37 $or$libresoc.v:182230$13473_Y + connect \$3 $and$libresoc.v:182231$13474_Y + connect \$39 $not$libresoc.v:182232$13475_Y + connect \$41 $and$libresoc.v:182233$13476_Y + connect \$43 $and$libresoc.v:182234$13477_Y + connect \$45 $eq$libresoc.v:182235$13478_Y + connect \$47 $and$libresoc.v:182236$13479_Y + connect \$49 $eq$libresoc.v:182237$13480_Y + connect \$51 $and$libresoc.v:182238$13481_Y + connect \$53 $and$libresoc.v:182239$13482_Y + connect \$55 $and$libresoc.v:182240$13483_Y + connect \$57 $or$libresoc.v:182241$13484_Y + connect \$59 $or$libresoc.v:182242$13485_Y + connect \$61 $or$libresoc.v:182243$13486_Y + connect \$63 $or$libresoc.v:182244$13487_Y + connect \$65 $and$libresoc.v:182245$13488_Y + connect \$67 $and$libresoc.v:182246$13489_Y + connect \$6 $not$libresoc.v:182247$13490_Y + connect \$69 $or$libresoc.v:182248$13491_Y + connect \$71 $and$libresoc.v:182249$13492_Y + connect \$73 $and$libresoc.v:182250$13493_Y + connect \$75 $and$libresoc.v:182251$13494_Y + connect \$77 $and$libresoc.v:182252$13495_Y + connect \$79 $and$libresoc.v:182253$13496_Y + connect \$81 $ternary$libresoc.v:182254$13497_Y + connect \$83 $ternary$libresoc.v:182255$13498_Y + connect \$85 $ternary$libresoc.v:182256$13499_Y + connect \$87 $ternary$libresoc.v:182257$13500_Y + connect \$8 $or$libresoc.v:182258$13501_Y + connect \$89 $and$libresoc.v:182259$13502_Y + connect \$91 $and$libresoc.v:182260$13503_Y + connect \$93 $and$libresoc.v:182261$13504_Y + connect \$95 $and$libresoc.v:182262$13505_Y + connect \$97 $not$libresoc.v:182263$13506_Y + connect \cu_go_die_i 1'0 + connect \cu_shadown_i 1'1 + connect \cu_wr__rel_o \$113 + connect \cu_rd__rel_o \$99 + connect \cu_busy_o \opc_l_q_opc + connect \alu_l_s_alu \all_rd_pulse + connect \alu_trap0_n_ready_i \alu_l_q_alu + connect \alui_l_s_alui \all_rd_pulse + connect \alu_trap0_p_valid_i \alui_l_q_alui + connect \alu_trap0_fast2$2 \$87 + connect \alu_trap0_fast1$1 \$85 + connect \alu_trap0_rb \$83 + connect \alu_trap0_ra \$81 + connect \cu_wrmask_o { \$79 \$77 \$75 \$73 \$71 } + connect \reset_r \$63 + connect \reset_w \$61 + connect \rst_r \$59 + connect \reset \$57 + connect \wr_any \$37 + connect \cu_done_o \$31 + connect \alu_pulsem { \alu_pulse \alu_pulse \alu_pulse \alu_pulse \alu_pulse } + connect \alu_pulse \alu_done_rise + connect \alu_done_rise \$19 + connect \alu_done_dly$next \alu_done + connect \alu_done \alu_trap0_n_valid_o + connect \all_rd_pulse \all_rd_rise + connect \all_rd_rise \$15 + connect \all_rd_dly$next \all_rd + connect \all_rd \$11 +end +attribute \src "libresoc.v:182793.1-182851.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.upd_l" +attribute \generator "nMigen" +module \upd_l + attribute \src "libresoc.v:182794.7-182794.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:182839.3-182847.6" + wire $0\q_int$next[0:0]$13706 + attribute \src "libresoc.v:182837.3-182838.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:182839.3-182847.6" + wire $1\q_int$next[0:0]$13707 + attribute \src "libresoc.v:182816.7-182816.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:182829.17-182829.96" + wire $and$libresoc.v:182829$13696_Y + attribute \src "libresoc.v:182834.17-182834.96" + wire $and$libresoc.v:182834$13701_Y + attribute \src "libresoc.v:182831.18-182831.93" + wire $not$libresoc.v:182831$13698_Y + attribute \src "libresoc.v:182833.17-182833.92" + wire $not$libresoc.v:182833$13700_Y + attribute \src "libresoc.v:182836.17-182836.92" + wire $not$libresoc.v:182836$13703_Y + attribute \src "libresoc.v:182830.18-182830.98" + wire $or$libresoc.v:182830$13697_Y + attribute \src "libresoc.v:182832.18-182832.99" + wire $or$libresoc.v:182832$13699_Y + attribute \src "libresoc.v:182835.17-182835.97" + wire $or$libresoc.v:182835$13702_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 1 \coresync_rst + attribute \src "libresoc.v:182794.7-182794.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 4 \q_upd + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_upd + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_upd + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_upd + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 2 \s_upd + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$libresoc.v:182829$13696 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:182829$13696_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:182834$13701 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:182834$13701_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:182831$13698 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_upd + connect \Y $not$libresoc.v:182831$13698_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:182833$13700 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_upd + connect \Y $not$libresoc.v:182833$13700_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:182836$13703 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_upd + connect \Y $not$libresoc.v:182836$13703_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:182830$13697 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_upd + connect \Y $or$libresoc.v:182830$13697_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:182832$13699 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_upd + connect \B \q_int + connect \Y $or$libresoc.v:182832$13699_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:182835$13702 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_upd + connect \Y $or$libresoc.v:182835$13702_Y + end + attribute \src "libresoc.v:182794.7-182794.20" + process $proc$libresoc.v:182794$13708 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:182816.7-182816.19" + process $proc$libresoc.v:182816$13709 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:182837.3-182838.27" + process $proc$libresoc.v:182837$13704 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:182839.3-182847.6" + process $proc$libresoc.v:182839$13705 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$13706 $1\q_int$next[0:0]$13707 + attribute \src "libresoc.v:182840.5-182840.29" + switch \initial + attribute \src "libresoc.v:182840.9-182840.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$13707 1'0 + case + assign $1\q_int$next[0:0]$13707 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$13706 + end + connect \$9 $and$libresoc.v:182829$13696_Y + connect \$11 $or$libresoc.v:182830$13697_Y + connect \$13 $not$libresoc.v:182831$13698_Y + connect \$15 $or$libresoc.v:182832$13699_Y + connect \$1 $not$libresoc.v:182833$13700_Y + connect \$3 $and$libresoc.v:182834$13701_Y + connect \$5 $or$libresoc.v:182835$13702_Y + connect \$7 $not$libresoc.v:182836$13703_Y + connect \qlq_upd \$15 + connect \qn_upd \$13 + connect \q_upd \$11 +end +attribute \src "libresoc.v:182855.1-182913.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.l0.pimem.valid_l" +attribute \generator "nMigen" +module \valid_l + attribute \src "libresoc.v:182856.7-182856.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:182901.3-182909.6" + wire $0\q_int$next[0:0]$13720 + attribute \src "libresoc.v:182899.3-182900.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:182901.3-182909.6" + wire $1\q_int$next[0:0]$13721 + attribute \src "libresoc.v:182878.7-182878.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:182891.17-182891.96" + wire $and$libresoc.v:182891$13710_Y + attribute \src "libresoc.v:182896.17-182896.96" + wire $and$libresoc.v:182896$13715_Y + attribute \src "libresoc.v:182893.18-182893.95" + wire $not$libresoc.v:182893$13712_Y + attribute \src "libresoc.v:182895.17-182895.94" + wire $not$libresoc.v:182895$13714_Y + attribute \src "libresoc.v:182898.17-182898.94" + wire $not$libresoc.v:182898$13717_Y + attribute \src "libresoc.v:182892.18-182892.100" + wire $or$libresoc.v:182892$13711_Y + attribute \src "libresoc.v:182894.18-182894.101" + wire $or$libresoc.v:182894$13713_Y + attribute \src "libresoc.v:182897.17-182897.99" + wire $or$libresoc.v:182897$13716_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 1 \coresync_rst + attribute \src "libresoc.v:182856.7-182856.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 3 \q_valid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_valid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_valid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 4 \r_valid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 2 \s_valid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$libresoc.v:182891$13710 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:182891$13710_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:182896$13715 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:182896$13715_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:182893$13712 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_valid + connect \Y $not$libresoc.v:182893$13712_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:182895$13714 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_valid + connect \Y $not$libresoc.v:182895$13714_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:182898$13717 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_valid + connect \Y $not$libresoc.v:182898$13717_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:182892$13711 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_valid + connect \Y $or$libresoc.v:182892$13711_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:182894$13713 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_valid + connect \B \q_int + connect \Y $or$libresoc.v:182894$13713_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:182897$13716 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_valid + connect \Y $or$libresoc.v:182897$13716_Y + end + attribute \src "libresoc.v:182856.7-182856.20" + process $proc$libresoc.v:182856$13722 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:182878.7-182878.19" + process $proc$libresoc.v:182878$13723 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:182899.3-182900.27" + process $proc$libresoc.v:182899$13718 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:182901.3-182909.6" + process $proc$libresoc.v:182901$13719 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$13720 $1\q_int$next[0:0]$13721 + attribute \src "libresoc.v:182902.5-182902.29" + switch \initial + attribute \src "libresoc.v:182902.9-182902.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$13721 1'0 + case + assign $1\q_int$next[0:0]$13721 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$13720 + end + connect \$9 $and$libresoc.v:182891$13710_Y + connect \$11 $or$libresoc.v:182892$13711_Y + connect \$13 $not$libresoc.v:182893$13712_Y + connect \$15 $or$libresoc.v:182894$13713_Y + connect \$1 $not$libresoc.v:182895$13714_Y + connect \$3 $and$libresoc.v:182896$13715_Y + connect \$5 $or$libresoc.v:182897$13716_Y + connect \$7 $not$libresoc.v:182898$13717_Y + connect \qlq_valid \$15 + connect \qn_valid \$13 + connect \q_valid \$11 +end +attribute \src "libresoc.v:182917.1-182975.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.wri_l" +attribute \generator "nMigen" +module \wri_l + attribute \src "libresoc.v:182918.7-182918.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:182963.3-182971.6" + wire $0\q_int$next[0:0]$13734 + attribute \src "libresoc.v:182961.3-182962.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:182963.3-182971.6" + wire $1\q_int$next[0:0]$13735 + attribute \src "libresoc.v:182940.7-182940.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:182953.17-182953.96" + wire $and$libresoc.v:182953$13724_Y + attribute \src "libresoc.v:182958.17-182958.96" + wire $and$libresoc.v:182958$13729_Y + attribute \src "libresoc.v:182955.18-182955.93" + wire $not$libresoc.v:182955$13726_Y + attribute \src "libresoc.v:182957.17-182957.92" + wire $not$libresoc.v:182957$13728_Y + attribute \src "libresoc.v:182960.17-182960.92" + wire $not$libresoc.v:182960$13731_Y + attribute \src "libresoc.v:182954.18-182954.98" + wire $or$libresoc.v:182954$13725_Y + attribute \src "libresoc.v:182956.18-182956.99" + wire $or$libresoc.v:182956$13727_Y + attribute \src "libresoc.v:182959.17-182959.97" + wire $or$libresoc.v:182959$13730_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 1 \coresync_rst + attribute \src "libresoc.v:182918.7-182918.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 4 \q_wri + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_wri + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_wri + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_wri + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 2 \s_wri + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$libresoc.v:182953$13724 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:182953$13724_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:182958$13729 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:182958$13729_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:182955$13726 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_wri + connect \Y $not$libresoc.v:182955$13726_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:182957$13728 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_wri + connect \Y $not$libresoc.v:182957$13728_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:182960$13731 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_wri + connect \Y $not$libresoc.v:182960$13731_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:182954$13725 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_wri + connect \Y $or$libresoc.v:182954$13725_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:182956$13727 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_wri + connect \B \q_int + connect \Y $or$libresoc.v:182956$13727_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:182959$13730 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_wri + connect \Y $or$libresoc.v:182959$13730_Y + end + attribute \src "libresoc.v:182918.7-182918.20" + process $proc$libresoc.v:182918$13736 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:182940.7-182940.19" + process $proc$libresoc.v:182940$13737 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:182961.3-182962.27" + process $proc$libresoc.v:182961$13732 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:182963.3-182971.6" + process $proc$libresoc.v:182963$13733 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$13734 $1\q_int$next[0:0]$13735 + attribute \src "libresoc.v:182964.5-182964.29" + switch \initial + attribute \src "libresoc.v:182964.9-182964.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$13735 1'0 + case + assign $1\q_int$next[0:0]$13735 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$13734 + end + connect \$9 $and$libresoc.v:182953$13724_Y + connect \$11 $or$libresoc.v:182954$13725_Y + connect \$13 $not$libresoc.v:182955$13726_Y + connect \$15 $or$libresoc.v:182956$13727_Y + connect \$1 $not$libresoc.v:182957$13728_Y + connect \$3 $and$libresoc.v:182958$13729_Y + connect \$5 $or$libresoc.v:182959$13730_Y + connect \$7 $not$libresoc.v:182960$13731_Y + connect \qlq_wri \$15 + connect \qn_wri \$13 + connect \q_wri \$11 +end +attribute \src "libresoc.v:182979.1-183045.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.wrpick_CR_cr_a" +attribute \generator "nMigen" +module \wrpick_CR_cr_a + attribute \src "libresoc.v:183024.17-183024.91" + wire $not$libresoc.v:183024$13738_Y + attribute \src "libresoc.v:183026.18-183026.93" + wire $not$libresoc.v:183026$13740_Y + attribute \src "libresoc.v:183028.18-183028.93" + wire $not$libresoc.v:183028$13742_Y + attribute \src "libresoc.v:183029.17-183029.89" + wire width 6 $not$libresoc.v:183029$13743_Y + attribute \src "libresoc.v:183031.18-183031.93" + wire $not$libresoc.v:183031$13745_Y + attribute \src "libresoc.v:183034.17-183034.91" + wire $not$libresoc.v:183034$13748_Y + attribute \src "libresoc.v:183025.18-183025.106" + wire $reduce_or$libresoc.v:183025$13739_Y + attribute \src "libresoc.v:183027.18-183027.106" + wire $reduce_or$libresoc.v:183027$13741_Y + attribute \src "libresoc.v:183030.18-183030.106" + wire $reduce_or$libresoc.v:183030$13744_Y + attribute \src "libresoc.v:183032.18-183032.90" + wire $reduce_or$libresoc.v:183032$13746_Y + attribute \src "libresoc.v:183033.17-183033.103" + wire $reduce_or$libresoc.v:183033$13747_Y + attribute \src "libresoc.v:183035.17-183035.105" + wire $reduce_or$libresoc.v:183035$13749_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire width 6 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 6 input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire width 6 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 6 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:183024$13738 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $not$libresoc.v:183024$13738_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:183026$13740 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$12 + connect \Y $not$libresoc.v:183026$13740_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:183028$13742 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \Y $not$libresoc.v:183028$13742_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $not$libresoc.v:183029$13743 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \i + connect \Y $not$libresoc.v:183029$13743_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:183031$13745 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$20 + connect \Y $not$libresoc.v:183031$13745_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:183034$13748 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$libresoc.v:183034$13748_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:183025$13739 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [2:0] \ni [3] } + connect \Y $reduce_or$libresoc.v:183025$13739_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:183027$13741 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [3:0] \ni [4] } + connect \Y $reduce_or$libresoc.v:183027$13741_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:183030$13744 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [4:0] \ni [5] } + connect \Y $reduce_or$libresoc.v:183030$13744_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_or $reduce_or$libresoc.v:183032$13746 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:183032$13746_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:183033$13747 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [0] \ni [1] } + connect \Y $reduce_or$libresoc.v:183033$13747_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:183035$13749 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [1:0] \ni [2] } + connect \Y $reduce_or$libresoc.v:183035$13749_Y + end + connect \$7 $not$libresoc.v:183024$13738_Y + connect \$12 $reduce_or$libresoc.v:183025$13739_Y + connect \$11 $not$libresoc.v:183026$13740_Y + connect \$16 $reduce_or$libresoc.v:183027$13741_Y + connect \$15 $not$libresoc.v:183028$13742_Y + connect \$1 $not$libresoc.v:183029$13743_Y + connect \$20 $reduce_or$libresoc.v:183030$13744_Y + connect \$19 $not$libresoc.v:183031$13745_Y + connect \$23 $reduce_or$libresoc.v:183032$13746_Y + connect \$4 $reduce_or$libresoc.v:183033$13747_Y + connect \$3 $not$libresoc.v:183034$13748_Y + connect \$8 $reduce_or$libresoc.v:183035$13749_Y + connect \en_o \$23 + connect \o { \t5 \t4 \t3 \t2 \t1 \t0 } + connect \t5 \$19 + connect \t4 \$15 + connect \t3 \$11 + connect \t2 \$7 + connect \t1 \$3 + connect \t0 \i [0] + connect \ni \$1 +end +attribute \src "libresoc.v:183049.1-183070.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.wrpick_CR_full_cr" +attribute \generator "nMigen" +module \wrpick_CR_full_cr + attribute \src "libresoc.v:183064.17-183064.89" + wire $not$libresoc.v:183064$13750_Y + attribute \src "libresoc.v:183065.17-183065.89" + wire $reduce_or$libresoc.v:183065$13751_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $not$libresoc.v:183064$13750 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \i + connect \Y $not$libresoc.v:183064$13750_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_or $reduce_or$libresoc.v:183065$13751 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:183065$13751_Y + end + connect \$1 $not$libresoc.v:183064$13750_Y + connect \$3 $reduce_or$libresoc.v:183065$13751_Y + connect \en_o \$3 + connect \o \t0 + connect \t0 \i + connect \ni \$1 +end +attribute \src "libresoc.v:183074.1-183131.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.wrpick_FAST_fast1" +attribute \generator "nMigen" +module \wrpick_FAST_fast1 + attribute \src "libresoc.v:183113.17-183113.91" + wire $not$libresoc.v:183113$13752_Y + attribute \src "libresoc.v:183115.18-183115.93" + wire $not$libresoc.v:183115$13754_Y + attribute \src "libresoc.v:183117.18-183117.93" + wire $not$libresoc.v:183117$13756_Y + attribute \src "libresoc.v:183118.17-183118.89" + wire width 5 $not$libresoc.v:183118$13757_Y + attribute \src "libresoc.v:183121.17-183121.91" + wire $not$libresoc.v:183121$13760_Y + attribute \src "libresoc.v:183114.18-183114.106" + wire $reduce_or$libresoc.v:183114$13753_Y + attribute \src "libresoc.v:183116.18-183116.106" + wire $reduce_or$libresoc.v:183116$13755_Y + attribute \src "libresoc.v:183119.18-183119.90" + wire $reduce_or$libresoc.v:183119$13758_Y + attribute \src "libresoc.v:183120.17-183120.103" + wire $reduce_or$libresoc.v:183120$13759_Y + attribute \src "libresoc.v:183122.17-183122.105" + wire $reduce_or$libresoc.v:183122$13761_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire width 5 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 5 input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire width 5 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 5 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:183113$13752 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $not$libresoc.v:183113$13752_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:183115$13754 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$12 + connect \Y $not$libresoc.v:183115$13754_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:183117$13756 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \Y $not$libresoc.v:183117$13756_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $not$libresoc.v:183118$13757 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \i + connect \Y $not$libresoc.v:183118$13757_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:183121$13760 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$libresoc.v:183121$13760_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:183114$13753 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [2:0] \ni [3] } + connect \Y $reduce_or$libresoc.v:183114$13753_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:183116$13755 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [3:0] \ni [4] } + connect \Y $reduce_or$libresoc.v:183116$13755_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_or $reduce_or$libresoc.v:183119$13758 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:183119$13758_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:183120$13759 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [0] \ni [1] } + connect \Y $reduce_or$libresoc.v:183120$13759_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:183122$13761 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [1:0] \ni [2] } + connect \Y $reduce_or$libresoc.v:183122$13761_Y + end + connect \$7 $not$libresoc.v:183113$13752_Y + connect \$12 $reduce_or$libresoc.v:183114$13753_Y + connect \$11 $not$libresoc.v:183115$13754_Y + connect \$16 $reduce_or$libresoc.v:183116$13755_Y + connect \$15 $not$libresoc.v:183117$13756_Y + connect \$1 $not$libresoc.v:183118$13757_Y + connect \$19 $reduce_or$libresoc.v:183119$13758_Y + connect \$4 $reduce_or$libresoc.v:183120$13759_Y + connect \$3 $not$libresoc.v:183121$13760_Y + connect \$8 $reduce_or$libresoc.v:183122$13761_Y + connect \en_o \$19 + connect \o { \t4 \t3 \t2 \t1 \t0 } + connect \t4 \$15 + connect \t3 \$11 + connect \t2 \$7 + connect \t1 \$3 + connect \t0 \i [0] + connect \ni \$1 +end +attribute \src "libresoc.v:183135.1-183237.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.wrpick_INT_o" +attribute \generator "nMigen" +module \wrpick_INT_o + attribute \src "libresoc.v:183204.17-183204.91" + wire $not$libresoc.v:183204$13762_Y + attribute \src "libresoc.v:183206.18-183206.93" + wire $not$libresoc.v:183206$13764_Y + attribute \src "libresoc.v:183208.18-183208.93" + wire $not$libresoc.v:183208$13766_Y + attribute \src "libresoc.v:183209.17-183209.89" + wire width 10 $not$libresoc.v:183209$13767_Y + attribute \src "libresoc.v:183211.18-183211.93" + wire $not$libresoc.v:183211$13769_Y + attribute \src "libresoc.v:183213.18-183213.93" + wire $not$libresoc.v:183213$13771_Y + attribute \src "libresoc.v:183215.18-183215.93" + wire $not$libresoc.v:183215$13773_Y + attribute \src "libresoc.v:183217.18-183217.93" + wire $not$libresoc.v:183217$13775_Y + attribute \src "libresoc.v:183219.18-183219.93" + wire $not$libresoc.v:183219$13777_Y + attribute \src "libresoc.v:183222.17-183222.91" + wire $not$libresoc.v:183222$13780_Y + attribute \src "libresoc.v:183205.18-183205.106" + wire $reduce_or$libresoc.v:183205$13763_Y + attribute \src "libresoc.v:183207.18-183207.106" + wire $reduce_or$libresoc.v:183207$13765_Y + attribute \src "libresoc.v:183210.18-183210.106" + wire $reduce_or$libresoc.v:183210$13768_Y + attribute \src "libresoc.v:183212.18-183212.106" + wire $reduce_or$libresoc.v:183212$13770_Y + attribute \src "libresoc.v:183214.18-183214.106" + wire $reduce_or$libresoc.v:183214$13772_Y + attribute \src "libresoc.v:183216.18-183216.106" + wire $reduce_or$libresoc.v:183216$13774_Y + attribute \src "libresoc.v:183218.18-183218.106" + wire $reduce_or$libresoc.v:183218$13776_Y + attribute \src "libresoc.v:183220.18-183220.90" + wire $reduce_or$libresoc.v:183220$13778_Y + attribute \src "libresoc.v:183221.17-183221.103" + wire $reduce_or$libresoc.v:183221$13779_Y + attribute \src "libresoc.v:183223.17-183223.105" + wire $reduce_or$libresoc.v:183223$13781_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire width 10 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$32 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$35 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$36 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire \$39 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 10 input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire width 10 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 10 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t9 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:183204$13762 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $not$libresoc.v:183204$13762_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:183206$13764 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$12 + connect \Y $not$libresoc.v:183206$13764_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:183208$13766 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \Y $not$libresoc.v:183208$13766_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $not$libresoc.v:183209$13767 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \Y_WIDTH 10 + connect \A \i + connect \Y $not$libresoc.v:183209$13767_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:183211$13769 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$20 + connect \Y $not$libresoc.v:183211$13769_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:183213$13771 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$24 + connect \Y $not$libresoc.v:183213$13771_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:183215$13773 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$28 + connect \Y $not$libresoc.v:183215$13773_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:183217$13775 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$32 + connect \Y $not$libresoc.v:183217$13775_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:183219$13777 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$36 + connect \Y $not$libresoc.v:183219$13777_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:183222$13780 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$libresoc.v:183222$13780_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:183205$13763 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [2:0] \ni [3] } + connect \Y $reduce_or$libresoc.v:183205$13763_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:183207$13765 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [3:0] \ni [4] } + connect \Y $reduce_or$libresoc.v:183207$13765_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:183210$13768 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [4:0] \ni [5] } + connect \Y $reduce_or$libresoc.v:183210$13768_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:183212$13770 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A { \i [5:0] \ni [6] } + connect \Y $reduce_or$libresoc.v:183212$13770_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:183214$13772 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A { \i [6:0] \ni [7] } + connect \Y $reduce_or$libresoc.v:183214$13772_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:183216$13774 + parameter \A_SIGNED 0 + parameter \A_WIDTH 9 + parameter \Y_WIDTH 1 + connect \A { \i [7:0] \ni [8] } + connect \Y $reduce_or$libresoc.v:183216$13774_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:183218$13776 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \Y_WIDTH 1 + connect \A { \i [8:0] \ni [9] } + connect \Y $reduce_or$libresoc.v:183218$13776_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_or $reduce_or$libresoc.v:183220$13778 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:183220$13778_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:183221$13779 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [0] \ni [1] } + connect \Y $reduce_or$libresoc.v:183221$13779_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:183223$13781 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [1:0] \ni [2] } + connect \Y $reduce_or$libresoc.v:183223$13781_Y + end + connect \$7 $not$libresoc.v:183204$13762_Y + connect \$12 $reduce_or$libresoc.v:183205$13763_Y + connect \$11 $not$libresoc.v:183206$13764_Y + connect \$16 $reduce_or$libresoc.v:183207$13765_Y + connect \$15 $not$libresoc.v:183208$13766_Y + connect \$1 $not$libresoc.v:183209$13767_Y + connect \$20 $reduce_or$libresoc.v:183210$13768_Y + connect \$19 $not$libresoc.v:183211$13769_Y + connect \$24 $reduce_or$libresoc.v:183212$13770_Y + connect \$23 $not$libresoc.v:183213$13771_Y + connect \$28 $reduce_or$libresoc.v:183214$13772_Y + connect \$27 $not$libresoc.v:183215$13773_Y + connect \$32 $reduce_or$libresoc.v:183216$13774_Y + connect \$31 $not$libresoc.v:183217$13775_Y + connect \$36 $reduce_or$libresoc.v:183218$13776_Y + connect \$35 $not$libresoc.v:183219$13777_Y + connect \$39 $reduce_or$libresoc.v:183220$13778_Y + connect \$4 $reduce_or$libresoc.v:183221$13779_Y + connect \$3 $not$libresoc.v:183222$13780_Y + connect \$8 $reduce_or$libresoc.v:183223$13781_Y + connect \en_o \$39 + connect \o { \t9 \t8 \t7 \t6 \t5 \t4 \t3 \t2 \t1 \t0 } + connect \t9 \$35 + connect \t8 \$31 + connect \t7 \$27 + connect \t6 \$23 + connect \t5 \$19 + connect \t4 \$15 + connect \t3 \$11 + connect \t2 \$7 + connect \t1 \$3 + connect \t0 \i [0] + connect \ni \$1 +end +attribute \src "libresoc.v:183241.1-183262.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.wrpick_SPR_spr1" +attribute \generator "nMigen" +module \wrpick_SPR_spr1 + attribute \src "libresoc.v:183256.17-183256.89" + wire $not$libresoc.v:183256$13782_Y + attribute \src "libresoc.v:183257.17-183257.89" + wire $reduce_or$libresoc.v:183257$13783_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $not$libresoc.v:183256$13782 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \i + connect \Y $not$libresoc.v:183256$13782_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_or $reduce_or$libresoc.v:183257$13783 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:183257$13783_Y + end + connect \$1 $not$libresoc.v:183256$13782_Y + connect \$3 $reduce_or$libresoc.v:183257$13783_Y + connect \en_o \$3 + connect \o \t0 + connect \t0 \i + connect \ni \$1 +end +attribute \src "libresoc.v:183266.1-183287.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.wrpick_STATE_msr" +attribute \generator "nMigen" +module \wrpick_STATE_msr + attribute \src "libresoc.v:183281.17-183281.89" + wire $not$libresoc.v:183281$13784_Y + attribute \src "libresoc.v:183282.17-183282.89" + wire $reduce_or$libresoc.v:183282$13785_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $not$libresoc.v:183281$13784 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \i + connect \Y $not$libresoc.v:183281$13784_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_or $reduce_or$libresoc.v:183282$13785 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:183282$13785_Y + end + connect \$1 $not$libresoc.v:183281$13784_Y + connect \$3 $reduce_or$libresoc.v:183282$13785_Y + connect \en_o \$3 + connect \o \t0 + connect \t0 \i + connect \ni \$1 +end +attribute \src "libresoc.v:183291.1-183321.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.wrpick_STATE_nia" +attribute \generator "nMigen" +module \wrpick_STATE_nia + attribute \src "libresoc.v:183312.17-183312.89" + wire width 2 $not$libresoc.v:183312$13786_Y + attribute \src "libresoc.v:183314.17-183314.91" + wire $not$libresoc.v:183314$13788_Y + attribute \src "libresoc.v:183313.17-183313.103" + wire $reduce_or$libresoc.v:183313$13787_Y + attribute \src "libresoc.v:183315.17-183315.89" + wire $reduce_or$libresoc.v:183315$13789_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire width 2 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 2 input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire width 2 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 2 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $not$libresoc.v:183312$13786 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \i + connect \Y $not$libresoc.v:183312$13786_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:183314$13788 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$libresoc.v:183314$13788_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:183313$13787 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [0] \ni [1] } + connect \Y $reduce_or$libresoc.v:183313$13787_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_or $reduce_or$libresoc.v:183315$13789 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:183315$13789_Y + end + connect \$1 $not$libresoc.v:183312$13786_Y + connect \$4 $reduce_or$libresoc.v:183313$13787_Y + connect \$3 $not$libresoc.v:183314$13788_Y + connect \$7 $reduce_or$libresoc.v:183315$13789_Y + connect \en_o \$7 + connect \o { \t1 \t0 } + connect \t1 \$3 + connect \t0 \i [0] + connect \ni \$1 +end +attribute \src "libresoc.v:183325.1-183364.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.wrpick_XER_xer_ca" +attribute \generator "nMigen" +module \wrpick_XER_xer_ca + attribute \src "libresoc.v:183352.17-183352.91" + wire $not$libresoc.v:183352$13790_Y + attribute \src "libresoc.v:183354.17-183354.89" + wire width 3 $not$libresoc.v:183354$13792_Y + attribute \src "libresoc.v:183356.17-183356.91" + wire $not$libresoc.v:183356$13794_Y + attribute \src "libresoc.v:183353.18-183353.90" + wire $reduce_or$libresoc.v:183353$13791_Y + attribute \src "libresoc.v:183355.17-183355.103" + wire $reduce_or$libresoc.v:183355$13793_Y + attribute \src "libresoc.v:183357.17-183357.105" + wire $reduce_or$libresoc.v:183357$13795_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire width 3 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 3 input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire width 3 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 3 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:183352$13790 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $not$libresoc.v:183352$13790_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $not$libresoc.v:183354$13792 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \i + connect \Y $not$libresoc.v:183354$13792_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:183356$13794 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$libresoc.v:183356$13794_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_or $reduce_or$libresoc.v:183353$13791 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:183353$13791_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:183355$13793 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [0] \ni [1] } + connect \Y $reduce_or$libresoc.v:183355$13793_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:183357$13795 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [1:0] \ni [2] } + connect \Y $reduce_or$libresoc.v:183357$13795_Y + end + connect \$7 $not$libresoc.v:183352$13790_Y + connect \$11 $reduce_or$libresoc.v:183353$13791_Y + connect \$1 $not$libresoc.v:183354$13792_Y + connect \$4 $reduce_or$libresoc.v:183355$13793_Y + connect \$3 $not$libresoc.v:183356$13794_Y + connect \$8 $reduce_or$libresoc.v:183357$13795_Y + connect \en_o \$11 + connect \o { \t2 \t1 \t0 } + connect \t2 \$7 + connect \t1 \$3 + connect \t0 \i [0] + connect \ni \$1 +end +attribute \src "libresoc.v:183368.1-183416.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.wrpick_XER_xer_ov" +attribute \generator "nMigen" +module \wrpick_XER_xer_ov + attribute \src "libresoc.v:183401.17-183401.91" + wire $not$libresoc.v:183401$13796_Y + attribute \src "libresoc.v:183403.18-183403.93" + wire $not$libresoc.v:183403$13798_Y + attribute \src "libresoc.v:183405.17-183405.89" + wire width 4 $not$libresoc.v:183405$13800_Y + attribute \src "libresoc.v:183407.17-183407.91" + wire $not$libresoc.v:183407$13802_Y + attribute \src "libresoc.v:183402.18-183402.106" + wire $reduce_or$libresoc.v:183402$13797_Y + attribute \src "libresoc.v:183404.18-183404.90" + wire $reduce_or$libresoc.v:183404$13799_Y + attribute \src "libresoc.v:183406.17-183406.103" + wire $reduce_or$libresoc.v:183406$13801_Y + attribute \src "libresoc.v:183408.17-183408.105" + wire $reduce_or$libresoc.v:183408$13803_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire width 4 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 4 input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire width 4 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 4 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:183401$13796 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $not$libresoc.v:183401$13796_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:183403$13798 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$12 + connect \Y $not$libresoc.v:183403$13798_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $not$libresoc.v:183405$13800 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \i + connect \Y $not$libresoc.v:183405$13800_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:183407$13802 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$libresoc.v:183407$13802_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:183402$13797 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [2:0] \ni [3] } + connect \Y $reduce_or$libresoc.v:183402$13797_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_or $reduce_or$libresoc.v:183404$13799 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:183404$13799_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:183406$13801 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [0] \ni [1] } + connect \Y $reduce_or$libresoc.v:183406$13801_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:183408$13803 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [1:0] \ni [2] } + connect \Y $reduce_or$libresoc.v:183408$13803_Y + end + connect \$7 $not$libresoc.v:183401$13796_Y + connect \$12 $reduce_or$libresoc.v:183402$13797_Y + connect \$11 $not$libresoc.v:183403$13798_Y + connect \$15 $reduce_or$libresoc.v:183404$13799_Y + connect \$1 $not$libresoc.v:183405$13800_Y + connect \$4 $reduce_or$libresoc.v:183406$13801_Y + connect \$3 $not$libresoc.v:183407$13802_Y + connect \$8 $reduce_or$libresoc.v:183408$13803_Y + connect \en_o \$15 + connect \o { \t3 \t2 \t1 \t0 } + connect \t3 \$11 + connect \t2 \$7 + connect \t1 \$3 + connect \t0 \i [0] + connect \ni \$1 +end +attribute \src "libresoc.v:183420.1-183468.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.wrpick_XER_xer_so" +attribute \generator "nMigen" +module \wrpick_XER_xer_so + attribute \src "libresoc.v:183453.17-183453.91" + wire $not$libresoc.v:183453$13804_Y + attribute \src "libresoc.v:183455.18-183455.93" + wire $not$libresoc.v:183455$13806_Y + attribute \src "libresoc.v:183457.17-183457.89" + wire width 4 $not$libresoc.v:183457$13808_Y + attribute \src "libresoc.v:183459.17-183459.91" + wire $not$libresoc.v:183459$13810_Y + attribute \src "libresoc.v:183454.18-183454.106" + wire $reduce_or$libresoc.v:183454$13805_Y + attribute \src "libresoc.v:183456.18-183456.90" + wire $reduce_or$libresoc.v:183456$13807_Y + attribute \src "libresoc.v:183458.17-183458.103" + wire $reduce_or$libresoc.v:183458$13809_Y + attribute \src "libresoc.v:183460.17-183460.105" + wire $reduce_or$libresoc.v:183460$13811_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire width 4 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 4 input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire width 4 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 4 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:183453$13804 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $not$libresoc.v:183453$13804_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:183455$13806 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$12 + connect \Y $not$libresoc.v:183455$13806_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $not$libresoc.v:183457$13808 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \i + connect \Y $not$libresoc.v:183457$13808_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:183459$13810 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$libresoc.v:183459$13810_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:183454$13805 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [2:0] \ni [3] } + connect \Y $reduce_or$libresoc.v:183454$13805_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_or $reduce_or$libresoc.v:183456$13807 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:183456$13807_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:183458$13809 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [0] \ni [1] } + connect \Y $reduce_or$libresoc.v:183458$13809_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:183460$13811 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [1:0] \ni [2] } + connect \Y $reduce_or$libresoc.v:183460$13811_Y + end + connect \$7 $not$libresoc.v:183453$13804_Y + connect \$12 $reduce_or$libresoc.v:183454$13805_Y + connect \$11 $not$libresoc.v:183455$13806_Y + connect \$15 $reduce_or$libresoc.v:183456$13807_Y + connect \$1 $not$libresoc.v:183457$13808_Y + connect \$4 $reduce_or$libresoc.v:183458$13809_Y + connect \$3 $not$libresoc.v:183459$13810_Y + connect \$8 $reduce_or$libresoc.v:183460$13811_Y + connect \en_o \$15 + connect \o { \t3 \t2 \t1 \t0 } + connect \t3 \$11 + connect \t2 \$7 + connect \t1 \$3 + connect \t0 \i [0] + connect \ni \$1 +end +attribute \src "libresoc.v:183472.1-183792.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.xer" +attribute \generator "nMigen" +module \xer + attribute \src "libresoc.v:183473.7-183473.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:183752.3-183760.6" + wire width 3 $0\ren_delay$11$next[2:0]$13835 + attribute \src "libresoc.v:183650.3-183651.43" + wire width 3 $0\ren_delay$11[2:0]$13824 + attribute \src "libresoc.v:183609.13-183609.34" + wire width 3 $0\ren_delay$11[2:0]$13841 + attribute \src "libresoc.v:183714.3-183722.6" + wire width 3 $0\ren_delay$18$next[2:0]$13827 + attribute \src "libresoc.v:183648.3-183649.43" + wire width 3 $0\ren_delay$18[2:0]$13822 + attribute \src "libresoc.v:183613.13-183613.34" + wire width 3 $0\ren_delay$18[2:0]$13843 + attribute \src "libresoc.v:183733.3-183741.6" + wire width 3 $0\ren_delay$next[2:0]$13831 + attribute \src "libresoc.v:183652.3-183653.35" + wire width 3 $0\ren_delay[2:0] + attribute \src "libresoc.v:183742.3-183751.6" + wire width 2 $0\src1__data_o[1:0] + attribute \src "libresoc.v:183761.3-183770.6" + wire width 2 $0\src2__data_o[1:0] + attribute \src "libresoc.v:183723.3-183732.6" + wire width 2 $0\src3__data_o[1:0] + attribute \src "libresoc.v:183752.3-183760.6" + wire width 3 $1\ren_delay$11$next[2:0]$13836 + attribute \src "libresoc.v:183714.3-183722.6" + wire width 3 $1\ren_delay$18$next[2:0]$13828 + attribute \src "libresoc.v:183733.3-183741.6" + wire width 3 $1\ren_delay$next[2:0]$13832 + attribute \src "libresoc.v:183607.13-183607.29" + wire width 3 $1\ren_delay[2:0] + attribute \src "libresoc.v:183742.3-183751.6" + wire width 2 $1\src1__data_o[1:0] + attribute \src "libresoc.v:183761.3-183770.6" + wire width 2 $1\src2__data_o[1:0] + attribute \src "libresoc.v:183723.3-183732.6" + wire width 2 $1\src3__data_o[1:0] + attribute \src "libresoc.v:183639.17-183639.109" + wire width 2 $or$libresoc.v:183639$13812_Y + attribute \src "libresoc.v:183641.18-183641.126" + wire width 2 $or$libresoc.v:183641$13814_Y + attribute \src "libresoc.v:183642.18-183642.111" + wire width 2 $or$libresoc.v:183642$13815_Y + attribute \src "libresoc.v:183644.18-183644.126" + wire width 2 $or$libresoc.v:183644$13817_Y + attribute \src "libresoc.v:183645.18-183645.111" + wire width 2 $or$libresoc.v:183645$13818_Y + attribute \src "libresoc.v:183647.17-183647.125" + wire width 2 $or$libresoc.v:183647$13820_Y + attribute \src "libresoc.v:183640.18-183640.100" + wire $reduce_or$libresoc.v:183640$13813_Y + attribute \src "libresoc.v:183643.18-183643.100" + wire $reduce_or$libresoc.v:183643$13816_Y + attribute \src "libresoc.v:183646.17-183646.95" + wire $reduce_or$libresoc.v:183646$13819_Y + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 2 \$14 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 2 \$16 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 2 \$21 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 2 \$23 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 2 \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 2 \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 16 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire input 15 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 input 9 \data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 input 11 \data_i$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 input 13 \data_i$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 6 output 2 \full_rd__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 3 input 1 \full_rd__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 6 \full_wr__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 3 \full_wr__wen + attribute \src "libresoc.v:183473.7-183473.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 \reg_0_dest10__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_0_dest10__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 \reg_0_dest20__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_0_dest20__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 \reg_0_dest30__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_0_dest30__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 \reg_0_r0__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_0_r0__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 \reg_0_src10__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_0_src10__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 \reg_0_src20__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_0_src20__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 \reg_0_src30__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_0_src30__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 \reg_0_w0__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_0_w0__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 \reg_1_dest11__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_1_dest11__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 \reg_1_dest21__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_1_dest21__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 \reg_1_dest31__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_1_dest31__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 \reg_1_r1__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_1_r1__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 \reg_1_src11__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_1_src11__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 \reg_1_src21__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_1_src21__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 \reg_1_src31__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_1_src31__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 \reg_1_w1__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_1_w1__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 \reg_2_dest12__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_2_dest12__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 \reg_2_dest22__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_2_dest22__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 \reg_2_dest32__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_2_dest32__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 \reg_2_r2__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_2_r2__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 \reg_2_src12__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_2_src12__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 \reg_2_src22__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_2_src22__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 \reg_2_src32__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_2_src32__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 \reg_2_w2__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_2_w2__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" + wire width 3 \ren_delay + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" + wire width 3 \ren_delay$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" + wire width 3 \ren_delay$11$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" + wire width 3 \ren_delay$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" + wire width 3 \ren_delay$18$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" + wire width 3 \ren_delay$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 output 3 \src1__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 3 input 4 \src1__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 output 5 \src2__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 3 input 6 \src2__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 output 7 \src3__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 3 input 8 \src3__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 3 input 10 \wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 3 input 12 \wen$2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 3 input 14 \wen$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $or$libresoc.v:183639$13812 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \reg_0_src10__data_o + connect \B \$7 + connect \Y $or$libresoc.v:183639$13812_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $or$libresoc.v:183641$13814 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \reg_1_src21__data_o + connect \B \reg_2_src22__data_o + connect \Y $or$libresoc.v:183641$13814_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $or$libresoc.v:183642$13815 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \reg_0_src20__data_o + connect \B \$14 + connect \Y $or$libresoc.v:183642$13815_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $or$libresoc.v:183644$13817 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \reg_1_src31__data_o + connect \B \reg_2_src32__data_o + connect \Y $or$libresoc.v:183644$13817_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $or$libresoc.v:183645$13818 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \reg_0_src30__data_o + connect \B \$21 + connect \Y $or$libresoc.v:183645$13818_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $or$libresoc.v:183647$13820 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \reg_1_src11__data_o + connect \B \reg_2_src12__data_o + connect \Y $or$libresoc.v:183647$13820_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + cell $reduce_or $reduce_or$libresoc.v:183640$13813 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \ren_delay$11 + connect \Y $reduce_or$libresoc.v:183640$13813_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + cell $reduce_or $reduce_or$libresoc.v:183643$13816 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \ren_delay$18 + connect \Y $reduce_or$libresoc.v:183643$13816_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + cell $reduce_or $reduce_or$libresoc.v:183646$13819 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \ren_delay + connect \Y $reduce_or$libresoc.v:183646$13819_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:183654.15-183673.4" + cell \reg_0$129 \reg_0 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \dest10__data_i \reg_0_dest10__data_i + connect \dest10__wen \reg_0_dest10__wen + connect \dest20__data_i \reg_0_dest20__data_i + connect \dest20__wen \reg_0_dest20__wen + connect \dest30__data_i \reg_0_dest30__data_i + connect \dest30__wen \reg_0_dest30__wen + connect \r0__data_o \reg_0_r0__data_o + connect \r0__ren \reg_0_r0__ren + connect \src10__data_o \reg_0_src10__data_o + connect \src10__ren \reg_0_src10__ren + connect \src20__data_o \reg_0_src20__data_o + connect \src20__ren \reg_0_src20__ren + connect \src30__data_o \reg_0_src30__data_o + connect \src30__ren \reg_0_src30__ren + connect \w0__data_i \reg_0_w0__data_i + connect \w0__wen \reg_0_w0__wen + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:183674.15-183693.4" + cell \reg_1$130 \reg_1 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \dest11__data_i \reg_1_dest11__data_i + connect \dest11__wen \reg_1_dest11__wen + connect \dest21__data_i \reg_1_dest21__data_i + connect \dest21__wen \reg_1_dest21__wen + connect \dest31__data_i \reg_1_dest31__data_i + connect \dest31__wen \reg_1_dest31__wen + connect \r1__data_o \reg_1_r1__data_o + connect \r1__ren \reg_1_r1__ren + connect \src11__data_o \reg_1_src11__data_o + connect \src11__ren \reg_1_src11__ren + connect \src21__data_o \reg_1_src21__data_o + connect \src21__ren \reg_1_src21__ren + connect \src31__data_o \reg_1_src31__data_o + connect \src31__ren \reg_1_src31__ren + connect \w1__data_i \reg_1_w1__data_i + connect \w1__wen \reg_1_w1__wen + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:183694.15-183713.4" + cell \reg_2$131 \reg_2 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \dest12__data_i \reg_2_dest12__data_i + connect \dest12__wen \reg_2_dest12__wen + connect \dest22__data_i \reg_2_dest22__data_i + connect \dest22__wen \reg_2_dest22__wen + connect \dest32__data_i \reg_2_dest32__data_i + connect \dest32__wen \reg_2_dest32__wen + connect \r2__data_o \reg_2_r2__data_o + connect \r2__ren \reg_2_r2__ren + connect \src12__data_o \reg_2_src12__data_o + connect \src12__ren \reg_2_src12__ren + connect \src22__data_o \reg_2_src22__data_o + connect \src22__ren \reg_2_src22__ren + connect \src32__data_o \reg_2_src32__data_o + connect \src32__ren \reg_2_src32__ren + connect \w2__data_i \reg_2_w2__data_i + connect \w2__wen \reg_2_w2__wen + end + attribute \src "libresoc.v:183473.7-183473.20" + process $proc$libresoc.v:183473$13838 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:183607.13-183607.29" + process $proc$libresoc.v:183607$13839 + assign { } { } + assign $1\ren_delay[2:0] 3'000 + sync always + sync init + update \ren_delay $1\ren_delay[2:0] + end + attribute \src "libresoc.v:183609.13-183609.34" + process $proc$libresoc.v:183609$13840 + assign { } { } + assign $0\ren_delay$11[2:0]$13841 3'000 + sync always + sync init + update \ren_delay$11 $0\ren_delay$11[2:0]$13841 + end + attribute \src "libresoc.v:183613.13-183613.34" + process $proc$libresoc.v:183613$13842 + assign { } { } + assign $0\ren_delay$18[2:0]$13843 3'000 + sync always + sync init + update \ren_delay$18 $0\ren_delay$18[2:0]$13843 + end + attribute \src "libresoc.v:183648.3-183649.43" + process $proc$libresoc.v:183648$13821 + assign { } { } + assign $0\ren_delay$18[2:0]$13822 \ren_delay$18$next + sync posedge \coresync_clk + update \ren_delay$18 $0\ren_delay$18[2:0]$13822 + end + attribute \src "libresoc.v:183650.3-183651.43" + process $proc$libresoc.v:183650$13823 + assign { } { } + assign $0\ren_delay$11[2:0]$13824 \ren_delay$11$next + sync posedge \coresync_clk + update \ren_delay$11 $0\ren_delay$11[2:0]$13824 + end + attribute \src "libresoc.v:183652.3-183653.35" + process $proc$libresoc.v:183652$13825 + assign { } { } + assign $0\ren_delay[2:0] \ren_delay$next + sync posedge \coresync_clk + update \ren_delay $0\ren_delay[2:0] + end + attribute \src "libresoc.v:183714.3-183722.6" + process $proc$libresoc.v:183714$13826 + assign { } { } + assign { } { } + assign $0\ren_delay$18$next[2:0]$13827 $1\ren_delay$18$next[2:0]$13828 + attribute \src "libresoc.v:183715.5-183715.29" + switch \initial + attribute \src "libresoc.v:183715.9-183715.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ren_delay$18$next[2:0]$13828 3'000 + case + assign $1\ren_delay$18$next[2:0]$13828 \src3__ren + end + sync always + update \ren_delay$18$next $0\ren_delay$18$next[2:0]$13827 + end + attribute \src "libresoc.v:183723.3-183732.6" + process $proc$libresoc.v:183723$13829 + assign { } { } + assign { } { } + assign $0\src3__data_o[1:0] $1\src3__data_o[1:0] + attribute \src "libresoc.v:183724.5-183724.29" + switch \initial + attribute \src "libresoc.v:183724.9-183724.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" + switch \$19 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src3__data_o[1:0] \$23 + case + assign $1\src3__data_o[1:0] 2'00 + end + sync always + update \src3__data_o $0\src3__data_o[1:0] + end + attribute \src "libresoc.v:183733.3-183741.6" + process $proc$libresoc.v:183733$13830 + assign { } { } + assign { } { } + assign $0\ren_delay$next[2:0]$13831 $1\ren_delay$next[2:0]$13832 + attribute \src "libresoc.v:183734.5-183734.29" + switch \initial + attribute \src "libresoc.v:183734.9-183734.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ren_delay$next[2:0]$13832 3'000 + case + assign $1\ren_delay$next[2:0]$13832 \src1__ren + end + sync always + update \ren_delay$next $0\ren_delay$next[2:0]$13831 + end + attribute \src "libresoc.v:183742.3-183751.6" + process $proc$libresoc.v:183742$13833 + assign { } { } + assign { } { } + assign $0\src1__data_o[1:0] $1\src1__data_o[1:0] + attribute \src "libresoc.v:183743.5-183743.29" + switch \initial + attribute \src "libresoc.v:183743.9-183743.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" + switch \$5 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src1__data_o[1:0] \$9 + case + assign $1\src1__data_o[1:0] 2'00 + end + sync always + update \src1__data_o $0\src1__data_o[1:0] + end + attribute \src "libresoc.v:183752.3-183760.6" + process $proc$libresoc.v:183752$13834 + assign { } { } + assign { } { } + assign $0\ren_delay$11$next[2:0]$13835 $1\ren_delay$11$next[2:0]$13836 + attribute \src "libresoc.v:183753.5-183753.29" + switch \initial + attribute \src "libresoc.v:183753.9-183753.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ren_delay$11$next[2:0]$13836 3'000 + case + assign $1\ren_delay$11$next[2:0]$13836 \src2__ren + end + sync always + update \ren_delay$11$next $0\ren_delay$11$next[2:0]$13835 + end + attribute \src "libresoc.v:183761.3-183770.6" + process $proc$libresoc.v:183761$13837 + assign { } { } + assign { } { } + assign $0\src2__data_o[1:0] $1\src2__data_o[1:0] + attribute \src "libresoc.v:183762.5-183762.29" + switch \initial + attribute \src "libresoc.v:183762.9-183762.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" + switch \$12 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src2__data_o[1:0] \$16 + case + assign $1\src2__data_o[1:0] 2'00 + end + sync always + update \src2__data_o $0\src2__data_o[1:0] + end + connect \$9 $or$libresoc.v:183639$13812_Y + connect \$12 $reduce_or$libresoc.v:183640$13813_Y + connect \$14 $or$libresoc.v:183641$13814_Y + connect \$16 $or$libresoc.v:183642$13815_Y + connect \$19 $reduce_or$libresoc.v:183643$13816_Y + connect \$21 $or$libresoc.v:183644$13817_Y + connect \$23 $or$libresoc.v:183645$13818_Y + connect \$5 $reduce_or$libresoc.v:183646$13819_Y + connect \$7 $or$libresoc.v:183647$13820_Y + connect \full_wr__data_i 6'000000 + connect \full_wr__wen 3'000 + connect { \reg_2_w2__wen \reg_1_w1__wen \reg_0_w0__wen } 3'000 + connect { \reg_2_w2__data_i \reg_1_w1__data_i \reg_0_w0__data_i } 6'000000 + connect { \reg_2_r2__ren \reg_1_r1__ren \reg_0_r0__ren } \full_rd__ren + connect \full_rd__data_o { \reg_2_r2__data_o \reg_1_r1__data_o \reg_0_r0__data_o } + connect \reg_2_dest32__data_i \data_i$1 + connect \reg_1_dest31__data_i \data_i$1 + connect \reg_0_dest30__data_i \data_i$1 + connect { \reg_2_dest32__wen \reg_1_dest31__wen \reg_0_dest30__wen } \wen$2 + connect \reg_2_dest22__data_i \data_i + connect \reg_1_dest21__data_i \data_i + connect \reg_0_dest20__data_i \data_i + connect { \reg_2_dest22__wen \reg_1_dest21__wen \reg_0_dest20__wen } \wen + connect \reg_2_dest12__data_i \data_i$3 + connect \reg_1_dest11__data_i \data_i$3 + connect \reg_0_dest10__data_i \data_i$3 + connect { \reg_2_dest12__wen \reg_1_dest11__wen \reg_0_dest10__wen } \wen$4 + connect { \reg_2_src32__ren \reg_1_src31__ren \reg_0_src30__ren } \src3__ren + connect { \reg_2_src22__ren \reg_1_src21__ren \reg_0_src20__ren } \src2__ren + connect { \reg_2_src12__ren \reg_1_src11__ren \reg_0_src10__ren } \src1__ren +end +attribute \src "libresoc.v:183796.1-184110.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.xics_icp" +attribute \generator "nMigen" +module \xics_icp + attribute \src "libresoc.v:183974.3-184002.6" + wire width 32 $0\be_out[31:0] + attribute \src "libresoc.v:184025.3-184033.6" + wire $0\core_irq_o$next[0:0]$13879 + attribute \src "libresoc.v:183916.3-183917.37" + wire $0\core_irq_o[0:0] + attribute \src "libresoc.v:184044.3-184106.6" + wire width 8 $0\cppr$10[7:0]$13883 + attribute \src "libresoc.v:183930.3-183945.6" + wire width 8 $0\cppr$next[7:0]$13862 + attribute \src "libresoc.v:183920.3-183921.25" + wire width 8 $0\cppr[7:0] + attribute \src "libresoc.v:184034.3-184043.6" + wire width 32 $0\icp_wb__dat_r[31:0] + attribute \src "libresoc.v:183797.7-183797.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:184044.3-184106.6" + wire $0\irq$12[0:0]$13884 + attribute \src "libresoc.v:183930.3-183945.6" + wire $0\irq$next[0:0]$13863 + attribute \src "libresoc.v:183924.3-183925.23" + wire $0\irq[0:0] + attribute \src "libresoc.v:184044.3-184106.6" + wire width 8 $0\mfrr$11[7:0]$13885 + attribute \src "libresoc.v:183930.3-183945.6" + wire width 8 $0\mfrr$next[7:0]$13864 + attribute \src "libresoc.v:183922.3-183923.25" + wire width 8 $0\mfrr[7:0] + attribute \src "libresoc.v:184013.3-184024.6" + wire width 8 $0\min_pri[7:0] + attribute \src "libresoc.v:184003.3-184012.6" + wire width 8 $0\pending_priority[7:0] + attribute \src "libresoc.v:184044.3-184106.6" + wire $0\wb_ack$14[0:0]$13886 + attribute \src "libresoc.v:183930.3-183945.6" + wire $0\wb_ack$next[0:0]$13865 + attribute \src "libresoc.v:183928.3-183929.29" + wire $0\wb_ack[0:0] + attribute \src "libresoc.v:184044.3-184106.6" + wire width 32 $0\wb_rd_data$13[31:0]$13887 + attribute \src "libresoc.v:183930.3-183945.6" + wire width 32 $0\wb_rd_data$next[31:0]$13866 + attribute \src "libresoc.v:183926.3-183927.37" + wire width 32 $0\wb_rd_data[31:0] + attribute \src "libresoc.v:183946.3-183973.6" + wire $0\xirr_accept_rd[0:0] + attribute \src "libresoc.v:184044.3-184106.6" + wire width 24 $0\xisr$9[23:0]$13888 + attribute \src "libresoc.v:183930.3-183945.6" + wire width 24 $0\xisr$next[23:0]$13867 + attribute \src "libresoc.v:183918.3-183919.25" + wire width 24 $0\xisr[23:0] + attribute \src "libresoc.v:183974.3-184002.6" + wire width 32 $1\be_out[31:0] + attribute \src "libresoc.v:184025.3-184033.6" + wire $1\core_irq_o$next[0:0]$13880 + attribute \src "libresoc.v:183826.7-183826.24" + wire $1\core_irq_o[0:0] + attribute \src "libresoc.v:184044.3-184106.6" + wire width 8 $1\cppr$10[7:0]$13889 + attribute \src "libresoc.v:183930.3-183945.6" + wire width 8 $1\cppr$next[7:0]$13868 + attribute \src "libresoc.v:183830.13-183830.25" + wire width 8 $1\cppr[7:0] + attribute \src "libresoc.v:184034.3-184043.6" + wire width 32 $1\icp_wb__dat_r[31:0] + attribute \src "libresoc.v:184044.3-184106.6" + wire $1\irq$12[0:0]$13899 + attribute \src "libresoc.v:183930.3-183945.6" + wire $1\irq$next[0:0]$13869 + attribute \src "libresoc.v:183859.7-183859.17" + wire $1\irq[0:0] + attribute \src "libresoc.v:184044.3-184106.6" + wire width 8 $1\mfrr$11[7:0]$13890 + attribute \src "libresoc.v:183930.3-183945.6" + wire width 8 $1\mfrr$next[7:0]$13870 + attribute \src "libresoc.v:183867.13-183867.25" + wire width 8 $1\mfrr[7:0] + attribute \src "libresoc.v:184013.3-184024.6" + wire width 8 $1\min_pri[7:0] + attribute \src "libresoc.v:184003.3-184012.6" + wire width 8 $1\pending_priority[7:0] + attribute \src "libresoc.v:184044.3-184106.6" + wire $1\wb_ack$14[0:0]$13891 + attribute \src "libresoc.v:183930.3-183945.6" + wire $1\wb_ack$next[0:0]$13871 + attribute \src "libresoc.v:183881.7-183881.20" + wire $1\wb_ack[0:0] + attribute \src "libresoc.v:183930.3-183945.6" + wire width 32 $1\wb_rd_data$next[31:0]$13872 + attribute \src "libresoc.v:183889.14-183889.32" + wire width 32 $1\wb_rd_data[31:0] + attribute \src "libresoc.v:183946.3-183973.6" + wire $1\xirr_accept_rd[0:0] + attribute \src "libresoc.v:184044.3-184106.6" + wire width 24 $1\xisr$9[23:0]$13896 + attribute \src "libresoc.v:183930.3-183945.6" + wire width 24 $1\xisr$next[23:0]$13873 + attribute \src "libresoc.v:183899.14-183899.31" + wire width 24 $1\xisr[23:0] + attribute \src "libresoc.v:183974.3-184002.6" + wire width 32 $2\be_out[31:0] + attribute \src "libresoc.v:184044.3-184106.6" + wire width 8 $2\cppr$10[7:0]$13892 + attribute \src "libresoc.v:184044.3-184106.6" + wire width 8 $2\mfrr$11[7:0]$13893 + attribute \src "libresoc.v:183946.3-183973.6" + wire $2\xirr_accept_rd[0:0] + attribute \src "libresoc.v:184044.3-184106.6" + wire width 24 $2\xisr$9[23:0]$13897 + attribute \src "libresoc.v:183974.3-184002.6" + wire width 32 $3\be_out[31:0] + attribute \src "libresoc.v:184044.3-184106.6" + wire width 8 $3\cppr$10[7:0]$13894 + attribute \src "libresoc.v:184044.3-184106.6" + wire width 8 $3\mfrr$11[7:0]$13895 + attribute \src "libresoc.v:183946.3-183973.6" + wire $3\xirr_accept_rd[0:0] + attribute \src "libresoc.v:184044.3-184106.6" + wire width 8 $4\cppr$10[7:0]$13898 + attribute \src "libresoc.v:183946.3-183973.6" + wire $4\xirr_accept_rd[0:0] + attribute \src "libresoc.v:183906.18-183906.116" + wire $and$libresoc.v:183906$13844_Y + attribute \src "libresoc.v:183910.18-183910.116" + wire $and$libresoc.v:183910$13848_Y + attribute \src "libresoc.v:183912.18-183912.116" + wire $and$libresoc.v:183912$13850_Y + attribute \src "libresoc.v:183915.17-183915.109" + wire $and$libresoc.v:183915$13853_Y + attribute \src "libresoc.v:183911.18-183911.110" + wire $eq$libresoc.v:183911$13849_Y + attribute \src "libresoc.v:183908.18-183908.114" + wire $lt$libresoc.v:183908$13846_Y + attribute \src "libresoc.v:183909.18-183909.109" + wire $lt$libresoc.v:183909$13847_Y + attribute \src "libresoc.v:183914.18-183914.114" + wire $lt$libresoc.v:183914$13852_Y + attribute \src "libresoc.v:183907.18-183907.109" + wire $ne$libresoc.v:183907$13845_Y + attribute \src "libresoc.v:183913.18-183913.109" + wire $ne$libresoc.v:183913$13851_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173" + wire \$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:178" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:195" + wire \$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:162" + wire \$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173" + wire \$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:178" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:96" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:103" + wire width 32 \be_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:104" + wire width 32 \be_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:151" + wire input 3 \clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:83" + wire output 2 \core_irq_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:83" + wire \core_irq_o$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:62" + wire width 8 \cppr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:62" + wire width 8 \cppr$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:62" + wire width 8 \cppr$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:62" + wire width 8 \cppr$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire output 5 \icp_wb__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire width 28 input 11 \icp_wb__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire input 6 \icp_wb__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire width 32 output 7 \icp_wb__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire width 32 input 8 \icp_wb__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire width 4 input 12 \icp_wb__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire input 9 \icp_wb__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire input 10 \icp_wb__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:46" + wire width 8 input 1 \ics_i_pri + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:45" + wire width 4 input 13 \ics_i_src + attribute \src "libresoc.v:183797.7-183797.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:64" + wire \irq + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:64" + wire \irq$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:64" + wire \irq$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:64" + wire \irq$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:63" + wire width 8 \mfrr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:63" + wire width 8 \mfrr$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:63" + wire width 8 \mfrr$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:63" + wire width 8 \mfrr$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:107" + wire width 8 \min_pri + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:106" + wire width 8 \pending_priority + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:151" + wire input 4 \rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:66" + wire \wb_ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:66" + wire \wb_ack$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:66" + wire \wb_ack$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:66" + wire \wb_ack$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:65" + wire width 32 \wb_rd_data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:65" + wire width 32 \wb_rd_data$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:65" + wire width 32 \wb_rd_data$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:65" + wire width 32 \wb_rd_data$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:101" + wire \xirr_accept_rd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:61" + wire width 24 \xisr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:61" + wire width 24 \xisr$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:61" + wire width 24 \xisr$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:61" + wire width 24 \xisr$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" + cell $and $and$libresoc.v:183906$13844 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \icp_wb__cyc + connect \B \icp_wb__stb + connect \Y $and$libresoc.v:183906$13844_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" + cell $and $and$libresoc.v:183910$13848 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \icp_wb__cyc + connect \B \icp_wb__stb + connect \Y $and$libresoc.v:183910$13848_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" + cell $and $and$libresoc.v:183912$13850 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \icp_wb__cyc + connect \B \icp_wb__stb + connect \Y $and$libresoc.v:183912$13850_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:96" + cell $and $and$libresoc.v:183915$13853 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wb_ack + connect \B \icp_wb__cyc + connect \Y $and$libresoc.v:183915$13853_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:162" + cell $eq $eq$libresoc.v:183911$13849 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \icp_wb__sel + connect \B 4'1111 + connect \Y $eq$libresoc.v:183911$13849_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:178" + cell $lt $lt$libresoc.v:183908$13846 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \mfrr + connect \B \pending_priority + connect \Y $lt$libresoc.v:183908$13846_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:195" + cell $lt $lt$libresoc.v:183909$13847 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \min_pri + connect \B \cppr$10 + connect \Y $lt$libresoc.v:183909$13847_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:178" + cell $lt $lt$libresoc.v:183914$13852 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \mfrr + connect \B \pending_priority + connect \Y $lt$libresoc.v:183914$13852_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173" + cell $ne $ne$libresoc.v:183907$13845 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ics_i_pri + connect \B 8'11111111 + connect \Y $ne$libresoc.v:183907$13845_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173" + cell $ne $ne$libresoc.v:183913$13851 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ics_i_pri + connect \B 8'11111111 + connect \Y $ne$libresoc.v:183913$13851_Y + end + attribute \src "libresoc.v:183797.7-183797.20" + process $proc$libresoc.v:183797$13900 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:183826.7-183826.24" + process $proc$libresoc.v:183826$13901 + assign { } { } + assign $1\core_irq_o[0:0] 1'0 + sync always + sync init + update \core_irq_o $1\core_irq_o[0:0] + end + attribute \src "libresoc.v:183830.13-183830.25" + process $proc$libresoc.v:183830$13902 + assign { } { } + assign $1\cppr[7:0] 8'00000000 + sync always + sync init + update \cppr $1\cppr[7:0] + end + attribute \src "libresoc.v:183859.7-183859.17" + process $proc$libresoc.v:183859$13903 + assign { } { } + assign $1\irq[0:0] 1'0 + sync always + sync init + update \irq $1\irq[0:0] + end + attribute \src "libresoc.v:183867.13-183867.25" + process $proc$libresoc.v:183867$13904 + assign { } { } + assign $1\mfrr[7:0] 8'11111111 + sync always + sync init + update \mfrr $1\mfrr[7:0] + end + attribute \src "libresoc.v:183881.7-183881.20" + process $proc$libresoc.v:183881$13905 + assign { } { } + assign $1\wb_ack[0:0] 1'0 + sync always + sync init + update \wb_ack $1\wb_ack[0:0] + end + attribute \src "libresoc.v:183889.14-183889.32" + process $proc$libresoc.v:183889$13906 + assign { } { } + assign $1\wb_rd_data[31:0] 0 + sync always + sync init + update \wb_rd_data $1\wb_rd_data[31:0] + end + attribute \src "libresoc.v:183899.14-183899.31" + process $proc$libresoc.v:183899$13907 + assign { } { } + assign $1\xisr[23:0] 24'000000000000000000000000 + sync always + sync init + update \xisr $1\xisr[23:0] + end + attribute \src "libresoc.v:183916.3-183917.37" + process $proc$libresoc.v:183916$13854 + assign { } { } + assign $0\core_irq_o[0:0] \core_irq_o$next + sync posedge \clk + update \core_irq_o $0\core_irq_o[0:0] + end + attribute \src "libresoc.v:183918.3-183919.25" + process $proc$libresoc.v:183918$13855 + assign { } { } + assign $0\xisr[23:0] \xisr$next + sync posedge \clk + update \xisr $0\xisr[23:0] + end + attribute \src "libresoc.v:183920.3-183921.25" + process $proc$libresoc.v:183920$13856 + assign { } { } + assign $0\cppr[7:0] \cppr$next + sync posedge \clk + update \cppr $0\cppr[7:0] + end + attribute \src "libresoc.v:183922.3-183923.25" + process $proc$libresoc.v:183922$13857 + assign { } { } + assign $0\mfrr[7:0] \mfrr$next + sync posedge \clk + update \mfrr $0\mfrr[7:0] + end + attribute \src "libresoc.v:183924.3-183925.23" + process $proc$libresoc.v:183924$13858 + assign { } { } + assign $0\irq[0:0] \irq$next + sync posedge \clk + update \irq $0\irq[0:0] + end + attribute \src "libresoc.v:183926.3-183927.37" + process $proc$libresoc.v:183926$13859 + assign { } { } + assign $0\wb_rd_data[31:0] \wb_rd_data$next + sync posedge \clk + update \wb_rd_data $0\wb_rd_data[31:0] + end + attribute \src "libresoc.v:183928.3-183929.29" + process $proc$libresoc.v:183928$13860 + assign { } { } + assign $0\wb_ack[0:0] \wb_ack$next + sync posedge \clk + update \wb_ack $0\wb_ack[0:0] + end + attribute \src "libresoc.v:183930.3-183945.6" + process $proc$libresoc.v:183930$13861 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\cppr$next[7:0]$13862 $1\cppr$next[7:0]$13868 + assign $0\irq$next[0:0]$13863 $1\irq$next[0:0]$13869 + assign $0\mfrr$next[7:0]$13864 $1\mfrr$next[7:0]$13870 + assign $0\wb_ack$next[0:0]$13865 $1\wb_ack$next[0:0]$13871 + assign $0\wb_rd_data$next[31:0]$13866 $1\wb_rd_data$next[31:0]$13872 + assign $0\xisr$next[23:0]$13867 $1\xisr$next[23:0]$13873 + attribute \src "libresoc.v:183931.5-183931.29" + switch \initial + attribute \src "libresoc.v:183931.9-183931.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\xisr$next[23:0]$13873 24'000000000000000000000000 + assign $1\cppr$next[7:0]$13868 8'00000000 + assign $1\mfrr$next[7:0]$13870 8'11111111 + assign $1\irq$next[0:0]$13869 1'0 + assign $1\wb_rd_data$next[31:0]$13872 0 + assign $1\wb_ack$next[0:0]$13871 1'0 + case + assign $1\cppr$next[7:0]$13868 \cppr$2 + assign $1\irq$next[0:0]$13869 \irq$4 + assign $1\mfrr$next[7:0]$13870 \mfrr$3 + assign $1\wb_ack$next[0:0]$13871 \wb_ack$6 + assign $1\wb_rd_data$next[31:0]$13872 \wb_rd_data$5 + assign $1\xisr$next[23:0]$13873 \xisr$1 + end + sync always + update \cppr$next $0\cppr$next[7:0]$13862 + update \irq$next $0\irq$next[0:0]$13863 + update \mfrr$next $0\mfrr$next[7:0]$13864 + update \wb_ack$next $0\wb_ack$next[0:0]$13865 + update \wb_rd_data$next $0\wb_rd_data$next[31:0]$13866 + update \xisr$next $0\xisr$next[23:0]$13867 + end + attribute \src "libresoc.v:183946.3-183973.6" + process $proc$libresoc.v:183946$13874 + assign { } { } + assign { } { } + assign $0\xirr_accept_rd[0:0] $1\xirr_accept_rd[0:0] + attribute \src "libresoc.v:183947.5-183947.29" + switch \initial + attribute \src "libresoc.v:183947.9-183947.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" + switch \$23 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\xirr_accept_rd[0:0] $2\xirr_accept_rd[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:119" + switch \icp_wb__we + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $2\xirr_accept_rd[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\xirr_accept_rd[0:0] $3\xirr_accept_rd[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:155" + switch \icp_wb__adr [5:0] + attribute \src "libresoc.v:0.0-0.0" + case 6'000001 + assign { } { } + assign $3\xirr_accept_rd[0:0] $4\xirr_accept_rd[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:162" + switch \$25 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\xirr_accept_rd[0:0] 1'1 + case + assign $4\xirr_accept_rd[0:0] 1'0 + end + case + assign $3\xirr_accept_rd[0:0] 1'0 + end + end + case + assign $1\xirr_accept_rd[0:0] 1'0 + end + sync always + update \xirr_accept_rd $0\xirr_accept_rd[0:0] + end + attribute \src "libresoc.v:183974.3-184002.6" + process $proc$libresoc.v:183974$13875 + assign { } { } + assign { } { } + assign $0\be_out[31:0] $1\be_out[31:0] + attribute \src "libresoc.v:183975.5-183975.29" + switch \initial + attribute \src "libresoc.v:183975.9-183975.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" + switch \$27 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\be_out[31:0] $2\be_out[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:119" + switch \icp_wb__we + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $2\be_out[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\be_out[31:0] $3\be_out[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:155" + switch \icp_wb__adr [5:0] + attribute \src "libresoc.v:0.0-0.0" + case 6'000000 + assign { } { } + assign $3\be_out[31:0] { \cppr \xisr } + attribute \src "libresoc.v:0.0-0.0" + case 6'000001 + assign { } { } + assign $3\be_out[31:0] { \cppr \xisr } + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign $3\be_out[31:0] [23:0] 24'000000000000000000000000 + assign $3\be_out[31:0] [31:24] \mfrr + case + assign $3\be_out[31:0] 0 + end + end + case + assign $1\be_out[31:0] 0 + end + sync always + update \be_out $0\be_out[31:0] + end + attribute \src "libresoc.v:184003.3-184012.6" + process $proc$libresoc.v:184003$13876 + assign { } { } + assign { } { } + assign $0\pending_priority[7:0] $1\pending_priority[7:0] + attribute \src "libresoc.v:184004.5-184004.29" + switch \initial + attribute \src "libresoc.v:184004.9-184004.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173" + switch \$29 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\pending_priority[7:0] \ics_i_pri + case + assign $1\pending_priority[7:0] 8'11111111 + end + sync always + update \pending_priority $0\pending_priority[7:0] + end + attribute \src "libresoc.v:184013.3-184024.6" + process $proc$libresoc.v:184013$13877 + assign { } { } + assign $0\min_pri[7:0] $1\min_pri[7:0] + attribute \src "libresoc.v:184014.5-184014.29" + switch \initial + attribute \src "libresoc.v:184014.9-184014.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:178" + switch \$31 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\min_pri[7:0] \mfrr + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\min_pri[7:0] \pending_priority + end + sync always + update \min_pri $0\min_pri[7:0] + end + attribute \src "libresoc.v:184025.3-184033.6" + process $proc$libresoc.v:184025$13878 + assign { } { } + assign { } { } + assign $0\core_irq_o$next[0:0]$13879 $1\core_irq_o$next[0:0]$13880 + attribute \src "libresoc.v:184026.5-184026.29" + switch \initial + attribute \src "libresoc.v:184026.9-184026.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\core_irq_o$next[0:0]$13880 1'0 + case + assign $1\core_irq_o$next[0:0]$13880 \irq + end + sync always + update \core_irq_o$next $0\core_irq_o$next[0:0]$13879 + end + attribute \src "libresoc.v:184034.3-184043.6" + process $proc$libresoc.v:184034$13881 + assign { } { } + assign { } { } + assign $0\icp_wb__dat_r[31:0] $1\icp_wb__dat_r[31:0] + attribute \src "libresoc.v:184035.5-184035.29" + switch \initial + attribute \src "libresoc.v:184035.9-184035.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:97" + switch \icp_wb__ack + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\icp_wb__dat_r[31:0] \wb_rd_data + case + assign $1\icp_wb__dat_r[31:0] 0 + end + sync always + update \icp_wb__dat_r $0\icp_wb__dat_r[31:0] + end + attribute \src "libresoc.v:184044.3-184106.6" + process $proc$libresoc.v:184044$13882 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\mfrr$11[7:0]$13885 $1\mfrr$11[7:0]$13890 + assign $0\wb_ack$14[0:0]$13886 $1\wb_ack$14[0:0]$13891 + assign { } { } + assign { } { } + assign { } { } + assign $0\xisr$9[23:0]$13888 $2\xisr$9[23:0]$13897 + assign $0\cppr$10[7:0]$13883 $4\cppr$10[7:0]$13898 + assign $0\wb_rd_data$13[31:0]$13887 { \be_out [7:0] \be_out [15:8] \be_out [23:16] \be_out [31:24] } + assign $0\irq$12[0:0]$13884 $1\irq$12[0:0]$13899 + attribute \src "libresoc.v:184045.5-184045.29" + switch \initial + attribute \src "libresoc.v:184045.9-184045.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" + switch \$15 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign $1\wb_ack$14[0:0]$13891 1'1 + assign $1\cppr$10[7:0]$13889 $2\cppr$10[7:0]$13892 + assign $1\mfrr$11[7:0]$13890 $2\mfrr$11[7:0]$13893 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:119" + switch \icp_wb__we + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $2\cppr$10[7:0]$13892 $3\cppr$10[7:0]$13894 + assign $2\mfrr$11[7:0]$13893 $3\mfrr$11[7:0]$13895 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:121" + switch \icp_wb__adr [5:0] + attribute \src "libresoc.v:0.0-0.0" + case 6'000000 + assign { } { } + assign $3\mfrr$11[7:0]$13895 \mfrr + assign $3\cppr$10[7:0]$13894 \be_in [31:24] + attribute \src "libresoc.v:0.0-0.0" + case 6'000001 + assign { } { } + assign $3\mfrr$11[7:0]$13895 \mfrr + assign $3\cppr$10[7:0]$13894 \be_in [31:24] + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign $3\cppr$10[7:0]$13894 \cppr + assign { } { } + assign $3\mfrr$11[7:0]$13895 \be_in [31:24] + case + assign $3\cppr$10[7:0]$13894 \cppr + assign $3\mfrr$11[7:0]$13895 \mfrr + end + case + assign $2\cppr$10[7:0]$13892 \cppr + assign $2\mfrr$11[7:0]$13893 \mfrr + end + case + assign $1\cppr$10[7:0]$13889 \cppr + assign $1\mfrr$11[7:0]$13890 \mfrr + assign $1\wb_ack$14[0:0]$13891 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173" + switch \$17 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\xisr$9[23:0]$13896 { 20'00000000000000000001 \ics_i_src } + case + assign $1\xisr$9[23:0]$13896 24'000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:178" + switch \$19 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\xisr$9[23:0]$13897 24'000000000000000000000010 + case + assign $2\xisr$9[23:0]$13897 $1\xisr$9[23:0]$13896 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:185" + switch \xirr_accept_rd + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\cppr$10[7:0]$13898 \min_pri + case + assign $4\cppr$10[7:0]$13898 $1\cppr$10[7:0]$13889 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:195" + switch { \irq \$21 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\irq$12[0:0]$13899 1'1 + case + assign $1\irq$12[0:0]$13899 1'0 + end + sync always + update \cppr$10 $0\cppr$10[7:0]$13883 + update \irq$12 $0\irq$12[0:0]$13884 + update \mfrr$11 $0\mfrr$11[7:0]$13885 + update \wb_ack$14 $0\wb_ack$14[0:0]$13886 + update \wb_rd_data$13 $0\wb_rd_data$13[31:0]$13887 + update \xisr$9 $0\xisr$9[23:0]$13888 + end + connect \$15 $and$libresoc.v:183906$13844_Y + connect \$17 $ne$libresoc.v:183907$13845_Y + connect \$19 $lt$libresoc.v:183908$13846_Y + connect \$21 $lt$libresoc.v:183909$13847_Y + connect \$23 $and$libresoc.v:183910$13848_Y + connect \$25 $eq$libresoc.v:183911$13849_Y + connect \$27 $and$libresoc.v:183912$13850_Y + connect \$29 $ne$libresoc.v:183913$13851_Y + connect \$31 $lt$libresoc.v:183914$13852_Y + connect \$7 $and$libresoc.v:183915$13853_Y + connect { \wb_ack$6 \wb_rd_data$5 \irq$4 \mfrr$3 \cppr$2 \xisr$1 } { \wb_ack$14 \wb_rd_data$13 \irq$12 \mfrr$11 \cppr$10 \xisr$9 } + connect \be_in { \icp_wb__dat_w [7:0] \icp_wb__dat_w [15:8] \icp_wb__dat_w [23:16] \icp_wb__dat_w [31:24] } + connect \icp_wb__ack \$7 +end +attribute \src "libresoc.v:184114.1-185163.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.xics_ics" +attribute \generator "nMigen" +module \xics_ics + attribute \src "libresoc.v:185044.3-185093.6" + wire width 32 $0\be_out[31:0] + attribute \src "libresoc.v:184755.3-184764.6" + wire width 4 $0\cur_idx0[3:0] + attribute \src "libresoc.v:184964.3-184973.6" + wire width 4 $0\cur_idx10[3:0] + attribute \src "libresoc.v:184984.3-184993.6" + wire width 4 $0\cur_idx11[3:0] + attribute \src "libresoc.v:185004.3-185013.6" + wire width 4 $0\cur_idx12[3:0] + attribute \src "libresoc.v:185024.3-185033.6" + wire width 4 $0\cur_idx13[3:0] + attribute \src "libresoc.v:185094.3-185103.6" + wire width 4 $0\cur_idx14[3:0] + attribute \src "libresoc.v:185114.3-185123.6" + wire width 4 $0\cur_idx15[3:0] + attribute \src "libresoc.v:184775.3-184784.6" + wire width 4 $0\cur_idx1[3:0] + attribute \src "libresoc.v:184795.3-184804.6" + wire width 4 $0\cur_idx2[3:0] + attribute \src "libresoc.v:184815.3-184824.6" + wire width 4 $0\cur_idx3[3:0] + attribute \src "libresoc.v:184844.3-184853.6" + wire width 4 $0\cur_idx4[3:0] + attribute \src "libresoc.v:184864.3-184873.6" + wire width 4 $0\cur_idx5[3:0] + attribute \src "libresoc.v:184884.3-184893.6" + wire width 4 $0\cur_idx6[3:0] + attribute \src "libresoc.v:184904.3-184913.6" + wire width 4 $0\cur_idx7[3:0] + attribute \src "libresoc.v:184924.3-184933.6" + wire width 4 $0\cur_idx8[3:0] + attribute \src "libresoc.v:184944.3-184953.6" + wire width 4 $0\cur_idx9[3:0] + attribute \src "libresoc.v:184745.3-184754.6" + wire width 8 $0\cur_pri0[7:0] + attribute \src "libresoc.v:184954.3-184963.6" + wire width 8 $0\cur_pri10[7:0] + attribute \src "libresoc.v:184974.3-184983.6" + wire width 8 $0\cur_pri11[7:0] + attribute \src "libresoc.v:184994.3-185003.6" + wire width 8 $0\cur_pri12[7:0] + attribute \src "libresoc.v:185014.3-185023.6" + wire width 8 $0\cur_pri13[7:0] + attribute \src "libresoc.v:185034.3-185043.6" + wire width 8 $0\cur_pri14[7:0] + attribute \src "libresoc.v:185104.3-185113.6" + wire width 8 $0\cur_pri15[7:0] + attribute \src "libresoc.v:184765.3-184774.6" + wire width 8 $0\cur_pri1[7:0] + attribute \src "libresoc.v:184785.3-184794.6" + wire width 8 $0\cur_pri2[7:0] + attribute \src "libresoc.v:184805.3-184814.6" + wire width 8 $0\cur_pri3[7:0] + attribute \src "libresoc.v:184825.3-184834.6" + wire width 8 $0\cur_pri4[7:0] + attribute \src "libresoc.v:184854.3-184863.6" + wire width 8 $0\cur_pri5[7:0] + attribute \src "libresoc.v:184874.3-184883.6" + wire width 8 $0\cur_pri6[7:0] + attribute \src "libresoc.v:184894.3-184903.6" + wire width 8 $0\cur_pri7[7:0] + attribute \src "libresoc.v:184914.3-184923.6" + wire width 8 $0\cur_pri8[7:0] + attribute \src "libresoc.v:184934.3-184943.6" + wire width 8 $0\cur_pri9[7:0] + attribute \src "libresoc.v:185124.3-185133.6" + wire $0\ibit[0:0] + attribute \src "libresoc.v:184619.3-184620.25" + wire width 8 $0\icp_o_pri[7:0] + attribute \src "libresoc.v:184617.3-184618.28" + wire width 4 $0\icp_o_src[3:0] + attribute \src "libresoc.v:185143.3-185151.6" + wire $0\ics_wb__ack$next[0:0]$14154 + attribute \src "libresoc.v:184653.3-184654.39" + wire $0\ics_wb__ack[0:0] + attribute \src "libresoc.v:185134.3-185142.6" + wire width 32 $0\ics_wb__dat_r$next[31:0]$14151 + attribute \src "libresoc.v:184655.3-184656.43" + wire width 32 $0\ics_wb__dat_r[31:0] + attribute \src "libresoc.v:184115.7-184115.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:184835.3-184843.6" + wire width 16 $0\int_level_l$next[15:0]$14123 + attribute \src "libresoc.v:184657.3-184658.39" + wire width 16 $0\int_level_l[15:0] + attribute \src "libresoc.v:184659.3-184744.6" + wire width 8 $0\xive0_pri$next[7:0]$14033 + attribute \src "libresoc.v:184621.3-184622.35" + wire width 8 $0\xive0_pri[7:0] + attribute \src "libresoc.v:184659.3-184744.6" + wire width 8 $0\xive10_pri$next[7:0]$14034 + attribute \src "libresoc.v:184641.3-184642.37" + wire width 8 $0\xive10_pri[7:0] + attribute \src "libresoc.v:184659.3-184744.6" + wire width 8 $0\xive11_pri$next[7:0]$14035 + attribute \src "libresoc.v:184643.3-184644.37" + wire width 8 $0\xive11_pri[7:0] + attribute \src "libresoc.v:184659.3-184744.6" + wire width 8 $0\xive12_pri$next[7:0]$14036 + attribute \src "libresoc.v:184645.3-184646.37" + wire width 8 $0\xive12_pri[7:0] + attribute \src "libresoc.v:184659.3-184744.6" + wire width 8 $0\xive13_pri$next[7:0]$14037 + attribute \src "libresoc.v:184647.3-184648.37" + wire width 8 $0\xive13_pri[7:0] + attribute \src "libresoc.v:184659.3-184744.6" + wire width 8 $0\xive14_pri$next[7:0]$14038 + attribute \src "libresoc.v:184649.3-184650.37" + wire width 8 $0\xive14_pri[7:0] + attribute \src "libresoc.v:184659.3-184744.6" + wire width 8 $0\xive15_pri$next[7:0]$14039 + attribute \src "libresoc.v:184651.3-184652.37" + wire width 8 $0\xive15_pri[7:0] + attribute \src "libresoc.v:184659.3-184744.6" + wire width 8 $0\xive1_pri$next[7:0]$14040 + attribute \src "libresoc.v:184623.3-184624.35" + wire width 8 $0\xive1_pri[7:0] + attribute \src "libresoc.v:184659.3-184744.6" + wire width 8 $0\xive2_pri$next[7:0]$14041 + attribute \src "libresoc.v:184625.3-184626.35" + wire width 8 $0\xive2_pri[7:0] + attribute \src "libresoc.v:184659.3-184744.6" + wire width 8 $0\xive3_pri$next[7:0]$14042 + attribute \src "libresoc.v:184627.3-184628.35" + wire width 8 $0\xive3_pri[7:0] + attribute \src "libresoc.v:184659.3-184744.6" + wire width 8 $0\xive4_pri$next[7:0]$14043 + attribute \src "libresoc.v:184629.3-184630.35" + wire width 8 $0\xive4_pri[7:0] + attribute \src "libresoc.v:184659.3-184744.6" + wire width 8 $0\xive5_pri$next[7:0]$14044 + attribute \src "libresoc.v:184631.3-184632.35" + wire width 8 $0\xive5_pri[7:0] + attribute \src "libresoc.v:184659.3-184744.6" + wire width 8 $0\xive6_pri$next[7:0]$14045 + attribute \src "libresoc.v:184633.3-184634.35" + wire width 8 $0\xive6_pri[7:0] + attribute \src "libresoc.v:184659.3-184744.6" + wire width 8 $0\xive7_pri$next[7:0]$14046 + attribute \src "libresoc.v:184635.3-184636.35" + wire width 8 $0\xive7_pri[7:0] + attribute \src "libresoc.v:184659.3-184744.6" + wire width 8 $0\xive8_pri$next[7:0]$14047 + attribute \src "libresoc.v:184637.3-184638.35" + wire width 8 $0\xive8_pri[7:0] + attribute \src "libresoc.v:184659.3-184744.6" + wire width 8 $0\xive9_pri$next[7:0]$14048 + attribute \src "libresoc.v:184639.3-184640.35" + wire width 8 $0\xive9_pri[7:0] + attribute \src "libresoc.v:185044.3-185093.6" + wire width 32 $1\be_out[31:0] + attribute \src "libresoc.v:184755.3-184764.6" + wire width 4 $1\cur_idx0[3:0] + attribute \src "libresoc.v:184964.3-184973.6" + wire width 4 $1\cur_idx10[3:0] + attribute \src "libresoc.v:184984.3-184993.6" + wire width 4 $1\cur_idx11[3:0] + attribute \src "libresoc.v:185004.3-185013.6" + wire width 4 $1\cur_idx12[3:0] + attribute \src "libresoc.v:185024.3-185033.6" + wire width 4 $1\cur_idx13[3:0] + attribute \src "libresoc.v:185094.3-185103.6" + wire width 4 $1\cur_idx14[3:0] + attribute \src "libresoc.v:185114.3-185123.6" + wire width 4 $1\cur_idx15[3:0] + attribute \src "libresoc.v:184775.3-184784.6" + wire width 4 $1\cur_idx1[3:0] + attribute \src "libresoc.v:184795.3-184804.6" + wire width 4 $1\cur_idx2[3:0] + attribute \src "libresoc.v:184815.3-184824.6" + wire width 4 $1\cur_idx3[3:0] + attribute \src "libresoc.v:184844.3-184853.6" + wire width 4 $1\cur_idx4[3:0] + attribute \src "libresoc.v:184864.3-184873.6" + wire width 4 $1\cur_idx5[3:0] + attribute \src "libresoc.v:184884.3-184893.6" + wire width 4 $1\cur_idx6[3:0] + attribute \src "libresoc.v:184904.3-184913.6" + wire width 4 $1\cur_idx7[3:0] + attribute \src "libresoc.v:184924.3-184933.6" + wire width 4 $1\cur_idx8[3:0] + attribute \src "libresoc.v:184944.3-184953.6" + wire width 4 $1\cur_idx9[3:0] + attribute \src "libresoc.v:184745.3-184754.6" + wire width 8 $1\cur_pri0[7:0] + attribute \src "libresoc.v:184954.3-184963.6" + wire width 8 $1\cur_pri10[7:0] + attribute \src "libresoc.v:184974.3-184983.6" + wire width 8 $1\cur_pri11[7:0] + attribute \src "libresoc.v:184994.3-185003.6" + wire width 8 $1\cur_pri12[7:0] + attribute \src "libresoc.v:185014.3-185023.6" + wire width 8 $1\cur_pri13[7:0] + attribute \src "libresoc.v:185034.3-185043.6" + wire width 8 $1\cur_pri14[7:0] + attribute \src "libresoc.v:185104.3-185113.6" + wire width 8 $1\cur_pri15[7:0] + attribute \src "libresoc.v:184765.3-184774.6" + wire width 8 $1\cur_pri1[7:0] + attribute \src "libresoc.v:184785.3-184794.6" + wire width 8 $1\cur_pri2[7:0] + attribute \src "libresoc.v:184805.3-184814.6" + wire width 8 $1\cur_pri3[7:0] + attribute \src "libresoc.v:184825.3-184834.6" + wire width 8 $1\cur_pri4[7:0] + attribute \src "libresoc.v:184854.3-184863.6" + wire width 8 $1\cur_pri5[7:0] + attribute \src "libresoc.v:184874.3-184883.6" + wire width 8 $1\cur_pri6[7:0] + attribute \src "libresoc.v:184894.3-184903.6" + wire width 8 $1\cur_pri7[7:0] + attribute \src "libresoc.v:184914.3-184923.6" + wire width 8 $1\cur_pri8[7:0] + attribute \src "libresoc.v:184934.3-184943.6" + wire width 8 $1\cur_pri9[7:0] + attribute \src "libresoc.v:185124.3-185133.6" + wire $1\ibit[0:0] + attribute \src "libresoc.v:184396.13-184396.30" + wire width 8 $1\icp_o_pri[7:0] + attribute \src "libresoc.v:184401.13-184401.29" + wire width 4 $1\icp_o_src[3:0] + attribute \src "libresoc.v:185143.3-185151.6" + wire $1\ics_wb__ack$next[0:0]$14155 + attribute \src "libresoc.v:184410.7-184410.25" + wire $1\ics_wb__ack[0:0] + attribute \src "libresoc.v:185134.3-185142.6" + wire width 32 $1\ics_wb__dat_r$next[31:0]$14152 + attribute \src "libresoc.v:184419.14-184419.35" + wire width 32 $1\ics_wb__dat_r[31:0] + attribute \src "libresoc.v:184835.3-184843.6" + wire width 16 $1\int_level_l$next[15:0]$14124 + attribute \src "libresoc.v:184431.14-184431.36" + wire width 16 $1\int_level_l[15:0] + attribute \src "libresoc.v:184659.3-184744.6" + wire width 8 $1\xive0_pri$next[7:0]$14049 + attribute \src "libresoc.v:184451.13-184451.30" + wire width 8 $1\xive0_pri[7:0] + attribute \src "libresoc.v:184659.3-184744.6" + wire width 8 $1\xive10_pri$next[7:0]$14050 + attribute \src "libresoc.v:184455.13-184455.31" + wire width 8 $1\xive10_pri[7:0] + attribute \src "libresoc.v:184659.3-184744.6" + wire width 8 $1\xive11_pri$next[7:0]$14051 + attribute \src "libresoc.v:184459.13-184459.31" + wire width 8 $1\xive11_pri[7:0] + attribute \src "libresoc.v:184659.3-184744.6" + wire width 8 $1\xive12_pri$next[7:0]$14052 + attribute \src "libresoc.v:184463.13-184463.31" + wire width 8 $1\xive12_pri[7:0] + attribute \src "libresoc.v:184659.3-184744.6" + wire width 8 $1\xive13_pri$next[7:0]$14053 + attribute \src "libresoc.v:184467.13-184467.31" + wire width 8 $1\xive13_pri[7:0] + attribute \src "libresoc.v:184659.3-184744.6" + wire width 8 $1\xive14_pri$next[7:0]$14054 + attribute \src "libresoc.v:184471.13-184471.31" + wire width 8 $1\xive14_pri[7:0] + attribute \src "libresoc.v:184659.3-184744.6" + wire width 8 $1\xive15_pri$next[7:0]$14055 + attribute \src "libresoc.v:184475.13-184475.31" + wire width 8 $1\xive15_pri[7:0] + attribute \src "libresoc.v:184659.3-184744.6" + wire width 8 $1\xive1_pri$next[7:0]$14056 + attribute \src "libresoc.v:184479.13-184479.30" + wire width 8 $1\xive1_pri[7:0] + attribute \src "libresoc.v:184659.3-184744.6" + wire width 8 $1\xive2_pri$next[7:0]$14057 + attribute \src "libresoc.v:184483.13-184483.30" + wire width 8 $1\xive2_pri[7:0] + attribute \src "libresoc.v:184659.3-184744.6" + wire width 8 $1\xive3_pri$next[7:0]$14058 + attribute \src "libresoc.v:184487.13-184487.30" + wire width 8 $1\xive3_pri[7:0] + attribute \src "libresoc.v:184659.3-184744.6" + wire width 8 $1\xive4_pri$next[7:0]$14059 + attribute \src "libresoc.v:184491.13-184491.30" + wire width 8 $1\xive4_pri[7:0] + attribute \src "libresoc.v:184659.3-184744.6" + wire width 8 $1\xive5_pri$next[7:0]$14060 + attribute \src "libresoc.v:184495.13-184495.30" + wire width 8 $1\xive5_pri[7:0] + attribute \src "libresoc.v:184659.3-184744.6" + wire width 8 $1\xive6_pri$next[7:0]$14061 + attribute \src "libresoc.v:184499.13-184499.30" + wire width 8 $1\xive6_pri[7:0] + attribute \src "libresoc.v:184659.3-184744.6" + wire width 8 $1\xive7_pri$next[7:0]$14062 + attribute \src "libresoc.v:184503.13-184503.30" + wire width 8 $1\xive7_pri[7:0] + attribute \src "libresoc.v:184659.3-184744.6" + wire width 8 $1\xive8_pri$next[7:0]$14063 + attribute \src "libresoc.v:184507.13-184507.30" + wire width 8 $1\xive8_pri[7:0] + attribute \src "libresoc.v:184659.3-184744.6" + wire width 8 $1\xive9_pri$next[7:0]$14064 + attribute \src "libresoc.v:184511.13-184511.30" + wire width 8 $1\xive9_pri[7:0] + attribute \src "libresoc.v:185044.3-185093.6" + wire width 32 $2\be_out[31:0] + attribute \src "libresoc.v:184659.3-184744.6" + wire width 8 $2\xive0_pri$next[7:0]$14065 + attribute \src "libresoc.v:184659.3-184744.6" + wire width 8 $2\xive10_pri$next[7:0]$14066 + attribute \src "libresoc.v:184659.3-184744.6" + wire width 8 $2\xive11_pri$next[7:0]$14067 + attribute \src "libresoc.v:184659.3-184744.6" + wire width 8 $2\xive12_pri$next[7:0]$14068 + attribute \src "libresoc.v:184659.3-184744.6" + wire width 8 $2\xive13_pri$next[7:0]$14069 + attribute \src "libresoc.v:184659.3-184744.6" + wire width 8 $2\xive14_pri$next[7:0]$14070 + attribute \src "libresoc.v:184659.3-184744.6" + wire width 8 $2\xive15_pri$next[7:0]$14071 + attribute \src "libresoc.v:184659.3-184744.6" + wire width 8 $2\xive1_pri$next[7:0]$14072 + attribute \src "libresoc.v:184659.3-184744.6" + wire width 8 $2\xive2_pri$next[7:0]$14073 + attribute \src "libresoc.v:184659.3-184744.6" + wire width 8 $2\xive3_pri$next[7:0]$14074 + attribute \src "libresoc.v:184659.3-184744.6" + wire width 8 $2\xive4_pri$next[7:0]$14075 + attribute \src "libresoc.v:184659.3-184744.6" + wire width 8 $2\xive5_pri$next[7:0]$14076 + attribute \src "libresoc.v:184659.3-184744.6" + wire width 8 $2\xive6_pri$next[7:0]$14077 + attribute \src "libresoc.v:184659.3-184744.6" + wire width 8 $2\xive7_pri$next[7:0]$14078 + attribute \src "libresoc.v:184659.3-184744.6" + wire width 8 $2\xive8_pri$next[7:0]$14079 + attribute \src "libresoc.v:184659.3-184744.6" + wire width 8 $2\xive9_pri$next[7:0]$14080 + attribute \src "libresoc.v:184659.3-184744.6" + wire width 8 $3\xive0_pri$next[7:0]$14081 + attribute \src "libresoc.v:184659.3-184744.6" + wire width 8 $3\xive10_pri$next[7:0]$14082 + attribute \src "libresoc.v:184659.3-184744.6" + wire width 8 $3\xive11_pri$next[7:0]$14083 + attribute \src "libresoc.v:184659.3-184744.6" + wire width 8 $3\xive12_pri$next[7:0]$14084 + attribute \src "libresoc.v:184659.3-184744.6" + wire width 8 $3\xive13_pri$next[7:0]$14085 + attribute \src "libresoc.v:184659.3-184744.6" + wire width 8 $3\xive14_pri$next[7:0]$14086 + attribute \src "libresoc.v:184659.3-184744.6" + wire width 8 $3\xive15_pri$next[7:0]$14087 + attribute \src "libresoc.v:184659.3-184744.6" + wire width 8 $3\xive1_pri$next[7:0]$14088 + attribute \src "libresoc.v:184659.3-184744.6" + wire width 8 $3\xive2_pri$next[7:0]$14089 + attribute \src "libresoc.v:184659.3-184744.6" + wire width 8 $3\xive3_pri$next[7:0]$14090 + attribute \src "libresoc.v:184659.3-184744.6" + wire width 8 $3\xive4_pri$next[7:0]$14091 + attribute \src "libresoc.v:184659.3-184744.6" + wire width 8 $3\xive5_pri$next[7:0]$14092 + attribute \src "libresoc.v:184659.3-184744.6" + wire width 8 $3\xive6_pri$next[7:0]$14093 + attribute \src "libresoc.v:184659.3-184744.6" + wire width 8 $3\xive7_pri$next[7:0]$14094 + attribute \src "libresoc.v:184659.3-184744.6" + wire width 8 $3\xive8_pri$next[7:0]$14095 + attribute \src "libresoc.v:184659.3-184744.6" + wire width 8 $3\xive9_pri$next[7:0]$14096 + attribute \src "libresoc.v:184659.3-184744.6" + wire width 8 $4\xive0_pri$next[7:0]$14097 + attribute \src "libresoc.v:184659.3-184744.6" + wire width 8 $4\xive10_pri$next[7:0]$14098 + attribute \src "libresoc.v:184659.3-184744.6" + wire width 8 $4\xive11_pri$next[7:0]$14099 + attribute \src "libresoc.v:184659.3-184744.6" + wire width 8 $4\xive12_pri$next[7:0]$14100 + attribute \src "libresoc.v:184659.3-184744.6" + wire width 8 $4\xive13_pri$next[7:0]$14101 + attribute \src "libresoc.v:184659.3-184744.6" + wire width 8 $4\xive14_pri$next[7:0]$14102 + attribute \src "libresoc.v:184659.3-184744.6" + wire width 8 $4\xive15_pri$next[7:0]$14103 + attribute \src "libresoc.v:184659.3-184744.6" + wire width 8 $4\xive1_pri$next[7:0]$14104 + attribute \src "libresoc.v:184659.3-184744.6" + wire width 8 $4\xive2_pri$next[7:0]$14105 + attribute \src "libresoc.v:184659.3-184744.6" + wire width 8 $4\xive3_pri$next[7:0]$14106 + attribute \src "libresoc.v:184659.3-184744.6" + wire width 8 $4\xive4_pri$next[7:0]$14107 + attribute \src "libresoc.v:184659.3-184744.6" + wire width 8 $4\xive5_pri$next[7:0]$14108 + attribute \src "libresoc.v:184659.3-184744.6" + wire width 8 $4\xive6_pri$next[7:0]$14109 + attribute \src "libresoc.v:184659.3-184744.6" + wire width 8 $4\xive7_pri$next[7:0]$14110 + attribute \src "libresoc.v:184659.3-184744.6" + wire width 8 $4\xive8_pri$next[7:0]$14111 + attribute \src "libresoc.v:184659.3-184744.6" + wire width 8 $4\xive9_pri$next[7:0]$14112 + attribute \src "libresoc.v:184516.19-184516.113" + wire $and$libresoc.v:184516$13910_Y + attribute \src "libresoc.v:184518.19-184518.114" + wire $and$libresoc.v:184518$13912_Y + attribute \src "libresoc.v:184520.19-184520.114" + wire $and$libresoc.v:184520$13914_Y + attribute \src "libresoc.v:184522.19-184522.114" + wire $and$libresoc.v:184522$13916_Y + attribute \src "libresoc.v:184524.19-184524.114" + wire $and$libresoc.v:184524$13918_Y + attribute \src "libresoc.v:184526.19-184526.114" + wire $and$libresoc.v:184526$13920_Y + attribute \src "libresoc.v:184528.19-184528.114" + wire $and$libresoc.v:184528$13922_Y + attribute \src "libresoc.v:184531.19-184531.114" + wire $and$libresoc.v:184531$13925_Y + attribute \src "libresoc.v:184533.19-184533.114" + wire $and$libresoc.v:184533$13927_Y + attribute \src "libresoc.v:184535.19-184535.114" + wire $and$libresoc.v:184535$13929_Y + attribute \src "libresoc.v:184538.19-184538.114" + wire $and$libresoc.v:184538$13932_Y + attribute \src "libresoc.v:184540.19-184540.114" + wire $and$libresoc.v:184540$13934_Y + attribute \src "libresoc.v:184542.19-184542.114" + wire $and$libresoc.v:184542$13936_Y + attribute \src "libresoc.v:184544.19-184544.114" + wire $and$libresoc.v:184544$13938_Y + attribute \src "libresoc.v:184546.19-184546.115" + wire $and$libresoc.v:184546$13940_Y + attribute \src "libresoc.v:184548.19-184548.115" + wire $and$libresoc.v:184548$13942_Y + attribute \src "libresoc.v:184550.19-184550.115" + wire $and$libresoc.v:184550$13944_Y + attribute \src "libresoc.v:184553.19-184553.115" + wire $and$libresoc.v:184553$13947_Y + attribute \src "libresoc.v:184555.19-184555.115" + wire $and$libresoc.v:184555$13949_Y + attribute \src "libresoc.v:184557.19-184557.115" + wire $and$libresoc.v:184557$13951_Y + attribute \src "libresoc.v:184560.19-184560.115" + wire $and$libresoc.v:184560$13954_Y + attribute \src "libresoc.v:184562.19-184562.115" + wire $and$libresoc.v:184562$13956_Y + attribute \src "libresoc.v:184564.19-184564.115" + wire $and$libresoc.v:184564$13958_Y + attribute \src "libresoc.v:184566.19-184566.115" + wire $and$libresoc.v:184566$13960_Y + attribute \src "libresoc.v:184568.19-184568.115" + wire $and$libresoc.v:184568$13962_Y + attribute \src "libresoc.v:184571.19-184571.115" + wire $and$libresoc.v:184571$13965_Y + attribute \src "libresoc.v:184595.17-184595.115" + wire $and$libresoc.v:184595$13989_Y + attribute \src "libresoc.v:184603.18-184603.112" + wire $and$libresoc.v:184603$13997_Y + attribute \src "libresoc.v:184605.18-184605.112" + wire $and$libresoc.v:184605$13999_Y + attribute \src "libresoc.v:184607.18-184607.112" + wire $and$libresoc.v:184607$14001_Y + attribute \src "libresoc.v:184609.18-184609.112" + wire $and$libresoc.v:184609$14003_Y + attribute \src "libresoc.v:184612.18-184612.112" + wire $and$libresoc.v:184612$14006_Y + attribute \src "libresoc.v:184614.18-184614.112" + wire $and$libresoc.v:184614$14008_Y + attribute \src "libresoc.v:184616.18-184616.112" + wire $and$libresoc.v:184616$14010_Y + attribute \src "libresoc.v:184530.18-184530.109" + wire $eq$libresoc.v:184530$13924_Y + attribute \src "libresoc.v:184552.18-184552.109" + wire $eq$libresoc.v:184552$13946_Y + attribute \src "libresoc.v:184569.17-184569.114" + wire $eq$libresoc.v:184569$13963_Y + attribute \src "libresoc.v:184572.19-184572.110" + wire $eq$libresoc.v:184572$13966_Y + attribute \src "libresoc.v:184574.18-184574.109" + wire $eq$libresoc.v:184574$13968_Y + attribute \src "libresoc.v:184576.18-184576.109" + wire $eq$libresoc.v:184576$13970_Y + attribute \src "libresoc.v:184578.18-184578.109" + wire $eq$libresoc.v:184578$13972_Y + attribute \src "libresoc.v:184580.18-184580.109" + wire $eq$libresoc.v:184580$13974_Y + attribute \src "libresoc.v:184582.18-184582.109" + wire $eq$libresoc.v:184582$13976_Y + attribute \src "libresoc.v:184584.17-184584.114" + wire $eq$libresoc.v:184584$13978_Y + attribute \src "libresoc.v:184585.18-184585.109" + wire $eq$libresoc.v:184585$13979_Y + attribute \src "libresoc.v:184587.18-184587.109" + wire $eq$libresoc.v:184587$13981_Y + attribute \src "libresoc.v:184589.18-184589.110" + wire $eq$libresoc.v:184589$13983_Y + attribute \src "libresoc.v:184591.18-184591.110" + wire $eq$libresoc.v:184591$13985_Y + attribute \src "libresoc.v:184593.18-184593.110" + wire $eq$libresoc.v:184593$13987_Y + attribute \src "libresoc.v:184596.18-184596.110" + wire $eq$libresoc.v:184596$13990_Y + attribute \src "libresoc.v:184598.18-184598.110" + wire $eq$libresoc.v:184598$13992_Y + attribute \src "libresoc.v:184600.18-184600.110" + wire $eq$libresoc.v:184600$13994_Y + attribute \src "libresoc.v:184611.17-184611.108" + wire $eq$libresoc.v:184611$14005_Y + attribute \src "libresoc.v:184515.18-184515.111" + wire $lt$libresoc.v:184515$13909_Y + attribute \src "libresoc.v:184517.19-184517.112" + wire $lt$libresoc.v:184517$13911_Y + attribute \src "libresoc.v:184519.19-184519.112" + wire $lt$libresoc.v:184519$13913_Y + attribute \src "libresoc.v:184521.19-184521.112" + wire $lt$libresoc.v:184521$13915_Y + attribute \src "libresoc.v:184523.19-184523.112" + wire $lt$libresoc.v:184523$13917_Y + attribute \src "libresoc.v:184525.19-184525.112" + wire $lt$libresoc.v:184525$13919_Y + attribute \src "libresoc.v:184527.19-184527.112" + wire $lt$libresoc.v:184527$13921_Y + attribute \src "libresoc.v:184529.19-184529.112" + wire $lt$libresoc.v:184529$13923_Y + attribute \src "libresoc.v:184532.19-184532.112" + wire $lt$libresoc.v:184532$13926_Y + attribute \src "libresoc.v:184534.19-184534.112" + wire $lt$libresoc.v:184534$13928_Y + attribute \src "libresoc.v:184537.19-184537.112" + wire $lt$libresoc.v:184537$13931_Y + attribute \src "libresoc.v:184539.19-184539.112" + wire $lt$libresoc.v:184539$13933_Y + attribute \src "libresoc.v:184541.19-184541.112" + wire $lt$libresoc.v:184541$13935_Y + attribute \src "libresoc.v:184543.19-184543.112" + wire $lt$libresoc.v:184543$13937_Y + attribute \src "libresoc.v:184545.19-184545.113" + wire $lt$libresoc.v:184545$13939_Y + attribute \src "libresoc.v:184547.19-184547.113" + wire $lt$libresoc.v:184547$13941_Y + attribute \src "libresoc.v:184549.19-184549.114" + wire $lt$libresoc.v:184549$13943_Y + attribute \src "libresoc.v:184551.19-184551.114" + wire $lt$libresoc.v:184551$13945_Y + attribute \src "libresoc.v:184554.19-184554.114" + wire $lt$libresoc.v:184554$13948_Y + attribute \src "libresoc.v:184556.19-184556.114" + wire $lt$libresoc.v:184556$13950_Y + attribute \src "libresoc.v:184559.19-184559.114" + wire $lt$libresoc.v:184559$13953_Y + attribute \src "libresoc.v:184561.19-184561.114" + wire $lt$libresoc.v:184561$13955_Y + attribute \src "libresoc.v:184563.19-184563.114" + wire $lt$libresoc.v:184563$13957_Y + attribute \src "libresoc.v:184565.19-184565.114" + wire $lt$libresoc.v:184565$13959_Y + attribute \src "libresoc.v:184567.19-184567.114" + wire $lt$libresoc.v:184567$13961_Y + attribute \src "libresoc.v:184570.19-184570.114" + wire $lt$libresoc.v:184570$13964_Y + attribute \src "libresoc.v:184604.18-184604.110" + wire $lt$libresoc.v:184604$13998_Y + attribute \src "libresoc.v:184606.18-184606.110" + wire $lt$libresoc.v:184606$14000_Y + attribute \src "libresoc.v:184608.18-184608.111" + wire $lt$libresoc.v:184608$14002_Y + attribute \src "libresoc.v:184610.18-184610.111" + wire $lt$libresoc.v:184610$14004_Y + attribute \src "libresoc.v:184613.18-184613.111" + wire $lt$libresoc.v:184613$14007_Y + attribute \src "libresoc.v:184615.18-184615.111" + wire $lt$libresoc.v:184615$14009_Y + attribute \src "libresoc.v:184602.18-184602.40" + wire width 16 $shr$libresoc.v:184602$13996_Y + attribute \src "libresoc.v:184514.17-184514.114" + wire width 8 $ternary$libresoc.v:184514$13908_Y + attribute \src "libresoc.v:184536.18-184536.116" + wire width 8 $ternary$libresoc.v:184536$13930_Y + attribute \src "libresoc.v:184558.18-184558.116" + wire width 8 $ternary$libresoc.v:184558$13952_Y + attribute \src "libresoc.v:184573.19-184573.118" + wire width 8 $ternary$libresoc.v:184573$13967_Y + attribute \src "libresoc.v:184575.18-184575.116" + wire width 8 $ternary$libresoc.v:184575$13969_Y + attribute \src "libresoc.v:184577.18-184577.116" + wire width 8 $ternary$libresoc.v:184577$13971_Y + attribute \src "libresoc.v:184579.18-184579.116" + wire width 8 $ternary$libresoc.v:184579$13973_Y + attribute \src "libresoc.v:184581.18-184581.116" + wire width 8 $ternary$libresoc.v:184581$13975_Y + attribute \src "libresoc.v:184583.18-184583.116" + wire width 8 $ternary$libresoc.v:184583$13977_Y + attribute \src "libresoc.v:184586.18-184586.116" + wire width 8 $ternary$libresoc.v:184586$13980_Y + attribute \src "libresoc.v:184588.18-184588.116" + wire width 8 $ternary$libresoc.v:184588$13982_Y + attribute \src "libresoc.v:184590.18-184590.117" + wire width 8 $ternary$libresoc.v:184590$13984_Y + attribute \src "libresoc.v:184592.18-184592.117" + wire width 8 $ternary$libresoc.v:184592$13986_Y + attribute \src "libresoc.v:184594.18-184594.117" + wire width 8 $ternary$libresoc.v:184594$13988_Y + attribute \src "libresoc.v:184597.18-184597.117" + wire width 8 $ternary$libresoc.v:184597$13991_Y + attribute \src "libresoc.v:184599.18-184599.117" + wire width 8 $ternary$libresoc.v:184599$13993_Y + attribute \src "libresoc.v:184601.18-184601.117" + wire width 8 $ternary$libresoc.v:184601$13995_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:293" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + wire \$101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + wire \$103 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + wire \$105 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + wire \$107 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + wire \$109 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + wire width 8 \$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + wire \$111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + wire \$113 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + wire \$115 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + wire \$117 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + wire \$119 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + wire \$121 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + wire \$123 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + wire \$125 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + wire \$127 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + wire \$129 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + wire \$131 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + wire \$133 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + wire \$135 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + wire \$137 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + wire \$139 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + wire \$141 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + wire \$143 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + wire \$145 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + wire \$147 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + wire \$149 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + wire width 8 \$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + wire \$151 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + wire \$153 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + wire \$155 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + wire \$157 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + wire \$159 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + wire \$161 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + wire \$163 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + wire \$165 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + wire \$167 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + wire \$169 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + wire \$171 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + wire \$173 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + wire \$175 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + wire \$177 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + wire \$179 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + wire \$181 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + wire \$183 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + wire \$185 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + wire \$187 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + wire \$189 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + wire width 8 \$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + wire \$191 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + wire \$193 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + wire \$195 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + wire \$197 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + wire \$199 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + wire \$201 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + wire width 8 \$203 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + wire \$204 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + wire width 8 \$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + wire width 8 \$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:294" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + wire width 8 \$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + wire \$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + wire width 8 \$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + wire \$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + wire width 8 \$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + wire \$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + wire width 8 \$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + wire \$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + wire width 8 \$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + wire \$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:304" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + wire width 8 \$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + wire \$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + wire width 8 \$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + wire \$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + wire width 8 \$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + wire \$60 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + wire width 8 \$63 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + wire \$64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + wire width 8 \$67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + wire \$68 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + wire width 8 \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:315" + wire \$71 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:341" + wire \$73 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + wire \$75 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + wire \$77 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + wire \$79 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + wire \$81 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + wire \$83 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + wire \$85 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + wire \$87 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + wire \$89 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + wire \$91 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + wire \$93 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + wire \$95 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + wire \$97 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + wire \$99 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:337" + wire width 32 \be_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:308" + wire width 32 \be_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:151" + wire input 2 \clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:365" + wire width 4 \cur_idx0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:365" + wire width 4 \cur_idx1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:365" + wire width 4 \cur_idx10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:365" + wire width 4 \cur_idx11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:365" + wire width 4 \cur_idx12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:365" + wire width 4 \cur_idx13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:365" + wire width 4 \cur_idx14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:365" + wire width 4 \cur_idx15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:365" + wire width 4 \cur_idx2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:365" + wire width 4 \cur_idx3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:365" + wire width 4 \cur_idx4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:365" + wire width 4 \cur_idx5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:365" + wire width 4 \cur_idx6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:365" + wire width 4 \cur_idx7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:365" + wire width 4 \cur_idx8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:365" + wire width 4 \cur_idx9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:366" + wire width 8 \cur_pri0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:366" + wire width 8 \cur_pri1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:366" + wire width 8 \cur_pri10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:366" + wire width 8 \cur_pri11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:366" + wire width 8 \cur_pri12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:366" + wire width 8 \cur_pri13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:366" + wire width 8 \cur_pri14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:366" + wire width 8 \cur_pri15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:366" + wire width 8 \cur_pri2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:366" + wire width 8 \cur_pri3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:366" + wire width 8 \cur_pri4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:366" + wire width 8 \cur_pri5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:366" + wire width 8 \cur_pri6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:366" + wire width 8 \cur_pri7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:366" + wire width 8 \cur_pri8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:366" + wire width 8 \cur_pri9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:314" + wire \ibit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:46" + wire width 8 output 1 \icp_o_pri + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:46" + wire width 8 \icp_o_pri$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:45" + wire width 4 output 12 \icp_o_src + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:45" + wire width 4 \icp_o_src$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:46" + wire width 8 \icp_r_pri + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:45" + wire width 4 \icp_r_src + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire output 9 \ics_wb__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire \ics_wb__ack$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire width 28 input 4 \ics_wb__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire input 6 \ics_wb__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire width 32 output 8 \ics_wb__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire width 32 \ics_wb__dat_r$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire width 32 input 10 \ics_wb__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire input 7 \ics_wb__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire input 11 \ics_wb__we + attribute \src "libresoc.v:184115.7-184115.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:237" + wire width 16 input 5 \int_level_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:263" + wire width 16 \int_level_l + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:263" + wire width 16 \int_level_l$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:358" + wire width 4 \max_idx + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:359" + wire width 8 \max_pri + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:261" + wire width 4 \reg_idx + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:287" + wire \reg_is_config + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:288" + wire \reg_is_debug + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:286" + wire \reg_is_xive + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:151" + wire input 3 \rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:260" + wire \wb_valid + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" + wire width 8 \xive0_pri + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" + wire width 8 \xive0_pri$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" + wire width 8 \xive10_pri + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" + wire width 8 \xive10_pri$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" + wire width 8 \xive11_pri + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" + wire width 8 \xive11_pri$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" + wire width 8 \xive12_pri + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" + wire width 8 \xive12_pri$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" + wire width 8 \xive13_pri + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" + wire width 8 \xive13_pri$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" + wire width 8 \xive14_pri + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" + wire width 8 \xive14_pri$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" + wire width 8 \xive15_pri + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" + wire width 8 \xive15_pri$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" + wire width 8 \xive1_pri + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" + wire width 8 \xive1_pri$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" + wire width 8 \xive2_pri + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" + wire width 8 \xive2_pri$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" + wire width 8 \xive3_pri + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" + wire width 8 \xive3_pri$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" + wire width 8 \xive4_pri + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" + wire width 8 \xive4_pri$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" + wire width 8 \xive5_pri + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" + wire width 8 \xive5_pri$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" + wire width 8 \xive6_pri + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" + wire width 8 \xive6_pri$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" + wire width 8 \xive7_pri + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" + wire width 8 \xive7_pri$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" + wire width 8 \xive8_pri + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" + wire width 8 \xive8_pri$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" + wire width 8 \xive9_pri + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" + wire width 8 \xive9_pri$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + cell $and $and$libresoc.v:184516$13910 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \int_level_l [3] + connect \B \$99 + connect \Y $and$libresoc.v:184516$13910_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + cell $and $and$libresoc.v:184518$13912 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \int_level_l [3] + connect \B \$103 + connect \Y $and$libresoc.v:184518$13912_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + cell $and $and$libresoc.v:184520$13914 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \int_level_l [4] + connect \B \$107 + connect \Y $and$libresoc.v:184520$13914_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + cell $and $and$libresoc.v:184522$13916 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \int_level_l [4] + connect \B \$111 + connect \Y $and$libresoc.v:184522$13916_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + cell $and $and$libresoc.v:184524$13918 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \int_level_l [5] + connect \B \$115 + connect \Y $and$libresoc.v:184524$13918_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + cell $and $and$libresoc.v:184526$13920 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \int_level_l [5] + connect \B \$119 + connect \Y $and$libresoc.v:184526$13920_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + cell $and $and$libresoc.v:184528$13922 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \int_level_l [6] + connect \B \$123 + connect \Y $and$libresoc.v:184528$13922_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + cell $and $and$libresoc.v:184531$13925 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \int_level_l [6] + connect \B \$127 + connect \Y $and$libresoc.v:184531$13925_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + cell $and $and$libresoc.v:184533$13927 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \int_level_l [7] + connect \B \$131 + connect \Y $and$libresoc.v:184533$13927_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + cell $and $and$libresoc.v:184535$13929 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \int_level_l [7] + connect \B \$135 + connect \Y $and$libresoc.v:184535$13929_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + cell $and $and$libresoc.v:184538$13932 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \int_level_l [8] + connect \B \$139 + connect \Y $and$libresoc.v:184538$13932_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + cell $and $and$libresoc.v:184540$13934 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \int_level_l [8] + connect \B \$143 + connect \Y $and$libresoc.v:184540$13934_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + cell $and $and$libresoc.v:184542$13936 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \int_level_l [9] + connect \B \$147 + connect \Y $and$libresoc.v:184542$13936_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + cell $and $and$libresoc.v:184544$13938 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \int_level_l [9] + connect \B \$151 + connect \Y $and$libresoc.v:184544$13938_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + cell $and $and$libresoc.v:184546$13940 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \int_level_l [10] + connect \B \$155 + connect \Y $and$libresoc.v:184546$13940_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + cell $and $and$libresoc.v:184548$13942 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \int_level_l [10] + connect \B \$159 + connect \Y $and$libresoc.v:184548$13942_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + cell $and $and$libresoc.v:184550$13944 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \int_level_l [11] + connect \B \$163 + connect \Y $and$libresoc.v:184550$13944_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + cell $and $and$libresoc.v:184553$13947 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \int_level_l [11] + connect \B \$167 + connect \Y $and$libresoc.v:184553$13947_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + cell $and $and$libresoc.v:184555$13949 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \int_level_l [12] + connect \B \$171 + connect \Y $and$libresoc.v:184555$13949_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + cell $and $and$libresoc.v:184557$13951 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \int_level_l [12] + connect \B \$175 + connect \Y $and$libresoc.v:184557$13951_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + cell $and $and$libresoc.v:184560$13954 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \int_level_l [13] + connect \B \$179 + connect \Y $and$libresoc.v:184560$13954_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + cell $and $and$libresoc.v:184562$13956 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \int_level_l [13] + connect \B \$183 + connect \Y $and$libresoc.v:184562$13956_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + cell $and $and$libresoc.v:184564$13958 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \int_level_l [14] + connect \B \$187 + connect \Y $and$libresoc.v:184564$13958_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + cell $and $and$libresoc.v:184566$13960 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \int_level_l [14] + connect \B \$191 + connect \Y $and$libresoc.v:184566$13960_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + cell $and $and$libresoc.v:184568$13962 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \int_level_l [15] + connect \B \$195 + connect \Y $and$libresoc.v:184568$13962_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + cell $and $and$libresoc.v:184571$13965 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \int_level_l [15] + connect \B \$199 + connect \Y $and$libresoc.v:184571$13965_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:304" + cell $and $and$libresoc.v:184595$13989 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ics_wb__cyc + connect \B \ics_wb__stb + connect \Y $and$libresoc.v:184595$13989_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:341" + cell $and $and$libresoc.v:184603$13997 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wb_valid + connect \B \ics_wb__we + connect \Y $and$libresoc.v:184603$13997_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + cell $and $and$libresoc.v:184605$13999 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \int_level_l [0] + connect \B \$75 + connect \Y $and$libresoc.v:184605$13999_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + cell $and $and$libresoc.v:184607$14001 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \int_level_l [0] + connect \B \$79 + connect \Y $and$libresoc.v:184607$14001_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + cell $and $and$libresoc.v:184609$14003 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \int_level_l [1] + connect \B \$83 + connect \Y $and$libresoc.v:184609$14003_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + cell $and $and$libresoc.v:184612$14006 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \int_level_l [1] + connect \B \$87 + connect \Y $and$libresoc.v:184612$14006_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + cell $and $and$libresoc.v:184614$14008 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \int_level_l [2] + connect \B \$91 + connect \Y $and$libresoc.v:184614$14008_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + cell $and $and$libresoc.v:184616$14010 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \int_level_l [2] + connect \B \$95 + connect \Y $and$libresoc.v:184616$14010_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + cell $eq $eq$libresoc.v:184530$13924 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive1_pri + connect \B 8'11111111 + connect \Y $eq$libresoc.v:184530$13924_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + cell $eq $eq$libresoc.v:184552$13946 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive2_pri + connect \B 8'11111111 + connect \Y $eq$libresoc.v:184552$13946_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:293" + cell $eq $eq$libresoc.v:184569$13963 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ics_wb__adr [9:0] + connect \B 1'0 + connect \Y $eq$libresoc.v:184569$13963_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + cell $eq $eq$libresoc.v:184572$13966 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \cur_pri15 + connect \B 8'11111111 + connect \Y $eq$libresoc.v:184572$13966_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + cell $eq $eq$libresoc.v:184574$13968 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive3_pri + connect \B 8'11111111 + connect \Y $eq$libresoc.v:184574$13968_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + cell $eq $eq$libresoc.v:184576$13970 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive4_pri + connect \B 8'11111111 + connect \Y $eq$libresoc.v:184576$13970_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + cell $eq $eq$libresoc.v:184578$13972 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive5_pri + connect \B 8'11111111 + connect \Y $eq$libresoc.v:184578$13972_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + cell $eq $eq$libresoc.v:184580$13974 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive6_pri + connect \B 8'11111111 + connect \Y $eq$libresoc.v:184580$13974_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + cell $eq $eq$libresoc.v:184582$13976 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive7_pri + connect \B 8'11111111 + connect \Y $eq$libresoc.v:184582$13976_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:294" + cell $eq $eq$libresoc.v:184584$13978 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \ics_wb__adr [9:0] + connect \B 3'100 + connect \Y $eq$libresoc.v:184584$13978_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + cell $eq $eq$libresoc.v:184585$13979 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive8_pri + connect \B 8'11111111 + connect \Y $eq$libresoc.v:184585$13979_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + cell $eq $eq$libresoc.v:184587$13981 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive9_pri + connect \B 8'11111111 + connect \Y $eq$libresoc.v:184587$13981_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + cell $eq $eq$libresoc.v:184589$13983 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive10_pri + connect \B 8'11111111 + connect \Y $eq$libresoc.v:184589$13983_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + cell $eq $eq$libresoc.v:184591$13985 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive11_pri + connect \B 8'11111111 + connect \Y $eq$libresoc.v:184591$13985_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + cell $eq $eq$libresoc.v:184593$13987 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive12_pri + connect \B 8'11111111 + connect \Y $eq$libresoc.v:184593$13987_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + cell $eq $eq$libresoc.v:184596$13990 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive13_pri + connect \B 8'11111111 + connect \Y $eq$libresoc.v:184596$13990_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + cell $eq $eq$libresoc.v:184598$13992 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive14_pri + connect \B 8'11111111 + connect \Y $eq$libresoc.v:184598$13992_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + cell $eq $eq$libresoc.v:184600$13994 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive15_pri + connect \B 8'11111111 + connect \Y $eq$libresoc.v:184600$13994_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + cell $eq $eq$libresoc.v:184611$14005 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive0_pri + connect \B 8'11111111 + connect \Y $eq$libresoc.v:184611$14005_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + cell $lt $lt$libresoc.v:184515$13909 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive3_pri + connect \B \cur_pri2 + connect \Y $lt$libresoc.v:184515$13909_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + cell $lt $lt$libresoc.v:184517$13911 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive3_pri + connect \B \cur_pri2 + connect \Y $lt$libresoc.v:184517$13911_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + cell $lt $lt$libresoc.v:184519$13913 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive4_pri + connect \B \cur_pri3 + connect \Y $lt$libresoc.v:184519$13913_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + cell $lt $lt$libresoc.v:184521$13915 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive4_pri + connect \B \cur_pri3 + connect \Y $lt$libresoc.v:184521$13915_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + cell $lt $lt$libresoc.v:184523$13917 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive5_pri + connect \B \cur_pri4 + connect \Y $lt$libresoc.v:184523$13917_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + cell $lt $lt$libresoc.v:184525$13919 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive5_pri + connect \B \cur_pri4 + connect \Y $lt$libresoc.v:184525$13919_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + cell $lt $lt$libresoc.v:184527$13921 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive6_pri + connect \B \cur_pri5 + connect \Y $lt$libresoc.v:184527$13921_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + cell $lt $lt$libresoc.v:184529$13923 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive6_pri + connect \B \cur_pri5 + connect \Y $lt$libresoc.v:184529$13923_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + cell $lt $lt$libresoc.v:184532$13926 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive7_pri + connect \B \cur_pri6 + connect \Y $lt$libresoc.v:184532$13926_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + cell $lt $lt$libresoc.v:184534$13928 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive7_pri + connect \B \cur_pri6 + connect \Y $lt$libresoc.v:184534$13928_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + cell $lt $lt$libresoc.v:184537$13931 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive8_pri + connect \B \cur_pri7 + connect \Y $lt$libresoc.v:184537$13931_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + cell $lt $lt$libresoc.v:184539$13933 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive8_pri + connect \B \cur_pri7 + connect \Y $lt$libresoc.v:184539$13933_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + cell $lt $lt$libresoc.v:184541$13935 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive9_pri + connect \B \cur_pri8 + connect \Y $lt$libresoc.v:184541$13935_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + cell $lt $lt$libresoc.v:184543$13937 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive9_pri + connect \B \cur_pri8 + connect \Y $lt$libresoc.v:184543$13937_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + cell $lt $lt$libresoc.v:184545$13939 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive10_pri + connect \B \cur_pri9 + connect \Y $lt$libresoc.v:184545$13939_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + cell $lt $lt$libresoc.v:184547$13941 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive10_pri + connect \B \cur_pri9 + connect \Y $lt$libresoc.v:184547$13941_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + cell $lt $lt$libresoc.v:184549$13943 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive11_pri + connect \B \cur_pri10 + connect \Y $lt$libresoc.v:184549$13943_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + cell $lt $lt$libresoc.v:184551$13945 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive11_pri + connect \B \cur_pri10 + connect \Y $lt$libresoc.v:184551$13945_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + cell $lt $lt$libresoc.v:184554$13948 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive12_pri + connect \B \cur_pri11 + connect \Y $lt$libresoc.v:184554$13948_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + cell $lt $lt$libresoc.v:184556$13950 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive12_pri + connect \B \cur_pri11 + connect \Y $lt$libresoc.v:184556$13950_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + cell $lt $lt$libresoc.v:184559$13953 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive13_pri + connect \B \cur_pri12 + connect \Y $lt$libresoc.v:184559$13953_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + cell $lt $lt$libresoc.v:184561$13955 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive13_pri + connect \B \cur_pri12 + connect \Y $lt$libresoc.v:184561$13955_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + cell $lt $lt$libresoc.v:184563$13957 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive14_pri + connect \B \cur_pri13 + connect \Y $lt$libresoc.v:184563$13957_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + cell $lt $lt$libresoc.v:184565$13959 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive14_pri + connect \B \cur_pri13 + connect \Y $lt$libresoc.v:184565$13959_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + cell $lt $lt$libresoc.v:184567$13961 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive15_pri + connect \B \cur_pri14 + connect \Y $lt$libresoc.v:184567$13961_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + cell $lt $lt$libresoc.v:184570$13964 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive15_pri + connect \B \cur_pri14 + connect \Y $lt$libresoc.v:184570$13964_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + cell $lt $lt$libresoc.v:184604$13998 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive0_pri + connect \B \max_pri + connect \Y $lt$libresoc.v:184604$13998_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + cell $lt $lt$libresoc.v:184606$14000 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive0_pri + connect \B \max_pri + connect \Y $lt$libresoc.v:184606$14000_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + cell $lt $lt$libresoc.v:184608$14002 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive1_pri + connect \B \cur_pri0 + connect \Y $lt$libresoc.v:184608$14002_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + cell $lt $lt$libresoc.v:184610$14004 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive1_pri + connect \B \cur_pri0 + connect \Y $lt$libresoc.v:184610$14004_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + cell $lt $lt$libresoc.v:184613$14007 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive2_pri + connect \B \cur_pri1 + connect \Y $lt$libresoc.v:184613$14007_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + cell $lt $lt$libresoc.v:184615$14009 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive2_pri + connect \B \cur_pri1 + connect \Y $lt$libresoc.v:184615$14009_Y + end + attribute \src "libresoc.v:184602.18-184602.40" + cell $shr $shr$libresoc.v:184602$13996 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 16 + connect \A \int_level_l + connect \B \reg_idx + connect \Y $shr$libresoc.v:184602$13996_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + cell $mux $ternary$libresoc.v:184514$13908 + parameter \WIDTH 8 + connect \A \xive0_pri + connect \B 8'11111111 + connect \S \$8 + connect \Y $ternary$libresoc.v:184514$13908_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + cell $mux $ternary$libresoc.v:184536$13930 + parameter \WIDTH 8 + connect \A \xive1_pri + connect \B 8'11111111 + connect \S \$12 + connect \Y $ternary$libresoc.v:184536$13930_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + cell $mux $ternary$libresoc.v:184558$13952 + parameter \WIDTH 8 + connect \A \xive2_pri + connect \B 8'11111111 + connect \S \$16 + connect \Y $ternary$libresoc.v:184558$13952_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + cell $mux $ternary$libresoc.v:184573$13967 + parameter \WIDTH 8 + connect \A \cur_pri15 + connect \B 8'11111111 + connect \S \$204 + connect \Y $ternary$libresoc.v:184573$13967_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + cell $mux $ternary$libresoc.v:184575$13969 + parameter \WIDTH 8 + connect \A \xive3_pri + connect \B 8'11111111 + connect \S \$20 + connect \Y $ternary$libresoc.v:184575$13969_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + cell $mux $ternary$libresoc.v:184577$13971 + parameter \WIDTH 8 + connect \A \xive4_pri + connect \B 8'11111111 + connect \S \$24 + connect \Y $ternary$libresoc.v:184577$13971_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + cell $mux $ternary$libresoc.v:184579$13973 + parameter \WIDTH 8 + connect \A \xive5_pri + connect \B 8'11111111 + connect \S \$28 + connect \Y $ternary$libresoc.v:184579$13973_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + cell $mux $ternary$libresoc.v:184581$13975 + parameter \WIDTH 8 + connect \A \xive6_pri + connect \B 8'11111111 + connect \S \$32 + connect \Y $ternary$libresoc.v:184581$13975_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + cell $mux $ternary$libresoc.v:184583$13977 + parameter \WIDTH 8 + connect \A \xive7_pri + connect \B 8'11111111 + connect \S \$36 + connect \Y $ternary$libresoc.v:184583$13977_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + cell $mux $ternary$libresoc.v:184586$13980 + parameter \WIDTH 8 + connect \A \xive8_pri + connect \B 8'11111111 + connect \S \$40 + connect \Y $ternary$libresoc.v:184586$13980_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + cell $mux $ternary$libresoc.v:184588$13982 + parameter \WIDTH 8 + connect \A \xive9_pri + connect \B 8'11111111 + connect \S \$44 + connect \Y $ternary$libresoc.v:184588$13982_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + cell $mux $ternary$libresoc.v:184590$13984 + parameter \WIDTH 8 + connect \A \xive10_pri + connect \B 8'11111111 + connect \S \$48 + connect \Y $ternary$libresoc.v:184590$13984_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + cell $mux $ternary$libresoc.v:184592$13986 + parameter \WIDTH 8 + connect \A \xive11_pri + connect \B 8'11111111 + connect \S \$52 + connect \Y $ternary$libresoc.v:184592$13986_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + cell $mux $ternary$libresoc.v:184594$13988 + parameter \WIDTH 8 + connect \A \xive12_pri + connect \B 8'11111111 + connect \S \$56 + connect \Y $ternary$libresoc.v:184594$13988_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + cell $mux $ternary$libresoc.v:184597$13991 + parameter \WIDTH 8 + connect \A \xive13_pri + connect \B 8'11111111 + connect \S \$60 + connect \Y $ternary$libresoc.v:184597$13991_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + cell $mux $ternary$libresoc.v:184599$13993 + parameter \WIDTH 8 + connect \A \xive14_pri + connect \B 8'11111111 + connect \S \$64 + connect \Y $ternary$libresoc.v:184599$13993_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + cell $mux $ternary$libresoc.v:184601$13995 + parameter \WIDTH 8 + connect \A \xive15_pri + connect \B 8'11111111 + connect \S \$68 + connect \Y $ternary$libresoc.v:184601$13995_Y + end + attribute \src "libresoc.v:184115.7-184115.20" + process $proc$libresoc.v:184115$14156 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:184396.13-184396.30" + process $proc$libresoc.v:184396$14157 + assign { } { } + assign $1\icp_o_pri[7:0] 8'00000000 + sync always + sync init + update \icp_o_pri $1\icp_o_pri[7:0] + end + attribute \src "libresoc.v:184401.13-184401.29" + process $proc$libresoc.v:184401$14158 + assign { } { } + assign $1\icp_o_src[3:0] 4'0000 + sync always + sync init + update \icp_o_src $1\icp_o_src[3:0] + end + attribute \src "libresoc.v:184410.7-184410.25" + process $proc$libresoc.v:184410$14159 + assign { } { } + assign $1\ics_wb__ack[0:0] 1'0 + sync always + sync init + update \ics_wb__ack $1\ics_wb__ack[0:0] + end + attribute \src "libresoc.v:184419.14-184419.35" + process $proc$libresoc.v:184419$14160 + assign { } { } + assign $1\ics_wb__dat_r[31:0] 0 + sync always + sync init + update \ics_wb__dat_r $1\ics_wb__dat_r[31:0] + end + attribute \src "libresoc.v:184431.14-184431.36" + process $proc$libresoc.v:184431$14161 + assign { } { } + assign $1\int_level_l[15:0] 16'0000000000000000 + sync always + sync init + update \int_level_l $1\int_level_l[15:0] + end + attribute \src "libresoc.v:184451.13-184451.30" + process $proc$libresoc.v:184451$14162 + assign { } { } + assign $1\xive0_pri[7:0] 8'11111111 + sync always + sync init + update \xive0_pri $1\xive0_pri[7:0] + end + attribute \src "libresoc.v:184455.13-184455.31" + process $proc$libresoc.v:184455$14163 + assign { } { } + assign $1\xive10_pri[7:0] 8'11111111 + sync always + sync init + update \xive10_pri $1\xive10_pri[7:0] + end + attribute \src "libresoc.v:184459.13-184459.31" + process $proc$libresoc.v:184459$14164 + assign { } { } + assign $1\xive11_pri[7:0] 8'11111111 + sync always + sync init + update \xive11_pri $1\xive11_pri[7:0] + end + attribute \src "libresoc.v:184463.13-184463.31" + process $proc$libresoc.v:184463$14165 + assign { } { } + assign $1\xive12_pri[7:0] 8'11111111 + sync always + sync init + update \xive12_pri $1\xive12_pri[7:0] + end + attribute \src "libresoc.v:184467.13-184467.31" + process $proc$libresoc.v:184467$14166 + assign { } { } + assign $1\xive13_pri[7:0] 8'11111111 + sync always + sync init + update \xive13_pri $1\xive13_pri[7:0] + end + attribute \src "libresoc.v:184471.13-184471.31" + process $proc$libresoc.v:184471$14167 + assign { } { } + assign $1\xive14_pri[7:0] 8'11111111 + sync always + sync init + update \xive14_pri $1\xive14_pri[7:0] + end + attribute \src "libresoc.v:184475.13-184475.31" + process $proc$libresoc.v:184475$14168 + assign { } { } + assign $1\xive15_pri[7:0] 8'11111111 + sync always + sync init + update \xive15_pri $1\xive15_pri[7:0] + end + attribute \src "libresoc.v:184479.13-184479.30" + process $proc$libresoc.v:184479$14169 + assign { } { } + assign $1\xive1_pri[7:0] 8'11111111 + sync always + sync init + update \xive1_pri $1\xive1_pri[7:0] + end + attribute \src "libresoc.v:184483.13-184483.30" + process $proc$libresoc.v:184483$14170 + assign { } { } + assign $1\xive2_pri[7:0] 8'11111111 + sync always + sync init + update \xive2_pri $1\xive2_pri[7:0] + end + attribute \src "libresoc.v:184487.13-184487.30" + process $proc$libresoc.v:184487$14171 + assign { } { } + assign $1\xive3_pri[7:0] 8'11111111 + sync always + sync init + update \xive3_pri $1\xive3_pri[7:0] + end + attribute \src "libresoc.v:184491.13-184491.30" + process $proc$libresoc.v:184491$14172 + assign { } { } + assign $1\xive4_pri[7:0] 8'11111111 + sync always + sync init + update \xive4_pri $1\xive4_pri[7:0] + end + attribute \src "libresoc.v:184495.13-184495.30" + process $proc$libresoc.v:184495$14173 + assign { } { } + assign $1\xive5_pri[7:0] 8'11111111 + sync always + sync init + update \xive5_pri $1\xive5_pri[7:0] + end + attribute \src "libresoc.v:184499.13-184499.30" + process $proc$libresoc.v:184499$14174 + assign { } { } + assign $1\xive6_pri[7:0] 8'11111111 + sync always + sync init + update \xive6_pri $1\xive6_pri[7:0] + end + attribute \src "libresoc.v:184503.13-184503.30" + process $proc$libresoc.v:184503$14175 + assign { } { } + assign $1\xive7_pri[7:0] 8'11111111 + sync always + sync init + update \xive7_pri $1\xive7_pri[7:0] + end + attribute \src "libresoc.v:184507.13-184507.30" + process $proc$libresoc.v:184507$14176 + assign { } { } + assign $1\xive8_pri[7:0] 8'11111111 + sync always + sync init + update \xive8_pri $1\xive8_pri[7:0] + end + attribute \src "libresoc.v:184511.13-184511.30" + process $proc$libresoc.v:184511$14177 + assign { } { } + assign $1\xive9_pri[7:0] 8'11111111 + sync always + sync init + update \xive9_pri $1\xive9_pri[7:0] + end + attribute \src "libresoc.v:184617.3-184618.28" + process $proc$libresoc.v:184617$14011 + assign { } { } + assign $0\icp_o_src[3:0] \cur_idx15 + sync posedge \clk + update \icp_o_src $0\icp_o_src[3:0] + end + attribute \src "libresoc.v:184619.3-184620.25" + process $proc$libresoc.v:184619$14012 + assign { } { } + assign $0\icp_o_pri[7:0] \$203 + sync posedge \clk + update \icp_o_pri $0\icp_o_pri[7:0] + end + attribute \src "libresoc.v:184621.3-184622.35" + process $proc$libresoc.v:184621$14013 + assign { } { } + assign $0\xive0_pri[7:0] \xive0_pri$next + sync posedge \clk + update \xive0_pri $0\xive0_pri[7:0] + end + attribute \src "libresoc.v:184623.3-184624.35" + process $proc$libresoc.v:184623$14014 + assign { } { } + assign $0\xive1_pri[7:0] \xive1_pri$next + sync posedge \clk + update \xive1_pri $0\xive1_pri[7:0] + end + attribute \src "libresoc.v:184625.3-184626.35" + process $proc$libresoc.v:184625$14015 + assign { } { } + assign $0\xive2_pri[7:0] \xive2_pri$next + sync posedge \clk + update \xive2_pri $0\xive2_pri[7:0] + end + attribute \src "libresoc.v:184627.3-184628.35" + process $proc$libresoc.v:184627$14016 + assign { } { } + assign $0\xive3_pri[7:0] \xive3_pri$next + sync posedge \clk + update \xive3_pri $0\xive3_pri[7:0] + end + attribute \src "libresoc.v:184629.3-184630.35" + process $proc$libresoc.v:184629$14017 + assign { } { } + assign $0\xive4_pri[7:0] \xive4_pri$next + sync posedge \clk + update \xive4_pri $0\xive4_pri[7:0] + end + attribute \src "libresoc.v:184631.3-184632.35" + process $proc$libresoc.v:184631$14018 + assign { } { } + assign $0\xive5_pri[7:0] \xive5_pri$next + sync posedge \clk + update \xive5_pri $0\xive5_pri[7:0] + end + attribute \src "libresoc.v:184633.3-184634.35" + process $proc$libresoc.v:184633$14019 + assign { } { } + assign $0\xive6_pri[7:0] \xive6_pri$next + sync posedge \clk + update \xive6_pri $0\xive6_pri[7:0] + end + attribute \src "libresoc.v:184635.3-184636.35" + process $proc$libresoc.v:184635$14020 + assign { } { } + assign $0\xive7_pri[7:0] \xive7_pri$next + sync posedge \clk + update \xive7_pri $0\xive7_pri[7:0] + end + attribute \src "libresoc.v:184637.3-184638.35" + process $proc$libresoc.v:184637$14021 + assign { } { } + assign $0\xive8_pri[7:0] \xive8_pri$next + sync posedge \clk + update \xive8_pri $0\xive8_pri[7:0] + end + attribute \src "libresoc.v:184639.3-184640.35" + process $proc$libresoc.v:184639$14022 + assign { } { } + assign $0\xive9_pri[7:0] \xive9_pri$next + sync posedge \clk + update \xive9_pri $0\xive9_pri[7:0] + end + attribute \src "libresoc.v:184641.3-184642.37" + process $proc$libresoc.v:184641$14023 + assign { } { } + assign $0\xive10_pri[7:0] \xive10_pri$next + sync posedge \clk + update \xive10_pri $0\xive10_pri[7:0] + end + attribute \src "libresoc.v:184643.3-184644.37" + process $proc$libresoc.v:184643$14024 + assign { } { } + assign $0\xive11_pri[7:0] \xive11_pri$next + sync posedge \clk + update \xive11_pri $0\xive11_pri[7:0] + end + attribute \src "libresoc.v:184645.3-184646.37" + process $proc$libresoc.v:184645$14025 + assign { } { } + assign $0\xive12_pri[7:0] \xive12_pri$next + sync posedge \clk + update \xive12_pri $0\xive12_pri[7:0] + end + attribute \src "libresoc.v:184647.3-184648.37" + process $proc$libresoc.v:184647$14026 + assign { } { } + assign $0\xive13_pri[7:0] \xive13_pri$next + sync posedge \clk + update \xive13_pri $0\xive13_pri[7:0] + end + attribute \src "libresoc.v:184649.3-184650.37" + process $proc$libresoc.v:184649$14027 + assign { } { } + assign $0\xive14_pri[7:0] \xive14_pri$next + sync posedge \clk + update \xive14_pri $0\xive14_pri[7:0] + end + attribute \src "libresoc.v:184651.3-184652.37" + process $proc$libresoc.v:184651$14028 + assign { } { } + assign $0\xive15_pri[7:0] \xive15_pri$next + sync posedge \clk + update \xive15_pri $0\xive15_pri[7:0] + end + attribute \src "libresoc.v:184653.3-184654.39" + process $proc$libresoc.v:184653$14029 + assign { } { } + assign $0\ics_wb__ack[0:0] \ics_wb__ack$next + sync posedge \clk + update \ics_wb__ack $0\ics_wb__ack[0:0] + end + attribute \src "libresoc.v:184655.3-184656.43" + process $proc$libresoc.v:184655$14030 + assign { } { } + assign $0\ics_wb__dat_r[31:0] \ics_wb__dat_r$next + sync posedge \clk + update \ics_wb__dat_r $0\ics_wb__dat_r[31:0] + end + attribute \src "libresoc.v:184657.3-184658.39" + process $proc$libresoc.v:184657$14031 + assign { } { } + assign $0\int_level_l[15:0] \int_level_l$next + sync posedge \clk + update \int_level_l $0\int_level_l[15:0] + end + attribute \src "libresoc.v:184659.3-184744.6" + process $proc$libresoc.v:184659$14032 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\xive0_pri$next[7:0]$14033 $4\xive0_pri$next[7:0]$14097 + assign $0\xive10_pri$next[7:0]$14034 $4\xive10_pri$next[7:0]$14098 + assign $0\xive11_pri$next[7:0]$14035 $4\xive11_pri$next[7:0]$14099 + assign $0\xive12_pri$next[7:0]$14036 $4\xive12_pri$next[7:0]$14100 + assign $0\xive13_pri$next[7:0]$14037 $4\xive13_pri$next[7:0]$14101 + assign $0\xive14_pri$next[7:0]$14038 $4\xive14_pri$next[7:0]$14102 + assign $0\xive15_pri$next[7:0]$14039 $4\xive15_pri$next[7:0]$14103 + assign $0\xive1_pri$next[7:0]$14040 $4\xive1_pri$next[7:0]$14104 + assign $0\xive2_pri$next[7:0]$14041 $4\xive2_pri$next[7:0]$14105 + assign $0\xive3_pri$next[7:0]$14042 $4\xive3_pri$next[7:0]$14106 + assign $0\xive4_pri$next[7:0]$14043 $4\xive4_pri$next[7:0]$14107 + assign $0\xive5_pri$next[7:0]$14044 $4\xive5_pri$next[7:0]$14108 + assign $0\xive6_pri$next[7:0]$14045 $4\xive6_pri$next[7:0]$14109 + assign $0\xive7_pri$next[7:0]$14046 $4\xive7_pri$next[7:0]$14110 + assign $0\xive8_pri$next[7:0]$14047 $4\xive8_pri$next[7:0]$14111 + assign $0\xive9_pri$next[7:0]$14048 $4\xive9_pri$next[7:0]$14112 + attribute \src "libresoc.v:184660.5-184660.29" + switch \initial + attribute \src "libresoc.v:184660.9-184660.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:341" + switch \$73 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\xive0_pri$next[7:0]$14049 $2\xive0_pri$next[7:0]$14065 + assign $1\xive10_pri$next[7:0]$14050 $2\xive10_pri$next[7:0]$14066 + assign $1\xive11_pri$next[7:0]$14051 $2\xive11_pri$next[7:0]$14067 + assign $1\xive12_pri$next[7:0]$14052 $2\xive12_pri$next[7:0]$14068 + assign $1\xive13_pri$next[7:0]$14053 $2\xive13_pri$next[7:0]$14069 + assign $1\xive14_pri$next[7:0]$14054 $2\xive14_pri$next[7:0]$14070 + assign $1\xive15_pri$next[7:0]$14055 $2\xive15_pri$next[7:0]$14071 + assign $1\xive1_pri$next[7:0]$14056 $2\xive1_pri$next[7:0]$14072 + assign $1\xive2_pri$next[7:0]$14057 $2\xive2_pri$next[7:0]$14073 + assign $1\xive3_pri$next[7:0]$14058 $2\xive3_pri$next[7:0]$14074 + assign $1\xive4_pri$next[7:0]$14059 $2\xive4_pri$next[7:0]$14075 + assign $1\xive5_pri$next[7:0]$14060 $2\xive5_pri$next[7:0]$14076 + assign $1\xive6_pri$next[7:0]$14061 $2\xive6_pri$next[7:0]$14077 + assign $1\xive7_pri$next[7:0]$14062 $2\xive7_pri$next[7:0]$14078 + assign $1\xive8_pri$next[7:0]$14063 $2\xive8_pri$next[7:0]$14079 + assign $1\xive9_pri$next[7:0]$14064 $2\xive9_pri$next[7:0]$14080 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:342" + switch \reg_is_xive + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $2\xive0_pri$next[7:0]$14065 $3\xive0_pri$next[7:0]$14081 + assign $2\xive10_pri$next[7:0]$14066 $3\xive10_pri$next[7:0]$14082 + assign $2\xive11_pri$next[7:0]$14067 $3\xive11_pri$next[7:0]$14083 + assign $2\xive12_pri$next[7:0]$14068 $3\xive12_pri$next[7:0]$14084 + assign $2\xive13_pri$next[7:0]$14069 $3\xive13_pri$next[7:0]$14085 + assign $2\xive14_pri$next[7:0]$14070 $3\xive14_pri$next[7:0]$14086 + assign $2\xive15_pri$next[7:0]$14071 $3\xive15_pri$next[7:0]$14087 + assign $2\xive1_pri$next[7:0]$14072 $3\xive1_pri$next[7:0]$14088 + assign $2\xive2_pri$next[7:0]$14073 $3\xive2_pri$next[7:0]$14089 + assign $2\xive3_pri$next[7:0]$14074 $3\xive3_pri$next[7:0]$14090 + assign $2\xive4_pri$next[7:0]$14075 $3\xive4_pri$next[7:0]$14091 + assign $2\xive5_pri$next[7:0]$14076 $3\xive5_pri$next[7:0]$14092 + assign $2\xive6_pri$next[7:0]$14077 $3\xive6_pri$next[7:0]$14093 + assign $2\xive7_pri$next[7:0]$14078 $3\xive7_pri$next[7:0]$14094 + assign $2\xive8_pri$next[7:0]$14079 $3\xive8_pri$next[7:0]$14095 + assign $2\xive9_pri$next[7:0]$14080 $3\xive9_pri$next[7:0]$14096 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:345" + switch \reg_idx + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $3\xive10_pri$next[7:0]$14082 \xive10_pri + assign $3\xive11_pri$next[7:0]$14083 \xive11_pri + assign $3\xive12_pri$next[7:0]$14084 \xive12_pri + assign $3\xive13_pri$next[7:0]$14085 \xive13_pri + assign $3\xive14_pri$next[7:0]$14086 \xive14_pri + assign $3\xive15_pri$next[7:0]$14087 \xive15_pri + assign $3\xive1_pri$next[7:0]$14088 \xive1_pri + assign $3\xive2_pri$next[7:0]$14089 \xive2_pri + assign $3\xive3_pri$next[7:0]$14090 \xive3_pri + assign $3\xive4_pri$next[7:0]$14091 \xive4_pri + assign $3\xive5_pri$next[7:0]$14092 \xive5_pri + assign $3\xive6_pri$next[7:0]$14093 \xive6_pri + assign $3\xive7_pri$next[7:0]$14094 \xive7_pri + assign $3\xive8_pri$next[7:0]$14095 \xive8_pri + assign $3\xive9_pri$next[7:0]$14096 \xive9_pri + assign $3\xive0_pri$next[7:0]$14081 \be_in [7:0] + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign $3\xive0_pri$next[7:0]$14081 \xive0_pri + assign $3\xive10_pri$next[7:0]$14082 \xive10_pri + assign $3\xive11_pri$next[7:0]$14083 \xive11_pri + assign $3\xive12_pri$next[7:0]$14084 \xive12_pri + assign $3\xive13_pri$next[7:0]$14085 \xive13_pri + assign $3\xive14_pri$next[7:0]$14086 \xive14_pri + assign $3\xive15_pri$next[7:0]$14087 \xive15_pri + assign { } { } + assign $3\xive2_pri$next[7:0]$14089 \xive2_pri + assign $3\xive3_pri$next[7:0]$14090 \xive3_pri + assign $3\xive4_pri$next[7:0]$14091 \xive4_pri + assign $3\xive5_pri$next[7:0]$14092 \xive5_pri + assign $3\xive6_pri$next[7:0]$14093 \xive6_pri + assign $3\xive7_pri$next[7:0]$14094 \xive7_pri + assign $3\xive8_pri$next[7:0]$14095 \xive8_pri + assign $3\xive9_pri$next[7:0]$14096 \xive9_pri + assign $3\xive1_pri$next[7:0]$14088 \be_in [7:0] + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign $3\xive0_pri$next[7:0]$14081 \xive0_pri + assign $3\xive10_pri$next[7:0]$14082 \xive10_pri + assign $3\xive11_pri$next[7:0]$14083 \xive11_pri + assign $3\xive12_pri$next[7:0]$14084 \xive12_pri + assign $3\xive13_pri$next[7:0]$14085 \xive13_pri + assign $3\xive14_pri$next[7:0]$14086 \xive14_pri + assign $3\xive15_pri$next[7:0]$14087 \xive15_pri + assign $3\xive1_pri$next[7:0]$14088 \xive1_pri + assign { } { } + assign $3\xive3_pri$next[7:0]$14090 \xive3_pri + assign $3\xive4_pri$next[7:0]$14091 \xive4_pri + assign $3\xive5_pri$next[7:0]$14092 \xive5_pri + assign $3\xive6_pri$next[7:0]$14093 \xive6_pri + assign $3\xive7_pri$next[7:0]$14094 \xive7_pri + assign $3\xive8_pri$next[7:0]$14095 \xive8_pri + assign $3\xive9_pri$next[7:0]$14096 \xive9_pri + assign $3\xive2_pri$next[7:0]$14089 \be_in [7:0] + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign $3\xive0_pri$next[7:0]$14081 \xive0_pri + assign $3\xive10_pri$next[7:0]$14082 \xive10_pri + assign $3\xive11_pri$next[7:0]$14083 \xive11_pri + assign $3\xive12_pri$next[7:0]$14084 \xive12_pri + assign $3\xive13_pri$next[7:0]$14085 \xive13_pri + assign $3\xive14_pri$next[7:0]$14086 \xive14_pri + assign $3\xive15_pri$next[7:0]$14087 \xive15_pri + assign $3\xive1_pri$next[7:0]$14088 \xive1_pri + assign $3\xive2_pri$next[7:0]$14089 \xive2_pri + assign { } { } + assign $3\xive4_pri$next[7:0]$14091 \xive4_pri + assign $3\xive5_pri$next[7:0]$14092 \xive5_pri + assign $3\xive6_pri$next[7:0]$14093 \xive6_pri + assign $3\xive7_pri$next[7:0]$14094 \xive7_pri + assign $3\xive8_pri$next[7:0]$14095 \xive8_pri + assign $3\xive9_pri$next[7:0]$14096 \xive9_pri + assign $3\xive3_pri$next[7:0]$14090 \be_in [7:0] + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign $3\xive0_pri$next[7:0]$14081 \xive0_pri + assign $3\xive10_pri$next[7:0]$14082 \xive10_pri + assign $3\xive11_pri$next[7:0]$14083 \xive11_pri + assign $3\xive12_pri$next[7:0]$14084 \xive12_pri + assign $3\xive13_pri$next[7:0]$14085 \xive13_pri + assign $3\xive14_pri$next[7:0]$14086 \xive14_pri + assign $3\xive15_pri$next[7:0]$14087 \xive15_pri + assign $3\xive1_pri$next[7:0]$14088 \xive1_pri + assign $3\xive2_pri$next[7:0]$14089 \xive2_pri + assign $3\xive3_pri$next[7:0]$14090 \xive3_pri + assign { } { } + assign $3\xive5_pri$next[7:0]$14092 \xive5_pri + assign $3\xive6_pri$next[7:0]$14093 \xive6_pri + assign $3\xive7_pri$next[7:0]$14094 \xive7_pri + assign $3\xive8_pri$next[7:0]$14095 \xive8_pri + assign $3\xive9_pri$next[7:0]$14096 \xive9_pri + assign $3\xive4_pri$next[7:0]$14091 \be_in [7:0] + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign $3\xive0_pri$next[7:0]$14081 \xive0_pri + assign $3\xive10_pri$next[7:0]$14082 \xive10_pri + assign $3\xive11_pri$next[7:0]$14083 \xive11_pri + assign $3\xive12_pri$next[7:0]$14084 \xive12_pri + assign $3\xive13_pri$next[7:0]$14085 \xive13_pri + assign $3\xive14_pri$next[7:0]$14086 \xive14_pri + assign $3\xive15_pri$next[7:0]$14087 \xive15_pri + assign $3\xive1_pri$next[7:0]$14088 \xive1_pri + assign $3\xive2_pri$next[7:0]$14089 \xive2_pri + assign $3\xive3_pri$next[7:0]$14090 \xive3_pri + assign $3\xive4_pri$next[7:0]$14091 \xive4_pri + assign { } { } + assign $3\xive6_pri$next[7:0]$14093 \xive6_pri + assign $3\xive7_pri$next[7:0]$14094 \xive7_pri + assign $3\xive8_pri$next[7:0]$14095 \xive8_pri + assign $3\xive9_pri$next[7:0]$14096 \xive9_pri + assign $3\xive5_pri$next[7:0]$14092 \be_in [7:0] + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign $3\xive0_pri$next[7:0]$14081 \xive0_pri + assign $3\xive10_pri$next[7:0]$14082 \xive10_pri + assign $3\xive11_pri$next[7:0]$14083 \xive11_pri + assign $3\xive12_pri$next[7:0]$14084 \xive12_pri + assign $3\xive13_pri$next[7:0]$14085 \xive13_pri + assign $3\xive14_pri$next[7:0]$14086 \xive14_pri + assign $3\xive15_pri$next[7:0]$14087 \xive15_pri + assign $3\xive1_pri$next[7:0]$14088 \xive1_pri + assign $3\xive2_pri$next[7:0]$14089 \xive2_pri + assign $3\xive3_pri$next[7:0]$14090 \xive3_pri + assign $3\xive4_pri$next[7:0]$14091 \xive4_pri + assign $3\xive5_pri$next[7:0]$14092 \xive5_pri + assign { } { } + assign $3\xive7_pri$next[7:0]$14094 \xive7_pri + assign $3\xive8_pri$next[7:0]$14095 \xive8_pri + assign $3\xive9_pri$next[7:0]$14096 \xive9_pri + assign $3\xive6_pri$next[7:0]$14093 \be_in [7:0] + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign $3\xive0_pri$next[7:0]$14081 \xive0_pri + assign $3\xive10_pri$next[7:0]$14082 \xive10_pri + assign $3\xive11_pri$next[7:0]$14083 \xive11_pri + assign $3\xive12_pri$next[7:0]$14084 \xive12_pri + assign $3\xive13_pri$next[7:0]$14085 \xive13_pri + assign $3\xive14_pri$next[7:0]$14086 \xive14_pri + assign $3\xive15_pri$next[7:0]$14087 \xive15_pri + assign $3\xive1_pri$next[7:0]$14088 \xive1_pri + assign $3\xive2_pri$next[7:0]$14089 \xive2_pri + assign $3\xive3_pri$next[7:0]$14090 \xive3_pri + assign $3\xive4_pri$next[7:0]$14091 \xive4_pri + assign $3\xive5_pri$next[7:0]$14092 \xive5_pri + assign $3\xive6_pri$next[7:0]$14093 \xive6_pri + assign { } { } + assign $3\xive8_pri$next[7:0]$14095 \xive8_pri + assign $3\xive9_pri$next[7:0]$14096 \xive9_pri + assign $3\xive7_pri$next[7:0]$14094 \be_in [7:0] + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign $3\xive0_pri$next[7:0]$14081 \xive0_pri + assign $3\xive10_pri$next[7:0]$14082 \xive10_pri + assign $3\xive11_pri$next[7:0]$14083 \xive11_pri + assign $3\xive12_pri$next[7:0]$14084 \xive12_pri + assign $3\xive13_pri$next[7:0]$14085 \xive13_pri + assign $3\xive14_pri$next[7:0]$14086 \xive14_pri + assign $3\xive15_pri$next[7:0]$14087 \xive15_pri + assign $3\xive1_pri$next[7:0]$14088 \xive1_pri + assign $3\xive2_pri$next[7:0]$14089 \xive2_pri + assign $3\xive3_pri$next[7:0]$14090 \xive3_pri + assign $3\xive4_pri$next[7:0]$14091 \xive4_pri + assign $3\xive5_pri$next[7:0]$14092 \xive5_pri + assign $3\xive6_pri$next[7:0]$14093 \xive6_pri + assign $3\xive7_pri$next[7:0]$14094 \xive7_pri + assign { } { } + assign $3\xive9_pri$next[7:0]$14096 \xive9_pri + assign $3\xive8_pri$next[7:0]$14095 \be_in [7:0] + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign $3\xive0_pri$next[7:0]$14081 \xive0_pri + assign $3\xive10_pri$next[7:0]$14082 \xive10_pri + assign $3\xive11_pri$next[7:0]$14083 \xive11_pri + assign $3\xive12_pri$next[7:0]$14084 \xive12_pri + assign $3\xive13_pri$next[7:0]$14085 \xive13_pri + assign $3\xive14_pri$next[7:0]$14086 \xive14_pri + assign $3\xive15_pri$next[7:0]$14087 \xive15_pri + assign $3\xive1_pri$next[7:0]$14088 \xive1_pri + assign $3\xive2_pri$next[7:0]$14089 \xive2_pri + assign $3\xive3_pri$next[7:0]$14090 \xive3_pri + assign $3\xive4_pri$next[7:0]$14091 \xive4_pri + assign $3\xive5_pri$next[7:0]$14092 \xive5_pri + assign $3\xive6_pri$next[7:0]$14093 \xive6_pri + assign $3\xive7_pri$next[7:0]$14094 \xive7_pri + assign $3\xive8_pri$next[7:0]$14095 \xive8_pri + assign { } { } + assign $3\xive9_pri$next[7:0]$14096 \be_in [7:0] + attribute \src "libresoc.v:0.0-0.0" + case 4'1010 + assign $3\xive0_pri$next[7:0]$14081 \xive0_pri + assign { } { } + assign $3\xive11_pri$next[7:0]$14083 \xive11_pri + assign $3\xive12_pri$next[7:0]$14084 \xive12_pri + assign $3\xive13_pri$next[7:0]$14085 \xive13_pri + assign $3\xive14_pri$next[7:0]$14086 \xive14_pri + assign $3\xive15_pri$next[7:0]$14087 \xive15_pri + assign $3\xive1_pri$next[7:0]$14088 \xive1_pri + assign $3\xive2_pri$next[7:0]$14089 \xive2_pri + assign $3\xive3_pri$next[7:0]$14090 \xive3_pri + assign $3\xive4_pri$next[7:0]$14091 \xive4_pri + assign $3\xive5_pri$next[7:0]$14092 \xive5_pri + assign $3\xive6_pri$next[7:0]$14093 \xive6_pri + assign $3\xive7_pri$next[7:0]$14094 \xive7_pri + assign $3\xive8_pri$next[7:0]$14095 \xive8_pri + assign $3\xive9_pri$next[7:0]$14096 \xive9_pri + assign $3\xive10_pri$next[7:0]$14082 \be_in [7:0] + attribute \src "libresoc.v:0.0-0.0" + case 4'1011 + assign $3\xive0_pri$next[7:0]$14081 \xive0_pri + assign $3\xive10_pri$next[7:0]$14082 \xive10_pri + assign { } { } + assign $3\xive12_pri$next[7:0]$14084 \xive12_pri + assign $3\xive13_pri$next[7:0]$14085 \xive13_pri + assign $3\xive14_pri$next[7:0]$14086 \xive14_pri + assign $3\xive15_pri$next[7:0]$14087 \xive15_pri + assign $3\xive1_pri$next[7:0]$14088 \xive1_pri + assign $3\xive2_pri$next[7:0]$14089 \xive2_pri + assign $3\xive3_pri$next[7:0]$14090 \xive3_pri + assign $3\xive4_pri$next[7:0]$14091 \xive4_pri + assign $3\xive5_pri$next[7:0]$14092 \xive5_pri + assign $3\xive6_pri$next[7:0]$14093 \xive6_pri + assign $3\xive7_pri$next[7:0]$14094 \xive7_pri + assign $3\xive8_pri$next[7:0]$14095 \xive8_pri + assign $3\xive9_pri$next[7:0]$14096 \xive9_pri + assign $3\xive11_pri$next[7:0]$14083 \be_in [7:0] + attribute \src "libresoc.v:0.0-0.0" + case 4'1100 + assign $3\xive0_pri$next[7:0]$14081 \xive0_pri + assign $3\xive10_pri$next[7:0]$14082 \xive10_pri + assign $3\xive11_pri$next[7:0]$14083 \xive11_pri + assign { } { } + assign $3\xive13_pri$next[7:0]$14085 \xive13_pri + assign $3\xive14_pri$next[7:0]$14086 \xive14_pri + assign $3\xive15_pri$next[7:0]$14087 \xive15_pri + assign $3\xive1_pri$next[7:0]$14088 \xive1_pri + assign $3\xive2_pri$next[7:0]$14089 \xive2_pri + assign $3\xive3_pri$next[7:0]$14090 \xive3_pri + assign $3\xive4_pri$next[7:0]$14091 \xive4_pri + assign $3\xive5_pri$next[7:0]$14092 \xive5_pri + assign $3\xive6_pri$next[7:0]$14093 \xive6_pri + assign $3\xive7_pri$next[7:0]$14094 \xive7_pri + assign $3\xive8_pri$next[7:0]$14095 \xive8_pri + assign $3\xive9_pri$next[7:0]$14096 \xive9_pri + assign $3\xive12_pri$next[7:0]$14084 \be_in [7:0] + attribute \src "libresoc.v:0.0-0.0" + case 4'1101 + assign $3\xive0_pri$next[7:0]$14081 \xive0_pri + assign $3\xive10_pri$next[7:0]$14082 \xive10_pri + assign $3\xive11_pri$next[7:0]$14083 \xive11_pri + assign $3\xive12_pri$next[7:0]$14084 \xive12_pri + assign { } { } + assign $3\xive14_pri$next[7:0]$14086 \xive14_pri + assign $3\xive15_pri$next[7:0]$14087 \xive15_pri + assign $3\xive1_pri$next[7:0]$14088 \xive1_pri + assign $3\xive2_pri$next[7:0]$14089 \xive2_pri + assign $3\xive3_pri$next[7:0]$14090 \xive3_pri + assign $3\xive4_pri$next[7:0]$14091 \xive4_pri + assign $3\xive5_pri$next[7:0]$14092 \xive5_pri + assign $3\xive6_pri$next[7:0]$14093 \xive6_pri + assign $3\xive7_pri$next[7:0]$14094 \xive7_pri + assign $3\xive8_pri$next[7:0]$14095 \xive8_pri + assign $3\xive9_pri$next[7:0]$14096 \xive9_pri + assign $3\xive13_pri$next[7:0]$14085 \be_in [7:0] + attribute \src "libresoc.v:0.0-0.0" + case 4'1110 + assign $3\xive0_pri$next[7:0]$14081 \xive0_pri + assign $3\xive10_pri$next[7:0]$14082 \xive10_pri + assign $3\xive11_pri$next[7:0]$14083 \xive11_pri + assign $3\xive12_pri$next[7:0]$14084 \xive12_pri + assign $3\xive13_pri$next[7:0]$14085 \xive13_pri + assign { } { } + assign $3\xive15_pri$next[7:0]$14087 \xive15_pri + assign $3\xive1_pri$next[7:0]$14088 \xive1_pri + assign $3\xive2_pri$next[7:0]$14089 \xive2_pri + assign $3\xive3_pri$next[7:0]$14090 \xive3_pri + assign $3\xive4_pri$next[7:0]$14091 \xive4_pri + assign $3\xive5_pri$next[7:0]$14092 \xive5_pri + assign $3\xive6_pri$next[7:0]$14093 \xive6_pri + assign $3\xive7_pri$next[7:0]$14094 \xive7_pri + assign $3\xive8_pri$next[7:0]$14095 \xive8_pri + assign $3\xive9_pri$next[7:0]$14096 \xive9_pri + assign $3\xive14_pri$next[7:0]$14086 \be_in [7:0] + attribute \src "libresoc.v:0.0-0.0" + case 4'---- + assign $3\xive0_pri$next[7:0]$14081 \xive0_pri + assign $3\xive10_pri$next[7:0]$14082 \xive10_pri + assign $3\xive11_pri$next[7:0]$14083 \xive11_pri + assign $3\xive12_pri$next[7:0]$14084 \xive12_pri + assign $3\xive13_pri$next[7:0]$14085 \xive13_pri + assign $3\xive14_pri$next[7:0]$14086 \xive14_pri + assign { } { } + assign $3\xive1_pri$next[7:0]$14088 \xive1_pri + assign $3\xive2_pri$next[7:0]$14089 \xive2_pri + assign $3\xive3_pri$next[7:0]$14090 \xive3_pri + assign $3\xive4_pri$next[7:0]$14091 \xive4_pri + assign $3\xive5_pri$next[7:0]$14092 \xive5_pri + assign $3\xive6_pri$next[7:0]$14093 \xive6_pri + assign $3\xive7_pri$next[7:0]$14094 \xive7_pri + assign $3\xive8_pri$next[7:0]$14095 \xive8_pri + assign $3\xive9_pri$next[7:0]$14096 \xive9_pri + assign $3\xive15_pri$next[7:0]$14087 \be_in [7:0] + case + assign $3\xive0_pri$next[7:0]$14081 \xive0_pri + assign $3\xive10_pri$next[7:0]$14082 \xive10_pri + assign $3\xive11_pri$next[7:0]$14083 \xive11_pri + assign $3\xive12_pri$next[7:0]$14084 \xive12_pri + assign $3\xive13_pri$next[7:0]$14085 \xive13_pri + assign $3\xive14_pri$next[7:0]$14086 \xive14_pri + assign $3\xive15_pri$next[7:0]$14087 \xive15_pri + assign $3\xive1_pri$next[7:0]$14088 \xive1_pri + assign $3\xive2_pri$next[7:0]$14089 \xive2_pri + assign $3\xive3_pri$next[7:0]$14090 \xive3_pri + assign $3\xive4_pri$next[7:0]$14091 \xive4_pri + assign $3\xive5_pri$next[7:0]$14092 \xive5_pri + assign $3\xive6_pri$next[7:0]$14093 \xive6_pri + assign $3\xive7_pri$next[7:0]$14094 \xive7_pri + assign $3\xive8_pri$next[7:0]$14095 \xive8_pri + assign $3\xive9_pri$next[7:0]$14096 \xive9_pri + end + case + assign $2\xive0_pri$next[7:0]$14065 \xive0_pri + assign $2\xive10_pri$next[7:0]$14066 \xive10_pri + assign $2\xive11_pri$next[7:0]$14067 \xive11_pri + assign $2\xive12_pri$next[7:0]$14068 \xive12_pri + assign $2\xive13_pri$next[7:0]$14069 \xive13_pri + assign $2\xive14_pri$next[7:0]$14070 \xive14_pri + assign $2\xive15_pri$next[7:0]$14071 \xive15_pri + assign $2\xive1_pri$next[7:0]$14072 \xive1_pri + assign $2\xive2_pri$next[7:0]$14073 \xive2_pri + assign $2\xive3_pri$next[7:0]$14074 \xive3_pri + assign $2\xive4_pri$next[7:0]$14075 \xive4_pri + assign $2\xive5_pri$next[7:0]$14076 \xive5_pri + assign $2\xive6_pri$next[7:0]$14077 \xive6_pri + assign $2\xive7_pri$next[7:0]$14078 \xive7_pri + assign $2\xive8_pri$next[7:0]$14079 \xive8_pri + assign $2\xive9_pri$next[7:0]$14080 \xive9_pri + end + case + assign $1\xive0_pri$next[7:0]$14049 \xive0_pri + assign $1\xive10_pri$next[7:0]$14050 \xive10_pri + assign $1\xive11_pri$next[7:0]$14051 \xive11_pri + assign $1\xive12_pri$next[7:0]$14052 \xive12_pri + assign $1\xive13_pri$next[7:0]$14053 \xive13_pri + assign $1\xive14_pri$next[7:0]$14054 \xive14_pri + assign $1\xive15_pri$next[7:0]$14055 \xive15_pri + assign $1\xive1_pri$next[7:0]$14056 \xive1_pri + assign $1\xive2_pri$next[7:0]$14057 \xive2_pri + assign $1\xive3_pri$next[7:0]$14058 \xive3_pri + assign $1\xive4_pri$next[7:0]$14059 \xive4_pri + assign $1\xive5_pri$next[7:0]$14060 \xive5_pri + assign $1\xive6_pri$next[7:0]$14061 \xive6_pri + assign $1\xive7_pri$next[7:0]$14062 \xive7_pri + assign $1\xive8_pri$next[7:0]$14063 \xive8_pri + assign $1\xive9_pri$next[7:0]$14064 \xive9_pri + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $4\xive0_pri$next[7:0]$14097 8'11111111 + assign $4\xive1_pri$next[7:0]$14104 8'11111111 + assign $4\xive2_pri$next[7:0]$14105 8'11111111 + assign $4\xive3_pri$next[7:0]$14106 8'11111111 + assign $4\xive4_pri$next[7:0]$14107 8'11111111 + assign $4\xive5_pri$next[7:0]$14108 8'11111111 + assign $4\xive6_pri$next[7:0]$14109 8'11111111 + assign $4\xive7_pri$next[7:0]$14110 8'11111111 + assign $4\xive8_pri$next[7:0]$14111 8'11111111 + assign $4\xive9_pri$next[7:0]$14112 8'11111111 + assign $4\xive10_pri$next[7:0]$14098 8'11111111 + assign $4\xive11_pri$next[7:0]$14099 8'11111111 + assign $4\xive12_pri$next[7:0]$14100 8'11111111 + assign $4\xive13_pri$next[7:0]$14101 8'11111111 + assign $4\xive14_pri$next[7:0]$14102 8'11111111 + assign $4\xive15_pri$next[7:0]$14103 8'11111111 + case + assign $4\xive0_pri$next[7:0]$14097 $1\xive0_pri$next[7:0]$14049 + assign $4\xive10_pri$next[7:0]$14098 $1\xive10_pri$next[7:0]$14050 + assign $4\xive11_pri$next[7:0]$14099 $1\xive11_pri$next[7:0]$14051 + assign $4\xive12_pri$next[7:0]$14100 $1\xive12_pri$next[7:0]$14052 + assign $4\xive13_pri$next[7:0]$14101 $1\xive13_pri$next[7:0]$14053 + assign $4\xive14_pri$next[7:0]$14102 $1\xive14_pri$next[7:0]$14054 + assign $4\xive15_pri$next[7:0]$14103 $1\xive15_pri$next[7:0]$14055 + assign $4\xive1_pri$next[7:0]$14104 $1\xive1_pri$next[7:0]$14056 + assign $4\xive2_pri$next[7:0]$14105 $1\xive2_pri$next[7:0]$14057 + assign $4\xive3_pri$next[7:0]$14106 $1\xive3_pri$next[7:0]$14058 + assign $4\xive4_pri$next[7:0]$14107 $1\xive4_pri$next[7:0]$14059 + assign $4\xive5_pri$next[7:0]$14108 $1\xive5_pri$next[7:0]$14060 + assign $4\xive6_pri$next[7:0]$14109 $1\xive6_pri$next[7:0]$14061 + assign $4\xive7_pri$next[7:0]$14110 $1\xive7_pri$next[7:0]$14062 + assign $4\xive8_pri$next[7:0]$14111 $1\xive8_pri$next[7:0]$14063 + assign $4\xive9_pri$next[7:0]$14112 $1\xive9_pri$next[7:0]$14064 + end + sync always + update \xive0_pri$next $0\xive0_pri$next[7:0]$14033 + update \xive10_pri$next $0\xive10_pri$next[7:0]$14034 + update \xive11_pri$next $0\xive11_pri$next[7:0]$14035 + update \xive12_pri$next $0\xive12_pri$next[7:0]$14036 + update \xive13_pri$next $0\xive13_pri$next[7:0]$14037 + update \xive14_pri$next $0\xive14_pri$next[7:0]$14038 + update \xive15_pri$next $0\xive15_pri$next[7:0]$14039 + update \xive1_pri$next $0\xive1_pri$next[7:0]$14040 + update \xive2_pri$next $0\xive2_pri$next[7:0]$14041 + update \xive3_pri$next $0\xive3_pri$next[7:0]$14042 + update \xive4_pri$next $0\xive4_pri$next[7:0]$14043 + update \xive5_pri$next $0\xive5_pri$next[7:0]$14044 + update \xive6_pri$next $0\xive6_pri$next[7:0]$14045 + update \xive7_pri$next $0\xive7_pri$next[7:0]$14046 + update \xive8_pri$next $0\xive8_pri$next[7:0]$14047 + update \xive9_pri$next $0\xive9_pri$next[7:0]$14048 + end + attribute \src "libresoc.v:184745.3-184754.6" + process $proc$libresoc.v:184745$14113 + assign { } { } + assign { } { } + assign $0\cur_pri0[7:0] $1\cur_pri0[7:0] + attribute \src "libresoc.v:184746.5-184746.29" + switch \initial + attribute \src "libresoc.v:184746.9-184746.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$77 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_pri0[7:0] \xive0_pri + case + assign $1\cur_pri0[7:0] \max_pri + end + sync always + update \cur_pri0 $0\cur_pri0[7:0] + end + attribute \src "libresoc.v:184755.3-184764.6" + process $proc$libresoc.v:184755$14114 + assign { } { } + assign { } { } + assign $0\cur_idx0[3:0] $1\cur_idx0[3:0] + attribute \src "libresoc.v:184756.5-184756.29" + switch \initial + attribute \src "libresoc.v:184756.9-184756.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$81 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_idx0[3:0] 4'0000 + case + assign $1\cur_idx0[3:0] \max_idx + end + sync always + update \cur_idx0 $0\cur_idx0[3:0] + end + attribute \src "libresoc.v:184765.3-184774.6" + process $proc$libresoc.v:184765$14115 + assign { } { } + assign { } { } + assign $0\cur_pri1[7:0] $1\cur_pri1[7:0] + attribute \src "libresoc.v:184766.5-184766.29" + switch \initial + attribute \src "libresoc.v:184766.9-184766.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$85 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_pri1[7:0] \xive1_pri + case + assign $1\cur_pri1[7:0] \cur_pri0 + end + sync always + update \cur_pri1 $0\cur_pri1[7:0] + end + attribute \src "libresoc.v:184775.3-184784.6" + process $proc$libresoc.v:184775$14116 + assign { } { } + assign { } { } + assign $0\cur_idx1[3:0] $1\cur_idx1[3:0] + attribute \src "libresoc.v:184776.5-184776.29" + switch \initial + attribute \src "libresoc.v:184776.9-184776.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$89 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_idx1[3:0] 4'0001 + case + assign $1\cur_idx1[3:0] \cur_idx0 + end + sync always + update \cur_idx1 $0\cur_idx1[3:0] + end + attribute \src "libresoc.v:184785.3-184794.6" + process $proc$libresoc.v:184785$14117 + assign { } { } + assign { } { } + assign $0\cur_pri2[7:0] $1\cur_pri2[7:0] + attribute \src "libresoc.v:184786.5-184786.29" + switch \initial + attribute \src "libresoc.v:184786.9-184786.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$93 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_pri2[7:0] \xive2_pri + case + assign $1\cur_pri2[7:0] \cur_pri1 + end + sync always + update \cur_pri2 $0\cur_pri2[7:0] + end + attribute \src "libresoc.v:184795.3-184804.6" + process $proc$libresoc.v:184795$14118 + assign { } { } + assign { } { } + assign $0\cur_idx2[3:0] $1\cur_idx2[3:0] + attribute \src "libresoc.v:184796.5-184796.29" + switch \initial + attribute \src "libresoc.v:184796.9-184796.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$97 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_idx2[3:0] 4'0010 + case + assign $1\cur_idx2[3:0] \cur_idx1 + end + sync always + update \cur_idx2 $0\cur_idx2[3:0] + end + attribute \src "libresoc.v:184805.3-184814.6" + process $proc$libresoc.v:184805$14119 + assign { } { } + assign { } { } + assign $0\cur_pri3[7:0] $1\cur_pri3[7:0] + attribute \src "libresoc.v:184806.5-184806.29" + switch \initial + attribute \src "libresoc.v:184806.9-184806.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$101 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_pri3[7:0] \xive3_pri + case + assign $1\cur_pri3[7:0] \cur_pri2 + end + sync always + update \cur_pri3 $0\cur_pri3[7:0] + end + attribute \src "libresoc.v:184815.3-184824.6" + process $proc$libresoc.v:184815$14120 + assign { } { } + assign { } { } + assign $0\cur_idx3[3:0] $1\cur_idx3[3:0] + attribute \src "libresoc.v:184816.5-184816.29" + switch \initial + attribute \src "libresoc.v:184816.9-184816.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$105 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_idx3[3:0] 4'0011 + case + assign $1\cur_idx3[3:0] \cur_idx2 + end + sync always + update \cur_idx3 $0\cur_idx3[3:0] + end + attribute \src "libresoc.v:184825.3-184834.6" + process $proc$libresoc.v:184825$14121 + assign { } { } + assign { } { } + assign $0\cur_pri4[7:0] $1\cur_pri4[7:0] + attribute \src "libresoc.v:184826.5-184826.29" + switch \initial + attribute \src "libresoc.v:184826.9-184826.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$109 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_pri4[7:0] \xive4_pri + case + assign $1\cur_pri4[7:0] \cur_pri3 + end + sync always + update \cur_pri4 $0\cur_pri4[7:0] + end + attribute \src "libresoc.v:184835.3-184843.6" + process $proc$libresoc.v:184835$14122 + assign { } { } + assign { } { } + assign $0\int_level_l$next[15:0]$14123 $1\int_level_l$next[15:0]$14124 + attribute \src "libresoc.v:184836.5-184836.29" + switch \initial + attribute \src "libresoc.v:184836.9-184836.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\int_level_l$next[15:0]$14124 16'0000000000000000 + case + assign $1\int_level_l$next[15:0]$14124 \int_level_i + end + sync always + update \int_level_l$next $0\int_level_l$next[15:0]$14123 + end + attribute \src "libresoc.v:184844.3-184853.6" + process $proc$libresoc.v:184844$14125 + assign { } { } + assign { } { } + assign $0\cur_idx4[3:0] $1\cur_idx4[3:0] + attribute \src "libresoc.v:184845.5-184845.29" + switch \initial + attribute \src "libresoc.v:184845.9-184845.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$113 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_idx4[3:0] 4'0100 + case + assign $1\cur_idx4[3:0] \cur_idx3 + end + sync always + update \cur_idx4 $0\cur_idx4[3:0] + end + attribute \src "libresoc.v:184854.3-184863.6" + process $proc$libresoc.v:184854$14126 + assign { } { } + assign { } { } + assign $0\cur_pri5[7:0] $1\cur_pri5[7:0] + attribute \src "libresoc.v:184855.5-184855.29" + switch \initial + attribute \src "libresoc.v:184855.9-184855.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$117 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_pri5[7:0] \xive5_pri + case + assign $1\cur_pri5[7:0] \cur_pri4 + end + sync always + update \cur_pri5 $0\cur_pri5[7:0] + end + attribute \src "libresoc.v:184864.3-184873.6" + process $proc$libresoc.v:184864$14127 + assign { } { } + assign { } { } + assign $0\cur_idx5[3:0] $1\cur_idx5[3:0] + attribute \src "libresoc.v:184865.5-184865.29" + switch \initial + attribute \src "libresoc.v:184865.9-184865.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$121 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_idx5[3:0] 4'0101 + case + assign $1\cur_idx5[3:0] \cur_idx4 + end + sync always + update \cur_idx5 $0\cur_idx5[3:0] + end + attribute \src "libresoc.v:184874.3-184883.6" + process $proc$libresoc.v:184874$14128 + assign { } { } + assign { } { } + assign $0\cur_pri6[7:0] $1\cur_pri6[7:0] + attribute \src "libresoc.v:184875.5-184875.29" + switch \initial + attribute \src "libresoc.v:184875.9-184875.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$125 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_pri6[7:0] \xive6_pri + case + assign $1\cur_pri6[7:0] \cur_pri5 + end + sync always + update \cur_pri6 $0\cur_pri6[7:0] + end + attribute \src "libresoc.v:184884.3-184893.6" + process $proc$libresoc.v:184884$14129 + assign { } { } + assign { } { } + assign $0\cur_idx6[3:0] $1\cur_idx6[3:0] + attribute \src "libresoc.v:184885.5-184885.29" + switch \initial + attribute \src "libresoc.v:184885.9-184885.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$129 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_idx6[3:0] 4'0110 + case + assign $1\cur_idx6[3:0] \cur_idx5 + end + sync always + update \cur_idx6 $0\cur_idx6[3:0] + end + attribute \src "libresoc.v:184894.3-184903.6" + process $proc$libresoc.v:184894$14130 + assign { } { } + assign { } { } + assign $0\cur_pri7[7:0] $1\cur_pri7[7:0] + attribute \src "libresoc.v:184895.5-184895.29" + switch \initial + attribute \src "libresoc.v:184895.9-184895.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$133 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_pri7[7:0] \xive7_pri + case + assign $1\cur_pri7[7:0] \cur_pri6 + end + sync always + update \cur_pri7 $0\cur_pri7[7:0] + end + attribute \src "libresoc.v:184904.3-184913.6" + process $proc$libresoc.v:184904$14131 + assign { } { } + assign { } { } + assign $0\cur_idx7[3:0] $1\cur_idx7[3:0] + attribute \src "libresoc.v:184905.5-184905.29" + switch \initial + attribute \src "libresoc.v:184905.9-184905.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$137 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_idx7[3:0] 4'0111 + case + assign $1\cur_idx7[3:0] \cur_idx6 + end + sync always + update \cur_idx7 $0\cur_idx7[3:0] + end + attribute \src "libresoc.v:184914.3-184923.6" + process $proc$libresoc.v:184914$14132 + assign { } { } + assign { } { } + assign $0\cur_pri8[7:0] $1\cur_pri8[7:0] + attribute \src "libresoc.v:184915.5-184915.29" + switch \initial + attribute \src "libresoc.v:184915.9-184915.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$141 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_pri8[7:0] \xive8_pri + case + assign $1\cur_pri8[7:0] \cur_pri7 + end + sync always + update \cur_pri8 $0\cur_pri8[7:0] + end + attribute \src "libresoc.v:184924.3-184933.6" + process $proc$libresoc.v:184924$14133 + assign { } { } + assign { } { } + assign $0\cur_idx8[3:0] $1\cur_idx8[3:0] + attribute \src "libresoc.v:184925.5-184925.29" + switch \initial + attribute \src "libresoc.v:184925.9-184925.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$145 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_idx8[3:0] 4'1000 + case + assign $1\cur_idx8[3:0] \cur_idx7 + end + sync always + update \cur_idx8 $0\cur_idx8[3:0] + end + attribute \src "libresoc.v:184934.3-184943.6" + process $proc$libresoc.v:184934$14134 + assign { } { } + assign { } { } + assign $0\cur_pri9[7:0] $1\cur_pri9[7:0] + attribute \src "libresoc.v:184935.5-184935.29" + switch \initial + attribute \src "libresoc.v:184935.9-184935.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$149 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_pri9[7:0] \xive9_pri + case + assign $1\cur_pri9[7:0] \cur_pri8 + end + sync always + update \cur_pri9 $0\cur_pri9[7:0] + end + attribute \src "libresoc.v:184944.3-184953.6" + process $proc$libresoc.v:184944$14135 + assign { } { } + assign { } { } + assign $0\cur_idx9[3:0] $1\cur_idx9[3:0] + attribute \src "libresoc.v:184945.5-184945.29" + switch \initial + attribute \src "libresoc.v:184945.9-184945.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$153 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_idx9[3:0] 4'1001 + case + assign $1\cur_idx9[3:0] \cur_idx8 + end + sync always + update \cur_idx9 $0\cur_idx9[3:0] + end + attribute \src "libresoc.v:184954.3-184963.6" + process $proc$libresoc.v:184954$14136 + assign { } { } + assign { } { } + assign $0\cur_pri10[7:0] $1\cur_pri10[7:0] + attribute \src "libresoc.v:184955.5-184955.29" + switch \initial + attribute \src "libresoc.v:184955.9-184955.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$157 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_pri10[7:0] \xive10_pri + case + assign $1\cur_pri10[7:0] \cur_pri9 + end + sync always + update \cur_pri10 $0\cur_pri10[7:0] + end + attribute \src "libresoc.v:184964.3-184973.6" + process $proc$libresoc.v:184964$14137 + assign { } { } + assign { } { } + assign $0\cur_idx10[3:0] $1\cur_idx10[3:0] + attribute \src "libresoc.v:184965.5-184965.29" + switch \initial + attribute \src "libresoc.v:184965.9-184965.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$161 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_idx10[3:0] 4'1010 + case + assign $1\cur_idx10[3:0] \cur_idx9 + end + sync always + update \cur_idx10 $0\cur_idx10[3:0] + end + attribute \src "libresoc.v:184974.3-184983.6" + process $proc$libresoc.v:184974$14138 + assign { } { } + assign { } { } + assign $0\cur_pri11[7:0] $1\cur_pri11[7:0] + attribute \src "libresoc.v:184975.5-184975.29" + switch \initial + attribute \src "libresoc.v:184975.9-184975.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$165 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_pri11[7:0] \xive11_pri + case + assign $1\cur_pri11[7:0] \cur_pri10 + end + sync always + update \cur_pri11 $0\cur_pri11[7:0] + end + attribute \src "libresoc.v:184984.3-184993.6" + process $proc$libresoc.v:184984$14139 + assign { } { } + assign { } { } + assign $0\cur_idx11[3:0] $1\cur_idx11[3:0] + attribute \src "libresoc.v:184985.5-184985.29" + switch \initial + attribute \src "libresoc.v:184985.9-184985.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$169 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_idx11[3:0] 4'1011 + case + assign $1\cur_idx11[3:0] \cur_idx10 + end + sync always + update \cur_idx11 $0\cur_idx11[3:0] + end + attribute \src "libresoc.v:184994.3-185003.6" + process $proc$libresoc.v:184994$14140 + assign { } { } + assign { } { } + assign $0\cur_pri12[7:0] $1\cur_pri12[7:0] + attribute \src "libresoc.v:184995.5-184995.29" + switch \initial + attribute \src "libresoc.v:184995.9-184995.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$173 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_pri12[7:0] \xive12_pri + case + assign $1\cur_pri12[7:0] \cur_pri11 + end + sync always + update \cur_pri12 $0\cur_pri12[7:0] + end + attribute \src "libresoc.v:185004.3-185013.6" + process $proc$libresoc.v:185004$14141 + assign { } { } + assign { } { } + assign $0\cur_idx12[3:0] $1\cur_idx12[3:0] + attribute \src "libresoc.v:185005.5-185005.29" + switch \initial + attribute \src "libresoc.v:185005.9-185005.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$177 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_idx12[3:0] 4'1100 + case + assign $1\cur_idx12[3:0] \cur_idx11 + end + sync always + update \cur_idx12 $0\cur_idx12[3:0] + end + attribute \src "libresoc.v:185014.3-185023.6" + process $proc$libresoc.v:185014$14142 + assign { } { } + assign { } { } + assign $0\cur_pri13[7:0] $1\cur_pri13[7:0] + attribute \src "libresoc.v:185015.5-185015.29" + switch \initial + attribute \src "libresoc.v:185015.9-185015.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$181 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_pri13[7:0] \xive13_pri + case + assign $1\cur_pri13[7:0] \cur_pri12 + end + sync always + update \cur_pri13 $0\cur_pri13[7:0] + end + attribute \src "libresoc.v:185024.3-185033.6" + process $proc$libresoc.v:185024$14143 + assign { } { } + assign { } { } + assign $0\cur_idx13[3:0] $1\cur_idx13[3:0] + attribute \src "libresoc.v:185025.5-185025.29" + switch \initial + attribute \src "libresoc.v:185025.9-185025.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$185 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_idx13[3:0] 4'1101 + case + assign $1\cur_idx13[3:0] \cur_idx12 + end + sync always + update \cur_idx13 $0\cur_idx13[3:0] + end + attribute \src "libresoc.v:185034.3-185043.6" + process $proc$libresoc.v:185034$14144 + assign { } { } + assign { } { } + assign $0\cur_pri14[7:0] $1\cur_pri14[7:0] + attribute \src "libresoc.v:185035.5-185035.29" + switch \initial + attribute \src "libresoc.v:185035.9-185035.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$189 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_pri14[7:0] \xive14_pri + case + assign $1\cur_pri14[7:0] \cur_pri13 + end + sync always + update \cur_pri14 $0\cur_pri14[7:0] + end + attribute \src "libresoc.v:185044.3-185093.6" + process $proc$libresoc.v:185044$14145 + assign { } { } + assign { } { } + assign $0\be_out[31:0] $1\be_out[31:0] + attribute \src "libresoc.v:185045.5-185045.29" + switch \initial + attribute \src "libresoc.v:185045.9-185045.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:312" + switch { \reg_is_debug \reg_is_config \reg_is_xive } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign { } { } + assign $1\be_out[31:0] $2\be_out[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + switch \reg_idx + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$7 } + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$11 } + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$15 } + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$19 } + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$23 } + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$27 } + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$31 } + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$35 } + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$39 } + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$43 } + attribute \src "libresoc.v:0.0-0.0" + case 4'1010 + assign { } { } + assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$47 } + attribute \src "libresoc.v:0.0-0.0" + case 4'1011 + assign { } { } + assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$51 } + attribute \src "libresoc.v:0.0-0.0" + case 4'1100 + assign { } { } + assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$55 } + attribute \src "libresoc.v:0.0-0.0" + case 4'1101 + assign { } { } + assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$59 } + attribute \src "libresoc.v:0.0-0.0" + case 4'1110 + assign { } { } + assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$63 } + attribute \src "libresoc.v:0.0-0.0" + case 4'---- + assign { } { } + assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$67 } + case + assign $2\be_out[31:0] 0 + end + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- + assign { } { } + assign $1\be_out[31:0] 134217744 + attribute \src "libresoc.v:0.0-0.0" + case 3'1-- + assign { } { } + assign $1\be_out[31:0] { \icp_r_src 20'00000000000000000000 \icp_r_pri } + case + assign $1\be_out[31:0] 0 + end + sync always + update \be_out $0\be_out[31:0] + end + attribute \src "libresoc.v:185094.3-185103.6" + process $proc$libresoc.v:185094$14146 + assign { } { } + assign { } { } + assign $0\cur_idx14[3:0] $1\cur_idx14[3:0] + attribute \src "libresoc.v:185095.5-185095.29" + switch \initial + attribute \src "libresoc.v:185095.9-185095.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$193 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_idx14[3:0] 4'1110 + case + assign $1\cur_idx14[3:0] \cur_idx13 + end + sync always + update \cur_idx14 $0\cur_idx14[3:0] + end + attribute \src "libresoc.v:185104.3-185113.6" + process $proc$libresoc.v:185104$14147 + assign { } { } + assign { } { } + assign $0\cur_pri15[7:0] $1\cur_pri15[7:0] + attribute \src "libresoc.v:185105.5-185105.29" + switch \initial + attribute \src "libresoc.v:185105.9-185105.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$197 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_pri15[7:0] \xive15_pri + case + assign $1\cur_pri15[7:0] \cur_pri14 + end + sync always + update \cur_pri15 $0\cur_pri15[7:0] + end + attribute \src "libresoc.v:185114.3-185123.6" + process $proc$libresoc.v:185114$14148 + assign { } { } + assign { } { } + assign $0\cur_idx15[3:0] $1\cur_idx15[3:0] + attribute \src "libresoc.v:185115.5-185115.29" + switch \initial + attribute \src "libresoc.v:185115.9-185115.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$201 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_idx15[3:0] 4'1111 + case + assign $1\cur_idx15[3:0] \cur_idx14 + end + sync always + update \cur_idx15 $0\cur_idx15[3:0] + end + attribute \src "libresoc.v:185124.3-185133.6" + process $proc$libresoc.v:185124$14149 + assign { } { } + assign { } { } + assign $0\ibit[0:0] $1\ibit[0:0] + attribute \src "libresoc.v:185125.5-185125.29" + switch \initial + attribute \src "libresoc.v:185125.9-185125.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:312" + switch { \reg_is_debug \reg_is_config \reg_is_xive } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign { } { } + assign $1\ibit[0:0] \$71 + case + assign $1\ibit[0:0] 1'0 + end + sync always + update \ibit $0\ibit[0:0] + end + attribute \src "libresoc.v:185134.3-185142.6" + process $proc$libresoc.v:185134$14150 + assign { } { } + assign { } { } + assign $0\ics_wb__dat_r$next[31:0]$14151 $1\ics_wb__dat_r$next[31:0]$14152 + attribute \src "libresoc.v:185135.5-185135.29" + switch \initial + attribute \src "libresoc.v:185135.9-185135.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ics_wb__dat_r$next[31:0]$14152 0 + case + assign $1\ics_wb__dat_r$next[31:0]$14152 { \be_out [7:0] \be_out [15:8] \be_out [23:16] \be_out [31:24] } + end + sync always + update \ics_wb__dat_r$next $0\ics_wb__dat_r$next[31:0]$14151 + end + attribute \src "libresoc.v:185143.3-185151.6" + process $proc$libresoc.v:185143$14153 + assign { } { } + assign { } { } + assign $0\ics_wb__ack$next[0:0]$14154 $1\ics_wb__ack$next[0:0]$14155 + attribute \src "libresoc.v:185144.5-185144.29" + switch \initial + attribute \src "libresoc.v:185144.9-185144.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ics_wb__ack$next[0:0]$14155 1'0 + case + assign $1\ics_wb__ack$next[0:0]$14155 \wb_valid + end + sync always + update \ics_wb__ack$next $0\ics_wb__ack$next[0:0]$14154 + end + connect \$7 $ternary$libresoc.v:184514$13908_Y + connect \$99 $lt$libresoc.v:184515$13909_Y + connect \$101 $and$libresoc.v:184516$13910_Y + connect \$103 $lt$libresoc.v:184517$13911_Y + connect \$105 $and$libresoc.v:184518$13912_Y + connect \$107 $lt$libresoc.v:184519$13913_Y + connect \$109 $and$libresoc.v:184520$13914_Y + connect \$111 $lt$libresoc.v:184521$13915_Y + connect \$113 $and$libresoc.v:184522$13916_Y + connect \$115 $lt$libresoc.v:184523$13917_Y + connect \$117 $and$libresoc.v:184524$13918_Y + connect \$119 $lt$libresoc.v:184525$13919_Y + connect \$121 $and$libresoc.v:184526$13920_Y + connect \$123 $lt$libresoc.v:184527$13921_Y + connect \$125 $and$libresoc.v:184528$13922_Y + connect \$127 $lt$libresoc.v:184529$13923_Y + connect \$12 $eq$libresoc.v:184530$13924_Y + connect \$129 $and$libresoc.v:184531$13925_Y + connect \$131 $lt$libresoc.v:184532$13926_Y + connect \$133 $and$libresoc.v:184533$13927_Y + connect \$135 $lt$libresoc.v:184534$13928_Y + connect \$137 $and$libresoc.v:184535$13929_Y + connect \$11 $ternary$libresoc.v:184536$13930_Y + connect \$139 $lt$libresoc.v:184537$13931_Y + connect \$141 $and$libresoc.v:184538$13932_Y + connect \$143 $lt$libresoc.v:184539$13933_Y + connect \$145 $and$libresoc.v:184540$13934_Y + connect \$147 $lt$libresoc.v:184541$13935_Y + connect \$149 $and$libresoc.v:184542$13936_Y + connect \$151 $lt$libresoc.v:184543$13937_Y + connect \$153 $and$libresoc.v:184544$13938_Y + connect \$155 $lt$libresoc.v:184545$13939_Y + connect \$157 $and$libresoc.v:184546$13940_Y + connect \$159 $lt$libresoc.v:184547$13941_Y + connect \$161 $and$libresoc.v:184548$13942_Y + connect \$163 $lt$libresoc.v:184549$13943_Y + connect \$165 $and$libresoc.v:184550$13944_Y + connect \$167 $lt$libresoc.v:184551$13945_Y + connect \$16 $eq$libresoc.v:184552$13946_Y + connect \$169 $and$libresoc.v:184553$13947_Y + connect \$171 $lt$libresoc.v:184554$13948_Y + connect \$173 $and$libresoc.v:184555$13949_Y + connect \$175 $lt$libresoc.v:184556$13950_Y + connect \$177 $and$libresoc.v:184557$13951_Y + connect \$15 $ternary$libresoc.v:184558$13952_Y + connect \$179 $lt$libresoc.v:184559$13953_Y + connect \$181 $and$libresoc.v:184560$13954_Y + connect \$183 $lt$libresoc.v:184561$13955_Y + connect \$185 $and$libresoc.v:184562$13956_Y + connect \$187 $lt$libresoc.v:184563$13957_Y + connect \$189 $and$libresoc.v:184564$13958_Y + connect \$191 $lt$libresoc.v:184565$13959_Y + connect \$193 $and$libresoc.v:184566$13960_Y + connect \$195 $lt$libresoc.v:184567$13961_Y + connect \$197 $and$libresoc.v:184568$13962_Y + connect \$1 $eq$libresoc.v:184569$13963_Y + connect \$199 $lt$libresoc.v:184570$13964_Y + connect \$201 $and$libresoc.v:184571$13965_Y + connect \$204 $eq$libresoc.v:184572$13966_Y + connect \$203 $ternary$libresoc.v:184573$13967_Y + connect \$20 $eq$libresoc.v:184574$13968_Y + connect \$19 $ternary$libresoc.v:184575$13969_Y + connect \$24 $eq$libresoc.v:184576$13970_Y + connect \$23 $ternary$libresoc.v:184577$13971_Y + connect \$28 $eq$libresoc.v:184578$13972_Y + connect \$27 $ternary$libresoc.v:184579$13973_Y + connect \$32 $eq$libresoc.v:184580$13974_Y + connect \$31 $ternary$libresoc.v:184581$13975_Y + connect \$36 $eq$libresoc.v:184582$13976_Y + connect \$35 $ternary$libresoc.v:184583$13977_Y + connect \$3 $eq$libresoc.v:184584$13978_Y + connect \$40 $eq$libresoc.v:184585$13979_Y + connect \$39 $ternary$libresoc.v:184586$13980_Y + connect \$44 $eq$libresoc.v:184587$13981_Y + connect \$43 $ternary$libresoc.v:184588$13982_Y + connect \$48 $eq$libresoc.v:184589$13983_Y + connect \$47 $ternary$libresoc.v:184590$13984_Y + connect \$52 $eq$libresoc.v:184591$13985_Y + connect \$51 $ternary$libresoc.v:184592$13986_Y + connect \$56 $eq$libresoc.v:184593$13987_Y + connect \$55 $ternary$libresoc.v:184594$13988_Y + connect \$5 $and$libresoc.v:184595$13989_Y + connect \$60 $eq$libresoc.v:184596$13990_Y + connect \$59 $ternary$libresoc.v:184597$13991_Y + connect \$64 $eq$libresoc.v:184598$13992_Y + connect \$63 $ternary$libresoc.v:184599$13993_Y + connect \$68 $eq$libresoc.v:184600$13994_Y + connect \$67 $ternary$libresoc.v:184601$13995_Y + connect \$71 $shr$libresoc.v:184602$13996_Y [0] + connect \$73 $and$libresoc.v:184603$13997_Y + connect \$75 $lt$libresoc.v:184604$13998_Y + connect \$77 $and$libresoc.v:184605$13999_Y + connect \$79 $lt$libresoc.v:184606$14000_Y + connect \$81 $and$libresoc.v:184607$14001_Y + connect \$83 $lt$libresoc.v:184608$14002_Y + connect \$85 $and$libresoc.v:184609$14003_Y + connect \$87 $lt$libresoc.v:184610$14004_Y + connect \$8 $eq$libresoc.v:184611$14005_Y + connect \$89 $and$libresoc.v:184612$14006_Y + connect \$91 $lt$libresoc.v:184613$14007_Y + connect \$93 $and$libresoc.v:184614$14008_Y + connect \$95 $lt$libresoc.v:184615$14009_Y + connect \$97 $and$libresoc.v:184616$14010_Y + connect \icp_r_pri \$203 + connect \icp_r_src \cur_idx15 + connect \max_idx 4'0000 + connect \max_pri 8'11111111 + connect { \icp_o_pri$next \icp_o_src$next } { \icp_r_pri \icp_r_src } + connect \be_in { \ics_wb__dat_w [7:0] \ics_wb__dat_w [15:8] \ics_wb__dat_w [23:16] \ics_wb__dat_w [31:24] } + connect \wb_valid \$5 + connect \reg_idx \ics_wb__adr [3:0] + connect \reg_is_debug \$3 + connect \reg_is_config \$1 + connect \reg_is_xive \ics_wb__adr [9] +end